Lines Matching refs:clk_phase
130 u32 clk_phase[2]; in socfpga_clk_prepare() local
132 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { in socfpga_clk_prepare()
140 switch (socfpgaclk->clk_phase[i]) { in socfpga_clk_prepare()
142 clk_phase[i] = 0; in socfpga_clk_prepare()
145 clk_phase[i] = 1; in socfpga_clk_prepare()
148 clk_phase[i] = 2; in socfpga_clk_prepare()
151 clk_phase[i] = 3; in socfpga_clk_prepare()
154 clk_phase[i] = 4; in socfpga_clk_prepare()
157 clk_phase[i] = 5; in socfpga_clk_prepare()
160 clk_phase[i] = 6; in socfpga_clk_prepare()
163 clk_phase[i] = 7; in socfpga_clk_prepare()
166 clk_phase[i] = 0; in socfpga_clk_prepare()
170 hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]); in socfpga_clk_prepare()
189 u32 clk_phase[2]; in __socfpga_gate_init() local
230 rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2); in __socfpga_gate_init()
232 socfpga_clk->clk_phase[0] = clk_phase[0]; in __socfpga_gate_init()
233 socfpga_clk->clk_phase[1] = clk_phase[1]; in __socfpga_gate_init()