Lines Matching refs:GATE
160 GATE(SCLK_HSMMC_EXT, "sclk_hsmmcext", "ext", SCLKCON, 13, 0, 0),
161 GATE(SCLK_HSMMC1, "sclk_hsmmc1", "div_hsmmc1", SCLKCON, 12, 0, 0),
162 GATE(SCLK_FIMD, "sclk_fimd", "div_fimd", SCLKCON, 10, 0, 0),
163 GATE(SCLK_I2S0, "sclk_i2s0", "mux_i2s0", SCLKCON, 9, 0, 0),
164 GATE(SCLK_UART, "sclk_uart", "div_uart", SCLKCON, 8, 0, 0),
165 GATE(SCLK_USBH, "sclk_usbhost", "div_usbhost", SCLKCON, 1, 0, 0),
166 GATE(HCLK_DRAM, "dram", "hclk", HCLKCON, 19, CLK_IGNORE_UNUSED, 0),
167 GATE(HCLK_SSMC, "ssmc", "hclk", HCLKCON, 18, CLK_IGNORE_UNUSED, 0),
168 GATE(HCLK_HSMMC1, "hsmmc1", "hclk", HCLKCON, 16, 0, 0),
169 GATE(HCLK_USBD, "usb-device", "hclk", HCLKCON, 12, 0, 0),
170 GATE(HCLK_USBH, "usb-host", "hclk", HCLKCON, 11, 0, 0),
171 GATE(HCLK_LCD, "lcd", "hclk", HCLKCON, 9, 0, 0),
172 GATE(HCLK_DMA5, "dma5", "hclk", HCLKCON, 5, CLK_IGNORE_UNUSED, 0),
173 GATE(HCLK_DMA4, "dma4", "hclk", HCLKCON, 4, CLK_IGNORE_UNUSED, 0),
174 GATE(HCLK_DMA3, "dma3", "hclk", HCLKCON, 3, CLK_IGNORE_UNUSED, 0),
175 GATE(HCLK_DMA2, "dma2", "hclk", HCLKCON, 2, CLK_IGNORE_UNUSED, 0),
176 GATE(HCLK_DMA1, "dma1", "hclk", HCLKCON, 1, CLK_IGNORE_UNUSED, 0),
177 GATE(HCLK_DMA0, "dma0", "hclk", HCLKCON, 0, CLK_IGNORE_UNUSED, 0),
178 GATE(PCLK_GPIO, "gpio", "pclk", PCLKCON, 13, CLK_IGNORE_UNUSED, 0),
179 GATE(PCLK_RTC, "rtc", "pclk", PCLKCON, 12, 0, 0),
180 GATE(PCLK_WDT, "wdt", "pclk", PCLKCON, 11, 0, 0),
181 GATE(PCLK_PWM, "pwm", "pclk", PCLKCON, 10, 0, 0),
182 GATE(PCLK_I2S0, "i2s0", "pclk", PCLKCON, 9, 0, 0),
183 GATE(PCLK_AC97, "ac97", "pclk", PCLKCON, 8, 0, 0),
184 GATE(PCLK_ADC, "adc", "pclk", PCLKCON, 7, 0, 0),
185 GATE(PCLK_SPI0, "spi0", "pclk", PCLKCON, 6, 0, 0),
186 GATE(PCLK_I2C0, "i2c0", "pclk", PCLKCON, 4, 0, 0),
187 GATE(PCLK_UART3, "uart3", "pclk", PCLKCON, 3, 0, 0),
188 GATE(PCLK_UART2, "uart2", "pclk", PCLKCON, 2, 0, 0),
189 GATE(PCLK_UART1, "uart1", "pclk", PCLKCON, 1, 0, 0),
190 GATE(PCLK_UART0, "uart0", "pclk", PCLKCON, 0, 0, 0),
259 GATE(0, "hsspi0_mpll", "div_hsspi0_mpll", SCLKCON, 19, 0, 0),
260 GATE(0, "hsspi0_epll", "div_hsspi0_epll", SCLKCON, 14, 0, 0),
261 GATE(0, "sclk_hsmmc0", "div_hsmmc0", SCLKCON, 6, 0, 0),
262 GATE(HCLK_2D, "2d", "hclk", HCLKCON, 20, 0, 0),
263 GATE(HCLK_HSMMC0, "hsmmc0", "hclk", HCLKCON, 15, 0, 0),
264 GATE(HCLK_IROM, "irom", "hclk", HCLKCON, 13, CLK_IGNORE_UNUSED, 0),
265 GATE(PCLK_PCM, "pcm", "pclk", PCLKCON, 19, 0, 0),
304 GATE(SCLK_HSSPI0, "sclk_hsspi0", "div_hsspi0_epll", SCLKCON, 14, 0, 0),
305 GATE(SCLK_CAM, "sclk_cam", "div_cam", SCLKCON, 11, 0, 0),
306 GATE(HCLK_CFC, "cfc", "hclk", HCLKCON, 17, CLK_IGNORE_UNUSED, 0),
307 GATE(HCLK_CAM, "cam", "hclk", HCLKCON, 8, 0, 0),
308 GATE(PCLK_SPI1, "spi1", "pclk", PCLKCON, 15, 0, 0),
309 GATE(PCLK_SDI, "sdi", "pclk", PCLKCON, 5, 0, 0),
342 GATE(SCLK_I2S1, "sclk_i2s1", "div_i2s1", SCLKCON, 5, 0, 0),
343 GATE(HCLK_CFC, "cfc", "hclk", HCLKCON, 17, 0, 0),
344 GATE(HCLK_CAM, "cam", "hclk", HCLKCON, 8, 0, 0),
345 GATE(HCLK_DMA7, "dma7", "hclk", HCLKCON, 7, CLK_IGNORE_UNUSED, 0),
346 GATE(HCLK_DMA6, "dma6", "hclk", HCLKCON, 6, CLK_IGNORE_UNUSED, 0),
347 GATE(PCLK_I2S1, "i2s1", "pclk", PCLKCON, 17, 0, 0),
348 GATE(PCLK_I2C1, "i2c1", "pclk", PCLKCON, 16, 0, 0),
349 GATE(PCLK_SPI1, "spi1", "pclk", PCLKCON, 14, 0, 0),