Lines Matching refs:C
694 #define C(x) PERF_COUNT_HW_CACHE_##x macro
701 static int power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
702 [ C(L1D) ] = {
703 [ C(OP_READ) ] = {
704 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
705 [ C(RESULT_MISS) ] = PM_LD_MISS_L1,
707 [ C(OP_WRITE) ] = {
708 [ C(RESULT_ACCESS) ] = 0,
709 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
711 [ C(OP_PREFETCH) ] = {
712 [ C(RESULT_ACCESS) ] = PM_L1_PREF,
713 [ C(RESULT_MISS) ] = 0,
716 [ C(L1I) ] = {
717 [ C(OP_READ) ] = {
718 [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
719 [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS,
721 [ C(OP_WRITE) ] = {
722 [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
723 [ C(RESULT_MISS) ] = -1,
725 [ C(OP_PREFETCH) ] = {
726 [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
727 [ C(RESULT_MISS) ] = 0,
730 [ C(LL) ] = {
731 [ C(OP_READ) ] = {
732 [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
733 [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS,
735 [ C(OP_WRITE) ] = {
736 [ C(RESULT_ACCESS) ] = PM_L2_ST,
737 [ C(RESULT_MISS) ] = PM_L2_ST_MISS,
739 [ C(OP_PREFETCH) ] = {
740 [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
741 [ C(RESULT_MISS) ] = 0,
744 [ C(DTLB) ] = {
745 [ C(OP_READ) ] = {
746 [ C(RESULT_ACCESS) ] = 0,
747 [ C(RESULT_MISS) ] = PM_DTLB_MISS,
749 [ C(OP_WRITE) ] = {
750 [ C(RESULT_ACCESS) ] = -1,
751 [ C(RESULT_MISS) ] = -1,
753 [ C(OP_PREFETCH) ] = {
754 [ C(RESULT_ACCESS) ] = -1,
755 [ C(RESULT_MISS) ] = -1,
758 [ C(ITLB) ] = {
759 [ C(OP_READ) ] = {
760 [ C(RESULT_ACCESS) ] = 0,
761 [ C(RESULT_MISS) ] = PM_ITLB_MISS,
763 [ C(OP_WRITE) ] = {
764 [ C(RESULT_ACCESS) ] = -1,
765 [ C(RESULT_MISS) ] = -1,
767 [ C(OP_PREFETCH) ] = {
768 [ C(RESULT_ACCESS) ] = -1,
769 [ C(RESULT_MISS) ] = -1,
772 [ C(BPU) ] = {
773 [ C(OP_READ) ] = {
774 [ C(RESULT_ACCESS) ] = PM_BRU_FIN,
775 [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL,
777 [ C(OP_WRITE) ] = {
778 [ C(RESULT_ACCESS) ] = -1,
779 [ C(RESULT_MISS) ] = -1,
781 [ C(OP_PREFETCH) ] = {
782 [ C(RESULT_ACCESS) ] = -1,
783 [ C(RESULT_MISS) ] = -1,
786 [ C(NODE) ] = {
787 [ C(OP_READ) ] = {
788 [ C(RESULT_ACCESS) ] = -1,
789 [ C(RESULT_MISS) ] = -1,
791 [ C(OP_WRITE) ] = {
792 [ C(RESULT_ACCESS) ] = -1,
793 [ C(RESULT_MISS) ] = -1,
795 [ C(OP_PREFETCH) ] = {
796 [ C(RESULT_ACCESS) ] = -1,
797 [ C(RESULT_MISS) ] = -1,
802 #undef C