Lines Matching refs:xcp
785 static inline int cop1_64bit(struct pt_regs *xcp) in cop1_64bit() argument
803 if (cop1_64bit(xcp) && !hybrid_fprs()) \
811 if (cop1_64bit(xcp) && !hybrid_fprs()) { \
832 ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
837 fpr = (x) & ~(cop1_64bit(xcp) == 0); \
851 static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx, in cop1_cfc() argument
861 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
871 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
879 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
890 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_cfc()
902 xcp->regs[MIPSInst_RT(ir)] = value; in cop1_cfc()
908 static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx, in cop1_ctc() argument
918 value = xcp->regs[MIPSInst_RT(ir)]; in cop1_ctc()
923 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_ctc()
934 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_ctc()
945 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_ctc()
954 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value); in cop1_ctc()
974 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, in cop1Emulate() argument
977 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc; in cop1Emulate()
995 if (delay_slot(xcp)) { in cop1Emulate()
997 if (!mm_isBranchInstr(xcp, dec_insn, &contpc)) in cop1Emulate()
998 clear_delay_slot(xcp); in cop1Emulate()
1000 if (!isBranchInstr(xcp, dec_insn, &contpc)) in cop1Emulate()
1001 clear_delay_slot(xcp); in cop1Emulate()
1005 if (delay_slot(xcp)) { in cop1Emulate()
1048 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0); in cop1Emulate()
1052 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()
1070 dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()
1087 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()
1104 wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()
1128 DIFROMREG(xcp->regs[MIPSInst_RT(ir)], in cop1Emulate()
1138 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); in cop1Emulate()
1147 SIFROMHREG(xcp->regs[MIPSInst_RT(ir)], in cop1Emulate()
1157 SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); in cop1Emulate()
1163 SIFROMREG(xcp->regs[MIPSInst_RT(ir)], in cop1Emulate()
1170 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); in cop1Emulate()
1175 cop1_cfc(xcp, ctx, ir); in cop1Emulate()
1180 cop1_ctc(xcp, ctx, ir); in cop1Emulate()
1188 if (!cpu_has_mips_r6 || delay_slot(xcp)) in cop1Emulate()
1205 if (delay_slot(xcp)) in cop1Emulate()
1231 set_delay_slot(xcp); in cop1Emulate()
1243 bcpc = xcp->cp0_epc; in cop1Emulate()
1244 xcp->cp0_epc += dec_insn.pc_inc; in cop1Emulate()
1249 contpc = (xcp->cp0_epc + (contpc << 1)); in cop1Emulate()
1269 sig = mips_dsemul(xcp, ir, in cop1Emulate()
1272 xcp->cp0_epc = bcpc; in cop1Emulate()
1280 contpc = (xcp->cp0_epc + (contpc << 2)); in cop1Emulate()
1315 xcp->cp0_epc = bcpc; in cop1Emulate()
1323 sig = mips_dsemul(xcp, ir, contpc); in cop1Emulate()
1325 xcp->cp0_epc = bcpc; in cop1Emulate()
1333 xcp->cp0_epc += dec_insn.pc_inc; in cop1Emulate()
1347 if ((sig = fpu_emu(xcp, ctx, ir))) in cop1Emulate()
1356 sig = fpux_emu(xcp, ctx, ir, fault_addr); in cop1Emulate()
1369 xcp->regs[MIPSInst_RD(ir)] = in cop1Emulate()
1370 xcp->regs[MIPSInst_RS(ir)]; in cop1Emulate()
1378 xcp->cp0_epc = contpc; in cop1Emulate()
1379 clear_delay_slot(xcp); in cop1Emulate()
1449 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, in fpux_emu() argument
1466 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + in fpux_emu()
1467 xcp->regs[MIPSInst_FT(ir)]); in fpux_emu()
1484 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + in fpux_emu()
1485 xcp->regs[MIPSInst_FT(ir)]); in fpux_emu()
1563 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + in fpux_emu()
1564 xcp->regs[MIPSInst_FT(ir)]); in fpux_emu()
1581 va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + in fpux_emu()
1582 xcp->regs[MIPSInst_FT(ir)]); in fpux_emu()
1644 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, in fpu_emu() argument
1726 if (xcp->regs[MIPSInst_FT(ir)] != 0) in fpu_emu()
1735 if (xcp->regs[MIPSInst_FT(ir)] == 0) in fpu_emu()
1925 if (xcp->regs[MIPSInst_FT(ir)] != 0) in fpu_emu()
1933 if (xcp->regs[MIPSInst_FT(ir)] == 0) in fpu_emu()
2143 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, in fpu_emulator_cop1Handler() argument
2152 oldepc = xcp->cp0_epc; in fpu_emulator_cop1Handler()
2154 prevepc = xcp->cp0_epc; in fpu_emulator_cop1Handler()
2161 if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) || in fpu_emulator_cop1Handler()
2162 (get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) || in fpu_emulator_cop1Handler()
2163 (get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) || in fpu_emulator_cop1Handler()
2164 (get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) { in fpu_emulator_cop1Handler()
2201 (mips_instruction __user *) xcp->cp0_epc)) || in fpu_emulator_cop1Handler()
2203 (mips_instruction __user *)(xcp->cp0_epc+4)))) { in fpu_emulator_cop1Handler()
2215 xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */ in fpu_emulator_cop1Handler()
2221 sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr); in fpu_emulator_cop1Handler()
2230 } while (xcp->cp0_epc > prevepc); in fpu_emulator_cop1Handler()
2233 if (sig == SIGILL && xcp->cp0_epc != oldepc) in fpu_emulator_cop1Handler()