Lines Matching refs:i_format
444 switch (insn.i_format.opcode) { in isBranchInstr()
463 switch (insn.i_format.rt) { in isBranchInstr()
466 if (NO_R6EMU && (insn.i_format.rs || in isBranchInstr()
467 insn.i_format.rt == bltzall_op)) in isBranchInstr()
478 if ((long)regs->regs[insn.i_format.rs] < 0) in isBranchInstr()
481 (insn.i_format.simmediate << 2); in isBranchInstr()
489 if (NO_R6EMU && (insn.i_format.rs || in isBranchInstr()
490 insn.i_format.rt == bgezall_op)) in isBranchInstr()
501 if ((long)regs->regs[insn.i_format.rs] >= 0) in isBranchInstr()
504 (insn.i_format.simmediate << 2); in isBranchInstr()
531 if (regs->regs[insn.i_format.rs] == in isBranchInstr()
532 regs->regs[insn.i_format.rt]) in isBranchInstr()
535 (insn.i_format.simmediate << 2); in isBranchInstr()
545 if (regs->regs[insn.i_format.rs] != in isBranchInstr()
546 regs->regs[insn.i_format.rt]) in isBranchInstr()
549 (insn.i_format.simmediate << 2); in isBranchInstr()
572 if (cpu_has_mips_r6 && insn.i_format.rt) { in isBranchInstr()
573 if ((insn.i_format.opcode == blez_op) && in isBranchInstr()
574 ((!insn.i_format.rs && insn.i_format.rt) || in isBranchInstr()
575 (insn.i_format.rs == insn.i_format.rt))) in isBranchInstr()
583 if ((long)regs->regs[insn.i_format.rs] <= 0) in isBranchInstr()
586 (insn.i_format.simmediate << 2); in isBranchInstr()
609 if (cpu_has_mips_r6 && insn.i_format.rt) { in isBranchInstr()
610 if ((insn.i_format.opcode == blez_op) && in isBranchInstr()
611 ((!insn.i_format.rs && insn.i_format.rt) || in isBranchInstr()
612 (insn.i_format.rs == insn.i_format.rt))) in isBranchInstr()
621 if ((long)regs->regs[insn.i_format.rs] > 0) in isBranchInstr()
624 (insn.i_format.simmediate << 2); in isBranchInstr()
634 if (insn.i_format.rt && !insn.i_format.rs) in isBranchInstr()
642 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0) in isBranchInstr()
643 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); in isBranchInstr()
648 if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0) in isBranchInstr()
649 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); in isBranchInstr()
654 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) in isBranchInstr()
655 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); in isBranchInstr()
660 if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) in isBranchInstr()
661 *contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2); in isBranchInstr()
696 if (!insn.i_format.rs) in isBranchInstr()
707 ((insn.i_format.rs == bc1eqz_op) || in isBranchInstr()
708 (insn.i_format.rs == bc1nez_op))) { in isBranchInstr()
710 switch (insn.i_format.rs) { in isBranchInstr()
712 if (get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1) in isBranchInstr()
716 if (!(get_fpr32(¤t->thread.fpu.fpr[insn.i_format.rt], 0) & 0x1)) in isBranchInstr()
723 (insn.i_format.simmediate << 2); in isBranchInstr()
734 if (insn.i_format.rs == bc_op) { in isBranchInstr()
742 bit = (insn.i_format.rt >> 2); in isBranchInstr()
745 switch (insn.i_format.rt & 3) { in isBranchInstr()
751 (insn.i_format.simmediate << 2); in isBranchInstr()
762 (insn.i_format.simmediate << 2); in isBranchInstr()