976 enum emulation_result kvm_mips_emulate_CP0(uint32_t inst, uint32_t *opc,  in kvm_mips_emulate_CP0()  argument
995 	copz = (inst >> 21) & 0x1f;  in kvm_mips_emulate_CP0()
996 	rt = (inst >> 16) & 0x1f;  in kvm_mips_emulate_CP0()
997 	rd = (inst >> 11) & 0x1f;  in kvm_mips_emulate_CP0()
998 	sel = inst & 0x7;  in kvm_mips_emulate_CP0()
999 	co_bit = (inst >> 25) & 1;  in kvm_mips_emulate_CP0()
1002 		op = (inst) & 0xff;  in kvm_mips_emulate_CP0()
1040 				kvm_mips_trans_mfc0(inst, opc, vcpu);  in kvm_mips_emulate_CP0()
1046 				kvm_mips_trans_mfc0(inst, opc, vcpu);  in kvm_mips_emulate_CP0()
1182 					kvm_mips_trans_mtc0(inst, opc, vcpu);  in kvm_mips_emulate_CP0()
1239 				kvm_mips_trans_mtc0(inst, opc, vcpu);  in kvm_mips_emulate_CP0()
1262 			if (inst & 0x20) {  in kvm_mips_emulate_CP0()
1316 enum emulation_result kvm_mips_emulate_store(uint32_t inst, uint32_t cause,  in kvm_mips_emulate_store()  argument
1335 	rt = (inst >> 16) & 0x1f;  in kvm_mips_emulate_store()
1336 	base = (inst >> 21) & 0x1f;  in kvm_mips_emulate_store()
1337 	offset = inst & 0xffff;  in kvm_mips_emulate_store()
1338 	op = (inst >> 26) & 0x3f;  in kvm_mips_emulate_store()
1428 enum emulation_result kvm_mips_emulate_load(uint32_t inst, uint32_t cause,  in kvm_mips_emulate_load()  argument
1436 	rt = (inst >> 16) & 0x1f;  in kvm_mips_emulate_load()
1437 	base = (inst >> 21) & 0x1f;  in kvm_mips_emulate_load()
1438 	offset = inst & 0xffff;  in kvm_mips_emulate_load()
1439 	op = (inst >> 26) & 0x3f;  in kvm_mips_emulate_load()
1572 enum emulation_result kvm_mips_emulate_cache(uint32_t inst, uint32_t *opc,  in kvm_mips_emulate_cache()  argument
1593 	base = (inst >> 21) & 0x1f;  in kvm_mips_emulate_cache()
1594 	op_inst = (inst >> 16) & 0x1f;  in kvm_mips_emulate_cache()
1595 	offset = (int16_t)inst;  in kvm_mips_emulate_cache()
1596 	cache = (inst >> 16) & 0x3;  in kvm_mips_emulate_cache()
1597 	op = (inst >> 18) & 0x7;  in kvm_mips_emulate_cache()
1625 		kvm_mips_trans_cache_index(inst, opc, vcpu);  in kvm_mips_emulate_cache()
1699 		kvm_mips_trans_cache_va(inst, opc, vcpu);  in kvm_mips_emulate_cache()
1707 		kvm_mips_trans_cache_va(inst, opc, vcpu);  in kvm_mips_emulate_cache()
1731 	uint32_t inst;  in kvm_mips_emulate_inst()  local
1737 	inst = kvm_get_inst(opc, vcpu);  in kvm_mips_emulate_inst()
1739 	switch (((union mips_instruction)inst).r_format.opcode) {  in kvm_mips_emulate_inst()
1741 		er = kvm_mips_emulate_CP0(inst, opc, cause, run, vcpu);  in kvm_mips_emulate_inst()
1746 		er = kvm_mips_emulate_store(inst, cause, run, vcpu);  in kvm_mips_emulate_inst()
1753 		er = kvm_mips_emulate_load(inst, cause, run, vcpu);  in kvm_mips_emulate_inst()
1759 		er = kvm_mips_emulate_cache(inst, opc, cause, run, vcpu);  in kvm_mips_emulate_inst()
1764 			inst);  in kvm_mips_emulate_inst()
2321 	uint32_t inst;  in kvm_mips_handle_ri()  local
2336 	inst = kvm_get_inst(opc, vcpu);  in kvm_mips_handle_ri()
2338 	if (inst == KVM_INVALID_INST) {  in kvm_mips_handle_ri()
2343 	if ((inst & OPCODE) == SPEC3 && (inst & FUNC) == RDHWR) {  in kvm_mips_handle_ri()
2345 		int rd = (inst & RD) >> 11;  in kvm_mips_handle_ri()
2346 		int rt = (inst & RT) >> 16;  in kvm_mips_handle_ri()
2383 		kvm_debug("Emulate RI not supported @ %p: %#x\n", opc, inst);  in kvm_mips_handle_ri()