513 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)  in simulate_ll()  argument
524 	offset = opcode & OFFSET;  in simulate_ll()
529 		((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);  in simulate_ll()
547 	regs->regs[(opcode & RT) >> 16] = value;  in simulate_ll()
552 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)  in simulate_sc()  argument
564 	offset = opcode & OFFSET;  in simulate_sc()
569 		((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);  in simulate_sc()
570 	reg = (opcode & RT) >> 16;  in simulate_sc()
600 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)  in simulate_llsc()  argument
602 	if ((opcode & OPCODE) == LL) {  in simulate_llsc()
605 		return simulate_ll(regs, opcode);  in simulate_llsc()
607 	if ((opcode & OPCODE) == SC) {  in simulate_llsc()
610 		return simulate_sc(regs, opcode);  in simulate_llsc()
655 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)  in simulate_rdhwr_normal()  argument
657 	if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {  in simulate_rdhwr_normal()
658 		int rd = (opcode & RD) >> 11;  in simulate_rdhwr_normal()
659 		int rt = (opcode & RT) >> 16;  in simulate_rdhwr_normal()
669 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode)  in simulate_rdhwr_mm()  argument
671 	if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {  in simulate_rdhwr_mm()
672 		int rd = (opcode & MM_RS) >> 16;  in simulate_rdhwr_mm()
673 		int rt = (opcode & MM_RT) >> 21;  in simulate_rdhwr_mm()
682 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)  in simulate_sync()  argument
684 	if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {  in simulate_sync()
766 static int simulate_fp(struct pt_regs *regs, unsigned int opcode,  in simulate_fp()  argument
769 	union mips_instruction inst = { .word = opcode };  in simulate_fp()
775 	switch (inst.i_format.opcode) {  in simulate_fp()
940 	unsigned int opcode, bcode;  in do_bp()  local
965 			opcode = (instr[0] << 16) | instr[1];  in do_bp()
966 			bcode = (opcode >> 6) & ((1 << 20) - 1);  in do_bp()
969 		if (__get_user(opcode, (unsigned int __user *)epc))  in do_bp()
971 		bcode = (opcode >> 6) & ((1 << 20) - 1);  in do_bp()
1018 	u32 opcode, tcode = 0;  in do_tr()  local
1033 		opcode = (instr[0] << 16) | instr[1];  in do_tr()
1035 		if (!(opcode & OPCODE))  in do_tr()
1036 			tcode = (opcode >> 12) & ((1 << 4) - 1);  in do_tr()
1038 		if (__get_user(opcode, (u32 __user *)epc))  in do_tr()
1041 		if (!(opcode & OPCODE))  in do_tr()
1042 			tcode = (opcode >> 6) & ((1 << 10) - 1);  in do_tr()
1063 	unsigned int opcode = 0;  in do_ri()  local
1072 	    likely(get_user(opcode, epc) >= 0)) {  in do_ri()
1075 		status = mipsr2_decoder(regs, opcode, &fcr31);  in do_ri()
1112 		opcode = (mmop[0] << 16) | mmop[1];  in do_ri()
1115 			status = simulate_rdhwr_mm(regs, opcode);  in do_ri()
1117 		if (unlikely(get_user(opcode, epc) < 0))  in do_ri()
1121 			status = simulate_llsc(regs, opcode);  in do_ri()
1124 			status = simulate_rdhwr_normal(regs, opcode);  in do_ri()
1127 			status = simulate_sync(regs, opcode);  in do_ri()
1130 			status = simulate_fp(regs, opcode, old_epc, old31);  in do_ri()
1334 	unsigned int opcode;  in do_cpu()  local
1352 		opcode = 0;  in do_cpu()
1365 			opcode = (mmop[0] << 16) | mmop[1];  in do_cpu()
1368 				status = simulate_rdhwr_mm(regs, opcode);  in do_cpu()
1370 			if (unlikely(get_user(opcode, epc) < 0))  in do_cpu()
1374 				status = simulate_llsc(regs, opcode);  in do_cpu()
1377 				status = simulate_rdhwr_normal(regs, opcode);  in do_cpu()