Lines Matching refs:PLL

425 comment "Clock/PLL Setup"
451 	bool "Bypass PLL"
460 	  If this is set the clock will be divided by 2, before it goes to the PLL.
475 	  This controls the frequency of the on-chip PLL. This can be between 1 and 64.
476 	  PLL Frequency = (Crystal Frequency) * (this setting)
484 	  Core Frequency = (PLL frequency) / (this setting)
509 	  System Clock = (PLL frequency) / (this setting)
540 	  DDR Clock = (PLL frequency) / (this setting)
1265 	  The PLL and system clock (SCLK) continue to operate at a very low
1280 	  The PLL and system clock (SCLK), however, continue to operate in
1439 	  This option violates the PLL BYPASS recommendation in the Blackfin Processor
1441 	  the PLL may unlock.