Lines Matching refs:C
76 #define C(_x) \ macro
720 [C(L1D)] = {
721 [C(OP_READ)] = {
722 [C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
723 [C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
725 [C(OP_WRITE)] = {
726 [C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
727 [C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
729 [C(OP_PREFETCH)] = {
730 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
731 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
734 [C(L1I)] = {
735 [C(OP_READ)] = {
736 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
737 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
739 [C(OP_WRITE)] = {
740 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
741 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
743 [C(OP_PREFETCH)] = {
744 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
745 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
748 [C(LL)] = {
749 [C(OP_READ)] = {
750 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
751 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
753 [C(OP_WRITE)] = {
754 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
755 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
757 [C(OP_PREFETCH)] = {
758 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
759 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
762 [C(DTLB)] = {
763 [C(OP_READ)] = {
764 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
765 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
767 [C(OP_WRITE)] = {
768 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
769 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
771 [C(OP_PREFETCH)] = {
772 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
773 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
776 [C(ITLB)] = {
777 [C(OP_READ)] = {
778 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
779 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
781 [C(OP_WRITE)] = {
782 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
783 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
785 [C(OP_PREFETCH)] = {
786 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
787 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
790 [C(BPU)] = {
791 [C(OP_READ)] = {
792 [C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
793 [C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
795 [C(OP_WRITE)] = {
796 [C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
797 [C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
799 [C(OP_PREFETCH)] = {
800 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
801 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
804 [C(NODE)] = {
805 [C(OP_READ)] = {
806 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
807 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
809 [C(OP_WRITE)] = {
810 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
811 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
813 [C(OP_PREFETCH)] = {
814 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
815 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,