Lines Matching refs:cmu

175 		cmu: clock-controller@10030000 {  label
176 			compatible = "samsung,exynos3250-cmu";
179 			assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
180 					  <&cmu CLK_MOUT_ACLK_266_SUB>;
181 			assigned-clock-parents = <&cmu CLK_FIN_PLL>,
182 						 <&cmu CLK_FIN_PLL>;
186 			compatible = "samsung,exynos3250-cmu-dmc";
203 			clocks = <&cmu CLK_TMU_APBIF>;
225 			clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
251 			clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
266 			clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
277 			clocks = <&cmu CLK_USBOTG>;
288 			clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
300 			clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
312 			clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
328 				clocks = <&cmu CLK_PDMA0>;
339 				clocks = <&cmu CLK_PDMA1>;
353 			clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
365 			clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
374 			clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
385 			clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
398 			clocks = <&cmu CLK_I2C0>;
411 			clocks = <&cmu CLK_I2C1>;
424 			clocks = <&cmu CLK_I2C2>;
437 			clocks = <&cmu CLK_I2C3>;
450 			clocks = <&cmu CLK_I2C4>;
463 			clocks = <&cmu CLK_I2C5>;
476 			clocks = <&cmu CLK_I2C6>;
489 			clocks = <&cmu CLK_I2C7>;
504 			clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
520 			clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
532 			clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
576 			clocks = <&cmu CLK_PPMURIGHT>;
584 			clocks = <&cmu CLK_PPMULEFT>;
592 			clocks = <&cmu CLK_PPMUCAMIF>;
600 			clocks = <&cmu CLK_PPMULCD0>;
608 			clocks = <&cmu CLK_PPMUFILE>;
616 			clocks = <&cmu CLK_PPMUG3D>;
624 			clocks = <&cmu CLK_PPMUMFC_L>;