[..]
- V
 
- V0
 
- V1
 
- V10
 
- V10_1610_CF_IREQ
 
- V10_1610_MPUIO10
 
- V10_1610_MPUIO7
 
- V10_STRUCTS_H_
 
- V14_16XX_GPIO37
 
- V14_16XX_UART1_RX
 
- V15_VLD
 
- V19
 
- V19_1610_UWIRE_SCLK
 
- V1_ANY_UNIQUENESS
 
- V1_DEL_ALLOC
 
- V1_DEL_REWRITE
 
- V1_DESC
 
- V1_DIRECT_UNIQUENESS
 
- V1_DIRENTRY_UNIQUENESS
 
- V1_INDIRECT_UNIQUENESS
 
- V1_INIT_ALLOC
 
- V1_INIT_REWRITE
 
- V1_POLL_TIMEOUT_US
 
- V1_SD_UNIQUENESS
 
- V1_STATID
 
- V1_VSEC_OFFSET
 
- V1_minix_blocks
 
- V1_minix_get_block
 
- V1_minix_iget
 
- V1_minix_truncate
 
- V1_minix_update_inode
 
- V2
 
- V20
 
- V20_DESC
 
- V21
 
- V21_DESC
 
- V22
 
- V22_DESC
 
- V24
 
- V24_CABLE
 
- V25
 
- V253_VLS_H
 
- V253_VLS_HT
 
- V253_VLS_L
 
- V253_VLS_LT
 
- V253_VLS_M
 
- V253_VLS_M1
 
- V253_VLS_M1S
 
- V253_VLS_M1S1
 
- V253_VLS_M1S1T
 
- V253_VLS_M1ST
 
- V253_VLS_MS
 
- V253_VLS_MS1
 
- V253_VLS_MS1T
 
- V253_VLS_MST
 
- V253_VLS_NONE
 
- V253_VLS_S
 
- V253_VLS_S1
 
- V253_VLS_S1T
 
- V253_VLS_ST
 
- V253_VLS_T
 
- V253_VLS_TEST
 
- V26
 
- V2CLK_DAC_PM_EN
 
- V2CLK_PM_EN
 
- V2I_VCO_RATIO
 
- V2M_MAX_SPI
 
- V2M_MIN_SPI
 
- V2M_MSI_IIDR
 
- V2M_MSI_SETSPI_NS
 
- V2M_MSI_TYPER
 
- V2M_MSI_TYPER_BASE_MASK
 
- V2M_MSI_TYPER_BASE_SHIFT
 
- V2M_MSI_TYPER_BASE_SPI
 
- V2M_MSI_TYPER_NUM_MASK
 
- V2M_MSI_TYPER_NUM_SPI
 
- V2PCFG
 
- V2PCFG_MASK
 
- V2PCFG_SHIFT
 
- V2PLL_CNTL
 
- V2PPR
 
- V2PPW
 
- V2PSR
 
- V2PUR
 
- V2PUW
 
- V2Pxx_INDEX
 
- V2Pxx_INDEX_MASK
 
- V2Pxx_INDEX_SHIFT
 
- V2Pxx_VA
 
- V2Pxx_VA_MASK
 
- V2Pxx_VA_SHIFT
 
- V2_16
 
- V2_1710_GPIO10
 
- V2_19
 
- V2_22
 
- V2_CHECK_CREDIT_US
 
- V2_CLOCK_8PRE_FETCH_DISABLE
 
- V2_CLOCK_8PRE_FETCH_ENABLE
 
- V2_CLOCK_RATE_MASK
 
- V2_CLOCK_RATE_SHIFT
 
- V2_CLOCK_SRC_MASK
 
- V2_CLOCK_SRC_SHIFT
 
- V2_CLOCK_STATUS_OFFSET
 
- V2_CLOCK_TRAVELER_FETCH_DISABLE
 
- V2_CLOCK_TRAVELER_FETCH_ENABLE
 
- V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_M
 
- V2_CQC_BYTE_16_CQE_CUR_BLK_ADDR_S
 
- V2_CQC_BYTE_16_CQE_HOP_NUM_M
 
- V2_CQC_BYTE_16_CQE_HOP_NUM_S
 
- V2_CQC_BYTE_24_CQE_BA_PG_SZ_M
 
- V2_CQC_BYTE_24_CQE_BA_PG_SZ_S
 
- V2_CQC_BYTE_24_CQE_BUF_PG_SZ_M
 
- V2_CQC_BYTE_24_CQE_BUF_PG_SZ_S
 
- V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_M
 
- V2_CQC_BYTE_24_CQE_NXT_BLK_ADDR_S
 
- V2_CQC_BYTE_28_CQ_PRODUCER_IDX_M
 
- V2_CQC_BYTE_28_CQ_PRODUCER_IDX_S
 
- V2_CQC_BYTE_32_CQ_CONSUMER_IDX_M
 
- V2_CQC_BYTE_32_CQ_CONSUMER_IDX_S
 
- V2_CQC_BYTE_40_CQE_BA_M
 
- V2_CQC_BYTE_40_CQE_BA_S
 
- V2_CQC_BYTE_44_DB_RECORD_ADDR_M
 
- V2_CQC_BYTE_44_DB_RECORD_ADDR_S
 
- V2_CQC_BYTE_44_DB_RECORD_EN_S
 
- V2_CQC_BYTE_4_ARM_ST_M
 
- V2_CQC_BYTE_4_ARM_ST_S
 
- V2_CQC_BYTE_4_CEQN_M
 
- V2_CQC_BYTE_4_CEQN_S
 
- V2_CQC_BYTE_4_CMD_SN_M
 
- V2_CQC_BYTE_4_CMD_SN_S
 
- V2_CQC_BYTE_4_COALESCE_S
 
- V2_CQC_BYTE_4_CQ_ST_M
 
- V2_CQC_BYTE_4_CQ_ST_S
 
- V2_CQC_BYTE_4_OVER_IGNORE_S
 
- V2_CQC_BYTE_4_PAGE_OFFSET_M
 
- V2_CQC_BYTE_4_PAGE_OFFSET_S
 
- V2_CQC_BYTE_4_POLL_S
 
- V2_CQC_BYTE_4_SE_S
 
- V2_CQC_BYTE_4_SHIFT_M
 
- V2_CQC_BYTE_4_SHIFT_S
 
- V2_CQC_BYTE_52_CQE_CNT_M
 
- V2_CQC_BYTE_52_CQE_CNT_S
 
- V2_CQC_BYTE_56_CQ_MAX_CNT_M
 
- V2_CQC_BYTE_56_CQ_MAX_CNT_S
 
- V2_CQC_BYTE_56_CQ_PERIOD_M
 
- V2_CQC_BYTE_56_CQ_PERIOD_S
 
- V2_CQC_BYTE_64_SE_CQE_IDX_M
 
- V2_CQC_BYTE_64_SE_CQE_IDX_S
 
- V2_CQC_BYTE_8_CQN_M
 
- V2_CQC_BYTE_8_CQN_S
 
- V2_CQE_BYTE_12_XRC_SRQN_M
 
- V2_CQE_BYTE_12_XRC_SRQN_S
 
- V2_CQE_BYTE_16_LCL_QPN_M
 
- V2_CQE_BYTE_16_LCL_QPN_S
 
- V2_CQE_BYTE_16_SUB_STATUS_M
 
- V2_CQE_BYTE_16_SUB_STATUS_S
 
- V2_CQE_BYTE_28_PORT_TYPE_M
 
- V2_CQE_BYTE_28_PORT_TYPE_S
 
- V2_CQE_BYTE_28_SMAC_4_M
 
- V2_CQE_BYTE_28_SMAC_4_S
 
- V2_CQE_BYTE_28_SMAC_5_M
 
- V2_CQE_BYTE_28_SMAC_5_S
 
- V2_CQE_BYTE_28_VID_M
 
- V2_CQE_BYTE_28_VID_S
 
- V2_CQE_BYTE_28_VID_VLD_S
 
- V2_CQE_BYTE_32_GRH_S
 
- V2_CQE_BYTE_32_LPK_S
 
- V2_CQE_BYTE_32_PORTN_M
 
- V2_CQE_BYTE_32_PORTN_S
 
- V2_CQE_BYTE_32_RMT_QPN_M
 
- V2_CQE_BYTE_32_RMT_QPN_S
 
- V2_CQE_BYTE_32_SL_M
 
- V2_CQE_BYTE_32_SL_S
 
- V2_CQE_BYTE_4_OPCODE_M
 
- V2_CQE_BYTE_4_OPCODE_S
 
- V2_CQE_BYTE_4_OWNER_S
 
- V2_CQE_BYTE_4_RQ_INLINE_S
 
- V2_CQE_BYTE_4_STATUS_M
 
- V2_CQE_BYTE_4_STATUS_S
 
- V2_CQE_BYTE_4_S_R_S
 
- V2_CQE_BYTE_4_WQE_INDX_M
 
- V2_CQE_BYTE_4_WQE_INDX_S
 
- V2_CQ_DB_BYTE_4_CMD_M
 
- V2_CQ_DB_BYTE_4_CMD_S
 
- V2_CQ_DB_BYTE_4_TAG_M
 
- V2_CQ_DB_BYTE_4_TAG_S
 
- V2_CQ_DB_PARAMETER_CMD_SN_M
 
- V2_CQ_DB_PARAMETER_CMD_SN_S
 
- V2_CQ_DB_PARAMETER_CONS_IDX_M
 
- V2_CQ_DB_PARAMETER_CONS_IDX_S
 
- V2_CQ_DB_PARAMETER_NOTIFY_S
 
- V2_CQ_DB_REQ_NOT
 
- V2_CQ_DB_REQ_NOT_SOL
 
- V2_CQ_STATE_VALID
 
- V2_CREDIT_TIMEOUT_US
 
- V2_DB_BYTE_4_CMD_M
 
- V2_DB_BYTE_4_CMD_S
 
- V2_DB_BYTE_4_TAG_M
 
- V2_DB_BYTE_4_TAG_S
 
- V2_DB_PARAMETER_IDX_M
 
- V2_DB_PARAMETER_IDX_S
 
- V2_DB_PARAMETER_SL_M
 
- V2_DB_PARAMETER_SL_S
 
- V2_DEL_ALLOC
 
- V2_DEL_REWRITE
 
- V2_DESC
 
- V2_DQBLKSIZE_BITS
 
- V2_DQINFOOFF
 
- V2_HARDWARE
 
- V2_INITQMAGICS
 
- V2_INITQVERSIONS
 
- V2_INIT_ALLOC
 
- V2_INIT_REWRITE
 
- V2_IN_OUT_CONF_OFFSET
 
- V2_IR
 
- V2_MICRO_LEVEL_RANGE
 
- V2_MODE
 
- V2_MPT_BYTE_12_BPD_S
 
- V2_MPT_BYTE_12_BQP_S
 
- V2_MPT_BYTE_12_FRE_S
 
- V2_MPT_BYTE_12_INNER_PA_VLD_S
 
- V2_MPT_BYTE_12_MR_MW_S
 
- V2_MPT_BYTE_12_MW_BIND_QPN_M
 
- V2_MPT_BYTE_12_MW_BIND_QPN_S
 
- V2_MPT_BYTE_12_PA_S
 
- V2_MPT_BYTE_48_BLK_MODE_S
 
- V2_MPT_BYTE_48_PBL_BA_H_M
 
- V2_MPT_BYTE_48_PBL_BA_H_S
 
- V2_MPT_BYTE_4_MPT_ST_M
 
- V2_MPT_BYTE_4_MPT_ST_S
 
- V2_MPT_BYTE_4_PBL_BA_PG_SZ_M
 
- V2_MPT_BYTE_4_PBL_BA_PG_SZ_S
 
- V2_MPT_BYTE_4_PBL_HOP_NUM_M
 
- V2_MPT_BYTE_4_PBL_HOP_NUM_S
 
- V2_MPT_BYTE_4_PD_M
 
- V2_MPT_BYTE_4_PD_S
 
- V2_MPT_BYTE_56_PA0_H_M
 
- V2_MPT_BYTE_56_PA0_H_S
 
- V2_MPT_BYTE_64_PA1_H_M
 
- V2_MPT_BYTE_64_PA1_H_S
 
- V2_MPT_BYTE_64_PBL_BUF_PG_SZ_M
 
- V2_MPT_BYTE_64_PBL_BUF_PG_SZ_S
 
- V2_MPT_BYTE_8_ATOMIC_EN_S
 
- V2_MPT_BYTE_8_BIND_EN_S
 
- V2_MPT_BYTE_8_LW_EN_S
 
- V2_MPT_BYTE_8_L_INV_EN_S
 
- V2_MPT_BYTE_8_MW_CNT_M
 
- V2_MPT_BYTE_8_MW_CNT_S
 
- V2_MPT_BYTE_8_RA_EN_S
 
- V2_MPT_BYTE_8_RR_EN_S
 
- V2_MPT_BYTE_8_RW_EN_S
 
- V2_MPT_BYTE_8_R_INV_EN_S
 
- V2_MPT_ST_FREE
 
- V2_MPT_ST_VALID
 
- V2_OFFSET
 
- V2_ONE_PORT_RVX_ONE_PORT_IMBED_MDM
 
- V2_OPT_IFACE_MODE_ADAT
 
- V2_OPT_IFACE_MODE_NONE
 
- V2_OPT_IFACE_MODE_SPDIF
 
- V2_OPT_IN_IFACE_MASK
 
- V2_OPT_IN_IFACE_SHIFT
 
- V2_OPT_OUT_IFACE_MASK
 
- V2_OPT_OUT_IFACE_SHIFT
 
- V2_POLL_TIMEOUT_US
 
- V2_QKEY_VAL
 
- V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_M
 
- V2_QPC_BYTE_104_RQ_CUR_WQE_SGE_NUM_S
 
- V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_M
 
- V2_QPC_BYTE_104_RQ_NXT_BLK_ADDR_S
 
- V2_QPC_BYTE_108_INV_CREDIT_S
 
- V2_QPC_BYTE_108_RX_REQ_EPSN_M
 
- V2_QPC_BYTE_108_RX_REQ_EPSN_S
 
- V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_M
 
- V2_QPC_BYTE_108_RX_REQ_LAST_OPTYPE_S
 
- V2_QPC_BYTE_108_RX_REQ_PSN_ERR_S
 
- V2_QPC_BYTE_108_RX_REQ_RNR_S
 
- V2_QPC_BYTE_12_RSVD_LKEY_EN_S
 
- V2_QPC_BYTE_12_SQ_HOP_NUM_M
 
- V2_QPC_BYTE_12_SQ_HOP_NUM_S
 
- V2_QPC_BYTE_12_WQE_SGE_BA_M
 
- V2_QPC_BYTE_12_WQE_SGE_BA_S
 
- V2_QPC_BYTE_132_TRRL_BA_M
 
- V2_QPC_BYTE_132_TRRL_BA_S
 
- V2_QPC_BYTE_132_TRRL_HEAD_MAX_M
 
- V2_QPC_BYTE_132_TRRL_HEAD_MAX_S
 
- V2_QPC_BYTE_132_TRRL_TAIL_MAX_M
 
- V2_QPC_BYTE_132_TRRL_TAIL_MAX_S
 
- V2_QPC_BYTE_140_RAQ_TRRL_HEAD_M
 
- V2_QPC_BYTE_140_RAQ_TRRL_HEAD_S
 
- V2_QPC_BYTE_140_RAQ_TRRL_TAIL_M
 
- V2_QPC_BYTE_140_RAQ_TRRL_TAIL_S
 
- V2_QPC_BYTE_140_RQ_RTY_WAIT_DO_S
 
- V2_QPC_BYTE_140_RR_MAX_M
 
- V2_QPC_BYTE_140_RR_MAX_S
 
- V2_QPC_BYTE_140_TRRL_BA_M
 
- V2_QPC_BYTE_140_TRRL_BA_S
 
- V2_QPC_BYTE_144_RAQ_CREDIT_M
 
- V2_QPC_BYTE_144_RAQ_CREDIT_S
 
- V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_M
 
- V2_QPC_BYTE_144_RAQ_RTY_INI_PSN_S
 
- V2_QPC_BYTE_144_RESP_RTY_FLG_S
 
- V2_QPC_BYTE_148_RAQ_SYNDROME_M
 
- V2_QPC_BYTE_148_RAQ_SYNDROME_S
 
- V2_QPC_BYTE_148_RQ_MSN_M
 
- V2_QPC_BYTE_148_RQ_MSN_S
 
- V2_QPC_BYTE_152_RAQ_PSN_M
 
- V2_QPC_BYTE_152_RAQ_PSN_S
 
- V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_M
 
- V2_QPC_BYTE_152_RAQ_TRRL_RTY_HEAD_S
 
- V2_QPC_BYTE_156_RAQ_USE_PKTN_M
 
- V2_QPC_BYTE_156_RAQ_USE_PKTN_S
 
- V2_QPC_BYTE_160_SQ_CONSUMER_IDX_M
 
- V2_QPC_BYTE_160_SQ_CONSUMER_IDX_S
 
- V2_QPC_BYTE_160_SQ_PRODUCER_IDX_M
 
- V2_QPC_BYTE_160_SQ_PRODUCER_IDX_S
 
- V2_QPC_BYTE_168_IRRL_IDX_LSB_M
 
- V2_QPC_BYTE_168_IRRL_IDX_LSB_S
 
- V2_QPC_BYTE_168_LP_SGEN_INI_M
 
- V2_QPC_BYTE_168_LP_SGEN_INI_S
 
- V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S
 
- V2_QPC_BYTE_168_POLL_DB_WAIT_DO_S
 
- V2_QPC_BYTE_168_SCC_TOKEN_FORBID_SQ_DEQ_S
 
- V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_M
 
- V2_QPC_BYTE_168_SQ_CUR_BLK_ADDR_S
 
- V2_QPC_BYTE_168_SQ_INVLD_FLG_S
 
- V2_QPC_BYTE_168_SQ_VLAN_EN_S
 
- V2_QPC_BYTE_168_WAIT_ACK_TIMEOUT_S
 
- V2_QPC_BYTE_16_PD_M
 
- V2_QPC_BYTE_16_PD_S
 
- V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_M
 
- V2_QPC_BYTE_16_WQE_SGE_BA_PG_SZ_S
 
- V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_M
 
- V2_QPC_BYTE_16_WQE_SGE_BUF_PG_SZ_S
 
- V2_QPC_BYTE_172_ACK_REQ_FREQ_M
 
- V2_QPC_BYTE_172_ACK_REQ_FREQ_S
 
- V2_QPC_BYTE_172_FRE_S
 
- V2_QPC_BYTE_172_MSG_RNR_FLG_S
 
- V2_QPC_BYTE_172_SQ_CUR_PSN_M
 
- V2_QPC_BYTE_172_SQ_CUR_PSN_S
 
- V2_QPC_BYTE_176_IRRL_HEAD_PRE_M
 
- V2_QPC_BYTE_176_IRRL_HEAD_PRE_S
 
- V2_QPC_BYTE_176_MSG_USE_PKTN_M
 
- V2_QPC_BYTE_176_MSG_USE_PKTN_S
 
- V2_QPC_BYTE_184_IRRL_IDX_MSB_M
 
- V2_QPC_BYTE_184_IRRL_IDX_MSB_S
 
- V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_M
 
- V2_QPC_BYTE_184_SQ_CUR_SGE_BLK_ADDR_S
 
- V2_QPC_BYTE_192_CUR_SGE_IDX_M
 
- V2_QPC_BYTE_192_CUR_SGE_IDX_S
 
- V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_M
 
- V2_QPC_BYTE_192_EXT_SGE_NUM_LEFT_S
 
- V2_QPC_BYTE_196_IRRL_HEAD_M
 
- V2_QPC_BYTE_196_IRRL_HEAD_S
 
- V2_QPC_BYTE_196_SQ_MAX_PSN_M
 
- V2_QPC_BYTE_196_SQ_MAX_PSN_S
 
- V2_QPC_BYTE_200_LCL_OPERATED_CNT_M
 
- V2_QPC_BYTE_200_LCL_OPERATED_CNT_S
 
- V2_QPC_BYTE_200_SQ_MAX_IDX_M
 
- V2_QPC_BYTE_200_SQ_MAX_IDX_S
 
- V2_QPC_BYTE_208_IRRL_BA_M
 
- V2_QPC_BYTE_208_IRRL_BA_S
 
- V2_QPC_BYTE_208_PKT_RNR_FLG_S
 
- V2_QPC_BYTE_208_PKT_RTY_FLG_S
 
- V2_QPC_BYTE_208_RMT_E2E_S
 
- V2_QPC_BYTE_208_SR_MAX_M
 
- V2_QPC_BYTE_208_SR_MAX_S
 
- V2_QPC_BYTE_20_RQWS_M
 
- V2_QPC_BYTE_20_RQWS_S
 
- V2_QPC_BYTE_20_RQ_HOP_NUM_M
 
- V2_QPC_BYTE_20_RQ_HOP_NUM_S
 
- V2_QPC_BYTE_20_RQ_SHIFT_M
 
- V2_QPC_BYTE_20_RQ_SHIFT_S
 
- V2_QPC_BYTE_20_SGE_HOP_NUM_M
 
- V2_QPC_BYTE_20_SGE_HOP_NUM_S
 
- V2_QPC_BYTE_20_SGID_IDX_M
 
- V2_QPC_BYTE_20_SGID_IDX_S
 
- V2_QPC_BYTE_20_SMAC_IDX_M
 
- V2_QPC_BYTE_20_SMAC_IDX_S
 
- V2_QPC_BYTE_20_SQ_SHIFT_M
 
- V2_QPC_BYTE_20_SQ_SHIFT_S
 
- V2_QPC_BYTE_212_CHECK_FLG_M
 
- V2_QPC_BYTE_212_CHECK_FLG_S
 
- V2_QPC_BYTE_212_LSN_M
 
- V2_QPC_BYTE_212_LSN_S
 
- V2_QPC_BYTE_212_RETRY_CNT_M
 
- V2_QPC_BYTE_212_RETRY_CNT_S
 
- V2_QPC_BYTE_212_RETRY_NUM_INIT_M
 
- V2_QPC_BYTE_212_RETRY_NUM_INIT_S
 
- V2_QPC_BYTE_220_RETRY_MSG_MSN_M
 
- V2_QPC_BYTE_220_RETRY_MSG_MSN_S
 
- V2_QPC_BYTE_220_RETRY_MSG_PSN_M
 
- V2_QPC_BYTE_220_RETRY_MSG_PSN_S
 
- V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_M
 
- V2_QPC_BYTE_224_RETRY_MSG_FPKT_PSN_S
 
- V2_QPC_BYTE_224_RETRY_MSG_PSN_M
 
- V2_QPC_BYTE_224_RETRY_MSG_PSN_S
 
- V2_QPC_BYTE_232_FENCE_LP_VLD_S
 
- V2_QPC_BYTE_232_IRRL_LP_VLD_S
 
- V2_QPC_BYTE_232_IRRL_SGE_IDX_M
 
- V2_QPC_BYTE_232_IRRL_SGE_IDX_S
 
- V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_M
 
- V2_QPC_BYTE_232_RX_SQ_CUR_BLK_ADDR_S
 
- V2_QPC_BYTE_232_SO_LP_VLD_S
 
- V2_QPC_BYTE_240_IRRL_TAIL_RD_M
 
- V2_QPC_BYTE_240_IRRL_TAIL_RD_S
 
- V2_QPC_BYTE_240_IRRL_TAIL_REAL_M
 
- V2_QPC_BYTE_240_IRRL_TAIL_REAL_S
 
- V2_QPC_BYTE_240_RX_ACK_MSN_M
 
- V2_QPC_BYTE_240_RX_ACK_MSN_S
 
- V2_QPC_BYTE_244_IRRL_RD_FLG_S
 
- V2_QPC_BYTE_244_LCL_OP_FLG_S
 
- V2_QPC_BYTE_244_RNR_CNT_M
 
- V2_QPC_BYTE_244_RNR_CNT_S
 
- V2_QPC_BYTE_244_RNR_NUM_INIT_M
 
- V2_QPC_BYTE_244_RNR_NUM_INIT_S
 
- V2_QPC_BYTE_244_RX_ACK_EPSN_M
 
- V2_QPC_BYTE_244_RX_ACK_EPSN_S
 
- V2_QPC_BYTE_248_ACK_LAST_OPTYPE_M
 
- V2_QPC_BYTE_248_ACK_LAST_OPTYPE_S
 
- V2_QPC_BYTE_248_ACK_PSN_ERR_S
 
- V2_QPC_BYTE_248_CQ_ERR_IND_S
 
- V2_QPC_BYTE_248_IRRL_PSN_M
 
- V2_QPC_BYTE_248_IRRL_PSN_S
 
- V2_QPC_BYTE_248_IRRL_PSN_VLD_S
 
- V2_QPC_BYTE_248_RNR_RETRY_FLAG_S
 
- V2_QPC_BYTE_24_HOP_LIMIT_M
 
- V2_QPC_BYTE_24_HOP_LIMIT_S
 
- V2_QPC_BYTE_24_MTU_M
 
- V2_QPC_BYTE_24_MTU_S
 
- V2_QPC_BYTE_24_TC_M
 
- V2_QPC_BYTE_24_TC_S
 
- V2_QPC_BYTE_24_VLAN_ID_M
 
- V2_QPC_BYTE_24_VLAN_ID_S
 
- V2_QPC_BYTE_252_ERR_TYPE_M
 
- V2_QPC_BYTE_252_ERR_TYPE_S
 
- V2_QPC_BYTE_252_SIG_TYPE_S
 
- V2_QPC_BYTE_252_TX_CQN_M
 
- V2_QPC_BYTE_252_TX_CQN_S
 
- V2_QPC_BYTE_256_RQ_CQE_IDX_M
 
- V2_QPC_BYTE_256_RQ_CQE_IDX_S
 
- V2_QPC_BYTE_256_SQ_FLUSH_IDX_M
 
- V2_QPC_BYTE_256_SQ_FLUSH_IDX_S
 
- V2_QPC_BYTE_28_AT_M
 
- V2_QPC_BYTE_28_AT_S
 
- V2_QPC_BYTE_28_CE_FLAG_S
 
- V2_QPC_BYTE_28_CNP_TX_FLAG_S
 
- V2_QPC_BYTE_28_FL_M
 
- V2_QPC_BYTE_28_FL_S
 
- V2_QPC_BYTE_28_LBI_S
 
- V2_QPC_BYTE_28_SL_M
 
- V2_QPC_BYTE_28_SL_S
 
- V2_QPC_BYTE_4_SGE_SHIFT_M
 
- V2_QPC_BYTE_4_SGE_SHIFT_S
 
- V2_QPC_BYTE_4_SQPN_M
 
- V2_QPC_BYTE_4_SQPN_S
 
- V2_QPC_BYTE_4_TST_M
 
- V2_QPC_BYTE_4_TST_S
 
- V2_QPC_BYTE_52_DMAC_M
 
- V2_QPC_BYTE_52_DMAC_S
 
- V2_QPC_BYTE_52_UDPSPN_M
 
- V2_QPC_BYTE_52_UDPSPN_S
 
- V2_QPC_BYTE_56_DQPN_M
 
- V2_QPC_BYTE_56_DQPN_S
 
- V2_QPC_BYTE_56_LP_PKTN_INI_M
 
- V2_QPC_BYTE_56_LP_PKTN_INI_S
 
- V2_QPC_BYTE_56_RQ_RX_ERR_S
 
- V2_QPC_BYTE_56_RQ_TX_ERR_S
 
- V2_QPC_BYTE_56_SQ_RX_ERR_S
 
- V2_QPC_BYTE_56_SQ_TX_ERR_S
 
- V2_QPC_BYTE_60_QP_ST_M
 
- V2_QPC_BYTE_60_QP_ST_S
 
- V2_QPC_BYTE_60_RQ_DB_DOING_S
 
- V2_QPC_BYTE_60_SCC_TOKEN_M
 
- V2_QPC_BYTE_60_SCC_TOKEN_S
 
- V2_QPC_BYTE_60_SQ_DB_DOING_S
 
- V2_QPC_BYTE_60_TEMPID_M
 
- V2_QPC_BYTE_60_TEMPID_S
 
- V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_M
 
- V2_QPC_BYTE_68_RQ_DB_RECORD_ADDR_S
 
- V2_QPC_BYTE_68_RQ_RECORD_EN_S
 
- V2_QPC_BYTE_76_ATE_S
 
- V2_QPC_BYTE_76_RQIE_S
 
- V2_QPC_BYTE_76_RQ_VLAN_EN_S
 
- V2_QPC_BYTE_76_RRE_S
 
- V2_QPC_BYTE_76_RWE_S
 
- V2_QPC_BYTE_76_SRQN_M
 
- V2_QPC_BYTE_76_SRQN_S
 
- V2_QPC_BYTE_76_SRQ_EN_S
 
- V2_QPC_BYTE_80_MIN_RNR_TIME_M
 
- V2_QPC_BYTE_80_MIN_RNR_TIME_S
 
- V2_QPC_BYTE_80_RX_CQN_M
 
- V2_QPC_BYTE_80_RX_CQN_S
 
- V2_QPC_BYTE_84_RQ_CONSUMER_IDX_M
 
- V2_QPC_BYTE_84_RQ_CONSUMER_IDX_S
 
- V2_QPC_BYTE_84_RQ_PRODUCER_IDX_M
 
- V2_QPC_BYTE_84_RQ_PRODUCER_IDX_S
 
- V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_M
 
- V2_QPC_BYTE_92_RQ_CUR_BLK_ADDR_S
 
- V2_QPC_BYTE_92_SRQ_INFO_M
 
- V2_QPC_BYTE_92_SRQ_INFO_S
 
- V2_QPC_BYTE_96_RX_REQ_MSN_M
 
- V2_QPC_BYTE_96_RX_REQ_MSN_S
 
- V2_QP_ATE_S
 
- V2_QP_RRE_S
 
- V2_QP_RWE_S
 
- V2_RC_FRMR_WQE_BYTE_40_BLK_MODE_S
 
- V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_M
 
- V2_RC_FRMR_WQE_BYTE_40_PBL_BUF_PG_SZ_S
 
- V2_RC_FRMR_WQE_BYTE_4_ATOMIC_S
 
- V2_RC_FRMR_WQE_BYTE_4_BIND_EN_S
 
- V2_RC_FRMR_WQE_BYTE_4_LW_S
 
- V2_RC_FRMR_WQE_BYTE_4_RR_S
 
- V2_RC_FRMR_WQE_BYTE_4_RW_S
 
- V2_RC_SEND_WQE_BYTE_16_SGE_NUM_M
 
- V2_RC_SEND_WQE_BYTE_16_SGE_NUM_S
 
- V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_M
 
- V2_RC_SEND_WQE_BYTE_16_XRC_SRQN_S
 
- V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M
 
- V2_RC_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S
 
- V2_RC_SEND_WQE_BYTE_4_CQE_S
 
- V2_RC_SEND_WQE_BYTE_4_FENCE_S
 
- V2_RC_SEND_WQE_BYTE_4_INLINE_S
 
- V2_RC_SEND_WQE_BYTE_4_OPCODE_M
 
- V2_RC_SEND_WQE_BYTE_4_OPCODE_S
 
- V2_RC_SEND_WQE_BYTE_4_OWNER_S
 
- V2_RC_SEND_WQE_BYTE_4_SE_S
 
- V2_RC_SEND_WQE_BYTE_4_SO_S
 
- V2_STATID
 
- V2_TCMP
 
- V2_TCN
 
- V2_TCTL_24MEN
 
- V2_TCTL_CLK_IPG
 
- V2_TCTL_CLK_OSC_DIV8
 
- V2_TCTL_CLK_PER
 
- V2_TCTL_FRR
 
- V2_TCTL_WAITEN
 
- V2_TIMER_RATE_OSC_DIV8
 
- V2_TPRER_PRE24M
 
- V2_TSTAT
 
- V2_TSTAT_OF1
 
- V2_TWO_PORTS_RVX
 
- V2_UD_SEND_WQE_BYTE_16_PD_M
 
- V2_UD_SEND_WQE_BYTE_16_PD_S
 
- V2_UD_SEND_WQE_BYTE_16_SGE_NUM_M
 
- V2_UD_SEND_WQE_BYTE_16_SGE_NUM_S
 
- V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_M
 
- V2_UD_SEND_WQE_BYTE_20_MSG_START_SGE_IDX_S
 
- V2_UD_SEND_WQE_BYTE_24_UDPSPN_M
 
- V2_UD_SEND_WQE_BYTE_24_UDPSPN_S
 
- V2_UD_SEND_WQE_BYTE_32_DQPN_M
 
- V2_UD_SEND_WQE_BYTE_32_DQPN_S
 
- V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M
 
- V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S
 
- V2_UD_SEND_WQE_BYTE_36_TCLASS_M
 
- V2_UD_SEND_WQE_BYTE_36_TCLASS_S
 
- V2_UD_SEND_WQE_BYTE_36_VLAN_M
 
- V2_UD_SEND_WQE_BYTE_36_VLAN_S
 
- V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M
 
- V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S
 
- V2_UD_SEND_WQE_BYTE_40_LBI_S
 
- V2_UD_SEND_WQE_BYTE_40_PORTN_M
 
- V2_UD_SEND_WQE_BYTE_40_PORTN_S
 
- V2_UD_SEND_WQE_BYTE_40_SL_M
 
- V2_UD_SEND_WQE_BYTE_40_SL_S
 
- V2_UD_SEND_WQE_BYTE_40_UD_VLAN_EN_S
 
- V2_UD_SEND_WQE_BYTE_48_DMAC_4_M
 
- V2_UD_SEND_WQE_BYTE_48_DMAC_4_S
 
- V2_UD_SEND_WQE_BYTE_48_DMAC_5_M
 
- V2_UD_SEND_WQE_BYTE_48_DMAC_5_S
 
- V2_UD_SEND_WQE_BYTE_48_SGID_INDX_M
 
- V2_UD_SEND_WQE_BYTE_48_SGID_INDX_S
 
- V2_UD_SEND_WQE_BYTE_48_SMAC_INDX_M
 
- V2_UD_SEND_WQE_BYTE_48_SMAC_INDX_S
 
- V2_UD_SEND_WQE_BYTE_4_CQE_S
 
- V2_UD_SEND_WQE_BYTE_4_OPCODE_M
 
- V2_UD_SEND_WQE_BYTE_4_OPCODE_S
 
- V2_UD_SEND_WQE_BYTE_4_OWNER_S
 
- V2_UD_SEND_WQE_BYTE_4_SE_S
 
- V2_UD_SEND_WQE_DMAC_0_M
 
- V2_UD_SEND_WQE_DMAC_0_S
 
- V2_UD_SEND_WQE_DMAC_1_M
 
- V2_UD_SEND_WQE_DMAC_1_S
 
- V2_UD_SEND_WQE_DMAC_2_M
 
- V2_UD_SEND_WQE_DMAC_2_S
 
- V2_UD_SEND_WQE_DMAC_3_M
 
- V2_UD_SEND_WQE_DMAC_3_S
 
- V2_USER_TIMEOUT_US
 
- V2_minix_blocks
 
- V2_minix_get_block
 
- V2_minix_iget
 
- V2_minix_truncate
 
- V2_minix_update_inode
 
- V3
 
- V3020_CMD_CLOCK2RAM
 
- V3020_CMD_RAM2CLOCK
 
- V3020_CS
 
- V3020_HOURS
 
- V3020_IO
 
- V3020_IS_COMMAND
 
- V3020_MINUTES
 
- V3020_MONTH
 
- V3020_MONTH_DAY
 
- V3020_RD
 
- V3020_SECONDS
 
- V3020_STATUS_0
 
- V3020_STATUS_1
 
- V3020_WEEK
 
- V3020_WEEK_DAY
 
- V3020_WR
 
- V3020_YEAR
 
- V35
 
- V35_CABLE
 
- V36_CABLE
 
- V3D_BFC
 
- V3D_BIN
 
- V3D_BMACTIVE
 
- V3D_BMBUSY
 
- V3D_BMOOM
 
- V3D_BPCA
 
- V3D_BPCS
 
- V3D_BPOA
 
- V3D_BPOS
 
- V3D_BRIDGE_READ
 
- V3D_BRIDGE_WRITE
 
- V3D_BXCF
 
- V3D_CACHE_CLEAN
 
- V3D_CLE_BFC
 
- V3D_CLE_CT0CA
 
- V3D_CLE_CT0CS
 
- V3D_CLE_CT0EA
 
- V3D_CLE_CT0LC
 
- V3D_CLE_CT0PC
 
- V3D_CLE_CT0QBA
 
- V3D_CLE_CT0QEA
 
- V3D_CLE_CT0QMA
 
- V3D_CLE_CT0QMS
 
- V3D_CLE_CT0QTS
 
- V3D_CLE_CT0QTS_ENABLE
 
- V3D_CLE_CT0RA
 
- V3D_CLE_CT0SYNC
 
- V3D_CLE_CT1CA
 
- V3D_CLE_CT1CFG
 
- V3D_CLE_CT1CS
 
- V3D_CLE_CT1EA
 
- V3D_CLE_CT1LC
 
- V3D_CLE_CT1PC
 
- V3D_CLE_CT1PTCT
 
- V3D_CLE_CT1QBA
 
- V3D_CLE_CT1QCFG
 
- V3D_CLE_CT1QEA
 
- V3D_CLE_CT1RA
 
- V3D_CLE_CT1SYNC
 
- V3D_CLE_CT1TILECT
 
- V3D_CLE_CT1TSKIP
 
- V3D_CLE_CTNCA
 
- V3D_CLE_CTNCS
 
- V3D_CLE_CTNEA
 
- V3D_CLE_CTNQBA
 
- V3D_CLE_CTNQEA
 
- V3D_CLE_CTNRA
 
- V3D_CLE_PCS
 
- V3D_CLE_QCFG_ETFILT
 
- V3D_CLE_QCFG_ETPROC
 
- V3D_CLE_QCFG_ETSFLUSH
 
- V3D_CLE_QCFG_MCDIS
 
- V3D_CLE_RFC
 
- V3D_CLE_TFBC
 
- V3D_CLE_TFIT
 
- V3D_CORE_IRQS
 
- V3D_CORE_READ
 
- V3D_CORE_WRITE
 
- V3D_CSD
 
- V3D_CSD_CURRENT_CFG0
 
- V3D_CSD_CURRENT_CFG1
 
- V3D_CSD_CURRENT_CFG2
 
- V3D_CSD_CURRENT_CFG3
 
- V3D_CSD_CURRENT_CFG4
 
- V3D_CSD_CURRENT_CFG5
 
- V3D_CSD_CURRENT_CFG6
 
- V3D_CSD_CURRENT_ID0
 
- V3D_CSD_CURRENT_ID0_L_IDX_MASK
 
- V3D_CSD_CURRENT_ID0_L_IDX_SHIFT
 
- V3D_CSD_CURRENT_ID0_WG_IN_SG_MASK
 
- V3D_CSD_CURRENT_ID0_WG_IN_SG_SHIFT
 
- V3D_CSD_CURRENT_ID0_WG_X_MASK
 
- V3D_CSD_CURRENT_ID0_WG_X_SHIFT
 
- V3D_CSD_CURRENT_ID0_WG_Y_MASK
 
- V3D_CSD_CURRENT_ID0_WG_Y_SHIFT
 
- V3D_CSD_CURRENT_ID0_WG_Z_MASK
 
- V3D_CSD_CURRENT_ID0_WG_Z_SHIFT
 
- V3D_CSD_CURRENT_ID1
 
- V3D_CSD_QUEUED_CFG0
 
- V3D_CSD_QUEUED_CFG0_NUM_WGS_X_MASK
 
- V3D_CSD_QUEUED_CFG0_NUM_WGS_X_SHIFT
 
- V3D_CSD_QUEUED_CFG0_WG_X_OFFSET_MASK
 
- V3D_CSD_QUEUED_CFG0_WG_X_OFFSET_SHIFT
 
- V3D_CSD_QUEUED_CFG1
 
- V3D_CSD_QUEUED_CFG1_NUM_WGS_Y_MASK
 
- V3D_CSD_QUEUED_CFG1_NUM_WGS_Y_SHIFT
 
- V3D_CSD_QUEUED_CFG1_WG_Y_OFFSET_MASK
 
- V3D_CSD_QUEUED_CFG1_WG_Y_OFFSET_SHIFT
 
- V3D_CSD_QUEUED_CFG2
 
- V3D_CSD_QUEUED_CFG2_NUM_WGS_Z_MASK
 
- V3D_CSD_QUEUED_CFG2_NUM_WGS_Z_SHIFT
 
- V3D_CSD_QUEUED_CFG2_WG_Z_OFFSET_MASK
 
- V3D_CSD_QUEUED_CFG2_WG_Z_OFFSET_SHIFT
 
- V3D_CSD_QUEUED_CFG3
 
- V3D_CSD_QUEUED_CFG3_BATCHES_PER_SG_M1_MASK
 
- V3D_CSD_QUEUED_CFG3_BATCHES_PER_SG_M1_SHIFT
 
- V3D_CSD_QUEUED_CFG3_MAX_SG_ID_MASK
 
- V3D_CSD_QUEUED_CFG3_MAX_SG_ID_SHIFT
 
- V3D_CSD_QUEUED_CFG3_OVERLAP_WITH_PREV
 
- V3D_CSD_QUEUED_CFG3_WGS_PER_SG_MASK
 
- V3D_CSD_QUEUED_CFG3_WGS_PER_SG_SHIFT
 
- V3D_CSD_QUEUED_CFG3_WG_SIZE_MASK
 
- V3D_CSD_QUEUED_CFG3_WG_SIZE_SHIFT
 
- V3D_CSD_QUEUED_CFG4
 
- V3D_CSD_QUEUED_CFG5
 
- V3D_CSD_QUEUED_CFG6
 
- V3D_CSD_STATUS
 
- V3D_CSD_STATUS_HAVE_CURRENT_DISPATCH
 
- V3D_CSD_STATUS_HAVE_QUEUED_DISPATCH
 
- V3D_CSD_STATUS_NUM_ACTIVE_MASK
 
- V3D_CSD_STATUS_NUM_ACTIVE_SHIFT
 
- V3D_CSD_STATUS_NUM_COMPLETED_MASK
 
- V3D_CSD_STATUS_NUM_COMPLETED_SHIFT
 
- V3D_CT00RA0
 
- V3D_CT01RA0
 
- V3D_CT0CA
 
- V3D_CT0CS
 
- V3D_CT0EA
 
- V3D_CT0LC
 
- V3D_CT0PC
 
- V3D_CT1CA
 
- V3D_CT1CS
 
- V3D_CT1EA
 
- V3D_CT1LC
 
- V3D_CT1PC
 
- V3D_CTERR
 
- V3D_CTL_IDENT0
 
- V3D_CTL_IDENT1
 
- V3D_CTL_IDENT2
 
- V3D_CTL_INT_CLR
 
- V3D_CTL_INT_MSK_CLR
 
- V3D_CTL_INT_MSK_SET
 
- V3D_CTL_INT_MSK_STS
 
- V3D_CTL_INT_SET
 
- V3D_CTL_INT_STS
 
- V3D_CTL_L2CACTL
 
- V3D_CTL_L2TCACTL
 
- V3D_CTL_L2TFLEND
 
- V3D_CTL_L2TFLSTA
 
- V3D_CTL_MISCCFG
 
- V3D_CTL_MISCCFG_QRMAXCNT_MASK
 
- V3D_CTL_MISCCFG_QRMAXCNT_SHIFT
 
- V3D_CTL_SLCACTL
 
- V3D_CTMODE
 
- V3D_CTNCA
 
- V3D_CTNCS
 
- V3D_CTNEA
 
- V3D_CTNLC
 
- V3D_CTNPC
 
- V3D_CTNRA0
 
- V3D_CTRSTA
 
- V3D_CTRTSD
 
- V3D_CTRUN
 
- V3D_CTSEMA
 
- V3D_CTSUBS
 
- V3D_DBGE
 
- V3D_DRIVER_IRQS
 
- V3D_ERRSTAT
 
- V3D_ERR_FDBGB
 
- V3D_ERR_FDBGO
 
- V3D_ERR_FDBGR
 
- V3D_ERR_FDBGS
 
- V3D_ERR_FDBGS_DEPTHO_FIFO_IP_STALL
 
- V3D_ERR_FDBGS_EZREQ_FIFO_OP_VALID
 
- V3D_ERR_FDBGS_EZTEST_ANYQVALID
 
- V3D_ERR_FDBGS_EZTEST_IP_PRSTALL
 
- V3D_ERR_FDBGS_EZTEST_IP_QSTALL
 
- V3D_ERR_FDBGS_EZTEST_IP_VLFSTALL
 
- V3D_ERR_FDBGS_EZTEST_PASS
 
- V3D_ERR_FDBGS_EZTEST_QREADY
 
- V3D_ERR_FDBGS_EZTEST_QSTALL
 
- V3D_ERR_FDBGS_EZTEST_VLF_OKNOVALID
 
- V3D_ERR_FDBGS_INTERPZ_IP_STALL
 
- V3D_ERR_FDBGS_QXYF_FIFO_OP_LAST
 
- V3D_ERR_FDBGS_QXYF_FIFO_OP_VALID
 
- V3D_ERR_FDBGS_XYNRM_IP_STALL
 
- V3D_ERR_L2CARE
 
- V3D_ERR_STAT
 
- V3D_ERR_VCDE
 
- V3D_ERR_VCDI
 
- V3D_ERR_VCMBE
 
- V3D_ERR_VCMRE
 
- V3D_ERR_VDWE
 
- V3D_ERR_VPAEABB
 
- V3D_ERR_VPAEBRGL
 
- V3D_ERR_VPAERGS
 
- V3D_ERR_VPAERRGL
 
- V3D_ERR_VPMEAS
 
- V3D_ERR_VPMEFNA
 
- V3D_ERR_VPMERNA
 
- V3D_ERR_VPMERR
 
- V3D_ERR_VPMEWNA
 
- V3D_ERR_VPMEWR
 
- V3D_EXPECTED_IDENT0
 
- V3D_FDBGB
 
- V3D_FDBGO
 
- V3D_FDBGR
 
- V3D_FDBGS
 
- V3D_GCA_CACHE_CTRL
 
- V3D_GCA_CACHE_CTRL_FLUSH
 
- V3D_GCA_READ
 
- V3D_GCA_SAFE_SHUTDOWN
 
- V3D_GCA_SAFE_SHUTDOWN_ACK
 
- V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED
 
- V3D_GCA_SAFE_SHUTDOWN_EN
 
- V3D_GCA_WRITE
 
- V3D_GET_FIELD
 
- V3D_GMP_CFG
 
- V3D_GMP_CFG_LBURSTEN
 
- V3D_GMP_CFG_PGCRSEN
 
- V3D_GMP_CFG_PROT_ENABLE
 
- V3D_GMP_CFG_STOP_REQ
 
- V3D_GMP_CLEAR_LOAD
 
- V3D_GMP_PRESERVE_LOAD
 
- V3D_GMP_STATUS
 
- V3D_GMP_STATUS_CFG_BUSY
 
- V3D_GMP_STATUS_CNTOVF
 
- V3D_GMP_STATUS_GMPRST
 
- V3D_GMP_STATUS_INVPROT
 
- V3D_GMP_STATUS_RD_ACTIVE
 
- V3D_GMP_STATUS_RD_COUNT_MASK
 
- V3D_GMP_STATUS_RD_COUNT_SHIFT
 
- V3D_GMP_STATUS_VIO
 
- V3D_GMP_STATUS_WR_ACTIVE
 
- V3D_GMP_STATUS_WR_COUNT_MASK
 
- V3D_GMP_STATUS_WR_COUNT_SHIFT
 
- V3D_GMP_TABLE_ADDR
 
- V3D_GMP_VALID_LINES
 
- V3D_GMP_VIO_ADDR
 
- V3D_GMP_VIO_TYPE
 
- V3D_HUB_AXICFG
 
- V3D_HUB_AXICFG_MAX_LEN_MASK
 
- V3D_HUB_AXICFG_MAX_LEN_SHIFT
 
- V3D_HUB_IDENT0
 
- V3D_HUB_IDENT1
 
- V3D_HUB_IDENT1_NCORES_MASK
 
- V3D_HUB_IDENT1_NCORES_SHIFT
 
- V3D_HUB_IDENT1_NHOSTS_MASK
 
- V3D_HUB_IDENT1_NHOSTS_SHIFT
 
- V3D_HUB_IDENT1_REV_MASK
 
- V3D_HUB_IDENT1_REV_SHIFT
 
- V3D_HUB_IDENT1_TVER_MASK
 
- V3D_HUB_IDENT1_TVER_SHIFT
 
- V3D_HUB_IDENT1_WITH_L3C
 
- V3D_HUB_IDENT1_WITH_MSO
 
- V3D_HUB_IDENT1_WITH_TFU
 
- V3D_HUB_IDENT1_WITH_TSY
 
- V3D_HUB_IDENT2
 
- V3D_HUB_IDENT2_L3C_NKB_MASK
 
- V3D_HUB_IDENT2_L3C_NKB_SHIFT
 
- V3D_HUB_IDENT2_WITH_MMU
 
- V3D_HUB_IDENT3
 
- V3D_HUB_IDENT3_IPIDX_MASK
 
- V3D_HUB_IDENT3_IPIDX_SHIFT
 
- V3D_HUB_IDENT3_IPREV_MASK
 
- V3D_HUB_IDENT3_IPREV_SHIFT
 
- V3D_HUB_INT_CLR
 
- V3D_HUB_INT_MMU_CAP
 
- V3D_HUB_INT_MMU_PTI
 
- V3D_HUB_INT_MMU_WRV
 
- V3D_HUB_INT_MSK_CLR
 
- V3D_HUB_INT_MSK_SET
 
- V3D_HUB_INT_MSK_STS
 
- V3D_HUB_INT_MSO
 
- V3D_HUB_INT_SET
 
- V3D_HUB_INT_STS
 
- V3D_HUB_INT_TFUC
 
- V3D_HUB_INT_TFUF
 
- V3D_HUB_IRQS
 
- V3D_HUB_UIFCFG
 
- V3D_IDENT0
 
- V3D_IDENT0_VER_MASK
 
- V3D_IDENT0_VER_SHIFT
 
- V3D_IDENT1
 
- V3D_IDENT1_NSEM_MASK
 
- V3D_IDENT1_NSEM_SHIFT
 
- V3D_IDENT1_NSLC_MASK
 
- V3D_IDENT1_NSLC_SHIFT
 
- V3D_IDENT1_NTMU_MASK
 
- V3D_IDENT1_NTMU_SHIFT
 
- V3D_IDENT1_QUPS_MASK
 
- V3D_IDENT1_QUPS_SHIFT
 
- V3D_IDENT1_REV_MASK
 
- V3D_IDENT1_REV_SHIFT
 
- V3D_IDENT1_TUPS_MASK
 
- V3D_IDENT1_TUPS_SHIFT
 
- V3D_IDENT1_VPM_SIZE_MASK
 
- V3D_IDENT1_VPM_SIZE_SHIFT
 
- V3D_IDENT2
 
- V3D_IDENT2_BCG_INT
 
- V3D_INTCTL
 
- V3D_INTDIS
 
- V3D_INTENA
 
- V3D_INT_CSDDONE
 
- V3D_INT_FLDONE
 
- V3D_INT_FRDONE
 
- V3D_INT_GMPV
 
- V3D_INT_OUTOMEM
 
- V3D_INT_PCTR
 
- V3D_INT_QPU_MASK
 
- V3D_INT_QPU_SHIFT
 
- V3D_INT_SPILLUSE
 
- V3D_INT_TRFB
 
- V3D_L2CACTL
 
- V3D_L2CACTL_L2CCLR
 
- V3D_L2CACTL_L2CDIS
 
- V3D_L2CACTL_L2CENA
 
- V3D_L2TCACTL_FLM_CLEAN
 
- V3D_L2TCACTL_FLM_CLEAR
 
- V3D_L2TCACTL_FLM_FLUSH
 
- V3D_L2TCACTL_FLM_MASK
 
- V3D_L2TCACTL_FLM_SHIFT
 
- V3D_L2TCACTL_L2TFLS
 
- V3D_L2TCACTL_L2T_NO_WM
 
- V3D_L2TCACTL_TMUWCF
 
- V3D_MASK
 
- V3D_MAX_QUEUES
 
- V3D_MISCCFG_OVRTMUOUT
 
- V3D_MMUC_CONTROL
 
- V3D_MMUC_CONTROL_CLEAR
 
- V3D_MMUC_CONTROL_ENABLE
 
- V3D_MMUC_CONTROL_FLUSH
 
- V3D_MMUC_CONTROL_FLUSHING
 
- V3D_MMU_ADDR_CAP
 
- V3D_MMU_ADDR_CAP_ENABLE
 
- V3D_MMU_ADDR_CAP_MPAGE_MASK
 
- V3D_MMU_ADDR_CAP_MPAGE_SHIFT
 
- V3D_MMU_BYPASS_END
 
- V3D_MMU_BYPASS_START
 
- V3D_MMU_CTL
 
- V3D_MMU_CTL_CAP_EXCEEDED
 
- V3D_MMU_CTL_CAP_EXCEEDED_ABORT
 
- V3D_MMU_CTL_CAP_EXCEEDED_EXCEPTION
 
- V3D_MMU_CTL_CAP_EXCEEDED_INT
 
- V3D_MMU_CTL_ENABLE
 
- V3D_MMU_CTL_PT_INVALID
 
- V3D_MMU_CTL_PT_INVALID_ABORT
 
- V3D_MMU_CTL_PT_INVALID_ENABLE
 
- V3D_MMU_CTL_PT_INVALID_EXCEPTION
 
- V3D_MMU_CTL_PT_INVALID_INT
 
- V3D_MMU_CTL_TLB_CLEAR
 
- V3D_MMU_CTL_TLB_CLEARING
 
- V3D_MMU_CTL_TLB_STATS_CLEAR
 
- V3D_MMU_CTL_TLB_STATS_ENABLE
 
- V3D_MMU_CTL_WRITE_VIOLATION
 
- V3D_MMU_CTL_WRITE_VIOLATION_ABORT
 
- V3D_MMU_CTL_WRITE_VIOLATION_EXCEPTION
 
- V3D_MMU_CTL_WRITE_VIOLATION_INT
 
- V3D_MMU_DEBUG_INFO
 
- V3D_MMU_HIT
 
- V3D_MMU_ILLEGAL_ADDR
 
- V3D_MMU_ILLEGAL_ADDR_ENABLE
 
- V3D_MMU_MISSES
 
- V3D_MMU_PAGE_SHIFT
 
- V3D_MMU_PA_WIDTH_MASK
 
- V3D_MMU_PA_WIDTH_SHIFT
 
- V3D_MMU_PT_PA_BASE
 
- V3D_MMU_SHOOT_DOWN
 
- V3D_MMU_SHOOT_DOWN_PAGE_MASK
 
- V3D_MMU_SHOOT_DOWN_PAGE_SHIFT
 
- V3D_MMU_SHOOT_DOWN_SHOOT
 
- V3D_MMU_SHOOT_DOWN_SHOOTING
 
- V3D_MMU_STALLS
 
- V3D_MMU_VA_WIDTH_MASK
 
- V3D_MMU_VA_WIDTH_SHIFT
 
- V3D_MMU_VERSION_MASK
 
- V3D_MMU_VERSION_SHIFT
 
- V3D_MMU_VIO_ADDR
 
- V3D_MMU_VIO_ID
 
- V3D_PCS
 
- V3D_PCTR
 
- V3D_PCTRC
 
- V3D_PCTRE
 
- V3D_PCTRE_EN
 
- V3D_PCTRS
 
- V3D_PCTR_0_OVERFLOW
 
- V3D_PCTR_0_PCTR0
 
- V3D_PCTR_0_PCTR31
 
- V3D_PCTR_0_PCTRX
 
- V3D_PCTR_CYCLE_COUNT
 
- V3D_PCTR_S0_MASK
 
- V3D_PCTR_S0_SHIFT
 
- V3D_PCTR_S1_MASK
 
- V3D_PCTR_S1_SHIFT
 
- V3D_PCTR_S2_MASK
 
- V3D_PCTR_S2_SHIFT
 
- V3D_PCTR_S3_MASK
 
- V3D_PCTR_S3_SHIFT
 
- V3D_PTB_BPCA
 
- V3D_PTB_BPCS
 
- V3D_PTB_BPOA
 
- V3D_PTB_BPOS
 
- V3D_PTB_BXCF
 
- V3D_PTB_BXCF_CLIPDISA
 
- V3D_PTB_BXCF_RWORDERDISA
 
- V3D_PTE_SUPERPAGE
 
- V3D_PTE_VALID
 
- V3D_PTE_WRITEABLE
 
- V3D_READ
 
- V3D_REGS_H
 
- V3D_RENDER
 
- V3D_RFC
 
- V3D_RMACTIVE
 
- V3D_RMBUSY
 
- V3D_SCRATCH
 
- V3D_SET_FIELD
 
- V3D_SLCACTL
 
- V3D_SLCACTL_ICC_MASK
 
- V3D_SLCACTL_ICC_SHIFT
 
- V3D_SLCACTL_T0CC_MASK
 
- V3D_SLCACTL_T0CC_SHIFT
 
- V3D_SLCACTL_T1CC_MASK
 
- V3D_SLCACTL_T1CC_SHIFT
 
- V3D_SLCACTL_TDCCS_MASK
 
- V3D_SLCACTL_TDCCS_SHIFT
 
- V3D_SLCACTL_TVCCS_MASK
 
- V3D_SLCACTL_TVCCS_SHIFT
 
- V3D_SLCACTL_UCC_MASK
 
- V3D_SLCACTL_UCC_SHIFT
 
- V3D_SQCNTL
 
- V3D_SQRSV0
 
- V3D_SQRSV1
 
- V3D_SRQCS
 
- V3D_SRQPC
 
- V3D_SRQUA
 
- V3D_SRQUL
 
- V3D_TFU
 
- V3D_TFU_COEF0
 
- V3D_TFU_COEF0_USECOEF
 
- V3D_TFU_COEF1
 
- V3D_TFU_COEF2
 
- V3D_TFU_COEF3
 
- V3D_TFU_CRC
 
- V3D_TFU_CS
 
- V3D_TFU_CS_BUSY
 
- V3D_TFU_CS_CVTCT_MASK
 
- V3D_TFU_CS_CVTCT_SHIFT
 
- V3D_TFU_CS_NFREE_MASK
 
- V3D_TFU_CS_NFREE_SHIFT
 
- V3D_TFU_CS_TFURST
 
- V3D_TFU_ICA
 
- V3D_TFU_ICFG
 
- V3D_TFU_ICFG_IOC
 
- V3D_TFU_IIA
 
- V3D_TFU_IIS
 
- V3D_TFU_IOA
 
- V3D_TFU_IOS
 
- V3D_TFU_IUA
 
- V3D_TFU_SU
 
- V3D_TFU_SU_CRC
 
- V3D_TFU_SU_CRCCHAIN
 
- V3D_TFU_SU_FINTTHR_MASK
 
- V3D_TFU_SU_FINTTHR_SHIFT
 
- V3D_TFU_SU_THROTTLE_MASK
 
- V3D_TFU_SU_THROTTLE_SHIFT
 
- V3D_TOP_GR_BRIDGE_MAJOR_MASK
 
- V3D_TOP_GR_BRIDGE_MAJOR_SHIFT
 
- V3D_TOP_GR_BRIDGE_MINOR_MASK
 
- V3D_TOP_GR_BRIDGE_MINOR_SHIFT
 
- V3D_TOP_GR_BRIDGE_REVISION
 
- V3D_TOP_GR_BRIDGE_SW_INIT_0
 
- V3D_TOP_GR_BRIDGE_SW_INIT_0_V3D_CLK_108_SW_INIT
 
- V3D_TOP_GR_BRIDGE_SW_INIT_1
 
- V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT
 
- V3D_V3_PCTR_0_CLR
 
- V3D_V3_PCTR_0_EN
 
- V3D_V3_PCTR_0_EN_ENABLE
 
- V3D_V3_PCTR_0_PCTRS0
 
- V3D_V3_PCTR_0_PCTRS15
 
- V3D_V3_PCTR_0_PCTRSX
 
- V3D_V4_PCTR_0_CLR
 
- V3D_V4_PCTR_0_EN
 
- V3D_V4_PCTR_0_SRC_0_3
 
- V3D_V4_PCTR_0_SRC_28_31
 
- V3D_VPACNTL
 
- V3D_VPMBASE
 
- V3D_WRITE
 
- V3_0_0_10NM_OLD_TIMINGS_QUIRK
 
- V3_ALIGNMENT
 
- V3_CLOCK_RATE_MASK
 
- V3_CLOCK_RATE_SHIFT
 
- V3_CLOCK_SOURCE_MASK
 
- V3_CLOCK_STATUS_OFFSET
 
- V3_COMMAND_M_FBB_EN
 
- V3_COMMAND_M_IO_EN
 
- V3_COMMAND_M_MASTER_EN
 
- V3_COMMAND_M_MEM_EN
 
- V3_COMMAND_M_PAR_EN
 
- V3_COMMAND_M_SERR_EN
 
- V3_DESC
 
- V3_DMA_CSR0
 
- V3_DMA_CSR1
 
- V3_DMA_CTLB_ADR0
 
- V3_DMA_CTLB_ADR1
 
- V3_DMA_DELAY
 
- V3_DMA_LENGTH0
 
- V3_DMA_LENGTH1
 
- V3_DMA_LOCAL_ADR0
 
- V3_DMA_LOCAL_ADR1
 
- V3_DMA_PCI_ADR0
 
- V3_DMA_PCI_ADR1
 
- V3_ENABLE_OPT_IN_IFACE_A
 
- V3_ENABLE_OPT_IN_IFACE_B
 
- V3_ENABLE_OPT_OUT_IFACE_A
 
- V3_ENABLE_OPT_OUT_IFACE_B
 
- V3_FETCH_PCM_FRAMES
 
- V3_FIFO_CFG
 
- V3_FIFO_PRIORITY
 
- V3_FIFO_PRIO_LB_RD0_FLUSH_ANY
 
- V3_FIFO_PRIO_LB_RD0_FLUSH_AP1
 
- V3_FIFO_PRIO_LB_RD0_FLUSH_EOB
 
- V3_FIFO_PRIO_LB_RD1_FLUSH_ANY
 
- V3_FIFO_PRIO_LB_RD1_FLUSH_AP1
 
- V3_FIFO_PRIO_LB_RD1_FLUSH_EOB
 
- V3_FIFO_PRIO_LOCAL
 
- V3_FIFO_PRIO_PCI
 
- V3_FIFO_PRIO_PCI_RD0_FLUSH_ANY
 
- V3_FIFO_PRIO_PCI_RD0_FLUSH_AP1
 
- V3_FIFO_PRIO_PCI_RD0_FLUSH_EOB
 
- V3_FIFO_PRIO_PCI_RD1_FLUSH_ANY
 
- V3_FIFO_PRIO_PCI_RD1_FLUSH_AP1
 
- V3_FIFO_PRIO_PCI_RD1_FLUSH_EOB
 
- V3_FIFO_STAT
 
- V3_LB_BASE0
 
- V3_LB_BASE1
 
- V3_LB_BASE2
 
- V3_LB_BASE2_ADR_BASE
 
- V3_LB_BASE2_ENABLE
 
- V3_LB_BASE2_SWAP_AUTO
 
- V3_LB_BASE_ADR_BASE
 
- V3_LB_BASE_ADR_SIZE
 
- V3_LB_BASE_ADR_SIZE_128MB
 
- V3_LB_BASE_ADR_SIZE_16MB
 
- V3_LB_BASE_ADR_SIZE_1GB
 
- V3_LB_BASE_ADR_SIZE_1MB
 
- V3_LB_BASE_ADR_SIZE_256MB
 
- V3_LB_BASE_ADR_SIZE_2GB
 
- V3_LB_BASE_ADR_SIZE_2MB
 
- V3_LB_BASE_ADR_SIZE_32MB
 
- V3_LB_BASE_ADR_SIZE_4MB
 
- V3_LB_BASE_ADR_SIZE_512MB
 
- V3_LB_BASE_ADR_SIZE_64MB
 
- V3_LB_BASE_ADR_SIZE_8MB
 
- V3_LB_BASE_ENABLE
 
- V3_LB_BASE_PREFETCH
 
- V3_LB_BASE_SWAP
 
- V3_LB_CFG
 
- V3_LB_CFG_LB_BE_IMODE
 
- V3_LB_CFG_LB_BE_OMODE
 
- V3_LB_CFG_LB_ENDIAN
 
- V3_LB_CFG_LB_ERR_EN
 
- V3_LB_CFG_LB_FBB_DIS
 
- V3_LB_CFG_LB_LB_INT
 
- V3_LB_CFG_LB_PARK_EN
 
- V3_LB_CFG_LB_PPC_RDY
 
- V3_LB_CFG_LB_RDY_EN
 
- V3_LB_CFG_LB_RST
 
- V3_LB_CFG_LB_TO_1024_CYCLES
 
- V3_LB_CFG_LB_TO_256_CYCLES
 
- V3_LB_CFG_LB_TO_512_CYCLES
 
- V3_LB_CFG_LB_TO_64_CYCLES
 
- V3_LB_IMASK
 
- V3_LB_IO_BASE
 
- V3_LB_ISTAT
 
- V3_LB_ISTAT_DMA0
 
- V3_LB_ISTAT_DMA1
 
- V3_LB_ISTAT_I2O_QWR
 
- V3_LB_ISTAT_MAILBOX
 
- V3_LB_ISTAT_PCI_INT
 
- V3_LB_ISTAT_PCI_PERR
 
- V3_LB_ISTAT_PCI_RD
 
- V3_LB_ISTAT_PCI_WR
 
- V3_LB_MAIL_IERD
 
- V3_LB_MAIL_IEWR
 
- V3_LB_MAP0
 
- V3_LB_MAP1
 
- V3_LB_MAP2
 
- V3_LB_MAP2_MAP_ADR
 
- V3_LB_MAP_AD_LOW_EN
 
- V3_LB_MAP_MAP_ADR
 
- V3_LB_MAP_TYPE
 
- V3_LB_MAP_TYPE_CONFIG
 
- V3_LB_MAP_TYPE_IACK
 
- V3_LB_MAP_TYPE_IO
 
- V3_LB_MAP_TYPE_MEM
 
- V3_LB_MAP_TYPE_MEM_MULTIPLE
 
- V3_LB_SIZE
 
- V3_MAIL_DATA
 
- V3_MAIL_RD_STAT
 
- V3_MAIL_WR_STAT
 
- V3_NO_ADAT_OPT_IN_IFACE_A
 
- V3_NO_ADAT_OPT_IN_IFACE_B
 
- V3_NO_ADAT_OPT_OUT_IFACE_A
 
- V3_NO_ADAT_OPT_OUT_IFACE_B
 
- V3_OPT_IFACE_MODE_OFFSET
 
- V3_PCI_BASE0
 
- V3_PCI_BASE1
 
- V3_PCI_BASE_M_ADR_BASE
 
- V3_PCI_BASE_M_ADR_BASEL
 
- V3_PCI_BASE_M_IO
 
- V3_PCI_BASE_M_PREFETCH
 
- V3_PCI_BASE_M_TYPE
 
- V3_PCI_BPARAM
 
- V3_PCI_CC_REV
 
- V3_PCI_CFG
 
- V3_PCI_CFG_M_AD_LOW0
 
- V3_PCI_CFG_M_AD_LOW1
 
- V3_PCI_CFG_M_EN3V
 
- V3_PCI_CFG_M_I2O_EN
 
- V3_PCI_CFG_M_IO_DIS
 
- V3_PCI_CFG_M_IO_REG_DIS
 
- V3_PCI_CFG_M_RETRY_EN
 
- V3_PCI_CFG_M_RTYPE_SHIFT
 
- V3_PCI_CFG_M_WTYPE_SHIFT
 
- V3_PCI_CFG_TYPE_DEFAULT
 
- V3_PCI_CMD
 
- V3_PCI_DEVICE
 
- V3_PCI_HDR_CFG
 
- V3_PCI_INT_CFG
 
- V3_PCI_INT_STAT
 
- V3_PCI_IO_BASE
 
- V3_PCI_MAIL_IERD
 
- V3_PCI_MAIL_IEWR
 
- V3_PCI_MAP0
 
- V3_PCI_MAP1
 
- V3_PCI_MAP_M_ADR_SIZE
 
- V3_PCI_MAP_M_ENABLE
 
- V3_PCI_MAP_M_MAP_ADR
 
- V3_PCI_MAP_M_RD_POST_INH
 
- V3_PCI_MAP_M_REG_EN
 
- V3_PCI_MAP_M_ROM_SIZE
 
- V3_PCI_MAP_M_SWAP
 
- V3_PCI_ROM
 
- V3_PCI_STAT
 
- V3_PCI_STAT_M_ABORT_ERR
 
- V3_PCI_STAT_PAR_ERR
 
- V3_PCI_STAT_SYS_ERR
 
- V3_PCI_STAT_T_ABORT_ERR
 
- V3_PCI_SUB_ID
 
- V3_PCI_SUB_VENDOR
 
- V3_PCI_VENDOR
 
- V3_QBA_MAP
 
- V3_STATID
 
- V3_SYSTEM
 
- V3_SYSTEM_M_LOCK
 
- V3_SYSTEM_M_RST_OUT
 
- V3_SYSTEM_UNLOCK
 
- V4
 
- V4L2_ASYNC_H
 
- V4L2_ASYNC_MATCH_CUSTOM
 
- V4L2_ASYNC_MATCH_DEVNAME
 
- V4L2_ASYNC_MATCH_FWNODE
 
- V4L2_ASYNC_MATCH_I2C
 
- V4L2_AUDCAP_AVL
 
- V4L2_AUDCAP_STEREO
 
- V4L2_AUDMODE_AVL
 
- V4L2_AUTO_FOCUS_RANGE_AUTO
 
- V4L2_AUTO_FOCUS_RANGE_INFINITY
 
- V4L2_AUTO_FOCUS_RANGE_MACRO
 
- V4L2_AUTO_FOCUS_RANGE_NORMAL
 
- V4L2_AUTO_FOCUS_STATUS_BUSY
 
- V4L2_AUTO_FOCUS_STATUS_FAILED
 
- V4L2_AUTO_FOCUS_STATUS_IDLE
 
- V4L2_AUTO_FOCUS_STATUS_REACHED
 
- V4L2_BAND_MODULATION_AM
 
- V4L2_BAND_MODULATION_FM
 
- V4L2_BAND_MODULATION_VSB
 
- V4L2_BUFFER_MASK_FLAGS
 
- V4L2_BUFFER_OUT_FLAGS
 
- V4L2_BUF_CAP_SUPPORTS_DMABUF
 
- V4L2_BUF_CAP_SUPPORTS_MMAP
 
- V4L2_BUF_CAP_SUPPORTS_ORPHANED_BUFS
 
- V4L2_BUF_CAP_SUPPORTS_REQUESTS
 
- V4L2_BUF_CAP_SUPPORTS_USERPTR
 
- V4L2_BUF_FLAG_BFRAME
 
- V4L2_BUF_FLAG_DONE
 
- V4L2_BUF_FLAG_ERROR
 
- V4L2_BUF_FLAG_IN_REQUEST
 
- V4L2_BUF_FLAG_KEYFRAME
 
- V4L2_BUF_FLAG_LAST
 
- V4L2_BUF_FLAG_MAPPED
 
- V4L2_BUF_FLAG_NO_CACHE_CLEAN
 
- V4L2_BUF_FLAG_NO_CACHE_INVALIDATE
 
- V4L2_BUF_FLAG_PFRAME
 
- V4L2_BUF_FLAG_PREPARED
 
- V4L2_BUF_FLAG_QUEUED
 
- V4L2_BUF_FLAG_REQUEST_FD
 
- V4L2_BUF_FLAG_TIMECODE
 
- V4L2_BUF_FLAG_TIMESTAMP_COPY
 
- V4L2_BUF_FLAG_TIMESTAMP_MASK
 
- V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC
 
- V4L2_BUF_FLAG_TIMESTAMP_UNKNOWN
 
- V4L2_BUF_FLAG_TSTAMP_SRC_EOF
 
- V4L2_BUF_FLAG_TSTAMP_SRC_MASK
 
- V4L2_BUF_FLAG_TSTAMP_SRC_SOE
 
- V4L2_BUF_TYPE_META_CAPTURE
 
- V4L2_BUF_TYPE_META_OUTPUT
 
- V4L2_BUF_TYPE_PRIVATE
 
- V4L2_BUF_TYPE_SDR_CAPTURE
 
- V4L2_BUF_TYPE_SDR_OUTPUT
 
- V4L2_BUF_TYPE_SLICED_VBI_CAPTURE
 
- V4L2_BUF_TYPE_SLICED_VBI_OUTPUT
 
- V4L2_BUF_TYPE_VBI_CAPTURE
 
- V4L2_BUF_TYPE_VBI_OUTPUT
 
- V4L2_BUF_TYPE_VIDEO_CAPTURE
 
- V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE
 
- V4L2_BUF_TYPE_VIDEO_OUTPUT
 
- V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE
 
- V4L2_BUF_TYPE_VIDEO_OUTPUT_OVERLAY
 
- V4L2_BUF_TYPE_VIDEO_OVERLAY
 
- V4L2_CAP_ASYNCIO
 
- V4L2_CAP_AUDIO
 
- V4L2_CAP_DEVICE_CAPS
 
- V4L2_CAP_EXT_PIX_FORMAT
 
- V4L2_CAP_HW_FREQ_SEEK
 
- V4L2_CAP_META_CAPTURE
 
- V4L2_CAP_META_OUTPUT
 
- V4L2_CAP_MODULATOR
 
- V4L2_CAP_RADIO
 
- V4L2_CAP_RDS_CAPTURE
 
- V4L2_CAP_RDS_OUTPUT
 
- V4L2_CAP_READWRITE
 
- V4L2_CAP_SDR_CAPTURE
 
- V4L2_CAP_SDR_OUTPUT
 
- V4L2_CAP_SLICED_VBI_CAPTURE
 
- V4L2_CAP_SLICED_VBI_OUTPUT
 
- V4L2_CAP_STREAMING
 
- V4L2_CAP_TIMEPERFRAME
 
- V4L2_CAP_TOUCH
 
- V4L2_CAP_TUNER
 
- V4L2_CAP_VBI_CAPTURE
 
- V4L2_CAP_VBI_OUTPUT
 
- V4L2_CAP_VIDEO_CAPTURE
 
- V4L2_CAP_VIDEO_CAPTURE_MPLANE
 
- V4L2_CAP_VIDEO_M2M
 
- V4L2_CAP_VIDEO_M2M_MPLANE
 
- V4L2_CAP_VIDEO_OUTPUT
 
- V4L2_CAP_VIDEO_OUTPUT_MPLANE
 
- V4L2_CAP_VIDEO_OUTPUT_OVERLAY
 
- V4L2_CAP_VIDEO_OVERLAY
 
- V4L2_CHIP_FL_READABLE
 
- V4L2_CHIP_FL_WRITABLE
 
- V4L2_CHIP_MATCH_AC97
 
- V4L2_CHIP_MATCH_BRIDGE
 
- V4L2_CHIP_MATCH_HOST
 
- V4L2_CHIP_MATCH_I2C_ADDR
 
- V4L2_CHIP_MATCH_I2C_DRIVER
 
- V4L2_CHIP_MATCH_SUBDEV
 
- V4L2_CID_3A_LOCK
 
- V4L2_CID_ADV_FAST_SWITCH
 
- V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE
 
- V4L2_CID_ADV_RX_FREE_RUN_COLOR
 
- V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL
 
- V4L2_CID_AEC_LPF
 
- V4L2_CID_AEC_MAX_SHUTTER_WIDTH
 
- V4L2_CID_AEC_UPDATE_INTERVAL
 
- V4L2_CID_AEGC_DESIRED_BIN
 
- V4L2_CID_AGC_LPF
 
- V4L2_CID_AGC_UPDATE_INTERVAL
 
- V4L2_CID_ALPHA_COMPONENT
 
- V4L2_CID_ANALOGUE_GAIN
 
- V4L2_CID_AUDIO_BALANCE
 
- V4L2_CID_AUDIO_BASS
 
- V4L2_CID_AUDIO_COMPRESSION_ATTACK_TIME
 
- V4L2_CID_AUDIO_COMPRESSION_ENABLED
 
- V4L2_CID_AUDIO_COMPRESSION_GAIN
 
- V4L2_CID_AUDIO_COMPRESSION_RELEASE_TIME
 
- V4L2_CID_AUDIO_COMPRESSION_THRESHOLD
 
- V4L2_CID_AUDIO_LIMITER_DEVIATION
 
- V4L2_CID_AUDIO_LIMITER_ENABLED
 
- V4L2_CID_AUDIO_LIMITER_RELEASE_TIME
 
- V4L2_CID_AUDIO_LOUDNESS
 
- V4L2_CID_AUDIO_MUTE
 
- V4L2_CID_AUDIO_TREBLE
 
- V4L2_CID_AUDIO_VOLUME
 
- V4L2_CID_AUTOBRIGHTNESS
 
- V4L2_CID_AUTOGAIN
 
- V4L2_CID_AUTO_EXPOSURE_BIAS
 
- V4L2_CID_AUTO_FOCUS_RANGE
 
- V4L2_CID_AUTO_FOCUS_START
 
- V4L2_CID_AUTO_FOCUS_STATUS
 
- V4L2_CID_AUTO_FOCUS_STOP
 
- V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE
 
- V4L2_CID_AUTO_WHITE_BALANCE
 
- V4L2_CID_BACKLIGHT_COMPENSATION
 
- V4L2_CID_BAND_STOP_FILTER
 
- V4L2_CID_BASE
 
- V4L2_CID_BG_COLOR
 
- V4L2_CID_BLACK_LEVEL
 
- V4L2_CID_BLACK_LEVEL_AUTO
 
- V4L2_CID_BLACK_LEVEL_CALIBRATE
 
- V4L2_CID_BLACK_LEVEL_OFFSET
 
- V4L2_CID_BLC_ANALOG_OFFSET
 
- V4L2_CID_BLC_AUTO
 
- V4L2_CID_BLC_DIGITAL_OFFSET
 
- V4L2_CID_BLC_TARGET_LEVEL
 
- V4L2_CID_BLUE_BALANCE
 
- V4L2_CID_BLUE_GAIN
 
- V4L2_CID_BRIGHTNESS
 
- V4L2_CID_CAMERA_CLASS
 
- V4L2_CID_CAMERA_CLASS_BASE
 
- V4L2_CID_CHROMA_AGC
 
- V4L2_CID_CHROMA_GAIN
 
- V4L2_CID_COLORFX
 
- V4L2_CID_COLORFX_CBCR
 
- V4L2_CID_COLOR_KILLER
 
- V4L2_CID_CONTRAST
 
- V4L2_CID_DEINTERLACING_MODE
 
- V4L2_CID_DETECT_CLASS
 
- V4L2_CID_DETECT_CLASS_BASE
 
- V4L2_CID_DETECT_MD_GLOBAL_THRESHOLD
 
- V4L2_CID_DETECT_MD_MODE
 
- V4L2_CID_DETECT_MD_REGION_GRID
 
- V4L2_CID_DETECT_MD_THRESHOLD_GRID
 
- V4L2_CID_DIGITAL_GAIN
 
- V4L2_CID_DO_WHITE_BALANCE
 
- V4L2_CID_DV_CLASS
 
- V4L2_CID_DV_CLASS_BASE
 
- V4L2_CID_DV_RX_IT_CONTENT_TYPE
 
- V4L2_CID_DV_RX_POWER_PRESENT
 
- V4L2_CID_DV_RX_RGB_RANGE
 
- V4L2_CID_DV_TX_EDID_PRESENT
 
- V4L2_CID_DV_TX_HOTPLUG
 
- V4L2_CID_DV_TX_IT_CONTENT_TYPE
 
- V4L2_CID_DV_TX_MODE
 
- V4L2_CID_DV_TX_RGB_RANGE
 
- V4L2_CID_DV_TX_RXSENSE
 
- V4L2_CID_EXPOSURE
 
- V4L2_CID_EXPOSURE_ABSOLUTE
 
- V4L2_CID_EXPOSURE_AUTO
 
- V4L2_CID_EXPOSURE_AUTO_PRIORITY
 
- V4L2_CID_EXPOSURE_METERING
 
- V4L2_CID_FLASH_CHARGE
 
- V4L2_CID_FLASH_CLASS
 
- V4L2_CID_FLASH_CLASS_BASE
 
- V4L2_CID_FLASH_FAULT
 
- V4L2_CID_FLASH_INDICATOR_INTENSITY
 
- V4L2_CID_FLASH_INTENSITY
 
- V4L2_CID_FLASH_LED_MODE
 
- V4L2_CID_FLASH_READY
 
- V4L2_CID_FLASH_STROBE
 
- V4L2_CID_FLASH_STROBE_SOURCE
 
- V4L2_CID_FLASH_STROBE_STATUS
 
- V4L2_CID_FLASH_STROBE_STOP
 
- V4L2_CID_FLASH_TIMEOUT
 
- V4L2_CID_FLASH_TORCH_INTENSITY
 
- V4L2_CID_FM_RX_CLASS
 
- V4L2_CID_FM_RX_CLASS_BASE
 
- V4L2_CID_FM_TX_CLASS
 
- V4L2_CID_FM_TX_CLASS_BASE
 
- V4L2_CID_FOCUS_ABSOLUTE
 
- V4L2_CID_FOCUS_AUTO
 
- V4L2_CID_FOCUS_RELATIVE
 
- V4L2_CID_FWHT_I_FRAME_QP
 
- V4L2_CID_FWHT_P_FRAME_QP
 
- V4L2_CID_GAIN
 
- V4L2_CID_GAIN_BLUE
 
- V4L2_CID_GAIN_GREEN_BLUE
 
- V4L2_CID_GAIN_GREEN_RED
 
- V4L2_CID_GAIN_RED
 
- V4L2_CID_GAMMA
 
- V4L2_CID_GREEN_GAIN
 
- V4L2_CID_HBLANK
 
- V4L2_CID_HFLIP
 
- V4L2_CID_HUE
 
- V4L2_CID_HUE_AUTO
 
- V4L2_CID_ILLUMINATORS_1
 
- V4L2_CID_ILLUMINATORS_2
 
- V4L2_CID_IMAGE_PROC_CLASS
 
- V4L2_CID_IMAGE_PROC_CLASS_BASE
 
- V4L2_CID_IMAGE_SOURCE_CLASS
 
- V4L2_CID_IMAGE_SOURCE_CLASS_BASE
 
- V4L2_CID_IMAGE_STABILIZATION
 
- V4L2_CID_IMX_FIM_ENABLE
 
- V4L2_CID_IMX_FIM_ICAP_CHANNEL
 
- V4L2_CID_IMX_FIM_ICAP_EDGE
 
- V4L2_CID_IMX_FIM_NUM
 
- V4L2_CID_IMX_FIM_NUM_SKIP
 
- V4L2_CID_IMX_FIM_TOLERANCE_MAX
 
- V4L2_CID_IMX_FIM_TOLERANCE_MIN
 
- V4L2_CID_INTEL_IPU3_BASE
 
- V4L2_CID_INTEL_IPU3_MODE
 
- V4L2_CID_IRIS_ABSOLUTE
 
- V4L2_CID_IRIS_RELATIVE
 
- V4L2_CID_ISO_SENSITIVITY
 
- V4L2_CID_ISO_SENSITIVITY_AUTO
 
- V4L2_CID_JPEG_ACTIVE_MARKER
 
- V4L2_CID_JPEG_CHROMA_SUBSAMPLING
 
- V4L2_CID_JPEG_CLASS
 
- V4L2_CID_JPEG_CLASS_BASE
 
- V4L2_CID_JPEG_COMPRESSION_QUALITY
 
- V4L2_CID_JPEG_RESTART_INTERVAL
 
- V4L2_CID_LASTP1
 
- V4L2_CID_LINK_FREQ
 
- V4L2_CID_MAX2175_HSLS
 
- V4L2_CID_MAX2175_I2S_ENABLE
 
- V4L2_CID_MAX2175_RX_MODE
 
- V4L2_CID_MAX_CTRLS
 
- V4L2_CID_MB_THRESHOLD0
 
- V4L2_CID_MB_THRESHOLD1
 
- V4L2_CID_MB_THRESHOLD2
 
- V4L2_CID_MB_THRESHOLD3
 
- V4L2_CID_MEYE_AGC
 
- V4L2_CID_MEYE_FRAMERATE
 
- V4L2_CID_MEYE_PICTURE
 
- V4L2_CID_MIN_BUFFERS_FOR_CAPTURE
 
- V4L2_CID_MIN_BUFFERS_FOR_OUTPUT
 
- V4L2_CID_MOTION_THRESHOLD0
 
- V4L2_CID_MOTION_THRESHOLD1
 
- V4L2_CID_MOTION_THRESHOLD2
 
- V4L2_CID_MOTION_THRESHOLD3
 
- V4L2_CID_MOTION_TRACE
 
- V4L2_CID_MPEG_AUDIO_AAC_BITRATE
 
- V4L2_CID_MPEG_AUDIO_AC3_BITRATE
 
- V4L2_CID_MPEG_AUDIO_CRC
 
- V4L2_CID_MPEG_AUDIO_DEC_MULTILINGUAL_PLAYBACK
 
- V4L2_CID_MPEG_AUDIO_DEC_PLAYBACK
 
- V4L2_CID_MPEG_AUDIO_EMPHASIS
 
- V4L2_CID_MPEG_AUDIO_ENCODING
 
- V4L2_CID_MPEG_AUDIO_L1_BITRATE
 
- V4L2_CID_MPEG_AUDIO_L2_BITRATE
 
- V4L2_CID_MPEG_AUDIO_L3_BITRATE
 
- V4L2_CID_MPEG_AUDIO_MODE
 
- V4L2_CID_MPEG_AUDIO_MODE_EXTENSION
 
- V4L2_CID_MPEG_AUDIO_MUTE
 
- V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ
 
- V4L2_CID_MPEG_BASE
 
- V4L2_CID_MPEG_CLASS
 
- V4L2_CID_MPEG_CX2341X_BASE
 
- V4L2_CID_MPEG_CX2341X_STREAM_INSERT_NAV_PACKETS
 
- V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM
 
- V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP
 
- V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE
 
- V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM
 
- V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP
 
- V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE
 
- V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE
 
- V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER
 
- V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE
 
- V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER
 
- V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE
 
- V4L2_CID_MPEG_MFC51_BASE
 
- V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY
 
- V4L2_CID_MPEG_MFC51_VIDEO_DECODER_H264_DISPLAY_DELAY_ENABLE
 
- V4L2_CID_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE
 
- V4L2_CID_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE
 
- V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_ACTIVITY
 
- V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_DARK
 
- V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_SMOOTH
 
- V4L2_CID_MPEG_MFC51_VIDEO_H264_ADAPTIVE_RC_STATIC
 
- V4L2_CID_MPEG_MFC51_VIDEO_H264_NUM_REF_PIC_FOR_P
 
- V4L2_CID_MPEG_MFC51_VIDEO_PADDING
 
- V4L2_CID_MPEG_MFC51_VIDEO_PADDING_YUV
 
- V4L2_CID_MPEG_MFC51_VIDEO_RC_FIXED_TARGET_BIT
 
- V4L2_CID_MPEG_MFC51_VIDEO_RC_REACTION_COEFF
 
- V4L2_CID_MPEG_STREAM_PES_ID_AUDIO
 
- V4L2_CID_MPEG_STREAM_PES_ID_VIDEO
 
- V4L2_CID_MPEG_STREAM_PID_AUDIO
 
- V4L2_CID_MPEG_STREAM_PID_PCR
 
- V4L2_CID_MPEG_STREAM_PID_PMT
 
- V4L2_CID_MPEG_STREAM_PID_VIDEO
 
- V4L2_CID_MPEG_STREAM_TYPE
 
- V4L2_CID_MPEG_STREAM_VBI_FMT
 
- V4L2_CID_MPEG_VIDEO_ASPECT
 
- V4L2_CID_MPEG_VIDEO_BITRATE
 
- V4L2_CID_MPEG_VIDEO_BITRATE_MODE
 
- V4L2_CID_MPEG_VIDEO_BITRATE_PEAK
 
- V4L2_CID_MPEG_VIDEO_B_FRAMES
 
- V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB
 
- V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER
 
- V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE
 
- V4L2_CID_MPEG_VIDEO_DEC_FRAME
 
- V4L2_CID_MPEG_VIDEO_DEC_PTS
 
- V4L2_CID_MPEG_VIDEO_ENCODING
 
- V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME
 
- V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE
 
- V4L2_CID_MPEG_VIDEO_FWHT_PARAMS
 
- V4L2_CID_MPEG_VIDEO_GOP_CLOSURE
 
- V4L2_CID_MPEG_VIDEO_GOP_SIZE
 
- V4L2_CID_MPEG_VIDEO_H263_B_FRAME_QP
 
- V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP
 
- V4L2_CID_MPEG_VIDEO_H263_MAX_QP
 
- V4L2_CID_MPEG_VIDEO_H263_MIN_QP
 
- V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP
 
- V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM
 
- V4L2_CID_MPEG_VIDEO_H264_ASO
 
- V4L2_CID_MPEG_VIDEO_H264_ASO_SLICE_ORDER
 
- V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP
 
- V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET
 
- V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION
 
- V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE
 
- V4L2_CID_MPEG_VIDEO_H264_DECODE_MODE
 
- V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAMS
 
- V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE
 
- V4L2_CID_MPEG_VIDEO_H264_FMO
 
- V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_DIRECTION
 
- V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_RATE
 
- V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE
 
- V4L2_CID_MPEG_VIDEO_H264_FMO_RUN_LENGTH
 
- V4L2_CID_MPEG_VIDEO_H264_FMO_SLICE_GROUP
 
- V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING
 
- V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER
 
- V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP
 
- V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_TYPE
 
- V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP
 
- V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP
 
- V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP
 
- V4L2_CID_MPEG_VIDEO_H264_I_PERIOD
 
- V4L2_CID_MPEG_VIDEO_H264_LEVEL
 
- V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA
 
- V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA
 
- V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE
 
- V4L2_CID_MPEG_VIDEO_H264_MAX_QP
 
- V4L2_CID_MPEG_VIDEO_H264_MIN_QP
 
- V4L2_CID_MPEG_VIDEO_H264_PPS
 
- V4L2_CID_MPEG_VIDEO_H264_PROFILE
 
- V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP
 
- V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP
 
- V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP
 
- V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX
 
- V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE
 
- V4L2_CID_MPEG_VIDEO_H264_SEI_FP_CURRENT_FRAME_0
 
- V4L2_CID_MPEG_VIDEO_H264_SEI_FRAME_PACKING
 
- V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAMS
 
- V4L2_CID_MPEG_VIDEO_H264_SPS
 
- V4L2_CID_MPEG_VIDEO_H264_START_CODE
 
- V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT
 
- V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH
 
- V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE
 
- V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC
 
- V4L2_CID_MPEG_VIDEO_HEADER_MODE
 
- V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP
 
- V4L2_CID_MPEG_VIDEO_HEVC_CONST_INTRA_PRED
 
- V4L2_CID_MPEG_VIDEO_HEVC_FRAME_RATE_RESOLUTION
 
- V4L2_CID_MPEG_VIDEO_HEVC_GENERAL_PB
 
- V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L0_BR
 
- V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L0_QP
 
- V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L1_BR
 
- V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L1_QP
 
- V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L2_BR
 
- V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L2_QP
 
- V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L3_BR
 
- V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L3_QP
 
- V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L4_BR
 
- V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L4_QP
 
- V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L5_BR
 
- V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L5_QP
 
- V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L6_BR
 
- V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_L6_QP
 
- V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_LAYER
 
- V4L2_CID_MPEG_VIDEO_HEVC_HIER_CODING_TYPE
 
- V4L2_CID_MPEG_VIDEO_HEVC_HIER_QP
 
- V4L2_CID_MPEG_VIDEO_HEVC_INTRA_PU_SPLIT
 
- V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP
 
- V4L2_CID_MPEG_VIDEO_HEVC_LEVEL
 
- V4L2_CID_MPEG_VIDEO_HEVC_LF_BETA_OFFSET_DIV2
 
- V4L2_CID_MPEG_VIDEO_HEVC_LF_TC_OFFSET_DIV2
 
- V4L2_CID_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE
 
- V4L2_CID_MPEG_VIDEO_HEVC_LOSSLESS_CU
 
- V4L2_CID_MPEG_VIDEO_HEVC_MAX_NUM_MERGE_MV_MINUS1
 
- V4L2_CID_MPEG_VIDEO_HEVC_MAX_PARTITION_DEPTH
 
- V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP
 
- V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP
 
- V4L2_CID_MPEG_VIDEO_HEVC_PROFILE
 
- V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP
 
- V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_PERIOD
 
- V4L2_CID_MPEG_VIDEO_HEVC_REFRESH_TYPE
 
- V4L2_CID_MPEG_VIDEO_HEVC_SIZE_OF_LENGTH_FIELD
 
- V4L2_CID_MPEG_VIDEO_HEVC_STRONG_SMOOTHING
 
- V4L2_CID_MPEG_VIDEO_HEVC_TEMPORAL_ID
 
- V4L2_CID_MPEG_VIDEO_HEVC_TIER
 
- V4L2_CID_MPEG_VIDEO_HEVC_TMV_PREDICTION
 
- V4L2_CID_MPEG_VIDEO_HEVC_WAVEFRONT
 
- V4L2_CID_MPEG_VIDEO_HEVC_WITHOUT_STARTCODE
 
- V4L2_CID_MPEG_VIDEO_MAX_REF_PIC
 
- V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE
 
- V4L2_CID_MPEG_VIDEO_MPEG2_LEVEL
 
- V4L2_CID_MPEG_VIDEO_MPEG2_PROFILE
 
- V4L2_CID_MPEG_VIDEO_MPEG2_QUANTIZATION
 
- V4L2_CID_MPEG_VIDEO_MPEG2_SLICE_PARAMS
 
- V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP
 
- V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP
 
- V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL
 
- V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP
 
- V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP
 
- V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE
 
- V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP
 
- V4L2_CID_MPEG_VIDEO_MPEG4_QPEL
 
- V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES
 
- V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB
 
- V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE
 
- V4L2_CID_MPEG_VIDEO_MUTE
 
- V4L2_CID_MPEG_VIDEO_MUTE_YUV
 
- V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE
 
- V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE
 
- V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR
 
- V4L2_CID_MPEG_VIDEO_PULLDOWN
 
- V4L2_CID_MPEG_VIDEO_REF_NUMBER_FOR_PFRAMES
 
- V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER
 
- V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION
 
- V4L2_CID_MPEG_VIDEO_VBV_DELAY
 
- V4L2_CID_MPEG_VIDEO_VBV_SIZE
 
- V4L2_CID_MPEG_VIDEO_VP8_FRAME_HEADER
 
- V4L2_CID_MPEG_VIDEO_VP8_PROFILE
 
- V4L2_CID_MPEG_VIDEO_VP9_PROFILE
 
- V4L2_CID_MPEG_VIDEO_VPX_1_PARTITION
 
- V4L2_CID_MPEG_VIDEO_VPX_1_REF_FRAME
 
- V4L2_CID_MPEG_VIDEO_VPX_2_PARTITIONS
 
- V4L2_CID_MPEG_VIDEO_VPX_2_REF_FRAME
 
- V4L2_CID_MPEG_VIDEO_VPX_3_REF_FRAME
 
- V4L2_CID_MPEG_VIDEO_VPX_4_PARTITIONS
 
- V4L2_CID_MPEG_VIDEO_VPX_8_PARTITIONS
 
- V4L2_CID_MPEG_VIDEO_VPX_FILTER_LEVEL
 
- V4L2_CID_MPEG_VIDEO_VPX_FILTER_SHARPNESS
 
- V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_REF_PERIOD
 
- V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_SEL
 
- V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_USE_PREV
 
- V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_USE_REF_PERIOD
 
- V4L2_CID_MPEG_VIDEO_VPX_IMD_DISABLE_4X4
 
- V4L2_CID_MPEG_VIDEO_VPX_I_FRAME_QP
 
- V4L2_CID_MPEG_VIDEO_VPX_MAX_QP
 
- V4L2_CID_MPEG_VIDEO_VPX_MIN_QP
 
- V4L2_CID_MPEG_VIDEO_VPX_NUM_PARTITIONS
 
- V4L2_CID_MPEG_VIDEO_VPX_NUM_REF_FRAMES
 
- V4L2_CID_MPEG_VIDEO_VPX_PROFILE
 
- V4L2_CID_MPEG_VIDEO_VPX_P_FRAME_QP
 
- V4L2_CID_OSD_TEXT
 
- V4L2_CID_PAN_ABSOLUTE
 
- V4L2_CID_PAN_RELATIVE
 
- V4L2_CID_PAN_RESET
 
- V4L2_CID_PAN_SPEED
 
- V4L2_CID_PILOT_TONE_DEVIATION
 
- V4L2_CID_PILOT_TONE_ENABLED
 
- V4L2_CID_PILOT_TONE_FREQUENCY
 
- V4L2_CID_PIXEL_RATE
 
- V4L2_CID_PIXEL_THRESHOLD0
 
- V4L2_CID_PIXEL_THRESHOLD1
 
- V4L2_CID_PIXEL_THRESHOLD2
 
- V4L2_CID_PIXEL_THRESHOLD3
 
- V4L2_CID_POWER_LINE_FREQUENCY
 
- V4L2_CID_POWER_LINE_FREQUENCY_50HZ
 
- V4L2_CID_POWER_LINE_FREQUENCY_60HZ
 
- V4L2_CID_POWER_LINE_FREQUENCY_AUTO
 
- V4L2_CID_POWER_LINE_FREQUENCY_DISABLED
 
- V4L2_CID_PRIVACY
 
- V4L2_CID_PRIVATE_AGC_CRUSH
 
- V4L2_CID_PRIVATE_AUTOMUTE
 
- V4L2_CID_PRIVATE_BASE
 
- V4L2_CID_PRIVATE_COMBFILTER
 
- V4L2_CID_PRIVATE_CORING
 
- V4L2_CID_PRIVATE_FULL_LUMA_RANGE
 
- V4L2_CID_PRIVATE_INVERT
 
- V4L2_CID_PRIVATE_LUMAFILTER
 
- V4L2_CID_PRIVATE_UV_RATIO
 
- V4L2_CID_PRIVATE_VCR_HACK
 
- V4L2_CID_PRIVATE_WHITECRUSH_LOWER
 
- V4L2_CID_PRIVATE_WHITECRUSH_UPPER
 
- V4L2_CID_PRIVATE_Y_EVEN
 
- V4L2_CID_PRIVATE_Y_ODD
 
- V4L2_CID_RDS_RECEPTION
 
- V4L2_CID_RDS_RX_MUSIC_SPEECH
 
- V4L2_CID_RDS_RX_PS_NAME
 
- V4L2_CID_RDS_RX_PTY
 
- V4L2_CID_RDS_RX_RADIO_TEXT
 
- V4L2_CID_RDS_RX_TRAFFIC_ANNOUNCEMENT
 
- V4L2_CID_RDS_RX_TRAFFIC_PROGRAM
 
- V4L2_CID_RDS_TX_ALT_FREQS
 
- V4L2_CID_RDS_TX_ALT_FREQS_ENABLE
 
- V4L2_CID_RDS_TX_ARTIFICIAL_HEAD
 
- V4L2_CID_RDS_TX_COMPRESSED
 
- V4L2_CID_RDS_TX_DEVIATION
 
- V4L2_CID_RDS_TX_DYNAMIC_PTY
 
- V4L2_CID_RDS_TX_MONO_STEREO
 
- V4L2_CID_RDS_TX_MUSIC_SPEECH
 
- V4L2_CID_RDS_TX_PI
 
- V4L2_CID_RDS_TX_PS_NAME
 
- V4L2_CID_RDS_TX_PTY
 
- V4L2_CID_RDS_TX_RADIO_TEXT
 
- V4L2_CID_RDS_TX_TRAFFIC_ANNOUNCEMENT
 
- V4L2_CID_RDS_TX_TRAFFIC_PROGRAM
 
- V4L2_CID_RED_BALANCE
 
- V4L2_CID_RED_GAIN
 
- V4L2_CID_RF_TUNER_BANDWIDTH
 
- V4L2_CID_RF_TUNER_BANDWIDTH_AUTO
 
- V4L2_CID_RF_TUNER_CLASS
 
- V4L2_CID_RF_TUNER_CLASS_BASE
 
- V4L2_CID_RF_TUNER_IF_GAIN
 
- V4L2_CID_RF_TUNER_IF_GAIN_AUTO
 
- V4L2_CID_RF_TUNER_LNA_GAIN
 
- V4L2_CID_RF_TUNER_LNA_GAIN_AUTO
 
- V4L2_CID_RF_TUNER_MIXER_GAIN
 
- V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO
 
- V4L2_CID_RF_TUNER_PLL_LOCK
 
- V4L2_CID_RF_TUNER_RF_GAIN
 
- V4L2_CID_ROTATE
 
- V4L2_CID_S2255_COLORFILTER
 
- V4L2_CID_SATURATION
 
- V4L2_CID_SCENE_MODE
 
- V4L2_CID_SHARPNESS
 
- V4L2_CID_SI476X_DIVERSITY_MODE
 
- V4L2_CID_SI476X_HARMONICS_COUNT
 
- V4L2_CID_SI476X_INTERCHIP_LINK
 
- V4L2_CID_SI476X_MAX_TUNE_ERROR
 
- V4L2_CID_SI476X_RSSI_THRESHOLD
 
- V4L2_CID_SI476X_SNR_THRESHOLD
 
- V4L2_CID_TEST_PATTERN
 
- V4L2_CID_TEST_PATTERN_BLUE
 
- V4L2_CID_TEST_PATTERN_COLOR
 
- V4L2_CID_TEST_PATTERN_GREENB
 
- V4L2_CID_TEST_PATTERN_GREENR
 
- V4L2_CID_TEST_PATTERN_RED
 
- V4L2_CID_TILT_ABSOLUTE
 
- V4L2_CID_TILT_RELATIVE
 
- V4L2_CID_TILT_RESET
 
- V4L2_CID_TILT_SPEED
 
- V4L2_CID_TRANS_NUM_BUFS
 
- V4L2_CID_TRANS_TIME_MSEC
 
- V4L2_CID_TUNE_ANTENNA_CAPACITOR
 
- V4L2_CID_TUNE_DEEMPHASIS
 
- V4L2_CID_TUNE_POWER_LEVEL
 
- V4L2_CID_TUNE_PREEMPHASIS
 
- V4L2_CID_USER_ADV7180_BASE
 
- V4L2_CID_USER_BASE
 
- V4L2_CID_USER_BTTV_BASE
 
- V4L2_CID_USER_CLASS
 
- V4L2_CID_USER_IMX_BASE
 
- V4L2_CID_USER_MAX217X_BASE
 
- V4L2_CID_USER_MEYE_BASE
 
- V4L2_CID_USER_S2255_BASE
 
- V4L2_CID_USER_SAA7134_BASE
 
- V4L2_CID_USER_SI476X_BASE
 
- V4L2_CID_USER_TC358743_BASE
 
- V4L2_CID_USER_TI_VPE_BASE
 
- V4L2_CID_VBLANK
 
- V4L2_CID_VFLIP
 
- V4L2_CID_VPE_BUFS_PER_JOB
 
- V4L2_CID_VSP1_CLU_MODE
 
- V4L2_CID_VSP1_CLU_MODE_2D
 
- V4L2_CID_VSP1_CLU_MODE_3D
 
- V4L2_CID_VSP1_CLU_TABLE
 
- V4L2_CID_VSP1_HGO_MAX_RGB
 
- V4L2_CID_VSP1_HGO_NUM_BINS
 
- V4L2_CID_VSP1_HGT_HUE_AREAS
 
- V4L2_CID_VSP1_LUT_TABLE
 
- V4L2_CID_VSP1_SRU_INTENSITY
 
- V4L2_CID_WHITENESS
 
- V4L2_CID_WHITE_BALANCE_TEMPERATURE
 
- V4L2_CID_WIDE_DYNAMIC_RANGE
 
- V4L2_CID_XILINX_BASE
 
- V4L2_CID_XILINX_OFFSET
 
- V4L2_CID_XILINX_TPG
 
- V4L2_CID_XILINX_TPG_BOX_COLOR
 
- V4L2_CID_XILINX_TPG_BOX_SIZE
 
- V4L2_CID_XILINX_TPG_COLOR_MASK
 
- V4L2_CID_XILINX_TPG_CROSS_HAIRS
 
- V4L2_CID_XILINX_TPG_CROSS_HAIR_COLUMN
 
- V4L2_CID_XILINX_TPG_CROSS_HAIR_ROW
 
- V4L2_CID_XILINX_TPG_MOTION
 
- V4L2_CID_XILINX_TPG_MOTION_SPEED
 
- V4L2_CID_XILINX_TPG_MOVING_BOX
 
- V4L2_CID_XILINX_TPG_NOISE
 
- V4L2_CID_XILINX_TPG_NOISE_GAIN
 
- V4L2_CID_XILINX_TPG_STUCK_PIXEL
 
- V4L2_CID_XILINX_TPG_STUCK_PIXEL_THRESH
 
- V4L2_CID_XILINX_TPG_ZPLATE_HOR_SPEED
 
- V4L2_CID_XILINX_TPG_ZPLATE_HOR_START
 
- V4L2_CID_XILINX_TPG_ZPLATE_VER_SPEED
 
- V4L2_CID_XILINX_TPG_ZPLATE_VER_START
 
- V4L2_CID_ZOOM_ABSOLUTE
 
- V4L2_CID_ZOOM_CONTINUOUS
 
- V4L2_CID_ZOOM_RELATIVE
 
- V4L2_CLK_NAME_SIZE
 
- V4L2_CMP_MAX_INPUT
 
- V4L2_COLORFX_ANTIQUE
 
- V4L2_COLORFX_AQUA
 
- V4L2_COLORFX_ART_FREEZE
 
- V4L2_COLORFX_BW
 
- V4L2_COLORFX_EMBOSS
 
- V4L2_COLORFX_GRASS_GREEN
 
- V4L2_COLORFX_NEGATIVE
 
- V4L2_COLORFX_NONE
 
- V4L2_COLORFX_SEPIA
 
- V4L2_COLORFX_SET_CBCR
 
- V4L2_COLORFX_SILHOUETTE
 
- V4L2_COLORFX_SKETCH
 
- V4L2_COLORFX_SKIN_WHITEN
 
- V4L2_COLORFX_SKY_BLUE
 
- V4L2_COLORFX_SOLARIZATION
 
- V4L2_COLORFX_VIVID
 
- V4L2_COLORSPACE_470_SYSTEM_BG
 
- V4L2_COLORSPACE_470_SYSTEM_M
 
- V4L2_COLORSPACE_ADOBERGB
 
- V4L2_COLORSPACE_BT2020
 
- V4L2_COLORSPACE_BT878
 
- V4L2_COLORSPACE_DCI_P3
 
- V4L2_COLORSPACE_DEFAULT
 
- V4L2_COLORSPACE_JPEG
 
- V4L2_COLORSPACE_OPRGB
 
- V4L2_COLORSPACE_RAW
 
- V4L2_COLORSPACE_REC709
 
- V4L2_COLORSPACE_SMPTE170M
 
- V4L2_COLORSPACE_SMPTE240M
 
- V4L2_COLORSPACE_SRGB
 
- V4L2_COMMON_H_
 
- V4L2_CTRL_CLASS_CAMERA
 
- V4L2_CTRL_CLASS_DETECT
 
- V4L2_CTRL_CLASS_DV
 
- V4L2_CTRL_CLASS_FLASH
 
- V4L2_CTRL_CLASS_FM_RX
 
- V4L2_CTRL_CLASS_FM_TX
 
- V4L2_CTRL_CLASS_IMAGE_PROC
 
- V4L2_CTRL_CLASS_IMAGE_SOURCE
 
- V4L2_CTRL_CLASS_JPEG
 
- V4L2_CTRL_CLASS_MPEG
 
- V4L2_CTRL_CLASS_RF_TUNER
 
- V4L2_CTRL_CLASS_USER
 
- V4L2_CTRL_COMPOUND_TYPES
 
- V4L2_CTRL_COUNT
 
- V4L2_CTRL_DRIVER_PRIV
 
- V4L2_CTRL_FLAG_DISABLED
 
- V4L2_CTRL_FLAG_EXECUTE_ON_WRITE
 
- V4L2_CTRL_FLAG_GRABBED
 
- V4L2_CTRL_FLAG_HAS_PAYLOAD
 
- V4L2_CTRL_FLAG_INACTIVE
 
- V4L2_CTRL_FLAG_MODIFY_LAYOUT
 
- V4L2_CTRL_FLAG_NEXT_COMPOUND
 
- V4L2_CTRL_FLAG_NEXT_CTRL
 
- V4L2_CTRL_FLAG_READ_ONLY
 
- V4L2_CTRL_FLAG_SLIDER
 
- V4L2_CTRL_FLAG_UPDATE
 
- V4L2_CTRL_FLAG_VOLATILE
 
- V4L2_CTRL_FLAG_WRITE_ONLY
 
- V4L2_CTRL_ID2CLASS
 
- V4L2_CTRL_ID2WHICH
 
- V4L2_CTRL_ID_MASK
 
- V4L2_CTRL_MAX_DIMS
 
- V4L2_CTRL_TYPE_BITMASK
 
- V4L2_CTRL_TYPE_BOOLEAN
 
- V4L2_CTRL_TYPE_BUTTON
 
- V4L2_CTRL_TYPE_CTRL_CLASS
 
- V4L2_CTRL_TYPE_FWHT_PARAMS
 
- V4L2_CTRL_TYPE_H264_DECODE_PARAMS
 
- V4L2_CTRL_TYPE_H264_PPS
 
- V4L2_CTRL_TYPE_H264_SCALING_MATRIX
 
- V4L2_CTRL_TYPE_H264_SLICE_PARAMS
 
- V4L2_CTRL_TYPE_H264_SPS
 
- V4L2_CTRL_TYPE_INTEGER
 
- V4L2_CTRL_TYPE_INTEGER64
 
- V4L2_CTRL_TYPE_INTEGER_MENU
 
- V4L2_CTRL_TYPE_MENU
 
- V4L2_CTRL_TYPE_MPEG2_QUANTIZATION
 
- V4L2_CTRL_TYPE_MPEG2_SLICE_PARAMS
 
- V4L2_CTRL_TYPE_STRING
 
- V4L2_CTRL_TYPE_U16
 
- V4L2_CTRL_TYPE_U32
 
- V4L2_CTRL_TYPE_U8
 
- V4L2_CTRL_TYPE_VP8_FRAME_HEADER
 
- V4L2_CTRL_WHICH_CUR_VAL
 
- V4L2_CTRL_WHICH_DEF_VAL
 
- V4L2_CTRL_WHICH_REQUEST_VAL
 
- V4L2_DEBUG_I2C
 
- V4L2_DEBUG_ISOC
 
- V4L2_DEBUG_OPEN
 
- V4L2_DEBUG_QUEUE
 
- V4L2_DEBUG_REG
 
- V4L2_DEBUG_RES_LOCK
 
- V4L2_DEC_CMD_PAUSE
 
- V4L2_DEC_CMD_PAUSE_TO_BLACK
 
- V4L2_DEC_CMD_RESUME
 
- V4L2_DEC_CMD_START
 
- V4L2_DEC_CMD_START_MUTE_AUDIO
 
- V4L2_DEC_CMD_STOP
 
- V4L2_DEC_CMD_STOP_IMMEDIATELY
 
- V4L2_DEC_CMD_STOP_TO_BLACK
 
- V4L2_DEC_START_FMT_GOP
 
- V4L2_DEC_START_FMT_NONE
 
- V4L2_DEEMPHASIS_50_uS
 
- V4L2_DEEMPHASIS_75_uS
 
- V4L2_DEEMPHASIS_DISABLED
 
- V4L2_DETECT_MD_MODE_DISABLED
 
- V4L2_DETECT_MD_MODE_GLOBAL
 
- V4L2_DETECT_MD_MODE_REGION_GRID
 
- V4L2_DETECT_MD_MODE_THRESHOLD_GRID
 
- V4L2_DEVICE_NAME_SIZE
 
- V4L2_DEVICE_NOTIFY_EVENT
 
- V4L2_DEV_DEBUG_CTRL
 
- V4L2_DEV_DEBUG_FOP
 
- V4L2_DEV_DEBUG_IOCTL
 
- V4L2_DEV_DEBUG_IOCTL_ARG
 
- V4L2_DEV_DEBUG_POLL
 
- V4L2_DEV_DEBUG_STREAMING
 
- V4L2_DV_BT_656_1120
 
- V4L2_DV_BT_BLANKING_HEIGHT
 
- V4L2_DV_BT_BLANKING_WIDTH
 
- V4L2_DV_BT_CAP_CUSTOM
 
- V4L2_DV_BT_CAP_INTERLACED
 
- V4L2_DV_BT_CAP_PROGRESSIVE
 
- V4L2_DV_BT_CAP_REDUCED_BLANKING
 
- V4L2_DV_BT_CEA_1280X720P24
 
- V4L2_DV_BT_CEA_1280X720P25
 
- V4L2_DV_BT_CEA_1280X720P30
 
- V4L2_DV_BT_CEA_1280X720P50
 
- V4L2_DV_BT_CEA_1280X720P60
 
- V4L2_DV_BT_CEA_1920X1080I50
 
- V4L2_DV_BT_CEA_1920X1080I60
 
- V4L2_DV_BT_CEA_1920X1080P24
 
- V4L2_DV_BT_CEA_1920X1080P25
 
- V4L2_DV_BT_CEA_1920X1080P30
 
- V4L2_DV_BT_CEA_1920X1080P50
 
- V4L2_DV_BT_CEA_1920X1080P60
 
- V4L2_DV_BT_CEA_3840X2160P24
 
- V4L2_DV_BT_CEA_3840X2160P25
 
- V4L2_DV_BT_CEA_3840X2160P30
 
- V4L2_DV_BT_CEA_3840X2160P50
 
- V4L2_DV_BT_CEA_3840X2160P60
 
- V4L2_DV_BT_CEA_4096X2160P24
 
- V4L2_DV_BT_CEA_4096X2160P25
 
- V4L2_DV_BT_CEA_4096X2160P30
 
- V4L2_DV_BT_CEA_4096X2160P50
 
- V4L2_DV_BT_CEA_4096X2160P60
 
- V4L2_DV_BT_CEA_640X480P59_94
 
- V4L2_DV_BT_CEA_720X480I59_94
 
- V4L2_DV_BT_CEA_720X480P59_94
 
- V4L2_DV_BT_CEA_720X576I50
 
- V4L2_DV_BT_CEA_720X576P50
 
- V4L2_DV_BT_DMT_1024X768I43
 
- V4L2_DV_BT_DMT_1024X768P120_RB
 
- V4L2_DV_BT_DMT_1024X768P60
 
- V4L2_DV_BT_DMT_1024X768P70
 
- V4L2_DV_BT_DMT_1024X768P75
 
- V4L2_DV_BT_DMT_1024X768P85
 
- V4L2_DV_BT_DMT_1152X864P75
 
- V4L2_DV_BT_DMT_1280X1024P120_RB
 
- V4L2_DV_BT_DMT_1280X1024P60
 
- V4L2_DV_BT_DMT_1280X1024P75
 
- V4L2_DV_BT_DMT_1280X1024P85
 
- V4L2_DV_BT_DMT_1280X720P60
 
- V4L2_DV_BT_DMT_1280X768P120_RB
 
- V4L2_DV_BT_DMT_1280X768P60
 
- V4L2_DV_BT_DMT_1280X768P60_RB
 
- V4L2_DV_BT_DMT_1280X768P75
 
- V4L2_DV_BT_DMT_1280X768P85
 
- V4L2_DV_BT_DMT_1280X800P120_RB
 
- V4L2_DV_BT_DMT_1280X800P60
 
- V4L2_DV_BT_DMT_1280X800P60_RB
 
- V4L2_DV_BT_DMT_1280X800P75
 
- V4L2_DV_BT_DMT_1280X800P85
 
- V4L2_DV_BT_DMT_1280X960P120_RB
 
- V4L2_DV_BT_DMT_1280X960P60
 
- V4L2_DV_BT_DMT_1280X960P85
 
- V4L2_DV_BT_DMT_1360X768P120_RB
 
- V4L2_DV_BT_DMT_1360X768P60
 
- V4L2_DV_BT_DMT_1366X768P60
 
- V4L2_DV_BT_DMT_1366X768P60_RB
 
- V4L2_DV_BT_DMT_1400X1050P120_RB
 
- V4L2_DV_BT_DMT_1400X1050P60
 
- V4L2_DV_BT_DMT_1400X1050P60_RB
 
- V4L2_DV_BT_DMT_1400X1050P75
 
- V4L2_DV_BT_DMT_1400X1050P85
 
- V4L2_DV_BT_DMT_1440X900P120_RB
 
- V4L2_DV_BT_DMT_1440X900P60
 
- V4L2_DV_BT_DMT_1440X900P60_RB
 
- V4L2_DV_BT_DMT_1440X900P75
 
- V4L2_DV_BT_DMT_1440X900P85
 
- V4L2_DV_BT_DMT_1600X1200P120_RB
 
- V4L2_DV_BT_DMT_1600X1200P60
 
- V4L2_DV_BT_DMT_1600X1200P65
 
- V4L2_DV_BT_DMT_1600X1200P70
 
- V4L2_DV_BT_DMT_1600X1200P75
 
- V4L2_DV_BT_DMT_1600X1200P85
 
- V4L2_DV_BT_DMT_1600X900P60_RB
 
- V4L2_DV_BT_DMT_1680X1050P120_RB
 
- V4L2_DV_BT_DMT_1680X1050P60
 
- V4L2_DV_BT_DMT_1680X1050P60_RB
 
- V4L2_DV_BT_DMT_1680X1050P75
 
- V4L2_DV_BT_DMT_1680X1050P85
 
- V4L2_DV_BT_DMT_1792X1344P120_RB
 
- V4L2_DV_BT_DMT_1792X1344P60
 
- V4L2_DV_BT_DMT_1792X1344P75
 
- V4L2_DV_BT_DMT_1856X1392P120_RB
 
- V4L2_DV_BT_DMT_1856X1392P60
 
- V4L2_DV_BT_DMT_1856X1392P75
 
- V4L2_DV_BT_DMT_1920X1080P60
 
- V4L2_DV_BT_DMT_1920X1200P120_RB
 
- V4L2_DV_BT_DMT_1920X1200P60
 
- V4L2_DV_BT_DMT_1920X1200P60_RB
 
- V4L2_DV_BT_DMT_1920X1200P75
 
- V4L2_DV_BT_DMT_1920X1200P85
 
- V4L2_DV_BT_DMT_1920X1440P120_RB
 
- V4L2_DV_BT_DMT_1920X1440P60
 
- V4L2_DV_BT_DMT_1920X1440P75
 
- V4L2_DV_BT_DMT_2048X1152P60_RB
 
- V4L2_DV_BT_DMT_2560X1600P120_RB
 
- V4L2_DV_BT_DMT_2560X1600P60
 
- V4L2_DV_BT_DMT_2560X1600P60_RB
 
- V4L2_DV_BT_DMT_2560X1600P75
 
- V4L2_DV_BT_DMT_2560X1600P85
 
- V4L2_DV_BT_DMT_4096X2160P59_94_RB
 
- V4L2_DV_BT_DMT_4096X2160P60_RB
 
- V4L2_DV_BT_DMT_640X350P85
 
- V4L2_DV_BT_DMT_640X400P85
 
- V4L2_DV_BT_DMT_640X480P60
 
- V4L2_DV_BT_DMT_640X480P72
 
- V4L2_DV_BT_DMT_640X480P75
 
- V4L2_DV_BT_DMT_640X480P85
 
- V4L2_DV_BT_DMT_720X400P85
 
- V4L2_DV_BT_DMT_800X600P120_RB
 
- V4L2_DV_BT_DMT_800X600P56
 
- V4L2_DV_BT_DMT_800X600P60
 
- V4L2_DV_BT_DMT_800X600P72
 
- V4L2_DV_BT_DMT_800X600P75
 
- V4L2_DV_BT_DMT_800X600P85
 
- V4L2_DV_BT_DMT_848X480P60
 
- V4L2_DV_BT_FRAME_HEIGHT
 
- V4L2_DV_BT_FRAME_WIDTH
 
- V4L2_DV_BT_SDI_720X487I60
 
- V4L2_DV_BT_STD_CEA861
 
- V4L2_DV_BT_STD_CVT
 
- V4L2_DV_BT_STD_DMT
 
- V4L2_DV_BT_STD_GTF
 
- V4L2_DV_BT_STD_SDI
 
- V4L2_DV_FL_CAN_DETECT_REDUCED_FPS
 
- V4L2_DV_FL_CAN_REDUCE_FPS
 
- V4L2_DV_FL_FIRST_FIELD_EXTRA_LINE
 
- V4L2_DV_FL_HALF_LINE
 
- V4L2_DV_FL_HAS_CEA861_VIC
 
- V4L2_DV_FL_HAS_HDMI_VIC
 
- V4L2_DV_FL_HAS_PICTURE_ASPECT
 
- V4L2_DV_FL_IS_CE_VIDEO
 
- V4L2_DV_FL_REDUCED_BLANKING
 
- V4L2_DV_FL_REDUCED_FPS
 
- V4L2_DV_HSYNC_POS_POL
 
- V4L2_DV_INTERLACED
 
- V4L2_DV_IT_CONTENT_TYPE_CINEMA
 
- V4L2_DV_IT_CONTENT_TYPE_GAME
 
- V4L2_DV_IT_CONTENT_TYPE_GRAPHICS
 
- V4L2_DV_IT_CONTENT_TYPE_NO_ITC
 
- V4L2_DV_IT_CONTENT_TYPE_PHOTO
 
- V4L2_DV_PROGRESSIVE
 
- V4L2_DV_RGB_RANGE_AUTO
 
- V4L2_DV_RGB_RANGE_FULL
 
- V4L2_DV_RGB_RANGE_LIMITED
 
- V4L2_DV_TX_MODE_DVI_D
 
- V4L2_DV_TX_MODE_HDMI
 
- V4L2_DV_VSYNC_POS_POL
 
- V4L2_ENC_CMD_PAUSE
 
- V4L2_ENC_CMD_RESUME
 
- V4L2_ENC_CMD_START
 
- V4L2_ENC_CMD_STOP
 
- V4L2_ENC_CMD_STOP_AT_GOP_END
 
- V4L2_ENC_IDX_ENTRIES
 
- V4L2_ENC_IDX_FRAME_B
 
- V4L2_ENC_IDX_FRAME_I
 
- V4L2_ENC_IDX_FRAME_MASK
 
- V4L2_ENC_IDX_FRAME_P
 
- V4L2_EVENT_ALL
 
- V4L2_EVENT_CTRL
 
- V4L2_EVENT_CTRL_CH_FLAGS
 
- V4L2_EVENT_CTRL_CH_RANGE
 
- V4L2_EVENT_CTRL_CH_VALUE
 
- V4L2_EVENT_EOS
 
- V4L2_EVENT_FRAME_SYNC
 
- V4L2_EVENT_H
 
- V4L2_EVENT_IMX_CLASS
 
- V4L2_EVENT_IMX_FRAME_INTERVAL_ERROR
 
- V4L2_EVENT_MD_FL_HAVE_FRAME_SEQ
 
- V4L2_EVENT_MOTION_DET
 
- V4L2_EVENT_OMAP3ISP_AEWB
 
- V4L2_EVENT_OMAP3ISP_AF
 
- V4L2_EVENT_OMAP3ISP_CLASS
 
- V4L2_EVENT_OMAP3ISP_HIST
 
- V4L2_EVENT_PRIVATE_START
 
- V4L2_EVENT_SOURCE_CHANGE
 
- V4L2_EVENT_SRC_CH_RESOLUTION
 
- V4L2_EVENT_SUB_FL_ALLOW_FEEDBACK
 
- V4L2_EVENT_SUB_FL_SEND_INITIAL
 
- V4L2_EVENT_VSYNC
 
- V4L2_EXPOSURE_APERTURE_PRIORITY
 
- V4L2_EXPOSURE_AUTO
 
- V4L2_EXPOSURE_MANUAL
 
- V4L2_EXPOSURE_METERING_AVERAGE
 
- V4L2_EXPOSURE_METERING_CENTER_WEIGHTED
 
- V4L2_EXPOSURE_METERING_MATRIX
 
- V4L2_EXPOSURE_METERING_SPOT
 
- V4L2_EXPOSURE_SHUTTER_PRIORITY
 
- V4L2_FBUF_CAP_BITMAP_CLIPPING
 
- V4L2_FBUF_CAP_CHROMAKEY
 
- V4L2_FBUF_CAP_EXTERNOVERLAY
 
- V4L2_FBUF_CAP_GLOBAL_ALPHA
 
- V4L2_FBUF_CAP_LIST_CLIPPING
 
- V4L2_FBUF_CAP_LOCAL_ALPHA
 
- V4L2_FBUF_CAP_LOCAL_INV_ALPHA
 
- V4L2_FBUF_CAP_SRC_CHROMAKEY
 
- V4L2_FBUF_FLAG_CHROMAKEY
 
- V4L2_FBUF_FLAG_GLOBAL_ALPHA
 
- V4L2_FBUF_FLAG_LOCAL_ALPHA
 
- V4L2_FBUF_FLAG_LOCAL_INV_ALPHA
 
- V4L2_FBUF_FLAG_OVERLAY
 
- V4L2_FBUF_FLAG_PRIMARY
 
- V4L2_FBUF_FLAG_SRC_CHROMAKEY
 
- V4L2_FH_H
 
- V4L2_FIELD_ALTERNATE
 
- V4L2_FIELD_ANY
 
- V4L2_FIELD_BOTTOM
 
- V4L2_FIELD_HAS_BOTH
 
- V4L2_FIELD_HAS_BOTTOM
 
- V4L2_FIELD_HAS_TOP
 
- V4L2_FIELD_HAS_T_OR_B
 
- V4L2_FIELD_INTERLACED
 
- V4L2_FIELD_INTERLACED_BT
 
- V4L2_FIELD_INTERLACED_TB
 
- V4L2_FIELD_IS_INTERLACED
 
- V4L2_FIELD_IS_SEQUENTIAL
 
- V4L2_FIELD_NONE
 
- V4L2_FIELD_SEQ_BT
 
- V4L2_FIELD_SEQ_TB
 
- V4L2_FIELD_TOP
 
- V4L2_FLASH_FAULT_INDICATOR
 
- V4L2_FLASH_FAULT_INPUT_VOLTAGE
 
- V4L2_FLASH_FAULT_LED_OVER_TEMPERATURE
 
- V4L2_FLASH_FAULT_OVER_CURRENT
 
- V4L2_FLASH_FAULT_OVER_TEMPERATURE
 
- V4L2_FLASH_FAULT_OVER_VOLTAGE
 
- V4L2_FLASH_FAULT_SHORT_CIRCUIT
 
- V4L2_FLASH_FAULT_TIMEOUT
 
- V4L2_FLASH_FAULT_UNDER_VOLTAGE
 
- V4L2_FLASH_LED_MODE_FLASH
 
- V4L2_FLASH_LED_MODE_NONE
 
- V4L2_FLASH_LED_MODE_TORCH
 
- V4L2_FLASH_STROBE_SOURCE_EXTERNAL
 
- V4L2_FLASH_STROBE_SOURCE_SOFTWARE
 
- V4L2_FL_QUIRK_INVERTED_CROP
 
- V4L2_FL_REGISTERED
 
- V4L2_FL_USES_V4L2_FH
 
- V4L2_FMT_FLAG_COMPRESSED
 
- V4L2_FMT_FLAG_CONTINUOUS_BYTESTREAM
 
- V4L2_FMT_FLAG_DYN_RESOLUTION
 
- V4L2_FMT_FLAG_EMULATED
 
- V4L2_FRACT_COMPARE
 
- V4L2_FRAME_DESC_ENTRY_MAX
 
- V4L2_FRMIVAL_TYPE_CONTINUOUS
 
- V4L2_FRMIVAL_TYPE_DISCRETE
 
- V4L2_FRMIVAL_TYPE_STEPWISE
 
- V4L2_FRMSIZE_TYPE_CONTINUOUS
 
- V4L2_FRMSIZE_TYPE_DISCRETE
 
- V4L2_FRMSIZE_TYPE_STEPWISE
 
- V4L2_FWNODE_BUS_TYPE_BT656
 
- V4L2_FWNODE_BUS_TYPE_CCP2
 
- V4L2_FWNODE_BUS_TYPE_CSI1
 
- V4L2_FWNODE_BUS_TYPE_CSI2_CPHY
 
- V4L2_FWNODE_BUS_TYPE_CSI2_DPHY
 
- V4L2_FWNODE_BUS_TYPE_GUESS
 
- V4L2_FWNODE_BUS_TYPE_PARALLEL
 
- V4L2_FWNODE_CSI2_MAX_DATA_LANES
 
- V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC
 
- V4L2_H264_DPB_ENTRY_FLAG_ACTIVE
 
- V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM
 
- V4L2_H264_DPB_ENTRY_FLAG_VALID
 
- V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT
 
- V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED
 
- V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT
 
- V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE
 
- V4L2_H264_PPS_FLAG_PIC_SCALING_MATRIX_PRESENT
 
- V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT
 
- V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE
 
- V4L2_H264_PPS_FLAG_WEIGHTED_PRED
 
- V4L2_H264_SLICE_FLAG_BOTTOM_FIELD
 
- V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED
 
- V4L2_H264_SLICE_FLAG_FIELD_PIC
 
- V4L2_H264_SLICE_FLAG_SP_FOR_SWITCH
 
- V4L2_H264_SLICE_TYPE_B
 
- V4L2_H264_SLICE_TYPE_I
 
- V4L2_H264_SLICE_TYPE_P
 
- V4L2_H264_SLICE_TYPE_SI
 
- V4L2_H264_SLICE_TYPE_SP
 
- V4L2_H264_SPS_CONSTRAINT_SET0_FLAG
 
- V4L2_H264_SPS_CONSTRAINT_SET1_FLAG
 
- V4L2_H264_SPS_CONSTRAINT_SET2_FLAG
 
- V4L2_H264_SPS_CONSTRAINT_SET3_FLAG
 
- V4L2_H264_SPS_CONSTRAINT_SET4_FLAG
 
- V4L2_H264_SPS_CONSTRAINT_SET5_FLAG
 
- V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO
 
- V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE
 
- V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY
 
- V4L2_H264_SPS_FLAG_GAPS_IN_FRAME_NUM_VALUE_ALLOWED
 
- V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD
 
- V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS
 
- V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE
 
- V4L2_HSV_ENC_180
 
- V4L2_HSV_ENC_256
 
- V4L2_INIT_BT_TIMINGS
 
- V4L2_INPUT_TYPE_CAMERA
 
- V4L2_INPUT_TYPE_TOUCH
 
- V4L2_INPUT_TYPE_TUNER
 
- V4L2_IN_CAP_CUSTOM_TIMINGS
 
- V4L2_IN_CAP_DV_TIMINGS
 
- V4L2_IN_CAP_NATIVE_SIZE
 
- V4L2_IN_CAP_STD
 
- V4L2_IN_ST_COLOR_KILL
 
- V4L2_IN_ST_HFLIP
 
- V4L2_IN_ST_MACROVISION
 
- V4L2_IN_ST_NO_ACCESS
 
- V4L2_IN_ST_NO_CARRIER
 
- V4L2_IN_ST_NO_COLOR
 
- V4L2_IN_ST_NO_EQU
 
- V4L2_IN_ST_NO_H_LOCK
 
- V4L2_IN_ST_NO_POWER
 
- V4L2_IN_ST_NO_SIGNAL
 
- V4L2_IN_ST_NO_STD_LOCK
 
- V4L2_IN_ST_NO_SYNC
 
- V4L2_IN_ST_NO_V_LOCK
 
- V4L2_IN_ST_VFLIP
 
- V4L2_IN_ST_VTR
 
- V4L2_IOCTLS
 
- V4L2_ISO_SENSITIVITY_AUTO
 
- V4L2_ISO_SENSITIVITY_MANUAL
 
- V4L2_JPEG_ACTIVE_MARKER_APP0
 
- V4L2_JPEG_ACTIVE_MARKER_APP1
 
- V4L2_JPEG_ACTIVE_MARKER_COM
 
- V4L2_JPEG_ACTIVE_MARKER_DHT
 
- V4L2_JPEG_ACTIVE_MARKER_DQT
 
- V4L2_JPEG_CHROMA_SUBSAMPLING_410
 
- V4L2_JPEG_CHROMA_SUBSAMPLING_411
 
- V4L2_JPEG_CHROMA_SUBSAMPLING_420
 
- V4L2_JPEG_CHROMA_SUBSAMPLING_422
 
- V4L2_JPEG_CHROMA_SUBSAMPLING_444
 
- V4L2_JPEG_CHROMA_SUBSAMPLING_GRAY
 
- V4L2_JPEG_MARKER_APP
 
- V4L2_JPEG_MARKER_COM
 
- V4L2_JPEG_MARKER_DHT
 
- V4L2_JPEG_MARKER_DQT
 
- V4L2_JPEG_MARKER_DRI
 
- V4L2_LOCK_EXPOSURE
 
- V4L2_LOCK_FOCUS
 
- V4L2_LOCK_WHITE_BALANCE
 
- V4L2_M2M_DST
 
- V4L2_M2M_SRC
 
- V4L2_MAP_COLORSPACE_DEFAULT
 
- V4L2_MAP_QUANTIZATION_DEFAULT
 
- V4L2_MAP_XFER_FUNC_DEFAULT
 
- V4L2_MAP_YCBCR_ENC_DEFAULT
 
- V4L2_MBUS_BT656
 
- V4L2_MBUS_CCP2
 
- V4L2_MBUS_CSI1
 
- V4L2_MBUS_CSI2_1_LANE
 
- V4L2_MBUS_CSI2_2_LANE
 
- V4L2_MBUS_CSI2_3_LANE
 
- V4L2_MBUS_CSI2_4_LANE
 
- V4L2_MBUS_CSI2_CHANNELS
 
- V4L2_MBUS_CSI2_CHANNEL_0
 
- V4L2_MBUS_CSI2_CHANNEL_1
 
- V4L2_MBUS_CSI2_CHANNEL_2
 
- V4L2_MBUS_CSI2_CHANNEL_3
 
- V4L2_MBUS_CSI2_CONTINUOUS_CLOCK
 
- V4L2_MBUS_CSI2_CPHY
 
- V4L2_MBUS_CSI2_DPHY
 
- V4L2_MBUS_CSI2_LANES
 
- V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK
 
- V4L2_MBUS_DATA_ACTIVE_HIGH
 
- V4L2_MBUS_DATA_ACTIVE_LOW
 
- V4L2_MBUS_DATA_ENABLE_HIGH
 
- V4L2_MBUS_DATA_ENABLE_LOW
 
- V4L2_MBUS_FIELD_EVEN_HIGH
 
- V4L2_MBUS_FIELD_EVEN_LOW
 
- V4L2_MBUS_FRAME_DESC_FL_BLOB
 
- V4L2_MBUS_FRAME_DESC_FL_LEN_MAX
 
- V4L2_MBUS_FROM_MEDIA_BUS_FMT
 
- V4L2_MBUS_HSYNC_ACTIVE_HIGH
 
- V4L2_MBUS_HSYNC_ACTIVE_LOW
 
- V4L2_MBUS_MASTER
 
- V4L2_MBUS_PARALLEL
 
- V4L2_MBUS_PCLK_SAMPLE_FALLING
 
- V4L2_MBUS_PCLK_SAMPLE_RISING
 
- V4L2_MBUS_SLAVE
 
- V4L2_MBUS_UNKNOWN
 
- V4L2_MBUS_VIDEO_SOG_ACTIVE_HIGH
 
- V4L2_MBUS_VIDEO_SOG_ACTIVE_LOW
 
- V4L2_MBUS_VSYNC_ACTIVE_HIGH
 
- V4L2_MBUS_VSYNC_ACTIVE_LOW
 
- V4L2_MEDIABUS_H
 
- V4L2_MEMORY_DMABUF
 
- V4L2_MEMORY_MMAP
 
- V4L2_MEMORY_OVERLAY
 
- V4L2_MEMORY_USERPTR
 
- V4L2_META_FMT_D4XX
 
- V4L2_META_FMT_IPU3_PARAMS
 
- V4L2_META_FMT_IPU3_STAT_3A
 
- V4L2_META_FMT_UVC
 
- V4L2_META_FMT_VSP1_HGO
 
- V4L2_META_FMT_VSP1_HGT
 
- V4L2_MODE_HIGHQUALITY
 
- V4L2_MPEG2_PICTURE_CODING_TYPE_B
 
- V4L2_MPEG2_PICTURE_CODING_TYPE_D
 
- V4L2_MPEG2_PICTURE_CODING_TYPE_I
 
- V4L2_MPEG2_PICTURE_CODING_TYPE_P
 
- V4L2_MPEG_AUDIO_AC3_BITRATE_112K
 
- V4L2_MPEG_AUDIO_AC3_BITRATE_128K
 
- V4L2_MPEG_AUDIO_AC3_BITRATE_160K
 
- V4L2_MPEG_AUDIO_AC3_BITRATE_192K
 
- V4L2_MPEG_AUDIO_AC3_BITRATE_224K
 
- V4L2_MPEG_AUDIO_AC3_BITRATE_256K
 
- V4L2_MPEG_AUDIO_AC3_BITRATE_320K
 
- V4L2_MPEG_AUDIO_AC3_BITRATE_32K
 
- V4L2_MPEG_AUDIO_AC3_BITRATE_384K
 
- V4L2_MPEG_AUDIO_AC3_BITRATE_40K
 
- V4L2_MPEG_AUDIO_AC3_BITRATE_448K
 
- V4L2_MPEG_AUDIO_AC3_BITRATE_48K
 
- V4L2_MPEG_AUDIO_AC3_BITRATE_512K
 
- V4L2_MPEG_AUDIO_AC3_BITRATE_56K
 
- V4L2_MPEG_AUDIO_AC3_BITRATE_576K
 
- V4L2_MPEG_AUDIO_AC3_BITRATE_640K
 
- V4L2_MPEG_AUDIO_AC3_BITRATE_64K
 
- V4L2_MPEG_AUDIO_AC3_BITRATE_80K
 
- V4L2_MPEG_AUDIO_AC3_BITRATE_96K
 
- V4L2_MPEG_AUDIO_CRC_CRC16
 
- V4L2_MPEG_AUDIO_CRC_NONE
 
- V4L2_MPEG_AUDIO_DEC_PLAYBACK_AUTO
 
- V4L2_MPEG_AUDIO_DEC_PLAYBACK_LEFT
 
- V4L2_MPEG_AUDIO_DEC_PLAYBACK_MONO
 
- V4L2_MPEG_AUDIO_DEC_PLAYBACK_RIGHT
 
- V4L2_MPEG_AUDIO_DEC_PLAYBACK_STEREO
 
- V4L2_MPEG_AUDIO_DEC_PLAYBACK_SWAPPED_STEREO
 
- V4L2_MPEG_AUDIO_EMPHASIS_50_DIV_15_uS
 
- V4L2_MPEG_AUDIO_EMPHASIS_CCITT_J17
 
- V4L2_MPEG_AUDIO_EMPHASIS_NONE
 
- V4L2_MPEG_AUDIO_ENCODING_AAC
 
- V4L2_MPEG_AUDIO_ENCODING_AC3
 
- V4L2_MPEG_AUDIO_ENCODING_LAYER_1
 
- V4L2_MPEG_AUDIO_ENCODING_LAYER_2
 
- V4L2_MPEG_AUDIO_ENCODING_LAYER_3
 
- V4L2_MPEG_AUDIO_L1_BITRATE_128K
 
- V4L2_MPEG_AUDIO_L1_BITRATE_160K
 
- V4L2_MPEG_AUDIO_L1_BITRATE_192K
 
- V4L2_MPEG_AUDIO_L1_BITRATE_224K
 
- V4L2_MPEG_AUDIO_L1_BITRATE_256K
 
- V4L2_MPEG_AUDIO_L1_BITRATE_288K
 
- V4L2_MPEG_AUDIO_L1_BITRATE_320K
 
- V4L2_MPEG_AUDIO_L1_BITRATE_32K
 
- V4L2_MPEG_AUDIO_L1_BITRATE_352K
 
- V4L2_MPEG_AUDIO_L1_BITRATE_384K
 
- V4L2_MPEG_AUDIO_L1_BITRATE_416K
 
- V4L2_MPEG_AUDIO_L1_BITRATE_448K
 
- V4L2_MPEG_AUDIO_L1_BITRATE_64K
 
- V4L2_MPEG_AUDIO_L1_BITRATE_96K
 
- V4L2_MPEG_AUDIO_L2_BITRATE_112K
 
- V4L2_MPEG_AUDIO_L2_BITRATE_128K
 
- V4L2_MPEG_AUDIO_L2_BITRATE_160K
 
- V4L2_MPEG_AUDIO_L2_BITRATE_192K
 
- V4L2_MPEG_AUDIO_L2_BITRATE_224K
 
- V4L2_MPEG_AUDIO_L2_BITRATE_256K
 
- V4L2_MPEG_AUDIO_L2_BITRATE_320K
 
- V4L2_MPEG_AUDIO_L2_BITRATE_32K
 
- V4L2_MPEG_AUDIO_L2_BITRATE_384K
 
- V4L2_MPEG_AUDIO_L2_BITRATE_48K
 
- V4L2_MPEG_AUDIO_L2_BITRATE_56K
 
- V4L2_MPEG_AUDIO_L2_BITRATE_64K
 
- V4L2_MPEG_AUDIO_L2_BITRATE_80K
 
- V4L2_MPEG_AUDIO_L2_BITRATE_96K
 
- V4L2_MPEG_AUDIO_L3_BITRATE_112K
 
- V4L2_MPEG_AUDIO_L3_BITRATE_128K
 
- V4L2_MPEG_AUDIO_L3_BITRATE_160K
 
- V4L2_MPEG_AUDIO_L3_BITRATE_192K
 
- V4L2_MPEG_AUDIO_L3_BITRATE_224K
 
- V4L2_MPEG_AUDIO_L3_BITRATE_256K
 
- V4L2_MPEG_AUDIO_L3_BITRATE_320K
 
- V4L2_MPEG_AUDIO_L3_BITRATE_32K
 
- V4L2_MPEG_AUDIO_L3_BITRATE_40K
 
- V4L2_MPEG_AUDIO_L3_BITRATE_48K
 
- V4L2_MPEG_AUDIO_L3_BITRATE_56K
 
- V4L2_MPEG_AUDIO_L3_BITRATE_64K
 
- V4L2_MPEG_AUDIO_L3_BITRATE_80K
 
- V4L2_MPEG_AUDIO_L3_BITRATE_96K
 
- V4L2_MPEG_AUDIO_MODE_DUAL
 
- V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_12
 
- V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_16
 
- V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_4
 
- V4L2_MPEG_AUDIO_MODE_EXTENSION_BOUND_8
 
- V4L2_MPEG_AUDIO_MODE_JOINT_STEREO
 
- V4L2_MPEG_AUDIO_MODE_MONO
 
- V4L2_MPEG_AUDIO_MODE_STEREO
 
- V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000
 
- V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100
 
- V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000
 
- V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_1D_HOR
 
- V4L2_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE_OFF
 
- V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_HOR
 
- V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_1D_VERT
 
- V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_HV_SEPARABLE
 
- V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_2D_SYM_NON_SEPARABLE
 
- V4L2_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE_OFF
 
- V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_DIAG
 
- V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR
 
- V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_HOR_VERT
 
- V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_OFF
 
- V4L2_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE_VERT
 
- V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_AUTO
 
- V4L2_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE_MANUAL
 
- V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_AUTO
 
- V4L2_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE_MANUAL
 
- V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_DISABLED
 
- V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_I_FRAME
 
- V4L2_MPEG_MFC51_VIDEO_FORCE_FRAME_TYPE_NOT_CODED
 
- V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT
 
- V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_DISABLED
 
- V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT
 
- V4L2_MPEG_STREAM_TYPE_MPEG1_SS
 
- V4L2_MPEG_STREAM_TYPE_MPEG1_VCD
 
- V4L2_MPEG_STREAM_TYPE_MPEG2_DVD
 
- V4L2_MPEG_STREAM_TYPE_MPEG2_PS
 
- V4L2_MPEG_STREAM_TYPE_MPEG2_SVCD
 
- V4L2_MPEG_STREAM_TYPE_MPEG2_TS
 
- V4L2_MPEG_STREAM_VBI_FMT_IVTV
 
- V4L2_MPEG_STREAM_VBI_FMT_NONE
 
- V4L2_MPEG_VBI_IVTV_CAPTION_525
 
- V4L2_MPEG_VBI_IVTV_MAGIC0
 
- V4L2_MPEG_VBI_IVTV_MAGIC1
 
- V4L2_MPEG_VBI_IVTV_TELETEXT_B
 
- V4L2_MPEG_VBI_IVTV_VPS
 
- V4L2_MPEG_VBI_IVTV_WSS_625
 
- V4L2_MPEG_VIDEO_ASPECT_16x9
 
- V4L2_MPEG_VIDEO_ASPECT_1x1
 
- V4L2_MPEG_VIDEO_ASPECT_221x100
 
- V4L2_MPEG_VIDEO_ASPECT_4x3
 
- V4L2_MPEG_VIDEO_BITRATE_MODE_CBR
 
- V4L2_MPEG_VIDEO_BITRATE_MODE_VBR
 
- V4L2_MPEG_VIDEO_ENCODING_MPEG_1
 
- V4L2_MPEG_VIDEO_ENCODING_MPEG_2
 
- V4L2_MPEG_VIDEO_ENCODING_MPEG_4_AVC
 
- V4L2_MPEG_VIDEO_H264_DECODE_MODE_FRAME_BASED
 
- V4L2_MPEG_VIDEO_H264_DECODE_MODE_SLICE_BASED
 
- V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC
 
- V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC
 
- V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_LEFT
 
- V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_RIGHT
 
- V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_BOX_OUT
 
- V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_EXPLICIT
 
- V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_FOREGROUND_WITH_LEFT_OVER
 
- V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES
 
- V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN
 
- V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES
 
- V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN
 
- V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_B
 
- V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P
 
- V4L2_MPEG_VIDEO_H264_LEVEL_1B
 
- V4L2_MPEG_VIDEO_H264_LEVEL_1_0
 
- V4L2_MPEG_VIDEO_H264_LEVEL_1_1
 
- V4L2_MPEG_VIDEO_H264_LEVEL_1_2
 
- V4L2_MPEG_VIDEO_H264_LEVEL_1_3
 
- V4L2_MPEG_VIDEO_H264_LEVEL_2_0
 
- V4L2_MPEG_VIDEO_H264_LEVEL_2_1
 
- V4L2_MPEG_VIDEO_H264_LEVEL_2_2
 
- V4L2_MPEG_VIDEO_H264_LEVEL_3_0
 
- V4L2_MPEG_VIDEO_H264_LEVEL_3_1
 
- V4L2_MPEG_VIDEO_H264_LEVEL_3_2
 
- V4L2_MPEG_VIDEO_H264_LEVEL_4_0
 
- V4L2_MPEG_VIDEO_H264_LEVEL_4_1
 
- V4L2_MPEG_VIDEO_H264_LEVEL_4_2
 
- V4L2_MPEG_VIDEO_H264_LEVEL_5_0
 
- V4L2_MPEG_VIDEO_H264_LEVEL_5_1
 
- V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED
 
- V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY
 
- V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED
 
- V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE
 
- V4L2_MPEG_VIDEO_H264_PROFILE_CAVLC_444_INTRA
 
- V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE
 
- V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED
 
- V4L2_MPEG_VIDEO_H264_PROFILE_HIGH
 
- V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10
 
- V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10_INTRA
 
- V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422
 
- V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422_INTRA
 
- V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_INTRA
 
- V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE
 
- V4L2_MPEG_VIDEO_H264_PROFILE_MAIN
 
- V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH
 
- V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_BASELINE
 
- V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH
 
- V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH_INTRA
 
- V4L2_MPEG_VIDEO_H264_PROFILE_STEREO_HIGH
 
- V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_CHECKERBOARD
 
- V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_COLUMN
 
- V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_ROW
 
- V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_SIDE_BY_SIDE
 
- V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_TEMPORAL
 
- V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_TOP_BOTTOM
 
- V4L2_MPEG_VIDEO_H264_START_CODE_ANNEX_B
 
- V4L2_MPEG_VIDEO_H264_START_CODE_NONE
 
- V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_10x11
 
- V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_12x11
 
- V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_15x11
 
- V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_160x99
 
- V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_16x11
 
- V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_18x11
 
- V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_1x1
 
- V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_20x11
 
- V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_24x11
 
- V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_2x1
 
- V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_32x11
 
- V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_3x2
 
- V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_40x33
 
- V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_4x3
 
- V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_64x33
 
- V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_80x33
 
- V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED
 
- V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED
 
- V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME
 
- V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE
 
- V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_B
 
- V4L2_MPEG_VIDEO_HEVC_HIERARCHICAL_CODING_P
 
- V4L2_MPEG_VIDEO_HEVC_LEVEL_1
 
- V4L2_MPEG_VIDEO_HEVC_LEVEL_2
 
- V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1
 
- V4L2_MPEG_VIDEO_HEVC_LEVEL_3
 
- V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1
 
- V4L2_MPEG_VIDEO_HEVC_LEVEL_4
 
- V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1
 
- V4L2_MPEG_VIDEO_HEVC_LEVEL_5
 
- V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1
 
- V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2
 
- V4L2_MPEG_VIDEO_HEVC_LEVEL_6
 
- V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1
 
- V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2
 
- V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED
 
- V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY
 
- V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_ENABLED
 
- V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN
 
- V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10
 
- V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE
 
- V4L2_MPEG_VIDEO_HEVC_REFRESH_CRA
 
- V4L2_MPEG_VIDEO_HEVC_REFRESH_IDR
 
- V4L2_MPEG_VIDEO_HEVC_REFRESH_NONE
 
- V4L2_MPEG_VIDEO_HEVC_SIZE_0
 
- V4L2_MPEG_VIDEO_HEVC_SIZE_1
 
- V4L2_MPEG_VIDEO_HEVC_SIZE_2
 
- V4L2_MPEG_VIDEO_HEVC_SIZE_4
 
- V4L2_MPEG_VIDEO_HEVC_TIER_HIGH
 
- V4L2_MPEG_VIDEO_HEVC_TIER_MAIN
 
- V4L2_MPEG_VIDEO_MPEG2_LEVEL_HIGH
 
- V4L2_MPEG_VIDEO_MPEG2_LEVEL_HIGH_1440
 
- V4L2_MPEG_VIDEO_MPEG2_LEVEL_LOW
 
- V4L2_MPEG_VIDEO_MPEG2_LEVEL_MAIN
 
- V4L2_MPEG_VIDEO_MPEG2_PROFILE_HIGH
 
- V4L2_MPEG_VIDEO_MPEG2_PROFILE_MAIN
 
- V4L2_MPEG_VIDEO_MPEG2_PROFILE_MULTIVIEW
 
- V4L2_MPEG_VIDEO_MPEG2_PROFILE_SIMPLE
 
- V4L2_MPEG_VIDEO_MPEG2_PROFILE_SNR_SCALABLE
 
- V4L2_MPEG_VIDEO_MPEG2_PROFILE_SPATIALLY_SCALABLE
 
- V4L2_MPEG_VIDEO_MPEG4_LEVEL_0
 
- V4L2_MPEG_VIDEO_MPEG4_LEVEL_0B
 
- V4L2_MPEG_VIDEO_MPEG4_LEVEL_1
 
- V4L2_MPEG_VIDEO_MPEG4_LEVEL_2
 
- V4L2_MPEG_VIDEO_MPEG4_LEVEL_3
 
- V4L2_MPEG_VIDEO_MPEG4_LEVEL_3B
 
- V4L2_MPEG_VIDEO_MPEG4_LEVEL_4
 
- V4L2_MPEG_VIDEO_MPEG4_LEVEL_5
 
- V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_CODING_EFFICIENCY
 
- V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_SIMPLE
 
- V4L2_MPEG_VIDEO_MPEG4_PROFILE_CORE
 
- V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE
 
- V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE_SCALABLE
 
- V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES
 
- V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB
 
- V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_BYTES
 
- V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB
 
- V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE
 
- V4L2_MPEG_VIDEO_VP8_PROFILE_0
 
- V4L2_MPEG_VIDEO_VP8_PROFILE_1
 
- V4L2_MPEG_VIDEO_VP8_PROFILE_2
 
- V4L2_MPEG_VIDEO_VP8_PROFILE_3
 
- V4L2_MPEG_VIDEO_VP9_PROFILE_0
 
- V4L2_MPEG_VIDEO_VP9_PROFILE_1
 
- V4L2_MPEG_VIDEO_VP9_PROFILE_2
 
- V4L2_MPEG_VIDEO_VP9_PROFILE_3
 
- V4L2_OUTPUT_TYPE_ANALOG
 
- V4L2_OUTPUT_TYPE_ANALOGVGAOVERLAY
 
- V4L2_OUTPUT_TYPE_MODULATOR
 
- V4L2_OUT_CAP_CUSTOM_TIMINGS
 
- V4L2_OUT_CAP_DV_TIMINGS
 
- V4L2_OUT_CAP_NATIVE_SIZE
 
- V4L2_OUT_CAP_STD
 
- V4L2_PIX_FMT_ABGR32
 
- V4L2_PIX_FMT_ABGR444
 
- V4L2_PIX_FMT_ABGR555
 
- V4L2_PIX_FMT_ARGB32
 
- V4L2_PIX_FMT_ARGB444
 
- V4L2_PIX_FMT_ARGB555
 
- V4L2_PIX_FMT_ARGB555X
 
- V4L2_PIX_FMT_AYUV32
 
- V4L2_PIX_FMT_BGR24
 
- V4L2_PIX_FMT_BGR32
 
- V4L2_PIX_FMT_BGR666
 
- V4L2_PIX_FMT_BGRA32
 
- V4L2_PIX_FMT_BGRA444
 
- V4L2_PIX_FMT_BGRA555
 
- V4L2_PIX_FMT_BGRX32
 
- V4L2_PIX_FMT_BGRX444
 
- V4L2_PIX_FMT_BGRX555
 
- V4L2_PIX_FMT_CIT_YYVYUY
 
- V4L2_PIX_FMT_CNF4
 
- V4L2_PIX_FMT_CPIA1
 
- V4L2_PIX_FMT_DV
 
- V4L2_PIX_FMT_ET61X251
 
- V4L2_PIX_FMT_FLAG_PREMUL_ALPHA
 
- V4L2_PIX_FMT_FWHT
 
- V4L2_PIX_FMT_FWHT_STATELESS
 
- V4L2_PIX_FMT_GREY
 
- V4L2_PIX_FMT_H263
 
- V4L2_PIX_FMT_H264
 
- V4L2_PIX_FMT_H264_MVC
 
- V4L2_PIX_FMT_H264_NO_SC
 
- V4L2_PIX_FMT_H264_SLICE
 
- V4L2_PIX_FMT_HEVC
 
- V4L2_PIX_FMT_HI240
 
- V4L2_PIX_FMT_HM12
 
- V4L2_PIX_FMT_HSV24
 
- V4L2_PIX_FMT_HSV32
 
- V4L2_PIX_FMT_INZI
 
- V4L2_PIX_FMT_IPU3_SBGGR10
 
- V4L2_PIX_FMT_IPU3_SGBRG10
 
- V4L2_PIX_FMT_IPU3_SGRBG10
 
- V4L2_PIX_FMT_IPU3_SRGGB10
 
- V4L2_PIX_FMT_JL2005BCD
 
- V4L2_PIX_FMT_JPEG
 
- V4L2_PIX_FMT_JPGL
 
- V4L2_PIX_FMT_KONICA420
 
- V4L2_PIX_FMT_M420
 
- V4L2_PIX_FMT_MJPEG
 
- V4L2_PIX_FMT_MPEG
 
- V4L2_PIX_FMT_MPEG1
 
- V4L2_PIX_FMT_MPEG2
 
- V4L2_PIX_FMT_MPEG2_SLICE
 
- V4L2_PIX_FMT_MPEG4
 
- V4L2_PIX_FMT_MR97310A
 
- V4L2_PIX_FMT_MT21C
 
- V4L2_PIX_FMT_NV12
 
- V4L2_PIX_FMT_NV12M
 
- V4L2_PIX_FMT_NV12MT
 
- V4L2_PIX_FMT_NV12MT_16X16
 
- V4L2_PIX_FMT_NV16
 
- V4L2_PIX_FMT_NV16M
 
- V4L2_PIX_FMT_NV21
 
- V4L2_PIX_FMT_NV21M
 
- V4L2_PIX_FMT_NV24
 
- V4L2_PIX_FMT_NV42
 
- V4L2_PIX_FMT_NV61
 
- V4L2_PIX_FMT_NV61M
 
- V4L2_PIX_FMT_OV511
 
- V4L2_PIX_FMT_OV518
 
- V4L2_PIX_FMT_PAC207
 
- V4L2_PIX_FMT_PAL8
 
- V4L2_PIX_FMT_PJPG
 
- V4L2_PIX_FMT_PRIV_MAGIC
 
- V4L2_PIX_FMT_PWC1
 
- V4L2_PIX_FMT_PWC2
 
- V4L2_PIX_FMT_RGB24
 
- V4L2_PIX_FMT_RGB32
 
- V4L2_PIX_FMT_RGB332
 
- V4L2_PIX_FMT_RGB444
 
- V4L2_PIX_FMT_RGB555
 
- V4L2_PIX_FMT_RGB555X
 
- V4L2_PIX_FMT_RGB565
 
- V4L2_PIX_FMT_RGB565X
 
- V4L2_PIX_FMT_RGBA32
 
- V4L2_PIX_FMT_RGBA444
 
- V4L2_PIX_FMT_RGBA555
 
- V4L2_PIX_FMT_RGBX32
 
- V4L2_PIX_FMT_RGBX444
 
- V4L2_PIX_FMT_RGBX555
 
- V4L2_PIX_FMT_S5C_UYVY_JPG
 
- V4L2_PIX_FMT_SBGGR10
 
- V4L2_PIX_FMT_SBGGR10ALAW8
 
- V4L2_PIX_FMT_SBGGR10DPCM8
 
- V4L2_PIX_FMT_SBGGR10P
 
- V4L2_PIX_FMT_SBGGR12
 
- V4L2_PIX_FMT_SBGGR12P
 
- V4L2_PIX_FMT_SBGGR14P
 
- V4L2_PIX_FMT_SBGGR16
 
- V4L2_PIX_FMT_SBGGR8
 
- V4L2_PIX_FMT_SE401
 
- V4L2_PIX_FMT_SGBRG10
 
- V4L2_PIX_FMT_SGBRG10ALAW8
 
- V4L2_PIX_FMT_SGBRG10DPCM8
 
- V4L2_PIX_FMT_SGBRG10P
 
- V4L2_PIX_FMT_SGBRG12
 
- V4L2_PIX_FMT_SGBRG12P
 
- V4L2_PIX_FMT_SGBRG14P
 
- V4L2_PIX_FMT_SGBRG16
 
- V4L2_PIX_FMT_SGBRG8
 
- V4L2_PIX_FMT_SGRBG10
 
- V4L2_PIX_FMT_SGRBG10ALAW8
 
- V4L2_PIX_FMT_SGRBG10DPCM8
 
- V4L2_PIX_FMT_SGRBG10P
 
- V4L2_PIX_FMT_SGRBG12
 
- V4L2_PIX_FMT_SGRBG12P
 
- V4L2_PIX_FMT_SGRBG14P
 
- V4L2_PIX_FMT_SGRBG16
 
- V4L2_PIX_FMT_SGRBG8
 
- V4L2_PIX_FMT_SN9C10X
 
- V4L2_PIX_FMT_SN9C2028
 
- V4L2_PIX_FMT_SN9C20X_I420
 
- V4L2_PIX_FMT_SPCA501
 
- V4L2_PIX_FMT_SPCA505
 
- V4L2_PIX_FMT_SPCA508
 
- V4L2_PIX_FMT_SPCA561
 
- V4L2_PIX_FMT_SQ905C
 
- V4L2_PIX_FMT_SRGGB10
 
- V4L2_PIX_FMT_SRGGB10ALAW8
 
- V4L2_PIX_FMT_SRGGB10DPCM8
 
- V4L2_PIX_FMT_SRGGB10P
 
- V4L2_PIX_FMT_SRGGB12
 
- V4L2_PIX_FMT_SRGGB12P
 
- V4L2_PIX_FMT_SRGGB14P
 
- V4L2_PIX_FMT_SRGGB16
 
- V4L2_PIX_FMT_SRGGB8
 
- V4L2_PIX_FMT_STV0680
 
- V4L2_PIX_FMT_SUNXI_TILED_NV12
 
- V4L2_PIX_FMT_TM6000
 
- V4L2_PIX_FMT_UV8
 
- V4L2_PIX_FMT_UYVY
 
- V4L2_PIX_FMT_VC1_ANNEX_G
 
- V4L2_PIX_FMT_VC1_ANNEX_L
 
- V4L2_PIX_FMT_VP8
 
- V4L2_PIX_FMT_VP8_FRAME
 
- V4L2_PIX_FMT_VP9
 
- V4L2_PIX_FMT_VUYA32
 
- V4L2_PIX_FMT_VUYX32
 
- V4L2_PIX_FMT_VYUY
 
- V4L2_PIX_FMT_WNVA
 
- V4L2_PIX_FMT_XBGR32
 
- V4L2_PIX_FMT_XBGR444
 
- V4L2_PIX_FMT_XBGR555
 
- V4L2_PIX_FMT_XRGB32
 
- V4L2_PIX_FMT_XRGB444
 
- V4L2_PIX_FMT_XRGB555
 
- V4L2_PIX_FMT_XRGB555X
 
- V4L2_PIX_FMT_XVID
 
- V4L2_PIX_FMT_XYUV32
 
- V4L2_PIX_FMT_Y10
 
- V4L2_PIX_FMT_Y10BPACK
 
- V4L2_PIX_FMT_Y10P
 
- V4L2_PIX_FMT_Y12
 
- V4L2_PIX_FMT_Y12I
 
- V4L2_PIX_FMT_Y16
 
- V4L2_PIX_FMT_Y16_BE
 
- V4L2_PIX_FMT_Y4
 
- V4L2_PIX_FMT_Y41P
 
- V4L2_PIX_FMT_Y6
 
- V4L2_PIX_FMT_Y8I
 
- V4L2_PIX_FMT_YUV32
 
- V4L2_PIX_FMT_YUV410
 
- V4L2_PIX_FMT_YUV411P
 
- V4L2_PIX_FMT_YUV420
 
- V4L2_PIX_FMT_YUV420M
 
- V4L2_PIX_FMT_YUV422M
 
- V4L2_PIX_FMT_YUV422P
 
- V4L2_PIX_FMT_YUV444
 
- V4L2_PIX_FMT_YUV444M
 
- V4L2_PIX_FMT_YUV555
 
- V4L2_PIX_FMT_YUV565
 
- V4L2_PIX_FMT_YUYV
 
- V4L2_PIX_FMT_YVU410
 
- V4L2_PIX_FMT_YVU420
 
- V4L2_PIX_FMT_YVU420M
 
- V4L2_PIX_FMT_YVU422M
 
- V4L2_PIX_FMT_YVU444M
 
- V4L2_PIX_FMT_YVYU
 
- V4L2_PIX_FMT_YYUV
 
- V4L2_PIX_FMT_Z16
 
- V4L2_PREEMPHASIS_50_uS
 
- V4L2_PREEMPHASIS_75_uS
 
- V4L2_PREEMPHASIS_DISABLED
 
- V4L2_PRIORITY_BACKGROUND
 
- V4L2_PRIORITY_DEFAULT
 
- V4L2_PRIORITY_INTERACTIVE
 
- V4L2_PRIORITY_RECORD
 
- V4L2_PRIORITY_UNSET
 
- V4L2_QUANTIZATION_DEFAULT
 
- V4L2_QUANTIZATION_FULL_RANGE
 
- V4L2_QUANTIZATION_LIM_RANGE
 
- V4L2_RDS_BLOCK_A
 
- V4L2_RDS_BLOCK_B
 
- V4L2_RDS_BLOCK_C
 
- V4L2_RDS_BLOCK_CORRECTED
 
- V4L2_RDS_BLOCK_C_ALT
 
- V4L2_RDS_BLOCK_D
 
- V4L2_RDS_BLOCK_ERROR
 
- V4L2_RDS_BLOCK_INVALID
 
- V4L2_RDS_BLOCK_MSK
 
- V4L2_SCENE_MODE_BACKLIGHT
 
- V4L2_SCENE_MODE_BEACH_SNOW
 
- V4L2_SCENE_MODE_CANDLE_LIGHT
 
- V4L2_SCENE_MODE_DAWN_DUSK
 
- V4L2_SCENE_MODE_FALL_COLORS
 
- V4L2_SCENE_MODE_FIREWORKS
 
- V4L2_SCENE_MODE_LANDSCAPE
 
- V4L2_SCENE_MODE_NIGHT
 
- V4L2_SCENE_MODE_NONE
 
- V4L2_SCENE_MODE_PARTY_INDOOR
 
- V4L2_SCENE_MODE_PORTRAIT
 
- V4L2_SCENE_MODE_SPORTS
 
- V4L2_SCENE_MODE_SUNSET
 
- V4L2_SCENE_MODE_TEXT
 
- V4L2_SDR_FMT_CS14LE
 
- V4L2_SDR_FMT_CS8
 
- V4L2_SDR_FMT_CU16LE
 
- V4L2_SDR_FMT_CU8
 
- V4L2_SDR_FMT_PCU16BE
 
- V4L2_SDR_FMT_PCU18BE
 
- V4L2_SDR_FMT_PCU20BE
 
- V4L2_SDR_FMT_RU12LE
 
- V4L2_SEL_FLAG_GE
 
- V4L2_SEL_FLAG_KEEP_CONFIG
 
- V4L2_SEL_FLAG_LE
 
- V4L2_SEL_TGT_COMPOSE
 
- V4L2_SEL_TGT_COMPOSE_ACTIVE
 
- V4L2_SEL_TGT_COMPOSE_BOUNDS
 
- V4L2_SEL_TGT_COMPOSE_DEFAULT
 
- V4L2_SEL_TGT_COMPOSE_PADDED
 
- V4L2_SEL_TGT_CROP
 
- V4L2_SEL_TGT_CROP_ACTIVE
 
- V4L2_SEL_TGT_CROP_BOUNDS
 
- V4L2_SEL_TGT_CROP_DEFAULT
 
- V4L2_SEL_TGT_NATIVE_SIZE
 
- V4L2_SLICED_CAPTION_525
 
- V4L2_SLICED_TELETEXT_B
 
- V4L2_SLICED_VBI_525
 
- V4L2_SLICED_VBI_625
 
- V4L2_SLICED_VPS
 
- V4L2_SLICED_WSS_625
 
- V4L2_SMIAPP_TEST_PATTERN_MODE_COLOUR_BARS
 
- V4L2_SMIAPP_TEST_PATTERN_MODE_COLOUR_BARS_GREY
 
- V4L2_SMIAPP_TEST_PATTERN_MODE_DISABLED
 
- V4L2_SMIAPP_TEST_PATTERN_MODE_PN9
 
- V4L2_SMIAPP_TEST_PATTERN_MODE_SOLID_COLOUR
 
- V4L2_STD_525_60
 
- V4L2_STD_625_50
 
- V4L2_STD_A2
 
- V4L2_STD_A2_A
 
- V4L2_STD_A2_B
 
- V4L2_STD_ALL
 
- V4L2_STD_AM
 
- V4L2_STD_ATSC
 
- V4L2_STD_ATSC_16_VSB
 
- V4L2_STD_ATSC_8_VSB
 
- V4L2_STD_AUDIO
 
- V4L2_STD_B
 
- V4L2_STD_BG
 
- V4L2_STD_BTSC
 
- V4L2_STD_DK
 
- V4L2_STD_EIAJ
 
- V4L2_STD_G
 
- V4L2_STD_GH
 
- V4L2_STD_H
 
- V4L2_STD_L
 
- V4L2_STD_MN
 
- V4L2_STD_MTS
 
- V4L2_STD_NICAM
 
- V4L2_STD_NICAM_A
 
- V4L2_STD_NICAM_B
 
- V4L2_STD_NTSC
 
- V4L2_STD_NTSC_443
 
- V4L2_STD_NTSC_M
 
- V4L2_STD_NTSC_M_JP
 
- V4L2_STD_NTSC_M_KR
 
- V4L2_STD_PAL
 
- V4L2_STD_PAL_60
 
- V4L2_STD_PAL_B
 
- V4L2_STD_PAL_B1
 
- V4L2_STD_PAL_BG
 
- V4L2_STD_PAL_BG_A2_A
 
- V4L2_STD_PAL_BG_A2_B
 
- V4L2_STD_PAL_BG_NICAM_A
 
- V4L2_STD_PAL_BG_NICAM_B
 
- V4L2_STD_PAL_D
 
- V4L2_STD_PAL_D1
 
- V4L2_STD_PAL_DK
 
- V4L2_STD_PAL_DK_A2
 
- V4L2_STD_PAL_DK_NICAM
 
- V4L2_STD_PAL_G
 
- V4L2_STD_PAL_H
 
- V4L2_STD_PAL_I
 
- V4L2_STD_PAL_K
 
- V4L2_STD_PAL_M
 
- V4L2_STD_PAL_N
 
- V4L2_STD_PAL_Nc
 
- V4L2_STD_PAL_SECAM
 
- V4L2_STD_SECAM
 
- V4L2_STD_SECAM_B
 
- V4L2_STD_SECAM_D
 
- V4L2_STD_SECAM_DK
 
- V4L2_STD_SECAM_G
 
- V4L2_STD_SECAM_H
 
- V4L2_STD_SECAM_K
 
- V4L2_STD_SECAM_K1
 
- V4L2_STD_SECAM_K3
 
- V4L2_STD_SECAM_L
 
- V4L2_STD_SECAM_LC
 
- V4L2_STD_SECAM_L_AM
 
- V4L2_STD_SECAM_L_NICAM
 
- V4L2_STD_UNKNOWN
 
- V4L2_SUBDEV_FL_HAS_DEVNODE
 
- V4L2_SUBDEV_FL_HAS_EVENTS
 
- V4L2_SUBDEV_FL_IS_I2C
 
- V4L2_SUBDEV_FL_IS_SPI
 
- V4L2_SUBDEV_FORMAT_ACTIVE
 
- V4L2_SUBDEV_FORMAT_TRY
 
- V4L2_SUBDEV_HAS_OP
 
- V4L2_SUBDEV_IO_PIN_ACTIVE_LOW
 
- V4L2_SUBDEV_IO_PIN_DISABLE
 
- V4L2_SUBDEV_IO_PIN_INPUT
 
- V4L2_SUBDEV_IO_PIN_OUTPUT
 
- V4L2_SUBDEV_IO_PIN_SET_VALUE
 
- V4L2_SUBDEV_IR_MODE_PULSE_WIDTH
 
- V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED
 
- V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ
 
- V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN
 
- V4L2_SUBDEV_IR_RX_NOTIFY
 
- V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN
 
- V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ
 
- V4L2_SUBDEV_IR_TX_NOTIFY
 
- V4L2_SUBDEV_NAME_SIZE
 
- V4L2_SUBDEV_SEL_FLAG_KEEP_CONFIG
 
- V4L2_SUBDEV_SEL_FLAG_SIZE_GE
 
- V4L2_SUBDEV_SEL_FLAG_SIZE_LE
 
- V4L2_SUBDEV_SEL_TGT_COMPOSE_ACTUAL
 
- V4L2_SUBDEV_SEL_TGT_COMPOSE_BOUNDS
 
- V4L2_SUBDEV_SEL_TGT_CROP_ACTUAL
 
- V4L2_SUBDEV_SEL_TGT_CROP_BOUNDS
 
- V4L2_TCH_FMT_DELTA_TD08
 
- V4L2_TCH_FMT_DELTA_TD16
 
- V4L2_TCH_FMT_TU08
 
- V4L2_TCH_FMT_TU16
 
- V4L2_TC_FLAG_COLORFRAME
 
- V4L2_TC_FLAG_DROPFRAME
 
- V4L2_TC_TYPE_24FPS
 
- V4L2_TC_TYPE_25FPS
 
- V4L2_TC_TYPE_30FPS
 
- V4L2_TC_TYPE_50FPS
 
- V4L2_TC_TYPE_60FPS
 
- V4L2_TC_USERBITS_8BITCHARS
 
- V4L2_TC_USERBITS_USERDEFINED
 
- V4L2_TC_USERBITS_field
 
- V4L2_TUNER_ADC
 
- V4L2_TUNER_ANALOG_TV
 
- V4L2_TUNER_CAP_1HZ
 
- V4L2_TUNER_CAP_FREQ_BANDS
 
- V4L2_TUNER_CAP_HWSEEK_BOUNDED
 
- V4L2_TUNER_CAP_HWSEEK_PROG_LIM
 
- V4L2_TUNER_CAP_HWSEEK_WRAP
 
- V4L2_TUNER_CAP_LANG1
 
- V4L2_TUNER_CAP_LANG2
 
- V4L2_TUNER_CAP_LOW
 
- V4L2_TUNER_CAP_NORM
 
- V4L2_TUNER_CAP_RDS
 
- V4L2_TUNER_CAP_RDS_BLOCK_IO
 
- V4L2_TUNER_CAP_RDS_CONTROLS
 
- V4L2_TUNER_CAP_SAP
 
- V4L2_TUNER_CAP_STEREO
 
- V4L2_TUNER_DIGITAL_TV
 
- V4L2_TUNER_MODE_LANG1
 
- V4L2_TUNER_MODE_LANG1_LANG2
 
- V4L2_TUNER_MODE_LANG2
 
- V4L2_TUNER_MODE_MONO
 
- V4L2_TUNER_MODE_SAP
 
- V4L2_TUNER_MODE_STEREO
 
- V4L2_TUNER_RADIO
 
- V4L2_TUNER_RF
 
- V4L2_TUNER_SDR
 
- V4L2_TUNER_SUB_LANG1
 
- V4L2_TUNER_SUB_LANG2
 
- V4L2_TUNER_SUB_MONO
 
- V4L2_TUNER_SUB_RDS
 
- V4L2_TUNER_SUB_SAP
 
- V4L2_TUNER_SUB_STEREO
 
- V4L2_TYPE_IS_MULTIPLANAR
 
- V4L2_TYPE_IS_OUTPUT
 
- V4L2_VBI_INTERLACED
 
- V4L2_VBI_ITU_525_F1_START
 
- V4L2_VBI_ITU_525_F2_START
 
- V4L2_VBI_ITU_625_F1_START
 
- V4L2_VBI_ITU_625_F2_START
 
- V4L2_VBI_UNSYNC
 
- V4L2_VP8_FRAME_HEADER_FLAG_EXPERIMENTAL
 
- V4L2_VP8_FRAME_HEADER_FLAG_KEY_FRAME
 
- V4L2_VP8_FRAME_HEADER_FLAG_MB_NO_SKIP_COEFF
 
- V4L2_VP8_FRAME_HEADER_FLAG_SHOW_FRAME
 
- V4L2_VP8_FRAME_HEADER_FLAG_SIGN_BIAS_ALT
 
- V4L2_VP8_FRAME_HEADER_FLAG_SIGN_BIAS_GOLDEN
 
- V4L2_VP8_LF_FILTER_TYPE_SIMPLE
 
- V4L2_VP8_LF_HEADER_ADJ_ENABLE
 
- V4L2_VP8_LF_HEADER_DELTA_UPDATE
 
- V4L2_VP8_SEGMENT_HEADER_FLAG_DELTA_VALUE_MODE
 
- V4L2_VP8_SEGMENT_HEADER_FLAG_ENABLED
 
- V4L2_VP8_SEGMENT_HEADER_FLAG_UPDATE_FEATURE_DATA
 
- V4L2_VP8_SEGMENT_HEADER_FLAG_UPDATE_MAP
 
- V4L2_WHITE_BALANCE_AUTO
 
- V4L2_WHITE_BALANCE_CLOUDY
 
- V4L2_WHITE_BALANCE_DAYLIGHT
 
- V4L2_WHITE_BALANCE_FLASH
 
- V4L2_WHITE_BALANCE_FLUORESCENT
 
- V4L2_WHITE_BALANCE_FLUORESCENT_H
 
- V4L2_WHITE_BALANCE_HORIZON
 
- V4L2_WHITE_BALANCE_INCANDESCENT
 
- V4L2_WHITE_BALANCE_MANUAL
 
- V4L2_WHITE_BALANCE_SHADE
 
- V4L2_XFER_FUNC_709
 
- V4L2_XFER_FUNC_ADOBERGB
 
- V4L2_XFER_FUNC_DCI_P3
 
- V4L2_XFER_FUNC_DEFAULT
 
- V4L2_XFER_FUNC_NONE
 
- V4L2_XFER_FUNC_OPRGB
 
- V4L2_XFER_FUNC_SMPTE2084
 
- V4L2_XFER_FUNC_SMPTE240M
 
- V4L2_XFER_FUNC_SRGB
 
- V4L2_YCBCR_ENC_601
 
- V4L2_YCBCR_ENC_709
 
- V4L2_YCBCR_ENC_BT2020
 
- V4L2_YCBCR_ENC_BT2020_CONST_LUM
 
- V4L2_YCBCR_ENC_DEFAULT
 
- V4L2_YCBCR_ENC_SMPTE240M
 
- V4L2_YCBCR_ENC_SYCC
 
- V4L2_YCBCR_ENC_XV601
 
- V4L2_YCBCR_ENC_XV709
 
- V4_DESC
 
- V4_PSR_T_BIT
 
- V4_SHADERS_PER_COREGROUP
 
- V4_STATID
 
- V5
 
- V5_1610_GPIO24
 
- V5_1610_MMC2_DATDIR0
 
- V5_1710_MCLK_OFF
 
- V5_1710_MCLK_ON
 
- V5_DESC
 
- V5_STATID
 
- V6
 
- V6_111SF_GPO_CTRL_REG
 
- V6_656_I2S_BUFF_STATUS_REG
 
- V6_656_OVERFLOW_MASK_BIT
 
- V6_ATSC_CONFIG_REG
 
- V6_CODE_RATE_TPS_MASK
 
- V6_CODE_RATE_TPS_REG
 
- V6_CP_LOCK_DET_MASK
 
- V6_CP_LOCK_DET_REG
 
- V6_CP_TPS_REG
 
- V6_DIG_CLK_FREQ_SEL_REG
 
- V6_DIG_RFREFSELECT_REG
 
- V6_DIG_RF_PWR_LSB_REG
 
- V6_DIG_RF_PWR_MSB_REG
 
- V6_DIG_XTAL_BIAS_REG
 
- V6_DIG_XTAL_ENABLE_REG
 
- V6_ENABLE_LOOP_THRU
 
- V6_ENABLE_PIN_MUX
 
- V6_FEC_PER_CLR_MASK
 
- V6_FEC_PER_CLR_REG
 
- V6_FEC_PER_COUNT_REG
 
- V6_FEC_PER_SCALE_MASK
 
- V6_FEC_PER_SCALE_REG
 
- V6_FORCE_NFFT_CPSIZE_REG
 
- V6_GPO_0_MASK
 
- V6_GPO_1_MASK
 
- V6_GPO_CTRL_REG
 
- V6_I2S_NUM_SAMPLES_REG
 
- V6_I2S_OVERFLOW_MASK_BIT
 
- V6_I2S_STREAM_END_BIT_REG
 
- V6_I2S_STREAM_START_BIT_REG
 
- V6_IDAC_HYSTERESIS_REG
 
- V6_IDAC_SETTINGS_REG
 
- V6_INITACQ_NODETECT_REG
 
- V6_INVERTED_CLK_PHASE
 
- V6_INVERTED_MPEG_SYNC
 
- V6_INVERTED_MPEG_VALID
 
- V6_IRQ_STATUS_REG
 
- V6_MODE_TPS_REG
 
- V6_MODORDER_TPS_REG
 
- V6_MPEG_INOUT_BIT_ORDER_CTRL_REG
 
- V6_MPEG_IN_CLK_INV_REG
 
- V6_MPEG_IN_CTRL_REG
 
- V6_MPEG_IN_DATA_PARALLEL
 
- V6_MPEG_IN_DATA_SERIAL
 
- V6_MPEG_SER_MSB_FIRST
 
- V6_N_ACCUMULATE_REG
 
- V6_PARAM_CONSTELLATION_MASK
 
- V6_PARAM_FFT_MODE_MASK
 
- V6_PARAM_GI_MASK
 
- V6_PARAM_TPS_LOCK_MASK
 
- V6_PIN_MUX_MODE_REG
 
- V6_REF_SYNTH_INT_REG
 
- V6_REF_SYNTH_REMAIN_REG
 
- V6_RF_LOCK_STATUS_REG
 
- V6_RS_AVG_ERRORS_LSB_REG
 
- V6_RS_AVG_ERRORS_MSB_REG
 
- V6_RS_LOCK_DET_REG
 
- V6_SNR_RB_LSB_REG
 
- V6_SNR_RB_MSB_REG
 
- V6_STATID
 
- V6_SYNC_LOCK_REG
 
- V6_TPS_HIERACHY_REG
 
- V6_TPS_HIERARCHY_INFO_MASK
 
- V6_TPS_LOCK_REG
 
- V6_TUNER_IF_FCW_BYP_REG
 
- V6_TUNER_IF_FCW_REG
 
- V6_TUNER_IF_SEL_REG
 
- V6_TUNER_LOOP_THRU_CONTROL_REG
 
- V6_TUNER_LOOP_THRU_CTRL_REG
 
- V6_USB0_TXD
 
- V6_USB2_TXD
 
- V6_XTAL_CAP_REG
 
- V6_XTAL_CLK_OUT_GAIN_REG
 
- V7
 
- V7M_PSR_T_BIT
 
- V7M_SCB_AIRCR
 
- V7M_SCB_AIRCR_SYSRESETREQ
 
- V7M_SCB_AIRCR_VECTKEY
 
- V7M_SCB_BPIALL
 
- V7M_SCB_CCR
 
- V7M_SCB_CCR_BP
 
- V7M_SCB_CCR_DC
 
- V7M_SCB_CCR_IC
 
- V7M_SCB_CCR_STKALIGN
 
- V7M_SCB_CCSIDR
 
- V7M_SCB_CLIDR
 
- V7M_SCB_CPUID
 
- V7M_SCB_CSSELR
 
- V7M_SCB_CTR
 
- V7M_SCB_DCCIMVAC
 
- V7M_SCB_DCCISW
 
- V7M_SCB_DCCMVAC
 
- V7M_SCB_DCCMVAU
 
- V7M_SCB_DCCSW
 
- V7M_SCB_DCIMVAC
 
- V7M_SCB_DCISW
 
- V7M_SCB_ICIALLU
 
- V7M_SCB_ICIMVAU
 
- V7M_SCB_ICSR
 
- V7M_SCB_ICSR_PENDSVCLR
 
- V7M_SCB_ICSR_PENDSVSET
 
- V7M_SCB_ICSR_RETTOBASE
 
- V7M_SCB_SCR
 
- V7M_SCB_SCR_SLEEPDEEP
 
- V7M_SCB_SHCSR
 
- V7M_SCB_SHCSR_BUSFAULTENA
 
- V7M_SCB_SHCSR_MEMFAULTENA
 
- V7M_SCB_SHCSR_USGFAULTENA
 
- V7M_SCB_SHPR2
 
- V7M_SCB_SHPR3
 
- V7M_SCB_VTOR
 
- V7M_SCS_ICTR
 
- V7M_SCS_ICTR_INTLINESNUM_MASK
 
- V7M_xPSR_EXCEPTIONNO
 
- V7M_xPSR_FRAMEPTRALIGN
 
- V7_BLOCK_NUMBER_OFFSET
 
- V7_BOOTLOADER_ID_OFFSET
 
- V7_COMMAND_OFFSET
 
- V7_FLASH_STATUS_OFFSET
 
- V7_LINK_MAX
 
- V7_MAXSIZE
 
- V7_NFILES
 
- V7_NICFREE
 
- V7_NICINOD
 
- V7_PACKET_ID
 
- V7_PACKET_ID_IDLE
 
- V7_PACKET_ID_MULTI
 
- V7_PACKET_ID_NEW
 
- V7_PACKET_ID_TWO
 
- V7_PACKET_ID_UNKNOWN
 
- V7_PARTITION_ID_OFFSET
 
- V7_PAYLOAD_OFFSET
 
- V7_STATID
 
- V7_TRANSFER_LENGTH_OFFSET
 
- V8
 
- V8_1610_MMC2_DAT1
 
- V8_MEMORY_EXTENDED
 
- V8_MEMORY_PAGE_DVB_CI
 
- V8_MEMORY_PAGE_DVB_DS
 
- V8_MEMORY_PAGE_FLASH
 
- V8_MEMORY_PAGE_MASK
 
- V8_MEMORY_PAGE_MULTI2
 
- V8_MEMORY_PAGE_SIZE
 
- V8_SPI_MODE_REG
 
- V8_table
 
- V9
 
- V9FS_ACCESS_ANY
 
- V9FS_ACCESS_CLIENT
 
- V9FS_ACCESS_MASK
 
- V9FS_ACCESS_SINGLE
 
- V9FS_ACCESS_USER
 
- V9FS_ACL_MASK
 
- V9FS_DEFANAME
 
- V9FS_DEFGID
 
- V9FS_DEFUID
 
- V9FS_DEFUSER
 
- V9FS_I
 
- V9FS_INO_INVALID_ATTR
 
- V9FS_MAGIC
 
- V9FS_PORT
 
- V9FS_POSIX_ACL
 
- V9FS_PROTO_2000L
 
- V9FS_PROTO_2000U
 
- V9FS_STAT2INODE_KEEP_ISIZE
 
- V9_1610_GPIO7
 
- V9_1610_MMC2_CMDDIR
 
- V9_PIPE_PER_MEC
 
- V9_QUEUES_PER_PIPE_MEC
 
- V9_STRUCTS_H_
 
- V9_USB0_SPEED
 
- V9_USB0_SUSP
 
- VA
 
- VAA
 
- VACK_MARK
 
- VACTIVE_LO
 
- VACTIVE_MASK
 
- VACTIVE_SHIFT
 
- VACT_LEN
 
- VADC5_MAX_CODE
 
- VADC_ABSOLUTE_RANGE_UV
 
- VADC_ACCESS
 
- VADC_ACCESS_DATA
 
- VADC_ADC_CH_SEL_CTL
 
- VADC_ADC_DIG_DEC_RATIO_SEL_SHIFT
 
- VADC_ADC_DIG_PARAM
 
- VADC_ADC_TRIM_EN
 
- VADC_AMUX_PU1
 
- VADC_AMUX_PU2
 
- VADC_AMUX_TRIM_EN
 
- VADC_AVG_SAMPLES_MAX
 
- VADC_CALIB_ABSOLUTE
 
- VADC_CALIB_RATIOMETRIC
 
- VADC_CHAN
 
- VADC_CHAN_MAX
 
- VADC_CHAN_MIN
 
- VADC_CHAN_NO_SCALE
 
- VADC_CHAN_TEMP
 
- VADC_CHAN_VOLT
 
- VADC_CHG_TEMP
 
- VADC_CONV_REQ
 
- VADC_CONV_REQ_SET
 
- VADC_CONV_TIME_MAX_US
 
- VADC_CONV_TIME_MIN_US
 
- VADC_DATA
 
- VADC_DCIN
 
- VADC_DECIMATION_MAX
 
- VADC_DECIMATION_MIN
 
- VADC_DEF_AVG_SAMPLES
 
- VADC_DEF_CALIB_TYPE
 
- VADC_DEF_DECIMATION
 
- VADC_DEF_HW_SETTLE_TIME
 
- VADC_DEF_PRESCALING
 
- VADC_DIE_TEMP
 
- VADC_EN_CTL1
 
- VADC_EN_CTL1_SET
 
- VADC_FAST_AVG_CTL
 
- VADC_FAST_AVG_EN
 
- VADC_FAST_AVG_EN_SET
 
- VADC_FOLLOW_WARM_RB
 
- VADC_GND_REF
 
- VADC_HW_SETTLE_DELAY
 
- VADC_HW_SETTLE_DELAY_MAX
 
- VADC_HW_SETTLE_SAMPLES_MAX
 
- VADC_LR_MUX10_PU1_AMUX_USB_ID
 
- VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID
 
- VADC_LR_MUX10_PU2_AMUX_USB_ID
 
- VADC_LR_MUX10_USB_ID
 
- VADC_LR_MUX1_BAT_THERM
 
- VADC_LR_MUX1_PU1_BAT_THERM
 
- VADC_LR_MUX1_PU1_PU2_BAT_THERM
 
- VADC_LR_MUX1_PU2_BAT_THERM
 
- VADC_LR_MUX2_BAT_ID
 
- VADC_LR_MUX2_PU1_BAT_ID
 
- VADC_LR_MUX2_PU1_PU2_BAT_ID
 
- VADC_LR_MUX2_PU2_BAT_ID
 
- VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM
 
- VADC_LR_MUX3_BUF_PU1_XO_THERM
 
- VADC_LR_MUX3_BUF_PU2_XO_THERM
 
- VADC_LR_MUX3_BUF_XO_THERM
 
- VADC_LR_MUX3_PU1_PU2_XO_THERM
 
- VADC_LR_MUX3_PU1_XO_THERM
 
- VADC_LR_MUX3_PU2_XO_THERM
 
- VADC_LR_MUX3_XO_THERM
 
- VADC_LR_MUX4_AMUX_THM1
 
- VADC_LR_MUX4_PU1_AMUX_THM1
 
- VADC_LR_MUX4_PU1_PU2_AMUX_THM1
 
- VADC_LR_MUX4_PU2_AMUX_THM1
 
- VADC_LR_MUX5_AMUX_THM2
 
- VADC_LR_MUX5_PU1_AMUX_THM2
 
- VADC_LR_MUX5_PU1_PU2_AMUX_THM2
 
- VADC_LR_MUX5_PU2_AMUX_THM2
 
- VADC_LR_MUX6_AMUX_THM3
 
- VADC_LR_MUX6_PU1_AMUX_THM3
 
- VADC_LR_MUX6_PU1_PU2_AMUX_THM3
 
- VADC_LR_MUX6_PU2_AMUX_THM3
 
- VADC_LR_MUX7_HW_ID
 
- VADC_LR_MUX7_PU1_AMUX_HW_ID
 
- VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID
 
- VADC_LR_MUX7_PU2_AMUX_HW_ID
 
- VADC_LR_MUX8_AMUX_THM4
 
- VADC_LR_MUX8_PU1_AMUX_THM4
 
- VADC_LR_MUX8_PU1_PU2_AMUX_THM4
 
- VADC_LR_MUX8_PU2_AMUX_THM4
 
- VADC_LR_MUX9_AMUX_THM5
 
- VADC_LR_MUX9_PU1_AMUX_THM5
 
- VADC_LR_MUX9_PU1_PU2_AMUX_THM5
 
- VADC_LR_MUX9_PU2_AMUX_THM5
 
- VADC_MAX_ADC_CODE
 
- VADC_MIN_ADC_CODE
 
- VADC_MODE_CTL
 
- VADC_NO_CHAN
 
- VADC_OP_MODE_NORMAL
 
- VADC_OP_MODE_SHIFT
 
- VADC_PERH_RESET_CTL3
 
- VADC_PERPH_SUBTYPE
 
- VADC_PERPH_SUBTYPE_VADC
 
- VADC_PERPH_TYPE
 
- VADC_PERPH_TYPE_ADC
 
- VADC_P_MUX10_1_1
 
- VADC_P_MUX10_1_3
 
- VADC_P_MUX11_1_1
 
- VADC_P_MUX11_1_3
 
- VADC_P_MUX12_1_1
 
- VADC_P_MUX12_1_3
 
- VADC_P_MUX13_1_1
 
- VADC_P_MUX13_1_3
 
- VADC_P_MUX14_1_1
 
- VADC_P_MUX14_1_3
 
- VADC_P_MUX15_1_1
 
- VADC_P_MUX15_1_3
 
- VADC_P_MUX16_1_1
 
- VADC_P_MUX16_1_3
 
- VADC_P_MUX1_1_1
 
- VADC_P_MUX1_1_3
 
- VADC_P_MUX2_1_1
 
- VADC_P_MUX2_1_3
 
- VADC_P_MUX3_1_1
 
- VADC_P_MUX3_1_3
 
- VADC_P_MUX4_1_1
 
- VADC_P_MUX4_1_3
 
- VADC_P_MUX5_1_1
 
- VADC_P_MUX5_1_3
 
- VADC_P_MUX6_1_1
 
- VADC_P_MUX6_1_3
 
- VADC_P_MUX7_1_1
 
- VADC_P_MUX7_1_3
 
- VADC_P_MUX8_1_1
 
- VADC_P_MUX8_1_3
 
- VADC_P_MUX9_1_1
 
- VADC_P_MUX9_1_3
 
- VADC_RATIOMETRIC_RANGE
 
- VADC_REF_1250MV
 
- VADC_REF_625MV
 
- VADC_REVISION2
 
- VADC_REVISION2_SUPPORTED_VADC
 
- VADC_SPARE1
 
- VADC_SPARE1_03
 
- VADC_SPARE2
 
- VADC_STATUS1
 
- VADC_STATUS1_EOC
 
- VADC_STATUS1_OP_MODE
 
- VADC_STATUS1_REQ_STS
 
- VADC_STATUS1_REQ_STS_EOC_MASK
 
- VADC_USBIN
 
- VADC_USB_ID_MV
 
- VADC_VBAT_SNS
 
- VADC_VCHG_SNS
 
- VADC_VCOIN
 
- VADC_VDD_VADC
 
- VADC_VSYS
 
- VADDR
 
- VADDR_FLAG_HUGE_POOL
 
- VADDR_FLAG_UPDATED_COUNT
 
- VADDR_HI_BIT
 
- VADOUT_L_MASK
 
- VADOUT_XN_H
 
- VADOUT_XN_L
 
- VADOUT_XP_H
 
- VADOUT_XP_L
 
- VADOUT_YN_H
 
- VADOUT_YN_L
 
- VADOUT_YP_H
 
- VADOUT_YP_L
 
- VADOUT_ZX_H
 
- VADOUT_ZX_L
 
- VADOUT_ZY_H
 
- VADOUT_ZY_L
 
- VAERR
 
- VAIO
 
- VAIO_RDESC_CONSTANT
 
- VAL
 
- VAL0
 
- VAL1
 
- VAL2
 
- VAL3
 
- VAL4
 
- VALID
 
- VALIDATE
 
- VALIDATE_ARGS
 
- VALIDATE_AUTH
 
- VALIDATE_BUF_SIZE
 
- VALIDATE_CUR_UNKNOWN
 
- VALIDATE_DESC
 
- VALIDATE_DESC_VOID
 
- VALIDATE_FLASH_AUTH
 
- VALIDATE_FLASH_NAME
 
- VALIDATE_HW_ERR
 
- VALIDATE_IMAGE
 
- VALIDATE_IMG_INCOMPLETE
 
- VALIDATE_IMG_READY
 
- VALIDATE_INCOMPLETE
 
- VALIDATE_INVALID_IMG
 
- VALIDATE_MSG_LEN
 
- VALIDATE_NO_OP
 
- VALIDATE_OUT_OF_WRNTY
 
- VALIDATE_PARAM_ERR
 
- VALIDATE_READY
 
- VALIDATE_TID
 
- VALIDATE_TMP_COMMIT
 
- VALIDATE_TMP_COMMIT_DL
 
- VALIDATE_TMP_UPDATE
 
- VALIDATE_TMP_UPDATE_DL
 
- VALID_0
 
- VALID_1
 
- VALID_10
 
- VALID_11
 
- VALID_12
 
- VALID_13
 
- VALID_14
 
- VALID_15
 
- VALID_2
 
- VALID_20
 
- VALID_3
 
- VALID_4
 
- VALID_40
 
- VALID_5
 
- VALID_6
 
- VALID_7
 
- VALID_8
 
- VALID_9
 
- VALID_AUDIO_IO_DIGITAL_LEVEL
 
- VALID_AUDIO_IO_MONITORING_LEVEL
 
- VALID_AUDIO_IO_MONITOR_LEVEL
 
- VALID_AUDIO_IO_MUTE_LEVEL
 
- VALID_AUDIO_IO_MUTE_MONITORING_1
 
- VALID_AUDIO_IO_MUTE_MONITORING_2
 
- VALID_AUDIO_IO_MUTE_MONITOR_1
 
- VALID_BIT
 
- VALID_BPP
 
- VALID_BPP124
 
- VALID_BPP1248
 
- VALID_CAPACITY_SEC
 
- VALID_CIPHER_BITMAP
 
- VALID_CMD_RESP_EL
 
- VALID_CMD_RESP_HEADER
 
- VALID_CPUID_INFO
 
- VALID_CRC_CNT_CRC_MASK
 
- VALID_CTRL
 
- VALID_DECODER
 
- VALID_DEVICE_ID
 
- VALID_DIP_WORDS
 
- VALID_DOUBLE_EXCEPTION_ADDRESS
 
- VALID_EVTCHN
 
- VALID_FLAGS
 
- VALID_FWNMI_BUFFER
 
- VALID_GUESTDBG_FLAGS
 
- VALID_ID
 
- VALID_INHERIT_FLAGS
 
- VALID_INIT_CRQ
 
- VALID_INIT_MSG
 
- VALID_INTR_BYTE
 
- VALID_INT_SOURCE
 
- VALID_IRQS
 
- VALID_LAPIC_ID
 
- VALID_LCN_RADIO
 
- VALID_MINOR
 
- VALID_MSIX_IDX
 
- VALID_N_RADIO
 
- VALID_OCM_ADDR
 
- VALID_OPEN_FLAGS
 
- VALID_PAGE
 
- VALID_PARTITION
 
- VALID_PROC_CXT_INFO_NUM
 
- VALID_PROC_ERR_INFO_NUM
 
- VALID_PROTECTION_FAULT_ENABLE_DEFAULT
 
- VALID_PROTECTION_FAULT_ENABLE_INTERRUPT
 
- VALID_RADIO
 
- VALID_SENSE
 
- VALID_SIGNAL
 
- VALID_SIG_EN
 
- VALID_SPEC_INVALID
 
- VALID_SPEC_NA
 
- VALID_SPEC_VALID
 
- VALID_STREAM_LEVEL_1_MASK
 
- VALID_STREAM_LEVEL_2_MASK
 
- VALID_STREAM_LEVEL_MASK
 
- VALID_STREAM_PAN_LEVEL_MASK
 
- VALID_TRANS_EVENT
 
- VALID_TS_RD_REG_MASK
 
- VALID_WAKEUPS
 
- VALID_XATTR_BLOCK_SIZE
 
- VALKYRIE_REG_PADSIZE
 
- VALLEYVIEW_CURSOR_MAX_WM
 
- VALLEYVIEW_FIFO_SIZE
 
- VALLEYVIEW_MAX_WM
 
- VALM
 
- VALR
 
- VALUE
 
- VALUES_16_COUNT
 
- VALUES_32_COUNT
 
- VALUES_64_COUNT
 
- VALUE_0_MASK
 
- VALUE_0_SHIFT
 
- VALUE_BITS
 
- VALUE_DWORD
 
- VALUE_HASH_SHIFT
 
- VALUE_INDEX_ACCESS_SINGLE
 
- VALUE_LENGTH
 
- VALUE_MASK
 
- VALUE_MASK_DWORD
 
- VALUE_MAXLEN
 
- VALUE_SAME_AS_ABOVE
 
- VALUE_SHIFT
 
- VALUE_UNIPERIF_CONFIG_MEM_FMT_16_0
 
- VALUE_UNIPERIF_CONFIG_MEM_FMT_16_16
 
- VALUE_UNIPERIF_CTRL_OPERATION_AUDIO_DATA
 
- VALUE_UNIPERIF_CTRL_OPERATION_CD_DATA
 
- VALUE_UNIPERIF_CTRL_OPERATION_ENC_DATA
 
- VALUE_UNIPERIF_CTRL_OPERATION_MUTE_PAUSE_BURST
 
- VALUE_UNIPERIF_CTRL_OPERATION_MUTE_PCM_NULL
 
- VALUE_UNIPERIF_CTRL_OPERATION_OFF
 
- VALUE_UNIPERIF_CTRL_OPERATION_PCM_DATA
 
- VALUE_UNIPERIF_CTRL_OPERATION_STANDBY
 
- VALUE_UNIPERIF_I2S_FMT_LR_POL_HIG
 
- VALUE_UNIPERIF_I2S_FMT_LR_POL_LOW
 
- VALUE_UNIPERIF_I2S_FMT_PADDING_I2S_MODE
 
- VALUE_UNIPERIF_I2S_FMT_PADDING_SONY_MODE
 
- VALUE_UNIPERIF_TDM_FS_REF_FREQ_16KHZ
 
- VALUE_UNIPERIF_TDM_FS_REF_FREQ_32KHZ
 
- VALUE_UNIPERIF_TDM_FS_REF_FREQ_48KHZ
 
- VALUE_UNIPERIF_TDM_FS_REF_FREQ_8KHZ
 
- VAL_BITS
 
- VAL_CBUS_MHL_DISCON
 
- VAL_DDC_CMD_DDC_CMD_ABORT
 
- VAL_DDC_CMD_DDC_CMD_CLEAR_FIFO
 
- VAL_DDC_CMD_ENH_DDC_READ_NO_ACK
 
- VAL_DISC_CTRL4
 
- VAL_DISC_STAT2_DEFAULT
 
- VAL_DISC_STAT2_MHL1_2
 
- VAL_DISC_STAT2_MHL3
 
- VAL_DISC_STAT2_RESERVED
 
- VAL_KEEPER_MODE_DEVICE
 
- VAL_KEEPER_MODE_HOST
 
- VAL_M3_CTRL_MHL1_2_VALUE
 
- VAL_M3_CTRL_MHL3_VALUE
 
- VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONG
 
- VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONGEST
 
- VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_WEAK
 
- VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_WEAKEST
 
- VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_734
 
- VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_740
 
- VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_747
 
- VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_754
 
- VAL_MHL_CBUS_CTL1_0888_OHM
 
- VAL_MHL_CBUS_CTL1_1115_OHM
 
- VAL_MHL_CBUS_CTL1_1378_OHM
 
- VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_1
 
- VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_10
 
- VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_2
 
- VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_2_PRIME
 
- VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_3
 
- VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_4
 
- VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_5
 
- VAL_MHL_PLL_CTL0_AUD_CLK_RATIO_5_6
 
- VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X
 
- VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_2X
 
- VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_4X
 
- VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_HALF_X
 
- VAL_PUP_20K
 
- VAL_PUP_5K
 
- VAL_PUP_OFF
 
- VAL_RGND_1K
 
- VAL_RGND_2K
 
- VAL_RGND_OPEN
 
- VAL_RGND_SHORT
 
- VAL_RX_HDMI_CTRL2_DEFVAL
 
- VAL_RX_HDMI_CTRL2_IDLE_CNT
 
- VAL_SET
 
- VAL_SH
 
- VAL_TDM_SYNCHRONIZED
 
- VAL_TERM
 
- VAL_TPI_COPP_LINK_STATUS_LINK_LOST
 
- VAL_TPI_COPP_LINK_STATUS_LINK_SUSPENDED
 
- VAL_TPI_COPP_LINK_STATUS_NORMAL
 
- VAL_TPI_COPP_LINK_STATUS_RENEGOTIATION_REQ
 
- VAL_TPI_FORMAT
 
- VAL_TPI_FORMAT_INTERNAL_RGB
 
- VAL_TPI_FORMAT_RGB
 
- VAL_TPI_FORMAT_YCBCR422
 
- VAL_TPI_FORMAT_YCBCR444
 
- VAL_TPI_INFO_FSEL_AUD
 
- VAL_TPI_INFO_FSEL_AVI
 
- VAL_TPI_INFO_FSEL_GEN
 
- VAL_TPI_INFO_FSEL_GEN2
 
- VAL_TPI_INFO_FSEL_MPG
 
- VAL_TPI_INFO_FSEL_SPD
 
- VAL_TPI_INFO_FSEL_VSI
 
- VAL_TPI_QUAN_RANGE_FULL
 
- VAL_TPI_QUAN_RANGE_LIMITED
 
- VAL_TX_ZONE_CTL1_TX_ZONE_CTRL_MODE
 
- VAL_TX_ZONE_CTL3_TX_ZONE_1_5GBPS
 
- VAL_TX_ZONE_CTL3_TX_ZONE_3GBPS
 
- VAL_TX_ZONE_CTL3_TX_ZONE_6GBPS
 
- VAL_WIDTH
 
- VANIR_A0_REV
 
- VANIR_B0_REV
 
- VANIR_C0_REV
 
- VANIR_C1_REV
 
- VANIR_C2_REV
 
- VANIR_REVISION_ID
 
- VAPEHIGHSPEEDVALTO_ERR
 
- VAPEOFFACCESS_ERR
 
- VAPEREGUVALTO_ERR
 
- VAPPLINE_END
 
- VAPPLINE_START
 
- VAP_ADD
 
- VAP_CAPABILITIES
 
- VAP_DELETE
 
- VAP_DYNAMIC_UPDATE
 
- VAP_INDEX_OFFSET
 
- VAP_PVS_STATE_FLUSH_REG
 
- VAP_UPDATE
 
- VAR
 
- VAR8
 
- VARDATASIZE
 
- VARIABLES
 
- VARIABLE_DATA
 
- VARIABLE_LENGTH_CMD
 
- VARIABLE_LENGTH_SZ
 
- VARIABLE_SETTINGS_TABLE_MAX
 
- VARIABLE_SETTINGS_TABLE_RESERVED
 
- VARIABLE_SETTINGS_TABLE_RX_PRESET_IDX
 
- VARIABLE_SETTINGS_TABLE_TX_PRESET_IDX
 
- VARIABLE_TS_CLOCK
 
- VARIANT_MV88F6180
 
- VARIANT_MV88F6190
 
- VARIANT_MV88F6192
 
- VARIANT_MV88F6281
 
- VARIANT_MV88F6282
 
- VARIANT_MV98DX1135
 
- VARIANT_MV98DX4122
 
- VARIAX_OFFSET_ACTIVATE
 
- VARIAX_STARTUP_ACTIVATE
 
- VARIAX_STARTUP_DELAY1
 
- VARIAX_STARTUP_DELAY3
 
- VARIAX_STARTUP_DELAY4
 
- VARIAX_STARTUP_SETUP
 
- VARIAX_STARTUP_VERSIONREQ
 
- VARIDECIMATE_SCB_ADDR
 
- VARI_DECIMATE_BUF0
 
- VARI_DECIMATE_BUF1
 
- VARMHIGHSPEEDACCESS_ERR
 
- VARMHIGHSPEEDVALTO_ERR
 
- VARMLOWSPEEDACCESS_ERR
 
- VARMLOWSPEEDVALTO_ERR
 
- VARMOFFACCESS_ERR
 
- VARMRETACCES_ERR
 
- VARMRETENTIONACCESS_ERR
 
- VARMRETENTIONVALTO_ERR
 
- VARYING_COMPONENT_USE_POINTCOORD_X
 
- VARYING_COMPONENT_USE_POINTCOORD_Y
 
- VARYING_COMPONENT_USE_UNUSED
 
- VARYING_COMPONENT_USE_USED
 
- VAR_APPEND
 
- VAR_BUFFER
 
- VAR_LEN_ARRAY
 
- VAR_MATCH
 
- VAR_NUM
 
- VAR_P
 
- VAR_PROC
 
- VAR_RECURSIVE
 
- VAR_SIMPLE
 
- VAR_START
 
- VAR_STRING
 
- VAR_TIME
 
- VAR_USED
 
- VAR_ZCTP
 
- VAR_ZDLE
 
- VAR_ZSAU
 
- VASSERT
 
- VAS_AMR
 
- VAS_AMR_OFFSET
 
- VAS_CASTOUT_REQ
 
- VAS_COP_TYPE_842
 
- VAS_COP_TYPE_842_HIPRI
 
- VAS_COP_TYPE_FAULT
 
- VAS_COP_TYPE_FTW
 
- VAS_COP_TYPE_GZIP
 
- VAS_COP_TYPE_GZIP_HIPRI
 
- VAS_COP_TYPE_MAX
 
- VAS_CURR_MSG_COUNT
 
- VAS_CURR_MSG_COUNT_OFFSET
 
- VAS_DMA_TYPE_INJECT
 
- VAS_DMA_TYPE_WRITE
 
- VAS_FAULT_TX_WIN
 
- VAS_FAULT_TX_WIN_OFFSET
 
- VAS_HVWC_SIZE
 
- VAS_HV_INTR_SRC_RA
 
- VAS_HV_INTR_SRC_RA_OFFSET
 
- VAS_INTR_DISABLE
 
- VAS_LDATA_STAMP
 
- VAS_LDATA_STAMP_CTL_OFFSET
 
- VAS_LDMA_CACHE_CTL_OFFSET
 
- VAS_LDMA_FIFO_DISABLE
 
- VAS_LDMA_TYPE
 
- VAS_LFIFO_BAR
 
- VAS_LFIFO_BAR_OFFSET
 
- VAS_LFIFO_SIZE
 
- VAS_LFIFO_SIZE_OFFSET
 
- VAS_LNOTIFY_AFTER_COUNT
 
- VAS_LNOTIFY_AFTER_COUNT_OFFSET
 
- VAS_LNOTIFY_CTL_OFFSET
 
- VAS_LNOTIFY_LPID
 
- VAS_LNOTIFY_LPID_OFFSET
 
- VAS_LNOTIFY_MAX_SCOPE
 
- VAS_LNOTIFY_MIN_SCOPE
 
- VAS_LNOTIFY_PID
 
- VAS_LNOTIFY_PID_OFFSET
 
- VAS_LNOTIFY_SCOPE_OFFSET
 
- VAS_LNOTIFY_TID
 
- VAS_LNOTIFY_TID_OFFSET
 
- VAS_LPID
 
- VAS_LPID_OFFSET
 
- VAS_LRFIFO_PUSH
 
- VAS_LRFIFO_PUSH_OFFSET
 
- VAS_LRFIFO_WIN_PTR_OFFSET
 
- VAS_LRX_WCRED
 
- VAS_LRX_WCRED_ADDER
 
- VAS_LRX_WCRED_ADDER_OFFSET
 
- VAS_LRX_WCRED_OFFSET
 
- VAS_LRX_WIN_ID
 
- VAS_NOTIFY_AFTER_2
 
- VAS_NOTIFY_AFTER_256
 
- VAS_NOTIFY_DISABLE
 
- VAS_NOTIFY_EARLY
 
- VAS_NOTIFY_NONE
 
- VAS_NOTIFY_OSU_INTR
 
- VAS_NX_UTIL
 
- VAS_NX_UTIL_ADDER
 
- VAS_NX_UTIL_ADDER_OFFSET
 
- VAS_NX_UTIL_OFFSET
 
- VAS_NX_UTIL_SE
 
- VAS_NX_UTIL_SE_OFFSET
 
- VAS_OSU_INTR_SRC_RA
 
- VAS_OSU_INTR_SRC_RA_OFFSET
 
- VAS_PAGE_MIGRATION_SELECT
 
- VAS_PID_ID
 
- VAS_PID_OFFSET
 
- VAS_PSWID_EA_HANDLE
 
- VAS_PSWID_OFFSET
 
- VAS_PUSH_TO_MEM
 
- VAS_RETRIES
 
- VAS_RXVD_BUF_COUNT
 
- VAS_RX_FIFO_SIZE_MAX
 
- VAS_RX_FIFO_SIZE_MIN
 
- VAS_RX_WCREDS_MAX
 
- VAS_SCOPE_GROUP
 
- VAS_SCOPE_LOCAL
 
- VAS_SCOPE_UNUSED
 
- VAS_SCOPE_VECTORED_GROUP
 
- VAS_SEIDR
 
- VAS_SEIDR_OFFSET
 
- VAS_SPARE1_OFFSET
 
- VAS_SPARE2_OFFSET
 
- VAS_SPARE3_OFFSET
 
- VAS_SPARE4_OFFSET
 
- VAS_SPARE5_OFFSET
 
- VAS_SPARE6_OFFSET
 
- VAS_THRESH_DISABLED
 
- VAS_THRESH_FIFO_GT_EIGHTH_FULL
 
- VAS_THRESH_FIFO_GT_HALF_FULL
 
- VAS_THRESH_FIFO_GT_QTR_FULL
 
- VAS_TX_RSVD_BUF_COUNT_OFFSET
 
- VAS_TX_WCRED
 
- VAS_TX_WCREDS_MAX
 
- VAS_TX_WCRED_ADDER
 
- VAS_TX_WCRED_ADDER_OFFSET
 
- VAS_TX_WCRED_OFFSET
 
- VAS_UWC_SIZE
 
- VAS_WCREDS_DEFAULT
 
- VAS_WINCTL_FAULT_WIN
 
- VAS_WINCTL_NX_WIN
 
- VAS_WINCTL_OFFSET
 
- VAS_WINCTL_OPEN
 
- VAS_WINCTL_PIN
 
- VAS_WINCTL_REJ_NO_CREDIT
 
- VAS_WINCTL_RSVD_TXBUF
 
- VAS_WINCTL_RX_WCRED_MODE
 
- VAS_WINCTL_RX_WORD_MODE
 
- VAS_WINCTL_THRESH_CTL
 
- VAS_WINCTL_TX_WCRED_MODE
 
- VAS_WINCTL_TX_WORD_MODE
 
- VAS_WINDOWS_PER_CHIP
 
- VAS_WIN_BUSY
 
- VAS_WIN_CACHE_STATUS
 
- VAS_WIN_CTX_CACHING_CTL_OFFSET
 
- VAS_WIN_STATUS_OFFSET
 
- VAS_XLATE_CTL_OFFSET
 
- VAS_XLATE_LPCR_ISL
 
- VAS_XLATE_LPCR_OFFSET
 
- VAS_XLATE_LPCR_PAGE_SIZE
 
- VAS_XLATE_LPCR_SC
 
- VAS_XLATE_LPCR_TC
 
- VAS_XLATE_MODE
 
- VAS_XLATE_MSR_DR
 
- VAS_XLATE_MSR_HV
 
- VAS_XLATE_MSR_OFFSET
 
- VAS_XLATE_MSR_PR
 
- VAS_XLATE_MSR_SF
 
- VAS_XLATE_MSR_TA
 
- VAS_XLATE_MSR_US
 
- VAS_XTRA_WRITE
 
- VAUX1
 
- VAUX1_SEL_MASK
 
- VAUX1_SEL_SHIFT
 
- VAUX1_ST_MASK
 
- VAUX1_ST_SHIFT
 
- VAUX2
 
- VAUX2_SEL_MASK
 
- VAUX2_SEL_SHIFT
 
- VAUX2_ST_MASK
 
- VAUX2_ST_SHIFT
 
- VAUX2_table
 
- VAUX3
 
- VAUX33_SEL_MASK
 
- VAUX33_SEL_SHIFT
 
- VAUX33_ST_MASK
 
- VAUX33_ST_SHIFT
 
- VAUX4
 
- VAU_MASK
 
- VAU_SHIFT
 
- VAVSRVIT
 
- VA_A9SM_AND_MPMC_BASE
 
- VA_A9SM_PERIP_BASE
 
- VA_BITS
 
- VA_BITS_MIN
 
- VA_C2
 
- VA_C3
 
- VA_C4
 
- VA_C5
 
- VA_CONTROL_PAGE
 
- VA_CPU_ACCESSIBLE_MEM_ADDR
 
- VA_DDR_SPACE_END
 
- VA_DDR_SPACE_SIZE
 
- VA_DDR_SPACE_START
 
- VA_EXCLUDE_END
 
- VA_EXCLUDE_START
 
- VA_HOST_SPACE_END
 
- VA_HOST_SPACE_SIZE
 
- VA_HOST_SPACE_START
 
- VA_IC_BASE
 
- VA_L2CC_BASE
 
- VA_MEMBER_MASK
 
- VA_MISC_BASE
 
- VA_PERIP_GRP1_BASE
 
- VA_PERIP_GRP2_BASE
 
- VA_SCU_BASE
 
- VA_SPEAR1310_RAS_BASE
 
- VA_SPEAR1310_RAS_GRP1_BASE
 
- VA_SPEAR320_SOC_CONFIG_BASE
 
- VA_SPEAR6XX_ML_CPU_BASE
 
- VA_SPEAR_ICM1_2_BASE
 
- VA_SPEAR_ICM1_UART_BASE
 
- VA_SPEAR_ICM3_MISC_REG_BASE
 
- VA_SPEAR_ICM3_SMI_CTRL_BASE
 
- VA_SPEAR_ICM3_SYS_CTRL_BASE
 
- VA_SPEAR_SYS_CTRL_BASE
 
- VA_SYSRAM0_BASE
 
- VA_UART_BASE
 
- VA_UNTAG_MASK_25
 
- VA_UNTAG_MASK_65
 
- VA_UNTAG_S_25
 
- VA_UNTAG_S_65
 
- VA_VALID_25
 
- VA_VALID_25_R4
 
- VA_VALID_65
 
- VA_VIC
 
- VA_VIC0
 
- VA_VIC1
 
- VA_VIC2
 
- VA_VIC3
 
- VA_VID_HIGH_MASK
 
- VA_VID_HIGH_S
 
- VB
 
- VB2_301
 
- VB2_301B
 
- VB2_301C
 
- VB2_301LV
 
- VB2_302B
 
- VB2_302ELV
 
- VB2_302LV
 
- VB2_307LV
 
- VB2_307T
 
- VB2_30xB
 
- VB2_30xBDH
 
- VB2_30xBLV
 
- VB2_30xC
 
- VB2_30xCLV
 
- VB2_BUF_STATE_ACTIVE
 
- VB2_BUF_STATE_DEQUEUED
 
- VB2_BUF_STATE_DONE
 
- VB2_BUF_STATE_ERROR
 
- VB2_BUF_STATE_IN_REQUEST
 
- VB2_BUF_STATE_PREPARING
 
- VB2_BUF_STATE_QUEUED
 
- VB2_CHRONTEL
 
- VB2_CONEXANT
 
- VB2_DMABUF
 
- VB2_LCD162MHZBRIDGE
 
- VB2_LCDOVER1280BRIDGE
 
- VB2_LCDOVER1600BRIDGE
 
- VB2_LVDS
 
- VB2_MAX_FRAME
 
- VB2_MAX_PLANES
 
- VB2_MEMORY_DMABUF
 
- VB2_MEMORY_MMAP
 
- VB2_MEMORY_UNKNOWN
 
- VB2_MEMORY_USERPTR
 
- VB2_MMAP
 
- VB2_RAMDAC202MHZBRIDGE
 
- VB2_READ
 
- VB2_SISBRIDGE
 
- VB2_SISEMIBRIDGE
 
- VB2_SISHIVISIONBRIDGE
 
- VB2_SISLCDABRIDGE
 
- VB2_SISLVDSBRIDGE
 
- VB2_SISTAP4SCALER
 
- VB2_SISTMDSBRIDGE
 
- VB2_SISTMDSLCDABRIDGE
 
- VB2_SISTVBRIDGE
 
- VB2_SISUMC
 
- VB2_SISVGA2BRIDGE
 
- VB2_SISYPBPRARBRIDGE
 
- VB2_SISYPBPRBRIDGE
 
- VB2_TRUMPION
 
- VB2_USERPTR
 
- VB2_VIDEOBRIDGE
 
- VB2_WRITE
 
- VB310Data_1_2_Offset
 
- VB310Data_4_10_Offset
 
- VB310Data_4_D_Offset
 
- VB310Data_4_E_Offset
 
- VBA
 
- VBAR
 
- VBAR_EL1
 
- VBATSENSE
 
- VBATT_RESISTOR_MAX
 
- VBATT_RESISTOR_MIN
 
- VBAT_LOW_ACT_MASK
 
- VBAT_LOW_VOL_MASK
 
- VBAT_MEAS_AND_IBAT
 
- VBAT_TIMER
 
- VBAT_TRESH_IP_CUR_RED
 
- VBAT_TRUE_MEAS
 
- VBAT_TRUE_MEAS_AND_IBAT
 
- VBB
 
- VBBASE
 
- VBBASE_COLKEY
 
- VBBASE_GLALPHA
 
- VBD_SHOW
 
- VBD_SHOW_ALLRING
 
- VBE
 
- VBE_1_2_INFO_BLOCK_UPDATABLE
 
- VBE_2_0_INFO_BLOCK_UPDATABLE
 
- VBE_CAP_CAN_SWITCH_DAC
 
- VBE_CAP_VGACOMPAT
 
- VBE_DISPI_8BIT_DAC
 
- VBE_DISPI_BANK_ADDRESS
 
- VBE_DISPI_BANK_SIZE_KB
 
- VBE_DISPI_DISABLED
 
- VBE_DISPI_ENABLED
 
- VBE_DISPI_GETCAPS
 
- VBE_DISPI_ID0
 
- VBE_DISPI_ID1
 
- VBE_DISPI_ID2
 
- VBE_DISPI_ID3
 
- VBE_DISPI_ID4
 
- VBE_DISPI_ID5
 
- VBE_DISPI_ID_ANYX
 
- VBE_DISPI_ID_HGSMI
 
- VBE_DISPI_ID_VBOX_VIDEO
 
- VBE_DISPI_INDEX_BANK
 
- VBE_DISPI_INDEX_BPP
 
- VBE_DISPI_INDEX_COUNT
 
- VBE_DISPI_INDEX_ENABLE
 
- VBE_DISPI_INDEX_FB_BASE_HI
 
- VBE_DISPI_INDEX_ID
 
- VBE_DISPI_INDEX_VBOX_VIDEO
 
- VBE_DISPI_INDEX_VIDEO_MEMORY_64K
 
- VBE_DISPI_INDEX_VIRT_HEIGHT
 
- VBE_DISPI_INDEX_VIRT_WIDTH
 
- VBE_DISPI_INDEX_XRES
 
- VBE_DISPI_INDEX_X_OFFSET
 
- VBE_DISPI_INDEX_YRES
 
- VBE_DISPI_INDEX_Y_OFFSET
 
- VBE_DISPI_IOPORT_DAC_DATA
 
- VBE_DISPI_IOPORT_DAC_WRITE_INDEX
 
- VBE_DISPI_IOPORT_DATA
 
- VBE_DISPI_IOPORT_INDEX
 
- VBE_DISPI_LFB_ENABLED
 
- VBE_DISPI_MAX_BPP
 
- VBE_DISPI_MAX_XRES
 
- VBE_DISPI_MAX_YRES
 
- VBE_DISPI_NOCLEARMEM
 
- VBE_FP_INFO
 
- VBE_INFO_BLOCK
 
- VBE_MODE_COLOR
 
- VBE_MODE_GRAPHICS
 
- VBE_MODE_LFB
 
- VBE_MODE_MASK
 
- VBE_MODE_SUPPORTEDHW
 
- VBE_MODE_VGACOMPAT
 
- VBE_VERSION_UNION
 
- VBG_DEBUG_PORT
 
- VBG_IOCTL_CHANGE_FILTER_MASK
 
- VBG_IOCTL_CHANGE_GUEST_CAPABILITIES
 
- VBG_IOCTL_CHECK_BALLOON
 
- VBG_IOCTL_DRIVER_VERSION_INFO
 
- VBG_IOCTL_HDR_TYPE_DEFAULT
 
- VBG_IOCTL_HDR_VERSION
 
- VBG_IOCTL_HGCM_CALL
 
- VBG_IOCTL_HGCM_CALL_32
 
- VBG_IOCTL_HGCM_CALL_64
 
- VBG_IOCTL_HGCM_CALL_PARMS
 
- VBG_IOCTL_HGCM_CALL_PARMS32
 
- VBG_IOCTL_HGCM_CONNECT
 
- VBG_IOCTL_HGCM_DISCONNECT
 
- VBG_IOCTL_INTERRUPT_ALL_WAIT_FOR_EVENTS
 
- VBG_IOCTL_LOG
 
- VBG_IOCTL_VMMDEV_REQUEST
 
- VBG_IOCTL_VMMDEV_REQUEST_BIG
 
- VBG_IOCTL_WAIT_FOR_EVENTS
 
- VBG_IOCTL_WRITE_CORE_DUMP
 
- VBG_IOC_VERSION
 
- VBG_KERNEL_REQUEST
 
- VBG_LOG
 
- VBG_MAX_HGCM_KERNEL_PARM
 
- VBG_MAX_HGCM_USER_PARM
 
- VBG_SVN_REV
 
- VBG_VERSION_BUILD
 
- VBG_VERSION_MAJOR
 
- VBG_VERSION_MINOR
 
- VBG_VERSION_STRING
 
- VBICNTL
 
- VBIDELAY
 
- VBIF_0
 
- VBIF_1
 
- VBIF_AXI_HALT_ACK_TIMEOUT_US
 
- VBIF_AXI_HALT_CTRL0
 
- VBIF_AXI_HALT_CTRL0_HALT_REQ
 
- VBIF_AXI_HALT_CTRL1
 
- VBIF_AXI_HALT_CTRL1_HALT_ACK
 
- VBIF_BASE
 
- VBIF_CLK_FORCE_CTRL0
 
- VBIF_CLK_FORCE_CTRL1
 
- VBIF_DEBUGBUS_BLOCK_SIZE
 
- VBIF_IN_RD_LIM_CONF0
 
- VBIF_IN_RD_LIM_CONF1
 
- VBIF_IN_RD_LIM_CONF2
 
- VBIF_IN_WR_LIM_CONF0
 
- VBIF_IN_WR_LIM_CONF1
 
- VBIF_IN_WR_LIM_CONF2
 
- VBIF_MAX
 
- VBIF_NRT
 
- VBIF_OUT_AXI_AMEMTYPE_CONF0
 
- VBIF_OUT_AXI_AMEMTYPE_CONF1
 
- VBIF_OUT_RD_LIM_CONF0
 
- VBIF_OUT_WR_LIM_CONF0
 
- VBIF_QOS_REMAP_00
 
- VBIF_QOS_REMAP_01
 
- VBIF_QOS_REMAP_10
 
- VBIF_QOS_REMAP_11
 
- VBIF_RESET_ACK_MASK
 
- VBIF_RESET_ACK_TIMEOUT
 
- VBIF_RT
 
- VBIF_VERSION
 
- VBIF_WRITE_GATHER_EN
 
- VBIF_XINL_QOS_LVL_REMAP_000
 
- VBIF_XINL_QOS_RP_REMAP_000
 
- VBIF_XIN_CLR_ERR
 
- VBIF_XIN_HALT_CTRL0
 
- VBIF_XIN_HALT_CTRL1
 
- VBIF_XIN_PND_ERR
 
- VBIF_XIN_SRC_ERR
 
- VBIMIN
 
- VBINT
 
- VBIOSSMC_MSG_EnableTmdp48MHzRefclkPwrDown
 
- VBIOSSMC_MSG_GetFclkFrequency
 
- VBIOSSMC_MSG_GetSmuVersion
 
- VBIOSSMC_MSG_PowerDownGfx
 
- VBIOSSMC_MSG_PowerUpGfx
 
- VBIOSSMC_MSG_SetDispclkFreq
 
- VBIOSSMC_MSG_SetDisplayCount
 
- VBIOSSMC_MSG_SetDppclkFreq
 
- VBIOSSMC_MSG_SetDprefclkFreq
 
- VBIOSSMC_MSG_SetHardMinDcfclkByFreq
 
- VBIOSSMC_MSG_SetMinDeepSleepDcfclk
 
- VBIOSSMC_MSG_SetPhyclkVoltageByFreq
 
- VBIOSSMC_MSG_TestMessage
 
- VBIOSSMC_MSG_UpdatePmeRestore
 
- VBIOSTablePointerStart
 
- VBIOS_CLK_MARK
 
- VBIOS_CMD_TBL_ID__ASIC_INIT
 
- VBIOS_CMD_TBL_ID__BLANK_CRTC
 
- VBIOS_CMD_TBL_ID__COMPUTE_GPU_CLOCK_PARAM
 
- VBIOS_CMD_TBL_ID__DIG1_TRANSMITTER_CONTROL
 
- VBIOS_CMD_TBL_ID__DIGX_ENCODER_CONTROL
 
- VBIOS_CMD_TBL_ID__DYNAMIC_MEMORY_SETTINGS
 
- VBIOS_CMD_TBL_ID__ENABLE_CRTC
 
- VBIOS_CMD_TBL_ID__ENABLE_DISP_POWER_GATING
 
- VBIOS_CMD_TBL_ID__EXTENAL_ENCODER_CONTROL
 
- VBIOS_CMD_TBL_ID__GET_ENGINE_CLOCK
 
- VBIOS_CMD_TBL_ID__GET_MEMORY_CLOCK
 
- VBIOS_CMD_TBL_ID__GET_SMU_CLOCK_INFO
 
- VBIOS_CMD_TBL_ID__GET_VOLTAGE_INF
 
- VBIOS_CMD_TBL_ID__MEMORY_TRAINING
 
- VBIOS_CMD_TBL_ID__PROCESS_AUX_CHANNEL_TRANSACTION
 
- VBIOS_CMD_TBL_ID__PROCESS_I2C_CHANNEL_TRANSACTION
 
- VBIOS_CMD_TBL_ID__SELECT_CRTC_SOURCE
 
- VBIOS_CMD_TBL_ID__SET_CRTC_USING_DTD_TIMING
 
- VBIOS_CMD_TBL_ID__SET_DCE_CLOCK
 
- VBIOS_CMD_TBL_ID__SET_ENGINE_CLOCK
 
- VBIOS_CMD_TBL_ID__SET_MEMORY_CLOCK
 
- VBIOS_CMD_TBL_ID__SET_PIXEL_CLOCK
 
- VBIOS_CMD_TBL_ID__SET_VOLTAGE
 
- VBIOS_CMD_TBL_ID__UNDEFINED
 
- VBIOS_CS_MARK
 
- VBIOS_DATA_TBL_ID__ASIC_PROFILING_INF
 
- VBIOS_DATA_TBL_ID__DCE_INF
 
- VBIOS_DATA_TBL_ID__DISPLAY_OBJECT_INF
 
- VBIOS_DATA_TBL_ID__FIRMWARE_INF
 
- VBIOS_DATA_TBL_ID__GFX_INF
 
- VBIOS_DATA_TBL_ID__GPIO_PIN_LUT
 
- VBIOS_DATA_TBL_ID__INDIRECT_IO_ACCESS
 
- VBIOS_DATA_TBL_ID__INTEGRATED_SYS_INF
 
- VBIOS_DATA_TBL_ID__LCD_INF
 
- VBIOS_DATA_TBL_ID__MULTIMEDIA_INF
 
- VBIOS_DATA_TBL_ID__POWER_PLAY_INF
 
- VBIOS_DATA_TBL_ID__SMU_INF
 
- VBIOS_DATA_TBL_ID__UMC_INF
 
- VBIOS_DATA_TBL_ID__UNDEFINED
 
- VBIOS_DATA_TBL_ID__UTILITY_PIPELINE
 
- VBIOS_DATA_TBL_ID__VOLTAGE_OBJ_INF
 
- VBIOS_DATA_TBL_ID__VRAM_INF
 
- VBIOS_DATA_TBL_ID__VRAM_USAGE_BY_FIRMWARE
 
- VBIOS_DI_MARK
 
- VBIOS_DO_MARK
 
- VBIOS_MAX_AC_TIMING_ENTRIES
 
- VBIOS_MC_REGISTER_ARRAY_SIZE
 
- VBIOS_ROM_HEADER
 
- VBIOS_SMU_MSG_BOX_REG_LIST_RV
 
- VBIOS_SMU_REG_FIELD_LIST
 
- VBI_ACTIVE_SAMPLES
 
- VBI_A_DMA
 
- VBI_A_GPCNT
 
- VBI_A_GPCNT_CTL
 
- VBI_BPL
 
- VBI_B_DMA
 
- VBI_B_GPCNT
 
- VBI_B_GPCNT_CTL
 
- VBI_CUST1_CFG1
 
- VBI_CUST1_CFG2
 
- VBI_CUST1_CFG3
 
- VBI_CUST2_CFG1
 
- VBI_CUST2_CFG2
 
- VBI_CUST2_CFG3
 
- VBI_CUST3_CFG1
 
- VBI_CUST3_CFG2
 
- VBI_CUST3_CFG3
 
- VBI_C_DMA
 
- VBI_C_GPCNT_CTL
 
- VBI_DEFLINES
 
- VBI_FC_CFG
 
- VBI_HBLANK_SAMPLES_50HZ
 
- VBI_HBLANK_SAMPLES_60HZ
 
- VBI_LINE_0
 
- VBI_LINE_COUNT
 
- VBI_LINE_CTRL1
 
- VBI_LINE_CTRL2
 
- VBI_LINE_CTRL3
 
- VBI_LINE_CTRL4
 
- VBI_LINE_CTRL5
 
- VBI_LINE_LENGTH
 
- VBI_LINE_NTSC_COUNT
 
- VBI_LINE_PAL_COUNT
 
- VBI_MISC_CFG1
 
- VBI_MISC_CFG2
 
- VBI_NTSC_LINE_COUNT
 
- VBI_OFFSET
 
- VBI_PAL_LINE_COUNT
 
- VBI_PASS_CTRL
 
- VBI_PAY1
 
- VBI_PAY2
 
- VBI_RESOURCES
 
- VBI_SAMPLES
 
- VBI_SAMPLES_PER_LINE
 
- VBI_SCALE
 
- VBI_START_END
 
- VBI_STRIDE
 
- VBI_TIMER_COUNT
 
- VBI_TIMER_COUNT_MASK
 
- VBI_TIMER_UNIT
 
- VBI_TIMER_UNIT_MASK
 
- VBLANK
 
- VBLANKEND_MASK
 
- VBLANKEND_SHIFT
 
- VBLANKSTART_MASK
 
- VBLANKSTART_SHIFT
 
- VBLANK_A
 
- VBLANK_ACK
 
- VBLANK_B
 
- VBLANK_BIT2_INT
 
- VBLANK_BIT2_INT_AK
 
- VBLANK_C
 
- VBLANK_EVASION_TIME_US
 
- VBLANK_FENCE
 
- VBLANK_INT
 
- VBLANK_INTERRUPT
 
- VBLANK_INTERRUPT_MASK
 
- VBLANK_INTERRUPT_TYPE
 
- VBLANK_INT_MASK
 
- VBLANK_OCCURRED
 
- VBLANK_STAT
 
- VBLANK_STATUS
 
- VBLANK_TIMER_PERIOD
 
- VBLK_CMP3
 
- VBLK_DGR3
 
- VBLK_DGR4
 
- VBLK_DSK3
 
- VBLK_DSK4
 
- VBLK_FLAG_COMP_STRIPE
 
- VBLK_FLAG_DGR3_IDS
 
- VBLK_FLAG_DGR4_IDS
 
- VBLK_FLAG_PART_INDEX
 
- VBLK_FLAG_VOLU_DRIVE
 
- VBLK_FLAG_VOLU_ID1
 
- VBLK_FLAG_VOLU_ID2
 
- VBLK_FLAG_VOLU_SIZE
 
- VBLK_PRT3
 
- VBLK_SIZE_CMP3
 
- VBLK_SIZE_DGR3
 
- VBLK_SIZE_DGR4
 
- VBLK_SIZE_DSK3
 
- VBLK_SIZE_DSK4
 
- VBLK_SIZE_HEAD
 
- VBLK_SIZE_PRT3
 
- VBLK_SIZE_VOL5
 
- VBLK_VOL5
 
- VBModeIDTableAddr
 
- VBModeStructSize
 
- VBOOT_MODE_DEVELOPER
 
- VBOOT_MODE_NORMAL
 
- VBOOT_MODE_RECOVERY
 
- VBOUT
 
- VBOXGUEST_FACILITY_STATUS_ACTIVE
 
- VBOXGUEST_FACILITY_STATUS_FAILED
 
- VBOXGUEST_FACILITY_STATUS_INACTIVE
 
- VBOXGUEST_FACILITY_STATUS_INIT
 
- VBOXGUEST_FACILITY_STATUS_PAUSED
 
- VBOXGUEST_FACILITY_STATUS_PRE_INIT
 
- VBOXGUEST_FACILITY_STATUS_SIZEHACK
 
- VBOXGUEST_FACILITY_STATUS_TERMINATED
 
- VBOXGUEST_FACILITY_STATUS_TERMINATING
 
- VBOXGUEST_FACILITY_STATUS_UNKNOWN
 
- VBOXGUEST_FACILITY_TYPE_ALL
 
- VBOXGUEST_FACILITY_TYPE_AUTO_LOGON
 
- VBOXGUEST_FACILITY_TYPE_GRAPHICS
 
- VBOXGUEST_FACILITY_TYPE_SEAMLESS
 
- VBOXGUEST_FACILITY_TYPE_SIZEHACK
 
- VBOXGUEST_FACILITY_TYPE_UNKNOWN
 
- VBOXGUEST_FACILITY_TYPE_VBOXGUEST_DRIVER
 
- VBOXGUEST_FACILITY_TYPE_VBOX_SERVICE
 
- VBOXGUEST_FACILITY_TYPE_VBOX_TRAY_CLIENT
 
- VBOX_MAX_CURSOR_HEIGHT
 
- VBOX_MAX_CURSOR_WIDTH
 
- VBOX_MAX_SCREENS
 
- VBOX_MOUSE_POINTER_ALPHA
 
- VBOX_MOUSE_POINTER_SHAPE
 
- VBOX_MOUSE_POINTER_VISIBLE
 
- VBOX_VBVA_CONF32_CURSOR_CAPABILITIES
 
- VBOX_VBVA_CONF32_GUEST_CURSOR_REPORTING
 
- VBOX_VBVA_CONF32_HOST_HEAP_SIZE
 
- VBOX_VBVA_CONF32_MAX_RECORD_SIZE
 
- VBOX_VBVA_CONF32_MODE_HINT_REPORTING
 
- VBOX_VBVA_CONF32_MONITOR_COUNT
 
- VBOX_VBVA_CONF32_SCREEN_FLAGS
 
- VBOX_VBVA_CURSOR_CAPABILITY_HARDWARE
 
- VBOX_VBVA_CURSOR_CAPABILITY_RESERVED0
 
- VBOX_VBVA_CURSOR_CAPABILITY_RESERVED2
 
- VBOX_VBVA_CURSOR_CAPABILITY_RESERVED3
 
- VBOX_VBVA_CURSOR_CAPABILITY_RESERVED4
 
- VBOX_VBVA_CURSOR_CAPABILITY_RESERVED5
 
- VBOX_VENDORID
 
- VBOX_VIDEO_DISABLE_ADAPTER_MEMORY
 
- VBOX_VIDEO_INTERPRET_ADAPTER_MEMORY
 
- VBOX_VIDEO_INTERPRET_DISPLAY_MEMORY_BASE
 
- VBOX_VIDEO_MAX_SCREENS
 
- VBPR
 
- VBP_LEN
 
- VBP_OFST
 
- VBR
 
- VBR_BASE
 
- VBR_RATE_TYPE
 
- VBR_SCQSIZE
 
- VBR_SCQ_NUM_ENTRIES
 
- VBSE
 
- VBSTS
 
- VBT_DP_MAX_LINK_RATE_HBR
 
- VBT_DP_MAX_LINK_RATE_HBR2
 
- VBT_DP_MAX_LINK_RATE_HBR3
 
- VBT_DP_MAX_LINK_RATE_LBR
 
- VBUFFER_SIZE
 
- VBUP33_VRTCN
 
- VBUSERR_RETRY_COUNT
 
- VBUSIN_SWITCH_MIC
 
- VBUSIN_SWITCH_OPEN
 
- VBUSIN_SWITCH_VBUSOUT
 
- VBUSIN_SWITCH_VBUSOUT_WITH_USB
 
- VBUSY
 
- VBUS_0_MARK
 
- VBUS_AUTO_IN_CURR_LIM_ENA
 
- VBUS_CHATTERING_MDELAY
 
- VBUS_CHECK
 
- VBUS_CH_NOK
 
- VBUS_CNTL_DPDM_FD_EN
 
- VBUS_CNTL_DPDM_PD_EN
 
- VBUS_CNTL_FIRST_PO_STAT
 
- VBUS_CTRL_1510
 
- VBUS_DEBOUNCE
 
- VBUS_DET
 
- VBUS_DET_DBNC1
 
- VBUS_DET_DBNC100
 
- VBUS_DET_VIN_CR
 
- VBUS_DISCHRG
 
- VBUS_EN_MARK
 
- VBUS_EN_VBUS_EN
 
- VBUS_FALLING_IRQ
 
- VBUS_FALL_INTR
 
- VBUS_FLG
 
- VBUS_FRC_EN
 
- VBUS_HIGH
 
- VBUS_INTEN
 
- VBUS_INTERRUPT
 
- VBUS_INTERRUPT_ENABLE
 
- VBUS_IN_CURR_LIM_RETRY_SET_TIME
 
- VBUS_IN_CURR_LIM_SHIFT
 
- VBUS_IRQ_EN
 
- VBUS_IRQ_FLAGS
 
- VBUS_IRQ_FLG
 
- VBUS_ISPOUT_CUR_LIM_1500MA
 
- VBUS_ISPOUT_CUR_LIM_2000MA
 
- VBUS_ISPOUT_CUR_LIM_900MA
 
- VBUS_ISPOUT_CUR_LIM_BIT_POS
 
- VBUS_ISPOUT_CUR_LIM_MASK
 
- VBUS_ISPOUT_CUR_NO_LIM
 
- VBUS_ISPOUT_VBUS_PATH_DIS
 
- VBUS_ISPOUT_VHOLD_SET_4300MV
 
- VBUS_ISPOUT_VHOLD_SET_BIT_POS
 
- VBUS_ISPOUT_VHOLD_SET_LSB_RES
 
- VBUS_ISPOUT_VHOLD_SET_MASK
 
- VBUS_ISPOUT_VHOLD_SET_OFFSET
 
- VBUS_LEVEL
 
- VBUS_LOW
 
- VBUS_LOW_INT
 
- VBUS_MARK
 
- VBUS_MODE_1510
 
- VBUS_OC_MARK
 
- VBUS_ON
 
- VBUS_OTG_DETECTION_DISABLED
 
- VBUS_OTG_DISCHARGE
 
- VBUS_OVERRIDE
 
- VBUS_OVV_SELECT_5P6V
 
- VBUS_OVV_SELECT_5P7V
 
- VBUS_OVV_SELECT_5P8V
 
- VBUS_OVV_SELECT_5P9V
 
- VBUS_OVV_SELECT_6P0V
 
- VBUS_OVV_SELECT_6P1V
 
- VBUS_OVV_SELECT_6P2V
 
- VBUS_OVV_SELECT_6P3V
 
- VBUS_OVV_SELECT_MASK
 
- VBUS_OVV_TH
 
- VBUS_OV_IRQ
 
- VBUS_PIN
 
- VBUS_POLL_TIMEOUT
 
- VBUS_RISE_INTR
 
- VBUS_RISING_IRQ
 
- VBUS_TO_HPI_ENABLE
 
- VBUS_V
 
- VBUS_VALUE
 
- VBUS_W2FC_1510
 
- VBVACAPS_COMPLETEGCMD_BY_IOREAD
 
- VBVACAPS_DISABLE_CURSOR_INTEGRATION
 
- VBVACAPS_IRQ
 
- VBVACAPS_USE_VBVA_ONLY
 
- VBVACAPS_VIDEO_MODE_HINTS
 
- VBVAHG_DISPLAY_CUSTOM
 
- VBVAHG_EVENT
 
- VBVAMODEHINT_MAGIC
 
- VBVA_ADAPTER_INFORMATION_SIZE
 
- VBVA_CMDVBVA_CTL
 
- VBVA_CMDVBVA_FLUSH
 
- VBVA_CMDVBVA_SUBMIT
 
- VBVA_CURSOR_POSITION
 
- VBVA_ENABLE
 
- VBVA_FLUSH
 
- VBVA_F_ABSOFFSET
 
- VBVA_F_DISABLE
 
- VBVA_F_ENABLE
 
- VBVA_F_EXTENDED
 
- VBVA_F_MODE_ENABLED
 
- VBVA_F_MODE_VRDP
 
- VBVA_F_MODE_VRDP_ORDER_MASK
 
- VBVA_F_MODE_VRDP_RESET
 
- VBVA_F_NONE
 
- VBVA_F_RECORD_PARTIAL
 
- VBVA_F_STATE_PROCESSING
 
- VBVA_INFO_CAPS
 
- VBVA_INFO_HEAP
 
- VBVA_INFO_SCREEN
 
- VBVA_INFO_VIEW
 
- VBVA_MAX_RECORDS
 
- VBVA_MAX_RECORD_SIZE
 
- VBVA_MIN_BUFFER_SIZE
 
- VBVA_MOUSE_POINTER_SHAPE
 
- VBVA_QUERY_CONF32
 
- VBVA_QUERY_MODE_HINTS
 
- VBVA_REPORT_INPUT_MAPPING
 
- VBVA_RING_BUFFER_SIZE
 
- VBVA_RING_BUFFER_THRESHOLD
 
- VBVA_SCANLINE_CFG
 
- VBVA_SCANLINE_INFO
 
- VBVA_SCREEN_F_ACTIVE
 
- VBVA_SCREEN_F_BLANK
 
- VBVA_SCREEN_F_BLANK2
 
- VBVA_SCREEN_F_DISABLED
 
- VBVA_SCREEN_F_NONE
 
- VBVA_SET_CONF32
 
- VB_301
 
- VB_301B
 
- VB_301C
 
- VB_301LV
 
- VB_302B
 
- VB_302ELV
 
- VB_302LV
 
- VB_30xBDH
 
- VB_AGE_TEST_WITH_RETURN
 
- VB_CHRONTEL
 
- VB_CONEXANT
 
- VB_DESC
 
- VB_DISPLAY_MODE
 
- VB_DISPMODE_DUAL
 
- VB_DISPMODE_MIRROR
 
- VB_DISPMODE_SINGLE
 
- VB_DISPTYPE_CRT1
 
- VB_DISPTYPE_CRT2
 
- VB_DISPTYPE_DISP1
 
- VB_DISPTYPE_DISP2
 
- VB_DUALVIEW_MODE
 
- VB_LCDHIndex
 
- VB_LCDTableIndex
 
- VB_LCDVIndex
 
- VB_LO_ACT
 
- VB_LO_SEL_3500MV
 
- VB_LVDS
 
- VB_MIN_BUFFERS
 
- VB_MIN_BUFSIZE
 
- VB_MIRROR_MODE
 
- VB_ModeID
 
- VB_NoLCD
 
- VB_PART1_ADR
 
- VB_PART1_DATA
 
- VB_PART2_ADR
 
- VB_PART2_DATA
 
- VB_PART3_ADR
 
- VB_PART3_DATA
 
- VB_PART4_ADR
 
- VB_PART4_DATA
 
- VB_SINGLE_MODE
 
- VB_SIS301
 
- VB_SIS301B
 
- VB_SIS301C
 
- VB_SIS301LV
 
- VB_SIS302B
 
- VB_SIS302ELV
 
- VB_SIS302LV
 
- VB_SIS307LV
 
- VB_SIS307T
 
- VB_SIS30xB
 
- VB_SIS30xBLV
 
- VB_SIS30xC
 
- VB_SIS30xCLV
 
- VB_SISBRIDGE
 
- VB_SISDUALLINK
 
- VB_SISEMI
 
- VB_SISHIVISION
 
- VB_SISLCDA
 
- VB_SISLVDS
 
- VB_SISPART4OVERFLOW
 
- VB_SISPART4SCALER
 
- VB_SISPOWER
 
- VB_SISPWD
 
- VB_SISRAMDAC202
 
- VB_SISTAP4SCALER
 
- VB_SISTMDS
 
- VB_SISTMDSLCDA
 
- VB_SISVB
 
- VB_SISVGA2
 
- VB_SISYPBPR
 
- VB_TRUMPION
 
- VB_TVTableIndex
 
- VB_UMC
 
- VB_VIDEOBRIDGE
 
- VBlankOff
 
- VBlankOn
 
- VBlankTimeout
 
- VBorder
 
- VC
 
- VC0_8021PF_CTRL_CHANGE_BOTH
 
- VC0_8021PF_CTRL_CHANGE_PRI
 
- VC0_8021PF_CTRL_CHANGE_VID
 
- VC0_8021PF_CTRL_MASK
 
- VC0_8021PF_CTRL_NONE
 
- VC0_8021QF_CTRL_CHANGE_BOTH
 
- VC0_8021QF_CTRL_CHANGE_PRI
 
- VC0_8021QF_CTRL_CHANGE_VID
 
- VC0_8021QF_CTRL_MASK
 
- VC0_DROP_VID_MISS
 
- VC0_RESERVED_1
 
- VC0_VID_CHK_EN
 
- VC0_VID_HASH_VID
 
- VC0_VLAN_EN
 
- VC1_RX_MCST_FWD_EN
 
- VC1_RX_MCST_TAG_EN
 
- VC1_RX_MCST_UNTAG_EN
 
- VC2_CGLYPH_ADDR
 
- VC2_CTRL_ECCURS
 
- VC2_CTRL_ECDISP
 
- VC2_CTRL_ECG64
 
- VC2_CTRL_ECURS
 
- VC2_CTRL_EDIDS
 
- VC2_CTRL_EDISP
 
- VC2_CTRL_EGSYNC
 
- VC2_CTRL_EILACE
 
- VC2_CTRL_EVIDEO
 
- VC2_CTRL_EVIRQ
 
- VC2_CTRL_GLSEL
 
- VC2_IREG_CCURSX
 
- VC2_IREG_CENTRY
 
- VC2_IREG_CONFIG
 
- VC2_IREG_CONTROL
 
- VC2_IREG_CTPTR
 
- VC2_IREG_CURSX
 
- VC2_IREG_CURSY
 
- VC2_IREG_DENTRY
 
- VC2_IREG_DFPTR
 
- VC2_IREG_DLTPTR
 
- VC2_IREG_RADDR
 
- VC2_IREG_SLEN
 
- VC2_IREG_VENTRY
 
- VC2_IREG_VFPTR
 
- VC2_IREG_VLCTR
 
- VC2_IREG_VLIR
 
- VC2_IREG_VLSPTR
 
- VC2_IREG_WCURSY
 
- VC2_PROTOCOL
 
- VC2_REGADDR_INDEX
 
- VC2_REGADDR_IREG
 
- VC2_REGADDR_RAM
 
- VC2_VFRAMET_ADDR
 
- VC2_VLINET_ADDR
 
- VC3_HIGH_8BIT_EN
 
- VC3_MAXSIZE_1532
 
- VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128
 
- VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_256
 
- VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_32
 
- VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_64
 
- VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_MASK
 
- VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_SHIFT
 
- VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_128
 
- VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_256
 
- VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32
 
- VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_64
 
- VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_MASK
 
- VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_SHIFT
 
- VC4_BIN_CONFIG_AUTO_INIT_TSDA
 
- VC4_BIN_CONFIG_DB_NON_MS
 
- VC4_BIN_CONFIG_MS_MODE_4X
 
- VC4_BIN_CONFIG_TILE_BUFFER_64BIT
 
- VC4_BO_TYPE_BCL
 
- VC4_BO_TYPE_BIN
 
- VC4_BO_TYPE_COUNT
 
- VC4_BO_TYPE_DUMB
 
- VC4_BO_TYPE_KERNEL
 
- VC4_BO_TYPE_KERNEL_CACHE
 
- VC4_BO_TYPE_RCL
 
- VC4_BO_TYPE_V3D
 
- VC4_BO_TYPE_V3D_SHADER
 
- VC4_CONFIG_BITS_AA_POINTS_AND_LINES
 
- VC4_CONFIG_BITS_COVERAGE_PIPE_SELECT
 
- VC4_CONFIG_BITS_COVERAGE_READ_LEAVE
 
- VC4_CONFIG_BITS_COVERAGE_UPDATE_NONZERO
 
- VC4_CONFIG_BITS_COVERAGE_UPDATE_ODD
 
- VC4_CONFIG_BITS_COVERAGE_UPDATE_OR
 
- VC4_CONFIG_BITS_COVERAGE_UPDATE_ZERO
 
- VC4_CONFIG_BITS_CW_PRIMITIVES
 
- VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT
 
- VC4_CONFIG_BITS_EARLY_Z
 
- VC4_CONFIG_BITS_EARLY_Z_UPDATE
 
- VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET
 
- VC4_CONFIG_BITS_ENABLE_PRIM_BACK
 
- VC4_CONFIG_BITS_ENABLE_PRIM_FRONT
 
- VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_16X
 
- VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X
 
- VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_NONE
 
- VC4_CONFIG_BITS_Z_UPDATE
 
- VC4_DEFINE_PACKET
 
- VC4_ENCODER_TYPE_DPI
 
- VC4_ENCODER_TYPE_DSI0
 
- VC4_ENCODER_TYPE_DSI1
 
- VC4_ENCODER_TYPE_HDMI
 
- VC4_ENCODER_TYPE_NONE
 
- VC4_ENCODER_TYPE_SMI
 
- VC4_ENCODER_TYPE_VEC
 
- VC4_GET_FIELD
 
- VC4_HDMI_AUDIO_PACKET_AUDIO_LAYOUT
 
- VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_MASK
 
- VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_SHIFT
 
- VC4_HDMI_AUDIO_PACKET_CEA_MASK_MASK
 
- VC4_HDMI_AUDIO_PACKET_CEA_MASK_SHIFT
 
- VC4_HDMI_AUDIO_PACKET_CONFIG
 
- VC4_HDMI_AUDIO_PACKET_FORCE_AUDIO_LAYOUT
 
- VC4_HDMI_AUDIO_PACKET_FORCE_B_FRAME
 
- VC4_HDMI_AUDIO_PACKET_FORCE_SAMPLE_PRESENT
 
- VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS
 
- VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT
 
- VC4_HDMI_CEC_ADDR_MASK
 
- VC4_HDMI_CEC_ADDR_SHIFT
 
- VC4_HDMI_CEC_CLEAR_RECEIVE_OFF
 
- VC4_HDMI_CEC_CLK_PRELOAD_MASK
 
- VC4_HDMI_CEC_CLK_PRELOAD_SHIFT
 
- VC4_HDMI_CEC_CNTRL_1
 
- VC4_HDMI_CEC_CNTRL_2
 
- VC4_HDMI_CEC_CNTRL_3
 
- VC4_HDMI_CEC_CNTRL_4
 
- VC4_HDMI_CEC_CNTRL_5
 
- VC4_HDMI_CEC_CNT_TO_1300_US_MASK
 
- VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT
 
- VC4_HDMI_CEC_CNT_TO_1500_US_MASK
 
- VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT
 
- VC4_HDMI_CEC_CNT_TO_1700_US_MASK
 
- VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT
 
- VC4_HDMI_CEC_CNT_TO_2050_US_MASK
 
- VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT
 
- VC4_HDMI_CEC_CNT_TO_2400_US_MASK
 
- VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT
 
- VC4_HDMI_CEC_CNT_TO_2750_US_MASK
 
- VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT
 
- VC4_HDMI_CEC_CNT_TO_3500_US_MASK
 
- VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT
 
- VC4_HDMI_CEC_CNT_TO_3600_US_MASK
 
- VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT
 
- VC4_HDMI_CEC_CNT_TO_3900_US_MASK
 
- VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT
 
- VC4_HDMI_CEC_CNT_TO_400_US_MASK
 
- VC4_HDMI_CEC_CNT_TO_400_US_SHIFT
 
- VC4_HDMI_CEC_CNT_TO_4300_US_MASK
 
- VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT
 
- VC4_HDMI_CEC_CNT_TO_4500_US_MASK
 
- VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT
 
- VC4_HDMI_CEC_CNT_TO_4700_US_MASK
 
- VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT
 
- VC4_HDMI_CEC_CNT_TO_600_US_MASK
 
- VC4_HDMI_CEC_CNT_TO_600_US_SHIFT
 
- VC4_HDMI_CEC_CNT_TO_800_US_MASK
 
- VC4_HDMI_CEC_CNT_TO_800_US_SHIFT
 
- VC4_HDMI_CEC_DIV_CLK_CNT_MASK
 
- VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT
 
- VC4_HDMI_CEC_MESSAGE_LENGTH_MASK
 
- VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT
 
- VC4_HDMI_CEC_MUX_TP_OUT_CEC
 
- VC4_HDMI_CEC_PAD_SW_RESET
 
- VC4_HDMI_CEC_REC_WRD_CNT_MASK
 
- VC4_HDMI_CEC_REC_WRD_CNT_SHIFT
 
- VC4_HDMI_CEC_RX_CEC_INT
 
- VC4_HDMI_CEC_RX_CONTINUE
 
- VC4_HDMI_CEC_RX_DATA_1
 
- VC4_HDMI_CEC_RX_DATA_2
 
- VC4_HDMI_CEC_RX_DATA_3
 
- VC4_HDMI_CEC_RX_DATA_4
 
- VC4_HDMI_CEC_RX_EOM
 
- VC4_HDMI_CEC_RX_STATUS_GOOD
 
- VC4_HDMI_CEC_RX_SW_RESET
 
- VC4_HDMI_CEC_START_XMIT_BEGIN
 
- VC4_HDMI_CEC_TX_CONTINUE
 
- VC4_HDMI_CEC_TX_DATA_1
 
- VC4_HDMI_CEC_TX_DATA_2
 
- VC4_HDMI_CEC_TX_DATA_3
 
- VC4_HDMI_CEC_TX_DATA_4
 
- VC4_HDMI_CEC_TX_EOM
 
- VC4_HDMI_CEC_TX_STATUS_GOOD
 
- VC4_HDMI_CEC_TX_SW_RESET
 
- VC4_HDMI_CORE_REV
 
- VC4_HDMI_CPU_CEC
 
- VC4_HDMI_CPU_CLEAR
 
- VC4_HDMI_CPU_HOTPLUG
 
- VC4_HDMI_CPU_MASK_CLEAR
 
- VC4_HDMI_CPU_MASK_SET
 
- VC4_HDMI_CPU_MASK_STATUS
 
- VC4_HDMI_CPU_SET
 
- VC4_HDMI_CPU_STATUS
 
- VC4_HDMI_CRP_CFG
 
- VC4_HDMI_CRP_CFG_DISABLE
 
- VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN
 
- VC4_HDMI_CRP_CFG_N_MASK
 
- VC4_HDMI_CRP_CFG_N_SHIFT
 
- VC4_HDMI_CRP_USE_MAI_BUS_SYNC_FOR_CTS
 
- VC4_HDMI_CTS_0
 
- VC4_HDMI_CTS_1
 
- VC4_HDMI_CTS_PERIOD_0
 
- VC4_HDMI_CTS_PERIOD_1
 
- VC4_HDMI_FIFO_CTL
 
- VC4_HDMI_FIFO_CTL_CAPTURE_PTR
 
- VC4_HDMI_FIFO_CTL_FIFO_RESET
 
- VC4_HDMI_FIFO_CTL_INV_CLK_XFR
 
- VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N
 
- VC4_HDMI_FIFO_CTL_ON_VB
 
- VC4_HDMI_FIFO_CTL_RECENTER
 
- VC4_HDMI_FIFO_CTL_RECENTER_DONE
 
- VC4_HDMI_FIFO_CTL_USE_EMPTY
 
- VC4_HDMI_FIFO_CTL_USE_FULL
 
- VC4_HDMI_FIFO_CTL_USE_PLL_LOCK
 
- VC4_HDMI_FIFO_VALID_WRITE_MASK
 
- VC4_HDMI_GCP
 
- VC4_HDMI_HORZA
 
- VC4_HDMI_HORZA_HAP_MASK
 
- VC4_HDMI_HORZA_HAP_SHIFT
 
- VC4_HDMI_HORZA_HPOS
 
- VC4_HDMI_HORZA_VPOS
 
- VC4_HDMI_HORZB
 
- VC4_HDMI_HORZB_HBP_MASK
 
- VC4_HDMI_HORZB_HBP_SHIFT
 
- VC4_HDMI_HORZB_HFP_MASK
 
- VC4_HDMI_HORZB_HFP_SHIFT
 
- VC4_HDMI_HORZB_HSP_MASK
 
- VC4_HDMI_HORZB_HSP_SHIFT
 
- VC4_HDMI_HOTPLUG
 
- VC4_HDMI_HOTPLUG_CONNECTED
 
- VC4_HDMI_HOTPLUG_INT
 
- VC4_HDMI_MAI_CHANNEL_MAP
 
- VC4_HDMI_MAI_CHANNEL_MASK_MASK
 
- VC4_HDMI_MAI_CHANNEL_MASK_SHIFT
 
- VC4_HDMI_MAI_CONFIG
 
- VC4_HDMI_MAI_CONFIG_BIT_REVERSE
 
- VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE
 
- VC4_HDMI_MAI_FORMAT
 
- VC4_HDMI_PACKET_STRIDE
 
- VC4_HDMI_RAM_PACKET
 
- VC4_HDMI_RAM_PACKET_CONFIG
 
- VC4_HDMI_RAM_PACKET_ENABLE
 
- VC4_HDMI_RAM_PACKET_STATUS
 
- VC4_HDMI_SCHEDULER_CONTROL
 
- VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE
 
- VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS
 
- VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT
 
- VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI
 
- VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT
 
- VC4_HDMI_SW_RESET_CONTROL
 
- VC4_HDMI_SW_RESET_FORMAT_DETECT
 
- VC4_HDMI_SW_RESET_HDMI
 
- VC4_HDMI_TX_PHY_CTL0
 
- VC4_HDMI_TX_PHY_RESET_CTL
 
- VC4_HDMI_TX_PHY_RNG_PWRDN
 
- VC4_HDMI_VERTA0
 
- VC4_HDMI_VERTA1
 
- VC4_HDMI_VERTA_VAL_MASK
 
- VC4_HDMI_VERTA_VAL_SHIFT
 
- VC4_HDMI_VERTA_VFP_MASK
 
- VC4_HDMI_VERTA_VFP_SHIFT
 
- VC4_HDMI_VERTA_VSP_MASK
 
- VC4_HDMI_VERTA_VSP_SHIFT
 
- VC4_HDMI_VERTB0
 
- VC4_HDMI_VERTB1
 
- VC4_HDMI_VERTB_VBP_MASK
 
- VC4_HDMI_VERTB_VBP_SHIFT
 
- VC4_HDMI_VERTB_VSPO_MASK
 
- VC4_HDMI_VERTB_VSPO_SHIFT
 
- VC4_HD_CECOVR
 
- VC4_HD_CECRXD
 
- VC4_HD_CSC_12_11
 
- VC4_HD_CSC_14_13
 
- VC4_HD_CSC_22_21
 
- VC4_HD_CSC_24_23
 
- VC4_HD_CSC_32_31
 
- VC4_HD_CSC_34_33
 
- VC4_HD_CSC_CTL
 
- VC4_HD_CSC_CTL_ENABLE
 
- VC4_HD_CSC_CTL_MODE_CUSTOM
 
- VC4_HD_CSC_CTL_MODE_MASK
 
- VC4_HD_CSC_CTL_MODE_RGB_TO_HD_YPRPB
 
- VC4_HD_CSC_CTL_MODE_RGB_TO_SD_YPRPB
 
- VC4_HD_CSC_CTL_MODE_SHIFT
 
- VC4_HD_CSC_CTL_ORDER_BGR
 
- VC4_HD_CSC_CTL_ORDER_BRG
 
- VC4_HD_CSC_CTL_ORDER_GBR
 
- VC4_HD_CSC_CTL_ORDER_GRB
 
- VC4_HD_CSC_CTL_ORDER_MASK
 
- VC4_HD_CSC_CTL_ORDER_RBG
 
- VC4_HD_CSC_CTL_ORDER_RGB
 
- VC4_HD_CSC_CTL_ORDER_SHIFT
 
- VC4_HD_CSC_CTL_PADMSB
 
- VC4_HD_CSC_CTL_RGB2YCC
 
- VC4_HD_FRAME_COUNT
 
- VC4_HD_MAI_CTL
 
- VC4_HD_MAI_CTL_BUSY
 
- VC4_HD_MAI_CTL_CHALIGN
 
- VC4_HD_MAI_CTL_CHNUM_MASK
 
- VC4_HD_MAI_CTL_CHNUM_SHIFT
 
- VC4_HD_MAI_CTL_DLATE
 
- VC4_HD_MAI_CTL_EMPTY
 
- VC4_HD_MAI_CTL_ENABLE
 
- VC4_HD_MAI_CTL_ERRORE
 
- VC4_HD_MAI_CTL_ERRORF
 
- VC4_HD_MAI_CTL_FLUSH
 
- VC4_HD_MAI_CTL_FULL
 
- VC4_HD_MAI_CTL_PAREN
 
- VC4_HD_MAI_CTL_RESET
 
- VC4_HD_MAI_CTL_WHOLSMP
 
- VC4_HD_MAI_DATA
 
- VC4_HD_MAI_FMT
 
- VC4_HD_MAI_SMP
 
- VC4_HD_MAI_SMP_M_MASK
 
- VC4_HD_MAI_SMP_M_SHIFT
 
- VC4_HD_MAI_SMP_N_MASK
 
- VC4_HD_MAI_SMP_N_SHIFT
 
- VC4_HD_MAI_THR
 
- VC4_HD_MAI_THR_DREQHIGH_MASK
 
- VC4_HD_MAI_THR_DREQHIGH_SHIFT
 
- VC4_HD_MAI_THR_DREQLOW_MASK
 
- VC4_HD_MAI_THR_DREQLOW_SHIFT
 
- VC4_HD_MAI_THR_PANICHIGH_MASK
 
- VC4_HD_MAI_THR_PANICHIGH_SHIFT
 
- VC4_HD_MAI_THR_PANICLOW_MASK
 
- VC4_HD_MAI_THR_PANICLOW_SHIFT
 
- VC4_HD_M_CTL
 
- VC4_HD_M_ENABLE
 
- VC4_HD_M_RAM_STANDBY
 
- VC4_HD_M_REGISTER_FILE_STANDBY
 
- VC4_HD_M_SW_RST
 
- VC4_HD_VID_CTL
 
- VC4_HD_VID_CTL_ENABLE
 
- VC4_HD_VID_CTL_FRAME_COUNTER_RESET
 
- VC4_HD_VID_CTL_HSYNC_LOW
 
- VC4_HD_VID_CTL_UNDERFLOW_ENABLE
 
- VC4_HD_VID_CTL_VSYNC_LOW
 
- VC4_INDEX_BUFFER_U16
 
- VC4_INDEX_BUFFER_U8
 
- VC4_ING_VID_CHECK_MASK
 
- VC4_ING_VID_CHECK_S
 
- VC4_ING_VID_VIO_DROP
 
- VC4_ING_VID_VIO_FWD
 
- VC4_ING_VID_VIO_TO_IMP
 
- VC4_INT_TO_COEFF
 
- VC4_KERNEL_DWORDS
 
- VC4_LINEAR_PHASE_KERNEL
 
- VC4_LINEAR_PHASE_KERNEL_DWORDS
 
- VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL
 
- VC4_LOADSTORE_FULL_RES_DISABLE_COLOR
 
- VC4_LOADSTORE_FULL_RES_DISABLE_ZS
 
- VC4_LOADSTORE_FULL_RES_EOF
 
- VC4_LOADSTORE_TILE_BUFFER_BGR565
 
- VC4_LOADSTORE_TILE_BUFFER_BGR565_DITHER
 
- VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK
 
- VC4_LOADSTORE_TILE_BUFFER_BUFFER_SHIFT
 
- VC4_LOADSTORE_TILE_BUFFER_COLOR
 
- VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_COLOR
 
- VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_VG_MASK
 
- VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_ZS
 
- VC4_LOADSTORE_TILE_BUFFER_EOF
 
- VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK
 
- VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT
 
- VC4_LOADSTORE_TILE_BUFFER_FULL
 
- VC4_LOADSTORE_TILE_BUFFER_NONE
 
- VC4_LOADSTORE_TILE_BUFFER_RGBA8888
 
- VC4_LOADSTORE_TILE_BUFFER_TILING_MASK
 
- VC4_LOADSTORE_TILE_BUFFER_TILING_SHIFT
 
- VC4_LOADSTORE_TILE_BUFFER_VG_MASK
 
- VC4_LOADSTORE_TILE_BUFFER_Z
 
- VC4_LOADSTORE_TILE_BUFFER_ZS
 
- VC4_MADV_DONTNEED
 
- VC4_MADV_WILLNEED
 
- VC4_MASK
 
- VC4_MAX_SAMPLES
 
- VC4_NO_ING_VID_CHK
 
- VC4_PACKET_BRANCH
 
- VC4_PACKET_BRANCH_SIZE
 
- VC4_PACKET_BRANCH_TO_SUB_LIST
 
- VC4_PACKET_BRANCH_TO_SUB_LIST_SIZE
 
- VC4_PACKET_CLEAR_COLORS
 
- VC4_PACKET_CLEAR_COLORS_SIZE
 
- VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE
 
- VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE_SIZE
 
- VC4_PACKET_CLIPPER_XY_SCALING
 
- VC4_PACKET_CLIPPER_XY_SCALING_SIZE
 
- VC4_PACKET_CLIPPER_Z_SCALING
 
- VC4_PACKET_CLIPPER_Z_SCALING_SIZE
 
- VC4_PACKET_CLIP_WINDOW
 
- VC4_PACKET_CLIP_WINDOW_SIZE
 
- VC4_PACKET_COMPRESSED_PRIMITIVE
 
- VC4_PACKET_COMPRESSED_PRIMITIVE_SIZE
 
- VC4_PACKET_CONFIGURATION_BITS
 
- VC4_PACKET_CONFIGURATION_BITS_SIZE
 
- VC4_PACKET_DEPTH_OFFSET
 
- VC4_PACKET_DEPTH_OFFSET_SIZE
 
- VC4_PACKET_FLAT_SHADE_FLAGS
 
- VC4_PACKET_FLAT_SHADE_FLAGS_SIZE
 
- VC4_PACKET_FLUSH
 
- VC4_PACKET_FLUSH_ALL
 
- VC4_PACKET_FLUSH_ALL_SIZE
 
- VC4_PACKET_FLUSH_SIZE
 
- VC4_PACKET_GEM_HANDLES
 
- VC4_PACKET_GEM_HANDLES_SIZE
 
- VC4_PACKET_GL_ARRAY_PRIMITIVE
 
- VC4_PACKET_GL_ARRAY_PRIMITIVE_SIZE
 
- VC4_PACKET_GL_INDEXED_PRIMITIVE
 
- VC4_PACKET_GL_INDEXED_PRIMITIVE_SIZE
 
- VC4_PACKET_GL_SHADER_STATE
 
- VC4_PACKET_GL_SHADER_STATE_SIZE
 
- VC4_PACKET_H
 
- VC4_PACKET_HALT
 
- VC4_PACKET_HALT_SIZE
 
- VC4_PACKET_INCREMENT_SEMAPHORE
 
- VC4_PACKET_INCREMENT_SEMAPHORE_SIZE
 
- VC4_PACKET_LINE_WIDTH
 
- VC4_PACKET_LINE_WIDTH_SIZE
 
- VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER
 
- VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE
 
- VC4_PACKET_LOAD_TILE_BUFFER_GENERAL
 
- VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE
 
- VC4_PACKET_NOP
 
- VC4_PACKET_NOP_SIZE
 
- VC4_PACKET_NV_SHADER_STATE
 
- VC4_PACKET_NV_SHADER_STATE_SIZE
 
- VC4_PACKET_POINT_SIZE
 
- VC4_PACKET_POINT_SIZE_SIZE
 
- VC4_PACKET_PRIMITIVE_LIST_FORMAT
 
- VC4_PACKET_PRIMITIVE_LIST_FORMAT_SIZE
 
- VC4_PACKET_RHT_X_BOUNDARY
 
- VC4_PACKET_RHT_X_BOUNDARY_SIZE
 
- VC4_PACKET_START_TILE_BINNING
 
- VC4_PACKET_START_TILE_BINNING_SIZE
 
- VC4_PACKET_STORE_FULL_RES_TILE_BUFFER
 
- VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE
 
- VC4_PACKET_STORE_MS_TILE_BUFFER
 
- VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF
 
- VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF_SIZE
 
- VC4_PACKET_STORE_MS_TILE_BUFFER_SIZE
 
- VC4_PACKET_STORE_TILE_BUFFER_GENERAL
 
- VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE
 
- VC4_PACKET_TILE_BINNING_MODE_CONFIG
 
- VC4_PACKET_TILE_BINNING_MODE_CONFIG_SIZE
 
- VC4_PACKET_TILE_COORDINATES
 
- VC4_PACKET_TILE_COORDINATES_SIZE
 
- VC4_PACKET_TILE_RENDERING_MODE_CONFIG
 
- VC4_PACKET_TILE_RENDERING_MODE_CONFIG_SIZE
 
- VC4_PACKET_VG_SHADER_STATE
 
- VC4_PACKET_VG_SHADER_STATE_SIZE
 
- VC4_PACKET_VIEWPORT_OFFSET
 
- VC4_PACKET_VIEWPORT_OFFSET_SIZE
 
- VC4_PACKET_WAIT_ON_SEMAPHORE
 
- VC4_PACKET_WAIT_ON_SEMAPHORE_SIZE
 
- VC4_PACKET_Z_CLIPPING
 
- VC4_PACKET_Z_CLIPPING_SIZE
 
- VC4_PERFCNT_FEP_CLIPPED_QUADS
 
- VC4_PERFCNT_FEP_VALID_PRIMS_NO_RENDER
 
- VC4_PERFCNT_FEP_VALID_PRIMS_RENDER
 
- VC4_PERFCNT_FEP_VALID_QUADS
 
- VC4_PERFCNT_L2C_TOTAL_L2_CACHE_HIT
 
- VC4_PERFCNT_L2C_TOTAL_L2_CACHE_MISS
 
- VC4_PERFCNT_NUM_EVENTS
 
- VC4_PERFCNT_PLB_PRIMS_NEED_CLIPPING
 
- VC4_PERFCNT_PLB_PRIMS_OUTSIDE_VIEWPORT
 
- VC4_PERFCNT_PSE_PRIMS_REVERSED
 
- VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_EXEC_VALID_INST
 
- VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_FRAGMENT_SHADING
 
- VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_VERTEX_COORD_SHADING
 
- VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_SCOREBOARD
 
- VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_TMUS
 
- VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_VARYINGS
 
- VC4_PERFCNT_QPU_TOTAL_IDLE_CYCLES
 
- VC4_PERFCNT_QPU_TOTAL_INST_CACHE_HIT
 
- VC4_PERFCNT_QPU_TOTAL_INST_CACHE_MISS
 
- VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_HIT
 
- VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_MISS
 
- VC4_PERFCNT_TLB_QUADS_NON_ZERO_COVERAGE
 
- VC4_PERFCNT_TLB_QUADS_NOT_PASSING_STENCIL
 
- VC4_PERFCNT_TLB_QUADS_NOT_PASSING_Z_AND_STENCIL
 
- VC4_PERFCNT_TLB_QUADS_PASSING_Z_AND_STENCIL
 
- VC4_PERFCNT_TLB_QUADS_WRITTEN_TO_COLOR_BUF
 
- VC4_PERFCNT_TLB_QUADS_ZERO_COVERAGE
 
- VC4_PERFCNT_TMU_TOTAL_TEXT_CACHE_MISS
 
- VC4_PERFCNT_TMU_TOTAL_TEXT_QUADS_PROCESSED
 
- VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VCD_STALLED
 
- VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VDW_STALLED
 
- VC4_PERFMONID_MAX
 
- VC4_PERFMONID_MIN
 
- VC4_PPF_FILTER_WORD
 
- VC4_PRIMITIVE_LIST_FORMAT_16_INDEX
 
- VC4_PRIMITIVE_LIST_FORMAT_32_XY
 
- VC4_PRIMITIVE_LIST_FORMAT_TYPE_LINES
 
- VC4_PRIMITIVE_LIST_FORMAT_TYPE_POINTS
 
- VC4_PRIMITIVE_LIST_FORMAT_TYPE_RHT
 
- VC4_PRIMITIVE_LIST_FORMAT_TYPE_TRIANGLES
 
- VC4_QPU_DEFINES_H
 
- VC4_REG32
 
- VC4_REGS_H
 
- VC4_RENDER_CONFIG_COVERAGE_MODE
 
- VC4_RENDER_CONFIG_DB_NON_MS
 
- VC4_RENDER_CONFIG_DECIMATE_MODE_16X
 
- VC4_RENDER_CONFIG_DECIMATE_MODE_1X
 
- VC4_RENDER_CONFIG_DECIMATE_MODE_4X
 
- VC4_RENDER_CONFIG_EARLY_Z_COVERAGE_DISABLE
 
- VC4_RENDER_CONFIG_EARLY_Z_DIRECTION_G
 
- VC4_RENDER_CONFIG_ENABLE_VG_MASK
 
- VC4_RENDER_CONFIG_FORMAT_BGR565
 
- VC4_RENDER_CONFIG_FORMAT_BGR565_DITHERED
 
- VC4_RENDER_CONFIG_FORMAT_MASK
 
- VC4_RENDER_CONFIG_FORMAT_RGBA8888
 
- VC4_RENDER_CONFIG_FORMAT_SHIFT
 
- VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK
 
- VC4_RENDER_CONFIG_MEMORY_FORMAT_SHIFT
 
- VC4_RENDER_CONFIG_MS_MODE_4X
 
- VC4_RENDER_CONFIG_TILE_BUFFER_64BIT
 
- VC4_SCALING_NONE
 
- VC4_SCALING_PPF
 
- VC4_SCALING_TPZ
 
- VC4_SET_FIELD
 
- VC4_SHADER_FLAG_ENABLE_CLIPPING
 
- VC4_SHADER_FLAG_FS_SINGLE_THREAD
 
- VC4_SHADER_FLAG_SHADED_CLIP_COORDS
 
- VC4_SHADER_FLAG_VS_POINT_SIZE
 
- VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR
 
- VC4_STORE_TILE_BUFFER_DISABLE_SWAP
 
- VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR
 
- VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR
 
- VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X16
 
- VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X4
 
- VC4_STORE_TILE_BUFFER_MODE_MASK
 
- VC4_STORE_TILE_BUFFER_MODE_SAMPLE0
 
- VC4_STORE_TILE_BUFFER_MODE_SHIFT
 
- VC4_SUBMIT_CL_FIXED_RCL_ORDER
 
- VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X
 
- VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y
 
- VC4_SUBMIT_CL_USE_CLEAR_COLOR
 
- VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES
 
- VC4_TEXTURE_TYPE_A1
 
- VC4_TEXTURE_TYPE_A4
 
- VC4_TEXTURE_TYPE_ALPHA
 
- VC4_TEXTURE_TYPE_BW1
 
- VC4_TEXTURE_TYPE_ETC1
 
- VC4_TEXTURE_TYPE_LUMALPHA
 
- VC4_TEXTURE_TYPE_LUMINANCE
 
- VC4_TEXTURE_TYPE_RGB565
 
- VC4_TEXTURE_TYPE_RGBA32R
 
- VC4_TEXTURE_TYPE_RGBA4444
 
- VC4_TEXTURE_TYPE_RGBA5551
 
- VC4_TEXTURE_TYPE_RGBA64
 
- VC4_TEXTURE_TYPE_RGBA8888
 
- VC4_TEXTURE_TYPE_RGBX8888
 
- VC4_TEXTURE_TYPE_S16
 
- VC4_TEXTURE_TYPE_S16F
 
- VC4_TEXTURE_TYPE_S8
 
- VC4_TEXTURE_TYPE_YUV422R
 
- VC4_TEX_P0_CMMODE_MASK
 
- VC4_TEX_P0_CMMODE_SHIFT
 
- VC4_TEX_P0_CSWIZ_MASK
 
- VC4_TEX_P0_CSWIZ_SHIFT
 
- VC4_TEX_P0_FLIPY_MASK
 
- VC4_TEX_P0_FLIPY_SHIFT
 
- VC4_TEX_P0_MIPLVLS_MASK
 
- VC4_TEX_P0_MIPLVLS_SHIFT
 
- VC4_TEX_P0_OFFSET_MASK
 
- VC4_TEX_P0_OFFSET_SHIFT
 
- VC4_TEX_P0_TYPE_MASK
 
- VC4_TEX_P0_TYPE_SHIFT
 
- VC4_TEX_P1_ETCFLIP_MASK
 
- VC4_TEX_P1_ETCFLIP_SHIFT
 
- VC4_TEX_P1_HEIGHT_MASK
 
- VC4_TEX_P1_HEIGHT_SHIFT
 
- VC4_TEX_P1_MAGFILT_LINEAR
 
- VC4_TEX_P1_MAGFILT_MASK
 
- VC4_TEX_P1_MAGFILT_NEAREST
 
- VC4_TEX_P1_MAGFILT_SHIFT
 
- VC4_TEX_P1_MINFILT_LINEAR
 
- VC4_TEX_P1_MINFILT_LIN_MIP_LIN
 
- VC4_TEX_P1_MINFILT_LIN_MIP_NEAR
 
- VC4_TEX_P1_MINFILT_MASK
 
- VC4_TEX_P1_MINFILT_NEAREST
 
- VC4_TEX_P1_MINFILT_NEAR_MIP_LIN
 
- VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR
 
- VC4_TEX_P1_MINFILT_SHIFT
 
- VC4_TEX_P1_TYPE4_MASK
 
- VC4_TEX_P1_TYPE4_SHIFT
 
- VC4_TEX_P1_WIDTH_MASK
 
- VC4_TEX_P1_WIDTH_SHIFT
 
- VC4_TEX_P1_WRAP_BORDER
 
- VC4_TEX_P1_WRAP_CLAMP
 
- VC4_TEX_P1_WRAP_MIRROR
 
- VC4_TEX_P1_WRAP_REPEAT
 
- VC4_TEX_P1_WRAP_S_MASK
 
- VC4_TEX_P1_WRAP_S_SHIFT
 
- VC4_TEX_P1_WRAP_T_MASK
 
- VC4_TEX_P1_WRAP_T_SHIFT
 
- VC4_TEX_P2_BSLOD_MASK
 
- VC4_TEX_P2_BSLOD_SHIFT
 
- VC4_TEX_P2_CHEIGHT_MASK
 
- VC4_TEX_P2_CHEIGHT_SHIFT
 
- VC4_TEX_P2_CMST_MASK
 
- VC4_TEX_P2_CMST_SHIFT
 
- VC4_TEX_P2_CWIDTH_MASK
 
- VC4_TEX_P2_CWIDTH_SHIFT
 
- VC4_TEX_P2_CXOFF_MASK
 
- VC4_TEX_P2_CXOFF_SHIFT
 
- VC4_TEX_P2_CYOFF_MASK
 
- VC4_TEX_P2_CYOFF_SHIFT
 
- VC4_TEX_P2_PTYPE_CHILD_IMAGE_DIMENSIONS
 
- VC4_TEX_P2_PTYPE_CHILD_IMAGE_OFFSETS
 
- VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE
 
- VC4_TEX_P2_PTYPE_IGNORED
 
- VC4_TEX_P2_PTYPE_MASK
 
- VC4_TEX_P2_PTYPE_SHIFT
 
- VC4_TILE_BUFFER_SIZE
 
- VC4_TILING_FORMAT_LINEAR
 
- VC4_TILING_FORMAT_LT
 
- VC4_TILING_FORMAT_T
 
- VC4_VEC_TV_MODE_NTSC
 
- VC4_VEC_TV_MODE_NTSC_J
 
- VC4_VEC_TV_MODE_PAL
 
- VC4_VEC_TV_MODE_PAL_M
 
- VC5_CLK_OE_SHDN
 
- VC5_CLK_OS_SHDN
 
- VC5_CLK_OUTPUT_CFG
 
- VC5_CLK_OUTPUT_CFG1_EN_CLKBUF
 
- VC5_DROP_VTABLE_MISS
 
- VC5_FEEDBACK_FRAC_DIV
 
- VC5_FEEDBACK_INT_DIV
 
- VC5_FEEDBACK_INT_DIV_BITS
 
- VC5_GLOBAL_REGISTER
 
- VC5_GLOBAL_REGISTER_GLOBAL_RESET
 
- VC5_HAS_INTERNAL_XTAL
 
- VC5_HAS_PFD_FREQ_DBL
 
- VC5_MAX_CLK_OUT_NUM
 
- VC5_MAX_FOD_NUM
 
- VC5_MUX_IN_CLKIN
 
- VC5_MUX_IN_XIN
 
- VC5_OTP_CONTROL
 
- VC5_OUT_DIV_CONTROL
 
- VC5_OUT_DIV_CONTROL_EN_FOD
 
- VC5_OUT_DIV_CONTROL_INT_MODE
 
- VC5_OUT_DIV_CONTROL_RESET
 
- VC5_OUT_DIV_CONTROL_SELB_NORM
 
- VC5_OUT_DIV_CONTROL_SEL_EXT
 
- VC5_OUT_DIV_FRAC
 
- VC5_OUT_DIV_FRAC4_OD_SCEE
 
- VC5_OUT_DIV_INT
 
- VC5_OUT_DIV_SKEW_FRAC
 
- VC5_OUT_DIV_SKEW_INT
 
- VC5_OUT_DIV_SPREAD_MOD
 
- VC5_OUT_DIV_STEP_SPREAD
 
- VC5_PLL_VCO_MAX
 
- VC5_PLL_VCO_MIN
 
- VC5_PRIM_SRC_SHDN
 
- VC5_PRIM_SRC_SHDN_EN_CLKIN
 
- VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ
 
- VC5_PRIM_SRC_SHDN_EN_GBL_SHDN
 
- VC5_PRIM_SRC_SHDN_EN_XTAL
 
- VC5_PRIM_SRC_SHDN_SP
 
- VC5_RC_CONTROL0
 
- VC5_RC_CONTROL1
 
- VC5_REF_DIVIDER
 
- VC5_REF_DIVIDER_REF_DIV
 
- VC5_REF_DIVIDER_SEL_PREDIV2
 
- VC5_RSVD_ADC_GAIN_15_8
 
- VC5_RSVD_ADC_GAIN_7_0
 
- VC5_RSVD_ADC_OFFSET_15_8
 
- VC5_RSVD_ADC_OFFSET_7_0
 
- VC5_RSVD_BANDGAP_TRIM_DN
 
- VC5_RSVD_BANDGAP_TRIM_UP
 
- VC5_RSVD_CLK_AMP_123
 
- VC5_RSVD_CLK_R_12_CLK_AMP_4
 
- VC5_RSVD_CLK_R_34_CLK_AMP_4
 
- VC5_RSVD_DEVICE_ID
 
- VC5_RSVD_GAIN
 
- VC5_RSVD_OFFSET_TBIN
 
- VC5_RSVD_TEMPY
 
- VC5_RSVD_TEST_NP
 
- VC5_RSVD_UNUSED
 
- VC5_VCO_BAND
 
- VC5_VCO_CTRL_AND_PREDIV
 
- VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV
 
- VC5_VID_FFF_EN
 
- VC5_XTAL_X1_LOAD_CAP
 
- VC5_XTAL_X2_LOAD_CAP
 
- VCAM_SIZE
 
- VCAP_ACT_SET
 
- VCAP_AHB_CLK
 
- VCAP_AHB_RESET
 
- VCAP_AXI_CLK
 
- VCAP_AXI_RESET
 
- VCAP_CLK
 
- VCAP_CMD_INITIALIZE
 
- VCAP_CMD_MOVE_DOWN
 
- VCAP_CMD_MOVE_UP
 
- VCAP_CMD_READ
 
- VCAP_CMD_WRITE
 
- VCAP_COUNTER_WIDTH
 
- VCAP_ENTRY_WIDTH
 
- VCAP_IS2_ACTION_WIDTH
 
- VCAP_IS2_CNT
 
- VCAP_IS2_ENTRY_WIDTH
 
- VCAP_KEY_ANY_SET
 
- VCAP_KEY_BIT_SET
 
- VCAP_KEY_BYTES_SET
 
- VCAP_KEY_SET
 
- VCAP_NPL_CLK
 
- VCAP_NPL_RESET
 
- VCAP_PORT_CNT
 
- VCAP_PORT_WIDTH
 
- VCAP_RESET
 
- VCAP_SEL_ACTION
 
- VCAP_SEL_ALL
 
- VCAP_SEL_COUNTER
 
- VCAP_SEL_ENTRY
 
- VCAP_SRC
 
- VCAP_TG_FULL
 
- VCAP_TG_HALF
 
- VCAP_TG_NONE
 
- VCAP_TG_QUARTER
 
- VCC2FLOW
 
- VCCA
 
- VCCAP
 
- VCCINP
 
- VCCTABLE_GETFREEPAGE
 
- VCC_0V
 
- VCC_3V
 
- VCC_3VORXV_CAPABLE
 
- VCC_3V_CAPABLE
 
- VCC_3V_EN
 
- VCC_5V
 
- VCC_5V_EN
 
- VCC_5V_ONLY
 
- VCC_BUFF_LEN
 
- VCC_CNT_0V
 
- VCC_CNT_3V
 
- VCC_CNT_5V
 
- VCC_CNT_MASK
 
- VCC_CTL_BREAK
 
- VCC_CTL_HUP
 
- VCC_DBG_DRV
 
- VCC_DBG_LDC
 
- VCC_DBG_PKT
 
- VCC_HTABLE_SIZE
 
- VCC_MASK
 
- VCC_MAX_PORTS
 
- VCC_MINOR_START
 
- VCC_REF_DELAY
 
- VCC_STATUS_3V
 
- VCC_STATUS_5V
 
- VCC_STATUS_XV
 
- VCC_TTY_FLAGS
 
- VCC_XV
 
- VCC_XV_ONLY
 
- VCDL_CTRL0
 
- VCDL_CTRL2
 
- VCDL_DAC2
 
- VCDT2_REG
 
- VCDT_REG
 
- VCDT_SEL_DT
 
- VCDT_SEL_DTN_ON
 
- VCDT_SEL_VC
 
- VCDT_VCDTN_EN
 
- VCEClockInfo
 
- VCEClockInfoArray
 
- VCEPLL_BYPASS_EN_MASK
 
- VCEPLL_CTLACK2_MASK
 
- VCEPLL_CTLACK_MASK
 
- VCEPLL_CTLREQ_MASK
 
- VCEPLL_FB_DIV
 
- VCEPLL_FB_DIV_MASK
 
- VCEPLL_PDIV_A
 
- VCEPLL_PDIV_A_MASK
 
- VCEPLL_PDIV_B
 
- VCEPLL_PDIV_B_MASK
 
- VCEPLL_REF_DIV_MASK
 
- VCEPLL_RESET_MASK
 
- VCEPLL_SLEEP_MASK
 
- VCEPLL_SSEN_MASK
 
- VCEPLL_VCO_MODE_MASK
 
- VCE_1_0_D_H
 
- VCE_1_0_SH_MASK_H
 
- VCE_2_0_D_H
 
- VCE_2_0_SH_MASK_H
 
- VCE_3_0_D_H
 
- VCE_3_0_SH_MASK_H
 
- VCE_4_0__CTXID__VCE_TRAP_GENERAL_PURPOSE
 
- VCE_4_0__CTXID__VCE_TRAP_LOW_LATENCY
 
- VCE_4_0__CTXID__VCE_TRAP_REAL_TIME
 
- VCE_ACLK
 
- VCE_BASE__INST0_SEG0
 
- VCE_BASE__INST0_SEG1
 
- VCE_BASE__INST0_SEG2
 
- VCE_BASE__INST0_SEG3
 
- VCE_BASE__INST0_SEG4
 
- VCE_BASE__INST0_SEG5
 
- VCE_BASE__INST1_SEG0
 
- VCE_BASE__INST1_SEG1
 
- VCE_BASE__INST1_SEG2
 
- VCE_BASE__INST1_SEG3
 
- VCE_BASE__INST1_SEG4
 
- VCE_BASE__INST1_SEG5
 
- VCE_BASE__INST2_SEG0
 
- VCE_BASE__INST2_SEG1
 
- VCE_BASE__INST2_SEG2
 
- VCE_BASE__INST2_SEG3
 
- VCE_BASE__INST2_SEG4
 
- VCE_BASE__INST2_SEG5
 
- VCE_BASE__INST3_SEG0
 
- VCE_BASE__INST3_SEG1
 
- VCE_BASE__INST3_SEG2
 
- VCE_BASE__INST3_SEG3
 
- VCE_BASE__INST3_SEG4
 
- VCE_BASE__INST3_SEG5
 
- VCE_BASE__INST4_SEG0
 
- VCE_BASE__INST4_SEG1
 
- VCE_BASE__INST4_SEG2
 
- VCE_BASE__INST4_SEG3
 
- VCE_BASE__INST4_SEG4
 
- VCE_BASE__INST4_SEG5
 
- VCE_BASE__INST5_SEG0
 
- VCE_BASE__INST5_SEG1
 
- VCE_BASE__INST5_SEG2
 
- VCE_BASE__INST5_SEG3
 
- VCE_BASE__INST5_SEG4
 
- VCE_BASE__INST5_SEG5
 
- VCE_CGTT_CLK_OVERRIDE
 
- VCE_CLK_EN
 
- VCE_CLOCK_GATING_A
 
- VCE_CLOCK_GATING_A__CGC_CLK_OFF_DELAY_MASK
 
- VCE_CLOCK_GATING_A__CGC_CLK_OFF_DELAY__SHIFT
 
- VCE_CLOCK_GATING_A__CGC_CLK_ON_DELAY_MASK
 
- VCE_CLOCK_GATING_A__CGC_CLK_ON_DELAY__SHIFT
 
- VCE_CLOCK_GATING_A__CGC_REG_AWAKE_MASK
 
- VCE_CLOCK_GATING_A__CGC_REG_AWAKE__SHIFT
 
- VCE_CLOCK_GATING_B
 
- VCE_CLOCK_GATING_B__CGC_CTLREG_CLK_FORCE_ON_MASK
 
- VCE_CLOCK_GATING_B__CGC_CTLREG_CLK_FORCE_ON__SHIFT
 
- VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_OFF_MASK
 
- VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_OFF__SHIFT
 
- VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_ON_MASK
 
- VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_ON__SHIFT
 
- VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_OFF_MASK
 
- VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_OFF__SHIFT
 
- VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_ON_MASK
 
- VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_ON__SHIFT
 
- VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_OFF_MASK
 
- VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_OFF__SHIFT
 
- VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_ON_MASK
 
- VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_ON__SHIFT
 
- VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_OFF_MASK
 
- VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_OFF__SHIFT
 
- VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_ON_MASK
 
- VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_ON__SHIFT
 
- VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_OFF_MASK
 
- VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_OFF__SHIFT
 
- VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_ON_MASK
 
- VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_ON__SHIFT
 
- VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_OFF_MASK
 
- VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_OFF__SHIFT
 
- VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_ON_MASK
 
- VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_ON__SHIFT
 
- VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_OFF_MASK
 
- VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_OFF__SHIFT
 
- VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_ON_MASK
 
- VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_ON__SHIFT
 
- VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_OFF_MASK
 
- VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_OFF__SHIFT
 
- VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_ON_MASK
 
- VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_ON__SHIFT
 
- VCE_CLOCK_GATING_B__CGC_VREG_CLK_FORCE_ON_MASK
 
- VCE_CLOCK_GATING_B__CGC_VREG_CLK_FORCE_ON__SHIFT
 
- VCE_CMD_END
 
- VCE_CMD_FENCE
 
- VCE_CMD_FLUSH_TLB
 
- VCE_CMD_IB
 
- VCE_CMD_IB_AUTO
 
- VCE_CMD_IB_VM
 
- VCE_CMD_NO_OP
 
- VCE_CMD_REG_WAIT
 
- VCE_CMD_REG_WRITE
 
- VCE_CMD_SEMAPHORE
 
- VCE_CMD_TRAP
 
- VCE_CMD_UPDATE_PTB
 
- VCE_CMD_WAIT_GE
 
- VCE_COMMAND_DISABLE_VPS
 
- VCE_COMMAND_DISABLE_VPS_LOGO
 
- VCE_COMMAND_DISABLE_VPS_LOGO_ALL
 
- VCE_COMMAND_DISABLE_VPS_REINIT
 
- VCE_COMMAND_ENABLE_VPS
 
- VCE_CONFIG__VCE_RDREQ_URG_MASK
 
- VCE_CONFIG__VCE_RDREQ_URG__SHIFT
 
- VCE_CONFIG__VCE_REQ_TRAN_MASK
 
- VCE_CONFIG__VCE_REQ_TRAN__SHIFT
 
- VCE_DPM_MASK
 
- VCE_ECPU_SOFT_RESET
 
- VCE_FME_SOFT_RESET
 
- VCE_FW_REG_STATUS
 
- VCE_FW_REG_STATUS_BUSY
 
- VCE_FW_REG_STATUS_DONE
 
- VCE_FW_REG_STATUS_PASS
 
- VCE_HARVEST_FUSE_MACRO__MASK
 
- VCE_HARVEST_FUSE_MACRO__SHIFT
 
- VCE_HWID
 
- VCE_HWIP
 
- VCE_HW_VERSION__VCE_CONFIGURATION_MASK
 
- VCE_HW_VERSION__VCE_CONFIGURATION__SHIFT
 
- VCE_HW_VERSION__VCE_INSTANCE_ID_MASK
 
- VCE_HW_VERSION__VCE_INSTANCE_ID__SHIFT
 
- VCE_HW_VERSION__VCE_VERSION_MASK
 
- VCE_HW_VERSION__VCE_VERSION__SHIFT
 
- VCE_IDLE_TIMEOUT
 
- VCE_IDLE_TIMEOUT_MS
 
- VCE_LMI_CACHE_CTRL
 
- VCE_LMI_CACHE_CTRL__VCPU_EN_MASK
 
- VCE_LMI_CACHE_CTRL__VCPU_EN__SHIFT
 
- VCE_LMI_CACHE_CTRL__VCPU_FLUSH_MASK
 
- VCE_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT
 
- VCE_LMI_CTRL
 
- VCE_LMI_CTRL2
 
- VCE_LMI_CTRL2__ASSERT_UMC_URGENT_MASK
 
- VCE_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT
 
- VCE_LMI_CTRL2__MASK_UMC_URGENT_MASK
 
- VCE_LMI_CTRL2__MASK_UMC_URGENT__SHIFT
 
- VCE_LMI_CTRL2__STALL_ARB_MASK
 
- VCE_LMI_CTRL2__STALL_ARB_UMC_MASK
 
- VCE_LMI_CTRL2__STALL_ARB_UMC__SHIFT
 
- VCE_LMI_CTRL2__STALL_ARB__SHIFT
 
- VCE_LMI_CTRL__ASSERT_MC_URGENT_MASK
 
- VCE_LMI_CTRL__ASSERT_MC_URGENT__SHIFT
 
- VCE_LMI_CTRL__DATA_COHERENCY_EN_MASK
 
- VCE_LMI_CTRL__DATA_COHERENCY_EN__SHIFT
 
- VCE_LMI_CTRL__MASK_MC_URGENT_MASK
 
- VCE_LMI_CTRL__MASK_MC_URGENT__SHIFT
 
- VCE_LMI_CTRL__MIF_DATA_COHERENCY_EN_MASK
 
- VCE_LMI_CTRL__MIF_DATA_COHERENCY_EN__SHIFT
 
- VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK
 
- VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT
 
- VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_EN_MASK
 
- VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_EN__SHIFT
 
- VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_RESET_MASK
 
- VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_RESET__SHIFT
 
- VCE_LMI_FW_PERIODIC_CTRL
 
- VCE_LMI_FW_START_KEYSEL
 
- VCE_LMI_SWAP_CNTL
 
- VCE_LMI_SWAP_CNTL1
 
- VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP_MASK
 
- VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT
 
- VCE_LMI_SWAP_CNTL1__RD_MC_CID_TRAN_MASK
 
- VCE_LMI_SWAP_CNTL1__RD_MC_CID_TRAN__SHIFT
 
- VCE_LMI_SWAP_CNTL1__RD_MC_CID_URG_MASK
 
- VCE_LMI_SWAP_CNTL1__RD_MC_CID_URG__SHIFT
 
- VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK
 
- VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP__SHIFT
 
- VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP_MASK
 
- VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP__SHIFT
 
- VCE_LMI_SWAP_CNTL2__WR_MC_CID_TRAN_MASK
 
- VCE_LMI_SWAP_CNTL2__WR_MC_CID_TRAN__SHIFT
 
- VCE_LMI_SWAP_CNTL2__WR_MC_CID_URG_MASK
 
- VCE_LMI_SWAP_CNTL2__WR_MC_CID_URG__SHIFT
 
- VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP_MASK
 
- VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP__SHIFT
 
- VCE_LMI_SWAP_CNTL3__RD_MC_CID_TRAN_MASK
 
- VCE_LMI_SWAP_CNTL3__RD_MC_CID_TRAN__SHIFT
 
- VCE_LMI_SWAP_CNTL3__RD_MC_CID_URG_MASK
 
- VCE_LMI_SWAP_CNTL3__RD_MC_CID_URG__SHIFT
 
- VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK
 
- VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT
 
- VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP_MASK
 
- VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP__SHIFT
 
- VCE_LMI_SWAP_CNTL__WR_MC_CID_TRAN_MASK
 
- VCE_LMI_SWAP_CNTL__WR_MC_CID_TRAN__SHIFT
 
- VCE_LMI_SWAP_CNTL__WR_MC_CID_URG_MASK
 
- VCE_LMI_SWAP_CNTL__WR_MC_CID_URG__SHIFT
 
- VCE_LMI_VCPU_CACHE_40BIT_BAR
 
- VCE_LMI_VCPU_CACHE_40BIT_BAR0__BAR_MASK
 
- VCE_LMI_VCPU_CACHE_40BIT_BAR0__BAR__SHIFT
 
- VCE_LMI_VCPU_CACHE_40BIT_BAR1__BAR_MASK
 
- VCE_LMI_VCPU_CACHE_40BIT_BAR1__BAR__SHIFT
 
- VCE_LMI_VCPU_CACHE_40BIT_BAR2__BAR_MASK
 
- VCE_LMI_VCPU_CACHE_40BIT_BAR2__BAR__SHIFT
 
- VCE_LMI_VCPU_CACHE_40BIT_BAR3__BAR_MASK
 
- VCE_LMI_VCPU_CACHE_40BIT_BAR3__BAR__SHIFT
 
- VCE_LMI_VCPU_CACHE_40BIT_BAR4__BAR_MASK
 
- VCE_LMI_VCPU_CACHE_40BIT_BAR4__BAR__SHIFT
 
- VCE_LMI_VCPU_CACHE_40BIT_BAR5__BAR_MASK
 
- VCE_LMI_VCPU_CACHE_40BIT_BAR5__BAR__SHIFT
 
- VCE_LMI_VCPU_CACHE_40BIT_BAR6__BAR_MASK
 
- VCE_LMI_VCPU_CACHE_40BIT_BAR6__BAR__SHIFT
 
- VCE_LMI_VCPU_CACHE_40BIT_BAR7__BAR_MASK
 
- VCE_LMI_VCPU_CACHE_40BIT_BAR7__BAR__SHIFT
 
- VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR_MASK
 
- VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR__SHIFT
 
- VCE_LMI_VCPU_CACHE_64BIT_BAR0__BAR_MASK
 
- VCE_LMI_VCPU_CACHE_64BIT_BAR0__BAR__SHIFT
 
- VCE_LMI_VCPU_CACHE_64BIT_BAR1__BAR_MASK
 
- VCE_LMI_VCPU_CACHE_64BIT_BAR1__BAR__SHIFT
 
- VCE_LMI_VCPU_CACHE_64BIT_BAR2__BAR_MASK
 
- VCE_LMI_VCPU_CACHE_64BIT_BAR2__BAR__SHIFT
 
- VCE_LMI_VCPU_CACHE_64BIT_BAR3__BAR_MASK
 
- VCE_LMI_VCPU_CACHE_64BIT_BAR3__BAR__SHIFT
 
- VCE_LMI_VCPU_CACHE_64BIT_BAR4__BAR_MASK
 
- VCE_LMI_VCPU_CACHE_64BIT_BAR4__BAR__SHIFT
 
- VCE_LMI_VCPU_CACHE_64BIT_BAR5__BAR_MASK
 
- VCE_LMI_VCPU_CACHE_64BIT_BAR5__BAR__SHIFT
 
- VCE_LMI_VCPU_CACHE_64BIT_BAR6__BAR_MASK
 
- VCE_LMI_VCPU_CACHE_64BIT_BAR6__BAR__SHIFT
 
- VCE_LMI_VCPU_CACHE_64BIT_BAR7__BAR_MASK
 
- VCE_LMI_VCPU_CACHE_64BIT_BAR7__BAR__SHIFT
 
- VCE_LMI_VM_CTRL
 
- VCE_MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK
 
- VCE_MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT
 
- VCE_MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK
 
- VCE_MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT
 
- VCE_MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK
 
- VCE_MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT
 
- VCE_MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI_MASK
 
- VCE_MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI__SHIFT
 
- VCE_MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO_MASK
 
- VCE_MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO__SHIFT
 
- VCE_MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE_MASK
 
- VCE_MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE__SHIFT
 
- VCE_MMSCH_VF_MAILBOX_HOST__DATA_MASK
 
- VCE_MMSCH_VF_MAILBOX_HOST__DATA__SHIFT
 
- VCE_MMSCH_VF_MAILBOX_RESP__RESP_MASK
 
- VCE_MMSCH_VF_MAILBOX_RESP__RESP__SHIFT
 
- VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK
 
- VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT
 
- VCE_MMSCH_VF_VMID__VF_GPCOM_VMID_MASK
 
- VCE_MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT
 
- VCE_RB_ARB_CTRL__RB_ARB_CTRL_MASK
 
- VCE_RB_ARB_CTRL__RB_ARB_CTRL__SHIFT
 
- VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE_MASK
 
- VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE__SHIFT
 
- VCE_RB_BASE_HI
 
- VCE_RB_BASE_HI2
 
- VCE_RB_BASE_HI2__RB_BASE_HI_MASK
 
- VCE_RB_BASE_HI2__RB_BASE_HI__SHIFT
 
- VCE_RB_BASE_HI3__RB_BASE_HI_MASK
 
- VCE_RB_BASE_HI3__RB_BASE_HI__SHIFT
 
- VCE_RB_BASE_HI__RB_BASE_HI_MASK
 
- VCE_RB_BASE_HI__RB_BASE_HI__SHIFT
 
- VCE_RB_BASE_LO
 
- VCE_RB_BASE_LO2
 
- VCE_RB_BASE_LO2__RB_BASE_LO_MASK
 
- VCE_RB_BASE_LO2__RB_BASE_LO__SHIFT
 
- VCE_RB_BASE_LO3__RB_BASE_LO_MASK
 
- VCE_RB_BASE_LO3__RB_BASE_LO__SHIFT
 
- VCE_RB_BASE_LO__RB_BASE_LO_MASK
 
- VCE_RB_BASE_LO__RB_BASE_LO__SHIFT
 
- VCE_RB_RPTR
 
- VCE_RB_RPTR2
 
- VCE_RB_RPTR2__RB_RPTR_MASK
 
- VCE_RB_RPTR2__RB_RPTR__SHIFT
 
- VCE_RB_RPTR3__RB_RPTR_MASK
 
- VCE_RB_RPTR3__RB_RPTR__SHIFT
 
- VCE_RB_RPTR__RB_RPTR_MASK
 
- VCE_RB_RPTR__RB_RPTR__SHIFT
 
- VCE_RB_SIZE
 
- VCE_RB_SIZE2
 
- VCE_RB_SIZE2__RB_SIZE_MASK
 
- VCE_RB_SIZE2__RB_SIZE__SHIFT
 
- VCE_RB_SIZE3__RB_SIZE_MASK
 
- VCE_RB_SIZE3__RB_SIZE__SHIFT
 
- VCE_RB_SIZE__RB_SIZE_MASK
 
- VCE_RB_SIZE__RB_SIZE__SHIFT
 
- VCE_RB_WPTR
 
- VCE_RB_WPTR2
 
- VCE_RB_WPTR2__RB_WPTR_MASK
 
- VCE_RB_WPTR2__RB_WPTR__SHIFT
 
- VCE_RB_WPTR3__RB_WPTR_MASK
 
- VCE_RB_WPTR3__RB_WPTR__SHIFT
 
- VCE_RB_WPTR__RB_WPTR_MASK
 
- VCE_RB_WPTR__RB_WPTR__SHIFT
 
- VCE_SOFT_RESET
 
- VCE_SOFT_RESET__ACAP_SOFT_RESET_MASK
 
- VCE_SOFT_RESET__ACAP_SOFT_RESET__SHIFT
 
- VCE_SOFT_RESET__AVMUX_SOFT_RESET_MASK
 
- VCE_SOFT_RESET__AVMUX_SOFT_RESET__SHIFT
 
- VCE_SOFT_RESET__CTL_SOFT_RESET_MASK
 
- VCE_SOFT_RESET__CTL_SOFT_RESET__SHIFT
 
- VCE_SOFT_RESET__DBF_SOFT_RESET_MASK
 
- VCE_SOFT_RESET__DBF_SOFT_RESET__SHIFT
 
- VCE_SOFT_RESET__DCAP_FSM_SOFT_RESET_MASK
 
- VCE_SOFT_RESET__DCAP_FSM_SOFT_RESET__SHIFT
 
- VCE_SOFT_RESET__DCAP_SOFT_RESET_MASK
 
- VCE_SOFT_RESET__DCAP_SOFT_RESET__SHIFT
 
- VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK
 
- VCE_SOFT_RESET__ECPU_SOFT_RESET__SHIFT
 
- VCE_SOFT_RESET__ENT_SOFT_RESET_MASK
 
- VCE_SOFT_RESET__ENT_SOFT_RESET__SHIFT
 
- VCE_SOFT_RESET__FME_SOFT_RESET_MASK
 
- VCE_SOFT_RESET__FME_SOFT_RESET__SHIFT
 
- VCE_SOFT_RESET__IH_SOFT_RESET_MASK
 
- VCE_SOFT_RESET__IH_SOFT_RESET__SHIFT
 
- VCE_SOFT_RESET__IME_SOFT_RESET_MASK
 
- VCE_SOFT_RESET__IME_SOFT_RESET__SHIFT
 
- VCE_SOFT_RESET__LCM_SOFT_RESET_MASK
 
- VCE_SOFT_RESET__LCM_SOFT_RESET__SHIFT
 
- VCE_SOFT_RESET__LMI_SOFT_RESET_MASK
 
- VCE_SOFT_RESET__LMI_SOFT_RESET__SHIFT
 
- VCE_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK
 
- VCE_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT
 
- VCE_SOFT_RESET__MIF_SOFT_RESET_MASK
 
- VCE_SOFT_RESET__MIF_SOFT_RESET__SHIFT
 
- VCE_SOFT_RESET__SEM_SOFT_RESET_MASK
 
- VCE_SOFT_RESET__SEM_SOFT_RESET__SHIFT
 
- VCE_SOFT_RESET__TAP_SOFT_RESET_MASK
 
- VCE_SOFT_RESET__TAP_SOFT_RESET__SHIFT
 
- VCE_SOFT_RESET__TBE_SOFT_RESET_MASK
 
- VCE_SOFT_RESET__TBE_SOFT_RESET__SHIFT
 
- VCE_SOFT_RESET__UENC_SOFT_RESET_MASK
 
- VCE_SOFT_RESET__UENC_SOFT_RESET__SHIFT
 
- VCE_SOFT_RESET__VEP_SOFT_RESET_MASK
 
- VCE_SOFT_RESET__VEP_SOFT_RESET__SHIFT
 
- VCE_SOFT_RESET__VREG_SOFT_RESET_MASK
 
- VCE_SOFT_RESET__VREG_SOFT_RESET__SHIFT
 
- VCE_STATUS
 
- VCE_STATUS_VCPU_REPORT_AUTO_BUSY_MASK
 
- VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK
 
- VCE_STATUS_VCPU_REPORT_RB0_BUSY_MASK
 
- VCE_STATUS_VCPU_REPORT_RB1_BUSY_MASK
 
- VCE_STATUS__JOB_BUSY_MASK
 
- VCE_STATUS__JOB_BUSY__SHIFT
 
- VCE_STATUS__UENC_BUSY_MASK
 
- VCE_STATUS__UENC_BUSY__SHIFT
 
- VCE_STATUS__VCE_CONFIGURATION_MASK
 
- VCE_STATUS__VCE_CONFIGURATION__SHIFT
 
- VCE_STATUS__VCE_INSTANCE_ID_MASK
 
- VCE_STATUS__VCE_INSTANCE_ID__SHIFT
 
- VCE_STATUS__VCPU_REPORT_MASK
 
- VCE_STATUS__VCPU_REPORT__SHIFT
 
- VCE_SYS_INT_ACK__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_ACK_MASK
 
- VCE_SYS_INT_ACK__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_ACK__SHIFT
 
- VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK_MASK
 
- VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK__SHIFT
 
- VCE_SYS_INT_EN
 
- VCE_SYS_INT_EN__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_EN_MASK
 
- VCE_SYS_INT_EN__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_EN__SHIFT
 
- VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK
 
- VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN__SHIFT
 
- VCE_SYS_INT_STATUS__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_INT_MASK
 
- VCE_SYS_INT_STATUS__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_INT__SHIFT
 
- VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK
 
- VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT__SHIFT
 
- VCE_SYS_INT_TRAP_INTERRUPT_EN
 
- VCE_UENC_CLOCK_GATING
 
- VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_OFF_MASK
 
- VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_OFF__SHIFT
 
- VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_ON_MASK
 
- VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_ON__SHIFT
 
- VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_OFF_MASK
 
- VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_OFF__SHIFT
 
- VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_ON_MASK
 
- VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_ON__SHIFT
 
- VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_OFF_MASK
 
- VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_OFF__SHIFT
 
- VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_ON_MASK
 
- VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_ON__SHIFT
 
- VCE_UENC_CLOCK_GATING__CLOCK_OFF_DELAY_MASK
 
- VCE_UENC_CLOCK_GATING__CLOCK_OFF_DELAY__SHIFT
 
- VCE_UENC_CLOCK_GATING__CLOCK_ON_DELAY_MASK
 
- VCE_UENC_CLOCK_GATING__CLOCK_ON_DELAY__SHIFT
 
- VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_OFF_MASK
 
- VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_OFF__SHIFT
 
- VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_ON_MASK
 
- VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_ON__SHIFT
 
- VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_OFF_MASK
 
- VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_OFF__SHIFT
 
- VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_ON_MASK
 
- VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_ON__SHIFT
 
- VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_OFF_MASK
 
- VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_OFF__SHIFT
 
- VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_ON_MASK
 
- VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_ON__SHIFT
 
- VCE_UENC_CLOCK_GATING__FMECLK_FORCE_OFF_MASK
 
- VCE_UENC_CLOCK_GATING__FMECLK_FORCE_OFF__SHIFT
 
- VCE_UENC_CLOCK_GATING__FMECLK_FORCE_ON_MASK
 
- VCE_UENC_CLOCK_GATING__FMECLK_FORCE_ON__SHIFT
 
- VCE_UENC_CLOCK_GATING__IMECLK_FORCE_OFF_MASK
 
- VCE_UENC_CLOCK_GATING__IMECLK_FORCE_OFF__SHIFT
 
- VCE_UENC_CLOCK_GATING__IMECLK_FORCE_ON_MASK
 
- VCE_UENC_CLOCK_GATING__IMECLK_FORCE_ON__SHIFT
 
- VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_OFF_MASK
 
- VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_OFF__SHIFT
 
- VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_ON_MASK
 
- VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_ON__SHIFT
 
- VCE_UENC_CLOCK_GATING__TBECLK_FORCE_OFF_MASK
 
- VCE_UENC_CLOCK_GATING__TBECLK_FORCE_OFF__SHIFT
 
- VCE_UENC_CLOCK_GATING__TBECLK_FORCE_ON_MASK
 
- VCE_UENC_CLOCK_GATING__TBECLK_FORCE_ON__SHIFT
 
- VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_OFF_MASK
 
- VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_OFF__SHIFT
 
- VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_ON_MASK
 
- VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_ON__SHIFT
 
- VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON_MASK
 
- VCE_UENC_DMA_DCLK_CTRL__RDDMCLK_FORCEON__SHIFT
 
- VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON_MASK
 
- VCE_UENC_DMA_DCLK_CTRL__REGCLK_FORCEON__SHIFT
 
- VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON_MASK
 
- VCE_UENC_DMA_DCLK_CTRL__WRDMCLK_FORCEON__SHIFT
 
- VCE_UENC_REG_CLOCK_GATING
 
- VCE_UENC_REG_CLOCK_GATING__AVMREGCLK_FORCE_ON_MASK
 
- VCE_UENC_REG_CLOCK_GATING__AVMREGCLK_FORCE_ON__SHIFT
 
- VCE_UENC_REG_CLOCK_GATING__DBFREGCLK_FORCE_ON_MASK
 
- VCE_UENC_REG_CLOCK_GATING__DBFREGCLK_FORCE_ON__SHIFT
 
- VCE_UENC_REG_CLOCK_GATING__DCAPREGCLK_FORCE_ON_MASK
 
- VCE_UENC_REG_CLOCK_GATING__DCAPREGCLK_FORCE_ON__SHIFT
 
- VCE_UENC_REG_CLOCK_GATING__ENTREGCLK_FORCE_ON_MASK
 
- VCE_UENC_REG_CLOCK_GATING__ENTREGCLK_FORCE_ON__SHIFT
 
- VCE_UENC_REG_CLOCK_GATING__FMEREGCLK_FORCE_ON_MASK
 
- VCE_UENC_REG_CLOCK_GATING__FMEREGCLK_FORCE_ON__SHIFT
 
- VCE_UENC_REG_CLOCK_GATING__IMEREGCLK_FORCE_ON_MASK
 
- VCE_UENC_REG_CLOCK_GATING__IMEREGCLK_FORCE_ON__SHIFT
 
- VCE_UENC_REG_CLOCK_GATING__LCMREGCLK_FORCE_ON_MASK
 
- VCE_UENC_REG_CLOCK_GATING__LCMREGCLK_FORCE_ON__SHIFT
 
- VCE_UENC_REG_CLOCK_GATING__MIFREGCLK_FORCE_ON_MASK
 
- VCE_UENC_REG_CLOCK_GATING__MIFREGCLK_FORCE_ON__SHIFT
 
- VCE_UENC_REG_CLOCK_GATING__RESERVED_MASK
 
- VCE_UENC_REG_CLOCK_GATING__RESERVED__SHIFT
 
- VCE_UENC_REG_CLOCK_GATING__TBEREGCLK_FORCE_ON_MASK
 
- VCE_UENC_REG_CLOCK_GATING__TBEREGCLK_FORCE_ON__SHIFT
 
- VCE_UENC_REG_CLOCK_GATING__VEPREGCLK_FORCE_ON_MASK
 
- VCE_UENC_REG_CLOCK_GATING__VEPREGCLK_FORCE_ON__SHIFT
 
- VCE_V1_0_DATA_SIZE
 
- VCE_V1_0_FW_SIZE
 
- VCE_V1_0_STACK_SIZE
 
- VCE_V2_0_DATA_SIZE
 
- VCE_V2_0_FW_SIZE
 
- VCE_V2_0_STACK_SIZE
 
- VCE_V3_0_DATA_SIZE
 
- VCE_V3_0_FW_SIZE
 
- VCE_V3_0_STACK_SIZE
 
- VCE_V4_0_DATA_SIZE
 
- VCE_V4_0_FW_SIZE
 
- VCE_V4_0_STACK_SIZE
 
- VCE_VCPU_CACHE_OFFSET0
 
- VCE_VCPU_CACHE_OFFSET0__OFFSET_MASK
 
- VCE_VCPU_CACHE_OFFSET0__OFFSET__SHIFT
 
- VCE_VCPU_CACHE_OFFSET1
 
- VCE_VCPU_CACHE_OFFSET1__OFFSET_MASK
 
- VCE_VCPU_CACHE_OFFSET1__OFFSET__SHIFT
 
- VCE_VCPU_CACHE_OFFSET2
 
- VCE_VCPU_CACHE_OFFSET2__OFFSET_MASK
 
- VCE_VCPU_CACHE_OFFSET2__OFFSET__SHIFT
 
- VCE_VCPU_CACHE_OFFSET3__OFFSET_MASK
 
- VCE_VCPU_CACHE_OFFSET3__OFFSET__SHIFT
 
- VCE_VCPU_CACHE_OFFSET4__OFFSET_MASK
 
- VCE_VCPU_CACHE_OFFSET4__OFFSET__SHIFT
 
- VCE_VCPU_CACHE_OFFSET5__OFFSET_MASK
 
- VCE_VCPU_CACHE_OFFSET5__OFFSET__SHIFT
 
- VCE_VCPU_CACHE_OFFSET6__OFFSET_MASK
 
- VCE_VCPU_CACHE_OFFSET6__OFFSET__SHIFT
 
- VCE_VCPU_CACHE_OFFSET7__OFFSET_MASK
 
- VCE_VCPU_CACHE_OFFSET7__OFFSET__SHIFT
 
- VCE_VCPU_CACHE_OFFSET8__OFFSET_MASK
 
- VCE_VCPU_CACHE_OFFSET8__OFFSET__SHIFT
 
- VCE_VCPU_CACHE_SIZE0
 
- VCE_VCPU_CACHE_SIZE0__SIZE_MASK
 
- VCE_VCPU_CACHE_SIZE0__SIZE__SHIFT
 
- VCE_VCPU_CACHE_SIZE1
 
- VCE_VCPU_CACHE_SIZE1__SIZE_MASK
 
- VCE_VCPU_CACHE_SIZE1__SIZE__SHIFT
 
- VCE_VCPU_CACHE_SIZE2
 
- VCE_VCPU_CACHE_SIZE2__SIZE_MASK
 
- VCE_VCPU_CACHE_SIZE2__SIZE__SHIFT
 
- VCE_VCPU_CACHE_SIZE3__SIZE_MASK
 
- VCE_VCPU_CACHE_SIZE3__SIZE__SHIFT
 
- VCE_VCPU_CACHE_SIZE4__SIZE_MASK
 
- VCE_VCPU_CACHE_SIZE4__SIZE__SHIFT
 
- VCE_VCPU_CACHE_SIZE5__SIZE_MASK
 
- VCE_VCPU_CACHE_SIZE5__SIZE__SHIFT
 
- VCE_VCPU_CACHE_SIZE6__SIZE_MASK
 
- VCE_VCPU_CACHE_SIZE6__SIZE__SHIFT
 
- VCE_VCPU_CACHE_SIZE7__SIZE_MASK
 
- VCE_VCPU_CACHE_SIZE7__SIZE__SHIFT
 
- VCE_VCPU_CACHE_SIZE8__SIZE_MASK
 
- VCE_VCPU_CACHE_SIZE8__SIZE__SHIFT
 
- VCE_VCPU_CNTL
 
- VCE_VCPU_CNTL__CLK_EN_MASK
 
- VCE_VCPU_CNTL__CLK_EN__SHIFT
 
- VCE_VCPU_CNTL__ED_ENABLE_MASK
 
- VCE_VCPU_CNTL__ED_ENABLE__SHIFT
 
- VCE_VCPU_CNTL__ONE_CACHE_SURFACE_EN_MASK
 
- VCE_VCPU_CNTL__ONE_CACHE_SURFACE_EN__SHIFT
 
- VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK
 
- VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT
 
- VCE_VCPU_SCRATCH7
 
- VCE_WM
 
- VCE_WM_MASK
 
- VCE_WM_SHIFT
 
- VCF_IDLE
 
- VCF_RSV
 
- VCF_RX
 
- VCF_TX
 
- VCH2CLK_AUXCLK
 
- VCH2CLK_MASK
 
- VCH2CLK_SYSCLK8
 
- VCH3CLK_AUXCLK
 
- VCH3CLK_MASK
 
- VCH3CLK_SYSCLK8
 
- VCHANNEL_A
 
- VCHANNEL_ANY
 
- VCHANNEL_B
 
- VCHG_NORMAL_CHECK
 
- VCHG_NORMAL_HIGH
 
- VCHG_NORMAL_LOW
 
- VCHG_OVP_LOW
 
- VCHIQ_ARM_H
 
- VCHIQ_BULK_ACTUAL_ABORTED
 
- VCHIQ_BULK_DIR_T
 
- VCHIQ_BULK_MODE_BLOCKING
 
- VCHIQ_BULK_MODE_CALLBACK
 
- VCHIQ_BULK_MODE_NOCALLBACK
 
- VCHIQ_BULK_MODE_T
 
- VCHIQ_BULK_MODE_WAITING
 
- VCHIQ_BULK_RECEIVE
 
- VCHIQ_BULK_RECEIVE_ABORTED
 
- VCHIQ_BULK_RECEIVE_DONE
 
- VCHIQ_BULK_TRANSMIT
 
- VCHIQ_BULK_TRANSMIT_ABORTED
 
- VCHIQ_BULK_TRANSMIT_DONE
 
- VCHIQ_CFG_H
 
- VCHIQ_CHANNEL_SIZE
 
- VCHIQ_CONNECTED_H
 
- VCHIQ_CONNSTATE_CONNECTED
 
- VCHIQ_CONNSTATE_CONNECTING
 
- VCHIQ_CONNSTATE_DISCONNECTED
 
- VCHIQ_CONNSTATE_PAUSED
 
- VCHIQ_CONNSTATE_PAUSE_SENT
 
- VCHIQ_CONNSTATE_PAUSE_TIMEOUT
 
- VCHIQ_CONNSTATE_PAUSING
 
- VCHIQ_CONNSTATE_RESUME_TIMEOUT
 
- VCHIQ_CONNSTATE_RESUMING
 
- VCHIQ_CONNSTATE_T
 
- VCHIQ_CORE_H
 
- VCHIQ_DEBUGFS_H
 
- VCHIQ_ENABLE_DEBUG
 
- VCHIQ_ENABLE_STATS
 
- VCHIQ_ERROR
 
- VCHIQ_FOURCC_AS_4CHARS
 
- VCHIQ_FOURCC_INVALID
 
- VCHIQ_FOURCC_IS_LEGAL
 
- VCHIQ_GET_SERVICE_FOURCC
 
- VCHIQ_GET_SERVICE_USERDATA
 
- VCHIQ_IF_H
 
- VCHIQ_INIT_RETRIES
 
- VCHIQ_INSTANCE_T
 
- VCHIQ_INVALID_HANDLE
 
- VCHIQ_IOCTLS_H
 
- VCHIQ_IOC_AWAIT_COMPLETION
 
- VCHIQ_IOC_AWAIT_COMPLETION32
 
- VCHIQ_IOC_CLOSE_DELIVERED
 
- VCHIQ_IOC_CLOSE_SERVICE
 
- VCHIQ_IOC_CONNECT
 
- VCHIQ_IOC_CREATE_SERVICE
 
- VCHIQ_IOC_CREATE_SERVICE32
 
- VCHIQ_IOC_DEQUEUE_MESSAGE
 
- VCHIQ_IOC_DEQUEUE_MESSAGE32
 
- VCHIQ_IOC_DUMP_PHYS_MEM
 
- VCHIQ_IOC_GET_CLIENT_ID
 
- VCHIQ_IOC_GET_CONFIG
 
- VCHIQ_IOC_GET_CONFIG32
 
- VCHIQ_IOC_LIB_VERSION
 
- VCHIQ_IOC_MAGIC
 
- VCHIQ_IOC_MAX
 
- VCHIQ_IOC_QUEUE_BULK_RECEIVE
 
- VCHIQ_IOC_QUEUE_BULK_RECEIVE32
 
- VCHIQ_IOC_QUEUE_BULK_TRANSMIT
 
- VCHIQ_IOC_QUEUE_BULK_TRANSMIT32
 
- VCHIQ_IOC_QUEUE_MESSAGE
 
- VCHIQ_IOC_QUEUE_MESSAGE32
 
- VCHIQ_IOC_RELEASE_SERVICE
 
- VCHIQ_IOC_REMOVE_SERVICE
 
- VCHIQ_IOC_SET_SERVICE_OPTION
 
- VCHIQ_IOC_SHUTDOWN
 
- VCHIQ_IOC_USE_SERVICE
 
- VCHIQ_LOG_DEFAULT
 
- VCHIQ_LOG_ERROR
 
- VCHIQ_LOG_ERROR_STR
 
- VCHIQ_LOG_INFO
 
- VCHIQ_LOG_INFO_STR
 
- VCHIQ_LOG_PREFIX
 
- VCHIQ_LOG_TRACE
 
- VCHIQ_LOG_TRACE_STR
 
- VCHIQ_LOG_WARNING
 
- VCHIQ_LOG_WARNING_STR
 
- VCHIQ_MAGIC
 
- VCHIQ_MAKE_FOURCC
 
- VCHIQ_MAKE_MSG
 
- VCHIQ_MAX_MSG_SIZE
 
- VCHIQ_MAX_SERVICES
 
- VCHIQ_MAX_SLOTS
 
- VCHIQ_MAX_SLOTS_PER_SIDE
 
- VCHIQ_MAX_STATES
 
- VCHIQ_MESSAGE_AVAILABLE
 
- VCHIQ_MMAL_MAX_COMPONENTS
 
- VCHIQ_MSGID_CLAIMED
 
- VCHIQ_MSGID_PADDING
 
- VCHIQ_MSG_BULK_RX
 
- VCHIQ_MSG_BULK_RX_DONE
 
- VCHIQ_MSG_BULK_TX
 
- VCHIQ_MSG_BULK_TX_DONE
 
- VCHIQ_MSG_CLOSE
 
- VCHIQ_MSG_CONNECT
 
- VCHIQ_MSG_DATA
 
- VCHIQ_MSG_DSTPORT
 
- VCHIQ_MSG_OPEN
 
- VCHIQ_MSG_OPENACK
 
- VCHIQ_MSG_PADDING
 
- VCHIQ_MSG_PAUSE
 
- VCHIQ_MSG_REMOTE_RELEASE
 
- VCHIQ_MSG_REMOTE_USE
 
- VCHIQ_MSG_REMOTE_USE_ACTIVE
 
- VCHIQ_MSG_RESUME
 
- VCHIQ_MSG_SRCPORT
 
- VCHIQ_MSG_TYPE
 
- VCHIQ_NUM_CURRENT_BULKS
 
- VCHIQ_NUM_SERVICE_BULKS
 
- VCHIQ_PAGELIST_H
 
- VCHIQ_PLATFORM_FRAGMENTS_COUNT_IDX
 
- VCHIQ_PLATFORM_FRAGMENTS_OFFSET_IDX
 
- VCHIQ_PLATFORM_STATE_T
 
- VCHIQ_POLL_COUNT
 
- VCHIQ_POLL_REMOVE
 
- VCHIQ_POLL_RXNOTIFY
 
- VCHIQ_POLL_TERMINATE
 
- VCHIQ_POLL_TXNOTIFY
 
- VCHIQ_PORT_FREE
 
- VCHIQ_PORT_IS_VALID
 
- VCHIQ_PORT_MAX
 
- VCHIQ_REASON_T
 
- VCHIQ_RETRY
 
- VCHIQ_SERVICE_CLOSED
 
- VCHIQ_SERVICE_HANDLE_INVALID
 
- VCHIQ_SERVICE_HANDLE_T
 
- VCHIQ_SERVICE_OPENED
 
- VCHIQ_SERVICE_OPTION_AUTOCLOSE
 
- VCHIQ_SERVICE_OPTION_MESSAGE_QUOTA
 
- VCHIQ_SERVICE_OPTION_SLOT_QUOTA
 
- VCHIQ_SERVICE_OPTION_SYNCHRONOUS
 
- VCHIQ_SERVICE_OPTION_T
 
- VCHIQ_SERVICE_OPTION_TRACE
 
- VCHIQ_SERVICE_STATS_ADD
 
- VCHIQ_SERVICE_STATS_INC
 
- VCHIQ_SLOT_HANDLER_STACK
 
- VCHIQ_SLOT_MASK
 
- VCHIQ_SLOT_QUEUE_MASK
 
- VCHIQ_SLOT_SIZE
 
- VCHIQ_SLOT_ZERO_SLOTS
 
- VCHIQ_SRVSTATE_CLOSED
 
- VCHIQ_SRVSTATE_CLOSERECVD
 
- VCHIQ_SRVSTATE_CLOSESENT
 
- VCHIQ_SRVSTATE_CLOSEWAIT
 
- VCHIQ_SRVSTATE_FREE
 
- VCHIQ_SRVSTATE_HIDDEN
 
- VCHIQ_SRVSTATE_LISTENING
 
- VCHIQ_SRVSTATE_OPEN
 
- VCHIQ_SRVSTATE_OPENING
 
- VCHIQ_SRVSTATE_OPENSYNC
 
- VCHIQ_STATS_INC
 
- VCHIQ_STATUS_T
 
- VCHIQ_SUCCESS
 
- VCHIQ_UTIL_H
 
- VCHIQ_VCHIQ_H
 
- VCHIQ_VERSION
 
- VCHIQ_VERSION_CLOSE_DELIVERED
 
- VCHIQ_VERSION_LIB_VERSION
 
- VCHIQ_VERSION_MIN
 
- VCHIQ_VERSION_SYNCHRONOUS_MODE
 
- VCHI_BULK_ALIGN
 
- VCHI_BULK_ALIGNED
 
- VCHI_BULK_ALIGN_NBYTES
 
- VCHI_BULK_GRANULARITY
 
- VCHI_BULK_ROUND_DOWN
 
- VCHI_BULK_ROUND_UP
 
- VCHI_CALLBACK_BULK_DATA_READ
 
- VCHI_CALLBACK_BULK_RECEIVED
 
- VCHI_CALLBACK_BULK_RECEIVE_ABORTED
 
- VCHI_CALLBACK_BULK_RX_SPACE_AVAILABLE
 
- VCHI_CALLBACK_BULK_SENT
 
- VCHI_CALLBACK_BULK_TRANSMIT_ABORTED
 
- VCHI_CALLBACK_BULK_TX_SPACE_AVAILABLE
 
- VCHI_CALLBACK_FORCED_POWER_OFF
 
- VCHI_CALLBACK_MSG_AVAILABLE
 
- VCHI_CALLBACK_MSG_SENT
 
- VCHI_CALLBACK_MSG_SPACE_AVAILABLE
 
- VCHI_CALLBACK_PEER_OFF
 
- VCHI_CALLBACK_PEER_ON
 
- VCHI_CALLBACK_PEER_RESUMED
 
- VCHI_CALLBACK_PEER_SUSPENDED
 
- VCHI_CALLBACK_REASON_MAX
 
- VCHI_CALLBACK_REASON_MIN
 
- VCHI_CALLBACK_REASON_T
 
- VCHI_CALLBACK_SENT_XOFF
 
- VCHI_CALLBACK_SENT_XON
 
- VCHI_CALLBACK_SERVICE_CLOSED
 
- VCHI_CALLBACK_SERVICE_OPENED
 
- VCHI_CCP2TX_IDLE_TIMEOUT
 
- VCHI_CCP2TX_OFF_TIMEOUT
 
- VCHI_CFG_H_
 
- VCHI_COMMON_H_
 
- VCHI_CONNECTION_API_T
 
- VCHI_CRC_CONTROL_T
 
- VCHI_CRC_EVERYTHING
 
- VCHI_CRC_NOTHING
 
- VCHI_CRC_PER_SERVICE
 
- VCHI_FLAGS_ALIGN_SLOT
 
- VCHI_FLAGS_ALLOW_PARTIAL
 
- VCHI_FLAGS_BLOCK_UNTIL_DATA_READ
 
- VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE
 
- VCHI_FLAGS_BLOCK_UNTIL_QUEUED
 
- VCHI_FLAGS_BULK_AUX_COMPLETE
 
- VCHI_FLAGS_BULK_AUX_QUEUED
 
- VCHI_FLAGS_BULK_DATA_COMPLETE
 
- VCHI_FLAGS_BULK_DATA_QUEUED
 
- VCHI_FLAGS_CALLBACK_WHEN_DATA_READ
 
- VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE
 
- VCHI_FLAGS_INTERNAL
 
- VCHI_FLAGS_NONE
 
- VCHI_FLAGS_T
 
- VCHI_H_
 
- VCHI_INSTANCE_T
 
- VCHI_MAX_BULK_CHUNK_SIZE_CCP2
 
- VCHI_MAX_BULK_CHUNK_SIZE_MPHI
 
- VCHI_MAX_BULK_RX_CHANNELS_PER_CONNECTION
 
- VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION
 
- VCHI_MAX_MSG_SIZE
 
- VCHI_MAX_NUM_CONNECTIONS
 
- VCHI_MAX_PEER_BULK_REQUESTS
 
- VCHI_MAX_SERVICES_PER_CONNECTION
 
- VCHI_MESSAGE_DRIVER_T
 
- VCHI_MIN_BULK_SIZE
 
- VCHI_NUM_READ_SLOTS
 
- VCHI_NUM_WRITE_SLOTS
 
- VCHI_RX_BULK_QUEUE_SIZE
 
- VCHI_RX_MSG_QUEUE_SIZE
 
- VCHI_SERVICE_HANDLE_T
 
- VCHI_SERVICE_OPTION_MAX
 
- VCHI_SERVICE_OPTION_MIN
 
- VCHI_SERVICE_OPTION_SYNCHRONOUS
 
- VCHI_SERVICE_OPTION_T
 
- VCHI_SERVICE_OPTION_TRACE
 
- VCHI_TX_BULK_QUEUE_SIZE
 
- VCHI_TX_MSG_QUEUE_SIZE
 
- VCHI_VERSION
 
- VCHI_VERSION_EX
 
- VCHI_XOFF_THRESHOLD
 
- VCHI_XON_THRESHOLD
 
- VCIV
 
- VCLK0_FB_DIV
 
- VCLK0_POST
 
- VCLK100_300
 
- VCLK100_315
 
- VCLK106_5
 
- VCLK108
 
- VCLK108_2_300
 
- VCLK108_2_315
 
- VCLK108_3_300
 
- VCLK108_3_315
 
- VCLK118_25
 
- VCLK119
 
- VCLK121_315
 
- VCLK130_315
 
- VCLK135
 
- VCLK146_25
 
- VCLK148_5
 
- VCLK154
 
- VCLK157_5
 
- VCLK162
 
- VCLK162_315
 
- VCLK1_FB_DIV
 
- VCLK1_POST
 
- VCLK25_175
 
- VCLK28
 
- VCLK28_322
 
- VCLK2_DIV1_EN
 
- VCLK2_DIV_EN
 
- VCLK2_DIV_MASK
 
- VCLK2_DIV_RESET
 
- VCLK2_EN
 
- VCLK2_FB_DIV
 
- VCLK2_POST
 
- VCLK2_SEL_MASK
 
- VCLK2_SEL_SHIFT
 
- VCLK2_SOFT_RESET
 
- VCLK2_VCO_DIV_SEL
 
- VCLK2_VCO_M
 
- VCLK2_VCO_MN_MSBS
 
- VCLK2_VCO_N
 
- VCLK31_5
 
- VCLK34_300
 
- VCLK34_315
 
- VCLK36
 
- VCLK3_FB_DIV
 
- VCLK3_POST
 
- VCLK40
 
- VCLK49_5
 
- VCLK50
 
- VCLK56_25
 
- VCLK65
 
- VCLK65_300
 
- VCLK65_315
 
- VCLK68_315
 
- VCLK71
 
- VCLK75
 
- VCLK78_75
 
- VCLK81_300
 
- VCLK81_315
 
- VCLK83_5
 
- VCLK85_5
 
- VCLK88_75
 
- VCLK94_5
 
- VCLK97_75
 
- VCLKCON0
 
- VCLKCON0_CLKVALUP
 
- VCLKCON0_VCLKFREE
 
- VCLKCON1
 
- VCLKCON1_CLKVAL_NUM_VCLK
 
- VCLKCON2
 
- VCLKCR
 
- VCLKDataPtrOffset
 
- VCLK_1024x576
 
- VCLK_1152x864
 
- VCLK_1280x720
 
- VCLK_1280x720_2
 
- VCLK_1280x768_2
 
- VCLK_1280x768_3
 
- VCLK_1280x800_315
 
- VCLK_1280x800_315_2
 
- VCLK_1280x854
 
- VCLK_1360x768
 
- VCLK_2X_SEL_DEL_SHIFT
 
- VCLK_720x480
 
- VCLK_720x576
 
- VCLK_768x576
 
- VCLK_800x480
 
- VCLK_848x480
 
- VCLK_856x480
 
- VCLK_CUSTOM_300
 
- VCLK_CUSTOM_315
 
- VCLK_DAC_PM_EN
 
- VCLK_DEL_SHIFT
 
- VCLK_DIR_CNTL_EN
 
- VCLK_DIV12_EN
 
- VCLK_DIV1_EN
 
- VCLK_DIV2_EN
 
- VCLK_DIV4_EN
 
- VCLK_DIV6_EN
 
- VCLK_DIVIDER_MASK
 
- VCLK_DIVISOR_VGA0
 
- VCLK_DIVISOR_VGA1
 
- VCLK_DIV_EN
 
- VCLK_DIV_MASK
 
- VCLK_DIV_RESET
 
- VCLK_ECP_CNTL
 
- VCLK_ECP_CNTL__ECP_DIV_MASK
 
- VCLK_ECP_CNTL__ECP_FORCE_ON
 
- VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb
 
- VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb
 
- VCLK_ECP_CNTL__PIXCLK_SRC_INVERT
 
- VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF
 
- VCLK_ECP_CNTL__SUBCLK_FORCE_ON
 
- VCLK_ECP_CNTL__VCLK_INVERT
 
- VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK
 
- VCLK_EN
 
- VCLK_LCD_OFF
 
- VCLK_POST_DIV
 
- VCLK_SEL_MASK
 
- VCLK_SEL_SHIFT
 
- VCLK_SOFT_RESET
 
- VCLK_SRC_SEL
 
- VCLK_SRC_SEL_BYTECLK
 
- VCLK_SRC_SEL_CPUCLK
 
- VCLK_SRC_SEL_MASK
 
- VCLK_SRC_SEL_PPLLCLK
 
- VCLK_SRC_SEL_PSCANCLK
 
- VCLOCK_HVCLOCK
 
- VCLOCK_MAX
 
- VCLOCK_NONE
 
- VCLOCK_PVCLOCK
 
- VCLOCK_STICK
 
- VCLOCK_TICK
 
- VCLOCK_TSC
 
- VCMOFSET
 
- VCMPEQUB_RC
 
- VCMPEQUD_RC
 
- VCMSK
 
- VCMSK_COLKEY_M
 
- VCN
 
- VCN25_MAX_HW_INSTANCES_ARCTURUS
 
- VCNL4000
 
- VCNL4000_AL_OD
 
- VCNL4000_AL_PARAM
 
- VCNL4000_AL_RDY
 
- VCNL4000_AL_RESULT_HI
 
- VCNL4000_AL_RESULT_LO
 
- VCNL4000_COMMAND
 
- VCNL4000_DRV_NAME
 
- VCNL4000_LED_CURRENT
 
- VCNL4000_PROD_ID
 
- VCNL4000_PROD_REV
 
- VCNL4000_PS_MEAS_FREQ
 
- VCNL4000_PS_MOD_ADJ
 
- VCNL4000_PS_OD
 
- VCNL4000_PS_RDY
 
- VCNL4000_PS_RESULT_HI
 
- VCNL4000_PS_RESULT_LO
 
- VCNL4010
 
- VCNL4010_PROD_ID
 
- VCNL4035_ALS_CONF
 
- VCNL4035_ALS_DATA
 
- VCNL4035_ALS_IT_DEFAULT
 
- VCNL4035_ALS_IT_MASK
 
- VCNL4035_ALS_PERS_DEFAULT
 
- VCNL4035_ALS_PERS_MASK
 
- VCNL4035_ALS_THDH
 
- VCNL4035_ALS_THDH_DEFAULT
 
- VCNL4035_ALS_THDL
 
- VCNL4035_ALS_THDL_DEFAULT
 
- VCNL4035_CHAN_INDEX_LIGHT
 
- VCNL4035_CHAN_INDEX_WHITE_LED
 
- VCNL4035_DEV_ID
 
- VCNL4035_DEV_ID_VAL
 
- VCNL4035_DRV_NAME
 
- VCNL4035_INT_ALS_IF_H_MASK
 
- VCNL4035_INT_ALS_IF_L_MASK
 
- VCNL4035_INT_FLAG
 
- VCNL4035_IRQ_NAME
 
- VCNL4035_MODE_ALS_DISABLE
 
- VCNL4035_MODE_ALS_ENABLE
 
- VCNL4035_MODE_ALS_INT_DISABLE
 
- VCNL4035_MODE_ALS_INT_ENABLE
 
- VCNL4035_MODE_ALS_INT_MASK
 
- VCNL4035_MODE_ALS_MASK
 
- VCNL4035_MODE_ALS_WHITE_CHAN
 
- VCNL4035_REGMAP_NAME
 
- VCNL4035_SLEEP_DELAY_MS
 
- VCNL4035_WHITE_DATA
 
- VCNL4040
 
- VCNL4040_DEV_ID
 
- VCNL4040_PROD_ID
 
- VCNL4200
 
- VCNL4200_AL_CONF
 
- VCNL4200_AL_DATA
 
- VCNL4200_DEV_ID
 
- VCNL4200_PROD_ID
 
- VCNL4200_PS_CONF1
 
- VCNL4200_PS_DATA
 
- VCNTL1
 
- VCNTL2
 
- VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE
 
- VCN_1_0__SRCID__UVD_ENC_LOW_LATENCY
 
- VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT
 
- VCN_2_0__SRCID__JPEG_DECODE
 
- VCN_2_0__SRCID__JPEG_ENCODE
 
- VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE
 
- VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY
 
- VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT
 
- VCN_AON_IP_ADDRESS_2_0
 
- VCN_AON_SOC_ADDRESS_2_0
 
- VCN_BASE__INST0_SEG0
 
- VCN_BASE__INST0_SEG1
 
- VCN_BASE__INST0_SEG2
 
- VCN_BASE__INST0_SEG3
 
- VCN_BASE__INST0_SEG4
 
- VCN_BASE__INST0_SEG5
 
- VCN_BASE__INST1_SEG0
 
- VCN_BASE__INST1_SEG1
 
- VCN_BASE__INST1_SEG2
 
- VCN_BASE__INST1_SEG3
 
- VCN_BASE__INST1_SEG4
 
- VCN_BASE__INST1_SEG5
 
- VCN_BASE__INST2_SEG0
 
- VCN_BASE__INST2_SEG1
 
- VCN_BASE__INST2_SEG2
 
- VCN_BASE__INST2_SEG3
 
- VCN_BASE__INST2_SEG4
 
- VCN_BASE__INST2_SEG5
 
- VCN_BASE__INST3_SEG0
 
- VCN_BASE__INST3_SEG1
 
- VCN_BASE__INST3_SEG2
 
- VCN_BASE__INST3_SEG3
 
- VCN_BASE__INST3_SEG4
 
- VCN_BASE__INST3_SEG5
 
- VCN_BASE__INST4_SEG0
 
- VCN_BASE__INST4_SEG1
 
- VCN_BASE__INST4_SEG2
 
- VCN_BASE__INST4_SEG3
 
- VCN_BASE__INST4_SEG4
 
- VCN_BASE__INST4_SEG5
 
- VCN_BASE__INST5_SEG0
 
- VCN_BASE__INST5_SEG1
 
- VCN_BASE__INST5_SEG2
 
- VCN_BASE__INST5_SEG3
 
- VCN_BASE__INST5_SEG4
 
- VCN_BASE__INST5_SEG5
 
- VCN_DEC_CMD_FENCE
 
- VCN_DEC_CMD_PACKET_END
 
- VCN_DEC_CMD_PACKET_START
 
- VCN_DEC_CMD_REG_READ_COND_WAIT
 
- VCN_DEC_CMD_TRAP
 
- VCN_DEC_CMD_WRITE_REG
 
- VCN_DEC_KMD_CMD
 
- VCN_DPG_STATE__PAUSE
 
- VCN_DPG_STATE__UNPAUSE
 
- VCN_ENC_CMD_END
 
- VCN_ENC_CMD_FENCE
 
- VCN_ENC_CMD_IB
 
- VCN_ENC_CMD_NO_OP
 
- VCN_ENC_CMD_REG_WAIT
 
- VCN_ENC_CMD_REG_WRITE
 
- VCN_ENC_CMD_TRAP
 
- VCN_HWID
 
- VCN_HWIP
 
- VCN_IDLE_TIMEOUT
 
- VCN_VID_IP_ADDRESS_2_0
 
- VCN_VID_SOC_ADDRESS_2_0
 
- VCOBANDSEL_1
 
- VCOBANDSEL_2
 
- VCOBANDSEL_3
 
- VCOBANDSEL_4
 
- VCOBANDSEL_5
 
- VCOBANDSEL_6
 
- VCOCAL_START
 
- VCODEC0_CLK_SRC
 
- VCODEC0_GDSC
 
- VCODEC1_GDSC
 
- VCODEC_AHB_CLK
 
- VCODEC_AHB_RESET
 
- VCODEC_AXI_A_CLK
 
- VCODEC_AXI_A_RESET
 
- VCODEC_AXI_B_CLK
 
- VCODEC_AXI_B_RESET
 
- VCODEC_AXI_CLK
 
- VCODEC_AXI_RESET
 
- VCODEC_CAPABILITY_4K_DISABLED
 
- VCODEC_CLK
 
- VCODEC_DEC_4K_CODED_HEIGHT
 
- VCODEC_DEC_4K_CODED_WIDTH
 
- VCODEC_RESET
 
- VCODEC_SRC
 
- VCODIV2
 
- VCODIV4
 
- VCOMS
 
- VCOM_HSWITCH_ADDR
 
- VCOM_VE_ADDR
 
- VCOM_VS_ADDR
 
- VCOPLL_CM
 
- VCOPLL_CTRL
 
- VCORE0
 
- VCORE_CTRL1_BYP_COMP
 
- VCORE_CTRL1_HW_NSW
 
- VCORE_ENTRY_MAP
 
- VCORE_EXITING
 
- VCORE_EXIT_MAP
 
- VCORE_EXIT_REQ
 
- VCORE_INACTIVE
 
- VCORE_IS_EXITING
 
- VCORE_PIGGYBACK
 
- VCORE_POLLING
 
- VCORE_PREEMPT
 
- VCORE_RUNNING
 
- VCORE_SLEEPING
 
- VCOUNTER
 
- VCO_2_4
 
- VCO_3_6
 
- VCO_BIT_600_MICRO
 
- VCO_CALIBRATION_START
 
- VCO_CHP1
 
- VCO_CHP1_I2C
 
- VCO_CHP2
 
- VCO_CHP2_I2C
 
- VCO_CLKDET_ENABLE
 
- VCO_CLOCK25
 
- VCO_CSYPOS
 
- VCO_CTRL
 
- VCO_CTRL0
 
- VCO_CTRL1
 
- VCO_CTRL10
 
- VCO_CTRL11
 
- VCO_CTRL12
 
- VCO_CTRL13
 
- VCO_CTRL14
 
- VCO_CTRL15
 
- VCO_CTRL30
 
- VCO_CTRL_INIT_VAL
 
- VCO_CTRL_VAL
 
- VCO_DIAG_FW
 
- VCO_DONT_RESET_UPDATE
 
- VCO_DONT_UPDATE_FW
 
- VCO_DPLL_CH1_ENABLE
 
- VCO_ENABLE_DSD
 
- VCO_END_OF_DATA
 
- VCO_FBDIV
 
- VCO_FBDIV_MASK
 
- VCO_FBDIV_SHIFT
 
- VCO_FORCE_UPDATE
 
- VCO_FREQOFFSET_MASK
 
- VCO_FREQOFFSETn
 
- VCO_HIGH
 
- VCO_HIGH_HIGH
 
- VCO_HSYPOS
 
- VCO_ICP
 
- VCO_ICP_MASK
 
- VCO_ICP_SHIFT
 
- VCO_INTERPOL_MASK
 
- VCO_INTERPOL_SHIFT
 
- VCO_IN_CAP_CON_DEFAULT
 
- VCO_IN_CAP_CON_HIGH
 
- VCO_IN_CAP_CON_LOW
 
- VCO_KVCOEXT_ENABLE
 
- VCO_KVCOEXT_MASK
 
- VCO_KVCOEXT_SHIFT
 
- VCO_LOAD_CAP
 
- VCO_LOOP_DIV_BY_16M
 
- VCO_LOOP_DIV_BY_4M
 
- VCO_LOW
 
- VCO_MAX
 
- VCO_MAX_RATE
 
- VCO_MID
 
- VCO_MIN
 
- VCO_MIN_RATE
 
- VCO_MODE
 
- VCO_MODE_MASK
 
- VCO_M_MSBS
 
- VCO_N_MSBS
 
- VCO_POWERUP
 
- VCO_POWERUP_CH1
 
- VCO_POWER_REF
 
- VCO_PREF_DIV_RATIO
 
- VCO_RANGE_CON_SEL
 
- VCO_REFDIV
 
- VCO_REFDIV_1
 
- VCO_REFDIV_2
 
- VCO_REFDIV_3
 
- VCO_REFDIV_4
 
- VCO_REFDIV_MASK
 
- VCO_REFDIV_SHIFT
 
- VCO_REF_CLK_RATE
 
- VCO_REG0V9_SEL_MASK
 
- VCO_REG0V9_SEL_SHIFT
 
- VCO_REG1V45_SEL
 
- VCO_REG1V45_SEL_1V40
 
- VCO_REG1V45_SEL_1V45
 
- VCO_REG1V45_SEL_1V50
 
- VCO_REG1V45_SEL_1V55
 
- VCO_REG1V45_SEL_MASK
 
- VCO_REG1V45_SEL_SHIFT
 
- VCO_RESET
 
- VCO_SECONDS
 
- VCO_SHORTOFFS
 
- VCO_SPEED
 
- VCO_SPEED_1G08_1G21
 
- VCO_SPEED_1G21_1G40
 
- VCO_SPEED_1G40_1G61
 
- VCO_SPEED_1G61_1G86
 
- VCO_SPEED_1G86_2G00
 
- VCO_SPEED_2G00_2G22
 
- VCO_SPEED_2G22
 
- VCO_SPEED_MASK
 
- VCO_SPEED_SHIFT
 
- VCO_SYNC1_MASK
 
- VCO_SYNC1n
 
- VCO_SYNC2_MASK
 
- VCO_SYNC2n
 
- VCO_V2IEXT_ENABLE
 
- VCO_V2IEXT_MASK
 
- VCO_V2IEXT_SHIFT
 
- VCO_VSYPOS
 
- VCO_VTHCAL
 
- VCO_VTHCAL_0V90
 
- VCO_VTHCAL_0V95
 
- VCO_VTHCAL_1V00
 
- VCO_VTHCAL_1V05
 
- VCO_VTHCAL_MASK
 
- VCO_VTHCAL_SHIFT
 
- VCPUOP_down
 
- VCPUOP_get_physid
 
- VCPUOP_get_runstate_info
 
- VCPUOP_initialise
 
- VCPUOP_is_up
 
- VCPUOP_register_runstate_memory_area
 
- VCPUOP_register_vcpu_info
 
- VCPUOP_register_vcpu_time_memory_area
 
- VCPUOP_send_nmi
 
- VCPUOP_set_periodic_timer
 
- VCPUOP_set_singleshot_timer
 
- VCPUOP_stop_periodic_timer
 
- VCPUOP_stop_singleshot_timer
 
- VCPUOP_up
 
- VCPU_ARGS_COMMON
 
- VCPU_ASSIGN_COMMON
 
- VCPU_CFGSHDW
 
- VCPU_CFGSHDW_ASPM_DBNC
 
- VCPU_CFGSHDW_WOL_ENABLE
 
- VCPU_CFGSHDW_WOL_MAGPKT
 
- VCPU_EVENT
 
- VCPU_EXREG_CR3
 
- VCPU_EXREG_PDPTR
 
- VCPU_EXREG_RFLAGS
 
- VCPU_EXREG_SEGMENTS
 
- VCPU_FIELD_COMMON
 
- VCPU_FPR
 
- VCPU_FTR_MMU_V2
 
- VCPU_GPR
 
- VCPU_GPRS_TM
 
- VCPU_GUEST_SPRG
 
- VCPU_HVM_MODE_32B
 
- VCPU_HVM_MODE_64B
 
- VCPU_ID
 
- VCPU_IRQS_MAX_BUF
 
- VCPU_LOAD_NVGPRS
 
- VCPU_NR_MODES
 
- VCPU_PROTO_COMMON
 
- VCPU_R10
 
- VCPU_R11
 
- VCPU_R12
 
- VCPU_R13
 
- VCPU_R14
 
- VCPU_R15
 
- VCPU_R8
 
- VCPU_R9
 
- VCPU_RAX
 
- VCPU_RBP
 
- VCPU_RBX
 
- VCPU_RCX
 
- VCPU_RDI
 
- VCPU_RDX
 
- VCPU_REGS_R10
 
- VCPU_REGS_R11
 
- VCPU_REGS_R12
 
- VCPU_REGS_R13
 
- VCPU_REGS_R14
 
- VCPU_REGS_R15
 
- VCPU_REGS_R8
 
- VCPU_REGS_R9
 
- VCPU_REGS_RAX
 
- VCPU_REGS_RBP
 
- VCPU_REGS_RBX
 
- VCPU_REGS_RCX
 
- VCPU_REGS_RDI
 
- VCPU_REGS_RDX
 
- VCPU_REGS_RIP
 
- VCPU_REGS_RSI
 
- VCPU_REGS_RSP
 
- VCPU_REG_OFFSET_ABT
 
- VCPU_REG_OFFSET_FIQ
 
- VCPU_REG_OFFSET_IRQ
 
- VCPU_REG_OFFSET_SVC
 
- VCPU_REG_OFFSET_UND
 
- VCPU_REG_OFFSET_USR
 
- VCPU_RSI
 
- VCPU_SIZE_BYTES
 
- VCPU_SIZE_LOG
 
- VCPU_SIZE_ORDER
 
- VCPU_SOFT_RESET
 
- VCPU_SREG_CS
 
- VCPU_SREG_DS
 
- VCPU_SREG_ES
 
- VCPU_SREG_FS
 
- VCPU_SREG_GS
 
- VCPU_SREG_LDTR
 
- VCPU_SREG_SS
 
- VCPU_SREG_TR
 
- VCPU_SSHOTTMR_future
 
- VCPU_STAT
 
- VCPU_STATUS
 
- VCPU_STATUS_DRV_RESET
 
- VCPU_STATUS_INIT_DONE
 
- VCPU_TP_PRINTK
 
- VCPU_VSX_FPR
 
- VCPU_VSX_VR
 
- VCPU_WORKAROUND_2_FLAG
 
- VCPU_WORKAROUND_2_FLAG_SHIFT
 
- VCP_UNIT_CLOCK_GATE_DISABLE
 
- VCR
 
- VCRAT_SIZE_FOR_CPU
 
- VCRAT_SIZE_FOR_GPU
 
- VCRC_LENGTH
 
- VCREATE_DATA
 
- VCREATE_FUNCS
 
- VCRITICAL
 
- VCR_ANCDATACNT
 
- VCR_AVSCALE
 
- VCR_AVS_HEN
 
- VCR_AVS_VEN
 
- VCR_CAPDATA
 
- VCR_CAPINTC
 
- VCR_CI_3BUFS
 
- VCR_CI_BSS
 
- VCR_CI_BSWAP
 
- VCR_CI_CCIR601_16
 
- VCR_CI_CCIR601_8
 
- VCR_CI_CCIR656_16
 
- VCR_CI_CCIR656_8
 
- VCR_CI_CFC
 
- VCR_CI_CLKEN
 
- VCR_CI_CLKINV
 
- VCR_CI_CLKPIN
 
- VCR_CI_CONVTYPE
 
- VCR_CI_DIBOTH
 
- VCR_CI_DIBOTH30
 
- VCR_CI_DIEVEN
 
- VCR_CI_DIODD
 
- VCR_CI_ENABLE
 
- VCR_CI_FILTER
 
- VCR_CI_FLDINV
 
- VCR_CI_HDMODE
 
- VCR_CI_HREFINV
 
- VCR_CI_HRLE
 
- VCR_CI_IFSEN
 
- VCR_CI_OFLDINV
 
- VCR_CI_THRESH
 
- VCR_CI_UYVY
 
- VCR_CI_VIPEN
 
- VCR_CI_VIPTYPE
 
- VCR_CI_VREFINV
 
- VCR_CI_VRLE
 
- VCR_CI_VYUY
 
- VCR_CI_YUYV
 
- VCR_CI_YVYU
 
- VCR_DET_CTRL
 
- VCR_HACK_LINES
 
- VCR_HORRANGE
 
- VCR_IC_ACTBUF
 
- VCR_IC_BOTFLD
 
- VCR_IC_EAV
 
- VCR_IC_EVBI
 
- VCR_IC_FBOTFLD
 
- VCR_IC_FFULL
 
- VCR_IC_INTEN
 
- VCR_IC_VBIBUF
 
- VCR_IC_VBIINT
 
- VCR_IC_VSYNC
 
- VCR_INTCTRL
 
- VCR_MAXDATA
 
- VCR_MAXVBI
 
- VCR_TS0ERR
 
- VCR_TS1ERR
 
- VCR_TS2ERR
 
- VCR_TSC
 
- VCR_TSC_BE
 
- VCR_TSC_CBMODE
 
- VCR_TSC_COUNT
 
- VCR_TSC_DROPERR
 
- VCR_TSC_ENABLE
 
- VCR_TSC_METHOD
 
- VCR_TSC_PSSIG
 
- VCR_TSC_SERIAL
 
- VCR_VBIBUF1
 
- VCR_VBIBUF2
 
- VCR_VBIHOR
 
- VCR_VBISTRIDE
 
- VCR_VBIVERT
 
- VCR_VBUF1
 
- VCR_VBUF2
 
- VCR_VBUF3
 
- VCR_VBUF_MASK
 
- VCR_VERTRANGE
 
- VCR_VSTRIDE
 
- VCR_VS_CCD
 
- VCR_VS_COREEN
 
- VCR_VS_STRIDE
 
- VCR_VS_STRIDE_SHIFT
 
- VCR_V_WAIT_1
 
- VCR_V_WAIT_2
 
- VCR_V_WIDTH
 
- VCS0
 
- VCS0_HW
 
- VCS1
 
- VCS1_HW
 
- VCS2
 
- VCS2_AS_CONTEXT_SWITCH
 
- VCS2_HW
 
- VCS2_MI_FLUSH_DW
 
- VCS2_MI_USER_INTERRUPT
 
- VCS3
 
- VCS3_HW
 
- VCSR_BS
 
- VCSR_CLR
 
- VCSR_CTL
 
- VCSR_SET
 
- VCSR_TO
 
- VCS_AS_CONTEXT_SWITCH
 
- VCS_CMD_STREAMER_ERR
 
- VCS_MAJOR
 
- VCS_MI_FLUSH_DW
 
- VCS_MI_USER_INTERRUPT
 
- VCS_MMIO_SYNC_FLUSH
 
- VCS_PAGE_DIRECTORY_FAULT
 
- VCS_TYPE
 
- VCS_WATCHDOG_EXCEEDED
 
- VCS_update
 
- VCT
 
- VCTE_BASE
 
- VCTRL1
 
- VCT_BASE
 
- VCT_COMMAND_MOD_ENABLE_VPS
 
- VCT_COMMAND_MOD_VPS
 
- VCU_AXI_DEC_CLK
 
- VCU_AXI_ENC_CLK
 
- VCU_AXI_MCU_CLK
 
- VCU_BUFFER_B_FRAME
 
- VCU_CORE_CLK
 
- VCU_DECODER_ENABLE
 
- VCU_DEC_CORE_CTRL
 
- VCU_DEC_FPS
 
- VCU_DEC_FRAME_SIZE_X
 
- VCU_DEC_FRAME_SIZE_Y
 
- VCU_DEC_MCU_CTRL
 
- VCU_DEC_VIDEO_STANDARD
 
- VCU_ECODER_ENABLE
 
- VCU_ENC_CLK
 
- VCU_ENC_COLOR_DEPTH
 
- VCU_ENC_COLOR_FORMAT
 
- VCU_ENC_CORE_CTRL
 
- VCU_ENC_FPS
 
- VCU_ENC_FRAME_SIZE_X
 
- VCU_ENC_FRAME_SIZE_Y
 
- VCU_ENC_MCU_CTRL
 
- VCU_ENC_VERTICAL_RANGE
 
- VCU_ENC_VIDEO_STANDARD
 
- VCU_GASKET_INIT
 
- VCU_GASKET_VALUE
 
- VCU_MASK
 
- VCU_MCU_CLK
 
- VCU_MEMORY_DEPTH
 
- VCU_PLL_BYPASS
 
- VCU_PLL_CFG
 
- VCU_PLL_CFG_CP_MASK
 
- VCU_PLL_CFG_CP_SHIFT
 
- VCU_PLL_CFG_LFHF_MASK
 
- VCU_PLL_CFG_LFHF_SHIFT
 
- VCU_PLL_CFG_LOCK_CNT_MASK
 
- VCU_PLL_CFG_LOCK_CNT_SHIFT
 
- VCU_PLL_CFG_LOCK_DLY_MASK
 
- VCU_PLL_CFG_LOCK_DLY_SHIFT
 
- VCU_PLL_CFG_RES_MASK
 
- VCU_PLL_CFG_RES_SHIFT
 
- VCU_PLL_CLK
 
- VCU_PLL_CLK_DEC
 
- VCU_PLL_CTRL
 
- VCU_PLL_CTRL_BYPASS_MASK
 
- VCU_PLL_CTRL_BYPASS_SHIFT
 
- VCU_PLL_CTRL_CLKOUTDIV_MASK
 
- VCU_PLL_CTRL_CLKOUTDIV_SHIFT
 
- VCU_PLL_CTRL_DEFAULT
 
- VCU_PLL_CTRL_FBDIV_MASK
 
- VCU_PLL_CTRL_FBDIV_SHIFT
 
- VCU_PLL_CTRL_POR_IN_MASK
 
- VCU_PLL_CTRL_POR_IN_SHIFT
 
- VCU_PLL_CTRL_PWR_POR_MASK
 
- VCU_PLL_CTRL_PWR_POR_SHIFT
 
- VCU_PLL_CTRL_RESET_MASK
 
- VCU_PLL_CTRL_RESET_SHIFT
 
- VCU_PLL_DIV2
 
- VCU_PLL_DIVISOR_MASK
 
- VCU_PLL_DIVISOR_SHIFT
 
- VCU_PLL_STATUS
 
- VCU_PLL_STATUS_LOCK_STATUS_MASK
 
- VCU_SHIFT
 
- VCU_SRCSEL_MASK
 
- VCU_SRCSEL_PLL
 
- VCU_SRCSEL_SHIFT
 
- VCU_STATUS
 
- VCU_WPP_EN
 
- VC_ALTGRLOCK
 
- VC_ALTLOCK
 
- VC_AND_TC
 
- VC_APPLIC
 
- VC_AUDIOSERV_MIN_VER
 
- VC_AUDIOSERV_VER
 
- VC_AUDIO_MSG_TYPE_CLOSE
 
- VC_AUDIO_MSG_TYPE_COMPLETE
 
- VC_AUDIO_MSG_TYPE_CONFIG
 
- VC_AUDIO_MSG_TYPE_CONTROL
 
- VC_AUDIO_MSG_TYPE_MAX
 
- VC_AUDIO_MSG_TYPE_OPEN
 
- VC_AUDIO_MSG_TYPE_RESULT
 
- VC_AUDIO_MSG_TYPE_START
 
- VC_AUDIO_MSG_TYPE_STOP
 
- VC_AUDIO_MSG_TYPE_WRITE
 
- VC_AUDIO_SERVER_NAME
 
- VC_AUDIO_WRITE_COOKIE1
 
- VC_AUDIO_WRITE_COOKIE2
 
- VC_CAPSLOCK
 
- VC_CKMODE
 
- VC_CRLF
 
- VC_CTRLLLOCK
 
- VC_CTRLLOCK
 
- VC_CTRLRLOCK
 
- VC_ENABLE
 
- VC_ENHANCE
 
- VC_INDEX
 
- VC_INPUT_TERMINAL
 
- VC_KANALOCK
 
- VC_LKUP_BASE
 
- VC_MASK
 
- VC_MAXDATASIZE
 
- VC_MAXMSGSIZE
 
- VC_MEDIUMRAW
 
- VC_META
 
- VC_MMAL_MIN_VER
 
- VC_MMAL_SERVER_NAME
 
- VC_MMAL_VER
 
- VC_NUM
 
- VC_NUMLOCK
 
- VC_OFF
 
- VC_ONLY
 
- VC_OUTPUT_TERMINAL
 
- VC_PROCESSING_UNIT
 
- VC_RAW
 
- VC_REPEAT
 
- VC_RESIZE_MAXCOL
 
- VC_RESIZE_MAXROW
 
- VC_RESUME_FAILED
 
- VC_RESUME_IDLE
 
- VC_RESUME_IN_PROGRESS
 
- VC_RESUME_NUM_OFFSET
 
- VC_RESUME_REQUESTED
 
- VC_RESUME_RESUMED
 
- VC_SCROLLOCK
 
- VC_SELECTOR_UNIT
 
- VC_SHIFT
 
- VC_SHIFTLLOCK
 
- VC_SHIFTLOCK
 
- VC_SHIFTRLOCK
 
- VC_SIZE
 
- VC_SUSPEND_FAILED
 
- VC_SUSPEND_FORCE_CANCELED
 
- VC_SUSPEND_IDLE
 
- VC_SUSPEND_IN_PROGRESS
 
- VC_SUSPEND_NUM_OFFSET
 
- VC_SUSPEND_REJECTED
 
- VC_SUSPEND_REQUESTED
 
- VC_SUSPEND_SUSPENDED
 
- VC_TUNER_PATH
 
- VC_UNICODE
 
- VC_UNI_SCREEN_DEBUG
 
- VC_XLATE
 
- VD
 
- VD09
 
- VD18
 
- VD1_BLEND_SRC_CTRL
 
- VD1_IF0_CANVAS0
 
- VD1_IF0_CANVAS1
 
- VD1_IF0_CHROMA0_RPT_PAT
 
- VD1_IF0_CHROMA1_RPT_PAT
 
- VD1_IF0_CHROMA_PSEL
 
- VD1_IF0_CHROMA_X0
 
- VD1_IF0_CHROMA_X1
 
- VD1_IF0_CHROMA_Y0
 
- VD1_IF0_CHROMA_Y1
 
- VD1_IF0_DUMMY_PIXEL
 
- VD1_IF0_GEN_REG
 
- VD1_IF0_GEN_REG2
 
- VD1_IF0_GEN_REG3
 
- VD1_IF0_LUMA0_RPT_PAT
 
- VD1_IF0_LUMA1_RPT_PAT
 
- VD1_IF0_LUMA_FIFO_SIZE
 
- VD1_IF0_LUMA_PSEL
 
- VD1_IF0_LUMA_X0
 
- VD1_IF0_LUMA_X1
 
- VD1_IF0_LUMA_Y0
 
- VD1_IF0_LUMA_Y1
 
- VD1_IF0_PROT_CNTL
 
- VD1_IF0_RANGE_MAP_CB
 
- VD1_IF0_RANGE_MAP_CR
 
- VD1_IF0_RANGE_MAP_Y
 
- VD1_IF0_RPT_LOOP
 
- VD25
 
- VD2_BLEND_SRC_CTRL
 
- VD2_IF0_CANVAS0
 
- VD2_IF0_CANVAS1
 
- VD2_IF0_CHROMA0_RPT_PAT
 
- VD2_IF0_CHROMA1_RPT_PAT
 
- VD2_IF0_CHROMA_PSEL
 
- VD2_IF0_CHROMA_X0
 
- VD2_IF0_CHROMA_X1
 
- VD2_IF0_CHROMA_Y0
 
- VD2_IF0_CHROMA_Y1
 
- VD2_IF0_DUMMY_PIXEL
 
- VD2_IF0_GEN_REG
 
- VD2_IF0_GEN_REG2
 
- VD2_IF0_LUMA0_RPT_PAT
 
- VD2_IF0_LUMA1_RPT_PAT
 
- VD2_IF0_LUMA_FIFO_SIZE
 
- VD2_IF0_LUMA_PSEL
 
- VD2_IF0_LUMA_X0
 
- VD2_IF0_LUMA_X1
 
- VD2_IF0_LUMA_Y0
 
- VD2_IF0_LUMA_Y1
 
- VD2_IF0_PROT_CNTL
 
- VD2_IF0_RANGE_MAP_CB
 
- VD2_IF0_RANGE_MAP_CR
 
- VD2_IF0_RANGE_MAP_Y
 
- VD2_IF0_RPT_LOOP
 
- VD2_PPS_DUMMY_DATA
 
- VD2_V_END
 
- VD2_V_START
 
- VD33
 
- VDAADAPINFO_VERSION
 
- VDAADAPINFO_VERSION0
 
- VDAAE_GROUP_STATE
 
- VDAAE_GRPOPPROC_CANCELABLE
 
- VDAAE_GRPOPPROC_HALTABLE
 
- VDAAE_GRPOPPROC_MASK
 
- VDAAE_GRPOPPROC_RESUMABLE
 
- VDAAE_GRPOPPROC_STARTABLE
 
- VDAAE_GRPOPSTAT_FAULTED
 
- VDAAE_GRPOPSTAT_HALTED
 
- VDAAE_GRPOPSTAT_INT
 
- VDAAE_GRPOPSTAT_INVALID
 
- VDAAE_GRPOPSTAT_MASK
 
- VDAAE_GRPOPSTAT_OK
 
- VDAAE_HDRF_EVENT_ACK
 
- VDAAE_HDR_TYPE_DEV
 
- VDAAE_HDR_TYPE_DISK
 
- VDAAE_HDR_TYPE_LOG_CRIT
 
- VDAAE_HDR_TYPE_LOG_FAIL
 
- VDAAE_HDR_TYPE_LOG_INFO
 
- VDAAE_HDR_TYPE_LOG_WARN
 
- VDAAE_HDR_TYPE_LU
 
- VDAAE_HDR_TYPE_MUTE
 
- VDAAE_HDR_TYPE_NVC
 
- VDAAE_HDR_TYPE_PWRMGT
 
- VDAAE_HDR_TYPE_RAID
 
- VDAAE_HDR_TYPE_RESET
 
- VDAAE_HDR_TYPE_TLG_CRIT
 
- VDAAE_HDR_TYPE_TLG_INFO
 
- VDAAE_HDR_TYPE_TLG_WARN
 
- VDAAE_HDR_VER_0
 
- VDAAE_LOG_STRSZ
 
- VDAAE_LU_BUSSCAN
 
- VDAAE_LU_DEGRADED
 
- VDAAE_LU_DELETED
 
- VDAAE_LU_DISC
 
- VDAAE_LU_FACTORY_DISABLED
 
- VDAAE_LU_LOST
 
- VDAAE_LU_NOT_PRESENT
 
- VDAAE_LU_OFFLINE
 
- VDAAE_LU_ONLINE
 
- VDAAE_LU_PASSTHROUGH
 
- VDAAE_LU_PHYS_ID
 
- VDAAE_LU_STATE
 
- VDAAE_LU_UNDEFINED
 
- VDAAE_LU_UNKNOWN
 
- VDAAE_MEMBER_CHG
 
- VDAAE_MEM_STATE_CHG
 
- VDAAE_PART_CHG
 
- VDAAE_RAID_BASIC
 
- VDAAE_RAID_DEGRADED
 
- VDAAE_RAID_DELETED
 
- VDAAE_RAID_EXTREME
 
- VDAAE_RAID_INVALID
 
- VDAAE_RAID_NEW
 
- VDAAE_RAID_OFFLINE
 
- VDAAE_RAID_ONLINE
 
- VDAAE_RAID_UNKNOWN
 
- VDAAE_RAID_WAITING
 
- VDAAE_RBLD_CONV
 
- VDAAE_RBLD_ERASE
 
- VDAAE_RBLD_FULL_INIT
 
- VDAAE_RBLD_NONE
 
- VDAAE_RBLD_PATTERN
 
- VDAAE_RBLD_PROG
 
- VDAAE_RBLD_QUICK_INIT
 
- VDAAE_RBLD_REBUILD
 
- VDAAE_RBLD_RECOV_REBUILD
 
- VDAAE_RBLD_SECT_SCAN
 
- VDAAE_RBLD_SECT_SCAN_PARITY
 
- VDAAE_RBLD_SECT_SCAN_PARITY_FIX
 
- VDAAE_RBLD_STATE
 
- VDAAE_RBLD_UNKNOWN
 
- VDAAE_TLG_STRSZ
 
- VDABUZZI_BUZZER_LAST
 
- VDABUZZI_BUZZER_OFF
 
- VDABUZZI_BUZZER_ON
 
- VDABUZZI_DURATION_INDEFINITE
 
- VDAC_COMPONENT
 
- VDAC_CONFIG_HD_V2
 
- VDAC_CONFIG_SD_V2
 
- VDAC_CONFIG_SD_V3
 
- VDAC_SEL_MASK
 
- VDAC_SEL_SHIFT
 
- VDAC_ST_MASK
 
- VDAC_ST_SHIFT
 
- VDAC_S_VIDEO
 
- VDADEVFEAT_DH_SUPP
 
- VDADEVFEAT_ENC_SERV
 
- VDADEVFEAT_IDENT
 
- VDADEVFEAT_PHYS_ID
 
- VDADEVINFO_VERSION
 
- VDADEVINFO_VERSION0
 
- VDADEVINFO_VERSION1
 
- VDADEVINFO_VERSION2
 
- VDADEVINFO_VERSION3
 
- VDADEVSTAT_ASSIGNED
 
- VDADEVSTAT_AVAIL
 
- VDADEVSTAT_CORRUPT
 
- VDADEVSTAT_INVALID
 
- VDADEVSTAT_LCLSPARE
 
- VDADEVSTAT_PT_MAINT
 
- VDADEVSTAT_SPARE
 
- VDADEVSTAT_UNAVAIL
 
- VDADEVSTAT_UNUSEABLE
 
- VDADHSM_CALCSTAT_GOOD
 
- VDADHSM_CALCSTAT_OLDAGE
 
- VDADHSM_CALCSTAT_PREFAIL
 
- VDADHSM_CALCSTAT_UNKNOWN
 
- VDADHSM_RAWSTAT_ERROR_RATE_ATTR
 
- VDADHSM_RAWSTAT_EVENT_COUNT_ATTR
 
- VDADHSM_RAWSTAT_ONLINE_COLLECTION
 
- VDADHSM_RAWSTAT_PERFORMANCE_ATTR
 
- VDADHSM_RAWSTAT_PREFAIL_WARRANTY
 
- VDADHSM_RAWSTAT_SELF_PRESERVING_ATTR
 
- VDADH_RQQUAL_INFOEXC
 
- VDADH_RQQUAL_MEDDEF
 
- VDADH_RQQUAL_SMART
 
- VDADH_RQTYPE_CACHE
 
- VDADH_RQTYPE_FETCH
 
- VDADH_RQTYPE_GET_STAT
 
- VDADH_RQTYPE_SET_STAT
 
- VDADH_SMARTSTAT_ERR
 
- VDADH_SMARTSTAT_OK
 
- VDADH_STAT_DISABLE
 
- VDADH_STAT_ENABLE
 
- VDAGRPOPPROC_CANCELABLE
 
- VDAGRPOPPROC_HALTABLE
 
- VDAGRPOPPROC_MASK
 
- VDAGRPOPPROC_RESUMABLE
 
- VDAGRPOPPROC_STARTABLE
 
- VDAGRPOPSTAT_FAULTED
 
- VDAGRPOPSTAT_HALTED
 
- VDAGRPOPSTAT_INT
 
- VDAGRPOPSTAT_INVALID
 
- VDAGRPOPSTAT_MASK
 
- VDAGRPOPSTAT_OK
 
- VDALINKSPEED_1GB
 
- VDALINKSPEED_1_5GB
 
- VDALINKSPEED_2GB
 
- VDALINKSPEED_3GB
 
- VDALINKSPEED_4GB
 
- VDALINKSPEED_6GB
 
- VDALINKSPEED_8GB
 
- VDALINKSPEED_UNKNOWN
 
- VDAMBRSTATE_DEGRADED
 
- VDAMBRSTATE_FAULTED
 
- VDAMBRSTATE_INCOMPAT
 
- VDAMBRSTATE_MISREAD
 
- VDAMBRSTATE_ONLINE
 
- VDAMBRSTATE_UNAVAIL
 
- VDAMDF_ALL
 
- VDAMDF_DRIVETEST
 
- VDAMDF_NEW
 
- VDAMDF_READ
 
- VDAMDF_RUN
 
- VDAMDF_RUN_ALL
 
- VDAMDF_RUN_READ
 
- VDAMDF_RUN_WRITE
 
- VDAMDF_WRITE
 
- VDAMD_LEN_LAST
 
- VDAMD_LEN_MASK
 
- VDAMET_ALL_DEVICES
 
- VDAMET_METACT_CLEAR
 
- VDAMET_METACT_NONE
 
- VDAMET_METACT_RETRIEVE
 
- VDAMET_METACT_START
 
- VDAMET_METACT_STOP
 
- VDAMET_TSTACT_NONE
 
- VDAMET_TSTACT_STOP
 
- VDAMET_TSTACT_STRT_INIT
 
- VDAMET_TSTACT_STRT_INIT_VERIFY
 
- VDAMET_TSTACT_STRT_READ
 
- VDAMET_TSTACT_STRT_VERIFY
 
- VDAMET_VERSION
 
- VDAMET_VERSION0
 
- VDAMGT_ADAP_FEATURES
 
- VDAMGT_ADAP_INFO
 
- VDAMGT_ADD_STORAGE
 
- VDAMGT_BUZZER_INFO
 
- VDAMGT_BUZZER_SET
 
- VDAMGT_CFG_SAVE
 
- VDAMGT_DEV_CLEAN
 
- VDAMGT_DEV_FEATURES
 
- VDAMGT_DEV_HEALTH_REQ
 
- VDAMGT_DEV_IDENTIFY
 
- VDAMGT_DEV_IDENTSTOP
 
- VDAMGT_DEV_INFO
 
- VDAMGT_DEV_INFO2
 
- VDAMGT_DEV_INFO2_BYADDR
 
- VDAMGT_DEV_METRICS
 
- VDAMGT_DEV_OPERATION
 
- VDAMGT_DEV_PT_FEATURES
 
- VDAMGT_DEV_PT_INFO
 
- VDAMGT_DEV_SCAN
 
- VDAMGT_FAN_INFO
 
- VDAMGT_GRP_COMMIT
 
- VDAMGT_GRP_COMMIT_INIT
 
- VDAMGT_GRP_COMMIT_INIT_AUTOMAP
 
- VDAMGT_GRP_CREATE
 
- VDAMGT_GRP_DELETE
 
- VDAMGT_GRP_FEATURES
 
- VDAMGT_GRP_INFO
 
- VDAMGT_GRP_OPERATION
 
- VDAMGT_GRP_REBUILD
 
- VDAMGT_LAST_ERROR
 
- VDAMGT_LOCAL_SPARE_ADD
 
- VDAMGT_MEMBER_ADD
 
- VDAMGT_NVCACHE_INFO
 
- VDAMGT_NVCACHE_SET
 
- VDAMGT_PART_AUTOMAP
 
- VDAMGT_PART_INFO
 
- VDAMGT_PART_MAP
 
- VDAMGT_PART_MERGE
 
- VDAMGT_PART_SPLIT
 
- VDAMGT_PART_UNMAP
 
- VDAMGT_QUICK_RAID
 
- VDAMGT_QUICK_RAID_INIT_AUTOMAP
 
- VDAMGT_SCHEDULE_EVENT
 
- VDAMGT_SCHEDULE_INFO
 
- VDAMGT_SPARE_ADD
 
- VDAMGT_SPARE_LIST
 
- VDAMGT_SPARE_REMOVE
 
- VDAMGT_TEMP_INFO
 
- VDANVCI_NVCACHEMODULE_NOT_PRESENT
 
- VDANVCI_NVCACHEMODULE_PRESENT
 
- VDANVCI_PROTMODE_HI_PERFORM
 
- VDANVCI_PROTMODE_HI_PROTECT
 
- VDANVCI_SUPERCAP_FULLY_CHARGED
 
- VDANVCI_SUPERCAP_NOT_CHARGED
 
- VDANVCI_SUPERCAP_NOT_PRESENT
 
- VDAOPSTAT_FAULTED
 
- VDAOPSTAT_HALTED
 
- VDAOPSTAT_INT
 
- VDAOPSTAT_OK
 
- VDAOP_CONVERSION
 
- VDAOP_ERASE
 
- VDAOP_FULL_INIT
 
- VDAOP_NONE
 
- VDAOP_PATTERN
 
- VDAOP_QUICK_INIT
 
- VDAOP_REBUILD
 
- VDAOP_RECOV_REBUILD
 
- VDAOP_SECT_SCAN
 
- VDAOP_SECT_SCAN_PARITY
 
- VDAOP_SECT_SCAN_PARITY_FIX
 
- VDAPI_FEAT_WRITE_CACHE
 
- VDASESDI_INVALID
 
- VDASI_DAY_NONE
 
- VDASI_EVTTYPE_SECT_SCAN
 
- VDASI_EVTTYPE_SECT_SCAN_PARITY
 
- VDASI_EVTTYPE_SECT_SCAN_PARITY_FIX
 
- VDASI_ID_NONE
 
- VDASI_OP_CANCEL
 
- VDASI_OP_CREATE
 
- VDASI_OP_NONE
 
- VDASI_PROG_NONE
 
- VDASI_RECUR_FOREVER
 
- VDASI_SCHTYPE_DAILY
 
- VDASI_SCHTYPE_ONETIME
 
- VDASI_SCHTYPE_WEEKLY
 
- VDATGTID_INVALID
 
- VDA_ADAP_FEAT_BUZZ_ERR
 
- VDA_ADAP_FEAT_IDENT
 
- VDA_ADAP_FEAT_UTC_TIME
 
- VDA_BUFFER_HEADER_SZ
 
- VDA_CFG_GET_INIT
 
- VDA_CFG_GET_INIT2
 
- VDA_CFG_INIT
 
- VDA_DEVADDRF_SATA
 
- VDA_DEVADDRF_SSD
 
- VDA_DEV_OP_CTRL_CANCEL
 
- VDA_DEV_OP_CTRL_HALT
 
- VDA_DEV_OP_CTRL_RESUME
 
- VDA_DEV_OP_CTRL_START
 
- VDA_DIAG_PAUSE
 
- VDA_DIAG_READ
 
- VDA_DIAG_RESET
 
- VDA_DIAG_RESUME
 
- VDA_DIAG_STATUS
 
- VDA_DIAG_WRITE
 
- VDA_DT_DAY_FRI
 
- VDA_DT_DAY_MASK
 
- VDA_DT_DAY_MON
 
- VDA_DT_DAY_NONE
 
- VDA_DT_DAY_SAT
 
- VDA_DT_DAY_SUN
 
- VDA_DT_DAY_THU
 
- VDA_DT_DAY_TUE
 
- VDA_DT_DAY_WED
 
- VDA_DT_MILITARY
 
- VDA_DT_PM
 
- VDA_FAN_STAT_FAIL
 
- VDA_FAN_STAT_NORMAL
 
- VDA_FAN_STAT_UNKNOWN
 
- VDA_FLASH_BEGINW
 
- VDA_FLASH_CANCEL
 
- VDA_FLASH_COMMIT
 
- VDA_FLASH_FINFO
 
- VDA_FLASH_FREAD
 
- VDA_FLASH_FWRITE
 
- VDA_FLASH_INFO
 
- VDA_FLASH_READ
 
- VDA_FLASH_WRITE
 
- VDA_FUNC_AE
 
- VDA_FUNC_CFG
 
- VDA_FUNC_CLI
 
- VDA_FUNC_DIAG
 
- VDA_FUNC_FLASH
 
- VDA_FUNC_GSV
 
- VDA_FUNC_IOCTL
 
- VDA_FUNC_MGT
 
- VDA_FUNC_SCSI
 
- VDA_GRP_FEAT_BOOT_DEV
 
- VDA_GRP_FEAT_HOTSWAP
 
- VDA_GRP_FEAT_IDENT
 
- VDA_GRP_FEAT_INIT_RESUME
 
- VDA_GRP_FEAT_RBLDPRI_HIGH
 
- VDA_GRP_FEAT_RBLDPRI_LOW
 
- VDA_GRP_FEAT_RBLDPRI_MASK
 
- VDA_GRP_FEAT_RBLDPRI_SAME
 
- VDA_GRP_FEAT_RBLD_RESUME
 
- VDA_GRP_FEAT_SECT_RESUME
 
- VDA_GRP_FEAT_SPDRD_AUTO
 
- VDA_GRP_FEAT_SPDRD_DIS
 
- VDA_GRP_FEAT_SPDRD_ENB
 
- VDA_GRP_FEAT_SPDRD_MASK
 
- VDA_GRP_FEAT_SSD
 
- VDA_GRP_FEAT_WRITE_CACHE
 
- VDA_GRP_OP_CTRL_CANCEL
 
- VDA_GRP_OP_CTRL_HALT
 
- VDA_GRP_OP_CTRL_RESUME
 
- VDA_GRP_OP_CTRL_START
 
- VDA_GRP_STAT_DEGRADED
 
- VDA_GRP_STAT_DELETED
 
- VDA_GRP_STAT_INVALID
 
- VDA_GRP_STAT_NEW
 
- VDA_GRP_STAT_OFFLINE
 
- VDA_GRP_STAT_ONLINE
 
- VDA_GRP_STAT_RECOV_BASIC
 
- VDA_GRP_STAT_RECOV_EXTREME
 
- VDA_GRP_STAT_WAITING
 
- VDA_GRP_TYPE_DVRAID_HS
 
- VDA_GRP_TYPE_DVRAID_NOHS
 
- VDA_GRP_TYPE_JBOD
 
- VDA_GRP_TYPE_RAID0
 
- VDA_GRP_TYPE_RAID1
 
- VDA_GRP_TYPE_RAID10
 
- VDA_GRP_TYPE_RAID4
 
- VDA_GRP_TYPE_RAID40
 
- VDA_GRP_TYPE_RAID5
 
- VDA_GRP_TYPE_RAID50
 
- VDA_GRP_TYPE_RAID6
 
- VDA_GRP_TYPE_RAID60
 
- VDA_GRP_TYPE_SPARE
 
- VDA_IOCTL_CSMI
 
- VDA_IOCTL_HBA
 
- VDA_IOCTL_SMP
 
- VDA_ITF_CONN_CTRL
 
- VDA_ITF_GET_DEV_ADDR
 
- VDA_ITF_GET_DEV_INFO
 
- VDA_ITF_MEM_RW
 
- VDA_ITF_PHY_CTRL
 
- VDA_ITF_SCSI_PASS_THRU
 
- VDA_ITF_TRACE
 
- VDA_MAX_BUFFER_SIZE
 
- VDA_MAX_PARTITIONS
 
- VDA_MAX_RAID_GROUPS
 
- VDA_MEMBER_MISSING
 
- VDA_MEMBER_NEW
 
- VDA_RBLD_CONV
 
- VDA_RBLD_ERASE
 
- VDA_RBLD_FULL_INIT
 
- VDA_RBLD_NONE
 
- VDA_RBLD_PATTERN
 
- VDA_RBLD_QUICK_INIT
 
- VDA_RBLD_REBUILD
 
- VDA_RBLD_RECOV_BASIC
 
- VDA_RBLD_RECOV_EXTREME
 
- VDA_RBLD_RECOV_REBUILD
 
- VDA_RBLD_SECT_SCAN
 
- VDA_RBLD_SECT_SCAN_PARITY
 
- VDA_RBLD_SECT_SCAN_PARITY_FIX
 
- VDA_TEMP_TYPE_CPU
 
- VDB
 
- VDBG
 
- VDBOX_MASK
 
- VDC3
 
- VDC4
 
- VDCBLK_NAME
 
- VDCTRL0_DOTCLK_ACT_FALLING
 
- VDCTRL0_ENABLE_ACT_HIGH
 
- VDCTRL0_ENABLE_PRESENT
 
- VDCTRL0_GET_VSYNC_PULSE_WIDTH
 
- VDCTRL0_HALF_LINE
 
- VDCTRL0_HALF_LINE_MODE
 
- VDCTRL0_HSYNC_ACT_HIGH
 
- VDCTRL0_SET_VSYNC_PULSE_WIDTH
 
- VDCTRL0_VSYNC_ACT_HIGH
 
- VDCTRL0_VSYNC_PERIOD_UNIT
 
- VDCTRL0_VSYNC_PULSE_WIDTH_UNIT
 
- VDCTRL2_GET_HSYNC_PERIOD
 
- VDCTRL2_SET_HSYNC_PERIOD
 
- VDCTRL3_MUX_SYNC_SIGNALS
 
- VDCTRL3_VSYNC_ONLY
 
- VDCTRL4_GET_DOTCLK_DLY
 
- VDCTRL4_SET_DOTCLK_DLY
 
- VDCTRL4_SYNC_SIGNALS_ON
 
- VDC_DEFAULT_BLK_SIZE
 
- VDC_MAX_RETRIES
 
- VDC_TX_RING_SIZE
 
- VDD1_2_MIN_VOLT
 
- VDD1_2_NUM_VOLT_COARSE
 
- VDD1_2_NUM_VOLT_FINE
 
- VDD1_2_OFFSET
 
- VDD1_ILMAX_MASK
 
- VDD1_ILMAX_SHIFT
 
- VDD1_OP_CMD_MASK
 
- VDD1_OP_CMD_SHIFT
 
- VDD1_OP_SEL_MASK
 
- VDD1_OP_SEL_SHIFT
 
- VDD1_SR_SEL_MASK
 
- VDD1_SR_SEL_SHIFT
 
- VDD1_ST_MASK
 
- VDD1_ST_SHIFT
 
- VDD1_TSTEP_MASK
 
- VDD1_TSTEP_SHIFT
 
- VDD1_VGAIN_SEL_MASK
 
- VDD1_VGAIN_SEL_SHIFT
 
- VDD2_ILMAX_MASK
 
- VDD2_ILMAX_SHIFT
 
- VDD2_OP_CMD_MASK
 
- VDD2_OP_CMD_SHIFT
 
- VDD2_OP_SEL_MASK
 
- VDD2_OP_SEL_SHIFT
 
- VDD2_SR_SEL_MASK
 
- VDD2_SR_SEL_SHIFT
 
- VDD2_ST_MASK
 
- VDD2_ST_SHIFT
 
- VDD2_TSTEP_MASK
 
- VDD2_TSTEP_SHIFT
 
- VDD2_VGAIN_SEL_MASK
 
- VDD2_VGAIN_SEL_SHIFT
 
- VDD3P3V_VID_MASK
 
- VDD3_CKINEN_MASK
 
- VDD3_CKINEN_SHIFT
 
- VDD3_ST_MASK
 
- VDD3_ST_SHIFT
 
- VDDA
 
- VDDA_PHY_MAX_UV
 
- VDDA_PHY_MIN_UV
 
- VDDA_PLL_MAX_UV
 
- VDDA_PLL_MIN_UV
 
- VDDA_UA_OFF_LOAD
 
- VDDA_UA_ON_LOAD
 
- VDDC3D_TURNOFF_D1
 
- VDDC3D_TURNOFF_D2
 
- VDDC3D_TURNOFF_D3
 
- VDDCI_MASK
 
- VDDCI_ON_SVI2
 
- VDDCI_SHIFT
 
- VDDCTRL_MIN_VOLT
 
- VDDCTRL_OFFSET
 
- VDDCTRL_OP_CMD_MASK
 
- VDDCTRL_OP_CMD_SHIFT
 
- VDDCTRL_OP_SEL_MASK
 
- VDDCTRL_OP_SEL_SHIFT
 
- VDDCTRL_SR_SEL_MASK
 
- VDDCTRL_SR_SEL_SHIFT
 
- VDDCTRL_ST_MASK
 
- VDDCTRL_ST_SHIFT
 
- VDDC_MASK
 
- VDDC_ON_SVI2
 
- VDDC_PCC_GPIO_PINID
 
- VDDC_SHIFT
 
- VDDC_VDDCI_DELTA
 
- VDDC_VRHOT_GPIO_PINID
 
- VDDD
 
- VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT_MASK
 
- VDDGFX_IDLE_CONTROL__FORCE_VDDGFX_IDLE_EXIT__SHIFT
 
- VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE_MASK
 
- VDDGFX_IDLE_CONTROL__SMC_VDDGFX_IDLE_STATE__SHIFT
 
- VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT_MASK
 
- VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_DETECT__SHIFT
 
- VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN_MASK
 
- VDDGFX_IDLE_CONTROL__VDDGFX_IDLE_EN__SHIFT
 
- VDDGFX_IDLE_EXIT__BIF_EXIT_REQ_MASK
 
- VDDGFX_IDLE_EXIT__BIF_EXIT_REQ__SHIFT
 
- VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_MASK
 
- VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT_MASK
 
- VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD_UNIT__SHIFT
 
- VDDGFX_IDLE_PARAMETER__VDDGFX_IDLE_THRESHOLD__SHIFT
 
- VDDGFX_MASK
 
- VDDIO
 
- VDDP_REF_CLK_MAX_UV
 
- VDDP_REF_CLK_MIN_UV
 
- VDD_CLAMP
 
- VDD_FROM_REG
 
- VDD_HIGH_SEL
 
- VDD_LOW_SEL
 
- VDD_OVERRIDE_FORCE
 
- VDD_SC1_ARRAY_CLAMP_GFS_CTL
 
- VDD_TO_REG
 
- VDE
 
- VDEB
 
- VDEBUG
 
- VDECCLK_GATE_D
 
- VDEC_A
 
- VDEC_AD
 
- VDEC_ASSIST_AMR1_INT8
 
- VDEC_AV
 
- VDEC_A_BRITE_CTRL
 
- VDEC_A_CNTRST_CTRL
 
- VDEC_A_HUE_CTRL
 
- VDEC_A_PEAK_SEL
 
- VDEC_A_USAT_CTRL
 
- VDEC_A_VSAT_CTRL
 
- VDEC_B
 
- VDEC_B_BP_MISC_CTRL
 
- VDEC_B_CHROMA_CTRL
 
- VDEC_B_COMB_2D_BLEND
 
- VDEC_B_COMB_2D_HFD_CFG
 
- VDEC_B_COMB_2D_HFS_CFG
 
- VDEC_B_COMB_2D_LF_CFG
 
- VDEC_B_COMB_FLAT_NOISE_CTRL
 
- VDEC_B_COMB_FLAT_THRESH_CTRL
 
- VDEC_B_COMB_MISC_CTRL
 
- VDEC_B_COMB_TEST
 
- VDEC_B_CRUSH_CTRL
 
- VDEC_B_DFE_CTRL1
 
- VDEC_B_DFE_CTRL2
 
- VDEC_B_DFE_CTRL3
 
- VDEC_B_FIELD_COUNT
 
- VDEC_B_GEN_STAT
 
- VDEC_B_HORIZ_TIM_CTRL
 
- VDEC_B_HSCALE_CTRL
 
- VDEC_B_HTL_CTRL
 
- VDEC_B_INT_STAT_MASK
 
- VDEC_B_LUMA_CTRL
 
- VDEC_B_MAN_AGC_CTRL
 
- VDEC_B_MAN_VGA_CTRL
 
- VDEC_B_MISC_TIM_CTRL
 
- VDEC_B_MODE_CTRL
 
- VDEC_B_NOISE_DET_CTRL
 
- VDEC_B_OUT_CTRL1
 
- VDEC_B_OUT_CTRL_NS
 
- VDEC_B_PLL_CTRL
 
- VDEC_B_PLL_CTRL_FAST
 
- VDEC_B_SC_CONVERGE_CTRL
 
- VDEC_B_SC_LOOP_CTRL
 
- VDEC_B_SC_STEP_SIZE
 
- VDEC_B_SOFT_RST_CTRL
 
- VDEC_B_SRC_CFG
 
- VDEC_B_VCR_DET_CTRL
 
- VDEC_B_VERSION
 
- VDEC_B_VERT_TIM_CTRL
 
- VDEC_B_VSCALE_CTRL
 
- VDEC_C
 
- VDEC_CM
 
- VDEC_C_BP_MISC_CTRL
 
- VDEC_C_CHROMA_CTRL
 
- VDEC_C_COMB_2D_BLEND
 
- VDEC_C_COMB_2D_HFD_CFG
 
- VDEC_C_COMB_2D_HFS_CFG
 
- VDEC_C_COMB_2D_LF_CFG
 
- VDEC_C_COMB_FLAT_NOISE_CTRL
 
- VDEC_C_COMB_FLAT_THRESH_CTRL
 
- VDEC_C_COMB_MISC_CTRL
 
- VDEC_C_COMB_TEST
 
- VDEC_C_CRUSH_CTRL
 
- VDEC_C_DFE_CTRL1
 
- VDEC_C_DFE_CTRL2
 
- VDEC_C_DFE_CTRL3
 
- VDEC_C_FIELD_COUNT
 
- VDEC_C_GEN_STAT
 
- VDEC_C_HORIZ_TIM_CTRL
 
- VDEC_C_HSCALE_CTRL
 
- VDEC_C_HTL_CTRL
 
- VDEC_C_INT_STAT_MASK
 
- VDEC_C_LUMA_CTRL
 
- VDEC_C_MAN_AGC_CTRL
 
- VDEC_C_MAN_VGA_CTRL
 
- VDEC_C_MISC_TIM_CTRL
 
- VDEC_C_MODE_CTRL
 
- VDEC_C_NOISE_DET_CTRL
 
- VDEC_C_OUT_CTRL1
 
- VDEC_C_OUT_CTRL_NS
 
- VDEC_C_PLL_CTRL
 
- VDEC_C_PLL_CTRL_FAST
 
- VDEC_C_SC_CONVERGE_CTRL
 
- VDEC_C_SC_LOOP_CTRL
 
- VDEC_C_SC_STEP_SIZE
 
- VDEC_C_SOFT_RST_CTRL
 
- VDEC_C_SRC_CFG
 
- VDEC_C_VCR_DET_CTRL
 
- VDEC_C_VERSION
 
- VDEC_C_VERT_TIM_CTRL
 
- VDEC_C_VSCALE_CTRL
 
- VDEC_D
 
- VDEC_D_BP_MISC_CTRL
 
- VDEC_D_CHROMA_CTRL
 
- VDEC_D_COMB_2D_BLEND
 
- VDEC_D_COMB_2D_HFD_CFG
 
- VDEC_D_COMB_2D_HFS_CFG
 
- VDEC_D_COMB_2D_LF_CFG
 
- VDEC_D_COMB_FLAT_NOISE_CTRL
 
- VDEC_D_COMB_FLAT_THRESH_CTRL
 
- VDEC_D_COMB_MISC_CTRL
 
- VDEC_D_COMB_TEST
 
- VDEC_D_CRUSH_CTRL
 
- VDEC_D_DFE_CTRL1
 
- VDEC_D_DFE_CTRL2
 
- VDEC_D_DFE_CTRL3
 
- VDEC_D_FIELD_COUNT
 
- VDEC_D_GEN_STAT
 
- VDEC_D_HORIZ_TIM_CTRL
 
- VDEC_D_HSCALE_CTRL
 
- VDEC_D_HTL_CTRL
 
- VDEC_D_INT_STAT_MASK
 
- VDEC_D_LUMA_CTRL
 
- VDEC_D_MAN_AGC_CTRL
 
- VDEC_D_MAN_VGA_CTRL
 
- VDEC_D_MISC_TIM_CTRL
 
- VDEC_D_MODE_CTRL
 
- VDEC_D_NOISE_DET_CTRL
 
- VDEC_D_OUT_CTRL1
 
- VDEC_D_OUT_CTRL_NS
 
- VDEC_D_PLL_CTRL
 
- VDEC_D_PLL_CTRL_FAST
 
- VDEC_D_SC_CONVERGE_CTRL
 
- VDEC_D_SC_LOOP_CTRL
 
- VDEC_D_SC_STEP_SIZE
 
- VDEC_D_SOFT_RST_CTRL
 
- VDEC_D_SRC_CFG
 
- VDEC_D_VCR_DET_CTRL
 
- VDEC_D_VERSION
 
- VDEC_D_VERT_TIM_CTRL
 
- VDEC_D_VSCALE_CTRL
 
- VDEC_E
 
- VDEC_E_BP_MISC_CTRL
 
- VDEC_E_CHROMA_CTRL
 
- VDEC_E_COMB_2D_BLEND
 
- VDEC_E_COMB_2D_HFD_CFG
 
- VDEC_E_COMB_2D_HFS_CFG
 
- VDEC_E_COMB_2D_LF_CFG
 
- VDEC_E_COMB_FLAT_NOISE_CTRL
 
- VDEC_E_COMB_FLAT_THRESH_CTRL
 
- VDEC_E_COMB_MISC_CTRL
 
- VDEC_E_COMB_TEST
 
- VDEC_E_CRUSH_CTRL
 
- VDEC_E_DFE_CTRL1
 
- VDEC_E_DFE_CTRL2
 
- VDEC_E_DFE_CTRL3
 
- VDEC_E_FIELD_COUNT
 
- VDEC_E_GEN_STAT
 
- VDEC_E_HORIZ_TIM_CTRL
 
- VDEC_E_HSCALE_CTRL
 
- VDEC_E_HTL_CTRL
 
- VDEC_E_INT_STAT_MASK
 
- VDEC_E_LUMA_CTRL
 
- VDEC_E_MAN_AGC_CTRL
 
- VDEC_E_MAN_VGA_CTRL
 
- VDEC_E_MISC_TIM_CTRL
 
- VDEC_E_MODE_CTRL
 
- VDEC_E_NOISE_DET_CTRL
 
- VDEC_E_OUT_CTRL1
 
- VDEC_E_OUT_CTRL_NS
 
- VDEC_E_PLL_CTRL
 
- VDEC_E_PLL_CTRL_FAST
 
- VDEC_E_SC_CONVERGE_CTRL
 
- VDEC_E_SC_LOOP_CTRL
 
- VDEC_E_SC_STEP_SIZE
 
- VDEC_E_SOFT_RST_CTRL
 
- VDEC_E_SRC_CFG
 
- VDEC_E_VCR_DET_CTRL
 
- VDEC_E_VERSION
 
- VDEC_E_VERT_TIM_CTRL
 
- VDEC_E_VSCALE_CTRL
 
- VDEC_F
 
- VDEC_F_BP_MISC_CTRL
 
- VDEC_F_CHROMA_CTRL
 
- VDEC_F_COMB_2D_BLEND
 
- VDEC_F_COMB_2D_HFD_CFG
 
- VDEC_F_COMB_2D_HFS_CFG
 
- VDEC_F_COMB_2D_LF_CFG
 
- VDEC_F_COMB_FLAT_NOISE_CTRL
 
- VDEC_F_COMB_FLAT_THRESH_CTRL
 
- VDEC_F_COMB_MISC_CTRL
 
- VDEC_F_COMB_TEST
 
- VDEC_F_CRUSH_CTRL
 
- VDEC_F_DFE_CTRL1
 
- VDEC_F_DFE_CTRL2
 
- VDEC_F_DFE_CTRL3
 
- VDEC_F_FIELD_COUNT
 
- VDEC_F_GEN_STAT
 
- VDEC_F_HORIZ_TIM_CTRL
 
- VDEC_F_HSCALE_CTRL
 
- VDEC_F_HTL_CTRL
 
- VDEC_F_INT_STAT_MASK
 
- VDEC_F_LUMA_CTRL
 
- VDEC_F_MAN_AGC_CTRL
 
- VDEC_F_MAN_VGA_CTRL
 
- VDEC_F_MISC_TIM_CTRL
 
- VDEC_F_MODE_CTRL
 
- VDEC_F_NOISE_DET_CTRL
 
- VDEC_F_OUT_CTRL1
 
- VDEC_F_OUT_CTRL_NS
 
- VDEC_F_PLL_CTRL
 
- VDEC_F_PLL_CTRL_FAST
 
- VDEC_F_SC_CONVERGE_CTRL
 
- VDEC_F_SC_LOOP_CTRL
 
- VDEC_F_SC_STEP_SIZE
 
- VDEC_F_SOFT_RST_CTRL
 
- VDEC_F_SRC_CFG
 
- VDEC_F_VCR_DET_CTRL
 
- VDEC_F_VERSION
 
- VDEC_F_VERT_TIM_CTRL
 
- VDEC_F_VSCALE_CTRL
 
- VDEC_G
 
- VDEC_G_BP_MISC_CTRL
 
- VDEC_G_CHROMA_CTRL
 
- VDEC_G_COMB_2D_BLEND
 
- VDEC_G_COMB_2D_HFD_CFG
 
- VDEC_G_COMB_2D_HFS_CFG
 
- VDEC_G_COMB_2D_LF_CFG
 
- VDEC_G_COMB_FLAT_NOISE_CTRL
 
- VDEC_G_COMB_FLAT_THRESH_CTRL
 
- VDEC_G_COMB_MISC_CTRL
 
- VDEC_G_COMB_TEST
 
- VDEC_G_CRUSH_CTRL
 
- VDEC_G_DFE_CTRL1
 
- VDEC_G_DFE_CTRL2
 
- VDEC_G_DFE_CTRL3
 
- VDEC_G_FIELD_COUNT
 
- VDEC_G_GEN_STAT
 
- VDEC_G_HORIZ_TIM_CTRL
 
- VDEC_G_HSCALE_CTRL
 
- VDEC_G_HTL_CTRL
 
- VDEC_G_INT_STAT_MASK
 
- VDEC_G_LUMA_CTRL
 
- VDEC_G_MAN_AGC_CTRL
 
- VDEC_G_MAN_VGA_CTRL
 
- VDEC_G_MISC_TIM_CTRL
 
- VDEC_G_MODE_CTRL
 
- VDEC_G_NOISE_DET_CTRL
 
- VDEC_G_OUT_CTRL1
 
- VDEC_G_OUT_CTRL_NS
 
- VDEC_G_PLL_CTRL
 
- VDEC_G_PLL_CTRL_FAST
 
- VDEC_G_SC_CONVERGE_CTRL
 
- VDEC_G_SC_LOOP_CTRL
 
- VDEC_G_SC_STEP_SIZE
 
- VDEC_G_SOFT_RST_CTRL
 
- VDEC_G_SRC_CFG
 
- VDEC_G_VCR_DET_CTRL
 
- VDEC_G_VERSION
 
- VDEC_G_VERT_TIM_CTRL
 
- VDEC_G_VSCALE_CTRL
 
- VDEC_H
 
- VDEC_HWB
 
- VDEC_HWD
 
- VDEC_HWG
 
- VDEC_HWQ
 
- VDEC_HW_ACTIVE
 
- VDEC_H_BP_MISC_CTRL
 
- VDEC_H_CHROMA_CTRL
 
- VDEC_H_COMB_2D_BLEND
 
- VDEC_H_COMB_2D_HFD_CFG
 
- VDEC_H_COMB_2D_HFS_CFG
 
- VDEC_H_COMB_2D_LF_CFG
 
- VDEC_H_COMB_FLAT_NOISE_CTRL
 
- VDEC_H_COMB_FLAT_THRESH_CTRL
 
- VDEC_H_COMB_MISC_CTRL
 
- VDEC_H_COMB_TEST
 
- VDEC_H_CRUSH_CTRL
 
- VDEC_H_DFE_CTRL1
 
- VDEC_H_DFE_CTRL2
 
- VDEC_H_DFE_CTRL3
 
- VDEC_H_FIELD_COUNT
 
- VDEC_H_GEN_STAT
 
- VDEC_H_HORIZ_TIM_CTRL
 
- VDEC_H_HSCALE_CTRL
 
- VDEC_H_HTL_CTRL
 
- VDEC_H_INT_STAT_MASK
 
- VDEC_H_LUMA_CTRL
 
- VDEC_H_MAN_AGC_CTRL
 
- VDEC_H_MAN_VGA_CTRL
 
- VDEC_H_MISC_TIM_CTRL
 
- VDEC_H_MODE_CTRL
 
- VDEC_H_NOISE_DET_CTRL
 
- VDEC_H_OUT_CTRL1
 
- VDEC_H_OUT_CTRL_NS
 
- VDEC_H_PLL_CTRL
 
- VDEC_H_PLL_CTRL_FAST
 
- VDEC_H_SC_CONVERGE_CTRL
 
- VDEC_H_SC_LOOP_CTRL
 
- VDEC_H_SC_STEP_SIZE
 
- VDEC_H_SOFT_RST_CTRL
 
- VDEC_H_SRC_CFG
 
- VDEC_H_VCR_DET_CTRL
 
- VDEC_H_VERSION
 
- VDEC_H_VERT_TIM_CTRL
 
- VDEC_H_VSCALE_CTRL
 
- VDEC_IRQ_CFG
 
- VDEC_IRQ_CFG_REG
 
- VDEC_IRQ_CLR
 
- VDEC_LD
 
- VDEC_MISC
 
- VDEC_PP
 
- VDEC_REVISION_GXBB
 
- VDEC_REVISION_GXL
 
- VDEC_REVISION_GXM
 
- VDEC_SYS
 
- VDEC_TOP
 
- VDELAY_LO
 
- VDER
 
- VDEVICE
 
- VDEV_CONSOLE_CON
 
- VDEV_DEFAULT_STATS_UPDATE_PERIOD
 
- VDEV_DISK
 
- VDEV_DISK_SERVER
 
- VDEV_EVENT_DOWN
 
- VDEV_EVENT_ERROR_MALLOC
 
- VDEV_EVENT_ERROR_TCP
 
- VDEV_EVENT_REMOVED
 
- VDEV_IS_EXTENDED
 
- VDEV_NETWORK
 
- VDEV_NETWORK_SWITCH
 
- VDEV_PORT_ERROR
 
- VDEV_ST_ERROR
 
- VDEV_ST_NOTASSIGNED
 
- VDEV_ST_NULL
 
- VDEV_ST_USED
 
- VDEV_SUBTYPE_BT
 
- VDEV_SUBTYPE_P2PCLI
 
- VDEV_SUBTYPE_P2PDEV
 
- VDEV_SUBTYPE_P2PGO
 
- VDE_ACLK
 
- VDE_INTERRUPT
 
- VDE_IO
 
- VDE_IOCTL_BASE
 
- VDE_IOR
 
- VDE_IOW
 
- VDE_IOWR
 
- VDE_I_C0AV
 
- VDE_I_C0AVEN
 
- VDE_I_C0VBI
 
- VDE_I_C0VBIEN
 
- VDE_I_C1AV
 
- VDE_I_C1AVEN
 
- VDE_I_C1VBI
 
- VDE_I_C1VBIEN
 
- VDE_I_DMA0DDEN
 
- VDE_I_DMA0DDONE
 
- VDE_I_DMA0TDEN
 
- VDE_I_DMA0TDONE
 
- VDE_I_DMA1DDEN
 
- VDE_I_DMA1DDONE
 
- VDE_I_DMA1TDEN
 
- VDE_I_DMA1TDONE
 
- VDE_I_DVISENSE
 
- VDE_I_DVISNSEN
 
- VDE_I_ENABLE
 
- VDE_I_HQV0
 
- VDE_I_HQV0EN
 
- VDE_I_HQV1
 
- VDE_I_HQV1EN
 
- VDE_I_LVDSSI
 
- VDE_I_LVDSSIEN
 
- VDE_I_MCCFI
 
- VDE_I_MCCFIEN
 
- VDE_I_VBLANK
 
- VDE_I_VSYNC
 
- VDE_I_VSYNC2
 
- VDE_I_VSYNC2EN
 
- VDE_I_VSYNCEN
 
- VDFSATLV
 
- VDIC_NUM_PADS
 
- VDIC_SINK_PAD_DIRECT
 
- VDIC_SINK_PAD_IDMAC
 
- VDIC_SRC_PAD_DIRECT
 
- VDIG1_SEL_MASK
 
- VDIG1_SEL_SHIFT
 
- VDIG1_ST_MASK
 
- VDIG1_ST_SHIFT
 
- VDIG2_SEL_MASK
 
- VDIG2_SEL_SHIFT
 
- VDIG2_ST_MASK
 
- VDIG2_ST_SHIFT
 
- VDINT0
 
- VDINT1
 
- VDINT2
 
- VDIP_ENABLE_PPS
 
- VDISCARD
 
- VDISKFULL
 
- VDISK_CDROM
 
- VDISK_MGMT_ACQUIRE
 
- VDISK_MGMT_RELEASE
 
- VDISK_READONLY
 
- VDISK_REMOVABLE
 
- VDISPLAY_REG
 
- VDISPR
 
- VDI_C
 
- VDI_C_BURST_SIZE1_4
 
- VDI_C_BURST_SIZE1_OFFSET
 
- VDI_C_BURST_SIZE2_4
 
- VDI_C_BURST_SIZE2_OFFSET
 
- VDI_C_BURST_SIZE3_4
 
- VDI_C_BURST_SIZE3_OFFSET
 
- VDI_C_BURST_SIZE_MASK
 
- VDI_C_CH_420
 
- VDI_C_CH_422
 
- VDI_C_MOT_SEL_FULL
 
- VDI_C_MOT_SEL_LOW
 
- VDI_C_MOT_SEL_MASK
 
- VDI_C_MOT_SEL_MED
 
- VDI_C_TOP_FIELD_AUTO_1
 
- VDI_C_TOP_FIELD_MAN_1
 
- VDI_C_VWM1_CLR_2
 
- VDI_C_VWM1_SET_1
 
- VDI_C_VWM1_SET_2
 
- VDI_C_VWM3_CLR_2
 
- VDI_C_VWM3_SET_1
 
- VDI_C_VWM3_SET_2
 
- VDI_FSIZE
 
- VDMA_ALIGNMENT
 
- VDMA_B_ADDR
 
- VDMA_CHANNEL_CONFIG
 
- VDMA_CSR0
 
- VDMA_C_ABORT
 
- VDMA_C_DONE
 
- VDMA_C_ENABLE
 
- VDMA_C_START
 
- VDMA_DAR0
 
- VDMA_DPRH0
 
- VDMA_DPRL0
 
- VDMA_DPR_IN
 
- VDMA_DQWCR0
 
- VDMA_END
 
- VDMA_F2_B_ADDR
 
- VDMA_F2_P_ADDR
 
- VDMA_F2_WHP
 
- VDMA_INIT
 
- VDMA_MARH0
 
- VDMA_MARL0
 
- VDMA_MR0
 
- VDMA_MR_CHAIN
 
- VDMA_MR_TDIE
 
- VDMA_OFFSET
 
- VDMA_PAGE
 
- VDMA_PAGESIZE
 
- VDMA_PAGE_EMPTY
 
- VDMA_PGTBL_ENTRIES
 
- VDMA_PGTBL_ENTRY
 
- VDMA_PGTBL_SIZE
 
- VDMA_PMR0
 
- VDMA_P_ADDR
 
- VDMA_START
 
- VDMA_TMR0
 
- VDMA_WHP
 
- VDMA_XFERSIZE
 
- VDMD_BACK
 
- VDMD_FRONT
 
- VDMD_MASK
 
- VDMD_STREAM
 
- VDM_STATE_BUSY
 
- VDM_STATE_DONE
 
- VDM_STATE_ERR_BUSY
 
- VDM_STATE_ERR_SEND
 
- VDM_STATE_ERR_TMOUT
 
- VDM_STATE_READY
 
- VDM_STATE_WAIT_RSP_BUSY
 
- VDNAMESIZE
 
- VDO
 
- VDOA1_VID_MASK
 
- VDOA23_VID_MASK
 
- VDOAC
 
- VDOAC_BAND_HEIGHT_16
 
- VDOAC_BAND_HEIGHT_32
 
- VDOAC_BAND_HEIGHT_8
 
- VDOAC_BNDM_MASK
 
- VDOAC_ISEL
 
- VDOAC_NF
 
- VDOAC_PFS
 
- VDOAC_SO
 
- VDOAC_SYNC
 
- VDOAFP
 
- VDOAFP_FH_MASK
 
- VDOAFP_FW_MASK
 
- VDOAIE
 
- VDOAIEBA00
 
- VDOAIEBA01
 
- VDOAIEBA02
 
- VDOAIEBA10
 
- VDOAIEBA11
 
- VDOAIEBA12
 
- VDOAIE_EIEOT
 
- VDOAIE_EITERR
 
- VDOAIST
 
- VDOAIST_EOT
 
- VDOAIST_TERR
 
- VDOAIUBO
 
- VDOASL
 
- VDOASL_ISLY_MASK
 
- VDOASL_VSLY_MASK
 
- VDOASR
 
- VDOASRR
 
- VDOASRR_START
 
- VDOASRR_SWRST
 
- VDOASR_CURRENT_BUFFER
 
- VDOASR_CURRENT_FRAME
 
- VDOASR_EOB
 
- VDOASR_ERRW
 
- VDOAVEBA0
 
- VDOAVEBA1
 
- VDOAVEBA2
 
- VDOAVUBO
 
- VDOA_NAME
 
- VDOUBLESCAN
 
- VDO_AMA
 
- VDO_CABLE
 
- VDO_CMDT
 
- VDO_CMDT_MASK
 
- VDO_CMD_CCD_EN
 
- VDO_CMD_CURRENT
 
- VDO_CMD_ERASE_SIG
 
- VDO_CMD_FLASH_ERASE
 
- VDO_CMD_FLASH_WRITE
 
- VDO_CMD_FLIP
 
- VDO_CMD_GET_LOG
 
- VDO_CMD_PING_ENABLE
 
- VDO_CMD_READ_INFO
 
- VDO_CMD_REBOOT
 
- VDO_CMD_SEND_INFO
 
- VDO_CMD_VENDOR
 
- VDO_CMD_VERSION
 
- VDO_CTL1_REG
 
- VDO_CTL2_REG
 
- VDO_CTL_REG
 
- VDO_IDH
 
- VDO_INDEX_AMA
 
- VDO_INDEX_CABLE
 
- VDO_INDEX_CSTAT
 
- VDO_INDEX_HDR
 
- VDO_INDEX_IDH
 
- VDO_INDEX_PRODUCT
 
- VDO_MAX_OBJECTS
 
- VDO_MAX_SIZE
 
- VDO_OPOS
 
- VDO_OPOS_MASK
 
- VDO_PRODUCT
 
- VDO_SRC_INITIATOR
 
- VDO_SRC_RESPONDER
 
- VDO_SVDM_TYPE
 
- VDO_SVDM_VERS
 
- VDO_SVID
 
- VDPU_REG_ADDITIONAL_CHROMA_ADDRESS
 
- VDPU_REG_ADDR_DST
 
- VDPU_REG_ADDR_QTABLE
 
- VDPU_REG_ADDR_REF_FIELD_E
 
- VDPU_REG_ADDR_REF_TOPC_E
 
- VDPU_REG_ADDR_STR
 
- VDPU_REG_AHB_HLOCK_E
 
- VDPU_REG_ALT_SCAN_E
 
- VDPU_REG_ALT_SCAN_FLAG_E
 
- VDPU_REG_APF_THRESHOLD
 
- VDPU_REG_AXI_CTRL
 
- VDPU_REG_AXI_DEC_SEL
 
- VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F0
 
- VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F1
 
- VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F2
 
- VDPU_REG_BD_P_REF_PIC_PINIT_RLIST_F3
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_B0
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_B1
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_B10
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_B11
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_B12
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_B13
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_B14
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_B15
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_B2
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_B3
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_B4
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_B5
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_B6
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_B7
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_B8
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_B9
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_F0
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_F1
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_F10
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_F11
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_F12
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_F13
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_F14
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_F15
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_F2
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_F3
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_F4
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_F5
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_F6
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_F7
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_F8
 
- VDPU_REG_BD_REF_PIC_BINIT_RLIST_F9
 
- VDPU_REG_BD_REF_PIC_PRED_TAP_2_4
 
- VDPU_REG_BD_REF_PIC_PRED_TAP_2_M1
 
- VDPU_REG_BD_REF_PIC_PRED_TAP_4_4
 
- VDPU_REG_BD_REF_PIC_PRED_TAP_4_M1
 
- VDPU_REG_BD_REF_PIC_PRED_TAP_6_4
 
- VDPU_REG_BD_REF_PIC_PRED_TAP_6_M1
 
- VDPU_REG_CACHE_E
 
- VDPU_REG_CONFIG_DEC_ADV_PRE_DIS
 
- VDPU_REG_CONFIG_DEC_AXI_RD_ID
 
- VDPU_REG_CONFIG_DEC_CLK_GATE_E
 
- VDPU_REG_CONFIG_DEC_DATA_DISC_E
 
- VDPU_REG_CONFIG_DEC_INSWAP32_E
 
- VDPU_REG_CONFIG_DEC_IN_ENDIAN
 
- VDPU_REG_CONFIG_DEC_LATENCY
 
- VDPU_REG_CONFIG_DEC_MAX_BURST
 
- VDPU_REG_CONFIG_DEC_OUTSWAP32_E
 
- VDPU_REG_CONFIG_DEC_OUT_ENDIAN
 
- VDPU_REG_CONFIG_DEC_OUT_TILED_E
 
- VDPU_REG_CONFIG_DEC_SCMD_DIS
 
- VDPU_REG_CONFIG_DEC_STRENDIAN_E
 
- VDPU_REG_CONFIG_DEC_STRSWAP32_E
 
- VDPU_REG_CONFIG_DEC_TIMEOUT_E
 
- VDPU_REG_CONFIG_TILED_MODE_LSB
 
- VDPU_REG_CONFIG_TILED_MODE_MSB
 
- VDPU_REG_CON_MV_E
 
- VDPU_REG_CURRENT_FRAME
 
- VDPU_REG_DATA_ENDIAN
 
- VDPU_REG_DEC_ADV_PRE_DIS
 
- VDPU_REG_DEC_AXI_RD_ID
 
- VDPU_REG_DEC_AXI_WR_ID
 
- VDPU_REG_DEC_CLK_GATE_E
 
- VDPU_REG_DEC_CTRL0
 
- VDPU_REG_DEC_CTRL0_DEC_AXI_WR_ID
 
- VDPU_REG_DEC_CTRL0_DEC_MODE
 
- VDPU_REG_DEC_CTRL0_DEC_OUT_DIS
 
- VDPU_REG_DEC_CTRL0_DIVX3_E
 
- VDPU_REG_DEC_CTRL0_FILTERING_DIS
 
- VDPU_REG_DEC_CTRL0_FWD_INTERLACE_E
 
- VDPU_REG_DEC_CTRL0_PICORD_COUNT_E
 
- VDPU_REG_DEC_CTRL0_PIC_B_E
 
- VDPU_REG_DEC_CTRL0_PIC_FIELDMODE_E
 
- VDPU_REG_DEC_CTRL0_PIC_FIXED_QUANT
 
- VDPU_REG_DEC_CTRL0_PIC_INTERLACE_E
 
- VDPU_REG_DEC_CTRL0_PIC_INTER_E
 
- VDPU_REG_DEC_CTRL0_PIC_TOPFIELD_E
 
- VDPU_REG_DEC_CTRL0_PJPEG_E
 
- VDPU_REG_DEC_CTRL0_REFTOPFIRST_E
 
- VDPU_REG_DEC_CTRL0_REF_TOPFIELD_E
 
- VDPU_REG_DEC_CTRL0_RLC_MODE_E
 
- VDPU_REG_DEC_CTRL0_SEQ_MBAFF_E
 
- VDPU_REG_DEC_CTRL0_SKIP_MODE
 
- VDPU_REG_DEC_CTRL0_SORENSON_E
 
- VDPU_REG_DEC_CTRL0_WRITE_MVS_E
 
- VDPU_REG_DEC_CTRL1_PIC_MB_HEIGHT_P
 
- VDPU_REG_DEC_CTRL1_PIC_MB_H_EXT
 
- VDPU_REG_DEC_CTRL1_PIC_MB_WIDTH
 
- VDPU_REG_DEC_CTRL1_PIC_MB_W_EXT
 
- VDPU_REG_DEC_CTRL1_REF_FRAMES
 
- VDPU_REG_DEC_CTRL2_BOOLEAN_RANGE
 
- VDPU_REG_DEC_CTRL2_BOOLEAN_VALUE
 
- VDPU_REG_DEC_CTRL2_CH_QP_OFFSET
 
- VDPU_REG_DEC_CTRL2_CH_QP_OFFSET2
 
- VDPU_REG_DEC_CTRL2_FIELDPIC_FLAG_E
 
- VDPU_REG_DEC_CTRL2_STRM1_START_BIT
 
- VDPU_REG_DEC_CTRL2_STRM_START_BIT
 
- VDPU_REG_DEC_CTRL2_TYPE1_QUANT_E
 
- VDPU_REG_DEC_CTRL3_CH_8PIX_ILEAV_E
 
- VDPU_REG_DEC_CTRL3_INIT_QP
 
- VDPU_REG_DEC_CTRL3_START_CODE_E
 
- VDPU_REG_DEC_CTRL3_STREAM_LEN
 
- VDPU_REG_DEC_CTRL4_BILIN_MC_E
 
- VDPU_REG_DEC_CTRL4_BLACKWHITE_E
 
- VDPU_REG_DEC_CTRL4_CABAC_E
 
- VDPU_REG_DEC_CTRL4_DCT1_START_BIT
 
- VDPU_REG_DEC_CTRL4_DCT2_START_BIT
 
- VDPU_REG_DEC_CTRL4_DIR_8X8_INFER_E
 
- VDPU_REG_DEC_CTRL4_FRAMENUM
 
- VDPU_REG_DEC_CTRL4_FRAMENUM_LEN
 
- VDPU_REG_DEC_CTRL4_VC1_HEIGHT_EXT
 
- VDPU_REG_DEC_CTRL4_WEIGHT_BIPR_IDC
 
- VDPU_REG_DEC_CTRL4_WEIGHT_PRED_E
 
- VDPU_REG_DEC_CTRL5_8X8TRANS_FLAG_E
 
- VDPU_REG_DEC_CTRL5_CONST_INTRA_E
 
- VDPU_REG_DEC_CTRL5_FILT_CTRL_PRES
 
- VDPU_REG_DEC_CTRL5_IDR_PIC_E
 
- VDPU_REG_DEC_CTRL5_IDR_PIC_ID
 
- VDPU_REG_DEC_CTRL5_RDPIC_CNT_PRES
 
- VDPU_REG_DEC_CTRL5_REFPIC_MK_LEN
 
- VDPU_REG_DEC_CTRL6
 
- VDPU_REG_DEC_CTRL6_COEFFS_PART_AM
 
- VDPU_REG_DEC_CTRL6_POC_LENGTH
 
- VDPU_REG_DEC_CTRL6_PPS_ID
 
- VDPU_REG_DEC_CTRL6_REFIDX0_ACTIVE
 
- VDPU_REG_DEC_CTRL6_REFIDX1_ACTIVE
 
- VDPU_REG_DEC_CTRL6_STREAM1_LEN
 
- VDPU_REG_DEC_CTRL7_DCT3_START_BIT
 
- VDPU_REG_DEC_CTRL7_DCT4_START_BIT
 
- VDPU_REG_DEC_CTRL7_DCT5_START_BIT
 
- VDPU_REG_DEC_CTRL7_DCT6_START_BIT
 
- VDPU_REG_DEC_CTRL7_DCT7_START_BIT
 
- VDPU_REG_DEC_DATA_DISC_E
 
- VDPU_REG_DEC_E
 
- VDPU_REG_DEC_FORMAT
 
- VDPU_REG_DEC_INSWAP32_E
 
- VDPU_REG_DEC_IN_ENDIAN
 
- VDPU_REG_DEC_LATENCY
 
- VDPU_REG_DEC_MAX_BURST
 
- VDPU_REG_DEC_MB_HEIGHT_OFF
 
- VDPU_REG_DEC_MB_WIDTH_OFF
 
- VDPU_REG_DEC_MODE
 
- VDPU_REG_DEC_OUTSWAP32_E
 
- VDPU_REG_DEC_OUT_BASE
 
- VDPU_REG_DEC_OUT_ENDIAN
 
- VDPU_REG_DEC_PIC_MB_HEIGHT_P
 
- VDPU_REG_DEC_PIC_MB_WIDTH
 
- VDPU_REG_DEC_SCMD_DIS
 
- VDPU_REG_DEC_STREAM_LEN_HI
 
- VDPU_REG_DEC_STRENDIAN_E
 
- VDPU_REG_DEC_STRSWAP32_E
 
- VDPU_REG_DEC_TIMEOUT_E
 
- VDPU_REG_DIRECT_MV_ADDR
 
- VDPU_REG_ENABLE_FLAG
 
- VDPU_REG_EN_FLAGS
 
- VDPU_REG_ERROR_CONCEALMENT
 
- VDPU_REG_ERR_CONC_STARTMB_X
 
- VDPU_REG_ERR_CONC_STARTMB_Y
 
- VDPU_REG_FCODE_BWD_HOR
 
- VDPU_REG_FCODE_BWD_VER
 
- VDPU_REG_FCODE_FWD_HOR
 
- VDPU_REG_FCODE_FWD_VER
 
- VDPU_REG_FILTERING_DIS
 
- VDPU_REG_FILTER_LEVEL
 
- VDPU_REG_FILTER_MB_ADJ
 
- VDPU_REG_FILTER_REF_ADJ
 
- VDPU_REG_FILT_MB_ADJ_0
 
- VDPU_REG_FILT_MB_ADJ_1
 
- VDPU_REG_FILT_MB_ADJ_2
 
- VDPU_REG_FILT_MB_ADJ_3
 
- VDPU_REG_FRAME_PRED_DCT
 
- VDPU_REG_FWD_INTERLACE_E
 
- VDPU_REG_FWD_PIC
 
- VDPU_REG_FWD_PIC1_SEGMENT_BASE
 
- VDPU_REG_FWD_PIC1_SEGMENT_E
 
- VDPU_REG_FWD_PIC1_SEGMENT_UPD_E
 
- VDPU_REG_FWD_PIC_PINIT_RLIST_F0
 
- VDPU_REG_FWD_PIC_PINIT_RLIST_F1
 
- VDPU_REG_FWD_PIC_PINIT_RLIST_F2
 
- VDPU_REG_FWD_PIC_PINIT_RLIST_F3
 
- VDPU_REG_FWD_PIC_PINIT_RLIST_F4
 
- VDPU_REG_FWD_PIC_PINIT_RLIST_F5
 
- VDPU_REG_H264_ADDR_REF
 
- VDPU_REG_H264_CTRL
 
- VDPU_REG_H264_PIC_MB_SIZE
 
- VDPU_REG_INITIAL_REF_PIC_LIST0
 
- VDPU_REG_INITIAL_REF_PIC_LIST1
 
- VDPU_REG_INITIAL_REF_PIC_LIST2
 
- VDPU_REG_INITIAL_REF_PIC_LIST3
 
- VDPU_REG_INITIAL_REF_PIC_LIST4
 
- VDPU_REG_INITIAL_REF_PIC_LIST5
 
- VDPU_REG_INITIAL_REF_PIC_LIST6
 
- VDPU_REG_INIT_QP
 
- VDPU_REG_INTERRUPT
 
- VDPU_REG_INTERRUPT_DEC_ASO_INT
 
- VDPU_REG_INTERRUPT_DEC_BUFFER_INT
 
- VDPU_REG_INTERRUPT_DEC_BUS_INT
 
- VDPU_REG_INTERRUPT_DEC_E
 
- VDPU_REG_INTERRUPT_DEC_ERROR_INT
 
- VDPU_REG_INTERRUPT_DEC_IRQ
 
- VDPU_REG_INTERRUPT_DEC_IRQ_DIS
 
- VDPU_REG_INTERRUPT_DEC_PIC_INF
 
- VDPU_REG_INTERRUPT_DEC_RDY_INT
 
- VDPU_REG_INTERRUPT_DEC_SLICE_INT
 
- VDPU_REG_INTERRUPT_DEC_TIMEOUT
 
- VDPU_REG_INTER_DOUBLE_SPEED
 
- VDPU_REG_INTRA_3_CYCLE_ENHANCE
 
- VDPU_REG_INTRA_DC_PREC
 
- VDPU_REG_INTRA_DOUBLE_SPEED
 
- VDPU_REG_INTRA_VLC_TAB
 
- VDPU_REG_LT_REF
 
- VDPU_REG_MV_ACCURACY_BWD
 
- VDPU_REG_MV_ACCURACY_FWD
 
- VDPU_REG_PARAL_BUS_E
 
- VDPU_REG_PIC_B_E
 
- VDPU_REG_PIC_FIELDMODE_E
 
- VDPU_REG_PIC_INTERLACE_E
 
- VDPU_REG_PIC_INTER_E
 
- VDPU_REG_PIC_MB_HEIGHT_P
 
- VDPU_REG_PIC_MB_WIDTH
 
- VDPU_REG_PIC_TOPFIELD_E
 
- VDPU_REG_PRED_FLT
 
- VDPU_REG_PRED_FLT1
 
- VDPU_REG_PRED_FLT10
 
- VDPU_REG_PRED_FLT2
 
- VDPU_REG_PRED_FLT3
 
- VDPU_REG_PRED_FLT4
 
- VDPU_REG_PRED_FLT5
 
- VDPU_REG_PRED_FLT6
 
- VDPU_REG_PRED_FLT7
 
- VDPU_REG_PRED_FLT8
 
- VDPU_REG_PRED_FLT9
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_0_0
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_0_1
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_0_2
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_0_3
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_1_0
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_1_1
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_1_2
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_1_3
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_2_0
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_2_1
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_2_2
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_2_3
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_3_0
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_3_1
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_3_2
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_3_3
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_4_0
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_4_1
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_4_2
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_4_3
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_5_0
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_5_1
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_5_2
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_5_3
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_6_0
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_6_1
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_6_2
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_6_3
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_7_0
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_7_1
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_7_2
 
- VDPU_REG_PRED_FLT_PRED_BC_TAP_7_3
 
- VDPU_REG_PREFETCH_SINGLE_CHANNEL_E
 
- VDPU_REG_QSCALE_TYPE
 
- VDPU_REG_QTABLE_BASE
 
- VDPU_REG_REFBUF_RELATED
 
- VDPU_REG_REFER0_BASE
 
- VDPU_REG_REFER1_BASE
 
- VDPU_REG_REFER2_BASE
 
- VDPU_REG_REFER3_BASE
 
- VDPU_REG_REF_BUF_CTRL2_APF_THRESHOLD
 
- VDPU_REG_REF_BUF_CTRL2_REFBU2_BUF_E
 
- VDPU_REG_REF_BUF_CTRL2_REFBU2_PICID
 
- VDPU_REG_REF_BUF_CTRL2_REFBU2_THR
 
- VDPU_REG_REF_FRAME
 
- VDPU_REG_REF_PIC
 
- VDPU_REG_REF_PIC_ADJ_0
 
- VDPU_REG_REF_PIC_ADJ_1
 
- VDPU_REG_REF_PIC_ADJ_2
 
- VDPU_REG_REF_PIC_ADJ_3
 
- VDPU_REG_REF_PIC_FILT_SHARPNESS
 
- VDPU_REG_REF_PIC_FILT_TYPE_E
 
- VDPU_REG_REF_PIC_LF_LEVEL_0
 
- VDPU_REG_REF_PIC_LF_LEVEL_1
 
- VDPU_REG_REF_PIC_LF_LEVEL_2
 
- VDPU_REG_REF_PIC_LF_LEVEL_3
 
- VDPU_REG_REF_PIC_QUANT_0
 
- VDPU_REG_REF_PIC_QUANT_1
 
- VDPU_REG_REF_PIC_QUANT_2
 
- VDPU_REG_REF_PIC_QUANT_3
 
- VDPU_REG_REF_PIC_QUANT_4
 
- VDPU_REG_REF_PIC_QUANT_5
 
- VDPU_REG_REF_PIC_QUANT_DELTA_0
 
- VDPU_REG_REF_PIC_QUANT_DELTA_1
 
- VDPU_REG_REF_PIC_QUANT_DELTA_2
 
- VDPU_REG_REF_PIC_QUANT_DELTA_3
 
- VDPU_REG_REF_PIC_QUANT_DELTA_4
 
- VDPU_REG_REF_PIC_REFER0_NBR
 
- VDPU_REG_REF_PIC_REFER1_NBR
 
- VDPU_REG_RLC_MODE_E
 
- VDPU_REG_RLC_VLC_BASE
 
- VDPU_REG_SOFT_RESET
 
- VDPU_REG_STARTMB_X
 
- VDPU_REG_STARTMB_Y
 
- VDPU_REG_STREAM_LEN
 
- VDPU_REG_STRM_START_BIT
 
- VDPU_REG_TOPFIELDFIRST_E
 
- VDPU_REG_VALID_REF
 
- VDPU_REG_VP8_ADDR_CTRL_PART
 
- VDPU_REG_VP8_ADDR_REF0
 
- VDPU_REG_VP8_ADDR_REF1
 
- VDPU_REG_VP8_ADDR_REF2_5
 
- VDPU_REG_VP8_AREF_SIGN_BIAS
 
- VDPU_REG_VP8_CTRL0
 
- VDPU_REG_VP8_DATA_VAL
 
- VDPU_REG_VP8_DCT_BASE
 
- VDPU_REG_VP8_DCT_START_BIT
 
- VDPU_REG_VP8_DCT_START_BIT2
 
- VDPU_REG_VP8_GREF_SIGN_BIAS
 
- VDPU_REG_VP8_PIC_MB_SIZE
 
- VDPU_REG_VP8_QUANTER0
 
- VDPU_REG_VP8_QUANTER1
 
- VDPU_REG_VP8_QUANTER2
 
- VDPU_REG_VP8_SEGMENT_VAL
 
- VDPU_REG_WRITE_MVS_E
 
- VDPU_SWREG
 
- VDP_CLK_SRC
 
- VDP_CTRL_COMPDEL_BP
 
- VDP_CTRL_FORMATTER_BP
 
- VDP_CTRL_MATRIX_BP
 
- VDP_CTRL_PREFILTER_BP
 
- VDQCR_FLAGS
 
- VDR
 
- VDREG2
 
- VDREG8
 
- VDS64_HAS_DESCRIPTORS
 
- VDSO32_LBASE
 
- VDSO32_MBASE
 
- VDSO64_LBASE
 
- VDSO_ALIGNMENT
 
- VDSO_AUX_ENT
 
- VDSO_BASE
 
- VDSO_BASES
 
- VDSO_CLOCK_GIC
 
- VDSO_CLOCK_NONE
 
- VDSO_CLOCK_R4K
 
- VDSO_COARSE
 
- VDSO_CPUNODE_BITS
 
- VDSO_CPUNODE_MASK
 
- VDSO_CURRENT_BASE
 
- VDSO_DEFAULT
 
- VDSO_ENTRY
 
- VDSO_FAULT
 
- VDSO_HAS_32BIT_FALLBACK
 
- VDSO_HAS_CLOCK_GETRES
 
- VDSO_HAS_TIME
 
- VDSO_HRES
 
- VDSO_LBASE
 
- VDSO_NOTE_NONEGSEG_BIT
 
- VDSO_PRECISION_MASK
 
- VDSO_PRELINK
 
- VDSO_RANDOMIZE_SIZE
 
- VDSO_RAW
 
- VDSO_SYM
 
- VDSO_SYMBOL
 
- VDSO_TYPES
 
- VDSO_VERSION_STRING
 
- VDSO__MAP_NAME
 
- VDSO__TEMP_FILE_NAME
 
- VDSR
 
- VDSUSP
 
- VDS_2ND_IO4
 
- VDS_DEBUG_PROM
 
- VDS_DEFAULTS
 
- VDS_MANUMODE
 
- VDS_NOARB
 
- VDS_NOGFX
 
- VDS_NOMEMCLEAR
 
- VDS_NOMP
 
- VDS_NO_DIAGS
 
- VDS_PODMODE
 
- VDS_POS_IMP_USE_VOL_DESC
 
- VDS_POS_LENGTH
 
- VDS_POS_LOGICAL_VOL_DESC
 
- VDS_POS_PRIMARY_VOL_DESC
 
- VDS_POS_UNALLOC_SPACE_DESC
 
- VDVS
 
- VDVVRHEN
 
- VDW
 
- VDWIDTH
 
- VD_BLEND_POSTBLD_PREMULT_EN
 
- VD_BLEND_POSTBLD_SRC_OSD1
 
- VD_BLEND_POSTBLD_SRC_OSD2
 
- VD_BLEND_POSTBLD_SRC_VD1
 
- VD_BLEND_POSTBLD_SRC_VD2
 
- VD_BLEND_PREBLD_PREMULT_EN
 
- VD_BLEND_PREBLD_SRC_OSD1
 
- VD_BLEND_PREBLD_SRC_OSD2
 
- VD_BLEND_PREBLD_SRC_VD1
 
- VD_BLEND_PREBLD_SRC_VD2
 
- VD_BYTES_PER_PIXEL
 
- VD_CHRO_RPT_LASTL_CTRL
 
- VD_COLOR_MAP
 
- VD_DEMUX_MODE_RGB
 
- VD_DISK_TYPE_DISK
 
- VD_DISK_TYPE_SLICE
 
- VD_ENABLE
 
- VD_HOLD_LINES
 
- VD_HORZ_FMT_EN
 
- VD_HORZ_Y_C_RATIO
 
- VD_H_END
 
- VD_H_START
 
- VD_H_WIDTH
 
- VD_LITTLE_ENDIAN
 
- VD_MEDIA_TYPE_CD
 
- VD_MEDIA_TYPE_DVD
 
- VD_MEDIA_TYPE_FIXED
 
- VD_OP_BREAD
 
- VD_OP_BWRITE
 
- VD_OP_FLUSH
 
- VD_OP_GET_DEVID
 
- VD_OP_GET_DISKGEOM
 
- VD_OP_GET_EFI
 
- VD_OP_GET_VTOC
 
- VD_OP_GET_WCE
 
- VD_OP_SCSICMD
 
- VD_OP_SET_DISKGEOM
 
- VD_OP_SET_EFI
 
- VD_OP_SET_VTOC
 
- VD_OP_SET_WCE
 
- VD_REGION13_END
 
- VD_REGION24_START
 
- VD_SEPARATE_EN
 
- VD_URGENT_CHROMA
 
- VD_URGENT_LUMA
 
- VD_VERT_FMT_EN
 
- VD_VERT_INITIAL_PHASE
 
- VD_VERT_PHASE_STEP
 
- VD_VERT_RPT_LINE0
 
- VD_V_END
 
- VD_V_START
 
- VD_V_WIDTH
 
- VD_X_END
 
- VD_X_START
 
- VD_Y_END
 
- VD_Y_START
 
- VEB
 
- VEBOX_HWS_PGA_GEN7
 
- VEBOX_MASK
 
- VEBOX_RING_BASE
 
- VECBASE_VADDR
 
- VECOFF
 
- VECS0
 
- VECS0_HW
 
- VECS1
 
- VECS1_HW
 
- VECS_AS_CONTEXT_SWITCH
 
- VECS_MI_FLUSH_DW
 
- VECS_MI_USER_INTERRUPT
 
- VECTOR
 
- VECTORING_INFO_DELIVER_CODE_MASK
 
- VECTORING_INFO_TYPE_MASK
 
- VECTORING_INFO_VALID_MASK
 
- VECTORING_INFO_VECTOR_MASK
 
- VECTORS
 
- VECTORSPACING
 
- VECTORS_BASE
 
- VECTORS__MAP_NAME
 
- VECTOR_BASE_IRQ
 
- VECTOR_BPF
 
- VECTOR_BREAKPOINT
 
- VECTOR_BUSY_TIMEOUT
 
- VECTOR_DOMAIN_NONE
 
- VECTOR_DOMAIN_PERCPU
 
- VECTOR_HEADERS
 
- VECTOR_IRQ_SPACE
 
- VECTOR_LENGTH
 
- VECTOR_MASK
 
- VECTOR_MODE
 
- VECTOR_NUM_STATS
 
- VECTOR_QDISC_BYPASS
 
- VECTOR_READ
 
- VECTOR_RETRIGGERED
 
- VECTOR_RX
 
- VECTOR_SHUTDOWN
 
- VECTOR_TABLE_SIZE
 
- VECTOR_TX
 
- VECTOR_UNUSED
 
- VECTOR_VADDR
 
- VECTOR_WRITE
 
- VEC_ACCESS
 
- VEC_ADDRERR
 
- VEC_ALIGN
 
- VEC_AUTOVEC
 
- VEC_BREAKPOINT
 
- VEC_BUSERR
 
- VEC_CFG
 
- VEC_CFG_ENABLE
 
- VEC_CFG_MB_EN
 
- VEC_CFG_SG_EN
 
- VEC_CFG_SG_MODE
 
- VEC_CFG_SG_MODE_MASK
 
- VEC_CFG_TB_EN
 
- VEC_CFG_VEC_EN
 
- VEC_CHK
 
- VEC_CLMP0_END
 
- VEC_CLMP0_START
 
- VEC_CONFIG0
 
- VEC_CONFIG0_BURDIS
 
- VEC_CONFIG0_CBURST_GAIN_1_128
 
- VEC_CONFIG0_CBURST_GAIN_1_32
 
- VEC_CONFIG0_CBURST_GAIN_1_64
 
- VEC_CONFIG0_CBURST_GAIN_MASK
 
- VEC_CONFIG0_CBURST_GAIN_UNITY
 
- VEC_CONFIG0_CDEL
 
- VEC_CONFIG0_CDEL_MASK
 
- VEC_CONFIG0_CHRBW0
 
- VEC_CONFIG0_CHRBW1
 
- VEC_CONFIG0_CHRDIS
 
- VEC_CONFIG0_CHROMA_GAIN_1_16
 
- VEC_CONFIG0_CHROMA_GAIN_1_32
 
- VEC_CONFIG0_CHROMA_GAIN_1_8
 
- VEC_CONFIG0_CHROMA_GAIN_MASK
 
- VEC_CONFIG0_CHROMA_GAIN_UNITY
 
- VEC_CONFIG0_NTSC_STD
 
- VEC_CONFIG0_PAL_BDGHI_STD
 
- VEC_CONFIG0_PAL_N_STD
 
- VEC_CONFIG0_PBPR_FIL
 
- VEC_CONFIG0_PDEN
 
- VEC_CONFIG0_RAMPEN
 
- VEC_CONFIG0_STD_MASK
 
- VEC_CONFIG0_SYNCDIS
 
- VEC_CONFIG0_YCDELAY
 
- VEC_CONFIG0_YCDIS
 
- VEC_CONFIG0_YDEL
 
- VEC_CONFIG0_YDEL_MASK
 
- VEC_CONFIG1
 
- VEC_CONFIG1_COMPDIS
 
- VEC_CONFIG1_CUSTOM_FREQ
 
- VEC_CONFIG1_CVBS_Y_C
 
- VEC_CONFIG1_CYDELAY
 
- VEC_CONFIG1_C_CVBS_CVBS
 
- VEC_CONFIG1_C_CVBS_Y
 
- VEC_CONFIG1_C_Y_CVBS
 
- VEC_CONFIG1_DIS_CHR
 
- VEC_CONFIG1_DIS_LUMA
 
- VEC_CONFIG1_DITHER_EN
 
- VEC_CONFIG1_DITHER_TYPE_COUNTER
 
- VEC_CONFIG1_DITHER_TYPE_LFSR
 
- VEC_CONFIG1_LUMADIS
 
- VEC_CONFIG1_OUTPUT_MODE_MASK
 
- VEC_CONFIG1_PR_Y_PB
 
- VEC_CONFIG1_RGB
 
- VEC_CONFIG1_YCBCR_IN
 
- VEC_CONFIG1_Y_C_CVBS
 
- VEC_CONFIG2
 
- VEC_CONFIG2_PBPR_EN
 
- VEC_CONFIG2_PROG_SCAN
 
- VEC_CONFIG2_RGB_DIG_DIS
 
- VEC_CONFIG2_SYNC_ADJ
 
- VEC_CONFIG2_SYNC_ADJ_MASK
 
- VEC_CONFIG2_TMUX_DRIVE0
 
- VEC_CONFIG2_TMUX_MASK
 
- VEC_CONFIG2_TMUX_RG_COMP
 
- VEC_CONFIG2_TMUX_SYNC_YC
 
- VEC_CONFIG2_TMUX_UV_YC
 
- VEC_CONFIG2_UV_DIG_DIS
 
- VEC_CONFIG3
 
- VEC_CONFIG3_HORIZ_LEN_MPEG1_SIF
 
- VEC_CONFIG3_HORIZ_LEN_STD
 
- VEC_CONFIG3_SHAPE_NON_LINEAR
 
- VEC_CONFIG_CBAR_EN
 
- VEC_CONFIG_RGB219
 
- VEC_CONFIG_TC_OBB
 
- VEC_CONFIG_VEC_RESYNC_OFF
 
- VEC_COPROC
 
- VEC_DAC_CONFIG
 
- VEC_DAC_CONFIG_DAC_CTRL
 
- VEC_DAC_CONFIG_DRIVER_CTRL
 
- VEC_DAC_CONFIG_LDO_BIAS_CTRL
 
- VEC_DAC_MISC
 
- VEC_DAC_MISC_BIAS_PWRDN
 
- VEC_DAC_MISC_DAC_PWRDN
 
- VEC_DAC_MISC_DAC_RST_N
 
- VEC_DAC_MISC_LDO_PWRDN
 
- VEC_DAC_MISC_VCD_CTRL
 
- VEC_DAC_MISC_VCD_CTRL_MASK
 
- VEC_DAC_MISC_VCD_PWRDN
 
- VEC_DAC_MISC_VID_ACT
 
- VEC_DAC_TEST
 
- VEC_FAUTOVEC
 
- VEC_FCW_SECAM_B
 
- VEC_FLAG_TERMINATE
 
- VEC_FORMAT
 
- VEC_FPBRUC
 
- VEC_FPDIVZ
 
- VEC_FPE
 
- VEC_FPIR
 
- VEC_FPNAN
 
- VEC_FPOE
 
- VEC_FPOVER
 
- VEC_FPUNDER
 
- VEC_FPUNSUP
 
- VEC_FREQ1_0
 
- VEC_FREQ3_2
 
- VEC_HWACCEL
 
- VEC_ILLEGAL
 
- VEC_INIT
 
- VEC_INT1
 
- VEC_INT2
 
- VEC_INT3
 
- VEC_INT4
 
- VEC_INT5
 
- VEC_INT6
 
- VEC_INT7
 
- VEC_INTERRUPT_CONTROL
 
- VEC_INTERRUPT_STATUS
 
- VEC_LINE10
 
- VEC_LINE11
 
- VEC_MASK0
 
- VEC_MAX
 
- VEC_MMUACC
 
- VEC_MMUCFG
 
- VEC_MMUILL
 
- VEC_NAME_SIZE
 
- VEC_POS
 
- VEC_PRFL
 
- VEC_PRIV
 
- VEC_READ
 
- VEC_RESET
 
- VEC_RESETPC
 
- VEC_RESETSP
 
- VEC_RESV12
 
- VEC_RESV16
 
- VEC_RESV17
 
- VEC_RESV18
 
- VEC_RESV19
 
- VEC_RESV20
 
- VEC_RESV21
 
- VEC_RESV22
 
- VEC_RESV23
 
- VEC_RESV59
 
- VEC_RESV62
 
- VEC_RESV63
 
- VEC_REVID
 
- VEC_SCHPH
 
- VEC_SECAM_GAIN_VAL
 
- VEC_SOFTRESET
 
- VEC_SOFT_RESET
 
- VEC_SPUR
 
- VEC_STATUS0
 
- VEC_SYS
 
- VEC_TLBINVALIDL
 
- VEC_TLBINVALIDS
 
- VEC_TLBMISS
 
- VEC_TLBMODIFIED
 
- VEC_TRACE
 
- VEC_TRAP
 
- VEC_TRAP0
 
- VEC_TRAP1
 
- VEC_TRAP10
 
- VEC_TRAP11
 
- VEC_TRAP12
 
- VEC_TRAP13
 
- VEC_TRAP14
 
- VEC_TRAP15
 
- VEC_TRAP2
 
- VEC_TRAP3
 
- VEC_TRAP4
 
- VEC_TRAP5
 
- VEC_TRAP6
 
- VEC_TRAP7
 
- VEC_TRAP8
 
- VEC_TRAP9
 
- VEC_UNA_EXCEPTION
 
- VEC_UNIMPEA
 
- VEC_UNIMPII
 
- VEC_UNINT
 
- VEC_UNRECOVER
 
- VEC_USER
 
- VEC_WRITE
 
- VEC_WSE_CONTROL
 
- VEC_WSE_RESET
 
- VEC_WSE_VPS_CONTROL
 
- VEC_WSE_VPS_DATA1
 
- VEC_WSE_WSS_DATA
 
- VEC_WSE_WSS_ENABLE
 
- VEC_ZERODIV
 
- VED_SS_PM0
 
- VEFLAGS
 
- VEGA10_CONFIGREG_CACHE
 
- VEGA10_CONFIGREG_DIDT
 
- VEGA10_CONFIGREG_DIDT_IND
 
- VEGA10_CONFIGREG_GCCAC
 
- VEGA10_CONFIGREG_MAX
 
- VEGA10_CONFIGREG_MMR
 
- VEGA10_CONFIGREG_SECAC
 
- VEGA10_CONFIGREG_SMC_IND
 
- VEGA10_DPM2_ABOVE_SAFE_INC
 
- VEGA10_DPM2_BELOW_SAFE_INC
 
- VEGA10_DPM2_LTA_WINDOW_SIZE
 
- VEGA10_DPM2_LTS_TRUNCATE
 
- VEGA10_DPM2_MAXPS_PERCENT_H
 
- VEGA10_DPM2_MAXPS_PERCENT_M
 
- VEGA10_DPM2_NEAR_TDP_DEC
 
- VEGA10_DPM2_PWREFFICIENCYRATIO_MARGIN
 
- VEGA10_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO
 
- VEGA10_DPM2_SQ_RAMP_MAX_POWER
 
- VEGA10_DPM2_SQ_RAMP_MAX_POWER_DELTA
 
- VEGA10_DPM2_SQ_RAMP_MIN_POWER
 
- VEGA10_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE
 
- VEGA10_DPM2_TDP_SAFE_LIMIT_PERCENT
 
- VEGA10_ENGINECLOCK_HARDMAX
 
- VEGA10_GB_ADDR_CONFIG_GOLDEN
 
- VEGA10_INC_H
 
- VEGA10_MAX_DEEPSLEEP_DIVIDER_ID
 
- VEGA10_MAX_HARDWARE_POWERLEVELS
 
- VEGA10_MAX_LEAKAGE_COUNT
 
- VEGA10_MINIMUM_ENGINE_CLOCK
 
- VEGA10_PROCESSPPTABLES_H
 
- VEGA10_Q88_FORMAT_CONVERSION_UNIT
 
- VEGA10_THERMAL_H
 
- VEGA10_THERMAL_HIGH_ALERT_MASK
 
- VEGA10_THERMAL_LOW_ALERT_MASK
 
- VEGA10_THERMAL_MAXIMUM_ALERT_TEMP
 
- VEGA10_THERMAL_MAXIMUM_TEMP_READING
 
- VEGA10_THERMAL_MINIMUM_ALERT_TEMP
 
- VEGA10_THERMAL_MINIMUM_TEMP_READING
 
- VEGA10_THERM_OUT_MODE_DISABLE
 
- VEGA10_THERM_OUT_MODE_THERM_ONLY
 
- VEGA10_THERM_OUT_MODE_THERM_VRHOT
 
- VEGA10_UMD_PSTATE_GFXCLK_LEVEL
 
- VEGA10_UMD_PSTATE_MCLK_LEVEL
 
- VEGA10_UMD_PSTATE_SOCCLK_LEVEL
 
- VEGA10_UNUSED_GPIO_PIN
 
- VEGA10_VOLTAGE_CONTROL_BY_GPIO
 
- VEGA10_VOLTAGE_CONTROL_BY_SVID2
 
- VEGA10_VOLTAGE_CONTROL_MERGED
 
- VEGA10_VOLTAGE_CONTROL_NONE
 
- VEGA12_DPM2_ABOVE_SAFE_INC
 
- VEGA12_DPM2_BELOW_SAFE_INC
 
- VEGA12_DPM2_LTA_WINDOW_SIZE
 
- VEGA12_DPM2_LTS_TRUNCATE
 
- VEGA12_DPM2_MAXPS_PERCENT_H
 
- VEGA12_DPM2_MAXPS_PERCENT_M
 
- VEGA12_DPM2_NEAR_TDP_DEC
 
- VEGA12_DPM2_PWREFFICIENCYRATIO_MARGIN
 
- VEGA12_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO
 
- VEGA12_DPM2_SQ_RAMP_MAX_POWER
 
- VEGA12_DPM2_SQ_RAMP_MAX_POWER_DELTA
 
- VEGA12_DPM2_SQ_RAMP_MIN_POWER
 
- VEGA12_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE
 
- VEGA12_DPM2_TDP_SAFE_LIMIT_PERCENT
 
- VEGA12_ENGINECLOCK_HARDMAX
 
- VEGA12_GB_ADDR_CONFIG_GOLDEN
 
- VEGA12_INC_H
 
- VEGA12_MAX_DEEPSLEEP_DIVIDER_ID
 
- VEGA12_MAX_HARDWARE_POWERLEVELS
 
- VEGA12_MAX_LEAKAGE_COUNT
 
- VEGA12_MINIMUM_ENGINE_CLOCK
 
- VEGA12_PP_SMC_H
 
- VEGA12_PROCESSPPTABLES_H
 
- VEGA12_Q88_FORMAT_CONVERSION_UNIT
 
- VEGA12_SMU9_DRIVER_IF_H
 
- VEGA12_THERMAL_H
 
- VEGA12_THERMAL_HIGH_ALERT_MASK
 
- VEGA12_THERMAL_LOW_ALERT_MASK
 
- VEGA12_THERMAL_MAXIMUM_ALERT_TEMP
 
- VEGA12_THERMAL_MAXIMUM_TEMP_READING
 
- VEGA12_THERMAL_MINIMUM_ALERT_TEMP
 
- VEGA12_THERMAL_MINIMUM_TEMP_READING
 
- VEGA12_THERM_OUT_MODE_DISABLE
 
- VEGA12_THERM_OUT_MODE_THERM_ONLY
 
- VEGA12_THERM_OUT_MODE_THERM_VRHOT
 
- VEGA12_UMD_PSTATE_GFXCLK_LEVEL
 
- VEGA12_UMD_PSTATE_MCLK_LEVEL
 
- VEGA12_UMD_PSTATE_SOCCLK_LEVEL
 
- VEGA12_UMD_PSTATE_UVDCLK_LEVEL
 
- VEGA12_UMD_PSTATE_VCEMCLK_LEVEL
 
- VEGA12_UNUSED_GPIO_PIN
 
- VEGA12_VOLTAGE_CONTROL_BY_GPIO
 
- VEGA12_VOLTAGE_CONTROL_BY_SVID2
 
- VEGA12_VOLTAGE_CONTROL_MERGED
 
- VEGA12_VOLTAGE_CONTROL_NONE
 
- VEGA20_DPM2_ABOVE_SAFE_INC
 
- VEGA20_DPM2_BELOW_SAFE_INC
 
- VEGA20_DPM2_LTA_WINDOW_SIZE
 
- VEGA20_DPM2_LTS_TRUNCATE
 
- VEGA20_DPM2_MAXPS_PERCENT_H
 
- VEGA20_DPM2_MAXPS_PERCENT_M
 
- VEGA20_DPM2_NEAR_TDP_DEC
 
- VEGA20_DPM2_PWREFFICIENCYRATIO_MARGIN
 
- VEGA20_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO
 
- VEGA20_DPM2_SQ_RAMP_MAX_POWER
 
- VEGA20_DPM2_SQ_RAMP_MAX_POWER_DELTA
 
- VEGA20_DPM2_SQ_RAMP_MIN_POWER
 
- VEGA20_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE
 
- VEGA20_DPM2_TDP_SAFE_LIMIT_PERCENT
 
- VEGA20_ENGINECLOCK_HARDMAX
 
- VEGA20_FAN_TARGET_TEMPERATURE_OVERRIDE
 
- VEGA20_INC_H
 
- VEGA20_MAX_DEEPSLEEP_DIVIDER_ID
 
- VEGA20_MAX_HARDWARE_POWERLEVELS
 
- VEGA20_MAX_LEAKAGE_COUNT
 
- VEGA20_MINIMUM_ENGINE_CLOCK
 
- VEGA20_PP_SMC_H
 
- VEGA20_PROCESSPPTABLES_H
 
- VEGA20_Q88_FORMAT_CONVERSION_UNIT
 
- VEGA20_THERMAL_H
 
- VEGA20_THERMAL_HIGH_ALERT_MASK
 
- VEGA20_THERMAL_LOW_ALERT_MASK
 
- VEGA20_THERMAL_MAXIMUM_ALERT_TEMP
 
- VEGA20_THERMAL_MAXIMUM_TEMP_READING
 
- VEGA20_THERMAL_MINIMUM_ALERT_TEMP
 
- VEGA20_THERMAL_MINIMUM_TEMP_READING
 
- VEGA20_THERM_OUT_MODE_DISABLE
 
- VEGA20_THERM_OUT_MODE_THERM_ONLY
 
- VEGA20_THERM_OUT_MODE_THERM_VRHOT
 
- VEGA20_UMD_PSTATE_GFXCLK_LEVEL
 
- VEGA20_UMD_PSTATE_MCLK_LEVEL
 
- VEGA20_UMD_PSTATE_SOCCLK_LEVEL
 
- VEGA20_UMD_PSTATE_UVDCLK_LEVEL
 
- VEGA20_UMD_PSTATE_VCEMCLK_LEVEL
 
- VEGA20_UNUSED_GPIO_PIN
 
- VEGA20_VOLTAGE_CONTROL_BY_GPIO
 
- VEGA20_VOLTAGE_CONTROL_BY_SVID2
 
- VEGA20_VOLTAGE_CONTROL_MERGED
 
- VEGA20_VOLTAGE_CONTROL_NONE
 
- VEI_CMD_BIT
 
- VEI_FLOW_OFF
 
- VEI_FLOW_ON
 
- VEI_PAYLOAD
 
- VEI_SET_PIN
 
- VELOCITY_AUTONEG_ENABLE
 
- VELOCITY_DBG
 
- VELOCITY_DUPLEX_FULL
 
- VELOCITY_FLAGS_FLOW_CTRL
 
- VELOCITY_FLAGS_IP_ALIGN
 
- VELOCITY_FLAGS_OPENED
 
- VELOCITY_FLAGS_RX_CSUM
 
- VELOCITY_FLAGS_TAGGING
 
- VELOCITY_FLAGS_VAL_PKT_LEN
 
- VELOCITY_FLAGS_VMNS_COMMITTED
 
- VELOCITY_FLAGS_VMNS_CONNECTED
 
- VELOCITY_FLAGS_WOL_ENABLED
 
- VELOCITY_FORCED_BY_EEPROM
 
- VELOCITY_FULL_DRV_NAM
 
- VELOCITY_H
 
- VELOCITY_INIT_COLD
 
- VELOCITY_INIT_RESET
 
- VELOCITY_INIT_WOL
 
- VELOCITY_IO_SIZE
 
- VELOCITY_LINK_CHANGE
 
- VELOCITY_LINK_FAIL
 
- VELOCITY_MAX_MTU
 
- VELOCITY_MIN_MTU
 
- VELOCITY_NAME
 
- VELOCITY_NAPI_WEIGHT
 
- VELOCITY_PARAM
 
- VELOCITY_PRT
 
- VELOCITY_PRT_CAMMASK
 
- VELOCITY_SPEED_10
 
- VELOCITY_SPEED_100
 
- VELOCITY_SPEED_1000
 
- VELOCITY_TX_CSUM_SUPPORT
 
- VELOCITY_VERSION
 
- VELOCITY_WOL_ARP
 
- VELOCITY_WOL_BCAST
 
- VELOCITY_WOL_MAGIC
 
- VELOCITY_WOL_MAGIC_SEC
 
- VELOCITY_WOL_MCAST
 
- VELOCITY_WOL_PHY
 
- VELOCITY_WOL_UCAST
 
- VEML6070_ADDR_CONFIG_DATA_MSB
 
- VEML6070_ADDR_DATA_LSB
 
- VEML6070_COMMAND_ACK
 
- VEML6070_COMMAND_IT
 
- VEML6070_COMMAND_RSRVD
 
- VEML6070_COMMAND_SD
 
- VEML6070_DRV_NAME
 
- VEML6070_IT_10
 
- VENC_ACCTL
 
- VENC_ARGBX0
 
- VENC_ARGBX1
 
- VENC_ARGBX2
 
- VENC_ARGBX3
 
- VENC_ARGBX4
 
- VENC_ATR0
 
- VENC_ATR1
 
- VENC_ATR2
 
- VENC_AVID_START_STOP_X
 
- VENC_AVID_START_STOP_Y
 
- VENC_BITSTREAM_FRAME_SIZE
 
- VENC_BITSTREAM_HEADER_LEN
 
- VENC_BLACK_LEVEL
 
- VENC_BLANK_BLACK_LEVEL
 
- VENC_BLANK_LEVEL
 
- VENC_BRTS
 
- VENC_BRTW
 
- VENC_BSTAMP_WSS_DATA
 
- VENC_BURST_LEVEL
 
- VENC_C656_CTRL
 
- VENC_CAPCTL
 
- VENC_CAPDE
 
- VENC_CAPDO
 
- VENC_CC_CARR_WSS_CARR
 
- VENC_CLKCTL
 
- VENC_CMPNT
 
- VENC_CMPNT_MRGB
 
- VENC_CMPNT_MRGB_SHIFT
 
- VENC_CONTROL_PARAM
 
- VENC_CULLLINE
 
- VENC_CVBS
 
- VENC_C_PHASE
 
- VENC_DACSEL
 
- VENC_DACTST
 
- VENC_DAC_B__DAC_C
 
- VENC_DCLKCTL
 
- VENC_DCLKCTL_DCKEC
 
- VENC_DCLKCTL_DCKEC_SHIFT
 
- VENC_DCLKCTL_DCKPW
 
- VENC_DCLKCTL_DCKPW_SHIFT
 
- VENC_DCLKHR
 
- VENC_DCLKHS
 
- VENC_DCLKHSA
 
- VENC_DCLKPTN0
 
- VENC_DCLKPTN0A
 
- VENC_DCLKPTN1
 
- VENC_DCLKPTN1A
 
- VENC_DCLKPTN2
 
- VENC_DCLKPTN2A
 
- VENC_DCLKPTN3
 
- VENC_DCLKPTN3A
 
- VENC_DCLKVR
 
- VENC_DCLKVS
 
- VENC_DRGBX0
 
- VENC_DRGBX1
 
- VENC_DRGBX2
 
- VENC_DRGBX3
 
- VENC_DRGBX4
 
- VENC_DVI_SETTING
 
- VENC_DVI_SETTING_MORE
 
- VENC_ENABLE
 
- VENC_ENCI_LINE
 
- VENC_ENCI_PIXEL
 
- VENC_ENCP_LINE
 
- VENC_ENCP_PIXEL
 
- VENC_END_OF_FRAME
 
- VENC_ETMG0
 
- VENC_ETMG1
 
- VENC_ETMG2
 
- VENC_ETMG3
 
- VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y
 
- VENC_FID_INT_OFFSET_Y__FID_EXT_START_X
 
- VENC_FID_INT_START_X__FID_INT_START_Y
 
- VENC_FIELD1_PARAM
 
- VENC_FIELD2_PARAM
 
- VENC_FIRST_FIELD
 
- VENC_FLENS
 
- VENC_FLEN__FAL
 
- VENC_F_CONTROL
 
- VENC_GAIN_U
 
- VENC_GAIN_V
 
- VENC_GAIN_Y
 
- VENC_GAMCTL
 
- VENC_GEN_CTRL
 
- VENC_GET_FLD
 
- VENC_H264_VPU_WORK_BUF_MAX
 
- VENC_H264_VPU_WORK_BUF_MV_INFO_1
 
- VENC_H264_VPU_WORK_BUF_MV_INFO_2
 
- VENC_H264_VPU_WORK_BUF_RC_CODE
 
- VENC_H264_VPU_WORK_BUF_RC_INFO
 
- VENC_H264_VPU_WORK_BUF_REC_CHROMA
 
- VENC_H264_VPU_WORK_BUF_REC_LUMA
 
- VENC_H264_VPU_WORK_BUF_REF_CHROMA
 
- VENC_H264_VPU_WORK_BUF_REF_LUMA
 
- VENC_H264_VPU_WORK_BUF_SKIP_FRAME
 
- VENC_HFLTR_CTRL
 
- VENC_HINT
 
- VENC_HSDLY
 
- VENC_HSPLS
 
- VENC_HSTART
 
- VENC_HS_EXT_START_STOP_X
 
- VENC_HS_INT_START_STOP_X
 
- VENC_HTRIGGER_VTRIGGER
 
- VENC_HVALID
 
- VENC_HVLDCL0
 
- VENC_HVLDCL1
 
- VENC_INTCTRL
 
- VENC_INTCTRL_ENCI_LNRST_INT_EN
 
- VENC_INTFLAG
 
- VENC_IPI_MSG_STATUS_FAIL
 
- VENC_IPI_MSG_STATUS_OK
 
- VENC_L21__WC_CTL
 
- VENC_LAL__PHASE_RESET
 
- VENC_LCDOUT
 
- VENC_LINE21
 
- VENC_LINECTL
 
- VENC_LINE_E_1
 
- VENC_LINE_E_2
 
- VENC_LINE_O_1
 
- VENC_LINE_O_2
 
- VENC_LINE_TIMING_PARAM
 
- VENC_LLEN
 
- VENC_LN_SEL
 
- VENC_LT_SYS
 
- VENC_MODE_NTSC
 
- VENC_MODE_PAL
 
- VENC_MODE_UNKNOWN
 
- VENC_M_CONTROL
 
- VENC_OSDCLK0
 
- VENC_OSDCLK1
 
- VENC_OSDHADV
 
- VENC_OUTPUT_CONTROL
 
- VENC_OUTPUT_TEST
 
- VENC_PHASE_LINE_INCR_CVBS
 
- VENC_PIC_BITSTREAM_BYTE_CNT
 
- VENC_PWMP
 
- VENC_PWMW
 
- VENC_RAMADR
 
- VENC_RAMPORT
 
- VENC_REV_ID
 
- VENC_RGBCLP
 
- VENC_RGBCTL
 
- VENC_SAVID__EAVID
 
- VENC_SCPROG
 
- VENC_SECOND_FIELD
 
- VENC_SET_PARAM_ADJUST_BITRATE
 
- VENC_SET_PARAM_ADJUST_FRAMERATE
 
- VENC_SET_PARAM_ENC
 
- VENC_SET_PARAM_FORCE_INTRA
 
- VENC_SET_PARAM_GOP_SIZE
 
- VENC_SET_PARAM_INTRA_PERIOD
 
- VENC_SET_PARAM_PREPEND_HEADER
 
- VENC_SET_PARAM_SKIP_FRAME
 
- VENC_SET_PARAM_TS_MODE
 
- VENC_START_OPT_ENCODE_FRAME
 
- VENC_START_OPT_ENCODE_SEQUENCE_HEADER
 
- VENC_STATA
 
- VENC_STATUS
 
- VENC_STD_ALL
 
- VENC_SUB_CARRIER_PHASE1
 
- VENC_SYNCCTL
 
- VENC_SYNCCTL_HPL
 
- VENC_SYNCCTL_HPL_SHIFT
 
- VENC_SYNCCTL_OVD
 
- VENC_SYNCCTL_OVD_SHIFT
 
- VENC_SYNCCTL_SYEH
 
- VENC_SYNCCTL_SYEH_SHIFT
 
- VENC_SYNCCTL_SYEV
 
- VENC_SYNCCTL_SYEV_SHIFT
 
- VENC_SYNCCTL_VPL
 
- VENC_SYNCCTL_VPL_SHIFT
 
- VENC_SYNC_CTRL
 
- VENC_SYNC_ROUTE
 
- VENC_SYS
 
- VENC_S_CARR
 
- VENC_TVDETGP_INT_START_STOP_X
 
- VENC_TVDETGP_INT_START_STOP_Y
 
- VENC_UPSAMPLE_CTRL0
 
- VENC_UPSAMPLE_CTRL1
 
- VENC_UPSAMPLE_CTRL2
 
- VENC_UPSAMPLE_CTRL_CVBS
 
- VENC_UPSAMPLE_CTRL_F0_2_CLK_RATIO
 
- VENC_UPSAMPLE_CTRL_F1_EN
 
- VENC_UPSAMPLE_CTRL_F1_UPSAMPLE_EN
 
- VENC_UPSAMPLE_CTRL_INTERLACE_B
 
- VENC_UPSAMPLE_CTRL_INTERLACE_G
 
- VENC_UPSAMPLE_CTRL_INTERLACE_HIGH_LUMA
 
- VENC_UPSAMPLE_CTRL_INTERLACE_PB
 
- VENC_UPSAMPLE_CTRL_INTERLACE_PR
 
- VENC_UPSAMPLE_CTRL_INTERLACE_R
 
- VENC_UPSAMPLE_CTRL_PROGRESSIVE_B
 
- VENC_UPSAMPLE_CTRL_PROGRESSIVE_G
 
- VENC_UPSAMPLE_CTRL_PROGRESSIVE_PB
 
- VENC_UPSAMPLE_CTRL_PROGRESSIVE_PR
 
- VENC_UPSAMPLE_CTRL_PROGRESSIVE_R
 
- VENC_UPSAMPLE_CTRL_PROGRESSIVE_Y
 
- VENC_UPSAMPLE_CTRL_S_VIDEO_CHROMA
 
- VENC_UPSAMPLE_CTRL_S_VIDEO_LUMA
 
- VENC_UPSAMPLE_CTRL_VDAC_TEST_VALUE
 
- VENC_VDAC_DAC0_FILT_CTRL0
 
- VENC_VDAC_DAC0_FILT_CTRL0_EN
 
- VENC_VDAC_DAC0_FILT_CTRL1
 
- VENC_VDAC_DAC0_GAINCTRL
 
- VENC_VDAC_DAC0_OFFSET
 
- VENC_VDAC_DAC1_FILT_CTRL0
 
- VENC_VDAC_DAC1_FILT_CTRL1
 
- VENC_VDAC_DAC1_GAINCTRL
 
- VENC_VDAC_DAC1_OFFSET
 
- VENC_VDAC_DAC2_FILT_CTRL0
 
- VENC_VDAC_DAC2_FILT_CTRL1
 
- VENC_VDAC_DAC2_GAINCTRL
 
- VENC_VDAC_DAC2_OFFSET
 
- VENC_VDAC_DAC3_FILT_CTRL0
 
- VENC_VDAC_DAC3_FILT_CTRL1
 
- VENC_VDAC_DAC3_GAINCTRL
 
- VENC_VDAC_DAC3_OFFSET
 
- VENC_VDAC_DAC4_FILT_CTRL0
 
- VENC_VDAC_DAC4_FILT_CTRL1
 
- VENC_VDAC_DAC4_GAINCTRL
 
- VENC_VDAC_DAC4_OFFSET
 
- VENC_VDAC_DAC5_FILT_CTRL0
 
- VENC_VDAC_DAC5_FILT_CTRL1
 
- VENC_VDAC_DAC5_GAINCTRL
 
- VENC_VDAC_DAC5_OFFSET
 
- VENC_VDAC_DACSEL0
 
- VENC_VDAC_DACSEL1
 
- VENC_VDAC_DACSEL2
 
- VENC_VDAC_DACSEL3
 
- VENC_VDAC_DACSEL4
 
- VENC_VDAC_DACSEL5
 
- VENC_VDAC_FIFO_CTRL
 
- VENC_VDAC_FIFO_EN_ENCI_ENABLE
 
- VENC_VDAC_SEL_ATV_DMD
 
- VENC_VDAC_SETTING
 
- VENC_VDAC_TST_VAL
 
- VENC_VDPRO
 
- VENC_VDPRO_ATCOM
 
- VENC_VDPRO_ATCOM_SHIFT
 
- VENC_VDPRO_ATYCC
 
- VENC_VDPRO_ATYCC_SHIFT
 
- VENC_VDPRO_CUPS
 
- VENC_VDPRO_DAFRQ
 
- VENC_VDPRO_DAUPS
 
- VENC_VDPRO_YUPS
 
- VENC_VIDCTL
 
- VENC_VIDCTL_DOMD
 
- VENC_VIDCTL_DOMD_SHIFT
 
- VENC_VIDCTL_SYDIR
 
- VENC_VIDCTL_SYDIR_SHIFT
 
- VENC_VIDCTL_VCLKE
 
- VENC_VIDCTL_VCLKE_SHIFT
 
- VENC_VIDCTL_VCLKP
 
- VENC_VIDCTL_VCLKZ
 
- VENC_VIDCTL_VCLKZ_SHIFT
 
- VENC_VIDCTL_YCDIR
 
- VENC_VIDCTL_YCDIR_SHIFT
 
- VENC_VIDEO_EXSRC
 
- VENC_VIDEO_INFO
 
- VENC_VIDEO_PROG_MODE
 
- VENC_VIDEO_RES
 
- VENC_VIDEO_TST_CB
 
- VENC_VIDEO_TST_CLRBAR_STRT
 
- VENC_VIDEO_TST_CLRBAR_WIDTH
 
- VENC_VIDEO_TST_CR
 
- VENC_VIDEO_TST_EN
 
- VENC_VIDEO_TST_MDSEL
 
- VENC_VIDEO_TST_VDCNT_STSET
 
- VENC_VIDEO_TST_Y
 
- VENC_VIDOUT_CTRL
 
- VENC_VINT
 
- VENC_VMOD
 
- VENC_VMOD_BLNK
 
- VENC_VMOD_HDMD
 
- VENC_VMOD_ITLC
 
- VENC_VMOD_ITLCL
 
- VENC_VMOD_NSIT
 
- VENC_VMOD_SLAVE
 
- VENC_VMOD_TVTYP
 
- VENC_VMOD_TVTYP_SHIFT
 
- VENC_VMOD_VDMD
 
- VENC_VMOD_VDMD_CASIO
 
- VENC_VMOD_VDMD_EPSON
 
- VENC_VMOD_VDMD_RGB666
 
- VENC_VMOD_VDMD_RGB8
 
- VENC_VMOD_VDMD_SHIFT
 
- VENC_VMOD_VDMD_STNLCD
 
- VENC_VMOD_VDMD_UDISPQVGA
 
- VENC_VMOD_VDMD_YCBCR16
 
- VENC_VMOD_VDMD_YCBCR8
 
- VENC_VMOD_VENC
 
- VENC_VMOD_VIE
 
- VENC_VMOD_VIE_SHIFT
 
- VENC_VMOD_VMD
 
- VENC_VP8_VPU_WORK_BUF_BS_HEADER
 
- VENC_VP8_VPU_WORK_BUF_CHROMA
 
- VENC_VP8_VPU_WORK_BUF_CHROMA2
 
- VENC_VP8_VPU_WORK_BUF_CHROMA3
 
- VENC_VP8_VPU_WORK_BUF_LUMA
 
- VENC_VP8_VPU_WORK_BUF_LUMA2
 
- VENC_VP8_VPU_WORK_BUF_LUMA3
 
- VENC_VP8_VPU_WORK_BUF_MAX
 
- VENC_VP8_VPU_WORK_BUF_MV_INFO
 
- VENC_VP8_VPU_WORK_BUF_PROB_BUF
 
- VENC_VP8_VPU_WORK_BUF_RC_CODE
 
- VENC_VP8_VPU_WORK_BUF_RC_CODE2
 
- VENC_VP8_VPU_WORK_BUF_RC_CODE3
 
- VENC_VP8_VPU_WORK_BUF_RC_INFO
 
- VENC_VSDLY
 
- VENC_VSPLS
 
- VENC_VSTART
 
- VENC_VSTARTA
 
- VENC_VSTAT
 
- VENC_VSTAT_FIDST
 
- VENC_VS_EXT_STOP_X__VS_EXT_START_Y
 
- VENC_VS_EXT_STOP_Y
 
- VENC_VS_INT_START_X
 
- VENC_VS_INT_STOP_X__VS_INT_START_Y
 
- VENC_VS_INT_STOP_Y__VS_EXT_START_X
 
- VENC_VVALID
 
- VENC_WEIGHT_VALUE
 
- VENC_XHINTVL
 
- VENC_X_COLOR
 
- VENC_YCCCTL
 
- VENC_YCOLVL
 
- VENC_YUV_FORMAT_I420
 
- VENC_YUV_FORMAT_NV12
 
- VENC_YUV_FORMAT_NV21
 
- VENC_YUV_FORMAT_YV12
 
- VEND
 
- VEND1_GENERAL_STAT1
 
- VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL
 
- VEND1_GENERAL_STAT1_HIGH_TEMP_WARN
 
- VEND1_GENERAL_STAT1_LOW_TEMP_FAIL
 
- VEND1_GENERAL_STAT1_LOW_TEMP_WARN
 
- VEND1_GLOBAL_FW_ID
 
- VEND1_GLOBAL_FW_ID_MAJOR
 
- VEND1_GLOBAL_FW_ID_MINOR
 
- VEND1_GLOBAL_INT_STD_MASK
 
- VEND1_GLOBAL_INT_STD_MASK_ALL
 
- VEND1_GLOBAL_INT_STD_MASK_AN1
 
- VEND1_GLOBAL_INT_STD_MASK_AN2
 
- VEND1_GLOBAL_INT_STD_MASK_GBE
 
- VEND1_GLOBAL_INT_STD_MASK_PCS1
 
- VEND1_GLOBAL_INT_STD_MASK_PCS2
 
- VEND1_GLOBAL_INT_STD_MASK_PCS3
 
- VEND1_GLOBAL_INT_STD_MASK_PHY_XS1
 
- VEND1_GLOBAL_INT_STD_MASK_PHY_XS2
 
- VEND1_GLOBAL_INT_STD_MASK_PMA1
 
- VEND1_GLOBAL_INT_STD_MASK_PMA2
 
- VEND1_GLOBAL_INT_STD_STATUS
 
- VEND1_GLOBAL_INT_VEND_MASK
 
- VEND1_GLOBAL_INT_VEND_MASK_AN
 
- VEND1_GLOBAL_INT_VEND_MASK_GBE
 
- VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1
 
- VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2
 
- VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3
 
- VEND1_GLOBAL_INT_VEND_MASK_PCS
 
- VEND1_GLOBAL_INT_VEND_MASK_PHY_XS
 
- VEND1_GLOBAL_INT_VEND_MASK_PMA
 
- VEND1_GLOBAL_INT_VEND_STATUS
 
- VEND1_GLOBAL_RSVD_STAT1
 
- VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID
 
- VEND1_GLOBAL_RSVD_STAT1_PROV_ID
 
- VEND1_GLOBAL_RSVD_STAT9
 
- VEND1_GLOBAL_RSVD_STAT9_1000BT2
 
- VEND1_GLOBAL_RSVD_STAT9_MODE
 
- VEND1_THERMAL_PROV_HIGH_TEMP_FAIL
 
- VEND1_THERMAL_PROV_HIGH_TEMP_WARN
 
- VEND1_THERMAL_PROV_LOW_TEMP_FAIL
 
- VEND1_THERMAL_PROV_LOW_TEMP_WARN
 
- VEND1_THERMAL_STAT1
 
- VEND1_THERMAL_STAT2
 
- VEND1_THERMAL_STAT2_VALID
 
- VENDOR
 
- VENDORIDREG
 
- VENDORID_IBM
 
- VENDOR_3COM
 
- VENDOR_ABOCOM
 
- VENDOR_ACCTON
 
- VENDOR_ADAPTEC
 
- VENDOR_ADMTEK
 
- VENDOR_AEILAB
 
- VENDOR_ALLIEDTEL
 
- VENDOR_ATEN
 
- VENDOR_BEHRINGER
 
- VENDOR_BELKIN
 
- VENDOR_BILLIONTON
 
- VENDOR_BLOCK
 
- VENDOR_BN
 
- VENDOR_CAP_LIST__CAP_ID_MASK
 
- VENDOR_CAP_LIST__CAP_ID__MASK
 
- VENDOR_CAP_LIST__CAP_ID__SHIFT
 
- VENDOR_CAP_LIST__LENGTH_MASK
 
- VENDOR_CAP_LIST__LENGTH__MASK
 
- VENDOR_CAP_LIST__LENGTH__SHIFT
 
- VENDOR_CAP_LIST__NEXT_PTR_MASK
 
- VENDOR_CAP_LIST__NEXT_PTR__MASK
 
- VENDOR_CAP_LIST__NEXT_PTR__SHIFT
 
- VENDOR_CCD
 
- VENDOR_CHIPIO_8051_ADDRESS_HIGH
 
- VENDOR_CHIPIO_8051_ADDRESS_LOW
 
- VENDOR_CHIPIO_8051_DATA_READ
 
- VENDOR_CHIPIO_8051_DATA_WRITE
 
- VENDOR_CHIPIO_8051_IRAM_READ
 
- VENDOR_CHIPIO_8051_IRAM_WRITE
 
- VENDOR_CHIPIO_8051_PMEM_READ
 
- VENDOR_CHIPIO_8051_READ_DIRECT
 
- VENDOR_CHIPIO_8051_WRITE_DIRECT
 
- VENDOR_CHIPIO_ADDRESS_HIGH
 
- VENDOR_CHIPIO_ADDRESS_LOW
 
- VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE
 
- VENDOR_CHIPIO_CT_EXTENSIONS_GET
 
- VENDOR_CHIPIO_DATA_HIGH
 
- VENDOR_CHIPIO_DATA_LOW
 
- VENDOR_CHIPIO_DMIC_CTL_GET
 
- VENDOR_CHIPIO_DMIC_CTL_SET
 
- VENDOR_CHIPIO_DMIC_MCLK_GET
 
- VENDOR_CHIPIO_DMIC_MCLK_SET
 
- VENDOR_CHIPIO_DMIC_PIN_GET
 
- VENDOR_CHIPIO_DMIC_PIN_SET
 
- VENDOR_CHIPIO_EAPD_SEL_SET
 
- VENDOR_CHIPIO_FLAGS_GET
 
- VENDOR_CHIPIO_FLAG_SET
 
- VENDOR_CHIPIO_GET_PARAMETER
 
- VENDOR_CHIPIO_HIC_POST_READ
 
- VENDOR_CHIPIO_HIC_READ_DATA
 
- VENDOR_CHIPIO_PARAM_EX_ID_GET
 
- VENDOR_CHIPIO_PARAM_EX_ID_SET
 
- VENDOR_CHIPIO_PARAM_EX_VALUE_GET
 
- VENDOR_CHIPIO_PARAM_EX_VALUE_SET
 
- VENDOR_CHIPIO_PARAM_GET
 
- VENDOR_CHIPIO_PARAM_SET
 
- VENDOR_CHIPIO_PLL_PMU_READ
 
- VENDOR_CHIPIO_PLL_PMU_WRITE
 
- VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET
 
- VENDOR_CHIPIO_PORT_ALLOC_GET
 
- VENDOR_CHIPIO_PORT_ALLOC_SET
 
- VENDOR_CHIPIO_PORT_FREE_SET
 
- VENDOR_CHIPIO_STATUS
 
- VENDOR_CHIPIO_STREAM_FORMAT
 
- VENDOR_CMD_MAX_DATA_LEN
 
- VENDOR_CMD_RAW_DATA
 
- VENDOR_CMND
 
- VENDOR_COMPAQ
 
- VENDOR_COMPRO
 
- VENDOR_CONEXANT
 
- VENDOR_COREGA
 
- VENDOR_DIG
 
- VENDOR_DIGIDESIGN
 
- VENDOR_DIR_IN
 
- VENDOR_DIR_OUT
 
- VENDOR_DLINK
 
- VENDOR_DSPIO_DSP_INIT
 
- VENDOR_DSPIO_SCP_POST_COUNT_QUERY
 
- VENDOR_DSPIO_SCP_POST_READ_DATA
 
- VENDOR_DSPIO_SCP_READ_COUNT
 
- VENDOR_DSPIO_SCP_READ_DATA
 
- VENDOR_DSPIO_SCP_WRITE_DATA_HIGH
 
- VENDOR_DSPIO_SCP_WRITE_DATA_LOW
 
- VENDOR_DSPIO_STATUS
 
- VENDOR_ECHO
 
- VENDOR_ECS
 
- VENDOR_ELCON
 
- VENDOR_ELECOM
 
- VENDOR_ELSA
 
- VENDOR_ENHANCED_STROBE
 
- VENDOR_ESA
 
- VENDOR_FIC
 
- VENDOR_FINTEK
 
- VENDOR_FORMOSA
 
- VENDOR_GAISLER
 
- VENDOR_GAMESTER
 
- VENDOR_GATEWAY
 
- VENDOR_GIBSON
 
- VENDOR_GIGABYTE
 
- VENDOR_GRIFFIN
 
- VENDOR_GROUP
 
- VENDOR_HAUPPAUGE
 
- VENDOR_HAWKING
 
- VENDOR_HP
 
- VENDOR_HT_CAPAB_OUI_TYPE
 
- VENDOR_ID
 
- VENDOR_ID1
 
- VENDOR_ID1_VAL
 
- VENDOR_ID2
 
- VENDOR_ID2_VAL
 
- VENDOR_ID_CYPRESS
 
- VENDOR_ID_DAZZLE
 
- VENDOR_ID_DELORME
 
- VENDOR_ID_FINTEK
 
- VENDOR_ID_FRWD
 
- VENDOR_ID_GTCO
 
- VENDOR_ID_LEN
 
- VENDOR_ID_LENOVO
 
- VENDOR_ID_LINKSYS
 
- VENDOR_ID_LONGSHINE
 
- VENDOR_ID_MELCO
 
- VENDOR_ID_MICRONET
 
- VENDOR_ID_MICROSOFT
 
- VENDOR_ID_MOTOROLA
 
- VENDOR_ID_NIKON
 
- VENDOR_ID_NOKIA
 
- VENDOR_ID_NVIDIA
 
- VENDOR_ID_OQO
 
- VENDOR_ID_PENTAX
 
- VENDOR_ID_POWERCOM
 
- VENDOR_ID_REALTEK
 
- VENDOR_ID_REG
 
- VENDOR_ID_SAMSUNG
 
- VENDOR_ID_STRING_ENABLE
 
- VENDOR_ID_TPLINK
 
- VENDOR_ID_ZYXEL
 
- VENDOR_ID__VENDOR_ID_MASK
 
- VENDOR_ID__VENDOR_ID__MASK
 
- VENDOR_ID__VENDOR_ID__SHIFT
 
- VENDOR_IODATA
 
- VENDOR_ITRON
 
- VENDOR_JH
 
- VENDOR_KINGSTON
 
- VENDOR_LACIE
 
- VENDOR_LANEED
 
- VENDOR_LG
 
- VENDOR_LINKSYS
 
- VENDOR_LINKSYS2
 
- VENDOR_LOUD
 
- VENDOR_MELCO
 
- VENDOR_MICROSOFT
 
- VENDOR_MITSUMI
 
- VENDOR_MOBILITY
 
- VENDOR_NEC
 
- VENDOR_NETGEAR
 
- VENDOR_NORTHSTAR
 
- VENDOR_OCT
 
- VENDOR_OPENCORES
 
- VENDOR_PCTV
 
- VENDOR_PENDER
 
- VENDOR_PHILIPS
 
- VENDOR_PINNACLE
 
- VENDOR_PRIM
 
- VENDOR_READ_LENGTH
 
- VENDOR_READ_REQUEST
 
- VENDOR_READ_REQUEST_TYPE
 
- VENDOR_REALTEK
 
- VENDOR_REQUEST_IN
 
- VENDOR_REQUEST_TYPE
 
- VENDOR_RICAVISION
 
- VENDOR_SCSI3
 
- VENDOR_SHUTTLE
 
- VENDOR_SHUTTLE2
 
- VENDOR_SIEMENS
 
- VENDOR_SMARTBRIDGES
 
- VENDOR_SMC
 
- VENDOR_SMK
 
- VENDOR_SOHOWARE
 
- VENDOR_SPECIFIC
 
- VENDOR_SPECIFIC_BIST
 
- VENDOR_SPECIFIC_CDB
 
- VENDOR_SPECIFIC_COMMANDS
 
- VENDOR_SPECIFIC_PWRCTL_CLEAR_REG
 
- VENDOR_SPECIFIC_PWRCTL_CTL_REG
 
- VENDOR_SPECIFIC_REG_POINTER
 
- VENDOR_STATUS_CHIPIO_BUSY
 
- VENDOR_STATUS_CHIPIO_OK
 
- VENDOR_STATUS_DSPIO_BUSY
 
- VENDOR_STATUS_DSPIO_OK
 
- VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL
 
- VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY
 
- VENDOR_STRING_READ
 
- VENDOR_TASCAM
 
- VENDOR_TATUNG
 
- VENDOR_TIMEOUT
 
- VENDOR_TIVO
 
- VENDOR_TOPSEED
 
- VENDOR_TOSHIBA
 
- VENDOR_TWISTEDMELON
 
- VENDOR_UNIQUE_FIS
 
- VENDOR_V_22
 
- VENDOR_V_23
 
- VENDOR_WISTRON
 
- VENDOR_WRITER
 
- VENDOR_WRITE_REQUEST
 
- VENDOR_WRITE_REQUEST_TYPE
 
- VENETF_LOOP
 
- VENETF_LRO
 
- VENETF_RSS
 
- VENETF_RSSHASH_IPV4
 
- VENETF_RSSHASH_IPV6
 
- VENETF_RSSHASH_IPV6_EX
 
- VENETF_RSSHASH_TCPIPV4
 
- VENETF_RSSHASH_TCPIPV6
 
- VENETF_RSSHASH_TCPIPV6_EX
 
- VENETF_RXCSUM
 
- VENETF_TSO
 
- VENETF_TXCSUM
 
- VENETF_VXLAN
 
- VENET_INTR_MODE_ANY
 
- VENET_INTR_MODE_INTX
 
- VENET_INTR_MODE_MSI
 
- VENET_INTR_TYPE_IDLE
 
- VENET_INTR_TYPE_MIN
 
- VENTURA_SERIES
 
- VENUM_EVENT
 
- VENUS0_AHB_CLK
 
- VENUS0_AXI_CLK
 
- VENUS0_CORE0_GDSC
 
- VENUS0_CORE0_VCODEC_CLK
 
- VENUS0_CORE1_GDSC
 
- VENUS0_CORE1_VCODEC_CLK
 
- VENUS0_GDSC
 
- VENUS0_OCMEMNOC_CLK
 
- VENUS0_RESET
 
- VENUS0_VCODEC0_CLK
 
- VENUS_CORE0_GDSC
 
- VENUS_CORE1_GDSC
 
- VENUS_DEC_STATE_CAPTURE_SETUP
 
- VENUS_DEC_STATE_DECODING
 
- VENUS_DEC_STATE_DEINIT
 
- VENUS_DEC_STATE_DRAIN
 
- VENUS_DEC_STATE_DRC
 
- VENUS_DEC_STATE_INIT
 
- VENUS_DEC_STATE_SEEK
 
- VENUS_DEC_STATE_STOPPED
 
- VENUS_FW_MEM_SIZE
 
- VENUS_FW_START_ADDR
 
- VENUS_GDSC
 
- VENUS_PAS_ID
 
- VENUS_RGB_META_SCANLINES
 
- VENUS_RGB_META_STRIDE
 
- VENUS_RGB_SCANLINES
 
- VENUS_RGB_STRIDE
 
- VENUS_STATE_DEINIT
 
- VENUS_STATE_INIT
 
- VENUS_UV_META_SCANLINES
 
- VENUS_UV_META_STRIDE
 
- VENUS_UV_SCANLINES
 
- VENUS_UV_STRIDE
 
- VENUS_Y_META_SCANLINES
 
- VENUS_Y_META_STRIDE
 
- VENUS_Y_SCANLINES
 
- VENUS_Y_STRIDE
 
- VENV_ATTACK
 
- VENV_BEFORE
 
- VENV_DONE
 
- VENV_RELEASE
 
- VENV_SUSTAIN
 
- VENV_VOLUME
 
- VEN_ACOUSTIC
 
- VEN_APOGEE
 
- VEN_BEHRINGER
 
- VEN_BRIDGECO
 
- VEN_CME
 
- VEN_DIGIDESIGN
 
- VEN_EDIROL
 
- VEN_ESI
 
- VEN_FOCUSRITE
 
- VEN_ICON
 
- VEN_ID_LEN
 
- VEN_IPI_MSG_ENC_STATE_ERROR
 
- VEN_IPI_MSG_ENC_STATE_FRAME
 
- VEN_IPI_MSG_ENC_STATE_PART
 
- VEN_IPI_MSG_ENC_STATE_SKIP
 
- VEN_LYNX
 
- VEN_MACKIE1
 
- VEN_MACKIE2
 
- VEN_MAUDIO1
 
- VEN_MAUDIO2
 
- VEN_PHONIC
 
- VEN_PRESONUS
 
- VEN_PRISMSOUND
 
- VEN_STANTON
 
- VEN_TASCAM
 
- VEN_TERRATEC
 
- VEN_YAMAHA
 
- VEOF
 
- VEOL
 
- VEOL2
 
- VEPU_JPEG_QUANT_TABLE_COUNT
 
- VEPU_QP_ADJUST_MAD_DELTA_ROI
 
- VEPU_REG_1MV_PENALTY
 
- VEPU_REG_4MV_PENALTY
 
- VEPU_REG_ADDR_CABAC_TBL
 
- VEPU_REG_ADDR_IN_PLANE_0
 
- VEPU_REG_ADDR_IN_PLANE_1
 
- VEPU_REG_ADDR_IN_PLANE_2
 
- VEPU_REG_ADDR_MV_OUT
 
- VEPU_REG_ADDR_NEXT_PIC
 
- VEPU_REG_ADDR_OUTPUT_CTRL
 
- VEPU_REG_ADDR_OUTPUT_STREAM
 
- VEPU_REG_ADDR_REC_CHROMA
 
- VEPU_REG_ADDR_REC_LUMA
 
- VEPU_REG_ADDR_REF_CHROMA
 
- VEPU_REG_ADDR_REF_LUMA
 
- VEPU_REG_ADDR_VP8_DCT_PART
 
- VEPU_REG_ADDR_VP8_PROB_CNT
 
- VEPU_REG_ADDR_VP8_SEG_MAP
 
- VEPU_REG_AXI_CTRL
 
- VEPU_REG_AXI_CTRL_BIRST_DISABLE
 
- VEPU_REG_AXI_CTRL_BIRST_DISCARD
 
- VEPU_REG_AXI_CTRL_BURST_LEN
 
- VEPU_REG_AXI_CTRL_INCREMENT_MODE
 
- VEPU_REG_AXI_CTRL_READ_ID
 
- VEPU_REG_AXI_CTRL_WRITE_ID
 
- VEPU_REG_CABAC_INIT_IDC
 
- VEPU_REG_CHECKPOINT
 
- VEPU_REG_CHECKPOINT_CHECK0
 
- VEPU_REG_CHECKPOINT_CHECK1
 
- VEPU_REG_CHECKPOINT_RESULT
 
- VEPU_REG_CHKPT_DELTA_QP
 
- VEPU_REG_CHKPT_DELTA_QP_CHK0
 
- VEPU_REG_CHKPT_DELTA_QP_CHK1
 
- VEPU_REG_CHKPT_DELTA_QP_CHK2
 
- VEPU_REG_CHKPT_DELTA_QP_CHK3
 
- VEPU_REG_CHKPT_DELTA_QP_CHK4
 
- VEPU_REG_CHKPT_DELTA_QP_CHK5
 
- VEPU_REG_CHKPT_DELTA_QP_CHK6
 
- VEPU_REG_CHKPT_WORD_ERR
 
- VEPU_REG_CHKPT_WORD_ERR_CHK0
 
- VEPU_REG_CHKPT_WORD_ERR_CHK1
 
- VEPU_REG_CHROMA_QP_OFFSET
 
- VEPU_REG_CIR_INTRA_CTRL
 
- VEPU_REG_CIR_INTRA_FIRST_MB
 
- VEPU_REG_CIR_INTRA_INTERVAL
 
- VEPU_REG_CLK_GATING_EN
 
- VEPU_REG_COMPLETED_SLICES
 
- VEPU_REG_CONSTRAINED_INTRA_PREDICTION
 
- VEPU_REG_DATA_ENDIAN
 
- VEPU_REG_DEBLOCKING_FILTER_MODE
 
- VEPU_REG_DISABLE_QUARTER_PIXEL_MV
 
- VEPU_REG_DMV_PENALTY_TABLE_BIT
 
- VEPU_REG_DMV_PENALTY_TBL
 
- VEPU_REG_DMV_Q_PIXEL_PENALTY_TABLE_BIT
 
- VEPU_REG_DMV_Q_PIXEL_PENALTY_TBL
 
- VEPU_REG_ENCODE_ENABLE
 
- VEPU_REG_ENCODE_FORMAT_H264
 
- VEPU_REG_ENCODE_FORMAT_JPEG
 
- VEPU_REG_ENCODE_START
 
- VEPU_REG_ENC_CTRL0
 
- VEPU_REG_ENC_CTRL1
 
- VEPU_REG_ENC_CTRL2
 
- VEPU_REG_ENC_CTRL3
 
- VEPU_REG_ENC_CTRL4
 
- VEPU_REG_ENC_OVER_FILL_STRM_OFFSET
 
- VEPU_REG_ENTROPY_CODING_MODE
 
- VEPU_REG_FILTER_DISABLE
 
- VEPU_REG_FRAME_NUM
 
- VEPU_REG_FRAME_TYPE_INTER
 
- VEPU_REG_FRAME_TYPE_INTRA
 
- VEPU_REG_FRAME_TYPE_MVCINTER
 
- VEPU_REG_H264_CHKPT_DISTANCE
 
- VEPU_REG_H264_INTER4X4_MODE
 
- VEPU_REG_H264_LUMA_INIT_QP
 
- VEPU_REG_H264_QP_MAX
 
- VEPU_REG_H264_QP_MIN
 
- VEPU_REG_H264_SLICE_SIZE
 
- VEPU_REG_H264_STREAM_MODE
 
- VEPU_REG_H264_TRANS8X8_MODE
 
- VEPU_REG_IDR_PIC_ID
 
- VEPU_REG_INPUT_LUMA_INFO
 
- VEPU_REG_INPUT_SWAP16
 
- VEPU_REG_INPUT_SWAP32
 
- VEPU_REG_INPUT_SWAP8
 
- VEPU_REG_INTERRUPT
 
- VEPU_REG_INTERRUPT_BIT
 
- VEPU_REG_INTERRUPT_BUFFER_FULL
 
- VEPU_REG_INTERRUPT_BUS_ERROR
 
- VEPU_REG_INTERRUPT_DIS_BIT
 
- VEPU_REG_INTERRUPT_FRAME_READY
 
- VEPU_REG_INTERRUPT_FUSE
 
- VEPU_REG_INTERRUPT_NON
 
- VEPU_REG_INTERRUPT_RESET
 
- VEPU_REG_INTERRUPT_SLICE_READY
 
- VEPU_REG_INTERRUPT_SLICE_READY_EN
 
- VEPU_REG_INTERRUPT_TIMEOUT
 
- VEPU_REG_INTERRUPT_TIMEOUT_EN
 
- VEPU_REG_INTER_MODE
 
- VEPU_REG_INTRA16X16_MODE
 
- VEPU_REG_INTRA_AREA_BOTTOM
 
- VEPU_REG_INTRA_AREA_CTRL
 
- VEPU_REG_INTRA_AREA_LEFT
 
- VEPU_REG_INTRA_AREA_RIGHT
 
- VEPU_REG_INTRA_AREA_TOP
 
- VEPU_REG_INTRA_INTER_MODE
 
- VEPU_REG_INTRA_PRED_MODE
 
- VEPU_REG_INTRA_SLICE_BITMAP
 
- VEPU_REG_IN_IMG_CHROMA_OFFSET
 
- VEPU_REG_IN_IMG_CTRL_FMT
 
- VEPU_REG_IN_IMG_CTRL_OVRFLB
 
- VEPU_REG_IN_IMG_CTRL_OVRFLR_D4
 
- VEPU_REG_IN_IMG_CTRL_ROW_LEN
 
- VEPU_REG_IN_IMG_LUMA_OFFSET
 
- VEPU_REG_IN_IMG_ROTATE_MODE
 
- VEPU_REG_JPEG_CHROMA_QUAT
 
- VEPU_REG_JPEG_LUMA_QUAT
 
- VEPU_REG_MAD_QP_ADJUSTMENT
 
- VEPU_REG_MAD_THRESHOLD
 
- VEPU_REG_MB_CNT_OUT
 
- VEPU_REG_MB_CNT_SET
 
- VEPU_REG_MB_CTRL
 
- VEPU_REG_MB_HEIGHT
 
- VEPU_REG_MB_WIDTH
 
- VEPU_REG_MVC_ANCHOR_PIC_FLAG
 
- VEPU_REG_MVC_INTER_VIEW_FLAG
 
- VEPU_REG_MVC_PRIORITY_ID
 
- VEPU_REG_MVC_RELATE
 
- VEPU_REG_MVC_TEMPORAL_ID
 
- VEPU_REG_MVC_VIEW_ID
 
- VEPU_REG_MV_PENALTY
 
- VEPU_REG_MV_PENALTY_16X8_8X16
 
- VEPU_REG_MV_PENALTY_8X4_4X8
 
- VEPU_REG_MV_PENALTY_8X8
 
- VEPU_REG_MV_WRITE_EN
 
- VEPU_REG_OUTPUT_SWAP16
 
- VEPU_REG_OUTPUT_SWAP32
 
- VEPU_REG_OUTPUT_SWAP8
 
- VEPU_REG_PENALTY_4X4MV
 
- VEPU_REG_PPS_ID
 
- VEPU_REG_PPS_INIT_QP
 
- VEPU_REG_QMV_PENALTY
 
- VEPU_REG_QP_SUM
 
- VEPU_REG_QP_SUM_DIV2
 
- VEPU_REG_QP_VAL
 
- VEPU_REG_RECON_WRITE_DIS
 
- VEPU_REG_RGB2YUV_CONVERSION_COEF1
 
- VEPU_REG_RGB2YUV_CONVERSION_COEF2
 
- VEPU_REG_RGB2YUV_CONVERSION_COEF3
 
- VEPU_REG_RGB2YUV_CONVERSION_COEFA
 
- VEPU_REG_RGB2YUV_CONVERSION_COEFB
 
- VEPU_REG_RGB2YUV_CONVERSION_COEFC
 
- VEPU_REG_RGB2YUV_CONVERSION_COEFE
 
- VEPU_REG_RGB2YUV_CONVERSION_COEFF
 
- VEPU_REG_RGB_MASK_B_MSB
 
- VEPU_REG_RGB_MASK_G_MSB
 
- VEPU_REG_RGB_MASK_MSB
 
- VEPU_REG_RGB_MASK_R_MSB
 
- VEPU_REG_RLC_SUM
 
- VEPU_REG_RLC_SUM_OUT
 
- VEPU_REG_ROI1
 
- VEPU_REG_ROI1_BOTTOM_MB
 
- VEPU_REG_ROI1_LEFT_MB
 
- VEPU_REG_ROI1_RIGHT_MB
 
- VEPU_REG_ROI1_TOP_MB
 
- VEPU_REG_ROI2
 
- VEPU_REG_ROI2_BOTTOM_MB
 
- VEPU_REG_ROI2_LEFT_MB
 
- VEPU_REG_ROI2_RIGHT_MB
 
- VEPU_REG_ROI2_TOP_MB
 
- VEPU_REG_ROI_QP_DELTA_1
 
- VEPU_REG_ROI_QP_DELTA_2
 
- VEPU_REG_SIZE_TABLE_PRESENT
 
- VEPU_REG_SKIP_MACROBLOCK_PENALTY
 
- VEPU_REG_SLICE_FILTER_ALPHA
 
- VEPU_REG_SLICE_FILTER_BETA
 
- VEPU_REG_SPLIT_MV_MODE_EN
 
- VEPU_REG_SPLIT_PENALTY_4X4
 
- VEPU_REG_STABILIZATION_OUTPUT
 
- VEPU_REG_STABLE_HOR_GMV
 
- VEPU_REG_STABLE_MATRIX
 
- VEPU_REG_STABLE_MIN_VALUE
 
- VEPU_REG_STABLE_MODE_SEL
 
- VEPU_REG_STABLE_MOTION_SUM
 
- VEPU_REG_STREAM_START_OFFSET
 
- VEPU_REG_STR_BUF_LIMIT
 
- VEPU_REG_STR_HDR_REM_LSB
 
- VEPU_REG_STR_HDR_REM_MSB
 
- VEPU_REG_TEST_COUNTER
 
- VEPU_REG_TEST_IRQ
 
- VEPU_REG_TEST_LEN
 
- VEPU_REG_TEST_MEMORY
 
- VEPU_REG_TEST_REG
 
- VEPU_REG_VP8_BOOL_ENC_RANGE
 
- VEPU_REG_VP8_BOOL_ENC_VALUE
 
- VEPU_REG_VP8_BOOL_ENC_VALUE_BITS
 
- VEPU_REG_VP8_COEF_DMV_PENALTY
 
- VEPU_REG_VP8_CONTROL
 
- VEPU_REG_VP8_DCT_PARTITION_CNT
 
- VEPU_REG_VP8_DEQUT_AC_CHR
 
- VEPU_REG_VP8_DEQUT_AC_Y1
 
- VEPU_REG_VP8_DEQUT_AC_Y2
 
- VEPU_REG_VP8_DEQUT_DC_CHR
 
- VEPU_REG_VP8_DEQUT_DC_Y1
 
- VEPU_REG_VP8_DEQUT_DC_Y2
 
- VEPU_REG_VP8_ENC_CTRL2
 
- VEPU_REG_VP8_FILTER_LEVEL
 
- VEPU_REG_VP8_FILTER_SHARPNESS
 
- VEPU_REG_VP8_INTER_TYPE_BIT_COST
 
- VEPU_REG_VP8_INTRA_16X16_PENALTY
 
- VEPU_REG_VP8_INTRA_16X16_PENALTY_0
 
- VEPU_REG_VP8_INTRA_16X16_PENALTY_1
 
- VEPU_REG_VP8_INTRA_4X4_PENALTY
 
- VEPU_REG_VP8_INTRA_4X4_PENALTY_0
 
- VEPU_REG_VP8_INTRA_4x4_PENALTY_1
 
- VEPU_REG_VP8_LF_MODE_DELTA_BPRED
 
- VEPU_REG_VP8_LF_MODE_DELTA_NEWMV
 
- VEPU_REG_VP8_LF_MODE_DELTA_SPLITMV
 
- VEPU_REG_VP8_LF_MODE_DELTA_ZEROMV
 
- VEPU_REG_VP8_LF_REF_DELTA_ALT_REF
 
- VEPU_REG_VP8_LF_REF_DELTA_GOLDEN
 
- VEPU_REG_VP8_LF_REF_DELTA_INTRA_MB
 
- VEPU_REG_VP8_LF_REF_DELTA_LAST_REF
 
- VEPU_REG_VP8_LOOP_FILTER_MODE_DELTA
 
- VEPU_REG_VP8_LOOP_FILTER_REF_DELTA
 
- VEPU_REG_VP8_MV_REF_IDX1
 
- VEPU_REG_VP8_MV_REF_IDX2
 
- VEPU_REG_VP8_MV_REF_IDX2_EN
 
- VEPU_REG_VP8_QUT_1ST
 
- VEPU_REG_VP8_QUT_2ND
 
- VEPU_REG_VP8_QUT_3RD
 
- VEPU_REG_VP8_QUT_4TH
 
- VEPU_REG_VP8_QUT_5TH
 
- VEPU_REG_VP8_QUT_6TH
 
- VEPU_REG_VP8_QUT_7TH
 
- VEPU_REG_VP8_QUT_8TH
 
- VEPU_REG_VP8_QUT_9TH
 
- VEPU_REG_VP8_QUT_AC_CHR
 
- VEPU_REG_VP8_QUT_AC_Y1
 
- VEPU_REG_VP8_QUT_AC_Y2
 
- VEPU_REG_VP8_QUT_DC_CHR
 
- VEPU_REG_VP8_QUT_DC_Y1
 
- VEPU_REG_VP8_QUT_DC_Y2
 
- VEPU_REG_VP8_QUT_RND_AC_CHR
 
- VEPU_REG_VP8_QUT_RND_AC_Y1
 
- VEPU_REG_VP8_QUT_RND_AC_Y2
 
- VEPU_REG_VP8_QUT_RND_DC_CHR
 
- VEPU_REG_VP8_QUT_RND_DC_Y1
 
- VEPU_REG_VP8_QUT_RND_DC_Y2
 
- VEPU_REG_VP8_QUT_ZB_AC_CHR
 
- VEPU_REG_VP8_QUT_ZB_AC_Y1
 
- VEPU_REG_VP8_QUT_ZB_AC_Y2
 
- VEPU_REG_VP8_QUT_ZB_DC_CHR
 
- VEPU_REG_VP8_QUT_ZB_DC_Y1
 
- VEPU_REG_VP8_QUT_ZB_DC_Y2
 
- VEPU_REG_VP8_REF_FRAME
 
- VEPU_REG_VP8_REF_FRAME_VAL
 
- VEPU_REG_VP8_SEG0_DQUT_AC_CHR
 
- VEPU_REG_VP8_SEG0_DQUT_AC_Y1
 
- VEPU_REG_VP8_SEG0_DQUT_AC_Y2
 
- VEPU_REG_VP8_SEG0_DQUT_DC_CHR
 
- VEPU_REG_VP8_SEG0_DQUT_DC_Y1
 
- VEPU_REG_VP8_SEG0_DQUT_DC_Y2
 
- VEPU_REG_VP8_SEG0_QUANT_AC_CHR
 
- VEPU_REG_VP8_SEG0_QUANT_AC_Y1
 
- VEPU_REG_VP8_SEG0_QUANT_AC_Y2
 
- VEPU_REG_VP8_SEG0_QUANT_DC_CHR
 
- VEPU_REG_VP8_SEG0_QUANT_DC_Y1
 
- VEPU_REG_VP8_SEG0_QUANT_DC_Y2
 
- VEPU_REG_VP8_SEG0_QUANT_DQUT
 
- VEPU_REG_VP8_SEG0_QUANT_DQUT_1
 
- VEPU_REG_VP8_SEG0_QUT_AC_CHR
 
- VEPU_REG_VP8_SEG0_QUT_AC_Y1
 
- VEPU_REG_VP8_SEG0_QUT_AC_Y2
 
- VEPU_REG_VP8_SEG0_QUT_DC_CHR
 
- VEPU_REG_VP8_SEG0_QUT_DC_Y1
 
- VEPU_REG_VP8_SEG0_QUT_DC_Y2
 
- VEPU_REG_VP8_SEG0_RND_AC_CHR
 
- VEPU_REG_VP8_SEG0_RND_AC_Y1
 
- VEPU_REG_VP8_SEG0_RND_AC_Y2
 
- VEPU_REG_VP8_SEG0_RND_DC_CHR
 
- VEPU_REG_VP8_SEG0_RND_DC_Y1
 
- VEPU_REG_VP8_SEG0_RND_DC_Y2
 
- VEPU_REG_VP8_SEG0_ZBIN_AC_CHR
 
- VEPU_REG_VP8_SEG0_ZBIN_AC_Y1
 
- VEPU_REG_VP8_SEG0_ZBIN_AC_Y2
 
- VEPU_REG_VP8_SEG0_ZBIN_DC_CHR
 
- VEPU_REG_VP8_SEG0_ZBIN_DC_Y1
 
- VEPU_REG_VP8_SEG0_ZBIN_DC_Y2
 
- VEPU_REG_VP8_SEGMENT_EN
 
- VEPU_REG_VP8_SEGMENT_MAP_UPDATE
 
- VEPU_REG_VP8_SEG_FILTER_LEVEL
 
- VEPU_REG_VP8_SPLIT_PENALTY_4X4
 
- VEPU_REG_VP8_ZERO_MV_PENALTY_FOR_REF2
 
- VEPU_REG_ZERO_MV_FAVOR_D2
 
- VER
 
- VERASE
 
- VERB
 
- VERBLEVEL_DEFAULT
 
- VERBLEVEL_SENSORS
 
- VERBOSE
 
- VERBOSE_ACCEPT
 
- VERBOSE_DEBUG
 
- VERBOSE_PERFOUT_ERRSTRING
 
- VERBOSE_PERFOUT_STRING
 
- VERBOSE_STATUS
 
- VERBOSE_SYM53C500_DEBUG
 
- VERBOSE_TOROUT_ERRSTRING
 
- VERBOSE_TOROUT_STRING
 
- VERBS_TXREQ_GFP
 
- VERB_CMD
 
- VERDE_GB_ADDR_CONFIG_GOLDEN
 
- VERDE_MC_UCODE_SIZE
 
- VERDE_NUM_CRTC
 
- VERDE_SMC_UCODE_SIZE
 
- VERDE_SMC_UCODE_START
 
- VERIFY
 
- VERIFYING_FIRMWARE_SIGNATURE
 
- VERIFYING_KEXEC_PE_SIGNATURE
 
- VERIFYING_KEY_SELF_SIGNATURE
 
- VERIFYING_KEY_SIGNATURE
 
- VERIFYING_MODULE_SIGNATURE
 
- VERIFYING_UNSPECIFIED_SIGNATURE
 
- VERIFY_12
 
- VERIFY_16
 
- VERIFY_32
 
- VERIFY_CAP_FRAME
 
- VERIFY_CAP_LOCAL_FABRIC
 
- VERIFY_CAP_LOCAL_LINK_MODE
 
- VERIFY_CAP_LOCAL_PHY
 
- VERIFY_CAP_REMOTE_FABRIC
 
- VERIFY_CAP_REMOTE_LINK_WIDTH
 
- VERIFY_CAP_REMOTE_PHY
 
- VERIFY_CHIP_IOCB_TYPE
 
- VERIFY_CMPL_SZ
 
- VERIFY_CSUM_OK
 
- VERIFY_HEADER_NOK
 
- VERIFY_HEADER_OK
 
- VERIFY_HW
 
- VERIFY_OCTAL_PERMISSIONS
 
- VERIFY_OFFSET
 
- VERIFY_PERCPU_PTR
 
- VERIFY_REQ_SZ
 
- VERIFY_SW
 
- VERIFY_SYSTEM_PASSWORD
 
- VERIFY_USER_PASSWORD
 
- VERIFY_USE_PLATFORM_KEYRING
 
- VERIFY_USE_SECONDARY_KEYRING
 
- VERMAGIC_STRING
 
- VERROR
 
- VERR_ACCESS_DENIED
 
- VERR_ADDRESS_CONFLICT
 
- VERR_ALREADY_EXISTS
 
- VERR_ALREADY_LOADED
 
- VERR_ASSOC_ALLOC_FAIL
 
- VERR_ASSOC_ID
 
- VERR_ASSOC_ID_LEN
 
- VERR_BAD_EXE_FORMAT
 
- VERR_BROKEN_PIPE
 
- VERR_BUFFER_OVERFLOW
 
- VERR_CANT_CREATE
 
- VERR_CANT_DELETE_DIRECTORY
 
- VERR_CONN_ID
 
- VERR_CONN_ID_LEN
 
- VERR_CR_ASSOC
 
- VERR_CR_ASSOC_ACC_LEN
 
- VERR_CR_ASSOC_CMD
 
- VERR_CR_ASSOC_CMD_LEN
 
- VERR_CR_ASSOC_LEN
 
- VERR_CR_ASSOC_RQST_LEN
 
- VERR_CR_CONN
 
- VERR_CR_CONN_ACC_LEN
 
- VERR_CR_CONN_CMD
 
- VERR_CR_CONN_CMD_LEN
 
- VERR_CR_CONN_LEN
 
- VERR_CR_CONN_RQST_LEN
 
- VERR_DEADLOCK
 
- VERR_DEV_IO_ERROR
 
- VERR_DIR_NOT_EMPTY
 
- VERR_DISCONN
 
- VERR_DISCONN_ACC_LEN
 
- VERR_DISCONN_CMD
 
- VERR_DISCONN_CMD_LEN
 
- VERR_DISCONN_LEN
 
- VERR_DISCONN_RQST_LEN
 
- VERR_DISCONN_SCOPE
 
- VERR_DISK_FULL
 
- VERR_EOF
 
- VERR_ERSP_RATIO
 
- VERR_FAILED_TO_SET_SELF_TLS
 
- VERR_FILENAME_TOO_LONG
 
- VERR_FILE_LOCK_FAILED
 
- VERR_FILE_LOCK_LOST
 
- VERR_FILE_LOCK_VIOLATION
 
- VERR_FILE_NOT_FOUND
 
- VERR_FILE_NOT_LOCKED
 
- VERR_FILE_TOO_BIG
 
- VERR_GENERAL_FAILURE
 
- VERR_IDT_FAILED
 
- VERR_INTERNAL_ERROR
 
- VERR_INTERNAL_ERROR_2
 
- VERR_INTERNAL_ERROR_3
 
- VERR_INTERNAL_ERROR_4
 
- VERR_INTERRUPTED
 
- VERR_INVALID_CONTEXT
 
- VERR_INVALID_FLAGS
 
- VERR_INVALID_FMODE
 
- VERR_INVALID_FUNCTION
 
- VERR_INVALID_HANDLE
 
- VERR_INVALID_MAGIC
 
- VERR_INVALID_NAME
 
- VERR_INVALID_PARAMETER
 
- VERR_INVALID_POINTER
 
- VERR_INVALID_STATE
 
- VERR_INVALID_UUID_FORMAT
 
- VERR_IO_BAD_LENGTH
 
- VERR_IS_A_DIRECTORY
 
- VERR_LOCK_FAILED
 
- VERR_LSACC
 
- VERR_LSDESC_RQST
 
- VERR_LSDESC_RQST_LEN
 
- VERR_MAX_PROCS_REACHED
 
- VERR_MAX_THRDS_REACHED
 
- VERR_MEDIA_NOT_PRESENT
 
- VERR_MEDIA_NOT_RECOGNIZED
 
- VERR_NEGATIVE_SEEK
 
- VERR_NEGATIVE_UNSIGNED
 
- VERR_NET_ADDRESS_FAMILY_NOT_SUPPORTED
 
- VERR_NET_ADDRESS_IN_USE
 
- VERR_NET_ADDRESS_NOT_AVAILABLE
 
- VERR_NET_ALREADY_CONNECTED
 
- VERR_NET_ALREADY_IN_PROGRESS
 
- VERR_NET_CONNECTION_ABORTED
 
- VERR_NET_CONNECTION_REFUSED
 
- VERR_NET_CONNECTION_RESET
 
- VERR_NET_CONNECTION_RESET_BY_PEER
 
- VERR_NET_CONNECTION_TIMED_OUT
 
- VERR_NET_DEST_ADDRESS_REQUIRED
 
- VERR_NET_DOWN
 
- VERR_NET_HOST_DOWN
 
- VERR_NET_HOST_NOT_FOUND
 
- VERR_NET_HOST_UNREACHABLE
 
- VERR_NET_INCOMPLETE_TX_PACKET
 
- VERR_NET_IN_PROGRESS
 
- VERR_NET_IO_ERROR
 
- VERR_NET_MSG_SIZE
 
- VERR_NET_NOT_CONNECTED
 
- VERR_NET_NOT_SOCKET
 
- VERR_NET_NOT_UNIQUE_NAME
 
- VERR_NET_NO_BUFFER_SPACE
 
- VERR_NET_NO_NETWORK
 
- VERR_NET_OPERATION_NOT_SUPPORTED
 
- VERR_NET_OUT_OF_RESOURCES
 
- VERR_NET_PATH_NOT_FOUND
 
- VERR_NET_PRINT_ERROR
 
- VERR_NET_PROTOCOL_ERROR
 
- VERR_NET_PROTOCOL_FAMILY_NOT_SUPPORTED
 
- VERR_NET_PROTOCOL_NOT_AVAILABLE
 
- VERR_NET_PROTOCOL_NOT_SUPPORTED
 
- VERR_NET_PROTOCOL_TYPE
 
- VERR_NET_SHUTDOWN
 
- VERR_NET_SOCKET_TYPE_NOT_SUPPORTED
 
- VERR_NET_TOO_MANY_REFERENCES
 
- VERR_NET_UNREACHABLE
 
- VERR_NOT_A_DIRECTORY
 
- VERR_NOT_EQUAL
 
- VERR_NOT_FOUND
 
- VERR_NOT_IMPLEMENTED
 
- VERR_NOT_SAME_DEVICE
 
- VERR_NOT_SUPPORTED
 
- VERR_NOT_SYMLINK
 
- VERR_NO_ASSOC
 
- VERR_NO_CONN
 
- VERR_NO_CONT_MEMORY
 
- VERR_NO_DATA
 
- VERR_NO_DIGITS
 
- VERR_NO_ERROR
 
- VERR_NO_MEMORY
 
- VERR_NO_MORE_FILES
 
- VERR_NO_PAGE_MEMORY
 
- VERR_NO_TLS_FOR_SELF
 
- VERR_NO_TMP_MEMORY
 
- VERR_NO_TRANSLATION
 
- VERR_NUMBER_TOO_BIG
 
- VERR_OUT_OF_RANGE
 
- VERR_OUT_OF_RESOURCES
 
- VERR_PAGE_TABLE_NOT_PRESENT
 
- VERR_PARSE_ERROR
 
- VERR_PATH_NOT_FOUND
 
- VERR_PERMISSION_DENIED
 
- VERR_PROCESS_NOT_FOUND
 
- VERR_PROCESS_RUNNING
 
- VERR_QUEUE_ALLOC_FAIL
 
- VERR_READ_ERROR
 
- VERR_RESOURCE_BUSY
 
- VERR_RS_CMD
 
- VERR_RS_CMD_LEN
 
- VERR_RS_LEN
 
- VERR_RS_RCTL
 
- VERR_RS_RO
 
- VERR_RS_RQST_LEN
 
- VERR_SEEK
 
- VERR_SEEK_ON_DEVICE
 
- VERR_SEM_DESTROYED
 
- VERR_SHARING_VIOLATION
 
- VERR_SIGNAL_INVALID
 
- VERR_SIGNAL_PENDING
 
- VERR_SIGNAL_REFUSED
 
- VERR_STATE_CHANGED
 
- VERR_THREAD_IS_DEAD
 
- VERR_THREAD_NOT_WAITABLE
 
- VERR_TIMEOUT
 
- VERR_TIMER_BUSY
 
- VERR_TOO_MANY_OPEN_FILES
 
- VERR_TOO_MANY_SYMLINKS
 
- VERR_TOO_MUCH_DATA
 
- VERR_TRY_AGAIN
 
- VERR_UNRESOLVED_ERROR
 
- VERR_VERSION_MISMATCH
 
- VERR_WRITE_ERROR
 
- VERR_WRITE_PROTECT
 
- VERR_WRONG_ORDER
 
- VERS
 
- VERSATILE_AUX_OSC_BITS
 
- VERSATILE_CLCD
 
- VERSATILE_FLASHPROT
 
- VERSATILE_IB2_BASE
 
- VERSATILE_IB2_CTL_BASE
 
- VERSATILE_LOCK_VAL
 
- VERSATILE_MMCI0_BASE
 
- VERSATILE_MMCI1_BASE
 
- VERSATILE_REBOOT_CM
 
- VERSATILE_REFCLK
 
- VERSATILE_SCTL_BASE
 
- VERSATILE_SYS_FLASH_OFFSET
 
- VERSATILE_SYS_LOCK_OFFSET
 
- VERSATILE_SYS_MCI_OFFSET
 
- VERSATILE_SYS_OSCCLCD_OFFSET
 
- VERSATILE_SYS_PCICTL_OFFSET
 
- VERSATILE_SYS_RESETCTL_OFFSET
 
- VERSATILE_TIMCLK
 
- VERSATILE_TIMER1_EnSel
 
- VERSATILE_TIMER2_EnSel
 
- VERSATILE_TIMER3_EnSel
 
- VERSATILE_TIMER4_EnSel
 
- VERSION
 
- VERSIONPTP_MASK
 
- VERSIONPTP_SHIFT
 
- VERSION_4_OFFLOAD_SIZE
 
- VERSION_8190_BD
 
- VERSION_8190_BE
 
- VERSION_8192S_ACUT
 
- VERSION_8192S_BCUT
 
- VERSION_8192S_CCUT
 
- VERSION_819XU_A
 
- VERSION_819XU_B
 
- VERSION_819XU_C
 
- VERSION_AVC
 
- VERSION_A_CHIP_88C
 
- VERSION_A_CHIP_92C
 
- VERSION_BITS
 
- VERSION_B_CHIP_88C
 
- VERSION_B_CHIP_92C
 
- VERSION_COUNT
 
- VERSION_CURRENT
 
- VERSION_ELEMENTS
 
- VERSION_EXCHANGE
 
- VERSION_EXCHANGE_RSP
 
- VERSION_GT
 
- VERSION_ID_MASK
 
- VERSION_INVAL
 
- VERSION_KERNEL
 
- VERSION_LEN
 
- VERSION_LENGTH
 
- VERSION_LOCK
 
- VERSION_LT
 
- VERSION_MAJOR
 
- VERSION_MASK
 
- VERSION_MAX_LEN
 
- VERSION_MINOR
 
- VERSION_NORMAL_CHIP_2T2R_8192E
 
- VERSION_NORMAL_CHIP_88E
 
- VERSION_NORMAL_CHIP_92D_C_CUT_DUALPHY
 
- VERSION_NORMAL_CHIP_92D_C_CUT_SINGLEPHY
 
- VERSION_NORMAL_CHIP_92D_DUALPHY
 
- VERSION_NORMAL_CHIP_92D_D_CUT_DUALPHY
 
- VERSION_NORMAL_CHIP_92D_D_CUT_SINGLEPHY
 
- VERSION_NORMAL_CHIP_92D_E_CUT_DUALPHY
 
- VERSION_NORMAL_CHIP_92D_E_CUT_SINGLEPHY
 
- VERSION_NORMAL_CHIP_92D_SINGLEPHY
 
- VERSION_NORMAL_SMIC_CHIP_1T1R_8723B
 
- VERSION_NORMAL_TSMC_CHIP_1T1R_8812
 
- VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT
 
- VERSION_NORMAL_TSMC_CHIP_2T2R_8812
 
- VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT
 
- VERSION_NORMAL_TSMC_CHIP_8821
 
- VERSION_NORMAL_TSMC_CHIP_8821_B_CUT
 
- VERSION_NORMAL_TSMC_CHIP_88C
 
- VERSION_NORMAL_TSMC_CHIP_92C
 
- VERSION_NORMAL_TSMC_CHIP_92C_1T2R
 
- VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT
 
- VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT
 
- VERSION_NORMAL_UMC_CHIP_88C_A_CUT
 
- VERSION_NORMAL_UMC_CHIP_88C_B_CUT
 
- VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT
 
- VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT
 
- VERSION_NORMAL_UMC_CHIP_92C_A_CUT
 
- VERSION_NORMAL_UMC_CHIP_92C_B_CUT
 
- VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT
 
- VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT
 
- VERSION_NUMBER
 
- VERSION_OS
 
- VERSION_PATCH
 
- VERSION_SHIFT
 
- VERSION_SIZE
 
- VERSION_SR
 
- VERSION_STR
 
- VERSION_STRING
 
- VERSION_STRING_SIZE
 
- VERSION_TEENIE
 
- VERSION_TEST_CHIP_1T1R_8723B
 
- VERSION_TEST_CHIP_1T1R_8812
 
- VERSION_TEST_CHIP_2T2R_8192E
 
- VERSION_TEST_CHIP_2T2R_8812
 
- VERSION_TEST_CHIP_8821
 
- VERSION_TEST_CHIP_88C
 
- VERSION_TEST_CHIP_88E
 
- VERSION_TEST_CHIP_92C
 
- VERSION_TEST_CHIP_92D_DUALPHY
 
- VERSION_TEST_CHIP_92D_SINGLEPHY
 
- VERSION_TEST_UMC_CHIP_8723
 
- VERSION_UNKNOWN
 
- VERSION_WIN10
 
- VERSION_WIN10_V5
 
- VERSION_WIN7
 
- VERSION_WIN8
 
- VERSION_WIN8_1
 
- VERSION_WS2008
 
- VERSION__A
 
- VERS_IMPL
 
- VERS_MANUF
 
- VERS_MASK
 
- VERS_MAXTL
 
- VERS_MAXWIN
 
- VERTEX_1_ARGB
 
- VERTEX_1_S
 
- VERTEX_1_SECONDARY_S
 
- VERTEX_1_SECONDARY_T
 
- VERTEX_1_SECONDARY_W
 
- VERTEX_1_SPEC_ARGB
 
- VERTEX_1_T
 
- VERTEX_1_W
 
- VERTEX_1_X_Y
 
- VERTEX_1_Z
 
- VERTEX_2_ARGB
 
- VERTEX_2_S
 
- VERTEX_2_SECONDARY_S
 
- VERTEX_2_SECONDARY_T
 
- VERTEX_2_SECONDARY_W
 
- VERTEX_2_SPEC_ARGB
 
- VERTEX_2_T
 
- VERTEX_2_W
 
- VERTEX_2_X_Y
 
- VERTEX_2_Z
 
- VERTEX_3_ARGB
 
- VERTEX_3_S
 
- VERTEX_3_SECONDARY_S
 
- VERTEX_3_SECONDARY_T
 
- VERTEX_3_SECONDARY_W
 
- VERTEX_3_SPEC_ARGB
 
- VERTEX_3_T
 
- VERTEX_3_W
 
- VERTEX_3_X_Y
 
- VERTEX_3_Z
 
- VERTICAL_ADDRESS_MASK
 
- VERTICAL_ADDRESS_SHIFT
 
- VERTICAL_COLOR_BAR_MASK
 
- VERTICAL_TAPS_2
 
- VERTICAL_TAPS_5
 
- VERT_AUTO_RATIO_EN
 
- VERT_AUTO_SCALE
 
- VERT_BACK_PORCH_COUNT_REG
 
- VERT_FP_LOOP_STRETCH
 
- VERT_FRONT_PORCH_COUNT_REG
 
- VERT_INTERP_BILINEAR
 
- VERT_INTERP_DISABLE
 
- VERT_INTERP_MASK
 
- VERT_LEAD_IN_LINES
 
- VERT_MAX_TAPS
 
- VERT_PANEL_SHIFT
 
- VERT_PANEL_SIZE
 
- VERT_SCROLL_CTRL
 
- VERT_SEED
 
- VERT_STRETCHING
 
- VERT_STRETCHING_LG
 
- VERT_STRETCH_BLEND
 
- VERT_STRETCH_EN
 
- VERT_STRETCH_ENABLE
 
- VERT_STRETCH_LINREP
 
- VERT_STRETCH_MODE
 
- VERT_STRETCH_RATIO0
 
- VERT_STRETCH_RATIO1
 
- VERT_STRETCH_RATIO2
 
- VERT_STRETCH_RATIO3
 
- VERT_STRETCH_RATIO_MASK
 
- VERT_STRETCH_RATIO_MAX
 
- VERT_STRETCH_RESERVED
 
- VERT_STRETCH_USE0
 
- VERT_SYNC_END
 
- VERT_SYNC_PAD_COUNT_REG
 
- VERT_TIM_CTRL
 
- VERVE_I2C_ADDRESS
 
- VERYDIRTY
 
- VERY_GOOD
 
- VERY_LOW_EXP
 
- VERY_LOW_PWR_OP
 
- VERY_LOW_RSSI
 
- VERY_VERBOSE
 
- VER_0_1
 
- VER_1_X
 
- VER_2_X
 
- VER_ADDR_1
 
- VER_ADDR_2
 
- VER_ADDR_3
 
- VER_BUILD
 
- VER_CAPI
 
- VER_CARDTYPE
 
- VER_DRIVER
 
- VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC
 
- VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA
 
- VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST
 
- VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM
 
- VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED
 
- VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED
 
- VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED
 
- VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED
 
- VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED
 
- VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED
 
- VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED
 
- VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED
 
- VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED
 
- VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED
 
- VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED
 
- VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED
 
- VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED
 
- VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED
 
- VER_GET_RESP_FLAGS_DEV_NOT_RDY
 
- VER_GET_RESP_FLAGS_EXT_VER_AVAIL
 
- VER_H
 
- VER_HWID
 
- VER_L
 
- VER_LEVEL
 
- VER_LIB_H_ADDR
 
- VER_LIB_L_ADDR
 
- VER_MAJOR
 
- VER_MAJREV_MASK
 
- VER_MASK
 
- VER_MINOR
 
- VER_MINREV_MASK
 
- VER_NUM
 
- VER_OEM
 
- VER_OPTION
 
- VER_PATCH
 
- VER_PROFILE
 
- VER_PROTO
 
- VER_SERIAL
 
- VER_SIZE
 
- VER_STEP
 
- VES
 
- VES1820_H
 
- VES1820_SELAGC_PWM
 
- VES1820_SELAGC_SIGNAMPERR
 
- VES1X93_H
 
- VESA
 
- VESA_HSYNC_SUSPEND
 
- VESA_MAGIC
 
- VESA_MEMORY_IN_64K_BLOCK
 
- VESA_MODEDB_SIZE
 
- VESA_MODE_ATTRIBUTE_MODE_SUPPORT
 
- VESA_MODE_INFO_BLOCK
 
- VESA_MODE_WIN_ATTRIBUTE
 
- VESA_NO_BLANKING
 
- VESA_OEM_PRODUCT_REV
 
- VESA_POWERDOWN
 
- VESA_VSYNC_SUSPEND
 
- VESA_WIN_SIZE
 
- VETH_FEATURES
 
- VETH_INFO_MAX
 
- VETH_INFO_PEER
 
- VETH_INFO_UNSPEC
 
- VETH_MAC_ADDR
 
- VETH_MCAST_FILTER_SIZE
 
- VETH_RING_SIZE
 
- VETH_RQ_STAT
 
- VETH_RQ_STATS_LEN
 
- VETH_XDP_FLAG
 
- VETH_XDP_HEADROOM
 
- VETH_XDP_REDIR
 
- VETH_XDP_TX
 
- VETH_XDP_TX_BULK_SIZE
 
- VEU0
 
- VEU2
 
- VEU2H1_VEU2HI
 
- VEU3F_VE3
 
- VEU_AFXR
 
- VEU_APCR
 
- VEU_BSRR
 
- VEU_BSSR
 
- VEU_CBR
 
- VEU_COFFR
 
- VEU_DACR
 
- VEU_DAYR
 
- VEU_ECCR
 
- VEU_EDWR
 
- VEU_EIER
 
- VEU_ENHR
 
- VEU_EVTR
 
- VEU_FMCR
 
- VEU_HTCR
 
- VEU_MCR00
 
- VEU_MCR01
 
- VEU_MCR02
 
- VEU_MCR10
 
- VEU_MCR11
 
- VEU_MCR12
 
- VEU_MCR20
 
- VEU_MCR21
 
- VEU_MCR22
 
- VEU_RFCR
 
- VEU_RFSR
 
- VEU_SACR
 
- VEU_SAYR
 
- VEU_SSR
 
- VEU_STAR
 
- VEU_STR
 
- VEU_SWPR
 
- VEU_SWR
 
- VEU_TRCR
 
- VEU_VTCR
 
- VEXPRESS_CLCD_V2M
 
- VEXPRESS_FPGAMUX_DAUGHTERBOARD_1
 
- VEXPRESS_FPGAMUX_DAUGHTERBOARD_2
 
- VEXPRESS_FPGAMUX_MOTHERBOARD
 
- VEXPRESS_SITE_DB1
 
- VEXPRESS_SITE_DB2
 
- VEXPRESS_SITE_MASTER
 
- VEXPRESS_SITE_MB
 
- VEXTRA_CLOBBERS
 
- VE_AVC_BASIC_BITS
 
- VE_AVC_CTRL
 
- VE_AVC_MB_INFO
 
- VE_AVC_MOTION_EST
 
- VE_AVC_PARAM
 
- VE_AVC_QP
 
- VE_AVC_REC_CHROMA
 
- VE_AVC_REC_LUMA
 
- VE_AVC_REC_SLUMA
 
- VE_AVC_REF_CHROMA
 
- VE_AVC_REF_LUMA
 
- VE_AVC_REF_SLUMA
 
- VE_AVC_SRAM_PORT_DATA
 
- VE_AVC_SRAM_PORT_OFFSET
 
- VE_AVC_STATUS
 
- VE_AVC_TRIGGER
 
- VE_AVC_UNK_BUF
 
- VE_AVC_VLE_ADDR
 
- VE_AVC_VLE_END
 
- VE_AVC_VLE_LENGTH
 
- VE_AVC_VLE_MAX
 
- VE_AVC_VLE_OFFSET
 
- VE_CAP_WINDOW
 
- VE_CHROMA_BUF_LEN
 
- VE_CHROMA_BUF_LEN_SDRT
 
- VE_COMP_ADDR
 
- VE_COMP_CTRL
 
- VE_COMP_CTRL_DCT_CHR
 
- VE_COMP_CTRL_DCT_LUM
 
- VE_COMP_CTRL_ENCODE
 
- VE_COMP_CTRL_EN_BQ
 
- VE_COMP_CTRL_EN_CRYPTO
 
- VE_COMP_CTRL_EN_HQ
 
- VE_COMP_CTRL_HQ_DCT_CHR
 
- VE_COMP_CTRL_HQ_DCT_LUM
 
- VE_COMP_CTRL_QUANTIZE
 
- VE_COMP_CTRL_RSVD
 
- VE_COMP_CTRL_VQ_4COLOR
 
- VE_COMP_CTRL_VQ_DCT_ONLY
 
- VE_COMP_OFFSET
 
- VE_COMP_PROC_OFFSET
 
- VE_COMP_WINDOW
 
- VE_CTRL
 
- VE_CTRL_AUTO_OR_CURSOR
 
- VE_CTRL_CAPTURE_FMT
 
- VE_CTRL_CLK_DELAY
 
- VE_CTRL_CLK_INVERSE
 
- VE_CTRL_DIRECT_FETCH
 
- VE_CTRL_FRC
 
- VE_CTRL_HSYNC_POL
 
- VE_CTRL_HSYNC_POL_CTRL
 
- VE_CTRL_INTERLACE
 
- VE_CTRL_INT_DE
 
- VE_CTRL_RGB
 
- VE_CTRL_SOURCE
 
- VE_CTRL_VSYNC_POL
 
- VE_CTRL_YUV
 
- VE_DEC_MPEG_BWD_REF_CHROMA_ADDR
 
- VE_DEC_MPEG_BWD_REF_LUMA_ADDR
 
- VE_DEC_MPEG_CRTMBADDR
 
- VE_DEC_MPEG_CTRL
 
- VE_DEC_MPEG_CTRL_ERROR_IRQ_EN
 
- VE_DEC_MPEG_CTRL_FINISH_IRQ_EN
 
- VE_DEC_MPEG_CTRL_IRQ_MASK
 
- VE_DEC_MPEG_CTRL_MC_CACHE_EN
 
- VE_DEC_MPEG_CTRL_MC_NO_WRITEBACK
 
- VE_DEC_MPEG_CTRL_QP_AC_DC_OUT_EN
 
- VE_DEC_MPEG_CTRL_ROTATE_IRQ_EN
 
- VE_DEC_MPEG_CTRL_ROTATE_SCALE_OUT_EN
 
- VE_DEC_MPEG_CTRL_SW_IQ_IS
 
- VE_DEC_MPEG_CTRL_SW_VLD
 
- VE_DEC_MPEG_CTRL_VLD_DATA_REQ_IRQ_EN
 
- VE_DEC_MPEG_ERROR
 
- VE_DEC_MPEG_FWD_REF_CHROMA_ADDR
 
- VE_DEC_MPEG_FWD_REF_LUMA_ADDR
 
- VE_DEC_MPEG_IQMINPUT
 
- VE_DEC_MPEG_IQMINPUT_FLAG_INTRA
 
- VE_DEC_MPEG_IQMINPUT_FLAG_NON_INTRA
 
- VE_DEC_MPEG_IQMINPUT_WEIGHT
 
- VE_DEC_MPEG_MBADDR
 
- VE_DEC_MPEG_MBADDR_X
 
- VE_DEC_MPEG_MBADDR_Y
 
- VE_DEC_MPEG_MP12HDR
 
- VE_DEC_MPEG_MP12HDR_ALTERNATE_SCAN
 
- VE_DEC_MPEG_MP12HDR_CONCEALMENT_MOTION_VECTORS
 
- VE_DEC_MPEG_MP12HDR_FRAME_PRED_FRAME_DCT
 
- VE_DEC_MPEG_MP12HDR_FULL_PEL_BACKWARD_VECTOR
 
- VE_DEC_MPEG_MP12HDR_FULL_PEL_FORWARD_VECTOR
 
- VE_DEC_MPEG_MP12HDR_F_CODE
 
- VE_DEC_MPEG_MP12HDR_F_CODE_SHIFT
 
- VE_DEC_MPEG_MP12HDR_INTRA_DC_PRECISION
 
- VE_DEC_MPEG_MP12HDR_INTRA_PICTURE_STRUCTURE
 
- VE_DEC_MPEG_MP12HDR_INTRA_VLC_FORMAT
 
- VE_DEC_MPEG_MP12HDR_Q_SCALE_TYPE
 
- VE_DEC_MPEG_MP12HDR_SLICE_TYPE
 
- VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST
 
- VE_DEC_MPEG_PICBOUNDSIZE
 
- VE_DEC_MPEG_PICBOUNDSIZE_HEIGHT
 
- VE_DEC_MPEG_PICBOUNDSIZE_WIDTH
 
- VE_DEC_MPEG_PICCODEDSIZE
 
- VE_DEC_MPEG_PICCODEDSIZE_HEIGHT
 
- VE_DEC_MPEG_PICCODEDSIZE_WIDTH
 
- VE_DEC_MPEG_REC_CHROMA
 
- VE_DEC_MPEG_REC_LUMA
 
- VE_DEC_MPEG_ROT_CHROMA
 
- VE_DEC_MPEG_ROT_LUMA
 
- VE_DEC_MPEG_STATUS
 
- VE_DEC_MPEG_STATUS_CHECK_ERROR
 
- VE_DEC_MPEG_STATUS_CHECK_MASK
 
- VE_DEC_MPEG_STATUS_DCAC_BUSY
 
- VE_DEC_MPEG_STATUS_DEBLOCKING_BUSY
 
- VE_DEC_MPEG_STATUS_ERROR
 
- VE_DEC_MPEG_STATUS_IDCT_BUF_EMPTY
 
- VE_DEC_MPEG_STATUS_IDCT_BUSY
 
- VE_DEC_MPEG_STATUS_IQIS_BUF_EMPTY
 
- VE_DEC_MPEG_STATUS_IQIS_BUSY
 
- VE_DEC_MPEG_STATUS_JPEG_BIT_END
 
- VE_DEC_MPEG_STATUS_JPEG_MARKER
 
- VE_DEC_MPEG_STATUS_JPEG_RESTART_ERROR
 
- VE_DEC_MPEG_STATUS_MAF_BUSY
 
- VE_DEC_MPEG_STATUS_MC_BUSY
 
- VE_DEC_MPEG_STATUS_ROTATE_BUSY
 
- VE_DEC_MPEG_STATUS_ROTATE_SUCCESS
 
- VE_DEC_MPEG_STATUS_SCALE_DOWN_BUSY
 
- VE_DEC_MPEG_STATUS_START_DETECT_BUSY
 
- VE_DEC_MPEG_STATUS_SUCCESS
 
- VE_DEC_MPEG_STATUS_VE_BUSY
 
- VE_DEC_MPEG_STATUS_VLD_BUSY
 
- VE_DEC_MPEG_STATUS_VLD_DATA_REQ
 
- VE_DEC_MPEG_STATUS_VP6_BIT
 
- VE_DEC_MPEG_STATUS_VP6_BIT_BUSY
 
- VE_DEC_MPEG_STATUS_VP6_MVP_BUSY
 
- VE_DEC_MPEG_TRIGGER
 
- VE_DEC_MPEG_TRIGGER_CHROMA_FMT_411
 
- VE_DEC_MPEG_TRIGGER_CHROMA_FMT_420
 
- VE_DEC_MPEG_TRIGGER_CHROMA_FMT_422
 
- VE_DEC_MPEG_TRIGGER_CHROMA_FMT_422T
 
- VE_DEC_MPEG_TRIGGER_CHROMA_FMT_444
 
- VE_DEC_MPEG_TRIGGER_HW_JPEG_VLD
 
- VE_DEC_MPEG_TRIGGER_HW_MAF
 
- VE_DEC_MPEG_TRIGGER_HW_MB
 
- VE_DEC_MPEG_TRIGGER_HW_MPEG_VLD
 
- VE_DEC_MPEG_TRIGGER_HW_ROTATE
 
- VE_DEC_MPEG_TRIGGER_HW_STCD_BEGIN
 
- VE_DEC_MPEG_TRIGGER_HW_STCD_END
 
- VE_DEC_MPEG_TRIGGER_HW_VP6_VLD
 
- VE_DEC_MPEG_TRIGGER_JPEG
 
- VE_DEC_MPEG_TRIGGER_MB_BOUNDARY
 
- VE_DEC_MPEG_TRIGGER_MPEG1
 
- VE_DEC_MPEG_TRIGGER_MPEG2
 
- VE_DEC_MPEG_TRIGGER_MPEG4
 
- VE_DEC_MPEG_TRIGGER_STCD_AVC
 
- VE_DEC_MPEG_TRIGGER_STCD_MPEG2
 
- VE_DEC_MPEG_TRIGGER_STCD_VC1
 
- VE_DEC_MPEG_TRIGGER_SW_IDCT
 
- VE_DEC_MPEG_TRIGGER_SW_IQ
 
- VE_DEC_MPEG_TRIGGER_SW_MC
 
- VE_DEC_MPEG_TRIGGER_SW_SCALE
 
- VE_DEC_MPEG_TRIGGER_SW_VP6
 
- VE_DEC_MPEG_TRIGGER_SW_VP62_AC_GET_BITS
 
- VE_DEC_MPEG_TRIGGER_VP62
 
- VE_DEC_MPEG_TRIGGER_VP62_AC_GET_BITS
 
- VE_DEC_MPEG_VLD_ADDR
 
- VE_DEC_MPEG_VLD_ADDR_BASE
 
- VE_DEC_MPEG_VLD_ADDR_FIRST_PIC_DATA
 
- VE_DEC_MPEG_VLD_ADDR_LAST_PIC_DATA
 
- VE_DEC_MPEG_VLD_ADDR_VALID_PIC_DATA
 
- VE_DEC_MPEG_VLD_END_ADDR
 
- VE_DEC_MPEG_VLD_LEN
 
- VE_DEC_MPEG_VLD_OFFSET
 
- VE_ENGINE_DEC_H264
 
- VE_ENGINE_DEC_MPEG
 
- VE_H264_BASIC_BITS
 
- VE_H264_CTRL
 
- VE_H264_CTRL_DECODE_ERR_INT
 
- VE_H264_CTRL_INT_MASK
 
- VE_H264_CTRL_SLICE_DECODE_INT
 
- VE_H264_CTRL_VLD_DATA_REQ_INT
 
- VE_H264_CUR_MB_NUM
 
- VE_H264_EXTRA_BUFFER1
 
- VE_H264_EXTRA_BUFFER2
 
- VE_H264_OUTPUT_FRAME_IDX
 
- VE_H264_PPS
 
- VE_H264_PPS_CONSTRAINED_INTRA_PRED
 
- VE_H264_PPS_ENTROPY_CODING_MODE
 
- VE_H264_PPS_TRANSFORM_8X8_MODE
 
- VE_H264_PPS_WEIGHTED_PRED
 
- VE_H264_SDROT_CTRL
 
- VE_H264_SHS
 
- VE_H264_SHS2
 
- VE_H264_SHS2_NUM_REF_IDX_ACTIVE_OVRD
 
- VE_H264_SHS_BOTTOM_FIELD
 
- VE_H264_SHS_DIRECT_SPATIAL_MV_PRED
 
- VE_H264_SHS_FIELD_PIC
 
- VE_H264_SHS_FIRST_SLICE_IN_PIC
 
- VE_H264_SHS_QP
 
- VE_H264_SHS_QP_SCALING_MATRIX_DEFAULT
 
- VE_H264_SHS_WP
 
- VE_H264_SPS
 
- VE_H264_SPS_DIRECT_8X8_INFERENCE
 
- VE_H264_SPS_MBS_ONLY
 
- VE_H264_SPS_MB_ADAPTIVE_FRAME_FIELD
 
- VE_H264_STATUS
 
- VE_H264_STATUS_DECODE_ERR_INT
 
- VE_H264_STATUS_INT_MASK
 
- VE_H264_STATUS_SLICE_DECODE_INT
 
- VE_H264_STATUS_VLD_DATA_REQ_INT
 
- VE_H264_TRIGGER_TYPE
 
- VE_H264_TRIGGER_TYPE_AVC_SLICE_DECODE
 
- VE_H264_TRIGGER_TYPE_INIT_SWDEC
 
- VE_H264_VLD_ADDR
 
- VE_H264_VLD_ADDR_FIRST
 
- VE_H264_VLD_ADDR_LAST
 
- VE_H264_VLD_ADDR_VAL
 
- VE_H264_VLD_ADDR_VALID
 
- VE_H264_VLD_END
 
- VE_H264_VLD_LEN
 
- VE_H264_VLD_OFFSET
 
- VE_INTERRUPT_CAPTURE_COMPLETE
 
- VE_INTERRUPT_COMP_COMPLETE
 
- VE_INTERRUPT_COMP_READY
 
- VE_INTERRUPT_CTRL
 
- VE_INTERRUPT_DECODE_ERR
 
- VE_INTERRUPT_FRAME_COMPLETE
 
- VE_INTERRUPT_HALT_READY
 
- VE_INTERRUPT_HANG_WD
 
- VE_INTERRUPT_MODE_DETECT
 
- VE_INTERRUPT_MODE_DETECT_WD
 
- VE_INTERRUPT_STATUS
 
- VE_INTERRUPT_STREAM_DESC
 
- VE_INTERRUPT_VSYNC_DESC
 
- VE_ISP_CTRL
 
- VE_ISP_INPUT_CHROMA
 
- VE_ISP_INPUT_LUMA
 
- VE_ISP_INPUT_SIZE
 
- VE_ISP_INPUT_STRIDE
 
- VE_JPEG_ADDR
 
- VE_JPEG_HEADER_SIZE
 
- VE_MAX_SRC_BUFFER_SIZE
 
- VE_MBOX_REG
 
- VE_MEM_REG
 
- VE_MEM_RESTRICT_END
 
- VE_MEM_RESTRICT_START
 
- VE_MODE
 
- VE_MODE_DDR_MODE_BW_128
 
- VE_MODE_DDR_MODE_BW_256
 
- VE_MODE_DEC_H264
 
- VE_MODE_DEC_H265
 
- VE_MODE_DEC_MPEG
 
- VE_MODE_DETECT
 
- VE_MODE_DETECT_H_PIXELS
 
- VE_MODE_DETECT_STATUS
 
- VE_MODE_DETECT_STATUS_HSYNC
 
- VE_MODE_DETECT_STATUS_VSYNC
 
- VE_MODE_DETECT_V_LINES
 
- VE_MODE_DETECT_V_LINES_SHF
 
- VE_MODE_DISABLED
 
- VE_MODE_REC_WR_MODE_1MB
 
- VE_MODE_REC_WR_MODE_2MB
 
- VE_OFFSET_COMP_STREAM
 
- VE_PRIMARY_CHROMA_BUF_LEN
 
- VE_PRIMARY_FB_LINE_STRIDE
 
- VE_PRIMARY_FB_LINE_STRIDE_CHROMA
 
- VE_PRIMARY_FB_LINE_STRIDE_LUMA
 
- VE_PRIMARY_OUT_FMT
 
- VE_PRIMARY_OUT_FMT_NV12
 
- VE_PRIMARY_OUT_FMT_NV21
 
- VE_PRIMARY_OUT_FMT_TILED_128_NV12
 
- VE_PRIMARY_OUT_FMT_TILED_32_NV12
 
- VE_PRIMARY_OUT_FMT_YU12
 
- VE_PRIMARY_OUT_FMT_YV12
 
- VE_PROTECTION_KEY
 
- VE_PROTECTION_KEY_UNLOCK
 
- VE_SCALING_FACTOR
 
- VE_SCALING_FILTER0
 
- VE_SCALING_FILTER1
 
- VE_SCALING_FILTER2
 
- VE_SCALING_FILTER3
 
- VE_SECONDARY_OUT_FMT_EXT
 
- VE_SECONDARY_OUT_FMT_EXT_NV12
 
- VE_SECONDARY_OUT_FMT_EXT_NV21
 
- VE_SECONDARY_OUT_FMT_EXT_TILED_128_NV12
 
- VE_SECONDARY_OUT_FMT_EXT_TILED_32_NV12
 
- VE_SECONDARY_OUT_FMT_EXT_YU12
 
- VE_SECONDARY_OUT_FMT_EXT_YV12
 
- VE_SECONDARY_OUT_FMT_TILED_32_NV12
 
- VE_SECONDARY_OUT_FMT_YU12
 
- VE_SECONDARY_OUT_FMT_YV12
 
- VE_SEQ_CTRL
 
- VE_SEQ_CTRL_AUTO_COMP
 
- VE_SEQ_CTRL_CAP_BUSY
 
- VE_SEQ_CTRL_COMP_BUSY
 
- VE_SEQ_CTRL_COMP_FMT
 
- VE_SEQ_CTRL_EN_WATCHDOG
 
- VE_SEQ_CTRL_EN_WATCHDOG_COMP
 
- VE_SEQ_CTRL_FORCE_IDLE
 
- VE_SEQ_CTRL_HALT
 
- VE_SEQ_CTRL_JPEG_MODE
 
- VE_SEQ_CTRL_MULT_FRAME
 
- VE_SEQ_CTRL_TRIG_CAPTURE
 
- VE_SEQ_CTRL_TRIG_COMP
 
- VE_SEQ_CTRL_TRIG_JPG
 
- VE_SEQ_CTRL_TRIG_MODE_DET
 
- VE_SEQ_CTRL_YUV420
 
- VE_SLP_REG
 
- VE_SRC0_ADDR
 
- VE_SRC1_ADDR
 
- VE_SRC_LR_EDGE_DET
 
- VE_SRC_LR_EDGE_DET_INTERLACE
 
- VE_SRC_LR_EDGE_DET_LEFT
 
- VE_SRC_LR_EDGE_DET_NO_CLK
 
- VE_SRC_LR_EDGE_DET_NO_DISP
 
- VE_SRC_LR_EDGE_DET_NO_H
 
- VE_SRC_LR_EDGE_DET_NO_V
 
- VE_SRC_LR_EDGE_DET_RT
 
- VE_SRC_LR_EDGE_DET_RT_SHF
 
- VE_SRC_SCANLINE_OFFSET
 
- VE_SRC_TB_EDGE_DET
 
- VE_SRC_TB_EDGE_DET_BOT
 
- VE_SRC_TB_EDGE_DET_BOT_SHF
 
- VE_SRC_TB_EDGE_DET_TOP
 
- VE_STREAM_BUF_SIZE
 
- VE_STREAM_BUF_SIZE_N_PACKETS
 
- VE_STREAM_BUF_SIZE_P_SIZE
 
- VE_SYNC_STATUS
 
- VE_SYNC_STATUS_HSYNC
 
- VE_SYNC_STATUS_VSYNC
 
- VE_SYNC_STATUS_VSYNC_SHF
 
- VE_TGS_0
 
- VE_TGS_1
 
- VE_TGS_FIRST
 
- VE_TGS_LAST
 
- VE_VECTOR
 
- VE_VERSION
 
- VE_VERSION_SHIFT
 
- VF610_ADCIOC_ADACK_SET
 
- VF610_ADCIOC_ALTCLK_SET
 
- VF610_ADCIOC_BUSCLK_SET
 
- VF610_ADCIOC_VR_VALT_SET
 
- VF610_ADCIOC_VR_VBG_SET
 
- VF610_ADCIOC_VR_VREF_SET
 
- VF610_ADCK_CYCLES_13
 
- VF610_ADCK_CYCLES_17
 
- VF610_ADCK_CYCLES_21
 
- VF610_ADCK_CYCLES_25
 
- VF610_ADCK_CYCLES_3
 
- VF610_ADCK_CYCLES_5
 
- VF610_ADCK_CYCLES_7
 
- VF610_ADCK_CYCLES_9
 
- VF610_ADC_ACFE
 
- VF610_ADC_ACFGT
 
- VF610_ADC_ACREN
 
- VF610_ADC_ADACKEN
 
- VF610_ADC_ADACK_SEL
 
- VF610_ADC_ADCCLK_MASK
 
- VF610_ADC_ADCHC
 
- VF610_ADC_ADCON
 
- VF610_ADC_ADHSC_EN
 
- VF610_ADC_ADLPC_EN
 
- VF610_ADC_ADLSMP_LONG
 
- VF610_ADC_ADSTS_LONG
 
- VF610_ADC_ADSTS_MASK
 
- VF610_ADC_ADSTS_NORMAL
 
- VF610_ADC_ADSTS_SHORT
 
- VF610_ADC_ADTRG_HARD
 
- VF610_ADC_AIEN
 
- VF610_ADC_ALTCLK_SEL
 
- VF610_ADC_AVGEN
 
- VF610_ADC_AVGS_16
 
- VF610_ADC_AVGS_32
 
- VF610_ADC_AVGS_8
 
- VF610_ADC_AVGS_MASK
 
- VF610_ADC_BUSCLK2_SEL
 
- VF610_ADC_CAL
 
- VF610_ADC_CALF
 
- VF610_ADC_CHAN
 
- VF610_ADC_CLK_DIV2
 
- VF610_ADC_CLK_DIV4
 
- VF610_ADC_CLK_DIV8
 
- VF610_ADC_CLK_MASK
 
- VF610_ADC_CONV_DISABLE
 
- VF610_ADC_CONV_HIGH_SPEED
 
- VF610_ADC_CONV_LOW_POWER
 
- VF610_ADC_CONV_NORMAL
 
- VF610_ADC_DMAEN
 
- VF610_ADC_HS_COCO0
 
- VF610_ADC_MODE_BIT10
 
- VF610_ADC_MODE_BIT12
 
- VF610_ADC_MODE_BIT8
 
- VF610_ADC_MODE_MASK
 
- VF610_ADC_OVWREN
 
- VF610_ADC_REFSEL_VALT
 
- VF610_ADC_REFSEL_VBG
 
- VF610_ADC_SAMPLE_1
 
- VF610_ADC_SAMPLE_16
 
- VF610_ADC_SAMPLE_32
 
- VF610_ADC_SAMPLE_4
 
- VF610_ADC_SAMPLE_8
 
- VF610_ADC_TEMPERATURE_CHAN
 
- VF610_ADC_TIMEOUT
 
- VF610_CLK_ADC0
 
- VF610_CLK_ADC1
 
- VF610_CLK_ANACLK1
 
- VF610_CLK_ASRC
 
- VF610_CLK_AUDIO_EXT
 
- VF610_CLK_DAC0
 
- VF610_CLK_DAC1
 
- VF610_CLK_DAP
 
- VF610_CLK_DCU0
 
- VF610_CLK_DCU0_DIV
 
- VF610_CLK_DCU0_EN
 
- VF610_CLK_DCU0_SEL
 
- VF610_CLK_DCU1
 
- VF610_CLK_DCU1_DIV
 
- VF610_CLK_DCU1_EN
 
- VF610_CLK_DCU1_SEL
 
- VF610_CLK_DDRMC
 
- VF610_CLK_DDR_SEL
 
- VF610_CLK_DMAMUX0
 
- VF610_CLK_DMAMUX1
 
- VF610_CLK_DMAMUX2
 
- VF610_CLK_DMAMUX3
 
- VF610_CLK_DSPI0
 
- VF610_CLK_DSPI1
 
- VF610_CLK_DSPI2
 
- VF610_CLK_DSPI3
 
- VF610_CLK_DUMMY
 
- VF610_CLK_END
 
- VF610_CLK_ENET
 
- VF610_CLK_ENET0
 
- VF610_CLK_ENET1
 
- VF610_CLK_ENET_25M
 
- VF610_CLK_ENET_50M
 
- VF610_CLK_ENET_EXT
 
- VF610_CLK_ENET_SEL
 
- VF610_CLK_ENET_TS
 
- VF610_CLK_ENET_TS_SEL
 
- VF610_CLK_ESAI
 
- VF610_CLK_ESAI_DIV
 
- VF610_CLK_ESAI_EN
 
- VF610_CLK_ESAI_SEL
 
- VF610_CLK_ESDHC0
 
- VF610_CLK_ESDHC0_DIV
 
- VF610_CLK_ESDHC0_EN
 
- VF610_CLK_ESDHC0_SEL
 
- VF610_CLK_ESDHC1
 
- VF610_CLK_ESDHC1_DIV
 
- VF610_CLK_ESDHC1_EN
 
- VF610_CLK_ESDHC1_SEL
 
- VF610_CLK_FASK_CLK_SEL
 
- VF610_CLK_FIRC
 
- VF610_CLK_FLEXCAN0
 
- VF610_CLK_FLEXCAN0_EN
 
- VF610_CLK_FLEXCAN1
 
- VF610_CLK_FLEXCAN1_EN
 
- VF610_CLK_FTM0
 
- VF610_CLK_FTM0_EXT_FIX_EN
 
- VF610_CLK_FTM0_EXT_SEL
 
- VF610_CLK_FTM0_FIX_SEL
 
- VF610_CLK_FTM1
 
- VF610_CLK_FTM1_EXT_FIX_EN
 
- VF610_CLK_FTM1_EXT_SEL
 
- VF610_CLK_FTM1_FIX_SEL
 
- VF610_CLK_FTM2
 
- VF610_CLK_FTM2_EXT_FIX_EN
 
- VF610_CLK_FTM2_EXT_SEL
 
- VF610_CLK_FTM2_FIX_SEL
 
- VF610_CLK_FTM3
 
- VF610_CLK_FTM3_EXT_FIX_EN
 
- VF610_CLK_FTM3_EXT_SEL
 
- VF610_CLK_FTM3_FIX_SEL
 
- VF610_CLK_FXOSC
 
- VF610_CLK_FXOSC_HALF
 
- VF610_CLK_GPU2D
 
- VF610_CLK_GPU_EN
 
- VF610_CLK_GPU_SEL
 
- VF610_CLK_I2C0
 
- VF610_CLK_I2C1
 
- VF610_CLK_I2C2
 
- VF610_CLK_I2C3
 
- VF610_CLK_IPG_BUS
 
- VF610_CLK_LVDS1_IN
 
- VF610_CLK_NFC
 
- VF610_CLK_NFC_EN
 
- VF610_CLK_NFC_FRAC_DIV
 
- VF610_CLK_NFC_INV
 
- VF610_CLK_NFC_PRE_DIV
 
- VF610_CLK_NFC_SEL
 
- VF610_CLK_OCOTP
 
- VF610_CLK_PIT
 
- VF610_CLK_PLATFORM_BUS
 
- VF610_CLK_PLL1
 
- VF610_CLK_PLL1_BYPASS_SRC
 
- VF610_CLK_PLL1_PFD1
 
- VF610_CLK_PLL1_PFD2
 
- VF610_CLK_PLL1_PFD3
 
- VF610_CLK_PLL1_PFD4
 
- VF610_CLK_PLL1_PFD_SEL
 
- VF610_CLK_PLL1_SYS
 
- VF610_CLK_PLL2
 
- VF610_CLK_PLL2_BUS
 
- VF610_CLK_PLL2_BYPASS_SRC
 
- VF610_CLK_PLL2_PFD1
 
- VF610_CLK_PLL2_PFD2
 
- VF610_CLK_PLL2_PFD3
 
- VF610_CLK_PLL2_PFD4
 
- VF610_CLK_PLL2_PFD_SEL
 
- VF610_CLK_PLL3
 
- VF610_CLK_PLL3_BYPASS_SRC
 
- VF610_CLK_PLL3_MAIN_DIV
 
- VF610_CLK_PLL3_PFD1
 
- VF610_CLK_PLL3_PFD2
 
- VF610_CLK_PLL3_PFD3
 
- VF610_CLK_PLL3_PFD4
 
- VF610_CLK_PLL3_USB_OTG
 
- VF610_CLK_PLL4
 
- VF610_CLK_PLL4_AUDIO
 
- VF610_CLK_PLL4_BYPASS_SRC
 
- VF610_CLK_PLL4_MAIN_DIV
 
- VF610_CLK_PLL5
 
- VF610_CLK_PLL5_BYPASS_SRC
 
- VF610_CLK_PLL5_ENET
 
- VF610_CLK_PLL6
 
- VF610_CLK_PLL6_BYPASS_SRC
 
- VF610_CLK_PLL6_MAIN_DIV
 
- VF610_CLK_PLL6_VIDEO
 
- VF610_CLK_PLL7
 
- VF610_CLK_PLL7_BYPASS_SRC
 
- VF610_CLK_PLL7_USB_HOST
 
- VF610_CLK_QSPI0
 
- VF610_CLK_QSPI0_EN
 
- VF610_CLK_QSPI0_SEL
 
- VF610_CLK_QSPI0_X1_DIV
 
- VF610_CLK_QSPI0_X2_DIV
 
- VF610_CLK_QSPI0_X4_DIV
 
- VF610_CLK_QSPI1
 
- VF610_CLK_QSPI1_EN
 
- VF610_CLK_QSPI1_SEL
 
- VF610_CLK_QSPI1_X1_DIV
 
- VF610_CLK_QSPI1_X2_DIV
 
- VF610_CLK_QSPI1_X4_DIV
 
- VF610_CLK_SAI0
 
- VF610_CLK_SAI0_DIV
 
- VF610_CLK_SAI0_EN
 
- VF610_CLK_SAI0_SEL
 
- VF610_CLK_SAI1
 
- VF610_CLK_SAI1_DIV
 
- VF610_CLK_SAI1_EN
 
- VF610_CLK_SAI1_SEL
 
- VF610_CLK_SAI2
 
- VF610_CLK_SAI2_DIV
 
- VF610_CLK_SAI2_EN
 
- VF610_CLK_SAI2_SEL
 
- VF610_CLK_SAI3
 
- VF610_CLK_SAI3_DIV
 
- VF610_CLK_SAI3_EN
 
- VF610_CLK_SAI3_SEL
 
- VF610_CLK_SIRC_128K
 
- VF610_CLK_SIRC_32K
 
- VF610_CLK_SLOW_CLK_SEL
 
- VF610_CLK_SNVS
 
- VF610_CLK_SXOSC
 
- VF610_CLK_SYS_BUS
 
- VF610_CLK_SYS_SEL
 
- VF610_CLK_TCON0
 
- VF610_CLK_TCON1
 
- VF610_CLK_UART0
 
- VF610_CLK_UART1
 
- VF610_CLK_UART2
 
- VF610_CLK_UART3
 
- VF610_CLK_UART4
 
- VF610_CLK_UART5
 
- VF610_CLK_USBC0
 
- VF610_CLK_USBC1
 
- VF610_CLK_USBPHY0
 
- VF610_CLK_USBPHY1
 
- VF610_CLK_VADC
 
- VF610_CLK_VADC_DIV
 
- VF610_CLK_VADC_DIV_HALF
 
- VF610_CLK_VADC_EN
 
- VF610_CLK_VADC_SEL
 
- VF610_CLK_WDT
 
- VF610_CLK_WKPU
 
- VF610_DAC_CHAN
 
- VF610_DAC_CONV_HIGH_POWER
 
- VF610_DAC_CONV_LOW_POWER
 
- VF610_DAC_DACEN
 
- VF610_DAC_DACRFS
 
- VF610_DAC_DAT0
 
- VF610_DAC_LPEN
 
- VF610_DACx_STATCTRL
 
- VF610_GPIO_PER_PORT
 
- VF610_I2C
 
- VF610_I2C_REGSHIFT
 
- VF610_LAYER_REG_NUM
 
- VF610_LPUART
 
- VF610_OCOTP_TIMEOUT
 
- VF610_OVER_CUR_DIS
 
- VF610_PAD_PTA10
 
- VF610_PAD_PTA10__DCU0_G0
 
- VF610_PAD_PTA10__ENET_TS_CLKIN
 
- VF610_PAD_PTA10__EXT_AUDIO_MCLK
 
- VF610_PAD_PTA10__GPIO_3
 
- VF610_PAD_PTA10__MLB_SIGNAL
 
- VF610_PAD_PTA10__TDO
 
- VF610_PAD_PTA11
 
- VF610_PAD_PTA11__DCU0_G1
 
- VF610_PAD_PTA11__GPIO_4
 
- VF610_PAD_PTA11__MLB_DATA
 
- VF610_PAD_PTA11__TMS
 
- VF610_PAD_PTA12
 
- VF610_PAD_PTA12__EXT_AUDIO_MCLK
 
- VF610_PAD_PTA12__GPIO_5
 
- VF610_PAD_PTA12__I2C0_SCL
 
- VF610_PAD_PTA12__TRACECK
 
- VF610_PAD_PTA12__VIU_DATA13
 
- VF610_PAD_PTA16
 
- VF610_PAD_PTA16__ADC1_SE0
 
- VF610_PAD_PTA16__GPIO_6
 
- VF610_PAD_PTA16__I2C0_SDA
 
- VF610_PAD_PTA16__LCD29
 
- VF610_PAD_PTA16__SAI2_TX_BCLK
 
- VF610_PAD_PTA16__TRACED0
 
- VF610_PAD_PTA16__USB0_VBUS_EN
 
- VF610_PAD_PTA16__VIU_DATA14
 
- VF610_PAD_PTA17
 
- VF610_PAD_PTA17__ADC1_SE1
 
- VF610_PAD_PTA17__GPIO_7
 
- VF610_PAD_PTA17__I2C1_SCL
 
- VF610_PAD_PTA17__LCD30
 
- VF610_PAD_PTA17__TRACED1
 
- VF610_PAD_PTA17__USB0_SOF_PULSE
 
- VF610_PAD_PTA17__USB0_VBUS_OC
 
- VF610_PAD_PTA17__VIU_DATA15
 
- VF610_PAD_PTA18
 
- VF610_PAD_PTA18__ADC0_SE0
 
- VF610_PAD_PTA18__FTM1_QD_PHA
 
- VF610_PAD_PTA18__GPIO_8
 
- VF610_PAD_PTA18__I2C1_SDA
 
- VF610_PAD_PTA18__LCD31
 
- VF610_PAD_PTA18__SAI2_TX_DATA
 
- VF610_PAD_PTA18__TRACED2
 
- VF610_PAD_PTA18__VIU_DATA16
 
- VF610_PAD_PTA19
 
- VF610_PAD_PTA19__ADC0_SE1
 
- VF610_PAD_PTA19__FTM1_QD_PHB
 
- VF610_PAD_PTA19__GPIO_9
 
- VF610_PAD_PTA19__LCD32
 
- VF610_PAD_PTA19__QSPI1_A_QSCK
 
- VF610_PAD_PTA19__SAI2_TX_SYNC
 
- VF610_PAD_PTA19__TRACED3
 
- VF610_PAD_PTA19__VIU_DATA17
 
- VF610_PAD_PTA20
 
- VF610_PAD_PTA20__DCU1_HSYNC
 
- VF610_PAD_PTA20__GPIO_10
 
- VF610_PAD_PTA20__LCD33
 
- VF610_PAD_PTA20__TRACED4
 
- VF610_PAD_PTA20__UART3_TX
 
- VF610_PAD_PTA21
 
- VF610_PAD_PTA21__DCU1_VSYNC
 
- VF610_PAD_PTA21__GPIO_11
 
- VF610_PAD_PTA21__SAI2_RX_BCLK
 
- VF610_PAD_PTA21__TRACED5
 
- VF610_PAD_PTA21__UART3_RX
 
- VF610_PAD_PTA22
 
- VF610_PAD_PTA22__DCU1_TAG
 
- VF610_PAD_PTA22__GPIO_12
 
- VF610_PAD_PTA22__I2C2_SCL
 
- VF610_PAD_PTA22__SAI2_RX_DATA
 
- VF610_PAD_PTA22__TRACED6
 
- VF610_PAD_PTA23
 
- VF610_PAD_PTA23__DCU1_DE
 
- VF610_PAD_PTA23__GPIO_13
 
- VF610_PAD_PTA23__I2C2_SDA
 
- VF610_PAD_PTA23__SAI2_RX_SYNC
 
- VF610_PAD_PTA23__TRACED7
 
- VF610_PAD_PTA24
 
- VF610_PAD_PTA24__DCU1_TCON4
 
- VF610_PAD_PTA24__DDR_TEST_PAD_CTRL
 
- VF610_PAD_PTA24__ESDHC1_CLK
 
- VF610_PAD_PTA24__GPIO_14
 
- VF610_PAD_PTA24__TRACED8
 
- VF610_PAD_PTA24__USB1_VBUS_EN
 
- VF610_PAD_PTA25
 
- VF610_PAD_PTA25__DCU1_TCON5
 
- VF610_PAD_PTA25__ESDHC1_CMD
 
- VF610_PAD_PTA25__GPIO_15
 
- VF610_PAD_PTA25__TRACED9
 
- VF610_PAD_PTA25__USB1_VBUS_OC
 
- VF610_PAD_PTA26
 
- VF610_PAD_PTA26__DCU1_TCON6
 
- VF610_PAD_PTA26__ESDHC1_DAT0
 
- VF610_PAD_PTA26__GPIO_16
 
- VF610_PAD_PTA26__SAI3_TX_BCLK
 
- VF610_PAD_PTA26__TRACED10
 
- VF610_PAD_PTA27
 
- VF610_PAD_PTA27__DCU1_TCON7
 
- VF610_PAD_PTA27__ESDHC1_DAT1
 
- VF610_PAD_PTA27__GPIO_17
 
- VF610_PAD_PTA27__SAI3_RX_BCLK
 
- VF610_PAD_PTA27__TRACED11
 
- VF610_PAD_PTA28
 
- VF610_PAD_PTA28__DCU1_TCON8
 
- VF610_PAD_PTA28__ENET1_1588_TMR0
 
- VF610_PAD_PTA28__ESDHC1_DATA2
 
- VF610_PAD_PTA28__GPIO_18
 
- VF610_PAD_PTA28__SAI3_RX_DATA
 
- VF610_PAD_PTA28__TRACED12
 
- VF610_PAD_PTA28__UART4_TX
 
- VF610_PAD_PTA29
 
- VF610_PAD_PTA29__DCU1_TCON9
 
- VF610_PAD_PTA29__ENET1_1588_TMR1
 
- VF610_PAD_PTA29__ESDHC1_DAT3
 
- VF610_PAD_PTA29__GPIO_19
 
- VF610_PAD_PTA29__SAI3_TX_DATA
 
- VF610_PAD_PTA29__TRACED13
 
- VF610_PAD_PTA29__UART4_RX
 
- VF610_PAD_PTA30
 
- VF610_PAD_PTA30__ENET1_1588_TMR2
 
- VF610_PAD_PTA30__GPIO_20
 
- VF610_PAD_PTA30__I2C3_SCL
 
- VF610_PAD_PTA30__SAI3_RX_SYNC
 
- VF610_PAD_PTA30__TRACED14
 
- VF610_PAD_PTA30__UART3_TX
 
- VF610_PAD_PTA30__UART4_RTS
 
- VF610_PAD_PTA31
 
- VF610_PAD_PTA31__ENET1_1588_TMR3
 
- VF610_PAD_PTA31__GPIO_21
 
- VF610_PAD_PTA31__I2C3_SDA
 
- VF610_PAD_PTA31__SAI3_TX_SYNC
 
- VF610_PAD_PTA31__TRACED15
 
- VF610_PAD_PTA31__UART3_RX
 
- VF610_PAD_PTA31__UART4_CTS
 
- VF610_PAD_PTA6
 
- VF610_PAD_PTA6__DCU1_R2
 
- VF610_PAD_PTA6__DCU1_TCON11
 
- VF610_PAD_PTA6__GPIO_0
 
- VF610_PAD_PTA6__RMII_CLKIN
 
- VF610_PAD_PTA6__RMII_CLKOUT
 
- VF610_PAD_PTA7
 
- VF610_PAD_PTA7__GPIO_134
 
- VF610_PAD_PTA7__VIU_PIX_CLK
 
- VF610_PAD_PTA8
 
- VF610_PAD_PTA8__DCU0_R0
 
- VF610_PAD_PTA8__GPIO_1
 
- VF610_PAD_PTA8__MLB_CLK
 
- VF610_PAD_PTA8__TCLK
 
- VF610_PAD_PTA9
 
- VF610_PAD_PTA9__DCU0_R1
 
- VF610_PAD_PTA9__GPIO_2
 
- VF610_PAD_PTA9__RMII_CLKIN
 
- VF610_PAD_PTA9__RMII_CLKOUT
 
- VF610_PAD_PTA9__TDI
 
- VF610_PAD_PTA9__WDOG_B
 
- VF610_PAD_PTB0
 
- VF610_PAD_PTB0__ADC0_SE2
 
- VF610_PAD_PTB0__FTM0_CH0
 
- VF610_PAD_PTB0__GPIO_22
 
- VF610_PAD_PTB0__LCD34
 
- VF610_PAD_PTB0__QSPI1_A_QPCS0
 
- VF610_PAD_PTB0__SAI2_RX_BCLK
 
- VF610_PAD_PTB0__TRACE_CTL
 
- VF610_PAD_PTB0__VIU_DATA18
 
- VF610_PAD_PTB1
 
- VF610_PAD_PTB10
 
- VF610_PAD_PTB10__CKO1
 
- VF610_PAD_PTB10__DCU0_TCON4
 
- VF610_PAD_PTB10__ENET_TS_CLKIN
 
- VF610_PAD_PTB10__GPIO_32
 
- VF610_PAD_PTB10__UART0_TX
 
- VF610_PAD_PTB10__VIU_DE
 
- VF610_PAD_PTB11
 
- VF610_PAD_PTB11_ENET0_1588_TMR0
 
- VF610_PAD_PTB11__CKO2
 
- VF610_PAD_PTB11__DCU0_TCON5
 
- VF610_PAD_PTB11__GPIO_33
 
- VF610_PAD_PTB11__SNVS_ALARM_OUT_B
 
- VF610_PAD_PTB11__UART0_RX
 
- VF610_PAD_PTB12
 
- VF610_PAD_PTB12__DCU0_TCON6
 
- VF610_PAD_PTB12__DSPI0_CS5
 
- VF610_PAD_PTB12__ENET0_1588_TMR1
 
- VF610_PAD_PTB12__FB_AD1
 
- VF610_PAD_PTB12__GPIO_34
 
- VF610_PAD_PTB12__NMI
 
- VF610_PAD_PTB12__UART0_RTS
 
- VF610_PAD_PTB13
 
- VF610_PAD_PTB13__DCU0_TCON7
 
- VF610_PAD_PTB13__DSPI0_CS4
 
- VF610_PAD_PTB13__FB_AD0
 
- VF610_PAD_PTB13__GPIO_35
 
- VF610_PAD_PTB13__TRACE_CTL
 
- VF610_PAD_PTB13__UART0_CTS
 
- VF610_PAD_PTB14
 
- VF610_PAD_PTB14__CAN0_RX
 
- VF610_PAD_PTB14__DCU0_TCON8
 
- VF610_PAD_PTB14__DCU1_PCLK
 
- VF610_PAD_PTB14__GPIO_36
 
- VF610_PAD_PTB14__I2C0_SCL
 
- VF610_PAD_PTB15
 
- VF610_PAD_PTB15__CAN0_TX
 
- VF610_PAD_PTB15__DCU0_TCON9
 
- VF610_PAD_PTB15__GPIO_37
 
- VF610_PAD_PTB15__I2C0_SDA
 
- VF610_PAD_PTB15__VIU_PIX_CLK
 
- VF610_PAD_PTB16
 
- VF610_PAD_PTB16__CAN1_RX
 
- VF610_PAD_PTB16__DCU0_TCON10
 
- VF610_PAD_PTB16__GPIO_38
 
- VF610_PAD_PTB16__I2C1_SCL
 
- VF610_PAD_PTB17
 
- VF610_PAD_PTB17__CAN1_TX
 
- VF610_PAD_PTB17__DCU0_TCON11
 
- VF610_PAD_PTB17__GPIO_39
 
- VF610_PAD_PTB17__I2C1_SDA
 
- VF610_PAD_PTB18
 
- VF610_PAD_PTB18__DSPI0_CS1
 
- VF610_PAD_PTB18__EXT_AUDIO_MCLK
 
- VF610_PAD_PTB18__GPIO_40
 
- VF610_PAD_PTB18__VIU_DATA9
 
- VF610_PAD_PTB19
 
- VF610_PAD_PTB19__DSPI0_CS0
 
- VF610_PAD_PTB19__GPIO_41
 
- VF610_PAD_PTB19__VIU_DATA10
 
- VF610_PAD_PTB1__ADC0_SE3
 
- VF610_PAD_PTB1__FTM0_CH1
 
- VF610_PAD_PTB1__GPIO_23
 
- VF610_PAD_PTB1__LCD35
 
- VF610_PAD_PTB1__QSPI1_A_DATA3
 
- VF610_PAD_PTB1__SAI2_RX_DATA
 
- VF610_PAD_PTB1__SRC_RCON30
 
- VF610_PAD_PTB1__VIU_DATA19
 
- VF610_PAD_PTB2
 
- VF610_PAD_PTB20
 
- VF610_PAD_PTB20__DSPI0_SIN
 
- VF610_PAD_PTB20__GPIO_42
 
- VF610_PAD_PTB20__LCD42
 
- VF610_PAD_PTB20__VIU_DATA11
 
- VF610_PAD_PTB21
 
- VF610_PAD_PTB21__DCU1_PCLK
 
- VF610_PAD_PTB21__DSPI0_SOUT
 
- VF610_PAD_PTB21__GPIO_43
 
- VF610_PAD_PTB21__LCD43
 
- VF610_PAD_PTB21__VIU_DATA12
 
- VF610_PAD_PTB22
 
- VF610_PAD_PTB22__DSPI0_SCK
 
- VF610_PAD_PTB22__GPIO_44
 
- VF610_PAD_PTB22__VIU_FID
 
- VF610_PAD_PTB22__VLCD
 
- VF610_PAD_PTB23
 
- VF610_PAD_PTB23__DCU1_G3
 
- VF610_PAD_PTB23__FB_MUXED_ALE
 
- VF610_PAD_PTB23__FB_TS_B
 
- VF610_PAD_PTB23__GPIO_93
 
- VF610_PAD_PTB23__SAI0_TX_BCLK
 
- VF610_PAD_PTB23__SRC_RCON18
 
- VF610_PAD_PTB23__UART1_TX
 
- VF610_PAD_PTB23__UART3_RTS
 
- VF610_PAD_PTB24
 
- VF610_PAD_PTB24__DCU1_G4
 
- VF610_PAD_PTB24__FB_MUXED_TSIZ0
 
- VF610_PAD_PTB24__GPIO_94
 
- VF610_PAD_PTB24__NF_WE_B
 
- VF610_PAD_PTB24__SAI0_RX_BCLK
 
- VF610_PAD_PTB24__SRC_RCON19
 
- VF610_PAD_PTB24__UART1_RX
 
- VF610_PAD_PTB24__UART3_CTS
 
- VF610_PAD_PTB25
 
- VF610_PAD_PTB25__DCU1_G5
 
- VF610_PAD_PTB25__FB_CS1_B
 
- VF610_PAD_PTB25__GPIO_95
 
- VF610_PAD_PTB25__NF_CE0_B
 
- VF610_PAD_PTB25__SAI0_RX_DATA
 
- VF610_PAD_PTB25__SRC_RCON20
 
- VF610_PAD_PTB25__UART1_RTS
 
- VF610_PAD_PTB26
 
- VF610_PAD_PTB26__DCU1_G6
 
- VF610_PAD_PTB26__FB_CS0_B
 
- VF610_PAD_PTB26__GPIO_96
 
- VF610_PAD_PTB26__NF_CE1_B
 
- VF610_PAD_PTB26__SAI0_TX_DATA
 
- VF610_PAD_PTB26__SRC_RCON21
 
- VF610_PAD_PTB26__UART1_CTS
 
- VF610_PAD_PTB27
 
- VF610_PAD_PTB27__DCU1_G7
 
- VF610_PAD_PTB27__FB_MUXED_TBST_B
 
- VF610_PAD_PTB27__FB_OE_B
 
- VF610_PAD_PTB27__GPIO_97
 
- VF610_PAD_PTB27__NF_RE_B
 
- VF610_PAD_PTB27__SAI0_RX_SYNC
 
- VF610_PAD_PTB27__SRC_RCON22
 
- VF610_PAD_PTB28
 
- VF610_PAD_PTB28__DCU1_B6
 
- VF610_PAD_PTB28__FB_RW_B
 
- VF610_PAD_PTB28__GPIO_98
 
- VF610_PAD_PTB28__SAI0_TX_SYNC
 
- VF610_PAD_PTB28__SRC_RCON23
 
- VF610_PAD_PTB2__ADC1_SE2
 
- VF610_PAD_PTB2__FTM0_CH2
 
- VF610_PAD_PTB2__GPIO_24
 
- VF610_PAD_PTB2__LCD36
 
- VF610_PAD_PTB2__QSPI1_A_DATA2
 
- VF610_PAD_PTB2__SAI2_RX_SYNC
 
- VF610_PAD_PTB2__SRC_RCON31
 
- VF610_PAD_PTB2__VIDEO_IN0_DATA20
 
- VF610_PAD_PTB3
 
- VF610_PAD_PTB3__ADC1_SE3
 
- VF610_PAD_PTB3__FTM0_CH3
 
- VF610_PAD_PTB3__GPIO_25
 
- VF610_PAD_PTB3__LCD37
 
- VF610_PAD_PTB3__PDB_EXTRIG
 
- VF610_PAD_PTB3__QSPI1_A_DATA1
 
- VF610_PAD_PTB3__VIU_DATA21
 
- VF610_PAD_PTB4
 
- VF610_PAD_PTB4__ADC0_SE4
 
- VF610_PAD_PTB4__FTM0_CH4
 
- VF610_PAD_PTB4__GPIO_26
 
- VF610_PAD_PTB4__LCD38
 
- VF610_PAD_PTB4__QSPI1_A_DATA0
 
- VF610_PAD_PTB4__UART1_TX
 
- VF610_PAD_PTB4__VIU_DATA22
 
- VF610_PAD_PTB4__VIU_FID
 
- VF610_PAD_PTB5
 
- VF610_PAD_PTB5__ADC1_SE4
 
- VF610_PAD_PTB5__FTM0_CH5
 
- VF610_PAD_PTB5__GPIO_27
 
- VF610_PAD_PTB5__LCD39
 
- VF610_PAD_PTB5__QSPI1_A_DQS
 
- VF610_PAD_PTB5__UART1_RX
 
- VF610_PAD_PTB5__VIU_DE
 
- VF610_PAD_PTB6
 
- VF610_PAD_PTB6__FB_CLKOUT
 
- VF610_PAD_PTB6__FTM0_CH6
 
- VF610_PAD_PTB6__GPIO_28
 
- VF610_PAD_PTB6__LCD_LCD40
 
- VF610_PAD_PTB6__QSPI0_QPCS1_A
 
- VF610_PAD_PTB6__UART1_RTS
 
- VF610_PAD_PTB6__UART2_TX
 
- VF610_PAD_PTB6__VIU_HSYNC
 
- VF610_PAD_PTB7
 
- VF610_PAD_PTB7__FTM0_CH7
 
- VF610_PAD_PTB7__GPIO_29
 
- VF610_PAD_PTB7__LCD41
 
- VF610_PAD_PTB7__QSPI0_B_QPCS1
 
- VF610_PAD_PTB7__UART1_CTS
 
- VF610_PAD_PTB7__UART2_RX
 
- VF610_PAD_PTB7__VIU_VSYNC
 
- VF610_PAD_PTB8
 
- VF610_PAD_PTB8__DCU1_R6
 
- VF610_PAD_PTB8__FTM1_CH0
 
- VF610_PAD_PTB8__FTM1_QD_PHA
 
- VF610_PAD_PTB8__GPIO_30
 
- VF610_PAD_PTB8__VIU_DE
 
- VF610_PAD_PTB9
 
- VF610_PAD_PTB9__DCU1_R7
 
- VF610_PAD_PTB9__FTM1_CH1
 
- VF610_PAD_PTB9__FTM1_QD_PHB
 
- VF610_PAD_PTB9__GPIO_31
 
- VF610_PAD_PTC0
 
- VF610_PAD_PTC0__DSPI0_CS3
 
- VF610_PAD_PTC0__ENET_RMII0_MDC
 
- VF610_PAD_PTC0__ESAI_SCKT
 
- VF610_PAD_PTC0__ESDHC0_CLK
 
- VF610_PAD_PTC0__FTM1_CH0
 
- VF610_PAD_PTC0__GPIO_45
 
- VF610_PAD_PTC0__SRC_RCON18
 
- VF610_PAD_PTC0__VIU_DATA0
 
- VF610_PAD_PTC1
 
- VF610_PAD_PTC10
 
- VF610_PAD_PTC10__DEBUG_OUT1
 
- VF610_PAD_PTC10__ENET_RMII1_MDIO
 
- VF610_PAD_PTC10__ESAI_FST
 
- VF610_PAD_PTC10__GPIO_55
 
- VF610_PAD_PTC10__MLB_SIGNAL
 
- VF610_PAD_PTC11
 
- VF610_PAD_PTC11__DEBUG_OUT
 
- VF610_PAD_PTC11__ENET_RMII1_CRS
 
- VF610_PAD_PTC11__ESAI_SDO0
 
- VF610_PAD_PTC11__GPIO_56
 
- VF610_PAD_PTC11__MLB_DATA
 
- VF610_PAD_PTC12
 
- VF610_PAD_PTC12__DEBUG_OUT3
 
- VF610_PAD_PTC12__ENET_RMII1_RXD1
 
- VF610_PAD_PTC12__ESAI_SDO1
 
- VF610_PAD_PTC12__GPIO_57
 
- VF610_PAD_PTC12__SAI2_TX_BCLK
 
- VF610_PAD_PTC13
 
- VF610_PAD_PTC13__DEBUG_OUT4
 
- VF610_PAD_PTC13__ENET_RMII1_RXD0
 
- VF610_PAD_PTC13__ESAI_SDO2
 
- VF610_PAD_PTC13__GPIO_58
 
- VF610_PAD_PTC13__SAI2_RX_BCLK
 
- VF610_PAD_PTC14
 
- VF610_PAD_PTC14__ADC0_SE6
 
- VF610_PAD_PTC14__DEBUG_OUT5
 
- VF610_PAD_PTC14__ENET_RMII1_RXER
 
- VF610_PAD_PTC14__ESAI_SDO3
 
- VF610_PAD_PTC14__GPIO_59
 
- VF610_PAD_PTC14__SAI2_RX_DATA
 
- VF610_PAD_PTC14__UART5_TX
 
- VF610_PAD_PTC15
 
- VF610_PAD_PTC15__ADC0_SE7
 
- VF610_PAD_PTC15__DEBUG_OUT6
 
- VF610_PAD_PTC15__ENET_RMII1_TXD1
 
- VF610_PAD_PTC15__ESAI_SDI0
 
- VF610_PAD_PTC15__GPIO_60
 
- VF610_PAD_PTC15__SAI2_TX_DATA
 
- VF610_PAD_PTC15__UART5_RX
 
- VF610_PAD_PTC16
 
- VF610_PAD_PTC16__ADC1_SE6
 
- VF610_PAD_PTC16__DEBUG_OUT7
 
- VF610_PAD_PTC16__ENET_RMII1_TXD0
 
- VF610_PAD_PTC16__ESAI_SDI1
 
- VF610_PAD_PTC16__GPIO_61
 
- VF610_PAD_PTC16__SAI2_RX_SYNC
 
- VF610_PAD_PTC16__UART5_RTS
 
- VF610_PAD_PTC17
 
- VF610_PAD_PTC17__ADC1_SE7
 
- VF610_PAD_PTC17__DEBUG_OUT8
 
- VF610_PAD_PTC17__ENET_RMII1_TXEN
 
- VF610_PAD_PTC17__GPIO_62
 
- VF610_PAD_PTC17__SAI2_TX_SYNC
 
- VF610_PAD_PTC17__UART5_CTS
 
- VF610_PAD_PTC17__USB1_SOF_PULSE
 
- VF610_PAD_PTC1__DSPI0_CS2
 
- VF610_PAD_PTC1__ENET_RMII0_MDIO
 
- VF610_PAD_PTC1__ESAI_FST
 
- VF610_PAD_PTC1__ESDHC0_CMD
 
- VF610_PAD_PTC1__FTM1_CH1
 
- VF610_PAD_PTC1__GPIO_46
 
- VF610_PAD_PTC1__SRC_RCON19
 
- VF610_PAD_PTC1__VIU_DATA1
 
- VF610_PAD_PTC2
 
- VF610_PAD_PTC26
 
- VF610_PAD_PTC26__DCU1_B7
 
- VF610_PAD_PTC26__DSPI0_CS5
 
- VF610_PAD_PTC26__FB_TA_B
 
- VF610_PAD_PTC26__GPIO_99
 
- VF610_PAD_PTC26__NF_RB_B
 
- VF610_PAD_PTC26__SAI1_TX_BCLK
 
- VF610_PAD_PTC26__SRC_RCON24
 
- VF610_PAD_PTC27
 
- VF610_PAD_PTC27__DCU1_B2
 
- VF610_PAD_PTC27__DSPI0_CS4
 
- VF610_PAD_PTC27__FB_BE3_B
 
- VF610_PAD_PTC27__FB_CS3_B
 
- VF610_PAD_PTC27__GPIO_100
 
- VF610_PAD_PTC27__NF_ALE
 
- VF610_PAD_PTC27__SAI1_RX_BCLK
 
- VF610_PAD_PTC27__SRC_RCON25
 
- VF610_PAD_PTC28
 
- VF610_PAD_PTC28__DCU1_B3
 
- VF610_PAD_PTC28__DSPI0_CS3
 
- VF610_PAD_PTC28__FB_BE2_B
 
- VF610_PAD_PTC28__FB_CS2_B
 
- VF610_PAD_PTC28__GPIO_101
 
- VF610_PAD_PTC28__NF_CLE
 
- VF610_PAD_PTC28__SAI1_RX_DATA
 
- VF610_PAD_PTC28__SRC_RCON26
 
- VF610_PAD_PTC29
 
- VF610_PAD_PTC29__DCU1_B4
 
- VF610_PAD_PTC29__DSPI0_CS2
 
- VF610_PAD_PTC29__FB_BE1_B
 
- VF610_PAD_PTC29__FB_MUXED_TSIZE1
 
- VF610_PAD_PTC29__GPIO_102
 
- VF610_PAD_PTC29__SAI1_TX_DATA
 
- VF610_PAD_PTC29__SRC_RCON27
 
- VF610_PAD_PTC2__ENET_RMII0_CRS
 
- VF610_PAD_PTC2__ESAI_SDO0
 
- VF610_PAD_PTC2__ESDHC0_DAT0
 
- VF610_PAD_PTC2__GPIO_47
 
- VF610_PAD_PTC2__SRC_RCON20
 
- VF610_PAD_PTC2__UART1_TX
 
- VF610_PAD_PTC2__VIU_DATA2
 
- VF610_PAD_PTC3
 
- VF610_PAD_PTC30
 
- VF610_PAD_PTC30__ADC0_SE5
 
- VF610_PAD_PTC30__DCU1_B5
 
- VF610_PAD_PTC30__DSPI1_CS2
 
- VF610_PAD_PTC30__FB_MUXED_BE0_B
 
- VF610_PAD_PTC30__FB_TSIZ0
 
- VF610_PAD_PTC30__GPIO_103
 
- VF610_PAD_PTC30__SAI1_RX_SYNC
 
- VF610_PAD_PTC30__SRC_RCON28
 
- VF610_PAD_PTC31
 
- VF610_PAD_PTC31__ADC1_SE5
 
- VF610_PAD_PTC31__DCU1_B6
 
- VF610_PAD_PTC31__GPIO_104
 
- VF610_PAD_PTC31__SAI1_TX_SYNC
 
- VF610_PAD_PTC31__SRC_RCON29
 
- VF610_PAD_PTC3__DCU0_R0
 
- VF610_PAD_PTC3__ENET_RMII0_RXD1
 
- VF610_PAD_PTC3__ESAI_SDO1
 
- VF610_PAD_PTC3__ESDHC0_DAT1
 
- VF610_PAD_PTC3__GPIO_48
 
- VF610_PAD_PTC3__UART1_RX
 
- VF610_PAD_PTC3__VIU_DATA3
 
- VF610_PAD_PTC4
 
- VF610_PAD_PTC4__DCU0_R1
 
- VF610_PAD_PTC4__DSPI1_CS1
 
- VF610_PAD_PTC4__ENET_RMII0_RXD0
 
- VF610_PAD_PTC4__ESAI_SDO2
 
- VF610_PAD_PTC4__ESDHC0_DAT2
 
- VF610_PAD_PTC4__GPIO_49
 
- VF610_PAD_PTC4__UART1_RTS
 
- VF610_PAD_PTC4__VIU_DATA4
 
- VF610_PAD_PTC5
 
- VF610_PAD_PTC5__DCU0_G0
 
- VF610_PAD_PTC5__DSPI1_CS0
 
- VF610_PAD_PTC5__ENET_RMII0_RXER
 
- VF610_PAD_PTC5__ESAI_SDO3
 
- VF610_PAD_PTC5__ESDHC0_DAT3
 
- VF610_PAD_PTC5__GPIO_50
 
- VF610_PAD_PTC5__UART1_CTS
 
- VF610_PAD_PTC5__VIU_DATA5
 
- VF610_PAD_PTC6
 
- VF610_PAD_PTC6__DCU0_G1
 
- VF610_PAD_PTC6__DSPI1_SIN
 
- VF610_PAD_PTC6__ENET_RMII0_TXD1
 
- VF610_PAD_PTC6__ESAI_SDI0
 
- VF610_PAD_PTC6__ESDHC0_WP
 
- VF610_PAD_PTC6__GPIO_51
 
- VF610_PAD_PTC6__VIU_DATA6
 
- VF610_PAD_PTC7
 
- VF610_PAD_PTC7__DCU0_B0
 
- VF610_PAD_PTC7__DSPI1_SOUT
 
- VF610_PAD_PTC7__ENET_RMII0_TXD0
 
- VF610_PAD_PTC7__ESAI_SDI1
 
- VF610_PAD_PTC7__GPIO_52
 
- VF610_PAD_PTC7__VIU_DATA7
 
- VF610_PAD_PTC8
 
- VF610_PAD_PTC8__DCU0_B1
 
- VF610_PAD_PTC8__DSPI1_SCK
 
- VF610_PAD_PTC8__ENET_RMII0_TXEN
 
- VF610_PAD_PTC8__GPIO_53
 
- VF610_PAD_PTC8__VIU_DATA8
 
- VF610_PAD_PTC9
 
- VF610_PAD_PTC9__DEBUG_OUT0
 
- VF610_PAD_PTC9__ENET_RMII1_MDC
 
- VF610_PAD_PTC9__ESAI_SCKT
 
- VF610_PAD_PTC9__GPIO_54
 
- VF610_PAD_PTC9__MLB_CLK
 
- VF610_PAD_PTD0
 
- VF610_PAD_PTD0__DEBUG_OUT17
 
- VF610_PAD_PTD0__FB_AD15
 
- VF610_PAD_PTD0__GPIO_79
 
- VF610_PAD_PTD0__QSPI0_A_QSCK
 
- VF610_PAD_PTD0__SPDIF_EXTCLK
 
- VF610_PAD_PTD0__UART2_TX
 
- VF610_PAD_PTD1
 
- VF610_PAD_PTD10
 
- VF610_PAD_PTD10__DCU1_B1
 
- VF610_PAD_PTD10__DSPI3_CS0
 
- VF610_PAD_PTD10__FB_AD5
 
- VF610_PAD_PTD10__GPIO_89
 
- VF610_PAD_PTD10__QSPI0_B_DATA2
 
- VF610_PAD_PTD11
 
- VF610_PAD_PTD11__DEBUG_OUT26
 
- VF610_PAD_PTD11__DSPI3_SIN
 
- VF610_PAD_PTD11__FB_AD4
 
- VF610_PAD_PTD11__GPIO_90
 
- VF610_PAD_PTD11__QSPI0_B_DATA1
 
- VF610_PAD_PTD12
 
- VF610_PAD_PTD12__DEBUG_OUT27
 
- VF610_PAD_PTD12__DSPI3_SOUT
 
- VF610_PAD_PTD12__FB_AD3
 
- VF610_PAD_PTD12__GPIO_91
 
- VF610_PAD_PTD12__QSPI0_B_DATA0
 
- VF610_PAD_PTD13
 
- VF610_PAD_PTD13__DEBUG_OUT28
 
- VF610_PAD_PTD13__DSPI3_SCK
 
- VF610_PAD_PTD13__FB_AD2
 
- VF610_PAD_PTD13__GPIO_92
 
- VF610_PAD_PTD13__QSPI0_B_DQS
 
- VF610_PAD_PTD16
 
- VF610_PAD_PTD16__DCU1_G2
 
- VF610_PAD_PTD16__ESAI_HCKT
 
- VF610_PAD_PTD16__FB_AD16
 
- VF610_PAD_PTD16__GPIO_78
 
- VF610_PAD_PTD16__I2C1_SDA
 
- VF610_PAD_PTD16__NF_IO0
 
- VF610_PAD_PTD17
 
- VF610_PAD_PTD17__DCU1_G1
 
- VF610_PAD_PTD17__ESAI_HCKR
 
- VF610_PAD_PTD17__FB_AD17
 
- VF610_PAD_PTD17__GPIO_77
 
- VF610_PAD_PTD17__I2C1_SCL
 
- VF610_PAD_PTD17__NF_IO1
 
- VF610_PAD_PTD18
 
- VF610_PAD_PTD18__DCU1_G0
 
- VF610_PAD_PTD18__ESAI_FSR
 
- VF610_PAD_PTD18__FB_AD18
 
- VF610_PAD_PTD18__FTM2_QD_PHB
 
- VF610_PAD_PTD18__GPIO_76
 
- VF610_PAD_PTD18__I2C0_SDA
 
- VF610_PAD_PTD18__NF_IO2
 
- VF610_PAD_PTD19
 
- VF610_PAD_PTD19__DCU1_R1
 
- VF610_PAD_PTD19__ESAI_SCKR
 
- VF610_PAD_PTD19__FB_AD19
 
- VF610_PAD_PTD19__FTM2_QD_PHA
 
- VF610_PAD_PTD19__GPIO_75
 
- VF610_PAD_PTD19__I2C0_SCL
 
- VF610_PAD_PTD19__NF_IO3
 
- VF610_PAD_PTD1__DEBUG_OUT18
 
- VF610_PAD_PTD1__FB_AD14
 
- VF610_PAD_PTD1__GPIO_80
 
- VF610_PAD_PTD1__QSPI0_A_CS0
 
- VF610_PAD_PTD1__SPDIF_IN1
 
- VF610_PAD_PTD1__UART2_RX
 
- VF610_PAD_PTD2
 
- VF610_PAD_PTD20
 
- VF610_PAD_PTD20__DCU1_R0
 
- VF610_PAD_PTD20__ENET0_1588_TMR3
 
- VF610_PAD_PTD20__ESDHC0_DAT7
 
- VF610_PAD_PTD20__FB_AD20
 
- VF610_PAD_PTD20__GPIO_74
 
- VF610_PAD_PTD20__NF_IO4
 
- VF610_PAD_PTD20__UART2_CTS
 
- VF610_PAD_PTD21
 
- VF610_PAD_PTD21__DCU1_R5
 
- VF610_PAD_PTD21__ENET0_1588_TMR2
 
- VF610_PAD_PTD21__ESDHC0_DAT6
 
- VF610_PAD_PTD21__FB_AD21
 
- VF610_PAD_PTD21__GPIO_73
 
- VF610_PAD_PTD21__NF_IO5
 
- VF610_PAD_PTD21__UART2_RTS
 
- VF610_PAD_PTD22
 
- VF610_PAD_PTD22__DCU1_R4
 
- VF610_PAD_PTD22__ENET0_1588_TMR1
 
- VF610_PAD_PTD22__ESDHC0_DAT5
 
- VF610_PAD_PTD22__FB_AD22
 
- VF610_PAD_PTD22__FTM2_CH1
 
- VF610_PAD_PTD22__GPIO_72
 
- VF610_PAD_PTD22__NF_IO6
 
- VF610_PAD_PTD22__UART2_RX
 
- VF610_PAD_PTD23
 
- VF610_PAD_PTD23__DCU1_R3
 
- VF610_PAD_PTD23__ENET0_1588_TMR0
 
- VF610_PAD_PTD23__ESDHC0_DAT4
 
- VF610_PAD_PTD23__FB_AD23
 
- VF610_PAD_PTD23__FTM2_CH0
 
- VF610_PAD_PTD23__GPIO_71
 
- VF610_PAD_PTD23__NF_IO7
 
- VF610_PAD_PTD23__UART2_TX
 
- VF610_PAD_PTD24
 
- VF610_PAD_PTD24__DEBUG_OUT16
 
- VF610_PAD_PTD24__FB_AD24
 
- VF610_PAD_PTD24__FTM3_CH7
 
- VF610_PAD_PTD24__GPIO_70
 
- VF610_PAD_PTD24__NF_IO8
 
- VF610_PAD_PTD25
 
- VF610_PAD_PTD25__DEBUG_OUT15
 
- VF610_PAD_PTD25__FB_AD25
 
- VF610_PAD_PTD25__FTM3_CH6
 
- VF610_PAD_PTD25__GPIO_69
 
- VF610_PAD_PTD25__NF_IO9
 
- VF610_PAD_PTD26
 
- VF610_PAD_PTD26__DEBUG_OUT14
 
- VF610_PAD_PTD26__ESDHC1_WP
 
- VF610_PAD_PTD26__FB_AD26
 
- VF610_PAD_PTD26__FTM3_CH5
 
- VF610_PAD_PTD26__GPIO_68
 
- VF610_PAD_PTD26__NF_IO10
 
- VF610_PAD_PTD27
 
- VF610_PAD_PTD27__DEBUG_OUT13
 
- VF610_PAD_PTD27__DSPI2_SCK
 
- VF610_PAD_PTD27__FB_AD27
 
- VF610_PAD_PTD27__FTM3_CH4
 
- VF610_PAD_PTD27__GPIO_67
 
- VF610_PAD_PTD27__I2C2_SDA
 
- VF610_PAD_PTD27__NF_IO11
 
- VF610_PAD_PTD28
 
- VF610_PAD_PTD28__DEBUG_OUT12
 
- VF610_PAD_PTD28__DSPI2_SOUT
 
- VF610_PAD_PTD28__FB_AD28
 
- VF610_PAD_PTD28__FTM3_CH3
 
- VF610_PAD_PTD28__GPIO_66
 
- VF610_PAD_PTD28__I2C2_SCL
 
- VF610_PAD_PTD28__NF_IO12
 
- VF610_PAD_PTD29
 
- VF610_PAD_PTD29__DEBUG_OUT11
 
- VF610_PAD_PTD29__DSPI2_SIN
 
- VF610_PAD_PTD29__FB_AD29
 
- VF610_PAD_PTD29__FTM3_CH2
 
- VF610_PAD_PTD29__GPIO_65
 
- VF610_PAD_PTD29__NF_IO13
 
- VF610_PAD_PTD2__DEBUG_OUT19
 
- VF610_PAD_PTD2__DSPI1_CS3
 
- VF610_PAD_PTD2__FB_AD13
 
- VF610_PAD_PTD2__GPIO_81
 
- VF610_PAD_PTD2__QSPI0_A_DATA3
 
- VF610_PAD_PTD2__SPDIF_OUT1
 
- VF610_PAD_PTD2__UART2_RTS
 
- VF610_PAD_PTD3
 
- VF610_PAD_PTD30
 
- VF610_PAD_PTD30__DEBUG_OUT10
 
- VF610_PAD_PTD30__DSPI2_CS0
 
- VF610_PAD_PTD30__FB_AD30
 
- VF610_PAD_PTD30__FTM3_CH1
 
- VF610_PAD_PTD30__GPIO_64
 
- VF610_PAD_PTD30__NF_IO14
 
- VF610_PAD_PTD31
 
- VF610_PAD_PTD31__DEBUG_OUT9
 
- VF610_PAD_PTD31__DSPI2_CS1
 
- VF610_PAD_PTD31__FB_AD31
 
- VF610_PAD_PTD31__FTM3_CH0
 
- VF610_PAD_PTD31__GPIO_63
 
- VF610_PAD_PTD31__NF_IO15
 
- VF610_PAD_PTD3__DEBUG_OUT20
 
- VF610_PAD_PTD3__DSPI1_CS2
 
- VF610_PAD_PTD3__FB_AD12
 
- VF610_PAD_PTD3__GPIO_82
 
- VF610_PAD_PTD3__QSPI0_A_DATA2
 
- VF610_PAD_PTD3__SPDIF_PLOCK
 
- VF610_PAD_PTD3__UART2_CTS
 
- VF610_PAD_PTD4
 
- VF610_PAD_PTD4__DEBUG_OUT21
 
- VF610_PAD_PTD4__DSPI1_CS1
 
- VF610_PAD_PTD4__FB_AD11
 
- VF610_PAD_PTD4__GPIO_83
 
- VF610_PAD_PTD4__QSPI0_A_DATA1
 
- VF610_PAD_PTD4__SPDIF_SRCLK
 
- VF610_PAD_PTD5
 
- VF610_PAD_PTD5__DEBUG_OUT22
 
- VF610_PAD_PTD5__DSPI1_CS0
 
- VF610_PAD_PTD5__FB_AD10
 
- VF610_PAD_PTD5__GPIO_84
 
- VF610_PAD_PTD5__QSPI0_A_DATA0
 
- VF610_PAD_PTD6
 
- VF610_PAD_PTD6__DEBUG_OUT23
 
- VF610_PAD_PTD6__DSPI1_SIN
 
- VF610_PAD_PTD6__FB_AD9
 
- VF610_PAD_PTD6__GPIO_85
 
- VF610_PAD_PTD6__QSPI1_A_DQS
 
- VF610_PAD_PTD7
 
- VF610_PAD_PTD7__DEBUG_OUT24
 
- VF610_PAD_PTD7__DSPI1_SOUT
 
- VF610_PAD_PTD7__FB_AD8
 
- VF610_PAD_PTD7__GPIO_86
 
- VF610_PAD_PTD7__QSPI0_B_QSCK
 
- VF610_PAD_PTD8
 
- VF610_PAD_PTD8__DEBUG_OUT25
 
- VF610_PAD_PTD8__DSPI1_SCK
 
- VF610_PAD_PTD8__FB_AD7
 
- VF610_PAD_PTD8__FB_CLKOUT
 
- VF610_PAD_PTD8__GPIO_87
 
- VF610_PAD_PTD8__QSPI0_B_CS0
 
- VF610_PAD_PTD9
 
- VF610_PAD_PTD9__DCU1_B0
 
- VF610_PAD_PTD9__DSPI3_CS1
 
- VF610_PAD_PTD9__FB_AD6
 
- VF610_PAD_PTD9__GPIO_88
 
- VF610_PAD_PTD9__QSPI0_B_DATA3
 
- VF610_PAD_PTD9__SAI1_TX_SYNC
 
- VF610_PAD_PTE0
 
- VF610_PAD_PTE0__DCU0_HSYNC
 
- VF610_PAD_PTE0__DEBUG_OUT29
 
- VF610_PAD_PTE0__GPIO_105
 
- VF610_PAD_PTE0__LCD0
 
- VF610_PAD_PTE0__SRC_BMODE1
 
- VF610_PAD_PTE1
 
- VF610_PAD_PTE10
 
- VF610_PAD_PTE10__DCU0_R5
 
- VF610_PAD_PTE10__DEBUG_OUT39
 
- VF610_PAD_PTE10__GPIO_115
 
- VF610_PAD_PTE10__LCD10
 
- VF610_PAD_PTE10__SRC_RCON3
 
- VF610_PAD_PTE11
 
- VF610_PAD_PTE11__DCU0_R6
 
- VF610_PAD_PTE11__DEBUG_OUT40
 
- VF610_PAD_PTE11__GPIO_116
 
- VF610_PAD_PTE11__LCD11
 
- VF610_PAD_PTE11__SRC_RCON4
 
- VF610_PAD_PTE12
 
- VF610_PAD_PTE12__DCU0_R7
 
- VF610_PAD_PTE12__DSPI1_CS3
 
- VF610_PAD_PTE12__GPIO_117
 
- VF610_PAD_PTE12__LCD12
 
- VF610_PAD_PTE12__LPT_ALT0
 
- VF610_PAD_PTE12__SRC_RCON5
 
- VF610_PAD_PTE13
 
- VF610_PAD_PTE13__DCU0_G0
 
- VF610_PAD_PTE13__DEBUG_OUT41
 
- VF610_PAD_PTE13__GPIO_118
 
- VF610_PAD_PTE13__LCD13
 
- VF610_PAD_PTE14
 
- VF610_PAD_PTE14__DCU0_G1
 
- VF610_PAD_PTE14__DEBUG_OUT42
 
- VF610_PAD_PTE14__GPIO_119
 
- VF610_PAD_PTE14__LCD14
 
- VF610_PAD_PTE15
 
- VF610_PAD_PTE15__DCU0_G2
 
- VF610_PAD_PTE15__DEBUG_OUT43
 
- VF610_PAD_PTE15__GPIO_120
 
- VF610_PAD_PTE15__LCD15
 
- VF610_PAD_PTE15__SRC_RCON6
 
- VF610_PAD_PTE16
 
- VF610_PAD_PTE16__DCU0_G3
 
- VF610_PAD_PTE16__GPIO_121
 
- VF610_PAD_PTE16__LCD16
 
- VF610_PAD_PTE16__SRC_RCON7
 
- VF610_PAD_PTE17
 
- VF610_PAD_PTE17__DCU0_G4
 
- VF610_PAD_PTE17__GPIO_122
 
- VF610_PAD_PTE17__LCD17
 
- VF610_PAD_PTE17__SRC_RCON8
 
- VF610_PAD_PTE18
 
- VF610_PAD_PTE18__DCU0_G5
 
- VF610_PAD_PTE18__GPIO_123
 
- VF610_PAD_PTE18__LCD18
 
- VF610_PAD_PTE18__SRC_RCON9
 
- VF610_PAD_PTE19
 
- VF610_PAD_PTE19__DCU0_G6
 
- VF610_PAD_PTE19__GPIO_124
 
- VF610_PAD_PTE19__I2C0_SCL
 
- VF610_PAD_PTE19__LCD19
 
- VF610_PAD_PTE19__SRC_RCON10
 
- VF610_PAD_PTE1__DCU0_VSYNC
 
- VF610_PAD_PTE1__DEBUG_OUT30
 
- VF610_PAD_PTE1__GPIO_106
 
- VF610_PAD_PTE1__LCD1
 
- VF610_PAD_PTE1__SRC_BMODE0
 
- VF610_PAD_PTE2
 
- VF610_PAD_PTE20
 
- VF610_PAD_PTE20__DCU0_G7
 
- VF610_PAD_PTE20__EWM_IN
 
- VF610_PAD_PTE20__GPIO_125
 
- VF610_PAD_PTE20__I2C0_SDA
 
- VF610_PAD_PTE20__LCD20
 
- VF610_PAD_PTE20__SRC_RCON11
 
- VF610_PAD_PTE21
 
- VF610_PAD_PTE21__DCU0_B0
 
- VF610_PAD_PTE21__GPIO_126
 
- VF610_PAD_PTE21__LCD21
 
- VF610_PAD_PTE22
 
- VF610_PAD_PTE22__DCU0_B1
 
- VF610_PAD_PTE22__GPIO_127
 
- VF610_PAD_PTE22__LCD22
 
- VF610_PAD_PTE23
 
- VF610_PAD_PTE23__DCU0_B2
 
- VF610_PAD_PTE23__GPIO_128
 
- VF610_PAD_PTE23__LCD23
 
- VF610_PAD_PTE23__SRC_RCON12
 
- VF610_PAD_PTE24
 
- VF610_PAD_PTE24__DCU0_B3
 
- VF610_PAD_PTE24__GPIO_129
 
- VF610_PAD_PTE24__LCD24
 
- VF610_PAD_PTE24__SRC_RCON13
 
- VF610_PAD_PTE25
 
- VF610_PAD_PTE25__DCU0_B4
 
- VF610_PAD_PTE25__GPIO_130
 
- VF610_PAD_PTE25__LCD25
 
- VF610_PAD_PTE25__SRC_RCON14
 
- VF610_PAD_PTE26
 
- VF610_PAD_PTE26__DCU0_B5
 
- VF610_PAD_PTE26__GPIO_131
 
- VF610_PAD_PTE26__LCD26
 
- VF610_PAD_PTE26__SRC_RCON15
 
- VF610_PAD_PTE27
 
- VF610_PAD_PTE27__DCU0_B6
 
- VF610_PAD_PTE27__GPIO_132
 
- VF610_PAD_PTE27__I2C1_SCL
 
- VF610_PAD_PTE27__LCD27
 
- VF610_PAD_PTE27__SRC_RCON16
 
- VF610_PAD_PTE28
 
- VF610_PAD_PTE28__DCU0_B7
 
- VF610_PAD_PTE28__EWM_OUT
 
- VF610_PAD_PTE28__GPIO_133
 
- VF610_PAD_PTE28__I2C1_SDA
 
- VF610_PAD_PTE28__LCD28
 
- VF610_PAD_PTE28__SRC_RCON17
 
- VF610_PAD_PTE2__DCU0_PCLK
 
- VF610_PAD_PTE2__DEBUG_OUT31
 
- VF610_PAD_PTE2__GPIO_107
 
- VF610_PAD_PTE2__LCD2
 
- VF610_PAD_PTE3
 
- VF610_PAD_PTE3__DCU0_TAG
 
- VF610_PAD_PTE3__DEBUG_OUT32
 
- VF610_PAD_PTE3__GPIO_108
 
- VF610_PAD_PTE3__LCD3
 
- VF610_PAD_PTE4
 
- VF610_PAD_PTE4__DCU0_DE
 
- VF610_PAD_PTE4__DEBUG_OUT33
 
- VF610_PAD_PTE4__GPIO_109
 
- VF610_PAD_PTE4__LCD4
 
- VF610_PAD_PTE5
 
- VF610_PAD_PTE5__DCU0_R0
 
- VF610_PAD_PTE5__DEBUG_OUT34
 
- VF610_PAD_PTE5__GPIO_110
 
- VF610_PAD_PTE5__LCD5
 
- VF610_PAD_PTE6
 
- VF610_PAD_PTE6__DCU0_R1
 
- VF610_PAD_PTE6__DEBUG_OUT35
 
- VF610_PAD_PTE6__GPIO_111
 
- VF610_PAD_PTE6__LCD6
 
- VF610_PAD_PTE7
 
- VF610_PAD_PTE7__DCU0_R2
 
- VF610_PAD_PTE7__DEBUG_OUT36
 
- VF610_PAD_PTE7__GPIO_112
 
- VF610_PAD_PTE7__LCD7
 
- VF610_PAD_PTE7__SRC_RCON0
 
- VF610_PAD_PTE8
 
- VF610_PAD_PTE8__DCU0_R3
 
- VF610_PAD_PTE8__DEBUG_OUT37
 
- VF610_PAD_PTE8__GPIO_113
 
- VF610_PAD_PTE8__LCD8
 
- VF610_PAD_PTE8__SRC_RCON1
 
- VF610_PAD_PTE9
 
- VF610_PAD_PTE9__DCU0_R4
 
- VF610_PAD_PTE9__DEBUG_OUT38
 
- VF610_PAD_PTE9__GPIO_114
 
- VF610_PAD_PTE9__LCD9
 
- VF610_PAD_PTE9__SRC_RCON2
 
- VF610_PLL1_BYPASS
 
- VF610_PLL2_BYPASS
 
- VF610_PLL3_BYPASS
 
- VF610_PLL4_BYPASS
 
- VF610_PLL5_BYPASS
 
- VF610_PLL6_BYPASS
 
- VF610_PLL7_BYPASS
 
- VF610_REG_ADC_CAL
 
- VF610_REG_ADC_CFG
 
- VF610_REG_ADC_CV
 
- VF610_REG_ADC_GC
 
- VF610_REG_ADC_GS
 
- VF610_REG_ADC_HC0
 
- VF610_REG_ADC_HC1
 
- VF610_REG_ADC_HS
 
- VF610_REG_ADC_OFS
 
- VF610_REG_ADC_PCTL
 
- VF610_REG_ADC_R0
 
- VF610_REG_ADC_R1
 
- VF610_TEMP_SLOPE_COEFF
 
- VF610_VTEMP25_3V0
 
- VF610_VTEMP25_3V3
 
- VFAC_CTL1
 
- VFAC_CTL1_CAPTURE
 
- VFAC_CTL1_FREEZE_CAPTURE
 
- VFAC_CTL1_FREEZE_CAPTURE_SYNC
 
- VFAC_CTL1_MODVINTERPOLCLK
 
- VFAC_CTL1_PHILIPS
 
- VFAC_CTL1_VALIDFRAME_SRC
 
- VFAC_CTL1_VFAC_ENABLE
 
- VFAC_CTL2
 
- VFAC_CTL2_INVERT_BLANK
 
- VFAC_CTL2_INVERT_DATACLK
 
- VFAC_CTL2_INVERT_FRAME
 
- VFAC_CTL2_INVERT_GRAPHREADY
 
- VFAC_CTL2_INVERT_HSYNC
 
- VFAC_CTL2_INVERT_OVSYNC
 
- VFAC_CTL2_INVERT_VIDDATAVALID
 
- VFAC_CTL2_INVERT_VSYNC
 
- VFAC_CTL3
 
- VFAC_CTL3_CAP_HOLD_0NS
 
- VFAC_CTL3_CAP_HOLD_2NS
 
- VFAC_CTL3_CAP_HOLD_4NS
 
- VFAC_CTL3_CAP_HOLD_6NS
 
- VFAC_CTL3_CAP_INTERLACE
 
- VFAC_CTL3_CAP_IRQ
 
- VFAC_CTL3_CAP_LARGE_FIFO
 
- VFAC_CTL3_CHROMAKEY
 
- VFAT_IOCTL_READDIR_BOTH
 
- VFAT_IOCTL_READDIR_BOTH32
 
- VFAT_IOCTL_READDIR_SHORT
 
- VFAT_IOCTL_READDIR_SHORT32
 
- VFAT_SFN_CREATE_WIN95
 
- VFAT_SFN_CREATE_WINNT
 
- VFAT_SFN_DISPLAY_LOWER
 
- VFAT_SFN_DISPLAY_WIN95
 
- VFAT_SFN_DISPLAY_WINNT
 
- VFCF_FCP_SEQ_LVL_ERR
 
- VFCF_FIP_CAPABLE
 
- VFCF_PERBI
 
- VFCHNEN_F
 
- VFCHNEN_S
 
- VFCHNEN_V
 
- VFCT_IMAGE_HEADER
 
- VFC_ALREADY_IN_PROGRESS
 
- VFC_CAM_ADDR_DWORDS
 
- VFC_CAM_ADDR_OP_OFFSET
 
- VFC_CAM_ADDR_OP_SIZE
 
- VFC_CAM_ADDR_STRUCT_SIZE
 
- VFC_CAM_CMD_DWORDS
 
- VFC_CAM_CMD_ROW_OFFSET
 
- VFC_CAM_CMD_ROW_SIZE
 
- VFC_CAM_CMD_STRUCT_SIZE
 
- VFC_CAM_NUM_ROWS
 
- VFC_CAM_RESP_DWORDS
 
- VFC_CAM_RESP_STRUCT_SIZE
 
- VFC_CHECKSUM_ERROR
 
- VFC_CNTL
 
- VFC_INVALID_LEN
 
- VFC_MEMORIES_RST_REG_CAM_RST
 
- VFC_MEMORIES_RST_REG_RAM_RST
 
- VFC_OPCODE_CAM_RD
 
- VFC_OPCODE_RAM_RD
 
- VFC_RAM_ADDR_DWORDS
 
- VFC_RAM_ADDR_OP_OFFSET
 
- VFC_RAM_ADDR_OP_SIZE
 
- VFC_RAM_ADDR_ROW_OFFSET
 
- VFC_RAM_ADDR_ROW_SIZE
 
- VFC_RAM_ADDR_STRUCT_SIZE
 
- VFC_RAM_CMD_DWORDS
 
- VFC_RAM_RESP_DWORDS
 
- VFC_RAM_RESP_STRUCT_SIZE
 
- VFC_REG_MEMORIES_RST
 
- VFDI_EV_DATA_LBN
 
- VFDI_EV_DATA_WIDTH
 
- VFDI_EV_SEQ_LBN
 
- VFDI_EV_SEQ_WIDTH
 
- VFDI_EV_TYPE_LBN
 
- VFDI_EV_TYPE_REQ_WORD0
 
- VFDI_EV_TYPE_REQ_WORD1
 
- VFDI_EV_TYPE_REQ_WORD2
 
- VFDI_EV_TYPE_REQ_WORD3
 
- VFDI_EV_TYPE_RESET
 
- VFDI_EV_TYPE_STATUS
 
- VFDI_EV_TYPE_WIDTH
 
- VFDI_MAC_FILTER_FLAG_RSS
 
- VFDI_MAC_FILTER_FLAG_SCATTER
 
- VFDI_OP_CLEAR_STATUS_PAGE
 
- VFDI_OP_FINI_ALL_QUEUES
 
- VFDI_OP_INIT_EVQ
 
- VFDI_OP_INIT_RXQ
 
- VFDI_OP_INIT_TXQ
 
- VFDI_OP_INSERT_FILTER
 
- VFDI_OP_LIMIT
 
- VFDI_OP_REMOVE_ALL_FILTERS
 
- VFDI_OP_RESPONSE
 
- VFDI_OP_SET_STATUS_PAGE
 
- VFDI_RC_EINVAL
 
- VFDI_RC_ENOMEM
 
- VFDI_RC_EOPNOTSUPP
 
- VFDI_RC_ETIMEDOUT
 
- VFDI_RC_SUCCESS
 
- VFDI_RXQ_FLAG_SCATTER_EN
 
- VFDI_TXQ_FLAG_IP_CSUM_DIS
 
- VFDI_TXQ_FLAG_TCPUDP_CSUM_DIS
 
- VFD_BFIFO_STALL
 
- VFD_BUSY_CYCLES
 
- VFD_FETCH_INSTRUCTIONS
 
- VFD_MODE_0_FIBERS
 
- VFD_MODE_1_FIBERS
 
- VFD_MODE_2_FIBERS
 
- VFD_MODE_3_FIBERS
 
- VFD_MODE_4_FIBERS
 
- VFD_NUM_VERTICES_TOTAL
 
- VFD_PACKER_FULL
 
- VFD_PERF_ACTIVE_CYCLES
 
- VFD_PERF_DECODE_INSTRUCTIONS
 
- VFD_PERF_FETCH_INSTRUCTIONS
 
- VFD_PERF_STALL_CYCLES_HLSQ
 
- VFD_PERF_STALL_CYCLES_UCHE
 
- VFD_PERF_STALL_CYCLES_VPC_ALLOC
 
- VFD_PERF_STALL_CYCLES_VPC_BYPASS
 
- VFD_PERF_UCHE_BYTE_FETCHED
 
- VFD_PERF_UCHE_TRANS
 
- VFD_PERF_VPC_BYPASS_COMPONENTS
 
- VFD_STALL_CYCLES_HLSQ
 
- VFD_STALL_CYCLES_UCHE
 
- VFD_STALL_CYCLES_VPC_ALLOC
 
- VFD_STALL_CYCLES_VPC_BYPASS
 
- VFD_STARVE_CYCLES_PC
 
- VFD_STARVE_CYCLES_UCHE
 
- VFD_UCHE_BYTE_FETCHED
 
- VFD_UCHE_REQUEST_FIFO_FULL
 
- VFD_UCHE_TRANS
 
- VFE0_CLK_SRC
 
- VFE0_GDSC
 
- VFE1_CLK_SRC
 
- VFE1_GDSC
 
- VFE_0_BUS_BDG_CMD
 
- VFE_0_BUS_BDG_CMD_HALT_REQ
 
- VFE_0_BUS_BDG_DS_CFG_0
 
- VFE_0_BUS_BDG_DS_CFG_0_CFG
 
- VFE_0_BUS_BDG_DS_CFG_1
 
- VFE_0_BUS_BDG_DS_CFG_10
 
- VFE_0_BUS_BDG_DS_CFG_11
 
- VFE_0_BUS_BDG_DS_CFG_12
 
- VFE_0_BUS_BDG_DS_CFG_13
 
- VFE_0_BUS_BDG_DS_CFG_14
 
- VFE_0_BUS_BDG_DS_CFG_15
 
- VFE_0_BUS_BDG_DS_CFG_16
 
- VFE_0_BUS_BDG_DS_CFG_16_CFG
 
- VFE_0_BUS_BDG_DS_CFG_2
 
- VFE_0_BUS_BDG_DS_CFG_3
 
- VFE_0_BUS_BDG_DS_CFG_4
 
- VFE_0_BUS_BDG_DS_CFG_5
 
- VFE_0_BUS_BDG_DS_CFG_6
 
- VFE_0_BUS_BDG_DS_CFG_7
 
- VFE_0_BUS_BDG_DS_CFG_8
 
- VFE_0_BUS_BDG_DS_CFG_9
 
- VFE_0_BUS_BDG_QOS_CFG_0
 
- VFE_0_BUS_BDG_QOS_CFG_0_CFG
 
- VFE_0_BUS_BDG_QOS_CFG_1
 
- VFE_0_BUS_BDG_QOS_CFG_2
 
- VFE_0_BUS_BDG_QOS_CFG_3
 
- VFE_0_BUS_BDG_QOS_CFG_4
 
- VFE_0_BUS_BDG_QOS_CFG_5
 
- VFE_0_BUS_BDG_QOS_CFG_6
 
- VFE_0_BUS_BDG_QOS_CFG_7
 
- VFE_0_BUS_BDG_QOS_CFG_7_CFG
 
- VFE_0_BUS_CFG
 
- VFE_0_BUS_CMD
 
- VFE_0_BUS_CMD_Mx_RLD_CMD
 
- VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG
 
- VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_BASED_SHIFT
 
- VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK
 
- VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_SHIFT
 
- VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG
 
- VFE_0_BUS_IMAGE_MASTER_n_WR_CFG
 
- VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_FRM_BASED_SHIFT
 
- VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT
 
- VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN
 
- VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE
 
- VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN
 
- VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF
 
- VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR
 
- VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR
 
- VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG
 
- VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG_OFFSET_SHIFT
 
- VFE_0_BUS_PING_PONG_STATUS
 
- VFE_0_BUS_XBAR_CFG_x
 
- VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN
 
- VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER
 
- VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA
 
- VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTRA
 
- VFE_0_BUS_XBAR_CFG_x_M_REALIGN_BUF_EN
 
- VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA
 
- VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT
 
- VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0
 
- VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1
 
- VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2
 
- VFE_0_CAMIF_CFG
 
- VFE_0_CAMIF_CFG_VFE_OUTPUT_EN
 
- VFE_0_CAMIF_CMD
 
- VFE_0_CAMIF_CMD_CLEAR_CAMIF_STATUS
 
- VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY
 
- VFE_0_CAMIF_CMD_ENABLE_FRAME_BOUNDARY
 
- VFE_0_CAMIF_CMD_NO_CHANGE
 
- VFE_0_CAMIF_FRAME_CFG
 
- VFE_0_CAMIF_IRQ_FRAMEDROP_PATTERN
 
- VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN
 
- VFE_0_CAMIF_STATUS
 
- VFE_0_CAMIF_STATUS_HALT
 
- VFE_0_CAMIF_SUBSAMPLE_CFG
 
- VFE_0_CAMIF_SUBSAMPLE_CFG_0
 
- VFE_0_CAMIF_WINDOW_HEIGHT_CFG
 
- VFE_0_CAMIF_WINDOW_WIDTH_CFG
 
- VFE_0_CGC_OVERRIDE_1
 
- VFE_0_CGC_OVERRIDE_1_IMAGE_Mx_CGC_OVERRIDE
 
- VFE_0_CLAMP_ENC_MAX_CFG
 
- VFE_0_CLAMP_ENC_MAX_CFG_CH0
 
- VFE_0_CLAMP_ENC_MAX_CFG_CH1
 
- VFE_0_CLAMP_ENC_MAX_CFG_CH2
 
- VFE_0_CLAMP_ENC_MIN_CFG
 
- VFE_0_CLAMP_ENC_MIN_CFG_CH0
 
- VFE_0_CLAMP_ENC_MIN_CFG_CH1
 
- VFE_0_CLAMP_ENC_MIN_CFG_CH2
 
- VFE_0_CORE_CFG
 
- VFE_0_CORE_CFG_COMPOSITE_REG_UPDATE_EN
 
- VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY
 
- VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY
 
- VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR
 
- VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB
 
- VFE_0_CROP_ENC_CBCR_HEIGHT
 
- VFE_0_CROP_ENC_CBCR_WIDTH
 
- VFE_0_CROP_ENC_Y_HEIGHT
 
- VFE_0_CROP_ENC_Y_WIDTH
 
- VFE_0_DEMUX_CFG
 
- VFE_0_DEMUX_CFG_PERIOD
 
- VFE_0_DEMUX_EVEN_CFG
 
- VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY
 
- VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY
 
- VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV
 
- VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU
 
- VFE_0_DEMUX_GAIN_0
 
- VFE_0_DEMUX_GAIN_0_CH0_EVEN
 
- VFE_0_DEMUX_GAIN_0_CH0_ODD
 
- VFE_0_DEMUX_GAIN_1
 
- VFE_0_DEMUX_GAIN_1_CH1
 
- VFE_0_DEMUX_GAIN_1_CH2
 
- VFE_0_DEMUX_ODD_CFG
 
- VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY
 
- VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY
 
- VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV
 
- VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU
 
- VFE_0_GLOBAL_RESET_CMD
 
- VFE_0_GLOBAL_RESET_CMD_BUS
 
- VFE_0_GLOBAL_RESET_CMD_BUS_BDG
 
- VFE_0_GLOBAL_RESET_CMD_BUS_MISR
 
- VFE_0_GLOBAL_RESET_CMD_CAMIF
 
- VFE_0_GLOBAL_RESET_CMD_CORE
 
- VFE_0_GLOBAL_RESET_CMD_DSP
 
- VFE_0_GLOBAL_RESET_CMD_IDLE_CGC
 
- VFE_0_GLOBAL_RESET_CMD_PM
 
- VFE_0_GLOBAL_RESET_CMD_REGISTER
 
- VFE_0_GLOBAL_RESET_CMD_TESTGEN
 
- VFE_0_GLOBAL_RESET_CMD_TIMER
 
- VFE_0_HW_VERSION
 
- VFE_0_IRQ_CLEAR_0
 
- VFE_0_IRQ_CLEAR_1
 
- VFE_0_IRQ_CMD
 
- VFE_0_IRQ_CMD_GLOBAL_CLEAR
 
- VFE_0_IRQ_COMPOSITE_MASK_0
 
- VFE_0_IRQ_MASK_0
 
- VFE_0_IRQ_MASK_0_CAMIF_EOF
 
- VFE_0_IRQ_MASK_0_CAMIF_SOF
 
- VFE_0_IRQ_MASK_0_IMAGE_COMPOSITE_DONE_n
 
- VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG
 
- VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE
 
- VFE_0_IRQ_MASK_0_RESET_ACK
 
- VFE_0_IRQ_MASK_0_line_n_REG_UPDATE
 
- VFE_0_IRQ_MASK_1
 
- VFE_0_IRQ_MASK_1_BUS_BDG_HALT_ACK
 
- VFE_0_IRQ_MASK_1_CAMIF_ERROR
 
- VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW
 
- VFE_0_IRQ_MASK_1_RDIn_SOF
 
- VFE_0_IRQ_MASK_1_VIOLATION
 
- VFE_0_IRQ_STATUS_0
 
- VFE_0_IRQ_STATUS_0_CAMIF_SOF
 
- VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n
 
- VFE_0_IRQ_STATUS_0_IMAGE_MASTER_n_PING_PONG
 
- VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE
 
- VFE_0_IRQ_STATUS_0_RESET_ACK
 
- VFE_0_IRQ_STATUS_0_line_n_REG_UPDATE
 
- VFE_0_IRQ_STATUS_1
 
- VFE_0_IRQ_STATUS_1_BUS_BDG_HALT_ACK
 
- VFE_0_IRQ_STATUS_1_RDIn_SOF
 
- VFE_0_IRQ_STATUS_1_VIOLATION
 
- VFE_0_MODULE_CFG
 
- VFE_0_MODULE_CFG_CHROMA_UPSAMPLE
 
- VFE_0_MODULE_CFG_CROP_ENC
 
- VFE_0_MODULE_CFG_DEMUX
 
- VFE_0_MODULE_CFG_SCALE_ENC
 
- VFE_0_MODULE_LENS_EN
 
- VFE_0_MODULE_LENS_EN_CHROMA_UPSAMPLE
 
- VFE_0_MODULE_LENS_EN_DEMUX
 
- VFE_0_MODULE_ZOOM_EN
 
- VFE_0_MODULE_ZOOM_EN_CROP_ENC
 
- VFE_0_MODULE_ZOOM_EN_REALIGN_BUF
 
- VFE_0_MODULE_ZOOM_EN_SCALE_ENC
 
- VFE_0_RDI_CFG_x
 
- VFE_0_RDI_CFG_x_MIPI_EN_BITS
 
- VFE_0_RDI_CFG_x_RDI_EN_BIT
 
- VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK
 
- VFE_0_RDI_CFG_x_RDI_M0_SEL_SHIFT
 
- VFE_0_RDI_CFG_x_RDI_Mr_FRAME_BASED_EN
 
- VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK
 
- VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT
 
- VFE_0_REALIGN_BUF_CFG
 
- VFE_0_REALIGN_BUF_CFG_CB_ODD_PIXEL
 
- VFE_0_REALIGN_BUF_CFG_CR_ODD_PIXEL
 
- VFE_0_REALIGN_BUF_CFG_HSUB_ENABLE
 
- VFE_0_REG_UPDATE
 
- VFE_0_REG_UPDATE_RDIn
 
- VFE_0_REG_UPDATE_line_n
 
- VFE_0_SCALE_ENC_CBCR_CFG
 
- VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE
 
- VFE_0_SCALE_ENC_CBCR_H_PHASE
 
- VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE
 
- VFE_0_SCALE_ENC_CBCR_V_PHASE
 
- VFE_0_SCALE_ENC_Y_CFG
 
- VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE
 
- VFE_0_SCALE_ENC_Y_H_PHASE
 
- VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE
 
- VFE_0_SCALE_ENC_Y_V_PHASE
 
- VFE_0_VIOLATION_STATUS
 
- VFE_AHB_CLK
 
- VFE_AHB_RESET
 
- VFE_AXI_CLK
 
- VFE_AXI_RESET
 
- VFE_CLK
 
- VFE_CSI_CLK
 
- VFE_CSI_RESET
 
- VFE_FRAME_DROP_UPDATES
 
- VFE_FRAME_DROP_VAL
 
- VFE_GDSC
 
- VFE_HALT_TIMEOUT_MS
 
- VFE_LINE_NONE
 
- VFE_LINE_PIX
 
- VFE_LINE_RDI0
 
- VFE_LINE_RDI1
 
- VFE_LINE_RDI2
 
- VFE_NEXT_SOF_MS
 
- VFE_OUTPUT_CONTINUOUS
 
- VFE_OUTPUT_IDLE
 
- VFE_OUTPUT_OFF
 
- VFE_OUTPUT_RESERVED
 
- VFE_OUTPUT_SINGLE
 
- VFE_OUTPUT_STOPPING
 
- VFE_RESET
 
- VFE_RESET_TIMEOUT_MS
 
- VFE_SRC
 
- VFF_4G_EN_B
 
- VFF_4G_SUPPORT
 
- VFF_4G_SUPPORT_CLR_B
 
- VFF_ADDR
 
- VFF_DEBUG_STATUS
 
- VFF_EN
 
- VFF_EN_B
 
- VFF_EN_CLR_B
 
- VFF_FLUSH
 
- VFF_FLUSH_B
 
- VFF_INT_EN
 
- VFF_INT_EN_CLR_B
 
- VFF_INT_FLAG
 
- VFF_LEFT_SIZE
 
- VFF_LEN
 
- VFF_RING_SIZE
 
- VFF_RING_WRAP
 
- VFF_RPT
 
- VFF_RST
 
- VFF_RX_INT_CLR_B
 
- VFF_RX_INT_EN_B
 
- VFF_RX_THRE
 
- VFF_STOP
 
- VFF_STOP_B
 
- VFF_STOP_CLR_B
 
- VFF_THRE
 
- VFF_TX_INT_CLR_B
 
- VFF_TX_INT_EN_B
 
- VFF_TX_THRE
 
- VFF_VALID_SIZE
 
- VFF_WARM_RST_B
 
- VFF_WPT
 
- VFGEN_RSTAT
 
- VFIDPERR_F
 
- VFIDPERR_S
 
- VFIDPERR_V
 
- VFIFO_ENABLE_F
 
- VFIFO_ENABLE_S
 
- VFIFO_ENABLE_V
 
- VFIFO_SIZE
 
- VFINT_DYN_CTLN
 
- VFINT_DYN_CTLN_CLEARPBA_M
 
- VFIO_API_VERSION
 
- VFIO_AP_DEV_NAME
 
- VFIO_AP_DRV_NAME
 
- VFIO_AP_ISC_INVALID
 
- VFIO_AP_MDEV_NAME_HWVIRT
 
- VFIO_AP_MDEV_TYPE_HWVIRT
 
- VFIO_AP_MODULE_NAME
 
- VFIO_AP_ROOT_NAME
 
- VFIO_BASE
 
- VFIO_CCW_ASYNC_CMD_CSCH
 
- VFIO_CCW_ASYNC_CMD_HSCH
 
- VFIO_CCW_CONFIG_REGION_INDEX
 
- VFIO_CCW_EVENT_ASYNC_REQ
 
- VFIO_CCW_EVENT_INTERRUPT
 
- VFIO_CCW_EVENT_IO_REQ
 
- VFIO_CCW_EVENT_NOT_OPER
 
- VFIO_CCW_HEX_EVENT
 
- VFIO_CCW_INDEX_TO_OFFSET
 
- VFIO_CCW_IO_IRQ_INDEX
 
- VFIO_CCW_ISC
 
- VFIO_CCW_MSG_EVENT
 
- VFIO_CCW_NUM_IRQS
 
- VFIO_CCW_NUM_REGIONS
 
- VFIO_CCW_OFFSET_MASK
 
- VFIO_CCW_OFFSET_SHIFT
 
- VFIO_CCW_OFFSET_TO_INDEX
 
- VFIO_CCW_STATE_CP_PENDING
 
- VFIO_CCW_STATE_CP_PROCESSING
 
- VFIO_CCW_STATE_IDLE
 
- VFIO_CCW_STATE_NOT_OPER
 
- VFIO_CCW_STATE_STANDBY
 
- VFIO_CCW_TRACE_EVENT
 
- VFIO_CHECK_EXTENSION
 
- VFIO_DEVICE_API_AMBA_STRING
 
- VFIO_DEVICE_API_AP_STRING
 
- VFIO_DEVICE_API_CCW_STRING
 
- VFIO_DEVICE_API_PCI_STRING
 
- VFIO_DEVICE_API_PLATFORM_STRING
 
- VFIO_DEVICE_FLAGS_AMBA
 
- VFIO_DEVICE_FLAGS_AP
 
- VFIO_DEVICE_FLAGS_CCW
 
- VFIO_DEVICE_FLAGS_PCI
 
- VFIO_DEVICE_FLAGS_PLATFORM
 
- VFIO_DEVICE_FLAGS_RESET
 
- VFIO_DEVICE_GET_GFX_DMABUF
 
- VFIO_DEVICE_GET_INFO
 
- VFIO_DEVICE_GET_IRQ_INFO
 
- VFIO_DEVICE_GET_PCI_HOT_RESET_INFO
 
- VFIO_DEVICE_GET_REGION_INFO
 
- VFIO_DEVICE_GFX_LINK_STATE_DOWN
 
- VFIO_DEVICE_GFX_LINK_STATE_UP
 
- VFIO_DEVICE_IOEVENTFD
 
- VFIO_DEVICE_IOEVENTFD_16
 
- VFIO_DEVICE_IOEVENTFD_32
 
- VFIO_DEVICE_IOEVENTFD_64
 
- VFIO_DEVICE_IOEVENTFD_8
 
- VFIO_DEVICE_IOEVENTFD_SIZE_MASK
 
- VFIO_DEVICE_PCI_HOT_RESET
 
- VFIO_DEVICE_QUERY_GFX_PLANE
 
- VFIO_DEVICE_RESET
 
- VFIO_DEVICE_SET_IRQS
 
- VFIO_DMA_CC_IOMMU
 
- VFIO_DMA_MAP_FLAG_READ
 
- VFIO_DMA_MAP_FLAG_WRITE
 
- VFIO_EEH
 
- VFIO_EEH_PE_CONFIGURE
 
- VFIO_EEH_PE_DISABLE
 
- VFIO_EEH_PE_ENABLE
 
- VFIO_EEH_PE_GET_STATE
 
- VFIO_EEH_PE_INJECT_ERR
 
- VFIO_EEH_PE_OP
 
- VFIO_EEH_PE_RESET_DEACTIVATE
 
- VFIO_EEH_PE_RESET_FUNDAMENTAL
 
- VFIO_EEH_PE_RESET_HOT
 
- VFIO_EEH_PE_STATE_NORMAL
 
- VFIO_EEH_PE_STATE_RESET
 
- VFIO_EEH_PE_STATE_STOPPED
 
- VFIO_EEH_PE_STATE_STOPPED_DMA
 
- VFIO_EEH_PE_STATE_UNAVAIL
 
- VFIO_EEH_PE_UNFREEZE_DMA
 
- VFIO_EEH_PE_UNFREEZE_IO
 
- VFIO_GET_API_VERSION
 
- VFIO_GFX_PLANE_TYPE_DMABUF
 
- VFIO_GFX_PLANE_TYPE_PROBE
 
- VFIO_GFX_PLANE_TYPE_REGION
 
- VFIO_GROUP_FLAGS_CONTAINER_SET
 
- VFIO_GROUP_FLAGS_VIABLE
 
- VFIO_GROUP_GET_DEVICE_FD
 
- VFIO_GROUP_GET_STATUS
 
- VFIO_GROUP_NOTIFY
 
- VFIO_GROUP_NOTIFY_SET_KVM
 
- VFIO_GROUP_SET_CONTAINER
 
- VFIO_GROUP_UNSET_CONTAINER
 
- VFIO_H
 
- VFIO_IOMMU_DISABLE
 
- VFIO_IOMMU_ENABLE
 
- VFIO_IOMMU_GET_INFO
 
- VFIO_IOMMU_INFO_CAPS
 
- VFIO_IOMMU_INFO_PGSIZES
 
- VFIO_IOMMU_MAP_DMA
 
- VFIO_IOMMU_NOTIFY
 
- VFIO_IOMMU_NOTIFY_DMA_UNMAP
 
- VFIO_IOMMU_SPAPR_INFO_DDW
 
- VFIO_IOMMU_SPAPR_REGISTER_MEMORY
 
- VFIO_IOMMU_SPAPR_TCE_CREATE
 
- VFIO_IOMMU_SPAPR_TCE_GET_INFO
 
- VFIO_IOMMU_SPAPR_TCE_REMOVE
 
- VFIO_IOMMU_SPAPR_UNREGISTER_MEMORY
 
- VFIO_IOMMU_TLB_SYNC_MAX
 
- VFIO_IOMMU_TYPE1_INFO_CAP_IOVA_RANGE
 
- VFIO_IOMMU_UNMAP_DMA
 
- VFIO_IRQ_INFO_AUTOMASKED
 
- VFIO_IRQ_INFO_EVENTFD
 
- VFIO_IRQ_INFO_MASKABLE
 
- VFIO_IRQ_INFO_NORESIZE
 
- VFIO_IRQ_SET_ACTION_MASK
 
- VFIO_IRQ_SET_ACTION_TRIGGER
 
- VFIO_IRQ_SET_ACTION_TYPE_MASK
 
- VFIO_IRQ_SET_ACTION_UNMASK
 
- VFIO_IRQ_SET_DATA_BOOL
 
- VFIO_IRQ_SET_DATA_EVENTFD
 
- VFIO_IRQ_SET_DATA_NONE
 
- VFIO_IRQ_SET_DATA_TYPE_MASK
 
- VFIO_MINOR
 
- VFIO_NOIOMMU_IOMMU
 
- VFIO_PCI_BAR0_REGION_INDEX
 
- VFIO_PCI_BAR1_REGION_INDEX
 
- VFIO_PCI_BAR2_REGION_INDEX
 
- VFIO_PCI_BAR3_REGION_INDEX
 
- VFIO_PCI_BAR4_REGION_INDEX
 
- VFIO_PCI_BAR5_REGION_INDEX
 
- VFIO_PCI_CONFIG_REGION_INDEX
 
- VFIO_PCI_ERR_IRQ_INDEX
 
- VFIO_PCI_INDEX_TO_OFFSET
 
- VFIO_PCI_INTX_IRQ_INDEX
 
- VFIO_PCI_IOEVENTFD_MAX
 
- VFIO_PCI_MSIX_IRQ_INDEX
 
- VFIO_PCI_MSI_IRQ_INDEX
 
- VFIO_PCI_NUM_IRQS
 
- VFIO_PCI_NUM_REGIONS
 
- VFIO_PCI_OFFSET_MASK
 
- VFIO_PCI_OFFSET_SHIFT
 
- VFIO_PCI_OFFSET_TO_INDEX
 
- VFIO_PCI_PRIVATE_H
 
- VFIO_PCI_REQ_IRQ_INDEX
 
- VFIO_PCI_ROM_REGION_INDEX
 
- VFIO_PCI_VGA_REGION_INDEX
 
- VFIO_PIN_PAGES_MAX_ENTRIES
 
- VFIO_PLATFORM_INDEX_TO_OFFSET
 
- VFIO_PLATFORM_IS_ACPI
 
- VFIO_PLATFORM_OFFSET_MASK
 
- VFIO_PLATFORM_OFFSET_SHIFT
 
- VFIO_PLATFORM_OFFSET_TO_INDEX
 
- VFIO_PLATFORM_PRIVATE_H
 
- VFIO_PLATFORM_REGION_TYPE_MMIO
 
- VFIO_PLATFORM_REGION_TYPE_PIO
 
- VFIO_REGION_INFO_CAP_MSIX_MAPPABLE
 
- VFIO_REGION_INFO_CAP_NVLINK2_LNKSPD
 
- VFIO_REGION_INFO_CAP_NVLINK2_SSATGT
 
- VFIO_REGION_INFO_CAP_SPARSE_MMAP
 
- VFIO_REGION_INFO_CAP_TYPE
 
- VFIO_REGION_INFO_FLAG_CAPS
 
- VFIO_REGION_INFO_FLAG_MMAP
 
- VFIO_REGION_INFO_FLAG_READ
 
- VFIO_REGION_INFO_FLAG_WRITE
 
- VFIO_REGION_SUBTYPE_CCW_ASYNC_CMD
 
- VFIO_REGION_SUBTYPE_GFX_EDID
 
- VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD
 
- VFIO_REGION_SUBTYPE_INTEL_IGD_HOST_CFG
 
- VFIO_REGION_SUBTYPE_INTEL_IGD_LPC_CFG
 
- VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION
 
- VFIO_REGION_SUBTYPE_NVIDIA_NVLINK2_RAM
 
- VFIO_REGION_TYPE_CCW
 
- VFIO_REGION_TYPE_GFX
 
- VFIO_REGION_TYPE_PCI_VENDOR_MASK
 
- VFIO_REGION_TYPE_PCI_VENDOR_TYPE
 
- VFIO_SET_IOMMU
 
- VFIO_SPAPR_TCE_IOMMU
 
- VFIO_SPAPR_TCE_v2_IOMMU
 
- VFIO_TYPE
 
- VFIO_TYPE1_IOMMU
 
- VFIO_TYPE1_NESTING_IOMMU
 
- VFIO_TYPE1v2_IOMMU
 
- VFIP4FOURTUPEN_F
 
- VFIP4FOURTUPEN_S
 
- VFIP4FOURTUPEN_V
 
- VFIP4TWOTUPEN_F
 
- VFIP4TWOTUPEN_S
 
- VFIP4TWOTUPEN_V
 
- VFIP6TWOTUPEN_F
 
- VFIP6TWOTUPEN_S
 
- VFIP6TWOTUPEN_V
 
- VFIX
 
- VFLAGS
 
- VFLIP
 
- VFLIP_IMG
 
- VFLIP_READY_DELAY
 
- VFLKPIDX_G
 
- VFLKPIDX_M
 
- VFLKPIDX_S
 
- VFL_DIR_M2M
 
- VFL_DIR_RX
 
- VFL_DIR_TX
 
- VFL_TYPE_GRABBER
 
- VFL_TYPE_MAX
 
- VFL_TYPE_RADIO
 
- VFL_TYPE_SDR
 
- VFL_TYPE_SUBDEV
 
- VFL_TYPE_TOUCH
 
- VFL_TYPE_VBI
 
- VFMAX
 
- VFMIN
 
- VFMT4_10_10_10_2_SINT
 
- VFMT4_10_10_10_2_SNORM
 
- VFMT4_10_10_10_2_UINT
 
- VFMT4_10_10_10_2_UNORM
 
- VFMT4_11_11_10_FLOAT
 
- VFMT4_16_16_16_16_FLOAT
 
- VFMT4_16_16_16_16_SINT
 
- VFMT4_16_16_16_16_SNORM
 
- VFMT4_16_16_16_16_UINT
 
- VFMT4_16_16_16_16_UNORM
 
- VFMT4_16_16_16_FLOAT
 
- VFMT4_16_16_16_SINT
 
- VFMT4_16_16_16_SNORM
 
- VFMT4_16_16_16_UINT
 
- VFMT4_16_16_16_UNORM
 
- VFMT4_16_16_FLOAT
 
- VFMT4_16_16_SINT
 
- VFMT4_16_16_SNORM
 
- VFMT4_16_16_UINT
 
- VFMT4_16_16_UNORM
 
- VFMT4_16_FLOAT
 
- VFMT4_16_SINT
 
- VFMT4_16_SNORM
 
- VFMT4_16_UINT
 
- VFMT4_16_UNORM
 
- VFMT4_2_10_10_10_SINT
 
- VFMT4_2_10_10_10_SNORM
 
- VFMT4_2_10_10_10_UINT
 
- VFMT4_2_10_10_10_UNORM
 
- VFMT4_32_32_32_32_FIXED
 
- VFMT4_32_32_32_32_FLOAT
 
- VFMT4_32_32_32_32_SINT
 
- VFMT4_32_32_32_32_UINT
 
- VFMT4_32_32_32_FIXED
 
- VFMT4_32_32_32_FLOAT
 
- VFMT4_32_32_32_SINT
 
- VFMT4_32_32_32_UINT
 
- VFMT4_32_32_FIXED
 
- VFMT4_32_32_FLOAT
 
- VFMT4_32_32_SINT
 
- VFMT4_32_32_UINT
 
- VFMT4_32_FIXED
 
- VFMT4_32_FLOAT
 
- VFMT4_32_SINT
 
- VFMT4_32_UINT
 
- VFMT4_8_8_8_8_SINT
 
- VFMT4_8_8_8_8_SNORM
 
- VFMT4_8_8_8_8_UINT
 
- VFMT4_8_8_8_8_UNORM
 
- VFMT4_8_8_8_SINT
 
- VFMT4_8_8_8_SNORM
 
- VFMT4_8_8_8_UINT
 
- VFMT4_8_8_8_UNORM
 
- VFMT4_8_8_SINT
 
- VFMT4_8_8_SNORM
 
- VFMT4_8_8_UINT
 
- VFMT4_8_8_UNORM
 
- VFMT4_8_SINT
 
- VFMT4_8_SNORM
 
- VFMT4_8_UINT
 
- VFMT4_8_UNORM
 
- VFMT5_10_10_10_2_SINT
 
- VFMT5_10_10_10_2_SNORM
 
- VFMT5_10_10_10_2_UINT
 
- VFMT5_10_10_10_2_UNORM
 
- VFMT5_11_11_10_FLOAT
 
- VFMT5_16_16_16_16_FLOAT
 
- VFMT5_16_16_16_16_SINT
 
- VFMT5_16_16_16_16_SNORM
 
- VFMT5_16_16_16_16_UINT
 
- VFMT5_16_16_16_16_UNORM
 
- VFMT5_16_16_16_FLOAT
 
- VFMT5_16_16_16_SINT
 
- VFMT5_16_16_16_SNORM
 
- VFMT5_16_16_16_UINT
 
- VFMT5_16_16_16_UNORM
 
- VFMT5_16_16_FLOAT
 
- VFMT5_16_16_SINT
 
- VFMT5_16_16_SNORM
 
- VFMT5_16_16_UINT
 
- VFMT5_16_16_UNORM
 
- VFMT5_16_FLOAT
 
- VFMT5_16_SINT
 
- VFMT5_16_SNORM
 
- VFMT5_16_UINT
 
- VFMT5_16_UNORM
 
- VFMT5_32_32_32_32_FIXED
 
- VFMT5_32_32_32_32_FLOAT
 
- VFMT5_32_32_32_32_SINT
 
- VFMT5_32_32_32_32_SNORM
 
- VFMT5_32_32_32_32_UINT
 
- VFMT5_32_32_32_32_UNORM
 
- VFMT5_32_32_32_FIXED
 
- VFMT5_32_32_32_FLOAT
 
- VFMT5_32_32_32_SINT
 
- VFMT5_32_32_32_SNORM
 
- VFMT5_32_32_32_UINT
 
- VFMT5_32_32_32_UNORM
 
- VFMT5_32_32_FIXED
 
- VFMT5_32_32_FLOAT
 
- VFMT5_32_32_SINT
 
- VFMT5_32_32_SNORM
 
- VFMT5_32_32_UINT
 
- VFMT5_32_32_UNORM
 
- VFMT5_32_FIXED
 
- VFMT5_32_FLOAT
 
- VFMT5_32_SINT
 
- VFMT5_32_SNORM
 
- VFMT5_32_UINT
 
- VFMT5_32_UNORM
 
- VFMT5_8_8_8_8_SINT
 
- VFMT5_8_8_8_8_SNORM
 
- VFMT5_8_8_8_8_UINT
 
- VFMT5_8_8_8_8_UNORM
 
- VFMT5_8_8_8_SINT
 
- VFMT5_8_8_8_SNORM
 
- VFMT5_8_8_8_UINT
 
- VFMT5_8_8_8_UNORM
 
- VFMT5_8_8_SINT
 
- VFMT5_8_8_SNORM
 
- VFMT5_8_8_UINT
 
- VFMT5_8_8_UNORM
 
- VFMT5_8_SINT
 
- VFMT5_8_SNORM
 
- VFMT5_8_UINT
 
- VFMT5_8_UNORM
 
- VFMT6_10_10_10_2_SINT
 
- VFMT6_10_10_10_2_SNORM
 
- VFMT6_10_10_10_2_UINT
 
- VFMT6_10_10_10_2_UNORM
 
- VFMT6_11_11_10_FLOAT
 
- VFMT6_16_16_16_16_FLOAT
 
- VFMT6_16_16_16_16_SINT
 
- VFMT6_16_16_16_16_SNORM
 
- VFMT6_16_16_16_16_UINT
 
- VFMT6_16_16_16_16_UNORM
 
- VFMT6_16_16_16_FLOAT
 
- VFMT6_16_16_16_SINT
 
- VFMT6_16_16_16_SNORM
 
- VFMT6_16_16_16_UINT
 
- VFMT6_16_16_16_UNORM
 
- VFMT6_16_16_FLOAT
 
- VFMT6_16_16_SINT
 
- VFMT6_16_16_SNORM
 
- VFMT6_16_16_UINT
 
- VFMT6_16_16_UNORM
 
- VFMT6_16_FLOAT
 
- VFMT6_16_SINT
 
- VFMT6_16_SNORM
 
- VFMT6_16_UINT
 
- VFMT6_16_UNORM
 
- VFMT6_32_32_32_32_FIXED
 
- VFMT6_32_32_32_32_FLOAT
 
- VFMT6_32_32_32_32_SINT
 
- VFMT6_32_32_32_32_SNORM
 
- VFMT6_32_32_32_32_UINT
 
- VFMT6_32_32_32_32_UNORM
 
- VFMT6_32_32_32_FIXED
 
- VFMT6_32_32_32_FLOAT
 
- VFMT6_32_32_32_SINT
 
- VFMT6_32_32_32_SNORM
 
- VFMT6_32_32_32_UINT
 
- VFMT6_32_32_32_UNORM
 
- VFMT6_32_32_FIXED
 
- VFMT6_32_32_FLOAT
 
- VFMT6_32_32_SINT
 
- VFMT6_32_32_SNORM
 
- VFMT6_32_32_UINT
 
- VFMT6_32_32_UNORM
 
- VFMT6_32_FIXED
 
- VFMT6_32_FLOAT
 
- VFMT6_32_SINT
 
- VFMT6_32_SNORM
 
- VFMT6_32_UINT
 
- VFMT6_32_UNORM
 
- VFMT6_8_8_8_8_SINT
 
- VFMT6_8_8_8_8_SNORM
 
- VFMT6_8_8_8_8_UINT
 
- VFMT6_8_8_8_8_UNORM
 
- VFMT6_8_8_8_SINT
 
- VFMT6_8_8_8_SNORM
 
- VFMT6_8_8_8_UINT
 
- VFMT6_8_8_8_UNORM
 
- VFMT6_8_8_SINT
 
- VFMT6_8_8_SNORM
 
- VFMT6_8_8_UINT
 
- VFMT6_8_8_UNORM
 
- VFMT6_8_SINT
 
- VFMT6_8_SNORM
 
- VFMT6_8_UINT
 
- VFMT6_8_UNORM
 
- VFMT_10_10_10_2_SINT
 
- VFMT_10_10_10_2_SNORM
 
- VFMT_10_10_10_2_UINT
 
- VFMT_10_10_10_2_UNORM
 
- VFMT_16_16_16_16_FLOAT
 
- VFMT_16_16_16_16_SINT
 
- VFMT_16_16_16_16_SNORM
 
- VFMT_16_16_16_16_UINT
 
- VFMT_16_16_16_16_UNORM
 
- VFMT_16_16_16_FLOAT
 
- VFMT_16_16_16_SINT
 
- VFMT_16_16_16_SNORM
 
- VFMT_16_16_16_UINT
 
- VFMT_16_16_16_UNORM
 
- VFMT_16_16_FLOAT
 
- VFMT_16_16_SINT
 
- VFMT_16_16_SNORM
 
- VFMT_16_16_UINT
 
- VFMT_16_16_UNORM
 
- VFMT_16_FLOAT
 
- VFMT_16_SINT
 
- VFMT_16_SNORM
 
- VFMT_16_UINT
 
- VFMT_16_UNORM
 
- VFMT_2_10_10_10_SINT
 
- VFMT_2_10_10_10_SNORM
 
- VFMT_2_10_10_10_UINT
 
- VFMT_2_10_10_10_UNORM
 
- VFMT_32_32_32_32_FIXED
 
- VFMT_32_32_32_32_FLOAT
 
- VFMT_32_32_32_32_SINT
 
- VFMT_32_32_32_32_UINT
 
- VFMT_32_32_32_FIXED
 
- VFMT_32_32_32_FLOAT
 
- VFMT_32_32_32_SINT
 
- VFMT_32_32_32_UINT
 
- VFMT_32_32_FIXED
 
- VFMT_32_32_FLOAT
 
- VFMT_32_32_SINT
 
- VFMT_32_32_UINT
 
- VFMT_32_FIXED
 
- VFMT_32_FLOAT
 
- VFMT_32_SINT
 
- VFMT_32_UINT
 
- VFMT_8_8_8_8_SINT
 
- VFMT_8_8_8_8_SNORM
 
- VFMT_8_8_8_8_UINT
 
- VFMT_8_8_8_8_UNORM
 
- VFMT_8_8_8_SINT
 
- VFMT_8_8_8_SNORM
 
- VFMT_8_8_8_UINT
 
- VFMT_8_8_8_UNORM
 
- VFMT_8_8_SINT
 
- VFMT_8_8_SNORM
 
- VFMT_8_8_UINT
 
- VFMT_8_8_UNORM
 
- VFMT_8_SINT
 
- VFMT_8_SNORM
 
- VFMT_8_UINT
 
- VFMT_8_UNORM
 
- VFMUNIT_CLOCK_GATE_DISABLE
 
- VFPERREN_F
 
- VFPERREN_S
 
- VFPERREN_V
 
- VFPF_ACQUIRE_CAP_100G
 
- VFPF_ACQUIRE_CAP_PHYSICAL_BAR
 
- VFPF_ACQUIRE_CAP_PRE_FP_HSI
 
- VFPF_ACQUIRE_CAP_QUEUE_QIDS
 
- VFPF_ACQUIRE_OS_ESX
 
- VFPF_ACQUIRE_OS_LINUX
 
- VFPF_ACQUIRE_OS_LINUX_USERSPACE
 
- VFPF_ACQUIRE_OS_SOLARIS
 
- VFPF_ACQUIRE_OS_WINDOWS
 
- VFPF_BULLETIN_MAC_ADDR
 
- VFPF_BULLETIN_UNTAGGED_DEFAULT
 
- VFPF_BULLETIN_UNTAGGED_DEFAULT_FORCED
 
- VFPF_INIT_FLG_STATS_COALESCE
 
- VFPF_LINK_REPORT_FULL_DUPLEX
 
- VFPF_LINK_REPORT_LINK_DOWN
 
- VFPF_LINK_REPORT_RX_FC_ON
 
- VFPF_LINK_REPORT_TX_FC_ON
 
- VFPF_MAC_FILTER
 
- VFPF_QUEUE_DROP_IP_CS_ERR
 
- VFPF_QUEUE_DROP_TCP_CS_ERR
 
- VFPF_QUEUE_DROP_TTL0
 
- VFPF_QUEUE_DROP_UDP_CS_ERR
 
- VFPF_QUEUE_FLG_CACHE_ALIGN
 
- VFPF_QUEUE_FLG_COS
 
- VFPF_QUEUE_FLG_DHC
 
- VFPF_QUEUE_FLG_HC
 
- VFPF_QUEUE_FLG_LEADING_RSS
 
- VFPF_QUEUE_FLG_OV
 
- VFPF_QUEUE_FLG_STATS
 
- VFPF_QUEUE_FLG_TPA
 
- VFPF_QUEUE_FLG_TPA_GRO
 
- VFPF_QUEUE_FLG_TPA_IPV6
 
- VFPF_QUEUE_FLG_VLAN
 
- VFPF_Q_FILTER_DEST_MAC_VALID
 
- VFPF_Q_FILTER_SET
 
- VFPF_Q_FILTER_SET_MAC
 
- VFPF_Q_FILTER_VLAN_TAG_VALID
 
- VFPF_RSS_IPV4
 
- VFPF_RSS_IPV4_TCP
 
- VFPF_RSS_IPV4_UDP
 
- VFPF_RSS_IPV6
 
- VFPF_RSS_IPV6_TCP
 
- VFPF_RSS_IPV6_UDP
 
- VFPF_RSS_MODE_DISABLED
 
- VFPF_RSS_MODE_REGULAR
 
- VFPF_RSS_SET_SRCH
 
- VFPF_RXQ_UPD_COMPLETE_CQE_FLAG
 
- VFPF_RXQ_UPD_COMPLETE_EVENT_FLAG
 
- VFPF_RXQ_UPD_INIT_SGE_DEPRECATE_FLAG
 
- VFPF_RXQ_VALID
 
- VFPF_RX_MASK_ACCEPT_ALL_MULTICAST
 
- VFPF_RX_MASK_ACCEPT_ALL_UNICAST
 
- VFPF_RX_MASK_ACCEPT_ANY_VLAN
 
- VFPF_RX_MASK_ACCEPT_BROADCAST
 
- VFPF_RX_MASK_ACCEPT_MATCHED_MULTICAST
 
- VFPF_RX_MASK_ACCEPT_MATCHED_UNICAST
 
- VFPF_RX_MASK_ACCEPT_NONE
 
- VFPF_SET_Q_FILTERS_MAC_VLAN_CHANGED
 
- VFPF_SET_Q_FILTERS_MULTICAST_CHANGED
 
- VFPF_SET_Q_FILTERS_RX_MASK_CHANGED
 
- VFPF_TPA_GRO_CONSIST_FLAG
 
- VFPF_TPA_HDR_DATA_SPLIT_FLAG
 
- VFPF_TPA_IPV4_EN_FLAG
 
- VFPF_TPA_IPV6_EN_FLAG
 
- VFPF_TPA_PKT_SPLIT_FLAG
 
- VFPF_TXQ_VALID
 
- VFPF_UPDATE_RSS_CAPS_FLAG
 
- VFPF_UPDATE_RSS_CONFIG_FLAG
 
- VFPF_UPDATE_RSS_IND_TABLE_FLAG
 
- VFPF_UPDATE_RSS_KEY_FLAG
 
- VFPF_UPDATE_SGE_DEPRECATED_FLAG
 
- VFPF_UPDATE_TPA_EN_FLAG
 
- VFPF_UPDATE_TPA_PARAM_FLAG
 
- VFPF_VLAN_FILTER
 
- VFPF_VLAN_MAC_FILTER
 
- VFPOPDESC_LENGTH_BIT
 
- VFPOPDESC_LENGTH_MASK
 
- VFPOPDESC_OPDESC_MASK
 
- VFPOPDESC_UNUSED_BIT
 
- VFPOPDESC_UNUSED_MASK
 
- VFPR
 
- VFPRTEN_F
 
- VFPRTEN_S
 
- VFPRTEN_V
 
- VFP_DENORMAL
 
- VFP_DOUBLE_EXPONENT_BITS
 
- VFP_DOUBLE_LOW_BITS
 
- VFP_DOUBLE_LOW_BITS_MASK
 
- VFP_DOUBLE_MANTISSA_BITS
 
- VFP_DOUBLE_SIGNIFICAND_QNAN
 
- VFP_EXCEPTION_ERROR
 
- VFP_FPEXC
 
- VFP_FPSCR_CTRL_MASK
 
- VFP_FPSCR_STAT_MASK
 
- VFP_INFINITY
 
- VFP_LEN
 
- VFP_MAGIC
 
- VFP_NAN
 
- VFP_NAN_FLAG
 
- VFP_NAN_SIGNAL
 
- VFP_NUMBER
 
- VFP_QNAN
 
- VFP_REG_ZERO
 
- VFP_SINGLE_EXPONENT_BITS
 
- VFP_SINGLE_LOW_BITS
 
- VFP_SINGLE_LOW_BITS_MASK
 
- VFP_SINGLE_MANTISSA_BITS
 
- VFP_SINGLE_SIGNIFICAND_QNAN
 
- VFP_SNAN
 
- VFP_STATE_SIZE
 
- VFP_STORAGE_SIZE
 
- VFP_ZERO
 
- VFP_bounce
 
- VFRDEN_F
 
- VFRDEN_S
 
- VFRDEN_V
 
- VFRDRG_F
 
- VFRDRG_S
 
- VFRDRG_V
 
- VFREQ
 
- VFS
 
- VFSOC0_LOCK
 
- VFSOC0_UNLOCK
 
- VFS_BLOCK_SIZE
 
- VFS_CAP_FLAGS_EFFECTIVE
 
- VFS_CAP_FLAGS_MASK
 
- VFS_CAP_REVISION
 
- VFS_CAP_REVISION_1
 
- VFS_CAP_REVISION_2
 
- VFS_CAP_REVISION_3
 
- VFS_CAP_REVISION_MASK
 
- VFS_CAP_REVISION_SHIFT
 
- VFS_CAP_U32
 
- VFS_CAP_U32_1
 
- VFS_CAP_U32_2
 
- VFS_CAP_U32_3
 
- VFS_I
 
- VFS_QC_MASK
 
- VFT
 
- VFTA_BLOCK_SIZE
 
- VFT_CELL_t
 
- VFT_COLUMNS
 
- VFT_SHIFT
 
- VFT_TABLE_DEFINED
 
- VFT_TABLE_t
 
- VFUEN
 
- VFUEN0
 
- VFUNIT_CLKGATE_DIS
 
- VFUPEN_F
 
- VFUPEN_S
 
- VFUPEN_V
 
- VFVLNEX_F
 
- VFVLNEX_S
 
- VFVLNEX_V
 
- VFWRADDR_G
 
- VFWRADDR_M
 
- VFWRADDR_S
 
- VFWRADDR_V
 
- VFWREN_F
 
- VFWREN_S
 
- VFWREN_V
 
- VFY_CHUNK
 
- VF_ACQUIRED
 
- VF_ACQUIRE_MAC_FILTERS
 
- VF_ACQUIRE_MC_FILTERS
 
- VF_ACQUIRE_THRESH
 
- VF_ACQUIRE_VLAN_FILTERS
 
- VF_ADC_MAX
 
- VF_BASE_MODE_OFFLOADS
 
- VF_BITWIDTH
 
- VF_CAP_SUPPORT_EXT_BULLETIN
 
- VF_CAP_SUPPORT_VLAN_FILTER
 
- VF_CFG_EXT_BULLETIN
 
- VF_CFG_STATS_COALESCE
 
- VF_CFG_VLAN_FILTER
 
- VF_DEVICE_STATUS
 
- VF_DRV_LOADED
 
- VF_DRV_MACADDR_CHANGED
 
- VF_DRV_REMOVED
 
- VF_ENABLED
 
- VF_EVFP_IOCB_TYPE
 
- VF_FREE
 
- VF_G
 
- VF_GUARDBAND
 
- VF_IDX_INVALID
 
- VF_IS_V10
 
- VF_IS_V11
 
- VF_LOST
 
- VF_M
 
- VF_MAC_CREDIT_CNT
 
- VF_MAX_RX_QUEUES
 
- VF_MAX_STATIC
 
- VF_MBX_ARQLEN
 
- VF_OS_MASK
 
- VF_OS_SHIFT
 
- VF_OS_SUBVERSION_MASK
 
- VF_OS_UNDEFINED
 
- VF_OS_WINDOWS
 
- VF_PF_CHANNEL_NOT_READY
 
- VF_PF_CHANNEL_STATE_READY
 
- VF_PF_CHANNEL_STATE_WAITING_FOR_ACK
 
- VF_PF_IF_H
 
- VF_RESET
 
- VF_RES_A_DATA_1_VF_QPC_BT_IDX_M
 
- VF_RES_A_DATA_1_VF_QPC_BT_IDX_S
 
- VF_RES_A_DATA_1_VF_QPC_BT_NUM_M
 
- VF_RES_A_DATA_1_VF_QPC_BT_NUM_S
 
- VF_RES_A_DATA_2_VF_SRQC_BT_IDX_M
 
- VF_RES_A_DATA_2_VF_SRQC_BT_IDX_S
 
- VF_RES_A_DATA_2_VF_SRQC_BT_NUM_M
 
- VF_RES_A_DATA_2_VF_SRQC_BT_NUM_S
 
- VF_RES_A_DATA_3_VF_CQC_BT_IDX_M
 
- VF_RES_A_DATA_3_VF_CQC_BT_IDX_S
 
- VF_RES_A_DATA_3_VF_CQC_BT_NUM_M
 
- VF_RES_A_DATA_3_VF_CQC_BT_NUM_S
 
- VF_RES_A_DATA_4_VF_MPT_BT_IDX_M
 
- VF_RES_A_DATA_4_VF_MPT_BT_IDX_S
 
- VF_RES_A_DATA_4_VF_MPT_BT_NUM_M
 
- VF_RES_A_DATA_4_VF_MPT_BT_NUM_S
 
- VF_RES_A_DATA_5_VF_EQC_IDX_M
 
- VF_RES_A_DATA_5_VF_EQC_IDX_S
 
- VF_RES_A_DATA_5_VF_EQC_NUM_M
 
- VF_RES_A_DATA_5_VF_EQC_NUM_S
 
- VF_RES_B_DATA_0_VF_ID_M
 
- VF_RES_B_DATA_0_VF_ID_S
 
- VF_RES_B_DATA_1_VF_SMAC_IDX_M
 
- VF_RES_B_DATA_1_VF_SMAC_IDX_S
 
- VF_RES_B_DATA_1_VF_SMAC_NUM_M
 
- VF_RES_B_DATA_1_VF_SMAC_NUM_S
 
- VF_RES_B_DATA_2_VF_SGID_IDX_M
 
- VF_RES_B_DATA_2_VF_SGID_IDX_S
 
- VF_RES_B_DATA_2_VF_SGID_NUM_M
 
- VF_RES_B_DATA_2_VF_SGID_NUM_S
 
- VF_RES_B_DATA_3_VF_QID_IDX_M
 
- VF_RES_B_DATA_3_VF_QID_IDX_S
 
- VF_RES_B_DATA_3_VF_SL_NUM_M
 
- VF_RES_B_DATA_3_VF_SL_NUM_S
 
- VF_RES_B_DATA_4_VF_SCCC_BT_IDX_M
 
- VF_RES_B_DATA_4_VF_SCCC_BT_IDX_S
 
- VF_RES_B_DATA_4_VF_SCCC_BT_NUM_M
 
- VF_RES_B_DATA_4_VF_SCCC_BT_NUM_S
 
- VF_S
 
- VF_STAT
 
- VF_STATE_DOWN
 
- VF_STATE_UP
 
- VF_STOPPED
 
- VF_SWITCH_DATA_CFG_ALW_DST_OVRD_S
 
- VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S
 
- VF_SWITCH_DATA_CFG_ALW_LPBK_S
 
- VF_SWITCH_DATA_FUN_ID_VF_ID_M
 
- VF_SWITCH_DATA_FUN_ID_VF_ID_S
 
- VF_TAKEOVER_INT
 
- VF_TRANS_PENDING_M
 
- VF_TRANS_PENDING_MASK
 
- VF_TX_FILTER_AUTO
 
- VF_TX_FILTER_OFF
 
- VF_TX_FILTER_ON
 
- VF_UART0_BASE_ADDR
 
- VF_UART1_BASE_ADDR
 
- VF_UART2_BASE_ADDR
 
- VF_UART3_BASE_ADDR
 
- VF_UART_BASE
 
- VF_UART_BASE_ADDR
 
- VF_UART_PHYSICAL_BASE
 
- VF_UART_VIRTUAL_BASE
 
- VF_UNIT_CLOCK_GATE_DISABLE
 
- VF_VALID_F
 
- VF_VALID_S
 
- VF_VALID_V
 
- VF_VLAN_CREDIT_CNT
 
- VF_ZONE_FUNC_NOT_ENABLED
 
- VF_ZONE_MSG_NOT_VALID
 
- VF_ZONE_SIZE_MODE_DEFAULT
 
- VF_ZONE_SIZE_MODE_DOUBLE
 
- VF_ZONE_SIZE_MODE_QUAD
 
- VFilter2TapInterpolate
 
- VFilter2TapNoInterpolate
 
- VFilter3TapInterpolate
 
- VFilter3TapNoInterpolate
 
- VFilter4TapInterpolate
 
- VFilter4TapNoInterpolate
 
- VFilter5TapInterpolate
 
- VFilter5TapNoInterpolate
 
- VG1
 
- VG12_PSUEDO_NUM_DCEFCLK_DPM_LEVELS
 
- VG12_PSUEDO_NUM_GFXCLK_DPM_LEVELS
 
- VG12_PSUEDO_NUM_SOCCLK_DPM_LEVELS
 
- VG12_PSUEDO_NUM_UCLK_DPM_LEVELS
 
- VG2
 
- VG20_CLOCK_MAX_DEFAULT
 
- VG20_PSUEDO_NUM_DCEFCLK_DPM_LEVELS
 
- VG20_PSUEDO_NUM_GFXCLK_DPM_LEVELS
 
- VG20_PSUEDO_NUM_SOCCLK_DPM_LEVELS
 
- VG20_PSUEDO_NUM_UCLK_DPM_LEVELS
 
- VG3
 
- VG4
 
- VG468_ATA
 
- VG468_CTL
 
- VG468_CTL_ASYNC
 
- VG468_CTL_COMPAT
 
- VG468_CTL_DELAY
 
- VG468_CTL_INPACK
 
- VG468_CTL_POLARITY
 
- VG468_CTL_SLOW
 
- VG468_CTL_TSSI
 
- VG468_GPIO_CFG
 
- VG468_MISC
 
- VG468_MISC_DMAWSB
 
- VG468_MISC_GPIO
 
- VG468_MISC_UNLOCK
 
- VG468_MISC_VADEMREV
 
- VG468_SELECT
 
- VG468_SELECT_CFG
 
- VG468_TIMER
 
- VG468_TIMER_MASK
 
- VG468_TIMER_RES
 
- VG468_TIMER_SIGEN
 
- VG468_TIMER_STATUS
 
- VG468_TIMER_ZEROPWR
 
- VG468_VPP2_12V
 
- VG468_VPP2_5V
 
- VG468_VPP2_MASK
 
- VG469_CTL_STRETCH
 
- VG469_CTL_WS_COMPAT
 
- VG469_EXT_MODE
 
- VG469_MISC_LEDENA
 
- VG469_MODE_B_3V
 
- VG469_MODE_CABLE
 
- VG469_MODE_COMPAT
 
- VG469_MODE_INT_SENSE
 
- VG469_MODE_RIO
 
- VG469_MODE_TEST
 
- VG469_MODE_VPPST
 
- VG469_VSELECT
 
- VG469_VSEL_3V
 
- VG469_VSEL_5V
 
- VG469_VSEL_EXT_BUS
 
- VG469_VSEL_EXT_STAT
 
- VG469_VSEL_ISA
 
- VG469_VSEL_MAX
 
- VG469_VSEL_MIXED
 
- VG469_VSEL_VCC
 
- VG469_VSENSE
 
- VG469_VSENSE_A_VS1
 
- VG469_VSENSE_A_VS2
 
- VG469_VSENSE_B_VS1
 
- VG469_VSENSE_B_VS2
 
- VGA
 
- VGA0
 
- VGA0_DIVISOR
 
- VGA0_PD_P1_DIV_2
 
- VGA0_PD_P1_MASK
 
- VGA0_PD_P1_SHIFT
 
- VGA0_PD_P2_DIV_4
 
- VGA0_PLL
 
- VGA1
 
- VGA1_DIVISOR
 
- VGA1_PD_P1_DIV_2
 
- VGA1_PD_P1_MASK
 
- VGA1_PD_P1_SHIFT
 
- VGA1_PD_P2_DIV_4
 
- VGA1_PLL
 
- VGA25_PPLL_ANALOG__VGA25_CAL_MODE_MASK
 
- VGA25_PPLL_ANALOG__VGA25_CAL_MODE__SHIFT
 
- VGA25_PPLL_ANALOG__VGA25_PPLL_CP_MASK
 
- VGA25_PPLL_ANALOG__VGA25_PPLL_CP__SHIFT
 
- VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS_MASK
 
- VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS__SHIFT
 
- VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE_MASK
 
- VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE__SHIFT
 
- VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL_MASK
 
- VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL__SHIFT
 
- VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL_MASK
 
- VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL__SHIFT
 
- VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_MASK
 
- VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION__SHIFT
 
- VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_MASK
 
- VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV__SHIFT
 
- VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK_MASK
 
- VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK__SHIFT
 
- VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK_MASK
 
- VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK__SHIFT
 
- VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK
 
- VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK__SHIFT
 
- VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV_MASK
 
- VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV__SHIFT
 
- VGA28_PPLL_ANALOG__VGA28_CAL_MODE_MASK
 
- VGA28_PPLL_ANALOG__VGA28_CAL_MODE__SHIFT
 
- VGA28_PPLL_ANALOG__VGA28_PPLL_CP_MASK
 
- VGA28_PPLL_ANALOG__VGA28_PPLL_CP__SHIFT
 
- VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS_MASK
 
- VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS__SHIFT
 
- VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE_MASK
 
- VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE__SHIFT
 
- VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL_MASK
 
- VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL__SHIFT
 
- VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL_MASK
 
- VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL__SHIFT
 
- VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_MASK
 
- VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION__SHIFT
 
- VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_MASK
 
- VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV__SHIFT
 
- VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK_MASK
 
- VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK__SHIFT
 
- VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK_MASK
 
- VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK__SHIFT
 
- VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK_MASK
 
- VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK__SHIFT
 
- VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV_MASK
 
- VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV__SHIFT
 
- VGA2_CONNECTED
 
- VGA41_PPLL_ANALOG__VGA41_CAL_MODE_MASK
 
- VGA41_PPLL_ANALOG__VGA41_CAL_MODE__SHIFT
 
- VGA41_PPLL_ANALOG__VGA41_PPLL_CP_MASK
 
- VGA41_PPLL_ANALOG__VGA41_PPLL_CP__SHIFT
 
- VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS_MASK
 
- VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS__SHIFT
 
- VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE_MASK
 
- VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE__SHIFT
 
- VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL_MASK
 
- VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL__SHIFT
 
- VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL_MASK
 
- VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL__SHIFT
 
- VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_MASK
 
- VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION__SHIFT
 
- VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_MASK
 
- VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV__SHIFT
 
- VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK_MASK
 
- VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK__SHIFT
 
- VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK_MASK
 
- VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK__SHIFT
 
- VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK_MASK
 
- VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK__SHIFT
 
- VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV_MASK
 
- VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV__SHIFT
 
- VGA6x11_IDX
 
- VGA8x16_IDX
 
- VGA8x8_IDX
 
- VGABASE
 
- VGACNTRL
 
- VGADCC_DBG_DCCIF_C__DBG_DCCIF_C_MASK
 
- VGADCC_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT
 
- VGAENABLE
 
- VGAGRA
 
- VGAINIT0
 
- VGAINIT0_8BIT_DAC
 
- VGAINIT0_ALT_READBACK
 
- VGAINIT0_DECODE_3C6
 
- VGAINIT0_EXTSHIFTOUT
 
- VGAINIT0_EXT_ENABLE
 
- VGAINIT0_EXT_TIMING
 
- VGAINIT0_FAST_BLINK
 
- VGAINIT0_LEGACY_DISABLE
 
- VGAINIT0_SGRAM_HBLANK_DISABLE
 
- VGAINIT0_VGA_DISABLE
 
- VGAINIT0_WAKEUP_3C3
 
- VGAINIT1
 
- VGAINIT1_MASK
 
- VGAModeIndex
 
- VGAPD
 
- VGAPD_0_P1_FORCE_DIV2
 
- VGAPD_0_P1_SHIFT
 
- VGAPD_0_P2_SHIFT
 
- VGAPD_1_P1_FORCE_DIV2
 
- VGAPD_1_P1_SHIFT
 
- VGAPD_1_P2_SHIFT
 
- VGASEQ
 
- VGA_0
 
- VGA_1
 
- VGA_128KAP_PAGING
 
- VGA_2
 
- VGA_2X_MODE
 
- VGA_3
 
- VGA_4
 
- VGA_5
 
- VGA_6
 
- VGA_6BIT_DAC
 
- VGA_7
 
- VGA_8BIT_DAC
 
- VGA_APERTURE_ENABLE
 
- VGA_AR_DATA_READ
 
- VGA_AR_DATA_WRITE
 
- VGA_AR_ENABLE_DISPLAY
 
- VGA_AR_INDEX
 
- VGA_AR_VID_EN
 
- VGA_ATC_COLOR_PAGE
 
- VGA_ATC_MODE
 
- VGA_ATC_OVERSCAN
 
- VGA_ATC_PALETTE0
 
- VGA_ATC_PALETTE1
 
- VGA_ATC_PALETTE2
 
- VGA_ATC_PALETTE3
 
- VGA_ATC_PALETTE4
 
- VGA_ATC_PALETTE5
 
- VGA_ATC_PALETTE6
 
- VGA_ATC_PALETTE7
 
- VGA_ATC_PALETTE8
 
- VGA_ATC_PALETTE9
 
- VGA_ATC_PALETTEA
 
- VGA_ATC_PALETTEB
 
- VGA_ATC_PALETTEC
 
- VGA_ATC_PALETTED
 
- VGA_ATC_PALETTEE
 
- VGA_ATC_PALETTEF
 
- VGA_ATC_PEL
 
- VGA_ATC_PLANE_ENABLE
 
- VGA_ATI_LINEAR
 
- VGA_ATT_C
 
- VGA_ATT_IW
 
- VGA_ATT_R
 
- VGA_ATT_W
 
- VGA_AUTO_DETECT_PARA
 
- VGA_AUTO_DETECT_SEL
 
- VGA_AUX_DIV_SHIFT
 
- VGA_BUFFER_CNTL
 
- VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK
 
- VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT
 
- VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK
 
- VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT
 
- VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK
 
- VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT
 
- VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK
 
- VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT
 
- VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK
 
- VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT
 
- VGA_CENTERING_ENABLE
 
- VGA_CLEAR_IRQ
 
- VGA_CLK
 
- VGA_CLK_DIV_FS
 
- VGA_CMD_CFG
 
- VGA_CMD_COMBO
 
- VGA_CMD_RW
 
- VGA_CMD_TRANS
 
- VGA_COHE_SPEC_TIMER_DIS
 
- VGA_CONFIGURATION
 
- VGA_CONFIGURATION_MODE
 
- VGA_CONFIGURATION_PLL
 
- VGA_CONFIGURATION_USER_DEFINE_MASK
 
- VGA_CR11_LOCK_CR0_CR7
 
- VGA_CR17_H_V_SIGNALS_ENABLED
 
- VGA_CRTC_CURSOR_END
 
- VGA_CRTC_CURSOR_HI
 
- VGA_CRTC_CURSOR_LO
 
- VGA_CRTC_CURSOR_START
 
- VGA_CRTC_H_BLANK_END
 
- VGA_CRTC_H_BLANK_START
 
- VGA_CRTC_H_DISP
 
- VGA_CRTC_H_SYNC_END
 
- VGA_CRTC_H_SYNC_START
 
- VGA_CRTC_H_TOTAL
 
- VGA_CRTC_LINE_COMPARE
 
- VGA_CRTC_MAX_SCAN
 
- VGA_CRTC_MODE
 
- VGA_CRTC_OFFSET
 
- VGA_CRTC_OVERFLOW
 
- VGA_CRTC_PRESET_ROW
 
- VGA_CRTC_REGS
 
- VGA_CRTC_START_HI
 
- VGA_CRTC_START_LO
 
- VGA_CRTC_UNDERLINE
 
- VGA_CRTC_V_BLANK_END
 
- VGA_CRTC_V_BLANK_START
 
- VGA_CRTC_V_DISP_END
 
- VGA_CRTC_V_SYNC_END
 
- VGA_CRTC_V_SYNC_START
 
- VGA_CRTC_V_TOTAL
 
- VGA_CRT_C
 
- VGA_CRT_DC
 
- VGA_CRT_DM
 
- VGA_CRT_IC
 
- VGA_CRT_IM
 
- VGA_CR_DATA
 
- VGA_CR_DATA_CGA
 
- VGA_CR_DATA_MDA
 
- VGA_CR_INDEX_CGA
 
- VGA_CR_INDEX_MDA
 
- VGA_CR_IX
 
- VGA_DACDATA
 
- VGA_DACMASK
 
- VGA_DACRX
 
- VGA_DACWX
 
- VGA_DAC_MASK
 
- VGA_DATA
 
- VGA_DDA_CONFIG
 
- VGA_DDA_ON_OFF
 
- VGA_DDC_CLK_INPUT
 
- VGA_DDC_CLK_OUTPUT
 
- VGA_DDC_CLK_OUT_EN
 
- VGA_DDC_DATA_INPUT
 
- VGA_DDC_DATA_OUTPUT
 
- VGA_DDC_DATA_OUT_EN
 
- VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA_MASK
 
- VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA__SHIFT
 
- VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX_MASK
 
- VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX__SHIFT
 
- VGA_DEFAULT_DEVICE
 
- VGA_DETECT_SEL_HAS_DEVICE
 
- VGA_DETECT_SEL_NO_DEVICE
 
- VGA_DEVICE_ADDR
 
- VGA_DEVICE_CONNECTED
 
- VGA_DEVICE_DISCONNECTED
 
- VGA_DISABLE
 
- VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK
 
- VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT
 
- VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK
 
- VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT
 
- VGA_DISP_DISABLE
 
- VGA_DSP_CONFIG
 
- VGA_DSP_OFF
 
- VGA_DSP_ON
 
- VGA_DSP_ON_OFF
 
- VGA_DSP_XCLKS_PER_QW
 
- VGA_EN
 
- VGA_ENABLE
 
- VGA_FAST_MODE_DISABLE
 
- VGA_FB_PHYS
 
- VGA_FB_PHYS_LEN
 
- VGA_FONTWIDTH
 
- VGA_FTC_R
 
- VGA_GAIN
 
- VGA_GFX_BIT_MASK
 
- VGA_GFX_C
 
- VGA_GFX_COMPARE_MASK
 
- VGA_GFX_COMPARE_VALUE
 
- VGA_GFX_D
 
- VGA_GFX_DATA_ROTATE
 
- VGA_GFX_I
 
- VGA_GFX_MISC
 
- VGA_GFX_MODE
 
- VGA_GFX_PLANE_READ
 
- VGA_GFX_SR_ENABLE
 
- VGA_GFX_SR_VALUE
 
- VGA_GR06_GRAPHICS_MODE
 
- VGA_GR_DATA
 
- VGA_GR_INDEX
 
- VGA_GR_MEM_A0000_AFFFF
 
- VGA_GR_MEM_A0000_BFFFF
 
- VGA_GR_MEM_B0000_B7FFF
 
- VGA_GR_MEM_B0000_BFFFF
 
- VGA_GR_MEM_MODE_MASK
 
- VGA_GR_MEM_MODE_SHIFT
 
- VGA_GR_MEM_READ_MODE_PLANE
 
- VGA_GR_MEM_READ_MODE_SHIFT
 
- VGA_HDP_CONTROL
 
- VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK
 
- VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT
 
- VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK
 
- VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT
 
- VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK
 
- VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT
 
- VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK
 
- VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT
 
- VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK
 
- VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT
 
- VGA_HEIGHT
 
- VGA_HS
 
- VGA_HW_DEBUG__VGA_HW_DEBUG_MASK
 
- VGA_HW_DEBUG__VGA_HW_DEBUG__SHIFT
 
- VGA_I2C_STATUS
 
- VGA_I2C_WCLK
 
- VGA_IH_SRC_ID_END
 
- VGA_IH_SRC_ID_START
 
- VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK
 
- VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT
 
- VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK
 
- VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT
 
- VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK
 
- VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT
 
- VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK
 
- VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT
 
- VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK
 
- VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT
 
- VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK
 
- VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT
 
- VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK
 
- VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT
 
- VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK
 
- VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT
 
- VGA_IS1_RC
 
- VGA_IS1_RM
 
- VGA_LEGACY_PALETTE
 
- VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK
 
- VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT
 
- VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK
 
- VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT
 
- VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK
 
- VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT
 
- VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY_MASK
 
- VGA_MAIN_CONTROL__VGA_MC_WRITE_CLEAN_WAIT_DELAY__SHIFT
 
- VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK
 
- VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT
 
- VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK
 
- VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT
 
- VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK
 
- VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT
 
- VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK
 
- VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT
 
- VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE_MASK
 
- VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE__SHIFT
 
- VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK
 
- VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT
 
- VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK
 
- VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT
 
- VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE_MASK
 
- VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE__SHIFT
 
- VGA_MAIN_DIV_SHIFT
 
- VGA_MAP_MEM
 
- VGA_MEM
 
- VGA_MEMORY_BASE_ADDRESS
 
- VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK
 
- VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT
 
- VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK
 
- VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT
 
- VGA_MEMORY_DISABLE
 
- VGA_MEM_PAGE_SELECT_EN
 
- VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK
 
- VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT
 
- VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK
 
- VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT
 
- VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK
 
- VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT
 
- VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK
 
- VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT
 
- VGA_MIS_C
 
- VGA_MIS_COLOR
 
- VGA_MIS_DCLK_28322_720
 
- VGA_MIS_ENB_MEM_ACCESS
 
- VGA_MIS_ENB_PLL_LOAD
 
- VGA_MIS_R
 
- VGA_MIS_SEL_HIGH_PAGE
 
- VGA_MIS_W
 
- VGA_MODE
 
- VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK
 
- VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT
 
- VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK
 
- VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT
 
- VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT_MASK
 
- VGA_MODE_CONTROL__VGA_DEEP_SLEEP_FORCE_EXIT__SHIFT
 
- VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK
 
- VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT
 
- VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK
 
- VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT
 
- VGA_MSR_CGA_MODE
 
- VGA_MSR_MEM_EN
 
- VGA_MSR_READ
 
- VGA_MSR_WRITE
 
- VGA_NO_WRAP
 
- VGA_OFFSET_POLARITY
 
- VGA_OUT16VAL
 
- VGA_OUTW_WRITE
 
- VGA_PALETTE_A_WRITE_DISABLE
 
- VGA_PALETTE_B_WRITE_DISABLE
 
- VGA_PALETTE_READ_SELECT
 
- VGA_PD
 
- VGA_PEL_D
 
- VGA_PEL_IR
 
- VGA_PEL_IW
 
- VGA_PEL_MSK
 
- VGA_PIPE_B_SELECT
 
- VGA_PIPE_SELECT_SHIFT
 
- VGA_PLL0_CTRL
 
- VGA_PLL1_CTRL
 
- VGA_PORT_HGSMI_GUEST
 
- VGA_PORT_HGSMI_HOST
 
- VGA_QOS_CTRL__VGA_READ_QOS_MASK
 
- VGA_QOS_CTRL__VGA_READ_QOS__SHIFT
 
- VGA_QOS_CTRL__VGA_WRITE_QOS_MASK
 
- VGA_QOS_CTRL__VGA_WRITE_QOS__SHIFT
 
- VGA_RBBM_LOCK_DISABLE
 
- VGA_RD08
 
- VGA_REGSET_END
 
- VGA_REGSET_END_VAL
 
- VGA_RENDER_CONTROL
 
- VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK
 
- VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT
 
- VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK
 
- VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT
 
- VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK
 
- VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT
 
- VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK
 
- VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT
 
- VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK
 
- VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT
 
- VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK
 
- VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT
 
- VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK
 
- VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT
 
- VGA_RSRC_LEGACY_IO
 
- VGA_RSRC_LEGACY_MASK
 
- VGA_RSRC_LEGACY_MEM
 
- VGA_RSRC_NONE
 
- VGA_RSRC_NORMAL_IO
 
- VGA_RSRC_NORMAL_MEM
 
- VGA_RXF_COUNT_MASK
 
- VGA_RXF_COUNT_SHIFT
 
- VGA_RXF_CTRL
 
- VGA_RXF_STATUS
 
- VGA_RX_FIFO_CLEAR
 
- VGA_SAVE_CMAP
 
- VGA_SAVE_FONT0
 
- VGA_SAVE_FONT1
 
- VGA_SAVE_FONTS
 
- VGA_SAVE_MODE
 
- VGA_SAVE_TEXT
 
- VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK
 
- VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT
 
- VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK
 
- VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT
 
- VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK
 
- VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT
 
- VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK
 
- VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT
 
- VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK
 
- VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT
 
- VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK
 
- VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT
 
- VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK
 
- VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT
 
- VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK
 
- VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT
 
- VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK
 
- VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT
 
- VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK
 
- VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT
 
- VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK
 
- VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT
 
- VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK
 
- VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT
 
- VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK
 
- VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT
 
- VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK
 
- VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT
 
- VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK
 
- VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT
 
- VGA_SEQ_C
 
- VGA_SEQ_CHARACTER_MAP
 
- VGA_SEQ_CLOCK_MODE
 
- VGA_SEQ_D
 
- VGA_SEQ_I
 
- VGA_SEQ_MEMORY_MODE
 
- VGA_SEQ_PLANE_WRITE
 
- VGA_SEQ_RESET
 
- VGA_SIZE
 
- VGA_SOFT_RESET
 
- VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK
 
- VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT
 
- VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK
 
- VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT
 
- VGA_SR01_CHAR_CLK_8DOTS
 
- VGA_SR01_SCREEN_OFF
 
- VGA_SR02_ALL_PLANES
 
- VGA_SR04_CHN_4M
 
- VGA_SR04_EXT_MEM
 
- VGA_SR04_SEQ_MODE
 
- VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL_MASK
 
- VGA_SRC_SPLIT_CNTL__VGA_SPLIT_SEL__SHIFT
 
- VGA_SR_DATA
 
- VGA_SR_INDEX
 
- VGA_ST01_CGA
 
- VGA_ST01_MDA
 
- VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK
 
- VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT
 
- VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK
 
- VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT
 
- VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK
 
- VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT
 
- VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK
 
- VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT
 
- VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK
 
- VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT
 
- VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK
 
- VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT
 
- VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK
 
- VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT
 
- VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK
 
- VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT
 
- VGA_SUB_ADDR
 
- VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK
 
- VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT
 
- VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK
 
- VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT
 
- VGA_SWITCHEROO_CAN_SWITCH_DDC
 
- VGA_SWITCHEROO_DIS
 
- VGA_SWITCHEROO_IGD
 
- VGA_SWITCHEROO_MAX_CLIENTS
 
- VGA_SWITCHEROO_NEEDS_EDP_CONFIG
 
- VGA_SWITCHEROO_NOT_FOUND
 
- VGA_SWITCHEROO_OFF
 
- VGA_SWITCHEROO_ON
 
- VGA_SWITCHEROO_UNKNOWN_ID
 
- VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK
 
- VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT
 
- VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK
 
- VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT
 
- VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK
 
- VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT
 
- VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK
 
- VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT
 
- VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA_MASK
 
- VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA__SHIFT
 
- VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX_MASK
 
- VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX__SHIFT
 
- VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN_MASK
 
- VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN__SHIFT
 
- VGA_THRESH_DFE
 
- VGA_TRANS_DONE
 
- VGA_VS
 
- VGA_VSTATUS_CNTL
 
- VGA_VSTATUS_CNTL_MASK
 
- VGA_WIDTH
 
- VGA_WR08
 
- VGA_WRAP_AT_256KB
 
- VGA_WRAP_MODE
 
- VGA__MEM_PG
 
- VGA__MEM_PG__0
 
- VGAdisablePalette
 
- VGAenablePalette
 
- VGArCR
 
- VGArGR
 
- VGArSEQ
 
- VGAwATTR
 
- VGAwCR
 
- VGAwGR
 
- VGAwMISC
 
- VGAwSEQ
 
- VGCF_I387_VALID
 
- VGCF_IN_KERNEL
 
- VGCF_IN_SYSCALL
 
- VGCF_failsafe_disables_events
 
- VGCF_i387_valid
 
- VGCF_in_kernel
 
- VGCF_in_syscall
 
- VGCF_online
 
- VGCF_syscall_disables_events
 
- VGEM_FENCE_TIMEOUT
 
- VGEM_FENCE_WRITE
 
- VGIC_ACCESS_32bit
 
- VGIC_ACCESS_64bit
 
- VGIC_ACCESS_8bit
 
- VGIC_ADDR_IRQ_MASK
 
- VGIC_ADDR_TO_INTID
 
- VGIC_ADDR_UNDEF
 
- VGIC_AFFINITY_0_MASK
 
- VGIC_AFFINITY_0_SHIFT
 
- VGIC_AFFINITY_1_MASK
 
- VGIC_AFFINITY_1_SHIFT
 
- VGIC_AFFINITY_2_MASK
 
- VGIC_AFFINITY_2_SHIFT
 
- VGIC_AFFINITY_3_MASK
 
- VGIC_AFFINITY_3_SHIFT
 
- VGIC_AFFINITY_LEVEL
 
- VGIC_CONFIG_EDGE
 
- VGIC_CONFIG_LEVEL
 
- VGIC_LEVEL_INFO_LINE_LEVEL
 
- VGIC_MAX_PRIVATE
 
- VGIC_MAX_RESERVED
 
- VGIC_MAX_SPI
 
- VGIC_MIN_LPI
 
- VGIC_NR_IRQS_LEGACY
 
- VGIC_NR_PPIS
 
- VGIC_NR_PRIVATE_IRQS
 
- VGIC_NR_SGIS
 
- VGIC_PRI_BITS
 
- VGIC_TO_MPIDR
 
- VGIC_V2
 
- VGIC_V2_MAX_CPUS
 
- VGIC_V2_MAX_LRS
 
- VGIC_V3
 
- VGIC_V3_LR_INDEX
 
- VGIC_V3_MAX_CPUS
 
- VGIC_V3_MAX_LRS
 
- VGPU_MAX_WEIGHT
 
- VGPU_WEIGHT
 
- VGT_BUSY
 
- VGT_BUSY_NO_DMA
 
- VGT_CACHE_INVALIDATION
 
- VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK
 
- VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT
 
- VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK
 
- VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT
 
- VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK
 
- VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT
 
- VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK
 
- VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT
 
- VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI_MASK
 
- VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_EOI__SHIFT
 
- VGT_CACHE_INVALIDATION__ENABLE_PING_PONG_MASK
 
- VGT_CACHE_INVALIDATION__ENABLE_PING_PONG__SHIFT
 
- VGT_CACHE_INVALIDATION__EN_WAVE_MERGE_MASK
 
- VGT_CACHE_INVALIDATION__EN_WAVE_MERGE__SHIFT
 
- VGT_CACHE_INVALIDATION__ES_LIMIT_MASK
 
- VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT
 
- VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK
 
- VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT
 
- VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1_MASK
 
- VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_1__SHIFT
 
- VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2_MASK
 
- VGT_CACHE_INVALIDATION__OPT_FLOW_CNTL_2__SHIFT
 
- VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK
 
- VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT
 
- VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK
 
- VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT
 
- VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK
 
- VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT
 
- VGT_CACHE_INVALID_MODE
 
- VGT_CAPS_FULL_PPGTT
 
- VGT_CAPS_HUGE_GTT
 
- VGT_CAPS_HWSP_EMULATION
 
- VGT_CNTL_STATUS__VGT_BUSY_MASK
 
- VGT_CNTL_STATUS__VGT_BUSY__SHIFT
 
- VGT_CNTL_STATUS__VGT_GS_BUSY_MASK
 
- VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT
 
- VGT_CNTL_STATUS__VGT_HS_BUSY_MASK
 
- VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT
 
- VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK
 
- VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT
 
- VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK
 
- VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT
 
- VGT_CNTL_STATUS__VGT_PI_BUSY_MASK
 
- VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT
 
- VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY_MASK
 
- VGT_CNTL_STATUS__VGT_PRIMGEN_BUSY__SHIFT
 
- VGT_CNTL_STATUS__VGT_PT_BUSY_MASK
 
- VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT
 
- VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK
 
- VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT
 
- VGT_CNTL_STATUS__VGT_TE_BUSY_MASK
 
- VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT
 
- VGT_CNTL_STATUS__VGT_VR_BUSY_MASK
 
- VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT
 
- VGT_COMPUTE_DIM_X
 
- VGT_COMPUTE_DIM_Y
 
- VGT_COMPUTE_DIM_Z
 
- VGT_COMPUTE_INDEX
 
- VGT_COMPUTE_START_X
 
- VGT_COMPUTE_START_Y
 
- VGT_COMPUTE_START_Z
 
- VGT_COMPUTE_THREAD_GROUP_SIZE
 
- VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK
 
- VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT
 
- VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B_MASK
 
- VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B__SHIFT
 
- VGT_DEBUG_DATA__DATA_MASK
 
- VGT_DEBUG_DATA__DATA__SHIFT
 
- VGT_DEBUG_REG0__SPARE0_MASK
 
- VGT_DEBUG_REG0__SPARE0__SHIFT
 
- VGT_DEBUG_REG0__SPARE10_MASK
 
- VGT_DEBUG_REG0__SPARE10__SHIFT
 
- VGT_DEBUG_REG0__SPARE1_MASK
 
- VGT_DEBUG_REG0__SPARE1__SHIFT
 
- VGT_DEBUG_REG0__SPARE2_MASK
 
- VGT_DEBUG_REG0__SPARE2__SHIFT
 
- VGT_DEBUG_REG0__SPARE3_MASK
 
- VGT_DEBUG_REG0__SPARE3__SHIFT
 
- VGT_DEBUG_REG0__SPARE4_MASK
 
- VGT_DEBUG_REG0__SPARE4__SHIFT
 
- VGT_DEBUG_REG0__SPARE5_MASK
 
- VGT_DEBUG_REG0__SPARE5__SHIFT
 
- VGT_DEBUG_REG0__SPARE6_MASK
 
- VGT_DEBUG_REG0__SPARE6__SHIFT
 
- VGT_DEBUG_REG0__SPARE7_MASK
 
- VGT_DEBUG_REG0__SPARE7__SHIFT
 
- VGT_DEBUG_REG0__SPARE8_MASK
 
- VGT_DEBUG_REG0__SPARE8__SHIFT
 
- VGT_DEBUG_REG0__SPARE9_MASK
 
- VGT_DEBUG_REG0__SPARE9__SHIFT
 
- VGT_DEBUG_REG0__cm_busy_MASK
 
- VGT_DEBUG_REG0__cm_busy__SHIFT
 
- VGT_DEBUG_REG0__combined_out_busy_MASK
 
- VGT_DEBUG_REG0__combined_out_busy__SHIFT
 
- VGT_DEBUG_REG0__core_clk_busy_MASK
 
- VGT_DEBUG_REG0__core_clk_busy__SHIFT
 
- VGT_DEBUG_REG0__frmt_busy_MASK
 
- VGT_DEBUG_REG0__frmt_busy__SHIFT
 
- VGT_DEBUG_REG0__gog_busy_MASK
 
- VGT_DEBUG_REG0__gog_busy__SHIFT
 
- VGT_DEBUG_REG0__gs_busy_MASK
 
- VGT_DEBUG_REG0__gs_busy__SHIFT
 
- VGT_DEBUG_REG0__gs_clk_busy_MASK
 
- VGT_DEBUG_REG0__gs_clk_busy__SHIFT
 
- VGT_DEBUG_REG0__pa_interfaces_busy_MASK
 
- VGT_DEBUG_REG0__pa_interfaces_busy__SHIFT
 
- VGT_DEBUG_REG0__pi_busy_MASK
 
- VGT_DEBUG_REG0__pi_busy__SHIFT
 
- VGT_DEBUG_REG0__pt_pi_busy_MASK
 
- VGT_DEBUG_REG0__pt_pi_busy__SHIFT
 
- VGT_DEBUG_REG0__rcm_busy_MASK
 
- VGT_DEBUG_REG0__rcm_busy__SHIFT
 
- VGT_DEBUG_REG0__reg_clk_busy_MASK
 
- VGT_DEBUG_REG0__reg_clk_busy__SHIFT
 
- VGT_DEBUG_REG0__sclk_core_vld_MASK
 
- VGT_DEBUG_REG0__sclk_core_vld__SHIFT
 
- VGT_DEBUG_REG0__sclk_gs_vld_MASK
 
- VGT_DEBUG_REG0__sclk_gs_vld__SHIFT
 
- VGT_DEBUG_REG0__spi_vs_interfaces_busy_MASK
 
- VGT_DEBUG_REG0__spi_vs_interfaces_busy__SHIFT
 
- VGT_DEBUG_REG0__te11_pi_busy_MASK
 
- VGT_DEBUG_REG0__te11_pi_busy__SHIFT
 
- VGT_DEBUG_REG0__te_pi_busy_MASK
 
- VGT_DEBUG_REG0__te_pi_busy__SHIFT
 
- VGT_DEBUG_REG0__tm_busy_MASK
 
- VGT_DEBUG_REG0__tm_busy__SHIFT
 
- VGT_DEBUG_REG0__vgt_busy_MASK
 
- VGT_DEBUG_REG0__vgt_busy__SHIFT
 
- VGT_DEBUG_REG0__vgt_busy_extended_MASK
 
- VGT_DEBUG_REG0__vgt_busy_extended__SHIFT
 
- VGT_DEBUG_REG0__vr_pi_busy_MASK
 
- VGT_DEBUG_REG0__vr_pi_busy__SHIFT
 
- VGT_DEBUG_REG10__SPARE2_MASK
 
- VGT_DEBUG_REG10__SPARE2__SHIFT
 
- VGT_DEBUG_REG10__eopg_r2_q_MASK
 
- VGT_DEBUG_REG10__eopg_r2_q__SHIFT
 
- VGT_DEBUG_REG10__eotg_r2_q_MASK
 
- VGT_DEBUG_REG10__eotg_r2_q__SHIFT
 
- VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0_MASK
 
- VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0__SHIFT
 
- VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0_MASK
 
- VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0__SHIFT
 
- VGT_DEBUG_REG10__index_buffer_depth_r1_q_MASK
 
- VGT_DEBUG_REG10__index_buffer_depth_r1_q__SHIFT
 
- VGT_DEBUG_REG10__onchip_gs_en_r0_q_MASK
 
- VGT_DEBUG_REG10__onchip_gs_en_r0_q__SHIFT
 
- VGT_DEBUG_REG10__rcm_mem_gsprim_re_q_MASK
 
- VGT_DEBUG_REG10__rcm_mem_gsprim_re_q__SHIFT
 
- VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq_MASK
 
- VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq__SHIFT
 
- VGT_DEBUG_REG11__SPARE0_MASK
 
- VGT_DEBUG_REG11__SPARE0__SHIFT
 
- VGT_DEBUG_REG11__SPARE1_MASK
 
- VGT_DEBUG_REG11__SPARE1__SHIFT
 
- VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q_MASK
 
- VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q__SHIFT
 
- VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q_MASK
 
- VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q__SHIFT
 
- VGT_DEBUG_REG11__counters_avail_r0_MASK
 
- VGT_DEBUG_REG11__counters_avail_r0__SHIFT
 
- VGT_DEBUG_REG11__counters_available_r0_MASK
 
- VGT_DEBUG_REG11__counters_available_r0__SHIFT
 
- VGT_DEBUG_REG11__counters_busy_r0_MASK
 
- VGT_DEBUG_REG11__counters_busy_r0__SHIFT
 
- VGT_DEBUG_REG11__es_r0_rtr_MASK
 
- VGT_DEBUG_REG11__es_r0_rtr__SHIFT
 
- VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy_MASK
 
- VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy__SHIFT
 
- VGT_DEBUG_REG11__es_rb_dealloc_fifo_full_MASK
 
- VGT_DEBUG_REG11__es_rb_dealloc_fifo_full__SHIFT
 
- VGT_DEBUG_REG11__es_rb_roll_over_r3_MASK
 
- VGT_DEBUG_REG11__es_rb_roll_over_r3__SHIFT
 
- VGT_DEBUG_REG11__es_tbl_empty_MASK
 
- VGT_DEBUG_REG11__es_tbl_empty__SHIFT
 
- VGT_DEBUG_REG11__gog_tm_vs_event_rtr_MASK
 
- VGT_DEBUG_REG11__gog_tm_vs_event_rtr__SHIFT
 
- VGT_DEBUG_REG11__gs_issue_rtr_MASK
 
- VGT_DEBUG_REG11__gs_issue_rtr__SHIFT
 
- VGT_DEBUG_REG11__gs_r0_rtr_MASK
 
- VGT_DEBUG_REG11__gs_r0_rtr__SHIFT
 
- VGT_DEBUG_REG11__hold_eswave_MASK
 
- VGT_DEBUG_REG11__hold_eswave__SHIFT
 
- VGT_DEBUG_REG11__no_active_states_r0_MASK
 
- VGT_DEBUG_REG11__no_active_states_r0__SHIFT
 
- VGT_DEBUG_REG11__send_event_q_MASK
 
- VGT_DEBUG_REG11__send_event_q__SHIFT
 
- VGT_DEBUG_REG11__spi_esthread_fifo_busy_MASK
 
- VGT_DEBUG_REG11__spi_esthread_fifo_busy__SHIFT
 
- VGT_DEBUG_REG11__spi_gsthread_fifo_busy_MASK
 
- VGT_DEBUG_REG11__spi_gsthread_fifo_busy__SHIFT
 
- VGT_DEBUG_REG11__tm_busy_q_MASK
 
- VGT_DEBUG_REG11__tm_busy_q__SHIFT
 
- VGT_DEBUG_REG11__tm_noif_busy_q_MASK
 
- VGT_DEBUG_REG11__tm_noif_busy_q__SHIFT
 
- VGT_DEBUG_REG11__tm_out_busy_q_MASK
 
- VGT_DEBUG_REG11__tm_out_busy_q__SHIFT
 
- VGT_DEBUG_REG11__tm_pt_event_rtr_MASK
 
- VGT_DEBUG_REG11__tm_pt_event_rtr__SHIFT
 
- VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr_MASK
 
- VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr__SHIFT
 
- VGT_DEBUG_REG11__tm_rcm_gs_event_rtr_MASK
 
- VGT_DEBUG_REG11__tm_rcm_gs_event_rtr__SHIFT
 
- VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr_MASK
 
- VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr__SHIFT
 
- VGT_DEBUG_REG11__vs_dealloc_tbl_busy_MASK
 
- VGT_DEBUG_REG11__vs_dealloc_tbl_busy__SHIFT
 
- VGT_DEBUG_REG11__vs_dealloc_tbl_full_MASK
 
- VGT_DEBUG_REG11__vs_dealloc_tbl_full__SHIFT
 
- VGT_DEBUG_REG11__vs_event_fifo_empty_MASK
 
- VGT_DEBUG_REG11__vs_event_fifo_empty__SHIFT
 
- VGT_DEBUG_REG11__vs_event_fifo_full_MASK
 
- VGT_DEBUG_REG11__vs_event_fifo_full__SHIFT
 
- VGT_DEBUG_REG11__vs_event_fifo_rtr_MASK
 
- VGT_DEBUG_REG11__vs_event_fifo_rtr__SHIFT
 
- VGT_DEBUG_REG12__SPARE0_MASK
 
- VGT_DEBUG_REG12__SPARE0__SHIFT
 
- VGT_DEBUG_REG12__gs_state0_r0_q_MASK
 
- VGT_DEBUG_REG12__gs_state0_r0_q__SHIFT
 
- VGT_DEBUG_REG12__gs_state1_r0_q_MASK
 
- VGT_DEBUG_REG12__gs_state1_r0_q__SHIFT
 
- VGT_DEBUG_REG12__gs_state2_r0_q_MASK
 
- VGT_DEBUG_REG12__gs_state2_r0_q__SHIFT
 
- VGT_DEBUG_REG12__gs_state3_r0_q_MASK
 
- VGT_DEBUG_REG12__gs_state3_r0_q__SHIFT
 
- VGT_DEBUG_REG12__gs_state4_r0_q_MASK
 
- VGT_DEBUG_REG12__gs_state4_r0_q__SHIFT
 
- VGT_DEBUG_REG12__gs_state5_r0_q_MASK
 
- VGT_DEBUG_REG12__gs_state5_r0_q__SHIFT
 
- VGT_DEBUG_REG12__gs_state6_r0_q_MASK
 
- VGT_DEBUG_REG12__gs_state6_r0_q__SHIFT
 
- VGT_DEBUG_REG12__gs_state7_r0_q_MASK
 
- VGT_DEBUG_REG12__gs_state7_r0_q__SHIFT
 
- VGT_DEBUG_REG12__gs_state8_r0_q_MASK
 
- VGT_DEBUG_REG12__gs_state8_r0_q__SHIFT
 
- VGT_DEBUG_REG12__gs_state9_r0_q_MASK
 
- VGT_DEBUG_REG12__gs_state9_r0_q__SHIFT
 
- VGT_DEBUG_REG12__hold_eswave_eop_MASK
 
- VGT_DEBUG_REG12__hold_eswave_eop__SHIFT
 
- VGT_DEBUG_REG13__SPARE0_MASK
 
- VGT_DEBUG_REG13__SPARE0__SHIFT
 
- VGT_DEBUG_REG13__SPARE1_MASK
 
- VGT_DEBUG_REG13__SPARE1__SHIFT
 
- VGT_DEBUG_REG13__active_cm_sm_r0_q_MASK
 
- VGT_DEBUG_REG13__active_cm_sm_r0_q__SHIFT
 
- VGT_DEBUG_REG13__es_tbl_full_MASK
 
- VGT_DEBUG_REG13__es_tbl_full__SHIFT
 
- VGT_DEBUG_REG13__gs_state10_r0_q_MASK
 
- VGT_DEBUG_REG13__gs_state10_r0_q__SHIFT
 
- VGT_DEBUG_REG13__gs_state11_r0_q_MASK
 
- VGT_DEBUG_REG13__gs_state11_r0_q__SHIFT
 
- VGT_DEBUG_REG13__gs_state12_r0_q_MASK
 
- VGT_DEBUG_REG13__gs_state12_r0_q__SHIFT
 
- VGT_DEBUG_REG13__gs_state13_r0_q_MASK
 
- VGT_DEBUG_REG13__gs_state13_r0_q__SHIFT
 
- VGT_DEBUG_REG13__gs_state14_r0_q_MASK
 
- VGT_DEBUG_REG13__gs_state14_r0_q__SHIFT
 
- VGT_DEBUG_REG13__gs_state15_r0_q_MASK
 
- VGT_DEBUG_REG13__gs_state15_r0_q__SHIFT
 
- VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0_MASK
 
- VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0__SHIFT
 
- VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0_MASK
 
- VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0__SHIFT
 
- VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0_MASK
 
- VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0__SHIFT
 
- VGT_DEBUG_REG14__SPARE0_MASK
 
- VGT_DEBUG_REG14__SPARE0__SHIFT
 
- VGT_DEBUG_REG14__SPARE1_MASK
 
- VGT_DEBUG_REG14__SPARE1__SHIFT
 
- VGT_DEBUG_REG14__SPARE2_MASK
 
- VGT_DEBUG_REG14__SPARE2__SHIFT
 
- VGT_DEBUG_REG14__SPARE3_MASK
 
- VGT_DEBUG_REG14__SPARE3__SHIFT
 
- VGT_DEBUG_REG14__SPARE8_MASK
 
- VGT_DEBUG_REG14__SPARE8__SHIFT
 
- VGT_DEBUG_REG14__SPARE_MASK
 
- VGT_DEBUG_REG14__SPARE__SHIFT
 
- VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q_MASK
 
- VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT
 
- VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q_MASK
 
- VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q__SHIFT
 
- VGT_DEBUG_REG14__es_flush_cnt_busy_q_MASK
 
- VGT_DEBUG_REG14__es_flush_cnt_busy_q__SHIFT
 
- VGT_DEBUG_REG14__gs_rb_space_avail_r0_MASK
 
- VGT_DEBUG_REG14__gs_rb_space_avail_r0__SHIFT
 
- VGT_DEBUG_REG14__gs_tbl_full_r0_MASK
 
- VGT_DEBUG_REG14__gs_tbl_full_r0__SHIFT
 
- VGT_DEBUG_REG14__gsfetch_done_fifo_full_MASK
 
- VGT_DEBUG_REG14__gsfetch_done_fifo_full__SHIFT
 
- VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0_MASK
 
- VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT
 
- VGT_DEBUG_REG14__se1spi_esthread_fifo_busy_MASK
 
- VGT_DEBUG_REG14__se1spi_esthread_fifo_busy__SHIFT
 
- VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy_MASK
 
- VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy__SHIFT
 
- VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0_MASK
 
- VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0__SHIFT
 
- VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0_MASK
 
- VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0__SHIFT
 
- VGT_DEBUG_REG14__vs_done_cnt_q_not_0_MASK
 
- VGT_DEBUG_REG14__vs_done_cnt_q_not_0__SHIFT
 
- VGT_DEBUG_REG15__SPARE25_MASK
 
- VGT_DEBUG_REG15__SPARE25__SHIFT
 
- VGT_DEBUG_REG15__SPARE31_MASK
 
- VGT_DEBUG_REG15__SPARE31__SHIFT
 
- VGT_DEBUG_REG15__active_sm_q_MASK
 
- VGT_DEBUG_REG15__active_sm_q__SHIFT
 
- VGT_DEBUG_REG15__cm_busy_q_MASK
 
- VGT_DEBUG_REG15__cm_busy_q__SHIFT
 
- VGT_DEBUG_REG15__cntr_tbl_wrptr_q_MASK
 
- VGT_DEBUG_REG15__cntr_tbl_wrptr_q__SHIFT
 
- VGT_DEBUG_REG15__counters_busy_q_MASK
 
- VGT_DEBUG_REG15__counters_busy_q__SHIFT
 
- VGT_DEBUG_REG15__counters_full_MASK
 
- VGT_DEBUG_REG15__counters_full__SHIFT
 
- VGT_DEBUG_REG15__entry_rdptr_q_MASK
 
- VGT_DEBUG_REG15__entry_rdptr_q__SHIFT
 
- VGT_DEBUG_REG15__gs_done_array_q_not_0_MASK
 
- VGT_DEBUG_REG15__gs_done_array_q_not_0__SHIFT
 
- VGT_DEBUG_REG15__output_fifo_empty_MASK
 
- VGT_DEBUG_REG15__output_fifo_empty__SHIFT
 
- VGT_DEBUG_REG15__output_fifo_full_MASK
 
- VGT_DEBUG_REG15__output_fifo_full__SHIFT
 
- VGT_DEBUG_REG15__st_cut_mode_q_MASK
 
- VGT_DEBUG_REG15__st_cut_mode_q__SHIFT
 
- VGT_DEBUG_REG16__SPARE24_MASK
 
- VGT_DEBUG_REG16__SPARE24__SHIFT
 
- VGT_DEBUG_REG16__gog_busy_MASK
 
- VGT_DEBUG_REG16__gog_busy__SHIFT
 
- VGT_DEBUG_REG16__gog_out_prim_state_sel_MASK
 
- VGT_DEBUG_REG16__gog_out_prim_state_sel__SHIFT
 
- VGT_DEBUG_REG16__gog_state_q_MASK
 
- VGT_DEBUG_REG16__gog_state_q__SHIFT
 
- VGT_DEBUG_REG16__gog_tm_vs_event_rtr_MASK
 
- VGT_DEBUG_REG16__gog_tm_vs_event_rtr__SHIFT
 
- VGT_DEBUG_REG16__indx_valid_r0_q_MASK
 
- VGT_DEBUG_REG16__indx_valid_r0_q__SHIFT
 
- VGT_DEBUG_REG16__indx_valid_r1_q_MASK
 
- VGT_DEBUG_REG16__indx_valid_r1_q__SHIFT
 
- VGT_DEBUG_REG16__indx_valid_r2_q_MASK
 
- VGT_DEBUG_REG16__indx_valid_r2_q__SHIFT
 
- VGT_DEBUG_REG16__multiple_streams_en_r1_q_MASK
 
- VGT_DEBUG_REG16__multiple_streams_en_r1_q__SHIFT
 
- VGT_DEBUG_REG16__new_vs_thread_r2_MASK
 
- VGT_DEBUG_REG16__new_vs_thread_r2__SHIFT
 
- VGT_DEBUG_REG16__num_gs_r2_q_not_0_MASK
 
- VGT_DEBUG_REG16__num_gs_r2_q_not_0__SHIFT
 
- VGT_DEBUG_REG16__prim_valid_r0_q_MASK
 
- VGT_DEBUG_REG16__prim_valid_r0_q__SHIFT
 
- VGT_DEBUG_REG16__prim_valid_r1_q_MASK
 
- VGT_DEBUG_REG16__prim_valid_r1_q__SHIFT
 
- VGT_DEBUG_REG16__prim_valid_r2_q_MASK
 
- VGT_DEBUG_REG16__prim_valid_r2_q__SHIFT
 
- VGT_DEBUG_REG16__r0_rtr_MASK
 
- VGT_DEBUG_REG16__r0_rtr__SHIFT
 
- VGT_DEBUG_REG16__r1_rtr_MASK
 
- VGT_DEBUG_REG16__r1_rtr__SHIFT
 
- VGT_DEBUG_REG16__r1_upstream_rtr_MASK
 
- VGT_DEBUG_REG16__r1_upstream_rtr__SHIFT
 
- VGT_DEBUG_REG16__r2_indx_rtr_MASK
 
- VGT_DEBUG_REG16__r2_indx_rtr__SHIFT
 
- VGT_DEBUG_REG16__r2_prim_rtr_MASK
 
- VGT_DEBUG_REG16__r2_prim_rtr__SHIFT
 
- VGT_DEBUG_REG16__r2_rtr_MASK
 
- VGT_DEBUG_REG16__r2_rtr__SHIFT
 
- VGT_DEBUG_REG16__r2_vs_tbl_rtr_MASK
 
- VGT_DEBUG_REG16__r2_vs_tbl_rtr__SHIFT
 
- VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr_MASK
 
- VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr__SHIFT
 
- VGT_DEBUG_REG16__send_event_q_MASK
 
- VGT_DEBUG_REG16__send_event_q__SHIFT
 
- VGT_DEBUG_REG16__valid_r0_q_MASK
 
- VGT_DEBUG_REG16__valid_r0_q__SHIFT
 
- VGT_DEBUG_REG16__valid_r1_q_MASK
 
- VGT_DEBUG_REG16__valid_r1_q__SHIFT
 
- VGT_DEBUG_REG16__valid_r2_q_MASK
 
- VGT_DEBUG_REG16__valid_r2_q__SHIFT
 
- VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q_MASK
 
- VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q__SHIFT
 
- VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0_MASK
 
- VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT
 
- VGT_DEBUG_REG17__gog_out_indx_13_0_MASK
 
- VGT_DEBUG_REG17__gog_out_indx_13_0__SHIFT
 
- VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0_MASK
 
- VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0__SHIFT
 
- VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0_MASK
 
- VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0__SHIFT
 
- VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0_MASK
 
- VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0__SHIFT
 
- VGT_DEBUG_REG18__components_valid_r0_q_MASK
 
- VGT_DEBUG_REG18__components_valid_r0_q__SHIFT
 
- VGT_DEBUG_REG18__eject_vtx_vect_r1_d_MASK
 
- VGT_DEBUG_REG18__eject_vtx_vect_r1_d__SHIFT
 
- VGT_DEBUG_REG18__eop_r0_q_MASK
 
- VGT_DEBUG_REG18__eop_r0_q__SHIFT
 
- VGT_DEBUG_REG18__grp_vr_valid_MASK
 
- VGT_DEBUG_REG18__grp_vr_valid__SHIFT
 
- VGT_DEBUG_REG18__gs_scenario_a_r0_q_MASK
 
- VGT_DEBUG_REG18__gs_scenario_a_r0_q__SHIFT
 
- VGT_DEBUG_REG18__gs_scenario_b_r0_q_MASK
 
- VGT_DEBUG_REG18__gs_scenario_b_r0_q__SHIFT
 
- VGT_DEBUG_REG18__indices_to_send_q_MASK
 
- VGT_DEBUG_REG18__indices_to_send_q__SHIFT
 
- VGT_DEBUG_REG18__indx0_hit_d_MASK
 
- VGT_DEBUG_REG18__indx0_hit_d__SHIFT
 
- VGT_DEBUG_REG18__indx0_new_d_MASK
 
- VGT_DEBUG_REG18__indx0_new_d__SHIFT
 
- VGT_DEBUG_REG18__indx1_hit_d_MASK
 
- VGT_DEBUG_REG18__indx1_hit_d__SHIFT
 
- VGT_DEBUG_REG18__indx1_new_d_MASK
 
- VGT_DEBUG_REG18__indx1_new_d__SHIFT
 
- VGT_DEBUG_REG18__indx2_hit_d_MASK
 
- VGT_DEBUG_REG18__indx2_hit_d__SHIFT
 
- VGT_DEBUG_REG18__indx2_new_d_MASK
 
- VGT_DEBUG_REG18__indx2_new_d__SHIFT
 
- VGT_DEBUG_REG18__last_group_of_instance_r0_q_MASK
 
- VGT_DEBUG_REG18__last_group_of_instance_r0_q__SHIFT
 
- VGT_DEBUG_REG18__last_indx_of_prim_MASK
 
- VGT_DEBUG_REG18__last_indx_of_prim__SHIFT
 
- VGT_DEBUG_REG18__null_primitive_r0_q_MASK
 
- VGT_DEBUG_REG18__null_primitive_r0_q__SHIFT
 
- VGT_DEBUG_REG18__out_vr_indx_read_MASK
 
- VGT_DEBUG_REG18__out_vr_indx_read__SHIFT
 
- VGT_DEBUG_REG18__out_vr_prim_read_MASK
 
- VGT_DEBUG_REG18__out_vr_prim_read__SHIFT
 
- VGT_DEBUG_REG18__pipe0_dr_MASK
 
- VGT_DEBUG_REG18__pipe0_dr__SHIFT
 
- VGT_DEBUG_REG18__pipe0_rtr_MASK
 
- VGT_DEBUG_REG18__pipe0_rtr__SHIFT
 
- VGT_DEBUG_REG18__pipe1_dr_MASK
 
- VGT_DEBUG_REG18__pipe1_dr__SHIFT
 
- VGT_DEBUG_REG18__pipe1_rtr_MASK
 
- VGT_DEBUG_REG18__pipe1_rtr__SHIFT
 
- VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q_MASK
 
- VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q__SHIFT
 
- VGT_DEBUG_REG18__sub_prim_type_r0_q_MASK
 
- VGT_DEBUG_REG18__sub_prim_type_r0_q__SHIFT
 
- VGT_DEBUG_REG18__valid_indices_MASK
 
- VGT_DEBUG_REG18__valid_indices__SHIFT
 
- VGT_DEBUG_REG18__vr_grp_read_MASK
 
- VGT_DEBUG_REG18__vr_grp_read__SHIFT
 
- VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q_MASK
 
- VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q__SHIFT
 
- VGT_DEBUG_REG19__VGT_PA_clips_rtr_q_MASK
 
- VGT_DEBUG_REG19__VGT_PA_clips_rtr_q__SHIFT
 
- VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q_MASK
 
- VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q__SHIFT
 
- VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q_MASK
 
- VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q__SHIFT
 
- VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q_MASK
 
- VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q__SHIFT
 
- VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q_MASK
 
- VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q__SHIFT
 
- VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q_MASK
 
- VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q__SHIFT
 
- VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect_MASK
 
- VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect__SHIFT
 
- VGT_DEBUG_REG19__buffered_prim_eop_MASK
 
- VGT_DEBUG_REG19__buffered_prim_eop__SHIFT
 
- VGT_DEBUG_REG19__buffered_prim_event_MASK
 
- VGT_DEBUG_REG19__buffered_prim_event__SHIFT
 
- VGT_DEBUG_REG19__buffered_prim_null_primitive_MASK
 
- VGT_DEBUG_REG19__buffered_prim_null_primitive__SHIFT
 
- VGT_DEBUG_REG19__buffered_prim_type_event_MASK
 
- VGT_DEBUG_REG19__buffered_prim_type_event__SHIFT
 
- VGT_DEBUG_REG19__filter_event_MASK
 
- VGT_DEBUG_REG19__filter_event__SHIFT
 
- VGT_DEBUG_REG19__hold_prim_MASK
 
- VGT_DEBUG_REG19__hold_prim__SHIFT
 
- VGT_DEBUG_REG19__new_packet_q_MASK
 
- VGT_DEBUG_REG19__new_packet_q__SHIFT
 
- VGT_DEBUG_REG19__null_terminate_vtx_vector_MASK
 
- VGT_DEBUG_REG19__null_terminate_vtx_vector__SHIFT
 
- VGT_DEBUG_REG19__num_new_unique_rel_indx_MASK
 
- VGT_DEBUG_REG19__num_new_unique_rel_indx__SHIFT
 
- VGT_DEBUG_REG19__pa_clipp_fifo_busy_q_MASK
 
- VGT_DEBUG_REG19__pa_clipp_fifo_busy_q__SHIFT
 
- VGT_DEBUG_REG19__pa_clips_fifo_busy_q_MASK
 
- VGT_DEBUG_REG19__pa_clips_fifo_busy_q__SHIFT
 
- VGT_DEBUG_REG19__pa_clipv_fifo_busy_q_MASK
 
- VGT_DEBUG_REG19__pa_clipv_fifo_busy_q__SHIFT
 
- VGT_DEBUG_REG19__prim_buffer_empty_MASK
 
- VGT_DEBUG_REG19__prim_buffer_empty__SHIFT
 
- VGT_DEBUG_REG19__prim_buffer_full_MASK
 
- VGT_DEBUG_REG19__prim_buffer_full__SHIFT
 
- VGT_DEBUG_REG19__separate_out_busy_q_MASK
 
- VGT_DEBUG_REG19__separate_out_busy_q__SHIFT
 
- VGT_DEBUG_REG19__separate_out_indx_busy_q_MASK
 
- VGT_DEBUG_REG19__separate_out_indx_busy_q__SHIFT
 
- VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q_MASK
 
- VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q__SHIFT
 
- VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q_MASK
 
- VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q__SHIFT
 
- VGT_DEBUG_REG1__SPARE0_MASK
 
- VGT_DEBUG_REG1__SPARE0__SHIFT
 
- VGT_DEBUG_REG1__SPARE10_MASK
 
- VGT_DEBUG_REG1__SPARE10__SHIFT
 
- VGT_DEBUG_REG1__SPARE11_MASK
 
- VGT_DEBUG_REG1__SPARE11__SHIFT
 
- VGT_DEBUG_REG1__SPARE12_MASK
 
- VGT_DEBUG_REG1__SPARE12__SHIFT
 
- VGT_DEBUG_REG1__SPARE1_MASK
 
- VGT_DEBUG_REG1__SPARE1__SHIFT
 
- VGT_DEBUG_REG1__SPARE23_MASK
 
- VGT_DEBUG_REG1__SPARE23__SHIFT
 
- VGT_DEBUG_REG1__SPARE25_MASK
 
- VGT_DEBUG_REG1__SPARE25__SHIFT
 
- VGT_DEBUG_REG1__SPARE2_MASK
 
- VGT_DEBUG_REG1__SPARE2__SHIFT
 
- VGT_DEBUG_REG1__SPARE3_MASK
 
- VGT_DEBUG_REG1__SPARE3__SHIFT
 
- VGT_DEBUG_REG1__SPARE4_MASK
 
- VGT_DEBUG_REG1__SPARE4__SHIFT
 
- VGT_DEBUG_REG1__SPARE5_MASK
 
- VGT_DEBUG_REG1__SPARE5__SHIFT
 
- VGT_DEBUG_REG1__SPARE6_MASK
 
- VGT_DEBUG_REG1__SPARE6__SHIFT
 
- VGT_DEBUG_REG1__SPARE7_MASK
 
- VGT_DEBUG_REG1__SPARE7__SHIFT
 
- VGT_DEBUG_REG1__SPARE8_MASK
 
- VGT_DEBUG_REG1__SPARE8__SHIFT
 
- VGT_DEBUG_REG1__SPARE9_MASK
 
- VGT_DEBUG_REG1__SPARE9__SHIFT
 
- VGT_DEBUG_REG1__gog_out_indx_valid_MASK
 
- VGT_DEBUG_REG1__gog_out_indx_valid__SHIFT
 
- VGT_DEBUG_REG1__gog_out_prim_valid_MASK
 
- VGT_DEBUG_REG1__gog_out_prim_valid__SHIFT
 
- VGT_DEBUG_REG1__gs_pi_read_MASK
 
- VGT_DEBUG_REG1__gs_pi_read__SHIFT
 
- VGT_DEBUG_REG1__out_indx_read_MASK
 
- VGT_DEBUG_REG1__out_indx_read__SHIFT
 
- VGT_DEBUG_REG1__out_prim_read_MASK
 
- VGT_DEBUG_REG1__out_prim_read__SHIFT
 
- VGT_DEBUG_REG1__pi_gs_valid_MASK
 
- VGT_DEBUG_REG1__pi_gs_valid__SHIFT
 
- VGT_DEBUG_REG1__pi_pt_valid_MASK
 
- VGT_DEBUG_REG1__pi_pt_valid__SHIFT
 
- VGT_DEBUG_REG1__pi_te_valid_MASK
 
- VGT_DEBUG_REG1__pi_te_valid__SHIFT
 
- VGT_DEBUG_REG1__pi_vr_valid_MASK
 
- VGT_DEBUG_REG1__pi_vr_valid__SHIFT
 
- VGT_DEBUG_REG1__pt_out_indx_valid_MASK
 
- VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT
 
- VGT_DEBUG_REG1__pt_out_prim_valid_MASK
 
- VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT
 
- VGT_DEBUG_REG1__pt_pi_read_MASK
 
- VGT_DEBUG_REG1__pt_pi_read__SHIFT
 
- VGT_DEBUG_REG1__te_grp_read_MASK
 
- VGT_DEBUG_REG1__te_grp_read__SHIFT
 
- VGT_DEBUG_REG1__te_out_data_valid_MASK
 
- VGT_DEBUG_REG1__te_out_data_valid__SHIFT
 
- VGT_DEBUG_REG1__vr_out_indx_valid_MASK
 
- VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT
 
- VGT_DEBUG_REG1__vr_out_prim_valid_MASK
 
- VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT
 
- VGT_DEBUG_REG1__vr_pi_read_MASK
 
- VGT_DEBUG_REG1__vr_pi_read__SHIFT
 
- VGT_DEBUG_REG20__SPARE17_MASK
 
- VGT_DEBUG_REG20__SPARE17__SHIFT
 
- VGT_DEBUG_REG20__alloc_counter_q_MASK
 
- VGT_DEBUG_REG20__alloc_counter_q__SHIFT
 
- VGT_DEBUG_REG20__curr_dealloc_distance_q_MASK
 
- VGT_DEBUG_REG20__curr_dealloc_distance_q__SHIFT
 
- VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0_MASK
 
- VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0__SHIFT
 
- VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0_MASK
 
- VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0__SHIFT
 
- VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex_MASK
 
- VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex__SHIFT
 
- VGT_DEBUG_REG20__int_vtx_counter_q_not_0_MASK
 
- VGT_DEBUG_REG20__int_vtx_counter_q_not_0__SHIFT
 
- VGT_DEBUG_REG20__new_allocate_q_MASK
 
- VGT_DEBUG_REG20__new_allocate_q__SHIFT
 
- VGT_DEBUG_REG21__buff_full_p1_MASK
 
- VGT_DEBUG_REG21__buff_full_p1__SHIFT
 
- VGT_DEBUG_REG21__eopg_p0_q_MASK
 
- VGT_DEBUG_REG21__eopg_p0_q__SHIFT
 
- VGT_DEBUG_REG21__eotg_r2_q_MASK
 
- VGT_DEBUG_REG21__eotg_r2_q__SHIFT
 
- VGT_DEBUG_REG21__full_state_p1_q_MASK
 
- VGT_DEBUG_REG21__full_state_p1_q__SHIFT
 
- VGT_DEBUG_REG21__indx_count_q_not_0_MASK
 
- VGT_DEBUG_REG21__indx_count_q_not_0__SHIFT
 
- VGT_DEBUG_REG21__indx_side_fifo_empty_MASK
 
- VGT_DEBUG_REG21__indx_side_fifo_empty__SHIFT
 
- VGT_DEBUG_REG21__indx_side_fifo_full_MASK
 
- VGT_DEBUG_REG21__indx_side_fifo_full__SHIFT
 
- VGT_DEBUG_REG21__indx_side_indx_valid_MASK
 
- VGT_DEBUG_REG21__indx_side_indx_valid__SHIFT
 
- VGT_DEBUG_REG21__interfaces_rtr_MASK
 
- VGT_DEBUG_REG21__interfaces_rtr__SHIFT
 
- VGT_DEBUG_REG21__is_event_p0_q_MASK
 
- VGT_DEBUG_REG21__is_event_p0_q__SHIFT
 
- VGT_DEBUG_REG21__lshs_dealloc_p1_MASK
 
- VGT_DEBUG_REG21__lshs_dealloc_p1__SHIFT
 
- VGT_DEBUG_REG21__null_r2_q_MASK
 
- VGT_DEBUG_REG21__null_r2_q__SHIFT
 
- VGT_DEBUG_REG21__out_indx_fifo_empty_MASK
 
- VGT_DEBUG_REG21__out_indx_fifo_empty__SHIFT
 
- VGT_DEBUG_REG21__out_indx_fifo_full_MASK
 
- VGT_DEBUG_REG21__out_indx_fifo_full__SHIFT
 
- VGT_DEBUG_REG21__p0_dr_MASK
 
- VGT_DEBUG_REG21__p0_dr__SHIFT
 
- VGT_DEBUG_REG21__p0_nobp_MASK
 
- VGT_DEBUG_REG21__p0_nobp__SHIFT
 
- VGT_DEBUG_REG21__p0_rtr_MASK
 
- VGT_DEBUG_REG21__p0_rtr__SHIFT
 
- VGT_DEBUG_REG21__pipe0_dr_MASK
 
- VGT_DEBUG_REG21__pipe0_dr__SHIFT
 
- VGT_DEBUG_REG21__pipe0_rtr_MASK
 
- VGT_DEBUG_REG21__pipe0_rtr__SHIFT
 
- VGT_DEBUG_REG21__pipe1_dr_MASK
 
- VGT_DEBUG_REG21__pipe1_dr__SHIFT
 
- VGT_DEBUG_REG21__pipe1_rtr_MASK
 
- VGT_DEBUG_REG21__pipe1_rtr__SHIFT
 
- VGT_DEBUG_REG21__pipe2_dr_MASK
 
- VGT_DEBUG_REG21__pipe2_dr__SHIFT
 
- VGT_DEBUG_REG21__pipe2_rtr_MASK
 
- VGT_DEBUG_REG21__pipe2_rtr__SHIFT
 
- VGT_DEBUG_REG21__stateid_p0_q_MASK
 
- VGT_DEBUG_REG21__stateid_p0_q__SHIFT
 
- VGT_DEBUG_REG21__stream_id_r2_q_MASK
 
- VGT_DEBUG_REG21__stream_id_r2_q__SHIFT
 
- VGT_DEBUG_REG21__strmout_valid_p1_MASK
 
- VGT_DEBUG_REG21__strmout_valid_p1__SHIFT
 
- VGT_DEBUG_REG21__vsthread_buff_empty_MASK
 
- VGT_DEBUG_REG21__vsthread_buff_empty__SHIFT
 
- VGT_DEBUG_REG21__vsthread_buff_full_MASK
 
- VGT_DEBUG_REG21__vsthread_buff_full__SHIFT
 
- VGT_DEBUG_REG21__vtx_vect_counter_q_not_0_MASK
 
- VGT_DEBUG_REG21__vtx_vect_counter_q_not_0__SHIFT
 
- VGT_DEBUG_REG21__wait_for_external_eopg_q_MASK
 
- VGT_DEBUG_REG21__wait_for_external_eopg_q__SHIFT
 
- VGT_DEBUG_REG22__cm_state16_MASK
 
- VGT_DEBUG_REG22__cm_state16__SHIFT
 
- VGT_DEBUG_REG22__cm_state17_MASK
 
- VGT_DEBUG_REG22__cm_state17__SHIFT
 
- VGT_DEBUG_REG22__cm_state18_MASK
 
- VGT_DEBUG_REG22__cm_state18__SHIFT
 
- VGT_DEBUG_REG22__cm_state19_MASK
 
- VGT_DEBUG_REG22__cm_state19__SHIFT
 
- VGT_DEBUG_REG22__cm_state20_MASK
 
- VGT_DEBUG_REG22__cm_state20__SHIFT
 
- VGT_DEBUG_REG22__cm_state21_MASK
 
- VGT_DEBUG_REG22__cm_state21__SHIFT
 
- VGT_DEBUG_REG22__cm_state22_MASK
 
- VGT_DEBUG_REG22__cm_state22__SHIFT
 
- VGT_DEBUG_REG22__cm_state23_MASK
 
- VGT_DEBUG_REG22__cm_state23__SHIFT
 
- VGT_DEBUG_REG22__cm_state24_MASK
 
- VGT_DEBUG_REG22__cm_state24__SHIFT
 
- VGT_DEBUG_REG22__cm_state25_MASK
 
- VGT_DEBUG_REG22__cm_state25__SHIFT
 
- VGT_DEBUG_REG22__cm_state26_MASK
 
- VGT_DEBUG_REG22__cm_state26__SHIFT
 
- VGT_DEBUG_REG22__cm_state27_MASK
 
- VGT_DEBUG_REG22__cm_state27__SHIFT
 
- VGT_DEBUG_REG22__cm_state28_MASK
 
- VGT_DEBUG_REG22__cm_state28__SHIFT
 
- VGT_DEBUG_REG22__cm_state29_MASK
 
- VGT_DEBUG_REG22__cm_state29__SHIFT
 
- VGT_DEBUG_REG22__cm_state30_MASK
 
- VGT_DEBUG_REG22__cm_state30__SHIFT
 
- VGT_DEBUG_REG22__cm_state31_MASK
 
- VGT_DEBUG_REG22__cm_state31__SHIFT
 
- VGT_DEBUG_REG23__SPARE_MASK
 
- VGT_DEBUG_REG23__SPARE__SHIFT
 
- VGT_DEBUG_REG23__frmt_busy_MASK
 
- VGT_DEBUG_REG23__frmt_busy__SHIFT
 
- VGT_DEBUG_REG23__new_verts_r2_q_MASK
 
- VGT_DEBUG_REG23__new_verts_r2_q__SHIFT
 
- VGT_DEBUG_REG23__prim_dr_r2_q_MASK
 
- VGT_DEBUG_REG23__prim_dr_r2_q__SHIFT
 
- VGT_DEBUG_REG23__prim_fifo_empty_MASK
 
- VGT_DEBUG_REG23__prim_fifo_empty__SHIFT
 
- VGT_DEBUG_REG23__prim_fifo_full_MASK
 
- VGT_DEBUG_REG23__prim_fifo_full__SHIFT
 
- VGT_DEBUG_REG23__prim_r2_rtr_MASK
 
- VGT_DEBUG_REG23__prim_r2_rtr__SHIFT
 
- VGT_DEBUG_REG23__prim_r3_rtr_MASK
 
- VGT_DEBUG_REG23__prim_r3_rtr__SHIFT
 
- VGT_DEBUG_REG23__prim_state_sel_r2_q_MASK
 
- VGT_DEBUG_REG23__prim_state_sel_r2_q__SHIFT
 
- VGT_DEBUG_REG23__rcm_frmt_prim_rtr_MASK
 
- VGT_DEBUG_REG23__rcm_frmt_prim_rtr__SHIFT
 
- VGT_DEBUG_REG23__rcm_frmt_vert_rtr_MASK
 
- VGT_DEBUG_REG23__rcm_frmt_vert_rtr__SHIFT
 
- VGT_DEBUG_REG23__vert_dr_r0_q_MASK
 
- VGT_DEBUG_REG23__vert_dr_r0_q__SHIFT
 
- VGT_DEBUG_REG23__vert_dr_r1_q_MASK
 
- VGT_DEBUG_REG23__vert_dr_r1_q__SHIFT
 
- VGT_DEBUG_REG23__vert_dr_r2_q_MASK
 
- VGT_DEBUG_REG23__vert_dr_r2_q__SHIFT
 
- VGT_DEBUG_REG23__vert_r0_rtr_MASK
 
- VGT_DEBUG_REG23__vert_r0_rtr__SHIFT
 
- VGT_DEBUG_REG23__vert_r1_rtr_MASK
 
- VGT_DEBUG_REG23__vert_r1_rtr__SHIFT
 
- VGT_DEBUG_REG23__vert_r2_rtr_MASK
 
- VGT_DEBUG_REG23__vert_r2_rtr__SHIFT
 
- VGT_DEBUG_REG23__vert_r3_rtr_MASK
 
- VGT_DEBUG_REG23__vert_r3_rtr__SHIFT
 
- VGT_DEBUG_REG23__verts_sent_r2_q_MASK
 
- VGT_DEBUG_REG23__verts_sent_r2_q__SHIFT
 
- VGT_DEBUG_REG24__SPARE31_MASK
 
- VGT_DEBUG_REG24__SPARE31__SHIFT
 
- VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0_MASK
 
- VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0__SHIFT
 
- VGT_DEBUG_REG24__dependent_st_cut_mode_q_MASK
 
- VGT_DEBUG_REG24__dependent_st_cut_mode_q__SHIFT
 
- VGT_DEBUG_REG25__active_sm_r0_q_MASK
 
- VGT_DEBUG_REG25__active_sm_r0_q__SHIFT
 
- VGT_DEBUG_REG25__add_gs_rb_space_r0_q_MASK
 
- VGT_DEBUG_REG25__add_gs_rb_space_r0_q__SHIFT
 
- VGT_DEBUG_REG25__add_gs_rb_space_r1_q_MASK
 
- VGT_DEBUG_REG25__add_gs_rb_space_r1_q__SHIFT
 
- VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK
 
- VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0__SHIFT
 
- VGT_DEBUG_REG26__cm_state0_MASK
 
- VGT_DEBUG_REG26__cm_state0__SHIFT
 
- VGT_DEBUG_REG26__cm_state10_MASK
 
- VGT_DEBUG_REG26__cm_state10__SHIFT
 
- VGT_DEBUG_REG26__cm_state11_MASK
 
- VGT_DEBUG_REG26__cm_state11__SHIFT
 
- VGT_DEBUG_REG26__cm_state12_MASK
 
- VGT_DEBUG_REG26__cm_state12__SHIFT
 
- VGT_DEBUG_REG26__cm_state13_MASK
 
- VGT_DEBUG_REG26__cm_state13__SHIFT
 
- VGT_DEBUG_REG26__cm_state14_MASK
 
- VGT_DEBUG_REG26__cm_state14__SHIFT
 
- VGT_DEBUG_REG26__cm_state15_MASK
 
- VGT_DEBUG_REG26__cm_state15__SHIFT
 
- VGT_DEBUG_REG26__cm_state1_MASK
 
- VGT_DEBUG_REG26__cm_state1__SHIFT
 
- VGT_DEBUG_REG26__cm_state2_MASK
 
- VGT_DEBUG_REG26__cm_state2__SHIFT
 
- VGT_DEBUG_REG26__cm_state3_MASK
 
- VGT_DEBUG_REG26__cm_state3__SHIFT
 
- VGT_DEBUG_REG26__cm_state4_MASK
 
- VGT_DEBUG_REG26__cm_state4__SHIFT
 
- VGT_DEBUG_REG26__cm_state5_MASK
 
- VGT_DEBUG_REG26__cm_state5__SHIFT
 
- VGT_DEBUG_REG26__cm_state6_MASK
 
- VGT_DEBUG_REG26__cm_state6__SHIFT
 
- VGT_DEBUG_REG26__cm_state7_MASK
 
- VGT_DEBUG_REG26__cm_state7__SHIFT
 
- VGT_DEBUG_REG26__cm_state8_MASK
 
- VGT_DEBUG_REG26__cm_state8__SHIFT
 
- VGT_DEBUG_REG26__cm_state9_MASK
 
- VGT_DEBUG_REG26__cm_state9__SHIFT
 
- VGT_DEBUG_REG27__eop_p1_q_MASK
 
- VGT_DEBUG_REG27__eop_p1_q__SHIFT
 
- VGT_DEBUG_REG27__event_flag_p1_q_MASK
 
- VGT_DEBUG_REG27__event_flag_p1_q__SHIFT
 
- VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q_MASK
 
- VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q__SHIFT
 
- VGT_DEBUG_REG27__gs_out_prim_type_p0_q_MASK
 
- VGT_DEBUG_REG27__gs_out_prim_type_p0_q__SHIFT
 
- VGT_DEBUG_REG27__gsc0_dr_MASK
 
- VGT_DEBUG_REG27__gsc0_dr__SHIFT
 
- VGT_DEBUG_REG27__gsc0_rtr_MASK
 
- VGT_DEBUG_REG27__gsc0_rtr__SHIFT
 
- VGT_DEBUG_REG27__gsc_2cycle_output_MASK
 
- VGT_DEBUG_REG27__gsc_2cycle_output__SHIFT
 
- VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q_MASK
 
- VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q__SHIFT
 
- VGT_DEBUG_REG27__gsc_eop_p0_q_MASK
 
- VGT_DEBUG_REG27__gsc_eop_p0_q__SHIFT
 
- VGT_DEBUG_REG27__gsc_indx_count_p0_q_MASK
 
- VGT_DEBUG_REG27__gsc_indx_count_p0_q__SHIFT
 
- VGT_DEBUG_REG27__gsc_null_primitive_p0_q_MASK
 
- VGT_DEBUG_REG27__gsc_null_primitive_p0_q__SHIFT
 
- VGT_DEBUG_REG27__indices_to_send_p0_q_MASK
 
- VGT_DEBUG_REG27__indices_to_send_p0_q__SHIFT
 
- VGT_DEBUG_REG27__last_indx_of_prim_p1_q_MASK
 
- VGT_DEBUG_REG27__last_indx_of_prim_p1_q__SHIFT
 
- VGT_DEBUG_REG27__last_indx_of_vsprim_MASK
 
- VGT_DEBUG_REG27__last_indx_of_vsprim__SHIFT
 
- VGT_DEBUG_REG27__last_vsprim_of_gsprim_MASK
 
- VGT_DEBUG_REG27__last_vsprim_of_gsprim__SHIFT
 
- VGT_DEBUG_REG27__pipe0_dr_MASK
 
- VGT_DEBUG_REG27__pipe0_dr__SHIFT
 
- VGT_DEBUG_REG27__pipe0_rtr_MASK
 
- VGT_DEBUG_REG27__pipe0_rtr__SHIFT
 
- VGT_DEBUG_REG27__pipe1_dr_MASK
 
- VGT_DEBUG_REG27__pipe1_dr__SHIFT
 
- VGT_DEBUG_REG27__pipe1_rtr_MASK
 
- VGT_DEBUG_REG27__pipe1_rtr__SHIFT
 
- VGT_DEBUG_REG27__tm_pt_event_rtr_MASK
 
- VGT_DEBUG_REG27__tm_pt_event_rtr__SHIFT
 
- VGT_DEBUG_REG28__advance_inner_point_p1_MASK
 
- VGT_DEBUG_REG28__advance_inner_point_p1__SHIFT
 
- VGT_DEBUG_REG28__advance_outer_point_p1_MASK
 
- VGT_DEBUG_REG28__advance_outer_point_p1__SHIFT
 
- VGT_DEBUG_REG28__con_state_q_MASK
 
- VGT_DEBUG_REG28__con_state_q__SHIFT
 
- VGT_DEBUG_REG28__first_ring_of_patch_p0_q_MASK
 
- VGT_DEBUG_REG28__first_ring_of_patch_p0_q__SHIFT
 
- VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q_MASK
 
- VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q__SHIFT
 
- VGT_DEBUG_REG28__last_point_of_inner_ring_p1_MASK
 
- VGT_DEBUG_REG28__last_point_of_inner_ring_p1__SHIFT
 
- VGT_DEBUG_REG28__last_point_of_outer_ring_p1_MASK
 
- VGT_DEBUG_REG28__last_point_of_outer_ring_p1__SHIFT
 
- VGT_DEBUG_REG28__last_ring_of_patch_p0_q_MASK
 
- VGT_DEBUG_REG28__last_ring_of_patch_p0_q__SHIFT
 
- VGT_DEBUG_REG28__next_ring_is_rect_p0_q_MASK
 
- VGT_DEBUG_REG28__next_ring_is_rect_p0_q__SHIFT
 
- VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q_MASK
 
- VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q__SHIFT
 
- VGT_DEBUG_REG28__outer_parity_p0_q_MASK
 
- VGT_DEBUG_REG28__outer_parity_p0_q__SHIFT
 
- VGT_DEBUG_REG28__parallel_parity_p0_q_MASK
 
- VGT_DEBUG_REG28__parallel_parity_p0_q__SHIFT
 
- VGT_DEBUG_REG28__pipe0_edge_dr_MASK
 
- VGT_DEBUG_REG28__pipe0_edge_dr__SHIFT
 
- VGT_DEBUG_REG28__pipe0_edge_rtr_MASK
 
- VGT_DEBUG_REG28__pipe0_edge_rtr__SHIFT
 
- VGT_DEBUG_REG28__pipe0_patch_dr_MASK
 
- VGT_DEBUG_REG28__pipe0_patch_dr__SHIFT
 
- VGT_DEBUG_REG28__pipe0_patch_rtr_MASK
 
- VGT_DEBUG_REG28__pipe0_patch_rtr__SHIFT
 
- VGT_DEBUG_REG28__pipe1_dr_MASK
 
- VGT_DEBUG_REG28__pipe1_dr__SHIFT
 
- VGT_DEBUG_REG28__pipe1_edge_rtr_MASK
 
- VGT_DEBUG_REG28__pipe1_edge_rtr__SHIFT
 
- VGT_DEBUG_REG28__pipe1_inner1_rtr_MASK
 
- VGT_DEBUG_REG28__pipe1_inner1_rtr__SHIFT
 
- VGT_DEBUG_REG28__pipe1_inner2_rtr_MASK
 
- VGT_DEBUG_REG28__pipe1_inner2_rtr__SHIFT
 
- VGT_DEBUG_REG28__pipe1_outer1_rtr_MASK
 
- VGT_DEBUG_REG28__pipe1_outer1_rtr__SHIFT
 
- VGT_DEBUG_REG28__pipe1_outer2_rtr_MASK
 
- VGT_DEBUG_REG28__pipe1_outer2_rtr__SHIFT
 
- VGT_DEBUG_REG28__pipe1_patch_rtr_MASK
 
- VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT
 
- VGT_DEBUG_REG28__pipe1_rtr_MASK
 
- VGT_DEBUG_REG28__pipe1_rtr__SHIFT
 
- VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q_MASK
 
- VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q__SHIFT
 
- VGT_DEBUG_REG28__process_tri_center_poly_p0_q_MASK
 
- VGT_DEBUG_REG28__process_tri_center_poly_p0_q__SHIFT
 
- VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK
 
- VGT_DEBUG_REG28__process_tri_middle_p0_q__SHIFT
 
- VGT_DEBUG_REG28__second_cycle_q_MASK
 
- VGT_DEBUG_REG28__second_cycle_q__SHIFT
 
- VGT_DEBUG_REG28__use_stored_inner_q_ring2_MASK
 
- VGT_DEBUG_REG28__use_stored_inner_q_ring2__SHIFT
 
- VGT_DEBUG_REG29__advance_inner_point_p1_MASK
 
- VGT_DEBUG_REG29__advance_inner_point_p1__SHIFT
 
- VGT_DEBUG_REG29__advance_outer_point_p1_MASK
 
- VGT_DEBUG_REG29__advance_outer_point_p1__SHIFT
 
- VGT_DEBUG_REG29__con_state_q_MASK
 
- VGT_DEBUG_REG29__con_state_q__SHIFT
 
- VGT_DEBUG_REG29__first_ring_of_patch_p0_q_MASK
 
- VGT_DEBUG_REG29__first_ring_of_patch_p0_q__SHIFT
 
- VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q_MASK
 
- VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q__SHIFT
 
- VGT_DEBUG_REG29__last_point_of_inner_ring_p1_MASK
 
- VGT_DEBUG_REG29__last_point_of_inner_ring_p1__SHIFT
 
- VGT_DEBUG_REG29__last_point_of_outer_ring_p1_MASK
 
- VGT_DEBUG_REG29__last_point_of_outer_ring_p1__SHIFT
 
- VGT_DEBUG_REG29__last_ring_of_patch_p0_q_MASK
 
- VGT_DEBUG_REG29__last_ring_of_patch_p0_q__SHIFT
 
- VGT_DEBUG_REG29__next_ring_is_rect_p0_q_MASK
 
- VGT_DEBUG_REG29__next_ring_is_rect_p0_q__SHIFT
 
- VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q_MASK
 
- VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q__SHIFT
 
- VGT_DEBUG_REG29__outer_parity_p0_q_MASK
 
- VGT_DEBUG_REG29__outer_parity_p0_q__SHIFT
 
- VGT_DEBUG_REG29__parallel_parity_p0_q_MASK
 
- VGT_DEBUG_REG29__parallel_parity_p0_q__SHIFT
 
- VGT_DEBUG_REG29__pipe0_edge_dr_MASK
 
- VGT_DEBUG_REG29__pipe0_edge_dr__SHIFT
 
- VGT_DEBUG_REG29__pipe0_edge_rtr_MASK
 
- VGT_DEBUG_REG29__pipe0_edge_rtr__SHIFT
 
- VGT_DEBUG_REG29__pipe0_patch_dr_MASK
 
- VGT_DEBUG_REG29__pipe0_patch_dr__SHIFT
 
- VGT_DEBUG_REG29__pipe0_patch_rtr_MASK
 
- VGT_DEBUG_REG29__pipe0_patch_rtr__SHIFT
 
- VGT_DEBUG_REG29__pipe1_dr_MASK
 
- VGT_DEBUG_REG29__pipe1_dr__SHIFT
 
- VGT_DEBUG_REG29__pipe1_edge_rtr_MASK
 
- VGT_DEBUG_REG29__pipe1_edge_rtr__SHIFT
 
- VGT_DEBUG_REG29__pipe1_inner1_rtr_MASK
 
- VGT_DEBUG_REG29__pipe1_inner1_rtr__SHIFT
 
- VGT_DEBUG_REG29__pipe1_inner2_rtr_MASK
 
- VGT_DEBUG_REG29__pipe1_inner2_rtr__SHIFT
 
- VGT_DEBUG_REG29__pipe1_outer1_rtr_MASK
 
- VGT_DEBUG_REG29__pipe1_outer1_rtr__SHIFT
 
- VGT_DEBUG_REG29__pipe1_outer2_rtr_MASK
 
- VGT_DEBUG_REG29__pipe1_outer2_rtr__SHIFT
 
- VGT_DEBUG_REG29__pipe1_patch_rtr_MASK
 
- VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT
 
- VGT_DEBUG_REG29__pipe1_rtr_MASK
 
- VGT_DEBUG_REG29__pipe1_rtr__SHIFT
 
- VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q_MASK
 
- VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q__SHIFT
 
- VGT_DEBUG_REG29__process_tri_center_poly_p0_q_MASK
 
- VGT_DEBUG_REG29__process_tri_center_poly_p0_q__SHIFT
 
- VGT_DEBUG_REG29__process_tri_middle_p0_q_MASK
 
- VGT_DEBUG_REG29__process_tri_middle_p0_q__SHIFT
 
- VGT_DEBUG_REG29__second_cycle_q_MASK
 
- VGT_DEBUG_REG29__second_cycle_q__SHIFT
 
- VGT_DEBUG_REG29__use_stored_inner_q_ring3_MASK
 
- VGT_DEBUG_REG29__use_stored_inner_q_ring3__SHIFT
 
- VGT_DEBUG_REG2__SPARE_MASK
 
- VGT_DEBUG_REG2__SPARE__SHIFT
 
- VGT_DEBUG_REG2__grpModBusy_MASK
 
- VGT_DEBUG_REG2__grpModBusy__SHIFT
 
- VGT_DEBUG_REG2__hsInputFifoEmpty_MASK
 
- VGT_DEBUG_REG2__hsInputFifoEmpty__SHIFT
 
- VGT_DEBUG_REG2__hsInputFifoFull_MASK
 
- VGT_DEBUG_REG2__hsInputFifoFull__SHIFT
 
- VGT_DEBUG_REG2__hsTifFifoEmpty_MASK
 
- VGT_DEBUG_REG2__hsTifFifoEmpty__SHIFT
 
- VGT_DEBUG_REG2__hsTifFifoFull_MASK
 
- VGT_DEBUG_REG2__hsTifFifoFull__SHIFT
 
- VGT_DEBUG_REG2__hsVertFifoEmpty_MASK
 
- VGT_DEBUG_REG2__hsVertFifoEmpty__SHIFT
 
- VGT_DEBUG_REG2__hsVertFifoFull_MASK
 
- VGT_DEBUG_REG2__hsVertFifoFull__SHIFT
 
- VGT_DEBUG_REG2__hsWaveFifoEmpty_MASK
 
- VGT_DEBUG_REG2__hsWaveFifoEmpty__SHIFT
 
- VGT_DEBUG_REG2__hsWaveFifoFull_MASK
 
- VGT_DEBUG_REG2__hsWaveFifoFull__SHIFT
 
- VGT_DEBUG_REG2__hs_grp_busy_MASK
 
- VGT_DEBUG_REG2__hs_grp_busy__SHIFT
 
- VGT_DEBUG_REG2__hs_noif_busy_MASK
 
- VGT_DEBUG_REG2__hs_noif_busy__SHIFT
 
- VGT_DEBUG_REG2__hs_te11_tess_input_rts_MASK
 
- VGT_DEBUG_REG2__hs_te11_tess_input_rts__SHIFT
 
- VGT_DEBUG_REG2__lsFwaveFlag_MASK
 
- VGT_DEBUG_REG2__lsFwaveFlag__SHIFT
 
- VGT_DEBUG_REG2__lsVertFifoEmpty_MASK
 
- VGT_DEBUG_REG2__lsVertFifoEmpty__SHIFT
 
- VGT_DEBUG_REG2__lsVertFifoFull_MASK
 
- VGT_DEBUG_REG2__lsVertFifoFull__SHIFT
 
- VGT_DEBUG_REG2__lsVertIfBusy_0_MASK
 
- VGT_DEBUG_REG2__lsVertIfBusy_0__SHIFT
 
- VGT_DEBUG_REG2__lsWaveFifoEmpty_MASK
 
- VGT_DEBUG_REG2__lsWaveFifoEmpty__SHIFT
 
- VGT_DEBUG_REG2__lsWaveFifoFull_MASK
 
- VGT_DEBUG_REG2__lsWaveFifoFull__SHIFT
 
- VGT_DEBUG_REG2__lsWaveIfBusy_0_MASK
 
- VGT_DEBUG_REG2__lsWaveIfBusy_0__SHIFT
 
- VGT_DEBUG_REG2__lsWaveSendFlush_MASK
 
- VGT_DEBUG_REG2__lsWaveSendFlush__SHIFT
 
- VGT_DEBUG_REG2__ls_sh_id_MASK
 
- VGT_DEBUG_REG2__ls_sh_id__SHIFT
 
- VGT_DEBUG_REG2__p0_dr_MASK
 
- VGT_DEBUG_REG2__p0_dr__SHIFT
 
- VGT_DEBUG_REG2__p0_rtr_MASK
 
- VGT_DEBUG_REG2__p0_rtr__SHIFT
 
- VGT_DEBUG_REG2__p0_rts_MASK
 
- VGT_DEBUG_REG2__p0_rts__SHIFT
 
- VGT_DEBUG_REG2__p1_dr_MASK
 
- VGT_DEBUG_REG2__p1_dr__SHIFT
 
- VGT_DEBUG_REG2__p1_rtr_MASK
 
- VGT_DEBUG_REG2__p1_rtr__SHIFT
 
- VGT_DEBUG_REG2__p1_rts_MASK
 
- VGT_DEBUG_REG2__p1_rts__SHIFT
 
- VGT_DEBUG_REG2__te11_hs_tess_input_rtr_MASK
 
- VGT_DEBUG_REG2__te11_hs_tess_input_rtr__SHIFT
 
- VGT_DEBUG_REG2__tfmmIsBusy_MASK
 
- VGT_DEBUG_REG2__tfmmIsBusy__SHIFT
 
- VGT_DEBUG_REG30__dynamic_hs_p0_q_MASK
 
- VGT_DEBUG_REG30__dynamic_hs_p0_q__SHIFT
 
- VGT_DEBUG_REG30__event_or_null_p0_q_MASK
 
- VGT_DEBUG_REG30__event_or_null_p0_q__SHIFT
 
- VGT_DEBUG_REG30__first_data_chunk_invalid_p0_q_MASK
 
- VGT_DEBUG_REG30__first_data_chunk_invalid_p0_q__SHIFT
 
- VGT_DEBUG_REG30__first_data_ret_of_req_p0_q_MASK
 
- VGT_DEBUG_REG30__first_data_ret_of_req_p0_q__SHIFT
 
- VGT_DEBUG_REG30__first_fetch_of_tg_p0_q_MASK
 
- VGT_DEBUG_REG30__first_fetch_of_tg_p0_q__SHIFT
 
- VGT_DEBUG_REG30__last_tf_of_tg_MASK
 
- VGT_DEBUG_REG30__last_tf_of_tg__SHIFT
 
- VGT_DEBUG_REG30__pipe0_dr_MASK
 
- VGT_DEBUG_REG30__pipe0_dr__SHIFT
 
- VGT_DEBUG_REG30__pipe0_rtr_MASK
 
- VGT_DEBUG_REG30__pipe0_rtr__SHIFT
 
- VGT_DEBUG_REG30__pipe0_tf_dr_MASK
 
- VGT_DEBUG_REG30__pipe0_tf_dr__SHIFT
 
- VGT_DEBUG_REG30__pipe1_rtr_MASK
 
- VGT_DEBUG_REG30__pipe1_rtr__SHIFT
 
- VGT_DEBUG_REG30__pipe1_tf_rtr_MASK
 
- VGT_DEBUG_REG30__pipe1_tf_rtr__SHIFT
 
- VGT_DEBUG_REG30__pipe2_dr_MASK
 
- VGT_DEBUG_REG30__pipe2_dr__SHIFT
 
- VGT_DEBUG_REG30__pipe2_rtr_MASK
 
- VGT_DEBUG_REG30__pipe2_rtr__SHIFT
 
- VGT_DEBUG_REG30__pipe4_dr_MASK
 
- VGT_DEBUG_REG30__pipe4_dr__SHIFT
 
- VGT_DEBUG_REG30__pipe4_rtr_MASK
 
- VGT_DEBUG_REG30__pipe4_rtr__SHIFT
 
- VGT_DEBUG_REG30__tf_fetch_state_q_MASK
 
- VGT_DEBUG_REG30__tf_fetch_state_q__SHIFT
 
- VGT_DEBUG_REG30__tf_pointer_p0_q_MASK
 
- VGT_DEBUG_REG30__tf_pointer_p0_q__SHIFT
 
- VGT_DEBUG_REG30__tf_xfer_count_p2_q_MASK
 
- VGT_DEBUG_REG30__tf_xfer_count_p2_q__SHIFT
 
- VGT_DEBUG_REG30__ttp_patch_fifo_empty_MASK
 
- VGT_DEBUG_REG30__ttp_patch_fifo_empty__SHIFT
 
- VGT_DEBUG_REG30__ttp_patch_fifo_full_MASK
 
- VGT_DEBUG_REG30__ttp_patch_fifo_full__SHIFT
 
- VGT_DEBUG_REG30__ttp_tf0_fifo_empty_MASK
 
- VGT_DEBUG_REG30__ttp_tf0_fifo_empty__SHIFT
 
- VGT_DEBUG_REG30__ttp_tf1_fifo_empty_MASK
 
- VGT_DEBUG_REG30__ttp_tf1_fifo_empty__SHIFT
 
- VGT_DEBUG_REG30__ttp_tf2_fifo_empty_MASK
 
- VGT_DEBUG_REG30__ttp_tf2_fifo_empty__SHIFT
 
- VGT_DEBUG_REG30__ttp_tf3_fifo_empty_MASK
 
- VGT_DEBUG_REG30__ttp_tf3_fifo_empty__SHIFT
 
- VGT_DEBUG_REG30__ttp_tf4_fifo_empty_MASK
 
- VGT_DEBUG_REG30__ttp_tf4_fifo_empty__SHIFT
 
- VGT_DEBUG_REG30__ttp_tf5_fifo_empty_MASK
 
- VGT_DEBUG_REG30__ttp_tf5_fifo_empty__SHIFT
 
- VGT_DEBUG_REG31__inner_ring_done_q_MASK
 
- VGT_DEBUG_REG31__inner_ring_done_q__SHIFT
 
- VGT_DEBUG_REG31__outer_ring_done_q_MASK
 
- VGT_DEBUG_REG31__outer_ring_done_q__SHIFT
 
- VGT_DEBUG_REG31__pg_con_inner_point1_rts_MASK
 
- VGT_DEBUG_REG31__pg_con_inner_point1_rts__SHIFT
 
- VGT_DEBUG_REG31__pg_con_inner_point2_rts_MASK
 
- VGT_DEBUG_REG31__pg_con_inner_point2_rts__SHIFT
 
- VGT_DEBUG_REG31__pg_con_outer_point1_rts_MASK
 
- VGT_DEBUG_REG31__pg_con_outer_point1_rts__SHIFT
 
- VGT_DEBUG_REG31__pg_con_outer_point2_rts_MASK
 
- VGT_DEBUG_REG31__pg_con_outer_point2_rts__SHIFT
 
- VGT_DEBUG_REG31__pg_edge_fifo_empty_MASK
 
- VGT_DEBUG_REG31__pg_edge_fifo_empty__SHIFT
 
- VGT_DEBUG_REG31__pg_edge_fifo_full_MASK
 
- VGT_DEBUG_REG31__pg_edge_fifo_full__SHIFT
 
- VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty_MASK
 
- VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty__SHIFT
 
- VGT_DEBUG_REG31__pg_inner_perp_fifo_full_MASK
 
- VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT
 
- VGT_DEBUG_REG31__pg_patch_fifo_empty_MASK
 
- VGT_DEBUG_REG31__pg_patch_fifo_empty__SHIFT
 
- VGT_DEBUG_REG31__pg_patch_fifo_full_MASK
 
- VGT_DEBUG_REG31__pg_patch_fifo_full__SHIFT
 
- VGT_DEBUG_REG31__pipe0_dr_MASK
 
- VGT_DEBUG_REG31__pipe0_dr__SHIFT
 
- VGT_DEBUG_REG31__pipe0_rtr_MASK
 
- VGT_DEBUG_REG31__pipe0_rtr__SHIFT
 
- VGT_DEBUG_REG31__pipe1_inner_dr_MASK
 
- VGT_DEBUG_REG31__pipe1_inner_dr__SHIFT
 
- VGT_DEBUG_REG31__pipe1_outer_dr_MASK
 
- VGT_DEBUG_REG31__pipe1_outer_dr__SHIFT
 
- VGT_DEBUG_REG31__pipe2_inner_dr_MASK
 
- VGT_DEBUG_REG31__pipe2_inner_dr__SHIFT
 
- VGT_DEBUG_REG31__pipe2_inner_rtr_MASK
 
- VGT_DEBUG_REG31__pipe2_inner_rtr__SHIFT
 
- VGT_DEBUG_REG31__pipe2_outer_dr_MASK
 
- VGT_DEBUG_REG31__pipe2_outer_dr__SHIFT
 
- VGT_DEBUG_REG31__pipe2_outer_rtr_MASK
 
- VGT_DEBUG_REG31__pipe2_outer_rtr__SHIFT
 
- VGT_DEBUG_REG31__pipe3_inner_dr_MASK
 
- VGT_DEBUG_REG31__pipe3_inner_dr__SHIFT
 
- VGT_DEBUG_REG31__pipe3_inner_rtr_MASK
 
- VGT_DEBUG_REG31__pipe3_inner_rtr__SHIFT
 
- VGT_DEBUG_REG31__pipe3_outer_dr_MASK
 
- VGT_DEBUG_REG31__pipe3_outer_dr__SHIFT
 
- VGT_DEBUG_REG31__pipe3_outer_rtr_MASK
 
- VGT_DEBUG_REG31__pipe3_outer_rtr__SHIFT
 
- VGT_DEBUG_REG31__pipe4_inner_dr_MASK
 
- VGT_DEBUG_REG31__pipe4_inner_dr__SHIFT
 
- VGT_DEBUG_REG31__pipe4_inner_rtr_MASK
 
- VGT_DEBUG_REG31__pipe4_inner_rtr__SHIFT
 
- VGT_DEBUG_REG31__pipe4_outer_dr_MASK
 
- VGT_DEBUG_REG31__pipe4_outer_dr__SHIFT
 
- VGT_DEBUG_REG31__pipe4_outer_rtr_MASK
 
- VGT_DEBUG_REG31__pipe4_outer_rtr__SHIFT
 
- VGT_DEBUG_REG31__pipe5_inner_dr_MASK
 
- VGT_DEBUG_REG31__pipe5_inner_dr__SHIFT
 
- VGT_DEBUG_REG31__pipe5_inner_rtr_MASK
 
- VGT_DEBUG_REG31__pipe5_inner_rtr__SHIFT
 
- VGT_DEBUG_REG31__pipe5_outer_dr_MASK
 
- VGT_DEBUG_REG31__pipe5_outer_dr__SHIFT
 
- VGT_DEBUG_REG31__pipe5_outer_rtr_MASK
 
- VGT_DEBUG_REG31__pipe5_outer_rtr__SHIFT
 
- VGT_DEBUG_REG32__SPARE_MASK
 
- VGT_DEBUG_REG32__SPARE__SHIFT
 
- VGT_DEBUG_REG32__event_flag_p5_q_MASK
 
- VGT_DEBUG_REG32__event_flag_p5_q__SHIFT
 
- VGT_DEBUG_REG32__event_null_special_p0_q_MASK
 
- VGT_DEBUG_REG32__event_null_special_p0_q__SHIFT
 
- VGT_DEBUG_REG32__fifos_rtr_MASK
 
- VGT_DEBUG_REG32__fifos_rtr__SHIFT
 
- VGT_DEBUG_REG32__first_point_of_edge_p5_q_MASK
 
- VGT_DEBUG_REG32__first_point_of_edge_p5_q__SHIFT
 
- VGT_DEBUG_REG32__first_point_of_patch_p5_q_MASK
 
- VGT_DEBUG_REG32__first_point_of_patch_p5_q__SHIFT
 
- VGT_DEBUG_REG32__first_ring_of_patch_MASK
 
- VGT_DEBUG_REG32__first_ring_of_patch__SHIFT
 
- VGT_DEBUG_REG32__inner2_fifos_rtr_MASK
 
- VGT_DEBUG_REG32__inner2_fifos_rtr__SHIFT
 
- VGT_DEBUG_REG32__inner_fifos_rtr_MASK
 
- VGT_DEBUG_REG32__inner_fifos_rtr__SHIFT
 
- VGT_DEBUG_REG32__last_edge_of_inner_ring_MASK
 
- VGT_DEBUG_REG32__last_edge_of_inner_ring__SHIFT
 
- VGT_DEBUG_REG32__last_edge_of_outer_ring_MASK
 
- VGT_DEBUG_REG32__last_edge_of_outer_ring__SHIFT
 
- VGT_DEBUG_REG32__last_patch_of_tg_p0_q_MASK
 
- VGT_DEBUG_REG32__last_patch_of_tg_p0_q__SHIFT
 
- VGT_DEBUG_REG32__last_patch_of_tg_p5_q_MASK
 
- VGT_DEBUG_REG32__last_patch_of_tg_p5_q__SHIFT
 
- VGT_DEBUG_REG32__last_point_of_inner_edge_MASK
 
- VGT_DEBUG_REG32__last_point_of_inner_edge__SHIFT
 
- VGT_DEBUG_REG32__last_point_of_outer_edge_MASK
 
- VGT_DEBUG_REG32__last_point_of_outer_edge__SHIFT
 
- VGT_DEBUG_REG32__last_ring_of_patch_MASK
 
- VGT_DEBUG_REG32__last_ring_of_patch__SHIFT
 
- VGT_DEBUG_REG32__outer_fifos_rtr_MASK
 
- VGT_DEBUG_REG32__outer_fifos_rtr__SHIFT
 
- VGT_DEBUG_REG32__pg_edge_fifo2_full_MASK
 
- VGT_DEBUG_REG32__pg_edge_fifo2_full__SHIFT
 
- VGT_DEBUG_REG32__pg_edge_fifo3_full_MASK
 
- VGT_DEBUG_REG32__pg_edge_fifo3_full__SHIFT
 
- VGT_DEBUG_REG32__pg_inner2_point_fifo_full_MASK
 
- VGT_DEBUG_REG32__pg_inner2_point_fifo_full__SHIFT
 
- VGT_DEBUG_REG32__pg_inner3_point_fifo_full_MASK
 
- VGT_DEBUG_REG32__pg_inner3_point_fifo_full__SHIFT
 
- VGT_DEBUG_REG32__pg_inner_point_fifo_full_MASK
 
- VGT_DEBUG_REG32__pg_inner_point_fifo_full__SHIFT
 
- VGT_DEBUG_REG32__pg_outer2_point_fifo_full_MASK
 
- VGT_DEBUG_REG32__pg_outer2_point_fifo_full__SHIFT
 
- VGT_DEBUG_REG32__pg_outer3_point_fifo_full_MASK
 
- VGT_DEBUG_REG32__pg_outer3_point_fifo_full__SHIFT
 
- VGT_DEBUG_REG32__pg_outer_point_fifo_full_MASK
 
- VGT_DEBUG_REG32__pg_outer_point_fifo_full__SHIFT
 
- VGT_DEBUG_REG32__pipe5_inner2_rtr_MASK
 
- VGT_DEBUG_REG32__pipe5_inner2_rtr__SHIFT
 
- VGT_DEBUG_REG32__pipe5_inner3_rtr_MASK
 
- VGT_DEBUG_REG32__pipe5_inner3_rtr__SHIFT
 
- VGT_DEBUG_REG32__tess_topology_p5_q_MASK
 
- VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT
 
- VGT_DEBUG_REG33__con_prim_fifo_empty_MASK
 
- VGT_DEBUG_REG33__con_prim_fifo_empty__SHIFT
 
- VGT_DEBUG_REG33__con_prim_fifo_full_MASK
 
- VGT_DEBUG_REG33__con_prim_fifo_full__SHIFT
 
- VGT_DEBUG_REG33__con_ring1_busy_MASK
 
- VGT_DEBUG_REG33__con_ring1_busy__SHIFT
 
- VGT_DEBUG_REG33__con_ring2_busy_MASK
 
- VGT_DEBUG_REG33__con_ring2_busy__SHIFT
 
- VGT_DEBUG_REG33__con_ring3_busy_MASK
 
- VGT_DEBUG_REG33__con_ring3_busy__SHIFT
 
- VGT_DEBUG_REG33__con_vert_fifo_empty_MASK
 
- VGT_DEBUG_REG33__con_vert_fifo_empty__SHIFT
 
- VGT_DEBUG_REG33__con_vert_fifo_full_MASK
 
- VGT_DEBUG_REG33__con_vert_fifo_full__SHIFT
 
- VGT_DEBUG_REG33__first_prim_of_patch_q_MASK
 
- VGT_DEBUG_REG33__first_prim_of_patch_q__SHIFT
 
- VGT_DEBUG_REG33__last_patch_of_tg_p0_q_MASK
 
- VGT_DEBUG_REG33__last_patch_of_tg_p0_q__SHIFT
 
- VGT_DEBUG_REG33__pipe0_patch_dr_MASK
 
- VGT_DEBUG_REG33__pipe0_patch_dr__SHIFT
 
- VGT_DEBUG_REG33__pipe0_patch_rtr_MASK
 
- VGT_DEBUG_REG33__pipe0_patch_rtr__SHIFT
 
- VGT_DEBUG_REG33__pipe1_dr_MASK
 
- VGT_DEBUG_REG33__pipe1_dr__SHIFT
 
- VGT_DEBUG_REG33__pipe1_patch_rtr_MASK
 
- VGT_DEBUG_REG33__pipe1_patch_rtr__SHIFT
 
- VGT_DEBUG_REG33__pipe2_dr_MASK
 
- VGT_DEBUG_REG33__pipe2_dr__SHIFT
 
- VGT_DEBUG_REG33__pipe2_rtr_MASK
 
- VGT_DEBUG_REG33__pipe2_rtr__SHIFT
 
- VGT_DEBUG_REG33__pipe3_dr_MASK
 
- VGT_DEBUG_REG33__pipe3_dr__SHIFT
 
- VGT_DEBUG_REG33__pipe3_rtr_MASK
 
- VGT_DEBUG_REG33__pipe3_rtr__SHIFT
 
- VGT_DEBUG_REG33__ring1_in_sync_q_MASK
 
- VGT_DEBUG_REG33__ring1_in_sync_q__SHIFT
 
- VGT_DEBUG_REG33__ring1_pipe1_dr_MASK
 
- VGT_DEBUG_REG33__ring1_pipe1_dr__SHIFT
 
- VGT_DEBUG_REG33__ring1_valid_p2_MASK
 
- VGT_DEBUG_REG33__ring1_valid_p2__SHIFT
 
- VGT_DEBUG_REG33__ring2_in_sync_q_MASK
 
- VGT_DEBUG_REG33__ring2_in_sync_q__SHIFT
 
- VGT_DEBUG_REG33__ring2_pipe1_dr_MASK
 
- VGT_DEBUG_REG33__ring2_pipe1_dr__SHIFT
 
- VGT_DEBUG_REG33__ring2_valid_p2_MASK
 
- VGT_DEBUG_REG33__ring2_valid_p2__SHIFT
 
- VGT_DEBUG_REG33__ring3_in_sync_q_MASK
 
- VGT_DEBUG_REG33__ring3_in_sync_q__SHIFT
 
- VGT_DEBUG_REG33__ring3_pipe1_dr_MASK
 
- VGT_DEBUG_REG33__ring3_pipe1_dr__SHIFT
 
- VGT_DEBUG_REG33__ring3_valid_p2_MASK
 
- VGT_DEBUG_REG33__ring3_valid_p2__SHIFT
 
- VGT_DEBUG_REG33__te11_out_vert_gs_en_MASK
 
- VGT_DEBUG_REG33__te11_out_vert_gs_en__SHIFT
 
- VGT_DEBUG_REG33__tess_topology_p0_q_MASK
 
- VGT_DEBUG_REG33__tess_topology_p0_q__SHIFT
 
- VGT_DEBUG_REG33__tess_type_p0_q_MASK
 
- VGT_DEBUG_REG33__tess_type_p0_q__SHIFT
 
- VGT_DEBUG_REG33__tm_te11_event_rtr_MASK
 
- VGT_DEBUG_REG33__tm_te11_event_rtr__SHIFT
 
- VGT_DEBUG_REG34__advance_inner_point_p1_MASK
 
- VGT_DEBUG_REG34__advance_inner_point_p1__SHIFT
 
- VGT_DEBUG_REG34__advance_outer_point_p1_MASK
 
- VGT_DEBUG_REG34__advance_outer_point_p1__SHIFT
 
- VGT_DEBUG_REG34__con_state_q_MASK
 
- VGT_DEBUG_REG34__con_state_q__SHIFT
 
- VGT_DEBUG_REG34__first_ring_of_patch_p0_q_MASK
 
- VGT_DEBUG_REG34__first_ring_of_patch_p0_q__SHIFT
 
- VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q_MASK
 
- VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q__SHIFT
 
- VGT_DEBUG_REG34__last_point_of_inner_ring_p1_MASK
 
- VGT_DEBUG_REG34__last_point_of_inner_ring_p1__SHIFT
 
- VGT_DEBUG_REG34__last_point_of_outer_ring_p1_MASK
 
- VGT_DEBUG_REG34__last_point_of_outer_ring_p1__SHIFT
 
- VGT_DEBUG_REG34__last_ring_of_patch_p0_q_MASK
 
- VGT_DEBUG_REG34__last_ring_of_patch_p0_q__SHIFT
 
- VGT_DEBUG_REG34__next_ring_is_rect_p0_q_MASK
 
- VGT_DEBUG_REG34__next_ring_is_rect_p0_q__SHIFT
 
- VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q_MASK
 
- VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT
 
- VGT_DEBUG_REG34__outer_parity_p0_q_MASK
 
- VGT_DEBUG_REG34__outer_parity_p0_q__SHIFT
 
- VGT_DEBUG_REG34__parallel_parity_p0_q_MASK
 
- VGT_DEBUG_REG34__parallel_parity_p0_q__SHIFT
 
- VGT_DEBUG_REG34__pipe0_edge_dr_MASK
 
- VGT_DEBUG_REG34__pipe0_edge_dr__SHIFT
 
- VGT_DEBUG_REG34__pipe0_edge_rtr_MASK
 
- VGT_DEBUG_REG34__pipe0_edge_rtr__SHIFT
 
- VGT_DEBUG_REG34__pipe0_patch_dr_MASK
 
- VGT_DEBUG_REG34__pipe0_patch_dr__SHIFT
 
- VGT_DEBUG_REG34__pipe0_patch_rtr_MASK
 
- VGT_DEBUG_REG34__pipe0_patch_rtr__SHIFT
 
- VGT_DEBUG_REG34__pipe1_dr_MASK
 
- VGT_DEBUG_REG34__pipe1_dr__SHIFT
 
- VGT_DEBUG_REG34__pipe1_edge_rtr_MASK
 
- VGT_DEBUG_REG34__pipe1_edge_rtr__SHIFT
 
- VGT_DEBUG_REG34__pipe1_inner1_rtr_MASK
 
- VGT_DEBUG_REG34__pipe1_inner1_rtr__SHIFT
 
- VGT_DEBUG_REG34__pipe1_inner2_rtr_MASK
 
- VGT_DEBUG_REG34__pipe1_inner2_rtr__SHIFT
 
- VGT_DEBUG_REG34__pipe1_outer1_rtr_MASK
 
- VGT_DEBUG_REG34__pipe1_outer1_rtr__SHIFT
 
- VGT_DEBUG_REG34__pipe1_outer2_rtr_MASK
 
- VGT_DEBUG_REG34__pipe1_outer2_rtr__SHIFT
 
- VGT_DEBUG_REG34__pipe1_patch_rtr_MASK
 
- VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT
 
- VGT_DEBUG_REG34__pipe1_rtr_MASK
 
- VGT_DEBUG_REG34__pipe1_rtr__SHIFT
 
- VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q_MASK
 
- VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q__SHIFT
 
- VGT_DEBUG_REG34__process_tri_center_poly_p0_q_MASK
 
- VGT_DEBUG_REG34__process_tri_center_poly_p0_q__SHIFT
 
- VGT_DEBUG_REG34__process_tri_middle_p0_q_MASK
 
- VGT_DEBUG_REG34__process_tri_middle_p0_q__SHIFT
 
- VGT_DEBUG_REG34__second_cycle_q_MASK
 
- VGT_DEBUG_REG34__second_cycle_q__SHIFT
 
- VGT_DEBUG_REG34__use_stored_inner_q_ring1_MASK
 
- VGT_DEBUG_REG34__use_stored_inner_q_ring1__SHIFT
 
- VGT_DEBUG_REG35__TC_VGT_rdret_data_in_MASK
 
- VGT_DEBUG_REG35__TC_VGT_rdret_data_in__SHIFT
 
- VGT_DEBUG_REG35__VGT_TC_rdnfo_stall_out_MASK
 
- VGT_DEBUG_REG35__VGT_TC_rdnfo_stall_out__SHIFT
 
- VGT_DEBUG_REG35__VGT_TC_rdreq_send_out_MASK
 
- VGT_DEBUG_REG35__VGT_TC_rdreq_send_out__SHIFT
 
- VGT_DEBUG_REG35__event_flag_p1_q_MASK
 
- VGT_DEBUG_REG35__event_flag_p1_q__SHIFT
 
- VGT_DEBUG_REG35__first_req_of_tg_p1_q_MASK
 
- VGT_DEBUG_REG35__first_req_of_tg_p1_q__SHIFT
 
- VGT_DEBUG_REG35__last_req_of_tg_p2_MASK
 
- VGT_DEBUG_REG35__last_req_of_tg_p2__SHIFT
 
- VGT_DEBUG_REG35__null_flag_p1_q_MASK
 
- VGT_DEBUG_REG35__null_flag_p1_q__SHIFT
 
- VGT_DEBUG_REG35__pipe0_dr_MASK
 
- VGT_DEBUG_REG35__pipe0_dr__SHIFT
 
- VGT_DEBUG_REG35__pipe0_rtr_MASK
 
- VGT_DEBUG_REG35__pipe0_rtr__SHIFT
 
- VGT_DEBUG_REG35__pipe1_dr_MASK
 
- VGT_DEBUG_REG35__pipe1_dr__SHIFT
 
- VGT_DEBUG_REG35__pipe1_rtr_MASK
 
- VGT_DEBUG_REG35__pipe1_rtr__SHIFT
 
- VGT_DEBUG_REG35__second_tf_ret_data_q_MASK
 
- VGT_DEBUG_REG35__second_tf_ret_data_q__SHIFT
 
- VGT_DEBUG_REG35__spi_vgt_hs_done_cnt_q_MASK
 
- VGT_DEBUG_REG35__spi_vgt_hs_done_cnt_q__SHIFT
 
- VGT_DEBUG_REG35__tf_data_fifo_busy_q_MASK
 
- VGT_DEBUG_REG35__tf_data_fifo_busy_q__SHIFT
 
- VGT_DEBUG_REG35__tf_data_fifo_cnt_q_MASK
 
- VGT_DEBUG_REG35__tf_data_fifo_cnt_q__SHIFT
 
- VGT_DEBUG_REG35__tf_data_fifo_rtr_q_MASK
 
- VGT_DEBUG_REG35__tf_data_fifo_rtr_q__SHIFT
 
- VGT_DEBUG_REG35__tf_skid_fifo_empty_MASK
 
- VGT_DEBUG_REG35__tf_skid_fifo_empty__SHIFT
 
- VGT_DEBUG_REG35__tf_skid_fifo_full_MASK
 
- VGT_DEBUG_REG35__tf_skid_fifo_full__SHIFT
 
- VGT_DEBUG_REG35__tfreq_tg_fifo_empty_MASK
 
- VGT_DEBUG_REG35__tfreq_tg_fifo_empty__SHIFT
 
- VGT_DEBUG_REG35__tfreq_tg_fifo_full_MASK
 
- VGT_DEBUG_REG35__tfreq_tg_fifo_full__SHIFT
 
- VGT_DEBUG_REG35__vgt_tc_rdreq_rtr_q_MASK
 
- VGT_DEBUG_REG35__vgt_tc_rdreq_rtr_q__SHIFT
 
- VGT_DEBUG_REG36__VGT_PA_clipp_eop_MASK
 
- VGT_DEBUG_REG36__VGT_PA_clipp_eop__SHIFT
 
- VGT_DEBUG_REG3__hsWaveRelInd_MASK
 
- VGT_DEBUG_REG3__hsWaveRelInd__SHIFT
 
- VGT_DEBUG_REG3__lsPatchCnt_MASK
 
- VGT_DEBUG_REG3__lsPatchCnt__SHIFT
 
- VGT_DEBUG_REG3__lsTgRelInd_MASK
 
- VGT_DEBUG_REG3__lsTgRelInd__SHIFT
 
- VGT_DEBUG_REG3__lsWaveRelInd_MASK
 
- VGT_DEBUG_REG3__lsWaveRelInd__SHIFT
 
- VGT_DEBUG_REG4__SPARE_MASK
 
- VGT_DEBUG_REG4__SPARE__SHIFT
 
- VGT_DEBUG_REG4__hsCpCnt_MASK
 
- VGT_DEBUG_REG4__hsCpCnt__SHIFT
 
- VGT_DEBUG_REG4__hsFwaveFlag_MASK
 
- VGT_DEBUG_REG4__hsFwaveFlag__SHIFT
 
- VGT_DEBUG_REG4__hsPatchCnt_MASK
 
- VGT_DEBUG_REG4__hsPatchCnt__SHIFT
 
- VGT_DEBUG_REG4__hsPrimId_15_0_MASK
 
- VGT_DEBUG_REG4__hsPrimId_15_0__SHIFT
 
- VGT_DEBUG_REG4__hsWaveSendFlush_MASK
 
- VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT
 
- VGT_DEBUG_REG5__SPARE1_MASK
 
- VGT_DEBUG_REG5__SPARE1__SHIFT
 
- VGT_DEBUG_REG5__SPARE2_MASK
 
- VGT_DEBUG_REG5__SPARE2__SHIFT
 
- VGT_DEBUG_REG5__SPARE3_MASK
 
- VGT_DEBUG_REG5__SPARE3__SHIFT
 
- VGT_DEBUG_REG5__SPARE4_MASK
 
- VGT_DEBUG_REG5__SPARE4__SHIFT
 
- VGT_DEBUG_REG5__hsVertCreditCnt_0_MASK
 
- VGT_DEBUG_REG5__hsVertCreditCnt_0__SHIFT
 
- VGT_DEBUG_REG5__hsWaveCreditCnt_0_MASK
 
- VGT_DEBUG_REG5__hsWaveCreditCnt_0__SHIFT
 
- VGT_DEBUG_REG5__lsVertCreditCnt_0_MASK
 
- VGT_DEBUG_REG5__lsVertCreditCnt_0__SHIFT
 
- VGT_DEBUG_REG5__lsWaveCreditCnt_0_MASK
 
- VGT_DEBUG_REG5__lsWaveCreditCnt_0__SHIFT
 
- VGT_DEBUG_REG6__debug_BASE_MASK
 
- VGT_DEBUG_REG6__debug_BASE__SHIFT
 
- VGT_DEBUG_REG6__debug_SIZE_MASK
 
- VGT_DEBUG_REG6__debug_SIZE__SHIFT
 
- VGT_DEBUG_REG7__SPARE_MASK
 
- VGT_DEBUG_REG7__SPARE__SHIFT
 
- VGT_DEBUG_REG7__TF_addr_MASK
 
- VGT_DEBUG_REG7__TF_addr__SHIFT
 
- VGT_DEBUG_REG7__debug_tfmmFifoEmpty_MASK
 
- VGT_DEBUG_REG7__debug_tfmmFifoEmpty__SHIFT
 
- VGT_DEBUG_REG7__debug_tfmmFifoFull_MASK
 
- VGT_DEBUG_REG7__debug_tfmmFifoFull__SHIFT
 
- VGT_DEBUG_REG7__hs_pipe0_dr_MASK
 
- VGT_DEBUG_REG7__hs_pipe0_dr__SHIFT
 
- VGT_DEBUG_REG7__hs_pipe0_rtr_MASK
 
- VGT_DEBUG_REG7__hs_pipe0_rtr__SHIFT
 
- VGT_DEBUG_REG7__hs_pipe1_rtr_MASK
 
- VGT_DEBUG_REG7__hs_pipe1_rtr__SHIFT
 
- VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q_MASK
 
- VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q__SHIFT
 
- VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q_MASK
 
- VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q__SHIFT
 
- VGT_DEBUG_REG8__es_gs_rtr_MASK
 
- VGT_DEBUG_REG8__es_gs_rtr__SHIFT
 
- VGT_DEBUG_REG8__gs_event_fifo_empty_MASK
 
- VGT_DEBUG_REG8__gs_event_fifo_empty__SHIFT
 
- VGT_DEBUG_REG8__gs_event_fifo_rtr_MASK
 
- VGT_DEBUG_REG8__gs_event_fifo_rtr__SHIFT
 
- VGT_DEBUG_REG8__gs_tbl_r3_rtr_MASK
 
- VGT_DEBUG_REG8__gs_tbl_r3_rtr__SHIFT
 
- VGT_DEBUG_REG8__gs_tbl_valid_r3_q_MASK
 
- VGT_DEBUG_REG8__gs_tbl_valid_r3_q__SHIFT
 
- VGT_DEBUG_REG8__gsprim_buff_empty_q_MASK
 
- VGT_DEBUG_REG8__gsprim_buff_empty_q__SHIFT
 
- VGT_DEBUG_REG8__gsprim_buff_full_q_MASK
 
- VGT_DEBUG_REG8__gsprim_buff_full_q__SHIFT
 
- VGT_DEBUG_REG8__hold_for_es_flush_MASK
 
- VGT_DEBUG_REG8__hold_for_es_flush__SHIFT
 
- VGT_DEBUG_REG8__prim_skid_fifo_empty_MASK
 
- VGT_DEBUG_REG8__prim_skid_fifo_empty__SHIFT
 
- VGT_DEBUG_REG8__r0_rtr_MASK
 
- VGT_DEBUG_REG8__r0_rtr__SHIFT
 
- VGT_DEBUG_REG8__r1_inst_rtr_MASK
 
- VGT_DEBUG_REG8__r1_inst_rtr__SHIFT
 
- VGT_DEBUG_REG8__r1_rtr_MASK
 
- VGT_DEBUG_REG8__r1_rtr__SHIFT
 
- VGT_DEBUG_REG8__r2_indx_rtr_MASK
 
- VGT_DEBUG_REG8__r2_indx_rtr__SHIFT
 
- VGT_DEBUG_REG8__r2_no_bp_rtr_MASK
 
- VGT_DEBUG_REG8__r2_no_bp_rtr__SHIFT
 
- VGT_DEBUG_REG8__r2_rtr_MASK
 
- VGT_DEBUG_REG8__r2_rtr__SHIFT
 
- VGT_DEBUG_REG8__rcm_busy_q_MASK
 
- VGT_DEBUG_REG8__rcm_busy_q__SHIFT
 
- VGT_DEBUG_REG8__rcm_noif_busy_q_MASK
 
- VGT_DEBUG_REG8__rcm_noif_busy_q__SHIFT
 
- VGT_DEBUG_REG8__spi_esvert_fifo_busy_q_MASK
 
- VGT_DEBUG_REG8__spi_esvert_fifo_busy_q__SHIFT
 
- VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q_MASK
 
- VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q__SHIFT
 
- VGT_DEBUG_REG8__te_prim_fifo_empty_MASK
 
- VGT_DEBUG_REG8__te_prim_fifo_empty__SHIFT
 
- VGT_DEBUG_REG8__te_prim_fifo_full_MASK
 
- VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT
 
- VGT_DEBUG_REG8__te_vert_fifo_empty_MASK
 
- VGT_DEBUG_REG8__te_vert_fifo_empty__SHIFT
 
- VGT_DEBUG_REG8__te_vert_fifo_full_MASK
 
- VGT_DEBUG_REG8__te_vert_fifo_full__SHIFT
 
- VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr_MASK
 
- VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr__SHIFT
 
- VGT_DEBUG_REG8__tm_rcm_gs_event_rtr_MASK
 
- VGT_DEBUG_REG8__tm_rcm_gs_event_rtr__SHIFT
 
- VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr_MASK
 
- VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr__SHIFT
 
- VGT_DEBUG_REG8__valid_r0_q_MASK
 
- VGT_DEBUG_REG8__valid_r0_q__SHIFT
 
- VGT_DEBUG_REG8__valid_r1_q_MASK
 
- VGT_DEBUG_REG8__valid_r1_q__SHIFT
 
- VGT_DEBUG_REG8__valid_r2_MASK
 
- VGT_DEBUG_REG8__valid_r2__SHIFT
 
- VGT_DEBUG_REG8__valid_r2_q_MASK
 
- VGT_DEBUG_REG8__valid_r2_q__SHIFT
 
- VGT_DEBUG_REG9__SPARE0_MASK
 
- VGT_DEBUG_REG9__SPARE0__SHIFT
 
- VGT_DEBUG_REG9__eop_indx_r3_MASK
 
- VGT_DEBUG_REG9__eop_indx_r3__SHIFT
 
- VGT_DEBUG_REG9__eop_prim_r3_MASK
 
- VGT_DEBUG_REG9__eop_prim_r3__SHIFT
 
- VGT_DEBUG_REG9__es_eov_r3_MASK
 
- VGT_DEBUG_REG9__es_eov_r3__SHIFT
 
- VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0_MASK
 
- VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0__SHIFT
 
- VGT_DEBUG_REG9__es_tbl_state_r3_q_0_MASK
 
- VGT_DEBUG_REG9__es_tbl_state_r3_q_0__SHIFT
 
- VGT_DEBUG_REG9__gs_eov_r3_MASK
 
- VGT_DEBUG_REG9__gs_eov_r3__SHIFT
 
- VGT_DEBUG_REG9__gs_instancing_state_q_MASK
 
- VGT_DEBUG_REG9__gs_instancing_state_q__SHIFT
 
- VGT_DEBUG_REG9__gs_pending_state_r3_q_MASK
 
- VGT_DEBUG_REG9__gs_pending_state_r3_q__SHIFT
 
- VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0_MASK
 
- VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0__SHIFT
 
- VGT_DEBUG_REG9__gs_tbl_eop_r3_q_MASK
 
- VGT_DEBUG_REG9__gs_tbl_eop_r3_q__SHIFT
 
- VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0_MASK
 
- VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0__SHIFT
 
- VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q_MASK
 
- VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q__SHIFT
 
- VGT_DEBUG_REG9__gs_tbl_state_r3_q_MASK
 
- VGT_DEBUG_REG9__gs_tbl_state_r3_q__SHIFT
 
- VGT_DEBUG_REG9__indices_to_send_r2_q_MASK
 
- VGT_DEBUG_REG9__indices_to_send_r2_q__SHIFT
 
- VGT_DEBUG_REG9__invalidate_rb_roll_over_q_MASK
 
- VGT_DEBUG_REG9__invalidate_rb_roll_over_q__SHIFT
 
- VGT_DEBUG_REG9__off_chip_hs_r2_q_MASK
 
- VGT_DEBUG_REG9__off_chip_hs_r2_q__SHIFT
 
- VGT_DEBUG_REG9__pending_es_flush_r3_MASK
 
- VGT_DEBUG_REG9__pending_es_flush_r3__SHIFT
 
- VGT_DEBUG_REG9__pending_es_send_r3_q_MASK
 
- VGT_DEBUG_REG9__pending_es_send_r3_q__SHIFT
 
- VGT_DEBUG_REG9__pre_r0_rtr_MASK
 
- VGT_DEBUG_REG9__pre_r0_rtr__SHIFT
 
- VGT_DEBUG_REG9__valid_indices_r3_MASK
 
- VGT_DEBUG_REG9__valid_indices_r3__SHIFT
 
- VGT_DEBUG_REG9__valid_pre_r0_q_MASK
 
- VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT
 
- VGT_DEBUG_REG9__valid_r3_q_MASK
 
- VGT_DEBUG_REG9__valid_r3_q__SHIFT
 
- VGT_DETECT_ONE
 
- VGT_DETECT_ZERO
 
- VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK
 
- VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT
 
- VGT_DIST_MODE
 
- VGT_DI_INDEX_SIZE
 
- VGT_DI_MAJOR_MODE_SELECT
 
- VGT_DI_PRIM_TYPE
 
- VGT_DI_SOURCE_SELECT
 
- VGT_DMA_BASE
 
- VGT_DMA_BASE_HI
 
- VGT_DMA_BASE_HI__BASE_ADDR_MASK
 
- VGT_DMA_BASE_HI__BASE_ADDR__SHIFT
 
- VGT_DMA_BASE__BASE_ADDR_MASK
 
- VGT_DMA_BASE__BASE_ADDR__SHIFT
 
- VGT_DMA_BUF_MEM
 
- VGT_DMA_BUF_RING
 
- VGT_DMA_BUF_SETUP
 
- VGT_DMA_BUF_TYPE
 
- VGT_DMA_CONTROL__EN_INST_OPT_ADV_MASK
 
- VGT_DMA_CONTROL__EN_INST_OPT_ADV__SHIFT
 
- VGT_DMA_CONTROL__EN_INST_OPT_BASIC_MASK
 
- VGT_DMA_CONTROL__EN_INST_OPT_BASIC__SHIFT
 
- VGT_DMA_CONTROL__HW_USE_ONLY_MASK
 
- VGT_DMA_CONTROL__HW_USE_ONLY__SHIFT
 
- VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK
 
- VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT
 
- VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK
 
- VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT
 
- VGT_DMA_CONTROL__SWITCH_ON_EOI_MASK
 
- VGT_DMA_CONTROL__SWITCH_ON_EOI__SHIFT
 
- VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK
 
- VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT
 
- VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK
 
- VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT
 
- VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK
 
- VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT
 
- VGT_DMA_EVENT_INITIATOR__ADDRESS_HI_MASK
 
- VGT_DMA_EVENT_INITIATOR__ADDRESS_HI__SHIFT
 
- VGT_DMA_EVENT_INITIATOR__EVENT_TYPE_MASK
 
- VGT_DMA_EVENT_INITIATOR__EVENT_TYPE__SHIFT
 
- VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT_MASK
 
- VGT_DMA_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT
 
- VGT_DMA_INDEX_TYPE__ATC_MASK
 
- VGT_DMA_INDEX_TYPE__ATC__SHIFT
 
- VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK
 
- VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT
 
- VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK
 
- VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT
 
- VGT_DMA_INDEX_TYPE__MTYPE_MASK
 
- VGT_DMA_INDEX_TYPE__MTYPE__SHIFT
 
- VGT_DMA_INDEX_TYPE__NOT_EOP_MASK
 
- VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT
 
- VGT_DMA_INDEX_TYPE__PRIMGEN_EN_MASK
 
- VGT_DMA_INDEX_TYPE__PRIMGEN_EN__SHIFT
 
- VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK
 
- VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT
 
- VGT_DMA_INDEX_TYPE__REQ_PATH_MASK
 
- VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT
 
- VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK
 
- VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT
 
- VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK
 
- VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT
 
- VGT_DMA_MAX_SIZE__MAX_SIZE_MASK
 
- VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT
 
- VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK
 
- VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT
 
- VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK
 
- VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT
 
- VGT_DMA_PTR_UPDATE
 
- VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK
 
- VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT
 
- VGT_DMA_SIZE__NUM_INDICES_MASK
 
- VGT_DMA_SIZE__NUM_INDICES__SHIFT
 
- VGT_DMA_SWAP_16_BIT
 
- VGT_DMA_SWAP_32_BIT
 
- VGT_DMA_SWAP_MODE
 
- VGT_DMA_SWAP_NONE
 
- VGT_DMA_SWAP_WORD
 
- VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC_MASK
 
- VGT_DRAW_INITIATOR__GRBM_SKEW_NO_DEC__SHIFT
 
- VGT_DRAW_INITIATOR__MAJOR_MODE_MASK
 
- VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT
 
- VGT_DRAW_INITIATOR__NOT_EOP_MASK
 
- VGT_DRAW_INITIATOR__NOT_EOP__SHIFT
 
- VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK
 
- VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT
 
- VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK
 
- VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT
 
- VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK
 
- VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT
 
- VGT_DRAW_INITIATOR__UNROLLED_INST_MASK
 
- VGT_DRAW_INITIATOR__UNROLLED_INST__SHIFT
 
- VGT_DRAW_INITIATOR__USE_OPAQUE_MASK
 
- VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT
 
- VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK
 
- VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT
 
- VGT_DRAW_PAYLOAD_CNTL__EN_DRAW_VP_MASK
 
- VGT_DRAW_PAYLOAD_CNTL__EN_DRAW_VP__SHIFT
 
- VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK
 
- VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID__SHIFT
 
- VGT_DRAW_PAYLOAD_CNTL__EN_PRIM_PAYLOAD_MASK
 
- VGT_DRAW_PAYLOAD_CNTL__EN_PRIM_PAYLOAD__SHIFT
 
- VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK
 
- VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT
 
- VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK
 
- VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN__SHIFT
 
- VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN_MASK
 
- VGT_DRAW_PAYLOAD_CNTL__OBJPRIM_ID_EN__SHIFT
 
- VGT_DRV_DISPLAY_NOT_READY
 
- VGT_DRV_DISPLAY_READY
 
- VGT_ENHANCE__MISC_MASK
 
- VGT_ENHANCE__MISC__SHIFT
 
- VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK
 
- VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT
 
- VGT_ESGS_RING_SIZE
 
- VGT_ESGS_RING_SIZE_UMD__MEM_SIZE_MASK
 
- VGT_ESGS_RING_SIZE_UMD__MEM_SIZE__SHIFT
 
- VGT_ESGS_RING_SIZE__MEM_SIZE_MASK
 
- VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT
 
- VGT_ES_PER_GS
 
- VGT_ES_PER_GS__ES_PER_GS_MASK
 
- VGT_ES_PER_GS__ES_PER_GS__SHIFT
 
- VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK
 
- VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT
 
- VGT_EVENT_INITIATOR
 
- VGT_EVENT_INITIATOR__ADDRESS_HI_MASK
 
- VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT
 
- VGT_EVENT_INITIATOR__EVENT_TYPE_MASK
 
- VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT
 
- VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK
 
- VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT
 
- VGT_EVENT_TYPE
 
- VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK
 
- VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT
 
- VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK
 
- VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT
 
- VGT_FIFO_DEPTHS__RESERVED_0_MASK
 
- VGT_FIFO_DEPTHS__RESERVED_0__SHIFT
 
- VGT_FIFO_DEPTHS__RESERVED_1_MASK
 
- VGT_FIFO_DEPTHS__RESERVED_1__SHIFT
 
- VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK
 
- VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT
 
- VGT_FLUSH
 
- VGT_G2V_EXECLIST_CONTEXT_CREATE
 
- VGT_G2V_EXECLIST_CONTEXT_DESTROY
 
- VGT_G2V_MAX
 
- VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE
 
- VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY
 
- VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE
 
- VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY
 
- VGT_GROUP_CONV_SEL
 
- VGT_GROUP_DECR__DECR_MASK
 
- VGT_GROUP_DECR__DECR__SHIFT
 
- VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK
 
- VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT
 
- VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK
 
- VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT
 
- VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK
 
- VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT
 
- VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK
 
- VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT
 
- VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK
 
- VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT
 
- VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK
 
- VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT
 
- VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK
 
- VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT
 
- VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK
 
- VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT
 
- VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK
 
- VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT
 
- VGT_GROUP_VECT_0_CNTL__SHIFT_MASK
 
- VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT
 
- VGT_GROUP_VECT_0_CNTL__STRIDE_MASK
 
- VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT
 
- VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK
 
- VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT
 
- VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK
 
- VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT
 
- VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK
 
- VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT
 
- VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK
 
- VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT
 
- VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK
 
- VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT
 
- VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK
 
- VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT
 
- VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK
 
- VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT
 
- VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK
 
- VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT
 
- VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK
 
- VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT
 
- VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK
 
- VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT
 
- VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK
 
- VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT
 
- VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK
 
- VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT
 
- VGT_GROUP_VECT_1_CNTL__SHIFT_MASK
 
- VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT
 
- VGT_GROUP_VECT_1_CNTL__STRIDE_MASK
 
- VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT
 
- VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK
 
- VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT
 
- VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK
 
- VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT
 
- VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK
 
- VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT
 
- VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK
 
- VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT
 
- VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK
 
- VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT
 
- VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK
 
- VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT
 
- VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK
 
- VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT
 
- VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK
 
- VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT
 
- VGT_GRP_2D_COPY_RECT_V0
 
- VGT_GRP_2D_COPY_RECT_V1
 
- VGT_GRP_2D_COPY_RECT_V2
 
- VGT_GRP_2D_COPY_RECT_V3
 
- VGT_GRP_2D_FILL_RECT
 
- VGT_GRP_2D_LINE
 
- VGT_GRP_2D_RECT
 
- VGT_GRP_2D_TRI
 
- VGT_GRP_3D_LINE
 
- VGT_GRP_3D_LINE_ADJ
 
- VGT_GRP_3D_PATCH
 
- VGT_GRP_3D_POINT
 
- VGT_GRP_3D_QUAD
 
- VGT_GRP_3D_RECT
 
- VGT_GRP_3D_TRI
 
- VGT_GRP_3D_TRI_ADJ
 
- VGT_GRP_AUTO_PRIM
 
- VGT_GRP_FAN
 
- VGT_GRP_FIX_1_23_TO_FLOAT
 
- VGT_GRP_FLOAT_32
 
- VGT_GRP_INDEX_16
 
- VGT_GRP_INDEX_32
 
- VGT_GRP_LIST
 
- VGT_GRP_LOOP
 
- VGT_GRP_POLYGON
 
- VGT_GRP_PRIM_INDEX_LINE
 
- VGT_GRP_PRIM_INDEX_QUAD
 
- VGT_GRP_PRIM_INDEX_TRI
 
- VGT_GRP_PRIM_ORDER
 
- VGT_GRP_PRIM_TYPE
 
- VGT_GRP_SINT_16
 
- VGT_GRP_SINT_32
 
- VGT_GRP_STRIP
 
- VGT_GRP_UINT_16
 
- VGT_GRP_UINT_32
 
- VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK
 
- VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT
 
- VGT_GSVS_RING_OFFSET_1__OFFSET_MASK
 
- VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT
 
- VGT_GSVS_RING_OFFSET_2__OFFSET_MASK
 
- VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT
 
- VGT_GSVS_RING_OFFSET_3__OFFSET_MASK
 
- VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT
 
- VGT_GSVS_RING_SIZE
 
- VGT_GSVS_RING_SIZE_UMD__MEM_SIZE_MASK
 
- VGT_GSVS_RING_SIZE_UMD__MEM_SIZE__SHIFT
 
- VGT_GSVS_RING_SIZE__MEM_SIZE_MASK
 
- VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT
 
- VGT_GS_CUT_MODE
 
- VGT_GS_INSTANCE_CNT__CNT_MASK
 
- VGT_GS_INSTANCE_CNT__CNT__SHIFT
 
- VGT_GS_INSTANCE_CNT__ENABLE_MASK
 
- VGT_GS_INSTANCE_CNT__ENABLE__SHIFT
 
- VGT_GS_INSTANCE_CNT__EN_MAX_VERT_OUT_PER_GS_INSTANCE_MASK
 
- VGT_GS_INSTANCE_CNT__EN_MAX_VERT_OUT_PER_GS_INSTANCE__SHIFT
 
- VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP_MASK
 
- VGT_GS_MAX_PRIMS_PER_SUBGROUP__MAX_PRIMS_PER_SUBGROUP__SHIFT
 
- VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK
 
- VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT
 
- VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK
 
- VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT
 
- VGT_GS_MODE_TYPE
 
- VGT_GS_MODE__COMPUTE_MODE_MASK
 
- VGT_GS_MODE__COMPUTE_MODE__SHIFT
 
- VGT_GS_MODE__CUT_MODE_MASK
 
- VGT_GS_MODE__CUT_MODE__SHIFT
 
- VGT_GS_MODE__ELEMENT_INFO_EN_MASK
 
- VGT_GS_MODE__ELEMENT_INFO_EN__SHIFT
 
- VGT_GS_MODE__ES_PASSTHRU_MASK
 
- VGT_GS_MODE__ES_PASSTHRU__SHIFT
 
- VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK
 
- VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT
 
- VGT_GS_MODE__FAST_COMPUTE_MODE_MASK
 
- VGT_GS_MODE__FAST_COMPUTE_MODE__SHIFT
 
- VGT_GS_MODE__GS_C_PACK_EN_MASK
 
- VGT_GS_MODE__GS_C_PACK_EN__SHIFT
 
- VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK
 
- VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT
 
- VGT_GS_MODE__MODE_MASK
 
- VGT_GS_MODE__MODE__SHIFT
 
- VGT_GS_MODE__ONCHIP_MASK
 
- VGT_GS_MODE__ONCHIP__SHIFT
 
- VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK
 
- VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT
 
- VGT_GS_MODE__RESERVED_0_MASK
 
- VGT_GS_MODE__RESERVED_0__SHIFT
 
- VGT_GS_MODE__RESERVED_1_MASK
 
- VGT_GS_MODE__RESERVED_1__SHIFT
 
- VGT_GS_MODE__RESERVED_2_MASK
 
- VGT_GS_MODE__RESERVED_2__SHIFT
 
- VGT_GS_MODE__RESERVED_3_MASK
 
- VGT_GS_MODE__RESERVED_3__SHIFT
 
- VGT_GS_MODE__RESERVED_4_MASK
 
- VGT_GS_MODE__RESERVED_4__SHIFT
 
- VGT_GS_MODE__RESERVED_5_MASK
 
- VGT_GS_MODE__RESERVED_5__SHIFT
 
- VGT_GS_MODE__SUPPRESS_CUTS_MASK
 
- VGT_GS_MODE__SUPPRESS_CUTS__SHIFT
 
- VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK
 
- VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT
 
- VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP_MASK
 
- VGT_GS_ONCHIP_CNTL__GS_INST_PRIMS_IN_SUBGRP__SHIFT
 
- VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK
 
- VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT
 
- VGT_GS_OUTPRIM_TYPE
 
- VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK
 
- VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT
 
- VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK
 
- VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT
 
- VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK
 
- VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT
 
- VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK
 
- VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT
 
- VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK
 
- VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT
 
- VGT_GS_PER_ES
 
- VGT_GS_PER_ES__GS_PER_ES_MASK
 
- VGT_GS_PER_ES__GS_PER_ES__SHIFT
 
- VGT_GS_PER_VS
 
- VGT_GS_PER_VS__GS_PER_VS_MASK
 
- VGT_GS_PER_VS__GS_PER_VS__SHIFT
 
- VGT_GS_VERTEX_REUSE
 
- VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK
 
- VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT
 
- VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK
 
- VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT
 
- VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK
 
- VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT
 
- VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK
 
- VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT
 
- VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK
 
- VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT
 
- VGT_HOS_CNTL__TESS_MODE_MASK
 
- VGT_HOS_CNTL__TESS_MODE__SHIFT
 
- VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK
 
- VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT
 
- VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK
 
- VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT
 
- VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK
 
- VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT
 
- VGT_HS_OFFCHIP_PARAM
 
- VGT_HS_OFFCHIP_PARAM_UMD__OFFCHIP_BUFFERING_MASK
 
- VGT_HS_OFFCHIP_PARAM_UMD__OFFCHIP_BUFFERING__SHIFT
 
- VGT_HS_OFFCHIP_PARAM_UMD__OFFCHIP_GRANULARITY_MASK
 
- VGT_HS_OFFCHIP_PARAM_UMD__OFFCHIP_GRANULARITY__SHIFT
 
- VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK
 
- VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT
 
- VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK
 
- VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT
 
- VGT_IMMED_DATA__DATA_MASK
 
- VGT_IMMED_DATA__DATA__SHIFT
 
- VGT_INDEX_16
 
- VGT_INDEX_32
 
- VGT_INDEX_8
 
- VGT_INDEX_TYPE
 
- VGT_INDEX_TYPE_MODE
 
- VGT_INDEX_TYPE__INDEX_TYPE_MASK
 
- VGT_INDEX_TYPE__INDEX_TYPE__SHIFT
 
- VGT_INDEX_TYPE__PRIMGEN_EN_MASK
 
- VGT_INDEX_TYPE__PRIMGEN_EN__SHIFT
 
- VGT_INDX_OFFSET__INDX_OFFSET_MASK
 
- VGT_INDX_OFFSET__INDX_OFFSET__SHIFT
 
- VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK
 
- VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT
 
- VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK
 
- VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT
 
- VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK
 
- VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT
 
- VGT_LAST_COPY_STATE__DST_STATE_ID_MASK
 
- VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT
 
- VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK
 
- VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT
 
- VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK
 
- VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT
 
- VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK
 
- VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT
 
- VGT_LS_HS_CONFIG__NUM_PATCHES_MASK
 
- VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT
 
- VGT_MAGIC
 
- VGT_MAX_VTX_INDX__MAX_INDX_MASK
 
- VGT_MAX_VTX_INDX__MAX_INDX__SHIFT
 
- VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK
 
- VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT
 
- VGT_MIN_VTX_INDX__MIN_INDX_MASK
 
- VGT_MIN_VTX_INDX__MIN_INDX__SHIFT
 
- VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK
 
- VGT_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT
 
- VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK
 
- VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT
 
- VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK
 
- VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT
 
- VGT_NUM_INDICES
 
- VGT_NUM_INDICES__NUM_INDICES_MASK
 
- VGT_NUM_INDICES__NUM_INDICES__SHIFT
 
- VGT_NUM_INSTANCES
 
- VGT_NUM_INSTANCES__NUM_INSTANCES_MASK
 
- VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT
 
- VGT_OFFCHIP_LDS_BASE
 
- VGT_OUTPATH_GS_BLOCK
 
- VGT_OUTPATH_HS_BLOCK
 
- VGT_OUTPATH_PASSTHRU
 
- VGT_OUTPATH_PRIM_GEN
 
- VGT_OUTPATH_SELECT
 
- VGT_OUTPATH_TESS_EN
 
- VGT_OUTPATH_TE_GS_BLOCK
 
- VGT_OUTPATH_TE_OUTPUT
 
- VGT_OUTPATH_TE_PRIM_GEN
 
- VGT_OUTPATH_VTX_REUSE
 
- VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK
 
- VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT
 
- VGT_OUT_2D_RECT
 
- VGT_OUT_DEALLOC_CNTL
 
- VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK
 
- VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT
 
- VGT_OUT_LINE
 
- VGT_OUT_LINE_ADJ
 
- VGT_OUT_PATCH
 
- VGT_OUT_POINT
 
- VGT_OUT_PRIM_TYPE
 
- VGT_OUT_RECT_V0
 
- VGT_OUT_RECT_V1
 
- VGT_OUT_RECT_V2
 
- VGT_OUT_RECT_V3
 
- VGT_OUT_RESERVED
 
- VGT_OUT_TRI
 
- VGT_OUT_TRI_ADJ
 
- VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK
 
- VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT
 
- VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK
 
- VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT
 
- VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK
 
- VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT
 
- VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK
 
- VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT
 
- VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK
 
- VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT
 
- VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK
 
- VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT
 
- VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK
 
- VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT
 
- VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK
 
- VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT
 
- VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK
 
- VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT
 
- VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK
 
- VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT
 
- VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK
 
- VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT
 
- VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK
 
- VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT
 
- VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK
 
- VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT
 
- VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK
 
- VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT
 
- VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK
 
- VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT
 
- VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK
 
- VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT
 
- VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK
 
- VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT
 
- VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK
 
- VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT
 
- VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK
 
- VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT
 
- VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK
 
- VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT
 
- VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK
 
- VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT
 
- VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK
 
- VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT
 
- VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK
 
- VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT
 
- VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK
 
- VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT
 
- VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK
 
- VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT
 
- VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK
 
- VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT
 
- VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK
 
- VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT
 
- VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK
 
- VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT
 
- VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK
 
- VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT
 
- VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK
 
- VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT
 
- VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK
 
- VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT
 
- VGT_PERFCOUNT_SELECT
 
- VGT_POLICY_BYPASS
 
- VGT_POLICY_LRU
 
- VGT_POLICY_RESERVED
 
- VGT_POLICY_STREAM
 
- VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK
 
- VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT
 
- VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK
 
- VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT
 
- VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK
 
- VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT
 
- VGT_PRIMITIVEID_RESET__VALUE_MASK
 
- VGT_PRIMITIVEID_RESET__VALUE__SHIFT
 
- VGT_PRIMITIVE_TYPE
 
- VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK
 
- VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT
 
- VGT_PVINFO_PAGE
 
- VGT_PVINFO_SIZE
 
- VGT_RDREQ_POLICY
 
- VGT_RESET_DEBUG__GS_DISABLE_MASK
 
- VGT_RESET_DEBUG__GS_DISABLE__SHIFT
 
- VGT_RESET_DEBUG__TESS_DISABLE_MASK
 
- VGT_RESET_DEBUG__TESS_DISABLE__SHIFT
 
- VGT_RESET_DEBUG__WD_DISABLE_MASK
 
- VGT_RESET_DEBUG__WD_DISABLE__SHIFT
 
- VGT_REUSE_OFF__REUSE_OFF_MASK
 
- VGT_REUSE_OFF__REUSE_OFF__SHIFT
 
- VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK
 
- VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT
 
- VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK
 
- VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT
 
- VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK
 
- VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT
 
- VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK
 
- VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT
 
- VGT_SHADER_STAGES_EN__ES_EN_MASK
 
- VGT_SHADER_STAGES_EN__ES_EN__SHIFT
 
- VGT_SHADER_STAGES_EN__GS_EN_MASK
 
- VGT_SHADER_STAGES_EN__GS_EN__SHIFT
 
- VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK
 
- VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT
 
- VGT_SHADER_STAGES_EN__GS_W32_EN_MASK
 
- VGT_SHADER_STAGES_EN__GS_W32_EN__SHIFT
 
- VGT_SHADER_STAGES_EN__HS_EN_MASK
 
- VGT_SHADER_STAGES_EN__HS_EN__SHIFT
 
- VGT_SHADER_STAGES_EN__HS_W32_EN_MASK
 
- VGT_SHADER_STAGES_EN__HS_W32_EN__SHIFT
 
- VGT_SHADER_STAGES_EN__LS_EN_MASK
 
- VGT_SHADER_STAGES_EN__LS_EN__SHIFT
 
- VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE_MASK
 
- VGT_SHADER_STAGES_EN__MAX_PRIMGRP_IN_WAVE__SHIFT
 
- VGT_SHADER_STAGES_EN__NGG_WAVE_ID_EN_MASK
 
- VGT_SHADER_STAGES_EN__NGG_WAVE_ID_EN__SHIFT
 
- VGT_SHADER_STAGES_EN__ORDERED_ID_MODE_MASK
 
- VGT_SHADER_STAGES_EN__ORDERED_ID_MODE__SHIFT
 
- VGT_SHADER_STAGES_EN__PRIMGEN_EN_MASK
 
- VGT_SHADER_STAGES_EN__PRIMGEN_EN__SHIFT
 
- VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_EN_MASK
 
- VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_EN__SHIFT
 
- VGT_SHADER_STAGES_EN__VS_EN_MASK
 
- VGT_SHADER_STAGES_EN__VS_EN__SHIFT
 
- VGT_SHADER_STAGES_EN__VS_W32_EN_MASK
 
- VGT_SHADER_STAGES_EN__VS_W32_EN__SHIFT
 
- VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK
 
- VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT
 
- VGT_SPRSTRIDE
 
- VGT_STAGES_ES_EN
 
- VGT_STAGES_GS_EN
 
- VGT_STAGES_HS_EN
 
- VGT_STAGES_LS_EN
 
- VGT_STAGES_VS_EN
 
- VGT_STREAMOUT_RESET
 
- VGT_STREAMOUT_SYNC
 
- VGT_STRMOUT_BASE_OFFSET_0
 
- VGT_STRMOUT_BASE_OFFSET_1
 
- VGT_STRMOUT_BASE_OFFSET_2
 
- VGT_STRMOUT_BASE_OFFSET_3
 
- VGT_STRMOUT_BASE_OFFSET_HI_0
 
- VGT_STRMOUT_BASE_OFFSET_HI_1
 
- VGT_STRMOUT_BASE_OFFSET_HI_2
 
- VGT_STRMOUT_BASE_OFFSET_HI_3
 
- VGT_STRMOUT_BUFFER_BASE_0
 
- VGT_STRMOUT_BUFFER_BASE_1
 
- VGT_STRMOUT_BUFFER_BASE_2
 
- VGT_STRMOUT_BUFFER_BASE_3
 
- VGT_STRMOUT_BUFFER_CONFIG
 
- VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK
 
- VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT
 
- VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK
 
- VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT
 
- VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK
 
- VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT
 
- VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK
 
- VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT
 
- VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK
 
- VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT
 
- VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK
 
- VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT
 
- VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK
 
- VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT
 
- VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK
 
- VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT
 
- VGT_STRMOUT_BUFFER_OFFSET_0
 
- VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK
 
- VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT
 
- VGT_STRMOUT_BUFFER_OFFSET_1
 
- VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK
 
- VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT
 
- VGT_STRMOUT_BUFFER_OFFSET_2
 
- VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK
 
- VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT
 
- VGT_STRMOUT_BUFFER_OFFSET_3
 
- VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK
 
- VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT
 
- VGT_STRMOUT_BUFFER_SIZE_0
 
- VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK
 
- VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT
 
- VGT_STRMOUT_BUFFER_SIZE_1
 
- VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK
 
- VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT
 
- VGT_STRMOUT_BUFFER_SIZE_2
 
- VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK
 
- VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT
 
- VGT_STRMOUT_BUFFER_SIZE_3
 
- VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK
 
- VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT
 
- VGT_STRMOUT_CONFIG
 
- VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT_MASK
 
- VGT_STRMOUT_CONFIG__EN_PRIMS_NEEDED_CNT__SHIFT
 
- VGT_STRMOUT_CONFIG__RAST_STREAM_MASK
 
- VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK
 
- VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT
 
- VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT
 
- VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK
 
- VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT
 
- VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK
 
- VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT
 
- VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK
 
- VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT
 
- VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK
 
- VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT
 
- VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK
 
- VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT
 
- VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK
 
- VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT
 
- VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK
 
- VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT
 
- VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK
 
- VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT
 
- VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK
 
- VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT
 
- VGT_STRMOUT_DELAY__SKIP_DELAY_MASK
 
- VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT
 
- VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK
 
- VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT
 
- VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK
 
- VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT
 
- VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK
 
- VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT
 
- VGT_STRMOUT_EN
 
- VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK
 
- VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT
 
- VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK
 
- VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT
 
- VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK
 
- VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT
 
- VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK
 
- VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT
 
- VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK
 
- VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT
 
- VGT_SYS_CONFIG__DUAL_CORE_EN_MASK
 
- VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT
 
- VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK
 
- VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT
 
- VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK
 
- VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT
 
- VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK
 
- VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT
 
- VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK
 
- VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT
 
- VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK
 
- VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT
 
- VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK
 
- VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT
 
- VGT_TESS_PARTITION
 
- VGT_TESS_TOPOLOGY
 
- VGT_TESS_TYPE
 
- VGT_TE_PRIM_INDEX_LINE
 
- VGT_TE_PRIM_INDEX_QUAD
 
- VGT_TE_PRIM_INDEX_TRI
 
- VGT_TE_QUAD
 
- VGT_TF_MEMORY_BASE
 
- VGT_TF_MEMORY_BASE_HI_UMD__BASE_HI_MASK
 
- VGT_TF_MEMORY_BASE_HI_UMD__BASE_HI__SHIFT
 
- VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK
 
- VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT
 
- VGT_TF_MEMORY_BASE_UMD__BASE_MASK
 
- VGT_TF_MEMORY_BASE_UMD__BASE__SHIFT
 
- VGT_TF_MEMORY_BASE__BASE_MASK
 
- VGT_TF_MEMORY_BASE__BASE__SHIFT
 
- VGT_TF_PARAM__DEPRECATED_MASK
 
- VGT_TF_PARAM__DEPRECATED__SHIFT
 
- VGT_TF_PARAM__DETECT_ONE_MASK
 
- VGT_TF_PARAM__DETECT_ONE__SHIFT
 
- VGT_TF_PARAM__DETECT_ZERO_MASK
 
- VGT_TF_PARAM__DETECT_ZERO__SHIFT
 
- VGT_TF_PARAM__DISABLE_DONUTS_MASK
 
- VGT_TF_PARAM__DISABLE_DONUTS__SHIFT
 
- VGT_TF_PARAM__DISTRIBUTION_MODE_MASK
 
- VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT
 
- VGT_TF_PARAM__MTYPE_MASK
 
- VGT_TF_PARAM__MTYPE__SHIFT
 
- VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK
 
- VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT
 
- VGT_TF_PARAM__PARTITIONING_MASK
 
- VGT_TF_PARAM__PARTITIONING__SHIFT
 
- VGT_TF_PARAM__RDREQ_POLICY_MASK
 
- VGT_TF_PARAM__RDREQ_POLICY__SHIFT
 
- VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK
 
- VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT
 
- VGT_TF_PARAM__TOPOLOGY_MASK
 
- VGT_TF_PARAM__TOPOLOGY__SHIFT
 
- VGT_TF_PARAM__TYPE_MASK
 
- VGT_TF_PARAM__TYPE__SHIFT
 
- VGT_TF_RING_SIZE
 
- VGT_TF_RING_SIZE_UMD__SIZE_MASK
 
- VGT_TF_RING_SIZE_UMD__SIZE__SHIFT
 
- VGT_TF_RING_SIZE__SIZE_MASK
 
- VGT_TF_RING_SIZE__SIZE__SHIFT
 
- VGT_VERSION_MAJOR
 
- VGT_VERSION_MINOR
 
- VGT_VERTEX_REUSE_BLOCK_CNTL
 
- VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK
 
- VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT
 
- VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK
 
- VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT
 
- VGT_VTX_CNT_EN__VTX_CNT_EN_MASK
 
- VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT
 
- VGT_VTX_VECT_EJECT_REG
 
- VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK
 
- VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT
 
- VHCI_HC_PORTS
 
- VHCI_MINOR
 
- VHCI_NR_HCS
 
- VHCI_PORTS
 
- VHCI_STATE_PATH
 
- VHMAGIC
 
- VHOST_ACCESS_RO
 
- VHOST_ACCESS_RW
 
- VHOST_ACCESS_WO
 
- VHOST_ADDR_AVAIL
 
- VHOST_ADDR_DESC
 
- VHOST_ADDR_USED
 
- VHOST_BACKEND_F_IOTLB_MSG_V2
 
- VHOST_DMA_CLEAR_LEN
 
- VHOST_DMA_DONE_LEN
 
- VHOST_DMA_FAILED_LEN
 
- VHOST_DMA_IN_PROGRESS
 
- VHOST_DMA_IS_DONE
 
- VHOST_FEATURES
 
- VHOST_F_LOG_ALL
 
- VHOST_GET_BACKEND_FEATURES
 
- VHOST_GET_FEATURES
 
- VHOST_GET_VRING_BASE
 
- VHOST_GET_VRING_BUSYLOOP_TIMEOUT
 
- VHOST_GET_VRING_ENDIAN
 
- VHOST_GOODCOPY_LEN
 
- VHOST_IOTLB_ACCESS_FAIL
 
- VHOST_IOTLB_INVALIDATE
 
- VHOST_IOTLB_MISS
 
- VHOST_IOTLB_MSG
 
- VHOST_IOTLB_MSG_V2
 
- VHOST_IOTLB_UPDATE
 
- VHOST_MAX_PEND
 
- VHOST_MEMORY_F_LOG
 
- VHOST_NET_BACKEND_FEATURES
 
- VHOST_NET_BATCH
 
- VHOST_NET_FEATURES
 
- VHOST_NET_F_VIRTIO_NET_HDR
 
- VHOST_NET_MINOR
 
- VHOST_NET_PKT_WEIGHT
 
- VHOST_NET_RX_PAD
 
- VHOST_NET_SET_BACKEND
 
- VHOST_NET_VQ_MAX
 
- VHOST_NET_VQ_RX
 
- VHOST_NET_VQ_TX
 
- VHOST_NET_WEIGHT
 
- VHOST_NUM_ADDRS
 
- VHOST_PAGE_SIZE
 
- VHOST_RESET_OWNER
 
- VHOST_SCSI_ABI_VERSION
 
- VHOST_SCSI_CLEAR_ENDPOINT
 
- VHOST_SCSI_DEFAULT_TAGS
 
- VHOST_SCSI_FEATURES
 
- VHOST_SCSI_GET_ABI_VERSION
 
- VHOST_SCSI_GET_EVENTS_MISSED
 
- VHOST_SCSI_MAX_CDB_SIZE
 
- VHOST_SCSI_MAX_EVENT
 
- VHOST_SCSI_MAX_TARGET
 
- VHOST_SCSI_MAX_VQ
 
- VHOST_SCSI_NAMELEN
 
- VHOST_SCSI_PREALLOC_PROT_SGLS
 
- VHOST_SCSI_PREALLOC_SGLS
 
- VHOST_SCSI_PREALLOC_UPAGES
 
- VHOST_SCSI_SET_ENDPOINT
 
- VHOST_SCSI_SET_EVENTS_MISSED
 
- VHOST_SCSI_VERSION
 
- VHOST_SCSI_VQ_CTL
 
- VHOST_SCSI_VQ_EVT
 
- VHOST_SCSI_VQ_IO
 
- VHOST_SCSI_WEIGHT
 
- VHOST_SET_BACKEND_FEATURES
 
- VHOST_SET_FEATURES
 
- VHOST_SET_LOG_BASE
 
- VHOST_SET_LOG_FD
 
- VHOST_SET_MEM_TABLE
 
- VHOST_SET_OWNER
 
- VHOST_SET_VRING_ADDR
 
- VHOST_SET_VRING_BASE
 
- VHOST_SET_VRING_BUSYLOOP_TIMEOUT
 
- VHOST_SET_VRING_CALL
 
- VHOST_SET_VRING_ENDIAN
 
- VHOST_SET_VRING_ERR
 
- VHOST_SET_VRING_KICK
 
- VHOST_SET_VRING_NUM
 
- VHOST_TEST_PKT_WEIGHT
 
- VHOST_TEST_RUN
 
- VHOST_TEST_VQ
 
- VHOST_TEST_VQ_MAX
 
- VHOST_TEST_WEIGHT
 
- VHOST_USER_FLAG_NEED_REPLY
 
- VHOST_USER_FLAG_REPLY
 
- VHOST_USER_F_PROTOCOL_FEATURES
 
- VHOST_USER_GET_CONFIG
 
- VHOST_USER_GET_FEATURES
 
- VHOST_USER_GET_PROTOCOL_FEATURES
 
- VHOST_USER_GET_QUEUE_NUM
 
- VHOST_USER_GET_VRING_BASE
 
- VHOST_USER_IOTLB_MSG
 
- VHOST_USER_NET_SEND_MTU
 
- VHOST_USER_PROTOCOL_F_CONFIG
 
- VHOST_USER_PROTOCOL_F_REPLY_ACK
 
- VHOST_USER_PROTOCOL_F_SLAVE_REQ
 
- VHOST_USER_RESET_OWNER
 
- VHOST_USER_SEND_RARP
 
- VHOST_USER_SET_CONFIG
 
- VHOST_USER_SET_FEATURES
 
- VHOST_USER_SET_LOG_BASE
 
- VHOST_USER_SET_LOG_FD
 
- VHOST_USER_SET_MEM_TABLE
 
- VHOST_USER_SET_OWNER
 
- VHOST_USER_SET_PROTOCOL_FEATURES
 
- VHOST_USER_SET_SLAVE_REQ_FD
 
- VHOST_USER_SET_VRING_ADDR
 
- VHOST_USER_SET_VRING_BASE
 
- VHOST_USER_SET_VRING_CALL
 
- VHOST_USER_SET_VRING_ENABLE
 
- VHOST_USER_SET_VRING_ENDIAN
 
- VHOST_USER_SET_VRING_ERR
 
- VHOST_USER_SET_VRING_KICK
 
- VHOST_USER_SET_VRING_NUM
 
- VHOST_USER_SLAVE_CONFIG_CHANGE_MSG
 
- VHOST_USER_SLAVE_IOTLB_MSG
 
- VHOST_USER_SLAVE_VRING_HOST_NOTIFIER_MSG
 
- VHOST_USER_SUPPORTED_F
 
- VHOST_USER_SUPPORTED_PROTOCOL_F
 
- VHOST_USER_VERSION
 
- VHOST_USER_VRING_INDEX_MASK
 
- VHOST_USER_VRING_POLL_MASK
 
- VHOST_VIRTIO
 
- VHOST_VRING_BIG_ENDIAN
 
- VHOST_VRING_F_LOG
 
- VHOST_VRING_LITTLE_ENDIAN
 
- VHOST_VSOCK_DEFAULT_HOST_CID
 
- VHOST_VSOCK_FEATURES
 
- VHOST_VSOCK_MINOR
 
- VHOST_VSOCK_PKT_WEIGHT
 
- VHOST_VSOCK_SET_GUEST_CID
 
- VHOST_VSOCK_SET_RUNNING
 
- VHOST_VSOCK_WEIGHT
 
- VHOST_WORK_QUEUED
 
- VHPT_ENABLE_BIT
 
- VHREF_HREF_SRC_STD
 
- VHREF_HSYNC_SEL_HS
 
- VHREF_INT_DET
 
- VHREF_STD_DET_AUTO
 
- VHREF_STD_DET_MASK
 
- VHREF_STD_DET_NTSC
 
- VHREF_STD_DET_OFF
 
- VHREF_STD_DET_PAL
 
- VHREF_STD_DET_SHIFT
 
- VHREF_VREF_SRC_STD
 
- VHREF_VSYNC_AUTO
 
- VHREF_VSYNC_EVEN
 
- VHREF_VSYNC_FDW
 
- VHREF_VSYNC_MASK
 
- VHREF_VSYNC_ODD
 
- VHREF_VSYNC_SHIFT
 
- VHT_1SSMCS0_1SSMCS9
 
- VHT_2SSMCS0_2SSMCS9
 
- VHT_3SSMCS0_3SSMCS9
 
- VHT_4SSMCS0_4SSMCS9
 
- VHT_AGG_SIZE_1024K
 
- VHT_AGG_SIZE_128K
 
- VHT_AGG_SIZE_256K
 
- VHT_AGG_SIZE_512K
 
- VHT_BW_80_160_80P80
 
- VHT_CAP_ASSOCIATION
 
- VHT_CAP_TX_OPERATION
 
- VHT_CAP_UAP_ONLY
 
- VHT_CFG_2GHZ
 
- VHT_CFG_5GHZ
 
- VHT_DATA_SC
 
- VHT_DATA_SC_20_LOWER_OF_80MHZ
 
- VHT_DATA_SC_20_LOWEST_OF_80MHZ
 
- VHT_DATA_SC_20_RECV1
 
- VHT_DATA_SC_20_RECV2
 
- VHT_DATA_SC_20_RECV3
 
- VHT_DATA_SC_20_RECV4
 
- VHT_DATA_SC_20_UPPERST_OF_80MHZ
 
- VHT_DATA_SC_20_UPPER_OF_80MHZ
 
- VHT_DATA_SC_40_LOWER_OF_80MHZ
 
- VHT_DATA_SC_40_UPPER_OF_80MHZ
 
- VHT_DATA_SC_DONOT_CARE
 
- VHT_GROUP
 
- VHT_GROUP_IDX
 
- VHT_GROUP_SHIFT
 
- VHT_LDPC_EN
 
- VHT_MUMIMO_GROUPS_DATA_LEN
 
- VHT_STBC_EN
 
- VHUB_CTRL_AUTO_REMOTE_WAKEUP
 
- VHUB_CTRL_CLK_STOP_SUSPEND
 
- VHUB_CTRL_DN_PWN
 
- VHUB_CTRL_DP_PWN
 
- VHUB_CTRL_FULL_SPEED_ONLY
 
- VHUB_CTRL_ISO_RSP_CTRL
 
- VHUB_CTRL_LONG_DESC
 
- VHUB_CTRL_LOOP_T_RESULT
 
- VHUB_CTRL_LOOP_T_STS
 
- VHUB_CTRL_MANUAL_REMOTE_WAKEUP
 
- VHUB_CTRL_PHY_BIST_CTRL
 
- VHUB_CTRL_PHY_BIST_RESULT
 
- VHUB_CTRL_PHY_CLK
 
- VHUB_CTRL_PHY_LOOP_TEST
 
- VHUB_CTRL_PHY_RESET_DIS
 
- VHUB_CTRL_SET_TEST_MODE
 
- VHUB_CTRL_SPLIT_IN
 
- VHUB_CTRL_UPSTREAM_CONNECT
 
- VHUB_DEV_EN_ADDR_MASK
 
- VHUB_DEV_EN_ENABLE_PORT
 
- VHUB_DEV_EN_EP0_IN_ACK_IRQEN
 
- VHUB_DEV_EN_EP0_NAK_IRQEN
 
- VHUB_DEV_EN_EP0_OUT_ACK_IRQEN
 
- VHUB_DEV_EN_EP0_OUT_NAK_IRQEN
 
- VHUB_DEV_EN_EP0_SETUP_IRQEN
 
- VHUB_DEV_EN_SET_ADDR
 
- VHUB_DEV_EN_SPEED_SEL_HIGH
 
- VHUB_DEV_EP0_CTRL_STALL
 
- VHUB_DEV_EP0_RX_BUFF_RDY
 
- VHUB_DEV_EP0_RX_LEN
 
- VHUB_DEV_EP0_SET_TX_LEN
 
- VHUB_DEV_EP0_TX_BUFF_RDY
 
- VHUB_DSC1_IN_INTERRUPT
 
- VHUB_DSC1_IN_LEN
 
- VHUB_DSC1_IN_SET_LEN
 
- VHUB_DSC1_IN_SPID_DATA0
 
- VHUB_DSC1_IN_SPID_DATA1
 
- VHUB_DSC1_IN_SPID_DATA2
 
- VHUB_DSC1_IN_SPID_MDATA
 
- VHUB_EP0_CTRL_STALL
 
- VHUB_EP0_RX_BUFF_RDY
 
- VHUB_EP0_RX_LEN
 
- VHUB_EP0_SET_TX_LEN
 
- VHUB_EP0_TX_BUFF_RDY
 
- VHUB_EP1_CTRL_ENABLE
 
- VHUB_EP1_CTRL_RESET_TOGGLE
 
- VHUB_EP1_CTRL_STALL
 
- VHUB_EP_CFG_AUTO_DATA_DISABLE
 
- VHUB_EP_CFG_DIR_OUT
 
- VHUB_EP_CFG_ENABLE
 
- VHUB_EP_CFG_SET_DEV
 
- VHUB_EP_CFG_SET_EP_NUM
 
- VHUB_EP_CFG_SET_MAX_PKT
 
- VHUB_EP_CFG_SET_TYPE
 
- VHUB_EP_CFG_STALL_CTRL
 
- VHUB_EP_DMA_CTRL_RESET
 
- VHUB_EP_DMA_DESC_MODE
 
- VHUB_EP_DMA_IN_LONG_MODE
 
- VHUB_EP_DMA_OUT_CONTIG_MODE
 
- VHUB_EP_DMA_PROC_STATUS
 
- VHUB_EP_DMA_RPTR
 
- VHUB_EP_DMA_SET_CPU_WPTR
 
- VHUB_EP_DMA_SET_RPTR
 
- VHUB_EP_DMA_SET_TX_SIZE
 
- VHUB_EP_DMA_SINGLE_KICK
 
- VHUB_EP_DMA_SINGLE_STAGE
 
- VHUB_EP_DMA_TX_SIZE
 
- VHUB_EP_IRQ
 
- VHUB_EP_IRQ_ALL
 
- VHUB_EP_TOGGLE_SET_EPNUM
 
- VHUB_EP_TOGGLE_VALUE
 
- VHUB_IRQ_ACK_ALL
 
- VHUB_IRQ_BUS_RESET
 
- VHUB_IRQ_BUS_RESUME
 
- VHUB_IRQ_BUS_SUSPEND
 
- VHUB_IRQ_DEVICE1
 
- VHUB_IRQ_DEVICE2
 
- VHUB_IRQ_DEVICE3
 
- VHUB_IRQ_DEVICE4
 
- VHUB_IRQ_DEVICE5
 
- VHUB_IRQ_EP_POOL_ACK_STALL
 
- VHUB_IRQ_EP_POOL_NAK
 
- VHUB_IRQ_HUB_EP0_IN_ACK_STALL
 
- VHUB_IRQ_HUB_EP0_IN_DATA_NAK
 
- VHUB_IRQ_HUB_EP0_OUT_ACK_STALL
 
- VHUB_IRQ_HUB_EP0_OUT_NAK
 
- VHUB_IRQ_HUB_EP0_SETUP
 
- VHUB_IRQ_HUB_EP1_IN_DATA_ACK
 
- VHUB_IRQ_USB_CMD_DEADLOCK
 
- VHUB_SW_RESET_ALL
 
- VHUB_SW_RESET_DEVICE1
 
- VHUB_SW_RESET_DEVICE2
 
- VHUB_SW_RESET_DEVICE3
 
- VHUB_SW_RESET_DEVICE4
 
- VHUB_SW_RESET_DEVICE5
 
- VHUB_SW_RESET_DMA_CONTROLLER
 
- VHUB_SW_RESET_EP_POOL
 
- VHUB_SW_RESET_ROOT_HUB
 
- VHUB_USBSTS_HISPEED
 
- VHUV_DEV_IRQ_EP0_IN_ACK_STALL
 
- VHUV_DEV_IRQ_EP0_IN_DATA_NACK
 
- VHUV_DEV_IRQ_EP0_OUT_ACK_STALL
 
- VHUV_DEV_IRQ_EP0_OUT_DATA_NACK
 
- VHUV_DEV_IRQ_EP0_SETUP
 
- VHYX
 
- VHYX_HSIZE_SET
 
- VHYX_VSIZE_SET
 
- VHYX_XOFF_SET
 
- VHYX_YOFF_SET
 
- VI0_CLKENB_B_MARK
 
- VI0_CLKENB_MARK
 
- VI0_CLK_B_MARK
 
- VI0_CLK_MARK
 
- VI0_D0_B0_C0_MARK
 
- VI0_D10_G2_Y2_MARK
 
- VI0_D11_G3_Y3_MARK
 
- VI0_D12_G4_Y4_MARK
 
- VI0_D13_G5_Y5_MARK
 
- VI0_D14_G6_Y6_MARK
 
- VI0_D15_G7_Y7_MARK
 
- VI0_D16_R0_MARK
 
- VI0_D17_R1_MARK
 
- VI0_D18_R2_MARK
 
- VI0_D19_R3_MARK
 
- VI0_D1_B1_C1_MARK
 
- VI0_D20_R4_MARK
 
- VI0_D21_R5_MARK
 
- VI0_D22_R6_MARK
 
- VI0_D23_R7_MARK
 
- VI0_D2_B2_C2_MARK
 
- VI0_D3_B3_C3_MARK
 
- VI0_D4_B4_C4_MARK
 
- VI0_D5_B5_C5_MARK
 
- VI0_D6_B6_C6_MARK
 
- VI0_D7_B7_C7_MARK
 
- VI0_D8_G0_Y0_MARK
 
- VI0_D9_G1_Y1_MARK
 
- VI0_DATA0_B_VI0_B0_B_MARK
 
- VI0_DATA0_VI0_B0_B_MARK
 
- VI0_DATA0_VI0_B0_MARK
 
- VI0_DATA1_B_VI0_B1_B_MARK
 
- VI0_DATA1_VI0_B1_B_MARK
 
- VI0_DATA1_VI0_B1_MARK
 
- VI0_DATA2_VI0_B2_B_MARK
 
- VI0_DATA2_VI0_B2_MARK
 
- VI0_DATA3_VI0_B3_B_MARK
 
- VI0_DATA3_VI0_B3_MARK
 
- VI0_DATA4_VI0_B4_B_MARK
 
- VI0_DATA4_VI0_B4_MARK
 
- VI0_DATA5_VI0_B5_B_MARK
 
- VI0_DATA5_VI0_B5_MARK
 
- VI0_DATA6_VI0_B6_B_MARK
 
- VI0_DATA6_VI0_B6_MARK
 
- VI0_DATA6_VI0_G0_MARK
 
- VI0_DATA7_VI0_B7_B_MARK
 
- VI0_DATA7_VI0_B7_MARK
 
- VI0_DATA7_VI0_G1_MARK
 
- VI0_FIELD_B_MARK
 
- VI0_FIELD_MARK
 
- VI0_G0_B_MARK
 
- VI0_G0_MARK
 
- VI0_G1_B_MARK
 
- VI0_G1_MARK
 
- VI0_G2_B_MARK
 
- VI0_G2_MARK
 
- VI0_G3_B_MARK
 
- VI0_G3_MARK
 
- VI0_G4_B_MARK
 
- VI0_G4_MARK
 
- VI0_G5_B_MARK
 
- VI0_G5_MARK
 
- VI0_G6_B_MARK
 
- VI0_G6_MARK
 
- VI0_G7_B_MARK
 
- VI0_G7_MARK
 
- VI0_HSYNC_MARK
 
- VI0_HSYNC_N_B_MARK
 
- VI0_HSYNC_N_MARK
 
- VI0_R0_A_MARK
 
- VI0_R0_B_MARK
 
- VI0_R0_C_MARK
 
- VI0_R0_D_MARK
 
- VI0_R0_MARK
 
- VI0_R1_A_MARK
 
- VI0_R1_B_MARK
 
- VI0_R1_C_MARK
 
- VI0_R1_D_MARK
 
- VI0_R1_MARK
 
- VI0_R2_A_MARK
 
- VI0_R2_B_MARK
 
- VI0_R2_C_MARK
 
- VI0_R2_D_MARK
 
- VI0_R2_MARK
 
- VI0_R3_A_MARK
 
- VI0_R3_B_MARK
 
- VI0_R3_C_MARK
 
- VI0_R3_D_MARK
 
- VI0_R3_MARK
 
- VI0_R4_A_MARK
 
- VI0_R4_B_MARK
 
- VI0_R4_C_MARK
 
- VI0_R4_D_MARK
 
- VI0_R4_MARK
 
- VI0_R5_A_MARK
 
- VI0_R5_B_MARK
 
- VI0_R5_C_MARK
 
- VI0_R5_D_MARK
 
- VI0_R5_MARK
 
- VI0_R6_B_MARK
 
- VI0_R6_MARK
 
- VI0_R7_B_MARK
 
- VI0_R7_MARK
 
- VI0_VSYNC_MARK
 
- VI0_VSYNC_N_B_MARK
 
- VI0_VSYNC_N_MARK
 
- VI1_0_A_MARK
 
- VI1_0_B_MARK
 
- VI1_1_A_MARK
 
- VI1_1_B_MARK
 
- VI1_2_A_MARK
 
- VI1_2_B_MARK
 
- VI1_3_A_MARK
 
- VI1_3_B_MARK
 
- VI1_4_A_MARK
 
- VI1_4_B_MARK
 
- VI1_5_A_MARK
 
- VI1_5_B_MARK
 
- VI1_6_A_MARK
 
- VI1_6_B_MARK
 
- VI1_7_A_MARK
 
- VI1_7_B_MARK
 
- VI1_CLKENB_B_MARK
 
- VI1_CLKENB_C_MARK
 
- VI1_CLKENB_MARK
 
- VI1_CLK_A_MARK
 
- VI1_CLK_B_MARK
 
- VI1_CLK_C_MARK
 
- VI1_CLK_MARK
 
- VI1_D0_B0_C0_MARK
 
- VI1_D10_G2_Y2_MARK
 
- VI1_D11_G3_Y3_MARK
 
- VI1_D12_G4_Y4_B_MARK
 
- VI1_D12_G4_Y4_MARK
 
- VI1_D13_G5_Y5_B_MARK
 
- VI1_D13_G5_Y5_MARK
 
- VI1_D14_G6_Y6_B_MARK
 
- VI1_D14_G6_Y6_MARK
 
- VI1_D15_G7_Y7_B_MARK
 
- VI1_D15_G7_Y7_MARK
 
- VI1_D16_R0_MARK
 
- VI1_D17_R1_MARK
 
- VI1_D18_R2_MARK
 
- VI1_D19_R3_MARK
 
- VI1_D1_B1_C1_MARK
 
- VI1_D20_R4_MARK
 
- VI1_D21_R5_MARK
 
- VI1_D22_R6_MARK
 
- VI1_D23_R7_MARK
 
- VI1_D2_B2_C2_MARK
 
- VI1_D3_B3_C3_MARK
 
- VI1_D4_B4_C4_MARK
 
- VI1_D5_B5_C5_MARK
 
- VI1_D6_B6_C6_MARK
 
- VI1_D7_B7_C7_MARK
 
- VI1_D8_G0_Y0_MARK
 
- VI1_D9_G1_Y1_MARK
 
- VI1_DATA0_B_MARK
 
- VI1_DATA0_C_MARK
 
- VI1_DATA0_MARK
 
- VI1_DATA0_VI1_B0_B_MARK
 
- VI1_DATA0_VI1_B0_MARK
 
- VI1_DATA10_A_MARK
 
- VI1_DATA10_B_MARK
 
- VI1_DATA10_MARK
 
- VI1_DATA11_A_MARK
 
- VI1_DATA11_B_MARK
 
- VI1_DATA11_MARK
 
- VI1_DATA12_MARK
 
- VI1_DATA13_MARK
 
- VI1_DATA14_MARK
 
- VI1_DATA15_MARK
 
- VI1_DATA1_B_MARK
 
- VI1_DATA1_C_MARK
 
- VI1_DATA1_MARK
 
- VI1_DATA1_VI1_B1_B_MARK
 
- VI1_DATA1_VI1_B1_MARK
 
- VI1_DATA2_B_MARK
 
- VI1_DATA2_C_MARK
 
- VI1_DATA2_MARK
 
- VI1_DATA2_VI1_B2_B_MARK
 
- VI1_DATA2_VI1_B2_MARK
 
- VI1_DATA3_B_MARK
 
- VI1_DATA3_C_MARK
 
- VI1_DATA3_MARK
 
- VI1_DATA3_VI1_B3_B_MARK
 
- VI1_DATA3_VI1_B3_MARK
 
- VI1_DATA4_B_MARK
 
- VI1_DATA4_C_MARK
 
- VI1_DATA4_MARK
 
- VI1_DATA4_VI1_B4_B_MARK
 
- VI1_DATA4_VI1_B4_MARK
 
- VI1_DATA5_B_MARK
 
- VI1_DATA5_C_MARK
 
- VI1_DATA5_MARK
 
- VI1_DATA5_VI1_B5_B_MARK
 
- VI1_DATA5_VI1_B5_MARK
 
- VI1_DATA6_B_MARK
 
- VI1_DATA6_C_MARK
 
- VI1_DATA6_MARK
 
- VI1_DATA6_VI1_B6_B_MARK
 
- VI1_DATA6_VI1_B6_MARK
 
- VI1_DATA7_B_MARK
 
- VI1_DATA7_C_MARK
 
- VI1_DATA7_MARK
 
- VI1_DATA7_VI1_B7_B_MARK
 
- VI1_DATA7_VI1_B7_MARK
 
- VI1_DATA8_MARK
 
- VI1_DATA9_MARK
 
- VI1_FIELD_B_MARK
 
- VI1_FIELD_C_MARK
 
- VI1_FIELD_MARK
 
- VI1_G0_B_MARK
 
- VI1_G0_MARK
 
- VI1_G1_B_MARK
 
- VI1_G1_MARK
 
- VI1_G2_B_MARK
 
- VI1_G2_MARK
 
- VI1_G3_B_MARK
 
- VI1_G3_MARK
 
- VI1_G4_B_MARK
 
- VI1_G4_MARK
 
- VI1_G5_B_MARK
 
- VI1_G5_MARK
 
- VI1_G6_B_MARK
 
- VI1_G6_MARK
 
- VI1_G7_B_MARK
 
- VI1_G7_MARK
 
- VI1_HSYNC_MARK
 
- VI1_HSYNC_N_B_MARK
 
- VI1_HSYNC_N_C_MARK
 
- VI1_HSYNC_N_MARK
 
- VI1_R0_B_MARK
 
- VI1_R0_MARK
 
- VI1_R1_B_MARK
 
- VI1_R1_MARK
 
- VI1_R2_B_MARK
 
- VI1_R2_MARK
 
- VI1_R3_B_MARK
 
- VI1_R3_MARK
 
- VI1_R4_B_MARK
 
- VI1_R4_MARK
 
- VI1_R5_B_MARK
 
- VI1_R5_MARK
 
- VI1_R6_B_MARK
 
- VI1_R6_MARK
 
- VI1_R7_B_MARK
 
- VI1_R7_MARK
 
- VI1_VSYNC_MARK
 
- VI1_VSYNC_N_B_MARK
 
- VI1_VSYNC_N_C_MARK
 
- VI1_VSYNC_N_MARK
 
- VI2_CLKENB_B_MARK
 
- VI2_CLKENB_MARK
 
- VI2_CLK_B_MARK
 
- VI2_CLK_MARK
 
- VI2_D0_C0_MARK
 
- VI2_D10_Y2_MARK
 
- VI2_D11_Y3_MARK
 
- VI2_D12_Y4_MARK
 
- VI2_D13_Y5_MARK
 
- VI2_D14_Y6_MARK
 
- VI2_D15_Y7_MARK
 
- VI2_D1_C1_MARK
 
- VI2_D2_C2_MARK
 
- VI2_D3_C3_MARK
 
- VI2_D4_C4_MARK
 
- VI2_D5_C5_MARK
 
- VI2_D6_C6_MARK
 
- VI2_D7_C7_MARK
 
- VI2_D8_Y0_MARK
 
- VI2_D9_Y1_MARK
 
- VI2_DATA0_MARK
 
- VI2_DATA0_VI2_B0_B_MARK
 
- VI2_DATA0_VI2_B0_MARK
 
- VI2_DATA1_MARK
 
- VI2_DATA1_VI2_B1_B_MARK
 
- VI2_DATA1_VI2_B1_MARK
 
- VI2_DATA2_MARK
 
- VI2_DATA2_VI2_B2_B_MARK
 
- VI2_DATA2_VI2_B2_MARK
 
- VI2_DATA3_MARK
 
- VI2_DATA3_VI2_B3_B_MARK
 
- VI2_DATA3_VI2_B3_MARK
 
- VI2_DATA4_MARK
 
- VI2_DATA4_VI2_B4_B_MARK
 
- VI2_DATA4_VI2_B4_MARK
 
- VI2_DATA5_MARK
 
- VI2_DATA5_VI2_B5_B_MARK
 
- VI2_DATA5_VI2_B5_MARK
 
- VI2_DATA6_MARK
 
- VI2_DATA6_VI2_B6_B_MARK
 
- VI2_DATA6_VI2_B6_MARK
 
- VI2_DATA7_MARK
 
- VI2_DATA7_VI2_B7_B_MARK
 
- VI2_DATA7_VI2_B7_MARK
 
- VI2_FIELD_B_MARK
 
- VI2_FIELD_MARK
 
- VI2_G0_MARK
 
- VI2_G1_MARK
 
- VI2_G2_MARK
 
- VI2_G3_MARK
 
- VI2_G4_MARK
 
- VI2_G5_MARK
 
- VI2_G6_MARK
 
- VI2_G7_MARK
 
- VI2_HSYNC_MARK
 
- VI2_HSYNC_N_B_MARK
 
- VI2_HSYNC_N_MARK
 
- VI2_R0_MARK
 
- VI2_R1_MARK
 
- VI2_R2_MARK
 
- VI2_R3_MARK
 
- VI2_R4_MARK
 
- VI2_R5_MARK
 
- VI2_R6_MARK
 
- VI2_R7_MARK
 
- VI2_VSYNC_MARK
 
- VI2_VSYNC_N_B_MARK
 
- VI2_VSYNC_N_MARK
 
- VI3_CLKENB_MARK
 
- VI3_CLK_B_MARK
 
- VI3_CLK_MARK
 
- VI3_D0_C0_MARK
 
- VI3_D10_Y2_MARK
 
- VI3_D11_Y3_MARK
 
- VI3_D12_Y4_MARK
 
- VI3_D13_Y5_MARK
 
- VI3_D14_Y6_MARK
 
- VI3_D15_Y7_MARK
 
- VI3_D1_C1_MARK
 
- VI3_D2_C2_MARK
 
- VI3_D3_C3_MARK
 
- VI3_D4_C4_MARK
 
- VI3_D5_C5_MARK
 
- VI3_D6_C6_MARK
 
- VI3_D7_C7_MARK
 
- VI3_D8_Y0_MARK
 
- VI3_D9_Y1_MARK
 
- VI3_DATA0_B_MARK
 
- VI3_DATA0_MARK
 
- VI3_DATA1_B_MARK
 
- VI3_DATA1_MARK
 
- VI3_DATA2_B_MARK
 
- VI3_DATA2_MARK
 
- VI3_DATA3_B_MARK
 
- VI3_DATA3_MARK
 
- VI3_DATA4_B_MARK
 
- VI3_DATA4_MARK
 
- VI3_DATA5_B_MARK
 
- VI3_DATA5_MARK
 
- VI3_DATA6_B_MARK
 
- VI3_DATA6_MARK
 
- VI3_DATA7_B_MARK
 
- VI3_DATA7_MARK
 
- VI3_FIELD_MARK
 
- VI3_HSYNC_MARK
 
- VI3_HSYNC_N_MARK
 
- VI3_VSYNC_MARK
 
- VI3_VSYNC_N_MARK
 
- VI4_CLKENB_MARK
 
- VI4_CLK_MARK
 
- VI4_D0_C0_MARK
 
- VI4_D10_Y2_MARK
 
- VI4_D11_Y3_MARK
 
- VI4_D1_C1_MARK
 
- VI4_D2_C2_MARK
 
- VI4_D3_C3_MARK
 
- VI4_D4_C4_MARK
 
- VI4_D5_C5_MARK
 
- VI4_D6_C6_MARK
 
- VI4_D7_C7_MARK
 
- VI4_D8_Y0_MARK
 
- VI4_D9_Y1_MARK
 
- VI4_FIELD_MARK
 
- VI4_HSYNC_N_MARK
 
- VI4_VSYNC_N_MARK
 
- VI5_CLKENB_MARK
 
- VI5_CLK_MARK
 
- VI5_D0_C0_MARK
 
- VI5_D10_Y2_MARK
 
- VI5_D11_Y3_MARK
 
- VI5_D1_C1_MARK
 
- VI5_D2_C2_MARK
 
- VI5_D3_C3_MARK
 
- VI5_D4_C4_MARK
 
- VI5_D5_C5_MARK
 
- VI5_D6_C6_MARK
 
- VI5_D7_C7_MARK
 
- VI5_D8_Y0_MARK
 
- VI5_D9_Y1_MARK
 
- VI5_FIELD_MARK
 
- VI5_HSYNC_N_MARK
 
- VI5_VSYNC_N_MARK
 
- VI6_BRS_BASE
 
- VI6_BRU_BASE
 
- VI6_BRU_BLD
 
- VI6_BRU_BLD_ABES
 
- VI6_BRU_BLD_ACMDX_255_DST_A
 
- VI6_BRU_BLD_ACMDX_255_SRC_A
 
- VI6_BRU_BLD_ACMDX_COEFX
 
- VI6_BRU_BLD_ACMDX_DST_A
 
- VI6_BRU_BLD_ACMDX_MASK
 
- VI6_BRU_BLD_ACMDX_SRC_A
 
- VI6_BRU_BLD_ACMDY_255_DST_A
 
- VI6_BRU_BLD_ACMDY_255_SRC_A
 
- VI6_BRU_BLD_ACMDY_COEFY
 
- VI6_BRU_BLD_ACMDY_DST_A
 
- VI6_BRU_BLD_ACMDY_MASK
 
- VI6_BRU_BLD_ACMDY_SRC_A
 
- VI6_BRU_BLD_CBES
 
- VI6_BRU_BLD_CCMDX_255_DST_A
 
- VI6_BRU_BLD_CCMDX_255_SRC_A
 
- VI6_BRU_BLD_CCMDX_COEFX
 
- VI6_BRU_BLD_CCMDX_DST_A
 
- VI6_BRU_BLD_CCMDX_MASK
 
- VI6_BRU_BLD_CCMDX_SRC_A
 
- VI6_BRU_BLD_CCMDY_255_DST_A
 
- VI6_BRU_BLD_CCMDY_255_SRC_A
 
- VI6_BRU_BLD_CCMDY_COEFY
 
- VI6_BRU_BLD_CCMDY_DST_A
 
- VI6_BRU_BLD_CCMDY_MASK
 
- VI6_BRU_BLD_CCMDY_SHIFT
 
- VI6_BRU_BLD_CCMDY_SRC_A
 
- VI6_BRU_BLD_COEFX_MASK
 
- VI6_BRU_BLD_COEFX_SHIFT
 
- VI6_BRU_BLD_COEFY_MASK
 
- VI6_BRU_BLD_COEFY_SHIFT
 
- VI6_BRU_CTRL
 
- VI6_BRU_CTRL_AROP
 
- VI6_BRU_CTRL_AROP_MASK
 
- VI6_BRU_CTRL_CROP
 
- VI6_BRU_CTRL_CROP_MASK
 
- VI6_BRU_CTRL_DSTSEL_BRUIN
 
- VI6_BRU_CTRL_DSTSEL_MASK
 
- VI6_BRU_CTRL_DSTSEL_VRPF
 
- VI6_BRU_CTRL_RBC
 
- VI6_BRU_CTRL_SRCSEL_BRUIN
 
- VI6_BRU_CTRL_SRCSEL_MASK
 
- VI6_BRU_CTRL_SRCSEL_VRPF
 
- VI6_BRU_INCTRL
 
- VI6_BRU_INCTRL_DITHn_12BPP
 
- VI6_BRU_INCTRL_DITHn_15BPP
 
- VI6_BRU_INCTRL_DITHn_16BPP
 
- VI6_BRU_INCTRL_DITHn_18BPP
 
- VI6_BRU_INCTRL_DITHn_8BPP
 
- VI6_BRU_INCTRL_DITHn_MASK
 
- VI6_BRU_INCTRL_DITHn_OFF
 
- VI6_BRU_INCTRL_DITHn_SHIFT
 
- VI6_BRU_INCTRL_DnON
 
- VI6_BRU_INCTRL_NRM
 
- VI6_BRU_ROP
 
- VI6_BRU_ROP_AROP
 
- VI6_BRU_ROP_AROP_MASK
 
- VI6_BRU_ROP_CROP
 
- VI6_BRU_ROP_CROP_MASK
 
- VI6_BRU_ROP_DSTSEL_BRUIN
 
- VI6_BRU_ROP_DSTSEL_MASK
 
- VI6_BRU_ROP_DSTSEL_VRPF
 
- VI6_BRU_VIRRPF_COL
 
- VI6_BRU_VIRRPF_COL_A_MASK
 
- VI6_BRU_VIRRPF_COL_A_SHIFT
 
- VI6_BRU_VIRRPF_COL_BCB_MASK
 
- VI6_BRU_VIRRPF_COL_BCB_SHIFT
 
- VI6_BRU_VIRRPF_COL_GY_MASK
 
- VI6_BRU_VIRRPF_COL_GY_SHIFT
 
- VI6_BRU_VIRRPF_COL_RCR_MASK
 
- VI6_BRU_VIRRPF_COL_RCR_SHIFT
 
- VI6_BRU_VIRRPF_LOC
 
- VI6_BRU_VIRRPF_LOC_HCOORD_MASK
 
- VI6_BRU_VIRRPF_LOC_HCOORD_SHIFT
 
- VI6_BRU_VIRRPF_LOC_VCOORD_MASK
 
- VI6_BRU_VIRRPF_LOC_VCOORD_SHIFT
 
- VI6_BRU_VIRRPF_SIZE
 
- VI6_BRU_VIRRPF_SIZE_HSIZE_MASK
 
- VI6_BRU_VIRRPF_SIZE_HSIZE_SHIFT
 
- VI6_BRU_VIRRPF_SIZE_VSIZE_MASK
 
- VI6_BRU_VIRRPF_SIZE_VSIZE_SHIFT
 
- VI6_CLK_DCSWT
 
- VI6_CLK_DCSWT_CSTPW_MASK
 
- VI6_CLK_DCSWT_CSTPW_SHIFT
 
- VI6_CLK_DCSWT_CSTRW_MASK
 
- VI6_CLK_DCSWT_CSTRW_SHIFT
 
- VI6_CLUT_TABLE
 
- VI6_CLU_ADDR
 
- VI6_CLU_CTRL
 
- VI6_CLU_CTRL_AAI
 
- VI6_CLU_CTRL_AX1I_2D
 
- VI6_CLU_CTRL_AX2I_2D
 
- VI6_CLU_CTRL_EN
 
- VI6_CLU_CTRL_M2D
 
- VI6_CLU_CTRL_MVS
 
- VI6_CLU_CTRL_OS0_2D
 
- VI6_CLU_CTRL_OS1_2D
 
- VI6_CLU_CTRL_OS2_2D
 
- VI6_CLU_DATA
 
- VI6_CMD
 
- VI6_CMD_STRCMD
 
- VI6_CMD_UPDHDR
 
- VI6_DISP_IRQ_ENB
 
- VI6_DISP_IRQ_ENB_DSTE
 
- VI6_DISP_IRQ_ENB_LNEE
 
- VI6_DISP_IRQ_ENB_MAEE
 
- VI6_DISP_IRQ_STA
 
- VI6_DISP_IRQ_STA_DST
 
- VI6_DISP_IRQ_STA_LNE
 
- VI6_DISP_IRQ_STA_MAE
 
- VI6_DL_BODY_SIZE
 
- VI6_DL_BODY_SIZE_BS_MASK
 
- VI6_DL_BODY_SIZE_BS_SHIFT
 
- VI6_DL_BODY_SIZE_UPD
 
- VI6_DL_CTRL
 
- VI6_DL_CTRL_AR_WAIT_MASK
 
- VI6_DL_CTRL_AR_WAIT_SHIFT
 
- VI6_DL_CTRL_CFM0
 
- VI6_DL_CTRL_DC0
 
- VI6_DL_CTRL_DC1
 
- VI6_DL_CTRL_DC2
 
- VI6_DL_CTRL_DLE
 
- VI6_DL_CTRL_NH0
 
- VI6_DL_EXT_AUTOFLD_INT
 
- VI6_DL_EXT_CTRL
 
- VI6_DL_EXT_CTRL_DLPRI
 
- VI6_DL_EXT_CTRL_EXPRI
 
- VI6_DL_EXT_CTRL_EXT
 
- VI6_DL_EXT_CTRL_NWE
 
- VI6_DL_EXT_CTRL_POLINT_MASK
 
- VI6_DL_EXT_CTRL_POLINT_SHIFT
 
- VI6_DL_HDR_ADDR
 
- VI6_DL_SWAP
 
- VI6_DL_SWAP_BTS
 
- VI6_DL_SWAP_LWS
 
- VI6_DL_SWAP_WDS
 
- VI6_DPR_BRU_ROUTE
 
- VI6_DPR_CLU_ROUTE
 
- VI6_DPR_HGO_SMPPT
 
- VI6_DPR_HGT_SMPPT
 
- VI6_DPR_HSI_ROUTE
 
- VI6_DPR_HST_ROUTE
 
- VI6_DPR_ILV_BRS_ROUTE
 
- VI6_DPR_LUT_ROUTE
 
- VI6_DPR_NODE_BRS_IN
 
- VI6_DPR_NODE_BRU_IN
 
- VI6_DPR_NODE_BRU_OUT
 
- VI6_DPR_NODE_CLU
 
- VI6_DPR_NODE_HSI
 
- VI6_DPR_NODE_HST
 
- VI6_DPR_NODE_LIF
 
- VI6_DPR_NODE_LUT
 
- VI6_DPR_NODE_RPF
 
- VI6_DPR_NODE_SRU
 
- VI6_DPR_NODE_UDS
 
- VI6_DPR_NODE_UIF
 
- VI6_DPR_NODE_UNUSED
 
- VI6_DPR_NODE_WPF
 
- VI6_DPR_ROUTE_BRSSEL
 
- VI6_DPR_ROUTE_FP_MASK
 
- VI6_DPR_ROUTE_FP_SHIFT
 
- VI6_DPR_ROUTE_FXA_MASK
 
- VI6_DPR_ROUTE_FXA_SHIFT
 
- VI6_DPR_ROUTE_RT_MASK
 
- VI6_DPR_ROUTE_RT_SHIFT
 
- VI6_DPR_RPF_ROUTE
 
- VI6_DPR_SMPPT_PT_MASK
 
- VI6_DPR_SMPPT_PT_SHIFT
 
- VI6_DPR_SMPPT_TGW_MASK
 
- VI6_DPR_SMPPT_TGW_SHIFT
 
- VI6_DPR_SRU_ROUTE
 
- VI6_DPR_UDS_ROUTE
 
- VI6_DPR_UIF_ROUTE
 
- VI6_DPR_WPF_FPORCH
 
- VI6_DPR_WPF_FPORCH_FP_WPFN
 
- VI6_FMT_ABGR_1555
 
- VI6_FMT_ABGR_4444
 
- VI6_FMT_ABGR_8888
 
- VI6_FMT_ARGBX_86666
 
- VI6_FMT_ARGB_1555
 
- VI6_FMT_ARGB_4444
 
- VI6_FMT_ARGB_8888
 
- VI6_FMT_ARXGXBX_8626262
 
- VI6_FMT_AXRGB_86666
 
- VI6_FMT_AXRXGXB_8262626
 
- VI6_FMT_BGRA_4444
 
- VI6_FMT_BGRA_5551
 
- VI6_FMT_BGR_888
 
- VI6_FMT_RGBA_4444
 
- VI6_FMT_RGBA_5551
 
- VI6_FMT_RGBA_8888
 
- VI6_FMT_RGBXA_66668
 
- VI6_FMT_RGBX_4444
 
- VI6_FMT_RGBX_5551
 
- VI6_FMT_RGBX_6666
 
- VI6_FMT_RGB_332
 
- VI6_FMT_RGB_565
 
- VI6_FMT_RGB_888
 
- VI6_FMT_RXGXBXA_6262628
 
- VI6_FMT_RXGXBX_626262
 
- VI6_FMT_XBXGXR_262626
 
- VI6_FMT_XRGBA_66668
 
- VI6_FMT_XRGB_1555
 
- VI6_FMT_XRGB_4444
 
- VI6_FMT_XRGB_6666
 
- VI6_FMT_XRGXGB_763763
 
- VI6_FMT_XRXGXBA_2626268
 
- VI6_FMT_XRXGXB_262626
 
- VI6_FMT_XXRGB_86666
 
- VI6_FMT_XXRGB_88565
 
- VI6_FMT_YUV_420
 
- VI6_FMT_YUV_444
 
- VI6_FMT_YUYV_422
 
- VI6_FMT_YYUV_422
 
- VI6_FMT_Y_UV_420
 
- VI6_FMT_Y_UV_422
 
- VI6_FMT_Y_UV_444
 
- VI6_FMT_Y_U_V_420
 
- VI6_FMT_Y_U_V_422
 
- VI6_FMT_Y_U_V_444
 
- VI6_HGO_B_HISTO
 
- VI6_HGO_B_LB_DET
 
- VI6_HGO_B_MAXMIN
 
- VI6_HGO_B_SUM
 
- VI6_HGO_EXT_HIST_ADDR
 
- VI6_HGO_EXT_HIST_DATA
 
- VI6_HGO_G_HISTO
 
- VI6_HGO_G_LB_DET
 
- VI6_HGO_G_MAXMIN
 
- VI6_HGO_G_SUM
 
- VI6_HGO_LB_TH
 
- VI6_HGO_LBn_H
 
- VI6_HGO_LBn_V
 
- VI6_HGO_MODE
 
- VI6_HGO_MODE_HRATIO_SHIFT
 
- VI6_HGO_MODE_MAXRGB
 
- VI6_HGO_MODE_OFSB_B
 
- VI6_HGO_MODE_OFSB_G
 
- VI6_HGO_MODE_OFSB_R
 
- VI6_HGO_MODE_STEP
 
- VI6_HGO_MODE_VRATIO_SHIFT
 
- VI6_HGO_OFFSET
 
- VI6_HGO_OFFSET_HOFFSET_SHIFT
 
- VI6_HGO_OFFSET_VOFFSET_SHIFT
 
- VI6_HGO_REGRST
 
- VI6_HGO_REGRST_RCLEA
 
- VI6_HGO_R_HISTO
 
- VI6_HGO_R_LB_DET
 
- VI6_HGO_R_MAXMIN
 
- VI6_HGO_R_SUM
 
- VI6_HGO_SIZE
 
- VI6_HGO_SIZE_HSIZE_SHIFT
 
- VI6_HGO_SIZE_VSIZE_SHIFT
 
- VI6_HGT_HISTO
 
- VI6_HGT_HUE_AREA
 
- VI6_HGT_HUE_AREA_LOWER_SHIFT
 
- VI6_HGT_HUE_AREA_UPPER_SHIFT
 
- VI6_HGT_LB_DET
 
- VI6_HGT_LB_TH
 
- VI6_HGT_LBn_H
 
- VI6_HGT_LBn_V
 
- VI6_HGT_MAXMIN
 
- VI6_HGT_MODE
 
- VI6_HGT_MODE_HRATIO_SHIFT
 
- VI6_HGT_MODE_VRATIO_SHIFT
 
- VI6_HGT_OFFSET
 
- VI6_HGT_OFFSET_HOFFSET_SHIFT
 
- VI6_HGT_OFFSET_VOFFSET_SHIFT
 
- VI6_HGT_REGRST
 
- VI6_HGT_REGRST_RCLEA
 
- VI6_HGT_SIZE
 
- VI6_HGT_SIZE_HSIZE_SHIFT
 
- VI6_HGT_SIZE_VSIZE_SHIFT
 
- VI6_HGT_SUM
 
- VI6_HSI_CTRL
 
- VI6_HSI_CTRL_EN
 
- VI6_HST_CTRL
 
- VI6_HST_CTRL_EN
 
- VI6_IP_VERSION
 
- VI6_IP_VERSION_MASK
 
- VI6_IP_VERSION_MODEL_MASK
 
- VI6_IP_VERSION_MODEL_VSPBC_GEN3
 
- VI6_IP_VERSION_MODEL_VSPBD_GEN3
 
- VI6_IP_VERSION_MODEL_VSPBS_GEN3
 
- VI6_IP_VERSION_MODEL_VSPDL_GEN3
 
- VI6_IP_VERSION_MODEL_VSPD_GEN2
 
- VI6_IP_VERSION_MODEL_VSPD_GEN3
 
- VI6_IP_VERSION_MODEL_VSPD_V2H
 
- VI6_IP_VERSION_MODEL_VSPD_V3
 
- VI6_IP_VERSION_MODEL_VSPI_GEN3
 
- VI6_IP_VERSION_MODEL_VSPR_H2
 
- VI6_IP_VERSION_MODEL_VSPS_H2
 
- VI6_IP_VERSION_MODEL_VSPS_M2
 
- VI6_IP_VERSION_MODEL_VSPS_V2H
 
- VI6_IP_VERSION_SOC_D3
 
- VI6_IP_VERSION_SOC_E3
 
- VI6_IP_VERSION_SOC_H2
 
- VI6_IP_VERSION_SOC_H3
 
- VI6_IP_VERSION_SOC_M2
 
- VI6_IP_VERSION_SOC_M3N
 
- VI6_IP_VERSION_SOC_M3W
 
- VI6_IP_VERSION_SOC_MASK
 
- VI6_IP_VERSION_SOC_V2H
 
- VI6_IP_VERSION_SOC_V3H
 
- VI6_IP_VERSION_SOC_V3M
 
- VI6_LIF_CSBTH
 
- VI6_LIF_CSBTH_HBTH_MASK
 
- VI6_LIF_CSBTH_HBTH_SHIFT
 
- VI6_LIF_CSBTH_LBTH_MASK
 
- VI6_LIF_CSBTH_LBTH_SHIFT
 
- VI6_LIF_CTRL
 
- VI6_LIF_CTRL_CFMT
 
- VI6_LIF_CTRL_LIF_EN
 
- VI6_LIF_CTRL_OBTH_MASK
 
- VI6_LIF_CTRL_OBTH_SHIFT
 
- VI6_LIF_CTRL_REQSEL
 
- VI6_LIF_LBA
 
- VI6_LIF_LBA_LBA0
 
- VI6_LIF_LBA_LBA1_MASK
 
- VI6_LIF_LBA_LBA1_SHIFT
 
- VI6_LIF_OFFSET
 
- VI6_LUT_CTRL
 
- VI6_LUT_CTRL_EN
 
- VI6_LUT_TABLE
 
- VI6_ROP_AND
 
- VI6_ROP_AND_INV
 
- VI6_ROP_AND_REV
 
- VI6_ROP_CLEAR
 
- VI6_ROP_COPY
 
- VI6_ROP_COPY_INV
 
- VI6_ROP_EQUIV
 
- VI6_ROP_INVERT
 
- VI6_ROP_NAND
 
- VI6_ROP_NOP
 
- VI6_ROP_NOR
 
- VI6_ROP_OR
 
- VI6_ROP_OR_INV
 
- VI6_ROP_OR_REV
 
- VI6_ROP_SET
 
- VI6_ROP_XOR
 
- VI6_RPF_ALPH_SEL
 
- VI6_RPF_ALPH_SEL_AEXT_EXT
 
- VI6_RPF_ALPH_SEL_AEXT_MASK
 
- VI6_RPF_ALPH_SEL_AEXT_ONE
 
- VI6_RPF_ALPH_SEL_AEXT_ZERO
 
- VI6_RPF_ALPH_SEL_ALPHA0_MASK
 
- VI6_RPF_ALPH_SEL_ALPHA0_SHIFT
 
- VI6_RPF_ALPH_SEL_ALPHA1_MASK
 
- VI6_RPF_ALPH_SEL_ALPHA1_SHIFT
 
- VI6_RPF_ALPH_SEL_ASEL_1B_PLANE
 
- VI6_RPF_ALPH_SEL_ASEL_8B_PLANE
 
- VI6_RPF_ALPH_SEL_ASEL_FIXED
 
- VI6_RPF_ALPH_SEL_ASEL_MASK
 
- VI6_RPF_ALPH_SEL_ASEL_PACKED
 
- VI6_RPF_ALPH_SEL_ASEL_SELECT
 
- VI6_RPF_ALPH_SEL_ASEL_SHIFT
 
- VI6_RPF_ALPH_SEL_BSEL
 
- VI6_RPF_ALPH_SEL_IROP_MASK
 
- VI6_RPF_ALPH_SEL_IROP_SHIFT
 
- VI6_RPF_CKEY_CTRL
 
- VI6_RPF_CKEY_CTRL_CV
 
- VI6_RPF_CKEY_CTRL_SAPE0
 
- VI6_RPF_CKEY_CTRL_SAPE1
 
- VI6_RPF_CKEY_SET0
 
- VI6_RPF_CKEY_SET1
 
- VI6_RPF_CKEY_SET_AP_MASK
 
- VI6_RPF_CKEY_SET_AP_SHIFT
 
- VI6_RPF_CKEY_SET_B_MASK
 
- VI6_RPF_CKEY_SET_B_SHIFT
 
- VI6_RPF_CKEY_SET_GY_MASK
 
- VI6_RPF_CKEY_SET_GY_SHIFT
 
- VI6_RPF_CKEY_SET_R_MASK
 
- VI6_RPF_CKEY_SET_R_SHIFT
 
- VI6_RPF_DSWAP
 
- VI6_RPF_DSWAP_A_BTS
 
- VI6_RPF_DSWAP_A_LLS
 
- VI6_RPF_DSWAP_A_LWS
 
- VI6_RPF_DSWAP_A_WDS
 
- VI6_RPF_DSWAP_P_BTS
 
- VI6_RPF_DSWAP_P_LLS
 
- VI6_RPF_DSWAP_P_LWS
 
- VI6_RPF_DSWAP_P_WDS
 
- VI6_RPF_INFMT
 
- VI6_RPF_INFMT_CEXT_EXT
 
- VI6_RPF_INFMT_CEXT_MASK
 
- VI6_RPF_INFMT_CEXT_ONE
 
- VI6_RPF_INFMT_CEXT_ZERO
 
- VI6_RPF_INFMT_CIPM
 
- VI6_RPF_INFMT_CSC
 
- VI6_RPF_INFMT_RDFMT_MASK
 
- VI6_RPF_INFMT_RDFMT_SHIFT
 
- VI6_RPF_INFMT_RDTM_BT601
 
- VI6_RPF_INFMT_RDTM_BT601_EXT
 
- VI6_RPF_INFMT_RDTM_BT709
 
- VI6_RPF_INFMT_RDTM_BT709_EXT
 
- VI6_RPF_INFMT_RDTM_MASK
 
- VI6_RPF_INFMT_SPUVS
 
- VI6_RPF_INFMT_SPYCS
 
- VI6_RPF_INFMT_VIR
 
- VI6_RPF_LOC
 
- VI6_RPF_LOC_HCOORD_MASK
 
- VI6_RPF_LOC_HCOORD_SHIFT
 
- VI6_RPF_LOC_VCOORD_MASK
 
- VI6_RPF_LOC_VCOORD_SHIFT
 
- VI6_RPF_MSK_CTRL
 
- VI6_RPF_MSK_CTRL_MGB_MASK
 
- VI6_RPF_MSK_CTRL_MGB_SHIFT
 
- VI6_RPF_MSK_CTRL_MGG_MASK
 
- VI6_RPF_MSK_CTRL_MGG_SHIFT
 
- VI6_RPF_MSK_CTRL_MGR_MASK
 
- VI6_RPF_MSK_CTRL_MGR_SHIFT
 
- VI6_RPF_MSK_CTRL_MSK_EN
 
- VI6_RPF_MSK_SET0
 
- VI6_RPF_MSK_SET1
 
- VI6_RPF_MSK_SET_MSA_MASK
 
- VI6_RPF_MSK_SET_MSA_SHIFT
 
- VI6_RPF_MSK_SET_MSB_MASK
 
- VI6_RPF_MSK_SET_MSB_SHIFT
 
- VI6_RPF_MSK_SET_MSG_MASK
 
- VI6_RPF_MSK_SET_MSG_SHIFT
 
- VI6_RPF_MSK_SET_MSR_MASK
 
- VI6_RPF_MSK_SET_MSR_SHIFT
 
- VI6_RPF_MULT_ALPHA
 
- VI6_RPF_MULT_ALPHA_A_MMD_NONE
 
- VI6_RPF_MULT_ALPHA_A_MMD_RATIO
 
- VI6_RPF_MULT_ALPHA_P_MMD_BOTH
 
- VI6_RPF_MULT_ALPHA_P_MMD_IMAGE
 
- VI6_RPF_MULT_ALPHA_P_MMD_NONE
 
- VI6_RPF_MULT_ALPHA_P_MMD_RATIO
 
- VI6_RPF_MULT_ALPHA_RATIO_MASK
 
- VI6_RPF_MULT_ALPHA_RATIO_SHIFT
 
- VI6_RPF_OFFSET
 
- VI6_RPF_SRCM_ADDR_AI
 
- VI6_RPF_SRCM_ADDR_C0
 
- VI6_RPF_SRCM_ADDR_C1
 
- VI6_RPF_SRCM_ADDR_Y
 
- VI6_RPF_SRCM_ASTRIDE
 
- VI6_RPF_SRCM_PSTRIDE
 
- VI6_RPF_SRCM_PSTRIDE_A_SHIFT
 
- VI6_RPF_SRCM_PSTRIDE_C_SHIFT
 
- VI6_RPF_SRCM_PSTRIDE_Y_SHIFT
 
- VI6_RPF_SRC_BSIZE
 
- VI6_RPF_SRC_BSIZE_BHSIZE_MASK
 
- VI6_RPF_SRC_BSIZE_BHSIZE_SHIFT
 
- VI6_RPF_SRC_BSIZE_BVSIZE_MASK
 
- VI6_RPF_SRC_BSIZE_BVSIZE_SHIFT
 
- VI6_RPF_SRC_ESIZE
 
- VI6_RPF_SRC_ESIZE_EHSIZE_MASK
 
- VI6_RPF_SRC_ESIZE_EHSIZE_SHIFT
 
- VI6_RPF_SRC_ESIZE_EVSIZE_MASK
 
- VI6_RPF_SRC_ESIZE_EVSIZE_SHIFT
 
- VI6_RPF_VRTCOL_SET
 
- VI6_RPF_VRTCOL_SET_LAYA_MASK
 
- VI6_RPF_VRTCOL_SET_LAYA_SHIFT
 
- VI6_RPF_VRTCOL_SET_LAYB_MASK
 
- VI6_RPF_VRTCOL_SET_LAYB_SHIFT
 
- VI6_RPF_VRTCOL_SET_LAYG_MASK
 
- VI6_RPF_VRTCOL_SET_LAYG_SHIFT
 
- VI6_RPF_VRTCOL_SET_LAYR_MASK
 
- VI6_RPF_VRTCOL_SET_LAYR_SHIFT
 
- VI6_SECURITY_CTRL0
 
- VI6_SECURITY_CTRL1
 
- VI6_SRESET
 
- VI6_SRESET_SRTS
 
- VI6_SRU_CTRL0
 
- VI6_SRU_CTRL0_EN
 
- VI6_SRU_CTRL0_MODE_UPSCALE
 
- VI6_SRU_CTRL0_PARAM0_MASK
 
- VI6_SRU_CTRL0_PARAM0_SHIFT
 
- VI6_SRU_CTRL0_PARAM1_MASK
 
- VI6_SRU_CTRL0_PARAM1_SHIFT
 
- VI6_SRU_CTRL0_PARAM2
 
- VI6_SRU_CTRL0_PARAM3
 
- VI6_SRU_CTRL0_PARAM4
 
- VI6_SRU_CTRL0_PARAMS
 
- VI6_SRU_CTRL1
 
- VI6_SRU_CTRL1_PARAM5
 
- VI6_SRU_CTRL2
 
- VI6_SRU_CTRL2_PARAM6_SHIFT
 
- VI6_SRU_CTRL2_PARAM7_SHIFT
 
- VI6_SRU_CTRL2_PARAM8_SHIFT
 
- VI6_SRU_CTRL2_PARAMS
 
- VI6_STATUS
 
- VI6_STATUS_FLD_STD
 
- VI6_STATUS_SYS_ACT
 
- VI6_UDS_ALPTH
 
- VI6_UDS_ALPTH_TH0_MASK
 
- VI6_UDS_ALPTH_TH0_SHIFT
 
- VI6_UDS_ALPTH_TH1_MASK
 
- VI6_UDS_ALPTH_TH1_SHIFT
 
- VI6_UDS_ALPVAL
 
- VI6_UDS_ALPVAL_VAL0_MASK
 
- VI6_UDS_ALPVAL_VAL0_SHIFT
 
- VI6_UDS_ALPVAL_VAL1_MASK
 
- VI6_UDS_ALPVAL_VAL1_SHIFT
 
- VI6_UDS_ALPVAL_VAL2_MASK
 
- VI6_UDS_ALPVAL_VAL2_SHIFT
 
- VI6_UDS_CLIP_SIZE
 
- VI6_UDS_CLIP_SIZE_HSIZE_MASK
 
- VI6_UDS_CLIP_SIZE_HSIZE_SHIFT
 
- VI6_UDS_CLIP_SIZE_VSIZE_MASK
 
- VI6_UDS_CLIP_SIZE_VSIZE_SHIFT
 
- VI6_UDS_CTRL
 
- VI6_UDS_CTRL_AMD
 
- VI6_UDS_CTRL_AMDSLH
 
- VI6_UDS_CTRL_AON
 
- VI6_UDS_CTRL_ATHON
 
- VI6_UDS_CTRL_BC
 
- VI6_UDS_CTRL_BLADV
 
- VI6_UDS_CTRL_FMD
 
- VI6_UDS_CTRL_NE_A
 
- VI6_UDS_CTRL_NE_BCB
 
- VI6_UDS_CTRL_NE_GY
 
- VI6_UDS_CTRL_NE_RCR
 
- VI6_UDS_CTRL_TDIPC
 
- VI6_UDS_FILL_COLOR
 
- VI6_UDS_FILL_COLOR_BFILC_MASK
 
- VI6_UDS_FILL_COLOR_BFILC_SHIFT
 
- VI6_UDS_FILL_COLOR_GFILC_MASK
 
- VI6_UDS_FILL_COLOR_GFILC_SHIFT
 
- VI6_UDS_FILL_COLOR_RFILC_MASK
 
- VI6_UDS_FILL_COLOR_RFILC_SHIFT
 
- VI6_UDS_HPHASE
 
- VI6_UDS_HPHASE_HEDP_MASK
 
- VI6_UDS_HPHASE_HEDP_SHIFT
 
- VI6_UDS_HPHASE_HSTP_MASK
 
- VI6_UDS_HPHASE_HSTP_SHIFT
 
- VI6_UDS_HSZCLIP
 
- VI6_UDS_HSZCLIP_HCEN
 
- VI6_UDS_HSZCLIP_HCL_OFST_MASK
 
- VI6_UDS_HSZCLIP_HCL_OFST_SHIFT
 
- VI6_UDS_HSZCLIP_HCL_SIZE_MASK
 
- VI6_UDS_HSZCLIP_HCL_SIZE_SHIFT
 
- VI6_UDS_IPC
 
- VI6_UDS_IPC_FIELD
 
- VI6_UDS_IPC_VEDP_MASK
 
- VI6_UDS_IPC_VEDP_SHIFT
 
- VI6_UDS_OFFSET
 
- VI6_UDS_PASS_BWIDTH
 
- VI6_UDS_PASS_BWIDTH_H_MASK
 
- VI6_UDS_PASS_BWIDTH_H_SHIFT
 
- VI6_UDS_PASS_BWIDTH_V_MASK
 
- VI6_UDS_PASS_BWIDTH_V_SHIFT
 
- VI6_UDS_SCALE
 
- VI6_UDS_SCALE_HFRAC_MASK
 
- VI6_UDS_SCALE_HFRAC_SHIFT
 
- VI6_UDS_SCALE_HMANT_MASK
 
- VI6_UDS_SCALE_HMANT_SHIFT
 
- VI6_UDS_SCALE_VFRAC_MASK
 
- VI6_UDS_SCALE_VFRAC_SHIFT
 
- VI6_UDS_SCALE_VMANT_MASK
 
- VI6_UDS_SCALE_VMANT_SHIFT
 
- VI6_UIF_DISCOM_DOCMCCRCR
 
- VI6_UIF_DISCOM_DOCMCLSTR
 
- VI6_UIF_DISCOM_DOCMCLSTR_CMPCLPRE
 
- VI6_UIF_DISCOM_DOCMCLSTR_CMPCLST
 
- VI6_UIF_DISCOM_DOCMCR
 
- VI6_UIF_DISCOM_DOCMCR_CMPR
 
- VI6_UIF_DISCOM_DOCMCR_CMPRU
 
- VI6_UIF_DISCOM_DOCMECRCR
 
- VI6_UIF_DISCOM_DOCMIENR
 
- VI6_UIF_DISCOM_DOCMIENR_CMPIEN
 
- VI6_UIF_DISCOM_DOCMIENR_CMPPREIEN
 
- VI6_UIF_DISCOM_DOCMMDR
 
- VI6_UIF_DISCOM_DOCMMDR_INTHRH
 
- VI6_UIF_DISCOM_DOCMPMR
 
- VI6_UIF_DISCOM_DOCMPMR_CMPDAUF
 
- VI6_UIF_DISCOM_DOCMPMR_CMPDFA
 
- VI6_UIF_DISCOM_DOCMPMR_CMPDFF
 
- VI6_UIF_DISCOM_DOCMPMR_SEL
 
- VI6_UIF_DISCOM_DOCMSPXR
 
- VI6_UIF_DISCOM_DOCMSPYR
 
- VI6_UIF_DISCOM_DOCMSTR
 
- VI6_UIF_DISCOM_DOCMSTR_CMPPRE
 
- VI6_UIF_DISCOM_DOCMSTR_CMPST
 
- VI6_UIF_DISCOM_DOCMSZXR
 
- VI6_UIF_DISCOM_DOCMSZYR
 
- VI6_UIF_OFFSET
 
- VI6_WFP_IRQ_ENB_DFEE
 
- VI6_WFP_IRQ_ENB_FREE
 
- VI6_WFP_IRQ_STA_DFE
 
- VI6_WFP_IRQ_STA_FRE
 
- VI6_WPF_DSTM_ADDR_C0
 
- VI6_WPF_DSTM_ADDR_C1
 
- VI6_WPF_DSTM_ADDR_Y
 
- VI6_WPF_DSTM_STRIDE_C
 
- VI6_WPF_DSTM_STRIDE_Y
 
- VI6_WPF_DSWAP
 
- VI6_WPF_DSWAP_P_BTS
 
- VI6_WPF_DSWAP_P_LLS
 
- VI6_WPF_DSWAP_P_LWS
 
- VI6_WPF_DSWAP_P_WDS
 
- VI6_WPF_HSZCLIP
 
- VI6_WPF_IRQ_ENB
 
- VI6_WPF_IRQ_STA
 
- VI6_WPF_LINE_COUNT
 
- VI6_WPF_LINE_COUNT_MASK
 
- VI6_WPF_OFFSET
 
- VI6_WPF_OUTFMT
 
- VI6_WPF_OUTFMT_CSC
 
- VI6_WPF_OUTFMT_DITH_DIS
 
- VI6_WPF_OUTFMT_DITH_EN
 
- VI6_WPF_OUTFMT_DITH_MASK
 
- VI6_WPF_OUTFMT_FLP
 
- VI6_WPF_OUTFMT_HFLP
 
- VI6_WPF_OUTFMT_PDV_MASK
 
- VI6_WPF_OUTFMT_PDV_SHIFT
 
- VI6_WPF_OUTFMT_PXA
 
- VI6_WPF_OUTFMT_ROT
 
- VI6_WPF_OUTFMT_SPUVS
 
- VI6_WPF_OUTFMT_SPYCS
 
- VI6_WPF_OUTFMT_WRFMT_MASK
 
- VI6_WPF_OUTFMT_WRFMT_SHIFT
 
- VI6_WPF_OUTFMT_WRTM_BT601
 
- VI6_WPF_OUTFMT_WRTM_BT601_EXT
 
- VI6_WPF_OUTFMT_WRTM_BT709
 
- VI6_WPF_OUTFMT_WRTM_BT709_EXT
 
- VI6_WPF_OUTFMT_WRTM_MASK
 
- VI6_WPF_RNDCTRL
 
- VI6_WPF_RNDCTRL_ABRM_MASK
 
- VI6_WPF_RNDCTRL_ABRM_ROUND
 
- VI6_WPF_RNDCTRL_ABRM_THRESH
 
- VI6_WPF_RNDCTRL_ABRM_TRUNC
 
- VI6_WPF_RNDCTRL_ATHRESH_MASK
 
- VI6_WPF_RNDCTRL_ATHRESH_SHIFT
 
- VI6_WPF_RNDCTRL_CBRM
 
- VI6_WPF_RNDCTRL_CLMD_CLIP
 
- VI6_WPF_RNDCTRL_CLMD_EXT
 
- VI6_WPF_RNDCTRL_CLMD_FULL
 
- VI6_WPF_RNDCTRL_CLMD_MASK
 
- VI6_WPF_ROT_CTRL
 
- VI6_WPF_ROT_CTRL_LMEM_WD_MASK
 
- VI6_WPF_ROT_CTRL_LMEM_WD_SHIFT
 
- VI6_WPF_ROT_CTRL_LN16
 
- VI6_WPF_SRCRPF
 
- VI6_WPF_SRCRPF_RPF_ACT_DIS
 
- VI6_WPF_SRCRPF_RPF_ACT_MASK
 
- VI6_WPF_SRCRPF_RPF_ACT_MST
 
- VI6_WPF_SRCRPF_RPF_ACT_SUB
 
- VI6_WPF_SRCRPF_VIRACT2_DIS
 
- VI6_WPF_SRCRPF_VIRACT2_MASK
 
- VI6_WPF_SRCRPF_VIRACT2_MST
 
- VI6_WPF_SRCRPF_VIRACT2_SUB
 
- VI6_WPF_SRCRPF_VIRACT_DIS
 
- VI6_WPF_SRCRPF_VIRACT_MASK
 
- VI6_WPF_SRCRPF_VIRACT_MST
 
- VI6_WPF_SRCRPF_VIRACT_SUB
 
- VI6_WPF_SZCLIP_EN
 
- VI6_WPF_SZCLIP_OFST_MASK
 
- VI6_WPF_SZCLIP_OFST_SHIFT
 
- VI6_WPF_SZCLIP_SIZE_MASK
 
- VI6_WPF_SZCLIP_SIZE_SHIFT
 
- VI6_WPF_VSZCLIP
 
- VI6_WPF_WRBCK_CTRL
 
- VI6_WPF_WRBCK_CTRL_WBMD
 
- VIA1A_CPUID0
 
- VIA1A_CPUID1
 
- VIA1A_CPUID2
 
- VIA1A_CPUID3
 
- VIA1A_vHeadSel
 
- VIA1A_vOverlay
 
- VIA1A_vRev8
 
- VIA1A_vSccWrReq
 
- VIA1A_vSync
 
- VIA1A_vVolume
 
- VIA1B_vADBInt
 
- VIA1B_vADBS1
 
- VIA1B_vADBS2
 
- VIA1B_vMystery
 
- VIA1B_vRTCClk
 
- VIA1B_vRTCData
 
- VIA1B_vRTCEnb
 
- VIA1B_vSound
 
- VIA1_BASE
 
- VIA1_SOURCE_BASE
 
- VIA2A_vIRQ9
 
- VIA2A_vIRQA
 
- VIA2A_vIRQB
 
- VIA2A_vIRQC
 
- VIA2A_vIRQD
 
- VIA2A_vIRQE
 
- VIA2A_vRAM0
 
- VIA2A_vRAM1
 
- VIA2B_vBusLk
 
- VIA2B_vCDis
 
- VIA2B_vMode32
 
- VIA2B_vPower
 
- VIA2B_vSndJck
 
- VIA2B_vTfr0
 
- VIA2B_vTfr1
 
- VIA2B_vVBL
 
- VIA2_BASE
 
- VIA2_SOURCE_BASE
 
- VIA686A_BASE_REG
 
- VIA686A_ENABLE_REG
 
- VIA686A_EXTENT
 
- VIA686A_REG_ALARM1
 
- VIA686A_REG_ALARM2
 
- VIA686A_REG_CONFIG
 
- VIA686A_REG_FAN
 
- VIA686A_REG_FANDIV
 
- VIA686A_REG_FAN_MIN
 
- VIA686A_REG_IN
 
- VIA686A_REG_IN_MAX
 
- VIA686A_REG_IN_MIN
 
- VIA686A_REG_TEMP_LOW1
 
- VIA686A_REG_TEMP_LOW23
 
- VIA686A_REG_TEMP_MODE
 
- VIA686A_TEMP_MODE_CONTINUOUS
 
- VIA686A_TEMP_MODE_MASK
 
- VIA8233_INTR_MASK
 
- VIA8233_REG_SGD_CHAN_MULTI
 
- VIA8233_REG_SGD_CHAN_REC
 
- VIA8233_REG_SGD_CHAN_REC1
 
- VIA8233_REG_SGD_CHAN_SDX
 
- VIA8233_REG_SGD_STAT_ACTIVE
 
- VIA8233_REG_SGD_STAT_EOL
 
- VIA8233_REG_SGD_STAT_FLAG
 
- VIA8233_REG_SGD_STAT_STOP
 
- VIA8233_REG_TYPE_16BIT
 
- VIA8233_REG_TYPE_STEREO
 
- VIA8233_SHADOW_STAT_ACTIVE
 
- VIA8233_SPDIF_CTRL
 
- VIA8233_SPDIF_DX3
 
- VIA8233_SPDIF_SLOT_1011
 
- VIA8233_SPDIF_SLOT_34
 
- VIA8233_SPDIF_SLOT_69
 
- VIA8233_SPDIF_SLOT_78
 
- VIA8233_SPDIF_SLOT_MASK
 
- VIA8233_VOLCHG_CTRL
 
- VIAAR
 
- VIACAM_SERIAL_BIT
 
- VIACAM_SERIAL_CREG
 
- VIACAM_SERIAL_DEVFN
 
- VIACR
 
- VIADEV_REG
 
- VIAFB_DEBUG
 
- VIAFB_DMA_FINAL_SEGMENT
 
- VIAFB_DMA_MAGIC
 
- VIAFB_GET_CHIP_INFO
 
- VIAFB_GET_DEVICE
 
- VIAFB_GET_DEVICE_CONNECT
 
- VIAFB_GET_DEVICE_INFO
 
- VIAFB_GET_DEVICE_SUPPORT
 
- VIAFB_GET_DEVICE_SUPPORT_STATE
 
- VIAFB_GET_DRIVER_CAPS
 
- VIAFB_GET_DRIVER_NAME
 
- VIAFB_GET_DRIVER_VERSION
 
- VIAFB_GET_GAMMA_LUT
 
- VIAFB_GET_GAMMA_SUPPORT_STATE
 
- VIAFB_GET_IGA_SCALING_INFO
 
- VIAFB_GET_INFO
 
- VIAFB_GET_INFO_SIZE
 
- VIAFB_GET_PANEL_MAX_POSITION
 
- VIAFB_GET_PANEL_MAX_SIZE
 
- VIAFB_GET_PANEL_POSITION
 
- VIAFB_GET_PANEL_SIZE
 
- VIAFB_GET_PANEL_SUPPORT_EXPAND
 
- VIAFB_GET_RESOLUTION
 
- VIAFB_GET_SAMM_INFO
 
- VIAFB_HOTPLUG
 
- VIAFB_NUM_GPIOS
 
- VIAFB_NUM_I2C
 
- VIAFB_NUM_PORTS
 
- VIAFB_SET_GAMMA_LUT
 
- VIAFB_SET_HOTPLUG_FLAG
 
- VIAFB_SET_PANEL_POSITION
 
- VIAFB_SET_PANEL_SIZE
 
- VIAFB_SYNC_SURFACE
 
- VIAFB_TURN_OFF_OUTPUT_DEVICE
 
- VIAFB_TURN_ON_OUTPUT_DEVICE
 
- VIAFB_WARN
 
- VIAGR
 
- VIAHDMI_CVT_NID
 
- VIAHDMI_PIN_NID
 
- VIAID
 
- VIAREG
 
- VIASR
 
- VIAStatus
 
- VIATELECOM_PRODUCT_CDS7
 
- VIATELECOM_VENDOR_ID
 
- VIA_2D_ENG_BUSY
 
- VIA_2D_ENG_BUSY_H5
 
- VIA_2D_ENG_BUSY_M1
 
- VIA_2D_ENG_H2
 
- VIA_2D_ENG_H5
 
- VIA_2D_ENG_M1
 
- VIA_3D_ENG_BUSY
 
- VIA_3D_ENG_BUSY_H5
 
- VIA_3D_ENG_BUSY_M1
 
- VIA_3D_REG_H
 
- VIA_8363_KL133_REVISION_ID
 
- VIA_8363_KM133_REVISION_ID
 
- VIA_8BIT_TIMING
 
- VIA_ACLINK_C00_READY
 
- VIA_ACLINK_C01_READY
 
- VIA_ACLINK_C10_READY
 
- VIA_ACLINK_C11_READY
 
- VIA_ACLINK_CTRL
 
- VIA_ACLINK_CTRL_ENABLE
 
- VIA_ACLINK_CTRL_FM
 
- VIA_ACLINK_CTRL_INIT
 
- VIA_ACLINK_CTRL_PCM
 
- VIA_ACLINK_CTRL_RESET
 
- VIA_ACLINK_CTRL_SB
 
- VIA_ACLINK_CTRL_SDO
 
- VIA_ACLINK_CTRL_SYNC
 
- VIA_ACLINK_CTRL_VRA
 
- VIA_ACLINK_LOWPOWER
 
- VIA_ACLINK_STAT
 
- VIA_ADDRESS_SETUP
 
- VIA_AGP3_APSIZE
 
- VIA_AGP3_ATTBASE
 
- VIA_AGP3_GARTCTRL
 
- VIA_AGPSEL
 
- VIA_ALEN_ALIGN
 
- VIA_APSIZE
 
- VIA_ATTBASE
 
- VIA_BACK
 
- VIA_BAD_AST
 
- VIA_BAD_CLK66
 
- VIA_BAD_ID
 
- VIA_BAD_PREQ
 
- VIA_BITBLT_COLOR
 
- VIA_BITBLT_FILL
 
- VIA_BITBLT_MONO
 
- VIA_CLKSRC_CAP0
 
- VIA_CLKSRC_CAP1
 
- VIA_CLKSRC_DVP1TVCLKR
 
- VIA_CLKSRC_TVPLL
 
- VIA_CLKSRC_TVX1
 
- VIA_CLKSRC_X1
 
- VIA_CLOCK_FREQ
 
- VIA_CMD_RGTR_BUSY
 
- VIA_CMD_RGTR_BUSY_H5
 
- VIA_CMD_RGTR_BUSY_M1
 
- VIA_COBALT_BRD_ID_REG
 
- VIA_COBALT_BRD_REG_to_ID
 
- VIA_CONFIG_DATA
 
- VIA_CONFIG_INDEX
 
- VIA_CRDR_DDMA_OFF
 
- VIA_CRDR_DMABASEADD
 
- VIA_CRDR_DMACOUNTER
 
- VIA_CRDR_DMACTRL
 
- VIA_CRDR_DMACTRL_DIR
 
- VIA_CRDR_DMACTRL_ENIRQ
 
- VIA_CRDR_DMACTRL_SFTRST
 
- VIA_CRDR_DMASTART
 
- VIA_CRDR_DMASTS
 
- VIA_CRDR_MAX_BLOCK_COUNT
 
- VIA_CRDR_MAX_BLOCK_LENGTH
 
- VIA_CRDR_MAX_CLOCK
 
- VIA_CRDR_MIN_CLOCK
 
- VIA_CRDR_PCICLKGATT
 
- VIA_CRDR_PCICLKGATT_3V3
 
- VIA_CRDR_PCICLKGATT_PAD_PWRON
 
- VIA_CRDR_PCICLKGATT_SFTRST
 
- VIA_CRDR_PCICTRL_OFF
 
- VIA_CRDR_PCIDMACLK
 
- VIA_CRDR_PCIDMACLK_SDC
 
- VIA_CRDR_PCIINTCTRL
 
- VIA_CRDR_PCIINTCTRL_SDCIRQEN
 
- VIA_CRDR_PCIINTSTATUS
 
- VIA_CRDR_PCIINTSTATUS_SDC
 
- VIA_CRDR_PCISDCCLK
 
- VIA_CRDR_PCITMOCTRL
 
- VIA_CRDR_PCITMOCTRL_1024MS
 
- VIA_CRDR_PCITMOCTRL_1024US
 
- VIA_CRDR_PCITMOCTRL_256MS
 
- VIA_CRDR_PCITMOCTRL_256US
 
- VIA_CRDR_PCITMOCTRL_32US
 
- VIA_CRDR_PCITMOCTRL_512MS
 
- VIA_CRDR_PCITMOCTRL_NO
 
- VIA_CRDR_PCI_DBG_MODE
 
- VIA_CRDR_PCI_WORK_MODE
 
- VIA_CRDR_QUIRK_300MS_PWRDELAY
 
- VIA_CRDR_SDACTIVE_INTMASK
 
- VIA_CRDR_SDBLKLEN
 
- VIA_CRDR_SDBLKLEN_GPIDET
 
- VIA_CRDR_SDBLKLEN_INTEN
 
- VIA_CRDR_SDBUSMODE
 
- VIA_CRDR_SDCARG
 
- VIA_CRDR_SDCLKSEL
 
- VIA_CRDR_SDCTRL
 
- VIA_CRDR_SDCTRL_MULTI_RD
 
- VIA_CRDR_SDCTRL_MULTI_WR
 
- VIA_CRDR_SDCTRL_RSP_NONE
 
- VIA_CRDR_SDCTRL_RSP_R1
 
- VIA_CRDR_SDCTRL_RSP_R1B
 
- VIA_CRDR_SDCTRL_RSP_R2
 
- VIA_CRDR_SDCTRL_RSP_R3
 
- VIA_CRDR_SDCTRL_SINGLE_RD
 
- VIA_CRDR_SDCTRL_SINGLE_WR
 
- VIA_CRDR_SDCTRL_START
 
- VIA_CRDR_SDCTRL_STOP
 
- VIA_CRDR_SDCTRL_WRITE
 
- VIA_CRDR_SDCURBLKCNT
 
- VIA_CRDR_SDC_OFF
 
- VIA_CRDR_SDEXTCTRL
 
- VIA_CRDR_SDEXTCTRL_HISPD
 
- VIA_CRDR_SDINTMASK
 
- VIA_CRDR_SDINTMASK_ASCRDIE
 
- VIA_CRDR_SDINTMASK_BDDIE
 
- VIA_CRDR_SDINTMASK_CIRIE
 
- VIA_CRDR_SDINTMASK_CRDIE
 
- VIA_CRDR_SDINTMASK_CRTOIE
 
- VIA_CRDR_SDINTMASK_DTIE
 
- VIA_CRDR_SDINTMASK_MBDIE
 
- VIA_CRDR_SDINTMASK_RCIE
 
- VIA_CRDR_SDINTMASK_SCIE
 
- VIA_CRDR_SDINTMASK_WCIE
 
- VIA_CRDR_SDMODE_4BIT
 
- VIA_CRDR_SDMODE_CLK_ON
 
- VIA_CRDR_SDRESP0
 
- VIA_CRDR_SDRESP1
 
- VIA_CRDR_SDRESP2
 
- VIA_CRDR_SDRESP3
 
- VIA_CRDR_SDRSPTMO
 
- VIA_CRDR_SDSTATUS
 
- VIA_CRDR_SDSTATUS2
 
- VIA_CRDR_SDSTS_ASCRDIE
 
- VIA_CRDR_SDSTS_BDD
 
- VIA_CRDR_SDSTS_CD
 
- VIA_CRDR_SDSTS_CECC
 
- VIA_CRDR_SDSTS_CFE
 
- VIA_CRDR_SDSTS_CIR
 
- VIA_CRDR_SDSTS_CMD_MASK
 
- VIA_CRDR_SDSTS_CRD
 
- VIA_CRDR_SDSTS_CRTO
 
- VIA_CRDR_SDSTS_DATA_MASK
 
- VIA_CRDR_SDSTS_DT
 
- VIA_CRDR_SDSTS_IGN_MASK
 
- VIA_CRDR_SDSTS_INT_MASK
 
- VIA_CRDR_SDSTS_IO
 
- VIA_CRDR_SDSTS_MBD
 
- VIA_CRDR_SDSTS_RC
 
- VIA_CRDR_SDSTS_SC
 
- VIA_CRDR_SDSTS_SLOTD
 
- VIA_CRDR_SDSTS_SLOTG
 
- VIA_CRDR_SDSTS_W1C_MASK
 
- VIA_CRDR_SDSTS_WC
 
- VIA_CRDR_SDSTS_WP
 
- VIA_CRT
 
- VIA_DEPTH
 
- VIA_DMACONTROL_PARALLEL
 
- VIA_DMA_CSR_DD
 
- VIA_DMA_CSR_DE
 
- VIA_DMA_CSR_TA
 
- VIA_DMA_CSR_TD
 
- VIA_DMA_CSR_TS
 
- VIA_DMA_DPR_DDIE
 
- VIA_DMA_DPR_DT
 
- VIA_DMA_DPR_EC
 
- VIA_DMA_MR_CM
 
- VIA_DMA_MR_HENDMACMD
 
- VIA_DMA_MR_TDIE
 
- VIA_DRIVE_TIMING
 
- VIA_DVP0
 
- VIA_DVP1
 
- VIA_DX9_0
 
- VIA_DXS_48K
 
- VIA_DXS_AUTO
 
- VIA_DXS_DISABLE
 
- VIA_DXS_ENABLE
 
- VIA_DXS_MAX_VOLUME
 
- VIA_DXS_NO_VRA
 
- VIA_DXS_SRC
 
- VIA_FIFO_CONFIG
 
- VIA_FIRE_BUF_SIZE
 
- VIA_FIXUP_ASUS_G75
 
- VIA_FIXUP_INTMIC_BOOST
 
- VIA_FM_NMI_CTRL
 
- VIA_FRONT
 
- VIA_FUNCTION_PARPORT_DISABLE
 
- VIA_FUNCTION_PARPORT_ECP
 
- VIA_FUNCTION_PARPORT_EPP
 
- VIA_FUNCTION_PARPORT_SPP
 
- VIA_FUNCTION_PROBE
 
- VIA_FUNC_ENABLE
 
- VIA_FUNC_ENABLE_FM
 
- VIA_FUNC_ENABLE_GAME
 
- VIA_FUNC_ENABLE_MIDI
 
- VIA_FUNC_ENABLE_SB
 
- VIA_FUNC_MIDI_IRQMASK
 
- VIA_FUNC_MIDI_PNP
 
- VIA_FUNC_RX2C_WRITE
 
- VIA_FUNC_SB_FIFO_EMPTY
 
- VIA_GARTCTRL
 
- VIA_GEC_BLT
 
- VIA_GEC_CLIP_DISABLE
 
- VIA_GEC_CLIP_ENABLE
 
- VIA_GEC_DECX
 
- VIA_GEC_DECY
 
- VIA_GEC_DST_FB
 
- VIA_GEC_DST_LINRAT
 
- VIA_GEC_DST_SYS
 
- VIA_GEC_DST_XY
 
- VIA_GEC_FIXCOLOR_PAT
 
- VIA_GEC_INCX
 
- VIA_GEC_INCY
 
- VIA_GEC_LASTPIXEL_OFF
 
- VIA_GEC_LASTPIXEL_ON
 
- VIA_GEC_LINE
 
- VIA_GEC_MONO_BYTE
 
- VIA_GEC_MONO_DWORD
 
- VIA_GEC_MONO_PACK
 
- VIA_GEC_MONO_UNPACK
 
- VIA_GEC_MONO_WORD
 
- VIA_GEC_MPAT_OPAQUE
 
- VIA_GEC_MPAT_TRANS
 
- VIA_GEC_MSRC_OPAQUE
 
- VIA_GEC_MSRC_TRANS
 
- VIA_GEC_NOOP
 
- VIA_GEC_PAT_FB
 
- VIA_GEC_PAT_MONO
 
- VIA_GEC_PAT_REG
 
- VIA_GEC_QUICK_START
 
- VIA_GEC_ROT
 
- VIA_GEC_SRC_FB
 
- VIA_GEC_SRC_LINEAR
 
- VIA_GEC_SRC_MONO
 
- VIA_GEC_SRC_SYS
 
- VIA_GEC_SRC_XY
 
- VIA_GEC_X_MAJOR
 
- VIA_GEC_Y_MAJOR
 
- VIA_GEM_16bpp
 
- VIA_GEM_32bpp
 
- VIA_GEM_8bpp
 
- VIA_HDAC_DEVICE_ID
 
- VIA_HDA_CODEC
 
- VIA_HSYNC_NEGATIVE
 
- VIA_IDE_CONFIG
 
- VIA_IDE_ENABLE
 
- VIA_IDFLAG_SINGLE
 
- VIA_IRQCONTROL_PARALLEL
 
- VIA_IRQ_ABSOLUTE
 
- VIA_IRQ_DMA0_DD_ENABLE
 
- VIA_IRQ_DMA0_DD_PENDING
 
- VIA_IRQ_DMA0_TD_ENABLE
 
- VIA_IRQ_DMA0_TD_PENDING
 
- VIA_IRQ_DMA1_DD_ENABLE
 
- VIA_IRQ_DMA1_DD_PENDING
 
- VIA_IRQ_DMA1_TD_ENABLE
 
- VIA_IRQ_DMA1_TD_PENDING
 
- VIA_IRQ_FLAGS_MASK
 
- VIA_IRQ_FORCE_SEQUENCE
 
- VIA_IRQ_GLOBAL
 
- VIA_IRQ_HQV0_ENABLE
 
- VIA_IRQ_HQV0_PENDING
 
- VIA_IRQ_HQV1_ENABLE
 
- VIA_IRQ_HQV1_PENDING
 
- VIA_IRQ_RELATIVE
 
- VIA_IRQ_SIGNAL
 
- VIA_IRQ_VBLANK_ENABLE
 
- VIA_IRQ_VBLANK_PENDING
 
- VIA_LDVP0
 
- VIA_LDVP1
 
- VIA_LOG_MIN_TEX_REGION_SIZE
 
- VIA_LVDS1
 
- VIA_LVDS2
 
- VIA_MAX_BUFSIZE
 
- VIA_MAX_CACHELINE_SIZE
 
- VIA_MAX_DEVS
 
- VIA_MAX_MODEM_DEVS
 
- VIA_MC97_CTRL
 
- VIA_MC97_CTRL_ENABLE
 
- VIA_MC97_CTRL_INIT
 
- VIA_MC97_CTRL_SECONDARY
 
- VIA_MEM_AGP
 
- VIA_MEM_MIXED
 
- VIA_MEM_SYSTEM
 
- VIA_MEM_UNKNOWN
 
- VIA_MEM_VIDEO
 
- VIA_MISC_1
 
- VIA_MISC_2
 
- VIA_MISC_3
 
- VIA_MISC_REG_READ
 
- VIA_MISC_REG_WRITE
 
- VIA_MMIO_BLTBASE
 
- VIA_MMIO_BLTSIZE
 
- VIA_MM_ALIGN_MASK
 
- VIA_MM_ALIGN_SHIFT
 
- VIA_MODE_GPIO
 
- VIA_MODE_I2C
 
- VIA_MODE_OFF
 
- VIA_NOISESRC1
 
- VIA_NOISESRC2
 
- VIA_NO_ENABLES
 
- VIA_NO_UNMASK
 
- VIA_NR_SAREA_CLIPRECTS
 
- VIA_NR_TEX_REGIONS
 
- VIA_NR_XVMC_LOCKS
 
- VIA_NR_XVMC_PORTS
 
- VIA_NUM_BLIT_ENGINES
 
- VIA_NUM_BLIT_SLOTS
 
- VIA_NUM_IRQS
 
- VIA_OTHER
 
- VIA_OUT_RING_QW
 
- VIA_PARPORT_BIDIR
 
- VIA_PARPORT_ECPEPP
 
- VIA_PCI_BUF_SIZE
 
- VIA_PCI_DMA_BCR0
 
- VIA_PCI_DMA_BCR1
 
- VIA_PCI_DMA_BCR2
 
- VIA_PCI_DMA_BCR3
 
- VIA_PCI_DMA_CSR0
 
- VIA_PCI_DMA_CSR1
 
- VIA_PCI_DMA_CSR2
 
- VIA_PCI_DMA_CSR3
 
- VIA_PCI_DMA_DAR0
 
- VIA_PCI_DMA_DAR1
 
- VIA_PCI_DMA_DAR2
 
- VIA_PCI_DMA_DAR3
 
- VIA_PCI_DMA_DPR0
 
- VIA_PCI_DMA_DPR1
 
- VIA_PCI_DMA_DPR2
 
- VIA_PCI_DMA_DPR3
 
- VIA_PCI_DMA_MAR0
 
- VIA_PCI_DMA_MAR1
 
- VIA_PCI_DMA_MAR2
 
- VIA_PCI_DMA_MAR3
 
- VIA_PCI_DMA_MR0
 
- VIA_PCI_DMA_MR1
 
- VIA_PCI_DMA_MR2
 
- VIA_PCI_DMA_MR3
 
- VIA_PCI_DMA_PTR
 
- VIA_PFN
 
- VIA_PGDN
 
- VIA_PGOFF
 
- VIA_PITCH_ENABLE
 
- VIA_PITCH_MAX
 
- VIA_PITCH_SIZE
 
- VIA_PNP_CONTROL
 
- VIA_PORT_25
 
- VIA_PORT_26
 
- VIA_PORT_2C
 
- VIA_PORT_31
 
- VIA_PORT_3D
 
- VIA_PORT_GPIO
 
- VIA_PORT_I2C
 
- VIA_PORT_NONE
 
- VIA_PRO_GROUP_A
 
- VIA_RAWBITS_ENABLE
 
- VIA_REG_
 
- VIA_REG_AC97
 
- VIA_REG_AC97_BUSY
 
- VIA_REG_AC97_CMD_MASK
 
- VIA_REG_AC97_CMD_SHIFT
 
- VIA_REG_AC97_CODEC_ID_MASK
 
- VIA_REG_AC97_CODEC_ID_PRIMARY
 
- VIA_REG_AC97_CODEC_ID_SECONDARY
 
- VIA_REG_AC97_CODEC_ID_SHIFT
 
- VIA_REG_AC97_DATA_MASK
 
- VIA_REG_AC97_DATA_SHIFT
 
- VIA_REG_AC97_PRIMARY_VALID
 
- VIA_REG_AC97_READ
 
- VIA_REG_AC97_SECONDARY_VALID
 
- VIA_REG_BGCOLOR
 
- VIA_REG_BGCOLOR_M1
 
- VIA_REG_CAPTURE_CHANNEL
 
- VIA_REG_CAPTURE_CHANNEL_LINE
 
- VIA_REG_CAPTURE_CHANNEL_MIC
 
- VIA_REG_CAPTURE_FIFO_ENABLE
 
- VIA_REG_CAPTURE_SELECT_CODEC
 
- VIA_REG_CLIPBR
 
- VIA_REG_CLIPBR_M1
 
- VIA_REG_CLIPTL
 
- VIA_REG_CLIPTL_M1
 
- VIA_REG_COLORPAT
 
- VIA_REG_COLORPAT_M1
 
- VIA_REG_CR_TRANSET
 
- VIA_REG_CR_TRANSPACE
 
- VIA_REG_CTRL_AUTOSTART
 
- VIA_REG_CTRL_INT
 
- VIA_REG_CTRL_INT_EOL
 
- VIA_REG_CTRL_INT_FLAG
 
- VIA_REG_CTRL_INT_STOP
 
- VIA_REG_CTRL_PAUSE
 
- VIA_REG_CTRL_RESET
 
- VIA_REG_CTRL_START
 
- VIA_REG_CTRL_TERMINATE
 
- VIA_REG_CURSOR_BG
 
- VIA_REG_CURSOR_FG
 
- VIA_REG_CURSOR_MODE
 
- VIA_REG_CURSOR_ORG
 
- VIA_REG_CURSOR_POS
 
- VIA_REG_DIMENSION
 
- VIA_REG_DIMENSION_M1
 
- VIA_REG_DSTBASE
 
- VIA_REG_DSTBASE_M1
 
- VIA_REG_DSTCOLORKEY_M1
 
- VIA_REG_DSTPOS
 
- VIA_REG_DSTPOS_M1
 
- VIA_REG_FGCOLOR
 
- VIA_REG_FGCOLOR_M1
 
- VIA_REG_GECMD
 
- VIA_REG_GECMD_M1
 
- VIA_REG_GEMODE
 
- VIA_REG_GEMODE_M1
 
- VIA_REG_GESTATUS_M1
 
- VIA_REG_GPI_INTR
 
- VIA_REG_GPI_STATUS
 
- VIA_REG_INTERRUPT
 
- VIA_REG_KEYCONTROL
 
- VIA_REG_KEYCONTROL_M1
 
- VIA_REG_LINE_ERROR_M1
 
- VIA_REG_LINE_K1K2_M1
 
- VIA_REG_LINE_XY_M1
 
- VIA_REG_MONOPAT0
 
- VIA_REG_MONOPAT0_M1
 
- VIA_REG_MONOPAT1
 
- VIA_REG_MONOPAT1_M1
 
- VIA_REG_MONOPATBGC_M1
 
- VIA_REG_MONOPATFGC_M1
 
- VIA_REG_MULTPLAY_FMT_16BIT
 
- VIA_REG_MULTPLAY_FMT_8BIT
 
- VIA_REG_MULTPLAY_FMT_CH_MASK
 
- VIA_REG_OFFSET
 
- VIA_REG_OFFSET_CONTROL
 
- VIA_REG_OFFSET_CURR_COUNT
 
- VIA_REG_OFFSET_CURR_INDEX
 
- VIA_REG_OFFSET_CURR_PTR
 
- VIA_REG_OFFSET_M1
 
- VIA_REG_OFFSET_STATUS
 
- VIA_REG_OFFSET_STOP_IDX
 
- VIA_REG_OFFSET_TABLE_PTR
 
- VIA_REG_OFFSET_TYPE
 
- VIA_REG_OFS_CAPTURE_FIFO
 
- VIA_REG_OFS_MULTPLAY_FORMAT
 
- VIA_REG_OFS_PLAYBACK_VOLUME_L
 
- VIA_REG_OFS_PLAYBACK_VOLUME_R
 
- VIA_REG_PATADDR
 
- VIA_REG_PATADDR_M1
 
- VIA_REG_PITCH
 
- VIA_REG_PITCH_M1
 
- VIA_REG_SGD_SHADOW
 
- VIA_REG_SGD_STAT_CP_ACTIVE
 
- VIA_REG_SGD_STAT_CP_EOL
 
- VIA_REG_SGD_STAT_CP_FLAG
 
- VIA_REG_SGD_STAT_CP_STOP
 
- VIA_REG_SGD_STAT_FM_ACTIVE
 
- VIA_REG_SGD_STAT_FM_EOL
 
- VIA_REG_SGD_STAT_FM_FLAG
 
- VIA_REG_SGD_STAT_FM_STOP
 
- VIA_REG_SGD_STAT_MR_ACTIVE
 
- VIA_REG_SGD_STAT_MR_EOL
 
- VIA_REG_SGD_STAT_MR_FLAG
 
- VIA_REG_SGD_STAT_MR_STOP
 
- VIA_REG_SGD_STAT_MW_ACTIVE
 
- VIA_REG_SGD_STAT_MW_EOL
 
- VIA_REG_SGD_STAT_MW_FLAG
 
- VIA_REG_SGD_STAT_MW_STOP
 
- VIA_REG_SGD_STAT_PB_ACTIVE
 
- VIA_REG_SGD_STAT_PB_EOL
 
- VIA_REG_SGD_STAT_PB_FLAG
 
- VIA_REG_SGD_STAT_PB_STOP
 
- VIA_REG_SRCBASE
 
- VIA_REG_SRCBASE_M1
 
- VIA_REG_SRCCOLORKEY_M1
 
- VIA_REG_SRCPOS
 
- VIA_REG_SRCPOS_M1
 
- VIA_REG_STATUS
 
- VIA_REG_STAT_ACTIVE
 
- VIA_REG_STAT_EOL
 
- VIA_REG_STAT_FLAG
 
- VIA_REG_STAT_PAUSED
 
- VIA_REG_STAT_STOPPED
 
- VIA_REG_STAT_TRIGGER_QUEUED
 
- VIA_REG_TRANSET
 
- VIA_REG_TRANSPACE
 
- VIA_REG_TYPE_16BIT
 
- VIA_REG_TYPE_AUTOSTART
 
- VIA_REG_TYPE_INT_EOL
 
- VIA_REG_TYPE_INT_FLAG
 
- VIA_REG_TYPE_INT_LESSONE
 
- VIA_REG_TYPE_INT_LLINE
 
- VIA_REG_TYPE_INT_LSAMPLE
 
- VIA_REG_TYPE_INT_MASK
 
- VIA_REG_TYPE_STEREO
 
- VIA_REV_686_A
 
- VIA_REV_686_B
 
- VIA_REV_686_C
 
- VIA_REV_686_D
 
- VIA_REV_686_E
 
- VIA_REV_686_H
 
- VIA_REV_8233
 
- VIA_REV_8233A
 
- VIA_REV_8233C
 
- VIA_REV_8235
 
- VIA_REV_8237
 
- VIA_REV_8251
 
- VIA_REV_PRE_8233
 
- VIA_RNG_CHUNK_1
 
- VIA_RNG_CHUNK_1_MASK
 
- VIA_RNG_CHUNK_2
 
- VIA_RNG_CHUNK_2_MASK
 
- VIA_RNG_CHUNK_4
 
- VIA_RNG_CHUNK_4_MASK
 
- VIA_RNG_CHUNK_8
 
- VIA_RNG_ENABLE
 
- VIA_SATA_PATA
 
- VIA_SET_FIFO
 
- VIA_STATE_OFF
 
- VIA_STATE_ON
 
- VIA_STATE_STANDBY
 
- VIA_STATE_SUSPEND
 
- VIA_STENCIL
 
- VIA_STRFILT_CNT_SHIFT
 
- VIA_STRFILT_ENABLE
 
- VIA_STRFILT_FAIL
 
- VIA_TABLE_SIZE
 
- VIA_TBL_BIT_EOL
 
- VIA_TBL_BIT_FLAG
 
- VIA_TC
 
- VIA_TC_HIGH
 
- VIA_TC_LOW
 
- VIA_TEX_SETUP_SIZE
 
- VIA_TIMER_1_INT
 
- VIA_TIMER_CYCLES
 
- VIA_TIMER_FREQ_6
 
- VIA_UDMA_TIMING
 
- VIA_UPLOAD_ALL
 
- VIA_UPLOAD_BUFFERS
 
- VIA_UPLOAD_CLIPRECTS
 
- VIA_UPLOAD_CTX
 
- VIA_UPLOAD_TEX0
 
- VIA_UPLOAD_TEX0IMAGE
 
- VIA_UPLOAD_TEX1
 
- VIA_UPLOAD_TEX1IMAGE
 
- VIA_VIDEOMASK
 
- VIA_VIDEO_HEADER5
 
- VIA_VIDEO_HEADER6
 
- VIA_VIDEO_HEADER7
 
- VIA_VR_QUEUE_BUSY
 
- VIA_VR_QUEUE_BUSY_H5
 
- VIA_VR_QUEUE_BUSY_M1
 
- VIA_VSYNC_NEGATIVE
 
- VIA_WAIT_ON
 
- VIA_WDT_CONF
 
- VIA_WDT_CONF_ENABLE
 
- VIA_WDT_CONF_MMIO
 
- VIA_WDT_COUNT
 
- VIA_WDT_CTL
 
- VIA_WDT_DISABLED
 
- VIA_WDT_FIRED
 
- VIA_WDT_MMIO_BASE
 
- VIA_WDT_MMIO_LEN
 
- VIA_WDT_PWROFF
 
- VIA_WDT_RUNNING
 
- VIA_WDT_TRIGGER
 
- VIA_XSTORE_CNT_MASK
 
- VIAdmTime
 
- VIBRACTRL_MEMBER
 
- VIB_MAX_LEVELS
 
- VIB_MAX_LEVEL_mV
 
- VIB_MIN_LEVEL_mV
 
- VICAM_FIRMWARE
 
- VICODEC_NAME
 
- VICSTATST_UIF_INDEX
 
- VICTIM
 
- VICTIM_MASK
 
- VICTIM_SHIFT
 
- VIC_FEATURE_MAX
 
- VIC_FEATURE_RDMA
 
- VIC_FEATURE_VXLAN
 
- VIC_FEATURE_VXLAN_PATCH
 
- VIC_FIQ_STATUS
 
- VIC_GENERIC_PROV_OS_TYPE_ESX
 
- VIC_GENERIC_PROV_OS_TYPE_LINUX
 
- VIC_GENERIC_PROV_OS_TYPE_SOLARIS
 
- VIC_GENERIC_PROV_OS_TYPE_UNKNOWN
 
- VIC_GENERIC_PROV_OS_TYPE_WINDOWS
 
- VIC_GENERIC_PROV_TLV_CLIENT_MAC_ADDR
 
- VIC_GENERIC_PROV_TLV_CLIENT_NAME_STR
 
- VIC_GENERIC_PROV_TLV_CLIENT_TYPE
 
- VIC_GENERIC_PROV_TLV_CLIENT_UUID_STR
 
- VIC_GENERIC_PROV_TLV_CLUSTER_NAME_STR
 
- VIC_GENERIC_PROV_TLV_CLUSTER_PORT_NAME_STR
 
- VIC_GENERIC_PROV_TLV_CLUSTER_PORT_UUID_STR
 
- VIC_GENERIC_PROV_TLV_CLUSTER_UUID_STR
 
- VIC_GENERIC_PROV_TLV_HOST_UUID_STR
 
- VIC_GENERIC_PROV_TLV_INCARNATION_NUMBER
 
- VIC_GENERIC_PROV_TLV_OS_TYPE
 
- VIC_GENERIC_PROV_TLV_OS_VENDOR
 
- VIC_GENERIC_PROV_TLV_PORT_PROFILE_NAME_STR
 
- VIC_INT_ENABLE
 
- VIC_INT_ENABLE_CLEAR
 
- VIC_INT_SELECT
 
- VIC_INT_SOFT
 
- VIC_INT_SOFT_CLEAR
 
- VIC_IRQ_STATUS
 
- VIC_ITCR
 
- VIC_PL190_DEF_VECT_ADDR
 
- VIC_PL190_VECT_ADDR
 
- VIC_PL192_VECT_ADDR
 
- VIC_PROTECT
 
- VIC_PROVINFO_ADD_TLV
 
- VIC_PROVINFO_CISCO_OUI
 
- VIC_PROVINFO_GENERIC_TYPE
 
- VIC_PROVINFO_MAX_DATA
 
- VIC_PROVINFO_MAX_TLV_DATA
 
- VIC_RAW_STATUS
 
- VIC_SET_APPLICATION_ID
 
- VIC_SET_FCE_UCODE_OFFSET
 
- VIC_SET_FCE_UCODE_SIZE
 
- VIC_TFBIF_TRANSCFG
 
- VIC_THI_STREAMID0
 
- VIC_THI_STREAMID1
 
- VIC_UCODE_FCE_DATA_OFFSET
 
- VIC_UCODE_FCE_HEADER_OFFSET
 
- VIC_VECT_ADDR0
 
- VIC_VECT_CNTL0
 
- VIC_VECT_CNTL_ENABLE
 
- VID
 
- VIDC20_CTRL
 
- VIDC20_CTRL_16BPP
 
- VIDC20_CTRL_1BPP
 
- VIDC20_CTRL_2BPP
 
- VIDC20_CTRL_32BPP
 
- VIDC20_CTRL_4BPP
 
- VIDC20_CTRL_8BPP
 
- VIDC20_CTRL_DUP
 
- VIDC20_CTRL_FIFO_12
 
- VIDC20_CTRL_FIFO_16
 
- VIDC20_CTRL_FIFO_20
 
- VIDC20_CTRL_FIFO_24
 
- VIDC20_CTRL_FIFO_28
 
- VIDC20_CTRL_FIFO_4
 
- VIDC20_CTRL_FIFO_8
 
- VIDC20_CTRL_FIFO_NS
 
- VIDC20_CTRL_INT
 
- VIDC20_CTRL_PDOWN
 
- VIDC20_CTRL_PIX_CK
 
- VIDC20_CTRL_PIX_CK2
 
- VIDC20_CTRL_PIX_CK3
 
- VIDC20_CTRL_PIX_CK4
 
- VIDC20_CTRL_PIX_CK5
 
- VIDC20_CTRL_PIX_CK6
 
- VIDC20_CTRL_PIX_CK7
 
- VIDC20_CTRL_PIX_CK8
 
- VIDC20_CTRL_PIX_HCLK
 
- VIDC20_CTRL_PIX_RCLK
 
- VIDC20_CTRL_PIX_VCLK
 
- VIDC20_DCTL
 
- VIDC20_DCTL_BUS_D31_0
 
- VIDC20_DCTL_BUS_D63_0
 
- VIDC20_DCTL_BUS_D63_32
 
- VIDC20_DCTL_BUS_NS
 
- VIDC20_DCTL_HDIS
 
- VIDC20_DCTL_SNA
 
- VIDC20_DCTL_VRAM_DIS
 
- VIDC20_DCTL_VRAM_PXCLK
 
- VIDC20_DCTL_VRAM_PXCLK2
 
- VIDC20_DCTL_VRAM_PXCLK4
 
- VIDC20_ECTL
 
- VIDC20_ECTL_BLUEPED
 
- VIDC20_ECTL_DAC
 
- VIDC20_ECTL_ECK
 
- VIDC20_ECTL_GREENPED
 
- VIDC20_ECTL_HRM
 
- VIDC20_ECTL_HS_CSYNC
 
- VIDC20_ECTL_HS_HSYNC
 
- VIDC20_ECTL_HS_MASK
 
- VIDC20_ECTL_HS_NCSYNC
 
- VIDC20_ECTL_HS_NHSYNC
 
- VIDC20_ECTL_LCDGS
 
- VIDC20_ECTL_REDPED
 
- VIDC20_ECTL_REG
 
- VIDC20_ECTL_VS_CSYNC
 
- VIDC20_ECTL_VS_MASK
 
- VIDC20_ECTL_VS_NCSYNC
 
- VIDC20_ECTL_VS_NVSYNC
 
- VIDC20_ECTL_VS_VSYNC
 
- VIDCFG_2X
 
- VIDCFG_CLUT_BYPASS
 
- VIDCFG_CURS_X11
 
- VIDCFG_DESK_ENABLE
 
- VIDCFG_HALF_MODE
 
- VIDCFG_HWCURSOR_ENABLE
 
- VIDCFG_INTERLACE
 
- VIDCFG_PIXFMT_SHIFT
 
- VIDCFG_VIDPROC_ENABLE
 
- VIDCH1CLK
 
- VIDCH2CLK
 
- VIDCH3CLK
 
- VIDCHRMAX
 
- VIDCHRMIN
 
- VIDCON0
 
- VIDCON0_CLKDIR
 
- VIDCON0_CLKSEL_27M
 
- VIDCON0_CLKSEL_HCLK
 
- VIDCON0_CLKSEL_LCD
 
- VIDCON0_CLKSEL_MASK
 
- VIDCON0_CLKSEL_SHIFT
 
- VIDCON0_CLKVALUP
 
- VIDCON0_CLKVAL_F
 
- VIDCON0_CLKVAL_F_LIMIT
 
- VIDCON0_CLKVAL_F_MASK
 
- VIDCON0_CLKVAL_F_SHIFT
 
- VIDCON0_DECON_STOP_STATUS
 
- VIDCON0_DSI_EN
 
- VIDCON0_ENVID
 
- VIDCON0_ENVID_F
 
- VIDCON0_INTERLACE
 
- VIDCON0_L0_DATA_16BPP
 
- VIDCON0_L0_DATA_16BPP8
 
- VIDCON0_L0_DATA_18BPP
 
- VIDCON0_L0_DATA_18BPP16
 
- VIDCON0_L0_DATA_18BPP9
 
- VIDCON0_L0_DATA_24BPP
 
- VIDCON0_L0_DATA_MASK
 
- VIDCON0_L0_DATA_SHIFT
 
- VIDCON0_L1_DATA_16BPP
 
- VIDCON0_L1_DATA_16BPP8
 
- VIDCON0_L1_DATA_18BPP
 
- VIDCON0_L1_DATA_18BPP16
 
- VIDCON0_L1_DATA_18BPP9
 
- VIDCON0_L1_DATA_24BPP
 
- VIDCON0_L1_DATA_MASK
 
- VIDCON0_L1_DATA_SHIFT
 
- VIDCON0_PNRMODE_BGR
 
- VIDCON0_PNRMODE_MASK
 
- VIDCON0_PNRMODE_RGB
 
- VIDCON0_PNRMODE_SERIAL_BGR
 
- VIDCON0_PNRMODE_SERIAL_RGB
 
- VIDCON0_PNRMODE_SHIFT
 
- VIDCON0_STOP_STATUS
 
- VIDCON0_SWRESET
 
- VIDCON0_VIDOUT_I80_LDI0
 
- VIDCON0_VIDOUT_I80_LDI1
 
- VIDCON0_VIDOUT_MASK
 
- VIDCON0_VIDOUT_RGB
 
- VIDCON0_VIDOUT_SHIFT
 
- VIDCON0_VIDOUT_TV
 
- VIDCON0_VIDOUT_WB_I80_LDI0
 
- VIDCON0_VIDOUT_WB_I80_LDI1
 
- VIDCON0_VIDOUT_WB_RGB
 
- VIDCON0_VLCKFREE
 
- VIDCON1
 
- VIDCON1_FSTATUS_EVEN
 
- VIDCON1_I80_ACTIVE
 
- VIDCON1_INV_HSYNC
 
- VIDCON1_INV_VCLK
 
- VIDCON1_INV_VDEN
 
- VIDCON1_INV_VSYNC
 
- VIDCON1_LINECNT_GET
 
- VIDCON1_LINECNT_MASK
 
- VIDCON1_LINECNT_SHIFT
 
- VIDCON1_RGB_ORDER_O_BGR
 
- VIDCON1_RGB_ORDER_O_BRG
 
- VIDCON1_RGB_ORDER_O_GBR
 
- VIDCON1_RGB_ORDER_O_GRB
 
- VIDCON1_RGB_ORDER_O_MASK
 
- VIDCON1_RGB_ORDER_O_RBG
 
- VIDCON1_RGB_ORDER_O_RGB
 
- VIDCON1_VCLK_HOLD
 
- VIDCON1_VCLK_MASK
 
- VIDCON1_VCLK_RUN
 
- VIDCON1_VCLK_RUN_VDEN_DISABLE
 
- VIDCON1_VSTATUS_AC
 
- VIDCON1_VSTATUS_ACTIVE
 
- VIDCON1_VSTATUS_BACKPORCH
 
- VIDCON1_VSTATUS_BP
 
- VIDCON1_VSTATUS_FP
 
- VIDCON1_VSTATUS_FRONTPORCH
 
- VIDCON1_VSTATUS_MASK
 
- VIDCON1_VSTATUS_SHIFT
 
- VIDCON1_VSTATUS_VS
 
- VIDCON1_VSTATUS_VSYNC
 
- VIDCON2
 
- VIDCON2_EN601
 
- VIDCON2_ORGYCbCr
 
- VIDCON2_TVFMTSEL1_MASK
 
- VIDCON2_TVFMTSEL1_RGB
 
- VIDCON2_TVFMTSEL1_SHIFT
 
- VIDCON2_TVFMTSEL1_YUV422
 
- VIDCON2_TVFMTSEL1_YUV444
 
- VIDCON2_TVFMTSEL_SW
 
- VIDCON2_YUVORDCrCb
 
- VIDCON3
 
- VIDCON4
 
- VIDCON4_FIFOCNT_START_EN
 
- VIDCTL
 
- VIDCURLIN
 
- VIDCUROVRSTART
 
- VIDC_BASE
 
- VIDC_CLKS_NUM_MAX
 
- VIDC_CORE_ID_1
 
- VIDC_CORE_ID_2
 
- VIDC_CORE_ID_3
 
- VIDC_CORE_ID_DEFAULT
 
- VIDC_CTRL_INIT
 
- VIDC_CTRL_INIT_CTRL_MASK
 
- VIDC_CTRL_INIT_CTRL_SHIFT
 
- VIDC_CTRL_INIT_RESERVED_BITS31_1_MASK
 
- VIDC_CTRL_INIT_RESERVED_BITS31_1_SHIFT
 
- VIDC_NAME
 
- VIDC_PALETTE_SIZE
 
- VIDC_RESOURCE_NONE
 
- VIDC_RESOURCE_OCMEM
 
- VIDC_RESOURCE_VMEM
 
- VIDC_SESSION_TYPE_DEC
 
- VIDC_SESSION_TYPE_ENC
 
- VIDC_SESSION_TYPE_VPE
 
- VIDC_WORK_MODE_1
 
- VIDC_WORK_MODE_2
 
- VIDDESKSTART
 
- VIDDESKSTRIDE
 
- VIDEL
 
- VIDEL_BAS
 
- VIDEL_PALETTE
 
- VIDEO
 
- VIDEO0_IN
 
- VIDEO0_PLL
 
- VIDEO1_IN
 
- VIDEO1_PLL
 
- VIDEO2_IN
 
- VIDEO2_PLL
 
- VIDEOBUF_ACTIVE
 
- VIDEOBUF_DONE
 
- VIDEOBUF_ERROR
 
- VIDEOBUF_IDLE
 
- VIDEOBUF_NEEDS_INIT
 
- VIDEOBUF_PREPARED
 
- VIDEOBUF_QUEUED
 
- VIDEODIMENSIONS
 
- VIDEOMEMBASE
 
- VIDEOMEMMASK
 
- VIDEOMEMSIZE
 
- VIDEOMEMSIZE_AGA_1M
 
- VIDEOMEMSIZE_AGA_2M
 
- VIDEOMEMSIZE_ECS_1M
 
- VIDEOMEMSIZE_ECS_2M
 
- VIDEOMEMSIZE_OCS
 
- VIDEOOFFSET
 
- VIDEOSIZE_192_144
 
- VIDEOSIZE_224_168
 
- VIDEOSIZE_256_192
 
- VIDEOSIZE_288_216
 
- VIDEOSIZE_CIF
 
- VIDEOSIZE_QCIF
 
- VIDEOSIZE_QVGA
 
- VIDEOSIZE_VGA
 
- VIDEO_80x25
 
- VIDEO_80x28
 
- VIDEO_80x30
 
- VIDEO_80x34
 
- VIDEO_80x43
 
- VIDEO_80x60
 
- VIDEO_8POINT
 
- VIDEO_AHB_CLK
 
- VIDEO_ALPHA_CHROMA_KEY
 
- VIDEO_ALPHA_CHROMA_KEY_MASK_MASK
 
- VIDEO_ALPHA_CHROMA_KEY_VALUE_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_01
 
- VIDEO_ALPHA_COLOR_LOOKUP_01_0_BLUE_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_01_0_GREEN_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_01_0_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_01_0_RED_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_01_1_BLUE_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_01_1_GREEN_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_01_1_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_01_1_RED_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_23
 
- VIDEO_ALPHA_COLOR_LOOKUP_23_2_BLUE_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_23_2_GREEN_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_23_2_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_23_2_RED_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_23_3_BLUE_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_23_3_GREEN_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_23_3_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_23_3_RED_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_45
 
- VIDEO_ALPHA_COLOR_LOOKUP_45_4_BLUE_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_45_4_GREEN_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_45_4_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_45_4_RED_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_45_5_BLUE_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_45_5_GREEN_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_45_5_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_45_5_RED_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_67
 
- VIDEO_ALPHA_COLOR_LOOKUP_67_6_BLUE_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_67_6_GREEN_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_67_6_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_67_6_RED_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_67_7_BLUE_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_67_7_GREEN_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_67_7_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_67_7_RED_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_89
 
- VIDEO_ALPHA_COLOR_LOOKUP_89_8_BLUE_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_89_8_GREEN_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_89_8_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_89_8_RED_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_89_9_BLUE_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_89_9_GREEN_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_89_9_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_89_9_RED_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_AB
 
- VIDEO_ALPHA_COLOR_LOOKUP_AB_A_BLUE_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_AB_A_GREEN_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_AB_A_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_AB_A_RED_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_AB_B_BLUE_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_AB_B_GREEN_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_AB_B_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_AB_B_RED_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_CD
 
- VIDEO_ALPHA_COLOR_LOOKUP_CD_C_BLUE_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_CD_C_GREEN_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_CD_C_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_CD_C_RED_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_CD_D_BLUE_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_CD_D_GREEN_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_CD_D_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_CD_D_RED_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_EF
 
- VIDEO_ALPHA_COLOR_LOOKUP_EF_E_BLUE_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_EF_E_GREEN_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_EF_E_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_EF_E_RED_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_EF_F_BLUE_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_EF_F_GREEN_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_EF_F_MASK
 
- VIDEO_ALPHA_COLOR_LOOKUP_EF_F_RED_MASK
 
- VIDEO_ALPHA_DISPLAY_CTRL
 
- VIDEO_ALPHA_DISPLAY_CTRL_ALPHA_MASK
 
- VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY
 
- VIDEO_ALPHA_DISPLAY_CTRL_FIFO_1
 
- VIDEO_ALPHA_DISPLAY_CTRL_FIFO_11
 
- VIDEO_ALPHA_DISPLAY_CTRL_FIFO_3
 
- VIDEO_ALPHA_DISPLAY_CTRL_FIFO_7
 
- VIDEO_ALPHA_DISPLAY_CTRL_FIFO_MASK
 
- VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_16
 
- VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_8
 
- VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4
 
- VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4_4_4
 
- VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_MASK
 
- VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE
 
- VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE
 
- VIDEO_ALPHA_DISPLAY_CTRL_PIXEL_MASK
 
- VIDEO_ALPHA_DISPLAY_CTRL_SELECT
 
- VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE
 
- VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE
 
- VIDEO_ALPHA_FB_ADDRESS
 
- VIDEO_ALPHA_FB_ADDRESS_ADDRESS_MASK
 
- VIDEO_ALPHA_FB_ADDRESS_EXT
 
- VIDEO_ALPHA_FB_ADDRESS_STATUS
 
- VIDEO_ALPHA_FB_LAST_ADDRESS
 
- VIDEO_ALPHA_FB_LAST_ADDRESS_ADDRESS_MASK
 
- VIDEO_ALPHA_FB_LAST_ADDRESS_EXT
 
- VIDEO_ALPHA_FB_WIDTH
 
- VIDEO_ALPHA_FB_WIDTH_OFFSET_MASK
 
- VIDEO_ALPHA_FB_WIDTH_WIDTH_MASK
 
- VIDEO_ALPHA_INITIAL_SCALE
 
- VIDEO_ALPHA_INITIAL_SCALE_HORIZONTAL_MASK
 
- VIDEO_ALPHA_INITIAL_SCALE_VERTICAL_MASK
 
- VIDEO_ALPHA_PLANE_BR
 
- VIDEO_ALPHA_PLANE_BR_BOTTOM_MASK
 
- VIDEO_ALPHA_PLANE_BR_RIGHT_MASK
 
- VIDEO_ALPHA_PLANE_TL
 
- VIDEO_ALPHA_PLANE_TL_LEFT_MASK
 
- VIDEO_ALPHA_PLANE_TL_TOP_MASK
 
- VIDEO_ALPHA_SCALE
 
- VIDEO_ALPHA_SCALE_HORIZONTAL_MODE
 
- VIDEO_ALPHA_SCALE_HORIZONTAL_SCALE_MASK
 
- VIDEO_ALPHA_SCALE_VERTICAL_MODE
 
- VIDEO_ALPHA_SCALE_VERTICAL_SCALE_MASK
 
- VIDEO_AUDIO_BALANCE
 
- VIDEO_AXI_CLK
 
- VIDEO_BCR
 
- VIDEO_BLOCK
 
- VIDEO_CAPABILITY_64BIT_BASE
 
- VIDEO_CAPABILITY_SKIP_QUIRKS
 
- VIDEO_CAP_AVC
 
- VIDEO_CAP_CSS
 
- VIDEO_CAP_H264
 
- VIDEO_CAP_MPEG1
 
- VIDEO_CAP_MPEG2
 
- VIDEO_CAP_MPEG4
 
- VIDEO_CAP_NAVI
 
- VIDEO_CAP_PROG
 
- VIDEO_CAP_SPU
 
- VIDEO_CAP_SYS
 
- VIDEO_CAP_VC1
 
- VIDEO_CAP_WMV9
 
- VIDEO_CC_APB_CLK
 
- VIDEO_CC_AT_CLK
 
- VIDEO_CC_INTERFACE_BCR
 
- VIDEO_CC_QDSS_TRIG_CLK
 
- VIDEO_CC_QDSS_TSCTR_DIV8_CLK
 
- VIDEO_CC_VCODEC0_AXI_CLK
 
- VIDEO_CC_VCODEC0_BCR
 
- VIDEO_CC_VCODEC0_CORE_CLK
 
- VIDEO_CC_VCODEC1_AXI_CLK
 
- VIDEO_CC_VCODEC1_BCR
 
- VIDEO_CC_VCODEC1_CORE_CLK
 
- VIDEO_CC_VENUS_AHB_CLK
 
- VIDEO_CC_VENUS_BCR
 
- VIDEO_CC_VENUS_CLK_SRC
 
- VIDEO_CC_VENUS_CTL_AXI_CLK
 
- VIDEO_CC_VENUS_CTL_CORE_CLK
 
- VIDEO_CENTER_CUT_OUT
 
- VIDEO_CFG_0
 
- VIDEO_CFG_1
 
- VIDEO_CFG_2
 
- VIDEO_CFG_3
 
- VIDEO_CFG_4
 
- VIDEO_CHANNEL_ID
 
- VIDEO_CLEAR_BUFFER
 
- VIDEO_CLOCKS_ON
 
- VIDEO_CMD_CONTINUE
 
- VIDEO_CMD_FREEZE
 
- VIDEO_CMD_FREEZE_TO_BLACK
 
- VIDEO_CMD_PLAY
 
- VIDEO_CMD_STOP
 
- VIDEO_CMD_STOP_IMMEDIATELY
 
- VIDEO_CMD_STOP_TO_BLACK
 
- VIDEO_CNL_1
 
- VIDEO_CNL_2
 
- VIDEO_CNL_3
 
- VIDEO_CNL_4
 
- VIDEO_COMMAND
 
- VIDEO_CONTINUE
 
- VIDEO_CONTROL1
 
- VIDEO_CONTROL2
 
- VIDEO_CORE_CLK
 
- VIDEO_CORE_CLK_SRC
 
- VIDEO_CTRL_STATUS_A
 
- VIDEO_CTRL_STATUS_B
 
- VIDEO_CURRENT_MODE
 
- VIDEO_DEBUG
 
- VIDEO_DECODE_CLASS
 
- VIDEO_DIP_CTL
 
- VIDEO_DIP_DATA
 
- VIDEO_DIP_DATA_SIZE
 
- VIDEO_DIP_ENABLE
 
- VIDEO_DIP_ENABLE_AVI
 
- VIDEO_DIP_ENABLE_AVI_HSW
 
- VIDEO_DIP_ENABLE_DRM_GLK
 
- VIDEO_DIP_ENABLE_GAMUT
 
- VIDEO_DIP_ENABLE_GCP
 
- VIDEO_DIP_ENABLE_GCP_HSW
 
- VIDEO_DIP_ENABLE_GMP_HSW
 
- VIDEO_DIP_ENABLE_SPD
 
- VIDEO_DIP_ENABLE_SPD_HSW
 
- VIDEO_DIP_ENABLE_VENDOR
 
- VIDEO_DIP_ENABLE_VSC_HSW
 
- VIDEO_DIP_ENABLE_VS_HSW
 
- VIDEO_DIP_FREQ_2VSYNC
 
- VIDEO_DIP_FREQ_MASK
 
- VIDEO_DIP_FREQ_ONCE
 
- VIDEO_DIP_FREQ_VSYNC
 
- VIDEO_DIP_PORT
 
- VIDEO_DIP_PORT_MASK
 
- VIDEO_DIP_PPS_DATA_SIZE
 
- VIDEO_DIP_SELECT_AVI
 
- VIDEO_DIP_SELECT_GAMUT
 
- VIDEO_DIP_SELECT_MASK
 
- VIDEO_DIP_SELECT_SPD
 
- VIDEO_DIP_SELECT_VENDOR
 
- VIDEO_DIP_VSC_DATA_SIZE
 
- VIDEO_DISPLAY_CTRL
 
- VIDEO_DISPLAY_CTRL_BUFFER
 
- VIDEO_DISPLAY_CTRL_BYTE_SWAP
 
- VIDEO_DISPLAY_CTRL_CAPTURE
 
- VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER
 
- VIDEO_DISPLAY_CTRL_FIFO_1
 
- VIDEO_DISPLAY_CTRL_FIFO_11
 
- VIDEO_DISPLAY_CTRL_FIFO_3
 
- VIDEO_DISPLAY_CTRL_FIFO_7
 
- VIDEO_DISPLAY_CTRL_FIFO_MASK
 
- VIDEO_DISPLAY_CTRL_FORMAT_16
 
- VIDEO_DISPLAY_CTRL_FORMAT_32
 
- VIDEO_DISPLAY_CTRL_FORMAT_8
 
- VIDEO_DISPLAY_CTRL_FORMAT_MASK
 
- VIDEO_DISPLAY_CTRL_FORMAT_YUV
 
- VIDEO_DISPLAY_CTRL_GAMMA
 
- VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE
 
- VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE
 
- VIDEO_DISPLAY_CTRL_LINE_BUFFER
 
- VIDEO_DISPLAY_CTRL_PIXEL_MASK
 
- VIDEO_DISPLAY_CTRL_VERTICAL_MODE
 
- VIDEO_DISPLAY_CTRL_VERTICAL_SCALE
 
- VIDEO_EN
 
- VIDEO_ENDPOINT
 
- VIDEO_ENHANCEMENT_CLASS
 
- VIDEO_EVENT_DECODER_STOPPED
 
- VIDEO_EVENT_FRAME_RATE_CHANGED
 
- VIDEO_EVENT_SIZE_CHANGED
 
- VIDEO_EVENT_VSYNC
 
- VIDEO_EXT0
 
- VIDEO_FAST_FORWARD
 
- VIDEO_FB_0_ADDRESS
 
- VIDEO_FB_0_ADDRESS_ADDRESS_MASK
 
- VIDEO_FB_0_ADDRESS_EXT
 
- VIDEO_FB_0_ADDRESS_STATUS
 
- VIDEO_FB_0_LAST_ADDRESS
 
- VIDEO_FB_0_LAST_ADDRESS_ADDRESS_MASK
 
- VIDEO_FB_0_LAST_ADDRESS_EXT
 
- VIDEO_FB_1_ADDRESS
 
- VIDEO_FB_1_ADDRESS_ADDRESS_MASK
 
- VIDEO_FB_1_ADDRESS_EXT
 
- VIDEO_FB_1_ADDRESS_STATUS
 
- VIDEO_FB_1_LAST_ADDRESS
 
- VIDEO_FB_1_LAST_ADDRESS_ADDRESS_MASK
 
- VIDEO_FB_1_LAST_ADDRESS_EXT
 
- VIDEO_FB_WIDTH
 
- VIDEO_FB_WIDTH_OFFSET_MASK
 
- VIDEO_FB_WIDTH_WIDTH_MASK
 
- VIDEO_FIELD_CTRL
 
- VIDEO_FIFO
 
- VIDEO_FIFO_MASK
 
- VIDEO_FIFO_STATUS
 
- VIDEO_FIRST_BIOS
 
- VIDEO_FIRST_MENU
 
- VIDEO_FIRST_RESOLUTION
 
- VIDEO_FIRST_SPECIAL
 
- VIDEO_FIRST_V7
 
- VIDEO_FIRST_VESA
 
- VIDEO_FLAGS_NOCURSOR
 
- VIDEO_FMT_REG
 
- VIDEO_FORMAT
 
- VIDEO_FORMAT_16_9
 
- VIDEO_FORMAT_221_1
 
- VIDEO_FORMAT_4_3
 
- VIDEO_FRAME_INPRG
 
- VIDEO_FRAME_PICTURE
 
- VIDEO_FREEZE
 
- VIDEO_FREEZED
 
- VIDEO_GET_CAPABILITIES
 
- VIDEO_GET_EVENT
 
- VIDEO_GET_EVENT32
 
- VIDEO_GET_FRAME_COUNT
 
- VIDEO_GET_PTS
 
- VIDEO_GET_SIZE
 
- VIDEO_GET_STATUS
 
- VIDEO_GFX_HACK
 
- VIDEO_HEADER_MAGIC
 
- VIDEO_I2C_DRIVER
 
- VIDEO_IN
 
- VIDEO_INITIAL_SCALE
 
- VIDEO_INITIAL_SCALE_FB_0_MASK
 
- VIDEO_INITIAL_SCALE_FB_1_MASK
 
- VIDEO_INPUT_10BITS
 
- VIDEO_INPUT_12BITS
 
- VIDEO_INPUT_8BITS
 
- VIDEO_INPUT_DDR_RGB444
 
- VIDEO_INPUT_DDR_YCBCR422
 
- VIDEO_INPUT_REVERT
 
- VIDEO_INPUT_SDR_RGB444
 
- VIDEO_LAST_SPECIAL
 
- VIDEO_LETTER_BOX
 
- VIDEO_LIPSYNC
 
- VIDEO_MAJOR
 
- VIDEO_MASK
 
- VIDEO_MASTER_CLK_SEL
 
- VIDEO_MASTER_MODE_EN
 
- VIDEO_MAXI_CLK
 
- VIDEO_MAX_FRAME
 
- VIDEO_MAX_PLANES
 
- VIDEO_MEMORY_SIZE_16M
 
- VIDEO_MEMORY_TYPE_DDR3
 
- VIDEO_MEMORY_TYPE_DDR4
 
- VIDEO_MEMORY_TYPE_GDDR5
 
- VIDEO_MEMORY_TYPE_GDDR6
 
- VIDEO_MEMORY_TYPE_HBM
 
- VIDEO_MEM_LIMIT
 
- VIDEO_MODE_BURST
 
- VIDEO_MODE_DETECT_DONE
 
- VIDEO_MODE_MASK
 
- VIDEO_MODE_MASTER_MODE
 
- VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS
 
- VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE
 
- VIDEO_MODE_SLAVE_MODE
 
- VIDEO_MODE_SYNC_EVENT
 
- VIDEO_MODE_SYNC_PULSE
 
- VIDEO_NAME
 
- VIDEO_NUM_DEVICES
 
- VIDEO_OFFSET_SHIFT
 
- VIDEO_OUTPUT_CONTROL_FORMATTER
 
- VIDEO_PACKET_SIZE
 
- VIDEO_PAN_SCAN
 
- VIDEO_PARSER_STATUS
 
- VIDEO_PLANE_BR
 
- VIDEO_PLANE_BR_BOTTOM_MASK
 
- VIDEO_PLANE_BR_RIGHT_MASK
 
- VIDEO_PLANE_TL
 
- VIDEO_PLANE_TL_LEFT_MASK
 
- VIDEO_PLANE_TL_TOP_MASK
 
- VIDEO_PLAY
 
- VIDEO_PLAYING
 
- VIDEO_PLAY_FMT_GOP
 
- VIDEO_PLAY_FMT_NONE
 
- VIDEO_PLL0
 
- VIDEO_PLL2
 
- VIDEO_PROCAMP_MAX
 
- VIDEO_PROCAMP_MIN
 
- VIDEO_RECALC
 
- VIDEO_RESET
 
- VIDEO_RESOURCES
 
- VIDEO_RES_CHANGE
 
- VIDEO_RES_DETECT
 
- VIDEO_ROM
 
- VIDEO_SCALE
 
- VIDEO_SCALE_HORIZONTAL_MODE
 
- VIDEO_SCALE_HORIZONTAL_SCALE_MASK
 
- VIDEO_SCALE_VERTICAL_MODE
 
- VIDEO_SCALE_VERTICAL_SCALE_MASK
 
- VIDEO_SELECT_SOURCE
 
- VIDEO_SET_BLANK
 
- VIDEO_SET_DISPLAY_FORMAT
 
- VIDEO_SET_FORMAT
 
- VIDEO_SET_STREAMTYPE
 
- VIDEO_SIZE
 
- VIDEO_SIZE_F2
 
- VIDEO_SLOWMOTION
 
- VIDEO_SOURCE_DEMUX
 
- VIDEO_SOURCE_MEMORY
 
- VIDEO_SOURCE_SEL
 
- VIDEO_STD_AUTO_SWITCH_BIT
 
- VIDEO_STD_MASK
 
- VIDEO_STD_NTSC_4_43_BIT
 
- VIDEO_STD_NTSC_4_43_BIT_AS
 
- VIDEO_STD_NTSC_MJ_BIT
 
- VIDEO_STD_NTSC_MJ_BIT_AS
 
- VIDEO_STD_PAL_60_BIT
 
- VIDEO_STD_PAL_BDGHIN_BIT
 
- VIDEO_STD_PAL_BDGHIN_BIT_AS
 
- VIDEO_STD_PAL_COMBINATION_N_BIT
 
- VIDEO_STD_PAL_COMBINATION_N_BIT_AS
 
- VIDEO_STD_PAL_M_BIT
 
- VIDEO_STD_PAL_M_BIT_AS
 
- VIDEO_STD_SECAM_BIT
 
- VIDEO_STD_SECAM_BIT_AS
 
- VIDEO_STILLPICTURE
 
- VIDEO_STILLPICTURE32
 
- VIDEO_STOP
 
- VIDEO_STOPPED
 
- VIDEO_STREAMING
 
- VIDEO_STREAM_E
 
- VIDEO_STREAM_S
 
- VIDEO_SUBCORE0_CLK
 
- VIDEO_SUBCORE0_CLK_SRC
 
- VIDEO_SUBCORE1_CLK
 
- VIDEO_SUBCORE1_CLK_SRC
 
- VIDEO_SYNC_TEST
 
- VIDEO_TIMING_FROM_CAPTURE
 
- VIDEO_TIMING_FROM_REGISTER
 
- VIDEO_TRY_COMMAND
 
- VIDEO_TYPE
 
- VIDEO_TYPE_CGA
 
- VIDEO_TYPE_EFI
 
- VIDEO_TYPE_EGAC
 
- VIDEO_TYPE_EGAM
 
- VIDEO_TYPE_MDA
 
- VIDEO_TYPE_MIPS_G364
 
- VIDEO_TYPE_PICA_S3
 
- VIDEO_TYPE_PMAC
 
- VIDEO_TYPE_SGI
 
- VIDEO_TYPE_SUN
 
- VIDEO_TYPE_SUNPCI
 
- VIDEO_TYPE_TGAC
 
- VIDEO_TYPE_VGAC
 
- VIDEO_TYPE_VLFB
 
- VIDEO_VSYNC_FIELD_EVEN
 
- VIDEO_VSYNC_FIELD_ODD
 
- VIDEO_VSYNC_FIELD_PROGRESSIVE
 
- VIDEO_VSYNC_FIELD_UNKNOWN
 
- VIDEO_YUV_CONSTANTS
 
- VIDEO_YUV_CONSTANTS_B_MASK
 
- VIDEO_YUV_CONSTANTS_G_MASK
 
- VIDEO_YUV_CONSTANTS_R_MASK
 
- VIDEO_YUV_CONSTANTS_Y_MASK
 
- VIDFREQ1
 
- VIDFREQ2
 
- VIDFREQ3
 
- VIDFREQ4
 
- VIDFREQ_BASE
 
- VIDFREQ_P0_CRCLK_MASK
 
- VIDFREQ_P0_CRCLK_SHIFT
 
- VIDFREQ_P0_CSCLK_MASK
 
- VIDFREQ_P0_CSCLK_SHIFT
 
- VIDFREQ_P0_MASK
 
- VIDFREQ_P0_SHIFT
 
- VIDFREQ_P1_CRCLK_MASK
 
- VIDFREQ_P1_CSCLK_MASK
 
- VIDFREQ_P1_CSCLK_SHIFT
 
- VIDFREQ_P1_MASK
 
- VIDFREQ_P1_SHIFT
 
- VIDGAM0
 
- VIDGAM1
 
- VIDGAM10
 
- VIDGAM11
 
- VIDGAM12
 
- VIDGAM13
 
- VIDGAM14
 
- VIDGAM15
 
- VIDGAM16
 
- VIDGAM2
 
- VIDGAM3
 
- VIDGAM4
 
- VIDGAM5
 
- VIDGAM6
 
- VIDGAM7
 
- VIDGAM8
 
- VIDGAM9
 
- VIDINADDR0
 
- VIDINADDR1
 
- VIDINADDR2
 
- VIDINFORMAT
 
- VIDININITERR
 
- VIDINSTATUS
 
- VIDINSTRIDE
 
- VIDINTCON0
 
- VIDINTCON0_FIFIOSEL_MASK
 
- VIDINTCON0_FIFIOSEL_SHIFT
 
- VIDINTCON0_FIFIOSEL_WINDOW0
 
- VIDINTCON0_FIFIOSEL_WINDOW1
 
- VIDINTCON0_FIFIOSEL_WINDOW2
 
- VIDINTCON0_FIFIOSEL_WINDOW3
 
- VIDINTCON0_FIFIOSEL_WINDOW4
 
- VIDINTCON0_FIFOINTERVAL
 
- VIDINTCON0_FIFOINTERVAL_LIMIT
 
- VIDINTCON0_FIFOINTERVAL_MASK
 
- VIDINTCON0_FIFOINTERVAL_SHIFT
 
- VIDINTCON0_FIFOLEVEL_EMPTY
 
- VIDINTCON0_FIFOLEVEL_FULL
 
- VIDINTCON0_FIFOLEVEL_MASK
 
- VIDINTCON0_FIFOLEVEL_SHIFT
 
- VIDINTCON0_FIFOLEVEL_TO25PC
 
- VIDINTCON0_FIFOLEVEL_TO50PC
 
- VIDINTCON0_FIFOLEVEL_TO75PC
 
- VIDINTCON0_FIFOSEL_MAIN_EN
 
- VIDINTCON0_FRAMEDONE
 
- VIDINTCON0_FRAMESEL0_ACTIVE
 
- VIDINTCON0_FRAMESEL0_BACKPORCH
 
- VIDINTCON0_FRAMESEL0_FRONTPORCH
 
- VIDINTCON0_FRAMESEL0_MASK
 
- VIDINTCON0_FRAMESEL0_SHIFT
 
- VIDINTCON0_FRAMESEL0_VSYNC
 
- VIDINTCON0_FRAMESEL1
 
- VIDINTCON0_FRAMESEL1_BACKPORCH
 
- VIDINTCON0_FRAMESEL1_FRONTPORCH
 
- VIDINTCON0_FRAMESEL1_MASK
 
- VIDINTCON0_FRAMESEL1_NONE
 
- VIDINTCON0_FRAMESEL1_VSYNC
 
- VIDINTCON0_FRAMESEL_AC
 
- VIDINTCON0_FRAMESEL_BP
 
- VIDINTCON0_FRAMESEL_FP
 
- VIDINTCON0_FRAMESEL_VS
 
- VIDINTCON0_INTEN
 
- VIDINTCON0_INTEXTRAEN
 
- VIDINTCON0_INTFRMEN
 
- VIDINTCON0_INT_ENABLE
 
- VIDINTCON0_INT_FIFO
 
- VIDINTCON0_INT_FIFO_MASK
 
- VIDINTCON0_INT_FIFO_SHIFT
 
- VIDINTCON0_INT_FRAME
 
- VIDINTCON0_INT_I80IFDONE
 
- VIDINTCON0_INT_SYSMAINCON
 
- VIDINTCON0_INT_SYSSUBCON
 
- VIDINTCON0_WAKEUP_MASK
 
- VIDINTCON1
 
- VIDINTCON1_INTEXTRA0_EN
 
- VIDINTCON1_INTEXTRA0_PEND
 
- VIDINTCON1_INTEXTRA1_EN
 
- VIDINTCON1_INTEXTRA1_PEND
 
- VIDINTCON1_INTFIFOPEND
 
- VIDINTCON1_INTFRMDONEPEND
 
- VIDINTCON1_INTFRMPEND
 
- VIDINTCON1_INT_EXTRA
 
- VIDINTCON1_INT_FIFO
 
- VIDINTCON1_INT_FRAME
 
- VIDINTCON1_INT_I80
 
- VIDINTCON2
 
- VIDINTCON3
 
- VIDINXDELTA
 
- VIDINYDELTA
 
- VIDIOC_AM437X_CCDC_CFG
 
- VIDIOC_CREATE_BUFS
 
- VIDIOC_CREATE_BUFS32
 
- VIDIOC_CROPCAP
 
- VIDIOC_DBG_G_CHIP_INFO
 
- VIDIOC_DBG_G_REGISTER
 
- VIDIOC_DBG_S_REGISTER
 
- VIDIOC_DECODER_CMD
 
- VIDIOC_DQBUF
 
- VIDIOC_DQBUF32
 
- VIDIOC_DQEVENT
 
- VIDIOC_DQEVENT32
 
- VIDIOC_DV_TIMINGS_CAP
 
- VIDIOC_ENCODER_CMD
 
- VIDIOC_ENUMAUDIO
 
- VIDIOC_ENUMAUDOUT
 
- VIDIOC_ENUMINPUT
 
- VIDIOC_ENUMINPUT32
 
- VIDIOC_ENUMOUTPUT
 
- VIDIOC_ENUMSTD
 
- VIDIOC_ENUMSTD32
 
- VIDIOC_ENUM_DV_TIMINGS
 
- VIDIOC_ENUM_FMT
 
- VIDIOC_ENUM_FRAMEINTERVALS
 
- VIDIOC_ENUM_FRAMESIZES
 
- VIDIOC_ENUM_FREQ_BANDS
 
- VIDIOC_EXPBUF
 
- VIDIOC_G_AUDIO
 
- VIDIOC_G_AUDOUT
 
- VIDIOC_G_CROP
 
- VIDIOC_G_CTRL
 
- VIDIOC_G_DV_TIMINGS
 
- VIDIOC_G_EDID
 
- VIDIOC_G_EDID32
 
- VIDIOC_G_ENC_INDEX
 
- VIDIOC_G_EXT_CTRLS
 
- VIDIOC_G_EXT_CTRLS32
 
- VIDIOC_G_FBUF
 
- VIDIOC_G_FBUF32
 
- VIDIOC_G_FMT
 
- VIDIOC_G_FMT32
 
- VIDIOC_G_FREQUENCY
 
- VIDIOC_G_INPUT
 
- VIDIOC_G_INPUT32
 
- VIDIOC_G_JPEGCOMP
 
- VIDIOC_G_MODULATOR
 
- VIDIOC_G_OUTPUT
 
- VIDIOC_G_OUTPUT32
 
- VIDIOC_G_PARM
 
- VIDIOC_G_PRIORITY
 
- VIDIOC_G_SELECTION
 
- VIDIOC_G_SLICED_VBI_CAP
 
- VIDIOC_G_STD
 
- VIDIOC_G_TUNER
 
- VIDIOC_INT_RESET
 
- VIDIOC_LOG_STATUS
 
- VIDIOC_OMAP3ISP_AEWB_CFG
 
- VIDIOC_OMAP3ISP_AF_CFG
 
- VIDIOC_OMAP3ISP_CCDC_CFG
 
- VIDIOC_OMAP3ISP_HIST_CFG
 
- VIDIOC_OMAP3ISP_PRV_CFG
 
- VIDIOC_OMAP3ISP_STAT_EN
 
- VIDIOC_OMAP3ISP_STAT_REQ
 
- VIDIOC_OMAP3ISP_STAT_REQ_TIME32
 
- VIDIOC_OVERLAY
 
- VIDIOC_OVERLAY32
 
- VIDIOC_PREPARE_BUF
 
- VIDIOC_PREPARE_BUF32
 
- VIDIOC_QBUF
 
- VIDIOC_QBUF32
 
- VIDIOC_QUERYBUF
 
- VIDIOC_QUERYBUF32
 
- VIDIOC_QUERYCAP
 
- VIDIOC_QUERYCTRL
 
- VIDIOC_QUERYMENU
 
- VIDIOC_QUERYSTD
 
- VIDIOC_QUERY_DV_TIMINGS
 
- VIDIOC_QUERY_EXT_CTRL
 
- VIDIOC_REQBUFS
 
- VIDIOC_STREAMOFF
 
- VIDIOC_STREAMOFF32
 
- VIDIOC_STREAMON
 
- VIDIOC_STREAMON32
 
- VIDIOC_SUBDEV_DV_TIMINGS_CAP
 
- VIDIOC_SUBDEV_ENUMSTD
 
- VIDIOC_SUBDEV_ENUM_DV_TIMINGS
 
- VIDIOC_SUBDEV_ENUM_FRAME_INTERVAL
 
- VIDIOC_SUBDEV_ENUM_FRAME_SIZE
 
- VIDIOC_SUBDEV_ENUM_MBUS_CODE
 
- VIDIOC_SUBDEV_G_CROP
 
- VIDIOC_SUBDEV_G_DV_TIMINGS
 
- VIDIOC_SUBDEV_G_EDID
 
- VIDIOC_SUBDEV_G_FMT
 
- VIDIOC_SUBDEV_G_FRAME_INTERVAL
 
- VIDIOC_SUBDEV_G_SELECTION
 
- VIDIOC_SUBDEV_G_STD
 
- VIDIOC_SUBDEV_QUERYSTD
 
- VIDIOC_SUBDEV_QUERY_DV_TIMINGS
 
- VIDIOC_SUBDEV_S_CROP
 
- VIDIOC_SUBDEV_S_DV_TIMINGS
 
- VIDIOC_SUBDEV_S_EDID
 
- VIDIOC_SUBDEV_S_FMT
 
- VIDIOC_SUBDEV_S_FRAME_INTERVAL
 
- VIDIOC_SUBDEV_S_SELECTION
 
- VIDIOC_SUBDEV_S_STD
 
- VIDIOC_SUBSCRIBE_EVENT
 
- VIDIOC_S_AUDIO
 
- VIDIOC_S_AUDOUT
 
- VIDIOC_S_CROP
 
- VIDIOC_S_CTRL
 
- VIDIOC_S_DV_TIMINGS
 
- VIDIOC_S_EDID
 
- VIDIOC_S_EDID32
 
- VIDIOC_S_EXT_CTRLS
 
- VIDIOC_S_EXT_CTRLS32
 
- VIDIOC_S_FBUF
 
- VIDIOC_S_FBUF32
 
- VIDIOC_S_FMT
 
- VIDIOC_S_FMT32
 
- VIDIOC_S_FREQUENCY
 
- VIDIOC_S_HW_FREQ_SEEK
 
- VIDIOC_S_INPUT
 
- VIDIOC_S_INPUT32
 
- VIDIOC_S_JPEGCOMP
 
- VIDIOC_S_MODULATOR
 
- VIDIOC_S_OUTPUT
 
- VIDIOC_S_OUTPUT32
 
- VIDIOC_S_PARM
 
- VIDIOC_S_PRIORITY
 
- VIDIOC_S_SELECTION
 
- VIDIOC_S_STD
 
- VIDIOC_S_TUNER
 
- VIDIOC_TRY_DECODER_CMD
 
- VIDIOC_TRY_ENCODER_CMD
 
- VIDIOC_TRY_EXT_CTRLS
 
- VIDIOC_TRY_EXT_CTRLS32
 
- VIDIOC_TRY_FMT
 
- VIDIOC_TRY_FMT32
 
- VIDIOC_UNSUBSCRIBE_EVENT
 
- VIDISD14C_ALPHA0_B
 
- VIDISD14C_ALPHA0_B_LIMIT
 
- VIDISD14C_ALPHA0_B_MASK
 
- VIDISD14C_ALPHA0_B_SHIFT
 
- VIDISD14C_ALPHA0_G
 
- VIDISD14C_ALPHA0_G_LIMIT
 
- VIDISD14C_ALPHA0_G_MASK
 
- VIDISD14C_ALPHA0_G_SHIFT
 
- VIDISD14C_ALPHA0_R
 
- VIDISD14C_ALPHA1_B
 
- VIDISD14C_ALPHA1_B_LIMIT
 
- VIDISD14C_ALPHA1_B_MASK
 
- VIDISD14C_ALPHA1_B_SHIFT
 
- VIDISD14C_ALPHA1_G
 
- VIDISD14C_ALPHA1_G_LIMIT
 
- VIDISD14C_ALPHA1_G_MASK
 
- VIDISD14C_ALPHA1_G_SHIFT
 
- VIDISD14C_ALPHA1_R
 
- VIDISD14C_ALPHA1_R_LIMIT
 
- VIDISD14C_ALPHA1_R_MASK
 
- VIDISD14C_ALPHA1_R_SHIFT
 
- VIDI_REFRESH_TIME
 
- VIDL_G
 
- VIDL_M
 
- VIDL_S
 
- VIDMEM
 
- VIDOSD_A
 
- VIDOSD_B
 
- VIDOSD_BASE
 
- VIDOSD_C
 
- VIDOSD_D
 
- VIDOSD_E
 
- VIDOSD_H
 
- VIDOSD_Wx_ALPHA_B_F
 
- VIDOSD_Wx_ALPHA_G_F
 
- VIDOSD_Wx_ALPHA_R_F
 
- VIDOSDxA_TOPLEFT_X
 
- VIDOSDxA_TOPLEFT_X_E
 
- VIDOSDxA_TOPLEFT_X_LIMIT
 
- VIDOSDxA_TOPLEFT_X_MASK
 
- VIDOSDxA_TOPLEFT_X_SHIFT
 
- VIDOSDxA_TOPLEFT_Y
 
- VIDOSDxA_TOPLEFT_Y_E
 
- VIDOSDxA_TOPLEFT_Y_LIMIT
 
- VIDOSDxA_TOPLEFT_Y_MASK
 
- VIDOSDxA_TOPLEFT_Y_SHIFT
 
- VIDOSDxB_BOTRIGHT_X
 
- VIDOSDxB_BOTRIGHT_X_E
 
- VIDOSDxB_BOTRIGHT_X_LIMIT
 
- VIDOSDxB_BOTRIGHT_X_MASK
 
- VIDOSDxB_BOTRIGHT_X_SHIFT
 
- VIDOSDxB_BOTRIGHT_Y
 
- VIDOSDxB_BOTRIGHT_Y_E
 
- VIDOSDxB_BOTRIGHT_Y_LIMIT
 
- VIDOSDxB_BOTRIGHT_Y_MASK
 
- VIDOSDxB_BOTRIGHT_Y_SHIFT
 
- VIDOSDxC_ALPHA0_B_F
 
- VIDOSDxC_ALPHA0_G_F
 
- VIDOSDxC_ALPHA0_RGB_MASK
 
- VIDOSDxC_ALPHA0_R_F
 
- VIDOSDxD_ALPHA1_B_F
 
- VIDOSDxD_ALPHA1_G_F
 
- VIDOSDxD_ALPHA1_R_F
 
- VIDOUTCON0
 
- VIDOUTCON0_DISP_IF_0_ON
 
- VIDOUTCON0_DISP_IF_1_ON
 
- VIDOUTCON0_DUAL_MASK
 
- VIDOUTCON0_DUAL_OFF
 
- VIDOUTCON0_DUAL_ON
 
- VIDOUTCON0_I80IF
 
- VIDOUTCON0_IF_MASK
 
- VIDOUTCON0_IF_SHIFT
 
- VIDOUTCON0_RGBIF
 
- VIDOUT_COMMAND_IF
 
- VIDOUT_CON
 
- VIDOUT_CON_F_I80_LDI0
 
- VIDOUT_IF_F_MASK
 
- VIDOUT_INTERLACE_EN_F
 
- VIDOUT_INTERLACE_FIELD_F
 
- VIDOUT_LCD_ON
 
- VIDOUT_RGB_IF
 
- VIDOVRDUDX
 
- VIDOVRDUDXOFF
 
- VIDOVRDVDY
 
- VIDOVRDVDYOFF
 
- VIDOVRENDCRD
 
- VIDOVRSTARTCRD
 
- VIDPIXBUFTHOLD
 
- VIDPROCCFG
 
- VIDSCREENSIZE
 
- VIDSERPARPORT
 
- VIDSTART
 
- VIDSTAT
 
- VIDSTS
 
- VIDShift
 
- VIDTCON0
 
- VIDTCON00_VBPD_F
 
- VIDTCON00_VFPD_F
 
- VIDTCON01_VSPW_F
 
- VIDTCON0_VBPD
 
- VIDTCON0_VBPDE
 
- VIDTCON0_VBPDE_LIMIT
 
- VIDTCON0_VBPDE_MASK
 
- VIDTCON0_VBPDE_SHIFT
 
- VIDTCON0_VBPD_LIMIT
 
- VIDTCON0_VBPD_MASK
 
- VIDTCON0_VBPD_SHIFT
 
- VIDTCON0_VFPD
 
- VIDTCON0_VFPD_LIMIT
 
- VIDTCON0_VFPD_MASK
 
- VIDTCON0_VFPD_SHIFT
 
- VIDTCON0_VSPW
 
- VIDTCON0_VSPW_LIMIT
 
- VIDTCON0_VSPW_MASK
 
- VIDTCON0_VSPW_SHIFT
 
- VIDTCON1
 
- VIDTCON10_HBPD_F
 
- VIDTCON10_HFPD_F
 
- VIDTCON11_HSPW_F
 
- VIDTCON1_HBPD
 
- VIDTCON1_HBPD_LIMIT
 
- VIDTCON1_HBPD_MASK
 
- VIDTCON1_HBPD_SHIFT
 
- VIDTCON1_HFPD
 
- VIDTCON1_HFPD_LIMIT
 
- VIDTCON1_HFPD_MASK
 
- VIDTCON1_HFPD_SHIFT
 
- VIDTCON1_HSPW
 
- VIDTCON1_HSPW_LIMIT
 
- VIDTCON1_HSPW_MASK
 
- VIDTCON1_HSPW_SHIFT
 
- VIDTCON1_VFPDE
 
- VIDTCON1_VFPDE_LIMIT
 
- VIDTCON1_VFPDE_MASK
 
- VIDTCON1_VFPDE_SHIFT
 
- VIDTCON1_VSPW
 
- VIDTCON1_VSPW_LIMIT
 
- VIDTCON1_VSPW_MASK
 
- VIDTCON1_VSPW_SHIFT
 
- VIDTCON2
 
- VIDTCON2_HBPD
 
- VIDTCON2_HBPD_LIMIT
 
- VIDTCON2_HBPD_MASK
 
- VIDTCON2_HBPD_SHIFT
 
- VIDTCON2_HFPD
 
- VIDTCON2_HFPD_LIMIT
 
- VIDTCON2_HFPD_MASK
 
- VIDTCON2_HFPD_SHIFT
 
- VIDTCON2_HOZVAL
 
- VIDTCON2_HOZVAL_E
 
- VIDTCON2_HOZVAL_LIMIT
 
- VIDTCON2_HOZVAL_MASK
 
- VIDTCON2_HOZVAL_SHIFT
 
- VIDTCON2_LINEVAL
 
- VIDTCON2_LINEVAL_E
 
- VIDTCON2_LINEVAL_LIMIT
 
- VIDTCON2_LINEVAL_MASK
 
- VIDTCON2_LINEVAL_SHIFT
 
- VIDTCON3
 
- VIDTCON3_HSPW
 
- VIDTCON3_HSPW_LIMIT
 
- VIDTCON3_HSPW_MASK
 
- VIDTCON3_HSPW_SHIFT
 
- VIDTCON4
 
- VIDTCON4_HOZVAL
 
- VIDTCON4_HOZVAL_LIMIT
 
- VIDTCON4_HOZVAL_MASK
 
- VIDTCON4_HOZVAL_SHIFT
 
- VIDTCON4_LINEVAL
 
- VIDTCON4_LINEVAL_LIMIT
 
- VIDTCON4_LINEVAL_MASK
 
- VIDTCON4_LINEVAL_SHIFT
 
- VIDW_ALPHA
 
- VIDW_ALPHA_B
 
- VIDW_ALPHA_G
 
- VIDW_ALPHA_R
 
- VIDW_BLKOFFSET
 
- VIDW_BLKSIZE
 
- VIDW_BUF_END
 
- VIDW_BUF_END1
 
- VIDW_BUF_SIZE
 
- VIDW_BUF_SIZE_OFFSET
 
- VIDW_BUF_SIZE_OFFSET_E
 
- VIDW_BUF_SIZE_OFFSET_LIMIT
 
- VIDW_BUF_SIZE_OFFSET_MASK
 
- VIDW_BUF_SIZE_OFFSET_SHIFT
 
- VIDW_BUF_SIZE_PAGEWIDTH
 
- VIDW_BUF_SIZE_PAGEWIDTH_E
 
- VIDW_BUF_SIZE_PAGEWIDTH_LIMIT
 
- VIDW_BUF_SIZE_PAGEWIDTH_MASK
 
- VIDW_BUF_SIZE_PAGEWIDTH_SHIFT
 
- VIDW_BUF_START
 
- VIDW_BUF_START1
 
- VIDW_BUF_START2
 
- VIDW_BUF_START_S
 
- VIDW_OFFSET_X
 
- VIDW_OFFSET_Y
 
- VIDW_WHOLE_X
 
- VIDW_WHOLE_Y
 
- VIDWnALPHA0
 
- VIDWnALPHA1
 
- VIDWx_BUF_END
 
- VIDWx_BUF_SIZE
 
- VIDWx_BUF_START
 
- VIDWx_BUF_START_S
 
- VID_ALP
 
- VID_ALP_OPAQUE
 
- VID_A_CDT
 
- VID_A_DMA_CTL
 
- VID_A_DOWN_CLUSTER_1
 
- VID_A_DOWN_CLUSTER_2
 
- VID_A_DOWN_CLUSTER_3
 
- VID_A_DOWN_CLUSTER_4
 
- VID_A_DOWN_CMDS
 
- VID_A_GPCNT
 
- VID_A_GPCNT_CTL
 
- VID_A_INT_MSK
 
- VID_A_INT_MSTAT
 
- VID_A_INT_SSTAT
 
- VID_A_INT_STAT
 
- VID_A_IQ
 
- VID_A_PIXEL_FRMT
 
- VID_A_UP_CLUSTER_1
 
- VID_A_UP_CLUSTER_2
 
- VID_A_UP_CLUSTER_3
 
- VID_A_UP_CLUSTER_4
 
- VID_A_UP_CMDS
 
- VID_A_VBI_CTL
 
- VID_A_VBI_CTRL
 
- VID_A_VIP_CTL
 
- VID_A_VIP_CTRL
 
- VID_BC
 
- VID_BC_DFLT
 
- VID_BC_MSK_BAD_PKT
 
- VID_BC_MSK_OF
 
- VID_BC_MSK_OPC_ERR
 
- VID_BC_MSK_RISCI1
 
- VID_BC_MSK_RISCI2
 
- VID_BC_MSK_SYNC
 
- VID_BC_MSK_VBI_RISCI1
 
- VID_BC_MSK_VBI_RISCI2
 
- VID_BLKSIZE1
 
- VID_BLKSIZE2
 
- VID_BLK_I2C_ADDRESS
 
- VID_B_BD_PKT_STATUS
 
- VID_B_CDT
 
- VID_B_DMA
 
- VID_B_DMA_CTL
 
- VID_B_DOWN_CLUSTER_1
 
- VID_B_DOWN_CLUSTER_2
 
- VID_B_DOWN_CLUSTER_3
 
- VID_B_DOWN_CLUSTER_4
 
- VID_B_DOWN_CMDS
 
- VID_B_FIFO_OVFL_STAT
 
- VID_B_GEN_CTL
 
- VID_B_GPCNT
 
- VID_B_GPCNT_CTL
 
- VID_B_HW_SOP_CTL
 
- VID_B_INT_MSK
 
- VID_B_INT_MSTAT
 
- VID_B_INT_SSTAT
 
- VID_B_INT_STAT
 
- VID_B_IQ
 
- VID_B_LNGTH
 
- VID_B_MSK_BAD_PKT
 
- VID_B_MSK_OF
 
- VID_B_MSK_OPC_ERR
 
- VID_B_MSK_RISCI1
 
- VID_B_MSK_RISCI2
 
- VID_B_MSK_SYNC
 
- VID_B_MSK_VBI_OF
 
- VID_B_MSK_VBI_OPC_ERR
 
- VID_B_MSK_VBI_RISCI1
 
- VID_B_MSK_VBI_RISCI2
 
- VID_B_MSK_VBI_SYNC
 
- VID_B_PIXEL_FRMT
 
- VID_B_SOP_STATUS
 
- VID_B_SRC_SEL
 
- VID_B_TS_CLK_EN
 
- VID_B_UP_CLUSTER_1
 
- VID_B_UP_CLUSTER_2
 
- VID_B_UP_CLUSTER_3
 
- VID_B_UP_CLUSTER_4
 
- VID_B_UP_CMDS
 
- VID_B_VIP_CTL
 
- VID_B_VIP_CTRL
 
- VID_B_VLD_MISC
 
- VID_CAPTURE
 
- VID_CAPTURE_CONTROL
 
- VID_CDT_SIZE
 
- VID_CDT_SIZE_QW
 
- VID_CENTRE_CUT_PREF
 
- VID_CHANNEL_NUM
 
- VID_CHK_UPDATE_TYPE_0
 
- VID_CHK_UPDATE_TYPE_1
 
- VID_CHK_UPDATE_TYPE_MASK
 
- VID_CHK_UPDATE_TYPE_SHIFT
 
- VID_CH_CLK_SEL
 
- VID_CH_MODE_SEL
 
- VID_CLF
 
- VID_CLK_CHG
 
- VID_CLOCK
 
- VID_CLUSTER_SIZE
 
- VID_CLUSTER_SIZE_OW
 
- VID_CMDS_SIZE
 
- VID_CRT
 
- VID_CRTU
 
- VID_CRTU_MASK
 
- VID_CRT_MASK
 
- VID_CSAT
 
- VID_CSAT_DFLT
 
- VID_CTL
 
- VID_CTL_IGNORE
 
- VID_CTL_PSI_ENABLE
 
- VID_C_BD_PKT_STATUS
 
- VID_C_CDT
 
- VID_C_DMA
 
- VID_C_DMA_CTL
 
- VID_C_DOWN_CLUSTER_1
 
- VID_C_DOWN_CLUSTER_2
 
- VID_C_DOWN_CLUSTER_3
 
- VID_C_DOWN_CLUSTER_4
 
- VID_C_DOWN_CMDS
 
- VID_C_FIFO_OVFL_STAT
 
- VID_C_GEN_CTL
 
- VID_C_GPCNT
 
- VID_C_GPCNT_CTL
 
- VID_C_HW_SOP_CTL
 
- VID_C_INT_MSK
 
- VID_C_INT_MSTAT
 
- VID_C_INT_SSTAT
 
- VID_C_INT_STAT
 
- VID_C_IQ
 
- VID_C_LNGTH
 
- VID_C_MSK_BAD_PKT
 
- VID_C_MSK_OF
 
- VID_C_MSK_OPC_ERR
 
- VID_C_MSK_RISCI1
 
- VID_C_MSK_RISCI2
 
- VID_C_MSK_SYNC
 
- VID_C_SOP_STATUS
 
- VID_C_TS_CLK_EN
 
- VID_C_UP_CLUSTER_1
 
- VID_C_UP_CLUSTER_2
 
- VID_C_UP_CLUSTER_3
 
- VID_C_UP_CLUSTER_4
 
- VID_C_UP_CMDS
 
- VID_C_VLD_MISC
 
- VID_DATATYPE
 
- VID_DPHY_TIME
 
- VID_DST_A_DMA_CTL
 
- VID_DST_A_GPCNT
 
- VID_DST_A_GPCNT_CTL
 
- VID_DST_A_PIX_FRMT
 
- VID_DST_A_VIP_CTL
 
- VID_DST_B_DMA_CTL
 
- VID_DST_B_GPCNT
 
- VID_DST_B_GPCNT_CTL
 
- VID_DST_B_PIX_FRMT
 
- VID_DST_B_VIP_CTL
 
- VID_DST_C_DMA_CTL
 
- VID_DST_C_GPCNT
 
- VID_DST_C_GPCNT_CTL
 
- VID_DST_C_PIX_FRMT
 
- VID_DST_C_VIP_CTL
 
- VID_DST_D_DMA_CTL
 
- VID_DST_D_GPCNT
 
- VID_DST_D_GPCNT_CTL
 
- VID_DST_D_PIX_FRMT
 
- VID_DST_D_VIP_CTL
 
- VID_DST_E_DMA_CTL
 
- VID_DST_E_GPCNT
 
- VID_DST_E_GPCNT_CTL
 
- VID_DST_E_PIX_FRMT
 
- VID_DST_E_VIP_CTL
 
- VID_DST_FORMAT_RGB565
 
- VID_DST_FORMAT_RGB666
 
- VID_DST_FORMAT_RGB666_LOOSE
 
- VID_DST_FORMAT_RGB888
 
- VID_DST_F_DMA_CTL
 
- VID_DST_F_GPCNT
 
- VID_DST_F_GPCNT_CTL
 
- VID_DST_F_PIX_FRMT
 
- VID_DST_F_VIP_CTL
 
- VID_DST_G_DMA_CTL
 
- VID_DST_G_GPCNT
 
- VID_DST_G_GPCNT_CTL
 
- VID_DST_G_PIX_FRMT
 
- VID_DST_G_VIP_CTL
 
- VID_DST_H_DMA_CTL
 
- VID_DST_H_GPCNT
 
- VID_DST_H_GPCNT_CTL
 
- VID_DST_H_PIX_FRMT
 
- VID_DST_H_VIP_CTL
 
- VID_D_CDT
 
- VID_D_DOWN_CLUSTER_1
 
- VID_D_DOWN_CLUSTER_2
 
- VID_D_DOWN_CLUSTER_3
 
- VID_D_DOWN_CLUSTER_4
 
- VID_D_DOWN_CMDS
 
- VID_D_INT_MSK
 
- VID_D_INT_MSTAT
 
- VID_D_INT_SSTAT
 
- VID_D_INT_STAT
 
- VID_D_IQ
 
- VID_D_UP_CLUSTER_1
 
- VID_D_UP_CLUSTER_2
 
- VID_D_UP_CLUSTER_3
 
- VID_D_UP_CLUSTER_4
 
- VID_D_UP_CMDS
 
- VID_ED
 
- VID_EN
 
- VID_ENHANCED_MODE
 
- VID_ERR_COLOR1
 
- VID_ERR_COLOR2
 
- VID_E_CDT
 
- VID_E_DOWN_CLUSTER_1
 
- VID_E_DOWN_CLUSTER_2
 
- VID_E_DOWN_CLUSTER_3
 
- VID_E_DOWN_CLUSTER_4
 
- VID_E_DOWN_CMDS
 
- VID_E_INT_MSK
 
- VID_E_INT_MSTAT
 
- VID_E_INT_SSTAT
 
- VID_E_INT_STAT
 
- VID_E_IQ
 
- VID_E_UP_CLUSTER_1
 
- VID_E_UP_CLUSTER_2
 
- VID_E_UP_CLUSTER_3
 
- VID_E_UP_CLUSTER_4
 
- VID_E_UP_CMDS
 
- VID_FIELD_SW
 
- VID_FMT_AUTO
 
- VID_FMT_NTSC_443
 
- VID_FMT_NTSC_J
 
- VID_FMT_NTSC_M
 
- VID_FMT_PAL_60
 
- VID_FMT_PAL_BDGHI
 
- VID_FMT_PAL_M
 
- VID_FMT_PAL_N
 
- VID_FMT_PAL_NC
 
- VID_FMT_SECAM
 
- VID_FMT_SECAM_60
 
- VID_FORMAT_CHG
 
- VID_F_CDT
 
- VID_F_DOWN_CLUSTER_1
 
- VID_F_DOWN_CLUSTER_2
 
- VID_F_DOWN_CLUSTER_3
 
- VID_F_DOWN_CLUSTER_4
 
- VID_F_DOWN_CMDS
 
- VID_F_INT_MSK
 
- VID_F_INT_MSTAT
 
- VID_F_INT_SSTAT
 
- VID_F_INT_STAT
 
- VID_F_IQ
 
- VID_F_UP_CLUSTER_1
 
- VID_F_UP_CLUSTER_2
 
- VID_F_UP_CLUSTER_3
 
- VID_F_UP_CLUSTER_4
 
- VID_F_UP_CMDS
 
- VID_GCT
 
- VID_G_CDT
 
- VID_G_DOWN_CLUSTER_1
 
- VID_G_DOWN_CLUSTER_2
 
- VID_G_DOWN_CLUSTER_3
 
- VID_G_DOWN_CLUSTER_4
 
- VID_G_DOWN_CMDS
 
- VID_G_INT_MSK
 
- VID_G_INT_MSTAT
 
- VID_G_INT_SSTAT
 
- VID_G_INT_STAT
 
- VID_G_IQ
 
- VID_HBP_TIME
 
- VID_HD_148M
 
- VID_HD_74M
 
- VID_HLINE_TIME
 
- VID_HPOS
 
- VID_HRES_TH
 
- VID_HSA_TIME
 
- VID_HSIZE1
 
- VID_HSIZE2
 
- VID_H_CDT
 
- VID_H_DOWN_CLUSTER_1
 
- VID_H_DOWN_CLUSTER_2
 
- VID_H_DOWN_CLUSTER_3
 
- VID_H_DOWN_CLUSTER_4
 
- VID_H_DOWN_CMDS
 
- VID_H_INT_MSK
 
- VID_H_INT_MSTAT
 
- VID_H_INT_SSTAT
 
- VID_H_INT_STAT
 
- VID_H_IQ
 
- VID_IGNORE_MISS_VSYNC
 
- VID_INTERLACED_EN
 
- VID_IQ_SIZE
 
- VID_IQ_SIZE_DW
 
- VID_I_CDT
 
- VID_I_INT_MSK
 
- VID_I_INT_MSTAT
 
- VID_I_INT_SSTAT
 
- VID_I_INT_STAT
 
- VID_I_IQ
 
- VID_I_UP_CLUSTER_1
 
- VID_I_UP_CLUSTER_2
 
- VID_I_UP_CLUSTER_3
 
- VID_I_UP_CLUSTER_4
 
- VID_I_UP_CMDS
 
- VID_J_CDT
 
- VID_J_INT_MSK
 
- VID_J_INT_MSTAT
 
- VID_J_INT_SSTAT
 
- VID_J_INT_STAT
 
- VID_J_IQ
 
- VID_J_UP_CLUSTER_1
 
- VID_J_UP_CLUSTER_2
 
- VID_J_UP_CLUSTER_3
 
- VID_J_UP_CLUSTER_4
 
- VID_J_UP_CMDS
 
- VID_KEY1
 
- VID_KEY2
 
- VID_LSB_ADDR
 
- VID_MAIN_CTL
 
- VID_MASK
 
- VID_MAX_HEIGHT
 
- VID_MAX_WIDTH
 
- VID_MEM_LIMIT
 
- VID_MIN_HD_HEIGHT
 
- VID_MIN_HEIGHT
 
- VID_MIN_WIDTH
 
- VID_MN_GEN
 
- VID_MODE_CFG
 
- VID_MODE_CHANNEL_NUMBER_MASK
 
- VID_MODE_CHANNEL_NUMBER_SHIFT
 
- VID_MODE_FORMAT_MASK
 
- VID_MODE_FORMAT_RGB565
 
- VID_MODE_FORMAT_RGB666
 
- VID_MODE_FORMAT_RGB666_PACKED
 
- VID_MODE_FORMAT_RGB888
 
- VID_MODE_NOT_SUPPORTED
 
- VID_MODE_STS
 
- VID_MODE_STS_CLR
 
- VID_MODE_STS_CTL
 
- VID_MODE_STS_FLAG
 
- VID_MODE_TYPE_BURST
 
- VID_MODE_TYPE_MASK
 
- VID_MODE_TYPE_NON_BURST_SYNC_EVENTS
 
- VID_MODE_TYPE_NON_BURST_SYNC_PULSES
 
- VID_MODE_VPG_ENABLE
 
- VID_MODE_VPG_HORIZONTAL
 
- VID_MPR0
 
- VID_MPR0_BT601
 
- VID_MPR0_BT709
 
- VID_MPR1
 
- VID_MPR1_BT601
 
- VID_MPR1_BT709
 
- VID_MPR2
 
- VID_MPR2_BT601
 
- VID_MPR2_BT709
 
- VID_MPR3
 
- VID_MPR3_BT601
 
- VID_MPR3_BT709
 
- VID_MSB_ADDR
 
- VID_MST
 
- VID_NONE_PREF
 
- VID_NORMAL_FRAME_MODE
 
- VID_NULL_SIZE
 
- VID_NUM_CHUNKS
 
- VID_OFF
 
- VID_OUTPUT
 
- VID_PAN_SCAN_PREF
 
- VID_PID
 
- VID_PIXEL_MODE_DSC_COMP
 
- VID_PIXEL_MODE_MASK
 
- VID_PIXEL_MODE_RGB101010
 
- VID_PIXEL_MODE_RGB121212
 
- VID_PIXEL_MODE_RGB565
 
- VID_PIXEL_MODE_RGB666
 
- VID_PIXEL_MODE_RGB666_PACKED
 
- VID_PIXEL_MODE_RGB888
 
- VID_PIXEL_MODE_YUV420
 
- VID_PIXEL_MODE_YUV422
 
- VID_PIXEL_MODE_YUV422_24B
 
- VID_PIXEL_MODE_YUV422_PACKED
 
- VID_PKT_SIZE
 
- VID_PKT_TIME
 
- VID_PLL_BYPASS
 
- VID_PLL_DIV
 
- VID_PLL_DIV_1
 
- VID_PLL_DIV_12
 
- VID_PLL_DIV_14
 
- VID_PLL_DIV_15
 
- VID_PLL_DIV_2
 
- VID_PLL_DIV_2p5
 
- VID_PLL_DIV_3
 
- VID_PLL_DIV_3p5
 
- VID_PLL_DIV_3p75
 
- VID_PLL_DIV_4
 
- VID_PLL_DIV_5
 
- VID_PLL_DIV_6
 
- VID_PLL_DIV_6p25
 
- VID_PLL_DIV_7
 
- VID_PLL_DIV_7p5
 
- VID_PLL_EN
 
- VID_PLL_FRAC
 
- VID_PLL_INT_POST
 
- VID_PLL_PRESET
 
- VID_REVISION_1_2
 
- VID_REVISION_1_3
 
- VID_RT
 
- VID_SD
 
- VID_SHIFT
 
- VID_SPDUP
 
- VID_SRC_A_ACTIVE_CTL1
 
- VID_SRC_A_ACTIVE_CTL2
 
- VID_SRC_A_CDT_SZ
 
- VID_SRC_A_DMA_CTL
 
- VID_SRC_A_FMT_CTL
 
- VID_SRC_A_GPCNT
 
- VID_SRC_A_GPCNT_CTL
 
- VID_SRC_B_ACTIVE_CTL1
 
- VID_SRC_B_ACTIVE_CTL2
 
- VID_SRC_B_CDT_SZ
 
- VID_SRC_B_DMA_CTL
 
- VID_SRC_B_FMT_CTL
 
- VID_SRC_B_GPCNT
 
- VID_SRC_B_GPCNT_CTL
 
- VID_SRC_C_ACTIVE_CTL1
 
- VID_SRC_C_ACTIVE_CTL2
 
- VID_SRC_C_CDT_SZ
 
- VID_SRC_C_DMA_CTL
 
- VID_SRC_C_FMT_CTL
 
- VID_SRC_C_GPCNT
 
- VID_SRC_C_GPCNT_CTL
 
- VID_SRC_D_ACTIVE_CTL1
 
- VID_SRC_D_ACTIVE_CTL2
 
- VID_SRC_D_CDT_SZ
 
- VID_SRC_D_DMA_CTL
 
- VID_SRC_D_FMT_CTL
 
- VID_SRC_D_GPCNT
 
- VID_SRC_D_GPCNT_CTL
 
- VID_SRC_E_ACTIVE_CTL1
 
- VID_SRC_E_ACTIVE_CTL2
 
- VID_SRC_E_CDT_SZ
 
- VID_SRC_E_DMA_CTL
 
- VID_SRC_E_FMT_CTL
 
- VID_SRC_E_GPCNT
 
- VID_SRC_E_GPCNT_CTL
 
- VID_SRC_F_ACTIVE_CTL1
 
- VID_SRC_F_ACTIVE_CTL2
 
- VID_SRC_F_CDT_SZ
 
- VID_SRC_F_DMA_CTL
 
- VID_SRC_F_FMT_CTL
 
- VID_SRC_F_GPCNT
 
- VID_SRC_F_GPCNT_CTL
 
- VID_SRC_I_ACTIVE_CTL1
 
- VID_SRC_I_ACTIVE_CTL2
 
- VID_SRC_I_CDT_SZ
 
- VID_SRC_I_DMA_CTL
 
- VID_SRC_I_FMT_CTL
 
- VID_SRC_I_GPCNT
 
- VID_SRC_I_GPCNT_CTL
 
- VID_SRC_J_ACTIVE_CTL1
 
- VID_SRC_J_ACTIVE_CTL2
 
- VID_SRC_J_CDT_SZ
 
- VID_SRC_J_DMA_CTL
 
- VID_SRC_J_FMT_CTL
 
- VID_SRC_J_GPCNT
 
- VID_SRC_J_GPCNT_CTL
 
- VID_STREAM_DISABLE_MASKED
 
- VID_STREAM_DISABLE_UNMASK
 
- VID_SWT
 
- VID_SWT_MASK
 
- VID_SYNC_DLY
 
- VID_TABLE_SIZE
 
- VID_TINT
 
- VID_TINT_DFLT
 
- VID_UPPER_GPIO_CNTL
 
- VID_UPSTREAM_SRAM_CHANNEL_I
 
- VID_UPSTREAM_SRAM_CHANNEL_J
 
- VID_VACTIVE_LINES
 
- VID_VBP_LINES
 
- VID_VCA_SETTING1
 
- VID_VCA_SETTING2
 
- VID_VC_AND_PS_PREF
 
- VID_VERT_COMP_PREF
 
- VID_VFP_LINES
 
- VID_VIDSEL
 
- VID_VIRTCHAN_ID
 
- VID_VPO
 
- VID_VPOS
 
- VID_VPS
 
- VID_VRES_TH
 
- VID_VSA_LINES
 
- VID_VSIZE1
 
- VID_VSIZE2
 
- VID_VSYNC_3DFORMAT_FRAME
 
- VID_VSYNC_3DFORMAT_LINE
 
- VID_VSYNC_3DFORMAT_PIXEL
 
- VID_VSYNC_3DMODE_LANDSCAPE
 
- VID_VSYNC_3DMODE_OFF
 
- VID_VSYNC_3DMODE_PORTRAIT
 
- VID_VSYNC_3D_EN
 
- VID_VSYNC_3D_LR
 
- VID_VSYNC_3D_SECOND_EN
 
- VIETTEL_PRODUCT_VT1000
 
- VIETTEL_VENDOR_ID
 
- VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK
 
- VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT
 
- VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK
 
- VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT
 
- VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY_MASK
 
- VIEWPORT_START_SECONDARY__VIEWPORT_X_START_SECONDARY__SHIFT
 
- VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY_MASK
 
- VIEWPORT_START_SECONDARY__VIEWPORT_Y_START_SECONDARY__SHIFT
 
- VIEWPORT_START__VIEWPORT_X_START_MASK
 
- VIEWPORT_START__VIEWPORT_X_START__SHIFT
 
- VIEWPORT_START__VIEWPORT_Y_START_MASK
 
- VIEWPORT_START__VIEWPORT_Y_START__SHIFT
 
- VIEW_3D_FORMAT_COUNT
 
- VIEW_3D_FORMAT_FIRST
 
- VIEW_3D_FORMAT_FRAME_SEQUENTIAL
 
- VIEW_3D_FORMAT_NONE
 
- VIEW_3D_FORMAT_SIDE_BY_SIDE
 
- VIEW_3D_FORMAT_TOP_AND_BOTTOM
 
- VIEW_PACKET
 
- VIEW_STATS
 
- VIEW_TRANSACTION
 
- VIF1
 
- VIF3
 
- VIFF_REGISTER
 
- VIFF_SRCRT
 
- VIFF_STATIC
 
- VIFF_TUNNEL
 
- VIFF_USE_IFINDEX
 
- VIFM_CLR
 
- VIFM_CLRALL
 
- VIFM_COPY
 
- VIFM_ISSET
 
- VIFM_SAME
 
- VIFM_SET
 
- VIF_ASSIGN
 
- VIF_BYPASS_INTERLACE
 
- VIF_ENTRY
 
- VIF_EXISTS
 
- VIF_LIST_RULE_CLEAR_ALL
 
- VIF_LIST_RULE_CLEAR_FUNC
 
- VIF_LIST_RULE_GET
 
- VIF_LIST_RULE_SET
 
- VIF_PR_ARG
 
- VIF_PR_FMT
 
- VIF_STATE_PRINT
 
- VIF_STATE_PRINT_HEX
 
- VIF_STATE_PRINT_INT
 
- VIF_STATE_PRINT_LHEX
 
- VIF_STATE_PRINT_LLHEX
 
- VIF_STATE_PRINT_LONG
 
- VIF_STATE_PRINT_NSTR
 
- VIF_STATE_PRINT_STR
 
- VIF_STATUS
 
- VIF_STATUS_CONNECTED
 
- VIG_0_QSEED2_SHARP
 
- VIG_CSC_10_EN
 
- VIG_CSC_10_SRC_DATAFMT
 
- VIG_OP_CSC_DST_DATAFMT
 
- VIG_OP_CSC_EN
 
- VIG_OP_CSC_SRC_DATAFMT
 
- VIG_OP_FOIL
 
- VIG_OP_HIST
 
- VIG_OP_MEM_PROT_BLEND
 
- VIG_OP_MEM_PROT_CONT
 
- VIG_OP_MEM_PROT_HUE
 
- VIG_OP_MEM_PROT_SAT
 
- VIG_OP_MEM_PROT_VAL
 
- VIG_OP_PA_EN
 
- VIG_OP_PA_SAT_ZERO_EXP
 
- VIG_OP_SKIN_COL
 
- VIG_OP_SKY_COL
 
- VIG_SDM845_MASK
 
- VIKING_ACENABLE
 
- VIKING_ACTION_MIX
 
- VIKING_BMODE
 
- VIKING_DCENABLE
 
- VIKING_DPENABLE
 
- VIKING_ICENABLE
 
- VIKING_MMODE
 
- VIKING_MMUENABLE
 
- VIKING_NOFAULT
 
- VIKING_PCENABLE
 
- VIKING_PSO
 
- VIKING_PTAG_DIRTY
 
- VIKING_PTAG_SHARED
 
- VIKING_PTAG_VALID
 
- VIKING_REV_12
 
- VIKING_REV_2
 
- VIKING_REV_30
 
- VIKING_REV_35
 
- VIKING_SBENABLE
 
- VIKING_SPENABLE
 
- VIKING_TCENABLE
 
- VIL
 
- VILLA_GLOBAL_CHIP_ID_LSB
 
- VILLA_GLOBAL_CHIP_ID_MSB
 
- VILLA_GLOBAL_GPIO_1_INTS
 
- VIMC_CAP_DRV_NAME
 
- VIMC_CID_TEST_PATTERN
 
- VIMC_CID_VIMC_BASE
 
- VIMC_CID_VIMC_CLASS
 
- VIMC_DEB_BLUE
 
- VIMC_DEB_DRV_NAME
 
- VIMC_DEB_GREEN
 
- VIMC_DEB_RED
 
- VIMC_ENT_LINK
 
- VIMC_FRAME_INDEX
 
- VIMC_FRAME_MAX_HEIGHT
 
- VIMC_FRAME_MAX_WIDTH
 
- VIMC_FRAME_MIN_HEIGHT
 
- VIMC_FRAME_MIN_WIDTH
 
- VIMC_MDEV_MODEL_NAME
 
- VIMC_PDEV_NAME
 
- VIMC_SCA_DRV_NAME
 
- VIMC_SEN_DRV_NAME
 
- VIMC_STREAMER_PIPELINE_MAX_SIZE
 
- VIN
 
- VIN0
 
- VIN1
 
- VINDPM_4200
 
- VINDPM_4280
 
- VINDPM_4360
 
- VINDPM_4440
 
- VINDPM_4520
 
- VINDPM_4600
 
- VINDPM_4680
 
- VINDPM_4760
 
- VINFO
 
- VINF_HGCM_ASYNC_EXECUTE
 
- VINF_SUCCESS
 
- VINLOW_CTRL_REG_MASK
 
- VINLOW_ENABLED
 
- VINTR
 
- VINT_CHECK
 
- VINT_EN
 
- VINT_ENABLE
 
- VINT_ENABLE_CLR_OFFSET
 
- VINT_ENABLE_SET_OFFSET
 
- VINT_LEVEL_LOW
 
- VINT_MAP0
 
- VINT_MAP1
 
- VINT_MAP2
 
- VINT_MARK
 
- VINT_OFFSET
 
- VINT_START
 
- VINT_STAT
 
- VINT_STATUS_MASKED_OFFSET
 
- VINT_STATUS_OFFSET
 
- VINT_TYPE_EDGE
 
- VINT_VECTOR
 
- VIN_BUF_SIZE
 
- VIN_DATA_PIN_GROUP
 
- VIN_M
 
- VIN_PFC_CLK
 
- VIN_PFC_DAT8
 
- VIN_PFC_PINS
 
- VIN_PFC_SYNC
 
- VIN_RW1C_MASK
 
- VIN_UNIT_ATTRS
 
- VIN_VDD
 
- VIO
 
- VIO0_CLK_MARK
 
- VIO0_D0_MARK
 
- VIO0_D10_MARK
 
- VIO0_D11_MARK
 
- VIO0_D12_MARK
 
- VIO0_D13_MARK
 
- VIO0_D13_PORT22_MARK
 
- VIO0_D13_PORT26_MARK
 
- VIO0_D14_MARK
 
- VIO0_D14_PORT25_MARK
 
- VIO0_D14_PORT95_MARK
 
- VIO0_D15_MARK
 
- VIO0_D15_PORT24_MARK
 
- VIO0_D15_PORT96_MARK
 
- VIO0_D1_MARK
 
- VIO0_D2_MARK
 
- VIO0_D3_MARK
 
- VIO0_D4_MARK
 
- VIO0_D5_MARK
 
- VIO0_D6_MARK
 
- VIO0_D7_MARK
 
- VIO0_D8_MARK
 
- VIO0_D9_MARK
 
- VIO0_FIELD_MARK
 
- VIO0_FLD_MARK
 
- VIO0_HD_MARK
 
- VIO0_VD_MARK
 
- VIO1_CLK_MARK
 
- VIO1_D0_MARK
 
- VIO1_D1_MARK
 
- VIO1_D2_MARK
 
- VIO1_D3_MARK
 
- VIO1_D4_MARK
 
- VIO1_D5_MARK
 
- VIO1_D6_MARK
 
- VIO1_D7_MARK
 
- VIO1_FIELD_MARK
 
- VIO1_FLD_MARK
 
- VIO1_HD_MARK
 
- VIO1_VD_MARK
 
- VIO2_CLK2_MARK
 
- VIO2_CLK3_MARK
 
- VIO2_CLK_MARK
 
- VIO2_D0_MARK
 
- VIO2_D1_MARK
 
- VIO2_D2_MARK
 
- VIO2_D3_MARK
 
- VIO2_D4_MARK
 
- VIO2_D5_MARK
 
- VIO2_D6_MARK
 
- VIO2_D7_MARK
 
- VIO2_FIELD2_MARK
 
- VIO2_FIELD3_MARK
 
- VIO2_FIELD_MARK
 
- VIO2_HD2_MARK
 
- VIO2_HD3_MARK
 
- VIO2_HD_MARK
 
- VIO2_VD2_MARK
 
- VIO2_VD3_MARK
 
- VIO2_VD_MARK
 
- VIOCD_MAJOR
 
- VIODASD_MAJOR
 
- VIOMMU_EVENT_VQ
 
- VIOMMU_FAULT_RESV_MASK
 
- VIOMMU_NR_VQS
 
- VIOMMU_REQUEST_VQ
 
- VIOSRP_ADAPTER_FAIL
 
- VIOSRP_ADAPTER_INFO_TYPE
 
- VIOSRP_AIX_FORMAT
 
- VIOSRP_CAPABILITIES_TYPE
 
- VIOSRP_CRQ_CMD_RSP
 
- VIOSRP_CRQ_FREE
 
- VIOSRP_CRQ_INIT
 
- VIOSRP_CRQ_INIT_COMPLETE
 
- VIOSRP_CRQ_INIT_RSP
 
- VIOSRP_CRQ_XPORT_EVENT
 
- VIOSRP_DEVICE_BUSY
 
- VIOSRP_EMPTY_IU_TYPE
 
- VIOSRP_ENABLE_FAST_FAIL
 
- VIOSRP_ERROR_LOG_TYPE
 
- VIOSRP_H
 
- VIOSRP_INLINE_FORMAT
 
- VIOSRP_LINUX_FORMAT
 
- VIOSRP_MAD_FAILED
 
- VIOSRP_MAD_FORMAT
 
- VIOSRP_MAD_NOT_SUPPORTED
 
- VIOSRP_MAD_SUCCESS
 
- VIOSRP_NONRECOVERABLE_ERR
 
- VIOSRP_OK
 
- VIOSRP_OK2
 
- VIOSRP_OS400_FORMAT
 
- VIOSRP_PARTNER_PANIC
 
- VIOSRP_SRP_FORMAT
 
- VIOSRP_VIOLATES_MAX_XFER
 
- VIOTAPE_MAJOR
 
- VIOVOU
 
- VIO_ACK_DISABLE
 
- VIO_ACK_ENABLE
 
- VIO_ATTR_INFO
 
- VIO_BASE
 
- VIO_BASE_PFO_UA
 
- VIO_BEU0
 
- VIO_BEUI
 
- VIO_CEU0
 
- VIO_CEUI
 
- VIO_CKO1_229
 
- VIO_CKO1_272
 
- VIO_CKO1_MARK
 
- VIO_CKO2_232
 
- VIO_CKO2_271
 
- VIO_CKO2_MARK
 
- VIO_CKO3_233
 
- VIO_CKO3_259
 
- VIO_CKO4_230
 
- VIO_CKO4_273
 
- VIO_CKO5_231
 
- VIO_CKO5_270
 
- VIO_CKO_1_MARK
 
- VIO_CKO_MARK
 
- VIO_CKO_SCIF2_RTS
 
- VIO_CLK
 
- VIO_CLK1_MARK
 
- VIO_CLK2_MARK
 
- VIO_CLK_MARK
 
- VIO_CLK_SCIF1_RTS
 
- VIO_CMO_BALANCE_CHUNK
 
- VIO_CMO_BALANCE_DELAY
 
- VIO_CMO_MIN_ENT
 
- VIO_D0
 
- VIO_D0_LCDLCLK
 
- VIO_D0_MARK
 
- VIO_D1
 
- VIO_D10_MARK
 
- VIO_D11_MARK
 
- VIO_D12_MARK
 
- VIO_D13_MARK
 
- VIO_D14_MARK
 
- VIO_D15_MARK
 
- VIO_D1_MARK
 
- VIO_D2
 
- VIO_D2_MARK
 
- VIO_D3
 
- VIO_D3_MARK
 
- VIO_D4
 
- VIO_D4_MARK
 
- VIO_D5
 
- VIO_D5_MARK
 
- VIO_D5_SCIF1_TXD
 
- VIO_D6
 
- VIO_D6_MARK
 
- VIO_D6_SCIF1_RXD
 
- VIO_D7
 
- VIO_D7_MARK
 
- VIO_D7_SCIF1_SCK
 
- VIO_D8
 
- VIO_D8_MARK
 
- VIO_D9
 
- VIO_D9_MARK
 
- VIO_DEBUG_DATA
 
- VIO_DEBUG_HS
 
- VIO_DESC_ACCEPTED
 
- VIO_DESC_DATA
 
- VIO_DESC_DONE
 
- VIO_DESC_FREE
 
- VIO_DESC_MODE
 
- VIO_DESC_READY
 
- VIO_DISK_ALABEL_LEN
 
- VIO_DISK_NUM_PART
 
- VIO_DISK_VNAME_LEN
 
- VIO_DRING_ACTIVE
 
- VIO_DRING_DATA
 
- VIO_DRING_MODE
 
- VIO_DRING_REG
 
- VIO_DRING_STOPPED
 
- VIO_DRING_UNREG
 
- VIO_DRIVER_RX_RING
 
- VIO_DRIVER_TX_RING
 
- VIO_DR_STATE_RXREG
 
- VIO_DR_STATE_RXREQ
 
- VIO_DR_STATE_TXREG
 
- VIO_DR_STATE_TXREQ
 
- VIO_FIELD_MARK
 
- VIO_FLD_MARK
 
- VIO_FLD_SCIF2_CTS
 
- VIO_HD
 
- VIO_HD1_MARK
 
- VIO_HD2_MARK
 
- VIO_HD_MARK
 
- VIO_HD_SCIF2_RXD
 
- VIO_HS_COMPLETE
 
- VIO_HS_GOTVERS
 
- VIO_HS_GOT_ATTR
 
- VIO_HS_GOT_RDX
 
- VIO_HS_GOT_RDX_ACK
 
- VIO_HS_INVALID
 
- VIO_HS_SENT_DREG
 
- VIO_HS_SENT_RDX
 
- VIO_HS_SENT_RDX_ACK
 
- VIO_ILMAX_MASK
 
- VIO_ILMAX_SHIFT
 
- VIO_IRQ_DISABLE
 
- VIO_IRQ_ENABLE
 
- VIO_MAX_COMPAT_LEN
 
- VIO_MAX_NAME_LEN
 
- VIO_MAX_RING_COOKIES
 
- VIO_MAX_TYPE_LEN
 
- VIO_NEW_DRING_MODE
 
- VIO_PKT_DATA
 
- VIO_PKT_MODE
 
- VIO_RDX
 
- VIO_RX_DRING
 
- VIO_RX_DRING_DATA
 
- VIO_SEL_MASK
 
- VIO_SEL_SHIFT
 
- VIO_SHIFT
 
- VIO_STEM_MARK
 
- VIO_STEM_SCIF2_TXD
 
- VIO_STEX_MARK
 
- VIO_STEX_SCIF2_SCK
 
- VIO_ST_MASK
 
- VIO_ST_SHIFT
 
- VIO_SUBTYPE_ACK
 
- VIO_SUBTYPE_INFO
 
- VIO_SUBTYPE_NACK
 
- VIO_TAG_SIZE
 
- VIO_TX_DRING
 
- VIO_TYPE_CTRL
 
- VIO_TYPE_DATA
 
- VIO_TYPE_ERR
 
- VIO_VCC_MTU_SIZE
 
- VIO_VD
 
- VIO_VD1_MARK
 
- VIO_VD2_MARK
 
- VIO_VD_MARK
 
- VIO_VD_SCIF1_CTS
 
- VIO_VER_INFO
 
- VIO_VEU1
 
- VIO_VEU2HI
 
- VIO_VEUI
 
- VIO_VOU
 
- VIO_VOUI
 
- VIP1_CHAN_NUM_MULT_ANC_A_SRC0
 
- VIP1_CHAN_NUM_MULT_PORT_A_SRC0
 
- VIP1_CHAN_NUM_PORT_A_CHROMA
 
- VIP1_CHAN_NUM_PORT_A_LUMA
 
- VIP1_CHAN_NUM_PORT_A_RGB
 
- VIP1_CHAN_NUM_PORT_B_RGB
 
- VIPER_BCKLIGHT_EN_GPIO
 
- VIPER_BOARD_ISSUE
 
- VIPER_BOARD_VERSION
 
- VIPER_BOOT_PHYS
 
- VIPER_BRIGHTNESS_GPIO
 
- VIPER_CF_CD_GPIO
 
- VIPER_CF_POWER_GPIO
 
- VIPER_CF_RDY_GPIO
 
- VIPER_CPLD_BASE
 
- VIPER_CPLD_GPIO
 
- VIPER_CPLD_P2V
 
- VIPER_CPLD_PHYS
 
- VIPER_CPLD_REVISION
 
- VIPER_CPLD_V2P
 
- VIPER_ETH_DATA_PHYS
 
- VIPER_ETH_GPIO
 
- VIPER_ETH_PHYS
 
- VIPER_FLASH_PHYS
 
- VIPER_HI_IRQ_STATUS
 
- VIPER_ICR
 
- VIPER_ICR_AUTO_CLR
 
- VIPER_ICR_CF_RST
 
- VIPER_ICR_RETRIG
 
- VIPER_ICR_R_DIS
 
- VIPER_INT_WORD
 
- VIPER_JEDEC_ID
 
- VIPER_LCD_EN_GPIO
 
- VIPER_LO_IRQ_STATUS
 
- VIPER_PC104IO_BASE
 
- VIPER_PSU_CLK_GPIO
 
- VIPER_PSU_DATA_GPIO
 
- VIPER_PSU_nCS_LD_GPIO
 
- VIPER_RTC_I2C_SCL_GPIO
 
- VIPER_RTC_I2C_SDA_GPIO
 
- VIPER_TPM_I2C_SCL_GPIO
 
- VIPER_TPM_I2C_SDA_GPIO
 
- VIPER_UARTA_GPIO
 
- VIPER_UARTA_PHYS
 
- VIPER_UARTB_GPIO
 
- VIPER_UARTB_PHYS
 
- VIPER_UART_SHDN_GPIO
 
- VIPER_UPS_GPIO
 
- VIPER_USB_BASE
 
- VIPER_USB_GPIO
 
- VIPER_USB_PHYS
 
- VIPER_VERSION
 
- VIPH_CONTROL
 
- VIP_AND_CAM0_REG2_MASK
 
- VIP_AND_CAM1_REG1_MASK
 
- VIP_AND_CAM1_REG2_MASK
 
- VIP_AND_CAM2_REG1_MASK
 
- VIP_AND_CAM3_REG0_MASK
 
- VIP_AND_CAM3_REG1_MASK
 
- VIP_CHAN_MULT_PORTB_OFFSET
 
- VIP_CHAN_RGB_PORTB_OFFSET
 
- VIP_CHAN_VIP2_OFFSET
 
- VIP_CHAN_YUV_PORTB_OFFSET
 
- VIP_CNTRL_0_MIRR_A
 
- VIP_CNTRL_0_MIRR_B
 
- VIP_CNTRL_0_SWAP_A
 
- VIP_CNTRL_0_SWAP_B
 
- VIP_CNTRL_1_MIRR_C
 
- VIP_CNTRL_1_MIRR_D
 
- VIP_CNTRL_1_SWAP_C
 
- VIP_CNTRL_1_SWAP_D
 
- VIP_CNTRL_2_MIRR_E
 
- VIP_CNTRL_2_MIRR_F
 
- VIP_CNTRL_2_SWAP_E
 
- VIP_CNTRL_2_SWAP_F
 
- VIP_CNTRL_3_DE_INT
 
- VIP_CNTRL_3_EDGE
 
- VIP_CNTRL_3_EMB
 
- VIP_CNTRL_3_H_TGL
 
- VIP_CNTRL_3_SYNC_DE
 
- VIP_CNTRL_3_SYNC_HS
 
- VIP_CNTRL_3_V_TGL
 
- VIP_CNTRL_3_X_TGL
 
- VIP_CNTRL_4_656_ALT
 
- VIP_CNTRL_4_BLANKIT
 
- VIP_CNTRL_4_BLC
 
- VIP_CNTRL_4_CCIR656
 
- VIP_CNTRL_4_TST_656
 
- VIP_CNTRL_4_TST_PAT
 
- VIP_CNTRL_5_CKCASE
 
- VIP_CNTRL_5_SP_CNT
 
- VIP_IH_SRC_ID_END
 
- VIP_IH_SRC_ID_START
 
- VIP_NUM
 
- VIP_PU_PD_CTRL_REG
 
- VIP_REG1_MASK
 
- VIQDA
 
- VIRQ_ARCH_0
 
- VIRQ_ARCH_1
 
- VIRQ_ARCH_2
 
- VIRQ_ARCH_3
 
- VIRQ_ARCH_4
 
- VIRQ_ARCH_5
 
- VIRQ_ARCH_6
 
- VIRQ_ARCH_7
 
- VIRQ_CONSOLE
 
- VIRQ_CON_RING
 
- VIRQ_DEBUG
 
- VIRQ_DEBUGGER
 
- VIRQ_DOM_EXC
 
- VIRQ_ENOMEM
 
- VIRQ_MCA
 
- VIRQ_MEM_EVENT
 
- VIRQ_PCPU_STATE
 
- VIRQ_TBUF
 
- VIRQ_TIMER
 
- VIRQ_XC_RESERVED
 
- VIRQ_XENOPROF
 
- VIRQ_XENPMU
 
- VIRTBALLOON_OOM_NOTIFY_PRIORITY
 
- VIRTCHNL_ACTION_DROP
 
- VIRTCHNL_ACTION_TC_REDIRECT
 
- VIRTCHNL_CHECK_STRUCT_LEN
 
- VIRTCHNL_CHECK_UNION_LEN
 
- VIRTCHNL_ERR_PARAM
 
- VIRTCHNL_EVENT_LINK_CHANGE
 
- VIRTCHNL_EVENT_PF_DRIVER_CLOSE
 
- VIRTCHNL_EVENT_RESET_IMPENDING
 
- VIRTCHNL_EVENT_UNKNOWN
 
- VIRTCHNL_LINK_SPEED_1000MB_SHIFT
 
- VIRTCHNL_LINK_SPEED_100MB
 
- VIRTCHNL_LINK_SPEED_100MB_SHIFT
 
- VIRTCHNL_LINK_SPEED_10GB
 
- VIRTCHNL_LINK_SPEED_10GB_SHIFT
 
- VIRTCHNL_LINK_SPEED_1GB
 
- VIRTCHNL_LINK_SPEED_20GB
 
- VIRTCHNL_LINK_SPEED_20GB_SHIFT
 
- VIRTCHNL_LINK_SPEED_25GB
 
- VIRTCHNL_LINK_SPEED_25GB_SHIFT
 
- VIRTCHNL_LINK_SPEED_2_5GB
 
- VIRTCHNL_LINK_SPEED_2_5GB_SHIFT
 
- VIRTCHNL_LINK_SPEED_40GB
 
- VIRTCHNL_LINK_SPEED_40GB_SHIFT
 
- VIRTCHNL_LINK_SPEED_5GB
 
- VIRTCHNL_LINK_SPEED_5GB_SHIFT
 
- VIRTCHNL_LINK_SPEED_UNKNOWN
 
- VIRTCHNL_OP_ADD_CLOUD_FILTER
 
- VIRTCHNL_OP_ADD_ETH_ADDR
 
- VIRTCHNL_OP_ADD_VLAN
 
- VIRTCHNL_OP_CONFIG_IRQ_MAP
 
- VIRTCHNL_OP_CONFIG_IWARP_IRQ_MAP
 
- VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE
 
- VIRTCHNL_OP_CONFIG_RSS_KEY
 
- VIRTCHNL_OP_CONFIG_RSS_LUT
 
- VIRTCHNL_OP_CONFIG_RX_QUEUE
 
- VIRTCHNL_OP_CONFIG_TX_QUEUE
 
- VIRTCHNL_OP_CONFIG_VSI_QUEUES
 
- VIRTCHNL_OP_DEL_CLOUD_FILTER
 
- VIRTCHNL_OP_DEL_ETH_ADDR
 
- VIRTCHNL_OP_DEL_VLAN
 
- VIRTCHNL_OP_DISABLE_CHANNELS
 
- VIRTCHNL_OP_DISABLE_QUEUES
 
- VIRTCHNL_OP_DISABLE_VLAN_STRIPPING
 
- VIRTCHNL_OP_ENABLE_CHANNELS
 
- VIRTCHNL_OP_ENABLE_QUEUES
 
- VIRTCHNL_OP_ENABLE_VLAN_STRIPPING
 
- VIRTCHNL_OP_EVENT
 
- VIRTCHNL_OP_GET_RSS_HENA_CAPS
 
- VIRTCHNL_OP_GET_STATS
 
- VIRTCHNL_OP_GET_VF_RESOURCES
 
- VIRTCHNL_OP_IWARP
 
- VIRTCHNL_OP_RELEASE_IWARP_IRQ_MAP
 
- VIRTCHNL_OP_REQUEST_QUEUES
 
- VIRTCHNL_OP_RESET_VF
 
- VIRTCHNL_OP_RSVD
 
- VIRTCHNL_OP_SET_RSS_HENA
 
- VIRTCHNL_OP_UNKNOWN
 
- VIRTCHNL_OP_VERSION
 
- VIRTCHNL_RX_HSPLIT_NO_SPLIT
 
- VIRTCHNL_RX_HSPLIT_SPLIT_IP
 
- VIRTCHNL_RX_HSPLIT_SPLIT_L2
 
- VIRTCHNL_RX_HSPLIT_SPLIT_SCTP
 
- VIRTCHNL_RX_HSPLIT_SPLIT_TCP_UDP
 
- VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR
 
- VIRTCHNL_STATUS_ERR_CQP_COMPL_ERROR
 
- VIRTCHNL_STATUS_ERR_INVALID_VF_ID
 
- VIRTCHNL_STATUS_ERR_NOT_SUPPORTED
 
- VIRTCHNL_STATUS_ERR_NO_MEMORY
 
- VIRTCHNL_STATUS_ERR_OPCODE_MISMATCH
 
- VIRTCHNL_STATUS_ERR_PARAM
 
- VIRTCHNL_STATUS_NOT_SUPPORTED
 
- VIRTCHNL_STATUS_SUCCESS
 
- VIRTCHNL_TCP_V4_FLOW
 
- VIRTCHNL_TCP_V6_FLOW
 
- VIRTCHNL_VERSION_MAJOR
 
- VIRTCHNL_VERSION_MINOR
 
- VIRTCHNL_VERSION_MINOR_NO_VF_CAPS
 
- VIRTCHNL_VFR_COMPLETED
 
- VIRTCHNL_VFR_INPROGRESS
 
- VIRTCHNL_VFR_VFACTIVE
 
- VIRTCHNL_VF_CAP_ADV_LINK_SPEED
 
- VIRTCHNL_VF_OFFLOAD_ADQ
 
- VIRTCHNL_VF_OFFLOAD_ENCAP
 
- VIRTCHNL_VF_OFFLOAD_ENCAP_CSUM
 
- VIRTCHNL_VF_OFFLOAD_IWARP
 
- VIRTCHNL_VF_OFFLOAD_L2
 
- VIRTCHNL_VF_OFFLOAD_REQ_QUEUES
 
- VIRTCHNL_VF_OFFLOAD_RSS_AQ
 
- VIRTCHNL_VF_OFFLOAD_RSS_PCTYPE_V2
 
- VIRTCHNL_VF_OFFLOAD_RSS_PF
 
- VIRTCHNL_VF_OFFLOAD_RSS_REG
 
- VIRTCHNL_VF_OFFLOAD_RSVD
 
- VIRTCHNL_VF_OFFLOAD_RX_ENCAP_CSUM
 
- VIRTCHNL_VF_OFFLOAD_RX_POLLING
 
- VIRTCHNL_VF_OFFLOAD_VLAN
 
- VIRTCHNL_VF_OFFLOAD_WB_ON_ITR
 
- VIRTCHNL_VSI_SRIOV
 
- VIRTCHNL_VSI_TYPE_INVALID
 
- VIRTENABLE_F
 
- VIRTENABLE_S
 
- VIRTENABLE_V
 
- VIRTFN_ID_LEN
 
- VIRTGPU_DRM_H
 
- VIRTGPU_EXECBUF_FENCE_FD_IN
 
- VIRTGPU_EXECBUF_FENCE_FD_OUT
 
- VIRTGPU_EXECBUF_FLAGS
 
- VIRTGPU_PARAM_3D_FEATURES
 
- VIRTGPU_PARAM_CAPSET_QUERY_FIX
 
- VIRTGPU_WAIT_NOWAIT
 
- VIRTIN0
 
- VIRTIN1
 
- VIRTIO_9P_MOUNT_TAG
 
- VIRTIO_AIRQ_ISC
 
- VIRTIO_BALLOON_ARRAY_PFNS_MAX
 
- VIRTIO_BALLOON_CMD_ID_DONE
 
- VIRTIO_BALLOON_CMD_ID_STOP
 
- VIRTIO_BALLOON_CONFIG_READ_CMD_ID
 
- VIRTIO_BALLOON_FREE_PAGE_ALLOC_FLAG
 
- VIRTIO_BALLOON_FREE_PAGE_ORDER
 
- VIRTIO_BALLOON_FREE_PAGE_SIZE
 
- VIRTIO_BALLOON_F_DEFLATE_ON_OOM
 
- VIRTIO_BALLOON_F_FREE_PAGE_HINT
 
- VIRTIO_BALLOON_F_MUST_TELL_HOST
 
- VIRTIO_BALLOON_F_PAGE_POISON
 
- VIRTIO_BALLOON_F_STATS_VQ
 
- VIRTIO_BALLOON_PAGES_PER_PAGE
 
- VIRTIO_BALLOON_PFN_SHIFT
 
- VIRTIO_BALLOON_S_AVAIL
 
- VIRTIO_BALLOON_S_CACHES
 
- VIRTIO_BALLOON_S_HTLB_PGALLOC
 
- VIRTIO_BALLOON_S_HTLB_PGFAIL
 
- VIRTIO_BALLOON_S_MAJFLT
 
- VIRTIO_BALLOON_S_MEMFREE
 
- VIRTIO_BALLOON_S_MEMTOT
 
- VIRTIO_BALLOON_S_MINFLT
 
- VIRTIO_BALLOON_S_NAMES
 
- VIRTIO_BALLOON_S_NAMES_WITH_PREFIX
 
- VIRTIO_BALLOON_S_NR
 
- VIRTIO_BALLOON_S_SWAP_IN
 
- VIRTIO_BALLOON_S_SWAP_OUT
 
- VIRTIO_BALLOON_VQ_DEFLATE
 
- VIRTIO_BALLOON_VQ_FREE_PAGE
 
- VIRTIO_BALLOON_VQ_INFLATE
 
- VIRTIO_BALLOON_VQ_MAX
 
- VIRTIO_BALLOON_VQ_STATS
 
- VIRTIO_BLK_F_BARRIER
 
- VIRTIO_BLK_F_BLK_SIZE
 
- VIRTIO_BLK_F_CONFIG_WCE
 
- VIRTIO_BLK_F_DISCARD
 
- VIRTIO_BLK_F_FLUSH
 
- VIRTIO_BLK_F_GEOMETRY
 
- VIRTIO_BLK_F_MQ
 
- VIRTIO_BLK_F_RO
 
- VIRTIO_BLK_F_SCSI
 
- VIRTIO_BLK_F_SEG_MAX
 
- VIRTIO_BLK_F_SIZE_MAX
 
- VIRTIO_BLK_F_TOPOLOGY
 
- VIRTIO_BLK_F_WCE
 
- VIRTIO_BLK_F_WRITE_ZEROES
 
- VIRTIO_BLK_ID_BYTES
 
- VIRTIO_BLK_S_IOERR
 
- VIRTIO_BLK_S_OK
 
- VIRTIO_BLK_S_UNSUPP
 
- VIRTIO_BLK_T_BARRIER
 
- VIRTIO_BLK_T_DISCARD
 
- VIRTIO_BLK_T_FLUSH
 
- VIRTIO_BLK_T_GET_ID
 
- VIRTIO_BLK_T_IN
 
- VIRTIO_BLK_T_OUT
 
- VIRTIO_BLK_T_SCSI_CMD
 
- VIRTIO_BLK_T_WRITE_ZEROES
 
- VIRTIO_BLK_WRITE_ZEROES_FLAG_UNMAP
 
- VIRTIO_CAIF_H
 
- VIRTIO_CCW_CONFIG_SIZE
 
- VIRTIO_CCW_DOING_READ_CONFIG
 
- VIRTIO_CCW_DOING_READ_FEAT
 
- VIRTIO_CCW_DOING_READ_STATUS
 
- VIRTIO_CCW_DOING_READ_VQ_CONF
 
- VIRTIO_CCW_DOING_RESET
 
- VIRTIO_CCW_DOING_SET_CONF_IND
 
- VIRTIO_CCW_DOING_SET_IND
 
- VIRTIO_CCW_DOING_SET_IND_ADAPTER
 
- VIRTIO_CCW_DOING_SET_VIRTIO_REV
 
- VIRTIO_CCW_DOING_SET_VQ
 
- VIRTIO_CCW_DOING_WRITE_CONFIG
 
- VIRTIO_CCW_DOING_WRITE_FEAT
 
- VIRTIO_CCW_DOING_WRITE_STATUS
 
- VIRTIO_CCW_INTPARM_MASK
 
- VIRTIO_CCW_REV_MAX
 
- VIRTIO_CONFIG_S_ACKNOWLEDGE
 
- VIRTIO_CONFIG_S_DRIVER
 
- VIRTIO_CONFIG_S_DRIVER_OK
 
- VIRTIO_CONFIG_S_FAILED
 
- VIRTIO_CONFIG_S_FEATURES_OK
 
- VIRTIO_CONFIG_S_NEEDS_RESET
 
- VIRTIO_CONSOLE_BAD_ID
 
- VIRTIO_CONSOLE_CONSOLE_PORT
 
- VIRTIO_CONSOLE_DEVICE_READY
 
- VIRTIO_CONSOLE_FD
 
- VIRTIO_CONSOLE_F_EMERG_WRITE
 
- VIRTIO_CONSOLE_F_MULTIPORT
 
- VIRTIO_CONSOLE_F_SIZE
 
- VIRTIO_CONSOLE_PORT_ADD
 
- VIRTIO_CONSOLE_PORT_NAME
 
- VIRTIO_CONSOLE_PORT_OPEN
 
- VIRTIO_CONSOLE_PORT_READY
 
- VIRTIO_CONSOLE_PORT_REMOVE
 
- VIRTIO_CONSOLE_RESIZE
 
- VIRTIO_CRYPTO_AEAD_CCM
 
- VIRTIO_CRYPTO_AEAD_CHACHA20_POLY1305
 
- VIRTIO_CRYPTO_AEAD_CREATE_SESSION
 
- VIRTIO_CRYPTO_AEAD_DECRYPT
 
- VIRTIO_CRYPTO_AEAD_DESTROY_SESSION
 
- VIRTIO_CRYPTO_AEAD_ENCRYPT
 
- VIRTIO_CRYPTO_AEAD_GCM
 
- VIRTIO_CRYPTO_BADMSG
 
- VIRTIO_CRYPTO_CIPHER_3DES_CBC
 
- VIRTIO_CRYPTO_CIPHER_3DES_CTR
 
- VIRTIO_CRYPTO_CIPHER_3DES_ECB
 
- VIRTIO_CRYPTO_CIPHER_AES_CBC
 
- VIRTIO_CRYPTO_CIPHER_AES_CTR
 
- VIRTIO_CRYPTO_CIPHER_AES_ECB
 
- VIRTIO_CRYPTO_CIPHER_AES_F8
 
- VIRTIO_CRYPTO_CIPHER_AES_XTS
 
- VIRTIO_CRYPTO_CIPHER_ARC4
 
- VIRTIO_CRYPTO_CIPHER_CREATE_SESSION
 
- VIRTIO_CRYPTO_CIPHER_DECRYPT
 
- VIRTIO_CRYPTO_CIPHER_DESTROY_SESSION
 
- VIRTIO_CRYPTO_CIPHER_DES_CBC
 
- VIRTIO_CRYPTO_CIPHER_DES_ECB
 
- VIRTIO_CRYPTO_CIPHER_ENCRYPT
 
- VIRTIO_CRYPTO_CIPHER_KASUMI_F8
 
- VIRTIO_CRYPTO_CIPHER_SNOW3G_UEA2
 
- VIRTIO_CRYPTO_CIPHER_ZUC_EEA3
 
- VIRTIO_CRYPTO_ERR
 
- VIRTIO_CRYPTO_HASH
 
- VIRTIO_CRYPTO_HASH_CREATE_SESSION
 
- VIRTIO_CRYPTO_HASH_DESTROY_SESSION
 
- VIRTIO_CRYPTO_HASH_MD5
 
- VIRTIO_CRYPTO_HASH_SHA1
 
- VIRTIO_CRYPTO_HASH_SHA3_224
 
- VIRTIO_CRYPTO_HASH_SHA3_256
 
- VIRTIO_CRYPTO_HASH_SHA3_384
 
- VIRTIO_CRYPTO_HASH_SHA3_512
 
- VIRTIO_CRYPTO_HASH_SHA3_SHAKE128
 
- VIRTIO_CRYPTO_HASH_SHA3_SHAKE256
 
- VIRTIO_CRYPTO_HASH_SHA_224
 
- VIRTIO_CRYPTO_HASH_SHA_256
 
- VIRTIO_CRYPTO_HASH_SHA_384
 
- VIRTIO_CRYPTO_HASH_SHA_512
 
- VIRTIO_CRYPTO_INVSESS
 
- VIRTIO_CRYPTO_MAC
 
- VIRTIO_CRYPTO_MAC_CBCMAC_AES
 
- VIRTIO_CRYPTO_MAC_CBCMAC_KASUMI_F9
 
- VIRTIO_CRYPTO_MAC_CMAC_3DES
 
- VIRTIO_CRYPTO_MAC_CMAC_AES
 
- VIRTIO_CRYPTO_MAC_CREATE_SESSION
 
- VIRTIO_CRYPTO_MAC_DESTROY_SESSION
 
- VIRTIO_CRYPTO_MAC_GMAC_AES
 
- VIRTIO_CRYPTO_MAC_GMAC_TWOFISH
 
- VIRTIO_CRYPTO_MAC_HMAC_MD5
 
- VIRTIO_CRYPTO_MAC_HMAC_SHA1
 
- VIRTIO_CRYPTO_MAC_HMAC_SHA_224
 
- VIRTIO_CRYPTO_MAC_HMAC_SHA_256
 
- VIRTIO_CRYPTO_MAC_HMAC_SHA_384
 
- VIRTIO_CRYPTO_MAC_HMAC_SHA_512
 
- VIRTIO_CRYPTO_MAC_KASUMI_F9
 
- VIRTIO_CRYPTO_MAC_SNOW3G_UIA2
 
- VIRTIO_CRYPTO_MAC_XCBC_AES
 
- VIRTIO_CRYPTO_MAX_DEVICES
 
- VIRTIO_CRYPTO_NOTSUPP
 
- VIRTIO_CRYPTO_NO_AEAD
 
- VIRTIO_CRYPTO_NO_CIPHER
 
- VIRTIO_CRYPTO_NO_HASH
 
- VIRTIO_CRYPTO_NO_MAC
 
- VIRTIO_CRYPTO_OK
 
- VIRTIO_CRYPTO_OPCODE
 
- VIRTIO_CRYPTO_OP_DECRYPT
 
- VIRTIO_CRYPTO_OP_ENCRYPT
 
- VIRTIO_CRYPTO_SERVICE_AEAD
 
- VIRTIO_CRYPTO_SERVICE_CIPHER
 
- VIRTIO_CRYPTO_SERVICE_HASH
 
- VIRTIO_CRYPTO_SERVICE_MAC
 
- VIRTIO_CRYPTO_SYM_ALG_CHAIN_ORDER_CIPHER_THEN_HASH
 
- VIRTIO_CRYPTO_SYM_ALG_CHAIN_ORDER_HASH_THEN_CIPHER
 
- VIRTIO_CRYPTO_SYM_HASH_MODE_AUTH
 
- VIRTIO_CRYPTO_SYM_HASH_MODE_NESTED
 
- VIRTIO_CRYPTO_SYM_HASH_MODE_PLAIN
 
- VIRTIO_CRYPTO_SYM_OP_ALGORITHM_CHAINING
 
- VIRTIO_CRYPTO_SYM_OP_CIPHER
 
- VIRTIO_CRYPTO_SYM_OP_NONE
 
- VIRTIO_CRYPTO_S_HW_READY
 
- VIRTIO_DEV_ANY_ID
 
- VIRTIO_DRV_H
 
- VIRTIO_F_ANY_LAYOUT
 
- VIRTIO_F_IOMMU_PLATFORM
 
- VIRTIO_F_NOTIFY_ON_EMPTY
 
- VIRTIO_F_ORDER_PLATFORM
 
- VIRTIO_F_RING_PACKED
 
- VIRTIO_F_SR_IOV
 
- VIRTIO_F_VERSION_1
 
- VIRTIO_GPU_CAPSET_VIRGL
 
- VIRTIO_GPU_CAPSET_VIRGL2
 
- VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE
 
- VIRTIO_GPU_CMD_CTX_CREATE
 
- VIRTIO_GPU_CMD_CTX_DESTROY
 
- VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE
 
- VIRTIO_GPU_CMD_GET_CAPSET
 
- VIRTIO_GPU_CMD_GET_CAPSET_INFO
 
- VIRTIO_GPU_CMD_GET_DISPLAY_INFO
 
- VIRTIO_GPU_CMD_GET_EDID
 
- VIRTIO_GPU_CMD_MOVE_CURSOR
 
- VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING
 
- VIRTIO_GPU_CMD_RESOURCE_CREATE_2D
 
- VIRTIO_GPU_CMD_RESOURCE_CREATE_3D
 
- VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING
 
- VIRTIO_GPU_CMD_RESOURCE_FLUSH
 
- VIRTIO_GPU_CMD_RESOURCE_UNREF
 
- VIRTIO_GPU_CMD_SET_SCANOUT
 
- VIRTIO_GPU_CMD_SUBMIT_3D
 
- VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D
 
- VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D
 
- VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D
 
- VIRTIO_GPU_CMD_UPDATE_CURSOR
 
- VIRTIO_GPU_DEBUGFS_ENTRIES
 
- VIRTIO_GPU_EVENT_DISPLAY
 
- VIRTIO_GPU_FLAG_FENCE
 
- VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM
 
- VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM
 
- VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM
 
- VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM
 
- VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM
 
- VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM
 
- VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM
 
- VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM
 
- VIRTIO_GPU_F_EDID
 
- VIRTIO_GPU_F_VIRGL
 
- VIRTIO_GPU_HW_H
 
- VIRTIO_GPU_MAX_SCANOUTS
 
- VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP
 
- VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID
 
- VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER
 
- VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID
 
- VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID
 
- VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY
 
- VIRTIO_GPU_RESP_ERR_UNSPEC
 
- VIRTIO_GPU_RESP_OK_CAPSET
 
- VIRTIO_GPU_RESP_OK_CAPSET_INFO
 
- VIRTIO_GPU_RESP_OK_DISPLAY_INFO
 
- VIRTIO_GPU_RESP_OK_EDID
 
- VIRTIO_GPU_RESP_OK_NODATA
 
- VIRTIO_GPU_UNDEFINED
 
- VIRTIO_ID_9P
 
- VIRTIO_ID_BALLOON
 
- VIRTIO_ID_BLOCK
 
- VIRTIO_ID_CAIF
 
- VIRTIO_ID_CONSOLE
 
- VIRTIO_ID_CRYPTO
 
- VIRTIO_ID_FS
 
- VIRTIO_ID_GPU
 
- VIRTIO_ID_INPUT
 
- VIRTIO_ID_IOMMU
 
- VIRTIO_ID_NET
 
- VIRTIO_ID_PMEM
 
- VIRTIO_ID_RNG
 
- VIRTIO_ID_RPMSG
 
- VIRTIO_ID_RPROC_SERIAL
 
- VIRTIO_ID_SCSI
 
- VIRTIO_ID_VSOCK
 
- VIRTIO_INPUT_CFG_ABS_INFO
 
- VIRTIO_INPUT_CFG_EV_BITS
 
- VIRTIO_INPUT_CFG_ID_DEVIDS
 
- VIRTIO_INPUT_CFG_ID_NAME
 
- VIRTIO_INPUT_CFG_ID_SERIAL
 
- VIRTIO_INPUT_CFG_PROP_BITS
 
- VIRTIO_INPUT_CFG_UNSET
 
- VIRTIO_IOMMU_FAULT_F_ADDRESS
 
- VIRTIO_IOMMU_FAULT_F_EXEC
 
- VIRTIO_IOMMU_FAULT_F_READ
 
- VIRTIO_IOMMU_FAULT_F_WRITE
 
- VIRTIO_IOMMU_FAULT_R_DOMAIN
 
- VIRTIO_IOMMU_FAULT_R_MAPPING
 
- VIRTIO_IOMMU_FAULT_R_UNKNOWN
 
- VIRTIO_IOMMU_F_BYPASS
 
- VIRTIO_IOMMU_F_DOMAIN_RANGE
 
- VIRTIO_IOMMU_F_INPUT_RANGE
 
- VIRTIO_IOMMU_F_MAP_UNMAP
 
- VIRTIO_IOMMU_F_MMIO
 
- VIRTIO_IOMMU_F_PROBE
 
- VIRTIO_IOMMU_MAP_F_MASK
 
- VIRTIO_IOMMU_MAP_F_MMIO
 
- VIRTIO_IOMMU_MAP_F_READ
 
- VIRTIO_IOMMU_MAP_F_WRITE
 
- VIRTIO_IOMMU_PROBE_T_MASK
 
- VIRTIO_IOMMU_PROBE_T_NONE
 
- VIRTIO_IOMMU_PROBE_T_RESV_MEM
 
- VIRTIO_IOMMU_RESV_MEM_T_MSI
 
- VIRTIO_IOMMU_RESV_MEM_T_RESERVED
 
- VIRTIO_IOMMU_S_DEVERR
 
- VIRTIO_IOMMU_S_FAULT
 
- VIRTIO_IOMMU_S_INVAL
 
- VIRTIO_IOMMU_S_IOERR
 
- VIRTIO_IOMMU_S_NOENT
 
- VIRTIO_IOMMU_S_NOMEM
 
- VIRTIO_IOMMU_S_OK
 
- VIRTIO_IOMMU_S_RANGE
 
- VIRTIO_IOMMU_S_UNSUPP
 
- VIRTIO_IOMMU_T_ATTACH
 
- VIRTIO_IOMMU_T_DETACH
 
- VIRTIO_IOMMU_T_MAP
 
- VIRTIO_IOMMU_T_PROBE
 
- VIRTIO_IOMMU_T_UNMAP
 
- VIRTIO_IRQ
 
- VIRTIO_IV_BITS
 
- VIRTIO_MMIO_CONFIG
 
- VIRTIO_MMIO_CONFIG_GENERATION
 
- VIRTIO_MMIO_DEVICE_FEATURES
 
- VIRTIO_MMIO_DEVICE_FEATURES_SEL
 
- VIRTIO_MMIO_DEVICE_ID
 
- VIRTIO_MMIO_DRIVER_FEATURES
 
- VIRTIO_MMIO_DRIVER_FEATURES_SEL
 
- VIRTIO_MMIO_GUEST_PAGE_SIZE
 
- VIRTIO_MMIO_INTERRUPT_ACK
 
- VIRTIO_MMIO_INTERRUPT_STATUS
 
- VIRTIO_MMIO_INT_CONFIG
 
- VIRTIO_MMIO_INT_VRING
 
- VIRTIO_MMIO_MAGIC_VALUE
 
- VIRTIO_MMIO_QUEUE_ALIGN
 
- VIRTIO_MMIO_QUEUE_AVAIL_HIGH
 
- VIRTIO_MMIO_QUEUE_AVAIL_LOW
 
- VIRTIO_MMIO_QUEUE_DESC_HIGH
 
- VIRTIO_MMIO_QUEUE_DESC_LOW
 
- VIRTIO_MMIO_QUEUE_NOTIFY
 
- VIRTIO_MMIO_QUEUE_NUM
 
- VIRTIO_MMIO_QUEUE_NUM_MAX
 
- VIRTIO_MMIO_QUEUE_PFN
 
- VIRTIO_MMIO_QUEUE_READY
 
- VIRTIO_MMIO_QUEUE_SEL
 
- VIRTIO_MMIO_QUEUE_USED_HIGH
 
- VIRTIO_MMIO_QUEUE_USED_LOW
 
- VIRTIO_MMIO_STATUS
 
- VIRTIO_MMIO_VENDOR_ID
 
- VIRTIO_MMIO_VERSION
 
- VIRTIO_MMIO_VRING_ALIGN
 
- VIRTIO_MSI_CONFIG_VECTOR
 
- VIRTIO_MSI_NO_VECTOR
 
- VIRTIO_MSI_QUEUE_VECTOR
 
- VIRTIO_NET_CTRL_ANNOUNCE
 
- VIRTIO_NET_CTRL_ANNOUNCE_ACK
 
- VIRTIO_NET_CTRL_GUEST_OFFLOADS
 
- VIRTIO_NET_CTRL_GUEST_OFFLOADS_SET
 
- VIRTIO_NET_CTRL_MAC
 
- VIRTIO_NET_CTRL_MAC_ADDR_SET
 
- VIRTIO_NET_CTRL_MAC_TABLE_SET
 
- VIRTIO_NET_CTRL_MQ
 
- VIRTIO_NET_CTRL_MQ_VQ_PAIRS_MAX
 
- VIRTIO_NET_CTRL_MQ_VQ_PAIRS_MIN
 
- VIRTIO_NET_CTRL_MQ_VQ_PAIRS_SET
 
- VIRTIO_NET_CTRL_RX
 
- VIRTIO_NET_CTRL_RX_ALLMULTI
 
- VIRTIO_NET_CTRL_RX_ALLUNI
 
- VIRTIO_NET_CTRL_RX_NOBCAST
 
- VIRTIO_NET_CTRL_RX_NOMULTI
 
- VIRTIO_NET_CTRL_RX_NOUNI
 
- VIRTIO_NET_CTRL_RX_PROMISC
 
- VIRTIO_NET_CTRL_VLAN
 
- VIRTIO_NET_CTRL_VLAN_ADD
 
- VIRTIO_NET_CTRL_VLAN_DEL
 
- VIRTIO_NET_ERR
 
- VIRTIO_NET_F_CSUM
 
- VIRTIO_NET_F_CTRL_GUEST_OFFLOADS
 
- VIRTIO_NET_F_CTRL_MAC_ADDR
 
- VIRTIO_NET_F_CTRL_RX
 
- VIRTIO_NET_F_CTRL_RX_EXTRA
 
- VIRTIO_NET_F_CTRL_VLAN
 
- VIRTIO_NET_F_CTRL_VQ
 
- VIRTIO_NET_F_GSO
 
- VIRTIO_NET_F_GUEST_ANNOUNCE
 
- VIRTIO_NET_F_GUEST_CSUM
 
- VIRTIO_NET_F_GUEST_ECN
 
- VIRTIO_NET_F_GUEST_TSO4
 
- VIRTIO_NET_F_GUEST_TSO6
 
- VIRTIO_NET_F_GUEST_UFO
 
- VIRTIO_NET_F_HOST_ECN
 
- VIRTIO_NET_F_HOST_TSO4
 
- VIRTIO_NET_F_HOST_TSO6
 
- VIRTIO_NET_F_HOST_UFO
 
- VIRTIO_NET_F_MAC
 
- VIRTIO_NET_F_MQ
 
- VIRTIO_NET_F_MRG_RXBUF
 
- VIRTIO_NET_F_MTU
 
- VIRTIO_NET_F_SPEED_DUPLEX
 
- VIRTIO_NET_F_STANDBY
 
- VIRTIO_NET_F_STATUS
 
- VIRTIO_NET_HDR_F_DATA_VALID
 
- VIRTIO_NET_HDR_F_NEEDS_CSUM
 
- VIRTIO_NET_HDR_GSO_ECN
 
- VIRTIO_NET_HDR_GSO_NONE
 
- VIRTIO_NET_HDR_GSO_TCPV4
 
- VIRTIO_NET_HDR_GSO_TCPV6
 
- VIRTIO_NET_HDR_GSO_UDP
 
- VIRTIO_NET_OK
 
- VIRTIO_NET_S_ANNOUNCE
 
- VIRTIO_NET_S_LINK_UP
 
- VIRTIO_PARAM
 
- VIRTIO_PCI_ABI_VERSION
 
- VIRTIO_PCI_CAP_BAR
 
- VIRTIO_PCI_CAP_CFG_TYPE
 
- VIRTIO_PCI_CAP_COMMON_CFG
 
- VIRTIO_PCI_CAP_DEVICE_CFG
 
- VIRTIO_PCI_CAP_ISR_CFG
 
- VIRTIO_PCI_CAP_LEN
 
- VIRTIO_PCI_CAP_LENGTH
 
- VIRTIO_PCI_CAP_NEXT
 
- VIRTIO_PCI_CAP_NOTIFY_CFG
 
- VIRTIO_PCI_CAP_OFFSET
 
- VIRTIO_PCI_CAP_PCI_CFG
 
- VIRTIO_PCI_CAP_VNDR
 
- VIRTIO_PCI_COMMON_CFGGENERATION
 
- VIRTIO_PCI_COMMON_DF
 
- VIRTIO_PCI_COMMON_DFSELECT
 
- VIRTIO_PCI_COMMON_GF
 
- VIRTIO_PCI_COMMON_GFSELECT
 
- VIRTIO_PCI_COMMON_MSIX
 
- VIRTIO_PCI_COMMON_NUMQ
 
- VIRTIO_PCI_COMMON_Q_AVAILHI
 
- VIRTIO_PCI_COMMON_Q_AVAILLO
 
- VIRTIO_PCI_COMMON_Q_DESCHI
 
- VIRTIO_PCI_COMMON_Q_DESCLO
 
- VIRTIO_PCI_COMMON_Q_ENABLE
 
- VIRTIO_PCI_COMMON_Q_MSIX
 
- VIRTIO_PCI_COMMON_Q_NOFF
 
- VIRTIO_PCI_COMMON_Q_SELECT
 
- VIRTIO_PCI_COMMON_Q_SIZE
 
- VIRTIO_PCI_COMMON_Q_USEDHI
 
- VIRTIO_PCI_COMMON_Q_USEDLO
 
- VIRTIO_PCI_COMMON_STATUS
 
- VIRTIO_PCI_CONFIG
 
- VIRTIO_PCI_CONFIG_OFF
 
- VIRTIO_PCI_GUEST_FEATURES
 
- VIRTIO_PCI_HOST_FEATURES
 
- VIRTIO_PCI_ISR
 
- VIRTIO_PCI_ISR_CONFIG
 
- VIRTIO_PCI_NOTIFY_CAP_MULT
 
- VIRTIO_PCI_NO_LEGACY
 
- VIRTIO_PCI_QUEUE_ADDR_SHIFT
 
- VIRTIO_PCI_QUEUE_NOTIFY
 
- VIRTIO_PCI_QUEUE_NUM
 
- VIRTIO_PCI_QUEUE_PFN
 
- VIRTIO_PCI_QUEUE_SEL
 
- VIRTIO_PCI_STATUS
 
- VIRTIO_PCI_VRING_ALIGN
 
- VIRTIO_PMEM_REQ_TYPE_FLUSH
 
- VIRTIO_RING_F_EVENT_IDX
 
- VIRTIO_RING_F_INDIRECT_DESC
 
- VIRTIO_RING_H
 
- VIRTIO_RPMSG_F_NS
 
- VIRTIO_SCSI_CDB_DEFAULT_SIZE
 
- VIRTIO_SCSI_CDB_SIZE
 
- VIRTIO_SCSI_EVENT_LEN
 
- VIRTIO_SCSI_EVT_RESET_HARD
 
- VIRTIO_SCSI_EVT_RESET_REMOVED
 
- VIRTIO_SCSI_EVT_RESET_RESCAN
 
- VIRTIO_SCSI_F_CHANGE
 
- VIRTIO_SCSI_F_HOTPLUG
 
- VIRTIO_SCSI_F_INOUT
 
- VIRTIO_SCSI_F_T10_PI
 
- VIRTIO_SCSI_MEMPOOL_SZ
 
- VIRTIO_SCSI_SENSE_DEFAULT_SIZE
 
- VIRTIO_SCSI_SENSE_SIZE
 
- VIRTIO_SCSI_S_ABORTED
 
- VIRTIO_SCSI_S_ACA
 
- VIRTIO_SCSI_S_BAD_TARGET
 
- VIRTIO_SCSI_S_BUSY
 
- VIRTIO_SCSI_S_FAILURE
 
- VIRTIO_SCSI_S_FUNCTION_REJECTED
 
- VIRTIO_SCSI_S_FUNCTION_SUCCEEDED
 
- VIRTIO_SCSI_S_HEAD
 
- VIRTIO_SCSI_S_INCORRECT_LUN
 
- VIRTIO_SCSI_S_NEXUS_FAILURE
 
- VIRTIO_SCSI_S_OK
 
- VIRTIO_SCSI_S_ORDERED
 
- VIRTIO_SCSI_S_OVERRUN
 
- VIRTIO_SCSI_S_RESET
 
- VIRTIO_SCSI_S_SIMPLE
 
- VIRTIO_SCSI_S_TARGET_FAILURE
 
- VIRTIO_SCSI_S_TRANSPORT_FAILURE
 
- VIRTIO_SCSI_T_AN_QUERY
 
- VIRTIO_SCSI_T_AN_SUBSCRIBE
 
- VIRTIO_SCSI_T_ASYNC_NOTIFY
 
- VIRTIO_SCSI_T_EVENTS_MISSED
 
- VIRTIO_SCSI_T_NO_EVENT
 
- VIRTIO_SCSI_T_PARAM_CHANGE
 
- VIRTIO_SCSI_T_TMF
 
- VIRTIO_SCSI_T_TMF_ABORT_TASK
 
- VIRTIO_SCSI_T_TMF_ABORT_TASK_SET
 
- VIRTIO_SCSI_T_TMF_CLEAR_ACA
 
- VIRTIO_SCSI_T_TMF_CLEAR_TASK_SET
 
- VIRTIO_SCSI_T_TMF_I_T_NEXUS_RESET
 
- VIRTIO_SCSI_T_TMF_LOGICAL_UNIT_RESET
 
- VIRTIO_SCSI_T_TMF_QUERY_TASK
 
- VIRTIO_SCSI_T_TMF_QUERY_TASK_SET
 
- VIRTIO_SCSI_T_TRANSPORT_RESET
 
- VIRTIO_SCSI_VQ_BASE
 
- VIRTIO_TRANSPORT_F_END
 
- VIRTIO_TRANSPORT_F_START
 
- VIRTIO_VSOCK_DEFAULT_BUF_SIZE
 
- VIRTIO_VSOCK_DEFAULT_MAX_BUF_SIZE
 
- VIRTIO_VSOCK_DEFAULT_MIN_BUF_SIZE
 
- VIRTIO_VSOCK_DEFAULT_RX_BUF_SIZE
 
- VIRTIO_VSOCK_EVENT_TRANSPORT_RESET
 
- VIRTIO_VSOCK_MAX_BUF_SIZE
 
- VIRTIO_VSOCK_MAX_PKT_BUF_SIZE
 
- VIRTIO_VSOCK_OP_CREDIT_REQUEST
 
- VIRTIO_VSOCK_OP_CREDIT_UPDATE
 
- VIRTIO_VSOCK_OP_INVALID
 
- VIRTIO_VSOCK_OP_REQUEST
 
- VIRTIO_VSOCK_OP_RESPONSE
 
- VIRTIO_VSOCK_OP_RST
 
- VIRTIO_VSOCK_OP_RW
 
- VIRTIO_VSOCK_OP_SHUTDOWN
 
- VIRTIO_VSOCK_SHUTDOWN_RCV
 
- VIRTIO_VSOCK_SHUTDOWN_SEND
 
- VIRTIO_VSOCK_TYPE_STREAM
 
- VIRTIO_XDP_FLAG
 
- VIRTIO_XDP_HEADROOM
 
- VIRTIO_XDP_REDIR
 
- VIRTIO_XDP_TX
 
- VIRTNET_DRIVER_VERSION
 
- VIRTNET_FAIL_ON
 
- VIRTNET_FEATURES
 
- VIRTNET_RQ_STAT
 
- VIRTNET_RQ_STATS_LEN
 
- VIRTNET_RX_PAD
 
- VIRTNET_SQ_STAT
 
- VIRTNET_SQ_STATS_LEN
 
- VIRTOUT0
 
- VIRTOUT1
 
- VIRTQUEUE_NUM
 
- VIRTUAL
 
- VIRTUALIZED_ENDPOINT_INTERRUPT
 
- VIRTUALIZED_ENDPOINT_INTERRUPT_ENABLE
 
- VIRTUAL_APIC_PAGE_ADDR
 
- VIRTUAL_APIC_PAGE_ADDR_HIGH
 
- VIRTUAL_BUG_ON
 
- VIRTUAL_CHANNEL_MASK
 
- VIRTUAL_CHANNEL_NUMBER_0
 
- VIRTUAL_CHANNEL_NUMBER_1
 
- VIRTUAL_CHANNEL_NUMBER_2
 
- VIRTUAL_CHANNEL_NUMBER_3
 
- VIRTUAL_CHANNEL_SHIFT
 
- VIRTUAL_CPU_RX_PORT
 
- VIRTUAL_CPU_TX_PORT
 
- VIRTUAL_ENDPOINTS
 
- VIRTUAL_ENDPOINT_ENABLE
 
- VIRTUAL_IO_FAILED_RETRY
 
- VIRTUAL_IRQS
 
- VIRTUAL_MODE_ENTER
 
- VIRTUAL_PROCESSOR_ID
 
- VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK
 
- VIRT_ADDR
 
- VIRT_ADDRESS
 
- VIRT_BASE
 
- VIRT_CABLE_PLUG_TIMEOUT
 
- VIRT_CTR
 
- VIRT_DMA_H
 
- VIRT_FREQ
 
- VIRT_H
 
- VIRT_IMMR_BASE
 
- VIRT_MAC_SIGNATURE
 
- VIRT_MAC_SIGN_MASK
 
- VIRT_PAGE_BASE
 
- VIRT_PHYS_OFFSET
 
- VIRT_TO_DMA
 
- VIRT_WATCHPOINT
 
- VIRT_WR_DMAE_LEN
 
- VIR_GENERIC
 
- VIS
 
- VISEntry
 
- VISEntryHalf
 
- VISEntryHalfFast
 
- VISExit
 
- VISExitHalf
 
- VISExitHalfFast
 
- VISION_LCD_ENABLE
 
- VISION_PHYS_BASE
 
- VISION_VIRT_BASE
 
- VISITED
 
- VISITED_BOARD
 
- VISITOR_FN
 
- VISITOR_FN_T
 
- VISLANDS30_IV_EXTID_D1_EXT_TIMING_SIGNAL
 
- VISLANDS30_IV_EXTID_D1_EXT_TIMING_SYNC
 
- VISLANDS30_IV_EXTID_D1_EXT_TIMING_SYNC_LOSS
 
- VISLANDS30_IV_EXTID_D1_GRPH_PFLIP
 
- VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT0
 
- VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT1
 
- VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT2
 
- VISLANDS30_IV_EXTID_D1_V_UPDATE_INT
 
- VISLANDS30_IV_EXTID_D2_EXT_TIMING_SIGNAL
 
- VISLANDS30_IV_EXTID_D2_EXT_TIMING_SYNC
 
- VISLANDS30_IV_EXTID_D2_EXT_TIMING_SYNC_LOSS
 
- VISLANDS30_IV_EXTID_D2_GRPH_PFLIP
 
- VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT0
 
- VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT1
 
- VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT2
 
- VISLANDS30_IV_EXTID_D2_V_UPDATE_INT
 
- VISLANDS30_IV_EXTID_D3_EXT_TIMING_SIGNAL
 
- VISLANDS30_IV_EXTID_D3_EXT_TIMING_SYNC
 
- VISLANDS30_IV_EXTID_D3_EXT_TIMING_SYNC_LOSS
 
- VISLANDS30_IV_EXTID_D3_GRPH_PFLIP
 
- VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT0
 
- VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT1
 
- VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT2
 
- VISLANDS30_IV_EXTID_D3_V_UPDATE_INT
 
- VISLANDS30_IV_EXTID_D4_EXT_TIMING_SIGNAL
 
- VISLANDS30_IV_EXTID_D4_EXT_TIMING_SYNC
 
- VISLANDS30_IV_EXTID_D4_EXT_TIMING_SYNC_LOSS
 
- VISLANDS30_IV_EXTID_D4_GRPH_PFLIP
 
- VISLANDS30_IV_EXTID_D4_VERTICAL_INTERRUPT0
 
- VISLANDS30_IV_EXTID_D4_VERTICAL_INTERRUPT1
 
- VISLANDS30_IV_EXTID_D4_VERTICAL_INTERRUPT2
 
- VISLANDS30_IV_EXTID_D4_V_UPDATE_INT
 
- VISLANDS30_IV_EXTID_D5_EXT_TIMING_SIGNAL
 
- VISLANDS30_IV_EXTID_D5_EXT_TIMING_SYNC
 
- VISLANDS30_IV_EXTID_D5_EXT_TIMING_SYNC_LOSS
 
- VISLANDS30_IV_EXTID_D5_GRPH_PFLIP
 
- VISLANDS30_IV_EXTID_D5_VERTICAL_INTERRUPT0
 
- VISLANDS30_IV_EXTID_D5_VERTICAL_INTERRUPT1
 
- VISLANDS30_IV_EXTID_D5_VERTICAL_INTERRUPT2
 
- VISLANDS30_IV_EXTID_D5_V_UPDATE_INT
 
- VISLANDS30_IV_EXTID_D6_GRPH_PFLIP
 
- VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT0
 
- VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT1
 
- VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT2
 
- VISLANDS30_IV_EXTID_D6_V_UPDATE_INT
 
- VISLANDS30_IV_EXTID_HOTPLUG_DETECT_A
 
- VISLANDS30_IV_EXTID_HOTPLUG_DETECT_B
 
- VISLANDS30_IV_EXTID_HOTPLUG_DETECT_C
 
- VISLANDS30_IV_EXTID_HOTPLUG_DETECT_D
 
- VISLANDS30_IV_EXTID_HOTPLUG_DETECT_E
 
- VISLANDS30_IV_EXTID_HOTPLUG_DETECT_F
 
- VISLANDS30_IV_EXTID_HPD_RX_A
 
- VISLANDS30_IV_EXTID_HPD_RX_B
 
- VISLANDS30_IV_EXTID_HPD_RX_C
 
- VISLANDS30_IV_EXTID_HPD_RX_D
 
- VISLANDS30_IV_EXTID_HPD_RX_E
 
- VISLANDS30_IV_EXTID_HPD_RX_F
 
- VISLANDS30_IV_EXTID_INVALID
 
- VISLANDS30_IV_EXTID_NONE
 
- VISLANDS30_IV_EXTID_VCE_TRAP_GENERAL_PURPOSE
 
- VISLANDS30_IV_EXTID_VCE_TRAP_LOW_LATENCY
 
- VISLANDS30_IV_EXTID_VCE_TRAP_REAL_TIME
 
- VISLANDS30_IV_EXTID_VM_CONTEXT0_ALL
 
- VISLANDS30_IV_EXTID_VM_CONTEXT1_ALL
 
- VISLANDS30_IV_SDMA_ATOMIC_SRC_ID
 
- VISLANDS30_IV_SRBM_REG_ACCESS_ERROR
 
- VISLANDS30_IV_SRCID_ACP
 
- VISLANDS30_IV_SRCID_BIF_PF_VF_MSGBUF_VALID
 
- VISLANDS30_IV_SRCID_BIF_VF_PF_MSGBUF_ACK
 
- VISLANDS30_IV_SRCID_CG_THERMAL_TRIG
 
- VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW
 
- VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH
 
- VISLANDS30_IV_SRCID_CP_BAD_OPCODE
 
- VISLANDS30_IV_SRCID_CP_COMPUTE_QUERY_STATUS
 
- VISLANDS30_IV_SRCID_CP_ECC_ERROR
 
- VISLANDS30_IV_SRCID_CP_END_OF_PIPE
 
- VISLANDS30_IV_SRCID_CP_GDS_ALLOC_ERROR
 
- VISLANDS30_IV_SRCID_CP_GENERAL_PROT_FAULT
 
- VISLANDS30_IV_SRCID_CP_GUI_BUSY
 
- VISLANDS30_IV_SRCID_CP_GUI_IDLE
 
- VISLANDS30_IV_SRCID_CP_INT_IB1
 
- VISLANDS30_IV_SRCID_CP_INT_IB2
 
- VISLANDS30_IV_SRCID_CP_INT_RB
 
- VISLANDS30_IV_SRCID_CP_PM4_RES_BITS_ERR
 
- VISLANDS30_IV_SRCID_CP_PREEMPT_ACK
 
- VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT
 
- VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT
 
- VISLANDS30_IV_SRCID_CP_SEM_SIG_INCOMPL
 
- VISLANDS30_IV_SRCID_CP_WAIT_MEM_SEM_FAULT
 
- VISLANDS30_IV_SRCID_CP_WAIT_REG_MEM_POLL_TIMEOUT
 
- VISLANDS30_IV_SRCID_D1_EXT_TIMING_SIGNAL
 
- VISLANDS30_IV_SRCID_D1_EXT_TIMING_SYNC
 
- VISLANDS30_IV_SRCID_D1_EXT_TIMING_SYNC_LOSS
 
- VISLANDS30_IV_SRCID_D1_GRPH_PFLIP
 
- VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0
 
- VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT1
 
- VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT2
 
- VISLANDS30_IV_SRCID_D1_V_UPDATE_INT
 
- VISLANDS30_IV_SRCID_D2_EXT_TIMING_SIGNAL
 
- VISLANDS30_IV_SRCID_D2_EXT_TIMING_SYNC
 
- VISLANDS30_IV_SRCID_D2_EXT_TIMING_SYNC_LOSS
 
- VISLANDS30_IV_SRCID_D2_GRPH_PFLIP
 
- VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT0
 
- VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT1
 
- VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT2
 
- VISLANDS30_IV_SRCID_D2_V_UPDATE_INT
 
- VISLANDS30_IV_SRCID_D3_EXT_TIMING_SIGNAL
 
- VISLANDS30_IV_SRCID_D3_EXT_TIMING_SYNC
 
- VISLANDS30_IV_SRCID_D3_EXT_TIMING_SYNC_LOSS
 
- VISLANDS30_IV_SRCID_D3_GRPH_PFLIP
 
- VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT0
 
- VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT1
 
- VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT2
 
- VISLANDS30_IV_SRCID_D3_V_UPDATE_INT
 
- VISLANDS30_IV_SRCID_D4_EXT_TIMING_SIGNAL
 
- VISLANDS30_IV_SRCID_D4_EXT_TIMING_SYNC
 
- VISLANDS30_IV_SRCID_D4_EXT_TIMING_SYNC_LOSS
 
- VISLANDS30_IV_SRCID_D4_GRPH_PFLIP
 
- VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT0
 
- VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT1
 
- VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT2
 
- VISLANDS30_IV_SRCID_D4_V_UPDATE_INT
 
- VISLANDS30_IV_SRCID_D5_EXT_TIMING_SIGNAL
 
- VISLANDS30_IV_SRCID_D5_EXT_TIMING_SYNC
 
- VISLANDS30_IV_SRCID_D5_EXT_TIMING_SYNC_LOSS
 
- VISLANDS30_IV_SRCID_D5_GRPH_PFLIP
 
- VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT0
 
- VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT1
 
- VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT2
 
- VISLANDS30_IV_SRCID_D5_V_UPDATE_INT
 
- VISLANDS30_IV_SRCID_D6_GRPH_PFLIP
 
- VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0
 
- VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT1
 
- VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT2
 
- VISLANDS30_IV_SRCID_D6_V_UPDATE_INT
 
- VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT
 
- VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT
 
- VISLANDS30_IV_SRCID_GPIO_19
 
- VISLANDS30_IV_SRCID_GRBM_READ_TIMEOUT_ERR
 
- VISLANDS30_IV_SRCID_GRBM_REG_GUI_IDLE
 
- VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A
 
- VISLANDS30_IV_SRCID_HOTPLUG_DETECT_B
 
- VISLANDS30_IV_SRCID_HOTPLUG_DETECT_C
 
- VISLANDS30_IV_SRCID_HOTPLUG_DETECT_D
 
- VISLANDS30_IV_SRCID_HOTPLUG_DETECT_E
 
- VISLANDS30_IV_SRCID_HOTPLUG_DETECT_F
 
- VISLANDS30_IV_SRCID_HPD_RX_A
 
- VISLANDS30_IV_SRCID_HPD_RX_B
 
- VISLANDS30_IV_SRCID_HPD_RX_C
 
- VISLANDS30_IV_SRCID_HPD_RX_D
 
- VISLANDS30_IV_SRCID_HPD_RX_E
 
- VISLANDS30_IV_SRCID_HPD_RX_F
 
- VISLANDS30_IV_SRCID_RLC_STRM_PERF_MONITOR
 
- VISLANDS30_IV_SRCID_SDMA_CTXEMPTY
 
- VISLANDS30_IV_SRCID_SDMA_DOORBELL_INVALID
 
- VISLANDS30_IV_SRCID_SDMA_ECC_ERROR
 
- VISLANDS30_IV_SRCID_SDMA_FROZEN
 
- VISLANDS30_IV_SRCID_SDMA_POLL_TIMEOUT
 
- VISLANDS30_IV_SRCID_SDMA_PREEMPT
 
- VISLANDS30_IV_SRCID_SDMA_SEM_INCOMPLETE
 
- VISLANDS30_IV_SRCID_SDMA_SEM_WAIT
 
- VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE
 
- VISLANDS30_IV_SRCID_SDMA_TRAP
 
- VISLANDS30_IV_SRCID_SDMA_VM_HOLE
 
- VISLANDS30_IV_SRCID_SEM_MEM_PROT_FAULT
 
- VISLANDS30_IV_SRCID_SEM_PAGE_INV_FAULT
 
- VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER
 
- VISLANDS30_IV_SRCID_SMU_DISP_TIMER_TRIGGER
 
- VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG
 
- VISLANDS30_IV_SRCID_SRBM_CTX_SWITCH
 
- VISLANDS30_IV_SRCID_SRBM_READ_TIMEOUT_ERR
 
- VISLANDS30_IV_SRCID_SYS_MEM_PROT_FAULT
 
- VISLANDS30_IV_SRCID_SYS_PAGE_INV_FAULT
 
- VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP
 
- VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE
 
- VISLANDS30_IV_SRCID_VCE_TRAP
 
- VISLANDS30_IV_SRCID_VM_CONTEXT_ALL
 
- VISORHBA_ERROR_COUNT
 
- VISORNIC_INFINITE_RSP_WAIT
 
- VISOR_CHANNEL_ENABLE_INTS
 
- VISOR_CHANNEL_IS_POLLING
 
- VISOR_CHANNEL_SIGNATURE
 
- VISOR_CHIPSET_FEATURE_PARA_HOTPLUG
 
- VISOR_CHIPSET_FEATURE_REPLY
 
- VISOR_CLOSE_NOTIFICATION
 
- VISOR_CONSOLEVIDEO_CHANNEL_GUID
 
- VISOR_CONTROLVM_CHANNEL_GUID
 
- VISOR_CONTROLVM_CHANNEL_VERSIONID
 
- VISOR_DRIVER_DISABLES_INTS
 
- VISOR_DRIVER_ENABLES_INTS
 
- VISOR_DRIVER_ENHANCED_RCVBUF_CHECKING
 
- VISOR_DRV_NAME
 
- VISOR_ENDPOINT_1
 
- VISOR_ENDPOINT_2
 
- VISOR_ETH_MAX_MTU
 
- VISOR_FUNCTION_CONSOLE
 
- VISOR_FUNCTION_DEBUGGER
 
- VISOR_FUNCTION_GENERIC
 
- VISOR_FUNCTION_HOTSYNC
 
- VISOR_FUNCTION_REMOTE_FILE_SYS
 
- VISOR_GET_CONNECTION_INFORMATION
 
- VISOR_IOVM_OK_DRIVER_DISABLING_INTS
 
- VISOR_KEYBOARD_CHANNEL_GUID
 
- VISOR_KEYBOARD_CHANNEL_GUID_STR
 
- VISOR_MOUSE_CHANNEL_GUID
 
- VISOR_MOUSE_CHANNEL_GUID_STR
 
- VISOR_REQUEST_BYTES_AVAILABLE
 
- VISOR_SIOVM_GUID
 
- VISOR_VBUS_CHANNEL_GUID
 
- VISOR_VBUS_CHANNEL_VERSIONID
 
- VISOR_VHBA_CHANNEL_GUID
 
- VISOR_VHBA_CHANNEL_GUID_STR
 
- VISOR_VHBA_CHANNEL_VERSIONID
 
- VISOR_VNIC_CHANNEL_GUID
 
- VISOR_VNIC_CHANNEL_GUID_STR
 
- VISOR_VNIC_CHANNEL_VERSIONID
 
- VISUAL_CONFIRM_DISABLE
 
- VISUAL_CONFIRM_HDR
 
- VISUAL_CONFIRM_SURFACE
 
- VIS_CRDR_SDEXTCTRL_AUTOSTOP_SD
 
- VIS_CRDR_SDEXTCTRL_AUTOSTOP_SPI
 
- VIS_CRDR_SDEXTCTRL_BAD_CMDA
 
- VIS_CRDR_SDEXTCTRL_BAD_DATA
 
- VIS_CRDR_SDEXTCTRL_MMC_8BIT
 
- VIS_CRDR_SDEXTCTRL_RELD_BLK
 
- VIS_CRDR_SDEXTCTRL_SHIFT_9
 
- VIS_OPCODE_MASK
 
- VIS_OPCODE_VAL
 
- VIS_OPF_MASK
 
- VIS_OPF_SHIFT
 
- VISenter
 
- VITCURPUN
 
- VITERBI_BER_COUNT_REG_L
 
- VITESSE_PHY_GPIO_CFG
 
- VITESSE_PHY_GPIO_DRIVEOFF
 
- VITESSE_PHY_GPIO_DRIVEON
 
- VITESSE_PHY_GPIO_HIGH
 
- VITESSE_PHY_GPIO_LOW
 
- VITID4_CTRL
 
- VITID5_CTRL
 
- VITINSYNC
 
- VITSCALE
 
- VITS_DTE_MAX_DEVID_OFFSET
 
- VITS_ITE_MAX_EVENTID_OFFSET
 
- VITS_TYPER_DEVBITS
 
- VITS_TYPER_IDBITS
 
- VIT_BERTIME_0
 
- VIT_BERTIME_1
 
- VIT_BERTIME_2
 
- VIT_BER_0
 
- VIT_BER_1
 
- VIT_COR_CTL
 
- VIT_COR_INTEN
 
- VIT_COR_INTSTAT
 
- VIT_COR_MASK
 
- VIT_COR_RESYNC
 
- VIT_CURPUN
 
- VIT_ERRCNT_H
 
- VIT_ERRCNT_L
 
- VIT_ERRCNT_M
 
- VIT_ERRPER_H
 
- VIT_ERRPER_L
 
- VIT_ERRPER_M
 
- VIT_ERR_CNT_0
 
- VIT_ERR_CNT_1
 
- VIT_ERR_CNT_2
 
- VIT_MAXERR
 
- VIT_MODE
 
- VIT_REF0
 
- VIT_REF1
 
- VIT_REF2
 
- VIT_REF3
 
- VIT_REF4
 
- VIT_REF5
 
- VIT_REF6
 
- VIT_SETUP
 
- VIT_SRCH_CTRL_REG_1
 
- VIT_SRCH_CTRL_REG_2
 
- VIT_SRCH_CTRL_REG_3
 
- VIT_SRCH_STATUS_REG
 
- VIT_SYNC_STATUS
 
- VIU1_SEL_VENC_ENCI
 
- VIU1_SEL_VENC_ENCL
 
- VIU1_SEL_VENC_ENCP
 
- VIU1_SEL_VENC_ENCT
 
- VIU1_SEL_VENC_MASK
 
- VIU2_ADDR_END
 
- VIU2_ADDR_START
 
- VIU2_OSD1_BLK0_CFG_W0
 
- VIU2_OSD1_BLK0_CFG_W1
 
- VIU2_OSD1_BLK0_CFG_W2
 
- VIU2_OSD1_BLK0_CFG_W3
 
- VIU2_OSD1_BLK0_CFG_W4
 
- VIU2_OSD1_BLK1_CFG_W0
 
- VIU2_OSD1_BLK1_CFG_W1
 
- VIU2_OSD1_BLK1_CFG_W2
 
- VIU2_OSD1_BLK1_CFG_W3
 
- VIU2_OSD1_BLK1_CFG_W4
 
- VIU2_OSD1_BLK2_CFG_W0
 
- VIU2_OSD1_BLK2_CFG_W1
 
- VIU2_OSD1_BLK2_CFG_W2
 
- VIU2_OSD1_BLK2_CFG_W3
 
- VIU2_OSD1_BLK2_CFG_W4
 
- VIU2_OSD1_BLK3_CFG_W0
 
- VIU2_OSD1_BLK3_CFG_W1
 
- VIU2_OSD1_BLK3_CFG_W2
 
- VIU2_OSD1_BLK3_CFG_W3
 
- VIU2_OSD1_BLK3_CFG_W4
 
- VIU2_OSD1_COLOR
 
- VIU2_OSD1_COLOR_ADDR
 
- VIU2_OSD1_CTRL_STAT
 
- VIU2_OSD1_CTRL_STAT2
 
- VIU2_OSD1_FIFO_CTRL_STAT
 
- VIU2_OSD1_PROT_CTRL
 
- VIU2_OSD1_TCOLOR_AG0
 
- VIU2_OSD1_TCOLOR_AG1
 
- VIU2_OSD1_TCOLOR_AG2
 
- VIU2_OSD1_TCOLOR_AG3
 
- VIU2_OSD1_TEST_RDDATA
 
- VIU2_OSD2_BLK0_CFG_W0
 
- VIU2_OSD2_BLK0_CFG_W1
 
- VIU2_OSD2_BLK0_CFG_W2
 
- VIU2_OSD2_BLK0_CFG_W3
 
- VIU2_OSD2_BLK0_CFG_W4
 
- VIU2_OSD2_BLK1_CFG_W0
 
- VIU2_OSD2_BLK1_CFG_W1
 
- VIU2_OSD2_BLK1_CFG_W2
 
- VIU2_OSD2_BLK1_CFG_W3
 
- VIU2_OSD2_BLK1_CFG_W4
 
- VIU2_OSD2_BLK2_CFG_W0
 
- VIU2_OSD2_BLK2_CFG_W1
 
- VIU2_OSD2_BLK2_CFG_W2
 
- VIU2_OSD2_BLK2_CFG_W3
 
- VIU2_OSD2_BLK2_CFG_W4
 
- VIU2_OSD2_BLK3_CFG_W0
 
- VIU2_OSD2_BLK3_CFG_W1
 
- VIU2_OSD2_BLK3_CFG_W2
 
- VIU2_OSD2_BLK3_CFG_W3
 
- VIU2_OSD2_BLK3_CFG_W4
 
- VIU2_OSD2_COLOR
 
- VIU2_OSD2_COLOR_ADDR
 
- VIU2_OSD2_CTRL_STAT
 
- VIU2_OSD2_CTRL_STAT2
 
- VIU2_OSD2_FIFO_CTRL_STAT
 
- VIU2_OSD2_HL1_H_START_END
 
- VIU2_OSD2_HL1_V_START_END
 
- VIU2_OSD2_HL2_H_START_END
 
- VIU2_OSD2_HL2_V_START_END
 
- VIU2_OSD2_PROT_CTRL
 
- VIU2_OSD2_TCOLOR_AG0
 
- VIU2_OSD2_TCOLOR_AG1
 
- VIU2_OSD2_TCOLOR_AG2
 
- VIU2_OSD2_TCOLOR_AG3
 
- VIU2_OSD2_TEST_RDDATA
 
- VIU2_SEL_VENC_ENCI
 
- VIU2_SEL_VENC_ENCL
 
- VIU2_SEL_VENC_ENCP
 
- VIU2_SEL_VENC_ENCT
 
- VIU2_SEL_VENC_MASK
 
- VIU2_SW_RESET
 
- VIU2_VD1_FMT_CTRL
 
- VIU2_VD1_FMT_W
 
- VIU2_VD1_IF0_CANVAS0
 
- VIU2_VD1_IF0_CANVAS1
 
- VIU2_VD1_IF0_CHROMA0_RPT_PAT
 
- VIU2_VD1_IF0_CHROMA1_RPT_PAT
 
- VIU2_VD1_IF0_CHROMA_PSEL
 
- VIU2_VD1_IF0_CHROMA_X0
 
- VIU2_VD1_IF0_CHROMA_X1
 
- VIU2_VD1_IF0_CHROMA_Y0
 
- VIU2_VD1_IF0_CHROMA_Y1
 
- VIU2_VD1_IF0_DUMMY_PIXEL
 
- VIU2_VD1_IF0_GEN_REG
 
- VIU2_VD1_IF0_GEN_REG2
 
- VIU2_VD1_IF0_LUMA0_RPT_PAT
 
- VIU2_VD1_IF0_LUMA1_RPT_PAT
 
- VIU2_VD1_IF0_LUMA_FIFO_SIZE
 
- VIU2_VD1_IF0_LUMA_PSEL
 
- VIU2_VD1_IF0_LUMA_X0
 
- VIU2_VD1_IF0_LUMA_X1
 
- VIU2_VD1_IF0_LUMA_Y0
 
- VIU2_VD1_IF0_LUMA_Y1
 
- VIU2_VD1_IF0_PROT_CNTL
 
- VIU2_VD1_IF0_RANGE_MAP_CB
 
- VIU2_VD1_IF0_RANGE_MAP_CR
 
- VIU2_VD1_IF0_RANGE_MAP_Y
 
- VIU2_VD1_IF0_RPT_LOOP
 
- VIU_ADDR_END
 
- VIU_ADDR_START
 
- VIU_CFG_CLK
 
- VIU_CTRL0_VD1_AFBC_MASK
 
- VIU_JPEG_WCLK
 
- VIU_LUT_OSD_EOTF
 
- VIU_LUT_OSD_OETF
 
- VIU_M0_ACLK
 
- VIU_M1_ACLK
 
- VIU_MATRIX_OSD
 
- VIU_MATRIX_OSD_EOTF
 
- VIU_MISC_CTRL0
 
- VIU_MISC_CTRL1
 
- VIU_OSD1_BLK0_CFG_W0
 
- VIU_OSD1_BLK0_CFG_W1
 
- VIU_OSD1_BLK0_CFG_W2
 
- VIU_OSD1_BLK0_CFG_W3
 
- VIU_OSD1_BLK0_CFG_W4
 
- VIU_OSD1_BLK1_CFG_W0
 
- VIU_OSD1_BLK1_CFG_W1
 
- VIU_OSD1_BLK1_CFG_W2
 
- VIU_OSD1_BLK1_CFG_W3
 
- VIU_OSD1_BLK1_CFG_W4
 
- VIU_OSD1_BLK2_CFG_W0
 
- VIU_OSD1_BLK2_CFG_W1
 
- VIU_OSD1_BLK2_CFG_W2
 
- VIU_OSD1_BLK2_CFG_W3
 
- VIU_OSD1_BLK2_CFG_W4
 
- VIU_OSD1_BLK3_CFG_W0
 
- VIU_OSD1_BLK3_CFG_W1
 
- VIU_OSD1_BLK3_CFG_W2
 
- VIU_OSD1_BLK3_CFG_W3
 
- VIU_OSD1_BLK3_CFG_W4
 
- VIU_OSD1_COLOR
 
- VIU_OSD1_COLOR_ADDR
 
- VIU_OSD1_CTRL_STAT
 
- VIU_OSD1_CTRL_STAT2
 
- VIU_OSD1_EOTF_COEF00_01
 
- VIU_OSD1_EOTF_COEF02_10
 
- VIU_OSD1_EOTF_COEF11_12
 
- VIU_OSD1_EOTF_COEF20_21
 
- VIU_OSD1_EOTF_COEF22_RS
 
- VIU_OSD1_EOTF_CTL
 
- VIU_OSD1_EOTF_LUT_ADDR_PORT
 
- VIU_OSD1_EOTF_LUT_DATA_PORT
 
- VIU_OSD1_FIFO_CTRL_STAT
 
- VIU_OSD1_MATRIX_COEF00_01
 
- VIU_OSD1_MATRIX_COEF02_10
 
- VIU_OSD1_MATRIX_COEF11_12
 
- VIU_OSD1_MATRIX_COEF20_21
 
- VIU_OSD1_MATRIX_COEF22_30
 
- VIU_OSD1_MATRIX_COEF31_32
 
- VIU_OSD1_MATRIX_COEF40_41
 
- VIU_OSD1_MATRIX_COLMOD_COEF42
 
- VIU_OSD1_MATRIX_CTRL
 
- VIU_OSD1_MATRIX_OFFSET0_1
 
- VIU_OSD1_MATRIX_OFFSET2
 
- VIU_OSD1_MATRIX_PRE_OFFSET0_1
 
- VIU_OSD1_MATRIX_PRE_OFFSET2
 
- VIU_OSD1_OETF_CTL
 
- VIU_OSD1_OETF_LUT_ADDR_PORT
 
- VIU_OSD1_OETF_LUT_DATA_PORT
 
- VIU_OSD1_OSD_BLK_ENABLE
 
- VIU_OSD1_OSD_ENABLE
 
- VIU_OSD1_POSTBLD_SRC_OSD1
 
- VIU_OSD1_POSTBLD_SRC_OSD2
 
- VIU_OSD1_POSTBLD_SRC_VD1
 
- VIU_OSD1_POSTBLD_SRC_VD2
 
- VIU_OSD1_PROT_CTRL
 
- VIU_OSD1_TCOLOR_AG0
 
- VIU_OSD1_TCOLOR_AG1
 
- VIU_OSD1_TCOLOR_AG2
 
- VIU_OSD1_TCOLOR_AG3
 
- VIU_OSD1_TEST_RDDATA
 
- VIU_OSD2_BLK0_CFG_W0
 
- VIU_OSD2_BLK0_CFG_W1
 
- VIU_OSD2_BLK0_CFG_W2
 
- VIU_OSD2_BLK0_CFG_W3
 
- VIU_OSD2_BLK0_CFG_W4
 
- VIU_OSD2_BLK1_CFG_W0
 
- VIU_OSD2_BLK1_CFG_W1
 
- VIU_OSD2_BLK1_CFG_W2
 
- VIU_OSD2_BLK1_CFG_W3
 
- VIU_OSD2_BLK1_CFG_W4
 
- VIU_OSD2_BLK2_CFG_W0
 
- VIU_OSD2_BLK2_CFG_W1
 
- VIU_OSD2_BLK2_CFG_W2
 
- VIU_OSD2_BLK2_CFG_W3
 
- VIU_OSD2_BLK2_CFG_W4
 
- VIU_OSD2_BLK3_CFG_W0
 
- VIU_OSD2_BLK3_CFG_W1
 
- VIU_OSD2_BLK3_CFG_W2
 
- VIU_OSD2_BLK3_CFG_W3
 
- VIU_OSD2_BLK3_CFG_W4
 
- VIU_OSD2_COLOR
 
- VIU_OSD2_COLOR_ADDR
 
- VIU_OSD2_CTRL_STAT
 
- VIU_OSD2_CTRL_STAT2
 
- VIU_OSD2_DIMM_CTRL
 
- VIU_OSD2_FIFO_CTRL_STAT
 
- VIU_OSD2_HL1_H_START_END
 
- VIU_OSD2_HL1_V_START_END
 
- VIU_OSD2_HL2_H_START_END
 
- VIU_OSD2_HL2_V_START_END
 
- VIU_OSD2_MALI_UNPACK_CTRL
 
- VIU_OSD2_MATRIX_COEF00_01
 
- VIU_OSD2_MATRIX_COEF02_10
 
- VIU_OSD2_MATRIX_COEF11_12
 
- VIU_OSD2_MATRIX_COEF20_21
 
- VIU_OSD2_MATRIX_COEF22
 
- VIU_OSD2_MATRIX_CTRL
 
- VIU_OSD2_MATRIX_HL_COLOR
 
- VIU_OSD2_MATRIX_OFFSET0_1
 
- VIU_OSD2_MATRIX_OFFSET2
 
- VIU_OSD2_MATRIX_PRE_OFFSET0_1
 
- VIU_OSD2_MATRIX_PRE_OFFSET2
 
- VIU_OSD2_MATRIX_PROBE_COLOR
 
- VIU_OSD2_MATRIX_PROBE_POS
 
- VIU_OSD2_PROT_CTRL
 
- VIU_OSD2_TCOLOR_AG0
 
- VIU_OSD2_TCOLOR_AG1
 
- VIU_OSD2_TCOLOR_AG2
 
- VIU_OSD2_TCOLOR_AG3
 
- VIU_OSD2_TEST_RDDATA
 
- VIU_OSD3_BLK0_CFG_W0
 
- VIU_OSD3_BLK0_CFG_W1
 
- VIU_OSD3_BLK0_CFG_W2
 
- VIU_OSD3_BLK0_CFG_W3
 
- VIU_OSD3_BLK0_CFG_W4
 
- VIU_OSD3_BLK1_CFG_W4
 
- VIU_OSD3_BLK2_CFG_W4
 
- VIU_OSD3_COLOR
 
- VIU_OSD3_COLOR_ADDR
 
- VIU_OSD3_CTRL_STAT
 
- VIU_OSD3_CTRL_STAT2
 
- VIU_OSD3_DIMM_CTRL
 
- VIU_OSD3_FIFO_CTRL_STAT
 
- VIU_OSD3_MALI_UNPACK_CTRL
 
- VIU_OSD3_PROT_CTRL
 
- VIU_OSD3_TCOLOR_AG0
 
- VIU_OSD3_TCOLOR_AG1
 
- VIU_OSD3_TCOLOR_AG2
 
- VIU_OSD3_TCOLOR_AG3
 
- VIU_OSD3_TEST_RDDATA
 
- VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1
 
- VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2
 
- VIU_OSD_BLENDO_H_START_END
 
- VIU_OSD_BLENDO_V_START_END
 
- VIU_OSD_BLEND_BLEN2_PREMULT_EN
 
- VIU_OSD_BLEND_BLEND0_SIZE
 
- VIU_OSD_BLEND_BLEND1_SIZE
 
- VIU_OSD_BLEND_CTRL
 
- VIU_OSD_BLEND_CTRL1
 
- VIU_OSD_BLEND_CURRENT_XY
 
- VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0
 
- VIU_OSD_BLEND_DIN0_SCOPE_H
 
- VIU_OSD_BLEND_DIN0_SCOPE_V
 
- VIU_OSD_BLEND_DIN1_SCOPE_H
 
- VIU_OSD_BLEND_DIN1_SCOPE_V
 
- VIU_OSD_BLEND_DIN2_SCOPE_H
 
- VIU_OSD_BLEND_DIN2_SCOPE_V
 
- VIU_OSD_BLEND_DIN3_SCOPE_H
 
- VIU_OSD_BLEND_DIN3_SCOPE_V
 
- VIU_OSD_BLEND_DIN_EN
 
- VIU_OSD_BLEND_DUMMY_ALPHA
 
- VIU_OSD_BLEND_DUMMY_DATA
 
- VIU_OSD_BLEND_DUMMY_DATA0
 
- VIU_OSD_BLEND_GEN_CTRL0
 
- VIU_OSD_BLEND_GEN_CTRL1
 
- VIU_OSD_BLEND_HOLD_LINES
 
- VIU_OSD_BLEND_REORDER
 
- VIU_OSD_BLEND_RO_CURRENT_XY
 
- VIU_OSD_DDR_PRIORITY_URGENT
 
- VIU_OSD_FIFO_DEPTH_VAL
 
- VIU_OSD_FIFO_LIMITS
 
- VIU_OSD_HOLD_FIFO_LINES
 
- VIU_OSD_WORDS_PER_BURST
 
- VIU_SW_RESET
 
- VIU_SW_RESET_OSD1
 
- VIU_VD1_FMT_CTRL
 
- VIU_VD1_FMT_W
 
- VIU_VD2_FMT_CTRL
 
- VIU_VD2_FMT_W
 
- VIU_VERSION
 
- VIU_VIDEO_DECODER_ADDR
 
- VIU_VID_MEM_LIMIT
 
- VIU_WCLK
 
- VIVID_CID_ALPHA_MODE
 
- VIVID_CID_BITMASK
 
- VIVID_CID_BOOLEAN
 
- VIVID_CID_BUF_PREPARE_ERROR
 
- VIVID_CID_BUTTON
 
- VIVID_CID_CLEAR_FB
 
- VIVID_CID_COLORSPACE
 
- VIVID_CID_CUSTOM_BASE
 
- VIVID_CID_DISCONNECT
 
- VIVID_CID_DISPLAY_PRESENT
 
- VIVID_CID_DQBUF_ERROR
 
- VIVID_CID_DV_TIMINGS
 
- VIVID_CID_DV_TIMINGS_ASPECT_RATIO
 
- VIVID_CID_DV_TIMINGS_SIGNAL_MODE
 
- VIVID_CID_HAS_COMPOSE_CAP
 
- VIVID_CID_HAS_COMPOSE_OUT
 
- VIVID_CID_HAS_CROP_CAP
 
- VIVID_CID_HAS_CROP_OUT
 
- VIVID_CID_HAS_SCALER_CAP
 
- VIVID_CID_HAS_SCALER_OUT
 
- VIVID_CID_HFLIP
 
- VIVID_CID_HOR_MOVEMENT
 
- VIVID_CID_HSV_ENC
 
- VIVID_CID_INSERT_EAV
 
- VIVID_CID_INSERT_SAV
 
- VIVID_CID_INTEGER
 
- VIVID_CID_INTEGER64
 
- VIVID_CID_INTMENU
 
- VIVID_CID_LIMITED_RGB_RANGE
 
- VIVID_CID_LOOP_VIDEO
 
- VIVID_CID_MAX_EDID_BLOCKS
 
- VIVID_CID_MENU
 
- VIVID_CID_OSD_TEXT_MODE
 
- VIVID_CID_PERCENTAGE_FILL
 
- VIVID_CID_PERC_DROPPED
 
- VIVID_CID_QUANTIZATION
 
- VIVID_CID_QUEUE_ERROR
 
- VIVID_CID_QUEUE_SETUP_ERROR
 
- VIVID_CID_RADIO_RX_RDS_BLOCKIO
 
- VIVID_CID_RADIO_RX_RDS_RBDS
 
- VIVID_CID_RADIO_SEEK_MODE
 
- VIVID_CID_RADIO_SEEK_PROG_LIM
 
- VIVID_CID_RADIO_TX_RDS_BLOCKIO
 
- VIVID_CID_REDUCED_FPS
 
- VIVID_CID_REQ_VALIDATE_ERROR
 
- VIVID_CID_SDR_CAP_FM_DEVIATION
 
- VIVID_CID_SEQ_WRAP
 
- VIVID_CID_SHOW_BORDER
 
- VIVID_CID_SHOW_SQUARE
 
- VIVID_CID_STANDARD
 
- VIVID_CID_START_STR_ERROR
 
- VIVID_CID_STD_ASPECT_RATIO
 
- VIVID_CID_STD_SIGNAL_MODE
 
- VIVID_CID_STRING
 
- VIVID_CID_TEST_PATTERN
 
- VIVID_CID_TIME_WRAP
 
- VIVID_CID_TSTAMP_SRC
 
- VIVID_CID_U16_MATRIX
 
- VIVID_CID_U32_ARRAY
 
- VIVID_CID_U8_4D_ARRAY
 
- VIVID_CID_VBI_CAP_INTERLACED
 
- VIVID_CID_VERT_MOVEMENT
 
- VIVID_CID_VFLIP
 
- VIVID_CID_VIVID_BASE
 
- VIVID_CID_VIVID_CLASS
 
- VIVID_CID_XFER_FUNC
 
- VIVID_CID_YCBCR_ENC
 
- VIVID_CS_170M
 
- VIVID_CS_2020
 
- VIVID_CS_240M
 
- VIVID_CS_709
 
- VIVID_CS_DCI_P3
 
- VIVID_CS_OPRGB
 
- VIVID_CS_SRGB
 
- VIVID_CS_SYS_BG
 
- VIVID_CS_SYS_M
 
- VIVID_HW_SEEK_BOTH
 
- VIVID_HW_SEEK_BOUNDED
 
- VIVID_HW_SEEK_WRAP
 
- VIVID_INVALID_SIGNAL
 
- VIVID_MAX_DEVS
 
- VIVID_MODULE_NAME
 
- VIVID_MPLANAR_FORMATS
 
- VIVID_RDS_GEN_BLKS_PER_GRP
 
- VIVID_RDS_GEN_BLOCKS
 
- VIVID_RDS_GEN_GROUPS
 
- VIVID_RDS_NSEC_PER_BLK
 
- VIVID_WEBCAM_IVALS
 
- VIVID_WEBCAM_SIZES
 
- VIVOPAY_IDS
 
- VIVS_BLT_ENABLE
 
- VIVS_BLT_ENABLE_ENABLE
 
- VIVS_DUMMY
 
- VIVS_DUMMY_DUMMY
 
- VIVS_FE
 
- VIVS_FE_AUTO_FLUSH
 
- VIVS_FE_CMD_STREAM_BASE_ADDR
 
- VIVS_FE_COMMAND_ADDRESS
 
- VIVS_FE_COMMAND_CONTROL
 
- VIVS_FE_COMMAND_CONTROL_ENABLE
 
- VIVS_FE_COMMAND_CONTROL_PREFETCH
 
- VIVS_FE_COMMAND_CONTROL_PREFETCH__MASK
 
- VIVS_FE_COMMAND_CONTROL_PREFETCH__SHIFT
 
- VIVS_FE_DESC_AVAIL
 
- VIVS_FE_DESC_AVAIL_COUNT
 
- VIVS_FE_DESC_AVAIL_COUNT__MASK
 
- VIVS_FE_DESC_AVAIL_COUNT__SHIFT
 
- VIVS_FE_DESC_END
 
- VIVS_FE_DESC_START
 
- VIVS_FE_DMA_ADDRESS
 
- VIVS_FE_DMA_DEBUG_STATE
 
- VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_IDLE
 
- VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_IDXCALC
 
- VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_LDADR
 
- VIVS_FE_DMA_DEBUG_STATE_CAL_STATE__MASK
 
- VIVS_FE_DMA_DEBUG_STATE_CAL_STATE__SHIFT
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_END
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_IDLE
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_REQ
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_START
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE__MASK
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE__SHIFT
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_IDLE
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_RAMVALID
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_VALID
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE__MASK
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE__SHIFT
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DDATA0
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DDATA1
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DRECT0
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DRECT1
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DADR
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DCMD
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DCNTL
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DIDXCNTL
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_ADR0
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_ADR1
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DEC
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DRAW
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DRAWIDX
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_END
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_IDLE
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_INITREQDMA
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LINK
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LOAD0
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LOAD1
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_STALL
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_WAIT
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_WAITFIFO
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__MASK
 
- VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__SHIFT
 
- VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_CAL
 
- VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_IDLE
 
- VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_WAITIDX
 
- VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE__MASK
 
- VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE__SHIFT
 
- VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_CKCACHE
 
- VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_IDLE
 
- VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_MISS
 
- VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE__MASK
 
- VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE__SHIFT
 
- VIVS_FE_DMA_HIGH
 
- VIVS_FE_DMA_LOW
 
- VIVS_FE_DMA_STATUS
 
- VIVS_FE_FENCE_WAIT_DATA_HIGH
 
- VIVS_FE_FENCE_WAIT_DATA_LOW
 
- VIVS_FE_GENERIC_ATTRIB
 
- VIVS_FE_GENERIC_ATTRIB_SCALE
 
- VIVS_FE_GENERIC_ATTRIB_UNK006C0
 
- VIVS_FE_GENERIC_ATTRIB_UNK00700
 
- VIVS_FE_GENERIC_ATTRIB_UNK00740
 
- VIVS_FE_GENERIC_ATTRIB__ESIZE
 
- VIVS_FE_GENERIC_ATTRIB__LEN
 
- VIVS_FE_HALTI5_UNK007C4
 
- VIVS_FE_HALTI5_UNK007D0
 
- VIVS_FE_HALTI5_UNK007D0__ESIZE
 
- VIVS_FE_HALTI5_UNK007D0__LEN
 
- VIVS_FE_HALTI5_UNK007D8
 
- VIVS_FE_INDEX_STREAM_BASE_ADDR
 
- VIVS_FE_INDEX_STREAM_CONTROL
 
- VIVS_FE_INDEX_STREAM_CONTROL_PRIMITIVE_RESTART
 
- VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_CHAR
 
- VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_INT
 
- VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_SHORT
 
- VIVS_FE_INDEX_STREAM_CONTROL_TYPE__MASK
 
- VIVS_FE_INDEX_STREAM_CONTROL_TYPE__SHIFT
 
- VIVS_FE_PRIMITIVE_RESTART_INDEX
 
- VIVS_FE_ROBUSTNESS_UNK007F8
 
- VIVS_FE_UNK00678
 
- VIVS_FE_UNK0067C
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG_END
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG_END__MASK
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_ON
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__MASK
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__SHIFT
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__MASK
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG_START
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__MASK
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG__ESIZE
 
- VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN
 
- VIVS_FE_VERTEX_STREAMS
 
- VIVS_FE_VERTEX_STREAMS_BASE_ADDR
 
- VIVS_FE_VERTEX_STREAMS_CONTROL
 
- VIVS_FE_VERTEX_STREAMS__ESIZE
 
- VIVS_FE_VERTEX_STREAMS__LEN
 
- VIVS_FE_VERTEX_STREAM_BASE_ADDR
 
- VIVS_FE_VERTEX_STREAM_CONTROL
 
- VIVS_GL
 
- VIVS_GL_API_MODE
 
- VIVS_GL_API_MODE_OPENCL
 
- VIVS_GL_API_MODE_OPENGL
 
- VIVS_GL_API_MODE_OPENVG
 
- VIVS_GL_BUG_FIXES
 
- VIVS_GL_CONTEXT_POINTER
 
- VIVS_GL_EVENT
 
- VIVS_GL_EVENT_EVENT_ID
 
- VIVS_GL_EVENT_EVENT_ID__MASK
 
- VIVS_GL_EVENT_EVENT_ID__SHIFT
 
- VIVS_GL_EVENT_FROM_BLT
 
- VIVS_GL_EVENT_FROM_FE
 
- VIVS_GL_EVENT_FROM_PE
 
- VIVS_GL_EVENT_SOURCE
 
- VIVS_GL_EVENT_SOURCE__MASK
 
- VIVS_GL_EVENT_SOURCE__SHIFT
 
- VIVS_GL_FENCE_OUT_ADDRESS
 
- VIVS_GL_FENCE_OUT_DATA_HIGH
 
- VIVS_GL_FENCE_OUT_DATA_LOW
 
- VIVS_GL_FLUSH_CACHE
 
- VIVS_GL_FLUSH_CACHE_COLOR
 
- VIVS_GL_FLUSH_CACHE_DEPTH
 
- VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK12
 
- VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK13
 
- VIVS_GL_FLUSH_CACHE_PE2D
 
- VIVS_GL_FLUSH_CACHE_SHADER_L1
 
- VIVS_GL_FLUSH_CACHE_SHADER_L2
 
- VIVS_GL_FLUSH_CACHE_TEXTURE
 
- VIVS_GL_FLUSH_CACHE_TEXTUREVS
 
- VIVS_GL_FLUSH_CACHE_UNK10
 
- VIVS_GL_FLUSH_CACHE_UNK11
 
- VIVS_GL_FLUSH_MMU
 
- VIVS_GL_FLUSH_MMU_FLUSH_FEMMU
 
- VIVS_GL_FLUSH_MMU_FLUSH_PEMMU
 
- VIVS_GL_FLUSH_MMU_FLUSH_UNK1
 
- VIVS_GL_FLUSH_MMU_FLUSH_UNK2
 
- VIVS_GL_FLUSH_MMU_FLUSH_UNK4
 
- VIVS_GL_GS_UNK0388C
 
- VIVS_GL_GS_UNK038A0
 
- VIVS_GL_GS_UNK038A0__ESIZE
 
- VIVS_GL_GS_UNK038A0__LEN
 
- VIVS_GL_HALTI5_SH_SPECIALS
 
- VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN
 
- VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__MASK
 
- VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__SHIFT
 
- VIVS_GL_HALTI5_SH_SPECIALS_UNK16
 
- VIVS_GL_HALTI5_SH_SPECIALS_UNK16__MASK
 
- VIVS_GL_HALTI5_SH_SPECIALS_UNK16__SHIFT
 
- VIVS_GL_HALTI5_SH_SPECIALS_UNK24
 
- VIVS_GL_HALTI5_SH_SPECIALS_UNK24__MASK
 
- VIVS_GL_HALTI5_SH_SPECIALS_UNK24__SHIFT
 
- VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT
 
- VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK
 
- VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__SHIFT
 
- VIVS_GL_HALTI5_UNK03884
 
- VIVS_GL_HALTI5_UNK038C0
 
- VIVS_GL_HALTI5_UNK038C0__ESIZE
 
- VIVS_GL_HALTI5_UNK038C0__LEN
 
- VIVS_GL_MULTI_SAMPLE_CONFIG
 
- VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES
 
- VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES_MASK
 
- VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__MASK
 
- VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__SHIFT
 
- VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X
 
- VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X
 
- VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_MASK
 
- VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE
 
- VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__MASK
 
- VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__SHIFT
 
- VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12
 
- VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12_MASK
 
- VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__MASK
 
- VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__SHIFT
 
- VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16
 
- VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16_MASK
 
- VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__MASK
 
- VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__SHIFT
 
- VIVS_GL_OCCLUSION_QUERY_ADDR
 
- VIVS_GL_OCCLUSION_QUERY_CONTROL
 
- VIVS_GL_PIPE_SELECT
 
- VIVS_GL_PIPE_SELECT_PIPE
 
- VIVS_GL_PIPE_SELECT_PIPE__MASK
 
- VIVS_GL_PIPE_SELECT_PIPE__SHIFT
 
- VIVS_GL_SECURITY_UNK3900
 
- VIVS_GL_SECURITY_UNK3904
 
- VIVS_GL_SEMAPHORE_TOKEN
 
- VIVS_GL_SEMAPHORE_TOKEN_FROM
 
- VIVS_GL_SEMAPHORE_TOKEN_FROM__MASK
 
- VIVS_GL_SEMAPHORE_TOKEN_FROM__SHIFT
 
- VIVS_GL_SEMAPHORE_TOKEN_TO
 
- VIVS_GL_SEMAPHORE_TOKEN_TO__MASK
 
- VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT
 
- VIVS_GL_SEMAPHORE_TOKEN_UNK28
 
- VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK
 
- VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT
 
- VIVS_GL_SHADER_INDEX
 
- VIVS_GL_STALL_TOKEN
 
- VIVS_GL_STALL_TOKEN_FLIP0
 
- VIVS_GL_STALL_TOKEN_FLIP1
 
- VIVS_GL_STALL_TOKEN_FROM
 
- VIVS_GL_STALL_TOKEN_FROM__MASK
 
- VIVS_GL_STALL_TOKEN_FROM__SHIFT
 
- VIVS_GL_STALL_TOKEN_TO
 
- VIVS_GL_STALL_TOKEN_TO__MASK
 
- VIVS_GL_STALL_TOKEN_TO__SHIFT
 
- VIVS_GL_UNK0382C
 
- VIVS_GL_UNK03834
 
- VIVS_GL_UNK03838
 
- VIVS_GL_UNK03854
 
- VIVS_GL_UNK03A00
 
- VIVS_GL_UNK03A04
 
- VIVS_GL_UNK03A08
 
- VIVS_GL_UNK03A0C
 
- VIVS_GL_UNK03A10
 
- VIVS_GL_VARYING_COMPONENT_USE
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP0
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP0__MASK
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP0__SHIFT
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP1
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP10
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP10__MASK
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP10__SHIFT
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP11
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP11__MASK
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP11__SHIFT
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP12
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP12__MASK
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP12__SHIFT
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP13
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP13__MASK
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP13__SHIFT
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP14
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP14__MASK
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP14__SHIFT
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP15
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP1__MASK
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP1__SHIFT
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP2
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP2__MASK
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP2__SHIFT
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP3
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP3__MASK
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP3__SHIFT
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP4
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP4__MASK
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP4__SHIFT
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP5
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP5__MASK
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP5__SHIFT
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP6
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP6__MASK
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP6__SHIFT
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP7
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP7__MASK
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP7__SHIFT
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP8
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP8__MASK
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP8__SHIFT
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP9
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP9__MASK
 
- VIVS_GL_VARYING_COMPONENT_USE_COMP9__SHIFT
 
- VIVS_GL_VARYING_COMPONENT_USE__ESIZE
 
- VIVS_GL_VARYING_COMPONENT_USE__LEN
 
- VIVS_GL_VARYING_NUM_COMPONENTS
 
- VIVS_GL_VARYING_TOTAL_COMPONENTS
 
- VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM
 
- VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK
 
- VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT
 
- VIVS_GL_VERTEX_ELEMENT_CONFIG
 
- VIVS_HI
 
- VIVS_HI_AUXBIT
 
- VIVS_HI_AXI_CONFIG
 
- VIVS_HI_AXI_CONFIG_ARCACHE
 
- VIVS_HI_AXI_CONFIG_ARCACHE__MASK
 
- VIVS_HI_AXI_CONFIG_ARCACHE__SHIFT
 
- VIVS_HI_AXI_CONFIG_ARID
 
- VIVS_HI_AXI_CONFIG_ARID__MASK
 
- VIVS_HI_AXI_CONFIG_ARID__SHIFT
 
- VIVS_HI_AXI_CONFIG_AWCACHE
 
- VIVS_HI_AXI_CONFIG_AWCACHE__MASK
 
- VIVS_HI_AXI_CONFIG_AWCACHE__SHIFT
 
- VIVS_HI_AXI_CONFIG_AWID
 
- VIVS_HI_AXI_CONFIG_AWID__MASK
 
- VIVS_HI_AXI_CONFIG_AWID__SHIFT
 
- VIVS_HI_AXI_CONTROL
 
- VIVS_HI_AXI_CONTROL_WR_FULL_BURST_MODE
 
- VIVS_HI_AXI_STATUS
 
- VIVS_HI_AXI_STATUS_DET_RD_ERR
 
- VIVS_HI_AXI_STATUS_DET_WR_ERR
 
- VIVS_HI_AXI_STATUS_RD_ERR_ID
 
- VIVS_HI_AXI_STATUS_RD_ERR_ID__MASK
 
- VIVS_HI_AXI_STATUS_RD_ERR_ID__SHIFT
 
- VIVS_HI_AXI_STATUS_WR_ERR_ID
 
- VIVS_HI_AXI_STATUS_WR_ERR_ID__MASK
 
- VIVS_HI_AXI_STATUS_WR_ERR_ID__SHIFT
 
- VIVS_HI_BLT_INTR
 
- VIVS_HI_CACHE_CONTROL
 
- VIVS_HI_CHIP_DATE
 
- VIVS_HI_CHIP_FEATURE
 
- VIVS_HI_CHIP_IDENTITY
 
- VIVS_HI_CHIP_IDENTITY_FAMILY
 
- VIVS_HI_CHIP_IDENTITY_FAMILY__MASK
 
- VIVS_HI_CHIP_IDENTITY_FAMILY__SHIFT
 
- VIVS_HI_CHIP_IDENTITY_PRODUCT
 
- VIVS_HI_CHIP_IDENTITY_PRODUCT__MASK
 
- VIVS_HI_CHIP_IDENTITY_PRODUCT__SHIFT
 
- VIVS_HI_CHIP_IDENTITY_REVISION
 
- VIVS_HI_CHIP_IDENTITY_REVISION__MASK
 
- VIVS_HI_CHIP_IDENTITY_REVISION__SHIFT
 
- VIVS_HI_CHIP_MINOR_FEATURE_0
 
- VIVS_HI_CHIP_MINOR_FEATURE_1
 
- VIVS_HI_CHIP_MINOR_FEATURE_2
 
- VIVS_HI_CHIP_MINOR_FEATURE_3
 
- VIVS_HI_CHIP_MINOR_FEATURE_4
 
- VIVS_HI_CHIP_MINOR_FEATURE_5
 
- VIVS_HI_CHIP_MODEL
 
- VIVS_HI_CHIP_PRODUCT_ID
 
- VIVS_HI_CHIP_REV
 
- VIVS_HI_CHIP_SPECS
 
- VIVS_HI_CHIP_SPECS_2
 
- VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE
 
- VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__MASK
 
- VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__SHIFT
 
- VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT
 
- VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__MASK
 
- VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__SHIFT
 
- VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS
 
- VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__MASK
 
- VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__SHIFT
 
- VIVS_HI_CHIP_SPECS_3
 
- VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT
 
- VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK
 
- VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT
 
- VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT
 
- VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__MASK
 
- VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__SHIFT
 
- VIVS_HI_CHIP_SPECS_4
 
- VIVS_HI_CHIP_SPECS_4_STREAM_COUNT
 
- VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__MASK
 
- VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__SHIFT
 
- VIVS_HI_CHIP_SPECS_PIXEL_PIPES
 
- VIVS_HI_CHIP_SPECS_PIXEL_PIPES__MASK
 
- VIVS_HI_CHIP_SPECS_PIXEL_PIPES__SHIFT
 
- VIVS_HI_CHIP_SPECS_REGISTER_MAX
 
- VIVS_HI_CHIP_SPECS_REGISTER_MAX__MASK
 
- VIVS_HI_CHIP_SPECS_REGISTER_MAX__SHIFT
 
- VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT
 
- VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__MASK
 
- VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__SHIFT
 
- VIVS_HI_CHIP_SPECS_STREAM_COUNT
 
- VIVS_HI_CHIP_SPECS_STREAM_COUNT__MASK
 
- VIVS_HI_CHIP_SPECS_STREAM_COUNT__SHIFT
 
- VIVS_HI_CHIP_SPECS_THREAD_COUNT
 
- VIVS_HI_CHIP_SPECS_THREAD_COUNT__MASK
 
- VIVS_HI_CHIP_SPECS_THREAD_COUNT__SHIFT
 
- VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE
 
- VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__MASK
 
- VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__SHIFT
 
- VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE
 
- VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__MASK
 
- VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__SHIFT
 
- VIVS_HI_CHIP_TIME
 
- VIVS_HI_CLOCK_CONTROL
 
- VIVS_HI_CLOCK_CONTROL_CLK2D_DIS
 
- VIVS_HI_CLOCK_CONTROL_CLK3D_DIS
 
- VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE
 
- VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK
 
- VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__SHIFT
 
- VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS
 
- VIVS_HI_CLOCK_CONTROL_DISABLE_RAM_CLK_GATING
 
- VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD
 
- VIVS_HI_CLOCK_CONTROL_FSCALE_VAL
 
- VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK
 
- VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__SHIFT
 
- VIVS_HI_CLOCK_CONTROL_IDLE_2D
 
- VIVS_HI_CLOCK_CONTROL_IDLE_3D
 
- VIVS_HI_CLOCK_CONTROL_IDLE_VG
 
- VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU
 
- VIVS_HI_CLOCK_CONTROL_SOFT_RESET
 
- VIVS_HI_COMPRESSION_FLAGS
 
- VIVS_HI_COMPRESSION_FLAGS_DEC300
 
- VIVS_HI_GP_OUT0
 
- VIVS_HI_GP_OUT1
 
- VIVS_HI_GP_OUT2
 
- VIVS_HI_IDLE_STATE
 
- VIVS_HI_IDLE_STATE_AXI_LP
 
- VIVS_HI_IDLE_STATE_DE
 
- VIVS_HI_IDLE_STATE_FE
 
- VIVS_HI_IDLE_STATE_FP
 
- VIVS_HI_IDLE_STATE_IM
 
- VIVS_HI_IDLE_STATE_PA
 
- VIVS_HI_IDLE_STATE_PE
 
- VIVS_HI_IDLE_STATE_RA
 
- VIVS_HI_IDLE_STATE_SE
 
- VIVS_HI_IDLE_STATE_SH
 
- VIVS_HI_IDLE_STATE_TS
 
- VIVS_HI_IDLE_STATE_TX
 
- VIVS_HI_IDLE_STATE_VG
 
- VIVS_HI_INTR_ACKNOWLEDGE
 
- VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR
 
- VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC
 
- VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK
 
- VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT
 
- VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION
 
- VIVS_HI_INTR_ENBL
 
- VIVS_HI_INTR_ENBL_INTR_ENBL_VEC
 
- VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__MASK
 
- VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__SHIFT
 
- VIVS_HI_MEMORY_COUNTER_RESET
 
- VIVS_HI_PROFILE_IDLE_CYCLES
 
- VIVS_HI_PROFILE_READ_BURSTS
 
- VIVS_HI_PROFILE_READ_BYTES8
 
- VIVS_HI_PROFILE_READ_LASTS
 
- VIVS_HI_PROFILE_READ_REQUESTS
 
- VIVS_HI_PROFILE_TOTAL_CYCLES
 
- VIVS_HI_PROFILE_WRITE_BURSTS
 
- VIVS_HI_PROFILE_WRITE_BYTES8
 
- VIVS_HI_PROFILE_WRITE_REQUESTS
 
- VIVS_MC
 
- VIVS_MC_BUS_CONFIG
 
- VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG
 
- VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK
 
- VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__SHIFT
 
- VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG
 
- VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK
 
- VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__SHIFT
 
- VIVS_MC_DEBUG_MEMORY
 
- VIVS_MC_DEBUG_MEMORY_COMPRESSION_BYPASS
 
- VIVS_MC_DEBUG_MEMORY_FAST_CLEAR_BYPASS
 
- VIVS_MC_DEBUG_MEMORY_SPECIAL_PATCH_GC320
 
- VIVS_MC_DEBUG_READ0
 
- VIVS_MC_DEBUG_READ1
 
- VIVS_MC_DEBUG_WRITE
 
- VIVS_MC_FLAGS
 
- VIVS_MC_FLAGS_128B_MERGE
 
- VIVS_MC_FLAGS_TPCV11_COMPRESSION
 
- VIVS_MC_L2_CACHE_CONFIG
 
- VIVS_MC_MEMORY_BASE_ADDR_FE
 
- VIVS_MC_MEMORY_BASE_ADDR_PE
 
- VIVS_MC_MEMORY_BASE_ADDR_PEZ
 
- VIVS_MC_MEMORY_BASE_ADDR_RA
 
- VIVS_MC_MEMORY_BASE_ADDR_TX
 
- VIVS_MC_MEMORY_FLUSH
 
- VIVS_MC_MEMORY_TIMING_CONTROL
 
- VIVS_MC_MMU_FE_PAGE_TABLE
 
- VIVS_MC_MMU_PEZ_PAGE_TABLE
 
- VIVS_MC_MMU_PE_PAGE_TABLE
 
- VIVS_MC_MMU_RA_PAGE_TABLE
 
- VIVS_MC_MMU_TX_PAGE_TABLE
 
- VIVS_MC_PROFILE_CONFIG0
 
- VIVS_MC_PROFILE_CONFIG0_DE_RESET
 
- VIVS_MC_PROFILE_CONFIG0_DE__MASK
 
- VIVS_MC_PROFILE_CONFIG0_DE__SHIFT
 
- VIVS_MC_PROFILE_CONFIG0_FE_RESET
 
- VIVS_MC_PROFILE_CONFIG0_FE__MASK
 
- VIVS_MC_PROFILE_CONFIG0_FE__SHIFT
 
- VIVS_MC_PROFILE_CONFIG0_PE_PIXELS_RENDERED_2D
 
- VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_COLOR_PIPE
 
- VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE
 
- VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE
 
- VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE
 
- VIVS_MC_PROFILE_CONFIG0_PE_RESET
 
- VIVS_MC_PROFILE_CONFIG0_PE__MASK
 
- VIVS_MC_PROFILE_CONFIG0_PE__SHIFT
 
- VIVS_MC_PROFILE_CONFIG0_SH_PS_INST_COUNTER
 
- VIVS_MC_PROFILE_CONFIG0_SH_PXL_BRANCH_INST_COUNTER
 
- VIVS_MC_PROFILE_CONFIG0_SH_PXL_TEXLD_INST_COUNTER
 
- VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_PIXEL_COUNTER
 
- VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_VERTICE_COUNTER
 
- VIVS_MC_PROFILE_CONFIG0_SH_RESET
 
- VIVS_MC_PROFILE_CONFIG0_SH_SHADER_CYCLES
 
- VIVS_MC_PROFILE_CONFIG0_SH_VS_INST_COUNTER
 
- VIVS_MC_PROFILE_CONFIG0_SH_VTX_BRANCH_INST_COUNTER
 
- VIVS_MC_PROFILE_CONFIG0_SH_VTX_TEXLD_INST_COUNTER
 
- VIVS_MC_PROFILE_CONFIG0_SH__MASK
 
- VIVS_MC_PROFILE_CONFIG0_SH__SHIFT
 
- VIVS_MC_PROFILE_CONFIG1
 
- VIVS_MC_PROFILE_CONFIG1_PA_CULLED_COUNTER
 
- VIVS_MC_PROFILE_CONFIG1_PA_DEPTH_CLIPPED_COUNTER
 
- VIVS_MC_PROFILE_CONFIG1_PA_INPUT_PRIM_COUNTER
 
- VIVS_MC_PROFILE_CONFIG1_PA_INPUT_VTX_COUNTER
 
- VIVS_MC_PROFILE_CONFIG1_PA_OUTPUT_PRIM_COUNTER
 
- VIVS_MC_PROFILE_CONFIG1_PA_RESET
 
- VIVS_MC_PROFILE_CONFIG1_PA_TRIVIAL_REJECTED_COUNTER
 
- VIVS_MC_PROFILE_CONFIG1_PA__MASK
 
- VIVS_MC_PROFILE_CONFIG1_PA__SHIFT
 
- VIVS_MC_PROFILE_CONFIG1_RA_CULLED_QUAD_COUNT
 
- VIVS_MC_PROFILE_CONFIG1_RA_PIPE_CACHE_MISS_COUNTER
 
- VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_CACHE_MISS_COUNTER
 
- VIVS_MC_PROFILE_CONFIG1_RA_RESET
 
- VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_PRIMITIVE_COUNT
 
- VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_QUAD_COUNT
 
- VIVS_MC_PROFILE_CONFIG1_RA_VALID_PIXEL_COUNT
 
- VIVS_MC_PROFILE_CONFIG1_RA_VALID_QUAD_COUNT_AFTER_EARLY_Z
 
- VIVS_MC_PROFILE_CONFIG1_RA__MASK
 
- VIVS_MC_PROFILE_CONFIG1_RA__SHIFT
 
- VIVS_MC_PROFILE_CONFIG1_SE_CULLED_LINES_COUNT
 
- VIVS_MC_PROFILE_CONFIG1_SE_CULLED_TRIANGLE_COUNT
 
- VIVS_MC_PROFILE_CONFIG1_SE_RESET
 
- VIVS_MC_PROFILE_CONFIG1_SE__MASK
 
- VIVS_MC_PROFILE_CONFIG1_SE__SHIFT
 
- VIVS_MC_PROFILE_CONFIG1_TX_CACHE_HIT_TEXEL_COUNT
 
- VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_COUNT
 
- VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_TEXEL_COUNT
 
- VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_COUNT
 
- VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_IN_8B_COUNT
 
- VIVS_MC_PROFILE_CONFIG1_TX_RESET
 
- VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_BILINEAR_REQUESTS
 
- VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_DISCARDED_TEXTURE_REQUESTS
 
- VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TEXTURE_REQUESTS
 
- VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TRILINEAR_REQUESTS
 
- VIVS_MC_PROFILE_CONFIG1_TX_UNKNOWN
 
- VIVS_MC_PROFILE_CONFIG1_TX__MASK
 
- VIVS_MC_PROFILE_CONFIG1_TX__SHIFT
 
- VIVS_MC_PROFILE_CONFIG2
 
- VIVS_MC_PROFILE_CONFIG2_BLT_UNK0
 
- VIVS_MC_PROFILE_CONFIG2_BLT__MASK
 
- VIVS_MC_PROFILE_CONFIG2_BLT__SHIFT
 
- VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_READ_REQUEST_STALLED
 
- VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_DATA_STALLED
 
- VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_REQUEST_STALLED
 
- VIVS_MC_PROFILE_CONFIG2_HI_RESET
 
- VIVS_MC_PROFILE_CONFIG2_HI__MASK
 
- VIVS_MC_PROFILE_CONFIG2_HI__SHIFT
 
- VIVS_MC_PROFILE_CONFIG2_MC_RESET
 
- VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_IP
 
- VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_PIPELINE
 
- VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_PIPELINE
 
- VIVS_MC_PROFILE_CONFIG2_MC__MASK
 
- VIVS_MC_PROFILE_CONFIG2_MC__SHIFT
 
- VIVS_MC_PROFILE_CONFIG3
 
- VIVS_MC_PROFILE_CYCLE_COUNTER
 
- VIVS_MC_PROFILE_DE_READ
 
- VIVS_MC_PROFILE_FE_READ
 
- VIVS_MC_PROFILE_HI_READ
 
- VIVS_MC_PROFILE_L2_READ
 
- VIVS_MC_PROFILE_MC_READ
 
- VIVS_MC_PROFILE_PA_READ
 
- VIVS_MC_PROFILE_PE_READ
 
- VIVS_MC_PROFILE_RA_READ
 
- VIVS_MC_PROFILE_SE_READ
 
- VIVS_MC_PROFILE_SH_READ
 
- VIVS_MC_PROFILE_TX_READ
 
- VIVS_MC_START_COMPOSITION
 
- VIVS_MMUv2
 
- VIVS_MMUv2_AHB_CONTROL
 
- VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS
 
- VIVS_MMUv2_AHB_CONTROL_RESET
 
- VIVS_MMUv2_AXI_POLICY
 
- VIVS_MMUv2_AXI_POLICY__ESIZE
 
- VIVS_MMUv2_AXI_POLICY__LEN
 
- VIVS_MMUv2_CONFIGURATION
 
- VIVS_MMUv2_CONFIGURATION_ADDRESS
 
- VIVS_MMUv2_CONFIGURATION_ADDRESS_MASK
 
- VIVS_MMUv2_CONFIGURATION_ADDRESS__MASK
 
- VIVS_MMUv2_CONFIGURATION_ADDRESS__SHIFT
 
- VIVS_MMUv2_CONFIGURATION_FLUSH_FLUSH
 
- VIVS_MMUv2_CONFIGURATION_FLUSH_MASK
 
- VIVS_MMUv2_CONFIGURATION_FLUSH__MASK
 
- VIVS_MMUv2_CONFIGURATION_FLUSH__SHIFT
 
- VIVS_MMUv2_CONFIGURATION_MODE_MASK
 
- VIVS_MMUv2_CONFIGURATION_MODE_MODE1_K
 
- VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K
 
- VIVS_MMUv2_CONFIGURATION_MODE__MASK
 
- VIVS_MMUv2_CONFIGURATION_MODE__SHIFT
 
- VIVS_MMUv2_CONTROL
 
- VIVS_MMUv2_CONTROL_ENABLE
 
- VIVS_MMUv2_EXCEPTION_ADDR
 
- VIVS_MMUv2_EXCEPTION_ADDR__ESIZE
 
- VIVS_MMUv2_EXCEPTION_ADDR__LEN
 
- VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW
 
- VIVS_MMUv2_PROFILE_BLT_READ
 
- VIVS_MMUv2_PTA_ADDRESS_HIGH
 
- VIVS_MMUv2_PTA_ADDRESS_LOW
 
- VIVS_MMUv2_PTA_CONFIG
 
- VIVS_MMUv2_PTA_CONFIG_INDEX
 
- VIVS_MMUv2_PTA_CONFIG_INDEX__MASK
 
- VIVS_MMUv2_PTA_CONFIG_INDEX__SHIFT
 
- VIVS_MMUv2_PTA_CONFIG_UNK16
 
- VIVS_MMUv2_PTA_CONTROL
 
- VIVS_MMUv2_PTA_CONTROL_ENABLE
 
- VIVS_MMUv2_SAFE_ADDRESS
 
- VIVS_MMUv2_SAFE_ADDRESS_CONFIG
 
- VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH
 
- VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__MASK
 
- VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__SHIFT
 
- VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH
 
- VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__MASK
 
- VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__SHIFT
 
- VIVS_MMUv2_SAFE_ADDRESS_CONFIG_UNK15
 
- VIVS_MMUv2_SAFE_ADDRESS_CONFIG_UNK31
 
- VIVS_MMUv2_SEC_COMMAND_CONTROL
 
- VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE
 
- VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH
 
- VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__MASK
 
- VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__SHIFT
 
- VIVS_MMUv2_SEC_CONTROL
 
- VIVS_MMUv2_SEC_CONTROL_ENABLE
 
- VIVS_MMUv2_SEC_EXCEPTION_ADDR
 
- VIVS_MMUv2_SEC_SAFE_ADDR_LOW
 
- VIVS_MMUv2_SEC_STATUS
 
- VIVS_MMUv2_SEC_STATUS_EXCEPTION0
 
- VIVS_MMUv2_SEC_STATUS_EXCEPTION0__MASK
 
- VIVS_MMUv2_SEC_STATUS_EXCEPTION0__SHIFT
 
- VIVS_MMUv2_SEC_STATUS_EXCEPTION1
 
- VIVS_MMUv2_SEC_STATUS_EXCEPTION1__MASK
 
- VIVS_MMUv2_SEC_STATUS_EXCEPTION1__SHIFT
 
- VIVS_MMUv2_SEC_STATUS_EXCEPTION2
 
- VIVS_MMUv2_SEC_STATUS_EXCEPTION2__MASK
 
- VIVS_MMUv2_SEC_STATUS_EXCEPTION2__SHIFT
 
- VIVS_MMUv2_SEC_STATUS_EXCEPTION3
 
- VIVS_MMUv2_SEC_STATUS_EXCEPTION3__MASK
 
- VIVS_MMUv2_SEC_STATUS_EXCEPTION3__SHIFT
 
- VIVS_MMUv2_STATUS
 
- VIVS_MMUv2_STATUS_EXCEPTION0
 
- VIVS_MMUv2_STATUS_EXCEPTION0__MASK
 
- VIVS_MMUv2_STATUS_EXCEPTION0__SHIFT
 
- VIVS_MMUv2_STATUS_EXCEPTION1
 
- VIVS_MMUv2_STATUS_EXCEPTION1__MASK
 
- VIVS_MMUv2_STATUS_EXCEPTION1__SHIFT
 
- VIVS_MMUv2_STATUS_EXCEPTION2
 
- VIVS_MMUv2_STATUS_EXCEPTION2__MASK
 
- VIVS_MMUv2_STATUS_EXCEPTION2__SHIFT
 
- VIVS_MMUv2_STATUS_EXCEPTION3
 
- VIVS_MMUv2_STATUS_EXCEPTION3__MASK
 
- VIVS_MMUv2_STATUS_EXCEPTION3__SHIFT
 
- VIVS_NFE
 
- VIVS_NFE_GENERIC_ATTRIB
 
- VIVS_NFE_GENERIC_ATTRIB_CONFIG0
 
- VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN
 
- VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK
 
- VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__SHIFT
 
- VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_OFF
 
- VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_ON
 
- VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__MASK
 
- VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__SHIFT
 
- VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM
 
- VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK
 
- VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__SHIFT
 
- VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START
 
- VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK
 
- VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__SHIFT
 
- VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM
 
- VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK
 
- VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__SHIFT
 
- VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE
 
- VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK
 
- VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT
 
- VIVS_NFE_GENERIC_ATTRIB_CONFIG1
 
- VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END
 
- VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK
 
- VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT
 
- VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE
 
- VIVS_NFE_GENERIC_ATTRIB_SCALE
 
- VIVS_NFE_GENERIC_ATTRIB_UNK17880
 
- VIVS_NFE_GENERIC_ATTRIB_UNK17900
 
- VIVS_NFE_GENERIC_ATTRIB_UNK17980
 
- VIVS_NFE_GENERIC_ATTRIB__ESIZE
 
- VIVS_NFE_GENERIC_ATTRIB__LEN
 
- VIVS_NFE_VERTEX_STREAMS
 
- VIVS_NFE_VERTEX_STREAMS_BASE_ADDR
 
- VIVS_NFE_VERTEX_STREAMS_CONTROL
 
- VIVS_NFE_VERTEX_STREAMS_ROBUSTNESS_UNK146C0
 
- VIVS_NFE_VERTEX_STREAMS_UNK14680
 
- VIVS_NFE_VERTEX_STREAMS__ESIZE
 
- VIVS_NFE_VERTEX_STREAMS__LEN
 
- VIVS_NTE_DESCRIPTOR_FLUSH
 
- VIVS_NTE_DESCRIPTOR_FLUSH_UNK28
 
- VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__MASK
 
- VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__SHIFT
 
- VIVS_PM
 
- VIVS_PM_MODULE_CONTROLS
 
- VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_DE
 
- VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_FE
 
- VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA
 
- VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE
 
- VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA
 
- VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ
 
- VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ
 
- VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE
 
- VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH
 
- VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX
 
- VIVS_PM_MODULE_STATUS
 
- VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_DE
 
- VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_FE
 
- VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_PA
 
- VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_PE
 
- VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_RA
 
- VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_SE
 
- VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_SH
 
- VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_TX
 
- VIVS_PM_POWER_CONTROLS
 
- VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING
 
- VIVS_PM_POWER_CONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING
 
- VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING
 
- VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER
 
- VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__MASK
 
- VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__SHIFT
 
- VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER
 
- VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__MASK
 
- VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__SHIFT
 
- VIVS_PM_PULSE_EATER
 
- VIVS_PM_PULSE_EATER_DISABLE
 
- VIVS_PM_PULSE_EATER_DVFS_PERIOD
 
- VIVS_PM_PULSE_EATER_DVFS_PERIOD__MASK
 
- VIVS_PM_PULSE_EATER_DVFS_PERIOD__SHIFT
 
- VIVS_PM_PULSE_EATER_INTERNAL_DFS
 
- VIVS_PM_PULSE_EATER_UNK16
 
- VIVS_PM_PULSE_EATER_UNK17
 
- VIVS_PM_PULSE_EATER_UNK19
 
- VIVS_PM_PULSE_EATER_UNK20
 
- VIVS_PM_PULSE_EATER_UNK22
 
- VIVS_PM_PULSE_EATER_UNK23
 
- VIVS_TS_FLUSH_CACHE
 
- VIVS_TS_FLUSH_CACHE_FLUSH
 
- VIV_FE_CALL
 
- VIV_FE_CALL_ADDRESS
 
- VIV_FE_CALL_HEADER
 
- VIV_FE_CALL_HEADER_OP_CALL
 
- VIV_FE_CALL_HEADER_OP__MASK
 
- VIV_FE_CALL_HEADER_OP__SHIFT
 
- VIV_FE_CALL_HEADER_PREFETCH
 
- VIV_FE_CALL_HEADER_PREFETCH__MASK
 
- VIV_FE_CALL_HEADER_PREFETCH__SHIFT
 
- VIV_FE_CALL_RETURN_ADDRESS
 
- VIV_FE_CALL_RETURN_PREFETCH
 
- VIV_FE_CHIP_SELECT
 
- VIV_FE_CHIP_SELECT_HEADER
 
- VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP0
 
- VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP1
 
- VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP10
 
- VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP11
 
- VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP12
 
- VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP13
 
- VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP14
 
- VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP15
 
- VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP2
 
- VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP3
 
- VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP4
 
- VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP5
 
- VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP6
 
- VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP7
 
- VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP8
 
- VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP9
 
- VIV_FE_CHIP_SELECT_HEADER_OP_CHIP_SELECT
 
- VIV_FE_CHIP_SELECT_HEADER_OP__MASK
 
- VIV_FE_CHIP_SELECT_HEADER_OP__SHIFT
 
- VIV_FE_DRAW_2D
 
- VIV_FE_DRAW_2D_BOTTOM_RIGHT
 
- VIV_FE_DRAW_2D_BOTTOM_RIGHT_X
 
- VIV_FE_DRAW_2D_BOTTOM_RIGHT_X__MASK
 
- VIV_FE_DRAW_2D_BOTTOM_RIGHT_X__SHIFT
 
- VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y
 
- VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y__MASK
 
- VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y__SHIFT
 
- VIV_FE_DRAW_2D_HEADER
 
- VIV_FE_DRAW_2D_HEADER_COUNT
 
- VIV_FE_DRAW_2D_HEADER_COUNT__MASK
 
- VIV_FE_DRAW_2D_HEADER_COUNT__SHIFT
 
- VIV_FE_DRAW_2D_HEADER_DATA_COUNT
 
- VIV_FE_DRAW_2D_HEADER_DATA_COUNT__MASK
 
- VIV_FE_DRAW_2D_HEADER_DATA_COUNT__SHIFT
 
- VIV_FE_DRAW_2D_HEADER_OP_DRAW_2D
 
- VIV_FE_DRAW_2D_HEADER_OP__MASK
 
- VIV_FE_DRAW_2D_HEADER_OP__SHIFT
 
- VIV_FE_DRAW_2D_TOP_LEFT
 
- VIV_FE_DRAW_2D_TOP_LEFT_X
 
- VIV_FE_DRAW_2D_TOP_LEFT_X__MASK
 
- VIV_FE_DRAW_2D_TOP_LEFT_X__SHIFT
 
- VIV_FE_DRAW_2D_TOP_LEFT_Y
 
- VIV_FE_DRAW_2D_TOP_LEFT_Y__MASK
 
- VIV_FE_DRAW_2D_TOP_LEFT_Y__SHIFT
 
- VIV_FE_DRAW_INDEXED_PRIMITIVES
 
- VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND
 
- VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND_TYPE
 
- VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND_TYPE__MASK
 
- VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND_TYPE__SHIFT
 
- VIV_FE_DRAW_INDEXED_PRIMITIVES_COUNT
 
- VIV_FE_DRAW_INDEXED_PRIMITIVES_HEADER
 
- VIV_FE_DRAW_INDEXED_PRIMITIVES_HEADER_OP_DRAW_INDEXED_PRIMITIVES
 
- VIV_FE_DRAW_INDEXED_PRIMITIVES_HEADER_OP__MASK
 
- VIV_FE_DRAW_INDEXED_PRIMITIVES_HEADER_OP__SHIFT
 
- VIV_FE_DRAW_INDEXED_PRIMITIVES_OFFSET
 
- VIV_FE_DRAW_INDEXED_PRIMITIVES_START
 
- VIV_FE_DRAW_INSTANCED
 
- VIV_FE_DRAW_INSTANCED_COUNT
 
- VIV_FE_DRAW_INSTANCED_COUNT_INSTANCE_COUNT_HI
 
- VIV_FE_DRAW_INSTANCED_COUNT_INSTANCE_COUNT_HI__MASK
 
- VIV_FE_DRAW_INSTANCED_COUNT_INSTANCE_COUNT_HI__SHIFT
 
- VIV_FE_DRAW_INSTANCED_COUNT_VERTEX_COUNT
 
- VIV_FE_DRAW_INSTANCED_COUNT_VERTEX_COUNT__MASK
 
- VIV_FE_DRAW_INSTANCED_COUNT_VERTEX_COUNT__SHIFT
 
- VIV_FE_DRAW_INSTANCED_HEADER
 
- VIV_FE_DRAW_INSTANCED_HEADER_INDEXED
 
- VIV_FE_DRAW_INSTANCED_HEADER_INSTANCE_COUNT_LO
 
- VIV_FE_DRAW_INSTANCED_HEADER_INSTANCE_COUNT_LO__MASK
 
- VIV_FE_DRAW_INSTANCED_HEADER_INSTANCE_COUNT_LO__SHIFT
 
- VIV_FE_DRAW_INSTANCED_HEADER_OP_DRAW_INSTANCED
 
- VIV_FE_DRAW_INSTANCED_HEADER_OP__MASK
 
- VIV_FE_DRAW_INSTANCED_HEADER_OP__SHIFT
 
- VIV_FE_DRAW_INSTANCED_HEADER_TYPE
 
- VIV_FE_DRAW_INSTANCED_HEADER_TYPE__MASK
 
- VIV_FE_DRAW_INSTANCED_HEADER_TYPE__SHIFT
 
- VIV_FE_DRAW_INSTANCED_START
 
- VIV_FE_DRAW_INSTANCED_START_INDEX
 
- VIV_FE_DRAW_INSTANCED_START_INDEX__MASK
 
- VIV_FE_DRAW_INSTANCED_START_INDEX__SHIFT
 
- VIV_FE_DRAW_PRIMITIVES
 
- VIV_FE_DRAW_PRIMITIVES_COMMAND
 
- VIV_FE_DRAW_PRIMITIVES_COMMAND_TYPE
 
- VIV_FE_DRAW_PRIMITIVES_COMMAND_TYPE__MASK
 
- VIV_FE_DRAW_PRIMITIVES_COMMAND_TYPE__SHIFT
 
- VIV_FE_DRAW_PRIMITIVES_COUNT
 
- VIV_FE_DRAW_PRIMITIVES_HEADER
 
- VIV_FE_DRAW_PRIMITIVES_HEADER_OP_DRAW_PRIMITIVES
 
- VIV_FE_DRAW_PRIMITIVES_HEADER_OP__MASK
 
- VIV_FE_DRAW_PRIMITIVES_HEADER_OP__SHIFT
 
- VIV_FE_DRAW_PRIMITIVES_START
 
- VIV_FE_END
 
- VIV_FE_END_HEADER
 
- VIV_FE_END_HEADER_EVENT_ENABLE
 
- VIV_FE_END_HEADER_EVENT_ID
 
- VIV_FE_END_HEADER_EVENT_ID__MASK
 
- VIV_FE_END_HEADER_EVENT_ID__SHIFT
 
- VIV_FE_END_HEADER_OP_END
 
- VIV_FE_END_HEADER_OP__MASK
 
- VIV_FE_END_HEADER_OP__SHIFT
 
- VIV_FE_LINK
 
- VIV_FE_LINK_ADDRESS
 
- VIV_FE_LINK_HEADER
 
- VIV_FE_LINK_HEADER_OP_LINK
 
- VIV_FE_LINK_HEADER_OP__MASK
 
- VIV_FE_LINK_HEADER_OP__SHIFT
 
- VIV_FE_LINK_HEADER_PREFETCH
 
- VIV_FE_LINK_HEADER_PREFETCH__MASK
 
- VIV_FE_LINK_HEADER_PREFETCH__SHIFT
 
- VIV_FE_LOAD_STATE
 
- VIV_FE_LOAD_STATE_HEADER
 
- VIV_FE_LOAD_STATE_HEADER_COUNT
 
- VIV_FE_LOAD_STATE_HEADER_COUNT__MASK
 
- VIV_FE_LOAD_STATE_HEADER_COUNT__SHIFT
 
- VIV_FE_LOAD_STATE_HEADER_FIXP
 
- VIV_FE_LOAD_STATE_HEADER_OFFSET
 
- VIV_FE_LOAD_STATE_HEADER_OFFSET__MASK
 
- VIV_FE_LOAD_STATE_HEADER_OFFSET__SHIFT
 
- VIV_FE_LOAD_STATE_HEADER_OFFSET__SHR
 
- VIV_FE_LOAD_STATE_HEADER_OP_LOAD_STATE
 
- VIV_FE_LOAD_STATE_HEADER_OP__MASK
 
- VIV_FE_LOAD_STATE_HEADER_OP__SHIFT
 
- VIV_FE_NOP
 
- VIV_FE_NOP_HEADER
 
- VIV_FE_NOP_HEADER_OP_NOP
 
- VIV_FE_NOP_HEADER_OP__MASK
 
- VIV_FE_NOP_HEADER_OP__SHIFT
 
- VIV_FE_RETURN
 
- VIV_FE_RETURN_HEADER
 
- VIV_FE_RETURN_HEADER_OP_RETURN
 
- VIV_FE_RETURN_HEADER_OP__MASK
 
- VIV_FE_RETURN_HEADER_OP__SHIFT
 
- VIV_FE_STALL
 
- VIV_FE_STALL_HEADER
 
- VIV_FE_STALL_HEADER_OP_STALL
 
- VIV_FE_STALL_HEADER_OP__MASK
 
- VIV_FE_STALL_HEADER_OP__SHIFT
 
- VIV_FE_STALL_TOKEN
 
- VIV_FE_STALL_TOKEN_FROM
 
- VIV_FE_STALL_TOKEN_FROM__MASK
 
- VIV_FE_STALL_TOKEN_FROM__SHIFT
 
- VIV_FE_STALL_TOKEN_TO
 
- VIV_FE_STALL_TOKEN_TO__MASK
 
- VIV_FE_STALL_TOKEN_TO__SHIFT
 
- VIV_FE_WAIT
 
- VIV_FE_WAIT_HEADER
 
- VIV_FE_WAIT_HEADER_DELAY
 
- VIV_FE_WAIT_HEADER_DELAY__MASK
 
- VIV_FE_WAIT_HEADER_DELAY__SHIFT
 
- VIV_FE_WAIT_HEADER_OP_WAIT
 
- VIV_FE_WAIT_HEADER_OP__MASK
 
- VIV_FE_WAIT_HEADER_OP__SHIFT
 
- VIZQUERY_END
 
- VIZQUERY_START
 
- VI_ADMTIME
 
- VI_ADMTM
 
- VI_BO_SIZE_ALIGN
 
- VI_FIJI_P_A0
 
- VI_FLUSH_GPU_TLB_NUM_WREG
 
- VI_H
 
- VI_MAILBOX_RESET_TIME
 
- VI_MAILBOX_TIMEDOUT
 
- VI_MASK_LENGTH
 
- VI_MODE
 
- VI_MUTE
 
- VI_PF_NUM_STATS
 
- VI_POLARIS10_P_A0
 
- VI_POLARIS11_M_A0
 
- VI_POLARIS12_V_A0
 
- VI_PRIORITY
 
- VI_PROG_HSIZE
 
- VI_PROG_VSIZE
 
- VI_Q
 
- VI_QID_01
 
- VI_QID_02
 
- VI_QUEUE
 
- VI_QUEUE_INX
 
- VI_REP
 
- VI_STATUS1
 
- VI_STATUS3
 
- VI_STRUCTS_H_
 
- VI_TONGA_P_A0
 
- VI_TONGA_P_A1
 
- VI_TYPE_LEFT_MERGEABLE
 
- VI_TYPE_RIGHT_MERGEABLE
 
- VI_UNKNOWN
 
- VI_VEGAM_A0
 
- VI_VF_NUM_STATS
 
- VK
 
- VKILL
 
- VL15BUF_MASK
 
- VL15BUF_SHIFT
 
- VL6180_ALS
 
- VL6180_ALS_GAIN
 
- VL6180_ALS_GAIN_1
 
- VL6180_ALS_GAIN_10
 
- VL6180_ALS_GAIN_1_25
 
- VL6180_ALS_GAIN_1_67
 
- VL6180_ALS_GAIN_20
 
- VL6180_ALS_GAIN_2_5
 
- VL6180_ALS_GAIN_40
 
- VL6180_ALS_GAIN_5
 
- VL6180_ALS_IT
 
- VL6180_ALS_IT_100
 
- VL6180_ALS_READY
 
- VL6180_ALS_START
 
- VL6180_ALS_STATUS
 
- VL6180_ALS_VALUE
 
- VL6180_CLEAR_ALS
 
- VL6180_CLEAR_ERROR
 
- VL6180_CLEAR_RANGE
 
- VL6180_DRV_NAME
 
- VL6180_HOLD
 
- VL6180_HOLD_ON
 
- VL6180_INTR_CLEAR
 
- VL6180_INTR_CONFIG
 
- VL6180_INTR_STATUS
 
- VL6180_MODEL_ID
 
- VL6180_MODEL_ID_VAL
 
- VL6180_MODE_CONT
 
- VL6180_OUT_OF_RESET
 
- VL6180_PROX
 
- VL6180_RANGE
 
- VL6180_RANGE_RATE
 
- VL6180_RANGE_READY
 
- VL6180_RANGE_START
 
- VL6180_RANGE_STATUS
 
- VL6180_RANGE_VALUE
 
- VL6180_STARTSTOP
 
- VLAN
 
- VLAN1
 
- VLAN1_VTI1_
 
- VLAN2
 
- VLAN2_VTI2_
 
- VLANDetected
 
- VLANId
 
- VLANTag
 
- VLANTagInsert
 
- VLAN_ACTION
 
- VLAN_ADDR_FORCED
 
- VLAN_ALLOWED
 
- VLAN_ATTR
 
- VLAN_ATTR_MASK
 
- VLAN_BITMAP_SIZE
 
- VLAN_BYP
 
- VLAN_CFI_MASK
 
- VLAN_CLEAR
 
- VLAN_CTRL
 
- VLAN_CTRL_RSP
 
- VLAN_EN
 
- VLAN_ETHER_TYPE
 
- VLAN_ETH_DATA_LEN
 
- VLAN_ETH_FRAME_LEN
 
- VLAN_ETH_HLEN
 
- VLAN_ETH_ZLEN
 
- VLAN_F
 
- VLAN_FEAT
 
- VLAN_FID_M
 
- VLAN_FLAG_BRIDGE_BINDING
 
- VLAN_FLAG_GVRP
 
- VLAN_FLAG_LOOSE_BINDING
 
- VLAN_FLAG_MVRP
 
- VLAN_FLAG_REORDER_HDR
 
- VLAN_FLTR_SIZE
 
- VLAN_FORWARD_OPTION
 
- VLAN_GROUP_ARRAY_PART_LEN
 
- VLAN_GROUP_ARRAY_SPLIT_PARTS
 
- VLAN_HDR_SZ
 
- VLAN_HEADER_INSERTION
 
- VLAN_HLEN
 
- VLAN_ID_LEN
 
- VLAN_INDEX_M
 
- VLAN_INSERT
 
- VLAN_LEN
 
- VLAN_LTYPE1_EN
 
- VLAN_LTYPE2_EN
 
- VLAN_MASK
 
- VLAN_MSTP_M
 
- VLAN_MSTP_S
 
- VLAN_NAME_TYPE_HIGHEST
 
- VLAN_NAME_TYPE_PLUS_VID
 
- VLAN_NAME_TYPE_PLUS_VID_NO_PAD
 
- VLAN_NAME_TYPE_RAW_PLUS_VID
 
- VLAN_NAME_TYPE_RAW_PLUS_VID_NO_PAD
 
- VLAN_NOCHANGE
 
- VLAN_NONE
 
- VLAN_NUMBER
 
- VLAN_N_VID
 
- VLAN_PRIORITY_MASK
 
- VLAN_PRIO_FULL_MASK
 
- VLAN_PRIO_M
 
- VLAN_PRIO_MASK
 
- VLAN_PRIO_S
 
- VLAN_PRIO_SHIFT
 
- VLAN_PRI_HASH_TYPE
 
- VLAN_PROTO_8021AD
 
- VLAN_PROTO_8021Q
 
- VLAN_PROTO_NUM
 
- VLAN_READ
 
- VLAN_REMOVE
 
- VLAN_REWRITE
 
- VLAN_S
 
- VLAN_START
 
- VLAN_STRIP
 
- VLAN_SUPPORT
 
- VLAN_TABLE_ENTRIES
 
- VLAN_TABLE_FID
 
- VLAN_TABLE_FID_SHIFT
 
- VLAN_TABLE_MEMBERSHIP
 
- VLAN_TABLE_MEMBERSHIP_S
 
- VLAN_TABLE_MEMBERSHIP_SHIFT
 
- VLAN_TABLE_S
 
- VLAN_TABLE_VALID
 
- VLAN_TABLE_VID
 
- VLAN_TAG_PRESENT
 
- VLAN_TAG_SIZE
 
- VLAN_TAG_TX_DEL
 
- VLAN_TAG_TX_INSERT
 
- VLAN_TAG_TX_NOP
 
- VLAN_TAG_TX_REPLACE
 
- VLAN_TCI
 
- VLAN_TYPE
 
- VLAN_TYPE_MASK
 
- VLAN_TYPE_MASK_
 
- VLAN_V
 
- VLAN_VALID
 
- VLAN_VID_MASK
 
- VLAN_WRITE
 
- VLC_LOOKUP_TABLE_LEN
 
- VLC_SA_RECEIVE_CREDENTIAL
 
- VLDBG
 
- VLD_CNT_ADDR_A
 
- VLD_CNT_ADDR_B
 
- VLD_MEM_VIFIFO_BUF_CNTL
 
- VLD_MEM_VIFIFO_CONTROL
 
- VLD_MEM_VIFIFO_CURR_PTR
 
- VLD_MEM_VIFIFO_END_PTR
 
- VLD_MEM_VIFIFO_LEVEL
 
- VLD_MEM_VIFIFO_RP
 
- VLD_MEM_VIFIFO_START_PTR
 
- VLD_MEM_VIFIFO_WP
 
- VLD_MEM_VIFIFO_WRAP_COUNT
 
- VLENSIMM
 
- VLESIMM
 
- VLEUIMM
 
- VLEUIMML
 
- VLE_OP
 
- VLE_OP_TO_SEG
 
- VLGETADDRSU
 
- VLGETCAPABILITIES
 
- VLGETENTRYBYID
 
- VLGETENTRYBYIDU
 
- VLGETENTRYBYNAME
 
- VLGETENTRYBYNAMEU
 
- VLINE0
 
- VLINE1
 
- VLINE2_INTERRUPT_MASK
 
- VLINE_ACK
 
- VLINE_INTERRUPT
 
- VLINE_INTERRUPT_MASK
 
- VLINE_INTERRUPT_TYPE
 
- VLINE_INT_MASK
 
- VLINE_OCCURRED
 
- VLINE_STAT
 
- VLINE_STATUS
 
- VLI_BYTES_MAX
 
- VLI_L_1_1
 
- VLI_MAX
 
- VLI_UNKNOWN
 
- VLM
 
- VLM_OVRFLW
 
- VLNEXT
 
- VLOCK_OWNER_NONE
 
- VLOCK_OWNER_OFFSET
 
- VLOCK_SIZE
 
- VLOCK_VOTING_OFFSET
 
- VLOCK_VOTING_SIZE
 
- VLONLY
 
- VLPROBE
 
- VLPT_IDX_mskEVPN
 
- VLPT_IDX_mskVLPTB
 
- VLPT_IDX_mskZERO
 
- VLPT_IDX_offEVPN
 
- VLPT_IDX_offVLPTB
 
- VLPT_IDX_offZERO
 
- VLV_ADPA
 
- VLV_AMP_MUTE
 
- VLV_AUD_CFG
 
- VLV_AUD_CHICKEN_BIT_REG
 
- VLV_AUD_CNTL_ST
 
- VLV_AUD_CNTL_ST2
 
- VLV_AUD_PORT_EN_DBG
 
- VLV_B0_WA_L3SQCREG1_VALUE
 
- VLV_BIAS_CPU_125_SOC_875
 
- VLV_BLC_HIST_CTL
 
- VLV_BLC_PWM_CTL
 
- VLV_BLC_PWM_CTL2
 
- VLV_CHICKEN_3
 
- VLV_CHICKEN_BIT_DBG_ENABLE
 
- VLV_CLK_CTL2
 
- VLV_CMN_DW0
 
- VLV_COUNTER_CONTROL
 
- VLV_COUNT_RANGE_HIGH
 
- VLV_DDL
 
- VLV_DISPLAY_BASE
 
- VLV_DISPLAY_POS
 
- VLV_DISPLAY_POWER_DOMAINS
 
- VLV_DISP_PW_DISP2D
 
- VLV_DISP_PW_DPIO_CMN_BC
 
- VLV_DPFLIPSTAT
 
- VLV_DPIO_CMN_BC_POWER_DOMAINS
 
- VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
 
- VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
 
- VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
 
- VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
 
- VLV_DP_B
 
- VLV_DP_C
 
- VLV_FIFO
 
- VLV_FIFO_START
 
- VLV_G3DCTL
 
- VLV_GFX_CLK_FORCE_ON_BIT
 
- VLV_GFX_CLK_STATUS_BIT
 
- VLV_GPIO_NC_0_HV_DDI0_HPD
 
- VLV_GPIO_NC_10_PANEL1_BKLTEN
 
- VLV_GPIO_NC_11_PANEL1_BKLTCTL
 
- VLV_GPIO_NC_1_HV_DDI0_DDC_SDA
 
- VLV_GPIO_NC_2_HV_DDI0_DDC_SCL
 
- VLV_GPIO_NC_3_PANEL0_VDDEN
 
- VLV_GPIO_NC_4_PANEL0_BKLTEN
 
- VLV_GPIO_NC_5_PANEL0_BKLTCTL
 
- VLV_GPIO_NC_6_HV_DDI1_HPD
 
- VLV_GPIO_NC_7_HV_DDI1_DDC_SDA
 
- VLV_GPIO_NC_8_HV_DDI1_DDC_SCL
 
- VLV_GPIO_NC_9_PANEL1_VDDEN
 
- VLV_GPIO_PAD_VAL
 
- VLV_GPIO_PCONF0
 
- VLV_GSCKGCTL
 
- VLV_GTLC_ALLOWWAKEACK
 
- VLV_GTLC_ALLOWWAKEERR
 
- VLV_GTLC_ALLOWWAKEREQ
 
- VLV_GTLC_MEDIA_CTX_EXISTS
 
- VLV_GTLC_PW_MEDIA_STATUS_MASK
 
- VLV_GTLC_PW_RENDER_STATUS_MASK
 
- VLV_GTLC_PW_STATUS
 
- VLV_GTLC_RENDER_CTX_EXISTS
 
- VLV_GTLC_SURVIVABILITY_REG
 
- VLV_GTLC_WAKE_CTRL
 
- VLV_GT_MEDIA_RC6
 
- VLV_GT_RENDER_RC6
 
- VLV_GUNIT_CLOCK_GATE
 
- VLV_GUNIT_CLOCK_GATE2
 
- VLV_GU_CTL0
 
- VLV_GU_CTL1
 
- VLV_HDMIB
 
- VLV_HDMIC
 
- VLV_HDMIW_HDMIEDID
 
- VLV_IER
 
- VLV_IIR
 
- VLV_IIR_RW
 
- VLV_IMR
 
- VLV_IOSF_ADDR
 
- VLV_IOSF_DATA
 
- VLV_IOSF_DOORBELL_REQ
 
- VLV_IOSF_SB_BUNIT
 
- VLV_IOSF_SB_CCK
 
- VLV_IOSF_SB_CCU
 
- VLV_IOSF_SB_DPIO
 
- VLV_IOSF_SB_FLISDSI
 
- VLV_IOSF_SB_GPIO
 
- VLV_IOSF_SB_NC
 
- VLV_IOSF_SB_PUNIT
 
- VLV_ISR
 
- VLV_MASTER_IER
 
- VLV_MEDIA_C0_COUNT
 
- VLV_MEDIA_RC0_COUNT_EN
 
- VLV_MEDIA_RC6_COUNT_EN
 
- VLV_MIPI_BASE
 
- VLV_OVERRIDE_EN
 
- VLV_PCBR
 
- VLV_PCBR_ADDR_SHIFT
 
- VLV_PCS01_DW0
 
- VLV_PCS01_DW1
 
- VLV_PCS01_DW10
 
- VLV_PCS01_DW11
 
- VLV_PCS01_DW12
 
- VLV_PCS01_DW8
 
- VLV_PCS01_DW9
 
- VLV_PCS23_DW0
 
- VLV_PCS23_DW1
 
- VLV_PCS23_DW10
 
- VLV_PCS23_DW11
 
- VLV_PCS23_DW12
 
- VLV_PCS23_DW8
 
- VLV_PCS23_DW9
 
- VLV_PCS_DW0
 
- VLV_PCS_DW1
 
- VLV_PCS_DW11
 
- VLV_PCS_DW12
 
- VLV_PCS_DW14
 
- VLV_PCS_DW23
 
- VLV_PCS_DW8
 
- VLV_PCS_DW9
 
- VLV_PLL_DW10
 
- VLV_PLL_DW11
 
- VLV_PLL_DW3
 
- VLV_PLL_DW5
 
- VLV_PLL_DW7
 
- VLV_PLL_DW8
 
- VLV_PLL_DW9
 
- VLV_PLL_DW9_BCAST
 
- VLV_PMWGICZ
 
- VLV_PPS_BASE
 
- VLV_PWRDWNUPCTL
 
- VLV_RCEDATA
 
- VLV_RC_CTL_CTX_RST_PARALLEL
 
- VLV_REF_DW13
 
- VLV_RENDER_C0_COUNT
 
- VLV_RENDER_RC0_COUNT_EN
 
- VLV_RENDER_RC6_COUNT_EN
 
- VLV_SOC_TDP_EN
 
- VLV_SPAREG2H
 
- VLV_TURBO_SOC_OVERRIDE
 
- VLV_TVIDEO_DIP_CTL
 
- VLV_TVIDEO_DIP_DATA
 
- VLV_TVIDEO_DIP_GCP
 
- VLV_TX3_DW4
 
- VLV_TX_DW11
 
- VLV_TX_DW14
 
- VLV_TX_DW2
 
- VLV_TX_DW3
 
- VLV_TX_DW4
 
- VLV_TX_DW5
 
- VLV_VGACNTRL
 
- VLV_WM_LEVEL_DDR_DVFS
 
- VLV_WM_LEVEL_PM2
 
- VLV_WM_LEVEL_PM5
 
- VLYNQ_AUTONEGO_V2
 
- VLYNQ_CTRL_CLOCK_DIV
 
- VLYNQ_CTRL_CLOCK_INT
 
- VLYNQ_CTRL_CLOCK_MASK
 
- VLYNQ_CTRL_INT2CFG
 
- VLYNQ_CTRL_INT_ENABLE
 
- VLYNQ_CTRL_INT_LOCAL
 
- VLYNQ_CTRL_INT_VECTOR
 
- VLYNQ_CTRL_PM_ENABLE
 
- VLYNQ_CTRL_RESET
 
- VLYNQ_INT_OFFSET
 
- VLYNQ_NUM_IRQS
 
- VLYNQ_REMOTE_OFFSET
 
- VLYNQ_STATUS_LERROR
 
- VLYNQ_STATUS_LINK
 
- VLYNQ_STATUS_RERROR
 
- VL_ARB_HIGH_PRIO_TABLE_SIZE
 
- VL_ARB_LOW_PRIO_TABLE_SIZE
 
- VL_ARB_TABLE_SIZE
 
- VL_CAP_MAX
 
- VL_CAP_VL0
 
- VL_CAP_VL0_1
 
- VL_CAP_VL0_10
 
- VL_CAP_VL0_11
 
- VL_CAP_VL0_12
 
- VL_CAP_VL0_13
 
- VL_CAP_VL0_14
 
- VL_CAP_VL0_2
 
- VL_CAP_VL0_3
 
- VL_CAP_VL0_4
 
- VL_CAP_VL0_5
 
- VL_CAP_VL0_6
 
- VL_CAP_VL0_7
 
- VL_CAP_VL0_8
 
- VL_CAP_VL0_9
 
- VL_CTRL0
 
- VL_CTRL1
 
- VL_CTRL2
 
- VL_FMT_YUV420
 
- VL_FMT_YUV420_HANTRO
 
- VL_FMT_YUV420_P010
 
- VL_FMT_YUV422
 
- VL_FMT_YUV444_10BIT
 
- VL_FMT_YUV444_8BIT
 
- VL_MASK_ALL
 
- VL_NUM
 
- VL_POS_END
 
- VL_POS_START
 
- VL_REG_RESULT_INT_STATUS
 
- VL_REG_RESULT_RANGE_STATUS
 
- VL_REG_RESULT_RANGE_STATUS_COMPLETE
 
- VL_REG_SYSRANGE_MODE_BACKTOBACK
 
- VL_REG_SYSRANGE_MODE_HISTOGRAM
 
- VL_REG_SYSRANGE_MODE_MASK
 
- VL_REG_SYSRANGE_MODE_SINGLESHOT
 
- VL_REG_SYSRANGE_MODE_START_STOP
 
- VL_REG_SYSRANGE_MODE_TIMED
 
- VL_REG_SYSRANGE_START
 
- VL_SCALER_BYPASS_MODE
 
- VL_SERVICE
 
- VL_SRC_SIZE
 
- VL_STATUS_CLEAR_TIMEOUT
 
- VL_STRIDE
 
- VL_TAG_DEL
 
- VL_UPDATE
 
- VL_Y
 
- VL_YUV420_PLANAR
 
- VL_YUV422_SHIFT
 
- VL_YUV422_UYVY
 
- VL_YUV422_VYUY
 
- VL_YUV422_YUYV
 
- VL_YUV422_YVYU
 
- VM
 
- VM86
 
- VM86_ARG
 
- VM86_ENTER
 
- VM86_ENTER_NO_BYPASS
 
- VM86_FREE_IRQ
 
- VM86_GET_AND_RESET_IRQ
 
- VM86_GET_IRQ_BITS
 
- VM86_INTx
 
- VM86_IRQNAME
 
- VM86_PICRETURN
 
- VM86_PLUS_INSTALL_CHECK
 
- VM86_REG_
 
- VM86_REQUEST_IRQ
 
- VM86_SCREEN_BITMAP
 
- VM86_SIGNAL
 
- VM86_STI
 
- VM86_TRAP
 
- VM86_TYPE
 
- VM86_UNKNOWN
 
- VMACACHE_BITS
 
- VMACACHE_FIND_CALLS
 
- VMACACHE_FIND_HITS
 
- VMACACHE_HASH
 
- VMACACHE_MASK
 
- VMACACHE_SHIFT
 
- VMACACHE_SIZE
 
- VMAC_KEY_LEN
 
- VMAC_KEY_SIZE
 
- VMAC_NHBYTES
 
- VMAC_NONCEBYTES
 
- VMAC_TAG_LEN
 
- VMADDR_CID_ANY
 
- VMADDR_CID_HOST
 
- VMADDR_CID_HYPERVISOR
 
- VMADDR_CID_RESERVED
 
- VMADDR_PORT_ANY
 
- VMALLOC_DEFAULT_SIZE
 
- VMALLOC_END
 
- VMALLOC_END_INIT
 
- VMALLOC_END_NR
 
- VMALLOC_FAULT_TARGET
 
- VMALLOC_MODULE_START
 
- VMALLOC_NR
 
- VMALLOC_OFFSET
 
- VMALLOC_PAGES
 
- VMALLOC_REGION_ID
 
- VMALLOC_RESERVE
 
- VMALLOC_SIZE
 
- VMALLOC_SIZE_TB
 
- VMALLOC_SIZE_TB_L4
 
- VMALLOC_SIZE_TB_L5
 
- VMALLOC_SPACE
 
- VMALLOC_START
 
- VMALLOC_START_NR
 
- VMALLOC_TOTAL
 
- VMALLOC_VMADDR
 
- VMAP_BBMAP_BITS
 
- VMAP_BBMAP_BITS_MAX
 
- VMAP_BBMAP_BITS_MIN
 
- VMAP_BLOCK_SIZE
 
- VMAP_MAX
 
- VMAP_MAX_ALLOC
 
- VMAP_MIN
 
- VMASST_CMD_disable
 
- VMASST_CMD_enable
 
- VMASST_TYPE_4gb_segments
 
- VMASST_TYPE_4gb_segments_notify
 
- VMASST_TYPE_architectural_iopl
 
- VMASST_TYPE_pae_extended_cr3
 
- VMASST_TYPE_runstate_update_flag
 
- VMASST_TYPE_writable_pagetables
 
- VMAX
 
- VMA_ADD_RESV
 
- VMA_COMMIT_RESV
 
- VMA_END_RESV
 
- VMA_NEEDS_RESV
 
- VMBALLOON_SHRINK_DELAY
 
- VMBUS_ALIAS_LEN
 
- VMBUS_CHANNEL_ENUMERATE_DEVICE_INTERFACE
 
- VMBUS_CHANNEL_LOOPBACK_OFFER
 
- VMBUS_CHANNEL_NAMED_PIPE_MODE
 
- VMBUS_CHANNEL_PARENT_OFFER
 
- VMBUS_CHANNEL_REQUEST_MONITORED_NOTIFICATION
 
- VMBUS_CHANNEL_SERVER_SUPPORTS_GPADLS
 
- VMBUS_CHANNEL_SERVER_SUPPORTS_TRANSFER_PAGES
 
- VMBUS_CHANNEL_TLNPI_PROVIDER_OFFER
 
- VMBUS_CHAN_ATTR
 
- VMBUS_CHAN_ATTR_RO
 
- VMBUS_CHAN_ATTR_RW
 
- VMBUS_CHAN_ATTR_WO
 
- VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED
 
- VMBUS_EVENT_CONNECTION_ID
 
- VMBUS_EVENT_PORT_ID
 
- VMBUS_MESSAGE_CONNECTION_ID
 
- VMBUS_MESSAGE_CONNECTION_ID_4
 
- VMBUS_MESSAGE_PORT_ID
 
- VMBUS_MESSAGE_SINT
 
- VMBUS_MONITOR_CONNECTION_ID
 
- VMBUS_MONITOR_PORT_ID
 
- VMBUS_PIPE_TYPE_BYTE
 
- VMBUS_PIPE_TYPE_MESSAGE
 
- VMBUS_PKT_TRAILER
 
- VMBUS_PKT_TRAILER_SIZE
 
- VMCALL_CONTROLVM_ADDR
 
- VMCALL_RESULT_DATA_UNAVAILABLE
 
- VMCALL_RESULT_DEVICE_ERROR
 
- VMCALL_RESULT_DEVICE_NOT_READY
 
- VMCALL_RESULT_FAILURE_UNAVAILABLE
 
- VMCALL_RESULT_INVALID_PARAM
 
- VMCALL_RESULT_SUCCESS
 
- VMCB_ALWAYS_DIRTY_MASK
 
- VMCB_ASID
 
- VMCB_AVIC
 
- VMCB_AVIC_APIC_BAR_MASK
 
- VMCB_CR
 
- VMCB_CR2
 
- VMCB_DIRTY_MAX
 
- VMCB_DR
 
- VMCB_DT
 
- VMCB_INTERCEPTS
 
- VMCB_INTR
 
- VMCB_LBR
 
- VMCB_NPT
 
- VMCB_PERM_MAP
 
- VMCB_SEG
 
- VMCIOBJ_CONTEXT
 
- VMCIOBJ_NOT_SET
 
- VMCIOBJ_SOCKET
 
- VMCIOBJ_VMX_VM
 
- VMCIQPB_ATTACHED_MEM
 
- VMCIQPB_ATTACHED_NO_MEM
 
- VMCIQPB_CREATED_MEM
 
- VMCIQPB_CREATED_NO_MEM
 
- VMCIQPB_GONE
 
- VMCIQPB_NEW
 
- VMCIQPB_SHUTDOWN_MEM
 
- VMCIQPB_SHUTDOWN_NO_MEM
 
- VMCI_ANON_SRC_CONTEXT_ID
 
- VMCI_ANON_SRC_RESOURCE_ID
 
- VMCI_CAPS_ADDR
 
- VMCI_CAPS_DATAGRAM
 
- VMCI_CAPS_GUESTCALL
 
- VMCI_CAPS_HYPERCALL
 
- VMCI_CAPS_NOTIFICATIONS
 
- VMCI_CAPS_PPN64
 
- VMCI_CONTEXT_IS_VM
 
- VMCI_CONTEXT_RESOURCE_ID
 
- VMCI_CONTROL_ADDR
 
- VMCI_CONTROL_INT_DISABLE
 
- VMCI_CONTROL_INT_ENABLE
 
- VMCI_CONTROL_RESET
 
- VMCI_DATAGRAM_REMOVE_MAP
 
- VMCI_DATAGRAM_REQUEST_MAP
 
- VMCI_DATA_IN_ADDR
 
- VMCI_DATA_OUT_ADDR
 
- VMCI_DEFAULT_PROC_PRIVILEGE_FLAGS
 
- VMCI_DG_HEADERSIZE
 
- VMCI_DG_IN_SIZE_STATE
 
- VMCI_DG_IN_STATE
 
- VMCI_DG_OUT_STATE
 
- VMCI_DG_PAYLOAD
 
- VMCI_DG_SIZE
 
- VMCI_DG_SIZE_ALIGNED
 
- VMCI_DOORBELL_CPT_STATE
 
- VMCI_DOORBELL_H
 
- VMCI_DOORBELL_HASH
 
- VMCI_DOORBELL_INDEX_BITS
 
- VMCI_DOORBELL_INDEX_TABLE_SIZE
 
- VMCI_DOORBELL_LINK
 
- VMCI_DOORBELL_NOTIFY
 
- VMCI_DOORBELL_UNLINK
 
- VMCI_DO_IOCTL
 
- VMCI_ERROR_ALREADY_EXISTS
 
- VMCI_ERROR_BUSMEM_INVALIDATION
 
- VMCI_ERROR_CANNOT_SHARE_PAGE
 
- VMCI_ERROR_CANNOT_UNSHARE_PAGE
 
- VMCI_ERROR_CLIENT_MAX
 
- VMCI_ERROR_CLIENT_MIN
 
- VMCI_ERROR_DATAGRAM_FAILED
 
- VMCI_ERROR_DATAGRAM_INCOMPLETE
 
- VMCI_ERROR_DEVICE_NOT_FOUND
 
- VMCI_ERROR_DST_UNREACHABLE
 
- VMCI_ERROR_DUPLICATE_ENTRY
 
- VMCI_ERROR_EVENT_UNKNOWN
 
- VMCI_ERROR_GENERIC
 
- VMCI_ERROR_INCORRECT_IRQL
 
- VMCI_ERROR_INVALID_ARGS
 
- VMCI_ERROR_INVALID_PRIV
 
- VMCI_ERROR_INVALID_RESOURCE
 
- VMCI_ERROR_INVALID_SIZE
 
- VMCI_ERROR_MODULE_NOT_LOADED
 
- VMCI_ERROR_MORE_DATA
 
- VMCI_ERROR_NOT_FOUND
 
- VMCI_ERROR_NOT_PAGE_ALIGNED
 
- VMCI_ERROR_NO_ACCESS
 
- VMCI_ERROR_NO_DATAGRAM
 
- VMCI_ERROR_NO_HANDLE
 
- VMCI_ERROR_NO_MEM
 
- VMCI_ERROR_NO_MORE_DATAGRAMS
 
- VMCI_ERROR_NO_PROCESS
 
- VMCI_ERROR_NO_RESOURCES
 
- VMCI_ERROR_OBSOLETE
 
- VMCI_ERROR_PAGE_ALREADY_SHARED
 
- VMCI_ERROR_PAYLOAD_TOO_LARGE
 
- VMCI_ERROR_QUEUEPAIR_MISMATCH
 
- VMCI_ERROR_QUEUEPAIR_NODATA
 
- VMCI_ERROR_QUEUEPAIR_NOSPACE
 
- VMCI_ERROR_QUEUEPAIR_NOTATTACHED
 
- VMCI_ERROR_QUEUEPAIR_NOTOWNER
 
- VMCI_ERROR_QUEUEPAIR_NOTSET
 
- VMCI_ERROR_QUEUEPAIR_NOT_READY
 
- VMCI_ERROR_REGION_ALREADY_SHARED
 
- VMCI_ERROR_TIMEOUT
 
- VMCI_ERROR_UNAVAILABLE
 
- VMCI_ERROR_WOULD_BLOCK
 
- VMCI_EVENT_CTX_ID_UPDATE
 
- VMCI_EVENT_CTX_REMOVED
 
- VMCI_EVENT_HANDLER
 
- VMCI_EVENT_MAX
 
- VMCI_EVENT_MAX_ATTEMPTS
 
- VMCI_EVENT_MEM_ACCESS_OFF
 
- VMCI_EVENT_MEM_ACCESS_ON
 
- VMCI_EVENT_QP_PEER_ATTACH
 
- VMCI_EVENT_QP_PEER_DETACH
 
- VMCI_EVENT_QP_RESUMED
 
- VMCI_EVENT_SUBSCRIBE
 
- VMCI_EVENT_UNSUBSCRIBE
 
- VMCI_EVENT_VALID
 
- VMCI_EVENT_VALID_VMX
 
- VMCI_FLAG_ANYCID_DG_HND
 
- VMCI_FLAG_DELAYED_CB
 
- VMCI_FLAG_DG_DELAYED_CB
 
- VMCI_FLAG_DG_NONE
 
- VMCI_FLAG_WELLKNOWN_DG_HND
 
- VMCI_GET_CONTEXT_ID
 
- VMCI_HANDLE_ARRAY_DEFAULT_CAPACITY
 
- VMCI_HANDLE_ARRAY_HEADER_SIZE
 
- VMCI_HANDLE_ARRAY_MAX_CAPACITY
 
- VMCI_HGFS_TRANSPORT
 
- VMCI_HOST_CONTEXT_ID
 
- VMCI_HYPERVISOR_CONTEXT_ID
 
- VMCI_ICR_ADDR
 
- VMCI_ICR_DATAGRAM
 
- VMCI_ICR_NOTIFICATION
 
- VMCI_IMR_ADDR
 
- VMCI_IMR_DATAGRAM
 
- VMCI_IMR_NOTIFICATION
 
- VMCI_INTR_DATAGRAM
 
- VMCI_INTR_NOTIFICATION
 
- VMCI_INVALID_ID
 
- VMCI_KERNEL_API_VERSION
 
- VMCI_KERNEL_API_VERSION_1
 
- VMCI_KERNEL_API_VERSION_2
 
- VMCI_LEAST_PRIVILEGE_FLAGS
 
- VMCI_MAKE_VERSION
 
- VMCI_MAX_CONTEXTS
 
- VMCI_MAX_DATAGRAM_AND_EVENT_QUEUE_SIZE
 
- VMCI_MAX_DATAGRAM_QUEUE_SIZE
 
- VMCI_MAX_DELAYED_DG_HOST_QUEUE_SIZE
 
- VMCI_MAX_DEVICES
 
- VMCI_MAX_DG_PAYLOAD_SIZE
 
- VMCI_MAX_DG_SIZE
 
- VMCI_MAX_GUEST_DOORBELL_COUNT
 
- VMCI_MAX_GUEST_QP_COUNT
 
- VMCI_MAX_GUEST_QP_MEMORY
 
- VMCI_MAX_INTRS
 
- VMCI_MAX_PINNED_QP_MEMORY
 
- VMCI_MAX_PRIVILEGE_FLAGS
 
- VMCI_NOTIFICATION_CPT_STATE
 
- VMCI_NOTIFY_RESOURCE_ACTION_CREATE
 
- VMCI_NOTIFY_RESOURCE_ACTION_DESTROY
 
- VMCI_NOTIFY_RESOURCE_ACTION_NOTIFY
 
- VMCI_NOTIFY_RESOURCE_DOOR_BELL
 
- VMCI_NOTIFY_RESOURCE_QUEUE_PAIR
 
- VMCI_NO_PRIVILEGE_FLAGS
 
- VMCI_PRIVILEGE_ALL_FLAGS
 
- VMCI_PRIVILEGE_FLAG_RESTRICTED
 
- VMCI_PRIVILEGE_FLAG_TRUSTED
 
- VMCI_QPFLAG_ATTACH_ONLY
 
- VMCI_QPFLAG_LOCAL
 
- VMCI_QPFLAG_NONBLOCK
 
- VMCI_QPFLAG_PINNED
 
- VMCI_QP_ALL_FLAGS
 
- VMCI_QP_ASYMM
 
- VMCI_QP_ASYMM_PEER
 
- VMCI_QP_PAGESTORE_IS_WELLFORMED
 
- VMCI_QUEUEPAIR_ALLOC
 
- VMCI_QUEUEPAIR_DETACH
 
- VMCI_RESERVED_CID_LIMIT
 
- VMCI_RESERVED_RESOURCE_ID_MAX
 
- VMCI_RESOURCES_QUERY
 
- VMCI_RESOURCE_HASH_BITS
 
- VMCI_RESOURCE_HASH_BUCKETS
 
- VMCI_RESOURCE_MAX
 
- VMCI_RESOURCE_QUERY_MAX_NUM
 
- VMCI_RESOURCE_QUERY_MAX_SIZE
 
- VMCI_RESOURCE_TYPE_ANY
 
- VMCI_RESOURCE_TYPE_API
 
- VMCI_RESOURCE_TYPE_DATAGRAM
 
- VMCI_RESOURCE_TYPE_DOORBELL
 
- VMCI_RESOURCE_TYPE_GROUP
 
- VMCI_RESOURCE_TYPE_QPAIR_GUEST
 
- VMCI_RESOURCE_TYPE_QPAIR_HOST
 
- VMCI_RESULT_HIGH_ADDR
 
- VMCI_RESULT_LOW_ADDR
 
- VMCI_ROUTE_AS_GUEST
 
- VMCI_ROUTE_AS_HOST
 
- VMCI_ROUTE_NONE
 
- VMCI_RPC_PRIVILEGED
 
- VMCI_RPC_UNPRIVILEGED
 
- VMCI_SET_NOTIFY_BITMAP
 
- VMCI_SHAREDMEM_ERROR_BAD_CONTEXT
 
- VMCI_SOCKETS_MAKE_VERSION
 
- VMCI_STATUS_ADDR
 
- VMCI_STATUS_INT_ON
 
- VMCI_SUCCESS
 
- VMCI_SUCCESS_ACCESS_GRANTED
 
- VMCI_SUCCESS_ENTRY_DEAD
 
- VMCI_SUCCESS_LAST_DETACH
 
- VMCI_SUCCESS_QUEUEPAIR_ATTACH
 
- VMCI_SUCCESS_QUEUEPAIR_CREATE
 
- VMCI_TRANSPORT_DEFAULT_QP_SIZE
 
- VMCI_TRANSPORT_DEFAULT_QP_SIZE_MAX
 
- VMCI_TRANSPORT_DEFAULT_QP_SIZE_MIN
 
- VMCI_TRANSPORT_HYPERVISOR_PACKET_RID
 
- VMCI_TRANSPORT_MAX_DGRAM_RESENDS
 
- VMCI_TRANSPORT_PACKET_RID
 
- VMCI_TRANSPORT_PACKET_TYPE_ATTACH
 
- VMCI_TRANSPORT_PACKET_TYPE_INVALID
 
- VMCI_TRANSPORT_PACKET_TYPE_MAX
 
- VMCI_TRANSPORT_PACKET_TYPE_NEGOTIATE
 
- VMCI_TRANSPORT_PACKET_TYPE_NEGOTIATE2
 
- VMCI_TRANSPORT_PACKET_TYPE_OFFER
 
- VMCI_TRANSPORT_PACKET_TYPE_READ
 
- VMCI_TRANSPORT_PACKET_TYPE_REQUEST
 
- VMCI_TRANSPORT_PACKET_TYPE_REQUEST2
 
- VMCI_TRANSPORT_PACKET_TYPE_RST
 
- VMCI_TRANSPORT_PACKET_TYPE_SHUTDOWN
 
- VMCI_TRANSPORT_PACKET_TYPE_WAITING_READ
 
- VMCI_TRANSPORT_PACKET_TYPE_WAITING_WRITE
 
- VMCI_TRANSPORT_PACKET_TYPE_WROTE
 
- VMCI_TRANSPORT_PACKET_VERSION
 
- VMCI_UNITY_PBRPC_REGISTER
 
- VMCI_UTIL_NUM_RESOURCES
 
- VMCI_VERSION
 
- VMCI_VERSION_HOSTQP
 
- VMCI_VERSION_MAJOR
 
- VMCI_VERSION_MINOR
 
- VMCI_VERSION_NOTIFY
 
- VMCI_VERSION_NOVMVM
 
- VMCI_VERSION_PREHOSTQP
 
- VMCI_VERSION_PREVERS2
 
- VMCI_VERSION_SHIFT_WIDTH
 
- VMCI_WELLKNOWN_CPT_STATE
 
- VMCI_WELL_KNOWN_CONTEXT_ID
 
- VMCOREDD_MAX_NAME_BYTES
 
- VMCOREDD_NOTE_NAME
 
- VMCOREINFO_BYTES
 
- VMCOREINFO_CONFIG
 
- VMCOREINFO_LENGTH
 
- VMCOREINFO_NOTE_NAME
 
- VMCOREINFO_NOTE_NAME_BYTES
 
- VMCOREINFO_NOTE_SIZE
 
- VMCOREINFO_NUMBER
 
- VMCOREINFO_OFFSET
 
- VMCOREINFO_OSRELEASE
 
- VMCOREINFO_PAGESIZE
 
- VMCOREINFO_SIZE
 
- VMCOREINFO_STRUCT_SIZE
 
- VMCOREINFO_SYMBOL
 
- VMCOREINFO_SYMBOL_ARRAY
 
- VMCP_GETCODE
 
- VMCP_GETSIZE
 
- VMCP_SETBUF
 
- VMCS12_MAX_FIELD_INDEX
 
- VMCS12_OFFSET
 
- VMCS12_REVISION
 
- VMCS12_SIZE
 
- VMCS_FIELD_WIDTH_NATURAL_WIDTH
 
- VMCS_FIELD_WIDTH_U16
 
- VMCS_FIELD_WIDTH_U32
 
- VMCS_FIELD_WIDTH_U64
 
- VMCS_LINK_POINTER
 
- VMCS_LINK_POINTER_HIGH
 
- VMCS_PAGE
 
- VMC_1_0__SRCID__VM_CONTEXT0_ALL
 
- VMC_1_0__SRCID__VM_CONTEXT1_ALL
 
- VMC_1_0__SRCID__VM_FAULT
 
- VMC_BASE
 
- VMC_BUF_OWNER_ALPHA
 
- VMC_BUF_OWNER_HV
 
- VMC_BUSY
 
- VMC_IH_SRC_ID_END
 
- VMC_IH_SRC_ID_START
 
- VMC_INVALID_BUFFER_ID
 
- VMC_IOCTL_QUERY
 
- VMC_IOCTL_REQUESTVMC
 
- VMC_IOCTL_SETHMCID
 
- VMC_MSG_ADD_BUF
 
- VMC_MSG_ADD_BUF_RESP
 
- VMC_MSG_CAP
 
- VMC_MSG_CAP_RESP
 
- VMC_MSG_CLOSE
 
- VMC_MSG_CLOSED_HMC
 
- VMC_MSG_CLOSE_RESP
 
- VMC_MSG_INTERFACE_FAILURE
 
- VMC_MSG_INVALID_BUFFER_ID
 
- VMC_MSG_INVALID_HMC_INDEX
 
- VMC_MSG_NO_BUFFER
 
- VMC_MSG_OPEN
 
- VMC_MSG_OPEN_RESP
 
- VMC_MSG_REM_BUF
 
- VMC_MSG_REM_BUF_RESP
 
- VMC_MSG_SIGNAL
 
- VMC_MSG_SUCCESS
 
- VMDQ_P
 
- VMD_CFGBAR
 
- VMD_FEAT_HAS_BUS_RESTRICTIONS
 
- VMD_FEAT_HAS_MEMBAR_SHADOW
 
- VMD_MEMBAR1
 
- VMD_MEMBAR2
 
- VMEMCMD_RETURN_IN_ORDER
 
- VMEMCMD_RETURN_IN_ORDER_READ
 
- VMEMCMD_RETURN_ORDER
 
- VMEMCMD_RETURN_OUT_OF_ORDER
 
- VMEMMAP_BASE
 
- VMEMMAP_END
 
- VMEMMAP_NR
 
- VMEMMAP_REGION_ID
 
- VMEMMAP_SHIFT
 
- VMEMMAP_SIZE
 
- VMEMMAP_START
 
- VMEMMAP_START_NR
 
- VMEM_AHB_CLK
 
- VMEM_BCR
 
- VMEM_CTL
 
- VMEM_MAXI_CLK
 
- VMEM_MAX_PHYS
 
- VMEM_PTPAH
 
- VMEM_PTPAL
 
- VMENAMSIZ
 
- VMENTER_L1D_FLUSH_ALWAYS
 
- VMENTER_L1D_FLUSH_AUTO
 
- VMENTER_L1D_FLUSH_COND
 
- VMENTER_L1D_FLUSH_EPT_DISABLED
 
- VMENTER_L1D_FLUSH_NEVER
 
- VMENTER_L1D_FLUSH_NOT_REQUIRED
 
- VMENTRY_CYCLES
 
- VMEXIT_CYCLES
 
- VME_2eSST
 
- VME_2eSST160
 
- VME_2eSST267
 
- VME_2eSST320
 
- VME_2eSSTB
 
- VME_2eVME
 
- VME_A16
 
- VME_A16_MAX
 
- VME_A24
 
- VME_A24_MAX
 
- VME_A32
 
- VME_A32_MAX
 
- VME_A64
 
- VME_A64_MAX
 
- VME_BLT
 
- VME_CONTROL
 
- VME_CRCSR
 
- VME_CRCSR_BUF_SIZE
 
- VME_CRCSR_MAX
 
- VME_D16
 
- VME_D32
 
- VME_D64
 
- VME_D8
 
- VME_DATA
 
- VME_DATA24
 
- VME_DEVS
 
- VME_DMA
 
- VME_DMA_MEM_TO_MEM
 
- VME_DMA_MEM_TO_VME
 
- VME_DMA_PATTERN
 
- VME_DMA_PATTERN_BYTE
 
- VME_DMA_PATTERN_INCREMENT
 
- VME_DMA_PATTERN_TO_MEM
 
- VME_DMA_PATTERN_TO_VME
 
- VME_DMA_PATTERN_WORD
 
- VME_DMA_PCI
 
- VME_DMA_VME
 
- VME_DMA_VME_TO_MEM
 
- VME_DMA_VME_TO_VME
 
- VME_GET_MASTER
 
- VME_GET_SLAVE
 
- VME_IOC_MAGIC
 
- VME_IOID_SPACE
 
- VME_IRQ_GEN
 
- VME_LM
 
- VME_MAJOR
 
- VME_MASTER
 
- VME_MAX_BRIDGES
 
- VME_MAX_SLOTS
 
- VME_MAX_SOURCES
 
- VME_MBLT
 
- VME_MEM_SPACE
 
- VME_NUM_STATUSID
 
- VME_PRIORITY_MODE
 
- VME_PROG
 
- VME_R_ROBIN_MODE
 
- VME_SCT
 
- VME_SET_MASTER
 
- VME_SET_SLAVE
 
- VME_SLAVE
 
- VME_SLOT_ALL
 
- VME_SLOT_CURRENT
 
- VME_SOURCE_BASE
 
- VME_SUPER
 
- VME_TYPE_BVME4000
 
- VME_TYPE_BVME6000
 
- VME_TYPE_MVME147
 
- VME_TYPE_MVME162
 
- VME_TYPE_MVME166
 
- VME_TYPE_MVME167
 
- VME_TYPE_MVME172
 
- VME_TYPE_MVME177
 
- VME_TYPE_TP34V
 
- VME_USER
 
- VME_USER1
 
- VME_USER2
 
- VME_USER3
 
- VME_USER4
 
- VME_USER_BUS_MAX
 
- VMFLAGS
 
- VMFUNC_EPTP_ENTRIES
 
- VMHT_BLOCKING
 
- VMHT_NON_BLOCKING
 
- VMID
 
- VMID_MASK
 
- VMID_SHIFT
 
- VMID_SZ
 
- VMIINTB_EVENT
 
- VMIN
 
- VMIXER_ARRAY_SIZE
 
- VMK8055_AI1_REG
 
- VMK8055_AI2_REG
 
- VMK8055_AO1_REG
 
- VMK8055_AO2_REG
 
- VMK8055_CMD_DEB1_TIME
 
- VMK8055_CMD_DEB2_TIME
 
- VMK8055_CMD_RST
 
- VMK8055_CMD_RST_CNT1
 
- VMK8055_CMD_RST_CNT2
 
- VMK8055_CMD_WRT_AD
 
- VMK8055_CNT1_REG
 
- VMK8055_CNT2_REG
 
- VMK8055_DI_REG
 
- VMK8055_DO_REG
 
- VMK8055_MODEL
 
- VMK8061_AI_REG1
 
- VMK8061_AI_REG2
 
- VMK8061_AO_REG
 
- VMK8061_CH_REG
 
- VMK8061_CMD_CLR_DO
 
- VMK8061_CMD_DO
 
- VMK8061_CMD_OUT_PWM
 
- VMK8061_CMD_RD_AI
 
- VMK8061_CMD_RD_AO
 
- VMK8061_CMD_RD_CNT
 
- VMK8061_CMD_RD_DI
 
- VMK8061_CMD_RD_DO
 
- VMK8061_CMD_RD_JMP_STAT
 
- VMK8061_CMD_RD_PWM
 
- VMK8061_CMD_RD_PWR_STAT
 
- VMK8061_CMD_RD_VERSION
 
- VMK8061_CMD_RST_CNT
 
- VMK8061_CMD_SET_ALL_AO
 
- VMK8061_CMD_SET_AO
 
- VMK8061_CMD_SET_DO
 
- VMK8061_CMR_RD_ALL_AI
 
- VMK8061_CNT_REG
 
- VMK8061_DI_REG
 
- VMK8061_DO_REG
 
- VMK8061_MODEL
 
- VMK8061_PWM_REG1
 
- VMK8061_PWM_REG2
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK
 
- VML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK
 
- VML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT
 
- VML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK
 
- VML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT
 
- VML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK
 
- VML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT
 
- VML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK
 
- VML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT
 
- VML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK
 
- VML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT
 
- VML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK
 
- VML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT
 
- VML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK
 
- VML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT
 
- VML1_0_MC_VM_MX_L1_TLB0_STATUS__BUSY_MASK
 
- VML1_0_MC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT
 
- VML1_0_MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK
 
- VML1_0_MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT
 
- VML1_0_MC_VM_MX_L1_TLB1_STATUS__BUSY_MASK
 
- VML1_0_MC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT
 
- VML1_0_MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK
 
- VML1_0_MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT
 
- VML1_0_MC_VM_MX_L1_TLB2_STATUS__BUSY_MASK
 
- VML1_0_MC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT
 
- VML1_0_MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK
 
- VML1_0_MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT
 
- VML1_0_MC_VM_MX_L1_TLB3_STATUS__BUSY_MASK
 
- VML1_0_MC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT
 
- VML1_0_MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK
 
- VML1_0_MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT
 
- VML1_0_MC_VM_MX_L1_TLB4_STATUS__BUSY_MASK
 
- VML1_0_MC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT
 
- VML1_0_MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK
 
- VML1_0_MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT
 
- VML1_0_MC_VM_MX_L1_TLB5_STATUS__BUSY_MASK
 
- VML1_0_MC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT
 
- VML1_0_MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK
 
- VML1_0_MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT
 
- VML1_0_MC_VM_MX_L1_TLB6_STATUS__BUSY_MASK
 
- VML1_0_MC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT
 
- VML1_0_MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK
 
- VML1_0_MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT
 
- VML1_0_MC_VM_MX_L1_TLB7_STATUS__BUSY_MASK
 
- VML1_0_MC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT
 
- VML1_0_MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK
 
- VML1_0_MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT
 
- VML1_1_MC_VM_MX_L1_TLB0_STATUS__BUSY_MASK
 
- VML1_1_MC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT
 
- VML1_1_MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK
 
- VML1_1_MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT
 
- VML1_1_MC_VM_MX_L1_TLB1_STATUS__BUSY_MASK
 
- VML1_1_MC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT
 
- VML1_1_MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK
 
- VML1_1_MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT
 
- VML1_1_MC_VM_MX_L1_TLB2_STATUS__BUSY_MASK
 
- VML1_1_MC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT
 
- VML1_1_MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK
 
- VML1_1_MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT
 
- VML1_1_MC_VM_MX_L1_TLB3_STATUS__BUSY_MASK
 
- VML1_1_MC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT
 
- VML1_1_MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK
 
- VML1_1_MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT
 
- VML1_1_MC_VM_MX_L1_TLB4_STATUS__BUSY_MASK
 
- VML1_1_MC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT
 
- VML1_1_MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK
 
- VML1_1_MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT
 
- VML1_1_MC_VM_MX_L1_TLB5_STATUS__BUSY_MASK
 
- VML1_1_MC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT
 
- VML1_1_MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK
 
- VML1_1_MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT
 
- VML1_1_MC_VM_MX_L1_TLB6_STATUS__BUSY_MASK
 
- VML1_1_MC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT
 
- VML1_1_MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK
 
- VML1_1_MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT
 
- VML1_1_MC_VM_MX_L1_TLB7_STATUS__BUSY_MASK
 
- VML1_1_MC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT
 
- VML1_1_MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK
 
- VML1_1_MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT
 
- VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK
 
- VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT
 
- VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK
 
- VML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT
 
- VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK
 
- VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT
 
- VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK
 
- VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT
 
- VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK
 
- VML2PF0_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT
 
- VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK
 
- VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT
 
- VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK
 
- VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT
 
- VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK
 
- VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT
 
- VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK
 
- VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT
 
- VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK
 
- VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT
 
- VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK
 
- VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT
 
- VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK
 
- VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT
 
- VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK
 
- VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT
 
- VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK
 
- VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT
 
- VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK
 
- VML2PF0_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT
 
- VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK
 
- VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT
 
- VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK
 
- VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT
 
- VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK
 
- VML2PF0_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT
 
- VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK
 
- VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT
 
- VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK
 
- VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT
 
- VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK
 
- VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT
 
- VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK
 
- VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT
 
- VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK
 
- VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT
 
- VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK
 
- VML2PF0_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT
 
- VML2PF0_VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK
 
- VML2PF0_VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT
 
- VML2PF0_VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
 
- VML2PF0_VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
 
- VML2PF0_VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK
 
- VML2PF0_VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT
 
- VML2PF0_VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK
 
- VML2PF0_VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT
 
- VML2PF0_VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
 
- VML2PF0_VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
 
- VML2PF0_VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK
 
- VML2PF0_VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT
 
- VML2PF0_VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK
 
- VML2PF0_VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT
 
- VML2PF0_VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK
 
- VML2PF0_VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT
 
- VML2PF0_VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK
 
- VML2PF0_VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT
 
- VML2PF0_VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK
 
- VML2PF0_VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT
 
- VML2PF0_VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK
 
- VML2PF0_VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT
 
- VML2PF0_VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK
 
- VML2PF0_VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT
 
- VML2PF0_VM_L2_CNTL3__BANK_SELECT_MASK
 
- VML2PF0_VM_L2_CNTL3__BANK_SELECT__SHIFT
 
- VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK
 
- VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT
 
- VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK
 
- VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT
 
- VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK
 
- VML2PF0_VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT
 
- VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK
 
- VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT
 
- VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK
 
- VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT
 
- VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK
 
- VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT
 
- VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK
 
- VML2PF0_VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT
 
- VML2PF0_VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK
 
- VML2PF0_VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT
 
- VML2PF0_VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK
 
- VML2PF0_VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT
 
- VML2PF0_VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK
 
- VML2PF0_VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT
 
- VML2PF0_VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK
 
- VML2PF0_VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT
 
- VML2PF0_VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK
 
- VML2PF0_VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT
 
- VML2PF0_VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK
 
- VML2PF0_VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT
 
- VML2PF0_VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK
 
- VML2PF0_VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT
 
- VML2PF0_VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK
 
- VML2PF0_VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT
 
- VML2PF0_VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK
 
- VML2PF0_VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT
 
- VML2PF0_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK
 
- VML2PF0_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT
 
- VML2PF0_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK
 
- VML2PF0_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT
 
- VML2PF0_VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK
 
- VML2PF0_VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT
 
- VML2PF0_VM_L2_CNTL__ENABLE_L2_CACHE_MASK
 
- VML2PF0_VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT
 
- VML2PF0_VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK
 
- VML2PF0_VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT
 
- VML2PF0_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK
 
- VML2PF0_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT
 
- VML2PF0_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK
 
- VML2PF0_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT
 
- VML2PF0_VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK
 
- VML2PF0_VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT
 
- VML2PF0_VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK
 
- VML2PF0_VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT
 
- VML2PF0_VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK
 
- VML2PF0_VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT
 
- VML2PF0_VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK
 
- VML2PF0_VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT
 
- VML2PF0_VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK
 
- VML2PF0_VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT
 
- VML2PF0_VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK
 
- VML2PF0_VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT
 
- VML2PF0_VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK
 
- VML2PF0_VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT
 
- VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK
 
- VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT
 
- VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK
 
- VML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK
 
- VML2PF0_VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__CID_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__RW_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VF_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT
 
- VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK
 
- VML2PF0_VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT
 
- VML2PF0_VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK
 
- VML2PF0_VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT
 
- VML2PF0_VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK
 
- VML2PF0_VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT
 
- VML2PF0_VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK
 
- VML2PF0_VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT
 
- VML2PF0_VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK
 
- VML2PF0_VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT
 
- VML2PF0_VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK
 
- VML2PF0_VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT
 
- VML2PF0_VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK
 
- VML2PF0_VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT
 
- VML2PF0_VM_L2_STATUS__L2_BUSY_MASK
 
- VML2PF0_VM_L2_STATUS__L2_BUSY__SHIFT
 
- VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK
 
- VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT
 
- VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK
 
- VML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT
 
- VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK
 
- VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT
 
- VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK
 
- VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT
 
- VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK
 
- VML2PF1_VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT
 
- VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK
 
- VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT
 
- VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK
 
- VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT
 
- VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK
 
- VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT
 
- VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK
 
- VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT
 
- VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK
 
- VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT
 
- VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK
 
- VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT
 
- VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK
 
- VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT
 
- VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK
 
- VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT
 
- VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK
 
- VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT
 
- VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK
 
- VML2PF1_VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT
 
- VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK
 
- VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT
 
- VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK
 
- VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT
 
- VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK
 
- VML2PF1_VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT
 
- VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK
 
- VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT
 
- VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK
 
- VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT
 
- VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK
 
- VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT
 
- VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK
 
- VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT
 
- VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK
 
- VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT
 
- VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK
 
- VML2PF1_VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT
 
- VML2PF1_VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK
 
- VML2PF1_VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT
 
- VML2PF1_VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
 
- VML2PF1_VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
 
- VML2PF1_VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK
 
- VML2PF1_VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT
 
- VML2PF1_VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK
 
- VML2PF1_VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT
 
- VML2PF1_VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
 
- VML2PF1_VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
 
- VML2PF1_VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK
 
- VML2PF1_VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT
 
- VML2PF1_VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK
 
- VML2PF1_VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT
 
- VML2PF1_VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK
 
- VML2PF1_VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT
 
- VML2PF1_VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK
 
- VML2PF1_VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT
 
- VML2PF1_VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK
 
- VML2PF1_VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT
 
- VML2PF1_VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK
 
- VML2PF1_VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT
 
- VML2PF1_VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK
 
- VML2PF1_VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT
 
- VML2PF1_VM_L2_CNTL3__BANK_SELECT_MASK
 
- VML2PF1_VM_L2_CNTL3__BANK_SELECT__SHIFT
 
- VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK
 
- VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT
 
- VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK
 
- VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT
 
- VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK
 
- VML2PF1_VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT
 
- VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK
 
- VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT
 
- VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK
 
- VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT
 
- VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK
 
- VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT
 
- VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK
 
- VML2PF1_VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT
 
- VML2PF1_VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK
 
- VML2PF1_VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT
 
- VML2PF1_VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK
 
- VML2PF1_VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT
 
- VML2PF1_VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK
 
- VML2PF1_VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT
 
- VML2PF1_VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK
 
- VML2PF1_VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT
 
- VML2PF1_VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK
 
- VML2PF1_VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT
 
- VML2PF1_VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK
 
- VML2PF1_VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT
 
- VML2PF1_VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK
 
- VML2PF1_VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT
 
- VML2PF1_VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK
 
- VML2PF1_VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT
 
- VML2PF1_VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK
 
- VML2PF1_VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT
 
- VML2PF1_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK
 
- VML2PF1_VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT
 
- VML2PF1_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK
 
- VML2PF1_VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT
 
- VML2PF1_VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK
 
- VML2PF1_VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT
 
- VML2PF1_VM_L2_CNTL__ENABLE_L2_CACHE_MASK
 
- VML2PF1_VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT
 
- VML2PF1_VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK
 
- VML2PF1_VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT
 
- VML2PF1_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK
 
- VML2PF1_VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT
 
- VML2PF1_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK
 
- VML2PF1_VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT
 
- VML2PF1_VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK
 
- VML2PF1_VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT
 
- VML2PF1_VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK
 
- VML2PF1_VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT
 
- VML2PF1_VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK
 
- VML2PF1_VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT
 
- VML2PF1_VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK
 
- VML2PF1_VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT
 
- VML2PF1_VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK
 
- VML2PF1_VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT
 
- VML2PF1_VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK
 
- VML2PF1_VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT
 
- VML2PF1_VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK
 
- VML2PF1_VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT
 
- VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK
 
- VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT
 
- VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK
 
- VML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK
 
- VML2PF1_VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__CID_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__RW_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VF_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT
 
- VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK
 
- VML2PF1_VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT
 
- VML2PF1_VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK
 
- VML2PF1_VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT
 
- VML2PF1_VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK
 
- VML2PF1_VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT
 
- VML2PF1_VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK
 
- VML2PF1_VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT
 
- VML2PF1_VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK
 
- VML2PF1_VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT
 
- VML2PF1_VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK
 
- VML2PF1_VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT
 
- VML2PF1_VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK
 
- VML2PF1_VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT
 
- VML2PF1_VM_L2_STATUS__L2_BUSY_MASK
 
- VML2PF1_VM_L2_STATUS__L2_BUSY__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT
 
- VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK
 
- VML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT
 
- VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK
 
- VML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT
 
- VML2PR0_MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK
 
- VML2PR0_MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT
 
- VML2PR0_MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK
 
- VML2PR0_MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT
 
- VML2PR0_MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK
 
- VML2PR0_MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT
 
- VML2PR1_MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK
 
- VML2PR1_MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT
 
- VML2PR1_MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK
 
- VML2PR1_MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT
 
- VML2PR1_MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK
 
- VML2PR1_MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT
 
- VML2VC0_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC0_VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC0_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC0_VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC0_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC0_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC0_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC0_VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC0_VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC0_VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC0_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC0_VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC0_VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC0_VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC0_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC0_VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC0_VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC0_VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC0_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC0_VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC0_VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC0_VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC0_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC0_VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC0_VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC0_VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC0_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC0_VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC0_VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC0_VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC0_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC0_VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC0_VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC0_VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC0_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC0_VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC0_VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC0_VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC0_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC0_VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC0_VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC0_VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC0_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC0_VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC0_VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC0_VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC0_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC0_VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC0_VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC0_VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC0_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC0_VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC0_VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC0_VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC0_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC0_VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC0_VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC0_VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC0_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC0_VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC0_VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC0_VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC0_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC0_VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC0_VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC0_VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC0_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC0_VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC0_VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC0_VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC0_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC0_VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC0_VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC0_VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC0_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC0_VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC0_VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC0_VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC0_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC0_VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC0_VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC0_VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC0_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC0_VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC0_VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC0_VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC0_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC0_VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC0_VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC0_VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC0_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC0_VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC0_VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC0_VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC0_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC0_VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC0_VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC0_VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC0_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC0_VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC0_VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC0_VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC0_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC0_VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC0_VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC0_VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC0_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC0_VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC0_VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC0_VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC0_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC0_VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC0_VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC0_VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC0_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC0_VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC0_VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC0_VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC0_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC0_VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC0_VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC0_VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC0_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC0_VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC0_VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC0_VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC0_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC0_VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC0_VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC0_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC0_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC0_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC0_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK
 
- VML2VC0_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC0_VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC0_VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC0_VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC0_VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC0_VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC0_VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC0_VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC0_VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC0_VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC0_VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC0_VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC0_VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC0_VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC0_VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC0_VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC0_VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC0_VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC0_VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC0_VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC0_VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC0_VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC0_VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC0_VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC0_VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC0_VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC0_VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC0_VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC0_VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC0_VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC0_VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC0_VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC0_VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC0_VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC0_VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC0_VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC0_VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC0_VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC0_VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC0_VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC0_VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC0_VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC0_VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC0_VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC0_VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC0_VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC0_VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC0_VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC0_VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC0_VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC0_VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC0_VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC0_VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC0_VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC0_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC0_VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC0_VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK
 
- VML2VC0_VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT
 
- VML2VC1_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC1_VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC1_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC1_VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC1_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC1_VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC1_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC1_VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC1_VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC1_VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC1_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC1_VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC1_VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC1_VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC1_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC1_VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC1_VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC1_VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC1_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC1_VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC1_VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC1_VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC1_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC1_VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC1_VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC1_VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC1_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC1_VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC1_VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC1_VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC1_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC1_VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC1_VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC1_VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC1_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC1_VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC1_VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC1_VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC1_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC1_VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC1_VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC1_VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC1_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC1_VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC1_VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC1_VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC1_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC1_VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC1_VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC1_VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC1_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC1_VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC1_VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC1_VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC1_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC1_VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC1_VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC1_VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC1_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC1_VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC1_VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC1_VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC1_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC1_VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC1_VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC1_VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC1_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC1_VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC1_VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC1_VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC1_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC1_VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC1_VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC1_VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC1_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC1_VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC1_VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC1_VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC1_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC1_VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC1_VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC1_VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC1_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC1_VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC1_VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC1_VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC1_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC1_VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC1_VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC1_VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC1_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC1_VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC1_VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC1_VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC1_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC1_VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC1_VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC1_VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC1_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC1_VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC1_VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC1_VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC1_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC1_VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC1_VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC1_VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC1_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC1_VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC1_VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC1_VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC1_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC1_VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC1_VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC1_VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC1_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC1_VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC1_VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC1_VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC1_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC1_VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC1_VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK
 
- VML2VC1_VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT
 
- VML2VC1_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VML2VC1_VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VML2VC1_VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VML2VC1_VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VML2VC1_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK
 
- VML2VC1_VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VML2VC1_VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VML2VC1_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VML2VC1_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VML2VC1_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VML2VC1_VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK
 
- VML2VC1_VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC1_VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC1_VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC1_VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC1_VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC1_VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC1_VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC1_VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC1_VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC1_VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC1_VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC1_VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC1_VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC1_VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC1_VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC1_VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC1_VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC1_VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC1_VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC1_VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC1_VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC1_VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC1_VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC1_VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC1_VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC1_VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC1_VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC1_VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC1_VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC1_VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC1_VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC1_VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC1_VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC1_VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC1_VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC1_VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC1_VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC1_VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC1_VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC1_VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC1_VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC1_VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC1_VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC1_VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC1_VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC1_VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC1_VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC1_VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC1_VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC1_VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC1_VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC1_VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VML2VC1_VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK
 
- VML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VML2VC1_VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK
 
- VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK
 
- VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK
 
- VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK
 
- VML2VC1_VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VML2VC1_VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VML2VC1_VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK
 
- VML2VC1_VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT
 
- VML_BCLRPAT_A
 
- VML_B_MASK
 
- VML_B_SHIFT
 
- VML_CANVSCLR_A
 
- VML_CONFIG_BASE
 
- VML_CONFIG_CLK_DIV2
 
- VML_CONFIG_CLK_INV
 
- VML_CONFIG_DE_INV
 
- VML_CONFIG_ESTRB_INV
 
- VML_CONFIG_HREF_INV
 
- VML_CONFIG_PIXEL_SWAP
 
- VML_CONFIG_VREF_INV
 
- VML_DEVICE_GPU
 
- VML_DEVICE_VDC
 
- VML_DSPARB
 
- VML_DSPCADDR
 
- VML_DSPCCNTR
 
- VML_DSPCGAMLUT
 
- VML_DSPCPOS
 
- VML_DSPCSIZE
 
- VML_DSPCSTRIDE
 
- VML_FIFO_DEFAULT
 
- VML_GFX_ALPHACONST
 
- VML_GFX_ALPHAMULT
 
- VML_GFX_ARGB1555
 
- VML_GFX_ARGB8888
 
- VML_GFX_CONST_ALPHA
 
- VML_GFX_ENABLE
 
- VML_GFX_GAMMABYPASS
 
- VML_GFX_RGB0888
 
- VML_G_MASK
 
- VML_G_SHIFT
 
- VML_HACTIVE_MASK
 
- VML_HACTIVE_SHIFT
 
- VML_HACTIVE_VAL
 
- VML_HBLANK_A
 
- VML_HBLANK_END_MASK
 
- VML_HBLANK_END_SHIFT
 
- VML_HBLANK_END_VAL
 
- VML_HBLANK_START_MASK
 
- VML_HBLANK_START_SHIFT
 
- VML_HBLANK_START_VAL
 
- VML_HSYNC_A
 
- VML_HSYNC_END_MASK
 
- VML_HSYNC_END_SHIFT
 
- VML_HSYNC_END_VAL
 
- VML_HSYNC_START_MASK
 
- VML_HSYNC_START_SHIFT
 
- VML_HSYNC_START_VAL
 
- VML_HTOTAL_A
 
- VML_HTOTAL_MASK
 
- VML_HTOTAL_SHIFT
 
- VML_HTOTAL_VAL
 
- VML_MAX_XRES
 
- VML_MAX_XRES_VIRTUAL
 
- VML_MAX_YRES
 
- VML_MDVO_PAD_ENABLE
 
- VML_MDVO_POWERSAVE_OFF
 
- VML_MDVO_PULLDOWN_ENABLE
 
- VML_MDVO_VDC_I_RCOMP
 
- VML_PIPEACONF
 
- VML_PIPEASRC
 
- VML_PIPEASRC_HMASK
 
- VML_PIPEASRC_HSHIFT
 
- VML_PIPEASRC_VMASK
 
- VML_PIPEASRC_VSHIFT
 
- VML_PIPE_ARGB_OUTPUT_MODE
 
- VML_PIPE_BASE
 
- VML_PIPE_ENABLE
 
- VML_PIPE_FORCE_BORDER
 
- VML_PIPE_PLANES_OFF
 
- VML_POS_XMASK
 
- VML_POS_XSHIFT
 
- VML_POS_YMASK
 
- VML_POS_YSHIFT
 
- VML_PVOCONFIG
 
- VML_RCOMPSTAT
 
- VML_READ32
 
- VML_R_MASK
 
- VML_R_SHIFT
 
- VML_SISE_WMASK
 
- VML_SIZE_HMASK
 
- VML_SIZE_HSHIFT
 
- VML_SIZE_WSHIFT
 
- VML_TOHW
 
- VML_VACTIVE_MASK
 
- VML_VACTIVE_SHIFT
 
- VML_VACTIVE_VAL
 
- VML_VBLANK_A
 
- VML_VBLANK_END_MASK
 
- VML_VBLANK_END_SHIFT
 
- VML_VBLANK_END_VAL
 
- VML_VBLANK_START_MASK
 
- VML_VBLANK_START_SHIFT
 
- VML_VBLANK_START_VAL
 
- VML_VRAM_AREAS
 
- VML_VSYNC_A
 
- VML_VSYNC_END_MASK
 
- VML_VSYNC_END_SHIFT
 
- VML_VSYNC_END_VAL
 
- VML_VSYNC_START_MASK
 
- VML_VSYNC_START_SHIFT
 
- VML_VSYNC_START_VAL
 
- VML_VTOTAL_A
 
- VML_VTOTAL_MASK
 
- VML_VTOTAL_SHIFT
 
- VML_VTOTAL_VAL
 
- VML_WRITE32
 
- VMMC_AUTO_OFF
 
- VMMC_SEL_MASK
 
- VMMC_SEL_SHIFT
 
- VMMC_ST_MASK
 
- VMMC_ST_SHIFT
 
- VMMDEVREQ_ACKNOWLEDGE_EVENTS
 
- VMMDEVREQ_CHANGE_MEMBALLOON
 
- VMMDEVREQ_CHECK_SHARED_MODULES
 
- VMMDEVREQ_CTL_GUEST_FILTER_MASK
 
- VMMDEVREQ_DEBUG_IS_PAGE_SHARED
 
- VMMDEVREQ_DEREGISTER_PATCH_MEMORY
 
- VMMDEVREQ_GET_CPU_HOTPLUG_REQ
 
- VMMDEVREQ_GET_DISPLAY_CHANGE_REQ
 
- VMMDEVREQ_GET_DISPLAY_CHANGE_REQ2
 
- VMMDEVREQ_GET_DISPLAY_CHANGE_REQEX
 
- VMMDEVREQ_GET_HEIGHT_REDUCTION
 
- VMMDEVREQ_GET_HOST_TIME
 
- VMMDEVREQ_GET_HOST_VERSION
 
- VMMDEVREQ_GET_HYPERVISOR_INFO
 
- VMMDEVREQ_GET_MEMBALLOON_CHANGE_REQ
 
- VMMDEVREQ_GET_MOUSE_STATUS
 
- VMMDEVREQ_GET_PAGE_SHARING_STATUS
 
- VMMDEVREQ_GET_SEAMLESS_CHANGE_REQ
 
- VMMDEVREQ_GET_SESSION_ID
 
- VMMDEVREQ_GET_STATISTICS_CHANGE_REQ
 
- VMMDEVREQ_GET_VRDPCHANGE_REQ
 
- VMMDEVREQ_GUEST_HEARTBEAT
 
- VMMDEVREQ_HEARTBEAT_CONFIGURE
 
- VMMDEVREQ_HGCM_CALL
 
- VMMDEVREQ_HGCM_CALL32
 
- VMMDEVREQ_HGCM_CALL64
 
- VMMDEVREQ_HGCM_CANCEL
 
- VMMDEVREQ_HGCM_CANCEL2
 
- VMMDEVREQ_HGCM_CONNECT
 
- VMMDEVREQ_HGCM_DISCONNECT
 
- VMMDEVREQ_IDLE
 
- VMMDEVREQ_INVALID_REQUEST
 
- VMMDEVREQ_LOG_STRING
 
- VMMDEVREQ_QUERY_CREDENTIALS
 
- VMMDEVREQ_REGISTER_PATCH_MEMORY
 
- VMMDEVREQ_REGISTER_SHARED_MODULE
 
- VMMDEVREQ_REPORT_CREDENTIALS_JUDGEMENT
 
- VMMDEVREQ_REPORT_GUEST_CAPABILITIES
 
- VMMDEVREQ_REPORT_GUEST_INFO
 
- VMMDEVREQ_REPORT_GUEST_INFO2
 
- VMMDEVREQ_REPORT_GUEST_STATS
 
- VMMDEVREQ_REPORT_GUEST_STATUS
 
- VMMDEVREQ_REPORT_GUEST_USER_STATE
 
- VMMDEVREQ_SET_CPU_HOTPLUG_STATUS
 
- VMMDEVREQ_SET_GUEST_CAPABILITIES
 
- VMMDEVREQ_SET_HYPERVISOR_INFO
 
- VMMDEVREQ_SET_MOUSE_STATUS
 
- VMMDEVREQ_SET_POINTER_SHAPE
 
- VMMDEVREQ_SET_POWER_STATUS
 
- VMMDEVREQ_SIZEHACK
 
- VMMDEVREQ_UNREGISTER_SHARED_MODULE
 
- VMMDEVREQ_VIDEMODE_SUPPORTED
 
- VMMDEVREQ_VIDEMODE_SUPPORTED2
 
- VMMDEVREQ_VIDEO_ACCEL_ENABLE
 
- VMMDEVREQ_VIDEO_ACCEL_FLUSH
 
- VMMDEVREQ_VIDEO_SET_VISIBLE_REGION
 
- VMMDEVREQ_WRITE_COREDUMP
 
- VMMDEV_ASSERT_SIZE
 
- VMMDEV_DEVICEID
 
- VMMDEV_EVENT_BALLOON_CHANGE_REQUEST
 
- VMMDEV_EVENT_CPU_HOTPLUG
 
- VMMDEV_EVENT_DISPLAY_CHANGE_REQUEST
 
- VMMDEV_EVENT_HGCM
 
- VMMDEV_EVENT_JUDGE_CREDENTIALS
 
- VMMDEV_EVENT_MOUSE_CAPABILITIES_CHANGED
 
- VMMDEV_EVENT_MOUSE_POSITION_CHANGED
 
- VMMDEV_EVENT_RESTORED
 
- VMMDEV_EVENT_SEAMLESS_MODE_CHANGE_REQUEST
 
- VMMDEV_EVENT_STATISTICS_INTERVAL_CHANGE_REQUEST
 
- VMMDEV_EVENT_VALID_EVENT_MASK
 
- VMMDEV_EVENT_VRDP
 
- VMMDEV_GUEST_INFO2_ADDITIONS_FEATURES_REQUESTOR_INFO
 
- VMMDEV_GUEST_SUPPORTS_GRAPHICS
 
- VMMDEV_GUEST_SUPPORTS_GUEST_HOST_WINDOW_MAPPING
 
- VMMDEV_GUEST_SUPPORTS_SEAMLESS
 
- VMMDEV_HGCM_CALL_PARMS
 
- VMMDEV_HGCM_F_PARM_DIRECTION_BOTH
 
- VMMDEV_HGCM_F_PARM_DIRECTION_FROM_HOST
 
- VMMDEV_HGCM_F_PARM_DIRECTION_NONE
 
- VMMDEV_HGCM_F_PARM_DIRECTION_TO_HOST
 
- VMMDEV_HGCM_LOC_INVALID
 
- VMMDEV_HGCM_LOC_LOCALHOST
 
- VMMDEV_HGCM_LOC_LOCALHOST_EXISTING
 
- VMMDEV_HGCM_LOC_SIZEHACK
 
- VMMDEV_HGCM_MAX_PARMS
 
- VMMDEV_HGCM_PARM_TYPE_32BIT
 
- VMMDEV_HGCM_PARM_TYPE_64BIT
 
- VMMDEV_HGCM_PARM_TYPE_INVALID
 
- VMMDEV_HGCM_PARM_TYPE_LINADDR
 
- VMMDEV_HGCM_PARM_TYPE_LINADDR_IN
 
- VMMDEV_HGCM_PARM_TYPE_LINADDR_KERNEL
 
- VMMDEV_HGCM_PARM_TYPE_LINADDR_KERNEL_IN
 
- VMMDEV_HGCM_PARM_TYPE_LINADDR_KERNEL_OUT
 
- VMMDEV_HGCM_PARM_TYPE_LINADDR_OUT
 
- VMMDEV_HGCM_PARM_TYPE_PAGELIST
 
- VMMDEV_HGCM_PARM_TYPE_PHYSADDR
 
- VMMDEV_HGCM_PARM_TYPE_SIZEHACK
 
- VMMDEV_HGCM_REQ_CANCELLED
 
- VMMDEV_HGCM_REQ_DONE
 
- VMMDEV_HVF_HGCM_PHYS_PAGE_LIST
 
- VMMDEV_MAX_VMMDEVREQ_SIZE
 
- VMMDEV_MEMORY_BALLOON_CHUNK_PAGES
 
- VMMDEV_MEMORY_BALLOON_CHUNK_SIZE
 
- VMMDEV_MEMORY_VERSION
 
- VMMDEV_MOUSE_GUEST_CAN_ABSOLUTE
 
- VMMDEV_MOUSE_GUEST_NEEDS_HOST_CURSOR
 
- VMMDEV_MOUSE_HOST_CANNOT_HWPOINTER
 
- VMMDEV_MOUSE_HOST_HAS_ABS_DEV
 
- VMMDEV_MOUSE_HOST_RECHECKS_NEEDS_HOST_CURSOR
 
- VMMDEV_MOUSE_HOST_WANTS_ABSOLUTE
 
- VMMDEV_MOUSE_NEW_PROTOCOL
 
- VMMDEV_MOUSE_RANGE_MAX
 
- VMMDEV_MOUSE_RANGE_MIN
 
- VMMDEV_OSTYPE_LINUX26
 
- VMMDEV_OSTYPE_X64
 
- VMMDEV_PORT_OFF_REQUEST
 
- VMMDEV_REQUESTOR_CON_DONT_KNOW
 
- VMMDEV_REQUESTOR_CON_MASK
 
- VMMDEV_REQUESTOR_CON_NO
 
- VMMDEV_REQUESTOR_CON_YES
 
- VMMDEV_REQUESTOR_GRP_VBOX
 
- VMMDEV_REQUESTOR_KERNEL
 
- VMMDEV_REQUESTOR_MODE_MASK
 
- VMMDEV_REQUESTOR_TRUST_HIGH
 
- VMMDEV_REQUESTOR_TRUST_LOW
 
- VMMDEV_REQUESTOR_TRUST_MASK
 
- VMMDEV_REQUESTOR_TRUST_MEDIUM
 
- VMMDEV_REQUESTOR_TRUST_MEDIUM_PLUS
 
- VMMDEV_REQUESTOR_TRUST_NOT_GIVEN
 
- VMMDEV_REQUESTOR_TRUST_PROTECTED
 
- VMMDEV_REQUESTOR_TRUST_SYSTEM
 
- VMMDEV_REQUESTOR_TRUST_UNTRUSTED
 
- VMMDEV_REQUESTOR_USERMODE
 
- VMMDEV_REQUESTOR_USER_DEVICE
 
- VMMDEV_REQUESTOR_USR_DRV
 
- VMMDEV_REQUESTOR_USR_DRV_OTHER
 
- VMMDEV_REQUESTOR_USR_MASK
 
- VMMDEV_REQUESTOR_USR_NOT_GIVEN
 
- VMMDEV_REQUESTOR_USR_ROOT
 
- VMMDEV_REQUESTOR_USR_USER
 
- VMMDEV_REQUEST_HEADER_VERSION
 
- VMMDEV_VERSION
 
- VMMDEV_VERSION_MAJOR
 
- VMMDEV_VERSION_MINOR
 
- VMMOUSE_CMD
 
- VMMOUSE_CMD_DISABLE
 
- VMMOUSE_CMD_ENABLE
 
- VMMOUSE_CMD_REQUEST_ABSOLUTE
 
- VMMOUSE_CMD_REQUEST_RELATIVE
 
- VMMOUSE_ERROR
 
- VMMOUSE_LEFT_BUTTON
 
- VMMOUSE_MAX_X
 
- VMMOUSE_MAX_Y
 
- VMMOUSE_MIDDLE_BUTTON
 
- VMMOUSE_NAME
 
- VMMOUSE_PROTO_CMD_ABSPOINTER_COMMAND
 
- VMMOUSE_PROTO_CMD_ABSPOINTER_DATA
 
- VMMOUSE_PROTO_CMD_ABSPOINTER_RESTRICT
 
- VMMOUSE_PROTO_CMD_ABSPOINTER_STATUS
 
- VMMOUSE_PROTO_CMD_GETVERSION
 
- VMMOUSE_PROTO_MAGIC
 
- VMMOUSE_PSNAME
 
- VMMOUSE_RELATIVE_PACKET
 
- VMMOUSE_RESTRICT_ANY
 
- VMMOUSE_RESTRICT_CPL0
 
- VMMOUSE_RESTRICT_IOPL
 
- VMMOUSE_RIGHT_BUTTON
 
- VMMOUSE_VENDOR
 
- VMMOUSE_VERSION_ID
 
- VMM_DEBUG
 
- VMM_FO
 
- VMM_FO032
 
- VMM_FO064
 
- VMM_FO128
 
- VMM_MAP_ITER
 
- VMM_MAP_ITER_DMA
 
- VMM_MAP_ITER_MEM
 
- VMM_MAP_ITER_SGL
 
- VMM_PRINT
 
- VMM_SPAM
 
- VMM_TRACE
 
- VMM_WO
 
- VMM_WO032
 
- VMM_WO064
 
- VMM_WO128
 
- VMM_XO
 
- VMM_XO128
 
- VMNET_CAP_BPF
 
- VMNET_CAP_ENABLE_HEADER_COPY
 
- VMNET_CAP_ENABLE_INT_INLINE
 
- VMNET_CAP_HIGH_DMA
 
- VMNET_CAP_HW_CSUM
 
- VMNET_CAP_HW_RX_VLAN
 
- VMNET_CAP_HW_TX_VLAN
 
- VMNET_CAP_IP4_CSUM
 
- VMNET_CAP_IP6_CSUM
 
- VMNET_CAP_LPD
 
- VMNET_CAP_RX_CHAIN
 
- VMNET_CAP_SG
 
- VMNET_CAP_SG_SPAN_PAGES
 
- VMNET_CAP_SW_TSO
 
- VMNET_CAP_SW_VLAN
 
- VMNET_CAP_TOE
 
- VMNET_CAP_TSO
 
- VMNET_CAP_TSO256k
 
- VMNET_CAP_TSO6
 
- VMNET_CAP_TX_CHAIN
 
- VMNET_CAP_UPT
 
- VMNET_CAP_VMXNET_APROM
 
- VMNET_CAP_WAKE_PCKT_RCV
 
- VMODEADD
 
- VMODE_1024_768_60
 
- VMODE_1024_768_70
 
- VMODE_1024_768_75
 
- VMODE_1024_768_75V
 
- VMODE_1024_768_85
 
- VMODE_1152_768_60
 
- VMODE_1152_864_75
 
- VMODE_1152_870_75
 
- VMODE_1280_1024_60
 
- VMODE_1280_1024_75
 
- VMODE_1280_1024_85
 
- VMODE_1280_960_60
 
- VMODE_1280_960_75
 
- VMODE_1280_960_85
 
- VMODE_1600_1024_60
 
- VMODE_1600_1200_60
 
- VMODE_1600_1200_65
 
- VMODE_1600_1200_70
 
- VMODE_1600_1200_75
 
- VMODE_1600_1200_85
 
- VMODE_1792_1344_60
 
- VMODE_1792_1344_75
 
- VMODE_1856_1392_60
 
- VMODE_1856_1392_75
 
- VMODE_1920_1440_60
 
- VMODE_1920_1440_75
 
- VMODE_512_384_60
 
- VMODE_512_384_60I
 
- VMODE_640_350_85
 
- VMODE_640_400_85
 
- VMODE_640_480_50I
 
- VMODE_640_480_60
 
- VMODE_640_480_60I
 
- VMODE_640_480_67
 
- VMODE_640_480_72
 
- VMODE_640_480_75
 
- VMODE_640_480_85
 
- VMODE_640_870_75P
 
- VMODE_720_400_85
 
- VMODE_768_576_50I
 
- VMODE_800_600_56
 
- VMODE_800_600_60
 
- VMODE_800_600_72
 
- VMODE_800_600_75
 
- VMODE_800_600_85
 
- VMODE_832_624_75
 
- VMODE_CHOOSE
 
- VMODE_DUMB
 
- VMODE_IPE
 
- VMODE_IRE
 
- VMODE_MAX
 
- VMODE_NVRAM
 
- VMODE_PALETTE4BIT
 
- VMODE_PALETTE8BIT
 
- VMODE_RESERVED
 
- VMODE_RGB1555
 
- VMODE_RGB565
 
- VMODE_RGB888PACKED
 
- VMODE_RGB888UNPACKED
 
- VMODE_RGBA888
 
- VMODE_SMPN
 
- VMODE_SMPNCMD
 
- VMODE_SMPNIRQ
 
- VMODE_YUV420PLANAR
 
- VMODE_YUV422PACKED
 
- VMODE_YUV422PLANAR
 
- VMODREGUVALTO_ERR
 
- VMODSEL1VALTO_ERR
 
- VMODSEL2VALTO_ERR
 
- VMON1
 
- VMON10
 
- VMON11
 
- VMON12
 
- VMON2
 
- VMON3
 
- VMON4
 
- VMON5
 
- VMON6
 
- VMON7
 
- VMON8
 
- VMON9
 
- VMON_OV_FAULT
 
- VMON_OV_WARNING
 
- VMON_STATUS0
 
- VMON_STATUS1
 
- VMON_STATUS2
 
- VMON_UV_FAULT
 
- VMON_UV_WARNING
 
- VMOVDQ
 
- VMOVED
 
- VMO_DOUBLE
 
- VMO_INTER
 
- VMO_PREMASK
 
- VMPACKET_DATA_LENGTH
 
- VMPACKET_DATA_START_ADDRESS
 
- VMPACKET_TRANSFER_MODE
 
- VMPG_SIZE
 
- VMPG_SIZE_4KB
 
- VMPG_SIZE_64KB
 
- VMPIDR
 
- VMPRESSURE_CRITICAL
 
- VMPRESSURE_HIERARCHY
 
- VMPRESSURE_LOCAL
 
- VMPRESSURE_LOW
 
- VMPRESSURE_MEDIUM
 
- VMPRESSURE_NO_PASSTHROUGH
 
- VMPRESSURE_NUM_LEVELS
 
- VMPRESSURE_NUM_MODES
 
- VMREAD_BITMAP
 
- VMREAD_BITMAP_HIGH
 
- VMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID__VFID_MASK
 
- VMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT
 
- VMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID__VF_MASK
 
- VMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK
 
- VMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK
 
- VMSHAREDHV0_MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK
 
- VMSHAREDHV0_MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK
 
- VMSHAREDHV0_MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK
 
- VMSHAREDHV0_MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK
 
- VMSHAREDHV0_MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK
 
- VMSHAREDHV0_MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK
 
- VMSHAREDHV0_MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK
 
- VMSHAREDHV0_MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK
 
- VMSHAREDHV0_MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK
 
- VMSHAREDHV0_MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK
 
- VMSHAREDHV0_MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK
 
- VMSHAREDHV0_MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK
 
- VMSHAREDHV0_MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK
 
- VMSHAREDHV0_MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK
 
- VMSHAREDHV0_MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK
 
- VMSHAREDHV0_MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK
 
- VMSHAREDHV0_MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK
 
- VMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT
 
- VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK
 
- VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT
 
- VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
 
- VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
 
- VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK
 
- VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT
 
- VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK
 
- VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT
 
- VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK
 
- VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT
 
- VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
 
- VMSHAREDHV0_UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
 
- VMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK
 
- VMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT
 
- VMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK
 
- VMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT
 
- VMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK
 
- VMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL__STU_MASK
 
- VMSHAREDHV0_VM_PCIE_ATS_CNTL__STU__SHIFT
 
- VMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID__VFID_MASK
 
- VMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT
 
- VMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID__VF_MASK
 
- VMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK
 
- VMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK
 
- VMSHAREDHV1_MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK
 
- VMSHAREDHV1_MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK
 
- VMSHAREDHV1_MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK
 
- VMSHAREDHV1_MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK
 
- VMSHAREDHV1_MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK
 
- VMSHAREDHV1_MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK
 
- VMSHAREDHV1_MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK
 
- VMSHAREDHV1_MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK
 
- VMSHAREDHV1_MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK
 
- VMSHAREDHV1_MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK
 
- VMSHAREDHV1_MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK
 
- VMSHAREDHV1_MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK
 
- VMSHAREDHV1_MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK
 
- VMSHAREDHV1_MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK
 
- VMSHAREDHV1_MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK
 
- VMSHAREDHV1_MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK
 
- VMSHAREDHV1_MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK
 
- VMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT
 
- VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK
 
- VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT
 
- VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
 
- VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
 
- VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK
 
- VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT
 
- VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK
 
- VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT
 
- VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK
 
- VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT
 
- VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
 
- VMSHAREDHV1_UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
 
- VMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK
 
- VMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT
 
- VMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK
 
- VMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT
 
- VMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK
 
- VMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL__STU_MASK
 
- VMSHAREDHV1_VM_PCIE_ATS_CNTL__STU__SHIFT
 
- VMSHAREDPF0_MC_MEM_POWER_LS__LS_HOLD_MASK
 
- VMSHAREDPF0_MC_MEM_POWER_LS__LS_HOLD__SHIFT
 
- VMSHAREDPF0_MC_MEM_POWER_LS__LS_SETUP_MASK
 
- VMSHAREDPF0_MC_MEM_POWER_LS__LS_SETUP__SHIFT
 
- VMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ__PF_MASK
 
- VMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ__PF__SHIFT
 
- VMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ__VF_MASK
 
- VMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ__VF__SHIFT
 
- VMSHAREDPF0_MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK
 
- VMSHAREDPF0_MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT
 
- VMSHAREDPF0_MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK
 
- VMSHAREDPF0_MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT
 
- VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK
 
- VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT
 
- VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK
 
- VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT
 
- VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE_MASK
 
- VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE__SHIFT
 
- VMSHAREDPF0_MC_VM_FB_OFFSET__FB_OFFSET_MASK
 
- VMSHAREDPF0_MC_VM_FB_OFFSET__FB_OFFSET__SHIFT
 
- VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK
 
- VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT
 
- VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK
 
- VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT
 
- VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK
 
- VMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT
 
- VMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK
 
- VMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT
 
- VMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK
 
- VMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT
 
- VMSHAREDPF0_MC_VM_NB_MMIOBASE__MMIOBASE_MASK
 
- VMSHAREDPF0_MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT
 
- VMSHAREDPF0_MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK
 
- VMSHAREDPF0_MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT
 
- VMSHAREDPF0_MC_VM_NB_PCI_ARB__VGA_HOLE_MASK
 
- VMSHAREDPF0_MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT
 
- VMSHAREDPF0_MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK
 
- VMSHAREDPF0_MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT
 
- VMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK
 
- VMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT
 
- VMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK
 
- VMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT
 
- VMSHAREDPF0_MC_VM_STEERING__DEFAULT_STEERING_MASK
 
- VMSHAREDPF0_MC_VM_STEERING__DEFAULT_STEERING__SHIFT
 
- VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK
 
- VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT
 
- VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK
 
- VMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT
 
- VMSHAREDPF0_MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK
 
- VMSHAREDPF0_MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT
 
- VMSHAREDPF0_MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK
 
- VMSHAREDPF0_MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT
 
- VMSHAREDPF0_MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK
 
- VMSHAREDPF0_MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT
 
- VMSHAREDPF1_MC_MEM_POWER_LS__LS_HOLD_MASK
 
- VMSHAREDPF1_MC_MEM_POWER_LS__LS_HOLD__SHIFT
 
- VMSHAREDPF1_MC_MEM_POWER_LS__LS_SETUP_MASK
 
- VMSHAREDPF1_MC_MEM_POWER_LS__LS_SETUP__SHIFT
 
- VMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ__PF_MASK
 
- VMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ__PF__SHIFT
 
- VMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ__VF_MASK
 
- VMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ__VF__SHIFT
 
- VMSHAREDPF1_MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK
 
- VMSHAREDPF1_MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT
 
- VMSHAREDPF1_MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK
 
- VMSHAREDPF1_MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT
 
- VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK
 
- VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT
 
- VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK
 
- VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT
 
- VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE_MASK
 
- VMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE__SHIFT
 
- VMSHAREDPF1_MC_VM_FB_OFFSET__FB_OFFSET_MASK
 
- VMSHAREDPF1_MC_VM_FB_OFFSET__FB_OFFSET__SHIFT
 
- VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK
 
- VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT
 
- VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK
 
- VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT
 
- VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK
 
- VMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT
 
- VMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK
 
- VMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT
 
- VMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK
 
- VMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT
 
- VMSHAREDPF1_MC_VM_NB_MMIOBASE__MMIOBASE_MASK
 
- VMSHAREDPF1_MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT
 
- VMSHAREDPF1_MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK
 
- VMSHAREDPF1_MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT
 
- VMSHAREDPF1_MC_VM_NB_PCI_ARB__VGA_HOLE_MASK
 
- VMSHAREDPF1_MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT
 
- VMSHAREDPF1_MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK
 
- VMSHAREDPF1_MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT
 
- VMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK
 
- VMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT
 
- VMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK
 
- VMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT
 
- VMSHAREDPF1_MC_VM_STEERING__DEFAULT_STEERING_MASK
 
- VMSHAREDPF1_MC_VM_STEERING__DEFAULT_STEERING__SHIFT
 
- VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK
 
- VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT
 
- VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK
 
- VMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT
 
- VMSHAREDPF1_MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK
 
- VMSHAREDPF1_MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT
 
- VMSHAREDPF1_MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK
 
- VMSHAREDPF1_MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT
 
- VMSHAREDPF1_MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK
 
- VMSHAREDPF1_MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT
 
- VMSHAREDVC0_MC_VM_AGP_BASE__AGP_BASE_MASK
 
- VMSHAREDVC0_MC_VM_AGP_BASE__AGP_BASE__SHIFT
 
- VMSHAREDVC0_MC_VM_AGP_BOT__AGP_BOT_MASK
 
- VMSHAREDVC0_MC_VM_AGP_BOT__AGP_BOT__SHIFT
 
- VMSHAREDVC0_MC_VM_AGP_TOP__AGP_TOP_MASK
 
- VMSHAREDVC0_MC_VM_AGP_TOP__AGP_TOP__SHIFT
 
- VMSHAREDVC0_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK
 
- VMSHAREDVC0_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT
 
- VMSHAREDVC0_MC_VM_FB_LOCATION_TOP__FB_TOP_MASK
 
- VMSHAREDVC0_MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT
 
- VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK
 
- VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT
 
- VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK
 
- VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT
 
- VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK
 
- VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT
 
- VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK
 
- VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT
 
- VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK
 
- VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT
 
- VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK
 
- VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT
 
- VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK
 
- VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT
 
- VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK
 
- VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT
 
- VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK
 
- VMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT
 
- VMSHAREDVC1_MC_VM_AGP_BASE__AGP_BASE_MASK
 
- VMSHAREDVC1_MC_VM_AGP_BASE__AGP_BASE__SHIFT
 
- VMSHAREDVC1_MC_VM_AGP_BOT__AGP_BOT_MASK
 
- VMSHAREDVC1_MC_VM_AGP_BOT__AGP_BOT__SHIFT
 
- VMSHAREDVC1_MC_VM_AGP_TOP__AGP_TOP_MASK
 
- VMSHAREDVC1_MC_VM_AGP_TOP__AGP_TOP__SHIFT
 
- VMSHAREDVC1_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK
 
- VMSHAREDVC1_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT
 
- VMSHAREDVC1_MC_VM_FB_LOCATION_TOP__FB_TOP_MASK
 
- VMSHAREDVC1_MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT
 
- VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK
 
- VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT
 
- VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK
 
- VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT
 
- VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK
 
- VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT
 
- VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK
 
- VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT
 
- VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK
 
- VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT
 
- VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK
 
- VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT
 
- VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK
 
- VMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT
 
- VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK
 
- VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT
 
- VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK
 
- VMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT
 
- VMSTOR_PROTO_VERSION
 
- VMSTOR_PROTO_VERSION_WIN10
 
- VMSTOR_PROTO_VERSION_WIN6
 
- VMSTOR_PROTO_VERSION_WIN7
 
- VMSTOR_PROTO_VERSION_WIN8
 
- VMSTOR_PROTO_VERSION_WIN8_1
 
- VMUTE_NORMAL
 
- VMWARE_BACKDOOR_PMC_APPARENT_TIME
 
- VMWARE_BACKDOOR_PMC_HOST_TSC
 
- VMWARE_BACKDOOR_PMC_REAL_TIME
 
- VMWARE_CMD
 
- VMWARE_CMD_GETHZ
 
- VMWARE_CMD_GETVCPU_INFO
 
- VMWARE_CMD_GETVERSION
 
- VMWARE_CMD_LEGACY_X2APIC
 
- VMWARE_CMD_VCPU_RESERVED
 
- VMWARE_FOURCC_UYVY
 
- VMWARE_FOURCC_YUY2
 
- VMWARE_FOURCC_YV12
 
- VMWARE_HYPERCALL
 
- VMWARE_HYPERCALL_HB_IN
 
- VMWARE_HYPERCALL_HB_OUT
 
- VMWARE_HYPERVISOR_HB
 
- VMWARE_HYPERVISOR_MAGIC
 
- VMWARE_HYPERVISOR_OUT
 
- VMWARE_HYPERVISOR_PORT
 
- VMWARE_HYPERVISOR_PORT_HB
 
- VMWARE_PORT
 
- VMWARE_PORT_VMPORT
 
- VMWARE_PORT_VMRPC
 
- VMWARE_VMCALL
 
- VMWARE_VMMCALL
 
- VMWGFX_CHIP_SVGAII
 
- VMWGFX_CMD_BOUNCE_INIT_SIZE
 
- VMWGFX_DRIVER_DATE
 
- VMWGFX_DRIVER_DESC
 
- VMWGFX_DRIVER_MAJOR
 
- VMWGFX_DRIVER_MINOR
 
- VMWGFX_DRIVER_NAME
 
- VMWGFX_DRIVER_PATCHLEVEL
 
- VMWGFX_ENABLE_SCREEN_TARGET_OTABLE
 
- VMWGFX_FIFO_STATIC_SIZE
 
- VMWGFX_GIT_VERSION
 
- VMWGFX_INDEX_PORT
 
- VMWGFX_IRQSTATUS_PORT
 
- VMWGFX_KMS_H_
 
- VMWGFX_MAX_DISPLAYS
 
- VMWGFX_MAX_RELOCATIONS
 
- VMWGFX_MAX_VALIDATIONS
 
- VMWGFX_NUM_DISPLAY_UNITS
 
- VMWGFX_NUM_DXCONTEXT
 
- VMWGFX_NUM_DXQUERY
 
- VMWGFX_NUM_GB_CONTEXT
 
- VMWGFX_NUM_GB_SCREEN_TARGET
 
- VMWGFX_NUM_GB_SHADER
 
- VMWGFX_NUM_GB_SURFACE
 
- VMWGFX_NUM_MOB
 
- VMWGFX_PRESENT_RATE
 
- VMWGFX_REPO
 
- VMWGFX_VALIDATION_MEM_GRAN
 
- VMWGFX_VALUE_PORT
 
- VMWRITE_BITMAP
 
- VMWRITE_BITMAP_HIGH
 
- VMW_ACTION_EVENT
 
- VMW_ACTION_MAX
 
- VMW_BALLOON_2M_ORDER
 
- VMW_BALLOON_2M_PAGE
 
- VMW_BALLOON_4K_PAGE
 
- VMW_BALLOON_64_BIT_TARGET
 
- VMW_BALLOON_BASIC_CMDS
 
- VMW_BALLOON_BATCHED_2M_CMDS
 
- VMW_BALLOON_BATCHED_CMDS
 
- VMW_BALLOON_CAPABILITIES
 
- VMW_BALLOON_CAPABILITIES_COMMON
 
- VMW_BALLOON_CMD_BATCHED_2M_LOCK
 
- VMW_BALLOON_CMD_BATCHED_2M_UNLOCK
 
- VMW_BALLOON_CMD_BATCHED_LOCK
 
- VMW_BALLOON_CMD_BATCHED_UNLOCK
 
- VMW_BALLOON_CMD_GET_TARGET
 
- VMW_BALLOON_CMD_GUEST_ID
 
- VMW_BALLOON_CMD_LAST
 
- VMW_BALLOON_CMD_LOCK
 
- VMW_BALLOON_CMD_NUM
 
- VMW_BALLOON_CMD_START
 
- VMW_BALLOON_CMD_UNLOCK
 
- VMW_BALLOON_CMD_VMCI_DOORBELL_SET
 
- VMW_BALLOON_CMD_WITH_TARGET_MASK
 
- VMW_BALLOON_DEFLATE
 
- VMW_BALLOON_ERROR_BUSY
 
- VMW_BALLOON_ERROR_CMD_INVALID
 
- VMW_BALLOON_ERROR_PPN_INVALID
 
- VMW_BALLOON_ERROR_PPN_LOCKED
 
- VMW_BALLOON_ERROR_PPN_NOTNEEDED
 
- VMW_BALLOON_ERROR_PPN_PINNED
 
- VMW_BALLOON_ERROR_PPN_UNLOCKED
 
- VMW_BALLOON_ERROR_RESET
 
- VMW_BALLOON_GUEST_ID
 
- VMW_BALLOON_HV_MAGIC
 
- VMW_BALLOON_HV_PORT
 
- VMW_BALLOON_INFLATE
 
- VMW_BALLOON_LAST_SIZE
 
- VMW_BALLOON_MAX_REFUSED
 
- VMW_BALLOON_NUM_PAGE_SIZES
 
- VMW_BALLOON_OP_FAIL_STAT
 
- VMW_BALLOON_OP_STAT
 
- VMW_BALLOON_OP_STAT_TYPES
 
- VMW_BALLOON_PAGE_STAT_ALLOC
 
- VMW_BALLOON_PAGE_STAT_ALLOC_FAIL
 
- VMW_BALLOON_PAGE_STAT_FREE
 
- VMW_BALLOON_PAGE_STAT_LAST
 
- VMW_BALLOON_PAGE_STAT_NUM
 
- VMW_BALLOON_PAGE_STAT_REFUSED_ALLOC
 
- VMW_BALLOON_PAGE_STAT_REFUSED_FREE
 
- VMW_BALLOON_SIGNALLED_WAKEUP_CMD
 
- VMW_BALLOON_STAT_DOORBELL
 
- VMW_BALLOON_STAT_LAST
 
- VMW_BALLOON_STAT_NUM
 
- VMW_BALLOON_STAT_RESET
 
- VMW_BALLOON_STAT_SHRINK
 
- VMW_BALLOON_STAT_SHRINK_FREE
 
- VMW_BALLOON_STAT_TIMER
 
- VMW_BALLOON_SUCCESS
 
- VMW_BALLOON_SUCCESS_WITH_CAPABILITIES
 
- VMW_BINDING_NUM_BITS
 
- VMW_BINDING_PS_BIT
 
- VMW_BINDING_PS_SR_BIT
 
- VMW_BINDING_RT_BIT
 
- VMW_BINDING_SO_BIT
 
- VMW_BINDING_VB_BIT
 
- VMW_CMDBUF_INLINE_ALIGN
 
- VMW_CMDBUF_INLINE_SIZE
 
- VMW_CMDBUF_RES_ADD
 
- VMW_CMDBUF_RES_COMMITTED
 
- VMW_CMDBUF_RES_DEL
 
- VMW_CMDBUF_RES_MAN_HT_ORDER
 
- VMW_CMD_DEF
 
- VMW_CPU_BLIT_DIFF_INITIALIZER
 
- VMW_CPU_BLIT_INITIALIZER
 
- VMW_DEBUG_KMS
 
- VMW_DEBUG_USER
 
- VMW_DECLARE_CMD_VAR
 
- VMW_DIRTY_DELAY
 
- VMW_FB_RESERVATION
 
- VMW_FENCE_WAIT_TIMEOUT
 
- VMW_FENCE_WRAP
 
- VMW_FIFO_RESERVE
 
- VMW_FIFO_RESERVE_DX
 
- VMW_FIND_FIRST_DIFF
 
- VMW_FIND_LAST_DIFF
 
- VMW_GET_CTX_NODE
 
- VMW_HYPERVISOR_MAGIC
 
- VMW_IDA_ACC_SIZE
 
- VMW_IOCTL_DEF
 
- VMW_IRQTHREAD_CMDBUF
 
- VMW_IRQTHREAD_FENCE
 
- VMW_IRQTHREAD_MAX
 
- VMW_MAX_NUM_STREAMS
 
- VMW_MAX_VIEW_BINDINGS
 
- VMW_MIN_INITIAL_HEIGHT
 
- VMW_MIN_INITIAL_WIDTH
 
- VMW_MOBFMT_PTDEPTH_0
 
- VMW_MOBFMT_PTDEPTH_1
 
- VMW_MOBFMT_PTDEPTH_2
 
- VMW_OTABLE_SETUP_SUB
 
- VMW_OVERLAY_CAP_MASK
 
- VMW_PL_FLAG_GMR
 
- VMW_PL_FLAG_MOB
 
- VMW_PL_GMR
 
- VMW_PL_MOB
 
- VMW_PORT
 
- VMW_PORT_CMD_CLOSE_CHANNEL
 
- VMW_PORT_CMD_HB_MSG
 
- VMW_PORT_CMD_MSG
 
- VMW_PORT_CMD_OPEN_CHANNEL
 
- VMW_PORT_CMD_RECVSIZE
 
- VMW_PORT_CMD_RECVSTATUS
 
- VMW_PORT_CMD_SENDSIZE
 
- VMW_PORT_HB_IN
 
- VMW_PORT_HB_OUT
 
- VMW_PPN_PER_REMAP
 
- VMW_PPN_SIZE
 
- VMW_RES_CONTEXT
 
- VMW_RES_DIRTY_CLEAR
 
- VMW_RES_DIRTY_NONE
 
- VMW_RES_DIRTY_SET
 
- VMW_RES_EVICT_ERR_COUNT
 
- VMW_RES_FENCE
 
- VMW_RES_HT_ORDER
 
- VMW_RES_SHADER
 
- VMW_RES_STREAM
 
- VMW_RES_SURFACE
 
- VMW_SO_H
 
- VMW_TRY_FIND_FIRST_DIFF
 
- VMW_TRY_FIND_LAST_DIFF
 
- VMX20
 
- VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS
 
- VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER
 
- VMXERR_ENTRY_INVALID_CONTROL_FIELD
 
- VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER
 
- VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
 
- VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS
 
- VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS
 
- VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
 
- VMXERR_UNSUPPORTED_VMCS_COMPONENT
 
- VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID
 
- VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES
 
- VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS
 
- VMXERR_VMCALL_IN_VMX_ROOT_OPERATION
 
- VMXERR_VMCALL_NONCLEAR_VMCS
 
- VMXERR_VMCLEAR_INVALID_ADDRESS
 
- VMXERR_VMCLEAR_VMXON_POINTER
 
- VMXERR_VMLAUNCH_NONCLEAR_VMCS
 
- VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
 
- VMXERR_VMPTRLD_INVALID_ADDRESS
 
- VMXERR_VMPTRLD_VMXON_POINTER
 
- VMXERR_VMRESUME_AFTER_VMXOFF
 
- VMXERR_VMRESUME_NONLAUNCHED_VMCS
 
- VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
 
- VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM
 
- VMXERR_VMXON_IN_VMX_ROOT_OPERATION
 
- VMXNET3_CDTYPE_RXCOMP
 
- VMXNET3_CDTYPE_RXCOMP_LRO
 
- VMXNET3_CDTYPE_TXCOMP
 
- VMXNET3_CLEAR_VFTABLE_ENTRY
 
- VMXNET3_CMD_ACTIVATE_DEV
 
- VMXNET3_CMD_FIRST_GET
 
- VMXNET3_CMD_FIRST_SET
 
- VMXNET3_CMD_GET_COALESCE
 
- VMXNET3_CMD_GET_CONF_INTR
 
- VMXNET3_CMD_GET_DEV_EXTRA_INFO
 
- VMXNET3_CMD_GET_DID_HI
 
- VMXNET3_CMD_GET_DID_LO
 
- VMXNET3_CMD_GET_LINK
 
- VMXNET3_CMD_GET_PERM_MAC_HI
 
- VMXNET3_CMD_GET_PERM_MAC_LO
 
- VMXNET3_CMD_GET_QUEUE_STATUS
 
- VMXNET3_CMD_GET_RESERVED1
 
- VMXNET3_CMD_GET_STATS
 
- VMXNET3_CMD_GET_TXDATA_DESC_SIZE
 
- VMXNET3_CMD_LOAD_PLUGIN
 
- VMXNET3_CMD_QUIESCE_DEV
 
- VMXNET3_CMD_REGISTER_MEMREGS
 
- VMXNET3_CMD_RESERVED1
 
- VMXNET3_CMD_RESERVED2
 
- VMXNET3_CMD_RESERVED3
 
- VMXNET3_CMD_RESET_DEV
 
- VMXNET3_CMD_SET_COALESCE
 
- VMXNET3_CMD_UPDATE_FEATURE
 
- VMXNET3_CMD_UPDATE_IML
 
- VMXNET3_CMD_UPDATE_MAC_FILTERS
 
- VMXNET3_CMD_UPDATE_PMCFG
 
- VMXNET3_CMD_UPDATE_RSSIDT
 
- VMXNET3_CMD_UPDATE_RX_MODE
 
- VMXNET3_CMD_UPDATE_VLAN_FILTERS
 
- VMXNET3_COALESCE_ADAPT
 
- VMXNET3_COALESCE_DISABLED
 
- VMXNET3_COALESCE_RBC
 
- VMXNET3_COALESCE_STATIC
 
- VMXNET3_COAL_RBC_MAX_RATE
 
- VMXNET3_COAL_RBC_MIN_RATE
 
- VMXNET3_COAL_RBC_RATE
 
- VMXNET3_COAL_RBC_USECS
 
- VMXNET3_COAL_STATIC_DEFAULT_DEPTH
 
- VMXNET3_COAL_STATIC_MAX_DEPTH
 
- VMXNET3_DEF_RXDATA_DESC_SIZE
 
- VMXNET3_DEF_RX_RING2_SIZE
 
- VMXNET3_DEF_RX_RING_SIZE
 
- VMXNET3_DEF_TX_RING_SIZE
 
- VMXNET3_DEVICE_MAX_RX_QUEUES
 
- VMXNET3_DEVICE_MAX_TX_QUEUES
 
- VMXNET3_DRIVER_DESC
 
- VMXNET3_DRIVER_VERSION_NUM
 
- VMXNET3_DRIVER_VERSION_REPORT
 
- VMXNET3_DRIVER_VERSION_STRING
 
- VMXNET3_ECR_DEBUG
 
- VMXNET3_ECR_DIC
 
- VMXNET3_ECR_LINK
 
- VMXNET3_ECR_RQERR
 
- VMXNET3_ECR_TQERR
 
- VMXNET3_ERR_BIG_PKT
 
- VMXNET3_ERR_DESC_NOT_SPT
 
- VMXNET3_ERR_NOEOP
 
- VMXNET3_ERR_SMALL_BUF
 
- VMXNET3_ERR_STRESS
 
- VMXNET3_ERR_SWITCH
 
- VMXNET3_ERR_TXD_INVALID
 
- VMXNET3_ERR_TXD_REUSE
 
- VMXNET3_FLIP_RING_GEN
 
- VMXNET3_GET_ADDR_HI
 
- VMXNET3_GET_ADDR_LO
 
- VMXNET3_GET_RING_IDX
 
- VMXNET3_GOS_BITS_32
 
- VMXNET3_GOS_BITS_64
 
- VMXNET3_GOS_BITS_UNK
 
- VMXNET3_GOS_TYPE_LINUX
 
- VMXNET3_HDR_COPY_SIZE
 
- VMXNET3_IC_DISABLE_ALL
 
- VMXNET3_IMM_ACTIVE
 
- VMXNET3_IMM_AUTO
 
- VMXNET3_IMM_LAZY
 
- VMXNET3_INC_RING_IDX_ONLY
 
- VMXNET3_INIT_GEN
 
- VMXNET3_INTR_BUDDYSHARE
 
- VMXNET3_INTR_DONTSHARE
 
- VMXNET3_INTR_TXSHARE
 
- VMXNET3_IO_ADDR
 
- VMXNET3_IO_REG
 
- VMXNET3_IO_TYPE
 
- VMXNET3_IO_TYPE_PT
 
- VMXNET3_IO_TYPE_VD
 
- VMXNET3_IT_AUTO
 
- VMXNET3_IT_INTX
 
- VMXNET3_IT_MSI
 
- VMXNET3_IT_MSIX
 
- VMXNET3_LINK_DOWN
 
- VMXNET3_LINK_UP
 
- VMXNET3_LINUX_MAX_MSIX_VECT
 
- VMXNET3_LINUX_MIN_MSIX_VECT
 
- VMXNET3_MAP_INVALID
 
- VMXNET3_MAP_NONE
 
- VMXNET3_MAP_PAGE
 
- VMXNET3_MAP_SINGLE
 
- VMXNET3_MAX_CSUM_OFFSET
 
- VMXNET3_MAX_ETH_HDR_SIZE
 
- VMXNET3_MAX_INTRS
 
- VMXNET3_MAX_MTU
 
- VMXNET3_MAX_RX_BUF_SIZE
 
- VMXNET3_MAX_RX_QUEUES
 
- VMXNET3_MAX_SKB_BUF_SIZE
 
- VMXNET3_MAX_TXD_PER_PKT
 
- VMXNET3_MAX_TX_BUF_SIZE
 
- VMXNET3_MAX_TX_QUEUES
 
- VMXNET3_MIN_MTU
 
- VMXNET3_MIN_T0_BUF_SIZE
 
- VMXNET3_OM_CSUM
 
- VMXNET3_OM_NONE
 
- VMXNET3_OM_TSO
 
- VMXNET3_PM_MAX_FILTERS
 
- VMXNET3_PM_MAX_MASK_SIZE
 
- VMXNET3_PM_MAX_PATTERN_SIZE
 
- VMXNET3_PM_WAKEUP_FILTER
 
- VMXNET3_PM_WAKEUP_MAGIC
 
- VMXNET3_PT_REG_SIZE
 
- VMXNET3_QUEUE_DESC_ALIGN
 
- VMXNET3_RCD_CSUM_OK
 
- VMXNET3_RCD_GEN_SHIFT
 
- VMXNET3_RCD_IPC_SHIFT
 
- VMXNET3_RCD_RSS_TYPE_IPV4
 
- VMXNET3_RCD_RSS_TYPE_IPV6
 
- VMXNET3_RCD_RSS_TYPE_NONE
 
- VMXNET3_RCD_RSS_TYPE_TCPIPV4
 
- VMXNET3_RCD_RSS_TYPE_TCPIPV6
 
- VMXNET3_RCD_TUC_SHIFT
 
- VMXNET3_RCD_TYPE_SHIFT
 
- VMXNET3_RC_RING_MAX_SIZE
 
- VMXNET3_READ_BAR0_REG
 
- VMXNET3_READ_BAR1_REG
 
- VMXNET3_REG_ALIGN
 
- VMXNET3_REG_ALIGN_MASK
 
- VMXNET3_REG_CMD
 
- VMXNET3_REG_DSAH
 
- VMXNET3_REG_DSAL
 
- VMXNET3_REG_ECR
 
- VMXNET3_REG_ICR
 
- VMXNET3_REG_IMR
 
- VMXNET3_REG_MACH
 
- VMXNET3_REG_MACL
 
- VMXNET3_REG_RXPROD
 
- VMXNET3_REG_RXPROD2
 
- VMXNET3_REG_TXPROD
 
- VMXNET3_REG_UVRS
 
- VMXNET3_REG_VRRS
 
- VMXNET3_REV1_MAGIC
 
- VMXNET3_REV_1
 
- VMXNET3_REV_2
 
- VMXNET3_REV_3
 
- VMXNET3_RING_BA_ALIGN
 
- VMXNET3_RING_BA_MASK
 
- VMXNET3_RING_SIZE_ALIGN
 
- VMXNET3_RING_SIZE_MASK
 
- VMXNET3_RSS
 
- VMXNET3_RSS_IND_TABLE_SIZE
 
- VMXNET3_RXDATA_DESC_MAX_SIZE
 
- VMXNET3_RXDATA_DESC_SIZE_ALIGN
 
- VMXNET3_RXDATA_DESC_SIZE_MASK
 
- VMXNET3_RXD_BTYPE_BODY
 
- VMXNET3_RXD_BTYPE_HEAD
 
- VMXNET3_RXD_BTYPE_SHIFT
 
- VMXNET3_RXD_GEN_SHIFT
 
- VMXNET3_RXM_ALL_MULTI
 
- VMXNET3_RXM_BCAST
 
- VMXNET3_RXM_MCAST
 
- VMXNET3_RXM_PROMISC
 
- VMXNET3_RXM_UCAST
 
- VMXNET3_RX_ALLOC_THRESHOLD
 
- VMXNET3_RX_BUF_NONE
 
- VMXNET3_RX_BUF_PAGE
 
- VMXNET3_RX_BUF_SKB
 
- VMXNET3_RX_DATA_RING
 
- VMXNET3_RX_RING2_MAX_SIZE
 
- VMXNET3_RX_RING_MAX_SIZE
 
- VMXNET3_SET_VFTABLE_ENTRY
 
- VMXNET3_STATE_BIT_QUIESCED
 
- VMXNET3_STATE_BIT_RESETTING
 
- VMXNET3_TCD_GEN_DWORD_SHIFT
 
- VMXNET3_TCD_GEN_SHIFT
 
- VMXNET3_TCD_GEN_SIZE
 
- VMXNET3_TCD_GET_GEN
 
- VMXNET3_TCD_GET_TXIDX
 
- VMXNET3_TCD_TXIDX_SHIFT
 
- VMXNET3_TCD_TXIDX_SIZE
 
- VMXNET3_TC_RING_MAX_SIZE
 
- VMXNET3_TXDATA_DESC_MAX_SIZE
 
- VMXNET3_TXDATA_DESC_MIN_SIZE
 
- VMXNET3_TXDATA_DESC_SIZE_ALIGN
 
- VMXNET3_TXDATA_DESC_SIZE_MASK
 
- VMXNET3_TXDESC_GET_EOP
 
- VMXNET3_TXDESC_GET_GEN
 
- VMXNET3_TXD_CQ
 
- VMXNET3_TXD_CQ_SHIFT
 
- VMXNET3_TXD_EOP
 
- VMXNET3_TXD_EOP_DWORD_SHIFT
 
- VMXNET3_TXD_EOP_SHIFT
 
- VMXNET3_TXD_EOP_SIZE
 
- VMXNET3_TXD_GEN
 
- VMXNET3_TXD_GEN_DWORD_SHIFT
 
- VMXNET3_TXD_GEN_SHIFT
 
- VMXNET3_TXD_GEN_SIZE
 
- VMXNET3_TXD_NEEDED
 
- VMXNET3_TX_RING_MAX_SIZE
 
- VMXNET3_VD_REG_SIZE
 
- VMXNET3_VERSION_GE_2
 
- VMXNET3_VERSION_GE_3
 
- VMXNET3_VFTABLE_ENTRY_IS_SET
 
- VMXNET3_VFT_SIZE
 
- VMXNET3_WAKE_QUEUE_THRESHOLD
 
- VMXNET3_WRITE_BAR0_REG
 
- VMXNET3_WRITE_BAR1_REG
 
- VMXON_CR0_ALWAYSON
 
- VMXON_CR4_ALWAYSON
 
- VMXON_PAGE
 
- VMX_ABORT_LOAD_HOST_MSR_FAIL
 
- VMX_ABORT_LOAD_HOST_PDPTE_FAIL
 
- VMX_ABORT_SAVE_GUEST_MSR_FAIL
 
- VMX_ALIGN
 
- VMX_ALIGN_MASK
 
- VMX_AR_DB_MASK
 
- VMX_AR_DPL
 
- VMX_AR_DPL_SHIFT
 
- VMX_AR_G_MASK
 
- VMX_AR_L_MASK
 
- VMX_AR_P_MASK
 
- VMX_AR_RESERVD_MASK
 
- VMX_AR_S_MASK
 
- VMX_AR_TYPE_ACCESSES_MASK
 
- VMX_AR_TYPE_BUSY_16_TSS
 
- VMX_AR_TYPE_BUSY_32_TSS
 
- VMX_AR_TYPE_BUSY_64_TSS
 
- VMX_AR_TYPE_CODE_MASK
 
- VMX_AR_TYPE_LDT
 
- VMX_AR_TYPE_MASK
 
- VMX_AR_TYPE_READABLE_MASK
 
- VMX_AR_TYPE_WRITEABLE_MASK
 
- VMX_AR_UNUSABLE_MASK
 
- VMX_BASIC_64
 
- VMX_BASIC_INOUT
 
- VMX_BASIC_MEM_TYPE_MASK
 
- VMX_BASIC_MEM_TYPE_SHIFT
 
- VMX_BASIC_MEM_TYPE_WB
 
- VMX_BASIC_TRUE_CTLS
 
- VMX_BASIC_VMCS_SIZE_SHIFT
 
- VMX_BITMAP_NR
 
- VMX_EPTP_AD_ENABLE_BIT
 
- VMX_EPTP_MT_MASK
 
- VMX_EPTP_MT_UC
 
- VMX_EPTP_MT_WB
 
- VMX_EPTP_PWL_4
 
- VMX_EPTP_PWL_5
 
- VMX_EPTP_PWL_MASK
 
- VMX_EPTP_UC_BIT
 
- VMX_EPTP_WB_BIT
 
- VMX_EPT_1GB_PAGE_BIT
 
- VMX_EPT_2MB_PAGE_BIT
 
- VMX_EPT_ACCESS_BIT
 
- VMX_EPT_AD_BIT
 
- VMX_EPT_DIRTY_BIT
 
- VMX_EPT_EXECUTABLE_MASK
 
- VMX_EPT_EXECUTE_ONLY_BIT
 
- VMX_EPT_EXTENT_CONTEXT
 
- VMX_EPT_EXTENT_CONTEXT_BIT
 
- VMX_EPT_EXTENT_GLOBAL
 
- VMX_EPT_EXTENT_GLOBAL_BIT
 
- VMX_EPT_EXTENT_SHIFT
 
- VMX_EPT_IDENTITY_PAGETABLE_ADDR
 
- VMX_EPT_INVEPT_BIT
 
- VMX_EPT_IPAT_BIT
 
- VMX_EPT_MISCONFIG_WX_VALUE
 
- VMX_EPT_MT_EPTE_SHIFT
 
- VMX_EPT_MT_MASK
 
- VMX_EPT_PAGE_WALK_4_BIT
 
- VMX_EPT_PAGE_WALK_5_BIT
 
- VMX_EPT_READABLE_MASK
 
- VMX_EPT_RWX_MASK
 
- VMX_EPT_VPID_CAP_AD_BITS
 
- VMX_EPT_WRITABLE_MASK
 
- VMX_EXIT_REASONS
 
- VMX_EXIT_REASONS_FAILED_VMENTRY
 
- VMX_H
 
- VMX_INSTRUCTION_INFO
 
- VMX_MAX
 
- VMX_MISC_ACTIVITY_HLT
 
- VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
 
- VMX_MISC_MSR_LIST_MULTIPLIER
 
- VMX_MISC_PREEMPTION_TIMER_RATE_MASK
 
- VMX_MISC_SAVE_EFER_LMA
 
- VMX_MISC_ZERO_LEN_INS
 
- VMX_NR_VPIDS
 
- VMX_PREEMPTION_TIMER_VALUE
 
- VMX_SEGMENT_AR_L_MASK
 
- VMX_SEGMENT_FIELD
 
- VMX_THRESH
 
- VMX_VMENTER_INSTRUCTION_ERRORS
 
- VMX_VMFUNC_EPTP_SWITCHING
 
- VMX_VMREAD_BITMAP
 
- VMX_VMWRITE_BITMAP
 
- VMX_VPID_EXTENT_ALL_CONTEXT
 
- VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
 
- VMX_VPID_EXTENT_INDIVIDUAL_ADDR
 
- VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT
 
- VMX_VPID_EXTENT_SINGLE_CONTEXT
 
- VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
 
- VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
 
- VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT
 
- VMX_VPID_EXTENT_SUPPORTED_MASK
 
- VMX_VPID_INVVPID_BIT
 
- VMX_XSS_EXIT_BITMAP
 
- VM_ACCOUNT
 
- VM_ACCT
 
- VM_ALLOC
 
- VM_ARCH_1
 
- VM_ARCH_CLEAR
 
- VM_ARM_EMPTY_MAPPING
 
- VM_ARM_MTYPE
 
- VM_ARM_MTYPE_MASK
 
- VM_ARM_SECTION_MAPPING
 
- VM_ARM_STATIC_MAPPING
 
- VM_BLOCK_DUMP
 
- VM_BUG_ON
 
- VM_BUG_ON_MM
 
- VM_BUG_ON_PAGE
 
- VM_BUG_ON_PGFLAGS
 
- VM_BUG_ON_VMA
 
- VM_CACHE_OPS
 
- VM_CLASS_GGTT
 
- VM_CLASS_PPGTT
 
- VM_CMD_EN
 
- VM_CMD_QUEUE
 
- VM_CMD_QUEUE_CAP
 
- VM_COMPLETIONS_PERIOD_LEN
 
- VM_CONTEXT0_CNTL
 
- VM_CONTEXT0_CNTL2
 
- VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK
 
- VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT
 
- VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK
 
- VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT
 
- VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK
 
- VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT
 
- VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK
 
- VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT
 
- VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK
 
- VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT
 
- VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK
 
- VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT
 
- VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK
 
- VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT
 
- VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK
 
- VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT
 
- VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK
 
- VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT
 
- VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK
 
- VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK
 
- VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT
 
- VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK
 
- VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT
 
- VM_CONTEXT0_INVALIDATION_HIGH_ADDR
 
- VM_CONTEXT0_INVALIDATION_LOW_ADDR
 
- VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
 
- VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK
 
- VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT
 
- VM_CONTEXT0_PAGE_TABLE_END_ADDR
 
- VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK
 
- VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT
 
- VM_CONTEXT0_PAGE_TABLE_START_ADDR
 
- VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK
 
- VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT
 
- VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK
 
- VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT
 
- VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR
 
- VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK
 
- VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT
 
- VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME_MASK
 
- VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT
 
- VM_CONTEXT0_PROTECTION_FAULT_STATUS__ATOMIC_MASK
 
- VM_CONTEXT0_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT
 
- VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK
 
- VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT
 
- VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK
 
- VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT
 
- VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK
 
- VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT
 
- VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID_MASK
 
- VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID__SHIFT
 
- VM_CONTEXT0_REQUEST_RESPONSE
 
- VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK
 
- VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT
 
- VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK
 
- VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT10_PAGE_TABLE_BASE_ADDR
 
- VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK
 
- VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT
 
- VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK
 
- VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT
 
- VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK
 
- VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT11_PAGE_TABLE_BASE_ADDR
 
- VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK
 
- VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT
 
- VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK
 
- VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT
 
- VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK
 
- VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT12_PAGE_TABLE_BASE_ADDR
 
- VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK
 
- VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT
 
- VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK
 
- VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT
 
- VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK
 
- VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT13_PAGE_TABLE_BASE_ADDR
 
- VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK
 
- VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT
 
- VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK
 
- VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT
 
- VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK
 
- VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT14_PAGE_TABLE_BASE_ADDR
 
- VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK
 
- VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT
 
- VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK
 
- VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT
 
- VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK
 
- VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT15_PAGE_TABLE_BASE_ADDR
 
- VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK
 
- VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT
 
- VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT1_CNTL
 
- VM_CONTEXT1_CNTL2
 
- VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK
 
- VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT
 
- VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK
 
- VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT
 
- VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK
 
- VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT
 
- VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK
 
- VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT
 
- VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK
 
- VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT
 
- VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK
 
- VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT
 
- VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK
 
- VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT
 
- VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK
 
- VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT
 
- VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK
 
- VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT
 
- VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK
 
- VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK
 
- VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT
 
- VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK
 
- VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT
 
- VM_CONTEXT1_PAGE_TABLE_BASE_ADDR
 
- VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK
 
- VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT
 
- VM_CONTEXT1_PAGE_TABLE_END_ADDR
 
- VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK
 
- VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT
 
- VM_CONTEXT1_PAGE_TABLE_START_ADDR
 
- VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK
 
- VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT
 
- VM_CONTEXT1_PROTECTION_FAULT_ADDR
 
- VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK
 
- VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT
 
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR
 
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK
 
- VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT
 
- VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT
 
- VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME_MASK
 
- VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT
 
- VM_CONTEXT1_PROTECTION_FAULT_STATUS
 
- VM_CONTEXT1_PROTECTION_FAULT_STATUS__ATOMIC_MASK
 
- VM_CONTEXT1_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT
 
- VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK
 
- VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT
 
- VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK
 
- VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT
 
- VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK
 
- VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT
 
- VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID_MASK
 
- VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID__SHIFT
 
- VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK
 
- VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT
 
- VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK
 
- VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT2_PAGE_TABLE_BASE_ADDR
 
- VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK
 
- VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT
 
- VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK
 
- VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT
 
- VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK
 
- VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT3_PAGE_TABLE_BASE_ADDR
 
- VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK
 
- VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT
 
- VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK
 
- VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT
 
- VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK
 
- VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT4_PAGE_TABLE_BASE_ADDR
 
- VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK
 
- VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT
 
- VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK
 
- VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT
 
- VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK
 
- VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT5_PAGE_TABLE_BASE_ADDR
 
- VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK
 
- VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT
 
- VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK
 
- VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT
 
- VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK
 
- VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT6_PAGE_TABLE_BASE_ADDR
 
- VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK
 
- VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT
 
- VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK
 
- VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT
 
- VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK
 
- VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT7_PAGE_TABLE_BASE_ADDR
 
- VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK
 
- VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT
 
- VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK
 
- VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT
 
- VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK
 
- VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT8_PAGE_TABLE_BASE_ADDR
 
- VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK
 
- VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT
 
- VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK
 
- VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT
 
- VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK
 
- VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT
 
- VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK
 
- VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT
 
- VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_CONTEXT9_PAGE_TABLE_BASE_ADDR
 
- VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK
 
- VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT
 
- VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK
 
- VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT
 
- VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK
 
- VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT
 
- VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK
 
- VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT
 
- VM_CloseAll
 
- VM_ContainerConfig
 
- VM_CtBlockRead
 
- VM_CtBlockRead64
 
- VM_CtBlockVerify
 
- VM_CtBlockVerify64
 
- VM_CtBlockWrite
 
- VM_CtBlockWrite64
 
- VM_CtHostRead64
 
- VM_CtHostWrite64
 
- VM_CtPerf
 
- VM_DATA_DEFAULT_FLAGS
 
- VM_DATA_DEFAULT_FLAGS32
 
- VM_DATA_DEFAULT_FLAGS64
 
- VM_DEBUG__FLAGS_MASK
 
- VM_DEBUG__FLAGS__SHIFT
 
- VM_DENYWRITE
 
- VM_DIRTY_BACKGROUND
 
- VM_DIRTY_EXPIRE_CS
 
- VM_DIRTY_RATIO
 
- VM_DIRTY_WB_CS
 
- VM_DMA_COHERENT
 
- VM_DONE_INT_FLAG
 
- VM_DONTCOPY
 
- VM_DONTDUMP
 
- VM_DONTEXPAND
 
- VM_DROP_PAGECACHE
 
- VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK
 
- VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT
 
- VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK
 
- VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT
 
- VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR_MASK
 
- VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR__SHIFT
 
- VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK
 
- VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT
 
- VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK_MASK
 
- VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK__SHIFT
 
- VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK
 
- VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT
 
- VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK
 
- VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT
 
- VM_DriveBlockRead
 
- VM_DriveBlockWrite
 
- VM_DrvErrTblLog
 
- VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
 
- VM_ENTRY_CONTROLS
 
- VM_ENTRY_DEACT_DUAL_MONITOR
 
- VM_ENTRY_EXCEPTION_ERROR_CODE
 
- VM_ENTRY_IA32E_MODE
 
- VM_ENTRY_INSTRUCTION_LEN
 
- VM_ENTRY_INTR_INFO_FIELD
 
- VM_ENTRY_LOAD_BNDCFGS
 
- VM_ENTRY_LOAD_DEBUG_CONTROLS
 
- VM_ENTRY_LOAD_IA32_EFER
 
- VM_ENTRY_LOAD_IA32_PAT
 
- VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
 
- VM_ENTRY_LOAD_IA32_RTIT_CTL
 
- VM_ENTRY_MSR_LOAD_ADDR
 
- VM_ENTRY_MSR_LOAD_ADDR_HIGH
 
- VM_ENTRY_MSR_LOAD_COUNT
 
- VM_ENTRY_PT_CONCEAL_PIP
 
- VM_ENTRY_SMM
 
- VM_EVENT
 
- VM_EVENT_ITEM_H_INCLUDED
 
- VM_EXEC
 
- VM_EXEC_BIT
 
- VM_EXIT_ACK_INTR_ON_EXIT
 
- VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
 
- VM_EXIT_CLEAR_BNDCFGS
 
- VM_EXIT_CLEAR_IA32_RTIT_CTL
 
- VM_EXIT_CONTROLS
 
- VM_EXIT_HOST_ADDR_SPACE_SIZE
 
- VM_EXIT_INSTRUCTION_LEN
 
- VM_EXIT_INTR_ERROR_CODE
 
- VM_EXIT_INTR_INFO
 
- VM_EXIT_LOAD_IA32_EFER
 
- VM_EXIT_LOAD_IA32_PAT
 
- VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
 
- VM_EXIT_MSR_LOAD_ADDR
 
- VM_EXIT_MSR_LOAD_ADDR_HIGH
 
- VM_EXIT_MSR_LOAD_COUNT
 
- VM_EXIT_MSR_STORE_ADDR
 
- VM_EXIT_MSR_STORE_ADDR_HIGH
 
- VM_EXIT_MSR_STORE_COUNT
 
- VM_EXIT_PT_CONCEAL_PIP
 
- VM_EXIT_REASON
 
- VM_EXIT_SAVE_DEBUG_CONTROLS
 
- VM_EXIT_SAVE_IA32_EFER
 
- VM_EXIT_SAVE_IA32_PAT
 
- VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
 
- VM_EnclosureMgt
 
- VM_FAULT_BADACCESS
 
- VM_FAULT_BADCONTEXT
 
- VM_FAULT_BADMAP
 
- VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MASK_MSB_MASK
 
- VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MASK_MSB__SHIFT
 
- VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MSB_MASK
 
- VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MSB__SHIFT
 
- VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK
 
- VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK_MASK
 
- VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK__SHIFT
 
- VM_FAULT_CLIENT_ID__MEMORY_CLIENT__SHIFT
 
- VM_FAULT_DONE_COW
 
- VM_FAULT_ERROR
 
- VM_FAULT_FALLBACK
 
- VM_FAULT_GET_HINDEX
 
- VM_FAULT_HINDEX_MASK
 
- VM_FAULT_HWPOISON
 
- VM_FAULT_HWPOISON_LARGE
 
- VM_FAULT_LOCKED
 
- VM_FAULT_MAJOR
 
- VM_FAULT_NEEDDSYNC
 
- VM_FAULT_NOPAGE
 
- VM_FAULT_OOM
 
- VM_FAULT_PFAULT
 
- VM_FAULT_RESULT_TRACE
 
- VM_FAULT_RETRY
 
- VM_FAULT_SET_HINDEX
 
- VM_FAULT_SIGBUS
 
- VM_FAULT_SIGNAL
 
- VM_FAULT_SIGSEGV
 
- VM_FAULT_WRITE
 
- VM_FLAGS_CLEAR
 
- VM_FLUSH_RESET_PERMS
 
- VM_FUNCTION_CONTROL
 
- VM_FUNCTION_CONTROL_HIGH
 
- VM_FilesystemIoctl
 
- VM_GROWSDOWN
 
- VM_GROWSUP
 
- VM_HIGH_ARCH_0
 
- VM_HIGH_ARCH_1
 
- VM_HIGH_ARCH_2
 
- VM_HIGH_ARCH_3
 
- VM_HIGH_ARCH_4
 
- VM_HIGH_ARCH_BIT_0
 
- VM_HIGH_ARCH_BIT_1
 
- VM_HIGH_ARCH_BIT_2
 
- VM_HIGH_ARCH_BIT_3
 
- VM_HIGH_ARCH_BIT_4
 
- VM_HUGEPAGE
 
- VM_HUGETLB
 
- VM_HUGETLB_GROUP
 
- VM_HUGETLB_PAGES
 
- VM_INIT_DEF_MASK
 
- VM_INIT_STATUS__VM_INIT_STATUS_MASK
 
- VM_INIT_STATUS__VM_INIT_STATUS__SHIFT
 
- VM_INSTRUCTION_ERROR
 
- VM_INT_DISABLE
 
- VM_INT_ENABLE
 
- VM_INT_MASK
 
- VM_INT_OPS
 
- VM_INT_UNMASK
 
- VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK
 
- VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK
 
- VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT
 
- VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK
 
- VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK
 
- VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK
 
- VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK
 
- VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK
 
- VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK
 
- VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK
 
- VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT
 
- VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK
 
- VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK
 
- VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK
 
- VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK
 
- VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK
 
- VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK
 
- VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK
 
- VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT
 
- VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK
 
- VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK
 
- VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK
 
- VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK
 
- VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK
 
- VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK
 
- VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK
 
- VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT
 
- VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK
 
- VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK
 
- VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK
 
- VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK
 
- VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK
 
- VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK
 
- VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK
 
- VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT
 
- VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK
 
- VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK
 
- VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK
 
- VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK
 
- VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK
 
- VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK
 
- VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK
 
- VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT
 
- VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK
 
- VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK
 
- VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK
 
- VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK
 
- VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK
 
- VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK
 
- VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK
 
- VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT
 
- VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK
 
- VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK
 
- VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK
 
- VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK
 
- VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK
 
- VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK
 
- VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK
 
- VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT
 
- VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK
 
- VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK
 
- VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK
 
- VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK
 
- VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK
 
- VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK
 
- VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK
 
- VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT
 
- VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK
 
- VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK
 
- VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK
 
- VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK
 
- VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK
 
- VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK
 
- VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK
 
- VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT
 
- VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK
 
- VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK
 
- VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK
 
- VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK
 
- VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK
 
- VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK
 
- VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK
 
- VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT
 
- VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK
 
- VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK
 
- VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK
 
- VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK
 
- VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK
 
- VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK
 
- VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK
 
- VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT
 
- VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK
 
- VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK
 
- VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK
 
- VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK
 
- VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK
 
- VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK
 
- VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK
 
- VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT
 
- VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK
 
- VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK
 
- VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK
 
- VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK
 
- VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK
 
- VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK
 
- VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK
 
- VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT
 
- VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK
 
- VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK
 
- VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK
 
- VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK
 
- VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK
 
- VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK
 
- VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK
 
- VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT
 
- VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK
 
- VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK
 
- VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK
 
- VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK
 
- VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK
 
- VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK
 
- VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK
 
- VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT
 
- VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK
 
- VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK
 
- VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK
 
- VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK
 
- VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK
 
- VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK
 
- VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK
 
- VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT
 
- VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK
 
- VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK
 
- VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK
 
- VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK
 
- VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK
 
- VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK
 
- VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT
 
- VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK
 
- VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT
 
- VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK
 
- VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT
 
- VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK
 
- VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT
 
- VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK
 
- VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT
 
- VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK
 
- VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT
 
- VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK
 
- VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT
 
- VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK
 
- VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT
 
- VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK
 
- VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT
 
- VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK
 
- VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT
 
- VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK
 
- VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT
 
- VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK
 
- VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT
 
- VM_INVALIDATE_REQUEST
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0_MASK
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0__SHIFT
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10_MASK
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10__SHIFT
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11_MASK
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11__SHIFT
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12_MASK
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12__SHIFT
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13_MASK
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13__SHIFT
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14_MASK
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14__SHIFT
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15_MASK
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15__SHIFT
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1_MASK
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1__SHIFT
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2_MASK
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2__SHIFT
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3_MASK
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3__SHIFT
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4_MASK
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4__SHIFT
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5_MASK
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5__SHIFT
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6_MASK
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6__SHIFT
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7_MASK
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7__SHIFT
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8_MASK
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8__SHIFT
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9_MASK
 
- VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9__SHIFT
 
- VM_INVALIDATE_RESPONSE
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0_MASK
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0__SHIFT
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10_MASK
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10__SHIFT
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11_MASK
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11__SHIFT
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12_MASK
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12__SHIFT
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13_MASK
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13__SHIFT
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14_MASK
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14__SHIFT
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15_MASK
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15__SHIFT
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1_MASK
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1__SHIFT
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2_MASK
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2__SHIFT
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3_MASK
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3__SHIFT
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4_MASK
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4__SHIFT
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5_MASK
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5__SHIFT
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6_MASK
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6__SHIFT
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7_MASK
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7__SHIFT
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8_MASK
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8__SHIFT
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9_MASK
 
- VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9__SHIFT
 
- VM_IO
 
- VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK
 
- VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT
 
- VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK
 
- VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT
 
- VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK
 
- VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT
 
- VM_IOREMAP
 
- VM_Ioctl
 
- VM_KASAN
 
- VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK_MASK
 
- VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK__SHIFT
 
- VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK_MASK
 
- VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK__SHIFT
 
- VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK
 
- VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT
 
- VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK
 
- VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT
 
- VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK
 
- VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT
 
- VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK
 
- VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT
 
- VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK
 
- VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT
 
- VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK
 
- VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT
 
- VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK
 
- VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT
 
- VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK
 
- VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT
 
- VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK
 
- VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT
 
- VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK
 
- VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT
 
- VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK
 
- VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT
 
- VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK
 
- VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT
 
- VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK
 
- VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT
 
- VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK
 
- VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT
 
- VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK
 
- VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT
 
- VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK
 
- VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT
 
- VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK
 
- VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT
 
- VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK
 
- VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT
 
- VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK
 
- VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT
 
- VM_L2_CG
 
- VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK
 
- VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT
 
- VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
 
- VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
 
- VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK
 
- VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT
 
- VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK
 
- VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT
 
- VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
 
- VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
 
- VM_L2_CG__ENABLE_MASK
 
- VM_L2_CG__ENABLE__SHIFT
 
- VM_L2_CG__MEM_LS_ENABLE_MASK
 
- VM_L2_CG__MEM_LS_ENABLE__SHIFT
 
- VM_L2_CG__OFFDLY_MASK
 
- VM_L2_CG__OFFDLY__SHIFT
 
- VM_L2_CG__OVERRIDE_MASK
 
- VM_L2_CG__OVERRIDE__SHIFT
 
- VM_L2_CNTL
 
- VM_L2_CNTL2
 
- VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK
 
- VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT
 
- VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK
 
- VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT
 
- VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK
 
- VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT
 
- VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK
 
- VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT
 
- VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK
 
- VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT
 
- VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK
 
- VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT
 
- VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK
 
- VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT
 
- VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK
 
- VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT
 
- VM_L2_CNTL3
 
- VM_L2_CNTL3__BANK_SELECT_MASK
 
- VM_L2_CNTL3__BANK_SELECT__SHIFT
 
- VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK
 
- VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT
 
- VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK
 
- VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT
 
- VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK
 
- VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT
 
- VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK
 
- VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT
 
- VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK
 
- VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT
 
- VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK
 
- VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT
 
- VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK
 
- VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT
 
- VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK
 
- VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT
 
- VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK
 
- VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT
 
- VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK
 
- VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT
 
- VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK
 
- VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT
 
- VM_L2_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING_MASK
 
- VM_L2_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING__SHIFT
 
- VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK
 
- VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT
 
- VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK
 
- VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT
 
- VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK
 
- VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT
 
- VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL_MASK
 
- VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL__SHIFT
 
- VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED_MASK
 
- VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED__SHIFT
 
- VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP_MASK
 
- VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP__SHIFT
 
- VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL_MASK
 
- VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL__SHIFT
 
- VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED_MASK
 
- VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED__SHIFT
 
- VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP_MASK
 
- VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP__SHIFT
 
- VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL_MASK
 
- VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL__SHIFT
 
- VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED_MASK
 
- VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED__SHIFT
 
- VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP_MASK
 
- VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP__SHIFT
 
- VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL_MASK
 
- VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL__SHIFT
 
- VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED_MASK
 
- VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED__SHIFT
 
- VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP_MASK
 
- VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP__SHIFT
 
- VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK
 
- VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT
 
- VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK
 
- VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT
 
- VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK
 
- VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT
 
- VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK
 
- VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT
 
- VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK
 
- VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT
 
- VM_L2_CNTL__ENABLE_L2_CACHE_MASK
 
- VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT
 
- VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK
 
- VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT
 
- VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK
 
- VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT
 
- VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK
 
- VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT
 
- VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK
 
- VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT
 
- VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK
 
- VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT
 
- VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK
 
- VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT
 
- VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK
 
- VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT
 
- VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK
 
- VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT
 
- VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK
 
- VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT
 
- VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK
 
- VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT
 
- VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK
 
- VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT
 
- VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK
 
- VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT
 
- VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK
 
- VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT
 
- VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK
 
- VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT
 
- VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK
 
- VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT
 
- VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK
 
- VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT
 
- VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET_MASK
 
- VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK
 
- VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT
 
- VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK
 
- VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT
 
- VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK
 
- VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT
 
- VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK
 
- VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK
 
- VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT
 
- VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT
 
- VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK
 
- VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT
 
- VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK
 
- VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT
 
- VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK
 
- VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT
 
- VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK
 
- VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT
 
- VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK
 
- VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT
 
- VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK
 
- VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT
 
- VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK
 
- VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT
 
- VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK
 
- VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT
 
- VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK
 
- VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT
 
- VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK
 
- VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT
 
- VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK
 
- VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT
 
- VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK
 
- VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT
 
- VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK
 
- VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT
 
- VM_L2_PROTECTION_FAULT_STATUS__CID_MASK
 
- VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT
 
- VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK
 
- VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT
 
- VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK
 
- VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT
 
- VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK
 
- VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT
 
- VM_L2_PROTECTION_FAULT_STATUS__RW_MASK
 
- VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT
 
- VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK
 
- VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT
 
- VM_L2_PROTECTION_FAULT_STATUS__VF_MASK
 
- VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT
 
- VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK
 
- VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT
 
- VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK
 
- VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT
 
- VM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK
 
- VM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT
 
- VM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK
 
- VM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT
 
- VM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK
 
- VM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT
 
- VM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE_MASK
 
- VM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE__SHIFT
 
- VM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE_MASK
 
- VM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE__SHIFT
 
- VM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK
 
- VM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT
 
- VM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK
 
- VM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT
 
- VM_L2_SAW_CNTL3__BANK_SELECT_MASK
 
- VM_L2_SAW_CNTL3__BANK_SELECT__SHIFT
 
- VM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK
 
- VM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT
 
- VM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK
 
- VM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT
 
- VM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK
 
- VM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT
 
- VM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK
 
- VM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT
 
- VM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK
 
- VM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT
 
- VM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK
 
- VM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT
 
- VM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK
 
- VM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT
 
- VM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE_MASK
 
- VM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT
 
- VM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK
 
- VM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT
 
- VM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS_MASK
 
- VM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT
 
- VM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING_MASK
 
- VM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING__SHIFT
 
- VM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK
 
- VM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT
 
- VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL_MASK
 
- VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL__SHIFT
 
- VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED_MASK
 
- VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED__SHIFT
 
- VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP_MASK
 
- VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP__SHIFT
 
- VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL_MASK
 
- VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL__SHIFT
 
- VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED_MASK
 
- VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED__SHIFT
 
- VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP_MASK
 
- VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP__SHIFT
 
- VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL_MASK
 
- VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL__SHIFT
 
- VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED_MASK
 
- VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED__SHIFT
 
- VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP_MASK
 
- VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP__SHIFT
 
- VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL_MASK
 
- VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL__SHIFT
 
- VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED_MASK
 
- VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED__SHIFT
 
- VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP_MASK
 
- VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP__SHIFT
 
- VM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK
 
- VM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT
 
- VM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK
 
- VM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT
 
- VM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK
 
- VM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT
 
- VM_L2_SAW_CNTL__ENABLE_L2_CACHE_MASK
 
- VM_L2_SAW_CNTL__ENABLE_L2_CACHE__SHIFT
 
- VM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK
 
- VM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT
 
- VM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK
 
- VM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT
 
- VM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK
 
- VM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT
 
- VM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK
 
- VM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT
 
- VM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK
 
- VM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT
 
- VM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK
 
- VM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT
 
- VM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK
 
- VM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT
 
- VM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK
 
- VM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT
 
- VM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK
 
- VM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT
 
- VM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK
 
- VM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT
 
- VM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION_MASK
 
- VM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT
 
- VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK
 
- VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT
 
- VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4_MASK
 
- VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32_MASK
 
- VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK
 
- VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT
 
- VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK
 
- VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK
 
- VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT
 
- VM_L2_SAW_PIPES_BUSY__PIPES_BUSY_MASK
 
- VM_L2_SAW_PIPES_BUSY__PIPES_BUSY__SHIFT
 
- VM_L2_STATUS
 
- VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK
 
- VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT
 
- VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK
 
- VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT
 
- VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK
 
- VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT
 
- VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK
 
- VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT
 
- VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK
 
- VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT
 
- VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK
 
- VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT
 
- VM_L2_STATUS__L2_BUSY_MASK
 
- VM_L2_STATUS__L2_BUSY__SHIFT
 
- VM_LAPTOP_MODE
 
- VM_LEGACY_VA_LAYOUT
 
- VM_LEVEL_MAX
 
- VM_LOCKED
 
- VM_LOCKED_CLEAR_MASK
 
- VM_LOCKONFAULT
 
- VM_LOWMEM_RESERVE_RATIO
 
- VM_MAP
 
- VM_MAPPED_COPY
 
- VM_MAP_OFFSET
 
- VM_MAX_MAP_COUNT
 
- VM_MAYEXEC
 
- VM_MAYREAD
 
- VM_MAYSHARE
 
- VM_MAYWRITE
 
- VM_MEM_SRC_ANONYMOUS
 
- VM_MEM_SRC_ANONYMOUS_HUGETLB
 
- VM_MEM_SRC_ANONYMOUS_THP
 
- VM_MERGEABLE
 
- VM_MIN_FREE_KBYTES
 
- VM_MIN_SLAB
 
- VM_MIN_UNMAPPED
 
- VM_MIXEDMAP
 
- VM_MODE_DEFAULT
 
- VM_MODE_P40V48_4K
 
- VM_MODE_P40V48_64K
 
- VM_MODE_P48V48_4K
 
- VM_MODE_P48V48_64K
 
- VM_MODE_P52V48_4K
 
- VM_MODE_P52V48_64K
 
- VM_MODE_PXXV48_4K
 
- VM_MPX
 
- VM_NEWMAP_TYPE_LINEAR
 
- VM_NEWMAP_TYPE_PGTABLES
 
- VM_NOHUGEPAGE
 
- VM_NONE
 
- VM_NORESERVE
 
- VM_NO_GUARD
 
- VM_NO_KHUGEPAGED
 
- VM_NR_PDFLUSH_THREADS
 
- VM_NameServe
 
- VM_NameServe64
 
- VM_NameServeAllBlk
 
- VM_Null
 
- VM_OFF
 
- VM_ON
 
- VM_OVERCOMMIT_MEMORY
 
- VM_OVERCOMMIT_RATIO
 
- VM_PAGEBUF
 
- VM_PAGE_CLUSTER
 
- VM_PANIC_ON_OOM
 
- VM_PAT
 
- VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK
 
- VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT
 
- VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK
 
- VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT
 
- VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK
 
- VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT
 
- VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK
 
- VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT
 
- VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK
 
- VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT
 
- VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK
 
- VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT
 
- VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK
 
- VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT
 
- VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK
 
- VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT
 
- VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK
 
- VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT
 
- VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK
 
- VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT
 
- VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK
 
- VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT
 
- VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK
 
- VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT
 
- VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK
 
- VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT
 
- VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK
 
- VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT
 
- VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK
 
- VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT
 
- VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK
 
- VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT
 
- VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK
 
- VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT
 
- VM_PCIE_ATS_CNTL__STU_MASK
 
- VM_PCIE_ATS_CNTL__STU__SHIFT
 
- VM_PERCPU_PAGELIST_FRACTION
 
- VM_PFNMAP
 
- VM_PKEY_BIT0
 
- VM_PKEY_BIT1
 
- VM_PKEY_BIT2
 
- VM_PKEY_BIT3
 
- VM_PKEY_BIT4
 
- VM_PKEY_SHIFT
 
- VM_PKT_ADDITIONAL_DATA
 
- VM_PKT_ADD_XFER_PAGESET
 
- VM_PKT_CANCEL_REQUEST
 
- VM_PKT_COMP
 
- VM_PKT_DATA_INBAND
 
- VM_PKT_DATA_USING_ADDITIONAL_PKT
 
- VM_PKT_DATA_USING_GPADL
 
- VM_PKT_DATA_USING_GPA_DIRECT
 
- VM_PKT_DATA_USING_XFER_PAGES
 
- VM_PKT_ESTABLISH_GPADL
 
- VM_PKT_INVALID
 
- VM_PKT_RM_XFER_PAGESET
 
- VM_PKT_SYNCH
 
- VM_PKT_TEARDOWN_GPADL
 
- VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK
 
- VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT
 
- VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK
 
- VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT
 
- VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK
 
- VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT
 
- VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK
 
- VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT
 
- VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK
 
- VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT
 
- VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK
 
- VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT
 
- VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK
 
- VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT
 
- VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK
 
- VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT
 
- VM_PRT_CNTL__CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS_MASK
 
- VM_PRT_CNTL__CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS__SHIFT
 
- VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK
 
- VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT
 
- VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK
 
- VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT
 
- VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES_MASK
 
- VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT
 
- VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK
 
- VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT
 
- VM_PRT_CNTL__MASK_PDE0_FAULT_MASK
 
- VM_PRT_CNTL__MASK_PDE0_FAULT__SHIFT
 
- VM_PRT_CNTL__TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS_MASK
 
- VM_PRT_CNTL__TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS__SHIFT
 
- VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK
 
- VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT
 
- VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK
 
- VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT
 
- VM_RAND_READ
 
- VM_READ
 
- VM_READAHEAD_PAGES
 
- VM_READ_BIT
 
- VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL_MASK
 
- VM_REQUEST_PHYSICAL__PDE_REQUEST_PHYSICAL__SHIFT
 
- VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL_MASK
 
- VM_REQUEST_PHYSICAL__PTE_REQUEST_PHYSICAL__SHIFT
 
- VM_SAO
 
- VM_SEQ_READ
 
- VM_SHARED
 
- VM_SOCKETS_INVALID_VERSION
 
- VM_SOCKETS_VERSION_EPOCH
 
- VM_SOCKETS_VERSION_MAJOR
 
- VM_SOCKETS_VERSION_MINOR
 
- VM_SOFTDIRTY
 
- VM_SPARC_ADI
 
- VM_SPECIAL
 
- VM_STACK
 
- VM_STACK_DEFAULT_FLAGS
 
- VM_STACK_DEFAULT_FLAGS32
 
- VM_STACK_DEFAULT_FLAGS64
 
- VM_STACK_FLAGS
 
- VM_STACK_INCOMPLETE_SETUP
 
- VM_STAT
 
- VM_SWAPPINESS
 
- VM_SWAP_TOKEN_TIMEOUT
 
- VM_SYNC
 
- VM_SliceBlockRead
 
- VM_SliceBlockWrite
 
- VM_TLB_INVALIDATE_FALSE
 
- VM_TLB_INVALIDATE_TRUE
 
- VM_TRANS_TYPE_LINEAR
 
- VM_TRANS_TYPE_TABLE
 
- VM_TYPE_PHYS_PACK
 
- VM_TYPE_USERPTR
 
- VM_UFFD_MISSING
 
- VM_UFFD_WP
 
- VM_UNICORE_SECTION_MAPPING
 
- VM_UNINITIALIZED
 
- VM_UNMAPPED_AREA_TOPDOWN
 
- VM_UNUSED1
 
- VM_UNUSED2
 
- VM_UNUSED3
 
- VM_UNUSED4
 
- VM_UNUSED5
 
- VM_UNUSED7
 
- VM_UNUSED8
 
- VM_UNUSED9
 
- VM_USERMAP
 
- VM_Unused
 
- VM_VDSO_ENABLED
 
- VM_VFS_CACHE_PRESSURE
 
- VM_WARN
 
- VM_WARN_ON
 
- VM_WARN_ONCE
 
- VM_WARN_ON_ONCE
 
- VM_WIPEONFORK
 
- VM_WRITE
 
- VM_WRITE_BIT
 
- VM_ZONE_RECLAIM_MODE
 
- VMwareVideoGetAttributes
 
- VNC1A_REG
 
- VNC1B_REG
 
- VNC1C_REG
 
- VNC2A_REG
 
- VNC2B_REG
 
- VNC2C_REG
 
- VNC3A_REG
 
- VNC3B_REG
 
- VNC3C_REG
 
- VNC4A_REG
 
- VNC4B_REG
 
- VNC4C_REG
 
- VNC5A_REG
 
- VNC5B_REG
 
- VNC5C_REG
 
- VNC6A_REG
 
- VNC6B_REG
 
- VNC6C_REG
 
- VNC7A_REG
 
- VNC7B_REG
 
- VNC7C_REG
 
- VNC8A_REG
 
- VNC8B_REG
 
- VNC8C_REG
 
- VNCSI_IFMD_CSI_CHSEL
 
- VNCSI_IFMD_CSI_CHSEL_MASK
 
- VNCSI_IFMD_DES0
 
- VNCSI_IFMD_DES1
 
- VNCSI_IFMD_REG
 
- VNDMR2_CES
 
- VNDMR2_FTEV
 
- VNDMR2_HPS
 
- VNDMR2_REG
 
- VNDMR2_VLV
 
- VNDMR2_VPS
 
- VNDMR_A8BIT
 
- VNDMR_A8BIT_MASK
 
- VNDMR_ABIT
 
- VNDMR_BPSM
 
- VNDMR_DTMD_ARGB
 
- VNDMR_DTMD_YCSEP
 
- VNDMR_EXRGB
 
- VNDMR_REG
 
- VNDMY_ABLMGSHLMT
 
- VNDR_IE_CMD_LEN
 
- VNDR_IE_COUNT_OFFSET
 
- VNDR_IE_HDR_SIZE
 
- VNDR_IE_PARSE_LIMIT
 
- VNDR_IE_PKTFLAG_OFFSET
 
- VNDR_IE_VSIE_OFFSET
 
- VND_CMD_ERASE
 
- VND_CMD_RESET
 
- VND_CMD_SFLCK
 
- VND_CMD_SFUNL
 
- VND_CMD_START
 
- VND_CMD_STOP
 
- VND_GET_CHECKSUM
 
- VND_READ_DATA
 
- VND_REQ_READ
 
- VND_REQ_WRITE
 
- VND_SET_CHECKSUM_CALC
 
- VND_SET_CHECKSUM_LENGTH
 
- VND_SET_COMMAND_DATA
 
- VND_SET_DATA
 
- VNELPOC_REG
 
- VNELPRC_REG
 
- VNEPPOC_REG
 
- VNEPPRC_REG
 
- VNET_ADDR_ETHERMAC
 
- VNET_CLEAN_TIMEOUT
 
- VNET_HDR_FAIL
 
- VNET_LSO_IPV4_CAPAB
 
- VNET_MAXCOOKIES
 
- VNET_MAXPACKET
 
- VNET_MAXTSO
 
- VNET_MAX_MTU
 
- VNET_MAX_RETRIES
 
- VNET_MAX_TXQS
 
- VNET_MCAST_INFO
 
- VNET_MINTSO
 
- VNET_NUM_MCAST
 
- VNET_PACKET_SKIP
 
- VNET_PKT_HASH
 
- VNET_PKT_HCK_FULLCKSUM
 
- VNET_PKT_HCK_FULLCKSUM_OK
 
- VNET_PKT_HCK_IPV4_HDRCKSUM
 
- VNET_PKT_HCK_IPV4_HDRCKSUM_OK
 
- VNET_PKT_IPV4_LSO
 
- VNET_PORT_HASH_MASK
 
- VNET_PORT_HASH_SIZE
 
- VNET_PORT_TO_NET_DEVICE
 
- VNET_TX_RING_SIZE
 
- VNET_TX_TIMEOUT
 
- VNET_TX_WAKEUP_THRESH
 
- VNFC_C_FRAME
 
- VNFC_REG
 
- VNFC_S_FRAME
 
- VNICC_DATA_SIZEOF
 
- VNIC_ALLOC_REQ_FLAGS_DEFAULT
 
- VNIC_CFG_REQ_ENABLES_COS_RULE
 
- VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID
 
- VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID
 
- VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP
 
- VNIC_CFG_REQ_ENABLES_LB_RULE
 
- VNIC_CFG_REQ_ENABLES_MRU
 
- VNIC_CFG_REQ_ENABLES_QUEUE_ID
 
- VNIC_CFG_REQ_ENABLES_RSS_RULE
 
- VNIC_CFG_REQ_FLAGS_BD_STALL_MODE
 
- VNIC_CFG_REQ_FLAGS_DEFAULT
 
- VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE
 
- VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE
 
- VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE
 
- VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE
 
- VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE
 
- VNIC_CLOSED
 
- VNIC_CLOSING
 
- VNIC_DEVCMD2_NARGS
 
- VNIC_DEVCMD2_NRESULTS
 
- VNIC_DEVCMD_NARGS
 
- VNIC_DEV_INTR_MODE_INTX
 
- VNIC_DEV_INTR_MODE_MSI
 
- VNIC_DEV_INTR_MODE_MSIX
 
- VNIC_DEV_INTR_MODE_UNKNOWN
 
- VNIC_DVCMD_TMO
 
- VNIC_ENV_OFF
 
- VNIC_F
 
- VNIC_FNIC_EDTOV_DEF
 
- VNIC_FNIC_EDTOV_MAX
 
- VNIC_FNIC_EDTOV_MIN
 
- VNIC_FNIC_FLOGI_RETRIES_DEF
 
- VNIC_FNIC_FLOGI_RETRIES_MAX
 
- VNIC_FNIC_FLOGI_RETRIES_MIN
 
- VNIC_FNIC_FLOGI_TIMEOUT_MAX
 
- VNIC_FNIC_FLOGI_TIMEOUT_MIN
 
- VNIC_FNIC_IO_THROTTLE_COUNT_MAX
 
- VNIC_FNIC_IO_THROTTLE_COUNT_MIN
 
- VNIC_FNIC_LINK_DOWN_TIMEOUT_MAX
 
- VNIC_FNIC_LINK_DOWN_TIMEOUT_MIN
 
- VNIC_FNIC_LUNS_PER_TARGET_MAX
 
- VNIC_FNIC_LUNS_PER_TARGET_MIN
 
- VNIC_FNIC_MAXDATAFIELDSIZE_MAX
 
- VNIC_FNIC_MAXDATAFIELDSIZE_MIN
 
- VNIC_FNIC_PLOGI_RETRIES_DEF
 
- VNIC_FNIC_PLOGI_RETRIES_MAX
 
- VNIC_FNIC_PLOGI_RETRIES_MIN
 
- VNIC_FNIC_PLOGI_TIMEOUT_MAX
 
- VNIC_FNIC_PLOGI_TIMEOUT_MIN
 
- VNIC_FNIC_PORT_DOWN_IO_RETRIES_MAX
 
- VNIC_FNIC_PORT_DOWN_IO_RETRIES_MIN
 
- VNIC_FNIC_PORT_DOWN_TIMEOUT_MAX
 
- VNIC_FNIC_PORT_DOWN_TIMEOUT_MIN
 
- VNIC_FNIC_RATOV_MAX
 
- VNIC_FNIC_RATOV_MIN
 
- VNIC_FNIC_RQ_DESCS_MAX
 
- VNIC_FNIC_RQ_DESCS_MIN
 
- VNIC_FNIC_WQ_COPY_COUNT_MAX
 
- VNIC_FNIC_WQ_COPY_COUNT_MIN
 
- VNIC_FNIC_WQ_COPY_DESCS_MAX
 
- VNIC_FNIC_WQ_COPY_DESCS_MIN
 
- VNIC_FNIC_WQ_DESCS_MAX
 
- VNIC_FNIC_WQ_DESCS_MIN
 
- VNIC_ID_F
 
- VNIC_ID_S
 
- VNIC_ID_V
 
- VNIC_INFO_PROT_L2
 
- VNIC_INFO_PROT_L3
 
- VNIC_INTR_RESET_TIMER_SHIFT
 
- VNIC_INTR_TIMER_MAX
 
- VNIC_INTR_TIMER_TYPE_ABS
 
- VNIC_INTR_TIMER_TYPE_QUIET
 
- VNIC_INTR_UNMASK_SHIFT
 
- VNIC_MAX_RES_HDR_SIZE
 
- VNIC_MODE
 
- VNIC_NOTIFY_INTR_MASK
 
- VNIC_OPEN
 
- VNIC_OPENING
 
- VNIC_PADDR_TARGET
 
- VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID
 
- VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID
 
- VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID
 
- VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE
 
- VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4
 
- VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6
 
- VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE
 
- VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT
 
- VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT
 
- VNIC_PROBED
 
- VNIC_PROBING
 
- VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP
 
- VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP
 
- VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP
 
- VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP
 
- VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP
 
- VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP
 
- VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP
 
- VNIC_QCAPS_RESP_FLAGS_UNUSED
 
- VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP
 
- VNIC_REMOVED
 
- VNIC_REMOVING
 
- VNIC_RESET_CHANGE_PARAM
 
- VNIC_RESET_FAILOVER
 
- VNIC_RESET_FATAL
 
- VNIC_RESET_MOBILITY
 
- VNIC_RESET_NON_FATAL
 
- VNIC_RESET_TIMEOUT
 
- VNIC_RES_MAGIC
 
- VNIC_RES_STRIDE
 
- VNIC_RES_VERSION
 
- VNIC_RQ_BUF_BLKS_MAX
 
- VNIC_RQ_BUF_BLKS_NEEDED
 
- VNIC_RQ_BUF_BLK_ENTRIES
 
- VNIC_RQ_BUF_BLK_SZ
 
- VNIC_RQ_BUF_DFLT_BLK_ENTRIES
 
- VNIC_RQ_BUF_MIN_BLK_ENTRIES
 
- VNIC_RQ_DEFER_RETURN_DESC
 
- VNIC_RQ_RETURN_DESC
 
- VNIC_RQ_RETURN_RATE
 
- VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT
 
- VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2
 
- VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4
 
- VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2
 
- VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4
 
- VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4
 
- VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6
 
- VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4
 
- VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6
 
- VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4
 
- VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6
 
- VNIC_S
 
- VNIC_SNIC_IO_THROTTLE_COUNT_MAX
 
- VNIC_SNIC_IO_THROTTLE_COUNT_MIN
 
- VNIC_SNIC_LUNS_PER_TARGET_MAX
 
- VNIC_SNIC_LUNS_PER_TARGET_MIN
 
- VNIC_SNIC_MAXDATAFIELDSIZE_MAX
 
- VNIC_SNIC_MAXDATAFIELDSIZE_MIN
 
- VNIC_SNIC_PORT_DOWN_IO_RETRIES_MAX
 
- VNIC_SNIC_PORT_DOWN_IO_RETRIES_MIN
 
- VNIC_SNIC_PORT_DOWN_TIMEOUT_MAX
 
- VNIC_SNIC_PORT_DOWN_TIMEOUT_MIN
 
- VNIC_SNIC_WQ_DESCS_MAX
 
- VNIC_SNIC_WQ_DESCS_MIN
 
- VNIC_STAT
 
- VNIC_STATS
 
- VNIC_STATS_LEN
 
- VNIC_STF_ALL
 
- VNIC_STF_FATAL_ERR
 
- VNIC_STF_PFC_PAUSE
 
- VNIC_STF_STD_PAUSE
 
- VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS
 
- VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS
 
- VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER
 
- VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN
 
- VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO
 
- VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN
 
- VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ
 
- VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA
 
- VNIC_TPA_CFG_REQ_FLAGS_GRO
 
- VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK
 
- VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK
 
- VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE
 
- VNIC_TPA_CFG_REQ_FLAGS_TPA
 
- VNIC_TPA_CFG_REQ_MAX_AGGS_1
 
- VNIC_TPA_CFG_REQ_MAX_AGGS_16
 
- VNIC_TPA_CFG_REQ_MAX_AGGS_2
 
- VNIC_TPA_CFG_REQ_MAX_AGGS_4
 
- VNIC_TPA_CFG_REQ_MAX_AGGS_8
 
- VNIC_TPA_CFG_REQ_MAX_AGGS_LAST
 
- VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
 
- VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1
 
- VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2
 
- VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4
 
- VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8
 
- VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST
 
- VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX
 
- VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN
 
- VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ
 
- VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA
 
- VNIC_TPA_QCFG_RESP_FLAGS_GRO
 
- VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK
 
- VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK
 
- VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE
 
- VNIC_TPA_QCFG_RESP_FLAGS_TPA
 
- VNIC_TPA_QCFG_RESP_MAX_AGGS_1
 
- VNIC_TPA_QCFG_RESP_MAX_AGGS_16
 
- VNIC_TPA_QCFG_RESP_MAX_AGGS_2
 
- VNIC_TPA_QCFG_RESP_MAX_AGGS_4
 
- VNIC_TPA_QCFG_RESP_MAX_AGGS_8
 
- VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST
 
- VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX
 
- VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1
 
- VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2
 
- VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4
 
- VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8
 
- VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST
 
- VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX
 
- VNIC_V
 
- VNIC_WQ_BUF_BLKS_MAX
 
- VNIC_WQ_BUF_BLKS_NEEDED
 
- VNIC_WQ_BUF_BLK_ENTRIES
 
- VNIC_WQ_BUF_BLK_SZ
 
- VNIC_WQ_BUF_DFLT_BLK_ENTRIES
 
- VNIC_WQ_BUF_MIN_BLK_ENTRIES
 
- VNIC_WQ_COPY_MAX
 
- VNID_AMIC1_ASEL
 
- VNID_AMIC1_SEL
 
- VNID_HP_ASEL
 
- VNID_HP_SEL
 
- VNID_MIC
 
- VNID_SPK
 
- VNIE_EFE
 
- VNIE_FIE
 
- VNIE_REG
 
- VNINTS_REG
 
- VNIS_REG
 
- VNI_HASH_BITS
 
- VNI_HASH_SIZE
 
- VNMB_REG
 
- VNMC_BPS
 
- VNMC_DPINE
 
- VNMC_FOC
 
- VNMC_IM_EVEN
 
- VNMC_IM_FULL
 
- VNMC_IM_ODD
 
- VNMC_IM_ODD_EVEN
 
- VNMC_INF_RGB888
 
- VNMC_INF_YUV10_BT601
 
- VNMC_INF_YUV10_BT656
 
- VNMC_INF_YUV16
 
- VNMC_INF_YUV8_BT601
 
- VNMC_INF_YUV8_BT656
 
- VNMC_ME
 
- VNMC_REG
 
- VNMC_SCLE
 
- VNMC_VUP
 
- VNMC_YCAL
 
- VNMS_AV
 
- VNMS_CA
 
- VNMS_FBS_MASK
 
- VNMS_FBS_SHIFT
 
- VNMS_FS
 
- VNMS_REG
 
- VNMTC_REG
 
- VNODES_COUNT
 
- VNODE_END_NID
 
- VNODE_START_NID
 
- VNOSERVICE
 
- VNOVNODE
 
- VNOVOL
 
- VNSI_REG
 
- VNSLPOC_REG
 
- VNSLPRC_REG
 
- VNSPPOC_REG
 
- VNSPPRC_REG
 
- VNSvInPortB
 
- VNSvInPortD
 
- VNSvInPortW
 
- VNSvOutPortB
 
- VNSvOutPortD
 
- VNSvOutPortW
 
- VNT_B_RATES
 
- VNT_KEY_ALLGROUP
 
- VNT_KEY_DEFAULTKEY
 
- VNT_KEY_GROUP
 
- VNT_KEY_GROUP_ADDRESS
 
- VNT_KEY_ONFLY
 
- VNT_KEY_ONFLY_ALL
 
- VNT_KEY_PAIRWISE
 
- VNT_REG_BLOCK_SIZE
 
- VNT_RF_MAX_POWER
 
- VNT_RF_REG_LEN
 
- VNT_USB_PRODUCT_ID
 
- VNT_USB_VENDOR_ID
 
- VNUVAOF_REG
 
- VNXS_REG
 
- VNYS_REG
 
- VN_0
 
- VN_1
 
- VN_2
 
- VN_3
 
- VN_PT_PHY_ETH_MAC
 
- VN_PT_PHY_PF_PORT
 
- VN_PT_PHY_SHIFT
 
- VN_PT_PHY_UNKNOWN
 
- VOAdmTime
 
- VOFFLINE
 
- VOICE
 
- VOICEFX
 
- VOICEFX_MAX_PARAM_COUNT
 
- VOICE_CAPTURE
 
- VOICE_DEC
 
- VOICE_FOCUS
 
- VOICE_INC
 
- VOICE_IN_USE
 
- VOICE_SSO_TIMING
 
- VOICE_SYNC_TIMING
 
- VOID
 
- VOID_FRAME_OFF
 
- VOID_PTE
 
- VOID_V
 
- VOL
 
- VOLAISB
 
- VOLATILE
 
- VOLBISA
 
- VOLLEFT
 
- VOLRIGHT
 
- VOLSENSE
 
- VOLTAGE
 
- VOLTAGE_CHG_EN
 
- VOLTAGE_CHG_EN_MASK
 
- VOLTAGE_CHG_EN_SHIFT
 
- VOLTAGE_CONTROLLED_BY_GPIO
 
- VOLTAGE_CONTROLLED_BY_HW
 
- VOLTAGE_CONTROLLED_BY_I2C_MASK
 
- VOLTAGE_CONTROL_ID_AD527x
 
- VOLTAGE_CONTROL_ID_CHL8214
 
- VOLTAGE_CONTROL_ID_CHL822x
 
- VOLTAGE_CONTROL_ID_CHLIR3564SVI2
 
- VOLTAGE_CONTROL_ID_DAC
 
- VOLTAGE_CONTROL_ID_DS4402
 
- VOLTAGE_CONTROL_ID_GENERIC_I2C
 
- VOLTAGE_CONTROL_ID_IR35xx
 
- VOLTAGE_CONTROL_ID_LM64
 
- VOLTAGE_CONTROL_ID_LTC2635
 
- VOLTAGE_CONTROL_ID_NCP4208
 
- VOLTAGE_CONTROL_ID_NCP81022
 
- VOLTAGE_CONTROL_ID_RT9403
 
- VOLTAGE_CONTROL_ID_SCORPIO
 
- VOLTAGE_CONTROL_ID_ST6788A
 
- VOLTAGE_CONTROL_ID_UP1637
 
- VOLTAGE_CONTROL_ID_UP1801
 
- VOLTAGE_CONTROL_ID_UP6266
 
- VOLTAGE_CONTROL_ID_VT116xM
 
- VOLTAGE_CONTROL_ID_VT1556M
 
- VOLTAGE_CONTROL_ID_VT1586M
 
- VOLTAGE_DATA_ONE_BYTE
 
- VOLTAGE_DATA_TWO_BYTE
 
- VOLTAGE_DELAY_SEL
 
- VOLTAGE_DIVIDER
 
- VOLTAGE_DROP_SYNC
 
- VOLTAGE_FROM_ADC
 
- VOLTAGE_GPIO
 
- VOLTAGE_INFO_0_85V
 
- VOLTAGE_INFO_0_95V
 
- VOLTAGE_INFO_1_05V
 
- VOLTAGE_INFO_MASK
 
- VOLTAGE_INFO_SHIFT
 
- VOLTAGE_LEVEL_0
 
- VOLTAGE_LEVEL_1
 
- VOLTAGE_LEVEL_2
 
- VOLTAGE_LEVEL_3
 
- VOLTAGE_LUT_ENTRY
 
- VOLTAGE_LUT_ENTRY_V2
 
- VOLTAGE_MAX_REG
 
- VOLTAGE_MIN_REG
 
- VOLTAGE_MODE_AVFS
 
- VOLTAGE_MODE_AVFS_INTERPOLATE
 
- VOLTAGE_MODE_AVFS_SS
 
- VOLTAGE_MODE_AVFS_WORST_CASE
 
- VOLTAGE_MODE_COUNT
 
- VOLTAGE_MODE_SS
 
- VOLTAGE_MODE_STATIC
 
- VOLTAGE_MODE_e
 
- VOLTAGE_NONE
 
- VOLTAGE_OBJ_EVV
 
- VOLTAGE_OBJ_GPIO_LUT
 
- VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT
 
- VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT
 
- VOLTAGE_OBJ_MERGED_POWER
 
- VOLTAGE_OBJ_PHASE_LUT
 
- VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT
 
- VOLTAGE_OBJ_SVID2
 
- VOLTAGE_OBJ_VR_I2C_INIT_SEQ
 
- VOLTAGE_REG
 
- VOLTAGE_SCALE
 
- VOLTAGE_SUPPLY_RANGE
 
- VOLTAGE_SW
 
- VOLTAGE_SWING_LEVEL0
 
- VOLTAGE_SWING_LEVEL1
 
- VOLTAGE_SWING_LEVEL2
 
- VOLTAGE_SWING_LEVEL3
 
- VOLTAGE_SWING_MAX_LEVEL
 
- VOLTAGE_SWITCH
 
- VOLTAGE_TYPE_GENERIC_I2C_1
 
- VOLTAGE_TYPE_GENERIC_I2C_10
 
- VOLTAGE_TYPE_GENERIC_I2C_2
 
- VOLTAGE_TYPE_GENERIC_I2C_3
 
- VOLTAGE_TYPE_GENERIC_I2C_4
 
- VOLTAGE_TYPE_GENERIC_I2C_5
 
- VOLTAGE_TYPE_GENERIC_I2C_6
 
- VOLTAGE_TYPE_GENERIC_I2C_7
 
- VOLTAGE_TYPE_GENERIC_I2C_8
 
- VOLTAGE_TYPE_GENERIC_I2C_9
 
- VOLTAGE_TYPE_LEDDPM
 
- VOLTAGE_TYPE_MVDDC
 
- VOLTAGE_TYPE_MVDDQ
 
- VOLTAGE_TYPE_MVPP
 
- VOLTAGE_TYPE_PCC
 
- VOLTAGE_TYPE_PCC_MVDD
 
- VOLTAGE_TYPE_PCIE_VDDC
 
- VOLTAGE_TYPE_PCIE_VDDR
 
- VOLTAGE_TYPE_VDDC
 
- VOLTAGE_TYPE_VDDCI
 
- VOLTAGE_TYPE_VDDGFX
 
- VOLTAGE_V25
 
- VOLTAGE_VDDC
 
- VOLTAGE_VID_OFFSET_SCALE1
 
- VOLTAGE_VID_OFFSET_SCALE2
 
- VOLTA_A
 
- VOLTA_CHANNEL_GPFIFO_A
 
- VOLTA_COMPUTE_A
 
- VOLTA_DMA_COPY_A
 
- VOLTA_FAULT_BUFFER_A
 
- VOLTA_USERMODE_A
 
- VOLT_CTRL_AMPCTRL_MASK
 
- VOLT_CTRL_AMPCTRL_SHIFT
 
- VOLT_CTRL_CABLE1TH_MASK
 
- VOLT_CTRL_CABLE1TH_SHIFT
 
- VOLT_CTRL_DACAMP10_MASK
 
- VOLT_CTRL_DACAMP10_SHIFT
 
- VOLT_CTRL_SWLOWEST
 
- VOLT_CTRL_SW_BYPASS
 
- VOLT_DATA_DEFINE
 
- VOLT_FROM_REG
 
- VOLT_MONITOR_MODE
 
- VOLT_PWRMGT_EN
 
- VOLT_SHIFT
 
- VOLT_TOL
 
- VOLT_TO_REG
 
- VOLUME
 
- VOLUME1
 
- VOLUME2
 
- VOLUME_ADD
 
- VOLUME_ADDIN
 
- VOLUME_AMI_TO_VOXWARE
 
- VOLUME_ATT_TO_VOXWARE
 
- VOLUME_CAPTURE
 
- VOLUME_CHKDSK_UNDERWAY
 
- VOLUME_CONTROL
 
- VOLUME_DB_TO_VOXWARE
 
- VOLUME_DELETE_USN_UNDERWAY
 
- VOLUME_DISABLED
 
- VOLUME_DISMOUNTED
 
- VOLUME_DOWN
 
- VOLUME_FLAGS
 
- VOLUME_FLAGS_MASK
 
- VOLUME_FWL
 
- VOLUME_IN
 
- VOLUME_INFORMATION
 
- VOLUME_INIT
 
- VOLUME_IS_DIRTY
 
- VOLUME_MODIFIED_BY_CHKDSK
 
- VOLUME_MONITOR
 
- VOLUME_MOUNTED
 
- VOLUME_MOUNTED_ON_NT4
 
- VOLUME_MOUNTED_QUOTAS
 
- VOLUME_MUST_MOUNT_RO_MASK
 
- VOLUME_NAME
 
- VOLUME_OUT
 
- VOLUME_OVERFLOW
 
- VOLUME_PLAYBACK
 
- VOLUME_RAMP_MAX_DVC
 
- VOLUME_RAMP_MAX_MIX
 
- VOLUME_RANGE_SHIFT
 
- VOLUME_REPAIR_OBJECT_ID
 
- VOLUME_RESIZE_LOG_FILE
 
- VOLUME_SET
 
- VOLUME_UNSPECIFIED
 
- VOLUME_UP
 
- VOLUME_UPGRADE_ON_MOUNT
 
- VOLUME_VOXWARE_TO_AMI
 
- VOLUME_VOXWARE_TO_ATT
 
- VOLUME_VOXWARE_TO_DB
 
- VOL_3V_CARD_DT
 
- VOL_3V_SKT
 
- VOL_5V_CARD_DT
 
- VOL_5V_SKT
 
- VOL_CLEAN
 
- VOL_DEC
 
- VOL_DIRTY
 
- VOL_FORTIETH_ROOT_OF_TEN
 
- VOL_HALF_DB_STEP
 
- VOL_IDX_ADC
 
- VOL_IDX_BASS
 
- VOL_IDX_LAST_MIX
 
- VOL_IDX_LAST_MONO
 
- VOL_IDX_PCM
 
- VOL_IDX_PCM2
 
- VOL_IDX_PCM_MONO
 
- VOL_IDX_TREBLE
 
- VOL_INC
 
- VOL_LABEL
 
- VOL_MAX
 
- VOL_METHOD_ADAGIO
 
- VOL_METHOD_LINEAR
 
- VOL_MIN
 
- VOL_MIXER_END
 
- VOL_MIXER_NUM
 
- VOL_MIXER_START
 
- VOL_PRESENT
 
- VOL_SCALE
 
- VOL_SHIFT
 
- VOL_STEP_mB
 
- VOL_TWENTIETH_ROOT_OF_TEN
 
- VOL_XV_CARD_DT
 
- VOL_YV_CARD_DT
 
- VOL_ZERO_DB
 
- VONLINE
 
- VOODOO3_MAX_PIXCLOCK
 
- VOODOO5_MAX_PIXCLOCK
 
- VOP_DEV_ANY_ID
 
- VOP_DEV_TRNSP
 
- VOP_FEATURE_INTERNAL_RGB
 
- VOP_FEATURE_OUTPUT_RGB10
 
- VOP_FMT_ARGB8888
 
- VOP_FMT_RGB565
 
- VOP_FMT_RGB888
 
- VOP_FMT_YUV420SP
 
- VOP_FMT_YUV422SP
 
- VOP_FMT_YUV444SP
 
- VOP_INTR_GET_TYPE
 
- VOP_INTR_SET_MASK
 
- VOP_INTR_SET_TYPE
 
- VOP_INT_DMA_BUF_SIZE
 
- VOP_MAJOR
 
- VOP_MAX_VRINGS
 
- VOP_MINOR
 
- VOP_PENDING_FB_UNREF
 
- VOP_REG
 
- VOP_REG_MASK_SYNC
 
- VOP_REG_SET
 
- VOP_REG_SYNC
 
- VOP_SCL_SET
 
- VOP_SCL_SET_EXT
 
- VOP_USE_DMA
 
- VOP_VERSION
 
- VOP_WIN_GET
 
- VOP_WIN_GET_YRGBADDR
 
- VOP_WIN_HAS_REG
 
- VOP_WIN_SET
 
- VOP_WIN_TO_INDEX
 
- VOP_WIN_YUV2YUV_COEFFICIENT_SET
 
- VOP_WIN_YUV2YUV_SET
 
- VOQDA
 
- VORTEX_ADBDMA_BUFBASE
 
- VORTEX_ADBDMA_BUFCFG0
 
- VORTEX_ADBDMA_BUFCFG1
 
- VORTEX_ADBDMA_CTRL
 
- VORTEX_ADBDMA_START
 
- VORTEX_ADBDMA_STAT
 
- VORTEX_ADBDMA_STATUS
 
- VORTEX_ADB_CHNBASE
 
- VORTEX_ADB_CHNBASE_COUNT
 
- VORTEX_ADB_RTBASE
 
- VORTEX_ADB_RTBASE_COUNT
 
- VORTEX_ADB_SR
 
- VORTEX_BAND_COEFF_SIZE
 
- VORTEX_BUS_MASTER
 
- VORTEX_CODEC2_CTRL
 
- VORTEX_CODEC_ADDMASK
 
- VORTEX_CODEC_ADDSHIFT
 
- VORTEX_CODEC_CHN
 
- VORTEX_CODEC_CTRL
 
- VORTEX_CODEC_DATMASK
 
- VORTEX_CODEC_DATSHIFT
 
- VORTEX_CODEC_EN
 
- VORTEX_CODEC_ID_SHIFT
 
- VORTEX_CODEC_IO
 
- VORTEX_CODEC_SPORTCTRL
 
- VORTEX_CODEC_WRITE
 
- VORTEX_CTRL
 
- VORTEX_CTRL2
 
- VORTEX_DMA_BUFFER
 
- VORTEX_EISA
 
- VORTEX_ENGINE_CTRL
 
- VORTEX_EQ_BASE
 
- VORTEX_EQ_CTRL
 
- VORTEX_EQ_DEST
 
- VORTEX_EQ_SOURCE
 
- VORTEX_FIFO_ADBCTRL
 
- VORTEX_FIFO_ADBDATA
 
- VORTEX_FIFO_GIRT
 
- VORTEX_FIFO_WTCTRL
 
- VORTEX_FIFO_WTDATA
 
- VORTEX_GAME_AXIS
 
- VORTEX_GAME_DWAIT
 
- VORTEX_GAME_LEGACY
 
- VORTEX_IRQ_CTRL
 
- VORTEX_IRQ_SOURCE
 
- VORTEX_IRQ_STAT
 
- VORTEX_IS_QUAD
 
- VORTEX_MIDI_CMD
 
- VORTEX_MIDI_DATA
 
- VORTEX_MIXER_CHNBASE
 
- VORTEX_MIXER_CLIP
 
- VORTEX_MIXER_RTBASE
 
- VORTEX_MIXER_SR
 
- VORTEX_MIX_ENIN
 
- VORTEX_MIX_INVOL_A
 
- VORTEX_MIX_INVOL_B
 
- VORTEX_MIX_SMP
 
- VORTEX_MIX_VOL_A
 
- VORTEX_MIX_VOL_B
 
- VORTEX_MODEM_CTRL
 
- VORTEX_MPU401_LEGACY
 
- VORTEX_NUM_STATS
 
- VORTEX_PCI
 
- VORTEX_PCM_A3D
 
- VORTEX_PCM_ADB
 
- VORTEX_PCM_I2S
 
- VORTEX_PCM_LAST
 
- VORTEX_PCM_SPDIF
 
- VORTEX_PCM_TYPE
 
- VORTEX_PCM_WT
 
- VORTEX_PM_OPS
 
- VORTEX_RESOURCE_A3D
 
- VORTEX_RESOURCE_DMA
 
- VORTEX_RESOURCE_LAST
 
- VORTEX_RESOURCE_MIXIN
 
- VORTEX_RESOURCE_MIXOUT
 
- VORTEX_RESOURCE_SRC
 
- VORTEX_SMP_TIME
 
- VORTEX_SMP_TIMER
 
- VORTEX_SPDIF_CFG0
 
- VORTEX_SPDIF_CFG1
 
- VORTEX_SPDIF_FLAGS
 
- VORTEX_SPDIF_SMPRATE
 
- VORTEX_SRCBLOCK_SR
 
- VORTEX_SRC_CHNBASE
 
- VORTEX_SRC_CONVRATIO
 
- VORTEX_SRC_DATA
 
- VORTEX_SRC_DATA0
 
- VORTEX_SRC_DRIFT0
 
- VORTEX_SRC_DRIFT1
 
- VORTEX_SRC_DRIFT2
 
- VORTEX_SRC_RTBASE
 
- VORTEX_SRC_SOURCE
 
- VORTEX_SRC_SOURCESIZE
 
- VORTEX_SRC_U0
 
- VORTEX_SRC_U1
 
- VORTEX_SRC_U2
 
- VORTEX_STAT
 
- VORTEX_TOTAL_SIZE
 
- VORTEX_WTDMA_BUFBASE
 
- VORTEX_WTDMA_BUFCFG0
 
- VORTEX_WTDMA_BUFCFG1
 
- VORTEX_WTDMA_CTRL
 
- VORTEX_WTDMA_START
 
- VORTEX_WTDMA_STAT
 
- VORTEX_WT_BASE
 
- VOTABLE
 
- VOTID6_CTRL
 
- VOTID7_CTRL
 
- VOU
 
- VOUAD1R
 
- VOUAD2R
 
- VOUAIR
 
- VOUBCR
 
- VOUCR
 
- VOUDFR
 
- VOUDPR
 
- VOUDSR
 
- VOUER
 
- VOUHIR
 
- VOUIR
 
- VOUISR
 
- VOUMSR
 
- VOURCR
 
- VOURPR
 
- VOUSRR
 
- VOUSTR
 
- VOUSWR
 
- VOUTC
 
- VOUTSIZE
 
- VOUT_LO_INT
 
- VOUT_NAME
 
- VOUT_ROT_NONE
 
- VOUT_ROT_VRFB
 
- VOUT_SET2
 
- VOUT_SET3
 
- VOUVCR
 
- VOUVPR
 
- VOU_ACLK
 
- VOU_AUX_WCLK
 
- VOU_CHN_AUX
 
- VOU_CHN_MAIN
 
- VOU_CLK_EN
 
- VOU_CLK_GL0_SEL
 
- VOU_CLK_GL1_SEL
 
- VOU_CLK_REQEN
 
- VOU_CLK_SEL
 
- VOU_CLK_VL0_SEL
 
- VOU_CLK_VL1_SEL
 
- VOU_CLK_VL2_SEL
 
- VOU_CRTC_MASK
 
- VOU_DIV_1
 
- VOU_DIV_2
 
- VOU_DIV_4
 
- VOU_DIV_8
 
- VOU_DIV_HDMI
 
- VOU_DIV_HDMI_PNX
 
- VOU_DIV_INF
 
- VOU_DIV_LAYER
 
- VOU_DIV_PARA
 
- VOU_DIV_PIC
 
- VOU_DIV_TVENC
 
- VOU_DIV_VGA
 
- VOU_HDMI
 
- VOU_HDMI_AUD_DSD
 
- VOU_HDMI_AUD_HBR
 
- VOU_HDMI_AUD_I2S
 
- VOU_HDMI_AUD_MASK
 
- VOU_HDMI_AUD_PARALLEL
 
- VOU_HDMI_AUD_SPDIF
 
- VOU_INF_CH_SEL
 
- VOU_INF_DATA_SEL
 
- VOU_INF_EN
 
- VOU_INF_HDMI_CTRL
 
- VOU_LOCAL_CLKEN
 
- VOU_LOCAL_CLKSEL
 
- VOU_LOCAL_DIV2_SET
 
- VOU_LVDS
 
- VOU_MAIN_WCLK
 
- VOU_MAX_IMAGE_WIDTH
 
- VOU_MIN_IMAGE_HEIGHT
 
- VOU_MIN_IMAGE_WIDTH
 
- VOU_MIPI_DSI
 
- VOU_PPU_WCLK
 
- VOU_RGB_101010
 
- VOU_RGB_666
 
- VOU_RGB_888
 
- VOU_RGB_LCD
 
- VOU_SOFT_RST
 
- VOU_TV_ENC
 
- VOU_VGA
 
- VOU_YUV444
 
- VOVERQUOTA
 
- VOVP_10000
 
- VOVP_10500
 
- VOVP_6000
 
- VOVP_6500
 
- VOVP_7000
 
- VOVP_8000
 
- VOVP_9000
 
- VOVP_9500
 
- VOVRCLK
 
- VOVRCLK_EN
 
- VOW_1P6M_800K_SEL_MASK
 
- VOW_1P6M_800K_SEL_MASK_SFT
 
- VOW_1P6M_800K_SEL_SFT
 
- VOW_32K_MODE_MASK
 
- VOW_32K_MODE_MASK_SFT
 
- VOW_32K_MODE_SFT
 
- VOW_ADC_CLK_INV_MASK
 
- VOW_ADC_CLK_INV_MASK_SFT
 
- VOW_ADC_CLK_INV_SFT
 
- VOW_ADC_TESTCK_SEL_MASK
 
- VOW_ADC_TESTCK_SEL_MASK_SFT
 
- VOW_ADC_TESTCK_SEL_SFT
 
- VOW_ADC_TESTCK_SRC_SEL_MASK
 
- VOW_ADC_TESTCK_SRC_SEL_MASK_SFT
 
- VOW_ADC_TESTCK_SRC_SEL_SFT
 
- VOW_A_MASK
 
- VOW_A_MASK_SFT
 
- VOW_A_SFT
 
- VOW_B_MASK
 
- VOW_B_MASK_SFT
 
- VOW_B_SFT
 
- VOW_CIC_MODE_SEL_MASK
 
- VOW_CIC_MODE_SEL_MASK_SFT
 
- VOW_CIC_MODE_SEL_SFT
 
- VOW_CK_DIV_RST_MASK
 
- VOW_CK_DIV_RST_MASK_SFT
 
- VOW_CK_DIV_RST_SFT
 
- VOW_CLK_SEL_MASK
 
- VOW_CLK_SEL_MASK_SFT
 
- VOW_CLK_SEL_SFT
 
- VOW_DIGMIC_CK_PHASE_SEL_MASK
 
- VOW_DIGMIC_CK_PHASE_SEL_MASK_SFT
 
- VOW_DIGMIC_CK_PHASE_SEL_SFT
 
- VOW_DIGMIC_ON_MASK
 
- VOW_DIGMIC_ON_MASK_SFT
 
- VOW_DIGMIC_ON_SFT
 
- VOW_DMICCLK_PDN_MASK
 
- VOW_DMICCLK_PDN_MASK_SFT
 
- VOW_DMICCLK_PDN_SFT
 
- VOW_DOWNCNT_MASK
 
- VOW_DOWNCNT_MASK_SFT
 
- VOW_DOWNCNT_SFT
 
- VOW_HPF_DC_TEST_MASK
 
- VOW_HPF_DC_TEST_MASK_SFT
 
- VOW_HPF_DC_TEST_SFT
 
- VOW_INTR_CLR_MASK
 
- VOW_INTR_CLR_MASK_SFT
 
- VOW_INTR_CLR_SFT
 
- VOW_INTR_FLAG_MASK
 
- VOW_INTR_FLAG_MASK_SFT
 
- VOW_INTR_FLAG_SFT
 
- VOW_INTR_SOURCE_SEL_MASK
 
- VOW_INTR_SOURCE_SEL_MASK_SFT
 
- VOW_INTR_SOURCE_SEL_SFT
 
- VOW_INTR_SW_MODE_MASK
 
- VOW_INTR_SW_MODE_MASK_SFT
 
- VOW_INTR_SW_MODE_SFT
 
- VOW_INTR_SW_VAL_MASK
 
- VOW_INTR_SW_VAL_MASK_SFT
 
- VOW_INTR_SW_VAL_SFT
 
- VOW_IRQ_LATCH_SNR_EN_MASK
 
- VOW_IRQ_LATCH_SNR_EN_MASK_SFT
 
- VOW_IRQ_LATCH_SNR_EN_SFT
 
- VOW_LOOP_BACK_MODE_MASK
 
- VOW_LOOP_BACK_MODE_MASK_SFT
 
- VOW_LOOP_BACK_MODE_SFT
 
- VOW_N_H_MASK
 
- VOW_N_H_MASK_SFT
 
- VOW_N_H_SFT
 
- VOW_N_L_MASK
 
- VOW_N_L_MASK_SFT
 
- VOW_N_L_SFT
 
- VOW_ON_MASK
 
- VOW_ON_MASK_SFT
 
- VOW_ON_PERIODIC_INVERSE_MASK
 
- VOW_ON_PERIODIC_INVERSE_MASK_SFT
 
- VOW_ON_PERIODIC_INVERSE_SFT
 
- VOW_ON_PERIODIC_MODE_MASK
 
- VOW_ON_PERIODIC_MODE_MASK_SFT
 
- VOW_ON_PERIODIC_MODE_SFT
 
- VOW_ON_PERIODIC_OFF_CYCLE_MASK
 
- VOW_ON_PERIODIC_OFF_CYCLE_MASK_SFT
 
- VOW_ON_PERIODIC_OFF_CYCLE_SFT
 
- VOW_ON_PERIODIC_ON_CYCLE_MASK
 
- VOW_ON_PERIODIC_ON_CYCLE_MASK_SFT
 
- VOW_ON_PERIODIC_ON_CYCLE_SFT
 
- VOW_ON_SFT
 
- VOW_PERIODIC_COUNT_MON_MASK
 
- VOW_PERIODIC_COUNT_MON_MASK_SFT
 
- VOW_PERIODIC_COUNT_MON_SFT
 
- VOW_PERIODIC_MON_MASK
 
- VOW_PERIODIC_MON_MASK_SFT
 
- VOW_PERIODIC_MON_SFT
 
- VOW_POSDIVCLK_PDN_MASK
 
- VOW_POSDIVCLK_PDN_MASK_SFT
 
- VOW_POSDIVCLK_PDN_SFT
 
- VOW_SDM_3_LEVEL_MASK
 
- VOW_SDM_3_LEVEL_MASK_SFT
 
- VOW_SDM_3_LEVEL_SFT
 
- VOW_SNRDET_PERIODIC_CFG_MASK
 
- VOW_SNRDET_PERIODIC_CFG_MASK_SFT
 
- VOW_SNRDET_PERIODIC_CFG_SFT
 
- VOW_SN_INI_CFG_EN_MASK
 
- VOW_SN_INI_CFG_EN_MASK_SFT
 
- VOW_SN_INI_CFG_EN_SFT
 
- VOW_SN_INI_CFG_VAL_MASK
 
- VOW_SN_INI_CFG_VAL_MASK_SFT
 
- VOW_SN_INI_CFG_VAL_SFT
 
- VOW_S_H_MASK
 
- VOW_S_H_MASK_SFT
 
- VOW_S_H_SFT
 
- VOW_S_L_MASK
 
- VOW_S_L_MASK_SFT
 
- VOW_S_L_SFT
 
- VOW_TGEN_EN_MASK
 
- VOW_TGEN_EN_MASK_SFT
 
- VOW_TGEN_EN_SFT
 
- VOW_TGEN_FREQ_DIV_MASK
 
- VOW_TGEN_FREQ_DIV_MASK_SFT
 
- VOW_TGEN_FREQ_DIV_SFT
 
- VOW_TGEN_MUTE_SW_MASK
 
- VOW_TGEN_MUTE_SW_MASK_SFT
 
- VOW_TGEN_MUTE_SW_SFT
 
- VOW_TXIF_MONO_MASK
 
- VOW_TXIF_MONO_MASK_SFT
 
- VOW_TXIF_MONO_SFT
 
- VOW_TXIF_SCK_DIV_MASK
 
- VOW_TXIF_SCK_DIV_MASK_SFT
 
- VOW_TXIF_SCK_DIV_SFT
 
- VOW_TXIF_SCK_INV_MASK
 
- VOW_TXIF_SCK_INV_MASK_SFT
 
- VOW_TXIF_SCK_INV_SFT
 
- VO_ADMTIME
 
- VO_ADMTM
 
- VO_INIT_SIZE
 
- VO_NTSC
 
- VO_PAL
 
- VO_PRIORITY
 
- VO_Q
 
- VO_QID_01
 
- VO_QID_02
 
- VO_QUEUE
 
- VO_QUEUE_INX
 
- VO_VGA
 
- VP
 
- VP8_BSASET
 
- VP8_BSDSET
 
- VP8_DEC_TABLE_OFFSET
 
- VP8_DEC_TABLE_PROC_LOOP
 
- VP8_DEC_TABLE_RW_UNIT
 
- VP8_DEC_TABLE_SZ
 
- VP8_DEC_TABLE_UNIT
 
- VP8_DPB_SIZE
 
- VP8_FRAME_IS_KEY_FRAME
 
- VP8_HW_SEGMENT_DATA_SZ
 
- VP8_HW_SEGMENT_UINT
 
- VP8_HW_VLD_ADDR
 
- VP8_HW_VLD_VALUE
 
- VP8_MAX_FRM_BUF_NODE_NUM
 
- VP8_MAX_FRM_BUF_NUM
 
- VP8_MB_DIM
 
- VP8_MB_HEIGHT
 
- VP8_MB_WIDTH
 
- VP8_RW_CKEN_SET
 
- VP8_RW_DCM_CON
 
- VP8_RW_MISC_DCM_CON
 
- VP8_RW_MISC_FUNC_CON
 
- VP8_RW_MISC_SPEC_CON
 
- VP8_RW_MISC_SRST
 
- VP8_RW_MISC_SYS_SEL
 
- VP8_RW_VP8_CTRL
 
- VP8_SEGID_DRAM_ADDR
 
- VP8_WORKING_BUF_SZ
 
- VP8_WO_VLD_SRST
 
- VP9_MAX_FRM_BUF_NODE_NUM
 
- VP9_MAX_FRM_BUF_NUM
 
- VP9_SEG_ID_SZ
 
- VP9_SUPER_FRAME_BS_SZ
 
- VPBE_DEFAULT_MODE
 
- VPBE_DEFAULT_NUM_BUFS
 
- VPBE_DEFAULT_OUTPUT
 
- VPBE_DISPLAY_BUILD
 
- VPBE_DISPLAY_DEVICE_0
 
- VPBE_DISPLAY_DEVICE_1
 
- VPBE_DISPLAY_DRIVER
 
- VPBE_DISPLAY_DRV_NAME
 
- VPBE_DISPLAY_H
 
- VPBE_DISPLAY_H_EXP_RATIO_D
 
- VPBE_DISPLAY_H_EXP_RATIO_N
 
- VPBE_DISPLAY_MAJOR_RELEASE
 
- VPBE_DISPLAY_MAX_DEVICES
 
- VPBE_DISPLAY_MINOR_RELEASE
 
- VPBE_DISPLAY_VALID_FIELD
 
- VPBE_DISPLAY_VERSION_CODE
 
- VPBE_DISPLAY_V_EXP_RATIO_D
 
- VPBE_DISPLAY_V_EXP_RATIO_N
 
- VPBE_DISPLAY_ZOOM_2X
 
- VPBE_DISPLAY_ZOOM_4X
 
- VPBE_ENC_DV_TIMINGS
 
- VPBE_ENC_STD
 
- VPBE_ENC_TIMINGS_INVALID
 
- VPBE_PCR
 
- VPBE_PCR_CLK_OFF
 
- VPBE_PCR_VENC_DIV
 
- VPBE_PID
 
- VPBE_REG_BASE
 
- VPBE_VERSION_1
 
- VPBE_VERSION_2
 
- VPBE_VERSION_3
 
- VPCCMD_R_3G
 
- VPCCMD_R_BL
 
- VPCCMD_R_BL_MAX
 
- VPCCMD_R_BL_POWER
 
- VPCCMD_R_BT
 
- VPCCMD_R_CAMERA
 
- VPCCMD_R_FAN
 
- VPCCMD_R_NOVO
 
- VPCCMD_R_ODD
 
- VPCCMD_R_RF
 
- VPCCMD_R_SPECIAL_BUTTONS
 
- VPCCMD_R_TOUCHPAD
 
- VPCCMD_R_VPC1
 
- VPCCMD_R_VPC2
 
- VPCCMD_R_WIFI
 
- VPCCMD_W_3G
 
- VPCCMD_W_BL
 
- VPCCMD_W_BL_POWER
 
- VPCCMD_W_BT
 
- VPCCMD_W_CAMERA
 
- VPCCMD_W_FAN
 
- VPCCMD_W_RF
 
- VPCCMD_W_TOUCHPAD
 
- VPCCMD_W_WIFI
 
- VPCERR_BAD_WWN
 
- VPCERR_NO_FABRIC_SUPP
 
- VPCERR_UNSUPPORTED
 
- VPCI2VC
 
- VPCTRL
 
- VPCTRL0
 
- VPC_BUSY_CYCLES
 
- VPC_INTERVAL_CNTL__VPC_PERIOD_MASK
 
- VPC_INTERVAL_CNTL__VPC_PERIOD__SHIFT
 
- VPC_PERF_ACTIVE_CYCLES
 
- VPC_PERF_COMPONENTS_FROM_SP
 
- VPC_PERF_SP_LM_COMPONENTS
 
- VPC_PERF_SP_LM_PRIMITIVES
 
- VPC_PERF_STALL_CYCLES_LM
 
- VPC_PERF_STALL_CYCLES_RAS
 
- VPC_SP0_LM_BYTES
 
- VPC_SP1_LM_BYTES
 
- VPC_SP2_LM_BYTES
 
- VPC_SP3_LM_BYTES
 
- VPC_SP_LM_COMPONENTS
 
- VPC_STALL_CYCLES_LM
 
- VPC_STALL_CYCLES_UCHE
 
- VPC_STARVE_CYCLES_RAS
 
- VPC_STARVE_CYCLES_SP
 
- VPC_STREAMOUT_CYCLES
 
- VPC_UCHE_TRANSACTIONS
 
- VPC_WORKING_CYCLES
 
- VPD
 
- VPDBOOTHOST
 
- VPDMASTERBIOS
 
- VPDMA_ADB_SIZE_ALIGN
 
- VPDMA_BG_RGB
 
- VPDMA_BG_YUV
 
- VPDMA_CFD_CTD_DESC_SIZE
 
- VPDMA_CSTAT_FRAME_START_MASK
 
- VPDMA_CSTAT_FRAME_START_SHIFT
 
- VPDMA_CSTAT_LINE_MODE_MASK
 
- VPDMA_CSTAT_LINE_MODE_SHIFT
 
- VPDMA_DATA_EVEN_LINE_SKIP
 
- VPDMA_DATA_FMT_ABGR16
 
- VPDMA_DATA_FMT_ABGR16_1555
 
- VPDMA_DATA_FMT_ABGR24
 
- VPDMA_DATA_FMT_ABGR32
 
- VPDMA_DATA_FMT_ARGB16
 
- VPDMA_DATA_FMT_ARGB16_1555
 
- VPDMA_DATA_FMT_ARGB24
 
- VPDMA_DATA_FMT_ARGB32
 
- VPDMA_DATA_FMT_BGR24
 
- VPDMA_DATA_FMT_BGR565
 
- VPDMA_DATA_FMT_BGRA16
 
- VPDMA_DATA_FMT_BGRA16_5551
 
- VPDMA_DATA_FMT_BGRA24
 
- VPDMA_DATA_FMT_BGRA32
 
- VPDMA_DATA_FMT_C420
 
- VPDMA_DATA_FMT_C422
 
- VPDMA_DATA_FMT_C444
 
- VPDMA_DATA_FMT_CBY422
 
- VPDMA_DATA_FMT_CRY422
 
- VPDMA_DATA_FMT_MV
 
- VPDMA_DATA_FMT_RAW16
 
- VPDMA_DATA_FMT_RAW8
 
- VPDMA_DATA_FMT_RGB24
 
- VPDMA_DATA_FMT_RGB565
 
- VPDMA_DATA_FMT_RGBA16
 
- VPDMA_DATA_FMT_RGBA16_5551
 
- VPDMA_DATA_FMT_RGBA24
 
- VPDMA_DATA_FMT_RGBA32
 
- VPDMA_DATA_FMT_TYPE_MISC
 
- VPDMA_DATA_FMT_TYPE_RGB
 
- VPDMA_DATA_FMT_TYPE_YUV
 
- VPDMA_DATA_FMT_Y420
 
- VPDMA_DATA_FMT_Y422
 
- VPDMA_DATA_FMT_Y444
 
- VPDMA_DATA_FMT_YC444
 
- VPDMA_DATA_FMT_YCB422
 
- VPDMA_DATA_FMT_YCR422
 
- VPDMA_DATA_FRAME_1D
 
- VPDMA_DATA_MODE_TILED
 
- VPDMA_DATA_ODD_LINE_SKIP
 
- VPDMA_DEI_CHROMA1_CSTAT
 
- VPDMA_DEI_CHROMA2_CSTAT
 
- VPDMA_DEI_CHROMA3_CSTAT
 
- VPDMA_DEI_LUMA1_CSTAT
 
- VPDMA_DEI_LUMA2_CSTAT
 
- VPDMA_DEI_LUMA3_CSTAT
 
- VPDMA_DEI_MV_IN_CSTAT
 
- VPDMA_DEI_MV_OUT_CSTAT
 
- VPDMA_DESC_ALIGN
 
- VPDMA_DTD_DESC_SIZE
 
- VPDMA_FIRMWARE
 
- VPDMA_FSEVENT_CHANNEL_ACTIVE
 
- VPDMA_FSEVENT_DVO2_FID
 
- VPDMA_FSEVENT_HDCOMP_FID
 
- VPDMA_FSEVENT_HDMI_FID
 
- VPDMA_FSEVENT_LM_FID0
 
- VPDMA_FSEVENT_LM_FID1
 
- VPDMA_FSEVENT_LM_FID2
 
- VPDMA_FSEVENT_SD_FID
 
- VPDMA_INTX_OFFSET
 
- VPDMA_INT_CHAN_MASK
 
- VPDMA_INT_CHAN_STAT
 
- VPDMA_INT_CLIENT0_MASK
 
- VPDMA_INT_CLIENT0_STAT
 
- VPDMA_INT_CLIENT1_MASK
 
- VPDMA_INT_CLIENT1_STAT
 
- VPDMA_INT_LIST0_MASK
 
- VPDMA_INT_LIST0_STAT
 
- VPDMA_LIST_ADDR
 
- VPDMA_LIST_ATTR
 
- VPDMA_LIST_NUM_MASK
 
- VPDMA_LIST_NUM_SHFT
 
- VPDMA_LIST_RDY_MASK
 
- VPDMA_LIST_RDY_SHFT
 
- VPDMA_LIST_SIZE_MASK
 
- VPDMA_LIST_STAT_SYNC
 
- VPDMA_LIST_STOP_SHFT
 
- VPDMA_LIST_TYPE_DOORBELL
 
- VPDMA_LIST_TYPE_MASK
 
- VPDMA_LIST_TYPE_NORMAL
 
- VPDMA_LIST_TYPE_SELF_MODIFYING
 
- VPDMA_LIST_TYPE_SHFT
 
- VPDMA_MAX_CHANNELS
 
- VPDMA_MAX_NUM_LIST
 
- VPDMA_MAX_SIZE1
 
- VPDMA_MAX_SIZE2
 
- VPDMA_MAX_SIZE3
 
- VPDMA_MAX_SIZE_HEIGHT_MASK
 
- VPDMA_MAX_SIZE_HEIGHT_SHFT
 
- VPDMA_MAX_SIZE_WIDTH_MASK
 
- VPDMA_MAX_SIZE_WIDTH_SHFT
 
- VPDMA_MAX_STRIDE
 
- VPDMA_PERFMON
 
- VPDMA_PID
 
- VPDMA_SETUP
 
- VPDMA_SET_MMR_ADB_HDR
 
- VPDMA_STRIDE_ALIGN
 
- VPDMA_VIP_LO_UV_CSTAT
 
- VPDMA_VIP_LO_Y_CSTAT
 
- VPDMA_VIP_UP_UV_CSTAT
 
- VPDMA_VIP_UP_Y_CSTAT
 
- VPDMA_VPI_CTL_CSTAT
 
- VPD_BASE
 
- VPD_BASE_OLD
 
- VPD_CAP_ID_MASK
 
- VPD_CAP_ID_SHIFT
 
- VPD_CAP_NEXT_PTR_MASK
 
- VPD_CAP_NEXT_PTR_SHIFT
 
- VPD_CAP_VPD_ADDR_MASK
 
- VPD_CAP_VPD_ADDR_SHIFT
 
- VPD_CAP_VPD_FLAG
 
- VPD_CBMEM_MAGIC
 
- VPD_ENTRY
 
- VPD_FAIL
 
- VPD_FLASH
 
- VPD_FOUND_MAC
 
- VPD_FOUND_PHY
 
- VPD_INFO_FLD_HDR_SIZE
 
- VPD_LEN
 
- VPD_MAGIC
 
- VPD_MASK
 
- VPD_MODEL_DESC
 
- VPD_MODEL_NAME
 
- VPD_OFFSET
 
- VPD_OK
 
- VPD_PAGE
 
- VPD_PORT
 
- VPD_PROGRAM_TYPE
 
- VPD_SIZE
 
- VPD_STRING_LEN
 
- VPD_TMP_BUF_SIZE
 
- VPD_TYPE_IMPLICIT_TERMINATOR
 
- VPD_TYPE_INFO
 
- VPD_TYPE_STRING
 
- VPD_TYPE_TERMINATOR
 
- VPEC
 
- VPECONF0_MVP
 
- VPECONF0_MVP_SHIFT
 
- VPECONF0_VPA
 
- VPECONF0_VPA_SHIFT
 
- VPECONF0_XTC
 
- VPECONF0_XTC_SHIFT
 
- VPECONF1_NCP1
 
- VPECONF1_NCP1_SHIFT
 
- VPECONF1_NCP2
 
- VPECONF1_NCP2_SHIFT
 
- VPECONF1_NCX
 
- VPECONF1_NCX_SHIFT
 
- VPECONTROL_EXCPT
 
- VPECONTROL_EXCPT_SHIFT
 
- VPECONTROL_GSI
 
- VPECONTROL_GSI_SHIFT
 
- VPECONTROL_TARGTC
 
- VPECONTROL_TE
 
- VPECONTROL_TE_SHIFT
 
- VPECONTROL_YSI
 
- VPECONTROL_YSI_SHIFT
 
- VPERM
 
- VPERMXOR
 
- VPE_AHB_CLK
 
- VPE_AHB_RESET
 
- VPE_ANCHOR_FID0_C0_MASK
 
- VPE_ANCHOR_FID0_C0_SHIFT
 
- VPE_ANCHOR_FID0_C1_MASK
 
- VPE_ANCHOR_FID0_C1_SHIFT
 
- VPE_ANCHOR_FID0_C2_MASK
 
- VPE_ANCHOR_FID0_C2_SHIFT
 
- VPE_ANCHOR_FID0_C3_MASK
 
- VPE_ANCHOR_FID0_C3_SHIFT
 
- VPE_ANCHOR_FID1_C0_MASK
 
- VPE_ANCHOR_FID1_C0_SHIFT
 
- VPE_ANCHOR_FID1_C1_MASK
 
- VPE_ANCHOR_FID1_C1_SHIFT
 
- VPE_ANCHOR_FID1_C2_MASK
 
- VPE_ANCHOR_FID1_C2_SHIFT
 
- VPE_ANCHOR_FID1_C3_MASK
 
- VPE_ANCHOR_FID1_C3_SHIFT
 
- VPE_AXI_CLK
 
- VPE_AXI_RESET
 
- VPE_CHAN_CHROMA1_IN
 
- VPE_CHAN_CHROMA2_IN
 
- VPE_CHAN_CHROMA3_IN
 
- VPE_CHAN_CHROMA_OUT
 
- VPE_CHAN_LUMA1_IN
 
- VPE_CHAN_LUMA2_IN
 
- VPE_CHAN_LUMA3_IN
 
- VPE_CHAN_LUMA_OUT
 
- VPE_CHAN_MV_IN
 
- VPE_CHAN_MV_OUT
 
- VPE_CHAN_NUM_CHROMA1_IN
 
- VPE_CHAN_NUM_CHROMA2_IN
 
- VPE_CHAN_NUM_CHROMA3_IN
 
- VPE_CHAN_NUM_CHROMA_OUT
 
- VPE_CHAN_NUM_LUMA1_IN
 
- VPE_CHAN_NUM_LUMA2_IN
 
- VPE_CHAN_NUM_LUMA3_IN
 
- VPE_CHAN_NUM_LUMA_OUT
 
- VPE_CHAN_NUM_MV_IN
 
- VPE_CHAN_NUM_MV_OUT
 
- VPE_CHAN_NUM_RGB_OUT
 
- VPE_CHAN_RGB_OUT
 
- VPE_CHROMA
 
- VPE_CLK
 
- VPE_CLK_ENABLE
 
- VPE_CLK_FORMAT_SELECT
 
- VPE_CLK_RANGE_MAP
 
- VPE_CLK_RESET
 
- VPE_COLOR_SEPARATE_422
 
- VPE_CSC_SRC_DEI_SCALER
 
- VPE_CSC_SRC_SELECT_MASK
 
- VPE_CSC_SRC_SELECT_SHIFT
 
- VPE_DATA_PATH_CLK_ENABLE
 
- VPE_DATA_PATH_CLK_RESET_MASK
 
- VPE_DATA_PATH_CLK_RESET_SHIFT
 
- VPE_DEF_BUFS_PER_JOB
 
- VPE_DEI_EDI_LUT_R0
 
- VPE_DEI_EDI_LUT_R1
 
- VPE_DEI_EDI_LUT_R2
 
- VPE_DEI_EDI_LUT_R3
 
- VPE_DEI_ERROR_INT
 
- VPE_DEI_FIELD_FLUSH
 
- VPE_DEI_FMD_CONTROL_R0
 
- VPE_DEI_FMD_CONTROL_R1
 
- VPE_DEI_FMD_INT
 
- VPE_DEI_FMD_STATUS_R0
 
- VPE_DEI_FMD_STATUS_R1
 
- VPE_DEI_FMD_STATUS_R2
 
- VPE_DEI_FMD_WINDOW_R0
 
- VPE_DEI_FMD_WINDOW_R1
 
- VPE_DEI_FRAME_SIZE
 
- VPE_DEI_HEIGHT_MASK
 
- VPE_DEI_HEIGHT_SHIFT
 
- VPE_DEI_INTERLACE_BYPASS
 
- VPE_DEI_PROGRESSIVE
 
- VPE_DEI_WIDTH_MASK
 
- VPE_DEI_WIDTH_SHIFT
 
- VPE_DESC_LIST_SIZE
 
- VPE_DS1_UV_ERROR_INT
 
- VPE_DS_BYPASS
 
- VPE_DS_SRC_DEI_SCALER
 
- VPE_DS_SRC_SELECT_MASK
 
- VPE_DS_SRC_SELECT_SHIFT
 
- VPE_EDI_CHROMA3D_COR_THR_MASK
 
- VPE_EDI_CHROMA3D_COR_THR_SHIFT
 
- VPE_EDI_CONFIG
 
- VPE_EDI_COR_SCALE_FACTOR_MASK
 
- VPE_EDI_COR_SCALE_FACTOR_SHIFT
 
- VPE_EDI_DIR_COR_LOWER_THR_MASK
 
- VPE_EDI_DIR_COR_LOWER_THR_SHIFT
 
- VPE_EDI_ENABLE_3D
 
- VPE_EDI_ENABLE_CHROMA_3D
 
- VPE_EDI_INP_MODE_MASK
 
- VPE_EDI_INP_MODE_SHIFT
 
- VPE_EDI_LUT0_MASK
 
- VPE_EDI_LUT0_SHIFT
 
- VPE_EDI_LUT10_MASK
 
- VPE_EDI_LUT10_SHIFT
 
- VPE_EDI_LUT11_MASK
 
- VPE_EDI_LUT11_SHIFT
 
- VPE_EDI_LUT1_MASK
 
- VPE_EDI_LUT1_SHIFT
 
- VPE_EDI_LUT2_MASK
 
- VPE_EDI_LUT2_SHIFT
 
- VPE_EDI_LUT3_MASK
 
- VPE_EDI_LUT3_SHIFT
 
- VPE_EDI_LUT4_MASK
 
- VPE_EDI_LUT4_SHIFT
 
- VPE_EDI_LUT5_MASK
 
- VPE_EDI_LUT5_SHIFT
 
- VPE_EDI_LUT6_MASK
 
- VPE_EDI_LUT6_SHIFT
 
- VPE_EDI_LUT7_MASK
 
- VPE_EDI_LUT7_SHIFT
 
- VPE_EDI_LUT8_MASK
 
- VPE_EDI_LUT8_SHIFT
 
- VPE_EDI_LUT9_MASK
 
- VPE_EDI_LUT9_SHIFT
 
- VPE_FMD_BED_ENABLE
 
- VPE_FMD_CAF_FIELD_THR_MASK
 
- VPE_FMD_CAF_FIELD_THR_SHIFT
 
- VPE_FMD_CAF_LINE_THR_MASK
 
- VPE_FMD_CAF_LINE_THR_SHIFT
 
- VPE_FMD_CAF_MASK
 
- VPE_FMD_CAF_SHIFT
 
- VPE_FMD_CAF_THR_MASK
 
- VPE_FMD_CAF_THR_SHIFT
 
- VPE_FMD_ENABLE
 
- VPE_FMD_FIELD_DIFF_MASK
 
- VPE_FMD_FIELD_DIFF_SHIFT
 
- VPE_FMD_FRAME_DIFF_MASK
 
- VPE_FMD_FRAME_DIFF_SHIFT
 
- VPE_FMD_JAM_DIR
 
- VPE_FMD_LOCK
 
- VPE_FMD_RESET
 
- VPE_FMD_WINDOW_ENABLE
 
- VPE_FMD_WINDOW_MAXX_MASK
 
- VPE_FMD_WINDOW_MAXX_SHIFT
 
- VPE_FMD_WINDOW_MAXY_MASK
 
- VPE_FMD_WINDOW_MAXY_SHIFT
 
- VPE_FMD_WINDOW_MINX_MASK
 
- VPE_FMD_WINDOW_MINX_SHIFT
 
- VPE_FMD_WINDOW_MINY_MASK
 
- VPE_FMD_WINDOW_MINY_SHIFT
 
- VPE_FMT_TYPE_CAPTURE
 
- VPE_FMT_TYPE_OUTPUT
 
- VPE_FORCE_IDLE_MODE
 
- VPE_FORCE_STANDBY_MODE
 
- VPE_INT0_CHANNEL_GROUP0
 
- VPE_INT0_CHANNEL_GROUP1
 
- VPE_INT0_CHANNEL_GROUP2
 
- VPE_INT0_CHANNEL_GROUP3
 
- VPE_INT0_CHANNEL_GROUP4
 
- VPE_INT0_CHANNEL_GROUP5
 
- VPE_INT0_CLIENT
 
- VPE_INT0_DESCRIPTOR
 
- VPE_INT0_ENABLE0
 
- VPE_INT0_ENABLE0_CLR
 
- VPE_INT0_ENABLE0_SET
 
- VPE_INT0_ENABLE1
 
- VPE_INT0_ENABLE1_CLR
 
- VPE_INT0_ENABLE1_SET
 
- VPE_INT0_LIST0_COMPLETE
 
- VPE_INT0_LIST0_NOTIFY
 
- VPE_INT0_LIST1_COMPLETE
 
- VPE_INT0_LIST1_NOTIFY
 
- VPE_INT0_LIST2_COMPLETE
 
- VPE_INT0_LIST2_NOTIFY
 
- VPE_INT0_LIST3_COMPLETE
 
- VPE_INT0_LIST3_NOTIFY
 
- VPE_INT0_LIST4_COMPLETE
 
- VPE_INT0_LIST4_NOTIFY
 
- VPE_INT0_LIST5_COMPLETE
 
- VPE_INT0_LIST5_NOTIFY
 
- VPE_INT0_LIST6_COMPLETE
 
- VPE_INT0_LIST6_NOTIFY
 
- VPE_INT0_LIST7_COMPLETE
 
- VPE_INT0_LIST7_NOTIFY
 
- VPE_INT0_STATUS0
 
- VPE_INT0_STATUS0_CLR
 
- VPE_INT0_STATUS0_RAW
 
- VPE_INT0_STATUS0_RAW_SET
 
- VPE_INT0_STATUS1
 
- VPE_INT0_STATUS1_CLR
 
- VPE_INT0_STATUS1_RAW
 
- VPE_INT0_STATUS1_RAW_SET
 
- VPE_INTC_EOI
 
- VPE_INTERP_FID0_C0_MASK
 
- VPE_INTERP_FID0_C0_SHIFT
 
- VPE_INTERP_FID0_C1_MASK
 
- VPE_INTERP_FID0_C1_SHIFT
 
- VPE_INTERP_FID0_C2_MASK
 
- VPE_INTERP_FID0_C2_SHIFT
 
- VPE_INTERP_FID0_C3_MASK
 
- VPE_INTERP_FID0_C3_SHIFT
 
- VPE_INTERP_FID1_C0_MASK
 
- VPE_INTERP_FID1_C0_SHIFT
 
- VPE_INTERP_FID1_C1_MASK
 
- VPE_INTERP_FID1_C1_SHIFT
 
- VPE_LUMA
 
- VPE_MAIN_RESET_MASK
 
- VPE_MAIN_RESET_SHIFT
 
- VPE_MAX_PLANES
 
- VPE_MAX_SRC_BUFS
 
- VPE_MDT_BYPASS
 
- VPE_MDT_SF_SC_THR1_MASK
 
- VPE_MDT_SF_SC_THR1_SHIFT
 
- VPE_MDT_SF_SC_THR2_MASK
 
- VPE_MDT_SF_SC_THR2_SHIFT
 
- VPE_MDT_SF_SC_THR3_MASK
 
- VPE_MDT_SF_SC_THR3_SHIFT
 
- VPE_MDT_SF_THRESHOLD
 
- VPE_MDT_SPATMAX_BYPASS
 
- VPE_MDT_TEMPMAX_BYPASS
 
- VPE_MODULE_MINOR
 
- VPE_MODULE_NAME
 
- VPE_NO_IDLE_MODE
 
- VPE_NO_STANDBY_MODE
 
- VPE_PATH_MAX
 
- VPE_PID
 
- VPE_PID_CUSTOM_MASK
 
- VPE_PID_CUSTOM_SHIFT
 
- VPE_PID_FUNC_MASK
 
- VPE_PID_FUNC_SHIFT
 
- VPE_PID_MAJOR_MASK
 
- VPE_PID_MAJOR_SHIFT
 
- VPE_PID_MINOR_MASK
 
- VPE_PID_MINOR_SHIFT
 
- VPE_PID_RTL_MASK
 
- VPE_PID_RTL_SHIFT
 
- VPE_PID_SCHEME_MASK
 
- VPE_PID_SCHEME_SHIFT
 
- VPE_PORT_CHROMA1_IN
 
- VPE_PORT_CHROMA2_IN
 
- VPE_PORT_CHROMA3_IN
 
- VPE_PORT_CHROMA_OUT
 
- VPE_PORT_LUMA1_IN
 
- VPE_PORT_LUMA2_IN
 
- VPE_PORT_LUMA3_IN
 
- VPE_PORT_LUMA_OUT
 
- VPE_PORT_MV_IN
 
- VPE_PORT_MV_OUT
 
- VPE_PORT_RGB_OUT
 
- VPE_RANGE_MAP_ON
 
- VPE_RANGE_RANGE_MAP_UV_MASK
 
- VPE_RANGE_RANGE_MAP_UV_SHIFT
 
- VPE_RANGE_RANGE_MAP_Y_MASK
 
- VPE_RANGE_RANGE_MAP_Y_SHIFT
 
- VPE_RANGE_REDUCTION_ON
 
- VPE_RESET
 
- VPE_RGB_OUT_SELECT
 
- VPE_SET_MMR_ADB_HDR
 
- VPE_SMART_IDLE_MODE
 
- VPE_SMART_IDLE_WAKEUP_MODE
 
- VPE_SMART_STANDBY_MODE
 
- VPE_SMART_STANDBY_WAKEUP_MODE
 
- VPE_SRC
 
- VPE_STATE_INUSE
 
- VPE_STATE_RUNNING
 
- VPE_STATE_UNUSED
 
- VPE_SYSCONFIG
 
- VPE_SYSCONFIG_IDLE_MASK
 
- VPE_SYSCONFIG_IDLE_SHIFT
 
- VPE_SYSCONFIG_STANDBY_MASK
 
- VPE_SYSCONFIG_STANDBY_SHIFT
 
- VPE_US1_R0
 
- VPE_US1_R1
 
- VPE_US1_R2
 
- VPE_US1_R3
 
- VPE_US1_R4
 
- VPE_US1_R5
 
- VPE_US1_R6
 
- VPE_US1_R7
 
- VPE_US2_R0
 
- VPE_US2_R1
 
- VPE_US2_R2
 
- VPE_US2_R3
 
- VPE_US2_R4
 
- VPE_US2_R5
 
- VPE_US2_R6
 
- VPE_US2_R7
 
- VPE_US3_R0
 
- VPE_US3_R1
 
- VPE_US3_R2
 
- VPE_US3_R3
 
- VPE_US3_R4
 
- VPE_US3_R5
 
- VPE_US3_R6
 
- VPE_US3_R7
 
- VPE_US_C0_MASK
 
- VPE_US_C0_SHIFT
 
- VPE_US_C1_MASK
 
- VPE_US_C1_SHIFT
 
- VPE_US_MODE_MASK
 
- VPE_US_MODE_SHIFT
 
- VPE_VPDMA_CLK_RESET_MASK
 
- VPE_VPDMA_CLK_RESET_SHIFT
 
- VPE_VPEDMA_CLK_ENABLE
 
- VPFE_32BYTE_ALIGN_VAL
 
- VPFE_ALAW
 
- VPFE_ALAW_ENABLE
 
- VPFE_ALAW_GAMMA_WD_MASK
 
- VPFE_BLKCMP
 
- VPFE_BLK_CLAMP_ENABLE
 
- VPFE_BLK_COMP_GB_COMP_SHIFT
 
- VPFE_BLK_COMP_GR_COMP_SHIFT
 
- VPFE_BLK_COMP_MASK
 
- VPFE_BLK_COMP_R_COMP_SHIFT
 
- VPFE_BLK_DC_SUB_MASK
 
- VPFE_BLK_SAMPLE_LINE_MASK
 
- VPFE_BLK_SAMPLE_LINE_SHIFT
 
- VPFE_BLK_SAMPLE_LN_MASK
 
- VPFE_BLK_SAMPLE_LN_SHIFT
 
- VPFE_BLK_SGAIN_MASK
 
- VPFE_BLK_ST_PXL_MASK
 
- VPFE_BLK_ST_PXL_SHIFT
 
- VPFE_BT1120
 
- VPFE_BT656
 
- VPFE_BT656_10BIT
 
- VPFE_BUILD
 
- VPFE_CAPTURE_NUM_DECODERS
 
- VPFE_CAPTURE_VERSION_CODE
 
- VPFE_CCDCFG
 
- VPFE_CCDCFG_BW656_10BIT
 
- VPFE_CCDCFG_Y8POS_SHIFT
 
- VPFE_CCDC_DATA_10BITS
 
- VPFE_CCDC_DATA_11BITS
 
- VPFE_CCDC_DATA_12BITS
 
- VPFE_CCDC_DATA_13BITS
 
- VPFE_CCDC_DATA_14BITS
 
- VPFE_CCDC_DATA_15BITS
 
- VPFE_CCDC_DATA_16BITS
 
- VPFE_CCDC_DATA_8BITS
 
- VPFE_CCDC_GAMMA_BITS_09_0
 
- VPFE_CCDC_GAMMA_BITS_10_1
 
- VPFE_CCDC_GAMMA_BITS_11_2
 
- VPFE_CCDC_GAMMA_BITS_12_3
 
- VPFE_CCDC_GAMMA_BITS_13_4
 
- VPFE_CCDC_GAMMA_BITS_14_5
 
- VPFE_CCDC_GAMMA_BITS_15_6
 
- VPFE_CCDC_SAMPLE_16LINES
 
- VPFE_CCDC_SAMPLE_16PIXELS
 
- VPFE_CCDC_SAMPLE_1LINES
 
- VPFE_CCDC_SAMPLE_1PIXELS
 
- VPFE_CCDC_SAMPLE_2LINES
 
- VPFE_CCDC_SAMPLE_2PIXELS
 
- VPFE_CCDC_SAMPLE_4LINES
 
- VPFE_CCDC_SAMPLE_4PIXELS
 
- VPFE_CCDC_SAMPLE_8LINES
 
- VPFE_CCDC_SAMPLE_8PIXELS
 
- VPFE_CLAMP
 
- VPFE_CLAMP_DEFAULT_VAL
 
- VPFE_COLPTN
 
- VPFE_COLPTN_VAL
 
- VPFE_CONFIG
 
- VPFE_CONFIG_EN_DISABLE
 
- VPFE_CONFIG_EN_ENABLE
 
- VPFE_CONFIG_EN_MASK
 
- VPFE_CONFIG_EN_SHIFT
 
- VPFE_CONFIG_PCLK_INV_INV
 
- VPFE_CONFIG_PCLK_INV_MASK
 
- VPFE_CONFIG_PCLK_INV_NOT_INV
 
- VPFE_CONFIG_PCLK_INV_SHIFT
 
- VPFE_CONFIG_ST_MASK
 
- VPFE_CONFIG_ST_OCP_ACTIVE
 
- VPFE_CONFIG_ST_OCP_STANDBY
 
- VPFE_CONFIG_ST_SHIFT
 
- VPFE_CULLING
 
- VPFE_DATA_PACK_ENABLE
 
- VPFE_DATA_SZ_MASK
 
- VPFE_DATA_SZ_SHIFT
 
- VPFE_DCSUB
 
- VPFE_DCSUB_DEFAULT_VAL
 
- VPFE_DMA_CNTL
 
- VPFE_DMA_CNTL_OVERFLOW
 
- VPFE_FID_POL_MASK
 
- VPFE_FID_POL_SHIFT
 
- VPFE_FRM_FMT_MASK
 
- VPFE_FRM_FMT_SHIFT
 
- VPFE_HD_POL_MASK
 
- VPFE_HD_POL_SHIFT
 
- VPFE_HD_VD_WID
 
- VPFE_HORZ_INFO
 
- VPFE_HORZ_INFO_SPH_SHIFT
 
- VPFE_HSIZE_OFF
 
- VPFE_HSIZE_OFF_MASK
 
- VPFE_INTERLACED_HEIGHT_SHIFT
 
- VPFE_INTERLACED_IMAGE_INVERT
 
- VPFE_INTERLACED_NO_IMAGE_INVERT
 
- VPFE_IRQ_EN_CLR
 
- VPFE_IRQ_EN_SET
 
- VPFE_IRQ_EOI
 
- VPFE_IRQ_STS
 
- VPFE_IRQ_STS_RAW
 
- VPFE_LATCH_ON_VSYNC_DISABLE
 
- VPFE_LPF_ENABLE
 
- VPFE_MAJOR_RELEASE
 
- VPFE_MAX_INPUTS
 
- VPFE_MAX_SUBDEV
 
- VPFE_MINOR_RELEASE
 
- VPFE_MODULE_NAME
 
- VPFE_NO_CULLING
 
- VPFE_PCR
 
- VPFE_PINPOL_NEGATIVE
 
- VPFE_PINPOL_POSITIVE
 
- VPFE_PIX_FMT_MASK
 
- VPFE_PIX_FMT_SHIFT
 
- VPFE_PIX_LINES
 
- VPFE_PPC_RAW
 
- VPFE_PROGRESSIVE_IMAGE_INVERT
 
- VPFE_PROGRESSIVE_NO_IMAGE_INVERT
 
- VPFE_RAW_BAYER
 
- VPFE_REC656IF
 
- VPFE_REC656IF_BT656_EN
 
- VPFE_REG_END
 
- VPFE_REVISION
 
- VPFE_SDOFST
 
- VPFE_SDOFST_FIELD_INTERLEAVED
 
- VPFE_SDR2RSZ_DISABLE
 
- VPFE_SDR_ADDR
 
- VPFE_SYNMODE
 
- VPFE_SYN_FLDMODE_MASK
 
- VPFE_SYN_FLDMODE_SHIFT
 
- VPFE_SYN_MODE_10BITS
 
- VPFE_SYN_MODE_11BITS
 
- VPFE_SYN_MODE_12BITS
 
- VPFE_SYN_MODE_13BITS
 
- VPFE_SYN_MODE_14BITS
 
- VPFE_SYN_MODE_15BITS
 
- VPFE_SYN_MODE_16BITS
 
- VPFE_SYN_MODE_8BITS
 
- VPFE_SYN_MODE_INPMOD_MASK
 
- VPFE_SYN_MODE_INPMOD_SHIFT
 
- VPFE_SYN_MODE_VD_POL_NEGATIVE
 
- VPFE_SYSCONFIG
 
- VPFE_TWO_BYTES_PER_PIXEL
 
- VPFE_VDHDEN_ENABLE
 
- VPFE_VDINT
 
- VPFE_VDINT0
 
- VPFE_VDINT1
 
- VPFE_VDINT2
 
- VPFE_VDINT_VDINT0_SHIFT
 
- VPFE_VDINT_VDINT1_MASK
 
- VPFE_VD_POL_MASK
 
- VPFE_VD_POL_SHIFT
 
- VPFE_VERSION
 
- VPFE_VERT_LINES
 
- VPFE_VERT_START
 
- VPFE_VERT_START_SLV0_SHIFT
 
- VPFE_VP2SDR_DISABLE
 
- VPFE_WEN_ENABLE
 
- VPFE_YCBCR_SYNC_16
 
- VPFE_YCBCR_SYNC_8
 
- VPGEN_VFRSTAT
 
- VPGEN_VFRSTAT_VFRD_M
 
- VPGEN_VFRTRIG
 
- VPGEN_VFRTRIG_VFSWR_M
 
- VPHN_ASSOC_BUFSIZE
 
- VPHN_FIELD_MASK
 
- VPHN_FIELD_MSB
 
- VPHN_FIELD_UNUSED
 
- VPHN_FLAG_PCPU
 
- VPHN_FLAG_VCPU
 
- VPHN_REGISTER_COUNT
 
- VPI18_DESC
 
- VPI24_DESC
 
- VPI30_DESC
 
- VPIDR
 
- VPIF_CAPTURE_CH_NIP
 
- VPIF_CAPTURE_H
 
- VPIF_CAPTURE_MAX_CHANNELS
 
- VPIF_CAPTURE_MAX_DEVICES
 
- VPIF_CAPTURE_NUM_CHANNELS
 
- VPIF_CAPTURE_VERSION
 
- VPIF_CH0_BTM_STRT_ADD_CHROMA
 
- VPIF_CH0_BTM_STRT_ADD_HANC
 
- VPIF_CH0_BTM_STRT_ADD_LUMA
 
- VPIF_CH0_BTM_STRT_ADD_VANC
 
- VPIF_CH0_CLK_EN
 
- VPIF_CH0_CTRL
 
- VPIF_CH0_EN
 
- VPIF_CH0_HANC_ADD_OFST
 
- VPIF_CH0_H_CFG
 
- VPIF_CH0_IMG_ADD_OFST
 
- VPIF_CH0_INT_CTRL_SHIFT
 
- VPIF_CH0_MAX_MODES
 
- VPIF_CH0_SP_CFG
 
- VPIF_CH0_TOP_STRT_ADD_CHROMA
 
- VPIF_CH0_TOP_STRT_ADD_HANC
 
- VPIF_CH0_TOP_STRT_ADD_LUMA
 
- VPIF_CH0_TOP_STRT_ADD_VANC
 
- VPIF_CH0_V_CFG_00
 
- VPIF_CH0_V_CFG_01
 
- VPIF_CH0_V_CFG_02
 
- VPIF_CH0_V_CFG_03
 
- VPIF_CH1_BTM_STRT_ADD_CHROMA
 
- VPIF_CH1_BTM_STRT_ADD_HANC
 
- VPIF_CH1_BTM_STRT_ADD_LUMA
 
- VPIF_CH1_BTM_STRT_ADD_VANC
 
- VPIF_CH1_CLK_EN
 
- VPIF_CH1_CTRL
 
- VPIF_CH1_EN
 
- VPIF_CH1_HANC_ADD_OFST
 
- VPIF_CH1_H_CFG
 
- VPIF_CH1_IMG_ADD_OFST
 
- VPIF_CH1_INT_CTRL_SHIFT
 
- VPIF_CH1_MAX_MODES
 
- VPIF_CH1_SP_CFG
 
- VPIF_CH1_TOP_STRT_ADD_CHROMA
 
- VPIF_CH1_TOP_STRT_ADD_HANC
 
- VPIF_CH1_TOP_STRT_ADD_LUMA
 
- VPIF_CH1_TOP_STRT_ADD_VANC
 
- VPIF_CH1_V_CFG_00
 
- VPIF_CH1_V_CFG_01
 
- VPIF_CH1_V_CFG_02
 
- VPIF_CH1_V_CFG_03
 
- VPIF_CH2_BTM_STRT_ADD_CHROMA
 
- VPIF_CH2_BTM_STRT_ADD_HANC
 
- VPIF_CH2_BTM_STRT_ADD_LUMA
 
- VPIF_CH2_BTM_STRT_ADD_VANC
 
- VPIF_CH2_CLIP_ACTIVE_EN
 
- VPIF_CH2_CLIP_ANC_EN
 
- VPIF_CH2_CLK_EN
 
- VPIF_CH2_CTRL
 
- VPIF_CH2_EN
 
- VPIF_CH2_HANC0_SIZE
 
- VPIF_CH2_HANC0_STRT
 
- VPIF_CH2_HANC1_SIZE
 
- VPIF_CH2_HANC1_STRT
 
- VPIF_CH2_HANC_ADD_OFST
 
- VPIF_CH2_H_CFG
 
- VPIF_CH2_IMG_ADD_OFST
 
- VPIF_CH2_INT_CTRL_SHIFT
 
- VPIF_CH2_MAX_MODES
 
- VPIF_CH2_SP_CFG
 
- VPIF_CH2_TOP_STRT_ADD_CHROMA
 
- VPIF_CH2_TOP_STRT_ADD_HANC
 
- VPIF_CH2_TOP_STRT_ADD_LUMA
 
- VPIF_CH2_TOP_STRT_ADD_VANC
 
- VPIF_CH2_VANC0_SIZE
 
- VPIF_CH2_VANC0_STRT
 
- VPIF_CH2_VANC1_SIZE
 
- VPIF_CH2_VANC1_STRT
 
- VPIF_CH2_V_CFG_00
 
- VPIF_CH2_V_CFG_01
 
- VPIF_CH2_V_CFG_02
 
- VPIF_CH2_V_CFG_03
 
- VPIF_CH3_BTM_STRT_ADD_CHROMA
 
- VPIF_CH3_BTM_STRT_ADD_HANC
 
- VPIF_CH3_BTM_STRT_ADD_LUMA
 
- VPIF_CH3_BTM_STRT_ADD_VANC
 
- VPIF_CH3_CLIP_ACTIVE_EN
 
- VPIF_CH3_CLIP_ANC_EN
 
- VPIF_CH3_CLK_EN
 
- VPIF_CH3_CTRL
 
- VPIF_CH3_EN
 
- VPIF_CH3_HANC0_SIZE
 
- VPIF_CH3_HANC0_STRT
 
- VPIF_CH3_HANC1_SIZE
 
- VPIF_CH3_HANC1_STRT
 
- VPIF_CH3_HANC_ADD_OFST
 
- VPIF_CH3_H_CFG
 
- VPIF_CH3_IMG_ADD_OFST
 
- VPIF_CH3_INT_CTRL_SHIFT
 
- VPIF_CH3_MAX_MODES
 
- VPIF_CH3_SP_CFG
 
- VPIF_CH3_TOP_STRT_ADD_CHROMA
 
- VPIF_CH3_TOP_STRT_ADD_HANC
 
- VPIF_CH3_TOP_STRT_ADD_LUMA
 
- VPIF_CH3_TOP_STRT_ADD_VANC
 
- VPIF_CH3_VANC0_SIZE
 
- VPIF_CH3_VANC0_STRT
 
- VPIF_CH3_VANC1_SIZE
 
- VPIF_CH3_VANC1_STRT
 
- VPIF_CH3_V_CFG_00
 
- VPIF_CH3_V_CFG_01
 
- VPIF_CH3_V_CFG_02
 
- VPIF_CH3_V_CFG_03
 
- VPIF_CHANNEL0_VIDEO
 
- VPIF_CHANNEL1_VIDEO
 
- VPIF_CHANNEL2_VIDEO
 
- VPIF_CHANNEL3_VIDEO
 
- VPIF_CH_CLK_EDGE_CTRL_BIT
 
- VPIF_CH_CLK_EN
 
- VPIF_CH_DATA_MODE_BIT
 
- VPIF_CH_DATA_WIDTH_BIT
 
- VPIF_CH_EAVSAV_MASK
 
- VPIF_CH_EN
 
- VPIF_CH_FID_MASK
 
- VPIF_CH_FID_POLARITY_BIT
 
- VPIF_CH_FID_SHIFT
 
- VPIF_CH_HANC_EN_BIT
 
- VPIF_CH_H_VALID_POLARITY_BIT
 
- VPIF_CH_INPUT_FIELD_FRAME_BIT
 
- VPIF_CH_INT_CTRL_SHIFT
 
- VPIF_CH_LEN_MASK
 
- VPIF_CH_LEN_SHIFT
 
- VPIF_CH_SDR_FMT_BIT
 
- VPIF_CH_VANC_EN
 
- VPIF_CH_VANC_EN_BIT
 
- VPIF_CH_V_VALID_POLARITY_BIT
 
- VPIF_CH_WIDTH_MASK
 
- VPIF_CH_YC_MUX_BIT
 
- VPIF_DISPLAY_CH_NIP
 
- VPIF_DISPLAY_H
 
- VPIF_DISPLAY_MAX_CHANNELS
 
- VPIF_DISPLAY_MAX_DEVICES
 
- VPIF_DISPLAY_NUM_CHANNELS
 
- VPIF_DISPLAY_PIX_EN_BIT
 
- VPIF_DISPLAY_VERSION
 
- VPIF_DMA_REQ_SIZE
 
- VPIF_DRIVER_NAME
 
- VPIF_EMULATION_CTRL
 
- VPIF_EMULATION_DISABLE
 
- VPIF_H
 
- VPIF_HBI_INDEX
 
- VPIF_IF_BT1120
 
- VPIF_IF_BT656
 
- VPIF_IF_RAW_BAYER
 
- VPIF_INPUT_ONE_CHANNEL
 
- VPIF_INPUT_TWO_CHANNEL
 
- VPIF_INTEN
 
- VPIF_INTEN_CLR
 
- VPIF_INTEN_FRAME_CH0
 
- VPIF_INTEN_FRAME_CH1
 
- VPIF_INTEN_FRAME_CH2
 
- VPIF_INTEN_FRAME_CH3
 
- VPIF_INTEN_SET
 
- VPIF_INT_BOTH
 
- VPIF_INT_BOTTOM
 
- VPIF_INT_TOP
 
- VPIF_IODFT_CTRL
 
- VPIF_MAX_NAME
 
- VPIF_NTSC_HBI_COUNT_FIELD0
 
- VPIF_NTSC_HBI_COUNT_FIELD1
 
- VPIF_NTSC_HBI_SAMPLES_PER_LINE
 
- VPIF_NTSC_HBI_START_FIELD0
 
- VPIF_NTSC_HBI_START_FIELD1
 
- VPIF_NTSC_VBI_COUNT_FIELD0
 
- VPIF_NTSC_VBI_COUNT_FIELD1
 
- VPIF_NTSC_VBI_SAMPLES_PER_LINE
 
- VPIF_NTSC_VBI_START_FIELD0
 
- VPIF_NTSC_VBI_START_FIELD1
 
- VPIF_NUMBER_OF_OBJECTS
 
- VPIF_NUMOBJECTS
 
- VPIF_NUM_CHANNELS
 
- VPIF_PAL_HBI_COUNT_FIELD0
 
- VPIF_PAL_HBI_COUNT_FIELD1
 
- VPIF_PAL_HBI_SAMPLES_PER_LINE
 
- VPIF_PAL_HBI_START_FIELD0
 
- VPIF_PAL_HBI_START_FIELD1
 
- VPIF_PAL_VBI_COUNT_FIELD0
 
- VPIF_PAL_VBI_COUNT_FIELD1
 
- VPIF_PAL_VBI_SAMPLES_PER_LINE
 
- VPIF_PAL_VBI_START_FIELD0
 
- VPIF_PAL_VBI_START_FIELD1
 
- VPIF_PID
 
- VPIF_REQ_SIZE
 
- VPIF_REQ_SIZE_MASK
 
- VPIF_SLICED_BUF_SIZE
 
- VPIF_SLICED_MAX_SERVICES
 
- VPIF_STATUS
 
- VPIF_STATUS_CLR
 
- VPIF_V4L2_STD
 
- VPIF_VALID_FIELD
 
- VPIF_VBI_INDEX
 
- VPIF_VIDEO_INDEX
 
- VPINT_ALLOC
 
- VPINT_ALLOC_FIRST_M
 
- VPINT_ALLOC_FIRST_S
 
- VPINT_ALLOC_LAST_M
 
- VPINT_ALLOC_LAST_S
 
- VPINT_ALLOC_PCI
 
- VPINT_ALLOC_PCI_FIRST_M
 
- VPINT_ALLOC_PCI_FIRST_S
 
- VPINT_ALLOC_PCI_LAST_M
 
- VPINT_ALLOC_PCI_LAST_S
 
- VPINT_ALLOC_PCI_VALID_M
 
- VPINT_ALLOC_VALID_M
 
- VPINT_MBX_CTL
 
- VPINT_MBX_CTL_CAUSE_ENA_M
 
- VPIOFF0_DESC
 
- VPIOFF1_DESC
 
- VPIRSVD_DESC
 
- VPITTable
 
- VPI_24_RSVD_DESC
 
- VPLAN_RXQ_MAPENA
 
- VPLAN_RXQ_MAPENA_RX_ENA_M
 
- VPLAN_RX_QBASE
 
- VPLAN_RX_QBASE_VFFIRSTQ_M
 
- VPLAN_RX_QBASE_VFFIRSTQ_S
 
- VPLAN_RX_QBASE_VFNUMQ_M
 
- VPLAN_RX_QBASE_VFNUMQ_S
 
- VPLAN_TXQ_MAPENA
 
- VPLAN_TXQ_MAPENA_TX_ENA_M
 
- VPLAN_TX_QBASE
 
- VPLAN_TX_QBASE_VFFIRSTQ_M
 
- VPLAN_TX_QBASE_VFFIRSTQ_S
 
- VPLAN_TX_QBASE_VFNUMQ_M
 
- VPLAN_TX_QBASE_VFNUMQ_S
 
- VPLL
 
- VPLL_CNTL
 
- VPLL_CON
 
- VPLL_CON0
 
- VPLL_CON1
 
- VPLL_CON2
 
- VPLL_HALF
 
- VPLL_INT
 
- VPLL_INT_MUX
 
- VPLL_LOCK
 
- VPLL_POST_SRC
 
- VPLL_PRE_SRC
 
- VPLL_SEL_MASK
 
- VPLL_SEL_SHIFT
 
- VPLL_ST_MASK
 
- VPLL_ST_SHIFT
 
- VPLL_TO_LPD
 
- VPM
 
- VPMSUMD
 
- VPMSUMW
 
- VPN2_MASK
 
- VPN_MASK
 
- VPN_SHIFT
 
- VPO12_DESC
 
- VPO24_DESC
 
- VPOOFF0_DESC
 
- VPOOFF1_DESC
 
- VPOOFF2_DESC
 
- VPORT_ALIGN
 
- VPORT_API_VERSION_1
 
- VPORT_CNT_INVALID
 
- VPORT_COUNTER_GET
 
- VPORT_COUNTER_OFF
 
- VPORT_CREATE
 
- VPORT_DELETE
 
- VPORT_ERROR
 
- VPORT_FAIL_ADAP_NORESOURCES
 
- VPORT_FAIL_FAB_LOGOUT
 
- VPORT_FAIL_FAB_NORESOURCES
 
- VPORT_FAIL_FAB_UNSUPPORTED
 
- VPORT_FAIL_LINKDOWN
 
- VPORT_FAIL_UNKNOWN
 
- VPORT_H
 
- VPORT_HASH_BUCKETS
 
- VPORT_INFO
 
- VPORT_INFO_REV
 
- VPORT_INFO_REV_MASK
 
- VPORT_INFO_SIG
 
- VPORT_INTERNAL_DEV_H
 
- VPORT_INVAL
 
- VPORT_MISS_MODE_ACCEPT_ALL
 
- VPORT_MISS_MODE_ACCEPT_MULTI
 
- VPORT_MISS_MODE_DROP
 
- VPORT_NETDEV_H
 
- VPORT_NOMEM
 
- VPORT_NORESOURCES
 
- VPORT_OK
 
- VPORT_OPT_AUTORETRY
 
- VPORT_STATE_ACTIVE
 
- VPORT_STATE_DOWN
 
- VPORT_STATE_FAILED
 
- VPORT_STATE_OFFLINE
 
- VPORT_STATE_UP
 
- VPORT_TYPE_PHYSICAL
 
- VPORT_TYPE_VIRTUAL
 
- VPO_24_OFF
 
- VPO_DESC
 
- VPO_OFF_12
 
- VPP2_BLEND_ONECOLOR_CTRL
 
- VPP2_CHROMA_ADDR_PORT
 
- VPP2_CHROMA_DATA_PORT
 
- VPP2_DNLP_CTRL_00
 
- VPP2_DNLP_CTRL_01
 
- VPP2_DNLP_CTRL_02
 
- VPP2_DNLP_CTRL_03
 
- VPP2_DNLP_CTRL_04
 
- VPP2_DNLP_CTRL_05
 
- VPP2_DNLP_CTRL_06
 
- VPP2_DNLP_CTRL_07
 
- VPP2_DNLP_CTRL_08
 
- VPP2_DNLP_CTRL_09
 
- VPP2_DNLP_CTRL_10
 
- VPP2_DNLP_CTRL_11
 
- VPP2_DNLP_CTRL_12
 
- VPP2_DNLP_CTRL_13
 
- VPP2_DNLP_CTRL_14
 
- VPP2_DNLP_CTRL_15
 
- VPP2_DUMMY_DATA
 
- VPP2_DUMMY_DATA1
 
- VPP2_FIFO_STATUS
 
- VPP2_GAINOFF_CTRL0
 
- VPP2_GAINOFF_CTRL1
 
- VPP2_GAINOFF_CTRL2
 
- VPP2_GAINOFF_CTRL3
 
- VPP2_GAINOFF_CTRL4
 
- VPP2_GCLK_CTRL0
 
- VPP2_GCLK_CTRL1
 
- VPP2_HOLD_LINES
 
- VPP2_HSC_INI_PAT_CTRL
 
- VPP2_HSC_PHASE_CTRL
 
- VPP2_HSC_PHASE_CTRL1
 
- VPP2_HSC_REGION0_PHASE_SLOPE
 
- VPP2_HSC_REGION12_STARTP
 
- VPP2_HSC_REGION1_PHASE_SLOPE
 
- VPP2_HSC_REGION34_STARTP
 
- VPP2_HSC_REGION3_PHASE_SLOPE
 
- VPP2_HSC_REGION4_ENDP
 
- VPP2_HSC_REGION4_PHASE_SLOPE
 
- VPP2_HSC_START_PHASE_STEP
 
- VPP2_INT_LINE_NUM
 
- VPP2_LINE_IN_LENGTH
 
- VPP2_MATRIX_COEF00_01
 
- VPP2_MATRIX_COEF02_10
 
- VPP2_MATRIX_COEF11_12
 
- VPP2_MATRIX_COEF20_21
 
- VPP2_MATRIX_COEF22
 
- VPP2_MATRIX_CTRL
 
- VPP2_MATRIX_HL_COLOR
 
- VPP2_MATRIX_OFFSET0_1
 
- VPP2_MATRIX_OFFSET2
 
- VPP2_MATRIX_PRE_OFFSET0_1
 
- VPP2_MATRIX_PRE_OFFSET2
 
- VPP2_MATRIX_PROBE_COLOR
 
- VPP2_MATRIX_PROBE_POS
 
- VPP2_MISC
 
- VPP2_MISC1
 
- VPP2_OFIFO_SIZE
 
- VPP2_OSD_HSC_CTRL0
 
- VPP2_OSD_HSC_INI_PAT_CTRL
 
- VPP2_OSD_HSC_INI_PHASE
 
- VPP2_OSD_HSC_PHASE_STEP
 
- VPP2_OSD_SCALE_COEF
 
- VPP2_OSD_SCALE_COEF_IDX
 
- VPP2_OSD_SCI_WH_M1
 
- VPP2_OSD_SCO_H_START_END
 
- VPP2_OSD_SCO_V_START_END
 
- VPP2_OSD_SC_CTRL0
 
- VPP2_OSD_SC_DUMMY_DATA
 
- VPP2_OSD_VSC_CTRL0
 
- VPP2_OSD_VSC_INI_PHASE
 
- VPP2_OSD_VSC_PHASE_STEP
 
- VPP2_PIC_IN_HEIGHT
 
- VPP2_POSTBLEND_CURRENT_XY
 
- VPP2_POSTBLEND_H_SIZE
 
- VPP2_POSTBLEND_VD1_H_START_END
 
- VPP2_POSTBLEND_VD1_V_START_END
 
- VPP2_PREBLEND_CURRENT_XY
 
- VPP2_PREBLEND_H_SIZE
 
- VPP2_PREBLEND_VD1_H_START_END
 
- VPP2_PREBLEND_VD1_V_START_END
 
- VPP2_SCALE_COEF
 
- VPP2_SCALE_COEF_IDX
 
- VPP2_SCO_FIFO_CTRL
 
- VPP2_SC_GCLK_CTRL
 
- VPP2_SC_MISC
 
- VPP2_SMOKE1_H_START_END
 
- VPP2_SMOKE1_VAL
 
- VPP2_SMOKE1_V_START_END
 
- VPP2_SMOKE2_H_START_END
 
- VPP2_SMOKE2_VAL
 
- VPP2_SMOKE2_V_START_END
 
- VPP2_SMOKE_CTRL
 
- VPP2_VADJ1_MA_MB
 
- VPP2_VADJ1_MC_MD
 
- VPP2_VADJ1_Y
 
- VPP2_VADJ2_MA_MB
 
- VPP2_VADJ2_MC_MD
 
- VPP2_VADJ2_Y
 
- VPP2_VADJ_CTRL
 
- VPP2_VDO_MEAS_CTRL
 
- VPP2_VDO_MEAS_VS_COUNT_HI
 
- VPP2_VDO_MEAS_VS_COUNT_LO
 
- VPP2_VE_DEMO_CENTER_BAR
 
- VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH
 
- VPP2_VE_ENABLE_CTRL
 
- VPP2_VE_H_V_SIZE
 
- VPP2_VSC_INI_PHASE
 
- VPP2_VSC_PHASE_CTRL
 
- VPP2_VSC_REGION0_PHASE_SLOPE
 
- VPP2_VSC_REGION12_STARTP
 
- VPP2_VSC_REGION1_PHASE_SLOPE
 
- VPP2_VSC_REGION34_STARTP
 
- VPP2_VSC_REGION3_PHASE_SLOPE
 
- VPP2_VSC_REGION4_ENDP
 
- VPP2_VSC_REGION4_PHASE_SLOPE
 
- VPP2_VSC_START_PHASE_STEP
 
- VPP_0V
 
- VPP_12V
 
- VPP_BLACKEXT_CTRL
 
- VPP_BLEND_ONECOLOR_CTRL
 
- VPP_BLEND_VD2_H_START_END
 
- VPP_BLEND_VD2_V_START_END
 
- VPP_BLUE_STRETCH_1
 
- VPP_BLUE_STRETCH_2
 
- VPP_BLUE_STRETCH_3
 
- VPP_CCORING_CTRL
 
- VPP_CHROMA_ADDR_PORT
 
- VPP_CHROMA_DATA_PORT
 
- VPP_CNT_0V
 
- VPP_CNT_12V
 
- VPP_CNT_3V
 
- VPP_CNT_5V
 
- VPP_CNT_MASK
 
- VPP_COLOR_MNG_ENABLE
 
- VPP_CTI_CTRL
 
- VPP_CTI_CTRL2
 
- VPP_DNLP_CTRL_00
 
- VPP_DNLP_CTRL_01
 
- VPP_DNLP_CTRL_02
 
- VPP_DNLP_CTRL_03
 
- VPP_DNLP_CTRL_04
 
- VPP_DNLP_CTRL_05
 
- VPP_DNLP_CTRL_06
 
- VPP_DNLP_CTRL_07
 
- VPP_DNLP_CTRL_08
 
- VPP_DNLP_CTRL_09
 
- VPP_DNLP_CTRL_10
 
- VPP_DNLP_CTRL_11
 
- VPP_DNLP_CTRL_12
 
- VPP_DNLP_CTRL_13
 
- VPP_DNLP_CTRL_14
 
- VPP_DNLP_CTRL_15
 
- VPP_DOLBY_CTRL
 
- VPP_DUMMY_DATA
 
- VPP_DUMMY_DATA1
 
- VPP_FIFO_STATUS
 
- VPP_FRONT_CTI_CTRL
 
- VPP_FRONT_CTI_CTRL2
 
- VPP_FRONT_HLTI_CTRL
 
- VPP_GAINOFF_CTRL0
 
- VPP_GAINOFF_CTRL1
 
- VPP_GAINOFF_CTRL2
 
- VPP_GAINOFF_CTRL3
 
- VPP_GAINOFF_CTRL4
 
- VPP_GCLK_CTRL0
 
- VPP_GCLK_CTRL1
 
- VPP_GCLK_CTRL2
 
- VPP_GET_VCC
 
- VPP_HLTI_CTRL
 
- VPP_HOLD_LINES
 
- VPP_HSC_BANK_LENGTH
 
- VPP_HSC_INI_PAT_CTRL
 
- VPP_HSC_PHASE_CTRL
 
- VPP_HSC_PHASE_CTRL1
 
- VPP_HSC_REGION0_PHASE_SLOPE
 
- VPP_HSC_REGION12_STARTP
 
- VPP_HSC_REGION1_PHASE_SLOPE
 
- VPP_HSC_REGION34_STARTP
 
- VPP_HSC_REGION3_PHASE_SLOPE
 
- VPP_HSC_REGION4_ENDP
 
- VPP_HSC_REGION4_PHASE_SLOPE
 
- VPP_HSC_START_PHASE_STEP
 
- VPP_HSHARP_CHROMA_GAIN
 
- VPP_HSHARP_CHROMA_THRESH01
 
- VPP_HSHARP_CHROMA_THRESH23
 
- VPP_HSHARP_CTRL
 
- VPP_HSHARP_LUMA_GAIN
 
- VPP_HSHARP_LUMA_THRESH01
 
- VPP_HSHARP_LUMA_THRESH23
 
- VPP_INPUT_CTRL
 
- VPP_INT_LINE_NUM
 
- VPP_LINE_IN_LENGTH
 
- VPP_MASK
 
- VPP_MATRIX_COEF00_01
 
- VPP_MATRIX_COEF02_10
 
- VPP_MATRIX_COEF11_12
 
- VPP_MATRIX_COEF20_21
 
- VPP_MATRIX_COEF22
 
- VPP_MATRIX_CTRL
 
- VPP_MATRIX_HL_COLOR
 
- VPP_MATRIX_OFFSET0_1
 
- VPP_MATRIX_OFFSET2
 
- VPP_MATRIX_PRE_OFFSET0_1
 
- VPP_MATRIX_PRE_OFFSET2
 
- VPP_MATRIX_PROBE_COLOR
 
- VPP_MATRIX_PROBE_POS
 
- VPP_MINUS_BLACK_LVL_VADJ1_ENABLE
 
- VPP_MISC
 
- VPP_MISC1
 
- VPP_OFF
 
- VPP_OFIFO_SIZE
 
- VPP_OFIFO_SIZE_DEFAULT
 
- VPP_OFIFO_SIZE_MASK
 
- VPP_ON
 
- VPP_OSD1_ALPHA_PREMULT
 
- VPP_OSD1_BLD_H_SCOPE
 
- VPP_OSD1_BLD_V_SCOPE
 
- VPP_OSD1_IN_SIZE
 
- VPP_OSD1_POSTBLEND
 
- VPP_OSD1_PREBLEND
 
- VPP_OSD2_ALPHA_PREMULT
 
- VPP_OSD2_BLD_H_SCOPE
 
- VPP_OSD2_BLD_V_SCOPE
 
- VPP_OSD2_POSTBLEND
 
- VPP_OSD2_PREBLEND
 
- VPP_OSD_HSC_CTRL0
 
- VPP_OSD_HSC_INI_PAT_CTRL
 
- VPP_OSD_HSC_INI_PHASE
 
- VPP_OSD_HSC_PHASE_STEP
 
- VPP_OSD_SCALE_COEF
 
- VPP_OSD_SCALE_COEF_IDX
 
- VPP_OSD_SCI_WH_M1
 
- VPP_OSD_SCO_H_START_END
 
- VPP_OSD_SCO_V_START_END
 
- VPP_OSD_SC_CTRL0
 
- VPP_OSD_SC_DUMMY_DATA
 
- VPP_OSD_VSC_CTRL0
 
- VPP_OSD_VSC_INI_PHASE
 
- VPP_OSD_VSC_PHASE_STEP
 
- VPP_OUT_H_V_SIZE
 
- VPP_PEAKING_DNLP
 
- VPP_PEAKING_GAIN_ADD1
 
- VPP_PEAKING_GAIN_ADD2
 
- VPP_PEAKING_HGAIN
 
- VPP_PEAKING_NLP_1
 
- VPP_PEAKING_NLP_2
 
- VPP_PEAKING_NLP_3
 
- VPP_PEAKING_NLP_4
 
- VPP_PEAKING_NLP_5
 
- VPP_PEAKING_SAT_THD1
 
- VPP_PEAKING_SAT_THD2
 
- VPP_PEAKING_SAT_THD3
 
- VPP_PEAKING_SAT_THD4
 
- VPP_PEAKING_SAT_THD5
 
- VPP_PEAKING_SAT_THD6
 
- VPP_PEAKING_SAT_THD7
 
- VPP_PEAKING_SAT_THD8
 
- VPP_PEAKING_SAT_THD9
 
- VPP_PEAKING_VGAIN
 
- VPP_PIC_IN_HEIGHT
 
- VPP_PORT
 
- VPP_POSTBLEND_CURRENT_XY
 
- VPP_POSTBLEND_ENABLE
 
- VPP_POSTBLEND_HOLD_LINES
 
- VPP_POSTBLEND_H_SIZE
 
- VPP_POSTBLEND_VD1_H_START_END
 
- VPP_POSTBLEND_VD1_V_START_END
 
- VPP_POST_BLEND_BLEND_DUMMY_DATA
 
- VPP_POST_BLEND_DUMMY_ALPHA
 
- VPP_PPS_DUMMY_DATA_MODE
 
- VPP_PREBLEND_CURRENT_XY
 
- VPP_PREBLEND_ENABLE
 
- VPP_PREBLEND_HOLD_LINES
 
- VPP_PREBLEND_H_SIZE
 
- VPP_PREBLEND_VD1_H_START_END
 
- VPP_PREBLEND_VD1_V_START_END
 
- VPP_RDARB_MODE
 
- VPP_RDARB_REQEN_SLV
 
- VPP_SCALE_COEF
 
- VPP_SCALE_COEF_IDX
 
- VPP_SCALE_HORIZONTAL_COEF
 
- VPP_SCO_FIFO_CTRL
 
- VPP_SC_GCLK_CTRL
 
- VPP_SC_HSC_EN_ENABLE
 
- VPP_SC_MISC
 
- VPP_SC_TOP_EN_ENABLE
 
- VPP_SC_VD_EN_ENABLE
 
- VPP_SC_VSC_EN_ENABLE
 
- VPP_SHARP_DEMO_WIN_CTRL1
 
- VPP_SHARP_DEMO_WIN_CTRL2
 
- VPP_SHARP_LIMIT
 
- VPP_SLEEP_CTRL
 
- VPP_SMOKE1_H_START_END
 
- VPP_SMOKE1_VAL
 
- VPP_SMOKE1_V_START_END
 
- VPP_SMOKE2_H_START_END
 
- VPP_SMOKE2_VAL
 
- VPP_SMOKE2_V_START_END
 
- VPP_SMOKE3_H_START_END
 
- VPP_SMOKE3_VAL
 
- VPP_SMOKE3_V_START_END
 
- VPP_SMOKE_CTRL
 
- VPP_VADJ1_MA_MB
 
- VPP_VADJ1_MC_MD
 
- VPP_VADJ1_Y
 
- VPP_VADJ2_MA_MB
 
- VPP_VADJ2_MC_MD
 
- VPP_VADJ2_Y
 
- VPP_VADJ_CTRL
 
- VPP_VCC
 
- VPP_VD1_POSTBLEND
 
- VPP_VD1_PREBLEND
 
- VPP_VD2_HDR_IN_SIZE
 
- VPP_VD2_POSTBLEND
 
- VPP_VD2_PREBLEND
 
- VPP_VDO_MEAS_CTRL
 
- VPP_VDO_MEAS_VS_COUNT_HI
 
- VPP_VDO_MEAS_VS_COUNT_LO
 
- VPP_VE_DEMO_CENTER_BAR
 
- VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH
 
- VPP_VE_ENABLE_CTRL
 
- VPP_VE_H_V_SIZE
 
- VPP_VLTI_CTRL
 
- VPP_VSC_BANK_LENGTH
 
- VPP_VSC_INI_PHASE
 
- VPP_VSC_PHASE_CTRL
 
- VPP_VSC_REGION0_PHASE_SLOPE
 
- VPP_VSC_REGION12_STARTP
 
- VPP_VSC_REGION1_PHASE_SLOPE
 
- VPP_VSC_REGION34_STARTP
 
- VPP_VSC_REGION3_PHASE_SLOPE
 
- VPP_VSC_REGION4_ENDP
 
- VPP_VSC_REGION4_PHASE_SLOPE
 
- VPP_VSC_START_PHASE_STEP
 
- VPP_WRAP_OSD1_MATRIX_CLIP
 
- VPP_WRAP_OSD1_MATRIX_COEF00_01
 
- VPP_WRAP_OSD1_MATRIX_COEF02_10
 
- VPP_WRAP_OSD1_MATRIX_COEF11_12
 
- VPP_WRAP_OSD1_MATRIX_COEF13_14
 
- VPP_WRAP_OSD1_MATRIX_COEF15_25
 
- VPP_WRAP_OSD1_MATRIX_COEF20_21
 
- VPP_WRAP_OSD1_MATRIX_COEF22
 
- VPP_WRAP_OSD1_MATRIX_COEF23_24
 
- VPP_WRAP_OSD1_MATRIX_EN_CTRL
 
- VPP_WRAP_OSD1_MATRIX_OFFSET0_1
 
- VPP_WRAP_OSD1_MATRIX_OFFSET2
 
- VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1
 
- VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2
 
- VPP_WRAP_OSD2_MATRIX_CLIP
 
- VPP_WRAP_OSD2_MATRIX_COEF00_01
 
- VPP_WRAP_OSD2_MATRIX_COEF02_10
 
- VPP_WRAP_OSD2_MATRIX_COEF11_12
 
- VPP_WRAP_OSD2_MATRIX_COEF13_14
 
- VPP_WRAP_OSD2_MATRIX_COEF15_25
 
- VPP_WRAP_OSD2_MATRIX_COEF20_21
 
- VPP_WRAP_OSD2_MATRIX_COEF22
 
- VPP_WRAP_OSD2_MATRIX_COEF23_24
 
- VPP_WRAP_OSD2_MATRIX_EN_CTRL
 
- VPP_WRAP_OSD2_MATRIX_OFFSET0_1
 
- VPP_WRAP_OSD2_MATRIX_OFFSET2
 
- VPP_WRAP_OSD2_MATRIX_PRE_OFFSET0_1
 
- VPP_WRAP_OSD2_MATRIX_PRE_OFFSET2
 
- VPP_WRAP_OSD3_MATRIX_CLIP
 
- VPP_WRAP_OSD3_MATRIX_COEF00_01
 
- VPP_WRAP_OSD3_MATRIX_COEF02_10
 
- VPP_WRAP_OSD3_MATRIX_COEF11_12
 
- VPP_WRAP_OSD3_MATRIX_COEF13_14
 
- VPP_WRAP_OSD3_MATRIX_COEF15_25
 
- VPP_WRAP_OSD3_MATRIX_COEF20_21
 
- VPP_WRAP_OSD3_MATRIX_COEF22
 
- VPP_WRAP_OSD3_MATRIX_COEF23_24
 
- VPP_WRAP_OSD3_MATRIX_EN_CTRL
 
- VPP_WRAP_OSD3_MATRIX_OFFSET0_1
 
- VPP_WRAP_OSD3_MATRIX_OFFSET2
 
- VPP_WRAP_OSD3_MATRIX_PRE_OFFSET0_1
 
- VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2
 
- VPP_WRBAK_CTRL
 
- VPRBRD_ADC_CHANNEL
 
- VPRBRD_ADC_CMD_GET
 
- VPRBRD_EP_IN
 
- VPRBRD_EP_OUT
 
- VPRBRD_GPIOA_CLK_100HZ
 
- VPRBRD_GPIOA_CLK_100KHZ
 
- VPRBRD_GPIOA_CLK_10HZ
 
- VPRBRD_GPIOA_CLK_10KHZ
 
- VPRBRD_GPIOA_CLK_1KHZ
 
- VPRBRD_GPIOA_CLK_1MHZ
 
- VPRBRD_GPIOA_CMD_CONT
 
- VPRBRD_GPIOA_CMD_GETIN
 
- VPRBRD_GPIOA_CMD_PULSE
 
- VPRBRD_GPIOA_CMD_PWM
 
- VPRBRD_GPIOA_CMD_SETIN
 
- VPRBRD_GPIOA_CMD_SETINT
 
- VPRBRD_GPIOA_CMD_SETOUT
 
- VPRBRD_GPIOA_FREQ_DEFAULT
 
- VPRBRD_GPIOB_CMD_SETDIR
 
- VPRBRD_GPIOB_CMD_SETVAL
 
- VPRBRD_I2C_CMD_ADDR
 
- VPRBRD_I2C_CMD_READ
 
- VPRBRD_I2C_CMD_WRITE
 
- VPRBRD_I2C_FREQ_100KHZ
 
- VPRBRD_I2C_FREQ_10KHZ
 
- VPRBRD_I2C_FREQ_1MHZ
 
- VPRBRD_I2C_FREQ_200KHZ
 
- VPRBRD_I2C_FREQ_3MHZ
 
- VPRBRD_I2C_FREQ_400KHZ
 
- VPRBRD_I2C_FREQ_6MHZ
 
- VPRBRD_I2C_FREQ_FAST
 
- VPRBRD_I2C_FREQ_STD
 
- VPRBRD_I2C_MSG_LEN
 
- VPRBRD_USB_REQUEST_ADC
 
- VPRBRD_USB_REQUEST_GPIOA
 
- VPRBRD_USB_REQUEST_GPIOB
 
- VPRBRD_USB_REQUEST_I2C
 
- VPRBRD_USB_REQUEST_I2C_FREQ
 
- VPRBRD_USB_REQUEST_MAJOR
 
- VPRBRD_USB_REQUEST_MINOR
 
- VPRBRD_USB_TIMEOUT_MS
 
- VPRBRD_USB_TYPE_IN
 
- VPRBRD_USB_TYPE_OUT
 
- VPRINTK
 
- VPR_KEY_DEBOUNCE
 
- VPSSBL_BCR
 
- VPSSBL_CCDCMUX
 
- VPSSBL_EVTSEL
 
- VPSSBL_INTSEL
 
- VPSSBL_INTSTAT
 
- VPSSBL_INTSTAT_CCDC_VDINT0
 
- VPSSBL_INTSTAT_CCDC_VDINT1
 
- VPSSBL_INTSTAT_CCDC_VDINT2
 
- VPSSBL_INTSTAT_CFALDINT
 
- VPSSBL_INTSTAT_H3AINT
 
- VPSSBL_INTSTAT_HSSIINT
 
- VPSSBL_INTSTAT_IPIPEIFINT
 
- VPSSBL_INTSTAT_IPIPE_INT0
 
- VPSSBL_INTSTAT_IPIPE_INT1
 
- VPSSBL_INTSTAT_IPIPE_INT2
 
- VPSSBL_INTSTAT_IPIPE_INT3
 
- VPSSBL_INTSTAT_IPIPE_INT4
 
- VPSSBL_INTSTAT_IPIPE_INT5
 
- VPSSBL_INTSTAT_OSDINT
 
- VPSSBL_INTSTAT_VENCINT
 
- VPSSBL_MEMCTRL
 
- VPSSBL_PCR
 
- VPSSBL_PID
 
- VPSSCLK_CLKCTRL
 
- VPSSCLK_PID
 
- VPSS_BL_CLOCK
 
- VPSS_CCDCIN
 
- VPSS_CCDCPG
 
- VPSS_CCDC_CLOCK
 
- VPSS_CFALD_CLOCK
 
- VPSS_CLK_CTRL
 
- VPSS_CLK_CTRL_DACCLKEN
 
- VPSS_CLK_CTRL_VENCCLKEN
 
- VPSS_DACCLKEN_ENABLE
 
- VPSS_FDIF_CLOCK
 
- VPSS_H3A_CLOCK
 
- VPSS_HSSIIN
 
- VPSS_HSSISEL_SHIFT
 
- VPSS_IPIPEIF_CLOCK
 
- VPSS_IPIPE_CLOCK
 
- VPSS_LDC_CLOCK
 
- VPSS_LDC_CLOCK_SEL
 
- VPSS_MUXSEL_EXTCLK_ENABLE
 
- VPSS_OSD_CLOCK_SEL
 
- VPSS_PCLK_INTERNAL
 
- VPSS_PCR_AEW_WBL_0
 
- VPSS_PCR_AF_WBL_0
 
- VPSS_PCR_CCDC_WBL_O
 
- VPSS_PCR_PREV_WBL_0
 
- VPSS_PCR_RSZ1_WBL_0
 
- VPSS_PCR_RSZ2_WBL_0
 
- VPSS_PCR_RSZ3_WBL_0
 
- VPSS_PCR_RSZ4_WBL_0
 
- VPSS_PGLPBK
 
- VPSS_PLLC2SYSCLK5_ENABLE
 
- VPSS_PSYNC_CLOCK_SEL
 
- VPSS_RSZ_CLOCK
 
- VPSS_VENCCLKEN_ENABLE
 
- VPSS_VENC_CLOCK_SEL
 
- VPSS_VPBE_CLOCK
 
- VPSTATUS
 
- VPT
 
- VPTB
 
- VPTE_INDEX_SIZE
 
- VPTE_PGD_SHIFT
 
- VPTE_PMD_SHIFT
 
- VPTE_PUD_SHIFT
 
- VPTE_SIZE
 
- VPU
 
- VPU_AHB_CLK
 
- VPU_ARB4_V1_MMC_CTRL
 
- VPU_ARB4_V2_MMC_CTRL
 
- VPU_AXI_CLK
 
- VPU_BT656_MMC_CTRL
 
- VPU_BUS_CLK
 
- VPU_BUS_CLK_SRC
 
- VPU_CLK_GATE
 
- VPU_COMPATIBLE_G12A
 
- VPU_COMPATIBLE_GXBB
 
- VPU_COMPATIBLE_GXL
 
- VPU_COMPATIBLE_GXM
 
- VPU_CONT_MMC_CTRL
 
- VPU_CXO_CLK
 
- VPU_D2D3_MMC_CTRL
 
- VPU_DI_CHAN2_MMC_CTRL
 
- VPU_DI_DIWR_MMC_CTRL
 
- VPU_DI_IF1_MMC_CTRL
 
- VPU_DI_INP_MMC_CTRL
 
- VPU_DI_MEM_MMC_CTRL
 
- VPU_DI_MTNRD_MMC_CTRL
 
- VPU_DI_MTNWR_MMC_CTRL
 
- VPU_DI_NRWR_MMC_CTRL
 
- VPU_DMEM_EXT0_ADDR
 
- VPU_DMEM_EXT1_ADDR
 
- VPU_DTCM_OFFSET
 
- VPU_DTCM_SIZE
 
- VPU_D_FW
 
- VPU_D_FW_SIZE
 
- VPU_EXT_D_SIZE
 
- VPU_EXT_P_SIZE
 
- VPU_FW_VER_LEN
 
- VPU_HDMI_DATA_OVR
 
- VPU_HDMI_ENCI_DATA_TO_HDMI
 
- VPU_HDMI_ENCP_DATA_TO_HDMI
 
- VPU_HDMI_FMT_CTRL
 
- VPU_HDMI_INV_HSYNC
 
- VPU_HDMI_INV_VSYNC
 
- VPU_HDMI_OUTPUT_CBCRY
 
- VPU_HDMI_OUTPUT_CBYCR
 
- VPU_HDMI_OUTPUT_CRCBY
 
- VPU_HDMI_OUTPUT_CRYCB
 
- VPU_HDMI_OUTPUT_YCBCR
 
- VPU_HDMI_OUTPUT_YCRCB
 
- VPU_HDMI_RD_RATE
 
- VPU_HDMI_SETTING
 
- VPU_HDMI_WR_RATE
 
- VPU_HHI_MEMPD
 
- VPU_IPC_INT
 
- VPU_IPIMSG_DEC_DEINIT_ACK
 
- VPU_IPIMSG_DEC_END_ACK
 
- VPU_IPIMSG_DEC_INIT_ACK
 
- VPU_IPIMSG_DEC_RESET_ACK
 
- VPU_IPIMSG_DEC_START_ACK
 
- VPU_IPIMSG_ENC_DEINIT_DONE
 
- VPU_IPIMSG_ENC_ENCODE_DONE
 
- VPU_IPIMSG_ENC_INIT_DONE
 
- VPU_IPIMSG_ENC_SET_PARAM_DONE
 
- VPU_IPIMSG_VENC_BASE
 
- VPU_ISP_GCLK_CTRL0
 
- VPU_ISP_GCLK_CTRL1
 
- VPU_MAFBC_BLOCK_ID
 
- VPU_MAFBC_BOUNDING_BOX_X_END_S0
 
- VPU_MAFBC_BOUNDING_BOX_X_END_S1
 
- VPU_MAFBC_BOUNDING_BOX_X_END_S2
 
- VPU_MAFBC_BOUNDING_BOX_X_END_S3
 
- VPU_MAFBC_BOUNDING_BOX_X_START_S0
 
- VPU_MAFBC_BOUNDING_BOX_X_START_S1
 
- VPU_MAFBC_BOUNDING_BOX_X_START_S2
 
- VPU_MAFBC_BOUNDING_BOX_X_START_S3
 
- VPU_MAFBC_BOUNDING_BOX_Y_END_S0
 
- VPU_MAFBC_BOUNDING_BOX_Y_END_S1
 
- VPU_MAFBC_BOUNDING_BOX_Y_END_S2
 
- VPU_MAFBC_BOUNDING_BOX_Y_END_S3
 
- VPU_MAFBC_BOUNDING_BOX_Y_START_S0
 
- VPU_MAFBC_BOUNDING_BOX_Y_START_S1
 
- VPU_MAFBC_BOUNDING_BOX_Y_START_S2
 
- VPU_MAFBC_BOUNDING_BOX_Y_START_S3
 
- VPU_MAFBC_BUFFER_HEIGHT_S0
 
- VPU_MAFBC_BUFFER_HEIGHT_S1
 
- VPU_MAFBC_BUFFER_HEIGHT_S2
 
- VPU_MAFBC_BUFFER_HEIGHT_S3
 
- VPU_MAFBC_BUFFER_WIDTH_S0
 
- VPU_MAFBC_BUFFER_WIDTH_S1
 
- VPU_MAFBC_BUFFER_WIDTH_S2
 
- VPU_MAFBC_BUFFER_WIDTH_S3
 
- VPU_MAFBC_COMMAND
 
- VPU_MAFBC_FORMAT_SPECIFIER_S0
 
- VPU_MAFBC_FORMAT_SPECIFIER_S1
 
- VPU_MAFBC_FORMAT_SPECIFIER_S2
 
- VPU_MAFBC_FORMAT_SPECIFIER_S3
 
- VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S0
 
- VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S1
 
- VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S2
 
- VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S3
 
- VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0
 
- VPU_MAFBC_HEADER_BUF_ADDR_LOW_S1
 
- VPU_MAFBC_HEADER_BUF_ADDR_LOW_S2
 
- VPU_MAFBC_HEADER_BUF_ADDR_LOW_S3
 
- VPU_MAFBC_IRQ_CLEAR
 
- VPU_MAFBC_IRQ_MASK
 
- VPU_MAFBC_IRQ_RAW_STATUS
 
- VPU_MAFBC_IRQ_STATUS
 
- VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S0
 
- VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S1
 
- VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S2
 
- VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S3
 
- VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S0
 
- VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S1
 
- VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S2
 
- VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S3
 
- VPU_MAFBC_OUTPUT_BUF_STRIDE_S0
 
- VPU_MAFBC_OUTPUT_BUF_STRIDE_S1
 
- VPU_MAFBC_OUTPUT_BUF_STRIDE_S2
 
- VPU_MAFBC_OUTPUT_BUF_STRIDE_S3
 
- VPU_MAFBC_PREFETCH_CFG_S0
 
- VPU_MAFBC_PREFETCH_CFG_S1
 
- VPU_MAFBC_PREFETCH_CFG_S2
 
- VPU_MAFBC_PREFETCH_CFG_S3
 
- VPU_MAFBC_STATUS
 
- VPU_MAFBC_SURFACE_CFG
 
- VPU_MAPLE_CLK
 
- VPU_MDP_DEINIT_ACK
 
- VPU_MDP_INIT_ACK
 
- VPU_MDP_PROCESS_ACK
 
- VPU_MEMPD
 
- VPU_MEM_PD_REG0
 
- VPU_MEM_PD_REG1
 
- VPU_MISC_CTRL
 
- VPU_OSD1_MMC_CTRL
 
- VPU_OSD2_MMC_CTRL
 
- VPU_OSD3_MMC_CTRL
 
- VPU_OSD4_MMC_CTRL
 
- VPU_PC_REG
 
- VPU_PD
 
- VPU_PLL
 
- VPU_PMEM_EXT0_ADDR
 
- VPU_PMEM_EXT1_ADDR
 
- VPU_PROT1_CLK_GATE
 
- VPU_PROT1_DDR
 
- VPU_PROT1_GEN_CNTL
 
- VPU_PROT1_MMC_CTRL
 
- VPU_PROT1_RBUF_ROOM
 
- VPU_PROT1_REQ_ONOFF
 
- VPU_PROT1_RPT_LOOP
 
- VPU_PROT1_RPT_PAT
 
- VPU_PROT1_STAT_0
 
- VPU_PROT1_STAT_1
 
- VPU_PROT1_STAT_2
 
- VPU_PROT1_X_START_END
 
- VPU_PROT1_Y_LEN_STEP
 
- VPU_PROT1_Y_START_END
 
- VPU_PROT2_CLK_GATE
 
- VPU_PROT2_DDR
 
- VPU_PROT2_GEN_CNTL
 
- VPU_PROT2_MMC_CTRL
 
- VPU_PROT2_RBUF_ROOM
 
- VPU_PROT2_REQ_ONOFF
 
- VPU_PROT2_RPT_LOOP
 
- VPU_PROT2_RPT_PAT
 
- VPU_PROT2_STAT_0
 
- VPU_PROT2_STAT_1
 
- VPU_PROT2_STAT_2
 
- VPU_PROT2_X_START_END
 
- VPU_PROT2_Y_LEN_STEP
 
- VPU_PROT2_Y_START_END
 
- VPU_PROT3_CLK_GATE
 
- VPU_PROT3_DDR
 
- VPU_PROT3_GEN_CNTL
 
- VPU_PROT3_MMC_CTRL
 
- VPU_PROT3_RBUF_ROOM
 
- VPU_PROT3_REQ_ONOFF
 
- VPU_PROT3_RPT_LOOP
 
- VPU_PROT3_RPT_PAT
 
- VPU_PROT3_STAT_0
 
- VPU_PROT3_STAT_1
 
- VPU_PROT3_STAT_2
 
- VPU_PROT3_X_START_END
 
- VPU_PROT3_Y_LEN_STEP
 
- VPU_PROT3_Y_START_END
 
- VPU_PTCM_SIZE
 
- VPU_P_FW
 
- VPU_P_FW_SIZE
 
- VPU_RDARB_MODE_L1C1
 
- VPU_RDARB_MODE_L1C2
 
- VPU_RDARB_MODE_L2C1
 
- VPU_RDARB_SLAVE_TO_MASTER_PORT
 
- VPU_RDMA_MMC_CTRL
 
- VPU_RESET
 
- VPU_RST_DEC
 
- VPU_RST_ENC
 
- VPU_RST_MAX
 
- VPU_RST_MDP
 
- VPU_SLEEP_CLK
 
- VPU_SW_RESET
 
- VPU_TCM_CFG
 
- VPU_TO_HOST
 
- VPU_TVD3D_MMC_CTRL
 
- VPU_TVDVBI_MMC_CTRL
 
- VPU_TVDVBI_VSLATCH_ADDR
 
- VPU_TVDVBI_WRRSP_ADDR
 
- VPU_VD1_MMC_CTRL
 
- VPU_VD2_MMC_CTRL
 
- VPU_VD3_MMC_CTRL
 
- VPU_VDIN0_MMC_CTRL
 
- VPU_VDIN1_MMC_CTRL
 
- VPU_VDIN_ASYNC_HOLD_CTRL
 
- VPU_VDIN_PRE_ARB_CTRL
 
- VPU_VDISP_ASYNC_HOLD_CTRL
 
- VPU_VDISP_PRE_ARB_CTRL
 
- VPU_VDP_CLK
 
- VPU_VIU_VENC_MUX_CTRL
 
- VPU_VPUARB2_ASYNC_HOLD_CTRL
 
- VPU_VPUARB2_PRE_ARB_CTRL
 
- VPU_VPUI
 
- VPU_VPU_PWM_H0
 
- VPU_VPU_PWM_H1
 
- VPU_VPU_PWM_H2
 
- VPU_VPU_PWM_H3
 
- VPU_VPU_PWM_V0
 
- VPU_VPU_PWM_V1
 
- VPU_VPU_PWM_V2
 
- VPU_VPU_PWM_V3
 
- VPU_WDT_REG
 
- VPU_WRARB_MODE_L2C1
 
- VPWR_OVV
 
- VPW_VPW
 
- VPX322_ADDR_ANALOGCONTROL1
 
- VPX322_ADDR_BRIGHTNESS0
 
- VPX322_ADDR_BRIGHTNESS1
 
- VPX322_ADDR_CONTRAST0
 
- VPX322_ADDR_CONTRAST1
 
- VPX322_ADDR_HUE
 
- VPX322_ADDR_SAT
 
- VPX_TIMEOUT_COUNT
 
- VP_A1C
 
- VP_A1T
 
- VP_A1X
 
- VP_A1Y
 
- VP_A1YE
 
- VP_A2C
 
- VP_A2T
 
- VP_A2X
 
- VP_A2Y
 
- VP_A2YE
 
- VP_A3C
 
- VP_A3T
 
- VP_A3X
 
- VP_A3Y
 
- VP_A3YE
 
- VP_AWT
 
- VP_BOT_C_PTR
 
- VP_BOT_Y_PTR
 
- VP_CC1
 
- VP_CC2
 
- VP_CCK
 
- VP_CCM
 
- VP_CCS
 
- VP_CLK_CTRL1_INVERTED
 
- VP_CLK_CTRL1_NON_INVERTED
 
- VP_CLK_CTRL2_DELAYED
 
- VP_CLK_CTRL2_NOT_DELAYED
 
- VP_CLK_SRC
 
- VP_CODEC
 
- VP_COEFF_SIZE
 
- VP_CONFIG_IOCB_TYPE
 
- VP_CRC
 
- VP_CRC32
 
- VP_CTRL
 
- VP_CTRL_DEPOL
 
- VP_CTRL_EVTMODE
 
- VP_CTRL_FLAG
 
- VP_CTRL_HSPOL
 
- VP_CTRL_IOCB_TYPE
 
- VP_CTRL_MSF
 
- VP_CTRL_RGB888
 
- VP_CTRL_VSDELAY
 
- VP_CTRL_VSPOL
 
- VP_CTRL_VTGEN
 
- VP_DCFG
 
- VP_DCFG_CRT_EN
 
- VP_DCFG_CRT_HSYNC_POL
 
- VP_DCFG_CRT_SYNC_SKW
 
- VP_DCFG_CRT_SYNC_SKW_DEFAULT
 
- VP_DCFG_CRT_VSYNC_POL
 
- VP_DCFG_DAC_BL_EN
 
- VP_DCFG_DAC_VREF
 
- VP_DCFG_FP_DATA_EN
 
- VP_DCFG_FP_PWR_EN
 
- VP_DCFG_GV_GAM
 
- VP_DCFG_HSYNC_EN
 
- VP_DCFG_PWR_SEQ_DELAY
 
- VP_DCFG_PWR_SEQ_DELAY_DEFAULT
 
- VP_DCFG_VG_CK
 
- VP_DCFG_VSYNC_EN
 
- VP_DEFAULT_WIN
 
- VP_DST_HEIGHT
 
- VP_DST_H_POSITION
 
- VP_DST_V_POSITION
 
- VP_DST_WIDTH
 
- VP_ENABLE
 
- VP_ENABLE_ON
 
- VP_ENDIAN_MODE
 
- VP_ENDIAN_MODE_LITTLE
 
- VP_FIELD_ID
 
- VP_FILTER
 
- VP_FLAGS
 
- VP_FLAGS_CON_FABRIC
 
- VP_FLAGS_CON_FLOOP
 
- VP_FLAGS_CON_P2P
 
- VP_FLAGS_NAME_VALID
 
- VP_FP_START
 
- VP_GAR
 
- VP_GDR
 
- VP_HTIM1
 
- VP_HTIM1_HBP
 
- VP_HTIM1_HSYNC
 
- VP_HTIM2
 
- VP_HTIM2_HACT
 
- VP_HTIM2_HFP
 
- VP_H_RATIO
 
- VP_IDLE_TIMEOUT
 
- VP_IMG_HSIZE
 
- VP_IMG_SIZE_C
 
- VP_IMG_SIZE_Y
 
- VP_IMG_VSIZE
 
- VP_INVAL
 
- VP_LKUP_BASE
 
- VP_MASK
 
- VP_MASK_VAL
 
- VP_MDET_RX
 
- VP_MDET_RX_VALID_M
 
- VP_MDET_TX_PQM
 
- VP_MDET_TX_PQM_VALID_M
 
- VP_MDET_TX_TCLAN
 
- VP_MDET_TX_TCLAN_VALID_M
 
- VP_MDET_TX_TDPU
 
- VP_MDET_TX_TDPU_VALID_M
 
- VP_MISC
 
- VP_MISC_APWRDN
 
- VP_MISC_BYP_BOTH
 
- VP_MISC_DACPWRDN
 
- VP_MISC_GAM_EN
 
- VP_MODE
 
- VP_MODE_2D_IPC
 
- VP_MODE_FIELD_ID_AUTO_TOGGLING
 
- VP_MODE_FMT_MASK
 
- VP_MODE_LINE_SKIP
 
- VP_MODE_MEM_LINEAR
 
- VP_MODE_MEM_TILED
 
- VP_MODE_NV12
 
- VP_MODE_NV21
 
- VP_MSIX_CONFIG_VECTOR
 
- VP_MSIX_VQ_VECTOR
 
- VP_PAL_COUNT
 
- VP_PAR
 
- VP_PCI_CLASS_ID
 
- VP_PCI_DEVICE_ID
 
- VP_PDR
 
- VP_PER_RATE_CTRL
 
- VP_POLY4_C0_LL
 
- VP_POLY4_Y0_LL
 
- VP_POLY8_Y0_LL
 
- VP_PREVIEW
 
- VP_REG_COUNT
 
- VP_RET_CODE_FATAL
 
- VP_RET_CODE_NOT_FOUND
 
- VP_RET_CODE_NO_MEM
 
- VP_RET_CODE_OK
 
- VP_RET_CODE_RESOURCES
 
- VP_RET_CODE_WRONG_ID
 
- VP_RET_CODE_WWPN
 
- VP_RPT_ID_IOCB_TYPE
 
- VP_RSVD_0
 
- VP_RSVD_1
 
- VP_RSVD_2
 
- VP_RSVD_3
 
- VP_SCL
 
- VP_SHADOW_UPDATE
 
- VP_SHADOW_UPDATE_ENABLE
 
- VP_SLR
 
- VP_SRC_HEIGHT
 
- VP_SRC_H_POSITION
 
- VP_SRC_H_POSITION_VAL
 
- VP_SRC_V_POSITION
 
- VP_SRC_WIDTH
 
- VP_SRESET
 
- VP_SRESET_PROCESSING
 
- VP_STATE_ACB_BMAX
 
- VP_STATE_ACB_GMAX
 
- VP_STATE_ACB_GMIN
 
- VP_STATE_ACB_RMAX
 
- VP_STATE_ACB_RMIN
 
- VP_STATE_AEC_MAX
 
- VP_STATE_FAILED_AECACBINIT
 
- VP_STATE_FAILED_VIDEOINIT
 
- VP_STATE_OK
 
- VP_STATUS
 
- VP_STAT_COMPL
 
- VP_STAT_FAIL
 
- VP_STAT_ID_CHG
 
- VP_STAT_SCR_RJT
 
- VP_STAT_SCR_TO
 
- VP_STAT_SNS_RJT
 
- VP_STAT_SNS_TO
 
- VP_TABLE
 
- VP_TABLE_SZ
 
- VP_TOP_C_PTR
 
- VP_TOP_Y_PTR
 
- VP_TRANXDONE_TIMEOUT
 
- VP_T_CODE_P_INVERTED
 
- VP_T_CODE_P_NON_INVERTED
 
- VP_VCFG
 
- VP_VCFG_VID_EN
 
- VP_VCK
 
- VP_VCM
 
- VP_VCO
 
- VP_VCR
 
- VP_VDC
 
- VP_VDE
 
- VP_VFUEN
 
- VP_VRR
 
- VP_VS
 
- VP_VS_TYPE_F_ITU
 
- VP_VS_TYPE_MASK
 
- VP_VS_TYPE_OFF
 
- VP_VS_TYPE_RESERVED1
 
- VP_VS_TYPE_RESERVED2
 
- VP_VS_TYPE_SC_FID
 
- VP_VS_TYPE_V123
 
- VP_VS_TYPE_VGATE_L
 
- VP_VS_TYPE_V_ITU
 
- VP_VTIM1
 
- VP_VTIM1_VBP
 
- VP_VTIM1_VSYNC
 
- VP_VTIM2
 
- VP_VTIM2_VACT
 
- VP_VTIM2_VFP
 
- VP_VTM
 
- VP_VX
 
- VP_VXS
 
- VP_VY
 
- VP_VYE
 
- VP_VYS
 
- VP_V_RATIO
 
- VQ
 
- VQUIET
 
- VQUIT
 
- VQ_DisplayConfig_AWD
 
- VQ_DisplayConfig_NoneAWD
 
- VQ_GFX_CU
 
- VQ_HIPRIO
 
- VQ_NAME_LEN
 
- VQ_REQUEST
 
- VQ_SIZE
 
- VQ_TYPE
 
- VR
 
- VR00
 
- VR00_BASE_ADDRESS_MASK
 
- VR01
 
- VR01_DITHER_ENABLE
 
- VR01_DVO_BYPASS_ENABLE
 
- VR01_DVO_ENABLE
 
- VR01_LCD_ENABLE
 
- VR01_PANEL_FIT_ENABLE
 
- VR10
 
- VR1000_BAUDBASE
 
- VR1000_CPLD_CTRL2_RAMWEN
 
- VR1000_DM9000_CS
 
- VR1000_IOADDR
 
- VR1000_IRQ_DM9000A
 
- VR1000_IRQ_DM9000N
 
- VR1000_IRQ_IDE0
 
- VR1000_IRQ_IDE1
 
- VR1000_IRQ_SERIAL
 
- VR1000_IRQ_SMALERT
 
- VR1000_IRQ_USBOC
 
- VR1000_PA_CTRL1
 
- VR1000_PA_CTRL2
 
- VR1000_PA_CTRL3
 
- VR1000_PA_CTRL4
 
- VR1000_PA_DM9000
 
- VR1000_PA_IDEPRI
 
- VR1000_PA_IDEPRIAUX
 
- VR1000_PA_IDESEC
 
- VR1000_PA_IDESECAUX
 
- VR1000_PA_PC104_IRQMASK
 
- VR1000_PA_PC104_IRQRAW
 
- VR1000_PA_PC104_IRQREQ
 
- VR1000_PA_SERIAL
 
- VR1000_PA_SRAM
 
- VR1000_SERIAL_MAPBASE
 
- VR1000_VA_ASIXNET
 
- VR1000_VA_CTRL1
 
- VR1000_VA_CTRL2
 
- VR1000_VA_CTRL3
 
- VR1000_VA_CTRL4
 
- VR1000_VA_DM9000
 
- VR1000_VA_IDEPRI
 
- VR1000_VA_IDEPRIAUX
 
- VR1000_VA_IDESEC
 
- VR1000_VA_IDESECAUX
 
- VR1000_VA_ISAIO
 
- VR1000_VA_ISAMEM
 
- VR1000_VA_MULTISPACE
 
- VR1000_VA_PC104_IRQMASK
 
- VR1000_VA_PC104_IRQRAW
 
- VR1000_VA_PC104_IRQREQ
 
- VR1000_VA_SERIAL
 
- VR1000_VA_SUPERIO
 
- VR10_INTERFACE_1X18
 
- VR10_INTERFACE_1X24
 
- VR10_INTERFACE_2X18
 
- VR10_INTERFACE_2X24
 
- VR10_INTERFACE_DEPTH_MASK
 
- VR10_LVDS_ENABLE
 
- VR20
 
- VR21
 
- VR30
 
- VR30_PANEL_ON
 
- VR40
 
- VR40_AUTO_RATIO_ENABLE
 
- VR40_CLOCK_GATING_ENABLE
 
- VR40_ENHANCED_PANEL_FITTING
 
- VR40_HORIZONTAL_INTERP_ENABLE
 
- VR40_STALL_ENABLE
 
- VR40_VERTICAL_INTERP_ENABLE
 
- VR41
 
- VR41_CONF_AD
 
- VR41_CONF_BP
 
- VR41_CONF_CS
 
- VR41_CONF_M16
 
- VR41_CONF_P4K
 
- VR42
 
- VR43
 
- VR80
 
- VR81
 
- VR82
 
- VR83
 
- VR84
 
- VR85
 
- VR86
 
- VR87
 
- VR88
 
- VR8E
 
- VR8E_FORCE_DEFAULT_PANEL
 
- VR8E_PANEL_INTERFACE_CMOS
 
- VR8E_PANEL_INTERFACE_LVDS
 
- VR8E_PANEL_TYPE_MASK
 
- VR8F
 
- VR8F_DISPLAY_CONN
 
- VR8F_POWER_MASK
 
- VR8F_POWER_POS
 
- VR8F_VCH_PRESENT
 
- VRAI_BS
 
- VRAI_CTL
 
- VRAM_ADR_INC
 
- VRAM_GPIO_DetectionInfo
 
- VRAM_MODULE_V4_MISC_BL8
 
- VRAM_MODULE_V4_MISC_BL_MASK
 
- VRAM_MODULE_V4_MISC_DUAL_CS
 
- VRAM_MODULE_V4_MISC_DUAL_RANK
 
- VRAM_MODULE_V4_MISC_RANK_MASK
 
- VRAMx16
 
- VRAMx16ssr
 
- VRATE_CLAMP_ADJ_PCT
 
- VRATE_MAX_PPM
 
- VRATE_MIN
 
- VRATE_MIN_PPM
 
- VRC4173_AC97INT1_IRQ
 
- VRC4173_AC97_IRQ
 
- VRC4173_AIU_IRQ
 
- VRC4173_CASCADE_IRQ
 
- VRC4173_DOZEPIU_IRQ
 
- VRC4173_GIU_IRQ
 
- VRC4173_IRQ
 
- VRC4173_IRQ_BASE
 
- VRC4173_IRQ_LAST
 
- VRC4173_KIU_IRQ
 
- VRC4173_PCMCIA1_IRQ
 
- VRC4173_PCMCIA2_IRQ
 
- VRC4173_PIN
 
- VRC4173_PIU_IRQ
 
- VRC4173_PS2CH1_IRQ
 
- VRC4173_PS2CH2_IRQ
 
- VRC4173_USB_IRQ
 
- VRCONF_MVDD_MASK
 
- VRCONF_MVDD_SHIFT
 
- VRCONF_VDDCI_MASK
 
- VRCONF_VDDCI_SHIFT
 
- VRCONF_VDDC_MASK
 
- VRCONF_VDDC_SHIFT
 
- VRCONF_VDDGFX_MASK
 
- VRCONF_VDDGFX_SHIFT
 
- VRCR
 
- VRCR_DUTF
 
- VRCR_DVTF
 
- VRCR_INIT_VALUE
 
- VRCR_IPEN
 
- VRCR_RIPE
 
- VRCR_RTCPE
 
- VRCR_RUDPE
 
- VRCR_VTDEN
 
- VRCR_VTREN
 
- VRDUNIT_CLOCK_GATE_DISABLE
 
- VREADY_AT_OR_AFTER_VSYNC
 
- VREADY_BEFORE_VSYNC
 
- VREF
 
- VREF_CK
 
- VREF_DDR_ACTIVE_CR
 
- VREF_DDR_PULL_DOWN_MASK
 
- VREF_DDR_PULL_DOWN_REG
 
- VREF_DDR_STDBY_CR
 
- VREF_GAIN_MASK
 
- VREF_MV_BASE
 
- VREF_R
 
- VREG
 
- VREGS
 
- VREG_BC_ALL
 
- VREG_BC_CLK_RST
 
- VREG_BC_PROC
 
- VREG_BC_REF
 
- VREG_CFG__bleeder_ac_MASK
 
- VREG_CFG__bleeder_ac__SHIFT
 
- VREG_CFG__bleeder_en_MASK
 
- VREG_CFG__bleeder_en__SHIFT
 
- VREG_CFG__dpll_cfg_2_MASK
 
- VREG_CFG__dpll_cfg_2__SHIFT
 
- VREG_CFG__is_1p2_MASK
 
- VREG_CFG__is_1p2__SHIFT
 
- VREG_CFG__reg_obs_sel_MASK
 
- VREG_CFG__reg_obs_sel__SHIFT
 
- VREG_CFG__reg_off_hi_MASK
 
- VREG_CFG__reg_off_hi__SHIFT
 
- VREG_CFG__reg_off_lo_MASK
 
- VREG_CFG__reg_off_lo__SHIFT
 
- VREG_CFG__reg_on_mode_MASK
 
- VREG_CFG__reg_on_mode__SHIFT
 
- VREG_CFG__rlad_tap_sel_MASK
 
- VREG_CFG__rlad_tap_sel__SHIFT
 
- VREG_CFG__scale_driver_MASK
 
- VREG_CFG__scale_driver__SHIFT
 
- VREG_CFG__sel_bump_MASK
 
- VREG_CFG__sel_bump__SHIFT
 
- VREG_CFG__sel_rladder_x_MASK
 
- VREG_CFG__sel_rladder_x__SHIFT
 
- VREG_CFG__short_rc_filt_x_MASK
 
- VREG_CFG__short_rc_filt_x__SHIFT
 
- VREG_CFG__vref_pwr_on_MASK
 
- VREG_CFG__vref_pwr_on__SHIFT
 
- VREG_DEDICATED
 
- VREG_GRP
 
- VREG_INFO
 
- VREG_REMAP
 
- VREG_SFX
 
- VREG_STATE
 
- VREG_TRANS
 
- VREG_TYPE
 
- VREG_VOLTAGE
 
- VREG_VOLTAGE_SMPS
 
- VREG_VOLTAGE_SMPS_4030
 
- VREPRINT
 
- VRESTARTING
 
- VRESTRICTED
 
- VRES_60HZ
 
- VRFB_NUM_BUFS
 
- VRFB_PAGE_HEIGHT
 
- VRFB_PAGE_HEIGHT_EXP
 
- VRFB_PAGE_WIDTH
 
- VRFB_PAGE_WIDTH_EXP
 
- VRFB_TX_TIMEOUT
 
- VRHS
 
- VRHUNIT_CLOCK_GATE_DISABLE
 
- VRINGH_IOV_ALLOCATED
 
- VRING_AVAIL_ALIGN_SIZE
 
- VRING_AVAIL_F_NO_INTERRUPT
 
- VRING_CFG_MAC_CTRL_AGGR_EN_LEN
 
- VRING_CFG_MAC_CTRL_AGGR_EN_MSK
 
- VRING_CFG_MAC_CTRL_AGGR_EN_POS
 
- VRING_CFG_MAC_CTRL_LIFETIME_EN_LEN
 
- VRING_CFG_MAC_CTRL_LIFETIME_EN_MSK
 
- VRING_CFG_MAC_CTRL_LIFETIME_EN_POS
 
- VRING_CFG_TO_RESOLUTION_VALUE_LEN
 
- VRING_CFG_TO_RESOLUTION_VALUE_MSK
 
- VRING_CFG_TO_RESOLUTION_VALUE_POS
 
- VRING_DESC_ALIGN_SIZE
 
- VRING_DESC_F_INDIRECT
 
- VRING_DESC_F_NEXT
 
- VRING_DESC_F_WRITE
 
- VRING_PACKED_DESC_F_AVAIL
 
- VRING_PACKED_DESC_F_USED
 
- VRING_PACKED_EVENT_FLAG_DESC
 
- VRING_PACKED_EVENT_FLAG_DISABLE
 
- VRING_PACKED_EVENT_FLAG_ENABLE
 
- VRING_PACKED_EVENT_F_WRAP_CTR
 
- VRING_USED_ALIGN_SIZE
 
- VRING_USED_F_NO_NOTIFY
 
- VRM
 
- VRMA_VSID
 
- VRR_STATE_ACTIVE_FIXED
 
- VRR_STATE_ACTIVE_VARIABLE
 
- VRR_STATE_DISABLED
 
- VRR_STATE_INACTIVE
 
- VRR_STATE_UNSUPPORTED
 
- VRSS_CHANNEL_DEFAULT
 
- VRSS_CHANNEL_MAX
 
- VRSS_SEND_TAB_SIZE
 
- VRS_FIFO_DEPTH
 
- VRTC_CALIBRATION
 
- VRTC_CALIB_INTERVAL
 
- VRTC_ST_MASK
 
- VRTC_ST_SHIFT
 
- VRTC_VRTC_OFFMASK_MASK
 
- VRTC_VRTC_OFFMASK_SHIFT
 
- VRTL_CARRIER_SENSE
 
- VRT_GET_EXTCID_DESC
 
- VRT_GET_GPIE
 
- VRT_GET_GPIO
 
- VRT_GET_I2C0
 
- VRT_GET_I2C1
 
- VRT_GET_I2C2
 
- VRT_GET_REGISTER
 
- VRT_SET_GPIE
 
- VRT_SET_GPIO
 
- VRT_SET_I2C0
 
- VRT_SET_I2C1
 
- VRT_SET_I2C2
 
- VRT_SET_REGISTER
 
- VRUNIT_CLOCK_GATE_DISABLE
 
- VR_CARRY
 
- VR_MAPPING_PLANE_SELECT_MASK
 
- VR_MAPPING_PLANE_SELECT_SHIFT
 
- VR_MAPPING_VR_SELECT_MASK
 
- VR_MAPPING_VR_SELECT_SHIFT
 
- VR_MERGED_WITH_VDDC
 
- VR_MODE_AUTO
 
- VR_MODE_DISABLED
 
- VR_MODE_ECO
 
- VR_MODE_NORMAL
 
- VR_MODE_SWITCH
 
- VR_NEGATE
 
- VR_SELECT
 
- VR_SMIO_PATTERN_1
 
- VR_SMIO_PATTERN_2
 
- VR_STATIC_VOLTAGE
 
- VR_SVI2_PLANE_1
 
- VR_SVI2_PLANE_2
 
- VS
 
- VS18
 
- VS1_STATUS
 
- VS2_STATUS
 
- VS30
 
- VS6624_ACTIVE_PIPE_SETUP
 
- VS6624_ANTI_ALIAS_FILTER
 
- VS6624_ANTI_FLICKER_MODE
 
- VS6624_BAYER_OUT_ALIGN0
 
- VS6624_BAYER_OUT_ALIGN1
 
- VS6624_BC_OFFSET
 
- VS6624_BLANK_DATA_LSB
 
- VS6624_BLANK_DATA_MSB
 
- VS6624_BLANK_FMT
 
- VS6624_CCP_EXT_DATA
 
- VS6624_CHANNEL_ID0
 
- VS6624_CHANNEL_ID1
 
- VS6624_CM_DISABLE
 
- VS6624_CM_HIGH_THR_LSB
 
- VS6624_CM_HIGH_THR_MSB
 
- VS6624_CM_LOW_THR_LSB
 
- VS6624_CM_LOW_THR_MSB
 
- VS6624_CM_MIN_OUT_LSB
 
- VS6624_CM_MIN_OUT_MSB
 
- VS6624_CODE_CK_EN
 
- VS6624_CONTRAST0
 
- VS6624_CONTRAST1
 
- VS6624_CROP_CTRL0
 
- VS6624_CROP_CTRL1
 
- VS6624_CROP_HSIZE0_LSB
 
- VS6624_CROP_HSIZE0_MSB
 
- VS6624_CROP_HSIZE1_LSB
 
- VS6624_CROP_HSIZE1_MSB
 
- VS6624_CROP_HSTART0_LSB
 
- VS6624_CROP_HSTART0_MSB
 
- VS6624_CROP_HSTART1_LSB
 
- VS6624_CROP_HSTART1_MSB
 
- VS6624_CROP_VSIZE0_LSB
 
- VS6624_CROP_VSIZE0_MSB
 
- VS6624_CROP_VSIZE1_LSB
 
- VS6624_CROP_VSIZE1_MSB
 
- VS6624_CROP_VSTART0_LSB
 
- VS6624_CROP_VSTART0_MSB
 
- VS6624_CROP_VSTART1_LSB
 
- VS6624_CROP_VSTART1_MSB
 
- VS6624_CUR_PIPE_SETUP
 
- VS6624_DEV_ID_LSB
 
- VS6624_DEV_ID_MSB
 
- VS6624_DIO_EN
 
- VS6624_DIRECT_ANAL_GAIN_LSB
 
- VS6624_DIRECT_ANAL_GAIN_MSB
 
- VS6624_DIRECT_COARSE_LSB
 
- VS6624_DIRECT_COARSE_MSB
 
- VS6624_DIRECT_DIGI_GAIN_LSB
 
- VS6624_DIRECT_DIGI_GAIN_MSB
 
- VS6624_DIRECT_FINE_LSB
 
- VS6624_DIRECT_FINE_MSB
 
- VS6624_DISABLE_FR_DAMPER
 
- VS6624_EXPO_COMPENSATION
 
- VS6624_EXPO_METER
 
- VS6624_EXPO_MODE
 
- VS6624_EXPO_TIME_DEN
 
- VS6624_EXPO_TIME_LSB
 
- VS6624_EXPO_TIME_MSB
 
- VS6624_EXPO_TIME_NUM
 
- VS6624_EXT_CLK_FREQ_DEN
 
- VS6624_EXT_CLK_FREQ_NUM_LSB
 
- VS6624_EXT_CLK_FREQ_NUM_MSB
 
- VS6624_F2B_BLACK_VAL_LSB
 
- VS6624_F2B_BLACK_VAL_MSB
 
- VS6624_F2B_DISABLE
 
- VS6624_F2B_HIGH_THR_LSB
 
- VS6624_F2B_HIGH_THR_MSB
 
- VS6624_F2B_LOW_THR_LSB
 
- VS6624_F2B_LOW_THR_MSB
 
- VS6624_F2B_MIN_OUT_LSB
 
- VS6624_F2B_MIN_OUT_MSB
 
- VS6624_FLASH_AG_THR_LSB
 
- VS6624_FLASH_AG_THR_MSB
 
- VS6624_FLASH_ANAL_GAIN_LSB
 
- VS6624_FLASH_ANAL_GAIN_MSB
 
- VS6624_FLASH_BG_LSB
 
- VS6624_FLASH_BG_MSB
 
- VS6624_FLASH_COARSE_LSB
 
- VS6624_FLASH_COARSE_MSB
 
- VS6624_FLASH_DIGI_GAIN_LSB
 
- VS6624_FLASH_DIGI_GAIN_MSB
 
- VS6624_FLASH_FINE_LSB
 
- VS6624_FLASH_FINE_MSB
 
- VS6624_FLASH_GG_LSB
 
- VS6624_FLASH_GG_MSB
 
- VS6624_FLASH_GRAB_COMPLETE
 
- VS6624_FLASH_MODE
 
- VS6624_FLASH_OFF_LINE_LSB
 
- VS6624_FLASH_OFF_LINE_MSB
 
- VS6624_FLASH_RECOM
 
- VS6624_FLASH_RG_LSB
 
- VS6624_FLASH_RG_MSB
 
- VS6624_FLICKER_COMPAT
 
- VS6624_FREEZE_AE
 
- VS6624_FR_DEN
 
- VS6624_FR_NUM_LSB
 
- VS6624_FR_NUM_MSB
 
- VS6624_FW_VSN_MAJOR
 
- VS6624_FW_VSN_MINOR
 
- VS6624_GAMMA0
 
- VS6624_GAMMA1
 
- VS6624_GAMMA_MAN_CTRL0
 
- VS6624_GAMMA_MAN_CTRL1
 
- VS6624_GAMMA_PEAK_B0
 
- VS6624_GAMMA_PEAK_B1
 
- VS6624_GAMMA_PEAK_G0
 
- VS6624_GAMMA_PEAK_G1
 
- VS6624_GAMMA_PEAK_R0
 
- VS6624_GAMMA_PEAK_R1
 
- VS6624_GAMMA_UNPEAK_B0
 
- VS6624_GAMMA_UNPEAK_B1
 
- VS6624_GAMMA_UNPEAK_G0
 
- VS6624_GAMMA_UNPEAK_G1
 
- VS6624_GAMMA_UNPEAK_R0
 
- VS6624_GAMMA_UNPEAK_R1
 
- VS6624_HMIRROR0
 
- VS6624_HMIRROR1
 
- VS6624_HSYNC_FALL_H
 
- VS6624_HSYNC_FALL_L
 
- VS6624_HSYNC_RIS_H
 
- VS6624_HSYNC_RIS_L
 
- VS6624_HSYNC_SETUP
 
- VS6624_IMAGE_SIZE0
 
- VS6624_IMAGE_SIZE1
 
- VS6624_IMG_FMT0
 
- VS6624_IMG_FMT1
 
- VS6624_INIT_PIPE_SETUP
 
- VS6624_JACK_FILTER
 
- VS6624_LIGHT_FREQ
 
- VS6624_MAN_BG
 
- VS6624_MAN_GG
 
- VS6624_MAN_HSIZE0_LSB
 
- VS6624_MAN_HSIZE0_MSB
 
- VS6624_MAN_HSIZE1_LSB
 
- VS6624_MAN_HSIZE1_MSB
 
- VS6624_MAN_RG
 
- VS6624_MAN_VSIZE0_LSB
 
- VS6624_MAN_VSIZE0_MSB
 
- VS6624_MAN_VSIZE1_LSB
 
- VS6624_MAN_VSIZE1_MSB
 
- VS6624_MAX_INT_TIME_LSB
 
- VS6624_MAX_INT_TIME_MSB
 
- VS6624_METER_ON
 
- VS6624_MICRO_EN
 
- VS6624_MIN_DAMPER_OUT_LSB
 
- VS6624_MIN_DAMPER_OUT_MSB
 
- VS6624_NORA_DISABLE
 
- VS6624_NORA_DISABLE_NP
 
- VS6624_NORA_HIGH_THR_LSB
 
- VS6624_NORA_HIGH_THR_MSB
 
- VS6624_NORA_LOW_THR_LSB
 
- VS6624_NORA_LOW_THR_MSB
 
- VS6624_NORA_MIN_OUT_LSB
 
- VS6624_NORA_MIN_OUT_MSB
 
- VS6624_NORA_SPLIT_KN
 
- VS6624_NORA_SPLIT_NI
 
- VS6624_NORA_TIGHT_G
 
- VS6624_NORA_USAGE
 
- VS6624_OPF_SP_SETUP
 
- VS6624_OUT_IF
 
- VS6624_PAN_CTRL0
 
- VS6624_PAN_CTRL1
 
- VS6624_PAN_HSTEP0_LSB
 
- VS6624_PAN_HSTEP0_MSB
 
- VS6624_PAN_HSTEP1_LSB
 
- VS6624_PAN_HSTEP1_MSB
 
- VS6624_PAN_VSTEP0_LSB
 
- VS6624_PAN_VSTEP0_MSB
 
- VS6624_PAN_VSTEP1_LSB
 
- VS6624_PAN_VSTEP1_MSB
 
- VS6624_PATCH_VSN_MAJOR
 
- VS6624_PATCH_VSN_MINOR
 
- VS6624_PCLK_EN
 
- VS6624_PCLK_SETUP
 
- VS6624_PEAK_C_DISABLE
 
- VS6624_PEAK_GAIN
 
- VS6624_PEAK_G_DISABLE
 
- VS6624_PEAK_HIGH_THR
 
- VS6624_PEAK_HIGH_THR_C_LSB
 
- VS6624_PEAK_HIGH_THR_C_MSB
 
- VS6624_PEAK_HIGH_THR_G_LSB
 
- VS6624_PEAK_HIGH_THR_G_MSB
 
- VS6624_PEAK_LOW_THR
 
- VS6624_PEAK_LOW_THR_C_LSB
 
- VS6624_PEAK_LOW_THR_C_MSB
 
- VS6624_PEAK_LOW_THR_G_LSB
 
- VS6624_PEAK_LOW_THR_G_MSB
 
- VS6624_PEAK_MIN_OUT_C_LSB
 
- VS6624_PEAK_MIN_OUT_C_MSB
 
- VS6624_PEAK_MIN_OUT_G_LSB
 
- VS6624_PEAK_MIN_OUT_G_MSB
 
- VS6624_RGB_SETUP
 
- VS6624_RYM0_MAN_CTRL
 
- VS6624_RYM0_W00_LSB
 
- VS6624_RYM0_W00_MSB
 
- VS6624_RYM0_W01_LSB
 
- VS6624_RYM0_W01_MSB
 
- VS6624_RYM0_W02_LSB
 
- VS6624_RYM0_W02_MSB
 
- VS6624_RYM0_W10_LSB
 
- VS6624_RYM0_W10_MSB
 
- VS6624_RYM0_W11_LSB
 
- VS6624_RYM0_W11_MSB
 
- VS6624_RYM0_W12_LSB
 
- VS6624_RYM0_W12_MSB
 
- VS6624_RYM0_W20_LSB
 
- VS6624_RYM0_W20_MSB
 
- VS6624_RYM0_W21_LSB
 
- VS6624_RYM0_W21_MSB
 
- VS6624_RYM0_W22_LSB
 
- VS6624_RYM0_W22_MSB
 
- VS6624_RYM0_YINCB_LSB
 
- VS6624_RYM0_YINCB_MSB
 
- VS6624_RYM0_YINCR_LSB
 
- VS6624_RYM0_YINCR_MSB
 
- VS6624_RYM0_YINY_LSB
 
- VS6624_RYM0_YINY_MSB
 
- VS6624_RYM1_MAN_CTRL
 
- VS6624_RYM1_W00_LSB
 
- VS6624_RYM1_W00_MSB
 
- VS6624_RYM1_W01_LSB
 
- VS6624_RYM1_W01_MSB
 
- VS6624_RYM1_W02_LSB
 
- VS6624_RYM1_W02_MSB
 
- VS6624_RYM1_W10_LSB
 
- VS6624_RYM1_W10_MSB
 
- VS6624_RYM1_W11_LSB
 
- VS6624_RYM1_W11_MSB
 
- VS6624_RYM1_W12_LSB
 
- VS6624_RYM1_W12_MSB
 
- VS6624_RYM1_W20_LSB
 
- VS6624_RYM1_W20_MSB
 
- VS6624_RYM1_W21_LSB
 
- VS6624_RYM1_W21_MSB
 
- VS6624_RYM1_W22_LSB
 
- VS6624_RYM1_W22_MSB
 
- VS6624_RYM1_YINCB_LSB
 
- VS6624_RYM1_YINCB_MSB
 
- VS6624_RYM1_YINCR_LSB
 
- VS6624_RYM1_YINCR_MSB
 
- VS6624_RYM1_YINY_LSB
 
- VS6624_RYM1_YINY_MSB
 
- VS6624_SATURATION0
 
- VS6624_SATURATION1
 
- VS6624_SCYTHE_FILTER
 
- VS6624_SENSOR_MODE
 
- VS6624_STABLE
 
- VS6624_STABLE_EXPO
 
- VS6624_STABLE_WB
 
- VS6624_STATE
 
- VS6624_SYNC_CODE_SETUP
 
- VS6624_SYS_CLK_MODE
 
- VS6624_TIME_TO_POWER_DOWN
 
- VS6624_USER_CMD
 
- VS6624_VFLIP0
 
- VS6624_VFLIP1
 
- VS6624_VIEW_LIVE_EN
 
- VS6624_VSYNC_FALL_COARSE_H
 
- VS6624_VSYNC_FALL_COARSE_L
 
- VS6624_VSYNC_FALL_FINE_H
 
- VS6624_VSYNC_FALL_FINE_L
 
- VS6624_VSYNC_RIS_COARSE_H
 
- VS6624_VSYNC_RIS_COARSE_L
 
- VS6624_VSYNC_RIS_FINE_H
 
- VS6624_VSYNC_RIS_FINE_L
 
- VS6624_VSYNC_SETUP
 
- VS6624_WB_MODE
 
- VS6624_YUV_SETUP
 
- VS6624_ZOOM_CTRL0
 
- VS6624_ZOOM_CTRL1
 
- VS6624_ZOOM_HSTEP0_LSB
 
- VS6624_ZOOM_HSTEP0_MSB
 
- VS6624_ZOOM_HSTEP1_LSB
 
- VS6624_ZOOM_HSTEP1_MSB
 
- VS6624_ZOOM_VSTEP0_LSB
 
- VS6624_ZOOM_VSTEP0_MSB
 
- VS6624_ZOOM_VSTEP1_LSB
 
- VS6624_ZOOM_VSTEP1_MSB
 
- VSADR
 
- VSADR_SRCSTRIDE
 
- VSADR_XSTART
 
- VSADR_YSTART
 
- VSAFE5V
 
- VSAFEHPVALTO_ERR
 
- VSALVAGE
 
- VSALVAGING
 
- VSAT
 
- VSAT_CTRL_BYTE
 
- VSA_LEN
 
- VSA_VRC_DATA
 
- VSA_VRC_INDEX
 
- VSA_VR_MEM_SIZE
 
- VSA_VR_SIGNATURE
 
- VSA_VR_UNLOCK
 
- VSB
 
- VSB_16
 
- VSB_8
 
- VSB_CARRIER_FREQ0
 
- VSB_CARRIER_FREQ1
 
- VSB_CARRIER_FREQ2
 
- VSB_CARRIER_FREQ3
 
- VSB_COMM_EXEC_ACTIVE
 
- VSB_COMM_EXEC_HOLD
 
- VSB_COMM_EXEC_STOP
 
- VSB_COMM_EXEC__A
 
- VSB_COMM_EXEC__M
 
- VSB_COMM_EXEC__PRE
 
- VSB_COMM_EXEC__W
 
- VSB_COMM_INT_MSK__A
 
- VSB_COMM_INT_MSK__M
 
- VSB_COMM_INT_MSK__PRE
 
- VSB_COMM_INT_MSK__W
 
- VSB_COMM_INT_REQ_TOP_INT_REQ__B
 
- VSB_COMM_INT_REQ_TOP_INT_REQ__M
 
- VSB_COMM_INT_REQ_TOP_INT_REQ__PRE
 
- VSB_COMM_INT_REQ_TOP_INT_REQ__W
 
- VSB_COMM_INT_REQ__A
 
- VSB_COMM_INT_REQ__M
 
- VSB_COMM_INT_REQ__PRE
 
- VSB_COMM_INT_REQ__W
 
- VSB_COMM_INT_STA__A
 
- VSB_COMM_INT_STA__M
 
- VSB_COMM_INT_STA__PRE
 
- VSB_COMM_INT_STA__W
 
- VSB_COMM_INT_STM__A
 
- VSB_COMM_INT_STM__M
 
- VSB_COMM_INT_STM__PRE
 
- VSB_COMM_INT_STM__W
 
- VSB_COMM_MB__A
 
- VSB_COMM_MB__M
 
- VSB_COMM_MB__PRE
 
- VSB_COMM_MB__W
 
- VSB_EQTAP_RAM_EQTAP_RAM__B
 
- VSB_EQTAP_RAM_EQTAP_RAM__M
 
- VSB_EQTAP_RAM_EQTAP_RAM__PRE
 
- VSB_EQTAP_RAM_EQTAP_RAM__W
 
- VSB_EQTAP_RAM__A
 
- VSB_FCPRE_RAM_FCPRE_RAM__B
 
- VSB_FCPRE_RAM_FCPRE_RAM__M
 
- VSB_FCPRE_RAM_FCPRE_RAM__PRE
 
- VSB_FCPRE_RAM_FCPRE_RAM__W
 
- VSB_FCPRE_RAM__A
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__A
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__M
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__W
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__A
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__M
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__W
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__A
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__M
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__W
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__A
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__M
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__W
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__A
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__M
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__W
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__A
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__M
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__W
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__A
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__M
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__W
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__A
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__M
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__W
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__A
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__M
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__W
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__A
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__M
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__W
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__A
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__M
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__W
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__A
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__M
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__W
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__A
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__M
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__W
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__A
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__M
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__W
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__A
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__M
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__W
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__A
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__M
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__W
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__A
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__M
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__W
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__A
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__M
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__W
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__A
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__M
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__W
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__A
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__M
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__W
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__A
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__M
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__W
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__A
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__M
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__W
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__A
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__M
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__W
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__A
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__M
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__W
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__A
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__M
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__W
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__A
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__M
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__W
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__A
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__M
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__W
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__A
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__M
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__W
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__A
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__M
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__W
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__A
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__M
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__W
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__A
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__M
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__W
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__A
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__M
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__W
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__A
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__M
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__W
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__A
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__M
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__W
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__A
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__M
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__PRE
 
- VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__W
 
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- VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__M
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__PRE
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__W
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__B
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__M
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__PRE
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__W
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__A
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__M
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__PRE
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__W
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__B
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__M
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__PRE
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__W
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__B
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__M
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__PRE
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__W
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__A
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__M
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__PRE
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__W
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__B
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__M
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__PRE
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__W
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__B
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__M
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__PRE
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__W
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__A
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__M
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__PRE
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__W
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__B
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__M
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__PRE
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__W
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__B
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__M
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__PRE
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__W
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__A
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__M
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__PRE
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__W
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__B
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__M
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__PRE
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__W
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__B
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__M
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__PRE
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__W
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__A
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__M
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__PRE
 
- VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__W
 
- VSB_TCMEQ_RAM_TCMEQ_RAM__B
 
- VSB_TCMEQ_RAM_TCMEQ_RAM__M
 
- VSB_TCMEQ_RAM_TCMEQ_RAM__PRE
 
- VSB_TCMEQ_RAM_TCMEQ_RAM__W
 
- VSB_TCMEQ_RAM__A
 
- VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__B
 
- VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__M
 
- VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__PRE
 
- VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__W
 
- VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__B
 
- VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__M
 
- VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__PRE
 
- VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__W
 
- VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__B
 
- VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__M
 
- VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__PRE
 
- VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__W
 
- VSB_TOP_AGC_TRUNCCTRL__A
 
- VSB_TOP_AGC_TRUNCCTRL__M
 
- VSB_TOP_AGC_TRUNCCTRL__PRE
 
- VSB_TOP_AGC_TRUNCCTRL__W
 
- VSB_TOP_BEAGC_DEADZONEINIT__A
 
- VSB_TOP_BEAGC_DEADZONEINIT__M
 
- VSB_TOP_BEAGC_DEADZONEINIT__PRE
 
- VSB_TOP_BEAGC_DEADZONEINIT__W
 
- VSB_TOP_BEAGC_GAINSHIFT__A
 
- VSB_TOP_BEAGC_GAINSHIFT__M
 
- VSB_TOP_BEAGC_GAINSHIFT__PRE
 
- VSB_TOP_BEAGC_GAINSHIFT__W
 
- VSB_TOP_BEAGC_REFLEVEL__A
 
- VSB_TOP_BEAGC_REFLEVEL__M
 
- VSB_TOP_BEAGC_REFLEVEL__PRE
 
- VSB_TOP_BEAGC_REFLEVEL__W
 
- VSB_TOP_BEAGC_REGINIT_BEAGC_RST__B
 
- VSB_TOP_BEAGC_REGINIT_BEAGC_RST__M
 
- VSB_TOP_BEAGC_REGINIT_BEAGC_RST__PRE
 
- VSB_TOP_BEAGC_REGINIT_BEAGC_RST__W
 
- VSB_TOP_BEAGC_REGINIT__A
 
- VSB_TOP_BEAGC_REGINIT__M
 
- VSB_TOP_BEAGC_REGINIT__PRE
 
- VSB_TOP_BEAGC_REGINIT__W
 
- VSB_TOP_BEAGC_SCALE__A
 
- VSB_TOP_BEAGC_SCALE__M
 
- VSB_TOP_BEAGC_SCALE__PRE
 
- VSB_TOP_BEAGC_SCALE__W
 
- VSB_TOP_BEDETCTRL_BYPASS_CSQ__B
 
- VSB_TOP_BEDETCTRL_BYPASS_CSQ__M
 
- VSB_TOP_BEDETCTRL_BYPASS_CSQ__PRE
 
- VSB_TOP_BEDETCTRL_BYPASS_CSQ__W
 
- VSB_TOP_BEDETCTRL_BYPASS_DMP__B
 
- VSB_TOP_BEDETCTRL_BYPASS_DMP__M
 
- VSB_TOP_BEDETCTRL_BYPASS_DMP__PRE
 
- VSB_TOP_BEDETCTRL_BYPASS_DMP__W
 
- VSB_TOP_BEDETCTRL_BYPASS_DSQ__B
 
- VSB_TOP_BEDETCTRL_BYPASS_DSQ__M
 
- VSB_TOP_BEDETCTRL_BYPASS_DSQ__PRE
 
- VSB_TOP_BEDETCTRL_BYPASS_DSQ__W
 
- VSB_TOP_BEDETCTRL_BYPASS_PSQ__B
 
- VSB_TOP_BEDETCTRL_BYPASS_PSQ__M
 
- VSB_TOP_BEDETCTRL_BYPASS_PSQ__PRE
 
- VSB_TOP_BEDETCTRL_BYPASS_PSQ__W
 
- VSB_TOP_BEDETCTRL_CYOFFSEL__B
 
- VSB_TOP_BEDETCTRL_CYOFFSEL__M
 
- VSB_TOP_BEDETCTRL_CYOFFSEL__PRE
 
- VSB_TOP_BEDETCTRL_CYOFFSEL__W
 
- VSB_TOP_BEDETCTRL_DATAOFFSEL__B
 
- VSB_TOP_BEDETCTRL_DATAOFFSEL__M
 
- VSB_TOP_BEDETCTRL_DATAOFFSEL__PRE
 
- VSB_TOP_BEDETCTRL_DATAOFFSEL__W
 
- VSB_TOP_BEDETCTRL_MIXRATIO__B
 
- VSB_TOP_BEDETCTRL_MIXRATIO__M
 
- VSB_TOP_BEDETCTRL_MIXRATIO__PRE
 
- VSB_TOP_BEDETCTRL_MIXRATIO__W
 
- VSB_TOP_BEDETCTRL__A
 
- VSB_TOP_BEDETCTRL__M
 
- VSB_TOP_BEDETCTRL__PRE
 
- VSB_TOP_BEDETCTRL__W
 
- VSB_TOP_BNCLPNUM__A
 
- VSB_TOP_BNCLPNUM__M
 
- VSB_TOP_BNCLPNUM__PRE
 
- VSB_TOP_BNCLPNUM__W
 
- VSB_TOP_BNFIELD__A
 
- VSB_TOP_BNFIELD__M
 
- VSB_TOP_BNFIELD__PRE
 
- VSB_TOP_BNFIELD__W
 
- VSB_TOP_BNSQERR__A
 
- VSB_TOP_BNSQERR__M
 
- VSB_TOP_BNSQERR__PRE
 
- VSB_TOP_BNSQERR__W
 
- VSB_TOP_BNTHRESH__A
 
- VSB_TOP_BNTHRESH__M
 
- VSB_TOP_BNTHRESH__PRE
 
- VSB_TOP_BNTHRESH__W
 
- VSB_TOP_CENTROID_FINE_DELAY__A
 
- VSB_TOP_CENTROID_FINE_DELAY__M
 
- VSB_TOP_CENTROID_FINE_DELAY__PRE
 
- VSB_TOP_CENTROID_FINE_DELAY__W
 
- VSB_TOP_CENTROID_SMACH_DELAY__A
 
- VSB_TOP_CENTROID_SMACH_DELAY__M
 
- VSB_TOP_CENTROID_SMACH_DELAY__PRE
 
- VSB_TOP_CENTROID_SMACH_DELAY__W
 
- VSB_TOP_CFAGC_DEADZONEINIT__A
 
- VSB_TOP_CFAGC_DEADZONEINIT__M
 
- VSB_TOP_CFAGC_DEADZONEINIT__PRE
 
- VSB_TOP_CFAGC_DEADZONEINIT__W
 
- VSB_TOP_CFAGC_GAINSHIFT__A
 
- VSB_TOP_CFAGC_GAINSHIFT__M
 
- VSB_TOP_CFAGC_GAINSHIFT__PRE
 
- VSB_TOP_CFAGC_GAINSHIFT__W
 
- VSB_TOP_CFAGC_REFLEVEL__A
 
- VSB_TOP_CFAGC_REFLEVEL__M
 
- VSB_TOP_CFAGC_REFLEVEL__PRE
 
- VSB_TOP_CFAGC_REFLEVEL__W
 
- VSB_TOP_CFAGC_REGINIT_CFAGC_RST__B
 
- VSB_TOP_CFAGC_REGINIT_CFAGC_RST__M
 
- VSB_TOP_CFAGC_REGINIT_CFAGC_RST__PRE
 
- VSB_TOP_CFAGC_REGINIT_CFAGC_RST__W
 
- VSB_TOP_CFAGC_REGINIT__A
 
- VSB_TOP_CFAGC_REGINIT__M
 
- VSB_TOP_CFAGC_REGINIT__PRE
 
- VSB_TOP_CFAGC_REGINIT__W
 
- VSB_TOP_CFAGC_SCALE__A
 
- VSB_TOP_CFAGC_SCALE__M
 
- VSB_TOP_CFAGC_SCALE__PRE
 
- VSB_TOP_CFAGC_SCALE__W
 
- VSB_TOP_CKGN1ACQ__A
 
- VSB_TOP_CKGN1ACQ__M
 
- VSB_TOP_CKGN1ACQ__PRE
 
- VSB_TOP_CKGN1ACQ__W
 
- VSB_TOP_CKGN1TRK__A
 
- VSB_TOP_CKGN1TRK__M
 
- VSB_TOP_CKGN1TRK__PRE
 
- VSB_TOP_CKGN1TRK__W
 
- VSB_TOP_CKGN2ACQ__A
 
- VSB_TOP_CKGN2ACQ__M
 
- VSB_TOP_CKGN2ACQ__PRE
 
- VSB_TOP_CKGN2ACQ__W
 
- VSB_TOP_CKGN2TRK__A
 
- VSB_TOP_CKGN2TRK__M
 
- VSB_TOP_CKGN2TRK__PRE
 
- VSB_TOP_CKGN2TRK__W
 
- VSB_TOP_CKGN3__A
 
- VSB_TOP_CKGN3__M
 
- VSB_TOP_CKGN3__PRE
 
- VSB_TOP_CKGN3__W
 
- VSB_TOP_CKTRKONCTL__A
 
- VSB_TOP_CKTRKONCTL__M
 
- VSB_TOP_CKTRKONCTL__PRE
 
- VSB_TOP_CKTRKONCTL__W
 
- VSB_TOP_CLOCKACCUM__A
 
- VSB_TOP_CLOCKACCUM__M
 
- VSB_TOP_CLOCKACCUM__PRE
 
- VSB_TOP_CLOCKACCUM__W
 
- VSB_TOP_CLPLASTNUM__A
 
- VSB_TOP_CLPLASTNUM__M
 
- VSB_TOP_CLPLASTNUM__PRE
 
- VSB_TOP_CLPLASTNUM__W
 
- VSB_TOP_COMM_EXEC_ACTIVE
 
- VSB_TOP_COMM_EXEC_HOLD
 
- VSB_TOP_COMM_EXEC_STOP
 
- VSB_TOP_COMM_EXEC__A
 
- VSB_TOP_COMM_EXEC__M
 
- VSB_TOP_COMM_EXEC__PRE
 
- VSB_TOP_COMM_EXEC__W
 
- VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__B
 
- VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__M
 
- VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__PRE
 
- VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__W
 
- VSB_TOP_COMM_INT_MSK_LOCK_MSK__B
 
- VSB_TOP_COMM_INT_MSK_LOCK_MSK__M
 
- VSB_TOP_COMM_INT_MSK_LOCK_MSK__PRE
 
- VSB_TOP_COMM_INT_MSK_LOCK_MSK__W
 
- VSB_TOP_COMM_INT_MSK_MERSER_MSK__B
 
- VSB_TOP_COMM_INT_MSK_MERSER_MSK__M
 
- VSB_TOP_COMM_INT_MSK_MERSER_MSK__PRE
 
- VSB_TOP_COMM_INT_MSK_MERSER_MSK__W
 
- VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__B
 
- VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__M
 
- VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__PRE
 
- VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__W
 
- VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__B
 
- VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__M
 
- VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__PRE
 
- VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__W
 
- VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__B
 
- VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__M
 
- VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__PRE
 
- VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__W
 
- VSB_TOP_COMM_INT_MSK__A
 
- VSB_TOP_COMM_INT_MSK__M
 
- VSB_TOP_COMM_INT_MSK__PRE
 
- VSB_TOP_COMM_INT_MSK__W
 
- VSB_TOP_COMM_INT_REQ__A
 
- VSB_TOP_COMM_INT_REQ__M
 
- VSB_TOP_COMM_INT_REQ__PRE
 
- VSB_TOP_COMM_INT_REQ__W
 
- VSB_TOP_COMM_INT_STA_FIELD_INT_STA__B
 
- VSB_TOP_COMM_INT_STA_FIELD_INT_STA__M
 
- VSB_TOP_COMM_INT_STA_FIELD_INT_STA__PRE
 
- VSB_TOP_COMM_INT_STA_FIELD_INT_STA__W
 
- VSB_TOP_COMM_INT_STA_LOCK_STA__B
 
- VSB_TOP_COMM_INT_STA_LOCK_STA__M
 
- VSB_TOP_COMM_INT_STA_LOCK_STA__PRE
 
- VSB_TOP_COMM_INT_STA_LOCK_STA__W
 
- VSB_TOP_COMM_INT_STA_MERSER_STA__B
 
- VSB_TOP_COMM_INT_STA_MERSER_STA__M
 
- VSB_TOP_COMM_INT_STA_MERSER_STA__PRE
 
- VSB_TOP_COMM_INT_STA_MERSER_STA__W
 
- VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__B
 
- VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__M
 
- VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__PRE
 
- VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__W
 
- VSB_TOP_COMM_INT_STA_TAPREADER_STA__B
 
- VSB_TOP_COMM_INT_STA_TAPREADER_STA__M
 
- VSB_TOP_COMM_INT_STA_TAPREADER_STA__PRE
 
- VSB_TOP_COMM_INT_STA_TAPREADER_STA__W
 
- VSB_TOP_COMM_INT_STA_UNLOCK_STA__B
 
- VSB_TOP_COMM_INT_STA_UNLOCK_STA__M
 
- VSB_TOP_COMM_INT_STA_UNLOCK_STA__PRE
 
- VSB_TOP_COMM_INT_STA_UNLOCK_STA__W
 
- VSB_TOP_COMM_INT_STA__A
 
- VSB_TOP_COMM_INT_STA__M
 
- VSB_TOP_COMM_INT_STA__PRE
 
- VSB_TOP_COMM_INT_STA__W
 
- VSB_TOP_COMM_INT_STM_FIELD_INT_STM__B
 
- VSB_TOP_COMM_INT_STM_FIELD_INT_STM__M
 
- VSB_TOP_COMM_INT_STM_FIELD_INT_STM__PRE
 
- VSB_TOP_COMM_INT_STM_FIELD_INT_STM__W
 
- VSB_TOP_COMM_INT_STM_LOCK_STM__B
 
- VSB_TOP_COMM_INT_STM_LOCK_STM__M
 
- VSB_TOP_COMM_INT_STM_LOCK_STM__PRE
 
- VSB_TOP_COMM_INT_STM_LOCK_STM__W
 
- VSB_TOP_COMM_INT_STM_MERSER_STM__B
 
- VSB_TOP_COMM_INT_STM_MERSER_STM__M
 
- VSB_TOP_COMM_INT_STM_MERSER_STM__PRE
 
- VSB_TOP_COMM_INT_STM_MERSER_STM__W
 
- VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__B
 
- VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__M
 
- VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__PRE
 
- VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__W
 
- VSB_TOP_COMM_INT_STM_TAPREADER_STM__B
 
- VSB_TOP_COMM_INT_STM_TAPREADER_STM__M
 
- VSB_TOP_COMM_INT_STM_TAPREADER_STM__PRE
 
- VSB_TOP_COMM_INT_STM_TAPREADER_STM__W
 
- VSB_TOP_COMM_INT_STM_UNLOCK_STM__B
 
- VSB_TOP_COMM_INT_STM_UNLOCK_STM__M
 
- VSB_TOP_COMM_INT_STM_UNLOCK_STM__PRE
 
- VSB_TOP_COMM_INT_STM_UNLOCK_STM__W
 
- VSB_TOP_COMM_INT_STM__A
 
- VSB_TOP_COMM_INT_STM__M
 
- VSB_TOP_COMM_INT_STM__PRE
 
- VSB_TOP_COMM_INT_STM__W
 
- VSB_TOP_COMM_MB_CTL_CTL_OFF
 
- VSB_TOP_COMM_MB_CTL_CTL_ON
 
- VSB_TOP_COMM_MB_CTL__B
 
- VSB_TOP_COMM_MB_CTL__M
 
- VSB_TOP_COMM_MB_CTL__PRE
 
- VSB_TOP_COMM_MB_CTL__W
 
- VSB_TOP_COMM_MB_MUX_CTL__B
 
- VSB_TOP_COMM_MB_MUX_CTL__M
 
- VSB_TOP_COMM_MB_MUX_CTL__PRE
 
- VSB_TOP_COMM_MB_MUX_CTL__W
 
- VSB_TOP_COMM_MB_MUX_OBS_VSB_DFE_1
 
- VSB_TOP_COMM_MB_MUX_OBS_VSB_DFE_2
 
- VSB_TOP_COMM_MB_MUX_OBS_VSB_FEC
 
- VSB_TOP_COMM_MB_MUX_OBS_VSB_FFE_1
 
- VSB_TOP_COMM_MB_MUX_OBS_VSB_FFE_2
 
- VSB_TOP_COMM_MB_MUX_OBS_VSB_IQM
 
- VSB_TOP_COMM_MB_MUX_OBS_VSB_IQM_AMPLITUDE
 
- VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_1
 
- VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_2
 
- VSB_TOP_COMM_MB_MUX_OBS__B
 
- VSB_TOP_COMM_MB_MUX_OBS__M
 
- VSB_TOP_COMM_MB_MUX_OBS__PRE
 
- VSB_TOP_COMM_MB_MUX_OBS__W
 
- VSB_TOP_COMM_MB_OBS_OBS_OFF
 
- VSB_TOP_COMM_MB_OBS_OBS_ON
 
- VSB_TOP_COMM_MB_OBS__B
 
- VSB_TOP_COMM_MB_OBS__M
 
- VSB_TOP_COMM_MB_OBS__PRE
 
- VSB_TOP_COMM_MB_OBS__W
 
- VSB_TOP_COMM_MB__A
 
- VSB_TOP_COMM_MB__M
 
- VSB_TOP_COMM_MB__PRE
 
- VSB_TOP_COMM_MB__W
 
- VSB_TOP_CORINGSEL__A
 
- VSB_TOP_CORINGSEL__M
 
- VSB_TOP_CORINGSEL__PRE
 
- VSB_TOP_CORINGSEL__W
 
- VSB_TOP_CTST__A
 
- VSB_TOP_CTST__M
 
- VSB_TOP_CTST__PRE
 
- VSB_TOP_CTST__W
 
- VSB_TOP_CURRENTSEGLOCAT__A
 
- VSB_TOP_CURRENTSEGLOCAT__M
 
- VSB_TOP_CURRENTSEGLOCAT__PRE
 
- VSB_TOP_CURRENTSEGLOCAT__W
 
- VSB_TOP_CYGN1ACQ__A
 
- VSB_TOP_CYGN1ACQ__M
 
- VSB_TOP_CYGN1ACQ__PRE
 
- VSB_TOP_CYGN1ACQ__W
 
- VSB_TOP_CYGN1TRK__A
 
- VSB_TOP_CYGN1TRK__M
 
- VSB_TOP_CYGN1TRK__PRE
 
- VSB_TOP_CYGN1TRK__W
 
- VSB_TOP_CYGN2ACQ__A
 
- VSB_TOP_CYGN2ACQ__M
 
- VSB_TOP_CYGN2ACQ__PRE
 
- VSB_TOP_CYGN2ACQ__W
 
- VSB_TOP_CYGN2TRK__A
 
- VSB_TOP_CYGN2TRK__M
 
- VSB_TOP_CYGN2TRK__PRE
 
- VSB_TOP_CYGN2TRK__W
 
- VSB_TOP_CYGN3__A
 
- VSB_TOP_CYGN3__M
 
- VSB_TOP_CYGN3__PRE
 
- VSB_TOP_CYGN3__W
 
- VSB_TOP_CYSMSTATES_EQST__B
 
- VSB_TOP_CYSMSTATES_EQST__M
 
- VSB_TOP_CYSMSTATES_EQST__PRE
 
- VSB_TOP_CYSMSTATES_EQST__W
 
- VSB_TOP_CYSMSTATES_SYSST__B
 
- VSB_TOP_CYSMSTATES_SYSST__M
 
- VSB_TOP_CYSMSTATES_SYSST__PRE
 
- VSB_TOP_CYSMSTATES_SYSST__W
 
- VSB_TOP_CYSMSTATES__A
 
- VSB_TOP_CYSMSTATES__M
 
- VSB_TOP_CYSMSTATES__PRE
 
- VSB_TOP_CYSMSTATES__W
 
- VSB_TOP_CYTRKONCTL__A
 
- VSB_TOP_CYTRKONCTL__M
 
- VSB_TOP_CYTRKONCTL__PRE
 
- VSB_TOP_CYTRKONCTL__W
 
- VSB_TOP_DCRMVACUMI__A
 
- VSB_TOP_DCRMVACUMI__M
 
- VSB_TOP_DCRMVACUMI__PRE
 
- VSB_TOP_DCRMVACUMI__W
 
- VSB_TOP_DCRMVACUMQ__A
 
- VSB_TOP_DCRMVACUMQ__M
 
- VSB_TOP_DCRMVACUMQ__PRE
 
- VSB_TOP_DCRMVACUMQ__W
 
- VSB_TOP_DLOCKACCUM__A
 
- VSB_TOP_DLOCKACCUM__M
 
- VSB_TOP_DLOCKACCUM__PRE
 
- VSB_TOP_DLOCKACCUM__W
 
- VSB_TOP_EQCTRL_CMAGAIN__B
 
- VSB_TOP_EQCTRL_CMAGAIN__M
 
- VSB_TOP_EQCTRL_CMAGAIN__PRE
 
- VSB_TOP_EQCTRL_CMAGAIN__W
 
- VSB_TOP_EQCTRL_ODAGCGO__B
 
- VSB_TOP_EQCTRL_ODAGCGO__M
 
- VSB_TOP_EQCTRL_ODAGCGO__PRE
 
- VSB_TOP_EQCTRL_ODAGCGO__W
 
- VSB_TOP_EQCTRL_OPTGAIN__B
 
- VSB_TOP_EQCTRL_OPTGAIN__M
 
- VSB_TOP_EQCTRL_OPTGAIN__PRE
 
- VSB_TOP_EQCTRL_OPTGAIN__W
 
- VSB_TOP_EQCTRL_ORCANCMAEN__B
 
- VSB_TOP_EQCTRL_ORCANCMAEN__M
 
- VSB_TOP_EQCTRL_ORCANCMAEN__PRE
 
- VSB_TOP_EQCTRL_ORCANCMAEN__W
 
- VSB_TOP_EQCTRL_STASSIGNEN__B
 
- VSB_TOP_EQCTRL_STASSIGNEN__M
 
- VSB_TOP_EQCTRL_STASSIGNEN__PRE
 
- VSB_TOP_EQCTRL_STASSIGNEN__W
 
- VSB_TOP_EQCTRL_TAPRAMWRTEN__B
 
- VSB_TOP_EQCTRL_TAPRAMWRTEN__M
 
- VSB_TOP_EQCTRL_TAPRAMWRTEN__PRE
 
- VSB_TOP_EQCTRL_TAPRAMWRTEN__W
 
- VSB_TOP_EQCTRL__A
 
- VSB_TOP_EQCTRL__M
 
- VSB_TOP_EQCTRL__PRE
 
- VSB_TOP_EQCTRL__W
 
- VSB_TOP_EQSMDDM1CTRL_DDMEN1__B
 
- VSB_TOP_EQSMDDM1CTRL_DDMEN1__M
 
- VSB_TOP_EQSMDDM1CTRL_DDMEN1__PRE
 
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- VSB_TOP_EQSMDDM1CTRL_DDMEN2__M
 
- VSB_TOP_EQSMDDM1CTRL_DDMEN2__PRE
 
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- VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__M
 
- VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__PRE
 
- VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__W
 
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- VSB_TOP_EQSMDDM1CTRL_PARAINITEN__M
 
- VSB_TOP_EQSMDDM1CTRL_PARAINITEN__PRE
 
- VSB_TOP_EQSMDDM1CTRL_PARAINITEN__W
 
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- VSB_TOP_EQSMDDM1CTRL_RCAON__M
 
- VSB_TOP_EQSMDDM1CTRL_RCAON__PRE
 
- VSB_TOP_EQSMDDM1CTRL_RCAON__W
 
- VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__B
 
- VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__M
 
- VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__PRE
 
- VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__W
 
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- VSB_TOP_EQSMDDM1CTRL__PRE
 
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- VSB_TOP_EQSMDDM2CTRL_DDMEN1__M
 
- VSB_TOP_EQSMDDM2CTRL_DDMEN1__PRE
 
- VSB_TOP_EQSMDDM2CTRL_DDMEN1__W
 
- VSB_TOP_EQSMDDM2CTRL_DDMEN2__B
 
- VSB_TOP_EQSMDDM2CTRL_DDMEN2__M
 
- VSB_TOP_EQSMDDM2CTRL_DDMEN2__PRE
 
- VSB_TOP_EQSMDDM2CTRL_DDMEN2__W
 
- VSB_TOP_EQSMDDM2CTRL_DFEON__B
 
- VSB_TOP_EQSMDDM2CTRL_DFEON__M
 
- VSB_TOP_EQSMDDM2CTRL_DFEON__PRE
 
- VSB_TOP_EQSMDDM2CTRL_DFEON__W
 
- VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__B
 
- VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__M
 
- VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__PRE
 
- VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__W
 
- VSB_TOP_EQSMDDM2CTRL_PARAINITEN__B
 
- VSB_TOP_EQSMDDM2CTRL_PARAINITEN__M
 
- VSB_TOP_EQSMDDM2CTRL_PARAINITEN__PRE
 
- VSB_TOP_EQSMDDM2CTRL_PARAINITEN__W
 
- VSB_TOP_EQSMDDM2CTRL_RCAON__B
 
- VSB_TOP_EQSMDDM2CTRL_RCAON__M
 
- VSB_TOP_EQSMDDM2CTRL_RCAON__PRE
 
- VSB_TOP_EQSMDDM2CTRL_RCAON__W
 
- VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__B
 
- VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__M
 
- VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__PRE
 
- VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__W
 
- VSB_TOP_EQSMDDM2CTRL__A
 
- VSB_TOP_EQSMDDM2CTRL__M
 
- VSB_TOP_EQSMDDM2CTRL__PRE
 
- VSB_TOP_EQSMDDM2CTRL__W
 
- VSB_TOP_EQSMRCA1CTRL_DDMEN1__B
 
- VSB_TOP_EQSMRCA1CTRL_DDMEN1__M
 
- VSB_TOP_EQSMRCA1CTRL_DDMEN1__PRE
 
- VSB_TOP_EQSMRCA1CTRL_DDMEN1__W
 
- VSB_TOP_EQSMRCA1CTRL_DDMEN2__B
 
- VSB_TOP_EQSMRCA1CTRL_DDMEN2__M
 
- VSB_TOP_EQSMRCA1CTRL_DDMEN2__PRE
 
- VSB_TOP_EQSMRCA1CTRL_DDMEN2__W
 
- VSB_TOP_EQSMRCA1CTRL_DFEON__B
 
- VSB_TOP_EQSMRCA1CTRL_DFEON__M
 
- VSB_TOP_EQSMRCA1CTRL_DFEON__PRE
 
- VSB_TOP_EQSMRCA1CTRL_DFEON__W
 
- VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__B
 
- VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__M
 
- VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__PRE
 
- VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__W
 
- VSB_TOP_EQSMRCA1CTRL_PARAINITEN__B
 
- VSB_TOP_EQSMRCA1CTRL_PARAINITEN__M
 
- VSB_TOP_EQSMRCA1CTRL_PARAINITEN__PRE
 
- VSB_TOP_EQSMRCA1CTRL_PARAINITEN__W
 
- VSB_TOP_EQSMRCA1CTRL_RCAON__B
 
- VSB_TOP_EQSMRCA1CTRL_RCAON__M
 
- VSB_TOP_EQSMRCA1CTRL_RCAON__PRE
 
- VSB_TOP_EQSMRCA1CTRL_RCAON__W
 
- VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__B
 
- VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__M
 
- VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__PRE
 
- VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__W
 
- VSB_TOP_EQSMRCA1CTRL__A
 
- VSB_TOP_EQSMRCA1CTRL__M
 
- VSB_TOP_EQSMRCA1CTRL__PRE
 
- VSB_TOP_EQSMRCA1CTRL__W
 
- VSB_TOP_EQSMRCA2CTRL_DDMEN1__B
 
- VSB_TOP_EQSMRCA2CTRL_DDMEN1__M
 
- VSB_TOP_EQSMRCA2CTRL_DDMEN1__PRE
 
- VSB_TOP_EQSMRCA2CTRL_DDMEN1__W
 
- VSB_TOP_EQSMRCA2CTRL_DDMEN2__B
 
- VSB_TOP_EQSMRCA2CTRL_DDMEN2__M
 
- VSB_TOP_EQSMRCA2CTRL_DDMEN2__PRE
 
- VSB_TOP_EQSMRCA2CTRL_DDMEN2__W
 
- VSB_TOP_EQSMRCA2CTRL_DFEON__B
 
- VSB_TOP_EQSMRCA2CTRL_DFEON__M
 
- VSB_TOP_EQSMRCA2CTRL_DFEON__PRE
 
- VSB_TOP_EQSMRCA2CTRL_DFEON__W
 
- VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__B
 
- VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__M
 
- VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__PRE
 
- VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__W
 
- VSB_TOP_EQSMRCA2CTRL_PARAINITEN__B
 
- VSB_TOP_EQSMRCA2CTRL_PARAINITEN__M
 
- VSB_TOP_EQSMRCA2CTRL_PARAINITEN__PRE
 
- VSB_TOP_EQSMRCA2CTRL_PARAINITEN__W
 
- VSB_TOP_EQSMRCA2CTRL_RCAON__B
 
- VSB_TOP_EQSMRCA2CTRL_RCAON__M
 
- VSB_TOP_EQSMRCA2CTRL_RCAON__PRE
 
- VSB_TOP_EQSMRCA2CTRL_RCAON__W
 
- VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__B
 
- VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__M
 
- VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__PRE
 
- VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__W
 
- VSB_TOP_EQSMRCA2CTRL__A
 
- VSB_TOP_EQSMRCA2CTRL__M
 
- VSB_TOP_EQSMRCA2CTRL__PRE
 
- VSB_TOP_EQSMRCA2CTRL__W
 
- VSB_TOP_EQSMRSTCTRL_DDMEN1__B
 
- VSB_TOP_EQSMRSTCTRL_DDMEN1__M
 
- VSB_TOP_EQSMRSTCTRL_DDMEN1__PRE
 
- VSB_TOP_EQSMRSTCTRL_DDMEN1__W
 
- VSB_TOP_EQSMRSTCTRL_DDMEN2__B
 
- VSB_TOP_EQSMRSTCTRL_DDMEN2__M
 
- VSB_TOP_EQSMRSTCTRL_DDMEN2__PRE
 
- VSB_TOP_EQSMRSTCTRL_DDMEN2__W
 
- VSB_TOP_EQSMRSTCTRL_DFEON__B
 
- VSB_TOP_EQSMRSTCTRL_DFEON__M
 
- VSB_TOP_EQSMRSTCTRL_DFEON__PRE
 
- VSB_TOP_EQSMRSTCTRL_DFEON__W
 
- VSB_TOP_EQSMRSTCTRL_DIGIAGCON__B
 
- VSB_TOP_EQSMRSTCTRL_DIGIAGCON__M
 
- VSB_TOP_EQSMRSTCTRL_DIGIAGCON__PRE
 
- VSB_TOP_EQSMRSTCTRL_DIGIAGCON__W
 
- VSB_TOP_EQSMRSTCTRL_PARAINITEN__B
 
- VSB_TOP_EQSMRSTCTRL_PARAINITEN__M
 
- VSB_TOP_EQSMRSTCTRL_PARAINITEN__PRE
 
- VSB_TOP_EQSMRSTCTRL_PARAINITEN__W
 
- VSB_TOP_EQSMRSTCTRL_RCAON__B
 
- VSB_TOP_EQSMRSTCTRL_RCAON__M
 
- VSB_TOP_EQSMRSTCTRL_RCAON__PRE
 
- VSB_TOP_EQSMRSTCTRL_RCAON__W
 
- VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__B
 
- VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__M
 
- VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__PRE
 
- VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__W
 
- VSB_TOP_EQSMRSTCTRL__A
 
- VSB_TOP_EQSMRSTCTRL__M
 
- VSB_TOP_EQSMRSTCTRL__PRE
 
- VSB_TOP_EQSMRSTCTRL__W
 
- VSB_TOP_EQSMTRNCTRL_DDMEN1__B
 
- VSB_TOP_EQSMTRNCTRL_DDMEN1__M
 
- VSB_TOP_EQSMTRNCTRL_DDMEN1__PRE
 
- VSB_TOP_EQSMTRNCTRL_DDMEN1__W
 
- VSB_TOP_EQSMTRNCTRL_DDMEN2__B
 
- VSB_TOP_EQSMTRNCTRL_DDMEN2__M
 
- VSB_TOP_EQSMTRNCTRL_DDMEN2__PRE
 
- VSB_TOP_EQSMTRNCTRL_DDMEN2__W
 
- VSB_TOP_EQSMTRNCTRL_DFEON__B
 
- VSB_TOP_EQSMTRNCTRL_DFEON__M
 
- VSB_TOP_EQSMTRNCTRL_DFEON__PRE
 
- VSB_TOP_EQSMTRNCTRL_DFEON__W
 
- VSB_TOP_EQSMTRNCTRL_DIGIAGCON__B
 
- VSB_TOP_EQSMTRNCTRL_DIGIAGCON__M
 
- VSB_TOP_EQSMTRNCTRL_DIGIAGCON__PRE
 
- VSB_TOP_EQSMTRNCTRL_DIGIAGCON__W
 
- VSB_TOP_EQSMTRNCTRL_PARAINITEN__B
 
- VSB_TOP_EQSMTRNCTRL_PARAINITEN__M
 
- VSB_TOP_EQSMTRNCTRL_PARAINITEN__PRE
 
- VSB_TOP_EQSMTRNCTRL_PARAINITEN__W
 
- VSB_TOP_EQSMTRNCTRL_RCAON__B
 
- VSB_TOP_EQSMTRNCTRL_RCAON__M
 
- VSB_TOP_EQSMTRNCTRL_RCAON__PRE
 
- VSB_TOP_EQSMTRNCTRL_RCAON__W
 
- VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__B
 
- VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__M
 
- VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__PRE
 
- VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__W
 
- VSB_TOP_EQSMTRNCTRL__A
 
- VSB_TOP_EQSMTRNCTRL__M
 
- VSB_TOP_EQSMTRNCTRL__PRE
 
- VSB_TOP_EQSMTRNCTRL__W
 
- VSB_TOP_EQSMUP__A
 
- VSB_TOP_EQSMUP__M
 
- VSB_TOP_EQSMUP__PRE
 
- VSB_TOP_EQSMUP__W
 
- VSB_TOP_ERR_ENERGY_H__A
 
- VSB_TOP_ERR_ENERGY_H__M
 
- VSB_TOP_ERR_ENERGY_H__PRE
 
- VSB_TOP_ERR_ENERGY_H__W
 
- VSB_TOP_ERR_ENERGY_L__A
 
- VSB_TOP_ERR_ENERGY_L__M
 
- VSB_TOP_ERR_ENERGY_L__PRE
 
- VSB_TOP_ERR_ENERGY_L__W
 
- VSB_TOP_FIRSTLARGDFETAPADDR__A
 
- VSB_TOP_FIRSTLARGDFETAPADDR__M
 
- VSB_TOP_FIRSTLARGDFETAPADDR__PRE
 
- VSB_TOP_FIRSTLARGDFETAPADDR__W
 
- VSB_TOP_FIRSTLARGDFETAP__A
 
- VSB_TOP_FIRSTLARGDFETAP__M
 
- VSB_TOP_FIRSTLARGDFETAP__PRE
 
- VSB_TOP_FIRSTLARGDFETAP__W
 
- VSB_TOP_FIRSTLARGFFETAPADDR__A
 
- VSB_TOP_FIRSTLARGFFETAPADDR__M
 
- VSB_TOP_FIRSTLARGFFETAPADDR__PRE
 
- VSB_TOP_FIRSTLARGFFETAPADDR__W
 
- VSB_TOP_FIRSTLARGFFETAP__A
 
- VSB_TOP_FIRSTLARGFFETAP__M
 
- VSB_TOP_FIRSTLARGFFETAP__PRE
 
- VSB_TOP_FIRSTLARGFFETAP__W
 
- VSB_TOP_LBAGCREFLVL__A
 
- VSB_TOP_LBAGCREFLVL__M
 
- VSB_TOP_LBAGCREFLVL__PRE
 
- VSB_TOP_LBAGCREFLVL__W
 
- VSB_TOP_LOCKSTATUS_CYLOCK__B
 
- VSB_TOP_LOCKSTATUS_CYLOCK__M
 
- VSB_TOP_LOCKSTATUS_CYLOCK__PRE
 
- VSB_TOP_LOCKSTATUS_CYLOCK__W
 
- VSB_TOP_LOCKSTATUS_DDMON__B
 
- VSB_TOP_LOCKSTATUS_DDMON__M
 
- VSB_TOP_LOCKSTATUS_DDMON__PRE
 
- VSB_TOP_LOCKSTATUS_DDMON__W
 
- VSB_TOP_LOCKSTATUS_FRMLOCK__B
 
- VSB_TOP_LOCKSTATUS_FRMLOCK__M
 
- VSB_TOP_LOCKSTATUS_FRMLOCK__PRE
 
- VSB_TOP_LOCKSTATUS_FRMLOCK__W
 
- VSB_TOP_LOCKSTATUS_VSBMODE__B
 
- VSB_TOP_LOCKSTATUS_VSBMODE__M
 
- VSB_TOP_LOCKSTATUS_VSBMODE__PRE
 
- VSB_TOP_LOCKSTATUS_VSBMODE__W
 
- VSB_TOP_LOCKSTATUS__A
 
- VSB_TOP_LOCKSTATUS__M
 
- VSB_TOP_LOCKSTATUS__PRE
 
- VSB_TOP_LOCKSTATUS__W
 
- VSB_TOP_MAINSMUP__A
 
- VSB_TOP_MAINSMUP__M
 
- VSB_TOP_MAINSMUP__PRE
 
- VSB_TOP_MAINSMUP__W
 
- VSB_TOP_MEASUREMENT_PERIOD
 
- VSB_TOP_MEASUREMENT_PERIOD__A
 
- VSB_TOP_MEASUREMENT_PERIOD__M
 
- VSB_TOP_MEASUREMENT_PERIOD__PRE
 
- VSB_TOP_MEASUREMENT_PERIOD__W
 
- VSB_TOP_NOTCH1_BIN_NUM__A
 
- VSB_TOP_NOTCH1_BIN_NUM__M
 
- VSB_TOP_NOTCH1_BIN_NUM__PRE
 
- VSB_TOP_NOTCH1_BIN_NUM__W
 
- VSB_TOP_NOTCH2_BIN_NUM__A
 
- VSB_TOP_NOTCH2_BIN_NUM__M
 
- VSB_TOP_NOTCH2_BIN_NUM__PRE
 
- VSB_TOP_NOTCH2_BIN_NUM__W
 
- VSB_TOP_NOTCH_SCALE_1__A
 
- VSB_TOP_NOTCH_SCALE_1__M
 
- VSB_TOP_NOTCH_SCALE_1__PRE
 
- VSB_TOP_NOTCH_SCALE_1__W
 
- VSB_TOP_NOTCH_SCALE_2__A
 
- VSB_TOP_NOTCH_SCALE_2__M
 
- VSB_TOP_NOTCH_SCALE_2__PRE
 
- VSB_TOP_NOTCH_SCALE_2__W
 
- VSB_TOP_NOTCH_START_BIN_NUM__A
 
- VSB_TOP_NOTCH_START_BIN_NUM__M
 
- VSB_TOP_NOTCH_START_BIN_NUM__PRE
 
- VSB_TOP_NOTCH_START_BIN_NUM__W
 
- VSB_TOP_NOTCH_STOP_BIN_NUM__A
 
- VSB_TOP_NOTCH_STOP_BIN_NUM__M
 
- VSB_TOP_NOTCH_STOP_BIN_NUM__PRE
 
- VSB_TOP_NOTCH_STOP_BIN_NUM__W
 
- VSB_TOP_NOTCH_SWEEP_RUNNING__A
 
- VSB_TOP_NOTCH_SWEEP_RUNNING__M
 
- VSB_TOP_NOTCH_SWEEP_RUNNING__PRE
 
- VSB_TOP_NOTCH_SWEEP_RUNNING__W
 
- VSB_TOP_NOTCH_TEST_DURATION__A
 
- VSB_TOP_NOTCH_TEST_DURATION__M
 
- VSB_TOP_NOTCH_TEST_DURATION__PRE
 
- VSB_TOP_NOTCH_TEST_DURATION__W
 
- VSB_TOP_NR_SYM_ERRS__A
 
- VSB_TOP_NR_SYM_ERRS__M
 
- VSB_TOP_NR_SYM_ERRS__PRE
 
- VSB_TOP_NR_SYM_ERRS__W
 
- VSB_TOP_PARAOWCTRL_PARAOWABUS__B
 
- VSB_TOP_PARAOWCTRL_PARAOWABUS__M
 
- VSB_TOP_PARAOWCTRL_PARAOWABUS__PRE
 
- VSB_TOP_PARAOWCTRL_PARAOWABUS__W
 
- VSB_TOP_PARAOWCTRL_PARAOWEN__B
 
- VSB_TOP_PARAOWCTRL_PARAOWEN__M
 
- VSB_TOP_PARAOWCTRL_PARAOWEN__PRE
 
- VSB_TOP_PARAOWCTRL_PARAOWEN__W
 
- VSB_TOP_PARAOWCTRL__A
 
- VSB_TOP_PARAOWCTRL__M
 
- VSB_TOP_PARAOWCTRL__PRE
 
- VSB_TOP_PARAOWCTRL__W
 
- VSB_TOP_PARAOWDBUS__A
 
- VSB_TOP_PARAOWDBUS__M
 
- VSB_TOP_PARAOWDBUS__PRE
 
- VSB_TOP_PARAOWDBUS__W
 
- VSB_TOP_PHASELOCKCTRL_CFORCEPLL__B
 
- VSB_TOP_PHASELOCKCTRL_CFORCEPLL__M
 
- VSB_TOP_PHASELOCKCTRL_CFORCEPLL__PRE
 
- VSB_TOP_PHASELOCKCTRL_CFORCEPLL__W
 
- VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__B
 
- VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__M
 
- VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__PRE
 
- VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__W
 
- VSB_TOP_PHASELOCKCTRL_DFORCEPLL__B
 
- VSB_TOP_PHASELOCKCTRL_DFORCEPLL__M
 
- VSB_TOP_PHASELOCKCTRL_DFORCEPLL__PRE
 
- VSB_TOP_PHASELOCKCTRL_DFORCEPLL__W
 
- VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__B
 
- VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__M
 
- VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__PRE
 
- VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__W
 
- VSB_TOP_PHASELOCKCTRL_IQSWITCH__B
 
- VSB_TOP_PHASELOCKCTRL_IQSWITCH__M
 
- VSB_TOP_PHASELOCKCTRL_IQSWITCH__PRE
 
- VSB_TOP_PHASELOCKCTRL_IQSWITCH__W
 
- VSB_TOP_PHASELOCKCTRL_PFORCEPLL__B
 
- VSB_TOP_PHASELOCKCTRL_PFORCEPLL__M
 
- VSB_TOP_PHASELOCKCTRL_PFORCEPLL__PRE
 
- VSB_TOP_PHASELOCKCTRL_PFORCEPLL__W
 
- VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__B
 
- VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__M
 
- VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__PRE
 
- VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__W
 
- VSB_TOP_PHASELOCKCTRL__A
 
- VSB_TOP_PHASELOCKCTRL__M
 
- VSB_TOP_PHASELOCKCTRL__PRE
 
- VSB_TOP_PHASELOCKCTRL__W
 
- VSB_TOP_PLOCKACCUM__A
 
- VSB_TOP_PLOCKACCUM__M
 
- VSB_TOP_PLOCKACCUM__PRE
 
- VSB_TOP_PLOCKACCUM__W
 
- VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__B
 
- VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__M
 
- VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__PRE
 
- VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__W
 
- VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__B
 
- VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__M
 
- VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__PRE
 
- VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__W
 
- VSB_TOP_PREEQAGCCTRL__A
 
- VSB_TOP_PREEQAGCCTRL__M
 
- VSB_TOP_PREEQAGCCTRL__PRE
 
- VSB_TOP_PREEQAGCCTRL__W
 
- VSB_TOP_PREEQAGCPWRREFLVLHI__A
 
- VSB_TOP_PREEQAGCPWRREFLVLHI__M
 
- VSB_TOP_PREEQAGCPWRREFLVLHI__PRE
 
- VSB_TOP_PREEQAGCPWRREFLVLHI__W
 
- VSB_TOP_PREEQAGCPWRREFLVLLO__A
 
- VSB_TOP_PREEQAGCPWRREFLVLLO__M
 
- VSB_TOP_PREEQAGCPWRREFLVLLO__PRE
 
- VSB_TOP_PREEQAGCPWRREFLVLLO__W
 
- VSB_TOP_PREEQDAGCRATIO__A
 
- VSB_TOP_PREEQDAGCRATIO__M
 
- VSB_TOP_PREEQDAGCRATIO__PRE
 
- VSB_TOP_PREEQDAGCRATIO__W
 
- VSB_TOP_PTONCTL__A
 
- VSB_TOP_PTONCTL__M
 
- VSB_TOP_PTONCTL__PRE
 
- VSB_TOP_PTONCTL__W
 
- VSB_TOP_RESULT_LARGE_PEAK_BIN__A
 
- VSB_TOP_RESULT_LARGE_PEAK_BIN__M
 
- VSB_TOP_RESULT_LARGE_PEAK_BIN__PRE
 
- VSB_TOP_RESULT_LARGE_PEAK_BIN__W
 
- VSB_TOP_RESULT_LARGE_PEAK_VALUE__A
 
- VSB_TOP_RESULT_LARGE_PEAK_VALUE__M
 
- VSB_TOP_RESULT_LARGE_PEAK_VALUE__PRE
 
- VSB_TOP_RESULT_LARGE_PEAK_VALUE__W
 
- VSB_TOP_RESULT_SMALL_PEAK_BIN__A
 
- VSB_TOP_RESULT_SMALL_PEAK_BIN__M
 
- VSB_TOP_RESULT_SMALL_PEAK_BIN__PRE
 
- VSB_TOP_RESULT_SMALL_PEAK_BIN__W
 
- VSB_TOP_RESULT_SMALL_PEAK_VALUE__A
 
- VSB_TOP_RESULT_SMALL_PEAK_VALUE__M
 
- VSB_TOP_RESULT_SMALL_PEAK_VALUE__PRE
 
- VSB_TOP_RESULT_SMALL_PEAK_VALUE__W
 
- VSB_TOP_SECONDLARGDFETAPADDR__A
 
- VSB_TOP_SECONDLARGDFETAPADDR__M
 
- VSB_TOP_SECONDLARGDFETAPADDR__PRE
 
- VSB_TOP_SECONDLARGDFETAPADDR__W
 
- VSB_TOP_SECONDLARGDFETAP__A
 
- VSB_TOP_SECONDLARGDFETAP__M
 
- VSB_TOP_SECONDLARGDFETAP__PRE
 
- VSB_TOP_SECONDLARGDFETAP__W
 
- VSB_TOP_SECONDLARGFFETAPADDR__A
 
- VSB_TOP_SECONDLARGFFETAPADDR__M
 
- VSB_TOP_SECONDLARGFFETAPADDR__PRE
 
- VSB_TOP_SECONDLARGFFETAPADDR__W
 
- VSB_TOP_SECONDLARGFFETAP__A
 
- VSB_TOP_SECONDLARGFFETAP__M
 
- VSB_TOP_SECONDLARGFFETAP__PRE
 
- VSB_TOP_SECONDLARGFFETAP__W
 
- VSB_TOP_SLICER_SEL_8LEV__A
 
- VSB_TOP_SLICER_SEL_8LEV__M
 
- VSB_TOP_SLICER_SEL_8LEV__PRE
 
- VSB_TOP_SLICER_SEL_8LEV__W
 
- VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__B
 
- VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__M
 
- VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__PRE
 
- VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__W
 
- VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__B
 
- VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__M
 
- VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__PRE
 
- VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__W
 
- VSB_TOP_SMALL_NOTCH_CONTROL_GO__B
 
- VSB_TOP_SMALL_NOTCH_CONTROL_GO__M
 
- VSB_TOP_SMALL_NOTCH_CONTROL_GO__PRE
 
- VSB_TOP_SMALL_NOTCH_CONTROL_GO__W
 
- VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__B
 
- VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__M
 
- VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__PRE
 
- VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__W
 
- VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__B
 
- VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__M
 
- VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__PRE
 
- VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__W
 
- VSB_TOP_SMALL_NOTCH_CONTROL__A
 
- VSB_TOP_SMALL_NOTCH_CONTROL__M
 
- VSB_TOP_SMALL_NOTCH_CONTROL__PRE
 
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- VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__PRE
 
- VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__W
 
- VSB_TOP_SYSSMTRNCTRL_STARTTRN__B
 
- VSB_TOP_SYSSMTRNCTRL_STARTTRN__M
 
- VSB_TOP_SYSSMTRNCTRL_STARTTRN__PRE
 
- VSB_TOP_SYSSMTRNCTRL_STARTTRN__W
 
- VSB_TOP_SYSSMTRNCTRL__A
 
- VSB_TOP_SYSSMTRNCTRL__M
 
- VSB_TOP_SYSSMTRNCTRL__PRE
 
- VSB_TOP_SYSSMTRNCTRL__W
 
- VSB_TOP_TAPREADCYC__A
 
- VSB_TOP_TAPREADCYC__M
 
- VSB_TOP_TAPREADCYC__PRE
 
- VSB_TOP_TAPREADCYC__W
 
- VSB_TOP_UBAGCREFLVL__A
 
- VSB_TOP_UBAGCREFLVL__M
 
- VSB_TOP_UBAGCREFLVL__PRE
 
- VSB_TOP_UBAGCREFLVL__W
 
- VSB_TOP_VALIDPKLVL__A
 
- VSB_TOP_VALIDPKLVL__M
 
- VSB_TOP_VALIDPKLVL__PRE
 
- VSB_TOP_VALIDPKLVL__W
 
- VSC7326_MAX_MTU
 
- VSC7385_CLOCK_DELAY
 
- VSC7385_CLOCK_DELAY_MASK
 
- VSC73XX_ADVLEARN
 
- VSC73XX_ADVPORTM
 
- VSC73XX_ADVPORTM_DDR_MODE
 
- VSC73XX_ADVPORTM_ENA_GTX
 
- VSC73XX_ADVPORTM_EXC_COL_CONT
 
- VSC73XX_ADVPORTM_EXT_PORT
 
- VSC73XX_ADVPORTM_HOST_LOOPBACK
 
- VSC73XX_ADVPORTM_IFG_PPM
 
- VSC73XX_ADVPORTM_INV_GTX
 
- VSC73XX_ADVPORTM_IO_LOOPBACK
 
- VSC73XX_AGENCTRL
 
- VSC73XX_AGGRCTRL
 
- VSC73XX_AGGRMSKS
 
- VSC73XX_ANAGEFIL
 
- VSC73XX_ANCNTMASK
 
- VSC73XX_ANCNTVAL
 
- VSC73XX_ANEVENTS
 
- VSC73XX_ANMOVED
 
- VSC73XX_ARBBURSTPROB
 
- VSC73XX_ARBDISC
 
- VSC73XX_ARBEMPTY
 
- VSC73XX_BLOCK_ANALYZER
 
- VSC73XX_BLOCK_ARBITER
 
- VSC73XX_BLOCK_CAPTURE
 
- VSC73XX_BLOCK_MAC
 
- VSC73XX_BLOCK_MEMINIT
 
- VSC73XX_BLOCK_MII
 
- VSC73XX_BLOCK_SYSTEM
 
- VSC73XX_CAPENAB
 
- VSC73XX_CAPRST
 
- VSC73XX_CAT_DROP
 
- VSC73XX_CAT_DROP_DROP_MC_SMAC_ENA
 
- VSC73XX_CAT_DROP_FWD_CTRL_ENA
 
- VSC73XX_CAT_DROP_FWD_PAUSE_ENA
 
- VSC73XX_CAT_DROP_NULL_MAC_ENA
 
- VSC73XX_CAT_DROP_TAGGED_ENA
 
- VSC73XX_CAT_DROP_UNTAGGED_ENA
 
- VSC73XX_CAT_PR_MISC_L2
 
- VSC73XX_CAT_PR_USR_PRIO
 
- VSC73XX_CHIPID
 
- VSC73XX_CHIPID_ID_7385
 
- VSC73XX_CHIPID_ID_7388
 
- VSC73XX_CHIPID_ID_7395
 
- VSC73XX_CHIPID_ID_7398
 
- VSC73XX_CHIPID_ID_MASK
 
- VSC73XX_CHIPID_ID_SHIFT
 
- VSC73XX_CHIPID_REV_MASK
 
- VSC73XX_CHIPID_REV_SHIFT
 
- VSC73XX_CMD_PLATFORM_BLOCK_MASK
 
- VSC73XX_CMD_PLATFORM_BLOCK_SHIFT
 
- VSC73XX_CMD_PLATFORM_REGISTER_SHIFT
 
- VSC73XX_CMD_PLATFORM_SUBBLOCK_MASK
 
- VSC73XX_CMD_PLATFORM_SUBBLOCK_SHIFT
 
- VSC73XX_CMD_SPI_BLOCK_MASK
 
- VSC73XX_CMD_SPI_BLOCK_SHIFT
 
- VSC73XX_CMD_SPI_MODE_READ
 
- VSC73XX_CMD_SPI_MODE_SHIFT
 
- VSC73XX_CMD_SPI_MODE_WRITE
 
- VSC73XX_CMD_SPI_SUBBLOCK_MASK
 
- VSC73XX_C_CFG
 
- VSC73XX_C_RX0
 
- VSC73XX_C_RX1
 
- VSC73XX_C_RX2
 
- VSC73XX_C_TX0
 
- VSC73XX_C_TX1
 
- VSC73XX_C_TX2
 
- VSC73XX_DBACKWDROP
 
- VSC73XX_DSTMASKS
 
- VSC73XX_EXT_PAGE_ACCESS
 
- VSC73XX_FCCONF
 
- VSC73XX_FCCONF_FLOW_CTRL_OBEY
 
- VSC73XX_FCCONF_PAUSE_VAL_MASK
 
- VSC73XX_FCCONF_ZERO_PAUSE_EN
 
- VSC73XX_FCMACHI
 
- VSC73XX_FCMACLO
 
- VSC73XX_GLORESET
 
- VSC73XX_GLORESET_ICPU_LOCK
 
- VSC73XX_GLORESET_MASTER_RESET
 
- VSC73XX_GLORESET_MEM_LOCK
 
- VSC73XX_GLORESET_PHY_RESET
 
- VSC73XX_GLORESET_STROBE
 
- VSC73XX_GMIIDELAY
 
- VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_4_NS
 
- VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_7_NS
 
- VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS
 
- VSC73XX_GMIIDELAY_GMII0_GTXDELAY_NONE
 
- VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_4_NS
 
- VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_7_NS
 
- VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS
 
- VSC73XX_GMIIDELAY_GMII0_RXDELAY_NONE
 
- VSC73XX_GPIO
 
- VSC73XX_HWSEM
 
- VSC73XX_ICPU_ADDR
 
- VSC73XX_ICPU_CTRL
 
- VSC73XX_ICPU_CTRL_BOOT_EN
 
- VSC73XX_ICPU_CTRL_CLK_DIV_MASK
 
- VSC73XX_ICPU_CTRL_CLK_EN
 
- VSC73XX_ICPU_CTRL_EXT_ACC_EN
 
- VSC73XX_ICPU_CTRL_ICPU_PI_EN
 
- VSC73XX_ICPU_CTRL_SRST
 
- VSC73XX_ICPU_CTRL_SRST_HOLD
 
- VSC73XX_ICPU_CTRL_START
 
- VSC73XX_ICPU_CTRL_STOP
 
- VSC73XX_ICPU_CTRL_WATCHDOG_RST
 
- VSC73XX_ICPU_MBOX_CLR
 
- VSC73XX_ICPU_MBOX_SET
 
- VSC73XX_ICPU_MBOX_VAL
 
- VSC73XX_ICPU_SIPAD
 
- VSC73XX_ICPU_SRAM
 
- VSC73XX_IFLODMSK
 
- VSC73XX_IPMCACCESS
 
- VSC73XX_LEARNMASK
 
- VSC73XX_MACACCESS
 
- VSC73XX_MACACCESS_AGED_FLAG
 
- VSC73XX_MACACCESS_CMD_AGE_TABLE
 
- VSC73XX_MACACCESS_CMD_CLEAR_TABLE
 
- VSC73XX_MACACCESS_CMD_FLUSH_TABLE
 
- VSC73XX_MACACCESS_CMD_FORGET
 
- VSC73XX_MACACCESS_CMD_IDLE
 
- VSC73XX_MACACCESS_CMD_LEARN
 
- VSC73XX_MACACCESS_CMD_MASK
 
- VSC73XX_MACACCESS_CMD_READ_ENTRY
 
- VSC73XX_MACACCESS_CMD_WRITE_ENTRY
 
- VSC73XX_MACACCESS_CPU_COPY
 
- VSC73XX_MACACCESS_DEST_IDX_MASK
 
- VSC73XX_MACACCESS_FWD_KILL
 
- VSC73XX_MACACCESS_IGNORE_VLAN
 
- VSC73XX_MACACCESS_LOCKED
 
- VSC73XX_MACACCESS_VALID
 
- VSC73XX_MACHDATA
 
- VSC73XX_MACHDXGAP
 
- VSC73XX_MACLDATA
 
- VSC73XX_MACTINDX
 
- VSC73XX_MAC_CFG
 
- VSC73XX_MAC_CFG_1000M_F_PHY
 
- VSC73XX_MAC_CFG_1000M_F_RGMII
 
- VSC73XX_MAC_CFG_100_10M_F_PHY
 
- VSC73XX_MAC_CFG_100_10M_H_PHY
 
- VSC73XX_MAC_CFG_100_BASE_T
 
- VSC73XX_MAC_CFG_CLK_SEL_1000M
 
- VSC73XX_MAC_CFG_CLK_SEL_100M
 
- VSC73XX_MAC_CFG_CLK_SEL_10M
 
- VSC73XX_MAC_CFG_CLK_SEL_EXT
 
- VSC73XX_MAC_CFG_CLK_SEL_MASK
 
- VSC73XX_MAC_CFG_CLK_SEL_OFFSET
 
- VSC73XX_MAC_CFG_FDX
 
- VSC73XX_MAC_CFG_GIGA_MODE
 
- VSC73XX_MAC_CFG_MAC_RX_RST
 
- VSC73XX_MAC_CFG_MAC_TX_RST
 
- VSC73XX_MAC_CFG_PORT_RST
 
- VSC73XX_MAC_CFG_RESET
 
- VSC73XX_MAC_CFG_RX_EN
 
- VSC73XX_MAC_CFG_SEED_LOAD
 
- VSC73XX_MAC_CFG_SEED_MASK
 
- VSC73XX_MAC_CFG_SEED_OFFSET
 
- VSC73XX_MAC_CFG_TX_EN
 
- VSC73XX_MAC_CFG_TX_IPG_1000M
 
- VSC73XX_MAC_CFG_TX_IPG_100_10M
 
- VSC73XX_MAC_CFG_TX_IPG_MASK
 
- VSC73XX_MAC_CFG_TX_IPG_OFFSET
 
- VSC73XX_MAC_CFG_VLAN_AWR
 
- VSC73XX_MAC_CFG_VLAN_DBLAWR
 
- VSC73XX_MAC_CFG_WEXC_DIS
 
- VSC73XX_MAXLEN
 
- VSC73XX_MFLODMASK
 
- VSC73XX_MII_CMD
 
- VSC73XX_MII_DATA
 
- VSC73XX_MII_STAT
 
- VSC73XX_Q_MISC_CONF
 
- VSC73XX_Q_MISC_CONF_EARLY_TX_512
 
- VSC73XX_Q_MISC_CONF_EARLY_TX_MASK
 
- VSC73XX_Q_MISC_CONF_EXTENT_MEM
 
- VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE
 
- VSC73XX_RECVMASK
 
- VSC73XX_RXOCT
 
- VSC73XX_SBACKWDROP
 
- VSC73XX_SRCMASKS
 
- VSC73XX_STORMLIMIT
 
- VSC73XX_TXOCT
 
- VSC73XX_TXQ_SELECT_CFG
 
- VSC73XX_TXUPDCFG
 
- VSC73XX_UFLODMASK
 
- VSC73XX_VLANACCESS
 
- VSC73XX_VLANACCESS_LEARN_DISABLED
 
- VSC73XX_VLANACCESS_VLAN_MIRROR
 
- VSC73XX_VLANACCESS_VLAN_PORT_MASK
 
- VSC73XX_VLANACCESS_VLAN_SRC_CHECK
 
- VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE
 
- VSC73XX_VLANACCESS_VLAN_TBL_CMD_IDLE
 
- VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK
 
- VSC73XX_VLANACCESS_VLAN_TBL_CMD_READ_ENTRY
 
- VSC73XX_VLANACCESS_VLAN_TBL_CMD_WRITE_ENTRY
 
- VSC73XX_VLANMASK
 
- VSC73XX_VLANTIDX
 
- VSC8211_AUX_CTRL_STAT
 
- VSC8211_EXT_CTRL
 
- VSC8211_EXT_PAGE_AXS
 
- VSC8211_INTR_ENABLE
 
- VSC8211_INTR_STATUS
 
- VSC8211_LED_CTRL
 
- VSC8211_SIGDET_CTRL
 
- VSC8531_ACTIVITY
 
- VSC8531_AUTONEG_FAULT
 
- VSC8531_COLLISION
 
- VSC8531_DUPLEX_COLLISION
 
- VSC8531_FORCE_LED_OFF
 
- VSC8531_FORCE_LED_ON
 
- VSC8531_LINK_1000_ACTIVITY
 
- VSC8531_LINK_100_1000_ACTIVITY
 
- VSC8531_LINK_100_ACTIVITY
 
- VSC8531_LINK_10_1000_ACTIVITY
 
- VSC8531_LINK_10_100_ACTIVITY
 
- VSC8531_LINK_10_ACTIVITY
 
- VSC8531_LINK_ACTIVITY
 
- VSC8531_SERIAL_MODE
 
- VSC8584_100FX_1000X_ACTIVITY
 
- VSC8584_LINK_100FX_1000X_ACTIVITY
 
- VSC8584_MAC_IF_SELECTION_1000BASEX
 
- VSC8584_MAC_IF_SELECTION_MASK
 
- VSC8584_MAC_IF_SELECTION_POS
 
- VSC8584_MAC_IF_SELECTION_SGMII
 
- VSC8584_REVB
 
- VSC8584_SUPP_LED_MODES
 
- VSC85XX_SUPP_LED_MODES
 
- VSCADR
 
- VSCADR_BLEND_CUR
 
- VSCADR_BLEND_GFX
 
- VSCADR_BLEND_GLOB
 
- VSCADR_BLEND_INV
 
- VSCADR_BLEND_M
 
- VSCADR_BLEND_NONE
 
- VSCADR_BLEND_PIX
 
- VSCADR_BLEND_POS
 
- VSCADR_BLEND_VID
 
- VSCADR_COLKEYSRC
 
- VSCADR_COLKEY_EN
 
- VSCADR_STR_EN
 
- VSCADR_VBASE_ADR
 
- VSCALE_CTRL
 
- VSCALE_LO
 
- VSCLKDIS_MASK
 
- VSCOEFF0
 
- VSCOEFF1
 
- VSCOEFF2
 
- VSCOEFF3
 
- VSCOEFF4
 
- VSCR_SAT
 
- VSCR_SAVE
 
- VSCSIBACK_OP_ADD_OR_DEL_LUN
 
- VSCSIBACK_OP_UPDATEDEV_STATE
 
- VSCSIFRONT_OP_ADD_LUN
 
- VSCSIFRONT_OP_DEL_LUN
 
- VSCSIFRONT_OP_READD_LUN
 
- VSCSIIF_ACT_SCSI_ABORT
 
- VSCSIIF_ACT_SCSI_CDB
 
- VSCSIIF_ACT_SCSI_RESET
 
- VSCSIIF_ACT_SCSI_SG_PRESET
 
- VSCSIIF_DEFAULT_CMD_PER_LUN
 
- VSCSIIF_MAX_COMMAND_SIZE
 
- VSCSIIF_MAX_LUN
 
- VSCSIIF_MAX_REQS
 
- VSCSIIF_MAX_TARGET
 
- VSCSIIF_RING_SIZE
 
- VSCSIIF_SENSE_BUFFERSIZE
 
- VSCSIIF_SG_GRANT
 
- VSCSIIF_SG_PER_PAGE
 
- VSCSIIF_SG_TABLESIZE
 
- VSCSI_DEFAULT_SESSION_TAGS
 
- VSCSI_GRANT_BATCH
 
- VSCSI_MAX_GRANTS
 
- VSCSI_NAMELEN
 
- VSCSI_VERSION
 
- VSCTL
 
- VSCTRL
 
- VSCTRL_COSITED
 
- VSCTRL_CSC_EN
 
- VSCTRL_GAMMA_EN
 
- VSCTRL_VPIXFMT
 
- VSCTRL_VPIXFMT_UY0VY1
 
- VSCTRL_VPIXFMT_VY0UY1
 
- VSCTRL_VPIXFMT_Y0UY1V
 
- VSCTRL_VPIXFMT_Y0VY1U
 
- VSCTRL_VPIXFMT_YUV12
 
- VSCTRL_VSHEIGHT
 
- VSCTRL_VSWIDTH
 
- VSC_ADDR_BIT_LEN
 
- VSC_ADDR_BIT_OFFS
 
- VSC_ADDR_OFFSET
 
- VSC_BANK_LEN
 
- VSC_BOT_INI_RCV_NUM
 
- VSC_BOT_RPT_L0_NUM
 
- VSC_BUSY_CYCLES
 
- VSC_COUNTER_OFFSET
 
- VSC_CTRL_CLAUSE37_VIEW
 
- VSC_CTRL_MEDIA_MODE_HI
 
- VSC_CTRL_OFFSET
 
- VSC_DATA_OFFSET
 
- VSC_DATA_SEL_SOFTWARE_CONTROL
 
- VSC_DIP_HW_DATA_SW_HEA
 
- VSC_DIP_HW_HEA_DATA
 
- VSC_DIP_HW_HEA_SW_DATA
 
- VSC_DIP_SW_HEA_DATA
 
- VSC_EOT_NUM
 
- VSC_FLAG_BIT_LEN
 
- VSC_FLAG_BIT_OFFS
 
- VSC_INI_PHASE_BOT
 
- VSC_INI_PHASE_TOP
 
- VSC_INTR_CABLE
 
- VSC_INTR_DESCRAMBL
 
- VSC_INTR_DPLX_CHG
 
- VSC_INTR_ENABLE
 
- VSC_INTR_FALSE_CARR
 
- VSC_INTR_LINK_CHG
 
- VSC_INTR_MEDIA_CHG
 
- VSC_INTR_MS_ERR
 
- VSC_INTR_NEG_DONE
 
- VSC_INTR_NEG_ERR
 
- VSC_INTR_RX_ERR
 
- VSC_INTR_RX_FIFO
 
- VSC_INTR_SPD_CHG
 
- VSC_INTR_SYMBOL_ERR
 
- VSC_INTR_TX_FIFO
 
- VSC_MAX_RETRIES
 
- VSC_MMIO_BAR
 
- VSC_PROG_INTERLACE
 
- VSC_SATA_DMA_CMD_OFFSET
 
- VSC_SATA_INT_ERROR
 
- VSC_SATA_INT_ERROR_CRC
 
- VSC_SATA_INT_ERROR_E
 
- VSC_SATA_INT_ERROR_M
 
- VSC_SATA_INT_ERROR_P
 
- VSC_SATA_INT_ERROR_R
 
- VSC_SATA_INT_ERROR_T
 
- VSC_SATA_INT_MASK_OFFSET
 
- VSC_SATA_INT_PHY_CHANGE
 
- VSC_SATA_INT_STAT_OFFSET
 
- VSC_SATA_PORT_OFFSET
 
- VSC_SATA_SCR_CONTROL_OFFSET
 
- VSC_SATA_SCR_ERROR_OFFSET
 
- VSC_SATA_SCR_STATUS_OFFSET
 
- VSC_SATA_TF_ALTSTATUS_OFFSET
 
- VSC_SATA_TF_CMD_OFFSET
 
- VSC_SATA_TF_COMMAND_OFFSET
 
- VSC_SATA_TF_CTL_OFFSET
 
- VSC_SATA_TF_DATA_OFFSET
 
- VSC_SATA_TF_DEVICE_OFFSET
 
- VSC_SATA_TF_ERROR_OFFSET
 
- VSC_SATA_TF_FEATURE_OFFSET
 
- VSC_SATA_TF_LBAH_OFFSET
 
- VSC_SATA_TF_LBAL_OFFSET
 
- VSC_SATA_TF_LBAM_OFFSET
 
- VSC_SATA_TF_NSECT_OFFSET
 
- VSC_SATA_TF_STATUS_OFFSET
 
- VSC_SATA_UP_DATA_BUFFER_OFFSET
 
- VSC_SATA_UP_DESCRIPTOR_OFFSET
 
- VSC_SELECT_MASK
 
- VSC_SELECT_SHIFT
 
- VSC_SEMAPHORE_OFFSET
 
- VSC_SIZE_VLD_BIT_LEN
 
- VSC_SIZE_VLD_BIT_OFFS
 
- VSC_SPACE_BIT_LEN
 
- VSC_SPACE_BIT_OFFS
 
- VSC_STALL_CYCLES_UCHE
 
- VSC_STARVE_CYCLES_RAS
 
- VSC_STATUS_BIT_LEN
 
- VSC_STATUS_BIT_OFFS
 
- VSC_SYND_BIT_LEN
 
- VSC_SYND_BIT_OFFS
 
- VSC_TOP_INI_RCV_NUM
 
- VSC_TOP_RPT_L0_NUM
 
- VSC_VERTICAL_SCALER_EN
 
- VSC_WORKING_CYCLES
 
- VSDELAY
 
- VSD_FIRST_SECTOR_OFFSET
 
- VSD_MAX_SECTOR_OFFSET
 
- VSD_OFFSET_MLX_BOARD_ID
 
- VSD_OFFSET_SIG1
 
- VSD_OFFSET_SIG2
 
- VSD_OFFSET_TS_BOARD_ID
 
- VSD_SIGNATURE_TOPSPIN
 
- VSD_STD_ID_BEA01
 
- VSD_STD_ID_BOOT2
 
- VSD_STD_ID_CD001
 
- VSD_STD_ID_CDW02
 
- VSD_STD_ID_LEN
 
- VSD_STD_ID_NSR02
 
- VSD_STD_ID_NSR03
 
- VSD_STD_ID_TEA01
 
- VSEL_BUCK_EN
 
- VSEL_MODE
 
- VSEN1_HV_HL_REG
 
- VSEN1_HV_LL_REG
 
- VSEN1_HV_REG
 
- VSEN1_LV_HL_REG
 
- VSEN1_LV_LL_REG
 
- VSEN_MAX
 
- VSE_CAP_OFFSET_MAX
 
- VSE_CVP_DATA
 
- VSE_CVP_MODE_CTRL
 
- VSE_CVP_MODE_CTRL_CVP_MODE
 
- VSE_CVP_MODE_CTRL_HIP_CLK_SEL
 
- VSE_CVP_MODE_CTRL_NUMCLKS_MASK
 
- VSE_CVP_MODE_CTRL_NUMCLKS_OFF
 
- VSE_CVP_PROG_CTRL
 
- VSE_CVP_PROG_CTRL_CONFIG
 
- VSE_CVP_PROG_CTRL_MASK
 
- VSE_CVP_PROG_CTRL_START_XFER
 
- VSE_CVP_STATUS
 
- VSE_CVP_STATUS_CFG_DONE
 
- VSE_CVP_STATUS_CFG_ERR
 
- VSE_CVP_STATUS_CFG_RDY
 
- VSE_CVP_STATUS_CVP_EN
 
- VSE_CVP_STATUS_PLD_CLK_IN_USE
 
- VSE_CVP_STATUS_USERMODE
 
- VSE_CVP_TX_CREDITS
 
- VSE_PCIE_EXT_CAP_ID
 
- VSE_PCIE_EXT_CAP_ID_VAL
 
- VSE_UNCOR_ERR_CVP_CFG_ERR
 
- VSE_UNCOR_ERR_STATUS
 
- VSG_RECOVERY
 
- VSG_RUNNING
 
- VSI0_BD
 
- VSI0_BS
 
- VSI0_CTL
 
- VSI0_TO
 
- VSI1_BD
 
- VSI1_BS
 
- VSI1_CTL
 
- VSI1_TO
 
- VSI2_BD
 
- VSI2_BS
 
- VSI2_CTL
 
- VSI2_TO
 
- VSI3_BD
 
- VSI3_BS
 
- VSI3_CTL
 
- VSI3_TO
 
- VSI4_BD
 
- VSI4_BS
 
- VSI4_CTL
 
- VSI4_TO
 
- VSI5_BD
 
- VSI5_BS
 
- VSI5_CTL
 
- VSI5_TO
 
- VSI6_BD
 
- VSI6_BS
 
- VSI6_CTL
 
- VSI6_TO
 
- VSI7_BD
 
- VSI7_BS
 
- VSI7_CTL
 
- VSI7_TO
 
- VSID_1T
 
- VSID_64K
 
- VSID_ALL
 
- VSID_BAT
 
- VSID_BITS_1T
 
- VSID_BITS_256M
 
- VSID_BITS_65_1T
 
- VSID_BITS_65_256M
 
- VSID_MASK
 
- VSID_MULINV_1T
 
- VSID_MULINV_256M
 
- VSID_MULTIPLIER_1T
 
- VSID_MULTIPLIER_256M
 
- VSID_POOL_SIZE
 
- VSID_PR
 
- VSID_REAL
 
- VSID_REAL_DR
 
- VSID_REAL_IR
 
- VSIM
 
- VSIM2
 
- VSIQF_HKEY_MAX_INDEX
 
- VSIQF_HLUT_MAX_INDEX
 
- VSIZE
 
- VSIZE8
 
- VSIZE8_SET
 
- VSIZE_MASK
 
- VSIZE_OFST
 
- VSIZE_SET
 
- VSMPS3REGUVALTO_ERR
 
- VSND_MAX_STREAM
 
- VSND_WAIT_BACK_MS
 
- VSOCK_CLOSE_TIMEOUT
 
- VSOCK_CONN_HASH
 
- VSOCK_DEFAULT_CONNECT_TIMEOUT
 
- VSOCK_HASH
 
- VSOCK_HASH_SIZE
 
- VSOCK_OPTIMIZATION_FLOW_CONTROL
 
- VSOCK_OPTIMIZATION_WAITING_NOTIFY
 
- VSOCK_PROTO_ALL_SUPPORTED
 
- VSOCK_PROTO_INVALID
 
- VSOCK_PROTO_PKT_ON_NOTIFY
 
- VSOCK_VQ_EVENT
 
- VSOCK_VQ_MAX
 
- VSOCK_VQ_RX
 
- VSOCK_VQ_TX
 
- VSOC_COND_WAIT
 
- VSOC_COND_WAKE
 
- VSOC_CREATE_FD_SCOPED_PERMISSION
 
- VSOC_DESCRIBE_REGION
 
- VSOC_DEVICE_NAME_SZ
 
- VSOC_DEV_NAME
 
- VSOC_GET_FD_SCOPED_PERMISSION
 
- VSOC_MAYBE_SEND_INTERRUPT_TO_HOST
 
- VSOC_NODE_FREE
 
- VSOC_REGION_FREE
 
- VSOC_REGION_WHOLE
 
- VSOC_SELF_INTERRUPT
 
- VSOC_SEND_INTERRUPT_TO_HOST
 
- VSOC_WAIT_FOR_INCOMING_INTERRUPT
 
- VSOC_WAIT_IF_EQUAL
 
- VSOC_WAIT_IF_EQUAL_TIMEOUT
 
- VSOC_WAIT_UNDEFINED
 
- VSP
 
- VSP0
 
- VSP0_MASK
 
- VSP0_SHIFT
 
- VSP1_DLH_AUTO_START
 
- VSP1_DLH_EXT_POST_CMD_EXEC
 
- VSP1_DLH_EXT_PRE_CMD_EXEC
 
- VSP1_DLH_INT_ENABLE
 
- VSP1_DL_FRAME_END_COMPLETED
 
- VSP1_DL_FRAME_END_INTERNAL
 
- VSP1_DL_FRAME_END_WRITEBACK
 
- VSP1_DL_NUM_ENTRIES
 
- VSP1_DU_CRC_NONE
 
- VSP1_DU_CRC_OUTPUT
 
- VSP1_DU_CRC_PLANE
 
- VSP1_DU_STATUS_COMPLETE
 
- VSP1_DU_STATUS_WRITEBACK
 
- VSP1_ENTITY_BRS
 
- VSP1_ENTITY_BRU
 
- VSP1_ENTITY_CLU
 
- VSP1_ENTITY_HGO
 
- VSP1_ENTITY_HGT
 
- VSP1_ENTITY_HSI
 
- VSP1_ENTITY_HST
 
- VSP1_ENTITY_LIF
 
- VSP1_ENTITY_LUT
 
- VSP1_ENTITY_MAX_INPUTS
 
- VSP1_ENTITY_ROUTE
 
- VSP1_ENTITY_ROUTE_RPF
 
- VSP1_ENTITY_ROUTE_UDS
 
- VSP1_ENTITY_ROUTE_UIF
 
- VSP1_ENTITY_ROUTE_WPF
 
- VSP1_ENTITY_RPF
 
- VSP1_ENTITY_SRU
 
- VSP1_ENTITY_UDS
 
- VSP1_ENTITY_UIF
 
- VSP1_ENTITY_WPF
 
- VSP1_EXTCMD_AUTODISP
 
- VSP1_EXTCMD_AUTOFLD
 
- VSP1_HAS_BRS
 
- VSP1_HAS_BRU
 
- VSP1_HAS_CLU
 
- VSP1_HAS_EXT_DL
 
- VSP1_HAS_HGO
 
- VSP1_HAS_HGT
 
- VSP1_HAS_LUT
 
- VSP1_HAS_SRU
 
- VSP1_HAS_WPF_HFLIP
 
- VSP1_HAS_WPF_VFLIP
 
- VSP1_MAX_LIF
 
- VSP1_MAX_RPF
 
- VSP1_MAX_UDS
 
- VSP1_MAX_UIF
 
- VSP1_MAX_WPF
 
- VSP1_PIPELINE_RUNNING
 
- VSP1_PIPELINE_STOPPED
 
- VSP1_PIPELINE_STOPPING
 
- VSP1_VIDEO_DEF_FORMAT
 
- VSP1_VIDEO_DEF_HEIGHT
 
- VSP1_VIDEO_DEF_WIDTH
 
- VSP1_VIDEO_MAX_HEIGHT
 
- VSP1_VIDEO_MAX_WIDTH
 
- VSPIC_MMIO_SIZE
 
- VSPR
 
- VSP_HI
 
- VSP_LO
 
- VSP_MARK
 
- VSP_MASK
 
- VSP_SHIFT
 
- VSP_TIMEOUT
 
- VSR
 
- VSR_PHY_ACT_LED
 
- VSR_PHY_DFE_UPDATE_CRTL
 
- VSR_PHY_FFE_CONTROL
 
- VSR_PHY_MODE1
 
- VSR_PHY_MODE10
 
- VSR_PHY_MODE11
 
- VSR_PHY_MODE2
 
- VSR_PHY_MODE3
 
- VSR_PHY_MODE4
 
- VSR_PHY_MODE5
 
- VSR_PHY_MODE6
 
- VSR_PHY_MODE7
 
- VSR_PHY_MODE8
 
- VSR_PHY_MODE9
 
- VSR_PHY_STAT
 
- VSR_PHY_VS0
 
- VSR_PHY_VS1
 
- VSR_REF_CLOCK_CRTL
 
- VSR_SAVE
 
- VSS
 
- VSSL_FIELD
 
- VSSL_VACT
 
- VSSL_VSYNC
 
- VSSL_VVALID
 
- VSSL_ZERO
 
- VSS_ADDR
 
- VSS_CLKRST
 
- VSS_FREEZE_TIMEOUT
 
- VSS_FTR
 
- VSS_GATE
 
- VSS_HBU_NO_AUTO_RECOVERY
 
- VSS_MAJOR
 
- VSS_MINOR
 
- VSS_OP_AUTO_RECOVER
 
- VSS_OP_BU_COMPLETE
 
- VSS_OP_COUNT
 
- VSS_OP_CREATE
 
- VSS_OP_DELETE
 
- VSS_OP_FREEZE
 
- VSS_OP_GET_DM_INFO
 
- VSS_OP_HOT_BACKUP
 
- VSS_OP_REGISTER
 
- VSS_OP_REGISTER1
 
- VSS_OP_THAW
 
- VSS_VERSION
 
- VSS_VER_COUNT
 
- VSTART
 
- VSTATUSVIT
 
- VSTOP
 
- VSTOR_OPERATION_BEGIN_INITIALIZATION
 
- VSTOR_OPERATION_COMPLETE_IO
 
- VSTOR_OPERATION_CREATE_SUB_CHANNELS
 
- VSTOR_OPERATION_END_INITIALIZATION
 
- VSTOR_OPERATION_ENUMERATE_BUS
 
- VSTOR_OPERATION_EXECUTE_SRB
 
- VSTOR_OPERATION_FCHBA_DATA
 
- VSTOR_OPERATION_MAXIMUM
 
- VSTOR_OPERATION_QUERY_PROPERTIES
 
- VSTOR_OPERATION_QUERY_PROTOCOL_VERSION
 
- VSTOR_OPERATION_REMOVE_DEVICE
 
- VSTOR_OPERATION_RESET_ADAPTER
 
- VSTOR_OPERATION_RESET_BUS
 
- VSTOR_OPERATION_RESET_LUN
 
- VSTR
 
- VSTREAM_ENABLE
 
- VST_MASK
 
- VST_SHIFT
 
- VST_UNITS_20US
 
- VSUNIT_CLKGATE_DIS
 
- VSUNIT_CLKGATE_DIS_TGL
 
- VSUNIT_CLOCK_GATE_DISABLE
 
- VSUSP
 
- VSV_CLOSE_PROTOCOL
 
- VSV_MODEM_CTL_UPDATE
 
- VSV_SEND_MODEM_CTL_STATUS
 
- VSV_SEND_VERSION_NUMBER
 
- VSV_SET_MODEM_CTL
 
- VSWITCH1_OUTPUT
 
- VSWITCH2_OUTPUT
 
- VSWTC
 
- VSWTCH
 
- VSW_TX_TIMEOUT
 
- VSX20
 
- VSXXXAA_DEBUG
 
- VSXXXAA_INTRO_HEAD
 
- VSXXXAA_INTRO_MASK
 
- VSXXXAA_PACKET_ABS
 
- VSXXXAA_PACKET_MASK
 
- VSXXXAA_PACKET_POR
 
- VSXXXAA_PACKET_REL
 
- VSX_CHECK_VEC
 
- VSX_FPCONV
 
- VSX_LDLEFT
 
- VSX_MAX
 
- VSX_SPLAT
 
- VSX_UNA_EXCEPTION
 
- VSX_XX1
 
- VSX_XX3
 
- VSYNC
 
- VSYNCEND_MASK
 
- VSYNCEND_SHIFT
 
- VSYNCH_REG
 
- VSYNCL_REG
 
- VSYNCSHIFT
 
- VSYNCSHIFT_A
 
- VSYNCSHIFT_B
 
- VSYNCSHIFT_C
 
- VSYNCSTART_MASK
 
- VSYNCSTART_SHIFT
 
- VSYNC_A
 
- VSYNC_ACTIVE_LOW
 
- VSYNC_B
 
- VSYNC_BACK_PORCH_MASK
 
- VSYNC_BACK_PORCH_SHIFT
 
- VSYNC_C
 
- VSYNC_CLK_RATE
 
- VSYNC_CLK_SRC
 
- VSYNC_CNTL
 
- VSYNC_CNT_LATCH_MASK
 
- VSYNC_CNT_LATCH_MASK_0
 
- VSYNC_CNT_LATCH_MASK_1
 
- VSYNC_CNT_REFCLK_SEL
 
- VSYNC_CNT_REFCLK_SEL_0
 
- VSYNC_CNT_REFCLK_SEL_1
 
- VSYNC_CNT_RESET_SEL
 
- VSYNC_CNT_RESET_SEL_0
 
- VSYNC_CNT_RESET_SEL_1
 
- VSYNC_DET
 
- VSYNC_FRONT_PORCH_MASK
 
- VSYNC_FRONT_PORCH_SHIFT
 
- VSYNC_HALF_LINE_MASK
 
- VSYNC_HALF_LINE_SHIFT
 
- VSYNC_HE_ADDR
 
- VSYNC_HIGH
 
- VSYNC_HS_ADDR
 
- VSYNC_H_POSITION
 
- VSYNC_IRQ
 
- VSYNC_IRQ_ENA
 
- VSYNC_IRQ_ENA_MASK
 
- VSYNC_IRQ_LEVEL
 
- VSYNC_IRQ_LEVEL_MASK
 
- VSYNC_IRQ_MASK
 
- VSYNC_MARK
 
- VSYNC_OFF
 
- VSYNC_ON
 
- VSYNC_PIPE_A_INTERRUPT
 
- VSYNC_PIPE_B_INTERRUPT
 
- VSYNC_POL
 
- VSYNC_POLARITY_CFG
 
- VSYNC_POSITIVE
 
- VSYNC_TIMEOUT_MSEC
 
- VSYNC_VE_ADDR
 
- VSYNC_VS_ADDR
 
- VSYNC_WIDTH_MASK
 
- VSYNC_WIDTH_SHIFT
 
- VSYNC_WINDOW_ENABLE
 
- VSYNC_WINDOW_END
 
- VSYNC_WINDOW_START
 
- VSYS
 
- VSYSCALL_ADDR
 
- VSYSCALL_AUX_ENT
 
- VSYSCALL_PAGE
 
- VSYSTEM_OVV
 
- VSYS_2P5_R_INT
 
- VSYS_2P5_R_INT_MASK
 
- VSYS_6P0_D200UR_INT
 
- VSYS_6P0_D200UR_INT_MASK
 
- VSYS_UV_D3R_INT
 
- VSYS_UV_D3R_INT_MASK
 
- VS_1_TO_1_SCALE
 
- VS_BK1_IF
 
- VS_BK1_IF_UPDATE
 
- VS_BK2_IF
 
- VS_BK2_IF_UPDATE
 
- VS_CAP_10
 
- VS_CAP_11
 
- VS_CAP_15
 
- VS_CAP_16
 
- VS_CAP_18
 
- VS_CAP_18_DONE
 
- VS_CAP_19
 
- VS_CAP_19_CMD_MASK
 
- VS_CAP_19_CMD_SHIFT
 
- VS_CAP_19_VALID
 
- VS_CAP_22
 
- VS_CAP_22_DMA_DELAY_MASK
 
- VS_CAP_22_DMA_DELAY_SHIFT
 
- VS_CAP_22_FORCE_POWER
 
- VS_CAP_9
 
- VS_CAP_9_FW_READY
 
- VS_CONTROL_PACKET_HEADER
 
- VS_CTL_REG
 
- VS_DATA_PACKET_HEADER
 
- VS_DEALLOC
 
- VS_DEBUGCLOCKENABLE
 
- VS_DEBUGOMC
 
- VS_DONE_TS
 
- VS_EN
 
- VS_FETCH_DONE
 
- VS_FORMAT_DIVX
 
- VS_FORMAT_MPEG2PS
 
- VS_FORMAT_MPEG2TS
 
- VS_FORMAT_MPEG4SL
 
- VS_FORMAT_RDS
 
- VS_FORMAT_TYPE
 
- VS_FORMAT_TYPE_I
 
- VS_FORMAT_UNCOMPRESSED
 
- VS_FORMAT_VBI
 
- VS_FORMAT_WM9
 
- VS_FRAME_UNCOMPRESSED
 
- VS_HDMI_IF
 
- VS_HDMI_IF_UPDATE
 
- VS_IE_FIXED_HDR_LEN
 
- VS_INVOCATION_COUNT
 
- VS_INVOCATION_COUNT_UDW
 
- VS_LEVEN_EN
 
- VS_LODD_EN
 
- VS_LT_10_16_SCALE
 
- VS_LT_11_16_SCALE
 
- VS_LT_12_16_SCALE
 
- VS_LT_13_16_SCALE
 
- VS_LT_14_16_SCALE
 
- VS_LT_15_16_SCALE
 
- VS_LT_16_16_SCALE
 
- VS_LT_9_16_SCALE
 
- VS_MASK
 
- VS_MPHYCFGUPDT
 
- VS_OUT_SEL
 
- VS_PARTIAL_FLUSH
 
- VS_POL_ACTIVE_LOW
 
- VS_POWERSTATE
 
- VS_PRIO
 
- VS_PS
 
- VS_QUERY_PACKET_HEADER
 
- VS_QUERY_RESPONSE_PACKET_HEADER
 
- VS_REVEN
 
- VS_RODD_EN
 
- VS_SAVEPOWERCONTROL
 
- VS_STAGE_COPY_SHADER
 
- VS_STAGE_DS
 
- VS_STAGE_REAL
 
- VS_TIMER_DISPATCH
 
- VS_UNIPROPOWERDOWNCONTROL
 
- VS_UP_SCALE
 
- VS_VREF_DELAY_MASK
 
- VS_VREF_DELAY_SHIFT
 
- VS_VREF_INV_SHIFT
 
- VS_VREF_SEL_MASK
 
- VS_VREF_SEL_NONE
 
- VS_VREF_SEL_SHIFT
 
- VS_VREF_SEL_VREF_HDMI
 
- VS_VREF_SEL_VREF_VHREF
 
- VS_VREF_SEL_VS_VHREF
 
- VS_WIDTH
 
- VT
 
- VT0
 
- VT1
 
- VT100ID
 
- VT102ID
 
- VT1211_REG_ALARM1
 
- VT1211_REG_ALARM2
 
- VT1211_REG_CONFIG
 
- VT1211_REG_FAN
 
- VT1211_REG_FAN_DIV
 
- VT1211_REG_FAN_MIN
 
- VT1211_REG_IN
 
- VT1211_REG_IN_MAX
 
- VT1211_REG_IN_MIN
 
- VT1211_REG_PWM
 
- VT1211_REG_PWM_AUTO_PWM
 
- VT1211_REG_PWM_AUTO_TEMP
 
- VT1211_REG_PWM_CLK
 
- VT1211_REG_PWM_CTL
 
- VT1211_REG_TEMP1_CONFIG
 
- VT1211_REG_TEMP2_CONFIG
 
- VT1211_REG_UCH_CONFIG
 
- VT1211_REG_VID
 
- VT1631_DEVICE_ID
 
- VT1631_DEVICE_ID_REG
 
- VT1631_LVDS
 
- VT1631_LVDS_I2C_ADDR
 
- VT1632_DEVICE_ID
 
- VT1632_DEVICE_ID_REG
 
- VT1632_TMDS
 
- VT1632_TMDS_I2C_ADDR
 
- VT1636_DPA_SETTING
 
- VT1636_LVDS
 
- VT1636_LVDS_I2C_ADDR
 
- VT1702
 
- VT1705CF
 
- VT1708
 
- VT1708BCE
 
- VT1708B_4CH
 
- VT1708B_8CH
 
- VT1708S
 
- VT1708_CD_PIN_NID
 
- VT1708_HP_PIN_NID
 
- VT1709_10CH
 
- VT1709_6CH
 
- VT1716S
 
- VT1718S
 
- VT1720_MOBO_DEVICE_DESC
 
- VT1720_SUBDEVICE_9CJS
 
- VT1720_SUBDEVICE_K8X800
 
- VT1720_SUBDEVICE_PONTIS_MS300
 
- VT1720_SUBDEVICE_SN25P
 
- VT1720_SUBDEVICE_ZNF3_150
 
- VT1720_SUBDEVICE_ZNF3_250
 
- VT1724_AC97_COLD
 
- VT1724_AC97_ID_MASK
 
- VT1724_AC97_READ
 
- VT1724_AC97_READY
 
- VT1724_AC97_WARM
 
- VT1724_AC97_WRITE
 
- VT1724_BUFFER_ALIGN
 
- VT1724_CFG_AC97_PACKED
 
- VT1724_CFG_ADC_MASK
 
- VT1724_CFG_ADC_NONE
 
- VT1724_CFG_CLOCK
 
- VT1724_CFG_CLOCK384
 
- VT1724_CFG_CLOCK512
 
- VT1724_CFG_DAC_MASK
 
- VT1724_CFG_I2S_192KHZ
 
- VT1724_CFG_I2S_96KHZ
 
- VT1724_CFG_I2S_CHIPID
 
- VT1724_CFG_I2S_OTHER
 
- VT1724_CFG_I2S_RESMASK
 
- VT1724_CFG_I2S_VOLUME
 
- VT1724_CFG_MPU401
 
- VT1724_CFG_PRO_I2S
 
- VT1724_CFG_SPDIF_IN
 
- VT1724_CFG_SPDIF_OUT
 
- VT1724_CFG_SPDIF_OUT_EN
 
- VT1724_CFG_SPDIF_OUT_INT
 
- VT1724_I2C_BUSY
 
- VT1724_I2C_EEPROM
 
- VT1724_I2C_WRITE
 
- VT1724_IRQ_MPU_RX
 
- VT1724_IRQ_MPU_TX
 
- VT1724_IRQ_MTPCM
 
- VT1724_MPU_FIFO_MASK
 
- VT1724_MPU_RX_EMPTY
 
- VT1724_MPU_RX_FIFO
 
- VT1724_MPU_RX_FULL
 
- VT1724_MPU_TX_EMPTY
 
- VT1724_MPU_TX_FULL
 
- VT1724_MPU_UART
 
- VT1724_MT_AC97_CMD
 
- VT1724_MT_AC97_DATA
 
- VT1724_MT_AC97_INDEX
 
- VT1724_MT_BURST
 
- VT1724_MT_CAPTURE_ADDR
 
- VT1724_MT_CAPTURE_COUNT
 
- VT1724_MT_CAPTURE_SIZE
 
- VT1724_MT_DMA_CONTROL
 
- VT1724_MT_DMA_FIFO_ERR
 
- VT1724_MT_DMA_INT_MASK
 
- VT1724_MT_DMA_PAUSE
 
- VT1724_MT_I2S_FORMAT
 
- VT1724_MT_I2S_FORMAT_I2S
 
- VT1724_MT_I2S_FORMAT_MASK
 
- VT1724_MT_I2S_MCLK_128X
 
- VT1724_MT_IRQ
 
- VT1724_MT_MONITOR_PEAKDATA
 
- VT1724_MT_MONITOR_PEAKINDEX
 
- VT1724_MT_PDMA1_ADDR
 
- VT1724_MT_PDMA1_COUNT
 
- VT1724_MT_PDMA1_SIZE
 
- VT1724_MT_PDMA2_ADDR
 
- VT1724_MT_PDMA2_COUNT
 
- VT1724_MT_PDMA2_SIZE
 
- VT1724_MT_PDMA3_ADDR
 
- VT1724_MT_PDMA3_COUNT
 
- VT1724_MT_PDMA3_SIZE
 
- VT1724_MT_PDMA4_ADDR
 
- VT1724_MT_PDMA4_COUNT
 
- VT1724_MT_PDMA4_SIZE
 
- VT1724_MT_PLAYBACK_ADDR
 
- VT1724_MT_PLAYBACK_COUNT
 
- VT1724_MT_PLAYBACK_SIZE
 
- VT1724_MT_RATE
 
- VT1724_MT_RDMA1_ADDR
 
- VT1724_MT_RDMA1_COUNT
 
- VT1724_MT_RDMA1_SIZE
 
- VT1724_MT_ROUTE_PLAYBACK
 
- VT1724_MT_SPDIF_CTRL
 
- VT1724_MULTI_FIFO_ERR
 
- VT1724_MULTI_PDMA0
 
- VT1724_MULTI_PDMA1
 
- VT1724_MULTI_PDMA2
 
- VT1724_MULTI_PDMA3
 
- VT1724_MULTI_PDMA4
 
- VT1724_MULTI_RDMA0
 
- VT1724_MULTI_RDMA1
 
- VT1724_PDMA0_PAUSE
 
- VT1724_PDMA0_START
 
- VT1724_PDMA0_UNDERRUN
 
- VT1724_PDMA1_PAUSE
 
- VT1724_PDMA1_START
 
- VT1724_PDMA1_UNDERRUN
 
- VT1724_PDMA2_PAUSE
 
- VT1724_PDMA2_START
 
- VT1724_PDMA2_UNDERRUN
 
- VT1724_PDMA3_PAUSE
 
- VT1724_PDMA3_START
 
- VT1724_PDMA3_UNDERRUN
 
- VT1724_PDMA4_PAUSE
 
- VT1724_PDMA4_START
 
- VT1724_PDMA4_UNDERRUN
 
- VT1724_PRODIGY192_CCLK
 
- VT1724_PRODIGY192_CDIN
 
- VT1724_PRODIGY192_CDOUT
 
- VT1724_PRODIGY192_CS
 
- VT1724_RDMA0_PAUSE
 
- VT1724_RDMA0_START
 
- VT1724_RDMA0_UNDERRUN
 
- VT1724_RDMA1_PAUSE
 
- VT1724_RDMA1_START
 
- VT1724_RDMA1_UNDERRUN
 
- VT1724_REG_AC97_CFG
 
- VT1724_REG_CONTROL
 
- VT1724_REG_GPIO_DATA
 
- VT1724_REG_GPIO_DATA_22
 
- VT1724_REG_GPIO_DIRECTION
 
- VT1724_REG_GPIO_WRITE_MASK
 
- VT1724_REG_GPIO_WRITE_MASK_22
 
- VT1724_REG_I2C_BYTE_ADDR
 
- VT1724_REG_I2C_CTRL
 
- VT1724_REG_I2C_DATA
 
- VT1724_REG_I2C_DEV_ADDR
 
- VT1724_REG_I2S_FEATURES
 
- VT1724_REG_IRQMASK
 
- VT1724_REG_IRQSTAT
 
- VT1724_REG_MPU_CTRL
 
- VT1724_REG_MPU_DATA
 
- VT1724_REG_MPU_FIFO_WM
 
- VT1724_REG_MPU_RXFIFO
 
- VT1724_REG_MPU_TXFIFO
 
- VT1724_REG_POWERDOWN
 
- VT1724_REG_SPDIF_CFG
 
- VT1724_REG_SYS_CFG
 
- VT1724_RESET
 
- VT1724_REVO_CCLK
 
- VT1724_REVO_CDIN
 
- VT1724_REVO_CDOUT
 
- VT1724_REVO_CS0
 
- VT1724_REVO_CS1
 
- VT1724_REVO_CS2
 
- VT1724_REVO_CS3
 
- VT1724_REVO_I2C_CLOCK
 
- VT1724_REVO_I2C_DATA
 
- VT1724_REVO_MUTE
 
- VT1724_SPDIF_MASTER
 
- VT1724_SUBDEVICE_AUDIO2000
 
- VT1724_SUBDEVICE_AUDIOPHILE192
 
- VT1724_SUBDEVICE_AUREON51_SKY
 
- VT1724_SUBDEVICE_AUREON71_SPACE
 
- VT1724_SUBDEVICE_AUREON71_UNIVERSE
 
- VT1724_SUBDEVICE_AV710
 
- VT1724_SUBDEVICE_FORTISSIMO4
 
- VT1724_SUBDEVICE_JULI
 
- VT1724_SUBDEVICE_MAYA44
 
- VT1724_SUBDEVICE_PHASE22
 
- VT1724_SUBDEVICE_PHASE28
 
- VT1724_SUBDEVICE_PRODIGY192VE
 
- VT1724_SUBDEVICE_PRODIGY71
 
- VT1724_SUBDEVICE_PRODIGY71LT
 
- VT1724_SUBDEVICE_PRODIGY71XT
 
- VT1724_SUBDEVICE_PRODIGY_HD2
 
- VT1724_SUBDEVICE_PRODIGY_HIFI
 
- VT1724_SUBDEVICE_PSC724
 
- VT1724_SUBDEVICE_QTET
 
- VT1724_SUBDEVICE_REVOLUTION51
 
- VT1724_SUBDEVICE_REVOLUTION71
 
- VT1724_SUBDEVICE_SE200PCI
 
- VT1724_SUBDEVICE_SE90PCI
 
- VT1724_SUBDEVICE_TS22
 
- VT1724_SUBDEVICE_WTM
 
- VT1802
 
- VT1808
 
- VT1812
 
- VT2002P
 
- VT2002P_COMPATIBLE
 
- VT3226_PWR_IDX_LEN
 
- VT3271_DEVICE_ID
 
- VT3271_DEVICE_ID_REG
 
- VT3271_LVDS_I2C_ADDR
 
- VT3342_PWR_IDX_LEN
 
- VT596_BLOCK_DATA
 
- VT596_BYTE
 
- VT596_BYTE_DATA
 
- VT596_I2C_BLOCK_DATA
 
- VT596_PROC_CALL
 
- VT596_QUICK
 
- VT596_WORD_DATA
 
- VT6102
 
- VT6105
 
- VT6105L
 
- VT6105M
 
- VT6105_B0
 
- VT6107
 
- VT8231
 
- VT8231_BASE_REG
 
- VT8231_ENABLE_REG
 
- VT8231_EXTENT
 
- VT8231_REG_ALARM1
 
- VT8231_REG_ALARM2
 
- VT8231_REG_CONFIG
 
- VT8231_REG_FAN
 
- VT8231_REG_FANDIV
 
- VT8231_REG_FAN_MIN
 
- VT8231_REG_TEMP1_CONFIG
 
- VT8231_REG_TEMP2_CONFIG
 
- VT8231_REG_TEMP_LOW01
 
- VT8231_REG_TEMP_LOW25
 
- VT8231_REG_UCH_CONFIG
 
- VT8233
 
- VT8235
 
- VT8237
 
- VT8237_FORCE_HPET_RESUME
 
- VT8500_BITS_TO_FREQ
 
- VT8500_BITS_TO_VAL
 
- VT8500_BREAK
 
- VT8500_CONSOLE
 
- VT8500_CS8
 
- VT8500_CSTOPB
 
- VT8500_DMA
 
- VT8500_EDGE
 
- VT8500_GPIO_MUX_REG
 
- VT8500_HAS_SWRTSCTS_SWITCH
 
- VT8500_HCR_REG
 
- VT8500_ICDC
 
- VT8500_ICIS
 
- VT8500_ICPC_FIQ
 
- VT8500_ICPC_IRQ
 
- VT8500_INTC_MAX
 
- VT8500_INT_DISABLE
 
- VT8500_INT_ENABLE
 
- VT8500_LOOPBK
 
- VT8500_MAX_PORTS
 
- VT8500_NR_PWMS
 
- VT8500_OVERSAMPLING_DIVISOR
 
- VT8500_PARENB
 
- VT8500_PARODD
 
- VT8500_PLL_DIV
 
- VT8500_PLL_MUL
 
- VT8500_PMC_BUSY_MASK
 
- VT8500_PMSR_REG
 
- VT8500_PSLVERR
 
- VT8500_RECOMMENDED_CLK
 
- VT8500_RTC_AS
 
- VT8500_RTC_CL
 
- VT8500_RTC_CR
 
- VT8500_RTC_CR_12H
 
- VT8500_RTC_CR_CALIB
 
- VT8500_RTC_CR_ENABLE
 
- VT8500_RTC_CR_SM_ENABLE
 
- VT8500_RTC_CR_SM_SEC
 
- VT8500_RTC_DR
 
- VT8500_RTC_DS
 
- VT8500_RTC_IS
 
- VT8500_RTC_IS_ALARM
 
- VT8500_RTC_ST
 
- VT8500_RTC_TR
 
- VT8500_RTC_TS
 
- VT8500_RTC_WS
 
- VT8500_RTS
 
- VT8500_RXEN
 
- VT8500_RXFIFO
 
- VT8500_SWRTSCTS
 
- VT8500_TIMER_HZ
 
- VT8500_TIMER_OFFSET
 
- VT8500_TRIGGER_FALLING
 
- VT8500_TRIGGER_HIGH
 
- VT8500_TRIGGER_RISING
 
- VT8500_TXEN
 
- VT8500_TXFIFO
 
- VT8500_URBKR
 
- VT8500_URDIV
 
- VT8500_URFCR
 
- VT8500_URFIDX
 
- VT8500_URICR
 
- VT8500_URIER
 
- VT8500_URISR
 
- VT8500_URLCR
 
- VT8500_URRDR
 
- VT8500_URTDR
 
- VT8500_URTOD
 
- VT8500_URUSR
 
- VT86C100A
 
- VTAG0_LID_MASK
 
- VTAG0_RELPTR_MASK
 
- VTAG0_TYPE_MASK
 
- VTAG0_VALID_BIT
 
- VTAGSIZE_T4
 
- VTAGSIZE_T8
 
- VTAG_EN
 
- VTA_CMD_CLEAR
 
- VTA_CMD_READ
 
- VTA_CMD_WRITE
 
- VTA_RW_OP_EN
 
- VTA_RW_STATE
 
- VTA_RW_STATE_RD
 
- VTA_RW_STATE_WR
 
- VTA_START_CMD
 
- VTA_VID_HIGH_MASK_25
 
- VTA_VID_HIGH_MASK_65
 
- VTA_VID_HIGH_S_25
 
- VTA_VID_HIGH_S_65
 
- VTA_VID_LOW_MASK_25
 
- VTA_VID_LOW_MASK_65
 
- VTBL_ADDR_INDEX_MASK
 
- VTB_EXT
 
- VTCR
 
- VTCR_BUSY
 
- VTCR_EL2_COMMON_BITS
 
- VTCR_EL2_FLAGS
 
- VTCR_EL2_HA
 
- VTCR_EL2_HD
 
- VTCR_EL2_IPA
 
- VTCR_EL2_IRGN0_MASK
 
- VTCR_EL2_IRGN0_WBWA
 
- VTCR_EL2_LVLS
 
- VTCR_EL2_LVLS_TO_SL0
 
- VTCR_EL2_ORGN0_MASK
 
- VTCR_EL2_ORGN0_WBWA
 
- VTCR_EL2_PS_MASK
 
- VTCR_EL2_PS_SHIFT
 
- VTCR_EL2_RES1
 
- VTCR_EL2_SH0_INNER
 
- VTCR_EL2_SH0_MASK
 
- VTCR_EL2_SL0_MASK
 
- VTCR_EL2_SL0_SHIFT
 
- VTCR_EL2_SL0_TO_LVLS
 
- VTCR_EL2_T0SZ
 
- VTCR_EL2_T0SZ_MASK
 
- VTCR_EL2_TG0_16K
 
- VTCR_EL2_TG0_4K
 
- VTCR_EL2_TG0_64K
 
- VTCR_EL2_TG0_MASK
 
- VTCR_EL2_TGRAN
 
- VTCR_EL2_TGRAN_SL0_BASE
 
- VTCR_EL2_VS_16BIT
 
- VTCR_EL2_VS_8BIT
 
- VTCR_EL2_VS_SHIFT
 
- VTCR_FUNC
 
- VTCR_GCHK
 
- VTCR_HTCR_SH
 
- VTCR_INIT_VALUE
 
- VTCR_INVALID
 
- VTCR_IRGN0
 
- VTCR_MASK
 
- VTCR_ORGN0
 
- VTCR_PPCHK
 
- VTCR_S
 
- VTCR_SH0
 
- VTCR_SL0
 
- VTCR_SL_L1
 
- VTCR_SL_L2
 
- VTCR_T0SZ
 
- VTCR_VGTI
 
- VTCR_VID
 
- VTCR_VPPTI
 
- VTDIVMODE
 
- VTDLY
 
- VTD_FLAG_IRQ_REMAP_PRE_ENABLED
 
- VTD_FLAG_TRANS_PRE_ENABLED
 
- VTD_MSK_SPEC_ERRORS
 
- VTD_PAGE_ALIGN
 
- VTD_PAGE_MASK
 
- VTD_PAGE_SHIFT
 
- VTD_PAGE_SIZE
 
- VTD_STRIDE_MASK
 
- VTD_STRIDE_SHIFT
 
- VTEM_MD0
 
- VTEM_MD1
 
- VTEM_MD2
 
- VTEM_MD3
 
- VTEM_PB0
 
- VTEM_PB1
 
- VTEM_PB2
 
- VTEM_PB3
 
- VTEM_PB4
 
- VTEM_PB5
 
- VTEM_PB6
 
- VTE_MEMBERS
 
- VTE_UNTAG
 
- VTE_UNTAG_S
 
- VTFT
 
- VTFT_FILTERTARGET
 
- VTFT_FILTERTARGET_MASK
 
- VTFT_VOLUMETARGET
 
- VTFT_VOLUMETARGET_MASK
 
- VTG0_CONTROL__VTG0_ENABLE_MASK
 
- VTG0_CONTROL__VTG0_ENABLE__SHIFT
 
- VTG0_CONTROL__VTG0_FP2_MASK
 
- VTG0_CONTROL__VTG0_FP2__SHIFT
 
- VTG0_CONTROL__VTG0_VCOUNT_INIT_MASK
 
- VTG0_CONTROL__VTG0_VCOUNT_INIT__SHIFT
 
- VTG1_CONTROL__VTG1_ENABLE_MASK
 
- VTG1_CONTROL__VTG1_ENABLE__SHIFT
 
- VTG1_CONTROL__VTG1_FP2_MASK
 
- VTG1_CONTROL__VTG1_FP2__SHIFT
 
- VTG1_CONTROL__VTG1_VCOUNT_INIT_MASK
 
- VTG1_CONTROL__VTG1_VCOUNT_INIT__SHIFT
 
- VTG2_CONTROL__VTG2_ENABLE_MASK
 
- VTG2_CONTROL__VTG2_ENABLE__SHIFT
 
- VTG2_CONTROL__VTG2_FP2_MASK
 
- VTG2_CONTROL__VTG2_FP2__SHIFT
 
- VTG2_CONTROL__VTG2_VCOUNT_INIT_MASK
 
- VTG2_CONTROL__VTG2_VCOUNT_INIT__SHIFT
 
- VTG3_CONTROL__VTG3_ENABLE_MASK
 
- VTG3_CONTROL__VTG3_ENABLE__SHIFT
 
- VTG3_CONTROL__VTG3_FP2_MASK
 
- VTG3_CONTROL__VTG3_FP2__SHIFT
 
- VTG3_CONTROL__VTG3_VCOUNT_INIT_MASK
 
- VTG3_CONTROL__VTG3_VCOUNT_INIT__SHIFT
 
- VTG4_CONTROL__VTG4_ENABLE_MASK
 
- VTG4_CONTROL__VTG4_ENABLE__SHIFT
 
- VTG4_CONTROL__VTG4_FP2_MASK
 
- VTG4_CONTROL__VTG4_FP2__SHIFT
 
- VTG4_CONTROL__VTG4_VCOUNT_INIT_MASK
 
- VTG4_CONTROL__VTG4_VCOUNT_INIT__SHIFT
 
- VTG5_CONTROL__VTG5_ENABLE_MASK
 
- VTG5_CONTROL__VTG5_ENABLE__SHIFT
 
- VTG5_CONTROL__VTG5_FP2_MASK
 
- VTG5_CONTROL__VTG5_FP2__SHIFT
 
- VTG5_CONTROL__VTG5_VCOUNT_INIT_MASK
 
- VTG5_CONTROL__VTG5_VCOUNT_INIT__SHIFT
 
- VTG_BOTTOM_FIELD_EVENT
 
- VTG_BOT_V_HD_1
 
- VTG_BOT_V_HD_2
 
- VTG_BOT_V_HD_3
 
- VTG_BOT_V_HD_4
 
- VTG_BOT_V_VD_1
 
- VTG_BOT_V_VD_2
 
- VTG_BOT_V_VD_3
 
- VTG_BOT_V_VD_4
 
- VTG_CLKLN
 
- VTG_DRST_AUTOC
 
- VTG_HLFLN
 
- VTG_HOST_ITM_BCLR
 
- VTG_HOST_ITM_BSET
 
- VTG_HOST_ITS
 
- VTG_HOST_ITS_BCLR
 
- VTG_H_HD_1
 
- VTG_H_HD_2
 
- VTG_H_HD_3
 
- VTG_H_HD_4
 
- VTG_IRQ_BOTTOM
 
- VTG_IRQ_MASK
 
- VTG_IRQ_TOP
 
- VTG_MAX_SYNC_OUTPUT
 
- VTG_MODE
 
- VTG_MODE_MASTER
 
- VTG_SEL_0
 
- VTG_SEL_1
 
- VTG_SEL_2
 
- VTG_SEL_3
 
- VTG_SEL_4
 
- VTG_SEL_5
 
- VTG_SYNC_ID_DVO
 
- VTG_SYNC_ID_HDDCS
 
- VTG_SYNC_ID_HDF
 
- VTG_SYNC_ID_HDMI
 
- VTG_TOP_FIELD_EVENT
 
- VTG_TOP_V_HD_1
 
- VTG_TOP_V_HD_2
 
- VTG_TOP_V_HD_3
 
- VTG_TOP_V_HD_4
 
- VTG_TOP_V_VD_1
 
- VTG_TOP_V_VD_2
 
- VTG_TOP_V_VD_3
 
- VTG_TOP_V_VD_4
 
- VTG_VID_BFO
 
- VTG_VID_BFS
 
- VTG_VID_TFO
 
- VTG_VID_TFS
 
- VTH12
 
- VTH23
 
- VTH34
 
- VTH56
 
- VTH67
 
- VTH78
 
- VTHINUSE
 
- VTIM01
 
- VTIM02
 
- VTIM1
 
- VTIM2
 
- VTIME
 
- VTIMER_MAX_SLICE
 
- VTIME_INACTIVE
 
- VTIME_PER_SEC
 
- VTIME_PER_SEC_SHIFT
 
- VTIME_PER_USEC
 
- VTIME_SYS
 
- VTIME_USER
 
- VTIME_VALID_DUR
 
- VTI_ISVTI
 
- VTOB_HASH_CODE
 
- VTOB_HASH_MASK
 
- VTOB_HASH_SHIFT
 
- VTOB_HASH_SIZE
 
- VTOP
 
- VTOP_INVALID
 
- VTOP_RETRY
 
- VTOP_SUCCESS
 
- VTOTAL
 
- VTOTAL_A
 
- VTOTAL_B
 
- VTOTAL_C
 
- VTOTAL_MASK
 
- VTOTAL_SHIFT
 
- VTPM_BASE_ADDRESS
 
- VTPM_GET_RTCE_BUFFER_SIZE
 
- VTPM_GET_RTCE_BUFFER_SIZE_RES
 
- VTPM_GET_VERSION
 
- VTPM_GET_VERSION_RES
 
- VTPM_MSG_RES
 
- VTPM_PREPARE_TO_SUSPEND
 
- VTPM_PREPARE_TO_SUSPEND_RES
 
- VTPM_PROXY_FLAGS_ALL
 
- VTPM_PROXY_FLAG_TPM2
 
- VTPM_PROXY_IOC_NEW_DEV
 
- VTPM_PROXY_REQ_COMPLETE_FLAG
 
- VTPM_STATE_CANCEL
 
- VTPM_STATE_FINISH
 
- VTPM_STATE_IDLE
 
- VTPM_STATE_SUBMIT
 
- VTPM_STATUS_CANCELED
 
- VTPM_STATUS_IDLE
 
- VTPM_STATUS_RESULT
 
- VTPM_STATUS_RUNNING
 
- VTPM_TPM_COMMAND
 
- VTPM_TPM_COMMAND_RES
 
- VTS1
 
- VTS2
 
- VTS3
 
- VTS4
 
- VTS5
 
- VTSABB
 
- VTT
 
- VTTBR
 
- VTTBR_BADDR_MASK
 
- VTTBR_CNP_BIT
 
- VTTBR_VMID_MASK
 
- VTTBR_VMID_SHIFT
 
- VTTBR_X
 
- VTUNCERRMSK_REG
 
- VTVOUT_V
 
- VTX_CLAMP
 
- VTX_Clamp_ClampToNAN
 
- VTX_Clamp_ClampToZero
 
- VTX_DONE_DELAY
 
- VTX_FETCH_TYPE
 
- VTX_FORMAT_COMP_ALL
 
- VTX_FetchType_InstanceData
 
- VTX_FetchType_NoIndexOffset
 
- VTX_FetchType_RESERVED_3
 
- VTX_FetchType_VertexData
 
- VTX_FormatCompAll_Signed
 
- VTX_FormatCompAll_Unsigned
 
- VTX_MEM_REQUEST_SIZE
 
- VTX_MemRequestSize_32B
 
- VTX_MemRequestSize_64B
 
- VTX_REUSE_DEPTH_MASK
 
- VT_50HZ
 
- VT_60HZ
 
- VT_ACKACQ
 
- VT_ACTIVATE
 
- VT_ADC_CTRL0_REG
 
- VT_ADC_CTRL1_REG
 
- VT_ADC_CTRL2_REG
 
- VT_ADC_MD_REG
 
- VT_ALLOCATE
 
- VT_AUTO
 
- VT_BUF_HAVE_MEMCPYW
 
- VT_BUF_HAVE_MEMMOVEW
 
- VT_BUF_HAVE_MEMSETW
 
- VT_BUF_HAVE_RW
 
- VT_CHIP_ID
 
- VT_DEALLOCATE
 
- VT_DISALLOCATE
 
- VT_EVENT_BLANK
 
- VT_EVENT_RESIZE
 
- VT_EVENT_SWITCH
 
- VT_EVENT_UNBLANK
 
- VT_GETHIFONTMASK
 
- VT_GETMODE
 
- VT_GETSTATE
 
- VT_LOCKSWITCH
 
- VT_MAX_EVENT
 
- VT_OPENQRY
 
- VT_PREWRITE
 
- VT_PROCESS
 
- VT_RELDISP
 
- VT_RESIZE
 
- VT_RESIZEX
 
- VT_SENDSIG
 
- VT_SETACTIVATE
 
- VT_SETMODE
 
- VT_TRIGGER
 
- VT_UNLOCKSWITCH
 
- VT_UPDATE
 
- VT_WAITACTIVE
 
- VT_WAITEVENT
 
- VT_WRITE
 
- VTunknown0
 
- VTunknown1
 
- VTunknown2
 
- VUB300_PRODUCT_ID
 
- VUB300_VENDOR_ID
 
- VUBASE
 
- VUBASE_UBASE_ADR
 
- VUBASE_UVHALFSTR
 
- VUDC_DEVICE_DESCR_FILE
 
- VUDC_EVENT_DOWN
 
- VUDC_EVENT_ERROR_MALLOC
 
- VUDC_EVENT_ERROR_TCP
 
- VUDC_EVENT_ERROR_USB
 
- VUDC_EVENT_REMOVED
 
- VUDC_TR_IDLE
 
- VUDC_TR_RUNNING
 
- VUDC_TR_STOPPED
 
- VUL12_4CH_MASK
 
- VUL12_4CH_MASK_SFT
 
- VUL12_4CH_SFT
 
- VUL12_AXI_WR_SIGN_MASK
 
- VUL12_AXI_WR_SIGN_MASK_SFT
 
- VUL12_AXI_WR_SIGN_SFT
 
- VUL12_HD_ALIGN_MASK
 
- VUL12_HD_ALIGN_MASK_SFT
 
- VUL12_HD_ALIGN_SFT
 
- VUL12_HD_MASK
 
- VUL12_HD_MASK_SFT
 
- VUL12_HD_SFT
 
- VUL12_MODE_MASK
 
- VUL12_MODE_MASK_SFT
 
- VUL12_MODE_SFT
 
- VUL12_MONO_MASK
 
- VUL12_MONO_MASK_SFT
 
- VUL12_MONO_SFT
 
- VUL12_NORMAL_MODE_MASK
 
- VUL12_NORMAL_MODE_MASK_SFT
 
- VUL12_NORMAL_MODE_SFT
 
- VUL12_ON_MASK
 
- VUL12_ON_MASK_SFT
 
- VUL12_ON_SFT
 
- VUL12_R_MONO_MASK
 
- VUL12_R_MONO_MASK_SFT
 
- VUL12_R_MONO_SFT
 
- VUL2_AXI_WR_SIGN_MASK
 
- VUL2_AXI_WR_SIGN_MASK_SFT
 
- VUL2_AXI_WR_SIGN_SFT
 
- VUL2_DATA_MASK
 
- VUL2_DATA_MASK_SFT
 
- VUL2_DATA_SFT
 
- VUL2_HD_ALIGN_MASK
 
- VUL2_HD_ALIGN_MASK_SFT
 
- VUL2_HD_ALIGN_SFT
 
- VUL2_HD_MASK
 
- VUL2_HD_MASK_SFT
 
- VUL2_HD_SFT
 
- VUL2_MODE_MASK
 
- VUL2_MODE_MASK_SFT
 
- VUL2_MODE_SFT
 
- VUL2_NORMAL_MODE_MASK
 
- VUL2_NORMAL_MODE_MASK_SFT
 
- VUL2_NORMAL_MODE_SFT
 
- VUL2_ON_MASK
 
- VUL2_ON_MASK_SFT
 
- VUL2_ON_SFT
 
- VUL2_R_MONO_MASK
 
- VUL2_R_MONO_MASK_SFT
 
- VUL2_R_MONO_SFT
 
- VULNBL_INTEL_STEPPINGS
 
- VULNWL
 
- VULNWL_AMD
 
- VULNWL_HYGON
 
- VULNWL_INTEL
 
- VUL_AXI_WR_SIGN_MASK
 
- VUL_AXI_WR_SIGN_MASK_SFT
 
- VUL_AXI_WR_SIGN_SFT
 
- VUL_DATA2_DATA_MASK
 
- VUL_DATA2_DATA_MASK_SFT
 
- VUL_DATA2_DATA_SFT
 
- VUL_DATA2_HD_ALIGN_MASK
 
- VUL_DATA2_HD_ALIGN_MASK_SFT
 
- VUL_DATA2_HD_ALIGN_SFT
 
- VUL_DATA2_HD_MASK
 
- VUL_DATA2_HD_MASK_SFT
 
- VUL_DATA2_HD_SFT
 
- VUL_DATA2_MODE_MASK
 
- VUL_DATA2_MODE_MASK_SFT
 
- VUL_DATA2_MODE_SFT
 
- VUL_DATA2_NORMAL_MODE_MASK
 
- VUL_DATA2_NORMAL_MODE_MASK_SFT
 
- VUL_DATA2_NORMAL_MODE_SFT
 
- VUL_DATA2_ON_MASK
 
- VUL_DATA2_ON_MASK_SFT
 
- VUL_DATA2_ON_SFT
 
- VUL_DATA2_R_MONO_MASK
 
- VUL_DATA2_R_MONO_MASK_SFT
 
- VUL_DATA2_R_MONO_SFT
 
- VUL_DATA_MASK
 
- VUL_DATA_MASK_SFT
 
- VUL_DATA_SFT
 
- VUL_HD_ALIGN_MASK
 
- VUL_HD_ALIGN_MASK_SFT
 
- VUL_HD_ALIGN_SFT
 
- VUL_HD_MASK
 
- VUL_HD_MASK_SFT
 
- VUL_HD_SFT
 
- VUL_MODE_MASK
 
- VUL_MODE_MASK_SFT
 
- VUL_MODE_SFT
 
- VUL_NORMAL_MODE_MASK
 
- VUL_NORMAL_MODE_MASK_SFT
 
- VUL_NORMAL_MODE_SFT
 
- VUL_ON_MASK
 
- VUL_ON_MASK_SFT
 
- VUL_ON_SFT
 
- VUL_R_MONO_MASK
 
- VUL_R_MONO_MASK_SFT
 
- VUL_R_MONO_SFT
 
- VUSB1V5_DEV_GRP
 
- VUSB1V5_REMAP
 
- VUSB1V5_TYPE
 
- VUSB1V8_DEV_GRP
 
- VUSB1V8_REMAP
 
- VUSB1V8_TYPE
 
- VUSB3V1_DEV_GRP
 
- VUSB3V1_REMAP
 
- VUSB3V1_TYPE
 
- VUSBHS_MAX_PORTS
 
- VUSBPHY_CHARGE
 
- VUSB_CFG_STATE
 
- VUSB_CFG_TRANS
 
- VUSB_CFG_VOLTAGE
 
- VUSB_DEDICATED1
 
- VUSB_DEDICATED2
 
- VU_CHIP_ID
 
- VU_METER_CHANNELS
 
- VV
 
- VV6410_ANALOGGAIN
 
- VV6410_AS0
 
- VV6410_AT0
 
- VV6410_AT1
 
- VV6410_BLACKAVGH
 
- VV6410_BLACKAVGL
 
- VV6410_BLACKOFFSETH
 
- VV6410_BLACKOFFSETL
 
- VV6410_BLACKOFFSETSETUP
 
- VV6410_CIF_LINELENGTH
 
- VV6410_CLKDIV
 
- VV6410_CLK_DIV_2
 
- VV6410_COARSEH
 
- VV6410_COARSEL
 
- VV6410_COARSE_EXPOSURE
 
- VV6410_COLS
 
- VV6410_CR0
 
- VV6410_CR1
 
- VV6410_CROP_TO_QVGA
 
- VV6410_DARKAVGH
 
- VV6410_DARKAVGL
 
- VV6410_DARKOFFSETH
 
- VV6410_DARKOFFSETL
 
- VV6410_DARKOFFSETSETUP
 
- VV6410_DATAFORMAT
 
- VV6410_DEFAULT_GAIN
 
- VV6410_DEVICEH
 
- VV6410_DEVICEL
 
- VV6410_FGMODES
 
- VV6410_FIELDLENGTHH
 
- VV6410_FIELDLENGTHL
 
- VV6410_FINEH
 
- VV6410_FINEL
 
- VV6410_FINE_EXPOSURE
 
- VV6410_HFLIP
 
- VV6410_LINECOUNTH
 
- VV6410_LINECOUNTL
 
- VV6410_LINELENGTHH
 
- VV6410_LINELENGTHL
 
- VV6410_LOW_POWER_MODE
 
- VV6410_MODESELECT
 
- VV6410_OPFORMAT
 
- VV6410_PAL_25_FPS
 
- VV6410_PINMAPPING
 
- VV6410_ROWS
 
- VV6410_SETUP0
 
- VV6410_SETUP1
 
- VV6410_SOFT_RESET
 
- VV6410_STATUS0
 
- VV6410_STATUS1
 
- VV6410_SUBSAMPLE
 
- VV6410_SYNCVALUE
 
- VV6410_VFLIP
 
- VV6410_XENDH
 
- VV6410_XENDL
 
- VV6410_XOFFSETH
 
- VV6410_XOFFSETL
 
- VV6410_YENDH
 
- VV6410_YENDL
 
- VV6410_YOFFSETH
 
- VV6410_YOFFSETL
 
- VVAR
 
- VVBASE
 
- VVBASE_VBASE_ADR
 
- VVBI
 
- VVIB
 
- VVOLEXISTS
 
- VV_CHIP_ID
 
- VV_HIGH_TH_SET
 
- VV_LOW_TH_SET
 
- VWERASE
 
- VX
 
- VX2_AKM_LEVEL_MAX
 
- VX800_FUNCTION3
 
- VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM
 
- VX800_IGA1_FIFO_HIGH_THRESHOLD
 
- VX800_IGA1_FIFO_MAX_DEPTH
 
- VX800_IGA1_FIFO_THRESHOLD
 
- VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM
 
- VX800_IGA2_FIFO_HIGH_THRESHOLD
 
- VX800_IGA2_FIFO_MAX_DEPTH
 
- VX800_IGA2_FIFO_THRESHOLD
 
- VX855_CFG_PMIO_OFFSET
 
- VX855_FUNCTION3
 
- VX855_GENL_PURPOSE_OUTPUT
 
- VX855_GPI
 
- VX855_GPIO
 
- VX855_GPI_SCI_SMI
 
- VX855_GPI_STATUS_CHG
 
- VX855_GPO
 
- VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM
 
- VX855_IGA1_FIFO_HIGH_THRESHOLD
 
- VX855_IGA1_FIFO_MAX_DEPTH
 
- VX855_IGA1_FIFO_THRESHOLD
 
- VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM
 
- VX855_IGA2_FIFO_HIGH_THRESHOLD
 
- VX855_IGA2_FIFO_MAX_DEPTH
 
- VX855_IGA2_FIFO_THRESHOLD
 
- VX855_PMIO_ACPI
 
- VX855_PMIO_ACPI_LEN
 
- VX855_PMIO_GPPM
 
- VX855_PMIO_GPPM_LEN
 
- VX855_PMIO_PPM
 
- VX855_PMIO_PPM_LEN
 
- VX855_PMIO_R_GPI
 
- VX855_PMIO_R_GPO
 
- VX900_FUNCTION3
 
- VX900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM
 
- VX900_IGA1_FIFO_HIGH_THRESHOLD
 
- VX900_IGA1_FIFO_MAX_DEPTH
 
- VX900_IGA1_FIFO_THRESHOLD
 
- VX900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM
 
- VX900_IGA2_FIFO_HIGH_THRESHOLD
 
- VX900_IGA2_FIFO_MAX_DEPTH
 
- VX900_IGA2_FIFO_THRESHOLD
 
- VXA
 
- VXASH
 
- VXASHB_MASK
 
- VXASH_MASK
 
- VXATTR_FLAG_HIDDEN
 
- VXATTR_FLAG_READONLY
 
- VXATTR_FLAG_RSTAT
 
- VXA_MASK
 
- VXCAN_INFO_MAX
 
- VXCAN_INFO_PEER
 
- VXCAN_INFO_UNSPEC
 
- VXDMP_MAJOR
 
- VXFS_BLOCK_PER_PAGE
 
- VXFS_BO_BE
 
- VXFS_BO_LE
 
- VXFS_DIRBLKOV
 
- VXFS_DIRLEN
 
- VXFS_DIRPAD
 
- VXFS_DIRROUND
 
- VXFS_IEXEC
 
- VXFS_IFATT
 
- VXFS_IFAUS
 
- VXFS_IFBLK
 
- VXFS_IFCHR
 
- VXFS_IFCMP
 
- VXFS_IFCUT
 
- VXFS_IFDEV
 
- VXFS_IFDIR
 
- VXFS_IFEAU
 
- VXFS_IFEMP
 
- VXFS_IFEMR
 
- VXFS_IFFSH
 
- VXFS_IFIAT
 
- VXFS_IFIAU
 
- VXFS_IFIFO
 
- VXFS_IFILT
 
- VXFS_IFLAB
 
- VXFS_IFLCT
 
- VXFS_IFLNK
 
- VXFS_IFLOG
 
- VXFS_IFNAM
 
- VXFS_IFOLT
 
- VXFS_IFPTI
 
- VXFS_IFQUO
 
- VXFS_IFREG
 
- VXFS_IFSOC
 
- VXFS_INO
 
- VXFS_IREAD
 
- VXFS_ISBLK
 
- VXFS_ISCHR
 
- VXFS_ISCMP
 
- VXFS_ISDIR
 
- VXFS_ISEXT4
 
- VXFS_ISFIFO
 
- VXFS_ISFSH
 
- VXFS_ISGID
 
- VXFS_ISILT
 
- VXFS_ISIMMED
 
- VXFS_ISIZE
 
- VXFS_ISLNK
 
- VXFS_ISNAM
 
- VXFS_ISNONE
 
- VXFS_ISREG
 
- VXFS_ISSOC
 
- VXFS_ISTYPED
 
- VXFS_ISUID
 
- VXFS_ISVTX
 
- VXFS_IS_ORG
 
- VXFS_IS_TYPE
 
- VXFS_IWRITE
 
- VXFS_NAMELEN
 
- VXFS_NAMEMIN
 
- VXFS_NDADDR
 
- VXFS_NEFREE
 
- VXFS_NIADDR
 
- VXFS_NIMMED
 
- VXFS_NTYPED
 
- VXFS_OLT_CUT
 
- VXFS_OLT_DEV
 
- VXFS_OLT_FREE
 
- VXFS_OLT_FSHEAD
 
- VXFS_OLT_ILIST
 
- VXFS_OLT_MAGIC
 
- VXFS_OLT_SB
 
- VXFS_ORG_EXT4
 
- VXFS_ORG_IMMED
 
- VXFS_ORG_NONE
 
- VXFS_ORG_TYPED
 
- VXFS_ROOT_INO
 
- VXFS_SBI
 
- VXFS_SUPER_MAGIC
 
- VXFS_TYPED_DATA
 
- VXFS_TYPED_DATA_DEV4
 
- VXFS_TYPED_INDIRECT
 
- VXFS_TYPED_INDIRECT_DEV4
 
- VXFS_TYPED_OFFSETMASK
 
- VXFS_TYPED_PER_BLOCK
 
- VXFS_TYPED_TYPEMASK
 
- VXFS_TYPED_TYPESHIFT
 
- VXFS_TYPE_MASK
 
- VXGE_ALARM_MSIX_ID
 
- VXGE_ALIGN
 
- VXGE_ALL_VID_DISABLE
 
- VXGE_ALL_VID_ENABLE
 
- VXGE_CACHE_LINE_SIZE
 
- VXGE_CERT_FW_VER
 
- VXGE_CERT_FW_VER_BUILD
 
- VXGE_CERT_FW_VER_MAJOR
 
- VXGE_CERT_FW_VER_MINOR
 
- VXGE_COMPLETE_ALL_RX
 
- VXGE_COMPLETE_ALL_TX
 
- VXGE_COMPLETE_VPATH_TX
 
- VXGE_COMPONENT_ALL
 
- VXGE_COMPONENT_LL
 
- VXGE_CONFIG_H
 
- VXGE_COPY_DEBUG_INFO_TO_LL
 
- VXGE_DEAD_FW_VER_BUILD
 
- VXGE_DEAD_FW_VER_MAJOR
 
- VXGE_DEAD_FW_VER_MINOR
 
- VXGE_DEBUG_ENTRYEXIT
 
- VXGE_DEBUG_ERR_MASK
 
- VXGE_DEBUG_INIT
 
- VXGE_DEBUG_INTR
 
- VXGE_DEBUG_LL_CONFIG
 
- VXGE_DEBUG_LOCK
 
- VXGE_DEBUG_MASK
 
- VXGE_DEBUG_MEM
 
- VXGE_DEBUG_MODULE_MASK
 
- VXGE_DEBUG_RX
 
- VXGE_DEBUG_SEM
 
- VXGE_DEBUG_TRACE_MASK
 
- VXGE_DEBUG_TX
 
- VXGE_DEF_FIFO_LENGTH
 
- VXGE_DEVICE_DEBUG_LEVEL_SET
 
- VXGE_DRIVER_FW_VERSION_MAJOR
 
- VXGE_DRIVER_NAME
 
- VXGE_DRIVER_VENDOR
 
- VXGE_EPROM_FW_VER
 
- VXGE_EPROM_FW_VER_BUILD
 
- VXGE_EPROM_FW_VER_MAJOR
 
- VXGE_EPROM_FW_VER_MINOR
 
- VXGE_EPROM_IMG_BUILD
 
- VXGE_EPROM_IMG_FIX
 
- VXGE_EPROM_IMG_MAJOR
 
- VXGE_EPROM_IMG_MINOR
 
- VXGE_ERR
 
- VXGE_EXEC_MODE_DISABLE
 
- VXGE_EXEC_MODE_ENABLE
 
- VXGE_FIFO_INDICATE_MAX_PKTS
 
- VXGE_FLICKER_OFF
 
- VXGE_FLICKER_ON
 
- VXGE_FW_DEAD_VER
 
- VXGE_FW_UPGRADE_BYTES2SKIP
 
- VXGE_FW_VER
 
- VXGE_HAL_SRPCIM_TO_MRPCIM_VPLANE_RMSG_SWIF_SRPCIM_TO_MRPCIM_VPLANE_RMSG
 
- VXGE_HW_ADAPTER_READY_ADAPTER_READY
 
- VXGE_HW_ADAPTER_STATUS_CMG_C_PLL_IN_LOCK
 
- VXGE_HW_ADAPTER_STATUS_FBIF_M_PLL_IN_LOCK
 
- VXGE_HW_ADAPTER_STATUS_G3IF_CM_G3IF_CM_GDDR3_READY
 
- VXGE_HW_ADAPTER_STATUS_G3IF_FB_G3IF_FB_GDDR3_READY
 
- VXGE_HW_ADAPTER_STATUS_KDFC_KDFC_READY
 
- VXGE_HW_ADAPTER_STATUS_PCC_PCC_IDLE
 
- VXGE_HW_ADAPTER_STATUS_RDCTL_PIC_QUIESCENT
 
- VXGE_HW_ADAPTER_STATUS_RIC_RIC_RUNNING
 
- VXGE_HW_ADAPTER_STATUS_ROCRC_OFFLOAD_QUIESCENT
 
- VXGE_HW_ADAPTER_STATUS_ROCRC_RC_PRC_QUIESCENT
 
- VXGE_HW_ADAPTER_STATUS_RTDMA_RTDMA_READY
 
- VXGE_HW_ADAPTER_STATUS_TPA_TMAC_BUF_EMPTY
 
- VXGE_HW_ADAPTER_STATUS_WRDMA_WRDMA_READY
 
- VXGE_HW_ADAPTER_STATUS_XGMAC_NETWORK_FAULT
 
- VXGE_HW_ADAPTER_STATUS_XGMAC_X_PLL_IN_LOCK
 
- VXGE_HW_AGGR_STATS_LEN
 
- VXGE_HW_ALL_FOXES
 
- VXGE_HW_ANBE_CFG_PORT_ALIGN_10G_KX4_OVERRIDE
 
- VXGE_HW_ANBE_CFG_PORT_RESET_CFG_REGS
 
- VXGE_HW_ANBE_CFG_PORT_SYNC_1G_KX_OVERRIDE
 
- VXGE_HW_ANBE_FW_MSTR_PORT_CONNECT_BEAN_TO_SERDES
 
- VXGE_HW_ANBE_FW_MSTR_PORT_TX_ZEROES_TO_SERDES
 
- VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_10G_KR_CAPABLE
 
- VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_10G_KX4_CAPABLE
 
- VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_1G_KX_CAPABLE
 
- VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ACK
 
- VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ASM_DIR
 
- VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ECHOED_NONCE
 
- VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_FEC_ABILITY
 
- VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_FEC_ENABLE
 
- VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_NP
 
- VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_PAUSE
 
- VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_REMOTE_FAULT
 
- VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_SELECTOR_FIELD
 
- VXGE_HW_ANBE_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_TX_NONCE
 
- VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_ANBEFSM_STATE
 
- VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_BEAN_AUTONEG_COMPLETE
 
- VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_BEAN_BASE_PAGE_RECEIVED
 
- VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_BEAN_NEXT_PAGE_RECEIVED
 
- VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_10G_KX4_USING_DME
 
- VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_10G_KX4_USING_PD
 
- VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_1G_KX_USING_DME
 
- VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_1G_KX_USING_PD
 
- VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_COUNT_BP
 
- VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_COUNT_NP
 
- VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_AN_COMPLETE_BEFORE_BP
 
- VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_AN_COMPLETE_BEFORE_NP
 
- VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_MODE_WHEN_AN_COMPLETE
 
- VXGE_HW_ANBE_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_NP_BEFORE_BP
 
- VXGE_HW_ANBE_HWFSM_NP_STATUS_PORT_RATEMGMT_NP_BITS_31_TO_0
 
- VXGE_HW_ANBE_HWFSM_NP_STATUS_PORT_RATEMGMT_NP_BITS_47_TO_32
 
- VXGE_HW_ANBE_MGR_CTRL_PORT_ADDR
 
- VXGE_HW_ANBE_MGR_CTRL_PORT_DATA
 
- VXGE_HW_ANBE_MGR_CTRL_PORT_STROBE
 
- VXGE_HW_ANBE_MGR_CTRL_PORT_WE
 
- VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ABILITY_FIELD
 
- VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_ACK
 
- VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_NP
 
- VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_RF
 
- VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_SELECTOR_FIELD
 
- VXGE_HW_ANTP_HWFSM_BP_STATUS_PORT_RATEMGMT_BP_XNP
 
- VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_ANTPFSM_STATE
 
- VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_AUTONEG_COMPLETE
 
- VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_10G
 
- VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_CHOSE_1G
 
- VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_FOUND_HCD
 
- VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_GOT_LP_XNP
 
- VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_PERSISTENT_LDOWN
 
- VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_INVALID_RATE
 
- VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_MESSAGE_CODE
 
- VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_NO_HCD
 
- VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_UNEXPECTED_NO_LP_XNP
 
- VXGE_HW_ANTP_HWFSM_GEN_STATUS_PORT_RATEMGMT_VALID_RATE
 
- VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_ACK
 
- VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_ACK2
 
- VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_MESSAGE_CODE
 
- VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_MP
 
- VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_NP
 
- VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_TOGGLE
 
- VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_UNF_CODE_FIELD1
 
- VXGE_HW_ANTP_HWFSM_XNP_STATUS_PORT_RATEMGMT_XNP_UNF_CODE_FIELD2
 
- VXGE_HW_ASIC_GPIO_ERR_REG_XMACJ_GPIO_INT
 
- VXGE_HW_ASIC_MODE_MR_IOV
 
- VXGE_HW_ASIC_MODE_NO_IOV
 
- VXGE_HW_ASIC_MODE_RESERVED
 
- VXGE_HW_ASIC_MODE_SR_IOV
 
- VXGE_HW_ASIC_NTWK_CFG_PORT_NUM_VP
 
- VXGE_HW_ASIC_NTWK_CFG_SHOW_PORT_INFO_VP
 
- VXGE_HW_ASIC_NTWK_CTRL_PORT0_REQ_TEST_PORT
 
- VXGE_HW_ASIC_NTWK_CTRL_PORT1_REQ_TEST_PORT
 
- VXGE_HW_ASIC_NTWK_CTRL_REQ_TEST_NTWK
 
- VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_DOWN
 
- VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT
 
- VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK
 
- VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_UP
 
- VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_WENT_DOWN
 
- VXGE_HW_ASIC_NTWK_ERR_REG_XMACJ_NTWK_WENT_UP
 
- VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_FAULT
 
- VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_FAULT_OCCURRED
 
- VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_OK
 
- VXGE_HW_ASIC_NTWK_SR_ERR_REG_XMACJ_NTWK_SUSTAINED_OK_OCCURRED
 
- VXGE_HW_ASIC_NTWK_VP_CTRL_REQ_TEST_NTWK
 
- VXGE_HW_ASIC_NTWK_VP_CTRL_XMACJ_PORT_NUM
 
- VXGE_HW_ASIC_NTWK_VP_CTRL_XMACJ_SHOW_PORT_INFO
 
- VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT
 
- VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK
 
- VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT
 
- VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR
 
- VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK
 
- VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR
 
- VXGE_HW_BADCFG_FIFO_BLOCKS
 
- VXGE_HW_BADCFG_INTR_MODE
 
- VXGE_HW_BADCFG_RING_INDICATE_MAX_PKTS
 
- VXGE_HW_BADCFG_RTS_MAC_EN
 
- VXGE_HW_BADCFG_VPATH_MIN_BANDWIDTH
 
- VXGE_HW_BADCFG_VPATH_MTU
 
- VXGE_HW_BADCFG_VPATH_RPA_STRIP_VLAN_TAG
 
- VXGE_HW_BARGRP_PF_OR_VF_BAR0_MASK_BARGRP_PF_OR_VF_BAR0_MASK
 
- VXGE_HW_BARGRP_PF_OR_VF_BAR1_MASK_BARGRP_PF_OR_VF_BAR1_MASK
 
- VXGE_HW_BARGRP_PF_OR_VF_BAR2_MASK_BARGRP_PF_OR_VF_BAR2_MASK
 
- VXGE_HW_BASE_BADCFG
 
- VXGE_HW_BASE_ERR
 
- VXGE_HW_BASE_INF
 
- VXGE_HW_BF_SW_RESET_BF_SW_RESET
 
- VXGE_HW_BLOCK_SIZE
 
- VXGE_HW_CHANNEL_TYPE_FIFO
 
- VXGE_HW_CHANNEL_TYPE_MAX
 
- VXGE_HW_CHANNEL_TYPE_RING
 
- VXGE_HW_CHANNEL_TYPE_UNKNOWN
 
- VXGE_HW_CLEAR_MSIX_MASK_ALL_VECT_CLEAR_MSIX_MASK_ALL_VECT
 
- VXGE_HW_CLEAR_MSIX_MASK_VECT_CLEAR_MSIX_MASK_VECT
 
- VXGE_HW_CLR_MSIX_ONE_SHOT_VEC_CLR_MSIX_ONE_SHOT_VEC
 
- VXGE_HW_CMC_ERR_REG_CMC_CMC_SM_ERR
 
- VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH
 
- VXGE_HW_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET
 
- VXGE_HW_CMN_RSTHDLR_CFG2_SW_RESET_FIFO0
 
- VXGE_HW_CMN_RSTHDLR_CFG3_SW_RESET_FIFO1
 
- VXGE_HW_CMN_RSTHDLR_CFG4_SW_RESET_FIFO2
 
- VXGE_HW_CMN_RSTHDLR_CFG8_INCR_VPATH_INST_NUM
 
- VXGE_HW_COMPLETIONS_REMAIN
 
- VXGE_HW_CONFIG_ERRORS_REG_CFGM_FSM_ERR
 
- VXGE_HW_CONFIG_ERRORS_REG_CFGM_I2C_TIMEOUT
 
- VXGE_HW_CONFIG_ERRORS_REG_I2C_EXP_RD_CNT
 
- VXGE_HW_CONFIG_ERRORS_REG_I2C_EXTRA_CYCLE
 
- VXGE_HW_CONFIG_ERRORS_REG_I2C_ILLEGAL_START_COND
 
- VXGE_HW_CONFIG_ERRORS_REG_I2C_ILLEGAL_STOP_COND
 
- VXGE_HW_CONFIG_ERRORS_REG_I2C_MAIN_FSM_ERR
 
- VXGE_HW_CONFIG_ERRORS_REG_I2C_REG_FSM_ERR
 
- VXGE_HW_CONFIG_ERRORS_REG_I2C_REQ_COLLISION
 
- VXGE_HW_CONFIG_ERRORS_REG_PIFM_FSM_ERR
 
- VXGE_HW_CONFIG_ERRORS_REG_PIFM_ILLEGAL_ACCESS
 
- VXGE_HW_CONFIG_ERRORS_REG_PIFM_TIMEOUT
 
- VXGE_HW_CONFIG_ERRORS_REG_PIFM_TO_FSM_ERR
 
- VXGE_HW_CONFIG_ERRORS_REG_RIC_FSM_ERR
 
- VXGE_HW_CONFIG_ERRORS_REG_RIC_I2C_TIMEOUT
 
- VXGE_HW_CONFIG_ERRORS_REG_RIC_RIC_RD_TIMEOUT
 
- VXGE_HW_CONFIG_PRIV_H
 
- VXGE_HW_CP_ERR_REG_CP_CP2DMA_FIFO_ERR
 
- VXGE_HW_CP_ERR_REG_CP_CP_DCACHE_DB_ERR
 
- VXGE_HW_CP_ERR_REG_CP_CP_DCACHE_SG_ERR
 
- VXGE_HW_CP_ERR_REG_CP_CP_DTAG_DB_ERR
 
- VXGE_HW_CP_ERR_REG_CP_CP_DTAG_SG_ERR
 
- VXGE_HW_CP_ERR_REG_CP_CP_ICACHE_DB_ERR
 
- VXGE_HW_CP_ERR_REG_CP_CP_ICACHE_SG_ERR
 
- VXGE_HW_CP_ERR_REG_CP_CP_ITAG_DB_ERR
 
- VXGE_HW_CP_ERR_REG_CP_CP_ITAG_SG_ERR
 
- VXGE_HW_CP_ERR_REG_CP_CP_PMON_FSM_INTEGRITY_ERR
 
- VXGE_HW_CP_ERR_REG_CP_CP_TRACE_DB_ERR
 
- VXGE_HW_CP_ERR_REG_CP_CP_TRACE_SG_ERR
 
- VXGE_HW_CP_ERR_REG_CP_CP_WAKE_FSM_INTEGRITY_ERR
 
- VXGE_HW_CP_ERR_REG_CP_DAM2CP_FIFO_ERR
 
- VXGE_HW_CP_ERR_REG_CP_DMA2CP_DB_ERR
 
- VXGE_HW_CP_ERR_REG_CP_DMA2CP_FIFO_ERR
 
- VXGE_HW_CP_ERR_REG_CP_DMA2CP_SG_ERR
 
- VXGE_HW_CP_ERR_REG_CP_DMA_RD_SHADOW_ERR
 
- VXGE_HW_CP_ERR_REG_CP_H2L2CP_FIFO_ERR
 
- VXGE_HW_CP_ERR_REG_CP_MP2CP_DB_ERR
 
- VXGE_HW_CP_ERR_REG_CP_MP2CP_FIFO_ERR
 
- VXGE_HW_CP_ERR_REG_CP_MP2CP_SG_ERR
 
- VXGE_HW_CP_ERR_REG_CP_PIFT_CREDIT_ERR
 
- VXGE_HW_CP_ERR_REG_CP_QCC2CP_DB_ERR
 
- VXGE_HW_CP_ERR_REG_CP_QCC2CP_FIFO_ERR
 
- VXGE_HW_CP_ERR_REG_CP_QCC2CP_SG_ERR
 
- VXGE_HW_CP_ERR_REG_CP_STC2CP_DB_ERR
 
- VXGE_HW_CP_ERR_REG_CP_STC2CP_FIFO_ERR
 
- VXGE_HW_CP_ERR_REG_CP_STC2CP_SG_ERR
 
- VXGE_HW_CP_ERR_REG_CP_STE2CP_FIFO_ERR
 
- VXGE_HW_CP_ERR_REG_CP_SWIF2CP_FIFO_ERR
 
- VXGE_HW_CP_ERR_REG_CP_TTE2CP_FIFO_ERR
 
- VXGE_HW_CP_EXC_CAUSE_CP_CP_CAUSE
 
- VXGE_HW_CP_EXC_REG_CP_CP_CAUSE_CRIT_INT
 
- VXGE_HW_CP_EXC_REG_CP_CP_CAUSE_INFO_INT
 
- VXGE_HW_CP_EXC_REG_CP_CP_SERR
 
- VXGE_HW_CP_RESET_IN_PROGRESS_CP_VPATH
 
- VXGE_HW_CRDT_ERRORS_REG_RDCRDTARB_DBLGEN_ILLEGAL_CRD_DEAL
 
- VXGE_HW_CRDT_ERRORS_REG_RDCRDTARB_FSM_ERR
 
- VXGE_HW_CRDT_ERRORS_REG_RDCRDTARB_PDA_ILLEGAL_CRD_DEAL
 
- VXGE_HW_CRDT_ERRORS_REG_RDCRDTARB_RDA_ILLEGAL_CRD_DEAL
 
- VXGE_HW_CRDT_ERRORS_REG_WRCRDTARB_FSM_ERR
 
- VXGE_HW_CRDT_ERRORS_REG_WRCRDTARB_INTCTL_ILLEGAL_CRD_DEAL
 
- VXGE_HW_CRDT_ERRORS_REG_WRCRDTARB_PCI_MSG_ILLEGAL_CRD_DEAL
 
- VXGE_HW_CRDT_ERRORS_REG_WRCRDTARB_PDA_ILLEGAL_CRD_DEAL
 
- VXGE_HW_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_NP_H_CONSUME_CRDT_ERR
 
- VXGE_HW_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_NP_H_RETURN_CRDT_ERR
 
- VXGE_HW_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_TAG_CONSUME_TAG_ERR
 
- VXGE_HW_CRDT_ERRORS_VPLANE_REG_RDCRDTARB_TAG_RETURN_TAG_ERR
 
- VXGE_HW_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_D_CONSUME_CRDT_ERR
 
- VXGE_HW_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_D_RETURN_CRDT_ERR
 
- VXGE_HW_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_H_CONSUME_CRDT_ERR
 
- VXGE_HW_CRDT_ERRORS_VPLANE_REG_WRCRDTARB_P_H_RETURN_CRDT_ERR
 
- VXGE_HW_DBECC_ERR_REG_PCI_NP_DATA_DB_ERR
 
- VXGE_HW_DBECC_ERR_REG_PCI_NP_HDR_DB_ERR
 
- VXGE_HW_DBECC_ERR_REG_PCI_P_DATA_DB_ERR
 
- VXGE_HW_DBECC_ERR_REG_PCI_P_HDR_DB_ERR
 
- VXGE_HW_DBECC_ERR_REG_PCI_RETRY_BUF_DB_ERR
 
- VXGE_HW_DBECC_ERR_REG_PCI_RETRY_SOT_DB_ERR
 
- VXGE_HW_DBG_STATS_FAU_RX_PATH_RX_PERMITTED_FRMS
 
- VXGE_HW_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS
 
- VXGE_HW_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS
 
- VXGE_HW_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS
 
- VXGE_HW_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS
 
- VXGE_HW_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS
 
- VXGE_HW_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS
 
- VXGE_HW_DBG_STATS_RX_FAU_RX_PERMITTED_FRMS
 
- VXGE_HW_DBG_STATS_RX_FAU_RX_VP_RESET_DISCARDED_FRMS
 
- VXGE_HW_DBG_STATS_RX_FAU_RX_WOL_FRMS
 
- VXGE_HW_DBG_STATS_RX_MPA_CRC_FAIL_FRMS
 
- VXGE_HW_DBG_STATS_RX_MPA_LEN_FAIL_FRMS
 
- VXGE_HW_DBG_STATS_RX_MPA_MRK_FAIL_FRMS
 
- VXGE_HW_DBG_STATS_TPA_TX_PATH_GET_TX_PERMITTED_FRMS
 
- VXGE_HW_DBG_STATS_TPA_TX_PATH_TX_PERMITTED_FRMS
 
- VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT0_RX_ANY_FRMS
 
- VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT1_RX_ANY_FRMS
 
- VXGE_HW_DBG_STAT_RX_ANY_FRMS_GET_PORT2_RX_ANY_FRMS
 
- VXGE_HW_DBG_STAT_RX_ANY_FRMS_PORT0_RX_ANY_FRMS
 
- VXGE_HW_DBG_STAT_RX_ANY_FRMS_PORT1_RX_ANY_FRMS
 
- VXGE_HW_DBG_STAT_RX_ANY_FRMS_PORT2_RX_ANY_FRMS
 
- VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT0_TX_ANY_FRMS
 
- VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT1_TX_ANY_FRMS
 
- VXGE_HW_DBG_STAT_TX_ANY_FRMS_GET_PORT2_TX_ANY_FRMS
 
- VXGE_HW_DBG_STAT_TX_ANY_FRMS_PORT0_TX_ANY_FRMS
 
- VXGE_HW_DBG_STAT_TX_ANY_FRMS_PORT1_TX_ANY_FRMS
 
- VXGE_HW_DBG_STAT_TX_ANY_FRMS_PORT2_TX_ANY_FRMS
 
- VXGE_HW_DEBUG_STATS0_GET_RSTDROP_CPL
 
- VXGE_HW_DEBUG_STATS0_GET_RSTDROP_MSG
 
- VXGE_HW_DEBUG_STATS0_RSTDROP_CPL
 
- VXGE_HW_DEBUG_STATS0_RSTDROP_MSG
 
- VXGE_HW_DEBUG_STATS1_GET_RSTDROP_CLIENT0
 
- VXGE_HW_DEBUG_STATS1_GET_RSTDROP_CLIENT1
 
- VXGE_HW_DEBUG_STATS1_RSTDROP_CLIENT0
 
- VXGE_HW_DEBUG_STATS1_RSTDROP_CLIENT1
 
- VXGE_HW_DEBUG_STATS2_GET_RSTDROP_CLIENT2
 
- VXGE_HW_DEBUG_STATS2_RSTDROP_CLIENT2
 
- VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_CPLH
 
- VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_NPH
 
- VXGE_HW_DEBUG_STATS3_GET_VPLANE_DEPL_PH
 
- VXGE_HW_DEBUG_STATS3_VPLANE_DEPL_CPLH
 
- VXGE_HW_DEBUG_STATS3_VPLANE_DEPL_NPH
 
- VXGE_HW_DEBUG_STATS3_VPLANE_DEPL_PH
 
- VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_CPLD
 
- VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_NPD
 
- VXGE_HW_DEBUG_STATS4_GET_VPLANE_DEPL_PD
 
- VXGE_HW_DEBUG_STATS4_VPLANE_DEPL_CPLD
 
- VXGE_HW_DEBUG_STATS4_VPLANE_DEPL_NPD
 
- VXGE_HW_DEBUG_STATS4_VPLANE_DEPL_PD
 
- VXGE_HW_DEFAULT_32
 
- VXGE_HW_DEFAULT_MTU
 
- VXGE_HW_DEF_DEVICE_POLL_MILLIS
 
- VXGE_HW_DEF_FIFO_ALIGNMENT_SIZE
 
- VXGE_HW_DEF_FIFO_MEMBLOCK_SIZE
 
- VXGE_HW_DEF_RING_BLOCKS
 
- VXGE_HW_DEF_RING_RXDS_LIMIT
 
- VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM
 
- VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM
 
- VXGE_HW_DEVICE_ACCESS_RIGHT_VPATH
 
- VXGE_HW_DEVICE_DEAD
 
- VXGE_HW_DEVICE_LINK_STATE_SET
 
- VXGE_HW_DEVICE_MAGIC
 
- VXGE_HW_DEVICE_STATS_PIO_READ
 
- VXGE_HW_DEVICE_TIM_INT_MASK_RESET
 
- VXGE_HW_DEVICE_TIM_INT_MASK_SET
 
- VXGE_HW_DMAIF_DMADBL_PENDING_DBLGEN_IN_PROG
 
- VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_MSG_WR
 
- VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_RTDMA_RD
 
- VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_RTDMA_WR
 
- VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_STATS_WR
 
- VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_WRDMA_RD
 
- VXGE_HW_DMAIF_DMADBL_PENDING_DMAIF_WRDMA_WR
 
- VXGE_HW_DMA_ERRORS_REG_DBLGEN_CREDIT_FSM_ERR
 
- VXGE_HW_DMA_ERRORS_REG_DBLGEN_DMA_WRR_SM_ERR
 
- VXGE_HW_DMA_ERRORS_REG_DBLGEN_FSM_ERR
 
- VXGE_HW_DMA_ERRORS_REG_DMA_MSG_WR_DATA_OVERFLOW
 
- VXGE_HW_DMA_ERRORS_REG_DMA_MSG_WR_DATA_UNDERFLOW
 
- VXGE_HW_DMA_ERRORS_REG_DMA_MSG_WR_HDR_OVERFLOW
 
- VXGE_HW_DMA_ERRORS_REG_DMA_MSG_WR_HDR_UNDERFLOW
 
- VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_RD_HDR_OVERFLOW
 
- VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_RD_HDR_UNDERFLOW
 
- VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_WR_DATA_OVERFLOW
 
- VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_WR_DATA_UNDERFLOW
 
- VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_WR_HDR_OVERFLOW
 
- VXGE_HW_DMA_ERRORS_REG_DMA_RTDMA_WR_HDR_UNDERFLOW
 
- VXGE_HW_DMA_ERRORS_REG_DMA_STATS_WR_DATA_OVERFLOW
 
- VXGE_HW_DMA_ERRORS_REG_DMA_STATS_WR_DATA_UNDERFLOW
 
- VXGE_HW_DMA_ERRORS_REG_DMA_STATS_WR_HDR_OVERFLOW
 
- VXGE_HW_DMA_ERRORS_REG_DMA_STATS_WR_HDR_UNDERFLOW
 
- VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_RD_HDR_OVERFLOW
 
- VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_RD_HDR_UNDERFLOW
 
- VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_WR_DATA_OVERFLOW
 
- VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_WR_DATA_UNDERFLOW
 
- VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_WR_HDR_OVERFLOW
 
- VXGE_HW_DMA_ERRORS_REG_DMA_WRDMA_WR_HDR_UNDERFLOW
 
- VXGE_HW_DMA_ERRORS_REG_RDARB_FSM_ERR
 
- VXGE_HW_DMA_ERRORS_REG_WRARB_FSM_ERR
 
- VXGE_HW_DMQ_BWR_INIT_ADD_HOST
 
- VXGE_HW_DMQ_BWR_INIT_BYTE_COUNT
 
- VXGE_HW_DMQ_INIT_NOTIFY_PULSE
 
- VXGE_HW_DMQ_IR_INT_BITMAP
 
- VXGE_HW_DMQ_IR_INT_EVENT_ENABLE
 
- VXGE_HW_DMQ_IR_INT_IMMED_ENABLE
 
- VXGE_HW_DMQ_IR_INT_NUMBER
 
- VXGE_HW_DMQ_IR_POLICY
 
- VXGE_HW_DOORBELL_INT_STATUS_KDFC_ERR_REG_TXDMA_KDFC_INT
 
- VXGE_HW_DOORBELL_INT_STATUS_USDC_ERR_REG_TXDMA_USDC_INT
 
- VXGE_HW_DTR_MAX_T_CODE
 
- VXGE_HW_EEPROM_SIZE
 
- VXGE_HW_EOF_TRACE_BUF
 
- VXGE_HW_ERR_CRITICAL
 
- VXGE_HW_ERR_FIFO
 
- VXGE_HW_ERR_INVALID_BLOCK_SIZE
 
- VXGE_HW_ERR_INVALID_DEVICE
 
- VXGE_HW_ERR_INVALID_HANDLE
 
- VXGE_HW_ERR_INVALID_INDEX
 
- VXGE_HW_ERR_INVALID_MTU_SIZE
 
- VXGE_HW_ERR_INVALID_OFFSET
 
- VXGE_HW_ERR_INVALID_PCI_INFO
 
- VXGE_HW_ERR_INVALID_PORT
 
- VXGE_HW_ERR_INVALID_STATE
 
- VXGE_HW_ERR_INVALID_TCODE
 
- VXGE_HW_ERR_INVALID_TYPE
 
- VXGE_HW_ERR_OUT_OF_MEMORY
 
- VXGE_HW_ERR_PRIVILEGED_OPERATION
 
- VXGE_HW_ERR_SLOT_FREEZE
 
- VXGE_HW_ERR_SWAPPER_CTRL
 
- VXGE_HW_ERR_VERSION_CONFLICT
 
- VXGE_HW_ERR_VPATH
 
- VXGE_HW_ERR_VPATH_NOT_AVAILABLE
 
- VXGE_HW_ERR_VPATH_NOT_OPEN
 
- VXGE_HW_ERR_WRONG_IRQ
 
- VXGE_HW_EVENT_ALARM_CLEARED
 
- VXGE_HW_EVENT_BASE
 
- VXGE_HW_EVENT_CRITICAL_ERR
 
- VXGE_HW_EVENT_ECCERR
 
- VXGE_HW_EVENT_FIFO_ERR
 
- VXGE_HW_EVENT_LINK_DOWN
 
- VXGE_HW_EVENT_LINK_UP
 
- VXGE_HW_EVENT_MRPCIM_ECCERR
 
- VXGE_HW_EVENT_MRPCIM_SERR
 
- VXGE_HW_EVENT_RESET_COMPLETE
 
- VXGE_HW_EVENT_RESET_START
 
- VXGE_HW_EVENT_SERR
 
- VXGE_HW_EVENT_SLOT_FREEZE
 
- VXGE_HW_EVENT_SRPCIM_SERR
 
- VXGE_HW_EVENT_UNKNOWN
 
- VXGE_HW_EVENT_VPATH_ERR
 
- VXGE_HW_FAIL
 
- VXGE_HW_FAU_ECC_ERR_REG_FAUJ_FAU_FSM_ERR
 
- VXGE_HW_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_DB_ERR
 
- VXGE_HW_FAU_ECC_ERR_REG_FAU_FAU_XFMD_INS_SG_ERR
 
- VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_N_DB_ERR
 
- VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_N_SG_ERR
 
- VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_DB_ERR
 
- VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT0_FAU_MAC2F_W_SG_ERR
 
- VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_N_DB_ERR
 
- VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_N_SG_ERR
 
- VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_DB_ERR
 
- VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT1_FAU_MAC2F_W_SG_ERR
 
- VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_N_DB_ERR
 
- VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_N_SG_ERR
 
- VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_DB_ERR
 
- VXGE_HW_FAU_ECC_ERR_REG_FAU_PORT2_FAU_MAC2F_W_SG_ERR
 
- VXGE_HW_FAU_GEN_ERR_REG_FALR_AUTO_LRO_NOTIFICATION
 
- VXGE_HW_FAU_GEN_ERR_REG_FMPF_PORT0_PERMANENT_STOP
 
- VXGE_HW_FAU_GEN_ERR_REG_FMPF_PORT1_PERMANENT_STOP
 
- VXGE_HW_FAU_GEN_ERR_REG_FMPF_PORT2_PERMANENT_STOP
 
- VXGE_HW_FAU_LAG_CFG_COLL_ALG
 
- VXGE_HW_FAU_LAG_CFG_INCR_RX_AGGR_STATS
 
- VXGE_HW_FAU_PA_CFG_REPL_L3_COMP_CSUM
 
- VXGE_HW_FAU_PA_CFG_REPL_L3_INCL_CF
 
- VXGE_HW_FAU_PA_CFG_REPL_L4_COMP_CSUM
 
- VXGE_HW_FAU_PA_CFG_VPMGMT_CLONE_REPL_L3_COMP_CSUM
 
- VXGE_HW_FAU_PA_CFG_VPMGMT_CLONE_REPL_L3_INCL_CF
 
- VXGE_HW_FAU_PA_CFG_VPMGMT_CLONE_REPL_L4_COMP_CSUM
 
- VXGE_HW_FAU_RPA_VCFG_L3_COMP_CSUM
 
- VXGE_HW_FAU_RPA_VCFG_L3_INCL_CF
 
- VXGE_HW_FAU_RPA_VCFG_L4_COMP_CSUM
 
- VXGE_HW_FBIF_READY_FAU_READY
 
- VXGE_HW_FBMC_ECC_CFG_ENABLE
 
- VXGE_HW_FBMC_VP_RDY_QUEUE_SPAV_FM
 
- VXGE_HW_FIFO0_STATUS_DBLGEN_FIFO0_RDIDX
 
- VXGE_HW_FIFO1_STATUS_DBLGEN_FIFO1_RDIDX
 
- VXGE_HW_FIFO2_STATUS_DBLGEN_FIFO2_RDIDX
 
- VXGE_HW_FIFO_DISABLE
 
- VXGE_HW_FIFO_ENABLE
 
- VXGE_HW_FIFO_GATHER_CODE_FIRST
 
- VXGE_HW_FIFO_GATHER_CODE_FIRST_LAST
 
- VXGE_HW_FIFO_GATHER_CODE_LAST
 
- VXGE_HW_FIFO_GATHER_CODE_MIDDLE
 
- VXGE_HW_FIFO_NO_SNOOP_ALL
 
- VXGE_HW_FIFO_NO_SNOOP_DEFAULT
 
- VXGE_HW_FIFO_NO_SNOOP_DISABLED
 
- VXGE_HW_FIFO_NO_SNOOP_FRM
 
- VXGE_HW_FIFO_NO_SNOOP_TXD
 
- VXGE_HW_FIFO_QUEUE_INTR_DEFAULT
 
- VXGE_HW_FIFO_QUEUE_INTR_DISABLE
 
- VXGE_HW_FIFO_QUEUE_INTR_ENABLE
 
- VXGE_HW_FIFO_TXD_BUFFER_SIZE
 
- VXGE_HW_FIFO_TXD_GATHER_CODE
 
- VXGE_HW_FIFO_TXD_GATHER_CODE_FIRST
 
- VXGE_HW_FIFO_TXD_GATHER_CODE_LAST
 
- VXGE_HW_FIFO_TXD_INT_NUMBER
 
- VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST
 
- VXGE_HW_FIFO_TXD_INT_TYPE_UTILZ
 
- VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER
 
- VXGE_HW_FIFO_TXD_LSO_EN
 
- VXGE_HW_FIFO_TXD_LSO_MSS
 
- VXGE_HW_FIFO_TXD_TX_CKO_IPV4_EN
 
- VXGE_HW_FIFO_TXD_TX_CKO_TCP_EN
 
- VXGE_HW_FIFO_TXD_TX_CKO_UDP_EN
 
- VXGE_HW_FIFO_TXD_T_CODE
 
- VXGE_HW_FIFO_TXD_T_CODE_GET
 
- VXGE_HW_FIFO_TXD_T_CODE_UNUSED
 
- VXGE_HW_FIFO_TXD_VLAN_ENABLE
 
- VXGE_HW_FIFO_TXD_VLAN_TAG
 
- VXGE_HW_FIFO_T_CODE_INVALID_MSS
 
- VXGE_HW_FIFO_T_CODE_LSO_ERROR
 
- VXGE_HW_FIFO_T_CODE_MULTI_ERROR
 
- VXGE_HW_FIFO_T_CODE_OK
 
- VXGE_HW_FIFO_T_CODE_PCI_READ_CORRUPT
 
- VXGE_HW_FIFO_T_CODE_PCI_READ_FAIL
 
- VXGE_HW_FIFO_T_CODE_UNUSED
 
- VXGE_HW_FRAME_PROTO_IPV4
 
- VXGE_HW_FRAME_PROTO_IPV6
 
- VXGE_HW_FRAME_PROTO_IP_FRAG
 
- VXGE_HW_FRAME_PROTO_TCP
 
- VXGE_HW_FRAME_PROTO_TCP_OR_UDP
 
- VXGE_HW_FRAME_PROTO_UDP
 
- VXGE_HW_FRAME_PROTO_VLAN_TAGGED
 
- VXGE_HW_FRF_ALARM_REG_PRC_VP_FRF_SM_ERR
 
- VXGE_HW_FRM_IN_PROGRESS_CNT_PRC_FRM_IN_PROGRESS_CNT
 
- VXGE_HW_FUNCTION_MODE_MRIOV
 
- VXGE_HW_FUNCTION_MODE_MRIOV_4
 
- VXGE_HW_FUNCTION_MODE_MRIOV_8
 
- VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION
 
- VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION_17
 
- VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION_2
 
- VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION_4
 
- VXGE_HW_FUNCTION_MODE_SINGLE_FUNCTION
 
- VXGE_HW_FUNCTION_MODE_SRIOV
 
- VXGE_HW_FUNCTION_MODE_SRIOV_4
 
- VXGE_HW_FUNCTION_MODE_SRIOV_8
 
- VXGE_HW_FW_API_GET_EPROM_REV
 
- VXGE_HW_FW_API_GET_FUNC_MODE
 
- VXGE_HW_FW_STRLEN
 
- VXGE_HW_FW_UPGRADE_ACTION
 
- VXGE_HW_FW_UPGRADE_BLK_SIZE
 
- VXGE_HW_FW_UPGRADE_DONE
 
- VXGE_HW_FW_UPGRADE_ERR
 
- VXGE_HW_FW_UPGRADE_ERR_BUFFER_OVERFLOW
 
- VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_1
 
- VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_7
 
- VXGE_HW_FW_UPGRADE_ERR_FAILED_TO_FLASH
 
- VXGE_HW_FW_UPGRADE_ERR_GENERIC_ERROR_UNKNOWN
 
- VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_3
 
- VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_4
 
- VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_5
 
- VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_6
 
- VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_8
 
- VXGE_HW_FW_UPGRADE_MEMO
 
- VXGE_HW_FW_UPGRADE_OFFSET_COMMIT
 
- VXGE_HW_FW_UPGRADE_OFFSET_READ
 
- VXGE_HW_FW_UPGRADE_OFFSET_SEND
 
- VXGE_HW_FW_UPGRADE_OFFSET_START
 
- VXGE_HW_FW_UPGRADE_OK
 
- VXGE_HW_G3CMCT_ERR_REG_G3IF_CTRL_FIFO_DECC
 
- VXGE_HW_G3CMCT_ERR_REG_G3IF_CTRL_FIFO_SECC
 
- VXGE_HW_G3CMCT_ERR_REG_G3IF_GDDR3_DECC
 
- VXGE_HW_G3CMCT_ERR_REG_G3IF_GDDR3_SECC
 
- VXGE_HW_G3CMCT_ERR_REG_G3IF_GDDR3_U_DECC
 
- VXGE_HW_G3CMCT_ERR_REG_G3IF_GDDR3_U_SECC
 
- VXGE_HW_G3CMCT_ERR_REG_G3IF_SM_ERR
 
- VXGE_HW_G3CMCT_INT_STATUS_ERR_G3IF_INT
 
- VXGE_HW_G3FBCT_ERR_REG_G3IF_CTRL_FIFO_DECC
 
- VXGE_HW_G3FBCT_ERR_REG_G3IF_CTRL_FIFO_SECC
 
- VXGE_HW_G3FBCT_ERR_REG_G3IF_GDDR3_DECC
 
- VXGE_HW_G3FBCT_ERR_REG_G3IF_GDDR3_SECC
 
- VXGE_HW_G3FBCT_ERR_REG_G3IF_GDDR3_U_DECC
 
- VXGE_HW_G3FBCT_ERR_REG_G3IF_GDDR3_U_SECC
 
- VXGE_HW_G3FBCT_ERR_REG_G3IF_SM_ERR
 
- VXGE_HW_G3FBCT_INT_STATUS_ERR_G3IF_INT
 
- VXGE_HW_G3IFCMD_CML_ERR_REG_G3IF_CK_DLL_LOCK
 
- VXGE_HW_G3IFCMD_CML_ERR_REG_G3IF_IOCAL_FAULT
 
- VXGE_HW_G3IFCMD_CML_ERR_REG_G3IF_RWDQS_DLL_LOCK
 
- VXGE_HW_G3IFCMD_CML_ERR_REG_G3IF_SM_ERR
 
- VXGE_HW_G3IFCMD_CML_INT_STATUS_ERR_G3IF_INT
 
- VXGE_HW_G3IFCMD_CMU_ERR_REG_G3IF_CK_DLL_LOCK
 
- VXGE_HW_G3IFCMD_CMU_ERR_REG_G3IF_IOCAL_FAULT
 
- VXGE_HW_G3IFCMD_CMU_ERR_REG_G3IF_RWDQS_DLL_LOCK
 
- VXGE_HW_G3IFCMD_CMU_ERR_REG_G3IF_SM_ERR
 
- VXGE_HW_G3IFCMD_CMU_INT_STATUS_ERR_G3IF_INT
 
- VXGE_HW_G3IFCMD_FB_ERR_REG_G3IF_CK_DLL_LOCK
 
- VXGE_HW_G3IFCMD_FB_ERR_REG_G3IF_IOCAL_FAULT
 
- VXGE_HW_G3IFCMD_FB_ERR_REG_G3IF_RWDQS_DLL_LOCK
 
- VXGE_HW_G3IFCMD_FB_ERR_REG_G3IF_SM_ERR
 
- VXGE_HW_G3IFCMD_FB_INT_STATUS_ERR_G3IF_INT
 
- VXGE_HW_GCMG1_INT_STATUS_GQCC_ERR_GQCC_INT
 
- VXGE_HW_GCMG1_INT_STATUS_GSSC0_ERR0_GSSC0_0_INT
 
- VXGE_HW_GCMG1_INT_STATUS_GSSC0_ERR1_GSSC0_1_INT
 
- VXGE_HW_GCMG1_INT_STATUS_GSSC1_ERR0_GSSC1_0_INT
 
- VXGE_HW_GCMG1_INT_STATUS_GSSC1_ERR1_GSSC1_1_INT
 
- VXGE_HW_GCMG1_INT_STATUS_GSSC2_ERR0_GSSC2_0_INT
 
- VXGE_HW_GCMG1_INT_STATUS_GSSC2_ERR1_GSSC2_1_INT
 
- VXGE_HW_GCMG1_INT_STATUS_GSSCC_ERR_GSSCC_INT
 
- VXGE_HW_GCMG1_INT_STATUS_UQM_ERR_UQM_INT
 
- VXGE_HW_GCMG2_INT_STATUS_CMC_ERR_CMC_INT
 
- VXGE_HW_GCMG2_INT_STATUS_GCP_ERR_GCP_INT
 
- VXGE_HW_GCMG2_INT_STATUS_GXTMC_ERR_GXTMC_INT
 
- VXGE_HW_GCMG3_INT_STATUS_GH2L_ERR0_GH2L0_INT
 
- VXGE_HW_GCMG3_INT_STATUS_GH2L_SMERR0_GH2L3_INT
 
- VXGE_HW_GCMG3_INT_STATUS_GHSQ_ERR2_GH2L2_INT
 
- VXGE_HW_GCMG3_INT_STATUS_GHSQ_ERR3_GH2L4_INT
 
- VXGE_HW_GCMG3_INT_STATUS_GHSQ_ERR_GH2L1_INT
 
- VXGE_HW_GCMG3_INT_STATUS_GSTC_ERR0_GSTC0_INT
 
- VXGE_HW_GCMG3_INT_STATUS_GSTC_ERR1_GSTC1_INT
 
- VXGE_HW_GCP_ERR_REG_CP_H2L2CP_FIFO_ERR
 
- VXGE_HW_GCP_ERR_REG_CP_STC2CP_FIFO_ERR
 
- VXGE_HW_GCP_ERR_REG_CP_STE2CP_FIFO_ERR
 
- VXGE_HW_GCP_ERR_REG_CP_TTE2CP_FIFO_ERR
 
- VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO0_OVRFLOW
 
- VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO1_OVRFLOW
 
- VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO2_OVRFLOW
 
- VXGE_HW_GENERAL_ERRORS_REG_INI_SERR_DET
 
- VXGE_HW_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT_REQ
 
- VXGE_HW_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR
 
- VXGE_HW_GENERAL_ERRORS_REG_TGT_ILLEGAL_ACCESS
 
- VXGE_HW_GENERAL_ERR_REG_PCI_DROPPED_ILLEGAL_CFG
 
- VXGE_HW_GENERAL_ERR_REG_PCI_ILLEGAL_MEM_MAP_PROG
 
- VXGE_HW_GENERAL_ERR_REG_PCI_LINK_RST_FSM_ERR
 
- VXGE_HW_GENERAL_ERR_REG_PCI_PCI_LINK_DOWN_DET
 
- VXGE_HW_GENERAL_ERR_REG_PCI_RESET_ACK_DLLP
 
- VXGE_HW_GENERAL_ERR_REG_PCI_RX_ILLEGAL_TLP_VPLANE
 
- VXGE_HW_GENERAL_ERR_REG_PCI_TRAINING_RESET_DET
 
- VXGE_HW_GENSTATS_CFG_CLIENT_NO_SEL
 
- VXGE_HW_GENSTATS_CFG_DTYPE_SEL
 
- VXGE_HW_GENSTATS_CFG_VPATH_SEL
 
- VXGE_HW_GENSTATS_CFG_WR_RD_CPL_SEL
 
- VXGE_HW_GENSTATS_COUNT01_GENSTATS_COUNT0
 
- VXGE_HW_GENSTATS_COUNT01_GENSTATS_COUNT1
 
- VXGE_HW_GENSTATS_COUNT01_GET_GENSTATS_COUNT0
 
- VXGE_HW_GENSTATS_COUNT01_GET_GENSTATS_COUNT1
 
- VXGE_HW_GENSTATS_COUNT23_GENSTATS_COUNT2
 
- VXGE_HW_GENSTATS_COUNT23_GENSTATS_COUNT3
 
- VXGE_HW_GENSTATS_COUNT23_GET_GENSTATS_COUNT2
 
- VXGE_HW_GENSTATS_COUNT23_GET_GENSTATS_COUNT3
 
- VXGE_HW_GENSTATS_COUNT4_GENSTATS_COUNT4
 
- VXGE_HW_GENSTATS_COUNT4_GET_GENSTATS_COUNT4
 
- VXGE_HW_GENSTATS_COUNT5_GENSTATS_COUNT5
 
- VXGE_HW_GENSTATS_COUNT5_GET_GENSTATS_COUNT5
 
- VXGE_HW_GENSTAT_64BIT_CFG_EN_FOR_GENSTATS0
 
- VXGE_HW_GENSTAT_64BIT_CFG_EN_FOR_GENSTATS2
 
- VXGE_HW_GEN_CTRL_SPI_APP_LTSSM_TIMER_DIS
 
- VXGE_HW_GEN_CTRL_SPI_DEBUG_DIS
 
- VXGE_HW_GEN_CTRL_SPI_MRPCIM_RD_DIS
 
- VXGE_HW_GEN_CTRL_SPI_MRPCIM_WR_DIS
 
- VXGE_HW_GEN_CTRL_SPI_NOT_USED
 
- VXGE_HW_GEN_CTRL_SPI_SRPCIM_RD_DIS
 
- VXGE_HW_GEN_CTRL_SPI_SRPCIM_WR_DIS
 
- VXGE_HW_GET_EPROM_IMAGE_INDEX
 
- VXGE_HW_GET_EPROM_IMAGE_REV
 
- VXGE_HW_GET_EPROM_IMAGE_TYPE
 
- VXGE_HW_GET_EPROM_IMAGE_VALID
 
- VXGE_HW_GET_FUNC_MODE_VAL
 
- VXGE_HW_GROCRC_ALARM_REG_WDE2MSR_RD_FIFO_ERR
 
- VXGE_HW_GROCRC_ALARM_REG_XFMD_WR_FIFO_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_ARB_SM_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_CFC_SM_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_CREDIT_OVERFLOW
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_CREDIT_UNDERFLOW
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_DFETCH_SM_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_CREDIT_OVERFLOW
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_CREDIT_UNDERFLOW
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_RCTRL_SM_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_WCOMPL_SM_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_WCOMPL_TAG_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_WREQ_FIFO_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_CMI_WREQ_SM_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_MEM_DB_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_BDT_MEM_SG_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_CMC_RD_DATA_DB_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_ARB_SM_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_CMC0_IF_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_DATA_SM_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_RRP_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_RRP_FIFO_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_WRP_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_CMI_WRP_FIFO_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_CP2BDT_RFIFO_POP_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_RD_RSP_FIFO_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_REQ_DATA_FIFO_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_REQ_FIFO_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_WR_RSP_FIFO_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_XTMC_BDT_CMI_OP_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_XTMC_BDT_DFETCH_OP_ERR
 
- VXGE_HW_GXTMC_ERR_REG_XTMC_XTMC_BDT_DFIFO_ERR
 
- VXGE_HW_HEADER_802_2_ALIGN
 
- VXGE_HW_HEADER_802_2_SIZE
 
- VXGE_HW_HEADER_802_2_SNAP_ALIGN
 
- VXGE_HW_HEADER_ETHERNET_II_802_3_ALIGN
 
- VXGE_HW_HEADER_SNAP_ALIGN
 
- VXGE_HW_HEADER_SNAP_SIZE
 
- VXGE_HW_HEADER_VLAN_SIZE
 
- VXGE_HW_HOST_ACCESS_EN_HOST_ACCESS_EN
 
- VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS
 
- VXGE_HW_HOST_TYPE_ASSIGNMENTS_HOST_TYPE_ASSIGNMENTS
 
- VXGE_HW_HWTS_DEFAULT
 
- VXGE_HW_HWTS_DISABLE
 
- VXGE_HW_HWTS_ENABLE
 
- VXGE_HW_INCR_DMA_BLOCK_POOL_SIZE
 
- VXGE_HW_INFO_LEN
 
- VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS
 
- VXGE_HW_INF_OUT_OF_DESCRIPTORS
 
- VXGE_HW_INITIAL_DMA_BLOCK_POOL_SIZE
 
- VXGE_HW_INI_ERRORS_REG_DCPL_ABORT
 
- VXGE_HW_INI_ERRORS_REG_DCPL_FSM_ERR
 
- VXGE_HW_INI_ERRORS_REG_DCPL_POISON
 
- VXGE_HW_INI_ERRORS_REG_DCPL_UNSUPPORTED
 
- VXGE_HW_INI_ERRORS_REG_INI_BUF_DB_ERR
 
- VXGE_HW_INI_ERRORS_REG_INI_BUF_SG_ERR
 
- VXGE_HW_INI_ERRORS_REG_INI_DATA_OVERFLOW
 
- VXGE_HW_INI_ERRORS_REG_INI_DLLP_ABORT
 
- VXGE_HW_INI_ERRORS_REG_INI_ECRC_ERR
 
- VXGE_HW_INI_ERRORS_REG_INI_HDR_OVERFLOW
 
- VXGE_HW_INI_ERRORS_REG_INI_MRD_CLIENT_DROP
 
- VXGE_HW_INI_ERRORS_REG_INI_MRD_SYS_DROP
 
- VXGE_HW_INI_ERRORS_REG_INI_MWR_CLIENT_DROP
 
- VXGE_HW_INI_ERRORS_REG_INI_MWR_SYS_DROP
 
- VXGE_HW_INI_ERRORS_REG_INI_TLP_ABORT
 
- VXGE_HW_INI_ERRORS_REG_SCPL_CPL_TIMEOUT
 
- VXGE_HW_INI_ERRORS_REG_SCPL_CPL_TIMEOUT_UNUSED_TAG
 
- VXGE_HW_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI
 
- VXGE_HW_INTERRUPT_CFG0_GROUP1_MSIX_FOR_TXTI
 
- VXGE_HW_INTERRUPT_CFG0_GROUP2_MSIX_FOR_TXTI
 
- VXGE_HW_INTERRUPT_CFG0_GROUP3_MSIX_FOR_TXTI
 
- VXGE_HW_INTERRUPT_CFG0_MSIX_FOR_RXTI
 
- VXGE_HW_INTERRUPT_CFG2_ALARM_MAP_TO_MSG
 
- VXGE_HW_INTR_MASK_ALL
 
- VXGE_HW_INTR_MODE_DEF
 
- VXGE_HW_INTR_MODE_IRQLINE
 
- VXGE_HW_INTR_MODE_MSIX
 
- VXGE_HW_INTR_MODE_MSIX_ONE_SHOT
 
- VXGE_HW_KDFCCTL_CFG0_BIT_FLIPEN_FIFO0
 
- VXGE_HW_KDFCCTL_CFG0_BIT_FLIPEN_FIFO1
 
- VXGE_HW_KDFCCTL_CFG0_BIT_FLIPEN_FIFO2
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE0_FIFO0
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE0_FIFO1
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE0_FIFO2
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE1_FIFO0
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE1_FIFO1
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE1_FIFO2
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE2_FIFO0
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE2_FIFO1
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE2_FIFO2
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE3_FIFO0
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE3_FIFO1
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE3_FIFO2
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE4_FIFO0
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE4_FIFO1
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE4_FIFO2
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE5_FIFO0
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE5_FIFO1
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE5_FIFO2
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE6_FIFO0
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE6_FIFO1
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE6_FIFO2
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE7_FIFO0
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE7_FIFO1
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_MASK_BYTE7_FIFO2
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1
 
- VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2
 
- VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_DMA_ERR
 
- VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_OVRWR
 
- VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_POISON
 
- VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_DMA_ERR
 
- VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_OVRWR
 
- VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_POISON
 
- VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_DMA_ERR
 
- VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_OVRWR
 
- VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_POISON
 
- VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO0_OVRWR
 
- VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO0_PRES
 
- VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO1_OVRWR
 
- VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO1_PRES
 
- VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO2_OVRWR
 
- VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO2_PRES
 
- VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE
 
- VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_KDFC_MAX_SIZE
 
- VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_0
 
- VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_1
 
- VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_2
 
- VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_3
 
- VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_4
 
- VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_5
 
- VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_6
 
- VXGE_HW_KDFC_ENTRY_TYPE_SEL_0_NUMBER_7
 
- VXGE_HW_KDFC_ENTRY_TYPE_SEL_1_NUMBER_8
 
- VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_ECC_DB_ERR
 
- VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_ECC_SG_ERR
 
- VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_MISC_ERR_1
 
- VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_PCIX_ERR
 
- VXGE_HW_KDFC_ERR_REG_ALARM_KDFC_KDFC_SM_ERR_ALARM
 
- VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_ECC_DB_ERR
 
- VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_ECC_SG_ERR
 
- VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_MISC_ERR_1
 
- VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_PCIX_ERR
 
- VXGE_HW_KDFC_ERR_REG_KDFC_KDFC_SM_ERR_ALARM
 
- VXGE_HW_KDFC_FIFO_0_CTRL_WRR_NUMBER
 
- VXGE_HW_KDFC_FIFO_17_CTRL_WRR_NUMBER
 
- VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE
 
- VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0
 
- VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_1
 
- VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_2
 
- VXGE_HW_KDFC_RESET_IN_PROGRESS_NOA_VP
 
- VXGE_HW_KDFC_STATUS_KDFC_WRR_0_READY
 
- VXGE_HW_KDFC_STATUS_KDFC_WRR_1_READY
 
- VXGE_HW_KDFC_STATUS_KDFC_WRR_2_READY
 
- VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_ADD_PAD
 
- VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_BIT_MAP
 
- VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_CTRL_STRUC
 
- VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_FLIP_EN
 
- VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_INT_CTRL
 
- VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_INT_NO
 
- VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE
 
- VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_LEGACY_MODE
 
- VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_MULTI_OP_MODE
 
- VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY
 
- VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_NO_SNOOP
 
- VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_RLX_ORD
 
- VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT
 
- VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN
 
- VXGE_HW_KDFC_TRPL_FIFO_0_WB_ADDRESS_ADD
 
- VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_ADD_PAD
 
- VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_BIT_MAP
 
- VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_CTRL_STRUC
 
- VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_FLIP_EN
 
- VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_INT_CTRL
 
- VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_INT_NO
 
- VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_MODE
 
- VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_MODE_MESSAGES_ONLY
 
- VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_MODE_MULTI_OP_MODE
 
- VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_NO_SNOOP
 
- VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_RLX_ORD
 
- VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_SELECT
 
- VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_SWAP_EN
 
- VXGE_HW_KDFC_TRPL_FIFO_1_WB_ADDRESS_ADD
 
- VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_ADD_PAD
 
- VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_BIT_MAP
 
- VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_CTRL_STRUC
 
- VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_FLIP_EN
 
- VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_INT_CTRL
 
- VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_INT_NO
 
- VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_NO_SNOOP
 
- VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_RLX_ORD
 
- VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_SELECT
 
- VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_SWAP_EN
 
- VXGE_HW_KDFC_TRPL_FIFO_2_WB_ADDRESS_ADD
 
- VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR0
 
- VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR1
 
- VXGE_HW_KDFC_TRPL_FIFO_OFFSET_GET_KDFC_RCTR2
 
- VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_NUM
 
- VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_FIFO_OFFSET
 
- VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR0
 
- VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR1
 
- VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR2
 
- VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_VAPTH_NUM
 
- VXGE_HW_KDFC_VP_PARTITION_0_ENABLE
 
- VXGE_HW_KDFC_VP_PARTITION_0_LENGTH_0
 
- VXGE_HW_KDFC_VP_PARTITION_0_LENGTH_1
 
- VXGE_HW_KDFC_VP_PARTITION_0_NUMBER_0
 
- VXGE_HW_KDFC_VP_PARTITION_0_NUMBER_1
 
- VXGE_HW_KDFC_VP_PARTITION_1_LENGTH_2
 
- VXGE_HW_KDFC_VP_PARTITION_1_LENGTH_3
 
- VXGE_HW_KDFC_VP_PARTITION_1_NUMBER_2
 
- VXGE_HW_KDFC_VP_PARTITION_1_NUMBER_3
 
- VXGE_HW_KDFC_VP_PARTITION_2_LENGTH_4
 
- VXGE_HW_KDFC_VP_PARTITION_2_LENGTH_5
 
- VXGE_HW_KDFC_VP_PARTITION_2_NUMBER_4
 
- VXGE_HW_KDFC_VP_PARTITION_2_NUMBER_5
 
- VXGE_HW_KDFC_VP_PARTITION_3_LENGTH_6
 
- VXGE_HW_KDFC_VP_PARTITION_3_LENGTH_7
 
- VXGE_HW_KDFC_VP_PARTITION_3_NUMBER_6
 
- VXGE_HW_KDFC_VP_PARTITION_3_NUMBER_7
 
- VXGE_HW_KDFC_VP_PARTITION_4_LENGTH_8
 
- VXGE_HW_KDFC_VP_PARTITION_4_LENGTH_9
 
- VXGE_HW_KDFC_VP_PARTITION_5_LENGTH_10
 
- VXGE_HW_KDFC_VP_PARTITION_5_LENGTH_11
 
- VXGE_HW_KDFC_VP_PARTITION_6_LENGTH_12
 
- VXGE_HW_KDFC_VP_PARTITION_6_LENGTH_13
 
- VXGE_HW_KDFC_VP_PARTITION_7_LENGTH_14
 
- VXGE_HW_KDFC_VP_PARTITION_7_LENGTH_15
 
- VXGE_HW_KDFC_VP_PARTITION_8_LENGTH_16
 
- VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_0
 
- VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_1
 
- VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_2
 
- VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_3
 
- VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_4
 
- VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_5
 
- VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_6
 
- VXGE_HW_KDFC_W_ROUND_ROBIN_0_NUMBER_7
 
- VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_0
 
- VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_1
 
- VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_2
 
- VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_3
 
- VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_4
 
- VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_5
 
- VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_6
 
- VXGE_HW_KDFC_W_ROUND_ROBIN_20_NUMBER_7
 
- VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_0
 
- VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_1
 
- VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_2
 
- VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_3
 
- VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_4
 
- VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_5
 
- VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_6
 
- VXGE_HW_KDFC_W_ROUND_ROBIN_40_NUMBER_7
 
- VXGE_HW_L3_CKSUM_OK
 
- VXGE_HW_L4_CKSUM_OK
 
- VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_AUTO_FAILBACK
 
- VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_COLD_FAILOVER_TIMEOUT
 
- VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_FAILBACK_EN
 
- VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_HOT_STANDBY
 
- VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_LACP_DECIDES
 
- VXGE_HW_LAG_ACTIVE_PASSIVE_CFG_PREF_ACTIVE_PORT_NUM
 
- VXGE_HW_LAG_AGGR_ADDR_CFG_ADDR
 
- VXGE_HW_LAG_AGGR_ADDR_CFG_ADDR_SEL
 
- VXGE_HW_LAG_AGGR_ADDR_CFG_USE_PORT_ADDR
 
- VXGE_HW_LAG_AGGR_ADMIN_KEY_KEY
 
- VXGE_HW_LAG_AGGR_ALT_ADMIN_KEY_ALT_AGGR
 
- VXGE_HW_LAG_AGGR_ALT_ADMIN_KEY_KEY
 
- VXGE_HW_LAG_AGGR_ID_CFG_ID
 
- VXGE_HW_LAG_AGGR_OPER_KEY_LAGC_KEY
 
- VXGE_HW_LAG_AGGR_PARTNER_INFO_LAGC_OPER_KEY
 
- VXGE_HW_LAG_AGGR_PARTNER_INFO_LAGC_SYS_PRI
 
- VXGE_HW_LAG_AGGR_PARTNER_SYS_ID_LAGC_ADDR
 
- VXGE_HW_LAG_AGGR_STATE_LAGC_INDIVIDUAL
 
- VXGE_HW_LAG_AGGR_STATE_LAGC_READY
 
- VXGE_HW_LAG_AGGR_STATE_LAGC_RX
 
- VXGE_HW_LAG_AGGR_STATE_LAGC_TX
 
- VXGE_HW_LAG_CFG_EN
 
- VXGE_HW_LAG_CFG_MODE
 
- VXGE_HW_LAG_CFG_PREF_INDIV_PORT_NUM
 
- VXGE_HW_LAG_CFG_RX_DISCARD_BEHAV
 
- VXGE_HW_LAG_CFG_TX_DISCARD_BEHAV
 
- VXGE_HW_LAG_DISTRIB_DEST_MAP_VPATH
 
- VXGE_HW_LAG_LACP_CFG_DISCARD_LACP
 
- VXGE_HW_LAG_LACP_CFG_EN
 
- VXGE_HW_LAG_LACP_CFG_LACP_BEGIN
 
- VXGE_HW_LAG_LACP_CFG_LIBERAL_LEN_CHK
 
- VXGE_HW_LAG_MARKER_CFG_GEN_RCVR_EN
 
- VXGE_HW_LAG_MARKER_CFG_RESP_EN
 
- VXGE_HW_LAG_MARKER_CFG_RESP_TIMEOUT
 
- VXGE_HW_LAG_MARKER_CFG_SLOW_PROTO_MRKR_MIN_INTERVAL
 
- VXGE_HW_LAG_MARKER_CFG_THROTTLE_MRKR_RESP
 
- VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_KEY_10G
 
- VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_KEY_1G
 
- VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_PORT_NUM
 
- VXGE_HW_LAG_PORT_ACTOR_ADMIN_CFG_PORT_PRI
 
- VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_AGGREGATION
 
- VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_COLLECTING
 
- VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_DEFAULTED
 
- VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_DISTRIBUTING
 
- VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_EXPIRED
 
- VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_LACP_ACTIVITY
 
- VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_LACP_TIMEOUT
 
- VXGE_HW_LAG_PORT_ACTOR_ADMIN_STATE_SYNCHRONIZATION
 
- VXGE_HW_LAG_PORT_ACTOR_OPER_KEY_LAGC_KEY
 
- VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_AGGREGATION
 
- VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_COLLECTING
 
- VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_DEFAULTED
 
- VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_DISTRIBUTING
 
- VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_EXPIRED
 
- VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_LACP_ACTIVITY
 
- VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_LACP_TIMEOUT
 
- VXGE_HW_LAG_PORT_ACTOR_OPER_STATE_LAGC_SYNCHRONIZATION
 
- VXGE_HW_LAG_PORT_CFG_DISCARD_SLOW_PROTO
 
- VXGE_HW_LAG_PORT_CFG_DISCARD_UNKNOWN_SLOW_PROTO
 
- VXGE_HW_LAG_PORT_CFG_EN
 
- VXGE_HW_LAG_PORT_CFG_HOST_CHOSEN_AGGR
 
- VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_KEY
 
- VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_PORT_NUM
 
- VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_PORT_PRI
 
- VXGE_HW_LAG_PORT_PARTNER_ADMIN_CFG_SYS_PRI
 
- VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_AGGREGATION
 
- VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_COLLECTING
 
- VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_DEFAULTED
 
- VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_DISTRIBUTING
 
- VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_EXPIRED
 
- VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_LACP_ACTIVITY
 
- VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_LACP_TIMEOUT
 
- VXGE_HW_LAG_PORT_PARTNER_ADMIN_STATE_SYNCHRONIZATION
 
- VXGE_HW_LAG_PORT_PARTNER_ADMIN_SYS_ID_ADDR
 
- VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_KEY
 
- VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_NUM
 
- VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_PORT_PRI
 
- VXGE_HW_LAG_PORT_PARTNER_OPER_INFO_LAGC_SYS_PRI
 
- VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_AGGREGATION
 
- VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_COLLECTING
 
- VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_DEFAULTED
 
- VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_DISTRIBUTING
 
- VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_EXPIRED
 
- VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_LACP_ACTIVITY
 
- VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_LACP_TIMEOUT
 
- VXGE_HW_LAG_PORT_PARTNER_OPER_STATE_LAGC_SYNCHRONIZATION
 
- VXGE_HW_LAG_PORT_PARTNER_OPER_SYS_ID_LAGC_ADDR
 
- VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN
 
- VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN_COUNT
 
- VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_CHURN_STATE
 
- VXGE_HW_LAG_PORT_STATE_VARS_LAGC_ACTOR_INFO_LEN_MISMATCH
 
- VXGE_HW_LAG_PORT_STATE_VARS_LAGC_AGGR_NUM
 
- VXGE_HW_LAG_PORT_STATE_VARS_LAGC_COLL_INFO_LEN_MISMATCH
 
- VXGE_HW_LAG_PORT_STATE_VARS_LAGC_MUX_FSM_STATE
 
- VXGE_HW_LAG_PORT_STATE_VARS_LAGC_MUX_REASON
 
- VXGE_HW_LAG_PORT_STATE_VARS_LAGC_NTT
 
- VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN
 
- VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN_COUNT
 
- VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_CHURN_STATE
 
- VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PARTNER_INFO_LEN_MISMATCH
 
- VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PORT_DISABLED
 
- VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PORT_ENABLED
 
- VXGE_HW_LAG_PORT_STATE_VARS_LAGC_PORT_MOVED
 
- VXGE_HW_LAG_PORT_STATE_VARS_LAGC_READY
 
- VXGE_HW_LAG_PORT_STATE_VARS_LAGC_RX_FSM_STATE
 
- VXGE_HW_LAG_PORT_STATE_VARS_LAGC_SELECTED
 
- VXGE_HW_LAG_PORT_STATE_VARS_LAGC_TERM_INFO_LEN_MISMATCH
 
- VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_CHANGE_COUNT
 
- VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_ACTOR_SYNC_TRANSITION_COUNT
 
- VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_CURRENT_WHILE
 
- VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_CHANGE_COUNT
 
- VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_PARTNER_SYNC_TRANSITION_COUNT
 
- VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_PERIODIC_WHILE
 
- VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_TX_LACP
 
- VXGE_HW_LAG_PORT_TIMER_CNTR_LAGC_WAIT_WHILE
 
- VXGE_HW_LAG_PORT_TO_AGGR_LAGC_AGGR_ID
 
- VXGE_HW_LAG_PORT_TO_AGGR_LAGC_AGGR_VLD_ID
 
- VXGE_HW_LAG_STATUS_XLCM_TIMER_VAL_COLD_FAILOVER
 
- VXGE_HW_LAG_STATUS_XLCM_WAITING_TO_FAILBACK
 
- VXGE_HW_LAG_SYS_CFG_SYS_PRI
 
- VXGE_HW_LAG_SYS_ID_ADDR
 
- VXGE_HW_LAG_SYS_ID_ADDR_SEL
 
- VXGE_HW_LAG_SYS_ID_USE_PORT_ADDR
 
- VXGE_HW_LAG_TIMER_CFG_1_FAST_PER
 
- VXGE_HW_LAG_TIMER_CFG_1_LONG_TIMEOUT
 
- VXGE_HW_LAG_TIMER_CFG_1_SHORT_TIMEOUT
 
- VXGE_HW_LAG_TIMER_CFG_1_SLOW_PER
 
- VXGE_HW_LAG_TIMER_CFG_2_AGGR_WAIT
 
- VXGE_HW_LAG_TIMER_CFG_2_CHURN_DET
 
- VXGE_HW_LAG_TIMER_CFG_2_LONG_TIMER_SCALE
 
- VXGE_HW_LAG_TIMER_CFG_2_SHORT_TIMER_SCALE
 
- VXGE_HW_LAG_TX_CFG_COLL_MAX_DELAY
 
- VXGE_HW_LAG_TX_CFG_DISTRIB_ALG_SEL
 
- VXGE_HW_LAG_TX_CFG_DISTRIB_REMAP_IF_FAIL
 
- VXGE_HW_LAG_TX_CFG_INCR_TX_AGGR_STATS
 
- VXGE_HW_LAG_TX_STATUS_TLAG_TIMER_VAL_EMPTIED_LINK
 
- VXGE_HW_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKR
 
- VXGE_HW_LAG_TX_STATUS_TLAG_TIMER_VAL_SLOW_PROTO_MRKRRESP
 
- VXGE_HW_LINK_DOWN
 
- VXGE_HW_LINK_NONE
 
- VXGE_HW_LINK_UP
 
- VXGE_HW_LSO_ERROR_REG_PCC_LSO_ABORT
 
- VXGE_HW_LSO_ERROR_REG_PCC_LSO_FSM_ERR_ALARM
 
- VXGE_HW_MAC_ADDR_LEARN_DEFAULT
 
- VXGE_HW_MAC_HEADER_MAX_SIZE
 
- VXGE_HW_MAC_MAX_MAC_PORT_ID
 
- VXGE_HW_MASK_VECTOR_MASK_VECTOR
 
- VXGE_HW_MAX_DEVICE_POLL_MILLIS
 
- VXGE_HW_MAX_DMA_BLOCK_POOL_SIZE
 
- VXGE_HW_MAX_FIFO_ALIGNMENT_SIZE
 
- VXGE_HW_MAX_FIFO_BLOCKS
 
- VXGE_HW_MAX_FIFO_FRAGS
 
- VXGE_HW_MAX_FIFO_MEMBLOCK_SIZE
 
- VXGE_HW_MAX_INTR_PER_VP
 
- VXGE_HW_MAX_MTU
 
- VXGE_HW_MAX_PAYLOAD_SIZE_512
 
- VXGE_HW_MAX_POLLING_COUNT
 
- VXGE_HW_MAX_RESOURCE_ASSIGNMENTS_PCI_MAX_VPATHS
 
- VXGE_HW_MAX_RESOURCE_ASSIGNMENTS_PCI_MAX_VPLANE
 
- VXGE_HW_MAX_RING_BLOCKS
 
- VXGE_HW_MAX_ROM_IMAGES
 
- VXGE_HW_MAX_TIM_BTIMER_VAL
 
- VXGE_HW_MAX_TIM_LTIMER_VAL
 
- VXGE_HW_MAX_TIM_RTIMER_VAL
 
- VXGE_HW_MAX_TIM_UEC_A
 
- VXGE_HW_MAX_TIM_UEC_B
 
- VXGE_HW_MAX_TIM_UEC_C
 
- VXGE_HW_MAX_TIM_UEC_D
 
- VXGE_HW_MAX_TIM_URANGE_A
 
- VXGE_HW_MAX_TIM_URANGE_B
 
- VXGE_HW_MAX_TIM_URANGE_C
 
- VXGE_HW_MAX_VIRTUAL_PATHS
 
- VXGE_HW_MC_ERR_REG_MC_G3IF_RD_FIFO_ECC_DB_ERR
 
- VXGE_HW_MC_ERR_REG_MC_G3IF_RD_FIFO_ECC_SG_ERR
 
- VXGE_HW_MC_ERR_REG_MC_MIRI_ECC_DB_ERR_0
 
- VXGE_HW_MC_ERR_REG_MC_MIRI_ECC_DB_ERR_1
 
- VXGE_HW_MC_ERR_REG_MC_MIRI_ECC_SG_ERR_0
 
- VXGE_HW_MC_ERR_REG_MC_MIRI_ECC_SG_ERR_1
 
- VXGE_HW_MC_ERR_REG_MC_SM_ERR
 
- VXGE_HW_MC_ERR_REG_MC_XFMD_MEM_ECC_DB_ERR_A
 
- VXGE_HW_MC_ERR_REG_MC_XFMD_MEM_ECC_DB_ERR_B
 
- VXGE_HW_MC_ERR_REG_MC_XFMD_MEM_ECC_SG_ERR_A
 
- VXGE_HW_MC_ERR_REG_MC_XFMD_MEM_ECC_SG_ERR_B
 
- VXGE_HW_MC_INT_STATUS_FAU_ECC_ERR_FAU_ECC_INT
 
- VXGE_HW_MC_INT_STATUS_FAU_GEN_ERR_FAU_GEN_INT
 
- VXGE_HW_MC_INT_STATUS_GROCRC_ALARM_ROCRC_INT
 
- VXGE_HW_MC_INT_STATUS_MC_ERR_MC_INT
 
- VXGE_HW_MDIO_MGR_ACCESS_PORT_ADDR
 
- VXGE_HW_MDIO_MGR_ACCESS_PORT_DATA
 
- VXGE_HW_MDIO_MGR_ACCESS_PORT_DEVAD
 
- VXGE_HW_MDIO_MGR_ACCESS_PORT_OP_TYPE
 
- VXGE_HW_MDIO_MGR_ACCESS_PORT_PREAMBLE
 
- VXGE_HW_MDIO_MGR_ACCESS_PORT_PRTAD
 
- VXGE_HW_MDIO_MGR_ACCESS_PORT_STROBE_ONE
 
- VXGE_HW_MDIO_MGR_ACCESS_PORT_STROBE_TWO
 
- VXGE_HW_MDIO_MGR_ACCESS_PORT_ST_PATTERN
 
- VXGE_HW_MIN_DEVICE_POLL_MILLIS
 
- VXGE_HW_MIN_DMA_BLOCK_POOL_SIZE
 
- VXGE_HW_MIN_FIFO_ALIGNMENT_SIZE
 
- VXGE_HW_MIN_FIFO_BLOCKS
 
- VXGE_HW_MIN_FIFO_FRAGS
 
- VXGE_HW_MIN_FIFO_MEMBLOCK_SIZE
 
- VXGE_HW_MIN_MTU
 
- VXGE_HW_MIN_RING_BLOCKS
 
- VXGE_HW_MIN_SUCCESSIVE_IDLE_COUNT
 
- VXGE_HW_MIN_TIM_BTIMER_VAL
 
- VXGE_HW_MIN_TIM_LTIMER_VAL
 
- VXGE_HW_MIN_TIM_RTIMER_VAL
 
- VXGE_HW_MIN_TIM_UEC_A
 
- VXGE_HW_MIN_TIM_UEC_B
 
- VXGE_HW_MIN_TIM_UEC_C
 
- VXGE_HW_MIN_TIM_UEC_D
 
- VXGE_HW_MIN_TIM_URANGE_A
 
- VXGE_HW_MIN_TIM_URANGE_B
 
- VXGE_HW_MIN_TIM_URANGE_C
 
- VXGE_HW_MRPCIM_DEBUG_STATS0_GET_INI_RD_DROP
 
- VXGE_HW_MRPCIM_DEBUG_STATS0_GET_INI_WR_DROP
 
- VXGE_HW_MRPCIM_DEBUG_STATS0_INI_RD_DROP
 
- VXGE_HW_MRPCIM_DEBUG_STATS0_INI_WR_DROP
 
- VXGE_HW_MRPCIM_DEBUG_STATS1_GET_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED
 
- VXGE_HW_MRPCIM_DEBUG_STATS1_VPLANE_WRCRDTARB_PH_CRDT_DEPLETED
 
- VXGE_HW_MRPCIM_DEBUG_STATS2_GET_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED
 
- VXGE_HW_MRPCIM_DEBUG_STATS2_VPLANE_WRCRDTARB_PD_CRDT_DEPLETED
 
- VXGE_HW_MRPCIM_DEBUG_STATS3_GET_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED
 
- VXGE_HW_MRPCIM_DEBUG_STATS3_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED
 
- VXGE_HW_MRPCIM_DEBUG_STATS4_GET_INI_RD_VPIN_DROP
 
- VXGE_HW_MRPCIM_DEBUG_STATS4_GET_INI_WR_VPIN_DROP
 
- VXGE_HW_MRPCIM_DEBUG_STATS4_INI_RD_VPIN_DROP
 
- VXGE_HW_MRPCIM_DEBUG_STATS4_INI_WR_VPIN_DROP
 
- VXGE_HW_MRPCIM_GENERAL_CFG1_CLEAR_SERR
 
- VXGE_HW_MRPCIM_GENERAL_CFG2_DIS_HOST_PIPELINE_WR
 
- VXGE_HW_MRPCIM_GENERAL_CFG2_DIS_SWIF_PROT_ON_RDS
 
- VXGE_HW_MRPCIM_GENERAL_CFG2_EN_BLOCK_MSIX_DUE_TO_SERR
 
- VXGE_HW_MRPCIM_GENERAL_CFG2_FLASH_READ_MSB
 
- VXGE_HW_MRPCIM_GENERAL_CFG2_FORCE_SENDING_INTA
 
- VXGE_HW_MRPCIM_GENERAL_CFG2_IGNORE_VPATH_RST_FOR_MSIX
 
- VXGE_HW_MRPCIM_GENERAL_CFG2_INI_TIMEOUT_EN_MRD
 
- VXGE_HW_MRPCIM_GENERAL_CFG2_INI_TIMEOUT_EN_MWR
 
- VXGE_HW_MRPCIM_GENERAL_CFG2_INS_TX_CPL_TD
 
- VXGE_HW_MRPCIM_GENERAL_CFG2_INS_TX_RD_TD
 
- VXGE_HW_MRPCIM_GENERAL_CFG2_INS_TX_WR_TD
 
- VXGE_HW_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_ENABLE
 
- VXGE_HW_MRPCIM_GENERAL_CFG2_MRPCIM_STATS_MAP_TO_VPATH
 
- VXGE_HW_MRPCIM_GENERAL_CFG3_BYPASS_DAISY_CHAIN
 
- VXGE_HW_MRPCIM_GENERAL_CFG3_CPL_ECC_ENABLE_N
 
- VXGE_HW_MRPCIM_GENERAL_CFG3_ILLEGAL_RD_CA_OR_UNSUPN
 
- VXGE_HW_MRPCIM_GENERAL_CFG3_MR_MAX_MVFS
 
- VXGE_HW_MRPCIM_GENERAL_CFG3_MR_MVF_TBL_SIZE
 
- VXGE_HW_MRPCIM_GENERAL_CFG3_PF0_SW_RESET_EN
 
- VXGE_HW_MRPCIM_GENERAL_CFG3_PROTECTION_CA_OR_UNSUPN
 
- VXGE_HW_MRPCIM_GENERAL_CFG3_RD_BIT_FLIPEN
 
- VXGE_HW_MRPCIM_GENERAL_CFG3_RD_BYTE_SWAPEN
 
- VXGE_HW_MRPCIM_GENERAL_CFG3_REG_MODIFIED_CFG
 
- VXGE_HW_MRPCIM_GENERAL_CFG3_WR_BIT_FLIPEN
 
- VXGE_HW_MRPCIM_GENERAL_CFG3_WR_BYTE_SWAPEN
 
- VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_INI_SERR_DET
 
- VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_INTCTL_MSIX_FSM_ERR
 
- VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_INTCTL_MSI_OVERFLOW
 
- VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_KDFCCTL_FSM_ERR
 
- VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_MRIOVCTL_FSM_ERR
 
- VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_PPIF_PCI_NOT_FLUSH_DURING_SW_RESET
 
- VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_PPIF_SW_RESET_FSM_ERR
 
- VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_SPI_FLSH_ERR
 
- VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_SPI_IIC_ACK_ERR
 
- VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_SPI_IIC_CHKSUM_ERR
 
- VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_STATSB_FSM_ERR
 
- VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_XGEN_FSM_ERR
 
- VXGE_HW_MRPCIM_GENERAL_ERRORS_REG_XMEM_FSM_ERR
 
- VXGE_HW_MRPCIM_GENERAL_INT_MASK_DRBELL_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_MASK_FBMC_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3CMCT_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3CMIFL_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3CMIFU_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3FBCT_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_MASK_G3FBIF_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_MASK_GCMG1_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_MASK_GCMG2_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_MASK_GCMG3_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_MASK_MSG_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_MASK_ONE_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_MASK_PCI_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_MASK_PCMG1_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_MASK_PCMG2_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_MASK_PCMG3_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_MASK_PIC_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_MASK_RTDMA_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_MASK_RXMAC_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_MASK_TMAC_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_MASK_TPA_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_MASK_WRDMA_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_MASK_XMAC_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_STATUS_DRBELL_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_STATUS_FBMC_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3CMCT_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3CMIFL_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3CMIFU_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3FBCT_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_STATUS_G3FBIF_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_STATUS_GCMG1_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_STATUS_GCMG2_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_STATUS_GCMG3_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_STATUS_MSG_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_STATUS_ONE_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PCI_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PCMG1_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PCMG2_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PCMG3_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_STATUS_PIC_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_STATUS_RTDMA_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_STATUS_RXMAC_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_STATUS_TMAC_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_STATUS_TPA_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_STATUS_WRDMA_INT
 
- VXGE_HW_MRPCIM_GENERAL_INT_STATUS_XMAC_INT
 
- VXGE_HW_MRPCIM_MSG_REG_SWIF_MRPCIM_TO_SRPCIM_RMSG_INT
 
- VXGE_HW_MRPCIM_PPIF_INT_STATUS_CONFIG_ERRORS_CONFIG_INT
 
- VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_CRDT_INT
 
- VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE0_CRD_INT_VPLANE0_INT
 
- VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE10_CRD_INT_VPLANE10_INT
 
- VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE11_CRD_INT_VPLANE11_INT
 
- VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE12_CRD_INT_VPLANE12_INT
 
- VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE13_CRD_INT_VPLANE13_INT
 
- VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE14_CRD_INT_VPLANE14_INT
 
- VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE15_CRD_INT_VPLANE15_INT
 
- VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE16_CRD_INT_VPLANE16_INT
 
- VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE1_CRD_INT_VPLANE1_INT
 
- VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE2_CRD_INT_VPLANE2_INT
 
- VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE3_CRD_INT_VPLANE3_INT
 
- VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE4_CRD_INT_VPLANE4_INT
 
- VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE5_CRD_INT_VPLANE5_INT
 
- VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE6_CRD_INT_VPLANE6_INT
 
- VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE7_CRD_INT_VPLANE7_INT
 
- VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE8_CRD_INT_VPLANE8_INT
 
- VXGE_HW_MRPCIM_PPIF_INT_STATUS_CRDT_ERRORS_VPLANE9_CRD_INT_VPLANE9_INT
 
- VXGE_HW_MRPCIM_PPIF_INT_STATUS_DMA_ERRORS_DMA_INT
 
- VXGE_HW_MRPCIM_PPIF_INT_STATUS_INI_ERRORS_INI_INT
 
- VXGE_HW_MRPCIM_PPIF_INT_STATUS_PLL_ERRORS_PLL_INT
 
- VXGE_HW_MRPCIM_PPIF_INT_STATUS_TGT_ERRORS_TGT_INT
 
- VXGE_HW_MRPCIM_PPIF_INT_STATUS_VPATH_TO_MRPCIM_ALARM_VPATH_TO_MRPCIM_ALARM_INT
 
- VXGE_HW_MRPCIM_REG_MODIFIED_MRPCIM_REG_MODIFIED
 
- VXGE_HW_MRPCIM_RST_IN_PROG_MRPCIM_RST_IN_PROG
 
- VXGE_HW_MRPCIM_STATS_START_HOST_ADDR_MRPCIM_STATS_START_HOST_ADDR
 
- VXGE_HW_MRPCIM_TO_SRPCIM_ALARM_REG_PPIF_MRPCIM_TO_SRPCIM_ALARM
 
- VXGE_HW_MRPCIM_TO_SRPCIM_RMSG_SWIF_MRPCIM_TO_SRPCIM_RMSG
 
- VXGE_HW_MRPCIM_TO_SRPCIM_VPLANE_WMSG_MRPCIM_TO_SRPCIM_VPLANE_WMSG
 
- VXGE_HW_MRPCIM_TO_VPATH_ALARM_REG_PPIF_MRPCIM_TO_VPATH_ALARM
 
- VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION
 
- VXGE_HW_MR_RQA_TOP_PRTY_FOR_VH_RQA_TOP_PRTY_FOR_VH
 
- VXGE_HW_MR_SR_VH0_INVALID_CONFIG
 
- VXGE_HW_MSG_DMQ_NONI_RTL_PREFETCH_BYPASS_ENABLE
 
- VXGE_HW_MSG_ERR2_REG_MP_MP_PIFT_IF_CREDIT_CNT_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_CMG2MSG_DISPATCH_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_CP_TA_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_DMA_TA_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_DMQ_DISPATCH_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_FBMC_OWN_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA0_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA10_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA11_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA12_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA13_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA14_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA15_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA16_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA1_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA2_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA3_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA4_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA5_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA6_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA7_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA8_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_LONGTERMUMQ_TA9_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_PIC_WRITE_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_RPE2MSG_DISPATCH_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_RXPE2MSG_DISPATCH_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_RXPE_TA_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_SWIFREG_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_SWIF_DISPATCH_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_SWIF_TA_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_TIM_WRITE_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_TXPE2MSG_DISPATCH_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_TXPE_TA_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_UMQ2PIC_CMD_FIFO_ERR
 
- VXGE_HW_MSG_ERR2_REG_MSG_QUE_UMQ_TA_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR2_REG_TIM_TIM2MSG_CMD_FIFO_ERR
 
- VXGE_HW_MSG_ERR2_REG_UP_UP_PIFT_IF_CREDIT_CNT_ERR
 
- VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR0
 
- VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR1
 
- VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR2
 
- VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR3
 
- VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR4
 
- VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR5
 
- VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR6
 
- VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_DB_ERR7
 
- VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR0
 
- VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR1
 
- VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR2
 
- VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR3
 
- VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR4
 
- VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR5
 
- VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR6
 
- VXGE_HW_MSG_ERR3_REG_MP_MXP_DCACHE_SG_ERR7
 
- VXGE_HW_MSG_ERR3_REG_MP_MXP_ICACHE_DB_ERR0
 
- VXGE_HW_MSG_ERR3_REG_MP_MXP_ICACHE_DB_ERR1
 
- VXGE_HW_MSG_ERR3_REG_MP_MXP_ICACHE_SG_ERR0
 
- VXGE_HW_MSG_ERR3_REG_MP_MXP_ICACHE_SG_ERR1
 
- VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR0
 
- VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR1
 
- VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR2
 
- VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR3
 
- VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR4
 
- VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR5
 
- VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR6
 
- VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_DB_ERR7
 
- VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR0
 
- VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR1
 
- VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR2
 
- VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR3
 
- VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR4
 
- VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR5
 
- VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR6
 
- VXGE_HW_MSG_ERR3_REG_UP_UXP_DCACHE_SG_ERR7
 
- VXGE_HW_MSG_ERR3_REG_UP_UXP_ICACHE_DB_ERR0
 
- VXGE_HW_MSG_ERR3_REG_UP_UXP_ICACHE_DB_ERR1
 
- VXGE_HW_MSG_ERR3_REG_UP_UXP_ICACHE_SG_ERR0
 
- VXGE_HW_MSG_ERR3_REG_UP_UXP_ICACHE_SG_ERR1
 
- VXGE_HW_MSG_ERR_REG_MP_MXP_DTAG_DB_ERR
 
- VXGE_HW_MSG_ERR_REG_MP_MXP_DTAG_SG_ERR
 
- VXGE_HW_MSG_ERR_REG_MP_MXP_ITAG_DB_ERR
 
- VXGE_HW_MSG_ERR_REG_MP_MXP_ITAG_SG_ERR
 
- VXGE_HW_MSG_ERR_REG_MP_MXP_PMON_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR_REG_MP_MXP_TRACE_DB_ERR
 
- VXGE_HW_MSG_ERR_REG_MP_MXP_TRACE_SG_ERR
 
- VXGE_HW_MSG_ERR_REG_MP_MXP_WAKE_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_FRMQRY_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_BWR_PF_DB_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_BWR_PF_SG_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_BWR_SIF_FIFO_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_CMG2MSG_DB_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_CMG2MSG_SG_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_CXP2SWIF_FIFO_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_DMA_READ_FIFO_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_DMA_RESP_ECC_DB_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_DMA_RESP_ECC_SG_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_DMA_READ_CMD_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_DMA_RESP_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_ECC_DB_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_ECC_SG_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_DMQ_OWN_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_KDFC_SIF_FIFO_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_MXP2UXP_FIFO_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_PDA_ACC_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_REG_READ_FIFO_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_REG_RESP_FIFO_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_RPE2MSG_DB_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_RPE2MSG_SG_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_RXPE2MSG_DB_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_RXPE2MSG_SG_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_TXPE2MSG_DB_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_TXPE2MSG_SG_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_UMQ_BWR_PF_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_UMQ_DB_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_UMQ_SG_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_UMQ_WRITE_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_QUE_UXP2MXP_FIFO_ERR
 
- VXGE_HW_MSG_ERR_REG_MSG_XFMDQRY_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR_REG_UP_UXP_DTAG_DB_ERR
 
- VXGE_HW_MSG_ERR_REG_UP_UXP_DTAG_SG_ERR
 
- VXGE_HW_MSG_ERR_REG_UP_UXP_ITAG_DB_ERR
 
- VXGE_HW_MSG_ERR_REG_UP_UXP_ITAG_SG_ERR
 
- VXGE_HW_MSG_ERR_REG_UP_UXP_PMON_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_ERR_REG_UP_UXP_TRACE_DB_ERR
 
- VXGE_HW_MSG_ERR_REG_UP_UXP_TRACE_SG_ERR
 
- VXGE_HW_MSG_ERR_REG_UP_UXP_WAKE_FSM_INTEGRITY_ERR
 
- VXGE_HW_MSG_EXC_CAUSE_MP_MXP
 
- VXGE_HW_MSG_EXC_CAUSE_UP_UXP
 
- VXGE_HW_MSG_EXC_REG_MP_MXP_CAUSE_CRIT_INT
 
- VXGE_HW_MSG_EXC_REG_MP_MXP_CAUSE_INFO_INT
 
- VXGE_HW_MSG_EXC_REG_MP_MXP_SERR
 
- VXGE_HW_MSG_EXC_REG_UP_UXP_CAUSE_CRIT_INT
 
- VXGE_HW_MSG_EXC_REG_UP_UXP_CAUSE_INFO_INT
 
- VXGE_HW_MSG_EXC_REG_UP_UXP_SERR
 
- VXGE_HW_MSG_INT_STATUS_MSG_ERR2_MSG_ERR2_INT
 
- VXGE_HW_MSG_INT_STATUS_MSG_ERR3_MSG_ERR3_INT
 
- VXGE_HW_MSG_INT_STATUS_MSG_ERR_MSG_ERR_INT
 
- VXGE_HW_MSG_INT_STATUS_MSG_EXC_MSG_XT_EXC_INT
 
- VXGE_HW_MSG_INT_STATUS_TIM_ERR_TIM_INT
 
- VXGE_HW_MSG_MXP_MR_READY_MP_BOOTED
 
- VXGE_HW_MSG_PCI_CFG_DMQ_NO_SNOOP
 
- VXGE_HW_MSG_PCI_CFG_GENDMA_NO_SNOOP
 
- VXGE_HW_MSG_PCI_CFG_UMQDMQ_IR_NO_SNOOP
 
- VXGE_HW_MSG_PCI_CFG_UMQ_NO_SNOOP
 
- VXGE_HW_MSG_QPAD_EN_CFG_DMQ_BWR_READ
 
- VXGE_HW_MSG_QPAD_EN_CFG_MXP_GENDMA_READ
 
- VXGE_HW_MSG_QPAD_EN_CFG_MXP_GENDMA_WRITE
 
- VXGE_HW_MSG_QPAD_EN_CFG_UMQDMQ_IR_WRITE
 
- VXGE_HW_MSG_QPAD_EN_CFG_UMQ_BWR_READ
 
- VXGE_HW_MSG_QPAD_EN_CFG_UMQ_MSG_WRITE
 
- VXGE_HW_MSG_QPAD_EN_CFG_UXP_GENDMA_READ
 
- VXGE_HW_MSG_QPAD_EN_CFG_UXP_GENDMA_WRITE
 
- VXGE_HW_MSG_RESET_IN_PROGRESS_MSG_COMPOSITE
 
- VXGE_HW_MSG_UMQ_RTL_BWR_PREFETCH_DISABLE
 
- VXGE_HW_MSG_UXP_MR_READY_UP_BOOTED
 
- VXGE_HW_MSIXGRP_NO_TABLE_SIZE
 
- VXGE_HW_MSIX_PENDING_VECTOR_MSIX_PENDING_VECTOR
 
- VXGE_HW_MXP_CMDS_RESET_IN_PROGRESS_NOA_VP
 
- VXGE_HW_NOA_CTRL_FRM_PRTY_QUOTA
 
- VXGE_HW_NOA_CTRL_IGNORE_KDFC_IF_STATUS
 
- VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE0
 
- VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE1
 
- VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE2
 
- VXGE_HW_NOA_CTRL_MAX_JOB_CNT_FOR_WDE3
 
- VXGE_HW_NOA_CTRL_NON_FRM_PRTY_QUOTA
 
- VXGE_HW_NOA_WCT_CTRL_VP_INT_NUM
 
- VXGE_HW_NODBW_GET_LAST_TXD_NUMBER
 
- VXGE_HW_NODBW_GET_NO_SNOOP
 
- VXGE_HW_NODBW_GET_TYPE
 
- VXGE_HW_NODBW_LAST_TXD_NUMBER
 
- VXGE_HW_NODBW_LIST_NO_SNOOP
 
- VXGE_HW_NODBW_LIST_NO_SNOOP_TXD_READ_TXD0_WRITE
 
- VXGE_HW_NODBW_LIST_NO_SNOOP_TX_FRAME_DATA_READ
 
- VXGE_HW_NODBW_TYPE
 
- VXGE_HW_NODBW_TYPE_NODBW
 
- VXGE_HW_NOFFLOAD_RESET_IN_PROGRESS_PRC_VP
 
- VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION
 
- VXGE_HW_NO_MR_SR_VH0_FUNCTION0
 
- VXGE_HW_NO_MR_SR_VH0_VIRTUAL_FUNCTION
 
- VXGE_HW_OK
 
- VXGE_HW_ONE_CFG_VP_RDY
 
- VXGE_HW_ONE_COMMON_PET_VPATH_RESET_IN_PROGRESS
 
- VXGE_HW_ONE_INT_STATUS_DLM_ERR_DLM_INT
 
- VXGE_HW_ONE_INT_STATUS_OES_ERR_OES_INT
 
- VXGE_HW_ONE_INT_STATUS_PE_ERR_PE_INT
 
- VXGE_HW_ONE_INT_STATUS_RPE_ERR_RPE_INT
 
- VXGE_HW_ONE_INT_STATUS_RPE_FSM_ERR_RPE_FSM_INT
 
- VXGE_HW_ONE_INT_STATUS_RXPE_ERR_RXPE_INT
 
- VXGE_HW_ONE_INT_STATUS_TXPE_BCC_MEM_DB_ECC_ERR_TXPE_BCC_MEM_DB_ECC_INT
 
- VXGE_HW_ONE_INT_STATUS_TXPE_BCC_MEM_SG_ECC_ERR_TXPE_BCC_MEM_SG_ECC_INT
 
- VXGE_HW_ONE_INT_STATUS_TXPE_ERR_TXPE_INT
 
- VXGE_HW_ONE_SHOT_VECT0_EN_ONE_SHOT_VECT0_EN
 
- VXGE_HW_ONE_SHOT_VECT1_EN_ONE_SHOT_VECT1_EN
 
- VXGE_HW_ONE_SHOT_VECT2_EN_ONE_SHOT_VECT2_EN
 
- VXGE_HW_ONE_SHOT_VECT3_EN_ONE_SHOT_VECT3_EN
 
- VXGE_HW_ORP_ERR_REG_ORP_FIFO_DB_ERR
 
- VXGE_HW_ORP_ERR_REG_ORP_FIFO_SG_ERR
 
- VXGE_HW_ORP_ERR_REG_ORP_FRM_FIFO_UFLOW_ERR
 
- VXGE_HW_ORP_ERR_REG_ORP_OPTPRS_SHADOW_ERR
 
- VXGE_HW_ORP_ERR_REG_ORP_OUTFRM_SHADOW_ERR
 
- VXGE_HW_ORP_ERR_REG_ORP_OUTQEM_FSM_ERR
 
- VXGE_HW_ORP_ERR_REG_ORP_OUTQEM_SHADOW_ERR
 
- VXGE_HW_ORP_ERR_REG_ORP_OUTREAD_FSM_ERR
 
- VXGE_HW_ORP_ERR_REG_ORP_OUTREAD_SHADOW_ERR
 
- VXGE_HW_ORP_ERR_REG_ORP_XFMD_FIFO_UFLOW_ERR
 
- VXGE_HW_ORP_ERR_REG_ORP_XFMD_RCV_FSM_ERR
 
- VXGE_HW_ORP_ERR_REG_ORP_XFMD_RCV_SHADOW_ERR
 
- VXGE_HW_OUTSTANDING_READ_OUTSTANDING_READ
 
- VXGE_HW_PCC_CFG_PCC_ECC_ENABLE_N
 
- VXGE_HW_PCC_CFG_PCC_ENABLE
 
- VXGE_HW_PCC_CONTROL_EARLY_ASSIGN_EN
 
- VXGE_HW_PCC_CONTROL_FE_ENABLE
 
- VXGE_HW_PCC_CONTROL_UNBLOCK_DB_ERR
 
- VXGE_HW_PCC_ERROR_REG_PCC_PCC_FRM_BUF_DBE
 
- VXGE_HW_PCC_ERROR_REG_PCC_PCC_FRM_BUF_SBE
 
- VXGE_HW_PCC_ERROR_REG_PCC_PCC_FSM_ERR_ALARM
 
- VXGE_HW_PCC_ERROR_REG_PCC_PCC_SERR
 
- VXGE_HW_PCC_ERROR_REG_PCC_PCC_TXDO_DBE
 
- VXGE_HW_PCC_ERROR_REG_PCC_PCC_TXDO_SBE
 
- VXGE_HW_PCIPIF_INT_STATUS_DBECC_ERR_DBECC_ERR_INT
 
- VXGE_HW_PCIPIF_INT_STATUS_GENERAL_ERR_GENERAL_ERR_INT
 
- VXGE_HW_PCIPIF_INT_STATUS_MRPCIM_SPARE_R1_MRPCIM_SPARE_R1_INT
 
- VXGE_HW_PCIPIF_INT_STATUS_SBECC_ERR_SBECC_ERR_INT
 
- VXGE_HW_PCIPIF_INT_STATUS_SRPCIM_MSG_SRPCIM_MSG_INT
 
- VXGE_HW_PCI_CONFIG_ACCESS_CFG1_ADDRESS
 
- VXGE_HW_PCI_CONFIG_ACCESS_CFG1_SEL_FUNC0
 
- VXGE_HW_PCI_CONFIG_ACCESS_CFG2_REQ
 
- VXGE_HW_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR
 
- VXGE_HW_PCI_CONFIG_ACCESS_STATUS_DATA
 
- VXGE_HW_PCI_CONFIG_ERRORS_REG_PCICONFIG_COR_ERR
 
- VXGE_HW_PCI_CONFIG_ERRORS_REG_PCICONFIG_STATUS_ERR
 
- VXGE_HW_PCI_CONFIG_ERRORS_REG_PCICONFIG_UNCOR_ERR
 
- VXGE_HW_PCI_EXP_DEVCTL_READRQ
 
- VXGE_HW_PCI_EXP_LNKCAP_LNK_SPEED
 
- VXGE_HW_PCI_EXP_LNKCAP_LNK_WIDTH
 
- VXGE_HW_PCI_EXP_LNKCAP_LW_RES
 
- VXGE_HW_PCMG1_INT_STATUS_PQCC_CQM_ERR_PQCC_CQM_INT
 
- VXGE_HW_PCMG1_INT_STATUS_PQCC_ERR_PQCC_INT
 
- VXGE_HW_PCMG1_INT_STATUS_PQCC_SQM_ERR_PQCC_SQM_INT
 
- VXGE_HW_PCMG1_INT_STATUS_PSSCC_ERR_PSSCC_INT
 
- VXGE_HW_PCMG2_INT_STATUS_CP_ERR_CP_ERR_INT
 
- VXGE_HW_PCMG2_INT_STATUS_CP_EXC_CP_XT_EXC_INT
 
- VXGE_HW_PCMG2_INT_STATUS_PXTMC_ERR_PXTMC_INT
 
- VXGE_HW_PDA_ALARM_REG_PDA_HSC_FIFO_ERR
 
- VXGE_HW_PDA_ALARM_REG_PDA_SM_ERR
 
- VXGE_HW_PDA_PCC_JOB_MONITOR_PDA_PCC_JOB_STATUS
 
- VXGE_HW_PDA_STATUS1_PDA_WRAP_0_CTR
 
- VXGE_HW_PDA_STATUS1_PDA_WRAP_1_CTR
 
- VXGE_HW_PDA_STATUS1_PDA_WRAP_2_CTR
 
- VXGE_HW_PDA_STATUS1_PDA_WRAP_3_CTR
 
- VXGE_HW_PDA_STATUS1_PDA_WRAP_4_CTR
 
- VXGE_HW_PDA_STATUS1_PDA_WRAP_5_CTR
 
- VXGE_HW_PDA_STATUS1_PDA_WRAP_6_CTR
 
- VXGE_HW_PDA_STATUS1_PDA_WRAP_7_CTR
 
- VXGE_HW_PENDING
 
- VXGE_HW_PE_MR2VP_ACK_BLK_LIMIT_BLK_LIMIT
 
- VXGE_HW_PE_MR2VP_RIRR_LIRR_BLK_LIMIT_LIRR_BLK_LIMIT
 
- VXGE_HW_PE_MR2VP_RIRR_LIRR_BLK_LIMIT_RIRR_BLK_LIMIT
 
- VXGE_HW_PF_SW_RESET_COMMAND
 
- VXGE_HW_PF_SW_RESET_PF_SW_RESET
 
- VXGE_HW_PF_VPATH_ASSIGNMENTS_PF_VPATH_ASSIGNMENTS
 
- VXGE_HW_PHASE_CFG_IMMM_RD_PHASE_EN
 
- VXGE_HW_PHASE_CFG_IMMM_WR_PHASE_EN
 
- VXGE_HW_PHASE_CFG_QCC_RD_PHASE_EN
 
- VXGE_HW_PHASE_CFG_QCC_WR_PHASE_EN
 
- VXGE_HW_PHASE_CFG_RCBM_RD_PHASE_EN
 
- VXGE_HW_PHASE_CFG_RCBM_WR_PHASE_EN
 
- VXGE_HW_PHASE_CFG_RXD_RC_RD_PHASE_EN
 
- VXGE_HW_PHASE_CFG_RXD_RC_WR_PHASE_EN
 
- VXGE_HW_PHASE_CFG_RXD_RHS_RD_PHASE_EN
 
- VXGE_HW_PHASE_CFG_RXD_RHS_WR_PHASE_EN
 
- VXGE_HW_PHASE_CFG_UMQM_RD_PHASE_EN
 
- VXGE_HW_PHASE_CFG_UMQM_WR_PHASE_EN
 
- VXGE_HW_PIFM_RD_FLIP_EN_PIFM_RD_FLIP_EN
 
- VXGE_HW_PIFM_RD_SWAP_EN_PIFM_RD_SWAP_EN
 
- VXGE_HW_PIFM_WR_FLIP_EN_PIFM_WR_FLIP_EN
 
- VXGE_HW_PIFM_WR_SWAP_EN_PIFM_WR_SWAP_EN
 
- VXGE_HW_PLL_ERRORS_REG_CORE_CMG_PLL_OOL
 
- VXGE_HW_PLL_ERRORS_REG_CORE_FB_PLL_OOL
 
- VXGE_HW_PLL_ERRORS_REG_CORE_X_PLL_OOL
 
- VXGE_HW_PORT_STATS_LEN
 
- VXGE_HW_PRC_ALARM_REG_PRC_QUANTA_SIZE_ERR
 
- VXGE_HW_PRC_ALARM_REG_PRC_RING_BUMP
 
- VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ABORT
 
- VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ERR
 
- VXGE_HW_PRC_CFG1_GREEDY_RETURN
 
- VXGE_HW_PRC_CFG1_QUICK_SHOT
 
- VXGE_HW_PRC_CFG1_RESET_TIMER_ON_RXD_RET
 
- VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE
 
- VXGE_HW_PRC_CFG1_RX_TIMER_CI
 
- VXGE_HW_PRC_CFG1_RX_TIMER_VAL
 
- VXGE_HW_PRC_CFG1_TIM_RING_BUMP_INT_ENABLE
 
- VXGE_HW_PRC_CFG4_BACKOFF_INTERVAL
 
- VXGE_HW_PRC_CFG4_BIMODAL_INTERRUPT
 
- VXGE_HW_PRC_CFG4_FRM_NO_SNOOP
 
- VXGE_HW_PRC_CFG4_IGNORE_OWNERSHIP
 
- VXGE_HW_PRC_CFG4_IN_SVC
 
- VXGE_HW_PRC_CFG4_RING_MODE
 
- VXGE_HW_PRC_CFG4_RING_MODE_FIVE_BUFFER
 
- VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER
 
- VXGE_HW_PRC_CFG4_RING_MODE_THREE_BUFFER
 
- VXGE_HW_PRC_CFG4_RTH_DISABLE
 
- VXGE_HW_PRC_CFG4_RXD_NO_SNOOP
 
- VXGE_HW_PRC_CFG4_SIGNAL_BENIGN_OVFLW
 
- VXGE_HW_PRC_CFG5_RXD0_ADD
 
- VXGE_HW_PRC_CFG6_DOORBELL_MODE_EN
 
- VXGE_HW_PRC_CFG6_FRM_PAD_EN
 
- VXGE_HW_PRC_CFG6_GET_RXD_SPAT
 
- VXGE_HW_PRC_CFG6_L3_CPC_TRSFR_CODE_EN
 
- VXGE_HW_PRC_CFG6_L4_CPC_TRSFR_CODE_EN
 
- VXGE_HW_PRC_CFG6_QSIZE_ALIGNED_RXD
 
- VXGE_HW_PRC_CFG6_RXD_CRXDT
 
- VXGE_HW_PRC_CFG6_RXD_SPAT
 
- VXGE_HW_PRC_CFG7_BUFF_SIZE0_MASK
 
- VXGE_HW_PRC_CFG7_NO_HDR_SEPARATION
 
- VXGE_HW_PRC_CFG7_RXD_BUFF_SIZE_MASK
 
- VXGE_HW_PRC_CFG7_RXD_NS_CHG_EN
 
- VXGE_HW_PRC_CFG7_SCATTER_MODE
 
- VXGE_HW_PRC_CFG7_SCATTER_MODE_A
 
- VXGE_HW_PRC_CFG7_SCATTER_MODE_B
 
- VXGE_HW_PRC_CFG7_SCATTER_MODE_C
 
- VXGE_HW_PRC_CFG7_SMART_SCAT_EN
 
- VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT
 
- VXGE_HW_PRC_STATUS1_PRC_VP_QUIESCENT
 
- VXGE_HW_PTM_ALARM_REG_PTM_FRMM_ECC_DB_ERR
 
- VXGE_HW_PTM_ALARM_REG_PTM_FRMM_ECC_SG_ERR
 
- VXGE_HW_PTM_ALARM_REG_PTM_RDCTRL_FIFO_ERR
 
- VXGE_HW_PTM_ALARM_REG_PTM_RDCTRL_SYNC_ERR
 
- VXGE_HW_PTM_ALARM_REG_WDE2MSR_WR_FIFO_ERR
 
- VXGE_HW_PTM_ALARM_REG_XFMD_RD_FIFO_ERR
 
- VXGE_HW_PTM_ECC_CFG_PTM_FRMM_ECC_EN_N
 
- VXGE_HW_PTM_PHASE_CFG_FRMM_RD_PHASE_EN
 
- VXGE_HW_PTM_PHASE_CFG_FRMM_WR_PHASE_EN
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_ARB_FSM_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_ARB_SHADOW_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_CMR_FSM_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_CMR_SHADOW_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_CMW_FSM_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_CMW_SHADOW_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_CP2BDT_DFIFO_PUSH_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_CP2BDT_RFIFO_PUSH_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_PRSP_FIFO_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_REQ_FIFO_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_REQ_FSM_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_REQ_SHADOW_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_RSP_FSM_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_RSP_SHADOW_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_CPT_WRSP_FIFO_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_INV_ADDR_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_INV_ADDR_INFO_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_RD_PROT_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_RD_PROT_INFO_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_WR_PROT_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_CXP_WR_PROT_INFO_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_PRSP_FIFO_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_REQ_FIFO_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_REQ_FSM_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_REQ_SHADOW_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_RSP_FSM_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_RSP_SHADOW_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_MPT_WRSP_FIFO_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_INV_ADDR_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_INV_ADDR_INFO_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_RD_PROT_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_RD_PROT_INFO_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_WR_PROT_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_MXP_WR_PROT_INFO_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_RAM_SHADOW_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_RD_RSP_FIFO_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_REQ_DATA_FIFO_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_REQ_FIFO_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_PRSP_FIFO_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_REQ_FIFO_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_REQ_FSM_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_REQ_SHADOW_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_RSP_FSM_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_RSP_SHADOW_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_UPT_WRSP_FIFO_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_INV_ADDR_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_INV_ADDR_INFO_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_RD_PROT_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_RD_PROT_INFO_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_WR_PROT_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_UXP_WR_PROT_INFO_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_WR_RSP_FIFO_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_XIL_FSM_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_XIL_SHADOW_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_DB_ERR
 
- VXGE_HW_PXTMC_ERR_REG_XTMC_XT_PIF_SRAM_SG_ERR
 
- VXGE_HW_RATEMGMT_ANBE_CFG_PORT_ADVERTISE_10G_KX4
 
- VXGE_HW_RATEMGMT_ANBE_CFG_PORT_ADVERTISE_1G_KX
 
- VXGE_HW_RATEMGMT_ANBE_CFG_PORT_PARALLEL_DETECT_10G_KX4_ENABLE
 
- VXGE_HW_RATEMGMT_ANBE_CFG_PORT_PARALLEL_DETECT_1G_KX_ENABLE
 
- VXGE_HW_RATEMGMT_ANBE_CFG_PORT_RESTART
 
- VXGE_HW_RATEMGMT_ANBE_CFG_PORT_T_DME_EXCHANGE
 
- VXGE_HW_RATEMGMT_ANBE_CFG_PORT_T_SYNC_10G_KX4
 
- VXGE_HW_RATEMGMT_ANBE_CFG_PORT_T_SYNC_1G_KX
 
- VXGE_HW_RATEMGMT_ANTP_CFG_PORT_ADVERTISE_10G
 
- VXGE_HW_RATEMGMT_ANTP_CFG_PORT_ADVERTISE_1G
 
- VXGE_HW_RATEMGMT_ANTP_CFG_PORT_RESTART
 
- VXGE_HW_RATEMGMT_ANTP_CFG_PORT_T_LDOWN_REAUTO_RESPONSE
 
- VXGE_HW_RATEMGMT_ANTP_CFG_PORT_T_RETRY_PHY_QUERY
 
- VXGE_HW_RATEMGMT_ANTP_CFG_PORT_T_WAIT_MDIO_RESPONSE
 
- VXGE_HW_RATEMGMT_ANTP_CFG_PORT_USE_ACT_SEL
 
- VXGE_HW_RATEMGMT_ANTP_CFG_PORT_USE_PREAMBLE_EXT_PHY
 
- VXGE_HW_RATEMGMT_CFG_PORT_ANBE_USE_FSM
 
- VXGE_HW_RATEMGMT_CFG_PORT_ANTP_USE_FSM
 
- VXGE_HW_RATEMGMT_CFG_PORT_FIXED_USE_FSM
 
- VXGE_HW_RATEMGMT_CFG_PORT_MODE
 
- VXGE_HW_RATEMGMT_CFG_PORT_RATE
 
- VXGE_HW_RATEMGMT_FIXED_CFG_PORT_RESTART
 
- VXGE_HW_RATEMGMT_STATUS_PORT_RATEMGMT_COMPLETE
 
- VXGE_HW_RATEMGMT_STATUS_PORT_RATEMGMT_MAC_MATCHES_PHY
 
- VXGE_HW_RATEMGMT_STATUS_PORT_RATEMGMT_RATE
 
- VXGE_HW_RCQ_BYPQ_CFG_BYP_OFF_THRESHOLD
 
- VXGE_HW_RCQ_BYPQ_CFG_BYP_ON_THRESHOLD
 
- VXGE_HW_RCQ_BYPQ_CFG_OVERFLOW_THRESHOLD
 
- VXGE_HW_RC_ALARM_REG_BTC_SM_ERR
 
- VXGE_HW_RC_ALARM_REG_BTC_VPATH_MISMATCH_ERR
 
- VXGE_HW_RC_ALARM_REG_BTDCM_SM_ERR
 
- VXGE_HW_RC_ALARM_REG_BTDRM_SM_ERR
 
- VXGE_HW_RC_ALARM_REG_BTDWM_SM_ERR
 
- VXGE_HW_RC_ALARM_REG_FTC_SM_ERR
 
- VXGE_HW_RC_ALARM_REG_FTC_SM_PHASE_ERR
 
- VXGE_HW_RC_ALARM_REG_RHS_RXD_RHS_ECC_DB_ERR
 
- VXGE_HW_RC_ALARM_REG_RHS_RXD_RHS_ECC_SG_ERR
 
- VXGE_HW_RC_ALARM_REG_RMM_RXD_RC_ECC_DB_ERR
 
- VXGE_HW_RC_ALARM_REG_RMM_RXD_RC_ECC_SG_ERR
 
- VXGE_HW_RC_ALARM_REG_RMM_SM_ERR
 
- VXGE_HW_RC_CFG2_BUFF1_SIZE
 
- VXGE_HW_RC_CFG2_BUFF2_SIZE
 
- VXGE_HW_RC_CFG2_BUFF3_SIZE
 
- VXGE_HW_RC_CFG2_BUFF4_SIZE
 
- VXGE_HW_RC_CFG3_BUFF5_SIZE
 
- VXGE_HW_RDA_ECC_DB_REG_RDA_RXD_ERR
 
- VXGE_HW_RDA_ECC_SG_REG_RDA_RXD_ERR
 
- VXGE_HW_RDA_ERR_REG_RDA_FRM_ECC_DB_ERR
 
- VXGE_HW_RDA_ERR_REG_RDA_IMM_ECC_DB_ERR
 
- VXGE_HW_RDA_ERR_REG_RDA_MISC_ERR
 
- VXGE_HW_RDA_ERR_REG_RDA_PCIX_ERR
 
- VXGE_HW_RDA_ERR_REG_RDA_RXD_ECC_DB_ERR
 
- VXGE_HW_RDA_ERR_REG_RDA_SM0_ERR_ALARM
 
- VXGE_HW_RDA_ERR_REG_RDA_TIM_ECC_DB_ERR
 
- VXGE_HW_RDA_ERR_REG_RDA_UQM_ECC_DB_ERR
 
- VXGE_HW_RDCRDTARB_CFG0_DBLGEN_MAX_OUTSTANDING_RDS
 
- VXGE_HW_RDCRDTARB_CFG0_EN_XON
 
- VXGE_HW_RDCRDTARB_CFG0_MAX_OUTSTANDING_RDS
 
- VXGE_HW_RDCRDTARB_CFG0_PDA_MAX_OUTSTANDING_RDS
 
- VXGE_HW_RDCRDTARB_CFG0_RDA_MAX_OUTSTANDING_RDS
 
- VXGE_HW_RDCRDTARB_CFG0_WAIT_CNT
 
- VXGE_HW_RD_REQ_IN_PROGRESS_VP
 
- VXGE_HW_RD_REQ_OUTSTANDING_VP
 
- VXGE_HW_READ_ARB_PENDING_RDARB_DBLGEN
 
- VXGE_HW_READ_ARB_PENDING_RDARB_RTDMA
 
- VXGE_HW_READ_ARB_PENDING_RDARB_WRDMA
 
- VXGE_HW_REPLICATION_QUEUE_PRIORITY_REPLICATION_QUEUE_PRIORITY
 
- VXGE_HW_REPLICQ_FLUSH_IN_PROGRESS_NOA_VP
 
- VXGE_HW_RESOURCE_ASSIGNMENTS_RESOURCE_ASSIGNMENTS
 
- VXGE_HW_RESOURCE_NO_PFN_OR_VF
 
- VXGE_HW_RING_DEFAULT
 
- VXGE_HW_RING_DISABLE
 
- VXGE_HW_RING_ENABLE
 
- VXGE_HW_RING_MEMBLOCK_IDX_OFFSET
 
- VXGE_HW_RING_NEXT_BLOCK_POINTER_OFFSET
 
- VXGE_HW_RING_RXD_1_BUFFER0_SIZE
 
- VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET
 
- VXGE_HW_RING_RXD_1_BUFFER0_SIZE_MASK
 
- VXGE_HW_RING_RXD_1_RTH_HASH_VAL_GET
 
- VXGE_HW_RING_RXD_BUFFER_MODE_1
 
- VXGE_HW_RING_RXD_BUFFER_MODE_3
 
- VXGE_HW_RING_RXD_BUFFER_MODE_5
 
- VXGE_HW_RING_RXD_BUFFER_MODE_DEFAULT
 
- VXGE_HW_RING_RXD_ETHER_ENCAP_GET
 
- VXGE_HW_RING_RXD_FAST_PATH_ELIGIBLE_GET
 
- VXGE_HW_RING_RXD_FRAME_PROTO_GET
 
- VXGE_HW_RING_RXD_IS_ICMP_GET
 
- VXGE_HW_RING_RXD_IS_VLAN_GET
 
- VXGE_HW_RING_RXD_L3_CKSUM_CORRECT_GET
 
- VXGE_HW_RING_RXD_L3_CKSUM_GET
 
- VXGE_HW_RING_RXD_L4_CKSUM_CORRECT_GET
 
- VXGE_HW_RING_RXD_L4_CKSUM_GET
 
- VXGE_HW_RING_RXD_LIST_OWN_ADAPTER
 
- VXGE_HW_RING_RXD_RTH_BUCKET_GET
 
- VXGE_HW_RING_RXD_RTH_HASH_TYPE_GET
 
- VXGE_HW_RING_RXD_RTH_IT_HIT_GET
 
- VXGE_HW_RING_RXD_RTH_SPDM_HIT_GET
 
- VXGE_HW_RING_RXD_SYN_GET
 
- VXGE_HW_RING_RXD_T_CODE
 
- VXGE_HW_RING_RXD_T_CODE_GET
 
- VXGE_HW_RING_RXD_T_CODE_UNUSED
 
- VXGE_HW_RING_RXD_VLAN_TAG_GET
 
- VXGE_HW_RING_SCATTER_MODE_A
 
- VXGE_HW_RING_SCATTER_MODE_B
 
- VXGE_HW_RING_SCATTER_MODE_C
 
- VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT
 
- VXGE_HW_RING_T_CODE_BENIGN_OVFLOW
 
- VXGE_HW_RING_T_CODE_BUF_SIZE_ERR
 
- VXGE_HW_RING_T_CODE_FRM_DROP
 
- VXGE_HW_RING_T_CODE_INT_ECC_ERR
 
- VXGE_HW_RING_T_CODE_L2_FRM_ERR
 
- VXGE_HW_RING_T_CODE_L3_CKSUM_MISMATCH
 
- VXGE_HW_RING_T_CODE_L3_L4_CKSUM_MISMATCH
 
- VXGE_HW_RING_T_CODE_L3_PKT_ERR
 
- VXGE_HW_RING_T_CODE_L4_CKSUM_MISMATCH
 
- VXGE_HW_RING_T_CODE_MULTI_ERR
 
- VXGE_HW_RING_T_CODE_OK
 
- VXGE_HW_RING_T_CODE_UNUSED
 
- VXGE_HW_RING_T_CODE_ZERO_LEN_BUFF
 
- VXGE_HW_ROCRC_ALARM_REG_NOA_IMMM_ECC_DB
 
- VXGE_HW_ROCRC_ALARM_REG_NOA_IMMM_ECC_SG
 
- VXGE_HW_ROCRC_ALARM_REG_NOA_NMA_SM_ERR
 
- VXGE_HW_ROCRC_ALARM_REG_NOA_RCBM_ECC_DB
 
- VXGE_HW_ROCRC_ALARM_REG_NOA_RCBM_ECC_SG
 
- VXGE_HW_ROCRC_ALARM_REG_NOA_WCT_CMD_FIFO_ERR
 
- VXGE_HW_ROCRC_ALARM_REG_QCQ_LOST_EGB_ERR
 
- VXGE_HW_ROCRC_ALARM_REG_QCQ_MULTI_BYP_OWN_ERR
 
- VXGE_HW_ROCRC_ALARM_REG_QCQ_MULTI_EGB_OWN_ERR
 
- VXGE_HW_ROCRC_ALARM_REG_QCQ_MULTI_EGB_RSVD_ERR
 
- VXGE_HW_ROCRC_ALARM_REG_QCQ_OWN_NOT_ASSIGNED_ERR
 
- VXGE_HW_ROCRC_ALARM_REG_QCQ_OWN_RSVD_SYNC_ERR
 
- VXGE_HW_ROCRC_ALARM_REG_QCQ_QCC_BYP_ECC_DB
 
- VXGE_HW_ROCRC_ALARM_REG_QCQ_QCC_BYP_ECC_SG
 
- VXGE_HW_ROCRC_ALARM_REG_RCQ_BYPQ0_OVERFLOW
 
- VXGE_HW_ROCRC_ALARM_REG_RCQ_BYPQ1_OVERFLOW
 
- VXGE_HW_ROCRC_ALARM_REG_RCQ_BYPQ2_OVERFLOW
 
- VXGE_HW_ROCRC_ALARM_REG_UDQ_UMQM_ECC_DB
 
- VXGE_HW_ROCRC_ALARM_REG_UDQ_UMQM_ECC_SG
 
- VXGE_HW_RPE_LRO_CFG_ALLOW_LRO_LLC_LLCJUMBO_MRG
 
- VXGE_HW_RPE_LRO_CFG_ALLOW_LRO_SNAP_SNAPJUMBO_MRG
 
- VXGE_HW_RPE_LRO_CFG_INCL_ACK_CNT_IN_CQE
 
- VXGE_HW_RPE_LRO_CFG_SUPPRESS_LRO_ETH_TRLR
 
- VXGE_HW_RPE_PCI_CFG_NOSNOOP_CQRQ_IR
 
- VXGE_HW_RPE_PCI_CFG_NOSNOOP_CQRR_IR
 
- VXGE_HW_RPE_PCI_CFG_NOSNOOP_CQSQ_IR
 
- VXGE_HW_RPE_PCI_CFG_NOSNOOP_DATA
 
- VXGE_HW_RPE_PCI_CFG_NOSNOOP_LL_CQE
 
- VXGE_HW_RPE_PCI_CFG_NOSNOOP_NONLL_CQE
 
- VXGE_HW_RPE_PCI_CFG_PAD_BASE_LL_CQE_ENABLE
 
- VXGE_HW_RPE_PCI_CFG_PAD_CQRQ_IR_ENABLE
 
- VXGE_HW_RPE_PCI_CFG_PAD_CQRR_IR_ENABLE
 
- VXGE_HW_RPE_PCI_CFG_PAD_CQSQ_IR_ENABLE
 
- VXGE_HW_RPE_PCI_CFG_PAD_LL_CQE_IDATA_ENABLE
 
- VXGE_HW_RPE_PCI_CFG_PAD_LRO_CQE_ENABLE
 
- VXGE_HW_RPE_PCI_CFG_PAD_LRO_DATA_ENABLE
 
- VXGE_HW_RPE_PCI_CFG_PAD_LRO_HDR_ENABLE
 
- VXGE_HW_RPE_PCI_CFG_PAD_NONLL_CQE_ENABLE
 
- VXGE_HW_RPE_PCI_CFG_RELAXED_CQRQ_IR
 
- VXGE_HW_RPE_PCI_CFG_RELAXED_CQRR_IR
 
- VXGE_HW_RPE_PCI_CFG_RELAXED_CQSQ_IR
 
- VXGE_HW_RPE_PCI_CFG_RELAXED_DATA
 
- VXGE_HW_RPE_PCI_CFG_RELAXED_LL_CQE
 
- VXGE_HW_RPE_PCI_CFG_RELAXED_NONLL_CQE
 
- VXGE_HW_RQA_ERR_REG_RQA_SM_ERR_ALARM
 
- VXGE_HW_RQA_PRTY_FOR_VP_RQA_PRTY_FOR_VP
 
- VXGE_HW_RQA_TOP_PRTY_FOR_VH_RQA_TOP_PRTY_FOR_VH
 
- VXGE_HW_RQA_TOP_PRTY_FOR_VP_RQA_TOP_PRTY_FOR_VP
 
- VXGE_HW_RQA_VPBP_CTRL_ROCRC_DIS
 
- VXGE_HW_RQA_VPBP_CTRL_TXPE_DIS
 
- VXGE_HW_RQA_VPBP_CTRL_WR_XON_DIS
 
- VXGE_HW_RSTHDLR_STATUS_RSTHDLR_CURRENT_RESET
 
- VXGE_HW_RSTHDLR_STATUS_RSTHDLR_CURRENT_VPIN
 
- VXGE_HW_RTDMA_BW_CTRL_BW_CTRL_EN
 
- VXGE_HW_RTDMA_BW_CTRL_DESIRED_BW
 
- VXGE_HW_RTDMA_BW_TIMER_TIMER_CTRL
 
- VXGE_HW_RTDMA_INT_STATUS_LSO_ERROR_LSO_INT
 
- VXGE_HW_RTDMA_INT_STATUS_PCC_ERROR_PCC_INT
 
- VXGE_HW_RTDMA_INT_STATUS_PDA_ALARM_PDA_INT
 
- VXGE_HW_RTDMA_INT_STATUS_SM_ERROR_SM_INT
 
- VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY
 
- VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN
 
- VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH
 
- VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE
 
- VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_GEN_INT_AFTER_ABORT
 
- VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_PAD_MODE
 
- VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_PAD_PATTERN
 
- VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_ADDR_BDRY
 
- VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_ADDR_BDRY_EN
 
- VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_FILL_THRESH
 
- VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_PYLD_WMARK
 
- VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_PYLD_WMARK_EN
 
- VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_TXD_WAIT_FOR_SPACE
 
- VXGE_HW_RTH_DEFAULT
 
- VXGE_HW_RTH_DISABLE
 
- VXGE_HW_RTH_ENABLE
 
- VXGE_HW_RTH_IT_TYPE_DEFAULT
 
- VXGE_HW_RTH_IT_TYPE_MULTI_IT
 
- VXGE_HW_RTH_IT_TYPE_SOLO_IT
 
- VXGE_HW_RTI_INT_MASK_RTI_INT_MASK
 
- VXGE_HW_RTI_INT_STATUS_RTI_INT_STATUS
 
- VXGE_HW_RTS_ACCESS_ICMP_EN
 
- VXGE_HW_RTS_ACCESS_IPFRAG_EN
 
- VXGE_HW_RTS_ACCESS_L4PRTCL_FLEX_EN
 
- VXGE_HW_RTS_ACCESS_L4PRTCL_TCP_EN
 
- VXGE_HW_RTS_ACCESS_L4PRTCL_UDP_EN
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_ALL_CLEAR
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_BEHAV_TBL_SEL
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DS
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_ETYPE
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_PN
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_QOS
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_JHASH_CFG
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_GET_ACTION
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE
 
- VXGE_HW_RTS_ACCESS_STEER_CTRL_TABLE_SEL
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_DATA
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_DS_ENTRY_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_ETYPE
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_BUILD
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_DAY
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_MAJOR
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_MINOR
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_MONTH
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_FW_VER_YEAR
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DS_ENTRY_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_ETYPE
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_PORT_NUM
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_SRC_DEST_SEL
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_PN_TCP_UDP_SEL
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_QOS_ENTRY_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ALG_SEL
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_BUCKET_SIZE
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_REPL_ENTRY_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV4_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_IPV6_EX_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV4_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_RTH_TCP_IPV6_EX_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_DATA
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_BUCKET_NUM
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM0_ENTRY_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_DATA
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_BUCKET_NUM
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_ITEM1_ENTRY_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_GOLDEN_RATIO
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_JHASH_CFG_INIT_VALUE
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_KEY_KEY
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_DA_MASK
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV4_SA_MASK
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_DA_MASK
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_IPV6_SA_MASK
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4DP_MASK
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_MASK_L4SP_MASK
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_BUCKET_DATA
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_SOLO_IT_ENTRY_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_VLAN_ID
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_LED_CONTROL_OFF
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_LED_CONTROL_ON
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_1
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_2
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PCI_MODE
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_VERSION
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_PN_PORT_NUM
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_PN_SRC_DEST_SEL
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_PN_TCP_UDP_SEL
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_QOS_ENTRY_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_CRC32C
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_JENKINS
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL_MS_RSS
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_REPL_ENTRY_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV4_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EX_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EX_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_ENTRY_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_ENTRY_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_GOLDEN_RATIO
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_JHASH_CFG_INIT_VALUE
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_KEY_KEY
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_DA_MASK
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV4_SA_MASK
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_DA_MASK
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_IPV6_SA_MASK
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4DP_MASK
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_MASK_L4SP_MASK
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_ENTRY_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA0_VLAN_ID
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_DATA
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MODE
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_BUILD
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_DAY
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_MAJOR
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_MINOR
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_MONTH
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_YEAR
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_DATA
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_BUCKET_NUM
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM0_ENTRY_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_DATA
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_BUCKET_NUM
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM1_ENTRY_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_DATA
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_BUCKET_NUM
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM4_ENTRY_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_DATA
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_BUCKET_NUM
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM5_ENTRY_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_DATA
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_BUCKET_NUM
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM6_ENTRY_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_DATA
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_BUCKET_NUM
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_RTH_ITEM7_ENTRY_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_ENTRY_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_ENTRY_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_BUCKET_DATA
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_BUCKET_NUM
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM4_ENTRY_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_BUCKET_DATA
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_BUCKET_NUM
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM5_ENTRY_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_BUCKET_DATA
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_BUCKET_NUM
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM6_ENTRY_EN
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_BUCKET_DATA
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_BUCKET_NUM
 
- VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM7_ENTRY_EN
 
- VXGE_HW_RTS_ACCESS_STEER_ROM_IMAGE_INDEX
 
- VXGE_HW_RTS_ACCESS_TCPSYN_EN
 
- VXGE_HW_RTS_ACCESS_ZL4PYLD_EN
 
- VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT
 
- VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT
 
- VXGE_HW_RTS_MAC_DEFAULT
 
- VXGE_HW_RTS_MAC_DISABLE
 
- VXGE_HW_RTS_MAC_ENABLE
 
- VXGE_HW_RTS_MGR_CFG0_FLEX_L4PRTCL_VALUE
 
- VXGE_HW_RTS_MGR_CFG0_ICMP_TRASH
 
- VXGE_HW_RTS_MGR_CFG0_IPFRAG_TRASH
 
- VXGE_HW_RTS_MGR_CFG0_L4PRTCL_FLEX_TRASH
 
- VXGE_HW_RTS_MGR_CFG0_L4PRTCL_TCP_TRASH
 
- VXGE_HW_RTS_MGR_CFG0_L4PRTCL_UDP_TRASH
 
- VXGE_HW_RTS_MGR_CFG0_RTS_DP_SP_PRIORITY
 
- VXGE_HW_RTS_MGR_CFG0_TCPSYN_TRASH
 
- VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_FLEX_L4PRTCL_VALUE
 
- VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_ICMP_TRASH
 
- VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_IPFRAG_TRASH
 
- VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_L4PRTCL_FLEX_TRASH
 
- VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_L4PRTCL_TCP_TRASH
 
- VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_L4PRTCL_UDP_TRASH
 
- VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_RTS_DP_SP_PRIORITY
 
- VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_TCPSYN_TRASH
 
- VXGE_HW_RTS_MGR_CFG0_VPMGMT_CLONE_ZL4PYLD_TRASH
 
- VXGE_HW_RTS_MGR_CFG0_ZL4PYLD_TRASH
 
- VXGE_HW_RTS_MGR_CFG1_DA_ACTIVE_TABLE
 
- VXGE_HW_RTS_MGR_CFG1_PN_ACTIVE_TABLE
 
- VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_DS
 
- VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_ETYPE
 
- VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_ICMP_TCPSYN
 
- VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_L4PN
 
- VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_L4PRTCL
 
- VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_QOS
 
- VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_RANGE_L4PN
 
- VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_RTH_IT
 
- VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_DS
 
- VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ETYPE
 
- VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ICMP_TCPSYN
 
- VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_L4PN
 
- VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_L4PRTCL
 
- VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_QOS
 
- VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_RANGE_L4PN
 
- VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_RTH_IT
 
- VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_VPMGMT_CLONE_ZL4PYLD
 
- VXGE_HW_RTS_MGR_CRITERIA_PRIORITY_ZL4PYLD
 
- VXGE_HW_RTS_MGR_DA_PAUSE_CFG_VPATH_VECTOR
 
- VXGE_HW_RTS_MGR_DA_SLOW_PROTO_CFG_VPATH_VECTOR
 
- VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_DA
 
- VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_DS
 
- VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_ETYPE
 
- VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_FW_VERSION
 
- VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_PN
 
- VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_QOS
 
- VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RANGE_PN
 
- VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG
 
- VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_JHASH_CFG
 
- VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY
 
- VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK
 
- VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT
 
- VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT
 
- VXGE_HW_RTS_MGR_STEER_CTRL_DATA_STRUCT_SEL_VID
 
- VXGE_HW_RTS_MGR_STEER_CTRL_WE_READ
 
- VXGE_HW_RTS_MGR_STEER_CTRL_WE_WRITE
 
- VXGE_HW_RTS_MGR_STEER_DATA0_DA_MAC_ADDR
 
- VXGE_HW_RTS_MGR_STEER_DATA0_GET_DA_MAC_ADDR
 
- VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_ADD_PRIVILEGED_MODE
 
- VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_ADD_VPATH
 
- VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MASK
 
- VXGE_HW_RTS_MGR_STEER_DATA1_DA_MAC_ADDR_MODE
 
- VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_MODE
 
- VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_ADD_VPATH
 
- VXGE_HW_RTS_MGR_STEER_DATA1_GET_DA_MAC_ADDR_MASK
 
- VXGE_HW_RXDCM_RESET_IN_PROGRESS_PRC_VP
 
- VXGE_HW_RXDCM_SM_ERR_REG_PRC_VP
 
- VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE
 
- VXGE_HW_RXDM_DBG_RD_ADDR
 
- VXGE_HW_RXDM_DBG_RD_DATA_RMC_RXDM_DBG_RD_DATA
 
- VXGE_HW_RXDM_DBG_RD_ENABLE
 
- VXGE_HW_RXDRM_SM_ERR_REG_PRC_VP
 
- VXGE_HW_RXDWM_SM_ERR_REG_PRC_VP
 
- VXGE_HW_RXD_RETURNED_GET_RXD_RETURNED
 
- VXGE_HW_RXD_RETURNED_RXD_RETURNED
 
- VXGE_HW_RXD_STATE_AVAIL
 
- VXGE_HW_RXD_STATE_FREED
 
- VXGE_HW_RXD_STATE_NONE
 
- VXGE_HW_RXD_STATE_POSTED
 
- VXGE_HW_RXMAC_AUTHORIZE_ALL_ADDR_VP
 
- VXGE_HW_RXMAC_AUTHORIZE_ALL_VID_VP
 
- VXGE_HW_RXMAC_CFG0_PORT_DISCARD_PFRM
 
- VXGE_HW_RXMAC_CFG0_PORT_IGNORE_FCS_ERR
 
- VXGE_HW_RXMAC_CFG0_PORT_IGNORE_LEN_MISMATCH
 
- VXGE_HW_RXMAC_CFG0_PORT_IGNORE_LONG_ERR
 
- VXGE_HW_RXMAC_CFG0_PORT_IGNORE_USIZED_ERR
 
- VXGE_HW_RXMAC_CFG0_PORT_MAX_PYLD_LEN
 
- VXGE_HW_RXMAC_CFG0_PORT_RMAC_EN
 
- VXGE_HW_RXMAC_CFG0_PORT_STRIP_FCS
 
- VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_DISCARD_PFRM
 
- VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN
 
- VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_FCS_ERR
 
- VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_LEN_MISMATCH
 
- VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_LONG_ERR
 
- VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_IGNORE_USIZED_ERR
 
- VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_MAX_PYLD_LEN
 
- VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_RMAC_EN
 
- VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_STRIP_FCS
 
- VXGE_HW_RXMAC_CFG2_PORT_PROM_EN
 
- VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_DB_ERR
 
- VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT0_RMAC_RTS_PART_SG_ERR
 
- VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_DB_ERR
 
- VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT1_RMAC_RTS_PART_SG_ERR
 
- VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_DB_ERR
 
- VXGE_HW_RXMAC_ECC_ERR_REG_RMAC_PORT2_RMAC_RTS_PART_SG_ERR
 
- VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_DB_ERR
 
- VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT0_SG_ERR
 
- VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_DB_ERR
 
- VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DA_LKP_PRT1_SG_ERR
 
- VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DS_LKP_DB_ERR
 
- VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_DS_LKP_SG_ERR
 
- VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT0_DB_ERR
 
- VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT0_SG_ERR
 
- VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT1_DB_ERR
 
- VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT1_SG_ERR
 
- VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT2_DB_ERR
 
- VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_PN_LKP_PRT2_SG_ERR
 
- VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_DB_ERR
 
- VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_LKP_SG_ERR
 
- VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_DB_ERR
 
- VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_RTH_MASK_SG_ERR
 
- VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_VID_LKP_DB_ERR
 
- VXGE_HW_RXMAC_ECC_ERR_REG_RTSJ_RMAC_VID_LKP_SG_ERR
 
- VXGE_HW_RXMAC_GEN_CFG_SCALE_RMAC_UTIL
 
- VXGE_HW_RXMAC_INT_STATUS_RXMAC_ECC_ERR_RXMAC_ECC_INT
 
- VXGE_HW_RXMAC_INT_STATUS_RXMAC_GEN_ERR_RXMAC_GEN_INT
 
- VXGE_HW_RXMAC_INT_STATUS_RXMAC_VARIOUS_ERR_RXMAC_VARIOUS_INT
 
- VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_PKT_WEIGHT
 
- VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_FRAC_UTIL
 
- VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_SCALE_FACTOR
 
- VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_RMAC_UTILIZATION
 
- VXGE_HW_RXMAC_LINK_UTIL_PORT_RMAC_UTIL_CFG
 
- VXGE_HW_RXMAC_PAUSE_CFG_PORT_ACCEL_SEND
 
- VXGE_HW_RXMAC_PAUSE_CFG_PORT_DUAL_THR
 
- VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN
 
- VXGE_HW_RXMAC_PAUSE_CFG_PORT_HIGH_PTIME
 
- VXGE_HW_RXMAC_PAUSE_CFG_PORT_IGNORE_PF_FCS_ERR
 
- VXGE_HW_RXMAC_PAUSE_CFG_PORT_IGNORE_PF_LEN_ERR
 
- VXGE_HW_RXMAC_PAUSE_CFG_PORT_LIMITER_EN
 
- VXGE_HW_RXMAC_PAUSE_CFG_PORT_MAX_LIMIT
 
- VXGE_HW_RXMAC_PAUSE_CFG_PORT_PERMIT_RATEMGMT_CTRL
 
- VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN
 
- VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_ACCEL_SEND
 
- VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_DUAL_THR
 
- VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_GEN_EN
 
- VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_HIGH_PTIME
 
- VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_IGNORE_PF_FCS_ERR
 
- VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_IGNORE_PF_LEN_ERR
 
- VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_LIMITER_EN
 
- VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_MAX_LIMIT
 
- VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_PERMIT_RATEMGMT_CTRL
 
- VXGE_HW_RXMAC_PAUSE_CFG_PORT_VPMGMT_CLONE_RCV_EN
 
- VXGE_HW_RXMAC_RED_CFG0_PORT_RED_EN_VP
 
- VXGE_HW_RXMAC_RED_CFG1_PORT_FINE_EN
 
- VXGE_HW_RXMAC_RED_CFG1_PORT_RED_EN_REPL_QUEUE
 
- VXGE_HW_RXMAC_RED_CFG2_PORT_TRICKLE_EN_VP
 
- VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR0
 
- VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR1
 
- VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR2
 
- VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_CRATE_THR3
 
- VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR0
 
- VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR1
 
- VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR2
 
- VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_FRATE_THR3
 
- VXGE_HW_RXMAC_RED_RATE_REPL_QUEUE_TRICKLE_EN
 
- VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR0
 
- VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR1
 
- VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR2
 
- VXGE_HW_RXMAC_RED_RATE_VP_CRATE_THR3
 
- VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR0
 
- VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR1
 
- VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR2
 
- VXGE_HW_RXMAC_RED_RATE_VP_FRATE_THR3
 
- VXGE_HW_RXMAC_RX_PA_CFG0_IGNORE_FRAME_ERR
 
- VXGE_HW_RXMAC_RX_PA_CFG0_IPV6_STOP_SEARCHING
 
- VXGE_HW_RXMAC_RX_PA_CFG0_JUMBO_SNAP_EN
 
- VXGE_HW_RXMAC_RX_PA_CFG0_NO_PS_IF_UNKNOWN
 
- VXGE_HW_RXMAC_RX_PA_CFG0_SEARCH_FOR_ETYPE
 
- VXGE_HW_RXMAC_RX_PA_CFG0_SEARCH_FOR_HAO
 
- VXGE_HW_RXMAC_RX_PA_CFG0_SUPPORT_MOBILE_IPV6_HDRS
 
- VXGE_HW_RXMAC_RX_PA_CFG0_SUPPORT_SNAP_AB_N
 
- VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_L3_CSUM_ERR
 
- VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_L4_CSUM_ERR
 
- VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_ANY_FRM_IF_RPA_ERR
 
- VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_L3_CSUM_ERR
 
- VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_L4_CSUM_ERR
 
- VXGE_HW_RXMAC_RX_PA_CFG0_TOSS_OFFLD_FRM_IF_RPA_ERR
 
- VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_IGNORE_FRAME_ERR
 
- VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_IPV6_STOP_SEARCHING
 
- VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_JUMBO_SNAP_EN
 
- VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_NO_PS_IF_UNKNOWN
 
- VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SEARCH_FOR_ETYPE
 
- VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SEARCH_FOR_HAO
 
- VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SUPPORT_MOBILE_IPV6_HDRS
 
- VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_SUPPORT_SNAP_AB_N
 
- VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_ANY_FRM_IF_L3_CSUM_ERR
 
- VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_ANY_FRM_IF_L4_CSUM_ERR
 
- VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_ANY_FRM_IF_RPA_ERR
 
- VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_OFFLD_FRM_IF_L3_CSUM_ERR
 
- VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_OFFLD_FRM_IF_L4_CSUM_ERR
 
- VXGE_HW_RXMAC_RX_PA_CFG0_VPMGMT_CLONE_TOSS_OFFLD_FRM_IF_RPA_ERR
 
- VXGE_HW_RXMAC_RX_PA_CFG1_REPL_IPV4_TCP_INCL_PH
 
- VXGE_HW_RXMAC_RX_PA_CFG1_REPL_IPV4_UDP_INCL_PH
 
- VXGE_HW_RXMAC_RX_PA_CFG1_REPL_IPV6_TCP_INCL_PH
 
- VXGE_HW_RXMAC_RX_PA_CFG1_REPL_IPV6_UDP_INCL_PH
 
- VXGE_HW_RXMAC_RX_PA_CFG1_REPL_L4_INCL_CF
 
- VXGE_HW_RXMAC_RX_PA_CFG1_REPL_STRIP_VLAN_TAG
 
- VXGE_HW_RXMAC_STATUS_PORT_RMAC_RX_FRM_RCVD
 
- VXGE_HW_RXMAC_VARIOUS_ERR_REG_RMACJ_RMACJ_FSM_ERR
 
- VXGE_HW_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT0_FSM_ERR
 
- VXGE_HW_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT1_FSM_ERR
 
- VXGE_HW_RXMAC_VARIOUS_ERR_REG_RMAC_RMAC_PORT2_FSM_ERR
 
- VXGE_HW_RXMAC_VCFG0_ALL_VID_EN
 
- VXGE_HW_RXMAC_VCFG0_BCAST_EN
 
- VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN
 
- VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN
 
- VXGE_HW_RXMAC_VCFG0_RTS_MIN_FRM_LEN
 
- VXGE_HW_RXMAC_VCFG0_RTS_USE_MIN_LEN
 
- VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN
 
- VXGE_HW_RXMAC_VCFG1_CONTRIB_L2_FLOW
 
- VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE
 
- VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE
 
- VXGE_HW_RXPE_CMDS_RESET_IN_PROGRESS_NOA_VP
 
- VXGE_HW_RXSYNC_FREQ_CNT
 
- VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_FAU_RX_FRAC_UTIL
 
- VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_FAU_RX_UTILIZATION
 
- VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_RX_PKT_WEIGHT
 
- VXGE_HW_RX_DATAPATH_UTIL_VP_CLONE_RX_UTIL_CFG
 
- VXGE_HW_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED
 
- VXGE_HW_RX_FRM_TRANSFERRED_RX_FRM_TRANSFERRED
 
- VXGE_HW_RX_MULTI_CAST_CTRL1_DELAY_COUNT
 
- VXGE_HW_RX_MULTI_CAST_CTRL1_ENABLE
 
- VXGE_HW_RX_MULTI_CAST_CTRL_FRM_DROP_DIS
 
- VXGE_HW_RX_MULTI_CAST_CTRL_NO_RXD_TIME_OUT_CNT
 
- VXGE_HW_RX_MULTI_CAST_CTRL_TIME_OUT_CNT
 
- VXGE_HW_RX_MULTI_CAST_CTRL_TIME_OUT_DIS
 
- VXGE_HW_RX_MULTI_CAST_STATS_FRAME_DISCARD
 
- VXGE_HW_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD
 
- VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_0
 
- VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_1
 
- VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_2
 
- VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_3
 
- VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_4
 
- VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_5
 
- VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_6
 
- VXGE_HW_RX_QUEUE_PRIORITY_0_RX_Q_NUMBER_7
 
- VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_10
 
- VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_11
 
- VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_12
 
- VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_13
 
- VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_14
 
- VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_15
 
- VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_8
 
- VXGE_HW_RX_QUEUE_PRIORITY_1_RX_Q_NUMBER_9
 
- VXGE_HW_RX_QUEUE_PRIORITY_2_RX_Q_NUMBER_16
 
- VXGE_HW_RX_QUEUE_SELECT_ENABLE_CODE
 
- VXGE_HW_RX_QUEUE_SELECT_ENABLE_HIERARCHICAL_PRTY
 
- VXGE_HW_RX_QUEUE_SELECT_NUMBER
 
- VXGE_HW_RX_THRESH_CFG_REPL_EXACT_VP_MATCH_REQ
 
- VXGE_HW_RX_THRESH_CFG_REPL_GLOBAL_WOL_EN
 
- VXGE_HW_RX_THRESH_CFG_REPL_PAUSE_HIGH_THR
 
- VXGE_HW_RX_THRESH_CFG_REPL_PAUSE_LOW_THR
 
- VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_0
 
- VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_1
 
- VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_2
 
- VXGE_HW_RX_THRESH_CFG_REPL_RED_THR_3
 
- VXGE_HW_RX_THRESH_CFG_VP_PAUSE_HIGH_THR
 
- VXGE_HW_RX_THRESH_CFG_VP_PAUSE_LOW_THR
 
- VXGE_HW_RX_THRESH_CFG_VP_RED_THR_0
 
- VXGE_HW_RX_THRESH_CFG_VP_RED_THR_1
 
- VXGE_HW_RX_THRESH_CFG_VP_RED_THR_2
 
- VXGE_HW_RX_THRESH_CFG_VP_RED_THR_3
 
- VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_0
 
- VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_1
 
- VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_2
 
- VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_3
 
- VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_4
 
- VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_5
 
- VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_6
 
- VXGE_HW_RX_W_ROUND_ROBIN_0_RX_W_PRIORITY_SS_7
 
- VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_80
 
- VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_81
 
- VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_82
 
- VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_83
 
- VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_84
 
- VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_85
 
- VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_86
 
- VXGE_HW_RX_W_ROUND_ROBIN_10_RX_W_PRIORITY_SS_87
 
- VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_88
 
- VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_89
 
- VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_90
 
- VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_91
 
- VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_92
 
- VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_93
 
- VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_94
 
- VXGE_HW_RX_W_ROUND_ROBIN_11_RX_W_PRIORITY_SS_95
 
- VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_100
 
- VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_101
 
- VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_102
 
- VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_103
 
- VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_96
 
- VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_97
 
- VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_98
 
- VXGE_HW_RX_W_ROUND_ROBIN_12_RX_W_PRIORITY_SS_99
 
- VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_104
 
- VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_105
 
- VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_106
 
- VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_107
 
- VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_108
 
- VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_109
 
- VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_110
 
- VXGE_HW_RX_W_ROUND_ROBIN_13_RX_W_PRIORITY_SS_111
 
- VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_112
 
- VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_113
 
- VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_114
 
- VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_115
 
- VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_116
 
- VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_117
 
- VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_118
 
- VXGE_HW_RX_W_ROUND_ROBIN_14_RX_W_PRIORITY_SS_119
 
- VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_120
 
- VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_121
 
- VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_122
 
- VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_123
 
- VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_124
 
- VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_125
 
- VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_126
 
- VXGE_HW_RX_W_ROUND_ROBIN_15_RX_W_PRIORITY_SS_127
 
- VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_128
 
- VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_129
 
- VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_130
 
- VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_131
 
- VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_132
 
- VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_133
 
- VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_134
 
- VXGE_HW_RX_W_ROUND_ROBIN_16_RX_W_PRIORITY_SS_135
 
- VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_136
 
- VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_137
 
- VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_138
 
- VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_139
 
- VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_140
 
- VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_141
 
- VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_142
 
- VXGE_HW_RX_W_ROUND_ROBIN_17_RX_W_PRIORITY_SS_143
 
- VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_144
 
- VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_145
 
- VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_146
 
- VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_147
 
- VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_148
 
- VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_149
 
- VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_150
 
- VXGE_HW_RX_W_ROUND_ROBIN_18_RX_W_PRIORITY_SS_151
 
- VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_152
 
- VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_153
 
- VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_154
 
- VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_155
 
- VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_156
 
- VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_157
 
- VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_158
 
- VXGE_HW_RX_W_ROUND_ROBIN_19_RX_W_PRIORITY_SS_159
 
- VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_10
 
- VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_11
 
- VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_12
 
- VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_13
 
- VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_14
 
- VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_15
 
- VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_8
 
- VXGE_HW_RX_W_ROUND_ROBIN_1_RX_W_PRIORITY_SS_9
 
- VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_160
 
- VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_161
 
- VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_162
 
- VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_163
 
- VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_164
 
- VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_165
 
- VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_166
 
- VXGE_HW_RX_W_ROUND_ROBIN_20_RX_W_PRIORITY_SS_167
 
- VXGE_HW_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_168
 
- VXGE_HW_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_169
 
- VXGE_HW_RX_W_ROUND_ROBIN_21_RX_W_PRIORITY_SS_170
 
- VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_16
 
- VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_17
 
- VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_18
 
- VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_19
 
- VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_20
 
- VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_21
 
- VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_22
 
- VXGE_HW_RX_W_ROUND_ROBIN_2_RX_W_PRIORITY_SS_23
 
- VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_24
 
- VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_25
 
- VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_26
 
- VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_27
 
- VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_28
 
- VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_29
 
- VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_30
 
- VXGE_HW_RX_W_ROUND_ROBIN_3_RX_W_PRIORITY_SS_31
 
- VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_32
 
- VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_33
 
- VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_34
 
- VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_35
 
- VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_36
 
- VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_37
 
- VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_38
 
- VXGE_HW_RX_W_ROUND_ROBIN_4_RX_W_PRIORITY_SS_39
 
- VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_40
 
- VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_41
 
- VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_42
 
- VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_43
 
- VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_44
 
- VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_45
 
- VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_46
 
- VXGE_HW_RX_W_ROUND_ROBIN_5_RX_W_PRIORITY_SS_47
 
- VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_48
 
- VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_49
 
- VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_50
 
- VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_51
 
- VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_52
 
- VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_53
 
- VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_54
 
- VXGE_HW_RX_W_ROUND_ROBIN_6_RX_W_PRIORITY_SS_55
 
- VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_56
 
- VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_57
 
- VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_58
 
- VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_59
 
- VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_60
 
- VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_61
 
- VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_62
 
- VXGE_HW_RX_W_ROUND_ROBIN_7_RX_W_PRIORITY_SS_63
 
- VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_64
 
- VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_65
 
- VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_66
 
- VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_67
 
- VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_68
 
- VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_69
 
- VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_70
 
- VXGE_HW_RX_W_ROUND_ROBIN_8_RX_W_PRIORITY_SS_71
 
- VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_72
 
- VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_73
 
- VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_74
 
- VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_75
 
- VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_76
 
- VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_77
 
- VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_78
 
- VXGE_HW_RX_W_ROUND_ROBIN_9_RX_W_PRIORITY_SS_79
 
- VXGE_HW_SBECC_ERR_REG_PCI_NP_DATA_SG_ERR
 
- VXGE_HW_SBECC_ERR_REG_PCI_NP_HDR_SG_ERR
 
- VXGE_HW_SBECC_ERR_REG_PCI_P_DATA_SG_ERR
 
- VXGE_HW_SBECC_ERR_REG_PCI_P_HDR_SG_ERR
 
- VXGE_HW_SBECC_ERR_REG_PCI_RETRY_BUF_SG_ERR
 
- VXGE_HW_SBECC_ERR_REG_PCI_RETRY_SOT_SG_ERR
 
- VXGE_HW_SET_LEVEL
 
- VXGE_HW_SET_MSIX_MASK_ALL_VECT_SET_MSIX_MASK_ALL_VECT
 
- VXGE_HW_SET_MSIX_MASK_VECT_SET_MSIX_MASK_VECT
 
- VXGE_HW_SGRP_AOA_AND_RESULT_PET_SGRP_AOA_AND_RESULT
 
- VXGE_HW_SGRP_ASSIGN_SGRP_ASSIGN
 
- VXGE_HW_SM_ERROR_REG_SM_FSM_ERR_ALARM
 
- VXGE_HW_SRPCIM_CLEAR_MSIX_MASK_SRPCIM_CLEAR_MSIX_MASK
 
- VXGE_HW_SRPCIM_CLR_MSIX_ONE_SHOT_SRPCIM_CLR_MSIX_ONE_SHOT
 
- VXGE_HW_SRPCIM_GENERAL_CFG1_BOOT_BIT_FLIPEN
 
- VXGE_HW_SRPCIM_GENERAL_CFG1_BOOT_BYTE_SWAPEN
 
- VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_ADDR_FLIPEN
 
- VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_ADDR_SWAPEN
 
- VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_DATA_FLIPEN
 
- VXGE_HW_SRPCIM_GENERAL_CFG1_MSIX_DATA_SWAPEN
 
- VXGE_HW_SRPCIM_GENERAL_INT_MASK_PCI_INT
 
- VXGE_HW_SRPCIM_GENERAL_INT_MASK_PIC_INT
 
- VXGE_HW_SRPCIM_GENERAL_INT_MASK_XMAC_INT
 
- VXGE_HW_SRPCIM_GENERAL_INT_STATUS_PCI_INT
 
- VXGE_HW_SRPCIM_GENERAL_INT_STATUS_PIC_INT
 
- VXGE_HW_SRPCIM_GENERAL_INT_STATUS_XMAC_INT
 
- VXGE_HW_SRPCIM_GEN_ERRORS_REG_INI_SERR_DET
 
- VXGE_HW_SRPCIM_GEN_ERRORS_REG_INTCTRL_SCHED_INT
 
- VXGE_HW_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_COR_ERR
 
- VXGE_HW_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_STATUS_ERR
 
- VXGE_HW_SRPCIM_GEN_ERRORS_REG_PCICONFIG_PF_UNCOR_ERR
 
- VXGE_HW_SRPCIM_GEN_ERRORS_REG_TGT_PF_ILLEGAL_ACCESS
 
- VXGE_HW_SRPCIM_INTERRUPT_CFG1_ALARM_MAP_TO_MSG
 
- VXGE_HW_SRPCIM_INTERRUPT_CFG1_TRAFFIC_CLASS
 
- VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE0_RMSG_INT
 
- VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE10_RMSG_INT
 
- VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE11_RMSG_INT
 
- VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE12_RMSG_INT
 
- VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE13_RMSG_INT
 
- VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE14_RMSG_INT
 
- VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE15_RMSG_INT
 
- VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE16_RMSG_INT
 
- VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE1_RMSG_INT
 
- VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE2_RMSG_INT
 
- VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE3_RMSG_INT
 
- VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE4_RMSG_INT
 
- VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE5_RMSG_INT
 
- VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE6_RMSG_INT
 
- VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE7_RMSG_INT
 
- VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE8_RMSG_INT
 
- VXGE_HW_SRPCIM_MSG_REG_SWIF_SRPCIM_TO_MRPCIM_VPLANE9_RMSG_INT
 
- VXGE_HW_SRPCIM_MSG_TO_VPATH_REG_SWIF_SRPCIM_TO_VPATH_RMSG_INT
 
- VXGE_HW_SRPCIM_MSIX_STATUS_INTCTL_SRPCIM_MSIX_MASK
 
- VXGE_HW_SRPCIM_MSIX_STATUS_INTCTL_SRPCIM_MSIX_PENDING_VECTOR
 
- VXGE_HW_SRPCIM_PCIPIF_INT_STATUS_MRPCIM_MSG_MRPCIM_MSG_INT
 
- VXGE_HW_SRPCIM_PCIPIF_INT_STATUS_SRPCIM_SPARE_R1_SRPCIM_SPARE_R1_INT
 
- VXGE_HW_SRPCIM_PCIPIF_INT_STATUS_VPATH_MSG_VPATH_MSG_INT
 
- VXGE_HW_SRPCIM_REG_MODIFIED_SRPCIM_REG_MODIFIED
 
- VXGE_HW_SRPCIM_RST_IN_PROG_SRPCIM_RST_IN_PROG
 
- VXGE_HW_SRPCIM_SET_MSIX_MASK_SRPCIM_SET_MSIX_MASK
 
- VXGE_HW_SRPCIM_TO_MRPCIM_ALARM_REG_PPIF_SRPCIM_TO_MRPCIM_ALARM
 
- VXGE_HW_SRPCIM_TO_MRPCIM_WMSG_SRPCIM_TO_MRPCIM_WMSG
 
- VXGE_HW_SRPCIM_TO_MRPCIM_WMSG_TRIG_SRPCIM_TO_MRPCIM_WMSG_TRIG
 
- VXGE_HW_SRPCIM_TO_VPATH_ALARM_REG_GET_PPIF_SRPCIM_TO_VPATH_ALARM
 
- VXGE_HW_SRPCIM_TO_VPATH_ALARM_REG_PPIF_SRPCIM_TO_VPATH_ALARM
 
- VXGE_HW_SRPCIM_TO_VPATH_WMSG_SRPCIM_TO_VPATH_WMSG
 
- VXGE_HW_SRPCIM_TO_VPATH_WMSG_TRIG_SRPCIM_TO_VPATH_WMSG_TRIG
 
- VXGE_HW_SR_VH_FUNCTION0
 
- VXGE_HW_SR_VH_VIRTUAL_FUNCTION
 
- VXGE_HW_STATS_AGGRn_OFFSET
 
- VXGE_HW_STATS_CFG0_STATS_ENABLE
 
- VXGE_HW_STATS_CFG_START_HOST_ADDR
 
- VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM0
 
- VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM1
 
- VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM2
 
- VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM3
 
- VXGE_HW_STATS_LEN
 
- VXGE_HW_STATS_LOC_AGGR
 
- VXGE_HW_STATS_OP_CLEAR_ALL_STATS
 
- VXGE_HW_STATS_OP_CLEAR_ALL_STATS_OF_LOC
 
- VXGE_HW_STATS_OP_CLEAR_ALL_VPATH_STATS
 
- VXGE_HW_STATS_OP_CLEAR_STAT
 
- VXGE_HW_STATS_OP_READ
 
- VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM0_OFFSET
 
- VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM2_OFFSET
 
- VXGE_HW_STATS_VPATH_RX_OFFSET
 
- VXGE_HW_STATS_VPATH_TX_OFFSET
 
- VXGE_HW_SWAPPER_BIT_FLIPPED
 
- VXGE_HW_SWAPPER_BYTE_SWAPPED
 
- VXGE_HW_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED
 
- VXGE_HW_SWAPPER_INITIAL_VALUE
 
- VXGE_HW_SWAPPER_READ_BIT_FLAP_DISABLE
 
- VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE
 
- VXGE_HW_SWAPPER_READ_BYTE_SWAP_DISABLE
 
- VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE
 
- VXGE_HW_SWAPPER_WRITE_BIT_FLAP_DISABLE
 
- VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE
 
- VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_DISABLE
 
- VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE
 
- VXGE_HW_SW_RESET_STATUS_INIT_CMPLT
 
- VXGE_HW_SW_RESET_STATUS_RESET_CMPLT
 
- VXGE_HW_TGT_ERRORS_REG_TGT_BOOT_WRITE
 
- VXGE_HW_TGT_ERRORS_REG_TGT_CPL_FSM_ERR
 
- VXGE_HW_TGT_ERRORS_REG_TGT_ILLEGAL_TLP_BE
 
- VXGE_HW_TGT_ERRORS_REG_TGT_KDFC_PROT_ERR
 
- VXGE_HW_TGT_ERRORS_REG_TGT_KDFC_READ
 
- VXGE_HW_TGT_ERRORS_REG_TGT_MRIOV_MEM_MAP_CFG_ERR
 
- VXGE_HW_TGT_ERRORS_REG_TGT_MSG_UNLOCK
 
- VXGE_HW_TGT_ERRORS_REG_TGT_MSIX_BEYOND_RANGE
 
- VXGE_HW_TGT_ERRORS_REG_TGT_NOT_MEM_TLP
 
- VXGE_HW_TGT_ERRORS_REG_TGT_PIF_READ_CROSS_QWRANGE
 
- VXGE_HW_TGT_ERRORS_REG_TGT_PIF_WR_CROSS_QWRANGE
 
- VXGE_HW_TGT_ERRORS_REG_TGT_REQ_FSM_ERR
 
- VXGE_HW_TGT_ERRORS_REG_TGT_SWIF_PROT_ERR
 
- VXGE_HW_TGT_ERRORS_REG_TGT_UNKNOWN_MEM_TLP
 
- VXGE_HW_TGT_ERRORS_REG_TGT_USDC_READ
 
- VXGE_HW_TGT_ERRORS_REG_TGT_USDC_WR_CROSS_QWRANGE
 
- VXGE_HW_TGT_ERRORS_REG_TGT_VENDOR_MSG
 
- VXGE_HW_TGT_ERRORS_REG_TGT_WR_TO_KDFC_POISON
 
- VXGE_HW_TGT_ERRORS_REG_TGT_WR_TO_MRIOV_POISON
 
- VXGE_HW_TGT_ERRORS_REG_TGT_WR_TO_MSIX_POISON
 
- VXGE_HW_TGT_ERRORS_REG_TGT_WR_TO_PIF_POISON
 
- VXGE_HW_TGT_ERRORS_REG_TGT_WR_TO_USDC_POISON
 
- VXGE_HW_TGT_ILLEGAL_ACCESS_SWIF_REGION
 
- VXGE_HW_TGT_PF_ILLEGAL_ACCESS_SWIF_REGION
 
- VXGE_HW_TIM_BITMAP_LLROOT_RXD_EN
 
- VXGE_HW_TIM_BITMAP_LLROOT_TXD_EN
 
- VXGE_HW_TIM_BITMAP_MASK
 
- VXGE_HW_TIM_BMAP_MAPPING_VP_ERR_TIM_DEST_VPATH
 
- VXGE_HW_TIM_BP_CTRL_RD_XON
 
- VXGE_HW_TIM_BP_CTRL_ROCRC_BYP
 
- VXGE_HW_TIM_BP_CTRL_WR_XON
 
- VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN
 
- VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL
 
- VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC
 
- VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI
 
- VXGE_HW_TIM_CFG1_INT_NUM_TXD_CNT_EN
 
- VXGE_HW_TIM_CFG1_INT_NUM_TXFRM_CNT_EN
 
- VXGE_HW_TIM_CFG1_INT_NUM_URNG_A
 
- VXGE_HW_TIM_CFG1_INT_NUM_URNG_B
 
- VXGE_HW_TIM_CFG1_INT_NUM_URNG_C
 
- VXGE_HW_TIM_CFG2_INT_NUM_UEC_A
 
- VXGE_HW_TIM_CFG2_INT_NUM_UEC_B
 
- VXGE_HW_TIM_CFG2_INT_NUM_UEC_C
 
- VXGE_HW_TIM_CFG2_INT_NUM_UEC_D
 
- VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL
 
- VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_EVENT_SF
 
- VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL
 
- VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI
 
- VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL
 
- VXGE_HW_TIM_CLR_INT_EN_VP
 
- VXGE_HW_TIM_DEST_ADDR_TIM_DEST_ADDR
 
- VXGE_HW_TIM_ECC_ENABLE_BMAP_MSG_N
 
- VXGE_HW_TIM_ECC_ENABLE_BMAP_N
 
- VXGE_HW_TIM_ECC_ENABLE_VBLS_N
 
- VXGE_HW_TIM_ERR_REG_TIM_BMAP_MAPPING_VP_ERR
 
- VXGE_HW_TIM_ERR_REG_TIM_BMAP_MEM_CNTRL_SM_ERR
 
- VXGE_HW_TIM_ERR_REG_TIM_BMAP_MSG_DB_ERR
 
- VXGE_HW_TIM_ERR_REG_TIM_BMAP_MSG_MEM_CNTRL_SM_ERR
 
- VXGE_HW_TIM_ERR_REG_TIM_BMAP_MSG_SG_ERR
 
- VXGE_HW_TIM_ERR_REG_TIM_BMAP_PA_DB_ERR
 
- VXGE_HW_TIM_ERR_REG_TIM_BMAP_PA_SG_ERR
 
- VXGE_HW_TIM_ERR_REG_TIM_BMAP_PB_DB_ERR
 
- VXGE_HW_TIM_ERR_REG_TIM_BMAP_PB_SG_ERR
 
- VXGE_HW_TIM_ERR_REG_TIM_CREATE_BMAPMSG_FIFO_ERR
 
- VXGE_HW_TIM_ERR_REG_TIM_MPIF_PCIWR_ERR
 
- VXGE_HW_TIM_ERR_REG_TIM_ROCRCIF_MISMATCH
 
- VXGE_HW_TIM_ERR_REG_TIM_ROCRC_BMAP_UPDT_FIFO_ERR
 
- VXGE_HW_TIM_ERR_REG_TIM_VBLS_DB_ERR
 
- VXGE_HW_TIM_ERR_REG_TIM_VBLS_SG_ERR
 
- VXGE_HW_TIM_INTR_DEFAULT
 
- VXGE_HW_TIM_INTR_DISABLE
 
- VXGE_HW_TIM_INTR_ENABLE
 
- VXGE_HW_TIM_INT_EN_TIM_VP
 
- VXGE_HW_TIM_INT_MASK0_TIM_INT_MASK0
 
- VXGE_HW_TIM_INT_MASK1_TIM_INT_MASK1
 
- VXGE_HW_TIM_INT_STATUS0_TIM_INT_STATUS0
 
- VXGE_HW_TIM_INT_STATUS1_TIM_INT_STATUS1
 
- VXGE_HW_TIM_MASK_INT_DURING_RESET_VPATH
 
- VXGE_HW_TIM_MR2SR_RESOURCE_ASSIGNMENT_VH_BMAP_ROOT
 
- VXGE_HW_TIM_OUTSTANDING_BMAP_TIM_VPATH
 
- VXGE_HW_TIM_PCI_CFG_ADD_PAD
 
- VXGE_HW_TIM_PCI_CFG_CTL_STR
 
- VXGE_HW_TIM_PCI_CFG_NO_SNOOP
 
- VXGE_HW_TIM_PCI_CFG_RELAXED
 
- VXGE_HW_TIM_REMAP_OFFLOAD_EN
 
- VXGE_HW_TIM_REMAP_RX_EN
 
- VXGE_HW_TIM_REMAP_TO_VPATH_NUM
 
- VXGE_HW_TIM_REMAP_TX_EN
 
- VXGE_HW_TIM_RESET_IN_PROGRESS_TIM_VPATH
 
- VXGE_HW_TIM_RESOURCE_ASSIGNMENT_VH_BMAP_ROOT
 
- VXGE_HW_TIM_RING_ASSN_INT_NUM
 
- VXGE_HW_TIM_SET_INT_EN_VP
 
- VXGE_HW_TIM_STATUS_TIM_RESET_IN_PROGRESS
 
- VXGE_HW_TIM_TIMER_AC_DISABLE
 
- VXGE_HW_TIM_TIMER_AC_ENABLE
 
- VXGE_HW_TIM_TIMER_CI_DISABLE
 
- VXGE_HW_TIM_TIMER_CI_ENABLE
 
- VXGE_HW_TIM_TIMER_RI_DISABLE
 
- VXGE_HW_TIM_TIMER_RI_ENABLE
 
- VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL
 
- VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL
 
- VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_RX_AVE_NET_UTIL
 
- VXGE_HW_TIM_UTIL_SEL_PER_VPATH
 
- VXGE_HW_TIM_VPATH_ASSIGNMENT_BMAP_ROOT
 
- VXGE_HW_TIM_VPATH_ASSIGNMENT_GET_BMAP_ROOT
 
- VXGE_HW_TIM_VPATH_MAP_BMAP_ROOT
 
- VXGE_HW_TIM_WRKLD_CLC_CNT_FRM_BYTE
 
- VXGE_HW_TIM_WRKLD_CLC_CNT_LNK_EN
 
- VXGE_HW_TIM_WRKLD_CLC_CNT_RX_TX
 
- VXGE_HW_TIM_WRKLD_CLC_HOST_UTIL
 
- VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_DIV
 
- VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_PRD
 
- VXGE_HW_TITAN1A_PCI_REVISION
 
- VXGE_HW_TITAN1_PCI_REVISION
 
- VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_DEVICE_ID
 
- VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MAJOR_REVISION
 
- VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MINOR_REVISION
 
- VXGE_HW_TITAN_ASIC_ID_INITIAL_DEVICE_ID
 
- VXGE_HW_TITAN_ASIC_ID_INITIAL_MAJOR_REVISION
 
- VXGE_HW_TITAN_ASIC_ID_INITIAL_MINOR_REVISION
 
- VXGE_HW_TITAN_GENERAL_INT_STATUS_MRPCIM_ALARM_INT
 
- VXGE_HW_TITAN_GENERAL_INT_STATUS_SRPCIM_ALARM_INT
 
- VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT
 
- VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT
 
- VXGE_HW_TITAN_MASK_ALL_INT_ALARM
 
- VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC
 
- VXGE_HW_TITAN_PCICFGMGMT_REG_SPACES
 
- VXGE_HW_TITAN_SRPCIM_REG_SPACES
 
- VXGE_HW_TITAN_VPATH_REG_SPACES
 
- VXGE_HW_TITAN_VPMGMT_REG_SPACES
 
- VXGE_HW_TMAC_INT_STATUS_TXMAC_ECC_ERR_TXMAC_ECC_INT
 
- VXGE_HW_TMAC_INT_STATUS_TXMAC_GEN_ERR_TXMAC_GEN_INT
 
- VXGE_HW_TOC_COMMON_POINTER_INITIAL_VAL
 
- VXGE_HW_TOC_FIRST_POINTER_INITIAL_VAL
 
- VXGE_HW_TOC_GET_KDFC_INITIAL_BIR
 
- VXGE_HW_TOC_GET_KDFC_INITIAL_OFFSET
 
- VXGE_HW_TOC_GET_USDC_INITIAL_BIR
 
- VXGE_HW_TOC_GET_USDC_INITIAL_OFFSET
 
- VXGE_HW_TOC_KDFC_FIFO_STRIDE_GET_TOC_KDFC_FIFO_STRIDE
 
- VXGE_HW_TOC_KDFC_FIFO_STRIDE_INITIAL_TOC_KDFC_FIFO_STRIDE
 
- VXGE_HW_TOC_KDFC_INITIAL_BIR
 
- VXGE_HW_TOC_KDFC_INITIAL_OFFSET
 
- VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE
 
- VXGE_HW_TOC_KDFC_VPATH_STRIDE_INITIAL_TOC_KDFC_VPATH_STRIDE
 
- VXGE_HW_TOC_MEMREPAIR_POINTER_INITIAL_VAL
 
- VXGE_HW_TOC_MRPCIM_POINTER_INITIAL_VAL
 
- VXGE_HW_TOC_PCICFGMGMT_POINTER_INITIAL_VAL
 
- VXGE_HW_TOC_SRPCIM_POINTER_INITIAL_VAL
 
- VXGE_HW_TOC_SWAPPER_FB_INITIAL_VAL
 
- VXGE_HW_TOC_USDC_INITIAL_BIR
 
- VXGE_HW_TOC_USDC_INITIAL_OFFSET
 
- VXGE_HW_TOC_VPATH_POINTER_INITIAL_VAL
 
- VXGE_HW_TOC_VPMGMT_POINTER_INITIAL_VAL
 
- VXGE_HW_TPA_CFG_IGNORE_FRAME_ERR
 
- VXGE_HW_TPA_CFG_IPV6_STOP_SEARCHING
 
- VXGE_HW_TPA_CFG_L4_PSHDR_PRESENT
 
- VXGE_HW_TPA_CFG_SUPPORT_MOBILE_IPV6_HDRS
 
- VXGE_HW_TPA_ERROR_REG_TPA_FSM_ERR_ALARM
 
- VXGE_HW_TPA_ERROR_REG_TPA_TPA_DA_LKUP_PRT0_DB_ERR
 
- VXGE_HW_TPA_ERROR_REG_TPA_TPA_DA_LKUP_PRT0_SG_ERR
 
- VXGE_HW_TPA_GLOBAL_CFG_ECC_ENABLE_N
 
- VXGE_HW_TPA_GLOBAL_CFG_SUPPORT_SNAP_AB_N
 
- VXGE_HW_TPA_INT_STATUS_ORP_ERR_ORP_INT
 
- VXGE_HW_TPA_INT_STATUS_PTM_ALARM_PTM_INT
 
- VXGE_HW_TPA_INT_STATUS_TPA_ERROR_TPA_INT
 
- VXGE_HW_TXDL_STATE_AVAIL
 
- VXGE_HW_TXDL_STATE_FREED
 
- VXGE_HW_TXDL_STATE_NONE
 
- VXGE_HW_TXDL_STATE_POSTED
 
- VXGE_HW_TXD_OWNERSHIP_CTRL_KEEP_OWNERSHIP
 
- VXGE_HW_TXMAC_CFG0_PORT_APPEND_PAD
 
- VXGE_HW_TXMAC_CFG0_PORT_PAD_BYTE
 
- VXGE_HW_TXMAC_CFG0_PORT_TMAC_EN
 
- VXGE_HW_TXMAC_CFG0_PORT_VPMGMT_CLONE_APPEND_PAD
 
- VXGE_HW_TXMAC_CFG0_PORT_VPMGMT_CLONE_PAD_BYTE
 
- VXGE_HW_TXMAC_CFG0_PORT_VPMGMT_CLONE_TMAC_EN
 
- VXGE_HW_TXMAC_CFG1_PORT_AVG_IPG
 
- VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMACJ_FSM_ERR
 
- VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2MAC_DB_ERR
 
- VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2MAC_SG_ERR
 
- VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_DA_DB_ERR
 
- VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_DA_SG_ERR
 
- VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_SB_DB_ERR
 
- VXGE_HW_TXMAC_ECC_ERR_REG_TMACJ_TMAC_TPA2M_SB_SG_ERR
 
- VXGE_HW_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT0_FSM_ERR
 
- VXGE_HW_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT1_FSM_ERR
 
- VXGE_HW_TXMAC_ECC_ERR_REG_TMAC_TMAC_PORT2_FSM_ERR
 
- VXGE_HW_TXMAC_GEN_CFG0_VPMGMT_CLONE_CHOSEN_TX_PORT
 
- VXGE_HW_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_SWITCH
 
- VXGE_HW_TXMAC_GEN_CFG1_BLOCK_BCAST_TO_WIRE
 
- VXGE_HW_TXMAC_GEN_CFG1_HOST_APPEND_FCS
 
- VXGE_HW_TXMAC_GEN_CFG1_TMAC_PERMA_STOP_EN
 
- VXGE_HW_TXMAC_GEN_ERR_REG_TMACJ_NO_VALID_VSPORT
 
- VXGE_HW_TXMAC_GEN_ERR_REG_TMACJ_PERMANENT_STOP
 
- VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_PKT_WEIGHT
 
- VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_FRAC_UTIL
 
- VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_SCALE_FACTOR
 
- VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_TMAC_UTILIZATION
 
- VXGE_HW_TXMAC_LINK_UTIL_PORT_TMAC_UTIL_CFG
 
- VXGE_HW_TXMAC_STATUS_PORT_TMAC_TX_FRM_SENT
 
- VXGE_HW_TXPE_PCI_NCE_CFG_NCE_THRESH
 
- VXGE_HW_TXPE_PCI_NCE_CFG_NOSNOOP_TOWI
 
- VXGE_HW_TXPE_PCI_NCE_CFG_PAD_TOWI_ENABLE
 
- VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TPA_TX_FRAC_UTIL
 
- VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TPA_TX_UTILIZATION
 
- VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TX_PKT_WEIGHT
 
- VXGE_HW_TX_DATAPATH_UTIL_VP_CLONE_TX_UTIL_CFG
 
- VXGE_HW_TX_PROTOCOL_ASSIST_CFG_IPV6_KEEP_SEARCHING
 
- VXGE_HW_TX_PROTOCOL_ASSIST_CFG_LSOV2_EN
 
- VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS
 
- VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_TX_VP_RESET_DISCARDED_FRMS
 
- VXGE_HW_UMQDMQ_IR_INIT_HOST_WRITE_ADD
 
- VXGE_HW_UMQDMQ_IR_INIT_NOTIFY_PULSE
 
- VXGE_HW_UMQ_BWR_INIT_ADD_HOST
 
- VXGE_HW_UMQ_BWR_INIT_BYTE_COUNT
 
- VXGE_HW_UMQ_BWR_PFCH_CTRL_POLL_EN
 
- VXGE_HW_UMQ_INIT_NOTIFY_PULSE
 
- VXGE_HW_UMQ_INT_BITMAP
 
- VXGE_HW_UMQ_INT_EVENT_ENABLE
 
- VXGE_HW_UMQ_INT_IMMED_ENABLE
 
- VXGE_HW_UMQ_INT_NUMBER
 
- VXGE_HW_UMQ_MR2VP_BWR_EOL_POLL_LATENCY
 
- VXGE_HW_UMQ_MR2VP_BWR_PFCH_INIT_NUMBER
 
- VXGE_HW_UMQ_VH_DATA_LIST_EMPTY_ROCRC_UMQ_VH_DATA_LIST_EMPTY
 
- VXGE_HW_UPGRADE_GET_RET_ERR_CODE
 
- VXGE_HW_UPGRADE_GET_SEC_ERR_CODE
 
- VXGE_HW_USDC_DRBL_CTRL_FLIP_EN
 
- VXGE_HW_USDC_DRBL_CTRL_SWAP_EN
 
- VXGE_HW_USDC_VPATH_SGRP_ASSIGN
 
- VXGE_HW_USDC_VP_READY_USDC_CQRQ_READY
 
- VXGE_HW_USDC_VP_READY_USDC_HTN_READY
 
- VXGE_HW_USDC_VP_READY_USDC_SRQ_READY
 
- VXGE_HW_USE_FLASH_DEFAULT
 
- VXGE_HW_VH_NORMAL_FUNCTION
 
- VXGE_HW_VIRTUAL_PATH_HANDLE
 
- VXGE_HW_VPATH_ASSIGNMENTS_VPATH_ASSIGNMENTS
 
- VXGE_HW_VPATH_BANDWIDTH_DEFAULT
 
- VXGE_HW_VPATH_BANDWIDTH_MAX
 
- VXGE_HW_VPATH_BANDWIDTH_MIN
 
- VXGE_HW_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT
 
- VXGE_HW_VPATH_DEBUG_STATS0_INI_NUM_MWR_SENT
 
- VXGE_HW_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT
 
- VXGE_HW_VPATH_DEBUG_STATS1_INI_NUM_MRD_SENT
 
- VXGE_HW_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD
 
- VXGE_HW_VPATH_DEBUG_STATS2_INI_NUM_CPL_RCVD
 
- VXGE_HW_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT
 
- VXGE_HW_VPATH_DEBUG_STATS3_INI_NUM_MWR_BYTE_SENT
 
- VXGE_HW_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD
 
- VXGE_HW_VPATH_DEBUG_STATS4_INI_NUM_CPL_BYTE_RCVD
 
- VXGE_HW_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF
 
- VXGE_HW_VPATH_DEBUG_STATS5_WRCRDTARB_XOFF
 
- VXGE_HW_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF
 
- VXGE_HW_VPATH_DEBUG_STATS6_RDCRDTARB_XOFF
 
- VXGE_HW_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN
 
- VXGE_HW_VPATH_GENERAL_CFG1_CTL_FLIPEN
 
- VXGE_HW_VPATH_GENERAL_CFG1_DATA_BYTE_SWAPEN
 
- VXGE_HW_VPATH_GENERAL_CFG1_DATA_FLIPEN
 
- VXGE_HW_VPATH_GENERAL_CFG1_MSIX_ADDR_FLIPEN
 
- VXGE_HW_VPATH_GENERAL_CFG1_MSIX_ADDR_SWAPEN
 
- VXGE_HW_VPATH_GENERAL_CFG1_MSIX_DATA_FLIPEN
 
- VXGE_HW_VPATH_GENERAL_CFG1_MSIX_DATA_SWAPEN
 
- VXGE_HW_VPATH_GENERAL_CFG1_TC_VALUE
 
- VXGE_HW_VPATH_GENERAL_CFG2_SIZE_QUANTUM
 
- VXGE_HW_VPATH_GENERAL_CFG3_IGNORE_VPATH_RST_FOR_INTA
 
- VXGE_HW_VPATH_GENERAL_INT_MASK_PCI_INT
 
- VXGE_HW_VPATH_GENERAL_INT_MASK_PIC_INT
 
- VXGE_HW_VPATH_GENERAL_INT_MASK_WRDMA_INT
 
- VXGE_HW_VPATH_GENERAL_INT_MASK_XMAC_INT
 
- VXGE_HW_VPATH_GENERAL_INT_STATUS_PCI_INT
 
- VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT
 
- VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT
 
- VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT
 
- VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0
 
- VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1
 
- VXGE_HW_VPATH_GENSTATS_COUNT01_PPIF_VPATH_GENSTATS_COUNT0
 
- VXGE_HW_VPATH_GENSTATS_COUNT01_PPIF_VPATH_GENSTATS_COUNT1
 
- VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2
 
- VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3
 
- VXGE_HW_VPATH_GENSTATS_COUNT23_PPIF_VPATH_GENSTATS_COUNT2
 
- VXGE_HW_VPATH_GENSTATS_COUNT23_PPIF_VPATH_GENSTATS_COUNT3
 
- VXGE_HW_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4
 
- VXGE_HW_VPATH_GENSTATS_COUNT4_PPIF_VPATH_GENSTATS_COUNT4
 
- VXGE_HW_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5
 
- VXGE_HW_VPATH_GENSTATS_COUNT5_PPIF_VPATH_GENSTATS_COUNT5
 
- VXGE_HW_VPATH_INTR_BMAP
 
- VXGE_HW_VPATH_INTR_EINTA
 
- VXGE_HW_VPATH_INTR_RX
 
- VXGE_HW_VPATH_INTR_TX
 
- VXGE_HW_VPATH_IS_FIRST_GET_VPATH_IS_FIRST
 
- VXGE_HW_VPATH_IS_FIRST_VPATH_IS_FIRST
 
- VXGE_HW_VPATH_MAC_ADDR_ADD_DUPLICATE
 
- VXGE_HW_VPATH_MAC_ADDR_DISCARD_DUPLICATE
 
- VXGE_HW_VPATH_MAC_ADDR_REPLACE_DUPLICATE
 
- VXGE_HW_VPATH_MAX_INITIAL_MTU
 
- VXGE_HW_VPATH_MIN_INITIAL_MTU
 
- VXGE_HW_VPATH_MSG_REG_SWIF_VPATH0_TO_SRPCIM_RMSG_INT
 
- VXGE_HW_VPATH_MSG_REG_SWIF_VPATH10_TO_SRPCIM_RMSG_INT
 
- VXGE_HW_VPATH_MSG_REG_SWIF_VPATH11_TO_SRPCIM_RMSG_INT
 
- VXGE_HW_VPATH_MSG_REG_SWIF_VPATH12_TO_SRPCIM_RMSG_INT
 
- VXGE_HW_VPATH_MSG_REG_SWIF_VPATH13_TO_SRPCIM_RMSG_INT
 
- VXGE_HW_VPATH_MSG_REG_SWIF_VPATH14_TO_SRPCIM_RMSG_INT
 
- VXGE_HW_VPATH_MSG_REG_SWIF_VPATH15_TO_SRPCIM_RMSG_INT
 
- VXGE_HW_VPATH_MSG_REG_SWIF_VPATH16_TO_SRPCIM_RMSG_INT
 
- VXGE_HW_VPATH_MSG_REG_SWIF_VPATH1_TO_SRPCIM_RMSG_INT
 
- VXGE_HW_VPATH_MSG_REG_SWIF_VPATH2_TO_SRPCIM_RMSG_INT
 
- VXGE_HW_VPATH_MSG_REG_SWIF_VPATH3_TO_SRPCIM_RMSG_INT
 
- VXGE_HW_VPATH_MSG_REG_SWIF_VPATH4_TO_SRPCIM_RMSG_INT
 
- VXGE_HW_VPATH_MSG_REG_SWIF_VPATH5_TO_SRPCIM_RMSG_INT
 
- VXGE_HW_VPATH_MSG_REG_SWIF_VPATH6_TO_SRPCIM_RMSG_INT
 
- VXGE_HW_VPATH_MSG_REG_SWIF_VPATH7_TO_SRPCIM_RMSG_INT
 
- VXGE_HW_VPATH_MSG_REG_SWIF_VPATH8_TO_SRPCIM_RMSG_INT
 
- VXGE_HW_VPATH_MSG_REG_SWIF_VPATH9_TO_SRPCIM_RMSG_INT
 
- VXGE_HW_VPATH_MSIX_ACTIVE
 
- VXGE_HW_VPATH_PCIPIF_INT_STATUS_SRPCIM_MSG_TO_VPATH_SRPCIM_MSG_TO_VPATH_INT
 
- VXGE_HW_VPATH_PCIPIF_INT_STATUS_VPATH_SPARE_R1_VPATH_SPARE_R1_INT
 
- VXGE_HW_VPATH_PPIF_INT_STATUS_GENERAL_ERRORS_GENERAL_INT
 
- VXGE_HW_VPATH_PPIF_INT_STATUS_KDFCCTL_ERRORS_KDFCCTL_INT
 
- VXGE_HW_VPATH_PPIF_INT_STATUS_MRPCIM_TO_VPATH_ALARM_MRPCIM_TO_VPATH_ALARM_INT
 
- VXGE_HW_VPATH_PPIF_INT_STATUS_PCI_CONFIG_ERRORS_PCI_CONFIG_INT
 
- VXGE_HW_VPATH_PPIF_INT_STATUS_SRPCIM_TO_VPATH_ALARM_SRPCIM_TO_VPATH_ALARM_INT
 
- VXGE_HW_VPATH_PRIORITY_DEFAULT
 
- VXGE_HW_VPATH_PRIORITY_MAX
 
- VXGE_HW_VPATH_PRIORITY_MIN
 
- VXGE_HW_VPATH_REG_MODIFIED_VPATH_REG_MODIFIED
 
- VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_DISABLE
 
- VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_ENABLE
 
- VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT
 
- VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG
 
- VXGE_HW_VPATH_RX_STATS_LEN
 
- VXGE_HW_VPATH_STATS_LEN
 
- VXGE_HW_VPATH_STATS_PIO_READ
 
- VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1
 
- VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_VPATH_TO_FUNC_MAP_CFG1
 
- VXGE_HW_VPATH_TO_MRPCIM_ALARM_REG_PPIF_VPATH_TO_MRPCIM_ALARM
 
- VXGE_HW_VPATH_TO_SRPCIM_RMSG_SEL_VPATH_TO_SRPCIM_RMSG_SEL
 
- VXGE_HW_VPATH_TO_SRPCIM_RMSG_SWIF_VPATH_TO_SRPCIM_RMSG
 
- VXGE_HW_VPATH_TO_SRPCIM_WMSG_TRIG_VPATH_TO_SRPCIM_WMSG_TRIG
 
- VXGE_HW_VPATH_TO_SRPCIM_WMSG_VPATH_TO_SRPCIM_WMSG
 
- VXGE_HW_VPATH_TO_VPLANE_MAP_VPATH_TO_VPLANE_MAP
 
- VXGE_HW_VPATH_TX_STATS_LEN
 
- VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU
 
- VXGE_HW_VPLANE_ASSIGNMENTS_VPLANE_ASSIGNMENTS
 
- VXGE_HW_VP_NOT_OPEN
 
- VXGE_HW_VP_OPEN
 
- VXGE_HW_WDE0_ALARM_REG_WDE0_CP_CMD_ERR
 
- VXGE_HW_WDE0_ALARM_REG_WDE0_CP_SM_ERR
 
- VXGE_HW_WDE0_ALARM_REG_WDE0_DCC_SM_ERR
 
- VXGE_HW_WDE0_ALARM_REG_WDE0_PCR_SM_ERR
 
- VXGE_HW_WDE0_ALARM_REG_WDE0_PRM_SM_ERR
 
- VXGE_HW_WDE1_ALARM_REG_WDE1_CP_CMD_ERR
 
- VXGE_HW_WDE1_ALARM_REG_WDE1_CP_SM_ERR
 
- VXGE_HW_WDE1_ALARM_REG_WDE1_DCC_SM_ERR
 
- VXGE_HW_WDE1_ALARM_REG_WDE1_PCR_SM_ERR
 
- VXGE_HW_WDE1_ALARM_REG_WDE1_PRM_SM_ERR
 
- VXGE_HW_WDE2_ALARM_REG_WDE2_CP_CMD_ERR
 
- VXGE_HW_WDE2_ALARM_REG_WDE2_CP_SM_ERR
 
- VXGE_HW_WDE2_ALARM_REG_WDE2_DCC_SM_ERR
 
- VXGE_HW_WDE2_ALARM_REG_WDE2_PCR_SM_ERR
 
- VXGE_HW_WDE2_ALARM_REG_WDE2_PRM_SM_ERR
 
- VXGE_HW_WDE3_ALARM_REG_WDE3_CP_CMD_ERR
 
- VXGE_HW_WDE3_ALARM_REG_WDE3_CP_SM_ERR
 
- VXGE_HW_WDE3_ALARM_REG_WDE3_DCC_SM_ERR
 
- VXGE_HW_WDE3_ALARM_REG_WDE3_PCR_SM_ERR
 
- VXGE_HW_WDE3_ALARM_REG_WDE3_PRM_SM_ERR
 
- VXGE_HW_WDE_CFG_ALIGNMENT_PREFERENCE
 
- VXGE_HW_WDE_CFG_DISABLE_QPAD_FOR_UNALIGNED_ADDR
 
- VXGE_HW_WDE_CFG_MEM_WORD_SIZE
 
- VXGE_HW_WDE_CFG_NS0_FORCE_MPSB_END
 
- VXGE_HW_WDE_CFG_NS0_FORCE_MPSB_START
 
- VXGE_HW_WDE_CFG_NS0_FORCE_MWB_END
 
- VXGE_HW_WDE_CFG_NS0_FORCE_MWB_START
 
- VXGE_HW_WDE_CFG_NS0_FORCE_QB_END
 
- VXGE_HW_WDE_CFG_NS0_FORCE_QB_START
 
- VXGE_HW_WDE_CFG_NS0_MPSB_OPT_EN
 
- VXGE_HW_WDE_CFG_NS0_MWB_OPT_EN
 
- VXGE_HW_WDE_CFG_NS0_QB_OPT_EN
 
- VXGE_HW_WDE_CFG_NS1_FORCE_MPSB_END
 
- VXGE_HW_WDE_CFG_NS1_FORCE_MPSB_START
 
- VXGE_HW_WDE_CFG_NS1_FORCE_MWB_END
 
- VXGE_HW_WDE_CFG_NS1_FORCE_MWB_START
 
- VXGE_HW_WDE_CFG_NS1_FORCE_QB_END
 
- VXGE_HW_WDE_CFG_NS1_FORCE_QB_START
 
- VXGE_HW_WDE_CFG_NS1_MPSB_OPT_EN
 
- VXGE_HW_WDE_CFG_NS1_MWB_OPT_EN
 
- VXGE_HW_WDE_CFG_NS1_QB_OPT_EN
 
- VXGE_HW_WDE_PRM_CTRL_FB_ROW_SIZE
 
- VXGE_HW_WDE_PRM_CTRL_SPAV_THRESHOLD
 
- VXGE_HW_WDE_PRM_CTRL_SPLIT_ON_1ST_ROW
 
- VXGE_HW_WDE_PRM_CTRL_SPLIT_ON_ROW_BNDRY
 
- VXGE_HW_WDE_PRM_CTRL_SPLIT_THRESHOLD
 
- VXGE_HW_WEIGHTED_RR_SERVICE_STATES
 
- VXGE_HW_WOL_MP_CRC_CRC
 
- VXGE_HW_WOL_MP_CRC_RC_EN
 
- VXGE_HW_WOL_MP_MASK_A_MASK
 
- VXGE_HW_WOL_MP_MASK_B_MASK
 
- VXGE_HW_WRCRDTARB_STATUS0_VPLANE_WRCRDTARB_ABS_AVAIL_P_H
 
- VXGE_HW_WRCRDTARB_STATUS1_VPLANE_WRCRDTARB_ABS_AVAIL_P_D
 
- VXGE_HW_WRDMA_ALARM_STATUS_PRC_ALARM_PRC_INT
 
- VXGE_HW_WRDMA_INT_STATUS_FRF_ALARM_FRF_INT
 
- VXGE_HW_WRDMA_INT_STATUS_RC_ALARM_RC_INT
 
- VXGE_HW_WRDMA_INT_STATUS_RDA_ECC_DB_RDA_ECC_DB_INT
 
- VXGE_HW_WRDMA_INT_STATUS_RDA_ECC_SG_RDA_ECC_SG_INT
 
- VXGE_HW_WRDMA_INT_STATUS_RDA_ERR_RDA_INT
 
- VXGE_HW_WRDMA_INT_STATUS_ROCRC_ALARM_ROCRC_INT
 
- VXGE_HW_WRDMA_INT_STATUS_RXDCM_SM_ERR_RXDCM_SM_INT
 
- VXGE_HW_WRDMA_INT_STATUS_RXDRM_SM_ERR_RXDRM_INT
 
- VXGE_HW_WRDMA_INT_STATUS_RXDWM_SM_ERR_RXDWM_INT
 
- VXGE_HW_WRDMA_INT_STATUS_WDE0_ALARM_WDE0_INT
 
- VXGE_HW_WRDMA_INT_STATUS_WDE1_ALARM_WDE1_INT
 
- VXGE_HW_WRDMA_INT_STATUS_WDE2_ALARM_WDE2_INT
 
- VXGE_HW_WRDMA_INT_STATUS_WDE3_ALARM_WDE3_INT
 
- VXGE_HW_WRITE_ARB_PENDING_WRARB_INTCTL
 
- VXGE_HW_WRITE_ARB_PENDING_WRARB_MSG
 
- VXGE_HW_WRITE_ARB_PENDING_WRARB_RTDMA
 
- VXGE_HW_WRITE_ARB_PENDING_WRARB_STATSB
 
- VXGE_HW_WRITE_ARB_PENDING_WRARB_WRDMA
 
- VXGE_HW_WRR_FIFO_COUNT
 
- VXGE_HW_WRR_FIFO_SERVICE_STATES
 
- VXGE_HW_WRR_RING_COUNT
 
- VXGE_HW_WRR_RING_SERVICE_STATES
 
- VXGE_HW_XGMAC_GEN_FW_MEMO_MASK_MASK
 
- VXGE_HW_XGMAC_GEN_FW_MEMO_STATUS_XMACJ_EVENTS_PENDING
 
- VXGE_HW_XGMAC_GEN_FW_VPATH_TO_VSPORT_STATUS_XMACJ_EVENTS_PENDING
 
- VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_DATA_RATE
 
- VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK
 
- VXGE_HW_XGMAC_GEN_STATUS_XMACJ_NTWK_DATA_RATE
 
- VXGE_HW_XGMAC_GEN_STATUS_XMACJ_NTWK_OK
 
- VXGE_HW_XGMAC_INT_STATUS_ASIC_GPIO_ERR_ASIC_GPIO_INT
 
- VXGE_HW_XGMAC_INT_STATUS_ASIC_NTWK_ERR_ASIC_NTWK_INT
 
- VXGE_HW_XGMAC_INT_STATUS_XGXS_GEN_ERR_XGXS_GEN_INT
 
- VXGE_HW_XGMAC_INT_STATUS_XMAC_GEN_ERR_XMAC_GEN_INT
 
- VXGE_HW_XGMAC_INT_STATUS_XMAC_LINK_ERR_PORT0_XMAC_LINK_INT_PORT0
 
- VXGE_HW_XGMAC_INT_STATUS_XMAC_LINK_ERR_PORT1_XMAC_LINK_INT_PORT1
 
- VXGE_HW_XGMAC_MAIN_CFG_PORT_PORT_EN
 
- VXGE_HW_XGMAC_READY_XMACJ_READY
 
- VXGE_HW_XGMAC_SR_INT_STATUS_ASIC_NTWK_SR_ERR_ASIC_NTWK_SR_INT
 
- VXGE_HW_XGMAC_STATUS_PORT_VPMGMT_CLONE_RMAC_LOCAL_FAULT
 
- VXGE_HW_XGMAC_STATUS_PORT_VPMGMT_CLONE_RMAC_REMOTE_FAULT
 
- VXGE_HW_XGMAC_STATUS_PORT_VPMGMT_CLONE_XMACJ_MAC_PHY_LAYER_AVAIL
 
- VXGE_HW_XGMAC_STATUS_PORT_VPMGMT_CLONE_XMACJ_PORT_OK
 
- VXGE_HW_XGMAC_VP_INT_STATUS_ASIC_NTWK_VP_ERR_ASIC_NTWK_VP_INT
 
- VXGE_HW_XGXS_CFG_PORT_SEL_INFO_0
 
- VXGE_HW_XGXS_CFG_PORT_SEL_INFO_1
 
- VXGE_HW_XGXS_CFG_PORT_SIG_DETECT_FORCE_LOS
 
- VXGE_HW_XGXS_CFG_PORT_SIG_DETECT_FORCE_VALID
 
- VXGE_HW_XGXS_CFG_PORT_TX_LANE0_SKEW
 
- VXGE_HW_XGXS_CFG_PORT_TX_LANE1_SKEW
 
- VXGE_HW_XGXS_CFG_PORT_TX_LANE2_SKEW
 
- VXGE_HW_XGXS_CFG_PORT_TX_LANE3_SKEW
 
- VXGE_HW_XGXS_GEN_ERR_REG_XGXS_XGXS_FSM_ERR
 
- VXGE_HW_XGXS_INFO_PORT_XMACJ_INFO_0
 
- VXGE_HW_XGXS_INFO_PORT_XMACJ_INFO_1
 
- VXGE_HW_XGXS_PMA_RESET_PORT_SERDES_RESET
 
- VXGE_HW_XGXS_RXBER_CFG_PORT_INTERVAL_DUR
 
- VXGE_HW_XGXS_RXBER_CFG_PORT_RXGXS_INTERVAL_CNT
 
- VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_A_ERR_CNT
 
- VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_B_ERR_CNT
 
- VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_C_ERR_CNT
 
- VXGE_HW_XGXS_RXBER_STATUS_PORT_RXGXS_RXGXS_LANE_D_ERR_CNT
 
- VXGE_HW_XGXS_STATIC_CFG_PORT_FW_CTRL_SERDES
 
- VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_ALIGNMENT_ERR
 
- VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_BYTE_SYNC_LOST
 
- VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_CTC_ERR
 
- VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_CTC_FIFO_ERR
 
- VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_DEC_ERR
 
- VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_RX_ACTIVITY
 
- VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_SKIP_DEL_REQ
 
- VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_SKIP_INS_REQ
 
- VXGE_HW_XGXS_STATUS_PORT_XMACJ_PCS_TX_ACTIVITY
 
- VXGE_HW_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_LOOPBACK
 
- VXGE_HW_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_REVERSE_LOOPBACK
 
- VXGE_HW_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_RX_BEHAV
 
- VXGE_HW_XMAC_CFG_PORT_VPMGMT_CLONE_XGMII_TX_BEHAV
 
- VXGE_HW_XMAC_CFG_PORT_XGMII_LOOPBACK
 
- VXGE_HW_XMAC_CFG_PORT_XGMII_REVERSE_LOOPBACK
 
- VXGE_HW_XMAC_CFG_PORT_XGMII_RX_BEHAV
 
- VXGE_HW_XMAC_CFG_PORT_XGMII_TX_BEHAV
 
- VXGE_HW_XMAC_GEN_CFG_FAULT_BEHAVIOUR
 
- VXGE_HW_XMAC_GEN_CFG_PERIOD_NTWK_DOWN
 
- VXGE_HW_XMAC_GEN_CFG_PERIOD_NTWK_UP
 
- VXGE_HW_XMAC_GEN_CFG_RATEMGMT_MAC_RATE_SEL
 
- VXGE_HW_XMAC_GEN_CFG_TX_HEAD_DROP_WHEN_FAULT
 
- VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_FAULT_BEHAVIOUR
 
- VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_PERIOD_NTWK_DOWN
 
- VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_PERIOD_NTWK_UP
 
- VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_RATEMGMT_MAC_RATE_SEL
 
- VXGE_HW_XMAC_GEN_CFG_VPMGMT_CLONE_TX_HEAD_DROP_WHEN_FAULT
 
- VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_ACTOR_CHURN_DETECTED
 
- VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_PARTNER_CHURN_DETECTED
 
- VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT0_RECEIVED_LACPDU
 
- VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_ACTOR_CHURN_DETECTED
 
- VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_PARTNER_CHURN_DETECTED
 
- VXGE_HW_XMAC_GEN_ERR_REG_LAGC_LAG_PORT1_RECEIVED_LACPDU
 
- VXGE_HW_XMAC_GEN_ERR_REG_XLCM_LAG_FAILOVER_DETECTED
 
- VXGE_HW_XMAC_GEN_ERR_REG_XMACJ_XMAC_FSM_ERR
 
- VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_DB_ERR
 
- VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE0_SG_ERR
 
- VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_DB_ERR
 
- VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE1_SG_ERR
 
- VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_DB_ERR
 
- VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE2_SG_ERR
 
- VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_DB_ERR
 
- VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE3_SG_ERR
 
- VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_DB_ERR
 
- VXGE_HW_XMAC_GEN_ERR_REG_XSTATS_RMAC_STATS_TILE4_SG_ERR
 
- VXGE_HW_XMAC_LINK_ERR_PORT_REG_RATEMGMT_LASI_INV
 
- VXGE_HW_XMAC_LINK_ERR_PORT_REG_RATEMGMT_RATE_CHANGE
 
- VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_LINK_DOWN
 
- VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_LINK_UP
 
- VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_DOWN
 
- VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_REAFFIRMED_FAULT
 
- VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_REAFFIRMED_OK
 
- VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_UP
 
- VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_WENT_DOWN
 
- VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMACJ_PORT_WENT_UP
 
- VXGE_HW_XMAC_LINK_ERR_PORT_REG_XMDIO_MDIO_MGR_ACCESS_COMPLETE
 
- VXGE_HW_XMAC_RPA_VCFG_IPV4_TCP_INCL_PH
 
- VXGE_HW_XMAC_RPA_VCFG_IPV4_UDP_INCL_PH
 
- VXGE_HW_XMAC_RPA_VCFG_IPV6_TCP_INCL_PH
 
- VXGE_HW_XMAC_RPA_VCFG_IPV6_UDP_INCL_PH
 
- VXGE_HW_XMAC_RPA_VCFG_L4_INCL_CF
 
- VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG
 
- VXGE_HW_XMAC_STATION_ADDR_PORT_MAC_ADDR
 
- VXGE_HW_XMAC_STATS_ACCESS_CMD_OFFSET_SEL
 
- VXGE_HW_XMAC_STATS_ACCESS_CMD_OP
 
- VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE
 
- VXGE_HW_XMAC_STATS_ACCESS_DATA_XSMGR_DATA
 
- VXGE_HW_XMAC_STATS_GEN_CFG_PRTAGGR_CUM_TIMER
 
- VXGE_HW_XMAC_STATS_GEN_CFG_VLAN_HANDLING
 
- VXGE_HW_XMAC_STATS_GEN_CFG_VPATH_CUM_TIMER
 
- VXGE_HW_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_PRTAGGR_CUM_TIMER
 
- VXGE_HW_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_VLAN_HANDLING
 
- VXGE_HW_XMAC_STATS_GEN_CFG_VPMGMT_CLONE_VPATH_CUM_TIMER
 
- VXGE_HW_XMAC_STATS_SYS_CMD_LOC_SEL
 
- VXGE_HW_XMAC_STATS_SYS_CMD_OFFSET_SEL
 
- VXGE_HW_XMAC_STATS_SYS_CMD_OP
 
- VXGE_HW_XMAC_STATS_SYS_CMD_STROBE
 
- VXGE_HW_XMAC_STATS_SYS_DATA_XSMGR_DATA
 
- VXGE_HW_XMAC_TIMESTAMP_EN
 
- VXGE_HW_XMAC_TIMESTAMP_INTERVAL
 
- VXGE_HW_XMAC_TIMESTAMP_TIMER_RESTART
 
- VXGE_HW_XMAC_TIMESTAMP_USE_LINK_ID
 
- VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_EN
 
- VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_INTERVAL
 
- VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_TIMER_RESTART
 
- VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_USE_LINK_ID
 
- VXGE_HW_XMAC_TIMESTAMP_VPMGMT_CLONE_XMACJ_ROLLOVER_CNT
 
- VXGE_HW_XMAC_TIMESTAMP_XMACJ_ROLLOVER_CNT
 
- VXGE_HW_XMAC_VPATH_TO_VSPORT_VPMGMT_CLONE_GET_VSPORT_NUMBER
 
- VXGE_HW_XMAC_VSPORT_CHOICES_SR_CLONE_VSPORT_VECTOR
 
- VXGE_HW_XMAC_VSPORT_CHOICES_VH_VSPORT_VECTOR
 
- VXGE_HW_XMAC_VSPORT_CHOICES_VP_GET_VSPORT_VECTOR
 
- VXGE_HW_XMAC_VSPORT_CHOICES_VP_VSPORT_VECTOR
 
- VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER
 
- VXGE_INTR_STRLEN
 
- VXGE_ISR_POLLING_CNT
 
- VXGE_LL_COMPL_RESET
 
- VXGE_LL_DEVICE_RESET
 
- VXGE_LL_EVENT_BASE
 
- VXGE_LL_FULL_RESET
 
- VXGE_LL_MAC_ADDR_IN_DA_TABLE
 
- VXGE_LL_MAC_ADDR_IN_LIST
 
- VXGE_LL_MAX_FRAME_SIZE
 
- VXGE_LL_RX_COPY_THRESHOLD
 
- VXGE_LL_START_RESET
 
- VXGE_LL_VPATH_RESET
 
- VXGE_LL_WATCH_DOG_TIMEOUT
 
- VXGE_MAIN_H
 
- VXGE_MAX_CONFIG_DEV
 
- VXGE_MAX_CONFIG_PORT
 
- VXGE_MAX_FLICKER_TIME
 
- VXGE_MAX_LEARN_MAC_ADDR_CNT
 
- VXGE_MAX_MAC_ADDR_COUNT
 
- VXGE_MAX_REQUESTED_MSIX
 
- VXGE_MODULE_PARAM_INT
 
- VXGE_NONE
 
- VXGE_PAUSE_CTRL_DISABLE
 
- VXGE_PAUSE_CTRL_ENABLE
 
- VXGE_REG_H
 
- VXGE_RTI_BTIMER_VAL
 
- VXGE_RTI_LTIMER_VAL
 
- VXGE_RTI_RTIMER_ADAPT_VAL
 
- VXGE_RTI_RTIMER_VAL
 
- VXGE_SW_STATS_LEN
 
- VXGE_T1A_MAX_INTERRUPT_COUNT
 
- VXGE_T1A_MAX_TX_INTERRUPT_COUNT
 
- VXGE_T1A_TTI_LTIMER_VAL
 
- VXGE_T1A_TTI_RTIMER_VAL
 
- VXGE_TIMER_DELAY
 
- VXGE_TITLE_LEN
 
- VXGE_TRACE
 
- VXGE_TRAFFIC_H
 
- VXGE_TTI_BTIMER_VAL
 
- VXGE_TTI_LTIMER_VAL
 
- VXGE_TTI_RTIMER_ADAPT_VAL
 
- VXGE_TTI_RTIMER_VAL
 
- VXGE_USE_DEFAULT
 
- VXGE_VERSION_BUILD
 
- VXGE_VERSION_FIX
 
- VXGE_VERSION_FOR
 
- VXGE_VERSION_H
 
- VXGE_VERSION_MAJOR
 
- VXGE_VERSION_MINOR
 
- VXLAN6_HEADROOM
 
- VXLAN_DF_INHERIT
 
- VXLAN_DF_MAX
 
- VXLAN_DF_SET
 
- VXLAN_DF_UNSET
 
- VXLAN_ENABLE
 
- VXLAN_ENABLE_MODIFY
 
- VXLAN_EN_F
 
- VXLAN_EN_S
 
- VXLAN_EN_V
 
- VXLAN_FLAG
 
- VXLAN_F_ALLOWED_GPE
 
- VXLAN_F_COLLECT_METADATA
 
- VXLAN_F_GBP
 
- VXLAN_F_GPE
 
- VXLAN_F_IPV6
 
- VXLAN_F_IPV6_LINKLOCAL
 
- VXLAN_F_L2MISS
 
- VXLAN_F_L3MISS
 
- VXLAN_F_LEARN
 
- VXLAN_F_PROXY
 
- VXLAN_F_RCV_FLAGS
 
- VXLAN_F_REMCSUM_NOPARTIAL
 
- VXLAN_F_REMCSUM_RX
 
- VXLAN_F_REMCSUM_TX
 
- VXLAN_F_RSC
 
- VXLAN_F_TTL_INHERIT
 
- VXLAN_F_UDP_ZERO_CSUM6_RX
 
- VXLAN_F_UDP_ZERO_CSUM6_TX
 
- VXLAN_F_UDP_ZERO_CSUM_TX
 
- VXLAN_G
 
- VXLAN_GBP_DONT_LEARN
 
- VXLAN_GBP_ID_MASK
 
- VXLAN_GBP_POLICY_APPLIED
 
- VXLAN_GBP_USED_BITS
 
- VXLAN_GPE_USED_BITS
 
- VXLAN_HEADROOM
 
- VXLAN_HF_GBP
 
- VXLAN_HF_NP
 
- VXLAN_HF_OAM
 
- VXLAN_HF_RCO
 
- VXLAN_HF_VER
 
- VXLAN_HF_VNI
 
- VXLAN_HLEN
 
- VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK
 
- VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT
 
- VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK
 
- VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT
 
- VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK
 
- VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT
 
- VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST
 
- VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK
 
- VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT
 
- VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK
 
- VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT
 
- VXLAN_M
 
- VXLAN_MAX_REMCSUM_START
 
- VXLAN_N_VID
 
- VXLAN_RCO_MASK
 
- VXLAN_RCO_SHIFT
 
- VXLAN_RCO_SHIFT_MASK
 
- VXLAN_RCO_UDP
 
- VXLAN_S
 
- VXLAN_STEERING_MODIFY
 
- VXLAN_STEER_BY_INNER_MAC
 
- VXLAN_STEER_BY_INNER_VLAN
 
- VXLAN_STEER_BY_OUTER_MAC
 
- VXLAN_STEER_BY_OUTER_VLAN
 
- VXLAN_STEER_BY_VSID_VNI
 
- VXLAN_V
 
- VXLAN_VERSION
 
- VXLAN_VID_MASK
 
- VXLAN_VNI_MASK
 
- VXPS_MASK
 
- VXP_CDSP_CLOCKIN_SEL_MASK
 
- VXP_CDSP_CODEC_RESET_MASK
 
- VXP_CDSP_DATAIN_SEL_MASK
 
- VXP_CDSP_DSP_RESET_MASK
 
- VXP_CDSP_MIC_SEL_MASK
 
- VXP_CDSP_RESERVED_MASK
 
- VXP_CDSP_SMPTE_SEL_MASK
 
- VXP_CDSP_VALID_IRQ_MASK
 
- VXP_DLG_ACK_MEMIRQ_MASK
 
- VXP_DLG_DATA_XICOR_MASK
 
- VXP_DLG_DMA16_SEL_MASK
 
- VXP_DLG_DMAREAD_SEL_MASK
 
- VXP_DLG_DMAWRITE_SEL_MASK
 
- VXP_DLG_MEMIRQ_MASK
 
- VXP_DLG_RESERVED1_0_MASK
 
- VXP_DLG_RESERVED2_0_MASK
 
- VXP_DLG_RESERVED4_0_MASK
 
- VXP_DLG_XILINX_REPROG_MASK
 
- VXP_IRQ_OFFSET
 
- VXR
 
- VXR_MASK
 
- VXSPEC_MAJOR
 
- VXUIMM2_MASK
 
- VXUIMM3_MASK
 
- VXUIMM4_MASK
 
- VXVA
 
- VXVAPS_MASK
 
- VXVAVB_MASK
 
- VXVA_MASK
 
- VXVB_MASK
 
- VXVDVA_MASK
 
- VXVM_MAJOR
 
- VX_12
 
- VX_ACQ
 
- VX_ALIGNMENT
 
- VX_ALIGN_MASK
 
- VX_ANALOG_OUT_LEVEL_MAX
 
- VX_AUDIO_INFO_LINEAR_16
 
- VX_AUDIO_INFO_LINEAR_24
 
- VX_AUDIO_INFO_LINEAR_8
 
- VX_AUDIO_INFO_MPEG1
 
- VX_AUDIO_INFO_MPEG2
 
- VX_AUDIO_INFO_OFFLINE
 
- VX_AUDIO_INFO_REAL_TIME
 
- VX_AUDIO_SRC_DIGITAL
 
- VX_AUDIO_SRC_LINE
 
- VX_AUDIO_SRC_MIC
 
- VX_BIT0
 
- VX_BIT1
 
- VX_CDSP
 
- VX_CDSP_CODEC_RESET_MASK
 
- VX_CDSP_DSP_RESET_MASK
 
- VX_CDSP_GPIO_OUT_MASK
 
- VX_CDSP_RESERVED0_0_MASK
 
- VX_CDSP_TEST0_MASK
 
- VX_CDSP_TEST1_MASK
 
- VX_CDSP_TOR1_MASK
 
- VX_CDSP_TOR2_MASK
 
- VX_CDSP_VALID_IRQ_MASK
 
- VX_CFG
 
- VX_CFG_CLOCKIN_SEL_MASK
 
- VX_CFG_DATAIN_SEL_MASK
 
- VX_CFG_RESERVED0_0_MASK
 
- VX_CFG_RESERVED1_0_MASK
 
- VX_CFG_RESERVED2_0_MASK
 
- VX_CFG_RESERVED3_0_MASK
 
- VX_CFG_RESERVED4_0_MASK
 
- VX_CFG_SYNCDSP_MASK
 
- VX_CLOCK_MODE_AUTO
 
- VX_CLOCK_MODE_EXTERNAL
 
- VX_CLOCK_MODE_INTERNAL
 
- VX_CNTRL
 
- VX_CNTRL_REGISTER_VALUE
 
- VX_CODEC2
 
- VX_COMPOT
 
- VX_CSUER
 
- VX_CUER_HH_BITC_SEL_MASK
 
- VX_CUER_LL_BITC_SEL_MASK
 
- VX_CUER_MH_BITC_SEL_MASK
 
- VX_CUER_ML_BITC_SEL_MASK
 
- VX_CVR
 
- VX_DATA
 
- VX_DATA_CODEC_MASK
 
- VX_DATA_XICOR_MASK
 
- VX_DIALOG
 
- VX_DMA
 
- VX_DRIVER_VERSION
 
- VX_ERR_MASK
 
- VX_GAIN
 
- VX_GLIMIT
 
- VX_GPIOC
 
- VX_GPIO_IN_BIT_OFFSET
 
- VX_GPIO_OUT_BIT_OFFSET
 
- VX_HIFREQ
 
- VX_ICR
 
- VX_INTCSR
 
- VX_INTCSR_VALUE
 
- VX_ISR
 
- VX_IVR
 
- VX_LOFREQ
 
- VX_MASK
 
- VX_MAX_CODECS
 
- VX_MAX_PERIODS
 
- VX_MAX_PIPES
 
- VX_MEMIRQ
 
- VX_MIC0
 
- VX_MIC1
 
- VX_MIC2
 
- VX_MIC3
 
- VX_MICRO
 
- VX_MIN_LEN
 
- VX_PCI_INTERRUPT_MASK
 
- VX_PCI_VX222_NEW
 
- VX_PCI_VX222_OLD
 
- VX_PLX0
 
- VX_PLX1
 
- VX_PLX2
 
- VX_REG_MAX
 
- VX_RESET_DMA
 
- VX_RESET_DMA_REGISTER_OFFSET
 
- VX_RFREQ
 
- VX_RUER
 
- VX_RUER_V2
 
- VX_RXH
 
- VX_RXL
 
- VX_RXM
 
- VX_SCOMPR
 
- VX_SELMIC
 
- VX_STATUS
 
- VX_STATUS_DATA_XICOR_MASK
 
- VX_STATUS_GPIO_IN_MASK
 
- VX_STATUS_LEVEL_IN_MASK
 
- VX_STATUS_MEMIRQ_MASK
 
- VX_STATUS_RESERVED0_MASK
 
- VX_STATUS_VAL_TEST0_MASK
 
- VX_STATUS_VAL_TEST1_MASK
 
- VX_STATUS_VAL_TOR0_MASK
 
- VX_STATUS_VAL_TOR1_MASK
 
- VX_STAT_CHIP_INIT
 
- VX_STAT_DEVICE_INIT
 
- VX_STAT_IN_SUSPEND
 
- VX_STAT_IS_STALE
 
- VX_STAT_XILINX_LOADED
 
- VX_SUER_CLOCK_PRESENT_MASK
 
- VX_SUER_DATA_PRESENT_MASK
 
- VX_SUER_FREQ_32KHz_MASK
 
- VX_SUER_FREQ_44KHz_MASK
 
- VX_SUER_FREQ_48KHz_MASK
 
- VX_SUER_FREQ_MASK
 
- VX_TXH
 
- VX_TXL
 
- VX_TXM
 
- VX_TYPE_BOARD
 
- VX_TYPE_MIC
 
- VX_TYPE_NUMS
 
- VX_TYPE_V2
 
- VX_TYPE_VXP440
 
- VX_TYPE_VXPOCKET
 
- VX_UER_MODE_CONSUMER
 
- VX_UER_MODE_NOT_PRESENT
 
- VX_UER_MODE_PROFESSIONAL
 
- VX_USERBIT0_MASK
 
- VX_USERBIT1_MASK
 
- VX_XILINX_RESET_MASK
 
- VYUY
 
- VYUY10_1X20
 
- VYUY10_2X10
 
- VYUY12_1X24
 
- VYUY12_2X12
 
- VYUY8_1X16
 
- VYUY8_1_5X8
 
- VYUY8_2X8
 
- VZ89TE
 
- VZ89TE_REG_MEASUREMENT
 
- VZ89TE_REG_MEASUREMENT_RD_SIZE
 
- VZ89TE_REG_MEASUREMENT_WR_SIZE
 
- VZ89TE_VOC_CO2_IDX
 
- VZ89TE_VOC_RESISTANCE_IDX
 
- VZ89TE_VOC_TVOC_IDX
 
- VZ89X
 
- VZ89X_REG_MEASUREMENT
 
- VZ89X_REG_MEASUREMENT_RD_SIZE
 
- VZ89X_REG_MEASUREMENT_WR_SIZE
 
- VZ89X_VOC_CO2_IDX
 
- VZ89X_VOC_RESISTANCE_IDX
 
- VZ89X_VOC_SHORT_IDX
 
- VZ89X_VOC_TVOC_IDX
 
- V_000102_PAGE_TABLE_FLAT
 
- V_00016C_SYSTEM_ACCESS_MODE_IN_SYS
 
- V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS
 
- V_00016C_SYSTEM_ACCESS_MODE_PA_ONLY
 
- V_00016C_SYSTEM_ACCESS_MODE_USE_SYS_MAP
 
- V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE
 
- V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH
 
- V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF
 
- V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q
 
- V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q
 
- V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY
 
- V_028010_ARRAY_1D_TILED_THIN1
 
- V_028010_ARRAY_2D_TILED_THIN1
 
- V_028010_DEPTH_16
 
- V_028010_DEPTH_32_FLOAT
 
- V_028010_DEPTH_8_24
 
- V_028010_DEPTH_8_24_FLOAT
 
- V_028010_DEPTH_INVALID
 
- V_028010_DEPTH_X24_8_32_FLOAT
 
- V_028010_DEPTH_X8_24
 
- V_028010_DEPTH_X8_24_FLOAT
 
- V_028040_Z_16
 
- V_028040_Z_24
 
- V_028040_Z_32_FLOAT
 
- V_028040_Z_INVALID
 
- V_028044_STENCIL_8
 
- V_028044_STENCIL_INVALID
 
- V_0280A0_ARRAY_1D_TILED_THIN1
 
- V_0280A0_ARRAY_2D_TILED_THIN1
 
- V_0280A0_ARRAY_LINEAR_ALIGNED
 
- V_0280A0_ARRAY_LINEAR_GENERAL
 
- V_0280A0_CLEAR_ENABLE
 
- V_0280A0_COLOR_10_10_10_2
 
- V_0280A0_COLOR_10_11_11
 
- V_0280A0_COLOR_10_11_11_FLOAT
 
- V_0280A0_COLOR_11_11_10
 
- V_0280A0_COLOR_11_11_10_FLOAT
 
- V_0280A0_COLOR_16
 
- V_0280A0_COLOR_16_16
 
- V_0280A0_COLOR_16_16_16_16
 
- V_0280A0_COLOR_16_16_16_16_FLOAT
 
- V_0280A0_COLOR_16_16_FLOAT
 
- V_0280A0_COLOR_16_FLOAT
 
- V_0280A0_COLOR_1_5_5_5
 
- V_0280A0_COLOR_24_8
 
- V_0280A0_COLOR_24_8_FLOAT
 
- V_0280A0_COLOR_2_10_10_10
 
- V_0280A0_COLOR_32
 
- V_0280A0_COLOR_32_32
 
- V_0280A0_COLOR_32_32_32_32
 
- V_0280A0_COLOR_32_32_32_32_FLOAT
 
- V_0280A0_COLOR_32_32_FLOAT
 
- V_0280A0_COLOR_32_FLOAT
 
- V_0280A0_COLOR_3_3_2
 
- V_0280A0_COLOR_4_4
 
- V_0280A0_COLOR_4_4_4_4
 
- V_0280A0_COLOR_5_5_5_1
 
- V_0280A0_COLOR_5_6_5
 
- V_0280A0_COLOR_6_5_5
 
- V_0280A0_COLOR_8
 
- V_0280A0_COLOR_8_24
 
- V_0280A0_COLOR_8_24_FLOAT
 
- V_0280A0_COLOR_8_8
 
- V_0280A0_COLOR_8_8_8_8
 
- V_0280A0_COLOR_INVALID
 
- V_0280A0_COLOR_X24_8_32_FLOAT
 
- V_0280A0_FRAG_ENABLE
 
- V_0280A0_TILE_DISABLE
 
- V_028800_STENCILFUNC_ALWAYS
 
- V_028800_STENCILFUNC_EQUAL
 
- V_028800_STENCILFUNC_GEQUAL
 
- V_028800_STENCILFUNC_GREATER
 
- V_028800_STENCILFUNC_LEQUAL
 
- V_028800_STENCILFUNC_LESS
 
- V_028800_STENCILFUNC_NEVER
 
- V_028800_STENCILFUNC_NOTEQUAL
 
- V_028800_STENCIL_DECR
 
- V_028800_STENCIL_DECR_WRAP
 
- V_028800_STENCIL_INCR
 
- V_028800_STENCIL_INCR_WRAP
 
- V_028800_STENCIL_INVERT
 
- V_028800_STENCIL_KEEP
 
- V_028800_STENCIL_REPLACE
 
- V_028800_STENCIL_ZERO
 
- V_028808_SPECIAL_DISABLE
 
- V_028808_SPECIAL_NORMAL
 
- V_028808_SPECIAL_RESOLVE_BOX
 
- V_028C70_ARRAY_1D_TILED_THIN1
 
- V_028C70_ARRAY_2D_TILED_THIN1
 
- V_028C70_ARRAY_LINEAR_ALIGNED
 
- V_028C70_ARRAY_LINEAR_GENERAL
 
- V_028C70_COLOR_10_10_10_2
 
- V_028C70_COLOR_10_11_11
 
- V_028C70_COLOR_10_11_11_FLOAT
 
- V_028C70_COLOR_11_11_10
 
- V_028C70_COLOR_11_11_10_FLOAT
 
- V_028C70_COLOR_16
 
- V_028C70_COLOR_16_16
 
- V_028C70_COLOR_16_16_16_16
 
- V_028C70_COLOR_16_16_16_16_FLOAT
 
- V_028C70_COLOR_16_16_FLOAT
 
- V_028C70_COLOR_16_FLOAT
 
- V_028C70_COLOR_1_5_5_5
 
- V_028C70_COLOR_24_8
 
- V_028C70_COLOR_24_8_FLOAT
 
- V_028C70_COLOR_2_10_10_10
 
- V_028C70_COLOR_32
 
- V_028C70_COLOR_32_32
 
- V_028C70_COLOR_32_32_32_32
 
- V_028C70_COLOR_32_32_32_32_FLOAT
 
- V_028C70_COLOR_32_32_32_FLOAT
 
- V_028C70_COLOR_32_32_FLOAT
 
- V_028C70_COLOR_32_FLOAT
 
- V_028C70_COLOR_3_3_2
 
- V_028C70_COLOR_4_4
 
- V_028C70_COLOR_4_4_4_4
 
- V_028C70_COLOR_5_5_5_1
 
- V_028C70_COLOR_5_6_5
 
- V_028C70_COLOR_6_5_5
 
- V_028C70_COLOR_8
 
- V_028C70_COLOR_8_24
 
- V_028C70_COLOR_8_24_FLOAT
 
- V_028C70_COLOR_8_8
 
- V_028C70_COLOR_8_8_8_8
 
- V_028C70_COLOR_INVALID
 
- V_028C70_COLOR_X24_8_32_FLOAT
 
- V_028C70_EXPORT_2C_32BPC
 
- V_028C70_EXPORT_4C_16BPC
 
- V_028C70_EXPORT_4C_32BPC
 
- V_028C70_NUMBER_FLOAT
 
- V_028C70_NUMBER_SINT
 
- V_028C70_NUMBER_SNORM
 
- V_028C70_NUMBER_SRGB
 
- V_028C70_NUMBER_SSCALED
 
- V_028C70_NUMBER_UINT
 
- V_028C70_NUMBER_UNORM
 
- V_028C70_NUMBER_USCALED
 
- V_028C70_SWAP_ALT
 
- V_028C70_SWAP_ALT_REV
 
- V_028C70_SWAP_STD
 
- V_028C70_SWAP_STD_REV
 
- V_030000_SQ_TEX_DIM_1D
 
- V_030000_SQ_TEX_DIM_1D_ARRAY
 
- V_030000_SQ_TEX_DIM_2D
 
- V_030000_SQ_TEX_DIM_2D_ARRAY
 
- V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA
 
- V_030000_SQ_TEX_DIM_2D_MSAA
 
- V_030000_SQ_TEX_DIM_3D
 
- V_030000_SQ_TEX_DIM_CUBEMAP
 
- V_030010_SQ_FORMAT_COMP_SIGNED
 
- V_030010_SQ_FORMAT_COMP_UNSIGNED
 
- V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED
 
- V_030010_SQ_NUM_FORMAT_INT
 
- V_030010_SQ_NUM_FORMAT_NORM
 
- V_030010_SQ_NUM_FORMAT_SCALED
 
- V_030010_SQ_SEL_0
 
- V_030010_SQ_SEL_1
 
- V_030010_SQ_SEL_W
 
- V_030010_SQ_SEL_X
 
- V_030010_SQ_SEL_Y
 
- V_030010_SQ_SEL_Z
 
- V_030010_SRF_MODE_NO_ZERO
 
- V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE
 
- V_03001C_SQ_TEX_VTX_INVALID_BUFFER
 
- V_03001C_SQ_TEX_VTX_INVALID_TEXTURE
 
- V_03001C_SQ_TEX_VTX_VALID_BUFFER
 
- V_03001C_SQ_TEX_VTX_VALID_TEXTURE
 
- V_038000_ARRAY_1D_TILED_THIN1
 
- V_038000_ARRAY_2D_TILED_THIN1
 
- V_038000_ARRAY_LINEAR_ALIGNED
 
- V_038000_ARRAY_LINEAR_GENERAL
 
- V_038000_SQ_TEX_DIM_1D
 
- V_038000_SQ_TEX_DIM_1D_ARRAY
 
- V_038000_SQ_TEX_DIM_2D
 
- V_038000_SQ_TEX_DIM_2D_ARRAY
 
- V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA
 
- V_038000_SQ_TEX_DIM_2D_MSAA
 
- V_038000_SQ_TEX_DIM_3D
 
- V_038000_SQ_TEX_DIM_CUBEMAP
 
- V_038004_COLOR_10_10_10_2
 
- V_038004_COLOR_10_11_11
 
- V_038004_COLOR_10_11_11_FLOAT
 
- V_038004_COLOR_11_11_10
 
- V_038004_COLOR_11_11_10_FLOAT
 
- V_038004_COLOR_16
 
- V_038004_COLOR_16_16
 
- V_038004_COLOR_16_16_16_16
 
- V_038004_COLOR_16_16_16_16_FLOAT
 
- V_038004_COLOR_16_16_FLOAT
 
- V_038004_COLOR_16_FLOAT
 
- V_038004_COLOR_1_5_5_5
 
- V_038004_COLOR_24_8
 
- V_038004_COLOR_24_8_FLOAT
 
- V_038004_COLOR_2_10_10_10
 
- V_038004_COLOR_32
 
- V_038004_COLOR_32_32
 
- V_038004_COLOR_32_32_32_32
 
- V_038004_COLOR_32_32_32_32_FLOAT
 
- V_038004_COLOR_32_32_FLOAT
 
- V_038004_COLOR_32_FLOAT
 
- V_038004_COLOR_3_3_2
 
- V_038004_COLOR_4_4
 
- V_038004_COLOR_4_4_4_4
 
- V_038004_COLOR_5_5_5_1
 
- V_038004_COLOR_5_6_5
 
- V_038004_COLOR_6_5_5
 
- V_038004_COLOR_8
 
- V_038004_COLOR_8_24
 
- V_038004_COLOR_8_24_FLOAT
 
- V_038004_COLOR_8_8
 
- V_038004_COLOR_8_8_8_8
 
- V_038004_COLOR_INVALID
 
- V_038004_COLOR_X24_8_32_FLOAT
 
- V_038004_FMT_1
 
- V_038004_FMT_16_16_16
 
- V_038004_FMT_16_16_16_FLOAT
 
- V_038004_FMT_32_32_32
 
- V_038004_FMT_32_32_32_FLOAT
 
- V_038004_FMT_32_AS_32_32_32_32
 
- V_038004_FMT_32_AS_8
 
- V_038004_FMT_32_AS_8_8
 
- V_038004_FMT_5_9_9_9_SHAREDEXP
 
- V_038004_FMT_8_8_8
 
- V_038004_FMT_BC1
 
- V_038004_FMT_BC2
 
- V_038004_FMT_BC3
 
- V_038004_FMT_BC4
 
- V_038004_FMT_BC5
 
- V_038004_FMT_BC6
 
- V_038004_FMT_BC7
 
- V_038004_FMT_BG_RG
 
- V_038004_FMT_GB_GR
 
- V_12
 
- V_16
 
- V_2MSL
 
- V_32
 
- V_5181
 
- V_5182
 
- V_5281
 
- V_5TUPLE_LOOKUP
 
- V_64BIT
 
- V_8
 
- V_88F6810
 
- V_88F6810_PLUS
 
- V_88F6820
 
- V_88F6820_PLUS
 
- V_88F6828
 
- V_88F6920
 
- V_88F6920_PLUS
 
- V_88F6925
 
- V_88F6925_PLUS
 
- V_88F6928
 
- V_96KHZ
 
- V_98DX3236
 
- V_98DX3236_PLUS
 
- V_98DX3336
 
- V_98DX4251
 
- V_A
 
- V_ACKLAT
 
- V_ACSR_ACTIPHY_TMR
 
- V_ACT
 
- V_ACTIVE
 
- V_ACTIVE_HI
 
- V_ACTIVE_LO
 
- V_ACTIVE_MASK
 
- V_ACTIVE_SHIFT
 
- V_ACTIVE_TO_PRECHARGE_DELAY
 
- V_ACTIVE_TO_READ_WRITE_DELAY
 
- V_ACTRGNFULL
 
- V_ACTTOPREDLY
 
- V_ACTTORDWRDLY
 
- V_ADDR_INC
 
- V_ADDR_INDEX
 
- V_ADDR_RES
 
- V_ADDR_SHADOW_INDEX
 
- V_ADDR_WRDLY
 
- V_AE
 
- V_AIS
 
- V_AIS_ITU
 
- V_AIS_OUT
 
- V_ALL
 
- V_ALMOSTEMPTY
 
- V_ALMOSTFULL
 
- V_ALT_FR_RX
 
- V_ALT_FR_TX
 
- V_AMERR
 
- V_AOPEN_IFF_VLAN
 
- V_AOPEN_MAC_MATCH
 
- V_AOPEN_MAC_MATCH_VALID
 
- V_AOPEN_PKT_TYPE
 
- V_AOPEN_VLAN_PRI
 
- V_AOPEN_VLAN_PRI_VALID
 
- V_ARBFPERR
 
- V_ARBPF0PERR
 
- V_ARBPF1PERR
 
- V_ARMADA_7K
 
- V_ARMADA_7K_8K_CPM
 
- V_ARMADA_7K_8K_CPS
 
- V_ARMADA_8K_CPM
 
- V_ARMADA_8K_CPS
 
- V_ARPLUTPERR
 
- V_ATRAP_CFG_AGENTID
 
- V_ATRAP_CFG_CATTR
 
- V_ATRAP_CFG_CNT
 
- V_ATTACK_FILTER
 
- V_ATT_LEV
 
- V_ATX
 
- V_AUTOCAREFUL
 
- V_AUTOENABLE
 
- V_AUTOSTATE1
 
- V_AUTOSTATE2
 
- V_AUTOSTATE3
 
- V_AUTO_ERR_RES
 
- V_AUTO_RECO
 
- V_AUTO_RESYNC
 
- V_AUTO_SYNC
 
- V_AUTO_WD_RES
 
- V_AVOIDCQOVFL
 
- V_B12_SWAP
 
- V_B1_EN
 
- V_B1_RX_EN
 
- V_B2_EN
 
- V_B2_RX_EN
 
- V_BACK_DOOR_OPERATION
 
- V_BANKS
 
- V_BASE1
 
- V_BCM1480_ATRAP_CFG_AGENTID
 
- V_BCM1480_ATRAP_CFG_CATTR
 
- V_BCM1480_ATRAP_CFG_CNT
 
- V_BCM1480_INT_HT_EDGETRIGGER
 
- V_BCM1480_INT_HT_INTDEST
 
- V_BCM1480_INT_HT_INTMSG
 
- V_BCM1480_INT_HT_LEVELTRIGGER
 
- V_BCM1480_INT_HT_LOGICALDEST
 
- V_BCM1480_INT_HT_PHYSICALDEST
 
- V_BCM1480_INT_HT_VECTOR
 
- V_BCM1480_L2C_DATA_ECC
 
- V_BCM1480_L2C_MGMT_ECC_DIAG
 
- V_BCM1480_L2C_MGMT_INDEX
 
- V_BCM1480_L2C_MGMT_WAY
 
- V_BCM1480_L2C_TAG_ECC
 
- V_BCM1480_L2C_TAG_INDEX
 
- V_BCM1480_L2C_TAG_TAG
 
- V_BCM1480_L2C_TAG_WAY
 
- V_BCM1480_MC_ADDR_COARSE_ADJ
 
- V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT
 
- V_BCM1480_MC_ADDR_FINE_ADJ
 
- V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT
 
- V_BCM1480_MC_ADDR_FREQ_RANGE
 
- V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT
 
- V_BCM1480_MC_BLK_CLR_MARK
 
- V_BCM1480_MC_BLK_SET_MARK
 
- V_BCM1480_MC_CHANNEL_SELECT
 
- V_BCM1480_MC_CLK_RATIO
 
- V_BCM1480_MC_CLK_RATIO_DEFAULT
 
- V_BCM1480_MC_COL00
 
- V_BCM1480_MC_COL01
 
- V_BCM1480_MC_COL02
 
- V_BCM1480_MC_COL03
 
- V_BCM1480_MC_COL04
 
- V_BCM1480_MC_COL05
 
- V_BCM1480_MC_COL06
 
- V_BCM1480_MC_COL07
 
- V_BCM1480_MC_COL08
 
- V_BCM1480_MC_COL09
 
- V_BCM1480_MC_COL11
 
- V_BCM1480_MC_COL12
 
- V_BCM1480_MC_COL13
 
- V_BCM1480_MC_COL14
 
- V_BCM1480_MC_COMMAND
 
- V_BCM1480_MC_COMMAND_AR
 
- V_BCM1480_MC_COMMAND_CLRPWRDN
 
- V_BCM1480_MC_COMMAND_CLRRFSH
 
- V_BCM1480_MC_COMMAND_DISABLE_MCLK
 
- V_BCM1480_MC_COMMAND_EMRS
 
- V_BCM1480_MC_COMMAND_EMRS2
 
- V_BCM1480_MC_COMMAND_EMRS3
 
- V_BCM1480_MC_COMMAND_ENABLE_MCLK
 
- V_BCM1480_MC_COMMAND_MRS
 
- V_BCM1480_MC_COMMAND_PRE
 
- V_BCM1480_MC_COMMAND_SETPWRDN
 
- V_BCM1480_MC_COMMAND_SETRFSH
 
- V_BCM1480_MC_CONFIG_DEFAULT
 
- V_BCM1480_MC_CS
 
- V_BCM1480_MC_CS01_BANK0
 
- V_BCM1480_MC_CS01_BANK1
 
- V_BCM1480_MC_CS01_BANK2
 
- V_BCM1480_MC_CS0_END
 
- V_BCM1480_MC_CS0_START
 
- V_BCM1480_MC_CS1_END
 
- V_BCM1480_MC_CS1_START
 
- V_BCM1480_MC_CS23_BANK0
 
- V_BCM1480_MC_CS23_BANK1
 
- V_BCM1480_MC_CS23_BANK2
 
- V_BCM1480_MC_CS2_END
 
- V_BCM1480_MC_CS2_START
 
- V_BCM1480_MC_CS3_END
 
- V_BCM1480_MC_CS3_START
 
- V_BCM1480_MC_CS_MODE
 
- V_BCM1480_MC_CS_MODE_DEFAULT
 
- V_BCM1480_MC_DLL_BGCTRL
 
- V_BCM1480_MC_DLL_DEFAULT
 
- V_BCM1480_MC_DLL_DEFAULT_BGCTRL
 
- V_BCM1480_MC_DLL_DEFAULT_DEFAULT
 
- V_BCM1480_MC_DLL_DEFAULT_PDSEL
 
- V_BCM1480_MC_DLL_DEFAULT_REGCTRL
 
- V_BCM1480_MC_DLL_FREQ_RANGE
 
- V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT
 
- V_BCM1480_MC_DLL_PDSEL
 
- V_BCM1480_MC_DLL_REGCTRL
 
- V_BCM1480_MC_DLL_STEP_SIZE
 
- V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT
 
- V_BCM1480_MC_DQI_COARSE_ADJ
 
- V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT
 
- V_BCM1480_MC_DQI_FINE_ADJ
 
- V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT
 
- V_BCM1480_MC_DQI_FREQ_RANGE
 
- V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT
 
- V_BCM1480_MC_DQO_COARSE_ADJ
 
- V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT
 
- V_BCM1480_MC_DQO_FINE_ADJ
 
- V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT
 
- V_BCM1480_MC_DQO_FREQ_RANGE
 
- V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT
 
- V_BCM1480_MC_DRAMMODE_DEFAULT
 
- V_BCM1480_MC_DRAM_TYPE
 
- V_BCM1480_MC_DRAM_TYPE_DDR2
 
- V_BCM1480_MC_DRAM_TYPE_FCRAM
 
- V_BCM1480_MC_DRAM_TYPE_JEDEC
 
- V_BCM1480_MC_ECC_CORRECT
 
- V_BCM1480_MC_ECC_CORR_ADDR
 
- V_BCM1480_MC_ECC_ERR_ADDR
 
- V_BCM1480_MC_EMODE
 
- V_BCM1480_MC_EMODE_DEFAULT
 
- V_BCM1480_MC_INTLV0
 
- V_BCM1480_MC_INTLV0_DEFAULT
 
- V_BCM1480_MC_INTLV1
 
- V_BCM1480_MC_INTLV1_DEFAULT
 
- V_BCM1480_MC_INTLV2
 
- V_BCM1480_MC_INTLV2_DEFAULT
 
- V_BCM1480_MC_INTLV_MODE
 
- V_BCM1480_MC_INTLV_MODE_01
 
- V_BCM1480_MC_INTLV_MODE_0123
 
- V_BCM1480_MC_INTLV_MODE_01_23
 
- V_BCM1480_MC_INTLV_MODE_23
 
- V_BCM1480_MC_INTLV_MODE_NONE
 
- V_BCM1480_MC_MAX_AGE
 
- V_BCM1480_MC_MODE
 
- V_BCM1480_MC_MODE_DEFAULT
 
- V_BCM1480_MC_ODT0
 
- V_BCM1480_MC_ODT2
 
- V_BCM1480_MC_ODT4
 
- V_BCM1480_MC_ODT6
 
- V_BCM1480_MC_PG_POLICY
 
- V_BCM1480_MC_PG_POLICY_CAS_TIME_CHK
 
- V_BCM1480_MC_PG_POLICY_CLOSED
 
- V_BCM1480_MC_PVT_BYP_C1_PULLDOWN
 
- V_BCM1480_MC_PVT_BYP_C1_PULLUP
 
- V_BCM1480_MC_PVT_BYP_C2_PULLDOWN
 
- V_BCM1480_MC_PVT_BYP_C2_PULLUP
 
- V_BCM1480_MC_REF_RATE
 
- V_BCM1480_MC_REF_RATE_100MHz
 
- V_BCM1480_MC_REF_RATE_200MHz
 
- V_BCM1480_MC_REF_RATE_400MHz
 
- V_BCM1480_MC_REF_RATE_DEFAULT
 
- V_BCM1480_MC_ROW00
 
- V_BCM1480_MC_ROW01
 
- V_BCM1480_MC_ROW02
 
- V_BCM1480_MC_ROW03
 
- V_BCM1480_MC_ROW04
 
- V_BCM1480_MC_ROW05
 
- V_BCM1480_MC_ROW06
 
- V_BCM1480_MC_ROW07
 
- V_BCM1480_MC_ROW08
 
- V_BCM1480_MC_ROW09
 
- V_BCM1480_MC_ROW10
 
- V_BCM1480_MC_ROW11
 
- V_BCM1480_MC_ROW12
 
- V_BCM1480_MC_ROW13
 
- V_BCM1480_MC_ROW14
 
- V_BCM1480_MC_RTT_BYP_PULLDOWN
 
- V_BCM1480_MC_RTT_BYP_PULLUP
 
- V_BCM1480_MC_SLEW
 
- V_BCM1480_MC_TIMING_DEFAULT
 
- V_BCM1480_MC_tAL
 
- V_BCM1480_MC_tAL_DEFAULT
 
- V_BCM1480_MC_tCL
 
- V_BCM1480_MC_tCL_DEFAULT
 
- V_BCM1480_MC_tCwD
 
- V_BCM1480_MC_tCwD_DEFAULT
 
- V_BCM1480_MC_tFAW
 
- V_BCM1480_MC_tFAW_DEFAULT
 
- V_BCM1480_MC_tFIFO
 
- V_BCM1480_MC_tFIFO_DEFAULT
 
- V_BCM1480_MC_tR2W
 
- V_BCM1480_MC_tR2W_DEFAULT
 
- V_BCM1480_MC_tRAP
 
- V_BCM1480_MC_tRAP_DEFAULT
 
- V_BCM1480_MC_tRCD
 
- V_BCM1480_MC_tRCD_DEFAULT
 
- V_BCM1480_MC_tRCr
 
- V_BCM1480_MC_tRCr_DEFAULT
 
- V_BCM1480_MC_tRCw
 
- V_BCM1480_MC_tRCw_DEFAULT
 
- V_BCM1480_MC_tRFC
 
- V_BCM1480_MC_tRFC_DEFAULT
 
- V_BCM1480_MC_tRP
 
- V_BCM1480_MC_tRP_DEFAULT
 
- V_BCM1480_MC_tRRD
 
- V_BCM1480_MC_tRRD_DEFAULT
 
- V_BCM1480_MC_tRTP
 
- V_BCM1480_MC_tRTP_DEFAULT
 
- V_BCM1480_MC_tW2R
 
- V_BCM1480_MC_tW2R_DEFAULT
 
- V_BCM1480_MC_tW2W
 
- V_BCM1480_MC_tW2W_DEFAULT
 
- V_BCM1480_MC_tWR
 
- V_BCM1480_MC_tWR_DEFAULT
 
- V_BCM1480_SCD_TRACE_CFG_MODE
 
- V_BCM1480_SCD_TRSEQ_SWFUNC
 
- V_BCM1480_SCD_WDOG_RESET_TYPE
 
- V_BCM1480_SPC_CNT_COUNT
 
- V_BCM1480_SYS_BOOT_MODE
 
- V_BCM1480_SYS_CONFIG
 
- V_BCM1480_SYS_NODEID
 
- V_BCM1480_SYS_PLL_DIV
 
- V_BCM1480_SYS_SW_DIV
 
- V_BERT_EN
 
- V_BERT_ERR
 
- V_BERT_INV_DATA
 
- V_BERT_SYNC
 
- V_BERT_SYNC_SRC
 
- V_BIGENDIANINGRESS
 
- V_BISTERR
 
- V_BIT_CNT
 
- V_BKCYC
 
- V_BKS
 
- V_BLANKING
 
- V_BLANKING_HI
 
- V_BLANKING_LO
 
- V_BLANK_END_INDEX
 
- V_BLANK_END_SHADOW_INDEX
 
- V_BLANK_SATRT_SHADOW_INDEX
 
- V_BLANK_START_INDEX
 
- V_BLKRDCTLINT
 
- V_BLKRDFLASHINT
 
- V_BLKRDPLINT
 
- V_BLKWRBOOTINT
 
- V_BLKWRCTLINT
 
- V_BLKWRFLASHINT
 
- V_BLKWRPLINT
 
- V_BOOTADDR
 
- V_BOOTSTRAPPER_END
 
- V_BOOTSTRAPPER_START
 
- V_BOOT_IMAGE_END
 
- V_BOOT_IMAGE_START
 
- V_BORDER
 
- V_BRG_ADDR
 
- V_BRG_CS
 
- V_BRG_CS_SRC
 
- V_BRG_EN
 
- V_BRG_MD
 
- V_BRG_MD0
 
- V_BRG_MD1
 
- V_BRG_MD2
 
- V_BRG_MD3
 
- V_BRG_MD4
 
- V_BRG_MD5
 
- V_BRG_MD6
 
- V_BRG_MD7
 
- V_BRG_RD_SEL0
 
- V_BRG_RD_SEL1
 
- V_BRG_RD_SEL2
 
- V_BRG_RD_SEL3
 
- V_BRG_RD_SEL4
 
- V_BRG_RD_SEL5
 
- V_BRG_RD_SEL6
 
- V_BRG_RD_SEL7
 
- V_BRG_TIM0_CLK
 
- V_BRG_TIM0_IDLE
 
- V_BRG_TIM1_CLK
 
- V_BRG_TIM1_IDLE
 
- V_BRG_TIM2_CLK
 
- V_BRG_TIM2_IDLE
 
- V_BRG_TIM3_CLK
 
- V_BRG_TIM3_IDLE
 
- V_BRG_WR_SEL0
 
- V_BRG_WR_SEL1
 
- V_BRG_WR_SEL2
 
- V_BRG_WR_SEL3
 
- V_BRG_WR_SEL4
 
- V_BRG_WR_SEL5
 
- V_BRG_WR_SEL6
 
- V_BRG_WR_SEL7
 
- V_BUILD
 
- V_BUNDLE_ADDR
 
- V_BUSY
 
- V_BYTECNT
 
- V_BYTETHRESHOLD
 
- V_C4_POL
 
- V_CALBUSY
 
- V_CALENDARLENGTH
 
- V_CALIMP
 
- V_CALRESET
 
- V_CALUPDATE
 
- V_CAL_FAULT
 
- V_CE
 
- V_CEQ_OOO
 
- V_CFG_CQE_SOP_MASK
 
- V_CFG_RR_ARB
 
- V_CFPARERR
 
- V_CF_PARITY_ERR
 
- V_CHAN
 
- V_CHANNEL_ADDR
 
- V_CHBL_SEL
 
- V_CHDRAFULL
 
- V_CHIP_ID
 
- V_CH_DIR
 
- V_CH_DIR0
 
- V_CH_NUM0
 
- V_CH_SEL
 
- V_CIM
 
- V_CIM_FRAMING_ERROR
 
- V_CIM_OP_MAP_PERR
 
- V_CIM_OVFL_ERROR
 
- V_CLEAR_FIN
 
- V_CLIDECEN
 
- V_CLKDIV
 
- V_CLKDIVRESET_
 
- V_CLKEN
 
- V_CLK_ENABLE
 
- V_CLK_OFF
 
- V_CLRSTATS
 
- V_CMCACHEPERR
 
- V_CMDMODE
 
- V_CMDQ0_ENABLE
 
- V_CMDQ0_POINTER
 
- V_CMDQ0_SIZE
 
- V_CMDQ1_ENABLE
 
- V_CMDQ1_POINTER
 
- V_CMDQ1_SIZE
 
- V_CMDQ_PRIORITY
 
- V_CMD_EOP
 
- V_CMD_GEN1
 
- V_CMD_GEN2
 
- V_CMD_LEN
 
- V_CMTIMERMAXNUM
 
- V_CMULOCK
 
- V_CM_MEMMGR_BASE
 
- V_CM_MEMMGR_INIT
 
- V_CM_MEMMGR_MAX_PSTRUCT
 
- V_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE
 
- V_CM_MEMMGR_RX_FREE_LIST_BASE
 
- V_CM_MEMMGR_TX_FREE_LIST_BASE
 
- V_CM_TIMER_BASE
 
- V_COMPEN
 
- V_COMPRESSION_ENABLE
 
- V_CONF_EN
 
- V_CONF_NUM
 
- V_CONF_OFLOW0
 
- V_CONF_OFLOW1
 
- V_CONF_OFLOW2
 
- V_CONF_OFLOW3
 
- V_CONF_OFLOW4
 
- V_CONF_OFLOW5
 
- V_CONF_OFLOW6
 
- V_CONF_OFLOW7
 
- V_CONF_SL
 
- V_CONGMODE
 
- V_CONG_CONTROL_FLAVOR
 
- V_CONN_POLICY
 
- V_CONT
 
- V_CONTEXT
 
- V_CONTEXT_CMD_BUSY
 
- V_CONTEXT_CMD_OPCODE
 
- V_CONTINUOUS
 
- V_COPYALLFRAMES
 
- V_CORRECTABLE_ERROR_COUNT
 
- V_CP115_STANDALONE
 
- V_CPL_ENABLE
 
- V_CPL_OPCODE
 
- V_CPL_STATUS
 
- V_CPL_SWITCH
 
- V_CPL_TX_TNL_LSO_ETHHDRLEN
 
- V_CPPARITYERROR
 
- V_CPU_IDX
 
- V_CPU_INDEX
 
- V_CPU_INDEX_VALID
 
- V_CQ
 
- V_CQCRDTCTRL
 
- V_CQE_GENBIT
 
- V_CQE_OPCODE
 
- V_CQE_QPID
 
- V_CQE_STATUS
 
- V_CQE_SWCQE
 
- V_CQE_TYPE
 
- V_CQ_ARMED
 
- V_CQ_ASYNC_NOTIF
 
- V_CQ_ASYNC_NOTIF_SOL
 
- V_CQ_BASE_HI
 
- V_CQ_CREDIT
 
- V_CQ_CREDITS
 
- V_CQ_CREDIT_THRES
 
- V_CQ_ERR
 
- V_CQ_GEN
 
- V_CQ_INDEX
 
- V_CQ_OVERFLOW_MODE
 
- V_CQ_RSPQ
 
- V_CQ_SIZE
 
- V_CRC_DEF_CRC_INIT
 
- V_CRC_DEF_CRC_POLY
 
- V_CRC_OK
 
- V_CREDITS
 
- V_CRSTWRM
 
- V_CRSTWRMMODE
 
- V_CSM_MD
 
- V_CSPIFRAMINGERROR
 
- V_CSPI_TRAIN_ALPHA
 
- V_CSPI_TRAIN_DATA_MAXT
 
- V_CSUMMARY
 
- V_CTCP_DEF_CRC_TXOR
 
- V_CTCP_DEF_CRC_WIDTH
 
- V_CTCP_DEF_TCPCS_INIT
 
- V_CURRENT_GENERATION_BIT
 
- V_D0_WEIGHT
 
- V_D1_WEIGHT
 
- V_DACK_AUTO_CAREFUL
 
- V_DACK_AUTO_MGMT
 
- V_DACK_BYTE_THRESHOLD
 
- V_DACK_MODE
 
- V_DACK_MSS_SELECTOR
 
- V_DATASELFRAMEERR0
 
- V_DATASELFRAMEERR1
 
- V_DATA_END
 
- V_DATA_FLOW
 
- V_DATA_PATTERN
 
- V_DATA_START
 
- V_DAY
 
- V_DBGIEN
 
- V_DBGIRSPVALID
 
- V_DBGI_ENABLE
 
- V_DBGI_RSP_ERR
 
- V_DBGI_RSP_ERR_REASON
 
- V_DBGI_RSP_HIT
 
- V_DBGI_RSP_VALID
 
- V_DBLSCAN
 
- V_DCACHEPARERR
 
- V_DDA_INC
 
- V_DDP_BUF_COMPLETE
 
- V_DDP_BUF_IDX
 
- V_DDP_BUF_TIMED_OUT
 
- V_DDP_COLOR_ERR
 
- V_DDP_DATACRC_ERR
 
- V_DDP_FC_ENABLE
 
- V_DDP_HDRCRC_ERR
 
- V_DDP_INVALID_PPOD
 
- V_DDP_INVALID_TAG
 
- V_DDP_LLIMIT_ERR
 
- V_DDP_OFFSET
 
- V_DDP_OFFSET_ERR
 
- V_DDP_PADDING_ERR
 
- V_DDP_PDU
 
- V_DDP_PPOD_MISMATCH
 
- V_DDP_PPOD_PARITY_ERR
 
- V_DDP_PSH
 
- V_DDP_STATUS
 
- V_DDP_TID_MISMATCH
 
- V_DDP_ULIMIT_ERR
 
- V_DDP_ULP_MODE
 
- V_DDP_URG
 
- V_DDP_VALID
 
- V_DEFAULT_PEER_MSS
 
- V_DELACK
 
- V_DELACTEMPTY
 
- V_DELAYEDACKRESOLUTION
 
- V_DELAYED_ACK_TIME
 
- V_DELAYED_ACK_TIMER_RESOLUTION
 
- V_DEN
 
- V_DENSITY
 
- V_DETCORECCERR
 
- V_DETPARERR
 
- V_DETUNCECCERR
 
- V_DET_PARITY_ERR
 
- V_DIP2PARITYERR
 
- V_DIP2_COUNT_MODE_ENABLE
 
- V_DIP2_ERR_CNT
 
- V_DIP2_PARITY_ERR_THRES
 
- V_DIP4ERR
 
- V_DIP4ERRORCNT
 
- V_DIP4ERRORCNTSHADOW
 
- V_DIP4_THRES
 
- V_DIP4_THRES_ENABLE
 
- V_DIRECTION
 
- V_DISABLE_CMDQ0_GTS
 
- V_DISABLE_CMDQ1_GTS
 
- V_DISABLE_FL0_GTS
 
- V_DISABLE_FL1_GTS
 
- V_DISABLE_PAST_TIMER_INSERTION
 
- V_DISABLE_RX_FLOW_CONTROL
 
- V_DISBCAST
 
- V_DISBLEDAPARBIT0
 
- V_DISERRFRAMES
 
- V_DISPAUSEFRAMES
 
- V_DISPQPARERR
 
- V_DIS_TX_FILL_WIN_PUSH
 
- V_DLLENB
 
- V_DLLRST
 
- V_DMASTOPEN
 
- V_DMA_ASICXFR_SIZE
 
- V_DMA_DESC_TYPE
 
- V_DMA_DSCRA_A_SIZE
 
- V_DMA_DSCRA_OFFSET
 
- V_DMA_DSCRA_STATUS
 
- V_DMA_DSCRB_A_SIZE
 
- V_DMA_DSCRB_B_SIZE
 
- V_DMA_DSCRB_OPTIONS
 
- V_DMA_DSCRB_PKT_SIZE
 
- V_DMA_DSCRB_PKT_SIZE_MSB
 
- V_DMA_DSCRB_STATUS
 
- V_DMA_ETHRX_PKTTYPE
 
- V_DMA_ETHRX_RXCH
 
- V_DMA_HDR_SIZE
 
- V_DMA_HIGH_WATERMARK
 
- V_DMA_INT_PKTCNT
 
- V_DMA_INT_TIMEOUT
 
- V_DMA_LOW_WATERMARK
 
- V_DMA_RINGSZ
 
- V_DM_CUR_DSCR_DSCR_COUNT
 
- V_DM_DSCRA_DIR_DEST
 
- V_DM_DSCRA_DIR_DEST_CONST
 
- V_DM_DSCRA_DIR_DEST_DECR
 
- V_DM_DSCRA_DIR_DEST_INCR
 
- V_DM_DSCRA_DIR_SRC
 
- V_DM_DSCRA_DIR_SRC_CONST
 
- V_DM_DSCRA_DIR_SRC_DECR
 
- V_DM_DSCRA_DIR_SRC_INCR
 
- V_DM_DSCRB_SRC_LENGTH
 
- V_DM_DSCR_BASE_PRIORITY
 
- V_DM_DSCR_BASE_RINGSZ
 
- V_DM_PARTIAL_CRC_PARTIAL
 
- V_DM_PARTIAL_TCPCS_PARTIAL
 
- V_DOWNSHIFT_CNT
 
- V_DOWNSHIFT_ENABLE
 
- V_DRAMPARERR
 
- V_DROPPKT
 
- V_DROP_TICKS_CNT
 
- V_DTAGPARERR
 
- V_DTMF_EN
 
- V_DTMF_IRQ
 
- V_DTMF_IRQMSK
 
- V_DTMF_RX_CH
 
- V_DTMF_STA
 
- V_DTMF_STOP
 
- V_DUART_BAUD_RATE
 
- V_DUART_BITS_PER_CHAR
 
- V_DUART_BITS_PER_CHAR_7
 
- V_DUART_BITS_PER_CHAR_8
 
- V_DUART_BITS_PER_CHAR_RSV0
 
- V_DUART_BITS_PER_CHAR_RSV1
 
- V_DUART_CHAN_MODE
 
- V_DUART_CHAN_MODE_LCL_LOOP
 
- V_DUART_CHAN_MODE_NORMAL
 
- V_DUART_CHAN_MODE_REM_LOOP
 
- V_DUART_INT_TIME
 
- V_DUART_ISR_RX_A
 
- V_DUART_MISC_CMD
 
- V_DUART_MISC_CMD_NOACTION0
 
- V_DUART_MISC_CMD_NOACTION1
 
- V_DUART_MISC_CMD_NOACTION4
 
- V_DUART_MISC_CMD_RESET_BREAK_INT
 
- V_DUART_MISC_CMD_RESET_RX
 
- V_DUART_MISC_CMD_RESET_TX
 
- V_DUART_MISC_CMD_START_BREAK
 
- V_DUART_MISC_CMD_STOP_BREAK
 
- V_DUART_PARITY_MODE
 
- V_DUART_PARITY_MODE_ADD
 
- V_DUART_PARITY_MODE_ADD_FIXED
 
- V_DUART_PARITY_MODE_NONE
 
- V_DUART_SIG_FULL
 
- V_DUP_THRESH
 
- V_DYNAMIC_DESKEW
 
- V_D_HI
 
- V_D_PRIO
 
- V_E1_LD_STA
 
- V_E1_SET_STA
 
- V_E1_STA
 
- V_ECCCHKEN
 
- V_ECCGENEN
 
- V_ECC_CHECK_ENABLE
 
- V_ECC_GENERATION_ENABLE
 
- V_ECN
 
- V_EC_BASE_HI
 
- V_EC_BASE_LO
 
- V_EC_CREDITS
 
- V_EC_GEN
 
- V_EC_GTS
 
- V_EC_INDEX
 
- V_EC_RESPQ
 
- V_EC_SIZE
 
- V_EC_TYPE
 
- V_EC_UP_TOKEN
 
- V_EC_VALID
 
- V_EGRCNTX
 
- V_EGRESS
 
- V_EGRGENCTRL
 
- V_EGRS_DATA_PAR_ERR
 
- V_ELEMENT0
 
- V_ELEMENT1
 
- V_ELEMENT2
 
- V_ELEMENT3
 
- V_EN1536BFRAMES
 
- V_ENABLEARPMISS
 
- V_ENABLEEPCMDAFULL
 
- V_ENABLEESND
 
- V_ENABLEIPV6RSS
 
- V_ENABLELINKDOWNRST
 
- V_ENABLELINKDWNDRST
 
- V_ENABLENONOFDTNLSYN
 
- V_ENABLEOCSPIFULL
 
- V_ENABLE_BIG_ENDIAN
 
- V_ENABLE_CSPI
 
- V_ENABLE_PCIX
 
- V_ENABLE_TX_DROP
 
- V_ENABLE_TX_ERROR
 
- V_END
 
- V_ENDROPPKT
 
- V_ENFORCEPKT
 
- V_ENHASHMCAST
 
- V_ENJUMBO
 
- V_ENRGMII
 
- V_EN_PLL
 
- V_ERRINTR
 
- V_ERROR_ACK
 
- V_ERR_SIM
 
- V_ESPI_CMD_BUSY
 
- V_ESPI_RX_CORE_RST
 
- V_ESPI_RX_LNK_RST
 
- V_ETRES
 
- V_EV_TS
 
- V_EXCHG_DATA_LI
 
- V_EXP_6_OVER_5
 
- V_EXP_OFF
 
- V_EXT_CLK_SYNC
 
- V_EXT_IRQSTA
 
- V_EXT_IRQ_EN
 
- V_EXT_RAM
 
- V_E_IGNO
 
- V_E_LO
 
- V_F0_LEN
 
- V_F0_NEG
 
- V_FAST_FINWAIT2_TIME
 
- V_FAST_PDU_DELIVERY
 
- V_FATALPERREN
 
- V_FATLPERREN
 
- V_FIFOSTATUSENABLE
 
- V_FIFO_DIR
 
- V_FIFO_IRQ
 
- V_FIFO_LPRIO
 
- V_FIFO_MD
 
- V_FIFO_NUM
 
- V_FIFO_SZ
 
- V_FILTER
 
- V_FINWAIT2_TIME
 
- V_FIRST_FIFO_NUM
 
- V_FIRST_FIRO_DIR
 
- V_FL0EMPTY
 
- V_FL0_ENABLE
 
- V_FL0_POINTER
 
- V_FL0_SIZE
 
- V_FL1_ENABLE
 
- V_FL1_POINTER
 
- V_FL1_SIZE
 
- V_FLASHRANGEINT
 
- V_FLAVORS_VALID
 
- V_FLD_GEN1
 
- V_FLD_GEN2
 
- V_FLEMPTY
 
- V_FLIT_CNT
 
- V_FLMODE
 
- V_FLMRXFLSTEMPTY
 
- V_FLMTXFLSTEMPTY
 
- V_FLPARITYERROR
 
- V_FLSTINITENABLE
 
- V_FL_BASE_HI
 
- V_FL_CONG_THRES
 
- V_FL_ENTRY_SIZE_HI
 
- V_FL_ENTRY_SIZE_LO
 
- V_FL_EXHAUSTED
 
- V_FL_GEN
 
- V_FL_GTS
 
- V_FL_INDEX_HI
 
- V_FL_INDEX_LO
 
- V_FL_SELECTION_CRITERIA
 
- V_FL_SIZE
 
- V_FL_THRESHOLD
 
- V_FORCE_DISABLE_STATUS
 
- V_FOSLIP_RX
 
- V_FOSLIP_TX
 
- V_FREE
 
- V_FREELIST
 
- V_FRONTPORCH
 
- V_FR_IRQSTA
 
- V_FR_PAGE_COUNT
 
- V_FR_PAGE_SIZE
 
- V_FR_PERMS
 
- V_FR_SYNC_E1
 
- V_FR_SYNC_ST
 
- V_FR_TYPE
 
- V_FSM_MD
 
- V_FUNCTION_BEGIN
 
- V_FUNCTION_END
 
- V_FW_RIWR_FLAGS
 
- V_FW_RIWR_GEN
 
- V_FW_RIWR_LEN
 
- V_FW_RIWR_OP
 
- V_FW_RIWR_SOPEOP
 
- V_FW_RIWR_TID
 
- V_FW_VERSION_MAJOR
 
- V_FW_VERSION_MICRO
 
- V_FW_VERSION_MINOR
 
- V_FW_VERSION_TYPE
 
- V_FZ_MD
 
- V_G2_G3
 
- V_G2_G3_EN
 
- V_GENERIC_TIMER_RESOLUTION
 
- V_GIF_ENABLE_MASK
 
- V_GIF_ENABLE_SHIFT
 
- V_GIF_MASK
 
- V_GIF_SHIFT
 
- V_GLOBALENABLE
 
- V_GLOBAL_TIMER_SEPARATOR
 
- V_GLOB_IRQ_EN
 
- V_GPIO0
 
- V_GPIO0_OEN
 
- V_GPIO0_OUT_VAL
 
- V_GPIO1
 
- V_GPIO10
 
- V_GPIO10_OEN
 
- V_GPIO10_OUT_VAL
 
- V_GPIO11
 
- V_GPIO11_OEN
 
- V_GPIO1_OEN
 
- V_GPIO1_OUT_VAL
 
- V_GPIO2
 
- V_GPIO2_OEN
 
- V_GPIO2_OUT_VAL
 
- V_GPIO3
 
- V_GPIO4
 
- V_GPIO4_OEN
 
- V_GPIO4_OUT_VAL
 
- V_GPIO5
 
- V_GPIO5_OEN
 
- V_GPIO5_OUT_VAL
 
- V_GPIO6
 
- V_GPIO6_OEN
 
- V_GPIO6_OUT_VAL
 
- V_GPIO7
 
- V_GPIO7_OEN
 
- V_GPIO7_OUT_VAL
 
- V_GPIO9
 
- V_GPIO_EN0
 
- V_GPIO_EN1
 
- V_GPIO_EN10
 
- V_GPIO_EN11
 
- V_GPIO_EN12
 
- V_GPIO_EN13
 
- V_GPIO_EN14
 
- V_GPIO_EN15
 
- V_GPIO_EN2
 
- V_GPIO_EN3
 
- V_GPIO_EN4
 
- V_GPIO_EN5
 
- V_GPIO_EN6
 
- V_GPIO_EN7
 
- V_GPIO_EN8
 
- V_GPIO_EN9
 
- V_GPIO_IN0
 
- V_GPIO_IN1
 
- V_GPIO_IN10
 
- V_GPIO_IN11
 
- V_GPIO_IN12
 
- V_GPIO_IN13
 
- V_GPIO_IN14
 
- V_GPIO_IN15
 
- V_GPIO_IN2
 
- V_GPIO_IN3
 
- V_GPIO_IN4
 
- V_GPIO_IN5
 
- V_GPIO_IN6
 
- V_GPIO_IN7
 
- V_GPIO_IN8
 
- V_GPIO_IN9
 
- V_GPIO_INTR_ATYPE0
 
- V_GPIO_INTR_ATYPE10
 
- V_GPIO_INTR_ATYPE12
 
- V_GPIO_INTR_ATYPE14
 
- V_GPIO_INTR_ATYPE2
 
- V_GPIO_INTR_ATYPE4
 
- V_GPIO_INTR_ATYPE6
 
- V_GPIO_INTR_ATYPE8
 
- V_GPIO_INTR_ATYPEX
 
- V_GPIO_INTR_TYPE0
 
- V_GPIO_INTR_TYPE10
 
- V_GPIO_INTR_TYPE12
 
- V_GPIO_INTR_TYPE14
 
- V_GPIO_INTR_TYPE2
 
- V_GPIO_INTR_TYPE4
 
- V_GPIO_INTR_TYPE6
 
- V_GPIO_INTR_TYPE8
 
- V_GPIO_INTR_TYPEX
 
- V_GPIO_OUT0
 
- V_GPIO_OUT1
 
- V_GPIO_OUT10
 
- V_GPIO_OUT11
 
- V_GPIO_OUT12
 
- V_GPIO_OUT13
 
- V_GPIO_OUT14
 
- V_GPIO_OUT15
 
- V_GPIO_OUT2
 
- V_GPIO_OUT3
 
- V_GPIO_OUT4
 
- V_GPIO_OUT5
 
- V_GPIO_OUT6
 
- V_GPIO_OUT7
 
- V_GPIO_OUT8
 
- V_GPIO_OUT9
 
- V_GPIO_SEL0
 
- V_GPIO_SEL1
 
- V_GPIO_SEL2
 
- V_GPIO_SEL3
 
- V_GPIO_SEL4
 
- V_GPIO_SEL5
 
- V_GPIO_SEL6
 
- V_GPIO_SEL7
 
- V_GPI_IN0
 
- V_GPI_IN1
 
- V_GPI_IN10
 
- V_GPI_IN11
 
- V_GPI_IN12
 
- V_GPI_IN13
 
- V_GPI_IN14
 
- V_GPI_IN15
 
- V_GPI_IN16
 
- V_GPI_IN17
 
- V_GPI_IN18
 
- V_GPI_IN19
 
- V_GPI_IN2
 
- V_GPI_IN20
 
- V_GPI_IN21
 
- V_GPI_IN22
 
- V_GPI_IN23
 
- V_GPI_IN24
 
- V_GPI_IN25
 
- V_GPI_IN26
 
- V_GPI_IN27
 
- V_GPI_IN28
 
- V_GPI_IN29
 
- V_GPI_IN3
 
- V_GPI_IN30
 
- V_GPI_IN31
 
- V_GPI_IN4
 
- V_GPI_IN5
 
- V_GPI_IN6
 
- V_GPI_IN7
 
- V_GPI_IN8
 
- V_GPI_IN9
 
- V_HARM_SEL
 
- V_HASHTOEPLITZ
 
- V_HCLK
 
- V_HDLC_TRP
 
- V_HEARBEATDACK
 
- V_HELD_FIN_DISABLE
 
- V_HFCRES
 
- V_HICTLDRBDROPERR
 
- V_HIDRBPARITYERROR
 
- V_HIPIODRBDROPERR
 
- V_HIPRIORITYDBEMPTY
 
- V_HIPRIORITYDBFULL
 
- V_HIRCQDRBTHRSH
 
- V_HIRCQPARITYERROR
 
- V_HOSTBUSY
 
- V_HOSTPAGESIZE
 
- V_HPZ0
 
- V_HREG_PAR_ERR
 
- V_I2C_CLKDIV
 
- V_IBQDBGADDR
 
- V_IBQDBGBUSY
 
- V_IBQDBGEN
 
- V_IBQDBGQID
 
- V_IBQDBGWR
 
- V_IBQSGEHIPARERR
 
- V_IBQSGELOPARERR
 
- V_IBQTPPARERR
 
- V_IBQULPPARERR
 
- V_ICACHEPARERR
 
- V_ICR_FR_TIME
 
- V_ICSPI0_FIFO2X_RX_FRAMING_ERROR
 
- V_ICSPI0_RX_FRAMING_ERROR
 
- V_ICSPI0_TX_FRAMING_ERROR
 
- V_ICSPI1_FIFO2X_RX_FRAMING_ERROR
 
- V_ICSPI1_RX_FRAMING_ERROR
 
- V_ICSPI1_TX_FRAMING_ERROR
 
- V_ICSPI_PAR_ERROR
 
- V_IDINDEX
 
- V_IESPI0_FIFO2X_RX_FRAMING_ERROR
 
- V_IESPI0_RX_FRAMING_ERROR
 
- V_IESPI0_TX_FRAMING_ERROR
 
- V_IESPI1_FIFO2X_RX_FRAMING_ERROR
 
- V_IESPI1_RX_FRAMING_ERROR
 
- V_IESPI1_TX_FRAMING_ERROR
 
- V_IESPI_PAR_ERROR
 
- V_IFEN
 
- V_IFF
 
- V_IGN_TPR_MASK
 
- V_IGN_TPR_SHIFT
 
- V_INC_F
 
- V_INFO0
 
- V_INGRS_DATA_PAR_ERR
 
- V_INITIAL_SLOW_START_THRESHOLD
 
- V_INITIAL_SRTT
 
- V_INITRD_START
 
- V_INIT_CONG_WIN
 
- V_INJECT_TIMER
 
- V_INTEL1010MODE
 
- V_INTERFACE
 
- V_INTERFACE_TYPE
 
- V_INTERRUPT_TIMER_COUNT
 
- V_INTRD_END
 
- V_INTR_MASKING_MASK
 
- V_INTR_MASKING_SHIFT
 
- V_INTR_PRIO_MASK
 
- V_INTR_PRIO_SHIFT
 
- V_INT_DIR
 
- V_INT_LDT_INTDEST
 
- V_INT_LDT_INTMSG
 
- V_INT_LDT_VECTOR
 
- V_INVERSION_CONTROL
 
- V_INVERSION_LINE
 
- V_INVERSION_PIXEL
 
- V_INV_CLK
 
- V_INV_DATA
 
- V_IO_ALE_TO_CS
 
- V_IO_ALE_TO_WRITE
 
- V_IO_ALE_WIDTH
 
- V_IO_BURST_WIDTH
 
- V_IO_CS_TO_OE
 
- V_IO_CS_WIDTH
 
- V_IO_DRV_A
 
- V_IO_DRV_B
 
- V_IO_DRV_C
 
- V_IO_DRV_D
 
- V_IO_DRV_E
 
- V_IO_DRV_F
 
- V_IO_DRV_G
 
- V_IO_DRV_H
 
- V_IO_DRV_J
 
- V_IO_DRV_K
 
- V_IO_DRV_L
 
- V_IO_DRV_M
 
- V_IO_DRV_N
 
- V_IO_DRV_P
 
- V_IO_DRV_Q
 
- V_IO_DRV_R
 
- V_IO_IDLE_CYCLE
 
- V_IO_MULT_SIZE
 
- V_IO_OE_TO_CS
 
- V_IO_RDY_SMPLE
 
- V_IO_SLEW0
 
- V_IO_SLEW1
 
- V_IO_SLEW2
 
- V_IO_SLEW3
 
- V_IO_START_ADDR
 
- V_IO_TIMEOUT
 
- V_IO_WIDTH_SEL
 
- V_IO_WRITE_WIDTH
 
- V_IPATS0
 
- V_IPATS1
 
- V_IPATS2
 
- V_IPCHECKSUMOFFLOAD
 
- V_IPTTL
 
- V_IPV6ENABLE
 
- V_IP_CSUM
 
- V_IP_FRAGMENT_DROP
 
- V_IP_ID_SPLIT
 
- V_IP_TTL
 
- V_IRPARITYERROR
 
- V_IRQ
 
- V_IRQ1S
 
- V_IRQ1S_MSK
 
- V_IRQ_FIFO0_RX
 
- V_IRQ_FIFO0_TX
 
- V_IRQ_FIFO10_RX
 
- V_IRQ_FIFO10_TX
 
- V_IRQ_FIFO11_RX
 
- V_IRQ_FIFO11_TX
 
- V_IRQ_FIFO12_RX
 
- V_IRQ_FIFO12_TX
 
- V_IRQ_FIFO13_RX
 
- V_IRQ_FIFO13_TX
 
- V_IRQ_FIFO14_RX
 
- V_IRQ_FIFO14_TX
 
- V_IRQ_FIFO15_RX
 
- V_IRQ_FIFO15_TX
 
- V_IRQ_FIFO16_RX
 
- V_IRQ_FIFO16_TX
 
- V_IRQ_FIFO17_RX
 
- V_IRQ_FIFO17_TX
 
- V_IRQ_FIFO18_RX
 
- V_IRQ_FIFO18_TX
 
- V_IRQ_FIFO19_RX
 
- V_IRQ_FIFO19_TX
 
- V_IRQ_FIFO1_RX
 
- V_IRQ_FIFO1_TX
 
- V_IRQ_FIFO20_RX
 
- V_IRQ_FIFO20_TX
 
- V_IRQ_FIFO21_RX
 
- V_IRQ_FIFO21_TX
 
- V_IRQ_FIFO22_RX
 
- V_IRQ_FIFO22_TX
 
- V_IRQ_FIFO23_RX
 
- V_IRQ_FIFO23_TX
 
- V_IRQ_FIFO24_RX
 
- V_IRQ_FIFO24_TX
 
- V_IRQ_FIFO25_RX
 
- V_IRQ_FIFO25_TX
 
- V_IRQ_FIFO26_RX
 
- V_IRQ_FIFO26_TX
 
- V_IRQ_FIFO27_RX
 
- V_IRQ_FIFO27_TX
 
- V_IRQ_FIFO28_RX
 
- V_IRQ_FIFO28_TX
 
- V_IRQ_FIFO29_RX
 
- V_IRQ_FIFO29_TX
 
- V_IRQ_FIFO2_RX
 
- V_IRQ_FIFO2_TX
 
- V_IRQ_FIFO30_RX
 
- V_IRQ_FIFO30_TX
 
- V_IRQ_FIFO31_RX
 
- V_IRQ_FIFO31_TX
 
- V_IRQ_FIFO3_RX
 
- V_IRQ_FIFO3_TX
 
- V_IRQ_FIFO4_RX
 
- V_IRQ_FIFO4_TX
 
- V_IRQ_FIFO5_RX
 
- V_IRQ_FIFO5_TX
 
- V_IRQ_FIFO6_RX
 
- V_IRQ_FIFO6_TX
 
- V_IRQ_FIFO7_RX
 
- V_IRQ_FIFO7_TX
 
- V_IRQ_FIFO8_RX
 
- V_IRQ_FIFO8_TX
 
- V_IRQ_FIFO9_RX
 
- V_IRQ_FIFO9_TX
 
- V_IRQ_FIFO_BL0
 
- V_IRQ_FIFO_BL1
 
- V_IRQ_FIFO_BL2
 
- V_IRQ_FIFO_BL3
 
- V_IRQ_FIFO_BL4
 
- V_IRQ_FIFO_BL5
 
- V_IRQ_FIFO_BL6
 
- V_IRQ_FIFO_BL7
 
- V_IRQ_MASK
 
- V_IRQ_POL
 
- V_IRQ_PROC
 
- V_IRQ_SEL
 
- V_IRQ_SHIFT
 
- V_ISCSICOALESCING
 
- V_ISCSI_COALESCE
 
- V_ISCSI_DDP
 
- V_ISCSI_PDU_LEN
 
- V_ITAGPARERR
 
- V_ITPARITYERROR
 
- V_JATT_OFF
 
- V_KEEPALIVEMAX
 
- V_KEEPALIVE_MAX
 
- V_KEEP_ALIVE
 
- V_KEEP_ALIVE_IDLE_TIME
 
- V_KEEP_ALIVE_INTERVAL_TIME
 
- V_L2C_MGMT_ECC_DIAG
 
- V_L2C_MGMT_INDEX
 
- V_L2C_MGMT_QUADRANT
 
- V_L2C_MGMT_TAG
 
- V_L2C_MGMT_WAY
 
- V_L2C_MISC_NO_WAY
 
- V_L2C_TAG_ECC
 
- V_L2C_TAG_INDEX
 
- V_L2C_TAG_TAG
 
- V_L2C_TAG_WAY
 
- V_L2T_IDX
 
- V_L2T_IDX16
 
- V_L2T_R_IFF
 
- V_L2T_R_PRIO
 
- V_L2T_R_VLAN
 
- V_L2T_STATUS
 
- V_L2T_W_IDX
 
- V_L2T_W_IFF
 
- V_L2T_W_PRIO
 
- V_L2T_W_VLAN
 
- V_L3_VALUE
 
- V_LAST_VAR
 
- V_LDT_ADDSTATUS_TGTDONE
 
- V_LDT_CLASSREV_CLASS
 
- V_LDT_CLASSREV_REV
 
- V_LDT_CMD_CAPTYPE
 
- V_LDT_DEVHDR_BIST
 
- V_LDT_DEVHDR_CLINESZ
 
- V_LDT_DEVHDR_HDRTYPE
 
- V_LDT_DEVHDR_LATTMR
 
- V_LDT_DEVICEID_DEVICEID
 
- V_LDT_DEVICEID_VENDOR
 
- V_LDT_LINKCTRL_CRCERR
 
- V_LDT_LINKCTRL_MAXIN
 
- V_LDT_LINKCTRL_MAXOUT
 
- V_LDT_LINKCTRL_WIDTHIN
 
- V_LDT_LINKCTRL_WIDTHOUT
 
- V_LDT_LINKFREQ_FREQ
 
- V_LDT_SRICMD_RXMARGIN
 
- V_LDT_SRICMD_TXINITIALOFFSET
 
- V_LDT_SRICTRL_BUFRELSPACE
 
- V_LDT_SRICTRL_NEEDNPREQ
 
- V_LDT_SRICTRL_NEEDPREQ
 
- V_LDT_SRICTRL_NEEDRESP
 
- V_LDT_SRICTRL_WANTNPREQ
 
- V_LDT_SRICTRL_WANTPREQ
 
- V_LDT_SRICTRL_WANTRESP
 
- V_LDT_STATUS_DEVSELTIMING
 
- V_LDT_TXBUFCNT_NPCMD
 
- V_LDT_TXBUFCNT_NPDATA
 
- V_LDT_TXBUFCNT_PCMD
 
- V_LDT_TXBUFCNT_PDATA
 
- V_LDT_TXBUFCNT_RCMD
 
- V_LDT_TXBUFCNT_RDATA
 
- V_LEARN_RESPONSE_LATENCY
 
- V_LINKFAULTCHANGE
 
- V_LOCAL_FUNC
 
- V_LOCAL_IP_RAM_ADDR
 
- V_LOCKTID
 
- V_LOCTLDRBDROPERR
 
- V_LODRBPARITYERROR
 
- V_LOOP_FIFO
 
- V_LOPIODRBDROPERR
 
- V_LOPRIORITYDBEMPTY
 
- V_LOPRIORITYDBFULL
 
- V_LORCQDRBTHRSH
 
- V_LORCQPARITYERROR
 
- V_LOST_STA
 
- V_LOWSIG0
 
- V_LRNLAT
 
- V_LRNVEREN
 
- V_LSO_ETH_TYPE
 
- V_LSO_IPHDR_WORDS
 
- V_LSO_IPV6
 
- V_LSO_MSS
 
- V_LSO_TCPHDR_WORDS
 
- V_MAC_BACKOFF_SEL
 
- V_MAC_BYPASS_CFG
 
- V_MAC_BYPASS_IFG
 
- V_MAC_COUNTER_ADDR
 
- V_MAC_ENC_FC_THRSH
 
- V_MAC_FC_CMD
 
- V_MAC_FC_CMD_DISABLED
 
- V_MAC_FC_CMD_ENABLED
 
- V_MAC_FC_CMD_ENAB_FALSECARR
 
- V_MAC_HALF_DUPLEX
 
- V_MAC_HD_FC_ENABLE
 
- V_MAC_IFG_RX
 
- V_MAC_IFG_RX_10
 
- V_MAC_IFG_RX_100
 
- V_MAC_IFG_RX_1000
 
- V_MAC_IFG_THRSH
 
- V_MAC_IFG_THRSH_10
 
- V_MAC_IFG_THRSH_100
 
- V_MAC_IFG_THRSH_1000
 
- V_MAC_IFG_TX
 
- V_MAC_IFG_TX_10
 
- V_MAC_IFG_TX_100
 
- V_MAC_IFG_TX_1000
 
- V_MAC_IFS1
 
- V_MAC_IFS2
 
- V_MAC_IPHDR_OFFSET
 
- V_MAC_ISL_ENABLE
 
- V_MAC_JUMBO_ENABLE
 
- V_MAC_LB_ENABLE
 
- V_MAC_LFSR_SEED
 
- V_MAC_LWM_ENABLE
 
- V_MAC_MAGIC_PKT_ENABLE
 
- V_MAC_MATCH
 
- V_MAC_MATCH_VALID
 
- V_MAC_MAX_FRAMESZ
 
- V_MAC_MAX_FRAMESZ_DEFAULT
 
- V_MAC_MAX_FRAMESZ_JUMBO
 
- V_MAC_MC_ENABLE
 
- V_MAC_MIN_FRAMESZ
 
- V_MAC_MIN_FRAMESZ_DEFAULT
 
- V_MAC_MIN_FRAMESZ_FIFO
 
- V_MAC_PRE_LEN
 
- V_MAC_PROMISC
 
- V_MAC_RESET
 
- V_MAC_RESET_
 
- V_MAC_RX_CH_MSN_SEL
 
- V_MAC_RX_CH_SEL
 
- V_MAC_RX_CRC_ENABLE
 
- V_MAC_RX_CRC_OFFSET
 
- V_MAC_RX_ENABLE
 
- V_MAC_RX_EOP_COUNTER
 
- V_MAC_RX_PAD_ENABLE
 
- V_MAC_RX_PAUSE_ENABLE
 
- V_MAC_RX_PKT_OFFSET
 
- V_MAC_RX_PL_THRSH
 
- V_MAC_RX_RDPTR
 
- V_MAC_RX_RD_THRSH
 
- V_MAC_RX_RL_THRSH
 
- V_MAC_RX_WRPTR
 
- V_MAC_SLOT_SIZE
 
- V_MAC_SLOT_SIZE_10
 
- V_MAC_SLOT_SIZE_100
 
- V_MAC_SLOT_SIZE_1000
 
- V_MAC_SPEED
 
- V_MAC_SPEED_SEL
 
- V_MAC_SPEED_SEL_1000MBPS
 
- V_MAC_SPEED_SEL_100MBPS
 
- V_MAC_SPEED_SEL_10MBPS
 
- V_MAC_SPEED_SEL_RESERVED
 
- V_MAC_TXD_WEIGHT0
 
- V_MAC_TXD_WEIGHT1
 
- V_MAC_TX_CRC_OFFSET
 
- V_MAC_TX_ENABLE
 
- V_MAC_TX_EOP_COUNTER
 
- V_MAC_TX_PAUSE_CNT
 
- V_MAC_TX_PAUSE_CNT_16K
 
- V_MAC_TX_PAUSE_CNT_1K
 
- V_MAC_TX_PAUSE_CNT_2K
 
- V_MAC_TX_PAUSE_CNT_32K
 
- V_MAC_TX_PAUSE_CNT_4K
 
- V_MAC_TX_PAUSE_CNT_512
 
- V_MAC_TX_PAUSE_CNT_64K
 
- V_MAC_TX_PAUSE_CNT_8K
 
- V_MAC_TX_PAUSE_ENABLE
 
- V_MAC_TX_PKT_OFFSET
 
- V_MAC_TX_RDPTR
 
- V_MAC_TX_RD_THRSH
 
- V_MAC_TX_RL_THRSH
 
- V_MAC_TX_WRPTR
 
- V_MAC_TX_WR_THRSH
 
- V_MAC_VLAN_TAG
 
- V_MASTER_DLL_LOCKED
 
- V_MASTER_DLL_MAX_TAP_COUNT
 
- V_MASTER_DLL_RESET
 
- V_MASTER_DLL_TAP_COUNT
 
- V_MASTER_DLL_TAP_COUNT_OFFSET
 
- V_MASTER_PARITY_ERR
 
- V_MAXBURST1
 
- V_MAXBURST2
 
- V_MAXRXDATA
 
- V_MAXTRAINALPHA
 
- V_MAXTRAINDATA
 
- V_MAX_RATE
 
- V_MAX_REORDER_FRAGMENTS
 
- V_MAX_RETRANS
 
- V_MAX_RETRANS_OVERRIDE
 
- V_MAX_RX_SIZE
 
- V_MBUSEN
 
- V_MC3_ADDR_ERR
 
- V_MC3_BANK_CYCLE
 
- V_MC3_CE_ADDR
 
- V_MC3_CORR_ERR
 
- V_MC3_EXTENDED_MODE
 
- V_MC3_MODE
 
- V_MC3_PARITY_ERR
 
- V_MC3_SLOW
 
- V_MC3_UE_ADDR
 
- V_MC3_UNCORR_ERR
 
- V_MC3_WIDTH
 
- V_MC4A_SLOW
 
- V_MC4A_WIDTH
 
- V_MC4_ADDR_ERR
 
- V_MC4_BACK_DOOR_ADDR
 
- V_MC4_BANK_CYCLE
 
- V_MC4_CE_ADDR
 
- V_MC4_CORR_ERR
 
- V_MC4_EXTENDED_MODE
 
- V_MC4_MODE
 
- V_MC4_NARROW
 
- V_MC4_SLOW
 
- V_MC4_UE_ADDR
 
- V_MC4_UNCORR_ERR
 
- V_MC5A
 
- V_MC5_INT_ACTIVE_REGION_FULL
 
- V_MC5_INT_DEL_ACT_EMPTY
 
- V_MC5_INT_DISPATCHQ_PARITY_ERR
 
- V_MC5_INT_HIT_IN_ACTIVE_REGION_ERR
 
- V_MC5_INT_HIT_IN_RT_REGION_ERR
 
- V_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR
 
- V_MC5_INT_LIP0_ERR
 
- V_MC5_INT_LIP_MISS_ERR
 
- V_MC5_INT_MISS_ERR
 
- V_MC5_INT_NFA_SRCH_ERR
 
- V_MC5_INT_PARITY_ERR
 
- V_MC5_INT_REQUESTQ_PARITY_ERR
 
- V_MC5_INT_SYN_COOKIE
 
- V_MC5_INT_SYN_COOKIE_BAD
 
- V_MC5_INT_SYN_COOKIE_OFF
 
- V_MC5_INT_UNKNOWN_CMD
 
- V_MC7_CM
 
- V_MC7_PMRX
 
- V_MC7_PMTX
 
- V_MCAPARERR
 
- V_MCAPARERRENB
 
- V_MC_ADDR_DRIVE
 
- V_MC_ADDR_DRIVE_DEFAULT
 
- V_MC_ADDR_SKEW
 
- V_MC_ADDR_SKEW_DEFAULT
 
- V_MC_AGE_LIMIT
 
- V_MC_AGE_LIMIT_DEFAULT
 
- V_MC_BANK0_MAP
 
- V_MC_BANK0_MAP_DEFAULT
 
- V_MC_BANK1_MAP
 
- V_MC_BANK1_MAP_DEFAULT
 
- V_MC_BANK2_MAP
 
- V_MC_BANK2_MAP_DEFAULT
 
- V_MC_BANK3_MAP
 
- V_MC_BANK3_MAP_DEFAULT
 
- V_MC_BA_SELECT
 
- V_MC_CAS_SELECT
 
- V_MC_CHANNEL_SEL
 
- V_MC_CLKCONFIG_DEFAULT
 
- V_MC_CLK_RATIO
 
- V_MC_CLK_RATIO_25X
 
- V_MC_CLK_RATIO_2X
 
- V_MC_CLK_RATIO_35X
 
- V_MC_CLK_RATIO_3X
 
- V_MC_CLK_RATIO_45X
 
- V_MC_CLK_RATIO_4X
 
- V_MC_CLK_RATIO_DEFAULT
 
- V_MC_CLOCK_DRIVE
 
- V_MC_CLOCK_DRIVE_DEFAULT
 
- V_MC_COMMAND
 
- V_MC_COMMAND_AR
 
- V_MC_COMMAND_CLRPWRDN
 
- V_MC_COMMAND_CLRRFSH
 
- V_MC_COMMAND_EMRS
 
- V_MC_COMMAND_MRS
 
- V_MC_COMMAND_PRE
 
- V_MC_COMMAND_SETPWRDN
 
- V_MC_COMMAND_SETRFSH
 
- V_MC_CONFIG_DEFAULT
 
- V_MC_CS0_END
 
- V_MC_CS0_PAGE
 
- V_MC_CS0_START
 
- V_MC_CS1_END
 
- V_MC_CS1_PAGE
 
- V_MC_CS1_START
 
- V_MC_CS2_END
 
- V_MC_CS2_PAGE
 
- V_MC_CS2_START
 
- V_MC_CS3_END
 
- V_MC_CS3_PAGE
 
- V_MC_CS3_START
 
- V_MC_CS_MODE
 
- V_MC_CS_MODE_INTLV_CS
 
- V_MC_CS_MODE_MIXED_CS_10
 
- V_MC_CS_MODE_MIXED_CS_30
 
- V_MC_CS_MODE_MIXED_CS_32
 
- V_MC_CS_MODE_MSB_CS
 
- V_MC_DATA_DRIVE
 
- V_MC_DATA_DRIVE_DEFAULT
 
- V_MC_DLL_DEFAULT
 
- V_MC_DLL_DEFAULT_DEFAULT
 
- V_MC_DQI_SKEW
 
- V_MC_DQI_SKEW_DEFAULT
 
- V_MC_DQO_SKEW
 
- V_MC_DQO_SKEW_DEFAULT
 
- V_MC_DRAM_TYPE
 
- V_MC_DRAM_TYPE_FCRAM
 
- V_MC_DRAM_TYPE_JEDEC
 
- V_MC_DRAM_TYPE_SGRAM
 
- V_MC_EMODE
 
- V_MC_EMODE_DEFAULT
 
- V_MC_INTERLEAVE
 
- V_MC_MODE
 
- V_MC_MODE_DEFAULT
 
- V_MC_QUEUE_SIZE
 
- V_MC_QUEUE_SIZE_DEFAULT
 
- V_MC_RAS_SELECT
 
- V_MC_REF_RATE
 
- V_MC_REF_RATE_100MHz
 
- V_MC_REF_RATE_133MHz
 
- V_MC_REF_RATE_200MHz
 
- V_MC_REF_RATE_DEFAULT
 
- V_MC_TIMING_DEFAULT
 
- V_MC_WR_LIMIT
 
- V_MC_WR_LIMIT_DEFAULT
 
- V_MC_tCrD
 
- V_MC_tCrD_DEFAULT
 
- V_MC_tCwCr
 
- V_MC_tCwCr_DEFAULT
 
- V_MC_tCwD
 
- V_MC_tCwD_DEFAULT
 
- V_MC_tFIFO
 
- V_MC_tFIFO_DEFAULT
 
- V_MC_tRCD
 
- V_MC_tRCD_DEFAULT
 
- V_MC_tRCr
 
- V_MC_tRCr_DEFAULT
 
- V_MC_tRCw
 
- V_MC_tRCw_DEFAULT
 
- V_MC_tRFC
 
- V_MC_tRFC_DEFAULT
 
- V_MC_tRP
 
- V_MC_tRP_DEFAULT
 
- V_MC_tRRD
 
- V_MC_tRRD_DEFAULT
 
- V_MDIEN
 
- V_MDIINV
 
- V_MDI_OP
 
- V_MFA_STA
 
- V_MF_RESYNC
 
- V_MF_RX_RDY
 
- V_MF_TX_RDY
 
- V_MI0_BUSY
 
- V_MI0_CLK_CNT
 
- V_MI0_CLK_DIV
 
- V_MI0_CSR_POLL
 
- V_MI0_INTR_ENABLE
 
- V_MI0_MDIO
 
- V_MI0_PHY_ADDR
 
- V_MI0_PHY_REG_ADDR
 
- V_MI0_PREAMBLE
 
- V_MI1_ADDR_AUTOINC
 
- V_MI1_CLK_DIV
 
- V_MI1_DATA
 
- V_MI1_MDI_ENABLE
 
- V_MI1_MDI_INVERT
 
- V_MI1_OP
 
- V_MI1_OP_BUSY
 
- V_MI1_PHY_ADDR
 
- V_MI1_PREAMBLE_ENABLE
 
- V_MI1_REG_ADDR
 
- V_MI1_SOF
 
- V_MIN_RATE
 
- V_MISC_IRQSTA
 
- V_MIX_IRQ
 
- V_MODE
 
- V_MODULATEUNIONMODE
 
- V_MODULATION_TIMER_SEPARATOR
 
- V_MODULE_ADDR
 
- V_MONITORED_DIRECTION
 
- V_MONITORED_INTERFACE
 
- V_MONITORED_PORT_NUM
 
- V_MONTH
 
- V_MPS0
 
- V_MSIXPARERR
 
- V_MSS
 
- V_MSSTHRESHOLD
 
- V_MSS_IDX
 
- V_MSTDETPARERR
 
- V_MTUDEFAULT
 
- V_MTUENABLE
 
- V_MULT_ST
 
- V_MV78230
 
- V_MV78230_PLUS
 
- V_MV78260
 
- V_MV78260_PLUS
 
- V_MV78460
 
- V_M_BUS_ENABLE
 
- V_NAGLE
 
- V_NEG_CLK
 
- V_NEG_E
 
- V_NEWINDEX
 
- V_NEWTIMER
 
- V_NEXT_FIFO_DIR
 
- V_NEXT_FIFO_NUM
 
- V_NFASRCHFAIL
 
- V_NICMODE
 
- V_NOISE_SUPPR
 
- V_NO_CONG
 
- V_NO_INSYNC
 
- V_NO_MF_SYNC
 
- V_NO_OFFLOAD
 
- V_NO_REPLY
 
- V_NTRI
 
- V_NUMFSTTRNSEQ
 
- V_NUMFSTTRNSEQRX
 
- V_NUM_LIP
 
- V_NUM_PKTS_DROPPED
 
- V_OBQSGEPARERR
 
- V_OBQULPHIPARERR
 
- V_OBQULPLOPARERR
 
- V_OCPARITYERROR
 
- V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR
 
- V_OCSPI0_RX_FRAMING_ERROR
 
- V_OCSPI0_TX_FRAMING_ERROR
 
- V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR
 
- V_OCSPI1_RX_FRAMING_ERROR
 
- V_OCSPI1_TX_FRAMING_ERROR
 
- V_OCSPI_PAR_ERROR
 
- V_ODEC_CON
 
- V_OESPI0_OFIFO2X_TX_FRAMING_ERROR
 
- V_OESPI0_RX_FRAMING_ERROR
 
- V_OESPI0_TX_FRAMING_ERROR
 
- V_OESPI1_OFIFO2X_TX_FRAMING_ERROR
 
- V_OESPI1_RX_FRAMING_ERROR
 
- V_OESPI1_TX_FRAMING_ERROR
 
- V_OESPI_PAR_ERROR
 
- V_OFF
 
- V_OFFLOAD_DISABLE
 
- V_OFFSET
 
- V_ONEINTMULTQ
 
- V_OP
 
- V_OPCODE
 
- V_OPERATION
 
- V_OPTONEINTMULTQ
 
- V_ORG
 
- V_ORGANIZATION
 
- V_OUT_EN
 
- V_OUT_OF_SYNC_COUNT
 
- V_PACING_FLAVOR
 
- V_PACKET_MISMATCH
 
- V_PACKET_TOO_BIG
 
- V_PARAM_SHIFT
 
- V_PARERRDATA
 
- V_PARERRPCMD
 
- V_PARITYERR
 
- V_PARITY_ENABLE
 
- V_PARLAT
 
- V_PASS_OPEN_TID
 
- V_PASS_OPEN_TOS
 
- V_PATHMTU
 
- V_PATH_MTU
 
- V_PAT_SEQ
 
- V_PBL_BOUND_ERR_CH0
 
- V_PBL_BOUND_ERR_CH1
 
- V_PCIE_CFPARERR
 
- V_PCIE_CLIDECEN
 
- V_PCIE_DMASTOPEN
 
- V_PCIE_MSIXPARERR
 
- V_PCIE_PIOPARERR
 
- V_PCIE_RFPARERR
 
- V_PCIE_WFPARERR
 
- V_PCIM0
 
- V_PCIXINITPAT
 
- V_PCI_MODE_64BIT
 
- V_PCI_MODE_66MHZ
 
- V_PCI_MODE_CLK
 
- V_PCI_MODE_PCIX
 
- V_PCI_MODE_PCIX_INITPAT
 
- V_PCLKRANGE
 
- V_PCMCIA_MODE
 
- V_PCMDMUXPERR
 
- V_PCMRES
 
- V_PCM_ADDR
 
- V_PCM_CLK
 
- V_PCM_DR
 
- V_PCM_LOOP
 
- V_PCM_MD
 
- V_PCM_SYNC
 
- V_PCS_RESET_
 
- V_PE
 
- V_PERREFEN
 
- V_PERSHIFTBACKOFFMAX
 
- V_PERSHIFTMAX
 
- V_PERSIST_TIMER_MAX
 
- V_PERSIST_TIMER_MIN
 
- V_PEXERR
 
- V_PHYADDR
 
- V_PING_DROP
 
- V_PIOPARERR
 
- V_PIO_PARITY_ERR
 
- V_PKTSHIFT
 
- V_PKT_TYPE
 
- V_PLAYING
 
- V_PLL_ADJ
 
- V_PL_INTR_CSPI
 
- V_PL_INTR_ESPI
 
- V_PL_INTR_EXT
 
- V_PL_INTR_MC3
 
- V_PL_INTR_MC4
 
- V_PL_INTR_MC5
 
- V_PL_INTR_PCIX
 
- V_PL_INTR_RAT
 
- V_PL_INTR_SGE_DATA
 
- V_PL_INTR_SGE_ERR
 
- V_PL_INTR_TP
 
- V_PL_INTR_ULP
 
- V_PM1_RX
 
- V_PM1_TX
 
- V_PMMAXXFERLEN0
 
- V_PMMAXXFERLEN1
 
- V_PM_C2E_EMPTY_ERR
 
- V_PM_C2E_SYNC_ERR
 
- V_PM_C2E_WRT_FULL
 
- V_PM_E2C_EMPTY_ERR
 
- V_PM_E2C_SYNC_ERR
 
- V_PM_E2C_WRT_FULL
 
- V_PM_INTR
 
- V_PM_PAR_ERR
 
- V_PNP_IRQ
 
- V_PORT0ACTIVE
 
- V_PORT1ACTIVE
 
- V_PORTSPEED
 
- V_POSITION
 
- V_POVEREN
 
- V_POWER_UP
 
- V_PRECHARGE_CYCLE
 
- V_PRECYC
 
- V_PREEN
 
- V_PREREFDIV
 
- V_PRESCALED_SIZE
 
- V_PROC
 
- V_PROC_IRQMSK
 
- V_PROGRESS
 
- V_PROTECT_MODE
 
- V_PRTYEN
 
- V_PSCR_MDI_XOVER_MODE
 
- V_PSSR_CABLE_LEN
 
- V_PSSR_DOWNSHIFT_STATUS
 
- V_PSSR_DUPLEX
 
- V_PSSR_ENERGY_DETECT
 
- V_PSSR_JABBER
 
- V_PSSR_LINK
 
- V_PSSR_MDI
 
- V_PSSR_PAGE_RECEIVED
 
- V_PSSR_POLARITY
 
- V_PSSR_RX_PAUSE
 
- V_PSSR_SPEED
 
- V_PSSR_STATUS_RESOLVED
 
- V_PSSR_TX_PAUSE
 
- V_PULSE2_INT
 
- V_PULSE3_INT
 
- V_PWM0_16KHZ
 
- V_PWM0_MD
 
- V_PWM1_16KHZ
 
- V_PWM1_MD
 
- V_PWRDN0
 
- V_PWRDN1
 
- V_PWRDN2
 
- V_PWRDN3
 
- V_QOS_MAPPING
 
- V_RAMPARITYERR
 
- V_RAM_ADDR2
 
- V_RAM_SZ
 
- V_RAM_WRITE_ENABLE
 
- V_RCPARITYERROR
 
- V_RCVMSTABT
 
- V_RCVSPLCMPERR
 
- V_RCVTARABT
 
- V_RCV_BUFSIZ
 
- V_RCV_MASTER_ABORT
 
- V_RCV_TARGET_ABORT
 
- V_RDLAT
 
- V_RDMA_ERR_ENABLE
 
- V_RDTOWRDLY
 
- V_RDY
 
- V_READY
 
- V_READ_DATA
 
- V_READ_TO_WRITE_DELAY
 
- V_RECEIVE_BUFFER_SIZE
 
- V_REFCYC
 
- V_REFRESH_CYCLE
 
- V_REFRESH_DIVISOR
 
- V_REFRESH_ENABLE
 
- V_REGADDR
 
- V_REGISTER_OFFSET
 
- V_REG_M
 
- V_REG_N
 
- V_RELEASED
 
- V_REPLAYLMT
 
- V_REQQPARERR
 
- V_RESET0
 
- V_RESET1
 
- V_RESET2
 
- V_RESET3
 
- V_RESETPLL01
 
- V_RESETPLL23
 
- V_RESPONSEQ
 
- V_RESPONSE_QUEUE_ENABLE
 
- V_RESPQ_CREDIT
 
- V_RESPQ_EXHAUSTED
 
- V_RESPQ_OVERFLOW
 
- V_RESPQ_SIZE
 
- V_RESYNC
 
- V_RES_F
 
- V_RES_LOST
 
- V_RES_NMF
 
- V_RETRANSMISSION_MAX
 
- V_RETRANSMIT_TIMER_MAX
 
- V_RETRANSMIT_TIMER_MIN
 
- V_RETRYBUFPARERR
 
- V_RETRYLUTPARERR
 
- V_REV
 
- V_REWRITEFORCETOSIZE
 
- V_RFPARERR
 
- V_RF_PARITY_ERR
 
- V_RGMIIIMPPD
 
- V_RGMIIIMPPU
 
- V_RGMII_RESET_
 
- V_RLD_EPR
 
- V_RMFCS
 
- V_ROUND_ROBIN
 
- V_ROUTE_TABLE_INDEX
 
- V_ROUTING
 
- V_RQFEEDBACKENABLE
 
- V_RQ_GEN
 
- V_RQ_INTR_EN
 
- V_RQ_MSI_VEC
 
- V_RRCPLCPUSIZE
 
- V_RRCPLMAPEN
 
- V_RSPD_ASYNC_NOTIF
 
- V_RSPD_EOP
 
- V_RSPD_FL0_GTS
 
- V_RSPD_FL1_GTS
 
- V_RSPD_FLQ
 
- V_RSPD_GEN1
 
- V_RSPD_GEN2
 
- V_RSPD_IMM_DATA_VALID
 
- V_RSPD_INR_VEC
 
- V_RSPD_LEN
 
- V_RSPD_OFFLOAD
 
- V_RSPD_SOP
 
- V_RSPD_TXQ0_CR
 
- V_RSPD_TXQ0_GTS
 
- V_RSPD_TXQ1_CR
 
- V_RSPD_TXQ1_GTS
 
- V_RSPD_TXQ2_CR
 
- V_RSPD_TXQ2_GTS
 
- V_RSPQ
 
- V_RSPQCREDITOVERFOW
 
- V_RSPQDISABLED
 
- V_RSS_ENABLE
 
- V_RSS_MASK_LEN
 
- V_RSTMAX
 
- V_RST_DTMF
 
- V_RSVDSPACEINT
 
- V_RTE_READ_REQ_SELECT
 
- V_RTE_REQ_LUT_BASE
 
- V_RTE_REQ_LUT_IX
 
- V_RTE_WRITE_REQ_LUT_BASE
 
- V_RTE_WRITE_REQ_LUT_IX
 
- V_RTR_TYPE
 
- V_RTTVAR_INIT
 
- V_RXCOALESCEENABLE
 
- V_RXCOALESCEPSHEN
 
- V_RXCOALESCESIZE
 
- V_RXCONGESTIONMODE
 
- V_RXDDPOFFINIT
 
- V_RXDROP
 
- V_RXEN
 
- V_RXENABLE
 
- V_RXENDIANMODE
 
- V_RXENFRAMER
 
- V_RXFBARBPRIO
 
- V_RXFIFOOVERFLOW
 
- V_RXFIFOPARITYERROR
 
- V_RXFIFOPAUSEHWM
 
- V_RXFIFOPAUSELWM
 
- V_RXFIFO_EMPTY
 
- V_RXFIFO_OVERFLOW
 
- V_RXFIFO_PRTY_ERR
 
- V_RXMAXFRAMERSIZE
 
- V_RXMAXPKTSIZE
 
- V_RXOVERFLOW
 
- V_RXPARERR
 
- V_RXPORT0DROPCNT
 
- V_RXPORT1DROPCNT
 
- V_RXPORT2DROPCNT
 
- V_RXPORT3DROPCNT
 
- V_RXSTATUSENABLE
 
- V_RXSTRFRWRD
 
- V_RXTPPARERR
 
- V_RXTPPARERRENB
 
- V_RXTSHIFTMAXR1
 
- V_RXTSHIFTMAXR2
 
- V_RX_CLK_STATUS
 
- V_RX_CMI
 
- V_RX_COALESCE
 
- V_RX_COALESCE_SIZE
 
- V_RX_COALESCE_VALID
 
- V_RX_COALESCING_ENABLE
 
- V_RX_COALESCING_PSH_DELIVER
 
- V_RX_CODE
 
- V_RX_CREDITS
 
- V_RX_DACK_CHANGE
 
- V_RX_DACK_MODE
 
- V_RX_E1
 
- V_RX_E2
 
- V_RX_EOMF
 
- V_RX_EOMF_MSK
 
- V_RX_FBAUD
 
- V_RX_FC_DISABLE
 
- V_RX_FC_VALID
 
- V_RX_FORCE_ACK
 
- V_RX_FREE_LIST_EMPTY
 
- V_RX_INIT
 
- V_RX_INV_CLK
 
- V_RX_INV_CMI
 
- V_RX_INV_DATA
 
- V_RX_MF
 
- V_RX_MF_SYNC
 
- V_RX_MODULATE
 
- V_RX_NPORTS
 
- V_RX_PKT_OFFSET
 
- V_RX_SL0_RAM
 
- V_RX_STA
 
- V_RX_SZ
 
- V_R_REQ_FRAMINGERROR
 
- V_SA6_IRQ
 
- V_SA6_IRQMSK
 
- V_SACK
 
- V_SACKMODE
 
- V_SACKRX
 
- V_SACK_ALGORITHM
 
- V_SADRSEL
 
- V_SCD_BERR_DCODE
 
- V_SCD_BERR_RID
 
- V_SCD_BERR_TID
 
- V_SCD_L2ECC_BAD_D
 
- V_SCD_L2ECC_BAD_T
 
- V_SCD_L2ECC_CORR_D
 
- V_SCD_L2ECC_CORR_T
 
- V_SCD_MEM_BUSERR
 
- V_SCD_MEM_ECC_BAD
 
- V_SCD_MEM_ECC_CORR
 
- V_SCD_TIMER_CNT
 
- V_SCD_TIMER_FREQ
 
- V_SCD_TIMER_INIT
 
- V_SCD_TIMER_WIDTH
 
- V_SCD_TRACE_CFG_CUR_ADDR
 
- V_SCD_TREVT_ADDR_MATCH
 
- V_SCD_TREVT_COUNT
 
- V_SCD_TREVT_DATAID
 
- V_SCD_TREVT_REQID
 
- V_SCD_TREVT_RESPID
 
- V_SCD_TRSEQ_EVENT1
 
- V_SCD_TRSEQ_EVENT2
 
- V_SCD_TRSEQ_EVENT3
 
- V_SCD_TRSEQ_EVENT4
 
- V_SCD_TRSEQ_FUNCTION
 
- V_SCD_TRSEQ_FUNC_FREEZE
 
- V_SCD_TRSEQ_FUNC_NOP
 
- V_SCD_TRSEQ_FUNC_START
 
- V_SCD_TRSEQ_FUNC_STOP
 
- V_SCD_WDOG_FREQ
 
- V_SCD_WDOG_RESET_TYPE
 
- V_SCHTOKEN0
 
- V_SCHTOKEN1
 
- V_SCHTOKEN2
 
- V_SCHTOKEN3
 
- V_SCI_MSK_ST0
 
- V_SCI_MSK_ST1
 
- V_SCI_MSK_ST2
 
- V_SCI_MSK_ST3
 
- V_SCI_MSK_ST4
 
- V_SCI_MSK_ST5
 
- V_SCI_MSK_ST6
 
- V_SCI_MSK_ST7
 
- V_SCI_ST0
 
- V_SCI_ST1
 
- V_SCI_ST2
 
- V_SCI_ST3
 
- V_SCI_ST4
 
- V_SCI_ST5
 
- V_SCI_ST6
 
- V_SCI_ST7
 
- V_SDRAMRANGEINT
 
- V_SEARCH_RESPONSE_LATENCY
 
- V_SEL
 
- V_SELEGRCNTX
 
- V_SEQ_END
 
- V_SERDESRESET_
 
- V_SERDES_LOS
 
- V_SET_ACTIVE_MODE_BC12_CDP
 
- V_SET_ACTIVE_MODE_BC12_DCP
 
- V_SET_ACTIVE_MODE_BC12_SDP
 
- V_SET_ACTIVE_MODE_DEDICATED
 
- V_SET_ACTIVE_MODE_MASK
 
- V_SET_ACTIVE_MODE_PASSTHROUGH
 
- V_SET_G2_G3
 
- V_SGE3
 
- V_SGEFRAMINGERROR
 
- V_SGE_FRAMING_ERROR
 
- V_SGLWRFLASHINT
 
- V_SGL_CAL_EN
 
- V_SHIFT_VAL
 
- V_SH_SEL0
 
- V_SH_SEL1
 
- V_SH_SEL2
 
- V_SH_SEL3
 
- V_SH_SEL4
 
- V_SH_SEL5
 
- V_SH_SEL6
 
- V_SH_SEL7
 
- V_SIGSYSERR
 
- V_SIGTARABT
 
- V_SIG_LOS
 
- V_SIG_SYS_ERR
 
- V_SIG_TARGET_ABORT
 
- V_SILENT
 
- V_SIZE
 
- V_SIZE_HI
 
- V_SIZE_LO
 
- V_SI_FAS
 
- V_SI_NFAS
 
- V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT
 
- V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE
 
- V_SLAVE_DELAY_LINE_TAP_COUNT
 
- V_SLAVE_DLL_DELTA
 
- V_SLAVE_DLL_RESET
 
- V_SLEEPING
 
- V_SLIP_RX
 
- V_SLIP_TX
 
- V_SLOW
 
- V_SLOW_RD
 
- V_SL_DIR
 
- V_SL_NUM
 
- V_SL_SEL0
 
- V_SL_SEL1
 
- V_SL_SEL2
 
- V_SL_SEL3
 
- V_SL_SEL4
 
- V_SL_SEL5
 
- V_SL_SEL6
 
- V_SL_SEL7
 
- V_SMB_ADDR
 
- V_SMB_AFMT
 
- V_SMB_AFMT_ADDR
 
- V_SMB_AFMT_ADDR_CMD1BYTE
 
- V_SMB_AFMT_ADDR_CMD2BYTE
 
- V_SMB_AFMT_NONE
 
- V_SMB_CMD
 
- V_SMB_CMDH
 
- V_SMB_DATA_IN
 
- V_SMB_DATA_OUT
 
- V_SMB_DFMT
 
- V_SMB_DFMT_1BYTE
 
- V_SMB_DFMT_2BYTE
 
- V_SMB_DFMT_3BYTE
 
- V_SMB_DFMT_4BYTE
 
- V_SMB_DFMT_CMD4BYTE
 
- V_SMB_DFMT_CMD5BYTE
 
- V_SMB_DFMT_NODATA
 
- V_SMB_DFMT_RESERVED
 
- V_SMB_FREQ_DIV
 
- V_SMB_LB
 
- V_SMB_MB
 
- V_SMB_REF
 
- V_SMB_SCL_IN
 
- V_SMB_TT
 
- V_SMB_TT_CMD_RD1BYTE
 
- V_SMB_TT_CMD_RD2BYTE
 
- V_SMB_TT_EEPROMREAD
 
- V_SMB_TT_QUICKCMD
 
- V_SMB_TT_RD1BYTE
 
- V_SMB_TT_WR1BYTE
 
- V_SMB_TT_WR2BYTE
 
- V_SMB_TT_WR3BYTE
 
- V_SPC_CFG_SRC0
 
- V_SPC_CFG_SRC1
 
- V_SPC_CFG_SRC2
 
- V_SPC_CFG_SRC3
 
- V_SPC_CFG_SRC4
 
- V_SPC_CFG_SRC5
 
- V_SPC_CFG_SRC6
 
- V_SPC_CFG_SRC7
 
- V_SPEC_MB
 
- V_SPI4_COMMAND
 
- V_SPLCMPDIS
 
- V_SQ_EN
 
- V_SRCHLAT
 
- V_SRC_MAC_SEL
 
- V_SRES
 
- V_SRTT_GAIN
 
- V_ST
 
- V_START
 
- V_START_BIT
 
- V_START_OF_ROUTING_TABLE
 
- V_START_OF_SERVER_INDEX
 
- V_STA_IRQ
 
- V_STA_IRQMSK
 
- V_STRES
 
- V_ST_ACT
 
- V_ST_CK_DLY
 
- V_ST_CLK
 
- V_ST_D_RX
 
- V_ST_D_TX
 
- V_ST_E_RX
 
- V_ST_LD_STA
 
- V_ST_MD
 
- V_ST_SEL
 
- V_ST_SET_STA
 
- V_ST_SMPL
 
- V_ST_SQ
 
- V_ST_STA
 
- V_ST_STOP
 
- V_ST_TRIS
 
- V_SWORD_COND
 
- V_SYNCSER_FLAG_NUM
 
- V_SYNCSER_RXSYNC_DLY
 
- V_SYNCSER_SEQ_COUNT
 
- V_SYNCSER_TXSYNC_DLY
 
- V_SYNC_E1_RX
 
- V_SYNC_END_INDEX
 
- V_SYNC_END_SHADOW_INDEX
 
- V_SYNC_IN
 
- V_SYNC_LOSS
 
- V_SYNC_OFFS
 
- V_SYNC_OFFSET
 
- V_SYNC_OFFSET_HI
 
- V_SYNC_OFFSET_LO
 
- V_SYNC_OUT
 
- V_SYNC_PLL
 
- V_SYNC_RQD
 
- V_SYNC_SATRT_SHADOW_INDEX
 
- V_SYNC_SEL
 
- V_SYNC_SRC
 
- V_SYNC_START_INDEX
 
- V_SYNC_WIDTH
 
- V_SYNC_WIDTH_HI
 
- V_SYNC_WIDTH_LO
 
- V_SYNSHIFTMAX
 
- V_SYN_COOKIE_ALGORITHM
 
- V_SYN_COOKIE_PARAMETER
 
- V_SYN_DEFENSE
 
- V_SYN_ISSUE_MODE
 
- V_SYN_MAX
 
- V_SYS_BIN
 
- V_SYS_BOOT_MODE
 
- V_SYS_CLKCOUNT
 
- V_SYS_CONFIG
 
- V_SYS_L2C_SIZE
 
- V_SYS_NUM_CPUS
 
- V_SYS_PART
 
- V_SYS_PLL_DIV
 
- V_SYS_REVISION
 
- V_SYS_SOC_TYPE
 
- V_SYS_WAFERID1_200
 
- V_SYS_WAFERID2_200
 
- V_SYS_WAFERID_300
 
- V_SYS_WID
 
- V_SYS_XPOS
 
- V_SYS_YPOS
 
- V_T3A_ACKLAT
 
- V_T3A_ENABLEESND
 
- V_T3DBG
 
- V_TABLELATENCYDELTA
 
- V_TAHOE_ENABLE
 
- V_TCAM_BYPASS
 
- V_TCAM_PART_CNT
 
- V_TCAM_PART_SIZE
 
- V_TCAM_PART_TYPE
 
- V_TCAM_PART_TYPE_HI
 
- V_TCAM_READY
 
- V_TCAM_RESET
 
- V_TCAM_SERVER_REGION_USAGE
 
- V_TCB_CPU_NO
 
- V_TCB_CQ_IDX_RQ
 
- V_TCB_CQ_IDX_SQ
 
- V_TCB_CRC_ENABLE
 
- V_TCB_DACK_TIMER
 
- V_TCB_DDP_RDMAP_VERSION
 
- V_TCB_DEL_FLAG
 
- V_TCB_DIP
 
- V_TCB_DP
 
- V_TCB_INB_READ_PERM
 
- V_TCB_INB_WRITE_PERM
 
- V_TCB_IRS_ULP
 
- V_TCB_ISS_ULP
 
- V_TCB_L2T_IX
 
- V_TCB_MARKER_ENABLE_RX
 
- V_TCB_MARKER_ENABLE_TX
 
- V_TCB_MAX_RT
 
- V_TCB_NEWRENO_RECOVER
 
- V_TCB_ORD_L_BIT_VLD
 
- V_TCB_PDU_HAVE_LEN
 
- V_TCB_PDU_HDR_LEN
 
- V_TCB_PDU_LEN
 
- V_TCB_PD_ID
 
- V_TCB_QP_ID
 
- V_TCB_RCV_ADV
 
- V_TCB_RCV_NXT
 
- V_TCB_RCV_SCALE
 
- V_TCB_RCV_WND
 
- V_TCB_RDMAP_OPCODE
 
- V_TCB_RQ_MAX_OFFSET
 
- V_TCB_RQ_MSN
 
- V_TCB_RQ_START
 
- V_TCB_RQ_WRITE_PTR
 
- V_TCB_RX_COMPACT
 
- V_TCB_RX_DDP_BUF0_LEN
 
- V_TCB_RX_DDP_BUF0_OFFSET
 
- V_TCB_RX_DDP_BUF0_TAG
 
- V_TCB_RX_DDP_BUF1_LEN
 
- V_TCB_RX_DDP_BUF1_OFFSET
 
- V_TCB_RX_DDP_BUF1_TAG
 
- V_TCB_RX_DDP_FLAGS
 
- V_TCB_RX_FRAG0_LEN
 
- V_TCB_RX_FRAG0_START_IDX_RAW
 
- V_TCB_RX_FRAG1_LEN
 
- V_TCB_RX_FRAG1_PTR_RAW
 
- V_TCB_RX_FRAG1_PTR_RAW2
 
- V_TCB_RX_FRAG1_START_IDX_OFFSET
 
- V_TCB_RX_FRAG2_LEN_RAW
 
- V_TCB_RX_FRAG2_PTR_RAW
 
- V_TCB_RX_FRAG2_START_IDX_OFFSET_RAW
 
- V_TCB_RX_FRAG3_LEN_RAW
 
- V_TCB_RX_FRAG3_PTR_RAW
 
- V_TCB_RX_FRAG3_START_IDX_OFFSET_RAW
 
- V_TCB_RX_HDR_OFFSET
 
- V_TCB_RX_PTR_RAW
 
- V_TCB_RX_QUIESCE
 
- V_TCB_SIP
 
- V_TCB_SLUSH1
 
- V_TCB_SLUSH_AUX2
 
- V_TCB_SLUSH_AUX3
 
- V_TCB_SMAC_SEL
 
- V_TCB_SND_CWND
 
- V_TCB_SND_MAX_RAW
 
- V_TCB_SND_NXT_RAW
 
- V_TCB_SND_SCALE
 
- V_TCB_SND_SSTHRESH
 
- V_TCB_SND_UNA_RAW
 
- V_TCB_SP
 
- V_TCB_STAG
 
- V_TCB_TIMER
 
- V_TCB_TIMESTAMP
 
- V_TCB_TIMESTAMP_OFFSET
 
- V_TCB_TOS
 
- V_TCB_TS_LAST_ACK_SENT_RAW
 
- V_TCB_TX_COMPACT
 
- V_TCB_TX_FLUSH
 
- V_TCB_TX_HDR_PTR_RAW
 
- V_TCB_TX_LAST_PTR_RAW
 
- V_TCB_TX_MAX
 
- V_TCB_TX_OOS_RXMT
 
- V_TCB_TX_OOS_TXMT
 
- V_TCB_TX_PDU_LEN
 
- V_TCB_TX_PDU_OUT
 
- V_TCB_T_DUPACKS
 
- V_TCB_T_FLAGS1
 
- V_TCB_T_FLAGS2
 
- V_TCB_T_MAXSEG
 
- V_TCB_T_MIGRATION
 
- V_TCB_T_RTSEQ_RECENT
 
- V_TCB_T_RTTVAR
 
- V_TCB_T_RTT_TS_RECENT_AGE
 
- V_TCB_T_RXTSHIFT
 
- V_TCB_T_SRTT
 
- V_TCB_T_STATE
 
- V_TCB_ULP_RAW
 
- V_TCB_ULP_TYPE
 
- V_TCPCHECKSUMOFFLOAD
 
- V_TCP_CSUM
 
- V_TERM150
 
- V_TERM_TID
 
- V_TF_ACTIVE_OPEN
 
- V_TF_ASK_MODE
 
- V_TF_CCTRL_SEL0
 
- V_TF_CCTRL_SEL1
 
- V_TF_CORE_FIN
 
- V_TF_CORE_MORE
 
- V_TF_CORE_PUSH
 
- V_TF_CORE_URG
 
- V_TF_DACK
 
- V_TF_DACK_MSS
 
- V_TF_DUPACK_COUNT_ODD
 
- V_TF_HALF_CLOSE
 
- V_TF_KEEPALIVE
 
- V_TF_MIGRATING
 
- V_TF_MOD_SCHD
 
- V_TF_MOD_SCHD_REASON0
 
- V_TF_MOD_SCHD_REASON1
 
- V_TF_MOD_SCHD_RX
 
- V_TF_NAGLE
 
- V_TF_NON_OFFLOAD
 
- V_TF_PEER_FIN_HELD
 
- V_TF_RCV_COALESCE_ENABLE
 
- V_TF_RCV_COALESCE_HEARTBEAT
 
- V_TF_RCV_COALESCE_LAST_PSH
 
- V_TF_RCV_COALESCE_PUSH
 
- V_TF_RDMA_ERROR
 
- V_TF_RDMA_FLM_ERROR
 
- V_TF_RECV_SACK
 
- V_TF_RECV_SCALE
 
- V_TF_RECV_TSTMP
 
- V_TF_RX_CHANNEL
 
- V_TF_RX_FLOW_CONTROL_DISABLE
 
- V_TF_SSWS_DISABLED
 
- V_TF_TCAM_BYPASS
 
- V_TF_TCP_NEWRENO_FAST_RECOVERY
 
- V_TF_TURBO
 
- V_TF_TX_CHANNEL
 
- V_TF_TX_PACE_AUTO
 
- V_TF_TX_PACE_FIXED
 
- V_THRESHOLD
 
- V_TI2_EXP
 
- V_TIMEOUT
 
- V_TIMERRESOLUTION
 
- V_TIMESTAMP
 
- V_TIMESTAMPRESOLUTION
 
- V_TIMESTAMPSMODE
 
- V_TI_IRQ
 
- V_TI_IRQMSK
 
- V_TMMODE
 
- V_TMPARTSIZE
 
- V_TMRDY
 
- V_TMRST
 
- V_TMTYPE
 
- V_TMTYPEHI
 
- V_TNL2TUPEN
 
- V_TNL4TUPEN
 
- V_TNLFLMODE
 
- V_TNLLKPEN
 
- V_TNLMAPEN
 
- V_TNLPRTEN
 
- V_TOS
 
- V_TOTAL
 
- V_TOTAL_INDEX
 
- V_TOTAL_SHADOW_INDEX
 
- V_TP1
 
- V_TPFRAMINGERROR
 
- V_TPIPAR
 
- V_TPIRDY
 
- V_TPIWR
 
- V_TPI_ADDRESS
 
- V_TPRESET
 
- V_TPRXPORTEN
 
- V_TPR_MASK
 
- V_TPTXPORT0EN
 
- V_TPTXPORT1EN
 
- V_TPT_ADDR_TYPE
 
- V_TPT_MW_BIND_ENABLE
 
- V_TPT_PAGE_SIZE
 
- V_TPT_PBL_ADDR
 
- V_TPT_PBL_SIZE
 
- V_TPT_PDID
 
- V_TPT_PERM
 
- V_TPT_PSTAG
 
- V_TPT_QPID
 
- V_TPT_REM_INV_DIS
 
- V_TPT_STAG_KEY
 
- V_TPT_STAG_STATE
 
- V_TPT_STAG_TYPE
 
- V_TPT_VALID
 
- V_TP_ACCESS_LATENCY
 
- V_TP_FRAMING_ERROR
 
- V_TP_IN_CSPI_CHECK_IP_CSUM
 
- V_TP_IN_CSPI_CHECK_TCP_CSUM
 
- V_TP_IN_CSPI_CPL
 
- V_TP_IN_CSPI_ETHERNET
 
- V_TP_IN_CSPI_POS
 
- V_TP_IN_CSPI_TUNNEL
 
- V_TP_IN_ESPI_CHECK_IP_CSUM
 
- V_TP_IN_ESPI_CHECK_TCP_CSUM
 
- V_TP_IN_ESPI_CPL
 
- V_TP_IN_ESPI_ETHERNET
 
- V_TP_IN_ESPI_POS
 
- V_TP_IN_ESPI_TUNNEL
 
- V_TP_OUT_CSPI_CPL
 
- V_TP_OUT_CSPI_GENERATE_IP_CSUM
 
- V_TP_OUT_CSPI_GENERATE_TCP_CSUM
 
- V_TP_OUT_CSPI_POS
 
- V_TP_OUT_C_ETH
 
- V_TP_OUT_ESPI_CPL
 
- V_TP_OUT_ESPI_ETHERNET
 
- V_TP_OUT_ESPI_GENERATE_IP_CSUM
 
- V_TP_OUT_ESPI_GENERATE_TCP_CSUM
 
- V_TP_OUT_ESPI_POS
 
- V_TP_OUT_ESPI_TAG_ETHERNET
 
- V_TP_PC_REV
 
- V_TP_RESET
 
- V_TP_VERSION_MAJOR
 
- V_TP_VERSION_MICRO
 
- V_TP_VERSION_MINOR
 
- V_TRANSACTION_TIMER
 
- V_TRICN_RX_TRAINING
 
- V_TRICN_RX_TRAIN_ERR
 
- V_TRICN_RX_TRAIN_OK
 
- V_TRP_FAS
 
- V_TRP_IRQ
 
- V_TRP_NFAS
 
- V_TRP_RAL
 
- V_TRP_SA
 
- V_TRP_SL0
 
- V_TX0TPPARERR
 
- V_TX0TPPARERRENB
 
- V_TX1TPPARERR
 
- V_TX1TPPARERRENB
 
- V_TXACTENABLE
 
- V_TXCONGESTIONMODE
 
- V_TXDATAACKIDX
 
- V_TXDEFERENABLE
 
- V_TXDROP
 
- V_TXDROPCNTCH0RCVD
 
- V_TXDROPENABLE
 
- V_TXEN
 
- V_TXENABLE
 
- V_TXENDIANMODE
 
- V_TXFBARBPRIO
 
- V_TXFIFOPARITYERROR
 
- V_TXFIFOTHRESH
 
- V_TXFIFO_PRTY_ERR
 
- V_TXFIFO_UNDERRUN
 
- V_TXF_READ_THRESHOLD
 
- V_TXF_WRITE_THRESHOLD
 
- V_TXIPG
 
- V_TXPACEAUTO
 
- V_TXPACEAUTOSTRICT
 
- V_TXPACEFIXED
 
- V_TXPACINGENABLE
 
- V_TXPARERR
 
- V_TXPAUSEEN
 
- V_TXPKT_INTF
 
- V_TXPKT_IPCSUM_DIS
 
- V_TXPKT_L4CSUM_DIS
 
- V_TXPKT_LOOPBACK
 
- V_TXPKT_OPCODE
 
- V_TXPKT_VLAN
 
- V_TXPKT_VLAN_VLD
 
- V_TXPORT0DROPCNT
 
- V_TXPORT1DROPCNT
 
- V_TXPORT2DROPCNT
 
- V_TXPORT3DROPCNT
 
- V_TXSPI4SOPCNT
 
- V_TXTOSQUEUEMAPMODE
 
- V_TX_ACK_PAGES
 
- V_TX_CHANNEL
 
- V_TX_CLOSE
 
- V_TX_CMI_CODE
 
- V_TX_CODE
 
- V_TX_CPU_IDX
 
- V_TX_E
 
- V_TX_E1
 
- V_TX_E2
 
- V_TX_EN
 
- V_TX_EOMF
 
- V_TX_EOMF_MSK
 
- V_TX_FAS
 
- V_TX_FBAUD
 
- V_TX_FREE_LIST_EMPTY
 
- V_TX_IMM_ACK
 
- V_TX_IMM_DMA
 
- V_TX_INIT
 
- V_TX_INV_CLK
 
- V_TX_INV_CMI_CODE
 
- V_TX_INV_DATA
 
- V_TX_LI
 
- V_TX_MF
 
- V_TX_MOD_QUEUE_REQ_MAP
 
- V_TX_MORE
 
- V_TX_MSS
 
- V_TX_NFAS
 
- V_TX_NPORTS
 
- V_TX_PORT
 
- V_TX_QOS
 
- V_TX_RAL
 
- V_TX_SA
 
- V_TX_SHOVE
 
- V_TX_SL0_RAM
 
- V_TX_SNDBUF
 
- V_TX_SZ
 
- V_TX_ULP_MODE
 
- V_TX_ULP_SUBMODE
 
- V_TX_URG
 
- V_TYPECFG_TYPE0
 
- V_TYPECFG_TYPE1
 
- V_TYPECFG_TYPE2
 
- V_TYPECFG_TYPE3
 
- V_UC_REQ_FRAMINGERROR
 
- V_UDPCHECKSUMOFFLOAD
 
- V_UDP_CSUM
 
- V_UE
 
- V_ULAW
 
- V_ULAW_SEL
 
- V_ULP2_RX
 
- V_ULP2_TX
 
- V_ULPTX_CMD
 
- V_ULPTX_NFLITS
 
- V_ULP_MEMIO_ADDR
 
- V_ULP_MEMIO_DATA_LEN
 
- V_ULP_MEMIO_LOCK
 
- V_ULP_MODE
 
- V_UNCORRECTABLE_ERROR_COUNT
 
- V_UNDERUNFIX
 
- V_UNKNOWNCMD
 
- V_UNMAPPED_ERR
 
- V_UNREGISTERED
 
- V_UNXSPLCMP
 
- V_UNXSPLCPLERRC
 
- V_UNXSPLCPLERRR
 
- V_USERSPACESIZE
 
- V_USE_ROUTE_TABLE
 
- V_VAR_GAIN
 
- V_VAR_MULT
 
- V_VLAN_PRI
 
- V_VLAN_PRI_VALID
 
- V_VLAN_XTRACT
 
- V_VPD_ADDR
 
- V_VPD_OP_FLAG
 
- V_VWVEREN
 
- V_WD_RES
 
- V_WD_TS
 
- V_WFPARERR
 
- V_WF_PARITY_ERR
 
- V_WIDTH
 
- V_WIDTH_1
 
- V_WIDTH_10
 
- V_WIDTH_12
 
- V_WIDTH_14
 
- V_WIDTH_2
 
- V_WIDTH_4
 
- V_WIDTH_6
 
- V_WIDTH_8
 
- V_WINDOWPROBE_MAX
 
- V_WINDOWSCALEMODE
 
- V_WINDOW_SCALE
 
- V_WND_SCALE
 
- V_WRBLKFLASHINT
 
- V_WRITE_BURST_SIZE
 
- V_WRITE_DATA
 
- V_WRITE_RECOVERY_DELAY
 
- V_WRITE_TO_READ_DELAY
 
- V_WRTORDDLY
 
- V_WR_BCNTLFLT
 
- V_WR_COMPL
 
- V_WR_CR_FLUSH
 
- V_WR_DATATYPE
 
- V_WR_EOP
 
- V_WR_GEN
 
- V_WR_LEN
 
- V_WR_OP
 
- V_WR_SGE_CREDITS
 
- V_WR_SGLSFLT
 
- V_WR_SOP
 
- V_WR_TID
 
- V_XAUIIMP
 
- V_XAUIPCSALIGNCHANGE
 
- V_XAUIPCSCTCERR
 
- V_XCRC_SYNC
 
- V_XG2G_RESET_
 
- V_XGMAC0_0
 
- V_XGMAC0_1
 
- V_XGMAC_STOP_EN
 
- V_XGM_CALFAULT
 
- V_XGM_IMPSETUPDATE
 
- V_XGM_INT
 
- V_XS12_ON
 
- V_XS15_ON
 
- V_ZEROROUTEERROR
 
- V_ZERO_C_CMD_ERROR
 
- V_ZERO_E_CMD_ERROR
 
- V_ZERO_SWITCH_ERROR
 
- Val_Ratio
 
- ValidCnt
 
- Valid_Max
 
- Valid_Min
 
- Value
 
- Variable_shift_double
 
- Variableshiftdouble
 
- Vbbase_Colkey
 
- Vbbase_Glalpha
 
- Vbi
 
- VceBootLevel
 
- VceBootLevel_MASK
 
- VceBootLevel_SHIFT
 
- Vcmsk_colkey_m
 
- VddgfxSavedRegisters
 
- Vega10_I2CLineID
 
- Vega10_I2CLineID_DDC1
 
- Vega10_I2CLineID_DDC2
 
- Vega10_I2CLineID_DDC3
 
- Vega10_I2CLineID_DDC4
 
- Vega10_I2CLineID_DDC5
 
- Vega10_I2CLineID_DDC6
 
- Vega10_I2CLineID_DDCVGA
 
- Vega10_I2CLineID_SCLSDA
 
- Vega10_I2C_DDC1CLK
 
- Vega10_I2C_DDC1DATA
 
- Vega10_I2C_DDC2CLK
 
- Vega10_I2C_DDC2DATA
 
- Vega10_I2C_DDC3CLK
 
- Vega10_I2C_DDC3DATA
 
- Vega10_I2C_DDC4CLK
 
- Vega10_I2C_DDC4DATA
 
- Vega10_I2C_DDC5CLK
 
- Vega10_I2C_DDC5DATA
 
- Vega10_I2C_DDC6CLK
 
- Vega10_I2C_DDC6DATA
 
- Vega10_I2C_DDCVGACLK
 
- Vega10_I2C_DDCVGADATA
 
- Vega10_I2C_SCL
 
- Vega10_I2C_SDA
 
- Vega10_PPTable_Generic_SubTable_Header
 
- Vega12_I2CLineID
 
- Vega12_I2CLineID_DDC1
 
- Vega12_I2CLineID_DDC2
 
- Vega12_I2CLineID_DDC3
 
- Vega12_I2CLineID_DDC4
 
- Vega12_I2CLineID_DDC5
 
- Vega12_I2CLineID_DDC6
 
- Vega12_I2CLineID_DDCVGA
 
- Vega12_I2CLineID_SCLSDA
 
- Vega12_I2C_DDC1CLK
 
- Vega12_I2C_DDC1DATA
 
- Vega12_I2C_DDC2CLK
 
- Vega12_I2C_DDC2DATA
 
- Vega12_I2C_DDC3CLK
 
- Vega12_I2C_DDC3DATA
 
- Vega12_I2C_DDC4CLK
 
- Vega12_I2C_DDC4DATA
 
- Vega12_I2C_DDC5CLK
 
- Vega12_I2C_DDC5DATA
 
- Vega12_I2C_DDC6CLK
 
- Vega12_I2C_DDC6DATA
 
- Vega12_I2C_DDCVGACLK
 
- Vega12_I2C_DDCVGADATA
 
- Vega12_I2C_SCL
 
- Vega12_I2C_SDA
 
- VertStretch
 
- VerticalRetraceWait
 
- VeryLowRSSI
 
- Vi_set
 
- ViceIoctl
 
- VideoFormatAuto
 
- VideoFormatAuto27MHz
 
- VideoFormatNTSC
 
- VideoFormatNTSC27MHz
 
- VideoFormatNTSC443
 
- VideoFormatNTSC44327MHz
 
- VideoFormatNTSCJapan
 
- VideoFormatNTSCJapan27MHz
 
- VideoFormatPAL
 
- VideoFormatPAL27MHz
 
- VideoFormatPAL60
 
- VideoFormatPAL6027MHz
 
- VideoFormatPALB
 
- VideoFormatPALB27MHz
 
- VideoFormatPALBDGHI
 
- VideoFormatPALBDGHI27MHz
 
- VideoFormatPALD
 
- VideoFormatPALD27MHz
 
- VideoFormatPALG
 
- VideoFormatPALG27MHz
 
- VideoFormatPALH
 
- VideoFormatPALH27MHz
 
- VideoFormatPALI
 
- VideoFormatPALI27MHz
 
- VideoFormatPALM
 
- VideoFormatPALM27MHz
 
- VideoFormatPALN
 
- VideoFormatPALN27MHz
 
- VideoFormatPALNC
 
- VideoFormatPALNC27MHz
 
- VideoFormatSECAM
 
- VideoFormatSECAM27MHz
 
- VideoInputComposite
 
- VideoInputMux0
 
- VideoInputMux1
 
- VideoInputMux2
 
- VideoInputMux3
 
- VideoInputOther
 
- VideoInputSVideo
 
- VideoInputTuner
 
- VideoPES
 
- VideoPID
 
- VideoSenseDataOffset
 
- VideoState1
 
- VideoState2
 
- VideoState3
 
- ViewQuestM318B
 
- ViewQuestVQ110
 
- Viking_12
 
- Viking_2x
 
- Viking_30
 
- Viking_35
 
- Viking_new
 
- VirtDevice
 
- VirtTarget
 
- VirtualJumpers
 
- Vit01
 
- Vit02
 
- Vit03
 
- Vit04
 
- Vit05
 
- Vit06
 
- Vit07
 
- Vit08
 
- Vit09
 
- Vit10
 
- Vit11
 
- Vit12
 
- VlanMode
 
- VlanType
 
- Vmxnet3_CmdInfo
 
- Vmxnet3_CoalesceMode
 
- Vmxnet3_CoalesceRbc
 
- Vmxnet3_CoalesceScheme
 
- Vmxnet3_CoalesceStatic
 
- Vmxnet3_DSDevRead
 
- Vmxnet3_DriverInfo
 
- Vmxnet3_DriverShared
 
- Vmxnet3_GOSInfo
 
- Vmxnet3_GenericDesc
 
- Vmxnet3_IntrConf
 
- Vmxnet3_MemRegs
 
- Vmxnet3_MemoryRegion
 
- Vmxnet3_MiscConf
 
- Vmxnet3_PMConf
 
- Vmxnet3_PM_PktFilter
 
- Vmxnet3_QueueStatus
 
- Vmxnet3_RxCompDesc
 
- Vmxnet3_RxCompDescExt
 
- Vmxnet3_RxDataDesc
 
- Vmxnet3_RxDesc
 
- Vmxnet3_RxFilterConf
 
- Vmxnet3_RxQueueConf
 
- Vmxnet3_RxQueueCtrl
 
- Vmxnet3_RxQueueDesc
 
- Vmxnet3_SetPolling
 
- Vmxnet3_TxCompDesc
 
- Vmxnet3_TxDataDesc
 
- Vmxnet3_TxDesc
 
- Vmxnet3_TxQueueConf
 
- Vmxnet3_TxQueueCtrl
 
- Vmxnet3_TxQueueDesc
 
- Vmxnet3_VariableLenConfDesc
 
- VoltageChangeTimeout
 
- Vort3DRend_Initialize
 
- VramMemType
 
- Vrc5074_BASE
 
- Vrc5074_PHYS_BASE
 
- Vsadr_Srcstride
 
- Vsadr_Xstart
 
- Vsadr_Ystart
 
- Vscadr_Vbase_Adr
 
- Vsctrl_Height
 
- Vsctrl_Width
 
- Vubase_Ubase_Adr
 
- Vvbase_Vbase_Adr
 
[..]