[..]
- U
 
- U008
 
- U016
 
- U032
 
- U0_SLOWLOCK
 
- U1
 
- U12_16
 
- U16
 
- U16_16
 
- U16_32
 
- U16_APER_SIZE
 
- U16_C
 
- U16_MAX
 
- U18
 
- U18_1610_SPIF_DIN
 
- U18_1610_UWIRE_SDI
 
- U19
 
- U19_1610_SPIF_SCK
 
- U19_DESC
 
- U1CTSR
 
- U1DONTCARE
 
- U1RXR
 
- U1U2_SPDWN_EN
 
- U1_ABSOLUTE_REPORT_ID
 
- U1_CMD_REGISTER_READ
 
- U1_CMD_REGISTER_WRITE
 
- U1_DESC
 
- U1_DEVICE_EXIT_LATENCY
 
- U1_DEVTYPE_SP_SUPPORT
 
- U1_DISABLE_DEV
 
- U1_ENABLE
 
- U1_FEATURE_REPORT_ID
 
- U1_FEATURE_REPORT_LEN
 
- U1_FEATURE_REPORT_LEN_ALL
 
- U1_GO_U2_EN
 
- U1_INACT_TIMEOUT_MSK
 
- U1_INACT_TIMEOUT_VALUE
 
- U1_LATENCY
 
- U1_MOUSE_REPORT_ID
 
- U1_SP_ABSOLUTE_REPORT_ID
 
- U1_SP_ABS_MODE
 
- U1_SYSTEM_EXIT_LATENCY
 
- U1_TIMEOUT
 
- U1_TP_ABS_MODE
 
- U1_g1_0
 
- U1_g1_1
 
- U1_g1_1_fp
 
- U1_g2_0_fp
 
- U1_g2_8_fp
 
- U1_g3_0_fp
 
- U1_g3_8_fp
 
- U1_gs_0
 
- U1_gs_0_fp
 
- U1_gs_0_o2_adj
 
- U1_gs_10
 
- U1_gs_40_fp
 
- U1_gs_8
 
- U1_gs_80_fp
 
- U1_gs_8_o2_adj
 
- U1_o2_0
 
- U1_o2_0_fp
 
- U1_o2_1
 
- U1_o2_1_fp
 
- U1_o2_4
 
- U1_o2_8
 
- U2
 
- U20
 
- U20_1610_MPUIO14
 
- U20_DESC
 
- U21
 
- U21_DESC
 
- U22
 
- U22_DESC
 
- U24
 
- U25
 
- U26
 
- U2CTSR
 
- U2C_I2C_FREQ
 
- U2C_I2C_FREQ_FAST
 
- U2C_I2C_FREQ_STD
 
- U2C_I2C_SPEED
 
- U2C_I2C_SPEED_2KHZ
 
- U2C_I2C_SPEED_FAST
 
- U2C_I2C_SPEED_STD
 
- U2DBCR
 
- U2DBCR0
 
- U2DCR
 
- U2DCR_AAISN
 
- U2DCR_ABP
 
- U2DCR_ACN
 
- U2DCR_ADD
 
- U2DCR_AIN
 
- U2DCR_CC
 
- U2DCR_DWRE
 
- U2DCR_EMCE
 
- U2DCR_FSTC
 
- U2DCR_HS
 
- U2DCR_HSTC
 
- U2DCR_NDC
 
- U2DCR_SMAC
 
- U2DCR_SPEOREN
 
- U2DCR_UCLKOVR
 
- U2DCR_UDA
 
- U2DCR_UDE
 
- U2DCR_UDR
 
- U2DCSR
 
- U2DCSR0
 
- U2DCSR0_DME
 
- U2DCSR0_FST
 
- U2DCSR0_FTF
 
- U2DCSR0_IPA
 
- U2DCSR0_IPR
 
- U2DCSR0_OPC
 
- U2DCSR0_RNE
 
- U2DCSR0_SA
 
- U2DCSR0_SST
 
- U2DCSR_BE
 
- U2DCSR_BF
 
- U2DCSR_BNE
 
- U2DCSR_BNF
 
- U2DCSR_DME
 
- U2DCSR_DPE
 
- U2DCSR_FEF
 
- U2DCSR_FS
 
- U2DCSR_FST
 
- U2DCSR_PC
 
- U2DCSR_SP
 
- U2DCSR_SST
 
- U2DCSR_TRN
 
- U2DDR0
 
- U2DEN
 
- U2DEN0
 
- U2DEPCR
 
- U2DEPCR_BS_MASK
 
- U2DEPCR_EE
 
- U2DFNR
 
- U2DICR
 
- U2DICR2
 
- U2DINT
 
- U2DINT_CC
 
- U2DINT_DPE
 
- U2DINT_FIFOERR
 
- U2DINT_PACKETCMP
 
- U2DINT_RS
 
- U2DINT_RU
 
- U2DINT_SOF
 
- U2DINT_SPACKETCMP
 
- U2DINT_SU
 
- U2DINT_USOF
 
- U2DISR
 
- U2DISR2
 
- U2DMABR
 
- U2DMABR0
 
- U2DMACMDR
 
- U2DMACMDR0
 
- U2DMACMDR_ENDIRQEN
 
- U2DMACMDR_LEN
 
- U2DMACMDR_PACKCOMP
 
- U2DMACMDR_STARTIRQEN
 
- U2DMACMDR_XFRDIS
 
- U2DMACR
 
- U2DMACSR
 
- U2DMACSR0
 
- U2DMACSR_BUSERRINTR
 
- U2DMACSR_BUSERRTYPE
 
- U2DMACSR_ENDINTR
 
- U2DMACSR_EORINTR
 
- U2DMACSR_EORIRQEN
 
- U2DMACSR_EORJMPEN
 
- U2DMACSR_EORSTOPEN
 
- U2DMACSR_MASKRUN
 
- U2DMACSR_RASINTR
 
- U2DMACSR_RASIRQEN
 
- U2DMACSR_REQPEND
 
- U2DMACSR_RUN
 
- U2DMACSR_SCEMC
 
- U2DMACSR_SCEMI
 
- U2DMACSR_STARTINTR
 
- U2DMACSR_STOPINTR
 
- U2DMACSR_STOPIRQEN
 
- U2DMADADR
 
- U2DMADADR0
 
- U2DMADADR_STOP
 
- U2DMAINT
 
- U2DMASADR
 
- U2DMASADR0
 
- U2DMATADR
 
- U2DMATADR0
 
- U2DONTCARE
 
- U2DOTGCR
 
- U2DOTGCR_AALTHNP
 
- U2DOTGCR_AHNP
 
- U2DOTGCR_BHNP
 
- U2DOTGCR_CKAF
 
- U2DOTGCR_IESI
 
- U2DOTGCR_ISSI
 
- U2DOTGCR_LPA
 
- U2DOTGCR_OTGEN
 
- U2DOTGCR_RTSM
 
- U2DOTGCR_SMAF
 
- U2DOTGCR_ULAF
 
- U2DOTGCR_ULE
 
- U2DOTGCR_UTMID
 
- U2DOTGICR
 
- U2DOTGINT_FCK
 
- U2DOTGINT_FID
 
- U2DOTGINT_FLS0
 
- U2DOTGINT_FLS1
 
- U2DOTGINT_FSE
 
- U2DOTGINT_FSV
 
- U2DOTGINT_FVV
 
- U2DOTGINT_RCK
 
- U2DOTGINT_RID
 
- U2DOTGINT_RLS0
 
- U2DOTGINT_RLS1
 
- U2DOTGINT_RSE
 
- U2DOTGINT_RSV
 
- U2DOTGINT_RVV
 
- U2DOTGINT_SF
 
- U2DOTGINT_SI
 
- U2DOTGISR
 
- U2DOTGUCR
 
- U2DOTGUCR_ADDR
 
- U2DOTGUCR_RDATA
 
- U2DOTGUCR_RNW
 
- U2DOTGUCR_RUN
 
- U2DOTGUCR_WDATA
 
- U2DOTGUSR
 
- U2DOTGUSR_CK
 
- U2DOTGUSR_CKA
 
- U2DOTGUSR_ID
 
- U2DOTGUSR_LPA
 
- U2DOTGUSR_LS0
 
- U2DOTGUSR_LS1
 
- U2DOTGUSR_S3A
 
- U2DOTGUSR_S6A
 
- U2DOTGUSR_SE
 
- U2DOTGUSR_SV
 
- U2DOTGUSR_VV
 
- U2DP3CR
 
- U2DP3CR_CFG
 
- U2DP3CR_P2SS
 
- U2DP3CR_P3SS
 
- U2DP3CR_VPVMBEN
 
- U2DSCA
 
- U2DSCA_VALUE
 
- U2F_CUSTOM_GET_RNG
 
- U2F_CUSTOM_WINK
 
- U2F_DISABLE
 
- U2F_ENABLE
 
- U2F_HID_MSG_LEN
 
- U2P3_ENABLE
 
- U2P_R0
 
- U2P_R0_ADP_CHARGE
 
- U2P_R0_ADP_DISCHARGE
 
- U2P_R0_ADP_PRB_EN
 
- U2P_R0_ATE_RESET
 
- U2P_R0_BYPASS_DM_DATA
 
- U2P_R0_BYPASS_DM_EN
 
- U2P_R0_BYPASS_DP_DATA
 
- U2P_R0_BYPASS_DP_EN
 
- U2P_R0_BYPASS_SEL
 
- U2P_R0_COMMON_ONN
 
- U2P_R0_DM_PULLDOWN
 
- U2P_R0_DP_PULLDOWN
 
- U2P_R0_DP_VBUS_VLD_EXT
 
- U2P_R0_DP_VBUS_VLD_EXT_SEL
 
- U2P_R0_DRV_VBUS
 
- U2P_R0_FSEL_MASK
 
- U2P_R0_FSV_MINUS
 
- U2P_R0_FSV_PLUS
 
- U2P_R0_HAST_MODE
 
- U2P_R0_HOST_DEVICE
 
- U2P_R0_ID_PULLUP
 
- U2P_R0_ID_SET_ID_DQ
 
- U2P_R0_LOOPBACK_EN_B
 
- U2P_R0_OTG_DISABLE
 
- U2P_R0_POWER_OK
 
- U2P_R0_POWER_ON_RESET
 
- U2P_R0_REF_CLK_SEL_MASK
 
- U2P_R0_TXBITSTUFF_EN
 
- U2P_R0_TXBITSTUFF_ENH
 
- U2P_R0_V_ATE_TEST_EN_B_MASK
 
- U2P_R1
 
- U2P_R1_ACA_ENABLE
 
- U2P_R1_BURN_IN_TEST
 
- U2P_R1_CHARGES_SEL
 
- U2P_R1_COMP_DIS_TUNE_MASK
 
- U2P_R1_DCD_ENABLE
 
- U2P_R1_ID_DIG
 
- U2P_R1_OTG_SESSION_VALID
 
- U2P_R1_OTG_TUNE_MASK
 
- U2P_R1_PHY_READY
 
- U2P_R1_SQRX_TUNE_MASK
 
- U2P_R1_TX_FSLS_TUNE_MASK
 
- U2P_R1_TX_HSXV_TUNE_MASK
 
- U2P_R1_TX_PREEMP_AMP_TUNE_MASK
 
- U2P_R1_TX_PREEMP_PULSE_TUNE
 
- U2P_R1_TX_RES_TUNE_MASK
 
- U2P_R1_TX_RISE_TUNE_MASK
 
- U2P_R1_TX_VREF_TUNE_MASK
 
- U2P_R1_VBUS_VALID
 
- U2P_R1_VDAT_DET_EN_B
 
- U2P_R1_VDAT_SRC_EN_B
 
- U2P_R2
 
- U2P_R2_ACA_PIN_FLOAT
 
- U2P_R2_ACA_PIN_GND
 
- U2P_R2_ACA_PIN_RANGE_A
 
- U2P_R2_ACA_PIN_RANGE_B
 
- U2P_R2_ACA_PIN_RANGE_C
 
- U2P_R2_ADP_PROBE
 
- U2P_R2_ADP_SENSE
 
- U2P_R2_A_VALID
 
- U2P_R2_B_VALID
 
- U2P_R2_CHARGE_DETECT
 
- U2P_R2_DEVICE_SESSION_VALID
 
- U2P_R2_ID_DIG
 
- U2P_R2_SESSION_END
 
- U2P_R2_TESTADDR_MASK
 
- U2P_R2_TESTCLK
 
- U2P_R2_TESTDATA_IN_MASK
 
- U2P_R2_TESTDATA_OUT_MASK
 
- U2P_R2_TESTDATA_OUT_SEL
 
- U2P_R2_VBUS_VALID
 
- U2P_R3
 
- U2P_REG_SIZE
 
- U2RXR
 
- U2U3_AUTO_SWITCH
 
- U2_BC_GSC
 
- U2_DESC
 
- U2_DEVICE_EXIT_LATENCY
 
- U2_ENABLE
 
- U2_INACT_TIMEOUT_MSK
 
- U2_IOA_RUNWAY
 
- U2_LATENCY
 
- U2_OFFSET
 
- U2_SYSTEM_EXIT_LATENCY
 
- U2x_CAPREGS_OFFSET
 
- U3
 
- U300_AHB_BRIDGE_BASE
 
- U300_AHB_PER_PHYS_BASE
 
- U300_AHB_PER_VIRT_BASE
 
- U300_APEX_BASE
 
- U300_BOOTROM_PHYS_BASE
 
- U300_BOOTROM_VIRT_BASE
 
- U300_BUSTR_BASE
 
- U300_CLK_TYPE_FAST
 
- U300_CLK_TYPE_REST
 
- U300_CLK_TYPE_SLOW
 
- U300_DMAC_BASE
 
- U300_DMA_APEX_RX
 
- U300_DMA_APEX_TX
 
- U300_DMA_CHANNELS
 
- U300_DMA_DEVICE_CHANNELS
 
- U300_DMA_GENERAL_PURPOSE_0
 
- U300_DMA_GENERAL_PURPOSE_1
 
- U300_DMA_GENERAL_PURPOSE_2
 
- U300_DMA_GENERAL_PURPOSE_3
 
- U300_DMA_GENERAL_PURPOSE_4
 
- U300_DMA_GENERAL_PURPOSE_5
 
- U300_DMA_GENERAL_PURPOSE_6
 
- U300_DMA_GENERAL_PURPOSE_7
 
- U300_DMA_GENERAL_PURPOSE_8
 
- U300_DMA_MMCSD_RX_TX
 
- U300_DMA_MSL_RX_0
 
- U300_DMA_MSL_RX_1
 
- U300_DMA_MSL_RX_2
 
- U300_DMA_MSL_RX_3
 
- U300_DMA_MSL_RX_4
 
- U300_DMA_MSL_RX_5
 
- U300_DMA_MSL_RX_6
 
- U300_DMA_MSL_TX_0
 
- U300_DMA_MSL_TX_1
 
- U300_DMA_MSL_TX_2
 
- U300_DMA_MSL_TX_3
 
- U300_DMA_MSL_TX_4
 
- U300_DMA_MSL_TX_5
 
- U300_DMA_MSL_TX_6
 
- U300_DMA_MSPRO_RX
 
- U300_DMA_MSPRO_TX
 
- U300_DMA_PCM_I2S0_RX
 
- U300_DMA_PCM_I2S0_TX
 
- U300_DMA_PCM_I2S1_RX
 
- U300_DMA_PCM_I2S1_TX
 
- U300_DMA_SPI_RX
 
- U300_DMA_SPI_TX
 
- U300_DMA_UART0_RX
 
- U300_DMA_UART0_TX
 
- U300_DMA_UART1_RX
 
- U300_DMA_UART1_TX
 
- U300_DMA_XGAM_CDI
 
- U300_DMA_XGAM_PDI
 
- U300_EMIF_CFG_BASE
 
- U300_EVHIST_BASE
 
- U300_FAST_BRIDGE_BASE
 
- U300_FAST_PER_PHYS_BASE
 
- U300_FAST_PER_VIRT_BASE
 
- U300_FLOATING_INPUT
 
- U300_GPIO_BASE
 
- U300_GPIO_CR
 
- U300_GPIO_CR_BLOCK_CLKRQ_ENABLE
 
- U300_GPIO_CR_SYNC_SEL_ENABLE
 
- U300_GPIO_MAX
 
- U300_GPIO_NUM_PORTS
 
- U300_GPIO_PINS_PER_PORT
 
- U300_GPIO_PORT_STRIDE
 
- U300_GPIO_PXICR
 
- U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK
 
- U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE
 
- U300_GPIO_PXICR_IRQ_CONFIG_MASK
 
- U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE
 
- U300_GPIO_PXIEN
 
- U300_GPIO_PXIEV
 
- U300_GPIO_PXIFR
 
- U300_GPIO_PXPCR
 
- U300_GPIO_PXPCR_ALL_PINS_MODE_MASK
 
- U300_GPIO_PXPCR_PIN_MODE_INPUT
 
- U300_GPIO_PXPCR_PIN_MODE_MASK
 
- U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN
 
- U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE
 
- U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
 
- U300_GPIO_PXPCR_PIN_MODE_SHIFT
 
- U300_GPIO_PXPDIR
 
- U300_GPIO_PXPDOR
 
- U300_GPIO_PXPER
 
- U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK
 
- U300_GPIO_PXPER_PULL_UP_DISABLE
 
- U300_I2C0_BASE
 
- U300_I2C1_BASE
 
- U300_INTCON0_BASE
 
- U300_INTCON0_VBASE
 
- U300_INTCON1_BASE
 
- U300_INTCON1_VBASE
 
- U300_ISP_BASE
 
- U300_KEYPAD_BASE
 
- U300_MMCSD_BASE
 
- U300_MSL_BASE
 
- U300_MSPRO_BASE
 
- U300_NAND_CS0_PHYS_BASE
 
- U300_NAND_IF_PHYS_BASE
 
- U300_NUM_PADS
 
- U300_OUTPUT_HIGH
 
- U300_OUTPUT_LOW
 
- U300_PCM_I2S0_BASE
 
- U300_PCM_I2S1_BASE
 
- U300_PIN_BIT
 
- U300_PIN_REG
 
- U300_PPM_BASE
 
- U300_PULL_UP_INPUT
 
- U300_RTC_BASE
 
- U300_SEMI_CONFIG_BASE
 
- U300_SLOW_BRIDGE_BASE
 
- U300_SLOW_PER_PHYS_BASE
 
- U300_SLOW_PER_VIRT_BASE
 
- U300_SPI_BASE
 
- U300_SYSCON_BASE
 
- U300_SYSCON_BCR
 
- U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND
 
- U300_SYSCON_BCR_APP_BOOT_SERV_MASK
 
- U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND
 
- U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK
 
- U300_SYSCON_C0OAR
 
- U300_SYSCON_C0OAR_AAIF_CLK
 
- U300_SYSCON_C0OAR_AFPB_P_CLK
 
- U300_SYSCON_C0OAR_AHB_CLK
 
- U300_SYSCON_C0OAR_AHPB_M_H_CLK
 
- U300_SYSCON_C0OAR_APEX_CLK
 
- U300_SYSCON_C0OAR_APP_104_CLK
 
- U300_SYSCON_C0OAR_APP_208_CLK
 
- U300_SYSCON_C0OAR_APP_52_CLK
 
- U300_SYSCON_C0OAR_APP_CPU_CLK
 
- U300_SYSCON_C0OAR_APP_I2S0_CLK
 
- U300_SYSCON_C0OAR_APP_I2S1_CLK
 
- U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK
 
- U300_SYSCON_C0OAR_APP_SEMI_CLK
 
- U300_SYSCON_C0OAR_APP_SEMI_H_CLK
 
- U300_SYSCON_C0OAR_ASPB_P_CLK
 
- U300_SYSCON_C0OAR_BT_H_CLK
 
- U300_SYSCON_C0OAR_MASK
 
- U300_SYSCON_C0OAR_VALUE
 
- U300_SYSCON_C1OAR
 
- U300_SYSCON_C1OAR_DMA_CLK
 
- U300_SYSCON_C1OAR_EMIF_H_CLK
 
- U300_SYSCON_C1OAR_EMIF_MPMC_CLK
 
- U300_SYSCON_C1OAR_EVHIST_CLK
 
- U300_SYSCON_C1OAR_GPIO_CLK
 
- U300_SYSCON_C1OAR_I2C0_P_CLK
 
- U300_SYSCON_C1OAR_I2C1_P_CLK
 
- U300_SYSCON_C1OAR_KP_P_CLK
 
- U300_SYSCON_C1OAR_MASK
 
- U300_SYSCON_C1OAR_MMC_CLK
 
- U300_SYSCON_C1OAR_MMC_P_CLK
 
- U300_SYSCON_C1OAR_MSPRO_CLK
 
- U300_SYSCON_C1OAR_NFIF_F_CLK
 
- U300_SYSCON_C1OAR_PPM_CLK
 
- U300_SYSCON_C1OAR_VALUE
 
- U300_SYSCON_C2OAR
 
- U300_SYSCON_C2OAR_MASK
 
- U300_SYSCON_C2OAR_PCM_I2S0_CLK
 
- U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK
 
- U300_SYSCON_C2OAR_PCM_I2S1_CLK
 
- U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK
 
- U300_SYSCON_C2OAR_SPI_P_CLK
 
- U300_SYSCON_C2OAR_TMR0_CLK
 
- U300_SYSCON_C2OAR_TMR1_CLK
 
- U300_SYSCON_C2OAR_UA_P_CLK
 
- U300_SYSCON_C2OAR_VALUE
 
- U300_SYSCON_C2OAR_VC_CLK
 
- U300_SYSCON_C2OAR_VC_H_CLK
 
- U300_SYSCON_C2OAR_XGAM_CDI_CLK
 
- U300_SYSCON_C2OAR_XGAM_CLK
 
- U300_SYSCON_CCR
 
- U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST
 
- U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH
 
- U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE
 
- U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW
 
- U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER
 
- U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK
 
- U300_SYSCON_CCR_I2S0_USE_VCXO
 
- U300_SYSCON_CCR_I2S1_USE_VCXO
 
- U300_SYSCON_CCR_TURN_VCXO_ON
 
- U300_SYSCON_CEFR
 
- U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN
 
- U300_SYSCON_CEFR_I2C0_CLK_EN
 
- U300_SYSCON_CEFR_I2C1_CLK_EN
 
- U300_SYSCON_CEFR_I2S0_CLK_EN
 
- U300_SYSCON_CEFR_I2S0_CORE_CLK_EN
 
- U300_SYSCON_CEFR_I2S1_CLK_EN
 
- U300_SYSCON_CEFR_I2S1_CORE_CLK_EN
 
- U300_SYSCON_CEFR_MMC_CLK_EN
 
- U300_SYSCON_CEFR_SPI_CLK_EN
 
- U300_SYSCON_CEFR_UART1_CLK_EN
 
- U300_SYSCON_CERR
 
- U300_SYSCON_CERR_AAIF_CLK_EN
 
- U300_SYSCON_CERR_AHB_CLK_EN
 
- U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN
 
- U300_SYSCON_CERR_APEX_CLK_EN
 
- U300_SYSCON_CERR_CDS_CLK_EN
 
- U300_SYSCON_CERR_CPU_CLK_EN
 
- U300_SYSCON_CERR_DMAC_CLK_EN
 
- U300_SYSCON_CERR_EMIF_CLK_EN
 
- U300_SYSCON_CERR_ISP_CLK_EN
 
- U300_SYSCON_CERR_MSPRO_CLK_EN
 
- U300_SYSCON_CERR_NANDIF_CLK_EN
 
- U300_SYSCON_CERR_SEMI_CLK_EN
 
- U300_SYSCON_CERR_VIDEO_ENC_CLK_EN
 
- U300_SYSCON_CERR_XGAM_CLK_EN
 
- U300_SYSCON_CESR
 
- U300_SYSCON_CESR_ACC_TMR_CLK_EN
 
- U300_SYSCON_CESR_APP_TMR_CLK_EN
 
- U300_SYSCON_CESR_BTR_CLK_EN
 
- U300_SYSCON_CESR_EH_CLK_EN
 
- U300_SYSCON_CESR_GPIO_CLK_EN
 
- U300_SYSCON_CESR_KEYPAD_CLK_EN
 
- U300_SYSCON_CESR_PPM_CLK_EN
 
- U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN
 
- U300_SYSCON_CESR_UART_CLK_EN
 
- U300_SYSCON_CFFR
 
- U300_SYSCON_CFRR
 
- U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN
 
- U300_SYSCON_CFRR_AHB_CLK_FORCE_EN
 
- U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN
 
- U300_SYSCON_CFRR_APEX_CLK_FORCE_EN
 
- U300_SYSCON_CFRR_CDS_CLK_FORCE_EN
 
- U300_SYSCON_CFRR_CPU_CLK_FORCE_EN
 
- U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN
 
- U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN
 
- U300_SYSCON_CFRR_ISP_CLK_FORCE_EN
 
- U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN
 
- U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN
 
- U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN
 
- U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN
 
- U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN
 
- U300_SYSCON_CFSR
 
- U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN
 
- U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN
 
- U300_SYSCON_CFSR_BTR_CLK_FORCE_EN
 
- U300_SYSCON_CFSR_EH_CLK_FORCE_EN
 
- U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN
 
- U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN
 
- U300_SYSCON_CFSR_PPM_CLK_FORCE_EN
 
- U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN
 
- U300_SYSCON_CFSR_UART_CLK_FORCE_EN
 
- U300_SYSCON_CIDR
 
- U300_SYSCON_CSDR
 
- U300_SYSCON_CSDR_SW_DEBUG_ENABLE
 
- U300_SYSCON_CSR
 
- U300_SYSCON_CSR_PLL13_LOCK_IND
 
- U300_SYSCON_CSR_PLL208_LOCK_IND
 
- U300_SYSCON_ECCR
 
- U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE
 
- U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE
 
- U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE
 
- U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE
 
- U300_SYSCON_ECCR_MASK
 
- U300_SYSCON_MMCR
 
- U300_SYSCON_MMCR_MASK
 
- U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE
 
- U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE
 
- U300_SYSCON_MMF0R
 
- U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK
 
- U300_SYSCON_MMF0R_FREQ_0_LOW_MASK
 
- U300_SYSCON_MMF0R_MASK
 
- U300_SYSCON_MMF1R
 
- U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK
 
- U300_SYSCON_MMF1R_FREQ_1_LOW_MASK
 
- U300_SYSCON_MMF1R_MASK
 
- U300_SYSCON_PCR
 
- U300_SYSCON_PCR_SERV_IND
 
- U300_SYSCON_PFCR
 
- U300_SYSCON_PFCR_DPLL_MULT_NUM
 
- U300_SYSCON_PICLR
 
- U300_SYSCON_PICLR_MASK
 
- U300_SYSCON_PICLR_PLL13_LOCK_SC
 
- U300_SYSCON_PICLR_PLL13_UNLOCK_SC
 
- U300_SYSCON_PICLR_PLL208_LOCK_SC
 
- U300_SYSCON_PICLR_PLL208_UNLOCK_SC
 
- U300_SYSCON_PICLR_RWMASK
 
- U300_SYSCON_PICR
 
- U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE
 
- U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE
 
- U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE
 
- U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE
 
- U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE
 
- U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE
 
- U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE
 
- U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE
 
- U300_SYSCON_PICR_MASK
 
- U300_SYSCON_PISR
 
- U300_SYSCON_PISR_MASK
 
- U300_SYSCON_PISR_PLL13_LOCK_IND
 
- U300_SYSCON_PISR_PLL13_UNLOCK_IND
 
- U300_SYSCON_PISR_PLL208_LOCK_IND
 
- U300_SYSCON_PISR_PLL208_UNLOCK_IND
 
- U300_SYSCON_PMC1HR
 
- U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF
 
- U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO
 
- U300_SYSCON_PMC1HR_APP_GPIO_1_DSP
 
- U300_SYSCON_PMC1HR_APP_GPIO_1_MASK
 
- U300_SYSCON_PMC1HR_APP_GPIO_1_MMC
 
- U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF
 
- U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO
 
- U300_SYSCON_PMC1HR_APP_GPIO_2_DSP
 
- U300_SYSCON_PMC1HR_APP_GPIO_2_MASK
 
- U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF
 
- U300_SYSCON_PMC1HR_APP_SPI_2_AAIF
 
- U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO
 
- U300_SYSCON_PMC1HR_APP_SPI_2_DSP
 
- U300_SYSCON_PMC1HR_APP_SPI_2_MASK
 
- U300_SYSCON_PMC1HR_APP_SPI_2_SPI
 
- U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF
 
- U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO
 
- U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK
 
- U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI
 
- U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF
 
- U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO
 
- U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK
 
- U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI
 
- U300_SYSCON_PMC1HR_APP_UART0_1_AAIF
 
- U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO
 
- U300_SYSCON_PMC1HR_APP_UART0_1_MASK
 
- U300_SYSCON_PMC1HR_APP_UART0_1_UART0
 
- U300_SYSCON_PMC1HR_APP_UART0_2_AAIF
 
- U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO
 
- U300_SYSCON_PMC1HR_APP_UART0_2_MASK
 
- U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS
 
- U300_SYSCON_PMC1HR_APP_UART0_2_UART0
 
- U300_SYSCON_PMC1HR_MASK
 
- U300_SYSCON_PMC1HR_MISC_2_AAIF
 
- U300_SYSCON_PMC1HR_MISC_2_APP_GPIO
 
- U300_SYSCON_PMC1HR_MISC_2_DSP
 
- U300_SYSCON_PMC1HR_MISC_2_MASK
 
- U300_SYSCON_PMC1HR_MISC_2_MSPRO
 
- U300_SYSCON_PMC1LR
 
- U300_SYSCON_PMC1LR_CDI_CDI
 
- U300_SYSCON_PMC1LR_CDI_CDI2
 
- U300_SYSCON_PMC1LR_CDI_EMIF
 
- U300_SYSCON_PMC1LR_CDI_GPIO
 
- U300_SYSCON_PMC1LR_CDI_MASK
 
- U300_SYSCON_PMC1LR_CDI_WCDMA
 
- U300_SYSCON_PMC1LR_CDI_WCDMA_APP_GPIO
 
- U300_SYSCON_PMC1LR_EMIF_1
 
- U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK
 
- U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF
 
- U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM
 
- U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI
 
- U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC
 
- U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK
 
- U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF
 
- U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM
 
- U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI
 
- U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC
 
- U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK
 
- U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF
 
- U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM
 
- U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC
 
- U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB
 
- U300_SYSCON_PMC1LR_EMIF_1_MASK
 
- U300_SYSCON_PMC1LR_EMIF_1_SDRAM0
 
- U300_SYSCON_PMC1LR_EMIF_1_SDRAM1
 
- U300_SYSCON_PMC1LR_EMIF_1_STATIC
 
- U300_SYSCON_PMC1LR_ETM_ACC
 
- U300_SYSCON_PMC1LR_ETM_APP
 
- U300_SYSCON_PMC1LR_ETM_MASK
 
- U300_SYSCON_PMC1LR_MASK
 
- U300_SYSCON_PMC1LR_MMCSD_DSP
 
- U300_SYSCON_PMC1LR_MMCSD_MASK
 
- U300_SYSCON_PMC1LR_MMCSD_MMCSD
 
- U300_SYSCON_PMC1LR_MMCSD_MSPRO
 
- U300_SYSCON_PMC1LR_MMCSD_WCDMA
 
- U300_SYSCON_PMC1LR_PDI_EGG
 
- U300_SYSCON_PMC1LR_PDI_MASK
 
- U300_SYSCON_PMC1LR_PDI_PDI
 
- U300_SYSCON_PMC1LR_PDI_WCDMA
 
- U300_SYSCON_PMC2R
 
- U300_SYSCON_PMC2R_APP_MISC_0_APP_GPIO
 
- U300_SYSCON_PMC2R_APP_MISC_0_CDI2
 
- U300_SYSCON_PMC2R_APP_MISC_0_EMIF_SDRAM
 
- U300_SYSCON_PMC2R_APP_MISC_0_MASK
 
- U300_SYSCON_PMC2R_APP_MISC_0_MMC
 
- U300_SYSCON_PMC2R_APP_MISC_1_APP_GPIO
 
- U300_SYSCON_PMC2R_APP_MISC_1_CDI2
 
- U300_SYSCON_PMC2R_APP_MISC_1_EMIF_SDRAM
 
- U300_SYSCON_PMC2R_APP_MISC_1_MASK
 
- U300_SYSCON_PMC2R_APP_MISC_1_MMC
 
- U300_SYSCON_PMC2R_APP_MISC_2_APP_GPIO
 
- U300_SYSCON_PMC2R_APP_MISC_2_CDI2
 
- U300_SYSCON_PMC2R_APP_MISC_2_EMIF_SDRAM
 
- U300_SYSCON_PMC2R_APP_MISC_2_MASK
 
- U300_SYSCON_PMC2R_APP_MISC_2_MMC
 
- U300_SYSCON_PMC2R_APP_MISC_3_APP_GPIO
 
- U300_SYSCON_PMC2R_APP_MISC_3_CDI2
 
- U300_SYSCON_PMC2R_APP_MISC_3_EMIF_SDRAM
 
- U300_SYSCON_PMC2R_APP_MISC_3_MASK
 
- U300_SYSCON_PMC2R_APP_MISC_3_MMC
 
- U300_SYSCON_PMC2R_APP_MISC_4_ACC_GPIO
 
- U300_SYSCON_PMC2R_APP_MISC_4_APP_GPIO
 
- U300_SYSCON_PMC2R_APP_MISC_4_EMIF_SDRAM
 
- U300_SYSCON_PMC2R_APP_MISC_4_MASK
 
- U300_SYSCON_PMC2R_APP_MISC_4_MMC
 
- U300_SYSCON_PMC3R
 
- U300_SYSCON_PMC3R_APP_MISC_10_MASK
 
- U300_SYSCON_PMC3R_APP_MISC_10_SPI
 
- U300_SYSCON_PMC3R_APP_MISC_11_MASK
 
- U300_SYSCON_PMC3R_APP_MISC_11_SPI
 
- U300_SYSCON_PMC4R
 
- U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO
 
- U300_SYSCON_PMC4R_APP_MISC_12_MASK
 
- U300_SYSCON_PMC4R_APP_MISC_13_APP_GPIO
 
- U300_SYSCON_PMC4R_APP_MISC_13_CDI
 
- U300_SYSCON_PMC4R_APP_MISC_13_MASK
 
- U300_SYSCON_PMC4R_APP_MISC_13_SMIA
 
- U300_SYSCON_PMC4R_APP_MISC_13_SMIA2
 
- U300_SYSCON_PMC4R_APP_MISC_14_APP_GPIO
 
- U300_SYSCON_PMC4R_APP_MISC_14_CDI
 
- U300_SYSCON_PMC4R_APP_MISC_14_CDI2
 
- U300_SYSCON_PMC4R_APP_MISC_14_MASK
 
- U300_SYSCON_PMC4R_APP_MISC_14_SMIA
 
- U300_SYSCON_PMC4R_APP_MISC_16_APP_GPIO_13
 
- U300_SYSCON_PMC4R_APP_MISC_16_APP_UART1_CTS
 
- U300_SYSCON_PMC4R_APP_MISC_16_EMIF_1_STATIC_CS5_N
 
- U300_SYSCON_PMC4R_APP_MISC_16_MASK
 
- U300_SYSCON_PMCR
 
- U300_SYSCON_PMCR_DCON_ENABLE
 
- U300_SYSCON_PMCR_PWR_MGNT_ENABLE
 
- U300_SYSCON_RCR
 
- U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE
 
- U300_SYSCON_RFR
 
- U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE
 
- U300_SYSCON_RFR_I2C0_RESET_ENABLE
 
- U300_SYSCON_RFR_I2C1_RESET_ENABLE
 
- U300_SYSCON_RFR_MMC_RESET_ENABLE
 
- U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE
 
- U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE
 
- U300_SYSCON_RFR_SPI_RESET_ENABLE
 
- U300_SYSCON_RFR_UART1_RESET_ENABLE
 
- U300_SYSCON_RRR
 
- U300_SYSCON_RRR_AAIF_RESET_EN
 
- U300_SYSCON_RRR_AHB_RESET_EN
 
- U300_SYSCON_RRR_APEX_RESET_EN
 
- U300_SYSCON_RRR_CDS_RESET_EN
 
- U300_SYSCON_RRR_CPU_RESET_EN
 
- U300_SYSCON_RRR_DMAC_RESET_EN
 
- U300_SYSCON_RRR_EMIF_RESET_EN
 
- U300_SYSCON_RRR_INTCON_RESET_EN
 
- U300_SYSCON_RRR_ISP_RESET_EN
 
- U300_SYSCON_RRR_MSPRO_RESET_EN
 
- U300_SYSCON_RRR_NANDIF_RESET_EN
 
- U300_SYSCON_RRR_XGAM_RESET_EN
 
- U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN
 
- U300_SYSCON_RSR
 
- U300_SYSCON_RSR_ACC_TMR_RESET_EN
 
- U300_SYSCON_RSR_APP_TMR_RESET_EN
 
- U300_SYSCON_RSR_BTR_RESET_EN
 
- U300_SYSCON_RSR_EH_RESET_EN
 
- U300_SYSCON_RSR_GPIO_RESET_EN
 
- U300_SYSCON_RSR_KEYPAD_RESET_EN
 
- U300_SYSCON_RSR_PPM_RESET_EN
 
- U300_SYSCON_RSR_RTC_RESET_EN
 
- U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN
 
- U300_SYSCON_RSR_UART_RESET_EN
 
- U300_SYSCON_S0CCR
 
- U300_SYSCON_S0CCR_CLOCK_ENABLE
 
- U300_SYSCON_S0CCR_CLOCK_FREQ_MASK
 
- U300_SYSCON_S0CCR_CLOCK_INV
 
- U300_SYSCON_S0CCR_CLOCK_REQ
 
- U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR
 
- U300_SYSCON_S0CCR_CLOCK_SELECT_MASK
 
- U300_SYSCON_S0CCR_FIELD_MASK
 
- U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK
 
- U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK
 
- U300_SYSCON_S0CCR_SEL_APP_FSM_CLK
 
- U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK
 
- U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK
 
- U300_SYSCON_S0CCR_SEL_MCLK
 
- U300_SYSCON_S0CCR_SEL_PLL60_48_CLK
 
- U300_SYSCON_S0CCR_SEL_PLL60_60_CLK
 
- U300_SYSCON_S0CCR_SEL_RTC_CLK
 
- U300_SYSCON_S1CCR
 
- U300_SYSCON_S1CCR_CLOCK_ENABLE
 
- U300_SYSCON_S1CCR_CLOCK_FREQ_MASK
 
- U300_SYSCON_S1CCR_CLOCK_INV
 
- U300_SYSCON_S1CCR_CLOCK_REQ
 
- U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR
 
- U300_SYSCON_S1CCR_CLOCK_SELECT_MASK
 
- U300_SYSCON_S1CCR_FIELD_MASK
 
- U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK
 
- U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK
 
- U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK
 
- U300_SYSCON_S1CCR_SEL_APP_FSM_CLK
 
- U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK
 
- U300_SYSCON_S1CCR_SEL_MCLK
 
- U300_SYSCON_S1CCR_SEL_PLL60_48_CLK
 
- U300_SYSCON_S1CCR_SEL_PLL60_60_CLK
 
- U300_SYSCON_S1CCR_SEL_RTC_CLK
 
- U300_SYSCON_S2CCR
 
- U300_SYSCON_S2CCR_CLK_STEAL
 
- U300_SYSCON_S2CCR_CLOCK_ENABLE
 
- U300_SYSCON_S2CCR_CLOCK_FREQ_MASK
 
- U300_SYSCON_S2CCR_CLOCK_INV
 
- U300_SYSCON_S2CCR_CLOCK_REQ
 
- U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR
 
- U300_SYSCON_S2CCR_CLOCK_SELECT_MASK
 
- U300_SYSCON_S2CCR_FIELD_MASK
 
- U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK
 
- U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK
 
- U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK
 
- U300_SYSCON_S2CCR_SEL_APP_FSM_CLK
 
- U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK
 
- U300_SYSCON_S2CCR_SEL_MCLK
 
- U300_SYSCON_S2CCR_SEL_PLL60_48_CLK
 
- U300_SYSCON_S2CCR_SEL_PLL60_60_CLK
 
- U300_SYSCON_S2CCR_SEL_RTC_CLK
 
- U300_SYSCON_SBCDR
 
- U300_SYSCON_SBCER
 
- U300_SYSCON_SBCER_AAIF_CLK_EN
 
- U300_SYSCON_SBCER_ACC_TMR_CLK_EN
 
- U300_SYSCON_SBCER_AHB_CLK_EN
 
- U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN
 
- U300_SYSCON_SBCER_APEX_CLK_EN
 
- U300_SYSCON_SBCER_APP_TMR_CLK_EN
 
- U300_SYSCON_SBCER_BTR_CLK_EN
 
- U300_SYSCON_SBCER_CDS_CLK_EN
 
- U300_SYSCON_SBCER_CPU_CLK_EN
 
- U300_SYSCON_SBCER_DMAC_CLK_EN
 
- U300_SYSCON_SBCER_EH_CLK_EN
 
- U300_SYSCON_SBCER_EMIF_CLK_EN
 
- U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN
 
- U300_SYSCON_SBCER_GPIO_CLK_EN
 
- U300_SYSCON_SBCER_I2C0_CLK_EN
 
- U300_SYSCON_SBCER_I2C1_CLK_EN
 
- U300_SYSCON_SBCER_I2S0_CLK_EN
 
- U300_SYSCON_SBCER_I2S0_CORE_CLK_EN
 
- U300_SYSCON_SBCER_I2S1_CLK_EN
 
- U300_SYSCON_SBCER_I2S1_CORE_CLK_EN
 
- U300_SYSCON_SBCER_ISP_CLK_EN
 
- U300_SYSCON_SBCER_KEYPAD_CLK_EN
 
- U300_SYSCON_SBCER_MMC_CLK_EN
 
- U300_SYSCON_SBCER_MSPRO_CLK_EN
 
- U300_SYSCON_SBCER_NANDIF_CLK_EN
 
- U300_SYSCON_SBCER_PPM_CLK_EN
 
- U300_SYSCON_SBCER_SEMI_CLK_EN
 
- U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN
 
- U300_SYSCON_SBCER_SPI_CLK_EN
 
- U300_SYSCON_SBCER_UART1_CLK_EN
 
- U300_SYSCON_SBCER_UART_CLK_EN
 
- U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN
 
- U300_SYSCON_SBCER_XGAM_CLK_EN
 
- U300_SYSCON_SMCR
 
- U300_SYSCON_SMCR_FIELD_MASK
 
- U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE
 
- U300_SYSCON_SMCR_SEMI_SREFACK_IND
 
- U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE
 
- U300_SYSCON_SRCLR
 
- U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A
 
- U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B
 
- U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A
 
- U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B
 
- U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A
 
- U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B
 
- U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A
 
- U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B
 
- U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A
 
- U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B
 
- U300_SYSCON_SRCLR_MASK
 
- U300_SYSCON_SRCLR_VALUE
 
- U300_SYSCON_VBASE
 
- U300_TIMER_APP_BASE
 
- U300_TIMER_APP_CRC
 
- U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE
 
- U300_TIMER_APP_DDDT
 
- U300_TIMER_APP_DDDT_TIMER_DISABLE
 
- U300_TIMER_APP_DDTCC
 
- U300_TIMER_APP_DDTIA
 
- U300_TIMER_APP_DDTIA_IRQ_ACK
 
- U300_TIMER_APP_DDTIE
 
- U300_TIMER_APP_DDTIE_IRQ_DISABLE
 
- U300_TIMER_APP_DDTIE_IRQ_ENABLE
 
- U300_TIMER_APP_DDTS
 
- U300_TIMER_APP_DDTS_ENABLE_IND
 
- U300_TIMER_APP_DDTS_IRQ_ENABLED_IND
 
- U300_TIMER_APP_DDTS_IRQ_PENDING_IND
 
- U300_TIMER_APP_DDTS_MODE_CONTINUOUS
 
- U300_TIMER_APP_DDTS_MODE_MASK
 
- U300_TIMER_APP_DDTS_MODE_ONE_SHOT
 
- U300_TIMER_APP_DDTS_TIMER_STATE_ACTIVE
 
- U300_TIMER_APP_DDTS_TIMER_STATE_IDLE
 
- U300_TIMER_APP_DDTS_TIMER_STATE_MASK
 
- U300_TIMER_APP_DDTTC
 
- U300_TIMER_APP_DGPT1
 
- U300_TIMER_APP_DGPT1_TIMER_DISABLE
 
- U300_TIMER_APP_DGPT2
 
- U300_TIMER_APP_DGPT2_TIMER_DISABLE
 
- U300_TIMER_APP_DOST
 
- U300_TIMER_APP_DOST_TIMER_DISABLE
 
- U300_TIMER_APP_EDDT
 
- U300_TIMER_APP_EDDT_TIMER_ENABLE
 
- U300_TIMER_APP_EGPT1
 
- U300_TIMER_APP_EGPT1_TIMER_ENABLE
 
- U300_TIMER_APP_EGPT2
 
- U300_TIMER_APP_EGPT2_TIMER_ENABLE
 
- U300_TIMER_APP_EOST
 
- U300_TIMER_APP_EOST_TIMER_ENABLE
 
- U300_TIMER_APP_GPT1CC
 
- U300_TIMER_APP_GPT1IA
 
- U300_TIMER_APP_GPT1IA_IRQ_ACK
 
- U300_TIMER_APP_GPT1IE
 
- U300_TIMER_APP_GPT1IE_IRQ_DISABLE
 
- U300_TIMER_APP_GPT1IE_IRQ_ENABLE
 
- U300_TIMER_APP_GPT1S
 
- U300_TIMER_APP_GPT1S_ENABLE_IND
 
- U300_TIMER_APP_GPT1S_IRQ_ENABLED_IND
 
- U300_TIMER_APP_GPT1S_IRQ_PENDING_IND
 
- U300_TIMER_APP_GPT1S_MODE_CONTINUOUS
 
- U300_TIMER_APP_GPT1S_MODE_MASK
 
- U300_TIMER_APP_GPT1S_MODE_ONE_SHOT
 
- U300_TIMER_APP_GPT1S_TIMER_STATE_ACTIVE
 
- U300_TIMER_APP_GPT1S_TIMER_STATE_IDLE
 
- U300_TIMER_APP_GPT1S_TIMER_STATE_MASK
 
- U300_TIMER_APP_GPT1TC
 
- U300_TIMER_APP_GPT2CC
 
- U300_TIMER_APP_GPT2IA
 
- U300_TIMER_APP_GPT2IA_IRQ_ACK
 
- U300_TIMER_APP_GPT2IE
 
- U300_TIMER_APP_GPT2IE_IRQ_DISABLE
 
- U300_TIMER_APP_GPT2IE_IRQ_ENABLE
 
- U300_TIMER_APP_GPT2S
 
- U300_TIMER_APP_GPT2S_ENABLE_IND
 
- U300_TIMER_APP_GPT2S_IRQ_ENABLED_IND
 
- U300_TIMER_APP_GPT2S_IRQ_PENDING_IND
 
- U300_TIMER_APP_GPT2S_MODE_CONTINUOUS
 
- U300_TIMER_APP_GPT2S_MODE_MASK
 
- U300_TIMER_APP_GPT2S_MODE_ONE_SHOT
 
- U300_TIMER_APP_GPT2S_TIMER_STATE_ACTIVE
 
- U300_TIMER_APP_GPT2S_TIMER_STATE_IDLE
 
- U300_TIMER_APP_GPT2S_TIMER_STATE_MASK
 
- U300_TIMER_APP_GPT2TC
 
- U300_TIMER_APP_OSTCC
 
- U300_TIMER_APP_OSTIA
 
- U300_TIMER_APP_OSTIA_IRQ_ACK
 
- U300_TIMER_APP_OSTIE
 
- U300_TIMER_APP_OSTIE_IRQ_DISABLE
 
- U300_TIMER_APP_OSTIE_IRQ_ENABLE
 
- U300_TIMER_APP_OSTS
 
- U300_TIMER_APP_OSTS_ENABLE_IND
 
- U300_TIMER_APP_OSTS_IRQ_ENABLED_IND
 
- U300_TIMER_APP_OSTS_IRQ_PENDING_IND
 
- U300_TIMER_APP_OSTS_MODE_CONTINUOUS
 
- U300_TIMER_APP_OSTS_MODE_MASK
 
- U300_TIMER_APP_OSTS_MODE_ONE_SHOT
 
- U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE
 
- U300_TIMER_APP_OSTS_TIMER_STATE_IDLE
 
- U300_TIMER_APP_OSTS_TIMER_STATE_MASK
 
- U300_TIMER_APP_OSTTC
 
- U300_TIMER_APP_RDDT
 
- U300_TIMER_APP_RDDT_TIMER_RESET
 
- U300_TIMER_APP_RGPT1
 
- U300_TIMER_APP_RGPT1_TIMER_RESET
 
- U300_TIMER_APP_RGPT2
 
- U300_TIMER_APP_RGPT2_TIMER_RESET
 
- U300_TIMER_APP_ROST
 
- U300_TIMER_APP_ROST_TIMER_RESET
 
- U300_TIMER_APP_SDDTM
 
- U300_TIMER_APP_SDDTM_MODE_CONTINUOUS
 
- U300_TIMER_APP_SDDTM_MODE_ONE_SHOT
 
- U300_TIMER_APP_SGPT1M
 
- U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS
 
- U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT
 
- U300_TIMER_APP_SGPT2M
 
- U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS
 
- U300_TIMER_APP_SGPT2M_MODE_ONE_SHOT
 
- U300_TIMER_APP_SOSTM
 
- U300_TIMER_APP_SOSTM_MODE_CONTINUOUS
 
- U300_TIMER_APP_SOSTM_MODE_ONE_SHOT
 
- U300_TIMER_APP_VBASE
 
- U300_TIMER_BASE
 
- U300_UART0_BASE
 
- U300_UART1_BASE
 
- U300_VIDEOENC_BASE
 
- U300_WDOG_BASE
 
- U300_WDOG_CR
 
- U300_WDOG_CR_COUNT_VALUE_MASK
 
- U300_WDOG_CR_VALID_IND
 
- U300_WDOG_CR_VALID_STABLE
 
- U300_WDOG_D1R
 
- U300_WDOG_D1R_DISABLE1_DISABLE_TIMER
 
- U300_WDOG_D2R
 
- U300_WDOG_D2R_DISABLE2_DISABLE_TIMER
 
- U300_WDOG_D2R_DISABLE_STATUS_DISABLED
 
- U300_WDOG_D2R_DISABLE_STATUS_ENABLED
 
- U300_WDOG_DEFAULT_TIMEOUT
 
- U300_WDOG_FR
 
- U300_WDOG_FR_FEED_RESTART_TIMER
 
- U300_WDOG_IER
 
- U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE
 
- U300_WDOG_IER_WILL_BARK_IRQ_EVENT_IND
 
- U300_WDOG_IFR
 
- U300_WDOG_IFR_WILL_BARK_IRQ_FORCE_ENABLE
 
- U300_WDOG_IMR
 
- U300_WDOG_IMR_WILL_BARK_IRQ_ENABLE
 
- U300_WDOG_JOR
 
- U300_WDOG_JOR_JTAG_MODE_IND
 
- U300_WDOG_JOR_JTAG_WATCHDOG_ENABLE
 
- U300_WDOG_RR
 
- U300_WDOG_RR_RESTART_VALUE_RESUME
 
- U300_WDOG_SR
 
- U300_WDOG_SR_RESET_STATUS_RESET
 
- U300_WDOG_SR_STATUS_NORMAL
 
- U300_WDOG_SR_STATUS_TIMED_OUT
 
- U300_WDOG_TR
 
- U300_WDOG_TR_TIMEOUT_MASK
 
- U300_XGAM_BASE
 
- U32
 
- U32_16
 
- U32_APER_SIZE
 
- U32_C
 
- U32_HASH_SHIFT
 
- U32_HASH_SIZE
 
- U32_MAX
 
- U32_MAX_DIGITS
 
- U32_PAD
 
- U32_PER_LONG
 
- U32_U64_PAD
 
- U3CTSR
 
- U3D_CAP_EP0FFSZ
 
- U3D_CAP_EPINFO
 
- U3D_CAP_EPNRXFFSZ
 
- U3D_CAP_EPNTXFFSZ
 
- U3D_COMMON_USB_INTR
 
- U3D_COMMON_USB_INTR_ENABLE
 
- U3D_DEVICE_CONF
 
- U3D_DEVICE_CONTROL
 
- U3D_DEV_LINK_INTR
 
- U3D_DEV_LINK_INTR_ENABLE
 
- U3D_EP0CSR
 
- U3D_EPIECR
 
- U3D_EPIER
 
- U3D_EPIESR
 
- U3D_EPISR
 
- U3D_EP_RST
 
- U3D_FIFO0
 
- U3D_LINK_ERR_COUNT
 
- U3D_LINK_POWER_CONTROL
 
- U3D_LINK_RESET_INFO
 
- U3D_LINK_STATE_MACHINE
 
- U3D_LINK_UX_INACT_TIMER
 
- U3D_LTSSM_CTRL
 
- U3D_LTSSM_INTR
 
- U3D_LTSSM_INTR_ENABLE
 
- U3D_LV1IECR
 
- U3D_LV1IER
 
- U3D_LV1IESR
 
- U3D_LV1ISR
 
- U3D_MISC_CTRL
 
- U3D_POWER_MANAGEMENT
 
- U3D_QCR0
 
- U3D_QCR1
 
- U3D_QCR2
 
- U3D_QCR3
 
- U3D_QFCR
 
- U3D_QIECR0
 
- U3D_QIECR1
 
- U3D_QIER0
 
- U3D_QIER1
 
- U3D_QIESR0
 
- U3D_QIESR1
 
- U3D_QISAR0
 
- U3D_QISAR1
 
- U3D_RESERVED
 
- U3D_RQERRIECR0
 
- U3D_RQERRIECR1
 
- U3D_RQERRIER0
 
- U3D_RQERRIER1
 
- U3D_RQERRIESR0
 
- U3D_RQERRIESR1
 
- U3D_RQERRIR0
 
- U3D_RQERRIR1
 
- U3D_RX1CSR0
 
- U3D_RX1CSR1
 
- U3D_RX1CSR2
 
- U3D_RXCOUNT0
 
- U3D_RXQCPR1
 
- U3D_RXQCSR1
 
- U3D_RXQHIAR1
 
- U3D_RXQLDPR1
 
- U3D_RXQSAR1
 
- U3D_SSUSB_DEV_RST_CTRL
 
- U3D_SSUSB_HW_ID
 
- U3D_SSUSB_HW_SUB_ID
 
- U3D_SSUSB_IP_DEV_CAP
 
- U3D_SSUSB_IP_PW_CTRL0
 
- U3D_SSUSB_IP_PW_CTRL1
 
- U3D_SSUSB_IP_PW_CTRL2
 
- U3D_SSUSB_IP_PW_CTRL3
 
- U3D_SSUSB_IP_PW_STS1
 
- U3D_SSUSB_IP_PW_STS2
 
- U3D_SSUSB_IP_SPARE0
 
- U3D_SSUSB_IP_TRUNK_VERS
 
- U3D_SSUSB_IP_XHCI_CAP
 
- U3D_SSUSB_OTG_INT_EN
 
- U3D_SSUSB_OTG_STS
 
- U3D_SSUSB_OTG_STS_CLR
 
- U3D_SSUSB_PRB_CTRL0
 
- U3D_SSUSB_PRB_CTRL1
 
- U3D_SSUSB_PRB_CTRL2
 
- U3D_SSUSB_PRB_CTRL3
 
- U3D_SSUSB_PRB_CTRL4
 
- U3D_SSUSB_PRB_CTRL5
 
- U3D_SSUSB_REF_CK_CTRL
 
- U3D_SSUSB_U2_CTRL_0P
 
- U3D_SSUSB_U3_CTRL_0P
 
- U3D_TQERRIECR0
 
- U3D_TQERRIER0
 
- U3D_TQERRIESR0
 
- U3D_TQERRIR0
 
- U3D_TX1CSR0
 
- U3D_TX1CSR1
 
- U3D_TX1CSR2
 
- U3D_TXQCPR1
 
- U3D_TXQCSR1
 
- U3D_TXQHIAR1
 
- U3D_TXQSAR1
 
- U3D_U2PHYDCR0
 
- U3D_U3U2_SWITCH_CTRL
 
- U3D_USB20_FRAME_NUM
 
- U3D_USB20_LPM_PARAMETER
 
- U3D_USB20_MISC_CONTROL
 
- U3D_USB20_OPSTATE
 
- U3D_USB2_TEST_MODE
 
- U3D_USB3_CONFIG
 
- U3EN
 
- U3P_FM_DET_CYCLE_CNT
 
- U3P_REF_CLK
 
- U3P_SLEW_RATE_COEF
 
- U3P_SPLLC_XTALCTL3
 
- U3P_SR_COEF_DIVISOR
 
- U3P_U2FREQ_FMCR0
 
- U3P_U2FREQ_FMMONR1
 
- U3P_U2FREQ_VALUE
 
- U3P_U2PHYACR4
 
- U3P_U2PHYBC12C
 
- U3P_U2PHYDTM0
 
- U3P_U2PHYDTM1
 
- U3P_U3_CHIP_GPIO_CTLD
 
- U3P_U3_CHIP_GPIO_CTLE
 
- U3P_U3_PHYA_DA_REG0
 
- U3P_U3_PHYA_DA_REG20
 
- U3P_U3_PHYA_DA_REG25
 
- U3P_U3_PHYA_DA_REG4
 
- U3P_U3_PHYA_DA_REG5
 
- U3P_U3_PHYA_DA_REG6
 
- U3P_U3_PHYA_DA_REG7
 
- U3P_U3_PHYA_REG0
 
- U3P_U3_PHYA_REG1
 
- U3P_U3_PHYA_REG6
 
- U3P_U3_PHYA_REG9
 
- U3P_U3_PHYD_CDR1
 
- U3P_U3_PHYD_LFPS1
 
- U3P_U3_PHYD_RXDET1
 
- U3P_U3_PHYD_RXDET2
 
- U3P_USBPHYACR0
 
- U3P_USBPHYACR1
 
- U3P_USBPHYACR2
 
- U3P_USBPHYACR5
 
- U3P_USBPHYACR6
 
- U3RXR
 
- U3_API_PHY_CONFIG_1
 
- U3_DESC
 
- U3_HT_CFA0
 
- U3_HT_CFA1
 
- U3_HT_CONFIG_BASE
 
- U3_HT_LINK_COMMAND
 
- U3_HT_LINK_CONFIG
 
- U3_HT_LINK_FREQ
 
- U3_LFPS_TMOUT_INTR
 
- U3_MPIC_OUTPUT_ENABLE
 
- U3_MPIC_RESET
 
- U3_N_CFG_GART_B2BGNT
 
- U3_N_CFG_GART_FASTDDR
 
- U3_N_CFG_GART_PERFRD
 
- U3_N_CFG_GART_SYNCMODE
 
- U3_PMC_START_STOP
 
- U3_RESUME_INTR
 
- U3_TOGGLE_REG
 
- U3_retl_o2
 
- U3_retl_o2_and_7_plus_GS
 
- U3_retl_o2_and_7_plus_GS_plus_8
 
- U3_retl_o2_fp
 
- U3_retl_o2_plus_1
 
- U3_retl_o2_plus_4
 
- U3_retl_o2_plus_8
 
- U3_retl_o2_plus_GS_plus_0x08
 
- U3_retl_o2_plus_GS_plus_0x10
 
- U3_retl_o2_plus_g1_plus_1
 
- U3_retl_o2_plus_g2_fp
 
- U3_retl_o2_plus_g2_plus_8_fp
 
- U3_retl_o2_plus_g2_plus_g1_plus_1_fp
 
- U3_retl_o2_plus_o3_sll_6_plus_0x40_fp
 
- U3_retl_o2_plus_o3_sll_6_plus_0x80_fp
 
- U4
 
- U4CTSR
 
- U4DONTCARE
 
- U4RXR
 
- U4_12
 
- U4_16
 
- U4_20
 
- U4_24
 
- U4_28
 
- U4_32
 
- U4_36
 
- U4_8
 
- U4_DESC
 
- U4_PCIE_CFA0
 
- U4_PCIE_CFA1
 
- U5
 
- U5CTSR
 
- U5RXR
 
- U5_DESC
 
- U64
 
- U642I64
 
- U64K
 
- U64STR_SIZE
 
- U64_C
 
- U64_HI
 
- U64_HIGH_BIT
 
- U64_LO
 
- U64_LSHIFT
 
- U64_MAX
 
- U64_TO_U32_HIGH
 
- U64_TO_U32_LOW
 
- U6CTSR
 
- U6RXR
 
- U8
 
- U802ROMAGIC
 
- U802TOCMAGIC
 
- U802WRMAGIC
 
- U8500_APE_BASE
 
- U8500_ASIC_ID_BASE
 
- U8500_B2R2_BASE
 
- U8500_BACKUPRAM0_BASE
 
- U8500_BACKUPRAM1_BASE
 
- U8500_BB_UID_BASE
 
- U8500_BOOT_ROM_BASE
 
- U8500_CLKRST1_BASE
 
- U8500_CLKRST2_BASE
 
- U8500_CLKRST3_BASE
 
- U8500_CLKRST5_BASE
 
- U8500_CLKRST6_BASE
 
- U8500_CRYP0_BASE
 
- U8500_CRYP1_BASE
 
- U8500_CR_BASE
 
- U8500_DMA_BASE
 
- U8500_DMA_LCLA_BASE
 
- U8500_DMA_LCPA_BASE
 
- U8500_DMC_BASE
 
- U8500_DSI_LINK1_BASE
 
- U8500_DSI_LINK2_BASE
 
- U8500_DSI_LINK3_BASE
 
- U8500_DSI_LINK_COUNT
 
- U8500_DSI_LINK_SIZE
 
- U8500_ESRAM_BANK0
 
- U8500_ESRAM_BANK1
 
- U8500_ESRAM_BANK2
 
- U8500_ESRAM_BANK3
 
- U8500_ESRAM_BANK4
 
- U8500_ESRAM_BANK_SIZE
 
- U8500_ESRAM_BASE
 
- U8500_ESRAM_DMA_LCPA_OFFSET
 
- U8500_FSMC_BASE
 
- U8500_GIC_CPU_BASE
 
- U8500_GIC_DIST_BASE
 
- U8500_GPIO0_BASE
 
- U8500_GPIO1_BASE
 
- U8500_GPIO2_BASE
 
- U8500_GPIO3_BASE
 
- U8500_GPIOBANK0_BASE
 
- U8500_GPIOBANK1_BASE
 
- U8500_GPIOBANK2_BASE
 
- U8500_GPIOBANK3_BASE
 
- U8500_GPIOBANK4_BASE
 
- U8500_GPIOBANK5_BASE
 
- U8500_GPIOBANK6_BASE
 
- U8500_GPIOBANK7_BASE
 
- U8500_GPIOBANK8_BASE
 
- U8500_HASH0_BASE
 
- U8500_HASH1_BASE
 
- U8500_HSEM_BASE
 
- U8500_HSIR_BASE
 
- U8500_HSIT_BASE
 
- U8500_I2C0_BASE
 
- U8500_I2C1_BASE
 
- U8500_I2C2_BASE
 
- U8500_I2C3_BASE
 
- U8500_I2C4_BASE
 
- U8500_ICN_BASE
 
- U8500_IO_PHYSICAL
 
- U8500_IO_VIRTUAL
 
- U8500_L2CC_BASE
 
- U8500_MAX_SEMAPHORE
 
- U8500_MCDE_BASE
 
- U8500_MCDE_SIZE
 
- U8500_MODEM_BASE
 
- U8500_MODEM_I2C
 
- U8500_MSP0_BASE
 
- U8500_MSP1_BASE
 
- U8500_MSP2_BASE
 
- U8500_MSP3_BASE
 
- U8500_MTU0_BASE
 
- U8500_MTU1_BASE
 
- U8500_PER1_BASE
 
- U8500_PER2_BASE
 
- U8500_PER3_BASE
 
- U8500_PER4_BASE
 
- U8500_PER5_BASE
 
- U8500_PER6_BASE
 
- U8500_PER7_BASE
 
- U8500_PKAM_BASE
 
- U8500_PKA_BASE
 
- U8500_PRCMU_BASE
 
- U8500_PRCMU_TCDM_BASE
 
- U8500_PRCMU_TCPM_BASE
 
- U8500_PRCMU_TIMER_3_BASE
 
- U8500_PRCMU_TIMER_4_BASE
 
- U8500_PWL_BASE
 
- U8500_RNG_BASE
 
- U8500_RTC_BASE
 
- U8500_RTT0_BASE
 
- U8500_RTT1_BASE
 
- U8500_SBAG_BASE
 
- U8500_SCR_BASE
 
- U8500_SCU_BASE
 
- U8500_SDI0_BASE
 
- U8500_SDI1_BASE
 
- U8500_SDI2_BASE
 
- U8500_SDI3_BASE
 
- U8500_SDI4_BASE
 
- U8500_SDI5_BASE
 
- U8500_SGA_BASE
 
- U8500_SHRM_GOP_INTERRUPT_BASE
 
- U8500_SIA_BASE
 
- U8500_SKE_BASE
 
- U8500_SLIM0_BASE
 
- U8500_SPI0_BASE
 
- U8500_SPI1_BASE
 
- U8500_SPI2_BASE
 
- U8500_SPI3_BASE
 
- U8500_SSP0_BASE
 
- U8500_SSP1_BASE
 
- U8500_STM_BASE
 
- U8500_STM_REG_BASE
 
- U8500_SVA_BASE
 
- U8500_TPIU_BASE
 
- U8500_TWD_BASE
 
- U8500_UART0_BASE
 
- U8500_UART0_PHYS_BASE
 
- U8500_UART1_BASE
 
- U8500_UART1_PHYS_BASE
 
- U8500_UART2_BASE
 
- U8500_UART2_PHYS_BASE
 
- U8500_USBOTG_BASE
 
- U8_16
 
- U8_24
 
- U8_28
 
- U8_32
 
- U8_8
 
- U8_APER_SIZE
 
- U8_C
 
- U8_MAX
 
- U9540_DMC1_BASE
 
- UA
 
- UA0_EMI_REC
 
- UA0_STATUS
 
- UA0_STATUS_TX_READY
 
- UAA_CFG_PWRSTATUS
 
- UAA_CFG_SPACE_FLAG
 
- UAA_CORE_CHANGE
 
- UAC1_ATTRIBUTE
 
- UAC1_AUDIO_BUF_SIZE
 
- UAC1_DEF_CCHMASK
 
- UAC1_DEF_CSRATE
 
- UAC1_DEF_CSSIZE
 
- UAC1_DEF_PCHMASK
 
- UAC1_DEF_PSRATE
 
- UAC1_DEF_PSSIZE
 
- UAC1_DEF_REQ_NUM
 
- UAC1_EXTENSION_UNIT
 
- UAC1_INT_ATTRIBUTE
 
- UAC1_OUT_EP_MAX_PACKET_SIZE
 
- UAC1_PROCESSING_UNIT
 
- UAC1_REQ_COUNT
 
- UAC1_STATUS_TYPE_IRQ_PENDING
 
- UAC1_STATUS_TYPE_MEM_CHANGED
 
- UAC1_STATUS_TYPE_ORIG_AUDIO_CONTROL_IF
 
- UAC1_STATUS_TYPE_ORIG_AUDIO_STREAM_EP
 
- UAC1_STATUS_TYPE_ORIG_AUDIO_STREAM_IF
 
- UAC1_STATUS_TYPE_ORIG_MASK
 
- UAC1_STR_ATTRIBUTE
 
- UAC2_AC3_DECODER_ERROR
 
- UAC2_AC3_DYN_RANGE
 
- UAC2_AC3_HILO_SCALING
 
- UAC2_AC3_MODE
 
- UAC2_AC3_OVERFLOW
 
- UAC2_AC3_SCALING
 
- UAC2_AC3_UNDEFINED
 
- UAC2_AC3_UNDERFLOW
 
- UAC2_AS_ACT_ALT_SETTING
 
- UAC2_AS_AUDIO_DATA_FORMAT
 
- UAC2_AS_UNDEFINED
 
- UAC2_AS_VAL_ALT_SETTINGS
 
- UAC2_ATTRIBUTE
 
- UAC2_CLOCK_MULTIPLIER
 
- UAC2_CLOCK_SELECTOR
 
- UAC2_CLOCK_SOURCE
 
- UAC2_CM_DENOMINTATOR
 
- UAC2_CM_NUMERATOR
 
- UAC2_CM_UNDEFINED
 
- UAC2_CONTROL_DATA_OVERRUN
 
- UAC2_CONTROL_DATA_UNDERRUN
 
- UAC2_CONTROL_PITCH
 
- UAC2_CS_CONTROL_CLOCK_VALID
 
- UAC2_CS_CONTROL_SAM_FREQ
 
- UAC2_CS_CUR
 
- UAC2_CS_MEM
 
- UAC2_CS_RANGE
 
- UAC2_CS_UNDEFINED
 
- UAC2_CX_CLOCK_SELECTOR
 
- UAC2_CX_UNDEFINED
 
- UAC2_DECODER
 
- UAC2_DECODER_AC3
 
- UAC2_DECODER_DTS
 
- UAC2_DECODER_MPEG
 
- UAC2_DECODER_OTHER
 
- UAC2_DECODER_UNDEFINED
 
- UAC2_DECODER_WMA
 
- UAC2_DEF_CCHMASK
 
- UAC2_DEF_CSRATE
 
- UAC2_DEF_CSSIZE
 
- UAC2_DEF_PCHMASK
 
- UAC2_DEF_PSRATE
 
- UAC2_DEF_PSSIZE
 
- UAC2_DEF_REQ_NUM
 
- UAC2_DP_CLUSTER
 
- UAC2_DP_ENABLE
 
- UAC2_DP_LATENCY
 
- UAC2_DP_MODE_SELECT
 
- UAC2_DP_OVERFLOW
 
- UAC2_DP_UNDEFINED
 
- UAC2_DP_UNDERFFLOW
 
- UAC2_DR_ATTACK_TIME
 
- UAC2_DR_COMPRESSION_RATE
 
- UAC2_DR_ENABLE
 
- UAC2_DR_LATENCY
 
- UAC2_DR_MAXAMPL
 
- UAC2_DR_OVERFLOW
 
- UAC2_DR_RELEASE_TIME
 
- UAC2_DR_THRESHOLD
 
- UAC2_DR_UNDEFINED
 
- UAC2_DR_UNDEFLOW
 
- UAC2_DTS_DECODER_ERROR
 
- UAC2_DTS_OVERFLOW
 
- UAC2_DTS_UNDEFINED
 
- UAC2_DTS_UNDERFLOW
 
- UAC2_EFFECT_DYN_RANGE_COMP
 
- UAC2_EFFECT_MOD_DELAY
 
- UAC2_EFFECT_PARAM_EQ
 
- UAC2_EFFECT_REVERB
 
- UAC2_EFFECT_UNDEFINED
 
- UAC2_EFFECT_UNIT
 
- UAC2_ENCODER
 
- UAC2_ENCODER_AC3
 
- UAC2_ENCODER_DTS
 
- UAC2_ENCODER_MPEG
 
- UAC2_ENCODER_OTHER
 
- UAC2_ENCODER_UNDEFINED
 
- UAC2_ENCODER_WMA
 
- UAC2_EN_BIT_RATE
 
- UAC2_EN_ENCODER_ERROR
 
- UAC2_EN_OVERFLOW
 
- UAC2_EN_PARAM1
 
- UAC2_EN_PARAM2
 
- UAC2_EN_PARAM3
 
- UAC2_EN_PARAM4
 
- UAC2_EN_PARAM5
 
- UAC2_EN_PARAM6
 
- UAC2_EN_PARAM7
 
- UAC2_EN_PARAM8
 
- UAC2_EN_QUALITY
 
- UAC2_EN_TYPE
 
- UAC2_EN_UNDEFINED
 
- UAC2_EN_UNDERFLOW
 
- UAC2_EN_VBR
 
- UAC2_EP_CS_DATA_OVERRUN
 
- UAC2_EP_CS_DATA_UNDERRUN
 
- UAC2_EP_CS_PITCH
 
- UAC2_EP_CS_UNDEFINED
 
- UAC2_EXTENSION_UNIT_V2
 
- UAC2_FORMAT_TYPE_I_RAW_DATA
 
- UAC2_FUNCTION_AUDIO_VIDEO
 
- UAC2_FUNCTION_CONTROL_PANEL
 
- UAC2_FUNCTION_CONVERTER
 
- UAC2_FUNCTION_DESKTOP_SPEAKER
 
- UAC2_FUNCTION_HEADSET
 
- UAC2_FUNCTION_HOME_THEATER
 
- UAC2_FUNCTION_IO_BOX
 
- UAC2_FUNCTION_MICROPHONE
 
- UAC2_FUNCTION_MUSICAL_INSTRUMENT
 
- UAC2_FUNCTION_OTHER
 
- UAC2_FUNCTION_PRO_AUDIO
 
- UAC2_FUNCTION_SOUND_RECORDER
 
- UAC2_FUNCTION_SUBCLASS_UNDEFINED
 
- UAC2_FUNCTION_TELEPHONE
 
- UAC2_FU_INPUT_GAIN
 
- UAC2_FU_INPUT_GAIN_PAD
 
- UAC2_FU_LATENCY
 
- UAC2_FU_OVERFLOW
 
- UAC2_FU_PHASE_INVERTER
 
- UAC2_FU_UNDERFLOW
 
- UAC2_INTERRUPT_DATA_MSG_EP
 
- UAC2_INTERRUPT_DATA_MSG_VENDOR
 
- UAC2_MD_BALANCE
 
- UAC2_MD_DEPTH
 
- UAC2_MD_ENABLE
 
- UAC2_MD_FEEDBACK
 
- UAC2_MD_LATENCY
 
- UAC2_MD_OVERFLOW
 
- UAC2_MD_RATE
 
- UAC2_MD_TIME
 
- UAC2_MD_UNDEFINED
 
- UAC2_MD_UNDERFLOW
 
- UAC2_MPEG_DECODER_ERROR
 
- UAC2_MPEG_DUAL_CHANNEL
 
- UAC2_MPEG_DYN_RANGE
 
- UAC2_MPEG_HILO_SCALING
 
- UAC2_MPEG_MULTILINGUAL
 
- UAC2_MPEG_OVERFLOW
 
- UAC2_MPEG_SCALING
 
- UAC2_MPEG_SECOND_STEREO
 
- UAC2_MPEG_UNDEFINED
 
- UAC2_MPEG_UNDERFLOW
 
- UAC2_MU_CLUSTER
 
- UAC2_MU_LATENCY
 
- UAC2_MU_MIXER
 
- UAC2_MU_OVERFLOW
 
- UAC2_MU_UNDEFINED
 
- UAC2_MU_UNDERFLOW
 
- UAC2_PE_CENTERFREQ
 
- UAC2_PE_ENABLE
 
- UAC2_PE_GAIN
 
- UAC2_PE_LATENCY
 
- UAC2_PE_OVERFLOW
 
- UAC2_PE_QFACTOR
 
- UAC2_PE_UNDEFINED
 
- UAC2_PE_UNDERFLOW
 
- UAC2_PROCESSING_UNIT_V2
 
- UAC2_PROCESS_DOLBY_PROLOCIC
 
- UAC2_PROCESS_STEREO_EXTENDER
 
- UAC2_PROCESS_UNDEFINED
 
- UAC2_PROCESS_UP_DOWNMIX
 
- UAC2_RV_DENSITY
 
- UAC2_RV_ENABLE
 
- UAC2_RV_FEEDBACK
 
- UAC2_RV_HIFREQ_ROLLOFF
 
- UAC2_RV_LATENCY
 
- UAC2_RV_LEVEL
 
- UAC2_RV_OVERFLOW
 
- UAC2_RV_PREDELAY
 
- UAC2_RV_TIME
 
- UAC2_RV_TYPE
 
- UAC2_RV_UNDEFINED
 
- UAC2_RV_UNDERFLOW
 
- UAC2_SAMPLE_RATE_CONVERTER
 
- UAC2_ST_EXT_ENABLE
 
- UAC2_ST_EXT_LATENCY
 
- UAC2_ST_EXT_OVERFLOW
 
- UAC2_ST_EXT_UNDEFINED
 
- UAC2_ST_EXT_UNDEFLOW
 
- UAC2_ST_EXT_WIDTH
 
- UAC2_SU_LATENCY
 
- UAC2_SU_SELECTOR
 
- UAC2_SU_UNDEFINED
 
- UAC2_TE_CLUSTER
 
- UAC2_TE_CONNECTOR
 
- UAC2_TE_COPY_PROTECT
 
- UAC2_TE_LATENCY
 
- UAC2_TE_OVERFLOW
 
- UAC2_TE_OVERLOAD
 
- UAC2_TE_UNDEFINED
 
- UAC2_TE_UNDERFLOW
 
- UAC2_UD_CLUSTER
 
- UAC2_UD_ENABLE
 
- UAC2_UD_LATENCY
 
- UAC2_UD_MODE_SELECT
 
- UAC2_UD_OVERFLOW
 
- UAC2_UD_UNDEFINED
 
- UAC2_UD_UNDERFLOW
 
- UAC2_WMA_DECODER_ERROR
 
- UAC2_WMA_OVERFLOW
 
- UAC2_WMA_UNDEFINED
 
- UAC2_WMA_UNDERFLOW
 
- UAC2_XU_CLUSTER
 
- UAC2_XU_ENABLE
 
- UAC2_XU_LATENCY
 
- UAC2_XU_OVERFLOW
 
- UAC2_XU_UNDEFINED
 
- UAC2_XU_UNDERFLOW
 
- UAC3_AC_ACTIVE_INTERFACE_CONTROL
 
- UAC3_AC_CONTROL_UNDEFINED
 
- UAC3_AC_POWER_DOMAIN_CONTROL
 
- UAC3_BADD_CS_ID9
 
- UAC3_BADD_EP_MAXPSIZE_ASYNC_MONO_16
 
- UAC3_BADD_EP_MAXPSIZE_ASYNC_MONO_24
 
- UAC3_BADD_EP_MAXPSIZE_ASYNC_STEREO_16
 
- UAC3_BADD_EP_MAXPSIZE_ASYNC_STEREO_24
 
- UAC3_BADD_EP_MAXPSIZE_SYNC_MONO_16
 
- UAC3_BADD_EP_MAXPSIZE_SYNC_MONO_24
 
- UAC3_BADD_EP_MAXPSIZE_SYNC_STEREO_16
 
- UAC3_BADD_EP_MAXPSIZE_SYNC_STEREO_24
 
- UAC3_BADD_FU_ID2
 
- UAC3_BADD_FU_ID5
 
- UAC3_BADD_FU_ID7
 
- UAC3_BADD_IT_ID1
 
- UAC3_BADD_IT_ID4
 
- UAC3_BADD_MU_ID8
 
- UAC3_BADD_OT_ID3
 
- UAC3_BADD_OT_ID6
 
- UAC3_BADD_PD_ID10
 
- UAC3_BADD_PD_ID11
 
- UAC3_BADD_PD_RECOVER_D1D0
 
- UAC3_BADD_PD_RECOVER_D2D0
 
- UAC3_BADD_SAMPLING_RATE
 
- UAC3_CHANNEL_AMBISONIC
 
- UAC3_CHANNEL_DESCRIPTION
 
- UAC3_CHANNEL_INFORMATION
 
- UAC3_CHANNEL_VENDOR_DEFINED
 
- UAC3_CH_ARRAY
 
- UAC3_CH_BACK_CENTER
 
- UAC3_CH_BACK_LEFT
 
- UAC3_CH_BACK_LEFT_OF_CENTER
 
- UAC3_CH_BACK_RIGHT
 
- UAC3_CH_BACK_RIGHT_OF_CENTER
 
- UAC3_CH_BACK_WIDE_LEFT
 
- UAC3_CH_BACK_WIDE_RIGHT
 
- UAC3_CH_BOTTOM_BACK_CENTER
 
- UAC3_CH_BOTTOM_BACK_LEFT
 
- UAC3_CH_BOTTOM_BACK_LOC
 
- UAC3_CH_BOTTOM_BACK_RIGHT
 
- UAC3_CH_BOTTOM_BACK_ROC
 
- UAC3_CH_BOTTOM_BACK_WIDE_LEFT
 
- UAC3_CH_BOTTOM_BACK_WIDE_RIGHT
 
- UAC3_CH_BOTTOM_CENTER
 
- UAC3_CH_BOTTOM_FRONT_CENTER
 
- UAC3_CH_BOTTOM_FRONT_LEFT
 
- UAC3_CH_BOTTOM_FRONT_LOC
 
- UAC3_CH_BOTTOM_FRONT_RIGHT
 
- UAC3_CH_BOTTOM_FRONT_ROC
 
- UAC3_CH_BOTTOM_FRONT_WIDE_LEFT
 
- UAC3_CH_BOTTOM_FRONT_WIDE_RIGHT
 
- UAC3_CH_BOTTOM_SIDE_LEFT
 
- UAC3_CH_BOTTOM_SIDE_RIGHT
 
- UAC3_CH_BOTTOM_SURR_ARRAY_LEFT
 
- UAC3_CH_BOTTOM_SURR_ARRAY_RIGHT
 
- UAC3_CH_FRONT_CENTER
 
- UAC3_CH_FRONT_LEFT
 
- UAC3_CH_FRONT_LEFT_OF_CENTER
 
- UAC3_CH_FRONT_RIGHT
 
- UAC3_CH_FRONT_RIGHT_OF_CENTER
 
- UAC3_CH_FRONT_WIDE_LEFT
 
- UAC3_CH_FRONT_WIDE_RIGHT
 
- UAC3_CH_HEADPHONE_LEFT
 
- UAC3_CH_HEADPHONE_RIGHT
 
- UAC3_CH_LEFT
 
- UAC3_CH_LFE_LEFT
 
- UAC3_CH_LFE_RIGHT
 
- UAC3_CH_LOW_FREQUENCY_EFFECTS
 
- UAC3_CH_MONO
 
- UAC3_CH_PATTERN_A
 
- UAC3_CH_PATTERN_B
 
- UAC3_CH_PATTERN_M
 
- UAC3_CH_PATTERN_S
 
- UAC3_CH_PATTERN_X
 
- UAC3_CH_PATTERN_Y
 
- UAC3_CH_RELATIONSHIP_UNDEFINED
 
- UAC3_CH_RIGHT
 
- UAC3_CH_SIDE_LEFT
 
- UAC3_CH_SIDE_RIGHT
 
- UAC3_CH_SURROUND_ARRAY_LEFT
 
- UAC3_CH_SURROUND_ARRAY_RIGHT
 
- UAC3_CH_TOP_BACK_CENTER
 
- UAC3_CH_TOP_BACK_LEFT
 
- UAC3_CH_TOP_BACK_LOC
 
- UAC3_CH_TOP_BACK_RIGHT
 
- UAC3_CH_TOP_BACK_ROC
 
- UAC3_CH_TOP_BACK_WIDE_LEFT
 
- UAC3_CH_TOP_BACK_WIDE_RIGHT
 
- UAC3_CH_TOP_CENTER
 
- UAC3_CH_TOP_FRONT_CENTER
 
- UAC3_CH_TOP_FRONT_LEFT
 
- UAC3_CH_TOP_FRONT_LOC
 
- UAC3_CH_TOP_FRONT_RIGHT
 
- UAC3_CH_TOP_FRONT_ROC
 
- UAC3_CH_TOP_FRONT_WIDE_LEFT
 
- UAC3_CH_TOP_FRONT_WIDE_RIGHT
 
- UAC3_CH_TOP_SIDE_LEFT
 
- UAC3_CH_TOP_SIDE_RIGHT
 
- UAC3_CH_TOP_SURR_ARRAY_LEFT
 
- UAC3_CH_TOP_SURR_ARRAY_RIGHT
 
- UAC3_CLOCK_MULTIPLIER
 
- UAC3_CLOCK_SELECTOR
 
- UAC3_CLOCK_SOURCE
 
- UAC3_CLOCK_SOURCE_ASYNC
 
- UAC3_CLOCK_SOURCE_SYNCED_TO_SOF
 
- UAC3_CLOCK_SOURCE_TYPE_EXT
 
- UAC3_CLOCK_SOURCE_TYPE_INT
 
- UAC3_CLUSTER_DESCRIPTION
 
- UAC3_CLUSTER_VENDOR_DEFINED
 
- UAC3_CONNECTORS
 
- UAC3_CS_CLUSTER
 
- UAC3_CS_CONFIGURATION
 
- UAC3_CS_DEVICE
 
- UAC3_CS_ENDPOINT
 
- UAC3_CS_INTERFACE
 
- UAC3_CS_REQ_HIGH_CAPABILITY_DESCRIPTOR
 
- UAC3_CS_REQ_INTEN
 
- UAC3_CS_REQ_STRING
 
- UAC3_CS_STRING
 
- UAC3_CS_UNDEFINED
 
- UAC3_DT_FEATURE_UNIT_SIZE
 
- UAC3_EFFECT_UNIT
 
- UAC3_END_SEGMENT
 
- UAC3_EXTENDED_TERMINAL
 
- UAC3_EXTENSION_UNIT
 
- UAC3_EXT_WIDTH_CONTROL
 
- UAC3_FEATURE_UNIT
 
- UAC3_FORMAT_TYPE_I_RAW_DATA
 
- UAC3_FUNCTION_AUDIO_VIDEO
 
- UAC3_FUNCTION_CONTROL_PANEL
 
- UAC3_FUNCTION_CONVERTER
 
- UAC3_FUNCTION_DESKTOP_SPEAKER
 
- UAC3_FUNCTION_GENERIC_SPEAKER
 
- UAC3_FUNCTION_HEADPHONE
 
- UAC3_FUNCTION_HEADSET
 
- UAC3_FUNCTION_HEADSET_ADAPTER
 
- UAC3_FUNCTION_HOME_THEATER
 
- UAC3_FUNCTION_IO_BOX
 
- UAC3_FUNCTION_MICROPHONE
 
- UAC3_FUNCTION_MUSICAL_INSTRUMENT
 
- UAC3_FUNCTION_OTHER
 
- UAC3_FUNCTION_PRO_AUDIO
 
- UAC3_FUNCTION_SOUND_RECORDER
 
- UAC3_FUNCTION_SPEAKERPHONE
 
- UAC3_FUNCTION_SUBCLASS_FULL_ADC_3_0
 
- UAC3_FUNCTION_SUBCLASS_GENERIC_IO
 
- UAC3_FUNCTION_SUBCLASS_HEADPHONE
 
- UAC3_FUNCTION_SUBCLASS_HEADSET
 
- UAC3_FUNCTION_SUBCLASS_HEADSET_ADAPTER
 
- UAC3_FUNCTION_SUBCLASS_MICROPHONE
 
- UAC3_FUNCTION_SUBCLASS_SPEAKER
 
- UAC3_FUNCTION_SUBCLASS_SPEAKERPHONE
 
- UAC3_FUNCTION_SUBCLASS_UNDEFINED
 
- UAC3_FUNCTION_TELEPHONE
 
- UAC3_MIXER_UNIT
 
- UAC3_PD_STATE_D0
 
- UAC3_PD_STATE_D1
 
- UAC3_PD_STATE_D2
 
- UAC3_POWER_DOMAIN
 
- UAC3_PROCESSING_UNIT
 
- UAC3_PROCESS_MULTI_FUNCTION
 
- UAC3_PROCESS_STEREO_EXTENDER
 
- UAC3_PROCESS_UNDEFINED
 
- UAC3_PROCESS_UP_DOWNMIX
 
- UAC3_PURPOSE_AMBIENT
 
- UAC3_PURPOSE_GENERIC_AUDIO
 
- UAC3_PURPOSE_NON_AUDIO
 
- UAC3_PURPOSE_REFERENCE
 
- UAC3_PURPOSE_SPEECH
 
- UAC3_PURPOSE_ULTRASONIC
 
- UAC3_PURPOSE_UNDEFINED
 
- UAC3_PURPOSE_VIBROKINETIC
 
- UAC3_PURPOSE_VOICE
 
- UAC3_SAMPLE_RATE_CONVERTER
 
- UAC3_SEGMENT_UNDEFINED
 
- UAC3_SELECTOR_UNIT
 
- UAC3_TE_INSERTION
 
- UAC3_TE_LATENCY
 
- UAC3_TE_OVERFLOW
 
- UAC3_TE_OVERLOAD
 
- UAC3_TE_UNDEFINED
 
- UAC3_TE_UNDERFLOW
 
- UAC3_UD_MODE_SELECT
 
- UACCESS_H
 
- UACT
 
- UAC_3D_ENABLE
 
- UAC_3D_SPACE
 
- UAC_AS_GENERAL
 
- UAC_BIDIR_TERMINAL_ECHO_CANCELING
 
- UAC_BIDIR_TERMINAL_ECHO_SUPPRESSING
 
- UAC_BIDIR_TERMINAL_HANDSET
 
- UAC_BIDIR_TERMINAL_HEADSET
 
- UAC_BIDIR_TERMINAL_SPEAKER_PHONE
 
- UAC_BIDIR_TERMINAL_UNDEFINED
 
- UAC_BITMASK
 
- UAC_CHORUS_DEPTH
 
- UAC_CHORUS_ENABLE
 
- UAC_CHORUS_LEVEL
 
- UAC_CHORUS_RATE
 
- UAC_CLOCK_SOURCE_SYNCED_TO_SOF
 
- UAC_CLOCK_SOURCE_TYPE_EXT
 
- UAC_CLOCK_SOURCE_TYPE_INT_FIXED
 
- UAC_CLOCK_SOURCE_TYPE_INT_PROG
 
- UAC_CLOCK_SOURCE_TYPE_INT_VAR
 
- UAC_CONTROL_BIT
 
- UAC_DCR_ATTACK_TIME
 
- UAC_DCR_ENABLE
 
- UAC_DCR_MAXAMPL
 
- UAC_DCR_RATE
 
- UAC_DCR_RELEASE_TIME
 
- UAC_DCR_THRESHOLD
 
- UAC_DP_ENABLE
 
- UAC_DP_MODE_SELECT
 
- UAC_DT_AC_HEADER_LENGTH
 
- UAC_DT_AC_HEADER_SIZE
 
- UAC_DT_AS_HEADER_SIZE
 
- UAC_DT_FEATURE_UNIT_SIZE
 
- UAC_DT_INPUT_TERMINAL_SIZE
 
- UAC_DT_OUTPUT_TERMINAL_SIZE
 
- UAC_DT_TOTAL_LENGTH
 
- UAC_EP_CS_ATTR_FILL_MAX
 
- UAC_EP_CS_ATTR_PITCH_CONTROL
 
- UAC_EP_CS_ATTR_SAMPLE_RATE
 
- UAC_EP_GENERAL
 
- UAC_EXT_FORMAT_TYPE_I
 
- UAC_EXT_FORMAT_TYPE_II
 
- UAC_EXT_FORMAT_TYPE_III
 
- UAC_FEATURE_UNIT
 
- UAC_FORMAT_SPECIFIC
 
- UAC_FORMAT_TYPE
 
- UAC_FORMAT_TYPE_I
 
- UAC_FORMAT_TYPE_II
 
- UAC_FORMAT_TYPE_III
 
- UAC_FORMAT_TYPE_III_IEC1937_AC3
 
- UAC_FORMAT_TYPE_III_IEC1937_MPEG1_LAYER1
 
- UAC_FORMAT_TYPE_III_IEC1937_MPEG2_EXT
 
- UAC_FORMAT_TYPE_III_IEC1937_MPEG2_LAYER1_LS
 
- UAC_FORMAT_TYPE_III_IEC1937_MPEG2_LAYER23_LS
 
- UAC_FORMAT_TYPE_III_IEC1937_MPEG2_NOEXT
 
- UAC_FORMAT_TYPE_II_AC3
 
- UAC_FORMAT_TYPE_II_MPEG
 
- UAC_FORMAT_TYPE_I_ALAW
 
- UAC_FORMAT_TYPE_I_CONTINUOUS_DESC_SIZE
 
- UAC_FORMAT_TYPE_I_DISCRETE_DESC_SIZE
 
- UAC_FORMAT_TYPE_I_IEEE_FLOAT
 
- UAC_FORMAT_TYPE_I_MULAW
 
- UAC_FORMAT_TYPE_I_PCM
 
- UAC_FORMAT_TYPE_I_PCM8
 
- UAC_FORMAT_TYPE_I_UNDEFINED
 
- UAC_FORMAT_TYPE_UNDEFINED
 
- UAC_FU_AUTOMATIC_GAIN
 
- UAC_FU_BASS
 
- UAC_FU_BASS_BOOST
 
- UAC_FU_DELAY
 
- UAC_FU_GRAPHIC_EQUALIZER
 
- UAC_FU_LOUDNESS
 
- UAC_FU_MID
 
- UAC_FU_MUTE
 
- UAC_FU_TREBLE
 
- UAC_FU_VOLUME
 
- UAC_GET_
 
- UAC_GET_CUR
 
- UAC_GET_MAX
 
- UAC_GET_MEM
 
- UAC_GET_MIN
 
- UAC_GET_RES
 
- UAC_GET_STAT
 
- UAC_HEADER
 
- UAC_INPUT_TERMINAL
 
- UAC_INPUT_TERMINAL_DESKTOP_MICROPHONE
 
- UAC_INPUT_TERMINAL_MICROPHONE
 
- UAC_INPUT_TERMINAL_MICROPHONE_ARRAY
 
- UAC_INPUT_TERMINAL_OMNI_DIR_MICROPHONE
 
- UAC_INPUT_TERMINAL_PERSONAL_MICROPHONE
 
- UAC_INPUT_TERMINAL_PROC_MICROPHONE_ARRAY
 
- UAC_INPUT_TERMINAL_UNDEFINED
 
- UAC_ISO_ENDPOINT_DESC_SIZE
 
- UAC_MIDI_IN_JACK
 
- UAC_MIDI_OUT_JACK
 
- UAC_MIXER_UNIT
 
- UAC_MS_GENERAL
 
- UAC_MS_HEADER
 
- UAC_NOFIX
 
- UAC_NOPRINT
 
- UAC_OUTPUT_TERMINAL
 
- UAC_OUTPUT_TERMINAL_COMMUNICATION_SPEAKER
 
- UAC_OUTPUT_TERMINAL_DESKTOP_SPEAKER
 
- UAC_OUTPUT_TERMINAL_HEADPHONES
 
- UAC_OUTPUT_TERMINAL_HEAD_MOUNTED_DISPLAY_AUDIO
 
- UAC_OUTPUT_TERMINAL_LOW_FREQ_EFFECTS_SPEAKER
 
- UAC_OUTPUT_TERMINAL_ROOM_SPEAKER
 
- UAC_OUTPUT_TERMINAL_SPEAKER
 
- UAC_OUTPUT_TERMINAL_UNDEFINED
 
- UAC_PROCESS_CHORUS
 
- UAC_PROCESS_DOLBY_PROLOGIC
 
- UAC_PROCESS_DYN_RANGE_COMP
 
- UAC_PROCESS_REVERB
 
- UAC_PROCESS_STEREO_EXTENDER
 
- UAC_PROCESS_UNDEFINED
 
- UAC_PROCESS_UP_DOWNMIX
 
- UAC_REVERB_ENABLE
 
- UAC_REVERB_FEEDBACK
 
- UAC_REVERB_LEVEL
 
- UAC_REVERB_TIME
 
- UAC_SELECTOR_UNIT
 
- UAC_SET_
 
- UAC_SET_CUR
 
- UAC_SET_MAX
 
- UAC_SET_MEM
 
- UAC_SET_MIN
 
- UAC_SET_RES
 
- UAC_SIGBUS
 
- UAC_TERMINAL_CS_COPY_PROTECT_CONTROL
 
- UAC_TERMINAL_STREAMING
 
- UAC_TERMINAL_UNDEFINED
 
- UAC_TERMINAL_VENDOR_SPEC
 
- UAC_TERM_COPY_PROTECT
 
- UAC_UD_ENABLE
 
- UAC_UD_MODE_SELECT
 
- UAC_VERSION_1
 
- UAC_VERSION_2
 
- UAC_VERSION_3
 
- UAC_VERSION_ALL
 
- UAC_XU_ENABLE
 
- UAC__CUR
 
- UAC__MAX
 
- UAC__MEM
 
- UAC__MIN
 
- UAC__RES
 
- UAE2BIG
 
- UAEACCES
 
- UAEADDRINUSE
 
- UAEADDRNOTAVAIL
 
- UAEADV
 
- UAEAFNOSUPPORT
 
- UAEAGAIN
 
- UAEALREADY
 
- UAEBADE
 
- UAEBADF
 
- UAEBADFD
 
- UAEBADMSG
 
- UAEBADR
 
- UAEBADRQC
 
- UAEBADSLT
 
- UAEBFONT
 
- UAEBUSY
 
- UAECHILD
 
- UAECHRNG
 
- UAECOMM
 
- UAECONNABORTED
 
- UAECONNREFUSED
 
- UAECONNRESET
 
- UAEDEADLK
 
- UAEDESTADDRREQ
 
- UAEDOM
 
- UAEDOTDOT
 
- UAEDQUOT
 
- UAEEXIST
 
- UAEFAULT
 
- UAEFBIG
 
- UAEHOSTDOWN
 
- UAEHOSTUNREACH
 
- UAEIDRM
 
- UAEILSEQ
 
- UAEINPROGRESS
 
- UAEINTR
 
- UAEINVAL
 
- UAEIO
 
- UAEISCONN
 
- UAEISDIR
 
- UAEISNAM
 
- UAEL2HLT
 
- UAEL2NSYNC
 
- UAEL3HLT
 
- UAEL3RST
 
- UAELIBACC
 
- UAELIBBAD
 
- UAELIBEXEC
 
- UAELIBMAX
 
- UAELIBSCN
 
- UAELNRNG
 
- UAELOOP
 
- UAEMEDIUMTYPE
 
- UAEMFILE
 
- UAEMLINK
 
- UAEMSGSIZE
 
- UAEMULTIHOP
 
- UAENAMETOOLONG
 
- UAENAVAIL
 
- UAENETDOWN
 
- UAENETRESET
 
- UAENETUNREACH
 
- UAENFILE
 
- UAENOANO
 
- UAENOBUFS
 
- UAENOCSI
 
- UAENODATA
 
- UAENODEV
 
- UAENOENT
 
- UAENOEXEC
 
- UAENOLCK
 
- UAENOLINK
 
- UAENOMEDIUM
 
- UAENOMEM
 
- UAENOMSG
 
- UAENONET
 
- UAENOPKG
 
- UAENOPROTOOPT
 
- UAENOSPC
 
- UAENOSR
 
- UAENOSTR
 
- UAENOSYS
 
- UAENOTBLK
 
- UAENOTCONN
 
- UAENOTDIR
 
- UAENOTEMPTY
 
- UAENOTNAM
 
- UAENOTSOCK
 
- UAENOTTY
 
- UAENOTUNIQ
 
- UAENXIO
 
- UAEOPNOTSUPP
 
- UAEOVERFLOW
 
- UAEPERM
 
- UAEPFNOSUPPORT
 
- UAEPIPE
 
- UAEPROTO
 
- UAEPROTONOSUPPORT
 
- UAEPROTOTYPE
 
- UAERANGE
 
- UAEREMCHG
 
- UAEREMOTE
 
- UAEREMOTEIO
 
- UAERESTART
 
- UAEROFS
 
- UAESHUTDOWN
 
- UAESOCKTNOSUPPORT
 
- UAESPIPE
 
- UAESRCH
 
- UAESRMNT
 
- UAESTALE
 
- UAESTRPIPE
 
- UAETIME
 
- UAETIMEDOUT
 
- UAETOOMANYREFS
 
- UAETXTBSY
 
- UAEUCLEAN
 
- UAEUNATCH
 
- UAEUSERS
 
- UAEWOULDBLOCK
 
- UAEXDEV
 
- UAEXFULL
 
- UAE_DUMMY
 
- UAIMI_SPR1
 
- UALIAS_BASE
 
- UALIAS_FLIP_ADDR
 
- UALIAS_FLIP_BASE
 
- UALIAS_FLIP_BIT
 
- UALIAS_FLIP_SIZE
 
- UALIAS_LIMIT
 
- UALIAS_SIZE
 
- UAPI_DEF_CHAIN
 
- UAPI_DEF_CHAIN_OBJ_TREE
 
- UAPI_DEF_CHAIN_OBJ_TREE_NAMED
 
- UAPI_DEF_END
 
- UAPI_DEF_IS_OBJ_SUPPORTED
 
- UAPI_DEF_IS_SUPPORTED_DEV_FN
 
- UAPI_DEF_IS_SUPPORTED_FUNC
 
- UAPI_DEF_METHOD_NEEDS_FN
 
- UAPI_DEF_OBJECT_START
 
- UAPI_DEF_OBJ_NEEDS_FN
 
- UAPI_DEF_WRITE
 
- UAPI_DEF_WRITE_I
 
- UAPI_DEF_WRITE_IO
 
- UAPI_DEF_WRITE_IO_EX
 
- UAPI_DEF_WRITE_I_EX
 
- UAPI_DEF_WRITE_UDATA_I
 
- UAPI_DEF_WRITE_UDATA_IO
 
- UAPI_SCOPE_METHOD
 
- UAPI_SCOPE_OBJECT
 
- UAPSD_MAX_SP
 
- UAP_BSS_PARAMS_I
 
- UAP_CUSTOM_IE_I
 
- UARM_HW_CGC_EN
 
- UARROW_CHAR
 
- UART
 
- UART010_CR
 
- UART010_CR_MSIE
 
- UART010_CR_RIE
 
- UART010_CR_RTIE
 
- UART010_CR_TIE
 
- UART010_ICR
 
- UART010_IIR
 
- UART010_IIR_MIS
 
- UART010_IIR_RIS
 
- UART010_IIR_RTIS
 
- UART010_IIR_TIS
 
- UART010_LCRH
 
- UART010_LCRL
 
- UART010_LCRM
 
- UART011_BEIC
 
- UART011_BEIM
 
- UART011_BEIS
 
- UART011_CR
 
- UART011_CR_CTSEN
 
- UART011_CR_DTR
 
- UART011_CR_LBE
 
- UART011_CR_OUT1
 
- UART011_CR_OUT2
 
- UART011_CR_RTS
 
- UART011_CR_RTSEN
 
- UART011_CR_RXE
 
- UART011_CR_TXE
 
- UART011_CTSMIC
 
- UART011_CTSMIM
 
- UART011_CTSMIS
 
- UART011_DCDMIC
 
- UART011_DCDMIM
 
- UART011_DCDMIS
 
- UART011_DMACR
 
- UART011_DMAONERR
 
- UART011_DR_BE
 
- UART011_DR_FE
 
- UART011_DR_OE
 
- UART011_DR_PE
 
- UART011_DSRMIC
 
- UART011_DSRMIM
 
- UART011_DSRMIS
 
- UART011_FBRD
 
- UART011_FEIC
 
- UART011_FEIM
 
- UART011_FEIS
 
- UART011_FR_RI
 
- UART011_FR_RXFF
 
- UART011_FR_TXFE
 
- UART011_IBRD
 
- UART011_ICR
 
- UART011_IFLS
 
- UART011_IFLS_RX1_8
 
- UART011_IFLS_RX2_8
 
- UART011_IFLS_RX4_8
 
- UART011_IFLS_RX6_8
 
- UART011_IFLS_RX7_8
 
- UART011_IFLS_RX_HALF
 
- UART011_IFLS_TX1_8
 
- UART011_IFLS_TX2_8
 
- UART011_IFLS_TX4_8
 
- UART011_IFLS_TX6_8
 
- UART011_IFLS_TX7_8
 
- UART011_IFLS_TX_HALF
 
- UART011_IMSC
 
- UART011_LCRH
 
- UART011_LCRH_SPS
 
- UART011_MIS
 
- UART011_OEIC
 
- UART011_OEIM
 
- UART011_OEIS
 
- UART011_PEIC
 
- UART011_PEIM
 
- UART011_PEIS
 
- UART011_RIMIC
 
- UART011_RIMIM
 
- UART011_RIMIS
 
- UART011_RIS
 
- UART011_RTIC
 
- UART011_RTIM
 
- UART011_RTIS
 
- UART011_RXDMAE
 
- UART011_RXIC
 
- UART011_RXIM
 
- UART011_RXIS
 
- UART011_TXDMAE
 
- UART011_TXIC
 
- UART011_TXIM
 
- UART011_TXIS
 
- UART01x_CR_IIRLP
 
- UART01x_CR_SIREN
 
- UART01x_CR_UARTEN
 
- UART01x_DR
 
- UART01x_ECR
 
- UART01x_FR
 
- UART01x_FR_BUSY
 
- UART01x_FR_CTS
 
- UART01x_FR_DCD
 
- UART01x_FR_DSR
 
- UART01x_FR_MODEM_ANY
 
- UART01x_FR_RXFE
 
- UART01x_FR_TMSK
 
- UART01x_FR_TXFF
 
- UART01x_ILPR
 
- UART01x_LCRH_BRK
 
- UART01x_LCRH_EPS
 
- UART01x_LCRH_FEN
 
- UART01x_LCRH_PEN
 
- UART01x_LCRH_STP2
 
- UART01x_LCRH_WLEN_5
 
- UART01x_LCRH_WLEN_6
 
- UART01x_LCRH_WLEN_7
 
- UART01x_LCRH_WLEN_8
 
- UART01x_RSR
 
- UART01x_RSR_ANY
 
- UART01x_RSR_BE
 
- UART01x_RSR_FE
 
- UART01x_RSR_OE
 
- UART01x_RSR_PE
 
- UART0BASE
 
- UART0_BASE
 
- UART0_BUFFER_CSR
 
- UART0_CLK_ENB
 
- UART0_ENABLE_MASK
 
- UART0_ENH_AND_GPT_REG0_MASK
 
- UART0_FRAME_CSR
 
- UART0_IRQ
 
- UART0_PHYS
 
- UART0_PHYS_BASE
 
- UART0_REF
 
- UART0_REG2_MASK
 
- UART0_RESET
 
- UART0_RX
 
- UART0_RXD
 
- UART0_RX_CSR
 
- UART0_SHUT
 
- UART0_STATUS_REG
 
- UART0_TX
 
- UART0_TXD
 
- UART0_TX_CSR
 
- UART0_USE_PWM01
 
- UART0_USE_PWM23
 
- UART0_VIRT
 
- UART0_VIRT_BASE
 
- UART1_2_USE_CAN0
 
- UART1_3_USE_CAN1
 
- UART1_CLK_ENB
 
- UART1_CTSB_MARK
 
- UART1_ENABLE_MASK
 
- UART1_GPIO_SEL
 
- UART1_IRQ
 
- UART1_IRQ_NUM
 
- UART1_PCLK_MASK
 
- UART1_PCLK_SHIFT
 
- UART1_PHYS
 
- UART1_PHYS_BASE
 
- UART1_REF
 
- UART1_REG
 
- UART1_REG2_MASK
 
- UART1_RESET
 
- UART1_RTS
 
- UART1_RTSB_MARK
 
- UART1_RX_MARK
 
- UART1_SHUT
 
- UART1_STATUS_REG
 
- UART1_TX
 
- UART1_TX_MARK
 
- UART1_USE_LCD0_5_6_11
 
- UART1_VIRT
 
- UART1_VIRT_BASE
 
- UART2CSR0
 
- UART2CSR1
 
- UART2CSR3
 
- UART2CSR4
 
- UART2_CTS
 
- UART2_CTSB
 
- UART2_ENABLE_MASK
 
- UART2_IRQ
 
- UART2_IRQ_NUM
 
- UART2_PHYS_BASE
 
- UART2_RTS
 
- UART2_RTSB
 
- UART2_RX
 
- UART2_RX_MARK
 
- UART2_SHUT
 
- UART2_TX
 
- UART2_TX_MARK
 
- UART2_VIRT_BASE
 
- UART3_ACREG
 
- UART3_BCLK
 
- UART3_BLR
 
- UART3_CLKREQ
 
- UART3_CTS
 
- UART3_CTSB
 
- UART3_DIV16
 
- UART3_DLH
 
- UART3_DLL
 
- UART3_EBLR
 
- UART3_EFR
 
- UART3_FCR
 
- UART3_IER
 
- UART3_IIR
 
- UART3_LCR
 
- UART3_LSR
 
- UART3_MCR
 
- UART3_MDR1
 
- UART3_MDR2
 
- UART3_MSR
 
- UART3_MVR
 
- UART3_OSC_12M_SEL
 
- UART3_PHYS_BASE
 
- UART3_RESUME
 
- UART3_RHR
 
- UART3_RTS
 
- UART3_RTSB
 
- UART3_RX
 
- UART3_RXFLH
 
- UART3_RXFLL
 
- UART3_RX_MARK
 
- UART3_SCR
 
- UART3_SFLSR
 
- UART3_SFREGH
 
- UART3_SFREGL
 
- UART3_SHUT
 
- UART3_SPR
 
- UART3_SSR
 
- UART3_TCR
 
- UART3_THR
 
- UART3_TLR
 
- UART3_TX
 
- UART3_TXFLH
 
- UART3_TXFLL
 
- UART3_TX_MARK
 
- UART3_VIRT_BASE
 
- UART3_XOFF1
 
- UART3_XOFF2
 
- UART3_XON1_ADDR1
 
- UART3_XON2_ADDR2
 
- UART4
 
- UART4_CK
 
- UART4_K
 
- UART4_R
 
- UART4_RX
 
- UART4_TX
 
- UART5
 
- UART5_CK
 
- UART5_K
 
- UART5_R
 
- UART6_DESC
 
- UART7
 
- UART7_K
 
- UART7_R
 
- UART8
 
- UART8_K
 
- UART8_R
 
- UARTA_3390
 
- UARTA_7250
 
- UARTA_7255
 
- UARTA_7260
 
- UARTA_7268
 
- UARTA_7271
 
- UARTA_7278
 
- UARTA_7364
 
- UARTA_7366
 
- UARTA_74371
 
- UARTA_7439
 
- UARTA_7445
 
- UARTA_BASE
 
- UARTA_BASE_ADDR
 
- UARTBAUD
 
- UARTBAUD_BOTHEDGE
 
- UARTBAUD_LBKDIE
 
- UARTBAUD_M10
 
- UARTBAUD_MAEN1
 
- UARTBAUD_MAEN2
 
- UARTBAUD_MATCFG
 
- UARTBAUD_OSR_MASK
 
- UARTBAUD_OSR_SHIFT
 
- UARTBAUD_RDMAE
 
- UARTBAUD_RESYNCDIS
 
- UARTBAUD_RXEDGIE
 
- UARTBAUD_SBNS
 
- UARTBAUD_SBR
 
- UARTBAUD_SBR_MASK
 
- UARTBAUD_TDMAE
 
- UARTBDH
 
- UARTBDH_LBKDIE
 
- UARTBDH_RXEDGIE
 
- UARTBDH_SBR_MASK
 
- UARTBDL
 
- UARTB_BASE
 
- UARTB_BASE_ADDR
 
- UARTCFIFO
 
- UARTCFIFO_RXFLUSH
 
- UARTCFIFO_RXOFE
 
- UARTCFIFO_RXUFE
 
- UARTCFIFO_TXFLUSH
 
- UARTCFIFO_TXOFE
 
- UARTCMA
 
- UARTCMB
 
- UARTCR
 
- UARTCR1
 
- UARTCR1_ILT
 
- UARTCR1_LOOPS
 
- UARTCR1_M
 
- UARTCR1_PE
 
- UARTCR1_PT
 
- UARTCR1_RSRC
 
- UARTCR1_WAKE
 
- UARTCR2
 
- UARTCR2_ILIE
 
- UARTCR2_RE
 
- UARTCR2_RIE
 
- UARTCR2_RWU
 
- UARTCR2_SBK
 
- UARTCR2_TCIE
 
- UARTCR2_TE
 
- UARTCR2_TIE
 
- UARTCR3
 
- UARTCR3_FEIE
 
- UARTCR3_NEIE
 
- UARTCR3_ORIE
 
- UARTCR3_PEIE
 
- UARTCR3_R8
 
- UARTCR3_T8
 
- UARTCR3_TXDIR
 
- UARTCR3_TXINV
 
- UARTCR4
 
- UARTCR4_BRFA_MASK
 
- UARTCR4_BRFA_OFF
 
- UARTCR4_M10
 
- UARTCR4_MAEN1
 
- UARTCR4_MAEN2
 
- UARTCR5
 
- UARTCR5_RDMAS
 
- UARTCR5_TDMAS
 
- UARTCSR0
 
- UARTCSR1
 
- UARTCSR3
 
- UARTCSR4
 
- UARTCTO
 
- UARTCTRL
 
- UARTCTRL_DOZEEN
 
- UARTCTRL_FEIE
 
- UARTCTRL_IDLECFG
 
- UARTCTRL_ILIE
 
- UARTCTRL_ILT
 
- UARTCTRL_LOOPS
 
- UARTCTRL_M
 
- UARTCTRL_MA1IE
 
- UARTCTRL_MA2IE
 
- UARTCTRL_NEIE
 
- UARTCTRL_ORIE
 
- UARTCTRL_PE
 
- UARTCTRL_PEIE
 
- UARTCTRL_PT
 
- UARTCTRL_R8T9
 
- UARTCTRL_R9T8
 
- UARTCTRL_RE
 
- UARTCTRL_RIE
 
- UARTCTRL_RSRC
 
- UARTCTRL_RWU
 
- UARTCTRL_SBK
 
- UARTCTRL_TCIE
 
- UARTCTRL_TE
 
- UARTCTRL_TIE
 
- UARTCTRL_TXDIR
 
- UARTCTRL_TXINV
 
- UARTCTRL_WAKE
 
- UARTDATA
 
- UARTDATA_FRETSC
 
- UARTDATA_IDLINE
 
- UARTDATA_MASK
 
- UARTDATA_NOISY
 
- UARTDATA_PARITYE
 
- UARTDATA_RXEMPT
 
- UARTDM_1P1
 
- UARTDM_1P2
 
- UARTDM_1P3
 
- UARTDM_1P4
 
- UARTDM_BURST_SIZE
 
- UARTDM_DMEN
 
- UARTDM_DMEN_RX_BAM_ENABLE
 
- UARTDM_DMEN_RX_DM_ENABLE
 
- UARTDM_DMEN_RX_SC_ENABLE
 
- UARTDM_DMEN_TX_BAM_ENABLE
 
- UARTDM_DMEN_TX_DM_ENABLE
 
- UARTDM_DMEN_TX_SC_ENABLE
 
- UARTDM_DMRX
 
- UARTDM_NCF_TX
 
- UARTDM_RF
 
- UARTDM_RXFS
 
- UARTDM_RXFS_BUF_MASK
 
- UARTDM_RXFS_BUF_SHIFT
 
- UARTDM_RX_SIZE
 
- UARTDM_RX_TOTAL_SNAP
 
- UARTDM_TF
 
- UARTDM_TX_AIGN
 
- UARTDM_TX_MAX
 
- UARTDR
 
- UARTDR_FRMERR
 
- UARTDR_OFFSET
 
- UARTDR_OVERR
 
- UARTDR_PARERR
 
- UARTEND
 
- UARTFIFO
 
- UARTFIFO_DEPTH
 
- UARTFIFO_FIFOSIZE_MASK
 
- UARTFIFO_RXEMPT
 
- UARTFIFO_RXFE
 
- UARTFIFO_RXFLUSH
 
- UARTFIFO_RXSIZE_OFF
 
- UARTFIFO_RXUF
 
- UARTFIFO_RXUFE
 
- UARTFIFO_TXEMPT
 
- UARTFIFO_TXFE
 
- UARTFIFO_TXFLUSH
 
- UARTFIFO_TXOF
 
- UARTFIFO_TXOFE
 
- UARTFIFO_TXSIZE_OFF
 
- UARTIE
 
- UARTIP
 
- UARTLITEEND
 
- UARTLITEOFFSET
 
- UARTMATCH
 
- UARTMODEM
 
- UARTMODEM_RXRTSE
 
- UARTMODEM_TXCTSE
 
- UARTMODEM_TXRTSE
 
- UARTMODEM_TXRTSPOL
 
- UARTMODIR
 
- UARTMODIR_IREN
 
- UARTMODIR_RXRTSE
 
- UARTMODIR_TXCTSC
 
- UARTMODIR_TXCTSE
 
- UARTMODIR_TXCTSSRC
 
- UARTMODIR_TXRTSE
 
- UARTMODIR_TXRTSPOL
 
- UARTOFFSET
 
- UARTPFIFO
 
- UARTPFIFO_FIFOSIZE_MASK
 
- UARTPFIFO_RXFE
 
- UARTPFIFO_RXSIZE_OFF
 
- UARTPFIFO_TXFE
 
- UARTPFIFO_TXSIZE_OFF
 
- UARTPTO
 
- UARTRWFIFO
 
- UARTSFIFO
 
- UARTSFIFO_RXEMPT
 
- UARTSFIFO_RXOF
 
- UARTSFIFO_RXUF
 
- UARTSFIFO_TXEMPT
 
- UARTSFIFO_TXOF
 
- UARTSR
 
- UARTSR1
 
- UARTSR1_FE
 
- UARTSR1_IDLE
 
- UARTSR1_NF
 
- UARTSR1_OR
 
- UARTSR1_PE
 
- UARTSR1_RDRF
 
- UARTSR1_TC
 
- UARTSR1_TDRE
 
- UARTSTAT
 
- UARTSTAT_BRK13
 
- UARTSTAT_FE
 
- UARTSTAT_IDLE
 
- UARTSTAT_LBKDE
 
- UARTSTAT_LBKDIF
 
- UARTSTAT_M21F
 
- UARTSTAT_MA1F
 
- UARTSTAT_MSBF
 
- UARTSTAT_NF
 
- UARTSTAT_OR
 
- UARTSTAT_PE
 
- UARTSTAT_RAF
 
- UARTSTAT_RDRF
 
- UARTSTAT_RWUID
 
- UARTSTAT_RXEDGIF
 
- UARTSTAT_RXINV
 
- UARTSTAT_TC
 
- UARTSTAT_TDRE
 
- UARTTCFIFO
 
- UARTTWFIFO
 
- UARTWATER
 
- UARTWATER_COUNT_MASK
 
- UARTWATER_RXCNT_OFF
 
- UARTWATER_RXWATER_OFF
 
- UARTWATER_TXCNT_OFF
 
- UARTWATER_TXWATER_OFF
 
- UARTWATER_WATER_MASK
 
- UART_0_X_INT
 
- UART_16654_FCR_RXTRIGGER_16
 
- UART_16654_FCR_RXTRIGGER_56
 
- UART_16654_FCR_RXTRIGGER_60
 
- UART_16654_FCR_RXTRIGGER_8
 
- UART_16654_FCR_TXTRIGGER_16
 
- UART_16654_FCR_TXTRIGGER_32
 
- UART_16654_FCR_TXTRIGGER_56
 
- UART_16654_FCR_TXTRIGGER_8
 
- UART_17158_EFR_CTSDSR
 
- UART_17158_EFR_ECB
 
- UART_17158_EFR_IXOFF
 
- UART_17158_EFR_IXON
 
- UART_17158_EFR_RTSDTR
 
- UART_17158_FCTR_BIT6
 
- UART_17158_FCTR_BIT7
 
- UART_17158_FCTR_RS485
 
- UART_17158_FCTR_RTS_12DELAY
 
- UART_17158_FCTR_RTS_16DELAY
 
- UART_17158_FCTR_RTS_20DELAY
 
- UART_17158_FCTR_RTS_24DELAY
 
- UART_17158_FCTR_RTS_28DELAY
 
- UART_17158_FCTR_RTS_32DELAY
 
- UART_17158_FCTR_RTS_36DELAY
 
- UART_17158_FCTR_RTS_40DELAY
 
- UART_17158_FCTR_RTS_44DELAY
 
- UART_17158_FCTR_RTS_48DELAY
 
- UART_17158_FCTR_RTS_4DELAY
 
- UART_17158_FCTR_RTS_52DELAY
 
- UART_17158_FCTR_RTS_6DELAY
 
- UART_17158_FCTR_RTS_8DELAY
 
- UART_17158_FCTR_RTS_IRDA
 
- UART_17158_FCTR_RTS_NODELAY
 
- UART_17158_FCTR_TRGA
 
- UART_17158_FCTR_TRGB
 
- UART_17158_FCTR_TRGC
 
- UART_17158_FCTR_TRGD
 
- UART_17158_IER_CTSDSR
 
- UART_17158_IER_RSVD1
 
- UART_17158_IER_RTSDTR
 
- UART_17158_IER_XOFF
 
- UART_17158_IIR_FIFO_ENABLED
 
- UART_17158_IIR_HWFLOW_STATE_CHANGE
 
- UART_17158_IIR_RDI_TIMEOUT
 
- UART_17158_IIR_XONXOFF
 
- UART_17158_MSR
 
- UART_17158_POLL_ADDR_OFFSET
 
- UART_17158_RXRDY_TIMEOUT
 
- UART_17158_RX_FIFOSIZE
 
- UART_17158_RX_FIFO_DATA_ERROR
 
- UART_17158_RX_LINE_STATUS
 
- UART_17158_TXRDY
 
- UART_17158_TX_AND_FIFO_CLR
 
- UART_17158_TX_FIFOSIZE
 
- UART_17158_XOFF_DETECT
 
- UART_17158_XON_DETECT
 
- UART_1_X_INT
 
- UART_7XX_1
 
- UART_7XX_2
 
- UART_910
 
- UART_ACR
 
- UART_ACR_ASREN
 
- UART_ACR_DSRFC
 
- UART_ACR_ICRRD
 
- UART_ACR_RXDIS
 
- UART_ACR_TLENB
 
- UART_ACR_TXDIS
 
- UART_ALL_IRQ_DISABLE
 
- UART_ALL_IRQ_ENABLE
 
- UART_ALTR_AFR
 
- UART_ALTR_EN_TXFIFO_LW
 
- UART_ALTR_TX_LOW
 
- UART_ASR
 
- UART_AUTOSUSPEND_TIMEOUT
 
- UART_A_REGISTER_BASE
 
- UART_BASE
 
- UART_BASE_ADD
 
- UART_BAUD
 
- UART_BAUD_REG
 
- UART_BRD
 
- UART_BRDV
 
- UART_BREAK_ERROR
 
- UART_BUG_NOMSR
 
- UART_BUG_PARITY
 
- UART_BUG_QUOT
 
- UART_BUG_THRE
 
- UART_BUG_TXEN
 
- UART_BUILD_REVISION
 
- UART_B_REGISTER_BASE
 
- UART_CAP_AFE
 
- UART_CAP_EFR
 
- UART_CAP_FIFO
 
- UART_CAP_HFIFO
 
- UART_CAP_IRDA
 
- UART_CAP_MINI
 
- UART_CAP_RPM
 
- UART_CAP_RTOIE
 
- UART_CAP_SLEEP
 
- UART_CAP_UUE
 
- UART_CD
 
- UART_CKS
 
- UART_CLASSIC_POLL_ADDR_OFFSET
 
- UART_CLEAR_FIFO
 
- UART_CLK
 
- UART_CLK_DEFAULT
 
- UART_CLK_ENB
 
- UART_CLK_MASK
 
- UART_CLK_SHIFT
 
- UART_CLK_SYNT
 
- UART_CLOCK
 
- UART_CLPS711X_DEVNAME
 
- UART_CLPS711X_MAJOR
 
- UART_CLPS711X_MINOR
 
- UART_CLPS711X_NR
 
- UART_CLR_STATUS
 
- UART_CNT
 
- UART_CONFIG_IRQ
 
- UART_CONFIG_TYPE
 
- UART_CPR
 
- UART_CR
 
- UART_CR_CMD_FORCE_STALE
 
- UART_CR_CMD_MODE_RESET
 
- UART_CR_CMD_NULL
 
- UART_CR_CMD_PACKET_MODE
 
- UART_CR_CMD_PROTECTION_EN
 
- UART_CR_CMD_RESET_BREAK_INT
 
- UART_CR_CMD_RESET_CTS
 
- UART_CR_CMD_RESET_ERR
 
- UART_CR_CMD_RESET_RFR
 
- UART_CR_CMD_RESET_RX
 
- UART_CR_CMD_RESET_RXBREAK_START
 
- UART_CR_CMD_RESET_STALE_INT
 
- UART_CR_CMD_RESET_TX
 
- UART_CR_CMD_RESET_TX_READY
 
- UART_CR_CMD_SET_RFR
 
- UART_CR_CMD_STALE_EVENT_DISABLE
 
- UART_CR_CMD_STALE_EVENT_ENABLE
 
- UART_CR_CMD_START_BREAK
 
- UART_CR_CMD_STOP_BREAK
 
- UART_CR_OFFSET
 
- UART_CR_RX_DISABLE
 
- UART_CR_RX_ENABLE
 
- UART_CR_TX_DISABLE
 
- UART_CR_TX_ENABLE
 
- UART_CS
 
- UART_CSR
 
- UART_CTL
 
- UART_CTL_BITSPERSYM_MASK
 
- UART_CTL_BITSPERSYM_SHIFT
 
- UART_CTL_BRGEN_MASK
 
- UART_CTL_BRGEN_SHIFT
 
- UART_CTL_LOOPBACK_MASK
 
- UART_CTL_LOOPBACK_SHIFT
 
- UART_CTL_REG
 
- UART_CTL_RSTRXFIFO_MASK
 
- UART_CTL_RSTRXFIFO_SHIFT
 
- UART_CTL_RSTTXDN_MASK
 
- UART_CTL_RSTTXDN_SHIFT
 
- UART_CTL_RSTTXFIFO_MASK
 
- UART_CTL_RSTTXFIFO_SHIFT
 
- UART_CTL_RSVD_MASK
 
- UART_CTL_RSVD_SHIFT
 
- UART_CTL_RXEN_MASK
 
- UART_CTL_RXEN_SHIFT
 
- UART_CTL_RXPAREN_MASK
 
- UART_CTL_RXPAREN_SHIFT
 
- UART_CTL_RXPAREVEN_MASK
 
- UART_CTL_RXPAREVEN_SHIFT
 
- UART_CTL_RXTMOUTCNT_MASK
 
- UART_CTL_RXTMOUTCNT_SHIFT
 
- UART_CTL_STOPBITS_1
 
- UART_CTL_STOPBITS_2
 
- UART_CTL_STOPBITS_MASK
 
- UART_CTL_STOPBITS_SHIFT
 
- UART_CTL_TXEN_MASK
 
- UART_CTL_TXEN_SHIFT
 
- UART_CTL_TXPAREN_MASK
 
- UART_CTL_TXPAREN_SHIFT
 
- UART_CTL_TXPAREVEN_MASK
 
- UART_CTL_TXPAREVEN_SHIFT
 
- UART_CTL_XMITBRK_MASK
 
- UART_CTL_XMITBRK_SHIFT
 
- UART_CTR
 
- UART_CTRL
 
- UART_CTRL_FL
 
- UART_CTRL_LB
 
- UART_CTRL_PE
 
- UART_CTRL_PS
 
- UART_CTRL_RE
 
- UART_CTRL_RI
 
- UART_CTRL_TE
 
- UART_CTRL_TI
 
- UART_CTS
 
- UART_CTS_MASK
 
- UART_DA830_PWREMU_MGMT
 
- UART_DA830_PWREMU_MGMT_FREE
 
- UART_DA830_PWREMU_MGMT_URRST
 
- UART_DA830_PWREMU_MGMT_UTRST
 
- UART_DAVINCI_PWREMU
 
- UART_DBUF
 
- UART_DCD
 
- UART_DEV_NAME_LEN
 
- UART_DISABLE
 
- UART_DIV13_EN
 
- UART_DIVISOR
 
- UART_DIVISOR0
 
- UART_DIVISOR1
 
- UART_DIVISOR_DEFAULT
 
- UART_DIV_MAX
 
- UART_DLAB
 
- UART_DLL
 
- UART_DLL_EM
 
- UART_DLM
 
- UART_DLM_EM
 
- UART_DM646X_SCR
 
- UART_DM646X_SCR_TX_WATERMARK
 
- UART_DM_IPR_STALE_TIMEOUT_MSB
 
- UART_DM_MR1_AUTO_RFR_LEVEL1
 
- UART_DREG
 
- UART_DR_ERROR
 
- UART_DSR
 
- UART_DUMMY_DR_RX
 
- UART_DUMMY_RSR_RX
 
- UART_DUMMY_UER_RX
 
- UART_EFR
 
- UART_EFR_CTS
 
- UART_EFR_ECB
 
- UART_EFR_RTS
 
- UART_EFR_SCD
 
- UART_EMSR
 
- UART_EMSR_ALT_COUNT
 
- UART_EMSR_FIFO_COUNT
 
- UART_ENABLE
 
- UART_ENABLE_MS
 
- UART_ENABLE_RX
 
- UART_ENABLE_TX
 
- UART_ERRATA_CLOCK_DISABLE
 
- UART_ERRATA_i202_MDR1_ACCESS
 
- UART_ERRATA_i291_DMA_FORCEIDLE
 
- UART_EXAR654_EFR_CTSDSR
 
- UART_EXAR654_EFR_ECB
 
- UART_EXAR654_EFR_IXOFF
 
- UART_EXAR654_EFR_IXON
 
- UART_EXAR654_EFR_RTSDTR
 
- UART_EXAR654_ENHANCED_REGISTER_SET
 
- UART_EXAR654_IER_CTSDSR
 
- UART_EXAR654_IER_RTSDTR
 
- UART_EXAR654_IER_XOFF
 
- UART_EXAR654_XOFF_DETECT
 
- UART_EXAR654_XON_DETECT
 
- UART_EXAR_8XMODE
 
- UART_EXAR_DVID
 
- UART_EXAR_FCTR
 
- UART_EXAR_INT0
 
- UART_EXAR_MPIO3T_15_8
 
- UART_EXAR_MPIO3T_7_0
 
- UART_EXAR_MPIOINT_15_8
 
- UART_EXAR_MPIOINT_7_0
 
- UART_EXAR_MPIOINV_15_8
 
- UART_EXAR_MPIOINV_7_0
 
- UART_EXAR_MPIOLVL_15_8
 
- UART_EXAR_MPIOLVL_7_0
 
- UART_EXAR_MPIOOD_15_8
 
- UART_EXAR_MPIOOD_7_0
 
- UART_EXAR_MPIOSEL_15_8
 
- UART_EXAR_MPIOSEL_7_0
 
- UART_EXAR_RS485_DLY
 
- UART_EXAR_RXTRG
 
- UART_EXAR_SLEEP
 
- UART_EXAR_TXTRG
 
- UART_EXTINP_CTS_MASK
 
- UART_EXTINP_CTS_NOSENSE_MASK
 
- UART_EXTINP_CTS_NOSENSE_SHIFT
 
- UART_EXTINP_CTS_SHIFT
 
- UART_EXTINP_DCD_MASK
 
- UART_EXTINP_DCD_NOSENSE_MASK
 
- UART_EXTINP_DCD_NOSENSE_SHIFT
 
- UART_EXTINP_DCD_SHIFT
 
- UART_EXTINP_DSR_MASK
 
- UART_EXTINP_DSR_NOSENSE_MASK
 
- UART_EXTINP_DSR_NOSENSE_SHIFT
 
- UART_EXTINP_DSR_SHIFT
 
- UART_EXTINP_INT_MASK
 
- UART_EXTINP_IRMASK
 
- UART_EXTINP_IRSTAT
 
- UART_EXTINP_IR_CTS
 
- UART_EXTINP_IR_DCD
 
- UART_EXTINP_IR_DSR
 
- UART_EXTINP_IR_RI
 
- UART_EXTINP_REG
 
- UART_EXTINP_RI_MASK
 
- UART_EXTINP_RI_NOSENSE_MASK
 
- UART_EXTINP_RI_NOSENSE_SHIFT
 
- UART_EXTINP_RI_SHIFT
 
- UART_EXT_CTRL1
 
- UART_EXT_CTRL2
 
- UART_EXT_RBR
 
- UART_EXT_TSH
 
- UART_FCH
 
- UART_FCL
 
- UART_FCR
 
- UART_FCR6_R_TRIGGER_16
 
- UART_FCR6_R_TRIGGER_24
 
- UART_FCR6_R_TRIGGER_28
 
- UART_FCR6_R_TRIGGER_8
 
- UART_FCR6_T_TRIGGER_16
 
- UART_FCR6_T_TRIGGER_24
 
- UART_FCR6_T_TRIGGER_30
 
- UART_FCR6_T_TRIGGER_8
 
- UART_FCR7_64BYTE
 
- UART_FCR_CLEAR_RCVR
 
- UART_FCR_CLEAR_XMIT
 
- UART_FCR_DMA_SELECT
 
- UART_FCR_ENABLE_FIFO
 
- UART_FCR_PXAR1
 
- UART_FCR_PXAR16
 
- UART_FCR_PXAR32
 
- UART_FCR_PXAR8
 
- UART_FCR_R_TRIG_00
 
- UART_FCR_R_TRIG_01
 
- UART_FCR_R_TRIG_10
 
- UART_FCR_R_TRIG_11
 
- UART_FCR_R_TRIG_BITS
 
- UART_FCR_R_TRIG_MAX_STATE
 
- UART_FCR_R_TRIG_SHIFT
 
- UART_FCR_TRIGGER_1
 
- UART_FCR_TRIGGER_14
 
- UART_FCR_TRIGGER_4
 
- UART_FCR_TRIGGER_8
 
- UART_FCR_TRIGGER_MASK
 
- UART_FCR_T_TRIG_00
 
- UART_FCR_T_TRIG_01
 
- UART_FCR_T_TRIG_10
 
- UART_FCR_T_TRIG_11
 
- UART_FCR_UME
 
- UART_FCTR
 
- UART_FCTR_EXAR_485
 
- UART_FCTR_EXAR_IRDA
 
- UART_FCTR_EXAR_TRGA
 
- UART_FCTR_EXAR_TRGB
 
- UART_FCTR_EXAR_TRGC
 
- UART_FCTR_EXAR_TRGD
 
- UART_FCTR_IRDA
 
- UART_FCTR_RTS_4DELAY
 
- UART_FCTR_RTS_6DELAY
 
- UART_FCTR_RTS_8DELAY
 
- UART_FCTR_RTS_NODELAY
 
- UART_FCTR_RX
 
- UART_FCTR_SCR_SWAP
 
- UART_FCTR_TRGA
 
- UART_FCTR_TRGB
 
- UART_FCTR_TRGC
 
- UART_FCTR_TRGD
 
- UART_FCTR_TX
 
- UART_FCTR_TX_INT
 
- UART_FIFO_ANYERR_MASK
 
- UART_FIFO_BRKDET_MASK
 
- UART_FIFO_BRKDET_SHIFT
 
- UART_FIFO_CTL
 
- UART_FIFO_FRAMEERR_MASK
 
- UART_FIFO_FRAMEERR_SHIFT
 
- UART_FIFO_OFFSET
 
- UART_FIFO_PARERR_MASK
 
- UART_FIFO_PARERR_SHIFT
 
- UART_FIFO_REG
 
- UART_FIFO_VALID_MASK
 
- UART_FIFO_VALID_SHIFT
 
- UART_FLAG_TXFF
 
- UART_FRAME_ERROR
 
- UART_GET_CHAR
 
- UART_GET_CTRL
 
- UART_GET_DATA
 
- UART_GET_FIFO_CNT
 
- UART_GET_SCAL
 
- UART_GET_STATUS
 
- UART_GET_UTCR0
 
- UART_GET_UTCR1
 
- UART_GET_UTCR2
 
- UART_GET_UTCR3
 
- UART_GET_UTSR0
 
- UART_GET_UTSR1
 
- UART_GPIO_CTS
 
- UART_GPIO_DCD
 
- UART_GPIO_DSR
 
- UART_GPIO_DTR
 
- UART_GPIO_MAX
 
- UART_GPIO_RI
 
- UART_GPIO_RNG
 
- UART_GPIO_RTS
 
- UART_HCR
 
- UART_ICR
 
- UART_ID1
 
- UART_ID2
 
- UART_ID3
 
- UART_IER
 
- UART_IERX_SLEEP
 
- UART_IER_DMAE
 
- UART_IER_MSI
 
- UART_IER_NRZE
 
- UART_IER_RDI
 
- UART_IER_RLSI
 
- UART_IER_RTOIE
 
- UART_IER_THRI
 
- UART_IER_UUE
 
- UART_IIR
 
- UART_IIR_BUSY
 
- UART_IIR_CTSRTS
 
- UART_IIR_CTS_RTS_DSR
 
- UART_IIR_ID
 
- UART_IIR_MSI
 
- UART_IIR_NO_INT
 
- UART_IIR_RDI
 
- UART_IIR_RDI_TIMEOUT
 
- UART_IIR_RLSI
 
- UART_IIR_RX_TIMEOUT
 
- UART_IIR_THRI
 
- UART_IIR_TOD
 
- UART_IIR_XOFF
 
- UART_IMR
 
- UART_IMR_CURRENT_CTS
 
- UART_IMR_DELTA_CTS
 
- UART_IMR_RXBREAK_START
 
- UART_IMR_RXLEV
 
- UART_IMR_RXSTALE
 
- UART_IMR_TXLEV
 
- UART_INFO_NUM
 
- UART_INTR
 
- UART_INTR_MASK
 
- UART_INT_EN
 
- UART_INT_ID
 
- UART_INT_MASK_CSR
 
- UART_INT_SOURCE_CSR
 
- UART_IPR
 
- UART_IPR_RXSTALE_LAST
 
- UART_IPR_STALE_LSB
 
- UART_IPR_STALE_TIMEOUT_MSB
 
- UART_IRDA
 
- UART_IRQ_COUNT
 
- UART_IRQ_NUM
 
- UART_IRQ_SUM
 
- UART_IR_EXTIP
 
- UART_IR_MASK
 
- UART_IR_REG
 
- UART_IR_RXBRK
 
- UART_IR_RXFRAMEERR
 
- UART_IR_RXFULL
 
- UART_IR_RXNOTEMPTY
 
- UART_IR_RXOVER
 
- UART_IR_RXPARERR
 
- UART_IR_RXTHRESH
 
- UART_IR_RXTIMEOUT
 
- UART_IR_RXUNDER
 
- UART_IR_STAT
 
- UART_IR_TXDONE
 
- UART_IR_TXEMPTY
 
- UART_IR_TXOVER
 
- UART_IR_TXRDLATCH
 
- UART_IR_TXTRESH
 
- UART_IR_TXUNDER
 
- UART_ISR
 
- UART_ISR_TX_READY
 
- UART_LCR
 
- UART_LCR_CONF_MODE_A
 
- UART_LCR_CONF_MODE_B
 
- UART_LCR_DLAB
 
- UART_LCR_EPAR
 
- UART_LCR_PARITY
 
- UART_LCR_SBC
 
- UART_LCR_SPAR
 
- UART_LCR_STOP
 
- UART_LCR_WLEN5
 
- UART_LCR_WLEN6
 
- UART_LCR_WLEN7
 
- UART_LCR_WLEN8
 
- UART_LINE_CTL
 
- UART_LINE_STS
 
- UART_LSR
 
- UART_LSR_BI
 
- UART_LSR_BRK_ERROR_BITS
 
- UART_LSR_DR
 
- UART_LSR_FE
 
- UART_LSR_FIFOE
 
- UART_LSR_OE
 
- UART_LSR_OFS
 
- UART_LSR_PE
 
- UART_LSR_SPECIAL
 
- UART_LSR_TEMT
 
- UART_LSR_THRE
 
- UART_MANUAL_RFR_EN
 
- UART_MCR
 
- UART_MCR_AFE
 
- UART_MCR_CLKSEL
 
- UART_MCR_DTR
 
- UART_MCR_FCM
 
- UART_MCR_LOOP
 
- UART_MCR_MDCE
 
- UART_MCR_OUT1
 
- UART_MCR_OUT2
 
- UART_MCR_RTS
 
- UART_MCR_TCRTLR
 
- UART_MCR_XONANY
 
- UART_MCTL_DTR_MASK
 
- UART_MCTL_DTR_SHIFT
 
- UART_MCTL_REG
 
- UART_MCTL_RTS_MASK
 
- UART_MCTL_RTS_SHIFT
 
- UART_MCTL_RXFIFOFILL_MASK
 
- UART_MCTL_RXFIFOFILL_SHIFT
 
- UART_MCTL_RXFIFOTHRESH_MASK
 
- UART_MCTL_RXFIFOTHRESH_SHIFT
 
- UART_MCTL_TXFIFOFILL_MASK
 
- UART_MCTL_TXFIFOFILL_SHIFT
 
- UART_MCTL_TXFIFOTHRESH_MASK
 
- UART_MCTL_TXFIFOTHRESH_SHIFT
 
- UART_MISR
 
- UART_MISR_EXPORT
 
- UART_MISR_MODE
 
- UART_MISR_RESET
 
- UART_MISR_VAL
 
- UART_MNDREG
 
- UART_MODEM_CTL
 
- UART_MODEM_STS
 
- UART_MODE_ON
 
- UART_MR1
 
- UART_MR1_AUTO_RFR_LEVEL0
 
- UART_MR1_AUTO_RFR_LEVEL1
 
- UART_MR1_CTS_CTL
 
- UART_MR1_RX_RDY_CTL
 
- UART_MR2
 
- UART_MR2_BITS_PER_CHAR
 
- UART_MR2_BITS_PER_CHAR_5
 
- UART_MR2_BITS_PER_CHAR_6
 
- UART_MR2_BITS_PER_CHAR_7
 
- UART_MR2_BITS_PER_CHAR_8
 
- UART_MR2_ERROR_MODE
 
- UART_MR2_PARITY_MODE
 
- UART_MR2_PARITY_MODE_EVEN
 
- UART_MR2_PARITY_MODE_NONE
 
- UART_MR2_PARITY_MODE_ODD
 
- UART_MR2_PARITY_MODE_SPACE
 
- UART_MR2_STOP_BIT_LEN_ONE
 
- UART_MR2_STOP_BIT_LEN_TWO
 
- UART_MREG
 
- UART_MSR
 
- UART_MSR_ANY_DELTA
 
- UART_MSR_CTS
 
- UART_MSR_DCD
 
- UART_MSR_DCTS
 
- UART_MSR_DDCD
 
- UART_MSR_DDSR
 
- UART_MSR_DSR
 
- UART_MSR_MASK
 
- UART_MSR_RI
 
- UART_MSR_TERI
 
- UART_NATSEMI
 
- UART_NMR
 
- UART_NPCM_TOIE
 
- UART_NPCM_TOR
 
- UART_NR
 
- UART_NREG
 
- UART_NR_MAX
 
- UART_OFFS
 
- UART_OFFSET
 
- UART_OMAP_EBLR
 
- UART_OMAP_MDR1
 
- UART_OMAP_MDR1_13X_MODE
 
- UART_OMAP_MDR1_16X_ABAUD_MODE
 
- UART_OMAP_MDR1_16X_MODE
 
- UART_OMAP_MDR1_CIR_MODE
 
- UART_OMAP_MDR1_DISABLE
 
- UART_OMAP_MDR1_FIR_MODE
 
- UART_OMAP_MDR1_MIR_MODE
 
- UART_OMAP_MDR1_SIR_MODE
 
- UART_OMAP_MDR2
 
- UART_OMAP_MVER
 
- UART_OMAP_OSC_12M_SEL
 
- UART_OMAP_SCR
 
- UART_OMAP_SSR
 
- UART_OMAP_SYSC
 
- UART_OMAP_SYSS
 
- UART_OMAP_TX_LVL
 
- UART_OMAP_WER
 
- UART_OSAMP
 
- UART_OVERRUN_ERROR
 
- UART_OVERSAMPLING
 
- UART_PADDR
 
- UART_PARAM
 
- UART_PARITY_ERROR
 
- UART_PHYS
 
- UART_PHYS_BASE
 
- UART_PM_STATE_OFF
 
- UART_PM_STATE_ON
 
- UART_PM_STATE_UNDEFINED
 
- UART_PORT_COMBINED_IRQ
 
- UART_PORT_SIZE
 
- UART_PRIORITY
 
- UART_PROBE_RSA
 
- UART_PUT_CHAR
 
- UART_PUT_CTRL
 
- UART_PUT_SCAL
 
- UART_PUT_STATUS
 
- UART_PUT_UTCR0
 
- UART_PUT_UTCR1
 
- UART_PUT_UTCR2
 
- UART_PUT_UTCR3
 
- UART_PUT_UTSR0
 
- UART_PUT_UTSR1
 
- UART_PU_PD_CTRL_REG
 
- UART_RBR
 
- UART_RBUF_LEN
 
- UART_REG_CLR
 
- UART_REG_GET
 
- UART_REG_LCR
 
- UART_REG_LSR
 
- UART_REG_LSR_RT2880
 
- UART_REG_OR
 
- UART_REG_SET
 
- UART_REG_TX
 
- UART_REV
 
- UART_RF
 
- UART_RFL
 
- UART_RFR_NOT_READY
 
- UART_RFR_READY
 
- UART_RFWR
 
- UART_RI
 
- UART_RING
 
- UART_RSA_BASE
 
- UART_RSA_FRR
 
- UART_RSA_IER
 
- UART_RSA_IER_Rx_FIFO_H
 
- UART_RSA_IER_Rx_TOUT
 
- UART_RSA_IER_TIMER
 
- UART_RSA_IER_Tx_FIFO_E
 
- UART_RSA_IER_Tx_FIFO_H
 
- UART_RSA_MSR
 
- UART_RSA_MSR_FIFO
 
- UART_RSA_MSR_FLOW
 
- UART_RSA_MSR_ITYP
 
- UART_RSA_MSR_SWAP
 
- UART_RSA_SRR
 
- UART_RSA_SRR_Rx_FIFO_NEMP
 
- UART_RSA_SRR_Rx_FIFO_NFUL
 
- UART_RSA_SRR_Rx_FIFO_NHFL
 
- UART_RSA_SRR_Rx_TOUT
 
- UART_RSA_SRR_TIMER
 
- UART_RSA_SRR_Tx_FIFO_NEMP
 
- UART_RSA_SRR_Tx_FIFO_NFUL
 
- UART_RSA_SRR_Tx_FIFO_NHFL
 
- UART_RSA_TCR
 
- UART_RSA_TCR_SWITCH
 
- UART_RSA_TIVSR
 
- UART_RTL
 
- UART_RX
 
- UART_RX_DATA
 
- UART_RX_INS_STATUS_BIT
 
- UART_RX_INT_MASK
 
- UART_RX_INT_STAT
 
- UART_RX_IRQ
 
- UART_RX_IRQ_DISABLE
 
- UART_RX_IRQ_ENABLE
 
- UART_RX_PAR_EN
 
- UART_RX_WM
 
- UART_SCC1
 
- UART_SCC2
 
- UART_SCC3
 
- UART_SCC4
 
- UART_SCCM_AB
 
- UART_SCCM_BRKE
 
- UART_SCCM_BRKS
 
- UART_SCCM_BSY
 
- UART_SCCM_CCR
 
- UART_SCCM_GLR
 
- UART_SCCM_GLT
 
- UART_SCCM_GRA
 
- UART_SCCM_IDL
 
- UART_SCCM_RX
 
- UART_SCCM_TX
 
- UART_SCR
 
- UART_SET_BAUDH
 
- UART_SET_BAUDL
 
- UART_SET_DATA
 
- UART_SHIFT
 
- UART_SMC1
 
- UART_SMC2
 
- UART_SPLIT
 
- UART_SPLIT_SHIFT
 
- UART_SR
 
- UART_SR_HUNT_CHAR
 
- UART_SR_OFFSET
 
- UART_SR_OVERRUN
 
- UART_SR_PAR_FRAME_ERR
 
- UART_SR_RX_BREAK
 
- UART_SR_RX_FULL
 
- UART_SR_RX_READY
 
- UART_SR_TXEMPTY
 
- UART_SR_TXFULL
 
- UART_SR_TX_EMPTY
 
- UART_SR_TX_READY
 
- UART_STARTECH
 
- UART_START_BREAK
 
- UART_START_READ
 
- UART_START_TX
 
- UART_STAT
 
- UART_STATE
 
- UART_STATE_INDEX
 
- UART_STATE_MSR_MASK
 
- UART_STATE_TRANSIENT_MASK
 
- UART_STATUS_BR
 
- UART_STATUS_DR
 
- UART_STATUS_ERR
 
- UART_STATUS_FE
 
- UART_STATUS_OE
 
- UART_STATUS_PE
 
- UART_STATUS_THE
 
- UART_STATUS_TSE
 
- UART_STD_CTRL1
 
- UART_STD_CTRL2
 
- UART_STD_RBR
 
- UART_STD_TSH
 
- UART_STOP_BREAK
 
- UART_TCR
 
- UART_TEST_CTRL
 
- UART_TF
 
- UART_TFL
 
- UART_TFWR
 
- UART_THR
 
- UART_TI752_TCR
 
- UART_TI752_TLR
 
- UART_TI752_TLR_RX
 
- UART_TI752_TLR_TX
 
- UART_TO_MSM
 
- UART_TRG
 
- UART_TRG_1
 
- UART_TRG_120
 
- UART_TRG_128
 
- UART_TRG_16
 
- UART_TRG_32
 
- UART_TRG_4
 
- UART_TRG_64
 
- UART_TRG_8
 
- UART_TRG_96
 
- UART_TSH
 
- UART_TTL
 
- UART_TX
 
- UART_TX_DATA
 
- UART_TX_FULL
 
- UART_TX_INT_MASK
 
- UART_TX_INT_STAT
 
- UART_TX_IRQ
 
- UART_TX_IRQ_DISABLE
 
- UART_TX_IRQ_ENABLE
 
- UART_TX_OFS
 
- UART_TX_PAR_EN
 
- UART_TX_READY
 
- UART_UART
 
- UART_USE_FIFO
 
- UART_VADDR
 
- UART_VIRTUAL_BASE
 
- UART_VIRT_BASE
 
- UART_XMIT_SIZE
 
- UART_XOFF1
 
- UART_XOFF2
 
- UART_XON1
 
- UART_XON2
 
- UART_XR_EFR
 
- UART_ZILOG
 
- UARTn_BAUDDIV
 
- UARTn_BAUDDIV_MASK
 
- UARTn_CLKDIV
 
- UARTn_CMD
 
- UARTn_CMD_RXDIS
 
- UARTn_CMD_RXEN
 
- UARTn_CMD_TXDIS
 
- UARTn_CMD_TXEN
 
- UARTn_CTRL
 
- UARTn_CTRL_RX_ENABLE
 
- UARTn_CTRL_RX_GRP
 
- UARTn_CTRL_RX_INT_ENABLE
 
- UARTn_CTRL_RX_OVERRUN_INT_ENABLE
 
- UARTn_CTRL_SYNC
 
- UARTn_CTRL_TXBIL
 
- UARTn_CTRL_TX_ENABLE
 
- UARTn_CTRL_TX_GRP
 
- UARTn_CTRL_TX_INT_ENABLE
 
- UARTn_CTRL_TX_OVERRUN_INT_ENABLE
 
- UARTn_DATA
 
- UARTn_FRAME
 
- UARTn_FRAME_DATABITS
 
- UARTn_FRAME_DATABITS__MASK
 
- UARTn_FRAME_PARITY_EVEN
 
- UARTn_FRAME_PARITY_NONE
 
- UARTn_FRAME_PARITY_ODD
 
- UARTn_FRAME_PARITY__MASK
 
- UARTn_FRAME_STOPBITS_HALF
 
- UARTn_FRAME_STOPBITS_ONE
 
- UARTn_FRAME_STOPBITS_TWO
 
- UARTn_IEN
 
- UARTn_IF
 
- UARTn_IFC
 
- UARTn_IFS
 
- UARTn_IF_RXDATAV
 
- UARTn_IF_RXOF
 
- UARTn_IF_TXBL
 
- UARTn_IF_TXC
 
- UARTn_INT
 
- UARTn_INT_RX
 
- UARTn_INT_RX_OVERRUN
 
- UARTn_INT_TX
 
- UARTn_INT_TX_OVERRUN
 
- UARTn_ROUTE
 
- UARTn_ROUTE_LOCATION
 
- UARTn_ROUTE_LOCATION__MASK
 
- UARTn_ROUTE_RXPEN
 
- UARTn_ROUTE_TXPEN
 
- UARTn_RXDATAX
 
- UARTn_RXDATAX_FERR
 
- UARTn_RXDATAX_PERR
 
- UARTn_RXDATAX_RXDATA__MASK
 
- UARTn_STATE
 
- UARTn_STATE_RX_FULL
 
- UARTn_STATE_RX_OVERRUN
 
- UARTn_STATE_TX_FULL
 
- UARTn_STATE_TX_OVERRUN
 
- UARTn_STATUS
 
- UARTn_STATUS_RXDATAV
 
- UARTn_STATUS_TXBL
 
- UARTn_STATUS_TXC
 
- UARTn_STATUS_TXENS
 
- UARTn_TXDATA
 
- UASM_EXPORT_SYMBOL
 
- UASM_LABEL_INVALID
 
- UASM_L_LA
 
- UASM_i_ADDIU
 
- UASM_i_ADDU
 
- UASM_i_CPUID_MFC0
 
- UASM_i_LA
 
- UASM_i_LA_mostly
 
- UASM_i_LL
 
- UASM_i_LW
 
- UASM_i_LWX
 
- UASM_i_MFC0
 
- UASM_i_MTC0
 
- UASM_i_ROTR
 
- UASM_i_SC
 
- UASM_i_SLL
 
- UASM_i_SRA
 
- UASM_i_SRL
 
- UASM_i_SRL_SAFE
 
- UASM_i_SUBU
 
- UASM_i_SW
 
- UASP_QUEUE_COMMAND
 
- UASP_RECEIVE_DATA
 
- UASP_SEND_DATA
 
- UASP_SEND_STATUS
 
- UASP_SS_EP_COMP_LOG_STREAMS
 
- UASP_SS_EP_COMP_NUM_STREAMS
 
- UAS_ACA
 
- UAS_HEAD_TAG
 
- UAS_ORDERED_TAG
 
- UAS_PRODUCT_ID
 
- UAS_SIMPLE_TAG
 
- UAS_VENDOR_ID
 
- UATH_CFLAGS_DEBUG
 
- UATH_CFLAGS_FINAL
 
- UATH_CFLAGS_RXMSG
 
- UATH_CHAN_2GHZ
 
- UATH_CHAN_5GHZ
 
- UATH_CHAN_CCK
 
- UATH_CHAN_OFDM
 
- UATH_CHAN_TURBO
 
- UATH_FILTER_OP_CLEAR
 
- UATH_FILTER_OP_INIT
 
- UATH_FILTER_OP_RESTORE
 
- UATH_FILTER_OP_SET
 
- UATH_FILTER_OP_TEMP
 
- UATH_FILTER_RX_BCAST
 
- UATH_FILTER_RX_BEACON
 
- UATH_FILTER_RX_CONTROL
 
- UATH_FILTER_RX_MCAST
 
- UATH_FILTER_RX_PHY_ERR
 
- UATH_FILTER_RX_PHY_RADAR
 
- UATH_FILTER_RX_PROBE_REQ
 
- UATH_FILTER_RX_PROM
 
- UATH_FILTER_RX_UCAST
 
- UATH_FILTER_RX_XR_POOL
 
- UATH_ID_INVALID
 
- UATH_LED_ACTIVITY
 
- UATH_LED_LINK
 
- UATH_LED_OFF
 
- UATH_LED_ON
 
- UATH_STATUS_CRC_ERR
 
- UATH_STATUS_DECOMP_ERR
 
- UATH_STATUS_DECRYPT_CRC_ERR
 
- UATH_STATUS_DECRYPT_MIC_ERR
 
- UATH_STATUS_ERR
 
- UATH_STATUS_KEY_ERR
 
- UATH_STATUS_OK
 
- UATH_STATUS_PHY_ERR
 
- UATH_STATUS_STOP_IN_PROGRESS
 
- UATH_TXQID_FF
 
- UATH_TXQID_MASK
 
- UATH_TXQID_MINRATE
 
- UATH_TX_NOTIFY
 
- UATTR_HSPEC
 
- UATTR_IO
 
- UATTR_MSPEC
 
- UATTR_UNCAC
 
- UAWM_HW_CGC_EN
 
- UA_ALLOC_AND_COPY
 
- UA_BASE_DEVICE
 
- UA_BASE_PAV_ALIAS
 
- UA_CHANGED_ASC
 
- UA_CONFIG
 
- UA_CONFIG_CHAR_LEN
 
- UA_CONFIG_FIFO
 
- UA_CONFIG_FIFO_RX_FIFO_MODE
 
- UA_CONFIG_FIFO_RX_THRESH
 
- UA_CONFIG_FIFO_TX_FIFO_MODE
 
- UA_CONFIG_ODD_PARITY
 
- UA_CONFIG_PARITY
 
- UA_CONFIG_STOP_BITS
 
- UA_CONTROL
 
- UA_CONTROL_RX_ENABLE
 
- UA_CONTROL_SOFT_RESET
 
- UA_CONTROL_TX_ENABLE
 
- UA_ECS
 
- UA_EMI_REC
 
- UA_ENABLE
 
- UA_ENABLE_ENABLE
 
- UA_HBAUD_HI
 
- UA_HBAUD_LO
 
- UA_HYPER_PAV_ALIAS
 
- UA_INTFLAG_CLEAR
 
- UA_INTFLAG_SET
 
- UA_INT_ENABLE
 
- UA_INT_RX
 
- UA_INT_STATUS
 
- UA_INT_TX
 
- UA_MANDATORY
 
- UA_NOT_CONFIGURED
 
- UA_OPTIONAL
 
- UA_RESET_ASC
 
- UA_STATUS
 
- UA_STATUS_FIFO
 
- UA_STATUS_FIFO_RX_EMPTY
 
- UA_STATUS_FIFO_RX_INT_ALMOST
 
- UA_STATUS_FIFO_TX_FULL
 
- UA_STATUS_FIFO_TX_INT_ALMOST
 
- UA_STATUS_FRAME_ERR
 
- UA_STATUS_OVERRUN_ERR
 
- UA_STATUS_PARITY_ERR
 
- UA_STATUS_TX_READY
 
- UB
 
- UBAUD
 
- UBAUD_ADDR
 
- UBAUD_BAUD_SRC
 
- UBAUD_DIVIDE_MASK
 
- UBAUD_DIVIDE_SHIFT
 
- UBAUD_GPIO
 
- UBAUD_GPIODELTA
 
- UBAUD_GPIODIR
 
- UBAUD_GPIOSRC
 
- UBAUD_PRESCALER_MASK
 
- UBAUD_PRESCALER_SHIFT
 
- UBAUD_UCLKDIR
 
- UBCR12
 
- UBCR14
 
- UBCR2
 
- UBCR4
 
- UBCR7
 
- UBCR9
 
- UBCTRG_MARK
 
- UBC_CAMR
 
- UBC_CAR
 
- UBC_CBCR
 
- UBC_CBR
 
- UBC_CBR_CE
 
- UBC_CCMFR
 
- UBC_CRR
 
- UBC_CRR_BIE
 
- UBC_CRR_PCB
 
- UBD_IRQ
 
- UBD_MAJOR
 
- UBD_MAX_REQUEST
 
- UBD_REQ_BUFFER_SIZE
 
- UBD_SHIFT
 
- UBI32_CORE1_AHB_RESET
 
- UBI32_CORE1_AXI_RESET
 
- UBI32_CORE1_CLAMP_RESET
 
- UBI32_CORE1_CLK
 
- UBI32_CORE1_CLKRST_CLAMP_RESET
 
- UBI32_CORE1_CLK_SRC
 
- UBI32_CORE2_AHB_RESET
 
- UBI32_CORE2_AXI_RESET
 
- UBI32_CORE2_CLAMP_RESET
 
- UBI32_CORE2_CLK
 
- UBI32_CORE2_CLKRST_CLAMP_RESET
 
- UBI32_CORE2_CLK_SRC
 
- UBI32_PLL
 
- UBI32_PLL_MAIN
 
- UBIBLOCK_MAX_DEVICES
 
- UBIBLOCK_PARAM_COUNT
 
- UBIBLOCK_PARAM_LEN
 
- UBIFS_APPEND_FL
 
- UBIFS_AUTH_NODE
 
- UBIFS_AUTH_NODE_SZ
 
- UBIFS_BASE_HEAD
 
- UBIFS_BLOCKS_PER_PAGE
 
- UBIFS_BLOCKS_PER_PAGE_SHIFT
 
- UBIFS_BLOCK_SHIFT
 
- UBIFS_BLOCK_SIZE
 
- UBIFS_BRANCH_SZ
 
- UBIFS_CH_SZ
 
- UBIFS_CIPHER_BLOCK_SIZE
 
- UBIFS_COMPR_FL
 
- UBIFS_COMPR_LZO
 
- UBIFS_COMPR_NONE
 
- UBIFS_COMPR_TYPES_CNT
 
- UBIFS_COMPR_ZLIB
 
- UBIFS_COMPR_ZSTD
 
- UBIFS_CRC32_INIT
 
- UBIFS_CRYPT_FL
 
- UBIFS_CS_NODE
 
- UBIFS_CS_NODE_SZ
 
- UBIFS_DATA_HEAD
 
- UBIFS_DATA_KEY
 
- UBIFS_DATA_NODE
 
- UBIFS_DATA_NODE_SZ
 
- UBIFS_DENT_KEY
 
- UBIFS_DENT_NODE
 
- UBIFS_DENT_NODE_SZ
 
- UBIFS_DFS_DIR_LEN
 
- UBIFS_DFS_DIR_NAME
 
- UBIFS_DIRSYNC_FL
 
- UBIFS_FIRST_INO
 
- UBIFS_FLG_AUTHENTICATION
 
- UBIFS_FLG_BIGLPT
 
- UBIFS_FLG_DOUBLE_HASH
 
- UBIFS_FLG_ENCRYPTION
 
- UBIFS_FLG_MASK
 
- UBIFS_FLG_SPACE_FIXUP
 
- UBIFS_FL_MASK
 
- UBIFS_FORMAT_VERSION
 
- UBIFS_GC_HEAD
 
- UBIFS_HASH_ARR_SZ
 
- UBIFS_HMAC_ARR_SZ
 
- UBIFS_IDX_NODE
 
- UBIFS_IDX_NODE_SZ
 
- UBIFS_IMMUTABLE_FL
 
- UBIFS_INO_KEY
 
- UBIFS_INO_NODE
 
- UBIFS_INO_NODE_SZ
 
- UBIFS_INVALID_KEY
 
- UBIFS_IN_NODE_GROUP
 
- UBIFS_ITYPES_CNT
 
- UBIFS_ITYPE_BLK
 
- UBIFS_ITYPE_CHR
 
- UBIFS_ITYPE_DIR
 
- UBIFS_ITYPE_FIFO
 
- UBIFS_ITYPE_LNK
 
- UBIFS_ITYPE_REG
 
- UBIFS_ITYPE_SOCK
 
- UBIFS_KEY_HASH_R5
 
- UBIFS_KEY_HASH_TEST
 
- UBIFS_KEY_OFFSET
 
- UBIFS_KEY_TYPES_CNT
 
- UBIFS_KMALLOC_OK
 
- UBIFS_LAST_OF_NODE_GROUP
 
- UBIFS_LOG_LNUM
 
- UBIFS_LPT_CRC_BITS
 
- UBIFS_LPT_CRC_BYTES
 
- UBIFS_LPT_FANOUT
 
- UBIFS_LPT_FANOUT_SHIFT
 
- UBIFS_LPT_LSAVE
 
- UBIFS_LPT_LTAB
 
- UBIFS_LPT_NNODE
 
- UBIFS_LPT_NODE_CNT
 
- UBIFS_LPT_NOT_A_NODE
 
- UBIFS_LPT_PNODE
 
- UBIFS_LPT_TYPE_BITS
 
- UBIFS_MAX_BULK_READ
 
- UBIFS_MAX_DATA_NODE_SZ
 
- UBIFS_MAX_DENT_NODE_SZ
 
- UBIFS_MAX_HASH_LEN
 
- UBIFS_MAX_HMAC_LEN
 
- UBIFS_MAX_INO_DATA
 
- UBIFS_MAX_INO_NODE_SZ
 
- UBIFS_MAX_JHEADS
 
- UBIFS_MAX_KEY_LEN
 
- UBIFS_MAX_LEVELS
 
- UBIFS_MAX_NLEN
 
- UBIFS_MAX_NODE_SZ
 
- UBIFS_MAX_XENT_NODE_SZ
 
- UBIFS_MIN_BUD_LEBS
 
- UBIFS_MIN_COMPRESS_DIFF
 
- UBIFS_MIN_COMPR_LEN
 
- UBIFS_MIN_FANOUT
 
- UBIFS_MIN_JNL_LEBS
 
- UBIFS_MIN_LEB_CNT
 
- UBIFS_MIN_LEB_SZ
 
- UBIFS_MIN_LOG_LEBS
 
- UBIFS_MIN_LPT_LEBS
 
- UBIFS_MIN_MAIN_LEBS
 
- UBIFS_MIN_ORPH_LEBS
 
- UBIFS_MST_DIRTY
 
- UBIFS_MST_LEBS
 
- UBIFS_MST_LNUM
 
- UBIFS_MST_NODE
 
- UBIFS_MST_NODE_SZ
 
- UBIFS_MST_NO_ORPHS
 
- UBIFS_MST_RCVRY
 
- UBIFS_NODE_MAGIC
 
- UBIFS_NODE_TYPES_CNT
 
- UBIFS_NO_NODE_GROUP
 
- UBIFS_ORPH_NODE
 
- UBIFS_ORPH_NODE_SZ
 
- UBIFS_PADDING_BYTE
 
- UBIFS_PAD_NODE
 
- UBIFS_PAD_NODE_SZ
 
- UBIFS_REF_NODE
 
- UBIFS_REF_NODE_SZ
 
- UBIFS_ROOT_INO
 
- UBIFS_RO_COMPAT_VERSION
 
- UBIFS_SB_LEBS
 
- UBIFS_SB_LNUM
 
- UBIFS_SB_NODE
 
- UBIFS_SB_NODE_SZ
 
- UBIFS_SIGNATURE_TYPE_PKCS7
 
- UBIFS_SIG_NODE
 
- UBIFS_SIG_NODE_SZ
 
- UBIFS_SIMPLE_KEY_FMT
 
- UBIFS_SK_LEN
 
- UBIFS_SUPER_MAGIC
 
- UBIFS_SUPPORTED_IOCTL_FLAGS
 
- UBIFS_SYNC_FL
 
- UBIFS_S_KEY_BLOCK_BITS
 
- UBIFS_S_KEY_BLOCK_MASK
 
- UBIFS_S_KEY_HASH_BITS
 
- UBIFS_S_KEY_HASH_MASK
 
- UBIFS_TRUN_KEY
 
- UBIFS_TRUN_NODE
 
- UBIFS_TRUN_NODE_SZ
 
- UBIFS_VERSION
 
- UBIFS_XATTR_FL
 
- UBIFS_XATTR_NAME_ENCRYPTION_CONTEXT
 
- UBIFS_XENT_KEY
 
- UBIFS_XENT_NODE
 
- UBIFS_XENT_NODE_SZ
 
- UBIR
 
- UBITSHIFT
 
- UBI_ALL
 
- UBI_BAD_FASTMAP
 
- UBI_BGT_NAME_PATTERN
 
- UBI_COMPAT_DELETE
 
- UBI_COMPAT_PRESERVE
 
- UBI_COMPAT_REJECT
 
- UBI_COMPAT_RO
 
- UBI_CRC32_INIT
 
- UBI_CTRL_IOC_MAGIC
 
- UBI_DEV_NUM_AUTO
 
- UBI_DFS_DIR_LEN
 
- UBI_DFS_DIR_NAME
 
- UBI_DYNAMIC_VOLUME
 
- UBI_EC_HDR_MAGIC
 
- UBI_EC_HDR_SIZE
 
- UBI_EC_HDR_SIZE_CRC
 
- UBI_EC_MAGIC
 
- UBI_EXCLUSIVE
 
- UBI_FM_DATA_VOLUME_ID
 
- UBI_FM_EBA_MAGIC
 
- UBI_FM_FMT_VERSION
 
- UBI_FM_HDR_MAGIC
 
- UBI_FM_MAX_BLOCKS
 
- UBI_FM_MAX_POOL_SIZE
 
- UBI_FM_MAX_START
 
- UBI_FM_MIN_POOL_SIZE
 
- UBI_FM_POOL_MAGIC
 
- UBI_FM_SB_MAGIC
 
- UBI_FM_SB_VOLUME_ID
 
- UBI_FM_VHDR_MAGIC
 
- UBI_INTERNAL_VOL_START
 
- UBI_INT_VOL_COUNT
 
- UBI_IOCATT
 
- UBI_IOCDET
 
- UBI_IOCEBCH
 
- UBI_IOCEBER
 
- UBI_IOCEBISMAP
 
- UBI_IOCEBMAP
 
- UBI_IOCEBUNMAP
 
- UBI_IOCMKVOL
 
- UBI_IOCRMVOL
 
- UBI_IOCRNVOL
 
- UBI_IOCRPEB
 
- UBI_IOCRSVOL
 
- UBI_IOCSETVOLPROP
 
- UBI_IOCSPEB
 
- UBI_IOCVOLCRBLK
 
- UBI_IOCVOLRMBLK
 
- UBI_IOCVOLUP
 
- UBI_IOC_MAGIC
 
- UBI_IO_BAD_HDR
 
- UBI_IO_BAD_HDR_EBADMSG
 
- UBI_IO_BITFLIPS
 
- UBI_IO_FF
 
- UBI_IO_FF_BITFLIPS
 
- UBI_IO_RETRIES
 
- UBI_LAYOUT_VOLUME_ALIGN
 
- UBI_LAYOUT_VOLUME_COMPAT
 
- UBI_LAYOUT_VOLUME_EBS
 
- UBI_LAYOUT_VOLUME_ID
 
- UBI_LAYOUT_VOLUME_NAME
 
- UBI_LAYOUT_VOLUME_TYPE
 
- UBI_LEB_UNMAPPED
 
- UBI_MAX_DEVICES
 
- UBI_MAX_ERASECOUNTER
 
- UBI_MAX_RNVOL
 
- UBI_MAX_SG_COUNT
 
- UBI_MAX_VOLUMES
 
- UBI_MAX_VOLUME_NAME
 
- UBI_METAONLY
 
- UBI_MPT_CLK_SRC
 
- UBI_NAME_STR
 
- UBI_NO_FASTMAP
 
- UBI_PROT_QUEUE_LEN
 
- UBI_READONLY
 
- UBI_READWRITE
 
- UBI_STATIC_VOLUME
 
- UBI_UNKNOWN
 
- UBI_VERSION
 
- UBI_VID_DYNAMIC
 
- UBI_VID_HDR_MAGIC
 
- UBI_VID_HDR_SIZE
 
- UBI_VID_HDR_SIZE_CRC
 
- UBI_VID_STATIC
 
- UBI_VOLUME_ADDED
 
- UBI_VOLUME_REMOVED
 
- UBI_VOLUME_RENAMED
 
- UBI_VOLUME_RESIZED
 
- UBI_VOLUME_UPDATED
 
- UBI_VOL_IOC_MAGIC
 
- UBI_VOL_NAME_MAX
 
- UBI_VOL_NUM_AUTO
 
- UBI_VOL_PROP_DIRECT_WRITE
 
- UBI_VOL_SKIP_CRC_CHECK_FLG
 
- UBI_VOL_VALID_FLGS
 
- UBI_VTBL_AUTORESIZE_FLG
 
- UBI_VTBL_RECORD_SIZE
 
- UBI_VTBL_RECORD_SIZE_CRC
 
- UBI_VTBL_SKIP_CRC_CHECK_FLG
 
- UBI_WL_H
 
- UBI_WL_THRESHOLD
 
- UBLOX_C099F9P_ODIN_PID
 
- UBLOX_C099F9P_ZED_PID
 
- UBLOX_PRODUCT_R410M
 
- UBLOX_VENDOR_ID
 
- UBLOX_VID
 
- UBMR
 
- UBOARDREG
 
- UBOOT_FW_OFFSET
 
- UBOOT_MAGIC_VALUE
 
- UBOOT_TAG_CMDLINE
 
- UBOOT_TAG_DTB
 
- UBOOT_TAG_NONE
 
- UBR
 
- UBRC
 
- UBRLCR_BAUD_MASK
 
- UBRLCR_BREAK
 
- UBRLCR_EVENPRT
 
- UBRLCR_FIFOEN
 
- UBRLCR_OFFSET
 
- UBRLCR_PRTEN
 
- UBRLCR_WRDLEN5
 
- UBRLCR_WRDLEN6
 
- UBRLCR_WRDLEN7
 
- UBRLCR_WRDLEN8
 
- UBRLCR_WRDLEN_MASK
 
- UBRLCR_XSTOP
 
- UBRNEXTLINK
 
- UBRWQ_BASE
 
- UBRWQ_RDPTR
 
- UBRWQ_WRPTR
 
- UBR_BUFFER
 
- UBR_EN
 
- UBR_SBPTR_BASE
 
- UBR_SBVC
 
- UBR_SCHED_TABLE
 
- UBR_WAIT_Q
 
- UBUFF_BA
 
- UBUS_ERR_IRQ
 
- UBWC_STATIC
 
- UC
 
- UCALL_ABORT
 
- UCALL_DONE
 
- UCALL_MAX_ARGS
 
- UCALL_NONE
 
- UCALL_PIO_PORT
 
- UCALL_SYNC
 
- UCAN_COMMAND_FILTER
 
- UCAN_COMMAND_GET
 
- UCAN_COMMAND_GET_INFO
 
- UCAN_COMMAND_GET_PROTOCOL_VERSION
 
- UCAN_COMMAND_RESET
 
- UCAN_COMMAND_RESTART
 
- UCAN_COMMAND_SET_BITTIMING
 
- UCAN_COMMAND_SLEEP
 
- UCAN_COMMAND_START
 
- UCAN_COMMAND_STOP
 
- UCAN_COMMAND_WAKEUP
 
- UCAN_DEVICE_GET_FW_STRING
 
- UCAN_DRIVER_NAME
 
- UCAN_FILTER_CLEAR
 
- UCAN_FILTER_DISABLE
 
- UCAN_FILTER_ENABLE
 
- UCAN_IN_HDR_SIZE
 
- UCAN_IN_LEN
 
- UCAN_IN_RX
 
- UCAN_IN_TX_COMPLETE
 
- UCAN_MAX_RX_URBS
 
- UCAN_MODE_3_SAMPLES
 
- UCAN_MODE_BERR_REPORT
 
- UCAN_MODE_LOOPBACK
 
- UCAN_MODE_ONE_SHOT
 
- UCAN_MODE_SILENT
 
- UCAN_OUT_HDR_SIZE
 
- UCAN_OUT_TX
 
- UCAN_PROTOCOL_VERSION_MAX
 
- UCAN_PROTOCOL_VERSION_MIN
 
- UCAN_TX_COMPLETE_SUCCESS
 
- UCAN_USB_CTL_PIPE_TIMEOUT
 
- UCAST
 
- UCAST_DATA_MATCHED
 
- UCAST_FLTR
 
- UCB1200_H
 
- UCB1400_TS_POLL_PERIOD
 
- UCB1X00_ATTR
 
- UCB_AC_A
 
- UCB_AC_B
 
- UCB_AC_B_IN_ENA
 
- UCB_AC_B_LOOP
 
- UCB_AC_B_MUTE
 
- UCB_AC_B_OUT_ENA
 
- UCB_ADC_CR
 
- UCB_ADC_DAT
 
- UCB_ADC_DATA
 
- UCB_ADC_DAT_MASK
 
- UCB_ADC_DAT_VAL
 
- UCB_ADC_DAT_VALID
 
- UCB_ADC_ENA
 
- UCB_ADC_EXT_REF
 
- UCB_ADC_INP_AD0
 
- UCB_ADC_INP_AD1
 
- UCB_ADC_INP_AD2
 
- UCB_ADC_INP_AD3
 
- UCB_ADC_INP_TSMX
 
- UCB_ADC_INP_TSMY
 
- UCB_ADC_INP_TSPX
 
- UCB_ADC_INP_TSPY
 
- UCB_ADC_START
 
- UCB_ADC_SYNC_ENA
 
- UCB_ADC_VREFBYP_CON
 
- UCB_FCSR
 
- UCB_FCSR_AVE
 
- UCB_ID
 
- UCB_ID_1200
 
- UCB_ID_1300
 
- UCB_ID_1400
 
- UCB_ID_TC35143
 
- UCB_IE_ACLIP
 
- UCB_IE_ADC
 
- UCB_IE_CLEAR
 
- UCB_IE_FAL
 
- UCB_IE_RIS
 
- UCB_IE_STATUS
 
- UCB_IE_TCLIP
 
- UCB_IE_TSMX
 
- UCB_IE_TSPX
 
- UCB_IO_0
 
- UCB_IO_1
 
- UCB_IO_2
 
- UCB_IO_3
 
- UCB_IO_4
 
- UCB_IO_5
 
- UCB_IO_6
 
- UCB_IO_7
 
- UCB_IO_8
 
- UCB_IO_9
 
- UCB_IO_DATA
 
- UCB_IO_DIR
 
- UCB_IRQ_TSPX
 
- UCB_MODE
 
- UCB_MODE_AUD_OFF_CAN
 
- UCB_MODE_DYN_VFLAG_ENA
 
- UCB_NOSYNC
 
- UCB_RST_PROBE
 
- UCB_RST_PROBE_FAIL
 
- UCB_RST_REMOVE
 
- UCB_RST_RESUME
 
- UCB_RST_SUSPEND
 
- UCB_SYNC
 
- UCB_TC_A
 
- UCB_TC_A_AMPL
 
- UCB_TC_A_LOOP
 
- UCB_TC_B
 
- UCB_TC_B_ATT
 
- UCB_TC_B_CLIP
 
- UCB_TC_B_IN_ENA
 
- UCB_TC_B_MUTE
 
- UCB_TC_B_OUT_ENA
 
- UCB_TC_B_SIDE_ENA
 
- UCB_TC_B_VOICE_ENA
 
- UCB_TS_CR
 
- UCB_TS_CR_BIAS_ENA
 
- UCB_TS_CR_MODE_INT
 
- UCB_TS_CR_MODE_POS
 
- UCB_TS_CR_MODE_PRES
 
- UCB_TS_CR_TSMX_GND
 
- UCB_TS_CR_TSMX_LOW
 
- UCB_TS_CR_TSMX_POW
 
- UCB_TS_CR_TSMY_GND
 
- UCB_TS_CR_TSMY_POW
 
- UCB_TS_CR_TSPX_GND
 
- UCB_TS_CR_TSPX_LOW
 
- UCB_TS_CR_TSPX_POW
 
- UCB_TS_CR_TSPY_GND
 
- UCB_TS_CR_TSPY_POW
 
- UCCE_HDLC_RX_EVENTS
 
- UCCE_HDLC_TX_EVENTS
 
- UCCE_OTHER
 
- UCCE_RXB
 
- UCCE_RXF
 
- UCCE_RX_EVENTS
 
- UCCE_TXB
 
- UCCE_TX_EVENTS
 
- UCCS_BPR
 
- UCCS_MPD
 
- UCCS_PAU
 
- UCC_BISYNC_UCCE_BSY
 
- UCC_BISYNC_UCCE_GRA
 
- UCC_BISYNC_UCCE_RCH
 
- UCC_BISYNC_UCCE_RXB
 
- UCC_BISYNC_UCCE_TXB
 
- UCC_BISYNC_UCCE_TXE
 
- UCC_BMR_BDB
 
- UCC_BMR_BO_BE
 
- UCC_BMR_CETM
 
- UCC_BMR_DTB
 
- UCC_BMR_GBL
 
- UCC_FAST_16_BIT_CRC
 
- UCC_FAST_32_BIT_CRC
 
- UCC_FAST_CRC_RESERVED0
 
- UCC_FAST_CRC_RESERVED1
 
- UCC_FAST_DIAGNOSTIC_AUTO_ECHO
 
- UCC_FAST_DIAGNOSTIC_LOCAL_LOOP_BACK
 
- UCC_FAST_DIAGNOSTIC_LOOP_BACK_AND_ECHO
 
- UCC_FAST_DIAGNOSTIC_NORMAL
 
- UCC_FAST_FUNCTION_CODE_BDB_LCL
 
- UCC_FAST_FUNCTION_CODE_DTB_LCL
 
- UCC_FAST_FUNCTION_CODE_GBL
 
- UCC_FAST_GUMR_CDP
 
- UCC_FAST_GUMR_CDS
 
- UCC_FAST_GUMR_CTSP
 
- UCC_FAST_GUMR_CTSS
 
- UCC_FAST_GUMR_ENR
 
- UCC_FAST_GUMR_ENT
 
- UCC_FAST_GUMR_LOOPBACK
 
- UCC_FAST_GUMR_REVD
 
- UCC_FAST_GUMR_RSYN
 
- UCC_FAST_GUMR_RTSM
 
- UCC_FAST_GUMR_SYNL_16
 
- UCC_FAST_GUMR_SYNL_8
 
- UCC_FAST_GUMR_SYNL_AUTO
 
- UCC_FAST_GUMR_SYNL_MASK
 
- UCC_FAST_GUMR_TCI
 
- UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL
 
- UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_TRANSPARENT
 
- UCC_FAST_GUMR_TRX
 
- UCC_FAST_GUMR_TTX
 
- UCC_FAST_GUMR_TXSY
 
- UCC_FAST_MRBLR_ALIGNMENT
 
- UCC_FAST_PROTOCOL_MODE_ATM
 
- UCC_FAST_PROTOCOL_MODE_ETHERNET
 
- UCC_FAST_PROTOCOL_MODE_HDLC
 
- UCC_FAST_PROTOCOL_MODE_POS
 
- UCC_FAST_PROTOCOL_MODE_RESERVED01
 
- UCC_FAST_PROTOCOL_MODE_RESERVED02
 
- UCC_FAST_PROTOCOL_MODE_RESERVED03
 
- UCC_FAST_PROTOCOL_MODE_RESERVED04
 
- UCC_FAST_PROTOCOL_MODE_RESERVED05
 
- UCC_FAST_PROTOCOL_MODE_RESERVED06
 
- UCC_FAST_PROTOCOL_MODE_RESERVED07
 
- UCC_FAST_PROTOCOL_MODE_RESERVED_BISYNC
 
- UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_1
 
- UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_2
 
- UCC_FAST_PROTOCOL_MODE_RESERVED_QMC
 
- UCC_FAST_PROTOCOL_MODE_RESERVED_UART
 
- UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR
 
- UCC_FAST_RX_ALIGN
 
- UCC_FAST_RX_ENCODING_NRZ
 
- UCC_FAST_RX_ENCODING_NRZI
 
- UCC_FAST_RX_ENCODING_RESERVED0
 
- UCC_FAST_RX_ENCODING_RESERVED1
 
- UCC_FAST_SEND_FLAGS_BETWEEN_FRAMES
 
- UCC_FAST_SEND_IDLES_BETWEEN_FRAMES
 
- UCC_FAST_SYNC_LEN_16_BIT
 
- UCC_FAST_SYNC_LEN_8_BIT
 
- UCC_FAST_SYNC_LEN_AUTOMATIC
 
- UCC_FAST_SYNC_LEN_NOT_USED
 
- UCC_FAST_TOD
 
- UCC_FAST_TX_ENCODING_NRZ
 
- UCC_FAST_TX_ENCODING_NRZI
 
- UCC_FAST_TX_ENCODING_RESERVED0
 
- UCC_FAST_TX_ENCODING_RESERVED1
 
- UCC_FAST_URFS_MIN_VAL
 
- UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT
 
- UCC_GETH_BD_RING_SIZE_MAX
 
- UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH
 
- UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH
 
- UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR2
 
- UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR3
 
- UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_FIRST
 
- UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_LAST
 
- UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_STATION_ADDRESS
 
- UCC_GETH_IP_PRIORITY_MAX
 
- UCC_GETH_MACCFG1_INIT
 
- UCC_GETH_MACCFG2_INIT
 
- UCC_GETH_MRBLR_ALIGNMENT
 
- UCC_GETH_NUM_OF_STATION_ADDRESSES_1
 
- UCC_GETH_NUM_OF_STATION_ADDRESSES_5
 
- UCC_GETH_NUM_OF_THREADS_1
 
- UCC_GETH_NUM_OF_THREADS_2
 
- UCC_GETH_NUM_OF_THREADS_4
 
- UCC_GETH_NUM_OF_THREADS_6
 
- UCC_GETH_NUM_OF_THREADS_8
 
- UCC_GETH_PAD_AND_CRC_MODE_CRC_ONLY
 
- UCC_GETH_PAD_AND_CRC_MODE_NONE
 
- UCC_GETH_PAD_AND_CRC_MODE_PAD_AND_CRC
 
- UCC_GETH_QOS_MODE_DEFAULT
 
- UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L2_CRITERIA
 
- UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L3_CRITERIA
 
- UCC_GETH_REMODER_INIT
 
- UCC_GETH_RX_BD_QUEUES_ALIGNMENT
 
- UCC_GETH_RX_BD_RING_ALIGNMENT
 
- UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT
 
- UCC_GETH_RX_BD_RING_SIZE_MIN
 
- UCC_GETH_RX_DATA_BUF_ALIGNMENT
 
- UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT
 
- UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT
 
- UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT
 
- UCC_GETH_RX_PREFETCHED_BDS_ALIGNMENT
 
- UCC_GETH_RX_STATISTICS_ALIGNMENT
 
- UCC_GETH_SCHEDULER_ALIGNMENT
 
- UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT
 
- UCC_GETH_SIZE_OF_BD
 
- UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX
 
- UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX
 
- UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE
 
- UCC_GETH_STATISTICS_GATHERING_MODE_NONE
 
- UCC_GETH_TAD_CFI
 
- UCC_GETH_TAD_EF
 
- UCC_GETH_TAD_REJ
 
- UCC_GETH_TAD_RQOS_SHIFT
 
- UCC_GETH_TAD_V
 
- UCC_GETH_TAD_VTAG_OP_RIGHT_SHIFT
 
- UCC_GETH_TAD_VTAG_OP_SHIFT
 
- UCC_GETH_TAD_V_NON_VTAG_OP
 
- UCC_GETH_TAD_V_PRIORITY_SHIFT
 
- UCC_GETH_TEMODER_INIT
 
- UCC_GETH_THREAD_DATA_ALIGNMENT
 
- UCC_GETH_THREAD_RX_PRAM_ALIGNMENT
 
- UCC_GETH_THREAD_TX_PRAM_ALIGNMENT
 
- UCC_GETH_TX_BD_RING_ALIGNMENT
 
- UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
 
- UCC_GETH_TX_BD_RING_SIZE_MIN
 
- UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT
 
- UCC_GETH_TX_STATISTICS_ALIGNMENT
 
- UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX
 
- UCC_GETH_UCCE_BSY
 
- UCC_GETH_UCCE_CBPR
 
- UCC_GETH_UCCE_GRA
 
- UCC_GETH_UCCE_MPD
 
- UCC_GETH_UCCE_RXB0
 
- UCC_GETH_UCCE_RXB1
 
- UCC_GETH_UCCE_RXB2
 
- UCC_GETH_UCCE_RXB3
 
- UCC_GETH_UCCE_RXB4
 
- UCC_GETH_UCCE_RXB5
 
- UCC_GETH_UCCE_RXB6
 
- UCC_GETH_UCCE_RXB7
 
- UCC_GETH_UCCE_RXC
 
- UCC_GETH_UCCE_RXF0
 
- UCC_GETH_UCCE_RXF1
 
- UCC_GETH_UCCE_RXF2
 
- UCC_GETH_UCCE_RXF3
 
- UCC_GETH_UCCE_RXF4
 
- UCC_GETH_UCCE_RXF5
 
- UCC_GETH_UCCE_RXF6
 
- UCC_GETH_UCCE_RXF7
 
- UCC_GETH_UCCE_SCAR
 
- UCC_GETH_UCCE_TXB0
 
- UCC_GETH_UCCE_TXB1
 
- UCC_GETH_UCCE_TXB2
 
- UCC_GETH_UCCE_TXB3
 
- UCC_GETH_UCCE_TXB4
 
- UCC_GETH_UCCE_TXB5
 
- UCC_GETH_UCCE_TXB6
 
- UCC_GETH_UCCE_TXB7
 
- UCC_GETH_UCCE_TXC
 
- UCC_GETH_UCCE_TXE
 
- UCC_GETH_UPSMR_BRO
 
- UCC_GETH_UPSMR_CAM
 
- UCC_GETH_UPSMR_CAP
 
- UCC_GETH_UPSMR_ECM
 
- UCC_GETH_UPSMR_FTFE
 
- UCC_GETH_UPSMR_HSE
 
- UCC_GETH_UPSMR_INIT
 
- UCC_GETH_UPSMR_PRO
 
- UCC_GETH_UPSMR_PTPE
 
- UCC_GETH_UPSMR_R10M
 
- UCC_GETH_UPSMR_RES1
 
- UCC_GETH_UPSMR_RLPB
 
- UCC_GETH_UPSMR_RMM
 
- UCC_GETH_UPSMR_RPM
 
- UCC_GETH_UPSMR_RSH
 
- UCC_GETH_UPSMR_SGMM
 
- UCC_GETH_UPSMR_SMM
 
- UCC_GETH_UPSMR_TBIM
 
- UCC_GETH_URFET_GIGA_INIT
 
- UCC_GETH_URFET_INIT
 
- UCC_GETH_URFSET_GIGA_INIT
 
- UCC_GETH_URFSET_INIT
 
- UCC_GETH_URFS_GIGA_INIT
 
- UCC_GETH_URFS_INIT
 
- UCC_GETH_UTFET_GIGA_INIT
 
- UCC_GETH_UTFET_INIT
 
- UCC_GETH_UTFS_GIGA_INIT
 
- UCC_GETH_UTFS_INIT
 
- UCC_GETH_UTFTT_GIGA_INIT
 
- UCC_GETH_UTFTT_INIT
 
- UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP
 
- UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT
 
- UCC_GETH_VLAN_OPERATION_TAGGED_EXTRACT_Q_TAG_FROM_FRAME
 
- UCC_GETH_VLAN_OPERATION_TAGGED_IF_VID0_REPLACE_VID_WITH_DEFAULT_VALUE
 
- UCC_GETH_VLAN_OPERATION_TAGGED_NOP
 
- UCC_GETH_VLAN_OPERATION_TAGGED_REPLACE_VID_PORTION_OF_Q_TAG
 
- UCC_GETH_VLAN_PRIORITY_MAX
 
- UCC_GUEMR_MODE_FAST_RX
 
- UCC_GUEMR_MODE_FAST_TX
 
- UCC_GUEMR_MODE_MASK
 
- UCC_GUEMR_MODE_MASK_RX
 
- UCC_GUEMR_MODE_MASK_TX
 
- UCC_GUEMR_MODE_SLOW_RX
 
- UCC_GUEMR_MODE_SLOW_TX
 
- UCC_GUEMR_SET_RESERVED3
 
- UCC_HDLC_UCCE_BRKE
 
- UCC_HDLC_UCCE_BRKS
 
- UCC_HDLC_UCCE_BSY
 
- UCC_HDLC_UCCE_GLR
 
- UCC_HDLC_UCCE_GLT
 
- UCC_HDLC_UCCE_IDLE
 
- UCC_HDLC_UCCE_RXB
 
- UCC_HDLC_UCCE_RXF
 
- UCC_HDLC_UCCE_TXB
 
- UCC_HDLC_UCCE_TXE
 
- UCC_HDLC_UPSMR_BUS
 
- UCC_HDLC_UPSMR_CW8
 
- UCC_HDLC_UPSMR_RTE
 
- UCC_MAX_NUM
 
- UCC_MAX_UART
 
- UCC_SLOW_CHANNEL_PROTOCOL_MODE_BISYNC
 
- UCC_SLOW_CHANNEL_PROTOCOL_MODE_QMC
 
- UCC_SLOW_CHANNEL_PROTOCOL_MODE_UART
 
- UCC_SLOW_DIAG_MODE_ECHO
 
- UCC_SLOW_DIAG_MODE_LOOPBACK
 
- UCC_SLOW_DIAG_MODE_LOOPBACK_ECHO
 
- UCC_SLOW_DIAG_MODE_NORMAL
 
- UCC_SLOW_GUMR_H_16SYNC
 
- UCC_SLOW_GUMR_H_4SYNC
 
- UCC_SLOW_GUMR_H_8SYNC
 
- UCC_SLOW_GUMR_H_CDP
 
- UCC_SLOW_GUMR_H_CDS
 
- UCC_SLOW_GUMR_H_CTSP
 
- UCC_SLOW_GUMR_H_CTSS
 
- UCC_SLOW_GUMR_H_REVD
 
- UCC_SLOW_GUMR_H_RFW
 
- UCC_SLOW_GUMR_H_RSYN
 
- UCC_SLOW_GUMR_H_RTSM
 
- UCC_SLOW_GUMR_H_SAM_QMC
 
- UCC_SLOW_GUMR_H_SAM_SATM
 
- UCC_SLOW_GUMR_H_SUART
 
- UCC_SLOW_GUMR_H_TFL
 
- UCC_SLOW_GUMR_H_TRX
 
- UCC_SLOW_GUMR_H_TTX
 
- UCC_SLOW_GUMR_H_TXSY
 
- UCC_SLOW_GUMR_L_DIAG_ECHO
 
- UCC_SLOW_GUMR_L_DIAG_LE
 
- UCC_SLOW_GUMR_L_DIAG_LOOP
 
- UCC_SLOW_GUMR_L_DIAG_MASK
 
- UCC_SLOW_GUMR_L_DIAG_NORM
 
- UCC_SLOW_GUMR_L_ENR
 
- UCC_SLOW_GUMR_L_ENT
 
- UCC_SLOW_GUMR_L_MODE_AHDLC
 
- UCC_SLOW_GUMR_L_MODE_BISYNC
 
- UCC_SLOW_GUMR_L_MODE_MASK
 
- UCC_SLOW_GUMR_L_MODE_QMC
 
- UCC_SLOW_GUMR_L_MODE_UART
 
- UCC_SLOW_GUMR_L_RDCR_1
 
- UCC_SLOW_GUMR_L_RDCR_16
 
- UCC_SLOW_GUMR_L_RDCR_32
 
- UCC_SLOW_GUMR_L_RDCR_8
 
- UCC_SLOW_GUMR_L_RDCR_MASK
 
- UCC_SLOW_GUMR_L_RENC_NRZ
 
- UCC_SLOW_GUMR_L_RENC_NRZI
 
- UCC_SLOW_GUMR_L_RINV
 
- UCC_SLOW_GUMR_L_TCI
 
- UCC_SLOW_GUMR_L_TDCR_1
 
- UCC_SLOW_GUMR_L_TDCR_16
 
- UCC_SLOW_GUMR_L_TDCR_32
 
- UCC_SLOW_GUMR_L_TDCR_8
 
- UCC_SLOW_GUMR_L_TDCR_MASK
 
- UCC_SLOW_GUMR_L_TENC_NRZ
 
- UCC_SLOW_GUMR_L_TENC_NRZI
 
- UCC_SLOW_GUMR_L_TEND
 
- UCC_SLOW_GUMR_L_TINV
 
- UCC_SLOW_MRBLR_ALIGNMENT
 
- UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_1
 
- UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_16
 
- UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_32
 
- UCC_SLOW_OVERSAMPLING_RATE_RX_RDCR_8
 
- UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_1
 
- UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_16
 
- UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_32
 
- UCC_SLOW_OVERSAMPLING_RATE_TX_TDCR_8
 
- UCC_SLOW_PRAM_SIZE
 
- UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZ
 
- UCC_SLOW_RECEIVER_DECODING_METHOD_RENC_NRZI
 
- UCC_SLOW_RX_ALIGN
 
- UCC_SLOW_TOD
 
- UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZ
 
- UCC_SLOW_TRANSMITTER_ENCODING_METHOD_TENC_NRZI
 
- UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC16
 
- UCC_SLOW_TRANSPARENT_TCRC_CCITT_CRC32
 
- UCC_SLOW_TRANSPARENT_TCRC_CRC16
 
- UCC_SPEED_TYPE_FAST
 
- UCC_SPEED_TYPE_SLOW
 
- UCC_TDM_NUM
 
- UCC_UART_PRAM_ALIGNMENT
 
- UCC_UART_SIZE_OF_BD
 
- UCC_UART_SUPSMR_CL_5
 
- UCC_UART_SUPSMR_CL_6
 
- UCC_UART_SUPSMR_CL_7
 
- UCC_UART_SUPSMR_CL_8
 
- UCC_UART_SUPSMR_CL_MASK
 
- UCC_UART_SUPSMR_FRZ
 
- UCC_UART_SUPSMR_PEN
 
- UCC_UART_SUPSMR_RPM_EVEN
 
- UCC_UART_SUPSMR_RPM_HIGH
 
- UCC_UART_SUPSMR_RPM_LOW
 
- UCC_UART_SUPSMR_RPM_MASK
 
- UCC_UART_SUPSMR_RPM_ODD
 
- UCC_UART_SUPSMR_SL
 
- UCC_UART_SUPSMR_TPM_EVEN
 
- UCC_UART_SUPSMR_TPM_HIGH
 
- UCC_UART_SUPSMR_TPM_LOW
 
- UCC_UART_SUPSMR_TPM_MASK
 
- UCC_UART_SUPSMR_TPM_ODD
 
- UCC_UART_SUPSMR_UM_AUTO_MULTI
 
- UCC_UART_SUPSMR_UM_MAN_MULTI
 
- UCC_UART_SUPSMR_UM_MASK
 
- UCC_UART_SUPSMR_UM_NORMAL
 
- UCC_UART_TX_STATE_AHDLC
 
- UCC_UART_TX_STATE_UART
 
- UCC_UART_TX_STATE_X1
 
- UCC_UART_TX_STATE_X16
 
- UCC_UART_UCCE_AB
 
- UCC_UART_UCCE_BRKE
 
- UCC_UART_UCCE_BRKS
 
- UCC_UART_UCCE_BSY
 
- UCC_UART_UCCE_CCR
 
- UCC_UART_UCCE_GRA
 
- UCC_UART_UCCE_IDLE
 
- UCC_UART_UCCE_RX
 
- UCC_UART_UCCE_TX
 
- UCC_UART_UPSMR_CL_5
 
- UCC_UART_UPSMR_CL_6
 
- UCC_UART_UPSMR_CL_7
 
- UCC_UART_UPSMR_CL_8
 
- UCC_UART_UPSMR_CL_MASK
 
- UCC_UART_UPSMR_DRT
 
- UCC_UART_UPSMR_FLC
 
- UCC_UART_UPSMR_FRZ
 
- UCC_UART_UPSMR_PEN
 
- UCC_UART_UPSMR_RPM_EVEN
 
- UCC_UART_UPSMR_RPM_HIGH
 
- UCC_UART_UPSMR_RPM_LOW
 
- UCC_UART_UPSMR_RPM_MASK
 
- UCC_UART_UPSMR_RPM_ODD
 
- UCC_UART_UPSMR_RZS
 
- UCC_UART_UPSMR_SL
 
- UCC_UART_UPSMR_SYN
 
- UCC_UART_UPSMR_TPM_EVEN
 
- UCC_UART_UPSMR_TPM_HIGH
 
- UCC_UART_UPSMR_TPM_LOW
 
- UCC_UART_UPSMR_TPM_MASK
 
- UCC_UART_UPSMR_TPM_ODD
 
- UCC_UART_UPSMR_UM_AUTO_MULTI
 
- UCC_UART_UPSMR_UM_MAN_MULTI
 
- UCC_UART_UPSMR_UM_MASK
 
- UCC_UART_UPSMR_UM_NORMAL
 
- UCC_WAIT_CLOSING
 
- UCD9000_DEBUGFS_NAME_LEN
 
- UCD9000_DEVICE_ID
 
- UCD9000_FAN_CONFIG
 
- UCD9000_FAN_CONFIG_INDEX
 
- UCD9000_GPIO_CONFIG
 
- UCD9000_GPIO_CONFIG_ENABLE
 
- UCD9000_GPIO_CONFIG_OUT_ENABLE
 
- UCD9000_GPIO_CONFIG_OUT_VALUE
 
- UCD9000_GPIO_CONFIG_STATUS
 
- UCD9000_GPIO_INPUT
 
- UCD9000_GPIO_NAME_LEN
 
- UCD9000_GPIO_OUTPUT
 
- UCD9000_GPIO_SELECT
 
- UCD9000_GPI_COUNT
 
- UCD9000_MFR_STATUS
 
- UCD9000_MONITOR_CONFIG
 
- UCD9000_MON_CURRENT
 
- UCD9000_MON_PAGE
 
- UCD9000_MON_TEMPERATURE
 
- UCD9000_MON_TYPE
 
- UCD9000_MON_VOLTAGE
 
- UCD9000_MON_VOLTAGE_HW
 
- UCD9000_NUM_FAN
 
- UCD9000_NUM_PAGES
 
- UCD901XX_NUM_GPIOS
 
- UCD9090_NUM_GPIOS
 
- UCD90910_NUM_GPIOS
 
- UCD9200_DEVICE_ID
 
- UCD9200_PHASE_INFO
 
- UCDC_SEND_ENCAPSULATED_COMMAND
 
- UCDR_ENABLE
 
- UCDR_SO_SATURATION
 
- UCDR_STEP_BY_TWO_MODE0
 
- UCDR_xO_GAIN_MODE
 
- UCD_AE_CNTX
 
- UCD_AE_EID_UCODE_BLOCK_NUMX
 
- UCD_BIST_STATUS
 
- UCD_SE_CNTX
 
- UCD_SE_EID_UCODE_BLOCK_NUMX
 
- UCD_UCODE_LOAD_BLOCK_NUM
 
- UCD_UCODE_LOAD_IDX_DATAX
 
- UCEN
 
- UCHAR
 
- UCHAR8
 
- UCHAR_T_SIZE_BITS
 
- UCHE_BUSY_CYCLES
 
- UCHE_EVICTS
 
- UCHE_FLUSHES
 
- UCHE_POWER0
 
- UCHE_POWER1
 
- UCHE_POWER2
 
- UCHE_POWER3
 
- UCHE_POWER4
 
- UCHE_POWER5
 
- UCHE_POWER6
 
- UCHE_POWER7
 
- UCHE_READ_REQUESTS_HLSQ
 
- UCHE_READ_REQUESTS_MARB
 
- UCHE_READ_REQUESTS_PC
 
- UCHE_READ_REQUESTS_SP
 
- UCHE_READ_REQUESTS_TP
 
- UCHE_READ_REQUESTS_VFD
 
- UCHE_STALL_BY_VBIF
 
- UCHE_TAG_CHECK_FAILS
 
- UCHE_UCHEPERF_ACTIVE_CYCLES
 
- UCHE_UCHEPERF_EVICTS
 
- UCHE_UCHEPERF_FLUSHES
 
- UCHE_UCHEPERF_READ_REQUESTS_HLSQ
 
- UCHE_UCHEPERF_READ_REQUESTS_MARB
 
- UCHE_UCHEPERF_READ_REQUESTS_SP
 
- UCHE_UCHEPERF_READ_REQUESTS_TP
 
- UCHE_UCHEPERF_READ_REQUESTS_VFD
 
- UCHE_UCHEPERF_TAG_CHECK_FAILS
 
- UCHE_UCHEPERF_VBIF_LATENCY_CYCLES
 
- UCHE_UCHEPERF_VBIF_LATENCY_SAMPLES
 
- UCHE_UCHEPERF_VBIF_READ_BEATS_HLSQ
 
- UCHE_UCHEPERF_VBIF_READ_BEATS_MARB
 
- UCHE_UCHEPERF_VBIF_READ_BEATS_SP
 
- UCHE_UCHEPERF_VBIF_READ_BEATS_TP
 
- UCHE_UCHEPERF_VBIF_READ_BEATS_VFD
 
- UCHE_UCHEPERF_WRITE_REQUESTS_MARB
 
- UCHE_UCHEPERF_WRITE_REQUESTS_SP
 
- UCHE_VBIF_LATENCY_CYCLES
 
- UCHE_VBIF_LATENCY_SAMPLES
 
- UCHE_VBIF_READ_BEATS_HLSQ
 
- UCHE_VBIF_READ_BEATS_MARB
 
- UCHE_VBIF_READ_BEATS_PC
 
- UCHE_VBIF_READ_BEATS_SP
 
- UCHE_VBIF_READ_BEATS_TP
 
- UCHE_VBIF_READ_BEATS_VFD
 
- UCHE_WRITE_REQUESTS_MARB
 
- UCHE_WRITE_REQUESTS_SP
 
- UCHE_WRITE_REQUESTS_VPC
 
- UCHE_WRITE_REQUESTS_VSC
 
- UCHIP_RF
 
- UCI_REG_DEVARCH_OFFSET
 
- UCI_REG_DEVTYPE_OFFSET
 
- UCKSEL
 
- UCLAMP_BUCKETS
 
- UCLAMP_BUCKET_DELTA
 
- UCLAMP_CNT
 
- UCLAMP_FLAG_IDLE
 
- UCLAMP_MAX
 
- UCLAMP_MIN
 
- UCLAMP_PERCENT_SCALE
 
- UCLAMP_PERCENT_SHIFT
 
- UCLK
 
- UCLK_DIV_BY_1
 
- UCLK_DIV_BY_2
 
- UCLK_DIV_BY_4
 
- UCLK_DIV_BY_8
 
- UCLK_DIV_e
 
- UCLK_SWITCH_FAST
 
- UCLK_SWITCH_SLOW
 
- UCLK_VLD
 
- UCLOGIC_PARAMS_FMT_ARGS
 
- UCLOGIC_PARAMS_FMT_STR
 
- UCLOGIC_PARAMS_PEN_INRANGE_INVERTED
 
- UCLOGIC_PARAMS_PEN_INRANGE_NONE
 
- UCLOGIC_PARAMS_PEN_INRANGE_NORMAL
 
- UCLOGIC_RDESC_BUTTONPAD_BYTES
 
- UCLOGIC_RDESC_BUTTONPAD_V1_ID
 
- UCLOGIC_RDESC_BUTTONPAD_V2_ID
 
- UCLOGIC_RDESC_PEN_PH
 
- UCLOGIC_RDESC_PEN_PH_ID_NUM
 
- UCLOGIC_RDESC_PEN_PH_ID_PRESSURE_LM
 
- UCLOGIC_RDESC_PEN_PH_ID_X_LM
 
- UCLOGIC_RDESC_PEN_PH_ID_X_PM
 
- UCLOGIC_RDESC_PEN_PH_ID_Y_LM
 
- UCLOGIC_RDESC_PEN_PH_ID_Y_PM
 
- UCLOGIC_RDESC_PEN_V1_ID
 
- UCLOGIC_RDESC_PEN_V2_ID
 
- UCLOGIC_RDESC_PF1209_ORIG_SIZE
 
- UCLOGIC_RDESC_PH_HEAD
 
- UCLOGIC_RDESC_TWHA60_ORIG0_SIZE
 
- UCLOGIC_RDESC_TWHA60_ORIG1_SIZE
 
- UCLOGIC_RDESC_TWHL850_ORIG0_SIZE
 
- UCLOGIC_RDESC_TWHL850_ORIG1_SIZE
 
- UCLOGIC_RDESC_TWHL850_ORIG2_SIZE
 
- UCLOGIC_RDESC_UGEE_G5_FRAME_DEV_ID_BYTE
 
- UCLOGIC_RDESC_UGEE_G5_FRAME_ID
 
- UCLOGIC_RDESC_UGEE_G5_FRAME_RE_LSB
 
- UCLOGIC_RDESC_WP1062_ORIG_SIZE
 
- UCLOGIC_RDESC_WP5540U_V2_ORIG_SIZE
 
- UCLOGIC_RDESC_WPXXXXU_ORIG_SIZE
 
- UCM_REG_AGG_CON_CTX
 
- UCM_REG_AGG_TASK_CTX
 
- UCM_REG_AG_CTX
 
- UCM_REG_CAM_OCCUP
 
- UCM_REG_CDU_AG_RD_IFEN
 
- UCM_REG_CDU_AG_WR_IFEN
 
- UCM_REG_CDU_SM_RD_IFEN
 
- UCM_REG_CDU_SM_WR_IFEN
 
- UCM_REG_CFC_INIT_CRD
 
- UCM_REG_CP_WEIGHT
 
- UCM_REG_CSEM_IFEN
 
- UCM_REG_CSEM_LENGTH_MIS
 
- UCM_REG_CSEM_WEIGHT
 
- UCM_REG_CTX_RBC_ACCS
 
- UCM_REG_DBG_DWORD_ENABLE
 
- UCM_REG_DBG_FORCE_FRAME
 
- UCM_REG_DBG_FORCE_VALID
 
- UCM_REG_DBG_SELECT
 
- UCM_REG_DBG_SHIFT
 
- UCM_REG_DORQ_IFEN
 
- UCM_REG_DORQ_LENGTH_MIS
 
- UCM_REG_DORQ_WEIGHT
 
- UCM_REG_ERR_EVNT_ID
 
- UCM_REG_ERR_UCM_HDR
 
- UCM_REG_EXPR_EVNT_ID
 
- UCM_REG_FIC0_INIT_CRD
 
- UCM_REG_FIC1_INIT_CRD
 
- UCM_REG_GR_ARB_TYPE
 
- UCM_REG_GR_LD0_PR
 
- UCM_REG_GR_LD1_PR
 
- UCM_REG_INIT
 
- UCM_REG_INV_CFLG_Q
 
- UCM_REG_N_SM_CTX_LD_0
 
- UCM_REG_N_SM_CTX_LD_1
 
- UCM_REG_N_SM_CTX_LD_2
 
- UCM_REG_N_SM_CTX_LD_3
 
- UCM_REG_N_SM_CTX_LD_4
 
- UCM_REG_N_SM_CTX_LD_5
 
- UCM_REG_PHYS_QNUM0_0
 
- UCM_REG_PHYS_QNUM0_1
 
- UCM_REG_PHYS_QNUM1_0
 
- UCM_REG_PHYS_QNUM1_1
 
- UCM_REG_PHYS_QNUM2_0
 
- UCM_REG_PHYS_QNUM2_1
 
- UCM_REG_PHYS_QNUM3_0
 
- UCM_REG_PHYS_QNUM3_1
 
- UCM_REG_SM_CON_CTX
 
- UCM_REG_SM_TASK_CTX
 
- UCM_REG_STOP_EVNT_ID
 
- UCM_REG_STORM_LENGTH_MIS
 
- UCM_REG_STORM_UCM_IFEN
 
- UCM_REG_STORM_WEIGHT
 
- UCM_REG_TM_INIT_CRD
 
- UCM_REG_TM_UCM_HDR
 
- UCM_REG_TM_UCM_IFEN
 
- UCM_REG_TM_WEIGHT
 
- UCM_REG_TSEM_IFEN
 
- UCM_REG_TSEM_LENGTH_MIS
 
- UCM_REG_TSEM_WEIGHT
 
- UCM_REG_UCM_CFC_IFEN
 
- UCM_REG_UCM_INT_MASK
 
- UCM_REG_UCM_INT_STS
 
- UCM_REG_UCM_PRTY_MASK
 
- UCM_REG_UCM_PRTY_STS
 
- UCM_REG_UCM_PRTY_STS_CLR
 
- UCM_REG_UCM_REG0_SZ
 
- UCM_REG_UCM_STORM0_IFEN
 
- UCM_REG_UCM_STORM1_IFEN
 
- UCM_REG_UCM_TM_IFEN
 
- UCM_REG_UCM_UQM_IFEN
 
- UCM_REG_UCM_UQM_USE_Q
 
- UCM_REG_UQM_INIT_CRD
 
- UCM_REG_UQM_P_WEIGHT
 
- UCM_REG_UQM_S_WEIGHT
 
- UCM_REG_UQM_UCM_HDR_P
 
- UCM_REG_UQM_UCM_HDR_S
 
- UCM_REG_UQM_UCM_IFEN
 
- UCM_REG_USDM_IFEN
 
- UCM_REG_USDM_LENGTH_MIS
 
- UCM_REG_USDM_WEIGHT
 
- UCM_REG_XSEM_IFEN
 
- UCM_REG_XSEM_LENGTH_MIS
 
- UCM_REG_XSEM_WEIGHT
 
- UCM_REG_XX_DESCR_TABLE
 
- UCM_REG_XX_DESCR_TABLE_SIZE
 
- UCM_REG_XX_FREE
 
- UCM_REG_XX_INIT_CRD
 
- UCM_REG_XX_MSG_NUM
 
- UCM_REG_XX_OVFL_EVNT_ID
 
- UCM_REG_XX_TABLE
 
- UCODE_ALIVE_TIMEOUT
 
- UCODE_CALIB_TIMEOUT
 
- UCODE_EQUIV_CPU_TABLE_TYPE
 
- UCODE_ERROR
 
- UCODE_FLAG_UNHALT_MASK
 
- UCODE_HLEN
 
- UCODE_ID_CP_CE
 
- UCODE_ID_CP_CE_MASK
 
- UCODE_ID_CP_CE_SIZE_BYTE
 
- UCODE_ID_CP_ME
 
- UCODE_ID_CP_MEC
 
- UCODE_ID_CP_MEC_JT1
 
- UCODE_ID_CP_MEC_JT1_MASK
 
- UCODE_ID_CP_MEC_JT1_SIZE_BYTE
 
- UCODE_ID_CP_MEC_JT2
 
- UCODE_ID_CP_MEC_JT2_MASK
 
- UCODE_ID_CP_MEC_JT2_SIZE_BYTE
 
- UCODE_ID_CP_MEC_MASK
 
- UCODE_ID_CP_ME_MASK
 
- UCODE_ID_CP_ME_SIZE_BYTE
 
- UCODE_ID_CP_PFP
 
- UCODE_ID_CP_PFP_MASK
 
- UCODE_ID_CP_PFP_SIZE_BYTE
 
- UCODE_ID_DMCU_ERAM
 
- UCODE_ID_DMCU_ERAM_MASK
 
- UCODE_ID_DMCU_ERAM_SIZE_BYTE
 
- UCODE_ID_DMCU_IRAM
 
- UCODE_ID_DMCU_IRAM_MASK
 
- UCODE_ID_DMCU_IRAM_SIZE_BYTE
 
- UCODE_ID_GMCON_RENG
 
- UCODE_ID_GMCON_RENG_MASK
 
- UCODE_ID_GMCON_RENG_SIZE_BYTE
 
- UCODE_ID_IH_REG_RESTORE
 
- UCODE_ID_IH_REG_RESTORE_MASK
 
- UCODE_ID_MEC_STORAGE
 
- UCODE_ID_MISC_METADATA
 
- UCODE_ID_RLC_G
 
- UCODE_ID_RLC_G_MASK
 
- UCODE_ID_RLC_G_SIZE_BYTE
 
- UCODE_ID_RLC_SCRATCH
 
- UCODE_ID_RLC_SCRATCH_MASK
 
- UCODE_ID_RLC_SCRATCH_SIZE_BYTE
 
- UCODE_ID_RLC_SRM_ARAM
 
- UCODE_ID_RLC_SRM_ARAM_MASK
 
- UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE
 
- UCODE_ID_RLC_SRM_DRAM
 
- UCODE_ID_RLC_SRM_DRAM_MASK
 
- UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE
 
- UCODE_ID_SDMA0
 
- UCODE_ID_SDMA0_MASK
 
- UCODE_ID_SDMA0_SIZE_BYTE
 
- UCODE_ID_SDMA1
 
- UCODE_ID_SDMA1_MASK
 
- UCODE_ID_SDMA1_SIZE_BYTE
 
- UCODE_ID_SMU
 
- UCODE_ID_SMU_MASK
 
- UCODE_ID_SMU_SK
 
- UCODE_ID_VBIOS
 
- UCODE_ID_VBIOS_MASK
 
- UCODE_ID_VBIOS_PARAMETERS
 
- UCODE_INIT
 
- UCODE_LOADER_API_VER
 
- UCODE_MAGIC
 
- UCODE_META_DATA
 
- UCODE_NEW
 
- UCODE_NFOUND
 
- UCODE_NONE
 
- UCODE_OK
 
- UCODE_READY_TIMEOUT
 
- UCODE_ROM_START_ADDRESS
 
- UCODE_RT
 
- UCODE_SIGNATURE
 
- UCODE_SIZE
 
- UCODE_STATISTICS_CLEAR_MSK
 
- UCODE_STATISTICS_FREQUENCY_MSK
 
- UCODE_STATISTICS_NARROW_BAND_MSK
 
- UCODE_STATS_CLEAR_MSK
 
- UCODE_STATS_FREQUENCY_MSK
 
- UCODE_STATS_NARROW_BAND_MSK
 
- UCODE_TRACE_PERIOD
 
- UCODE_UCODE_TYPE
 
- UCODE_UPDATED
 
- UCODE_UPLOAD
 
- UCODE_VALID_OK
 
- UCODE_VERIFY
 
- UCON
 
- UCONFIG_SPACE_END
 
- UCONFIG_SPACE_START
 
- UCONTEXTSIZEWITHOUTVSX
 
- UCONTEXT_BANNABLE
 
- UCONTEXT_MSR
 
- UCONTEXT_NIA
 
- UCONTEXT_NO_ERROR_CAPTURE
 
- UCONTEXT_NO_ZEROMAP
 
- UCONTEXT_RECOVERABLE
 
- UCOUNTS_HASHTABLE_BITS
 
- UCOUNT_CGROUP_NAMESPACES
 
- UCOUNT_COUNTS
 
- UCOUNT_ENTRY
 
- UCOUNT_INOTIFY_INSTANCES
 
- UCOUNT_INOTIFY_WATCHES
 
- UCOUNT_IPC_NAMESPACES
 
- UCOUNT_MNT_NAMESPACES
 
- UCOUNT_NET_NAMESPACES
 
- UCOUNT_PID_NAMESPACES
 
- UCOUNT_USER_NAMESPACES
 
- UCOUNT_UTS_NAMESPACES
 
- UCPI_UBH
 
- UCR1
 
- UCR1_ADBR
 
- UCR1_ADEN
 
- UCR1_ATDMAEN
 
- UCR1_DOZE
 
- UCR1_ICD_REG
 
- UCR1_IDEN
 
- UCR1_IREN
 
- UCR1_RRDYEN
 
- UCR1_RTSDEN
 
- UCR1_RXDMAEN
 
- UCR1_SNDBRK
 
- UCR1_TRDYEN
 
- UCR1_TXDMAEN
 
- UCR1_TXMPTYEN
 
- UCR1_UARTEN
 
- UCR2
 
- UCR2_ATEN
 
- UCR2_CTS
 
- UCR2_CTSC
 
- UCR2_ESCEN
 
- UCR2_ESCI
 
- UCR2_IRTS
 
- UCR2_PREN
 
- UCR2_PROE
 
- UCR2_RTSEN
 
- UCR2_RXEN
 
- UCR2_SRST
 
- UCR2_STPB
 
- UCR2_TXEN
 
- UCR2_WS
 
- UCR3
 
- UCR3_ADNIMP
 
- UCR3_AIRINTEN
 
- UCR3_AWAKEN
 
- UCR3_BPEN
 
- UCR3_DCD
 
- UCR3_DSR
 
- UCR3_DTRDEN
 
- UCR3_DTREN
 
- UCR3_FRAERREN
 
- UCR3_INVT
 
- UCR3_PARERREN
 
- UCR3_RI
 
- UCR3_RXDSEN
 
- UCR4
 
- UCR4_BKEN
 
- UCR4_CTSTL_MASK
 
- UCR4_CTSTL_SHF
 
- UCR4_DREN
 
- UCR4_ENIRI
 
- UCR4_IDDMAEN
 
- UCR4_INVR
 
- UCR4_IRSC
 
- UCR4_OREN
 
- UCR4_REF16
 
- UCR4_TCEN
 
- UCR4_WKEN
 
- UCS1002_ILIM_SW_MASK
 
- UCS1002_MANUFACTURER
 
- UCS1002_PRODUCT_ID
 
- UCS1002_PWR_STATE_MASK
 
- UCS1002_REG_CURRENT_MEASUREMENT
 
- UCS1002_REG_EMU_CFG
 
- UCS1002_REG_GENERAL_CFG
 
- UCS1002_REG_ILIMIT
 
- UCS1002_REG_INTERRUPT_STATUS
 
- UCS1002_REG_OTHER_STATUS
 
- UCS1002_REG_PIN_STATUS
 
- UCS1002_REG_PRODUCT_ID
 
- UCS1002_REG_SWITCH_CFG
 
- UCS1002_REG_TOTAL_ACC_CHARGE
 
- UCSC_CC_STATUS_PWRDEFSNK
 
- UCSC_CC_STATUS_PWR_1P5A_SNK
 
- UCSC_CC_STATUS_PWR_3A_SNK
 
- UCSC_CC_STATUS_RX
 
- UCSC_CC_STATUS_SNK_RP
 
- UCSC_CC_STATUS_SRC_RP
 
- UCSI_ACK_CC_CI
 
- UCSI_ACK_CMD
 
- UCSI_ACK_EVENT
 
- UCSI_BUSY
 
- UCSI_CABLE_PROPERTY_PLUG_OTHER
 
- UCSI_CABLE_PROPERTY_PLUG_TYPE_A
 
- UCSI_CABLE_PROPERTY_PLUG_TYPE_B
 
- UCSI_CABLE_PROPERTY_PLUG_TYPE_C
 
- UCSI_CANCEL
 
- UCSI_CAP_ALT_MODE_DETAILS
 
- UCSI_CAP_ALT_MODE_OVERRIDE
 
- UCSI_CAP_ATTR_BATTERY_CHARGING
 
- UCSI_CAP_ATTR_DISABLE_STATE
 
- UCSI_CAP_ATTR_POWER_AC_SUPPLY
 
- UCSI_CAP_ATTR_POWER_OTHER
 
- UCSI_CAP_ATTR_POWER_VBUS
 
- UCSI_CAP_ATTR_TYPEC_CURRENT
 
- UCSI_CAP_ATTR_USB_PD
 
- UCSI_CAP_CABLE_DETAILS
 
- UCSI_CAP_EXT_SUPPLY_NOTIFICATIONS
 
- UCSI_CAP_PDO_DETAILS
 
- UCSI_CAP_PD_RESET
 
- UCSI_CAP_SET_PDM
 
- UCSI_CAP_SET_UOM
 
- UCSI_CMD_ACK
 
- UCSI_CMD_CONNECTOR_RESET
 
- UCSI_CMD_GET_ALTERNATE_MODES
 
- UCSI_CMD_GET_CAM_SUPPORTED
 
- UCSI_CMD_GET_CAPABILITY
 
- UCSI_CMD_GET_CONNECTOR_CAPABILITY
 
- UCSI_CMD_GET_CONNECTOR_STATUS
 
- UCSI_CMD_GET_CURRENT_CAM
 
- UCSI_CMD_SET_NEW_CAM
 
- UCSI_CMD_SET_NTFY_ENABLE
 
- UCSI_CMD_SET_PDR
 
- UCSI_CMD_SET_UOR
 
- UCSI_CONCAP_OPMODE_ALT_MODE
 
- UCSI_CONCAP_OPMODE_AUDIO_ACCESSORY
 
- UCSI_CONCAP_OPMODE_DEBUG_ACCESSORY
 
- UCSI_CONCAP_OPMODE_DFP
 
- UCSI_CONCAP_OPMODE_DRP
 
- UCSI_CONCAP_OPMODE_UFP
 
- UCSI_CONCAP_OPMODE_USB2
 
- UCSI_CONCAP_OPMODE_USB3
 
- UCSI_CONNECTOR_RESET
 
- UCSI_CONSTAT_BC_CHANGE
 
- UCSI_CONSTAT_BC_NOMINAL_CHARGING
 
- UCSI_CONSTAT_BC_NOT_CHARGING
 
- UCSI_CONSTAT_BC_SLOW_CHARGING
 
- UCSI_CONSTAT_BC_TRICKLE_CHARGING
 
- UCSI_CONSTAT_CAM_CHANGE
 
- UCSI_CONSTAT_CAP_PWR_BUDGET_LIMIT
 
- UCSI_CONSTAT_CAP_PWR_LOWERED
 
- UCSI_CONSTAT_CONNECT_CHANGE
 
- UCSI_CONSTAT_ERROR
 
- UCSI_CONSTAT_EXT_SUPPLY_CHANGE
 
- UCSI_CONSTAT_PARTNER_CHANGE
 
- UCSI_CONSTAT_PARTNER_FLAG_ALT_MODE
 
- UCSI_CONSTAT_PARTNER_FLAG_USB
 
- UCSI_CONSTAT_PARTNER_TYPE_AUDIO
 
- UCSI_CONSTAT_PARTNER_TYPE_CABLE
 
- UCSI_CONSTAT_PARTNER_TYPE_CABLE_AND_UFP
 
- UCSI_CONSTAT_PARTNER_TYPE_DEBUG
 
- UCSI_CONSTAT_PARTNER_TYPE_DFP
 
- UCSI_CONSTAT_PARTNER_TYPE_UFP
 
- UCSI_CONSTAT_PDOS_CHANGE
 
- UCSI_CONSTAT_PD_RESET_COMPLETE
 
- UCSI_CONSTAT_POWER_DIR_CHANGE
 
- UCSI_CONSTAT_POWER_LEVEL_CHANGE
 
- UCSI_CONSTAT_POWER_OPMODE_CHANGE
 
- UCSI_CONSTAT_PWR_OPMODE_BC
 
- UCSI_CONSTAT_PWR_OPMODE_DEFAULT
 
- UCSI_CONSTAT_PWR_OPMODE_NONE
 
- UCSI_CONSTAT_PWR_OPMODE_PD
 
- UCSI_CONSTAT_PWR_OPMODE_TYPEC1_5
 
- UCSI_CONSTAT_PWR_OPMODE_TYPEC3_0
 
- UCSI_DSM_FUNC_READ
 
- UCSI_DSM_FUNC_WRITE
 
- UCSI_DSM_UUID
 
- UCSI_ENABLE_NTFY_ALL
 
- UCSI_ENABLE_NTFY_BAT_STATUS_CHANGE
 
- UCSI_ENABLE_NTFY_CAM_CHANGE
 
- UCSI_ENABLE_NTFY_CAP_CHANGE
 
- UCSI_ENABLE_NTFY_CMD_COMPLETE
 
- UCSI_ENABLE_NTFY_CONNECTOR_CHANGE
 
- UCSI_ENABLE_NTFY_ERROR
 
- UCSI_ENABLE_NTFY_EXT_PWR_SRC_CHANGE
 
- UCSI_ENABLE_NTFY_PARTNER_CHANGE
 
- UCSI_ENABLE_NTFY_PD_RESET_COMPLETE
 
- UCSI_ENABLE_NTFY_PWR_DIR_CHANGE
 
- UCSI_ENABLE_NTFY_PWR_LEVEL_CHANGE
 
- UCSI_ENABLE_NTFY_PWR_OPMODE_CHANGE
 
- UCSI_ERROR
 
- UCSI_ERROR_CC_COMMUNICATION_ERR
 
- UCSI_ERROR_CONTRACT_NEGOTIATION_FAIL
 
- UCSI_ERROR_DEAD_BATTERY
 
- UCSI_ERROR_INCOMPATIBLE_PARTNER
 
- UCSI_ERROR_INVALID_CMD_ARGUMENT
 
- UCSI_ERROR_INVALID_CON_NUM
 
- UCSI_ERROR_UNREGONIZED_CMD
 
- UCSI_GET_ALTERNATE_MODES
 
- UCSI_GET_CABLE_PROPERTY
 
- UCSI_GET_CAM_SUPPORTED
 
- UCSI_GET_CAPABILITY
 
- UCSI_GET_CONNECTOR_CAPABILITY
 
- UCSI_GET_CONNECTOR_STATUS
 
- UCSI_GET_CURRENT_CAM
 
- UCSI_GET_ERROR_STATUS
 
- UCSI_GET_PDOS
 
- UCSI_IDLE
 
- UCSI_MAX_ALTMODES
 
- UCSI_MAX_SVID
 
- UCSI_PPM_RESET
 
- UCSI_READ_INT
 
- UCSI_RECIPIENT_CON
 
- UCSI_RECIPIENT_SOP
 
- UCSI_RECIPIENT_SOP_P
 
- UCSI_RECIPIENT_SOP_PP
 
- UCSI_SET_NEW_CAM
 
- UCSI_SET_NOTIFICATION_ENABLE
 
- UCSI_SET_PDM
 
- UCSI_SET_PDR
 
- UCSI_SET_UOM
 
- UCSI_SET_UOR
 
- UCSI_SWAP_TIMEOUT_MS
 
- UCSI_TIMEOUT_MS
 
- UCSI_UOR_ROLE_DFP
 
- UCSI_UOR_ROLE_DRP
 
- UCSI_UOR_ROLE_UFP
 
- UCSOLNT
 
- UCSOLNT_RESP_SHIFT
 
- UCTL_HOST_CFG
 
- UCTL_SHIM_CFG
 
- UCTRL_INTR_RXNE_MSK
 
- UCTRL_INTR_RXNE_REQ
 
- UCTRL_INTR_RXO_MSK
 
- UCTRL_INTR_RXO_REQ
 
- UCTRL_INTR_TXE_MSK
 
- UCTRL_INTR_TXE_REQ
 
- UCTRL_INTR_TXNF_MSK
 
- UCTRL_INTR_TXNF_REQ
 
- UCTRL_MINOR
 
- UCTRL_STAT_RXNE_STA
 
- UCTRL_STAT_RXO_STA
 
- UCTRL_STAT_TXE_STA
 
- UCTRL_STAT_TXNF_STA
 
- UCTX
 
- UCTXT_FMT
 
- UCTX_MASK
 
- UC_CHIP_OFFSET
 
- UC_CLEARDEV
 
- UC_DATA_EN
 
- UC_END
 
- UC_FP_XSTATE
 
- UC_FWD_EN
 
- UC_FW_BLOB
 
- UC_GPRS_HIGH
 
- UC_IRQ_CONTROL
 
- UC_LOCAL_LB
 
- UC_OFF
 
- UC_OP
 
- UC_PAR_CLR_D
 
- UC_PAR_CLR_M
 
- UC_RANGE
 
- UC_REGION_ADDR
 
- UC_REGION_SIZE
 
- UC_RESETDEV
 
- UC_SETDEBUG
 
- UC_SETFLAG
 
- UC_SETORDER
 
- UC_SETSYNC
 
- UC_SETTAGS
 
- UC_SETVERBOSE
 
- UC_SETWIDE
 
- UC_SIGCONTEXT_SS
 
- UC_SIZE
 
- UC_STRICT_RESTORE_SS
 
- UC_TODO_RETRY
 
- UC_TODO_RETRY_ON_NEW_PATH
 
- UC_TODO_STOP
 
- UC_UC_CHANNEL_COUNT
 
- UC_UC_CHAN_INCR
 
- UC_UC_INST_OFFSET
 
- UC_UC_MODULE_OFFSET
 
- UC_VXRS
 
- UCreg_00
 
- UCreg_01
 
- UCreg_02
 
- UCreg_03
 
- UCreg_04
 
- UCreg_05
 
- UCreg_06
 
- UCreg_07
 
- UCreg_08
 
- UCreg_09
 
- UCreg_10
 
- UCreg_11
 
- UCreg_12
 
- UCreg_13
 
- UCreg_14
 
- UCreg_15
 
- UCreg_16
 
- UCreg_17
 
- UCreg_18
 
- UCreg_19
 
- UCreg_20
 
- UCreg_21
 
- UCreg_22
 
- UCreg_23
 
- UCreg_24
 
- UCreg_25
 
- UCreg_26
 
- UCreg_ORIG_00
 
- UCreg_asr
 
- UCreg_fp
 
- UCreg_ip
 
- UCreg_lr
 
- UCreg_pc
 
- UCreg_sp
 
- UD
 
- UDA1334_FORMATS
 
- UDA1334_NUM_RATES
 
- UDA1334_RATES
 
- UDA1342_IN1
 
- UDA1342_IN2
 
- UDA134X_DATA000
 
- UDA134X_DATA001
 
- UDA134X_DATA010
 
- UDA134X_DATA011
 
- UDA134X_DATA0_ADDR
 
- UDA134X_DATA1
 
- UDA134X_DATA1_ADDR
 
- UDA134X_EA000
 
- UDA134X_EA001
 
- UDA134X_EA010
 
- UDA134X_EA011
 
- UDA134X_EA100
 
- UDA134X_EA101
 
- UDA134X_EA110
 
- UDA134X_EA111
 
- UDA134X_EXTADDR_PREFIX
 
- UDA134X_EXTDATA_PREFIX
 
- UDA134X_FORMATS
 
- UDA134X_L3ADDR
 
- UDA134X_RATES
 
- UDA134X_STATUS0
 
- UDA134X_STATUS1
 
- UDA134X_STATUS_ADDR
 
- UDA134X_UDA1340
 
- UDA134X_UDA1341
 
- UDA134X_UDA1344
 
- UDA134X_UDA1345
 
- UDA1380_ADC
 
- UDA1380_AGC
 
- UDA1380_AMIX
 
- UDA1380_CACHEREGNUM
 
- UDA1380_CLK
 
- UDA1380_DAC_CLK_SYSCLK
 
- UDA1380_DAC_CLK_WSPLL
 
- UDA1380_DEC
 
- UDA1380_DECSTAT
 
- UDA1380_DEEMP
 
- UDA1380_HP
 
- UDA1380_IFACE
 
- UDA1380_INTSTAT
 
- UDA1380_MIXER
 
- UDA1380_MIXVOL
 
- UDA1380_MODE
 
- UDA1380_MVOL
 
- UDA1380_PGA
 
- UDA1380_PM
 
- UDA1380_RATES
 
- UDA1380_RESET
 
- UDBE_CE
 
- UDBE_E_SYNDR
 
- UDBE_UE
 
- UDBG_BADABORT
 
- UDBG_BUFSIZE
 
- UDBG_BUS
 
- UDBG_SEGV
 
- UDBG_SYSCALL
 
- UDBG_UART_MAPLE_ADDR
 
- UDBG_UART_PAS_ADDR
 
- UDBG_UNDEFINED
 
- UDC
 
- UDCAR_ADD
 
- UDCA_BUFF_SIZE
 
- UDCBCN
 
- UDCBCR0
 
- UDCBCRA
 
- UDCBCRB
 
- UDCBCRC
 
- UDCBCRD
 
- UDCBCRE
 
- UDCBCRF
 
- UDCBCRG
 
- UDCBCRH
 
- UDCBCRI
 
- UDCBCRJ
 
- UDCBCRK
 
- UDCBCRL
 
- UDCBCRM
 
- UDCBCRN
 
- UDCBCRP
 
- UDCBCRQ
 
- UDCBCRR
 
- UDCBCRS
 
- UDCBCRT
 
- UDCBCRU
 
- UDCBCRV
 
- UDCBCRW
 
- UDCBCRX
 
- UDCBCRn
 
- UDCCFR
 
- UDCCFR_ACM
 
- UDCCFR_AREN
 
- UDCCFR_MB1
 
- UDCCISR0_EP_MASK
 
- UDCCISR1_EP_MASK
 
- UDCCN
 
- UDCCONR_AISN
 
- UDCCONR_AISN_S
 
- UDCCONR_CN
 
- UDCCONR_CN_S
 
- UDCCONR_DE
 
- UDCCONR_ED
 
- UDCCONR_EE
 
- UDCCONR_EN
 
- UDCCONR_EN_S
 
- UDCCONR_ET
 
- UDCCONR_ET_BULK
 
- UDCCONR_ET_INT
 
- UDCCONR_ET_ISO
 
- UDCCONR_ET_NU
 
- UDCCONR_ET_S
 
- UDCCONR_IN
 
- UDCCONR_IN_S
 
- UDCCONR_MPS
 
- UDCCONR_MPS_S
 
- UDCCR
 
- UDCCRA
 
- UDCCRB
 
- UDCCRC
 
- UDCCRD
 
- UDCCRE
 
- UDCCRF
 
- UDCCRG
 
- UDCCRH
 
- UDCCRI
 
- UDCCRJ
 
- UDCCRK
 
- UDCCRL
 
- UDCCRM
 
- UDCCRN
 
- UDCCRP
 
- UDCCRQ
 
- UDCCRR
 
- UDCCRS
 
- UDCCRT
 
- UDCCRU
 
- UDCCRV
 
- UDCCRW
 
- UDCCRX
 
- UDCCR_AAISN
 
- UDCCR_AAISN_S
 
- UDCCR_AALTHNP
 
- UDCCR_ACN
 
- UDCCR_ACN_S
 
- UDCCR_AHNP
 
- UDCCR_AIN
 
- UDCCR_AIN_S
 
- UDCCR_BHNP
 
- UDCCR_DWRE
 
- UDCCR_EIM
 
- UDCCR_EMCE
 
- UDCCR_MASK_BITS
 
- UDCCR_OEN
 
- UDCCR_REM
 
- UDCCR_RESIM
 
- UDCCR_RESIR
 
- UDCCR_RIM
 
- UDCCR_RSM
 
- UDCCR_RSTIR
 
- UDCCR_SMAC
 
- UDCCR_SRM
 
- UDCCR_SUSIM
 
- UDCCR_SUSIR
 
- UDCCR_TIM
 
- UDCCR_UDA
 
- UDCCR_UDD
 
- UDCCR_UDE
 
- UDCCR_UDR
 
- UDCCRn
 
- UDCCS0
 
- UDCCS0_DE
 
- UDCCS0_DRWF
 
- UDCCS0_FST
 
- UDCCS0_FTF
 
- UDCCS0_IPR
 
- UDCCS0_OPR
 
- UDCCS0_RNE
 
- UDCCS0_SA
 
- UDCCS0_SE
 
- UDCCS0_SO
 
- UDCCS0_SSE
 
- UDCCS0_SST
 
- UDCCS1
 
- UDCCS10
 
- UDCCS11
 
- UDCCS12
 
- UDCCS13
 
- UDCCS14
 
- UDCCS15
 
- UDCCS1_FST
 
- UDCCS1_RFS
 
- UDCCS1_RNE
 
- UDCCS1_RPC
 
- UDCCS1_RPE
 
- UDCCS1_SST
 
- UDCCS2
 
- UDCCS2_FST
 
- UDCCS2_SST
 
- UDCCS2_TFS
 
- UDCCS2_TPC
 
- UDCCS2_TPE
 
- UDCCS2_TUR
 
- UDCCS3
 
- UDCCS4
 
- UDCCS5
 
- UDCCS6
 
- UDCCS7
 
- UDCCS8
 
- UDCCS9
 
- UDCCSN
 
- UDCCSR0
 
- UDCCSR0_ACM
 
- UDCCSR0_AREN
 
- UDCCSR0_CTRL_REQ_MASK
 
- UDCCSR0_DME
 
- UDCCSR0_FST
 
- UDCCSR0_FTF
 
- UDCCSR0_IPR
 
- UDCCSR0_OPC
 
- UDCCSR0_RNE
 
- UDCCSR0_SA
 
- UDCCSR0_SST
 
- UDCCSRA
 
- UDCCSRB
 
- UDCCSRC
 
- UDCCSRD
 
- UDCCSRE
 
- UDCCSRF
 
- UDCCSRG
 
- UDCCSRH
 
- UDCCSRI
 
- UDCCSRJ
 
- UDCCSRK
 
- UDCCSRL
 
- UDCCSRM
 
- UDCCSRN
 
- UDCCSRP
 
- UDCCSRQ
 
- UDCCSRR
 
- UDCCSRS
 
- UDCCSRT
 
- UDCCSRU
 
- UDCCSRV
 
- UDCCSRW
 
- UDCCSRX
 
- UDCCSR_BNE
 
- UDCCSR_BNF
 
- UDCCSR_DME
 
- UDCCSR_DPE
 
- UDCCSR_FEF
 
- UDCCSR_FS
 
- UDCCSR_FST
 
- UDCCSR_MASK
 
- UDCCSR_PC
 
- UDCCSR_SP
 
- UDCCSR_SST
 
- UDCCSR_TRN
 
- UDCCSR_WR_MASK
 
- UDCCSRn
 
- UDCCS_BI_FST
 
- UDCCS_BI_FTF
 
- UDCCS_BI_SST
 
- UDCCS_BI_TFS
 
- UDCCS_BI_TPC
 
- UDCCS_BI_TSP
 
- UDCCS_BI_TUR
 
- UDCCS_BO_DME
 
- UDCCS_BO_FST
 
- UDCCS_BO_RFS
 
- UDCCS_BO_RNE
 
- UDCCS_BO_RPC
 
- UDCCS_BO_RSP
 
- UDCCS_BO_SST
 
- UDCCS_II_FTF
 
- UDCCS_II_TFS
 
- UDCCS_II_TPC
 
- UDCCS_II_TSP
 
- UDCCS_II_TUR
 
- UDCCS_INT_FST
 
- UDCCS_INT_FTF
 
- UDCCS_INT_SST
 
- UDCCS_INT_TFS
 
- UDCCS_INT_TPC
 
- UDCCS_INT_TSP
 
- UDCCS_INT_TUR
 
- UDCCS_IO_DME
 
- UDCCS_IO_RFS
 
- UDCCS_IO_RNE
 
- UDCCS_IO_ROF
 
- UDCCS_IO_RPC
 
- UDCCS_IO_RSP
 
- UDCD0_DATA
 
- UDCDBG
 
- UDCDN
 
- UDCDR0
 
- UDCDRA
 
- UDCDRB
 
- UDCDRC
 
- UDCDRD
 
- UDCDRE
 
- UDCDRF
 
- UDCDRG
 
- UDCDRH
 
- UDCDRI
 
- UDCDRJ
 
- UDCDRK
 
- UDCDRL
 
- UDCDRM
 
- UDCDRN
 
- UDCDRP
 
- UDCDRQ
 
- UDCDRR
 
- UDCDRS
 
- UDCDRT
 
- UDCDRU
 
- UDCDRV
 
- UDCDRW
 
- UDCDRX
 
- UDCDR_DATA
 
- UDCDRn
 
- UDCFNR
 
- UDCICR0
 
- UDCICR1
 
- UDCICR1_IECC
 
- UDCICR1_IERS
 
- UDCICR1_IERU
 
- UDCICR1_IESOF
 
- UDCICR1_IESU
 
- UDCICR_FIFOERR
 
- UDCICR_INT
 
- UDCICR_INT_MASK
 
- UDCICR_PKTCOMPL
 
- UDCIMP_INMAXP
 
- UDCIMP_InMaxPkt
 
- UDCISR0
 
- UDCISR1
 
- UDCISR1_IRCC
 
- UDCISR1_IRRS
 
- UDCISR1_IRRU
 
- UDCISR1_IRSOF
 
- UDCISR1_IRSU
 
- UDCISR_INT
 
- UDCISR_INT_MASK
 
- UDCOMP_OUTMAXP
 
- UDCOMP_OutMaxPkt
 
- UDCOTGICR
 
- UDCOTGICR_IEIDF
 
- UDCOTGICR_IEIDR
 
- UDCOTGICR_IESDF
 
- UDCOTGICR_IESDR
 
- UDCOTGICR_IESF
 
- UDCOTGICR_IESVF
 
- UDCOTGICR_IESVR
 
- UDCOTGICR_IEVV40F
 
- UDCOTGICR_IEVV40R
 
- UDCOTGICR_IEVV44F
 
- UDCOTGICR_IEVV44R
 
- UDCOTGICR_IEXF
 
- UDCOTGICR_IEXR
 
- UDCSR_EIR
 
- UDCSR_RESIR
 
- UDCSR_RIR
 
- UDCSR_RSTIR
 
- UDCSR_SUSIR
 
- UDCSR_TIR
 
- UDCVDBG
 
- UDCWC_WC
 
- UDC_ACK
 
- UDC_ADD
 
- UDC_ATT
 
- UDC_AUTODECODE_DIS
 
- UDC_A_ALT_HNP_SUPPORT
 
- UDC_A_HNP_SUPPORT
 
- UDC_BASE
 
- UDC_BCM_REV
 
- UDC_BCR_MASK
 
- UDC_BITS_PER_BYTE
 
- UDC_BITS_PER_BYTE_SHIFT
 
- UDC_BUFIN_FRAMENUM_ADDR
 
- UDC_BUFOUT_MAXPKT_ADDR
 
- UDC_BULK_MAX_PKT_SIZE
 
- UDC_BYTE_MASK
 
- UDC_B_HNP_ENABLE
 
- UDC_CFG
 
- UDC_CFG_LOCK
 
- UDC_CHN_HI
 
- UDC_CHN_LO
 
- UDC_CHN_START
 
- UDC_CLRDATA_TOGGLE
 
- UDC_CLR_CFG
 
- UDC_CLR_EP
 
- UDC_CLR_HALT
 
- UDC_CONFIRM_ADDR
 
- UDC_COUNT
 
- UDC_CSR
 
- UDC_CSR_ADDR
 
- UDC_CSR_BUSY
 
- UDC_CSR_BUSY_ADDR
 
- UDC_CSR_EP_OUT_IX_OFS
 
- UDC_CSR_NE_ALT_MASK
 
- UDC_CSR_NE_ALT_OFS
 
- UDC_CSR_NE_ALT_SHIFT
 
- UDC_CSR_NE_CFG_MASK
 
- UDC_CSR_NE_CFG_OFS
 
- UDC_CSR_NE_CFG_SHIFT
 
- UDC_CSR_NE_DIR_MASK
 
- UDC_CSR_NE_DIR_OFS
 
- UDC_CSR_NE_DIR_SHIFT
 
- UDC_CSR_NE_INTF_MASK
 
- UDC_CSR_NE_INTF_OFS
 
- UDC_CSR_NE_INTF_SHIFT
 
- UDC_CSR_NE_MAX_PKT_MASK
 
- UDC_CSR_NE_MAX_PKT_OFS
 
- UDC_CSR_NE_MAX_PKT_SHIFT
 
- UDC_CSR_NE_NUM_MASK
 
- UDC_CSR_NE_NUM_OFS
 
- UDC_CSR_NE_NUM_SHIFT
 
- UDC_CSR_NE_TYPE_MASK
 
- UDC_CSR_NE_TYPE_OFS
 
- UDC_CSR_NE_TYPE_SHIFT
 
- UDC_CTRL
 
- UDC_CURA_HI
 
- UDC_CURA_LO
 
- UDC_CURB_HI
 
- UDC_CURB_LO
 
- UDC_DATA
 
- UDC_DATA_DMA
 
- UDC_DATA_ENDIAN
 
- UDC_DATA_FLUSH
 
- UDC_DEBUG
 
- UDC_DEBUG_DUMP
 
- UDC_DEF
 
- UDC_DESPTR_ADDR
 
- UDC_DEVCFG_ADDR
 
- UDC_DEVCFG_CSR_PRG
 
- UDC_DEVCFG_DIR
 
- UDC_DEVCFG_DMARST
 
- UDC_DEVCFG_HNPSFEN
 
- UDC_DEVCFG_PI
 
- UDC_DEVCFG_RWKP
 
- UDC_DEVCFG_SET_DESC
 
- UDC_DEVCFG_SOFTRESET
 
- UDC_DEVCFG_SP
 
- UDC_DEVCFG_SPD_FS
 
- UDC_DEVCFG_SPD_HS
 
- UDC_DEVCFG_SPD_LS
 
- UDC_DEVCFG_SPD_MASK
 
- UDC_DEVCFG_SPD_OFS
 
- UDC_DEVCFG_SS
 
- UDC_DEVCFG_STATUS
 
- UDC_DEVCTL_ADDR
 
- UDC_DEVCTL_BE
 
- UDC_DEVCTL_BF
 
- UDC_DEVCTL_BREN
 
- UDC_DEVCTL_BRLEN_MASK
 
- UDC_DEVCTL_BRLEN_OFS
 
- UDC_DEVCTL_BRLEN_SHIFT
 
- UDC_DEVCTL_CSR_DONE
 
- UDC_DEVCTL_DEVNAK
 
- UDC_DEVCTL_DU
 
- UDC_DEVCTL_MODE
 
- UDC_DEVCTL_RDE
 
- UDC_DEVCTL_RES
 
- UDC_DEVCTL_SD
 
- UDC_DEVCTL_SRX_FLUSH
 
- UDC_DEVCTL_TDE
 
- UDC_DEVCTL_THE
 
- UDC_DEVCTL_THLEN_MASK
 
- UDC_DEVCTL_THLEN_OFS
 
- UDC_DEVCTL_THLEN_SHIFT
 
- UDC_DEVINT_ADDR
 
- UDC_DEVINT_ENUM
 
- UDC_DEVINT_ES
 
- UDC_DEVINT_MSK
 
- UDC_DEVINT_MSK_ADDR
 
- UDC_DEVINT_RWKP
 
- UDC_DEVINT_SC
 
- UDC_DEVINT_SI
 
- UDC_DEVINT_SOF
 
- UDC_DEVINT_SVC
 
- UDC_DEVINT_UR
 
- UDC_DEVINT_US
 
- UDC_DEVIRQMSK_ADDR
 
- UDC_DEVIRQSTS_ADDR
 
- UDC_DEVLPM_ADDR
 
- UDC_DEVSTAT
 
- UDC_DEVSTS_ADDR
 
- UDC_DEVSTS_ALT_MASK
 
- UDC_DEVSTS_ALT_OFS
 
- UDC_DEVSTS_ALT_SHIFT
 
- UDC_DEVSTS_CFG_MASK
 
- UDC_DEVSTS_CFG_OFS
 
- UDC_DEVSTS_CFG_SHIFT
 
- UDC_DEVSTS_ENUM_SPEED_FULL
 
- UDC_DEVSTS_ENUM_SPEED_FULLX
 
- UDC_DEVSTS_ENUM_SPEED_HIGH
 
- UDC_DEVSTS_ENUM_SPEED_LOW
 
- UDC_DEVSTS_ENUM_SPEED_MASK
 
- UDC_DEVSTS_ENUM_SPEED_OFS
 
- UDC_DEVSTS_ENUM_SPEED_SHIFT
 
- UDC_DEVSTS_INTF_MASK
 
- UDC_DEVSTS_INTF_OFS
 
- UDC_DEVSTS_INTF_SHIFT
 
- UDC_DEVSTS_PHY_ERROR
 
- UDC_DEVSTS_RXFIFO_EMPTY
 
- UDC_DEVSTS_SESSVLD
 
- UDC_DEVSTS_SUSP
 
- UDC_DEVSTS_TS_MASK
 
- UDC_DEVSTS_TS_OFS
 
- UDC_DEVSTS_TS_SHIFT
 
- UDC_DEV_CFG
 
- UDC_DEV_MSK_DISABLE
 
- UDC_DMAN_STAT
 
- UDC_DMA_BOUNDARY
 
- UDC_DMA_ENDIAN
 
- UDC_DMA_IN_STS_BS_DMA_BUSY
 
- UDC_DMA_IN_STS_BS_DMA_DONE
 
- UDC_DMA_IN_STS_BS_HOST_BUSY
 
- UDC_DMA_IN_STS_BS_HOST_READY
 
- UDC_DMA_IN_STS_BS_MASK
 
- UDC_DMA_IN_STS_BS_OFS
 
- UDC_DMA_IN_STS_FRAMENUM_MASK
 
- UDC_DMA_IN_STS_FRAMENUM_OFS
 
- UDC_DMA_IN_STS_L
 
- UDC_DMA_IN_STS_TXBYTES_MASK
 
- UDC_DMA_IN_STS_TXBYTES_OFS
 
- UDC_DMA_IN_STS_TX_MASK
 
- UDC_DMA_IN_STS_TX_OFS
 
- UDC_DMA_IRQ_EN
 
- UDC_DMA_MAXPACKET
 
- UDC_DMA_OUT_STS_BS_DMA_BUSY
 
- UDC_DMA_OUT_STS_BS_DMA_DONE
 
- UDC_DMA_OUT_STS_BS_HOST_BUSY
 
- UDC_DMA_OUT_STS_BS_HOST_READY
 
- UDC_DMA_OUT_STS_BS_MASK
 
- UDC_DMA_OUT_STS_BS_OFS
 
- UDC_DMA_OUT_STS_FRAMENUM_MASK
 
- UDC_DMA_OUT_STS_FRAMENUM_OFS
 
- UDC_DMA_OUT_STS_L
 
- UDC_DMA_OUT_STS_RXBYTES_MASK
 
- UDC_DMA_OUT_STS_RXBYTES_OFS
 
- UDC_DMA_OUT_STS_RX_MASK
 
- UDC_DMA_OUT_STS_RX_OFS
 
- UDC_DMA_REQ
 
- UDC_DMA_RX_SB
 
- UDC_DMA_RX_SRC
 
- UDC_DMA_STP_STS_BS_DMA_BUSY
 
- UDC_DMA_STP_STS_BS_DMA_DONE
 
- UDC_DMA_STP_STS_BS_HOST_BUSY
 
- UDC_DMA_STP_STS_BS_HOST_READY
 
- UDC_DMA_STP_STS_BS_MASK
 
- UDC_DMA_STP_STS_BS_OFS
 
- UDC_DMA_STP_STS_CFG_ALT_MASK
 
- UDC_DMA_STP_STS_CFG_ALT_OFS
 
- UDC_DMA_STP_STS_CFG_INTF_MASK
 
- UDC_DMA_STP_STS_CFG_INTF_OFS
 
- UDC_DMA_STP_STS_CFG_MASK
 
- UDC_DMA_STP_STS_CFG_NUM_MASK
 
- UDC_DMA_STP_STS_CFG_NUM_OFS
 
- UDC_DMA_STP_STS_CFG_OFS
 
- UDC_DMA_STP_STS_RX_MASK
 
- UDC_DMA_STP_STS_RX_OFS
 
- UDC_DMA_TX_SRC
 
- UDC_DRIVER_NAME
 
- UDC_DRIVER_VERSION_STRING
 
- UDC_DS_CHG
 
- UDC_DS_CHG_IE
 
- UDC_DWORD_BYTES
 
- UDC_EP0IN_BUFF_SIZE
 
- UDC_EP0IN_IDX
 
- UDC_EP0IN_IX
 
- UDC_EP0IN_MAXPACKET
 
- UDC_EP0IN_MAX_PKT_SIZE
 
- UDC_EP0OUT_BUFF_SIZE
 
- UDC_EP0OUT_IDX
 
- UDC_EP0OUT_IX
 
- UDC_EP0OUT_MAX_PKT_SIZE
 
- UDC_EP0_IE
 
- UDC_EP0_RX
 
- UDC_EP0_TX
 
- UDC_EPCTL_ADDR
 
- UDC_EPCTL_CNAK
 
- UDC_EPCTL_ET_BULK
 
- UDC_EPCTL_ET_CONTROL
 
- UDC_EPCTL_ET_INTERRUPT
 
- UDC_EPCTL_ET_ISO
 
- UDC_EPCTL_ET_MASK
 
- UDC_EPCTL_ET_OFS
 
- UDC_EPCTL_ET_SHIFT
 
- UDC_EPCTL_F
 
- UDC_EPCTL_MRXFLUSH
 
- UDC_EPCTL_NAK
 
- UDC_EPCTL_P
 
- UDC_EPCTL_RRDY
 
- UDC_EPCTL_S
 
- UDC_EPCTL_SN
 
- UDC_EPCTL_SNAK
 
- UDC_EPDATAINT_MSK_DISABLE
 
- UDC_EPIN0_BUFF_SIZE
 
- UDC_EPINT_ADDR
 
- UDC_EPINT_EP0_ENABLE_MSK
 
- UDC_EPINT_IN_EP0
 
- UDC_EPINT_IN_EP1
 
- UDC_EPINT_IN_EP2
 
- UDC_EPINT_IN_EP3
 
- UDC_EPINT_IN_MASK
 
- UDC_EPINT_IN_MSK_MASK
 
- UDC_EPINT_IN_MSK_OFS
 
- UDC_EPINT_IN_OFS
 
- UDC_EPINT_IN_SHIFT
 
- UDC_EPINT_MSK_ADDR
 
- UDC_EPINT_MSK_DISABLE_ALL
 
- UDC_EPINT_OUT_EP0
 
- UDC_EPINT_OUT_EP1
 
- UDC_EPINT_OUT_EP2
 
- UDC_EPINT_OUT_EP3
 
- UDC_EPINT_OUT_MASK
 
- UDC_EPINT_OUT_MSK_MASK
 
- UDC_EPINT_OUT_MSK_OFS
 
- UDC_EPINT_OUT_OFS
 
- UDC_EPINT_OUT_SHIFT
 
- UDC_EPIN_BUFF_SIZE
 
- UDC_EPIN_BUFF_SIZE_ADDR
 
- UDC_EPIN_BUFF_SIZE_MASK
 
- UDC_EPIN_BUFF_SIZE_MULT
 
- UDC_EPIN_BUFF_SIZE_OFS
 
- UDC_EPIN_IDX
 
- UDC_EPIN_IX
 
- UDC_EPIN_NUM
 
- UDC_EPIN_NUM_USED
 
- UDC_EPIN_REGS_ADDR
 
- UDC_EPIN_SMALLINT_BUFF_SIZE
 
- UDC_EPIN_STATUS_IX
 
- UDC_EPIRQMSK_ADDR
 
- UDC_EPIRQSTS_ADDR
 
- UDC_EPN_RX
 
- UDC_EPN_RX_DB
 
- UDC_EPN_RX_IE
 
- UDC_EPN_RX_ISO
 
- UDC_EPN_RX_VALID
 
- UDC_EPN_STAT
 
- UDC_EPN_TX
 
- UDC_EPN_TX_IE
 
- UDC_EPOUT_BUFF_SIZE
 
- UDC_EPOUT_BUFF_SIZE_ADDR
 
- UDC_EPOUT_BUFF_SIZE_MASK
 
- UDC_EPOUT_BUFF_SIZE_OFS
 
- UDC_EPOUT_FRAME_NUMBER_ADDR
 
- UDC_EPOUT_FRAME_NUMBER_MASK
 
- UDC_EPOUT_FRAME_NUMBER_OFS
 
- UDC_EPOUT_IDX
 
- UDC_EPOUT_IX
 
- UDC_EPOUT_NUM
 
- UDC_EPOUT_REGS_ADDR
 
- UDC_EPREGS_ADDR
 
- UDC_EPSTS_ADDR
 
- UDC_EPSTS_ALL_CLR_MASK
 
- UDC_EPSTS_BNA
 
- UDC_EPSTS_HE
 
- UDC_EPSTS_IN
 
- UDC_EPSTS_MRXFIFO_EMP
 
- UDC_EPSTS_OUT_CLEAR
 
- UDC_EPSTS_OUT_DATA
 
- UDC_EPSTS_OUT_DATA_CLEAR
 
- UDC_EPSTS_OUT_MASK
 
- UDC_EPSTS_OUT_OFS
 
- UDC_EPSTS_OUT_SETUP
 
- UDC_EPSTS_OUT_SETUP_CLEAR
 
- UDC_EPSTS_OUT_SHIFT
 
- UDC_EPSTS_RCS
 
- UDC_EPSTS_RSS
 
- UDC_EPSTS_RX_PKT_SIZE_MASK
 
- UDC_EPSTS_RX_PKT_SIZE_OFS
 
- UDC_EPSTS_TDC
 
- UDC_EPSTS_TXEMPTY
 
- UDC_EPSTS_XFERDONE
 
- UDC_EP_DESPTR_ADDR
 
- UDC_EP_DIR
 
- UDC_EP_HALTED
 
- UDC_EP_MAX_PKT_SIZE_ADDR
 
- UDC_EP_MAX_PKT_SIZE_MASK
 
- UDC_EP_MAX_PKT_SIZE_OFS
 
- UDC_EP_NUM
 
- UDC_EP_REG_SHIFT
 
- UDC_EP_RX
 
- UDC_EP_SEL
 
- UDC_EP_SUBPTR_ADDR
 
- UDC_EP_TX
 
- UDC_EP_WRITE_CONFIRM_ADDR
 
- UDC_FIFO_EN
 
- UDC_FIFO_FULL
 
- UDC_FIFO_UNWRITABLE
 
- UDC_FNR_MASK
 
- UDC_FS_EP0IN_MAX_PKT_SIZE
 
- UDC_FS_EP0OUT_MAX_PKT_SIZE
 
- UDC_FS_EPIN0_BUFF_SIZE
 
- UDC_FS_EPIN_BUFF_SIZE
 
- UDC_FT_LOCK
 
- UDC_HSA0_REV
 
- UDC_HSB1_REV
 
- UDC_INT_ENABLE
 
- UDC_INT_FIFOERROR
 
- UDC_INT_PACKETCMP
 
- UDC_IRQ_EN
 
- UDC_IRQ_SOF
 
- UDC_IRQ_SRC
 
- UDC_IRQ_SRC_MASK
 
- UDC_ISO_ERR
 
- UDC_ISO_FIFO_EMPTY
 
- UDC_ISO_FIFO_FULL
 
- UDC_MISS_IN
 
- UDC_MODE
 
- UDC_MODE_HI
 
- UDC_MODE_HIWORD
 
- UDC_MODE_LO
 
- UDC_MODE_LRECV
 
- UDC_MODE_LSEND
 
- UDC_MOD_DESCRIPTION
 
- UDC_MSCRES_DWORD0
 
- UDC_MSCRES_DWORD1
 
- UDC_MSTRD_ENDPOINT
 
- UDC_MSTWR_ENDPOINT
 
- UDC_NAK
 
- UDC_NAK_EN
 
- UDC_NON_ISO_FIFO_EMPTY
 
- UDC_NON_ISO_FIFO_FULL
 
- UDC_NO_RXPACKET
 
- UDC_POLLSTALL_TIMER_USECONDS
 
- UDC_PSRST
 
- UDC_PULLUP_EN
 
- UDC_QUEUE_CNAK
 
- UDC_RDE_TIMER_DIV
 
- UDC_RDE_TIMER_SECONDS
 
- UDC_RES1
 
- UDC_RES2
 
- UDC_RES3
 
- UDC_RESET
 
- UDC_RESET_EP
 
- UDC_REV
 
- UDC_RMT_WKP
 
- UDC_RSEL_RECV
 
- UDC_RSEL_SEND
 
- UDC_RXDMA
 
- UDC_RXDMA_CFG
 
- UDC_RXFIFO_ADDR
 
- UDC_RXFIFO_SIZE
 
- UDC_RXFSTAT
 
- UDC_RXN_CNT
 
- UDC_RXN_EOT
 
- UDC_RXN_STOP
 
- UDC_RXN_TC
 
- UDC_RX_CNT_IE
 
- UDC_RX_EOT_IE
 
- UDC_R_WK_OK
 
- UDC_SELF_PWR
 
- UDC_SETCONFIG_DWORD0
 
- UDC_SETCONFIG_DWORD0_VALUE_MASK
 
- UDC_SETCONFIG_DWORD0_VALUE_OFS
 
- UDC_SETCONFIG_DWORD1
 
- UDC_SETINTF_DWORD0
 
- UDC_SETINTF_DWORD0_ALT_MASK
 
- UDC_SETINTF_DWORD0_ALT_OFS
 
- UDC_SETINTF_DWORD1
 
- UDC_SETINTF_DWORD1_INTF_MASK
 
- UDC_SETINTF_DWORD1_INTF_OFS
 
- UDC_SETUP
 
- UDC_SETUP_SEL
 
- UDC_SET_FIFO_EN
 
- UDC_SET_HALT
 
- UDC_SOF
 
- UDC_SOFF_DIS
 
- UDC_SOF_IE
 
- UDC_SRST
 
- UDC_SRST_ADDR
 
- UDC_STALL
 
- UDC_STALL_CMD
 
- UDC_STAT_FLG
 
- UDC_SUBPTR_ADDR
 
- UDC_SUS
 
- UDC_SYSCON1
 
- UDC_SYSCON2
 
- UDC_TRACE_STR_MAX
 
- UDC_TS
 
- UDC_TS_OK
 
- UDC_TXDMA
 
- UDC_TXDMA_CFG
 
- UDC_TXFIFO_ADDR
 
- UDC_TXFIFO_SIZE
 
- UDC_TXN_DONE
 
- UDC_TXN_EOT
 
- UDC_TXN_START
 
- UDC_TXN_TSC
 
- UDC_TX_DONE_IE
 
- UDC_USB_RESET
 
- UDC_USED_EP_NUM
 
- UDDR0
 
- UDDR1
 
- UDDR10
 
- UDDR11
 
- UDDR12
 
- UDDR13
 
- UDDR14
 
- UDDR15
 
- UDDR2
 
- UDDR3
 
- UDDR4
 
- UDDR5
 
- UDDR6
 
- UDDR7
 
- UDDR8
 
- UDDR9
 
- UDELAY
 
- UDELAY_10MS_DEFAULT
 
- UDELAY_COUNT
 
- UDELAY_DELAY
 
- UDELAY_MULT
 
- UDELAY_SHIFT
 
- UDEV_WAKEUP
 
- UDE_BASE
 
- UDE_CC0
 
- UDE_CC1
 
- UDE_CFG
 
- UDE_CFG_CDEN_ENABLE
 
- UDE_CFG_DST16
 
- UDE_CFG_DST24
 
- UDE_CFG_DST32
 
- UDE_CFG_DST8
 
- UDE_CFG_DST_MASK
 
- UDE_CFG_GDEN_ENABLE
 
- UDE_CFG_TIMEUP_ENABLE
 
- UDE_CFG_VDEN_ENABLE
 
- UDE_CXY
 
- UDE_FSA
 
- UDE_HAT
 
- UDE_HBT
 
- UDE_HST
 
- UDE_LS
 
- UDE_PS
 
- UDE_VAT
 
- UDE_VBT
 
- UDE_VS
 
- UDE_VSA
 
- UDE_VST
 
- UDE_VXY
 
- UDF
 
- UDFIdentSuffix
 
- UDFS_PER_SLICE
 
- UDF_CHAR_SET_INFO
 
- UDF_CHAR_SET_TYPE
 
- UDF_CLEAR_FLAG
 
- UDF_DEFAULT_PREALLOC_BLOCKS
 
- UDF_EXTENT_FLAG_MASK
 
- UDF_EXTENT_LENGTH_MASK
 
- UDF_FLAG_BLOCKSIZE_SET
 
- UDF_FLAG_GID_FORGET
 
- UDF_FLAG_GID_SET
 
- UDF_FLAG_INCONSISTENT
 
- UDF_FLAG_LASTBLOCK_SET
 
- UDF_FLAG_NLS_MAP
 
- UDF_FLAG_RW_INCOMPAT
 
- UDF_FLAG_SESSION_SET
 
- UDF_FLAG_STRICT
 
- UDF_FLAG_UID_FORGET
 
- UDF_FLAG_UID_SET
 
- UDF_FLAG_UNDELETE
 
- UDF_FLAG_UNHIDE
 
- UDF_FLAG_USE_AD_IN_ICB
 
- UDF_FLAG_USE_EXTENDED_FE
 
- UDF_FLAG_USE_FILE_CTIME_EA
 
- UDF_FLAG_USE_SHORT_AD
 
- UDF_FLAG_USE_STREAMS
 
- UDF_FLAG_UTF8
 
- UDF_FLAG_VARCONV
 
- UDF_GETEABLOCK
 
- UDF_GETEASIZE
 
- UDF_GETVOLIDENT
 
- UDF_I
 
- UDF_ID_ALLOC
 
- UDF_ID_BACKUP
 
- UDF_ID_COMPLIANT
 
- UDF_ID_DEVELOPER
 
- UDF_ID_DVD_CGMS
 
- UDF_ID_FREE_APP_EA
 
- UDF_ID_FREE_EA
 
- UDF_ID_LV_INFO
 
- UDF_ID_MAC_FINDER
 
- UDF_ID_MAC_RESOURCE
 
- UDF_ID_MAC_UNIQUE
 
- UDF_ID_MAC_VOLUME
 
- UDF_ID_METADATA
 
- UDF_ID_NON_ALLOC
 
- UDF_ID_OS2_EA
 
- UDF_ID_OS2_EA_LENGTH
 
- UDF_ID_POWER_CAL
 
- UDF_ID_SPARABLE
 
- UDF_ID_SPARING
 
- UDF_ID_UNIQUE_ID
 
- UDF_ID_VIRTUAL
 
- UDF_INVALID_ID
 
- UDF_INVALID_MODE
 
- UDF_MAX_BLOCK_LOADED
 
- UDF_MAX_ICB_NESTING
 
- UDF_MAX_INDIR_EXTS
 
- UDF_MAX_LINKS
 
- UDF_MAX_LVID_NESTING
 
- UDF_MAX_READ_VERSION
 
- UDF_MAX_TD_NESTING
 
- UDF_MAX_WRITE_VERSION
 
- UDF_METADATA_MAP25
 
- UDF_NAME_LEN
 
- UDF_NAME_LEN_CS0
 
- UDF_NAME_PAD
 
- UDF_NUM_SLICES
 
- UDF_OS_CLASS_BEOS
 
- UDF_OS_CLASS_DOS
 
- UDF_OS_CLASS_MAC
 
- UDF_OS_CLASS_OS2
 
- UDF_OS_CLASS_OS400
 
- UDF_OS_CLASS_UNDEF
 
- UDF_OS_CLASS_UNIX
 
- UDF_OS_CLASS_WIN9X
 
- UDF_OS_CLASS_WINCE
 
- UDF_OS_CLASS_WINNT
 
- UDF_OS_ID_AIX
 
- UDF_OS_ID_BEOS
 
- UDF_OS_ID_DOS
 
- UDF_OS_ID_FREEBSD
 
- UDF_OS_ID_HPUX
 
- UDF_OS_ID_IRIX
 
- UDF_OS_ID_LINUX
 
- UDF_OS_ID_MAC
 
- UDF_OS_ID_MAX_OSX
 
- UDF_OS_ID_MKLINUX
 
- UDF_OS_ID_OS2
 
- UDF_OS_ID_OS400
 
- UDF_OS_ID_SOLARIS
 
- UDF_OS_ID_UNDEF
 
- UDF_OS_ID_UNIX
 
- UDF_OS_ID_WIN9X
 
- UDF_OS_ID_WINCE
 
- UDF_OS_ID_WINNT
 
- UDF_PART_FLAG_OVERWRITABLE
 
- UDF_PART_FLAG_READ_ONLY
 
- UDF_PART_FLAG_REWRITABLE
 
- UDF_PART_FLAG_UNALLOC_BITMAP
 
- UDF_PART_FLAG_UNALLOC_TABLE
 
- UDF_PART_FLAG_WRITE_ONCE
 
- UDF_QUERY_FLAG
 
- UDF_RELOCATE_BLOCKS
 
- UDF_SB
 
- UDF_SET_FLAG
 
- UDF_SLICE_OFFSET
 
- UDF_SPARABLE_MAP15
 
- UDF_SUPER_MAGIC
 
- UDF_TYPE1_MAP15
 
- UDF_VERS_USE_EXTENDED_FE
 
- UDF_VERS_USE_STREAMS
 
- UDF_VIRTUAL_MAP15
 
- UDF_VIRTUAL_MAP20
 
- UDIAG_SHOW_ICONS
 
- UDIAG_SHOW_MEMINFO
 
- UDIAG_SHOW_NAME
 
- UDIAG_SHOW_PEER
 
- UDIAG_SHOW_RQLEN
 
- UDIAG_SHOW_UID
 
- UDIAG_SHOW_VFS
 
- UDIDETCR0
 
- UDIDETCR1
 
- UDIVX
 
- UDIV_NEEDS_NORMALIZATION
 
- UDIV_TIME
 
- UDItype
 
- UDLFB_H
 
- UDL_BO_CACHEABLE
 
- UDL_BO_WC
 
- UDL_DRV_H
 
- UDM
 
- UDMABUF_CREATE
 
- UDMABUF_CREATE_LIST
 
- UDMABUF_FLAGS_CLOEXEC
 
- UDMA_OFF
 
- UDP
 
- UDP6_INC_STATS
 
- UDPCS
 
- UDPCheckSumErrors
 
- UDPChecksumEnable
 
- UDPChksumErr
 
- UDPChksumValid
 
- UDPDetected
 
- UDPENABLE_F
 
- UDPENABLE_S
 
- UDPENABLE_V
 
- UDPError
 
- UDPF
 
- UDPFOURTUPEN_F
 
- UDPFOURTUPEN_S
 
- UDPFOURTUPEN_V
 
- UDPFail
 
- UDPHDR_LEN
 
- UDPLITE_BIT
 
- UDPLITE_RECV_CC
 
- UDPLITE_RECV_CSCOV
 
- UDPLITE_SEND_CC
 
- UDPLITE_SEND_CSCOV
 
- UDPON
 
- UDPTCP
 
- UDP_APP_TAB_BITS
 
- UDP_APP_TAB_MASK
 
- UDP_APP_TAB_SIZE
 
- UDP_CORK
 
- UDP_CS
 
- UDP_CSUM_OFF
 
- UDP_CT_MAX
 
- UDP_CT_REPLIED
 
- UDP_CT_UNREPLIED
 
- UDP_DATA_OFFSET
 
- UDP_DPORT
 
- UDP_ENCAP
 
- UDP_ENCAP_ESPINUDP
 
- UDP_ENCAP_ESPINUDP_NON_IKE
 
- UDP_ENCAP_GTP0
 
- UDP_ENCAP_GTP1U
 
- UDP_ENCAP_L2TPINUDP
 
- UDP_ENCAP_RXRPC
 
- UDP_FRAME
 
- UDP_GENEVE_PORT_NUM
 
- UDP_GRO
 
- UDP_GRO_CNT_MAX
 
- UDP_HDR_LEN
 
- UDP_HDR_OFFSET
 
- UDP_HDR_SIZE
 
- UDP_HLEN
 
- UDP_HTABLE_SIZE_MIN
 
- UDP_INC_STATS
 
- UDP_MAX_SEGMENTS
 
- UDP_MIB_CSUMERRORS
 
- UDP_MIB_IGNOREDMULTI
 
- UDP_MIB_INDATAGRAMS
 
- UDP_MIB_INERRORS
 
- UDP_MIB_MAX
 
- UDP_MIB_NOPORTS
 
- UDP_MIB_NUM
 
- UDP_MIB_OUTDATAGRAMS
 
- UDP_MIB_RCVBUFERRORS
 
- UDP_MIB_SNDBUFERRORS
 
- UDP_MIN_HEADROOM
 
- UDP_NO_CHECK6_RX
 
- UDP_NO_CHECK6_TX
 
- UDP_OFFLOAD_ENABLE
 
- UDP_PORT
 
- UDP_PORT_DEFAULT
 
- UDP_RSS_FLAGS
 
- UDP_SEGMENT
 
- UDP_SKB_CB
 
- UDP_SKB_IS_STATELESS
 
- UDP_SPORT
 
- UDP_TUNNEL_TYPE_GENEVE
 
- UDP_TUNNEL_TYPE_VXLAN
 
- UDP_TUNNEL_TYPE_VXLAN_GPE
 
- UDP_V4_FLOW
 
- UDP_V6_FLOW
 
- UDP_VXLAN_PORT_NUM
 
- UDRN
 
- UDRS
 
- UDRWE
 
- UDR_READ_RETRY_CNT
 
- UDSL_DEFAULT_RCV_BUF_SIZE
 
- UDSL_DEFAULT_RCV_URBS
 
- UDSL_DEFAULT_SND_BUF_SIZE
 
- UDSL_DEFAULT_SND_URBS
 
- UDSL_IGNORE_EILSEQ
 
- UDSL_MAX_BUF_SIZE
 
- UDSL_MAX_RCV_URBS
 
- UDSL_MAX_SND_URBS
 
- UDSL_SKB
 
- UDSL_SKIP_HEAVY_INIT
 
- UDSL_USE_ISOC
 
- UDSR_MAGIC
 
- UDS_MAX_FACTOR
 
- UDS_MAX_SIZE
 
- UDS_MIN_FACTOR
 
- UDS_MIN_SIZE
 
- UDS_PAD_SINK
 
- UDS_PAD_SOURCE
 
- UDT
 
- UDWtype
 
- UD_SEND_WQE_U32_16_DEST_QP_M
 
- UD_SEND_WQE_U32_16_DEST_QP_S
 
- UD_SEND_WQE_U32_16_MAX_STATIC_RATE_M
 
- UD_SEND_WQE_U32_16_MAX_STATIC_RATE_S
 
- UD_SEND_WQE_U32_36_FLOW_LABEL_M
 
- UD_SEND_WQE_U32_36_FLOW_LABEL_S
 
- UD_SEND_WQE_U32_36_PRIORITY_M
 
- UD_SEND_WQE_U32_36_PRIORITY_S
 
- UD_SEND_WQE_U32_36_SGID_INDEX_M
 
- UD_SEND_WQE_U32_36_SGID_INDEX_S
 
- UD_SEND_WQE_U32_40_HOP_LIMIT_M
 
- UD_SEND_WQE_U32_40_HOP_LIMIT_S
 
- UD_SEND_WQE_U32_40_TRAFFIC_CLASS_M
 
- UD_SEND_WQE_U32_40_TRAFFIC_CLASS_S
 
- UD_SEND_WQE_U32_4_DMAC_0_M
 
- UD_SEND_WQE_U32_4_DMAC_0_S
 
- UD_SEND_WQE_U32_4_DMAC_1_M
 
- UD_SEND_WQE_U32_4_DMAC_1_S
 
- UD_SEND_WQE_U32_4_DMAC_2_M
 
- UD_SEND_WQE_U32_4_DMAC_2_S
 
- UD_SEND_WQE_U32_4_DMAC_3_M
 
- UD_SEND_WQE_U32_4_DMAC_3_S
 
- UD_SEND_WQE_U32_8_DMAC_4_M
 
- UD_SEND_WQE_U32_8_DMAC_4_S
 
- UD_SEND_WQE_U32_8_DMAC_5_M
 
- UD_SEND_WQE_U32_8_DMAC_5_S
 
- UD_SEND_WQE_U32_8_LOOPBACK_INDICATOR_S
 
- UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_M
 
- UD_SEND_WQE_U32_8_NUMBER_OF_DATA_SEG_S
 
- UD_SEND_WQE_U32_8_OPERATION_TYPE_M
 
- UD_SEND_WQE_U32_8_OPERATION_TYPE_S
 
- UD_SEND_WQE_U32_8_SEND_GL_ROUTING_HDR_FLAG_S
 
- UD_SIZE_BYTES
 
- UD_VECTOR
 
- UData
 
- UEA_ATTR
 
- UEA_BIHDR
 
- UEA_BOOT_IDMA
 
- UEA_BULK_DATA_PIPE
 
- UEA_CHIP_VERSION
 
- UEA_DS_IFACE_NO
 
- UEA_E1_SET_BLOCK
 
- UEA_E4_SET_BLOCK
 
- UEA_END_RESET
 
- UEA_FW_NAME_MAX
 
- UEA_IDMA_PIPE
 
- UEA_INTR_IFACE_NO
 
- UEA_INTR_PIPE
 
- UEA_ISO_DATA_PIPE
 
- UEA_IS_PREFIRM
 
- UEA_LOOPBACK_OFF
 
- UEA_LOOPBACK_ON
 
- UEA_MPRX_MAILBOX
 
- UEA_MPTX_MAILBOX
 
- UEA_MPTX_START
 
- UEA_RESERVED
 
- UEA_SET_2183_DATA
 
- UEA_SET_MODE
 
- UEA_SET_TIMEOUT
 
- UEA_START_RESET
 
- UEA_SWAP_MAILBOX
 
- UEA_US_IFACE_NO
 
- UECC_EXCP_DETECTED
 
- UEC_HW_STATS_LEN
 
- UEC_RX_FW_STATS_LEN
 
- UEC_TX_FW_STATS_LEN
 
- UEFI_ACPI_VFCT
 
- UEFI_PARAM
 
- UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT
 
- UEMPR_PAUSE_TIME_VALUE_SHIFT
 
- UER_SYNC
 
- UESC
 
- UESCR_AUTOZ
 
- UESCR_CLRCNT
 
- UESCR_MAXCOV_SHIFT
 
- UESCR_SCOV_SHIFT
 
- UESP
 
- UES_BYTE0
 
- UES_BYTE1
 
- UES_BYTE2
 
- UES_BYTE3
 
- UETH__VERSION
 
- UEVENT_BASE
 
- UEVENT_BUFFER_SIZE
 
- UEVENT_BUF_SIZE
 
- UEVENT_HELPER_PATH_LEN
 
- UEVENT_NUM_ENVP
 
- UE_ADDR_OFST
 
- UE_DATA_31_0_OFST
 
- UE_EFFECTIVE_ADDR_PROVIDED
 
- UE_ERR
 
- UE_LOGICAL_ADDR_PROVIDED
 
- UE_LOG_OFST
 
- UF
 
- UFCD0
 
- UFCD1
 
- UFCD2
 
- UFCD3
 
- UFCD4
 
- UFCD_BIT
 
- UFCD_DV0
 
- UFCD_DV1
 
- UFCD_DV2
 
- UFCD_DV3
 
- UFCON
 
- UFCR
 
- UFCR_DCEDTE
 
- UFCR_RFDIV
 
- UFCR_RFDIV_REG
 
- UFCR_RXTL_SHF
 
- UFCR_TXTL_SHF
 
- UFCS
 
- UFCS_BIT
 
- UFCS_SL0
 
- UFCS_SL1
 
- UFCS_SL2
 
- UFCS_SL3
 
- UFCV0
 
- UFCV1
 
- UFCV2
 
- UFCV3
 
- UFCV4
 
- UFCV_BIT
 
- UFCV_CV0
 
- UFCV_CV1
 
- UFCV_CV2
 
- UFCV_CV3
 
- UFCW
 
- UFCW_BIT
 
- UFCW_WL0
 
- UFCW_WL1
 
- UFCW_WL2
 
- UFCW_WL3
 
- UFDCS
 
- UFE_STAT
 
- UFFDIO
 
- UFFDIO_API
 
- UFFDIO_COPY
 
- UFFDIO_COPY_MODE_DONTWAKE
 
- UFFDIO_REGISTER
 
- UFFDIO_REGISTER_MODE_MISSING
 
- UFFDIO_REGISTER_MODE_WP
 
- UFFDIO_UNREGISTER
 
- UFFDIO_WAKE
 
- UFFDIO_ZEROPAGE
 
- UFFDIO_ZEROPAGE_MODE_DONTWAKE
 
- UFFD_API
 
- UFFD_API_FEATURES
 
- UFFD_API_IOCTLS
 
- UFFD_API_RANGE_IOCTLS
 
- UFFD_API_RANGE_IOCTLS_BASIC
 
- UFFD_CLOEXEC
 
- UFFD_EVENT_FORK
 
- UFFD_EVENT_PAGEFAULT
 
- UFFD_EVENT_REMAP
 
- UFFD_EVENT_REMOVE
 
- UFFD_EVENT_UNMAP
 
- UFFD_FEATURE_EVENT_FORK
 
- UFFD_FEATURE_EVENT_REMAP
 
- UFFD_FEATURE_EVENT_REMOVE
 
- UFFD_FEATURE_EVENT_UNMAP
 
- UFFD_FEATURE_MISSING_HUGETLBFS
 
- UFFD_FEATURE_MISSING_SHMEM
 
- UFFD_FEATURE_PAGEFAULT_FLAG_WP
 
- UFFD_FEATURE_SIGBUS
 
- UFFD_FEATURE_THREAD_ID
 
- UFFD_FLAGS_SET
 
- UFFD_NONBLOCK
 
- UFFD_PAGEFAULT_FLAG_WP
 
- UFFD_PAGEFAULT_FLAG_WRITE
 
- UFFD_SHARED_FCNTL_FLAGS
 
- UFFD_STATE_RUNNING
 
- UFFD_STATE_WAIT_API
 
- UFIX
 
- UFLASH_BUSWIDTH
 
- UFLASH_OBPNAME
 
- UFLASH_WINDOW_SIZE
 
- UFLO
 
- UFNRH
 
- UFNRH_IPE14
 
- UFNRH_IPE4
 
- UFNRH_IPE9
 
- UFNRH_SIM
 
- UFNRH_SIR
 
- UFNRL
 
- UFOE_MOUT_EN_DSI0
 
- UFO_BYPASS
 
- UFP
 
- UFRAME
 
- UFRMNUM
 
- UFRNM
 
- UFS
 
- UFS2_MAGIC
 
- UFS2_MAXMNTLEN
 
- UFS2_MAXVOLLEN
 
- UFS2_NOCSPTRS
 
- UFSCHD_CLK_GATING_STATES
 
- UFSD
 
- UFSHCD
 
- UFSHCD_AMP
 
- UFSHCD_CAN_QUEUE
 
- UFSHCD_CAP_AUTO_BKOPS_SUSPEND
 
- UFSHCD_CAP_CLK_GATING
 
- UFSHCD_CAP_CLK_SCALING
 
- UFSHCD_CAP_HIBERN8_WITH_CLK_GATING
 
- UFSHCD_CAP_INTR_AGGR
 
- UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND
 
- UFSHCD_CMD_PER_LUN
 
- UFSHCD_DEFAULT_LANES_PER_DIRECTION
 
- UFSHCD_DRIVER_VERSION
 
- UFSHCD_EH_IN_PROGRESS
 
- UFSHCD_ENABLE_INTRS
 
- UFSHCD_ERROR_MASK
 
- UFSHCD_LINK_IS_DOWN
 
- UFSHCD_LINK_IS_UP
 
- UFSHCD_MAX_CHANNEL
 
- UFSHCD_MAX_ID
 
- UFSHCD_MICRO_AMP
 
- UFSHCD_MILI_AMP
 
- UFSHCD_NANO_AMP
 
- UFSHCD_PLTFRM_H_
 
- UFSHCD_QUIRK_BROKEN_INTR_AGGR
 
- UFSHCD_QUIRK_BROKEN_LCC
 
- UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP
 
- UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION
 
- UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS
 
- UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE
 
- UFSHCD_QUIRK_PRDT_BYTE_GRAN
 
- UFSHCD_STATE_EH_SCHEDULED
 
- UFSHCD_STATE_ERROR
 
- UFSHCD_STATE_OPERATIONAL
 
- UFSHCD_STATE_RESET
 
- UFSHCD_STATUS_READY
 
- UFSHCD_UIC_DL_NAC_RECEIVED_ERROR
 
- UFSHCD_UIC_DL_PA_INIT_ERROR
 
- UFSHCD_UIC_DL_TCx_REPLAY_ERROR
 
- UFSHCD_UIC_DME_ERROR
 
- UFSHCD_UIC_HIBERN8_MASK
 
- UFSHCD_UIC_MASK
 
- UFSHCD_UIC_NL_ERROR
 
- UFSHCD_UIC_PWR_MASK
 
- UFSHCD_UIC_TL_ERROR
 
- UFSHCI_AHIBERN8_MAX
 
- UFSHCI_AHIBERN8_SCALE_FACTOR
 
- UFSHCI_AHIBERN8_SCALE_MASK
 
- UFSHCI_AHIBERN8_TIMER_MASK
 
- UFSHCI_CRYPTO_REG_SPACE_SIZE
 
- UFSHCI_QUIRK_BROKEN_HCE
 
- UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR
 
- UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR
 
- UFSHCI_REG_SPACE_SIZE
 
- UFSHCI_VERSION_10
 
- UFSHCI_VERSION_11
 
- UFSHCI_VERSION_20
 
- UFSHCI_VERSION_21
 
- UFS_42INODEFMT
 
- UFS_42POSTBLFMT
 
- UFS_44INODEFMT
 
- UFS_ABORT_TASK
 
- UFS_ABORT_TASK_SET
 
- UFS_ACLS
 
- UFS_ACTIVE_PWR_MODE
 
- UFS_AH8_CFG
 
- UFS_AHIT_AH8ITV_MASK
 
- UFS_ANY_MODEL
 
- UFS_ANY_VENDOR
 
- UFS_ATTRIBUTE
 
- UFS_AXI_CLK_SRC
 
- UFS_BBLOCK
 
- UFS_BBSIZE
 
- UFS_BSG_H
 
- UFS_BSIZE
 
- UFS_CARD_GDSC
 
- UFS_CDB_SIZE
 
- UFS_CGNO_EMPTY
 
- UFS_CG_44BSD
 
- UFS_CG_MASK
 
- UFS_CG_OLD
 
- UFS_CG_SUN
 
- UFS_CIGAM
 
- UFS_CIGAM_4GB
 
- UFS_CIGAM_FEA
 
- UFS_CIGAM_LFN
 
- UFS_CIGAM_SEC
 
- UFS_CLEAR_TASK_SET
 
- UFS_CNTLR_2_x_x_VEN_REGS_OFFSET
 
- UFS_CNTLR_3_x_x_VEN_REGS_OFFSET
 
- UFS_DBG_RD_REG_DFC
 
- UFS_DBG_RD_REG_RXUC
 
- UFS_DBG_RD_REG_TMRLUT
 
- UFS_DBG_RD_REG_TRLUT
 
- UFS_DBG_RD_REG_TXUC
 
- UFS_DBG_RD_REG_UARM
 
- UFS_DBG_RD_REG_UAWM
 
- UFS_DEFAULTOPT
 
- UFS_DESC_PARAM
 
- UFS_DEVICE_DESC_PARAM
 
- UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM
 
- UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME
 
- UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE
 
- UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME
 
- UFS_DEVICE_QUIRK_PA_TACTIVATE
 
- UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS
 
- UFS_DEVICE_RESET_CTRL
 
- UFS_DE_44BSD
 
- UFS_DE_MASK
 
- UFS_DE_OLD
 
- UFS_DIND_BLOCK
 
- UFS_DIND_FRAGMENT
 
- UFS_DIR_PAD
 
- UFS_DIR_REC_LEN
 
- UFS_DIR_ROUND
 
- UFS_DOSOFTDEP
 
- UFS_DYNAMICPOSTBLFMT
 
- UFS_ERR_REG_HIST_LENGTH
 
- UFS_FIRST_INO
 
- UFS_FIX
 
- UFS_FLAG
 
- UFS_FLAGS_UPDATED
 
- UFS_FREQ_CFG_CLK
 
- UFS_FSACTIVE
 
- UFS_FSBAD
 
- UFS_FSCLEAN
 
- UFS_FSFIX
 
- UFS_FSF_B1
 
- UFS_FSF_LFN
 
- UFS_FSF_LFS
 
- UFS_FSF_LUID
 
- UFS_FSIZE
 
- UFS_FSLOG
 
- UFS_FSOK
 
- UFS_FSOSF1
 
- UFS_FSSTABLE
 
- UFS_FSSUSPEND
 
- UFS_GDSC
 
- UFS_GEOMETRY_DESC_PARAM
 
- UFS_HCLKDIV_NORMAL_VALUE
 
- UFS_HEALTH_DESC_PARAM
 
- UFS_HISI_CAP_PHY10nm
 
- UFS_HISI_CAP_RESERVED
 
- UFS_HISI_H_
 
- UFS_HISI_LIMIT_DESIRED_MODE
 
- UFS_HISI_LIMIT_HSGEAR_RX
 
- UFS_HISI_LIMIT_HSGEAR_TX
 
- UFS_HISI_LIMIT_HS_RATE
 
- UFS_HISI_LIMIT_NUM_LANES_RX
 
- UFS_HISI_LIMIT_NUM_LANES_TX
 
- UFS_HISI_LIMIT_PWMGEAR_RX
 
- UFS_HISI_LIMIT_PWMGEAR_TX
 
- UFS_HISI_LIMIT_RX_PWR_HS
 
- UFS_HISI_LIMIT_RX_PWR_PWM
 
- UFS_HISI_LIMIT_TX_PWR_HS
 
- UFS_HISI_LIMIT_TX_PWR_PWM
 
- UFS_HS_DONT_CHANGE
 
- UFS_HS_G1
 
- UFS_HS_G2
 
- UFS_HS_G3
 
- UFS_HS_MODE
 
- UFS_HW_VER_MAJOR_MASK
 
- UFS_HW_VER_MAJOR_SHFT
 
- UFS_HW_VER_MINOR_MASK
 
- UFS_HW_VER_MINOR_SHFT
 
- UFS_HW_VER_STEP_MASK
 
- UFS_HW_VER_STEP_SHFT
 
- UFS_I
 
- UFS_ICE_CORE_CLK_SRC
 
- UFS_INDEXDIRS
 
- UFS_IND_BLOCK
 
- UFS_IND_FRAGMENT
 
- UFS_INTERCONNECT_DESC_PARAM
 
- UFS_LINK_MAX
 
- UFS_LINK_STATES
 
- UFS_LOGICAL_RESET
 
- UFS_LUN_DESC_PARAM
 
- UFS_LU_NO_WP
 
- UFS_LU_PERM_WP
 
- UFS_LU_POWER_ON_WP
 
- UFS_MAGIC
 
- UFS_MAGIC_4GB
 
- UFS_MAGIC_BW
 
- UFS_MAGIC_FEA
 
- UFS_MAGIC_LFN
 
- UFS_MAGIC_SEC
 
- UFS_MASK
 
- UFS_MAXCSBUFS
 
- UFS_MAXFRAG
 
- UFS_MAXMNTLEN
 
- UFS_MAXNAMLEN
 
- UFS_MAX_GROUP_LOADED
 
- UFS_MAX_LUNS
 
- UFS_MINBSIZE
 
- UFS_MINFREE
 
- UFS_MIN_GEAR_TO_SCALE_DOWN
 
- UFS_MOUNT_ONERROR
 
- UFS_MOUNT_ONERROR_LOCK
 
- UFS_MOUNT_ONERROR_PANIC
 
- UFS_MOUNT_ONERROR_REPAIR
 
- UFS_MOUNT_ONERROR_UMOUNT
 
- UFS_MOUNT_UFSTYPE
 
- UFS_MOUNT_UFSTYPE_44BSD
 
- UFS_MOUNT_UFSTYPE_HP
 
- UFS_MOUNT_UFSTYPE_NEXTSTEP
 
- UFS_MOUNT_UFSTYPE_NEXTSTEP_CD
 
- UFS_MOUNT_UFSTYPE_OLD
 
- UFS_MOUNT_UFSTYPE_OPENSTEP
 
- UFS_MOUNT_UFSTYPE_SUN
 
- UFS_MOUNT_UFSTYPE_SUNOS
 
- UFS_MOUNT_UFSTYPE_SUNx86
 
- UFS_MOUNT_UFSTYPE_UFS2
 
- UFS_MTK_LIMIT_DESIRED_MODE
 
- UFS_MTK_LIMIT_HSGEAR_RX
 
- UFS_MTK_LIMIT_HSGEAR_TX
 
- UFS_MTK_LIMIT_HS_RATE
 
- UFS_MTK_LIMIT_NUM_LANES_RX
 
- UFS_MTK_LIMIT_NUM_LANES_TX
 
- UFS_MTK_LIMIT_PWMGEAR_RX
 
- UFS_MTK_LIMIT_PWMGEAR_TX
 
- UFS_MTK_LIMIT_RX_PWR_HS
 
- UFS_MTK_LIMIT_RX_PWR_PWM
 
- UFS_MTK_LIMIT_TX_PWR_HS
 
- UFS_MTK_LIMIT_TX_PWR_PWM
 
- UFS_MULTILABEL
 
- UFS_NDADDR
 
- UFS_NDIR_FRAGMENT
 
- UFS_NEEDSFSCK
 
- UFS_NINDIR
 
- UFS_NXADDR
 
- UFS_OPTSPACE
 
- UFS_OPTTIME
 
- UFS_PHY_AUX_CLK_SRC
 
- UFS_PHY_CFG_CHANGE_CNT_VAL
 
- UFS_PHY_CORECLK_PWM_G1_CLK_DIVIDER
 
- UFS_PHY_CORECLK_PWM_G2_CLK_DIVIDER
 
- UFS_PHY_CORECLK_PWM_G3_CLK_DIVIDER
 
- UFS_PHY_CORECLK_PWM_G4_CLK_DIVIDER
 
- UFS_PHY_GDSC
 
- UFS_PHY_LINE_RESET_GRANULARITY
 
- UFS_PHY_LINE_RESET_TIME
 
- UFS_PHY_NAME
 
- UFS_PHY_OMC_STATUS_RDVAL
 
- UFS_PHY_PCS_READY_STATUS
 
- UFS_PHY_PHY_START
 
- UFS_PHY_PLL_CNTL
 
- UFS_PHY_POWER_DOWN_CONTROL
 
- UFS_PHY_PWM_G1_CLK_DIVIDER
 
- UFS_PHY_PWM_G2_CLK_DIVIDER
 
- UFS_PHY_PWM_G3_CLK_DIVIDER
 
- UFS_PHY_PWM_G4_CLK_DIVIDER
 
- UFS_PHY_RMMI_ATTRID
 
- UFS_PHY_RMMI_ATTRRDVAL_L0_STATUS
 
- UFS_PHY_RMMI_ATTRRDVAL_L1_STATUS
 
- UFS_PHY_RMMI_ATTRWRVAL
 
- UFS_PHY_RMMI_ATTR_CTRL
 
- UFS_PHY_RMMI_CFGRD_L0
 
- UFS_PHY_RMMI_CFGRD_L1
 
- UFS_PHY_RMMI_CFGWR_L0
 
- UFS_PHY_RMMI_CFGWR_L1
 
- UFS_PHY_RMMI_RX_CFGUPDT_L0
 
- UFS_PHY_RMMI_RX_CFGUPDT_L1
 
- UFS_PHY_RMMI_TX_CFGUPDT_L0
 
- UFS_PHY_RMMI_TX_CFGUPDT_L1
 
- UFS_PHY_RX_MIN_ACTIVATETIME_CAPABILITY
 
- UFS_PHY_RX_MIN_SAVE_CONFIG_TIME_CAPABILITY
 
- UFS_PHY_RX_MIN_SLEEP_NOCONFIG_TIME_CAPABILITY
 
- UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAPABILITY
 
- UFS_PHY_RX_PWM_BURST_CLOSURE_LENGTH_CAPABILITY
 
- UFS_PHY_RX_SIGDET_CTRL3
 
- UFS_PHY_RX_SYNC_WAIT_TIME
 
- UFS_PHY_TSYNC_RSYNC_CNTL
 
- UFS_PHY_TX_LANE_ENABLE
 
- UFS_PHY_TX_LANE_ENABLE_MASK
 
- UFS_PHY_TX_LARGE_AMP_DRV_LVL
 
- UFS_PHY_TX_LARGE_AMP_POST_EMP_LVL
 
- UFS_PHY_TX_MIN_SAVE_CONFIG_TIME_CAPABILITY
 
- UFS_PHY_TX_MIN_SLEEP_NOCONFIG_TIME_CAPABILITY
 
- UFS_PHY_TX_MIN_STALL_NOCONFIG_TIME_CAPABILITY
 
- UFS_PHY_TX_SMALL_AMP_DRV_LVL
 
- UFS_PHY_TX_SMALL_AMP_POST_EMP_LVL
 
- UFS_PHY_VDDA_PHY_UV
 
- UFS_PM_LVL_0
 
- UFS_PM_LVL_1
 
- UFS_PM_LVL_2
 
- UFS_PM_LVL_3
 
- UFS_PM_LVL_4
 
- UFS_PM_LVL_5
 
- UFS_PM_LVL_MAX
 
- UFS_POWERDOWN_PWR_MODE
 
- UFS_POWER_DESC_PARAM
 
- UFS_PWM_DONT_CHANGE
 
- UFS_PWM_G1
 
- UFS_PWM_G2
 
- UFS_PWM_G3
 
- UFS_PWM_G4
 
- UFS_PWM_G5
 
- UFS_PWM_G6
 
- UFS_PWM_G7
 
- UFS_PWM_MODE
 
- UFS_PWR_MODES
 
- UFS_QCOM_CAP_QUNIPRO
 
- UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE
 
- UFS_QCOM_DBG_PRINT_ALL
 
- UFS_QCOM_DBG_PRINT_ICE_REGS_EN
 
- UFS_QCOM_DBG_PRINT_REGS_EN
 
- UFS_QCOM_DBG_PRINT_TEST_BUS_EN
 
- UFS_QCOM_DEFAULT_DBG_PRINT_EN
 
- UFS_QCOM_H_
 
- UFS_QCOM_LIMIT_DESIRED_MODE
 
- UFS_QCOM_LIMIT_HSGEAR_RX
 
- UFS_QCOM_LIMIT_HSGEAR_TX
 
- UFS_QCOM_LIMIT_HS_RATE
 
- UFS_QCOM_LIMIT_NUM_LANES_RX
 
- UFS_QCOM_LIMIT_NUM_LANES_TX
 
- UFS_QCOM_LIMIT_PWMGEAR_RX
 
- UFS_QCOM_LIMIT_PWMGEAR_TX
 
- UFS_QCOM_LIMIT_RX_PWR_HS
 
- UFS_QCOM_LIMIT_RX_PWR_PWM
 
- UFS_QCOM_LIMIT_TX_PWR_HS
 
- UFS_QCOM_LIMIT_TX_PWR_PWM
 
- UFS_QCOM_PHY_CAL_ENTRY
 
- UFS_QCOM_PHY_I_H_
 
- UFS_QCOM_PHY_NAME_LEN
 
- UFS_QCOM_PHY_QMP_14NM_H_
 
- UFS_QCOM_PHY_QMP_20NM_H_
 
- UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE
 
- UFS_QUERY_TASK
 
- UFS_QUERY_TASK_SET
 
- UFS_REG_CDACFG
 
- UFS_REG_CDARX1
 
- UFS_REG_CDARX2
 
- UFS_REG_CDASTA
 
- UFS_REG_CDATX1
 
- UFS_REG_CDATX2
 
- UFS_REG_HCLKDIV
 
- UFS_REG_LBMCFG
 
- UFS_REG_LBMSTA
 
- UFS_REG_OCPTHRTL
 
- UFS_REG_OOCPR
 
- UFS_REG_TEST_BUS_EN
 
- UFS_REG_UFSMODE
 
- UFS_RESET
 
- UFS_ROOTINO
 
- UFS_RUNTIME_PM
 
- UFS_SBLOCK
 
- UFS_SBSIZE
 
- UFS_SECTOR_BITS
 
- UFS_SECTOR_SIZE
 
- UFS_SENSE_SIZE
 
- UFS_SF_APPEND
 
- UFS_SF_ARCHIVED
 
- UFS_SF_IMMUTABLE
 
- UFS_SF_NOUNLINK
 
- UFS_SF_SETTABLE
 
- UFS_SHUTDOWN_PM
 
- UFS_SLEEP_PWR_MODE
 
- UFS_STRING_DESCRIPTOR
 
- UFS_ST_44BSD
 
- UFS_ST_MASK
 
- UFS_ST_OLD
 
- UFS_ST_SUN
 
- UFS_ST_SUNOS
 
- UFS_ST_SUNx86
 
- UFS_SYSCTRL
 
- UFS_SYSTEM_PM
 
- UFS_TEST_BUS
 
- UFS_TEST_BUS_CTRL_0
 
- UFS_TEST_BUS_CTRL_1
 
- UFS_TEST_BUS_CTRL_2
 
- UFS_TEST_FREE_SPACE_CG
 
- UFS_TIND_BLOCK
 
- UFS_TIND_FRAGMENT
 
- UFS_TYPE_MASK
 
- UFS_TYPE_UFS1
 
- UFS_TYPE_UFS2
 
- UFS_UFS_DBG_RD_DESC_RAM
 
- UFS_UFS_DBG_RD_EDTL_RAM
 
- UFS_UFS_DBG_RD_PRDT_RAM
 
- UFS_UFS_DBG_RD_REG_OCSC
 
- UFS_UFS_DBG_RD_RESP_RAM
 
- UFS_UF_APPEND
 
- UFS_UF_IMMUTABLE
 
- UFS_UF_NODUMP
 
- UFS_UF_NOUNLINK
 
- UFS_UF_OPAQUE
 
- UFS_UF_SETTABLE
 
- UFS_UIC_COMMAND_RETRIES
 
- UFS_UID_44BSD
 
- UFS_UID_EFT
 
- UFS_UID_MASK
 
- UFS_UID_OLD
 
- UFS_UNCLEAN
 
- UFS_UNIPRO_CFG
 
- UFS_UNIPRO_CORE_CLK_SRC
 
- UFS_UNIPRO_VER_1_40
 
- UFS_UNIPRO_VER_1_41
 
- UFS_UNIPRO_VER_1_6
 
- UFS_UNIPRO_VER_MASK
 
- UFS_UNIPRO_VER_MAX
 
- UFS_UNIPRO_VER_RESERVED
 
- UFS_UNIT_DESC_PARAM
 
- UFS_UPIU_BOOT_WLUN
 
- UFS_UPIU_MAX_GENERAL_LUN
 
- UFS_UPIU_MAX_UNIT_NUM_ID
 
- UFS_UPIU_REPORT_LUNS_WLUN
 
- UFS_UPIU_RPMB_WLUN
 
- UFS_UPIU_UFS_DEVICE_WLUN
 
- UFS_UPIU_WLUN_ID
 
- UFS_USEEFT
 
- UFS_VENDOR_SAMSUNG
 
- UFS_VENDOR_SKHYNIX
 
- UFS_VENDOR_TOSHIBA
 
- UFS_VREG_LPM_LOAD_UA
 
- UFS_VREG_VCCQ2_MAX_UV
 
- UFS_VREG_VCCQ2_MIN_UV
 
- UFS_VREG_VCCQ_MAX_UV
 
- UFS_VREG_VCCQ_MIN_UV
 
- UFS_VREG_VCC_1P8_MAX_UV
 
- UFS_VREG_VCC_1P8_MIN_UV
 
- UFS_VREG_VCC_MAX_UV
 
- UFS_VREG_VCC_MIN_UV
 
- UFWP
 
- UFX_DEFIO_WRITE_DELAY
 
- UFX_DEFIO_WRITE_DISABLE
 
- UFX_IOCTL_REPORT_DAMAGE
 
- UFX_IOCTL_RETURN_EDID
 
- UF_NODISC
 
- UF_NOSCAN
 
- UF_TRACE
 
- UGA_IO_PROTOCOL_GUID
 
- UGCTRL
 
- UGCTRL2
 
- UGCTRL2_RESERVED_3
 
- UGCTRL2_USB0SEL_HSUSB
 
- UGCTRL2_USB0SEL_OTG
 
- UGCTRL2_VBUSSEL
 
- UGCTRL_CONNECT
 
- UGCTRL_PLLRESET
 
- UGETH_MSG_DEFAULT
 
- UGE_BASE
 
- UGE_BCOLOR
 
- UGE_CLIP0
 
- UGE_CLIP1
 
- UGE_COMMAND
 
- UGE_DCH
 
- UGE_DCL
 
- UGE_DSTSTART
 
- UGE_DSTXY
 
- UGE_FCOLOR
 
- UGE_P0
 
- UGE_P1
 
- UGE_P10
 
- UGE_P11
 
- UGE_P12
 
- UGE_P13
 
- UGE_P14
 
- UGE_P15
 
- UGE_P16
 
- UGE_P17
 
- UGE_P18
 
- UGE_P19
 
- UGE_P2
 
- UGE_P20
 
- UGE_P21
 
- UGE_P22
 
- UGE_P23
 
- UGE_P24
 
- UGE_P25
 
- UGE_P26
 
- UGE_P27
 
- UGE_P28
 
- UGE_P29
 
- UGE_P3
 
- UGE_P30
 
- UGE_P31
 
- UGE_P4
 
- UGE_P5
 
- UGE_P6
 
- UGE_P7
 
- UGE_P8
 
- UGE_P9
 
- UGE_PITCH
 
- UGE_ROPALPHA
 
- UGE_SCH
 
- UGE_SCL
 
- UGE_SRCSTART
 
- UGE_SRCXY
 
- UGE_WIDHEIGHT
 
- UGRUADDR
 
- UGSTS
 
- UGSTS_LOCK
 
- UG_READ_ATTEMPTS
 
- UG_WRITE_ATTEMPTS
 
- UHCBCED
 
- UHCBHED
 
- UHCCCED
 
- UHCCHED
 
- UHCCOMS
 
- UHCDHEAD
 
- UHCFMI
 
- UHCFMN
 
- UHCFMR
 
- UHCHCCA
 
- UHCHCON
 
- UHCHIE
 
- UHCHIE_HBAIE
 
- UHCHIE_RWIE
 
- UHCHIE_TAIE
 
- UHCHIE_UPRIE
 
- UHCHIE_UPS1IE
 
- UHCHIE_UPS2IE
 
- UHCHIE_UPS3IE
 
- UHCHIT
 
- UHCHR
 
- UHCHR_CGR
 
- UHCHR_FHR
 
- UHCHR_FSBIR
 
- UHCHR_PCPL
 
- UHCHR_PSPL
 
- UHCHR_SSDC
 
- UHCHR_SSE
 
- UHCHR_SSEP1
 
- UHCHR_SSEP2
 
- UHCHR_SSEP3
 
- UHCHR_UIT
 
- UHCINTD
 
- UHCINTE
 
- UHCINTS
 
- UHCI_DEBUG_OPS
 
- UHCI_IS_STOPPED
 
- UHCI_MAX_SOF_NUMBER
 
- UHCI_NUMFRAMES
 
- UHCI_NUM_SKELQH
 
- UHCI_PTR_BITS
 
- UHCI_PTR_BREADTH
 
- UHCI_PTR_DEPTH
 
- UHCI_PTR_QH
 
- UHCI_PTR_TERM
 
- UHCI_RH_AUTO_STOPPED
 
- UHCI_RH_MAXCHILD
 
- UHCI_RH_RESET
 
- UHCI_RH_RESUMING
 
- UHCI_RH_RUNNING
 
- UHCI_RH_RUNNING_NODEVS
 
- UHCI_RH_SUSPENDED
 
- UHCI_RH_SUSPENDING
 
- UHCI_USBCMD
 
- UHCI_USBCMD_CONFIGURE
 
- UHCI_USBCMD_EGSM
 
- UHCI_USBCMD_HCRESET
 
- UHCI_USBCMD_RUN
 
- UHCI_USBINTR
 
- UHCI_USBINTR_RESUME
 
- UHCI_USBLEGSUP
 
- UHCI_USBLEGSUP_RO
 
- UHCI_USBLEGSUP_RWC
 
- UHCLS
 
- UHCPCED
 
- UHCPERS
 
- UHCREV
 
- UHCRHDA
 
- UHCRHDA_NOCP
 
- UHCRHDA_OCPM
 
- UHCRHDA_POTPGT
 
- UHCRHDB
 
- UHCRHPS1
 
- UHCRHPS2
 
- UHCRHPS3
 
- UHCRHS
 
- UHCSTAT
 
- UHCSTAT_HBA
 
- UHCSTAT_HTA
 
- UHCSTAT_RWUE
 
- UHCSTAT_SBMAI
 
- UHCSTAT_SBTAI
 
- UHCSTAT_UPRI
 
- UHCSTAT_UPS1
 
- UHCSTAT_UPS2
 
- UHCSTAT_UPS3
 
- UHID_BUFSIZE
 
- UHID_CLOSE
 
- UHID_CREATE
 
- UHID_CREATE2
 
- UHID_DATA_MAX
 
- UHID_DESTROY
 
- UHID_DEV_NUMBERED_FEATURE_REPORTS
 
- UHID_DEV_NUMBERED_INPUT_REPORTS
 
- UHID_DEV_NUMBERED_OUTPUT_REPORTS
 
- UHID_FEATURE
 
- UHID_FEATURE_ANSWER
 
- UHID_FEATURE_REPORT
 
- UHID_GET_REPORT
 
- UHID_GET_REPORT_REPLY
 
- UHID_INPUT
 
- UHID_INPUT2
 
- UHID_INPUT_REPORT
 
- UHID_MINOR
 
- UHID_NAME
 
- UHID_OPEN
 
- UHID_OUTPUT
 
- UHID_OUTPUT_EV
 
- UHID_OUTPUT_REPORT
 
- UHID_SET_REPORT
 
- UHID_SET_REPORT_REPLY
 
- UHID_START
 
- UHID_STOP
 
- UHIMR_ATIMEND
 
- UHIMR_ATIMEND_E
 
- UHIMR_BCNDMAINT0
 
- UHIMR_BCNDMAINT1
 
- UHIMR_BCNDMAINT2
 
- UHIMR_BCNDMAINT3
 
- UHIMR_BCNDMAINT4
 
- UHIMR_BCNDMAINT5
 
- UHIMR_BCNDMAINT6
 
- UHIMR_BCNDMAINT7
 
- UHIMR_BCNDMAINT_E
 
- UHIMR_BCNDOK0
 
- UHIMR_BCNDOK1
 
- UHIMR_BCNDOK2
 
- UHIMR_BCNDOK3
 
- UHIMR_BCNDOK4
 
- UHIMR_BCNDOK5
 
- UHIMR_BCNDOK6
 
- UHIMR_BCNDOK7
 
- UHIMR_BEDOK
 
- UHIMR_BKDOK
 
- UHIMR_C2HCMD
 
- UHIMR_CPWM
 
- UHIMR_CPWM2
 
- UHIMR_CTW_END
 
- UHIMR_GTINT3
 
- UHIMR_GTINT4
 
- UHIMR_HIGHDOK
 
- UHIMR_HSISR_IND
 
- UHIMR_MGNTDOK
 
- UHIMR_OCPINT
 
- UHIMR_PSTIMEOUT
 
- UHIMR_RDU
 
- UHIMR_ROK
 
- UHIMR_RXERR
 
- UHIMR_RXFOVW
 
- UHIMR_TIMEOUT1
 
- UHIMR_TIMEOUT2
 
- UHIMR_TSF_BIT32_TOGGLE
 
- UHIMR_TXBCNERR
 
- UHIMR_TXBCNOK
 
- UHIMR_TXERR
 
- UHIMR_TXFOVW
 
- UHIMR_VIDOK
 
- UHIMR_VODOK
 
- UHOST_EN
 
- UHSIC_RESET
 
- UHS_DDR50_BUS_SPEED
 
- UHS_DDR50_MAX_DTR
 
- UHS_REG_EXT_DRIVE_MASK
 
- UHS_REG_EXT_SAMPLE_DLY_MASK
 
- UHS_REG_EXT_SAMPLE_DRVPHASE_MASK
 
- UHS_REG_EXT_SAMPLE_MASK
 
- UHS_REG_EXT_SAMPLE_PHASE_MASK
 
- UHS_SDR104_BUS_SPEED
 
- UHS_SDR104_MAX_DTR
 
- UHS_SDR12_BUS_SPEED
 
- UHS_SDR12_MAX_DTR
 
- UHS_SDR25_BUS_SPEED
 
- UHS_SDR25_MAX_DTR
 
- UHS_SDR50_BUS_SPEED
 
- UHS_SDR50_MAX_DTR
 
- UHWtype
 
- UI
 
- UI5
 
- UI7
 
- UICR0
 
- UICR0_IM0
 
- UICR0_IM1
 
- UICR0_IM2
 
- UICR0_IM3
 
- UICR0_IM4
 
- UICR0_IM5
 
- UICR0_IM6
 
- UICR0_IM7
 
- UICR1
 
- UICR1_IM10
 
- UICR1_IM11
 
- UICR1_IM12
 
- UICR1_IM13
 
- UICR1_IM14
 
- UICR1_IM15
 
- UICR1_IM8
 
- UICR1_IM9
 
- UIC_ARG_ATTR_TYPE
 
- UIC_ARG_MIB
 
- UIC_ARG_MIB_SEL
 
- UIC_ARG_MPHY_RX_GEN_SEL_INDEX
 
- UIC_ARG_MPHY_TX_GEN_SEL_INDEX
 
- UIC_CMD_DME_ENABLE
 
- UIC_CMD_DME_END_PT_RST
 
- UIC_CMD_DME_GET
 
- UIC_CMD_DME_HIBER_ENTER
 
- UIC_CMD_DME_HIBER_EXIT
 
- UIC_CMD_DME_LINK_STARTUP
 
- UIC_CMD_DME_PEER_GET
 
- UIC_CMD_DME_PEER_SET
 
- UIC_CMD_DME_POWEROFF
 
- UIC_CMD_DME_POWERON
 
- UIC_CMD_DME_RESET
 
- UIC_CMD_DME_SET
 
- UIC_CMD_DME_TEST_MODE
 
- UIC_CMD_RESULT_BAD_INDEX
 
- UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX
 
- UIC_CMD_RESULT_BUSY
 
- UIC_CMD_RESULT_DME_FAILURE
 
- UIC_CMD_RESULT_FAILURE
 
- UIC_CMD_RESULT_INVALID_ATTR
 
- UIC_CMD_RESULT_INVALID_ATTR_VALUE
 
- UIC_CMD_RESULT_LOCKED_ATTR
 
- UIC_CMD_RESULT_PEER_COMM_FAILURE
 
- UIC_CMD_RESULT_READ_ONLY_ATTR
 
- UIC_CMD_RESULT_SUCCESS
 
- UIC_CMD_RESULT_WRITE_ONLY_ATTR
 
- UIC_CMD_SIZE
 
- UIC_CMD_TIMEOUT
 
- UIC_COMMAND_COMPL
 
- UIC_COMMAND_READY
 
- UIC_CR
 
- UIC_DATA_LINK_LAYER_ERROR
 
- UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP
 
- UIC_DATA_LINK_LAYER_ERROR_CODE_MASK
 
- UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP
 
- UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED
 
- UIC_DATA_LINK_LAYER_ERROR_PA_INIT
 
- UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF
 
- UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP
 
- UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT
 
- UIC_DME_END_PT_RESET
 
- UIC_DME_ERROR
 
- UIC_DME_ERROR_CODE_MASK
 
- UIC_ER
 
- UIC_ERROR
 
- UIC_GET_ATTR_ID
 
- UIC_HIBERN8_ENTER_RETRIES
 
- UIC_HIBERNATE_ENTER
 
- UIC_HIBERNATE_EXIT
 
- UIC_LINK_ACTIVE_STATE
 
- UIC_LINK_HIBERN8_STATE
 
- UIC_LINK_LOST
 
- UIC_LINK_OFF_STATE
 
- UIC_LINK_STARTUP
 
- UIC_MSR
 
- UIC_NETWORK_BAD_DEVICEID_ENC
 
- UIC_NETWORK_LAYER_ERROR
 
- UIC_NETWORK_LAYER_ERROR_CODE_MASK
 
- UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING
 
- UIC_NETWORK_UNSUPPORTED_HEADER_TYPE
 
- UIC_PHY_ADAPTER_LAYER_ERROR
 
- UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK
 
- UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK
 
- UIC_POWER_MODE
 
- UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK
 
- UIC_PR
 
- UIC_SR
 
- UIC_TEST_MODE
 
- UIC_TR
 
- UIC_TRANSPORT_BAD_TC
 
- UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING
 
- UIC_TRANSPORT_E2E_CREDIT_OVERFOW
 
- UIC_TRANSPORT_LAYER_ERROR
 
- UIC_TRANSPORT_LAYER_ERROR_CODE_MASK
 
- UIC_TRANSPORT_NO_CONNECTION_RX
 
- UIC_TRANSPORT_SAFETY_VALUE_DROPPING
 
- UIC_TRANSPORT_UNKNOWN_CPORTID
 
- UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE
 
- UIC_VCR
 
- UIC_VR
 
- UIDHASH_BITS
 
- UIDHASH_MASK
 
- UIDHASH_SZ
 
- UID_GID_MAP_MAX_BASE_EXTENTS
 
- UID_GID_MAP_MAX_EXTENTS
 
- UID_HASH
 
- UID_IS_CHARACTER
 
- UID_IS_INTEGER
 
- UID_KEY_LEN
 
- UID_NOT_PRESENT
 
- UID_STRLEN
 
- UIEN
 
- UIF_MAX_SIZE
 
- UIF_MIN_SIZE
 
- UIF_PAD_SINK
 
- UIF_PAD_SOURCE
 
- UIH
 
- UIM
 
- UIM6
 
- UIMM
 
- UIMM2
 
- UIMM3
 
- UIMM4
 
- UINPUT_BUFFER_SIZE
 
- UINPUT_IOCTL_BASE
 
- UINPUT_MAX_NAME_SIZE
 
- UINPUT_MINOR
 
- UINPUT_NAME
 
- UINPUT_NUM_REQUESTS
 
- UINPUT_VERSION
 
- UINSNS_PER_PAGE
 
- UINT
 
- UINT16
 
- UINT32
 
- UINT32_MAX
 
- UINT48_MAX
 
- UINT64_C
 
- UINT64_CAST
 
- UINTCMD
 
- UINTTYPE
 
- UINT_MAX
 
- UIOC_RD
 
- UIOC_WR
 
- UIOLI
 
- UIO_CID_OFFSET
 
- UIO_CID_PAD
 
- UIO_DEV_OPENED
 
- UIO_DPM
 
- UIO_DPM_ALIGN
 
- UIO_DPM_CID0_OFFSET
 
- UIO_FASTIOV
 
- UIO_IRQ_CUSTOM
 
- UIO_IRQ_DISABLED
 
- UIO_IRQ_NONE
 
- UIO_MAXIOV
 
- UIO_MAX_DEVICES
 
- UIO_MEM_IOVA
 
- UIO_MEM_LOGICAL
 
- UIO_MEM_NONE
 
- UIO_MEM_PHYS
 
- UIO_MEM_VIRTUAL
 
- UIO_PORT_GPIO
 
- UIO_PORT_NONE
 
- UIO_PORT_OTHER
 
- UIO_PORT_X86
 
- UIO_ROUNDUP
 
- UIO_USE_TX_DOORBELL
 
- UIRQ
 
- UISIGNOPT
 
- UIST_CREATED
 
- UIST_NEW_DEVICE
 
- UIST_SETUP_COMPLETE
 
- UIS_DMA_BIDIRECTIONAL
 
- UIS_DMA_FROM_DEVICE
 
- UIS_DMA_NONE
 
- UIS_DMA_TO_DEVICE
 
- UI_ABS_SETUP
 
- UI_BEGIN_FF_ERASE
 
- UI_BEGIN_FF_UPLOAD
 
- UI_BEGIN_FF_UPLOAD_COMPAT
 
- UI_BITMAP
 
- UI_CMD
 
- UI_CONFIG_CONTAINER
 
- UI_CONTAINER
 
- UI_CURRENT
 
- UI_DEV_CREATE
 
- UI_DEV_DESTROY
 
- UI_DEV_SETUP
 
- UI_END_FF_ERASE
 
- UI_END_FF_UPLOAD
 
- UI_END_FF_UPLOAD_COMPAT
 
- UI_EXTENDED_SIZE
 
- UI_FF_ERASE
 
- UI_FF_UPLOAD
 
- UI_FLAGS
 
- UI_GET_SYSNAME
 
- UI_GET_VERSION
 
- UI_HISTORY_END
 
- UI_HISTORY_START
 
- UI_IMAGE
 
- UI_PROTOCOL_DESCRIPTOR_CONTAINER
 
- UI_SC_CTL
 
- UI_SET_ABSBIT
 
- UI_SET_EVBIT
 
- UI_SET_FFBIT
 
- UI_SET_KEYBIT
 
- UI_SET_LEDBIT
 
- UI_SET_MSCBIT
 
- UI_SET_PHYS
 
- UI_SET_PHYS_COMPAT
 
- UI_SET_PROPBIT
 
- UI_SET_RELBIT
 
- UI_SET_SNDBIT
 
- UI_SET_SWBIT
 
- UI_SIZE
 
- UI_error
 
- UJ_PER_MJ
 
- UKEYP
 
- UL
 
- ULARGE_INTEGER
 
- ULCF_CFG_EN_CTL_MASK
 
- ULCF_CFG_EN_CTL_MASK_SFT
 
- ULCF_CFG_EN_CTL_SFT
 
- ULCON
 
- ULD_CTX
 
- ULEDS_NAME
 
- ULEDS_STATE_REGISTERED
 
- ULEDS_STATE_UNKNOWN
 
- ULE_BRIDGED
 
- ULE_OPTEXTHDR_PADDING
 
- ULE_TEST
 
- ULI5261_MAX_MULTICAST
 
- ULI526X_100MFD
 
- ULI526X_100MHF
 
- ULI526X_10MFD
 
- ULI526X_10MHF
 
- ULI526X_AUTO
 
- ULI526X_DBUG
 
- ULI526X_IO_SIZE
 
- ULI526X_RESET
 
- ULI526X_TIMER_WUT
 
- ULI526X_TXTH_128
 
- ULI526X_TXTH_1K
 
- ULI526X_TXTH_256
 
- ULI526X_TXTH_512
 
- ULI526X_TXTH_72
 
- ULI526X_TXTH_96
 
- ULI526X_TX_KICK
 
- ULI526X_TX_TIMEOUT
 
- ULI5281_BASE
 
- ULI5281_OFFS
 
- ULI5287_BASE
 
- ULI5287_OFFS
 
- ULIST_ITER_INIT
 
- ULITE_CONTROL
 
- ULITE_CONTROL_IE
 
- ULITE_CONTROL_RST_RX
 
- ULITE_CONTROL_RST_TX
 
- ULITE_MAJOR
 
- ULITE_MINOR
 
- ULITE_NAME
 
- ULITE_NR_UARTS
 
- ULITE_REGION
 
- ULITE_RX
 
- ULITE_STATUS
 
- ULITE_STATUS_FRAME
 
- ULITE_STATUS_IE
 
- ULITE_STATUS_OVERRUN
 
- ULITE_STATUS_PARITY
 
- ULITE_STATUS_RXFULL
 
- ULITE_STATUS_RXVALID
 
- ULITE_STATUS_TXEMPTY
 
- ULITE_STATUS_TXFULL
 
- ULITE_TX
 
- ULI_8259_IRQ1
 
- ULI_8259_IRQ10
 
- ULI_8259_IRQ11
 
- ULI_8259_IRQ12
 
- ULI_8259_IRQ14
 
- ULI_8259_IRQ15
 
- ULI_8259_IRQ3
 
- ULI_8259_IRQ4
 
- ULI_8259_IRQ5
 
- ULI_8259_IRQ6
 
- ULI_8259_IRQ7
 
- ULI_8259_IRQ9
 
- ULI_8259_NONE
 
- ULI_NUM_CAPTURE
 
- ULI_NUM_PLAYBACK
 
- ULI_PIRQA
 
- ULI_PIRQB
 
- ULI_PIRQC
 
- ULI_PIRQD
 
- ULI_PIRQE
 
- ULI_PIRQF
 
- ULI_PIRQG
 
- ULI_X86_64_BASE_ADDR
 
- ULI_X86_64_ENU_SCR_REG
 
- ULI_X86_64_HTT_FEA_REG
 
- ULL
 
- ULLONG_MAX
 
- ULL_POST_PROCESSING_PCM_MODE
 
- ULONG
 
- ULONG_CMP_GE
 
- ULONG_CMP_LT
 
- ULONG_MAX
 
- ULONG_SIZE
 
- ULP2_MAX_PDU_PAYLOAD
 
- ULP2_MAX_PKT_LEN
 
- ULP2_MAX_PKT_SIZE
 
- ULP2_MODE_ISCSI
 
- ULPCB_FLAG_BARRIER
 
- ULPCB_FLAG_COMPL
 
- ULPCB_FLAG_HOLD
 
- ULPCB_FLAG_NEED_HDR
 
- ULPCB_FLAG_NO_APPEND
 
- ULPCB_FLAG_NO_HDR
 
- ULPCB_FLAG_TLS_HDR
 
- ULPCB_FLAG_URG
 
- ULPD_APLL_CTRL
 
- ULPD_CAM_CLK_CTRL
 
- ULPD_CLOCK_CTRL
 
- ULPD_DEEP_SLEEP_TRANSITION_EN
 
- ULPD_DPLL_CTRL
 
- ULPD_IT_STATUS
 
- ULPD_LOW_PWR_EN
 
- ULPD_POWER_CTRL
 
- ULPD_POWER_CTRL_REG_VAL
 
- ULPD_REG_BASE
 
- ULPD_RESTORE
 
- ULPD_SAVE
 
- ULPD_SDW_CLK_DIV_CTRL_SEL
 
- ULPD_SETUP_ANALOG_CELL_3
 
- ULPD_SETUP_ANALOG_CELL_3_VAL
 
- ULPD_SHOW
 
- ULPD_SLEEP_SAVE_SIZE
 
- ULPD_SLEEP_SAVE_START
 
- ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL
 
- ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL
 
- ULPD_SLEEP_SAVE_ULPD_IT_STATUS
 
- ULPD_SLEEP_SAVE_ULPD_POWER_CTRL
 
- ULPD_SLEEP_SAVE_ULPD_SOFT_REQ
 
- ULPD_SLEEP_SAVE_ULPD_STATUS_REQ
 
- ULPD_SOFT_DISABLE_REQ_REG
 
- ULPD_SOFT_REQ
 
- ULPD_STATUS_REQ
 
- ULPI_12PIN
 
- ULPI_8PIN
 
- ULPI_ACCESS_EXTENDED
 
- ULPI_ADDR
 
- ULPI_CARKIT_CTRL
 
- ULPI_CARKIT_CTRL_CARKITPWR
 
- ULPI_CARKIT_CTRL_IDGNDDRV
 
- ULPI_CARKIT_CTRL_MICEN
 
- ULPI_CARKIT_CTRL_RXDEN
 
- ULPI_CARKIT_CTRL_SPKLEFTEN
 
- ULPI_CARKIT_CTRL_SPKRIGHTEN
 
- ULPI_CARKIT_CTRL_TXDEN
 
- ULPI_CARKIT_INT_CARINTDET
 
- ULPI_CARKIT_INT_DELAY
 
- ULPI_CARKIT_INT_DP
 
- ULPI_CARKIT_INT_EN
 
- ULPI_CARKIT_INT_EN_CARINTDET
 
- ULPI_CARKIT_INT_EN_DP_FALL
 
- ULPI_CARKIT_INT_EN_DP_RISE
 
- ULPI_CARKIT_INT_EN_IDFLOAT_FALL
 
- ULPI_CARKIT_INT_EN_IDFLOAT_RISE
 
- ULPI_CARKIT_INT_IDFLOAT
 
- ULPI_CARKIT_INT_LATCH
 
- ULPI_CARKIT_INT_STS
 
- ULPI_CARKIT_PLS_CTRL
 
- ULPI_CARKIT_PLS_CTRL_RXPLSEN
 
- ULPI_CARKIT_PLS_CTRL_SPKRLEFT_BIASEN
 
- ULPI_CARKIT_PLS_CTRL_SPKRRIGHT_BIASEN
 
- ULPI_CARKIT_PLS_CTRL_TXPLSEN
 
- ULPI_CLKOUT_PINMUX_BYP
 
- ULPI_CLR
 
- ULPI_DATA
 
- ULPI_DATA_TRIMMER_LOAD
 
- ULPI_DATA_TRIMMER_SEL
 
- ULPI_DEBUG
 
- ULPI_DEBUG_LINESTATE0
 
- ULPI_DEBUG_LINESTATE1
 
- ULPI_DIR
 
- ULPI_DIR_TRIMMER_LOAD
 
- ULPI_DIR_TRIMMER_SEL
 
- ULPI_EXT_VENDOR_SPECIFIC
 
- ULPI_FC_FS
 
- ULPI_FC_FS4LS
 
- ULPI_FC_HS
 
- ULPI_FC_LS
 
- ULPI_FC_OP_DIS_NRZI
 
- ULPI_FC_OP_NODRV
 
- ULPI_FC_OP_NORM
 
- ULPI_FC_OP_NSYNC_NEOP
 
- ULPI_FC_RST
 
- ULPI_FC_SUSPM
 
- ULPI_FC_TERMSEL
 
- ULPI_FUNC_CTRL
 
- ULPI_FUNC_CTRL_FS4LS
 
- ULPI_FUNC_CTRL_FULL_SPEED
 
- ULPI_FUNC_CTRL_HIGH_SPEED
 
- ULPI_FUNC_CTRL_LOW_SPEED
 
- ULPI_FUNC_CTRL_OPMODE
 
- ULPI_FUNC_CTRL_OPMODE_DISABLE_NRZI
 
- ULPI_FUNC_CTRL_OPMODE_MASK
 
- ULPI_FUNC_CTRL_OPMODE_NONDRIVING
 
- ULPI_FUNC_CTRL_OPMODE_NORMAL
 
- ULPI_FUNC_CTRL_OPMODE_NOSYNC_NOEOP
 
- ULPI_FUNC_CTRL_RESET
 
- ULPI_FUNC_CTRL_SUSPENDM
 
- ULPI_FUNC_CTRL_TERMSELECT
 
- ULPI_FUNC_CTRL_XCVRSEL
 
- ULPI_FUNC_CTRL_XCVRSEL_MASK
 
- ULPI_HSIC_CFG
 
- ULPI_HSIC_IO_CAL
 
- ULPI_I2C_CONFLICT_INTEN
 
- ULPI_IC_3PIN_SERIAL
 
- ULPI_IC_6PIN_SERIAL
 
- ULPI_IC_AUTORESUME
 
- ULPI_IC_CARKIT
 
- ULPI_IC_CLKSUSPM
 
- ULPI_IC_EXTVBUS_INDINV
 
- ULPI_IC_IND_PASSTHRU
 
- ULPI_IC_PROTECT_DIS
 
- ULPI_ID
 
- ULPI_IFC_CTRL
 
- ULPI_IFC_CTRL_3_PIN_SERIAL_MODE
 
- ULPI_IFC_CTRL_6_PIN_SERIAL_MODE
 
- ULPI_IFC_CTRL_AUTORESUME
 
- ULPI_IFC_CTRL_CARKITMODE
 
- ULPI_IFC_CTRL_CLOCKSUSPENDM
 
- ULPI_IFC_CTRL_EXTERNAL_VBUS
 
- ULPI_IFC_CTRL_PASSTHRU
 
- ULPI_IFC_CTRL_PROTECT_IFC_DISABLE
 
- ULPI_INFO
 
- ULPI_INT_EN
 
- ULPI_INT_HOST_DISCONNECT
 
- ULPI_INT_IDGRD
 
- ULPI_INT_SESS_END
 
- ULPI_INT_SESS_VALID
 
- ULPI_INT_VBUS_VALID
 
- ULPI_MISC_A
 
- ULPI_MISC_A_VBUSVLDEXT
 
- ULPI_MISC_A_VBUSVLDEXTSEL
 
- ULPI_NXT
 
- ULPI_OTG_CHRGVBUS
 
- ULPI_OTG_CTRL
 
- ULPI_OTG_CTRL_CHRGVBUS
 
- ULPI_OTG_CTRL_DISCHRGVBUS
 
- ULPI_OTG_CTRL_DM_PULLDOWN
 
- ULPI_OTG_CTRL_DP_PULLDOWN
 
- ULPI_OTG_CTRL_DRVVBUS
 
- ULPI_OTG_CTRL_DRVVBUS_EXT
 
- ULPI_OTG_CTRL_EXTVBUSIND
 
- ULPI_OTG_CTRL_ID_PULLUP
 
- ULPI_OTG_DISCHRGVBUS
 
- ULPI_OTG_DM_PULLDOWN_DIS
 
- ULPI_OTG_DP_PULLDOWN_DIS
 
- ULPI_OTG_DRVVBUS
 
- ULPI_OTG_DRVVBUS_EXT
 
- ULPI_OTG_EXTVBUSIND
 
- ULPI_OTG_ID_PULLUP
 
- ULPI_OUTPUT_PINMUX_BYP
 
- ULPI_PHY_CLK_SEL
 
- ULPI_PHY_ENABLE
 
- ULPI_POLARITY_RECOVERY
 
- ULPI_PRODUCT_ID_HIGH
 
- ULPI_PRODUCT_ID_LOW
 
- ULPI_PWR_CLK_MNG_REG
 
- ULPI_PWR_OTG_COMP_DISABLE
 
- ULPI_RUN
 
- ULPI_SCRATCH
 
- ULPI_SER_3PIN
 
- ULPI_SER_6PIN
 
- ULPI_SET
 
- ULPI_STP
 
- ULPI_STPDIRNXT_TRIMMER_LOAD
 
- ULPI_STPDIRNXT_TRIMMER_SEL
 
- ULPI_SYNC_STATE
 
- ULPI_TIMING_CTRL_0
 
- ULPI_TIMING_CTRL_1
 
- ULPI_TX_NEG_WIDTH
 
- ULPI_TX_POS_WIDTH
 
- ULPI_USB_INT_EN_FALL
 
- ULPI_USB_INT_EN_RISE
 
- ULPI_USB_INT_LATCH
 
- ULPI_USB_INT_STS
 
- ULPI_VENDOR_ID_HIGH
 
- ULPI_VENDOR_ID_LOW
 
- ULPI_VENDOR_SPECIFIC
 
- ULPI_VIEWPORT
 
- ULPI_VIEWPORT_OFFSET
 
- ULPI_VIEW_ADDR
 
- ULPI_VIEW_DATA_READ
 
- ULPI_VIEW_DATA_WRITE
 
- ULPI_VIEW_READ
 
- ULPI_VIEW_RUN
 
- ULPI_VIEW_WAKEUP
 
- ULPI_VIEW_WRITE
 
- ULPI_WAKEUP
 
- ULPI_WRITE
 
- ULPMEM_DSGL_MAX_NPPODS
 
- ULPMEM_IDATA_MAX_NPPODS
 
- ULPRX_INTR_MASK
 
- ULPRX_LA_SIZE
 
- ULPS_MASK
 
- ULPS_SEQUENCE
 
- ULPS_STATE_ENTER
 
- ULPS_STATE_EXIT
 
- ULPS_STATE_MASK
 
- ULPS_STATE_NORMAL_OPERATION
 
- ULPTX_CMD_M
 
- ULPTX_CMD_S
 
- ULPTX_CMD_V
 
- ULPTX_INTR_MASK
 
- ULPTX_LEN16_M
 
- ULPTX_LEN16_S
 
- ULPTX_LEN16_V
 
- ULPTX_MORE_F
 
- ULPTX_MORE_S
 
- ULPTX_MORE_V
 
- ULPTX_NSGE_G
 
- ULPTX_NSGE_M
 
- ULPTX_NSGE_S
 
- ULPTX_NSGE_V
 
- ULP_ACCEPT
 
- ULP_BDE_TUS
 
- ULP_BDL
 
- ULP_CRC_DATA
 
- ULP_CRC_HEADER
 
- ULP_CRYPTO_IPSEC_INLINE
 
- ULP_CRYPTO_LOOKASIDE
 
- ULP_ENABLE_SIZE
 
- ULP_F_CALL_PENDING
 
- ULP_F_INIT
 
- ULP_F_START
 
- ULP_ISCSI_GET_PARAMS
 
- ULP_ISCSI_SET_PARAMS
 
- ULP_MEMIO_ADDR_S
 
- ULP_MEMIO_ADDR_V
 
- ULP_MEMIO_DATA_LEN_S
 
- ULP_MEMIO_DATA_LEN_V
 
- ULP_MEMIO_LOCK_F
 
- ULP_MEMIO_LOCK_S
 
- ULP_MEMIO_LOCK_V
 
- ULP_MEMIO_ORDER_F
 
- ULP_MEMIO_ORDER_S
 
- ULP_MEMIO_ORDER_V
 
- ULP_MEM_READ
 
- ULP_MEM_WRITE
 
- ULP_MODE_FCOE
 
- ULP_MODE_ISCSI
 
- ULP_MODE_IWARP
 
- ULP_MODE_NONE
 
- ULP_MODE_RDMA
 
- ULP_MODE_S
 
- ULP_MODE_SSL
 
- ULP_MODE_TCPDDP
 
- ULP_MODE_TLS
 
- ULP_MODE_V
 
- ULP_PM_HSRUN
 
- ULP_PM_RUN
 
- ULP_PM_STOP
 
- ULP_PM_VLLS
 
- ULP_PM_VLPS
 
- ULP_PM_WAIT
 
- ULP_REJECT
 
- ULP_RX_CTX_BASE_A
 
- ULP_RX_F
 
- ULP_RX_INT_CAUSE_A
 
- ULP_RX_ISCSI_LLIMIT_A
 
- ULP_RX_ISCSI_PSZ_A
 
- ULP_RX_ISCSI_TAGMASK_A
 
- ULP_RX_ISCSI_ULIMIT_A
 
- ULP_RX_LA_CTL_A
 
- ULP_RX_LA_RDDATA_A
 
- ULP_RX_LA_RDPTR_A
 
- ULP_RX_LA_WRPTR_A
 
- ULP_RX_PBL_LLIMIT_A
 
- ULP_RX_PBL_ULIMIT_A
 
- ULP_RX_RQUDP_LLIMIT_A
 
- ULP_RX_RQUDP_ULIMIT_A
 
- ULP_RX_RQ_LLIMIT_A
 
- ULP_RX_RQ_ULIMIT_A
 
- ULP_RX_S
 
- ULP_RX_STAG_LLIMIT_A
 
- ULP_RX_STAG_ULIMIT_A
 
- ULP_RX_TDDP_LLIMIT_A
 
- ULP_RX_TDDP_PSZ_A
 
- ULP_RX_TDDP_ULIMIT_A
 
- ULP_RX_TLS_KEY_LLIMIT_A
 
- ULP_RX_TLS_KEY_ULIMIT_A
 
- ULP_RX_V
 
- ULP_SETUP_SIZE
 
- ULP_SKB_CB
 
- ULP_TXPKT
 
- ULP_TXPKT_CHANNELID_F
 
- ULP_TXPKT_CHANNELID_G
 
- ULP_TXPKT_CHANNELID_M
 
- ULP_TXPKT_CHANNELID_S
 
- ULP_TXPKT_CHANNELID_V
 
- ULP_TXPKT_DATAMODIFY_F
 
- ULP_TXPKT_DATAMODIFY_G
 
- ULP_TXPKT_DATAMODIFY_M
 
- ULP_TXPKT_DATAMODIFY_S
 
- ULP_TXPKT_DATAMODIFY_V
 
- ULP_TXPKT_DEST_M
 
- ULP_TXPKT_DEST_S
 
- ULP_TXPKT_DEST_V
 
- ULP_TXPKT_FID_M
 
- ULP_TXPKT_FID_S
 
- ULP_TXPKT_FID_V
 
- ULP_TXPKT_RO_F
 
- ULP_TXPKT_RO_S
 
- ULP_TXPKT_RO_V
 
- ULP_TX_ASIC_DEBUG_0_A
 
- ULP_TX_ASIC_DEBUG_1_A
 
- ULP_TX_ASIC_DEBUG_2_A
 
- ULP_TX_ASIC_DEBUG_3_A
 
- ULP_TX_ASIC_DEBUG_4_A
 
- ULP_TX_ASIC_DEBUG_CTRL_A
 
- ULP_TX_ERR_TABLE_BASE_A
 
- ULP_TX_F
 
- ULP_TX_INT_CAUSE_A
 
- ULP_TX_LA_RDDATA_0_A
 
- ULP_TX_LA_RDPTR_0_A
 
- ULP_TX_LA_WRPTR_0_A
 
- ULP_TX_MEM_READ
 
- ULP_TX_MEM_WRITE
 
- ULP_TX_PBL_LLIMIT_A
 
- ULP_TX_PBL_ULIMIT_A
 
- ULP_TX_PKT
 
- ULP_TX_S
 
- ULP_TX_SC_DSGL
 
- ULP_TX_SC_IMM
 
- ULP_TX_SC_ISGL
 
- ULP_TX_SC_MEMRD
 
- ULP_TX_SC_MORE_F
 
- ULP_TX_SC_MORE_S
 
- ULP_TX_SC_MORE_V
 
- ULP_TX_SC_NOOP
 
- ULP_TX_TPT_LLIMIT_A
 
- ULP_TX_TPT_ULIMIT_A
 
- ULP_TX_V
 
- ULTAUDIO_AHBFABRIC_CLK_SRC
 
- ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC
 
- ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC
 
- ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC
 
- ULTAUDIO_XO_CLK_SRC
 
- ULTRA
 
- ULTRA20M
 
- ULTRA20M_MODE
 
- ULTRA3_DO_PATCH
 
- ULTRA_CMDREG
 
- ULTRA_DMA_ENB
 
- ULTRA_DMA_TIMING_MASK
 
- ULTRA_DMA_TIMING_SHIFT
 
- ULTRA_FAST
 
- ULTRA_IO_EXTENT
 
- ULTRA_LOW_LATENCY_PCM_MODE
 
- ULTRA_MEMENB
 
- ULTRA_NIC_OFFSET
 
- ULTRA_RESET
 
- ULTRA_STRING_MAX_LEN
 
- ULTRA_SXFR
 
- ULT_SMPS_RANGE_SPLIT
 
- ULV_CLIENT_DCEFCLK_DPM_MASK
 
- ULV_CLIENT_GFXCLK_DPM_MASK
 
- ULV_CLIENT_JPEG_MASK
 
- ULV_CLIENT_MP0CLK_DPM_MASK
 
- ULV_CLIENT_RLC_MASK
 
- ULV_CLIENT_SDMA0_MASK
 
- ULV_CLIENT_SDMA1_MASK
 
- ULV_CLIENT_SOCCLK_DPM_MASK
 
- ULV_CLIENT_UCLK_DPM_MASK
 
- ULV_CLIENT_UVD_DPM_MASK
 
- ULV_CLIENT_UVD_MASK
 
- ULV_CLIENT_VCE_DPM_MASK
 
- ULV_CLIENT_VCE_MASK
 
- UL_DIGITS
 
- UL_DISABLE_HW_CG_CTL_MASK
 
- UL_DISABLE_HW_CG_CTL_MASK_SFT
 
- UL_DISABLE_HW_CG_CTL_SFT
 
- UL_FIFO_DIGMIC_TESTIN_MASK
 
- UL_FIFO_DIGMIC_TESTIN_MASK_SFT
 
- UL_FIFO_DIGMIC_TESTIN_SFT
 
- UL_FIFO_DIGMIC_WDATA_TESTEN_MASK
 
- UL_FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT
 
- UL_FIFO_DIGMIC_WDATA_TESTEN_SFT
 
- UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK
 
- UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK_SFT
 
- UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_SFT
 
- UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK
 
- UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT
 
- UL_FIFO_WCLK_6P5M_TESTCK_SEL_SFT
 
- UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK
 
- UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK_SFT
 
- UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_SFT
 
- UL_FIFO_WCLK_INV_MASK
 
- UL_FIFO_WCLK_INV_MASK_SFT
 
- UL_FIFO_WCLK_INV_SFT
 
- UL_FIFO_WDATA_TESTEN_MASK
 
- UL_FIFO_WDATA_TESTEN_MASK_SFT
 
- UL_FIFO_WDATA_TESTEN_SFT
 
- UL_FIFO_WDATA_TESTSRC_SEL_MASK
 
- UL_FIFO_WDATA_TESTSRC_SEL_MASK_SFT
 
- UL_FIFO_WDATA_TESTSRC_SEL_SFT
 
- UL_IIRMODE_CTL_MASK
 
- UL_IIRMODE_CTL_MASK_SFT
 
- UL_IIRMODE_CTL_SFT
 
- UL_IIR_ON_TMP_CTL_MASK
 
- UL_IIR_ON_TMP_CTL_MASK_SFT
 
- UL_IIR_ON_TMP_CTL_SFT
 
- UL_LOOP_BACK_MODE_CTL_MASK
 
- UL_LOOP_BACK_MODE_CTL_MASK_SFT
 
- UL_LOOP_BACK_MODE_CTL_SFT
 
- UL_MODE_3P25M_CH1_CTL_MASK
 
- UL_MODE_3P25M_CH1_CTL_MASK_SFT
 
- UL_MODE_3P25M_CH1_CTL_SFT
 
- UL_MODE_3P25M_CH2_CTL_MASK
 
- UL_MODE_3P25M_CH2_CTL_MASK_SFT
 
- UL_MODE_3P25M_CH2_CTL_SFT
 
- UL_SDM_3_LEVEL_CTL_MASK
 
- UL_SDM_3_LEVEL_CTL_MASK_SFT
 
- UL_SDM_3_LEVEL_CTL_SFT
 
- UL_SINE_ON_MASK
 
- UL_SINE_ON_MASK_SFT
 
- UL_SINE_ON_SFT
 
- UL_SRC_ON_TMP_CTL
 
- UL_SRC_ON_TMP_CTL_MASK
 
- UL_SRC_ON_TMP_CTL_MASK_SFT
 
- UL_SRC_ON_TMP_CTL_SFT
 
- UL_SRC_USE_CIC_OUT_CTL_MASK
 
- UL_SRC_USE_CIC_OUT_CTL_MASK_SFT
 
- UL_SRC_USE_CIC_OUT_CTL_SFT
 
- UL_VOICE_MODE_CH1_CH2_CTL_MASK
 
- UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT
 
- UL_VOICE_MODE_CH1_CH2_CTL_SFT
 
- ULi_ethtool_get_link_ksettings
 
- UM
 
- UMAC_CLK_20BW
 
- UMAC_CLK_40BW
 
- UMAC_CLK_40MHZ
 
- UMAC_CMD
 
- UMAC_COMMAND_CONFIG_REG_HD_ENA
 
- UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE
 
- UMAC_COMMAND_CONFIG_REG_LOOP_ENA
 
- UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK
 
- UMAC_COMMAND_CONFIG_REG_PAD_EN
 
- UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE
 
- UMAC_COMMAND_CONFIG_REG_PROMIS_EN
 
- UMAC_COMMAND_CONFIG_REG_RX_ENA
 
- UMAC_COMMAND_CONFIG_REG_SW_RESET
 
- UMAC_COMMAND_CONFIG_REG_TX_ENA
 
- UMAC_EEE_CTRL
 
- UMAC_EEE_LPI_TIMER
 
- UMAC_EEE_REF_COUNT
 
- UMAC_EEE_WAKE_TIMER
 
- UMAC_HD_BKP_CTRL
 
- UMAC_IRQ1_RX_INTR_MASK
 
- UMAC_IRQ1_RX_INTR_SHIFT
 
- UMAC_IRQ1_TX_INTR_MASK
 
- UMAC_IRQ_EPHY
 
- UMAC_IRQ_HFB_MM
 
- UMAC_IRQ_HFB_SM
 
- UMAC_IRQ_LINK_DOWN
 
- UMAC_IRQ_LINK_EVENT
 
- UMAC_IRQ_LINK_UP
 
- UMAC_IRQ_MDIO_DONE
 
- UMAC_IRQ_MDIO_ERROR
 
- UMAC_IRQ_MPD_R
 
- UMAC_IRQ_PHY_DET_F
 
- UMAC_IRQ_PHY_DET_R
 
- UMAC_IRQ_RBUF_OVERFLOW
 
- UMAC_IRQ_RXDMA_BDONE
 
- UMAC_IRQ_RXDMA_DONE
 
- UMAC_IRQ_RXDMA_MBDONE
 
- UMAC_IRQ_RXDMA_PDONE
 
- UMAC_IRQ_SCB
 
- UMAC_IRQ_TBUF_UNDERRUN
 
- UMAC_IRQ_TXDMA_BDONE
 
- UMAC_IRQ_TXDMA_DONE
 
- UMAC_IRQ_TXDMA_MBDONE
 
- UMAC_IRQ_TXDMA_PDONE
 
- UMAC_IRQ_UMAC
 
- UMAC_IRQ_UMAC_TSV
 
- UMAC_MAC0
 
- UMAC_MAC1
 
- UMAC_MAX_FRAME_LEN
 
- UMAC_MAX_MTU_SIZE
 
- UMAC_MDF_ADDR
 
- UMAC_MDF_CTRL
 
- UMAC_MDF_ERR_CNT
 
- UMAC_MDIO_CMD
 
- UMAC_MIB_CTRL
 
- UMAC_MIB_START
 
- UMAC_MIB_STAT_OFFSET
 
- UMAC_MODE
 
- UMAC_MPD_CTRL
 
- UMAC_MPD_PW_LS
 
- UMAC_MPD_PW_MS
 
- UMAC_PSW_LS
 
- UMAC_PSW_MS
 
- UMAC_RBUF_ERR_CNT_V1
 
- UMAC_RBUF_OVFL_CNT_V1
 
- UMAC_RD_WR
 
- UMAC_REG_COMMAND_CONFIG
 
- UMAC_REG_DBG_DWORD_ENABLE_K2_E5
 
- UMAC_REG_DBG_FORCE_FRAME_K2_E5
 
- UMAC_REG_DBG_FORCE_VALID_K2_E5
 
- UMAC_REG_DBG_SELECT_K2_E5
 
- UMAC_REG_DBG_SHIFT_K2_E5
 
- UMAC_REG_EEE_WAKE_TIMER
 
- UMAC_REG_IPG_HD_BKP_CNTL_BB_B0
 
- UMAC_REG_MAC_ADDR0
 
- UMAC_REG_MAC_ADDR1
 
- UMAC_REG_MAXFR
 
- UMAC_REG_UMAC_EEE_CTRL
 
- UMAC_SPEED_10
 
- UMAC_SPEED_100
 
- UMAC_SPEED_1000
 
- UMAC_SPEED_2500
 
- UMAC_TX_FLUSH
 
- UMAC_UMAC_EEE_CTRL_REG_EEE_EN
 
- UMAG_GEN_HW_IS_FPGA
 
- UMAG_GEN_HW_STATUS
 
- UMAG_SB_CPU_1_STATUS
 
- UMAG_SB_CPU_2_STATUS
 
- UMAL_CFG1
 
- UMAL_CFG1_CONFFLCTL
 
- UMAL_CFG1_CONFLPBK
 
- UMAL_CFG1_RESET
 
- UMAL_CFG1_RXENABLE
 
- UMAL_CFG1_RXFLOWCTL
 
- UMAL_CFG1_TXENABLE
 
- UMAL_CFG1_TXFLOWCTL
 
- UMAL_CFG2
 
- UMAL_CFG2_BYTEMODE
 
- UMAL_CFG2_CRCENABLE
 
- UMAL_CFG2_DEFPREAMBLEN
 
- UMAL_CFG2_FD100
 
- UMAL_CFG2_FD1000
 
- UMAL_CFG2_FULLDUPLEX
 
- UMAL_CFG2_HD100
 
- UMAL_CFG2_LENGTHCHECK
 
- UMAL_CFG2_MODEMASK
 
- UMAL_CFG2_NIBBLEMODE
 
- UMAL_CFG2_PADCRC
 
- UMAL_CFG2_PREAMBLENMASK
 
- UMAL_DESC_PACKETSIZE_EMPTY
 
- UMAL_DESC_PACKETSIZE_NONEMPTY
 
- UMAL_DESC_PACKETSIZE_SIZEMASK
 
- UMAL_DMAInterrupt
 
- UMAL_DMAIntrMask
 
- UMAL_DMAIntrMask_ENABLEHALFWORD
 
- UMAL_DMARxCtrl
 
- UMAL_DMARxDescriptor
 
- UMAL_DMARxStatus
 
- UMAL_DMATxCtrl
 
- UMAL_DMATxDescriptor
 
- UMAL_DMATxStatus
 
- UMAL_DMA_Enable
 
- UMAL_FIFOCFG0
 
- UMAL_FIFOCFG1
 
- UMAL_FIFOCFG2
 
- UMAL_FIFOCFG3
 
- UMAL_FIFOCFG4
 
- UMAL_FIFOCFG5
 
- UMAL_FIFORAM0
 
- UMAL_FIFORAM1
 
- UMAL_FIFORAM2
 
- UMAL_FIFORAM3
 
- UMAL_FIFORAM4
 
- UMAL_FIFORAM5
 
- UMAL_FIFORAM6
 
- UMAL_FIFORAM7
 
- UMAL_HALFDUPLEX
 
- UMAL_IFCTRL
 
- UMAL_IFCTRL_RESET
 
- UMAL_IFSTATUS
 
- UMAL_IPGIFG
 
- UMAL_MAXFRAME
 
- UMAL_MIIADDR
 
- UMAL_MIICFG
 
- UMAL_MIICFG_RESET
 
- UMAL_MIICMD
 
- UMAL_MIICMD_READ
 
- UMAL_MIICTRL
 
- UMAL_MIIIDCT
 
- UMAL_MIIIDCT_BUSY
 
- UMAL_MIIIDCT_NOTVALID
 
- UMAL_MIISTATUS
 
- UMAL_STADDR1
 
- UMAL_STADDR2
 
- UMAL_TESTREG
 
- UMASK_AUDIO_CONTROL
 
- UMA_MICRO_SEC_TIMEOUT
 
- UMC
 
- UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH
 
- UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH
 
- UMC60_UCODE_FUNC_ID_REINIT
 
- UMCCH0_0_EccCtrl__RdEccEn_MASK
 
- UMCCH0_0_EccCtrl__RdEccEn__SHIFT
 
- UMCCH0_0_EccCtrl__WrEccEn_MASK
 
- UMCCH0_0_EccCtrl__WrEccEn__SHIFT
 
- UMCCH0_0_EccErrCntSel__EccErrCntCsSel_MASK
 
- UMCCH0_0_EccErrCntSel__EccErrCntCsSel__SHIFT
 
- UMCCH0_0_EccErrCntSel__EccErrCntEn_MASK
 
- UMCCH0_0_EccErrCntSel__EccErrCntEn__SHIFT
 
- UMCCH0_0_EccErrCntSel__EccErrInt_MASK
 
- UMCCH0_0_EccErrCntSel__EccErrInt__SHIFT
 
- UMCCH0_0_EccErrCnt__EccErrCnt_MASK
 
- UMCCH0_0_EccErrCnt__EccErrCnt__SHIFT
 
- UMCCH0_0_UMC_CONFIG__DramReady_MASK
 
- UMCCH0_0_UMC_CONFIG__DramReady__SHIFT
 
- UMCCH0_0_UmcLocalCap__EccDis_MASK
 
- UMCCH0_0_UmcLocalCap__EccDis__SHIFT
 
- UMCCH_ADDR_CFG
 
- UMCCH_ADDR_MASK
 
- UMCCH_ADDR_MASK_SEC
 
- UMCCH_BASE_ADDR
 
- UMCCH_BASE_ADDR_SEC
 
- UMCCH_DIMM_CFG
 
- UMCCH_ECC_BAD_SYMBOL
 
- UMCCH_ECC_CTRL
 
- UMCCH_SDP_CTRL
 
- UMCCH_UMC_CAP
 
- UMCCH_UMC_CAP_HI
 
- UMCCH_UMC_CFG
 
- UMC_BASE__INST0_SEG0
 
- UMC_BASE__INST0_SEG1
 
- UMC_BASE__INST0_SEG2
 
- UMC_BASE__INST0_SEG3
 
- UMC_BASE__INST0_SEG4
 
- UMC_BASE__INST0_SEG5
 
- UMC_BASE__INST1_SEG0
 
- UMC_BASE__INST1_SEG1
 
- UMC_BASE__INST1_SEG2
 
- UMC_BASE__INST1_SEG3
 
- UMC_BASE__INST1_SEG4
 
- UMC_BASE__INST1_SEG5
 
- UMC_BASE__INST2_SEG0
 
- UMC_BASE__INST2_SEG1
 
- UMC_BASE__INST2_SEG2
 
- UMC_BASE__INST2_SEG3
 
- UMC_BASE__INST2_SEG4
 
- UMC_BASE__INST2_SEG5
 
- UMC_BASE__INST3_SEG0
 
- UMC_BASE__INST3_SEG1
 
- UMC_BASE__INST3_SEG2
 
- UMC_BASE__INST3_SEG3
 
- UMC_BASE__INST3_SEG4
 
- UMC_BASE__INST3_SEG5
 
- UMC_BASE__INST4_SEG0
 
- UMC_BASE__INST4_SEG1
 
- UMC_BASE__INST4_SEG2
 
- UMC_BASE__INST4_SEG3
 
- UMC_BASE__INST4_SEG4
 
- UMC_BASE__INST4_SEG5
 
- UMC_BASE__INST5_SEG0
 
- UMC_BASE__INST5_SEG1
 
- UMC_BASE__INST5_SEG2
 
- UMC_BASE__INST5_SEG3
 
- UMC_BASE__INST5_SEG4
 
- UMC_BASE__INST5_SEG5
 
- UMC_BASE__INST6_SEG0
 
- UMC_BASE__INST6_SEG1
 
- UMC_BASE__INST6_SEG2
 
- UMC_BASE__INST6_SEG3
 
- UMC_BASE__INST6_SEG4
 
- UMC_BASE__INST6_SEG5
 
- UMC_BASE__INST7_SEG0
 
- UMC_BASE__INST7_SEG1
 
- UMC_BASE__INST7_SEG2
 
- UMC_BASE__INST7_SEG3
 
- UMC_BASE__INST7_SEG4
 
- UMC_BASE__INST7_SEG5
 
- UMC_CAP_ID_WHCI_RC
 
- UMC_CAP_ID_WHCI_WUSB_HC
 
- UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE
 
- UMC_CONFIG__DISABLE_UCODE_CHKSTATUS
 
- UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE
 
- UMC_CONFIG__ENABLE_BANK_HARVESTING
 
- UMC_CONFIG__ENABLE_HBM_LANE_REPAIR
 
- UMC_CONFIG__ENABLE_PHY_REINIT
 
- UMC_DRIVE0
 
- UMC_DRIVE1
 
- UMC_DRIVE2
 
- UMC_DRIVE3
 
- UMC_ECC_CHIPKILL_CAP
 
- UMC_ECC_ENABLED
 
- UMC_ENABLED
 
- UMC_HWID
 
- UMC_HWIP
 
- UMC_SDP_INIT
 
- UMC_V6_1_CE_CNT_INIT
 
- UMC_V6_1_CE_CNT_MAX
 
- UMC_V6_1_CE_INT_THRESHOLD
 
- UMC_V6_1_CHANNEL_INSTANCE_NUM
 
- UMC_V6_1_HBM_MEMORY_CHANNEL_WIDTH
 
- UMC_V6_1_PER_CHANNEL_OFFSET
 
- UMC_V6_1_TOTAL_CHANNEL_NUM
 
- UMC_V6_1_UMC_INSTANCE_NUM
 
- UMH_DISABLED
 
- UMH_ENABLED
 
- UMH_FREEZING
 
- UMH_KILLABLE
 
- UMH_NO_WAIT
 
- UMH_WAIT_EXEC
 
- UMH_WAIT_PROC
 
- UMID_LEN
 
- UMIP_DUMMY_GDT_BASE
 
- UMIP_DUMMY_IDT_BASE
 
- UMIP_GDT_IDT_BASE_SIZE_32BIT
 
- UMIP_GDT_IDT_BASE_SIZE_64BIT
 
- UMIP_GDT_IDT_LIMIT_SIZE
 
- UMIP_INST_SGDT
 
- UMIP_INST_SIDT
 
- UMIP_INST_SLDT
 
- UMIP_INST_SMSW
 
- UMIP_INST_STR
 
- UMISC
 
- UMISC_ADDR
 
- UMISC_BAUD_RESET
 
- UMISC_BAUD_TEST
 
- UMISC_CLKSRC
 
- UMISC_FORCE_PERR
 
- UMISC_IRDA_EN
 
- UMISC_IRDA_LOOP
 
- UMISC_IR_TEST
 
- UMISC_LOOP
 
- UMISC_RTS
 
- UMISC_RTSCONT
 
- UMISC_RX_POL
 
- UMISC_TX_POL
 
- UML_DIR
 
- UML_LIB_PATH
 
- UML_LONGJMP
 
- UML_MCONSOLE_HELPTEXT
 
- UML_NET_VERSION
 
- UML_ROUND_UP
 
- UML_SETJMP
 
- UMN_IRQ
 
- UMOUNT_CONNECTED
 
- UMOUNT_DISCARD_TIMEOUT
 
- UMOUNT_NOFOLLOW
 
- UMOUNT_PROPAGATE
 
- UMOUNT_SYNC
 
- UMOUNT_UNUSED
 
- UMP3410
 
- UMP5152
 
- UMPC_CLOSE_PORT
 
- UMPC_COMPLETE_READ
 
- UMPC_COPY_DNLD_TO_I2C
 
- UMPC_HARDWARE_RESET
 
- UMPC_MEMORY_READ
 
- UMPC_MEMORY_WRITE
 
- UMPC_OPEN_PORT
 
- UMPC_PURGE_PORT
 
- UMPC_READ_MSR
 
- UMPC_READ_SFR
 
- UMPC_SET_CLR_BREAK
 
- UMPC_SET_CLR_DTR
 
- UMPC_SET_CLR_LOOPBACK
 
- UMPC_SET_CLR_RTS
 
- UMPC_SET_CONFIG
 
- UMPC_START_PORT
 
- UMPC_STOP_PORT
 
- UMPC_TEST_PORT
 
- UMPC_WRITE_SFR
 
- UMPD_OEDB1_ADDRESS
 
- UMPD_OEDB2_ADDRESS
 
- UMPMEM_BASE_UART1
 
- UMPMEM_BASE_UART2
 
- UMPMEM_OFFS_UART_LSR
 
- UMPM_UART1_PORT
 
- UMP_DMA_MODE_CONTINOUS
 
- UMP_MASK_UART_FLAGS_AUTO_START_ON_ERR
 
- UMP_MASK_UART_FLAGS_DTR_DISABLE
 
- UMP_MASK_UART_FLAGS_DTR_FLOW
 
- UMP_MASK_UART_FLAGS_IN_X
 
- UMP_MASK_UART_FLAGS_OUT_X
 
- UMP_MASK_UART_FLAGS_OUT_XA
 
- UMP_MASK_UART_FLAGS_OUT_X_CTS_FLOW
 
- UMP_MASK_UART_FLAGS_OUT_X_DSR_FLOW
 
- UMP_MASK_UART_FLAGS_PARITY
 
- UMP_MASK_UART_FLAGS_RECEIVE_MS_INT
 
- UMP_MASK_UART_FLAGS_RTS_DISABLE
 
- UMP_MASK_UART_FLAGS_RTS_FLOW
 
- UMP_PIPE_TRANSFER_MODE_MASK
 
- UMP_PIPE_TRANS_TIMEOUT_ENA
 
- UMP_PIPE_TRANS_TIMEOUT_MASK
 
- UMP_PORT_DIR_IN
 
- UMP_PORT_DIR_OUT
 
- UMP_UART_CHAR5BITS
 
- UMP_UART_CHAR6BITS
 
- UMP_UART_CHAR7BITS
 
- UMP_UART_CHAR8BITS
 
- UMP_UART_EVENPARITY
 
- UMP_UART_LSR_BR_MASK
 
- UMP_UART_LSR_DATA_MASK
 
- UMP_UART_LSR_ER_MASK
 
- UMP_UART_LSR_FE_MASK
 
- UMP_UART_LSR_OV_MASK
 
- UMP_UART_LSR_PE_MASK
 
- UMP_UART_LSR_RX_MASK
 
- UMP_UART_LSR_TX_MASK
 
- UMP_UART_MARKPARITY
 
- UMP_UART_NOPARITY
 
- UMP_UART_ODDPARITY
 
- UMP_UART_SPACEPARITY
 
- UMP_UART_STOPBIT1
 
- UMP_UART_STOPBIT15
 
- UMP_UART_STOPBIT2
 
- UMR_WQE_BULK
 
- UMUL_TIME
 
- UMWAIT_C02_ENABLE
 
- UMWAIT_CTRL_VAL
 
- UM_ETH_IRQ
 
- UM_FIXUP
 
- UM_FLAG_DMA_IN_REGS
 
- UM_FLAG_NO_BATT
 
- UM_FLAG_NO_BATTREG
 
- UM_FLAG_NO_BYTE_STATUS
 
- UM_KERN_ALERT
 
- UM_KERN_CONT
 
- UM_KERN_CRIT
 
- UM_KERN_DEBUG
 
- UM_KERN_EMERG
 
- UM_KERN_ERR
 
- UM_KERN_INFO
 
- UM_KERN_NOTICE
 
- UM_KERN_WARNING
 
- UM_SIGNAL
 
- UM_WARN
 
- UNALGN_ADDR
 
- UNALIGNED_ACTION_QUIET
 
- UNALIGNED_ACTION_SHOW
 
- UNALIGNED_ACTION_SIGNAL
 
- UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK
 
- UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_SHIFT
 
- UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK
 
- UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT
 
- UNALIGNED_OPAQUE_DATA_RESERVED_MASK
 
- UNALIGNED_OPAQUE_DATA_RESERVED_SHIFT
 
- UNALIGNED_USER_EXCEPTION
 
- UNAME26
 
- UNASSIGN
 
- UNASSIGNED_CELL_COUNT_OFF
 
- UNASSOC_D2H_FIS
 
- UNAT_OFF
 
- UNAUTHENTICATED
 
- UNAVAILABLE
 
- UNBIND_ST_FAILED
 
- UNBIND_ST_OK
 
- UNBIND_ST_USBIP_HOST
 
- UNBLANK
 
- UNBLOCK_CONTINUE
 
- UNBLOCK_CONTINUE_POST
 
- UNBLOCK_STOP_POST
 
- UNBOUND_POOL_HASH_ORDER
 
- UNBPM_AXIMST_LAST_CMD__AXI_MASTER_LAST_CMD_MASK
 
- UNBPM_AXIMST_LAST_CMD__AXI_MASTER_LAST_CMD__SHIFT
 
- UNBPM_CK_IRESET__CK_IRESET_LOCAL_MASK
 
- UNBPM_CK_IRESET__CK_IRESET_LOCAL__SHIFT
 
- UNBPM_DEBUG_BUS_CNTL__DEBUG_BUS_CYCLE_NUM_MASK
 
- UNBPM_DEBUG_BUS_CNTL__DEBUG_BUS_CYCLE_NUM__SHIFT
 
- UNBPM_DEBUG_BUS_CNTL__DEBUG_BUS_LOGGING_EN_MASK
 
- UNBPM_DEBUG_BUS_CNTL__DEBUG_BUS_LOGGING_EN__SHIFT
 
- UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_ACTIVE_MASK
 
- UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_ACTIVE__SHIFT
 
- UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_BUSY_MASK
 
- UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_BUSY__SHIFT
 
- UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_QOS_MASK
 
- UNBPM_DEBUG_CONFIG_STATUS__AXI_MASTER_QOS__SHIFT
 
- UNBPM_DEBUG_CONFIG_STATUS__FIFO_BUFF_FLUSH_MASK
 
- UNBPM_DEBUG_CONFIG_STATUS__FIFO_BUFF_FLUSH__SHIFT
 
- UNBPM_DEBUG_CONFIG_STATUS__FIFO_DATA_COUNT_MASK
 
- UNBPM_DEBUG_CONFIG_STATUS__FIFO_DATA_COUNT__SHIFT
 
- UNBPM_DEBUG_CONFIG_STATUS__MASTER_DEBUG_EN_MASK
 
- UNBPM_DEBUG_CONFIG_STATUS__MASTER_DEBUG_EN__SHIFT
 
- UNBPM_DEBUG_CONFIG_STATUS__MST_OUTSTANDING_TRANS_MASK
 
- UNBPM_DEBUG_CONFIG_STATUS__MST_OUTSTANDING_TRANS__SHIFT
 
- UNBPM_EXIT_TO_PSTATE__EXIT_TO_PSTATE_MASK
 
- UNBPM_EXIT_TO_PSTATE__EXIT_TO_PSTATE__SHIFT
 
- UNBPM_FUSES_VAL_PWROK__CK_FUSES_VAL_PWROK_MASK
 
- UNBPM_FUSES_VAL_PWROK__CK_FUSES_VAL_PWROK__SHIFT
 
- UNBPM_MSG_INT_CONFIG__MSG_REG_TARGET_ADDR_MASK
 
- UNBPM_MSG_INT_CONFIG__MSG_REG_TARGET_ADDR__SHIFT
 
- UNBPM_NBPWRMGT_CMD__DCT_SR_MAP_MASK
 
- UNBPM_NBPWRMGT_CMD__DCT_SR_MAP__SHIFT
 
- UNBPM_NBPWRMGT_CMD__OVERRIDE_PARAMS_MASK
 
- UNBPM_NBPWRMGT_CMD__OVERRIDE_PARAMS__SHIFT
 
- UNBPM_NBPWRMGT_CMD__RETURN_NB_ACK_MASK
 
- UNBPM_NBPWRMGT_CMD__RETURN_NB_ACK__SHIFT
 
- UNBPM_NBPWRMGT_CMD__SET_NB_LOW_POWER_MASK
 
- UNBPM_NBPWRMGT_CMD__SET_NB_LOW_POWER__SHIFT
 
- UNBPM_NBPWRMGT_CMD__SET_NB_STUTTER_MODE_MASK
 
- UNBPM_NBPWRMGT_CMD__SET_NB_STUTTER_MODE__SHIFT
 
- UNBPM_NBPWRMGT_CMD__TARGET_BLOCK_MASK
 
- UNBPM_NBPWRMGT_CMD__TARGET_BLOCK__SHIFT
 
- UNBPM_NBPWRMGT_CMD__TARGET_CMD_MASK
 
- UNBPM_NBPWRMGT_CMD__TARGET_CMD__SHIFT
 
- UNBPM_NBPWRMGT_FSM_CFG__DIS_AUTO_PWRGATE_ON_EXIT_MASK
 
- UNBPM_NBPWRMGT_FSM_CFG__DIS_AUTO_PWRGATE_ON_EXIT__SHIFT
 
- UNBPM_PWRCTRL_MISC__PWRGATEMASTERDIS_MASK
 
- UNBPM_PWRCTRL_MISC__PWRGATEMASTERDIS__SHIFT
 
- UNBPM_PWRMGT_ACK__ERROR_CODE_MASK
 
- UNBPM_PWRMGT_ACK__ERROR_CODE__SHIFT
 
- UNBPM_PWRMGT_ACK__REQUESTOR_CODE_MASK
 
- UNBPM_PWRMGT_ACK__REQUESTOR_CODE__SHIFT
 
- UNBPM_PWRMGT_ACK__REQUEST_ACK_MASK
 
- UNBPM_PWRMGT_ACK__REQUEST_ACK__SHIFT
 
- UNBPM_PWRMGT_ACK__REQUEST_NACK_MASK
 
- UNBPM_PWRMGT_ACK__REQUEST_NACK__SHIFT
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuNbFid_MASK
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuNbFid__SHIFT
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuPrbEn_MASK
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuPrbEn__SHIFT
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuPwrTog_MASK
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpuPwrTog__SHIFT
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpu_MASK
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqCpu__SHIFT
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqDct_MASK
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqDct__SHIFT
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqDid_MASK
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqDid__SHIFT
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqGateEn_MASK
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqGateEn__SHIFT
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNbMemPstate_MASK
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNbMemPstate__SHIFT
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNbPstateLo_MASK
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNbPstateLo__SHIFT
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNb_MASK
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqNb__SHIFT
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqPstateId_MASK
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqPstateId__SHIFT
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqPstate_MASK
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NB_PwrMgtReqPstate__SHIFT
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NbPwrMgtReqOutstanding_MASK
 
- UNBPM_PWRMGT_REQ_DBG_STATUS__NbPwrMgtReqOutstanding__SHIFT
 
- UNBPM_SCRATCH_0__DATA_MASK
 
- UNBPM_SCRATCH_0__DATA__SHIFT
 
- UNBPM_SCRATCH_1__DATA_MASK
 
- UNBPM_SCRATCH_1__DATA__SHIFT
 
- UNBPM_VIDCHG_REQ_DBG_STATUS__CK_VidChgBusy_MASK
 
- UNBPM_VIDCHG_REQ_DBG_STATUS__CK_VidChgBusy__SHIFT
 
- UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VSTime_MASK
 
- UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VSTime__SHIFT
 
- UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidChgRamp_MASK
 
- UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidChgRamp__SHIFT
 
- UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidChgZeroVid_MASK
 
- UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidChgZeroVid__SHIFT
 
- UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidPlane_MASK
 
- UNBPM_VIDCHG_REQ_DBG_STATUS__NB_VidPlane__SHIFT
 
- UNBPM_VIDCHG_REQ_DBG_STATUS__NB_Vid_MASK
 
- UNBPM_VIDCHG_REQ_DBG_STATUS__NB_Vid__SHIFT
 
- UNBPM_VOLTAGE_CNTL__VOLTAGE_EN_MASK
 
- UNBPM_VOLTAGE_CNTL__VOLTAGE_EN__SHIFT
 
- UNBPM_VOLTAGE_CNTL__VOLTAGE_LEVEL_MASK
 
- UNBPM_VOLTAGE_CNTL__VOLTAGE_LEVEL__SHIFT
 
- UNBPM_VOLTAGE_STATUS__VOLTAGE_CURRENT_LEVEL_MASK
 
- UNBPM_VOLTAGE_STATUS__VOLTAGE_CURRENT_LEVEL__SHIFT
 
- UNBPM_VOLTAGE_STATUS__VOLTAGE_STATUS_MASK
 
- UNBPM_VOLTAGE_STATUS__VOLTAGE_STATUS__SHIFT
 
- UNBPM_WARM_RESET_HS_STATUS__NB_CSTATE_ACTIVE_MASK
 
- UNBPM_WARM_RESET_HS_STATUS__NB_CSTATE_ACTIVE__SHIFT
 
- UNBPM_WARM_RESET_HS_STATUS__WARM_RESET_HS_DONE_MASK
 
- UNBPM_WARM_RESET_HS_STATUS__WARM_RESET_HS_DONE__SHIFT
 
- UNBR_LNB_13V
 
- UNBR_LNB_18V
 
- UNBR_LNB_MASK
 
- UNBR_LNB_OFF
 
- UNBUSY_THR_PCT
 
- UNB_IF_INTRGEN_LAST_SENT__GNBPM_LAST_DATA_SENT_MASK
 
- UNB_IF_INTRGEN_LAST_SENT__GNBPM_LAST_DATA_SENT__SHIFT
 
- UNB_IF_INTRGEN_LAST_SENT__SMUPM_LAST_DATA_SENT_MASK
 
- UNB_IF_INTRGEN_LAST_SENT__SMUPM_LAST_DATA_SENT__SHIFT
 
- UNCACHEABLE
 
- UNCACHEABLE_ADDR
 
- UNCACHED
 
- UNCACHED_ID
 
- UNCACHED_PHYS_0
 
- UNCACHED_PHYS_0_SIZE
 
- UNCACHED_RD
 
- UNCACHED_SHADOW_MASK
 
- UNCACHED_WR
 
- UNCAC_ADDR
 
- UNCAC_BASE
 
- UNCAPTURED_ERROR_F
 
- UNCAPTURED_ERROR_S
 
- UNCAPTURED_ERROR_V
 
- UNCHANGED
 
- UNCHECKED
 
- UNCO
 
- UNCONFIGURING
 
- UNCONFIRMED_NULLS_VAL
 
- UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS
 
- UNCORE_BOX_FLAG_CTL_OFFS8
 
- UNCORE_BOX_FLAG_INITIATED
 
- UNCORE_EVENT_CONSTRAINT
 
- UNCORE_EXTRA_PCI_DEV
 
- UNCORE_EXTRA_PCI_DEV_MAX
 
- UNCORE_FIXED_EVENT
 
- UNCORE_FREERUNNING_UMASK_START
 
- UNCORE_HAS_DBG_UNCLAIMED
 
- UNCORE_HAS_FIFO
 
- UNCORE_HAS_FORCEWAKE
 
- UNCORE_HAS_FPGA_DBG_UNCLAIMED
 
- UNCORE_PCI_DEV_DATA
 
- UNCORE_PCI_DEV_DEV
 
- UNCORE_PCI_DEV_FULL_DATA
 
- UNCORE_PCI_DEV_FUNC
 
- UNCORE_PCI_DEV_IDX
 
- UNCORE_PCI_DEV_TYPE
 
- UNCORE_PMC_IDX_FIXED
 
- UNCORE_PMC_IDX_FREERUNNING
 
- UNCORE_PMC_IDX_MAX
 
- UNCORE_PMC_IDX_MAX_FIXED
 
- UNCORE_PMC_IDX_MAX_FREERUNNING
 
- UNCORE_PMC_IDX_MAX_GENERIC
 
- UNCORE_PMU_HRTIMER_INTERVAL
 
- UNCORE_PMU_NAME_LEN
 
- UNCORE_SNB_IMC_HRTIMER_INTERVAL
 
- UNCOR_ECCERR
 
- UNDECID
 
- UNDEC_SM_PWDB
 
- UNDEF
 
- UNDEFFPINST
 
- UNDEFINED
 
- UNDEFINED_CAPABLE
 
- UNDEFINE_MRS_S
 
- UNDEFINE_MSR_S
 
- UNDEF_CONNID
 
- UNDEF_ERROR
 
- UNDEF_IRO
 
- UNDEF_REG
 
- UNDEF_TRACE_INCLUDE_FILE
 
- UNDEF_TRACE_INCLUDE_PATH
 
- UNDERFLOWEXCEPTION
 
- UNDERFLOW_MODE_RED
 
- UNDERFLOW_REPORT_ENABLE
 
- UNDERLAY_BRIGHTNESS_DEFAULT
 
- UNDERLAY_BRIGHTNESS_DIVIDER
 
- UNDERLAY_BRIGHTNESS_MAX
 
- UNDERLAY_BRIGHTNESS_MIN
 
- UNDERLAY_BRIGHTNESS_STEP
 
- UNDERLAY_CONTRAST_DEFAULT
 
- UNDERLAY_CONTRAST_DIVIDER
 
- UNDERLAY_CONTRAST_MAX
 
- UNDERLAY_CONTRAST_MIN
 
- UNDERLAY_CONTRAST_STEP
 
- UNDERLAY_HUE_DEFAULT
 
- UNDERLAY_HUE_DIVIDER
 
- UNDERLAY_HUE_MAX
 
- UNDERLAY_HUE_MIN
 
- UNDERLAY_HUE_STEP
 
- UNDERLAY_SATURATION_DEFAULT
 
- UNDERLAY_SATURATION_DIVIDER
 
- UNDERLAY_SATURATION_MAX
 
- UNDERLAY_SATURATION_MIN
 
- UNDERLAY_SATURATION_STEP
 
- UNDERRUN
 
- UNDERRUN_IE
 
- UNDERSCAN_AUTO
 
- UNDERSCAN_OFF
 
- UNDERSCAN_ON
 
- UNDERVOLTAGE_STICKY_BIT
 
- UNDER_RUN
 
- UNDO
 
- UNDOCK_EVENT
 
- UNDO_NOOP
 
- UNDO_SWITCH_STACK
 
- UND_MODE
 
- UNESCAPE_ANY
 
- UNESCAPE_HEX
 
- UNESCAPE_OCTAL
 
- UNESCAPE_SPACE
 
- UNESCAPE_SPECIAL
 
- UNEVEN_VISCHUNK
 
- UNEVEN_VISCHUNK_LAST
 
- UNEVICTABLE_BIT
 
- UNEVICTABLE_PGCLEARED
 
- UNEVICTABLE_PGCULLED
 
- UNEVICTABLE_PGMLOCKED
 
- UNEVICTABLE_PGMUNLOCKED
 
- UNEVICTABLE_PGRESCUED
 
- UNEVICTABLE_PGSCANNED
 
- UNEVICTABLE_PGSTRANDED
 
- UNEXPECTED_DISCONNECT
 
- UNEXP_SC
 
- UNEXP_XFER_RDY
 
- UNFLW_CTRL
 
- UNFM_P_SHIFT
 
- UNFM_P_SIZE
 
- UNGERMANN
 
- UNGERMANN_MAC_ID
 
- UNHANDLED_EXCEPTION
 
- UNICASERANGE
 
- UNICAST_ADDR
 
- UNICAST_ADDRESS
 
- UNICAST_LEARN_DISABLE
 
- UNICAST_LID_TYPE
 
- UNICAST_PATTERN
 
- UNICAST_PROMISCUOUS_MODE
 
- UNICAST_RETRIES
 
- UNICAST_TABLE
 
- UNICAST_VLAN_BOUNDARY
 
- UNICHROME_CLE266
 
- UNICHROME_CLE266_DID
 
- UNICHROME_CN700
 
- UNICHROME_CN700_DID
 
- UNICHROME_CN750
 
- UNICHROME_CN750_DID
 
- UNICHROME_CX700
 
- UNICHROME_CX700_DID
 
- UNICHROME_K400
 
- UNICHROME_K400_DID
 
- UNICHROME_K800
 
- UNICHROME_K800_DID
 
- UNICHROME_K8M890
 
- UNICHROME_K8M890_DID
 
- UNICHROME_P4M890
 
- UNICHROME_P4M890_DID
 
- UNICHROME_P4M900
 
- UNICHROME_P4M900_DID
 
- UNICHROME_PM800
 
- UNICHROME_PM800_DID
 
- UNICHROME_VX800
 
- UNICHROME_VX800_DID
 
- UNICHROME_VX855
 
- UNICHROME_VX855_DID
 
- UNICHROME_VX900
 
- UNICHROME_VX900_DID
 
- UNICODE_AGE
 
- UNICODE_DOT
 
- UNICODE_MAJ_MAX
 
- UNICODE_MAJ_SHIFT
 
- UNICODE_MAX
 
- UNICODE_MIN_MAX
 
- UNICODE_MIN_SHIFT
 
- UNICODE_NAME_MAX
 
- UNICODE_NULL
 
- UNICODE_REV_MAX
 
- UNIFB_MEMSIZE
 
- UNIFB_REGS_NUM
 
- UNIMAC_MDIO_DRV_NAME
 
- UNIMATCH
 
- UNIMPLEMENTED
 
- UNIMPLEMENTEDEXCEPTION
 
- UNIMPL_RBPAGE_ERR_MASK
 
- UNIMP_S_INSTRUCTION
 
- UNINIT
 
- UNINITIALISED_STATE
 
- UNINITIALIZED
 
- UNINITIALIZED_LUN
 
- UNINIT_PWR_MODE
 
- UNINIT_SLEEP_TIME
 
- UNINSTALL_NOTIFY_HANDLER
 
- UNION_WINDOW_A_B
 
- UNION_WINDOW_A_NOT_B
 
- UNION_WINDOW_NOT_A_B
 
- UNION_WINDOW_NOT_A_NOT_B
 
- UNIPERIF_ALLOWED_FRAME_SZ
 
- UNIPERIF_BIT_CONTROL_CHL_STS_UPDATE_MASK
 
- UNIPERIF_BIT_CONTROL_CHL_STS_UPDATE_SHIFT
 
- UNIPERIF_BIT_CONTROL_CLR_UNDERFLOW_DURATION_MASK
 
- UNIPERIF_BIT_CONTROL_CLR_UNDERFLOW_DURATION_SHIFT
 
- UNIPERIF_BIT_CONTROL_OFFSET
 
- UNIPERIF_CHANNEL_STA_REG0_OFFSET
 
- UNIPERIF_CHANNEL_STA_REG1_OFFSET
 
- UNIPERIF_CHANNEL_STA_REG2_OFFSET
 
- UNIPERIF_CHANNEL_STA_REG3_OFFSET
 
- UNIPERIF_CHANNEL_STA_REG4_OFFSET
 
- UNIPERIF_CHANNEL_STA_REG5_OFFSET
 
- UNIPERIF_CHANNEL_STA_REGN
 
- UNIPERIF_CONFIG_BACK_STALL_REQ_MASK
 
- UNIPERIF_CONFIG_BACK_STALL_REQ_SHIFT
 
- UNIPERIF_CONFIG_CHANNEL_STA_CNTR_MASK
 
- UNIPERIF_CONFIG_CHANNEL_STA_CNTR_SHIFT
 
- UNIPERIF_CONFIG_CHL_STS_UPDATE_MASK
 
- UNIPERIF_CONFIG_CHL_STS_UPDATE_SHIFT
 
- UNIPERIF_CONFIG_DMA_TRIG_LIMIT_MASK
 
- UNIPERIF_CONFIG_DMA_TRIG_LIMIT_SHIFT
 
- UNIPERIF_CONFIG_IDLE_MOD_MASK
 
- UNIPERIF_CONFIG_IDLE_MOD_SHIFT
 
- UNIPERIF_CONFIG_MEM_FMT_MASK
 
- UNIPERIF_CONFIG_MEM_FMT_SHIFT
 
- UNIPERIF_CONFIG_MSTR_CLKEDGE_MASK
 
- UNIPERIF_CONFIG_MSTR_CLKEDGE_SHIFT
 
- UNIPERIF_CONFIG_OFFSET
 
- UNIPERIF_CONFIG_ONE_BIT_AUD_MASK
 
- UNIPERIF_CONFIG_ONE_BIT_AUD_SHIFT
 
- UNIPERIF_CONFIG_PARITY_CNTR_MASK
 
- UNIPERIF_CONFIG_PARITY_CNTR_SHIFT
 
- UNIPERIF_CONFIG_REPEAT_CHL_STS_MASK
 
- UNIPERIF_CONFIG_REPEAT_CHL_STS_SHIFT
 
- UNIPERIF_CONFIG_SPDIF_SW_CTRL_MASK
 
- UNIPERIF_CONFIG_SPDIF_SW_CTRL_SHIFT
 
- UNIPERIF_CONFIG_SUBFRAME_SEL_MASK
 
- UNIPERIF_CONFIG_SUBFRAME_SEL_SHIFT
 
- UNIPERIF_CONFIG_USER_DAT_CNTR_MASK
 
- UNIPERIF_CONFIG_USER_DAT_CNTR_SHIFT
 
- UNIPERIF_CONFIG_VALIDITY_DAT_CNTR_MASK
 
- UNIPERIF_CONFIG_VALIDITY_DAT_CNTR_SHIFT
 
- UNIPERIF_CTRL_BYTE_SWP_MASK
 
- UNIPERIF_CTRL_BYTE_SWP_SHIFT
 
- UNIPERIF_CTRL_DIVIDER_MASK
 
- UNIPERIF_CTRL_DIVIDER_SHIFT
 
- UNIPERIF_CTRL_EXIT_STBY_ON_EOBLOCK_MASK
 
- UNIPERIF_CTRL_EXIT_STBY_ON_EOBLOCK_SHIFT
 
- UNIPERIF_CTRL_OFFSET
 
- UNIPERIF_CTRL_OPERATION_MASK
 
- UNIPERIF_CTRL_OPERATION_SHIFT
 
- UNIPERIF_CTRL_READER_OUT_SEL_MASK
 
- UNIPERIF_CTRL_READER_OUT_SEL_SHIFT
 
- UNIPERIF_CTRL_ROUNDING_MASK
 
- UNIPERIF_CTRL_ROUNDING_SHIFT
 
- UNIPERIF_CTRL_SPDIF_FMT_MASK
 
- UNIPERIF_CTRL_SPDIF_FMT_SHIFT
 
- UNIPERIF_CTRL_SPDIF_LAT_MASK
 
- UNIPERIF_CTRL_SPDIF_LAT_SHIFT
 
- UNIPERIF_CTRL_UNDERFLOW_REC_WINDOW_MASK
 
- UNIPERIF_CTRL_UNDERFLOW_REC_WINDOW_SHIFT
 
- UNIPERIF_CTRL_ZERO_STUFF_MASK
 
- UNIPERIF_CTRL_ZERO_STUFF_SHIFT
 
- UNIPERIF_DBG_STANDBY_LEFT_SP_MASK
 
- UNIPERIF_DBG_STANDBY_LEFT_SP_OFFSET
 
- UNIPERIF_DBG_STANDBY_LEFT_SP_SHIFT
 
- UNIPERIF_FIFO_DATA_OFFSET
 
- UNIPERIF_FIFO_FRAMES
 
- UNIPERIF_FIFO_SIZE
 
- UNIPERIF_I2S_FMT_ALIGN_MASK
 
- UNIPERIF_I2S_FMT_ALIGN_SHIFT
 
- UNIPERIF_I2S_FMT_DATA_SIZE_MASK
 
- UNIPERIF_I2S_FMT_DATA_SIZE_SHIFT
 
- UNIPERIF_I2S_FMT_LR_POL_MASK
 
- UNIPERIF_I2S_FMT_LR_POL_SHIFT
 
- UNIPERIF_I2S_FMT_NBIT_MASK
 
- UNIPERIF_I2S_FMT_NBIT_SHIFT
 
- UNIPERIF_I2S_FMT_NO_OF_SAMPLES_TO_READ_MASK
 
- UNIPERIF_I2S_FMT_NO_OF_SAMPLES_TO_READ_SHIFT
 
- UNIPERIF_I2S_FMT_NUM_CH_MASK
 
- UNIPERIF_I2S_FMT_NUM_CH_SHIFT
 
- UNIPERIF_I2S_FMT_OFFSET
 
- UNIPERIF_I2S_FMT_ORDER_MASK
 
- UNIPERIF_I2S_FMT_ORDER_SHIFT
 
- UNIPERIF_I2S_FMT_PADDING_MASK
 
- UNIPERIF_I2S_FMT_PADDING_SHIFT
 
- UNIPERIF_I2S_FMT_SCLK_EDGE_MASK
 
- UNIPERIF_I2S_FMT_SCLK_EDGE_SHIFT
 
- UNIPERIF_IEC958_ENCODING_MODE_ENCODED
 
- UNIPERIF_IEC958_ENCODING_MODE_PCM
 
- UNIPERIF_ITM_BCLR_DMA_ERROR_MASK
 
- UNIPERIF_ITM_BCLR_DMA_ERROR_SHIFT
 
- UNIPERIF_ITM_BCLR_FIFO_ERROR_MASK
 
- UNIPERIF_ITM_BCLR_FIFO_ERROR_SHIFT
 
- UNIPERIF_ITM_BCLR_OFFSET
 
- UNIPERIF_ITM_BSET_DMA_ERROR_MASK
 
- UNIPERIF_ITM_BSET_DMA_ERROR_SHIFT
 
- UNIPERIF_ITM_BSET_FIFO_ERROR_MASK
 
- UNIPERIF_ITM_BSET_FIFO_ERROR_SHIFT
 
- UNIPERIF_ITM_BSET_MEM_BLK_READ_MASK
 
- UNIPERIF_ITM_BSET_MEM_BLK_READ_SHIFT
 
- UNIPERIF_ITM_BSET_OFFSET
 
- UNIPERIF_ITM_BSET_UNDERFLOW_REC_DONE_MASK
 
- UNIPERIF_ITM_BSET_UNDERFLOW_REC_DONE_SHIFT
 
- UNIPERIF_ITM_BSET_UNDERFLOW_REC_FAILED_MASK
 
- UNIPERIF_ITM_BSET_UNDERFLOW_REC_FAILED_SHIFT
 
- UNIPERIF_ITM_FIFO_ERROR_MASK
 
- UNIPERIF_ITM_FIFO_ERROR_SHIFT
 
- UNIPERIF_ITM_OFFSET
 
- UNIPERIF_ITM_UNDERFLOW_REC_DONE_MASK
 
- UNIPERIF_ITM_UNDERFLOW_REC_DONE_SHIFT
 
- UNIPERIF_ITM_UNDERFLOW_REC_FAILED_MASK
 
- UNIPERIF_ITM_UNDERFLOW_REC_FAILED_SHIFT
 
- UNIPERIF_ITS_BCLR_FIFO_ERROR_MASK
 
- UNIPERIF_ITS_BCLR_FIFO_ERROR_SHIFT
 
- UNIPERIF_ITS_BCLR_OFFSET
 
- UNIPERIF_ITS_DMA_ERROR_MASK
 
- UNIPERIF_ITS_DMA_ERROR_SHIFT
 
- UNIPERIF_ITS_FIFO_ERROR_MASK
 
- UNIPERIF_ITS_FIFO_ERROR_SHIFT
 
- UNIPERIF_ITS_MEM_BLK_READ_MASK
 
- UNIPERIF_ITS_MEM_BLK_READ_SHIFT
 
- UNIPERIF_ITS_OFFSET
 
- UNIPERIF_ITS_UNDERFLOW_REC_DONE_MASK
 
- UNIPERIF_ITS_UNDERFLOW_REC_DONE_SHIFT
 
- UNIPERIF_ITS_UNDERFLOW_REC_FAILED_MASK
 
- UNIPERIF_ITS_UNDERFLOW_REC_FAILED_SHIFT
 
- UNIPERIF_MAX_FRAME_SZ
 
- UNIPERIF_PLAYER_CLK_ADJ_MAX
 
- UNIPERIF_PLAYER_CLK_ADJ_MIN
 
- UNIPERIF_PLAYER_I2S_OUT
 
- UNIPERIF_READER_I2S_IN
 
- UNIPERIF_SOFT_RST_OFFSET
 
- UNIPERIF_SOFT_RST_SOFT_RST_MASK
 
- UNIPERIF_SOFT_RST_SOFT_RST_SHIFT
 
- UNIPERIF_STATE_OVERFLOW
 
- UNIPERIF_STATE_STANDBY
 
- UNIPERIF_STATE_STARTED
 
- UNIPERIF_STATE_STOPPED
 
- UNIPERIF_STATE_UNDERFLOW
 
- UNIPERIF_STATE_XRUN
 
- UNIPERIF_STATUS_1_OFFSET
 
- UNIPERIF_STATUS_1_UNDERFLOW_DURATION_MASK
 
- UNIPERIF_STATUS_1_UNDERFLOW_DURATION_SHIFT
 
- UNIPERIF_TDM_ENABLE_EN_TDM_MASK
 
- UNIPERIF_TDM_ENABLE_EN_TDM_SHIFT
 
- UNIPERIF_TDM_ENABLE_OFFSET
 
- UNIPERIF_TDM_FS_REF_DIV_NUM_TIMESLOT_MASK
 
- UNIPERIF_TDM_FS_REF_DIV_NUM_TIMESLOT_SHIFT
 
- UNIPERIF_TDM_FS_REF_DIV_OFFSET
 
- UNIPERIF_TDM_FS_REF_FREQ_OFFSET
 
- UNIPERIF_TDM_FS_REF_FREQ_REF_FREQ_MASK
 
- UNIPERIF_TDM_FS_REF_FREQ_REF_FREQ_SHIFT
 
- UNIPERIF_TDM_WORD_POS_1_2_OFFSET
 
- UNIPERIF_TDM_WORD_POS_3_4_OFFSET
 
- UNIPERIF_TDM_WORD_POS_5_6_OFFSET
 
- UNIPERIF_TDM_WORD_POS_7_8_OFFSET
 
- UNIPERIF_TYPE_IS_HDMI
 
- UNIPERIF_TYPE_IS_IEC958
 
- UNIPERIF_TYPE_IS_PCM
 
- UNIPERIF_TYPE_IS_SPDIF
 
- UNIPERIF_TYPE_IS_TDM
 
- UNIPERIF_USER_VALIDITY_OFFSET
 
- UNIPERIF_USER_VALIDITY_VALIDITY_LR_MASK
 
- UNIPERIF_USER_VALIDITY_VALIDITY_LR_SHIFT
 
- UNIPHIER_AIDET_DETCONF
 
- UNIPHIER_AIDET_NR_IRQS
 
- UNIPHIER_CLK_CPUGEAR
 
- UNIPHIER_CLK_CPUGEAR_MAX_PARENTS
 
- UNIPHIER_CLK_CPUGEAR_SET
 
- UNIPHIER_CLK_CPUGEAR_STAT
 
- UNIPHIER_CLK_CPUGEAR_UPD
 
- UNIPHIER_CLK_CPUGEAR_UPD_BIT
 
- UNIPHIER_CLK_DIV
 
- UNIPHIER_CLK_DIV2
 
- UNIPHIER_CLK_DIV3
 
- UNIPHIER_CLK_DIV4
 
- UNIPHIER_CLK_FACTOR
 
- UNIPHIER_CLK_GATE
 
- UNIPHIER_CLK_MUX_MAX_PARENTS
 
- UNIPHIER_CLK_TYPE_CPUGEAR
 
- UNIPHIER_CLK_TYPE_FIXED_FACTOR
 
- UNIPHIER_CLK_TYPE_FIXED_RATE
 
- UNIPHIER_CLK_TYPE_GATE
 
- UNIPHIER_CLK_TYPE_MUX
 
- UNIPHIER_FI2C_BM
 
- UNIPHIER_FI2C_BM_SCLO
 
- UNIPHIER_FI2C_BM_SCLS
 
- UNIPHIER_FI2C_BM_SDAO
 
- UNIPHIER_FI2C_BM_SDAS
 
- UNIPHIER_FI2C_BRST
 
- UNIPHIER_FI2C_BRST_FOEN
 
- UNIPHIER_FI2C_BRST_RSCL
 
- UNIPHIER_FI2C_BYTE_WISE
 
- UNIPHIER_FI2C_CR
 
- UNIPHIER_FI2C_CR_MST
 
- UNIPHIER_FI2C_CR_NACK
 
- UNIPHIER_FI2C_CR_STA
 
- UNIPHIER_FI2C_CR_STO
 
- UNIPHIER_FI2C_CYC
 
- UNIPHIER_FI2C_DEFAULT_SPEED
 
- UNIPHIER_FI2C_DEFER_STOP_COMP
 
- UNIPHIER_FI2C_DSUT
 
- UNIPHIER_FI2C_DTRX
 
- UNIPHIER_FI2C_DTTX
 
- UNIPHIER_FI2C_DTTX_CMD
 
- UNIPHIER_FI2C_DTTX_RD
 
- UNIPHIER_FI2C_FIFO_SIZE
 
- UNIPHIER_FI2C_IC
 
- UNIPHIER_FI2C_IE
 
- UNIPHIER_FI2C_INT
 
- UNIPHIER_FI2C_INT_AL
 
- UNIPHIER_FI2C_INT_FAULTS
 
- UNIPHIER_FI2C_INT_NA
 
- UNIPHIER_FI2C_INT_RB
 
- UNIPHIER_FI2C_INT_RC
 
- UNIPHIER_FI2C_INT_RF
 
- UNIPHIER_FI2C_INT_STOP
 
- UNIPHIER_FI2C_INT_TB
 
- UNIPHIER_FI2C_INT_TC
 
- UNIPHIER_FI2C_INT_TE
 
- UNIPHIER_FI2C_LCTL
 
- UNIPHIER_FI2C_MANUAL_NACK
 
- UNIPHIER_FI2C_MAX_SPEED
 
- UNIPHIER_FI2C_NOISE
 
- UNIPHIER_FI2C_RBC
 
- UNIPHIER_FI2C_RBCM
 
- UNIPHIER_FI2C_RD
 
- UNIPHIER_FI2C_RST
 
- UNIPHIER_FI2C_RST_RBRST
 
- UNIPHIER_FI2C_RST_RST
 
- UNIPHIER_FI2C_RST_TBRST
 
- UNIPHIER_FI2C_SLAD
 
- UNIPHIER_FI2C_SR
 
- UNIPHIER_FI2C_SR_BB
 
- UNIPHIER_FI2C_SR_DB
 
- UNIPHIER_FI2C_SR_RFF
 
- UNIPHIER_FI2C_SR_RNE
 
- UNIPHIER_FI2C_SR_STS
 
- UNIPHIER_FI2C_SR_TFE
 
- UNIPHIER_FI2C_SR_TNF
 
- UNIPHIER_FI2C_SSUT
 
- UNIPHIER_FI2C_STOP
 
- UNIPHIER_FI2C_TBC
 
- UNIPHIER_FI2C_TBCM
 
- UNIPHIER_GPIO_BANK_MASK
 
- UNIPHIER_GPIO_IRQ
 
- UNIPHIER_GPIO_IRQ_EN
 
- UNIPHIER_GPIO_IRQ_FLT_CYC
 
- UNIPHIER_GPIO_IRQ_FLT_EN
 
- UNIPHIER_GPIO_IRQ_MAX_NUM
 
- UNIPHIER_GPIO_IRQ_MODE
 
- UNIPHIER_GPIO_IRQ_OFFSET
 
- UNIPHIER_GPIO_LINES_PER_BANK
 
- UNIPHIER_GPIO_PORT
 
- UNIPHIER_GPIO_PORT_DATA
 
- UNIPHIER_GPIO_PORT_DIR
 
- UNIPHIER_I2C_BRST
 
- UNIPHIER_I2C_BRST_FOEN
 
- UNIPHIER_I2C_BRST_RSCL
 
- UNIPHIER_I2C_BSTS
 
- UNIPHIER_I2C_BSTS_SCL
 
- UNIPHIER_I2C_BSTS_SDA
 
- UNIPHIER_I2C_CLK
 
- UNIPHIER_I2C_DEFAULT_SPEED
 
- UNIPHIER_I2C_DREC
 
- UNIPHIER_I2C_DREC_BBN
 
- UNIPHIER_I2C_DREC_LAB
 
- UNIPHIER_I2C_DREC_LRB
 
- UNIPHIER_I2C_DREC_MST
 
- UNIPHIER_I2C_DREC_STS
 
- UNIPHIER_I2C_DREC_TX
 
- UNIPHIER_I2C_DTRM
 
- UNIPHIER_I2C_DTRM_IRQEN
 
- UNIPHIER_I2C_DTRM_NACK
 
- UNIPHIER_I2C_DTRM_RD
 
- UNIPHIER_I2C_DTRM_STA
 
- UNIPHIER_I2C_DTRM_STO
 
- UNIPHIER_I2C_HOLD
 
- UNIPHIER_I2C_MAX_SPEED
 
- UNIPHIER_I2C_MYAD
 
- UNIPHIER_I2C_NOISE
 
- UNIPHIER_I2C_SETUP
 
- UNIPHIER_LD11_SYS_CLK_AIO
 
- UNIPHIER_LD11_SYS_CLK_EMMC
 
- UNIPHIER_LD11_SYS_CLK_ETHER
 
- UNIPHIER_LD11_SYS_CLK_EVEA
 
- UNIPHIER_LD11_SYS_CLK_EXIV
 
- UNIPHIER_LD11_SYS_CLK_HSC
 
- UNIPHIER_LD11_SYS_CLK_NAND
 
- UNIPHIER_LD11_SYS_CLK_STDMAC
 
- UNIPHIER_LD20_SYS_CLK_SD
 
- UNIPHIER_LD4_SYS_CLK_NAND
 
- UNIPHIER_LD4_SYS_CLK_SD
 
- UNIPHIER_LD4_SYS_CLK_STDMAC
 
- UNIPHIER_MDMAC_CH_DEST_ADDR
 
- UNIPHIER_MDMAC_CH_DEST_MODE
 
- UNIPHIER_MDMAC_CH_IRQ_DET
 
- UNIPHIER_MDMAC_CH_IRQ_EN
 
- UNIPHIER_MDMAC_CH_IRQ_REQ
 
- UNIPHIER_MDMAC_CH_IRQ_STAT
 
- UNIPHIER_MDMAC_CH_IRQ__ABORT
 
- UNIPHIER_MDMAC_CH_IRQ__DONE
 
- UNIPHIER_MDMAC_CH_MODE__ADDR_DEC
 
- UNIPHIER_MDMAC_CH_MODE__ADDR_FIXED
 
- UNIPHIER_MDMAC_CH_MODE__ADDR_INC
 
- UNIPHIER_MDMAC_CH_OFFSET
 
- UNIPHIER_MDMAC_CH_SIZE
 
- UNIPHIER_MDMAC_CH_SRC_ADDR
 
- UNIPHIER_MDMAC_CH_SRC_MODE
 
- UNIPHIER_MDMAC_CH_STRIDE
 
- UNIPHIER_MDMAC_CMD
 
- UNIPHIER_MDMAC_CMD_ABORT
 
- UNIPHIER_MDMAC_SLAVE_BUSWIDTHS
 
- UNIPHIER_MIO_CLK_SD
 
- UNIPHIER_MIO_CLK_SD_FIXED
 
- UNIPHIER_MIO_CLK_USB2
 
- UNIPHIER_MIO_CLK_USB2_PHY
 
- UNIPHIER_MIO_RESET_DMAC
 
- UNIPHIER_MIO_RESET_EMMC_HW_RESET
 
- UNIPHIER_MIO_RESET_SD
 
- UNIPHIER_MIO_RESET_SD_BRIDGE
 
- UNIPHIER_MIO_RESET_USB2
 
- UNIPHIER_MIO_RESET_USB2_BRIDGE
 
- UNIPHIER_PERI_CLK_FI2C
 
- UNIPHIER_PERI_CLK_I2C
 
- UNIPHIER_PERI_CLK_I2C_COMMON
 
- UNIPHIER_PERI_CLK_MCSSI
 
- UNIPHIER_PERI_CLK_SCSSI
 
- UNIPHIER_PERI_CLK_UART
 
- UNIPHIER_PERI_RESET_FI2C
 
- UNIPHIER_PERI_RESET_I2C
 
- UNIPHIER_PERI_RESET_MCSSI
 
- UNIPHIER_PERI_RESET_SCSSI
 
- UNIPHIER_PERI_RESET_UART
 
- UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE
 
- UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL
 
- UNIPHIER_PINCTRL_DRV2CTRL_BASE
 
- UNIPHIER_PINCTRL_DRV3CTRL_BASE
 
- UNIPHIER_PINCTRL_DRVCTRL_BASE
 
- UNIPHIER_PINCTRL_GROUP
 
- UNIPHIER_PINCTRL_GROUP_GPIO
 
- UNIPHIER_PINCTRL_IECTRL_BASE
 
- UNIPHIER_PINCTRL_LOAD_PINMUX
 
- UNIPHIER_PINCTRL_PIN
 
- UNIPHIER_PINCTRL_PINMUX_BASE
 
- UNIPHIER_PINCTRL_PUPDCTRL_BASE
 
- UNIPHIER_PINMUX_FUNCTION
 
- UNIPHIER_PIN_ATTR_PACKED
 
- UNIPHIER_PIN_DRVCTRL
 
- UNIPHIER_PIN_DRVCTRL_BITS
 
- UNIPHIER_PIN_DRVCTRL_MASK
 
- UNIPHIER_PIN_DRVCTRL_SHIFT
 
- UNIPHIER_PIN_DRV_1BIT
 
- UNIPHIER_PIN_DRV_2BIT
 
- UNIPHIER_PIN_DRV_3BIT
 
- UNIPHIER_PIN_DRV_FIXED4
 
- UNIPHIER_PIN_DRV_FIXED5
 
- UNIPHIER_PIN_DRV_FIXED8
 
- UNIPHIER_PIN_DRV_NONE
 
- UNIPHIER_PIN_DRV_TYPE
 
- UNIPHIER_PIN_DRV_TYPE_BITS
 
- UNIPHIER_PIN_DRV_TYPE_MASK
 
- UNIPHIER_PIN_DRV_TYPE_SHIFT
 
- UNIPHIER_PIN_IECTRL
 
- UNIPHIER_PIN_IECTRL_BITS
 
- UNIPHIER_PIN_IECTRL_EXIST
 
- UNIPHIER_PIN_IECTRL_MASK
 
- UNIPHIER_PIN_IECTRL_NONE
 
- UNIPHIER_PIN_IECTRL_SHIFT
 
- UNIPHIER_PIN_PULL_DIR
 
- UNIPHIER_PIN_PULL_DIR_BITS
 
- UNIPHIER_PIN_PULL_DIR_MASK
 
- UNIPHIER_PIN_PULL_DIR_SHIFT
 
- UNIPHIER_PIN_PULL_DOWN
 
- UNIPHIER_PIN_PULL_DOWN_FIXED
 
- UNIPHIER_PIN_PULL_NONE
 
- UNIPHIER_PIN_PULL_UP
 
- UNIPHIER_PIN_PULL_UP_FIXED
 
- UNIPHIER_PIN_PUPDCTRL
 
- UNIPHIER_PIN_PUPDCTRL_BITS
 
- UNIPHIER_PIN_PUPDCTRL_MASK
 
- UNIPHIER_PIN_PUPDCTRL_SHIFT
 
- UNIPHIER_PRO4_SYS_CLK_AIO
 
- UNIPHIER_PRO4_SYS_CLK_ETHER
 
- UNIPHIER_PRO4_SYS_CLK_GIO
 
- UNIPHIER_PRO4_SYS_CLK_USB3
 
- UNIPHIER_PRO5_SYS_CLK_AIO
 
- UNIPHIER_PRO5_SYS_CLK_NAND
 
- UNIPHIER_PRO5_SYS_CLK_SD
 
- UNIPHIER_RESET
 
- UNIPHIER_RESETX
 
- UNIPHIER_RESET_ACTIVE_LOW
 
- UNIPHIER_RESET_END
 
- UNIPHIER_RESET_ID_END
 
- UNIPHIER_SBC_BASE
 
- UNIPHIER_SBC_BASE_BE
 
- UNIPHIER_SBC_BASE_DUMMY
 
- UNIPHIER_SBC_CTRL0
 
- UNIPHIER_SBC_CTRL1
 
- UNIPHIER_SBC_CTRL2
 
- UNIPHIER_SBC_CTRL3
 
- UNIPHIER_SBC_CTRL4
 
- UNIPHIER_SBC_NR_BANKS
 
- UNIPHIER_SBC_STRIDE
 
- UNIPHIER_SD_CAP_BROKEN_DMA_RX
 
- UNIPHIER_SD_CAP_EXTENDED_IP
 
- UNIPHIER_SD_CC_EXT_MODE
 
- UNIPHIER_SD_CC_EXT_MODE_DMA
 
- UNIPHIER_SD_CLKCTL_OFFEN
 
- UNIPHIER_SD_CLK_CTL_DIV1
 
- UNIPHIER_SD_CLK_CTL_DIV1024
 
- UNIPHIER_SD_DMA_ADDR_H
 
- UNIPHIER_SD_DMA_ADDR_L
 
- UNIPHIER_SD_DMA_CTL
 
- UNIPHIER_SD_DMA_CTL_START
 
- UNIPHIER_SD_DMA_MODE
 
- UNIPHIER_SD_DMA_MODE_ADDR_INC
 
- UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV
 
- UNIPHIER_SD_DMA_MODE_DIR_MASK
 
- UNIPHIER_SD_DMA_MODE_DIR_TO_DEV
 
- UNIPHIER_SD_DMA_MODE_WIDTH_16
 
- UNIPHIER_SD_DMA_MODE_WIDTH_32
 
- UNIPHIER_SD_DMA_MODE_WIDTH_64
 
- UNIPHIER_SD_DMA_MODE_WIDTH_8
 
- UNIPHIER_SD_DMA_MODE_WIDTH_MASK
 
- UNIPHIER_SD_DMA_RST
 
- UNIPHIER_SD_DMA_RST_CH0
 
- UNIPHIER_SD_DMA_RST_CH1
 
- UNIPHIER_SD_HOST_MODE
 
- UNIPHIER_SD_VOLT
 
- UNIPHIER_SD_VOLT_180
 
- UNIPHIER_SD_VOLT_330
 
- UNIPHIER_SD_VOLT_MASK
 
- UNIPHIER_SD_VOLT_OFF
 
- UNIPHIER_SSCC
 
- UNIPHIER_SSCC_ACT
 
- UNIPHIER_SSCC_BST
 
- UNIPHIER_SSCC_ON
 
- UNIPHIER_SSCC_PRD
 
- UNIPHIER_SSCC_WTG
 
- UNIPHIER_SSCID
 
- UNIPHIER_SSCLPDAWCR
 
- UNIPHIER_SSCLPIAWCR
 
- UNIPHIER_SSCOLPQS
 
- UNIPHIER_SSCOLPQS_EF
 
- UNIPHIER_SSCOLPQS_EST
 
- UNIPHIER_SSCOLPQS_QST
 
- UNIPHIER_SSCOPE
 
- UNIPHIER_SSCOPE_CM_CLEAN
 
- UNIPHIER_SSCOPE_CM_FLUSH
 
- UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH
 
- UNIPHIER_SSCOPE_CM_INV
 
- UNIPHIER_SSCOPE_CM_SYNC
 
- UNIPHIER_SSCOPPQSEF
 
- UNIPHIER_SSCOPPQSEF_FE
 
- UNIPHIER_SSCOPPQSEF_OE
 
- UNIPHIER_SSCOQAD
 
- UNIPHIER_SSCOQM
 
- UNIPHIER_SSCOQM_CE
 
- UNIPHIER_SSCOQM_CM_CLEAN
 
- UNIPHIER_SSCOQM_CM_FLUSH
 
- UNIPHIER_SSCOQM_CM_INV
 
- UNIPHIER_SSCOQM_S_ALL
 
- UNIPHIER_SSCOQM_S_IS_RANGE
 
- UNIPHIER_SSCOQM_S_MASK
 
- UNIPHIER_SSCOQM_S_RANGE
 
- UNIPHIER_SSCOQSZ
 
- UNIPHIER_SYS_CLK_NAND_4X
 
- UNIPHIER_UART_CHAR_FCR
 
- UNIPHIER_UART_DLR
 
- UNIPHIER_UART_LCR_MCR
 
- UNIPHIER_UART_REGSHIFT
 
- UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN_MASK
 
- UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN__SHIFT
 
- UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN_MASK
 
- UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN__SHIFT
 
- UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL_MASK
 
- UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL__SHIFT
 
- UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED_MASK
 
- UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED__SHIFT
 
- UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK
 
- UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT
 
- UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK
 
- UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT
 
- UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK
 
- UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT
 
- UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK
 
- UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT
 
- UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK
 
- UNIPHYA_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT
 
- UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK
 
- UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT
 
- UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK
 
- UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT
 
- UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK
 
- UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT
 
- UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK
 
- UNIPHYA_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT
 
- UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK
 
- UNIPHYA_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT
 
- UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK
 
- UNIPHYA_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT
 
- UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK
 
- UNIPHYA_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT
 
- UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG_MASK
 
- UNIPHYA_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT
 
- UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK
 
- UNIPHYA_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT
 
- UNIPHYA_PRESENT
 
- UNIPHYA_PRESENT__1
 
- UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK
 
- UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT
 
- UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK
 
- UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT
 
- UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK
 
- UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT
 
- UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK
 
- UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT
 
- UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK
 
- UNIPHYB_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT
 
- UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK
 
- UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT
 
- UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK
 
- UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT
 
- UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK
 
- UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT
 
- UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK
 
- UNIPHYB_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT
 
- UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK
 
- UNIPHYB_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT
 
- UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK
 
- UNIPHYB_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT
 
- UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK
 
- UNIPHYB_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT
 
- UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG_MASK
 
- UNIPHYB_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT
 
- UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK
 
- UNIPHYB_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT
 
- UNIPHYB_PRESENT
 
- UNIPHYB_PRESENT__1
 
- UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN_MASK
 
- UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN__SHIFT
 
- UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN_MASK
 
- UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN__SHIFT
 
- UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL_MASK
 
- UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL__SHIFT
 
- UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED_MASK
 
- UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED__SHIFT
 
- UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK
 
- UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT
 
- UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK
 
- UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT
 
- UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK
 
- UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT
 
- UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK
 
- UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT
 
- UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK
 
- UNIPHYC_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT
 
- UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK
 
- UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT
 
- UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK
 
- UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT
 
- UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK
 
- UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT
 
- UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK
 
- UNIPHYC_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT
 
- UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK
 
- UNIPHYC_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT
 
- UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK
 
- UNIPHYC_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT
 
- UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK
 
- UNIPHYC_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT
 
- UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG_MASK
 
- UNIPHYC_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT
 
- UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK
 
- UNIPHYC_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT
 
- UNIPHYC_PRESENT
 
- UNIPHYC_PRESENT__1
 
- UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK
 
- UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT
 
- UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK
 
- UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT
 
- UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK
 
- UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT
 
- UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK
 
- UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT
 
- UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK
 
- UNIPHYD_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT
 
- UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK
 
- UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT
 
- UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK
 
- UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT
 
- UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK
 
- UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT
 
- UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK
 
- UNIPHYD_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT
 
- UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK
 
- UNIPHYD_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT
 
- UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK
 
- UNIPHYD_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT
 
- UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK
 
- UNIPHYD_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT
 
- UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG_MASK
 
- UNIPHYD_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT
 
- UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK
 
- UNIPHYD_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT
 
- UNIPHYD_PRESENT
 
- UNIPHYD_PRESENT__1
 
- UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN_MASK
 
- UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN__SHIFT
 
- UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN_MASK
 
- UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN__SHIFT
 
- UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL_MASK
 
- UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL__SHIFT
 
- UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED_MASK
 
- UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED__SHIFT
 
- UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK
 
- UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT
 
- UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK
 
- UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT
 
- UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK
 
- UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT
 
- UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK
 
- UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT
 
- UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK
 
- UNIPHYE_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT
 
- UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK
 
- UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT
 
- UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK
 
- UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT
 
- UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK
 
- UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT
 
- UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK
 
- UNIPHYE_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT
 
- UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK
 
- UNIPHYE_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT
 
- UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK
 
- UNIPHYE_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT
 
- UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK
 
- UNIPHYE_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT
 
- UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG_MASK
 
- UNIPHYE_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT
 
- UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK
 
- UNIPHYE_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT
 
- UNIPHYE_PRESENT
 
- UNIPHYE_PRESENT__0
 
- UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK
 
- UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT
 
- UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK
 
- UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT
 
- UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK
 
- UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT
 
- UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK
 
- UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT
 
- UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK
 
- UNIPHYF_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT
 
- UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK
 
- UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT
 
- UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK
 
- UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT
 
- UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK
 
- UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT
 
- UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK
 
- UNIPHYF_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT
 
- UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK
 
- UNIPHYF_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT
 
- UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK
 
- UNIPHYF_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT
 
- UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK
 
- UNIPHYF_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT
 
- UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG_MASK
 
- UNIPHYF_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT
 
- UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK
 
- UNIPHYF_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT
 
- UNIPHYF_PRESENT
 
- UNIPHYF_PRESENT__0
 
- UNIPHYGH_TPG_CONTROL__UNIPHYGH_STATIC_TEST_PATTERN_MASK
 
- UNIPHYGH_TPG_CONTROL__UNIPHYGH_STATIC_TEST_PATTERN__SHIFT
 
- UNIPHYGH_TPG_CONTROL__UNIPHYGH_TPG_EN_MASK
 
- UNIPHYGH_TPG_CONTROL__UNIPHYGH_TPG_EN__SHIFT
 
- UNIPHYGH_TPG_CONTROL__UNIPHYGH_TPG_SEL_MASK
 
- UNIPHYGH_TPG_CONTROL__UNIPHYGH_TPG_SEL__SHIFT
 
- UNIPHYGH_TPG_SEED__UNIPHYGH_TPG_SEED_MASK
 
- UNIPHYGH_TPG_SEED__UNIPHYGH_TPG_SEED__SHIFT
 
- UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK
 
- UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT
 
- UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK
 
- UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT
 
- UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK
 
- UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT
 
- UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK
 
- UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT
 
- UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE_MASK
 
- UNIPHYG_CHANNEL_XBAR_CNTL__UNIPHY_LINK_ENABLE__SHIFT
 
- UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK
 
- UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT
 
- UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK
 
- UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT
 
- UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK
 
- UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT
 
- UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK
 
- UNIPHYG_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT
 
- UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK
 
- UNIPHYG_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT
 
- UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK
 
- UNIPHYG_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT
 
- UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK
 
- UNIPHYG_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT
 
- UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG_MASK
 
- UNIPHYG_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT
 
- UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK
 
- UNIPHYG_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT
 
- UNIPHYG_PRESENT
 
- UNIPHYG_PRESENT__0
 
- UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE_MASK
 
- UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE__SHIFT
 
- UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE_MASK
 
- UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE__SHIFT
 
- UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE_MASK
 
- UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE__SHIFT
 
- UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE_MASK
 
- UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE__SHIFT
 
- UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE_MASK
 
- UNIPHYLPA_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE__SHIFT
 
- UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT_MASK
 
- UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT__SHIFT
 
- UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT_MASK
 
- UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT__SHIFT
 
- UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT_MASK
 
- UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT__SHIFT
 
- UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT_MASK
 
- UNIPHYLPA_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT__SHIFT
 
- UNIPHYLPA_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY_MASK
 
- UNIPHYLPA_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY__SHIFT
 
- UNIPHYLPA_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK_MASK
 
- UNIPHYLPA_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK__SHIFT
 
- UNIPHYLPA_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION_MASK
 
- UNIPHYLPA_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION__SHIFT
 
- UNIPHYLPA_LINK_CNTL__UNIPHYLP_PFREQCHG_MASK
 
- UNIPHYLPA_LINK_CNTL__UNIPHYLP_PFREQCHG__SHIFT
 
- UNIPHYLPA_LINK_CNTL__UNIPHYLP_PIXVLD_RESET_MASK
 
- UNIPHYLPA_LINK_CNTL__UNIPHYLP_PIXVLD_RESET__SHIFT
 
- UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE_MASK
 
- UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL0_XBAR_SOURCE__SHIFT
 
- UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE_MASK
 
- UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL1_XBAR_SOURCE__SHIFT
 
- UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE_MASK
 
- UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL2_XBAR_SOURCE__SHIFT
 
- UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE_MASK
 
- UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_CHANNEL3_XBAR_SOURCE__SHIFT
 
- UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE_MASK
 
- UNIPHYLPB_CHANNEL_XBAR_CNTL__UNIPHYLP_LINK_ENABLE__SHIFT
 
- UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT_MASK
 
- UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL0_INVERT__SHIFT
 
- UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT_MASK
 
- UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL1_INVERT__SHIFT
 
- UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT_MASK
 
- UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL2_INVERT__SHIFT
 
- UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT_MASK
 
- UNIPHYLPB_LINK_CNTL__UNIPHYLP_CHANNEL3_INVERT__SHIFT
 
- UNIPHYLPB_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY_MASK
 
- UNIPHYLPB_LINK_CNTL__UNIPHYLP_LANE_STAGGER_DELAY__SHIFT
 
- UNIPHYLPB_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK_MASK
 
- UNIPHYLPB_LINK_CNTL__UNIPHYLP_LINK_ENABLE_HPD_MASK__SHIFT
 
- UNIPHYLPB_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION_MASK
 
- UNIPHYLPB_LINK_CNTL__UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION__SHIFT
 
- UNIPHYLPB_LINK_CNTL__UNIPHYLP_PFREQCHG_MASK
 
- UNIPHYLPB_LINK_CNTL__UNIPHYLP_PFREQCHG__SHIFT
 
- UNIPHYLPB_LINK_CNTL__UNIPHYLP_PIXVLD_RESET_MASK
 
- UNIPHYLPB_LINK_CNTL__UNIPHYLP_PIXVLD_RESET__SHIFT
 
- UNIPHYTransmitterControl
 
- UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR_MASK
 
- UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR__SHIFT
 
- UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET_MASK
 
- UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET__SHIFT
 
- UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN_MASK
 
- UNIPHY_ANG_BIST_CNTL__UNIPHY_BIST_EN__SHIFT
 
- UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT_MASK
 
- UNIPHY_ANG_BIST_CNTL__UNIPHY_CLK_CH_EN4_DFT__SHIFT
 
- UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB_MASK
 
- UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB__SHIFT
 
- UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS_MASK
 
- UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS__SHIFT
 
- UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN_MASK
 
- UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN__SHIFT
 
- UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK
 
- UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT
 
- UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK
 
- UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT
 
- UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK
 
- UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT
 
- UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK
 
- UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT
 
- UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL_MASK
 
- UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL__SHIFT
 
- UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR_MASK
 
- UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR__SHIFT
 
- UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL_MASK
 
- UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL__SHIFT
 
- UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE_MASK
 
- UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE__SHIFT
 
- UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE_MASK
 
- UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE__SHIFT
 
- UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT_MASK
 
- UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT__SHIFT
 
- UNIPHY_DCN2_REG_LIST
 
- UNIPHY_DEBUG__DBG_SEL_MASK
 
- UNIPHY_DEBUG__DBG_SEL__SHIFT
 
- UNIPHY_DEBUG__DEBUG0_MASK
 
- UNIPHY_DEBUG__DEBUG0__SHIFT
 
- UNIPHY_DEBUG__DEBUG1_MASK
 
- UNIPHY_DEBUG__DEBUG1__SHIFT
 
- UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK
 
- UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT
 
- UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK
 
- UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT
 
- UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK
 
- UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT
 
- UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK
 
- UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT
 
- UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK
 
- UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT
 
- UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK
 
- UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT
 
- UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK
 
- UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT
 
- UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK
 
- UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT
 
- UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK
 
- UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT
 
- UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK
 
- UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT
 
- UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK
 
- UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT
 
- UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK
 
- UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT
 
- UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK
 
- UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT
 
- UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK
 
- UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT
 
- UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK
 
- UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT
 
- UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK
 
- UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT
 
- UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK
 
- UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT
 
- UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK
 
- UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT
 
- UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK
 
- UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT
 
- UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK
 
- UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT
 
- UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK
 
- UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT
 
- UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK
 
- UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT
 
- UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK
 
- UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT
 
- UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK
 
- UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT
 
- UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK
 
- UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT
 
- UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK
 
- UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT
 
- UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK
 
- UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT
 
- UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK
 
- UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT
 
- UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK
 
- UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT
 
- UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK
 
- UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT
 
- UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK
 
- UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT
 
- UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK
 
- UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT
 
- UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK
 
- UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT
 
- UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK
 
- UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT
 
- UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK
 
- UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT
 
- UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK
 
- UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT
 
- UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK
 
- UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT
 
- UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK
 
- UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT
 
- UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK
 
- UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT
 
- UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK
 
- UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT
 
- UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK
 
- UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT
 
- UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK
 
- UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT
 
- UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK
 
- UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT
 
- UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK
 
- UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT
 
- UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK
 
- UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT
 
- UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK
 
- UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT
 
- UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK
 
- UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT
 
- UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK
 
- UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT
 
- UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK
 
- UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT
 
- UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK
 
- UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT
 
- UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK
 
- UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT
 
- UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK
 
- UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT
 
- UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK
 
- UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT
 
- UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK
 
- UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT
 
- UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK
 
- UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT
 
- UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK
 
- UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT
 
- UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK
 
- UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT
 
- UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK
 
- UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT
 
- UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK
 
- UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT
 
- UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK
 
- UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT
 
- UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK
 
- UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT
 
- UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK
 
- UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT
 
- UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK
 
- UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT
 
- UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK
 
- UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT
 
- UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK
 
- UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT
 
- UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK
 
- UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT
 
- UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK
 
- UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT
 
- UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK
 
- UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT
 
- UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG_MASK
 
- UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT
 
- UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK
 
- UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED0__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED100__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED101__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED102__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED103__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED104__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED105__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED106__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED107__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED108__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED109__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED10__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED110__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED111__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED112__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED113__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED114__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED115__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED116__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED117__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED118__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED119__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED11__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED120__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED121__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED122__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED123__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED124__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED125__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED126__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED127__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED128__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED129__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED12__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED130__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED131__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED132__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED133__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED134__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED135__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED136__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED137__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED138__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED139__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED13__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED140__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED141__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED142__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED143__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED144__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED145__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED146__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED147__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED148__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED149__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED14__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED150__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED151__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED152__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED153__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED154__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED155__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED156__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED157__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED158__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED159__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED15__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED16__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED17__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED18__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED19__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED1__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED20__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED21__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED22__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED23__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED24__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED25__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED26__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED27__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED28__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED29__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED2__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED30__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED31__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED32__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED33__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED34__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED35__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED36__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED37__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED38__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED39__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED3__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED40__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED41__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED42__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED43__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED44__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED45__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED46__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED47__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED48__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED49__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED4__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED50__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED51__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED52__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED53__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED54__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED55__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED56__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED57__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED58__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED59__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED5__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED60__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED61__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED62__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED63__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED64__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED65__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED66__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED67__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED68__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED69__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED6__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED70__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED71__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED72__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED73__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED74__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED75__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED76__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED77__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED78__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED79__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED7__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED80__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED81__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED82__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED83__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED84__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED85__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED86__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED87__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED88__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED89__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED8__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED90__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED91__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED92__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED93__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED94__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED95__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED96__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED97__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED98__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED99__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED_MASK
 
- UNIPHY_MACRO_CNTL_RESERVED9__UNIPHY_MACRO_CNTL_RESERVED__SHIFT
 
- UNIPHY_MASK_SH_LIST
 
- UNIPHY_PLL_CAL_CFG0
 
- UNIPHY_PLL_CAL_CFG10
 
- UNIPHY_PLL_CAL_CFG11
 
- UNIPHY_PLL_CAL_CFG8
 
- UNIPHY_PLL_CAL_CFG9
 
- UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL_MASK
 
- UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL__SHIFT
 
- UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN_MASK
 
- UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN__SHIFT
 
- UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN_MASK
 
- UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN__SHIFT
 
- UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE_MASK
 
- UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE__SHIFT
 
- UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN_MASK
 
- UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN__SHIFT
 
- UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL_MASK
 
- UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL__SHIFT
 
- UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET_MASK
 
- UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET__SHIFT
 
- UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN_MASK
 
- UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN__SHIFT
 
- UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC_MASK
 
- UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC__SHIFT
 
- UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN_MASK
 
- UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN__SHIFT
 
- UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE_MASK
 
- UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE__SHIFT
 
- UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV_MASK
 
- UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV__SHIFT
 
- UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL_MASK
 
- UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT
 
- UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN_MASK
 
- UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN__SHIFT
 
- UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL_MASK
 
- UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL__SHIFT
 
- UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL_MASK
 
- UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL__SHIFT
 
- UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK
 
- UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL__SHIFT
 
- UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN_MASK
 
- UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN__SHIFT
 
- UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL_MASK
 
- UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL__SHIFT
 
- UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL_MASK
 
- UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL__SHIFT
 
- UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE_MASK
 
- UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE__SHIFT
 
- UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC_MASK
 
- UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC__SHIFT
 
- UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV_MASK
 
- UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV__SHIFT
 
- UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS_MASK
 
- UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS__SHIFT
 
- UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL_MASK
 
- UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL__SHIFT
 
- UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION_MASK
 
- UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION__SHIFT
 
- UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_MASK
 
- UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV__SHIFT
 
- UNIPHY_PLL_GLB_CFG
 
- UNIPHY_PLL_LKDET_CFG0
 
- UNIPHY_PLL_LKDET_CFG1
 
- UNIPHY_PLL_LKDET_CFG2
 
- UNIPHY_PLL_LOCK
 
- UNIPHY_PLL_PWRGEN_CFG
 
- UNIPHY_PLL_REFCLK_CFG
 
- UNIPHY_PLL_SDM_CFG0
 
- UNIPHY_PLL_SDM_CFG1
 
- UNIPHY_PLL_SDM_CFG2
 
- UNIPHY_PLL_SDM_CFG3
 
- UNIPHY_PLL_SDM_CFG4
 
- UNIPHY_PLL_SSC_CFG0
 
- UNIPHY_PLL_SSC_CFG1
 
- UNIPHY_PLL_SSC_CFG2
 
- UNIPHY_PLL_SSC_CFG3
 
- UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN_MASK
 
- UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN__SHIFT
 
- UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN_MASK
 
- UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN__SHIFT
 
- UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM_MASK
 
- UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM__SHIFT
 
- UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE_MASK
 
- UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE__SHIFT
 
- UNIPHY_PLL_STATUS
 
- UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45_MASK
 
- UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45__SHIFT
 
- UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00_MASK
 
- UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00__SHIFT
 
- UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25_MASK
 
- UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25__SHIFT
 
- UNIPHY_POWER_CONTROL__UNIPHY_BGPDN_MASK
 
- UNIPHY_POWER_CONTROL__UNIPHY_BGPDN__SHIFT
 
- UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL_MASK
 
- UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL__SHIFT
 
- UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC_MASK
 
- UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC__SHIFT
 
- UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX_MASK
 
- UNIPHY_REG_TEST_OUTPUT2__UNIPHY_TX__SHIFT
 
- UNIPHY_REG_TEST_OUTPUT__OA_PLL_TEST_UNLOCK_RAW_MASK
 
- UNIPHY_REG_TEST_OUTPUT__OA_PLL_TEST_UNLOCK_RAW__SHIFT
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR_MASK
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR__SHIFT
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET_MASK
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET__SHIFT
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL_MASK
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL__SHIFT
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET_MASK
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET__SHIFT
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK_MASK
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK__SHIFT
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK_MASK
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_LOCK__SHIFT
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN_MASK
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_SSAMP_EN__SHIFT
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR_MASK
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_CLR__SHIFT
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY_MASK
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_UNLOCK_STICKY__SHIFT
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC_MASK
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC__SHIFT
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_MASK
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL__SHIFT
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL_MASK
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN_MASK
 
- UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN__SHIFT
 
- UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET_MASK
 
- UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT
 
- UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET_MASK
 
- UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT
 
- UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET_MASK
 
- UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT
 
- UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET_MASK
 
- UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT
 
- UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET_MASK
 
- UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT
 
- UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET_MASK
 
- UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT
 
- UNIPHY_SOFT_RESET__DSYNCG_SOFT_RESET_MASK
 
- UNIPHY_SOFT_RESET__DSYNCG_SOFT_RESET__SHIFT
 
- UNIPHY_TMDP_REG0__ICALRA_MODE_MASK
 
- UNIPHY_TMDP_REG0__ICALRA_MODE__SHIFT
 
- UNIPHY_TMDP_REG0__ITXA_DPPC_PWN_MASK
 
- UNIPHY_TMDP_REG0__ITXA_DPPC_PWN__SHIFT
 
- UNIPHY_TMDP_REG0__ITXA_IMPCAL_EN_MASK
 
- UNIPHY_TMDP_REG0__ITXA_IMPCAL_EN__SHIFT
 
- UNIPHY_TMDP_REG0__ITXA_IMPVSCALEN_MASK
 
- UNIPHY_TMDP_REG0__ITXA_IMPVSCALEN__SHIFT
 
- UNIPHY_TMDP_REG0__ITXA_IOCNTL_TSTSEL_MASK
 
- UNIPHY_TMDP_REG0__ITXA_IOCNTL_TSTSEL__SHIFT
 
- UNIPHY_TMDP_REG0__ITXA_OVERRIDE_EN_MASK
 
- UNIPHY_TMDP_REG0__ITXA_OVERRIDE_EN__SHIFT
 
- UNIPHY_TMDP_REG0__ITXA_OVERRIDE_NG_MASK
 
- UNIPHY_TMDP_REG0__ITXA_OVERRIDE_NG__SHIFT
 
- UNIPHY_TMDP_REG0__ITXA_OVERRIDE_PG_MASK
 
- UNIPHY_TMDP_REG0__ITXA_OVERRIDE_PG__SHIFT
 
- UNIPHY_TMDP_REG0__ITXA_PCALEN_MASK
 
- UNIPHY_TMDP_REG0__ITXA_PCALEN__SHIFT
 
- UNIPHY_TMDP_REG0__ITXA_TPC_CNTL_MASK
 
- UNIPHY_TMDP_REG0__ITXA_TPC_CNTL__SHIFT
 
- UNIPHY_TMDP_REG0__ITXA_TPC_SEL_MASK
 
- UNIPHY_TMDP_REG0__ITXA_TPC_SEL__SHIFT
 
- UNIPHY_TMDP_REG0__ITXA_VSCALEN_MASK
 
- UNIPHY_TMDP_REG0__ITXA_VSCALEN__SHIFT
 
- UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_ADJ_MASK
 
- UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_ADJ__SHIFT
 
- UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_PDN_MASK
 
- UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_PDN__SHIFT
 
- UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_TST_MASK
 
- UNIPHY_TMDP_REG1__ITXA_BIAS_ICC_TST__SHIFT
 
- UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL100_ADJ_MASK
 
- UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL100_ADJ__SHIFT
 
- UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL50_ADJ_MASK
 
- UNIPHY_TMDP_REG1__ITXA_BIAS_IPLL50_ADJ__SHIFT
 
- UNIPHY_TMDP_REG1__ITXA_BIAS_PLLREFSEL_MASK
 
- UNIPHY_TMDP_REG1__ITXA_BIAS_PLLREFSEL__SHIFT
 
- UNIPHY_TMDP_REG1__ITXA_IOCNTL_MASK
 
- UNIPHY_TMDP_REG1__ITXA_IOCNTL__SHIFT
 
- UNIPHY_TMDP_REG1__ITX_EDPSEL_MASK
 
- UNIPHY_TMDP_REG1__ITX_EDPSEL__SHIFT
 
- UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_EN_MASK
 
- UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_EN__SHIFT
 
- UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET_MASK
 
- UNIPHY_TMDP_REG2__ITXA_IMPCALN_OFFSET__SHIFT
 
- UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_EN_MASK
 
- UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_EN__SHIFT
 
- UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE_MASK
 
- UNIPHY_TMDP_REG2__ITXA_IMPCALN_OVERRIDE__SHIFT
 
- UNIPHY_TMDP_REG2__ITXA_IMPCALN_PDN_MASK
 
- UNIPHY_TMDP_REG2__ITXA_IMPCALN_PDN__SHIFT
 
- UNIPHY_TMDP_REG2__ITXA_IMPCALN_SET_MASK
 
- UNIPHY_TMDP_REG2__ITXA_IMPCALN_SET__SHIFT
 
- UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_EN_MASK
 
- UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_EN__SHIFT
 
- UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET_MASK
 
- UNIPHY_TMDP_REG2__ITXA_IMPCALP_OFFSET__SHIFT
 
- UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_EN_MASK
 
- UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_EN__SHIFT
 
- UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE_MASK
 
- UNIPHY_TMDP_REG2__ITXA_IMPCALP_OVERRIDE__SHIFT
 
- UNIPHY_TMDP_REG2__ITXA_IMPCALP_PDN_MASK
 
- UNIPHY_TMDP_REG2__ITXA_IMPCALP_PDN__SHIFT
 
- UNIPHY_TMDP_REG2__ITXA_IMPCALP_SET_MASK
 
- UNIPHY_TMDP_REG2__ITXA_IMPCALP_SET__SHIFT
 
- UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_EN_MASK
 
- UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_EN__SHIFT
 
- UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET_MASK
 
- UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OFFSET__SHIFT
 
- UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_EN_MASK
 
- UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_EN__SHIFT
 
- UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE_MASK
 
- UNIPHY_TMDP_REG3__ITXA_IMPCALVS_OVERRIDE__SHIFT
 
- UNIPHY_TMDP_REG3__ITXA_IMPCALVS_PDN_MASK
 
- UNIPHY_TMDP_REG3__ITXA_IMPCALVS_PDN__SHIFT
 
- UNIPHY_TMDP_REG3__ITXA_IMPCALVS_SET_MASK
 
- UNIPHY_TMDP_REG3__ITXA_IMPCALVS_SET__SHIFT
 
- UNIPHY_TMDP_REG3__ITXA_PREM_ADJ_MASK
 
- UNIPHY_TMDP_REG3__ITXA_PREM_ADJ__SHIFT
 
- UNIPHY_TMDP_REG3__OTXA_RES_NCAL_MASK
 
- UNIPHY_TMDP_REG3__OTXA_RES_NCAL__SHIFT
 
- UNIPHY_TMDP_REG3__OTXA_RES_PCAL_MASK
 
- UNIPHY_TMDP_REG3__OTXA_RES_PCAL__SHIFT
 
- UNIPHY_TMDP_REG4__OTXA_IOCNTL_NF_MASK
 
- UNIPHY_TMDP_REG4__OTXA_IOCNTL_NF__SHIFT
 
- UNIPHY_TMDP_REG4__RESERVED_MASK
 
- UNIPHY_TMDP_REG4__RESERVED__SHIFT
 
- UNIPHY_TMDP_REG5__OTXA0_IOFSM_TIMEOUT_MASK
 
- UNIPHY_TMDP_REG5__OTXA0_IOFSM_TIMEOUT__SHIFT
 
- UNIPHY_TMDP_REG5__OTXA0_RESCAL_DONE_MASK
 
- UNIPHY_TMDP_REG5__OTXA0_RESCAL_DONE__SHIFT
 
- UNIPHY_TMDP_REG5__OTXA1_IOFSM_TIMEOUT_MASK
 
- UNIPHY_TMDP_REG5__OTXA1_IOFSM_TIMEOUT__SHIFT
 
- UNIPHY_TMDP_REG5__OTXA1_RESCAL_DONE_MASK
 
- UNIPHY_TMDP_REG5__OTXA1_RESCAL_DONE__SHIFT
 
- UNIPHY_TMDP_REG5__OTXA2_IOFSM_TIMEOUT_MASK
 
- UNIPHY_TMDP_REG5__OTXA2_IOFSM_TIMEOUT__SHIFT
 
- UNIPHY_TMDP_REG5__OTXA2_RESCAL_DONE_MASK
 
- UNIPHY_TMDP_REG5__OTXA2_RESCAL_DONE__SHIFT
 
- UNIPHY_TMDP_REG5__OTXA3_IOFSM_TIMEOUT_MASK
 
- UNIPHY_TMDP_REG5__OTXA3_IOFSM_TIMEOUT__SHIFT
 
- UNIPHY_TMDP_REG5__OTXA3_RESCAL_DONE_MASK
 
- UNIPHY_TMDP_REG5__OTXA3_RESCAL_DONE__SHIFT
 
- UNIPHY_TMDP_REG5__OTXA_IMPCALN_DONE_MASK
 
- UNIPHY_TMDP_REG5__OTXA_IMPCALN_DONE__SHIFT
 
- UNIPHY_TMDP_REG5__OTXA_IMPCALN_ERROR_MASK
 
- UNIPHY_TMDP_REG5__OTXA_IMPCALN_ERROR__SHIFT
 
- UNIPHY_TMDP_REG5__OTXA_IMPCALN_MASK
 
- UNIPHY_TMDP_REG5__OTXA_IMPCALN__SHIFT
 
- UNIPHY_TMDP_REG5__OTXA_IMPCALP_DONE_MASK
 
- UNIPHY_TMDP_REG5__OTXA_IMPCALP_DONE__SHIFT
 
- UNIPHY_TMDP_REG5__OTXA_IMPCALP_ERROR_MASK
 
- UNIPHY_TMDP_REG5__OTXA_IMPCALP_ERROR__SHIFT
 
- UNIPHY_TMDP_REG5__OTXA_IMPCALP_MASK
 
- UNIPHY_TMDP_REG5__OTXA_IMPCALP__SHIFT
 
- UNIPHY_TMDP_REG5__OTXA_IMPCALVS_DONE_MASK
 
- UNIPHY_TMDP_REG5__OTXA_IMPCALVS_DONE__SHIFT
 
- UNIPHY_TMDP_REG5__OTXA_IMPCALVS_ERROR_MASK
 
- UNIPHY_TMDP_REG5__OTXA_IMPCALVS_ERROR__SHIFT
 
- UNIPHY_TMDP_REG5__OTXA_IMPCALVS_MASK
 
- UNIPHY_TMDP_REG5__OTXA_IMPCALVS__SHIFT
 
- UNIPHY_TMDP_REG6__IRXA_BIST_SEL_MASK
 
- UNIPHY_TMDP_REG6__IRXA_BIST_SEL__SHIFT
 
- UNIPHY_TMDP_REG6__IRXA_CPSEL_MASK
 
- UNIPHY_TMDP_REG6__IRXA_CPSEL__SHIFT
 
- UNIPHY_TMDP_REG6__IRXA_OS_ADJ_MASK
 
- UNIPHY_TMDP_REG6__IRXA_OS_ADJ__SHIFT
 
- UNIPHY_TMDP_REG6__IRXA_OS_POLB_MASK
 
- UNIPHY_TMDP_REG6__IRXA_OS_POLB__SHIFT
 
- UNIPHY_TMDP_REG6__IRXA_SENADJ_MASK
 
- UNIPHY_TMDP_REG6__IRXA_SENADJ__SHIFT
 
- UNIPHY_TMDP_REG6__UNIPHY_IMPCAL_SEL_LINKA_MASK
 
- UNIPHY_TMDP_REG6__UNIPHY_IMPCAL_SEL_LINKA__SHIFT
 
- UNIPHY_TPG_CONTROL__UNIPHY_STATIC_TEST_PATTERN_MASK
 
- UNIPHY_TPG_CONTROL__UNIPHY_STATIC_TEST_PATTERN__SHIFT
 
- UNIPHY_TPG_CONTROL__UNIPHY_TPG_EN_MASK
 
- UNIPHY_TPG_CONTROL__UNIPHY_TPG_EN__SHIFT
 
- UNIPHY_TPG_CONTROL__UNIPHY_TPG_SEL_MASK
 
- UNIPHY_TPG_CONTROL__UNIPHY_TPG_SEL__SHIFT
 
- UNIPHY_TPG_SEED__UNIPHY_TPG_SEED_MASK
 
- UNIPHY_TPG_SEED__UNIPHY_TPG_SEED__SHIFT
 
- UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0_MASK
 
- UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0__SHIFT
 
- UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1_MASK
 
- UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1__SHIFT
 
- UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2_MASK
 
- UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2__SHIFT
 
- UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3_MASK
 
- UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3__SHIFT
 
- UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4_MASK
 
- UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4__SHIFT
 
- UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0_MASK
 
- UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0__SHIFT
 
- UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1_MASK
 
- UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1__SHIFT
 
- UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2_MASK
 
- UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2__SHIFT
 
- UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3_MASK
 
- UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3__SHIFT
 
- UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4_MASK
 
- UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4__SHIFT
 
- UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC_MASK
 
- UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC__SHIFT
 
- UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC_MASK
 
- UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC__SHIFT
 
- UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC_MASK
 
- UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC__SHIFT
 
- UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC_MASK
 
- UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC__SHIFT
 
- UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC_MASK
 
- UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC__SHIFT
 
- UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL_MASK
 
- UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL__SHIFT
 
- UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL_MASK
 
- UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL__SHIFT
 
- UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL_MASK
 
- UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL__SHIFT
 
- UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL_MASK
 
- UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL__SHIFT
 
- UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL_MASK
 
- UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL__SHIFT
 
- UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL_MASK
 
- UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL__SHIFT
 
- UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN_MASK
 
- UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN__SHIFT
 
- UNIPHY_TX_CONTROL3__UNIPHY_PESEL0_MASK
 
- UNIPHY_TX_CONTROL3__UNIPHY_PESEL0__SHIFT
 
- UNIPHY_TX_CONTROL3__UNIPHY_PESEL1_MASK
 
- UNIPHY_TX_CONTROL3__UNIPHY_PESEL1__SHIFT
 
- UNIPHY_TX_CONTROL3__UNIPHY_PESEL2_MASK
 
- UNIPHY_TX_CONTROL3__UNIPHY_PESEL2__SHIFT
 
- UNIPHY_TX_CONTROL3__UNIPHY_PESEL3_MASK
 
- UNIPHY_TX_CONTROL3__UNIPHY_PESEL3__SHIFT
 
- UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK_MASK
 
- UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK__SHIFT
 
- UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT_MASK
 
- UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT__SHIFT
 
- UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK_MASK
 
- UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK__SHIFT
 
- UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT_MASK
 
- UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT__SHIFT
 
- UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK_MASK
 
- UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK__SHIFT
 
- UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT_MASK
 
- UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT__SHIFT
 
- UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ_MASK
 
- UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ__SHIFT
 
- UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK_MASK
 
- UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK__SHIFT
 
- UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT_MASK
 
- UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT__SHIFT
 
- UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK_MASK
 
- UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK__SHIFT
 
- UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT_MASK
 
- UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT__SHIFT
 
- UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK_MASK
 
- UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK__SHIFT
 
- UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT_MASK
 
- UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT__SHIFT
 
- UNIPRO_CB_OFFSET
 
- UNIP_BIT
 
- UNIQID
 
- UNIQUE_BL_ID
 
- UNIQUE_ENTRYHI
 
- UNIQUE_GUEST_ENTRYHI
 
- UNIQUE_ID1
 
- UNIQUE_ID2
 
- UNIQUE_ID_IF_CREATE_ADDR_FAILED
 
- UNIQUE_ID_LEN
 
- UNIQUE_ID_NOT_BY_CARD
 
- UNIQUE_TRANGE_EN_METHOD
 
- UNIQ_TRANS_SCALE
 
- UNIQ_TRANS_SCALE_SHIFT
 
- UNISOLATE
 
- UNISYS_VISOR_ID_EBX
 
- UNISYS_VISOR_ID_ECX
 
- UNISYS_VISOR_ID_EDX
 
- UNISYS_VISOR_LEAF_ID
 
- UNIT
 
- UNITY_GAIN
 
- UNIT_ALLOCATED
 
- UNIT_ATTENTION
 
- UNIT_ATTENTION_CLEARED
 
- UNIT_DESC_PARAM_BOOT_LUN_ID
 
- UNIT_DESC_PARAM_CTX_CAPABILITIES
 
- UNIT_DESC_PARAM_DATA_RELIABILITY
 
- UNIT_DESC_PARAM_ERASE_BLK_SIZE
 
- UNIT_DESC_PARAM_LARGE_UNIT_SIZE_M1
 
- UNIT_DESC_PARAM_LEN
 
- UNIT_DESC_PARAM_LOGICAL_BLK_COUNT
 
- UNIT_DESC_PARAM_LOGICAL_BLK_SIZE
 
- UNIT_DESC_PARAM_LU_ENABLE
 
- UNIT_DESC_PARAM_LU_Q_DEPTH
 
- UNIT_DESC_PARAM_LU_WR_PROTECT
 
- UNIT_DESC_PARAM_MEM_TYPE
 
- UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT
 
- UNIT_DESC_PARAM_PROVISIONING_TYPE
 
- UNIT_DESC_PARAM_PSA_SENSITIVE
 
- UNIT_DESC_PARAM_TYPE
 
- UNIT_DESC_PARAM_UNIT_INDEX
 
- UNIT_INFO_CHANGED
 
- UNIT_INT
 
- UNIT_MASK
 
- UNIT_MAX_LEN
 
- UNIT_MINUTE
 
- UNIT_PAGES
 
- UNIT_RETRY
 
- UNIT_SECOND
 
- UNIT_SHIFT
 
- UNIT_SYNC_BARRIER_ALL
 
- UNIT_SYNC_BARRIER_OFF
 
- UNIT_mA
 
- UNIT_none
 
- UNIT_volt
 
- UNIUPR_NOLOWER
 
- UNIVERSAL_DEV_PM_OPS
 
- UNIX98_PTY_MAJOR_COUNT
 
- UNIX98_PTY_MASTER_MAJOR
 
- UNIX98_PTY_SLAVE_MAJOR
 
- UNIXCB
 
- UNIXWARE_DISKMAGIC
 
- UNIXWARE_DISKMAGIC2
 
- UNIXWARE_FS_UNUSED
 
- UNIXWARE_NUMSLICE
 
- UNIXWARE_PARTITION
 
- UNIX_ABSTRACT
 
- UNIX_BIND_FAIL
 
- UNIX_BLOCKDEV
 
- UNIX_CHARDEV
 
- UNIX_DIAG_ICONS
 
- UNIX_DIAG_MAX
 
- UNIX_DIAG_MEMINFO
 
- UNIX_DIAG_NAME
 
- UNIX_DIAG_PEER
 
- UNIX_DIAG_RQLEN
 
- UNIX_DIAG_SHUTDOWN
 
- UNIX_DIAG_UID
 
- UNIX_DIAG_VFS
 
- UNIX_DIR
 
- UNIX_FIFO
 
- UNIX_FILE
 
- UNIX_GC_CANDIDATE
 
- UNIX_GC_MAYBE_CYCLE
 
- UNIX_HASH_BITS
 
- UNIX_HASH_SIZE
 
- UNIX_INFLIGHT_TRIGGER_GC
 
- UNIX_PATH_MAX
 
- UNIX_SECS_1980
 
- UNIX_SECS_2108
 
- UNIX_SKB_FRAGS_SZ
 
- UNIX_SOCKET
 
- UNIX_SYMLINK
 
- UNI_ASTERISK
 
- UNI_CMD_CLOSE
 
- UNI_CMD_OPEN
 
- UNI_COLON
 
- UNI_CUR_DIR_NAME
 
- UNI_DIRECT_BASE
 
- UNI_DIRECT_MASK
 
- UNI_GRTRTHAN
 
- UNI_LESSTHAN
 
- UNI_N_AACK_DELAY
 
- UNI_N_AACK_DELAY_ENABLE
 
- UNI_N_ADDR_COARSE_MASK
 
- UNI_N_ADDR_FINE_MASK
 
- UNI_N_ADDR_SELECT
 
- UNI_N_ARB_CTRL
 
- UNI_N_ARB_CTRL_QACK_DELAY
 
- UNI_N_ARB_CTRL_QACK_DELAY105
 
- UNI_N_ARB_CTRL_QACK_DELAY_MASK
 
- UNI_N_ARB_CTRL_QACK_DELAY_SHIFT
 
- UNI_N_CFG_AGP_BASE
 
- UNI_N_CFG_GART_2xRESET
 
- UNI_N_CFG_GART_BASE
 
- UNI_N_CFG_GART_CTRL
 
- UNI_N_CFG_GART_DISSBADET
 
- UNI_N_CFG_GART_DUMMY_PAGE
 
- UNI_N_CFG_GART_ENABLE
 
- UNI_N_CFG_GART_INVAL
 
- UNI_N_CFG_INTERNAL_STATUS
 
- UNI_N_CLOCK_CNTL
 
- UNI_N_CLOCK_CNTL_ATA100
 
- UNI_N_CLOCK_CNTL_FW
 
- UNI_N_CLOCK_CNTL_GMAC
 
- UNI_N_CLOCK_CNTL_PCI
 
- UNI_N_CLOCK_SPREADING
 
- UNI_N_CLOCK_STOPPED_18
 
- UNI_N_CLOCK_STOPPED_32
 
- UNI_N_CLOCK_STOPPED_45
 
- UNI_N_CLOCK_STOPPED_49
 
- UNI_N_CLOCK_STOPPED_7PCI1
 
- UNI_N_CLOCK_STOPPED_AGP
 
- UNI_N_CLOCK_STOPPED_AGPDEL
 
- UNI_N_CLOCK_STOPPED_ATA100
 
- UNI_N_CLOCK_STOPPED_ATA66
 
- UNI_N_CLOCK_STOPPED_BUF_REFCKO
 
- UNI_N_CLOCK_STOPPED_CPU
 
- UNI_N_CLOCK_STOPPED_CPUDEL
 
- UNI_N_CLOCK_STOPPED_EXTAGP
 
- UNI_N_CLOCK_STOPPED_FW
 
- UNI_N_CLOCK_STOPPED_GB
 
- UNI_N_CLOCK_STOPPED_I2S0_18
 
- UNI_N_CLOCK_STOPPED_I2S0_45_49
 
- UNI_N_CLOCK_STOPPED_I2S1_18
 
- UNI_N_CLOCK_STOPPED_I2S1_45_49
 
- UNI_N_CLOCK_STOPPED_KLPCI
 
- UNI_N_CLOCK_STOPPED_MAX
 
- UNI_N_CLOCK_STOPPED_PCI0
 
- UNI_N_CLOCK_STOPPED_PCI1
 
- UNI_N_CLOCK_STOPPED_PCI2
 
- UNI_N_CLOCK_STOPPED_PCI_FBCLKO
 
- UNI_N_CLOCK_STOPPED_PLL4REF
 
- UNI_N_CLOCK_STOPPED_SCC_RTCLK18
 
- UNI_N_CLOCK_STOPPED_SCC_RTCLK32
 
- UNI_N_CLOCK_STOPPED_SCC_SLOT0
 
- UNI_N_CLOCK_STOPPED_SCC_SLOT1
 
- UNI_N_CLOCK_STOPPED_SCC_SLOT2
 
- UNI_N_CLOCK_STOPPED_SCC_VIA32
 
- UNI_N_CLOCK_STOPPED_TIMER
 
- UNI_N_CLOCK_STOPPED_USB0
 
- UNI_N_CLOCK_STOPPED_USB0PCI
 
- UNI_N_CLOCK_STOPPED_USB1
 
- UNI_N_CLOCK_STOPPED_USB1PCI
 
- UNI_N_CLOCK_STOPPED_USB2
 
- UNI_N_CLOCK_STOPPED_USB2PCI
 
- UNI_N_CLOCK_STOPPED_VEO0
 
- UNI_N_CLOCK_STOPPED_VEO1
 
- UNI_N_CLOCK_STOP_STATUS0
 
- UNI_N_CLOCK_STOP_STATUS1
 
- UNI_N_CPU_NUMBER
 
- UNI_N_HWINIT_STATE
 
- UNI_N_HWINIT_STATE_CPU1_FLAG
 
- UNI_N_HWINIT_STATE_RUNNING
 
- UNI_N_HWINIT_STATE_SLEEPING
 
- UNI_N_POWER_MGT
 
- UNI_N_POWER_MGT_IDLE2
 
- UNI_N_POWER_MGT_NORMAL
 
- UNI_N_POWER_MGT_SLEEP
 
- UNI_N_VERSION
 
- UNI_N_VERSION_107
 
- UNI_N_VERSION_10A
 
- UNI_N_VERSION_150
 
- UNI_N_VERSION_200
 
- UNI_N_VERSION_300
 
- UNI_N_VERSION_INTREPID
 
- UNI_N_VERSION_PANGEA
 
- UNI_PAR_DIR_NAME
 
- UNI_PIPE
 
- UNI_QUESTION
 
- UNI_RANGE
 
- UNI_SLASH
 
- UNJO_ISODEBUG_V1_PID
 
- UNJO_VID
 
- UNKNOWN
 
- UNKNOWN10
 
- UNKNOWN6b
 
- UNKNOWN73
 
- UNKNOWNCMD_F
 
- UNKNOWNCMD_S
 
- UNKNOWNCMD_V
 
- UNKNOWNCOMMAND
 
- UNKNOWN_ADDRESS
 
- UNKNOWN_BASED_IOP
 
- UNKNOWN_BOARD
 
- UNKNOWN_CLASS
 
- UNKNOWN_COMMAND
 
- UNKNOWN_COMMAND_NOTIFIED
 
- UNKNOWN_DEV
 
- UNKNOWN_DMA_BURST_ENABLE_BITS
 
- UNKNOWN_DRIVE
 
- UNKNOWN_FRAME
 
- UNKNOWN_HYSTERESIS
 
- UNKNOWN_IFORMAT
 
- UNKNOWN_INT
 
- UNKNOWN_INTF
 
- UNKNOWN_MATCH_PRIO
 
- UNKNOWN_METER
 
- UNKNOWN_PKEY
 
- UNKNOWN_SYNC_SOURCE
 
- UNKNOWN_TRANSMITTER_PHY_ID
 
- UNKNOWN_TYPE
 
- UNKNOWN_VGA
 
- UNKNOWN_WRITE
 
- UNKNWN
 
- UNK_1C
 
- UNK_1D
 
- UNK_25
 
- UNK_2C
 
- UNK_2D
 
- UNK_FIS
 
- UNLINK_TIMEOUT_MS
 
- UNLMT_STEP
 
- UNLOADED_LIB
 
- UNLOAD_CLOSE
 
- UNLOAD_MEDIUM
 
- UNLOAD_NORMAL
 
- UNLOAD_RECOVERY
 
- UNLOCK
 
- UNLOCK1
 
- UNLOCK2
 
- UNLOCK_01_MASK
 
- UNLOCK_10_MASK
 
- UNLOCK_CODE
 
- UNLOCK_CORE
 
- UNLOCK_DATA
 
- UNLOCK_MASK
 
- UNLOCK_OFFSET
 
- UNLOCK_PFS
 
- UNLOCK_PHY_REGS
 
- UNLOCK_SEQ0
 
- UNLOCK_SEQ1
 
- UNLOCK_VPE
 
- UNMAP
 
- UNMAPPED_GVA
 
- UNMAP_FMR
 
- UNMAP_NOTIFY_CLEAR_BYTE
 
- UNMAP_NOTIFY_SEND_EVENT
 
- UNMAP_ONE
 
- UNMAP_THREE
 
- UNMAP_TWO
 
- UNMARK
 
- UNMASKED_UNDERFLOW
 
- UNMASK_INT
 
- UNMASK_INTERRUPTS
 
- UNMASK_IRQs
 
- UNMUTE
 
- UNM_FFP
 
- UNM_FFP_MASK
 
- UNNAMED_MAJOR
 
- UNORD_DISPATCH
 
- UNP0_UNP_CRC_CONTROL__UNP_CRC_ENABLE_MASK
 
- UNP0_UNP_CRC_CONTROL__UNP_CRC_ENABLE__SHIFT
 
- UNP0_UNP_CRC_CONTROL__UNP_CRC_LINE_SEL_MASK
 
- UNP0_UNP_CRC_CONTROL__UNP_CRC_LINE_SEL__SHIFT
 
- UNP0_UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL_MASK
 
- UNP0_UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL__SHIFT
 
- UNP0_UNP_CRC_CURRENT__UNP_CRC_CURRENT_MASK
 
- UNP0_UNP_CRC_CURRENT__UNP_CRC_CURRENT__SHIFT
 
- UNP0_UNP_CRC_LAST__UNP_CRC_LAST_MASK
 
- UNP0_UNP_CRC_LAST__UNP_CRC_LAST__SHIFT
 
- UNP0_UNP_CRC_MASK__UNP_CRC_MASK_MASK
 
- UNP0_UNP_CRC_MASK__UNP_CRC_MASK__SHIFT
 
- UNP0_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C_MASK
 
- UNP0_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C__SHIFT
 
- UNP0_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C_MASK
 
- UNP0_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C__SHIFT
 
- UNP0_UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK
 
- UNP0_UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT
 
- UNP0_UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK
 
- UNP0_UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT
 
- UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C_MASK
 
- UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C__SHIFT
 
- UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C_MASK
 
- UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C__SHIFT
 
- UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C_MASK
 
- UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C__SHIFT
 
- UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C_MASK
 
- UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C__SHIFT
 
- UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C_MASK
 
- UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C__SHIFT
 
- UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C_MASK
 
- UNP0_UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C__SHIFT
 
- UNP0_UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK
 
- UNP0_UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT
 
- UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK
 
- UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT
 
- UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK
 
- UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT
 
- UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK
 
- UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT
 
- UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK
 
- UNP0_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT
 
- UNP0_UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK
 
- UNP0_UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT
 
- UNP0_UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK
 
- UNP0_UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT
 
- UNP0_UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C_MASK
 
- UNP0_UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C__SHIFT
 
- UNP0_UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C_MASK
 
- UNP0_UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C__SHIFT
 
- UNP0_UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C_MASK
 
- UNP0_UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C__SHIFT
 
- UNP0_UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C_MASK
 
- UNP0_UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C__SHIFT
 
- UNP0_UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C_MASK
 
- UNP0_UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C__SHIFT
 
- UNP0_UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT_MASK
 
- UNP0_UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT__SHIFT
 
- UNP0_UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK
 
- UNP0_UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT
 
- UNP0_UNP_GRPH_CONTROL__GRPH_ARRAY_MODE_MASK
 
- UNP0_UNP_GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT
 
- UNP0_UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L_MASK
 
- UNP0_UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L__SHIFT
 
- UNP0_UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L_MASK
 
- UNP0_UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L__SHIFT
 
- UNP0_UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK
 
- UNP0_UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT
 
- UNP0_UNP_GRPH_CONTROL__GRPH_DEPTH_MASK
 
- UNP0_UNP_GRPH_CONTROL__GRPH_DEPTH__SHIFT
 
- UNP0_UNP_GRPH_CONTROL__GRPH_FORMAT_MASK
 
- UNP0_UNP_GRPH_CONTROL__GRPH_FORMAT__SHIFT
 
- UNP0_UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L_MASK
 
- UNP0_UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L__SHIFT
 
- UNP0_UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L_MASK
 
- UNP0_UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L__SHIFT
 
- UNP0_UNP_GRPH_CONTROL__GRPH_NUM_BANKS_MASK
 
- UNP0_UNP_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT
 
- UNP0_UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK
 
- UNP0_UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT
 
- UNP0_UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK
 
- UNP0_UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT
 
- UNP0_UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L_MASK
 
- UNP0_UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L__SHIFT
 
- UNP0_UNP_GRPH_CONTROL__GRPH_Z_MASK
 
- UNP0_UNP_GRPH_CONTROL__GRPH_Z__SHIFT
 
- UNP0_UNP_GRPH_ENABLE__GRPH_ENABLE_MASK
 
- UNP0_UNP_GRPH_ENABLE__GRPH_ENABLE__SHIFT
 
- UNP0_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
 
- UNP0_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT
 
- UNP0_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK
 
- UNP0_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT
 
- UNP0_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK
 
- UNP0_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT
 
- UNP0_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK
 
- UNP0_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT
 
- UNP0_UNP_GRPH_PITCH_C__GRPH_PITCH_C_MASK
 
- UNP0_UNP_GRPH_PITCH_C__GRPH_PITCH_C__SHIFT
 
- UNP0_UNP_GRPH_PITCH_L__GRPH_PITCH_L_MASK
 
- UNP0_UNP_GRPH_PITCH_L__GRPH_PITCH_L__SHIFT
 
- UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_MASK
 
- UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT
 
- UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK
 
- UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK
 
- UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT
 
- UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_MASK
 
- UNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT
 
- UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C_MASK
 
- UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT
 
- UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK
 
- UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK
 
- UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__SHIFT
 
- UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L_MASK
 
- UNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT
 
- UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_MASK
 
- UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT
 
- UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK
 
- UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK
 
- UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT
 
- UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_MASK
 
- UNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT
 
- UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C_MASK
 
- UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C__SHIFT
 
- UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK
 
- UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_MASK
 
- UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__SHIFT
 
- UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L_MASK
 
- UNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L__SHIFT
 
- UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING_MASK
 
- UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING__SHIFT
 
- UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK
 
- UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT
 
- UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING_MASK
 
- UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING__SHIFT
 
- UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK
 
- UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT
 
- UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN_MASK
 
- UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN__SHIFT
 
- UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE_MASK
 
- UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE__SHIFT
 
- UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK
 
- UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT
 
- UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK
 
- UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT
 
- UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK
 
- UNP0_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT
 
- UNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_MASK
 
- UNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__SHIFT
 
- UNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_MASK
 
- UNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__SHIFT
 
- UNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C_MASK
 
- UNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C__SHIFT
 
- UNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L_MASK
 
- UNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L__SHIFT
 
- UNP0_UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C_MASK
 
- UNP0_UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C__SHIFT
 
- UNP0_UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L_MASK
 
- UNP0_UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L__SHIFT
 
- UNP0_UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C_MASK
 
- UNP0_UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C__SHIFT
 
- UNP0_UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L_MASK
 
- UNP0_UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L__SHIFT
 
- UNP0_UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK
 
- UNP0_UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT
 
- UNP0_UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK
 
- UNP0_UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
 
- UNP0_UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK
 
- UNP0_UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT
 
- UNP0_UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK
 
- UNP0_UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT
 
- UNP0_UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK
 
- UNP0_UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT
 
- UNP0_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK
 
- UNP0_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT
 
- UNP0_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK
 
- UNP0_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT
 
- UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK
 
- UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT
 
- UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK
 
- UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT
 
- UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK
 
- UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT
 
- UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK
 
- UNP0_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT
 
- UNP0_UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK
 
- UNP0_UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT
 
- UNP0_UNP_GRPH_X_END_C__GRPH_X_END_C_MASK
 
- UNP0_UNP_GRPH_X_END_C__GRPH_X_END_C__SHIFT
 
- UNP0_UNP_GRPH_X_END_L__GRPH_X_END_L_MASK
 
- UNP0_UNP_GRPH_X_END_L__GRPH_X_END_L__SHIFT
 
- UNP0_UNP_GRPH_X_START_C__GRPH_X_START_C_MASK
 
- UNP0_UNP_GRPH_X_START_C__GRPH_X_START_C__SHIFT
 
- UNP0_UNP_GRPH_X_START_L__GRPH_X_START_L_MASK
 
- UNP0_UNP_GRPH_X_START_L__GRPH_X_START_L__SHIFT
 
- UNP0_UNP_GRPH_Y_END_C__GRPH_Y_END_C_MASK
 
- UNP0_UNP_GRPH_Y_END_C__GRPH_Y_END_C__SHIFT
 
- UNP0_UNP_GRPH_Y_END_L__GRPH_Y_END_L_MASK
 
- UNP0_UNP_GRPH_Y_END_L__GRPH_Y_END_L__SHIFT
 
- UNP0_UNP_GRPH_Y_START_C__GRPH_Y_START_C_MASK
 
- UNP0_UNP_GRPH_Y_START_C__GRPH_Y_START_C__SHIFT
 
- UNP0_UNP_GRPH_Y_START_L__GRPH_Y_START_L_MASK
 
- UNP0_UNP_GRPH_Y_START_L__GRPH_Y_START_L__SHIFT
 
- UNP0_UNP_HW_ROTATION__BUFFER_MODE_MASK
 
- UNP0_UNP_HW_ROTATION__BUFFER_MODE__SHIFT
 
- UNP0_UNP_HW_ROTATION__PIXEL_DROP_MASK
 
- UNP0_UNP_HW_ROTATION__PIXEL_DROP__SHIFT
 
- UNP0_UNP_HW_ROTATION__ROTATION_ANGLE_MASK
 
- UNP0_UNP_HW_ROTATION__ROTATION_ANGLE__SHIFT
 
- UNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK_MASK
 
- UNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK__SHIFT
 
- UNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C_MASK
 
- UNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C__SHIFT
 
- UNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L_MASK
 
- UNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L__SHIFT
 
- UNP1_UNP_CRC_CONTROL__UNP_CRC_ENABLE_MASK
 
- UNP1_UNP_CRC_CONTROL__UNP_CRC_ENABLE__SHIFT
 
- UNP1_UNP_CRC_CONTROL__UNP_CRC_LINE_SEL_MASK
 
- UNP1_UNP_CRC_CONTROL__UNP_CRC_LINE_SEL__SHIFT
 
- UNP1_UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL_MASK
 
- UNP1_UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL__SHIFT
 
- UNP1_UNP_CRC_CURRENT__UNP_CRC_CURRENT_MASK
 
- UNP1_UNP_CRC_CURRENT__UNP_CRC_CURRENT__SHIFT
 
- UNP1_UNP_CRC_LAST__UNP_CRC_LAST_MASK
 
- UNP1_UNP_CRC_LAST__UNP_CRC_LAST__SHIFT
 
- UNP1_UNP_CRC_MASK__UNP_CRC_MASK_MASK
 
- UNP1_UNP_CRC_MASK__UNP_CRC_MASK__SHIFT
 
- UNP1_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C_MASK
 
- UNP1_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C__SHIFT
 
- UNP1_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C_MASK
 
- UNP1_UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C__SHIFT
 
- UNP1_UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK
 
- UNP1_UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT
 
- UNP1_UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK
 
- UNP1_UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT
 
- UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C_MASK
 
- UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C__SHIFT
 
- UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C_MASK
 
- UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C__SHIFT
 
- UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C_MASK
 
- UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C__SHIFT
 
- UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C_MASK
 
- UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C__SHIFT
 
- UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C_MASK
 
- UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C__SHIFT
 
- UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C_MASK
 
- UNP1_UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C__SHIFT
 
- UNP1_UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK
 
- UNP1_UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT
 
- UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK
 
- UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT
 
- UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK
 
- UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT
 
- UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK
 
- UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT
 
- UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK
 
- UNP1_UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT
 
- UNP1_UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK
 
- UNP1_UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT
 
- UNP1_UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK
 
- UNP1_UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT
 
- UNP1_UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C_MASK
 
- UNP1_UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C__SHIFT
 
- UNP1_UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C_MASK
 
- UNP1_UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C__SHIFT
 
- UNP1_UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C_MASK
 
- UNP1_UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C__SHIFT
 
- UNP1_UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C_MASK
 
- UNP1_UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C__SHIFT
 
- UNP1_UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C_MASK
 
- UNP1_UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C__SHIFT
 
- UNP1_UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT_MASK
 
- UNP1_UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT__SHIFT
 
- UNP1_UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK
 
- UNP1_UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT
 
- UNP1_UNP_GRPH_CONTROL__GRPH_ARRAY_MODE_MASK
 
- UNP1_UNP_GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT
 
- UNP1_UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L_MASK
 
- UNP1_UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L__SHIFT
 
- UNP1_UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L_MASK
 
- UNP1_UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L__SHIFT
 
- UNP1_UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK
 
- UNP1_UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT
 
- UNP1_UNP_GRPH_CONTROL__GRPH_DEPTH_MASK
 
- UNP1_UNP_GRPH_CONTROL__GRPH_DEPTH__SHIFT
 
- UNP1_UNP_GRPH_CONTROL__GRPH_FORMAT_MASK
 
- UNP1_UNP_GRPH_CONTROL__GRPH_FORMAT__SHIFT
 
- UNP1_UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L_MASK
 
- UNP1_UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L__SHIFT
 
- UNP1_UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L_MASK
 
- UNP1_UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L__SHIFT
 
- UNP1_UNP_GRPH_CONTROL__GRPH_NUM_BANKS_MASK
 
- UNP1_UNP_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT
 
- UNP1_UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK
 
- UNP1_UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT
 
- UNP1_UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK
 
- UNP1_UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT
 
- UNP1_UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L_MASK
 
- UNP1_UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L__SHIFT
 
- UNP1_UNP_GRPH_CONTROL__GRPH_Z_MASK
 
- UNP1_UNP_GRPH_CONTROL__GRPH_Z__SHIFT
 
- UNP1_UNP_GRPH_ENABLE__GRPH_ENABLE_MASK
 
- UNP1_UNP_GRPH_ENABLE__GRPH_ENABLE__SHIFT
 
- UNP1_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
 
- UNP1_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT
 
- UNP1_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK
 
- UNP1_UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT
 
- UNP1_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK
 
- UNP1_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT
 
- UNP1_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK
 
- UNP1_UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT
 
- UNP1_UNP_GRPH_PITCH_C__GRPH_PITCH_C_MASK
 
- UNP1_UNP_GRPH_PITCH_C__GRPH_PITCH_C__SHIFT
 
- UNP1_UNP_GRPH_PITCH_L__GRPH_PITCH_L_MASK
 
- UNP1_UNP_GRPH_PITCH_L__GRPH_PITCH_L__SHIFT
 
- UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_MASK
 
- UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT
 
- UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK
 
- UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK
 
- UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT
 
- UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_MASK
 
- UNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT
 
- UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C_MASK
 
- UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT
 
- UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK
 
- UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK
 
- UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__SHIFT
 
- UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L_MASK
 
- UNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT
 
- UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_MASK
 
- UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT
 
- UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK
 
- UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK
 
- UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT
 
- UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_MASK
 
- UNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT
 
- UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C_MASK
 
- UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C__SHIFT
 
- UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK
 
- UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_MASK
 
- UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__SHIFT
 
- UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L_MASK
 
- UNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L__SHIFT
 
- UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING_MASK
 
- UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING__SHIFT
 
- UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK
 
- UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT
 
- UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING_MASK
 
- UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING__SHIFT
 
- UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK
 
- UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT
 
- UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN_MASK
 
- UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN__SHIFT
 
- UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE_MASK
 
- UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE__SHIFT
 
- UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK
 
- UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT
 
- UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK
 
- UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT
 
- UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK
 
- UNP1_UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT
 
- UNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_MASK
 
- UNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__SHIFT
 
- UNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_MASK
 
- UNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__SHIFT
 
- UNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C_MASK
 
- UNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C__SHIFT
 
- UNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L_MASK
 
- UNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L__SHIFT
 
- UNP1_UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C_MASK
 
- UNP1_UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C__SHIFT
 
- UNP1_UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L_MASK
 
- UNP1_UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L__SHIFT
 
- UNP1_UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C_MASK
 
- UNP1_UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C__SHIFT
 
- UNP1_UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L_MASK
 
- UNP1_UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L__SHIFT
 
- UNP1_UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK
 
- UNP1_UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT
 
- UNP1_UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK
 
- UNP1_UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
 
- UNP1_UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK
 
- UNP1_UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT
 
- UNP1_UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK
 
- UNP1_UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT
 
- UNP1_UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK
 
- UNP1_UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT
 
- UNP1_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK
 
- UNP1_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT
 
- UNP1_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK
 
- UNP1_UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT
 
- UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK
 
- UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT
 
- UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK
 
- UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT
 
- UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK
 
- UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT
 
- UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK
 
- UNP1_UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT
 
- UNP1_UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK
 
- UNP1_UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT
 
- UNP1_UNP_GRPH_X_END_C__GRPH_X_END_C_MASK
 
- UNP1_UNP_GRPH_X_END_C__GRPH_X_END_C__SHIFT
 
- UNP1_UNP_GRPH_X_END_L__GRPH_X_END_L_MASK
 
- UNP1_UNP_GRPH_X_END_L__GRPH_X_END_L__SHIFT
 
- UNP1_UNP_GRPH_X_START_C__GRPH_X_START_C_MASK
 
- UNP1_UNP_GRPH_X_START_C__GRPH_X_START_C__SHIFT
 
- UNP1_UNP_GRPH_X_START_L__GRPH_X_START_L_MASK
 
- UNP1_UNP_GRPH_X_START_L__GRPH_X_START_L__SHIFT
 
- UNP1_UNP_GRPH_Y_END_C__GRPH_Y_END_C_MASK
 
- UNP1_UNP_GRPH_Y_END_C__GRPH_Y_END_C__SHIFT
 
- UNP1_UNP_GRPH_Y_END_L__GRPH_Y_END_L_MASK
 
- UNP1_UNP_GRPH_Y_END_L__GRPH_Y_END_L__SHIFT
 
- UNP1_UNP_GRPH_Y_START_C__GRPH_Y_START_C_MASK
 
- UNP1_UNP_GRPH_Y_START_C__GRPH_Y_START_C__SHIFT
 
- UNP1_UNP_GRPH_Y_START_L__GRPH_Y_START_L_MASK
 
- UNP1_UNP_GRPH_Y_START_L__GRPH_Y_START_L__SHIFT
 
- UNP1_UNP_HW_ROTATION__BUFFER_MODE_MASK
 
- UNP1_UNP_HW_ROTATION__BUFFER_MODE__SHIFT
 
- UNP1_UNP_HW_ROTATION__PIXEL_DROP_MASK
 
- UNP1_UNP_HW_ROTATION__PIXEL_DROP__SHIFT
 
- UNP1_UNP_HW_ROTATION__ROTATION_ANGLE_MASK
 
- UNP1_UNP_HW_ROTATION__ROTATION_ANGLE__SHIFT
 
- UNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK_MASK
 
- UNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK__SHIFT
 
- UNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C_MASK
 
- UNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C__SHIFT
 
- UNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L_MASK
 
- UNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L__SHIFT
 
- UNPACK
 
- UNPACKED
 
- UNPACK_ARRAY
 
- UNPACK_D
 
- UNPACK_S
 
- UNPLUGGED_PER_PAGE
 
- UNPLUG_ERR
 
- UNPLUG_REMOTE
 
- UNPRED
 
- UNPRIV_SYSCTL
 
- UNPROTECTED_DACL_SECINFO
 
- UNPROTECTED_SACL_SECINFO
 
- UNPROTECT_ARRAY
 
- UNPROTECT_CTX
 
- UNPROTECT_CTX_NOIRQ
 
- UNPROTECT_CTX_NOPRINT
 
- UNP_ADDR_SURF_MACRO_ASPECT_1
 
- UNP_ADDR_SURF_MACRO_ASPECT_2
 
- UNP_ADDR_SURF_MACRO_ASPECT_4
 
- UNP_ADDR_SURF_MACRO_ASPECT_8
 
- UNP_ADDR_SURF_TILE_SPLIT_128B
 
- UNP_ADDR_SURF_TILE_SPLIT_1KB
 
- UNP_ADDR_SURF_TILE_SPLIT_256B
 
- UNP_ADDR_SURF_TILE_SPLIT_2KB
 
- UNP_ADDR_SURF_TILE_SPLIT_4KB
 
- UNP_ADDR_SURF_TILE_SPLIT_512B
 
- UNP_ADDR_SURF_TILE_SPLIT_64B
 
- UNP_BUFFER_MODE
 
- UNP_BUFFER_MODE_LUMA
 
- UNP_BUFFER_MODE_LUMA_CHROMA
 
- UNP_CRC_CONTROL__UNP_CRC_ENABLE_MASK
 
- UNP_CRC_CONTROL__UNP_CRC_ENABLE__SHIFT
 
- UNP_CRC_CONTROL__UNP_CRC_LINE_SEL_MASK
 
- UNP_CRC_CONTROL__UNP_CRC_LINE_SEL__SHIFT
 
- UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL_MASK
 
- UNP_CRC_CONTROL__UNP_CRC_SOURCE_SEL__SHIFT
 
- UNP_CRC_CURRENT__UNP_CRC_CURRENT_MASK
 
- UNP_CRC_CURRENT__UNP_CRC_CURRENT__SHIFT
 
- UNP_CRC_LAST__UNP_CRC_LAST_MASK
 
- UNP_CRC_LAST__UNP_CRC_LAST__SHIFT
 
- UNP_CRC_LINE_SEL
 
- UNP_CRC_LINE_SEL_EVEN_ONLY
 
- UNP_CRC_LINE_SEL_ODD_EVEN
 
- UNP_CRC_LINE_SEL_ODD_ONLY
 
- UNP_CRC_LINE_SEL_RESERVED
 
- UNP_CRC_MASK__UNP_CRC_MASK_MASK
 
- UNP_CRC_MASK__UNP_CRC_MASK__SHIFT
 
- UNP_CRC_SOURCE_SEL
 
- UNP_CRC_SOURCE_SEL_LOWER16
 
- UNP_CRC_SOURCE_SEL_LOWER32
 
- UNP_CRC_SOURCE_SEL_NP_TO_LBV
 
- UNP_CRC_SOURCE_SEL_RESERVED
 
- UNP_CRC_SOURCE_SEL_UNP_TO_LBV
 
- UNP_DEBUG2__UNP_DEBUG2_MASK
 
- UNP_DEBUG2__UNP_DEBUG2__SHIFT
 
- UNP_DEBUG__UNP_DEBUG_MASK
 
- UNP_DEBUG__UNP_DEBUG__SHIFT
 
- UNP_DVMM_DEBUG__UNP_C_DVMM_DEBUG_MASK
 
- UNP_DVMM_DEBUG__UNP_C_DVMM_DEBUG__SHIFT
 
- UNP_DVMM_DEBUG__UNP_L_DVMM_DEBUG_MASK
 
- UNP_DVMM_DEBUG__UNP_L_DVMM_DEBUG__SHIFT
 
- UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C_MASK
 
- UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_MAX_PTE_REQ_OUTSTANDING_C__SHIFT
 
- UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C_MASK
 
- UNP_DVMM_PTE_ARB_CONTROL_C__DVMM_PTE_REQ_PER_CHUNK_C__SHIFT
 
- UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING_MASK
 
- UNP_DVMM_PTE_ARB_CONTROL__DVMM_MAX_PTE_REQ_OUTSTANDING__SHIFT
 
- UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK_MASK
 
- UNP_DVMM_PTE_ARB_CONTROL__DVMM_PTE_REQ_PER_CHUNK__SHIFT
 
- UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C_MASK
 
- UNP_DVMM_PTE_CONTROL_C__DVMM_MIN_PTE_BEFORE_FLIP_C__SHIFT
 
- UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C_MASK
 
- UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_HEIGHT_C__SHIFT
 
- UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C_MASK
 
- UNP_DVMM_PTE_CONTROL_C__DVMM_PAGE_WIDTH_C__SHIFT
 
- UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C_MASK
 
- UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE0_C__SHIFT
 
- UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C_MASK
 
- UNP_DVMM_PTE_CONTROL_C__DVMM_PTE_BUFFER_MODE1_C__SHIFT
 
- UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C_MASK
 
- UNP_DVMM_PTE_CONTROL_C__DVMM_USE_SINGLE_PTE_C__SHIFT
 
- UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP_MASK
 
- UNP_DVMM_PTE_CONTROL__DVMM_MIN_PTE_BEFORE_FLIP__SHIFT
 
- UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT_MASK
 
- UNP_DVMM_PTE_CONTROL__DVMM_PAGE_HEIGHT__SHIFT
 
- UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH_MASK
 
- UNP_DVMM_PTE_CONTROL__DVMM_PAGE_WIDTH__SHIFT
 
- UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0_MASK
 
- UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE0__SHIFT
 
- UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1_MASK
 
- UNP_DVMM_PTE_CONTROL__DVMM_PTE_BUFFER_MODE1__SHIFT
 
- UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE_MASK
 
- UNP_DVMM_PTE_CONTROL__DVMM_USE_SINGLE_PTE__SHIFT
 
- UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE_MASK
 
- UNP_FLIP_CONTROL__GRPH_SURFACE_UPDATE_PENDING_MODE__SHIFT
 
- UNP_FLIP_CONTROL__UNP_DEBUG_SG_MASK
 
- UNP_FLIP_CONTROL__UNP_DEBUG_SG__SHIFT
 
- UNP_GRPH_16BPP
 
- UNP_GRPH_32BPP
 
- UNP_GRPH_8BPP
 
- UNP_GRPH_ADDRESS_TRANSLATION_ENABLE
 
- UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0
 
- UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1
 
- UNP_GRPH_ADDR_SURF_16_BANK
 
- UNP_GRPH_ADDR_SURF_2_BANK
 
- UNP_GRPH_ADDR_SURF_4_BANK
 
- UNP_GRPH_ADDR_SURF_8_BANK
 
- UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1
 
- UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2
 
- UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4
 
- UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8
 
- UNP_GRPH_ADDR_SURF_BANK_WIDTH_1
 
- UNP_GRPH_ADDR_SURF_BANK_WIDTH_2
 
- UNP_GRPH_ADDR_SURF_BANK_WIDTH_4
 
- UNP_GRPH_ADDR_SURF_BANK_WIDTH_8
 
- UNP_GRPH_BANK_HEIGHT
 
- UNP_GRPH_BANK_WIDTH
 
- UNP_GRPH_BLUE_CROSSBAR
 
- UNP_GRPH_BLUE_CROSSBAR_A
 
- UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C
 
- UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y
 
- UNP_GRPH_BLUE_CROSSBAR_R_Cr
 
- UNP_GRPH_COLOR_EXPANSION_MODE
 
- UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C_MASK
 
- UNP_GRPH_CONTROL_C__GRPH_BANK_HEIGHT_C__SHIFT
 
- UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C_MASK
 
- UNP_GRPH_CONTROL_C__GRPH_BANK_WIDTH_C__SHIFT
 
- UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C_MASK
 
- UNP_GRPH_CONTROL_C__GRPH_MACRO_TILE_ASPECT_C__SHIFT
 
- UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C_MASK
 
- UNP_GRPH_CONTROL_C__GRPH_MICRO_TILE_MODE_C__SHIFT
 
- UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C_MASK
 
- UNP_GRPH_CONTROL_C__GRPH_TILE_SPLIT_C__SHIFT
 
- UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT_MASK
 
- UNP_GRPH_CONTROL_EXP__VIDEO_FORMAT__SHIFT
 
- UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK
 
- UNP_GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT
 
- UNP_GRPH_CONTROL__GRPH_ARRAY_MODE_MASK
 
- UNP_GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT
 
- UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L_MASK
 
- UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_L__SHIFT
 
- UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK
 
- UNP_GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT
 
- UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L_MASK
 
- UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_L__SHIFT
 
- UNP_GRPH_CONTROL__GRPH_BANK_WIDTH_MASK
 
- UNP_GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT
 
- UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK
 
- UNP_GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT
 
- UNP_GRPH_CONTROL__GRPH_DEPTH_MASK
 
- UNP_GRPH_CONTROL__GRPH_DEPTH__SHIFT
 
- UNP_GRPH_CONTROL__GRPH_FORMAT_MASK
 
- UNP_GRPH_CONTROL__GRPH_FORMAT__SHIFT
 
- UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L_MASK
 
- UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_L__SHIFT
 
- UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK
 
- UNP_GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT
 
- UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L_MASK
 
- UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_L__SHIFT
 
- UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE_MASK
 
- UNP_GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT
 
- UNP_GRPH_CONTROL__GRPH_NUM_BANKS_MASK
 
- UNP_GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT
 
- UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK
 
- UNP_GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT
 
- UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK
 
- UNP_GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT
 
- UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L_MASK
 
- UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_L__SHIFT
 
- UNP_GRPH_CONTROL__GRPH_TILE_SPLIT_MASK
 
- UNP_GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT
 
- UNP_GRPH_CONTROL__GRPH_Z_MASK
 
- UNP_GRPH_CONTROL__GRPH_Z__SHIFT
 
- UNP_GRPH_DEPTH
 
- UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK
 
- UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT
 
- UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK
 
- UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT
 
- UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK
 
- UNP_GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT
 
- UNP_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK
 
- UNP_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT
 
- UNP_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK
 
- UNP_GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT
 
- UNP_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK
 
- UNP_GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT
 
- UNP_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK
 
- UNP_GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT
 
- UNP_GRPH_DISABLED
 
- UNP_GRPH_DYNAMIC_EXPANSION
 
- UNP_GRPH_EN
 
- UNP_GRPH_ENABLED
 
- UNP_GRPH_ENABLE__GRPH_ENABLE_MASK
 
- UNP_GRPH_ENABLE__GRPH_ENABLE__SHIFT
 
- UNP_GRPH_ENDIAN_SWAP
 
- UNP_GRPH_ENDIAN_SWAP_8IN16
 
- UNP_GRPH_ENDIAN_SWAP_8IN32
 
- UNP_GRPH_ENDIAN_SWAP_8IN43
 
- UNP_GRPH_ENDIAN_SWAP_NONE
 
- UNP_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE_MASK
 
- UNP_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_ENABLE__SHIFT
 
- UNP_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE_MASK
 
- UNP_GRPH_FLIP_RATE_CNTL__GRPH_FLIP_RATE__SHIFT
 
- UNP_GRPH_GREEN_CROSSBAR
 
- UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK
 
- UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT
 
- UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK
 
- UNP_GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT
 
- UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK
 
- UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT
 
- UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK
 
- UNP_GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT
 
- UNP_GRPH_MACRO_TILE_ASPECT
 
- UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE
 
- UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0
 
- UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1
 
- UNP_GRPH_MODE_UPDATE_LOCKG
 
- UNP_GRPH_NUM_BANKS
 
- UNP_GRPH_PITCH_C__GRPH_PITCH_C_MASK
 
- UNP_GRPH_PITCH_C__GRPH_PITCH_C__SHIFT
 
- UNP_GRPH_PITCH_L__GRPH_PITCH_L_MASK
 
- UNP_GRPH_PITCH_L__GRPH_PITCH_L__SHIFT
 
- UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_C_MASK
 
- UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_C__SHIFT
 
- UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C_MASK
 
- UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT
 
- UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK
 
- UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK
 
- UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT
 
- UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_L_MASK
 
- UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_L__SHIFT
 
- UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L_MASK
 
- UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT
 
- UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_DFQ_ENABLE_C_MASK
 
- UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_DFQ_ENABLE_C__SHIFT
 
- UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C_MASK
 
- UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT
 
- UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK
 
- UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK
 
- UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__SHIFT
 
- UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_DFQ_ENABLE_L_MASK
 
- UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_DFQ_ENABLE_L__SHIFT
 
- UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L_MASK
 
- UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT
 
- UNP_GRPH_PRIVILEGED_ACCESS_DIS
 
- UNP_GRPH_PRIVILEGED_ACCESS_EN
 
- UNP_GRPH_PRIVILEGED_ACCESS_ENABLE
 
- UNP_GRPH_RED_CROSSBAR
 
- UNP_GRPH_RED_CROSSBAR_A
 
- UNP_GRPH_RED_CROSSBAR_B_Cb
 
- UNP_GRPH_RED_CROSSBAR_G_Y
 
- UNP_GRPH_RED_CROSSBAR_R_Cr
 
- UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_C_MASK
 
- UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_C__SHIFT
 
- UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C_MASK
 
- UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C__SHIFT
 
- UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C_MASK
 
- UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L_MASK
 
- UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L__SHIFT
 
- UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_L_MASK
 
- UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_L__SHIFT
 
- UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L_MASK
 
- UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L__SHIFT
 
- UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_DFQ_ENABLE_C_MASK
 
- UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_DFQ_ENABLE_C__SHIFT
 
- UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C_MASK
 
- UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C__GRPH_SECONDARY_SURFACE_ADDRESS_C__SHIFT
 
- UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C_MASK
 
- UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C__SHIFT
 
- UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L_MASK
 
- UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L__SHIFT
 
- UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_DFQ_ENABLE_L_MASK
 
- UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_DFQ_ENABLE_L__SHIFT
 
- UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L_MASK
 
- UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L__GRPH_SECONDARY_SURFACE_ADDRESS_L__SHIFT
 
- UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE
 
- UNP_GRPH_STACK_INTERLACE_FLIP_EN
 
- UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE
 
- UNP_GRPH_STACK_INTERLACE_FLIP_MODE
 
- UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0
 
- UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1
 
- UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2
 
- UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3
 
- UNP_GRPH_STEREOSYNC_FLIP_DISABLE
 
- UNP_GRPH_STEREOSYNC_FLIP_EN
 
- UNP_GRPH_STEREOSYNC_FLIP_ENABLE
 
- UNP_GRPH_STEREOSYNC_FLIP_MODE
 
- UNP_GRPH_STEREOSYNC_FLIP_MODE_0
 
- UNP_GRPH_STEREOSYNC_FLIP_MODE_1
 
- UNP_GRPH_STEREOSYNC_FLIP_MODE_2
 
- UNP_GRPH_STEREOSYNC_FLIP_MODE_3
 
- UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING_MASK
 
- UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_BOTTOM_SURFACE_PENDING__SHIFT
 
- UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK
 
- UNP_GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT
 
- UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING_MASK
 
- UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_BOTTOM_SURFACE_PENDING__SHIFT
 
- UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK
 
- UNP_GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT
 
- UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN_MASK
 
- UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_EN__SHIFT
 
- UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE_MASK
 
- UNP_GRPH_STEREOSYNC_FLIP__GRPH_STACK_INTERLACE_FLIP_MODE__SHIFT
 
- UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK
 
- UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT
 
- UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK
 
- UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT
 
- UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK
 
- UNP_GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT
 
- UNP_GRPH_STEREOSYNC_SELECT_DIS
 
- UNP_GRPH_STEREOSYNC_SELECT_DISABLE
 
- UNP_GRPH_STEREOSYNC_SELECT_EN
 
- UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C_MASK
 
- UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__GRPH_SURFACE_ADDRESS_HIGH_INUSE_C__SHIFT
 
- UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L_MASK
 
- UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__GRPH_SURFACE_ADDRESS_HIGH_INUSE_L__SHIFT
 
- UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C_MASK
 
- UNP_GRPH_SURFACE_ADDRESS_INUSE_C__GRPH_SURFACE_ADDRESS_INUSE_C__SHIFT
 
- UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L_MASK
 
- UNP_GRPH_SURFACE_ADDRESS_INUSE_L__GRPH_SURFACE_ADDRESS_INUSE_L__SHIFT
 
- UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE
 
- UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0
 
- UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1
 
- UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK
 
- UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0
 
- UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1
 
- UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C_MASK
 
- UNP_GRPH_SURFACE_OFFSET_X_C__GRPH_SURFACE_OFFSET_X_C__SHIFT
 
- UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L_MASK
 
- UNP_GRPH_SURFACE_OFFSET_X_L__GRPH_SURFACE_OFFSET_X_L__SHIFT
 
- UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C_MASK
 
- UNP_GRPH_SURFACE_OFFSET_Y_C__GRPH_SURFACE_OFFSET_Y_C__SHIFT
 
- UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L_MASK
 
- UNP_GRPH_SURFACE_OFFSET_Y_L__GRPH_SURFACE_OFFSET_Y_L__SHIFT
 
- UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK
 
- UNP_GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT
 
- UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK
 
- UNP_GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT
 
- UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK
 
- UNP_GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT
 
- UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK
 
- UNP_GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT
 
- UNP_GRPH_TILE_SPLIT
 
- UNP_GRPH_UPDATE_LOCK_0
 
- UNP_GRPH_UPDATE_LOCK_1
 
- UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK
 
- UNP_GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT
 
- UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK
 
- UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT
 
- UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK
 
- UNP_GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT
 
- UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK
 
- UNP_GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT
 
- UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK_MASK
 
- UNP_GRPH_UPDATE__GRPH_SURFACE_IGNORE_UPDATE_LOCK__SHIFT
 
- UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK
 
- UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT
 
- UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK
 
- UNP_GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT
 
- UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK
 
- UNP_GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT
 
- UNP_GRPH_X_END_C__GRPH_X_END_C_MASK
 
- UNP_GRPH_X_END_C__GRPH_X_END_C__SHIFT
 
- UNP_GRPH_X_END_L__GRPH_X_END_L_MASK
 
- UNP_GRPH_X_END_L__GRPH_X_END_L__SHIFT
 
- UNP_GRPH_X_START_C__GRPH_X_START_C_MASK
 
- UNP_GRPH_X_START_C__GRPH_X_START_C__SHIFT
 
- UNP_GRPH_X_START_L__GRPH_X_START_L_MASK
 
- UNP_GRPH_X_START_L__GRPH_X_START_L__SHIFT
 
- UNP_GRPH_Y_END_C__GRPH_Y_END_C_MASK
 
- UNP_GRPH_Y_END_C__GRPH_Y_END_C__SHIFT
 
- UNP_GRPH_Y_END_L__GRPH_Y_END_L_MASK
 
- UNP_GRPH_Y_END_L__GRPH_Y_END_L__SHIFT
 
- UNP_GRPH_Y_START_C__GRPH_Y_START_C_MASK
 
- UNP_GRPH_Y_START_C__GRPH_Y_START_C__SHIFT
 
- UNP_GRPH_Y_START_L__GRPH_Y_START_L_MASK
 
- UNP_GRPH_Y_START_L__GRPH_Y_START_L__SHIFT
 
- UNP_GRPH_ZERO_EXPANSION
 
- UNP_HW_ROTATION__BUFFER_MODE_MASK
 
- UNP_HW_ROTATION__BUFFER_MODE__SHIFT
 
- UNP_HW_ROTATION__PIXEL_DROP_MASK
 
- UNP_HW_ROTATION__PIXEL_DROP__SHIFT
 
- UNP_HW_ROTATION__ROTATION_ANGLE_MASK
 
- UNP_HW_ROTATION__ROTATION_ANGLE__SHIFT
 
- UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK_MASK
 
- UNP_LB_DATA_GAP_BETWEEN_CHUNK__UNP_LB_GAP_BETWEEN_CHUNK__SHIFT
 
- UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C_MASK
 
- UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C__SHIFT
 
- UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L_MASK
 
- UNP_PIPE_OUTSTANDING_REQUEST_LIMIT__UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L__SHIFT
 
- UNP_PIXEL_DROP
 
- UNP_PIXEL_DROPPING
 
- UNP_PIXEL_NO_DROP
 
- UNP_ROTATION_ANGLE
 
- UNP_ROTATION_ANGLE_0
 
- UNP_ROTATION_ANGLE_0m
 
- UNP_ROTATION_ANGLE_180
 
- UNP_ROTATION_ANGLE_180m
 
- UNP_ROTATION_ANGLE_270
 
- UNP_ROTATION_ANGLE_270m
 
- UNP_ROTATION_ANGLE_90
 
- UNP_ROTATION_ANGLE_90m
 
- UNP_TEST_DEBUG_DATA__UNP_TEST_DEBUG_DATA_MASK
 
- UNP_TEST_DEBUG_DATA__UNP_TEST_DEBUG_DATA__SHIFT
 
- UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_INDEX_MASK
 
- UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_INDEX__SHIFT
 
- UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_WRITE_EN_MASK
 
- UNP_TEST_DEBUG_INDEX__UNP_TEST_DEBUG_WRITE_EN__SHIFT
 
- UNP_UNP_GRPH_GREEN_CROSSBAR_A
 
- UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C
 
- UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y
 
- UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr
 
- UNP_VIDEO_FORMAT
 
- UNP_VIDEO_FORMAT0
 
- UNP_VIDEO_FORMAT1
 
- UNP_VIDEO_FORMAT_YUV420_YCbCr
 
- UNP_VIDEO_FORMAT_YUV420_YCrCb
 
- UNP_VIDEO_FORMAT_YUV422_CbY
 
- UNP_VIDEO_FORMAT_YUV422_CrY
 
- UNP_VIDEO_FORMAT_YUV422_YCb
 
- UNP_VIDEO_FORMAT_YUV422_YCr
 
- UNREASONABLE_LAT
 
- UNRECOVERED_READ_ERR
 
- UNREG_D_ID_VAR
 
- UNREG_LOGIN_VAR
 
- UNREG_VPI_VAR
 
- UNRESONABLE_LATENCY
 
- UNRESTRICTED_DOMID
 
- UNROLL_LOOP_FOR_COPY
 
- UNRUNNABLE
 
- UNSET
 
- UNSET_AIACKT
 
- UNSET_AIE
 
- UNSET_ECMDAE
 
- UNSET_ECMDBE
 
- UNSET_EDATAF
 
- UNSET_EDATBF
 
- UNSET_EMPUIRQ
 
- UNSET_ESBIRQON
 
- UNSET_GRESET
 
- UNSET_HASH
 
- UNSET_PSET
 
- UNSET_TYPE
 
- UNSHARED_PTRS_PER_PGD
 
- UNSIGNALED_EVENT_SLOT
 
- UNSIGNED
 
- UNSIGNED_BYTE_MAX
 
- UNSIGNED_BYTE_MIN
 
- UNSIGNED_EXTRACT
 
- UNSLICE_UNIT_LEVEL_CLKGATE
 
- UNSLICE_UNIT_LEVEL_CLKGATE2
 
- UNSOLICITED_FRAME_EMPTY
 
- UNSOLICITED_FRAME_IN_USE
 
- UNSOLICITED_FRAME_MAX_STATES
 
- UNSOLICITED_FRAME_RELEASED
 
- UNSOLICITED_RESPONSE_ENABLE
 
- UNSOL_DATA_DIGEST_ERROR_NOTIFY
 
- UNSOL_DATA_NOTIFY
 
- UNSOL_HDR_NOTIFY
 
- UNSOL_INVALID
 
- UNSOL_TAG_DSP
 
- UNSOL_VALID
 
- UNSPECIFIED_ERROR
 
- UNSTABLE_FLAG
 
- UNSTUFF_BITS
 
- UNSUP
 
- UNSUPPORTED
 
- UNSUPPORTEDOPTION
 
- UNSUPPORTED_CMD
 
- UNSUPPORTED_COMMAND
 
- UNSUPPORTED_MDDEV_FLAGS
 
- UNSUPPORTED_REQUEST
 
- UNSUP_CMD
 
- UNSUP_MASK
 
- UNTAGGED
 
- UNTAG_MAP_MASK
 
- UNTAG_MAP_SHIFT
 
- UNTIL
 
- UNTIL_IOCTL
 
- UNTIL_STOP
 
- UNUSABLE
 
- UNUSABLE_ELEMS_PER_PAGE
 
- UNUSED
 
- UNUSED_BLOCK
 
- UNUSED_CMND
 
- UNUSED_ERR
 
- UNUSED_FORMAT
 
- UNUSED_IPS
 
- UNUSED_IRQ
 
- UNUSED_LOADER_MAILBOXES
 
- UNUSED_MSR_REG
 
- UNUSED_REGISTER
 
- UNUSED_REPORT
 
- UNUSUAL_DEV
 
- UNUSUAL_VENDOR_INTF
 
- UNU_FFP
 
- UNU_FFP_MASK
 
- UNWIND
 
- UNWINDER_BUG
 
- UNWINDER_BUG_ON
 
- UNWINDGUARD
 
- UNWIND_ESPFIX_STACK
 
- UNWIND_HINT
 
- UNWIND_HINT_RESTORE
 
- UNWIND_HINT_SAVE
 
- UNWIND_HINT_TYPE_RESTORE
 
- UNWIND_HINT_TYPE_SAVE
 
- UNW_AR_BSP
 
- UNW_AR_BSPSTORE
 
- UNW_AR_CCV
 
- UNW_AR_CSD
 
- UNW_AR_EC
 
- UNW_AR_FPSR
 
- UNW_AR_LC
 
- UNW_AR_PFS
 
- UNW_AR_RNAT
 
- UNW_AR_RSC
 
- UNW_AR_SSD
 
- UNW_AR_UNAT
 
- UNW_BLINK
 
- UNW_CACHE_SIZE
 
- UNW_DEBUG_ON
 
- UNW_DEC_ABI
 
- UNW_DEC_BAD_CODE
 
- UNW_DEC_BR_GR
 
- UNW_DEC_BR_MEM
 
- UNW_DEC_COPY_STATE
 
- UNW_DEC_EPILOGUE
 
- UNW_DEC_FRGR_MEM
 
- UNW_DEC_FR_MEM
 
- UNW_DEC_GR_GR
 
- UNW_DEC_GR_MEM
 
- UNW_DEC_LABEL_STATE
 
- UNW_DEC_MEM_STACK_F
 
- UNW_DEC_MEM_STACK_V
 
- UNW_DEC_PRIUNAT_GR
 
- UNW_DEC_PRIUNAT_PSPREL
 
- UNW_DEC_PRIUNAT_SPREL
 
- UNW_DEC_PRIUNAT_WHEN_GR
 
- UNW_DEC_PRIUNAT_WHEN_MEM
 
- UNW_DEC_PROLOGUE
 
- UNW_DEC_PROLOGUE_GR
 
- UNW_DEC_REG_GR
 
- UNW_DEC_REG_PSPREL
 
- UNW_DEC_REG_SPREL
 
- UNW_DEC_REG_WHEN
 
- UNW_DEC_RESTORE
 
- UNW_DEC_RESTORE_P
 
- UNW_DEC_RP_BR
 
- UNW_DEC_SPILL_BASE
 
- UNW_DEC_SPILL_MASK
 
- UNW_DEC_SPILL_PSPREL
 
- UNW_DEC_SPILL_PSPREL_P
 
- UNW_DEC_SPILL_REG
 
- UNW_DEC_SPILL_REG_P
 
- UNW_DEC_SPILL_SPREL
 
- UNW_DEC_SPILL_SPREL_P
 
- UNW_DEFAULT_RA
 
- UNW_DPRINT
 
- UNW_FLAG_EHANDLER
 
- UNW_FLAG_INTERRUPT_FRAME
 
- UNW_FLAG_MASK
 
- UNW_FLAG_OSMASK
 
- UNW_FLAG_UHANDLER
 
- UNW_FP
 
- UNW_HASH_SIZE
 
- UNW_INSN_ADD
 
- UNW_INSN_ADD_PSP
 
- UNW_INSN_ADD_SP
 
- UNW_INSN_LOAD
 
- UNW_INSN_MOVE
 
- UNW_INSN_MOVE2
 
- UNW_INSN_MOVE_CONST
 
- UNW_INSN_MOVE_SCRATCH
 
- UNW_INSN_MOVE_STACKED
 
- UNW_INSN_SETNAT_MEMSTK
 
- UNW_INSN_SETNAT_TYPE
 
- UNW_LENGTH
 
- UNW_LOG_CACHE_SIZE
 
- UNW_LOG_HASH_SIZE
 
- UNW_MAX_SCRIPT_LEN
 
- UNW_NAT_MEMSTK
 
- UNW_NAT_NONE
 
- UNW_NAT_REGSTK
 
- UNW_NAT_VAL
 
- UNW_NUM_REGS
 
- UNW_PC
 
- UNW_REGISTER_INFO
 
- UNW_REG_B1
 
- UNW_REG_B2
 
- UNW_REG_B3
 
- UNW_REG_B4
 
- UNW_REG_B5
 
- UNW_REG_BSP
 
- UNW_REG_BSPSTORE
 
- UNW_REG_F16
 
- UNW_REG_F17
 
- UNW_REG_F18
 
- UNW_REG_F19
 
- UNW_REG_F2
 
- UNW_REG_F20
 
- UNW_REG_F21
 
- UNW_REG_F22
 
- UNW_REG_F23
 
- UNW_REG_F24
 
- UNW_REG_F25
 
- UNW_REG_F26
 
- UNW_REG_F27
 
- UNW_REG_F28
 
- UNW_REG_F29
 
- UNW_REG_F3
 
- UNW_REG_F30
 
- UNW_REG_F31
 
- UNW_REG_F4
 
- UNW_REG_F5
 
- UNW_REG_FPSR
 
- UNW_REG_LC
 
- UNW_REG_PFS
 
- UNW_REG_PR
 
- UNW_REG_PRI_UNAT_GR
 
- UNW_REG_PRI_UNAT_MEM
 
- UNW_REG_PSP
 
- UNW_REG_R4
 
- UNW_REG_R5
 
- UNW_REG_R6
 
- UNW_REG_R7
 
- UNW_REG_RNAT
 
- UNW_REG_RP
 
- UNW_REG_UNAT
 
- UNW_SP
 
- UNW_STATS
 
- UNW_VER
 
- UNW_WHEN_NEVER
 
- UNW_WHERE_BR
 
- UNW_WHERE_FR
 
- UNW_WHERE_GR
 
- UNW_WHERE_GR_SAVE
 
- UNW_WHERE_NONE
 
- UNW_WHERE_PSPREL
 
- UNW_WHERE_SPILL_HOME
 
- UNW_WHERE_SPREL
 
- UNXSPLCPLERR_F
 
- UNXSPLCPLERR_S
 
- UNXSPLCPLERR_V
 
- UNX_CALLSLACK
 
- UNX_MAXNODENAME
 
- UNX_NGROUPS
 
- UN_BIC
 
- UN_BIS
 
- UN_IN
 
- UN_MAPPED
 
- UN_OUT
 
- UN_REG
 
- UOC_CON0
 
- UOC_CON0_COMMON_ON_N
 
- UOC_CON0_DISABLE
 
- UOC_CON0_SIDDQ
 
- UOC_CON2
 
- UOC_CON2_SOFT_CON_SEL
 
- UOC_CON3
 
- UOC_CON3_UTMI_OPMODE_MASK
 
- UOC_CON3_UTMI_OPMODE_NODRIVING
 
- UOC_CON3_UTMI_SUSPENDN
 
- UOC_CON3_UTMI_TERMSEL_FULLSPEED
 
- UOC_CON3_UTMI_XCVRSEELCT_FSTRANSC
 
- UOC_CON3_UTMI_XCVRSEELCT_MASK
 
- UOS_MOVE
 
- UOS_RSA_SCRATCH
 
- UOS_RSA_SCRATCH_COUNT
 
- UP
 
- UP2AC
 
- UP2OCR
 
- UP2OCR_CPVEN
 
- UP2OCR_CPVPE
 
- UP2OCR_DMPDE
 
- UP2OCR_DMPUBE
 
- UP2OCR_DMPUE
 
- UP2OCR_DPPDE
 
- UP2OCR_DPPUBE
 
- UP2OCR_DPPUE
 
- UP2OCR_EXSP
 
- UP2OCR_EXSUS
 
- UP2OCR_HXOE
 
- UP2OCR_HXS
 
- UP2OCR_IDON
 
- UP2OCR_SEOS
 
- UP3OCR
 
- UP8TERM
 
- UPACCNONZERO_F
 
- UPACCNONZERO_S
 
- UPACCNONZERO_V
 
- UPAGES
 
- UPARG
 
- UPA_CONFIG_MID
 
- UPA_CONFIG_PCAP
 
- UPA_CONFIG_PCON
 
- UPA_CONFIG_RESV
 
- UPA_PORTID_ECCVALID
 
- UPA_PORTID_FNP
 
- UPA_PORTID_ID
 
- UPA_PORTID_ONEREAD
 
- UPA_PORTID_PINTRDQ
 
- UPA_PORTID_PREQDQ
 
- UPA_PORTID_PREQRD
 
- UPA_PORTID_RESV
 
- UPA_PORTID_UPACAP
 
- UPCALL_BUF_LEN
 
- UPCI_AIOP_INTR_BITS
 
- UPCI_AIOP_INTR_BIT_0
 
- UPCI_AIOP_INTR_BIT_1
 
- UPCI_AIOP_INTR_BIT_2
 
- UPCI_AIOP_INTR_BIT_3
 
- UPCOMING_RUNTIME_D3
 
- UPCRCKO0
 
- UPCRCKO1
 
- UPCRST_F
 
- UPCRST_S
 
- UPCRST_V
 
- UPD29F064115
 
- UPD60620_PHY_ID
 
- UPD64031A_3DYCS_COMPOSITE
 
- UPD64031A_3DYCS_DISABLE
 
- UPD64031A_3DYCS_SVIDEO
 
- UPD64031A_COMPOSITE_EXTERNAL
 
- UPD64031A_GR_OFF
 
- UPD64031A_GR_ON
 
- UPD64031A_GR_THROUGH
 
- UPD64031A_VERTICAL_EXTERNAL
 
- UPD64083_EXT_Y_ADC
 
- UPD64083_MNNR_MODE
 
- UPD64083_YCNR_MODE
 
- UPD64083_YCS_MODE
 
- UPD64083_YCS_PLUS_MODE
 
- UPD720100_INTA_IRQ
 
- UPD720100_INTA_PIN
 
- UPD720100_INTB_IRQ
 
- UPD720100_INTB_PIN
 
- UPD720100_INTC_IRQ
 
- UPD720100_INTC_PIN
 
- UPD78F0730_BREAK
 
- UPD78F0730_CMD_LINE_CONTROL
 
- UPD78F0730_CMD_OPEN_CLOSE
 
- UPD78F0730_CMD_SET_DTR_RTS
 
- UPD78F0730_CMD_SET_ERR_CHR
 
- UPD78F0730_CMD_SET_XON_XOFF_CHR
 
- UPD78F0730_DATA_SIZE_7_BITS
 
- UPD78F0730_DATA_SIZE_8_BITS
 
- UPD78F0730_DATA_SIZE_MASK
 
- UPD78F0730_DTR
 
- UPD78F0730_ERR_CHR_DISABLED
 
- UPD78F0730_ERR_CHR_ENABLED
 
- UPD78F0730_FLOW_CONTROL_HW
 
- UPD78F0730_FLOW_CONTROL_MASK
 
- UPD78F0730_FLOW_CONTROL_NONE
 
- UPD78F0730_FLOW_CONTROL_SW
 
- UPD78F0730_PARITY_EVEN
 
- UPD78F0730_PARITY_MASK
 
- UPD78F0730_PARITY_NONE
 
- UPD78F0730_PARITY_ODD
 
- UPD78F0730_PORT_CLOSE
 
- UPD78F0730_PORT_OPEN
 
- UPD78F0730_RTS
 
- UPD78F0730_STOP_BIT_1_BIT
 
- UPD78F0730_STOP_BIT_2_BIT
 
- UPD78F0730_STOP_BIT_MASK
 
- UPDATE
 
- UPDATEDELIVERY_INTERRUPT_X
 
- UPDATES_PER_WINDOW
 
- UPDATE_ASSOC_IES
 
- UPDATE_ATM_SIGNAL
 
- UPDATE_ATM_STAT
 
- UPDATE_AUTH_TYPE
 
- UPDATE_BACKREF
 
- UPDATE_BLOCK
 
- UPDATE_CHANNEL_LIST
 
- UPDATE_CIE_SRC
 
- UPDATE_CIE_WATCHDOG
 
- UPDATE_CLASSID_BATCH
 
- UPDATE_COEF
 
- UPDATE_COEFEX
 
- UPDATE_COUNTER
 
- UPDATE_DATA_PTRS
 
- UPDATE_DCB
 
- UPDATE_DCB_DSCP
 
- UPDATE_DECODE_VARIABLES
 
- UPDATE_DSCP
 
- UPDATE_DT_NODE
 
- UPDATE_ENCODE_VARIABLES
 
- UPDATE_ESTAT
 
- UPDATE_ESTAT_QSTAT
 
- UPDATE_ESTAT_QSTAT_64
 
- UPDATE_EVENT_COUNTER
 
- UPDATE_EXTEND_E_TSTAT
 
- UPDATE_EXTEND_E_USTAT
 
- UPDATE_EXTEND_STAT
 
- UPDATE_EXTEND_TSTAT
 
- UPDATE_EXTEND_TSTAT_X
 
- UPDATE_EXTEND_USTAT
 
- UPDATE_EXTEND_XSTAT
 
- UPDATE_FILE_MODE
 
- UPDATE_FILS_ERP_INFO
 
- UPDATE_FIRST
 
- UPDATE_FREQUENCY
 
- UPDATE_FSTAT_QSTAT
 
- UPDATE_FW_STAT
 
- UPDATE_FW_STAT_OLD
 
- UPDATE_HASH
 
- UPDATE_HEAD
 
- UPDATE_INO
 
- UPDATE_INTERVAL
 
- UPDATE_IRQ_MASK
 
- UPDATE_IRQ_TYPE
 
- UPDATE_LOCKED
 
- UPDATE_MU_GROUPS_CMD
 
- UPDATE_NEW
 
- UPDATE_OLD
 
- UPDATE_PENDING
 
- UPDATE_PROPERTY
 
- UPDATE_PTR_LEFT
 
- UPDATE_PULSE_ASLEEP
 
- UPDATE_PULSE_AWAKE
 
- UPDATE_PULSE_MODE
 
- UPDATE_QSTAT
 
- UPDATE_QSTAT_OLD
 
- UPDATE_REQUEST
 
- UPDATE_STAT64
 
- UPDATE_STAT64_NIG
 
- UPDATE_STATIC_BRIGHTNESS
 
- UPDATE_TG
 
- UPDATE_TYPE_FAST
 
- UPDATE_TYPE_FULL
 
- UPDATE_TYPE_MED
 
- UPDATE_UNLOCKED
 
- UPDATE_VAL
 
- UPDATE_VF_COUNTER
 
- UPDATE_VF_COUNTER_32bit
 
- UPDATE_VF_COUNTER_36bit
 
- UPDATE_VTIME
 
- UPDBGLACAPTPCONLY_F
 
- UPDBGLACAPTPCONLY_S
 
- UPDBGLACAPTPCONLY_V
 
- UPDBGLAEN_F
 
- UPDBGLAEN_S
 
- UPDBGLAEN_V
 
- UPDBGLARDEN_F
 
- UPDBGLARDEN_S
 
- UPDBGLARDEN_V
 
- UPDBGLARDPTR_M
 
- UPDBGLARDPTR_S
 
- UPDBGLARDPTR_V
 
- UPDBGLAWRPTR_G
 
- UPDBGLAWRPTR_M
 
- UPDBGLAWRPTR_S
 
- UPDCHN0_F
 
- UPDCHN0_S
 
- UPDCHN0_V
 
- UPDCHN1_F
 
- UPDCHN1_S
 
- UPDCHN1_V
 
- UPDCHN2_F
 
- UPDCHN2_S
 
- UPDCHN2_V
 
- UPDCHN3_F
 
- UPDCHN3_S
 
- UPDCHN3_V
 
- UPDOWN
 
- UPDT_OFST
 
- UPDVLD_F
 
- UPDVLD_S
 
- UPDVLD_V
 
- UPD_IMMEDIATE
 
- UPD_REG
 
- UPF_AUTO_CTS
 
- UPF_AUTO_IRQ
 
- UPF_AUTO_RTS
 
- UPF_BOOT_AUTOCONF
 
- UPF_BUGGY_UART
 
- UPF_BUG_THRE
 
- UPF_CHANGE_MASK
 
- UPF_CONS_FLOW
 
- UPF_DEAD
 
- UPF_EXAR_EFR
 
- UPF_FIXED_PORT
 
- UPF_FIXED_TYPE
 
- UPF_FOURPORT
 
- UPF_HARDPPS_CD
 
- UPF_HARD_FLOW
 
- UPF_IOREMAP
 
- UPF_LOW_LATENCY
 
- UPF_MAGIC_MULTIPLIER
 
- UPF_NO_THRE_TEST
 
- UPF_SAK
 
- UPF_SHARE_IRQ
 
- UPF_SKIP_TEST
 
- UPF_SOFT_FLOW
 
- UPF_SPD_CUST
 
- UPF_SPD_HI
 
- UPF_SPD_MASK
 
- UPF_SPD_SHI
 
- UPF_SPD_VHI
 
- UPF_SPD_WARP
 
- UPF_TXX9_HAVE_CTS_LINE
 
- UPF_TXX9_USE_SCLK
 
- UPF_USR_MASK
 
- UPGCR_ADDR
 
- UPGCR_DIAG
 
- UPGCR_PROTOCOL
 
- UPGCR_RMS
 
- UPGCR_TMS
 
- UPHY_SUSB
 
- UPIO_AU
 
- UPIO_HUB6
 
- UPIO_MEM
 
- UPIO_MEM16
 
- UPIO_MEM32
 
- UPIO_MEM32BE
 
- UPIO_PORT
 
- UPIO_TSI
 
- UPIU_CMD_FLAGS_NONE
 
- UPIU_CMD_FLAGS_READ
 
- UPIU_CMD_FLAGS_WRITE
 
- UPIU_COMMAND_SET_TYPE_QUERY
 
- UPIU_COMMAND_SET_TYPE_SCSI
 
- UPIU_COMMAND_SET_TYPE_UFS
 
- UPIU_COMMAND_TYPE_OFFSET
 
- UPIU_HEADER_DWORD
 
- UPIU_INCORRECT_LOGICAL_UNIT_NO
 
- UPIU_QUERY_FUNC_STANDARD_READ_REQUEST
 
- UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST
 
- UPIU_QUERY_OPCODE_CLEAR_FLAG
 
- UPIU_QUERY_OPCODE_NOP
 
- UPIU_QUERY_OPCODE_READ_ATTR
 
- UPIU_QUERY_OPCODE_READ_DESC
 
- UPIU_QUERY_OPCODE_READ_FLAG
 
- UPIU_QUERY_OPCODE_SET_FLAG
 
- UPIU_QUERY_OPCODE_TOGGLE_FLAG
 
- UPIU_QUERY_OPCODE_WRITE_ATTR
 
- UPIU_QUERY_OPCODE_WRITE_DESC
 
- UPIU_RSP_CODE_OFFSET
 
- UPIU_TASK_ATTR_ACA
 
- UPIU_TASK_ATTR_HEADQ
 
- UPIU_TASK_ATTR_ORDERED
 
- UPIU_TASK_ATTR_SIMPLE
 
- UPIU_TASK_MANAGEMENT_FUNC_COMPL
 
- UPIU_TASK_MANAGEMENT_FUNC_FAILED
 
- UPIU_TASK_MANAGEMENT_FUNC_NOT_SUPPORTED
 
- UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED
 
- UPIU_TRANSACTION_COMMAND
 
- UPIU_TRANSACTION_DATA_IN
 
- UPIU_TRANSACTION_DATA_OUT
 
- UPIU_TRANSACTION_NOP_IN
 
- UPIU_TRANSACTION_NOP_OUT
 
- UPIU_TRANSACTION_QUERY_REQ
 
- UPIU_TRANSACTION_QUERY_RSP
 
- UPIU_TRANSACTION_READY_XFER
 
- UPIU_TRANSACTION_REJECT_UPIU
 
- UPIU_TRANSACTION_RESPONSE
 
- UPIU_TRANSACTION_TASK_REQ
 
- UPIU_TRANSACTION_TASK_RSP
 
- UPIU_TRANSACTION_UIC_CMD
 
- UPLD_IIC
 
- UPLINK_REP_INDEX
 
- UPLINK_TRAFFIC
 
- UPLL
 
- UPLLCLK
 
- UPLLCON
 
- UPLLE
 
- UPLL_BYPASS_CNTL
 
- UPLL_BYPASS_EN_MASK
 
- UPLL_CON0
 
- UPLL_CTLACK2_MASK
 
- UPLL_CTLACK_MASK
 
- UPLL_CTLREQ_MASK
 
- UPLL_DIV
 
- UPLL_DIVEN2_MASK
 
- UPLL_DIVEN_MASK
 
- UPLL_FB_DIV
 
- UPLL_FB_DIV_MASK
 
- UPLL_LOCK
 
- UPLL_PDIV_A
 
- UPLL_PDIV_A_MASK
 
- UPLL_PDIV_B
 
- UPLL_PDIV_B_MASK
 
- UPLL_REFCLK_SRC_SEL_MASK
 
- UPLL_REF_DIV
 
- UPLL_REF_DIV_MASK
 
- UPLL_RESET_MASK
 
- UPLL_SLEEP_MASK
 
- UPLL_SPARE_ISPARE9
 
- UPLL_SW_HILEN
 
- UPLL_SW_HILEN2
 
- UPLL_SW_LOLEN
 
- UPLL_SW_LOLEN2
 
- UPLL_SW_MASK
 
- UPLL_VCO_MODE_MASK
 
- UPLOAD
 
- UPLOAD_SUBCH
 
- UPLSTR0
 
- UPLSTR1
 
- UPORT_EVENT_LSR
 
- UPORT_EVENT_MCR
 
- UPORT_EVENT_MSR
 
- UPORT_EVENT_NONE
 
- UPORT_EVENT_SEND_NEXT
 
- UPORT_EVENT_TXBUF_THRESHOLD
 
- UPPER
 
- UPPERCASE
 
- UPPER_20_ENABLE
 
- UPPER_5G_SUB_BAND_START
 
- UPPER_8_BITS
 
- UPPER_BIT_RUBIN
 
- UPPER_DATA
 
- UPPER_GPIO_ENABLE
 
- UPPER_GROUP
 
- UPPER_HEAD
 
- UPPER_LIMIT_TH
 
- UPPER_NIBBLE
 
- UPPER_STATUS_0
 
- UPPER_STATUS_1
 
- UPPER_STATUS_10
 
- UPPER_STATUS_11
 
- UPPER_STATUS_12
 
- UPPER_STATUS_13
 
- UPPER_STATUS_14
 
- UPPER_STATUS_15
 
- UPPER_STATUS_2
 
- UPPER_STATUS_3
 
- UPPER_STATUS_4
 
- UPPER_STATUS_5
 
- UPPER_STATUS_6
 
- UPPER_STATUS_7
 
- UPPER_STATUS_8
 
- UPPER_STATUS_9
 
- UPPER_STATUS_CLR
 
- UPPHUB
 
- UPQ_NO_TXEN_TEST
 
- UPROBES_BRK_IMM
 
- UPROBES_HASH_SZ
 
- UPROBES_TRAP
 
- UPROBE_BRK_UPROBE
 
- UPROBE_BRK_UPROBE_XOL
 
- UPROBE_COPY_INSN
 
- UPROBE_EVENT_SYSTEM
 
- UPROBE_FILTER_MMAP
 
- UPROBE_FILTER_REGISTER
 
- UPROBE_FILTER_UNREGISTER
 
- UPROBE_FIX_CALL
 
- UPROBE_FIX_IP
 
- UPROBE_FIX_RIP_BX
 
- UPROBE_FIX_RIP_DI
 
- UPROBE_FIX_RIP_MASK
 
- UPROBE_FIX_RIP_SI
 
- UPROBE_FIX_SETF
 
- UPROBE_HANDLER_MASK
 
- UPROBE_HANDLER_REMOVE
 
- UPROBE_INV_FAULT_CODE
 
- UPROBE_SS_ARM_INSN
 
- UPROBE_STP_INSN
 
- UPROBE_SWBP_ARM_INSN
 
- UPROBE_SWBP_INSN
 
- UPROBE_SWBP_INSN_SIZE
 
- UPROBE_TRAP_NR
 
- UPROBE_XOL_SLOT_BYTES
 
- UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE
 
- UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_PAUSE_WHEN_EMERGENCY
 
- UPSTAT_AUTOCTS
 
- UPSTAT_AUTORTS
 
- UPSTAT_AUTOXOFF
 
- UPSTAT_CTS_ENABLE
 
- UPSTAT_DCD_ENABLE
 
- UPSTAT_SYNC_FIFO
 
- UPSTREAM_KEEP
 
- UPSTREAM_REMOVE
 
- UPS_EN
 
- UPS_FLAGS_250M_CKDIV
 
- UPS_FLAGS_CTAP_SHORT_DIS
 
- UPS_FLAGS_EEE_CMOD_LV_EN
 
- UPS_FLAGS_EEE_PLLOFF_100
 
- UPS_FLAGS_EEE_PLLOFF_GIGA
 
- UPS_FLAGS_EN_10M_CKDIV
 
- UPS_FLAGS_EN_500M_EEE
 
- UPS_FLAGS_EN_ALDPS
 
- UPS_FLAGS_EN_EEE
 
- UPS_FLAGS_EN_EEE_CKDIV
 
- UPS_FLAGS_EN_FLOW_CTR
 
- UPS_FLAGS_EN_GREEN
 
- UPS_FLAGS_R_TUNE
 
- UPT1_F_LRO
 
- UPT1_F_RSS
 
- UPT1_F_RXCSUM
 
- UPT1_F_RXVLAN
 
- UPT1_IML_ADAPTIVE
 
- UPT1_IML_HIGHEST
 
- UPT1_IML_NONE
 
- UPT1_RSSConf
 
- UPT1_RSS_HASH_FUNC_NONE
 
- UPT1_RSS_HASH_FUNC_TOEPLITZ
 
- UPT1_RSS_HASH_TYPE_IPV4
 
- UPT1_RSS_HASH_TYPE_IPV6
 
- UPT1_RSS_HASH_TYPE_NONE
 
- UPT1_RSS_HASH_TYPE_TCP_IPV4
 
- UPT1_RSS_HASH_TYPE_TCP_IPV6
 
- UPT1_RSS_MAX_IND_TABLE_SIZE
 
- UPT1_RSS_MAX_KEY_SIZE
 
- UPT1_RxStats
 
- UPT1_TxStats
 
- UPT_AX
 
- UPT_BP
 
- UPT_BX
 
- UPT_CS
 
- UPT_CX
 
- UPT_DI
 
- UPT_DS
 
- UPT_DX
 
- UPT_EFLAGS
 
- UPT_ES
 
- UPT_FAULTINFO
 
- UPT_IP
 
- UPT_IS_USER
 
- UPT_R10
 
- UPT_R11
 
- UPT_R12
 
- UPT_R13
 
- UPT_R14
 
- UPT_R15
 
- UPT_R8
 
- UPT_R9
 
- UPT_RESTART_SYSCALL
 
- UPT_SI
 
- UPT_SP
 
- UPT_SS
 
- UPT_SYSCALL_ARG1
 
- UPT_SYSCALL_ARG2
 
- UPT_SYSCALL_ARG3
 
- UPT_SYSCALL_ARG4
 
- UPT_SYSCALL_ARG5
 
- UPT_SYSCALL_ARG6
 
- UPT_SYSCALL_NR
 
- UP_CACHE_SIZE
 
- UP_CNT
 
- UP_DOWN_MIXER_MAX_COEFF
 
- UP_IBQ_0_RDADDR_A
 
- UP_IBQ_0_SHADOW_RDADDR_A
 
- UP_INT_EN
 
- UP_LD_CMD_PORT_HOST_INT_STATUS
 
- UP_LD_HOST_INT_MASK
 
- UP_LD_HOST_INT_STATUS
 
- UP_LINK
 
- UP_OBQ_0_REALADDR_A
 
- UP_OBQ_0_SHADOW_REALADDR_A
 
- UP_SCALE_MAX
 
- UP_UNALIGNED
 
- UP_UP_DBG_LA_CFG_A
 
- UP_UP_DBG_LA_DATA_A
 
- UQEN
 
- UQItype
 
- UR
 
- UR8_REGS_CLOCKS
 
- UR8_REGS_UART1
 
- UR8_REGS_WDT
 
- URA
 
- URB
 
- URBS_AsyncSeq
 
- URB_ALIGNED_TEMP_BUFFER
 
- URB_ASYNC_UNLINK
 
- URB_BUF
 
- URB_BUFSIZE
 
- URB_COUNT
 
- URB_DBG
 
- URB_DEL
 
- URB_DIR_IN
 
- URB_DIR_MASK
 
- URB_DIR_OUT
 
- URB_DMA_MAP_PAGE
 
- URB_DMA_MAP_SG
 
- URB_DMA_MAP_SINGLE
 
- URB_DMA_SG_COMBINED
 
- URB_DataLen_AsyncSeq
 
- URB_FREE_BUFFER
 
- URB_GIVEBACK_ASAP
 
- URB_INPROGRESS
 
- URB_INT_LED_DELAY
 
- URB_ISO_ASAP
 
- URB_MAP_LOCAL
 
- URB_MAX_CTRL_SIZE
 
- URB_NOTSHORT
 
- URB_NO_INTERRUPT
 
- URB_NO_TRANSFER_DMA_MAP
 
- URB_SEND_ZERO_PACKET
 
- URB_SETUP_MAP_LOCAL
 
- URB_SETUP_MAP_SINGLE
 
- URB_SHORT_NOT_OK
 
- URB_SIZE
 
- URB_SUBMIT_DELAY
 
- URB_TRACE
 
- URB_TRANSFER_BUFFER_SIZE
 
- URB_UPPER_LIMIT
 
- URB_ZERO_PACKET
 
- URC
 
- URCCMD
 
- URCCMDADDR
 
- URCCMD_ACTIVE
 
- URCCMD_EARV
 
- URCCMD_IWR
 
- URCCMD_RESET
 
- URCCMD_RS
 
- URCCMD_SIZE_MASK
 
- URCCR
 
- URCEVTADDR
 
- URCEVTADDR_OFFSET_MASK
 
- URCINTR
 
- URCINTR_EN_ALL
 
- URCNTH
 
- URCNTL
 
- URCSTS
 
- URCSTS_EPS
 
- URCSTS_ER
 
- URCSTS_HALTED
 
- URCSTS_HSE
 
- URCSTS_INT_MASK
 
- URCSTS_ISI
 
- URCSTS_RCI
 
- URC_CONTINUE_UNWIND
 
- URC_FAILURE
 
- URC_OK
 
- URD_CODE
 
- UREGS
 
- UREG_CHICK
 
- UREG_CHICK_MSIX_ENABLE
 
- UREG_CHICK_MSI_ENABLE
 
- UREG_CPU_INIT_RUN
 
- UREG_DOORBELL_TO_ISR6
 
- UREG_DOORBELL_TO_ISR6_NMI_BIT
 
- UREG_DOORBELL_TO_ISR6_RESUME
 
- UREG_DOORBELL_TO_ISR6_SUSPEND
 
- UREG_FP
 
- UREG_G0
 
- UREG_G1
 
- UREG_G2
 
- UREG_G3
 
- UREG_G4
 
- UREG_G5
 
- UREG_G6
 
- UREG_G7
 
- UREG_I0
 
- UREG_I1
 
- UREG_I2
 
- UREG_I3
 
- UREG_I4
 
- UREG_I5
 
- UREG_I6
 
- UREG_I7
 
- UREG_NIC_SET_NMI_DRIVER
 
- UREG_NIC_SET_NMI_DRIVER_NMI_FROM_DRIVER_MSK
 
- UREG_RETPC
 
- UREG_UCODE_LOAD_STATUS
 
- URT
 
- URTX0
 
- URT_INT
 
- URT_SLP_REG
 
- URX
 
- URXD0
 
- URXD_BRK
 
- URXD_CHARRDY
 
- URXD_DUMMY_READ
 
- URXD_ERR
 
- URXD_FRMERR
 
- URXD_OVRRUN
 
- URXD_PRERR
 
- URXD_RX_DATA
 
- URX_ADDR
 
- URX_BREAK
 
- URX_DATA_READY
 
- URX_FIFO_FULL
 
- URX_FIFO_HALF
 
- URX_FRAME_ERROR
 
- URX_OLD_DATA
 
- URX_OVRUN
 
- URX_PARITY_ERROR
 
- URX_RXDATA
 
- URX_RXDATA_ADDR
 
- URX_RXDATA_MASK
 
- URX_RXDATA_SHIFT
 
- UR_MAJOR
 
- UR_MASK
 
- UR_REG_IMM
 
- UR_REG_IMM_MAX
 
- UR_REG_IMM_encode
 
- UR_REG_LM
 
- UR_REG_LM_IDX
 
- UR_REG_LM_IDX_MAX
 
- UR_REG_LM_POST_MOD
 
- UR_REG_LM_POST_MOD_DEC
 
- UR_REG_NN
 
- UR_REG_NO_DST
 
- UR_REG_XFR
 
- UR_SHIFT
 
- US122L
 
- US122L_FLAG_US144
 
- US122L_H
 
- US2BCLK
 
- US3_CYCLE_CNT
 
- US3_CYCLE_CNT_D1
 
- US3_DC_RD
 
- US3_DC_RD_MISS
 
- US3_DC_WR
 
- US3_DC_WR_MISS
 
- US3_DISPATCH0_2ND_BR
 
- US3_DISPATCH0_BR_TGT
 
- US3_DISPATCH0_IC_MISS
 
- US3_DISPATCH0_MISPRED
 
- US3_DISP_RS_MISPRED
 
- US3_DTLB_MISS
 
- US3_EC_IC_MISS
 
- US3_EC_MISSES
 
- US3_EC_RD_MISS
 
- US3_EC_REF
 
- US3_EC_SNOOP_CB
 
- US3_EC_SNOOP_INV
 
- US3_EC_WB
 
- US3_EC_WR_HIT_RTO
 
- US3_FA_PIPE_COMPL
 
- US3_FM_PIPE_COMPLETION
 
- US3_IC_MISS
 
- US3_IC_MISS_CANCELLED
 
- US3_IC_REF
 
- US3_INSTR_CNT
 
- US3_INSTR_CNT_D1
 
- US3_ITLB_MISS
 
- US3_IU_BR_COUNT_TAKEN
 
- US3_IU_BR_MISS_TAKEN
 
- US3_IU_STAT_BR_COUNT_UNTAKEN
 
- US3_IU_STAT_BR_MIS_UNTAKEN
 
- US3_MC_READS_0
 
- US3_MC_READS_1
 
- US3_MC_READS_2
 
- US3_MC_READS_3
 
- US3_MC_STALLS_0
 
- US3_MC_STALLS_1
 
- US3_MC_STALLS_2
 
- US3_MC_STALLS_3
 
- US3_MC_WRITES_0
 
- US3_MC_WRITES_1
 
- US3_MC_WRITES_2
 
- US3_MC_WRITES_3
 
- US3_PC_HARD_HIT
 
- US3_PC_MS_MISSES
 
- US3_PC_PORT0_RD
 
- US3_PC_PORT1_RD
 
- US3_PC_SNOOP_INV
 
- US3_PC_SOFT_HIT
 
- US3_RE_DC_MISS
 
- US3_RE_EC_MISS
 
- US3_RE_ENDIAN_MISS
 
- US3_RE_FPU_BYPASS
 
- US3_RE_PC_MISS
 
- US3_RE_RAW_MISS
 
- US3_RSTALL_FP_USE
 
- US3_RSTALL_IU_USE
 
- US3_RSTALL_STOREQ
 
- US3_SI_CIQ_FLOW
 
- US3_SI_OWNED
 
- US3_SI_SNOOP
 
- US3_SW_COUNT_0
 
- US3_SW_COUNT_1
 
- US3_WC_MISS
 
- US3_WC_SCRUBBED
 
- US3_WC_SNOOP_CB
 
- US3_WC_WB_WO_READ
 
- US5182D_AGAIN_MASK
 
- US5182D_ALS_ONLY
 
- US5182D_ALS_PX
 
- US5182D_CFG0_ONESHOT_EN
 
- US5182D_CFG0_PROX
 
- US5182D_CFG0_PX_IRQ
 
- US5182D_CFG0_SHUTDOWN_EN
 
- US5182D_CFG0_WORD_ENABLE
 
- US5182D_CFG1_AGAIN_DEFAULT
 
- US5182D_CFG1_ALS_RES16
 
- US5182D_CFG2_PXGAIN_DEFAULT
 
- US5182D_CFG2_PX_RES16
 
- US5182D_CFG3_INT_SOURCE_PX
 
- US5182D_CFG3_LED_CURRENT100
 
- US5182D_CHIPID
 
- US5182D_CONTINUOUS
 
- US5182D_DRV_NAME
 
- US5182D_GA_RESOLUTION
 
- US5182D_ONESHOT
 
- US5182D_OPMODE_ALS
 
- US5182D_OPMODE_MASK
 
- US5182D_OPMODE_PX
 
- US5182D_OPMODE_SHIFT
 
- US5182D_OPSTORE_SLEEP_TIME
 
- US5182D_PXH_TH_DISABLE
 
- US5182D_PXL_TH_DISABLE
 
- US5182D_PX_ONLY
 
- US5182D_READ_BYTE
 
- US5182D_READ_WORD
 
- US5182D_REG_ADL
 
- US5182D_REG_AUTO_HDARK_GAIN
 
- US5182D_REG_AUTO_HDARK_GAIN_DEFAULT
 
- US5182D_REG_AUTO_LDARK_GAIN
 
- US5182D_REG_AUTO_LDARK_GAIN_DEFAULT
 
- US5182D_REG_CFG0
 
- US5182D_REG_CFG1
 
- US5182D_REG_CFG2
 
- US5182D_REG_CFG3
 
- US5182D_REG_CFG4
 
- US5182D_REG_CHIPID
 
- US5182D_REG_DARK_AUTO_EN
 
- US5182D_REG_DARK_AUTO_EN_DEFAULT
 
- US5182D_REG_MODE_STORE
 
- US5182D_REG_PDL
 
- US5182D_REG_PXH_TH
 
- US5182D_REG_PXH_TH_DEFAULT
 
- US5182D_REG_PXL_TH
 
- US5182D_REG_PXL_TH_DEFAULT
 
- US5182D_REG_UDARK_TH
 
- US5182D_RESET_CHIP
 
- US5182D_SLEEP_MS
 
- US5182D_STORE_MODE
 
- USA
 
- USABLE_ELEMS_PER_PAGE
 
- USABLE_HV
 
- USABLE_OS
 
- USABLE_PR
 
- USAGE_COMMON_LONG_OPTS
 
- USAGE_COMMON_OPTS_HELP
 
- USAGE_COMMON_SHORT_OPTS
 
- USAGE_GAP
 
- USAGE_OPTS_WIDTH
 
- USAGE_STR
 
- USAGE_TYPE_MSG
 
- USART1
 
- USART1_CK
 
- USART1_K
 
- USART1_R
 
- USART2
 
- USART2_CK
 
- USART2_K
 
- USART2_R
 
- USART3
 
- USART3_CK
 
- USART3_K
 
- USART3_R
 
- USART6
 
- USART6_CK
 
- USART6_K
 
- USART6_R
 
- USART7_CK
 
- USART8_CK
 
- USART_BRR_04_R_SHIFT
 
- USART_BRR_DIV_F_MASK
 
- USART_BRR_DIV_M_MASK
 
- USART_BRR_DIV_M_SHIFT
 
- USART_CR1_CMIE
 
- USART_CR1_DEAT_MASK
 
- USART_CR1_DEAT_SHIFT
 
- USART_CR1_DEDT_MASK
 
- USART_CR1_DEDT_SHIFT
 
- USART_CR1_EOBIE
 
- USART_CR1_FIFOEN
 
- USART_CR1_IDLEIE
 
- USART_CR1_IE_MASK
 
- USART_CR1_M0
 
- USART_CR1_M1
 
- USART_CR1_MME
 
- USART_CR1_OVER8
 
- USART_CR1_PCE
 
- USART_CR1_PEIE
 
- USART_CR1_PS
 
- USART_CR1_RE
 
- USART_CR1_RTOIE
 
- USART_CR1_RWU
 
- USART_CR1_RXNEIE
 
- USART_CR1_SBK
 
- USART_CR1_TCIE
 
- USART_CR1_TE
 
- USART_CR1_TXEIE
 
- USART_CR1_UESM
 
- USART_CR1_WAKE
 
- USART_CR2_ABREN
 
- USART_CR2_ABRMOD_MASK
 
- USART_CR2_ADDM7
 
- USART_CR2_ADD_F7_MASK
 
- USART_CR2_ADD_MASK
 
- USART_CR2_CLKEN
 
- USART_CR2_CPHA
 
- USART_CR2_CPOL
 
- USART_CR2_DATAINV
 
- USART_CR2_LBCL
 
- USART_CR2_LINEN
 
- USART_CR2_MSBFIRST
 
- USART_CR2_RTOEN
 
- USART_CR2_RXINV
 
- USART_CR2_STOP_2B
 
- USART_CR2_STOP_MASK
 
- USART_CR2_SWAP
 
- USART_CR2_TXINV
 
- USART_CR3_CTSE
 
- USART_CR3_CTSIE
 
- USART_CR3_DDRE
 
- USART_CR3_DEM
 
- USART_CR3_DEP
 
- USART_CR3_DMAR
 
- USART_CR3_DMAT
 
- USART_CR3_EIE
 
- USART_CR3_HDSEL
 
- USART_CR3_IREN
 
- USART_CR3_IRLP
 
- USART_CR3_NACK
 
- USART_CR3_ONEBIT
 
- USART_CR3_OVRDIS
 
- USART_CR3_RTSE
 
- USART_CR3_RXFTCFG_HALF
 
- USART_CR3_RXFTCFG_MASK
 
- USART_CR3_RXFTCFG_SHIFT
 
- USART_CR3_RXFTIE
 
- USART_CR3_SCARCNT_MASK
 
- USART_CR3_SCEN
 
- USART_CR3_TCBGTIE
 
- USART_CR3_TXFTCFG_HALF
 
- USART_CR3_TXFTCFG_MASK
 
- USART_CR3_TXFTCFG_SHIFT
 
- USART_CR3_TXFTIE
 
- USART_CR3_WUFIE
 
- USART_CR3_WUS_MASK
 
- USART_CR3_WUS_START_BIT
 
- USART_CR_TC
 
- USART_DR_MASK
 
- USART_GTPR_GT_MASK
 
- USART_GTPR_PSC_MASK
 
- USART_ICR_CMCF
 
- USART_ICR_CTSCF
 
- USART_ICR_EOBCF
 
- USART_ICR_FECF
 
- USART_ICR_IDLECF
 
- USART_ICR_ORECF
 
- USART_ICR_PECF
 
- USART_ICR_RTOCF
 
- USART_ICR_TCCF
 
- USART_ICR_WUCF
 
- USART_RQR_ABRRQ
 
- USART_RQR_MMRQ
 
- USART_RQR_RXFRQ
 
- USART_RQR_SBKRQ
 
- USART_RQR_TXFRQ
 
- USART_RTOR_BLEN_MASK
 
- USART_RTOR_RTO_MASK
 
- USART_SR_ABRE
 
- USART_SR_ABRF
 
- USART_SR_BUSY
 
- USART_SR_CMF
 
- USART_SR_CTS
 
- USART_SR_CTSIF
 
- USART_SR_DUMMY_RX
 
- USART_SR_EOBF
 
- USART_SR_ERR_MASK
 
- USART_SR_FE
 
- USART_SR_IDLE
 
- USART_SR_NF
 
- USART_SR_ORE
 
- USART_SR_PE
 
- USART_SR_RTOF
 
- USART_SR_RXNE
 
- USART_SR_SBKF
 
- USART_SR_TC
 
- USART_SR_TEACK
 
- USART_SR_TXE
 
- USART_SR_WUF
 
- USAT
 
- USAT_CTRL_BYTE
 
- USA_DATABITS_5
 
- USA_DATABITS_6
 
- USA_DATABITS_7
 
- USA_DATABITS_8
 
- USA_HOP_MOD
 
- USA_MSR_CTS
 
- USA_MSR_DSR
 
- USA_MSR_dCTS
 
- USA_MSR_dDCD
 
- USA_MSR_dDSR
 
- USA_MSR_dRI
 
- USA_PARITY_EVEN
 
- USA_PARITY_NONE
 
- USA_PARITY_ODD
 
- USA_USA_MSR_RI
 
- USB
 
- USB0
 
- USB0PDEN
 
- USB0PUEN
 
- USB0VDR
 
- USB0_AUX_CLK_SRC
 
- USB0_BASE__INST0_SEG0
 
- USB0_BASE__INST0_SEG1
 
- USB0_BASE__INST0_SEG2
 
- USB0_BASE__INST0_SEG3
 
- USB0_BASE__INST0_SEG4
 
- USB0_BASE__INST1_SEG0
 
- USB0_BASE__INST1_SEG1
 
- USB0_BASE__INST1_SEG2
 
- USB0_BASE__INST1_SEG3
 
- USB0_BASE__INST1_SEG4
 
- USB0_BASE__INST2_SEG0
 
- USB0_BASE__INST2_SEG1
 
- USB0_BASE__INST2_SEG2
 
- USB0_BASE__INST2_SEG3
 
- USB0_BASE__INST2_SEG4
 
- USB0_BASE__INST3_SEG0
 
- USB0_BASE__INST3_SEG1
 
- USB0_BASE__INST3_SEG2
 
- USB0_BASE__INST3_SEG3
 
- USB0_BASE__INST3_SEG4
 
- USB0_BASE__INST4_SEG0
 
- USB0_BASE__INST4_SEG1
 
- USB0_BASE__INST4_SEG2
 
- USB0_BASE__INST4_SEG3
 
- USB0_BASE__INST4_SEG4
 
- USB0_BASE__INST5_SEG0
 
- USB0_BASE__INST5_SEG1
 
- USB0_BASE__INST5_SEG2
 
- USB0_BASE__INST5_SEG3
 
- USB0_BASE__INST5_SEG4
 
- USB0_BASE__INST6_SEG0
 
- USB0_BASE__INST6_SEG1
 
- USB0_BASE__INST6_SEG2
 
- USB0_BASE__INST6_SEG3
 
- USB0_BASE__INST6_SEG4
 
- USB0_BUS_REF
 
- USB0_EXTP_MARK
 
- USB0_IDIN_MARK
 
- USB0_MASTER_CLK_SRC
 
- USB0_MOCK_UTMI_CLK_SRC
 
- USB0_OCI_MARK
 
- USB0_OCP_RESET
 
- USB0_OVC_MARK
 
- USB0_OVC_VBUS_MARK
 
- USB0_PHYS_BASE
 
- USB0_PIPE_CLK_SRC
 
- USB0_PPON_MARK
 
- USB0_PWEN_MARK
 
- USB0_RESET
 
- USB0_TRX_MODE
 
- USB1
 
- USB11BHID_DESC
 
- USB11D1_DESC
 
- USB11H2_DESC
 
- USB11H3_DESC
 
- USB1D_DMNS_MARK
 
- USB1D_DPLS_MARK
 
- USB1D_RCV_MARK
 
- USB1D_SPEED_MARK
 
- USB1D_SUSPEND_MARK
 
- USB1D_TXDPLS_MARK
 
- USB1D_TXENL_MARK
 
- USB1D_TXSE0_MARK
 
- USB1OTG_CK
 
- USB1PDEN
 
- USB1PUEN
 
- USB1ULPI_CK
 
- USB1VDR
 
- USB1_AUX_CLK_SRC
 
- USB1_BUFFER_SIZE
 
- USB1_BUS_REF
 
- USB1_EXTP_MARK
 
- USB1_IDIN_MARK
 
- USB1_LEGACY_CTRL
 
- USB1_MASTER_CLK_SRC
 
- USB1_MOCK_UTMI_CLK_SRC
 
- USB1_NO_LEGACY_MODE
 
- USB1_OCI_MARK
 
- USB1_OCP_RESET
 
- USB1_OVC_MARK
 
- USB1_PHYS_BASE
 
- USB1_PIPE_CLK_SRC
 
- USB1_PPON_MARK
 
- USB1_PWEN_MARK
 
- USB1_PWR_EN_USBF_UPLUP_MARK
 
- USB1_RCV
 
- USB1_RESET
 
- USB1_SEO
 
- USB1_SPEED
 
- USB1_SUSP
 
- USB1_TRX_MODE
 
- USB1_TXD
 
- USB1_TXEN
 
- USB1_VBUS_SENSE_CTL_AB_SESS_VLD
 
- USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP
 
- USB1_VBUS_SENSE_CTL_A_SESS_VLD
 
- USB1_VBUS_SENSE_CTL_MASK
 
- USB1_VBUS_SENSE_CTL_VBUS_WAKEUP
 
- USB1_VM
 
- USB1_VP
 
- USB20_CLKSET0
 
- USB20_CON_B2_CONNECT
 
- USB20_CON_B2_PUE
 
- USB20_CON_B2_SUSPEND
 
- USB20_CON_B2_TSTMOD
 
- USB20_CON_B2_TSTMOD_EN
 
- USB20_CON_B2_TSTMOD_MASK
 
- USB20_CON_B2_TSTMOD_SHIFT
 
- USB20_HCLK
 
- USB20_MASTER_CLK_SRC
 
- USB20_MOCK_UTMI_CLK_SRC
 
- USB20_PHY_CLK
 
- USB21_HCLK
 
- USB21_PHY_CLK
 
- USB251XB_ADDR_BATTERY_CHARGING_ENABLE
 
- USB251XB_ADDR_BOOST_14
 
- USB251XB_ADDR_BOOST_57
 
- USB251XB_ADDR_BOOST_UP
 
- USB251XB_ADDR_CONFIG_DATA_1
 
- USB251XB_ADDR_CONFIG_DATA_2
 
- USB251XB_ADDR_CONFIG_DATA_3
 
- USB251XB_ADDR_DEVICE_ID_LSB
 
- USB251XB_ADDR_DEVICE_ID_MSB
 
- USB251XB_ADDR_LANGUAGE_ID_HIGH
 
- USB251XB_ADDR_LANGUAGE_ID_LOW
 
- USB251XB_ADDR_MANUFACTURER_STRING
 
- USB251XB_ADDR_MANUFACTURER_STRING_LEN
 
- USB251XB_ADDR_MAX_CURRENT_BUS
 
- USB251XB_ADDR_MAX_CURRENT_SELF
 
- USB251XB_ADDR_MAX_POWER_BUS
 
- USB251XB_ADDR_MAX_POWER_SELF
 
- USB251XB_ADDR_NON_REMOVABLE_DEVICES
 
- USB251XB_ADDR_PORT_DISABLE_BUS
 
- USB251XB_ADDR_PORT_DISABLE_SELF
 
- USB251XB_ADDR_PORT_MAP_12
 
- USB251XB_ADDR_PORT_MAP_34
 
- USB251XB_ADDR_PORT_MAP_56
 
- USB251XB_ADDR_PORT_MAP_7
 
- USB251XB_ADDR_PORT_SWAP
 
- USB251XB_ADDR_POWER_ON_TIME
 
- USB251XB_ADDR_PRODUCT_ID_LSB
 
- USB251XB_ADDR_PRODUCT_ID_MSB
 
- USB251XB_ADDR_PRODUCT_STRING
 
- USB251XB_ADDR_PRODUCT_STRING_LEN
 
- USB251XB_ADDR_SERIAL_STRING
 
- USB251XB_ADDR_SERIAL_STRING_LEN
 
- USB251XB_ADDR_STATUS_COMMAND
 
- USB251XB_ADDR_VENDOR_ID_LSB
 
- USB251XB_ADDR_VENDOR_ID_MSB
 
- USB251XB_DEF_BATTERY_CHARGING_ENABLE
 
- USB251XB_DEF_BOOST_14
 
- USB251XB_DEF_BOOST_57
 
- USB251XB_DEF_BOOST_UP
 
- USB251XB_DEF_CONFIG_DATA_1
 
- USB251XB_DEF_CONFIG_DATA_2
 
- USB251XB_DEF_CONFIG_DATA_3
 
- USB251XB_DEF_DEVICE_ID
 
- USB251XB_DEF_LANGUAGE_ID
 
- USB251XB_DEF_MANUFACTURER_STRING
 
- USB251XB_DEF_MAX_CURRENT_BUS
 
- USB251XB_DEF_MAX_CURRENT_SELF
 
- USB251XB_DEF_MAX_POWER_BUS
 
- USB251XB_DEF_MAX_POWER_SELF
 
- USB251XB_DEF_NON_REMOVABLE_DEVICES
 
- USB251XB_DEF_PORT_DISABLE_BUS
 
- USB251XB_DEF_PORT_DISABLE_SELF
 
- USB251XB_DEF_PORT_MAP_12
 
- USB251XB_DEF_PORT_MAP_34
 
- USB251XB_DEF_PORT_MAP_56
 
- USB251XB_DEF_PORT_MAP_7
 
- USB251XB_DEF_PORT_SWAP
 
- USB251XB_DEF_POWER_ON_TIME
 
- USB251XB_DEF_PRODUCT_ID_12
 
- USB251XB_DEF_PRODUCT_ID_13
 
- USB251XB_DEF_PRODUCT_ID_14
 
- USB251XB_DEF_PRODUCT_ID_17
 
- USB251XB_DEF_PRODUCT_STRING
 
- USB251XB_DEF_SERIAL_STRING
 
- USB251XB_DEF_VENDOR_ID
 
- USB251XB_I2C_REG_SZ
 
- USB251XB_I2C_WRITE_SZ
 
- USB251XB_STATUS_COMMAND_ATTACH
 
- USB251XB_STATUS_COMMAND_RESET
 
- USB251XB_STATUS_COMMAND_SMBUS_DOWN
 
- USB251XB_STRING_BUFSIZE
 
- USB2BD_DESC
 
- USB2BH1_DESC
 
- USB2BH2_DESC
 
- USB2D1_DESC
 
- USB2H1_DESC
 
- USB2OTG_CK
 
- USB2PDEN
 
- USB2PHYCTL_OFFSET
 
- USB2PHY_ANA_CONFIG1
 
- USB2PHY_DISCON_BYP_LATCH
 
- USB2PHY_L1
 
- USB2PHY_NUM_PORTS
 
- USB2PHY_PORT_HOST
 
- USB2PHY_PORT_OTG
 
- USB2PHY_SQCAL_DONE
 
- USB2PHY_SUSPEND
 
- USB2PUEN
 
- USB2ULPI_CK
 
- USB2VDR
 
- USB2_ADPCTRL
 
- USB2_ADPCTRL_DRVVBUS
 
- USB2_ADPCTRL_IDDIG
 
- USB2_ADPCTRL_IDPULLUP
 
- USB2_ADPCTRL_OTGSESSVLD
 
- USB2_ANA_PU_ANA_SHIFT_MMP3
 
- USB2_ANA_REG0
 
- USB2_ANA_REG1
 
- USB2_ANA_REG2
 
- USB2_BUFFER_SIZE
 
- USB2_CHARGER_REG0
 
- USB2_COMMCTRL
 
- USB2_COMMCTRL_OTG_PERI
 
- USB2_CORE_ENABLE
 
- USB2_DIG_REG0
 
- USB2_DIG_REG1
 
- USB2_DIG_REG2
 
- USB2_DIG_REG3
 
- USB2_DM_PULLDN_DEV_MODE
 
- USB2_DP_PULLDN_DEV_MODE
 
- USB2_EXTP_MARK
 
- USB2_HOST_DELAY
 
- USB2_HOST_PHY
 
- USB2_HSIC_PORT_WAKEUP_EVENT
 
- USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE
 
- USB2_HSPHY_POR_ARES
 
- USB2_HSPHY_S_ARES
 
- USB2_ICID_REG0
 
- USB2_ICID_REG1
 
- USB2_IDIN_MARK
 
- USB2_INT_ENABLE
 
- USB2_INT_ENABLE_UCOM_INTEN
 
- USB2_INT_ENABLE_USBH_INTA_EN
 
- USB2_INT_ENABLE_USBH_INTB_EN
 
- USB2_LINECTRL1
 
- USB2_LINECTRL1_DMRPD_EN
 
- USB2_LINECTRL1_DM_RPD
 
- USB2_LINECTRL1_DPRPD_EN
 
- USB2_LINECTRL1_DP_RPD
 
- USB2_LINECTRL1_OPMODE_NODRV
 
- USB2_MST_ID
 
- USB2_OBINTEN
 
- USB2_OBINTSTA
 
- USB2_OBINT_BITS
 
- USB2_OBINT_IDDIGCHG
 
- USB2_OBINT_SESSVLDCHG
 
- USB2_OC_TIMSET
 
- USB2_OC_TIMSET_INIT
 
- USB2_OTG_PD
 
- USB2_OTG_PD2
 
- USB2_OTG_PD2_OVRD_EN
 
- USB2_OTG_PD_DR
 
- USB2_OTG_PD_ZI
 
- USB2_OTG_PHY
 
- USB2_OTG_PU_OTG_SHIFT_MMP3
 
- USB2_OTG_REG0
 
- USB2_OVC_MARK
 
- USB2_PD_TRK
 
- USB2_PHYS_BASE
 
- USB2_PHY_CAL_CTRL
 
- USB2_PHY_CHRGR_DETECT
 
- USB2_PHY_CONFIG_DISABLE
 
- USB2_PHY_CTRL
 
- USB2_PHY_MON0
 
- USB2_PHY_OTG_CTRL
 
- USB2_PHY_PLL_CTRL_REG0
 
- USB2_PLL_CAL12_SHIFT_MMP3
 
- USB2_PLL_CALI12_MASK_MMP3
 
- USB2_PLL_FBDIV_MASK_MMP3
 
- USB2_PLL_FBDIV_MASK_MMP3_B0
 
- USB2_PLL_FBDIV_SHIFT_MMP3
 
- USB2_PLL_FBDIV_SHIFT_MMP3_B0
 
- USB2_PLL_ICP_MASK_MMP3
 
- USB2_PLL_ICP_SHIFT_MMP3
 
- USB2_PLL_KVCO_MASK_MMP3
 
- USB2_PLL_KVCO_SHIFT_MMP3
 
- USB2_PLL_LOCK_BYPASS_SHIFT_MMP3
 
- USB2_PLL_PU_PLL_MASK
 
- USB2_PLL_PU_PLL_SHIFT_MMP3
 
- USB2_PLL_READY_MASK_MMP3
 
- USB2_PLL_REFDIV_MASK_MMP3
 
- USB2_PLL_REFDIV_MASK_MMP3_B0
 
- USB2_PLL_REFDIV_SHIFT_MMP3
 
- USB2_PLL_REFDIV_SHIFT_MMP3_B0
 
- USB2_PLL_REG0
 
- USB2_PLL_REG1
 
- USB2_PLL_VCOCAL_START_SHIFT_MMP3
 
- USB2_PLL_VDD12_SHIFT_MMP3
 
- USB2_PLL_VDD18_SHIFT_MMP3
 
- USB2_PLL_VDD18_SHIFT_MMP3_B0
 
- USB2_PORT
 
- USB2_PORT_MASK
 
- USB2_PORT_SHIFT
 
- USB2_PORT_WAKEUP_EVENT
 
- USB2_PORT_WAKE_INTERRUPT_ENABLE
 
- USB2_PWEN_MARK
 
- USB2_PWR_EN_MARK
 
- USB2_RCV
 
- USB2_RESETVE_REG0
 
- USB2_RX_CHAN_CTRL1
 
- USB2_RX_REG0
 
- USB2_RX_REG1
 
- USB2_RX_REG2
 
- USB2_RX_SQ_LENGTH_MASK_MMP3
 
- USB2_RX_SQ_LENGTH_SHIFT_MMP3
 
- USB2_RX_SQ_THRESH_MASK_MMP3
 
- USB2_RX_SQ_THRESH_SHIFT_MMP3
 
- USB2_SEO
 
- USB2_SPD_RSM_TIMSET
 
- USB2_SPD_RSM_TIMSET_INIT
 
- USB2_SUSP
 
- USB2_SW_DISCONNECT
 
- USB2_TEST_REG0
 
- USB2_TEST_REG1
 
- USB2_TEST_REG2
 
- USB2_TRK_DONE_RESET_TIMER
 
- USB2_TRK_START_TIMER
 
- USB2_TRX_MODE
 
- USB2_TXD
 
- USB2_TXEN
 
- USB2_TX_AMP_MASK_MMP3
 
- USB2_TX_AMP_SHIFT_MMP3
 
- USB2_TX_CK60_PHSEL_MASK_MMP3
 
- USB2_TX_CK60_PHSEL_SHIFT_MMP3
 
- USB2_TX_DRV_SLEWRATE_SHIFT
 
- USB2_TX_IMPCAL_VTH_MASK_MMP3
 
- USB2_TX_IMPCAL_VTH_SHIFT_MMP3
 
- USB2_TX_RCAL_START_SHIFT_MMP3
 
- USB2_TX_REG0
 
- USB2_TX_REG1
 
- USB2_TX_REG2
 
- USB2_TX_VDD12_MASK_MMP3
 
- USB2_TX_VDD12_SHIFT_MMP3
 
- USB2_USBCTR
 
- USB2_USBCTR_DIRPD
 
- USB2_USBCTR_PLL_RST
 
- USB2_VBCTRL
 
- USB2_VBCTRL_DRVVBUSSEL
 
- USB2_VBCTRL_OCCLREN
 
- USB2_VBUS_ID
 
- USB2_VBUS_MNGMNT_SEL1
 
- USB2_VBUS_PIPEW
 
- USB2_VBUS_REG30
 
- USB2_VBUS_UTMIOTG
 
- USB2_VBUS_ZERO
 
- USB2_VM
 
- USB2_VP
 
- USB30_0_MASTER_CLK
 
- USB30_0_MASTER_RESET
 
- USB30_0_PHY_RESET
 
- USB30_0_PORT2_HS_PHY_RESET
 
- USB30_0_POWERON_RESET
 
- USB30_0_SLEEP_RESET
 
- USB30_0_UTMI_CLK
 
- USB30_0_UTMI_PHY_RESET
 
- USB30_1_MASTER_CLK
 
- USB30_1_MASTER_RESET
 
- USB30_1_PHY_RESET
 
- USB30_1_POWERON_RESET
 
- USB30_1_SLEEP_RESET
 
- USB30_1_UTMI_CLK
 
- USB30_1_UTMI_PHY_RESET
 
- USB30_CLKSET0
 
- USB30_CLKSET1
 
- USB30_CON_B3_CONNECT
 
- USB30_CON_B3_HOTRST_CMP
 
- USB30_CON_B3_PLLWAKE
 
- USB30_CON_POW_SEL_IN_DISCON
 
- USB30_CON_POW_SEL_IN_U3
 
- USB30_CON_POW_SEL_MASK
 
- USB30_CON_POW_SEL_P0_TO_P2
 
- USB30_CON_POW_SEL_P0_TO_P3
 
- USB30_CON_POW_SEL_P2_TO_P0
 
- USB30_CON_POW_SEL_SHIFT
 
- USB30_GDSC
 
- USB30_MASTER_CLK_SRC
 
- USB30_MASTER_SRC
 
- USB30_MOCK_UTMI_CLK_SRC
 
- USB30_PHY_ENABLE
 
- USB30_PRIM_GDSC
 
- USB30_SEC_GDSC
 
- USB30_SEC_MASTER_CLK_SRC
 
- USB30_SEC_MOCK_UTMI_CLK_SRC
 
- USB30_SLEEP_CLK
 
- USB30_SSC_SET
 
- USB30_UTMI_SRC
 
- USB30_VBUS_EN
 
- USB3380_EP_CFG_MASK_IN
 
- USB3380_EP_CFG_MASK_OUT
 
- USB3380_IRQSTAT0_EP_INTR_MASK_IN
 
- USB3380_IRQSTAT0_EP_INTR_MASK_OUT
 
- USB3503_CFG1
 
- USB3503_CFG2
 
- USB3503_CFG3
 
- USB3503_CFGP
 
- USB3503_CLKSUSP
 
- USB3503_DIDL
 
- USB3503_DIDM
 
- USB3503_I2C_NAME
 
- USB3503_MODE_HUB
 
- USB3503_MODE_STANDBY
 
- USB3503_MODE_UNKNOWN
 
- USB3503_NRD
 
- USB3503_OFF_PORT1
 
- USB3503_OFF_PORT2
 
- USB3503_OFF_PORT3
 
- USB3503_PDS
 
- USB3503_PIDL
 
- USB3503_PIDM
 
- USB3503_RESET
 
- USB3503_SELF_BUS_PWR
 
- USB3503_SPILOCK_CONFIG
 
- USB3503_SPILOCK_CONNECT
 
- USB3503_SP_ILOCK
 
- USB3503_VIDL
 
- USB3503_VIDM
 
- USB3VBUS_OFFSET
 
- USB3VBUS_REG
 
- USB3VBUS_REG_EN
 
- USB3_AXI_INT_ENA
 
- USB3_AXI_INT_STA
 
- USB3_CONTROL_MASK
 
- USB3_CORE_ENABLE
 
- USB3_DEEMPHASIS0
 
- USB3_DEEMPHASIS_MASK
 
- USB3_DELAY_VBUSVALID
 
- USB3_DEVICE_NOT_HOST
 
- USB3_DMA_CH0_CON
 
- USB3_DMA_CH0_PRD_ADR
 
- USB3_DMA_INT_ENA
 
- USB3_DMA_INT_STA
 
- USB3_DMA_MAX_XFER_SIZE
 
- USB3_DMA_MAX_XFER_SIZE_ALL_PRDS
 
- USB3_DMA_NUM_PRD_ENTRIES
 
- USB3_DMA_NUM_SETTING_AREA
 
- USB3_DMA_PRD_SIZE
 
- USB3_DRD_CON
 
- USB3_DUAL_REF
 
- USB3_EN
 
- USB3_EP0_BUF_SIZE
 
- USB3_EP0_HSFS_MAX_PACKET_SIZE
 
- USB3_EP0_SS_MAX_PACKET_SIZE
 
- USB3_EP_NAME_SIZE
 
- USB3_FORCE_DMPULLDOWN2
 
- USB3_FORCE_DPPULLDOWN2
 
- USB3_FORCE_OPMODE
 
- USB3_FORCE_VBUSVALID
 
- USB3_HOST_PHY
 
- USB3_HSPHY_POR_ARES
 
- USB3_HSPHY_S_ARES
 
- USB3_LPM_DEVICE_INITIATED
 
- USB3_LPM_DISABLED
 
- USB3_LPM_MAX_U1_SEL_PEL
 
- USB3_LPM_MAX_U2_SEL_PEL
 
- USB3_LPM_U0
 
- USB3_LPM_U1
 
- USB3_LPM_U1_MAX_TIMEOUT
 
- USB3_LPM_U2
 
- USB3_LPM_U2_MAX_TIMEOUT
 
- USB3_LPM_U3
 
- USB3_MAX_NUM_PIPES
 
- USB3_MAX_WINDOWS
 
- USB3_MODE
 
- USB3_MST_ID
 
- USB3_P0_CON
 
- USB3_P0_INT_ENA
 
- USB3_P0_INT_STA
 
- USB3_P0_LNG
 
- USB3_P0_MOD
 
- USB3_P0_READ
 
- USB3_P0_STA
 
- USB3_P0_WRITE
 
- USB3_PHY_AUX_CLK_SRC
 
- USB3_PIPE_COM
 
- USB3_PN_CON
 
- USB3_PN_INT_ENA
 
- USB3_PN_INT_STA
 
- USB3_PN_LNG
 
- USB3_PN_MOD
 
- USB3_PN_RAMMAP
 
- USB3_PN_READ
 
- USB3_PN_STA
 
- USB3_PN_WRITE
 
- USB3_PORT
 
- USB3_PRD1_B_INC
 
- USB3_PRD1_D
 
- USB3_PRD1_E
 
- USB3_PRD1_INT
 
- USB3_PRD1_LST
 
- USB3_PRD1_MPS_1024
 
- USB3_PRD1_MPS_16
 
- USB3_PRD1_MPS_32
 
- USB3_PRD1_MPS_512
 
- USB3_PRD1_MPS_64
 
- USB3_PRD1_MPS_8
 
- USB3_PRD1_MPS_RESERVED
 
- USB3_PRD1_SIZE_MASK
 
- USB3_PRD1_U
 
- USB3_SEL_FORCE_DMPULLDOWN2
 
- USB3_SEL_FORCE_DPPULLDOWN2
 
- USB3_SEL_FORCE_OPMODE
 
- USB3_SSIFCMD
 
- USB3_STUP_DAT_0
 
- USB3_STUP_DAT_1
 
- USB3_SW_DISCONNECT
 
- USB3_TX_MARGIN1
 
- USB3_UNIPHY_PHY_ARES
 
- USB3_USB20_CON
 
- USB3_USB30_CON
 
- USB3_USB_COM_CON
 
- USB3_USB_INT_ENA_1
 
- USB3_USB_INT_ENA_2
 
- USB3_USB_INT_STA_1
 
- USB3_USB_INT_STA_2
 
- USB3_USB_OTG_INT_ENA
 
- USB3_USB_OTG_INT_STA
 
- USB3_USB_OTG_STA
 
- USB3_USB_STA
 
- USB3_WAIT_US
 
- USB3_WIN_BASE
 
- USB3_WIN_CTRL
 
- USB4604_MODE_HUB
 
- USB4604_MODE_STANDBY
 
- USB4604_MODE_UNKNOWN
 
- USB480M
 
- USB6FIRE_CHIP_H
 
- USB6FIRE_COMMON_H
 
- USB6FIRE_COMM_H
 
- USB6FIRE_CONTROL_H
 
- USB6FIRE_FIRMWARE_H
 
- USB6FIRE_MIDI_H
 
- USB6FIRE_PCM_H
 
- USB8766_DEFAULT_FW_NAME
 
- USB8766_PID_1
 
- USB8766_PID_2
 
- USB8797_DEFAULT_FW_NAME
 
- USB8797_PID_1
 
- USB8797_PID_2
 
- USB8801_DEFAULT_FW_NAME
 
- USB8801_PID_1
 
- USB8801_PID_2
 
- USB8997_DEFAULT_FW_NAME
 
- USB8997_PID_1
 
- USB8997_PID_2
 
- USB8XXX_FW_DNLD
 
- USB8XXX_FW_MAX_RETRY
 
- USB8XXX_FW_READY
 
- USB8XXX_VID
 
- USBADDR
 
- USBAT_ATA
 
- USBAT_ATA_ALTSTATUS
 
- USBAT_ATA_CMD
 
- USBAT_ATA_DATA
 
- USBAT_ATA_DEVICE
 
- USBAT_ATA_ERROR
 
- USBAT_ATA_FEATURES
 
- USBAT_ATA_LBA_HI
 
- USBAT_ATA_LBA_ME
 
- USBAT_ATA_SECCNT
 
- USBAT_ATA_SECNUM
 
- USBAT_ATA_STATUS
 
- USBAT_CMD_COND_READ_BLOCK
 
- USBAT_CMD_COND_WRITE_BLOCK
 
- USBAT_CMD_EXEC_CMD
 
- USBAT_CMD_READ_BLOCK
 
- USBAT_CMD_READ_REG
 
- USBAT_CMD_SET_FEAT
 
- USBAT_CMD_UIO
 
- USBAT_CMD_WRITE_BLOCK
 
- USBAT_CMD_WRITE_REG
 
- USBAT_CMD_WRITE_REGS
 
- USBAT_DEV_FLASH
 
- USBAT_DEV_HP8200
 
- USBAT_EPP_PORT
 
- USBAT_EPP_REGISTER
 
- USBAT_FEAT_ET1
 
- USBAT_FEAT_ET2
 
- USBAT_FEAT_ETEN
 
- USBAT_FEAT_U0
 
- USBAT_FEAT_U1
 
- USBAT_FLASH_MEDIA_CF
 
- USBAT_FLASH_MEDIA_CHANGED
 
- USBAT_FLASH_MEDIA_NONE
 
- USBAT_FLASH_MEDIA_SAME
 
- USBAT_ISA
 
- USBAT_QUAL_ALQ
 
- USBAT_QUAL_FCQ
 
- USBAT_UIO_0
 
- USBAT_UIO_1
 
- USBAT_UIO_ACKD
 
- USBAT_UIO_ADPRST
 
- USBAT_UIO_CDT
 
- USBAT_UIO_DRVRST
 
- USBAT_UIO_EPAD
 
- USBAT_UIO_EPP_ATA
 
- USBAT_UIO_INTR_ACK
 
- USBAT_UIO_OE0
 
- USBAT_UIO_OE1
 
- USBAT_UIO_READ
 
- USBAT_UIO_UI0
 
- USBAT_UIO_UI1
 
- USBAT_UIO_WRITE
 
- USBA_AUTO_VALID
 
- USBA_BF
 
- USBA_BFEXT
 
- USBA_BFINS
 
- USBA_BK_NUMBER_DOUBLE
 
- USBA_BK_NUMBER_OFFSET
 
- USBA_BK_NUMBER_ONE
 
- USBA_BK_NUMBER_SIZE
 
- USBA_BK_NUMBER_TRIPLE
 
- USBA_BK_NUMBER_ZERO
 
- USBA_BUSY_BANKS_OFFSET
 
- USBA_BUSY_BANKS_SIZE
 
- USBA_BUSY_BANK_IE
 
- USBA_BYTE_COUNT_OFFSET
 
- USBA_BYTE_COUNT_SIZE
 
- USBA_CTRL
 
- USBA_CURRENT_BANK_OFFSET
 
- USBA_CURRENT_BANK_SIZE
 
- USBA_DATAX_RX
 
- USBA_DETACH
 
- USBA_DET_SUSPEND
 
- USBA_DEV_ADDR_OFFSET
 
- USBA_DEV_ADDR_SIZE
 
- USBA_DISABLE_MASK
 
- USBA_DMA_ADDRESS
 
- USBA_DMA_BASE
 
- USBA_DMA_BUF_LEN_OFFSET
 
- USBA_DMA_BUF_LEN_SIZE
 
- USBA_DMA_BURST_LOCK
 
- USBA_DMA_CH_ACTIVE
 
- USBA_DMA_CH_EN
 
- USBA_DMA_CONTROL
 
- USBA_DMA_DESC_LOAD_IE
 
- USBA_DMA_DESC_LOAD_ST
 
- USBA_DMA_END_BUF_EN
 
- USBA_DMA_END_BUF_IE
 
- USBA_DMA_END_BUF_ST
 
- USBA_DMA_END_TR_EN
 
- USBA_DMA_END_TR_IE
 
- USBA_DMA_END_TR_ST
 
- USBA_DMA_INT_OFFSET
 
- USBA_DMA_INT_SIZE
 
- USBA_DMA_LINK
 
- USBA_DMA_NXT_DSC
 
- USBA_DMA_STATUS
 
- USBA_ENABLE_MASK
 
- USBA_END_OF_RESET
 
- USBA_END_OF_RESUME
 
- USBA_EN_USBA
 
- USBA_EPT_BASE
 
- USBA_EPT_CFG
 
- USBA_EPT_CLR_STA
 
- USBA_EPT_CTL
 
- USBA_EPT_CTL_DIS
 
- USBA_EPT_CTL_ENB
 
- USBA_EPT_DIR_IN
 
- USBA_EPT_ENABLE
 
- USBA_EPT_INT_OFFSET
 
- USBA_EPT_INT_SIZE
 
- USBA_EPT_MAPPED
 
- USBA_EPT_RST
 
- USBA_EPT_SET_STA
 
- USBA_EPT_SIZE_1024
 
- USBA_EPT_SIZE_128
 
- USBA_EPT_SIZE_16
 
- USBA_EPT_SIZE_256
 
- USBA_EPT_SIZE_32
 
- USBA_EPT_SIZE_512
 
- USBA_EPT_SIZE_64
 
- USBA_EPT_SIZE_8
 
- USBA_EPT_SIZE_OFFSET
 
- USBA_EPT_SIZE_SIZE
 
- USBA_EPT_STA
 
- USBA_EPT_TYPE_BULK
 
- USBA_EPT_TYPE_CONTROL
 
- USBA_EPT_TYPE_INT
 
- USBA_EPT_TYPE_ISO
 
- USBA_EPT_TYPE_OFFSET
 
- USBA_EPT_TYPE_SIZE
 
- USBA_ERR_OVFLW
 
- USBA_FADDR_EN
 
- USBA_FIFO_BASE
 
- USBA_FNUM
 
- USBA_FORCE_STALL
 
- USBA_FRAME_NUMBER_OFFSET
 
- USBA_FRAME_NUMBER_SIZE
 
- USBA_FRAME_NUM_ERROR
 
- USBA_HIGH_SPEED
 
- USBA_INTDIS_DMA
 
- USBA_INT_CLR
 
- USBA_INT_ENB
 
- USBA_INT_STA
 
- USBA_ISO_ERR_CRC
 
- USBA_ISO_ERR_FLOW
 
- USBA_ISO_ERR_FLUSH
 
- USBA_ISO_ERR_NBTRANS
 
- USBA_ISO_ERR_TRANS
 
- USBA_KILL_BANK
 
- USBA_MDATA_RX
 
- USBA_MICRO_FRAME_NUM_OFFSET
 
- USBA_MICRO_FRAME_NUM_SIZE
 
- USBA_MICRO_SOF
 
- USBA_NAK_IN
 
- USBA_NAK_OUT
 
- USBA_NB_TRANS_OFFSET
 
- USBA_NB_TRANS_SIZE
 
- USBA_NR_DMAS
 
- USBA_NYET_DIS
 
- USBA_OPMODE2
 
- USBA_PULLD_DIS
 
- USBA_REMOTE_WAKE_UP
 
- USBA_RST_OFFSET
 
- USBA_RST_SIZE
 
- USBA_RX_BK_RDY
 
- USBA_RX_SETUP
 
- USBA_SHORT_PACKET
 
- USBA_SOF
 
- USBA_SPEED_CFG_FORCE_FULL
 
- USBA_SPEED_CFG_FORCE_HIGH
 
- USBA_SPEED_CFG_NORMAL
 
- USBA_SPEED_CFG_OFFSET
 
- USBA_SPEED_CFG_SIZE
 
- USBA_STALL_SENT
 
- USBA_TOGGLE_CLR
 
- USBA_TOGGLE_SEQ_OFFSET
 
- USBA_TOGGLE_SEQ_SIZE
 
- USBA_TST
 
- USBA_TST_J_MODE
 
- USBA_TST_K_MODE
 
- USBA_TST_PKT_MODE
 
- USBA_TX_COMPLETE
 
- USBA_TX_PK_RDY
 
- USBA_UPSTREAM_RESUME
 
- USBA_VBUS_IRQFLAGS
 
- USBA_WAKE_UP
 
- USBBUXSIGMA_AD_CMD
 
- USBCAN_ERROR_STATE_BUSERROR
 
- USBCAN_ERROR_STATE_NONE
 
- USBCAN_ERROR_STATE_RX_ERROR
 
- USBCAN_ERROR_STATE_TX_ERROR
 
- USBCFG_DBE
 
- USBCFG_DME
 
- USBCFG_EBE
 
- USBCFG_ECE
 
- USBCFG_EME
 
- USBCFG_FLA
 
- USBCFG_GME
 
- USBCFG_INIT_AU1200
 
- USBCFG_OBE
 
- USBCFG_OCE
 
- USBCFG_OME
 
- USBCFG_PFEN
 
- USBCFG_PPE
 
- USBCFG_RDCOMB
 
- USBCFG_SSD
 
- USBCFG_UCAM
 
- USBCFG_UCE
 
- USBCFG_UNKNOWN
 
- USBCMD
 
- USBCMD_ATDTW
 
- USBCMD_ATDTW_TRIPWIRE_CLEAR
 
- USBCMD_ATDTW_TRIPWIRE_SET
 
- USBCMD_CF
 
- USBCMD_CTRL_RESET
 
- USBCMD_EGSM
 
- USBCMD_FGR
 
- USBCMD_FRAME_SIZE_1024
 
- USBCMD_FRAME_SIZE_128
 
- USBCMD_FRAME_SIZE_16
 
- USBCMD_FRAME_SIZE_256
 
- USBCMD_FRAME_SIZE_32
 
- USBCMD_FRAME_SIZE_512
 
- USBCMD_FRAME_SIZE_64
 
- USBCMD_FRAME_SIZE_8
 
- USBCMD_GRESET
 
- USBCMD_HCRESET
 
- USBCMD_MAXP
 
- USBCMD_RS
 
- USBCMD_RST
 
- USBCMD_RUN_STOP
 
- USBCMD_SETUP_TRIPWIRE_CLEAR
 
- USBCMD_SETUP_TRIPWIRE_SET
 
- USBCMD_SUTW
 
- USBCMD_SWDBG
 
- USBCR
 
- USBCTL0
 
- USBCTL1
 
- USBCTL_DISCONN_OTHER
 
- USBCTL_DISCONN_THIS
 
- USBCTL_ENABLE_DEFAULTS
 
- USBCTL_ENABLE_LANG
 
- USBCTL_ENABLE_MFGR
 
- USBCTL_ENABLE_PROD
 
- USBCTL_ENABLE_SERIAL
 
- USBCTL_FLUSH_OTHER
 
- USBCTL_FLUSH_THIS
 
- USBCTL_WRITABLE_MASK
 
- USBCTRL
 
- USBCTRL0
 
- USBCTRL_FNT_WU_INT_EN
 
- USBCTRL_FNT_WU_INT_STAT
 
- USBCTRL_HOST1_BYP_TLL
 
- USBCTRL_HOST1_BYP_VAL
 
- USBCTRL_HOST1_PWR_MASK
 
- USBCTRL_HOST1_TXEN_OE
 
- USBCTRL_HOST2_PWR_MASK
 
- USBCTRL_HOST_WU_INT_EN
 
- USBCTRL_HOST_WU_INT_STAT
 
- USBCTRL_I2C_WU_INT_EN
 
- USBCTRL_I2C_WU_INT_STAT
 
- USBCTRL_OTC_RCV_RXDP
 
- USBCTRL_OTGBASE_OFFSET
 
- USBCTRL_OTG_BYP_VAL
 
- USBCTRL_OTG_PWR_MASK
 
- USBCTRL_OTG_WU_INT_EN
 
- USBCTRL_OTG_WU_INT_STAT
 
- USBCTRL_USB_BYP
 
- USBC_CC1
 
- USBC_CC1_CTRL
 
- USBC_CC1_STATUS
 
- USBC_CC2
 
- USBC_CC2_CTRL
 
- USBC_CC2_STATUS
 
- USBC_CC_CTRL_ADC_EN
 
- USBC_CC_CTRL_CDET_EN
 
- USBC_CC_CTRL_PD_EN
 
- USBC_CC_CTRL_PU_EN
 
- USBC_CC_CTRL_RDET_EN
 
- USBC_CC_CTRL_TX_EN
 
- USBC_CC_CTRL_VBUSOK
 
- USBC_CC_CTRL_VCONN_EN
 
- USBC_CC_STATUS_RA
 
- USBC_CC_STATUS_RD
 
- USBC_CONTROL1
 
- USBC_CONTROL1_CURSRC_MASK
 
- USBC_CONTROL1_CURSRC_UA_0
 
- USBC_CONTROL1_CURSRC_UA_180
 
- USBC_CONTROL1_CURSRC_UA_330
 
- USBC_CONTROL1_CURSRC_UA_80
 
- USBC_CONTROL1_DRPTOGGLE_RANDOM
 
- USBC_CONTROL1_MODE_DRP
 
- USBC_CONTROL1_MODE_DRPACC
 
- USBC_CONTROL1_MODE_MASK
 
- USBC_CONTROL1_MODE_SNK
 
- USBC_CONTROL1_MODE_SNKACC
 
- USBC_CONTROL1_MODE_SRC
 
- USBC_CONTROL1_MODE_SRCACC
 
- USBC_CONTROL1_MODE_TEST
 
- USBC_CONTROL2
 
- USBC_CONTROL2_DIS_ST
 
- USBC_CONTROL2_UNATT_SNK
 
- USBC_CONTROL2_UNATT_SRC
 
- USBC_CONTROL3
 
- USBC_CONTROL3_DET_DIS
 
- USBC_CONTROL3_PD_DIS
 
- USBC_CONTROL3_RESETPHY
 
- USBC_EP3ACK
 
- USBC_EP3NAK
 
- USBC_IRQ1
 
- USBC_IRQ1_ADCDONE1
 
- USBC_IRQ1_OVERTEMP
 
- USBC_IRQ1_SHORT
 
- USBC_IRQ2
 
- USBC_IRQ2_CC_CHANGE
 
- USBC_IRQ2_RX_CR
 
- USBC_IRQ2_RX_HR
 
- USBC_IRQ2_RX_PD
 
- USBC_IRQ2_TX_FAIL
 
- USBC_IRQ2_TX_SUCCESS
 
- USBC_IRQMASK1
 
- USBC_IRQMASK1_ALL
 
- USBC_IRQMASK2
 
- USBC_IRQMASK2_ALL
 
- USBC_ORIENT_NORMAL
 
- USBC_ORIENT_REVERSE
 
- USBC_PDCFG2
 
- USBC_PDCFG2_SOP
 
- USBC_PDCFG2_SOP_P
 
- USBC_PDCFG2_SOP_PP
 
- USBC_PDCFG2_SOP_PP_DEBUG
 
- USBC_PDCFG2_SOP_P_DEBUG
 
- USBC_PDCFG3
 
- USBC_PDCFG3_DATAROLE_SHIFT
 
- USBC_PDCFG3_SOP_SHIFT
 
- USBC_PDSTATUS
 
- USBC_PD_CC_AUDIO_ACC
 
- USBC_PD_CC_DEBUG_ACC
 
- USBC_PD_CC_DFP_ATTACHED
 
- USBC_PD_CC_NONE
 
- USBC_PD_CC_NO_UFP
 
- USBC_PD_CC_UFP_ATTACHED
 
- USBC_RSLT_AUDIO_ACC
 
- USBC_RSLT_DEBUG_ACC
 
- USBC_RSLT_NOTHING
 
- USBC_RSLT_SNK
 
- USBC_RSLT_SRC_1_5A
 
- USBC_RSLT_SRC_3_0A
 
- USBC_RSLT_SRC_DEFAULT
 
- USBC_RSLT_UNDEF
 
- USBC_RXINFO
 
- USBC_RXINFO_RXBYTES
 
- USBC_RXSTATUS
 
- USBC_RXSTATUS_RXCLEAR
 
- USBC_RXSTATUS_RXDATA
 
- USBC_RX_DATA
 
- USBC_STATUS1
 
- USBC_STATUS1_DET_ONGOING
 
- USBC_STATUS1_ORIENT
 
- USBC_STATUS1_RSLT
 
- USBC_STATUS2
 
- USBC_STATUS2_VBUS_REQ
 
- USBC_STATUS3
 
- USBC_TXCMD
 
- USBC_TXCMD_BIST
 
- USBC_TXCMD_BUF_RDY
 
- USBC_TXCMD_CR
 
- USBC_TXCMD_HR
 
- USBC_TXCMD_MSG
 
- USBC_TXCMD_NOP
 
- USBC_TXCMD_START
 
- USBC_TXINFO
 
- USBC_TXINFO_RETRIES
 
- USBC_TX_DATA
 
- USBDA_USBFA
 
- USBDEVFS_ALLOC_STREAMS
 
- USBDEVFS_ALLOW_SUSPEND
 
- USBDEVFS_BULK
 
- USBDEVFS_BULK32
 
- USBDEVFS_CAP_BULK_CONTINUATION
 
- USBDEVFS_CAP_BULK_SCATTER_GATHER
 
- USBDEVFS_CAP_CONNINFO_EX
 
- USBDEVFS_CAP_DROP_PRIVILEGES
 
- USBDEVFS_CAP_MMAP
 
- USBDEVFS_CAP_NO_PACKET_SIZE_LIM
 
- USBDEVFS_CAP_REAP_AFTER_DISCONNECT
 
- USBDEVFS_CAP_SUSPEND
 
- USBDEVFS_CAP_ZERO_PACKET
 
- USBDEVFS_CLAIMINTERFACE
 
- USBDEVFS_CLAIM_PORT
 
- USBDEVFS_CLEAR_HALT
 
- USBDEVFS_CONNECT
 
- USBDEVFS_CONNECTINFO
 
- USBDEVFS_CONNINFO_EX
 
- USBDEVFS_CONTROL
 
- USBDEVFS_CONTROL32
 
- USBDEVFS_DISCARDURB
 
- USBDEVFS_DISCONNECT
 
- USBDEVFS_DISCONNECT_CLAIM
 
- USBDEVFS_DISCONNECT_CLAIM_EXCEPT_DRIVER
 
- USBDEVFS_DISCONNECT_CLAIM_IF_DRIVER
 
- USBDEVFS_DISCSIGNAL
 
- USBDEVFS_DISCSIGNAL32
 
- USBDEVFS_DROP_PRIVILEGES
 
- USBDEVFS_FORBID_SUSPEND
 
- USBDEVFS_FREE_STREAMS
 
- USBDEVFS_GETDRIVER
 
- USBDEVFS_GET_CAPABILITIES
 
- USBDEVFS_GET_SPEED
 
- USBDEVFS_HUB_PORTINFO
 
- USBDEVFS_IOCTL
 
- USBDEVFS_IOCTL32
 
- USBDEVFS_MAXDRIVERNAME
 
- USBDEVFS_REAPURB
 
- USBDEVFS_REAPURB32
 
- USBDEVFS_REAPURBNDELAY
 
- USBDEVFS_REAPURBNDELAY32
 
- USBDEVFS_RELEASEINTERFACE
 
- USBDEVFS_RELEASE_PORT
 
- USBDEVFS_RESET
 
- USBDEVFS_RESETEP
 
- USBDEVFS_SETCONFIGURATION
 
- USBDEVFS_SETINTERFACE
 
- USBDEVFS_SUBMITURB
 
- USBDEVFS_SUBMITURB32
 
- USBDEVFS_URB_BULK_CONTINUATION
 
- USBDEVFS_URB_ISO_ASAP
 
- USBDEVFS_URB_NO_FSBR
 
- USBDEVFS_URB_NO_INTERRUPT
 
- USBDEVFS_URB_SHORT_NOT_OK
 
- USBDEVFS_URB_TYPE_BULK
 
- USBDEVFS_URB_TYPE_CONTROL
 
- USBDEVFS_URB_TYPE_INTERRUPT
 
- USBDEVFS_URB_TYPE_ISO
 
- USBDEVFS_URB_ZERO_PACKET
 
- USBDEVFS_WAIT_FOR_RESUME
 
- USBDEVICE_SUPER_MAGIC
 
- USBDHDR
 
- USBDIAG
 
- USBDUXFASTSUB_CPUCS
 
- USBDUXFASTSUB_FIRMWARE
 
- USBDUXSIGMA_DA_CMD
 
- USBDUXSIGMA_DIO_BITS_CMD
 
- USBDUXSIGMA_DIO_CFG_CMD
 
- USBDUXSIGMA_PWM_OFF_CMD
 
- USBDUXSIGMA_PWM_ON_CMD
 
- USBDUXSIGMA_SINGLE_AD_CMD
 
- USBDUXSUB_CPUCS
 
- USBDUXSUB_FIRMWARE
 
- USBDUX_CMD_AO
 
- USBDUX_CMD_DIO_BITS
 
- USBDUX_CMD_DIO_CFG
 
- USBDUX_CMD_MULT_AI
 
- USBDUX_CMD_PWM_OFF
 
- USBDUX_CMD_PWM_ON
 
- USBDUX_CMD_SINGLE_AI
 
- USBDUX_CMD_TIMER_RD
 
- USBDUX_CMD_TIMER_WR
 
- USBDUX_CPU_CS
 
- USBDUX_FIRMWARE
 
- USBDUX_FIRMWARE_CMD
 
- USBDUX_FIRMWARE_MAX_LEN
 
- USBD_CCEMPTY
 
- USBD_CDFULL
 
- USBD_CLK_ENB
 
- USBD_CMDCODE
 
- USBD_CMDDATA
 
- USBD_CMD_CODE
 
- USBD_CMD_PHASE
 
- USBD_CONTROL_AUTO_CSRS_MASK
 
- USBD_CONTROL_AUTO_CSRS_SHIFT
 
- USBD_CONTROL_DONE_CSRS_MASK
 
- USBD_CONTROL_DONE_CSRS_SHIFT
 
- USBD_CONTROL_FIFO_RESET_MASK
 
- USBD_CONTROL_FIFO_RESET_SHIFT
 
- USBD_CONTROL_INIT_SEL_MASK
 
- USBD_CONTROL_INIT_SEL_SHIFT
 
- USBD_CONTROL_REG
 
- USBD_CONTROL_RXZSCFG_MASK
 
- USBD_CONTROL_RXZSCFG_SHIFT
 
- USBD_CONTROL_SETUPERRLOCK_MASK
 
- USBD_CONTROL_SETUPERRLOCK_SHIFT
 
- USBD_CONTROL_TXZLENINS_MASK
 
- USBD_CONTROL_TXZLENINS_SHIFT
 
- USBD_CSR_EP_ALTIFACE_MASK
 
- USBD_CSR_EP_ALTIFACE_SHIFT
 
- USBD_CSR_EP_CFG_MASK
 
- USBD_CSR_EP_CFG_SHIFT
 
- USBD_CSR_EP_DIR_MASK
 
- USBD_CSR_EP_DIR_SHIFT
 
- USBD_CSR_EP_IFACE_MASK
 
- USBD_CSR_EP_IFACE_SHIFT
 
- USBD_CSR_EP_LOG_MASK
 
- USBD_CSR_EP_LOG_SHIFT
 
- USBD_CSR_EP_MAXPKT_MASK
 
- USBD_CSR_EP_MAXPKT_SHIFT
 
- USBD_CSR_EP_REG
 
- USBD_CSR_EP_TYPE_MASK
 
- USBD_CSR_EP_TYPE_SHIFT
 
- USBD_CSR_SETUPADDR_DEF
 
- USBD_CSR_SETUPADDR_REG
 
- USBD_CTRL
 
- USBD_DEVINTCLR
 
- USBD_DEVINTEN
 
- USBD_DEVINTPRI
 
- USBD_DEVINTSET
 
- USBD_DEVINTST
 
- USBD_DEV_STAT
 
- USBD_DMAEP
 
- USBD_DMAINTEN
 
- USBD_DMAINTST
 
- USBD_DMARCLR
 
- USBD_DMARSET
 
- USBD_DMARST
 
- USBD_DV
 
- USBD_EOTINTCLR
 
- USBD_EOTINTSET
 
- USBD_EOTINTST
 
- USBD_EOT_INT
 
- USBD_EPDMADIS
 
- USBD_EPDMAEN
 
- USBD_EPDMAST
 
- USBD_EPIND
 
- USBD_EPINTCLR
 
- USBD_EPINTEN
 
- USBD_EPINTPRI
 
- USBD_EPINTSET
 
- USBD_EPINTST
 
- USBD_EPMAXPSIZE
 
- USBD_EPNUM_TYPEMAP_DMA_CH_MASK
 
- USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT
 
- USBD_EPNUM_TYPEMAP_REG
 
- USBD_EPNUM_TYPEMAP_TYPE_MASK
 
- USBD_EPNUM_TYPEMAP_TYPE_SHIFT
 
- USBD_EP_FAST
 
- USBD_EP_RLZED
 
- USBD_EP_SEL
 
- USBD_EP_SLOW
 
- USBD_ERR_INT
 
- USBD_EVENTS_REG
 
- USBD_EVENTS_USB_LINK_MASK
 
- USBD_EVENTS_USB_LINK_SHIFT
 
- USBD_EVENT_IRQ_CFG_FALLING
 
- USBD_EVENT_IRQ_CFG_HI_REG
 
- USBD_EVENT_IRQ_CFG_LO_REG
 
- USBD_EVENT_IRQ_CFG_MASK
 
- USBD_EVENT_IRQ_CFG_RISING
 
- USBD_EVENT_IRQ_CFG_SHIFT
 
- USBD_EVENT_IRQ_EARLY_SUSPEND
 
- USBD_EVENT_IRQ_ENUM_ON
 
- USBD_EVENT_IRQ_ERRATIC_ERR
 
- USBD_EVENT_IRQ_MASK_REG
 
- USBD_EVENT_IRQ_SETCFG
 
- USBD_EVENT_IRQ_SETINTF
 
- USBD_EVENT_IRQ_SETUP
 
- USBD_EVENT_IRQ_SET_CSRS
 
- USBD_EVENT_IRQ_SOF
 
- USBD_EVENT_IRQ_STATUS_REG
 
- USBD_EVENT_IRQ_SUSPEND
 
- USBD_EVENT_IRQ_USB_LINK
 
- USBD_EVENT_IRQ_USB_RESET
 
- USBD_FRAME
 
- USBD_LOG_ENDPOINT
 
- USBD_NDDRTINTCLR
 
- USBD_NDDRTINTSET
 
- USBD_NDDRTINTST
 
- USBD_NEW_DD_INT
 
- USBD_PKT_RDY
 
- USBD_PK_LEN_MASK
 
- USBD_RD_EN
 
- USBD_REEP
 
- USBD_RXDATA
 
- USBD_RXENDPKT
 
- USBD_RXFIFO_CONFIG_END_MASK
 
- USBD_RXFIFO_CONFIG_END_SHIFT
 
- USBD_RXFIFO_CONFIG_REG
 
- USBD_RXFIFO_CONFIG_START_MASK
 
- USBD_RXFIFO_CONFIG_START_SHIFT
 
- USBD_RXFIFO_EPSIZE_REG
 
- USBD_RXPLEN
 
- USBD_RX_EP_SEL
 
- USBD_STALL_ENABLE_MASK
 
- USBD_STALL_ENABLE_SHIFT
 
- USBD_STALL_EPNUM_MASK
 
- USBD_STALL_EPNUM_SHIFT
 
- USBD_STALL_REG
 
- USBD_STALL_UPDATE_MASK
 
- USBD_STALL_UPDATE_SHIFT
 
- USBD_STATUS_ALTINTF_MASK
 
- USBD_STATUS_ALTINTF_SHIFT
 
- USBD_STATUS_CFG_MASK
 
- USBD_STATUS_CFG_SHIFT
 
- USBD_STATUS_INTF_MASK
 
- USBD_STATUS_INTF_SHIFT
 
- USBD_STATUS_REG
 
- USBD_STATUS_SOF_MASK
 
- USBD_STATUS_SOF_SHIFT
 
- USBD_STATUS_SPD_MASK
 
- USBD_STATUS_SPD_SHIFT
 
- USBD_STRAPS_APP_8BITPHY_MASK
 
- USBD_STRAPS_APP_8BITPHY_SHIFT
 
- USBD_STRAPS_APP_CSRPRGSUP_MASK
 
- USBD_STRAPS_APP_CSRPRGSUP_SHIFT
 
- USBD_STRAPS_APP_DISCON_MASK
 
- USBD_STRAPS_APP_DISCON_SHIFT
 
- USBD_STRAPS_APP_RAM_IF_MASK
 
- USBD_STRAPS_APP_RAM_IF_SHIFT
 
- USBD_STRAPS_APP_RMTWKUP_MASK
 
- USBD_STRAPS_APP_RMTWKUP_SHIFT
 
- USBD_STRAPS_APP_SELF_PWR_MASK
 
- USBD_STRAPS_APP_SELF_PWR_SHIFT
 
- USBD_STRAPS_REG
 
- USBD_STRAPS_SPEED_MASK
 
- USBD_STRAPS_SPEED_SHIFT
 
- USBD_SYSERRTINTCLR
 
- USBD_SYSERRTINTSET
 
- USBD_SYSERRTINTST
 
- USBD_SYS_ERR_INT
 
- USBD_TXDATA
 
- USBD_TXENDPKT
 
- USBD_TXFIFO_CONFIG_END_MASK
 
- USBD_TXFIFO_CONFIG_END_SHIFT
 
- USBD_TXFIFO_CONFIG_REG
 
- USBD_TXFIFO_CONFIG_START_MASK
 
- USBD_TXFIFO_CONFIG_START_SHIFT
 
- USBD_TXFIFO_EPSIZE_REG
 
- USBD_TXPLEN
 
- USBD_TX_EP_SEL
 
- USBD_UDCAH
 
- USBD_WR_EN
 
- USBE
 
- USBER_ALL_CLEAR
 
- USBF
 
- USBFI
 
- USBFLBASEADD
 
- USBFRNUM
 
- USBFS_XFER_MAX
 
- USBF_SPD
 
- USBGEAR_USBG_V1
 
- USBGENCTRL
 
- USBGENCTRL_PFP
 
- USBGENCTRL_PPP
 
- USBG_BOT_CMD_PEND
 
- USBG_ENABLED
 
- USBG_IS_BOT
 
- USBG_IS_UAS
 
- USBG_MAX_CMD
 
- USBG_NAMELEN
 
- USBG_USE_STREAMS
 
- USBH
 
- USBH0_CLK_ENB
 
- USBH1_CLK_ENB
 
- USBH1_MODE
 
- USBH1_VBUSEN_B
 
- USBH2_CS
 
- USBH2_EN_B
 
- USBH2_PHY_CS_GPIO
 
- USBH2_RESET
 
- USBH2_RST_B
 
- USBHEN_BE
 
- USBHEN_C
 
- USBHEN_CE
 
- USBHEN_E
 
- USBHEN_RD
 
- USBHI
 
- USBHOST_RSTN
 
- USBHOST_SHUT
 
- USBHPENA_GPIO
 
- USBHPENB_GPIO
 
- USBHSF_PKT_DMA_DONE
 
- USBHSF_PKT_PREPARE
 
- USBHSF_PKT_TRY_RUN
 
- USBHSG_STATUS_REGISTERD
 
- USBHSG_STATUS_SELF_POWERED
 
- USBHSG_STATUS_SOFT_CONNECT
 
- USBHSG_STATUS_STARTED
 
- USBHSG_STATUS_WEDGE
 
- USBHSH_DEVICE_MAX
 
- USBHSH_PORT_MAX
 
- USBHSIC_CTRL
 
- USBHS_DFIFO_INIT
 
- USBHS_DFIFO_INIT_NO_PORT
 
- USBHS_DRIVER_NAME
 
- USBHS_GADGET
 
- USBHS_HOST
 
- USBHS_LPSTS
 
- USBHS_LPSTS_SUSPM
 
- USBHS_MAX
 
- USBHS_MAX_NUM_DFIFO
 
- USBHS_PIPE_FLAGS_IS_DIR_HOST
 
- USBHS_PIPE_FLAGS_IS_DIR_IN
 
- USBHS_PIPE_FLAGS_IS_RUNNING
 
- USBHS_PIPE_FLAGS_IS_USED
 
- USBHS_UGCTRL
 
- USBHS_UGCTRL2
 
- USBHS_UGCTRL2_USB0SEL
 
- USBHS_UGCTRL2_USB0SEL_HS_USB
 
- USBHS_UGCTRL2_USB0SEL_HS_USB20
 
- USBHS_UGCTRL2_USB0SEL_PCI
 
- USBHS_UGCTRL2_USB0SEL_USB20
 
- USBHS_UGCTRL2_USB2SEL
 
- USBHS_UGCTRL2_USB2SEL_PCI
 
- USBHS_UGCTRL2_USB2SEL_USB30
 
- USBHS_UGCTRL_CONNECT
 
- USBHS_UGCTRL_PLLRESET
 
- USBHS_UGSTS
 
- USBHS_UGSTS_LOCK
 
- USBHS_USB_DMAC_XFER_SIZE
 
- USBH_CLK_ENB
 
- USBH_ETDDONEEN
 
- USBH_ETDDONESTAT
 
- USBH_ETDENCLR
 
- USBH_ETDENSET
 
- USBH_FRMNUB
 
- USBH_HOST_CTRL
 
- USBH_HOST_CTRL_CTLBLKSR_1
 
- USBH_HOST_CTRL_CTLBLKSR_2
 
- USBH_HOST_CTRL_CTLBLKSR_3
 
- USBH_HOST_CTRL_CTLBLKSR_4
 
- USBH_HOST_CTRL_HCRESET
 
- USBH_HOST_CTRL_HCUSBSTE_OPERATIONAL
 
- USBH_HOST_CTRL_HCUSBSTE_RESET
 
- USBH_HOST_CTRL_HCUSBSTE_RESUME
 
- USBH_HOST_CTRL_HCUSBSTE_SUSPEND
 
- USBH_HOST_CTRL_RMTWUEN
 
- USBH_HOST_CTRL_SCHDOVR
 
- USBH_IMMEDINT
 
- USBH_LSTHRESH
 
- USBH_PORTSTAT
 
- USBH_PORTSTAT_CONNECTSC
 
- USBH_PORTSTAT_CURCONST
 
- USBH_PORTSTAT_LSDEVCON
 
- USBH_PORTSTAT_OVRCURIC
 
- USBH_PORTSTAT_PRTENABST
 
- USBH_PORTSTAT_PRTENBLSC
 
- USBH_PORTSTAT_PRTOVRCURI
 
- USBH_PORTSTAT_PRTPWRST
 
- USBH_PORTSTAT_PRTRSTSC
 
- USBH_PORTSTAT_PRTRSTST
 
- USBH_PORTSTAT_PRTSTATSC
 
- USBH_PORTSTAT_PRTSUSPST
 
- USBH_PRIV_SETUP_6368_REG
 
- USBH_PRIV_SETUP_IOC_MASK
 
- USBH_PRIV_SETUP_IOC_SHIFT
 
- USBH_PRIV_SWAP_6358_REG
 
- USBH_PRIV_SWAP_6368_REG
 
- USBH_PRIV_SWAP_EHCI_DATA_MASK
 
- USBH_PRIV_SWAP_EHCI_DATA_SHIFT
 
- USBH_PRIV_SWAP_EHCI_ENDN_MASK
 
- USBH_PRIV_SWAP_EHCI_ENDN_SHIFT
 
- USBH_PRIV_SWAP_OHCI_DATA_MASK
 
- USBH_PRIV_SWAP_OHCI_DATA_SHIFT
 
- USBH_PRIV_SWAP_OHCI_ENDN_MASK
 
- USBH_PRIV_SWAP_OHCI_ENDN_SHIFT
 
- USBH_PRIV_SWAP_USBD_MASK
 
- USBH_PRIV_SWAP_USBD_SHIFT
 
- USBH_PRIV_TEST_6358_REG
 
- USBH_PRIV_TEST_6368_REG
 
- USBH_PRIV_UTMI_CTL_6368_REG
 
- USBH_PRIV_UTMI_CTL_HOSTB_MASK
 
- USBH_PRIV_UTMI_CTL_HOSTB_SHIFT
 
- USBH_PRIV_UTMI_CTL_NODRIV_MASK
 
- USBH_PRIV_UTMI_CTL_NODRIV_SHIFT
 
- USBH_R
 
- USBH_ROOTHUBA
 
- USBH_ROOTHUBA_DEVTYPE
 
- USBH_ROOTHUBA_NDNSTMPRT_MASK
 
- USBH_ROOTHUBA_NOOVRCURP
 
- USBH_ROOTHUBA_NOPWRSWT
 
- USBH_ROOTHUBA_OVRCURPM
 
- USBH_ROOTHUBA_PWRSWTMD
 
- USBH_ROOTHUBA_PWRTOGOOD_MASK
 
- USBH_ROOTHUBA_PWRTOGOOD_SHIFT
 
- USBH_ROOTHUBB
 
- USBH_ROOTHUBB_DEVREMOVE
 
- USBH_ROOTHUBB_PRTPWRCM
 
- USBH_ROOTSTAT
 
- USBH_ROOTSTAT_CLRRMTWUE
 
- USBH_ROOTSTAT_DEVCONWUE
 
- USBH_ROOTSTAT_LOCPWRS
 
- USBH_ROOTSTAT_OVRCURCHG
 
- USBH_ROOTSTAT_OVRCURI
 
- USBH_SYSIEN
 
- USBH_SYSIEN_DONEINT
 
- USBH_SYSIEN_FMOFINT
 
- USBH_SYSIEN_HERRINT
 
- USBH_SYSIEN_PSCINT
 
- USBH_SYSIEN_RESDETINT
 
- USBH_SYSIEN_SOFINT
 
- USBH_SYSIEN_SORINT
 
- USBH_SYSISR
 
- USBH_SYSISR_DONEINT
 
- USBH_SYSISR_FMOFINT
 
- USBH_SYSISR_HERRINT
 
- USBH_SYSISR_PSCINT
 
- USBH_SYSISR_RESDETINT
 
- USBH_SYSISR_SOFINT
 
- USBH_SYSISR_SORINT
 
- USBH_XBUFSTAT
 
- USBH_XFILLSTAT
 
- USBH_XYINTEN
 
- USBH_YBUFSTAT
 
- USBH_YFILLSTAT
 
- USBI0
 
- USBI1
 
- USBIDS_FILE
 
- USBIF_BULK
 
- USBIF_CMDONLY
 
- USBIF_ISO_1
 
- USBIF_ISO_2
 
- USBIF_ISO_3
 
- USBIF_ISO_4
 
- USBIF_ISO_5
 
- USBIF_ISO_6
 
- USBINDX
 
- USBINITREG1
 
- USBINITREG2
 
- USBINITVAL1
 
- USBINITVAL2
 
- USBINTR
 
- USBINTR_ASYNC_ADV_AAE
 
- USBINTR_ASYNC_ADV_AAE_DISABLE
 
- USBINTR_ASYNC_ADV_AAE_ENABLE
 
- USBINTR_DEVICE_SUSPEND
 
- USBINTR_ERR_INT_EN
 
- USBINTR_INT_EN
 
- USBINTR_IOC
 
- USBINTR_PORT_CHANGE_DETECT_EN
 
- USBINTR_RESET_EN
 
- USBINTR_RESUME
 
- USBINTR_SOF_UFRAME_EN
 
- USBINTR_SP
 
- USBINTR_TIMEOUT
 
- USBIN_ACTION
 
- USBIP_CMD_SUBMIT
 
- USBIP_CMD_UNLINK
 
- USBIP_CORE_MOD_NAME
 
- USBIP_DEVICE_DRV_NAME
 
- USBIP_DIR_IN
 
- USBIP_DIR_OUT
 
- USBIP_EH_BYE
 
- USBIP_EH_RESET
 
- USBIP_EH_SHUTDOWN
 
- USBIP_EH_UNUSABLE
 
- USBIP_HOST_DRV_NAME
 
- USBIP_MAX_ISO_PACKETS
 
- USBIP_RET_SUBMIT
 
- USBIP_RET_UNLINK
 
- USBIP_STUB
 
- USBIP_VHCI
 
- USBIP_VHCI_BUS_TYPE
 
- USBIP_VHCI_DEVICE_NAME
 
- USBIP_VHCI_DRV_NAME
 
- USBIP_VUDC
 
- USBLCD_MINOR
 
- USBLEGSUP
 
- USBLEGSUP_DEFAULT
 
- USBLEGSUP_RO
 
- USBLEGSUP_RWC
 
- USBLENG
 
- USBLP_BUF_SIZE
 
- USBLP_BUF_SIZE_IN
 
- USBLP_CTL_TIMEOUT
 
- USBLP_DEVICE_ID_SIZE
 
- USBLP_FIRST_PROTOCOL
 
- USBLP_LAST_PROTOCOL
 
- USBLP_MAX_PROTOCOLS
 
- USBLP_MINORS
 
- USBLP_MINOR_BASE
 
- USBLP_QUIRK_BAD_CLASS
 
- USBLP_QUIRK_BIDIR
 
- USBLP_QUIRK_USB_INIT
 
- USBLP_REQ_GET_ID
 
- USBLP_REQ_GET_STATUS
 
- USBLP_REQ_HP_CHANNEL_CHANGE_REQUEST
 
- USBLP_REQ_RESET
 
- USBMODE_BE
 
- USBMODE_CI_SDIS
 
- USBMODE_CM
 
- USBMODE_CM_DC
 
- USBMODE_CM_HC
 
- USBMODE_CM_HOST
 
- USBMODE_CM_IDLE
 
- USBMODE_CM_MASK
 
- USBMODE_CTRL_MODE_DEVICE
 
- USBMODE_CTRL_MODE_HOST
 
- USBMODE_CTRL_MODE_IDLE
 
- USBMODE_CTRL_MODE_RSV
 
- USBMODE_ES
 
- USBMODE_EX_HC
 
- USBMODE_EX_VBPS
 
- USBMODE_SDIS
 
- USBMODE_SETUP_LOCK_OFF
 
- USBMODE_SLOM
 
- USBMODE_STREAM_DISABLE
 
- USBMSG_TYPE1
 
- USBMSG_TYPE2
 
- USBMSG_TYPE3
 
- USBMSG_TYPE4
 
- USBO
 
- USBOTG3CTRL2_POWERDOWN_HSP
 
- USBOTG3CTRL2_POWERDOWN_SSP
 
- USBOTG3_CTRL0
 
- USBOTG3_CTRL2
 
- USBOTG3_CTRL3
 
- USBOTG3_CTRL3_VBUSVLDEXT
 
- USBOTG3_CTRL3_VBUSVLDEXTSEL
 
- USBOTG3_CTRL4
 
- USBOTG3_CTRL7
 
- USBOTGSS_DEBUG_CFG
 
- USBOTGSS_DEBUG_DATA
 
- USBOTGSS_DEBUG_OFFSET
 
- USBOTGSS_DEV_EBC_EN
 
- USBOTGSS_EOI_OFFSET
 
- USBOTGSS_FLADJ
 
- USBOTGSS_IRQ0_OFFSET
 
- USBOTGSS_IRQENABLE_CLR_0
 
- USBOTGSS_IRQENABLE_CLR_1
 
- USBOTGSS_IRQENABLE_CLR_2
 
- USBOTGSS_IRQENABLE_CLR_3
 
- USBOTGSS_IRQENABLE_CLR_MISC
 
- USBOTGSS_IRQENABLE_SET_0
 
- USBOTGSS_IRQENABLE_SET_1
 
- USBOTGSS_IRQENABLE_SET_2
 
- USBOTGSS_IRQENABLE_SET_3
 
- USBOTGSS_IRQENABLE_SET_MISC
 
- USBOTGSS_IRQMISC_CHRGVBUS_FALL
 
- USBOTGSS_IRQMISC_CHRGVBUS_RISE
 
- USBOTGSS_IRQMISC_DISCHRGVBUS_FALL
 
- USBOTGSS_IRQMISC_DISCHRGVBUS_RISE
 
- USBOTGSS_IRQMISC_DMADISABLECLR
 
- USBOTGSS_IRQMISC_DRVVBUS_FALL
 
- USBOTGSS_IRQMISC_DRVVBUS_RISE
 
- USBOTGSS_IRQMISC_IDPULLUP_FALL
 
- USBOTGSS_IRQMISC_IDPULLUP_RISE
 
- USBOTGSS_IRQMISC_OEVT
 
- USBOTGSS_IRQMISC_OFFSET
 
- USBOTGSS_IRQO_COREIRQ_ST
 
- USBOTGSS_IRQSTATUS_0
 
- USBOTGSS_IRQSTATUS_1
 
- USBOTGSS_IRQSTATUS_2
 
- USBOTGSS_IRQSTATUS_3
 
- USBOTGSS_IRQSTATUS_EOI_MISC
 
- USBOTGSS_IRQSTATUS_MISC
 
- USBOTGSS_IRQSTATUS_RAW_0
 
- USBOTGSS_IRQSTATUS_RAW_1
 
- USBOTGSS_IRQSTATUS_RAW_2
 
- USBOTGSS_IRQSTATUS_RAW_3
 
- USBOTGSS_IRQSTATUS_RAW_MISC
 
- USBOTGSS_IRQ_EOI
 
- USBOTGSS_IRQ_EOI_LINE_NUMBER
 
- USBOTGSS_MMRAM_OFFSET
 
- USBOTGSS_REVISION
 
- USBOTGSS_RXFIFO_DEPTH
 
- USBOTGSS_SYSCONFIG
 
- USBOTGSS_SYSCONFIG_DMADISABLE
 
- USBOTGSS_TXFIFO_DEPTH
 
- USBOTGSS_UTMI_OTG_CTRL
 
- USBOTGSS_UTMI_OTG_CTRL_IDDIG
 
- USBOTGSS_UTMI_OTG_CTRL_POWERPRESENT
 
- USBOTGSS_UTMI_OTG_CTRL_SESSEND
 
- USBOTGSS_UTMI_OTG_CTRL_SESSVALID
 
- USBOTGSS_UTMI_OTG_CTRL_SW_MODE
 
- USBOTGSS_UTMI_OTG_CTRL_TXBITSTUFFENABLE
 
- USBOTGSS_UTMI_OTG_CTRL_VBUSVALID
 
- USBOTGSS_UTMI_OTG_OFFSET
 
- USBOTGSS_UTMI_OTG_STATUS
 
- USBOTGSS_UTMI_OTG_STATUS_CHRGVBUS
 
- USBOTGSS_UTMI_OTG_STATUS_DISCHRGVBUS
 
- USBOTGSS_UTMI_OTG_STATUS_DRVVBUS
 
- USBOTGSS_UTMI_OTG_STATUS_IDPULLUP
 
- USBOTG_ASFCINT
 
- USBOTG_ASHCINT
 
- USBOTG_ASHNPINT
 
- USBOTG_CINT_STAT
 
- USBOTG_CINT_STEN
 
- USBOTG_CLK_CTRL
 
- USBOTG_CLK_CTRL_FUNC
 
- USBOTG_CLK_CTRL_HST
 
- USBOTG_CLK_CTRL_MAIN
 
- USBOTG_DMEM
 
- USBOTG_FCINT
 
- USBOTG_FRM_INTVL
 
- USBOTG_FRM_REMAIN
 
- USBOTG_HCINT
 
- USBOTG_HNP_CSR
 
- USBOTG_HNP_IEN
 
- USBOTG_HNP_ISR
 
- USBOTG_HWMODE
 
- USBOTG_HWMODE_ANASDBEN
 
- USBOTG_HWMODE_CRECFG_FUNC
 
- USBOTG_HWMODE_CRECFG_HNP
 
- USBOTG_HWMODE_CRECFG_HOST
 
- USBOTG_HWMODE_CRECFG_MASK
 
- USBOTG_HWMODE_HOSTXCVR_MASK
 
- USBOTG_HWMODE_HOSTXCVR_SHIFT
 
- USBOTG_HWMODE_HOSTXCVR_TD_RD
 
- USBOTG_HWMODE_HOSTXCVR_TD_RS
 
- USBOTG_HWMODE_HOSTXCVR_TS_RD
 
- USBOTG_HWMODE_HOSTXCVR_TS_RS
 
- USBOTG_HWMODE_OTGXCVR_MASK
 
- USBOTG_HWMODE_OTGXCVR_SHIFT
 
- USBOTG_HWMODE_OTGXCVR_TD_RD
 
- USBOTG_HWMODE_OTGXCVR_TD_RS
 
- USBOTG_HWMODE_OTGXCVR_TS_RD
 
- USBOTG_HWMODE_OTGXCVR_TS_RS
 
- USBOTG_I2C_MASTER_INT_REG
 
- USBOTG_I2C_OP_CTRL_REG
 
- USBOTG_I2C_SCLK_TO_SCK_HPER
 
- USBOTG_I2C_SEQ_OP_REG
 
- USBOTG_I2C_SEQ_RD_STARTAD
 
- USBOTG_I2C_TXCVR_REG
 
- USBOTG_I2C_XCVR_DEVAD
 
- USBOTG_INTR_OFFSET
 
- USBOTG_RST_B
 
- USBOTG_RST_CTRL
 
- USBOTG_RST_RSTCTRL
 
- USBOTG_RST_RSTFC
 
- USBOTG_RST_RSTFSKE
 
- USBOTG_RST_RSTHC
 
- USBOTG_RST_RSTHSIE
 
- USBOTG_RST_RSTI2C
 
- USBOTG_RST_RSTRH
 
- USBOTG_SHNPINT
 
- USBOTG_SHUT
 
- USBO_K
 
- USBO_R
 
- USBPCR1_REFCLKDIV_12
 
- USBPCR1_REFCLKDIV_19_2
 
- USBPCR1_REFCLKDIV_24
 
- USBPCR1_REFCLKDIV_48
 
- USBPCR1_REFCLKDIV_MASK
 
- USBPCR1_REFCLKDIV_SHIFT
 
- USBPCR1_REFCLKSEL_CORE
 
- USBPCR1_REFCLKSEL_MASK
 
- USBPCR1_REFCLKSEL_SHIFT
 
- USBPCR1_UHC_POWER
 
- USBPCR1_USB_SEL
 
- USBPCR1_WORD_IF0
 
- USBPCR1_WORD_IF1
 
- USBPCR_COMMONONN
 
- USBPCR_COMPDISTUNE_MASK
 
- USBPCR_IDPULLUP_MASK
 
- USBPCR_OTGTUNE_MASK
 
- USBPCR_OTG_DISABLE
 
- USBPCR_POR
 
- USBPCR_SQRXTUNE_MASK
 
- USBPCR_TXFSLSTUNE_MASK
 
- USBPCR_TXHSXVTUNE_MASK
 
- USBPCR_TXPREEMPHTUNE
 
- USBPCR_TXVREFTUNE_MASK
 
- USBPCR_USB_MODE
 
- USBPCR_VBUSVLDEXT
 
- USBPCR_VBUSVLDEXTSEL
 
- USBPCTL1
 
- USBPHY
 
- USBPHYCTRL_EVDO
 
- USBPHYCTRL_OTGBASE_OFFSET
 
- USBPHY_CDET_EXTCTL
 
- USBPHY_CHGDET_DIS
 
- USBPHY_CHGDET_RSTRT
 
- USBPHY_CHGISINK_EN
 
- USBPHY_CHGVSRC_EN
 
- USBPHY_CLKO1SEL
 
- USBPHY_CM_PWRDN
 
- USBPHY_CTL_PADDR
 
- USBPHY_DATAPOL
 
- USBPHY_DATA_POLARITY
 
- USBPHY_DMGPIO_PD
 
- USBPHY_DMINPUT
 
- USBPHY_DMOPBUFCTL
 
- USBPHY_DMPULLUP
 
- USBPHY_DPGPIO_PD
 
- USBPHY_DPINPUT
 
- USBPHY_DPOPBUFCTL
 
- USBPHY_DPPULLUP
 
- USBPHY_GPIO_MODE
 
- USBPHY_INTERFACE_MODE_HSIC
 
- USBPHY_INTERFACE_MODE_SERIAL
 
- USBPHY_INTERFACE_MODE_ULPI
 
- USBPHY_INTERFACE_MODE_UNKNOWN
 
- USBPHY_INTERFACE_MODE_UTMI
 
- USBPHY_INTERFACE_MODE_UTMIW
 
- USBPHY_K
 
- USBPHY_OSCPDWN
 
- USBPHY_OTGPDWN
 
- USBPHY_OTGSESSEND_EN
 
- USBPHY_OTGVDET_EN
 
- USBPHY_OTG_PWRDN
 
- USBPHY_PHYCLKGD
 
- USBPHY_PHYPDWN
 
- USBPHY_PHYPLLON
 
- USBPHY_R
 
- USBPHY_SESNDEN
 
- USBPHY_SINKONDP
 
- USBPHY_SRCONDM
 
- USBPHY_VBDTCTEN
 
- USBPHY_VBUSSENS
 
- USBPORT1EN
 
- USBPORT2EN
 
- USBPORTSC1
 
- USBPORTSC2
 
- USBPORTSC3
 
- USBPORTSC4
 
- USBPORTSC_CCS
 
- USBPORTSC_CSC
 
- USBPORTSC_DMINUS
 
- USBPORTSC_DPLUS
 
- USBPORTSC_LSDA
 
- USBPORTSC_OC
 
- USBPORTSC_OCC
 
- USBPORTSC_PE
 
- USBPORTSC_PEC
 
- USBPORTSC_PR
 
- USBPORTSC_RD
 
- USBPORTSC_RES1
 
- USBPORTSC_RES2
 
- USBPORTSC_RES3
 
- USBPORTSC_RES4
 
- USBPORTSC_SUSP
 
- USBP_TM_BULK
 
- USBP_TM_CTL
 
- USBP_TM_INT
 
- USBP_TM_ISO
 
- USBRDT_USBRDT_MASK
 
- USBRDT_VBFIL_LD_EN
 
- USBREQ
 
- USBRES_INTEL
 
- USBRST
 
- USBR_MASTER_SW1
 
- USBR_MASTER_SW2
 
- USBR_NSUSPEND
 
- USBR_REGOUT
 
- USBR_SEMODE
 
- USBR_SLAVE_CONTROL
 
- USBR_SLAVE_SW
 
- USBR_SPEED
 
- USBR_VPPVIO_SW
 
- USBSOF
 
- USBSOF_DEFAULT
 
- USBSPD
 
- USBSPD_SPEED_FULL
 
- USBSPD_SPEED_HIGH
 
- USBSPD_SPEED_LOW
 
- USBSS_IRQENABLE_CLR_0
 
- USBSS_IRQENABLE_SET_0
 
- USBSS_IRQSTATUS_0
 
- USBSS_IRQSTATUS_RAW_0
 
- USBSS_IRQ_CLEARR
 
- USBSS_IRQ_COREIRQ_CLR
 
- USBSS_IRQ_COREIRQ_EN
 
- USBSS_IRQ_ENABLER
 
- USBSS_IRQ_EOI
 
- USBSS_IRQ_EOI_LINE
 
- USBSS_IRQ_EVENT_ST
 
- USBSS_IRQ_PD_COMP
 
- USBSS_IRQ_STATUS
 
- USBSS_REVISION
 
- USBSS_SYSCONFIG
 
- USBST
 
- USBSTAT0
 
- USBSTATE_ADDRESSED
 
- USBSTATE_CONFIGURED
 
- USBSTATE_DEFAULT
 
- USBSTS
 
- USBSTS_ASYNC_SCHEDULE
 
- USBSTS_ERR
 
- USBSTS_ERROR
 
- USBSTS_FRM_LST_ROLL
 
- USBSTS_HCH
 
- USBSTS_HCPE
 
- USBSTS_HC_HALTED
 
- USBSTS_HSE
 
- USBSTS_IAA
 
- USBSTS_INT
 
- USBSTS_PERIODIC_SCHEDULE
 
- USBSTS_PORT_CHANGE
 
- USBSTS_RCL
 
- USBSTS_RD
 
- USBSTS_RESET
 
- USBSTS_SOF
 
- USBSTS_SUSPEND
 
- USBSTS_SYS_ERR
 
- USBSTS_USBINT
 
- USBSW_OTG_SWITCH_ENABLED
 
- USBTEST
 
- USBTEST_REQUEST
 
- USBTEST_REQUEST_32
 
- USBTEST_REQUEST_64
 
- USBTLL_DRIVER_NAME
 
- USBTMC488_CAPABILITY_488_DOT_2
 
- USBTMC488_CAPABILITY_DT1
 
- USBTMC488_CAPABILITY_FULL_SCPI
 
- USBTMC488_CAPABILITY_GOTO_LOCAL
 
- USBTMC488_CAPABILITY_LOCAL_LOCKOUT
 
- USBTMC488_CAPABILITY_REN_CONTROL
 
- USBTMC488_CAPABILITY_RL1
 
- USBTMC488_CAPABILITY_SIMPLE
 
- USBTMC488_CAPABILITY_SR1
 
- USBTMC488_CAPABILITY_TRIGGER
 
- USBTMC488_IOCTL_GET_CAPS
 
- USBTMC488_IOCTL_GOTO_LOCAL
 
- USBTMC488_IOCTL_LOCAL_LOCKOUT
 
- USBTMC488_IOCTL_READ_STB
 
- USBTMC488_IOCTL_REN_CONTROL
 
- USBTMC488_IOCTL_TRIGGER
 
- USBTMC488_IOCTL_WAIT_SRQ
 
- USBTMC488_REQUEST_GOTO_LOCAL
 
- USBTMC488_REQUEST_LOCAL_LOCKOUT
 
- USBTMC488_REQUEST_READ_STATUS_BYTE
 
- USBTMC488_REQUEST_REN_CONTROL
 
- USBTMC_API_VERSION
 
- USBTMC_BUFSIZE
 
- USBTMC_FLAG_APPEND
 
- USBTMC_FLAG_ASYNC
 
- USBTMC_FLAG_IGNORE_TRAILER
 
- USBTMC_HEADER_SIZE
 
- USBTMC_IOCTL_ABORT_BULK_IN
 
- USBTMC_IOCTL_ABORT_BULK_OUT
 
- USBTMC_IOCTL_API_VERSION
 
- USBTMC_IOCTL_AUTO_ABORT
 
- USBTMC_IOCTL_CANCEL_IO
 
- USBTMC_IOCTL_CLEANUP_IO
 
- USBTMC_IOCTL_CLEAR
 
- USBTMC_IOCTL_CLEAR_IN_HALT
 
- USBTMC_IOCTL_CLEAR_OUT_HALT
 
- USBTMC_IOCTL_CONFIG_TERMCHAR
 
- USBTMC_IOCTL_CTRL_REQUEST
 
- USBTMC_IOCTL_EOM_ENABLE
 
- USBTMC_IOCTL_GET_TIMEOUT
 
- USBTMC_IOCTL_INDICATOR_PULSE
 
- USBTMC_IOCTL_MSG_IN_ATTR
 
- USBTMC_IOCTL_READ
 
- USBTMC_IOCTL_SET_TIMEOUT
 
- USBTMC_IOCTL_WRITE
 
- USBTMC_IOCTL_WRITE_RESULT
 
- USBTMC_IOC_NR
 
- USBTMC_MAX_READS_TO_CLEAR_BULK_IN
 
- USBTMC_MINOR_BASE
 
- USBTMC_MIN_TIMEOUT
 
- USBTMC_REQUEST_CHECK_ABORT_BULK_IN_STATUS
 
- USBTMC_REQUEST_CHECK_ABORT_BULK_OUT_STATUS
 
- USBTMC_REQUEST_CHECK_CLEAR_STATUS
 
- USBTMC_REQUEST_GET_CAPABILITIES
 
- USBTMC_REQUEST_INDICATOR_PULSE
 
- USBTMC_REQUEST_INITIATE_ABORT_BULK_IN
 
- USBTMC_REQUEST_INITIATE_ABORT_BULK_OUT
 
- USBTMC_REQUEST_INITIATE_CLEAR
 
- USBTMC_STATUS_FAILED
 
- USBTMC_STATUS_PENDING
 
- USBTMC_STATUS_SPLIT_IN_PROGRESS
 
- USBTMC_STATUS_SPLIT_NOT_IN_PROGRESS
 
- USBTMC_STATUS_SUCCESS
 
- USBTMC_STATUS_TRANSFER_NOT_IN_PROGRESS
 
- USBTMC_TIMEOUT
 
- USBTRDTIM_UTMI_16_BIT
 
- USBTRDTIM_UTMI_8_BIT
 
- USBTV_AUDIO_BUFFER
 
- USBTV_AUDIO_ENDP
 
- USBTV_AUDIO_HDRSIZE
 
- USBTV_AUDIO_URBSIZE
 
- USBTV_BASE
 
- USBTV_CHUNK
 
- USBTV_CHUNK_NO
 
- USBTV_CHUNK_SIZE
 
- USBTV_COMPOSITE_INPUT
 
- USBTV_CONTROL_REG
 
- USBTV_FRAME_ID
 
- USBTV_ISOC_PACKETS
 
- USBTV_ISOC_TRANSFERS
 
- USBTV_MAGIC_OK
 
- USBTV_ODD
 
- USBTV_REQUEST_REG
 
- USBTV_SVIDEO_INPUT
 
- USBTV_TV_STD
 
- USBTV_VIDEO_ENDP
 
- USBUSX2Y_H
 
- USBVAL
 
- USBVBFIL_IDDIGFIL_MASK
 
- USBVBFIL_IDDIGFIL_SHIFT
 
- USBVBFIL_USBVBFIL_MASK
 
- USBVISION_16_422_SYNC
 
- USBVISION_8_422_SYNC
 
- USBVISION_ADRS_REG
 
- USBVISION_ALTER_REG
 
- USBVISION_AUDIO_CONT
 
- USBVISION_AUDIO_IN
 
- USBVISION_AUDIO_MUTE
 
- USBVISION_AUDIO_RADIO
 
- USBVISION_AUDIO_TV
 
- USBVISION_AUD_PK_LEN
 
- USBVISION_AUTO_FID
 
- USBVISION_BLK_PK_LEN
 
- USBVISION_BUF_THR
 
- USBVISION_CLIPMASK_SIZE
 
- USBVISION_CLK_OUT
 
- USBVISION_CONFIG_REG
 
- USBVISION_DAT_IO
 
- USBVISION_DEBUG
 
- USBVISION_DIST_THR_H
 
- USBVISION_DIST_THR_L
 
- USBVISION_DRM_CONT
 
- USBVISION_DRM_PRM1
 
- USBVISION_DRM_PRM2
 
- USBVISION_DRM_PRM3
 
- USBVISION_DRM_PRM4
 
- USBVISION_DRM_PRM5
 
- USBVISION_DRM_PRM6
 
- USBVISION_DRM_PRM7
 
- USBVISION_DRM_PRM8
 
- USBVISION_DVI_YUV
 
- USBVISION_E2_EN
 
- USBVISION_EE_CONT
 
- USBVISION_EE_DATA
 
- USBVISION_EE_LSBAD
 
- USBVISION_FID_POL
 
- USBVISION_FILT_CONT
 
- USBVISION_FIX_2C
 
- USBVISION_FORCE_ALTER_REG
 
- USBVISION_FORCE_INTRA
 
- USBVISION_FORCE_UP
 
- USBVISION_FRAME_FORMAT_PARAM_INTRA
 
- USBVISION_FRM_RATE
 
- USBVISION_HEADER_LENGTH
 
- USBVISION_HSNC_POL
 
- USBVISION_HVALID_PO
 
- USBVISION_IIC_LRACK
 
- USBVISION_IIC_LRNACK
 
- USBVISION_INTRA_CYC
 
- USBVISION_IOPIN_REG
 
- USBVISION_IO_1
 
- USBVISION_IO_2
 
- USBVISION_IS_OPERATIONAL
 
- USBVISION_KEEP_BLANK
 
- USBVISION_LXSIZE_I
 
- USBVISION_LXSIZE_O
 
- USBVISION_LX_OFFST
 
- USBVISION_LYSIZE_I
 
- USBVISION_LYSIZE_O
 
- USBVISION_LY_OFFST
 
- USBVISION_MAGIC_1
 
- USBVISION_MAGIC_2
 
- USBVISION_MAX_DIST_H
 
- USBVISION_MAX_DIST_L
 
- USBVISION_MXSIZE_I
 
- USBVISION_MXSIZE_O
 
- USBVISION_MX_OFFST
 
- USBVISION_MYSIZE_I
 
- USBVISION_MYSIZE_O
 
- USBVISION_MY_OFFST
 
- USBVISION_NOHVALID
 
- USBVISION_NONE_INTER
 
- USBVISION_NORMS
 
- USBVISION_NUMFRAMES
 
- USBVISION_NUMSBUF
 
- USBVISION_NUM_HEADERMARKER
 
- USBVISION_OP_CODE
 
- USBVISION_PCM_THR1
 
- USBVISION_PCM_THR2
 
- USBVISION_POWEROFF_TIME
 
- USBVISION_PWR_REG
 
- USBVISION_PWR_VID
 
- USBVISION_REF
 
- USBVISION_RES2
 
- USBVISION_RES_FDL
 
- USBVISION_RES_UR
 
- USBVISION_RES_VDW
 
- USBVISION_SAA7111_ADDR
 
- USBVISION_SAA7113_ADDR
 
- USBVISION_SEND_FID
 
- USBVISION_SENS_OUT
 
- USBVISION_SER_ADRS
 
- USBVISION_SER_CONT
 
- USBVISION_SER_DAT1
 
- USBVISION_SER_DAT2
 
- USBVISION_SER_DAT3
 
- USBVISION_SER_DAT4
 
- USBVISION_SER_MODE
 
- USBVISION_SER_MODE_SIO
 
- USBVISION_SER_MODE_SOFT
 
- USBVISION_SSPND_EN
 
- USBVISION_STATUS_REG
 
- USBVISION_STRIP_HEADER_LEN
 
- USBVISION_STRIP_LEN_MAX
 
- USBVISION_STRIP_MAGIC
 
- USBVISION_STRIP_SZ
 
- USBVISION_SUPPORTED_PALETTES
 
- USBVISION_URB_FRAMES
 
- USBVISION_UV_ID
 
- USBVISION_VCLK_POL
 
- USBVISION_VERSION_STRING
 
- USBVISION_VIN_REG1
 
- USBVISION_VIN_REG2
 
- USBVISION_VO_MODE
 
- USBVISION_VSNC_POL
 
- USBX_SYNCHRO
 
- USB_0P1A
 
- USB_0P2A
 
- USB_0P3A
 
- USB_0P4A
 
- USB_0P5A
 
- USB_2WIRE_VENDOR_ID
 
- USB_2WIRE_WIRELESS_ID
 
- USB_3070_PRODUCT_ID
 
- USB_3075_PRODUCT_ID
 
- USB_30_GDSC
 
- USB_3_3_EN
 
- USB_3_3_RDY
 
- USB_5GBPS_OPERATION
 
- USB_8DEV_ABP_CLOCK
 
- USB_8DEV_BAUD_MANUAL
 
- USB_8DEV_CLOSE
 
- USB_8DEV_CMD_END
 
- USB_8DEV_CMD_ERROR
 
- USB_8DEV_CMD_START
 
- USB_8DEV_CMD_SUCCESS
 
- USB_8DEV_CMD_TIMEOUT
 
- USB_8DEV_DATA_END
 
- USB_8DEV_DATA_START
 
- USB_8DEV_DISABLE_AUTO_RESTRANS
 
- USB_8DEV_ENDP_CMD_RX
 
- USB_8DEV_ENDP_CMD_TX
 
- USB_8DEV_ENDP_DATA_RX
 
- USB_8DEV_ENDP_DATA_TX
 
- USB_8DEV_ERR_FLAG
 
- USB_8DEV_EXTID
 
- USB_8DEV_GET_HARDW_VER
 
- USB_8DEV_GET_SERIAL
 
- USB_8DEV_GET_SOFTW_HARDW_VER
 
- USB_8DEV_GET_SOFTW_VER
 
- USB_8DEV_GET_STATISTICS
 
- USB_8DEV_GET_STATUS
 
- USB_8DEV_LOOPBACK
 
- USB_8DEV_OPEN
 
- USB_8DEV_PRODUCT_ID
 
- USB_8DEV_RESET
 
- USB_8DEV_RESET_TIMESTAMP
 
- USB_8DEV_RP_MASK
 
- USB_8DEV_RTR
 
- USB_8DEV_SET_MASK_FILTER
 
- USB_8DEV_SET_SPEED
 
- USB_8DEV_SILENT
 
- USB_8DEV_STATUSMSG_ACK
 
- USB_8DEV_STATUSMSG_BIT0
 
- USB_8DEV_STATUSMSG_BIT1
 
- USB_8DEV_STATUSMSG_BUSHEAVY
 
- USB_8DEV_STATUSMSG_BUSLIGHT
 
- USB_8DEV_STATUSMSG_BUSOFF
 
- USB_8DEV_STATUSMSG_CRC
 
- USB_8DEV_STATUSMSG_FORM
 
- USB_8DEV_STATUSMSG_OK
 
- USB_8DEV_STATUSMSG_OVERRUN
 
- USB_8DEV_STATUSMSG_STUFF
 
- USB_8DEV_STATUS_FRAME
 
- USB_8DEV_TYPE_CAN_FRAME
 
- USB_8DEV_TYPE_ERROR_FRAME
 
- USB_8DEV_VENDOR_ID
 
- USB_ACM_AUX_MAJOR
 
- USB_ACM_MAJOR
 
- USB_ACPI_LOCATION_VALID
 
- USB_ADDR
 
- USB_ADRS_SHIFT
 
- USB_AFE_CTRL2
 
- USB_AGERE_MODEL0801_ID
 
- USB_AGERE_MODEL0802_ID
 
- USB_AGERE_REBRANDED_ID
 
- USB_AGERE_VENDOR_ID
 
- USB_AGG_EN
 
- USB_AMRADIO_PRODUCT
 
- USB_AMRADIO_VENDOR
 
- USB_ATI_MEMO_PRO_2HS_V2_PRODUCT_ID
 
- USB_ATI_USBCAN_PRO_2HS_V2_PRODUCT_ID
 
- USB_AUTHORIZE_ALL
 
- USB_AUTHORIZE_INTERNAL
 
- USB_AUTHORIZE_NONE
 
- USB_AUTHORIZE_WIRED
 
- USB_AUTOREQ_REG
 
- USB_AVAYA8_VENDOR_ID
 
- USB_AVAYAE_VENDOR_ID
 
- USB_AVAYA_WIRELESS_ID
 
- USB_BCMA_CLKCTLST_USB_CLK_REQ
 
- USB_BDRING_LEN
 
- USB_BDRING_LEN_RX
 
- USB_BDRING_LEN_TX
 
- USB_BESL_BASELINE_VALID
 
- USB_BESL_DEEP_VALID
 
- USB_BESL_SUPPORT
 
- USB_BLACKBIRD_SPRO_PRODUCT_ID
 
- USB_BLACKBIRD_V2_PRODUCT_ID
 
- USB_BMU_RESET
 
- USB_BP2_EN
 
- USB_BP_0
 
- USB_BP_1
 
- USB_BP_10
 
- USB_BP_11
 
- USB_BP_12
 
- USB_BP_13
 
- USB_BP_14
 
- USB_BP_15
 
- USB_BP_2
 
- USB_BP_3
 
- USB_BP_4
 
- USB_BP_5
 
- USB_BP_6
 
- USB_BP_7
 
- USB_BP_8
 
- USB_BP_9
 
- USB_BP_BA
 
- USB_BP_EN
 
- USB_BRCM_FAMILY
 
- USB_BUFFALO_L11G_ID
 
- USB_BUFFALO_L11G_WR_ID
 
- USB_BUFFALO_L11_ID
 
- USB_BUFSIZE
 
- USB_BUF_SZ
 
- USB_BULK
 
- USB_BURST_SIZE
 
- USB_BUS
 
- USB_BUSMODE_BE
 
- USB_BUSMODE_BO_MASK
 
- USB_BUSMODE_BO_SHIFT
 
- USB_BUSMODE_CETM
 
- USB_BUSMODE_DTB
 
- USB_BUSMODE_GBL
 
- USB_BUS_ADD
 
- USB_BUS_POWER
 
- USB_BUS_REMOVE
 
- USB_C2H_CMDID_OFFSET
 
- USB_C2H_EVENT_OFFSET
 
- USB_C2H_SEQ_OFFSET
 
- USB_CANDLELIGHT_PRODUCT_ID
 
- USB_CANDLELIGHT_VENDOR_ID
 
- USB_CANUSB2_PRODUCT_ID
 
- USB_CANUSBM_PRODUCT_ID
 
- USB_CAN_R_PRODUCT_ID
 
- USB_CAP
 
- USB_CAP1_DMA_TYPE_MASK
 
- USB_CAP1_DMA_WIDTH_MASK
 
- USB_CAP1_OTG_READY
 
- USB_CAP1_SFR_TYPE_MASK
 
- USB_CAP1_SFR_WIDTH_MASK
 
- USB_CAP1_TDL_FROM_TRB
 
- USB_CAP1_U2PHY_EN
 
- USB_CAP1_U3PHY_TYPE_MASK
 
- USB_CAP1_U3PHY_WIDTH_MASK
 
- USB_CAP2_ACTUAL_MEM_SIZE
 
- USB_CAP2_MAX_MEM_SIZE
 
- USB_CAPTURE_RUNNING
 
- USB_CAP_TYPE_EXT
 
- USB_CAP_TYPE_WIRELESS_USB
 
- USB_CAUSE
 
- USB_CDC_1_5_STOP_BITS
 
- USB_CDC_1_STOP_BITS
 
- USB_CDC_2_STOP_BITS
 
- USB_CDC_ACM_PROTO_AT_3G
 
- USB_CDC_ACM_PROTO_AT_CDMA
 
- USB_CDC_ACM_PROTO_AT_GSM
 
- USB_CDC_ACM_PROTO_AT_PCCA101
 
- USB_CDC_ACM_PROTO_AT_PCCA101_WAKE
 
- USB_CDC_ACM_PROTO_AT_V25TER
 
- USB_CDC_ACM_PROTO_VENDOR
 
- USB_CDC_ACM_TYPE
 
- USB_CDC_CALL_MANAGEMENT_TYPE
 
- USB_CDC_CALL_MGMT_CAP_CALL_MGMT
 
- USB_CDC_CALL_MGMT_CAP_DATA_INTF
 
- USB_CDC_CAP_BRK
 
- USB_CDC_CAP_LINE
 
- USB_CDC_CAP_NOTIFY
 
- USB_CDC_COMM_FEATURE
 
- USB_CDC_COUNTRY_TYPE
 
- USB_CDC_DMM_TYPE
 
- USB_CDC_ETHERNET_TYPE
 
- USB_CDC_EVEN_PARITY
 
- USB_CDC_GET_CRC_MODE
 
- USB_CDC_GET_ENCAPSULATED_RESPONSE
 
- USB_CDC_GET_ETHERNET_PM_PATTERN_FILTER
 
- USB_CDC_GET_ETHERNET_STATISTIC
 
- USB_CDC_GET_MAX_DATAGRAM_SIZE
 
- USB_CDC_GET_NET_ADDRESS
 
- USB_CDC_GET_NTB_FORMAT
 
- USB_CDC_GET_NTB_INPUT_SIZE
 
- USB_CDC_GET_NTB_PARAMETERS
 
- USB_CDC_HEADER_TYPE
 
- USB_CDC_MARK_PARITY
 
- USB_CDC_MBIM_EXTENDED_TYPE
 
- USB_CDC_MBIM_NDP16_DSS_SIGN
 
- USB_CDC_MBIM_NDP16_IPS_SIGN
 
- USB_CDC_MBIM_NDP32_DSS_SIGN
 
- USB_CDC_MBIM_NDP32_IPS_SIGN
 
- USB_CDC_MBIM_PROTO_NTB
 
- USB_CDC_MBIM_TYPE
 
- USB_CDC_MDLM_DETAIL_TYPE
 
- USB_CDC_MDLM_TYPE
 
- USB_CDC_NCM_CRC_APPENDED
 
- USB_CDC_NCM_CRC_NOT_APPENDED
 
- USB_CDC_NCM_DATAGRAM_FORMAT_CRC
 
- USB_CDC_NCM_DATAGRAM_FORMAT_NOCRC
 
- USB_CDC_NCM_NCAP_CRC_MODE
 
- USB_CDC_NCM_NCAP_ENCAP_COMMAND
 
- USB_CDC_NCM_NCAP_ETH_FILTER
 
- USB_CDC_NCM_NCAP_MAX_DATAGRAM_SIZE
 
- USB_CDC_NCM_NCAP_NET_ADDRESS
 
- USB_CDC_NCM_NCAP_NTB_INPUT_SIZE
 
- USB_CDC_NCM_NDP16_CRC_SIGN
 
- USB_CDC_NCM_NDP16_INDEX_MIN
 
- USB_CDC_NCM_NDP16_LENGTH_MIN
 
- USB_CDC_NCM_NDP16_NOCRC_SIGN
 
- USB_CDC_NCM_NDP32_CRC_SIGN
 
- USB_CDC_NCM_NDP32_INDEX_MIN
 
- USB_CDC_NCM_NDP32_NOCRC_SIGN
 
- USB_CDC_NCM_NDP_ALIGN_MIN_SIZE
 
- USB_CDC_NCM_NTB16_FORMAT
 
- USB_CDC_NCM_NTB16_SUPPORTED
 
- USB_CDC_NCM_NTB32_FORMAT
 
- USB_CDC_NCM_NTB32_SUPPORTED
 
- USB_CDC_NCM_NTB_MAX_LENGTH
 
- USB_CDC_NCM_NTB_MIN_IN_SIZE
 
- USB_CDC_NCM_NTB_MIN_OUT_SIZE
 
- USB_CDC_NCM_NTH16_SIGN
 
- USB_CDC_NCM_NTH32_SIGN
 
- USB_CDC_NCM_PROTO_CODE_EXTERN_PROTO
 
- USB_CDC_NCM_PROTO_CODE_NO_ENCAP_COMMANDS
 
- USB_CDC_NCM_PROTO_NTB
 
- USB_CDC_NCM_TYPE
 
- USB_CDC_NETWORK_TERMINAL_TYPE
 
- USB_CDC_NOTIFY_NETWORK_CONNECTION
 
- USB_CDC_NOTIFY_RESPONSE_AVAILABLE
 
- USB_CDC_NOTIFY_SERIAL_STATE
 
- USB_CDC_NOTIFY_SPEED_CHANGE
 
- USB_CDC_NO_PARITY
 
- USB_CDC_OBEX_TYPE
 
- USB_CDC_ODD_PARITY
 
- USB_CDC_PACKET_TYPE_ALL_MULTICAST
 
- USB_CDC_PACKET_TYPE_BROADCAST
 
- USB_CDC_PACKET_TYPE_DIRECTED
 
- USB_CDC_PACKET_TYPE_MULTICAST
 
- USB_CDC_PACKET_TYPE_PROMISCUOUS
 
- USB_CDC_PHONET_TYPE
 
- USB_CDC_PROTO_EEM
 
- USB_CDC_PROTO_NONE
 
- USB_CDC_REQ_GET_LINE_CODING
 
- USB_CDC_REQ_SEND_BREAK
 
- USB_CDC_REQ_SET_CONTROL_LINE_STATE
 
- USB_CDC_REQ_SET_LINE_CODING
 
- USB_CDC_SEND_ENCAPSULATED_COMMAND
 
- USB_CDC_SET_CRC_MODE
 
- USB_CDC_SET_ETHERNET_MULTICAST_FILTERS
 
- USB_CDC_SET_ETHERNET_PACKET_FILTER
 
- USB_CDC_SET_ETHERNET_PM_PATTERN_FILTER
 
- USB_CDC_SET_MAX_DATAGRAM_SIZE
 
- USB_CDC_SET_NET_ADDRESS
 
- USB_CDC_SET_NTB_FORMAT
 
- USB_CDC_SET_NTB_INPUT_SIZE
 
- USB_CDC_SPACE_PARITY
 
- USB_CDC_SUBCLASS_ACM
 
- USB_CDC_SUBCLASS_DMM
 
- USB_CDC_SUBCLASS_EEM
 
- USB_CDC_SUBCLASS_ETHERNET
 
- USB_CDC_SUBCLASS_MBIM
 
- USB_CDC_SUBCLASS_MDLM
 
- USB_CDC_SUBCLASS_NCM
 
- USB_CDC_SUBCLASS_OBEX
 
- USB_CDC_SUBCLASS_PHONET
 
- USB_CDC_SUBCLASS_WHCM
 
- USB_CDC_UNION_TYPE
 
- USB_CDC_WHCM_TYPE
 
- USB_CFG0
 
- USB_CFG1
 
- USB_CFG1_DEV_U1_EN_
 
- USB_CFG1_DEV_U1_INIT_EN_
 
- USB_CFG1_DEV_U2_EN_
 
- USB_CFG1_DEV_U2_INIT_EN_
 
- USB_CFG1_FS_TOUT_CAL_MASK_
 
- USB_CFG1_HS_TOUT_CAL_MASK_
 
- USB_CFG1_LTM_ENABLE_
 
- USB_CFG1_SCALE_DOWN_MASK_
 
- USB_CFG1_SCALE_DOWN_MODE0_
 
- USB_CFG1_SCALE_DOWN_MODE1_
 
- USB_CFG1_SCALE_DOWN_MODE2_
 
- USB_CFG1_SCALE_DOWN_MODE3_
 
- USB_CFG1_U1_TIMEOUT_MASK_
 
- USB_CFG1_U2_TIMEOUT_MASK_
 
- USB_CFG2
 
- USB_CFG2_HS_DETACH_TIME_MASK_
 
- USB_CFG2_SS_DETACH_TIME_MASK_
 
- USB_CFG3
 
- USB_CFG3_BULK_OUT_NUMP_OVR_
 
- USB_CFG3_DELAY_P1P2P3_
 
- USB_CFG3_DELAY_PHY_PWR_CHG_
 
- USB_CFG3_DIS_FAST_U1_EXIT_
 
- USB_CFG3_DIS_SCRAMB_
 
- USB_CFG3_EN_U2_LTM_
 
- USB_CFG3_HST_PRT_CMPL_
 
- USB_CFG3_LFPS_FILT_
 
- USB_CFG3_LPM_NYET_THR_
 
- USB_CFG3_PWR_DN_SCALE_
 
- USB_CFG3_REQ_P1P2P3
 
- USB_CFG3_RX_DET_2_POL_LFPS_
 
- USB_CFG3_SKIP_RX_DET_
 
- USB_CFG3_U1U2_EXIT_FR_
 
- USB_CFG_BCE_
 
- USB_CFG_BIR_
 
- USB_CFG_HIRD_THR_135_
 
- USB_CFG_HIRD_THR_210_
 
- USB_CFG_HIRD_THR_285_
 
- USB_CFG_HIRD_THR_360_
 
- USB_CFG_HIRD_THR_435_
 
- USB_CFG_HIRD_THR_510_
 
- USB_CFG_HIRD_THR_585_
 
- USB_CFG_HIRD_THR_60_
 
- USB_CFG_HIRD_THR_660_
 
- USB_CFG_HIRD_THR_735_
 
- USB_CFG_HIRD_THR_810_
 
- USB_CFG_HIRD_THR_885_
 
- USB_CFG_HIRD_THR_960_
 
- USB_CFG_HIRD_THR_MASK_
 
- USB_CFG_LPM_CAPABILITY_
 
- USB_CFG_LPM_ENBL_SLPM_
 
- USB_CFG_LPM_EN_
 
- USB_CFG_LPM_RESPONSE_
 
- USB_CFG_MAX_BURST_BI_MASK_
 
- USB_CFG_MAX_BURST_BO_MASK_
 
- USB_CFG_MAX_DEV_SPEED_FS_
 
- USB_CFG_MAX_DEV_SPEED_HS_
 
- USB_CFG_MAX_DEV_SPEED_MASK_
 
- USB_CFG_MAX_DEV_SPEED_SS_
 
- USB_CFG_PHY_BOOST_MASK_
 
- USB_CFG_PHY_BOOST_NORMAL_
 
- USB_CFG_PHY_BOOST_PLUS_12_
 
- USB_CFG_PHY_BOOST_PLUS_4_
 
- USB_CFG_PHY_BOOST_PLUS_8_
 
- USB_CFG_PORT_SWAP_
 
- USB_CFG_PWR_SEL_
 
- USB_CFG_RMT_WKP_
 
- USB_CFG_STALL_BO_DIS_
 
- USB_CHAOSKEY_MINOR_BASE
 
- USB_CHARGER_ABSENT
 
- USB_CHARGER_C
 
- USB_CHARGER_DEFAULT
 
- USB_CHARGER_PRESENT
 
- USB_CHAR_MAJOR
 
- USB_CHG
 
- USB_CHG_NO_OVERSHOOT_ENA_N
 
- USB_CHG_STATE_DCD_DONE
 
- USB_CHG_STATE_DETECTED
 
- USB_CHG_STATE_PRIMARY_DONE
 
- USB_CHG_STATE_SECONDARY_DONE
 
- USB_CHG_STATE_UNDEFINED
 
- USB_CHG_STATE_WAIT_FOR_DCD
 
- USB_CHG_TYPE_BC12_CDP
 
- USB_CHG_TYPE_BC12_DCP
 
- USB_CHG_TYPE_BC12_SDP
 
- USB_CHG_TYPE_C
 
- USB_CHG_TYPE_DEDICATED
 
- USB_CHG_TYPE_NONE
 
- USB_CHG_TYPE_OTHER
 
- USB_CHG_TYPE_PD
 
- USB_CHG_TYPE_PROPRIETARY
 
- USB_CHG_TYPE_UNKNOWN
 
- USB_CHG_TYPE_VBUS
 
- USB_CH_CV_ON
 
- USB_CH_DET
 
- USB_CH_ENA
 
- USB_CH_IP_CUR_LVL_0P05
 
- USB_CH_IP_CUR_LVL_0P09
 
- USB_CH_IP_CUR_LVL_0P19
 
- USB_CH_IP_CUR_LVL_0P29
 
- USB_CH_IP_CUR_LVL_0P38
 
- USB_CH_IP_CUR_LVL_0P45
 
- USB_CH_IP_CUR_LVL_0P5
 
- USB_CH_IP_CUR_LVL_0P6
 
- USB_CH_IP_CUR_LVL_0P7
 
- USB_CH_IP_CUR_LVL_0P8
 
- USB_CH_IP_CUR_LVL_0P9
 
- USB_CH_IP_CUR_LVL_1P0
 
- USB_CH_IP_CUR_LVL_1P1
 
- USB_CH_IP_CUR_LVL_1P3
 
- USB_CH_IP_CUR_LVL_1P4
 
- USB_CH_IP_CUR_LVL_1P5
 
- USB_CH_TH_PROT
 
- USB_CH_VBUSDETDBNC
 
- USB_CH_VBUSDROP
 
- USB_CLASS_APP_SPEC
 
- USB_CLASS_AUDIO
 
- USB_CLASS_CDC_DATA
 
- USB_CLASS_COMM
 
- USB_CLASS_CONTENT_SEC
 
- USB_CLASS_CSCID
 
- USB_CLASS_HID
 
- USB_CLASS_HUB
 
- USB_CLASS_MASS_STORAGE
 
- USB_CLASS_MISC
 
- USB_CLASS_PER_INTERFACE
 
- USB_CLASS_PHYSICAL
 
- USB_CLASS_PRINTER
 
- USB_CLASS_STILL_IMAGE
 
- USB_CLASS_VENDOR_SPEC
 
- USB_CLASS_VIDEO
 
- USB_CLASS_WIRELESS_CONTROLLER
 
- USB_CLOCK
 
- USB_CLOCK_TYPE_CRYSTAL_12
 
- USB_CLOCK_TYPE_REF_12
 
- USB_CLOCK_TYPE_REF_24
 
- USB_CLOCK_TYPE_REF_48
 
- USB_CMD
 
- USB_CMD_ASP
 
- USB_CMD_ASP_00
 
- USB_CMD_ASP_01
 
- USB_CMD_ASP_10
 
- USB_CMD_ASP_11
 
- USB_CMD_ASP_BIT_POS
 
- USB_CMD_ASYNC_SCHEDULE_EN
 
- USB_CMD_ASYNC_SCH_PARK_EN
 
- USB_CMD_ATDTW
 
- USB_CMD_CTRL_RESET
 
- USB_CMD_DNFW_INT_MASK
 
- USB_CMD_DNLTM_BELT_MASK
 
- USB_CMD_DSFT
 
- USB_CMD_EP_MASK
 
- USB_CMD_FADDR
 
- USB_CMD_FADDR_MASK
 
- USB_CMD_FLUSH_FIFO
 
- USB_CMD_FRAME_SIZE_1024
 
- USB_CMD_FRAME_SIZE_128
 
- USB_CMD_FRAME_SIZE_16
 
- USB_CMD_FRAME_SIZE_256
 
- USB_CMD_FRAME_SIZE_32
 
- USB_CMD_FRAME_SIZE_512
 
- USB_CMD_FRAME_SIZE_64
 
- USB_CMD_FRAME_SIZE_8
 
- USB_CMD_INT_AA_DOORBELL
 
- USB_CMD_ISFT
 
- USB_CMD_ITC
 
- USB_CMD_ITC_16_MICRO_FRM
 
- USB_CMD_ITC_1_MICRO_FRM
 
- USB_CMD_ITC_2_MICRO_FRM
 
- USB_CMD_ITC_32_MICRO_FRM
 
- USB_CMD_ITC_4_MICRO_FRM
 
- USB_CMD_ITC_64_MICRO_FRM
 
- USB_CMD_ITC_8_MICRO_FRM
 
- USB_CMD_ITC_BIT_POS
 
- USB_CMD_ITC_NO_THRESHOLD
 
- USB_CMD_PERIODIC_SCHEDULE_EN
 
- USB_CMD_RESET
 
- USB_CMD_RUN
 
- USB_CMD_RUN_STOP
 
- USB_CMD_SDNFW
 
- USB_CMD_SDNLTM
 
- USB_CMD_SET_ADDR
 
- USB_CMD_SPKT
 
- USB_CMD_STMODE
 
- USB_CMD_STR_FIFO
 
- USB_CMD_SUTW
 
- USB_CNTTEST
 
- USB_COMMAND_TIMEOUT
 
- USB_COMPAQ_VENDOR_ID
 
- USB_COMPAQ_W200_ID
 
- USB_COMPAQ_WL215_ID
 
- USB_COMPLETE
 
- USB_COMP_EP0_BUFSIZ
 
- USB_COMP_EP0_OS_DESC_BUFSIZ
 
- USB_COM_CON_CONF
 
- USB_COM_CON_DEV_ADDR
 
- USB_COM_CON_DEV_ADDR_MASK
 
- USB_COM_CON_DEV_ADDR_SHIFT
 
- USB_COM_CON_EP0_EN
 
- USB_COM_CON_PIPE_CLR
 
- USB_COM_CON_PN_LSTTR_PP
 
- USB_COM_CON_PN_RDATAIF_NL
 
- USB_COM_CON_PN_WDATAIF_NL
 
- USB_COM_CON_RX_DETECTION
 
- USB_COM_CON_SPD_MODE
 
- USB_CONF2_DIS_TDL_TRB
 
- USB_CONF2_EN_TDL_TRB
 
- USB_CONFIG
 
- USB_CONFIG_ATT_BATTERY
 
- USB_CONFIG_ATT_ONE
 
- USB_CONFIG_ATT_SELFPOWER
 
- USB_CONFIG_ATT_WAKEUP
 
- USB_CONFIG_BASE
 
- USB_CONFIG_STRINGS_LANG
 
- USB_CONFIG_STRING_RW_OPS
 
- USB_CONF_BENDIAN
 
- USB_CONF_CFGRST
 
- USB_CONF_CFGSET
 
- USB_CONF_CFORCE_FS
 
- USB_CONF_CLK2OFFDS
 
- USB_CONF_CLK2OFFEN
 
- USB_CONF_CLK3OFFDS
 
- USB_CONF_CLK3OFFEN
 
- USB_CONF_DEVDS
 
- USB_CONF_DEVEN
 
- USB_CONF_DMAOFFDS
 
- USB_CONF_DMAOFFEN
 
- USB_CONF_DMULT
 
- USB_CONF_DSING
 
- USB_CONF_L1DS
 
- USB_CONF_L1EN
 
- USB_CONF_LENDIAN
 
- USB_CONF_LGO_L0
 
- USB_CONF_LGO_SSINACT
 
- USB_CONF_LGO_U0
 
- USB_CONF_LGO_U1
 
- USB_CONF_LGO_U2
 
- USB_CONF_SFORCE_FS
 
- USB_CONF_SWRST
 
- USB_CONF_U1DS
 
- USB_CONF_U1EN
 
- USB_CONF_U2DS
 
- USB_CONF_U2EN
 
- USB_CONF_USB2DIS
 
- USB_CONF_USB3DIS
 
- USB_CONNECT_TIMER
 
- USB_CONN_IRQF
 
- USB_CONTROLLER_RESET
 
- USB_CPCUSB_ARM7_PRODUCT_ID
 
- USB_CPCUSB_VENDOR_ID
 
- USB_CRC_SIZE
 
- USB_CSR_DUMMY1
 
- USB_CSR_DUMMY2
 
- USB_CTLR_MODE_DEVICE
 
- USB_CTLR_MODE_DRD
 
- USB_CTLR_MODE_HOST
 
- USB_CTLR_MODE_TYPEC_PD
 
- USB_CTL_0
 
- USB_CTL_REG
 
- USB_CTL_WAIT
 
- USB_CTRL
 
- USB_CTRL_AUTOREQ
 
- USB_CTRL_EBRIDGE
 
- USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK
 
- USB_CTRL_FIFO_THRESH
 
- USB_CTRL_GET_TIMEOUT
 
- USB_CTRL_INTERRUPT_EN
 
- USB_CTRL_IOENB
 
- USB_CTRL_MASK
 
- USB_CTRL_MASK_FAMILY
 
- USB_CTRL_MDIO
 
- USB_CTRL_MDIO2
 
- USB_CTRL_MODE_STREAM_DISABLE
 
- USB_CTRL_MSG_SZ
 
- USB_CTRL_OBRIDGE
 
- USB_CTRL_OBRIDGE_LS_KEEP_ALIVE_MASK
 
- USB_CTRL_PLL_CTL
 
- USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK
 
- USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SELECTOR
 
- USB_CTRL_PLL_CTL_PLL_RESETB_MASK
 
- USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK
 
- USB_CTRL_REG
 
- USB_CTRL_RX_MODE
 
- USB_CTRL_SELECTOR_COUNT
 
- USB_CTRL_SET
 
- USB_CTRL_SETUP
 
- USB_CTRL_SETUP_BABO_MASK
 
- USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_MASK
 
- USB_CTRL_SETUP_CC_DRD_MODE_ENABLE_SELECTOR
 
- USB_CTRL_SETUP_ENDIAN_BITS
 
- USB_CTRL_SETUP_ENDIAN_SELECTOR
 
- USB_CTRL_SETUP_FNBO_MASK
 
- USB_CTRL_SETUP_FNHW_MASK
 
- USB_CTRL_SETUP_IOC_MASK
 
- USB_CTRL_SETUP_IPP_MASK
 
- USB_CTRL_SETUP_OC3_DISABLE_MASK
 
- USB_CTRL_SETUP_OC3_DISABLE_SELECTOR
 
- USB_CTRL_SETUP_SCB1_EN_MASK
 
- USB_CTRL_SETUP_SCB1_EN_SELECTOR
 
- USB_CTRL_SETUP_SCB2_EN_MASK
 
- USB_CTRL_SETUP_SCB2_EN_SELECTOR
 
- USB_CTRL_SETUP_SCB_CLIENT_SWAP_MASK
 
- USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK
 
- USB_CTRL_SETUP_SS_EHCI64BIT_EN_SELECTOR
 
- USB_CTRL_SETUP_SS_EHCI64BIT_EN_VAR_MASK
 
- USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_MASK
 
- USB_CTRL_SETUP_STRAP_CC_DRD_MODE_ENABLE_SEL_SELECTOR
 
- USB_CTRL_SETUP_STRAP_IPP_SEL_MASK
 
- USB_CTRL_SETUP_STRAP_IPP_SEL_SELECTOR
 
- USB_CTRL_SETUP_WABO_MASK
 
- USB_CTRL_SET_FAMILY
 
- USB_CTRL_SET_TIMEOUT
 
- USB_CTRL_TX_MODE
 
- USB_CTRL_ULPI_INT0EN
 
- USB_CTRL_ULPI_PHY_CLK_SEL
 
- USB_CTRL_UNSET
 
- USB_CTRL_UNSET_FAMILY
 
- USB_CTRL_USB30_CTL1
 
- USB_CTRL_USB30_CTL1_PHY3_PLL_SEQ_START_MASK
 
- USB_CTRL_USB30_CTL1_PHY3_RESETB_MASK
 
- USB_CTRL_USB30_CTL1_USB3_IOC_MASK
 
- USB_CTRL_USB30_CTL1_USB3_IOC_SELECTOR
 
- USB_CTRL_USB30_CTL1_USB3_IPP_MASK
 
- USB_CTRL_USB30_CTL1_USB3_IPP_SELECTOR
 
- USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_MASK
 
- USB_CTRL_USB30_CTL1_XHC_SOFT_RESETB_SELECTOR
 
- USB_CTRL_USB30_PCTL
 
- USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_MASK
 
- USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_MASK
 
- USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_MASK
 
- USB_CTRL_USB_DEVICE_CTL1
 
- USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_MASK
 
- USB_CTRL_USB_DEVICE_CTL1_PORT_MODE_SELECTOR
 
- USB_CTRL_USB_EN
 
- USB_CTRL_USB_PM
 
- USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK
 
- USB_CTRL_USB_PM_BDC_SOFT_RESETB_SELECTOR
 
- USB_CTRL_USB_PM_SOFT_RESET_MASK
 
- USB_CTRL_USB_PM_SOFT_RESET_SELECTOR
 
- USB_CTRL_USB_PM_USB20_HC_RESETB_MASK
 
- USB_CTRL_USB_PM_USB20_HC_RESETB_SELECTOR
 
- USB_CTRL_USB_PM_USB20_HC_RESETB_VAR_MASK
 
- USB_CTRL_USB_PM_USB_PWRDN_MASK
 
- USB_CTRL_USB_PM_USB_PWRDN_SELECTOR
 
- USB_CTRL_USB_PM_XHC_SOFT_RESETB_MASK
 
- USB_CTRL_USB_PM_XHC_SOFT_RESETB_SELECTOR
 
- USB_CTRL_USB_PM_XHC_SOFT_RESETB_VAR_MASK
 
- USB_CTRL_UTMI_CTL_1
 
- USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_MASK
 
- USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_MASK
 
- USB_CTRL_UTMI_PHY_EN
 
- USB_CUR_DELAY
 
- USB_CUR_STEP
 
- USB_DBGIDX
 
- USB_DBGMUX
 
- USB_DEBUG_BRK_SIZE
 
- USB_DEBUG_DEVNUM
 
- USB_DEBUG_MAX_PACKET_SIZE
 
- USB_DEDICATED_CHG
 
- USB_DEFAULT_BESL_UNSPECIFIED
 
- USB_DEFAULT_U1_DEV_EXIT_LAT
 
- USB_DEFAULT_U2_DEV_EXIT_LAT
 
- USB_DESC_BUFSIZE
 
- USB_DETECT_ENABLE
 
- USB_DEVADDR
 
- USB_DEVICE
 
- USB_DEVICE_ADD
 
- USB_DEVICE_ADDRESS_BIT_POS
 
- USB_DEVICE_ADDRESS_BIT_SHIFT
 
- USB_DEVICE_ADDRESS_MASK
 
- USB_DEVICE_AND_INTERFACE_INFO
 
- USB_DEVICE_AUTHORIZE_ALL
 
- USB_DEVICE_AUTHORIZE_INTERNAL
 
- USB_DEVICE_AUTHORIZE_NONE
 
- USB_DEVICE_A_ALT_HNP_SUPPORT
 
- USB_DEVICE_A_HNP_SUPPORT
 
- USB_DEVICE_BATTERY
 
- USB_DEVICE_BATTERY_WAKE_MASK
 
- USB_DEVICE_B_HNP_ENABLE
 
- USB_DEVICE_CDC_DATA
 
- USB_DEVICE_CHARGING_POLICY
 
- USB_DEVICE_CLASS
 
- USB_DEVICE_DATA
 
- USB_DEVICE_DEBUG_MODE
 
- USB_DEVICE_DEV
 
- USB_DEVICE_FIXED
 
- USB_DEVICE_HID_CLASS
 
- USB_DEVICE_ID_258A_6A88
 
- USB_DEVICE_ID_302
 
- USB_DEVICE_ID_3M1968
 
- USB_DEVICE_ID_3M2256
 
- USB_DEVICE_ID_3M3266
 
- USB_DEVICE_ID_A4TECH_RP_649
 
- USB_DEVICE_ID_A4TECH_WCP32PU
 
- USB_DEVICE_ID_A4TECH_X5_005D
 
- USB_DEVICE_ID_AASHIMA_GAMEPAD
 
- USB_DEVICE_ID_AASHIMA_PREDATOR
 
- USB_DEVICE_ID_ACECAD_302
 
- USB_DEVICE_ID_ACECAD_FLAIR
 
- USB_DEVICE_ID_ACTIONSTAR_1011
 
- USB_DEVICE_ID_ADS_TECH_RADIO_SI470X
 
- USB_DEVICE_ID_AFATECH_AF9016
 
- USB_DEVICE_ID_AIPTEK_01
 
- USB_DEVICE_ID_AIPTEK_10
 
- USB_DEVICE_ID_AIPTEK_20
 
- USB_DEVICE_ID_AIPTEK_21
 
- USB_DEVICE_ID_AIPTEK_22
 
- USB_DEVICE_ID_AIPTEK_23
 
- USB_DEVICE_ID_AIPTEK_24
 
- USB_DEVICE_ID_AIRCABLE1
 
- USB_DEVICE_ID_AIREN_SLIMPLUS
 
- USB_DEVICE_ID_AKAI_09E8_MIDIMIX
 
- USB_DEVICE_ID_AKAI_MPKMINI2
 
- USB_DEVICE_ID_ALCOR_MALTRON_KB
 
- USB_DEVICE_ID_ALCOR_USBRS232
 
- USB_DEVICE_ID_AMI_VIRT_KEYBOARD_AND_MOUSE
 
- USB_DEVICE_ID_ANTON_TOUCH_PAD
 
- USB_DEVICE_ID_APPLE_ALU_ANSI
 
- USB_DEVICE_ID_APPLE_ALU_ISO
 
- USB_DEVICE_ID_APPLE_ALU_JIS
 
- USB_DEVICE_ID_APPLE_ALU_MINI_ANSI
 
- USB_DEVICE_ID_APPLE_ALU_MINI_ISO
 
- USB_DEVICE_ID_APPLE_ALU_MINI_JIS
 
- USB_DEVICE_ID_APPLE_ALU_REVB_ANSI
 
- USB_DEVICE_ID_APPLE_ALU_REVB_ISO
 
- USB_DEVICE_ID_APPLE_ALU_REVB_JIS
 
- USB_DEVICE_ID_APPLE_ALU_WIRELESS_2009_ANSI
 
- USB_DEVICE_ID_APPLE_ALU_WIRELESS_2009_ISO
 
- USB_DEVICE_ID_APPLE_ALU_WIRELESS_2009_JIS
 
- USB_DEVICE_ID_APPLE_ALU_WIRELESS_2011_ANSI
 
- USB_DEVICE_ID_APPLE_ALU_WIRELESS_2011_ISO
 
- USB_DEVICE_ID_APPLE_ALU_WIRELESS_2011_JIS
 
- USB_DEVICE_ID_APPLE_ALU_WIRELESS_ANSI
 
- USB_DEVICE_ID_APPLE_ALU_WIRELESS_ISO
 
- USB_DEVICE_ID_APPLE_ALU_WIRELESS_JIS
 
- USB_DEVICE_ID_APPLE_FOUNTAIN_ANSI
 
- USB_DEVICE_ID_APPLE_FOUNTAIN_ISO
 
- USB_DEVICE_ID_APPLE_FOUNTAIN_TP_ONLY
 
- USB_DEVICE_ID_APPLE_GEYSER1_TP_ONLY
 
- USB_DEVICE_ID_APPLE_GEYSER3_ANSI
 
- USB_DEVICE_ID_APPLE_GEYSER3_ISO
 
- USB_DEVICE_ID_APPLE_GEYSER3_JIS
 
- USB_DEVICE_ID_APPLE_GEYSER4_ANSI
 
- USB_DEVICE_ID_APPLE_GEYSER4_HF_ANSI
 
- USB_DEVICE_ID_APPLE_GEYSER4_HF_ISO
 
- USB_DEVICE_ID_APPLE_GEYSER4_HF_JIS
 
- USB_DEVICE_ID_APPLE_GEYSER4_ISO
 
- USB_DEVICE_ID_APPLE_GEYSER4_JIS
 
- USB_DEVICE_ID_APPLE_GEYSER_ANSI
 
- USB_DEVICE_ID_APPLE_GEYSER_ISO
 
- USB_DEVICE_ID_APPLE_GEYSER_JIS
 
- USB_DEVICE_ID_APPLE_IRCONTROL
 
- USB_DEVICE_ID_APPLE_IRCONTROL2
 
- USB_DEVICE_ID_APPLE_IRCONTROL3
 
- USB_DEVICE_ID_APPLE_IRCONTROL4
 
- USB_DEVICE_ID_APPLE_IRCONTROL5
 
- USB_DEVICE_ID_APPLE_MAGICMOUSE
 
- USB_DEVICE_ID_APPLE_MAGICTRACKPAD
 
- USB_DEVICE_ID_APPLE_MAGICTRACKPAD2
 
- USB_DEVICE_ID_APPLE_MAGIC_KEYBOARD_ANSI
 
- USB_DEVICE_ID_APPLE_MAGIC_KEYBOARD_NUMPAD_ANSI
 
- USB_DEVICE_ID_APPLE_MIGHTYMOUSE
 
- USB_DEVICE_ID_APPLE_WELLSPRING2_ANSI
 
- USB_DEVICE_ID_APPLE_WELLSPRING2_ISO
 
- USB_DEVICE_ID_APPLE_WELLSPRING2_JIS
 
- USB_DEVICE_ID_APPLE_WELLSPRING3_ANSI
 
- USB_DEVICE_ID_APPLE_WELLSPRING3_ISO
 
- USB_DEVICE_ID_APPLE_WELLSPRING3_JIS
 
- USB_DEVICE_ID_APPLE_WELLSPRING4A_ANSI
 
- USB_DEVICE_ID_APPLE_WELLSPRING4A_ISO
 
- USB_DEVICE_ID_APPLE_WELLSPRING4A_JIS
 
- USB_DEVICE_ID_APPLE_WELLSPRING4_ANSI
 
- USB_DEVICE_ID_APPLE_WELLSPRING4_ISO
 
- USB_DEVICE_ID_APPLE_WELLSPRING4_JIS
 
- USB_DEVICE_ID_APPLE_WELLSPRING5A_ANSI
 
- USB_DEVICE_ID_APPLE_WELLSPRING5A_ISO
 
- USB_DEVICE_ID_APPLE_WELLSPRING5A_JIS
 
- USB_DEVICE_ID_APPLE_WELLSPRING5_ANSI
 
- USB_DEVICE_ID_APPLE_WELLSPRING5_ISO
 
- USB_DEVICE_ID_APPLE_WELLSPRING5_JIS
 
- USB_DEVICE_ID_APPLE_WELLSPRING6A_ANSI
 
- USB_DEVICE_ID_APPLE_WELLSPRING6A_ISO
 
- USB_DEVICE_ID_APPLE_WELLSPRING6A_JIS
 
- USB_DEVICE_ID_APPLE_WELLSPRING6_ANSI
 
- USB_DEVICE_ID_APPLE_WELLSPRING6_ISO
 
- USB_DEVICE_ID_APPLE_WELLSPRING6_JIS
 
- USB_DEVICE_ID_APPLE_WELLSPRING7A_ANSI
 
- USB_DEVICE_ID_APPLE_WELLSPRING7A_ISO
 
- USB_DEVICE_ID_APPLE_WELLSPRING7A_JIS
 
- USB_DEVICE_ID_APPLE_WELLSPRING7_ANSI
 
- USB_DEVICE_ID_APPLE_WELLSPRING7_ISO
 
- USB_DEVICE_ID_APPLE_WELLSPRING7_JIS
 
- USB_DEVICE_ID_APPLE_WELLSPRING8_ANSI
 
- USB_DEVICE_ID_APPLE_WELLSPRING8_ISO
 
- USB_DEVICE_ID_APPLE_WELLSPRING8_JIS
 
- USB_DEVICE_ID_APPLE_WELLSPRING9_ANSI
 
- USB_DEVICE_ID_APPLE_WELLSPRING9_ISO
 
- USB_DEVICE_ID_APPLE_WELLSPRING9_JIS
 
- USB_DEVICE_ID_APPLE_WELLSPRING_ANSI
 
- USB_DEVICE_ID_APPLE_WELLSPRING_ISO
 
- USB_DEVICE_ID_APPLE_WELLSPRING_JIS
 
- USB_DEVICE_ID_ASUSTEK_FX503VD_KEYBOARD
 
- USB_DEVICE_ID_ASUSTEK_I2C_KEYBOARD
 
- USB_DEVICE_ID_ASUSTEK_I2C_TOUCHPAD
 
- USB_DEVICE_ID_ASUSTEK_LCM
 
- USB_DEVICE_ID_ASUSTEK_LCM2
 
- USB_DEVICE_ID_ASUSTEK_MULTITOUCH_YFO
 
- USB_DEVICE_ID_ASUSTEK_ROG_KEYBOARD1
 
- USB_DEVICE_ID_ASUSTEK_ROG_KEYBOARD2
 
- USB_DEVICE_ID_ASUSTEK_ROG_KEYBOARD3
 
- USB_DEVICE_ID_ASUSTEK_T100CHI_KEYBOARD
 
- USB_DEVICE_ID_ASUSTEK_T100TAF_KEYBOARD
 
- USB_DEVICE_ID_ASUSTEK_T100TA_KEYBOARD
 
- USB_DEVICE_ID_ASUSTEK_T101HA_KEYBOARD
 
- USB_DEVICE_ID_ASUSTEK_T304_KEYBOARD
 
- USB_DEVICE_ID_ASUS_AK1D
 
- USB_DEVICE_ID_ASUS_MD_5110
 
- USB_DEVICE_ID_ASUS_MD_5112
 
- USB_DEVICE_ID_ASUS_T91MT
 
- USB_DEVICE_ID_ATEN_2PORTKVM
 
- USB_DEVICE_ID_ATEN_4PORTKVM
 
- USB_DEVICE_ID_ATEN_4PORTKVMC
 
- USB_DEVICE_ID_ATEN_CS124U
 
- USB_DEVICE_ID_ATEN_CS1758
 
- USB_DEVICE_ID_ATEN_CS682
 
- USB_DEVICE_ID_ATEN_CS692
 
- USB_DEVICE_ID_ATEN_UC100KM
 
- USB_DEVICE_ID_ATMEL_MULTITOUCH
 
- USB_DEVICE_ID_ATMEL_MXT_DIGITIZER
 
- USB_DEVICE_ID_ATMEL_V_USB
 
- USB_DEVICE_ID_AUREAL_W01RN
 
- USB_DEVICE_ID_AVER_FM_MR800
 
- USB_DEVICE_ID_AXENTIA_FM_RADIO
 
- USB_DEVICE_ID_BAANTO_MT_190W2
 
- USB_DEVICE_ID_BERKSHIRE_PCWD
 
- USB_DEVICE_ID_BIGBEN_PS3OFMINIPAD
 
- USB_DEVICE_ID_BLINK1
 
- USB_DEVICE_ID_BTC_8193
 
- USB_DEVICE_ID_BTC_EMPREX_REMOTE
 
- USB_DEVICE_ID_BTC_EMPREX_REMOTE_2
 
- USB_DEVICE_ID_CANDO_MULTI_TOUCH
 
- USB_DEVICE_ID_CANDO_MULTI_TOUCH_10_1
 
- USB_DEVICE_ID_CANDO_MULTI_TOUCH_11_6
 
- USB_DEVICE_ID_CANDO_MULTI_TOUCH_15_6
 
- USB_DEVICE_ID_CANDO_PIXCIR_MULTI_TOUCH
 
- USB_DEVICE_ID_CHERRY_CYMOTION
 
- USB_DEVICE_ID_CHERRY_CYMOTION_SOLAR
 
- USB_DEVICE_ID_CHICONY_ACER_SWITCH12
 
- USB_DEVICE_ID_CHICONY_MULTI_TOUCH
 
- USB_DEVICE_ID_CHICONY_PIXART_USB_OPTICAL_MOUSE
 
- USB_DEVICE_ID_CHICONY_PIXART_USB_OPTICAL_MOUSE2
 
- USB_DEVICE_ID_CHICONY_TACTICAL_PAD
 
- USB_DEVICE_ID_CHICONY_TOSHIBA_WT10A
 
- USB_DEVICE_ID_CHICONY_WIRELESS
 
- USB_DEVICE_ID_CHICONY_WIRELESS2
 
- USB_DEVICE_ID_CHIC_GAMEPAD
 
- USB_DEVICE_ID_CHUNGHWAT_MULTITOUCH
 
- USB_DEVICE_ID_CH_3AXIS_5BUTTON_STICK
 
- USB_DEVICE_ID_CH_AXIS_295
 
- USB_DEVICE_ID_CH_COMBATSTICK
 
- USB_DEVICE_ID_CH_FIGHTERSTICK
 
- USB_DEVICE_ID_CH_FLIGHT_SIM_ECLIPSE_YOKE
 
- USB_DEVICE_ID_CH_FLIGHT_SIM_YOKE
 
- USB_DEVICE_ID_CH_PRO_PEDALS
 
- USB_DEVICE_ID_CH_PRO_THROTTLE
 
- USB_DEVICE_ID_CJTOUCH_MULTI_TOUCH_0020
 
- USB_DEVICE_ID_CJTOUCH_MULTI_TOUCH_0040
 
- USB_DEVICE_ID_CM109
 
- USB_DEVICE_ID_CM6533
 
- USB_DEVICE_ID_CODEMERCS_IOW100
 
- USB_DEVICE_ID_CODEMERCS_IOW24
 
- USB_DEVICE_ID_CODEMERCS_IOW24SAG
 
- USB_DEVICE_ID_CODEMERCS_IOW28
 
- USB_DEVICE_ID_CODEMERCS_IOW28L
 
- USB_DEVICE_ID_CODEMERCS_IOW40
 
- USB_DEVICE_ID_CODEMERCS_IOW56
 
- USB_DEVICE_ID_CODEMERCS_IOW56AM
 
- USB_DEVICE_ID_CODEMERCS_IOWPV1
 
- USB_DEVICE_ID_CODEMERCS_IOWPV2
 
- USB_DEVICE_ID_CODEMERCS_IOW_FIRST
 
- USB_DEVICE_ID_CODEMERCS_IOW_LAST
 
- USB_DEVICE_ID_CORSAIR_GLAIVE_RGB
 
- USB_DEVICE_ID_CORSAIR_K65RGB
 
- USB_DEVICE_ID_CORSAIR_K65RGB_RAPIDFIRE
 
- USB_DEVICE_ID_CORSAIR_K70R
 
- USB_DEVICE_ID_CORSAIR_K70RGB
 
- USB_DEVICE_ID_CORSAIR_K70RGB_RAPIDFIRE
 
- USB_DEVICE_ID_CORSAIR_K90
 
- USB_DEVICE_ID_CORSAIR_K95RGB
 
- USB_DEVICE_ID_CORSAIR_M65RGB
 
- USB_DEVICE_ID_CORSAIR_SCIMITAR_PRO_RGB
 
- USB_DEVICE_ID_CORSAIR_STRAFE
 
- USB_DEVICE_ID_COUGAR_500K_GAMING_KEYBOARD
 
- USB_DEVICE_ID_COUGAR_700K_GAMING_KEYBOARD
 
- USB_DEVICE_ID_CREATIVE_SB0540
 
- USB_DEVICE_ID_CREATIVE_SB_OMNI_SURROUND_51
 
- USB_DEVICE_ID_CRYSTALTOUCH
 
- USB_DEVICE_ID_CRYSTALTOUCH_DUAL
 
- USB_DEVICE_ID_CVTOUCH_SCREEN
 
- USB_DEVICE_ID_CYGNAL_CP2112
 
- USB_DEVICE_ID_CYGNAL_RADIO_SI470X
 
- USB_DEVICE_ID_CYGNAL_RADIO_SI4713
 
- USB_DEVICE_ID_CYPRESS_BARCODE_1
 
- USB_DEVICE_ID_CYPRESS_BARCODE_2
 
- USB_DEVICE_ID_CYPRESS_BARCODE_3
 
- USB_DEVICE_ID_CYPRESS_BARCODE_4
 
- USB_DEVICE_ID_CYPRESS_HIDCOM
 
- USB_DEVICE_ID_CYPRESS_MOUSE
 
- USB_DEVICE_ID_CYPRESS_TRUETOUCH
 
- USB_DEVICE_ID_CYPRESS_ULTRAMOUSE
 
- USB_DEVICE_ID_DEALEXTREAME_RADIO_SI4701
 
- USB_DEVICE_ID_DELCOM_VISUAL_IND
 
- USB_DEVICE_ID_DELL_PIXART_USB_OPTICAL_MOUSE
 
- USB_DEVICE_ID_DELORME_EARTHMATE
 
- USB_DEVICE_ID_DELORME_EM_LT20
 
- USB_DEVICE_ID_DINOVO_DESKTOP
 
- USB_DEVICE_ID_DINOVO_EDGE
 
- USB_DEVICE_ID_DINOVO_MINI
 
- USB_DEVICE_ID_DIOLAN_U2C
 
- USB_DEVICE_ID_DISC_STAKKA
 
- USB_DEVICE_ID_DMI_ENC
 
- USB_DEVICE_ID_DRAGONRISE_DOLPHINBAR
 
- USB_DEVICE_ID_DRAGONRISE_GAMECUBE1
 
- USB_DEVICE_ID_DRAGONRISE_GAMECUBE2
 
- USB_DEVICE_ID_DRAGONRISE_PS3
 
- USB_DEVICE_ID_DRAGONRISE_WIIU
 
- USB_DEVICE_ID_DREAM_CHEEKY_FA
 
- USB_DEVICE_ID_DREAM_CHEEKY_WN
 
- USB_DEVICE_ID_DUAL_USB_JOYPAD
 
- USB_DEVICE_ID_DWAV_EGALAX_MULTITOUCH_480D
 
- USB_DEVICE_ID_DWAV_EGALAX_MULTITOUCH_480E
 
- USB_DEVICE_ID_DWAV_EGALAX_MULTITOUCH_7207
 
- USB_DEVICE_ID_DWAV_EGALAX_MULTITOUCH_720C
 
- USB_DEVICE_ID_DWAV_EGALAX_MULTITOUCH_7224
 
- USB_DEVICE_ID_DWAV_EGALAX_MULTITOUCH_722A
 
- USB_DEVICE_ID_DWAV_EGALAX_MULTITOUCH_725E
 
- USB_DEVICE_ID_DWAV_EGALAX_MULTITOUCH_7262
 
- USB_DEVICE_ID_DWAV_EGALAX_MULTITOUCH_726B
 
- USB_DEVICE_ID_DWAV_EGALAX_MULTITOUCH_72A1
 
- USB_DEVICE_ID_DWAV_EGALAX_MULTITOUCH_72AA
 
- USB_DEVICE_ID_DWAV_EGALAX_MULTITOUCH_72C4
 
- USB_DEVICE_ID_DWAV_EGALAX_MULTITOUCH_72D0
 
- USB_DEVICE_ID_DWAV_EGALAX_MULTITOUCH_72FA
 
- USB_DEVICE_ID_DWAV_EGALAX_MULTITOUCH_7302
 
- USB_DEVICE_ID_DWAV_EGALAX_MULTITOUCH_7349
 
- USB_DEVICE_ID_DWAV_EGALAX_MULTITOUCH_73F7
 
- USB_DEVICE_ID_DWAV_EGALAX_MULTITOUCH_A001
 
- USB_DEVICE_ID_DWAV_EGALAX_MULTITOUCH_C002
 
- USB_DEVICE_ID_DWAV_TOUCHCONTROLLER
 
- USB_DEVICE_ID_EGALAX_TOUCHCONTROLLER
 
- USB_DEVICE_ID_ELECOM_BM084
 
- USB_DEVICE_ID_ELECOM_M_DT1DRBK
 
- USB_DEVICE_ID_ELECOM_M_DT1URBK
 
- USB_DEVICE_ID_ELECOM_M_HT1DRBK
 
- USB_DEVICE_ID_ELECOM_M_HT1URBK
 
- USB_DEVICE_ID_ELECOM_M_XT3DRBK
 
- USB_DEVICE_ID_ELECOM_M_XT3URBK
 
- USB_DEVICE_ID_ELECOM_M_XT4DRBK
 
- USB_DEVICE_ID_ELITEGROUP_05D8
 
- USB_DEVICE_ID_ELO_ACCUTOUCH_2216
 
- USB_DEVICE_ID_ELO_TS2515
 
- USB_DEVICE_ID_ELO_TS2700
 
- USB_DEVICE_ID_EMS_TRIO_LINKER_PLUS_II
 
- USB_DEVICE_ID_ESSENTIAL_REALITY_P5
 
- USB_DEVICE_ID_ETURBOTOUCH
 
- USB_DEVICE_ID_ETURBOTOUCH_2968
 
- USB_DEVICE_ID_FLAIR
 
- USB_DEVICE_ID_FLIP_KVM
 
- USB_DEVICE_ID_FOCALTECH_FTXXXX_MULTITOUCH
 
- USB_DEVICE_ID_FORMOSA_IR_RECEIVER
 
- USB_DEVICE_ID_FREESCALE_MX28
 
- USB_DEVICE_ID_GAMERON_DUAL_PCS_ADAPTOR
 
- USB_DEVICE_ID_GAMERON_DUAL_PSX_ADAPTOR
 
- USB_DEVICE_ID_GAMETEL_MT_MODE
 
- USB_DEVICE_ID_GEMBIRD_JPD_DUALFORCE2
 
- USB_DEVICE_ID_GENERAL_TOUCH_WIN7_TWOFINGERS
 
- USB_DEVICE_ID_GENERAL_TOUCH_WIN8_PIT_0101
 
- USB_DEVICE_ID_GENERAL_TOUCH_WIN8_PIT_0102
 
- USB_DEVICE_ID_GENERAL_TOUCH_WIN8_PIT_0106
 
- USB_DEVICE_ID_GENERAL_TOUCH_WIN8_PIT_010A
 
- USB_DEVICE_ID_GENERAL_TOUCH_WIN8_PIT_E100
 
- USB_DEVICE_ID_GENERAL_TOUCH_WIN8_PWT_TENFINGERS
 
- USB_DEVICE_ID_GENIUS_GILA_GAMING_MOUSE
 
- USB_DEVICE_ID_GENIUS_GX_IMPERATOR
 
- USB_DEVICE_ID_GENIUS_KB29E
 
- USB_DEVICE_ID_GENIUS_MANTICORE
 
- USB_DEVICE_ID_GOGOPEN
 
- USB_DEVICE_ID_GOODTOUCH_000f
 
- USB_DEVICE_ID_GOOGLE_HAMMER
 
- USB_DEVICE_ID_GOOGLE_MAGNEMITE
 
- USB_DEVICE_ID_GOOGLE_MASTERBALL
 
- USB_DEVICE_ID_GOOGLE_MOONBALL
 
- USB_DEVICE_ID_GOOGLE_STAFF
 
- USB_DEVICE_ID_GOOGLE_TOUCH_ROSE
 
- USB_DEVICE_ID_GOOGLE_WAND
 
- USB_DEVICE_ID_GOOGLE_WHISKERS
 
- USB_DEVICE_ID_GREENASIA_DUAL_USB_JOYPAD
 
- USB_DEVICE_ID_GRETAGMACBETH_HUEY
 
- USB_DEVICE_ID_GTCO_100
 
- USB_DEVICE_ID_GTCO_1000
 
- USB_DEVICE_ID_GTCO_1001
 
- USB_DEVICE_ID_GTCO_1002
 
- USB_DEVICE_ID_GTCO_1003
 
- USB_DEVICE_ID_GTCO_1004
 
- USB_DEVICE_ID_GTCO_1005
 
- USB_DEVICE_ID_GTCO_1006
 
- USB_DEVICE_ID_GTCO_1007
 
- USB_DEVICE_ID_GTCO_101
 
- USB_DEVICE_ID_GTCO_103
 
- USB_DEVICE_ID_GTCO_104
 
- USB_DEVICE_ID_GTCO_105
 
- USB_DEVICE_ID_GTCO_106
 
- USB_DEVICE_ID_GTCO_107
 
- USB_DEVICE_ID_GTCO_108
 
- USB_DEVICE_ID_GTCO_200
 
- USB_DEVICE_ID_GTCO_201
 
- USB_DEVICE_ID_GTCO_202
 
- USB_DEVICE_ID_GTCO_203
 
- USB_DEVICE_ID_GTCO_204
 
- USB_DEVICE_ID_GTCO_205
 
- USB_DEVICE_ID_GTCO_206
 
- USB_DEVICE_ID_GTCO_207
 
- USB_DEVICE_ID_GTCO_300
 
- USB_DEVICE_ID_GTCO_301
 
- USB_DEVICE_ID_GTCO_302
 
- USB_DEVICE_ID_GTCO_303
 
- USB_DEVICE_ID_GTCO_304
 
- USB_DEVICE_ID_GTCO_305
 
- USB_DEVICE_ID_GTCO_306
 
- USB_DEVICE_ID_GTCO_307
 
- USB_DEVICE_ID_GTCO_308
 
- USB_DEVICE_ID_GTCO_309
 
- USB_DEVICE_ID_GTCO_400
 
- USB_DEVICE_ID_GTCO_401
 
- USB_DEVICE_ID_GTCO_402
 
- USB_DEVICE_ID_GTCO_403
 
- USB_DEVICE_ID_GTCO_404
 
- USB_DEVICE_ID_GTCO_405
 
- USB_DEVICE_ID_GTCO_500
 
- USB_DEVICE_ID_GTCO_501
 
- USB_DEVICE_ID_GTCO_502
 
- USB_DEVICE_ID_GTCO_503
 
- USB_DEVICE_ID_GTCO_504
 
- USB_DEVICE_ID_GTCO_90
 
- USB_DEVICE_ID_GYRATION_REMOTE
 
- USB_DEVICE_ID_GYRATION_REMOTE_2
 
- USB_DEVICE_ID_GYRATION_REMOTE_3
 
- USB_DEVICE_ID_HANVON_ALT_MULTITOUCH
 
- USB_DEVICE_ID_HANVON_MULTITOUCH
 
- USB_DEVICE_ID_HANWANG_TABLET_FIRST
 
- USB_DEVICE_ID_HANWANG_TABLET_LAST
 
- USB_DEVICE_ID_HOLTEK_ALT_KEYBOARD
 
- USB_DEVICE_ID_HOLTEK_ALT_KEYBOARD_A096
 
- USB_DEVICE_ID_HOLTEK_ALT_MOUSE_A04A
 
- USB_DEVICE_ID_HOLTEK_ALT_MOUSE_A067
 
- USB_DEVICE_ID_HOLTEK_ALT_MOUSE_A070
 
- USB_DEVICE_ID_HOLTEK_ALT_MOUSE_A072
 
- USB_DEVICE_ID_HOLTEK_ALT_MOUSE_A081
 
- USB_DEVICE_ID_HOLTEK_ALT_MOUSE_A0C2
 
- USB_DEVICE_ID_HOLTEK_ON_LINE_GRIP
 
- USB_DEVICE_ID_HP_X2
 
- USB_DEVICE_ID_HP_X2_10_COVER
 
- USB_DEVICE_ID_HUION_HS64
 
- USB_DEVICE_ID_HUION_TABLET
 
- USB_DEVICE_ID_I6050
 
- USB_DEVICE_ID_I6050_2
 
- USB_DEVICE_ID_I6150
 
- USB_DEVICE_ID_I6150_2
 
- USB_DEVICE_ID_I6150_3
 
- USB_DEVICE_ID_I6250
 
- USB_DEVICE_ID_IBM_GAMEPAD
 
- USB_DEVICE_ID_IBM_SCROLLPOINT_800DPI_OPTICAL
 
- USB_DEVICE_ID_IBM_SCROLLPOINT_800DPI_OPTICAL_PRO
 
- USB_DEVICE_ID_IBM_SCROLLPOINT_III
 
- USB_DEVICE_ID_IBM_SCROLLPOINT_OPTICAL
 
- USB_DEVICE_ID_IBM_SCROLLPOINT_PRO
 
- USB_DEVICE_ID_ICADE
 
- USB_DEVICE_ID_IDEACOM_IDC6650
 
- USB_DEVICE_ID_IDEACOM_IDC6651
 
- USB_DEVICE_ID_IDEACOM_IDC6680
 
- USB_DEVICE_ID_ILITEK_MULTITOUCH
 
- USB_DEVICE_ID_INNEX_GENESIS_ATARI
 
- USB_DEVICE_ID_INTEL_HID_SENSOR_0
 
- USB_DEVICE_ID_INTEL_HID_SENSOR_1
 
- USB_DEVICE_ID_IRTOUCH_INFRARED_USB
 
- USB_DEVICE_ID_ITE8595
 
- USB_DEVICE_ID_ITE_LENOVO_YOGA
 
- USB_DEVICE_ID_ITE_LENOVO_YOGA2
 
- USB_DEVICE_ID_ITE_LENOVO_YOGA900
 
- USB_DEVICE_ID_JABRA_GN9350E
 
- USB_DEVICE_ID_JABRA_SPEAK_410
 
- USB_DEVICE_ID_JABRA_SPEAK_510
 
- USB_DEVICE_ID_JESS2_COLOR_RUMBLE_PAD
 
- USB_DEVICE_ID_JESS_YUREX
 
- USB_DEVICE_ID_KBGEAR_JAMSTUDIO
 
- USB_DEVICE_ID_KEYTOUCH_IEC
 
- USB_DEVICE_ID_KS_SLIMBLADE
 
- USB_DEVICE_ID_KWORLD_RADIO_FM700
 
- USB_DEVICE_ID_KYE_EASYPEN_I405X
 
- USB_DEVICE_ID_KYE_EASYPEN_M406XE
 
- USB_DEVICE_ID_KYE_EASYPEN_M610X
 
- USB_DEVICE_ID_KYE_ERGO_525V
 
- USB_DEVICE_ID_KYE_GPEN_560
 
- USB_DEVICE_ID_KYE_MOUSEPEN_I608X
 
- USB_DEVICE_ID_KYE_MOUSEPEN_I608X_V2
 
- USB_DEVICE_ID_KYE_PENSKETCH_M912
 
- USB_DEVICE_ID_LABTEC_WIRELESS_KEYBOARD
 
- USB_DEVICE_ID_LCPOWER_LC1000
 
- USB_DEVICE_ID_LD_ABSESP
 
- USB_DEVICE_ID_LD_AUTODATABUS
 
- USB_DEVICE_ID_LD_CASSY
 
- USB_DEVICE_ID_LD_CASSY2
 
- USB_DEVICE_ID_LD_COM3LAB
 
- USB_DEVICE_ID_LD_CONVERTERCONTROLLERCASSY
 
- USB_DEVICE_ID_LD_DMMP
 
- USB_DEVICE_ID_LD_HEATCONTROL
 
- USB_DEVICE_ID_LD_HYBRID
 
- USB_DEVICE_ID_LD_JWM
 
- USB_DEVICE_ID_LD_MACHINETEST
 
- USB_DEVICE_ID_LD_MACHINETESTCASSY
 
- USB_DEVICE_ID_LD_MCT
 
- USB_DEVICE_ID_LD_MICROCASSYCURRENT
 
- USB_DEVICE_ID_LD_MICROCASSYPH
 
- USB_DEVICE_ID_LD_MICROCASSYTEMPERATURE
 
- USB_DEVICE_ID_LD_MICROCASSYTIME
 
- USB_DEVICE_ID_LD_MICROCASSYVOLTAGE
 
- USB_DEVICE_ID_LD_MOBILECASSY
 
- USB_DEVICE_ID_LD_MOBILECASSY2
 
- USB_DEVICE_ID_LD_MOSTANALYSER
 
- USB_DEVICE_ID_LD_MOSTANALYSER2
 
- USB_DEVICE_ID_LD_MOTOR
 
- USB_DEVICE_ID_LD_NETWORKANALYSER
 
- USB_DEVICE_ID_LD_POCKETCASSY
 
- USB_DEVICE_ID_LD_POCKETCASSY2
 
- USB_DEVICE_ID_LD_POWERANALYSERCASSY
 
- USB_DEVICE_ID_LD_POWERCONTROL
 
- USB_DEVICE_ID_LD_TELEPORT
 
- USB_DEVICE_ID_LD_UMIB
 
- USB_DEVICE_ID_LD_UMIC
 
- USB_DEVICE_ID_LD_UMIP
 
- USB_DEVICE_ID_LD_VIDEOCOM
 
- USB_DEVICE_ID_LD_XRAY
 
- USB_DEVICE_ID_LD_XRAY2
 
- USB_DEVICE_ID_LD_XRAYCT
 
- USB_DEVICE_ID_LED_DISPLAY
 
- USB_DEVICE_ID_LENOVO_CBTKBD
 
- USB_DEVICE_ID_LENOVO_CUSBKBD
 
- USB_DEVICE_ID_LENOVO_PIXART_USB_MOUSE_608D
 
- USB_DEVICE_ID_LENOVO_SCROLLPOINT_OPTICAL
 
- USB_DEVICE_ID_LENOVO_TPKBD
 
- USB_DEVICE_ID_LENOVO_TPPRODOCK
 
- USB_DEVICE_ID_LENOVO_X1_COVER
 
- USB_DEVICE_ID_LENOVO_X1_TAB
 
- USB_DEVICE_ID_LENOVO_X1_TAB3
 
- USB_DEVICE_ID_LG_MELFAS_MT
 
- USB_DEVICE_ID_LG_MULTITOUCH
 
- USB_DEVICE_ID_LOGITECH_27MHZ_MOUSE_RECEIVER
 
- USB_DEVICE_ID_LOGITECH_AUDIOHUB
 
- USB_DEVICE_ID_LOGITECH_C007
 
- USB_DEVICE_ID_LOGITECH_C077
 
- USB_DEVICE_ID_LOGITECH_CORDLESS_DESKTOP_LX500
 
- USB_DEVICE_ID_LOGITECH_DFGT_WHEEL
 
- USB_DEVICE_ID_LOGITECH_DFP_WHEEL
 
- USB_DEVICE_ID_LOGITECH_DUAL_ACTION
 
- USB_DEVICE_ID_LOGITECH_ELITE_KBD
 
- USB_DEVICE_ID_LOGITECH_EXTREME_3D
 
- USB_DEVICE_ID_LOGITECH_FLIGHT_SYSTEM_G940
 
- USB_DEVICE_ID_LOGITECH_FORCE3D_PRO
 
- USB_DEVICE_ID_LOGITECH_G25_WHEEL
 
- USB_DEVICE_ID_LOGITECH_G27_WHEEL
 
- USB_DEVICE_ID_LOGITECH_G29_WHEEL
 
- USB_DEVICE_ID_LOGITECH_G920_WHEEL
 
- USB_DEVICE_ID_LOGITECH_HARMONY_FIRST
 
- USB_DEVICE_ID_LOGITECH_HARMONY_LAST
 
- USB_DEVICE_ID_LOGITECH_HARMONY_PS3
 
- USB_DEVICE_ID_LOGITECH_KEYBOARD_G710_PLUS
 
- USB_DEVICE_ID_LOGITECH_MOMO_WHEEL
 
- USB_DEVICE_ID_LOGITECH_MOMO_WHEEL2
 
- USB_DEVICE_ID_LOGITECH_MOUSE_C01A
 
- USB_DEVICE_ID_LOGITECH_MOUSE_C05A
 
- USB_DEVICE_ID_LOGITECH_MOUSE_C06A
 
- USB_DEVICE_ID_LOGITECH_NANO_RECEIVER
 
- USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_2
 
- USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_LIGHTSPEED_1
 
- USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_LIGHTSPEED_1_1
 
- USB_DEVICE_ID_LOGITECH_NANO_RECEIVER_POWERPLAY
 
- USB_DEVICE_ID_LOGITECH_RECEIVER
 
- USB_DEVICE_ID_LOGITECH_RUMBLEPAD
 
- USB_DEVICE_ID_LOGITECH_RUMBLEPAD2
 
- USB_DEVICE_ID_LOGITECH_RUMBLEPAD2_2
 
- USB_DEVICE_ID_LOGITECH_RUMBLEPAD_CORD
 
- USB_DEVICE_ID_LOGITECH_T651
 
- USB_DEVICE_ID_LOGITECH_UNIFYING_RECEIVER
 
- USB_DEVICE_ID_LOGITECH_UNIFYING_RECEIVER_2
 
- USB_DEVICE_ID_LOGITECH_VIBRATION_WHEEL
 
- USB_DEVICE_ID_LOGITECH_WHEEL
 
- USB_DEVICE_ID_LOGITECH_WII_WHEEL
 
- USB_DEVICE_ID_LOGITECH_WINGMAN_F3D
 
- USB_DEVICE_ID_LOGITECH_WINGMAN_FFG
 
- USB_DEVICE_ID_LOGITECH_WINGMAN_FG
 
- USB_DEVICE_ID_LUXAFOR
 
- USB_DEVICE_ID_MACALLY_IKEY_KEYBOARD
 
- USB_DEVICE_ID_MADCATZ_BEATPAD
 
- USB_DEVICE_ID_MADCATZ_RAT5
 
- USB_DEVICE_ID_MADCATZ_RAT9
 
- USB_DEVICE_ID_MATCH_DEVICE
 
- USB_DEVICE_ID_MATCH_DEVICE_AND_VERSION
 
- USB_DEVICE_ID_MATCH_DEV_CLASS
 
- USB_DEVICE_ID_MATCH_DEV_HI
 
- USB_DEVICE_ID_MATCH_DEV_INFO
 
- USB_DEVICE_ID_MATCH_DEV_LO
 
- USB_DEVICE_ID_MATCH_DEV_PROTOCOL
 
- USB_DEVICE_ID_MATCH_DEV_RANGE
 
- USB_DEVICE_ID_MATCH_DEV_SUBCLASS
 
- USB_DEVICE_ID_MATCH_INT_CLASS
 
- USB_DEVICE_ID_MATCH_INT_INFO
 
- USB_DEVICE_ID_MATCH_INT_NUMBER
 
- USB_DEVICE_ID_MATCH_INT_PROTOCOL
 
- USB_DEVICE_ID_MATCH_INT_SUBCLASS
 
- USB_DEVICE_ID_MATCH_PRODUCT
 
- USB_DEVICE_ID_MATCH_VENDOR
 
- USB_DEVICE_ID_MCC_PMD1024LS
 
- USB_DEVICE_ID_MCC_PMD1208LS
 
- USB_DEVICE_ID_MCS_GAMEPADBLOCK
 
- USB_DEVICE_ID_MGE_UPS
 
- USB_DEVICE_ID_MGE_UPS1
 
- USB_DEVICE_ID_MSI_GT683R_LED_PANEL
 
- USB_DEVICE_ID_MS_COMFORT_KEYBOARD
 
- USB_DEVICE_ID_MS_COMFORT_MOUSE_4500
 
- USB_DEVICE_ID_MS_DIGITAL_MEDIA_3K
 
- USB_DEVICE_ID_MS_DIGITAL_MEDIA_3KV1
 
- USB_DEVICE_ID_MS_DIGITAL_MEDIA_600
 
- USB_DEVICE_ID_MS_DIGITAL_MEDIA_7K
 
- USB_DEVICE_ID_MS_LK6K
 
- USB_DEVICE_ID_MS_NE4K
 
- USB_DEVICE_ID_MS_NE4K_JP
 
- USB_DEVICE_ID_MS_NE7K
 
- USB_DEVICE_ID_MS_OFFICE_KB
 
- USB_DEVICE_ID_MS_PIXART_MOUSE
 
- USB_DEVICE_ID_MS_POWER_COVER
 
- USB_DEVICE_ID_MS_PRESENTER_8K_BT
 
- USB_DEVICE_ID_MS_PRESENTER_8K_USB
 
- USB_DEVICE_ID_MS_SURFACE_PRO_2
 
- USB_DEVICE_ID_MS_TOUCH_COVER_2
 
- USB_DEVICE_ID_MS_TYPE_COVER_2
 
- USB_DEVICE_ID_MS_XBOX_ONE_S_CONTROLLER
 
- USB_DEVICE_ID_MTP
 
- USB_DEVICE_ID_MTP_SITRONIX
 
- USB_DEVICE_ID_MTP_STM
 
- USB_DEVICE_ID_MULTITOUCH_3200
 
- USB_DEVICE_ID_MX3000_RECEIVER
 
- USB_DEVICE_ID_NATSU_GAMEPAD
 
- USB_DEVICE_ID_NCR_FIRST
 
- USB_DEVICE_ID_NCR_LAST
 
- USB_DEVICE_ID_NEC_USB_GAME_PAD
 
- USB_DEVICE_ID_NEXIO_MULTITOUCH_420
 
- USB_DEVICE_ID_NEXIO_MULTITOUCH_PTI0750
 
- USB_DEVICE_ID_NEXTWINDOW_TOUCHSCREEN
 
- USB_DEVICE_ID_NINTENDO_WIIMOTE
 
- USB_DEVICE_ID_NINTENDO_WIIMOTE2
 
- USB_DEVICE_ID_NOVATEK_MOUSE
 
- USB_DEVICE_ID_NOVATEK_PCT
 
- USB_DEVICE_ID_NTRIG_DUOSENSE
 
- USB_DEVICE_ID_NTRIG_TOUCH_SCREEN
 
- USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_1
 
- USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_10
 
- USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_11
 
- USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_12
 
- USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_13
 
- USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_14
 
- USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_15
 
- USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_16
 
- USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_17
 
- USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_18
 
- USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_2
 
- USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_3
 
- USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_4
 
- USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_5
 
- USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_6
 
- USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_7
 
- USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_8
 
- USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_9
 
- USB_DEVICE_ID_N_S_HARMONY
 
- USB_DEVICE_ID_ONTRAK_ADU100
 
- USB_DEVICE_ID_ORTEK_IHOME_IMAC_A210S
 
- USB_DEVICE_ID_ORTEK_PKB1700
 
- USB_DEVICE_ID_ORTEK_WKB2000
 
- USB_DEVICE_ID_PANABOARD_UBT780
 
- USB_DEVICE_ID_PANABOARD_UBT880
 
- USB_DEVICE_ID_PANTHERLORD_TWIN_USB_JOYSTICK
 
- USB_DEVICE_ID_PEGASUS_NOTETAKER_EN100
 
- USB_DEVICE_ID_PENMOUNT_1610
 
- USB_DEVICE_ID_PENMOUNT_1640
 
- USB_DEVICE_ID_PENMOUNT_6000
 
- USB_DEVICE_ID_PENMOUNT_PCI
 
- USB_DEVICE_ID_PENPOWER
 
- USB_DEVICE_ID_PETALYNX_MAXTER_REMOTE
 
- USB_DEVICE_ID_PETZL_HEADLAMP
 
- USB_DEVICE_ID_PHILIPS_IEEE802154_DONGLE
 
- USB_DEVICE_ID_PICK16F1454
 
- USB_DEVICE_ID_PICK16F1454_V2
 
- USB_DEVICE_ID_PICKIT1
 
- USB_DEVICE_ID_PICKIT2
 
- USB_DEVICE_ID_PICOLCD
 
- USB_DEVICE_ID_PICOLCD_BOOTLOADER
 
- USB_DEVICE_ID_PIXART_OPTICAL_TOUCH_SCREEN
 
- USB_DEVICE_ID_PIXART_OPTICAL_TOUCH_SCREEN1
 
- USB_DEVICE_ID_PIXART_OPTICAL_TOUCH_SCREEN2
 
- USB_DEVICE_ID_PIXART_USB_OPTICAL_MOUSE
 
- USB_DEVICE_ID_PIXART_USB_OPTICAL_MOUSE_ID2
 
- USB_DEVICE_ID_PI_ENGINEERING_VEC_USB_FOOTPEDAL
 
- USB_DEVICE_ID_PLAYDOTCOM_EMS_USBII
 
- USB_DEVICE_ID_POWERCOM_UPS
 
- USB_DEVICE_ID_POWERMATE
 
- USB_DEVICE_ID_PRIMAX_KEYBOARD
 
- USB_DEVICE_ID_PRIMAX_MOUSE_4D22
 
- USB_DEVICE_ID_PRIMAX_PIXART_MOUSE_4D0F
 
- USB_DEVICE_ID_PRIMAX_PIXART_MOUSE_4D65
 
- USB_DEVICE_ID_PRIMAX_PIXART_MOUSE_4E22
 
- USB_DEVICE_ID_PRIMAX_REZEL
 
- USB_DEVICE_ID_PRODIGE_CORDLESS
 
- USB_DEVICE_ID_PRODIKEYS_PCMIDI
 
- USB_DEVICE_ID_QUAD_USB_JOYPAD
 
- USB_DEVICE_ID_QUANTA_OPTICAL_TOUCH
 
- USB_DEVICE_ID_QUANTA_OPTICAL_TOUCH_3001
 
- USB_DEVICE_ID_QUANTA_OPTICAL_TOUCH_3003
 
- USB_DEVICE_ID_QUANTA_OPTICAL_TOUCH_3008
 
- USB_DEVICE_ID_RADIOSHARK
 
- USB_DEVICE_ID_RAPHNET_2NES2SNES
 
- USB_DEVICE_ID_RAPHNET_4NES4SNES
 
- USB_DEVICE_ID_RAPHNET_4NES4SNES_OLD
 
- USB_DEVICE_ID_RARITAN_KVM_DONGLE
 
- USB_DEVICE_ID_RAZER_BLADE_14
 
- USB_DEVICE_ID_REALTEK_READER
 
- USB_DEVICE_ID_REDRAGON_ASURA
 
- USB_DEVICE_ID_REDRAGON_SEYMUR2
 
- USB_DEVICE_ID_RETRODE2
 
- USB_DEVICE_ID_RETROUSB_SNES_RETROPAD
 
- USB_DEVICE_ID_RETROUSB_SNES_RETROPORT
 
- USB_DEVICE_ID_RETRO_ADAPTER
 
- USB_DEVICE_ID_RI_KA_WEBMAIL
 
- USB_DEVICE_ID_ROCCAT_ARVO
 
- USB_DEVICE_ID_ROCCAT_ISKU
 
- USB_DEVICE_ID_ROCCAT_ISKUFX
 
- USB_DEVICE_ID_ROCCAT_KONE
 
- USB_DEVICE_ID_ROCCAT_KONEPLUS
 
- USB_DEVICE_ID_ROCCAT_KONEPURE
 
- USB_DEVICE_ID_ROCCAT_KONEPURE_OPTICAL
 
- USB_DEVICE_ID_ROCCAT_KONEXTD
 
- USB_DEVICE_ID_ROCCAT_KOVAPLUS
 
- USB_DEVICE_ID_ROCCAT_LUA
 
- USB_DEVICE_ID_ROCCAT_PYRA_WIRED
 
- USB_DEVICE_ID_ROCCAT_PYRA_WIRELESS
 
- USB_DEVICE_ID_ROCCAT_RYOS_MK
 
- USB_DEVICE_ID_ROCCAT_RYOS_MK_GLOW
 
- USB_DEVICE_ID_ROCCAT_RYOS_MK_PRO
 
- USB_DEVICE_ID_ROCCAT_SAVU
 
- USB_DEVICE_ID_S510_RECEIVER
 
- USB_DEVICE_ID_S510_RECEIVER_2
 
- USB_DEVICE_ID_SAITEK_MMO7
 
- USB_DEVICE_ID_SAITEK_PS1000
 
- USB_DEVICE_ID_SAITEK_RAT7
 
- USB_DEVICE_ID_SAITEK_RAT7_CONTAGION
 
- USB_DEVICE_ID_SAITEK_RAT7_OLD
 
- USB_DEVICE_ID_SAITEK_RAT9
 
- USB_DEVICE_ID_SAITEK_RUMBLEPAD
 
- USB_DEVICE_ID_SAITEK_X52
 
- USB_DEVICE_ID_SAMSUNG_IR_REMOTE
 
- USB_DEVICE_ID_SAMSUNG_WIRELESS_KBD_MOUSE
 
- USB_DEVICE_ID_SEMICO_USB_KEYKOARD
 
- USB_DEVICE_ID_SEMICO_USB_KEYKOARD2
 
- USB_DEVICE_ID_SENNHEISER_BTD500USB
 
- USB_DEVICE_ID_SIDEWINDER_GV
 
- USB_DEVICE_ID_SIGMATEL_STMP3780
 
- USB_DEVICE_ID_SIGMA_MICRO_KEYBOARD
 
- USB_DEVICE_ID_SIGNOTEC_VIEWSONIC_PD1011
 
- USB_DEVICE_ID_SINO_LITE_CONTROLLER
 
- USB_DEVICE_ID_SIS1030_TOUCH
 
- USB_DEVICE_ID_SIS817_TOUCH
 
- USB_DEVICE_ID_SIS9200_TOUCH
 
- USB_DEVICE_ID_SIS_TS
 
- USB_DEVICE_ID_SKYCABLE_WIRELESS_PRESENTER
 
- USB_DEVICE_ID_SMARTJOY_DUAL_PLUS
 
- USB_DEVICE_ID_SMARTJOY_PLUS
 
- USB_DEVICE_ID_SMK_NSG_MR5U_REMOTE
 
- USB_DEVICE_ID_SMK_NSG_MR7U_REMOTE
 
- USB_DEVICE_ID_SMK_PS3_BDREMOTE
 
- USB_DEVICE_ID_SONY_BUZZ_CONTROLLER
 
- USB_DEVICE_ID_SONY_MOTION_CONTROLLER
 
- USB_DEVICE_ID_SONY_NAVIGATION_CONTROLLER
 
- USB_DEVICE_ID_SONY_PS3_BDREMOTE
 
- USB_DEVICE_ID_SONY_PS3_CONTROLLER
 
- USB_DEVICE_ID_SONY_PS4_CONTROLLER
 
- USB_DEVICE_ID_SONY_PS4_CONTROLLER_2
 
- USB_DEVICE_ID_SONY_PS4_CONTROLLER_DONGLE
 
- USB_DEVICE_ID_SONY_VAIO_VGP_MOUSE
 
- USB_DEVICE_ID_SONY_VAIO_VGX_MOUSE
 
- USB_DEVICE_ID_SONY_WIRELESS_BUZZ_CONTROLLER
 
- USB_DEVICE_ID_SOUNDGRAPH_IMON_FIRST
 
- USB_DEVICE_ID_SOUNDGRAPH_IMON_LAST
 
- USB_DEVICE_ID_SOUNDKNOB
 
- USB_DEVICE_ID_SPACENAVIGATOR
 
- USB_DEVICE_ID_SPACETRAVELLER
 
- USB_DEVICE_ID_SPEEDLINK_VAD_CEZANNE
 
- USB_DEVICE_ID_STEAM_CONTROLLER
 
- USB_DEVICE_ID_STEAM_CONTROLLER_WIRELESS
 
- USB_DEVICE_ID_STEELSERIES_SRWS1
 
- USB_DEVICE_ID_STM_HID_SENSOR
 
- USB_DEVICE_ID_STM_HID_SENSOR_1
 
- USB_DEVICE_ID_SUNPLUS_WDESKTOP
 
- USB_DEVICE_ID_SUPER_DUAL_BOX_PRO
 
- USB_DEVICE_ID_SUPER_JOY_BOX_3
 
- USB_DEVICE_ID_SUPER_JOY_BOX_3_PRO
 
- USB_DEVICE_ID_SUPER_JOY_BOX_5_PRO
 
- USB_DEVICE_ID_SUPER_Q2
 
- USB_DEVICE_ID_SYMBOL_SCANNER_1
 
- USB_DEVICE_ID_SYMBOL_SCANNER_2
 
- USB_DEVICE_ID_SYMBOL_SCANNER_3
 
- USB_DEVICE_ID_SYNAPTICS_ACER_SWITCH5
 
- USB_DEVICE_ID_SYNAPTICS_ACER_SWITCH5_012
 
- USB_DEVICE_ID_SYNAPTICS_COMP_TP
 
- USB_DEVICE_ID_SYNAPTICS_CPAD
 
- USB_DEVICE_ID_SYNAPTICS_DELL_K12A
 
- USB_DEVICE_ID_SYNAPTICS_DPAD
 
- USB_DEVICE_ID_SYNAPTICS_HD
 
- USB_DEVICE_ID_SYNAPTICS_INT_TP
 
- USB_DEVICE_ID_SYNAPTICS_LTS1
 
- USB_DEVICE_ID_SYNAPTICS_LTS2
 
- USB_DEVICE_ID_SYNAPTICS_QUAD_HD
 
- USB_DEVICE_ID_SYNAPTICS_STICK
 
- USB_DEVICE_ID_SYNAPTICS_TP
 
- USB_DEVICE_ID_SYNAPTICS_TP_V103
 
- USB_DEVICE_ID_SYNAPTICS_TS
 
- USB_DEVICE_ID_SYNAPTICS_WP
 
- USB_DEVICE_ID_SYNAPTICS_WTP
 
- USB_DEVICE_ID_TC4UM
 
- USB_DEVICE_ID_TC5UH
 
- USB_DEVICE_ID_TEXAS_INSTRUMENTS_LENOVO_YOGA
 
- USB_DEVICE_ID_THQ_PS3_UDRAW
 
- USB_DEVICE_ID_THT_2P_ARCADE
 
- USB_DEVICE_ID_TIVO_SLIDE
 
- USB_DEVICE_ID_TIVO_SLIDE_BT
 
- USB_DEVICE_ID_TIVO_SLIDE_PRO
 
- USB_DEVICE_ID_TOPMAX_COBRAPAD
 
- USB_DEVICE_ID_TOPSEED2_PERIPAD_701
 
- USB_DEVICE_ID_TOPSEED2_RF_COMBO
 
- USB_DEVICE_ID_TOPSEED_CYBERLINK
 
- USB_DEVICE_ID_TOSHIBA_CLICK_L9W
 
- USB_DEVICE_ID_TOUCHPACK_RTS
 
- USB_DEVICE_ID_TOUCH_INTL_MULTI_TOUCH
 
- USB_DEVICE_ID_TPV_OPTICAL_TOUCHSCREEN_8882
 
- USB_DEVICE_ID_TPV_OPTICAL_TOUCHSCREEN_8883
 
- USB_DEVICE_ID_TURBOX_KEYBOARD
 
- USB_DEVICE_ID_TURBOX_TOUCHSCREEN_MOSART
 
- USB_DEVICE_ID_TWINHAN_IR_REMOTE
 
- USB_DEVICE_ID_U2F_ZERO
 
- USB_DEVICE_ID_UCLOGIC_DRAWIMAGE_G3
 
- USB_DEVICE_ID_UCLOGIC_TABLET_KNA5
 
- USB_DEVICE_ID_UCLOGIC_TABLET_PF1209
 
- USB_DEVICE_ID_UCLOGIC_TABLET_TWA60
 
- USB_DEVICE_ID_UCLOGIC_TABLET_TWHA60
 
- USB_DEVICE_ID_UCLOGIC_TABLET_WP1062
 
- USB_DEVICE_ID_UCLOGIC_TABLET_WP4030U
 
- USB_DEVICE_ID_UCLOGIC_TABLET_WP5540U
 
- USB_DEVICE_ID_UCLOGIC_TABLET_WP8060U
 
- USB_DEVICE_ID_UCLOGIC_UGEE_TABLET_45
 
- USB_DEVICE_ID_UCLOGIC_UGEE_TABLET_47
 
- USB_DEVICE_ID_UCLOGIC_UGEE_TABLET_81
 
- USB_DEVICE_ID_UCLOGIC_WIRELESS_TABLET_TWHL850
 
- USB_DEVICE_ID_UGCI_DRIVING
 
- USB_DEVICE_ID_UGCI_FIGHTING
 
- USB_DEVICE_ID_UGCI_FLYING
 
- USB_DEVICE_ID_UGEE_TABLET_EX07S
 
- USB_DEVICE_ID_UGEE_TABLET_G5
 
- USB_DEVICE_ID_UGEE_TABLET_RAINBOW_CV720
 
- USB_DEVICE_ID_UGEE_XPPEN_TABLET_DECO01
 
- USB_DEVICE_ID_UGEE_XPPEN_TABLET_G540
 
- USB_DEVICE_ID_UGEE_XPPEN_TABLET_G640
 
- USB_DEVICE_ID_UGTIZER_TABLET_GP0610
 
- USB_DEVICE_ID_UNITEC_USB_TOUCH_0709
 
- USB_DEVICE_ID_UNITEC_USB_TOUCH_0A19
 
- USB_DEVICE_ID_USB_SUN
 
- USB_DEVICE_ID_VELLEMAN_K8055_FIRST
 
- USB_DEVICE_ID_VELLEMAN_K8055_LAST
 
- USB_DEVICE_ID_VELLEMAN_K8061_FIRST
 
- USB_DEVICE_ID_VELLEMAN_K8061_LAST
 
- USB_DEVICE_ID_VIEWSONIC_PD1011
 
- USB_DEVICE_ID_VTL_MULTITOUCH_FF3F
 
- USB_DEVICE_ID_WACOM_GRAPHIRE_BLUETOOTH
 
- USB_DEVICE_ID_WACOM_INTUOS4_BLUETOOTH
 
- USB_DEVICE_ID_WALTOP_MEDIA_TABLET_10_6_INCH
 
- USB_DEVICE_ID_WALTOP_MEDIA_TABLET_14_1_INCH
 
- USB_DEVICE_ID_WALTOP_PID_0038
 
- USB_DEVICE_ID_WALTOP_Q_PAD
 
- USB_DEVICE_ID_WALTOP_SIRIUS_BATTERY_FREE_TABLET
 
- USB_DEVICE_ID_WALTOP_SLIM_TABLET_12_1_INCH
 
- USB_DEVICE_ID_WALTOP_SLIM_TABLET_5_8_INCH
 
- USB_DEVICE_ID_WEIDA_8752
 
- USB_DEVICE_ID_WEIDA_8755
 
- USB_DEVICE_ID_WIRELESS_OPTICAL_DESKTOP_3_0
 
- USB_DEVICE_ID_WISTRON_OPTICAL_TOUCH
 
- USB_DEVICE_ID_XAT_CSR
 
- USB_DEVICE_ID_XIN_MO_DUAL_ARCADE
 
- USB_DEVICE_ID_XIROKU_CSR
 
- USB_DEVICE_ID_XIROKU_CSR1
 
- USB_DEVICE_ID_XIROKU_CSR2
 
- USB_DEVICE_ID_XIROKU_MPX
 
- USB_DEVICE_ID_XIROKU_MPX1
 
- USB_DEVICE_ID_XIROKU_MPX2
 
- USB_DEVICE_ID_XIROKU_SPX
 
- USB_DEVICE_ID_XIROKU_SPX1
 
- USB_DEVICE_ID_XIROKU_SPX2
 
- USB_DEVICE_ID_YEALINK_P1K_P4K_B2K
 
- USB_DEVICE_ID_YIYNOVA_TABLET
 
- USB_DEVICE_ID_ZYDACRON_REMOTE_CONTROL
 
- USB_DEVICE_ID_ZYTRONIC_ZXY100
 
- USB_DEVICE_INFO
 
- USB_DEVICE_INTERFACE_CLASS
 
- USB_DEVICE_INTERFACE_NUMBER
 
- USB_DEVICE_INTERFACE_PROTOCOL
 
- USB_DEVICE_LENOVO
 
- USB_DEVICE_LTM_ENABLE
 
- USB_DEVICE_MAJOR
 
- USB_DEVICE_MASS_DATA
 
- USB_DEVICE_MAX
 
- USB_DEVICE_MAX_ADDRESS
 
- USB_DEVICE_MODE
 
- USB_DEVICE_OS_IS_PD_AWARE
 
- USB_DEVICE_POLICY_MODE
 
- USB_DEVICE_REMOTE_WAKEUP
 
- USB_DEVICE_REMOVABLE
 
- USB_DEVICE_REMOVABLE_UNKNOWN
 
- USB_DEVICE_REMOVE
 
- USB_DEVICE_SELF_POWERED
 
- USB_DEVICE_SYNAPTICS
 
- USB_DEVICE_TEST_MODE
 
- USB_DEVICE_U1_ENABLE
 
- USB_DEVICE_U2_ENABLE
 
- USB_DEVICE_VENDOR_SPEC
 
- USB_DEVICE_VER
 
- USB_DEVICE_WACOM
 
- USB_DEVICE_WUSB_DEVICE
 
- USB_DEV_ID_BRDG
 
- USB_DEV_ID_OS81118
 
- USB_DEV_ID_OS81119
 
- USB_DEV_ID_OS81210
 
- USB_DEV_INIT
 
- USB_DEV_STAT
 
- USB_DEV_STAT_LTM_ENABLED
 
- USB_DEV_STAT_U1_ENABLED
 
- USB_DEV_STAT_U2_ENABLED
 
- USB_DIAG
 
- USB_DIR_BOTH
 
- USB_DIR_IN
 
- USB_DIR_OUT
 
- USB_DMACHCR
 
- USB_DMACHCR_DE
 
- USB_DMACHCR_FTE
 
- USB_DMACHCR_IE
 
- USB_DMACHCR_NULL
 
- USB_DMACHCR_NULLE
 
- USB_DMACHCR_SP
 
- USB_DMACHCR_TE
 
- USB_DMACHCR_TS_16B
 
- USB_DMACHCR_TS_32B
 
- USB_DMACHCR_TS_8B
 
- USB_DMAC_CHAN_OFFSET
 
- USB_DMAC_CHCR_TS
 
- USB_DMAC_INITIAL_NR_DESC
 
- USB_DMAC_INITIAL_NR_SG
 
- USB_DMAC_SLAVE_BUSWIDTH
 
- USB_DMAC_XFER_SHIFT
 
- USB_DMAC_XFER_SIZE
 
- USB_DMADAR
 
- USB_DMAINTEN
 
- USB_DMAINTEN_EPERRINTEN
 
- USB_DMAINTEN_ETDERRINTEN
 
- USB_DMAINTSTAT
 
- USB_DMAINTSTAT_EPERR
 
- USB_DMAINTSTAT_ETDERR
 
- USB_DMAOR
 
- USB_DMAOR_AE
 
- USB_DMAOR_DME
 
- USB_DMAREV
 
- USB_DMASAR
 
- USB_DMASWR
 
- USB_DMASWR_SWR
 
- USB_DMATCR
 
- USB_DMATCR_MASK
 
- USB_DMATEND
 
- USB_DMA_CFG
 
- USB_DMA_CFG_EP_OUT_VALID
 
- USB_DMA_CFG_PHY_CLEAR
 
- USB_DMA_CFG_RX_BULK_AGG_EN
 
- USB_DMA_CFG_RX_BULK_AGG_LIMIT
 
- USB_DMA_CFG_RX_BULK_AGG_TIMEOUT
 
- USB_DMA_CFG_RX_BULK_EN
 
- USB_DMA_CFG_RX_BUSY
 
- USB_DMA_CFG_TXOP_HALT
 
- USB_DMA_CFG_TX_BULK_EN
 
- USB_DMA_CFG_TX_BUSY
 
- USB_DMA_CFG_TX_CLEAR
 
- USB_DR_MODE_HOST
 
- USB_DR_MODE_OTG
 
- USB_DR_MODE_PERIPHERAL
 
- USB_DR_MODE_UNKNOWN
 
- USB_DR_SYS_OFFSET
 
- USB_DT_BOS
 
- USB_DT_BOS_SIZE
 
- USB_DT_CONFIG
 
- USB_DT_CONFIG_SIZE
 
- USB_DT_CS_CONFIG
 
- USB_DT_CS_DEVICE
 
- USB_DT_CS_ENDPOINT
 
- USB_DT_CS_INTERFACE
 
- USB_DT_CS_IRDA
 
- USB_DT_CS_RADIO_CONTROL
 
- USB_DT_CS_STRING
 
- USB_DT_DEBUG
 
- USB_DT_DEVICE
 
- USB_DT_DEVICE_CAPABILITY
 
- USB_DT_DEVICE_QUALIFIER
 
- USB_DT_DEVICE_SIZE
 
- USB_DT_ENCRYPTION_TYPE
 
- USB_DT_ENDPOINT
 
- USB_DT_ENDPOINT_AUDIO_SIZE
 
- USB_DT_ENDPOINT_SIZE
 
- USB_DT_HUB
 
- USB_DT_HUB_NONVAR_SIZE
 
- USB_DT_INTERFACE
 
- USB_DT_INTERFACE_ASSOCIATION
 
- USB_DT_INTERFACE_ASSOCIATION_SIZE
 
- USB_DT_INTERFACE_POWER
 
- USB_DT_INTERFACE_SIZE
 
- USB_DT_KEY
 
- USB_DT_MIDI_IN_SIZE
 
- USB_DT_MIDI_OUT_SIZE
 
- USB_DT_MS_ENDPOINT_SIZE
 
- USB_DT_MS_HEADER_SIZE
 
- USB_DT_OTG
 
- USB_DT_OTHER_SPEED_CONFIG
 
- USB_DT_PIPE_USAGE
 
- USB_DT_RPIPE
 
- USB_DT_SECURITY
 
- USB_DT_SSP_ISOC_ENDPOINT_COMP
 
- USB_DT_SSP_ISOC_EP_COMP_SIZE
 
- USB_DT_SS_ENDPOINT_COMP
 
- USB_DT_SS_EP_COMP_SIZE
 
- USB_DT_SS_HUB
 
- USB_DT_SS_HUB_SIZE
 
- USB_DT_STRING
 
- USB_DT_USB_EXT_CAP_SIZE
 
- USB_DT_USB_PTM_ID_SIZE
 
- USB_DT_USB_SSP_CAP_SIZE
 
- USB_DT_USB_SS_CAP_SIZE
 
- USB_DT_USB_SS_CONTN_ID_SIZE
 
- USB_DT_USB_WIRELESS_CAP_SIZE
 
- USB_DT_WIRELESS_ENDPOINT_COMP
 
- USB_DT_WIRE_ADAPTER
 
- USB_DWC_CTRL1
 
- USB_DWC_CTRL1_DCRS
 
- USB_DWC_CTRL1_HSTRS
 
- USB_DWC_CTRL1_OTGD
 
- USB_DWC_CTRL2
 
- USB_DWC_CTRL2_PHY0RS
 
- USB_DWC_CTRL2_PHY1RS
 
- USB_DWC_CTRL2_PHYRS
 
- USB_DWC_CTRL3
 
- USB_DWC_CTRL3_EHCI0_CKEN
 
- USB_DWC_CTRL3_OHCI0_CKEN
 
- USB_DWC_CTRL3_OHCI1_CKEN
 
- USB_DWC_CTRL3_OTG0_CKEN
 
- USB_DWC_CTRL4
 
- USB_DWC_CTRL5
 
- USB_DWC_CTRL6
 
- USB_DWC_CTRL7
 
- USB_D_ODN
 
- USB_D_OEN
 
- USB_D_OVR
 
- USB_EEPROM_READ
 
- USB_EEPROM_WRITE
 
- USB_EHCI
 
- USB_EHCI_LOADED
 
- USB_EHCI_REG_BIT_STAT_STS
 
- USB_EHCI_REG_USB_FIFO
 
- USB_EHCI_REG_USB_MODE
 
- USB_EHCI_REG_USB_STATUS
 
- USB_EHCI_START
 
- USB_ELSA_AIRLANCER_ID
 
- USB_ELSA_VENDOR_ID
 
- USB_EMULATION_REG
 
- USB_ENC_TYPE_CCM_1
 
- USB_ENC_TYPE_RSA_1
 
- USB_ENC_TYPE_UNSECURE
 
- USB_ENC_TYPE_WIRED
 
- USB_ENDPOINT_DIR_MASK
 
- USB_ENDPOINT_HALT
 
- USB_ENDPOINT_INTRTYPE
 
- USB_ENDPOINT_INTR_NOTIFICATION
 
- USB_ENDPOINT_INTR_PERIODIC
 
- USB_ENDPOINT_MAXP_MASK
 
- USB_ENDPOINT_MAX_ADJUSTABLE
 
- USB_ENDPOINT_NUMBER_MASK
 
- USB_ENDPOINT_SWITCH_MASK
 
- USB_ENDPOINT_SWITCH_NO
 
- USB_ENDPOINT_SWITCH_SCALE
 
- USB_ENDPOINT_SWITCH_SWITCH
 
- USB_ENDPOINT_SYNCTYPE
 
- USB_ENDPOINT_SYNC_ADAPTIVE
 
- USB_ENDPOINT_SYNC_ASYNC
 
- USB_ENDPOINT_SYNC_NONE
 
- USB_ENDPOINT_SYNC_SYNC
 
- USB_ENDPOINT_USAGE_DATA
 
- USB_ENDPOINT_USAGE_FEEDBACK
 
- USB_ENDPOINT_USAGE_IMPLICIT_FB
 
- USB_ENDPOINT_USAGE_MASK
 
- USB_ENDPOINT_XFERTYPE_MASK
 
- USB_ENDPOINT_XFER_BULK
 
- USB_ENDPOINT_XFER_CONTROL
 
- USB_ENDPOINT_XFER_INT
 
- USB_ENDPOINT_XFER_ISOC
 
- USB_END_I2C_CMD
 
- USB_END_OF_INTR_REG
 
- USB_EP0_BC
 
- USB_EP0_CFG
 
- USB_EP0_CTL
 
- USB_EP0_IRQEN
 
- USB_EP0_IRQSTAT
 
- USB_EP0_MAXPKT
 
- USB_EP0_MAX_SIZE
 
- USB_EP0_STAT
 
- USB_EPA_CFG
 
- USB_EPA_CFG_0
 
- USB_EPA_CFG_1
 
- USB_EPA_CFG_2
 
- USB_EPA_CFG_3
 
- USB_EPA_CTL
 
- USB_EPA_CTL_0
 
- USB_EPA_CTL_1
 
- USB_EPA_CTL_2
 
- USB_EPA_CTL_3
 
- USB_EPA_FIFO_CFG
 
- USB_EPA_FIFO_CFG_0
 
- USB_EPA_FIFO_CFG_1
 
- USB_EPA_FIFO_CFG_2
 
- USB_EPA_FIFO_CFG_3
 
- USB_EPA_IRQEN
 
- USB_EPA_IRQSTAT
 
- USB_EPA_MAXPKT
 
- USB_EPA_MAXPKT_0
 
- USB_EPA_MAXPKT_1
 
- USB_EPA_MAXPKT_2
 
- USB_EPA_MAXPKT_3
 
- USB_EPA_STAT
 
- USB_EPDMABST4EN
 
- USB_EPDMABUFPTR
 
- USB_EPDMACHANLCLR
 
- USB_EPDMAEN
 
- USB_EPDMAENXYT
 
- USB_EPDMAERSTAT
 
- USB_EPDMAXTEN
 
- USB_EPNUM_MASK
 
- USB_EPNUM_SHIFT
 
- USB_EPSMSA
 
- USB_EP_BULK
 
- USB_EP_CAPS
 
- USB_EP_CAPS_DIR_ALL
 
- USB_EP_CAPS_DIR_IN
 
- USB_EP_CAPS_DIR_OUT
 
- USB_EP_CAPS_TYPE_ALL
 
- USB_EP_CAPS_TYPE_BULK
 
- USB_EP_CAPS_TYPE_CONTROL
 
- USB_EP_CAPS_TYPE_INT
 
- USB_EP_CAPS_TYPE_ISO
 
- USB_EP_CTRL
 
- USB_EP_DEF
 
- USB_EP_INT
 
- USB_EP_IN_BULK
 
- USB_EP_IN_INT
 
- USB_EP_IN_ISO
 
- USB_EP_ISO
 
- USB_EP_LIST_ADDRESS_MASK
 
- USB_EP_MAXP_MULT
 
- USB_EP_MAXP_MULT_MASK
 
- USB_EP_MAXP_MULT_SHIFT
 
- USB_EP_MF
 
- USB_EP_OUT_BULK
 
- USB_EP_OUT_ISO
 
- USB_EP_PARA_ALIGNMENT
 
- USB_EP_RTE
 
- USB_ERROR
 
- USB_ESDGMBH_VENDOR_ID
 
- USB_ETDDMABST4EN
 
- USB_ETDDMABUFPTR
 
- USB_ETDDMACHANLCLR
 
- USB_ETDDMAEN
 
- USB_ETDDMAENXYT
 
- USB_ETDDMAERSTAT
 
- USB_ETDDMAXTEN
 
- USB_ETDSMSA
 
- USB_ETD_DWORD
 
- USB_ETHERNET_CONFIGFS_ITEM
 
- USB_ETHERNET_CONFIGFS_ITEM_ATTR_DEV_ADDR
 
- USB_ETHERNET_CONFIGFS_ITEM_ATTR_HOST_ADDR
 
- USB_ETHERNET_CONFIGFS_ITEM_ATTR_IFNAME
 
- USB_ETHERNET_CONFIGFS_ITEM_ATTR_QMULT
 
- USB_ETHERNET_MODULE_PARAMETERS
 
- USB_ETHER_CONFIGFS_ITEM_ATTR_U8_RW
 
- USB_ETH_RNDIS
 
- USB_EVENT_CHARGER
 
- USB_EVENT_ENUMERATED
 
- USB_EVENT_ID
 
- USB_EVENT_NONE
 
- USB_EVENT_VBUS
 
- USB_EXT_PORT_RX_LANES
 
- USB_EXT_PORT_STAT_RX_LANES
 
- USB_EXT_PORT_STAT_RX_SPEED_ID
 
- USB_EXT_PORT_STAT_TX_LANES
 
- USB_EXT_PORT_STAT_TX_SPEED_ID
 
- USB_EXT_PORT_TX_LANES
 
- USB_EXT_PROP_BE32
 
- USB_EXT_PROP_BINARY
 
- USB_EXT_PROP_B_PROPERTY_DATA
 
- USB_EXT_PROP_B_PROPERTY_NAME
 
- USB_EXT_PROP_DW_PROPERTY_DATA_LENGTH
 
- USB_EXT_PROP_DW_PROPERTY_DATA_TYPE
 
- USB_EXT_PROP_DW_SIZE
 
- USB_EXT_PROP_LE32
 
- USB_EXT_PROP_RESERVED
 
- USB_EXT_PROP_UNICODE
 
- USB_EXT_PROP_UNICODE_ENV
 
- USB_EXT_PROP_UNICODE_LINK
 
- USB_EXT_PROP_UNICODE_MULTI
 
- USB_EXT_PROP_W_PROPERTY_NAME_LENGTH
 
- USB_E_BSY_MASK
 
- USB_E_DEFAULT_DEVICE
 
- USB_E_IDLE_MASK
 
- USB_E_MSF_MASK
 
- USB_E_RESET_MASK
 
- USB_E_RXB_MASK
 
- USB_E_SFT_MASK
 
- USB_E_SOF_MASK
 
- USB_E_TXB_MASK
 
- USB_E_TXE1_MASK
 
- USB_E_TXE2_MASK
 
- USB_E_TXE3_MASK
 
- USB_E_TXE4_MASK
 
- USB_E_TXE_MASK
 
- USB_FAST_LOOP
 
- USB_FIFO_ADDR
 
- USB_FIFO_ADDRESS
 
- USB_FIFO_CMD
 
- USB_FIFO_DATA
 
- USB_FLASH_MAX
 
- USB_FRAME_NUMBER
 
- USB_FRAME_USAGE
 
- USB_FRINDEX_MASKS
 
- USB_FS1_H_CLK
 
- USB_FS1_RESET
 
- USB_FS1_SYSTEM_CLK
 
- USB_FS1_XCVR_CLK
 
- USB_FS1_XCVR_FS_CLK
 
- USB_FS1_XCVR_FS_SRC
 
- USB_FS1_XCVR_RESET
 
- USB_FS1_XCVR_SRC
 
- USB_FS2_H_CLK
 
- USB_FS2_RESET
 
- USB_FS2_SYSTEM_CLK
 
- USB_FS2_XCVR_FS_CLK
 
- USB_FS2_XCVR_FS_SRC
 
- USB_FS2_XCVR_RESET
 
- USB_FTDI_ELAN_MINOR_BASE
 
- USB_FTDI_ELAN_PRODUCT_ID
 
- USB_FTDI_ELAN_VENDOR_ID
 
- USB_FUJITSU_E1100_ID
 
- USB_FUJITSU_VENDOR_ID
 
- USB_FULL_SPEED
 
- USB_FULL_SPEED_BULK_SIZE
 
- USB_FULL_SPEED_OPERATION
 
- USB_FUNC_GET_DESCRIPTOR
 
- USB_FUNC_I2C_CHECKRESULT
 
- USB_FUNC_I2C_CHECKWRITE
 
- USB_FUNC_I2C_MULTIWRITE
 
- USB_FUNC_I2C_READ
 
- USB_FUNC_I2C_REPEATREAD
 
- USB_FUNC_I2C_REPEATWRITE
 
- USB_FUNC_I2C_WRITE
 
- USB_F_MASS_STORAGE_H
 
- USB_GADGET_COMPOSITE_OPTIONS
 
- USB_GADGET_DELAYED_STATUS
 
- USB_GADGET_FIRST_AVAIL_IDX
 
- USB_GADGET_MANUFACTURER_IDX
 
- USB_GADGET_PRODUCT_IDX
 
- USB_GADGET_SERIAL_IDX
 
- USB_GET_BESL_BASELINE
 
- USB_GET_BESL_DEEP
 
- USB_GIGA_VENDOR_ID
 
- USB_GPIO_DEBOUNCE_MS
 
- USB_GPIO_DEB_MS
 
- USB_GPIO_DEB_US
 
- USB_GSUSB_1_PRODUCT_ID
 
- USB_GSUSB_1_VENDOR_ID
 
- USB_GZERO_LB_DESC
 
- USB_GZERO_SS_DESC
 
- USB_G_ALT_INT_BBB
 
- USB_G_ALT_INT_UAS
 
- USB_G_DEFAULT_SESSION_TAGS
 
- USB_G_STR_CONFIG
 
- USB_G_STR_INT_BBB
 
- USB_G_STR_INT_UAS
 
- USB_HIGH_INTERVALS_PER_SECOND
 
- USB_HIGH_ISO_BUFFERS
 
- USB_HIGH_SPEED
 
- USB_HIGH_SPEED_BULK_SIZE
 
- USB_HIGH_SPEED_OPERATION
 
- USB_HIMR_BCNDMAINT0
 
- USB_HIMR_BCNDMAINT1
 
- USB_HIMR_BCNDMAINT2
 
- USB_HIMR_BCNDMAINT3
 
- USB_HIMR_BCNDMAINT_E
 
- USB_HIMR_BCNDOK0
 
- USB_HIMR_BCNDOK1
 
- USB_HIMR_BCNDOK2
 
- USB_HIMR_BCNDOK3
 
- USB_HIMR_BEDOK
 
- USB_HIMR_BKDOK
 
- USB_HIMR_C2HCMD
 
- USB_HIMR_CPWM
 
- USB_HIMR_CPWM2
 
- USB_HIMR_CTW_END
 
- USB_HIMR_GTINT3
 
- USB_HIMR_GTINT4
 
- USB_HIMR_HIGHDOK
 
- USB_HIMR_HSISR_IND
 
- USB_HIMR_MGNTDOK
 
- USB_HIMR_PSTIMEOUT
 
- USB_HIMR_RDU
 
- USB_HIMR_ROK
 
- USB_HIMR_TIMEOUT1
 
- USB_HIMR_TIMEOUT2
 
- USB_HIMR_TSF_BIT32_TOGGLE
 
- USB_HIMR_TXBCNERR
 
- USB_HIMR_TXBCNOK
 
- USB_HIMR_VIDOK
 
- USB_HIMR_VODOK
 
- USB_HOST
 
- USB_HOST_EXTCON_HID
 
- USB_HOST_EXTCON_NAME
 
- USB_HOST_HHC_UHOST_EN
 
- USB_HP_WL215_ID
 
- USB_HS1_H_CLK
 
- USB_HS1_RESET
 
- USB_HS1_SYSTEM_CLK
 
- USB_HS1_SYSTEM_CLK_SRC
 
- USB_HS1_XCVR_CLK
 
- USB_HS1_XCVR_SRC
 
- USB_HS2_H_CLK
 
- USB_HS2_RESET
 
- USB_HS2_XCVR_CLK
 
- USB_HS2_XCVR_RESET
 
- USB_HS2_XCVR_SRC
 
- USB_HS3_H_CLK
 
- USB_HS3_RESET
 
- USB_HS3_XCVR_CLK
 
- USB_HS3_XCVR_SRC
 
- USB_HS4_H_CLK
 
- USB_HS4_RESET
 
- USB_HS4_XCVR_CLK
 
- USB_HS4_XCVR_SRC
 
- USB_HSIC_AHB_CLK_SRC
 
- USB_HSIC_CLK_SRC
 
- USB_HSIC_HSIC_CLK
 
- USB_HSIC_HSIC_CLK_SRC
 
- USB_HSIC_HSIO_CAL_CLK
 
- USB_HSIC_H_CLK
 
- USB_HSIC_IO_CAL_CLK_SRC
 
- USB_HSIC_MOCK_UTMI_CLK_SRC
 
- USB_HSIC_RESET
 
- USB_HSIC_SYSTEM_CLK
 
- USB_HSIC_SYSTEM_CLK_SRC
 
- USB_HSIC_XCVR_CLK
 
- USB_HSIC_XCVR_FS_CLK
 
- USB_HSIC_XCVR_FS_SRC
 
- USB_HSIC_XCVR_SRC
 
- USB_HS_HSIC_GDSC
 
- USB_HS_PHY
 
- USB_HS_SYSTEM_CLK_SRC
 
- USB_HUB_PR_FS
 
- USB_HUB_PR_HS_MULTI_TT
 
- USB_HUB_PR_HS_NO_TT
 
- USB_HUB_PR_HS_SINGLE_TT
 
- USB_HUB_PR_SS
 
- USB_HWDESC_HEADER_LEN
 
- USB_HWID
 
- USB_HYBRID_CANLIN_PRODUCT_ID
 
- USB_HYBRID_PRO_CANLIN_PRODUCT_ID
 
- USB_ID
 
- USB_IDLE
 
- USB_IDLE_STATUS_MASK
 
- USB_IDMOUSE_MINOR_BASE
 
- USB_ID_CTRL_CLR
 
- USB_ID_CTRL_SET
 
- USB_ID_DEBOUNCE_MS
 
- USB_ID_INT_EN_HI_CLR
 
- USB_ID_INT_EN_HI_SET
 
- USB_ID_INT_EN_LO_CLR
 
- USB_ID_INT_EN_LO_SET
 
- USB_ID_INT_LATCH_CLR
 
- USB_ID_INT_LATCH_SET
 
- USB_ID_INT_SRC
 
- USB_ID_OVR
 
- USB_ID_PRODUCT
 
- USB_ID_US122
 
- USB_ID_US122L
 
- USB_ID_US122MKII
 
- USB_ID_US144
 
- USB_ID_US144MKII
 
- USB_ID_US224
 
- USB_ID_US428
 
- USB_ID_VALUE
 
- USB_ID_VENDOR
 
- USB_IEN_CFGRESIEN
 
- USB_IEN_CON2IEN
 
- USB_IEN_CONIEN
 
- USB_IEN_DIS2IEN
 
- USB_IEN_DISIEN
 
- USB_IEN_INIT
 
- USB_IEN_ITPIEN
 
- USB_IEN_L1ENTIEN
 
- USB_IEN_L1EXTIEN
 
- USB_IEN_L2ENTIEN
 
- USB_IEN_L2EXTIEN
 
- USB_IEN_SPKTIEN
 
- USB_IEN_U1ENTIEN
 
- USB_IEN_U1EXTIEN
 
- USB_IEN_U2ENTIEN
 
- USB_IEN_U2EXTIEN
 
- USB_IEN_U2RESIEN
 
- USB_IEN_U3ENTIEN
 
- USB_IEN_U3EXTIEN
 
- USB_IEN_UHRESIEN
 
- USB_IEN_UWRESEIEN
 
- USB_IEN_UWRESIEN
 
- USB_IEN_UWRESSIEN
 
- USB_IEN_WAKEIEN
 
- USB_IGATE_IGATE_11M_ID
 
- USB_IGATE_VENDOR_ID
 
- USB_ILIM_MASK
 
- USB_ILIM_SHIFT
 
- USB_INT
 
- USB_INTEL_USB2PRM
 
- USB_INTEL_USB3PRM
 
- USB_INTEL_USB3_PSSEN
 
- USB_INTEL_XUSB2PR
 
- USB_INTEN_EHCI
 
- USB_INTEN_FORCE
 
- USB_INTEN_OHCI0
 
- USB_INTEN_OHCI1
 
- USB_INTEN_PHY
 
- USB_INTEN_UDC
 
- USB_INTERFACE_BINDING
 
- USB_INTERFACE_BOUND
 
- USB_INTERFACE_CLASS_CCID
 
- USB_INTERFACE_CLASS_HID
 
- USB_INTERFACE_INFO
 
- USB_INTERFACE_PROTOCOL_KEYBOARD
 
- USB_INTERFACE_PROTOCOL_MOUSE
 
- USB_INTERFACE_SUBCLASS_BOOT
 
- USB_INTERFACE_UNBINDING
 
- USB_INTERFACE_UNBOUND
 
- USB_INTERNAL_REG_1
 
- USB_INTERRUPT_ENABLE
 
- USB_INTRF_FUNC_SUSPEND
 
- USB_INTRF_FUNC_SUSPEND_LP
 
- USB_INTRF_FUNC_SUSPEND_RW
 
- USB_INTRF_STAT_FUNC_RW
 
- USB_INTRF_STAT_FUNC_RW_CAP
 
- USB_INTR_ASYN_ADV_EN
 
- USB_INTR_CONTENT_C2H_OFFSET
 
- USB_INTR_CONTENT_CPWM1_OFFSET
 
- USB_INTR_CONTENT_CPWM2_OFFSET
 
- USB_INTR_CONTENT_HISRE_OFFSET
 
- USB_INTR_CONTENT_HISR_OFFSET
 
- USB_INTR_CONTENT_LENGTH
 
- USB_INTR_CPWM_OFFSET
 
- USB_INTR_DEVICE_SUSPEND
 
- USB_INTR_ERR_INT_EN
 
- USB_INTR_FRM_LST_ROLL_EN
 
- USB_INTR_FUNC_SUSPEND_OPT_MASK
 
- USB_INTR_INT_EN
 
- USB_INTR_OFFSET
 
- USB_INTR_PC_DETECT_EN
 
- USB_INTR_PTC_DETECT_EN
 
- USB_INTR_RESET_EN
 
- USB_INTR_SOF_EN
 
- USB_INTR_SYS_ERR_EN
 
- USB_INT_1_B2_L1SPND
 
- USB_INT_1_B2_RSUM
 
- USB_INT_1_B2_SPND
 
- USB_INT_1_B2_USBRST
 
- USB_INT_1_B3_DISABLE
 
- USB_INT_1_B3_HOTRST
 
- USB_INT_1_B3_LUPSUCS
 
- USB_INT_1_B3_PLLWKUP
 
- USB_INT_1_B3_WRMRST
 
- USB_INT_1_SPEED
 
- USB_INT_1_VBUS_CNG
 
- USB_INT_2_PIPE
 
- USB_INT_EN
 
- USB_INT_ENABLE
 
- USB_INT_EN_BIT
 
- USB_INT_ID_REGS
 
- USB_INT_ID_RETRY_FAILED
 
- USB_INT_READ_REGS_EN
 
- USB_INT_STATUS
 
- USB_INT_STA_RW
 
- USB_INT_TYPE
 
- USB_IN_ACK_RCVD
 
- USB_IN_CLK_ID
 
- USB_IN_NAK_SENT
 
- USB_IN_OT_ID
 
- USB_IPG
 
- USB_IPW_MAGIC
 
- USB_IRDA_AB_0
 
- USB_IRDA_AB_1
 
- USB_IRDA_AB_12
 
- USB_IRDA_AB_2
 
- USB_IRDA_AB_24
 
- USB_IRDA_AB_3
 
- USB_IRDA_AB_48
 
- USB_IRDA_AB_6
 
- USB_IRDA_BR_115200
 
- USB_IRDA_BR_1152000
 
- USB_IRDA_BR_19200
 
- USB_IRDA_BR_2400
 
- USB_IRDA_BR_38400
 
- USB_IRDA_BR_4000000
 
- USB_IRDA_BR_57600
 
- USB_IRDA_BR_576000
 
- USB_IRDA_BR_9600
 
- USB_IRDA_DS_1024
 
- USB_IRDA_DS_128
 
- USB_IRDA_DS_2048
 
- USB_IRDA_DS_256
 
- USB_IRDA_DS_512
 
- USB_IRDA_DS_64
 
- USB_IRDA_EXTRA_BOFS
 
- USB_IRDA_LS_115200
 
- USB_IRDA_LS_1152000
 
- USB_IRDA_LS_19200
 
- USB_IRDA_LS_2400
 
- USB_IRDA_LS_38400
 
- USB_IRDA_LS_4000000
 
- USB_IRDA_LS_57600
 
- USB_IRDA_LS_576000
 
- USB_IRDA_LS_9600
 
- USB_IRDA_LS_NO_CHANGE
 
- USB_IRDA_MTT_0
 
- USB_IRDA_MTT_10
 
- USB_IRDA_MTT_100
 
- USB_IRDA_MTT_1000
 
- USB_IRDA_MTT_10000
 
- USB_IRDA_MTT_50
 
- USB_IRDA_MTT_500
 
- USB_IRDA_MTT_5000
 
- USB_IRDA_RATE_SNIFF
 
- USB_IRDA_STATUS_LINK_SPEED
 
- USB_IRDA_STATUS_MEDIA_BUSY
 
- USB_IRDA_WS_1
 
- USB_IRDA_WS_2
 
- USB_IRDA_WS_3
 
- USB_IRDA_WS_4
 
- USB_IRDA_WS_5
 
- USB_IRDA_WS_6
 
- USB_IRDA_WS_7
 
- USB_IRQ
 
- USB_IRQEN
 
- USB_IRQSTAT
 
- USB_IRQTEST
 
- USB_ISOC
 
- USB_ISTS_CFGRESI
 
- USB_ISTS_CON2I
 
- USB_ISTS_CONI
 
- USB_ISTS_DIS2I
 
- USB_ISTS_DISI
 
- USB_ISTS_ITPI
 
- USB_ISTS_L1ENTI
 
- USB_ISTS_L1EXTI
 
- USB_ISTS_L2ENTI
 
- USB_ISTS_L2EXTI
 
- USB_ISTS_SPKTI
 
- USB_ISTS_U1ENTI
 
- USB_ISTS_U1EXTI
 
- USB_ISTS_U2ENTI
 
- USB_ISTS_U2EXTI
 
- USB_ISTS_U2RESI
 
- USB_ISTS_U3ENTI
 
- USB_ISTS_U3EXTI
 
- USB_ISTS_UHRESI
 
- USB_ISTS_UWRESEI
 
- USB_ISTS_UWRESI
 
- USB_ISTS_UWRESSI
 
- USB_ISTS_WAKEI
 
- USB_IS_FULL_SPEED
 
- USB_IS_HIGH_SPEED
 
- USB_ITPN
 
- USB_ITPN_MASK
 
- USB_IWARN_SD
 
- USB_KEENE_PRODUCT
 
- USB_KEENE_VENDOR
 
- USB_KEYSPAN_PRODUCT_UIA11
 
- USB_KEYSPAN_VENDOR_ID
 
- USB_L1_LPM_HIRD
 
- USB_L1_LPM_REMOTE_WAKE
 
- USB_L1_LPM_SUPPORT
 
- USB_LCD_CONCURRENT_WRITES
 
- USB_LD_MINOR_BASE
 
- USB_LEAF_DEVEL_PRODUCT_ID
 
- USB_LEAF_LIGHT_HS_V2_OEM_PRODUCT_ID
 
- USB_LEAF_LITE_CH_PRODUCT_ID
 
- USB_LEAF_LITE_GI_PRODUCT_ID
 
- USB_LEAF_LITE_PRODUCT_ID
 
- USB_LEAF_LITE_V2_PRODUCT_ID
 
- USB_LEAF_PRO_HS_V2_PRODUCT_ID
 
- USB_LEAF_PRO_LIN_PRODUCT_ID
 
- USB_LEAF_PRO_LS_PRODUCT_ID
 
- USB_LEAF_PRO_OBDII_PRODUCT_ID
 
- USB_LEAF_PRO_PRODUCT_ID
 
- USB_LEAF_PRO_SWC_PRODUCT_ID
 
- USB_LEAF_SPRO_LS_PRODUCT_ID
 
- USB_LEAF_SPRO_PRODUCT_ID
 
- USB_LEAF_SPRO_SWC_PRODUCT_ID
 
- USB_LED_CONTROL
 
- USB_LED_EVENT_GADGET
 
- USB_LED_EVENT_HOST
 
- USB_LEGEND_JOYNET_ID
 
- USB_LEGEND_VENDOR_ID
 
- USB_LINK_ACA_DOCK_CHGR_8505
 
- USB_LINK_ACA_RID_A_8500
 
- USB_LINK_ACA_RID_A_8505
 
- USB_LINK_ACA_RID_B_8500
 
- USB_LINK_ACA_RID_B_8505
 
- USB_LINK_ACA_RID_C_HS_8500
 
- USB_LINK_ACA_RID_C_HS_CHIRP_8500
 
- USB_LINK_ACA_RID_C_NM_8500
 
- USB_LINK_ACA_RID_C_NM_8505
 
- USB_LINK_CARKIT_CHGR_1_8505
 
- USB_LINK_CARKIT_CHGR_2_8505
 
- USB_LINK_CDP_8505
 
- USB_LINK_CHARGERPORT_NOT_OK_8505
 
- USB_LINK_CHARGER_DM_HIGH_8505
 
- USB_LINK_CHARGER_SE1_8505
 
- USB_LINK_DEDICATED_CHG_8500
 
- USB_LINK_DEDICATED_CHG_8505
 
- USB_LINK_HM_IDGND_8500
 
- USB_LINK_HM_IDGND_8505
 
- USB_LINK_HOST_CHG_HS_8500
 
- USB_LINK_HOST_CHG_HS_CHIRP_8500
 
- USB_LINK_HOST_CHG_NM_8500
 
- USB_LINK_MOTOROLA_FACTORY_CBL_PHY_EN_8505
 
- USB_LINK_NOT_CONFIGURED_8500
 
- USB_LINK_NOT_CONFIGURED_8505
 
- USB_LINK_NOT_VALID_LINK_8500
 
- USB_LINK_PHYEN_NO_VBUS_NO_IDGND_8505
 
- USB_LINK_RESERVED0_8505
 
- USB_LINK_RESERVED1_8505
 
- USB_LINK_RESERVED2_8505
 
- USB_LINK_RESERVED3_8505
 
- USB_LINK_RESERVED_8500
 
- USB_LINK_SAMSUNG_BOOT_CBL_PHY_DISB_8505
 
- USB_LINK_SAMSUNG_BOOT_CBL_PHY_EN_8505
 
- USB_LINK_SAMSUNG_UART_CBL_PHY_DISB_8505
 
- USB_LINK_SAMSUNG_UART_CBL_PHY_EN_8505
 
- USB_LINK_STATUS_SHIFT
 
- USB_LINK_STD_HOST_C_NS_8500
 
- USB_LINK_STD_HOST_C_NS_8505
 
- USB_LINK_STD_HOST_C_S_8500
 
- USB_LINK_STD_HOST_C_S_8505
 
- USB_LINK_STD_HOST_NC_8500
 
- USB_LINK_STD_HOST_NC_8505
 
- USB_LINK_STD_UPSTREAM_8505
 
- USB_LINK_STD_UPSTREAM_NO_IDGNG_NO_VBUS_8505
 
- USB_LOW_INTERVALS_PER_SECOND
 
- USB_LOW_ISO_BUFFERS
 
- USB_LOW_SPEED_OPERATION
 
- USB_LPM_BRW
 
- USB_LPM_CONFIG
 
- USB_LPM_CTRL
 
- USB_LPM_HIRD
 
- USB_LPM_HIRD_MASK
 
- USB_LPM_SUPPORT
 
- USB_LTM_SUPPORT
 
- USB_LUCENT_ORINOCO_ID
 
- USB_LUCENT_VENDOR_ID
 
- USB_M105_PRODUCT_ID
 
- USB_M105_VENDOR_ID
 
- USB_MA901_PRODUCT
 
- USB_MA901_VENDOR
 
- USB_MAJOR
 
- USB_MASK
 
- USB_MAXALTSETTING
 
- USB_MAXBUS
 
- USB_MAXCHILDREN
 
- USB_MAXCONFIG
 
- USB_MAXENDPOINTS
 
- USB_MAXIADS
 
- USB_MAXINTERFACES
 
- USB_MAX_CLKS
 
- USB_MAX_CTRL_PAYLOAD
 
- USB_MAX_CURRENT
 
- USB_MAX_ENDPOINTS
 
- USB_MAX_EP_INT_BUFFER
 
- USB_MAX_FRAME_NUMBER
 
- USB_MAX_IOREAD16_COUNT
 
- USB_MAX_IOREAD32_COUNT
 
- USB_MAX_IOWRITE16_COUNT
 
- USB_MAX_IOWRITE32_COUNT
 
- USB_MAX_PIPES
 
- USB_MAX_RETRIES
 
- USB_MAX_RFWRITE_BIT_COUNT
 
- USB_MAX_RX_SIZE
 
- USB_MAX_TRANSFER_SIZE
 
- USB_MCLK_EN
 
- USB_MCLK_EN_BIT
 
- USB_MELCO_VENDOR_ID
 
- USB_MEMO2_DEVEL_PRODUCT_ID
 
- USB_MEMO2_HSHS_PRODUCT_ID
 
- USB_MEMO2_HSLS_PRODUCT_ID
 
- USB_MEMORATOR_PRODUCT_ID
 
- USB_MEMO_2HS_PRODUCT_ID
 
- USB_MEMO_PRO_2HS_V2_PRODUCT_ID
 
- USB_MEMO_PRO_5HS_PRODUCT_ID
 
- USB_MEM_BIST
 
- USB_MEM_READ_MAX
 
- USB_MEM_WRITE_MAX
 
- USB_MENTOR_CORE_OFFSET
 
- USB_MINI_PCIE_2HS_PRODUCT_ID
 
- USB_MINI_PCIE_HS_PRODUCT_ID
 
- USB_MIN_RFWRITE_BIT_COUNT
 
- USB_MIN_VOLT
 
- USB_MISCCONTROL
 
- USB_MISCCONTROL_ARBMODE
 
- USB_MISCCONTROL_FILTCC
 
- USB_MISCCONTROL_ISOPREVFRM
 
- USB_MISCCONTROL_SKPRTRY
 
- USB_MISC_0
 
- USB_MISC_1
 
- USB_MIXER_BOOLEAN
 
- USB_MIXER_INV_BOOLEAN
 
- USB_MIXER_S16
 
- USB_MIXER_S32
 
- USB_MIXER_S8
 
- USB_MIXER_U16
 
- USB_MIXER_U32
 
- USB_MIXER_U8
 
- USB_MLB_PU_PD_CTRL_REG
 
- USB_MODE
 
- USB_MODE_AUTORUN
 
- USB_MODE_CTRL_MODE_DEVICE
 
- USB_MODE_CTRL_MODE_HOST
 
- USB_MODE_CTRL_MODE_IDLE
 
- USB_MODE_CTRL_MODE_MASK
 
- USB_MODE_CTRL_MODE_RSV
 
- USB_MODE_DEVICE
 
- USB_MODE_DISCONNECT
 
- USB_MODE_EN
 
- USB_MODE_ES
 
- USB_MODE_FIRMWARE
 
- USB_MODE_FUNCTION
 
- USB_MODE_HOST
 
- USB_MODE_LSS
 
- USB_MODE_MASK
 
- USB_MODE_RESET
 
- USB_MODE_RESUME
 
- USB_MODE_SDIS
 
- USB_MODE_SETUP_LOCK_OFF
 
- USB_MODE_SFTE
 
- USB_MODE_SLEEP
 
- USB_MODE_STREAM_DISABLE
 
- USB_MODE_TEST
 
- USB_MODE_UNDEFINED
 
- USB_MODE_UNPLUG
 
- USB_MODE_WAKEUP
 
- USB_MSC_TIMER
 
- USB_MSG_TIMEOUT
 
- USB_MSR_ERR
 
- USB_MSR_REG
 
- USB_MST_ID
 
- USB_MS_ELEMENT
 
- USB_MS_EMBEDDED
 
- USB_MS_EXTERNAL
 
- USB_MS_GENERAL
 
- USB_MS_HEADER
 
- USB_MS_MIDI_IN_JACK
 
- USB_MS_MIDI_OUT_JACK
 
- USB_MS_TO_HS_INTERVAL
 
- USB_MTU
 
- USB_MULTI_READ
 
- USB_MULTI_WRITE
 
- USB_NORMAL_SIE_EP_MASK
 
- USB_NORMAL_SIE_EP_SHIFT
 
- USB_NUM_ETD
 
- USB_OC_GPIO
 
- USB_OEM_LEAF_PRODUCT_ID
 
- USB_OEM_MERCURY_PRODUCT_ID
 
- USB_OHCI
 
- USB_OHCI_INTERRUPT1_EN
 
- USB_OHCI_INTERRUPT2_EN
 
- USB_OHCI_INTERRUPT_EN
 
- USB_OHCI_LOADED
 
- USB_OHCI_START
 
- USB_OSIF_PRODUCT_ID
 
- USB_OSIF_VENDOR_ID
 
- USB_OTG_ADP
 
- USB_OTG_ADP_CTRL
 
- USB_OTG_ADP_HIGH
 
- USB_OTG_ADP_LOW
 
- USB_OTG_ADP_RISE
 
- USB_OTG_HNP
 
- USB_OTG_IDMON
 
- USB_OTG_REVISION
 
- USB_OTG_SRP
 
- USB_OTG_STATUS
 
- USB_OUT_ACK_SENT
 
- USB_OUT_CLK_ID
 
- USB_OUT_IT_ID
 
- USB_OUT_NAK_SENT
 
- USB_OUT_PING_NAK_SENT
 
- USB_OVC0_MARK
 
- USB_OVC1_MARK
 
- USB_OVC2_MARK
 
- USB_PAD_CFG
 
- USB_PCWD_PRODUCT_ID
 
- USB_PCWD_VENDOR_ID
 
- USB_PD_ADO_FIXED_BATT_MASK
 
- USB_PD_ADO_FIXED_BATT_SHIFT
 
- USB_PD_ADO_HOT_SWAP_BATT_MASK
 
- USB_PD_ADO_HOT_SWAP_BATT_SHIFT
 
- USB_PD_ADO_TYPE_BATT_STATUS_CHANGE
 
- USB_PD_ADO_TYPE_MASK
 
- USB_PD_ADO_TYPE_OCP
 
- USB_PD_ADO_TYPE_OP_COND_CHANGE
 
- USB_PD_ADO_TYPE_OTP
 
- USB_PD_ADO_TYPE_OVP
 
- USB_PD_ADO_TYPE_SHIFT
 
- USB_PD_ADO_TYPE_SRC_INPUT_CHANGE
 
- USB_PD_BATTERY_INFO_CAPABILITY
 
- USB_PD_CAP_BATTERY_CHARGING
 
- USB_PD_CAP_CHARGING_POLICY
 
- USB_PD_CAP_CONSUMER
 
- USB_PD_CAP_CONSUMER_BC
 
- USB_PD_CAP_CONSUMER_PD
 
- USB_PD_CAP_CONSUMER_TYPE_C
 
- USB_PD_CAP_CONSUMER_UNKNOWN_PEAK_POWER_TIME
 
- USB_PD_CAP_PROVIDER
 
- USB_PD_CAP_PROVIDER_BC
 
- USB_PD_CAP_PROVIDER_PD
 
- USB_PD_CAP_PROVIDER_TYPE_C
 
- USB_PD_CAP_PWR_AC
 
- USB_PD_CAP_PWR_BAT
 
- USB_PD_CAP_PWR_USE_V_BUS
 
- USB_PD_CAP_TYPE_C_CURRENT
 
- USB_PD_CAP_USB_PD
 
- USB_PD_CTRL_MUX_AUTO
 
- USB_PD_CTRL_MUX_COUNT
 
- USB_PD_CTRL_MUX_DOCK
 
- USB_PD_CTRL_MUX_DP
 
- USB_PD_CTRL_MUX_NONE
 
- USB_PD_CTRL_MUX_NO_CHANGE
 
- USB_PD_CTRL_MUX_USB
 
- USB_PD_CTRL_ROLE_COUNT
 
- USB_PD_CTRL_ROLE_FORCE_SINK
 
- USB_PD_CTRL_ROLE_FORCE_SOURCE
 
- USB_PD_CTRL_ROLE_FREEZE
 
- USB_PD_CTRL_ROLE_NO_CHANGE
 
- USB_PD_CTRL_ROLE_TOGGLE_OFF
 
- USB_PD_CTRL_ROLE_TOGGLE_ON
 
- USB_PD_CTRL_SWAP_COUNT
 
- USB_PD_CTRL_SWAP_DATA
 
- USB_PD_CTRL_SWAP_NONE
 
- USB_PD_CTRL_SWAP_POWER
 
- USB_PD_CTRL_SWAP_VCONN
 
- USB_PD_EXT_SDB_DATA_SIZE
 
- USB_PD_EXT_SDB_EVENT_CF_CV_MODE
 
- USB_PD_EXT_SDB_EVENT_FLAGS
 
- USB_PD_EXT_SDB_EVENT_OCP
 
- USB_PD_EXT_SDB_EVENT_OTP
 
- USB_PD_EXT_SDB_EVENT_OVP
 
- USB_PD_EXT_SDB_INTERNAL_TEMP
 
- USB_PD_EXT_SDB_PPS_EVENTS
 
- USB_PD_EXT_SDB_PRESENT_BATT_INPUT
 
- USB_PD_EXT_SDB_PRESENT_INPUT
 
- USB_PD_EXT_SDB_TEMP_STATUS
 
- USB_PD_FW_ERASE_SIG
 
- USB_PD_FW_FLASH_ERASE
 
- USB_PD_FW_FLASH_WRITE
 
- USB_PD_FW_REBOOT
 
- USB_PD_MUX_DP_ENABLED
 
- USB_PD_MUX_HPD_IRQ
 
- USB_PD_MUX_HPD_LVL
 
- USB_PD_MUX_POLARITY_INVERTED
 
- USB_PD_MUX_USB_ENABLED
 
- USB_PD_PD_CONSUMER_PORT_CAPABILITY
 
- USB_PD_PD_PROVIDER_PORT_CAPABILITY
 
- USB_PD_PORT_POWER_DISCONNECTED
 
- USB_PD_PORT_POWER_SINK
 
- USB_PD_PORT_POWER_SINK_NOT_CHARGING
 
- USB_PD_PORT_POWER_SOURCE
 
- USB_PD_POWER_DELIVERY_CAPABILITY
 
- USB_PENC0_MARK
 
- USB_PENC1_MARK
 
- USB_PENC2_MARK
 
- USB_PERIPHERAL
 
- USB_PHY0_RESET
 
- USB_PHY1_RESET
 
- USB_PHYTST
 
- USB_PHYTSTDIS
 
- USB_PHY_0
 
- USB_PHY_ANALOG
 
- USB_PHY_CLK_VALID
 
- USB_PHY_CONTROL1
 
- USB_PHY_CONTROL1_FSEL_MASK
 
- USB_PHY_CONTROL1_FSEL_SHIFT
 
- USB_PHY_CTL_CLOCK
 
- USB_PHY_CTL_PARAM_1
 
- USB_PHY_CTL_PARAM_2
 
- USB_PHY_CTL_PIPE
 
- USB_PHY_CTL_PLL
 
- USB_PHY_CTL_UTMI
 
- USB_PHY_CTRL
 
- USB_PHY_INTERRUPT_EN
 
- USB_PHY_IVREF_CTRL
 
- USB_PHY_PLL
 
- USB_PHY_PLL_CONTROL
 
- USB_PHY_PORT_RESET_0
 
- USB_PHY_PORT_RESET_1
 
- USB_PHY_PWR_CTRL
 
- USB_PHY_RANGE
 
- USB_PHY_RESET
 
- USB_PHY_RX_CTRL
 
- USB_PHY_STATUS
 
- USB_PHY_STATUS_RX_PHY_CLK
 
- USB_PHY_STATUS_RX_UTMI_CLK
 
- USB_PHY_STATUS_VBUS_FAULT
 
- USB_PHY_STRAP_CONTROL
 
- USB_PHY_STRAP_CONTROL_REFCLK_MASK
 
- USB_PHY_STRAP_CONTROL_REFCLK_SHIFT
 
- USB_PHY_TST_GRP_CTRL
 
- USB_PHY_TX_CTRL
 
- USB_PHY_TX_CTRL0
 
- USB_PHY_TX_CTRL1
 
- USB_PHY_TX_CTRL2
 
- USB_PHY_TYPE_DEVICE
 
- USB_PHY_TYPE_HOST
 
- USB_PHY_TYPE_UNDEFINED
 
- USB_PHY_TYPE_USB2
 
- USB_PHY_TYPE_USB3
 
- USB_PHY_UTMI_8B60M
 
- USB_PID_ACK
 
- USB_PID_ADSTECH_USB2_COLD
 
- USB_PID_ADSTECH_USB2_WARM
 
- USB_PID_AFATECH_AF9005
 
- USB_PID_AFATECH_AF9015_9015
 
- USB_PID_AFATECH_AF9015_9016
 
- USB_PID_AFATECH_AF9035_1000
 
- USB_PID_AFATECH_AF9035_1001
 
- USB_PID_AFATECH_AF9035_1002
 
- USB_PID_AFATECH_AF9035_1003
 
- USB_PID_AFATECH_AF9035_9035
 
- USB_PID_AK1
 
- USB_PID_ANSONIC_DVBT_USB
 
- USB_PID_ANYSEE
 
- USB_PID_ARTEC_T14BR
 
- USB_PID_ARTEC_T14_COLD
 
- USB_PID_ARTEC_T14_WARM
 
- USB_PID_ASUS_U3000
 
- USB_PID_ASUS_U3000H
 
- USB_PID_ASUS_U3100
 
- USB_PID_ASUS_U3100MINI_PLUS
 
- USB_PID_AUDIO2DJ
 
- USB_PID_AUDIO4DJ
 
- USB_PID_AUDIO8DJ
 
- USB_PID_AVERMEDIA_1867
 
- USB_PID_AVERMEDIA_A309
 
- USB_PID_AVERMEDIA_A310
 
- USB_PID_AVERMEDIA_A805
 
- USB_PID_AVERMEDIA_A815M
 
- USB_PID_AVERMEDIA_A835
 
- USB_PID_AVERMEDIA_A835B_1835
 
- USB_PID_AVERMEDIA_A835B_2835
 
- USB_PID_AVERMEDIA_A835B_3835
 
- USB_PID_AVERMEDIA_A835B_4835
 
- USB_PID_AVERMEDIA_A850
 
- USB_PID_AVERMEDIA_A850T
 
- USB_PID_AVERMEDIA_A867
 
- USB_PID_AVERMEDIA_B835
 
- USB_PID_AVERMEDIA_DVBT_USB2_COLD
 
- USB_PID_AVERMEDIA_DVBT_USB2_WARM
 
- USB_PID_AVERMEDIA_DVBT_USB_COLD
 
- USB_PID_AVERMEDIA_DVBT_USB_WARM
 
- USB_PID_AVERMEDIA_EXPRESS
 
- USB_PID_AVERMEDIA_H335
 
- USB_PID_AVERMEDIA_HYBRID_ULTRA_USB_M039R
 
- USB_PID_AVERMEDIA_HYBRID_ULTRA_USB_M039R_ATSC
 
- USB_PID_AVERMEDIA_HYBRID_ULTRA_USB_M039R_DVBT
 
- USB_PID_AVERMEDIA_MCE_USB_M038
 
- USB_PID_AVERMEDIA_TD110
 
- USB_PID_AVERMEDIA_TD310
 
- USB_PID_AVERMEDIA_TWINSTAR
 
- USB_PID_AVERMEDIA_VOLAR
 
- USB_PID_AVERMEDIA_VOLAR_2
 
- USB_PID_AVERMEDIA_VOLAR_A868R
 
- USB_PID_AVERMEDIA_VOLAR_X
 
- USB_PID_AVERMEDIA_VOLAR_X_2
 
- USB_PID_AZUREWAVE_6007
 
- USB_PID_AZUREWAVE_AD_TU700
 
- USB_PID_AZUREWAVE_AZ6027
 
- USB_PID_COMPRO_DVBU2000_COLD
 
- USB_PID_COMPRO_DVBU2000_UNK_COLD
 
- USB_PID_COMPRO_DVBU2000_UNK_WARM
 
- USB_PID_COMPRO_DVBU2000_WARM
 
- USB_PID_COMPRO_VIDEOMATE_U500
 
- USB_PID_COMPRO_VIDEOMATE_U500_PC
 
- USB_PID_CONCEPTRONIC_CTVDIGRCU
 
- USB_PID_CONEXANT_D680_DMB
 
- USB_PID_CPYTO_REDI_PC50A
 
- USB_PID_CREATIX_CTX1921
 
- USB_PID_CTVDIGDUAL_V2
 
- USB_PID_DATA0
 
- USB_PID_DATA1
 
- USB_PID_DATA2
 
- USB_PID_DATA_TOGGLE
 
- USB_PID_DELOCK_USB2_DVBT
 
- USB_PID_DIBCOM_ANCHOR_2135_COLD
 
- USB_PID_DIBCOM_HOOK_DEFAULT
 
- USB_PID_DIBCOM_HOOK_DEFAULT_REENUM
 
- USB_PID_DIBCOM_MOD3000_COLD
 
- USB_PID_DIBCOM_MOD3000_WARM
 
- USB_PID_DIBCOM_MOD3001_COLD
 
- USB_PID_DIBCOM_MOD3001_WARM
 
- USB_PID_DIBCOM_NIM7090
 
- USB_PID_DIBCOM_NIM8096MD
 
- USB_PID_DIBCOM_NIM9090M
 
- USB_PID_DIBCOM_NIM9090MD
 
- USB_PID_DIBCOM_STK7070P
 
- USB_PID_DIBCOM_STK7070PD
 
- USB_PID_DIBCOM_STK7700D
 
- USB_PID_DIBCOM_STK7700P
 
- USB_PID_DIBCOM_STK7700P_PC
 
- USB_PID_DIBCOM_STK7700_U7000
 
- USB_PID_DIBCOM_STK7770P
 
- USB_PID_DIBCOM_STK807XP
 
- USB_PID_DIBCOM_STK807XPVR
 
- USB_PID_DIBCOM_STK8096GP
 
- USB_PID_DIBCOM_STK8096PVR
 
- USB_PID_DIBCOM_TFE7090PVR
 
- USB_PID_DIBCOM_TFE7790P
 
- USB_PID_DIBCOM_TFE8096P
 
- USB_PID_DIGITALNOW_BLUEBIRD_DUAL_1_COLD
 
- USB_PID_DIGITALNOW_BLUEBIRD_DUAL_1_WARM
 
- USB_PID_DIGIVOX_MINI_SL_COLD
 
- USB_PID_DIGIVOX_MINI_SL_WARM
 
- USB_PID_DNTV_TINYUSB2_COLD
 
- USB_PID_DNTV_TINYUSB2_WARM
 
- USB_PID_DPOSH_M9206_COLD
 
- USB_PID_DPOSH_M9206_WARM
 
- USB_PID_DTT200U_COLD
 
- USB_PID_DTT200U_WARM
 
- USB_PID_DVB_T_USB_STICK_HIGH_SPEED_COLD
 
- USB_PID_DVB_T_USB_STICK_HIGH_SPEED_WARM
 
- USB_PID_DVICO_BLUEBIRD_DUAL_1_COLD
 
- USB_PID_DVICO_BLUEBIRD_DUAL_1_WARM
 
- USB_PID_DVICO_BLUEBIRD_DUAL_2_COLD
 
- USB_PID_DVICO_BLUEBIRD_DUAL_2_WARM
 
- USB_PID_DVICO_BLUEBIRD_DUAL_4
 
- USB_PID_DVICO_BLUEBIRD_DUAL_4_REV_2
 
- USB_PID_DVICO_BLUEBIRD_DVB_T_NANO_2
 
- USB_PID_DVICO_BLUEBIRD_DVB_T_NANO_2_NFW_WARM
 
- USB_PID_DVICO_BLUEBIRD_LG064F_COLD
 
- USB_PID_DVICO_BLUEBIRD_LG064F_WARM
 
- USB_PID_DVICO_BLUEBIRD_LGDT
 
- USB_PID_DVICO_BLUEBIRD_LGZ201_COLD
 
- USB_PID_DVICO_BLUEBIRD_LGZ201_WARM
 
- USB_PID_DVICO_BLUEBIRD_TH7579_COLD
 
- USB_PID_DVICO_BLUEBIRD_TH7579_WARM
 
- USB_PID_DW2102
 
- USB_PID_DW2104
 
- USB_PID_DW3101
 
- USB_PID_E3C_EC168
 
- USB_PID_E3C_EC168_2
 
- USB_PID_E3C_EC168_3
 
- USB_PID_E3C_EC168_4
 
- USB_PID_E3C_EC168_5
 
- USB_PID_ELGATO_EYETV_DIVERSITY
 
- USB_PID_ELGATO_EYETV_DTT
 
- USB_PID_ELGATO_EYETV_DTT_2
 
- USB_PID_ELGATO_EYETV_DTT_Dlx
 
- USB_PID_ELGATO_EYETV_SAT
 
- USB_PID_ELGATO_EYETV_SAT_V2
 
- USB_PID_ELGATO_EYETV_SAT_V3
 
- USB_PID_ERR
 
- USB_PID_EVOLVEO_XTRATV_STICK
 
- USB_PID_EXT
 
- USB_PID_FORCE
 
- USB_PID_FREECOM_DVBT
 
- USB_PID_FREECOM_DVBT_2
 
- USB_PID_FRIIO_WHITE
 
- USB_PID_GENIUS_TVGO_DVB_T03
 
- USB_PID_GENPIX_8PSK_REV_1_COLD
 
- USB_PID_GENPIX_8PSK_REV_1_WARM
 
- USB_PID_GENPIX_8PSK_REV_2
 
- USB_PID_GENPIX_SKYWALKER_1
 
- USB_PID_GENPIX_SKYWALKER_2
 
- USB_PID_GENPIX_SKYWALKER_CW3K
 
- USB_PID_GIGABYTE_U7000
 
- USB_PID_GIGABYTE_U8000
 
- USB_PID_GOTVIEW_SAT_HD
 
- USB_PID_GRANDTEC_DVBT_USB2_COLD
 
- USB_PID_GRANDTEC_DVBT_USB2_WARM
 
- USB_PID_GRANDTEC_DVBT_USB_COLD
 
- USB_PID_GRANDTEC_DVBT_USB_WARM
 
- USB_PID_GUITARRIGMOBILE
 
- USB_PID_HAMA_DVBT_HYBRID
 
- USB_PID_HANFTEK_UMT_010_COLD
 
- USB_PID_HANFTEK_UMT_010_WARM
 
- USB_PID_HAUPPAUGE_MYTV_T
 
- USB_PID_HAUPPAUGE_NOVA_TD_STICK
 
- USB_PID_HAUPPAUGE_NOVA_TD_STICK_52009
 
- USB_PID_HAUPPAUGE_NOVA_T_500
 
- USB_PID_HAUPPAUGE_NOVA_T_500_2
 
- USB_PID_HAUPPAUGE_NOVA_T_500_3
 
- USB_PID_HAUPPAUGE_NOVA_T_STICK
 
- USB_PID_HAUPPAUGE_NOVA_T_STICK_2
 
- USB_PID_HAUPPAUGE_NOVA_T_STICK_3
 
- USB_PID_HAUPPAUGE_TIGER_ATSC
 
- USB_PID_HAUPPAUGE_TIGER_ATSC_B210
 
- USB_PID_IN
 
- USB_PID_INTEL_CE9500
 
- USB_PID_ITETECH_IT9135
 
- USB_PID_ITETECH_IT9135_9005
 
- USB_PID_ITETECH_IT9135_9006
 
- USB_PID_ITETECH_IT9303
 
- USB_PID_KORECONTROLLER
 
- USB_PID_KORECONTROLLER2
 
- USB_PID_KWORLD_395U
 
- USB_PID_KWORLD_395U_2
 
- USB_PID_KWORLD_395U_3
 
- USB_PID_KWORLD_395U_4
 
- USB_PID_KWORLD_399U
 
- USB_PID_KWORLD_399U_2
 
- USB_PID_KWORLD_MC810
 
- USB_PID_KWORLD_PC160_2T
 
- USB_PID_KWORLD_PC160_T
 
- USB_PID_KWORLD_UB383_T
 
- USB_PID_KWORLD_UB499_2T_T09
 
- USB_PID_KWORLD_VSTREAM_COLD
 
- USB_PID_KWORLD_VSTREAM_WARM
 
- USB_PID_KYE_DVB_T_COLD
 
- USB_PID_KYE_DVB_T_WARM
 
- USB_PID_LIFEVIEW_TV_WALKER_TWIN_COLD
 
- USB_PID_LIFEVIEW_TV_WALKER_TWIN_WARM
 
- USB_PID_LITEON_DVB_T_COLD
 
- USB_PID_LITEON_DVB_T_WARM
 
- USB_PID_MASCHINECONTROLLER
 
- USB_PID_MDATA
 
- USB_PID_MEDION_MD95700
 
- USB_PID_MSI_DIGIVOX_DUO
 
- USB_PID_MSI_DIGI_VOX_MINI_II
 
- USB_PID_MSI_DIGI_VOX_MINI_III
 
- USB_PID_MSI_MEGASKY580
 
- USB_PID_MSI_MEGASKY580_55801
 
- USB_PID_MYGICA_D689
 
- USB_PID_MYGICA_T230
 
- USB_PID_MYGICA_T230C
 
- USB_PID_MYGICA_T230C2
 
- USB_PID_MYGICA_T230C_LITE
 
- USB_PID_NAK
 
- USB_PID_NEBULA_DIGITV
 
- USB_PID_NOXON_DAB_STICK
 
- USB_PID_NOXON_DAB_STICK_REV2
 
- USB_PID_NOXON_DAB_STICK_REV3
 
- USB_PID_NYET
 
- USB_PID_OPERA1_COLD
 
- USB_PID_OPERA1_WARM
 
- USB_PID_OUT
 
- USB_PID_PCTV_2002E
 
- USB_PID_PCTV_2002E_SE
 
- USB_PID_PCTV_200E
 
- USB_PID_PCTV_400E
 
- USB_PID_PCTV_450E
 
- USB_PID_PCTV_452E
 
- USB_PID_PCTV_78E
 
- USB_PID_PCTV_79E
 
- USB_PID_PING
 
- USB_PID_PINNACLE_EXPRESSCARD_320CX
 
- USB_PID_PINNACLE_PCTV2000E
 
- USB_PID_PINNACLE_PCTV282E
 
- USB_PID_PINNACLE_PCTV310E
 
- USB_PID_PINNACLE_PCTV340E
 
- USB_PID_PINNACLE_PCTV340E_SE
 
- USB_PID_PINNACLE_PCTV71E
 
- USB_PID_PINNACLE_PCTV72E
 
- USB_PID_PINNACLE_PCTV73A
 
- USB_PID_PINNACLE_PCTV73E
 
- USB_PID_PINNACLE_PCTV73ESE
 
- USB_PID_PINNACLE_PCTV74E
 
- USB_PID_PINNACLE_PCTV801E
 
- USB_PID_PINNACLE_PCTV801E_SE
 
- USB_PID_PINNACLE_PCTV_DUAL_DIVERSITY_DVB_T
 
- USB_PID_PINNACLE_PCTV_DVB_T_FLASH
 
- USB_PID_PIXELVIEW_SBTVD
 
- USB_PID_PREAMBLE
 
- USB_PID_PROF_1100
 
- USB_PID_REALTEK_RTL2831U
 
- USB_PID_REALTEK_RTL2832U
 
- USB_PID_RIGKONTROL2
 
- USB_PID_RIGKONTROL3
 
- USB_PID_SESSIONIO
 
- USB_PID_SETUP
 
- USB_PID_SIGMATEK_DVB_110
 
- USB_PID_SOF
 
- USB_PID_SONY_PLAYTV
 
- USB_PID_SPLIT
 
- USB_PID_STALL
 
- USB_PID_SVEON_STV20
 
- USB_PID_SVEON_STV20_RTL2832U
 
- USB_PID_SVEON_STV21
 
- USB_PID_SVEON_STV22
 
- USB_PID_SVEON_STV22_IT9137
 
- USB_PID_SVEON_STV27
 
- USB_PID_TECHNISAT_AIRSTAR_TELESTICK_2
 
- USB_PID_TECHNISAT_USB2_CABLESTAR_HDCI
 
- USB_PID_TECHNISAT_USB2_DVB_S2
 
- USB_PID_TECHNISAT_USB2_HDCI_V1
 
- USB_PID_TECHNISAT_USB2_HDCI_V2
 
- USB_PID_TECHNOTREND_CONNECT_CT2_4650_CI
 
- USB_PID_TECHNOTREND_CONNECT_CT2_4650_CI_2
 
- USB_PID_TECHNOTREND_CONNECT_CT3650
 
- USB_PID_TECHNOTREND_CONNECT_S2400
 
- USB_PID_TECHNOTREND_CONNECT_S2400_8KEEPROM
 
- USB_PID_TECHNOTREND_CONNECT_S2_3600
 
- USB_PID_TECHNOTREND_CONNECT_S2_3650_CI
 
- USB_PID_TECHNOTREND_CONNECT_S2_4600
 
- USB_PID_TECHNOTREND_CONNECT_S2_4650_CI
 
- USB_PID_TECHNOTREND_TVSTICK_CT2_4400
 
- USB_PID_TELESTAR_STARSTICK_2
 
- USB_PID_TERRATEC_CINERGY_DT_XS_DIVERSITY
 
- USB_PID_TERRATEC_CINERGY_DT_XS_DIVERSITY_2
 
- USB_PID_TERRATEC_CINERGY_HT_EXPRESS
 
- USB_PID_TERRATEC_CINERGY_HT_USB_XE
 
- USB_PID_TERRATEC_CINERGY_S
 
- USB_PID_TERRATEC_CINERGY_S2_R1
 
- USB_PID_TERRATEC_CINERGY_S2_R2
 
- USB_PID_TERRATEC_CINERGY_S2_R3
 
- USB_PID_TERRATEC_CINERGY_S2_R4
 
- USB_PID_TERRATEC_CINERGY_T_EXPRESS
 
- USB_PID_TERRATEC_CINERGY_T_STICK
 
- USB_PID_TERRATEC_CINERGY_T_STICK_BLACK_REV1
 
- USB_PID_TERRATEC_CINERGY_T_STICK_DUAL_RC
 
- USB_PID_TERRATEC_CINERGY_T_STICK_RC
 
- USB_PID_TERRATEC_CINERGY_T_USB_XE
 
- USB_PID_TERRATEC_CINERGY_T_USB_XE_REV2
 
- USB_PID_TERRATEC_CINERGY_T_XXS
 
- USB_PID_TERRATEC_CINERGY_T_XXS_2
 
- USB_PID_TERRATEC_DVBS2CI_V1
 
- USB_PID_TERRATEC_DVBS2CI_V2
 
- USB_PID_TERRATEC_H7
 
- USB_PID_TERRATEC_H7_2
 
- USB_PID_TERRATEC_H7_3
 
- USB_PID_TERRATEC_T1
 
- USB_PID_TERRATEC_T3
 
- USB_PID_TERRATEC_T5
 
- USB_PID_TEVII_S421
 
- USB_PID_TEVII_S480_1
 
- USB_PID_TEVII_S480_2
 
- USB_PID_TEVII_S630
 
- USB_PID_TEVII_S632
 
- USB_PID_TEVII_S650
 
- USB_PID_TEVII_S660
 
- USB_PID_TEVII_S662
 
- USB_PID_TINYTWIN
 
- USB_PID_TINYTWIN_2
 
- USB_PID_TINYTWIN_3
 
- USB_PID_TRAKTORAUDIO2
 
- USB_PID_TRAKTORKONTROLS4
 
- USB_PID_TRAKTORKONTROLX1
 
- USB_PID_TREKSTOR_DVBT
 
- USB_PID_TREKSTOR_TERRES_2_0
 
- USB_PID_TURBOX_DTT_2000
 
- USB_PID_TVWAY_PLUS
 
- USB_PID_TWINHAN_VP7020_COLD
 
- USB_PID_TWINHAN_VP7020_WARM
 
- USB_PID_TWINHAN_VP7021_COLD
 
- USB_PID_TWINHAN_VP7021_WARM
 
- USB_PID_TWINHAN_VP7041_COLD
 
- USB_PID_TWINHAN_VP7041_WARM
 
- USB_PID_TWINHAN_VP7045_COLD
 
- USB_PID_TWINHAN_VP7045_WARM
 
- USB_PID_TWINHAN_VP7049
 
- USB_PID_ULTIMA_TVBOX_AN2235_COLD
 
- USB_PID_ULTIMA_TVBOX_AN2235_WARM
 
- USB_PID_ULTIMA_TVBOX_ANCHOR_COLD
 
- USB_PID_ULTIMA_TVBOX_COLD
 
- USB_PID_ULTIMA_TVBOX_USB2_COLD
 
- USB_PID_ULTIMA_TVBOX_USB2_FX_COLD
 
- USB_PID_ULTIMA_TVBOX_USB2_FX_WARM
 
- USB_PID_ULTIMA_TVBOX_USB2_WARM
 
- USB_PID_ULTIMA_TVBOX_WARM
 
- USB_PID_UNDEF_0
 
- USB_PID_UNIWILL_STK7700P
 
- USB_PID_UNK_HYPER_PALTEK_COLD
 
- USB_PID_UNK_HYPER_PALTEK_WARM
 
- USB_PID_WINFAST_DTV2000DS
 
- USB_PID_WINFAST_DTV2000DS_PLUS
 
- USB_PID_WINFAST_DTV_DONGLE_COLD
 
- USB_PID_WINFAST_DTV_DONGLE_GOLD
 
- USB_PID_WINFAST_DTV_DONGLE_H
 
- USB_PID_WINFAST_DTV_DONGLE_MINID
 
- USB_PID_WINFAST_DTV_DONGLE_STK7700P
 
- USB_PID_WINFAST_DTV_DONGLE_STK7700P_2
 
- USB_PID_WINFAST_DTV_DONGLE_WARM
 
- USB_PID_WINTV_NOVA_T_USB2_COLD
 
- USB_PID_WINTV_NOVA_T_USB2_WARM
 
- USB_PID_WINTV_SOLOHD
 
- USB_PID_WINTV_SOLOHD_2
 
- USB_PID_WT220U_COLD
 
- USB_PID_WT220U_FC_COLD
 
- USB_PID_WT220U_FC_WARM
 
- USB_PID_WT220U_WARM
 
- USB_PID_WT220U_ZAP250_COLD
 
- USB_PID_WT220U_ZL0353_COLD
 
- USB_PID_WT220U_ZL0353_WARM
 
- USB_PID_XBOX_ONE_TUNER
 
- USB_PID_XTENSIONS_XD_380
 
- USB_PID_YUAN_EC372S
 
- USB_PID_YUAN_MC770
 
- USB_PID_YUAN_PD378S
 
- USB_PID_YUAN_STK7700D
 
- USB_PID_YUAN_STK7700D_2
 
- USB_PID_YUAN_STK7700PH
 
- USB_PKTERR_CNT
 
- USB_PKT_LEN
 
- USB_PLATFORM_DEV
 
- USB_PLAYBACK_RUNNING
 
- USB_PLL_SOURCE_SHIFT
 
- USB_PLUG_CAPTIVE
 
- USB_PLUG_NONE
 
- USB_PLUG_TYPE_A
 
- USB_PLUG_TYPE_B
 
- USB_PLUG_TYPE_C
 
- USB_PM
 
- USB_PM_CTRL_STATUS
 
- USB_PORT_ACCEPT_PD_REQUEST
 
- USB_PORT_CABLE_PD_RESET
 
- USB_PORT_CONNECT_TYPE_HARD_WIRED
 
- USB_PORT_CONNECT_TYPE_HOT_PLUG
 
- USB_PORT_CONNECT_TYPE_UNKNOWN
 
- USB_PORT_C_PORT_PD_CHANGE
 
- USB_PORT_FEAT_BH_PORT_RESET
 
- USB_PORT_FEAT_CONNECTION
 
- USB_PORT_FEAT_C_BH_PORT_RESET
 
- USB_PORT_FEAT_C_CONNECTION
 
- USB_PORT_FEAT_C_ENABLE
 
- USB_PORT_FEAT_C_OVER_CURRENT
 
- USB_PORT_FEAT_C_PORT_CONFIG_ERROR
 
- USB_PORT_FEAT_C_PORT_L1
 
- USB_PORT_FEAT_C_PORT_LINK_STATE
 
- USB_PORT_FEAT_C_RESET
 
- USB_PORT_FEAT_C_SUSPEND
 
- USB_PORT_FEAT_ENABLE
 
- USB_PORT_FEAT_FORCE_LINKPM_ACCEPT
 
- USB_PORT_FEAT_INDICATOR
 
- USB_PORT_FEAT_L1
 
- USB_PORT_FEAT_LINK_STATE
 
- USB_PORT_FEAT_LOWSPEED
 
- USB_PORT_FEAT_OVER_CURRENT
 
- USB_PORT_FEAT_POWER
 
- USB_PORT_FEAT_REMOTE_WAKE_CONNECT
 
- USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT
 
- USB_PORT_FEAT_REMOTE_WAKE_MASK
 
- USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT
 
- USB_PORT_FEAT_RESET
 
- USB_PORT_FEAT_SUSPEND
 
- USB_PORT_FEAT_TEST
 
- USB_PORT_FEAT_U1_TIMEOUT
 
- USB_PORT_FEAT_U2_TIMEOUT
 
- USB_PORT_GOTO_MIN
 
- USB_PORT_LPM_TIMEOUT
 
- USB_PORT_NOT_USED
 
- USB_PORT_PORT_PD_RESET
 
- USB_PORT_PR_SWAP
 
- USB_PORT_QUIRK_FAST_ENUM
 
- USB_PORT_QUIRK_OLD_SCHEME
 
- USB_PORT_REJECT_PD_REQUEST
 
- USB_PORT_RETURN_POWER
 
- USB_PORT_STAT_CONNECTION
 
- USB_PORT_STAT_C_BH_RESET
 
- USB_PORT_STAT_C_CONFIG_ERROR
 
- USB_PORT_STAT_C_CONNECTION
 
- USB_PORT_STAT_C_ENABLE
 
- USB_PORT_STAT_C_L1
 
- USB_PORT_STAT_C_LINK_STATE
 
- USB_PORT_STAT_C_OVERCURRENT
 
- USB_PORT_STAT_C_RESET
 
- USB_PORT_STAT_C_SUSPEND
 
- USB_PORT_STAT_ENABLE
 
- USB_PORT_STAT_HIGH_SPEED
 
- USB_PORT_STAT_INDICATOR
 
- USB_PORT_STAT_L1
 
- USB_PORT_STAT_LINK_STATE
 
- USB_PORT_STAT_LOW_SPEED
 
- USB_PORT_STAT_OVERCURRENT
 
- USB_PORT_STAT_POWER
 
- USB_PORT_STAT_RESET
 
- USB_PORT_STAT_SPEED_5GBPS
 
- USB_PORT_STAT_SUSPEND
 
- USB_PORT_STAT_TEST
 
- USB_POWER_CUT
 
- USB_POWE_TYPE
 
- USB_PRES_INTR_OFFSET
 
- USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0A4A
 
- USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0B4A
 
- USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE
 
- USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE_0641
 
- USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE_0941
 
- USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE_094A
 
- USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE_1f4a
 
- USB_PRODUCT_ID_LAN7500
 
- USB_PRODUCT_ID_LAN7505
 
- USB_PRODUCT_ID_LSB
 
- USB_PRODUCT_ID_MSB
 
- USB_PRODUCT_USB5534B
 
- USB_PR_ALAUDA
 
- USB_PR_BULK
 
- USB_PR_CB
 
- USB_PR_CBI
 
- USB_PR_DATAFAB
 
- USB_PR_DEVICE
 
- USB_PR_DPCM_USB
 
- USB_PR_EUSB_SDDR09
 
- USB_PR_FREECOM
 
- USB_PR_JUMPSHOT
 
- USB_PR_KARMA
 
- USB_PR_SDDR55
 
- USB_PR_UAS
 
- USB_PR_USBAT
 
- USB_PTM_CAP_TYPE
 
- USB_PW_CONN
 
- USB_QMU_RQCPR
 
- USB_QMU_RQCSR
 
- USB_QMU_RQHIAR
 
- USB_QMU_RQSAR
 
- USB_QMU_TQCPR
 
- USB_QMU_TQCSR
 
- USB_QMU_TQHIAR
 
- USB_QMU_TQSAR
 
- USB_QUEUE_BULK
 
- USB_QUIRK_CONFIG_INTF_STRINGS
 
- USB_QUIRK_DELAY_CTRL_MSG
 
- USB_QUIRK_DELAY_INIT
 
- USB_QUIRK_DEVICE_QUALIFIER
 
- USB_QUIRK_DISCONNECT_SUSPEND
 
- USB_QUIRK_ENDPOINT_BLACKLIST
 
- USB_QUIRK_HONOR_BNUMINTERFACES
 
- USB_QUIRK_HUB_SLOW_RESET
 
- USB_QUIRK_IGNORE_REMOTE_WAKEUP
 
- USB_QUIRK_LINEAR_FRAME_INTR_BINTERVAL
 
- USB_QUIRK_LINEAR_UFRAME_INTR_BINTERVAL
 
- USB_QUIRK_NO_LPM
 
- USB_QUIRK_NO_SET_INTF
 
- USB_QUIRK_RESET
 
- USB_QUIRK_RESET_RESUME
 
- USB_QUIRK_STRING_FETCH_255
 
- USB_QoS_CNTL__UnitID0Enable_MASK
 
- USB_QoS_CNTL__UnitID0Enable__SHIFT
 
- USB_QoS_CNTL__UnitID0QoSPriority_MASK
 
- USB_QoS_CNTL__UnitID0QoSPriority__SHIFT
 
- USB_QoS_CNTL__UnitID0_MASK
 
- USB_QoS_CNTL__UnitID0__SHIFT
 
- USB_QoS_CNTL__UnitID1Enable_MASK
 
- USB_QoS_CNTL__UnitID1Enable__SHIFT
 
- USB_QoS_CNTL__UnitID1QoSPriority_MASK
 
- USB_QoS_CNTL__UnitID1QoSPriority__SHIFT
 
- USB_QoS_CNTL__UnitID1_MASK
 
- USB_QoS_CNTL__UnitID1__SHIFT
 
- USB_R0
 
- USB_R0_P30_ACJT_LEVEL_MASK
 
- USB_R0_P30_FSEL_MASK
 
- USB_R0_P30_LANE0_EXT_PCLK_REQ
 
- USB_R0_P30_LANE0_TX2RX_LOOPBACK
 
- USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK
 
- USB_R0_P30_PHY_RESET
 
- USB_R0_P30_TEST_POWERDOWN_HSP
 
- USB_R0_P30_TEST_POWERDOWN_SSP
 
- USB_R0_P30_TX_BOOST_LEVEL_MASK
 
- USB_R0_U2D_ACT
 
- USB_R0_U2D_SS_SCALEDOWN_MODE_MASK
 
- USB_R1
 
- USB_R1_P30_PCS_TX_SWING_FULL_MASK
 
- USB_R1_U3H_BIGENDIAN_GS
 
- USB_R1_U3H_FLADJ_30MHZ_REG_MASK
 
- USB_R1_U3H_HOST_MSI_ENABLE
 
- USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT
 
- USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK
 
- USB_R1_U3H_HOST_U3_PORT_DISABLE
 
- USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK
 
- USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK
 
- USB_R1_U3H_PME_ENABLE
 
- USB_R2
 
- USB_R2_P30_CR_CAP_ADDR
 
- USB_R2_P30_CR_CAP_DATA
 
- USB_R2_P30_CR_DATA_IN_MASK
 
- USB_R2_P30_CR_READ
 
- USB_R2_P30_CR_WRITE
 
- USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK
 
- USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK
 
- USB_R3
 
- USB_R3_P30_LOS_BIAS_MASK
 
- USB_R3_P30_LOS_LEVEL_MASK
 
- USB_R3_P30_MPLL_MULTIPLIER_MASK
 
- USB_R3_P30_REF_SSP_EN
 
- USB_R3_P30_SSC_ENABLE
 
- USB_R3_P30_SSC_RANGE_MASK
 
- USB_R3_P30_SSC_REF_CLK_SEL_MASK
 
- USB_R4
 
- USB_R4_MEM_PD_MASK
 
- USB_R4_P21_ONLY
 
- USB_R4_P21_PORT_RESET_0
 
- USB_R4_P21_SLEEP_M0
 
- USB_R5
 
- USB_R5_ID_DIG_CFG_MASK
 
- USB_R5_ID_DIG_CNT_MASK
 
- USB_R5_ID_DIG_CURR
 
- USB_R5_ID_DIG_EN_0
 
- USB_R5_ID_DIG_EN_1
 
- USB_R5_ID_DIG_IRQ
 
- USB_R5_ID_DIG_REG
 
- USB_R5_ID_DIG_SYNC
 
- USB_R5_ID_DIG_TH_MASK
 
- USB_R6
 
- USB_R6_P30_CR_ACK
 
- USB_R6_P30_CR_DATA_OUT_MASK
 
- USB_READ_COFDM
 
- USB_READ_EEPROM
 
- USB_READ_I2C_CMD
 
- USB_READ_I2C_CMD_LEN
 
- USB_READ_PORT_FAIL
 
- USB_READ_REMOTE
 
- USB_RECIP_DEVICE
 
- USB_RECIP_ENDPOINT
 
- USB_RECIP_INTERFACE
 
- USB_RECIP_MASK
 
- USB_RECIP_OTHER
 
- USB_RECIP_PORT
 
- USB_RECIP_RPIPE
 
- USB_RECV
 
- USB_REFCLK_ISO_EN
 
- USB_REG4
 
- USB_REG_CR
 
- USB_REG_IN_PIPE
 
- USB_REG_OUT_PIPE
 
- USB_REG_RANGE
 
- USB_REG_SWITCH_VID_PID
 
- USB_REQUEST_ION_DIS_INT_TIMER
 
- USB_REQUEST_ION_ENABLE_SUSPEND
 
- USB_REQUEST_ION_EXEC_DL_CODE
 
- USB_REQUEST_ION_GET_EPIC_DESC
 
- USB_REQUEST_ION_READ_RAM
 
- USB_REQUEST_ION_READ_ROM
 
- USB_REQUEST_ION_RECV_IOSP
 
- USB_REQUEST_ION_RESET_DEVICE
 
- USB_REQUEST_ION_SEND_IOSP
 
- USB_REQUEST_ION_WRITE_RAM
 
- USB_REQUEST_ION_WRITE_ROM
 
- USB_REQ_CLEAR_FEATURE
 
- USB_REQ_CS_IRDA_CHECK_MEDIA_BUSY
 
- USB_REQ_CS_IRDA_GET_CLASS_DESC
 
- USB_REQ_CS_IRDA_RATE_SNIFF
 
- USB_REQ_CS_IRDA_RECEIVING
 
- USB_REQ_CS_IRDA_UNICAST_LIST
 
- USB_REQ_DFU_DNLOAD
 
- USB_REQ_EEPROM_END
 
- USB_REQ_EEPROM_MID
 
- USB_REQ_EEPROM_START
 
- USB_REQ_EN_SHIFT
 
- USB_REQ_FIRMWARE_CONFIRM
 
- USB_REQ_FIRMWARE_DOWNLOAD
 
- USB_REQ_FIRMWARE_READ_DATA
 
- USB_REQ_GET_BATTERY_STATUS
 
- USB_REQ_GET_CONFIGURATION
 
- USB_REQ_GET_DESCRIPTOR
 
- USB_REQ_GET_ENCRYPTION
 
- USB_REQ_GET_HANDSHAKE
 
- USB_REQ_GET_INTERFACE
 
- USB_REQ_GET_PARTNER_PDO
 
- USB_REQ_GET_REPORT
 
- USB_REQ_GET_SECURITY_DATA
 
- USB_REQ_GET_STATUS
 
- USB_REQ_GET_VDM
 
- USB_REQ_LOOPBACK_DATA_READ
 
- USB_REQ_LOOPBACK_DATA_WRITE
 
- USB_REQ_PROG_FLASH
 
- USB_REQ_READ_REGS
 
- USB_REQ_RPIPE_ABORT
 
- USB_REQ_RPIPE_RESET
 
- USB_REQ_SEND_VDM
 
- USB_REQ_SET_ADDRESS
 
- USB_REQ_SET_CONFIGURATION
 
- USB_REQ_SET_CONNECTION
 
- USB_REQ_SET_DESCRIPTOR
 
- USB_REQ_SET_ENCRYPTION
 
- USB_REQ_SET_FEATURE
 
- USB_REQ_SET_HANDSHAKE
 
- USB_REQ_SET_INTERFACE
 
- USB_REQ_SET_INTERFACE_DS
 
- USB_REQ_SET_ISOCH_DELAY
 
- USB_REQ_SET_PDO
 
- USB_REQ_SET_REPORT
 
- USB_REQ_SET_SECURITY_DATA
 
- USB_REQ_SET_SEL
 
- USB_REQ_SET_WUSB_DATA
 
- USB_REQ_SYNCH_FRAME
 
- USB_REQ_WRITE_REGS
 
- USB_REQ_WRITE_RF
 
- USB_RESET
 
- USB_RESET_B
 
- USB_RESET_CLKGENRESET
 
- USB_RESET_FORCEHCRESET
 
- USB_RESET_FORCEIFRESET
 
- USB_RESET_PWRCTRLLOW
 
- USB_RESET_PWRSENSELOW
 
- USB_RESET_SIMSCALEDOWN
 
- USB_RESET_SLEEPSTBYEN
 
- USB_RESET_USBINTTEST
 
- USB_RESET_WIDTH
 
- USB_RESP_TIMEOUT
 
- USB_RESUME_TIMEOUT
 
- USB_REVISION_REG
 
- USB_RHS_IGNORE_OUT
 
- USB_RHS_MASK
 
- USB_RHS_NACK
 
- USB_RHS_NORMAL
 
- USB_RHS_SHIFT
 
- USB_RHS_STALL
 
- USB_ROLE_DEVICE
 
- USB_ROLE_HOST
 
- USB_ROLE_NONE
 
- USB_ROOT_PORT_WAKEUP_ENABLE
 
- USB_RR3IIUSB_PRODUCT_ID
 
- USB_RR3USB_PRODUCT_ID
 
- USB_RR3USB_VENDOR_ID
 
- USB_RST
 
- USB_RST_EN
 
- USB_RST_INT
 
- USB_RTHS_MASK
 
- USB_RT_ACM
 
- USB_RT_HUB
 
- USB_RT_PORT
 
- USB_RXERR_CNT
 
- USB_RX_AGG_DISABLE
 
- USB_RX_AGG_DMA
 
- USB_RX_AGG_DMA_USB
 
- USB_RX_AGG_MIX
 
- USB_RX_AGG_USB
 
- USB_RX_BUF_TH
 
- USB_RX_CONTROL
 
- USB_RX_EARLY_SIZE
 
- USB_RX_EARLY_TIMEOUT
 
- USB_RX_EXTRA_AGGR_TMR
 
- USB_S3C2410_DEBUG_LEVEL
 
- USB_SAMSUNG_SEW2001U1_ID
 
- USB_SAMSUNG_SEW2001U2_ID
 
- USB_SAMSUNG_SEW2003U_ID
 
- USB_SAMSUNG_VENDOR_ID
 
- USB_SBUSCFG
 
- USB_SBUSCFG_AHBBRST_INCR16
 
- USB_SBUSCFG_BARD_ALIGN_128B
 
- USB_SBUSCFG_BAWR_ALIGN_128B
 
- USB_SBUSCFG_DEF_VAL
 
- USB_SBUS_CTRL
 
- USB_SBUS_CTRL_SBCA
 
- USB_SC_8020
 
- USB_SC_8070
 
- USB_SC_CYP_ATACB
 
- USB_SC_DEVICE
 
- USB_SC_ISD200
 
- USB_SC_LOCKABLE
 
- USB_SC_QIC
 
- USB_SC_RBC
 
- USB_SC_SCSI
 
- USB_SC_UFI
 
- USB_SELF_POWER
 
- USB_SELF_POWER_VBUS_MAX_DRAW
 
- USB_SEND
 
- USB_SENSORAY_VID
 
- USB_SERIAL_THROTTLED
 
- USB_SERIAL_TTY_MAJOR
 
- USB_SERIAL_TTY_MINORS
 
- USB_SERIAL_WRITE_BUSY
 
- USB_SET_BESL_BASELINE
 
- USB_SET_BESL_DEEP
 
- USB_SET_FIELD32
 
- USB_SG_SIZE
 
- USB_SHUT
 
- USB_SI4713_PRODUCT
 
- USB_SI4713_VENDOR
 
- USB_SID_DISPLAYPORT
 
- USB_SID_MHL
 
- USB_SID_PD
 
- USB_SIE_INTF_ADDR
 
- USB_SIE_INTF_CTRL
 
- USB_SIE_INTF_RD
 
- USB_SIE_INTF_WD
 
- USB_SINGLE_READ
 
- USB_SINGLE_WRITE
 
- USB_SKEL_MINOR_BASE
 
- USB_SKEL_PRODUCT_ID
 
- USB_SKEL_VENDOR_ID
 
- USB_SLBBIST
 
- USB_SLVADDR_MASK
 
- USB_SMI
 
- USB_SOFT_RESET
 
- USB_SOURCE_MAX
 
- USB_SPEC_INT_BULK_SELECT
 
- USB_SPEC_USB_AGG_ENABLE
 
- USB_SPEED
 
- USB_SPEED_FULL
 
- USB_SPEED_HIGH
 
- USB_SPEED_LOW
 
- USB_SPEED_MASK
 
- USB_SPEED_SUPER
 
- USB_SPEED_SUPER_PLUS
 
- USB_SPEED_UNKNOWN
 
- USB_SPEED_WIRELESS
 
- USB_SQUSET
 
- USB_SRP_FIX_TIME_REG
 
- USB_SSPHYLINK1
 
- USB_SSPHYLINK2
 
- USB_SSP_CAP_TYPE
 
- USB_SSP_MIN_RX_LANE_COUNT
 
- USB_SSP_MIN_SUBLINK_SPEED_ATTRIBUTE_ID
 
- USB_SSP_MIN_TX_LANE_COUNT
 
- USB_SSP_SUBLINK_SPEED_ATTRIBS
 
- USB_SSP_SUBLINK_SPEED_IDS
 
- USB_SSP_SUBLINK_SPEED_LP
 
- USB_SSP_SUBLINK_SPEED_LSE
 
- USB_SSP_SUBLINK_SPEED_LSM
 
- USB_SSP_SUBLINK_SPEED_RSVD
 
- USB_SSP_SUBLINK_SPEED_SSID
 
- USB_SSP_SUBLINK_SPEED_ST
 
- USB_SS_CAP_TYPE
 
- USB_SS_MAXPORTS
 
- USB_SS_MULT
 
- USB_SS_PHY
 
- USB_SS_PORT_LS_COMP_MOD
 
- USB_SS_PORT_LS_HOT_RESET
 
- USB_SS_PORT_LS_LOOPBACK
 
- USB_SS_PORT_LS_POLLING
 
- USB_SS_PORT_LS_RECOVERY
 
- USB_SS_PORT_LS_RX_DETECT
 
- USB_SS_PORT_LS_SS_DISABLED
 
- USB_SS_PORT_LS_SS_INACTIVE
 
- USB_SS_PORT_LS_U0
 
- USB_SS_PORT_LS_U1
 
- USB_SS_PORT_LS_U2
 
- USB_SS_PORT_LS_U3
 
- USB_SS_PORT_STAT_MASK
 
- USB_SS_PORT_STAT_POWER
 
- USB_SS_PORT_STAT_SPEED
 
- USB_SS_SSP_ISOC_COMP
 
- USB_STALL_SENT
 
- USB_STAT
 
- USB_STATE_ADDRESS
 
- USB_STATE_ATTACHED
 
- USB_STATE_CONFIGURED
 
- USB_STATE_DEFAULT
 
- USB_STATE_INIT
 
- USB_STATE_NOTATTACHED
 
- USB_STATE_POWERED
 
- USB_STATE_RECONNECTING
 
- USB_STATE_START
 
- USB_STATE_STOP
 
- USB_STATE_SUSPENDED
 
- USB_STATE_UNAUTHENTICATED
 
- USB_STATE_URB_BUF
 
- USB_STATUS
 
- USB_STATUS_FUNC_REMOTE_WK_
 
- USB_STATUS_FUNC_REMOTE_WK_STS_
 
- USB_STATUS_IRQHCIBUFFACC
 
- USB_STATUS_IRQHCIRMTWKUP
 
- USB_STATUS_LTM_ENABLE_
 
- USB_STATUS_LTM_ENABLE_STS_
 
- USB_STATUS_NHCIMFCLR
 
- USB_STATUS_NIRQHCIM
 
- USB_STATUS_REMOTE_WK_
 
- USB_STATUS_REMOTE_WK_STS_
 
- USB_STATUS_SET_SEL_
 
- USB_STATUS_TYPE_PTM
 
- USB_STATUS_TYPE_STANDARD
 
- USB_STATUS_U1_ENABLE_
 
- USB_STATUS_U1_ENABLE_STS_
 
- USB_STATUS_U2_ENABLE_
 
- USB_STATUS_U2_ENABLE_STS_
 
- USB_STATUS_USBPWRSENSE
 
- USB_STAT_ACA_DOCK_CHARGER
 
- USB_STAT_ACA_RID_A
 
- USB_STAT_ACA_RID_B
 
- USB_STAT_ACA_RID_C_HS
 
- USB_STAT_ACA_RID_C_HS_CHIRP
 
- USB_STAT_ACA_RID_C_NM
 
- USB_STAT_BUS_STAT_ATHD
 
- USB_STAT_BUS_STAT_CONF
 
- USB_STAT_BUS_STAT_CONN
 
- USB_STAT_BUS_STAT_MASK
 
- USB_STAT_BUS_STAT_SHIFT
 
- USB_STAT_BUS_STAT_SUSP
 
- USB_STAT_CARKIT_1
 
- USB_STAT_CARKIT_2
 
- USB_STAT_CHARGER_LINE_1
 
- USB_STAT_DBP_UNCFG
 
- USB_STAT_DEAD_BAT_DET
 
- USB_STAT_DEDICATED_CHG
 
- USB_STAT_HM_IDGND
 
- USB_STAT_HOST_CHG_HS
 
- USB_STAT_HOST_CHG_HS_CHIRP
 
- USB_STAT_HOST_CHG_NM
 
- USB_STAT_NOT_CONFIGURED
 
- USB_STAT_NOT_VALID_LINK
 
- USB_STAT_PHY_EN
 
- USB_STAT_REG
 
- USB_STAT_RESERVED
 
- USB_STAT_STD_HOST_C_NS
 
- USB_STAT_STD_HOST_C_S
 
- USB_STAT_STD_HOST_NC
 
- USB_STAT_SUP_IDGND_VBUS
 
- USB_STAT_SUP_NO_IDGND_VBUS
 
- USB_STAT_USB_SS_MODE
 
- USB_STA_SPEED_FS
 
- USB_STA_SPEED_HS
 
- USB_STA_SPEED_MASK
 
- USB_STA_SPEED_SS
 
- USB_STA_VBUS_STA
 
- USB_STORAGE_COMMON_H
 
- USB_STOR_STRING_LEN
 
- USB_STOR_TRANSPORT_ERROR
 
- USB_STOR_TRANSPORT_FAILED
 
- USB_STOR_TRANSPORT_GOOD
 
- USB_STOR_TRANSPORT_NO_SENSE
 
- USB_STOR_XFER_ERROR
 
- USB_STOR_XFER_GOOD
 
- USB_STOR_XFER_LONG
 
- USB_STOR_XFER_SHORT
 
- USB_STOR_XFER_STALLED
 
- USB_STREAMZAP_PRODUCT_ID
 
- USB_STREAMZAP_VENDOR_ID
 
- USB_STREAM_INTERFACE_VERSION
 
- USB_STREAM_NURBS
 
- USB_STREAM_URBDEPTH
 
- USB_STS_ADDRESSED
 
- USB_STS_ADDRESSED_MASK
 
- USB_STS_ASYNC_SCHEDULE
 
- USB_STS_CFGSTS
 
- USB_STS_CFGSTS_MASK
 
- USB_STS_CLK2OFF
 
- USB_STS_CLK2OFF_MASK
 
- USB_STS_CLK3OFF
 
- USB_STS_CLK3OFF_MASK
 
- USB_STS_DCSUSPEND
 
- USB_STS_DEVS
 
- USB_STS_DEVS_MASK
 
- USB_STS_DISABLE_HS
 
- USB_STS_DISABLE_HS_MASK
 
- USB_STS_DMAOFF
 
- USB_STS_DMAOFF_MASK
 
- USB_STS_DNFW_INT
 
- USB_STS_DNLTM_BELT
 
- USB_STS_DTRANS
 
- USB_STS_DTRANS_MASK
 
- USB_STS_ENDIAN
 
- USB_STS_ENDIAN2
 
- USB_STS_ENDIAN2_MASK
 
- USB_STS_ENDIAN_MASK
 
- USB_STS_ERR
 
- USB_STS_FRM_LST_ROLL
 
- USB_STS_FS
 
- USB_STS_HC_HALTED
 
- USB_STS_HS
 
- USB_STS_IAA
 
- USB_STS_INT
 
- USB_STS_IN_RST
 
- USB_STS_IN_RST_MASK
 
- USB_STS_L1ENS
 
- USB_STS_L1ENS_MASK
 
- USB_STS_LPMST_MASK
 
- USB_STS_LS
 
- USB_STS_LST_MASK
 
- USB_STS_OV
 
- USB_STS_OV_MASK
 
- USB_STS_PERIODIC_SCHEDULE
 
- USB_STS_PORT_CHANGE
 
- USB_STS_RCL
 
- USB_STS_RESET
 
- USB_STS_RESET_RECEIVED
 
- USB_STS_RETRIES
 
- USB_STS_SOF
 
- USB_STS_SS
 
- USB_STS_SUSPEND
 
- USB_STS_SYS_ERR
 
- USB_STS_TDL_TRB_ENABLED
 
- USB_STS_TIMEOUT
 
- USB_STS_TMODE_SEL
 
- USB_STS_TMODE_SEL_MASK
 
- USB_STS_U1ENS
 
- USB_STS_U1ENS_MASK
 
- USB_STS_U2ENS
 
- USB_STS_U2ENS_MASK
 
- USB_STS_USB2CONS
 
- USB_STS_USB2CONS_MASK
 
- USB_STS_USB3CONS
 
- USB_STS_USB3CONS_MASK
 
- USB_STS_USBSPEED
 
- USB_STS_USBSPEED_MASK
 
- USB_STS_VBUSS
 
- USB_STS_VBUSS_MASK
 
- USB_SUBCLASS_AUDIOCONTROL
 
- USB_SUBCLASS_AUDIOSTREAMING
 
- USB_SUBCLASS_IRDA
 
- USB_SUBCLASS_MIDISTREAMING
 
- USB_SUBCLASS_VENDOR_SPEC
 
- USB_SUSEN
 
- USB_SUSPEND_TIME
 
- USB_SUSP_CLR
 
- USB_SUSP_CTRL
 
- USB_SUSP_SET
 
- USB_SW_DRV_NAME
 
- USB_SW_RESOURCE_SIZE
 
- USB_SX303_PRODUCT_ID
 
- USB_SX353_PRODUCT_ID
 
- USB_SYSCTL
 
- USB_SYSCTL_0
 
- USB_SYSCTL_1
 
- USB_SYSCTL_2
 
- USB_SYSCTL_3
 
- USB_TCXO_EN
 
- USB_TDOWN
 
- USB_TD_ERROR
 
- USB_TD_INPROGRESS
 
- USB_TD_OK
 
- USB_TD_RX_DATA_OVERUN
 
- USB_TD_RX_DATA_UNDERUN
 
- USB_TD_RX_ER_BITSTUFF
 
- USB_TD_RX_ER_CRC
 
- USB_TD_RX_ER_NONOCT
 
- USB_TD_RX_ER_OVERUN
 
- USB_TD_RX_ER_PID
 
- USB_TD_TOGGLE_CARRY
 
- USB_TD_TOGGLE_DATA0
 
- USB_TD_TOGGLE_DATA1
 
- USB_TD_TX_ER_NAK
 
- USB_TD_TX_ER_STALL
 
- USB_TD_TX_ER_TIMEOUT
 
- USB_TD_TX_ER_UNDERUN
 
- USB_TEARDOWN_REG
 
- USB_TEST
 
- USB_TEST_EP_MASK
 
- USB_TEST_EP_SHIFT
 
- USB_TEST_MODE
 
- USB_THS_IGNORE_IN
 
- USB_THS_MASK
 
- USB_THS_NACK
 
- USB_THS_NORMAL
 
- USB_THS_SHIFT
 
- USB_THS_STALL
 
- USB_TIMEOUT
 
- USB_TOLERANCE
 
- USB_TOUT_VAL
 
- USB_TP_TRANSMISSION_DELAY
 
- USB_TP_TRANSMISSION_DELAY_MAX
 
- USB_TRACE
 
- USB_TRANSCEIVER_CTRL
 
- USB_TRANS_BULK
 
- USB_TRANS_CTR
 
- USB_TRANS_INT
 
- USB_TRANS_ISO
 
- USB_TRANS_MODE_SHIFT
 
- USB_TSD_MASK
 
- USB_TSD_SHIFT
 
- USB_TSTCTL
 
- USB_TSTCTL2
 
- USB_TWARN_MASK
 
- USB_TWARN_SHIFT
 
- USB_TXAGG_NUM_SHT
 
- USB_TX_AGG
 
- USB_TX_DMA
 
- USB_TX_TIMEOUT
 
- USB_TYPEC_DP_MODE
 
- USB_TYPEC_DP_SID
 
- USB_TYPEC_NVIDIA_VLINK_SID
 
- USB_TYPEC_REV_1_0
 
- USB_TYPEC_REV_1_1
 
- USB_TYPEC_REV_1_2
 
- USB_TYPE_CLASS
 
- USB_TYPE_MASK
 
- USB_TYPE_OPTION_VENDOR
 
- USB_TYPE_RESERVED
 
- USB_TYPE_STANDARD
 
- USB_TYPE_VENDOR
 
- USB_U1U2_TIMER
 
- USB_U2P3_CTRL
 
- USB_UDC_ATTR
 
- USB_UDC_SPEED_ATTR
 
- USB_UHCI_LOADED
 
- USB_UPRO_HSHS_PRODUCT_ID
 
- USB_UPS_CFG
 
- USB_UPS_CTRL
 
- USB_UPS_FLAGS
 
- USB_UPT_RXDMA_OWN
 
- USB_USB2PHY
 
- USB_USBCAN2_PRODUCT_ID
 
- USB_USBCAN_LIGHT_2HS_PRODUCT_ID
 
- USB_USBCAN_LIGHT_4HS_PRODUCT_ID
 
- USB_USBCAN_PRO_2HS_V2_PRODUCT_ID
 
- USB_USBCAN_PRO_5HS_PRODUCT_ID
 
- USB_USBCAN_REVB_PRODUCT_ID
 
- USB_USBHSC
 
- USB_USBI0
 
- USB_USBI1
 
- USB_USBMODE
 
- USB_USBMODE_DEVICE
 
- USB_USBMODE_HOST
 
- USB_USBMODE_MASK
 
- USB_USB_CTRL
 
- USB_USB_TIMER
 
- USB_USFRN_MASK
 
- USB_USI0
 
- USB_USSFT_MASK
 
- USB_UTMI_STATUS
 
- USB_UTMI_TST
 
- USB_VBUS_CTRL_CLR
 
- USB_VBUS_CTRL_SET
 
- USB_VBUS_INT_EN_HI_CLR
 
- USB_VBUS_INT_EN_HI_SET
 
- USB_VBUS_INT_EN_LO_CLR
 
- USB_VBUS_INT_EN_LO_SET
 
- USB_VBUS_INT_LATCH_CLR
 
- USB_VBUS_INT_LATCH_SET
 
- USB_VBUS_INT_SRC
 
- USB_VBUS_MARK
 
- USB_VBUS_TIMER
 
- USB_VCI2_PRODUCT_ID
 
- USB_VDRCTRL
 
- USB_VENDER_ID_REALTEK
 
- USB_VENDOR_AND_INTERFACE_INFO
 
- USB_VENDOR_APPLE
 
- USB_VENDOR_GENESYS_LOGIC
 
- USB_VENDOR_ID_258A
 
- USB_VENDOR_ID_3M
 
- USB_VENDOR_ID_A4TECH
 
- USB_VENDOR_ID_AASHIMA
 
- USB_VENDOR_ID_ACECAD
 
- USB_VENDOR_ID_ACRUX
 
- USB_VENDOR_ID_ACTIONSTAR
 
- USB_VENDOR_ID_ADS_TECH
 
- USB_VENDOR_ID_AFATECH
 
- USB_VENDOR_ID_AIPTEK
 
- USB_VENDOR_ID_AIRCABLE
 
- USB_VENDOR_ID_AIREN
 
- USB_VENDOR_ID_AKAI
 
- USB_VENDOR_ID_AKAI_09E8
 
- USB_VENDOR_ID_ALCOR
 
- USB_VENDOR_ID_ALPS
 
- USB_VENDOR_ID_ALPS_JP
 
- USB_VENDOR_ID_AMI
 
- USB_VENDOR_ID_ANTON
 
- USB_VENDOR_ID_APPLE
 
- USB_VENDOR_ID_ASUS
 
- USB_VENDOR_ID_ASUSTEK
 
- USB_VENDOR_ID_ATEN
 
- USB_VENDOR_ID_ATENINTL
 
- USB_VENDOR_ID_ATMEL
 
- USB_VENDOR_ID_ATMEL_V_USB
 
- USB_VENDOR_ID_AUREAL
 
- USB_VENDOR_ID_AVERMEDIA
 
- USB_VENDOR_ID_AXENTIA
 
- USB_VENDOR_ID_AXIOHM
 
- USB_VENDOR_ID_BAANTO
 
- USB_VENDOR_ID_BANDB
 
- USB_VENDOR_ID_BELKIN
 
- USB_VENDOR_ID_BERKSHIRE
 
- USB_VENDOR_ID_BETOP_2185BFM
 
- USB_VENDOR_ID_BETOP_2185PC
 
- USB_VENDOR_ID_BETOP_2185V2BFM
 
- USB_VENDOR_ID_BETOP_2185V2PC
 
- USB_VENDOR_ID_BIGBEN
 
- USB_VENDOR_ID_BTC
 
- USB_VENDOR_ID_CANDO
 
- USB_VENDOR_ID_CH
 
- USB_VENDOR_ID_CHERRY
 
- USB_VENDOR_ID_CHIC
 
- USB_VENDOR_ID_CHICONY
 
- USB_VENDOR_ID_CHUNGHWAT
 
- USB_VENDOR_ID_CIDC
 
- USB_VENDOR_ID_CJTOUCH
 
- USB_VENDOR_ID_CMEDIA
 
- USB_VENDOR_ID_CODEMERCS
 
- USB_VENDOR_ID_CORSAIR
 
- USB_VENDOR_ID_CREATIVELABS
 
- USB_VENDOR_ID_CVTOUCH
 
- USB_VENDOR_ID_CYGNAL
 
- USB_VENDOR_ID_CYPRESS
 
- USB_VENDOR_ID_DATA_MODUL
 
- USB_VENDOR_ID_DATA_MODUL_EASYMAXTOUCH
 
- USB_VENDOR_ID_DEALEXTREAME
 
- USB_VENDOR_ID_DELCOM
 
- USB_VENDOR_ID_DELL
 
- USB_VENDOR_ID_DELORME
 
- USB_VENDOR_ID_DIOLAN
 
- USB_VENDOR_ID_DMI
 
- USB_VENDOR_ID_DRACAL_RAPHNET
 
- USB_VENDOR_ID_DRAGONRISE
 
- USB_VENDOR_ID_DREAM_CHEEKY
 
- USB_VENDOR_ID_DWAV
 
- USB_VENDOR_ID_ELAN
 
- USB_VENDOR_ID_ELECOM
 
- USB_VENDOR_ID_ELITEGROUP
 
- USB_VENDOR_ID_ELO
 
- USB_VENDOR_ID_EMS
 
- USB_VENDOR_ID_ESSENTIAL_REALITY
 
- USB_VENDOR_ID_ETT
 
- USB_VENDOR_ID_ETURBOTOUCH
 
- USB_VENDOR_ID_EZKEY
 
- USB_VENDOR_ID_FLATFROG
 
- USB_VENDOR_ID_FORMOSA
 
- USB_VENDOR_ID_FREESCALE
 
- USB_VENDOR_ID_FRUCTEL
 
- USB_VENDOR_ID_FUTABA
 
- USB_VENDOR_ID_FUTURE_TECHNOLOGY
 
- USB_VENDOR_ID_GAMERON
 
- USB_VENDOR_ID_GEMBIRD
 
- USB_VENDOR_ID_GENERAL_TOUCH
 
- USB_VENDOR_ID_GOODTOUCH
 
- USB_VENDOR_ID_GOOGLE
 
- USB_VENDOR_ID_GOTOP
 
- USB_VENDOR_ID_GREENASIA
 
- USB_VENDOR_ID_GRETAGMACBETH
 
- USB_VENDOR_ID_GRIFFIN
 
- USB_VENDOR_ID_GTCO
 
- USB_VENDOR_ID_GYRATION
 
- USB_VENDOR_ID_HANVON
 
- USB_VENDOR_ID_HANVON_ALT
 
- USB_VENDOR_ID_HANWANG
 
- USB_VENDOR_ID_HAPP
 
- USB_VENDOR_ID_HOLTEK
 
- USB_VENDOR_ID_HOLTEK_ALT
 
- USB_VENDOR_ID_HP
 
- USB_VENDOR_ID_HUION
 
- USB_VENDOR_ID_IBM
 
- USB_VENDOR_ID_IDEACOM
 
- USB_VENDOR_ID_ILITEK
 
- USB_VENDOR_ID_IMATION
 
- USB_VENDOR_ID_INNOMEDIA
 
- USB_VENDOR_ID_INTEL_0
 
- USB_VENDOR_ID_INTEL_1
 
- USB_VENDOR_ID_ION
 
- USB_VENDOR_ID_IRTOUCHSYSTEMS
 
- USB_VENDOR_ID_ITE
 
- USB_VENDOR_ID_JABRA
 
- USB_VENDOR_ID_JESS
 
- USB_VENDOR_ID_JESS2
 
- USB_VENDOR_ID_KBGEAR
 
- USB_VENDOR_ID_KENSINGTON
 
- USB_VENDOR_ID_KEYTOUCH
 
- USB_VENDOR_ID_KWORLD
 
- USB_VENDOR_ID_KYE
 
- USB_VENDOR_ID_LABTEC
 
- USB_VENDOR_ID_LCPOWER
 
- USB_VENDOR_ID_LD
 
- USB_VENDOR_ID_LENOVO
 
- USB_VENDOR_ID_LG
 
- USB_VENDOR_ID_LOGITECH
 
- USB_VENDOR_ID_LSB
 
- USB_VENDOR_ID_LUMIO
 
- USB_VENDOR_ID_MADCATZ
 
- USB_VENDOR_ID_MCC
 
- USB_VENDOR_ID_MCS
 
- USB_VENDOR_ID_MGE
 
- USB_VENDOR_ID_MICROCHIP
 
- USB_VENDOR_ID_MICROSOFT
 
- USB_VENDOR_ID_MOJO
 
- USB_VENDOR_ID_MONTEREY
 
- USB_VENDOR_ID_MOSCHIP
 
- USB_VENDOR_ID_MOXA
 
- USB_VENDOR_ID_MSB
 
- USB_VENDOR_ID_MSI
 
- USB_VENDOR_ID_MULTIPLE_1781
 
- USB_VENDOR_ID_NATIONAL_SEMICONDUCTOR
 
- USB_VENDOR_ID_NATSU
 
- USB_VENDOR_ID_NCR
 
- USB_VENDOR_ID_NEC
 
- USB_VENDOR_ID_NEXIO
 
- USB_VENDOR_ID_NEXTWINDOW
 
- USB_VENDOR_ID_NINTENDO
 
- USB_VENDOR_ID_NOVATEK
 
- USB_VENDOR_ID_NTI
 
- USB_VENDOR_ID_NTRIG
 
- USB_VENDOR_ID_ONTRAK
 
- USB_VENDOR_ID_ORTEK
 
- USB_VENDOR_ID_PANASONIC
 
- USB_VENDOR_ID_PANJIT
 
- USB_VENDOR_ID_PANTHERLORD
 
- USB_VENDOR_ID_PEGASUSTECH
 
- USB_VENDOR_ID_PENMOUNT
 
- USB_VENDOR_ID_PETALYNX
 
- USB_VENDOR_ID_PETZL
 
- USB_VENDOR_ID_PHILIPS
 
- USB_VENDOR_ID_PIXART
 
- USB_VENDOR_ID_PI_ENGINEERING
 
- USB_VENDOR_ID_PLANTRONICS
 
- USB_VENDOR_ID_PLAYDOTCOM
 
- USB_VENDOR_ID_POWERCOM
 
- USB_VENDOR_ID_PRIMAX
 
- USB_VENDOR_ID_PRODIGE
 
- USB_VENDOR_ID_QUANTA
 
- USB_VENDOR_ID_QUATECH
 
- USB_VENDOR_ID_RAZER
 
- USB_VENDOR_ID_REALTEK
 
- USB_VENDOR_ID_RETROUSB
 
- USB_VENDOR_ID_RISO_KAGAKU
 
- USB_VENDOR_ID_ROCCAT
 
- USB_VENDOR_ID_SAITEK
 
- USB_VENDOR_ID_SAMSUNG
 
- USB_VENDOR_ID_SEMICO
 
- USB_VENDOR_ID_SENNHEISER
 
- USB_VENDOR_ID_SIGMATEL
 
- USB_VENDOR_ID_SIGMA_MICRO
 
- USB_VENDOR_ID_SIGNOTEC
 
- USB_VENDOR_ID_SINO_LITE
 
- USB_VENDOR_ID_SIS_TOUCH
 
- USB_VENDOR_ID_SKYCABLE
 
- USB_VENDOR_ID_SMK
 
- USB_VENDOR_ID_SMSC
 
- USB_VENDOR_ID_SOLID_YEAR
 
- USB_VENDOR_ID_SONY
 
- USB_VENDOR_ID_SOUNDGRAPH
 
- USB_VENDOR_ID_STANTUM
 
- USB_VENDOR_ID_STANTUM_SITRONIX
 
- USB_VENDOR_ID_STANTUM_STM
 
- USB_VENDOR_ID_STEELSERIES
 
- USB_VENDOR_ID_STM_0
 
- USB_VENDOR_ID_SUN
 
- USB_VENDOR_ID_SUNPLUS
 
- USB_VENDOR_ID_SYMBOL
 
- USB_VENDOR_ID_SYNAPTICS
 
- USB_VENDOR_ID_TEXAS_INSTRUMENTS
 
- USB_VENDOR_ID_THINGM
 
- USB_VENDOR_ID_THQ
 
- USB_VENDOR_ID_THRUSTMASTER
 
- USB_VENDOR_ID_TI
 
- USB_VENDOR_ID_TIVO
 
- USB_VENDOR_ID_TOPMAX
 
- USB_VENDOR_ID_TOPSEED
 
- USB_VENDOR_ID_TOPSEED2
 
- USB_VENDOR_ID_TOUCHPACK
 
- USB_VENDOR_ID_TOUCH_INTL
 
- USB_VENDOR_ID_TPV
 
- USB_VENDOR_ID_TURBOX
 
- USB_VENDOR_ID_TWINHAN
 
- USB_VENDOR_ID_UCLOGIC
 
- USB_VENDOR_ID_UGEE
 
- USB_VENDOR_ID_UGTIZER
 
- USB_VENDOR_ID_UNITEC
 
- USB_VENDOR_ID_VALVE
 
- USB_VENDOR_ID_VELLEMAN
 
- USB_VENDOR_ID_VIEWSONIC
 
- USB_VENDOR_ID_VTL
 
- USB_VENDOR_ID_WACOM
 
- USB_VENDOR_ID_WALTOP
 
- USB_VENDOR_ID_WEIDA
 
- USB_VENDOR_ID_WISEGROUP
 
- USB_VENDOR_ID_WISEGROUP_LTD
 
- USB_VENDOR_ID_WISEGROUP_LTD2
 
- USB_VENDOR_ID_WISTRON
 
- USB_VENDOR_ID_XAT
 
- USB_VENDOR_ID_XIN_MO
 
- USB_VENDOR_ID_XIROKU
 
- USB_VENDOR_ID_X_TENSIONS
 
- USB_VENDOR_ID_YEALINK
 
- USB_VENDOR_ID_ZEROPLUS
 
- USB_VENDOR_ID_ZYDACRON
 
- USB_VENDOR_ID_ZYTRONIC
 
- USB_VENDOR_REGISTER_READ
 
- USB_VENDOR_REGISTER_WRITE
 
- USB_VENDOR_REQUEST
 
- USB_VENDOR_REQUEST_GET_STATS
 
- USB_VENDOR_REQUEST_IN
 
- USB_VENDOR_REQUEST_OUT
 
- USB_VENDOR_REQUEST_READ_REGISTER
 
- USB_VENDOR_REQUEST_WRITE_REGISTER
 
- USB_VENDOR_SMSC
 
- USB_VEN_REQ_CMD_FAIL
 
- USB_VERSION
 
- USB_VID_774
 
- USB_VID_ADSTECH
 
- USB_VID_AFATECH
 
- USB_VID_ALCOR_MICRO
 
- USB_VID_ALINK
 
- USB_VID_ALINK_DTU
 
- USB_VID_AMT
 
- USB_VID_ANCHOR
 
- USB_VID_ANSONIC
 
- USB_VID_ANUBIS_ELECTRONIC
 
- USB_VID_ASUS
 
- USB_VID_AVERMEDIA
 
- USB_VID_AZUREWAVE
 
- USB_VID_COMPRO
 
- USB_VID_COMPRO_UNK
 
- USB_VID_CONEXANT
 
- USB_VID_CYPRESS
 
- USB_VID_DEXATEK
 
- USB_VID_DIBCOM
 
- USB_VID_DPOSH
 
- USB_VID_DVICO
 
- USB_VID_E3C
 
- USB_VID_ELGATO
 
- USB_VID_EMPIA
 
- USB_VID_EVOLUTEPC
 
- USB_VID_GENPIX
 
- USB_VID_GIGABYTE
 
- USB_VID_GRANDTEC
 
- USB_VID_GTEK
 
- USB_VID_HAMA
 
- USB_VID_HANFTEK
 
- USB_VID_HAUPPAUGE
 
- USB_VID_HUMAX_COEX
 
- USB_VID_HYPER_PALTEK
 
- USB_VID_INTEL
 
- USB_VID_ITETECH
 
- USB_VID_KWORLD
 
- USB_VID_KWORLD_2
 
- USB_VID_KYE
 
- USB_VID_LEADTEK
 
- USB_VID_LITEON
 
- USB_VID_MEDION
 
- USB_VID_MICROSOFT
 
- USB_VID_MIGLIA
 
- USB_VID_MSI
 
- USB_VID_MSI_2
 
- USB_VID_NATIVEINSTRUMENTS
 
- USB_VID_OPERA1
 
- USB_VID_PCTV
 
- USB_VID_PINNACLE
 
- USB_VID_PIXELVIEW
 
- USB_VID_REALTEK
 
- USB_VID_SONY
 
- USB_VID_TECHNISAT
 
- USB_VID_TECHNOTREND
 
- USB_VID_TELESTAR
 
- USB_VID_TERRATEC
 
- USB_VID_TWINHAN
 
- USB_VID_ULTIMA_ELECTRONIC
 
- USB_VID_UNIWILL
 
- USB_VID_VISIONPLUS
 
- USB_VID_WIDEVIEW
 
- USB_VID_XTENSIONS
 
- USB_VID_YUAN
 
- USB_VID_ZYDAS
 
- USB_VLOADM
 
- USB_VSTAIN
 
- USB_VSTAOUT
 
- USB_WAKEUP_DEBOUNCE_COUNT
 
- USB_WAKE_ON_CNNT_EN_DEV
 
- USB_WAKE_ON_DISCON_EN_DEV
 
- USB_WDT11_CTRL
 
- USB_WINDOW_BASE
 
- USB_WINDOW_CTRL
 
- USB_WIRELESS_BEACON_DIRECTED
 
- USB_WIRELESS_BEACON_MASK
 
- USB_WIRELESS_BEACON_NONE
 
- USB_WIRELESS_BEACON_SELF
 
- USB_WIRELESS_P2P_DRD
 
- USB_WIRELESS_PHY_107
 
- USB_WIRELESS_PHY_160
 
- USB_WIRELESS_PHY_200
 
- USB_WIRELESS_PHY_320
 
- USB_WIRELESS_PHY_400
 
- USB_WIRELESS_PHY_480
 
- USB_WIRELESS_PHY_53
 
- USB_WIRELESS_PHY_80
 
- USB_WLAN_RX_PIPE
 
- USB_WLAN_TX_PIPE
 
- USB_WRITE_COFDM
 
- USB_WRITE_I2C_CMD
 
- USB_WRITE_I2C_CMD_LEN
 
- USB_WRITE_PORT_FAIL
 
- USB_WRITE_REMOTE
 
- USB_WRITE_REMOTE_TYPE
 
- USB_WRITE_TUNER
 
- USB_XHCI_EC_IRAADR
 
- USB_XHCI_EC_IRADAT
 
- USB_XHCI_EC_REG
 
- USB_XU_CLOCK_RATE
 
- USB_XU_CLOCK_RATE_SELECTOR
 
- USB_XU_CLOCK_SOURCE
 
- USB_XU_CLOCK_SOURCE_SELECTOR
 
- USB_XU_DEVICE_OPTIONS
 
- USB_XU_DIGITAL_FORMAT_SELECTOR
 
- USB_XU_DIGITAL_IO_STATUS
 
- USB_XU_DIRECT_MONITORING
 
- USB_XU_METERING
 
- USB_XU_SOFT_LIMIT_SELECTOR
 
- USB_ZD1211B_BCD_DEVICE
 
- USB__GADGET__CONFIGFS__H
 
- USBi_PCI
 
- USBi_SLI
 
- USBi_UEI
 
- USBi_UI
 
- USBi_URI
 
- USCSICMD
 
- USD
 
- USDHI6_CC_EXT_MODE
 
- USDHI6_CC_EXT_MODE_SDRW
 
- USDHI6_HOST_MODE
 
- USDHI6_MIN_DMA
 
- USDHI6_SDIF_MODE
 
- USDHI6_SDIO_INFO1
 
- USDHI6_SDIO_INFO1_EXPUB52
 
- USDHI6_SDIO_INFO1_EXWT
 
- USDHI6_SDIO_INFO1_IOIRQ
 
- USDHI6_SDIO_INFO1_IRQ
 
- USDHI6_SDIO_INFO1_MASK
 
- USDHI6_SDIO_MODE
 
- USDHI6_SD_ARG
 
- USDHI6_SD_BUF0
 
- USDHI6_SD_CLK_CTRL
 
- USDHI6_SD_CLK_CTRL_DIV_MASK
 
- USDHI6_SD_CLK_CTRL_SCLKEN
 
- USDHI6_SD_CMD
 
- USDHI6_SD_CMD_APP
 
- USDHI6_SD_CMD_CMD12_AUTO_OFF
 
- USDHI6_SD_CMD_DATA
 
- USDHI6_SD_CMD_MODE_RSP_AUTO
 
- USDHI6_SD_CMD_MODE_RSP_NONE
 
- USDHI6_SD_CMD_MODE_RSP_R1
 
- USDHI6_SD_CMD_MODE_RSP_R1B
 
- USDHI6_SD_CMD_MODE_RSP_R2
 
- USDHI6_SD_CMD_MODE_RSP_R3
 
- USDHI6_SD_CMD_MULTI
 
- USDHI6_SD_CMD_READ
 
- USDHI6_SD_ERR_STS1
 
- USDHI6_SD_ERR_STS1_CRC_NO_ERROR
 
- USDHI6_SD_ERR_STS2
 
- USDHI6_SD_INFO1
 
- USDHI6_SD_INFO1_ACCESS_END
 
- USDHI6_SD_INFO1_CARD
 
- USDHI6_SD_INFO1_CARD_CD
 
- USDHI6_SD_INFO1_CARD_EJECT
 
- USDHI6_SD_INFO1_CARD_IN
 
- USDHI6_SD_INFO1_CARD_INSERT
 
- USDHI6_SD_INFO1_CARD_OUT
 
- USDHI6_SD_INFO1_CD
 
- USDHI6_SD_INFO1_D3_CARD_IN
 
- USDHI6_SD_INFO1_D3_CARD_OUT
 
- USDHI6_SD_INFO1_IRQ
 
- USDHI6_SD_INFO1_MASK
 
- USDHI6_SD_INFO1_RSP_END
 
- USDHI6_SD_INFO1_WP
 
- USDHI6_SD_INFO2
 
- USDHI6_SD_INFO2_BRE
 
- USDHI6_SD_INFO2_BWE
 
- USDHI6_SD_INFO2_CBSY
 
- USDHI6_SD_INFO2_CMD_ERR
 
- USDHI6_SD_INFO2_CRC_ERR
 
- USDHI6_SD_INFO2_END_ERR
 
- USDHI6_SD_INFO2_ERR
 
- USDHI6_SD_INFO2_ILA
 
- USDHI6_SD_INFO2_IRA_ERR
 
- USDHI6_SD_INFO2_IRQ
 
- USDHI6_SD_INFO2_IWA_ERR
 
- USDHI6_SD_INFO2_MASK
 
- USDHI6_SD_INFO2_RSP_TOUT
 
- USDHI6_SD_INFO2_SCLKDIVEN
 
- USDHI6_SD_INFO2_SDDAT0
 
- USDHI6_SD_INFO2_TOUT
 
- USDHI6_SD_OPTION
 
- USDHI6_SD_OPTION_TIMEOUT_MASK
 
- USDHI6_SD_OPTION_TIMEOUT_SHIFT
 
- USDHI6_SD_OPTION_WIDTH_1
 
- USDHI6_SD_PORT_SEL
 
- USDHI6_SD_PORT_SEL_PORTS_SHIFT
 
- USDHI6_SD_RSP10
 
- USDHI6_SD_RSP32
 
- USDHI6_SD_RSP54
 
- USDHI6_SD_RSP76
 
- USDHI6_SD_SECCNT
 
- USDHI6_SD_SIZE
 
- USDHI6_SD_STOP
 
- USDHI6_SD_STOP_SEC
 
- USDHI6_SD_STOP_STP
 
- USDHI6_SOFT_RST
 
- USDHI6_SOFT_RST_RESERVED
 
- USDHI6_SOFT_RST_RESET
 
- USDHI6_VERSION
 
- USDHI6_WAIT_FOR_CMD
 
- USDHI6_WAIT_FOR_DATA_END
 
- USDHI6_WAIT_FOR_DMA
 
- USDHI6_WAIT_FOR_MREAD
 
- USDHI6_WAIT_FOR_MWRITE
 
- USDHI6_WAIT_FOR_READ
 
- USDHI6_WAIT_FOR_REQUEST
 
- USDHI6_WAIT_FOR_STOP
 
- USDHI6_WAIT_FOR_WRITE
 
- USDMA_HDR_FORMAT
 
- USDM_REG_AGG_INT_EVENT_0
 
- USDM_REG_AGG_INT_EVENT_1
 
- USDM_REG_AGG_INT_EVENT_2
 
- USDM_REG_AGG_INT_EVENT_4
 
- USDM_REG_AGG_INT_EVENT_5
 
- USDM_REG_AGG_INT_EVENT_6
 
- USDM_REG_AGG_INT_MODE_0
 
- USDM_REG_AGG_INT_MODE_1
 
- USDM_REG_AGG_INT_MODE_4
 
- USDM_REG_AGG_INT_MODE_5
 
- USDM_REG_AGG_INT_MODE_6
 
- USDM_REG_AGG_INT_T_5
 
- USDM_REG_AGG_INT_T_6
 
- USDM_REG_CFC_RSP_START_ADDR
 
- USDM_REG_CMP_COUNTER_MAX0
 
- USDM_REG_CMP_COUNTER_MAX1
 
- USDM_REG_CMP_COUNTER_MAX2
 
- USDM_REG_CMP_COUNTER_MAX3
 
- USDM_REG_CMP_COUNTER_START_ADDR
 
- USDM_REG_DBG_DWORD_ENABLE
 
- USDM_REG_DBG_FORCE_FRAME
 
- USDM_REG_DBG_FORCE_VALID
 
- USDM_REG_DBG_SELECT
 
- USDM_REG_DBG_SHIFT
 
- USDM_REG_ENABLE_IN1
 
- USDM_REG_ENABLE_IN2
 
- USDM_REG_ENABLE_OUT1
 
- USDM_REG_ENABLE_OUT2
 
- USDM_REG_INIT_CREDIT_PXP_CTRL
 
- USDM_REG_NUM_OF_ACK_AFTER_PLACE
 
- USDM_REG_NUM_OF_PKT_END_MSG
 
- USDM_REG_NUM_OF_PXP_ASYNC_REQ
 
- USDM_REG_NUM_OF_Q0_CMD
 
- USDM_REG_NUM_OF_Q10_CMD
 
- USDM_REG_NUM_OF_Q11_CMD
 
- USDM_REG_NUM_OF_Q1_CMD
 
- USDM_REG_NUM_OF_Q2_CMD
 
- USDM_REG_NUM_OF_Q3_CMD
 
- USDM_REG_NUM_OF_Q4_CMD
 
- USDM_REG_NUM_OF_Q5_CMD
 
- USDM_REG_NUM_OF_Q6_CMD
 
- USDM_REG_NUM_OF_Q7_CMD
 
- USDM_REG_NUM_OF_Q8_CMD
 
- USDM_REG_NUM_OF_Q9_CMD
 
- USDM_REG_PCK_END_MSG_START_ADDR
 
- USDM_REG_Q_COUNTER_START_ADDR
 
- USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY
 
- USDM_REG_SYNC_PARSER_EMPTY
 
- USDM_REG_SYNC_SYNC_EMPTY
 
- USDM_REG_TIMER_TICK
 
- USDM_REG_USDM_INT_MASK_0
 
- USDM_REG_USDM_INT_MASK_1
 
- USDM_REG_USDM_INT_STS_0
 
- USDM_REG_USDM_INT_STS_1
 
- USDM_REG_USDM_PRTY_MASK
 
- USDM_REG_USDM_PRTY_STS
 
- USDM_REG_USDM_PRTY_STS_CLR
 
- USECS_PER_BYTE
 
- USECS_PER_JIFFY
 
- USECS_PER_SEC
 
- USECS_TO_CYCLES
 
- USEC_AFTER
 
- USEC_BEFORE
 
- USEC_PER_MSEC
 
- USEC_PER_POLL
 
- USEC_PER_SEC
 
- USEC_POLL
 
- USEC_SHOW_FUNCTION
 
- USEC_STORE_FUNCTION
 
- USED
 
- USED_EXIST
 
- USED_EXTCONTEXT
 
- USED_FP
 
- USED_FR1
 
- USED_G
 
- USED_HYBRID_FPRS
 
- USED_IN_
 
- USED_M
 
- USED_QUEUES
 
- USED_S
 
- USED_SYM
 
- USEM_REG_ARB_CYCLE_SIZE
 
- USEM_REG_ARB_ELEMENT0
 
- USEM_REG_ARB_ELEMENT1
 
- USEM_REG_ARB_ELEMENT2
 
- USEM_REG_ARB_ELEMENT3
 
- USEM_REG_ARB_ELEMENT4
 
- USEM_REG_DBG_DWORD_ENABLE
 
- USEM_REG_DBG_FORCE_FRAME
 
- USEM_REG_DBG_FORCE_VALID
 
- USEM_REG_DBG_FRAME_MODE_BB_K2
 
- USEM_REG_DBG_MODE1_CFG_BB_K2
 
- USEM_REG_DBG_SELECT
 
- USEM_REG_DBG_SHIFT
 
- USEM_REG_ENABLE_IN
 
- USEM_REG_ENABLE_OUT
 
- USEM_REG_FAST_MEMORY
 
- USEM_REG_FIC0_DISABLE
 
- USEM_REG_FIC1_DISABLE
 
- USEM_REG_INT_TABLE
 
- USEM_REG_MSG_NUM_FIC0
 
- USEM_REG_MSG_NUM_FIC1
 
- USEM_REG_MSG_NUM_FOC0
 
- USEM_REG_MSG_NUM_FOC1
 
- USEM_REG_MSG_NUM_FOC2
 
- USEM_REG_MSG_NUM_FOC3
 
- USEM_REG_PASSIVE_BUFFER
 
- USEM_REG_PAS_DISABLE
 
- USEM_REG_PRAM
 
- USEM_REG_SLEEP_THREADS_VALID
 
- USEM_REG_SLOW_DBG_ACTIVE_BB_K2
 
- USEM_REG_SLOW_DBG_EMPTY_BB_K2
 
- USEM_REG_SLOW_DBG_MODE_BB_K2
 
- USEM_REG_SLOW_EXT_STORE_EMPTY
 
- USEM_REG_SYNC_DBG_EMPTY
 
- USEM_REG_THREADS_LIST
 
- USEM_REG_TS_0_AS
 
- USEM_REG_TS_10_AS
 
- USEM_REG_TS_11_AS
 
- USEM_REG_TS_12_AS
 
- USEM_REG_TS_13_AS
 
- USEM_REG_TS_14_AS
 
- USEM_REG_TS_15_AS
 
- USEM_REG_TS_16_AS
 
- USEM_REG_TS_17_AS
 
- USEM_REG_TS_18_AS
 
- USEM_REG_TS_1_AS
 
- USEM_REG_TS_2_AS
 
- USEM_REG_TS_3_AS
 
- USEM_REG_TS_4_AS
 
- USEM_REG_TS_5_AS
 
- USEM_REG_TS_6_AS
 
- USEM_REG_TS_7_AS
 
- USEM_REG_TS_8_AS
 
- USEM_REG_TS_9_AS
 
- USEM_REG_USEM_INT_MASK_0
 
- USEM_REG_USEM_INT_MASK_1
 
- USEM_REG_USEM_INT_STS_0
 
- USEM_REG_USEM_INT_STS_1
 
- USEM_REG_USEM_PRTY_MASK_0
 
- USEM_REG_USEM_PRTY_MASK_1
 
- USEM_REG_USEM_PRTY_STS_0
 
- USEM_REG_USEM_PRTY_STS_1
 
- USEM_REG_USEM_PRTY_STS_CLR_0
 
- USEM_REG_USEM_PRTY_STS_CLR_1
 
- USEM_REG_VFPF_ERR_NUM
 
- USER
 
- USER1_BN_UC_DIN_MASK
 
- USER1_BN_UC_DIN_SHIFT
 
- USER1_BN_UC_DOUT_MASK
 
- USER1_BN_UC_DOUT_SHIFT
 
- USER4_CS_ACT
 
- USERACCESS_ACK
 
- USERACCESS_DATA
 
- USERACCESS_GO
 
- USERACCESS_READ
 
- USERACCESS_WRITE
 
- USERATE
 
- USERCONFIG_REG_BASE
 
- USERCONFIG_REG_END
 
- USERCONFIG_REG_SIZE
 
- USERDATA_LEN
 
- USERDLM_H
 
- USEREXR
 
- USERGS_SYSRET32
 
- USERGS_SYSRET64
 
- USERHASH
 
- USERINFO_LEN
 
- USERINFO_POS
 
- USERIO_BUFSIZE
 
- USERIO_CMD_REGISTER
 
- USERIO_CMD_SEND_INTERRUPT
 
- USERIO_CMD_SET_PORT_TYPE
 
- USERIO_MINOR
 
- USERIO_NAME
 
- USERL
 
- USERMUX_ACLK_MSCL_532
 
- USERNS_INIT_FLAGS
 
- USERNS_SETGROUPS_ALLOWED
 
- USEROP
 
- USERRET
 
- USER_AM
 
- USER_ASID_BIT
 
- USER_ASID_FLAG
 
- USER_BAP
 
- USER_BIT1
 
- USER_BIT2
 
- USER_BUF_PAGE
 
- USER_CLIENT
 
- USER_CLOCKEVENT
 
- USER_CLOCKSOURCE
 
- USER_CMP_MODE
 
- USER_CONTROL_OBTMPFLT_LVL
 
- USER_CONTROL_OPBIASFLT_LVL
 
- USER_CONTROL_OPPRFLT_LVL
 
- USER_CONTROL_OPRXFLT_LVL
 
- USER_CONTROL_OPRXLOS_LVL
 
- USER_CONTROL_OPTXENB_LVL
 
- USER_CONTROL_OPTXFLT_LVL
 
- USER_CONTROL_OPTXON_LVL
 
- USER_CONTROL_OPTXRST_LVL
 
- USER_CONTROL_RES1
 
- USER_CONTROL_RES1_SHIFT
 
- USER_COPY_SIZE
 
- USER_CTRL_IRQ
 
- USER_CTX_SWITCH
 
- USER_DATA
 
- USER_DEFINED
 
- USER_DEFINED_INTERRUPT
 
- USER_DIC
 
- USER_DIN_EN_MS
 
- USER_DLM_LOCK_ID_MAX_LEN
 
- USER_DS
 
- USER_DS_SACF
 
- USER_DT_UPDATE
 
- USER_EEPROM_BASE
 
- USER_EEPROM_SIZE
 
- USER_EEPROM_SLICES
 
- USER_EXT_USER_PMU_3
 
- USER_FAULT
 
- USER_FRAQ
 
- USER_FREE_LIST_LOCK
 
- USER_HZ
 
- USER_IP_EN
 
- USER_IP_SEL
 
- USER_KERNEL_GUTTER
 
- USER_KEY
 
- USER_KEY_LEN
 
- USER_LIMIT
 
- USER_LOCAL
 
- USER_LOCK_ATTACHED
 
- USER_LOCK_BLOCKED
 
- USER_LOCK_BUSY
 
- USER_LOCK_IN_CANCEL
 
- USER_LOCK_IN_TEARDOWN
 
- USER_LOCK_QUEUED
 
- USER_MAP
 
- USER_MEM
 
- USER_MODE
 
- USER_MSS
 
- USER_NOTIF_MAGIC
 
- USER_NR
 
- USER_NS_INDEX
 
- USER_ODIG_CTRL_EFILT_EN
 
- USER_ODIG_CTRL_FMODE
 
- USER_ODIG_CTRL_GPIOS
 
- USER_ODIG_CTRL_GPIOS_SHIFT
 
- USER_ODIG_CTRL_LB_ERR_DIS
 
- USER_ODIG_CTRL_OPT_RST
 
- USER_ODIG_CTRL_PCS_RI
 
- USER_ODIG_CTRL_PCS_TIB
 
- USER_ODIG_CTRL_RESV1
 
- USER_ODIG_CTRL_RESV2
 
- USER_ODIG_CTRL_RESV3
 
- USER_ODIG_CTRL_RX_PDOWN
 
- USER_ODIG_CTRL_TXONOFF_PD_DIS
 
- USER_ODIG_CTRL_TX_PDOWN
 
- USER_OPCODE_CHECK_MASK
 
- USER_OPCODE_CHECK_VAL
 
- USER_PGD_PTRS
 
- USER_PGTABLES_CEILING
 
- USER_PGTABLE_CHECK_PMD_HUGE
 
- USER_PGTABLE_CHECK_PUD_HUGE
 
- USER_PGTABLE_WALK_TL1
 
- USER_PMD_TX_CTL_CMU_LPWREN
 
- USER_PMD_TX_CTL_RES1
 
- USER_PMD_TX_CTL_SFIFORST
 
- USER_PMD_TX_CTL_TSCK_LPWREN
 
- USER_PMD_TX_CTL_TSD_LPWREN
 
- USER_PMD_TX_CTL_TX_DAC_TXCK
 
- USER_PMD_TX_CTL_TX_DAC_TXCK_SH
 
- USER_PMD_TX_CTL_TX_DAC_TXD
 
- USER_PMD_TX_CTL_TX_DAC_TXD_SH
 
- USER_PMD_TX_CTL_XFP_CLKEN
 
- USER_PRIO
 
- USER_PROGRAM
 
- USER_PSW
 
- USER_PSW_BITS
 
- USER_PSW_HI_MASK
 
- USER_PSW_MASK
 
- USER_PS_VALUE
 
- USER_PTRS_PER_PGD
 
- USER_QUOTA_SYSTEM_INODE
 
- USER_REDZONE_SIZE
 
- USER_REGION_ID
 
- USER_REGS_OFFSET
 
- USER_RING
 
- USER_RPL
 
- USER_SAVEDKEYS_STAT_INIT
 
- USER_SAVEDKEYS_STAT_RUN
 
- USER_SEGMENT_RPL_MASK
 
- USER_SPACE_NR
 
- USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK
 
- USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT
 
- USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK
 
- USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT
 
- USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK
 
- USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT
 
- USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK
 
- USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT
 
- USER_SR
 
- USER_STACKID_FLAGS
 
- USER_TICK_USEC
 
- USER_UC_DIN_SEL
 
- USER_UC_DOUT_SEL
 
- USER_UC_MASK
 
- USER_VECTOR_VADDR
 
- USER_VSID_RANGE
 
- USER_WIDE_MODE
 
- USER_XATTR
 
- USER_XSTATE_FX_SW_WORDS
 
- USER_XSTATE_XCR0_WORD
 
- USES_GUC
 
- USES_GUC_SUBMISSION
 
- USES_WARPCORE
 
- USEWIRECH_F
 
- USEWIRECH_S
 
- USEWIRECH_V
 
- USE_32BIT
 
- USE_32_BIT
 
- USE_ACPI_C3
 
- USE_ALL
 
- USE_ALTERNATE
 
- USE_ANY_MDS
 
- USE_ASYNC_IOBDMA
 
- USE_ASYNC_SCAN
 
- USE_AUTH_MDS
 
- USE_AUTO_FP_POS
 
- USE_AUTO_LCD_VSYNC
 
- USE_B
 
- USE_BIG_BUF
 
- USE_BRL
 
- USE_BSD
 
- USE_BUS16BITS
 
- USE_CAN_ADDR
 
- USE_CHANNELS_MAX
 
- USE_CHANNELS_MIN
 
- USE_CHECKSUM_HW
 
- USE_CLEAR_BUFFER_WORKAROUND
 
- USE_CLEAR_DIRTY_LOG
 
- USE_CLSR
 
- USE_CMPXCHG_LOCKREF
 
- USE_CPUCLK
 
- USE_CPU_COUNTER_TIMER
 
- USE_CRC
 
- USE_CSMA_CD_PROTO
 
- USE_CTRL_O_SYSRQ
 
- USE_DEBUG
 
- USE_DEGR_WFC_T
 
- USE_DISPLAY_GAP
 
- USE_DISPLAY_GAP_CTXSW
 
- USE_DISPLAY_URGENT_CTXSW
 
- USE_DISPLAY_URGENT_NORMAL
 
- USE_DLY_MAX_SMPL
 
- USE_DLY_MIN_SMPL
 
- USE_DMA
 
- USE_DMAC
 
- USE_DMA_ACCESS
 
- USE_DOUBLE
 
- USE_DPLL
 
- USE_DTB_CMDLINE
 
- USE_DVICHIP
 
- USE_DYNAMIC_DMA
 
- USE_EARLY_PGTABLE_L5
 
- USE_EEPROM
 
- USE_ELF_CORE_DUMP
 
- USE_ENC_IDX_F
 
- USE_ENC_IDX_S
 
- USE_ENC_IDX_V
 
- USE_ENTROPY_DEV
 
- USE_EXTENDED_TAG
 
- USE_EXTRA_VOLT
 
- USE_F32KHZ
 
- USE_FAST_PIO
 
- USE_FIXED_SECTION
 
- USE_FORMATS
 
- USE_FSR
 
- USE_FTRACE_NOP
 
- USE_GLOBAL_LOCK_HYSTERESIS
 
- USE_GTS
 
- USE_G_PROTECTION
 
- USE_HASH_FUNCTION
 
- USE_HMEMTYPE_LAST_ON_DESC_OR_CHAIN_MSK
 
- USE_HMEMTYPE_LAST_ON_DESC_OR_CHAIN_SHFT
 
- USE_HP_WORKAROUND
 
- USE_HVC
 
- USE_HW_I2C
 
- USE_HW_KEY
 
- USE_HW_KEY_AUTH_SHIFT
 
- USE_HW_KEY_ENCR_SHIFT
 
- USE_INITIAL_ONLY
 
- USE_INODE_GENERATION_COUNTER
 
- USE_IO_OPS
 
- USE_ISO
 
- USE_KEYRSC
 
- USE_KEY_REG
 
- USE_KEY_REGISTERS
 
- USE_LEADING_ONLY
 
- USE_LIO3_IRQ
 
- USE_LONGIO
 
- USE_LOOKUP_TABLE_TO_CLAMP
 
- USE_MAILBOX_RESPONSE
 
- USE_MAX_PLL_RATE
 
- USE_MEMCPY
 
- USE_MEMORY_SELF_REFRESH_MASK
 
- USE_MFP
 
- USE_NATIVE_ALLOCATE_ZEROED
 
- USE_NDELAY
 
- USE_NEW_SCHEME
 
- USE_NON_BUS_CLOCK_MASK
 
- USE_NORTHBRIDGE
 
- USE_OCTEON_INTERNAL_ARBITER
 
- USE_OLD_WOWLAN_DEBUG_FW
 
- USE_PAGER
 
- USE_PAGE_ORDER
 
- USE_PAT_CPUID
 
- USE_PCI_DMA_API
 
- USE_PCI_INTB
 
- USE_PCI_INTC
 
- USE_PCI_INTD
 
- USE_PCI_TIMING
 
- USE_PERIODS_MAX
 
- USE_PERIODS_MIN
 
- USE_PESRTB_CTL_DELINK
 
- USE_PF
 
- USE_PHY_WORK_AROUND
 
- USE_PIPE_KEY_AUTH_SHIFT
 
- USE_PIPE_KEY_ENCR_ENABLED
 
- USE_PIPE_KEY_ENCR_SHIFT
 
- USE_PKCS7
 
- USE_PLATFORM_DELAY
 
- USE_PLATFORM_PM_SLEEP_OPS
 
- USE_PM_CLK_RUNTIME_OPS
 
- USE_PROM_CMDLINE
 
- USE_QOS
 
- USE_QUICK_LAST_INST
 
- USE_RANDOM_MDS
 
- USE_RATE
 
- USE_RATE_MAX
 
- USE_RATE_MIN
 
- USE_RDK_LEDS
 
- USE_REAL_VBLANKSTART
 
- USE_RGN_FLSH
 
- USE_RISC_NOOP
 
- USE_RX_BLANK
 
- USE_SCATTERGATHER
 
- USE_SEL_BIT
 
- USE_SHADOWED_ROWCUR
 
- USE_SHADOWED_VEND
 
- USE_SHMEM
 
- USE_SHORT_G1
 
- USE_SIMIC
 
- USE_SMC
 
- USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN
 
- USE_SPI_DMA
 
- USE_SPLIT_PMD_PTLOCKS
 
- USE_SPLIT_PTE_PTLOCKS
 
- USE_SS_ENABLED_PIXEL_CLOCK
 
- USE_SUSPEND_WAIT
 
- USE_TEXT_SECTION
 
- USE_TX_COAL_NOW
 
- USE_TX_COMPWB
 
- USE_TYPE_E
 
- USE_TYPE_SERVICE
 
- USE_TYPE_SERVICE_NO_RESUME
 
- USE_TYPE_VCHIQ
 
- USE_VCHIQ_ARM
 
- USE_VISIBILITY
 
- USE_VMIDMT
 
- USE_VPD_DEBUG
 
- USE_WCACHING
 
- USE_WINDOWSIZE
 
- USE_WORD_ACCESS
 
- USE_WORKITEM
 
- USHC_CBW_SIGNATURE
 
- USHC_CLK_FREQ
 
- USHC_CLK_FREQ_TYPE
 
- USHC_CSW_SIGNATURE
 
- USHC_EXEC_CMD
 
- USHC_EXEC_CMD_TYPE
 
- USHC_GET_CAPS
 
- USHC_GET_CAPS_1V8
 
- USHC_GET_CAPS_3V0
 
- USHC_GET_CAPS_3V3
 
- USHC_GET_CAPS_HIGH_SPD
 
- USHC_GET_CAPS_TYPE
 
- USHC_GET_CAPS_VERSION_MASK
 
- USHC_HOST_CTRL
 
- USHC_HOST_CTRL_4BIT
 
- USHC_HOST_CTRL_HIGH_SPD
 
- USHC_HOST_CTRL_TYPE
 
- USHC_INT_STATUS_CARD_PRESENT
 
- USHC_INT_STATUS_SDIO_INT
 
- USHC_PWR_CTRL
 
- USHC_PWR_CTRL_1V8
 
- USHC_PWR_CTRL_3V0
 
- USHC_PWR_CTRL_3V3
 
- USHC_PWR_CTRL_OFF
 
- USHC_PWR_CTRL_TYPE
 
- USHC_READ_RESP
 
- USHC_READ_RESP_BUSY
 
- USHC_READ_RESP_ERR_CMD
 
- USHC_READ_RESP_ERR_CRC
 
- USHC_READ_RESP_ERR_DAT
 
- USHC_READ_RESP_ERR_MASK
 
- USHC_READ_RESP_ERR_TIMEOUT
 
- USHC_READ_RESP_TYPE
 
- USHC_RESET
 
- USHC_RESET_TYPE
 
- USHORT
 
- USHRT_MAX
 
- USI0_CS1_MARK
 
- USI0_CS2_MARK
 
- USI0_CS3_MARK
 
- USI0_CS4_MARK
 
- USI0_CS5_MARK
 
- USI0_CS6_MARK
 
- USI1_DI_MARK
 
- USI1_DO_MARK
 
- USI2_CLK_MARK
 
- USI2_CS0_MARK
 
- USI2_CS1_MARK
 
- USI2_CS2_MARK
 
- USI2_DI_MARK
 
- USI2_DO_MARK
 
- USI3_CLK_MARK
 
- USI3_CS0_MARK
 
- USI3_DI_MARK
 
- USI3_DO_MARK
 
- USI4_CLK_MARK
 
- USI4_CS0_MARK
 
- USI4_CS1_MARK
 
- USI4_DI_MARK
 
- USI4_DO_MARK
 
- USI5_CLK_A_MARK
 
- USI5_CLK_B_MARK
 
- USI5_CS0_A_MARK
 
- USI5_CS0_B_MARK
 
- USI5_CS1_A_MARK
 
- USI5_CS1_B_MARK
 
- USI5_CS2_A_MARK
 
- USI5_CS2_B_MARK
 
- USI5_CS3_B_MARK
 
- USI5_CS4_B_MARK
 
- USI5_DI_A_MARK
 
- USI5_DI_B_MARK
 
- USI5_DO_A_MARK
 
- USI5_DO_B_MARK
 
- USIAU0_RSTCTRL
 
- USIBU1_RSTCTRL
 
- USIBU2_RSTCTRL
 
- USIBU3_RSTCTRL
 
- USIM1_CD
 
- USIM1_CLK
 
- USIM1_DATA
 
- USIM1_RST
 
- USING_COMPARE
 
- USING_MSI
 
- USING_MSIX
 
- USING_MSIX_FLAG
 
- USING_MSI_FLAG
 
- USING_SINGLE_MSIX_FLAG
 
- USIO_CONSOLE
 
- USIO_NAME
 
- USIO_UART_DEV_NAME
 
- USIR0
 
- USIR0_IR0
 
- USIR0_IR1
 
- USIR0_IR2
 
- USIR0_IR3
 
- USIR0_IR4
 
- USIR0_IR5
 
- USIR0_IR6
 
- USIR0_IR7
 
- USIR1
 
- USIR1_IR10
 
- USIR1_IR11
 
- USIR1_IR12
 
- USIR1_IR13
 
- USIR1_IR14
 
- USIR1_IR15
 
- USIR1_IR8
 
- USIR1_IR9
 
- USI_MAX_MEMCNT
 
- USI_MAX_MEMCNT_BASE
 
- USItype
 
- USL_Info_S
 
- USN
 
- USNIC_ABI_H
 
- USNIC_CMN_PKT_HDR_H
 
- USNIC_CMN_UTIL_H
 
- USNIC_DEBUGFS_H_
 
- USNIC_DEFAULT_TRANSPORT
 
- USNIC_FWD_H_
 
- USNIC_H_
 
- USNIC_IB_H_
 
- USNIC_IB_NUM_COMP_VECTORS
 
- USNIC_IB_PORT_CNT
 
- USNIC_IB_QP_GRP_H_
 
- USNIC_IB_SYSFS_H_
 
- USNIC_IB_VERBS_H_
 
- USNIC_LOG_H_
 
- USNIC_LOG_LVL_DBG
 
- USNIC_LOG_LVL_ERR
 
- USNIC_LOG_LVL_INFO
 
- USNIC_LOG_LVL_NONE
 
- USNIC_PROTO_VER
 
- USNIC_QP_GRP_MAX_CQS
 
- USNIC_QP_GRP_MAX_RQS
 
- USNIC_QP_GRP_MAX_WQS
 
- USNIC_ROCE_GRH_VER
 
- USNIC_ROCE_GRH_VER_SHIFT
 
- USNIC_TRANSPORT_H_
 
- USNIC_TRANSPORT_IPV4_UDP
 
- USNIC_TRANSPORT_MAX
 
- USNIC_TRANSPORT_ROCE_CUSTOM
 
- USNIC_TRANSPORT_UNKNOWN
 
- USNIC_UIOM_H_
 
- USNIC_UIOM_INTERVAL_TREE_H_
 
- USNIC_UIOM_MAX_MR_CNT
 
- USNIC_UIOM_MAX_MR_SIZE
 
- USNIC_UIOM_MAX_PD_CNT
 
- USNIC_UIOM_PAGE_CHUNK
 
- USNIC_UIOM_PAGE_SIZE
 
- USNIC_UIOM_READ
 
- USNIC_UIOM_WRITE
 
- USNIC_UVERBS_ABI_VERSION
 
- USNIC_VNIC_H_
 
- USNIC_VNIC_RES_TYPES
 
- USN_HEADER
 
- USN_REASON_BASIC_INFO_CHANGE
 
- USN_REASON_CLOSE
 
- USN_REASON_COMPRESSION_CHANGE
 
- USN_REASON_DATA_EXTEND
 
- USN_REASON_DATA_OVERWRITE
 
- USN_REASON_DATA_TRUNCATION
 
- USN_REASON_EA_CHANGE
 
- USN_REASON_ENCRYPTION_CHANGE
 
- USN_REASON_FILE_CREATE
 
- USN_REASON_FILE_DELETE
 
- USN_REASON_FLAGS
 
- USN_REASON_HARD_LINK_CHANGE
 
- USN_REASON_INDEXABLE_CHANGE
 
- USN_REASON_NAMED_DATA_EXTEND
 
- USN_REASON_NAMED_DATA_OVERWRITE
 
- USN_REASON_NAMED_DATA_TRUNCATION
 
- USN_REASON_OBJECT_ID_CHANGE
 
- USN_REASON_RENAME_NEW_NAME
 
- USN_REASON_RENAME_OLD_NAME
 
- USN_REASON_REPARSE_POINT_CHANGE
 
- USN_REASON_SECURITY_CHANGE
 
- USN_REASON_STREAM_CHANGE
 
- USN_RECORD
 
- USN_SOURCE_AUXILIARY_DATA
 
- USN_SOURCE_DATA_MANAGEMENT
 
- USN_SOURCE_INFO_FLAGS
 
- USN_SOURCE_REPLICATION_MANAGEMENT
 
- USPI_UBH
 
- USPTOKSP
 
- USP_ASYNC_DIV2
 
- USP_ASYNC_DIV2_MASK
 
- USP_ASYNC_DIV2_OFFSET
 
- USP_ASYNC_TIMEOUT
 
- USP_ASYNC_TIMEOUT_MASK
 
- USP_ASYNC_TIMEOUT_OFFSET
 
- USP_AYSNC_PARAM_REG
 
- USP_CLK_DIVISOR_MASK
 
- USP_CLK_DIVISOR_OFFSET
 
- USP_CLOCK_MODE_SLAVE
 
- USP_EN
 
- USP_ENA_CTRL_MODE
 
- USP_ENDIAN_CTRL_LSBF
 
- USP_FIFO_SIZE
 
- USP_FIFO_WIDTH_BYTE
 
- USP_FIFO_WIDTH_DWORD
 
- USP_FIFO_WIDTH_WORD
 
- USP_FRAME_CTRL_MODE
 
- USP_HPSIR_EN
 
- USP_I2S_SYNC_CHG
 
- USP_INT_ALL
 
- USP_INT_ENABLE
 
- USP_INT_STATUS
 
- USP_IRDA_DATA_WIDTH
 
- USP_IRDA_IDLE_LEVEL_HIGH
 
- USP_IRDA_WIDTH_DIV_MASK
 
- USP_IRDA_WIDTH_DIV_OFFSET
 
- USP_IRDA_X_MODE_DIV
 
- USP_LOOP_BACK_EN
 
- USP_MODE1
 
- USP_MODE2
 
- USP_PIN_IO_DATA
 
- USP_PLUGOUT_RETRY_CNT
 
- USP_PREWAKE
 
- USP_RFS_ACT_LEVEL_LOGIC1
 
- USP_RFS_CLK_SLAVE_MODE
 
- USP_RFS_IO_MODE_INPUT
 
- USP_RFS_PIN_MODE_IO
 
- USP_RFS_PIN_VALUE_MASK
 
- USP_RISC_DSP_MODE
 
- USP_RISC_DSP_SEL
 
- USP_RXC_CLK_DIVISOR_MASK
 
- USP_RXC_CLK_DIVISOR_OFFSET
 
- USP_RXC_DATA_LEN_MASK
 
- USP_RXC_DATA_LEN_OFFSET
 
- USP_RXC_FRAME_LEN_MASK
 
- USP_RXC_FRAME_LEN_OFFSET
 
- USP_RXC_SHIFTER_LEN_MASK
 
- USP_RXC_SHIFTER_LEN_OFFSET
 
- USP_RXD_ACT_EDGE_FALLING
 
- USP_RXD_BREAK_INT
 
- USP_RXD_DELAY_LEN_MASK
 
- USP_RXD_DELAY_LEN_OFFSET
 
- USP_RXD_IO_MODE_INPUT
 
- USP_RXD_PIN_MODE_IO
 
- USP_RXD_PIN_VALUE_MASK
 
- USP_RXFIFO_FULL_INT
 
- USP_RXFIFO_THD_INT
 
- USP_RX_DATA_LEN_MASK
 
- USP_RX_DATA_LEN_OFFSET
 
- USP_RX_DMA_FLUSH
 
- USP_RX_DMA_IO_CTRL
 
- USP_RX_DMA_IO_LEN
 
- USP_RX_DONE_INT
 
- USP_RX_ENA
 
- USP_RX_ENDIAN_MODE
 
- USP_RX_FIFO_CTRL
 
- USP_RX_FIFO_DATA
 
- USP_RX_FIFO_DATA_MASK
 
- USP_RX_FIFO_DATA_OFFSET
 
- USP_RX_FIFO_EMPTY
 
- USP_RX_FIFO_FULL
 
- USP_RX_FIFO_HC_OFFSET
 
- USP_RX_FIFO_LC_OFFSET
 
- USP_RX_FIFO_LEVEL_CHECK_MASK
 
- USP_RX_FIFO_LEVEL_CHK
 
- USP_RX_FIFO_LEVEL_MASK
 
- USP_RX_FIFO_LEVEL_OFFSET
 
- USP_RX_FIFO_OP
 
- USP_RX_FIFO_RESET
 
- USP_RX_FIFO_SC_OFFSET
 
- USP_RX_FIFO_START
 
- USP_RX_FIFO_STATUS
 
- USP_RX_FIFO_THD_MASK
 
- USP_RX_FIFO_THD_OFFSET
 
- USP_RX_FIFO_THRESHOLD
 
- USP_RX_FIFO_WIDTH_MASK
 
- USP_RX_FIFO_WIDTH_OFFSET
 
- USP_RX_FRAME_CTRL
 
- USP_RX_INTERRUPT
 
- USP_RX_IO_DMA_INT
 
- USP_RX_MODE_IO
 
- USP_RX_OFLOW_INT
 
- USP_RX_TIMEOUT_INT
 
- USP_SCLK_IDLE_LEVEL_LOGIC1
 
- USP_SCLK_IDLE_MODE_TOGGLE
 
- USP_SCLK_IO_MODE_INPUT
 
- USP_SCLK_PIN_MODE_IO
 
- USP_SCLK_PIN_VALUE_MASK
 
- USP_SINGLE_SYNC_MODE
 
- USP_SM_CFG
 
- USP_START_EDGE_MODE
 
- USP_SYNC_MODE
 
- USP_TFS_ACT_LEVEL_LOGIC1
 
- USP_TFS_CLK_SLAVE_MODE
 
- USP_TFS_IO_MODE_INPUT
 
- USP_TFS_MS_MODE
 
- USP_TFS_PIN_MODE_IO
 
- USP_TFS_PIN_VALUE_MASK
 
- USP_TFS_SOURCE_MODE
 
- USP_TXC_CLK_DIVISOR_MASK
 
- USP_TXC_CLK_DIVISOR_OFFSET
 
- USP_TXC_DATA_LEN_MASK
 
- USP_TXC_DATA_LEN_OFFSET
 
- USP_TXC_FRAME_LEN_MASK
 
- USP_TXC_FRAME_LEN_OFFSET
 
- USP_TXC_SHIFTER_LEN_MASK
 
- USP_TXC_SHIFTER_LEN_OFFSET
 
- USP_TXC_SLAVE_CLK_SAMPLE
 
- USP_TXC_SYNC_LEN_MASK
 
- USP_TXC_SYNC_LEN_OFFSET
 
- USP_TXD_ACT_EDGE_FALLING
 
- USP_TXD_DELAY_LEN_MASK
 
- USP_TXD_DELAY_LEN_OFFSET
 
- USP_TXD_IO_MODE_INPUT
 
- USP_TXD_PIN_MODE_IO
 
- USP_TXD_PIN_VALUE_MASK
 
- USP_TXFIFO_EMPTY_INT
 
- USP_TXFIFO_THD_INT
 
- USP_TX_ALLOUT_INT
 
- USP_TX_DATA_LEN_MASK
 
- USP_TX_DATA_LEN_OFFSET
 
- USP_TX_DMA_IO_CTRL
 
- USP_TX_DMA_IO_LEN
 
- USP_TX_DONE_INT
 
- USP_TX_ENA
 
- USP_TX_ENDIAN_MODE
 
- USP_TX_FIFO_CTRL
 
- USP_TX_FIFO_DATA
 
- USP_TX_FIFO_DATA_MASK
 
- USP_TX_FIFO_DATA_OFFSET
 
- USP_TX_FIFO_EMPTY
 
- USP_TX_FIFO_FULL
 
- USP_TX_FIFO_HC_OFFSET
 
- USP_TX_FIFO_LC_OFFSET
 
- USP_TX_FIFO_LEVEL_CHECK_MASK
 
- USP_TX_FIFO_LEVEL_CHK
 
- USP_TX_FIFO_LEVEL_MASK
 
- USP_TX_FIFO_LEVEL_OFFSET
 
- USP_TX_FIFO_OP
 
- USP_TX_FIFO_RESET
 
- USP_TX_FIFO_SC_OFFSET
 
- USP_TX_FIFO_START
 
- USP_TX_FIFO_STATUS
 
- USP_TX_FIFO_THD_MASK
 
- USP_TX_FIFO_THD_OFFSET
 
- USP_TX_FIFO_THRESHOLD
 
- USP_TX_FIFO_WIDTH_MASK
 
- USP_TX_FIFO_WIDTH_OFFSET
 
- USP_TX_FRAME_CTRL
 
- USP_TX_INTERRUPT
 
- USP_TX_IO_DMA_INT
 
- USP_TX_MODE_IO
 
- USP_TX_RX_ENABLE
 
- USP_TX_RX_FIFO_WIDTH_DWORD
 
- USP_TX_UFLOW_INT
 
- USP_TX_UFLOW_REPEAT_ZERO
 
- USP_UART_FRM_ERR_INT
 
- USR
 
- USR1
 
- USR1_AGTIM
 
- USR1_AIRINT
 
- USR1_AWAKE
 
- USR1_DST_OFF_PITCH
 
- USR1_DTRD
 
- USR1_ESCF
 
- USR1_FRAMERR
 
- USR1_PARITYERR
 
- USR1_RRDY
 
- USR1_RTSD
 
- USR1_RTSS
 
- USR1_RXDS
 
- USR1_TRDY
 
- USR2
 
- USR26_MODE
 
- USR2_ADET
 
- USR2_BRCD
 
- USR2_DCDIN
 
- USR2_DST_OFF_PITCH
 
- USR2_DTRF
 
- USR2_IDLE
 
- USR2_IRINT
 
- USR2_ORE
 
- USR2_RDR
 
- USR2_RIDELT
 
- USR2_RIIN
 
- USR2_RTSF
 
- USR2_TXDC
 
- USR2_TXFE
 
- USR2_WAKE
 
- USRACR
 
- USRGPIR
 
- USRLCDR
 
- USRLEDR
 
- USRQUOTA
 
- USR_BKPT
 
- USR_BLK_NM
 
- USR_DATA_BLOCK_SZ_MSK
 
- USR_DATA_BLOCK_SZ_OFF
 
- USR_DST_PICTH
 
- USR_INT
 
- USR_MODE
 
- USR_PR_INST
 
- USR_REGS_OFFSET
 
- USR_REG_OFFSET
 
- USR_VID
 
- USTCNT
 
- USTCNT_8_7
 
- USTCNT_ADDR
 
- USTCNT_CLKM
 
- USTCNT_CLKMODE
 
- USTCNT_CTSD
 
- USTCNT_CTSDELTAEN
 
- USTCNT_GPIODELTAEN
 
- USTCNT_ODD
 
- USTCNT_ODD_EVEN
 
- USTCNT_ODEN
 
- USTCNT_PARITYEN
 
- USTCNT_PEN
 
- USTCNT_RXEN
 
- USTCNT_RXFE
 
- USTCNT_RXFULLEN
 
- USTCNT_RXHALFEN
 
- USTCNT_RXHE
 
- USTCNT_RXRE
 
- USTCNT_RXREADYEN
 
- USTCNT_STOP
 
- USTCNT_TXAE
 
- USTCNT_TXAVAILEN
 
- USTCNT_TXEE
 
- USTCNT_TXEMPTYEN
 
- USTCNT_TXEN
 
- USTCNT_TXHALFEN
 
- USTCNT_TXHE
 
- USTCNT_UARTEN
 
- USTCNT_UEN
 
- USTIME
 
- USTIME_EDCA
 
- USTIME_TSF
 
- USTORE_ADDRESS
 
- USTORE_DATA_LOWER
 
- USTORE_DATA_UPPER
 
- USTORM
 
- USTORM_AGG_DATA_OFFSET
 
- USTORM_AGG_DATA_SIZE
 
- USTORM_ASSERT_LIST_INDEX_OFFSET
 
- USTORM_ASSERT_LIST_OFFSET
 
- USTORM_COMMON_QUEUE_CONS_OFFSET
 
- USTORM_COMMON_QUEUE_CONS_SIZE
 
- USTORM_EQE_CONS_OFFSET
 
- USTORM_EQE_CONS_SIZE
 
- USTORM_ETH_PAUSE_ENABLED_OFFSET
 
- USTORM_ETH_PF_STAT_OFFSET
 
- USTORM_ETH_PF_STAT_SIZE
 
- USTORM_ETH_QUEUE_ZONE_OFFSET
 
- USTORM_ETH_QUEUE_ZONE_SIZE
 
- USTORM_FATAL_ASSERT_ATTENTION_BIT
 
- USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE
 
- USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT
 
- USTORM_FCOE_AG_CONTEXT_COMPLETION_CF
 
- USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN
 
- USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT
 
- USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT
 
- USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG
 
- USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT
 
- USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE
 
- USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT
 
- USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1
 
- USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT
 
- USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2
 
- USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT
 
- USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3
 
- USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT
 
- USTORM_FCOE_AG_CONTEXT_INV_CF
 
- USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT
 
- USTORM_FCOE_AG_CONTEXT_TX_CF
 
- USTORM_FCOE_AG_CONTEXT_TX_CF_EN
 
- USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT
 
- USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT
 
- USTORM_FCOE_EQ_PROD_OFFSET
 
- USTORM_FCOE_PARAMS_B_CONF_REQ
 
- USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT
 
- USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT
 
- USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT
 
- USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT
 
- USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT
 
- USTORM_FCOE_PARAMS_B_E_D_TOV_RES
 
- USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT
 
- USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS
 
- USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT
 
- USTORM_FCOE_PARAMS_B_REC_VALID
 
- USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT
 
- USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT
 
- USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT
 
- USTORM_FCOE_PARAMS_RSRV0
 
- USTORM_FCOE_PARAMS_RSRV0_SHIFT
 
- USTORM_FLR_FINAL_ACK_OFFSET
 
- USTORM_FLR_FINAL_ACK_SIZE
 
- USTORM_FUNC_EN_OFFSET
 
- USTORM_ID
 
- USTORM_INTEG_TEST_DATA_OFFSET
 
- USTORM_INTEG_TEST_DATA_SIZE
 
- USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE
 
- USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE_SHIFT
 
- USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG
 
- USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT
 
- USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE
 
- USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE_SHIFT
 
- USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF
 
- USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN
 
- USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN_SHIFT
 
- USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_SHIFT
 
- USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1
 
- USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT
 
- USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2
 
- USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT
 
- USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3
 
- USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT
 
- USTORM_ISCSI_AG_CONTEXT_INV_CF
 
- USTORM_ISCSI_AG_CONTEXT_INV_CF_EN
 
- USTORM_ISCSI_AG_CONTEXT_INV_CF_EN_SHIFT
 
- USTORM_ISCSI_AG_CONTEXT_INV_CF_SHIFT
 
- USTORM_ISCSI_AG_CONTEXT_TX_CF
 
- USTORM_ISCSI_AG_CONTEXT_TX_CF_EN
 
- USTORM_ISCSI_AG_CONTEXT_TX_CF_EN_SHIFT
 
- USTORM_ISCSI_AG_CONTEXT_TX_CF_SHIFT
 
- USTORM_ISCSI_CQ_SIZE_OFFSET
 
- USTORM_ISCSI_CQ_SQN_SIZE_OFFSET
 
- USTORM_ISCSI_ERROR_BITMAP_OFFSET
 
- USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET
 
- USTORM_ISCSI_NUM_OF_TASKS_OFFSET
 
- USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET
 
- USTORM_ISCSI_PAGE_SIZE_OFFSET
 
- USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE
 
- USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE_SHIFT
 
- USTORM_ISCSI_PLACEMENT_DB_CQ_ID
 
- USTORM_ISCSI_PLACEMENT_DB_CQ_ID_SHIFT
 
- USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B
 
- USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B_SHIFT
 
- USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX
 
- USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX_SHIFT
 
- USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD
 
- USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD_SHIFT
 
- USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE
 
- USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE_SHIFT
 
- USTORM_ISCSI_R2TQ_SIZE_OFFSET
 
- USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET
 
- USTORM_ISCSI_RQ_SIZE_OFFSET
 
- USTORM_ISCSI_RX_STATS_OFFSET
 
- USTORM_ISCSI_RX_STATS_SIZE
 
- USTORM_ISCSI_ST_CONTEXT_BFENCECQE
 
- USTORM_ISCSI_ST_CONTEXT_BFENCECQE_SHIFT
 
- USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU
 
- USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT
 
- USTORM_ISCSI_ST_CONTEXT_BRESETCRC
 
- USTORM_ISCSI_ST_CONTEXT_BRESETCRC_SHIFT
 
- USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED
 
- USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED_SHIFT
 
- USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED
 
- USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED_SHIFT
 
- USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN
 
- USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN_SHIFT
 
- USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN
 
- USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN_SHIFT
 
- USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR
 
- USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR_SHIFT
 
- USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID
 
- USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID_SHIFT
 
- USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH
 
- USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH_SHIFT
 
- USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS
 
- USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT
 
- USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH
 
- USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH_SHIFT
 
- USTORM_ISCSI_ST_CONTEXT_RESERVED1
 
- USTORM_ISCSI_ST_CONTEXT_RESERVED1_SHIFT
 
- USTORM_ISCSI_ST_CONTEXT_TASK_TYPE
 
- USTORM_ISCSI_ST_CONTEXT_TASK_TYPE_SHIFT
 
- USTORM_ISCSI_TASK_ST_CTX_AHS_EXIST_MASK
 
- USTORM_ISCSI_TASK_ST_CTX_AHS_EXIST_SHIFT
 
- USTORM_ISCSI_TASK_ST_CTX_CQE_WRITE_MASK
 
- USTORM_ISCSI_TASK_ST_CTX_CQE_WRITE_SHIFT
 
- USTORM_ISCSI_TASK_ST_CTX_DATA_DIGEST_ERROR_MASK
 
- USTORM_ISCSI_TASK_ST_CTX_DATA_DIGEST_ERROR_SHIFT
 
- USTORM_ISCSI_TASK_ST_CTX_DATA_TRUNCATED_ERROR_MASK
 
- USTORM_ISCSI_TASK_ST_CTX_DATA_TRUNCATED_ERROR_SHIFT
 
- USTORM_ISCSI_TASK_ST_CTX_HQ_SCANNED_DONE_MASK
 
- USTORM_ISCSI_TASK_ST_CTX_HQ_SCANNED_DONE_SHIFT
 
- USTORM_ISCSI_TASK_ST_CTX_LOCAL_COMP_MASK
 
- USTORM_ISCSI_TASK_ST_CTX_LOCAL_COMP_SHIFT
 
- USTORM_ISCSI_TASK_ST_CTX_Q0_R2TQE_WRITE_MASK
 
- USTORM_ISCSI_TASK_ST_CTX_Q0_R2TQE_WRITE_SHIFT
 
- USTORM_ISCSI_TASK_ST_CTX_R2T2RECV_DONE_MASK
 
- USTORM_ISCSI_TASK_ST_CTX_R2T2RECV_DONE_SHIFT
 
- USTORM_ISCSI_TASK_ST_CTX_RESERVED0_MASK
 
- USTORM_ISCSI_TASK_ST_CTX_RESERVED0_SHIFT
 
- USTORM_ISCSI_TASK_ST_CTX_RESERVED1_MASK
 
- USTORM_ISCSI_TASK_ST_CTX_RESERVED1_SHIFT
 
- USTORM_ISCSI_TASK_ST_CTX_RESERVED8_MASK
 
- USTORM_ISCSI_TASK_ST_CTX_RESERVED8_SHIFT
 
- USTORM_ISCSI_TASK_ST_CTX_TOTAL_DATA_ACKED_DONE_MASK
 
- USTORM_ISCSI_TASK_ST_CTX_TOTAL_DATA_ACKED_DONE_SHIFT
 
- USTORM_ISCSI_TASK_ST_CTX_UNDER_RUN_ERROR_MASK
 
- USTORM_ISCSI_TASK_ST_CTX_UNDER_RUN_ERROR_SHIFT
 
- USTORM_MEM_WORKAROUND_ADDRESS_OFFSET
 
- USTORM_QUEUE_STAT_OFFSET
 
- USTORM_QUEUE_STAT_SIZE
 
- USTORM_QZONE_SIZE
 
- USTORM_RDMA_ASSERT_LEVEL_OFFSET
 
- USTORM_RDMA_ASSERT_LEVEL_SIZE
 
- USTORM_RECORD_SLOW_PATH_OFFSET
 
- USTORM_ROCE_CQE_STATS_OFFSET
 
- USTORM_ROCE_CQE_STATS_SIZE
 
- USTORM_RX_PRODS_E1X_OFFSET
 
- USTORM_RX_PRODS_E2_OFFSET
 
- USTORM_TOE_CQ_PROD_OFFSET
 
- USTORM_TOE_CQ_PROD_SIZE
 
- USTORM_TOE_GRQ_PROD_OFFSET
 
- USTORM_TOE_GRQ_PROD_SIZE
 
- USTORM_TPA_BTR_OFFSET
 
- USTORM_TPA_BTR_SIZE
 
- USTORM_VF_PF_CHANNEL_READY_OFFSET
 
- USTORM_VF_PF_CHANNEL_READY_SIZE
 
- USTORM_VF_TO_PF_OFFSET
 
- USUAL_DEV
 
- USX2YHWDEP_H
 
- USX2Y_DRIVER_VERSION
 
- USX2Y_NRPACKS
 
- USX2Y_NRPACKS_VARIABLE
 
- USX2Y_STAT_CHIP_HUP
 
- USX2Y_STAT_CHIP_INIT
 
- USX2Y_STAT_CHIP_MMAP_PCM_URBS
 
- USX2Y_TYPE_122
 
- USX2Y_TYPE_224
 
- USX2Y_TYPE_428
 
- USX2Y_TYPE_NUMS
 
- USYSCLK
 
- US_BRGR
 
- US_BRGR_SIZE
 
- US_BULK
 
- US_BULK0
 
- US_BULK_CB_SIGN
 
- US_BULK_CB_WRAP_LEN
 
- US_BULK_CS_SIGN
 
- US_BULK_CS_WRAP_LEN
 
- US_BULK_FLAG_IN
 
- US_BULK_FLAG_OUT
 
- US_BULK_GET_MAX_LUN
 
- US_BULK_RESET_REQUEST
 
- US_BULK_STAT_FAIL
 
- US_BULK_STAT_OK
 
- US_BULK_STAT_PHASE
 
- US_CBI_ADSC
 
- US_CR
 
- US_CR_RSTRX
 
- US_CR_RSTTX
 
- US_CR_RXDIS
 
- US_CR_RXEN
 
- US_CR_TXDIS
 
- US_CR_TXEN
 
- US_CSR
 
- US_CTRL_ACK
 
- US_CTRL_DATA
 
- US_CTRL_SETUP
 
- US_CYC_CNT
 
- US_CYC_CNT_BT_MODE_EN
 
- US_CYC_CNT_CLOCK_CYCLE
 
- US_DEBUG
 
- US_DISABLE
 
- US_DMA_MIN_BYTES
 
- US_DMA_TIMEOUT
 
- US_DO_ALL_FLAGS
 
- US_ENABLE
 
- US_FLAG
 
- US_FLIDX_ABORTING
 
- US_FLIDX_DISCONNECTING
 
- US_FLIDX_READ10_WORKED
 
- US_FLIDX_REDO_READ10
 
- US_FLIDX_RESETTING
 
- US_FLIDX_SCAN_PENDING
 
- US_FLIDX_SG_ACTIVE
 
- US_FLIDX_TIMED_OUT
 
- US_FLIDX_URB_ACTIVE
 
- US_IDR
 
- US_IER
 
- US_IF
 
- US_INIT
 
- US_IOBUF_SIZE
 
- US_IR_OVRE
 
- US_IR_RXRDY
 
- US_IR_TXRDY
 
- US_MAX_CLK_DIV
 
- US_MIN_CLK_DIV
 
- US_MR
 
- US_MR_CHRL
 
- US_MR_CLKO
 
- US_MR_CPHA
 
- US_MR_CPOL
 
- US_MR_LOOP
 
- US_MR_SPI_MASTER
 
- US_MR_WRDBT
 
- US_OVRE_RXRDY_IRQS
 
- US_PER_DOT
 
- US_RESET
 
- US_RESUME
 
- US_RHR
 
- US_SCALE
 
- US_SENSE_SIZE
 
- US_SUSPEND
 
- US_THR
 
- US_TO_FR_TIME
 
- US_TO_NS
 
- US_TO_SAMPLES
 
- US_VERSION
 
- UTASK_RUNNING
 
- UTASK_SSTEP
 
- UTASK_SSTEP_ACK
 
- UTASK_SSTEP_TRAPPED
 
- UTBIPAR_PHY_ADDRESS_MASK
 
- UTBIPAR_PHY_ADDRESS_SHIFT
 
- UTBL_COL_COUNT
 
- UTBL_ROW_COUNT
 
- UTCL0FaultType
 
- UTCL0RequestType
 
- UTCL0_TYPE_BYPASS
 
- UTCL0_TYPE_NORMAL
 
- UTCL0_TYPE_SHOOTDOWN
 
- UTCL0_XNACK_NO_RETRY
 
- UTCL0_XNACK_PRT
 
- UTCL0_XNACK_RETRY
 
- UTCL0_XNACK_SUCCESS
 
- UTCL1FaultType
 
- UTCL1PerfSel
 
- UTCL1RequestType
 
- UTCL1_ALOG__UTCL1_ALOG_ACTIVE_MASK
 
- UTCL1_ALOG__UTCL1_ALOG_ACTIVE__SHIFT
 
- UTCL1_ALOG__UTCL1_ALOG_CLEAN_MASK
 
- UTCL1_ALOG__UTCL1_ALOG_CLEAN__SHIFT
 
- UTCL1_ALOG__UTCL1_ALOG_IDLE_MASK
 
- UTCL1_ALOG__UTCL1_ALOG_IDLE__SHIFT
 
- UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS_MASK
 
- UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS__SHIFT
 
- UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD_MASK
 
- UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD__SHIFT
 
- UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS_MASK
 
- UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS__SHIFT
 
- UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC_MASK
 
- UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC__SHIFT
 
- UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD_MASK
 
- UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD__SHIFT
 
- UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW_MASK
 
- UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW__SHIFT
 
- UTCL1_ALOG__UTCL1_ALOG_MODE_MASK
 
- UTCL1_ALOG__UTCL1_ALOG_MODE__SHIFT
 
- UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS_MASK
 
- UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS__SHIFT
 
- UTCL1_ALOG__UTCL1_ALOG_SPACE_EN_MASK
 
- UTCL1_ALOG__UTCL1_ALOG_SPACE_EN__SHIFT
 
- UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE_MASK
 
- UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE__SHIFT
 
- UTCL1_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
 
- UTCL1_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
 
- UTCL1_CGTT_CLK_CTRL__ON_DELAY_MASK
 
- UTCL1_CGTT_CLK_CTRL__ON_DELAY__SHIFT
 
- UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE0_MASK
 
- UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE0__SHIFT
 
- UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE1_MASK
 
- UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE1__SHIFT
 
- UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE2_MASK
 
- UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE2__SHIFT
 
- UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE3_MASK
 
- UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE3__SHIFT
 
- UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE4_MASK
 
- UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT
 
- UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE5_MASK
 
- UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE5__SHIFT
 
- UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE6_MASK
 
- UTCL1_CGTT_CLK_CTRL__SOFT_OVERRIDE6__SHIFT
 
- UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK
 
- UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT
 
- UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK
 
- UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT
 
- UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK
 
- UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT
 
- UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK
 
- UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT
 
- UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK
 
- UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT
 
- UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK
 
- UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT
 
- UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK
 
- UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT
 
- UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK
 
- UTCL1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT
 
- UTCL1_CTRL__RESERVED_MASK
 
- UTCL1_CTRL__RESERVED__SHIFT
 
- UTCL1_CTRL__UTCL1_CACHE_CORE_BYPASS_MASK
 
- UTCL1_CTRL__UTCL1_CACHE_CORE_BYPASS__SHIFT
 
- UTCL1_CTRL__UTCL1_CACHE_WRITE_PERM_MASK
 
- UTCL1_CTRL__UTCL1_CACHE_WRITE_PERM__SHIFT
 
- UTCL1_CTRL__UTCL1_FORCE_INV_ALL_DONE_MASK
 
- UTCL1_CTRL__UTCL1_FORCE_INV_ALL_DONE__SHIFT
 
- UTCL1_CTRL__UTCL1_FORCE_INV_ALL_MASK
 
- UTCL1_CTRL__UTCL1_FORCE_INV_ALL__SHIFT
 
- UTCL1_CTRL__UTCL1_FORCE_RANGE_INV_TO_VMID_MASK
 
- UTCL1_CTRL__UTCL1_FORCE_RANGE_INV_TO_VMID__SHIFT
 
- UTCL1_CTRL__UTCL1_INV_FILTER_2M_MASK
 
- UTCL1_CTRL__UTCL1_INV_FILTER_2M__SHIFT
 
- UTCL1_CTRL__UTCL1_LARGE_PAGE_SIZE_MASK
 
- UTCL1_CTRL__UTCL1_LARGE_PAGE_SIZE__SHIFT
 
- UTCL1_CTRL__UTCL1_MH_CAM_DUPLICATE_4K_FILTER_MASK
 
- UTCL1_CTRL__UTCL1_MH_CAM_DUPLICATE_4K_FILTER__SHIFT
 
- UTCL1_CTRL__UTCL1_MH_DISABLE_DUPLICATES_MASK
 
- UTCL1_CTRL__UTCL1_MH_DISABLE_DUPLICATES__SHIFT
 
- UTCL1_CTRL__UTCL1_MH_DISABLE_RECENT_BUFFER_MASK
 
- UTCL1_CTRL__UTCL1_MH_DISABLE_RECENT_BUFFER__SHIFT
 
- UTCL1_CTRL__UTCL1_MH_DISABLE_REQUEST_SQUASHING_MASK
 
- UTCL1_CTRL__UTCL1_MH_DISABLE_REQUEST_SQUASHING__SHIFT
 
- UTCL1_CTRL__UTCL1_MH_INV_FRAG_SIZE_OVERRIDE_MASK
 
- UTCL1_CTRL__UTCL1_MH_INV_FRAG_SIZE_OVERRIDE__SHIFT
 
- UTCL1_CTRL__UTCL1_MISS_CC_PRIORITY_MASK
 
- UTCL1_CTRL__UTCL1_MISS_CC_PRIORITY__SHIFT
 
- UTCL1_CTRL__UTCL1_RANGE_INV_FORCE_CHK_ALL_MASK
 
- UTCL1_CTRL__UTCL1_RANGE_INV_FORCE_CHK_ALL__SHIFT
 
- UTCL1_CTRL__UTCL1_REDUCE_CC_SIZE_MASK
 
- UTCL1_CTRL__UTCL1_REDUCE_CC_SIZE__SHIFT
 
- UTCL1_CTRL__UTCL1_REDUCE_MH_CAM_SIZE_MASK
 
- UTCL1_CTRL__UTCL1_REDUCE_MH_CAM_SIZE__SHIFT
 
- UTCL1_CTRL__UTCL1_REDUCE_MH_CFIFO_SIZE_MASK
 
- UTCL1_CTRL__UTCL1_REDUCE_MH_CFIFO_SIZE__SHIFT
 
- UTCL1_CTRL__UTCL1_RMI_BYPASS_MASK
 
- UTCL1_CTRL__UTCL1_RMI_BYPASS__SHIFT
 
- UTCL1_CTRL__UTCL1_RMI_DEDICATED_CACHE_CORE_MASK
 
- UTCL1_CTRL__UTCL1_RMI_DEDICATED_CACHE_CORE__SHIFT
 
- UTCL1_CTRL__UTCL1_SMALL_PAGE_SIZE_MASK
 
- UTCL1_CTRL__UTCL1_SMALL_PAGE_SIZE__SHIFT
 
- UTCL1_CTRL__UTCL1_SQCD_BYPASS_MASK
 
- UTCL1_CTRL__UTCL1_SQCD_BYPASS__SHIFT
 
- UTCL1_CTRL__UTCL1_SQCI_BYPASS_MASK
 
- UTCL1_CTRL__UTCL1_SQCI_BYPASS__SHIFT
 
- UTCL1_CTRL__UTCL1_SQG_BYPASS_MASK
 
- UTCL1_CTRL__UTCL1_SQG_BYPASS__SHIFT
 
- UTCL1_CTRL__UTCL1_TCP_BYPASS_MASK
 
- UTCL1_CTRL__UTCL1_TCP_BYPASS__SHIFT
 
- UTCL1_CTRL__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE_MASK
 
- UTCL1_CTRL__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE__SHIFT
 
- UTCL1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK
 
- UTCL1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT
 
- UTCL1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK
 
- UTCL1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT
 
- UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE_MASK
 
- UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE__SHIFT
 
- UTCL1_PERFCOUNTER0_SELECT__PERF_SEL_MASK
 
- UTCL1_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT
 
- UTCL1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK
 
- UTCL1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT
 
- UTCL1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK
 
- UTCL1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT
 
- UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE_MASK
 
- UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE__SHIFT
 
- UTCL1_PERFCOUNTER1_SELECT__PERF_SEL_MASK
 
- UTCL1_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT
 
- UTCL1_PERF_SEL_BYPASS_REQS
 
- UTCL1_PERF_SEL_HITS
 
- UTCL1_PERF_SEL_HIT_INV_FILTER_REQS
 
- UTCL1_PERF_SEL_MISSES
 
- UTCL1_PERF_SEL_NONE
 
- UTCL1_PERF_SEL_NONRANGE_INV_REQS
 
- UTCL1_PERF_SEL_NUM_BIGK_PAGES
 
- UTCL1_PERF_SEL_NUM_SMALLK_PAGES
 
- UTCL1_PERF_SEL_OUTSTANDING_UTCL2_REQS_ACCUM
 
- UTCL1_PERF_SEL_RANGE_INV_REQS
 
- UTCL1_PERF_SEL_REQS
 
- UTCL1_PERF_SEL_STALL_MH_CAM_FULL
 
- UTCL1_PERF_SEL_STALL_MH_OFIFO_FULL
 
- UTCL1_PERF_SEL_STALL_ON_UTCL2_CREDITS
 
- UTCL1_PERF_SEL_TOTAL_UTCL2_REQS
 
- UTCL1_TYPE_BYPASS
 
- UTCL1_TYPE_NORMAL
 
- UTCL1_TYPE_SHOOTDOWN
 
- UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE_MASK
 
- UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE__SHIFT
 
- UTCL1_XNACK_NO_RETRY
 
- UTCL1_XNACK_PRT
 
- UTCL1_XNACK_RETRY
 
- UTCL1_XNACK_SUCCESS
 
- UTCL2_1_0__SRCID__FAULT
 
- UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK
 
- UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT
 
- UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK
 
- UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT
 
- UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK
 
- UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT
 
- UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK
 
- UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT
 
- UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK
 
- UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT
 
- UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK
 
- UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT
 
- UTCR0
 
- UTCR0_1StpBit
 
- UTCR0_2StpBit
 
- UTCR0_7BitData
 
- UTCR0_8BitData
 
- UTCR0_DSS
 
- UTCR0_EvenPar
 
- UTCR0_OES
 
- UTCR0_OddPar
 
- UTCR0_PE
 
- UTCR0_RCE
 
- UTCR0_RcFlEdg
 
- UTCR0_RcRsEdg
 
- UTCR0_SBS
 
- UTCR0_SCE
 
- UTCR0_Ser2IrDA
 
- UTCR0_TCE
 
- UTCR0_TrFlEdg
 
- UTCR0_TrRsEdg
 
- UTCR1
 
- UTCR1_BRD
 
- UTCR1_BdRtDiv
 
- UTCR1_CeilBdRtDiv
 
- UTCR2
 
- UTCR2_BRD
 
- UTCR2_BdRtDiv
 
- UTCR2_CeilBdRtDiv
 
- UTCR3
 
- UTCR3_BRK
 
- UTCR3_LBM
 
- UTCR3_RIE
 
- UTCR3_RXE
 
- UTCR3_Ser2IrDA
 
- UTCR3_TIE
 
- UTCR3_TXE
 
- UTCR4_HPSIR
 
- UTCR4_HSE
 
- UTCR4_LPM
 
- UTCR4_NRZ
 
- UTCR4_Z1_6us
 
- UTCR4_Z3_16Bit
 
- UTC_0
 
- UTC_0_MASK
 
- UTC_0_SHIFT
 
- UTDR
 
- UTDR_DATA
 
- UTDR_FRE
 
- UTDR_PRE
 
- UTDR_ROR
 
- UTEMP
 
- UTF16_BIG_ENDIAN
 
- UTF16_HOST_ENDIAN
 
- UTF16_LITTLE_ENDIAN
 
- UTF8HANGULLEAF
 
- UTF8NORM_H
 
- UTF8_2_BITS
 
- UTF8_2_MASK
 
- UTF8_3_BITS
 
- UTF8_3_MASK
 
- UTF8_4_BITS
 
- UTF8_4_MASK
 
- UTF8_NAME
 
- UTF8_N_BITS
 
- UTF8_N_MASK
 
- UTF8_V_MASK
 
- UTF8_V_SHIFT
 
- UTHR_FROM_PERIOD_SIZE
 
- UTH_NOCHANGE
 
- UTILITY_DATA_ENABLE
 
- UTILITY_DATA_RESET
 
- UTILITY_FLEX_MULTIWRITE
 
- UTILITY_FLEX_OPERATOR
 
- UTILITY_FLEX_RESET300
 
- UTILITY_FLEX_RESET300_START
 
- UTILITY_FLEX_RESET300_STOP
 
- UTILITY_GET_DATA_STATUS
 
- UTILITY_GET_V8_REG
 
- UTILITY_NAME_LENGTH
 
- UTILITY_SET_BUFFER_SIZE
 
- UTILITY_SET_FILTER
 
- UTILITY_SET_ISO_SIZE
 
- UTILITY_SRAM_READ
 
- UTILITY_SRAM_TESTFILL
 
- UTILITY_SRAM_TESTSET
 
- UTILITY_SRAM_TESTVERIFY
 
- UTILITY_SRAM_WRITE
 
- UTIL_ALL
 
- UTIL_AVG_UNCHANGED
 
- UTIL_CMD_BIT
 
- UTIL_EST_WEIGHT_SHIFT
 
- UTIL_FLOW_OFF
 
- UTIL_FLOW_ON
 
- UTIL_FW_MAJOR
 
- UTIL_FW_MINOR
 
- UTIL_FW_VERSION
 
- UTIL_H
 
- UTIL_PAYLOAD
 
- UTIL_PIN_CTL
 
- UTIL_PIN_ENABLE
 
- UTIL_PIN_MODE_MASK
 
- UTIL_PIN_MODE_PWM
 
- UTIL_PIN_PIPE
 
- UTIL_PIN_PIPE_MASK
 
- UTIL_PIN_POLARITY
 
- UTIL_REMOTE_SHUTDOWN
 
- UTIL_STR_LEN
 
- UTIL_WS2K8_FW_MAJOR
 
- UTIL_WS2K8_FW_VERSION
 
- UTIM
 
- UTIME_NOW
 
- UTIME_OMIT
 
- UTMIPLL_HW_PWRDN_CFG0
 
- UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL
 
- UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE
 
- UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE
 
- UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL
 
- UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE
 
- UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL
 
- UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE
 
- UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE
 
- UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET
 
- UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK
 
- UTMIP_BAT_CHRG_CFG0
 
- UTMIP_BIASPD
 
- UTMIP_BIAS_CFG0
 
- UTMIP_BIAS_CFG1
 
- UTMIP_BIAS_DEBOUNCE_A
 
- UTMIP_BIAS_PDTRK_COUNT
 
- UTMIP_DEBOUNCE_CFG0
 
- UTMIP_DPDM_OBSERVE
 
- UTMIP_DPDM_OBSERVE_SEL
 
- UTMIP_DPDM_OBSERVE_SEL_FS_J
 
- UTMIP_DPDM_OBSERVE_SEL_FS_K
 
- UTMIP_DPDM_OBSERVE_SEL_FS_SE0
 
- UTMIP_DPDM_OBSERVE_SEL_FS_SE1
 
- UTMIP_ELASTIC_LIMIT
 
- UTMIP_FORCE_PD2_POWERDOWN
 
- UTMIP_FORCE_PDCHRP_POWERDOWN
 
- UTMIP_FORCE_PDDISC_POWERDOWN
 
- UTMIP_FORCE_PDDR_POWERDOWN
 
- UTMIP_FORCE_PDZI_POWERDOWN
 
- UTMIP_FORCE_PD_POWERDOWN
 
- UTMIP_FS_PREABMLE_J
 
- UTMIP_HSDISCON_LEVEL
 
- UTMIP_HSDISCON_LEVEL_MSB
 
- UTMIP_HSRX_CFG0
 
- UTMIP_HSRX_CFG1
 
- UTMIP_HSSQUELCH_LEVEL
 
- UTMIP_HS_DISCON_DISABLE
 
- UTMIP_HS_SYNC_START_DLY
 
- UTMIP_IDLE_WAIT
 
- UTMIP_MISC_CFG0
 
- UTMIP_MISC_CFG1
 
- UTMIP_OTGPD
 
- UTMIP_PD_CHRG
 
- UTMIP_PHY_ENABLE
 
- UTMIP_PLLU_ENABLE_DLY_COUNT
 
- UTMIP_PLLU_STABLE_COUNT
 
- UTMIP_PLL_ACTIVE_DLY_COUNT
 
- UTMIP_PLL_CFG1
 
- UTMIP_PLL_CFG1_ENABLE_DLY_COUNT
 
- UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN
 
- UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP
 
- UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN
 
- UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN
 
- UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP
 
- UTMIP_PLL_CFG1_XTAL_FREQ_COUNT
 
- UTMIP_PLL_CFG2
 
- UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT
 
- UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN
 
- UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP
 
- UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN
 
- UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP
 
- UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN
 
- UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP
 
- UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN
 
- UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP
 
- UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN
 
- UTMIP_PLL_CFG2_STABLE_COUNT
 
- UTMIP_RESET
 
- UTMIP_SPARE_CFG0
 
- UTMIP_SUSPEND_EXIT_ON_EDGE
 
- UTMIP_TX_CFG0
 
- UTMIP_XCVR_CFG0
 
- UTMIP_XCVR_CFG1
 
- UTMIP_XCVR_HSSLEW
 
- UTMIP_XCVR_HSSLEW_MSB
 
- UTMIP_XCVR_LSBIAS_SEL
 
- UTMIP_XCVR_LSFSLEW
 
- UTMIP_XCVR_LSRSLEW
 
- UTMIP_XCVR_SETUP
 
- UTMIP_XCVR_SETUP_MSB
 
- UTMIP_XCVR_TERM_RANGE_ADJ
 
- UTMIP_XTAL_FREQ_COUNT
 
- UTMI_8BIT
 
- UTMI_CLK_STABLE_TIME
 
- UTMI_CTRL
 
- UTMI_CTRL_ARC_PULLDN_SHIFT
 
- UTMI_CTRL_INPKT_DELAY_SHIFT
 
- UTMI_CTRL_INPKT_DELAY_SOF_SHIFT
 
- UTMI_CTRL_PLL_PWR_UP_SHIFT
 
- UTMI_CTRL_PU_REF_SHIFT
 
- UTMI_CTRL_PWR_UP_SHIFT
 
- UTMI_CTRL_RXBUF_PDWN
 
- UTMI_CTRL_SUSPEND_SET1
 
- UTMI_CTRL_SUSPEND_SET2
 
- UTMI_CTRL_TXBUF_PDWN
 
- UTMI_CTRL_USB_CLK_EN
 
- UTMI_DBG_CTL
 
- UTMI_IVREF
 
- UTMI_OTG_ADDON
 
- UTMI_OTG_ADDON_OTG_ON
 
- UTMI_OTG_VBUS_VALID
 
- UTMI_PHYIF_16_BIT
 
- UTMI_PHYIF_8_BIT
 
- UTMI_PHY_CLK_VALID_CHK_RETRY
 
- UTMI_PHY_EN
 
- UTMI_PLL
 
- UTMI_PLL_CLK_BLK_EN_SHIFT
 
- UTMI_PLL_FBDIV_MASK
 
- UTMI_PLL_FBDIV_SHIFT
 
- UTMI_PLL_ICP_MASK
 
- UTMI_PLL_ICP_SHIFT
 
- UTMI_PLL_KVCO_MASK
 
- UTMI_PLL_KVCO_SHIFT
 
- UTMI_PLL_PLLCALI12_MASK
 
- UTMI_PLL_PLLCALI12_SHIFT
 
- UTMI_PLL_PLLVDD12_MASK
 
- UTMI_PLL_PLLVDD12_SHIFT
 
- UTMI_PLL_PLLVDD18_MASK
 
- UTMI_PLL_PLLVDD18_SHIFT
 
- UTMI_PLL_REFDIV_MASK
 
- UTMI_PLL_REFDIV_SHIFT
 
- UTMI_RATE
 
- UTMI_REG_SQ_LENGTH_MASK
 
- UTMI_REG_SQ_LENGTH_SHIFT
 
- UTMI_RESERVE
 
- UTMI_REVISION
 
- UTMI_RST_COMPLETE_TIME
 
- UTMI_RX
 
- UTMI_RX_SQ_THRESH_MASK
 
- UTMI_RX_SQ_THRESH_SHIFT
 
- UTMI_T0
 
- UTMI_T1
 
- UTMI_T2
 
- UTMI_T3
 
- UTMI_T4
 
- UTMI_T5
 
- UTMI_TX
 
- UTMI_TX_AMP_MASK
 
- UTMI_TX_AMP_SHIFT
 
- UTMI_TX_CK60_PHSEL_MASK
 
- UTMI_TX_CK60_PHSEL_SHIFT
 
- UTMI_TX_IMPCAL_VTH_MASK
 
- UTMI_TX_IMPCAL_VTH_SHIFT
 
- UTMI_TX_LOW_VDD_EN_SHIFT
 
- UTMI_TX_REG_EXT_FS_RCAL_EN_MASK
 
- UTMI_TX_REG_EXT_FS_RCAL_EN_SHIFT
 
- UTMI_TX_REG_EXT_FS_RCAL_MASK
 
- UTMI_TX_REG_EXT_FS_RCAL_SHIFT
 
- UTMI_TX_TXVDD12_MASK
 
- UTMI_TX_TXVDD12_SHIFT
 
- UTMI_USB_INT
 
- UTP_CMD_TYPE_DEV_MANAGE
 
- UTP_CMD_TYPE_SCSI
 
- UTP_CMD_TYPE_UFS
 
- UTP_CMD_TYPE_UFS_STORAGE
 
- UTP_DBG_RAMS_EN
 
- UTP_DEVICE_MANAGEMENT_FUNCTION
 
- UTP_DEVICE_TO_HOST
 
- UTP_HOST_TO_DEVICE
 
- UTP_NATIVE_UFS_COMMAND
 
- UTP_NO_DATA_TRANSFER
 
- UTP_REQ_DESC_INT_CMD
 
- UTP_SCSI_COMMAND
 
- UTP_TASK_REQ_COMPL
 
- UTP_TASK_REQ_LIST_READY
 
- UTP_TASK_REQ_LIST_RUN_STOP_BIT
 
- UTP_TRANSFER_REQ_COMPL
 
- UTP_TRANSFER_REQ_LIST_READY
 
- UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT
 
- UTSR0
 
- UTSR0_EIF
 
- UTSR0_RBB
 
- UTSR0_REB
 
- UTSR0_RFS
 
- UTSR0_RID
 
- UTSR0_TFS
 
- UTSR0_TO_SM
 
- UTSR1
 
- UTSR1_FRE
 
- UTSR1_PRE
 
- UTSR1_RNE
 
- UTSR1_ROR
 
- UTSR1_TBY
 
- UTSR1_TNF
 
- UTSR1_TO_SM
 
- UTST
 
- UTSTARCOM_PRODUCT_PC5740
 
- UTSTARCOM_PRODUCT_PC5750
 
- UTSTARCOM_PRODUCT_UM150
 
- UTSTARCOM_PRODUCT_UM175_ALLTEL
 
- UTSTARCOM_PRODUCT_UM175_V1
 
- UTSTARCOM_PRODUCT_UM175_V2
 
- UTSTARCOM_VENDOR_ID
 
- UTS_DOMAINNAME
 
- UTS_FRCPERR
 
- UTS_LOOP
 
- UTS_NODENAME
 
- UTS_NS_INDEX
 
- UTS_PROC_DOMAINNAME
 
- UTS_PROC_HOSTNAME
 
- UTS_PROC_OSRELEASE
 
- UTS_PROC_OSTYPE
 
- UTS_PROC_VERSION
 
- UTS_RXEMPTY
 
- UTS_RXFULL
 
- UTS_SOFTRST
 
- UTS_SYSNAME
 
- UTS_TXEMPTY
 
- UTS_TXFULL
 
- UTURN_BC_GSC
 
- UTURN_IOA_RUNWAY
 
- UTX
 
- UTX_ADDR
 
- UTX_BUSY
 
- UTX_CTS_DELTA
 
- UTX_CTS_STAT
 
- UTX_CTS_STATUS
 
- UTX_FIFO_EMPTY
 
- UTX_FIFO_HALF
 
- UTX_IGNORE_CTS
 
- UTX_NOCTS
 
- UTX_SEND_BREAK
 
- UTX_TXDATA
 
- UTX_TXDATA_ADDR
 
- UTX_TXDATA_MASK
 
- UTX_TXDATA_SHIFT
 
- UTX_TX_AVAIL
 
- UT_ASYNC_DATA_ERROR
 
- UT_DATA_ERROR
 
- UT_DATA_EXCEPTION
 
- UT_DATA_PROTECTION
 
- UT_DEFAULT
 
- UT_DEGRADED
 
- UT_DIVISION_BY_ZERO
 
- UT_FP_DISABLED
 
- UT_FP_EXCEPTION_IEEE_754
 
- UT_FP_EXCEPTION_OTHER
 
- UT_ILLEGAL_INSTRUCTION
 
- UT_ILLTRAP_INSTRUCTION
 
- UT_INSTRUCTION_ERROR
 
- UT_INSTRUCTION_EXCEPTION
 
- UT_INSTRUCTION_PROTECTION
 
- UT_MEM_ADDRESS_NOT_ALIGNED
 
- UT_PEER_OUTDATED
 
- UT_PRIVILEGED_ACTION
 
- UT_PRIVILEGED_OPCODE
 
- UT_RD_DELAY
 
- UT_TAG_OVERVIEW
 
- UT_TRAP_INSTRUCTION_16
 
- UT_TRAP_INSTRUCTION_17
 
- UT_TRAP_INSTRUCTION_18
 
- UT_TRAP_INSTRUCTION_19
 
- UT_TRAP_INSTRUCTION_20
 
- UT_TRAP_INSTRUCTION_21
 
- UT_TRAP_INSTRUCTION_22
 
- UT_TRAP_INSTRUCTION_23
 
- UT_TRAP_INSTRUCTION_24
 
- UT_TRAP_INSTRUCTION_25
 
- UT_TRAP_INSTRUCTION_26
 
- UT_TRAP_INSTRUCTION_27
 
- UT_TRAP_INSTRUCTION_28
 
- UT_TRAP_INSTRUCTION_29
 
- UT_TRAP_INSTRUCTION_30
 
- UT_TRAP_INSTRUCTION_31
 
- UU
 
- UUID_BATTERY_THERMAL_LIMIT
 
- UUID_BUFFER_LENGTH
 
- UUID_CACHE_PROPERTIES
 
- UUID_CONTROL_REGION
 
- UUID_DATA_REGION
 
- UUID_DEVICE_LABELING
 
- UUID_DEVICE_PROPERTIES
 
- UUID_DYNAMIC_ENUMERATION
 
- UUID_GPIO_CONTROLLER
 
- UUID_HYPHEN1_OFFSET
 
- UUID_HYPHEN2_OFFSET
 
- UUID_HYPHEN3_OFFSET
 
- UUID_HYPHEN4_OFFSET
 
- UUID_I2C_DEVICE
 
- UUID_INIT
 
- UUID_JUST_CREATED
 
- UUID_LE
 
- UUID_LEN
 
- UUID_MAGIC
 
- UUID_NEW_BM_OFFSET
 
- UUID_NFIT_BUS
 
- UUID_NFIT_DIMM
 
- UUID_NFIT_DIMM_N_HPE1
 
- UUID_NFIT_DIMM_N_HPE2
 
- UUID_NFIT_DIMM_N_HYPERV
 
- UUID_NFIT_DIMM_N_MSFT
 
- UUID_PCI_HOST_BRIDGE
 
- UUID_PERSISTENT_MEMORY
 
- UUID_PERSISTENT_VIRTUAL_CD
 
- UUID_PERSISTENT_VIRTUAL_DISK
 
- UUID_PHYSICAL_PRESENCE
 
- UUID_PHYSICAL_PROPERTY
 
- UUID_PLATFORM_CAPABILITIES
 
- UUID_POWER_BUTTON
 
- UUID_REQUEST
 
- UUID_REQUEST_OLD
 
- UUID_RESPONSE
 
- UUID_SATA_CONTROLLER
 
- UUID_SIZE
 
- UUID_STRING_LEN
 
- UUID_STRING_LENGTH
 
- UUID_THERMAL_EXTENSIONS
 
- UUID_USB_CONTROLLER
 
- UUID_VOLATILE_MEMORY
 
- UUID_VOLATILE_VIRTUAL_CD
 
- UUID_VOLATILE_VIRTUAL_DISK
 
- UU_MSG
 
- UV1H_BAU_DATA_BROADCAST_32
 
- UV1H_BAU_DATA_CONFIG_32
 
- UV1H_EVENT_OCCURRED0_ASIC_TO_L1_MASK
 
- UV1H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT
 
- UV1H_EVENT_OCCURRED0_BAU_DATA_MASK
 
- UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT
 
- UV1H_EVENT_OCCURRED0_EXTIO_INT0_MASK
 
- UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT
 
- UV1H_EVENT_OCCURRED0_EXTIO_INT1_MASK
 
- UV1H_EVENT_OCCURRED0_EXTIO_INT1_SHFT
 
- UV1H_EVENT_OCCURRED0_EXTIO_INT2_MASK
 
- UV1H_EVENT_OCCURRED0_EXTIO_INT2_SHFT
 
- UV1H_EVENT_OCCURRED0_EXTIO_INT3_MASK
 
- UV1H_EVENT_OCCURRED0_EXTIO_INT3_SHFT
 
- UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK
 
- UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT
 
- UV1H_EVENT_OCCURRED0_GR0_AOERR1_MASK
 
- UV1H_EVENT_OCCURRED0_GR0_AOERR1_SHFT
 
- UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK
 
- UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT
 
- UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK
 
- UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT
 
- UV1H_EVENT_OCCURRED0_GR1_AOERR1_MASK
 
- UV1H_EVENT_OCCURRED0_GR1_AOERR1_SHFT
 
- UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK
 
- UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT
 
- UV1H_EVENT_OCCURRED0_IPI_INT_MASK
 
- UV1H_EVENT_OCCURRED0_IPI_INT_SHFT
 
- UV1H_EVENT_OCCURRED0_L1_NMI_INT_MASK
 
- UV1H_EVENT_OCCURRED0_L1_NMI_INT_SHFT
 
- UV1H_EVENT_OCCURRED0_L1_TO_ASIC_MASK
 
- UV1H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT
 
- UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK
 
- UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT
 
- UV1H_EVENT_OCCURRED0_LB_AOERR0_MASK
 
- UV1H_EVENT_OCCURRED0_LB_AOERR0_SHFT
 
- UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK
 
- UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK
 
- UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT
 
- UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK
 
- UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT
 
- UV1H_EVENT_OCCURRED0_LH_AOERR1_MASK
 
- UV1H_EVENT_OCCURRED0_LH_AOERR1_SHFT
 
- UV1H_EVENT_OCCURRED0_LH_HCERR_MASK
 
- UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT
 
- UV1H_EVENT_OCCURRED0_LTC_INT_MASK
 
- UV1H_EVENT_OCCURRED0_LTC_INT_SHFT
 
- UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK
 
- UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT
 
- UV1H_EVENT_OCCURRED0_PROFILE_INT_MASK
 
- UV1H_EVENT_OCCURRED0_PROFILE_INT_SHFT
 
- UV1H_EVENT_OCCURRED0_RH_AOERR1_MASK
 
- UV1H_EVENT_OCCURRED0_RH_AOERR1_SHFT
 
- UV1H_EVENT_OCCURRED0_RH_HCERR_MASK
 
- UV1H_EVENT_OCCURRED0_RH_HCERR_SHFT
 
- UV1H_EVENT_OCCURRED0_RH_VPI_INT_MASK
 
- UV1H_EVENT_OCCURRED0_RH_VPI_INT_SHFT
 
- UV1H_EVENT_OCCURRED0_RTC0_MASK
 
- UV1H_EVENT_OCCURRED0_RTC0_SHFT
 
- UV1H_EVENT_OCCURRED0_RTC1_MASK
 
- UV1H_EVENT_OCCURRED0_RTC1_SHFT
 
- UV1H_EVENT_OCCURRED0_RTC2_MASK
 
- UV1H_EVENT_OCCURRED0_RTC2_SHFT
 
- UV1H_EVENT_OCCURRED0_RTC3_MASK
 
- UV1H_EVENT_OCCURRED0_RTC3_SHFT
 
- UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK
 
- UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT
 
- UV1H_EVENT_OCCURRED0_SI_AOERR1_MASK
 
- UV1H_EVENT_OCCURRED0_SI_AOERR1_SHFT
 
- UV1H_EVENT_OCCURRED0_SI_HCERR_MASK
 
- UV1H_EVENT_OCCURRED0_SI_HCERR_SHFT
 
- UV1H_EVENT_OCCURRED0_STOP_CLOCK_MASK
 
- UV1H_EVENT_OCCURRED0_STOP_CLOCK_SHFT
 
- UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK
 
- UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT
 
- UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK
 
- UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT
 
- UV1H_EVENT_OCCURRED0_XN_AOERR1_MASK
 
- UV1H_EVENT_OCCURRED0_XN_AOERR1_SHFT
 
- UV1H_EVENT_OCCURRED0_XN_HCERR_MASK
 
- UV1H_EVENT_OCCURRED0_XN_HCERR_SHFT
 
- UV1H_EXTIO_INT0_BROADCAST_32
 
- UV1H_GR0_TLB_MMR_CONTROL
 
- UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK
 
- UV1H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT
 
- UV1H_GR0_TLB_MMR_CONTROL_INDEX_MASK
 
- UV1H_GR0_TLB_MMR_CONTROL_INDEX_SHFT
 
- UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK
 
- UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT
 
- UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK
 
- UV1H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT
 
- UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK
 
- UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT
 
- UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK
 
- UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT
 
- UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK
 
- UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT
 
- UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK
 
- UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT
 
- UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK
 
- UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT
 
- UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK
 
- UV1H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT
 
- UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK
 
- UV1H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT
 
- UV1H_GR0_TLB_MMR_READ_DATA_HI
 
- UV1H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK
 
- UV1H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT
 
- UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK
 
- UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT
 
- UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK
 
- UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT
 
- UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK
 
- UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT
 
- UV1H_GR0_TLB_MMR_READ_DATA_LO
 
- UV1H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK
 
- UV1H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT
 
- UV1H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK
 
- UV1H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT
 
- UV1H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK
 
- UV1H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT
 
- UV1H_GR1_TLB_INT0_CONFIG
 
- UV1H_GR1_TLB_INT1_CONFIG
 
- UV1H_GR1_TLB_MMR_CONTROL
 
- UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK
 
- UV1H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT
 
- UV1H_GR1_TLB_MMR_CONTROL_INDEX_MASK
 
- UV1H_GR1_TLB_MMR_CONTROL_INDEX_SHFT
 
- UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK
 
- UV1H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT
 
- UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK
 
- UV1H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT
 
- UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK
 
- UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT
 
- UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK
 
- UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_SHFT
 
- UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_MASK
 
- UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBPGSIZE_SHFT
 
- UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK
 
- UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT
 
- UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_MASK
 
- UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRREG_SHFT
 
- UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK
 
- UV1H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT
 
- UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK
 
- UV1H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT
 
- UV1H_GR1_TLB_MMR_READ_DATA_HI
 
- UV1H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK
 
- UV1H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT
 
- UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK
 
- UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT
 
- UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK
 
- UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT
 
- UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK
 
- UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT
 
- UV1H_GR1_TLB_MMR_READ_DATA_LO
 
- UV1H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK
 
- UV1H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT
 
- UV1H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK
 
- UV1H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT
 
- UV1H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK
 
- UV1H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT
 
- UV1H_INT_CMPC_REAL_TIME_CMPC_MASK
 
- UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT
 
- UV1H_INT_CMPD_REAL_TIME_CMPD_MASK
 
- UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT
 
- UV1H_IPI_INT_32
 
- UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST
 
- UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK
 
- UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT
 
- UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK
 
- UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT
 
- UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST
 
- UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK
 
- UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT
 
- UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL
 
- UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK
 
- UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK
 
- UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT
 
- UV1H_LB_BAU_MISC_CONTROL
 
- UV1H_LB_BAU_MISC_CONTROL_32
 
- UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK
 
- UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT
 
- UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK
 
- UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT
 
- UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK
 
- UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT
 
- UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK
 
- UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT
 
- UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK
 
- UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT
 
- UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK
 
- UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT
 
- UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK
 
- UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT
 
- UV1H_LB_BAU_MISC_CONTROL_FUN_MASK
 
- UV1H_LB_BAU_MISC_CONTROL_FUN_SHFT
 
- UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK
 
- UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
 
- UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK
 
- UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT
 
- UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK
 
- UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT
 
- UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK
 
- UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT
 
- UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK
 
- UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT
 
- UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK
 
- UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT
 
- UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK
 
- UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT
 
- UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK
 
- UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT
 
- UV1H_LB_BAU_SB_ACTIVATION_CONTROL
 
- UV1H_LB_BAU_SB_ACTIVATION_CONTROL_32
 
- UV1H_LB_BAU_SB_ACTIVATION_STATUS_0
 
- UV1H_LB_BAU_SB_ACTIVATION_STATUS_0_32
 
- UV1H_LB_BAU_SB_ACTIVATION_STATUS_1
 
- UV1H_LB_BAU_SB_ACTIVATION_STATUS_1_32
 
- UV1H_LB_BAU_SB_DESCRIPTOR_BASE
 
- UV1H_LB_BAU_SB_DESCRIPTOR_BASE_32
 
- UV1H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK
 
- UV1H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT
 
- UV1H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK
 
- UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK
 
- UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_32
 
- UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK
 
- UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT
 
- UV1H_NODE_ID
 
- UV1H_NODE_ID_FORCE1_MASK
 
- UV1H_NODE_ID_FORCE1_SHFT
 
- UV1H_NODE_ID_MANUFACTURER_MASK
 
- UV1H_NODE_ID_MANUFACTURER_SHFT
 
- UV1H_NODE_ID_NI_PORT_MASK
 
- UV1H_NODE_ID_NI_PORT_SHFT
 
- UV1H_NODE_ID_NODES_PER_BIT_MASK
 
- UV1H_NODE_ID_NODES_PER_BIT_SHFT
 
- UV1H_NODE_ID_NODE_ID_MASK
 
- UV1H_NODE_ID_NODE_ID_SHFT
 
- UV1H_NODE_ID_PART_NUMBER_MASK
 
- UV1H_NODE_ID_PART_NUMBER_SHFT
 
- UV1H_NODE_ID_REVISION_MASK
 
- UV1H_NODE_ID_REVISION_SHFT
 
- UV1H_NODE_PRESENT_TABLE_DEPTH
 
- UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR
 
- UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK
 
- UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT
 
- UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK
 
- UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT
 
- UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK
 
- UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT
 
- UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR
 
- UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK
 
- UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT
 
- UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK
 
- UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT
 
- UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK
 
- UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT
 
- UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR
 
- UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK
 
- UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT
 
- UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK
 
- UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT
 
- UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK
 
- UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT
 
- UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR
 
- UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK
 
- UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 
- UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR
 
- UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK
 
- UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT
 
- UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR
 
- UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK
 
- UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT
 
- UV1H_RH_GAM_CONFIG_MMR
 
- UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK
 
- UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT
 
- UV1H_RH_GAM_CONFIG_MMR_M_SKT_MASK
 
- UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT
 
- UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK
 
- UV1H_RH_GAM_CONFIG_MMR_N_SKT_SHFT
 
- UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR
 
- UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK
 
- UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT
 
- UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK
 
- UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT
 
- UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK
 
- UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT
 
- UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK
 
- UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT
 
- UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR
 
- UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR
 
- UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR
 
- UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK
 
- UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT
 
- UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK
 
- UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT
 
- UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK
 
- UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT
 
- UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK
 
- UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT
 
- UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR
 
- UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH
 
- UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR
 
- UV1H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH
 
- UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR
 
- UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK
 
- UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT
 
- UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK
 
- UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT
 
- UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK
 
- UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT
 
- UV1H_RTC
 
- UV1H_SCRATCH5
 
- UV1H_SCRATCH5_32
 
- UV1H_SCRATCH5_ALIAS
 
- UV1H_SCRATCH5_ALIAS_2
 
- UV1H_SCRATCH5_ALIAS_32
 
- UV1_GLOBAL_MMR32_BASE
 
- UV1_GLOBAL_MMR32_SIZE
 
- UV1_HUB_IS_SUPPORTED
 
- UV1_HUB_PART_NUMBER
 
- UV1_HUB_REVISION_BASE
 
- UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD
 
- UV1_LOCAL_MMR_BASE
 
- UV1_LOCAL_MMR_SIZE
 
- UV1_NET_ENDPOINT_INTD
 
- UV2H_BAU_DATA_BROADCAST_32
 
- UV2H_BAU_DATA_CONFIG_32
 
- UV2H_DESC_BUSY
 
- UV2H_DESC_DEST_PUT_ERR
 
- UV2H_DESC_DEST_STRONG_NACK
 
- UV2H_DESC_DEST_TIMEOUT
 
- UV2H_DESC_IDLE
 
- UV2H_DESC_SOURCE_TIMEOUT
 
- UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK
 
- UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT
 
- UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK
 
- UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT
 
- UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK
 
- UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT
 
- UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK
 
- UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT
 
- UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK
 
- UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT
 
- UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK
 
- UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT
 
- UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK
 
- UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT
 
- UV2H_EVENT_OCCURRED0_IPI_INT_MASK
 
- UV2H_EVENT_OCCURRED0_IPI_INT_SHFT
 
- UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK
 
- UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT
 
- UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK
 
- UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT
 
- UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK
 
- UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT
 
- UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK
 
- UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK
 
- UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT
 
- UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK
 
- UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT
 
- UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK
 
- UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT
 
- UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK
 
- UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT
 
- UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK
 
- UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT
 
- UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK
 
- UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT
 
- UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK
 
- UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT
 
- UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK
 
- UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT
 
- UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK
 
- UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT
 
- UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK
 
- UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT
 
- UV2H_EVENT_OCCURRED0_QP_HCERR_MASK
 
- UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT
 
- UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK
 
- UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT
 
- UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK
 
- UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT
 
- UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK
 
- UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT
 
- UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK
 
- UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT
 
- UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK
 
- UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT
 
- UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK
 
- UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT
 
- UV2H_EVENT_OCCURRED2_32
 
- UV2H_EVENT_OCCURRED2_ALIAS_32
 
- UV2H_EVENT_OCCURRED2_RTC_0_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_0_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_10_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_10_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_11_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_11_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_12_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_12_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_13_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_13_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_14_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_14_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_15_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_15_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_16_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_16_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_17_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_17_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_18_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_18_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_19_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_19_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_1_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_1_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_20_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_20_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_21_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_21_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_22_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_22_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_23_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_23_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_24_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_24_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_25_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_25_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_26_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_26_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_27_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_27_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_28_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_28_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_29_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_29_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_2_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_2_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_30_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_30_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_31_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_31_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_3_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_3_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_4_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_4_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_5_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_5_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_6_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_6_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_7_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_7_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_8_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_8_SHFT
 
- UV2H_EVENT_OCCURRED2_RTC_9_MASK
 
- UV2H_EVENT_OCCURRED2_RTC_9_SHFT
 
- UV2H_EXTIO_INT0_BROADCAST_32
 
- UV2H_GR0_TLB_MMR_CONTROL
 
- UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK
 
- UV2H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT
 
- UV2H_GR0_TLB_MMR_CONTROL_INDEX_MASK
 
- UV2H_GR0_TLB_MMR_CONTROL_INDEX_SHFT
 
- UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK
 
- UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT
 
- UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK
 
- UV2H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT
 
- UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_MASK
 
- UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT
 
- UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK
 
- UV2H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT
 
- UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK
 
- UV2H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT
 
- UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK
 
- UV2H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT
 
- UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK
 
- UV2H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT
 
- UV2H_GR0_TLB_MMR_READ_DATA_HI
 
- UV2H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK
 
- UV2H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT
 
- UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK
 
- UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT
 
- UV2H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK
 
- UV2H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT
 
- UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK
 
- UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT
 
- UV2H_GR0_TLB_MMR_READ_DATA_LO
 
- UV2H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK
 
- UV2H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT
 
- UV2H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK
 
- UV2H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT
 
- UV2H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK
 
- UV2H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT
 
- UV2H_GR1_TLB_INT0_CONFIG
 
- UV2H_GR1_TLB_INT1_CONFIG
 
- UV2H_GR1_TLB_MMR_CONTROL
 
- UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK
 
- UV2H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT
 
- UV2H_GR1_TLB_MMR_CONTROL_INDEX_MASK
 
- UV2H_GR1_TLB_MMR_CONTROL_INDEX_SHFT
 
- UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK
 
- UV2H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT
 
- UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK
 
- UV2H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT
 
- UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_MASK
 
- UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_CON_SHFT
 
- UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_MASK
 
- UV2H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBRAM_SHFT
 
- UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK
 
- UV2H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT
 
- UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK
 
- UV2H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT
 
- UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK
 
- UV2H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT
 
- UV2H_GR1_TLB_MMR_READ_DATA_HI
 
- UV2H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK
 
- UV2H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT
 
- UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK
 
- UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT
 
- UV2H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK
 
- UV2H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT
 
- UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK
 
- UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT
 
- UV2H_GR1_TLB_MMR_READ_DATA_LO
 
- UV2H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK
 
- UV2H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT
 
- UV2H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK
 
- UV2H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT
 
- UV2H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK
 
- UV2H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT
 
- UV2H_IPI_INT_32
 
- UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST
 
- UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK
 
- UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT
 
- UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK
 
- UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT
 
- UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST
 
- UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK
 
- UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT
 
- UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL
 
- UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK
 
- UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK
 
- UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT
 
- UV2H_LB_BAU_MISC_CONTROL
 
- UV2H_LB_BAU_MISC_CONTROL_32
 
- UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK
 
- UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT
 
- UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK
 
- UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT
 
- UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK
 
- UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT
 
- UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK
 
- UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT
 
- UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK
 
- UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT
 
- UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK
 
- UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
 
- UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK
 
- UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT
 
- UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK
 
- UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT
 
- UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK
 
- UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT
 
- UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK
 
- UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT
 
- UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK
 
- UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT
 
- UV2H_LB_BAU_MISC_CONTROL_FUN_MASK
 
- UV2H_LB_BAU_MISC_CONTROL_FUN_SHFT
 
- UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK
 
- UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
 
- UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK
 
- UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT
 
- UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK
 
- UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT
 
- UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK
 
- UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT
 
- UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK
 
- UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT
 
- UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK
 
- UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT
 
- UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK
 
- UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT
 
- UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK
 
- UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT
 
- UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK
 
- UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT
 
- UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK
 
- UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT
 
- UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK
 
- UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT
 
- UV2H_LB_BAU_SB_ACTIVATION_CONTROL
 
- UV2H_LB_BAU_SB_ACTIVATION_CONTROL_32
 
- UV2H_LB_BAU_SB_ACTIVATION_STATUS_0
 
- UV2H_LB_BAU_SB_ACTIVATION_STATUS_0_32
 
- UV2H_LB_BAU_SB_ACTIVATION_STATUS_1
 
- UV2H_LB_BAU_SB_ACTIVATION_STATUS_1_32
 
- UV2H_LB_BAU_SB_ACTIVATION_STATUS_2
 
- UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32
 
- UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK
 
- UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT
 
- UV2H_LB_BAU_SB_DESCRIPTOR_BASE
 
- UV2H_LB_BAU_SB_DESCRIPTOR_BASE_32
 
- UV2H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK
 
- UV2H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT
 
- UV2H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK
 
- UV2H_NODE_ID
 
- UV2H_NODE_ID_FORCE1_MASK
 
- UV2H_NODE_ID_FORCE1_SHFT
 
- UV2H_NODE_ID_MANUFACTURER_MASK
 
- UV2H_NODE_ID_MANUFACTURER_SHFT
 
- UV2H_NODE_ID_NI_PORT_MASK
 
- UV2H_NODE_ID_NI_PORT_SHFT
 
- UV2H_NODE_ID_NODES_PER_BIT_MASK
 
- UV2H_NODE_ID_NODES_PER_BIT_SHFT
 
- UV2H_NODE_ID_NODE_ID_MASK
 
- UV2H_NODE_ID_NODE_ID_SHFT
 
- UV2H_NODE_ID_PART_NUMBER_MASK
 
- UV2H_NODE_ID_PART_NUMBER_SHFT
 
- UV2H_NODE_ID_REVISION_MASK
 
- UV2H_NODE_ID_REVISION_SHFT
 
- UV2H_NODE_PRESENT_TABLE_DEPTH
 
- UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR
 
- UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK
 
- UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT
 
- UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK
 
- UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT
 
- UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK
 
- UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT
 
- UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR
 
- UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK
 
- UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT
 
- UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK
 
- UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT
 
- UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK
 
- UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT
 
- UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR
 
- UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK
 
- UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT
 
- UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK
 
- UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT
 
- UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK
 
- UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT
 
- UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR
 
- UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK
 
- UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 
- UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR
 
- UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK
 
- UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT
 
- UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR
 
- UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK
 
- UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT
 
- UV2H_RH_GAM_CONFIG_MMR
 
- UV2H_RH_GAM_CONFIG_MMR_M_SKT_MASK
 
- UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT
 
- UV2H_RH_GAM_CONFIG_MMR_N_SKT_MASK
 
- UV2H_RH_GAM_CONFIG_MMR_N_SKT_SHFT
 
- UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR
 
- UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK
 
- UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT
 
- UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK
 
- UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT
 
- UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK
 
- UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT
 
- UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR
 
- UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR
 
- UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR
 
- UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK
 
- UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT
 
- UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK
 
- UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT
 
- UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK
 
- UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT
 
- UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK
 
- UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT
 
- UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR
 
- UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH
 
- UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR
 
- UV2H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH
 
- UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR
 
- UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK
 
- UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT
 
- UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK
 
- UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT
 
- UV2H_RTC
 
- UV2H_SCRATCH5
 
- UV2H_SCRATCH5_32
 
- UV2H_SCRATCH5_ALIAS
 
- UV2H_SCRATCH5_ALIAS_2
 
- UV2H_SCRATCH5_ALIAS_32
 
- UV2_ACK_MASK
 
- UV2_ACK_UNITS_SHFT
 
- UV2_EXT_SHFT
 
- UV2_GLOBAL_MMR32_BASE
 
- UV2_GLOBAL_MMR32_SIZE
 
- UV2_HUB_IS_SUPPORTED
 
- UV2_HUB_PART_NUMBER
 
- UV2_HUB_PART_NUMBER_X
 
- UV2_HUB_REVISION_BASE
 
- UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD
 
- UV2_LOCAL_MMR_BASE
 
- UV2_LOCAL_MMR_SIZE
 
- UV2_NET_ENDPOINT_INTD
 
- UV2_OFFSET
 
- UV3H_BAU_DATA_BROADCAST_32
 
- UV3H_BAU_DATA_CONFIG_32
 
- UV3H_EVENT_OCCURRED0_ASIC_TO_L1_MASK
 
- UV3H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT
 
- UV3H_EVENT_OCCURRED0_EXTIO_INT0_MASK
 
- UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT
 
- UV3H_EVENT_OCCURRED0_EXTIO_INT1_MASK
 
- UV3H_EVENT_OCCURRED0_EXTIO_INT1_SHFT
 
- UV3H_EVENT_OCCURRED0_EXTIO_INT2_MASK
 
- UV3H_EVENT_OCCURRED0_EXTIO_INT2_SHFT
 
- UV3H_EVENT_OCCURRED0_EXTIO_INT3_MASK
 
- UV3H_EVENT_OCCURRED0_EXTIO_INT3_SHFT
 
- UV3H_EVENT_OCCURRED0_GR0_AOERR1_MASK
 
- UV3H_EVENT_OCCURRED0_GR0_AOERR1_SHFT
 
- UV3H_EVENT_OCCURRED0_GR1_AOERR1_MASK
 
- UV3H_EVENT_OCCURRED0_GR1_AOERR1_SHFT
 
- UV3H_EVENT_OCCURRED0_IPI_INT_MASK
 
- UV3H_EVENT_OCCURRED0_IPI_INT_SHFT
 
- UV3H_EVENT_OCCURRED0_L1_NMI_INT_MASK
 
- UV3H_EVENT_OCCURRED0_L1_NMI_INT_SHFT
 
- UV3H_EVENT_OCCURRED0_L1_TO_ASIC_MASK
 
- UV3H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT
 
- UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK
 
- UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT
 
- UV3H_EVENT_OCCURRED0_LB_AOERR1_MASK
 
- UV3H_EVENT_OCCURRED0_LB_AOERR1_SHFT
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK
 
- UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT
 
- UV3H_EVENT_OCCURRED0_LH0_AOERR1_MASK
 
- UV3H_EVENT_OCCURRED0_LH0_AOERR1_SHFT
 
- UV3H_EVENT_OCCURRED0_LH1_AOERR1_MASK
 
- UV3H_EVENT_OCCURRED0_LH1_AOERR1_SHFT
 
- UV3H_EVENT_OCCURRED0_NI0_AOERR0_MASK
 
- UV3H_EVENT_OCCURRED0_NI0_AOERR0_SHFT
 
- UV3H_EVENT_OCCURRED0_NI0_AOERR1_MASK
 
- UV3H_EVENT_OCCURRED0_NI0_AOERR1_SHFT
 
- UV3H_EVENT_OCCURRED0_NI1_AOERR0_MASK
 
- UV3H_EVENT_OCCURRED0_NI1_AOERR0_SHFT
 
- UV3H_EVENT_OCCURRED0_NI1_AOERR1_MASK
 
- UV3H_EVENT_OCCURRED0_NI1_AOERR1_SHFT
 
- UV3H_EVENT_OCCURRED0_PROFILE_INT_MASK
 
- UV3H_EVENT_OCCURRED0_PROFILE_INT_SHFT
 
- UV3H_EVENT_OCCURRED0_QP_AOERR0_MASK
 
- UV3H_EVENT_OCCURRED0_QP_AOERR0_SHFT
 
- UV3H_EVENT_OCCURRED0_QP_AOERR1_MASK
 
- UV3H_EVENT_OCCURRED0_QP_AOERR1_SHFT
 
- UV3H_EVENT_OCCURRED0_QP_HCERR_MASK
 
- UV3H_EVENT_OCCURRED0_QP_HCERR_SHFT
 
- UV3H_EVENT_OCCURRED0_RH_AOERR1_MASK
 
- UV3H_EVENT_OCCURRED0_RH_AOERR1_SHFT
 
- UV3H_EVENT_OCCURRED0_RT_AOERR0_MASK
 
- UV3H_EVENT_OCCURRED0_RT_AOERR0_SHFT
 
- UV3H_EVENT_OCCURRED0_RT_AOERR1_MASK
 
- UV3H_EVENT_OCCURRED0_RT_AOERR1_SHFT
 
- UV3H_EVENT_OCCURRED0_STOP_CLOCK_MASK
 
- UV3H_EVENT_OCCURRED0_STOP_CLOCK_SHFT
 
- UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK
 
- UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT
 
- UV3H_EVENT_OCCURRED0_XB_AOERR1_MASK
 
- UV3H_EVENT_OCCURRED0_XB_AOERR1_SHFT
 
- UV3H_EVENT_OCCURRED2_32
 
- UV3H_EVENT_OCCURRED2_ALIAS_32
 
- UV3H_EVENT_OCCURRED2_RTC_0_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_0_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_10_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_10_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_11_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_11_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_12_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_12_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_13_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_13_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_14_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_14_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_15_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_15_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_16_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_16_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_17_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_17_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_18_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_18_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_19_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_19_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_1_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_1_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_20_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_20_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_21_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_21_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_22_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_22_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_23_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_23_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_24_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_24_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_25_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_25_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_26_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_26_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_27_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_27_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_28_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_28_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_29_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_29_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_2_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_2_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_30_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_30_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_31_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_31_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_3_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_3_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_4_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_4_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_5_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_5_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_6_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_6_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_7_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_7_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_8_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_8_SHFT
 
- UV3H_EVENT_OCCURRED2_RTC_9_MASK
 
- UV3H_EVENT_OCCURRED2_RTC_9_SHFT
 
- UV3H_EXTIO_INT0_BROADCAST_32
 
- UV3H_GR0_GAM_GR_CONFIG
 
- UV3H_GR0_GAM_GR_CONFIG_M_SKT_MASK
 
- UV3H_GR0_GAM_GR_CONFIG_M_SKT_SHFT
 
- UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_MASK
 
- UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_SHFT
 
- UV3H_GR0_TLB_MMR_CONTROL
 
- UV3H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK
 
- UV3H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT
 
- UV3H_GR0_TLB_MMR_CONTROL_ECC_SEL_MASK
 
- UV3H_GR0_TLB_MMR_CONTROL_ECC_SEL_SHFT
 
- UV3H_GR0_TLB_MMR_CONTROL_INDEX_MASK
 
- UV3H_GR0_TLB_MMR_CONTROL_INDEX_SHFT
 
- UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK
 
- UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT
 
- UV3H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK
 
- UV3H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT
 
- UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK
 
- UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT
 
- UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK
 
- UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT
 
- UV3H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK
 
- UV3H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT
 
- UV3H_GR0_TLB_MMR_READ_DATA_HI
 
- UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK
 
- UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT
 
- UV3H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK
 
- UV3H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT
 
- UV3H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK
 
- UV3H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT
 
- UV3H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK
 
- UV3H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT
 
- UV3H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK
 
- UV3H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT
 
- UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK
 
- UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT
 
- UV3H_GR0_TLB_MMR_READ_DATA_LO
 
- UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK
 
- UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT
 
- UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK
 
- UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT
 
- UV3H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK
 
- UV3H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT
 
- UV3H_GR1_TLB_INT0_CONFIG
 
- UV3H_GR1_TLB_INT1_CONFIG
 
- UV3H_GR1_TLB_MMR_CONTROL
 
- UV3H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK
 
- UV3H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT
 
- UV3H_GR1_TLB_MMR_CONTROL_ECC_SEL_MASK
 
- UV3H_GR1_TLB_MMR_CONTROL_ECC_SEL_SHFT
 
- UV3H_GR1_TLB_MMR_CONTROL_INDEX_MASK
 
- UV3H_GR1_TLB_MMR_CONTROL_INDEX_SHFT
 
- UV3H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK
 
- UV3H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT
 
- UV3H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK
 
- UV3H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT
 
- UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK
 
- UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT
 
- UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK
 
- UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT
 
- UV3H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK
 
- UV3H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT
 
- UV3H_GR1_TLB_MMR_READ_DATA_HI
 
- UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK
 
- UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT
 
- UV3H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK
 
- UV3H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT
 
- UV3H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK
 
- UV3H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT
 
- UV3H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK
 
- UV3H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT
 
- UV3H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK
 
- UV3H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT
 
- UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK
 
- UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT
 
- UV3H_GR1_TLB_MMR_READ_DATA_LO
 
- UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK
 
- UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT
 
- UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK
 
- UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT
 
- UV3H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK
 
- UV3H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT
 
- UV3H_IPI_INT_32
 
- UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST
 
- UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK
 
- UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT
 
- UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK
 
- UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT
 
- UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST
 
- UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK
 
- UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT
 
- UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL
 
- UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK
 
- UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK
 
- UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL
 
- UV3H_LB_BAU_MISC_CONTROL_32
 
- UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_PREFETCH_HINT_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL_FUN_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_FUN_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT
 
- UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK
 
- UV3H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT
 
- UV3H_LB_BAU_SB_ACTIVATION_CONTROL
 
- UV3H_LB_BAU_SB_ACTIVATION_CONTROL_32
 
- UV3H_LB_BAU_SB_ACTIVATION_STATUS_0
 
- UV3H_LB_BAU_SB_ACTIVATION_STATUS_0_32
 
- UV3H_LB_BAU_SB_ACTIVATION_STATUS_1
 
- UV3H_LB_BAU_SB_ACTIVATION_STATUS_1_32
 
- UV3H_LB_BAU_SB_ACTIVATION_STATUS_2
 
- UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32
 
- UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK
 
- UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT
 
- UV3H_LB_BAU_SB_DESCRIPTOR_BASE
 
- UV3H_LB_BAU_SB_DESCRIPTOR_BASE_32
 
- UV3H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK
 
- UV3H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT
 
- UV3H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK
 
- UV3H_NODE_ID
 
- UV3H_NODE_ID_FORCE1_MASK
 
- UV3H_NODE_ID_FORCE1_SHFT
 
- UV3H_NODE_ID_MANUFACTURER_MASK
 
- UV3H_NODE_ID_MANUFACTURER_SHFT
 
- UV3H_NODE_ID_NI_PORT_MASK
 
- UV3H_NODE_ID_NI_PORT_SHFT
 
- UV3H_NODE_ID_NODES_PER_BIT_MASK
 
- UV3H_NODE_ID_NODES_PER_BIT_SHFT
 
- UV3H_NODE_ID_NODE_ID_MASK
 
- UV3H_NODE_ID_NODE_ID_SHFT
 
- UV3H_NODE_ID_PART_NUMBER_MASK
 
- UV3H_NODE_ID_PART_NUMBER_SHFT
 
- UV3H_NODE_ID_RESERVED_2_MASK
 
- UV3H_NODE_ID_RESERVED_2_SHFT
 
- UV3H_NODE_ID_REVISION_MASK
 
- UV3H_NODE_ID_REVISION_SHFT
 
- UV3H_NODE_ID_ROUTER_SELECT_MASK
 
- UV3H_NODE_ID_ROUTER_SELECT_SHFT
 
- UV3H_NODE_PRESENT_TABLE_DEPTH
 
- UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR
 
- UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK
 
- UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT
 
- UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK
 
- UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT
 
- UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK
 
- UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT
 
- UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR
 
- UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK
 
- UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT
 
- UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK
 
- UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT
 
- UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK
 
- UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT
 
- UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR
 
- UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK
 
- UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT
 
- UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK
 
- UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT
 
- UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK
 
- UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT
 
- UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR
 
- UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK
 
- UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 
- UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR
 
- UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK
 
- UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT
 
- UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR
 
- UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK
 
- UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT
 
- UV3H_RH_GAM_CONFIG_MMR
 
- UV3H_RH_GAM_CONFIG_MMR_M_SKT_MASK
 
- UV3H_RH_GAM_CONFIG_MMR_M_SKT_SHFT
 
- UV3H_RH_GAM_CONFIG_MMR_N_SKT_MASK
 
- UV3H_RH_GAM_CONFIG_MMR_N_SKT_SHFT
 
- UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR
 
- UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK
 
- UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT
 
- UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK
 
- UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT
 
- UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_MASK
 
- UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_SHFT
 
- UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK
 
- UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT
 
- UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR
 
- UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK
 
- UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT
 
- UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK
 
- UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_SHFT
 
- UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK
 
- UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT
 
- UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR
 
- UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK
 
- UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_SHFT
 
- UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_MASK
 
- UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_SHFT
 
- UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK
 
- UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT
 
- UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR
 
- UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR
 
- UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH
 
- UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK
 
- UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_SHFT
 
- UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR
 
- UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH
 
- UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK
 
- UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_SHFT
 
- UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR
 
- UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK
 
- UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT
 
- UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK
 
- UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT
 
- UV3H_RTC
 
- UV3H_SCRATCH5
 
- UV3H_SCRATCH5_32
 
- UV3H_SCRATCH5_ALIAS
 
- UV3H_SCRATCH5_ALIAS_2
 
- UV3H_SCRATCH5_ALIAS_32
 
- UV3_GLOBAL_MMR32_BASE
 
- UV3_GLOBAL_MMR32_SIZE
 
- UV3_HUB_IS_SUPPORTED
 
- UV3_HUB_PART_NUMBER
 
- UV3_HUB_PART_NUMBER_X
 
- UV3_HUB_REVISION_BASE
 
- UV3_LOCAL_MMR_BASE
 
- UV3_LOCAL_MMR_SIZE
 
- UV4AH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK
 
- UV4AH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT
 
- UV4AH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK
 
- UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK
 
- UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK
 
- UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK
 
- UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT
 
- UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK
 
- UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK
 
- UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT
 
- UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK
 
- UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK
 
- UV4A_HUB_IS_SUPPORTED
 
- UV4A_HUB_REVISION_BASE
 
- UV4H_BAU_DATA_BROADCAST_32
 
- UV4H_BAU_DATA_CONFIG_32
 
- UV4H_EVENT_OCCURRED0_ASIC_TO_L1_MASK
 
- UV4H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT
 
- UV4H_EVENT_OCCURRED0_EXTIO_INT0_MASK
 
- UV4H_EVENT_OCCURRED0_EXTIO_INT0_SHFT
 
- UV4H_EVENT_OCCURRED0_EXTIO_INT1_MASK
 
- UV4H_EVENT_OCCURRED0_EXTIO_INT1_SHFT
 
- UV4H_EVENT_OCCURRED0_EXTIO_INT2_MASK
 
- UV4H_EVENT_OCCURRED0_EXTIO_INT2_SHFT
 
- UV4H_EVENT_OCCURRED0_EXTIO_INT3_MASK
 
- UV4H_EVENT_OCCURRED0_EXTIO_INT3_SHFT
 
- UV4H_EVENT_OCCURRED0_GR0_AOERR1_MASK
 
- UV4H_EVENT_OCCURRED0_GR0_AOERR1_SHFT
 
- UV4H_EVENT_OCCURRED0_GR1_AOERR1_MASK
 
- UV4H_EVENT_OCCURRED0_GR1_AOERR1_SHFT
 
- UV4H_EVENT_OCCURRED0_IPI_INT_MASK
 
- UV4H_EVENT_OCCURRED0_IPI_INT_SHFT
 
- UV4H_EVENT_OCCURRED0_KT_AOERR0_MASK
 
- UV4H_EVENT_OCCURRED0_KT_AOERR0_SHFT
 
- UV4H_EVENT_OCCURRED0_KT_AOERR1_MASK
 
- UV4H_EVENT_OCCURRED0_KT_AOERR1_SHFT
 
- UV4H_EVENT_OCCURRED0_KT_HCERR_MASK
 
- UV4H_EVENT_OCCURRED0_KT_HCERR_SHFT
 
- UV4H_EVENT_OCCURRED0_L1_NMI_INT_MASK
 
- UV4H_EVENT_OCCURRED0_L1_NMI_INT_SHFT
 
- UV4H_EVENT_OCCURRED0_L1_TO_ASIC_MASK
 
- UV4H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT
 
- UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK
 
- UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT
 
- UV4H_EVENT_OCCURRED0_LB_AOERR1_MASK
 
- UV4H_EVENT_OCCURRED0_LB_AOERR1_SHFT
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK
 
- UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT
 
- UV4H_EVENT_OCCURRED0_LH0_AOERR1_MASK
 
- UV4H_EVENT_OCCURRED0_LH0_AOERR1_SHFT
 
- UV4H_EVENT_OCCURRED0_LH1_AOERR1_MASK
 
- UV4H_EVENT_OCCURRED0_LH1_AOERR1_SHFT
 
- UV4H_EVENT_OCCURRED0_NI0_AOERR0_MASK
 
- UV4H_EVENT_OCCURRED0_NI0_AOERR0_SHFT
 
- UV4H_EVENT_OCCURRED0_NI0_AOERR1_MASK
 
- UV4H_EVENT_OCCURRED0_NI0_AOERR1_SHFT
 
- UV4H_EVENT_OCCURRED0_NI1_AOERR0_MASK
 
- UV4H_EVENT_OCCURRED0_NI1_AOERR0_SHFT
 
- UV4H_EVENT_OCCURRED0_NI1_AOERR1_MASK
 
- UV4H_EVENT_OCCURRED0_NI1_AOERR1_SHFT
 
- UV4H_EVENT_OCCURRED0_RH_AOERR1_MASK
 
- UV4H_EVENT_OCCURRED0_RH_AOERR1_SHFT
 
- UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_MASK
 
- UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_SHFT
 
- UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_MASK
 
- UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_SHFT
 
- UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_MASK
 
- UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_SHFT
 
- UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_MASK
 
- UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_SHFT
 
- UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_MASK
 
- UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_SHFT
 
- UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_MASK
 
- UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_SHFT
 
- UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_MASK
 
- UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_SHFT
 
- UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_MASK
 
- UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_SHFT
 
- UV4H_EVENT_OCCURRED0_STOP_CLOCK_MASK
 
- UV4H_EVENT_OCCURRED0_STOP_CLOCK_SHFT
 
- UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK
 
- UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT
 
- UV4H_EVENT_OCCURRED0_XB_AOERR1_MASK
 
- UV4H_EVENT_OCCURRED0_XB_AOERR1_SHFT
 
- UV4H_EVENT_OCCURRED2_32
 
- UV4H_EVENT_OCCURRED2_ALIAS_32
 
- UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_MASK
 
- UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_SHFT
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_MASK
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_SHFT
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_MASK
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_SHFT
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_MASK
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_SHFT
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_MASK
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_SHFT
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_MASK
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_SHFT
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_MASK
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_SHFT
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_MASK
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_SHFT
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_MASK
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_SHFT
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_MASK
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_SHFT
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_MASK
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_SHFT
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_MASK
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_SHFT
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_MASK
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_SHFT
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_MASK
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_SHFT
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_MASK
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_SHFT
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_MASK
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_SHFT
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_MASK
 
- UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_0_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_0_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_10_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_10_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_11_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_11_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_12_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_12_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_13_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_13_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_14_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_14_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_15_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_15_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_16_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_16_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_17_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_17_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_18_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_18_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_19_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_19_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_1_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_1_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_20_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_20_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_21_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_21_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_22_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_22_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_23_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_23_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_24_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_24_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_25_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_25_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_26_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_26_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_27_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_27_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_28_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_28_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_29_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_29_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_2_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_2_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_30_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_30_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_31_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_31_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_3_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_3_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_4_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_4_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_5_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_5_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_6_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_6_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_7_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_7_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_8_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_8_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_9_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_9_SHFT
 
- UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_MASK
 
- UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_SHFT
 
- UV4H_EXTIO_INT0_BROADCAST_32
 
- UV4H_GR0_TLB_MMR_CONTROL
 
- UV4H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK
 
- UV4H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT
 
- UV4H_GR0_TLB_MMR_CONTROL_ECC_SEL_MASK
 
- UV4H_GR0_TLB_MMR_CONTROL_ECC_SEL_SHFT
 
- UV4H_GR0_TLB_MMR_CONTROL_INDEX_MASK
 
- UV4H_GR0_TLB_MMR_CONTROL_INDEX_SHFT
 
- UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK
 
- UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT
 
- UV4H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK
 
- UV4H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT
 
- UV4H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK
 
- UV4H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT
 
- UV4H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK
 
- UV4H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT
 
- UV4H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK
 
- UV4H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT
 
- UV4H_GR0_TLB_MMR_CONTROL_PAGE_SIZE_MASK
 
- UV4H_GR0_TLB_MMR_CONTROL_PAGE_SIZE_SHFT
 
- UV4H_GR0_TLB_MMR_READ_DATA_HI
 
- UV4H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK
 
- UV4H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT
 
- UV4H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK
 
- UV4H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT
 
- UV4H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK
 
- UV4H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT
 
- UV4H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK
 
- UV4H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT
 
- UV4H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK
 
- UV4H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT
 
- UV4H_GR0_TLB_MMR_READ_DATA_HI_PNID_MASK
 
- UV4H_GR0_TLB_MMR_READ_DATA_HI_PNID_SHFT
 
- UV4H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK
 
- UV4H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT
 
- UV4H_GR0_TLB_MMR_READ_DATA_LO
 
- UV4H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK
 
- UV4H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT
 
- UV4H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK
 
- UV4H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT
 
- UV4H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK
 
- UV4H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT
 
- UV4H_GR1_TLB_INT0_CONFIG
 
- UV4H_GR1_TLB_INT1_CONFIG
 
- UV4H_GR1_TLB_MMR_CONTROL
 
- UV4H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK
 
- UV4H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT
 
- UV4H_GR1_TLB_MMR_CONTROL_ECC_SEL_MASK
 
- UV4H_GR1_TLB_MMR_CONTROL_ECC_SEL_SHFT
 
- UV4H_GR1_TLB_MMR_CONTROL_INDEX_MASK
 
- UV4H_GR1_TLB_MMR_CONTROL_INDEX_SHFT
 
- UV4H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK
 
- UV4H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT
 
- UV4H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK
 
- UV4H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT
 
- UV4H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK
 
- UV4H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT
 
- UV4H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK
 
- UV4H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT
 
- UV4H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK
 
- UV4H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT
 
- UV4H_GR1_TLB_MMR_CONTROL_PAGE_SIZE_MASK
 
- UV4H_GR1_TLB_MMR_CONTROL_PAGE_SIZE_SHFT
 
- UV4H_GR1_TLB_MMR_READ_DATA_HI
 
- UV4H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK
 
- UV4H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT
 
- UV4H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK
 
- UV4H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT
 
- UV4H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK
 
- UV4H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT
 
- UV4H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK
 
- UV4H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT
 
- UV4H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK
 
- UV4H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT
 
- UV4H_GR1_TLB_MMR_READ_DATA_HI_PNID_MASK
 
- UV4H_GR1_TLB_MMR_READ_DATA_HI_PNID_SHFT
 
- UV4H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK
 
- UV4H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT
 
- UV4H_GR1_TLB_MMR_READ_DATA_LO
 
- UV4H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK
 
- UV4H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT
 
- UV4H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK
 
- UV4H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT
 
- UV4H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK
 
- UV4H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT
 
- UV4H_IPI_INT_32
 
- UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST
 
- UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST
 
- UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL
 
- UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE
 
- UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS
 
- UV4H_LB_BAU_MISC_CONTROL
 
- UV4H_LB_BAU_MISC_CONTROL_32
 
- UV4H_LB_BAU_MISC_CONTROL_ADDRESS_INTERLEAVE_SELECT_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_ADDRESS_INTERLEAVE_SELECT_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_FUN_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_FUN_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_RESERVED_15_19_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_RESERVED_15_19_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_RESERVED_37_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_RESERVED_37_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT
 
- UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK
 
- UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT
 
- UV4H_LB_BAU_SB_ACTIVATION_CONTROL
 
- UV4H_LB_BAU_SB_ACTIVATION_CONTROL_32
 
- UV4H_LB_BAU_SB_ACTIVATION_STATUS_0
 
- UV4H_LB_BAU_SB_ACTIVATION_STATUS_0_32
 
- UV4H_LB_BAU_SB_ACTIVATION_STATUS_1
 
- UV4H_LB_BAU_SB_ACTIVATION_STATUS_1_32
 
- UV4H_LB_BAU_SB_ACTIVATION_STATUS_2
 
- UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_32
 
- UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK
 
- UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT
 
- UV4H_LB_BAU_SB_DESCRIPTOR_BASE
 
- UV4H_LB_BAU_SB_DESCRIPTOR_BASE_32
 
- UV4H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK
 
- UV4H_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT
 
- UV4H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK
 
- UV4H_LB_PROC_INTD_QUEUE_FIRST
 
- UV4H_LB_PROC_INTD_QUEUE_FIRST_FIRST_PAYLOAD_ADDRESS_MASK
 
- UV4H_LB_PROC_INTD_QUEUE_FIRST_FIRST_PAYLOAD_ADDRESS_SHFT
 
- UV4H_LB_PROC_INTD_QUEUE_LAST
 
- UV4H_LB_PROC_INTD_QUEUE_LAST_LAST_PAYLOAD_ADDRESS_MASK
 
- UV4H_LB_PROC_INTD_QUEUE_LAST_LAST_PAYLOAD_ADDRESS_SHFT
 
- UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR
 
- UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR_SOFT_ACK_PENDING_FLAGS_MASK
 
- UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR_SOFT_ACK_PENDING_FLAGS_SHFT
 
- UV4H_LB_PROC_INTD_SOFT_ACK_PENDING
 
- UV4H_LB_PROC_INTD_SOFT_ACK_PENDING_SOFT_ACK_FLAGS_MASK
 
- UV4H_LB_PROC_INTD_SOFT_ACK_PENDING_SOFT_ACK_FLAGS_SHFT
 
- UV4H_NODE_ID
 
- UV4H_NODE_ID_FORCE1_MASK
 
- UV4H_NODE_ID_FORCE1_SHFT
 
- UV4H_NODE_ID_MANUFACTURER_MASK
 
- UV4H_NODE_ID_MANUFACTURER_SHFT
 
- UV4H_NODE_ID_NI_PORT_MASK
 
- UV4H_NODE_ID_NI_PORT_SHFT
 
- UV4H_NODE_ID_NODES_PER_BIT_MASK
 
- UV4H_NODE_ID_NODES_PER_BIT_SHFT
 
- UV4H_NODE_ID_NODE_ID_MASK
 
- UV4H_NODE_ID_NODE_ID_SHFT
 
- UV4H_NODE_ID_PART_NUMBER_MASK
 
- UV4H_NODE_ID_PART_NUMBER_SHFT
 
- UV4H_NODE_ID_RESERVED_2_MASK
 
- UV4H_NODE_ID_RESERVED_2_SHFT
 
- UV4H_NODE_ID_REVISION_MASK
 
- UV4H_NODE_ID_REVISION_SHFT
 
- UV4H_NODE_ID_ROUTER_SELECT_MASK
 
- UV4H_NODE_ID_ROUTER_SELECT_SHFT
 
- UV4H_NODE_PRESENT_TABLE_DEPTH
 
- UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR
 
- UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK
 
- UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT
 
- UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK
 
- UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT
 
- UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK
 
- UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT
 
- UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR
 
- UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK
 
- UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT
 
- UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK
 
- UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT
 
- UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK
 
- UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT
 
- UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR
 
- UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK
 
- UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT
 
- UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK
 
- UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT
 
- UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK
 
- UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT
 
- UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR
 
- UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK
 
- UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 
- UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR
 
- UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK
 
- UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT
 
- UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR
 
- UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK
 
- UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT
 
- UV4H_RH_GAM_CONFIG_MMR
 
- UV4H_RH_GAM_CONFIG_MMR_N_SKT_MASK
 
- UV4H_RH_GAM_CONFIG_MMR_N_SKT_SHFT
 
- UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR
 
- UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK
 
- UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT
 
- UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK
 
- UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT
 
- UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK
 
- UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT
 
- UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR
 
- UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK
 
- UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT
 
- UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK
 
- UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_SHFT
 
- UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK
 
- UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT
 
- UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR
 
- UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK
 
- UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_SHFT
 
- UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_MASK
 
- UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_ENABLE_SHFT
 
- UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK
 
- UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT
 
- UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR
 
- UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR
 
- UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH
 
- UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK
 
- UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_SHFT
 
- UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR
 
- UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH
 
- UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK
 
- UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_SHFT
 
- UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR
 
- UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK
 
- UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT
 
- UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK
 
- UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT
 
- UV4H_RTC
 
- UV4H_SCRATCH5
 
- UV4H_SCRATCH5_32
 
- UV4H_SCRATCH5_ALIAS
 
- UV4H_SCRATCH5_ALIAS_2
 
- UV4H_SCRATCH5_ALIAS_32
 
- UV4_GLOBAL_MMR32_BASE
 
- UV4_GLOBAL_MMR32_SIZE
 
- UV4_HUB_IS_SUPPORTED
 
- UV4_HUB_PART_NUMBER
 
- UV4_HUB_REVISION_BASE
 
- UV4_LOCAL_MMR_BASE
 
- UV4_LOCAL_MMR_SIZE
 
- UV8_1X8
 
- UVAD_J0
 
- UVAD_J1
 
- UVCG_CTRL_HDR_ATTR
 
- UVCG_DEFAULT_CAMERA_ATTR
 
- UVCG_DEFAULT_COLOR_MATCHING_ATTR
 
- UVCG_DEFAULT_OUTPUT_ATTR
 
- UVCG_DEFAULT_PROCESSING_ATTR
 
- UVCG_FORMAT
 
- UVCG_FRAME
 
- UVCG_FRAME_ATTR
 
- UVCG_HEADER
 
- UVCG_MJPEG
 
- UVCG_MJPEG_ATTR
 
- UVCG_MJPEG_ATTR_RO
 
- UVCG_OPTS_ATTR
 
- UVCG_STREAMING_CONTROL_SIZE
 
- UVCG_STREAMING_HEADER_ATTR
 
- UVCG_UNCOMPRESSED
 
- UVCG_UNCOMPRESSED_ATTR
 
- UVCG_UNCOMPRESSED_ATTR_RO
 
- UVCIOC_CTRL_MAP
 
- UVCIOC_CTRL_MAP32
 
- UVCIOC_CTRL_QUERY
 
- UVCIOC_CTRL_QUERY32
 
- UVCIOC_SEND_RESPONSE
 
- UVC_ATTR
 
- UVC_ATTR_RO
 
- UVC_BUF_STATE_ACTIVE
 
- UVC_BUF_STATE_DONE
 
- UVC_BUF_STATE_ERROR
 
- UVC_BUF_STATE_IDLE
 
- UVC_BUF_STATE_QUEUED
 
- UVC_BUF_STATE_READY
 
- UVC_CMD_QUI
 
- UVC_CMD_REMOVE_SHARED_ACCESS
 
- UVC_CMD_SET_SHARED_ACCESS
 
- UVC_COMPONENT_CONNECTOR
 
- UVC_COMPOSITE_CONNECTOR
 
- UVC_CONFIGFS_H
 
- UVC_CONTROL_CAP_ASYNCHRONOUS
 
- UVC_CONTROL_CAP_AUTOUPDATE
 
- UVC_CONTROL_CAP_DISABLED
 
- UVC_CONTROL_CAP_GET
 
- UVC_CONTROL_CAP_SET
 
- UVC_COPY_DESCRIPTOR
 
- UVC_COPY_DESCRIPTORS
 
- UVC_CTRL_CONTROL_TIMEOUT
 
- UVC_CTRL_DATA_BACKUP
 
- UVC_CTRL_DATA_CURRENT
 
- UVC_CTRL_DATA_DEF
 
- UVC_CTRL_DATA_LAST
 
- UVC_CTRL_DATA_MAX
 
- UVC_CTRL_DATA_MIN
 
- UVC_CTRL_DATA_RES
 
- UVC_CTRL_DATA_TYPE_BITMASK
 
- UVC_CTRL_DATA_TYPE_BOOLEAN
 
- UVC_CTRL_DATA_TYPE_ENUM
 
- UVC_CTRL_DATA_TYPE_RAW
 
- UVC_CTRL_DATA_TYPE_SIGNED
 
- UVC_CTRL_DATA_TYPE_UNSIGNED
 
- UVC_CTRL_FAILURE_CHANGE
 
- UVC_CTRL_FLAG_ASYNCHRONOUS
 
- UVC_CTRL_FLAG_AUTO_UPDATE
 
- UVC_CTRL_FLAG_GET_CUR
 
- UVC_CTRL_FLAG_GET_DEF
 
- UVC_CTRL_FLAG_GET_MAX
 
- UVC_CTRL_FLAG_GET_MIN
 
- UVC_CTRL_FLAG_GET_RANGE
 
- UVC_CTRL_FLAG_GET_RES
 
- UVC_CTRL_FLAG_RESTORE
 
- UVC_CTRL_FLAG_SET_CUR
 
- UVC_CTRL_INFO_CHANGE
 
- UVC_CTRL_MAX_CHANGE
 
- UVC_CTRL_MIN_CHANGE
 
- UVC_CTRL_STREAMING_TIMEOUT
 
- UVC_CTRL_VALUE_CHANGE
 
- UVC_CT_AE_MODE_CONTROL
 
- UVC_CT_AE_PRIORITY_CONTROL
 
- UVC_CT_CONTROL_UNDEFINED
 
- UVC_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL
 
- UVC_CT_EXPOSURE_TIME_RELATIVE_CONTROL
 
- UVC_CT_FOCUS_ABSOLUTE_CONTROL
 
- UVC_CT_FOCUS_AUTO_CONTROL
 
- UVC_CT_FOCUS_RELATIVE_CONTROL
 
- UVC_CT_IRIS_ABSOLUTE_CONTROL
 
- UVC_CT_IRIS_RELATIVE_CONTROL
 
- UVC_CT_PANTILT_ABSOLUTE_CONTROL
 
- UVC_CT_PANTILT_RELATIVE_CONTROL
 
- UVC_CT_PRIVACY_CONTROL
 
- UVC_CT_ROLL_ABSOLUTE_CONTROL
 
- UVC_CT_ROLL_RELATIVE_CONTROL
 
- UVC_CT_SCANNING_MODE_CONTROL
 
- UVC_CT_ZOOM_ABSOLUTE_CONTROL
 
- UVC_CT_ZOOM_RELATIVE_CONTROL
 
- UVC_DEBUGFS_BUF_SIZE
 
- UVC_DT_CAMERA_TERMINAL_SIZE
 
- UVC_DT_COLOR_MATCHING_SIZE
 
- UVC_DT_CONTROL_ENDPOINT_SIZE
 
- UVC_DT_EXTENSION_UNIT_SIZE
 
- UVC_DT_FORMAT_MJPEG_SIZE
 
- UVC_DT_FORMAT_UNCOMPRESSED_SIZE
 
- UVC_DT_FRAME_MJPEG_SIZE
 
- UVC_DT_FRAME_UNCOMPRESSED_SIZE
 
- UVC_DT_HEADER_SIZE
 
- UVC_DT_INPUT_HEADER_SIZE
 
- UVC_DT_INPUT_TERMINAL_SIZE
 
- UVC_DT_OUTPUT_HEADER_SIZE
 
- UVC_DT_OUTPUT_TERMINAL_SIZE
 
- UVC_DT_PROCESSING_UNIT_SIZE
 
- UVC_DT_SELECTOR_UNIT_SIZE
 
- UVC_ENTITY_FLAG_DEFAULT
 
- UVC_ENTITY_IS_ITERM
 
- UVC_ENTITY_IS_OTERM
 
- UVC_ENTITY_IS_TERM
 
- UVC_ENTITY_IS_UNIT
 
- UVC_ENTITY_TYPE
 
- UVC_EP_ENDPOINT
 
- UVC_EP_GENERAL
 
- UVC_EP_INTERRUPT
 
- UVC_EP_UNDEFINED
 
- UVC_EVENT_CONNECT
 
- UVC_EVENT_DATA
 
- UVC_EVENT_DISCONNECT
 
- UVC_EVENT_FIRST
 
- UVC_EVENT_LAST
 
- UVC_EVENT_SETUP
 
- UVC_EVENT_STREAMOFF
 
- UVC_EVENT_STREAMON
 
- UVC_EXTENSION_UNIT_DESCRIPTOR
 
- UVC_EXTERNAL_VENDOR_SPECIFIC
 
- UVC_FMT_FLAG_COMPRESSED
 
- UVC_FMT_FLAG_STREAM
 
- UVC_FRAME_MJPEG
 
- UVC_FRAME_UNCOMPRESSED
 
- UVC_GET_CUR
 
- UVC_GET_DEF
 
- UVC_GET_INFO
 
- UVC_GET_LEN
 
- UVC_GET_MAX
 
- UVC_GET_MIN
 
- UVC_GET_RES
 
- UVC_GUID_FORMAT_BA81
 
- UVC_GUID_FORMAT_BG16
 
- UVC_GUID_FORMAT_BGR3
 
- UVC_GUID_FORMAT_BY8
 
- UVC_GUID_FORMAT_CNF4
 
- UVC_GUID_FORMAT_D3DFMT_L8
 
- UVC_GUID_FORMAT_GB16
 
- UVC_GUID_FORMAT_GBRG
 
- UVC_GUID_FORMAT_GR16
 
- UVC_GUID_FORMAT_GRBG
 
- UVC_GUID_FORMAT_H264
 
- UVC_GUID_FORMAT_I420
 
- UVC_GUID_FORMAT_INVI
 
- UVC_GUID_FORMAT_INVZ
 
- UVC_GUID_FORMAT_INZI
 
- UVC_GUID_FORMAT_KSMEDIA_L8_IR
 
- UVC_GUID_FORMAT_M420
 
- UVC_GUID_FORMAT_MJPEG
 
- UVC_GUID_FORMAT_NV12
 
- UVC_GUID_FORMAT_RG16
 
- UVC_GUID_FORMAT_RGBP
 
- UVC_GUID_FORMAT_RGGB
 
- UVC_GUID_FORMAT_RW10
 
- UVC_GUID_FORMAT_UYVY
 
- UVC_GUID_FORMAT_Y10
 
- UVC_GUID_FORMAT_Y12
 
- UVC_GUID_FORMAT_Y12I
 
- UVC_GUID_FORMAT_Y16
 
- UVC_GUID_FORMAT_Y8
 
- UVC_GUID_FORMAT_Y800
 
- UVC_GUID_FORMAT_Y8I
 
- UVC_GUID_FORMAT_YUY2
 
- UVC_GUID_FORMAT_YUY2_ISIGHT
 
- UVC_GUID_FORMAT_YV12
 
- UVC_GUID_FORMAT_Z16
 
- UVC_GUID_UVC_CAMERA
 
- UVC_GUID_UVC_MEDIA_TRANSPORT_INPUT
 
- UVC_GUID_UVC_OUTPUT
 
- UVC_GUID_UVC_PROCESSING
 
- UVC_GUID_UVC_SELECTOR
 
- UVC_HANDLE_ACTIVE
 
- UVC_HANDLE_PASSIVE
 
- UVC_HEADER_DESCRIPTOR
 
- UVC_INFO_META
 
- UVC_INFO_QUIRK
 
- UVC_INPUT_HEADER_DESCRIPTOR
 
- UVC_INTF_VIDEO_CONTROL
 
- UVC_INTF_VIDEO_STREAMING
 
- UVC_ITT_CAMERA
 
- UVC_ITT_MEDIA_TRANSPORT_INPUT
 
- UVC_ITT_VENDOR_SPECIFIC
 
- UVC_MAX_CONTROL_MAPPINGS
 
- UVC_MAX_CONTROL_MENU_ENTRIES
 
- UVC_MAX_EVENTS
 
- UVC_MAX_FRAME_SIZE
 
- UVC_MAX_PACKETS
 
- UVC_MAX_REQUEST_SIZE
 
- UVC_MAX_STATUS_SIZE
 
- UVC_MAX_VIDEO_BUFFERS
 
- UVC_METATADA_BUF_SIZE
 
- UVC_NUM_REQUESTS
 
- UVC_OTT_DISPLAY
 
- UVC_OTT_MEDIA_TRANSPORT_OUTPUT
 
- UVC_OTT_VENDOR_SPECIFIC
 
- UVC_OUTPUT_HEADER_DESCRIPTOR
 
- UVC_PC_PROTOCOL_15
 
- UVC_PC_PROTOCOL_UNDEFINED
 
- UVC_PU_ANALOG_LOCK_STATUS_CONTROL
 
- UVC_PU_ANALOG_VIDEO_STANDARD_CONTROL
 
- UVC_PU_BACKLIGHT_COMPENSATION_CONTROL
 
- UVC_PU_BRIGHTNESS_CONTROL
 
- UVC_PU_CONTRAST_CONTROL
 
- UVC_PU_CONTROL_UNDEFINED
 
- UVC_PU_DIGITAL_MULTIPLIER_CONTROL
 
- UVC_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL
 
- UVC_PU_GAIN_CONTROL
 
- UVC_PU_GAMMA_CONTROL
 
- UVC_PU_HUE_AUTO_CONTROL
 
- UVC_PU_HUE_CONTROL
 
- UVC_PU_POWER_LINE_FREQUENCY_CONTROL
 
- UVC_PU_SATURATION_CONTROL
 
- UVC_PU_SHARPNESS_CONTROL
 
- UVC_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL
 
- UVC_PU_WHITE_BALANCE_COMPONENT_CONTROL
 
- UVC_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL
 
- UVC_PU_WHITE_BALANCE_TEMPERATURE_CONTROL
 
- UVC_QUEUE_DISCONNECTED
 
- UVC_QUEUE_DROP_CORRUPTED
 
- UVC_QUEUE_DROP_INCOMPLETE
 
- UVC_QUEUE_PAUSED
 
- UVC_QUIRK_BUILTIN_ISIGHT
 
- UVC_QUIRK_FIX_BANDWIDTH
 
- UVC_QUIRK_FORCE_BPP
 
- UVC_QUIRK_FORCE_Y8
 
- UVC_QUIRK_IGNORE_SELECTOR_UNIT
 
- UVC_QUIRK_PROBE_DEF
 
- UVC_QUIRK_PROBE_EXTRAFIELDS
 
- UVC_QUIRK_PROBE_MINMAX
 
- UVC_QUIRK_RESTORE_CTRLS_ON_INIT
 
- UVC_QUIRK_RESTRICT_FRAME_RATE
 
- UVC_QUIRK_STATUS_INTERVAL
 
- UVC_QUIRK_STREAM_NO_FID
 
- UVC_RC_EXECUTED
 
- UVC_RC_INV_CMD
 
- UVC_RC_INV_LEN
 
- UVC_RC_INV_STATE
 
- UVC_RC_NO_RESUME
 
- UVC_RC_UNDEFINED
 
- UVC_SC_UNDEFINED
 
- UVC_SC_VIDEOCONTROL
 
- UVC_SC_VIDEOSTREAMING
 
- UVC_SC_VIDEO_INTERFACE_COLLECTION
 
- UVC_SELECTOR_UNIT_DESCRIPTOR
 
- UVC_SET_CUR
 
- UVC_STATE_CONNECTED
 
- UVC_STATE_DISCONNECTED
 
- UVC_STATE_STREAMING
 
- UVC_STATUS_MAX_PACKET_SIZE
 
- UVC_STATUS_TYPE_CONTROL
 
- UVC_STATUS_TYPE_STREAMING
 
- UVC_STREAM_EOF
 
- UVC_STREAM_EOH
 
- UVC_STREAM_ERR
 
- UVC_STREAM_FID
 
- UVC_STREAM_PTS
 
- UVC_STREAM_RES
 
- UVC_STREAM_SCR
 
- UVC_STREAM_STI
 
- UVC_STRING_CONTROL_IDX
 
- UVC_STRING_STREAMING_IDX
 
- UVC_SU_CONTROL_UNDEFINED
 
- UVC_SU_INPUT_SELECT_CONTROL
 
- UVC_SVIDEO_CONNECTOR
 
- UVC_TERM_DIRECTION
 
- UVC_TERM_INPUT
 
- UVC_TERM_OUTPUT
 
- UVC_TE_CONTROL_UNDEFINED
 
- UVC_TRACE_CALLS
 
- UVC_TRACE_CAPTURE
 
- UVC_TRACE_CLOCK
 
- UVC_TRACE_CONTROL
 
- UVC_TRACE_DESCR
 
- UVC_TRACE_FORMAT
 
- UVC_TRACE_FRAME
 
- UVC_TRACE_IOCTL
 
- UVC_TRACE_PROBE
 
- UVC_TRACE_STATS
 
- UVC_TRACE_STATUS
 
- UVC_TRACE_SUSPEND
 
- UVC_TRACE_VIDEO
 
- UVC_TT_STREAMING
 
- UVC_TT_VENDOR_SPECIFIC
 
- UVC_URBS
 
- UVC_VC_CONTROL_UNDEFINED
 
- UVC_VC_DESCRIPTOR_UNDEFINED
 
- UVC_VC_EXTENSION_UNIT
 
- UVC_VC_HEADER
 
- UVC_VC_INPUT_TERMINAL
 
- UVC_VC_OUTPUT_TERMINAL
 
- UVC_VC_PROCESSING_UNIT
 
- UVC_VC_REQUEST_ERROR_CODE_CONTROL
 
- UVC_VC_SELECTOR_UNIT
 
- UVC_VC_VIDEO_POWER_MODE_CONTROL
 
- UVC_VS_COLORFORMAT
 
- UVC_VS_COMMIT_CONTROL
 
- UVC_VS_CONTROL_UNDEFINED
 
- UVC_VS_FORMAT_DV
 
- UVC_VS_FORMAT_FRAME_BASED
 
- UVC_VS_FORMAT_MJPEG
 
- UVC_VS_FORMAT_MPEG2TS
 
- UVC_VS_FORMAT_STREAM_BASED
 
- UVC_VS_FORMAT_UNCOMPRESSED
 
- UVC_VS_FRAME_FRAME_BASED
 
- UVC_VS_FRAME_MJPEG
 
- UVC_VS_FRAME_UNCOMPRESSED
 
- UVC_VS_GENERATE_KEY_FRAME_CONTROL
 
- UVC_VS_INPUT_HEADER
 
- UVC_VS_OUTPUT_HEADER
 
- UVC_VS_PROBE_CONTROL
 
- UVC_VS_STILL_COMMIT_CONTROL
 
- UVC_VS_STILL_IMAGE_FRAME
 
- UVC_VS_STILL_IMAGE_TRIGGER_CONTROL
 
- UVC_VS_STILL_PROBE_CONTROL
 
- UVC_VS_STREAM_ERROR_CODE_CONTROL
 
- UVC_VS_SYNC_DELAY_CONTROL
 
- UVC_VS_UNDEFINED
 
- UVC_VS_UPDATE_FRAME_SEGMENT_CONTROL
 
- UVC_WARN_MINMAX
 
- UVC_WARN_PROBE_DEF
 
- UVC_WARN_XU_GET_RES
 
- UVD0_BASE__INST0_SEG0
 
- UVD0_BASE__INST0_SEG1
 
- UVD0_BASE__INST0_SEG2
 
- UVD0_BASE__INST0_SEG3
 
- UVD0_BASE__INST0_SEG4
 
- UVD0_BASE__INST1_SEG0
 
- UVD0_BASE__INST1_SEG1
 
- UVD0_BASE__INST1_SEG2
 
- UVD0_BASE__INST1_SEG3
 
- UVD0_BASE__INST1_SEG4
 
- UVD0_BASE__INST2_SEG0
 
- UVD0_BASE__INST2_SEG1
 
- UVD0_BASE__INST2_SEG2
 
- UVD0_BASE__INST2_SEG3
 
- UVD0_BASE__INST2_SEG4
 
- UVD0_BASE__INST3_SEG0
 
- UVD0_BASE__INST3_SEG1
 
- UVD0_BASE__INST3_SEG2
 
- UVD0_BASE__INST3_SEG3
 
- UVD0_BASE__INST3_SEG4
 
- UVD0_BASE__INST4_SEG0
 
- UVD0_BASE__INST4_SEG1
 
- UVD0_BASE__INST4_SEG2
 
- UVD0_BASE__INST4_SEG3
 
- UVD0_BASE__INST4_SEG4
 
- UVD0_BASE__INST5_SEG0
 
- UVD0_BASE__INST5_SEG1
 
- UVD0_BASE__INST5_SEG2
 
- UVD0_BASE__INST5_SEG3
 
- UVD0_BASE__INST5_SEG4
 
- UVD0_BASE__INST6_SEG0
 
- UVD0_BASE__INST6_SEG1
 
- UVD0_BASE__INST6_SEG2
 
- UVD0_BASE__INST6_SEG3
 
- UVD0_BASE__INST6_SEG4
 
- UVD7_MAX_HW_INSTANCES_VEGA20
 
- UVDClockInfo
 
- UVDClockInfoArray
 
- UVDFC_BITSTREAM_ADDR
 
- UVDFC_BITSTREAM_SIZE
 
- UVDFC_DECODED_ADDR
 
- UVDFC_DISPLAY_ADDR
 
- UVDFC_DISPLAY_PITCH
 
- UVDFC_DISPLAY_TILING
 
- UVDFC_EOD
 
- UVDFC_FENCE
 
- UVDFC_ITBUF_ADDR
 
- UVDFC_MBLOCK_ADDR
 
- UVDFC_TRAP
 
- UVDFirmwareCommand
 
- UVD_4_0_D_H
 
- UVD_4_0_SH_MASK_H
 
- UVD_4_2_D_H
 
- UVD_4_2_SH_MASK_H
 
- UVD_5_0_D_H
 
- UVD_5_0_ENUM_H
 
- UVD_5_0_SH_MASK_H
 
- UVD_6_0_D_H
 
- UVD_6_0_ENUM_H
 
- UVD_6_0_SH_MASK_H
 
- UVD_7_0__SRCID__UVD_ENC_GEN_PURP
 
- UVD_7_0__SRCID__UVD_ENC_LOW_LATENCY
 
- UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT
 
- UVD_BASE_SI
 
- UVD_BASE__INST0_SEG0
 
- UVD_BASE__INST0_SEG1
 
- UVD_BASE__INST0_SEG2
 
- UVD_BASE__INST0_SEG3
 
- UVD_BASE__INST0_SEG4
 
- UVD_BASE__INST0_SEG5
 
- UVD_BASE__INST1_SEG0
 
- UVD_BASE__INST1_SEG1
 
- UVD_BASE__INST1_SEG2
 
- UVD_BASE__INST1_SEG3
 
- UVD_BASE__INST1_SEG4
 
- UVD_BASE__INST1_SEG5
 
- UVD_BASE__INST2_SEG0
 
- UVD_BASE__INST2_SEG1
 
- UVD_BASE__INST2_SEG2
 
- UVD_BASE__INST2_SEG3
 
- UVD_BASE__INST2_SEG4
 
- UVD_BASE__INST2_SEG5
 
- UVD_BASE__INST3_SEG0
 
- UVD_BASE__INST3_SEG1
 
- UVD_BASE__INST3_SEG2
 
- UVD_BASE__INST3_SEG3
 
- UVD_BASE__INST3_SEG4
 
- UVD_BASE__INST3_SEG5
 
- UVD_BASE__INST4_SEG0
 
- UVD_BASE__INST4_SEG1
 
- UVD_BASE__INST4_SEG2
 
- UVD_BASE__INST4_SEG3
 
- UVD_BASE__INST4_SEG4
 
- UVD_BASE__INST4_SEG5
 
- UVD_BASE__INST5_SEG0
 
- UVD_BASE__INST5_SEG1
 
- UVD_BASE__INST5_SEG2
 
- UVD_BASE__INST5_SEG3
 
- UVD_BASE__INST5_SEG4
 
- UVD_BASE__INST5_SEG5
 
- UVD_BASE__INST6_SEG0
 
- UVD_BASE__INST6_SEG1
 
- UVD_BASE__INST6_SEG2
 
- UVD_BASE__INST6_SEG3
 
- UVD_BASE__INST6_SEG4
 
- UVD_BASE__INST6_SEG5
 
- UVD_BASE__INST7_SEG0
 
- UVD_BASE__INST7_SEG1
 
- UVD_BASE__INST7_SEG2
 
- UVD_BASE__INST7_SEG3
 
- UVD_BASE__INST7_SEG4
 
- UVD_BASE__INST7_SEG5
 
- UVD_BUSY
 
- UVD_CBUF_ID__CBUF_ID_MASK
 
- UVD_CBUF_ID__CBUF_ID__SHIFT
 
- UVD_CGC_CTRL
 
- UVD_CGC_CTRL2
 
- UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK
 
- UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT
 
- UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK
 
- UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT
 
- UVD_CGC_CTRL2__GATER_DIV_ID_MASK
 
- UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT
 
- UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK
 
- UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT
 
- UVD_CGC_CTRL__CLK_OFF_DELAY_MASK
 
- UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT
 
- UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK
 
- UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT
 
- UVD_CGC_CTRL__IDCT_MODE_MASK
 
- UVD_CGC_CTRL__IDCT_MODE__SHIFT
 
- UVD_CGC_CTRL__JPEG2_MODE_MASK
 
- UVD_CGC_CTRL__JPEG2_MODE__SHIFT
 
- UVD_CGC_CTRL__JPEG_MODE_MASK
 
- UVD_CGC_CTRL__JPEG_MODE__SHIFT
 
- UVD_CGC_CTRL__LBSI_MODE_MASK
 
- UVD_CGC_CTRL__LBSI_MODE__SHIFT
 
- UVD_CGC_CTRL__LMI_MC_MODE_MASK
 
- UVD_CGC_CTRL__LMI_MC_MODE__SHIFT
 
- UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 
- UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT
 
- UVD_CGC_CTRL__LRBBM_MODE_MASK
 
- UVD_CGC_CTRL__LRBBM_MODE__SHIFT
 
- UVD_CGC_CTRL__MMSCH_MODE_MASK
 
- UVD_CGC_CTRL__MMSCH_MODE__SHIFT
 
- UVD_CGC_CTRL__MPC_MODE_MASK
 
- UVD_CGC_CTRL__MPC_MODE__SHIFT
 
- UVD_CGC_CTRL__MPEG2_MODE_MASK
 
- UVD_CGC_CTRL__MPEG2_MODE__SHIFT
 
- UVD_CGC_CTRL__MPRD_MODE_MASK
 
- UVD_CGC_CTRL__MPRD_MODE__SHIFT
 
- UVD_CGC_CTRL__RBC_MODE_MASK
 
- UVD_CGC_CTRL__RBC_MODE__SHIFT
 
- UVD_CGC_CTRL__REGS_MODE_MASK
 
- UVD_CGC_CTRL__REGS_MODE__SHIFT
 
- UVD_CGC_CTRL__SCPU_MODE_MASK
 
- UVD_CGC_CTRL__SCPU_MODE__SHIFT
 
- UVD_CGC_CTRL__SYS_MODE_MASK
 
- UVD_CGC_CTRL__SYS_MODE__SHIFT
 
- UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 
- UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT
 
- UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 
- UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT
 
- UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 
- UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT
 
- UVD_CGC_CTRL__UDEC_MODE_MASK
 
- UVD_CGC_CTRL__UDEC_MODE__SHIFT
 
- UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 
- UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT
 
- UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 
- UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT
 
- UVD_CGC_CTRL__VCPU_MODE_MASK
 
- UVD_CGC_CTRL__VCPU_MODE__SHIFT
 
- UVD_CGC_CTRL__WCB_MODE_MASK
 
- UVD_CGC_CTRL__WCB_MODE__SHIFT
 
- UVD_CGC_GATE
 
- UVD_CGC_GATE__IDCT_MASK
 
- UVD_CGC_GATE__IDCT__SHIFT
 
- UVD_CGC_GATE__JPEG2_MASK
 
- UVD_CGC_GATE__JPEG2__SHIFT
 
- UVD_CGC_GATE__JPEG_MASK
 
- UVD_CGC_GATE__JPEG__SHIFT
 
- UVD_CGC_GATE__LBSI_MASK
 
- UVD_CGC_GATE__LBSI__SHIFT
 
- UVD_CGC_GATE__LMI_MC_MASK
 
- UVD_CGC_GATE__LMI_MC__SHIFT
 
- UVD_CGC_GATE__LMI_UMC_MASK
 
- UVD_CGC_GATE__LMI_UMC__SHIFT
 
- UVD_CGC_GATE__LRBBM_MASK
 
- UVD_CGC_GATE__LRBBM__SHIFT
 
- UVD_CGC_GATE__MMSCH_MASK
 
- UVD_CGC_GATE__MMSCH__SHIFT
 
- UVD_CGC_GATE__MPC_MASK
 
- UVD_CGC_GATE__MPC__SHIFT
 
- UVD_CGC_GATE__MPEG2_MASK
 
- UVD_CGC_GATE__MPEG2__SHIFT
 
- UVD_CGC_GATE__MPRD_MASK
 
- UVD_CGC_GATE__MPRD__SHIFT
 
- UVD_CGC_GATE__RBC_MASK
 
- UVD_CGC_GATE__RBC__SHIFT
 
- UVD_CGC_GATE__REGS_MASK
 
- UVD_CGC_GATE__REGS__SHIFT
 
- UVD_CGC_GATE__SCPU_MASK
 
- UVD_CGC_GATE__SCPU__SHIFT
 
- UVD_CGC_GATE__SYS_MASK
 
- UVD_CGC_GATE__SYS__SHIFT
 
- UVD_CGC_GATE__UDEC_CM_MASK
 
- UVD_CGC_GATE__UDEC_CM__SHIFT
 
- UVD_CGC_GATE__UDEC_DB_MASK
 
- UVD_CGC_GATE__UDEC_DB__SHIFT
 
- UVD_CGC_GATE__UDEC_IT_MASK
 
- UVD_CGC_GATE__UDEC_IT__SHIFT
 
- UVD_CGC_GATE__UDEC_MASK
 
- UVD_CGC_GATE__UDEC_MP_MASK
 
- UVD_CGC_GATE__UDEC_MP__SHIFT
 
- UVD_CGC_GATE__UDEC_RE_MASK
 
- UVD_CGC_GATE__UDEC_RE__SHIFT
 
- UVD_CGC_GATE__UDEC__SHIFT
 
- UVD_CGC_GATE__VCPU_MASK
 
- UVD_CGC_GATE__VCPU__SHIFT
 
- UVD_CGC_GATE__WCB_MASK
 
- UVD_CGC_GATE__WCB__SHIFT
 
- UVD_CGC_MEM_CTRL
 
- UVD_CGC_MEM_CTRL__JPEG2_LS_EN_MASK
 
- UVD_CGC_MEM_CTRL__JPEG2_LS_EN__SHIFT
 
- UVD_CGC_MEM_CTRL__JPEG_LS_EN_MASK
 
- UVD_CGC_MEM_CTRL__JPEG_LS_EN__SHIFT
 
- UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK
 
- UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT
 
- UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK
 
- UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT
 
- UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK
 
- UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT
 
- UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK
 
- UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT
 
- UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK
 
- UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT
 
- UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK
 
- UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT
 
- UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK
 
- UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT
 
- UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK
 
- UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT
 
- UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK
 
- UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT
 
- UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK
 
- UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT
 
- UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK
 
- UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT
 
- UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK
 
- UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT
 
- UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK
 
- UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT
 
- UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK
 
- UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT
 
- UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK
 
- UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT
 
- UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK
 
- UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT
 
- UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK
 
- UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT
 
- UVD_CGC_STATUS__ALL_ENC_ACTIVE_MASK
 
- UVD_CGC_STATUS__ALL_ENC_ACTIVE__SHIFT
 
- UVD_CGC_STATUS__IDCT_SCLK_MASK
 
- UVD_CGC_STATUS__IDCT_SCLK__SHIFT
 
- UVD_CGC_STATUS__IDCT_VCLK_MASK
 
- UVD_CGC_STATUS__IDCT_VCLK__SHIFT
 
- UVD_CGC_STATUS__JPEG_ACTIVE_MASK
 
- UVD_CGC_STATUS__JPEG_ACTIVE__SHIFT
 
- UVD_CGC_STATUS__LBSI_SCLK_MASK
 
- UVD_CGC_STATUS__LBSI_SCLK__SHIFT
 
- UVD_CGC_STATUS__LBSI_VCLK_MASK
 
- UVD_CGC_STATUS__LBSI_VCLK__SHIFT
 
- UVD_CGC_STATUS__LMI_MC_SCLK_MASK
 
- UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT
 
- UVD_CGC_STATUS__LMI_UMC_SCLK_MASK
 
- UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT
 
- UVD_CGC_STATUS__LRBBM_SCLK_MASK
 
- UVD_CGC_STATUS__LRBBM_SCLK__SHIFT
 
- UVD_CGC_STATUS__MMSCH_SCLK_MASK
 
- UVD_CGC_STATUS__MMSCH_SCLK__SHIFT
 
- UVD_CGC_STATUS__MMSCH_VCLK_MASK
 
- UVD_CGC_STATUS__MMSCH_VCLK__SHIFT
 
- UVD_CGC_STATUS__MPC_DCLK_MASK
 
- UVD_CGC_STATUS__MPC_DCLK__SHIFT
 
- UVD_CGC_STATUS__MPC_SCLK_MASK
 
- UVD_CGC_STATUS__MPC_SCLK__SHIFT
 
- UVD_CGC_STATUS__MPEG2_DCLK_MASK
 
- UVD_CGC_STATUS__MPEG2_DCLK__SHIFT
 
- UVD_CGC_STATUS__MPEG2_SCLK_MASK
 
- UVD_CGC_STATUS__MPEG2_SCLK__SHIFT
 
- UVD_CGC_STATUS__MPEG2_VCLK_MASK
 
- UVD_CGC_STATUS__MPEG2_VCLK__SHIFT
 
- UVD_CGC_STATUS__MPRD_DCLK_MASK
 
- UVD_CGC_STATUS__MPRD_DCLK__SHIFT
 
- UVD_CGC_STATUS__MPRD_SCLK_MASK
 
- UVD_CGC_STATUS__MPRD_SCLK__SHIFT
 
- UVD_CGC_STATUS__MPRD_VCLK_MASK
 
- UVD_CGC_STATUS__MPRD_VCLK__SHIFT
 
- UVD_CGC_STATUS__RBC_SCLK_MASK
 
- UVD_CGC_STATUS__RBC_SCLK__SHIFT
 
- UVD_CGC_STATUS__REGS_SCLK_MASK
 
- UVD_CGC_STATUS__REGS_SCLK__SHIFT
 
- UVD_CGC_STATUS__REGS_VCLK_MASK
 
- UVD_CGC_STATUS__REGS_VCLK__SHIFT
 
- UVD_CGC_STATUS__SCPU_SCLK_MASK
 
- UVD_CGC_STATUS__SCPU_SCLK__SHIFT
 
- UVD_CGC_STATUS__SCPU_VCLK_MASK
 
- UVD_CGC_STATUS__SCPU_VCLK__SHIFT
 
- UVD_CGC_STATUS__SYS_DCLK_MASK
 
- UVD_CGC_STATUS__SYS_DCLK__SHIFT
 
- UVD_CGC_STATUS__SYS_SCLK_MASK
 
- UVD_CGC_STATUS__SYS_SCLK__SHIFT
 
- UVD_CGC_STATUS__SYS_VCLK_MASK
 
- UVD_CGC_STATUS__SYS_VCLK__SHIFT
 
- UVD_CGC_STATUS__UDEC_DCLK_MASK
 
- UVD_CGC_STATUS__UDEC_DCLK__SHIFT
 
- UVD_CGC_STATUS__UDEC_SCLK_MASK
 
- UVD_CGC_STATUS__UDEC_SCLK__SHIFT
 
- UVD_CGC_STATUS__UDEC_VCLK_MASK
 
- UVD_CGC_STATUS__UDEC_VCLK__SHIFT
 
- UVD_CGC_STATUS__VCPU_SCLK_MASK
 
- UVD_CGC_STATUS__VCPU_SCLK__SHIFT
 
- UVD_CGC_STATUS__VCPU_VCLK_MASK
 
- UVD_CGC_STATUS__VCPU_VCLK__SHIFT
 
- UVD_CGC_STATUS__WCB_SCLK_MASK
 
- UVD_CGC_STATUS__WCB_SCLK__SHIFT
 
- UVD_CGC_UDEC_STATUS__CM_DCLK_MASK
 
- UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT
 
- UVD_CGC_UDEC_STATUS__CM_SCLK_MASK
 
- UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT
 
- UVD_CGC_UDEC_STATUS__CM_VCLK_MASK
 
- UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT
 
- UVD_CGC_UDEC_STATUS__DB_DCLK_MASK
 
- UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT
 
- UVD_CGC_UDEC_STATUS__DB_SCLK_MASK
 
- UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT
 
- UVD_CGC_UDEC_STATUS__DB_VCLK_MASK
 
- UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT
 
- UVD_CGC_UDEC_STATUS__IT_DCLK_MASK
 
- UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT
 
- UVD_CGC_UDEC_STATUS__IT_SCLK_MASK
 
- UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT
 
- UVD_CGC_UDEC_STATUS__IT_VCLK_MASK
 
- UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT
 
- UVD_CGC_UDEC_STATUS__JPEG2_SCLK_MASK
 
- UVD_CGC_UDEC_STATUS__JPEG2_SCLK__SHIFT
 
- UVD_CGC_UDEC_STATUS__JPEG2_VCLK_MASK
 
- UVD_CGC_UDEC_STATUS__JPEG2_VCLK__SHIFT
 
- UVD_CGC_UDEC_STATUS__JPEG_SCLK_MASK
 
- UVD_CGC_UDEC_STATUS__JPEG_SCLK__SHIFT
 
- UVD_CGC_UDEC_STATUS__JPEG_VCLK_MASK
 
- UVD_CGC_UDEC_STATUS__JPEG_VCLK__SHIFT
 
- UVD_CGC_UDEC_STATUS__MP_DCLK_MASK
 
- UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT
 
- UVD_CGC_UDEC_STATUS__MP_SCLK_MASK
 
- UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT
 
- UVD_CGC_UDEC_STATUS__MP_VCLK_MASK
 
- UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT
 
- UVD_CGC_UDEC_STATUS__RE_DCLK_MASK
 
- UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT
 
- UVD_CGC_UDEC_STATUS__RE_SCLK_MASK
 
- UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT
 
- UVD_CGC_UDEC_STATUS__RE_VCLK_MASK
 
- UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT
 
- UVD_CONFIG__UVD_RDREQ_URG_MASK
 
- UVD_CONFIG__UVD_RDREQ_URG__SHIFT
 
- UVD_CONFIG__UVD_REQ_TRAN_MASK
 
- UVD_CONFIG__UVD_REQ_TRAN__SHIFT
 
- UVD_CONTEXT_ID
 
- UVD_CONTEXT_ID2__CONTEXT_ID2_MASK
 
- UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT
 
- UVD_CONTEXT_ID__CONTEXT_ID_MASK
 
- UVD_CONTEXT_ID__CONTEXT_ID__SHIFT
 
- UVD_CTX_DATA__DATA_MASK
 
- UVD_CTX_DATA__DATA__SHIFT
 
- UVD_CTX_INDEX__INDEX_MASK
 
- UVD_CTX_INDEX__INDEX__SHIFT
 
- UVD_CXW_BLOCK_STATUS__LBSI_IDLE_MASK
 
- UVD_CXW_BLOCK_STATUS__LBSI_IDLE__SHIFT
 
- UVD_CXW_BLOCK_STATUS__LMI_IDLE_MASK
 
- UVD_CXW_BLOCK_STATUS__LMI_IDLE__SHIFT
 
- UVD_CXW_BLOCK_STATUS__VCPU_IDLE_MASK
 
- UVD_CXW_BLOCK_STATUS__VCPU_IDLE__SHIFT
 
- UVD_CXW_CNTL__EXTERNAL_CXW_EN_MASK
 
- UVD_CXW_CNTL__EXTERNAL_CXW_EN__SHIFT
 
- UVD_CXW_CNTL__EXTERNAL_CXW_INT_EN_MASK
 
- UVD_CXW_CNTL__EXTERNAL_CXW_INT_EN__SHIFT
 
- UVD_CXW_CNTL__HOST_CXW_EN_MASK
 
- UVD_CXW_CNTL__HOST_CXW_EN__SHIFT
 
- UVD_CXW_CNTL__HOST_CXW_INT_EN_MASK
 
- UVD_CXW_CNTL__HOST_CXW_INT_EN__SHIFT
 
- UVD_CXW_CNTL__SEMAPHORE_TIMEOUT_CXW_EN_MASK
 
- UVD_CXW_CNTL__SEMAPHORE_TIMEOUT_CXW_EN__SHIFT
 
- UVD_CXW_CNTL__SEMAPHORE_TIMEOUT_CXW_INT_EN_MASK
 
- UVD_CXW_CNTL__SEMAPHORE_TIMEOUT_CXW_INT_EN__SHIFT
 
- UVD_CXW_EN__CXW_ENABLE_MASK
 
- UVD_CXW_EN__CXW_ENABLE__SHIFT
 
- UVD_CXW_EVENT__EXTERNAL_CXW_EVENT_OCCURRED_MASK
 
- UVD_CXW_EVENT__EXTERNAL_CXW_EVENT_OCCURRED__SHIFT
 
- UVD_CXW_EVENT__HOST_CXW_EVENT_OCCURRED_MASK
 
- UVD_CXW_EVENT__HOST_CXW_EVENT_OCCURRED__SHIFT
 
- UVD_CXW_EVENT__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_EVENT_OCCURRED_MASK
 
- UVD_CXW_EVENT__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_EVENT_OCCURRED__SHIFT
 
- UVD_CXW_EVENT__SEMAPHORE_WAIT_FAULT_TIMEOUT_EVENT_OCCURRED_MASK
 
- UVD_CXW_EVENT__SEMAPHORE_WAIT_FAULT_TIMEOUT_EVENT_OCCURRED__SHIFT
 
- UVD_CXW_EVENT__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_EVENT_OCCURRED_MASK
 
- UVD_CXW_EVENT__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_EVENT_OCCURRED__SHIFT
 
- UVD_CXW_FINISHED__CXW_FINISHED_MASK
 
- UVD_CXW_FINISHED__CXW_FINISHED__SHIFT
 
- UVD_CXW_INT_ID__ID_MASK
 
- UVD_CXW_INT_ID__ID__SHIFT
 
- UVD_CXW_SAVE_AREA_ADDR__CXW_SAVE_AREA_ADDR_MASK
 
- UVD_CXW_SAVE_AREA_ADDR__CXW_SAVE_AREA_ADDR__SHIFT
 
- UVD_CXW_SAVE_AREA_SIZE__CXW_SAVE_AREA_SIZE_MASK
 
- UVD_CXW_SAVE_AREA_SIZE__CXW_SAVE_AREA_SIZE__SHIFT
 
- UVD_CXW_SCAN_AREA_OFFSET__CXW_CONTEXT_RESTORE_MASK
 
- UVD_CXW_SCAN_AREA_OFFSET__CXW_CONTEXT_RESTORE__SHIFT
 
- UVD_CXW_SCAN_AREA_OFFSET__CXW_CONTEXT_SAVE_MASK
 
- UVD_CXW_SCAN_AREA_OFFSET__CXW_CONTEXT_SAVE__SHIFT
 
- UVD_CXW_SCAN_AREA_OFFSET__CXW_SCAN_AREA_OFFSET_MASK
 
- UVD_CXW_SCAN_AREA_OFFSET__CXW_SCAN_AREA_OFFSET__SHIFT
 
- UVD_CXW_SE__CXW_SCAN_ENABLE_MASK
 
- UVD_CXW_SE__CXW_SCAN_ENABLE__SHIFT
 
- UVD_CXW_SHIFT_CNTL__SHIFT_CNTL_MASK
 
- UVD_CXW_SHIFT_CNTL__SHIFT_CNTL__SHIFT
 
- UVD_CXW_SHIFT_CNTL__SHIFT_COUNT_MASK
 
- UVD_CXW_SHIFT_CNTL__SHIFT_COUNT__SHIFT
 
- UVD_CXW_SHIFT_FINISHED__SHIFT_FINISHED_MASK
 
- UVD_CXW_SHIFT_FINISHED__SHIFT_FINISHED__SHIFT
 
- UVD_CXW_START__START_CXW_MASK
 
- UVD_CXW_START__START_CXW__SHIFT
 
- UVD_CXW_WR_INT_CTX_ID__ID_MASK
 
- UVD_CXW_WR_INT_CTX_ID__ID__SHIFT
 
- UVD_CXW_WR_INT_ID__ID_MASK
 
- UVD_CXW_WR_INT_ID__ID__SHIFT
 
- UVD_CXW_WR__DAT_MASK
 
- UVD_CXW_WR__DAT__SHIFT
 
- UVD_CXW_WR__STAT_MASK
 
- UVD_CXW_WR__STAT__SHIFT
 
- UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN_MASK
 
- UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN__SHIFT
 
- UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT_MASK
 
- UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT__SHIFT
 
- UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK
 
- UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT
 
- UVD_DPG_LMA_CTL__MASK_EN_MASK
 
- UVD_DPG_LMA_CTL__MASK_EN__SHIFT
 
- UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK
 
- UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT
 
- UVD_DPG_LMA_CTL__READ_WRITE_MASK
 
- UVD_DPG_LMA_CTL__READ_WRITE__SHIFT
 
- UVD_DPG_LMA_CTL__SRAM_SEL_MASK
 
- UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT
 
- UVD_DPG_LMA_DATA__LMA_DATA_MASK
 
- UVD_DPG_LMA_DATA__LMA_DATA__SHIFT
 
- UVD_DPG_LMA_MASK__LMA_MASK_MASK
 
- UVD_DPG_LMA_MASK__LMA_MASK__SHIFT
 
- UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK
 
- UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT
 
- UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK
 
- UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT
 
- UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK
 
- UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT
 
- UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK
 
- UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT
 
- UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK
 
- UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT
 
- UVD_DPG_RBC_RB_BASE_HIGH__RB_BASE_HIGH_MASK
 
- UVD_DPG_RBC_RB_BASE_HIGH__RB_BASE_HIGH__SHIFT
 
- UVD_DPG_RBC_RB_BASE_LOW__RB_BASE_LOW_MASK
 
- UVD_DPG_RBC_RB_BASE_LOW__RB_BASE_LOW__SHIFT
 
- UVD_DPG_RBC_RB_CNTL__RB_BLKSZ_MASK
 
- UVD_DPG_RBC_RB_CNTL__RB_BLKSZ__SHIFT
 
- UVD_DPG_RBC_RB_CNTL__RB_BUFSZ_MASK
 
- UVD_DPG_RBC_RB_CNTL__RB_BUFSZ__SHIFT
 
- UVD_DPG_RBC_RB_CNTL__RB_NO_FETCH_MASK
 
- UVD_DPG_RBC_RB_CNTL__RB_NO_FETCH__SHIFT
 
- UVD_DPG_RBC_RB_CNTL__RB_NO_UPDATE_MASK
 
- UVD_DPG_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT
 
- UVD_DPG_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK
 
- UVD_DPG_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT
 
- UVD_DPG_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK
 
- UVD_DPG_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT
 
- UVD_DPG_RBC_RB_RPTR__RB_RPTR_MASK
 
- UVD_DPG_RBC_RB_RPTR__RB_RPTR__SHIFT
 
- UVD_DPG_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK
 
- UVD_DPG_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT
 
- UVD_DPG_RBC_RB_WPTR__RB_WPTR_MASK
 
- UVD_DPG_RBC_RB_WPTR__RB_WPTR__SHIFT
 
- UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK
 
- UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT
 
- UVD_DPM_MASK
 
- UVD_ENC_PIPE_BUSY__ENT_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__ENT_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__IME_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__IME_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__LCM_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__LCM_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__SDB_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__SDB_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__SIT_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__SIT_BUSY__SHIFT
 
- UVD_ENC_PIPE_BUSY__SMP_BUSY_MASK
 
- UVD_ENC_PIPE_BUSY__SMP_BUSY__SHIFT
 
- UVD_ENC_REG_DATA__DATA_MASK
 
- UVD_ENC_REG_DATA__DATA__SHIFT
 
- UVD_ENC_REG_INDEX__INDEX_MASK
 
- UVD_ENC_REG_INDEX__INDEX__SHIFT
 
- UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK_MASK
 
- UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK__SHIFT
 
- UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK_MASK
 
- UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK__SHIFT
 
- UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK_MASK
 
- UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK__SHIFT
 
- UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN_MASK
 
- UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN__SHIFT
 
- UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN_MASK
 
- UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN__SHIFT
 
- UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN_MASK
 
- UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN__SHIFT
 
- UVD_ENGINE_CNTL
 
- UVD_ENGINE_CNTL__ENGINE_START_MASK
 
- UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK
 
- UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT
 
- UVD_ENGINE_CNTL__ENGINE_START__SHIFT
 
- UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE_MASK
 
- UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE__SHIFT
 
- UVD_FREE_COUNTER_REG__FREE_COUNTER_MASK
 
- UVD_FREE_COUNTER_REG__FREE_COUNTER__SHIFT
 
- UVD_FW_START
 
- UVD_GFX10_ADDR_CONFIG__NUM_BANKS_MASK
 
- UVD_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT
 
- UVD_GFX10_ADDR_CONFIG__NUM_PIPES_MASK
 
- UVD_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT
 
- UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK
 
- UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT
 
- UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK
 
- UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT
 
- UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK
 
- UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT
 
- UVD_GPCNT2_CNTL__CLR_MASK
 
- UVD_GPCNT2_CNTL__CLR__SHIFT
 
- UVD_GPCNT2_CNTL__COUNTUP_MASK
 
- UVD_GPCNT2_CNTL__COUNTUP__SHIFT
 
- UVD_GPCNT2_CNTL__START_MASK
 
- UVD_GPCNT2_CNTL__START__SHIFT
 
- UVD_GPCNT2_STATUS_LOWER__COUNT_MASK
 
- UVD_GPCNT2_STATUS_LOWER__COUNT__SHIFT
 
- UVD_GPCNT2_STATUS_UPPER__COUNT_MASK
 
- UVD_GPCNT2_STATUS_UPPER__COUNT__SHIFT
 
- UVD_GPCNT2_TARGET_LOWER__TARGET_MASK
 
- UVD_GPCNT2_TARGET_LOWER__TARGET__SHIFT
 
- UVD_GPCNT2_TARGET_UPPER__TARGET_MASK
 
- UVD_GPCNT2_TARGET_UPPER__TARGET__SHIFT
 
- UVD_GPCNT3_CNTL__CLR_MASK
 
- UVD_GPCNT3_CNTL__CLR__SHIFT
 
- UVD_GPCNT3_CNTL__COUNTUP_MASK
 
- UVD_GPCNT3_CNTL__COUNTUP__SHIFT
 
- UVD_GPCNT3_CNTL__DIV_MASK
 
- UVD_GPCNT3_CNTL__DIV__SHIFT
 
- UVD_GPCNT3_CNTL__FREQ_MASK
 
- UVD_GPCNT3_CNTL__FREQ__SHIFT
 
- UVD_GPCNT3_CNTL__START_MASK
 
- UVD_GPCNT3_CNTL__START__SHIFT
 
- UVD_GPCNT3_STATUS_LOWER__COUNT_MASK
 
- UVD_GPCNT3_STATUS_LOWER__COUNT__SHIFT
 
- UVD_GPCNT3_STATUS_UPPER__COUNT_MASK
 
- UVD_GPCNT3_STATUS_UPPER__COUNT__SHIFT
 
- UVD_GPCNT3_TARGET_LOWER__TARGET_MASK
 
- UVD_GPCNT3_TARGET_LOWER__TARGET__SHIFT
 
- UVD_GPCNT3_TARGET_UPPER__TARGET_MASK
 
- UVD_GPCNT3_TARGET_UPPER__TARGET__SHIFT
 
- UVD_GPCOM_SYS_CMD__CMD_MASK
 
- UVD_GPCOM_SYS_CMD__CMD_SEND_MASK
 
- UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT
 
- UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK
 
- UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT
 
- UVD_GPCOM_SYS_CMD__CMD__SHIFT
 
- UVD_GPCOM_SYS_DATA0__DATA0_MASK
 
- UVD_GPCOM_SYS_DATA0__DATA0__SHIFT
 
- UVD_GPCOM_SYS_DATA1__DATA1_MASK
 
- UVD_GPCOM_SYS_DATA1__DATA1__SHIFT
 
- UVD_GPCOM_VCPU_CMD
 
- UVD_GPCOM_VCPU_CMD__CMD_MASK
 
- UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK
 
- UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT
 
- UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK
 
- UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT
 
- UVD_GPCOM_VCPU_CMD__CMD__SHIFT
 
- UVD_GPCOM_VCPU_DATA0
 
- UVD_GPCOM_VCPU_DATA0__DATA0_MASK
 
- UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT
 
- UVD_GPCOM_VCPU_DATA1
 
- UVD_GPCOM_VCPU_DATA1__DATA1_MASK
 
- UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT
 
- UVD_GP_SCRATCH0__DATA_MASK
 
- UVD_GP_SCRATCH0__DATA__SHIFT
 
- UVD_GP_SCRATCH10__DATA_MASK
 
- UVD_GP_SCRATCH10__DATA__SHIFT
 
- UVD_GP_SCRATCH11__DATA_MASK
 
- UVD_GP_SCRATCH11__DATA__SHIFT
 
- UVD_GP_SCRATCH12__DATA_MASK
 
- UVD_GP_SCRATCH12__DATA__SHIFT
 
- UVD_GP_SCRATCH13__DATA_MASK
 
- UVD_GP_SCRATCH13__DATA__SHIFT
 
- UVD_GP_SCRATCH14__DATA_MASK
 
- UVD_GP_SCRATCH14__DATA__SHIFT
 
- UVD_GP_SCRATCH15__DATA_MASK
 
- UVD_GP_SCRATCH15__DATA__SHIFT
 
- UVD_GP_SCRATCH16__DATA_MASK
 
- UVD_GP_SCRATCH16__DATA__SHIFT
 
- UVD_GP_SCRATCH17__DATA_MASK
 
- UVD_GP_SCRATCH17__DATA__SHIFT
 
- UVD_GP_SCRATCH18__DATA_MASK
 
- UVD_GP_SCRATCH18__DATA__SHIFT
 
- UVD_GP_SCRATCH19__DATA_MASK
 
- UVD_GP_SCRATCH19__DATA__SHIFT
 
- UVD_GP_SCRATCH1__DATA_MASK
 
- UVD_GP_SCRATCH1__DATA__SHIFT
 
- UVD_GP_SCRATCH20__DATA_MASK
 
- UVD_GP_SCRATCH20__DATA__SHIFT
 
- UVD_GP_SCRATCH21__DATA_MASK
 
- UVD_GP_SCRATCH21__DATA__SHIFT
 
- UVD_GP_SCRATCH22__DATA_MASK
 
- UVD_GP_SCRATCH22__DATA__SHIFT
 
- UVD_GP_SCRATCH23__DATA_MASK
 
- UVD_GP_SCRATCH23__DATA__SHIFT
 
- UVD_GP_SCRATCH2__DATA_MASK
 
- UVD_GP_SCRATCH2__DATA__SHIFT
 
- UVD_GP_SCRATCH3__DATA_MASK
 
- UVD_GP_SCRATCH3__DATA__SHIFT
 
- UVD_GP_SCRATCH4
 
- UVD_GP_SCRATCH4__DATA_MASK
 
- UVD_GP_SCRATCH4__DATA__SHIFT
 
- UVD_GP_SCRATCH5__DATA_MASK
 
- UVD_GP_SCRATCH5__DATA__SHIFT
 
- UVD_GP_SCRATCH6__DATA_MASK
 
- UVD_GP_SCRATCH6__DATA__SHIFT
 
- UVD_GP_SCRATCH7__DATA_MASK
 
- UVD_GP_SCRATCH7__DATA__SHIFT
 
- UVD_GP_SCRATCH8__DATA_MASK
 
- UVD_GP_SCRATCH8__DATA__SHIFT
 
- UVD_GP_SCRATCH9__DATA_MASK
 
- UVD_GP_SCRATCH9__DATA__SHIFT
 
- UVD_HEIGHT__DUM_MASK
 
- UVD_HEIGHT__DUM__SHIFT
 
- UVD_HWID
 
- UVD_HWIP
 
- UVD_IDLE_TIMEOUT
 
- UVD_IDLE_TIMEOUT_MS
 
- UVD_IH_SRC_ID_END
 
- UVD_IH_SRC_ID_START
 
- UVD_JMI_CNTL__MC_RD_REQ_RET_MAX_MASK
 
- UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT
 
- UVD_JMI_CNTL__SOFT_RESET_MASK
 
- UVD_JMI_CNTL__SOFT_RESET__SHIFT
 
- UVD_JMI_CTRL__ASSERT_MC_URGENT_MASK
 
- UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT
 
- UVD_JMI_CTRL__CRC_RESET_MASK
 
- UVD_JMI_CTRL__CRC_RESET__SHIFT
 
- UVD_JMI_CTRL__CRC_SEL_MASK
 
- UVD_JMI_CTRL__CRC_SEL__SHIFT
 
- UVD_JMI_CTRL__MASK_MC_URGENT_MASK
 
- UVD_JMI_CTRL__MASK_MC_URGENT__SHIFT
 
- UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER_MASK
 
- UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER__SHIFT
 
- UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER_MASK
 
- UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER__SHIFT
 
- UVD_JMI_CTRL__STALL_MC_ARB_MASK
 
- UVD_JMI_CTRL__STALL_MC_ARB__SHIFT
 
- UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP_MASK
 
- UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP__SHIFT
 
- UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP_MASK
 
- UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP__SHIFT
 
- UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK
 
- UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT
 
- UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK
 
- UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT
 
- UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK
 
- UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT
 
- UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK
 
- UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT
 
- UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK
 
- UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT
 
- UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK
 
- UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT
 
- UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK
 
- UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT
 
- UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK
 
- UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT
 
- UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK
 
- UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT
 
- UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN_MASK
 
- UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN__SHIFT
 
- UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN_MASK
 
- UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN__SHIFT
 
- UVD_JMI_EJRBC_CTRL__RD_MAX_BURST_MASK
 
- UVD_JMI_EJRBC_CTRL__RD_MAX_BURST__SHIFT
 
- UVD_JMI_EJRBC_CTRL__RD_SWAP_MASK
 
- UVD_JMI_EJRBC_CTRL__RD_SWAP__SHIFT
 
- UVD_JMI_EJRBC_CTRL__WR_MAX_BURST_MASK
 
- UVD_JMI_EJRBC_CTRL__WR_MAX_BURST__SHIFT
 
- UVD_JMI_EJRBC_CTRL__WR_SWAP_MASK
 
- UVD_JMI_EJRBC_CTRL__WR_SWAP__SHIFT
 
- UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID_MASK
 
- UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID__SHIFT
 
- UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID_MASK
 
- UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID__SHIFT
 
- UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID_MASK
 
- UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID__SHIFT
 
- UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID_MASK
 
- UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID__SHIFT
 
- UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID_MASK
 
- UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID__SHIFT
 
- UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID_MASK
 
- UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID__SHIFT
 
- UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID_MASK
 
- UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID__SHIFT
 
- UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID_MASK
 
- UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID__SHIFT
 
- UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID_MASK
 
- UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID__SHIFT
 
- UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID_MASK
 
- UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID__SHIFT
 
- UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID_MASK
 
- UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID__SHIFT
 
- UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID_MASK
 
- UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID__SHIFT
 
- UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP_MASK
 
- UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP__SHIFT
 
- UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP_MASK
 
- UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP__SHIFT
 
- UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP_MASK
 
- UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP__SHIFT
 
- UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK
 
- UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT
 
- UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK
 
- UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT
 
- UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP_MASK
 
- UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP__SHIFT
 
- UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK
 
- UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT
 
- UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP_MASK
 
- UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP__SHIFT
 
- UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK
 
- UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT
 
- UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK
 
- UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT
 
- UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP_MASK
 
- UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP__SHIFT
 
- UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP_MASK
 
- UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP__SHIFT
 
- UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK
 
- UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT
 
- UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK
 
- UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT
 
- UVD_JMI_PERFMON_CTRL__PERFMON_SEL_MASK
 
- UVD_JMI_PERFMON_CTRL__PERFMON_SEL__SHIFT
 
- UVD_JMI_PERFMON_CTRL__PERFMON_STATE_MASK
 
- UVD_JMI_PERFMON_CTRL__PERFMON_STATE__SHIFT
 
- UVD_JOB_DONE__JOB_DONE_MASK
 
- UVD_JOB_DONE__JOB_DONE__SHIFT
 
- UVD_JOB_START__JOB_START_MASK
 
- UVD_JOB_START__JOB_START__SHIFT
 
- UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK
 
- UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT
 
- UVD_JPEG_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK
 
- UVD_JPEG_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT
 
- UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK
 
- UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT
 
- UVD_JPEG_ADDR_CONFIG__NUM_BANKS_MASK
 
- UVD_JPEG_ADDR_CONFIG__NUM_BANKS__SHIFT
 
- UVD_JPEG_ADDR_CONFIG__NUM_GPUS_MASK
 
- UVD_JPEG_ADDR_CONFIG__NUM_GPUS__SHIFT
 
- UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES_MASK
 
- UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT
 
- UVD_JPEG_ADDR_CONFIG__NUM_PIPES_MASK
 
- UVD_JPEG_ADDR_CONFIG__NUM_PIPES__SHIFT
 
- UVD_JPEG_ADDR_CONFIG__NUM_RB_PER_SE_MASK
 
- UVD_JPEG_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT
 
- UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK
 
- UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT
 
- UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK
 
- UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT
 
- UVD_JPEG_ADDR_CONFIG__ROW_SIZE_MASK
 
- UVD_JPEG_ADDR_CONFIG__ROW_SIZE__SHIFT
 
- UVD_JPEG_ADDR_CONFIG__SE_ENABLE_MASK
 
- UVD_JPEG_ADDR_CONFIG__SE_ENABLE__SHIFT
 
- UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK
 
- UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT
 
- UVD_JPEG_CNTL__DBG_MUX_SEL_MASK
 
- UVD_JPEG_CNTL__DBG_MUX_SEL__SHIFT
 
- UVD_JPEG_CNTL__ERR_RST_EN_MASK
 
- UVD_JPEG_CNTL__ERR_RST_EN__SHIFT
 
- UVD_JPEG_CNTL__HUFF_SPEED_EN_MASK
 
- UVD_JPEG_CNTL__HUFF_SPEED_EN__SHIFT
 
- UVD_JPEG_CNTL__HUFF_SPEED_STATUS_MASK
 
- UVD_JPEG_CNTL__HUFF_SPEED_STATUS__SHIFT
 
- UVD_JPEG_CNTL__REQUEST_EN_MASK
 
- UVD_JPEG_CNTL__REQUEST_EN__SHIFT
 
- UVD_JPEG_CNTL__SOFT_RESET_MASK
 
- UVD_JPEG_CNTL__SOFT_RESET__SHIFT
 
- UVD_JPEG_DEC_SCRATCH0__SCRATCH0_MASK
 
- UVD_JPEG_DEC_SCRATCH0__SCRATCH0__SHIFT
 
- UVD_JPEG_DEC_SOFT_RST__RESET_STATUS_MASK
 
- UVD_JPEG_DEC_SOFT_RST__RESET_STATUS__SHIFT
 
- UVD_JPEG_DEC_SOFT_RST__SOFT_RESET_MASK
 
- UVD_JPEG_DEC_SOFT_RST__SOFT_RESET__SHIFT
 
- UVD_JPEG_ENC_CGC_CNTL__CGC_EN_MASK
 
- UVD_JPEG_ENC_CGC_CNTL__CGC_EN__SHIFT
 
- UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE_MASK
 
- UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE__SHIFT
 
- UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE_MASK
 
- UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE__SHIFT
 
- UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED_MASK
 
- UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED__SHIFT
 
- UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES_MASK
 
- UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES__SHIFT
 
- UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN_MASK
 
- UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN__SHIFT
 
- UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN_MASK
 
- UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN__SHIFT
 
- UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS_MASK
 
- UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS__SHIFT
 
- UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN_MASK
 
- UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN__SHIFT
 
- UVD_JPEG_ENC_GPCOM_CMD__CMD_MASK
 
- UVD_JPEG_ENC_GPCOM_CMD__CMD__SHIFT
 
- UVD_JPEG_ENC_GPCOM_DATA0__DATA0_MASK
 
- UVD_JPEG_ENC_GPCOM_DATA0__DATA0__SHIFT
 
- UVD_JPEG_ENC_GPCOM_DATA1__DATA1_MASK
 
- UVD_JPEG_ENC_GPCOM_DATA1__DATA1__SHIFT
 
- UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN_MASK
 
- UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN__SHIFT
 
- UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN_MASK
 
- UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN__SHIFT
 
- UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN_MASK
 
- UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN__SHIFT
 
- UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN_MASK
 
- UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN__SHIFT
 
- UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN_MASK
 
- UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN__SHIFT
 
- UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN_MASK
 
- UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN__SHIFT
 
- UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN_MASK
 
- UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN__SHIFT
 
- UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS_MASK
 
- UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS__SHIFT
 
- UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS_MASK
 
- UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS__SHIFT
 
- UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS_MASK
 
- UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS__SHIFT
 
- UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS_MASK
 
- UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS__SHIFT
 
- UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS_MASK
 
- UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS__SHIFT
 
- UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS_MASK
 
- UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS__SHIFT
 
- UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS_MASK
 
- UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS__SHIFT
 
- UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE_MASK
 
- UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE__SHIFT
 
- UVD_JPEG_ENC_PITCH__PITCH_UV_MASK
 
- UVD_JPEG_ENC_PITCH__PITCH_UV__SHIFT
 
- UVD_JPEG_ENC_PITCH__PITCH_Y_MASK
 
- UVD_JPEG_ENC_PITCH__PITCH_Y__SHIFT
 
- UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN_MASK
 
- UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN__SHIFT
 
- UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK
 
- UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT
 
- UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK
 
- UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT
 
- UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK
 
- UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT
 
- UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK
 
- UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT
 
- UVD_JPEG_ENC_SCRATCH0__SCRATCH0_MASK
 
- UVD_JPEG_ENC_SCRATCH0__SCRATCH0__SHIFT
 
- UVD_JPEG_ENC_SCRATCH1__SCRATCH1_MASK
 
- UVD_JPEG_ENC_SCRATCH1__SCRATCH1__SHIFT
 
- UVD_JPEG_ENC_SOFT_RST__RESET_STATUS_MASK
 
- UVD_JPEG_ENC_SOFT_RST__RESET_STATUS__SHIFT
 
- UVD_JPEG_ENC_SOFT_RST__SOFT_RST_MASK
 
- UVD_JPEG_ENC_SOFT_RST__SOFT_RST__SHIFT
 
- UVD_JPEG_ENC_STATUS__FDCT_IDLE_MASK
 
- UVD_JPEG_ENC_STATUS__FDCT_IDLE__SHIFT
 
- UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE_MASK
 
- UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE__SHIFT
 
- UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE_MASK
 
- UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE__SHIFT
 
- UVD_JPEG_ENC_STATUS__SCALAR_IDLE_MASK
 
- UVD_JPEG_ENC_STATUS__SCALAR_IDLE__SHIFT
 
- UVD_JPEG_GPCOM_CMD__CMD_MASK
 
- UVD_JPEG_GPCOM_CMD__CMD_SEND_MASK
 
- UVD_JPEG_GPCOM_CMD__CMD_SEND__SHIFT
 
- UVD_JPEG_GPCOM_CMD__CMD_SOURCE_MASK
 
- UVD_JPEG_GPCOM_CMD__CMD_SOURCE__SHIFT
 
- UVD_JPEG_GPCOM_CMD__CMD__SHIFT
 
- UVD_JPEG_GPCOM_DATA0__DATA0_MASK
 
- UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT
 
- UVD_JPEG_GPCOM_DATA1__DATA1_MASK
 
- UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT
 
- UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN_MASK
 
- UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN__SHIFT
 
- UVD_JPEG_INT_EN__ECS_MK_ERR_EN_MASK
 
- UVD_JPEG_INT_EN__ECS_MK_ERR_EN__SHIFT
 
- UVD_JPEG_INT_EN__EOI_ERR_EN_MASK
 
- UVD_JPEG_INT_EN__EOI_ERR_EN__SHIFT
 
- UVD_JPEG_INT_EN__FENCE_VAL_EN_MASK
 
- UVD_JPEG_INT_EN__FENCE_VAL_EN__SHIFT
 
- UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN_MASK
 
- UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN__SHIFT
 
- UVD_JPEG_INT_EN__FMT_ERR_EN_MASK
 
- UVD_JPEG_INT_EN__FMT_ERR_EN__SHIFT
 
- UVD_JPEG_INT_EN__HFM_ERR_EN_MASK
 
- UVD_JPEG_INT_EN__HFM_ERR_EN__SHIFT
 
- UVD_JPEG_INT_EN__JOB_AVAIL_EN_MASK
 
- UVD_JPEG_INT_EN__JOB_AVAIL_EN__SHIFT
 
- UVD_JPEG_INT_EN__MARKER_ERR_EN_MASK
 
- UVD_JPEG_INT_EN__MARKER_ERR_EN__SHIFT
 
- UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN_MASK
 
- UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN__SHIFT
 
- UVD_JPEG_INT_EN__PROFILE_ERR_EN_MASK
 
- UVD_JPEG_INT_EN__PROFILE_ERR_EN__SHIFT
 
- UVD_JPEG_INT_EN__RST_ERR_EN_MASK
 
- UVD_JPEG_INT_EN__RST_ERR_EN__SHIFT
 
- UVD_JPEG_INT_EN__TIMEOUT_ERR_EN_MASK
 
- UVD_JPEG_INT_EN__TIMEOUT_ERR_EN__SHIFT
 
- UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT_MASK
 
- UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT__SHIFT
 
- UVD_JPEG_INT_STAT__ECS_MK_ERR_INT_MASK
 
- UVD_JPEG_INT_STAT__ECS_MK_ERR_INT__SHIFT
 
- UVD_JPEG_INT_STAT__EOI_ERR_INT_MASK
 
- UVD_JPEG_INT_STAT__EOI_ERR_INT__SHIFT
 
- UVD_JPEG_INT_STAT__FENCE_VAL_INT_MASK
 
- UVD_JPEG_INT_STAT__FENCE_VAL_INT__SHIFT
 
- UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT_MASK
 
- UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT__SHIFT
 
- UVD_JPEG_INT_STAT__FMT_ERR_INT_MASK
 
- UVD_JPEG_INT_STAT__FMT_ERR_INT__SHIFT
 
- UVD_JPEG_INT_STAT__HFM_ERR_INT_MASK
 
- UVD_JPEG_INT_STAT__HFM_ERR_INT__SHIFT
 
- UVD_JPEG_INT_STAT__JOB_AVAIL_INT_MASK
 
- UVD_JPEG_INT_STAT__JOB_AVAIL_INT__SHIFT
 
- UVD_JPEG_INT_STAT__MARKER_ERR_INT_MASK
 
- UVD_JPEG_INT_STAT__MARKER_ERR_INT__SHIFT
 
- UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT_MASK
 
- UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT__SHIFT
 
- UVD_JPEG_INT_STAT__PROFILE_ERR_INT_MASK
 
- UVD_JPEG_INT_STAT__PROFILE_ERR_INT__SHIFT
 
- UVD_JPEG_INT_STAT__RST_ERR_INT_MASK
 
- UVD_JPEG_INT_STAT__RST_ERR_INT__SHIFT
 
- UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT_MASK
 
- UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT__SHIFT
 
- UVD_JPEG_JRB_BASE_HI__JRB_BASE_HI_MASK
 
- UVD_JPEG_JRB_BASE_HI__JRB_BASE_HI__SHIFT
 
- UVD_JPEG_JRB_BASE_LO__JRB_BASE_LO_MASK
 
- UVD_JPEG_JRB_BASE_LO__JRB_BASE_LO__SHIFT
 
- UVD_JPEG_JRB_RPTR__JRB_RPTR_MASK
 
- UVD_JPEG_JRB_RPTR__JRB_RPTR__SHIFT
 
- UVD_JPEG_JRB_SIZE__JRB_SIZE_MASK
 
- UVD_JPEG_JRB_SIZE__JRB_SIZE__SHIFT
 
- UVD_JPEG_JRB_WPTR__JRB_WPTR_MASK
 
- UVD_JPEG_JRB_WPTR__JRB_WPTR__SHIFT
 
- UVD_JPEG_PITCH__PITCH_MASK
 
- UVD_JPEG_PITCH__PITCH__SHIFT
 
- UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK
 
- UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT
 
- UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK
 
- UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT
 
- UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS_MASK
 
- UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS__SHIFT
 
- UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS_MASK
 
- UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS__SHIFT
 
- UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP_MASK
 
- UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP__SHIFT
 
- UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK
 
- UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT
 
- UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK
 
- UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT
 
- UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK
 
- UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT
 
- UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK
 
- UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT
 
- UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK
 
- UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT
 
- UVD_JPEG_RB_BASE__RB_BASE_MASK
 
- UVD_JPEG_RB_BASE__RB_BASE__SHIFT
 
- UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK
 
- UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT
 
- UVD_JPEG_RB_RPTR__RB_RPTR_MASK
 
- UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT
 
- UVD_JPEG_RB_SIZE__RB_SIZE_MASK
 
- UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT
 
- UVD_JPEG_RB_WPTR__RB_WPTR_MASK
 
- UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT
 
- UVD_JPEG_SCRATCH1__SCRATCH1_MASK
 
- UVD_JPEG_SCRATCH1__SCRATCH1__SHIFT
 
- UVD_JPEG_UV_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK
 
- UVD_JPEG_UV_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT
 
- UVD_JPEG_UV_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK
 
- UVD_JPEG_UV_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT
 
- UVD_JPEG_UV_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK
 
- UVD_JPEG_UV_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT
 
- UVD_JPEG_UV_ADDR_CONFIG__NUM_BANKS_MASK
 
- UVD_JPEG_UV_ADDR_CONFIG__NUM_BANKS__SHIFT
 
- UVD_JPEG_UV_ADDR_CONFIG__NUM_GPUS_MASK
 
- UVD_JPEG_UV_ADDR_CONFIG__NUM_GPUS__SHIFT
 
- UVD_JPEG_UV_ADDR_CONFIG__NUM_LOWER_PIPES_MASK
 
- UVD_JPEG_UV_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT
 
- UVD_JPEG_UV_ADDR_CONFIG__NUM_PIPES_MASK
 
- UVD_JPEG_UV_ADDR_CONFIG__NUM_PIPES__SHIFT
 
- UVD_JPEG_UV_ADDR_CONFIG__NUM_RB_PER_SE_MASK
 
- UVD_JPEG_UV_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT
 
- UVD_JPEG_UV_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK
 
- UVD_JPEG_UV_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT
 
- UVD_JPEG_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK
 
- UVD_JPEG_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT
 
- UVD_JPEG_UV_ADDR_CONFIG__ROW_SIZE_MASK
 
- UVD_JPEG_UV_ADDR_CONFIG__ROW_SIZE__SHIFT
 
- UVD_JPEG_UV_ADDR_CONFIG__SE_ENABLE_MASK
 
- UVD_JPEG_UV_ADDR_CONFIG__SE_ENABLE__SHIFT
 
- UVD_JPEG_UV_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK
 
- UVD_JPEG_UV_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT
 
- UVD_JPEG_UV_PITCH__UV_PITCH_MASK
 
- UVD_JPEG_UV_PITCH__UV_PITCH__SHIFT
 
- UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK
 
- UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT
 
- UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID_MASK
 
- UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT
 
- UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK
 
- UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT
 
- UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK
 
- UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT
 
- UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK
 
- UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT
 
- UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK
 
- UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT
 
- UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK
 
- UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT
 
- UVD_JRBC_ENC_IB_REF_DATA__REF_DATA_MASK
 
- UVD_JRBC_ENC_IB_REF_DATA__REF_DATA__SHIFT
 
- UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK
 
- UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT
 
- UVD_JRBC_ENC_IB_SIZE__IB_SIZE_MASK
 
- UVD_JRBC_ENC_IB_SIZE__IB_SIZE__SHIFT
 
- UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK
 
- UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT
 
- UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID_MASK
 
- UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT
 
- UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK
 
- UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT
 
- UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH_MASK
 
- UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH__SHIFT
 
- UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK
 
- UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT
 
- UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN_MASK
 
- UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN__SHIFT
 
- UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK
 
- UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT
 
- UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK
 
- UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT
 
- UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK
 
- UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT
 
- UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK
 
- UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT
 
- UVD_JRBC_ENC_RB_REF_DATA__REF_DATA_MASK
 
- UVD_JRBC_ENC_RB_REF_DATA__REF_DATA__SHIFT
 
- UVD_JRBC_ENC_RB_RPTR__RB_RPTR_MASK
 
- UVD_JRBC_ENC_RB_RPTR__RB_RPTR__SHIFT
 
- UVD_JRBC_ENC_RB_SIZE__RB_SIZE_MASK
 
- UVD_JRBC_ENC_RB_SIZE__RB_SIZE__SHIFT
 
- UVD_JRBC_ENC_RB_WPTR__RB_WPTR_MASK
 
- UVD_JRBC_ENC_RB_WPTR__RB_WPTR__SHIFT
 
- UVD_JRBC_ENC_SCRATCH0__SCRATCH0_MASK
 
- UVD_JRBC_ENC_SCRATCH0__SCRATCH0__SHIFT
 
- UVD_JRBC_ENC_SOFT_RESET__RESET_MASK
 
- UVD_JRBC_ENC_SOFT_RESET__RESET__SHIFT
 
- UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS_MASK
 
- UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT
 
- UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK
 
- UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT
 
- UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD_MASK
 
- UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD__SHIFT
 
- UVD_JRBC_ENC_STATUS__IB_JOB_DONE_MASK
 
- UVD_JRBC_ENC_STATUS__IB_JOB_DONE__SHIFT
 
- UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT_MASK
 
- UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT
 
- UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT_MASK
 
- UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT
 
- UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS_MASK
 
- UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS__SHIFT
 
- UVD_JRBC_ENC_STATUS__INT_ACK_MASK
 
- UVD_JRBC_ENC_STATUS__INT_ACK__SHIFT
 
- UVD_JRBC_ENC_STATUS__INT_EN_MASK
 
- UVD_JRBC_ENC_STATUS__INT_EN__SHIFT
 
- UVD_JRBC_ENC_STATUS__PREEMPT_STATUS_MASK
 
- UVD_JRBC_ENC_STATUS__PREEMPT_STATUS__SHIFT
 
- UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK
 
- UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT
 
- UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD_MASK
 
- UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD__SHIFT
 
- UVD_JRBC_ENC_STATUS__RB_JOB_DONE_MASK
 
- UVD_JRBC_ENC_STATUS__RB_JOB_DONE__SHIFT
 
- UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT_MASK
 
- UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT
 
- UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT_MASK
 
- UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT
 
- UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS_MASK
 
- UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS__SHIFT
 
- UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK
 
- UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT
 
- UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK
 
- UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT
 
- UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK
 
- UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT
 
- UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK
 
- UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT
 
- UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK
 
- UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT
 
- UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK
 
- UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT
 
- UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK
 
- UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT
 
- UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK
 
- UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT
 
- UVD_JRBC_IB_REF_DATA__REF_DATA_MASK
 
- UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT
 
- UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK
 
- UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT
 
- UVD_JRBC_IB_SIZE__IB_SIZE_MASK
 
- UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT
 
- UVD_JRBC_LMI_SWAP_CNTL__IB_MC_SWAP_MASK
 
- UVD_JRBC_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT
 
- UVD_JRBC_LMI_SWAP_CNTL__RB_MC_SWAP_MASK
 
- UVD_JRBC_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT
 
- UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK
 
- UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT
 
- UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK
 
- UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT
 
- UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK
 
- UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT
 
- UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK
 
- UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT
 
- UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK
 
- UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT
 
- UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK
 
- UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT
 
- UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK
 
- UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT
 
- UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK
 
- UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT
 
- UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK
 
- UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT
 
- UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK
 
- UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT
 
- UVD_JRBC_RB_REF_DATA__REF_DATA_MASK
 
- UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT
 
- UVD_JRBC_RB_RPTR__RB_RPTR_MASK
 
- UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT
 
- UVD_JRBC_RB_SIZE__RB_SIZE_MASK
 
- UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT
 
- UVD_JRBC_RB_WPTR__RB_WPTR_MASK
 
- UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT
 
- UVD_JRBC_SCRATCH0__SCRATCH0_MASK
 
- UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT
 
- UVD_JRBC_SOFT_RESET__RESET_MASK
 
- UVD_JRBC_SOFT_RESET__RESET__SHIFT
 
- UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK
 
- UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT
 
- UVD_JRBC_SOFT_RESET__VCLK_RESET_STATUS_MASK
 
- UVD_JRBC_SOFT_RESET__VCLK_RESET_STATUS__SHIFT
 
- UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK
 
- UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT
 
- UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK
 
- UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT
 
- UVD_JRBC_STATUS__IB_JOB_DONE_MASK
 
- UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT
 
- UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK
 
- UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT
 
- UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK
 
- UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT
 
- UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK
 
- UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT
 
- UVD_JRBC_STATUS__INT_ACK_MASK
 
- UVD_JRBC_STATUS__INT_ACK__SHIFT
 
- UVD_JRBC_STATUS__INT_EN_MASK
 
- UVD_JRBC_STATUS__INT_EN__SHIFT
 
- UVD_JRBC_STATUS__PREEMPT_STATUS_MASK
 
- UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT
 
- UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK
 
- UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT
 
- UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK
 
- UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT
 
- UVD_JRBC_STATUS__RB_JOB_DONE_MASK
 
- UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT
 
- UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK
 
- UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT
 
- UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK
 
- UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT
 
- UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK
 
- UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT
 
- UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK
 
- UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT
 
- UVD_LCM_CGC_CNTRL__FORCE_OFF_MASK
 
- UVD_LCM_CGC_CNTRL__FORCE_OFF__SHIFT
 
- UVD_LCM_CGC_CNTRL__FORCE_ON_MASK
 
- UVD_LCM_CGC_CNTRL__FORCE_ON__SHIFT
 
- UVD_LCM_CGC_CNTRL__OFF_DELAY_MASK
 
- UVD_LCM_CGC_CNTRL__OFF_DELAY__SHIFT
 
- UVD_LCM_CGC_CNTRL__ON_DELAY_MASK
 
- UVD_LCM_CGC_CNTRL__ON_DELAY__SHIFT
 
- UVD_LMI_ADDR_EXT
 
- UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK
 
- UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT
 
- UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK
 
- UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT
 
- UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK
 
- UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT
 
- UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK
 
- UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT
 
- UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK
 
- UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT
 
- UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK
 
- UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT
 
- UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK
 
- UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT
 
- UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK
 
- UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT
 
- UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK
 
- UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT
 
- UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK
 
- UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT
 
- UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK
 
- UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT
 
- UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK
 
- UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT
 
- UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST_MASK
 
- UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST__SHIFT
 
- UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN_MASK
 
- UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN__SHIFT
 
- UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST_MASK
 
- UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST__SHIFT
 
- UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN_MASK
 
- UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN__SHIFT
 
- UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX_MASK
 
- UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX__SHIFT
 
- UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX_MASK
 
- UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX__SHIFT
 
- UVD_LMI_AVG_LAT_CNTR__ENV_HIGH_MASK
 
- UVD_LMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT
 
- UVD_LMI_AVG_LAT_CNTR__ENV_HIT_MASK
 
- UVD_LMI_AVG_LAT_CNTR__ENV_HIT__SHIFT
 
- UVD_LMI_AVG_LAT_CNTR__ENV_LOW_MASK
 
- UVD_LMI_AVG_LAT_CNTR__ENV_LOW__SHIFT
 
- UVD_LMI_CACHE_CTRL__CM_EN_MASK
 
- UVD_LMI_CACHE_CTRL__CM_EN__SHIFT
 
- UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK
 
- UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT
 
- UVD_LMI_CACHE_CTRL__IT_EN_MASK
 
- UVD_LMI_CACHE_CTRL__IT_EN__SHIFT
 
- UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK
 
- UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT
 
- UVD_LMI_CACHE_CTRL__VCPU_EN_MASK
 
- UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT
 
- UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK
 
- UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT
 
- UVD_LMI_CRC0__CRC32_MASK
 
- UVD_LMI_CRC0__CRC32__SHIFT
 
- UVD_LMI_CRC1__CRC32_MASK
 
- UVD_LMI_CRC1__CRC32__SHIFT
 
- UVD_LMI_CRC2__CRC32_MASK
 
- UVD_LMI_CRC2__CRC32__SHIFT
 
- UVD_LMI_CRC3__CRC32_MASK
 
- UVD_LMI_CRC3__CRC32__SHIFT
 
- UVD_LMI_CTRL
 
- UVD_LMI_CTRL2
 
- UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK
 
- UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT
 
- UVD_LMI_CTRL2__CLEAR_NJ_PF_BP_MASK
 
- UVD_LMI_CTRL2__CLEAR_NJ_PF_BP__SHIFT
 
- UVD_LMI_CTRL2__CRC1_RESET_MASK
 
- UVD_LMI_CTRL2__CRC1_RESET__SHIFT
 
- UVD_LMI_CTRL2__CRC1_SEL_MASK
 
- UVD_LMI_CTRL2__CRC1_SEL__SHIFT
 
- UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK
 
- UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT
 
- UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK
 
- UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT
 
- UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK
 
- UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT
 
- UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK
 
- UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT
 
- UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK
 
- UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT
 
- UVD_LMI_CTRL2__NJ_MIF_GATING_MASK
 
- UVD_LMI_CTRL2__NJ_MIF_GATING__SHIFT
 
- UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK
 
- UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT
 
- UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK
 
- UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT
 
- UVD_LMI_CTRL2__SPH_DIS_MASK
 
- UVD_LMI_CTRL2__SPH_DIS__SHIFT
 
- UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK
 
- UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT
 
- UVD_LMI_CTRL2__STALL_ARB_MASK
 
- UVD_LMI_CTRL2__STALL_ARB_UMC_MASK
 
- UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT
 
- UVD_LMI_CTRL2__STALL_ARB__SHIFT
 
- UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK
 
- UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT
 
- UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK
 
- UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT
 
- UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK
 
- UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT
 
- UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK
 
- UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT
 
- UVD_LMI_CTRL__CRC_RESET_MASK
 
- UVD_LMI_CTRL__CRC_RESET__SHIFT
 
- UVD_LMI_CTRL__CRC_SEL_MASK
 
- UVD_LMI_CTRL__CRC_SEL__SHIFT
 
- UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK
 
- UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT
 
- UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK
 
- UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT
 
- UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK
 
- UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT
 
- UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK
 
- UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT
 
- UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK
 
- UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT
 
- UVD_LMI_CTRL__MASK_MC_URGENT_MASK
 
- UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT
 
- UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ_MASK
 
- UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ__SHIFT
 
- UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK
 
- UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT
 
- UVD_LMI_CTRL__REQ_MODE_MASK
 
- UVD_LMI_CTRL__REQ_MODE__SHIFT
 
- UVD_LMI_CTRL__RFU_MASK
 
- UVD_LMI_CTRL__RFU__SHIFT
 
- UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK
 
- UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT
 
- UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK
 
- UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT
 
- UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK
 
- UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT
 
- UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN_MASK
 
- UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN__SHIFT
 
- UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN_MASK
 
- UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN__SHIFT
 
- UVD_LMI_EJPEG_CTRL__RD_MAX_BURST_MASK
 
- UVD_LMI_EJPEG_CTRL__RD_MAX_BURST__SHIFT
 
- UVD_LMI_EJPEG_CTRL__RD_SWAP_MASK
 
- UVD_LMI_EJPEG_CTRL__RD_SWAP__SHIFT
 
- UVD_LMI_EJPEG_CTRL__WR_MAX_BURST_MASK
 
- UVD_LMI_EJPEG_CTRL__WR_MAX_BURST__SHIFT
 
- UVD_LMI_EJPEG_CTRL__WR_SWAP_MASK
 
- UVD_LMI_EJPEG_CTRL__WR_SWAP__SHIFT
 
- UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID_MASK
 
- UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID__SHIFT
 
- UVD_LMI_EXT40_ADDR
 
- UVD_LMI_EXT40_ADDR__ADDR_MASK
 
- UVD_LMI_EXT40_ADDR__ADDR__SHIFT
 
- UVD_LMI_EXT40_ADDR__INDEX_MASK
 
- UVD_LMI_EXT40_ADDR__INDEX__SHIFT
 
- UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK
 
- UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT
 
- UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID_MASK
 
- UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID__SHIFT
 
- UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID_MASK
 
- UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID__SHIFT
 
- UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN_MASK
 
- UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN__SHIFT
 
- UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN_MASK
 
- UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN__SHIFT
 
- UVD_LMI_JPEG_CTRL2__RD_MAX_BURST_MASK
 
- UVD_LMI_JPEG_CTRL2__RD_MAX_BURST__SHIFT
 
- UVD_LMI_JPEG_CTRL2__RD_SWAP_MASK
 
- UVD_LMI_JPEG_CTRL2__RD_SWAP__SHIFT
 
- UVD_LMI_JPEG_CTRL2__WR_MAX_BURST_MASK
 
- UVD_LMI_JPEG_CTRL2__WR_MAX_BURST__SHIFT
 
- UVD_LMI_JPEG_CTRL2__WR_SWAP_MASK
 
- UVD_LMI_JPEG_CTRL2__WR_SWAP__SHIFT
 
- UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK
 
- UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT
 
- UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK
 
- UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT
 
- UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK
 
- UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT
 
- UVD_LMI_JPEG_CTRL__RD_SWAP_MASK
 
- UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT
 
- UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK
 
- UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT
 
- UVD_LMI_JPEG_CTRL__WR_SWAP_MASK
 
- UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT
 
- UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK
 
- UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT
 
- UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK
 
- UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT
 
- UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK
 
- UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT
 
- UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK
 
- UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT
 
- UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK
 
- UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT
 
- UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK
 
- UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT
 
- UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK
 
- UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT
 
- UVD_LMI_JRBC_CTRL__RD_SWAP_MASK
 
- UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT
 
- UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK
 
- UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT
 
- UVD_LMI_JRBC_CTRL__WR_SWAP_MASK
 
- UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT
 
- UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK
 
- UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT
 
- UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK
 
- UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT
 
- UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK
 
- UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT
 
- UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK
 
- UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT
 
- UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK
 
- UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT
 
- UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK
 
- UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT
 
- UVD_LMI_LAT_CNTR__MAX_LAT_MASK
 
- UVD_LMI_LAT_CNTR__MAX_LAT__SHIFT
 
- UVD_LMI_LAT_CNTR__MIN_LAT_MASK
 
- UVD_LMI_LAT_CNTR__MIN_LAT__SHIFT
 
- UVD_LMI_LAT_CTRL__AVG_START_MASK
 
- UVD_LMI_LAT_CTRL__AVG_START__SHIFT
 
- UVD_LMI_LAT_CTRL__MAX_START_MASK
 
- UVD_LMI_LAT_CTRL__MAX_START__SHIFT
 
- UVD_LMI_LAT_CTRL__MIN_START_MASK
 
- UVD_LMI_LAT_CTRL__MIN_START__SHIFT
 
- UVD_LMI_LAT_CTRL__PERFMON_SYNC_MASK
 
- UVD_LMI_LAT_CTRL__PERFMON_SYNC__SHIFT
 
- UVD_LMI_LAT_CTRL__SCALE_MASK
 
- UVD_LMI_LAT_CTRL__SCALE__SHIFT
 
- UVD_LMI_LAT_CTRL__SKIP_MASK
 
- UVD_LMI_LAT_CTRL__SKIP__SHIFT
 
- UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_MC_CREDITS__UMC_RD_CREDITS_MASK
 
- UVD_LMI_MC_CREDITS__UMC_RD_CREDITS__SHIFT
 
- UVD_LMI_MC_CREDITS__UMC_WR_CREDITS_MASK
 
- UVD_LMI_MC_CREDITS__UMC_WR_CREDITS__SHIFT
 
- UVD_LMI_MC_CREDITS__UVD_RD_CREDITS_MASK
 
- UVD_LMI_MC_CREDITS__UVD_RD_CREDITS__SHIFT
 
- UVD_LMI_MC_CREDITS__UVD_WR_CREDITS_MASK
 
- UVD_LMI_MC_CREDITS__UVD_WR_CREDITS__SHIFT
 
- UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN_MASK
 
- UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN__SHIFT
 
- UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP_MASK
 
- UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP__SHIFT
 
- UVD_LMI_MMSCH_CTRL__MMSCH_RD_MASK
 
- UVD_LMI_MMSCH_CTRL__MMSCH_RD__SHIFT
 
- UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP_MASK
 
- UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP__SHIFT
 
- UVD_LMI_MMSCH_CTRL__MMSCH_VM_MASK
 
- UVD_LMI_MMSCH_CTRL__MMSCH_VM__SHIFT
 
- UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP_MASK
 
- UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP__SHIFT
 
- UVD_LMI_MMSCH_CTRL__MMSCH_WR_MASK
 
- UVD_LMI_MMSCH_CTRL__MMSCH_WR__SHIFT
 
- UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP_MASK
 
- UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP__SHIFT
 
- UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID_MASK
 
- UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID__SHIFT
 
- UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID_MASK
 
- UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID__SHIFT
 
- UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID_MASK
 
- UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID__SHIFT
 
- UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID_MASK
 
- UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID__SHIFT
 
- UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID_MASK
 
- UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID__SHIFT
 
- UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID_MASK
 
- UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID__SHIFT
 
- UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID_MASK
 
- UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID__SHIFT
 
- UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID_MASK
 
- UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID__SHIFT
 
- UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK
 
- UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT
 
- UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK
 
- UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT
 
- UVD_LMI_PERFMON_CTRL__PERFMON_SEL_MASK
 
- UVD_LMI_PERFMON_CTRL__PERFMON_SEL__SHIFT
 
- UVD_LMI_PERFMON_CTRL__PERFMON_STATE_MASK
 
- UVD_LMI_PERFMON_CTRL__PERFMON_STATE__SHIFT
 
- UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_RBC_IB_VMID__IB_VMID_MASK
 
- UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT
 
- UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_RBC_RB_VMID__RB_VMID_MASK
 
- UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT
 
- UVD_LMI_SPH__ADDR_MASK
 
- UVD_LMI_SPH__ADDR__SHIFT
 
- UVD_LMI_SPH__STS_MASK
 
- UVD_LMI_SPH__STS_OVERFLOW_MASK
 
- UVD_LMI_SPH__STS_OVERFLOW__SHIFT
 
- UVD_LMI_SPH__STS_VALID_MASK
 
- UVD_LMI_SPH__STS_VALID__SHIFT
 
- UVD_LMI_SPH__STS__SHIFT
 
- UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK
 
- UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT
 
- UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK
 
- UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT
 
- UVD_LMI_STATUS__BSP0_WRITE_CLEAN_MASK
 
- UVD_LMI_STATUS__BSP0_WRITE_CLEAN__SHIFT
 
- UVD_LMI_STATUS__BSP1_WRITE_CLEAN_MASK
 
- UVD_LMI_STATUS__BSP1_WRITE_CLEAN__SHIFT
 
- UVD_LMI_STATUS__BSP2_WRITE_CLEAN_MASK
 
- UVD_LMI_STATUS__BSP2_WRITE_CLEAN__SHIFT
 
- UVD_LMI_STATUS__BSP3_WRITE_CLEAN_MASK
 
- UVD_LMI_STATUS__BSP3_WRITE_CLEAN__SHIFT
 
- UVD_LMI_STATUS__CENC_READ_CLEAN_MASK
 
- UVD_LMI_STATUS__CENC_READ_CLEAN__SHIFT
 
- UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK
 
- UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT
 
- UVD_LMI_STATUS__READ_CLEAN_MASK
 
- UVD_LMI_STATUS__READ_CLEAN_RAW_MASK
 
- UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT
 
- UVD_LMI_STATUS__READ_CLEAN__SHIFT
 
- UVD_LMI_STATUS__UMC_AVP_IDLE_MASK
 
- UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT
 
- UVD_LMI_STATUS__UMC_READ_CLEAN_MASK
 
- UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK
 
- UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT
 
- UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT
 
- UVD_LMI_STATUS__UMC_UVD_IDLE_MASK
 
- UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT
 
- UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK
 
- UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK
 
- UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT
 
- UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT
 
- UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK
 
- UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT
 
- UVD_LMI_STATUS__WRITE_CLEAN_MASK
 
- UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK
 
- UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT
 
- UVD_LMI_STATUS__WRITE_CLEAN__SHIFT
 
- UVD_LMI_SWAP_CNTL
 
- UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK
 
- UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT
 
- UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK
 
- UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT
 
- UVD_LMI_SWAP_CNTL__ACAP_MC_SWAP_MASK
 
- UVD_LMI_SWAP_CNTL__ACAP_MC_SWAP__SHIFT
 
- UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK
 
- UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT
 
- UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK
 
- UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT
 
- UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK
 
- UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT
 
- UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK
 
- UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT
 
- UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK
 
- UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT
 
- UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK
 
- UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT
 
- UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK
 
- UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT
 
- UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK
 
- UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT
 
- UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK
 
- UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT
 
- UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK
 
- UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT
 
- UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK
 
- UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT
 
- UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK
 
- UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT
 
- UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK
 
- UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT
 
- UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK
 
- UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT
 
- UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK
 
- UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT
 
- UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL_MASK
 
- UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL__SHIFT
 
- UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK
 
- UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT
 
- UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL_MASK
 
- UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL__SHIFT
 
- UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK
 
- UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT
 
- UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL_MASK
 
- UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL__SHIFT
 
- UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT_MASK
 
- UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT__SHIFT
 
- UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL_MASK
 
- UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL__SHIFT
 
- UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT_MASK
 
- UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT__SHIFT
 
- UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK
 
- UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT
 
- UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK
 
- UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT
 
- UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL_MASK
 
- UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL__SHIFT
 
- UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL_MASK
 
- UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL__SHIFT
 
- UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID_MASK
 
- UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID__SHIFT
 
- UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID_MASK
 
- UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID__SHIFT
 
- UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID_MASK
 
- UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID__SHIFT
 
- UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID_MASK
 
- UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID__SHIFT
 
- UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID_MASK
 
- UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID__SHIFT
 
- UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID_MASK
 
- UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID__SHIFT
 
- UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID_MASK
 
- UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID__SHIFT
 
- UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID_MASK
 
- UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID__SHIFT
 
- UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK
 
- UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT
 
- UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK
 
- UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT
 
- UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0_MASK
 
- UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT
 
- UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID_MASK
 
- UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID__SHIFT
 
- UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID_MASK
 
- UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID__SHIFT
 
- UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID_MASK
 
- UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID__SHIFT
 
- UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID_MASK
 
- UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID__SHIFT
 
- UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID_MASK
 
- UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID__SHIFT
 
- UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID_MASK
 
- UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID__SHIFT
 
- UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID_MASK
 
- UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID__SHIFT
 
- UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID_MASK
 
- UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID__SHIFT
 
- UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID_MASK
 
- UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID__SHIFT
 
- UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID_MASK
 
- UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID__SHIFT
 
- UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID_MASK
 
- UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID__SHIFT
 
- UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID_MASK
 
- UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID__SHIFT
 
- UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID_MASK
 
- UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID__SHIFT
 
- UVD_LMI_VMID_INTERNAL2__VDMA_VMID_MASK
 
- UVD_LMI_VMID_INTERNAL2__VDMA_VMID__SHIFT
 
- UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID_MASK
 
- UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID__SHIFT
 
- UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID_MASK
 
- UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID__SHIFT
 
- UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID_MASK
 
- UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID__SHIFT
 
- UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID_MASK
 
- UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID__SHIFT
 
- UVD_LMI_VMID_INTERNAL3__MIF_SCLR_VMID_MASK
 
- UVD_LMI_VMID_INTERNAL3__MIF_SCLR_VMID__SHIFT
 
- UVD_LMI_VMID_INTERNAL__DBW_VMID_MASK
 
- UVD_LMI_VMID_INTERNAL__DBW_VMID__SHIFT
 
- UVD_LMI_VMID_INTERNAL__DPB_VMID_MASK
 
- UVD_LMI_VMID_INTERNAL__DPB_VMID__SHIFT
 
- UVD_LMI_VMID_INTERNAL__IDCT_VMID_MASK
 
- UVD_LMI_VMID_INTERNAL__IDCT_VMID__SHIFT
 
- UVD_LMI_VMID_INTERNAL__JPEG2_VMID_MASK
 
- UVD_LMI_VMID_INTERNAL__JPEG2_VMID__SHIFT
 
- UVD_LMI_VMID_INTERNAL__JPEG_VMID_MASK
 
- UVD_LMI_VMID_INTERNAL__JPEG_VMID__SHIFT
 
- UVD_LMI_VMID_INTERNAL__LBSI_VMID_MASK
 
- UVD_LMI_VMID_INTERNAL__LBSI_VMID__SHIFT
 
- UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID_MASK
 
- UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID__SHIFT
 
- UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID_MASK
 
- UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID__SHIFT
 
- UVD_LMI_VM_CTRL__ACAP_VM_MASK
 
- UVD_LMI_VM_CTRL__ACAP_VM__SHIFT
 
- UVD_LMI_VM_CTRL__CM_VM_MASK
 
- UVD_LMI_VM_CTRL__CM_VM__SHIFT
 
- UVD_LMI_VM_CTRL__CSM_VM_MASK
 
- UVD_LMI_VM_CTRL__CSM_VM__SHIFT
 
- UVD_LMI_VM_CTRL__DBW_VM_MASK
 
- UVD_LMI_VM_CTRL__DBW_VM__SHIFT
 
- UVD_LMI_VM_CTRL__DB_VM_MASK
 
- UVD_LMI_VM_CTRL__DB_VM__SHIFT
 
- UVD_LMI_VM_CTRL__IB_VM_MASK
 
- UVD_LMI_VM_CTRL__IB_VM__SHIFT
 
- UVD_LMI_VM_CTRL__IT_VM_MASK
 
- UVD_LMI_VM_CTRL__IT_VM__SHIFT
 
- UVD_LMI_VM_CTRL__MP_VM_MASK
 
- UVD_LMI_VM_CTRL__MP_VM__SHIFT
 
- UVD_LMI_VM_CTRL__RB_RPTR_VM_MASK
 
- UVD_LMI_VM_CTRL__RB_RPTR_VM__SHIFT
 
- UVD_LMI_VM_CTRL__RB_VM_MASK
 
- UVD_LMI_VM_CTRL__RB_VM__SHIFT
 
- UVD_LMI_VM_CTRL__RB_WR_VM_MASK
 
- UVD_LMI_VM_CTRL__RB_WR_VM__SHIFT
 
- UVD_LMI_VM_CTRL__RE_VM_MASK
 
- UVD_LMI_VM_CTRL__RE_VM__SHIFT
 
- UVD_LMI_VM_CTRL__SCPU_VM_MASK
 
- UVD_LMI_VM_CTRL__SCPU_VM__SHIFT
 
- UVD_LMI_VM_CTRL__VCPU_VM_MASK
 
- UVD_LMI_VM_CTRL__VCPU_VM__SHIFT
 
- UVD_MASTINT_EN
 
- UVD_MASTINT_EN__INT_OVERRUN_MASK
 
- UVD_MASTINT_EN__INT_OVERRUN__SHIFT
 
- UVD_MASTINT_EN__OVERRUN_RST_MASK
 
- UVD_MASTINT_EN__OVERRUN_RST__SHIFT
 
- UVD_MASTINT_EN__SYS_EN_MASK
 
- UVD_MASTINT_EN__SYS_EN__SHIFT
 
- UVD_MASTINT_EN__VCPU_EN_MASK
 
- UVD_MASTINT_EN__VCPU_EN__SHIFT
 
- UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK
 
- UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT
 
- UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK
 
- UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT
 
- UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK
 
- UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT
 
- UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK
 
- UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT
 
- UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK
 
- UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT
 
- UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK
 
- UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT
 
- UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK
 
- UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT
 
- UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK
 
- UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT
 
- UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK
 
- UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT
 
- UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK
 
- UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT
 
- UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK
 
- UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT
 
- UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK
 
- UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT
 
- UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK
 
- UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT
 
- UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK
 
- UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT
 
- UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK
 
- UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT
 
- UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK
 
- UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT
 
- UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK
 
- UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT
 
- UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK
 
- UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT
 
- UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK
 
- UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT
 
- UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK
 
- UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT
 
- UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK
 
- UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT
 
- UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK
 
- UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT
 
- UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK
 
- UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT
 
- UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK
 
- UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT
 
- UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK
 
- UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT
 
- UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK
 
- UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT
 
- UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK
 
- UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT
 
- UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK
 
- UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT
 
- UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK
 
- UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT
 
- UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS_MASK
 
- UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS__SHIFT
 
- UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK
 
- UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT
 
- UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES_MASK
 
- UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES__SHIFT
 
- UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK
 
- UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT
 
- UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK
 
- UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT
 
- UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE_MASK
 
- UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE__SHIFT
 
- UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK
 
- UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT
 
- UVD_MMSCH_SOFT_RESET__MMSCH_LOCK_MASK
 
- UVD_MMSCH_SOFT_RESET__MMSCH_LOCK__SHIFT
 
- UVD_MMSCH_SOFT_RESET__MMSCH_RESET_MASK
 
- UVD_MMSCH_SOFT_RESET__MMSCH_RESET__SHIFT
 
- UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET_MASK
 
- UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET__SHIFT
 
- UVD_MPC_CHROMA_HITPEND__CNTR_MASK
 
- UVD_MPC_CHROMA_HITPEND__CNTR__SHIFT
 
- UVD_MPC_CHROMA_HIT__CNTR_MASK
 
- UVD_MPC_CHROMA_HIT__CNTR__SHIFT
 
- UVD_MPC_CHROMA_SRCH__CNTR_MASK
 
- UVD_MPC_CHROMA_SRCH__CNTR__SHIFT
 
- UVD_MPC_CNTL
 
- UVD_MPC_CNTL__AVE_WEIGHT_MASK
 
- UVD_MPC_CNTL__AVE_WEIGHT__SHIFT
 
- UVD_MPC_CNTL__DBG_MUX_MASK
 
- UVD_MPC_CNTL__DBG_MUX__SHIFT
 
- UVD_MPC_CNTL__PERF_RST_MASK
 
- UVD_MPC_CNTL__PERF_RST__SHIFT
 
- UVD_MPC_CNTL__REPLACEMENT_MODE_MASK
 
- UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT
 
- UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP_MASK
 
- UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP__SHIFT
 
- UVD_MPC_CNTL__TEST_MODE_EN_MASK
 
- UVD_MPC_CNTL__TEST_MODE_EN__SHIFT
 
- UVD_MPC_CNTL__URGENT_EN_MASK
 
- UVD_MPC_CNTL__URGENT_EN__SHIFT
 
- UVD_MPC_LUMA_HITPEND__CNTR_MASK
 
- UVD_MPC_LUMA_HITPEND__CNTR__SHIFT
 
- UVD_MPC_LUMA_HIT__CNTR_MASK
 
- UVD_MPC_LUMA_HIT__CNTR__SHIFT
 
- UVD_MPC_LUMA_SRCH__CNTR_MASK
 
- UVD_MPC_LUMA_SRCH__CNTR__SHIFT
 
- UVD_MPC_PERF0__MAX_LAT_MASK
 
- UVD_MPC_PERF0__MAX_LAT__SHIFT
 
- UVD_MPC_PERF1__AVE_LAT_MASK
 
- UVD_MPC_PERF1__AVE_LAT__SHIFT
 
- UVD_MPC_PITCH__LUMA_PITCH_MASK
 
- UVD_MPC_PITCH__LUMA_PITCH__SHIFT
 
- UVD_MPC_SET_ALU
 
- UVD_MPC_SET_ALU__FUNCT_MASK
 
- UVD_MPC_SET_ALU__FUNCT__SHIFT
 
- UVD_MPC_SET_ALU__OPERAND_MASK
 
- UVD_MPC_SET_ALU__OPERAND__SHIFT
 
- UVD_MPC_SET_MUX
 
- UVD_MPC_SET_MUXA0
 
- UVD_MPC_SET_MUXA0__VARA_0_MASK
 
- UVD_MPC_SET_MUXA0__VARA_0__SHIFT
 
- UVD_MPC_SET_MUXA0__VARA_1_MASK
 
- UVD_MPC_SET_MUXA0__VARA_1__SHIFT
 
- UVD_MPC_SET_MUXA0__VARA_2_MASK
 
- UVD_MPC_SET_MUXA0__VARA_2__SHIFT
 
- UVD_MPC_SET_MUXA0__VARA_3_MASK
 
- UVD_MPC_SET_MUXA0__VARA_3__SHIFT
 
- UVD_MPC_SET_MUXA0__VARA_4_MASK
 
- UVD_MPC_SET_MUXA0__VARA_4__SHIFT
 
- UVD_MPC_SET_MUXA1
 
- UVD_MPC_SET_MUXA1__VARA_5_MASK
 
- UVD_MPC_SET_MUXA1__VARA_5__SHIFT
 
- UVD_MPC_SET_MUXA1__VARA_6_MASK
 
- UVD_MPC_SET_MUXA1__VARA_6__SHIFT
 
- UVD_MPC_SET_MUXA1__VARA_7_MASK
 
- UVD_MPC_SET_MUXA1__VARA_7__SHIFT
 
- UVD_MPC_SET_MUXB0
 
- UVD_MPC_SET_MUXB0__VARB_0_MASK
 
- UVD_MPC_SET_MUXB0__VARB_0__SHIFT
 
- UVD_MPC_SET_MUXB0__VARB_1_MASK
 
- UVD_MPC_SET_MUXB0__VARB_1__SHIFT
 
- UVD_MPC_SET_MUXB0__VARB_2_MASK
 
- UVD_MPC_SET_MUXB0__VARB_2__SHIFT
 
- UVD_MPC_SET_MUXB0__VARB_3_MASK
 
- UVD_MPC_SET_MUXB0__VARB_3__SHIFT
 
- UVD_MPC_SET_MUXB0__VARB_4_MASK
 
- UVD_MPC_SET_MUXB0__VARB_4__SHIFT
 
- UVD_MPC_SET_MUXB1
 
- UVD_MPC_SET_MUXB1__VARB_5_MASK
 
- UVD_MPC_SET_MUXB1__VARB_5__SHIFT
 
- UVD_MPC_SET_MUXB1__VARB_6_MASK
 
- UVD_MPC_SET_MUXB1__VARB_6__SHIFT
 
- UVD_MPC_SET_MUXB1__VARB_7_MASK
 
- UVD_MPC_SET_MUXB1__VARB_7__SHIFT
 
- UVD_MPC_SET_MUX__SET_0_MASK
 
- UVD_MPC_SET_MUX__SET_0__SHIFT
 
- UVD_MPC_SET_MUX__SET_1_MASK
 
- UVD_MPC_SET_MUX__SET_1__SHIFT
 
- UVD_MPC_SET_MUX__SET_2_MASK
 
- UVD_MPC_SET_MUX__SET_2__SHIFT
 
- UVD_MP_SWAP_CNTL
 
- UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK
 
- UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT
 
- UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK
 
- UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT
 
- UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK
 
- UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT
 
- UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK
 
- UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT
 
- UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK
 
- UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT
 
- UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK
 
- UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT
 
- UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK
 
- UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT
 
- UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK
 
- UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT
 
- UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK
 
- UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT
 
- UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK
 
- UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT
 
- UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK
 
- UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT
 
- UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK
 
- UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT
 
- UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK
 
- UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT
 
- UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK
 
- UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT
 
- UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK
 
- UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT
 
- UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK
 
- UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT
 
- UVD_NO_OP
 
- UVD_NO_OP__NO_OP_MASK
 
- UVD_NO_OP__NO_OP__SHIFT
 
- UVD_OUT_RB_BASE_HI__RB_BASE_HI_MASK
 
- UVD_OUT_RB_BASE_HI__RB_BASE_HI__SHIFT
 
- UVD_OUT_RB_BASE_LO__RB_BASE_LO_MASK
 
- UVD_OUT_RB_BASE_LO__RB_BASE_LO__SHIFT
 
- UVD_OUT_RB_RPTR__RB_RPTR_MASK
 
- UVD_OUT_RB_RPTR__RB_RPTR__SHIFT
 
- UVD_OUT_RB_SIZE__RB_SIZE_MASK
 
- UVD_OUT_RB_SIZE__RB_SIZE__SHIFT
 
- UVD_OUT_RB_WPTR__RB_WPTR_MASK
 
- UVD_OUT_RB_WPTR__RB_WPTR__SHIFT
 
- UVD_PF_STATUS__DJ_ATM_PF_OCCURED_MASK
 
- UVD_PF_STATUS__DJ_ATM_PF_OCCURED__SHIFT
 
- UVD_PF_STATUS__EJPEG_PF_CLEAR_MASK
 
- UVD_PF_STATUS__EJPEG_PF_CLEAR__SHIFT
 
- UVD_PF_STATUS__EJPEG_PF_OCCURED_MASK
 
- UVD_PF_STATUS__EJPEG_PF_OCCURED__SHIFT
 
- UVD_PF_STATUS__EJ_ATM_PF_OCCURED_MASK
 
- UVD_PF_STATUS__EJ_ATM_PF_OCCURED__SHIFT
 
- UVD_PF_STATUS__ENCODER0_PF_CLEAR_MASK
 
- UVD_PF_STATUS__ENCODER0_PF_CLEAR__SHIFT
 
- UVD_PF_STATUS__ENCODER0_PF_OCCURED_MASK
 
- UVD_PF_STATUS__ENCODER0_PF_OCCURED__SHIFT
 
- UVD_PF_STATUS__ENCODER1_PF_CLEAR_MASK
 
- UVD_PF_STATUS__ENCODER1_PF_CLEAR__SHIFT
 
- UVD_PF_STATUS__ENCODER1_PF_OCCURED_MASK
 
- UVD_PF_STATUS__ENCODER1_PF_OCCURED__SHIFT
 
- UVD_PF_STATUS__ENCODER2_PF_CLEAR_MASK
 
- UVD_PF_STATUS__ENCODER2_PF_CLEAR__SHIFT
 
- UVD_PF_STATUS__ENCODER2_PF_OCCURED_MASK
 
- UVD_PF_STATUS__ENCODER2_PF_OCCURED__SHIFT
 
- UVD_PF_STATUS__ENCODER3_PF_CLEAR_MASK
 
- UVD_PF_STATUS__ENCODER3_PF_CLEAR__SHIFT
 
- UVD_PF_STATUS__ENCODER3_PF_OCCURED_MASK
 
- UVD_PF_STATUS__ENCODER3_PF_OCCURED__SHIFT
 
- UVD_PF_STATUS__ENCODER4_PF_CLEAR_MASK
 
- UVD_PF_STATUS__ENCODER4_PF_CLEAR__SHIFT
 
- UVD_PF_STATUS__ENCODER4_PF_OCCURED_MASK
 
- UVD_PF_STATUS__ENCODER4_PF_OCCURED__SHIFT
 
- UVD_PF_STATUS__JPEG_PF_CLEAR_MASK
 
- UVD_PF_STATUS__JPEG_PF_CLEAR__SHIFT
 
- UVD_PF_STATUS__JPEG_PF_OCCURED_MASK
 
- UVD_PF_STATUS__JPEG_PF_OCCURED__SHIFT
 
- UVD_PF_STATUS__NJ_ATM_PF_OCCURED_MASK
 
- UVD_PF_STATUS__NJ_ATM_PF_OCCURED__SHIFT
 
- UVD_PF_STATUS__NJ_PF_CLEAR_MASK
 
- UVD_PF_STATUS__NJ_PF_CLEAR__SHIFT
 
- UVD_PF_STATUS__NJ_PF_OCCURED_MASK
 
- UVD_PF_STATUS__NJ_PF_OCCURED__SHIFT
 
- UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK
 
- UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE__SHIFT
 
- UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG_MASK
 
- UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 
- UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG_MASK
 
- UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 
- UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG_MASK
 
- UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 
- UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG_MASK
 
- UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 
- UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG_MASK
 
- UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 
- UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG_MASK
 
- UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 
- UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG_MASK
 
- UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT
 
- UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK
 
- UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 
- UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON
 
- UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG_MASK
 
- UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 
- UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG_MASK
 
- UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 
- UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG_MASK
 
- UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 
- UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG_MASK
 
- UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT
 
- UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK
 
- UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT
 
- UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK
 
- UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT
 
- UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK
 
- UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT
 
- UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK
 
- UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT
 
- UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK
 
- UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT
 
- UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK
 
- UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT
 
- UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK
 
- UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT
 
- UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK
 
- UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT
 
- UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK
 
- UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT
 
- UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK
 
- UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT
 
- UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE_MASK
 
- UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE__SHIFT
 
- UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE_MASK
 
- UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE__SHIFT
 
- UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE_MASK
 
- UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE__SHIFT
 
- UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE_MASK
 
- UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE__SHIFT
 
- UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE_MASK
 
- UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE__SHIFT
 
- UVD_PGFSM_STATUS_UVDJ_PWR_ON
 
- UVD_PGFSM_STATUS__UVDB_PWR_STATUS_MASK
 
- UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
 
- UVD_PGFSM_STATUS__UVDC_PWR_STATUS_MASK
 
- UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
 
- UVD_PGFSM_STATUS__UVDE_PWR_STATUS_MASK
 
- UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
 
- UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK
 
- UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
 
- UVD_PGFSM_STATUS__UVDIL_PWR_STATUS_MASK
 
- UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
 
- UVD_PGFSM_STATUS__UVDIR_PWR_STATUS_MASK
 
- UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
 
- UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK
 
- UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT
 
- UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK
 
- UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
 
- UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON
 
- UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0
 
- UVD_PGFSM_STATUS__UVDTD_PWR_STATUS_MASK
 
- UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
 
- UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK
 
- UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
 
- UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK
 
- UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
 
- UVD_PGFSM_STATUS__UVDW_PWR_STATUS_MASK
 
- UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT
 
- UVD_PG_IND_DATA__DATA_MASK
 
- UVD_PG_IND_DATA__DATA__SHIFT
 
- UVD_PG_IND_INDEX__INDEX_MASK
 
- UVD_PG_IND_INDEX__INDEX__SHIFT
 
- UVD_PICCOUNT__DUM_MASK
 
- UVD_PICCOUNT__DUM__SHIFT
 
- UVD_PITCH__DUM_MASK
 
- UVD_PITCH__DUM__SHIFT
 
- UVD_POWER_STATUS_U__UVD_POWER_STATUS_MASK
 
- UVD_POWER_STATUS_U__UVD_POWER_STATUS__SHIFT
 
- UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK
 
- UVD_POWER_STATUS__JRBC_SNOOP_DIS__SHIFT
 
- UVD_POWER_STATUS__PAUSE_DPG_ACK_MASK
 
- UVD_POWER_STATUS__PAUSE_DPG_ACK__SHIFT
 
- UVD_POWER_STATUS__PAUSE_DPG_REQ_MASK
 
- UVD_POWER_STATUS__PAUSE_DPG_REQ__SHIFT
 
- UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT_MASK
 
- UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT__SHIFT
 
- UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT_MASK
 
- UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT__SHIFT
 
- UVD_POWER_STATUS__RBC_SNOOP_DIS_MASK
 
- UVD_POWER_STATUS__RBC_SNOOP_DIS__SHIFT
 
- UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK
 
- UVD_POWER_STATUS__STALL_DPG_POWER_UP__SHIFT
 
- UVD_POWER_STATUS__SW_RB_SNOOP_DIS_MASK
 
- UVD_POWER_STATUS__SW_RB_SNOOP_DIS__SHIFT
 
- UVD_POWER_STATUS__UVD_CG_MODE_MASK
 
- UVD_POWER_STATUS__UVD_CG_MODE__SHIFT
 
- UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE_MASK
 
- UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE__SHIFT
 
- UVD_POWER_STATUS__UVD_PG_EN_MASK
 
- UVD_POWER_STATUS__UVD_PG_EN__SHIFT
 
- UVD_POWER_STATUS__UVD_PG_MODE_MASK
 
- UVD_POWER_STATUS__UVD_PG_MODE__SHIFT
 
- UVD_POWER_STATUS__UVD_POWER_STATUS_MASK
 
- UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF
 
- UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT
 
- UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT_MASK
 
- UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT__SHIFT
 
- UVD_PWR_GATER_BUSY
 
- UVD_PWR_GATER_STATE
 
- UVD_RBC_BDM_PRE__BDM_ENABLE_MASK
 
- UVD_RBC_BDM_PRE__BDM_ENABLE__SHIFT
 
- UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR_MASK
 
- UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT
 
- UVD_RBC_BUF_STATUS__IB_BUF_VALID_MASK
 
- UVD_RBC_BUF_STATUS__IB_BUF_VALID__SHIFT
 
- UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR_MASK
 
- UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT
 
- UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR_MASK
 
- UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT
 
- UVD_RBC_BUF_STATUS__RB_BUF_VALID_MASK
 
- UVD_RBC_BUF_STATUS__RB_BUF_VALID__SHIFT
 
- UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR_MASK
 
- UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT
 
- UVD_RBC_CAM_DATA__RBC_CAM_DATA_MAP_MASK
 
- UVD_RBC_CAM_DATA__RBC_CAM_DATA_MAP__SHIFT
 
- UVD_RBC_CAM_DATA__RBC_CAM_DATA_ORG_MASK
 
- UVD_RBC_CAM_DATA__RBC_CAM_DATA_ORG__SHIFT
 
- UVD_RBC_CAM_EN__RBC_CAM_EN_MASK
 
- UVD_RBC_CAM_EN__RBC_CAM_EN__SHIFT
 
- UVD_RBC_CAM_INDEX__RBC_CAM_INDEX_MASK
 
- UVD_RBC_CAM_INDEX__RBC_CAM_INDEX__SHIFT
 
- UVD_RBC_CXW_RELEASE__SOFT_RELEASE_RBC_MASK
 
- UVD_RBC_CXW_RELEASE__SOFT_RELEASE_RBC__SHIFT
 
- UVD_RBC_IB_BASE
 
- UVD_RBC_IB_BASE__IB_BASE_MASK
 
- UVD_RBC_IB_BASE__IB_BASE__SHIFT
 
- UVD_RBC_IB_SIZE
 
- UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK
 
- UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT
 
- UVD_RBC_IB_SIZE__IB_SIZE_MASK
 
- UVD_RBC_IB_SIZE__IB_SIZE__SHIFT
 
- UVD_RBC_RB_BASE
 
- UVD_RBC_RB_BASE__RB_BASE_MASK
 
- UVD_RBC_RB_BASE__RB_BASE__SHIFT
 
- UVD_RBC_RB_CNTL
 
- UVD_RBC_RB_CNTL__RB_BLKSZ_MASK
 
- UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT
 
- UVD_RBC_RB_CNTL__RB_BUFSZ_MASK
 
- UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT
 
- UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK
 
- UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT
 
- UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK
 
- UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT
 
- UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK
 
- UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT
 
- UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK
 
- UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT
 
- UVD_RBC_RB_RPTR
 
- UVD_RBC_RB_RPTR_ADDR
 
- UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK
 
- UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT
 
- UVD_RBC_RB_RPTR__RB_RPTR_MASK
 
- UVD_RBC_RB_RPTR__RB_RPTR__SHIFT
 
- UVD_RBC_RB_WPTR
 
- UVD_RBC_RB_WPTR_CNTL
 
- UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK
 
- UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT
 
- UVD_RBC_RB_WPTR__RB_WPTR_MASK
 
- UVD_RBC_RB_WPTR__RB_WPTR__SHIFT
 
- UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK
 
- UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT
 
- UVD_RBC_VCPU_ACCESS__ENABLE_RBC_MASK
 
- UVD_RBC_VCPU_ACCESS__ENABLE_RBC__SHIFT
 
- UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR_MASK
 
- UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR__SHIFT
 
- UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK
 
- UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT
 
- UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ_MASK
 
- UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ__SHIFT
 
- UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE_MASK
 
- UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE__SHIFT
 
- UVD_RB_ARB_CTRL
 
- UVD_RB_ARB_CTRL__FAST_PATH_EN_MASK
 
- UVD_RB_ARB_CTRL__FAST_PATH_EN__SHIFT
 
- UVD_RB_ARB_CTRL__FWOFLD_DIS_MASK
 
- UVD_RB_ARB_CTRL__FWOFLD_DIS__SHIFT
 
- UVD_RB_ARB_CTRL__FWOFLD_DROP_MASK
 
- UVD_RB_ARB_CTRL__FWOFLD_DROP__SHIFT
 
- UVD_RB_ARB_CTRL__RBC_DIS_MASK
 
- UVD_RB_ARB_CTRL__RBC_DIS__SHIFT
 
- UVD_RB_ARB_CTRL__RBC_DROP_MASK
 
- UVD_RB_ARB_CTRL__RBC_DROP__SHIFT
 
- UVD_RB_ARB_CTRL__SRBM_DIS_MASK
 
- UVD_RB_ARB_CTRL__SRBM_DIS__SHIFT
 
- UVD_RB_ARB_CTRL__SRBM_DROP_MASK
 
- UVD_RB_ARB_CTRL__SRBM_DROP__SHIFT
 
- UVD_RB_ARB_CTRL__VCPU_DIS_MASK
 
- UVD_RB_ARB_CTRL__VCPU_DIS__SHIFT
 
- UVD_RB_ARB_CTRL__VCPU_DROP_MASK
 
- UVD_RB_ARB_CTRL__VCPU_DROP__SHIFT
 
- UVD_RB_BASE_HI2__RB_BASE_HI_MASK
 
- UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT
 
- UVD_RB_BASE_HI3__RB_BASE_HI_MASK
 
- UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT
 
- UVD_RB_BASE_HI4__RB_BASE_HI_MASK
 
- UVD_RB_BASE_HI4__RB_BASE_HI__SHIFT
 
- UVD_RB_BASE_HI__RB_BASE_HI_MASK
 
- UVD_RB_BASE_HI__RB_BASE_HI__SHIFT
 
- UVD_RB_BASE_LO2__RB_BASE_LO_MASK
 
- UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT
 
- UVD_RB_BASE_LO3__RB_BASE_LO_MASK
 
- UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT
 
- UVD_RB_BASE_LO4__RB_BASE_LO_MASK
 
- UVD_RB_BASE_LO4__RB_BASE_LO__SHIFT
 
- UVD_RB_BASE_LO__RB_BASE_LO_MASK
 
- UVD_RB_BASE_LO__RB_BASE_LO__SHIFT
 
- UVD_RB_RPTR2__RB_RPTR_MASK
 
- UVD_RB_RPTR2__RB_RPTR__SHIFT
 
- UVD_RB_RPTR3__RB_RPTR_MASK
 
- UVD_RB_RPTR3__RB_RPTR__SHIFT
 
- UVD_RB_RPTR4__RB_RPTR_MASK
 
- UVD_RB_RPTR4__RB_RPTR__SHIFT
 
- UVD_RB_RPTR__RB_RPTR_MASK
 
- UVD_RB_RPTR__RB_RPTR__SHIFT
 
- UVD_RB_SIZE2__RB_SIZE_MASK
 
- UVD_RB_SIZE2__RB_SIZE__SHIFT
 
- UVD_RB_SIZE3__RB_SIZE_MASK
 
- UVD_RB_SIZE3__RB_SIZE__SHIFT
 
- UVD_RB_SIZE4__RB_SIZE_MASK
 
- UVD_RB_SIZE4__RB_SIZE__SHIFT
 
- UVD_RB_SIZE__RB_SIZE_MASK
 
- UVD_RB_SIZE__RB_SIZE__SHIFT
 
- UVD_RB_WPTR2__RB_WPTR_MASK
 
- UVD_RB_WPTR2__RB_WPTR__SHIFT
 
- UVD_RB_WPTR3__RB_WPTR_MASK
 
- UVD_RB_WPTR3__RB_WPTR__SHIFT
 
- UVD_RB_WPTR4__RB_WPTR_MASK
 
- UVD_RB_WPTR4__RB_WPTR__SHIFT
 
- UVD_RB_WPTR__RB_WPTR_MASK
 
- UVD_RB_WPTR__RB_WPTR__SHIFT
 
- UVD_RQ_PENDING
 
- UVD_SCRATCH10__SCRATCH10_DATA_MASK
 
- UVD_SCRATCH10__SCRATCH10_DATA__SHIFT
 
- UVD_SCRATCH11__SCRATCH11_DATA_MASK
 
- UVD_SCRATCH11__SCRATCH11_DATA__SHIFT
 
- UVD_SCRATCH12__SCRATCH12_DATA_MASK
 
- UVD_SCRATCH12__SCRATCH12_DATA__SHIFT
 
- UVD_SCRATCH13__SCRATCH13_DATA_MASK
 
- UVD_SCRATCH13__SCRATCH13_DATA__SHIFT
 
- UVD_SCRATCH14__SCRATCH14_DATA_MASK
 
- UVD_SCRATCH14__SCRATCH14_DATA__SHIFT
 
- UVD_SCRATCH1__SCRATCH1_DATA_MASK
 
- UVD_SCRATCH1__SCRATCH1_DATA__SHIFT
 
- UVD_SCRATCH2__SCRATCH2_DATA_MASK
 
- UVD_SCRATCH2__SCRATCH2_DATA__SHIFT
 
- UVD_SCRATCH3__SCRATCH3_DATA_MASK
 
- UVD_SCRATCH3__SCRATCH3_DATA__SHIFT
 
- UVD_SCRATCH4__SCRATCH4_DATA_MASK
 
- UVD_SCRATCH4__SCRATCH4_DATA__SHIFT
 
- UVD_SCRATCH5__SCRATCH5_DATA_MASK
 
- UVD_SCRATCH5__SCRATCH5_DATA__SHIFT
 
- UVD_SCRATCH6__SCRATCH6_DATA_MASK
 
- UVD_SCRATCH6__SCRATCH6_DATA__SHIFT
 
- UVD_SCRATCH7__SCRATCH7_DATA_MASK
 
- UVD_SCRATCH7__SCRATCH7_DATA__SHIFT
 
- UVD_SCRATCH8__SCRATCH8_DATA_MASK
 
- UVD_SCRATCH8__SCRATCH8_DATA__SHIFT
 
- UVD_SCRATCH9__SCRATCH9_DATA_MASK
 
- UVD_SCRATCH9__SCRATCH9_DATA__SHIFT
 
- UVD_SCRATCH_NP__DATA_MASK
 
- UVD_SCRATCH_NP__DATA__SHIFT
 
- UVD_SEMA_ADDR_HIGH
 
- UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK
 
- UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT
 
- UVD_SEMA_ADDR_HIGH__ADDR_47_27_MASK
 
- UVD_SEMA_ADDR_HIGH__ADDR_47_27__SHIFT
 
- UVD_SEMA_ADDR_LOW
 
- UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK
 
- UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT
 
- UVD_SEMA_ADDR_LOW__ADDR_26_3_MASK
 
- UVD_SEMA_ADDR_LOW__ADDR_26_3__SHIFT
 
- UVD_SEMA_CMD
 
- UVD_SEMA_CMD__MODE_MASK
 
- UVD_SEMA_CMD__MODE__SHIFT
 
- UVD_SEMA_CMD__REQ_CMD_MASK
 
- UVD_SEMA_CMD__REQ_CMD__SHIFT
 
- UVD_SEMA_CMD__VMID_EN_MASK
 
- UVD_SEMA_CMD__VMID_EN__SHIFT
 
- UVD_SEMA_CMD__VMID_MASK
 
- UVD_SEMA_CMD__VMID__SHIFT
 
- UVD_SEMA_CMD__WR_PHASE_MASK
 
- UVD_SEMA_CMD__WR_PHASE__SHIFT
 
- UVD_SEMA_CNTL
 
- UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK
 
- UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT
 
- UVD_SEMA_CNTL__SEMAPHORE_EN_MASK
 
- UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT
 
- UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL
 
- UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK
 
- UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT
 
- UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK
 
- UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT
 
- UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK
 
- UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT
 
- UVD_SEMA_TIMEOUT_STATUS
 
- UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK
 
- UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT
 
- UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK
 
- UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT
 
- UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK
 
- UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT
 
- UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK
 
- UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT
 
- UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL
 
- UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK
 
- UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT
 
- UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK
 
- UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT
 
- UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK
 
- UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT
 
- UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL
 
- UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK
 
- UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT
 
- UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK
 
- UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT
 
- UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK
 
- UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT
 
- UVD_SOFT_RESET
 
- UVD_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK
 
- UVD_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT
 
- UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS_MASK
 
- UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS__SHIFT
 
- UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS_MASK
 
- UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS__SHIFT
 
- UVD_SOFT_RESET__CSM_SOFT_RESET_MASK
 
- UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT
 
- UVD_SOFT_RESET__CXW_SOFT_RESET_MASK
 
- UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT
 
- UVD_SOFT_RESET__EFC_SOFT_RESET_MASK
 
- UVD_SOFT_RESET__EFC_SOFT_RESET__SHIFT
 
- UVD_SOFT_RESET__FWV_SOFT_RESET_MASK
 
- UVD_SOFT_RESET__FWV_SOFT_RESET__SHIFT
 
- UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK
 
- UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT
 
- UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK
 
- UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT
 
- UVD_SOFT_RESET__IH_SOFT_RESET_MASK
 
- UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT
 
- UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS_MASK
 
- UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS__SHIFT
 
- UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK
 
- UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT
 
- UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK
 
- UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT
 
- UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK
 
- UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT
 
- UVD_SOFT_RESET__LCM_SOFT_RESET_MASK
 
- UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT
 
- UVD_SOFT_RESET__LMI_SOFT_RESET_MASK
 
- UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT
 
- UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK
 
- UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT
 
- UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK
 
- UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT
 
- UVD_SOFT_RESET__MIF_SOFT_RESET_MASK
 
- UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT
 
- UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK
 
- UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT
 
- UVD_SOFT_RESET__MPC_SOFT_RESET_MASK
 
- UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT
 
- UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK
 
- UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT
 
- UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK
 
- UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT
 
- UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK
 
- UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT
 
- UVD_SOFT_RESET__RBC_SOFT_RESET_MASK
 
- UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT
 
- UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK
 
- UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT
 
- UVD_SOFT_RESET__SPH_SOFT_RESET_MASK
 
- UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT
 
- UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK
 
- UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT
 
- UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK
 
- UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT
 
- UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK
 
- UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT
 
- UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK
 
- UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT
 
- UVD_SOFT_RESET__TAP_SOFT_RESET_MASK
 
- UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT
 
- UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK
 
- UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT
 
- UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK
 
- UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT
 
- UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK
 
- UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT
 
- UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK
 
- UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT
 
- UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK
 
- UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT
 
- UVD_STATUS
 
- UVD_STATUS__AVP_BLOCK_ACK_MASK
 
- UVD_STATUS__AVP_BLOCK_ACK__SHIFT
 
- UVD_STATUS__AVP_BUSY_MASK
 
- UVD_STATUS__AVP_BUSY__SHIFT
 
- UVD_STATUS__BUSY
 
- UVD_STATUS__IDCT_BLOCK_ACK_MASK
 
- UVD_STATUS__IDCT_BLOCK_ACK__SHIFT
 
- UVD_STATUS__IDCT_BUSY_MASK
 
- UVD_STATUS__IDCT_BUSY__SHIFT
 
- UVD_STATUS__IDCT_CTL_ACK_MASK
 
- UVD_STATUS__IDCT_CTL_ACK__SHIFT
 
- UVD_STATUS__IDLE
 
- UVD_STATUS__RBC_ACCESS_GPCOM_MASK
 
- UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT
 
- UVD_STATUS__RBC_BUSY
 
- UVD_STATUS__RBC_BUSY_MASK
 
- UVD_STATUS__RBC_BUSY__SHIFT
 
- UVD_STATUS__SYS_GPCOM_REQ_MASK
 
- UVD_STATUS__SYS_GPCOM_REQ__SHIFT
 
- UVD_STATUS__UVD_BLOCK_ACK_MASK
 
- UVD_STATUS__UVD_BLOCK_ACK__SHIFT
 
- UVD_STATUS__UVD_BUSY
 
- UVD_STATUS__UVD_CTL_ACK_MASK
 
- UVD_STATUS__UVD_CTL_ACK__SHIFT
 
- UVD_STATUS__VCPU_REPORT_MASK
 
- UVD_STATUS__VCPU_REPORT__SHIFT
 
- UVD_STOP_CONTEXT__CONTEXT_MODE_MASK
 
- UVD_STOP_CONTEXT__CONTEXT_MODE__SHIFT
 
- UVD_STOP_CONTEXT__STOP_CONTEXT_MASK
 
- UVD_STOP_CONTEXT__STOP_CONTEXT__SHIFT
 
- UVD_SUVD_CGC_CTRL__EFC_MODE_MASK
 
- UVD_SUVD_CGC_CTRL__EFC_MODE__SHIFT
 
- UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 
- UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT
 
- UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 
- UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT
 
- UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 
- UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT
 
- UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 
- UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT
 
- UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 
- UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT
 
- UVD_SUVD_CGC_CTRL__SITE_MODE_MASK
 
- UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT
 
- UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 
- UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT
 
- UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 
- UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT
 
- UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 
- UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT
 
- UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 
- UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT
 
- UVD_SUVD_CGC_GATE__EFC_MASK
 
- UVD_SUVD_CGC_GATE__EFC__SHIFT
 
- UVD_SUVD_CGC_GATE__ENT_MASK
 
- UVD_SUVD_CGC_GATE__ENT__SHIFT
 
- UVD_SUVD_CGC_GATE__IME_HEVC_MASK
 
- UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT
 
- UVD_SUVD_CGC_GATE__IME_MASK
 
- UVD_SUVD_CGC_GATE__IME__SHIFT
 
- UVD_SUVD_CGC_GATE__SCLR_MASK
 
- UVD_SUVD_CGC_GATE__SCLR__SHIFT
 
- UVD_SUVD_CGC_GATE__SCM_H264_MASK
 
- UVD_SUVD_CGC_GATE__SCM_H264__SHIFT
 
- UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
 
- UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT
 
- UVD_SUVD_CGC_GATE__SCM_MASK
 
- UVD_SUVD_CGC_GATE__SCM_VP9_MASK
 
- UVD_SUVD_CGC_GATE__SCM_VP9__SHIFT
 
- UVD_SUVD_CGC_GATE__SCM__SHIFT
 
- UVD_SUVD_CGC_GATE__SDB_H264_MASK
 
- UVD_SUVD_CGC_GATE__SDB_H264__SHIFT
 
- UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
 
- UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT
 
- UVD_SUVD_CGC_GATE__SDB_MASK
 
- UVD_SUVD_CGC_GATE__SDB_VP9_MASK
 
- UVD_SUVD_CGC_GATE__SDB_VP9__SHIFT
 
- UVD_SUVD_CGC_GATE__SDB__SHIFT
 
- UVD_SUVD_CGC_GATE__SITE_MASK
 
- UVD_SUVD_CGC_GATE__SITE__SHIFT
 
- UVD_SUVD_CGC_GATE__SIT_H264_MASK
 
- UVD_SUVD_CGC_GATE__SIT_H264__SHIFT
 
- UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
 
- UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT
 
- UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
 
- UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT
 
- UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
 
- UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT
 
- UVD_SUVD_CGC_GATE__SIT_MASK
 
- UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
 
- UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT
 
- UVD_SUVD_CGC_GATE__SIT__SHIFT
 
- UVD_SUVD_CGC_GATE__SMP_MASK
 
- UVD_SUVD_CGC_GATE__SMP__SHIFT
 
- UVD_SUVD_CGC_GATE__SRE_H264_MASK
 
- UVD_SUVD_CGC_GATE__SRE_H264__SHIFT
 
- UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
 
- UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT
 
- UVD_SUVD_CGC_GATE__SRE_MASK
 
- UVD_SUVD_CGC_GATE__SRE_VP9_MASK
 
- UVD_SUVD_CGC_GATE__SRE_VP9__SHIFT
 
- UVD_SUVD_CGC_GATE__SRE__SHIFT
 
- UVD_SUVD_CGC_GATE__UVD_SC_MASK
 
- UVD_SUVD_CGC_GATE__UVD_SC__SHIFT
 
- UVD_SUVD_CGC_STATUS__EFC_DCLK_MASK
 
- UVD_SUVD_CGC_STATUS__EFC_DCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK
 
- UVD_SUVD_CGC_STATUS__ENT_DCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__IME_DCLK_MASK
 
- UVD_SUVD_CGC_STATUS__IME_DCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK
 
- UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK
 
- UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK
 
- UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK
 
- UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK
 
- UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK_MASK
 
- UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK
 
- UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK
 
- UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK
 
- UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK_MASK
 
- UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__SITE_DCLK_MASK
 
- UVD_SUVD_CGC_STATUS__SITE_DCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK_MASK
 
- UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK_MASK
 
- UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK
 
- UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK
 
- UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK
 
- UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK_MASK
 
- UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK
 
- UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK
 
- UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK
 
- UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK
 
- UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK
 
- UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK
 
- UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK
 
- UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK_MASK
 
- UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK__SHIFT
 
- UVD_SUVD_CGC_STATUS__UVD_SC_MASK
 
- UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT
 
- UVD_SYS_INT_ACK__AVM_INT_ACK_MASK
 
- UVD_SYS_INT_ACK__AVM_INT_ACK__SHIFT
 
- UVD_SYS_INT_ACK__CLK_SWT_ACK_MASK
 
- UVD_SYS_INT_ACK__CLK_SWT_ACK__SHIFT
 
- UVD_SYS_INT_ACK__CXW_WR_ACK_MASK
 
- UVD_SYS_INT_ACK__CXW_WR_ACK__SHIFT
 
- UVD_SYS_INT_ACK__FCS_ACK_MASK
 
- UVD_SYS_INT_ACK__FCS_ACK__SHIFT
 
- UVD_SYS_INT_ACK__IDCT_ACK_MASK
 
- UVD_SYS_INT_ACK__IDCT_ACK__SHIFT
 
- UVD_SYS_INT_ACK__JOB_DONE_ACK_MASK
 
- UVD_SYS_INT_ACK__JOB_DONE_ACK__SHIFT
 
- UVD_SYS_INT_ACK__LBSI_ACK_MASK
 
- UVD_SYS_INT_ACK__LBSI_ACK__SHIFT
 
- UVD_SYS_INT_ACK__MIF_HWINT_ACK_MASK
 
- UVD_SYS_INT_ACK__MIF_HWINT_ACK__SHIFT
 
- UVD_SYS_INT_ACK__MPRD_ACK_MASK
 
- UVD_SYS_INT_ACK__MPRD_ACK__SHIFT
 
- UVD_SYS_INT_ACK__MPRD_ERR_ACK_MASK
 
- UVD_SYS_INT_ACK__MPRD_ERR_ACK__SHIFT
 
- UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK_MASK
 
- UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT
 
- UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK
 
- UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT
 
- UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_IDCT_ACK_MASK
 
- UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_IDCT_ACK__SHIFT
 
- UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK
 
- UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT
 
- UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK
 
- UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT
 
- UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK
 
- UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT
 
- UVD_SYS_INT_ACK__UDEC_ACK_MASK
 
- UVD_SYS_INT_ACK__UDEC_ACK__SHIFT
 
- UVD_SYS_INT_ACK__UVD_HOST_CXW_ACK_MASK
 
- UVD_SYS_INT_ACK__UVD_HOST_CXW_ACK__SHIFT
 
- UVD_SYS_INT_ACK__WPTR_IDLE_ACK_MASK
 
- UVD_SYS_INT_ACK__WPTR_IDLE_ACK__SHIFT
 
- UVD_SYS_INT_EN__AVM_INT_EN_MASK
 
- UVD_SYS_INT_EN__AVM_INT_EN__SHIFT
 
- UVD_SYS_INT_EN__CLK_SWT_EN_MASK
 
- UVD_SYS_INT_EN__CLK_SWT_EN__SHIFT
 
- UVD_SYS_INT_EN__CXW_WR_EN_MASK
 
- UVD_SYS_INT_EN__CXW_WR_EN__SHIFT
 
- UVD_SYS_INT_EN__FCS_EN_MASK
 
- UVD_SYS_INT_EN__FCS_EN__SHIFT
 
- UVD_SYS_INT_EN__IDCT_EN_MASK
 
- UVD_SYS_INT_EN__IDCT_EN__SHIFT
 
- UVD_SYS_INT_EN__JOB_DONE_EN_MASK
 
- UVD_SYS_INT_EN__JOB_DONE_EN__SHIFT
 
- UVD_SYS_INT_EN__LBSI_EN_MASK
 
- UVD_SYS_INT_EN__LBSI_EN__SHIFT
 
- UVD_SYS_INT_EN__MIF_HWINT_EN_MASK
 
- UVD_SYS_INT_EN__MIF_HWINT_EN__SHIFT
 
- UVD_SYS_INT_EN__MPRD_EN_MASK
 
- UVD_SYS_INT_EN__MPRD_EN__SHIFT
 
- UVD_SYS_INT_EN__MPRD_ERR_EN_MASK
 
- UVD_SYS_INT_EN__MPRD_ERR_EN__SHIFT
 
- UVD_SYS_INT_EN__PIF_ADDR_ERR_EN_MASK
 
- UVD_SYS_INT_EN__PIF_ADDR_ERR_EN__SHIFT
 
- UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK
 
- UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT
 
- UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_IDCT_EN_MASK
 
- UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_IDCT_EN__SHIFT
 
- UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK
 
- UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT
 
- UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK
 
- UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT
 
- UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK
 
- UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT
 
- UVD_SYS_INT_EN__UDEC_EN_MASK
 
- UVD_SYS_INT_EN__UDEC_EN__SHIFT
 
- UVD_SYS_INT_EN__UVD_HOST_CXW_EN_MASK
 
- UVD_SYS_INT_EN__UVD_HOST_CXW_EN__SHIFT
 
- UVD_SYS_INT_EN__UVD_JRBC_EN_MASK
 
- UVD_SYS_INT_EN__UVD_JRBC_EN__SHIFT
 
- UVD_SYS_INT_EN__WPTR_IDLE_EN_MASK
 
- UVD_SYS_INT_EN__WPTR_IDLE_EN__SHIFT
 
- UVD_SYS_INT_STATUS__AVM_INT_MASK
 
- UVD_SYS_INT_STATUS__AVM_INT__SHIFT
 
- UVD_SYS_INT_STATUS__CLK_SWT_INT_MASK
 
- UVD_SYS_INT_STATUS__CLK_SWT_INT__SHIFT
 
- UVD_SYS_INT_STATUS__CXW_WR_INT_MASK
 
- UVD_SYS_INT_STATUS__CXW_WR_INT__SHIFT
 
- UVD_SYS_INT_STATUS__FCS_INT_MASK
 
- UVD_SYS_INT_STATUS__FCS_INT__SHIFT
 
- UVD_SYS_INT_STATUS__GPCOM_INT_MASK
 
- UVD_SYS_INT_STATUS__GPCOM_INT__SHIFT
 
- UVD_SYS_INT_STATUS__IDCT_INT_MASK
 
- UVD_SYS_INT_STATUS__IDCT_INT__SHIFT
 
- UVD_SYS_INT_STATUS__JOB_DONE_INT_MASK
 
- UVD_SYS_INT_STATUS__JOB_DONE_INT__SHIFT
 
- UVD_SYS_INT_STATUS__LBSI_INT_MASK
 
- UVD_SYS_INT_STATUS__LBSI_INT__SHIFT
 
- UVD_SYS_INT_STATUS__MIF_HWINT_MASK
 
- UVD_SYS_INT_STATUS__MIF_HWINT__SHIFT
 
- UVD_SYS_INT_STATUS__MPRD_ERR_INT_MASK
 
- UVD_SYS_INT_STATUS__MPRD_ERR_INT__SHIFT
 
- UVD_SYS_INT_STATUS__MPRD_INT_MASK
 
- UVD_SYS_INT_STATUS__MPRD_INT__SHIFT
 
- UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT_MASK
 
- UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT
 
- UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_IDCT_INT_MASK
 
- UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_IDCT_INT__SHIFT
 
- UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK
 
- UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT
 
- UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK
 
- UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT
 
- UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK
 
- UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT
 
- UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK
 
- UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT
 
- UVD_SYS_INT_STATUS__UDEC_INT_MASK
 
- UVD_SYS_INT_STATUS__UDEC_INT__SHIFT
 
- UVD_SYS_INT_STATUS__UVD_HOST_CXW_INT_MASK
 
- UVD_SYS_INT_STATUS__UVD_HOST_CXW_INT__SHIFT
 
- UVD_SYS_INT_STATUS__WPTR_IDLE_INT_MASK
 
- UVD_SYS_INT_STATUS__WPTR_IDLE_INT__SHIFT
 
- UVD_TOP_CTRL__STANDARD_MASK
 
- UVD_TOP_CTRL__STANDARD__SHIFT
 
- UVD_TOP_CTRL__STD_VERSION_MASK
 
- UVD_TOP_CTRL__STD_VERSION__SHIFT
 
- UVD_TSC_LOWER__COUNT_MASK
 
- UVD_TSC_LOWER__COUNT__SHIFT
 
- UVD_TSC_UPPER__COUNT_MASK
 
- UVD_TSC_UPPER__COUNT__SHIFT
 
- UVD_UDEC_ADDR_CONFIG
 
- UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK
 
- UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT
 
- UVD_UDEC_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK
 
- UVD_UDEC_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT
 
- UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK
 
- UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT
 
- UVD_UDEC_ADDR_CONFIG__NUM_BANKS_MASK
 
- UVD_UDEC_ADDR_CONFIG__NUM_BANKS__SHIFT
 
- UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK
 
- UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT
 
- UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK
 
- UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT
 
- UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK
 
- UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT
 
- UVD_UDEC_ADDR_CONFIG__NUM_RB_PER_SE_MASK
 
- UVD_UDEC_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT
 
- UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK
 
- UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT
 
- UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK
 
- UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT
 
- UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK
 
- UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT
 
- UVD_UDEC_ADDR_CONFIG__SE_ENABLE_MASK
 
- UVD_UDEC_ADDR_CONFIG__SE_ENABLE__SHIFT
 
- UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK
 
- UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT
 
- UVD_UDEC_ADR__SYNC_RE_MASK
 
- UVD_UDEC_ADR__SYNC_RE__SHIFT
 
- UVD_UDEC_DBW_ADDR_CONFIG
 
- UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK
 
- UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT
 
- UVD_UDEC_DBW_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK
 
- UVD_UDEC_DBW_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT
 
- UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK
 
- UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT
 
- UVD_UDEC_DBW_ADDR_CONFIG__NUM_BANKS_MASK
 
- UVD_UDEC_DBW_ADDR_CONFIG__NUM_BANKS__SHIFT
 
- UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK
 
- UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT
 
- UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK
 
- UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT
 
- UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK
 
- UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT
 
- UVD_UDEC_DBW_ADDR_CONFIG__NUM_RB_PER_SE_MASK
 
- UVD_UDEC_DBW_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT
 
- UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK
 
- UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT
 
- UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK
 
- UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT
 
- UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK
 
- UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT
 
- UVD_UDEC_DBW_ADDR_CONFIG__SE_ENABLE_MASK
 
- UVD_UDEC_DBW_ADDR_CONFIG__SE_ENABLE__SHIFT
 
- UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK
 
- UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT
 
- UVD_UDEC_DBW_TILING_CONFIG
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_BANKS_MASK
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_BANKS__SHIFT
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_GPUS_MASK
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_GPUS__SHIFT
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_LOWER_PIPES_MASK
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_PIPES_MASK
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_PIPES__SHIFT
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_RB_PER_SE_MASK
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__ROW_SIZE_MASK
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__ROW_SIZE__SHIFT
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__SE_ENABLE_MASK
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__SE_ENABLE__SHIFT
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK
 
- UVD_UDEC_DBW_UV_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT
 
- UVD_UDEC_DB_ADDR_CONFIG
 
- UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK
 
- UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT
 
- UVD_UDEC_DB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK
 
- UVD_UDEC_DB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT
 
- UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK
 
- UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT
 
- UVD_UDEC_DB_ADDR_CONFIG__NUM_BANKS_MASK
 
- UVD_UDEC_DB_ADDR_CONFIG__NUM_BANKS__SHIFT
 
- UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK
 
- UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT
 
- UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK
 
- UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT
 
- UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK
 
- UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT
 
- UVD_UDEC_DB_ADDR_CONFIG__NUM_RB_PER_SE_MASK
 
- UVD_UDEC_DB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT
 
- UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK
 
- UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT
 
- UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK
 
- UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT
 
- UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK
 
- UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT
 
- UVD_UDEC_DB_ADDR_CONFIG__SE_ENABLE_MASK
 
- UVD_UDEC_DB_ADDR_CONFIG__SE_ENABLE__SHIFT
 
- UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK
 
- UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT
 
- UVD_UDEC_DB_TILING_CONFIG
 
- UVD_UDEC_TILING_CONFIG
 
- UVD_UMC_UVD_BLOCK_REQ__CMC_BLOCK_REQ_MASK
 
- UVD_UMC_UVD_BLOCK_REQ__CMC_BLOCK_REQ__SHIFT
 
- UVD_UMC_UVD_CTL_CMD__CMC_REQ_MASK
 
- UVD_UMC_UVD_CTL_CMD__CMC_REQ__SHIFT
 
- UVD_UVBASE__DUM_MASK
 
- UVD_UVBASE__DUM__SHIFT
 
- UVD_VCPU_CACHE_OFFSET0
 
- UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK
 
- UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT
 
- UVD_VCPU_CACHE_OFFSET1
 
- UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK
 
- UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT
 
- UVD_VCPU_CACHE_OFFSET2
 
- UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK
 
- UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT
 
- UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3_MASK
 
- UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3__SHIFT
 
- UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4_MASK
 
- UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4__SHIFT
 
- UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5_MASK
 
- UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5__SHIFT
 
- UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6_MASK
 
- UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6__SHIFT
 
- UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7_MASK
 
- UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7__SHIFT
 
- UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8_MASK
 
- UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8__SHIFT
 
- UVD_VCPU_CACHE_SIZE0
 
- UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK
 
- UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT
 
- UVD_VCPU_CACHE_SIZE1
 
- UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK
 
- UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT
 
- UVD_VCPU_CACHE_SIZE2
 
- UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK
 
- UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT
 
- UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3_MASK
 
- UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3__SHIFT
 
- UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4_MASK
 
- UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4__SHIFT
 
- UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK
 
- UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5__SHIFT
 
- UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6_MASK
 
- UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6__SHIFT
 
- UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7_MASK
 
- UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7__SHIFT
 
- UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8_MASK
 
- UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8__SHIFT
 
- UVD_VCPU_CHIP_ID
 
- UVD_VCPU_CNTL
 
- UVD_VCPU_CNTL__ABORT_REQ_MASK
 
- UVD_VCPU_CNTL__ABORT_REQ__SHIFT
 
- UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK
 
- UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT
 
- UVD_VCPU_CNTL__BLK_RST_MASK
 
- UVD_VCPU_CNTL__BLK_RST__SHIFT
 
- UVD_VCPU_CNTL__CABAC_MB_ACC_MASK
 
- UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT
 
- UVD_VCPU_CNTL__CLK_ACTIVE_MASK
 
- UVD_VCPU_CNTL__CLK_ACTIVE__SHIFT
 
- UVD_VCPU_CNTL__CLK_EN_MASK
 
- UVD_VCPU_CNTL__CLK_EN__SHIFT
 
- UVD_VCPU_CNTL__DBG_MUX_MASK
 
- UVD_VCPU_CNTL__DBG_MUX__SHIFT
 
- UVD_VCPU_CNTL__ECPU_AM32_EN_MASK
 
- UVD_VCPU_CNTL__ECPU_AM32_EN__SHIFT
 
- UVD_VCPU_CNTL__IRQ_ERR_MASK
 
- UVD_VCPU_CNTL__IRQ_ERR__SHIFT
 
- UVD_VCPU_CNTL__JTAG_EN_MASK
 
- UVD_VCPU_CNTL__JTAG_EN__SHIFT
 
- UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK
 
- UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT
 
- UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK
 
- UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT
 
- UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK
 
- UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT
 
- UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK
 
- UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT
 
- UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK
 
- UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT
 
- UVD_VCPU_CNTL__RE_OFFLOAD_EN_MASK
 
- UVD_VCPU_CNTL__RE_OFFLOAD_EN__SHIFT
 
- UVD_VCPU_CNTL__SUVD_EN_MASK
 
- UVD_VCPU_CNTL__SUVD_EN__SHIFT
 
- UVD_VCPU_CNTL__TIMEOUT_DIS_MASK
 
- UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT
 
- UVD_VCPU_CNTL__TRCE_EN_MASK
 
- UVD_VCPU_CNTL__TRCE_EN__SHIFT
 
- UVD_VCPU_CNTL__TRCE_MUX_MASK
 
- UVD_VCPU_CNTL__TRCE_MUX__SHIFT
 
- UVD_VCPU_CNTL__WMV9_EN_MASK
 
- UVD_VCPU_CNTL__WMV9_EN__SHIFT
 
- UVD_VCPU_INT_ACK__AVM_INT_ACK_MASK
 
- UVD_VCPU_INT_ACK__AVM_INT_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__CLK_SWT_ACK_MASK
 
- UVD_VCPU_INT_ACK__CLK_SWT_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK_MASK
 
- UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK_MASK
 
- UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__IDCT_ACK_MASK
 
- UVD_VCPU_INT_ACK__IDCT_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__JOB_START_ACK_MASK
 
- UVD_VCPU_INT_ACK__JOB_START_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__LBSI_ACK_MASK
 
- UVD_VCPU_INT_ACK__LBSI_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__MIF_HWINT_ACK_MASK
 
- UVD_VCPU_INT_ACK__MIF_HWINT_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__MPRD_ACK_MASK
 
- UVD_VCPU_INT_ACK__MPRD_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__MPRD_ERR_ACK_MASK
 
- UVD_VCPU_INT_ACK__MPRD_ERR_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__NJ_PF_ACK_MASK
 
- UVD_VCPU_INT_ACK__NJ_PF_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK_MASK
 
- UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK_MASK
 
- UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK
 
- UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_IDCT_ACK_MASK
 
- UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_IDCT_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__RPTR_WR_ACK_MASK
 
- UVD_VCPU_INT_ACK__RPTR_WR_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK
 
- UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK
 
- UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK
 
- UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__SW_RB1_INT_ACK_MASK
 
- UVD_VCPU_INT_ACK__SW_RB1_INT_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__SW_RB2_INT_ACK_MASK
 
- UVD_VCPU_INT_ACK__SW_RB2_INT_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__SW_RB3_INT_ACK_MASK
 
- UVD_VCPU_INT_ACK__SW_RB3_INT_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__SW_RB4_INT_ACK_MASK
 
- UVD_VCPU_INT_ACK__SW_RB4_INT_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__SW_RB5_INT_ACK_MASK
 
- UVD_VCPU_INT_ACK__SW_RB5_INT_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__UDEC_ACK_MASK
 
- UVD_VCPU_INT_ACK__UDEC_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__UVD_HOST_CXW_ACK_MASK
 
- UVD_VCPU_INT_ACK__UVD_HOST_CXW_ACK__SHIFT
 
- UVD_VCPU_INT_ACK__WPTR_IDLE_ACK_MASK
 
- UVD_VCPU_INT_ACK__WPTR_IDLE_ACK__SHIFT
 
- UVD_VCPU_INT_EN__AVM_INT_EN_MASK
 
- UVD_VCPU_INT_EN__AVM_INT_EN__SHIFT
 
- UVD_VCPU_INT_EN__CLK_SWT_EN_MASK
 
- UVD_VCPU_INT_EN__CLK_SWT_EN__SHIFT
 
- UVD_VCPU_INT_EN__DRV_FW_ACK_EN_MASK
 
- UVD_VCPU_INT_EN__DRV_FW_ACK_EN__SHIFT
 
- UVD_VCPU_INT_EN__DRV_FW_REQ_EN_MASK
 
- UVD_VCPU_INT_EN__DRV_FW_REQ_EN__SHIFT
 
- UVD_VCPU_INT_EN__IDCT_EN_MASK
 
- UVD_VCPU_INT_EN__IDCT_EN__SHIFT
 
- UVD_VCPU_INT_EN__JOB_START_EN_MASK
 
- UVD_VCPU_INT_EN__JOB_START_EN__SHIFT
 
- UVD_VCPU_INT_EN__LBSI_EN_MASK
 
- UVD_VCPU_INT_EN__LBSI_EN__SHIFT
 
- UVD_VCPU_INT_EN__MIF_HWINT_EN_MASK
 
- UVD_VCPU_INT_EN__MIF_HWINT_EN__SHIFT
 
- UVD_VCPU_INT_EN__MPRD_EN_MASK
 
- UVD_VCPU_INT_EN__MPRD_EN__SHIFT
 
- UVD_VCPU_INT_EN__MPRD_ERR_EN_MASK
 
- UVD_VCPU_INT_EN__MPRD_ERR_EN__SHIFT
 
- UVD_VCPU_INT_EN__NJ_PF_EN_MASK
 
- UVD_VCPU_INT_EN__NJ_PF_EN__SHIFT
 
- UVD_VCPU_INT_EN__NJ_PF_RPT_EN_MASK
 
- UVD_VCPU_INT_EN__NJ_PF_RPT_EN__SHIFT
 
- UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN_MASK
 
- UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN__SHIFT
 
- UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK
 
- UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT
 
- UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_IDCT_EN_MASK
 
- UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_IDCT_EN__SHIFT
 
- UVD_VCPU_INT_EN__RPTR_WR_EN_MASK
 
- UVD_VCPU_INT_EN__RPTR_WR_EN__SHIFT
 
- UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK
 
- UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT
 
- UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK
 
- UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT
 
- UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK
 
- UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT
 
- UVD_VCPU_INT_EN__SW_RB1_INT_EN_MASK
 
- UVD_VCPU_INT_EN__SW_RB1_INT_EN__SHIFT
 
- UVD_VCPU_INT_EN__SW_RB2_INT_EN_MASK
 
- UVD_VCPU_INT_EN__SW_RB2_INT_EN__SHIFT
 
- UVD_VCPU_INT_EN__SW_RB3_INT_EN_MASK
 
- UVD_VCPU_INT_EN__SW_RB3_INT_EN__SHIFT
 
- UVD_VCPU_INT_EN__SW_RB4_INT_EN_MASK
 
- UVD_VCPU_INT_EN__SW_RB4_INT_EN__SHIFT
 
- UVD_VCPU_INT_EN__SW_RB5_INT_EN_MASK
 
- UVD_VCPU_INT_EN__SW_RB5_INT_EN__SHIFT
 
- UVD_VCPU_INT_EN__UDEC_EN_MASK
 
- UVD_VCPU_INT_EN__UDEC_EN__SHIFT
 
- UVD_VCPU_INT_EN__UVD_HOST_CXW_EN_MASK
 
- UVD_VCPU_INT_EN__UVD_HOST_CXW_EN__SHIFT
 
- UVD_VCPU_INT_EN__WPTR_IDLE_EN_MASK
 
- UVD_VCPU_INT_EN__WPTR_IDLE_EN__SHIFT
 
- UVD_VCPU_INT_ROUTE__DRV_FW_MSG_MASK
 
- UVD_VCPU_INT_ROUTE__DRV_FW_MSG__SHIFT
 
- UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK_MASK
 
- UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK__SHIFT
 
- UVD_VCPU_INT_ROUTE__VCPU_GPCOM_MASK
 
- UVD_VCPU_INT_ROUTE__VCPU_GPCOM__SHIFT
 
- UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0_MASK
 
- UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0__SHIFT
 
- UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1_MASK
 
- UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1__SHIFT
 
- UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0_MASK
 
- UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0__SHIFT
 
- UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1_MASK
 
- UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1__SHIFT
 
- UVD_VCPU_PRID__PRID_MASK
 
- UVD_VCPU_PRID__PRID__SHIFT
 
- UVD_VCPU_TRCE_RD__DATA_MASK
 
- UVD_VCPU_TRCE_RD__DATA__SHIFT
 
- UVD_VCPU_TRCE__PC_MASK
 
- UVD_VCPU_TRCE__PC__SHIFT
 
- UVD_VERSION__MAJOR_VERSION_MASK
 
- UVD_VERSION__MAJOR_VERSION__SHIFT
 
- UVD_VERSION__MINOR_VERSION_MASK
 
- UVD_VERSION__MINOR_VERSION__SHIFT
 
- UVD_WIDTH__DUM_MASK
 
- UVD_WIDTH__DUM__SHIFT
 
- UVD_YBASE__DUM_MASK
 
- UVD_YBASE__DUM__SHIFT
 
- UVERBS_ACCESS_DESTROY
 
- UVERBS_ACCESS_NEW
 
- UVERBS_ACCESS_READ
 
- UVERBS_ACCESS_WRITE
 
- UVERBS_API_ATTR_BKEY_LEN
 
- UVERBS_API_ATTR_KEY_BITS
 
- UVERBS_API_ATTR_KEY_MASK
 
- UVERBS_API_KEY_ERR
 
- UVERBS_API_METHOD_IS_WRITE
 
- UVERBS_API_METHOD_IS_WRITE_EX
 
- UVERBS_API_METHOD_KEY_BITS
 
- UVERBS_API_METHOD_KEY_MASK
 
- UVERBS_API_METHOD_KEY_NUM_CORE
 
- UVERBS_API_METHOD_KEY_NUM_DRIVER
 
- UVERBS_API_METHOD_KEY_SHIFT
 
- UVERBS_API_NS_FLAG
 
- UVERBS_API_OBJ_KEY_BITS
 
- UVERBS_API_OBJ_KEY_MASK
 
- UVERBS_API_OBJ_KEY_NUM_CORE
 
- UVERBS_API_OBJ_KEY_NUM_DRIVER
 
- UVERBS_API_OBJ_KEY_SHIFT
 
- UVERBS_API_WRITE_KEY_NUM
 
- UVERBS_ATTR_ADVISE_MR_ADVICE
 
- UVERBS_ATTR_ADVISE_MR_FLAGS
 
- UVERBS_ATTR_ADVISE_MR_PD_HANDLE
 
- UVERBS_ATTR_ADVISE_MR_SGE_LIST
 
- UVERBS_ATTR_ALLOC_DM_ALIGNMENT
 
- UVERBS_ATTR_ALLOC_DM_HANDLE
 
- UVERBS_ATTR_ALLOC_DM_LENGTH
 
- UVERBS_ATTR_CONST_IN
 
- UVERBS_ATTR_CORE_IN
 
- UVERBS_ATTR_CORE_OUT
 
- UVERBS_ATTR_CREATE_COUNTERS_HANDLE
 
- UVERBS_ATTR_CREATE_CQ_COMP_CHANNEL
 
- UVERBS_ATTR_CREATE_CQ_COMP_VECTOR
 
- UVERBS_ATTR_CREATE_CQ_CQE
 
- UVERBS_ATTR_CREATE_CQ_FLAGS
 
- UVERBS_ATTR_CREATE_CQ_HANDLE
 
- UVERBS_ATTR_CREATE_CQ_RESP_CQE
 
- UVERBS_ATTR_CREATE_CQ_USER_HANDLE
 
- UVERBS_ATTR_CREATE_FLOW_ACTION_ESP_HANDLE
 
- UVERBS_ATTR_DESTROY_AH_HANDLE
 
- UVERBS_ATTR_DESTROY_COUNTERS_HANDLE
 
- UVERBS_ATTR_DESTROY_CQ_HANDLE
 
- UVERBS_ATTR_DESTROY_CQ_RESP
 
- UVERBS_ATTR_DESTROY_FLOW_ACTION_HANDLE
 
- UVERBS_ATTR_DESTROY_FLOW_HANDLE
 
- UVERBS_ATTR_DESTROY_MR_HANDLE
 
- UVERBS_ATTR_DESTROY_MW_HANDLE
 
- UVERBS_ATTR_DESTROY_PD_HANDLE
 
- UVERBS_ATTR_DESTROY_RWQ_IND_TBL_HANDLE
 
- UVERBS_ATTR_DESTROY_XRCD_HANDLE
 
- UVERBS_ATTR_ENUM_IN
 
- UVERBS_ATTR_FD
 
- UVERBS_ATTR_FLAGS_IN
 
- UVERBS_ATTR_FLOW_ACTION_ESP_ATTRS
 
- UVERBS_ATTR_FLOW_ACTION_ESP_ENCAP
 
- UVERBS_ATTR_FLOW_ACTION_ESP_ESN
 
- UVERBS_ATTR_FLOW_ACTION_ESP_KEYMAT
 
- UVERBS_ATTR_FLOW_ACTION_ESP_REPLAY
 
- UVERBS_ATTR_FREE_DM_HANDLE
 
- UVERBS_ATTR_F_MANDATORY
 
- UVERBS_ATTR_F_VALID_OUTPUT
 
- UVERBS_ATTR_IDR
 
- UVERBS_ATTR_IDRS_ARR
 
- UVERBS_ATTR_INFO_HANDLES_LIST
 
- UVERBS_ATTR_INFO_OBJECT_ID
 
- UVERBS_ATTR_INFO_TOTAL_HANDLES
 
- UVERBS_ATTR_MIN_SIZE
 
- UVERBS_ATTR_MODIFY_FLOW_ACTION_ESP_HANDLE
 
- UVERBS_ATTR_NO_DATA
 
- UVERBS_ATTR_PTR_IN
 
- UVERBS_ATTR_PTR_OUT
 
- UVERBS_ATTR_QUERY_PORT_PORT_NUM
 
- UVERBS_ATTR_QUERY_PORT_RESP
 
- UVERBS_ATTR_READ_COUNTERS_BUFF
 
- UVERBS_ATTR_READ_COUNTERS_FLAGS
 
- UVERBS_ATTR_READ_COUNTERS_HANDLE
 
- UVERBS_ATTR_REG_DM_MR_ACCESS_FLAGS
 
- UVERBS_ATTR_REG_DM_MR_DM_HANDLE
 
- UVERBS_ATTR_REG_DM_MR_HANDLE
 
- UVERBS_ATTR_REG_DM_MR_LENGTH
 
- UVERBS_ATTR_REG_DM_MR_OFFSET
 
- UVERBS_ATTR_REG_DM_MR_PD_HANDLE
 
- UVERBS_ATTR_REG_DM_MR_RESP_LKEY
 
- UVERBS_ATTR_REG_DM_MR_RESP_RKEY
 
- UVERBS_ATTR_SIZE
 
- UVERBS_ATTR_STRUCT
 
- UVERBS_ATTR_TYPE
 
- UVERBS_ATTR_TYPE_ENUM_IN
 
- UVERBS_ATTR_TYPE_FD
 
- UVERBS_ATTR_TYPE_IDR
 
- UVERBS_ATTR_TYPE_IDRS_ARRAY
 
- UVERBS_ATTR_TYPE_NA
 
- UVERBS_ATTR_TYPE_PTR_IN
 
- UVERBS_ATTR_TYPE_PTR_OUT
 
- UVERBS_ATTR_UHW
 
- UVERBS_ATTR_UHW_IN
 
- UVERBS_ATTR_UHW_OUT
 
- UVERBS_ATTR_WRITE_CMD
 
- UVERBS_BUILD_BUG_ON
 
- UVERBS_H
 
- UVERBS_HANDLER
 
- UVERBS_IDR_ANY_OBJECT
 
- UVERBS_ID_NS_MASK
 
- UVERBS_ID_NS_SHIFT
 
- UVERBS_LOOKUP_DESTROY
 
- UVERBS_LOOKUP_READ
 
- UVERBS_LOOKUP_WRITE
 
- UVERBS_METHOD
 
- UVERBS_METHOD_ADVISE_MR
 
- UVERBS_METHOD_AH_DESTROY
 
- UVERBS_METHOD_ATTRS
 
- UVERBS_METHOD_COUNTERS_CREATE
 
- UVERBS_METHOD_COUNTERS_DESTROY
 
- UVERBS_METHOD_COUNTERS_READ
 
- UVERBS_METHOD_CQ_CREATE
 
- UVERBS_METHOD_CQ_DESTROY
 
- UVERBS_METHOD_DM_ALLOC
 
- UVERBS_METHOD_DM_FREE
 
- UVERBS_METHOD_DM_MR_REG
 
- UVERBS_METHOD_FLOW_ACTION_DESTROY
 
- UVERBS_METHOD_FLOW_ACTION_ESP_CREATE
 
- UVERBS_METHOD_FLOW_ACTION_ESP_MODIFY
 
- UVERBS_METHOD_FLOW_DESTROY
 
- UVERBS_METHOD_INFO_HANDLES
 
- UVERBS_METHOD_INVOKE_WRITE
 
- UVERBS_METHOD_MR_DESTROY
 
- UVERBS_METHOD_MW_DESTROY
 
- UVERBS_METHOD_PD_DESTROY
 
- UVERBS_METHOD_QUERY_PORT
 
- UVERBS_METHOD_RWQ_IND_TBL_DESTROY
 
- UVERBS_METHOD_XRCD_DESTROY
 
- UVERBS_MODULE_NAME
 
- UVERBS_OBJECT
 
- UVERBS_OBJECT_AH
 
- UVERBS_OBJECT_COMP_CHANNEL
 
- UVERBS_OBJECT_COUNTERS
 
- UVERBS_OBJECT_CQ
 
- UVERBS_OBJECT_DEVICE
 
- UVERBS_OBJECT_DM
 
- UVERBS_OBJECT_FLOW
 
- UVERBS_OBJECT_FLOW_ACTION
 
- UVERBS_OBJECT_METHODS
 
- UVERBS_OBJECT_MR
 
- UVERBS_OBJECT_MW
 
- UVERBS_OBJECT_PD
 
- UVERBS_OBJECT_QP
 
- UVERBS_OBJECT_RWQ_IND_TBL
 
- UVERBS_OBJECT_SRQ
 
- UVERBS_OBJECT_WQ
 
- UVERBS_OBJECT_XRCD
 
- UVERBS_TYPE_ALLOC_FD
 
- UVERBS_TYPE_ALLOC_IDR
 
- UVERBS_TYPE_ALLOC_IDR_SZ
 
- UVERBS_UDATA_DRIVER_DATA_FLAG
 
- UVERBS_UDATA_DRIVER_DATA_NS
 
- UVESAFB_DEFAULT_MODE
 
- UVESAFB_EXACT_DEPTH
 
- UVESAFB_EXACT_RES
 
- UVESAFB_TASKS_MAX
 
- UVESAFB_TIMEOUT
 
- UVH_AGING_PRESCALE_SEL
 
- UVH_APICID
 
- UVH_BAU_DATA_BROADCAST
 
- UVH_BAU_DATA_BROADCAST_32
 
- UVH_BAU_DATA_BROADCAST_ENABLE_MASK
 
- UVH_BAU_DATA_BROADCAST_ENABLE_SHFT
 
- UVH_BAU_DATA_CONFIG
 
- UVH_BAU_DATA_CONFIG_32
 
- UVH_BAU_DATA_CONFIG_APIC_ID_MASK
 
- UVH_BAU_DATA_CONFIG_APIC_ID_SHFT
 
- UVH_BAU_DATA_CONFIG_DESTMODE_MASK
 
- UVH_BAU_DATA_CONFIG_DESTMODE_SHFT
 
- UVH_BAU_DATA_CONFIG_DM_MASK
 
- UVH_BAU_DATA_CONFIG_DM_SHFT
 
- UVH_BAU_DATA_CONFIG_M_MASK
 
- UVH_BAU_DATA_CONFIG_M_SHFT
 
- UVH_BAU_DATA_CONFIG_P_MASK
 
- UVH_BAU_DATA_CONFIG_P_SHFT
 
- UVH_BAU_DATA_CONFIG_STATUS_MASK
 
- UVH_BAU_DATA_CONFIG_STATUS_SHFT
 
- UVH_BAU_DATA_CONFIG_T_MASK
 
- UVH_BAU_DATA_CONFIG_T_SHFT
 
- UVH_BAU_DATA_CONFIG_VECTOR_MASK
 
- UVH_BAU_DATA_CONFIG_VECTOR_SHFT
 
- UVH_BIOS_KERNEL_MMR
 
- UVH_BIOS_KERNEL_MMR_ALIAS
 
- UVH_BIOS_KERNEL_MMR_ALIAS_2
 
- UVH_EVENT_OCCURRED0
 
- UVH_EVENT_OCCURRED0_32
 
- UVH_EVENT_OCCURRED0_ALIAS
 
- UVH_EVENT_OCCURRED0_ALIAS_32
 
- UVH_EVENT_OCCURRED0_ASIC_TO_L1_MASK
 
- UVH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT
 
- UVH_EVENT_OCCURRED0_BAU_DATA_MASK
 
- UVH_EVENT_OCCURRED0_BAU_DATA_SHFT
 
- UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK
 
- UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT
 
- UVH_EVENT_OCCURRED0_EXTIO_INT1_MASK
 
- UVH_EVENT_OCCURRED0_EXTIO_INT1_SHFT
 
- UVH_EVENT_OCCURRED0_EXTIO_INT2_MASK
 
- UVH_EVENT_OCCURRED0_EXTIO_INT2_SHFT
 
- UVH_EVENT_OCCURRED0_EXTIO_INT3_MASK
 
- UVH_EVENT_OCCURRED0_EXTIO_INT3_SHFT
 
- UVH_EVENT_OCCURRED0_GR0_AOERR0_MASK
 
- UVH_EVENT_OCCURRED0_GR0_AOERR0_SHFT
 
- UVH_EVENT_OCCURRED0_GR0_AOERR1_MASK
 
- UVH_EVENT_OCCURRED0_GR0_AOERR1_SHFT
 
- UVH_EVENT_OCCURRED0_GR0_HCERR_MASK
 
- UVH_EVENT_OCCURRED0_GR0_HCERR_SHFT
 
- UVH_EVENT_OCCURRED0_GR1_AOERR0_MASK
 
- UVH_EVENT_OCCURRED0_GR1_AOERR0_SHFT
 
- UVH_EVENT_OCCURRED0_GR1_AOERR1_MASK
 
- UVH_EVENT_OCCURRED0_GR1_AOERR1_SHFT
 
- UVH_EVENT_OCCURRED0_GR1_HCERR_MASK
 
- UVH_EVENT_OCCURRED0_GR1_HCERR_SHFT
 
- UVH_EVENT_OCCURRED0_IPI_INT_MASK
 
- UVH_EVENT_OCCURRED0_IPI_INT_SHFT
 
- UVH_EVENT_OCCURRED0_L1_NMI_INT_MASK
 
- UVH_EVENT_OCCURRED0_L1_NMI_INT_SHFT
 
- UVH_EVENT_OCCURRED0_L1_TO_ASIC_MASK
 
- UVH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT
 
- UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK
 
- UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT
 
- UVH_EVENT_OCCURRED0_LB_AOERR0_MASK
 
- UVH_EVENT_OCCURRED0_LB_AOERR0_SHFT
 
- UVH_EVENT_OCCURRED0_LB_AOERR1_MASK
 
- UVH_EVENT_OCCURRED0_LB_AOERR1_SHFT
 
- UVH_EVENT_OCCURRED0_LB_HCERR_MASK
 
- UVH_EVENT_OCCURRED0_LB_HCERR_SHFT
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK
 
- UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT
 
- UVH_EVENT_OCCURRED0_LH_AOERR0_MASK
 
- UVH_EVENT_OCCURRED0_LH_AOERR0_SHFT
 
- UVH_EVENT_OCCURRED0_LH_AOERR1_MASK
 
- UVH_EVENT_OCCURRED0_LH_AOERR1_SHFT
 
- UVH_EVENT_OCCURRED0_LH_HCERR_MASK
 
- UVH_EVENT_OCCURRED0_LH_HCERR_SHFT
 
- UVH_EVENT_OCCURRED0_LTC_INT_MASK
 
- UVH_EVENT_OCCURRED0_LTC_INT_SHFT
 
- UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK
 
- UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT
 
- UVH_EVENT_OCCURRED0_PROFILE_INT_MASK
 
- UVH_EVENT_OCCURRED0_PROFILE_INT_SHFT
 
- UVH_EVENT_OCCURRED0_RH_AOERR0_MASK
 
- UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT
 
- UVH_EVENT_OCCURRED0_RH_AOERR1_MASK
 
- UVH_EVENT_OCCURRED0_RH_AOERR1_SHFT
 
- UVH_EVENT_OCCURRED0_RH_HCERR_MASK
 
- UVH_EVENT_OCCURRED0_RH_HCERR_SHFT
 
- UVH_EVENT_OCCURRED0_RH_VPI_INT_MASK
 
- UVH_EVENT_OCCURRED0_RH_VPI_INT_SHFT
 
- UVH_EVENT_OCCURRED0_RTC0_MASK
 
- UVH_EVENT_OCCURRED0_RTC0_SHFT
 
- UVH_EVENT_OCCURRED0_RTC1_MASK
 
- UVH_EVENT_OCCURRED0_RTC1_SHFT
 
- UVH_EVENT_OCCURRED0_RTC2_MASK
 
- UVH_EVENT_OCCURRED0_RTC2_SHFT
 
- UVH_EVENT_OCCURRED0_RTC3_MASK
 
- UVH_EVENT_OCCURRED0_RTC3_SHFT
 
- UVH_EVENT_OCCURRED0_SI_AOERR0_MASK
 
- UVH_EVENT_OCCURRED0_SI_AOERR0_SHFT
 
- UVH_EVENT_OCCURRED0_SI_AOERR1_MASK
 
- UVH_EVENT_OCCURRED0_SI_AOERR1_SHFT
 
- UVH_EVENT_OCCURRED0_SI_HCERR_MASK
 
- UVH_EVENT_OCCURRED0_SI_HCERR_SHFT
 
- UVH_EVENT_OCCURRED0_STOP_CLOCK_MASK
 
- UVH_EVENT_OCCURRED0_STOP_CLOCK_SHFT
 
- UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK
 
- UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT
 
- UVH_EVENT_OCCURRED0_XN_AOERR0_MASK
 
- UVH_EVENT_OCCURRED0_XN_AOERR0_SHFT
 
- UVH_EVENT_OCCURRED0_XN_AOERR1_MASK
 
- UVH_EVENT_OCCURRED0_XN_AOERR1_SHFT
 
- UVH_EVENT_OCCURRED0_XN_HCERR_MASK
 
- UVH_EVENT_OCCURRED0_XN_HCERR_SHFT
 
- UVH_EVENT_OCCURRED2_32
 
- UVH_EVENT_OCCURRED2_ALIAS_32
 
- UVH_EXTIO_INT0_BROADCAST
 
- UVH_EXTIO_INT0_BROADCAST_32
 
- UVH_EXTIO_INT0_BROADCAST_ENABLE_MASK
 
- UVH_EXTIO_INT0_BROADCAST_ENABLE_SHFT
 
- UVH_GR0_TLB_INT0_CONFIG
 
- UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK
 
- UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT
 
- UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK
 
- UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT
 
- UVH_GR0_TLB_INT0_CONFIG_DM_MASK
 
- UVH_GR0_TLB_INT0_CONFIG_DM_SHFT
 
- UVH_GR0_TLB_INT0_CONFIG_M_MASK
 
- UVH_GR0_TLB_INT0_CONFIG_M_SHFT
 
- UVH_GR0_TLB_INT0_CONFIG_P_MASK
 
- UVH_GR0_TLB_INT0_CONFIG_P_SHFT
 
- UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK
 
- UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT
 
- UVH_GR0_TLB_INT0_CONFIG_T_MASK
 
- UVH_GR0_TLB_INT0_CONFIG_T_SHFT
 
- UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK
 
- UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT
 
- UVH_GR0_TLB_INT1_CONFIG
 
- UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK
 
- UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT
 
- UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK
 
- UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT
 
- UVH_GR0_TLB_INT1_CONFIG_DM_MASK
 
- UVH_GR0_TLB_INT1_CONFIG_DM_SHFT
 
- UVH_GR0_TLB_INT1_CONFIG_M_MASK
 
- UVH_GR0_TLB_INT1_CONFIG_M_SHFT
 
- UVH_GR0_TLB_INT1_CONFIG_P_MASK
 
- UVH_GR0_TLB_INT1_CONFIG_P_SHFT
 
- UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK
 
- UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT
 
- UVH_GR0_TLB_INT1_CONFIG_T_MASK
 
- UVH_GR0_TLB_INT1_CONFIG_T_SHFT
 
- UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK
 
- UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT
 
- UVH_GR0_TLB_MMR_CONTROL
 
- UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK
 
- UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT
 
- UVH_GR0_TLB_MMR_CONTROL_INDEX_MASK
 
- UVH_GR0_TLB_MMR_CONTROL_INDEX_SHFT
 
- UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK
 
- UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT
 
- UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK
 
- UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT
 
- UVH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK
 
- UVH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT
 
- UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK
 
- UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT
 
- UVH_GR0_TLB_MMR_READ_DATA_HI
 
- UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT
 
- UVH_GR0_TLB_MMR_READ_DATA_LO
 
- UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK
 
- UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT
 
- UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK
 
- UVH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT
 
- UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK
 
- UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT
 
- UVH_GR1_TLB_INT0_CONFIG
 
- UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK
 
- UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT
 
- UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK
 
- UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT
 
- UVH_GR1_TLB_INT0_CONFIG_DM_MASK
 
- UVH_GR1_TLB_INT0_CONFIG_DM_SHFT
 
- UVH_GR1_TLB_INT0_CONFIG_M_MASK
 
- UVH_GR1_TLB_INT0_CONFIG_M_SHFT
 
- UVH_GR1_TLB_INT0_CONFIG_P_MASK
 
- UVH_GR1_TLB_INT0_CONFIG_P_SHFT
 
- UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK
 
- UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT
 
- UVH_GR1_TLB_INT0_CONFIG_T_MASK
 
- UVH_GR1_TLB_INT0_CONFIG_T_SHFT
 
- UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK
 
- UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT
 
- UVH_GR1_TLB_INT1_CONFIG
 
- UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK
 
- UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT
 
- UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK
 
- UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT
 
- UVH_GR1_TLB_INT1_CONFIG_DM_MASK
 
- UVH_GR1_TLB_INT1_CONFIG_DM_SHFT
 
- UVH_GR1_TLB_INT1_CONFIG_M_MASK
 
- UVH_GR1_TLB_INT1_CONFIG_M_SHFT
 
- UVH_GR1_TLB_INT1_CONFIG_P_MASK
 
- UVH_GR1_TLB_INT1_CONFIG_P_SHFT
 
- UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK
 
- UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT
 
- UVH_GR1_TLB_INT1_CONFIG_T_MASK
 
- UVH_GR1_TLB_INT1_CONFIG_T_SHFT
 
- UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK
 
- UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT
 
- UVH_GR1_TLB_MMR_CONTROL
 
- UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK
 
- UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT
 
- UVH_GR1_TLB_MMR_CONTROL_INDEX_SHFT
 
- UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK
 
- UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT
 
- UVH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK
 
- UVH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT
 
- UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK
 
- UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT
 
- UVH_GR1_TLB_MMR_READ_DATA_HI
 
- UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT
 
- UVH_GR1_TLB_MMR_READ_DATA_LO
 
- UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK
 
- UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT
 
- UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK
 
- UVH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT
 
- UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK
 
- UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT
 
- UVH_INT_CMPB
 
- UVH_INT_CMPB_REAL_TIME_CMPB_MASK
 
- UVH_INT_CMPB_REAL_TIME_CMPB_SHFT
 
- UVH_INT_CMPC
 
- UVH_INT_CMPC_REAL_TIME_CMPC_MASK
 
- UVH_INT_CMPC_REAL_TIME_CMPC_SHFT
 
- UVH_INT_CMPD
 
- UVH_INT_CMPD_REAL_TIME_CMPD_MASK
 
- UVH_INT_CMPD_REAL_TIME_CMPD_SHFT
 
- UVH_IPI_INT
 
- UVH_IPI_INT_32
 
- UVH_IPI_INT_APIC_ID_MASK
 
- UVH_IPI_INT_APIC_ID_SHFT
 
- UVH_IPI_INT_DELIVERY_MODE_MASK
 
- UVH_IPI_INT_DELIVERY_MODE_SHFT
 
- UVH_IPI_INT_DESTMODE_MASK
 
- UVH_IPI_INT_DESTMODE_SHFT
 
- UVH_IPI_INT_SEND_MASK
 
- UVH_IPI_INT_SEND_SHFT
 
- UVH_IPI_INT_VECTOR_MASK
 
- UVH_IPI_INT_VECTOR_SHFT
 
- UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST
 
- UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32
 
- UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST
 
- UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32
 
- UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL
 
- UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32
 
- UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE
 
- UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32
 
- UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS
 
- UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32
 
- UVH_LB_BAU_MISC_CONTROL
 
- UVH_LB_BAU_MISC_CONTROL_32
 
- UVH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK
 
- UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT
 
- UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK
 
- UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT
 
- UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK
 
- UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT
 
- UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK
 
- UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT
 
- UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK
 
- UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT
 
- UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK
 
- UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT
 
- UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK
 
- UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT
 
- UVH_LB_BAU_MISC_CONTROL_FUN_MASK
 
- UVH_LB_BAU_MISC_CONTROL_FUN_SHFT
 
- UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK
 
- UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
 
- UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK
 
- UVH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT
 
- UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK
 
- UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT
 
- UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK
 
- UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT
 
- UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK
 
- UVH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT
 
- UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK
 
- UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT
 
- UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK
 
- UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT
 
- UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK
 
- UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT
 
- UVH_LB_BAU_SB_ACTIVATION_CONTROL
 
- UVH_LB_BAU_SB_ACTIVATION_CONTROL_32
 
- UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK
 
- UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT
 
- UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK
 
- UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_SHFT
 
- UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK
 
- UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT
 
- UVH_LB_BAU_SB_ACTIVATION_STATUS_0
 
- UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32
 
- UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK
 
- UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT
 
- UVH_LB_BAU_SB_ACTIVATION_STATUS_1
 
- UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32
 
- UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK
 
- UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT
 
- UVH_LB_BAU_SB_ACTIVATION_STATUS_2
 
- UVH_LB_BAU_SB_ACTIVATION_STATUS_2_32
 
- UVH_LB_BAU_SB_DESCRIPTOR_BASE
 
- UVH_LB_BAU_SB_DESCRIPTOR_BASE_32
 
- UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK
 
- UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT
 
- UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT
 
- UVH_LB_BAU_SB_DESCRIPTOR_PAGE_ADDRESS_MASK
 
- UVH_NMI_MMR
 
- UVH_NMI_MMRX
 
- UVH_NMI_MMRX_CLEAR
 
- UVH_NMI_MMRX_REQ
 
- UVH_NMI_MMRX_REQ_SHIFT
 
- UVH_NMI_MMRX_SHIFT
 
- UVH_NMI_MMRX_SUPPORTED
 
- UVH_NMI_MMRX_TYPE
 
- UVH_NMI_MMR_CLEAR
 
- UVH_NMI_MMR_SHIFT
 
- UVH_NMI_MMR_TYPE
 
- UVH_NODE_ID
 
- UVH_NODE_ID_FORCE1_MASK
 
- UVH_NODE_ID_FORCE1_SHFT
 
- UVH_NODE_ID_MANUFACTURER_MASK
 
- UVH_NODE_ID_MANUFACTURER_SHFT
 
- UVH_NODE_ID_NI_PORT_MASK
 
- UVH_NODE_ID_NI_PORT_SHFT
 
- UVH_NODE_ID_NODES_PER_BIT_MASK
 
- UVH_NODE_ID_NODES_PER_BIT_SHFT
 
- UVH_NODE_ID_NODE_ID_MASK
 
- UVH_NODE_ID_NODE_ID_SHFT
 
- UVH_NODE_ID_PART_NUMBER_MASK
 
- UVH_NODE_ID_PART_NUMBER_SHFT
 
- UVH_NODE_ID_REVISION_MASK
 
- UVH_NODE_ID_REVISION_SHFT
 
- UVH_NODE_PRESENT_TABLE
 
- UVH_NODE_PRESENT_TABLE_DEPTH
 
- UVH_NODE_PRESENT_TABLE_NODES_MASK
 
- UVH_NODE_PRESENT_TABLE_NODES_SHFT
 
- UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR
 
- UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK
 
- UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT
 
- UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK
 
- UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT
 
- UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK
 
- UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT
 
- UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR
 
- UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK
 
- UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT
 
- UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK
 
- UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT
 
- UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK
 
- UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT
 
- UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR
 
- UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK
 
- UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT
 
- UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK
 
- UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT
 
- UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK
 
- UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT
 
- UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR
 
- UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK
 
- UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 
- UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR
 
- UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK
 
- UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT
 
- UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR
 
- UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK
 
- UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT
 
- UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH
 
- UVH_RH_GAM_CONFIG_MMR
 
- UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK
 
- UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT
 
- UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR
 
- UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK
 
- UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT
 
- UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK
 
- UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT
 
- UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK
 
- UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT
 
- UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK
 
- UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT
 
- UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR
 
- UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_MASK
 
- UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_ENABLE_MASK
 
- UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_MASK
 
- UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_M_IO_SHFT
 
- UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR
 
- UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_BASE_MASK
 
- UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_MASK
 
- UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR_M_IO_SHFT
 
- UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR
 
- UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR
 
- UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH
 
- UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_NASID_MASK
 
- UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR
 
- UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_DEPTH
 
- UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR_NASID_MASK
 
- UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR
 
- UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK
 
- UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT
 
- UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK
 
- UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT
 
- UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK
 
- UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT
 
- UVH_RTC
 
- UVH_RTC1_INT_CONFIG
 
- UVH_RTC1_INT_CONFIG_APIC_ID_MASK
 
- UVH_RTC1_INT_CONFIG_APIC_ID_SHFT
 
- UVH_RTC1_INT_CONFIG_DESTMODE_MASK
 
- UVH_RTC1_INT_CONFIG_DESTMODE_SHFT
 
- UVH_RTC1_INT_CONFIG_DM_MASK
 
- UVH_RTC1_INT_CONFIG_DM_SHFT
 
- UVH_RTC1_INT_CONFIG_M_MASK
 
- UVH_RTC1_INT_CONFIG_M_SHFT
 
- UVH_RTC1_INT_CONFIG_P_MASK
 
- UVH_RTC1_INT_CONFIG_P_SHFT
 
- UVH_RTC1_INT_CONFIG_STATUS_MASK
 
- UVH_RTC1_INT_CONFIG_STATUS_SHFT
 
- UVH_RTC1_INT_CONFIG_T_MASK
 
- UVH_RTC1_INT_CONFIG_T_SHFT
 
- UVH_RTC1_INT_CONFIG_VECTOR_MASK
 
- UVH_RTC1_INT_CONFIG_VECTOR_SHFT
 
- UVH_RTC2_INT_CONFIG
 
- UVH_RTC2_INT_CONFIG_APIC_ID_MASK
 
- UVH_RTC2_INT_CONFIG_APIC_ID_SHFT
 
- UVH_RTC2_INT_CONFIG_DESTMODE_MASK
 
- UVH_RTC2_INT_CONFIG_DESTMODE_SHFT
 
- UVH_RTC2_INT_CONFIG_DM_MASK
 
- UVH_RTC2_INT_CONFIG_DM_SHFT
 
- UVH_RTC2_INT_CONFIG_M_MASK
 
- UVH_RTC2_INT_CONFIG_M_SHFT
 
- UVH_RTC2_INT_CONFIG_P_MASK
 
- UVH_RTC2_INT_CONFIG_P_SHFT
 
- UVH_RTC2_INT_CONFIG_STATUS_MASK
 
- UVH_RTC2_INT_CONFIG_STATUS_SHFT
 
- UVH_RTC2_INT_CONFIG_T_MASK
 
- UVH_RTC2_INT_CONFIG_T_SHFT
 
- UVH_RTC2_INT_CONFIG_VECTOR_MASK
 
- UVH_RTC2_INT_CONFIG_VECTOR_SHFT
 
- UVH_RTC3_INT_CONFIG
 
- UVH_RTC3_INT_CONFIG_APIC_ID_MASK
 
- UVH_RTC3_INT_CONFIG_APIC_ID_SHFT
 
- UVH_RTC3_INT_CONFIG_DESTMODE_MASK
 
- UVH_RTC3_INT_CONFIG_DESTMODE_SHFT
 
- UVH_RTC3_INT_CONFIG_DM_MASK
 
- UVH_RTC3_INT_CONFIG_DM_SHFT
 
- UVH_RTC3_INT_CONFIG_M_MASK
 
- UVH_RTC3_INT_CONFIG_M_SHFT
 
- UVH_RTC3_INT_CONFIG_P_MASK
 
- UVH_RTC3_INT_CONFIG_P_SHFT
 
- UVH_RTC3_INT_CONFIG_STATUS_MASK
 
- UVH_RTC3_INT_CONFIG_STATUS_SHFT
 
- UVH_RTC3_INT_CONFIG_T_MASK
 
- UVH_RTC3_INT_CONFIG_T_SHFT
 
- UVH_RTC3_INT_CONFIG_VECTOR_MASK
 
- UVH_RTC3_INT_CONFIG_VECTOR_SHFT
 
- UVH_RTC_INC_RATIO
 
- UVH_RTC_INC_RATIO_FRACTION_MASK
 
- UVH_RTC_INC_RATIO_FRACTION_SHFT
 
- UVH_RTC_INC_RATIO_RATIO_MASK
 
- UVH_RTC_INC_RATIO_RATIO_SHFT
 
- UVH_RTC_REAL_TIME_CLOCK_MASK
 
- UVH_RTC_REAL_TIME_CLOCK_SHFT
 
- UVH_SCRATCH5
 
- UVH_SCRATCH5_32
 
- UVH_SCRATCH5_ALIAS
 
- UVH_SCRATCH5_ALIAS_2
 
- UVH_SCRATCH5_ALIAS_2_32
 
- UVH_SCRATCH5_ALIAS_32
 
- UVH_SCRATCH5_SCRATCH5_MASK
 
- UVH_SCRATCH5_SCRATCH5_SHFT
 
- UVH_SI_ADDR_MAP_CONFIG
 
- UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK
 
- UVH_SI_ADDR_MAP_CONFIG_M_SKT_SHFT
 
- UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK
 
- UVH_SI_ADDR_MAP_CONFIG_N_SKT_SHFT
 
- UVH_SI_ALIAS0_OVERLAY_CONFIG
 
- UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK
 
- UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT
 
- UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK
 
- UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT
 
- UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK
 
- UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT
 
- UVH_SI_ALIAS1_OVERLAY_CONFIG
 
- UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK
 
- UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT
 
- UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK
 
- UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT
 
- UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK
 
- UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT
 
- UVH_SI_ALIAS2_OVERLAY_CONFIG
 
- UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK
 
- UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT
 
- UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK
 
- UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT
 
- UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK
 
- UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT
 
- UVH_TRANSACTION_TIMEOUT
 
- UVH_TSC_SYNC_INVALID
 
- UVH_TSC_SYNC_MASK
 
- UVH_TSC_SYNC_MMR
 
- UVH_TSC_SYNC_SHIFT
 
- UVH_TSC_SYNC_SHIFT_UV2K
 
- UVH_TSC_SYNC_VALID
 
- UVIS25_I2C_AUTO_INCREMENT
 
- UVIS25_SENSORS_SPI_READ
 
- UVIS25_SPI_AUTO_INCREMENT
 
- UVLO_EN_MASK
 
- UVLO_EN_SHIFT
 
- UVMF_ALL
 
- UVMF_FLUSHTYPE_MASK
 
- UVMF_INVLPG
 
- UVMF_LOCAL
 
- UVMF_MULTI
 
- UVMF_NONE
 
- UVMF_TLB_FLUSH
 
- UVSCALE
 
- UVSCC
 
- UVXH_EVENT_OCCURRED0_GR0_AOERR0_MASK
 
- UVXH_EVENT_OCCURRED0_GR0_AOERR0_SHFT
 
- UVXH_EVENT_OCCURRED0_GR0_HCERR_MASK
 
- UVXH_EVENT_OCCURRED0_GR0_HCERR_SHFT
 
- UVXH_EVENT_OCCURRED0_GR1_AOERR0_MASK
 
- UVXH_EVENT_OCCURRED0_GR1_AOERR0_SHFT
 
- UVXH_EVENT_OCCURRED0_GR1_HCERR_MASK
 
- UVXH_EVENT_OCCURRED0_GR1_HCERR_SHFT
 
- UVXH_EVENT_OCCURRED0_LB_AOERR0_MASK
 
- UVXH_EVENT_OCCURRED0_LB_AOERR0_SHFT
 
- UVXH_EVENT_OCCURRED0_LH0_AOERR0_MASK
 
- UVXH_EVENT_OCCURRED0_LH0_AOERR0_SHFT
 
- UVXH_EVENT_OCCURRED0_LH0_HCERR_MASK
 
- UVXH_EVENT_OCCURRED0_LH0_HCERR_SHFT
 
- UVXH_EVENT_OCCURRED0_LH1_AOERR0_MASK
 
- UVXH_EVENT_OCCURRED0_LH1_AOERR0_SHFT
 
- UVXH_EVENT_OCCURRED0_LH1_HCERR_MASK
 
- UVXH_EVENT_OCCURRED0_LH1_HCERR_SHFT
 
- UVXH_EVENT_OCCURRED0_NI0_HCERR_MASK
 
- UVXH_EVENT_OCCURRED0_NI0_HCERR_SHFT
 
- UVXH_EVENT_OCCURRED0_NI1_HCERR_MASK
 
- UVXH_EVENT_OCCURRED0_NI1_HCERR_SHFT
 
- UVXH_EVENT_OCCURRED0_RH_HCERR_MASK
 
- UVXH_EVENT_OCCURRED0_RH_HCERR_SHFT
 
- UVXH_EVENT_OCCURRED0_XB_AOERR0_MASK
 
- UVXH_EVENT_OCCURRED0_XB_AOERR0_SHFT
 
- UVXH_EVENT_OCCURRED2
 
- UVXH_EVENT_OCCURRED2_ALIAS
 
- UVXH_EVENT_OCCURRED2_RTC_1_MASK
 
- UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK
 
- UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT
 
- UVXH_GR0_TLB_MMR_CONTROL_INDEX_SHFT
 
- UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK
 
- UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT
 
- UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK
 
- UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT
 
- UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_MASK
 
- UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT
 
- UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK
 
- UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT
 
- UVXH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT
 
- UVXH_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK
 
- UVXH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT
 
- UVXH_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK
 
- UVXH_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT
 
- UVXH_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK
 
- UVXH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT
 
- UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK
 
- UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT
 
- UVXH_GR1_TLB_MMR_CONTROL_INDEX_SHFT
 
- UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK
 
- UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT
 
- UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK
 
- UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT
 
- UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_MASK
 
- UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT
 
- UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK
 
- UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT
 
- UVXH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT
 
- UVXH_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK
 
- UVXH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT
 
- UVXH_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK
 
- UVXH_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT
 
- UVXH_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK
 
- UVXH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT
 
- UVXH_INT_CMPC_REAL_TIME_CMP_2_MASK
 
- UVXH_INT_CMPC_REAL_TIME_CMP_2_SHFT
 
- UVXH_INT_CMPD_REAL_TIME_CMP_3_MASK
 
- UVXH_INT_CMPD_REAL_TIME_CMP_3_SHFT
 
- UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_MASK
 
- UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT
 
- UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK
 
- UVXH_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT
 
- UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK
 
- UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT
 
- UVXH_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK
 
- UVXH_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT
 
- UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK
 
- UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT
 
- UVXH_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK
 
- UVXH_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
 
- UVXH_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK
 
- UVXH_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT
 
- UVXH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK
 
- UVXH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT
 
- UVXH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK
 
- UVXH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT
 
- UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK
 
- UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT
 
- UVXH_LB_BAU_MISC_CONTROL_FUN_MASK
 
- UVXH_LB_BAU_MISC_CONTROL_FUN_SHFT
 
- UVXH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK
 
- UVXH_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT
 
- UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK
 
- UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT
 
- UVXH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK
 
- UVXH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT
 
- UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK
 
- UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT
 
- UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK
 
- UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT
 
- UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK
 
- UVXH_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT
 
- UVXH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK
 
- UVXH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT
 
- UVXH_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK
 
- UVXH_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT
 
- UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK
 
- UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT
 
- UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK
 
- UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT
 
- UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK
 
- UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT
 
- UVXH_NODE_ID_FORCE1_MASK
 
- UVXH_NODE_ID_FORCE1_SHFT
 
- UVXH_NODE_ID_MANUFACTURER_MASK
 
- UVXH_NODE_ID_MANUFACTURER_SHFT
 
- UVXH_NODE_ID_NI_PORT_MASK
 
- UVXH_NODE_ID_NI_PORT_SHFT
 
- UVXH_NODE_ID_NODES_PER_BIT_MASK
 
- UVXH_NODE_ID_NODES_PER_BIT_SHFT
 
- UVXH_NODE_ID_NODE_ID_MASK
 
- UVXH_NODE_ID_NODE_ID_SHFT
 
- UVXH_NODE_ID_PART_NUMBER_MASK
 
- UVXH_NODE_ID_PART_NUMBER_SHFT
 
- UVXH_NODE_ID_REVISION_MASK
 
- UVXH_NODE_ID_REVISION_SHFT
 
- UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_MASK
 
- UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT
 
- UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK
 
- UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_SHFT
 
- UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK
 
- UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT
 
- UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_MASK
 
- UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT
 
- UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK
 
- UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_SHFT
 
- UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK
 
- UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT
 
- UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_MASK
 
- UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT
 
- UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK
 
- UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_SHFT
 
- UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK
 
- UVXH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT
 
- UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK
 
- UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 
- UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK
 
- UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT
 
- UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK
 
- UVXH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT
 
- UVXH_RH_GAM_CONFIG_MMR_N_SKT_MASK
 
- UVXH_RH_GAM_CONFIG_MMR_N_SKT_SHFT
 
- UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK
 
- UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT
 
- UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK
 
- UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT
 
- UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK
 
- UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT
 
- UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK
 
- UVXH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT
 
- UV_ACTRL
 
- UV_ACT_STATUS_MASK
 
- UV_ACT_STATUS_SIZE
 
- UV_AFFINITY_ALL
 
- UV_AFFINITY_CPU
 
- UV_AFFINITY_NODE
 
- UV_APICID_HIBIT_MASK
 
- UV_APIC_PNODE_SHIFT
 
- UV_BAU_BASENAME
 
- UV_BAU_MESSAGE
 
- UV_BAU_TUNABLES_DIR
 
- UV_BAU_TUNABLES_FILE
 
- UV_BAU_V1
 
- UV_BAU_V2
 
- UV_BAU_V3
 
- UV_BAU_V4
 
- UV_BIOS_COMMON
 
- UV_BIOS_FREQ_BASE
 
- UV_BIOS_GET_PARTITION_ADDR
 
- UV_BIOS_GET_SN_INFO
 
- UV_BIOS_MEMPROTECT
 
- UV_BIOS_SET_LEGACY_VGA_TARGET
 
- UV_BIOS_WATCHLIST_ALLOC
 
- UV_BIOS_WATCHLIST_FREE
 
- UV_CPUS_PER_AS
 
- UV_DISTRIBUTION_SIZE
 
- UV_ESM
 
- UV_GAM_RANGE_SHFT
 
- UV_GAM_RANGE_TYPE_HOLE
 
- UV_GAM_RANGE_TYPE_MAX
 
- UV_GAM_RANGE_TYPE_NVRAM
 
- UV_GAM_RANGE_TYPE_NV_MAILBOX
 
- UV_GAM_RANGE_TYPE_NV_WINDOW
 
- UV_GAM_RANGE_TYPE_RAM
 
- UV_GAM_RANGE_TYPE_UNUSED
 
- UV_GLOBAL_GRU_MMR_BASE
 
- UV_GLOBAL_MMR32_BASE
 
- UV_GLOBAL_MMR32_PNODE_BITS
 
- UV_GLOBAL_MMR32_PNODE_SHIFT
 
- UV_GLOBAL_MMR32_SIZE
 
- UV_GLOBAL_MMR64_BASE
 
- UV_GLOBAL_MMR64_PNODE_BITS
 
- UV_GLOBAL_MMR64_PNODE_SHIFT
 
- UV_HUB_INFO_VERSION
 
- UV_INTD_SOFT_ACK_TIMEOUT_PERIOD
 
- UV_LB_SUBNODEID
 
- UV_LEGACY_APIC
 
- UV_LOCAL_MMR_BASE
 
- UV_LOCAL_MMR_SIZE
 
- UV_LPF_HIGH_BANDPASS
 
- UV_LPF_LOW_BANDPASS
 
- UV_LPF_MEDIUM_BANDPASS
 
- UV_MASK
 
- UV_MAX_INT_CORES
 
- UV_MAX_NASID_VALUE
 
- UV_MAX_NUMALINK_BLADES
 
- UV_MAX_SSI_BLADES
 
- UV_MEMPROT_ALLOW_AMO
 
- UV_MEMPROT_ALLOW_RW
 
- UV_MEMPROT_RESTRICT_ACCESS
 
- UV_MMR_ENABLE
 
- UV_MMTIMER_DESC
 
- UV_MMTIMER_NAME
 
- UV_MMTIMER_VERSION
 
- UV_NASID_TO_PNODE
 
- UV_NET_ENDPOINT_INTD
 
- UV_NMI_STATE_DUMP
 
- UV_NMI_STATE_DUMP_DONE
 
- UV_NMI_STATE_IN
 
- UV_NMI_STATE_OUT
 
- UV_NONE
 
- UV_NON_UNIQUE_APIC
 
- UV_OFF
 
- UV_OFFSET
 
- UV_ON
 
- UV_ON_OFF
 
- UV_PAYLOADQ_GNODE_SHIFT
 
- UV_PNODE_TO_GNODE
 
- UV_PNODE_TO_NASID
 
- UV_PTC_BASENAME
 
- UV_QUANTABLE
 
- UV_RETURN
 
- UV_SA_MASK
 
- UV_SA_SHFT
 
- UV_SHARE_PAGE
 
- UV_SWAP
 
- UV_SW_ACK_NPENDING
 
- UV_SYSTAB_SIG
 
- UV_SYSTAB_TYPE_GAM_PARAMS
 
- UV_SYSTAB_TYPE_GAM_RNG_TBL
 
- UV_SYSTAB_TYPE_MAX
 
- UV_SYSTAB_TYPE_UNUSED
 
- UV_SYSTAB_VERSION_1
 
- UV_SYSTAB_VERSION_UV4
 
- UV_SYSTAB_VERSION_UV4_1
 
- UV_SYSTAB_VERSION_UV4_2
 
- UV_SYSTAB_VERSION_UV4_3
 
- UV_SYSTAB_VERSION_UV4_LATEST
 
- UV_SYSTEM_TABLE_GUID
 
- UV_UNSHARE_ALL_PAGES
 
- UV_UNSHARE_PAGE
 
- UV_VPH
 
- UV_WRITE_PATE
 
- UV_X2APIC
 
- UW
 
- UW2451_RF
 
- UW2453_INTR_REG
 
- UW2453_PRIV
 
- UW2453_REGWRITE
 
- UW2453_RF
 
- UWBCAPDATA
 
- UWBCAPDATA_SIZE
 
- UWBCAPDATA_TO_BAR
 
- UWBCAPDATA_TO_CAP_ID
 
- UWBCAPDATA_TO_OFFSET
 
- UWBCAPDATA_TO_SIZE
 
- UWBCAPDATA_TO_VERSION
 
- UWBCAPINFO
 
- UWBCAPINFO_TO_N_CAPS
 
- UWB_ACK_B
 
- UWB_ACK_B_REQ
 
- UWB_ACK_INM
 
- UWB_ACK_NO
 
- UWB_ADDR_DEV
 
- UWB_ADDR_MAC
 
- UWB_ADDR_STRSIZE
 
- UWB_APP_SPEC_IE
 
- UWB_APP_SPEC_PROBE_IE
 
- UWB_BEACON_SLOT_LENGTH_US
 
- UWB_BP_SWITCH_IE
 
- UWB_DBG_CMD_IE_ADD
 
- UWB_DBG_CMD_IE_RM
 
- UWB_DBG_CMD_RADIO_START
 
- UWB_DBG_CMD_RADIO_STOP
 
- UWB_DBG_CMD_RSV_ESTABLISH
 
- UWB_DBG_CMD_RSV_TERMINATE
 
- UWB_DEV_INFO_NAME
 
- UWB_DEV_INFO_VENDOR_ID
 
- UWB_DEV_INFO_VENDOR_TYPE
 
- UWB_DRP_BACKOFF_WIN_MAX
 
- UWB_DRP_BACKOFF_WIN_MIN
 
- UWB_DRP_CONFLICT_ACT1
 
- UWB_DRP_CONFLICT_ACT2
 
- UWB_DRP_CONFLICT_ACT3
 
- UWB_DRP_CONFLICT_MANTAIN
 
- UWB_DRP_NOTIF_CONFLICT
 
- UWB_DRP_NOTIF_DRP_IE_RCVD
 
- UWB_DRP_NOTIF_TERMINATE
 
- UWB_DRP_REASON_ACCEPTED
 
- UWB_DRP_REASON_CONFLICT
 
- UWB_DRP_REASON_DENIED
 
- UWB_DRP_REASON_MODIFIED
 
- UWB_DRP_REASON_PENDING
 
- UWB_DRP_TYPE_ALIEN_BP
 
- UWB_DRP_TYPE_HARD
 
- UWB_DRP_TYPE_PCA
 
- UWB_DRP_TYPE_PRIVATE
 
- UWB_DRP_TYPE_SOFT
 
- UWB_EST_16
 
- UWB_EST_8
 
- UWB_EVT_MSG_RESET
 
- UWB_EVT_TYPE_MSG
 
- UWB_EVT_TYPE_NOTIF
 
- UWB_IDENTIFICATION_IE
 
- UWB_IE_DRP
 
- UWB_IE_DRP_AVAILABILITY
 
- UWB_IE_WLP
 
- UWB_MAC_CAPABILITIES_IE
 
- UWB_MASTER_KEY_ID_IE
 
- UWB_MAS_LENGTH_US
 
- UWB_MAS_PER_ZONE
 
- UWB_MAX_LOST_BEACONS
 
- UWB_NOTIF_OFFAIR
 
- UWB_NOTIF_ONAIR
 
- UWB_NUM_GLOBAL_STREAMS
 
- UWB_NUM_MAS
 
- UWB_NUM_STREAMS
 
- UWB_NUM_ZONES
 
- UWB_PCA_AVAILABILITY
 
- UWB_PHY_CAPABILITIES_IE
 
- UWB_PHY_RATE_106
 
- UWB_PHY_RATE_160
 
- UWB_PHY_RATE_200
 
- UWB_PHY_RATE_320
 
- UWB_PHY_RATE_400
 
- UWB_PHY_RATE_480
 
- UWB_PHY_RATE_53
 
- UWB_PHY_RATE_80
 
- UWB_PHY_RATE_INVALID
 
- UWB_PRID_WLP
 
- UWB_PRID_WLP_RESERVED
 
- UWB_PRID_WUSB
 
- UWB_PRID_WUSB_BOT
 
- UWB_PRID_WUSB_TOP
 
- UWB_RC_BEACON_TYPE_NEIGHBOR
 
- UWB_RC_BEACON_TYPE_NOL_ALIEN
 
- UWB_RC_BEACON_TYPE_OL_ALIEN
 
- UWB_RC_BEACON_TYPE_SCAN
 
- UWB_RC_CET_EX_TYPE_1
 
- UWB_RC_CET_GENERAL
 
- UWB_RC_CMD_BP_MERGE
 
- UWB_RC_CMD_CHANNEL_CHANGE
 
- UWB_RC_CMD_DEV_ADDR_MGMT
 
- UWB_RC_CMD_GET_IE
 
- UWB_RC_CMD_RESET
 
- UWB_RC_CMD_SCAN
 
- UWB_RC_CMD_SEND_COMMAND_FRAME
 
- UWB_RC_CMD_SET_ASIE_NOTIF
 
- UWB_RC_CMD_SET_BEACON_FILTER
 
- UWB_RC_CMD_SET_DRP_IE
 
- UWB_RC_CMD_SET_IE
 
- UWB_RC_CMD_SET_NOTIFICATION_FILTER
 
- UWB_RC_CMD_SET_TX_POWER
 
- UWB_RC_CMD_SLEEP
 
- UWB_RC_CMD_START_BEACON
 
- UWB_RC_CMD_STOP_BEACON
 
- UWB_RC_CMD_TIMEOUT_MS
 
- UWB_RC_CTX_MAX
 
- UWB_RC_DAA_ENERGY_DETECTED
 
- UWB_RC_EVT_BEACON
 
- UWB_RC_EVT_BEACON_SIZE
 
- UWB_RC_EVT_BPOIE_CHANGE
 
- UWB_RC_EVT_BP_SLOT_CHANGE
 
- UWB_RC_EVT_BP_SWITCH_IE_RCV
 
- UWB_RC_EVT_BP_SWITCH_STATUS
 
- UWB_RC_EVT_CHANNEL_CHANGE_IE_RCV
 
- UWB_RC_EVT_CMD_FRAME_RCV
 
- UWB_RC_EVT_DEV_ADDR_CONFLICT
 
- UWB_RC_EVT_DRP
 
- UWB_RC_EVT_DRP_AVAIL
 
- UWB_RC_EVT_IE_RCV
 
- UWB_RC_EVT_UNKNOWN_CMD_RCV
 
- UWB_RC_RES_FAIL
 
- UWB_RC_RES_FAIL_ACK_NOT_RECEIVED
 
- UWB_RC_RES_FAIL_BEACON_SIZE_EXCEEDED
 
- UWB_RC_RES_FAIL_BEACON_TOO_LARGE
 
- UWB_RC_RES_FAIL_CANCELLED
 
- UWB_RC_RES_FAIL_HARDWARE
 
- UWB_RC_RES_FAIL_INVALID_IE_DATA
 
- UWB_RC_RES_FAIL_INVALID_PARAMETER
 
- UWB_RC_RES_FAIL_INVALID_SIZE
 
- UWB_RC_RES_FAIL_INVALID_STATE
 
- UWB_RC_RES_FAIL_NO_MORE_ASIE_NOTIF
 
- UWB_RC_RES_FAIL_NO_SLOTS
 
- UWB_RC_RES_FAIL_TIME_OUT
 
- UWB_RC_RES_FAIL_UNSUPPORTED_PWR_LEVEL
 
- UWB_RC_RES_SUCCESS
 
- UWB_RC_SET_DAA_ENERGY_MASK
 
- UWB_RC_SET_NOTIFICATION_FILTER_EX
 
- UWB_RELINQUISH_REQUEST_IE
 
- UWB_RELINQUISH_REQ_REASON_NON_SPECIFIC
 
- UWB_RELINQUISH_REQ_REASON_OVER_ALLOCATION
 
- UWB_RSV_ALLOC_FOUND
 
- UWB_RSV_ALLOC_NOT_FOUND
 
- UWB_RSV_MAS_NOT_AVAIL
 
- UWB_RSV_MAS_SAFE
 
- UWB_RSV_MAS_UNSAFE
 
- UWB_RSV_STATE_LAST
 
- UWB_RSV_STATE_NONE
 
- UWB_RSV_STATE_O_ESTABLISHED
 
- UWB_RSV_STATE_O_INITIATED
 
- UWB_RSV_STATE_O_MODIFIED
 
- UWB_RSV_STATE_O_MOVE_COMBINING
 
- UWB_RSV_STATE_O_MOVE_EXPANDING
 
- UWB_RSV_STATE_O_MOVE_REDUCING
 
- UWB_RSV_STATE_O_PENDING
 
- UWB_RSV_STATE_O_TO_BE_MOVED
 
- UWB_RSV_STATE_T_ACCEPTED
 
- UWB_RSV_STATE_T_CONFLICT
 
- UWB_RSV_STATE_T_DENIED
 
- UWB_RSV_STATE_T_EXPANDING_ACCEPTED
 
- UWB_RSV_STATE_T_EXPANDING_CONFLICT
 
- UWB_RSV_STATE_T_EXPANDING_DENIED
 
- UWB_RSV_STATE_T_EXPANDING_PENDING
 
- UWB_RSV_STATE_T_PENDING
 
- UWB_RSV_STATE_T_RESIZED
 
- UWB_RSV_TARGET_DEV
 
- UWB_RSV_TARGET_DEVADDR
 
- UWB_SCAN_DISABLED
 
- UWB_SCAN_ONLY
 
- UWB_SCAN_ONLY_STARTTIME
 
- UWB_SCAN_OUTSIDE_BP
 
- UWB_SCAN_TOP
 
- UWB_SCAN_WHILE_INACTIVE
 
- UWB_SUPERFRAME_LENGTH_US
 
- UWB_USABLE_MAS_PER_ROW
 
- UWF
 
- UWF_EN
 
- UWIRE_BASE_PHYS
 
- UWIRE_CHK_READY
 
- UWIRE_CLK_INVERTED
 
- UWIRE_CSR
 
- UWIRE_CS_ACTIVE_HIGH
 
- UWIRE_CS_ACTIVE_LOW
 
- UWIRE_FREQ_DIV_2
 
- UWIRE_FREQ_DIV_4
 
- UWIRE_FREQ_DIV_8
 
- UWIRE_IO_SIZE
 
- UWIRE_RDR
 
- UWIRE_READ_FALLING_EDGE
 
- UWIRE_READ_RISING_EDGE
 
- UWIRE_SR1
 
- UWIRE_SR2
 
- UWIRE_SR3
 
- UWIRE_SR4
 
- UWIRE_SR5
 
- UWIRE_TDR
 
- UWIRE_WRITE_FALLING_EDGE
 
- UWIRE_WRITE_RISING_EDGE
 
- UWORD_CPYBUF_SIZE
 
- UWRCRSXE
 
- UW_MASK
 
- UW_SHIFT
 
- UWtype
 
- UX500_CPU1_JUMPADDR_OFFSET
 
- UX500_CPU1_WAKEMAGIC_OFFSET
 
- UX500_I2S_FORMATS
 
- UX500_I2S_RATES
 
- UX500_MSP1_INTERNAL_CLOCK_FREQ
 
- UX500_MSP_I2S_H
 
- UX500_MSP_INTERNAL_CLOCK_FREQ
 
- UX500_MSP_MASTER_CLOCK
 
- UX500_MSP_MAX_CHANNELS
 
- UX500_MSP_MIN_CHANNELS
 
- UX500_MUSB_CHARGER
 
- UX500_MUSB_CLEAN
 
- UX500_MUSB_DMA_NUM_RX_TX_CHANNELS
 
- UX500_MUSB_ENUMERATED
 
- UX500_MUSB_ID
 
- UX500_MUSB_NONE
 
- UX500_MUSB_PREPARE
 
- UX500_MUSB_RIDA
 
- UX500_MUSB_RIDB
 
- UX500_MUSB_RIDC
 
- UX500_MUSB_VBUS
 
- UX500_NBR_OF_DAI
 
- UX500_PCM_H
 
- UX500_PHYS_UART
 
- UX500_PLATFORM_BUFFER_BYTES_MAX
 
- UX500_PLATFORM_PERIODS_BYTES_MAX
 
- UX500_PLATFORM_PERIODS_BYTES_MIN
 
- UX500_PLATFORM_PERIODS_MAX
 
- UX500_PLATFORM_PERIODS_MIN
 
- UX500_SUSPEND_OPS
 
- UX500_VIRT_ROM
 
- UX500_msp_dai_H
 
- UXGA_HEIGHT
 
- UXGA_WIDTH
 
- UX_DISC_INT
 
- UX_EXIT
 
- UYVY
 
- UYVY10_1X20
 
- UYVY10_2X10
 
- UYVY12_1X24
 
- UYVY12_2X12
 
- UYVY8_1X16
 
- UYVY8_1_5X8
 
- UYVY8_2X8
 
- U_AUTO_DMA_DISABLE
 
- U_AUTO_DMA_EN_MASK
 
- U_BRG
 
- U_BUSY
 
- U_ECM_H
 
- U_EEM_H
 
- U_ETH_BDS_PER_PAGE
 
- U_ETH_BDS_PER_PAGE_MASK
 
- U_ETH_CQE_PER_PAGE_MASK
 
- U_ETH_LOCAL_BD_RING_SIZE
 
- U_ETH_LOCAL_SGE_RING_SIZE
 
- U_ETH_MAX_SGES_FOR_PACKET
 
- U_ETH_NUM_OF_SGES_TO_FETCH
 
- U_ETH_SGES_PER_PAGE
 
- U_ETH_SGES_PER_PAGE_INVERSE_MASK
 
- U_ETH_SGES_PER_PAGE_MASK
 
- U_ETH_SGL_SIZE
 
- U_ETH_UNDEFINED_Q
 
- U_FFS_H
 
- U_FRAME_RSET
 
- U_FRAME_UA
 
- U_FUNCTION
 
- U_GETHER_H
 
- U_HID_H
 
- U_MIDI_H
 
- U_MODE
 
- U_NCM_H
 
- U_NOT_AVAILABLE
 
- U_OFFSET
 
- U_P2
 
- U_P3
 
- U_P4
 
- U_P5
 
- U_PARAMETER
 
- U_PERMISSION
 
- U_PRINTER_H
 
- U_RNDIS_H
 
- U_STA
 
- U_SUCCESS
 
- U_TCM_H
 
- U_TXR
 
- U_UAC2_H
 
- U_UVC_H
 
- UartInterrupt
 
- UcodeLoadStatus
 
- UnMount
 
- Un_impl
 
- Unaligned
 
- Undefined
 
- Underflowflag
 
- Underflowtrap
 
- UniCaseRange
 
- UniStrcat
 
- UniStrchr
 
- UniStrcmp
 
- UniStrcpy
 
- UniStrlen
 
- UniStrlwr
 
- UniStrncat
 
- UniStrncmp
 
- UniStrncmp_le
 
- UniStrncpy
 
- UniStrncpy_from_le
 
- UniStrncpy_le
 
- UniStrncpy_to_le
 
- UniStrnlen
 
- UniStrstr
 
- UniStrupr
 
- UniTolower
 
- UniToupper
 
- UnicastAddress
 
- UnicastAddress_iP6Address
 
- UnicastAddress_iPAddress
 
- UnknownMemType
 
- UnknownMessage
 
- UnloadStateExt
 
- Unordered
 
- Unorderedbit
 
- UnregistrationRequest
 
- UnregistrationRequest_callSignalAddress
 
- Unspecified
 
- UnusedRegister
 
- UpComplete
 
- UpListPtr
 
- UpPktStatus
 
- UpStall
 
- UpUnstall
 
- UpdateBrateTbl
 
- UpdateBrateTblForSoftAP
 
- UpdateFifoState
 
- UpdateHalRAMask8188EUsb
 
- UpdateHalRAMask8723B
 
- UpdateReceivedRateHistogramStatistics8190
 
- UpdateReg
 
- UpdateRegs
 
- UpdateRxPktTimeStamp8190
 
- UpdateStats
 
- Update_ODM_ComInfo_8723b
 
- Update_ODM_ComInfo_88E
 
- Update_RA_Entry
 
- UpperWordSwap
 
- Usage
 
- UsbStst
 
- UseASER1Input
 
- UsePriorityShift
 
- UsnJrnlMajorVer
 
- UsnJrnlMinorVer
 
- UvdBootLevel
 
- UvdBootLevel_MASK
 
- UvdBootLevel_SHIFT
 
[..]