[..]
- T
 
- T0
 
- T0_BIT
 
- T0_BOT
 
- T0_TOP
 
- T1
 
- T100CHI_MOUSE_REPORT_ID
 
- T100_TPAD_INTF
 
- T10_CHK_APP_TAG_MSK
 
- T10_CHK_EN_MSK
 
- T10_CHK_EN_OFF
 
- T10_CHK_MSK_OFF
 
- T10_CHK_REF_TAG_MSK
 
- T10_INSRT_EN_MSK
 
- T10_INSRT_EN_OFF
 
- T10_PI_APP_ESCAPE
 
- T10_PI_REF_ESCAPE
 
- T10_PI_TYPE0_PROTECTION
 
- T10_PI_TYPE1_PROTECTION
 
- T10_PI_TYPE2_PROTECTION
 
- T10_PI_TYPE3_PROTECTION
 
- T10_RMV_EN_MSK
 
- T10_RMV_EN_OFF
 
- T10_RPLC_EN_MSK
 
- T10_RPLC_EN_OFF
 
- T17
 
- T18
 
- T18_DESC
 
- T19
 
- T19_1610_SPIF_CS2
 
- T19_DESC
 
- T1CH
 
- T1CL
 
- T1CMPR
 
- T1CNTR
 
- T1CNTRLR
 
- T1DONE
 
- T1ENABLE
 
- T1FRAMER_AERR
 
- T1FRAMER_ALARM1_STATUS
 
- T1FRAMER_ALARM2_STATUS
 
- T1FRAMER_COFA_MASK
 
- T1FRAMER_FERR_LSB
 
- T1FRAMER_FERR_MSB
 
- T1FRAMER_LCV_LSB
 
- T1FRAMER_LCV_MSB
 
- T1FRAMER_LOF_MASK
 
- T1FRAMER_SEF_MASK
 
- T1F_IEMPTY
 
- T1F_IFLAGS
 
- T1F_IFULL
 
- T1F_IHALF
 
- T1F_IREADY
 
- T1F_OEMPTY
 
- T1F_OFLAGS
 
- T1F_OFULL
 
- T1F_OHALF
 
- T1F_OREADY
 
- T1F_RAIS
 
- T1F_RALOS
 
- T1F_RLOF
 
- T1F_RLOS
 
- T1F_RMYEL
 
- T1F_RYEL
 
- T1F_SIGFRZ
 
- T1F_UNUSED
 
- T1LH
 
- T1LL
 
- T1MODE
 
- T1MODE_CONT
 
- T1PRESCALER_MASK
 
- T1RELOAD
 
- T1_ANALYSE
 
- T1_BIT
 
- T1_BOT
 
- T1_DESC
 
- T1_FASTLINK
 
- T1_FIFOSTAT
 
- T1_IDENT
 
- T1_INSTAT
 
- T1_INT
 
- T1_IRQENABLE
 
- T1_IRQMASTER
 
- T1_OUTSTAT
 
- T1_READ
 
- T1_RESETBOARD
 
- T1_RESETLINK
 
- T1_SLOWLINK
 
- T1_TOP
 
- T1_WRITE
 
- T2
 
- T20
 
- T20_1610_LOW_PWR
 
- T20_1610_MPUIO5
 
- T20_DESC
 
- T21
 
- T213_FORMAT_STATUS_BYTE
 
- T213_FORMAT_STATUS_MASK
 
- T213_FORMAT_TOUCH_BIT
 
- T213_MAX_XC
 
- T213_MAX_YC
 
- T213_MIN_XC
 
- T213_MIN_YC
 
- T21_DESC
 
- T22
 
- T22_DESC
 
- T23
 
- T24
 
- T25
 
- T26
 
- T262_RAM_AREA_CRITICAL_RAM
 
- T262_RAM_AREA_DDR_RAM
 
- T262_RAM_AREA_EXTERNAL_RAM
 
- T262_RAM_AREA_MISC
 
- T262_RAM_AREA_SHARED_RAM
 
- T263_QUEUE_TYPE_ATIO
 
- T263_QUEUE_TYPE_REQ
 
- T263_QUEUE_TYPE_RSP
 
- T268_BUF_TYPE_EXCH_BUFOFF
 
- T268_BUF_TYPE_EXTD_LOGIN
 
- T268_BUF_TYPE_EXTD_TRACE
 
- T268_BUF_TYPE_REQ_MIRROR
 
- T268_BUF_TYPE_RSP_MIRROR
 
- T274_QUEUE_TYPE_ATIO_SHAD
 
- T274_QUEUE_TYPE_REQ_SHAD
 
- T274_QUEUE_TYPE_RSP_SHAD
 
- T2CH
 
- T2CKR
 
- T2CL
 
- T2CMPR
 
- T2CMP_OFST
 
- T2CNTR
 
- T2CNTRLR
 
- T2DONE
 
- T2ENABLE
 
- T2PRESCALER_MASK
 
- T2RELOAD
 
- T2_AIR
 
- T2_CERR1
 
- T2_CERR2
 
- T2_CERR3
 
- T2_CONF
 
- T2_CPU0_BASE
 
- T2_CPU1_BASE
 
- T2_CPU2_BASE
 
- T2_CPU3_BASE
 
- T2_CPUn_BASE
 
- T2_DEFAULT_MEM_BASE
 
- T2_DENSE_MEM
 
- T2_DIR
 
- T2_DIRECTMAP_2G
 
- T2_DIRECTMAP_LENGTH
 
- T2_DIRECTMAP_START
 
- T2_FFIRST_RSP_PARMS
 
- T2_FNEXT_RSP_PARMS
 
- T2_HAE_1
 
- T2_HAE_2
 
- T2_HAE_3
 
- T2_HAE_4
 
- T2_HAE_ADDRESS
 
- T2_HBASE
 
- T2_IACK_SC
 
- T2_ICE
 
- T2_IO
 
- T2_IOCSR
 
- T2_ISA_SG_LENGTH
 
- T2_ISA_SG_START
 
- T2_IVR
 
- T2_MEM0_BASE
 
- T2_MEM1_BASE
 
- T2_MEM2_BASE
 
- T2_MEM3_BASE
 
- T2_MEM_R1_MASK
 
- T2_ONE_HAE_WINDOW
 
- T2_PERR1
 
- T2_PERR2
 
- T2_PSCR
 
- T2_REGMAP_SIZE
 
- T2_SPARSE_MEM
 
- T2_TBASE1
 
- T2_TBASE2
 
- T2_TBASE3
 
- T2_TBASE4
 
- T2_TDR0
 
- T2_TDR1
 
- T2_TDR2
 
- T2_TDR3
 
- T2_TDR4
 
- T2_TDR5
 
- T2_TDR6
 
- T2_TDR7
 
- T2_TLBBR
 
- T2_USB_MODE_CEA2011_3PIN
 
- T2_USB_MODE_ULPI
 
- T2_VAR
 
- T2_WBASE1
 
- T2_WBASE2
 
- T2_WBASE3
 
- T2_WBASE4
 
- T2_WMASK1
 
- T2_WMASK2
 
- T2_WMASK3
 
- T2_WMASK4
 
- T2_XMM
 
- T3
 
- T3A
 
- T3B
 
- T3C
 
- T3CKR
 
- T3CNAMSIZ
 
- T3C_DATA
 
- T3_BIND_MW
 
- T3_BYPASS
 
- T3_COMPLETION_FLAG
 
- T3_CPL_H
 
- T3_CTL_QP_TID
 
- T3_CTRL_CQ_ID
 
- T3_CTRL_QP_ID
 
- T3_CTRL_QP_SIZE_LOG2
 
- T3_EOP
 
- T3_FAST_REGISTER
 
- T3_LOCAL_FENCE_FLAG
 
- T3_LOCAL_INV
 
- T3_LOOP
 
- T3_MAX_CQ_DEPTH
 
- T3_MAX_DEV_NAME_LEN
 
- T3_MAX_FASTREG_DEPTH
 
- T3_MAX_FASTREG_FRAG
 
- T3_MAX_INLINE
 
- T3_MAX_MR_SIZE
 
- T3_MAX_NUM_CQ
 
- T3_MAX_NUM_PD
 
- T3_MAX_NUM_QP
 
- T3_MAX_NUM_RI
 
- T3_MAX_NUM_STAG
 
- T3_MAX_PBL_SIZE
 
- T3_MAX_QP_DEPTH
 
- T3_MAX_RQ_SIZE
 
- T3_MAX_SGE
 
- T3_MUX
 
- T3_MUX_2
 
- T3_NOTIFY_FLAG
 
- T3_PAGESIZE_MASK
 
- T3_QP_MOD
 
- T3_RDMA_INIT
 
- T3_RDMA_READ_REQ_WITH_INV
 
- T3_RDMA_WRITE
 
- T3_READ_FENCE_FLAG
 
- T3_READ_REQ
 
- T3_READ_RESP
 
- T3_REGMAP_SIZE
 
- T3_REV_A
 
- T3_REV_B
 
- T3_REV_B2
 
- T3_REV_C
 
- T3_RQ_COOKIE_FLIT
 
- T3_RQ_CQE_FLIT
 
- T3_SEND
 
- T3_SEND_WITH_INV
 
- T3_SEND_WITH_SE
 
- T3_SEND_WITH_SE_INV
 
- T3_SOLICITED_EVENT_FLAG
 
- T3_SOP
 
- T3_SOPEOP
 
- T3_SQ_COOKIE_FLIT
 
- T3_SQ_CQE_FLIT
 
- T3_STAG0_MAX_PBE_LEN
 
- T3_STAG0_PAGE_SHIFT
 
- T3_STAG0_PBL_SIZE
 
- T3_STAG_UNSET
 
- T3_TERMINATE
 
- T3_UNLOOP
 
- T3_UTX_MEM_READ
 
- T3_UTX_MEM_WRITE
 
- T3_VRAM
 
- T3_VRAM_2
 
- T3_WR_BIND
 
- T3_WR_BP
 
- T3_WR_FASTREG
 
- T3_WR_INIT
 
- T3_WR_INV_STAG
 
- T3_WR_QP_MOD
 
- T3_WR_RCV
 
- T3_WR_READ
 
- T3_WR_SEND
 
- T3_WR_WRITE
 
- T3_XMM
 
- T4
 
- T4CKR
 
- T4D_AINTEN_A
 
- T4D_AINTEN_B
 
- T4D_AINT_A
 
- T4D_AINT_B
 
- T4D_BANK_A
 
- T4D_BANK_B
 
- T4D_CEBC_A
 
- T4D_CSPF_A
 
- T4D_CSPF_B
 
- T4D_DEFAULT_PCM_CVOL
 
- T4D_DEFAULT_PCM_PAN
 
- T4D_DEFAULT_PCM_RVOL
 
- T4D_DEFAULT_PCM_VOL
 
- T4D_DLY_A
 
- T4D_LFO_GC_CIR
 
- T4D_MISCINT
 
- T4D_MPU401_BASE
 
- T4D_MPUR0
 
- T4D_MPUR1
 
- T4D_MPUR2
 
- T4D_MPUR3
 
- T4D_MUSICVOL_WAVEVOL
 
- T4D_NUM_BANKS
 
- T4D_RCI
 
- T4D_SBBL_SBCL
 
- T4D_SBCTRL_SBE2R_SBDD
 
- T4D_SBDELTA_DELTA_R
 
- T4D_SIGN_CSO_A
 
- T4D_START_A
 
- T4D_START_B
 
- T4D_STIMER
 
- T4D_STOP_A
 
- T4D_STOP_B
 
- T4FW_MIN_VERSION_MAJOR
 
- T4FW_MIN_VERSION_MICRO
 
- T4FW_MIN_VERSION_MINOR
 
- T4FW_VERSION_BUILD
 
- T4FW_VERSION_MAJOR
 
- T4FW_VERSION_MICRO
 
- T4FW_VERSION_MINOR
 
- T4VF_CIM_BASE_ADDR
 
- T4VF_ETHTXQ_MAX_HDR
 
- T4VF_MBDATA_BASE_ADDR
 
- T4VF_MBDATA_FIRST
 
- T4VF_MBDATA_LAST
 
- T4VF_MOD_MAP
 
- T4VF_MPS_BASE_ADDR
 
- T4VF_OS_LOG_MBOX_CMDS
 
- T4VF_PL_BASE_ADDR
 
- T4VF_REGMAP_SIZE
 
- T4VF_REGMAP_START
 
- T4VF_SGE_BASE_ADDR
 
- T4_A1
 
- T4_A2
 
- T4_ADDRESS_BASE
 
- T4_BAR2_QTYPE_EGRESS
 
- T4_BAR2_QTYPE_INGRESS
 
- T4_CMD_REGISTER_READ
 
- T4_CMD_REGISTER_WRITE
 
- T4_COUNT_PER_ELECTRODE
 
- T4_DESC
 
- T4_EQ_ENTRY_SIZE
 
- T4_ERR_ACCESS
 
- T4_ERR_BOUND
 
- T4_ERR_CRC
 
- T4_ERR_DDP_QUEUE_NUM
 
- T4_ERR_DDP_VERSION
 
- T4_ERR_ECC
 
- T4_ERR_ECC_PSTAG
 
- T4_ERR_INTERNAL_ERR
 
- T4_ERR_INVALIDATE_MR_WITH_MW_BOUND
 
- T4_ERR_INVALIDATE_SHARED_MR
 
- T4_ERR_IRD_OVERFLOW
 
- T4_ERR_MARKER
 
- T4_ERR_MO
 
- T4_ERR_MSN
 
- T4_ERR_MSN_GAP
 
- T4_ERR_MSN_RANGE
 
- T4_ERR_OPCODE
 
- T4_ERR_OUT_OF_RQE
 
- T4_ERR_PBL_ADDR_BOUND
 
- T4_ERR_PDID
 
- T4_ERR_PDU_LEN_ERR
 
- T4_ERR_QPID
 
- T4_ERR_RDMA_VERSION
 
- T4_ERR_RQE_ADDR_BOUND
 
- T4_ERR_STAG
 
- T4_ERR_SUCCESS
 
- T4_ERR_SWFLUSH
 
- T4_ERR_TBIT
 
- T4_ERR_WRAP
 
- T4_FATAL_ERROR
 
- T4_FEATURE_REPORT_ID
 
- T4_FEATURE_REPORT_LEN
 
- T4_FEEDCFG4_ADVANCED_ABS_ENABLE
 
- T4_FIRST_REV
 
- T4_FW_MAJ
 
- T4_I2C_ABS
 
- T4_INPUT_REPORT_LEN
 
- T4_LAST_REV
 
- T4_LISTEN_STARTED
 
- T4_LISTEN_START_PENDING
 
- T4_MAX_FR_DSGL
 
- T4_MAX_FR_DSGL_DEPTH
 
- T4_MAX_FR_IMMD
 
- T4_MAX_FR_IMMD_DEPTH
 
- T4_MAX_MR_SIZE
 
- T4_MAX_NUM_PD
 
- T4_MAX_RECV_SGE
 
- T4_MAX_SEND_INLINE
 
- T4_MAX_SEND_SGE
 
- T4_MAX_WRITE_INLINE
 
- T4_MAX_WRITE_SGE
 
- T4_MEMORY_READ
 
- T4_MEMORY_WRITE
 
- T4_OS_LOG_MBOX_CMDS
 
- T4_PAGESIZE_MASK
 
- T4_PRM_FEED_CONFIG_1
 
- T4_PRM_FEED_CONFIG_4
 
- T4_PRM_ID_CONFIG_3
 
- T4_REGMAP_SIZE
 
- T4_RQT_ENTRY_SHIFT
 
- T4_RQT_ENTRY_SIZE
 
- T4_RQ_NUM_BYTES
 
- T4_RQ_NUM_SLOTS
 
- T4_SQ_NUM_BYTES
 
- T4_SQ_NUM_SLOTS
 
- T4_SQ_ONCHIP
 
- T4_SRQ_LIMIT_SUPPORT
 
- T4_STAG_UNSET
 
- T4_STATUS_PAGE_DISABLED
 
- T4_TX_MODQ_10G_WEIGHT_DEFAULT
 
- T4_ULPTX_MAX_DMA
 
- T4_ULPTX_MIN_IO
 
- T4_WRITE_CMPL_MAX_CQE
 
- T4_WRITE_CMPL_MAX_SGL
 
- T4_init
 
- T5
 
- T5403_C
 
- T5403_CALIB_DATA
 
- T5403_COMMAND
 
- T5403_C_U16
 
- T5403_DATA
 
- T5403_I2C_ADDR
 
- T5403_I2C_MASK
 
- T5403_MODE_HIGH
 
- T5403_MODE_LOW
 
- T5403_MODE_SHIFT
 
- T5403_MODE_STANDARD
 
- T5403_MODE_ULTRA_HIGH
 
- T5403_PT
 
- T5403_SCO
 
- T5403_SLAVE_ADDR
 
- T5CKR
 
- T5FW_MIN_VERSION_MAJOR
 
- T5FW_MIN_VERSION_MICRO
 
- T5FW_MIN_VERSION_MINOR
 
- T5FW_VERSION_BUILD
 
- T5FW_VERSION_MAJOR
 
- T5FW_VERSION_MICRO
 
- T5FW_VERSION_MINOR
 
- T5_A0
 
- T5_A1
 
- T5_ALLOC_G
 
- T5_ALLOC_M
 
- T5_ALLOC_S
 
- T5_DESC
 
- T5_FIRST_REV
 
- T5_ISS_F
 
- T5_ISS_S
 
- T5_ISS_V
 
- T5_ISS_VALID
 
- T5_LAST_REV
 
- T5_OPT_2_VALID_F
 
- T5_OPT_2_VALID_S
 
- T5_OPT_2_VALID_V
 
- T5_PORT0_BASE
 
- T5_PORT_BASE
 
- T5_PORT_REG
 
- T5_PORT_STRIDE
 
- T5_REGMAP_SIZE
 
- T5_TFEN_F
 
- T5_TFEN_S
 
- T5_TFEN_V
 
- T5_TFINVERTMATCH_F
 
- T5_TFINVERTMATCH_S
 
- T5_TFINVERTMATCH_V
 
- T5_TFPORT_G
 
- T5_TFPORT_M
 
- T5_TFPORT_S
 
- T5_TFPORT_V
 
- T5_ULP_MEMIO_FID_M
 
- T5_ULP_MEMIO_FID_S
 
- T5_ULP_MEMIO_FID_V
 
- T5_ULP_MEMIO_IMM_F
 
- T5_ULP_MEMIO_IMM_S
 
- T5_ULP_MEMIO_IMM_V
 
- T5_ULP_MEMIO_ORDER_F
 
- T5_ULP_MEMIO_ORDER_S
 
- T5_ULP_MEMIO_ORDER_V
 
- T5_USED_G
 
- T5_USED_M
 
- T5_USED_S
 
- T6
 
- T6CKR
 
- T6FW_MIN_VERSION_MAJOR
 
- T6FW_MIN_VERSION_MICRO
 
- T6FW_MIN_VERSION_MINOR
 
- T6FW_VERSION_BUILD
 
- T6FW_VERSION_MAJOR
 
- T6FW_VERSION_MICRO
 
- T6FW_VERSION_MINOR
 
- T6VF_MBDATA_BASE_ADDR
 
- T6_A0
 
- T6_COMPR_RXERR_LEN_F
 
- T6_COMPR_RXERR_LEN_S
 
- T6_COMPR_RXERR_LEN_V
 
- T6_COMPR_RXERR_SUM_F
 
- T6_COMPR_RXERR_SUM_S
 
- T6_COMPR_RXERR_SUM_V
 
- T6_COMPR_RXERR_VEC_G
 
- T6_COMPR_RXERR_VEC_M
 
- T6_COMPR_RXERR_VEC_S
 
- T6_COMPR_RXERR_VEC_V
 
- T6_DBVFIFO_SIZE_G
 
- T6_DBVFIFO_SIZE_M
 
- T6_DBVFIFO_SIZE_S
 
- T6_EGRTHRESHOLDPACKING_G
 
- T6_EGRTHRESHOLDPACKING_M
 
- T6_EGRTHRESHOLDPACKING_S
 
- T6_ENABLE_F
 
- T6_ENABLE_S
 
- T6_ENABLE_V
 
- T6_ETH_HDR_LEN_G
 
- T6_ETH_HDR_LEN_M
 
- T6_ETH_HDR_LEN_S
 
- T6_ETH_HDR_LEN_V
 
- T6_FIRST_REV
 
- T6_INGPADBOUNDARY_32B_X
 
- T6_INGPADBOUNDARY_8B_X
 
- T6_INGPADBOUNDARY_SHIFT_X
 
- T6_IP_HDR_LEN_G
 
- T6_IP_HDR_LEN_S
 
- T6_IP_HDR_LEN_V
 
- T6_LAST_REV
 
- T6_LE_DB_HASH_TID_BASE_A
 
- T6_LIP0_F
 
- T6_LIP0_S
 
- T6_LIP0_V
 
- T6_LIPMISS_F
 
- T6_LIPMISS_S
 
- T6_LIPMISS_V
 
- T6_MAX_AAD_SIZE
 
- T6_MULTILISTEN0_S
 
- T6_PF_G
 
- T6_PF_M
 
- T6_PF_S
 
- T6_PM_NSTATS
 
- T6_REPLICATE_F
 
- T6_REPLICATE_S
 
- T6_REPLICATE_V
 
- T6_RSS_NENTRIES
 
- T6_RX_TNLHDR_LEN_G
 
- T6_RX_TNLHDR_LEN_M
 
- T6_RX_TNLHDR_LEN_S
 
- T6_RX_TNLHDR_LEN_V
 
- T6_SOURCEPF_G
 
- T6_SOURCEPF_M
 
- T6_SOURCEPF_S
 
- T6_SRAM_PRIO0_G
 
- T6_SRAM_PRIO0_M
 
- T6_SRAM_PRIO0_S
 
- T6_SRAM_PRIO1_G
 
- T6_SRAM_PRIO1_M
 
- T6_SRAM_PRIO1_S
 
- T6_SRAM_PRIO2_G
 
- T6_SRAM_PRIO2_M
 
- T6_SRAM_PRIO2_S
 
- T6_SRAM_PRIO3_G
 
- T6_SRAM_PRIO3_M
 
- T6_SRAM_PRIO3_S
 
- T6_SRAM_VLD_F
 
- T6_SRAM_VLD_S
 
- T6_SRAM_VLD_V
 
- T6_STATMODE_S
 
- T6_STATMODE_V
 
- T6_TCP_HDR_LEN_G
 
- T6_TCP_HDR_LEN_S
 
- T6_TCP_HDR_LEN_V
 
- T6_TXPKT_ETHHDR_LEN_S
 
- T6_TXPKT_ETHHDR_LEN_V
 
- T6_TX_FORCE_F
 
- T6_TX_FORCE_S
 
- T6_TX_FORCE_V
 
- T6_UNKNOWNCMD_F
 
- T6_UNKNOWNCMD_S
 
- T6_UNKNOWNCMD_V
 
- T6_VFWRADDR_G
 
- T6_VFWRADDR_M
 
- T6_VFWRADDR_S
 
- T6_VFWRADDR_V
 
- T6_VF_G
 
- T6_VF_M
 
- T6_VF_S
 
- T6_VF_VALID_F
 
- T6_VF_VALID_S
 
- T6_VF_VALID_V
 
- T6_keyBlock_hdr
 
- T7
 
- T7CKR
 
- T7L66XB_CELL_MMC
 
- T7L66XB_CELL_NAND
 
- T7L66XB_NR_IRQS
 
- T8CKR
 
- T9
 
- T93C46_Clk
 
- T93C46_Read_Bit
 
- T93C46_Read_Data
 
- T93C46_Read_Word
 
- T93C46_Send_Command
 
- T93C46_Stop
 
- T93C46_Write_Bit
 
- T9CKR
 
- TA
 
- TA8874Z_B0
 
- TA8874Z_B1
 
- TA8874Z_CHAG_FLAG
 
- TA8874Z_F_MONO
 
- TA8874Z_LED_BIL
 
- TA8874Z_LED_EXT
 
- TA8874Z_LED_STE
 
- TA8874Z_MODE_MAIN
 
- TA8874Z_MODE_SUB
 
- TA8874Z_MONO_SET
 
- TA8874Z_MUTE
 
- TA8874Z_SEPARATION
 
- TA8874Z_SEPARATION_DEFAULT
 
- TAA_MITIGATION_OFF
 
- TAA_MITIGATION_TSX_DISABLED
 
- TAA_MITIGATION_UCODE_NEEDED
 
- TAA_MITIGATION_VERW
 
- TAA_MSG_SMT
 
- TAB
 
- TAB0
 
- TAB1
 
- TAB2
 
- TAB3
 
- TABCLR
 
- TABDLY
 
- TABLE
 
- TABLE32_TEST
 
- TABLE64_TEST_HI
 
- TABLE64_TEST_LO
 
- TABLETPC
 
- TABLETPC2FG
 
- TABLETPCE
 
- TABLET_MODE_FLAG
 
- TABLE_4
 
- TABLE_ACL
 
- TABLE_ACL_V
 
- TABLE_ACTIVITY_MONITOR_COEFF
 
- TABLE_ADDRESS
 
- TABLE_AVFS
 
- TABLE_AVFS_FUSE_OVERRIDE
 
- TABLE_AVFS_PSM_DEBUG
 
- TABLE_BIOS_IF
 
- TABLE_CASE
 
- TABLE_COUNT
 
- TABLE_CUSTOM_DPM
 
- TABLE_DPMCLOCKS
 
- TABLE_DRIVER_SMU_CONFIG
 
- TABLE_DYNAMIC_MAC
 
- TABLE_DYNAMIC_MAC_V
 
- TABLE_EEE
 
- TABLE_EEE_V
 
- TABLE_ENTRY_MASK
 
- TABLE_EXT_ENTRY_MASK
 
- TABLE_EXT_SELECT_S
 
- TABLE_I2C_COMMANDS
 
- TABLE_LINK_MD
 
- TABLE_LINK_MD_V
 
- TABLE_LOCAL_INDEX
 
- TABLE_MAIN_INDEX
 
- TABLE_MIB
 
- TABLE_MIB_V
 
- TABLE_MODERN_STDBY
 
- TABLE_MOMENTARY_PM
 
- TABLE_OF_DEVICES
 
- TABLE_ON_PAGE
 
- TABLE_OVERDRIVE
 
- TABLE_PACE
 
- TABLE_PME
 
- TABLE_PME_V
 
- TABLE_PMSTATUSLOG
 
- TABLE_PPTABLE
 
- TABLE_READ
 
- TABLE_ROUTING
 
- TABLE_SELECT_S
 
- TABLE_SEL_SHIFT
 
- TABLE_SIZE
 
- TABLE_SMU_METRICS
 
- TABLE_SPARE1
 
- TABLE_STATIC_MAC
 
- TABLE_STATIC_MAC_V
 
- TABLE_TRANSFER_FAILED
 
- TABLE_TRANSFER_OK
 
- TABLE_TRANSFER_PENDING
 
- TABLE_TYPE_REGION1
 
- TABLE_TYPE_REGION2
 
- TABLE_TYPE_REGION3
 
- TABLE_TYPE_SEGMENT
 
- TABLE_UPDATE_SLEEP_US
 
- TABLE_UPDATE_TIMEOUT_US
 
- TABLE_VLAN
 
- TABLE_VLAN_V
 
- TABLE_WAFL_XGMI_TOPOLOGY
 
- TABLE_WATERMARKS
 
- TABMSK
 
- TABORT
 
- TABRT
 
- TABT_DET
 
- TABT_GEN
 
- TAB_DFX
 
- TAB_MAP
 
- TAB_MAP_INVALID
 
- TAB_MAP_VALID
 
- TAB_RD_TYPE
 
- TAB_SIZE
 
- TAB_STOP_SIZE
 
- TACHO
 
- TACH_MIN_REG
 
- TACH_PERIOD
 
- TACH_PERIOD_MASK
 
- TACH_PERIOD_SHIFT
 
- TACH_PWM_RESP_RATE
 
- TACH_PWM_RESP_RATE_MASK
 
- TACH_PWM_RESP_RATE_SHIFT
 
- TACH_PWM_SOURCE_BIT01
 
- TACH_PWM_SOURCE_BIT2
 
- TACH_PWM_SOURCE_MASK_BIT01
 
- TACH_PWM_SOURCE_MASK_BIT2
 
- TACH_REG
 
- TACK
 
- TAC_BLUE
 
- TAC_DEFAULT
 
- TAC_GREEN
 
- TAC_PINK
 
- TAC_RED
 
- TAC_RESET
 
- TAC_TURQ
 
- TAC_WHITE
 
- TAC_YELLOW
 
- TAD_CH
 
- TAD_DEV_TO_CHAN
 
- TAD_LIMIT
 
- TAD_OFFSET
 
- TAD_SOCK
 
- TAD_TGT0
 
- TAD_TGT1
 
- TAD_TGT2
 
- TAD_TGT3
 
- TAG
 
- TAGFILEMAGIC
 
- TAGINFO1_LEN
 
- TAGINFO2_LEN
 
- TAGLAYOUT_LEN
 
- TAGLOADS
 
- TAGON
 
- TAGSTORES
 
- TAGVER_LEN
 
- TAG_ABSDATA
 
- TAG_AGA
 
- TAG_BOOTDTA
 
- TAG_CABSDATA
 
- TAG_CBOOTDTA
 
- TAG_CIP
 
- TAG_CMP
 
- TAG_COMMENT
 
- TAG_CONTEXT_BITS
 
- TAG_DECODE
 
- TAG_ECS
 
- TAG_ENCODE
 
- TAG_ENTRIES
 
- TAG_Empty
 
- TAG_Error
 
- TAG_FLOWCTRL
 
- TAG_FMODE_1
 
- TAG_FMODE_2
 
- TAG_FMODE_4
 
- TAG_GLOB_LOG_MAX
 
- TAG_GLOB_LOG_MIN
 
- TAG_GLOB_MAX
 
- TAG_GLOB_PHYS_MAX
 
- TAG_GLOB_PHYS_MIN
 
- TAG_GLOB_POP
 
- TAG_GLOB_PUSH
 
- TAG_GLOB_REPORT_CNT
 
- TAG_GLOB_REPORT_ID
 
- TAG_GLOB_REPORT_SZ
 
- TAG_GLOB_UNIT
 
- TAG_GLOB_UNIT_EXP
 
- TAG_GLOB_USAGE
 
- TAG_HIRES
 
- TAG_IDENT_AED
 
- TAG_IDENT_AVDP
 
- TAG_IDENT_EAHD
 
- TAG_IDENT_EFE
 
- TAG_IDENT_FE
 
- TAG_IDENT_FID
 
- TAG_IDENT_FSD
 
- TAG_IDENT_IE
 
- TAG_IDENT_IUVD
 
- TAG_IDENT_LVD
 
- TAG_IDENT_LVID
 
- TAG_IDENT_PD
 
- TAG_IDENT_PIE
 
- TAG_IDENT_PVD
 
- TAG_IDENT_SBD
 
- TAG_IDENT_TD
 
- TAG_IDENT_TE
 
- TAG_IDENT_USD
 
- TAG_IDENT_USE
 
- TAG_IDENT_VDP
 
- TAG_LORES
 
- TAG_MAIN_COL_END
 
- TAG_MAIN_COL_START
 
- TAG_MAIN_FEATURE
 
- TAG_MAIN_INPUT
 
- TAG_MAIN_OUTPUT
 
- TAG_MODE
 
- TAG_NONE
 
- TAG_NO_CIP_HEADER
 
- TAG_OCS
 
- TAG_OVERRIDE
 
- TAG_PTR
 
- TAG_Q_REJECT
 
- TAG_Q_TRYING
 
- TAG_READ
 
- TAG_SHRES
 
- TAG_STATUS_QUERY_CONDITION_BITS
 
- TAG_STATUS_QUERY_MASK_BITS
 
- TAG_STORAGE_PAGES
 
- TAG_STRT
 
- TAG_SYSCALL
 
- TAG_SZ
 
- TAG_Special
 
- TAG_TIMESTMP
 
- TAG_TW_Command_Apache
 
- TAG_TW_Command_Apache_Header
 
- TAG_TW_Command_Full
 
- TAG_TW_Compatibility_Info
 
- TAG_TW_Device_Extension
 
- TAG_TW_Event
 
- TAG_TW_Initconnect
 
- TAG_TW_Ioctl
 
- TAG_TW_Ioctl_Apache
 
- TAG_TW_Ioctl_Driver_Command
 
- TAG_TW_Lock
 
- TAG_TW_New_Ioctl
 
- TAG_TW_Passthru
 
- TAG_TW_Response_Queue
 
- TAG_TW_SG_Entry
 
- TAG_TW_SG_Entry_ISO
 
- TAG_TYPE_MASK
 
- TAG_VALID
 
- TAG_Valid
 
- TAG_WRITE
 
- TAG_Zero
 
- TAG_twa_message_type
 
- TAHITI_GB_ADDR_CONFIG_GOLDEN
 
- TAHITI_IO_MC_REGS_SIZE
 
- TAHITI_MC_UCODE_SIZE
 
- TAHITI_RB_BITMAP_WIDTH_PER_SH
 
- TAHITI_SMC_UCODE_SIZE
 
- TAHITI_SMC_UCODE_START
 
- TAHVO_INT_VBUS
 
- TAHVO_MODE_HOST
 
- TAHVO_MODE_PERIPHERAL
 
- TAHVO_REG_IDSR
 
- TAHVO_REG_IMR
 
- TAHVO_REG_USBR
 
- TAHVO_STAT_VBUS
 
- TAH_MR_CVR
 
- TAH_MR_DIG
 
- TAH_MR_DTFP
 
- TAH_MR_SR
 
- TAH_MR_ST_1024
 
- TAH_MR_ST_1280
 
- TAH_MR_ST_1536
 
- TAH_MR_ST_256
 
- TAH_MR_ST_512
 
- TAH_MR_ST_768
 
- TAH_MR_TFS_10KB
 
- TAH_MR_TFS_16KB
 
- TAH_MR_TFS_2KB
 
- TAH_MR_TFS_4KB
 
- TAH_MR_TFS_6KB
 
- TAH_MR_TFS_8KB
 
- TAILQ_EMPTY
 
- TAILQ_ENTRY
 
- TAILQ_FIRST
 
- TAILQ_FOREACH
 
- TAILQ_FOREACH_REVERSE
 
- TAILQ_HEAD
 
- TAILQ_HEAD_INITIALIZER
 
- TAILQ_INIT
 
- TAILQ_INSERT_AFTER
 
- TAILQ_INSERT_BEFORE
 
- TAILQ_INSERT_HEAD
 
- TAILQ_INSERT_TAIL
 
- TAILQ_LAST
 
- TAILQ_NEXT
 
- TAILQ_PREV
 
- TAILQ_REMOVE
 
- TAIL_ADDR
 
- TAIL_FULL
 
- TAIL_MAPPING
 
- TAIL_SIZE
 
- TAIL_TAG_LOOKUP
 
- TAIL_TAG_OVERRIDE
 
- TAINT_AUX
 
- TAINT_BAD_PAGE
 
- TAINT_CPU_OUT_OF_SPEC
 
- TAINT_CRAP
 
- TAINT_DIE
 
- TAINT_FIRMWARE_WORKAROUND
 
- TAINT_FLAGS_COUNT
 
- TAINT_FORCED_MODULE
 
- TAINT_FORCED_RMMOD
 
- TAINT_LIVEPATCH
 
- TAINT_MACHINE_CHECK
 
- TAINT_OOT_MODULE
 
- TAINT_OVERRIDDEN_ACPI_TABLE
 
- TAINT_PROPRIETARY_MODULE
 
- TAINT_RANDSTRUCT
 
- TAINT_SOFTLOCKUP
 
- TAINT_UNSIGNED_MODULE
 
- TAINT_USER
 
- TAINT_WARN
 
- TAIWAN_HI_IF_FREQ_44_MHZ
 
- TAI_EVENT_WORK_INTERVAL
 
- TALITOS10_AESU
 
- TALITOS10_AFEU
 
- TALITOS10_DEU
 
- TALITOS10_MDEU
 
- TALITOS10_PKEU
 
- TALITOS10_RNGU
 
- TALITOS12_AESU
 
- TALITOS12_DEU
 
- TALITOS12_MDEU
 
- TALITOS1_CCCR_LO_RESET
 
- TALITOS1_CH_STRIDE
 
- TALITOS1_DEUICR_KPE
 
- TALITOS1_IMR_DONE
 
- TALITOS1_IMR_INIT
 
- TALITOS1_IMR_LO_INIT
 
- TALITOS1_ISR_4CHDONE
 
- TALITOS1_ISR_4CHERR
 
- TALITOS1_ISR_CH_0_DONE
 
- TALITOS1_ISR_CH_0_ERR
 
- TALITOS1_ISR_TEA_ERR
 
- TALITOS1_MAX_DATA_LEN
 
- TALITOS1_MCR_SWR
 
- TALITOS2_AESU
 
- TALITOS2_AFEU
 
- TALITOS2_CCCR_CONT
 
- TALITOS2_CCCR_RESET
 
- TALITOS2_CH_STRIDE
 
- TALITOS2_CRCU
 
- TALITOS2_DEU
 
- TALITOS2_IMR_DONE
 
- TALITOS2_IMR_INIT
 
- TALITOS2_IMR_LO_INIT
 
- TALITOS2_ISR_4CHDONE
 
- TALITOS2_ISR_4CHERR
 
- TALITOS2_ISR_CH_0_2_DONE
 
- TALITOS2_ISR_CH_0_2_ERR
 
- TALITOS2_ISR_CH_0_DONE
 
- TALITOS2_ISR_CH_0_ERR
 
- TALITOS2_ISR_CH_1_3_DONE
 
- TALITOS2_ISR_CH_1_3_ERR
 
- TALITOS2_KEU
 
- TALITOS2_MAX_DATA_LEN
 
- TALITOS2_MCR_SWR
 
- TALITOS2_MDEU
 
- TALITOS2_PKEU
 
- TALITOS2_RNGU
 
- TALITOS_CCCR
 
- TALITOS_CCCR_LO
 
- TALITOS_CCCR_LO_CDIE
 
- TALITOS_CCCR_LO_CDWE
 
- TALITOS_CCCR_LO_EAE
 
- TALITOS_CCCR_LO_IWSE
 
- TALITOS_CCCR_LO_NE
 
- TALITOS_CCCR_LO_NT
 
- TALITOS_CCPSR
 
- TALITOS_CCPSR_LO
 
- TALITOS_CCPSR_LO_DOF
 
- TALITOS_CCPSR_LO_EU
 
- TALITOS_CCPSR_LO_FPZ
 
- TALITOS_CCPSR_LO_GB
 
- TALITOS_CCPSR_LO_GRL
 
- TALITOS_CCPSR_LO_IDH
 
- TALITOS_CCPSR_LO_IEU
 
- TALITOS_CCPSR_LO_MDTE
 
- TALITOS_CCPSR_LO_SB
 
- TALITOS_CCPSR_LO_SGDLZ
 
- TALITOS_CCPSR_LO_SOF
 
- TALITOS_CCPSR_LO_SRL
 
- TALITOS_CDPR
 
- TALITOS_CDPR_LO
 
- TALITOS_CH_BASE_OFFSET
 
- TALITOS_CRA_PRIORITY
 
- TALITOS_CRA_PRIORITY_AEAD_HSNA
 
- TALITOS_DESCBUF
 
- TALITOS_DESCBUF_LO
 
- TALITOS_DESC_SIZE
 
- TALITOS_EUDSR
 
- TALITOS_EUDSR_LO
 
- TALITOS_EUICR
 
- TALITOS_EUICR_LO
 
- TALITOS_EUISR
 
- TALITOS_EUISR_LO
 
- TALITOS_EURCR
 
- TALITOS_EURCR_LO
 
- TALITOS_EUSR
 
- TALITOS_EUSR_LO
 
- TALITOS_EU_FIFO
 
- TALITOS_EU_FIFO_LO
 
- TALITOS_FF
 
- TALITOS_FF_LO
 
- TALITOS_FTR_HMAC_OK
 
- TALITOS_FTR_HW_AUTH_CHECK
 
- TALITOS_FTR_SEC1
 
- TALITOS_FTR_SHA224_HWINIT
 
- TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT
 
- TALITOS_GATHER
 
- TALITOS_GATHER_LO
 
- TALITOS_ICR
 
- TALITOS_ICR_LO
 
- TALITOS_IMR
 
- TALITOS_IMR_LO
 
- TALITOS_ISR
 
- TALITOS_ISR_LO
 
- TALITOS_MAX_IV_LENGTH
 
- TALITOS_MAX_KEY_SIZE
 
- TALITOS_MCR
 
- TALITOS_MCR_LO
 
- TALITOS_MCR_RCA0
 
- TALITOS_MCR_RCA1
 
- TALITOS_MCR_RCA2
 
- TALITOS_MCR_RCA3
 
- TALITOS_MDEUICR_LO_ICE
 
- TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
 
- TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
 
- TALITOS_MDEU_MAX_CONTEXT_SIZE
 
- TALITOS_RNGURCR_LO_SR
 
- TALITOS_RNGUSR_LO_OFL
 
- TALITOS_RNGUSR_LO_RD
 
- TALITOS_SCATTER
 
- TALITOS_SCATTER_LO
 
- TALITOS_TIMEOUT
 
- TALLY
 
- TALLY_RESET
 
- TALLY_SUM_UP
 
- TALYN_FW_MAPPING_TABLE_SIZE
 
- TALYN_MB_FW_MAPPING_TABLE_SIZE
 
- TALYN_RGF_FW_ASSERT_CODE
 
- TALYN_RGF_UCODE_ASSERT_CODE
 
- TAMTX
 
- TANAR
 
- TANAR_FULL_DUP
 
- TANAR_HALF_DUP
 
- TANAR_PS1
 
- TANAR_PS2
 
- TANER
 
- TANGENT
 
- TANGIER_EXT_TIMER0_MSI
 
- TANG_CARD_STATUS
 
- TANG_CLEAR_INT
 
- TANG_RESET
 
- TANG_RX_READY
 
- TANG_TX_READY
 
- TANKMEMADDRREGBASE
 
- TANKMEMADDRREG_ADDR_MASK
 
- TANKMEMADDRREG_ALIGN
 
- TANKMEMADDRREG_CLEAR
 
- TANKMEMADDRREG_READ
 
- TANKMEMADDRREG_WRITE
 
- TANKMEMDATAREGBASE
 
- TANKMEMDATAREG_MASK
 
- TANLPAR
 
- TANSPORTMAPABREGS_END
 
- TANSPORTMAPABREGS_START
 
- TANSPPAGETABLEPHYADDR015_END
 
- TANSPPAGETABLEPHYADDR015_START
 
- TAN_CODE
 
- TAOS_ALS_I2C_ADDR
 
- TAOS_BUFFER_SIZE
 
- TAOS_CMD_ECHO_OFF
 
- TAOS_CMD_ECHO_ON
 
- TAOS_CMD_RESET
 
- TAOS_STATE_EOFF
 
- TAOS_STATE_IDLE
 
- TAOS_STATE_INIT
 
- TAOS_STATE_RECV
 
- TAP2_DISABLE
 
- TAP3_DISABLE
 
- TAPCOLD_RESET
 
- TAPE34XX_FMT_3480
 
- TAPE34XX_FMT_3480_2_XF
 
- TAPE34XX_FMT_3480_XF
 
- TAPE390_CRYPT_ON
 
- TAPE390_CRYPT_ON_MASK
 
- TAPE390_CRYPT_QUERY
 
- TAPE390_CRYPT_SET
 
- TAPE390_CRYPT_SUPPORTED
 
- TAPE390_CRYPT_SUPPORTED_MASK
 
- TAPE390_DISPLAY
 
- TAPE390_KEKL_QUERY
 
- TAPE390_KEKL_SET
 
- TAPE390_KEKL_TYPE_HASH
 
- TAPE390_KEKL_TYPE_LABEL
 
- TAPE390_KEKL_TYPE_NONE
 
- TAPE390_MEDIUM_ENCRYPTED
 
- TAPE390_MEDIUM_ENCRYPTED_MASK
 
- TAPE390_MEDIUM_LOADED
 
- TAPE390_MEDIUM_LOADED_MASK
 
- TAPEBLOCK_HSEC_S2B
 
- TAPEBLOCK_HSEC_SIZE
 
- TAPEBLOCK_RETRIES
 
- TAPECHAR_MAJOR
 
- TAPECLASS_NAME_LEN
 
- TAPE_3590_CRYPT_INFO
 
- TAPE_3590_MAX_MSG
 
- TAPE_3590_READ_BACK_OP
 
- TAPE_DBF_AREA
 
- TAPE_IO_LONG_BUSY
 
- TAPE_IO_PENDING
 
- TAPE_IO_RETRY
 
- TAPE_IO_STOP
 
- TAPE_IO_SUCCESS
 
- TAPE_MAGIC
 
- TAPE_MINOR
 
- TAPE_MINORS_PER_DEV
 
- TAPE_MODE
 
- TAPE_NR
 
- TAPE_NR_MTOPS
 
- TAPE_REQUEST_CANCEL
 
- TAPE_REQUEST_DONE
 
- TAPE_REQUEST_INIT
 
- TAPE_REQUEST_IN_IO
 
- TAPE_REQUEST_LONG_BUSY
 
- TAPE_REQUEST_QUEUED
 
- TAPE_VERSION_MAJOR
 
- TAPE_VERSION_MINOR
 
- TAPRIO_ALL_GATES_OPEN
 
- TAPRIO_FLAGS_INVALID
 
- TAPWAVE_VENDOR_ID
 
- TAPWAVE_ZODIAC_ID
 
- TAP_102_4US
 
- TAP_12_8US
 
- TAP_1_6MS
 
- TAP_200US
 
- TAP_25_6US
 
- TAP_51_2US
 
- TAP_800US
 
- TAP_AXES
 
- TAP_FEATURES
 
- TAP_IFFEATURES
 
- TAP_NOPOLL
 
- TAP_NUM_DEVS
 
- TAP_RESERVE
 
- TAP_RESET
 
- TAP_SIGN
 
- TAP_SOFT_RESET
 
- TAP_VNET_BE
 
- TAP_VNET_LE
 
- TAP_X_EN
 
- TAP_X_SRC
 
- TAP_Y_EN
 
- TAP_Y_SRC
 
- TAP_Z_EN
 
- TAP_Z_SRC
 
- TAR
 
- TARGET
 
- TARGETADDRESS
 
- TARGETALIAS
 
- TARGETLUN_DOK
 
- TARGETLUN_TLV
 
- TARGETNAME
 
- TARGETOS_H
 
- TARGETPORTALGROUPTAG
 
- TARGETRECVDATASEGMENTLENGTH
 
- TARGET_10X_AST_SKID_LIMIT
 
- TARGET_10X_BMISS_OFFLOAD_MAX_VDEV
 
- TARGET_10X_DMA_BURST_SIZE
 
- TARGET_10X_GTK_OFFLOAD_MAX_VDEV
 
- TARGET_10X_MAC_AGGR_DELIM
 
- TARGET_10X_MAX_FRAG_ENTRIES
 
- TARGET_10X_MCAST2UCAST_MODE
 
- TARGET_10X_NUM_MCAST_GROUPS
 
- TARGET_10X_NUM_MCAST_TABLE_ELEMS
 
- TARGET_10X_NUM_MSDU_DESC
 
- TARGET_10X_NUM_OFFLOAD_PEERS
 
- TARGET_10X_NUM_OFFLOAD_REORDER_BUFS
 
- TARGET_10X_NUM_PEERS
 
- TARGET_10X_NUM_PEER_AST
 
- TARGET_10X_NUM_PEER_KEYS
 
- TARGET_10X_NUM_STATIONS
 
- TARGET_10X_NUM_TIDS
 
- TARGET_10X_NUM_TIDS_MAX
 
- TARGET_10X_NUM_VDEVS
 
- TARGET_10X_NUM_WDS_ENTRIES
 
- TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES
 
- TARGET_10X_ROAM_OFFLOAD_MAX_VDEV
 
- TARGET_10X_RX_CHAIN_MASK
 
- TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK
 
- TARGET_10X_RX_TIMEOUT_HI_PRI
 
- TARGET_10X_RX_TIMEOUT_LO_PRI
 
- TARGET_10X_SCAN_MAX_PENDING_REQS
 
- TARGET_10X_TX_CHAIN_MASK
 
- TARGET_10X_TX_DBG_LOG_SIZE
 
- TARGET_10X_TX_STATS_NUM_PEERS
 
- TARGET_10X_TX_STATS_NUM_STATIONS
 
- TARGET_10X_TX_STATS_NUM_TIDS
 
- TARGET_10X_VOW_CONFIG
 
- TARGET_10_2_DMA_BURST_SIZE
 
- TARGET_10_4_11AC_TX_MAX_FRAGS
 
- TARGET_10_4_ACTIVE_PEERS
 
- TARGET_10_4_AST_SKID_LIMIT
 
- TARGET_10_4_ATF_CONFIG
 
- TARGET_10_4_BE_MIN_FREE
 
- TARGET_10_4_BK_MIN_FREE
 
- TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV
 
- TARGET_10_4_DMA_BURST_SIZE
 
- TARGET_10_4_GTK_OFFLOAD_MAX_VDEV
 
- TARGET_10_4_IPHDR_PAD_CONFIG
 
- TARGET_10_4_MAC_AGGR_DELIM
 
- TARGET_10_4_MAX_PEER_EXT_STATS
 
- TARGET_10_4_MCAST2UCAST_MODE
 
- TARGET_10_4_NUM_MCAST_GROUPS
 
- TARGET_10_4_NUM_MCAST_TABLE_ELEMS
 
- TARGET_10_4_NUM_MSDU_DESC
 
- TARGET_10_4_NUM_MSDU_DESC_PFC
 
- TARGET_10_4_NUM_OFFLOAD_PEERS
 
- TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS
 
- TARGET_10_4_NUM_PEERS
 
- TARGET_10_4_NUM_PEER_KEYS
 
- TARGET_10_4_NUM_QCACHE_PEERS_MAX
 
- TARGET_10_4_NUM_STATIONS
 
- TARGET_10_4_NUM_TDLS_BUFFER_STA
 
- TARGET_10_4_NUM_TDLS_SLEEP_STA
 
- TARGET_10_4_NUM_TDLS_VDEVS
 
- TARGET_10_4_NUM_VDEVS
 
- TARGET_10_4_NUM_WDS_ENTRIES
 
- TARGET_10_4_QCACHE_ACTIVE_PEERS
 
- TARGET_10_4_QCACHE_ACTIVE_PEERS_PFC
 
- TARGET_10_4_QWRAP_CONFIG
 
- TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES
 
- TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV
 
- TARGET_10_4_RX_BATCH_MODE
 
- TARGET_10_4_RX_DECAP_MODE
 
- TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK
 
- TARGET_10_4_RX_TIMEOUT_HI_PRI
 
- TARGET_10_4_RX_TIMEOUT_LO_PRI
 
- TARGET_10_4_SCAN_MAX_REQS
 
- TARGET_10_4_SMART_ANT_CAP
 
- TARGET_10_4_TGT_NUM_TIDS
 
- TARGET_10_4_THERMAL_THROTTLING_CONFIG
 
- TARGET_10_4_TX_DBG_LOG_SIZE
 
- TARGET_10_4_VI_MIN_FREE
 
- TARGET_10_4_VOW_CONFIG
 
- TARGET_10_4_VO_MIN_FREE
 
- TARGET_440GX
 
- TARGET_44x
 
- TARGET_4xx
 
- TARGET_824x
 
- TARGET_83xx
 
- TARGET_85xx
 
- TARGET_86xx
 
- TARGET_8xx
 
- TARGET_ABORT_DMA
 
- TARGET_ABORT_INT
 
- TARGET_AND_CURRENT_PROFILE_INDEX
 
- TARGET_AND_CURRENT_PROFILE_INDEX_1
 
- TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT
 
- TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT
 
- TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT
 
- TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT
 
- TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT
 
- TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT
 
- TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT
 
- TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT
 
- TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_ACP_INDEX_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_ACP_INDEX__SHIFT
 
- TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_SAMU_INDEX_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_SAMU_INDEX__SHIFT
 
- TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_UVD_INDEX_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_UVD_INDEX__SHIFT
 
- TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_VCE_INDEX_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX_2__CURR_VCE_INDEX__SHIFT
 
- TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_ACP_INDEX_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_ACP_INDEX__SHIFT
 
- TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_SAMU_INDEX_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_SAMU_INDEX__SHIFT
 
- TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_UVD_INDEX_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_UVD_INDEX__SHIFT
 
- TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_VCE_INDEX_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX_2__TARG_VCE_INDEX__SHIFT
 
- TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT
 
- TARGET_AND_CURRENT_PROFILE_INDEX__CURR_ACPI_INDEX_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX__CURR_ACPI_INDEX__SHIFT
 
- TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT
 
- TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT
 
- TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT
 
- TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT
 
- TARGET_AND_CURRENT_PROFILE_INDEX__TARG_ACPI_INDEX_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX__TARG_ACPI_INDEX__SHIFT
 
- TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT
 
- TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT
 
- TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK
 
- TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT
 
- TARGET_ASSIST_EXT_EEDP_CHKREGEN_OP
 
- TARGET_ASSIST_EXT_EEDP_CHKRM_OP
 
- TARGET_ASSIST_EXT_EEDP_CHK_OP
 
- TARGET_ASSIST_EXT_EEDP_INC_PRI_APPTAG
 
- TARGET_ASSIST_EXT_EEDP_INC_PRI_REFTAG
 
- TARGET_ASSIST_EXT_EEDP_INC_SEC_APPTAG
 
- TARGET_ASSIST_EXT_EEDP_INC_SEC_REFTAG
 
- TARGET_ASSIST_EXT_EEDP_INSERT_OP
 
- TARGET_ASSIST_EXT_EEDP_MASK_OP
 
- TARGET_ASSIST_EXT_EEDP_NOOP_OP
 
- TARGET_ASSIST_EXT_EEDP_PASS_REF_TAG
 
- TARGET_ASSIST_EXT_EEDP_REPLACE_OP
 
- TARGET_ASSIST_EXT_EEDP_STRIP_OP
 
- TARGET_ASSIST_EXT_EEDP_T10_CHK_APPTAG
 
- TARGET_ASSIST_EXT_EEDP_T10_CHK_GUARD
 
- TARGET_ASSIST_EXT_EEDP_T10_CHK_MASK
 
- TARGET_ASSIST_EXT_EEDP_T10_CHK_REFTAG
 
- TARGET_ASSIST_EXT_EEDP_T10_CHK_SHIFT
 
- TARGET_ASSIST_EXT_MSGFLAGS_BIDIRECTIONAL
 
- TARGET_ASSIST_EXT_MSGFLAGS_MULTICAST
 
- TARGET_ASSIST_EXT_MSGFLAGS_SGL_OFFSET_CHAINS
 
- TARGET_ASSIST_FLAGS_AUTO_STATUS
 
- TARGET_ASSIST_FLAGS_CONFIRMED
 
- TARGET_ASSIST_FLAGS_DATA_DIRECTION
 
- TARGET_ASSIST_FLAGS_HIGH_PRIORITY
 
- TARGET_ASSIST_FLAGS_REPOST_CMD_BUFFER
 
- TARGET_AST_SKID_LIMIT
 
- TARGET_ATTRIBUTE_HELPER
 
- TARGET_BER_NOT_MET
 
- TARGET_BMISS_OFFLOAD_MAX_VDEV
 
- TARGET_BOOT_SLEEP
 
- TARGET_BUCKET_SIZE
 
- TARGET_BUSY
 
- TARGET_BUSY_T
 
- TARGET_CHANGED_ASC
 
- TARGET_CHKCOND
 
- TARGET_CHK_COND
 
- TARGET_CHNL_NUM_2G
 
- TARGET_CHNL_NUM_2G_5G
 
- TARGET_CHNL_NUM_2G_5G_8812
 
- TARGET_CHNL_NUM_5G
 
- TARGET_COMMAND_REG
 
- TARGET_CORE_ALUA_H
 
- TARGET_CORE_BACKEND_H
 
- TARGET_CORE_BASE_H
 
- TARGET_CORE_FABRIC_H
 
- TARGET_CORE_FILE_H
 
- TARGET_CORE_IBLOCK_H
 
- TARGET_CORE_INTERNAL_H
 
- TARGET_CORE_NAME_MAX_LEN
 
- TARGET_CORE_PR_H
 
- TARGET_CORE_PSCSI_H
 
- TARGET_CORE_RD_H
 
- TARGET_CORE_UA_H
 
- TARGET_CORE_VERSION
 
- TARGET_CPM2
 
- TARGET_DDR
 
- TARGET_DEVICE_AWAKE
 
- TARGET_DEVICE_PWRDN
 
- TARGET_DEVICE_PWRSAVE
 
- TARGET_DEVICE_RESUME
 
- TARGET_DEVICE_SLEEP
 
- TARGET_DEVICE_SUSPEND
 
- TARGET_DIF_CHECK_APPTAG
 
- TARGET_DIF_CHECK_GUARD
 
- TARGET_DIF_CHECK_REFTAG
 
- TARGET_DIF_TYPE0_PROT
 
- TARGET_DIF_TYPE1_PROT
 
- TARGET_DIF_TYPE2_PROT
 
- TARGET_DIF_TYPE3_PROT
 
- TARGET_DMA_BURST_SIZE
 
- TARGET_ERRNO__INVALID_UID
 
- TARGET_ERRNO__PID_OVERRIDE_CPU
 
- TARGET_ERRNO__PID_OVERRIDE_SYSTEM
 
- TARGET_ERRNO__PID_OVERRIDE_UID
 
- TARGET_ERRNO__SUCCESS
 
- TARGET_ERRNO__SYSTEM_OVERRIDE_THREAD
 
- TARGET_ERRNO__UID_OVERRIDE_CPU
 
- TARGET_ERRNO__UID_OVERRIDE_SYSTEM
 
- TARGET_ERRNO__USER_NOT_FOUND
 
- TARGET_ERR_ADDR_HI
 
- TARGET_ERR_ADDR_HI__VALUE
 
- TARGET_ERR_ADDR_LO
 
- TARGET_ERR_ADDR_LO__VALUE
 
- TARGET_FABRIC_NAME_SIZE
 
- TARGET_FRAME_INITIAL
 
- TARGET_GTK_OFFLOAD_MAX_VDEV
 
- TARGET_H
 
- TARGET_HAS_ETH1
 
- TARGET_HAS_ETH2
 
- TARGET_HAS_ETH3
 
- TARGET_HL_TLV_AST_SKID_LIMIT
 
- TARGET_HL_TLV_NUM_PEERS
 
- TARGET_HL_TLV_NUM_WDS_ENTRIES
 
- TARGET_HOTFOOT
 
- TARGET_HW_I2C_CLOCK
 
- TARGET_IDLE_COUNT
 
- TARGET_IDLE_COUNT_MASK
 
- TARGET_IDLE_COUNT_SHIFT
 
- TARGET_LINK_SPEED_MASK
 
- TARGET_LOCAL
 
- TARGET_MAC_AGGR_DELIM
 
- TARGET_MASK
 
- TARGET_MAX
 
- TARGET_MAX_FRAG_ENTRIES
 
- TARGET_MAX_N
 
- TARGET_MCAST2UCAST_MODE
 
- TARGET_MODE_ABORT_TYPE_ALL_CMD_BUFFERS
 
- TARGET_MODE_ABORT_TYPE_ALL_IO
 
- TARGET_MODE_ABORT_TYPE_EXACT_IO
 
- TARGET_MODE_ABORT_TYPE_EXACT_IO_REQUEST
 
- TARGET_MODE_REPLY_0100_MASK_HOST_INDEX
 
- TARGET_MODE_REPLY_0100_MASK_INITIATOR_INDEX
 
- TARGET_MODE_REPLY_0100_MASK_IOC_INDEX
 
- TARGET_MODE_REPLY_0100_PORT_MASK
 
- TARGET_MODE_REPLY_0100_PORT_SHIFT
 
- TARGET_MODE_REPLY_0100_SHIFT_HOST_INDEX
 
- TARGET_MODE_REPLY_0100_SHIFT_INITIATOR_INDEX
 
- TARGET_MODE_REPLY_0100_SHIFT_IOC_INDEX
 
- TARGET_MODE_REPLY_ALIAS_MASK
 
- TARGET_MODE_REPLY_ALIAS_SHIFT
 
- TARGET_MODE_REPLY_INITIATOR_INDEX_MASK
 
- TARGET_MODE_REPLY_INITIATOR_INDEX_SHIFT
 
- TARGET_MODE_REPLY_IO_INDEX_MASK
 
- TARGET_MODE_REPLY_IO_INDEX_SHIFT
 
- TARGET_MODE_REPLY_PORT_MASK
 
- TARGET_MODE_REPLY_PORT_SHIFT
 
- TARGET_MSK
 
- TARGET_NAME_MAXLEN
 
- TARGET_NUM_MCAST_GROUPS
 
- TARGET_NUM_MCAST_TABLE_ELEMS
 
- TARGET_NUM_MSDU_DESC
 
- TARGET_NUM_OFFLOAD_PEERS
 
- TARGET_NUM_OFFLOAD_REORDER_BUFS
 
- TARGET_NUM_PEERS
 
- TARGET_NUM_PEER_AST
 
- TARGET_NUM_PEER_KEYS
 
- TARGET_NUM_STATIONS
 
- TARGET_NUM_TIDS
 
- TARGET_NUM_VDEVS
 
- TARGET_NUM_WDS_ENTRIES
 
- TARGET_N_MAX
 
- TARGET_OFFSET
 
- TARGET_PERIOD
 
- TARGET_PERIOD_MASK
 
- TARGET_PERIOD_SHIFT
 
- TARGET_PPC_MPC52xx
 
- TARGET_PROFILE_INDEX_MASK
 
- TARGET_PROFILE_INDEX_SHIFT
 
- TARGET_PROT_ALL
 
- TARGET_PROT_DIN_INSERT
 
- TARGET_PROT_DIN_PASS
 
- TARGET_PROT_DIN_STRIP
 
- TARGET_PROT_DOUT_INSERT
 
- TARGET_PROT_DOUT_PASS
 
- TARGET_PROT_DOUT_STRIP
 
- TARGET_PROT_NORMAL
 
- TARGET_REACHED
 
- TARGET_REMOTE
 
- TARGET_RESET
 
- TARGET_RETRY_DISABLE
 
- TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES
 
- TARGET_ROAM_OFFLOAD_MAX_VDEV
 
- TARGET_RUNNING
 
- TARGET_RX_CHAIN_MASK
 
- TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK
 
- TARGET_RX_TIMEOUT_HI_PRI
 
- TARGET_RX_TIMEOUT_LO_PRI
 
- TARGET_SCAN_MAX_PENDING_REQS
 
- TARGET_SCF_ACK_KREF
 
- TARGET_SCF_BIDI_OP
 
- TARGET_SCF_LOOKUP_LUN_FROM_TAG
 
- TARGET_SCF_UNKNOWN_SIZE
 
- TARGET_SCF_USE_CPUID
 
- TARGET_STATE
 
- TARGET_STATE_MASK
 
- TARGET_STATE_SHIFT
 
- TARGET_STATUS_SEND_FLAGS_AUTO_GOOD_STATUS
 
- TARGET_STATUS_SEND_FLAGS_CONFIRMED
 
- TARGET_STATUS_SEND_FLAGS_HIGH_PRIORITY
 
- TARGET_STATUS_SEND_FLAGS_REPOST_CMD_BUFFER
 
- TARGET_STILL_ACTIVE
 
- TARGET_STOP
 
- TARGET_TAG_FULL
 
- TARGET_TEMP_TO_REG
 
- TARGET_TIMEOUT
 
- TARGET_TLV_MGMT_NUM_MSDU_DESC
 
- TARGET_TLV_NUM_MSDU_DESC
 
- TARGET_TLV_NUM_MSDU_DESC_HL
 
- TARGET_TLV_NUM_PEERS
 
- TARGET_TLV_NUM_STATIONS
 
- TARGET_TLV_NUM_TDLS_VDEVS
 
- TARGET_TLV_NUM_TIDS
 
- TARGET_TLV_NUM_VDEVS
 
- TARGET_TLV_NUM_WOW_PATTERNS
 
- TARGET_TX_CHAIN_MASK
 
- TARGET_TX_DBG_LOG_SIZE
 
- TARGET_TYPE_AR6003
 
- TARGET_TYPE_AR6004
 
- TARGET_VERSION_SENTINAL
 
- TARGET_VOW_CONFIG
 
- TARGET_WIDTH_32
 
- TARGET_WIDTH_64
 
- TARG_CMD_COMPLETE
 
- TARG_CONN_STATE_CLEANUP_WAIT
 
- TARG_CONN_STATE_FREE
 
- TARG_CONN_STATE_IN_LOGIN
 
- TARG_CONN_STATE_IN_LOGOUT
 
- TARG_CONN_STATE_LOGGED_IN
 
- TARG_CONN_STATE_LOGOUT_REQUESTED
 
- TARG_CONN_STATE_XPT_UP
 
- TARG_INDEX
 
- TARG_INDEX_MASK
 
- TARG_INDEX_SHIFT
 
- TARG_SCLK_INDEX
 
- TARG_SCLK_INDEX_MASK
 
- TARG_SCLK_INDEX_SHIFT
 
- TARG_SESS_STATE_ACTIVE
 
- TARG_SESS_STATE_FAILED
 
- TARG_SESS_STATE_FREE
 
- TARG_SESS_STATE_IN_CONTINUE
 
- TARG_SESS_STATE_LOGGED_IN
 
- TARG_VTOP
 
- TARL
 
- TARTAGPERR_F
 
- TARTAGPERR_S
 
- TARTAGPERR_V
 
- TARU
 
- TARVID_MASK
 
- TAR_1
 
- TAR_2
 
- TAR_3
 
- TAR_4
 
- TAR_5
 
- TAR_ALLOW_DISC
 
- TAR_RESET
 
- TAR_SW_BITS
 
- TAR_SYNC_MASK
 
- TAR_TAG_Q_MASK
 
- TAR_VALID
 
- TAR_WIDE_MASK
 
- TAS2552_ANALOG_IN_SEL
 
- TAS2552_APT_DELAY_125
 
- TAS2552_APT_DELAY_200
 
- TAS2552_APT_DELAY_50
 
- TAS2552_APT_DELAY_75
 
- TAS2552_APT_EN
 
- TAS2552_APT_THRESH_05_02
 
- TAS2552_APT_THRESH_10_07
 
- TAS2552_APT_THRESH_14_11
 
- TAS2552_APT_THRESH_20_17
 
- TAS2552_BCLKDIR
 
- TAS2552_BOOST_APT_CTRL
 
- TAS2552_BOOST_EN
 
- TAS2552_BTIP
 
- TAS2552_BTS_CTRL
 
- TAS2552_CFG_1
 
- TAS2552_CFG_2
 
- TAS2552_CFG_3
 
- TAS2552_CLASSD_EN
 
- TAS2552_CLKSPERFRAME_128
 
- TAS2552_CLKSPERFRAME_256
 
- TAS2552_CLKSPERFRAME_32
 
- TAS2552_CLKSPERFRAME_64
 
- TAS2552_CLKSPERFRAME_MASK
 
- TAS2552_CLK_TARGET_MASK
 
- TAS2552_DAI_FMT_MASK
 
- TAS2552_DATAFORMAT_DSP
 
- TAS2552_DATAFORMAT_I2S
 
- TAS2552_DATAFORMAT_LEFT_J
 
- TAS2552_DATAFORMAT_MASK
 
- TAS2552_DATAFORMAT_RIGHT_J
 
- TAS2552_DATA_OUT_DISABLED
 
- TAS2552_DATA_OUT_IV_DATA
 
- TAS2552_DATA_OUT_I_DATA
 
- TAS2552_DATA_OUT_PGA_GAIN
 
- TAS2552_DATA_OUT_VBAT_DATA
 
- TAS2552_DATA_OUT_VBAT_VBOOST_GAIN
 
- TAS2552_DATA_OUT_VBOOST_DATA
 
- TAS2552_DATA_OUT_V_DATA
 
- TAS2552_DEVICE_STATUS
 
- TAS2552_DEV_RESET
 
- TAS2552_DIN_SRC_SEL_AVG_L_R
 
- TAS2552_DIN_SRC_SEL_LEFT
 
- TAS2552_DIN_SRC_SEL_MUTED
 
- TAS2552_DIN_SRC_SEL_RIGHT
 
- TAS2552_DOUT
 
- TAS2552_EDGE_RATE_CTRL
 
- TAS2552_FORMATS
 
- TAS2552_I2S_OUT_SEL
 
- TAS2552_IVSENSE_EN
 
- TAS2552_LIMIT_INT_COUNT
 
- TAS2552_LIMIT_RATE_HYS
 
- TAS2552_LIMIT_RELEASE
 
- TAS2552_LIM_EN
 
- TAS2552_L_DATA_OUT
 
- TAS2552_MAX_REG
 
- TAS2552_MUTE
 
- TAS2552_NUM_SUPPLIES
 
- TAS2552_OUTPUT_DATA
 
- TAS2552_PDM_CFG
 
- TAS2552_PDM_CLK
 
- TAS2552_PDM_CLK_BCLK
 
- TAS2552_PDM_CLK_IVCLKIN
 
- TAS2552_PDM_CLK_MCLK
 
- TAS2552_PDM_CLK_PLL
 
- TAS2552_PDM_CLK_SEL_BCLK
 
- TAS2552_PDM_CLK_SEL_IVCLKIN
 
- TAS2552_PDM_CLK_SEL_MASK
 
- TAS2552_PDM_CLK_SEL_MCLK
 
- TAS2552_PDM_CLK_SEL_PLL
 
- TAS2552_PDM_DATA_ES
 
- TAS2552_PDM_DATA_SEL_I
 
- TAS2552_PDM_DATA_SEL_I_V
 
- TAS2552_PDM_DATA_SEL_MASK
 
- TAS2552_PDM_DATA_SEL_V
 
- TAS2552_PDM_DATA_SEL_V_I
 
- TAS2552_PDM_IN_SEL
 
- TAS2552_PGA_GAIN
 
- TAS2552_PLAT_H
 
- TAS2552_PLL_BYPASS
 
- TAS2552_PLL_CLKIN
 
- TAS2552_PLL_CLKIN_1_8_FIXED
 
- TAS2552_PLL_CLKIN_BCLK
 
- TAS2552_PLL_CLKIN_IVCLKIN
 
- TAS2552_PLL_CLKIN_MCLK
 
- TAS2552_PLL_CTRL_1
 
- TAS2552_PLL_CTRL_2
 
- TAS2552_PLL_CTRL_3
 
- TAS2552_PLL_D_LOWER
 
- TAS2552_PLL_D_UPPER
 
- TAS2552_PLL_ENABLE
 
- TAS2552_PLL_J_MASK
 
- TAS2552_PLL_SRC_1_8_FIXED
 
- TAS2552_PLL_SRC_BCLK
 
- TAS2552_PLL_SRC_IVCLKIN
 
- TAS2552_PLL_SRC_MASK
 
- TAS2552_PLL_SRC_MCLK
 
- TAS2552_RESERVED_0D
 
- TAS2552_R_DATA_OUT
 
- TAS2552_SDOUT_TRISTATE
 
- TAS2552_SER_CTRL_1
 
- TAS2552_SER_CTRL_2
 
- TAS2552_SWS
 
- TAS2552_VBAT_DATA
 
- TAS2552_VER_NUM
 
- TAS2552_WCLKDIR
 
- TAS2552_WCLK_FREQ_11_12KHZ
 
- TAS2552_WCLK_FREQ_16KHZ
 
- TAS2552_WCLK_FREQ_176_192KHZ
 
- TAS2552_WCLK_FREQ_22_24KHZ
 
- TAS2552_WCLK_FREQ_32KHZ
 
- TAS2552_WCLK_FREQ_44_48KHZ
 
- TAS2552_WCLK_FREQ_88_96KHZ
 
- TAS2552_WCLK_FREQ_8KHZ
 
- TAS2552_WCLK_FREQ_MASK
 
- TAS2552_WORDLENGTH_16BIT
 
- TAS2552_WORDLENGTH_20BIT
 
- TAS2552_WORDLENGTH_24BIT
 
- TAS2552_WORDLENGTH_32BIT
 
- TAS2552_WORDLENGTH_MASK
 
- TAS3001_DRC_MAX
 
- TAS3004_BASS_MAX
 
- TAS3004_BASS_MIN
 
- TAS3004_BASS_ZERO
 
- TAS3004_DRC_MAX
 
- TAS3004_TREBLE_MAX
 
- TAS3004_TREBLE_MIN
 
- TAS3004_TREBLE_ZERO
 
- TAS5086_BKNDERR
 
- TAS5086_CHANNEL_VOL
 
- TAS5086_CLK_IDX_MCLK
 
- TAS5086_CLK_IDX_SCLK
 
- TAS5086_CLOCK_CONTROL
 
- TAS5086_CLOCK_RATE
 
- TAS5086_CLOCK_RATE_MASK
 
- TAS5086_CLOCK_RATIO
 
- TAS5086_CLOCK_RATIO_MASK
 
- TAS5086_CLOCK_SCLK_RATIO_48
 
- TAS5086_CLOCK_VALID
 
- TAS5086_DEEMPH_MASK
 
- TAS5086_DEV_ID
 
- TAS5086_ERROR_STATUS
 
- TAS5086_INPUT_MUX
 
- TAS5086_MASTER_VOL
 
- TAS5086_MAX_REGISTER
 
- TAS5086_MOD_LIMIT
 
- TAS5086_OSC_TRIM
 
- TAS5086_PCM_FORMATS
 
- TAS5086_PCM_RATES
 
- TAS5086_PWM_OUTPUT_MUX
 
- TAS5086_PWM_START
 
- TAS5086_PWM_START_CHANNEL_MASK
 
- TAS5086_PWM_START_MIDZ_FOR_START_1
 
- TAS5086_PWM_START_MIDZ_FOR_START_2
 
- TAS5086_SERIAL_DATA_IF
 
- TAS5086_SOFT_MUTE
 
- TAS5086_SOFT_MUTE_ALL
 
- TAS5086_SPLIT_CAP_CHARGE
 
- TAS5086_SURROUND
 
- TAS5086_SYS_CONTROL_1
 
- TAS5086_SYS_CONTROL_2
 
- TAS5086_VOLUME_CONTROL
 
- TAS5707_CH1_BQ0_REG
 
- TAS5707_CH1_BQ1_REG
 
- TAS5707_CH1_BQ2_REG
 
- TAS5707_CH1_BQ3_REG
 
- TAS5707_CH1_BQ4_REG
 
- TAS5707_CH1_BQ5_REG
 
- TAS5707_CH1_BQ6_REG
 
- TAS5707_CH2_BQ0_REG
 
- TAS5707_CH2_BQ1_REG
 
- TAS5707_CH2_BQ2_REG
 
- TAS5707_CH2_BQ3_REG
 
- TAS5707_CH2_BQ4_REG
 
- TAS5707_CH2_BQ5_REG
 
- TAS5707_CH2_BQ6_REG
 
- TAS5717_CH1_BQ0_REG
 
- TAS5717_CH1_BQ10_REG
 
- TAS5717_CH1_BQ11_REG
 
- TAS5717_CH1_BQ1_REG
 
- TAS5717_CH1_BQ2_REG
 
- TAS5717_CH1_BQ3_REG
 
- TAS5717_CH1_BQ4_REG
 
- TAS5717_CH1_BQ5_REG
 
- TAS5717_CH1_BQ6_REG
 
- TAS5717_CH1_BQ7_REG
 
- TAS5717_CH1_BQ8_REG
 
- TAS5717_CH1_BQ9_REG
 
- TAS5717_CH1_LEFT_CH_MIX_REG
 
- TAS5717_CH1_RIGHT_CH_MIX_REG
 
- TAS5717_CH2_BQ0_REG
 
- TAS5717_CH2_BQ10_REG
 
- TAS5717_CH2_BQ11_REG
 
- TAS5717_CH2_BQ1_REG
 
- TAS5717_CH2_BQ2_REG
 
- TAS5717_CH2_BQ3_REG
 
- TAS5717_CH2_BQ4_REG
 
- TAS5717_CH2_BQ5_REG
 
- TAS5717_CH2_BQ6_REG
 
- TAS5717_CH2_BQ7_REG
 
- TAS5717_CH2_BQ8_REG
 
- TAS5717_CH2_BQ9_REG
 
- TAS5717_CH2_LEFT_CH_MIX_REG
 
- TAS5717_CH2_RIGHT_CH_MIX_REG
 
- TAS5717_CH3_BQ0_REG
 
- TAS5717_CH3_BQ1_REG
 
- TAS5717_CH4_BQ0_REG
 
- TAS5717_CH4_BQ1_REG
 
- TAS571X_BKND_ERR_REG
 
- TAS571X_CH1_VOL_REG
 
- TAS571X_CH2_VOL_REG
 
- TAS571X_CH3_VOL_REG
 
- TAS571X_CH4_SRC_SELECT_REG
 
- TAS571X_CLK_CTRL_REG
 
- TAS571X_DEV_ID_REG
 
- TAS571X_ERR_STATUS_REG
 
- TAS571X_IC_DELAY_CH1_REG
 
- TAS571X_IC_DELAY_CH2_REG
 
- TAS571X_IC_DELAY_CH3_REG
 
- TAS571X_IC_DELAY_CH4_REG
 
- TAS571X_INPUT_MUX_REG
 
- TAS571X_MAX_SUPPLIES
 
- TAS571X_MODULATION_LIMIT_REG
 
- TAS571X_MVOL_REG
 
- TAS571X_OSC_TRIM_REG
 
- TAS571X_PWM_CH1_SDN_MASK
 
- TAS571X_PWM_CH2_SDN_SHIFT
 
- TAS571X_PWM_CH3_SDN_SHIFT
 
- TAS571X_PWM_CH4_SDN_SHIFT
 
- TAS571X_PWM_CH_SDN_GROUP_REG
 
- TAS571X_PWM_MUX_REG
 
- TAS571X_SDI_FMT_MASK
 
- TAS571X_SDI_REG
 
- TAS571X_SOFT_MUTE_CH1_SHIFT
 
- TAS571X_SOFT_MUTE_CH2_SHIFT
 
- TAS571X_SOFT_MUTE_CH3_SHIFT
 
- TAS571X_SOFT_MUTE_REG
 
- TAS571X_START_STOP_PERIOD_REG
 
- TAS571X_SYS_CTRL_1_REG
 
- TAS571X_SYS_CTRL_2_REG
 
- TAS571X_SYS_CTRL_2_SDN_MASK
 
- TAS571X_VOL_CFG_REG
 
- TAS5720
 
- TAS5720_ANALOG_CTRL_REG
 
- TAS5720_ANALOG_GAIN_19_2DBV
 
- TAS5720_ANALOG_GAIN_20_7DBV
 
- TAS5720_ANALOG_GAIN_23_5DBV
 
- TAS5720_ANALOG_GAIN_26_3DBV
 
- TAS5720_ANALOG_GAIN_MASK
 
- TAS5720_ANALOG_GAIN_SHIFT
 
- TAS5720_CLIP1_MASK
 
- TAS5720_CLIP1_SHIFT
 
- TAS5720_CLKE
 
- TAS5720_DCE
 
- TAS5720_DEVICE_ID
 
- TAS5720_DEVICE_ID_REG
 
- TAS5720_DIGITAL_CLIP1_REG
 
- TAS5720_DIGITAL_CLIP2_REG
 
- TAS5720_DIGITAL_CTRL1_REG
 
- TAS5720_DIGITAL_CTRL2_REG
 
- TAS5720_DIG_CLIP_MASK
 
- TAS5720_FAULT_CHECK_INTERVAL
 
- TAS5720_FAULT_MASK
 
- TAS5720_FAULT_REG
 
- TAS5720_FORMATS
 
- TAS5720_HPF_BYPASS
 
- TAS5720_MAX_REG
 
- TAS5720_MUTE
 
- TAS5720_NUM_SUPPLIES
 
- TAS5720_OCE
 
- TAS5720_OC_THRESH_100PCT
 
- TAS5720_OC_THRESH_25PCT
 
- TAS5720_OC_THRESH_50PCT
 
- TAS5720_OC_THRESH_75PCT
 
- TAS5720_OC_THRESH_MASK
 
- TAS5720_OTE
 
- TAS5720_POWER_CTRL_REG
 
- TAS5720_PWM_RATE_10_5_FSYNC
 
- TAS5720_PWM_RATE_12_6_FSYNC
 
- TAS5720_PWM_RATE_14_7_FSYNC
 
- TAS5720_PWM_RATE_16_8_FSYNC
 
- TAS5720_PWM_RATE_20_10_FSYNC
 
- TAS5720_PWM_RATE_24_12_FSYNC
 
- TAS5720_PWM_RATE_6_3_FSYNC
 
- TAS5720_PWM_RATE_8_4_FSYNC
 
- TAS5720_PWM_RATE_MASK
 
- TAS5720_RATES
 
- TAS5720_SAIF_FORMAT_MASK
 
- TAS5720_SAIF_I2S
 
- TAS5720_SAIF_LEFTJ
 
- TAS5720_SAIF_RIGHTJ_16BIT
 
- TAS5720_SAIF_RIGHTJ_18BIT
 
- TAS5720_SAIF_RIGHTJ_20BIT
 
- TAS5720_SAIF_RIGHTJ_24BIT
 
- TAS5720_SDZ
 
- TAS5720_SLEEP
 
- TAS5720_SSZ_DS
 
- TAS5720_TDM_CFG_SRC
 
- TAS5720_TDM_SLOT_SEL_MASK
 
- TAS5720_VOLUME_CTRL_REG
 
- TAS5722
 
- TAS5722_ANALOG_CTRL2_REG
 
- TAS5722_AUTO_SLEEP_1024LR
 
- TAS5722_AUTO_SLEEP_262144LR
 
- TAS5722_AUTO_SLEEP_65536LR
 
- TAS5722_AUTO_SLEEP_MASK
 
- TAS5722_AUTO_SLEEP_OFF
 
- TAS5722_DEVICE_ID
 
- TAS5722_DIGITAL_CTRL2_REG
 
- TAS5722_FAULTZ_PU
 
- TAS5722_HPF_118_4HZ
 
- TAS5722_HPF_14_9HZ
 
- TAS5722_HPF_235_0HZ
 
- TAS5722_HPF_29_7HZ
 
- TAS5722_HPF_3_7HZ
 
- TAS5722_HPF_463_2HZ
 
- TAS5722_HPF_59_4HZ
 
- TAS5722_HPF_7_4HZ
 
- TAS5722_HPF_MASK
 
- TAS5722_MAX_REG
 
- TAS5722_MCLK_PIN_CFG
 
- TAS5722_PWR_TUNE
 
- TAS5722_TDM_SLOT_16B
 
- TAS5722_VOL_CONTROL_LSB
 
- TAS5722_VOL_RAMP_RATE
 
- TAS5722_VREG_LVL
 
- TAS6424_AC_DIAG_CTRL1
 
- TAS6424_AC_DIAG_CTRL2
 
- TAS6424_AC_LOAD_DIAG_REP1
 
- TAS6424_AC_LOAD_DIAG_REP2
 
- TAS6424_AC_LOAD_DIAG_REP3
 
- TAS6424_AC_LOAD_DIAG_REP4
 
- TAS6424_ALL_STATE_DIAG
 
- TAS6424_ALL_STATE_HIZ
 
- TAS6424_ALL_STATE_MUTE
 
- TAS6424_ALL_STATE_PLAY
 
- TAS6424_CBC_STAT
 
- TAS6424_CH1_STATE_DIAG
 
- TAS6424_CH1_STATE_HIZ
 
- TAS6424_CH1_STATE_MASK
 
- TAS6424_CH1_STATE_MUTE
 
- TAS6424_CH1_STATE_PLAY
 
- TAS6424_CH1_VOL_CTRL
 
- TAS6424_CH2_STATE_DIAG
 
- TAS6424_CH2_STATE_HIZ
 
- TAS6424_CH2_STATE_MASK
 
- TAS6424_CH2_STATE_MUTE
 
- TAS6424_CH2_STATE_PLAY
 
- TAS6424_CH2_VOL_CTRL
 
- TAS6424_CH3_STATE_DIAG
 
- TAS6424_CH3_STATE_HIZ
 
- TAS6424_CH3_STATE_MASK
 
- TAS6424_CH3_STATE_MUTE
 
- TAS6424_CH3_STATE_PLAY
 
- TAS6424_CH3_VOL_CTRL
 
- TAS6424_CH4_STATE_DIAG
 
- TAS6424_CH4_STATE_HIZ
 
- TAS6424_CH4_STATE_MASK
 
- TAS6424_CH4_STATE_MUTE
 
- TAS6424_CH4_STATE_PLAY
 
- TAS6424_CH4_VOL_CTRL
 
- TAS6424_CHANNEL_FAULT
 
- TAS6424_CHANNEL_STATE
 
- TAS6424_CH_STATE_CTRL
 
- TAS6424_CLEAR_FAULT
 
- TAS6424_CLIP_CTRL
 
- TAS6424_CLIP_WARN
 
- TAS6424_CLIP_WINDOW
 
- TAS6424_DC_DIAG_CTRL1
 
- TAS6424_DC_DIAG_CTRL2
 
- TAS6424_DC_DIAG_CTRL3
 
- TAS6424_DC_LOAD_DIAG_REP12
 
- TAS6424_DC_LOAD_DIAG_REP34
 
- TAS6424_DC_LOAD_DIAG_REPLO
 
- TAS6424_FAULT_CHECK_INTERVAL
 
- TAS6424_FAULT_CLOCK
 
- TAS6424_FAULT_DC_CH1
 
- TAS6424_FAULT_DC_CH2
 
- TAS6424_FAULT_DC_CH3
 
- TAS6424_FAULT_DC_CH4
 
- TAS6424_FAULT_OC_CH1
 
- TAS6424_FAULT_OC_CH2
 
- TAS6424_FAULT_OC_CH3
 
- TAS6424_FAULT_OC_CH4
 
- TAS6424_FAULT_OTSD
 
- TAS6424_FAULT_OTSD_CH1
 
- TAS6424_FAULT_OTSD_CH2
 
- TAS6424_FAULT_OTSD_CH3
 
- TAS6424_FAULT_OTSD_CH4
 
- TAS6424_FAULT_PVDD_OV
 
- TAS6424_FAULT_PVDD_UV
 
- TAS6424_FAULT_VBAT_OV
 
- TAS6424_FAULT_VBAT_UV
 
- TAS6424_FORMATS
 
- TAS6424_GLOB_FAULT1
 
- TAS6424_GLOB_FAULT2
 
- TAS6424_LDGBYPASS_MASK
 
- TAS6424_LDGBYPASS_SHIFT
 
- TAS6424_MASK_CBC_WARN
 
- TAS6424_MASK_VDD_UV
 
- TAS6424_MAX
 
- TAS6424_MISC_CTRL1
 
- TAS6424_MISC_CTRL2
 
- TAS6424_MISC_CTRL3
 
- TAS6424_MISC_CTRL4
 
- TAS6424_MODE_CTRL
 
- TAS6424_NUM_SUPPLIES
 
- TAS6424_OTSD_AUTO_RECOVERY
 
- TAS6424_PBTL_CH_SEL
 
- TAS6424_PIN_CTRL
 
- TAS6424_RATES
 
- TAS6424_RESET
 
- TAS6424_SAP_CTRL
 
- TAS6424_SAP_DSP
 
- TAS6424_SAP_FMT_MASK
 
- TAS6424_SAP_I2S
 
- TAS6424_SAP_LEFTJ
 
- TAS6424_SAP_RATE_44100
 
- TAS6424_SAP_RATE_48000
 
- TAS6424_SAP_RATE_96000
 
- TAS6424_SAP_RATE_MASK
 
- TAS6424_SAP_RIGHTJ_16
 
- TAS6424_SAP_RIGHTJ_18
 
- TAS6424_SAP_RIGHTJ_20
 
- TAS6424_SAP_RIGHTJ_24
 
- TAS6424_SAP_TDM_SLOT_LAST
 
- TAS6424_SAP_TDM_SLOT_SWAP
 
- TAS6424_SAP_TDM_SLOT_SZ_16
 
- TAS6424_WARN
 
- TAS6424_WARN_VDD_OTW
 
- TAS6424_WARN_VDD_OTW_CH1
 
- TAS6424_WARN_VDD_OTW_CH2
 
- TAS6424_WARN_VDD_OTW_CH3
 
- TAS6424_WARN_VDD_OTW_CH4
 
- TAS6424_WARN_VDD_POR
 
- TAS6424_WARN_VDD_UV
 
- TASK32_SIZE
 
- TASKFILE_48
 
- TASKFILE_IN
 
- TASKFILE_INVALID
 
- TASKFILE_IN_DMA
 
- TASKFILE_IN_DMAQ
 
- TASKFILE_IN_OUT
 
- TASKFILE_MULTI_IN
 
- TASKFILE_MULTI_OUT
 
- TASKFILE_NO_DATA
 
- TASKFILE_OUT
 
- TASKFILE_OUT_DMA
 
- TASKFILE_OUT_DMAQ
 
- TASKFILE_P_IN
 
- TASKFILE_P_IN_DMA
 
- TASKFILE_P_IN_DMAQ
 
- TASKFILE_P_OUT
 
- TASKFILE_P_OUT_DMA
 
- TASKFILE_P_OUT_DMAQ
 
- TASKLET_MAX_TIME
 
- TASKLET_MAX_TIME_JIFFIES
 
- TASKLET_SOFTIRQ
 
- TASKLET_STATE_RUN
 
- TASKLET_STATE_SCHED
 
- TASKS
 
- TASKSTATS_CMD_ATTR_DEREGISTER_CPUMASK
 
- TASKSTATS_CMD_ATTR_MAX
 
- TASKSTATS_CMD_ATTR_PID
 
- TASKSTATS_CMD_ATTR_REGISTER_CPUMASK
 
- TASKSTATS_CMD_ATTR_TGID
 
- TASKSTATS_CMD_ATTR_UNSPEC
 
- TASKSTATS_CMD_GET
 
- TASKSTATS_CMD_MAX
 
- TASKSTATS_CMD_NEW
 
- TASKSTATS_CMD_UNSPEC
 
- TASKSTATS_CPUMASK_MAXLEN
 
- TASKSTATS_GENL_NAME
 
- TASKSTATS_GENL_VERSION
 
- TASKSTATS_HAS_IO_ACCOUNTING
 
- TASKSTATS_TYPE_AGGR_PID
 
- TASKSTATS_TYPE_AGGR_TGID
 
- TASKSTATS_TYPE_MAX
 
- TASKSTATS_TYPE_NULL
 
- TASKSTATS_TYPE_PID
 
- TASKSTATS_TYPE_STATS
 
- TASKSTATS_TYPE_TGID
 
- TASKSTATS_TYPE_UNSPEC
 
- TASKSTATS_VERSION
 
- TASK_A
 
- TASK_ABORTED
 
- TASK_ABORT_FAILED
 
- TASK_ARG_INIT_CLK_TABLE
 
- TASK_ARG_INIT_MM_PWR_LOG
 
- TASK_ARG_REG_FCH
 
- TASK_ARG_REG_MMIO
 
- TASK_ARG_REG_SMCIND
 
- TASK_ARG_REG_UNB
 
- TASK_ATTRIBUTE_ACA
 
- TASK_ATTRIBUTE_HEADOFQUEUE
 
- TASK_ATTRIBUTE_ORDERED
 
- TASK_ATTRIBUTE_SIMPLE
 
- TASK_ATTR_ACA
 
- TASK_ATTR_HOQ
 
- TASK_ATTR_MASK
 
- TASK_ATTR_ORDERED
 
- TASK_ATTR_SIMPLE
 
- TASK_B
 
- TASK_COMM_LEN
 
- TASK_CONTEXT_SIZE
 
- TASK_DEAD
 
- TASK_ENABLE
 
- TASK_IDLE
 
- TASK_INTERRUPTIBLE
 
- TASK_IS_32BIT_ADDR
 
- TASK_IS_ABORTED
 
- TASK_IS_AT_LU
 
- TASK_IS_DONE
 
- TASK_IS_NOT_AT_LU
 
- TASK_KILLABLE
 
- TASK_LIST_FULL
 
- TASK_MANAGEMENT
 
- TASK_MGMT_ABORT_TASK
 
- TASK_MGMT_BUS_RESET
 
- TASK_MGMT_FAILED
 
- TASK_MGMT_LUN_RESET
 
- TASK_MGMT_TARGET_RESET
 
- TASK_MOVE_GROUP
 
- TASK_NEW
 
- TASK_NOLOAD
 
- TASK_NORMAL
 
- TASK_ON_RQ_MIGRATING
 
- TASK_ON_RQ_QUEUED
 
- TASK_PARKED
 
- TASK_PFA_CLEAR
 
- TASK_PFA_SET
 
- TASK_PFA_TEST
 
- TASK_PRIO_MASK
 
- TASK_REGOFF
 
- TASK_REPORT
 
- TASK_REPORT_IDLE
 
- TASK_REPORT_MAX
 
- TASK_REQ_UPIU_SIZE_DWORDS
 
- TASK_RETRY
 
- TASK_RSP_UPIU_SIZE_DWORDS
 
- TASK_RSS_EVENTS_THRESH
 
- TASK_RUNNING
 
- TASK_SCC_0
 
- TASK_SCC_1
 
- TASK_SCC_2
 
- TASK_SCC_3
 
- TASK_SEGMENTS
 
- TASK_SEGMENT_VF
 
- TASK_SET_GROUP
 
- TASK_SIZE
 
- TASK_SIZE32
 
- TASK_SIZE64
 
- TASK_SIZE_128TB
 
- TASK_SIZE_1PB
 
- TASK_SIZE_26
 
- TASK_SIZE_2PB
 
- TASK_SIZE_32
 
- TASK_SIZE_4PB
 
- TASK_SIZE_512TB
 
- TASK_SIZE_64
 
- TASK_SIZE_64TB
 
- TASK_SIZE_LOW
 
- TASK_SIZE_MAX
 
- TASK_SIZE_OF
 
- TASK_SIZE_USER32
 
- TASK_SIZE_USER64
 
- TASK_SLICE_ARRAY_SZ
 
- TASK_STATE_ARMED
 
- TASK_STATE_BUSY
 
- TASK_STATE_MAX
 
- TASK_STATE_START
 
- TASK_STATE_TO_CHAR_STR
 
- TASK_STAT_ACTIVE
 
- TASK_STAT_IDLE
 
- TASK_STAT_WAIT4READY
 
- TASK_STOPPED
 
- TASK_SWITCH_CALL
 
- TASK_SWITCH_GATE
 
- TASK_SWITCH_IRET
 
- TASK_SWITCH_JMP
 
- TASK_TAG_ORDERED
 
- TASK_TAG_QUEUE_HEAD
 
- TASK_TAG_SIMPLE
 
- TASK_TIMEOUT
 
- TASK_TOMBSTONE
 
- TASK_TRACED
 
- TASK_TYPE_INITIALIZE
 
- TASK_TYPE_NO_ACTION
 
- TASK_TYPE_REG_LOAD
 
- TASK_TYPE_REG_SAVE
 
- TASK_TYPE_UCODE_LOAD
 
- TASK_TYPE_UCODE_SAVE
 
- TASK_UNINTERRUPTIBLE
 
- TASK_UNMAPPED_ALIGN
 
- TASK_UNMAPPED_BASE
 
- TASK_UNMAPPED_BASE_USER32
 
- TASK_UNMAPPED_BASE_USER64
 
- TASK_USER_PRIO
 
- TASK_WAKEKILL
 
- TASK_WAKING
 
- TAS_ACR_ANALOG_PDOWN
 
- TAS_ACR_B_MONAUREAL
 
- TAS_ACR_B_MON_SEL_RIGHT
 
- TAS_ACR_DEEMPH_44KHz
 
- TAS_ACR_DEEMPH_48KHz
 
- TAS_ACR_DEEMPH_MASK
 
- TAS_ACR_DEEMPH_OFF
 
- TAS_ACR_INPUT_B
 
- TAS_BUFFER_FNS
 
- TAS_I2C_ADDR
 
- TAS_MCS2_ALLPASS
 
- TAS_MCS_FASTLOAD
 
- TAS_MCS_SCLK64
 
- TAS_MCS_SPORT_MODE_I2S
 
- TAS_MCS_SPORT_MODE_LJ
 
- TAS_MCS_SPORT_MODE_MASK
 
- TAS_MCS_SPORT_MODE_RJ
 
- TAS_MCS_SPORT_WL_16BIT
 
- TAS_MCS_SPORT_WL_18BIT
 
- TAS_MCS_SPORT_WL_20BIT
 
- TAS_MCS_SPORT_WL_24BIT
 
- TAS_MCS_SPORT_WL_MASK
 
- TAS_NINO_FNS
 
- TAS_REG_ACR
 
- TAS_REG_ACS
 
- TAS_REG_BASS
 
- TAS_REG_DRC
 
- TAS_REG_INPUT1
 
- TAS_REG_INPUT2
 
- TAS_REG_LEFT_BIQUAD6
 
- TAS_REG_LEFT_LOUDNESS
 
- TAS_REG_LEFT_LOUDNESS_GAIN
 
- TAS_REG_LMIX
 
- TAS_REG_MCS
 
- TAS_REG_MCS2
 
- TAS_REG_PCM
 
- TAS_REG_RIGHT_BIQUAD6
 
- TAS_REG_RIGHT_LOUDNESS
 
- TAS_REG_RIGHT_LOUDNESS_GAIN
 
- TAS_REG_RMIX
 
- TAS_REG_TREBLE
 
- TAS_REG_VOL
 
- TAT_CHARS
 
- TAT_COLOR
 
- TAT_EXTHI
 
- TAT_FIELD
 
- TAT_RESET
 
- TAT_TRANS
 
- TAUException
 
- TAUROS3_AUX2_CTRL
 
- TAUROS3_AUX2_CTRL_LINEFILL_BURST8_EN
 
- TAUROS3_CLEAN_ALL
 
- TAUROS3_EVENT_CNT2_CFG
 
- TAUROS3_EVENT_CNT2_VAL
 
- TAUROS3_INV_ALL
 
- TAUSWORTHE
 
- TAU_init
 
- TAU_init_smp
 
- TAUupdate
 
- TAVOR
 
- TAVOREVB_ETH_PHYS
 
- TAX_BLINK
 
- TAX_RESET
 
- TAX_REVER
 
- TAX_SG_IN
 
- TAX_SG_OUT
 
- TAX_UNDER
 
- TAX_X_ABT
 
- TAX_X_CLR_FIFO
 
- TAX_X_FORC
 
- TAX_X_IN
 
- TAX_X_OUT
 
- TA_AIDL_BDIS
 
- TA_AUTHENTICATION
 
- TA_BASE_ADDR
 
- TA_BC_BASE_ADDR_HI__ADDRESS_MASK
 
- TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT
 
- TA_BC_BASE_ADDR__ADDRESS_MASK
 
- TA_BC_BASE_ADDR__ADDRESS__SHIFT
 
- TA_BIDL_ADIS
 
- TA_BUSY
 
- TA_CACHE_CORE_NPS
 
- TA_CACHE_DYNAMIC_ACLS
 
- TA_CGTT_CTRL__OFF_HYSTERESIS_MASK
 
- TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT
 
- TA_CGTT_CTRL__ON_DELAY_MASK
 
- TA_CGTT_CTRL__ON_DELAY__SHIFT
 
- TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK
 
- TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT
 
- TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK
 
- TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT
 
- TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK
 
- TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT
 
- TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK
 
- TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT
 
- TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK
 
- TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT
 
- TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK
 
- TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT
 
- TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK
 
- TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT
 
- TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK
 
- TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT
 
- TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK
 
- TA_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT
 
- TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK
 
- TA_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT
 
- TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK
 
- TA_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT
 
- TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK
 
- TA_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT
 
- TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK
 
- TA_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT
 
- TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK
 
- TA_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT
 
- TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK
 
- TA_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT
 
- TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK
 
- TA_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT
 
- TA_CMD_GET_ENTROPY
 
- TA_CMD_GET_RNG_INFO
 
- TA_CNTL_AUX
 
- TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK
 
- TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT
 
- TA_CNTL_AUX__ANISO_HALF_THRESH_MASK
 
- TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT
 
- TA_CNTL_AUX__ANISO_MAG_STEP_CLAMP_MASK
 
- TA_CNTL_AUX__ANISO_MAG_STEP_CLAMP__SHIFT
 
- TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK
 
- TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT
 
- TA_CNTL_AUX__ANISO_RATIO_LUT_MASK
 
- TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT
 
- TA_CNTL_AUX__ANISO_STEP_MASK
 
- TA_CNTL_AUX__ANISO_STEP_ORDER_MASK
 
- TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT
 
- TA_CNTL_AUX__ANISO_STEP__SHIFT
 
- TA_CNTL_AUX__ANISO_TAP_MASK
 
- TA_CNTL_AUX__ANISO_TAP__SHIFT
 
- TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK
 
- TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT
 
- TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK
 
- TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT
 
- TA_CNTL_AUX__AUTO_ALIGN_FORMAT_MASK
 
- TA_CNTL_AUX__AUTO_ALIGN_FORMAT__SHIFT
 
- TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK
 
- TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT
 
- TA_CNTL_AUX__D16_PACK_DISABLE_MASK
 
- TA_CNTL_AUX__D16_PACK_DISABLE__SHIFT
 
- TA_CNTL_AUX__DERIV_ADJUST_DIS_MASK
 
- TA_CNTL_AUX__DERIV_ADJUST_DIS__SHIFT
 
- TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK
 
- TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT
 
- TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK
 
- TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT
 
- TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK
 
- TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT
 
- TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK
 
- TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT
 
- TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK
 
- TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT
 
- TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK
 
- TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT
 
- TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK
 
- TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT
 
- TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE_MASK
 
- TA_CNTL_AUX__DISABLE_DWORD_X2_COALESCE__SHIFT
 
- TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK
 
- TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT
 
- TA_CNTL_AUX__GATHERH_DST_SEL_MASK
 
- TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT
 
- TA_CNTL_AUX__MINMAG_UNNORM_MASK
 
- TA_CNTL_AUX__MINMAG_UNNORM__SHIFT
 
- TA_CNTL_AUX__NONIMG_ANISO_BYPASS_MASK
 
- TA_CNTL_AUX__NONIMG_ANISO_BYPASS__SHIFT
 
- TA_CNTL_AUX__RESERVED_MASK
 
- TA_CNTL_AUX__RESERVED__SHIFT
 
- TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK
 
- TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT
 
- TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK
 
- TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT
 
- TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK
 
- TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT
 
- TA_CNTL__ALIGNER_CREDIT_MASK
 
- TA_CNTL__ALIGNER_CREDIT__SHIFT
 
- TA_CNTL__FX_XNACK_CREDIT_MASK
 
- TA_CNTL__FX_XNACK_CREDIT__SHIFT
 
- TA_CNTL__SQ_XNACK_CREDIT_MASK
 
- TA_CNTL__SQ_XNACK_CREDIT__SHIFT
 
- TA_CNTL__TC_DATA_CREDIT_MASK
 
- TA_CNTL__TC_DATA_CREDIT__SHIFT
 
- TA_CNTL__TD_FIFO_CREDIT_MASK
 
- TA_CNTL__TD_FIFO_CREDIT__SHIFT
 
- TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO
 
- TA_COMMAND_XGMI__GET_HIVE_ID
 
- TA_COMMAND_XGMI__GET_NODE_ID
 
- TA_COMMAND_XGMI__INITIALIZE
 
- TA_COMMAND_XGMI__SET_TOPOLOGY_INFO
 
- TA_CONFIRM_TYPE
 
- TA_CS0EN_MASK
 
- TA_CS0EN_SHIFT
 
- TA_CS1EN_MASK
 
- TA_CS1EN_SHIFT
 
- TA_CS_BC_BASE_ADDR
 
- TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK
 
- TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT
 
- TA_CS_BC_BASE_ADDR__ADDRESS_MASK
 
- TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT
 
- TA_CTL_BUSY
 
- TA_CTL_ENABLE
 
- TA_CTL_START
 
- TA_CTL_WRITE
 
- TA_DEBUG_DATA__DATA_MASK
 
- TA_DEBUG_DATA__DATA__SHIFT
 
- TA_DEBUG_INDEX__INDEX_MASK
 
- TA_DEBUG_INDEX__INDEX__SHIFT
 
- TA_DEFAULT_CMDSN_DEPTH
 
- TA_DEFAULT_CMDSN_DEPTH_MAX
 
- TA_DEFAULT_CMDSN_DEPTH_MIN
 
- TA_DEFAULT_ERL
 
- TA_DEFAULT_FABRIC_PROT_TYPE
 
- TA_DEFAULT_LOGIN_KEYS_WORKAROUND
 
- TA_DEFAULT_T10_PI
 
- TA_DEFAULT_TPG_ENABLED_SENDTARGETS
 
- TA_DEMO_MODE_DISCOVERY
 
- TA_DEMO_MODE_WRITE_PROTECT
 
- TA_DEVCNT_MASK
 
- TA_DEVCNT_SHIFT
 
- TA_DEVWDT_MASK
 
- TA_DEVWDT_SHIFT
 
- TA_EDC_CNT__TA_FL_LFIFO_SED_COUNT_MASK
 
- TA_EDC_CNT__TA_FL_LFIFO_SED_COUNT__SHIFT
 
- TA_EDC_CNT__TA_FS_AFIFO_SED_COUNT_MASK
 
- TA_EDC_CNT__TA_FS_AFIFO_SED_COUNT__SHIFT
 
- TA_EDC_CNT__TA_FS_CFIFO_SED_COUNT_MASK
 
- TA_EDC_CNT__TA_FS_CFIFO_SED_COUNT__SHIFT
 
- TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT_MASK
 
- TA_EDC_CNT__TA_FS_DFIFO_DED_COUNT__SHIFT
 
- TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT_MASK
 
- TA_EDC_CNT__TA_FS_DFIFO_SEC_COUNT__SHIFT
 
- TA_EDC_CNT__TA_FX_LFIFO_SED_COUNT_MASK
 
- TA_EDC_CNT__TA_FX_LFIFO_SED_COUNT__SHIFT
 
- TA_GENERATE_NODE_ACLS
 
- TA_GET
 
- TA_GET_MASK
 
- TA_GET_OVERRIDE
 
- TA_GET_SHIFT
 
- TA_GO
 
- TA_GO_MASK
 
- TA_GO_OVERRIDE
 
- TA_GO_SHIFT
 
- TA_HOLD_THREAD_REG
 
- TA_HOLD_THREAD_VALUE
 
- TA_I_T_NEXUS_LOSS
 
- TA_LL_MASK
 
- TA_LL_SHIFT
 
- TA_LOGIN_TIMEOUT
 
- TA_LOGIN_TIMEOUT_MAX
 
- TA_LOGIN_TIMEOUT_MIN
 
- TA_MASK
 
- TA_MAX
 
- TA_NETIF_TIMEOUT
 
- TA_NETIF_TIMEOUT_MAX
 
- TA_NETIF_TIMEOUT_MIN
 
- TA_NUM_BLOCK_MAX
 
- TA_ON_REQ
 
- TA_PAYLOAD
 
- TA_PC_ZERO
 
- TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK
 
- TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT
 
- TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK
 
- TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT
 
- TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK
 
- TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT
 
- TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK
 
- TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT
 
- TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK
 
- TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT
 
- TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK
 
- TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT
 
- TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK
 
- TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT
 
- TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK
 
- TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT
 
- TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK
 
- TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT
 
- TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK
 
- TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT
 
- TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK
 
- TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT
 
- TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK
 
- TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT
 
- TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK
 
- TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT
 
- TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK
 
- TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT
 
- TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK
 
- TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT
 
- TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK
 
- TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT
 
- TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK
 
- TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT
 
- TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK
 
- TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT
 
- TA_PERFCOUNT_SEL
 
- TA_PERF_SEL_NULL
 
- TA_PERF_SEL_RESERVED_15
 
- TA_PERF_SEL_RESERVED_28
 
- TA_PERF_SEL_RESERVED_29
 
- TA_PERF_SEL_RESERVED_41
 
- TA_PERF_SEL_RESERVED_42
 
- TA_PERF_SEL_RESERVED_43
 
- TA_PERF_SEL_addr_stalled_by_tc_cycles
 
- TA_PERF_SEL_addr_stalled_by_td_cycles
 
- TA_PERF_SEL_addresser_busy
 
- TA_PERF_SEL_addresser_fifo_busy
 
- TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles
 
- TA_PERF_SEL_addresser_stalled_cycles
 
- TA_PERF_SEL_aligner_busy
 
- TA_PERF_SEL_aligner_cycles
 
- TA_PERF_SEL_aniso_10_cycle_quads
 
- TA_PERF_SEL_aniso_12_cycle_quads
 
- TA_PERF_SEL_aniso_14_cycle_quads
 
- TA_PERF_SEL_aniso_16_cycle_quads
 
- TA_PERF_SEL_aniso_1_cycle_quads
 
- TA_PERF_SEL_aniso_2_cycle_quads
 
- TA_PERF_SEL_aniso_4_cycle_quads
 
- TA_PERF_SEL_aniso_6_cycle_quads
 
- TA_PERF_SEL_aniso_8_cycle_quads
 
- TA_PERF_SEL_aniso_gt1_cycle_quads
 
- TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles
 
- TA_PERF_SEL_aniso_stalled_cycles
 
- TA_PERF_SEL_bilin_point_1_cycle_pixels
 
- TA_PERF_SEL_buffer_atomic_wavefronts
 
- TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles
 
- TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles
 
- TA_PERF_SEL_buffer_coalescable_wavefronts
 
- TA_PERF_SEL_buffer_coalesced_read_cycles
 
- TA_PERF_SEL_buffer_coalesced_write_cycles
 
- TA_PERF_SEL_buffer_read_wavefronts
 
- TA_PERF_SEL_buffer_total_cycles
 
- TA_PERF_SEL_buffer_wavefronts
 
- TA_PERF_SEL_buffer_write_wavefronts
 
- TA_PERF_SEL_color_1_cycle_pixels
 
- TA_PERF_SEL_color_2_cycle_pixels
 
- TA_PERF_SEL_color_3_cycle_pixels
 
- TA_PERF_SEL_color_4_cycle_pixels
 
- TA_PERF_SEL_data_stalled_by_tc_cycles
 
- TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles
 
- TA_PERF_SEL_deriv_stalled_cycles
 
- TA_PERF_SEL_first_xnack_on_phase0
 
- TA_PERF_SEL_first_xnack_on_phase1
 
- TA_PERF_SEL_first_xnack_on_phase2
 
- TA_PERF_SEL_first_xnack_on_phase3
 
- TA_PERF_SEL_flat_atomic_wavefronts
 
- TA_PERF_SEL_flat_coalesceable_wavefronts
 
- TA_PERF_SEL_flat_read_wavefronts
 
- TA_PERF_SEL_flat_wavefronts
 
- TA_PERF_SEL_flat_write_wavefronts
 
- TA_PERF_SEL_gradient_busy
 
- TA_PERF_SEL_gradient_cycles
 
- TA_PERF_SEL_gradient_fifo_busy
 
- TA_PERF_SEL_image_atomic_wavefronts
 
- TA_PERF_SEL_image_read_wavefronts
 
- TA_PERF_SEL_image_total_cycles
 
- TA_PERF_SEL_image_wavefronts
 
- TA_PERF_SEL_image_write_wavefronts
 
- TA_PERF_SEL_local_cg_dyn_sclk_grp0_en
 
- TA_PERF_SEL_local_cg_dyn_sclk_grp1_en
 
- TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en
 
- TA_PERF_SEL_local_cg_dyn_sclk_grp4_en
 
- TA_PERF_SEL_local_cg_dyn_sclk_grp5_en
 
- TA_PERF_SEL_lod_busy
 
- TA_PERF_SEL_lod_fifo_busy
 
- TA_PERF_SEL_mip_1_cycle_pixels
 
- TA_PERF_SEL_mip_2_cycle_pixels
 
- TA_PERF_SEL_mipmap_invalid_samples
 
- TA_PERF_SEL_mipmap_lod_0_samples
 
- TA_PERF_SEL_mipmap_lod_10_samples
 
- TA_PERF_SEL_mipmap_lod_11_samples
 
- TA_PERF_SEL_mipmap_lod_12_samples
 
- TA_PERF_SEL_mipmap_lod_13_samples
 
- TA_PERF_SEL_mipmap_lod_14_samples
 
- TA_PERF_SEL_mipmap_lod_1_samples
 
- TA_PERF_SEL_mipmap_lod_2_samples
 
- TA_PERF_SEL_mipmap_lod_3_samples
 
- TA_PERF_SEL_mipmap_lod_4_samples
 
- TA_PERF_SEL_mipmap_lod_5_samples
 
- TA_PERF_SEL_mipmap_lod_6_samples
 
- TA_PERF_SEL_mipmap_lod_7_samples
 
- TA_PERF_SEL_mipmap_lod_8_samples
 
- TA_PERF_SEL_mipmap_lod_9_samples
 
- TA_PERF_SEL_reg_sclk_vld
 
- TA_PERF_SEL_sh_fifo_addr_busy
 
- TA_PERF_SEL_sh_fifo_addr_cycles
 
- TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles
 
- TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles
 
- TA_PERF_SEL_sh_fifo_busy
 
- TA_PERF_SEL_sh_fifo_cmd_busy
 
- TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles
 
- TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles
 
- TA_PERF_SEL_sh_fifo_data_busy
 
- TA_PERF_SEL_sh_fifo_data_cycles
 
- TA_PERF_SEL_sh_fifo_data_sfifo_busy
 
- TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles
 
- TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles
 
- TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles
 
- TA_PERF_SEL_sh_fifo_data_tfifo_busy
 
- TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles
 
- TA_PERF_SEL_sp_ta_addr_cycles
 
- TA_PERF_SEL_sp_ta_data_cycles
 
- TA_PERF_SEL_sq_ta_cmd_cycles
 
- TA_PERF_SEL_ta_busy
 
- TA_PERF_SEL_ta_fa_data_state_cycles
 
- TA_PERF_SEL_ta_sh_fifo_starved
 
- TA_PERF_SEL_total_wavefronts
 
- TA_PERF_SEL_vol_1_cycle_pixels
 
- TA_PERF_SEL_vol_2_cycle_pixels
 
- TA_PERF_SEL_walker_cycles
 
- TA_PERF_SEL_write_path_busy
 
- TA_PERF_SEL_write_path_input_cycles
 
- TA_PERF_SEL_write_path_output_cycles
 
- TA_PERF_SEL_xnack_on_phase0
 
- TA_PERF_SEL_xnack_on_phase1
 
- TA_PERF_SEL_xnack_on_phase2
 
- TA_PERF_SEL_xnack_on_phase3
 
- TA_PLL_M_VAL_20
 
- TA_PLL_M_VAL_40
 
- TA_PLL_N_VAL_20
 
- TA_PLL_N_VAL_40
 
- TA_PLL_P_VAL_20
 
- TA_PLL_P_VAL_40
 
- TA_POWER_CNTL__NOSAMPLER_CLK_EN_MODE_MASK
 
- TA_POWER_CNTL__NOSAMPLER_CLK_EN_MODE__SHIFT
 
- TA_POWER_CNTL__NOSAMPLER_CLK_VALID_DELAY_MASK
 
- TA_POWER_CNTL__NOSAMPLER_CLK_VALID_DELAY__SHIFT
 
- TA_POWER_CNTL__SAMPLER_CLK_EN_MODE_MASK
 
- TA_POWER_CNTL__SAMPLER_CLK_EN_MODE__SHIFT
 
- TA_POWER_CNTL__SAMPLER_CLK_VALID_DELAY_MASK
 
- TA_POWER_CNTL__SAMPLER_CLK_VALID_DELAY__SHIFT
 
- TA_PROD_MODE_WRITE_PROTECT
 
- TA_RAS_BLOCK__ATHUB
 
- TA_RAS_BLOCK__DF
 
- TA_RAS_BLOCK__FUSE
 
- TA_RAS_BLOCK__GFX
 
- TA_RAS_BLOCK__GFX_CPC_INDEX_END
 
- TA_RAS_BLOCK__GFX_CPC_INDEX_START
 
- TA_RAS_BLOCK__GFX_CPC_SCRATCH
 
- TA_RAS_BLOCK__GFX_CPC_UCODE
 
- TA_RAS_BLOCK__GFX_CPF_INDEX_END
 
- TA_RAS_BLOCK__GFX_CPF_INDEX_START
 
- TA_RAS_BLOCK__GFX_CPF_ROQ_ME1
 
- TA_RAS_BLOCK__GFX_CPF_ROQ_ME2
 
- TA_RAS_BLOCK__GFX_CPF_TAG
 
- TA_RAS_BLOCK__GFX_CPG_DMA_ROQ
 
- TA_RAS_BLOCK__GFX_CPG_DMA_TAG
 
- TA_RAS_BLOCK__GFX_CPG_INDEX_END
 
- TA_RAS_BLOCK__GFX_CPG_INDEX_START
 
- TA_RAS_BLOCK__GFX_CPG_TAG
 
- TA_RAS_BLOCK__GFX_DC_CSINVOC_ME1
 
- TA_RAS_BLOCK__GFX_DC_CSINVOC_ME2
 
- TA_RAS_BLOCK__GFX_DC_RESTORE_ME1
 
- TA_RAS_BLOCK__GFX_DC_RESTORE_ME2
 
- TA_RAS_BLOCK__GFX_DC_STATE_ME1
 
- TA_RAS_BLOCK__GFX_DC_STATE_ME2
 
- TA_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM
 
- TA_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM
 
- TA_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM
 
- TA_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM
 
- TA_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM
 
- TA_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM
 
- TA_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM
 
- TA_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM
 
- TA_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM
 
- TA_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM
 
- TA_RAS_BLOCK__GFX_EA_INDEX0_END
 
- TA_RAS_BLOCK__GFX_EA_INDEX0_START
 
- TA_RAS_BLOCK__GFX_EA_INDEX1_END
 
- TA_RAS_BLOCK__GFX_EA_INDEX1_START
 
- TA_RAS_BLOCK__GFX_EA_INDEX2_END
 
- TA_RAS_BLOCK__GFX_EA_INDEX2_START
 
- TA_RAS_BLOCK__GFX_EA_INDEX_END
 
- TA_RAS_BLOCK__GFX_EA_INDEX_START
 
- TA_RAS_BLOCK__GFX_EA_IORD_CMDMEM
 
- TA_RAS_BLOCK__GFX_EA_IOWR_CMDMEM
 
- TA_RAS_BLOCK__GFX_EA_IOWR_DATAMEM
 
- TA_RAS_BLOCK__GFX_EA_MAM_D0MEM
 
- TA_RAS_BLOCK__GFX_EA_MAM_D1MEM
 
- TA_RAS_BLOCK__GFX_EA_MAM_D2MEM
 
- TA_RAS_BLOCK__GFX_EA_MAM_D3MEM
 
- TA_RAS_BLOCK__GFX_EA_RRET_TAGMEM
 
- TA_RAS_BLOCK__GFX_EA_WRET_TAGMEM
 
- TA_RAS_BLOCK__GFX_GDS_INDEX_END
 
- TA_RAS_BLOCK__GFX_GDS_INDEX_START
 
- TA_RAS_BLOCK__GFX_GDS_INPUT_QUEUE
 
- TA_RAS_BLOCK__GFX_GDS_MEM
 
- TA_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM
 
- TA_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM
 
- TA_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM
 
- TA_RAS_BLOCK__GFX_MAX
 
- TA_RAS_BLOCK__GFX_SPI_SR_MEM
 
- TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM
 
- TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM
 
- TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO
 
- TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO
 
- TA_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM
 
- TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM
 
- TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM
 
- TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO
 
- TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO
 
- TA_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM
 
- TA_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO
 
- TA_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF
 
- TA_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO
 
- TA_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF
 
- TA_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO
 
- TA_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF
 
- TA_RAS_BLOCK__GFX_SQC_INDEX0_END
 
- TA_RAS_BLOCK__GFX_SQC_INDEX0_START
 
- TA_RAS_BLOCK__GFX_SQC_INDEX1_END
 
- TA_RAS_BLOCK__GFX_SQC_INDEX1_START
 
- TA_RAS_BLOCK__GFX_SQC_INDEX2_END
 
- TA_RAS_BLOCK__GFX_SQC_INDEX2_START
 
- TA_RAS_BLOCK__GFX_SQC_INDEX_END
 
- TA_RAS_BLOCK__GFX_SQC_INDEX_START
 
- TA_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM
 
- TA_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO
 
- TA_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM
 
- TA_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO
 
- TA_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM
 
- TA_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO
 
- TA_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM
 
- TA_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO
 
- TA_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO
 
- TA_RAS_BLOCK__GFX_SQ_INDEX_END
 
- TA_RAS_BLOCK__GFX_SQ_INDEX_START
 
- TA_RAS_BLOCK__GFX_SQ_LDS_D
 
- TA_RAS_BLOCK__GFX_SQ_LDS_I
 
- TA_RAS_BLOCK__GFX_SQ_SGPR
 
- TA_RAS_BLOCK__GFX_SQ_VGPR
 
- TA_RAS_BLOCK__GFX_TA_FL_LFIFO
 
- TA_RAS_BLOCK__GFX_TA_FS_AFIFO
 
- TA_RAS_BLOCK__GFX_TA_FS_CFIFO
 
- TA_RAS_BLOCK__GFX_TA_FS_DFIFO
 
- TA_RAS_BLOCK__GFX_TA_FX_LFIFO
 
- TA_RAS_BLOCK__GFX_TA_INDEX_END
 
- TA_RAS_BLOCK__GFX_TA_INDEX_START
 
- TA_RAS_BLOCK__GFX_TCA_HOLE_FIFO
 
- TA_RAS_BLOCK__GFX_TCA_INDEX_END
 
- TA_RAS_BLOCK__GFX_TCA_INDEX_START
 
- TA_RAS_BLOCK__GFX_TCA_REQ_FIFO
 
- TA_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER
 
- TA_RAS_BLOCK__GFX_TCC_CACHE_DATA
 
- TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1
 
- TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0
 
- TA_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1
 
- TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0
 
- TA_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1
 
- TA_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO
 
- TA_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG
 
- TA_RAS_BLOCK__GFX_TCC_INDEX0_END
 
- TA_RAS_BLOCK__GFX_TCC_INDEX0_START
 
- TA_RAS_BLOCK__GFX_TCC_INDEX1_END
 
- TA_RAS_BLOCK__GFX_TCC_INDEX1_START
 
- TA_RAS_BLOCK__GFX_TCC_INDEX2_END
 
- TA_RAS_BLOCK__GFX_TCC_INDEX2_START
 
- TA_RAS_BLOCK__GFX_TCC_INDEX3_END
 
- TA_RAS_BLOCK__GFX_TCC_INDEX3_START
 
- TA_RAS_BLOCK__GFX_TCC_INDEX4_END
 
- TA_RAS_BLOCK__GFX_TCC_INDEX4_START
 
- TA_RAS_BLOCK__GFX_TCC_INDEX_END
 
- TA_RAS_BLOCK__GFX_TCC_INDEX_START
 
- TA_RAS_BLOCK__GFX_TCC_IN_USE_DEC
 
- TA_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER
 
- TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO
 
- TA_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM
 
- TA_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG
 
- TA_RAS_BLOCK__GFX_TCC_RETURN_CONTROL
 
- TA_RAS_BLOCK__GFX_TCC_RETURN_DATA
 
- TA_RAS_BLOCK__GFX_TCC_SRC_FIFO
 
- TA_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM
 
- TA_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO
 
- TA_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ
 
- TA_RAS_BLOCK__GFX_TCC_WRITE_RETURN
 
- TA_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN
 
- TA_RAS_BLOCK__GFX_TCI_WRITE_RAM
 
- TA_RAS_BLOCK__GFX_TCP_CACHE_RAM
 
- TA_RAS_BLOCK__GFX_TCP_CMD_FIFO
 
- TA_RAS_BLOCK__GFX_TCP_DB_RAM
 
- TA_RAS_BLOCK__GFX_TCP_INDEX_END
 
- TA_RAS_BLOCK__GFX_TCP_INDEX_START
 
- TA_RAS_BLOCK__GFX_TCP_LFIFO_RAM
 
- TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0
 
- TA_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1
 
- TA_RAS_BLOCK__GFX_TCP_VM_FIFO
 
- TA_RAS_BLOCK__GFX_TD_CS_FIFO
 
- TA_RAS_BLOCK__GFX_TD_INDEX_END
 
- TA_RAS_BLOCK__GFX_TD_INDEX_START
 
- TA_RAS_BLOCK__GFX_TD_SS_FIFO_HI
 
- TA_RAS_BLOCK__GFX_TD_SS_FIFO_LO
 
- TA_RAS_BLOCK__HDP
 
- TA_RAS_BLOCK__MMHUB
 
- TA_RAS_BLOCK__MP0
 
- TA_RAS_BLOCK__MP1
 
- TA_RAS_BLOCK__PCIE_BIF
 
- TA_RAS_BLOCK__SDMA
 
- TA_RAS_BLOCK__SEM
 
- TA_RAS_BLOCK__SMN
 
- TA_RAS_BLOCK__UMC
 
- TA_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK
 
- TA_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK
 
- TA_RAS_BLOCK__UTC_VML2_BANK_CACHE
 
- TA_RAS_BLOCK__UTC_VML2_WALKER
 
- TA_RAS_BLOCK__XGMI_WAFL
 
- TA_RAS_COMMAND__DISABLE_FEATURES
 
- TA_RAS_COMMAND__ENABLE_FEATURES
 
- TA_RAS_COMMAND__TRIGGER_ERROR
 
- TA_RAS_ERROR__MULTI_UNCORRECTABLE
 
- TA_RAS_ERROR__NONE
 
- TA_RAS_ERROR__PARITY
 
- TA_RAS_ERROR__POISON
 
- TA_RAS_ERROR__SINGLE_CORRECTABLE
 
- TA_RAS_STATUS__ERROR_ASD_READ_WRITE
 
- TA_RAS_STATUS__ERROR_BLOCK_DISABLED
 
- TA_RAS_STATUS__ERROR_GENERIC
 
- TA_RAS_STATUS__ERROR_INJECTION_FAILED
 
- TA_RAS_STATUS__ERROR_INVALID_PARAMETER
 
- TA_RAS_STATUS__ERROR_RAS_DUPLICATE_CMD
 
- TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE
 
- TA_RAS_STATUS__ERROR_TIMEOUT
 
- TA_RAS_STATUS__ERROR_TOGGLE_DF_CSTATE
 
- TA_RAS_STATUS__RESET_NEEDED
 
- TA_RAS_STATUS__SUCCESS
 
- TA_READY_INPUT_ENABLE
 
- TA_REFINTERVAL_MASK
 
- TA_REFINTERVAL_SHIFT
 
- TA_RELEASE_THREAD_REG
 
- TA_RELEASE_THREAD_VALUE
 
- TA_RESERVED_010C__Unused_MASK
 
- TA_RESERVED_010C__Unused__SHIFT
 
- TA_RTA
 
- TA_SCRATCH__SCRATCH_MASK
 
- TA_SCRATCH__SCRATCH__SHIFT
 
- TA_SET
 
- TA_SFEXITEN_MASK
 
- TA_SFEXITEN_SHIFT
 
- TA_SHIFT
 
- TA_SIZE
 
- TA_SOFT_RESET_REG
 
- TA_SOFT_RST_CLR
 
- TA_SOFT_RST_SET
 
- TA_STATUS__AL_BUSY_MASK
 
- TA_STATUS__AL_BUSY__SHIFT
 
- TA_STATUS__BUSY_MASK
 
- TA_STATUS__BUSY__SHIFT
 
- TA_STATUS__FA_BUSY_MASK
 
- TA_STATUS__FA_BUSY__SHIFT
 
- TA_STATUS__FA_LFIFO_EMPTYB_MASK
 
- TA_STATUS__FA_LFIFO_EMPTYB__SHIFT
 
- TA_STATUS__FA_PFIFO_EMPTYB_MASK
 
- TA_STATUS__FA_PFIFO_EMPTYB__SHIFT
 
- TA_STATUS__FA_SFIFO_EMPTYB_MASK
 
- TA_STATUS__FA_SFIFO_EMPTYB__SHIFT
 
- TA_STATUS__FG_BUSY_MASK
 
- TA_STATUS__FG_BUSY__SHIFT
 
- TA_STATUS__FG_LFIFO_EMPTYB_MASK
 
- TA_STATUS__FG_LFIFO_EMPTYB__SHIFT
 
- TA_STATUS__FG_PFIFO_EMPTYB_MASK
 
- TA_STATUS__FG_PFIFO_EMPTYB__SHIFT
 
- TA_STATUS__FG_SFIFO_EMPTYB_MASK
 
- TA_STATUS__FG_SFIFO_EMPTYB__SHIFT
 
- TA_STATUS__FL_BUSY_MASK
 
- TA_STATUS__FL_BUSY__SHIFT
 
- TA_STATUS__FL_LFIFO_EMPTYB_MASK
 
- TA_STATUS__FL_LFIFO_EMPTYB__SHIFT
 
- TA_STATUS__FL_PFIFO_EMPTYB_MASK
 
- TA_STATUS__FL_PFIFO_EMPTYB__SHIFT
 
- TA_STATUS__FL_SFIFO_EMPTYB_MASK
 
- TA_STATUS__FL_SFIFO_EMPTYB__SHIFT
 
- TA_STATUS__IN_BUSY_MASK
 
- TA_STATUS__IN_BUSY__SHIFT
 
- TA_STATUS__LA_BUSY_MASK
 
- TA_STATUS__LA_BUSY__SHIFT
 
- TA_STATUS__TA_BUSY_MASK
 
- TA_STATUS__TA_BUSY__SHIFT
 
- TA_SURE
 
- TA_SURE_MASK
 
- TA_SURE_OVERRIDE
 
- TA_SURE_SHIFT
 
- TA_SYS_MASK
 
- TA_SYS_SHIFT
 
- TA_TC_ADDR_MODES
 
- TA_TC_ADDR_MODE_BORDER_COLOR
 
- TA_TC_ADDR_MODE_COMP0
 
- TA_TC_ADDR_MODE_COMP1
 
- TA_TC_ADDR_MODE_COMP2
 
- TA_TC_ADDR_MODE_COMP3
 
- TA_TC_ADDR_MODE_DEFAULT
 
- TA_TC_ADDR_MODE_UNALIGNED
 
- TA_TC_REQ_MODES
 
- TA_TC_REQ_MODE_BORDER
 
- TA_TC_REQ_MODE_BYTE
 
- TA_TC_REQ_MODE_BYTE_NV
 
- TA_TC_REQ_MODE_DWORD
 
- TA_TC_REQ_MODE_NORMAL
 
- TA_TC_REQ_MODE_TEX0
 
- TA_TC_REQ_MODE_TEX1
 
- TA_TC_REQ_MODE_TEX2
 
- TA_TH0_PC_REG
 
- TA_TIMED_OUT
 
- TA_TIMEOUT_VALUE
 
- TA_TIMEOUT_VALUE_MASK
 
- TA_TIMEOUT_VALUE_SHIFT
 
- TA_VAL
 
- TA_WAIT_BCON
 
- TA_WAIT_VFALL
 
- TA_WAIT_VRISE
 
- TA_XGMI_ASSIGNED_SDMA_ENGINE__NOT_ASSIGNED
 
- TA_XGMI_ASSIGNED_SDMA_ENGINE__SDMA0
 
- TA_XGMI_ASSIGNED_SDMA_ENGINE__SDMA1
 
- TA_XGMI_ASSIGNED_SDMA_ENGINE__SDMA2
 
- TA_XGMI_ASSIGNED_SDMA_ENGINE__SDMA3
 
- TA_XGMI_ASSIGNED_SDMA_ENGINE__SDMA4
 
- TA_XGMI_ASSIGNED_SDMA_ENGINE__SDMA5
 
- TA_XGMI_STATUS__FAILED_ID_GEN
 
- TA_XGMI_STATUS__FAILED_TOPOLOGY_INIT
 
- TA_XGMI_STATUS__GENERIC_FAILURE
 
- TA_XGMI_STATUS__INVALID_NODE_ID
 
- TA_XGMI_STATUS__INVALID_NODE_NUM
 
- TA_XGMI_STATUS__INVALID_PARAMETER
 
- TA_XGMI_STATUS__INVALID_TOPOLOGY
 
- TA_XGMI_STATUS__NOT_INITIALIZED
 
- TA_XGMI_STATUS__NULL_POINTER
 
- TA_XGMI_STATUS__SET_SHARING_ERROR
 
- TA_XGMI_STATUS__SUCCESS
 
- TA_XGMI__MAX_CONNECTED_NODES
 
- TB
 
- TB0219_DIP_SWITCH
 
- TB0219_GPIO_INPUT
 
- TB0219_GPIO_OUTPUT
 
- TB0219_LED
 
- TB0219_MISC
 
- TB0219_PCI_SLOT1_IRQ
 
- TB0219_PCI_SLOT1_IRQ_STATUS
 
- TB0219_PCI_SLOT1_PIN
 
- TB0219_PCI_SLOT2_IRQ
 
- TB0219_PCI_SLOT2_IRQ_STATUS
 
- TB0219_PCI_SLOT2_PIN
 
- TB0219_PCI_SLOT3_IRQ
 
- TB0219_PCI_SLOT3_IRQ_STATUS
 
- TB0219_PCI_SLOT3_PIN
 
- TB0219_RESET
 
- TB0219_SIZE
 
- TB0219_START
 
- TB0287_PCI_SLOT_IRQ
 
- TB0287_PCI_SLOT_PIN
 
- TB0287_RTL8110_IRQ
 
- TB0287_RTL8110_PIN
 
- TB0287_SIL680A_IRQ
 
- TB0287_SIL680A_PIN
 
- TB0287_SM501_IRQ
 
- TB0287_SM501_PIN
 
- TB10X_GPIOS
 
- TB10X_GPIO_DIR_IN
 
- TB10X_GPIO_DIR_OUT
 
- TB10X_PORT1
 
- TB10X_PORT2
 
- TB10X_PORT3
 
- TB10X_PORT4
 
- TB10X_PORT5
 
- TB10X_PORT6
 
- TB10X_PORT7
 
- TB10X_PORT8
 
- TB10X_PORT9
 
- TB10X_PORTS
 
- TB1_FWI_MASK
 
- TBAT_0D
 
- TBAT_10D
 
- TBAT_20D
 
- TBAT_30D
 
- TBAT_40D
 
- TBAT_NEG_10D
 
- TBAT_NEG_25D
 
- TBBISTDN
 
- TBBISTEN
 
- TBBISTFAIL
 
- TBCA
 
- TBCA_ADDR
 
- TBCDSTR
 
- TBCNTR
 
- TBCNTR_XM
 
- TBCNTR_XP
 
- TBCNTR_YM
 
- TBCNTR_YP
 
- TBCR
 
- TBCR_CI
 
- TBCR_TBRST
 
- TBCR_TBSB
 
- TBCR_X_FLT
 
- TBCR_Y_FLT
 
- TBCTL
 
- TBCTL_CLKDIV_MASK
 
- TBCTL_CLKDIV_SHIFT
 
- TBCTL_CTRMODE_DOWN
 
- TBCTL_CTRMODE_FREEZE
 
- TBCTL_CTRMODE_MASK
 
- TBCTL_CTRMODE_UP
 
- TBCTL_CTRMODE_UPDOWN
 
- TBCTL_FREEZE
 
- TBCTL_HSPCLKDIV_SHIFT
 
- TBCTL_PRDLD_IMDT
 
- TBCTL_PRDLD_MASK
 
- TBCTL_PRDLD_SHDW
 
- TBCTL_RESTART
 
- TBCTL_UPDATE_LOWER
 
- TBCTL_UPDATE_UPPER
 
- TBD
 
- TBDA
 
- TBD_LAST
 
- TBD_SIZE
 
- TBE
 
- TBEDA
 
- TBE_MASK
 
- TBE_SHIFT
 
- TBG_A_FBDIV
 
- TBG_A_REFDIV
 
- TBG_A_VCODIV_DIFF
 
- TBG_A_VCODIV_SE
 
- TBG_B_FBDIV
 
- TBG_B_REFDIV
 
- TBG_B_VCODIV_DIFF
 
- TBG_B_VCODIV_SE
 
- TBG_CNTRL_0_DE_EXT
 
- TBG_CNTRL_0_FRAME_DIS
 
- TBG_CNTRL_0_SYNC_MTHD
 
- TBG_CNTRL_0_SYNC_ONCE
 
- TBG_CNTRL_0_TOP_EXT
 
- TBG_CNTRL_0_TOP_SEL
 
- TBG_CNTRL_0_TOP_TGL
 
- TBG_CNTRL_1_DWIN_DIS
 
- TBG_CNTRL_1_H_EXT
 
- TBG_CNTRL_1_H_TGL
 
- TBG_CNTRL_1_TGL_EN
 
- TBG_CNTRL_1_V_EXT
 
- TBG_CNTRL_1_V_TGL
 
- TBG_CNTRL_1_X_EXT
 
- TBG_CTRL0
 
- TBG_CTRL1
 
- TBG_CTRL7
 
- TBG_CTRL8
 
- TBG_DIV_MASK
 
- TBG_SEL
 
- TBHSEL
 
- TBHSEL_MASK
 
- TBHSEL_SHIFT
 
- TBIANA_1000X
 
- TBIANA_ASYMMETRIC_PAUSE
 
- TBIANA_FULL_DUPLEX
 
- TBIANA_HALF_DUPLEX
 
- TBIANA_SETTINGS
 
- TBIANA_SGMII
 
- TBIANA_SYMMETRIC_PAUSE
 
- TBICON_AN_SENSE
 
- TBICON_CLK_SELECT
 
- TBICON_DISABLE_RX_DIS
 
- TBICON_DISABLE_TX_DIS
 
- TBICON_MI_MODE
 
- TBICON_SOFT_RESET
 
- TBICR
 
- TBICR_ANEG_ENABLE
 
- TBICR_FULL_DUPLEX
 
- TBICR_MR_AN_ENABLE
 
- TBICR_MR_RESTART_AN
 
- TBICR_PHY_RESET
 
- TBICR_RESTART_ANEG
 
- TBICR_SETTINGS
 
- TBICR_SPEED1_SET
 
- TBILinkOK
 
- TBIP_HDR_LENGTH_MASK
 
- TBIP_HDR_SN_MASK
 
- TBIP_HDR_SN_SHIFT
 
- TBIP_LOGIN
 
- TBIP_LOGIN_PROTO_VERSION
 
- TBIP_LOGIN_RESPONSE
 
- TBIP_LOGOUT
 
- TBIP_PDF_FRAME_END
 
- TBIP_PDF_FRAME_START
 
- TBIP_STATUS
 
- TBISR
 
- TBISR_LSTATUS
 
- TBISR_MR_AN_COMPLETE
 
- TBISR_MR_LINK_STATUS
 
- TBI_ACCEPT
 
- TBI_Enable
 
- TBI_INTERFACE
 
- TBKDA
 
- TBL
 
- TBLSEL
 
- TBLSEL_MASK
 
- TBLSEL_SHIFT
 
- TBL_BOOSTI
 
- TBL_BOOSTV
 
- TBL_ICHG
 
- TBL_ITERM
 
- TBL_MIN_BUCKETS
 
- TBL_SYSVMIN
 
- TBL_TREG
 
- TBL_VREG
 
- TBMU_TEST_BMU_TX_CHK_AUTO_OFF
 
- TBMU_TEST_BMU_TX_CHK_AUTO_ON
 
- TBMU_TEST_HOME_ADD_FIX_DIS
 
- TBMU_TEST_HOME_ADD_FIX_EN
 
- TBMU_TEST_HOME_ADD_PAD_FIX1_DIS
 
- TBMU_TEST_HOME_ADD_PAD_FIX1_EN
 
- TBMU_TEST_ROUTING_ADD_FIX_DIS
 
- TBMU_TEST_ROUTING_ADD_FIX_EN
 
- TBMU_TEST_TESTSTEP_DONE_IDX
 
- TBMU_TEST_TESTSTEP_REQ_NB
 
- TBMU_TEST_TESTSTEP_RPTR
 
- TBMU_TEST_TESTSTEP_RSPTR
 
- TBMU_TEST_TESTSTEP_WPTR
 
- TBMU_TEST_TESTSTEP_WSPTR
 
- TBMU_TEST_TEST_DONE_IDX_OFF
 
- TBMU_TEST_TEST_DONE_IDX_ON
 
- TBMU_TEST_TEST_REQ_NB_OFF
 
- TBMU_TEST_TEST_REQ_NB_ON
 
- TBMU_TEST_TEST_RPTR_OFF
 
- TBMU_TEST_TEST_RPTR_ON
 
- TBMU_TEST_TEST_RSPTR_OFF
 
- TBMU_TEST_TEST_RSPTR_ON
 
- TBMU_TEST_TEST_WPTR_OFF
 
- TBMU_TEST_TEST_WPTR_ON
 
- TBMU_TEST_TEST_WSPTR_OFF
 
- TBMU_TEST_TEST_WSPTR_ON
 
- TBN
 
- TBNET_FRAME_SIZE
 
- TBNET_L0_PORT_NUM
 
- TBNET_LOCAL_PATH
 
- TBNET_LOGIN_DELAY
 
- TBNET_LOGIN_RETRIES
 
- TBNET_LOGIN_TIMEOUT
 
- TBNET_LOGOUT_RETRIES
 
- TBNET_LOGOUT_TIMEOUT
 
- TBNET_MATCH_FRAGS_ID
 
- TBNET_MAX_MTU
 
- TBNET_MAX_PAYLOAD_SIZE
 
- TBNET_RING_SIZE
 
- TBNET_RX_MAX_SIZE
 
- TBNET_RX_PAGE_ORDER
 
- TBNET_RX_PAGE_SIZE
 
- TBOOT_LOG_UUID
 
- TBOOT_SERIAL_LOG_ADDR
 
- TBOOT_SERIAL_LOG_SIZE
 
- TBOOT_UUID
 
- TBPRD
 
- TBR
 
- TBRAR
 
- TBRQ_ALIGNMENT
 
- TBRQ_EOS
 
- TBRQ_MASK
 
- TBRQ_MULTIPLE
 
- TBRQ_THRESH
 
- TBRQ_TPD
 
- TBR_ID_SHIFT
 
- TBSBC
 
- TBSBC_TBSBC
 
- TBSCR_REFA
 
- TBSCR_REFAE
 
- TBSCR_REFB
 
- TBSCR_REFBE
 
- TBSCR_TBE
 
- TBSCR_TBF
 
- TBSCR_TBIRQ_MASK
 
- TBSMask
 
- TBSShift
 
- TBSVC_MATCH_PROTOCOL_ID
 
- TBSVC_MATCH_PROTOCOL_KEY
 
- TBSVC_MATCH_PROTOCOL_REVISION
 
- TBSVC_MATCH_PROTOCOL_VERSION
 
- TBSWAP_MASK
 
- TBSWAP_SHIFT
 
- TBSYNC_CAL
 
- TBSYNC_CNT
 
- TBTT_SYNC_CFG
 
- TBTT_SYNC_CFG_BCN_AIFSN
 
- TBTT_SYNC_CFG_BCN_CWMIN
 
- TBTT_SYNC_CFG_BCN_EXP_WIN
 
- TBTT_SYNC_CFG_TBTT_ADJUST
 
- TBTT_TIMER
 
- TBT_PLL_ENABLE
 
- TBU
 
- TBUF_BP_EN
 
- TBUF_BP_MC
 
- TBUF_BP_MC_V1
 
- TBUF_CONTROL
 
- TBUF_CTRL
 
- TBUF_CTRL_V1
 
- TBUF_EEE_EN
 
- TBUF_ENERGY_CTRL
 
- TBUF_FULL_THRESH_MASK
 
- TBUF_FULL_THRESH_SHIFT
 
- TBUF_MAX_PKT_THRESH_MASK
 
- TBUF_MAX_PKT_THRESH_SHIFT
 
- TBUF_PM_EN
 
- TBUF_SIZE
 
- TBUSY_SHIFT
 
- TBU_CONNECT_MODE
 
- TBU_DISCONNECT_MODE
 
- TBU_DOUTSTDCAPB_MASK
 
- TB_AIDL_BDIS
 
- TB_ASE0_BRST
 
- TB_AUTOSUSPEND_DELAY
 
- TB_A_SUSPEND
 
- TB_BUS_RESUME
 
- TB_CFG_COUNTERS
 
- TB_CFG_DEFAULT_TIMEOUT
 
- TB_CFG_ERROR_ACK_PLUG_EVENT
 
- TB_CFG_ERROR_FLOW_CONTROL_ERROR
 
- TB_CFG_ERROR_HEC_ERROR_DETECTED
 
- TB_CFG_ERROR_INVALID_CONFIG_SPACE
 
- TB_CFG_ERROR_LINK_ERROR
 
- TB_CFG_ERROR_LOOP
 
- TB_CFG_ERROR_NO_SUCH_PORT
 
- TB_CFG_ERROR_PORT_NOT_CONNECTED
 
- TB_CFG_HOPS
 
- TB_CFG_PKG_ERROR
 
- TB_CFG_PKG_EVENT
 
- TB_CFG_PKG_ICM_CMD
 
- TB_CFG_PKG_ICM_EVENT
 
- TB_CFG_PKG_ICM_RESP
 
- TB_CFG_PKG_NOTIFY_ACK
 
- TB_CFG_PKG_OVERRIDE
 
- TB_CFG_PKG_PREPARE_TO_SLEEP
 
- TB_CFG_PKG_READ
 
- TB_CFG_PKG_RESET
 
- TB_CFG_PKG_WRITE
 
- TB_CFG_PKG_XDOMAIN_REQ
 
- TB_CFG_PKG_XDOMAIN_RESP
 
- TB_CFG_PORT
 
- TB_CFG_REQUEST_ACTIVE
 
- TB_CFG_REQUEST_CANCELED
 
- TB_CFG_SWITCH
 
- TB_CIT_SETUP
 
- TB_CIT_SETUP_DRV
 
- TB_COPY_GAS
 
- TB_CTL_RETRIES
 
- TB_CTL_RX_PKG_COUNT
 
- TB_DATA_PLS
 
- TB_DATA_PLS_MAX
 
- TB_DATA_PLS_MIN
 
- TB_DMA_PATH_IN
 
- TB_DMA_PATH_OUT
 
- TB_DP_AUX_EN
 
- TB_DP_AUX_PATH_IN
 
- TB_DP_AUX_PATH_OUT
 
- TB_DP_AUX_RX_HOPID
 
- TB_DP_AUX_RX_HOPID_MASK
 
- TB_DP_AUX_RX_HOPID_SHIFT
 
- TB_DP_AUX_TX_HOPID
 
- TB_DP_AUX_TX_HOPID_MASK
 
- TB_DP_HDP
 
- TB_DP_HPDC
 
- TB_DP_LOCAL_CAP
 
- TB_DP_REMOTE_CAP
 
- TB_DP_VIDEO_EN
 
- TB_DP_VIDEO_HOPID
 
- TB_DP_VIDEO_HOPID_MASK
 
- TB_DP_VIDEO_HOPID_SHIFT
 
- TB_DP_VIDEO_PATH_OUT
 
- TB_DROM_DATA_START
 
- TB_DROM_ENTRY_GENERIC
 
- TB_DROM_ENTRY_PORT
 
- TB_EEPROM_IN
 
- TB_EEPROM_OUT
 
- TB_FRAME_SIZE
 
- TB_FULL
 
- TB_HI_N_LEN_ADDR_HI_MSK
 
- TB_HI_N_LEN_LEN_MSK
 
- TB_H_
 
- TB_KEY_SIZE
 
- TB_LC_DESC
 
- TB_LC_DESC_NLC_MASK
 
- TB_LC_DESC_PORT_SIZE_MASK
 
- TB_LC_DESC_PORT_SIZE_SHIFT
 
- TB_LC_DESC_SIZE_MASK
 
- TB_LC_DESC_SIZE_SHIFT
 
- TB_LC_FUSE
 
- TB_LC_SX_CTRL
 
- TB_LC_SX_CTRL_L1C
 
- TB_LC_SX_CTRL_L2C
 
- TB_LC_SX_CTRL_SLP
 
- TB_LC_SX_CTRL_UPSTREAM
 
- TB_LEN
 
- TB_LINKS_PER_PHY_PORT
 
- TB_MAX_CONFIG_RW_LENGTH
 
- TB_NIL
 
- TB_PATH_ALL
 
- TB_PATH_DESTINATION
 
- TB_PATH_INTERNAL
 
- TB_PATH_MAX_HOPS
 
- TB_PATH_MIN_HOPID
 
- TB_PATH_NONE
 
- TB_PATH_SOURCE
 
- TB_PCI_EN
 
- TB_PCI_HOPID
 
- TB_PCI_PATH_DOWN
 
- TB_PCI_PATH_UP
 
- TB_PORT_CAP_ADAP
 
- TB_PORT_CAP_PHY
 
- TB_PORT_CAP_TIME1
 
- TB_PORT_CAP_VSE
 
- TB_PORT_CONNECTING
 
- TB_PORT_DISABLED
 
- TB_PORT_LCA_MASK
 
- TB_PORT_LCA_SHIFT
 
- TB_PORT_MAX_CREDITS_MASK
 
- TB_PORT_MAX_CREDITS_SHIFT
 
- TB_PORT_NFC_CREDITS_MASK
 
- TB_PORT_UNPLUGGED
 
- TB_PORT_UP
 
- TB_PROPERTY_KEY_SIZE
 
- TB_PROPERTY_ROOTDIR_MAGIC
 
- TB_PROPERTY_TYPE_DATA
 
- TB_PROPERTY_TYPE_DIRECTORY
 
- TB_PROPERTY_TYPE_TEXT
 
- TB_PROPERTY_TYPE_UNKNOWN
 
- TB_PROPERTY_TYPE_VALUE
 
- TB_ROUTE_SHIFT
 
- TB_SAMPLE_SIZE
 
- TB_SE0_SRP
 
- TB_SECURITY_DPONLY
 
- TB_SECURITY_NONE
 
- TB_SECURITY_SECURE
 
- TB_SECURITY_USBONLY
 
- TB_SECURITY_USER
 
- TB_SERVICE
 
- TB_SET
 
- TB_SHIFT
 
- TB_SHUTDOWN_HALT
 
- TB_SHUTDOWN_REBOOT
 
- TB_SHUTDOWN_S3
 
- TB_SHUTDOWN_S4
 
- TB_SHUTDOWN_S5
 
- TB_SHUTDOWN_WFS
 
- TB_SRP_FAIL
 
- TB_SRP_INIT
 
- TB_SRP_WAIT
 
- TB_SSEND_SRP
 
- TB_SWITCH_CAP_VSE
 
- TB_SWITCH_KEY_SIZE
 
- TB_SWITCH_MAX_DEPTH
 
- TB_TUNNEL_DMA
 
- TB_TUNNEL_DP
 
- TB_TUNNEL_H_
 
- TB_TUNNEL_PCI
 
- TB_TYPE_DP_HDMI_IN
 
- TB_TYPE_DP_HDMI_OUT
 
- TB_TYPE_INACTIVE
 
- TB_TYPE_NHI
 
- TB_TYPE_PCIE_DOWN
 
- TB_TYPE_PCIE_UP
 
- TB_TYPE_PORT
 
- TB_VBUS_DSCHRG
 
- TB_VBUS_PLS
 
- TB_VSE_CAP_IECS
 
- TB_VSE_CAP_LINK_CONTROLLER
 
- TB_VSE_CAP_PLUG_EVENTS
 
- TB_VSE_CAP_TIME2
 
- TB_XDOMAIN_LENGTH_MASK
 
- TB_XDOMAIN_SN_MASK
 
- TB_XDOMAIN_SN_SHIFT
 
- TB_XDP_PROPERTIES_MAX_DATA_LENGTH
 
- TB_XDP_PROPERTIES_MAX_LENGTH
 
- TB_ZSECSENDCPRB
 
- TC
 
- TC0R
 
- TC0_MASTER_BUSY
 
- TC1100_INSTANCE_JOGDIAL
 
- TC1100_INSTANCE_WIRELESS
 
- TC1550
 
- TC1R
 
- TC1_MASTER_BUSY
 
- TC2_CLUSTERS
 
- TC2_MAX_CPUS_PER_CLUSTER
 
- TC35815CF
 
- TC35815_NWU
 
- TC35815_TX4939
 
- TC35815_TX_TIMEOUT
 
- TC358743_CID_AUDIO_PRESENT
 
- TC358743_CID_AUDIO_SAMPLING_RATE
 
- TC35876X
 
- TC35893_DATA_REGS
 
- TC35893_KEYCODE_FIFO_CLEAR
 
- TC35893_KEYCODE_FIFO_EMPTY
 
- TC35893_KEYPAD_ROW_SHIFT
 
- TC3589X_TC35890
 
- TC3589X_TC35892
 
- TC3589X_TC35893
 
- TC3589X_TC35894
 
- TC3589X_TC35895
 
- TC3589X_TC35896
 
- TC3589X_UNKNOWN
 
- TC3589x_BLOCK_GPIO
 
- TC3589x_BLOCK_KEYPAD
 
- TC3589x_CLKCFG
 
- TC3589x_CLKEN
 
- TC3589x_CLKMODE
 
- TC3589x_CLKMODE_MODCTL_OPERATION
 
- TC3589x_CLKMODE_MODCTL_SLEEP
 
- TC3589x_EVTCODE_FIFO
 
- TC3589x_EVT_INT
 
- TC3589x_EVT_INT_CLR
 
- TC3589x_EVT_LOSS_INT
 
- TC3589x_EXTRSTN
 
- TC3589x_GPIODATA0
 
- TC3589x_GPIODATA1
 
- TC3589x_GPIODATA2
 
- TC3589x_GPIODIR0
 
- TC3589x_GPIODIR1
 
- TC3589x_GPIODIR2
 
- TC3589x_GPIOIBE0
 
- TC3589x_GPIOIBE1
 
- TC3589x_GPIOIBE2
 
- TC3589x_GPIOIC0
 
- TC3589x_GPIOIC1
 
- TC3589x_GPIOIC2
 
- TC3589x_GPIOIE0
 
- TC3589x_GPIOIE1
 
- TC3589x_GPIOIE2
 
- TC3589x_GPIOIEV0
 
- TC3589x_GPIOIEV1
 
- TC3589x_GPIOIEV2
 
- TC3589x_GPIOIS0
 
- TC3589x_GPIOIS1
 
- TC3589x_GPIOIS2
 
- TC3589x_GPIOMASK0
 
- TC3589x_GPIOMASK1
 
- TC3589x_GPIOMASK2
 
- TC3589x_GPIOMIS0
 
- TC3589x_GPIOMIS1
 
- TC3589x_GPIOMIS2
 
- TC3589x_GPIOODE0
 
- TC3589x_GPIOODE1
 
- TC3589x_GPIOODE2
 
- TC3589x_GPIOODM0
 
- TC3589x_GPIOODM1
 
- TC3589x_GPIOODM2
 
- TC3589x_GPIORIS0
 
- TC3589x_GPIORIS1
 
- TC3589x_GPIORIS2
 
- TC3589x_GPIOSYNC0
 
- TC3589x_GPIOSYNC1
 
- TC3589x_GPIOSYNC2
 
- TC3589x_GPIOWAKE0
 
- TC3589x_GPIOWAKE1
 
- TC3589x_GPIOWAKE2
 
- TC3589x_INT_GPIIRQ
 
- TC3589x_INT_KBDIRQ
 
- TC3589x_INT_PORIRQ
 
- TC3589x_INT_ROTIRQ
 
- TC3589x_INT_TI0IRQ
 
- TC3589x_INT_TI1IRQ
 
- TC3589x_INT_TI2IRQ
 
- TC3589x_IOCFG
 
- TC3589x_IOPULLCFG0_LSB
 
- TC3589x_IOPULLCFG0_MSB
 
- TC3589x_IOPULLCFG1_LSB
 
- TC3589x_IOPULLCFG1_MSB
 
- TC3589x_IOPULLCFG2_LSB
 
- TC3589x_IO_PULL_VAL
 
- TC3589x_IRQRST
 
- TC3589x_IRQST
 
- TC3589x_KBCFG_LSB
 
- TC3589x_KBCFG_MSB
 
- TC3589x_KBDBOUNCE
 
- TC3589x_KBDIC
 
- TC3589x_KBDMFS
 
- TC3589x_KBDMFS_EN
 
- TC3589x_KBDMSK
 
- TC3589x_KBDRST
 
- TC3589x_KBDSETTLE_REG
 
- TC3589x_KBDSIZE
 
- TC3589x_KBD_INT
 
- TC3589x_KBD_INT_CLR
 
- TC3589x_KBD_LOSS_INT
 
- TC3589x_MANFCODE
 
- TC3589x_MANFCODE_MAGIC
 
- TC3589x_MAX_DEBOUNCE_SETTLE
 
- TC3589x_MAX_KPCOL
 
- TC3589x_MAX_KPROW
 
- TC3589x_NO_PULL_MASK
 
- TC3589x_NR_INTERNAL_IRQS
 
- TC3589x_PULLUP_ALL_MASK
 
- TC3589x_PULL_DOWN_MASK
 
- TC3589x_PULL_UP_MASK
 
- TC3589x_RESET_ALL
 
- TC3589x_RSTCTRL
 
- TC3589x_RSTCTRL_GPIRST
 
- TC3589x_RSTCTRL_IRQRST
 
- TC3589x_RSTCTRL_KBDRST
 
- TC3589x_RSTCTRL_ROTRST
 
- TC3589x_RSTCTRL_TIMRST
 
- TC3589x_RSTINTCLR
 
- TC3589x_VERSION
 
- TC58FVB160
 
- TC58FVB321
 
- TC58FVB641
 
- TC58FVT160
 
- TC58FVT321
 
- TC58FVT641
 
- TC6387XB_CELL_MMC
 
- TC6393XB_CELL_FB
 
- TC6393XB_CELL_MMC
 
- TC6393XB_CELL_NAND
 
- TC6393XB_CELL_OHCI
 
- TC6393XB_NR_IRQS
 
- TC654_FAN_FAULT_FROM_REG
 
- TC654_FAN_FAULT_TO_REG
 
- TC654_HIGH_RPM_RESOLUTION
 
- TC654_LOW_RPM_RESOLUTION
 
- TC654_REG_CONFIG
 
- TC654_REG_CONFIG_DUTYC
 
- TC654_REG_CONFIG_RES
 
- TC654_REG_CONFIG_SDM
 
- TC654_REG_DUTY_CYCLE
 
- TC654_REG_FAN_FAULT
 
- TC654_REG_FAN_FAULT1
 
- TC654_REG_FAN_FAULT2
 
- TC654_REG_MFR_ID
 
- TC654_REG_RPM
 
- TC654_REG_RPM1
 
- TC654_REG_RPM2
 
- TC654_REG_STATUS
 
- TC654_REG_STATUS_F1F
 
- TC654_REG_STATUS_F2F
 
- TC654_REG_VER_ID
 
- TC654_UPDATE_INTERVAL
 
- TC74_REG_CONFIG
 
- TC74_REG_TEMP
 
- TC90522_H
 
- TC90522_I2C_DEV_SAT
 
- TC90522_I2C_DEV_TER
 
- TC90522_I2C_THRU_REG
 
- TC90522_MODULE_IDX
 
- TC9154A_ATT_MAJ
 
- TC9154A_ATT_MAJ_0DB
 
- TC9154A_ATT_MAJ_10DB
 
- TC9154A_ATT_MAJ_20DB
 
- TC9154A_ATT_MAJ_30DB
 
- TC9154A_ATT_MAJ_40DB
 
- TC9154A_ATT_MAJ_50DB
 
- TC9154A_ATT_MAJ_60DB
 
- TC9154A_ATT_MIN
 
- TC9154A_ATT_MIN_0DB
 
- TC9154A_ATT_MIN_2DB
 
- TC9154A_ATT_MIN_4DB
 
- TC9154A_ATT_MIN_6DB
 
- TC9154A_ATT_MIN_8DB
 
- TC9154A_CHANNEL_LEFT
 
- TC9154A_CHANNEL_RIGHT
 
- TCA6416_BASE
 
- TCA6416_DIRECTION
 
- TCA6416_INPUT
 
- TCA6416_INTR
 
- TCA6416_INVERT
 
- TCA6416_NAME
 
- TCA6416_OUTPUT
 
- TCA6507_FADE_OFF
 
- TCA6507_FADE_ON
 
- TCA6507_FIRST_OFF
 
- TCA6507_FULL_ON
 
- TCA6507_INITIALIZE
 
- TCA6507_LS_BLINK0
 
- TCA6507_LS_BLINK1
 
- TCA6507_LS_LED_MIR
 
- TCA6507_LS_LED_OFF
 
- TCA6507_LS_LED_OFF1
 
- TCA6507_LS_LED_ON
 
- TCA6507_LS_LED_PWM0
 
- TCA6507_LS_LED_PWM1
 
- TCA6507_MAKE_GPIO
 
- TCA6507_MASTER_INTENSITY
 
- TCA6507_MAX_INTENSITY
 
- TCA6507_REG_CNT
 
- TCA6507_SECOND_OFF
 
- TCA8418_MAX_COLS
 
- TCA8418_MAX_ROWS
 
- TCAA_MAX
 
- TCALL_CNT
 
- TCAMINTPERR_F
 
- TCAMINTPERR_S
 
- TCAMINTPERR_V
 
- TCAM_ACTV_HIT_G
 
- TCAM_ACTV_HIT_M
 
- TCAM_ACTV_HIT_S
 
- TCAM_ACTV_HIT_V
 
- TCAM_ASSOCDATA_AGE
 
- TCAM_ASSOCDATA_DISC
 
- TCAM_ASSOCDATA_OFFSET
 
- TCAM_ASSOCDATA_OFFSET_SHIFT
 
- TCAM_ASSOCDATA_RDCTBL
 
- TCAM_ASSOCDATA_RDCTBL_SHIFT
 
- TCAM_ASSOCDATA_SYNDROME
 
- TCAM_ASSOCDATA_SYNDROME_SHIFT
 
- TCAM_ASSOCDATA_TRES_MASK
 
- TCAM_ASSOCDATA_TRES_OVR_RDC
 
- TCAM_ASSOCDATA_TRES_OVR_RDC_OFF
 
- TCAM_ASSOCDATA_TRES_USE_L2RDC
 
- TCAM_ASSOCDATA_TRES_USE_OFFSET
 
- TCAM_ASSOCDATA_V4_ECC_OK
 
- TCAM_ASSOCDATA_ZFID
 
- TCAM_ASSOCDATA_ZFID_SHIFT
 
- TCAM_ASSOCDATA_ZFVLD
 
- TCAM_BYPASS_F
 
- TCAM_BYPASS_S
 
- TCAM_BYPASS_V
 
- TCAM_CTL
 
- TCAM_CTL_LOC
 
- TCAM_CTL_MATCH
 
- TCAM_CTL_RWC
 
- TCAM_CTL_RWC_RAM_READ
 
- TCAM_CTL_RWC_RAM_WRITE
 
- TCAM_CTL_RWC_TCAM_COMPARE
 
- TCAM_CTL_RWC_TCAM_READ
 
- TCAM_CTL_RWC_TCAM_WRITE
 
- TCAM_CTL_STAT
 
- TCAM_ERR
 
- TCAM_ERR_ADDR
 
- TCAM_ERR_ERR
 
- TCAM_ERR_MULT
 
- TCAM_ERR_P_ECC
 
- TCAM_ERR_SYNDROME
 
- TCAM_ETHKEY0_CLASS_CODE
 
- TCAM_ETHKEY0_CLASS_CODE_SHIFT
 
- TCAM_ETHKEY0_RESV1
 
- TCAM_ETHKEY0_RESV2
 
- TCAM_ETHKEY1_FRAME_BYTE0_7
 
- TCAM_ETHKEY2_FRAME_BYTE10
 
- TCAM_ETHKEY2_FRAME_BYTE10_SHIFT
 
- TCAM_ETHKEY2_FRAME_BYTE8
 
- TCAM_ETHKEY2_FRAME_BYTE8_SHIFT
 
- TCAM_ETHKEY2_FRAME_BYTE9
 
- TCAM_ETHKEY2_FRAME_BYTE9_SHIFT
 
- TCAM_ETHKEY2_FRAME_RESV
 
- TCAM_ETHKEY3_FRAME_RESV
 
- TCAM_KEY
 
- TCAM_KEY_0
 
- TCAM_KEY_0_KEY
 
- TCAM_KEY_1
 
- TCAM_KEY_1_KEY
 
- TCAM_KEY_2
 
- TCAM_KEY_2_KEY
 
- TCAM_KEY_3
 
- TCAM_KEY_3_KEY
 
- TCAM_KEY_DISC
 
- TCAM_KEY_IPADDR
 
- TCAM_KEY_MASK_0
 
- TCAM_KEY_MASK_0_KEY_SEL
 
- TCAM_KEY_MASK_1
 
- TCAM_KEY_MASK_1_KEY_SEL
 
- TCAM_KEY_MASK_2
 
- TCAM_KEY_MASK_2_KEY_SEL
 
- TCAM_KEY_MASK_3
 
- TCAM_KEY_MASK_3_KEY_SEL
 
- TCAM_KEY_TSEL
 
- TCAM_RESET
 
- TCAM_SEL
 
- TCAM_SOFT_ERR_IRQ
 
- TCAM_V4KEY0_CLASS_CODE
 
- TCAM_V4KEY0_CLASS_CODE_SHIFT
 
- TCAM_V4KEY0_RESV1
 
- TCAM_V4KEY0_RESV2
 
- TCAM_V4KEY1_L2RDCNUM
 
- TCAM_V4KEY1_L2RDCNUM_SHIFT
 
- TCAM_V4KEY1_NOPORT
 
- TCAM_V4KEY1_RESV
 
- TCAM_V4KEY2_PORT_SPI
 
- TCAM_V4KEY2_PORT_SPI_SHIFT
 
- TCAM_V4KEY2_PROTO
 
- TCAM_V4KEY2_PROTO_SHIFT
 
- TCAM_V4KEY2_RESV
 
- TCAM_V4KEY2_TOS
 
- TCAM_V4KEY2_TOS_SHIFT
 
- TCAM_V4KEY3_DADDR
 
- TCAM_V4KEY3_DADDR_SHIFT
 
- TCAM_V4KEY3_SADDR
 
- TCAM_V4KEY3_SADDR_SHIFT
 
- TCAM_V6KEY0_CLASS_CODE
 
- TCAM_V6KEY0_CLASS_CODE_SHIFT
 
- TCAM_V6KEY0_RESV1
 
- TCAM_V6KEY0_RESV2
 
- TCAM_V6KEY1_L2RDCNUM
 
- TCAM_V6KEY1_L2RDCNUM_SHIFT
 
- TCAM_V6KEY1_NEXT_HDR
 
- TCAM_V6KEY1_NEXT_HDR_SHIFT
 
- TCAM_V6KEY1_NOPORT
 
- TCAM_V6KEY1_PORT_SPI
 
- TCAM_V6KEY1_PORT_SPI_SHIFT
 
- TCAM_V6KEY1_RESV
 
- TCAM_V6KEY1_TOS
 
- TCAM_V6KEY1_TOS_SHIFT
 
- TCAM_V6KEY2_ADDR_HIGH
 
- TCAM_V6KEY3_ADDR_LOW
 
- TCAN4X5X_BUS_FAULT
 
- TCAN4X5X_CANBUSBAT_INT_EN
 
- TCAN4X5X_CANBUSGND_INT_EN
 
- TCAN4X5X_CANBUSOPEN_INT_EN
 
- TCAN4X5X_CANBUSTERMOPEN_INT_EN
 
- TCAN4X5X_CANBUS_ERR_INT_EN
 
- TCAN4X5X_CANDOM_INT_EN
 
- TCAN4X5X_CANHBAT_INT_EN
 
- TCAN4X5X_CANHCANL_INT_EN
 
- TCAN4X5X_CANINT_INT_EN
 
- TCAN4X5X_CANLGND_INT_EN
 
- TCAN4X5X_CANSLNT_INT_EN
 
- TCAN4X5X_CLEAR_ALL_INT
 
- TCAN4X5X_CONFIG
 
- TCAN4X5X_CONTROL
 
- TCAN4X5X_DEV_ID0
 
- TCAN4X5X_DEV_ID1
 
- TCAN4X5X_ECCERR_INT_EN
 
- TCAN4X5X_ENABLE_MCAN_INT
 
- TCAN4X5X_ENABLE_TCAN_INT
 
- TCAN4X5X_ERROR_STATUS
 
- TCAN4X5X_EXT_CLK_DEF
 
- TCAN4X5X_INT_EN
 
- TCAN4X5X_INT_FLAGS
 
- TCAN4X5X_LWU_INT_EN
 
- TCAN4X5X_MAX_REGISTER
 
- TCAN4X5X_MCAN_CONFIGURED
 
- TCAN4X5X_MCAN_INT
 
- TCAN4X5X_MCAN_INT_REG
 
- TCAN4X5X_MCAN_IR_ARA
 
- TCAN4X5X_MCAN_IR_BEC
 
- TCAN4X5X_MCAN_IR_BEU
 
- TCAN4X5X_MCAN_IR_BO
 
- TCAN4X5X_MCAN_IR_DRX
 
- TCAN4X5X_MCAN_IR_ELO
 
- TCAN4X5X_MCAN_IR_EP
 
- TCAN4X5X_MCAN_IR_EW
 
- TCAN4X5X_MCAN_IR_HPM
 
- TCAN4X5X_MCAN_IR_MRAF
 
- TCAN4X5X_MCAN_IR_PEA
 
- TCAN4X5X_MCAN_IR_PED
 
- TCAN4X5X_MCAN_IR_RF0F
 
- TCAN4X5X_MCAN_IR_RF0L
 
- TCAN4X5X_MCAN_IR_RF0N
 
- TCAN4X5X_MCAN_IR_RF0W
 
- TCAN4X5X_MCAN_IR_RF1F
 
- TCAN4X5X_MCAN_IR_RF1L
 
- TCAN4X5X_MCAN_IR_RF1N
 
- TCAN4X5X_MCAN_IR_RF1W
 
- TCAN4X5X_MCAN_IR_TC
 
- TCAN4X5X_MCAN_IR_TCF
 
- TCAN4X5X_MCAN_IR_TEFF
 
- TCAN4X5X_MCAN_IR_TEFL
 
- TCAN4X5X_MCAN_IR_TEFN
 
- TCAN4X5X_MCAN_IR_TEFW
 
- TCAN4X5X_MCAN_IR_TFE
 
- TCAN4X5X_MCAN_IR_TOO
 
- TCAN4X5X_MCAN_IR_TSW
 
- TCAN4X5X_MCAN_IR_WD
 
- TCAN4X5X_MCAN_OFFSET
 
- TCAN4X5X_MODE_NORMAL
 
- TCAN4X5X_MODE_SEL_MASK
 
- TCAN4X5X_MODE_SLEEP
 
- TCAN4X5X_MODE_STANDBY
 
- TCAN4X5X_MRAM_START
 
- TCAN4X5X_READ_CMD
 
- TCAN4X5X_REV
 
- TCAN4X5X_SET_ALL_INT
 
- TCAN4X5X_STATUS
 
- TCAN4X5X_SW_RESET
 
- TCAN4X5X_TEST_REG
 
- TCAN4X5X_TSD_INT_EN
 
- TCAN4X5X_TS_PRESCALE
 
- TCAN4X5X_UVIO_INT_EN
 
- TCAN4X5X_UVSUP_INT_EN
 
- TCAN4X5X_WATCHDOG_EN
 
- TCAN4X5X_WD_3_S_TIMER
 
- TCAN4X5X_WD_600_MS_TIMER
 
- TCAN4X5X_WD_60_MS_TIMER
 
- TCAN4X5X_WD_6_S_TIMER
 
- TCAN4X5X_WRITE_CMD
 
- TCAP_F
 
- TCAP_S
 
- TCAP_V
 
- TCA_ACT_BIND
 
- TCA_ACT_BPF
 
- TCA_ACT_BPF_FD
 
- TCA_ACT_BPF_ID
 
- TCA_ACT_BPF_MAX
 
- TCA_ACT_BPF_NAME
 
- TCA_ACT_BPF_OPS
 
- TCA_ACT_BPF_OPS_LEN
 
- TCA_ACT_BPF_PAD
 
- TCA_ACT_BPF_PARMS
 
- TCA_ACT_BPF_TAG
 
- TCA_ACT_BPF_TM
 
- TCA_ACT_BPF_UNSPEC
 
- TCA_ACT_CONNMARK
 
- TCA_ACT_COOKIE
 
- TCA_ACT_CSUM
 
- TCA_ACT_GACT
 
- TCA_ACT_IFE
 
- TCA_ACT_INDEX
 
- TCA_ACT_IPT
 
- TCA_ACT_KIND
 
- TCA_ACT_MAX
 
- TCA_ACT_MAX_PRIO
 
- TCA_ACT_MAX_PRIO_MASK
 
- TCA_ACT_MIRRED
 
- TCA_ACT_NAT
 
- TCA_ACT_NOBIND
 
- TCA_ACT_NOREPLACE
 
- TCA_ACT_NOUNBIND
 
- TCA_ACT_OPTIONS
 
- TCA_ACT_PAD
 
- TCA_ACT_PEDIT
 
- TCA_ACT_REPLACE
 
- TCA_ACT_SAMPLE
 
- TCA_ACT_SIMP
 
- TCA_ACT_SKBEDIT
 
- TCA_ACT_SKBMOD
 
- TCA_ACT_STATS
 
- TCA_ACT_TAB
 
- TCA_ACT_TUNNEL_KEY
 
- TCA_ACT_UNBIND
 
- TCA_ACT_UNSPEC
 
- TCA_ACT_VLAN
 
- TCA_ACT_XT
 
- TCA_ATM_ADDR
 
- TCA_ATM_EXCESS
 
- TCA_ATM_FD
 
- TCA_ATM_HDR
 
- TCA_ATM_MAX
 
- TCA_ATM_PTR
 
- TCA_ATM_STATE
 
- TCA_ATM_UNSPEC
 
- TCA_BASIC_ACT
 
- TCA_BASIC_CLASSID
 
- TCA_BASIC_EMATCHES
 
- TCA_BASIC_MAX
 
- TCA_BASIC_PAD
 
- TCA_BASIC_PCNT
 
- TCA_BASIC_POLICE
 
- TCA_BASIC_UNSPEC
 
- TCA_BPF_ACT
 
- TCA_BPF_CLASSID
 
- TCA_BPF_FD
 
- TCA_BPF_FLAGS
 
- TCA_BPF_FLAGS_GEN
 
- TCA_BPF_FLAG_ACT_DIRECT
 
- TCA_BPF_ID
 
- TCA_BPF_MAX
 
- TCA_BPF_NAME
 
- TCA_BPF_OPS
 
- TCA_BPF_OPS_LEN
 
- TCA_BPF_POLICE
 
- TCA_BPF_TAG
 
- TCA_BPF_UNSPEC
 
- TCA_BURST_CTRL__CPF_DISABLE_MASK
 
- TCA_BURST_CTRL__CPF_DISABLE__SHIFT
 
- TCA_BURST_CTRL__CPG_DISABLE_MASK
 
- TCA_BURST_CTRL__CPG_DISABLE__SHIFT
 
- TCA_BURST_CTRL__IA_DISABLE_MASK
 
- TCA_BURST_CTRL__IA_DISABLE__SHIFT
 
- TCA_BURST_CTRL__MAX_BURST_MASK
 
- TCA_BURST_CTRL__MAX_BURST__SHIFT
 
- TCA_BURST_CTRL__PA_DISABLE_MASK
 
- TCA_BURST_CTRL__PA_DISABLE__SHIFT
 
- TCA_BURST_CTRL__RB_DISABLE_MASK
 
- TCA_BURST_CTRL__RB_DISABLE__SHIFT
 
- TCA_BURST_CTRL__RLC_DISABLE_MASK
 
- TCA_BURST_CTRL__RLC_DISABLE__SHIFT
 
- TCA_BURST_CTRL__SQC_DISABLE_MASK
 
- TCA_BURST_CTRL__SQC_DISABLE__SHIFT
 
- TCA_BURST_CTRL__SQG_DISABLE_MASK
 
- TCA_BURST_CTRL__SQG_DISABLE__SHIFT
 
- TCA_BURST_CTRL__TCP_DISABLE_MASK
 
- TCA_BURST_CTRL__TCP_DISABLE__SHIFT
 
- TCA_BURST_CTRL__TPI_DISABLE_MASK
 
- TCA_BURST_CTRL__TPI_DISABLE__SHIFT
 
- TCA_BURST_CTRL__UTCL2_DISABLE_MASK
 
- TCA_BURST_CTRL__UTCL2_DISABLE__SHIFT
 
- TCA_BURST_CTRL__WD_DISABLE_MASK
 
- TCA_BURST_CTRL__WD_DISABLE__SHIFT
 
- TCA_BURST_MASK__ADDR_MASK_MASK
 
- TCA_BURST_MASK__ADDR_MASK__SHIFT
 
- TCA_CAKE_ACK_FILTER
 
- TCA_CAKE_ATM
 
- TCA_CAKE_AUTORATE
 
- TCA_CAKE_BASE_RATE64
 
- TCA_CAKE_DIFFSERV_MODE
 
- TCA_CAKE_FLOW_MODE
 
- TCA_CAKE_FWMARK
 
- TCA_CAKE_INGRESS
 
- TCA_CAKE_MAX
 
- TCA_CAKE_MEMORY
 
- TCA_CAKE_MPU
 
- TCA_CAKE_NAT
 
- TCA_CAKE_OVERHEAD
 
- TCA_CAKE_PAD
 
- TCA_CAKE_RAW
 
- TCA_CAKE_RTT
 
- TCA_CAKE_SPLIT_GSO
 
- TCA_CAKE_STATS_AVG_NETOFF
 
- TCA_CAKE_STATS_BLUE_TIMER_US
 
- TCA_CAKE_STATS_CAPACITY_ESTIMATE64
 
- TCA_CAKE_STATS_COBALT_COUNT
 
- TCA_CAKE_STATS_DEFICIT
 
- TCA_CAKE_STATS_DROPPING
 
- TCA_CAKE_STATS_DROP_NEXT_US
 
- TCA_CAKE_STATS_MAX
 
- TCA_CAKE_STATS_MAX_ADJLEN
 
- TCA_CAKE_STATS_MAX_NETLEN
 
- TCA_CAKE_STATS_MEMORY_LIMIT
 
- TCA_CAKE_STATS_MEMORY_USED
 
- TCA_CAKE_STATS_MIN_ADJLEN
 
- TCA_CAKE_STATS_MIN_NETLEN
 
- TCA_CAKE_STATS_PAD
 
- TCA_CAKE_STATS_P_DROP
 
- TCA_CAKE_STATS_TIN_STATS
 
- TCA_CAKE_TARGET
 
- TCA_CAKE_TIN_STATS_ACKS_DROPPED_BYTES64
 
- TCA_CAKE_TIN_STATS_ACKS_DROPPED_PACKETS
 
- TCA_CAKE_TIN_STATS_AVG_DELAY_US
 
- TCA_CAKE_TIN_STATS_BACKLOG_BYTES
 
- TCA_CAKE_TIN_STATS_BACKLOG_PACKETS
 
- TCA_CAKE_TIN_STATS_BASE_DELAY_US
 
- TCA_CAKE_TIN_STATS_BULK_FLOWS
 
- TCA_CAKE_TIN_STATS_DROPPED_BYTES64
 
- TCA_CAKE_TIN_STATS_DROPPED_PACKETS
 
- TCA_CAKE_TIN_STATS_ECN_MARKED_BYTES64
 
- TCA_CAKE_TIN_STATS_ECN_MARKED_PACKETS
 
- TCA_CAKE_TIN_STATS_FLOW_QUANTUM
 
- TCA_CAKE_TIN_STATS_INTERVAL_US
 
- TCA_CAKE_TIN_STATS_MAX
 
- TCA_CAKE_TIN_STATS_MAX_SKBLEN
 
- TCA_CAKE_TIN_STATS_PAD
 
- TCA_CAKE_TIN_STATS_PEAK_DELAY_US
 
- TCA_CAKE_TIN_STATS_SENT_BYTES64
 
- TCA_CAKE_TIN_STATS_SENT_PACKETS
 
- TCA_CAKE_TIN_STATS_SPARSE_FLOWS
 
- TCA_CAKE_TIN_STATS_TARGET_US
 
- TCA_CAKE_TIN_STATS_THRESHOLD_RATE64
 
- TCA_CAKE_TIN_STATS_UNRESPONSIVE_FLOWS
 
- TCA_CAKE_TIN_STATS_WAY_COLLISIONS
 
- TCA_CAKE_TIN_STATS_WAY_INDIRECT_HITS
 
- TCA_CAKE_TIN_STATS_WAY_MISSES
 
- TCA_CAKE_UNSPEC
 
- TCA_CAKE_WASH
 
- TCA_CBQ_FOPT
 
- TCA_CBQ_LSSOPT
 
- TCA_CBQ_MAX
 
- TCA_CBQ_OVL_STRATEGY
 
- TCA_CBQ_POLICE
 
- TCA_CBQ_RATE
 
- TCA_CBQ_RTAB
 
- TCA_CBQ_UNSPEC
 
- TCA_CBQ_WRROPT
 
- TCA_CBS_MAX
 
- TCA_CBS_PARMS
 
- TCA_CBS_UNSPEC
 
- TCA_CGROUP_ACT
 
- TCA_CGROUP_EMATCHES
 
- TCA_CGROUP_MAX
 
- TCA_CGROUP_POLICE
 
- TCA_CGROUP_UNSPEC
 
- TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK
 
- TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT
 
- TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK
 
- TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT
 
- TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK
 
- TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT
 
- TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK
 
- TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT
 
- TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK
 
- TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT
 
- TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK
 
- TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT
 
- TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK
 
- TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT
 
- TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK
 
- TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT
 
- TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK
 
- TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT
 
- TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK
 
- TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT
 
- TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK
 
- TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT
 
- TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK
 
- TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT
 
- TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK
 
- TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT
 
- TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK
 
- TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT
 
- TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK
 
- TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT
 
- TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK
 
- TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT
 
- TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK
 
- TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT
 
- TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK
 
- TCA_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT
 
- TCA_CHAIN
 
- TCA_CHOKE_MAX
 
- TCA_CHOKE_MAX_P
 
- TCA_CHOKE_PARMS
 
- TCA_CHOKE_STAB
 
- TCA_CHOKE_UNSPEC
 
- TCA_CLS_FLAGS_IN_HW
 
- TCA_CLS_FLAGS_NOT_IN_HW
 
- TCA_CLS_FLAGS_SKIP_HW
 
- TCA_CLS_FLAGS_SKIP_SW
 
- TCA_CLS_FLAGS_VERBOSE
 
- TCA_CODEL_CE_THRESHOLD
 
- TCA_CODEL_ECN
 
- TCA_CODEL_INTERVAL
 
- TCA_CODEL_LIMIT
 
- TCA_CODEL_MAX
 
- TCA_CODEL_TARGET
 
- TCA_CODEL_UNSPEC
 
- TCA_CONNMARK_MAX
 
- TCA_CONNMARK_PAD
 
- TCA_CONNMARK_PARMS
 
- TCA_CONNMARK_TM
 
- TCA_CONNMARK_UNSPEC
 
- TCA_CSUM_MAX
 
- TCA_CSUM_PAD
 
- TCA_CSUM_PARMS
 
- TCA_CSUM_TM
 
- TCA_CSUM_UNSPEC
 
- TCA_CSUM_UPDATE_FLAG_ICMP
 
- TCA_CSUM_UPDATE_FLAG_IGMP
 
- TCA_CSUM_UPDATE_FLAG_IPV4HDR
 
- TCA_CSUM_UPDATE_FLAG_SCTP
 
- TCA_CSUM_UPDATE_FLAG_TCP
 
- TCA_CSUM_UPDATE_FLAG_UDP
 
- TCA_CSUM_UPDATE_FLAG_UDPLITE
 
- TCA_CTINFO_ACT
 
- TCA_CTINFO_MAX
 
- TCA_CTINFO_PAD
 
- TCA_CTINFO_PARMS_CPMARK_MASK
 
- TCA_CTINFO_PARMS_DSCP_MASK
 
- TCA_CTINFO_PARMS_DSCP_STATEMASK
 
- TCA_CTINFO_STATS_CPMARK_SET
 
- TCA_CTINFO_STATS_DSCP_ERROR
 
- TCA_CTINFO_STATS_DSCP_SET
 
- TCA_CTINFO_TM
 
- TCA_CTINFO_UNSPEC
 
- TCA_CTINFO_ZONE
 
- TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER_MASK
 
- TCA_CTRL__DISABLE_RB_ONLY_TCA_ARBITER__SHIFT
 
- TCA_CTRL__DISABLE_UTCL2_PRIORITY_MASK
 
- TCA_CTRL__DISABLE_UTCL2_PRIORITY__SHIFT
 
- TCA_CTRL__HOLE_TIMEOUT_MASK
 
- TCA_CTRL__HOLE_TIMEOUT__SHIFT
 
- TCA_CTRL__RB_AS_TCI_MASK
 
- TCA_CTRL__RB_AS_TCI__SHIFT
 
- TCA_CTRL__RB_STILL_4_PHASE_MASK
 
- TCA_CTRL__RB_STILL_4_PHASE__SHIFT
 
- TCA_CT_ACTION
 
- TCA_CT_ACT_CLEAR
 
- TCA_CT_ACT_COMMIT
 
- TCA_CT_ACT_FORCE
 
- TCA_CT_ACT_NAT
 
- TCA_CT_ACT_NAT_DST
 
- TCA_CT_ACT_NAT_SRC
 
- TCA_CT_LABELS
 
- TCA_CT_LABELS_MASK
 
- TCA_CT_MARK
 
- TCA_CT_MARK_MASK
 
- TCA_CT_MAX
 
- TCA_CT_NAT_IPV4_MAX
 
- TCA_CT_NAT_IPV4_MIN
 
- TCA_CT_NAT_IPV6_MAX
 
- TCA_CT_NAT_IPV6_MIN
 
- TCA_CT_NAT_PORT_MAX
 
- TCA_CT_NAT_PORT_MIN
 
- TCA_CT_PAD
 
- TCA_CT_PARMS
 
- TCA_CT_TM
 
- TCA_CT_UNSPEC
 
- TCA_CT_ZONE
 
- TCA_DEF_DATA
 
- TCA_DEF_MAX
 
- TCA_DEF_PAD
 
- TCA_DEF_PARMS
 
- TCA_DEF_TM
 
- TCA_DEF_UNSPEC
 
- TCA_DRR_MAX
 
- TCA_DRR_QUANTUM
 
- TCA_DRR_UNSPEC
 
- TCA_DSMARK_DEFAULT_INDEX
 
- TCA_DSMARK_INDICES
 
- TCA_DSMARK_MASK
 
- TCA_DSMARK_MAX
 
- TCA_DSMARK_SET_TC_INDEX
 
- TCA_DSMARK_UNSPEC
 
- TCA_DSMARK_VALUE
 
- TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT_MASK
 
- TCA_DSM_CNTL2__HOLE_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT
 
- TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY_MASK
 
- TCA_DSM_CNTL2__HOLE_FIFO_SED_SELECT_INJECT_DELAY__SHIFT
 
- TCA_DSM_CNTL2__INJECT_DELAY_MASK
 
- TCA_DSM_CNTL2__INJECT_DELAY__SHIFT
 
- TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT_MASK
 
- TCA_DSM_CNTL2__REQ_FIFO_SED_ENABLE_ERROR_INJECT__SHIFT
 
- TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY_MASK
 
- TCA_DSM_CNTL2__REQ_FIFO_SED_SELECT_INJECT_DELAY__SHIFT
 
- TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL_MASK
 
- TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT
 
- TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK
 
- TCA_DSM_CNTL__HOLE_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT
 
- TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL_MASK
 
- TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_DATA_SEL__SHIFT
 
- TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE_MASK
 
- TCA_DSM_CNTL__REQ_FIFO_SED_IRRITATOR_SINGLE_WRITE__SHIFT
 
- TCA_DUMP_INVISIBLE
 
- TCA_EDC_CNT__HOLE_FIFO_SED_COUNT_MASK
 
- TCA_EDC_CNT__HOLE_FIFO_SED_COUNT__SHIFT
 
- TCA_EDC_CNT__REQ_FIFO_SED_COUNT_MASK
 
- TCA_EDC_CNT__REQ_FIFO_SED_COUNT__SHIFT
 
- TCA_EGRESS_BLOCK
 
- TCA_EGRESS_MIRROR
 
- TCA_EGRESS_REDIR
 
- TCA_EMATCH_TREE_HDR
 
- TCA_EMATCH_TREE_LIST
 
- TCA_EMATCH_TREE_MAX
 
- TCA_EMATCH_TREE_UNSPEC
 
- TCA_EM_IPT_HOOK
 
- TCA_EM_IPT_MATCH_DATA
 
- TCA_EM_IPT_MATCH_NAME
 
- TCA_EM_IPT_MATCH_REVISION
 
- TCA_EM_IPT_MAX
 
- TCA_EM_IPT_NFPROTO
 
- TCA_EM_IPT_UNSPEC
 
- TCA_EM_META_HDR
 
- TCA_EM_META_LVALUE
 
- TCA_EM_META_MAX
 
- TCA_EM_META_RVALUE
 
- TCA_EM_META_UNSPEC
 
- TCA_ETF_MAX
 
- TCA_ETF_PARMS
 
- TCA_ETF_UNSPEC
 
- TCA_FCNT
 
- TCA_FLAG_LARGE_DUMP_ON
 
- TCA_FLOWER_ACT
 
- TCA_FLOWER_CLASSID
 
- TCA_FLOWER_FLAGS
 
- TCA_FLOWER_INDEV
 
- TCA_FLOWER_IN_HW_COUNT
 
- TCA_FLOWER_KEY_ARP_OP
 
- TCA_FLOWER_KEY_ARP_OP_MASK
 
- TCA_FLOWER_KEY_ARP_SHA
 
- TCA_FLOWER_KEY_ARP_SHA_MASK
 
- TCA_FLOWER_KEY_ARP_SIP
 
- TCA_FLOWER_KEY_ARP_SIP_MASK
 
- TCA_FLOWER_KEY_ARP_THA
 
- TCA_FLOWER_KEY_ARP_THA_MASK
 
- TCA_FLOWER_KEY_ARP_TIP
 
- TCA_FLOWER_KEY_ARP_TIP_MASK
 
- TCA_FLOWER_KEY_CT_FLAGS_ESTABLISHED
 
- TCA_FLOWER_KEY_CT_FLAGS_NEW
 
- TCA_FLOWER_KEY_CT_FLAGS_RELATED
 
- TCA_FLOWER_KEY_CT_FLAGS_TRACKED
 
- TCA_FLOWER_KEY_CT_LABELS
 
- TCA_FLOWER_KEY_CT_LABELS_MASK
 
- TCA_FLOWER_KEY_CT_MARK
 
- TCA_FLOWER_KEY_CT_MARK_MASK
 
- TCA_FLOWER_KEY_CT_STATE
 
- TCA_FLOWER_KEY_CT_STATE_MASK
 
- TCA_FLOWER_KEY_CT_ZONE
 
- TCA_FLOWER_KEY_CT_ZONE_MASK
 
- TCA_FLOWER_KEY_CVLAN_ETH_TYPE
 
- TCA_FLOWER_KEY_CVLAN_ID
 
- TCA_FLOWER_KEY_CVLAN_PRIO
 
- TCA_FLOWER_KEY_ENC_IPV4_DST
 
- TCA_FLOWER_KEY_ENC_IPV4_DST_MASK
 
- TCA_FLOWER_KEY_ENC_IPV4_SRC
 
- TCA_FLOWER_KEY_ENC_IPV4_SRC_MASK
 
- TCA_FLOWER_KEY_ENC_IPV6_DST
 
- TCA_FLOWER_KEY_ENC_IPV6_DST_MASK
 
- TCA_FLOWER_KEY_ENC_IPV6_SRC
 
- TCA_FLOWER_KEY_ENC_IPV6_SRC_MASK
 
- TCA_FLOWER_KEY_ENC_IP_TOS
 
- TCA_FLOWER_KEY_ENC_IP_TOS_MASK
 
- TCA_FLOWER_KEY_ENC_IP_TTL
 
- TCA_FLOWER_KEY_ENC_IP_TTL_MASK
 
- TCA_FLOWER_KEY_ENC_KEY_ID
 
- TCA_FLOWER_KEY_ENC_OPTS
 
- TCA_FLOWER_KEY_ENC_OPTS_GENEVE
 
- TCA_FLOWER_KEY_ENC_OPTS_MASK
 
- TCA_FLOWER_KEY_ENC_OPTS_MAX
 
- TCA_FLOWER_KEY_ENC_OPTS_UNSPEC
 
- TCA_FLOWER_KEY_ENC_OPT_GENEVE_CLASS
 
- TCA_FLOWER_KEY_ENC_OPT_GENEVE_DATA
 
- TCA_FLOWER_KEY_ENC_OPT_GENEVE_MAX
 
- TCA_FLOWER_KEY_ENC_OPT_GENEVE_TYPE
 
- TCA_FLOWER_KEY_ENC_OPT_GENEVE_UNSPEC
 
- TCA_FLOWER_KEY_ENC_UDP_DST_PORT
 
- TCA_FLOWER_KEY_ENC_UDP_DST_PORT_MASK
 
- TCA_FLOWER_KEY_ENC_UDP_SRC_PORT
 
- TCA_FLOWER_KEY_ENC_UDP_SRC_PORT_MASK
 
- TCA_FLOWER_KEY_ETH_DST
 
- TCA_FLOWER_KEY_ETH_DST_MASK
 
- TCA_FLOWER_KEY_ETH_SRC
 
- TCA_FLOWER_KEY_ETH_SRC_MASK
 
- TCA_FLOWER_KEY_ETH_TYPE
 
- TCA_FLOWER_KEY_FLAGS
 
- TCA_FLOWER_KEY_FLAGS_FRAG_IS_FIRST
 
- TCA_FLOWER_KEY_FLAGS_IS_FRAGMENT
 
- TCA_FLOWER_KEY_FLAGS_MASK
 
- TCA_FLOWER_KEY_ICMPV4_CODE
 
- TCA_FLOWER_KEY_ICMPV4_CODE_MASK
 
- TCA_FLOWER_KEY_ICMPV4_TYPE
 
- TCA_FLOWER_KEY_ICMPV4_TYPE_MASK
 
- TCA_FLOWER_KEY_ICMPV6_CODE
 
- TCA_FLOWER_KEY_ICMPV6_CODE_MASK
 
- TCA_FLOWER_KEY_ICMPV6_TYPE
 
- TCA_FLOWER_KEY_ICMPV6_TYPE_MASK
 
- TCA_FLOWER_KEY_IPV4_DST
 
- TCA_FLOWER_KEY_IPV4_DST_MASK
 
- TCA_FLOWER_KEY_IPV4_SRC
 
- TCA_FLOWER_KEY_IPV4_SRC_MASK
 
- TCA_FLOWER_KEY_IPV6_DST
 
- TCA_FLOWER_KEY_IPV6_DST_MASK
 
- TCA_FLOWER_KEY_IPV6_SRC
 
- TCA_FLOWER_KEY_IPV6_SRC_MASK
 
- TCA_FLOWER_KEY_IP_PROTO
 
- TCA_FLOWER_KEY_IP_TOS
 
- TCA_FLOWER_KEY_IP_TOS_MASK
 
- TCA_FLOWER_KEY_IP_TTL
 
- TCA_FLOWER_KEY_IP_TTL_MASK
 
- TCA_FLOWER_KEY_MPLS_BOS
 
- TCA_FLOWER_KEY_MPLS_LABEL
 
- TCA_FLOWER_KEY_MPLS_TC
 
- TCA_FLOWER_KEY_MPLS_TTL
 
- TCA_FLOWER_KEY_PORT_DST_MAX
 
- TCA_FLOWER_KEY_PORT_DST_MIN
 
- TCA_FLOWER_KEY_PORT_SRC_MAX
 
- TCA_FLOWER_KEY_PORT_SRC_MIN
 
- TCA_FLOWER_KEY_SCTP_DST
 
- TCA_FLOWER_KEY_SCTP_DST_MASK
 
- TCA_FLOWER_KEY_SCTP_SRC
 
- TCA_FLOWER_KEY_SCTP_SRC_MASK
 
- TCA_FLOWER_KEY_TCP_DST
 
- TCA_FLOWER_KEY_TCP_DST_MASK
 
- TCA_FLOWER_KEY_TCP_FLAGS
 
- TCA_FLOWER_KEY_TCP_FLAGS_MASK
 
- TCA_FLOWER_KEY_TCP_SRC
 
- TCA_FLOWER_KEY_TCP_SRC_MASK
 
- TCA_FLOWER_KEY_UDP_DST
 
- TCA_FLOWER_KEY_UDP_DST_MASK
 
- TCA_FLOWER_KEY_UDP_SRC
 
- TCA_FLOWER_KEY_UDP_SRC_MASK
 
- TCA_FLOWER_KEY_VLAN_ETH_TYPE
 
- TCA_FLOWER_KEY_VLAN_ID
 
- TCA_FLOWER_KEY_VLAN_PRIO
 
- TCA_FLOWER_MASK_FLAGS_RANGE
 
- TCA_FLOWER_MAX
 
- TCA_FLOWER_UNSPEC
 
- TCA_FLOW_ACT
 
- TCA_FLOW_ADDEND
 
- TCA_FLOW_BASECLASS
 
- TCA_FLOW_DIVISOR
 
- TCA_FLOW_EMATCHES
 
- TCA_FLOW_KEYS
 
- TCA_FLOW_MASK
 
- TCA_FLOW_MAX
 
- TCA_FLOW_MODE
 
- TCA_FLOW_PERTURB
 
- TCA_FLOW_POLICE
 
- TCA_FLOW_RSHIFT
 
- TCA_FLOW_UNSPEC
 
- TCA_FLOW_XOR
 
- TCA_FQ_BUCKETS_LOG
 
- TCA_FQ_CE_THRESHOLD
 
- TCA_FQ_CODEL_CE_THRESHOLD
 
- TCA_FQ_CODEL_DROP_BATCH_SIZE
 
- TCA_FQ_CODEL_ECN
 
- TCA_FQ_CODEL_FLOWS
 
- TCA_FQ_CODEL_INTERVAL
 
- TCA_FQ_CODEL_LIMIT
 
- TCA_FQ_CODEL_MAX
 
- TCA_FQ_CODEL_MEMORY_LIMIT
 
- TCA_FQ_CODEL_QUANTUM
 
- TCA_FQ_CODEL_TARGET
 
- TCA_FQ_CODEL_UNSPEC
 
- TCA_FQ_CODEL_XSTATS_CLASS
 
- TCA_FQ_CODEL_XSTATS_QDISC
 
- TCA_FQ_FLOW_DEFAULT_RATE
 
- TCA_FQ_FLOW_MAX_RATE
 
- TCA_FQ_FLOW_PLIMIT
 
- TCA_FQ_FLOW_REFILL_DELAY
 
- TCA_FQ_INITIAL_QUANTUM
 
- TCA_FQ_LOW_RATE_THRESHOLD
 
- TCA_FQ_MAX
 
- TCA_FQ_ORPHAN_MASK
 
- TCA_FQ_PLIMIT
 
- TCA_FQ_QUANTUM
 
- TCA_FQ_RATE_ENABLE
 
- TCA_FQ_UNSPEC
 
- TCA_FW_ACT
 
- TCA_FW_CLASSID
 
- TCA_FW_INDEV
 
- TCA_FW_MASK
 
- TCA_FW_MAX
 
- TCA_FW_POLICE
 
- TCA_FW_UNSPEC
 
- TCA_GACT_MAX
 
- TCA_GACT_PAD
 
- TCA_GACT_PARMS
 
- TCA_GACT_PROB
 
- TCA_GACT_TM
 
- TCA_GACT_UNSPEC
 
- TCA_GRED_DPS
 
- TCA_GRED_LIMIT
 
- TCA_GRED_MAX
 
- TCA_GRED_MAX_P
 
- TCA_GRED_PARMS
 
- TCA_GRED_STAB
 
- TCA_GRED_UNSPEC
 
- TCA_GRED_VQ_DP
 
- TCA_GRED_VQ_ENTRY
 
- TCA_GRED_VQ_ENTRY_MAX
 
- TCA_GRED_VQ_ENTRY_UNSPEC
 
- TCA_GRED_VQ_FLAGS
 
- TCA_GRED_VQ_LIST
 
- TCA_GRED_VQ_MAX
 
- TCA_GRED_VQ_PAD
 
- TCA_GRED_VQ_STAT_BACKLOG
 
- TCA_GRED_VQ_STAT_BYTES
 
- TCA_GRED_VQ_STAT_FORCED_DROP
 
- TCA_GRED_VQ_STAT_FORCED_MARK
 
- TCA_GRED_VQ_STAT_OTHER
 
- TCA_GRED_VQ_STAT_PACKETS
 
- TCA_GRED_VQ_STAT_PDROP
 
- TCA_GRED_VQ_STAT_PROB_DROP
 
- TCA_GRED_VQ_STAT_PROB_MARK
 
- TCA_GRED_VQ_UNSPEC
 
- TCA_HFSC_FSC
 
- TCA_HFSC_MAX
 
- TCA_HFSC_RSC
 
- TCA_HFSC_UNSPEC
 
- TCA_HFSC_USC
 
- TCA_HHF_ADMIT_BYTES
 
- TCA_HHF_BACKLOG_LIMIT
 
- TCA_HHF_EVICT_TIMEOUT
 
- TCA_HHF_HH_FLOWS_LIMIT
 
- TCA_HHF_MAX
 
- TCA_HHF_NON_HH_WEIGHT
 
- TCA_HHF_QUANTUM
 
- TCA_HHF_RESET_TIMEOUT
 
- TCA_HHF_UNSPEC
 
- TCA_HTB_CEIL64
 
- TCA_HTB_CTAB
 
- TCA_HTB_DIRECT_QLEN
 
- TCA_HTB_INIT
 
- TCA_HTB_MAX
 
- TCA_HTB_PAD
 
- TCA_HTB_PARMS
 
- TCA_HTB_RATE64
 
- TCA_HTB_RTAB
 
- TCA_HTB_UNSPEC
 
- TCA_HW_OFFLOAD
 
- TCA_ID_BPF
 
- TCA_ID_CONNMARK
 
- TCA_ID_CSUM
 
- TCA_ID_CT
 
- TCA_ID_CTINFO
 
- TCA_ID_GACT
 
- TCA_ID_IFE
 
- TCA_ID_IPT
 
- TCA_ID_MAX
 
- TCA_ID_MIRRED
 
- TCA_ID_MPLS
 
- TCA_ID_NAT
 
- TCA_ID_PEDIT
 
- TCA_ID_POLICE
 
- TCA_ID_SAMPLE
 
- TCA_ID_SIMP
 
- TCA_ID_SKBEDIT
 
- TCA_ID_SKBMOD
 
- TCA_ID_TUNNEL_KEY
 
- TCA_ID_UNSPEC
 
- TCA_ID_VLAN
 
- TCA_ID_XT
 
- TCA_IFE_DMAC
 
- TCA_IFE_MAX
 
- TCA_IFE_METALST
 
- TCA_IFE_PAD
 
- TCA_IFE_PARMS
 
- TCA_IFE_SMAC
 
- TCA_IFE_TM
 
- TCA_IFE_TYPE
 
- TCA_IFE_UNSPEC
 
- TCA_INGRESS_BLOCK
 
- TCA_INGRESS_MIRROR
 
- TCA_INGRESS_REDIR
 
- TCA_IPT_CNT
 
- TCA_IPT_HOOK
 
- TCA_IPT_INDEX
 
- TCA_IPT_MAX
 
- TCA_IPT_PAD
 
- TCA_IPT_TABLE
 
- TCA_IPT_TARG
 
- TCA_IPT_TM
 
- TCA_IPT_UNSPEC
 
- TCA_KIND
 
- TCA_MATCHALL_ACT
 
- TCA_MATCHALL_CLASSID
 
- TCA_MATCHALL_FLAGS
 
- TCA_MATCHALL_MAX
 
- TCA_MATCHALL_PAD
 
- TCA_MATCHALL_PCNT
 
- TCA_MATCHALL_UNSPEC
 
- TCA_MAX
 
- TCA_MIRRED_MAX
 
- TCA_MIRRED_PAD
 
- TCA_MIRRED_PARMS
 
- TCA_MIRRED_TM
 
- TCA_MIRRED_UNSPEC
 
- TCA_MPLS_ACT_DEC_TTL
 
- TCA_MPLS_ACT_MODIFY
 
- TCA_MPLS_ACT_POP
 
- TCA_MPLS_ACT_PUSH
 
- TCA_MPLS_BOS
 
- TCA_MPLS_LABEL
 
- TCA_MPLS_MAX
 
- TCA_MPLS_PAD
 
- TCA_MPLS_PARMS
 
- TCA_MPLS_PROTO
 
- TCA_MPLS_TC
 
- TCA_MPLS_TM
 
- TCA_MPLS_TTL
 
- TCA_MPLS_UNSPEC
 
- TCA_MQPRIO_MAX
 
- TCA_MQPRIO_MAX_RATE64
 
- TCA_MQPRIO_MIN_RATE64
 
- TCA_MQPRIO_MODE
 
- TCA_MQPRIO_SHAPER
 
- TCA_MQPRIO_UNSPEC
 
- TCA_NAT_FLAG_EGRESS
 
- TCA_NAT_MAX
 
- TCA_NAT_PAD
 
- TCA_NAT_PARMS
 
- TCA_NAT_TM
 
- TCA_NAT_UNSPEC
 
- TCA_NETEM_CORR
 
- TCA_NETEM_CORRUPT
 
- TCA_NETEM_DELAY_DIST
 
- TCA_NETEM_ECN
 
- TCA_NETEM_JITTER64
 
- TCA_NETEM_LATENCY64
 
- TCA_NETEM_LOSS
 
- TCA_NETEM_MAX
 
- TCA_NETEM_PAD
 
- TCA_NETEM_RATE
 
- TCA_NETEM_RATE64
 
- TCA_NETEM_REORDER
 
- TCA_NETEM_SLOT
 
- TCA_NETEM_SLOT_DIST
 
- TCA_NETEM_UNSPEC
 
- TCA_OLD_COMPAT
 
- TCA_OPTIONS
 
- TCA_PAD
 
- TCA_PAYLOAD
 
- TCA_PEDIT_CMD_MAX
 
- TCA_PEDIT_HDR_TYPE_MAX
 
- TCA_PEDIT_KEYS_EX
 
- TCA_PEDIT_KEY_EX
 
- TCA_PEDIT_KEY_EX_CMD
 
- TCA_PEDIT_KEY_EX_CMD_ADD
 
- TCA_PEDIT_KEY_EX_CMD_SET
 
- TCA_PEDIT_KEY_EX_HDR_TYPE_ETH
 
- TCA_PEDIT_KEY_EX_HDR_TYPE_IP4
 
- TCA_PEDIT_KEY_EX_HDR_TYPE_IP6
 
- TCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK
 
- TCA_PEDIT_KEY_EX_HDR_TYPE_TCP
 
- TCA_PEDIT_KEY_EX_HDR_TYPE_UDP
 
- TCA_PEDIT_KEY_EX_HTYPE
 
- TCA_PEDIT_KEY_EX_MAX
 
- TCA_PEDIT_MAX
 
- TCA_PEDIT_PAD
 
- TCA_PEDIT_PARMS
 
- TCA_PEDIT_PARMS_EX
 
- TCA_PEDIT_TM
 
- TCA_PEDIT_UNSPEC
 
- TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK
 
- TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT
 
- TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK
 
- TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT
 
- TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK
 
- TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT
 
- TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK
 
- TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT
 
- TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK
 
- TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT
 
- TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK
 
- TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT
 
- TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK
 
- TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT
 
- TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK
 
- TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT
 
- TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK
 
- TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT
 
- TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK
 
- TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT
 
- TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK
 
- TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT
 
- TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK
 
- TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT
 
- TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK
 
- TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT
 
- TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK
 
- TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT
 
- TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK
 
- TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT
 
- TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK
 
- TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT
 
- TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK
 
- TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT
 
- TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK
 
- TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT
 
- TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK
 
- TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT
 
- TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK
 
- TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT
 
- TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK
 
- TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT
 
- TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK
 
- TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT
 
- TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK
 
- TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT
 
- TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK
 
- TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT
 
- TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK
 
- TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT
 
- TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK
 
- TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT
 
- TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK
 
- TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT
 
- TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK
 
- TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT
 
- TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK
 
- TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT
 
- TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK
 
- TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT
 
- TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK
 
- TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT
 
- TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK
 
- TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT
 
- TCA_PERF_SEL
 
- TCA_PERF_SEL_BUSY
 
- TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0
 
- TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1
 
- TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2
 
- TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3
 
- TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4
 
- TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5
 
- TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6
 
- TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7
 
- TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCS
 
- TCA_PERF_SEL_CROSSBAR_STALL_TCC0
 
- TCA_PERF_SEL_CROSSBAR_STALL_TCC1
 
- TCA_PERF_SEL_CROSSBAR_STALL_TCC2
 
- TCA_PERF_SEL_CROSSBAR_STALL_TCC3
 
- TCA_PERF_SEL_CROSSBAR_STALL_TCC4
 
- TCA_PERF_SEL_CROSSBAR_STALL_TCC5
 
- TCA_PERF_SEL_CROSSBAR_STALL_TCC6
 
- TCA_PERF_SEL_CROSSBAR_STALL_TCC7
 
- TCA_PERF_SEL_CROSSBAR_STALL_TCS
 
- TCA_PERF_SEL_CYCLE
 
- TCA_PERF_SEL_FORCED_HOLE_TCC0
 
- TCA_PERF_SEL_FORCED_HOLE_TCC1
 
- TCA_PERF_SEL_FORCED_HOLE_TCC2
 
- TCA_PERF_SEL_FORCED_HOLE_TCC3
 
- TCA_PERF_SEL_FORCED_HOLE_TCC4
 
- TCA_PERF_SEL_FORCED_HOLE_TCC5
 
- TCA_PERF_SEL_FORCED_HOLE_TCC6
 
- TCA_PERF_SEL_FORCED_HOLE_TCC7
 
- TCA_PERF_SEL_FORCED_HOLE_TCS
 
- TCA_PERF_SEL_NONE
 
- TCA_PERF_SEL_REQ_TCC0
 
- TCA_PERF_SEL_REQ_TCC1
 
- TCA_PERF_SEL_REQ_TCC2
 
- TCA_PERF_SEL_REQ_TCC3
 
- TCA_PERF_SEL_REQ_TCC4
 
- TCA_PERF_SEL_REQ_TCC5
 
- TCA_PERF_SEL_REQ_TCC6
 
- TCA_PERF_SEL_REQ_TCC7
 
- TCA_PERF_SEL_REQ_TCS
 
- TCA_PIE_ALPHA
 
- TCA_PIE_BETA
 
- TCA_PIE_BYTEMODE
 
- TCA_PIE_ECN
 
- TCA_PIE_LIMIT
 
- TCA_PIE_MAX
 
- TCA_PIE_TARGET
 
- TCA_PIE_TUPDATE
 
- TCA_PIE_UNSPEC
 
- TCA_POLICE_AVRATE
 
- TCA_POLICE_MAX
 
- TCA_POLICE_PAD
 
- TCA_POLICE_PEAKRATE
 
- TCA_POLICE_PEAKRATE64
 
- TCA_POLICE_RATE
 
- TCA_POLICE_RATE64
 
- TCA_POLICE_RESULT
 
- TCA_POLICE_TBF
 
- TCA_POLICE_TM
 
- TCA_POLICE_UNSPEC
 
- TCA_QFQ_LMAX
 
- TCA_QFQ_MAX
 
- TCA_QFQ_UNSPEC
 
- TCA_QFQ_WEIGHT
 
- TCA_RATE
 
- TCA_RED_MAX
 
- TCA_RED_MAX_P
 
- TCA_RED_PARMS
 
- TCA_RED_STAB
 
- TCA_RED_UNSPEC
 
- TCA_ROOT_COUNT
 
- TCA_ROOT_FLAGS
 
- TCA_ROOT_MAX
 
- TCA_ROOT_TAB
 
- TCA_ROOT_TIME_DELTA
 
- TCA_ROOT_UNSPEC
 
- TCA_ROUTE4_ACT
 
- TCA_ROUTE4_CLASSID
 
- TCA_ROUTE4_FROM
 
- TCA_ROUTE4_IIF
 
- TCA_ROUTE4_MAX
 
- TCA_ROUTE4_POLICE
 
- TCA_ROUTE4_TO
 
- TCA_ROUTE4_UNSPEC
 
- TCA_RSVP_ACT
 
- TCA_RSVP_CLASSID
 
- TCA_RSVP_DST
 
- TCA_RSVP_MAX
 
- TCA_RSVP_PINFO
 
- TCA_RSVP_POLICE
 
- TCA_RSVP_SRC
 
- TCA_RSVP_UNSPEC
 
- TCA_RTA
 
- TCA_SAMPLE_MAX
 
- TCA_SAMPLE_PAD
 
- TCA_SAMPLE_PARMS
 
- TCA_SAMPLE_PSAMPLE_GROUP
 
- TCA_SAMPLE_RATE
 
- TCA_SAMPLE_TM
 
- TCA_SAMPLE_TRUNC_SIZE
 
- TCA_SAMPLE_UNSPEC
 
- TCA_SFB_MAX
 
- TCA_SFB_PARMS
 
- TCA_SFB_UNSPEC
 
- TCA_SKBEDIT_FLAGS
 
- TCA_SKBEDIT_MARK
 
- TCA_SKBEDIT_MASK
 
- TCA_SKBEDIT_MAX
 
- TCA_SKBEDIT_PAD
 
- TCA_SKBEDIT_PARMS
 
- TCA_SKBEDIT_PRIORITY
 
- TCA_SKBEDIT_PTYPE
 
- TCA_SKBEDIT_QUEUE_MAPPING
 
- TCA_SKBEDIT_TM
 
- TCA_SKBEDIT_UNSPEC
 
- TCA_SKBMOD_DMAC
 
- TCA_SKBMOD_ETYPE
 
- TCA_SKBMOD_MAX
 
- TCA_SKBMOD_PAD
 
- TCA_SKBMOD_PARMS
 
- TCA_SKBMOD_SMAC
 
- TCA_SKBMOD_TM
 
- TCA_SKBMOD_UNSPEC
 
- TCA_STAB
 
- TCA_STAB_BASE
 
- TCA_STAB_DATA
 
- TCA_STAB_MAX
 
- TCA_STAB_UNSPEC
 
- TCA_STATS
 
- TCA_STATS2
 
- TCA_STATS_APP
 
- TCA_STATS_BASIC
 
- TCA_STATS_BASIC_HW
 
- TCA_STATS_MAX
 
- TCA_STATS_PAD
 
- TCA_STATS_QUEUE
 
- TCA_STATS_RATE_EST
 
- TCA_STATS_RATE_EST64
 
- TCA_STATS_UNSPEC
 
- TCA_TAPRIO_ATTR_ADMIN_SCHED
 
- TCA_TAPRIO_ATTR_FLAGS
 
- TCA_TAPRIO_ATTR_FLAG_FULL_OFFLOAD
 
- TCA_TAPRIO_ATTR_FLAG_TXTIME_ASSIST
 
- TCA_TAPRIO_ATTR_MAX
 
- TCA_TAPRIO_ATTR_PRIOMAP
 
- TCA_TAPRIO_ATTR_SCHED_BASE_TIME
 
- TCA_TAPRIO_ATTR_SCHED_CLOCKID
 
- TCA_TAPRIO_ATTR_SCHED_CYCLE_TIME
 
- TCA_TAPRIO_ATTR_SCHED_CYCLE_TIME_EXTENSION
 
- TCA_TAPRIO_ATTR_SCHED_ENTRY_LIST
 
- TCA_TAPRIO_ATTR_SCHED_SINGLE_ENTRY
 
- TCA_TAPRIO_ATTR_TXTIME_DELAY
 
- TCA_TAPRIO_ATTR_UNSPEC
 
- TCA_TAPRIO_PAD
 
- TCA_TAPRIO_SCHED_ENTRY
 
- TCA_TAPRIO_SCHED_ENTRY_CMD
 
- TCA_TAPRIO_SCHED_ENTRY_GATE_MASK
 
- TCA_TAPRIO_SCHED_ENTRY_INDEX
 
- TCA_TAPRIO_SCHED_ENTRY_INTERVAL
 
- TCA_TAPRIO_SCHED_ENTRY_MAX
 
- TCA_TAPRIO_SCHED_ENTRY_UNSPEC
 
- TCA_TAPRIO_SCHED_MAX
 
- TCA_TAPRIO_SCHED_UNSPEC
 
- TCA_TBF_BURST
 
- TCA_TBF_MAX
 
- TCA_TBF_PAD
 
- TCA_TBF_PARMS
 
- TCA_TBF_PBURST
 
- TCA_TBF_PRATE64
 
- TCA_TBF_PTAB
 
- TCA_TBF_RATE64
 
- TCA_TBF_RTAB
 
- TCA_TBF_UNSPEC
 
- TCA_TCINDEX_ACT
 
- TCA_TCINDEX_CLASSID
 
- TCA_TCINDEX_FALL_THROUGH
 
- TCA_TCINDEX_HASH
 
- TCA_TCINDEX_MASK
 
- TCA_TCINDEX_MAX
 
- TCA_TCINDEX_POLICE
 
- TCA_TCINDEX_SHIFT
 
- TCA_TCINDEX_UNSPEC
 
- TCA_TUNNEL_KEY_ACT_RELEASE
 
- TCA_TUNNEL_KEY_ACT_SET
 
- TCA_TUNNEL_KEY_ENC_DST_PORT
 
- TCA_TUNNEL_KEY_ENC_IPV4_DST
 
- TCA_TUNNEL_KEY_ENC_IPV4_SRC
 
- TCA_TUNNEL_KEY_ENC_IPV6_DST
 
- TCA_TUNNEL_KEY_ENC_IPV6_SRC
 
- TCA_TUNNEL_KEY_ENC_KEY_ID
 
- TCA_TUNNEL_KEY_ENC_OPTS
 
- TCA_TUNNEL_KEY_ENC_OPTS_GENEVE
 
- TCA_TUNNEL_KEY_ENC_OPTS_MAX
 
- TCA_TUNNEL_KEY_ENC_OPTS_UNSPEC
 
- TCA_TUNNEL_KEY_ENC_OPT_GENEVE_CLASS
 
- TCA_TUNNEL_KEY_ENC_OPT_GENEVE_DATA
 
- TCA_TUNNEL_KEY_ENC_OPT_GENEVE_MAX
 
- TCA_TUNNEL_KEY_ENC_OPT_GENEVE_TYPE
 
- TCA_TUNNEL_KEY_ENC_OPT_GENEVE_UNSPEC
 
- TCA_TUNNEL_KEY_ENC_TOS
 
- TCA_TUNNEL_KEY_ENC_TTL
 
- TCA_TUNNEL_KEY_MAX
 
- TCA_TUNNEL_KEY_NO_CSUM
 
- TCA_TUNNEL_KEY_PAD
 
- TCA_TUNNEL_KEY_PARMS
 
- TCA_TUNNEL_KEY_TM
 
- TCA_TUNNEL_KEY_UNSPEC
 
- TCA_U32_ACT
 
- TCA_U32_CLASSID
 
- TCA_U32_DIVISOR
 
- TCA_U32_FLAGS
 
- TCA_U32_HASH
 
- TCA_U32_INDEV
 
- TCA_U32_LINK
 
- TCA_U32_MARK
 
- TCA_U32_MAX
 
- TCA_U32_PAD
 
- TCA_U32_PCNT
 
- TCA_U32_POLICE
 
- TCA_U32_SEL
 
- TCA_U32_UNSPEC
 
- TCA_UNSPEC
 
- TCA_VLAN_ACT_MODIFY
 
- TCA_VLAN_ACT_POP
 
- TCA_VLAN_ACT_PUSH
 
- TCA_VLAN_MAX
 
- TCA_VLAN_PAD
 
- TCA_VLAN_PARMS
 
- TCA_VLAN_PUSH_VLAN_ID
 
- TCA_VLAN_PUSH_VLAN_PRIORITY
 
- TCA_VLAN_PUSH_VLAN_PROTOCOL
 
- TCA_VLAN_TM
 
- TCA_VLAN_UNSPEC
 
- TCA_XSTATS
 
- TCAdapter
 
- TCB
 
- TCBContextBlk
 
- TCBData
 
- TCBIND_CURTC
 
- TCBIND_CURTC_SHIFT
 
- TCBIND_CURVPE
 
- TCBIND_CURVPE_SHIFT
 
- TCBR
 
- TCBS
 
- TCBS_BUFFSIZE_1024K
 
- TCBS_BUFFSIZE_128K
 
- TCBS_BUFFSIZE_16K
 
- TCBS_BUFFSIZE_2048K
 
- TCBS_BUFFSIZE_256K
 
- TCBS_BUFFSIZE_32K
 
- TCBS_BUFFSIZE_512K
 
- TCBS_BUFFSIZE_64K
 
- TCBS_MASK
 
- TCB_COOKIE_G
 
- TCB_COOKIE_M
 
- TCB_COOKIE_S
 
- TCB_COOKIE_V
 
- TCB_MASK
 
- TCB_OP
 
- TCB_PDU_HDR_LEN_W
 
- TCB_RQ_START_M
 
- TCB_RQ_START_S
 
- TCB_RQ_START_V
 
- TCB_RQ_START_W
 
- TCB_RSS_INFO_M
 
- TCB_RSS_INFO_S
 
- TCB_RSS_INFO_V
 
- TCB_RSS_INFO_W
 
- TCB_RTT_TS_RECENT_AGE_M
 
- TCB_RTT_TS_RECENT_AGE_S
 
- TCB_RTT_TS_RECENT_AGE_V
 
- TCB_RTT_TS_RECENT_AGE_W
 
- TCB_RX_FRAG2_PTR_RAW_W
 
- TCB_RX_FRAG3_LEN_RAW_W
 
- TCB_RX_FRAG3_START_IDX_OFFSET_RAW_W
 
- TCB_SIZE
 
- TCB_SMAC_SEL_M
 
- TCB_SMAC_SEL_S
 
- TCB_SMAC_SEL_V
 
- TCB_SMAC_SEL_W
 
- TCB_SND_UNA_RAW_W
 
- TCB_TIMESTAMP_M
 
- TCB_TIMESTAMP_S
 
- TCB_TIMESTAMP_V
 
- TCB_TIMESTAMP_W
 
- TCB_T_FLAGS_M
 
- TCB_T_FLAGS_S
 
- TCB_T_FLAGS_V
 
- TCB_T_FLAGS_W
 
- TCB_ULP_RAW_M
 
- TCB_ULP_RAW_S
 
- TCB_ULP_RAW_V
 
- TCB_ULP_RAW_W
 
- TCB_ULP_TYPE_M
 
- TCB_ULP_TYPE_S
 
- TCB_ULP_TYPE_V
 
- TCB_ULP_TYPE_W
 
- TCB_WORDS
 
- TCB_WORD_S
 
- TCB_WORD_V
 
- TCCB_FORMAT_DEFAULT
 
- TCCB_MAX_DCW
 
- TCCB_MAX_SIZE
 
- TCCB_SAC_DEFAULT
 
- TCCB_SAC_INTRG
 
- TCCHEN
 
- TCCMODE
 
- TCCR
 
- TCCR_BIT
 
- TCCR_IP
 
- TCCR_TCP
 
- TCCR_TFEN
 
- TCCR_TFR
 
- TCCR_TOG
 
- TCCR_TSRQ0
 
- TCCR_TSRQ1
 
- TCCR_TSRQ2
 
- TCCR_TSRQ3
 
- TCCR_UDP
 
- TCC_CACHE_POLICIES
 
- TCC_CACHE_POLICY_BYPASS
 
- TCC_CACHE_POLICY_LRU
 
- TCC_CACHE_POLICY_STREAM
 
- TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK
 
- TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT
 
- TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK
 
- TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT
 
- TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK
 
- TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT
 
- TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK
 
- TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT
 
- TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK
 
- TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT
 
- TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK
 
- TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT
 
- TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK
 
- TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT
 
- TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK
 
- TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT
 
- TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK
 
- TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT
 
- TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK
 
- TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT
 
- TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK
 
- TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT
 
- TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK
 
- TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT
 
- TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK
 
- TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT
 
- TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK
 
- TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT
 
- TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK
 
- TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT
 
- TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK
 
- TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT
 
- TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK
 
- TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT
 
- TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK
 
- TCC_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT
 
- TCC_CTRL2__PROBE_FIFO_SIZE_MASK
 
- TCC_CTRL2__PROBE_FIFO_SIZE__SHIFT
 
- TCC_CTRL__CACHE_SIZE_MASK
 
- TCC_CTRL__CACHE_SIZE__SHIFT
 
- TCC_CTRL__LATENCY_FIFO_SIZE_MASK
 
- TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT
 
- TCC_CTRL__LINEAR_SET_HASH_MASK
 
- TCC_CTRL__LINEAR_SET_HASH__SHIFT
 
- TCC_CTRL__MDC_SECTOR_SIZE_MASK
 
- TCC_CTRL__MDC_SECTOR_SIZE__SHIFT
 
- TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK
 
- TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT
 
- TCC_CTRL__MDC_SIZE_MASK
 
- TCC_CTRL__MDC_SIZE__SHIFT
 
- TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK
 
- TCC_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT
 
- TCC_CTRL__RATE_MASK
 
- TCC_CTRL__RATE__SHIFT
 
- TCC_CTRL__SRC_FIFO_SIZE_MASK
 
- TCC_CTRL__SRC_FIFO_SIZE__SHIFT
 
- TCC_CTRL__WB_OR_INV_ALL_VMIDS_MASK
 
- TCC_CTRL__WB_OR_INV_ALL_VMIDS__SHIFT
 
- TCC_CTRL__WRITEBACK_MARGIN_MASK
 
- TCC_CTRL__WRITEBACK_MARGIN__SHIFT
 
- TCC_DISABLE_MASK
 
- TCC_DISABLE_SHIFT
 
- TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT_MASK
 
- TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_ENABLE_ERROR_INJECT__SHIFT
 
- TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY_MASK
 
- TCC_DSM_CNTL2A__CACHE_TAG_PROBE_FIFO_SELECT_INJECT_DELAY__SHIFT
 
- TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT_MASK
 
- TCC_DSM_CNTL2A__IN_USE_DEC_ENABLE_ERROR_INJECT__SHIFT
 
- TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY_MASK
 
- TCC_DSM_CNTL2A__IN_USE_DEC_SELECT_INJECT_DELAY__SHIFT
 
- TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT_MASK
 
- TCC_DSM_CNTL2A__IN_USE_TRANSFER_ENABLE_ERROR_INJECT__SHIFT
 
- TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY_MASK
 
- TCC_DSM_CNTL2A__IN_USE_TRANSFER_SELECT_INJECT_DELAY__SHIFT
 
- TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT_MASK
 
- TCC_DSM_CNTL2A__RETURN_CONTROL_ENABLE_ERROR_INJECT__SHIFT
 
- TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY_MASK
 
- TCC_DSM_CNTL2A__RETURN_CONTROL_SELECT_INJECT_DELAY__SHIFT
 
- TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT_MASK
 
- TCC_DSM_CNTL2A__RETURN_DATA_ENABLE_ERROR_INJECT__SHIFT
 
- TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY_MASK
 
- TCC_DSM_CNTL2A__RETURN_DATA_SELECT_INJECT_DELAY__SHIFT
 
- TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT_MASK
 
- TCC_DSM_CNTL2A__SRC_FIFO_ENABLE_ERROR_INJECT__SHIFT
 
- TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK
 
- TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT
 
- TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK
 
- TCC_DSM_CNTL2A__SRC_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT
 
- TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY_MASK
 
- TCC_DSM_CNTL2A__SRC_FIFO_SELECT_INJECT_DELAY__SHIFT
 
- TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT_MASK
 
- TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_ENABLE_ERROR_INJECT__SHIFT
 
- TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY_MASK
 
- TCC_DSM_CNTL2A__UC_ATOMIC_FIFO_SELECT_INJECT_DELAY__SHIFT
 
- TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT_MASK
 
- TCC_DSM_CNTL2A__WRITE_CACHE_READ_ENABLE_ERROR_INJECT__SHIFT
 
- TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY_MASK
 
- TCC_DSM_CNTL2A__WRITE_CACHE_READ_SELECT_INJECT_DELAY__SHIFT
 
- TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT_MASK
 
- TCC_DSM_CNTL2A__WRITE_RETURN_ENABLE_ERROR_INJECT__SHIFT
 
- TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY_MASK
 
- TCC_DSM_CNTL2A__WRITE_RETURN_SELECT_INJECT_DELAY__SHIFT
 
- TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT_MASK
 
- TCC_DSM_CNTL2B__LATENCY_FIFO_ENABLE_ERROR_INJECT__SHIFT
 
- TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT_MASK
 
- TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_ENABLE_ERROR_INJECT__SHIFT
 
- TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY_MASK
 
- TCC_DSM_CNTL2B__LATENCY_FIFO_NEXT_RAM_SELECT_INJECT_DELAY__SHIFT
 
- TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY_MASK
 
- TCC_DSM_CNTL2B__LATENCY_FIFO_SELECT_INJECT_DELAY__SHIFT
 
- TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT_MASK
 
- TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_ENABLE_ERROR_INJECT__SHIFT
 
- TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY_MASK
 
- TCC_DSM_CNTL2__CACHE_DATA_BANK_0_1_SELECT_INJECT_DELAY__SHIFT
 
- TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT_MASK
 
- TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_ENABLE_ERROR_INJECT__SHIFT
 
- TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY_MASK
 
- TCC_DSM_CNTL2__CACHE_DATA_BANK_1_0_SELECT_INJECT_DELAY__SHIFT
 
- TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT_MASK
 
- TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_ENABLE_ERROR_INJECT__SHIFT
 
- TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY_MASK
 
- TCC_DSM_CNTL2__CACHE_DATA_BANK_1_1_SELECT_INJECT_DELAY__SHIFT
 
- TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT_MASK
 
- TCC_DSM_CNTL2__CACHE_DATA_ENABLE_ERROR_INJECT__SHIFT
 
- TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY_MASK
 
- TCC_DSM_CNTL2__CACHE_DATA_SELECT_INJECT_DELAY__SHIFT
 
- TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT_MASK
 
- TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_ENABLE_ERROR_INJECT__SHIFT
 
- TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY_MASK
 
- TCC_DSM_CNTL2__CACHE_DIRTY_BANK_0_SELECT_INJECT_DELAY__SHIFT
 
- TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT_MASK
 
- TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_ENABLE_ERROR_INJECT__SHIFT
 
- TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY_MASK
 
- TCC_DSM_CNTL2__CACHE_DIRTY_BANK_1_SELECT_INJECT_DELAY__SHIFT
 
- TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT_MASK
 
- TCC_DSM_CNTL2__HIGH_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT
 
- TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY_MASK
 
- TCC_DSM_CNTL2__HIGH_RATE_TAG_SELECT_INJECT_DELAY__SHIFT
 
- TCC_DSM_CNTL2__INJECT_DELAY_MASK
 
- TCC_DSM_CNTL2__INJECT_DELAY__SHIFT
 
- TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT_MASK
 
- TCC_DSM_CNTL2__LOW_RATE_TAG_ENABLE_ERROR_INJECT__SHIFT
 
- TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY_MASK
 
- TCC_DSM_CNTL2__LOW_RATE_TAG_SELECT_INJECT_DELAY__SHIFT
 
- TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL_MASK
 
- TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_DATA_SEL__SHIFT
 
- TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE_MASK
 
- TCC_DSM_CNTLA__CACHE_TAG_PROBE_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT
 
- TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL_MASK
 
- TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_DATA_SEL__SHIFT
 
- TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE_MASK
 
- TCC_DSM_CNTLA__LATENCY_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT
 
- TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK
 
- TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT
 
- TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK
 
- TCC_DSM_CNTLA__LATENCY_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT
 
- TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL_MASK
 
- TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_DATA_SEL__SHIFT
 
- TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE_MASK
 
- TCC_DSM_CNTLA__RETURN_CONTROL_IRRITATOR_SINGLE_WRITE__SHIFT
 
- TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL_MASK
 
- TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_DATA_SEL__SHIFT
 
- TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE_MASK
 
- TCC_DSM_CNTLA__RETURN_DATA_IRRITATOR_SINGLE_WRITE__SHIFT
 
- TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL_MASK
 
- TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_DATA_SEL__SHIFT
 
- TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE_MASK
 
- TCC_DSM_CNTLA__SRC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT
 
- TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL_MASK
 
- TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_DATA_SEL__SHIFT
 
- TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE_MASK
 
- TCC_DSM_CNTLA__SRC_FIFO_NEXT_RAM_IRRITATOR_SINGLE_WRITE__SHIFT
 
- TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL_MASK
 
- TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_DATA_SEL__SHIFT
 
- TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE_MASK
 
- TCC_DSM_CNTLA__UC_ATOMIC_FIFO_IRRITATOR_SINGLE_WRITE__SHIFT
 
- TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL_MASK
 
- TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_DATA_SEL__SHIFT
 
- TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE_MASK
 
- TCC_DSM_CNTLA__WRITE_CACHE_READ_IRRITATOR_SINGLE_WRITE__SHIFT
 
- TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL_MASK
 
- TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_DATA_SEL__SHIFT
 
- TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE_MASK
 
- TCC_DSM_CNTLA__WRITE_RETURN_IRRITATOR_SINGLE_WRITE__SHIFT
 
- TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL_MASK
 
- TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_DATA_SEL__SHIFT
 
- TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE_MASK
 
- TCC_DSM_CNTL__CACHE_DATA_BANK_0_1_IRRITATOR_SINGLE_WRITE__SHIFT
 
- TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL_MASK
 
- TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_DATA_SEL__SHIFT
 
- TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE_MASK
 
- TCC_DSM_CNTL__CACHE_DATA_BANK_1_0_IRRITATOR_SINGLE_WRITE__SHIFT
 
- TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL_MASK
 
- TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_DATA_SEL__SHIFT
 
- TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE_MASK
 
- TCC_DSM_CNTL__CACHE_DATA_BANK_1_1_IRRITATOR_SINGLE_WRITE__SHIFT
 
- TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL_MASK
 
- TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_DATA_SEL__SHIFT
 
- TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE_MASK
 
- TCC_DSM_CNTL__CACHE_DATA_IRRITATOR_SINGLE_WRITE__SHIFT
 
- TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL_MASK
 
- TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_DATA_SEL__SHIFT
 
- TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE_MASK
 
- TCC_DSM_CNTL__CACHE_DIRTY_BANK_0_IRRITATOR_SINGLE_WRITE__SHIFT
 
- TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL_MASK
 
- TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_DATA_SEL__SHIFT
 
- TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE_MASK
 
- TCC_DSM_CNTL__CACHE_DIRTY_BANK_1_IRRITATOR_SINGLE_WRITE__SHIFT
 
- TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK
 
- TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT
 
- TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK
 
- TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT
 
- TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL_MASK
 
- TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT
 
- TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK
 
- TCC_DSM_CNTL__HIGH_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT
 
- TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL_MASK
 
- TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_DATA_SEL__SHIFT
 
- TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE_MASK
 
- TCC_DSM_CNTL__IN_USE_DEC_IRRITATOR_SINGLE_WRITE__SHIFT
 
- TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL_MASK
 
- TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_DATA_SEL__SHIFT
 
- TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE_MASK
 
- TCC_DSM_CNTL__IN_USE_TRANSFER_IRRITATOR_SINGLE_WRITE__SHIFT
 
- TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL_MASK
 
- TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_DATA_SEL__SHIFT
 
- TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE_MASK
 
- TCC_DSM_CNTL__LOW_RATE_TAG_IRRITATOR_SINGLE_WRITE__SHIFT
 
- TCC_EDC_CNT2__ATOMIC_RETURN_BUFFER_SED_COUNT_MASK
 
- TCC_EDC_CNT2__ATOMIC_RETURN_BUFFER_SED_COUNT__SHIFT
 
- TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT_MASK
 
- TCC_EDC_CNT2__CACHE_TAG_PROBE_FIFO_SED_COUNT__SHIFT
 
- TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT_MASK
 
- TCC_EDC_CNT2__LATENCY_FIFO_NEXT_RAM_SED_COUNT__SHIFT
 
- TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT_MASK
 
- TCC_EDC_CNT2__SRC_FIFO_NEXT_RAM_SED_COUNT__SHIFT
 
- TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT_MASK
 
- TCC_EDC_CNT2__WRITE_CACHE_READ_SED_COUNT__SHIFT
 
- TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT_MASK
 
- TCC_EDC_CNT2__WRITE_RETURN_SED_COUNT__SHIFT
 
- TCC_EDC_CNT2__WRRET_TAG_WRITE_RETURN_SED_COUNT_MASK
 
- TCC_EDC_CNT2__WRRET_TAG_WRITE_RETURN_SED_COUNT__SHIFT
 
- TCC_EDC_CNT__CACHE_DATA_DED_COUNT_MASK
 
- TCC_EDC_CNT__CACHE_DATA_DED_COUNT__SHIFT
 
- TCC_EDC_CNT__CACHE_DATA_SEC_COUNT_MASK
 
- TCC_EDC_CNT__CACHE_DATA_SEC_COUNT__SHIFT
 
- TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT_MASK
 
- TCC_EDC_CNT__CACHE_DIRTY_DED_COUNT__SHIFT
 
- TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT_MASK
 
- TCC_EDC_CNT__CACHE_DIRTY_SEC_COUNT__SHIFT
 
- TCC_EDC_CNT__DED_COUNT_MASK
 
- TCC_EDC_CNT__DED_COUNT__SHIFT
 
- TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT_MASK
 
- TCC_EDC_CNT__HIGH_RATE_TAG_DED_COUNT__SHIFT
 
- TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT_MASK
 
- TCC_EDC_CNT__HIGH_RATE_TAG_SEC_COUNT__SHIFT
 
- TCC_EDC_CNT__IN_USE_DEC_SED_COUNT_MASK
 
- TCC_EDC_CNT__IN_USE_DEC_SED_COUNT__SHIFT
 
- TCC_EDC_CNT__IN_USE_TRANSFER_SED_COUNT_MASK
 
- TCC_EDC_CNT__IN_USE_TRANSFER_SED_COUNT__SHIFT
 
- TCC_EDC_CNT__LATENCY_FIFO_SED_COUNT_MASK
 
- TCC_EDC_CNT__LATENCY_FIFO_SED_COUNT__SHIFT
 
- TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT_MASK
 
- TCC_EDC_CNT__LOW_RATE_TAG_DED_COUNT__SHIFT
 
- TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT_MASK
 
- TCC_EDC_CNT__LOW_RATE_TAG_SEC_COUNT__SHIFT
 
- TCC_EDC_CNT__RETURN_CONTROL_SED_COUNT_MASK
 
- TCC_EDC_CNT__RETURN_CONTROL_SED_COUNT__SHIFT
 
- TCC_EDC_CNT__RETURN_DATA_SED_COUNT_MASK
 
- TCC_EDC_CNT__RETURN_DATA_SED_COUNT__SHIFT
 
- TCC_EDC_CNT__SEC_COUNT_MASK
 
- TCC_EDC_CNT__SEC_COUNT__SHIFT
 
- TCC_EDC_CNT__SRC_FIFO_DED_COUNT_MASK
 
- TCC_EDC_CNT__SRC_FIFO_DED_COUNT__SHIFT
 
- TCC_EDC_CNT__SRC_FIFO_SEC_COUNT_MASK
 
- TCC_EDC_CNT__SRC_FIFO_SEC_COUNT__SHIFT
 
- TCC_EDC_CNT__UC_ATOMIC_FIFO_SED_COUNT_MASK
 
- TCC_EDC_CNT__UC_ATOMIC_FIFO_SED_COUNT__SHIFT
 
- TCC_EDC_COUNTER__DED_COUNT_MASK
 
- TCC_EDC_COUNTER__DED_COUNT__SHIFT
 
- TCC_EDC_COUNTER__SEC_COUNT_MASK
 
- TCC_EDC_COUNTER__SEC_COUNT__SHIFT
 
- TCC_EXE_DISABLE__EXE_DISABLE_MASK
 
- TCC_EXE_DISABLE__EXE_DISABLE__SHIFT
 
- TCC_MASK
 
- TCC_MTYPE
 
- TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK
 
- TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT
 
- TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK
 
- TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT
 
- TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK
 
- TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT
 
- TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK
 
- TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT
 
- TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK
 
- TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT
 
- TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK
 
- TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT
 
- TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK
 
- TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT
 
- TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK
 
- TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT
 
- TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK
 
- TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT
 
- TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK
 
- TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT
 
- TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK
 
- TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT
 
- TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK
 
- TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT
 
- TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK
 
- TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT
 
- TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK
 
- TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT
 
- TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK
 
- TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT
 
- TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK
 
- TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT
 
- TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK
 
- TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT
 
- TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK
 
- TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT
 
- TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK
 
- TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT
 
- TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK
 
- TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT
 
- TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK
 
- TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT
 
- TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK
 
- TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT
 
- TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK
 
- TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT
 
- TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK
 
- TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT
 
- TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK
 
- TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT
 
- TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK
 
- TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT
 
- TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK
 
- TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT
 
- TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK
 
- TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT
 
- TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK
 
- TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT
 
- TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK
 
- TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT
 
- TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK
 
- TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT
 
- TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK
 
- TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT
 
- TCC_PERF_SEL
 
- TCC_PERF_SEL_ALL_TC_OP_INV_EVICT
 
- TCC_PERF_SEL_ALL_TC_OP_INV_VOL_EVICT
 
- TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE
 
- TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH
 
- TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START
 
- TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_CYCLE
 
- TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_FINISH
 
- TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START
 
- TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK
 
- TCC_PERF_SEL_ATOMIC
 
- TCC_PERF_SEL_BUBBLE
 
- TCC_PERF_SEL_BUSY
 
- TCC_PERF_SEL_CC_PHYSICAL_REQ
 
- TCC_PERF_SEL_CLIENT0_REQ
 
- TCC_PERF_SEL_CLIENT100_REQ
 
- TCC_PERF_SEL_CLIENT101_REQ
 
- TCC_PERF_SEL_CLIENT102_REQ
 
- TCC_PERF_SEL_CLIENT103_REQ
 
- TCC_PERF_SEL_CLIENT104_REQ
 
- TCC_PERF_SEL_CLIENT105_REQ
 
- TCC_PERF_SEL_CLIENT106_REQ
 
- TCC_PERF_SEL_CLIENT107_REQ
 
- TCC_PERF_SEL_CLIENT108_REQ
 
- TCC_PERF_SEL_CLIENT109_REQ
 
- TCC_PERF_SEL_CLIENT10_REQ
 
- TCC_PERF_SEL_CLIENT110_REQ
 
- TCC_PERF_SEL_CLIENT111_REQ
 
- TCC_PERF_SEL_CLIENT112_REQ
 
- TCC_PERF_SEL_CLIENT113_REQ
 
- TCC_PERF_SEL_CLIENT114_REQ
 
- TCC_PERF_SEL_CLIENT115_REQ
 
- TCC_PERF_SEL_CLIENT116_REQ
 
- TCC_PERF_SEL_CLIENT117_REQ
 
- TCC_PERF_SEL_CLIENT118_REQ
 
- TCC_PERF_SEL_CLIENT119_REQ
 
- TCC_PERF_SEL_CLIENT11_REQ
 
- TCC_PERF_SEL_CLIENT120_REQ
 
- TCC_PERF_SEL_CLIENT121_REQ
 
- TCC_PERF_SEL_CLIENT122_REQ
 
- TCC_PERF_SEL_CLIENT123_REQ
 
- TCC_PERF_SEL_CLIENT124_REQ
 
- TCC_PERF_SEL_CLIENT125_REQ
 
- TCC_PERF_SEL_CLIENT126_REQ
 
- TCC_PERF_SEL_CLIENT127_REQ
 
- TCC_PERF_SEL_CLIENT12_REQ
 
- TCC_PERF_SEL_CLIENT13_REQ
 
- TCC_PERF_SEL_CLIENT14_REQ
 
- TCC_PERF_SEL_CLIENT15_REQ
 
- TCC_PERF_SEL_CLIENT16_REQ
 
- TCC_PERF_SEL_CLIENT17_REQ
 
- TCC_PERF_SEL_CLIENT18_REQ
 
- TCC_PERF_SEL_CLIENT19_REQ
 
- TCC_PERF_SEL_CLIENT1_REQ
 
- TCC_PERF_SEL_CLIENT20_REQ
 
- TCC_PERF_SEL_CLIENT21_REQ
 
- TCC_PERF_SEL_CLIENT22_REQ
 
- TCC_PERF_SEL_CLIENT23_REQ
 
- TCC_PERF_SEL_CLIENT24_REQ
 
- TCC_PERF_SEL_CLIENT25_REQ
 
- TCC_PERF_SEL_CLIENT26_REQ
 
- TCC_PERF_SEL_CLIENT27_REQ
 
- TCC_PERF_SEL_CLIENT28_REQ
 
- TCC_PERF_SEL_CLIENT29_REQ
 
- TCC_PERF_SEL_CLIENT2_REQ
 
- TCC_PERF_SEL_CLIENT30_REQ
 
- TCC_PERF_SEL_CLIENT31_REQ
 
- TCC_PERF_SEL_CLIENT32_REQ
 
- TCC_PERF_SEL_CLIENT33_REQ
 
- TCC_PERF_SEL_CLIENT34_REQ
 
- TCC_PERF_SEL_CLIENT35_REQ
 
- TCC_PERF_SEL_CLIENT36_REQ
 
- TCC_PERF_SEL_CLIENT37_REQ
 
- TCC_PERF_SEL_CLIENT38_REQ
 
- TCC_PERF_SEL_CLIENT39_REQ
 
- TCC_PERF_SEL_CLIENT3_REQ
 
- TCC_PERF_SEL_CLIENT40_REQ
 
- TCC_PERF_SEL_CLIENT41_REQ
 
- TCC_PERF_SEL_CLIENT42_REQ
 
- TCC_PERF_SEL_CLIENT43_REQ
 
- TCC_PERF_SEL_CLIENT44_REQ
 
- TCC_PERF_SEL_CLIENT45_REQ
 
- TCC_PERF_SEL_CLIENT46_REQ
 
- TCC_PERF_SEL_CLIENT47_REQ
 
- TCC_PERF_SEL_CLIENT48_REQ
 
- TCC_PERF_SEL_CLIENT49_REQ
 
- TCC_PERF_SEL_CLIENT4_REQ
 
- TCC_PERF_SEL_CLIENT50_REQ
 
- TCC_PERF_SEL_CLIENT51_REQ
 
- TCC_PERF_SEL_CLIENT52_REQ
 
- TCC_PERF_SEL_CLIENT53_REQ
 
- TCC_PERF_SEL_CLIENT54_REQ
 
- TCC_PERF_SEL_CLIENT55_REQ
 
- TCC_PERF_SEL_CLIENT56_REQ
 
- TCC_PERF_SEL_CLIENT57_REQ
 
- TCC_PERF_SEL_CLIENT58_REQ
 
- TCC_PERF_SEL_CLIENT59_REQ
 
- TCC_PERF_SEL_CLIENT5_REQ
 
- TCC_PERF_SEL_CLIENT60_REQ
 
- TCC_PERF_SEL_CLIENT61_REQ
 
- TCC_PERF_SEL_CLIENT62_REQ
 
- TCC_PERF_SEL_CLIENT63_REQ
 
- TCC_PERF_SEL_CLIENT64_REQ
 
- TCC_PERF_SEL_CLIENT65_REQ
 
- TCC_PERF_SEL_CLIENT66_REQ
 
- TCC_PERF_SEL_CLIENT67_REQ
 
- TCC_PERF_SEL_CLIENT68_REQ
 
- TCC_PERF_SEL_CLIENT69_REQ
 
- TCC_PERF_SEL_CLIENT6_REQ
 
- TCC_PERF_SEL_CLIENT70_REQ
 
- TCC_PERF_SEL_CLIENT71_REQ
 
- TCC_PERF_SEL_CLIENT72_REQ
 
- TCC_PERF_SEL_CLIENT73_REQ
 
- TCC_PERF_SEL_CLIENT74_REQ
 
- TCC_PERF_SEL_CLIENT75_REQ
 
- TCC_PERF_SEL_CLIENT76_REQ
 
- TCC_PERF_SEL_CLIENT77_REQ
 
- TCC_PERF_SEL_CLIENT78_REQ
 
- TCC_PERF_SEL_CLIENT79_REQ
 
- TCC_PERF_SEL_CLIENT7_REQ
 
- TCC_PERF_SEL_CLIENT80_REQ
 
- TCC_PERF_SEL_CLIENT81_REQ
 
- TCC_PERF_SEL_CLIENT82_REQ
 
- TCC_PERF_SEL_CLIENT83_REQ
 
- TCC_PERF_SEL_CLIENT84_REQ
 
- TCC_PERF_SEL_CLIENT85_REQ
 
- TCC_PERF_SEL_CLIENT86_REQ
 
- TCC_PERF_SEL_CLIENT87_REQ
 
- TCC_PERF_SEL_CLIENT88_REQ
 
- TCC_PERF_SEL_CLIENT89_REQ
 
- TCC_PERF_SEL_CLIENT8_REQ
 
- TCC_PERF_SEL_CLIENT90_REQ
 
- TCC_PERF_SEL_CLIENT91_REQ
 
- TCC_PERF_SEL_CLIENT92_REQ
 
- TCC_PERF_SEL_CLIENT93_REQ
 
- TCC_PERF_SEL_CLIENT94_REQ
 
- TCC_PERF_SEL_CLIENT95_REQ
 
- TCC_PERF_SEL_CLIENT96_REQ
 
- TCC_PERF_SEL_CLIENT97_REQ
 
- TCC_PERF_SEL_CLIENT98_REQ
 
- TCC_PERF_SEL_CLIENT99_REQ
 
- TCC_PERF_SEL_CLIENT9_REQ
 
- TCC_PERF_SEL_COMPRESSED_0_REQ
 
- TCC_PERF_SEL_COMPRESSED_REQ
 
- TCC_PERF_SEL_CYCLE
 
- TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT
 
- TCC_PERF_SEL_EA_ATOMIC
 
- TCC_PERF_SEL_EA_ATOMIC_LEVEL
 
- TCC_PERF_SEL_EA_RDREQ
 
- TCC_PERF_SEL_EA_RDREQ_32B
 
- TCC_PERF_SEL_EA_RDREQ_CREDIT_STALL
 
- TCC_PERF_SEL_EA_RDREQ_LEVEL
 
- TCC_PERF_SEL_EA_RD_COMPRESSED_32B
 
- TCC_PERF_SEL_EA_RD_MDC_32B
 
- TCC_PERF_SEL_EA_RD_UNCACHED_32B
 
- TCC_PERF_SEL_EA_WRREQ
 
- TCC_PERF_SEL_EA_WRREQ_64B
 
- TCC_PERF_SEL_EA_WRREQ_CREDIT_STALL
 
- TCC_PERF_SEL_EA_WRREQ_LEVEL
 
- TCC_PERF_SEL_EA_WRREQ_PROBE_COMMAND
 
- TCC_PERF_SEL_EA_WRREQ_STALL
 
- TCC_PERF_SEL_EA_WR_UNCACHED_32B
 
- TCC_PERF_SEL_EXE_REQ
 
- TCC_PERF_SEL_FULLY_WRITTEN_HIT
 
- TCC_PERF_SEL_HIT
 
- TCC_PERF_SEL_HOLE_FIFO_FULL
 
- TCC_PERF_SEL_HOLE_LEVEL
 
- TCC_PERF_SEL_IB_MDC_STALL
 
- TCC_PERF_SEL_IB_REQ
 
- TCC_PERF_SEL_IB_STALL
 
- TCC_PERF_SEL_IB_TAG_STALL
 
- TCC_PERF_SEL_LATENCY_FIFO_FULL
 
- TCC_PERF_SEL_MC_ATOMIC
 
- TCC_PERF_SEL_MC_ATOMIC_LEVEL
 
- TCC_PERF_SEL_MC_RDREQ
 
- TCC_PERF_SEL_MC_RDREQ_COMPRESSED
 
- TCC_PERF_SEL_MC_RDREQ_CREDIT_STALL
 
- TCC_PERF_SEL_MC_RDREQ_LEVEL
 
- TCC_PERF_SEL_MC_RDREQ_MC_HALT_STALL
 
- TCC_PERF_SEL_MC_RDREQ_MDC
 
- TCC_PERF_SEL_MC_RDREQ_UNCACHED
 
- TCC_PERF_SEL_MC_RDRET_NACK
 
- TCC_PERF_SEL_MC_WRREQ
 
- TCC_PERF_SEL_MC_WRREQ_CREDIT_STALL
 
- TCC_PERF_SEL_MC_WRREQ_LEVEL
 
- TCC_PERF_SEL_MC_WRREQ_MC_HALT_STALL
 
- TCC_PERF_SEL_MC_WRREQ_STALL
 
- TCC_PERF_SEL_MC_WRREQ_UNCACHED
 
- TCC_PERF_SEL_MC_WRRET_NACK
 
- TCC_PERF_SEL_MDC_LEVEL
 
- TCC_PERF_SEL_MDC_REQ
 
- TCC_PERF_SEL_MDC_SECTOR_HIT
 
- TCC_PERF_SEL_MDC_SECTOR_MISS
 
- TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL
 
- TCC_PERF_SEL_MDC_TAG_HIT
 
- TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL
 
- TCC_PERF_SEL_MDC_TAG_STALL
 
- TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL
 
- TCC_PERF_SEL_METADATA_REQ
 
- TCC_PERF_SEL_MISS
 
- TCC_PERF_SEL_NC_PHYSICAL_REQ
 
- TCC_PERF_SEL_NC_VIRTUAL_REQ
 
- TCC_PERF_SEL_NONE
 
- TCC_PERF_SEL_NORMAL_EVICT
 
- TCC_PERF_SEL_NORMAL_WRITEBACK
 
- TCC_PERF_SEL_PROBE
 
- TCC_PERF_SEL_PROBE_ALL
 
- TCC_PERF_SEL_PROBE_EVICT
 
- TCC_PERF_SEL_PROBE_FILTER_DISABLED
 
- TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION
 
- TCC_PERF_SEL_READ
 
- TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE
 
- TCC_PERF_SEL_READ_RETURN_TIMEOUT
 
- TCC_PERF_SEL_REQ
 
- TCC_PERF_SEL_RETURN_ACK
 
- TCC_PERF_SEL_RETURN_ACK_HOLE
 
- TCC_PERF_SEL_RETURN_DATA
 
- TCC_PERF_SEL_RETURN_HOLE
 
- TCC_PERF_SEL_SECTOR_HIT
 
- TCC_PERF_SEL_SRC_FIFO_FULL
 
- TCC_PERF_SEL_STREAMING_REQ
 
- TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL
 
- TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL
 
- TCC_PERF_SEL_TAG_PROBE_FILTER_STALL
 
- TCC_PERF_SEL_TAG_PROBE_STALL
 
- TCC_PERF_SEL_TAG_STALL
 
- TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL
 
- TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL
 
- TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL
 
- TCC_PERF_SEL_TCA_LEVEL
 
- TCC_PERF_SEL_TC_OP_INVL1L2_VOL_CYCLE
 
- TCC_PERF_SEL_TC_OP_INVL1L2_VOL_EVICT
 
- TCC_PERF_SEL_TC_OP_INVL1L2_VOL_FINISH
 
- TCC_PERF_SEL_TC_OP_INVL1L2_VOL_START
 
- TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE
 
- TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT
 
- TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH
 
- TCC_PERF_SEL_TC_OP_INVL2_NC_START
 
- TCC_PERF_SEL_TC_OP_INVL2_VOL_CYCLE
 
- TCC_PERF_SEL_TC_OP_INVL2_VOL_EVICT
 
- TCC_PERF_SEL_TC_OP_INVL2_VOL_FINISH
 
- TCC_PERF_SEL_TC_OP_INVL2_VOL_START
 
- TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE
 
- TCC_PERF_SEL_TC_OP_WBINVL2_EVICT
 
- TCC_PERF_SEL_TC_OP_WBINVL2_FINISH
 
- TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE
 
- TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT
 
- TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH
 
- TCC_PERF_SEL_TC_OP_WBINVL2_NC_START
 
- TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK
 
- TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE
 
- TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT
 
- TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH
 
- TCC_PERF_SEL_TC_OP_WBINVL2_SD_START
 
- TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK
 
- TCC_PERF_SEL_TC_OP_WBINVL2_START
 
- TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK
 
- TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE
 
- TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT
 
- TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH
 
- TCC_PERF_SEL_TC_OP_WBL2_NC_START
 
- TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK
 
- TCC_PERF_SEL_TC_OP_WBL2_VOL_CYCLE
 
- TCC_PERF_SEL_TC_OP_WBL2_VOL_EVICT
 
- TCC_PERF_SEL_TC_OP_WBL2_VOL_FINISH
 
- TCC_PERF_SEL_TC_OP_WBL2_VOL_START
 
- TCC_PERF_SEL_TC_OP_WBL2_VOL_WRITEBACK
 
- TCC_PERF_SEL_TC_OP_WBL2_WC_CYCLE
 
- TCC_PERF_SEL_TC_OP_WBL2_WC_EVICT
 
- TCC_PERF_SEL_TC_OP_WBL2_WC_FINISH
 
- TCC_PERF_SEL_TC_OP_WBL2_WC_START
 
- TCC_PERF_SEL_TC_OP_WBL2_WC_WRITEBACK
 
- TCC_PERF_SEL_TOO_MANY_EA_WRREQS_STALL
 
- TCC_PERF_SEL_TOO_MANY_MC_WRREQS_STALL
 
- TCC_PERF_SEL_UC_PHYSICAL_REQ
 
- TCC_PERF_SEL_UC_VIRTUAL_REQ
 
- TCC_PERF_SEL_VOL_MC_RDREQ
 
- TCC_PERF_SEL_VOL_MC_WRREQ
 
- TCC_PERF_SEL_VOL_REQ
 
- TCC_PERF_SEL_WBINVL2
 
- TCC_PERF_SEL_WBINVL2_CYCLE
 
- TCC_PERF_SEL_WRITE
 
- TCC_PERF_SEL_WRITEBACK
 
- TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT
 
- TCC_REDUNDANCY__MC_SEL0_MASK
 
- TCC_REDUNDANCY__MC_SEL0__SHIFT
 
- TCC_REDUNDANCY__MC_SEL1_MASK
 
- TCC_REDUNDANCY__MC_SEL1__SHIFT
 
- TCC_SOFT_RESET__HALT_FOR_RESET_MASK
 
- TCC_SOFT_RESET__HALT_FOR_RESET__SHIFT
 
- TCC_VLAN_INSERT
 
- TCC_VLAN_REPLACE
 
- TCC_WBINVL2__DONE_MASK
 
- TCC_WBINVL2__DONE__SHIFT
 
- TCDA
 
- TCDPLL
 
- TCDR
 
- TCEIE
 
- TCES_PER_PAGE
 
- TCE_ALLIO
 
- TCE_ENTRY_SIZE
 
- TCE_HUBID_SHIFT
 
- TCE_PAGE_SIZE
 
- TCE_PCI
 
- TCE_PCI_READ
 
- TCE_PCI_WRITE
 
- TCE_READ_SHIFT
 
- TCE_RPN_MASK
 
- TCE_RPN_SHIFT
 
- TCE_RSVD_SHIFT
 
- TCE_SHIFT
 
- TCE_TABLE_SIZE_128K
 
- TCE_TABLE_SIZE_1M
 
- TCE_TABLE_SIZE_256K
 
- TCE_TABLE_SIZE_2M
 
- TCE_TABLE_SIZE_4M
 
- TCE_TABLE_SIZE_512K
 
- TCE_TABLE_SIZE_64K
 
- TCE_TABLE_SIZE_8M
 
- TCE_TABLE_SIZE_UNSPECIFIED
 
- TCE_UNUSED_SHIFT
 
- TCE_VALID
 
- TCE_VB
 
- TCE_VB_WRITE
 
- TCE_WRITE_SHIFT
 
- TCFC_REG_ACTIVITY_COUNTER
 
- TCFC_REG_DBG_DWORD_ENABLE
 
- TCFC_REG_DBG_FORCE_FRAME
 
- TCFC_REG_DBG_FORCE_VALID
 
- TCFC_REG_DBG_SELECT
 
- TCFC_REG_DBG_SHIFT
 
- TCFC_REG_STRONG_ENABLE_PF
 
- TCFC_REG_STRONG_ENABLE_VF
 
- TCFC_REG_WEAK_ENABLE_VF
 
- TCFG0_PRESCALER1_SHIFT
 
- TCFG0_PRESCALER_MASK
 
- TCFG1_MUX_MASK
 
- TCFG1_SHIFT
 
- TCFLSH
 
- TCFV
 
- TCF_ABORT_TASK_SET
 
- TCF_BUSY
 
- TCF_CBQ_LSS_AVPKT
 
- TCF_CBQ_LSS_BOUNDED
 
- TCF_CBQ_LSS_EWMA
 
- TCF_CBQ_LSS_FLAGS
 
- TCF_CBQ_LSS_ISOLATED
 
- TCF_CBQ_LSS_MAXIDLE
 
- TCF_CBQ_LSS_MINIDLE
 
- TCF_CBQ_LSS_OFFTIME
 
- TCF_CLEAR_ACA
 
- TCF_CLEAR_TASK_SET
 
- TCF_DISCONNECT
 
- TCF_DRV_255_63
 
- TCF_DRV_BUSY
 
- TCF_DRV_EN_TAG
 
- TCF_EM_ALIGN_U16
 
- TCF_EM_ALIGN_U32
 
- TCF_EM_ALIGN_U8
 
- TCF_EM_CANID
 
- TCF_EM_CMP
 
- TCF_EM_CMP_TRANS
 
- TCF_EM_CONTAINER
 
- TCF_EM_INVERT
 
- TCF_EM_IPSET
 
- TCF_EM_IPT
 
- TCF_EM_MAX
 
- TCF_EM_META
 
- TCF_EM_NBYTE
 
- TCF_EM_OPND_EQ
 
- TCF_EM_OPND_GT
 
- TCF_EM_OPND_LT
 
- TCF_EM_PROG_TC
 
- TCF_EM_REL_AND
 
- TCF_EM_REL_END
 
- TCF_EM_REL_MASK
 
- TCF_EM_REL_OR
 
- TCF_EM_REL_VALID
 
- TCF_EM_SIMPLE
 
- TCF_EM_TEXT
 
- TCF_EM_U32
 
- TCF_EM_VLAN
 
- TCF_EN_255
 
- TCF_EN_DISC
 
- TCF_EN_START
 
- TCF_EN_TAG
 
- TCF_LAYER_LINK
 
- TCF_LAYER_MAX
 
- TCF_LAYER_NETWORK
 
- TCF_LAYER_TRANSPORT
 
- TCF_LUN_RESET
 
- TCF_META_ID
 
- TCF_META_ID_DATALEN
 
- TCF_META_ID_DEV
 
- TCF_META_ID_LOADAVG_0
 
- TCF_META_ID_LOADAVG_1
 
- TCF_META_ID_LOADAVG_2
 
- TCF_META_ID_MACLEN
 
- TCF_META_ID_MASK
 
- TCF_META_ID_MAX
 
- TCF_META_ID_NFMARK
 
- TCF_META_ID_PKTLEN
 
- TCF_META_ID_PKTTYPE
 
- TCF_META_ID_PRIORITY
 
- TCF_META_ID_PROTOCOL
 
- TCF_META_ID_RANDOM
 
- TCF_META_ID_RTCLASSID
 
- TCF_META_ID_RTIIF
 
- TCF_META_ID_RXHASH
 
- TCF_META_ID_SK_ACK_BACKLOG
 
- TCF_META_ID_SK_ALLOCS
 
- TCF_META_ID_SK_BOUND_IF
 
- TCF_META_ID_SK_ERR_QLEN
 
- TCF_META_ID_SK_FAMILY
 
- TCF_META_ID_SK_FORWARD_ALLOCS
 
- TCF_META_ID_SK_HASH
 
- TCF_META_ID_SK_LINGERTIME
 
- TCF_META_ID_SK_MAX_ACK_BACKLOG
 
- TCF_META_ID_SK_OMEM_ALLOC
 
- TCF_META_ID_SK_PRIO
 
- TCF_META_ID_SK_PROTO
 
- TCF_META_ID_SK_RCVBUF
 
- TCF_META_ID_SK_RCVLOWAT
 
- TCF_META_ID_SK_RCVTIMEO
 
- TCF_META_ID_SK_RCV_QLEN
 
- TCF_META_ID_SK_REFCNT
 
- TCF_META_ID_SK_REUSE
 
- TCF_META_ID_SK_RMEM_ALLOC
 
- TCF_META_ID_SK_SENDMSG_OFF
 
- TCF_META_ID_SK_SHUTDOWN
 
- TCF_META_ID_SK_SNDBUF
 
- TCF_META_ID_SK_SNDTIMEO
 
- TCF_META_ID_SK_SND_QLEN
 
- TCF_META_ID_SK_STATE
 
- TCF_META_ID_SK_TYPE
 
- TCF_META_ID_SK_WMEM_ALLOC
 
- TCF_META_ID_SK_WMEM_QUEUED
 
- TCF_META_ID_SK_WRITE_PENDING
 
- TCF_META_ID_TCINDEX
 
- TCF_META_ID_VALUE
 
- TCF_META_ID_VLAN_TAG
 
- TCF_META_TYPE
 
- TCF_META_TYPE_INT
 
- TCF_META_TYPE_MASK
 
- TCF_META_TYPE_MAX
 
- TCF_META_TYPE_VAR
 
- TCF_NOTMCMD_TO_TARGET
 
- TCF_NO_SYNC_NEGO
 
- TCF_NO_WDTR
 
- TCF_PROTO_OPS_DOIT_UNLOCKED
 
- TCF_SCSI_RATE
 
- TCF_SPIN_UP
 
- TCF_SYNC_DONE
 
- TCF_TARGET_RESET
 
- TCF_WDTR_DONE
 
- TCGETA
 
- TCGETS
 
- TCGETS2
 
- TCGETX
 
- TCG_EVENT_NAME_LEN_MAX
 
- TCG_SECP_00
 
- TCG_SECP_01
 
- TCH
 
- TCHALT_H
 
- TCHECK_TXSTATUS
 
- TCHG_MAX_EN
 
- TCIC_ADDR
 
- TCIC_ADDR_INDREG
 
- TCIC_ADDR_IO
 
- TCIC_ADDR_MASK
 
- TCIC_ADDR_REG
 
- TCIC_ADDR_SS_MASK
 
- TCIC_ADDR_SS_SHFT
 
- TCIC_ADR2_INDREG
 
- TCIC_ADR2_REG
 
- TCIC_AUX
 
- TCIC_AUX_EXTERN
 
- TCIC_AUX_ILOCK
 
- TCIC_AUX_PCTL
 
- TCIC_AUX_PDATA
 
- TCIC_AUX_SYSCFG
 
- TCIC_AUX_TCTL
 
- TCIC_AUX_TEST
 
- TCIC_AUX_WCTL
 
- TCIC_BASE
 
- TCIC_DATA
 
- TCIC_EDC
 
- TCIC_IBASE_X
 
- TCIC_ICSR
 
- TCIC_ICSR_CDCHG
 
- TCIC_ICSR_CLEAR
 
- TCIC_ICSR_ERR
 
- TCIC_ICSR_ILOCK
 
- TCIC_ICSR_IOCHK
 
- TCIC_ICSR_JAM
 
- TCIC_ICSR_PROGTIME
 
- TCIC_ICSR_SET
 
- TCIC_ICSR_STOPCPU
 
- TCIC_ICTL_1K
 
- TCIC_ICTL_ACC
 
- TCIC_ICTL_B16
 
- TCIC_ICTL_B8
 
- TCIC_ICTL_BW_16
 
- TCIC_ICTL_BW_8
 
- TCIC_ICTL_BW_ATA
 
- TCIC_ICTL_BW_DYN
 
- TCIC_ICTL_BW_MASK
 
- TCIC_ICTL_ENA
 
- TCIC_ICTL_PASS16
 
- TCIC_ICTL_QUIET
 
- TCIC_ICTL_SS_MASK
 
- TCIC_ICTL_SS_SHFT
 
- TCIC_ICTL_TINY
 
- TCIC_ICTL_WSCNT_MASK
 
- TCIC_ICTL_X
 
- TCIC_ID_DB86072
 
- TCIC_ID_DB86082
 
- TCIC_ID_DB86082A
 
- TCIC_ID_DB86082B
 
- TCIC_ID_DB86084
 
- TCIC_ID_DB86084A
 
- TCIC_ID_DB86184
 
- TCIC_IENA
 
- TCIC_IENA_CDCHG
 
- TCIC_IENA_CFG_HIGH
 
- TCIC_IENA_CFG_LOW
 
- TCIC_IENA_CFG_MASK
 
- TCIC_IENA_CFG_OD
 
- TCIC_IENA_CFG_OFF
 
- TCIC_IENA_ERR
 
- TCIC_IENA_ILOCK
 
- TCIC_IENA_PROGTIME
 
- TCIC_ILOCKTEST_ID_MASK
 
- TCIC_ILOCKTEST_ID_SH
 
- TCIC_ILOCKTEST_MCIC_1
 
- TCIC_ILOCK_CRESENA
 
- TCIC_ILOCK_CRESET
 
- TCIC_ILOCK_CWAIT
 
- TCIC_ILOCK_CWAITSNS
 
- TCIC_ILOCK_HOLD_CCLK
 
- TCIC_ILOCK_HOLD_MASK
 
- TCIC_ILOCK_OUT
 
- TCIC_ILOCK_SENSE
 
- TCIC_IRQ
 
- TCIC_IWIN
 
- TCIC_MBASE_4K_BIT
 
- TCIC_MBASE_HA_MASK
 
- TCIC_MBASE_HA_SHFT
 
- TCIC_MBASE_X
 
- TCIC_MCTL_ACC
 
- TCIC_MCTL_B8
 
- TCIC_MCTL_EDC
 
- TCIC_MCTL_ENA
 
- TCIC_MCTL_KE
 
- TCIC_MCTL_QUIET
 
- TCIC_MCTL_SS_MASK
 
- TCIC_MCTL_SS_SHFT
 
- TCIC_MCTL_WCLK
 
- TCIC_MCTL_WCLK_BCLK
 
- TCIC_MCTL_WCLK_CCLK
 
- TCIC_MCTL_WP
 
- TCIC_MCTL_WSCNT_MASK
 
- TCIC_MCTL_X
 
- TCIC_MMAP_CA_MASK
 
- TCIC_MMAP_CA_SHFT
 
- TCIC_MMAP_REG
 
- TCIC_MMAP_X
 
- TCIC_MODE
 
- TCIC_MODE_AUXSEL_MASK
 
- TCIC_MODE_NORMAL
 
- TCIC_MODE_PGMCE
 
- TCIC_MODE_PGMDBW
 
- TCIC_MODE_PGMMASK
 
- TCIC_MODE_PGMRD
 
- TCIC_MODE_PGMWORD
 
- TCIC_MODE_PGMWR
 
- TCIC_MWIN
 
- TCIC_PWR
 
- TCIC_PWR_CLIMENA
 
- TCIC_PWR_CLIMSTAT
 
- TCIC_PWR_VCC
 
- TCIC_PWR_VCC_MASK
 
- TCIC_PWR_VPP
 
- TCIC_PWR_VPP_MASK
 
- TCIC_SCF1
 
- TCIC_SCF1_ATA
 
- TCIC_SCF1_DELWR
 
- TCIC_SCF1_DMA_MASK
 
- TCIC_SCF1_DMA_OFF
 
- TCIC_SCF1_DMA_SHIFT
 
- TCIC_SCF1_DREQ2
 
- TCIC_SCF1_FINPACK
 
- TCIC_SCF1_HD7IDE
 
- TCIC_SCF1_IOSTS
 
- TCIC_SCF1_IRDY
 
- TCIC_SCF1_IRQOC
 
- TCIC_SCF1_IRQ_MASK
 
- TCIC_SCF1_IRQ_OFF
 
- TCIC_SCF1_PCVT
 
- TCIC_SCF1_SPKR
 
- TCIC_SCF2
 
- TCIC_SCF2_IDBR
 
- TCIC_SCF2_MALL
 
- TCIC_SCF2_MCD
 
- TCIC_SCF2_MDBR
 
- TCIC_SCF2_MLBAT1
 
- TCIC_SCF2_MLBAT2
 
- TCIC_SCF2_MRDY
 
- TCIC_SCF2_MWP
 
- TCIC_SCF2_RI
 
- TCIC_SCTRL
 
- TCIC_SCTRL_EDCSUM
 
- TCIC_SCTRL_ENA
 
- TCIC_SCTRL_INCMODE
 
- TCIC_SCTRL_INCMODE_AUTO
 
- TCIC_SCTRL_INCMODE_HOLD
 
- TCIC_SCTRL_INCMODE_REG
 
- TCIC_SCTRL_INCMODE_WORD
 
- TCIC_SCTRL_RESET
 
- TCIC_SSTAT
 
- TCIC_SSTAT_10US
 
- TCIC_SSTAT_6US
 
- TCIC_SSTAT_CD
 
- TCIC_SSTAT_LBAT1
 
- TCIC_SSTAT_LBAT2
 
- TCIC_SSTAT_PROGTIME
 
- TCIC_SSTAT_RDY
 
- TCIC_SSTAT_WP
 
- TCIC_SS_MASK
 
- TCIC_SS_SHFT
 
- TCIC_SYSCFG_ACC
 
- TCIC_SYSCFG_AUTOBUSY
 
- TCIC_SYSCFG_ICSXB
 
- TCIC_SYSCFG_IO1723
 
- TCIC_SYSCFG_IRQ_MASK
 
- TCIC_SYSCFG_MCSFULL
 
- TCIC_SYSCFG_MCSXB
 
- TCIC_SYSCFG_MPSEL_MASK
 
- TCIC_SYSCFG_MPSEL_SHFT
 
- TCIC_SYSCFG_MPSENSE
 
- TCIC_SYSCFG_NOPDN
 
- TCIC_TEST_DIAG
 
- TCIC_WAIT_ASYNC
 
- TCIC_WAIT_COUNT_MASK
 
- TCIC_WAIT_SENSE
 
- TCIC_WAIT_SRC
 
- TCIC_WCTL_CE
 
- TCIC_WCTL_LCD
 
- TCIC_WCTL_LLBAT1
 
- TCIC_WCTL_LLBAT2
 
- TCIC_WCTL_LRDY
 
- TCIC_WCTL_LWP
 
- TCIC_WCTL_RD
 
- TCIC_WCTL_WR
 
- TCIFLUSH
 
- TCINTEN
 
- TCIOFF
 
- TCIOFLUSH
 
- TCION
 
- TCIP_F
 
- TCIP_S
 
- TCIP_V
 
- TCIShift
 
- TCI_CNTL_1__REQ_FIFO_DEPTH_MASK
 
- TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT
 
- TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK
 
- TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT
 
- TCI_CNTL_1__WDATA_RAM_DEPTH_MASK
 
- TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT
 
- TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK
 
- TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT
 
- TCI_CNTL_2__TCA_MAX_CREDIT_MASK
 
- TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT
 
- TCI_DLL_CNTL
 
- TCI_EDC_CNT__WRITE_RAM_SED_COUNT_MASK
 
- TCI_EDC_CNT__WRITE_RAM_SED_COUNT__SHIFT
 
- TCI_MCLK_PWRMGT_CNTL
 
- TCI_STATUS__TCI_BUSY_MASK
 
- TCI_STATUS__TCI_BUSY__SHIFT
 
- TCI_WORDS
 
- TCKON_MARK
 
- TCKPOL_MASK
 
- TCKPOL_SHIFT
 
- TCKSEL_SHIFT
 
- TCK_CTRL_RGMII_1000
 
- TCK_CTRL_RGMII_10_100
 
- TCK_MARK
 
- TCK_TAP
 
- TCLAS_NUM
 
- TCLK
 
- TCLK0_B_MARK
 
- TCLK0_C_MARK
 
- TCLK0_D_MARK
 
- TCLK0_MARK
 
- TCLK1_A_MARK
 
- TCLK1_B_MARK
 
- TCLK1_C_MARK
 
- TCLK1_MARK
 
- TCLK2_A_MARK
 
- TCLK2_B_MARK
 
- TCLK2_MARK
 
- TCLK3_MARK
 
- TCLKA_A_MARK
 
- TCLKA_C_MARK
 
- TCLKA_MARK
 
- TCLKA_PD_MARK
 
- TCLKA_PF_MARK
 
- TCLKB_A_MARK
 
- TCLKB_C_MARK
 
- TCLKB_MARK
 
- TCLKB_PD_MARK
 
- TCLKB_PF_MARK
 
- TCLKCNTHREG
 
- TCLKCNTLREG
 
- TCLKCR_OFS
 
- TCLKC_A_MARK
 
- TCLKC_C_MARK
 
- TCLKC_MARK
 
- TCLKC_PD_MARK
 
- TCLKC_PF_MARK
 
- TCLKD_A_MARK
 
- TCLKD_C_MARK
 
- TCLKD_MARK
 
- TCLKD_PD_MARK
 
- TCLKD_PF_MARK
 
- TCLKHREG
 
- TCLKLREG
 
- TCLK_HEADERCNT
 
- TCLK_MARK
 
- TCLK_MISS
 
- TCLK_PERIOD_MASK
 
- TCLK_PERIOD_SHIFT
 
- TCLK_POSTCNT
 
- TCLK_SETTLE
 
- TCLK_TERM
 
- TCLK_TRAILCNT
 
- TCLOCK_INT
 
- TCLOCK_IRQ
 
- TCLR
 
- TCL_LUN
 
- TCL_TARGET_OFFSET
 
- TCMCONFIG
 
- TCMDQ_HALT
 
- TCMDQ_INIT_ER
 
- TCMDQ_LACR
 
- TCMDQ_START
 
- TCMDQ_START_LACR
 
- TCMD_DEFERRED
 
- TCMD_ERRMASK
 
- TCMD_HEARTBEAT
 
- TCMD_LATECOLL
 
- TCMD_LOSTCTS
 
- TCMD_MAXCOLL
 
- TCMD_MAXCOLLMASK
 
- TCMD_NOCARRIER
 
- TCMD_UNDERRUN
 
- TCMIF_ASM_BASE
 
- TCMIF_BASE
 
- TCMISS
 
- TCMP
 
- TCMP1
 
- TCMP1_ADDR
 
- TCMP2
 
- TCMP2_ADDR
 
- TCMP_ADDR
 
- TCMTR_FORMAT_MASK
 
- TCMU_ATTR_CMD_STATUS
 
- TCMU_ATTR_DEVICE
 
- TCMU_ATTR_DEVICE_ID
 
- TCMU_ATTR_DEV_CFG
 
- TCMU_ATTR_DEV_SIZE
 
- TCMU_ATTR_MAX
 
- TCMU_ATTR_MINOR
 
- TCMU_ATTR_PAD
 
- TCMU_ATTR_SUPP_KERN_CMD_REPLY
 
- TCMU_ATTR_UNSPEC
 
- TCMU_ATTR_WRITECACHE
 
- TCMU_BLOCKS_TO_MBS
 
- TCMU_CMD_ADDED_DEVICE
 
- TCMU_CMD_ADDED_DEVICE_DONE
 
- TCMU_CMD_BIT_EXPIRED
 
- TCMU_CMD_BIT_INFLIGHT
 
- TCMU_CMD_MAX
 
- TCMU_CMD_RECONFIG_DEVICE
 
- TCMU_CMD_RECONFIG_DEVICE_DONE
 
- TCMU_CMD_REMOVED_DEVICE
 
- TCMU_CMD_REMOVED_DEVICE_DONE
 
- TCMU_CMD_SET_FEATURES
 
- TCMU_CMD_UNSPEC
 
- TCMU_CONFIG_LEN
 
- TCMU_DEV
 
- TCMU_DEV_BIT_BLOCKED
 
- TCMU_DEV_BIT_BROKEN
 
- TCMU_DEV_BIT_OPEN
 
- TCMU_GLOBAL_MAX_BLOCKS_DEF
 
- TCMU_MAILBOX_FLAG_CAP_OOOC
 
- TCMU_MAILBOX_FLAG_CAP_READ_LEN
 
- TCMU_MAILBOX_VERSION
 
- TCMU_MBS_TO_BLOCKS
 
- TCMU_MCGRP_CONFIG
 
- TCMU_OP_ALIGN_SIZE
 
- TCMU_OP_CMD
 
- TCMU_OP_MASK
 
- TCMU_OP_PAD
 
- TCMU_SENSE_BUFFERSIZE
 
- TCMU_TIME_OUT
 
- TCMU_UFLAG_READ_LEN
 
- TCMU_UFLAG_UNKNOWN_OP
 
- TCMU_VERSION
 
- TCM_ACA_TAG
 
- TCM_ADDRESS_OUT_OF_RANGE
 
- TCM_ALIGN
 
- TCM_CHECK_CONDITION_ABORT_CMD
 
- TCM_CHECK_CONDITION_NOT_READY
 
- TCM_CHECK_CONDITION_UNIT_ATTENTION
 
- TCM_COPY_TARGET_DEVICE_NOT_REACHABLE
 
- TCM_DATA
 
- TCM_FC_DEFAULT_TAGS
 
- TCM_F_MORE
 
- TCM_F_REQUEST
 
- TCM_H
 
- TCM_HEAD_TAG
 
- TCM_IFINDEX_MAGIC_BLOCK
 
- TCM_INCORRECT_AMOUNT_OF_DATA
 
- TCM_INSUFFICIENT_REGISTRATION_RESOURCES
 
- TCM_INVALID_CDB_FIELD
 
- TCM_INVALID_PARAMETER_LIST
 
- TCM_LENGTH
 
- TCM_LOGICAL_BLOCK_APP_TAG_CHECK_FAILED
 
- TCM_LOGICAL_BLOCK_GUARD_CHECK_FAILED
 
- TCM_LOGICAL_BLOCK_REF_TAG_CHECK_FAILED
 
- TCM_LOGICAL_UNIT_COMMUNICATION_FAILURE
 
- TCM_LOOP_VERSION
 
- TCM_LUN_BUSY
 
- TCM_MAX_COMMAND_SIZE
 
- TCM_MEM_SIZE
 
- TCM_MISCOMPARE_VERIFY
 
- TCM_NON_EXISTENT_LUN
 
- TCM_NO_SENSE
 
- TCM_ORDERED_TAG
 
- TCM_OUT_OF_RESOURCES
 
- TCM_PARAMETER_LIST_LENGTH_ERROR
 
- TCM_QLA2XXX_DEFAULT_TAGS
 
- TCM_QLA2XXX_NAMELEN
 
- TCM_REGION_READ_INSTR
 
- TCM_REGION_READ_MASK
 
- TCM_REG_AGG_CON_CTX
 
- TCM_REG_AGG_TASK_CTX
 
- TCM_REG_CAM_OCCUP
 
- TCM_REG_CDU_AG_RD_IFEN
 
- TCM_REG_CDU_AG_WR_IFEN
 
- TCM_REG_CDU_SM_RD_IFEN
 
- TCM_REG_CDU_SM_WR_IFEN
 
- TCM_REG_CFC_INIT_CRD
 
- TCM_REG_CP_WEIGHT
 
- TCM_REG_CSEM_IFEN
 
- TCM_REG_CSEM_LENGTH_MIS
 
- TCM_REG_CSEM_WEIGHT
 
- TCM_REG_CTX_RBC_ACCS
 
- TCM_REG_DBG_DWORD_ENABLE
 
- TCM_REG_DBG_FORCE_FRAME
 
- TCM_REG_DBG_FORCE_VALID
 
- TCM_REG_DBG_SELECT
 
- TCM_REG_DBG_SHIFT
 
- TCM_REG_ERR_EVNT_ID
 
- TCM_REG_ERR_TCM_HDR
 
- TCM_REG_EXPR_EVNT_ID
 
- TCM_REG_FIC0_INIT_CRD
 
- TCM_REG_FIC1_INIT_CRD
 
- TCM_REG_GR_ARB_TYPE
 
- TCM_REG_GR_LD0_PR
 
- TCM_REG_GR_LD1_PR
 
- TCM_REG_INIT
 
- TCM_REG_N_SM_CTX_LD_0
 
- TCM_REG_N_SM_CTX_LD_1
 
- TCM_REG_N_SM_CTX_LD_2
 
- TCM_REG_N_SM_CTX_LD_3
 
- TCM_REG_N_SM_CTX_LD_4
 
- TCM_REG_N_SM_CTX_LD_5
 
- TCM_REG_PBF_IFEN
 
- TCM_REG_PBF_LENGTH_MIS
 
- TCM_REG_PBF_WEIGHT
 
- TCM_REG_PHYS_QNUM0_0
 
- TCM_REG_PHYS_QNUM0_1
 
- TCM_REG_PHYS_QNUM1_0
 
- TCM_REG_PHYS_QNUM1_1
 
- TCM_REG_PHYS_QNUM2_0
 
- TCM_REG_PHYS_QNUM2_1
 
- TCM_REG_PHYS_QNUM3_0
 
- TCM_REG_PHYS_QNUM3_1
 
- TCM_REG_PRS_IFEN
 
- TCM_REG_PRS_LENGTH_MIS
 
- TCM_REG_PRS_WEIGHT
 
- TCM_REG_SM_CON_CTX
 
- TCM_REG_SM_TASK_CTX
 
- TCM_REG_STOP_EVNT_ID
 
- TCM_REG_STORM_LENGTH_MIS
 
- TCM_REG_STORM_TCM_IFEN
 
- TCM_REG_STORM_WEIGHT
 
- TCM_REG_TCM_CFC_IFEN
 
- TCM_REG_TCM_INT_MASK
 
- TCM_REG_TCM_INT_STS
 
- TCM_REG_TCM_PRTY_MASK
 
- TCM_REG_TCM_PRTY_STS
 
- TCM_REG_TCM_PRTY_STS_CLR
 
- TCM_REG_TCM_REG0_SZ
 
- TCM_REG_TCM_STORM0_IFEN
 
- TCM_REG_TCM_STORM1_IFEN
 
- TCM_REG_TCM_TQM_IFEN
 
- TCM_REG_TCM_TQM_USE_Q
 
- TCM_REG_TM_TCM_HDR
 
- TCM_REG_TM_TCM_IFEN
 
- TCM_REG_TM_WEIGHT
 
- TCM_REG_TQM_INIT_CRD
 
- TCM_REG_TQM_P_WEIGHT
 
- TCM_REG_TQM_S_WEIGHT
 
- TCM_REG_TQM_TCM_HDR_P
 
- TCM_REG_TQM_TCM_HDR_S
 
- TCM_REG_TQM_TCM_IFEN
 
- TCM_REG_TSDM_IFEN
 
- TCM_REG_TSDM_LENGTH_MIS
 
- TCM_REG_TSDM_WEIGHT
 
- TCM_REG_USEM_IFEN
 
- TCM_REG_USEM_LENGTH_MIS
 
- TCM_REG_USEM_WEIGHT
 
- TCM_REG_XX_DESCR_TABLE
 
- TCM_REG_XX_DESCR_TABLE_SIZE
 
- TCM_REG_XX_FREE
 
- TCM_REG_XX_INIT_CRD
 
- TCM_REG_XX_MAX_LL_SZ
 
- TCM_REG_XX_MSG_NUM
 
- TCM_REG_XX_OVFL_EVNT_ID
 
- TCM_REG_XX_TABLE
 
- TCM_RESERVATION_CONFLICT
 
- TCM_SECTOR_COUNT_TOO_MANY
 
- TCM_SERVICE_CRC_ERROR
 
- TCM_SET
 
- TCM_SIMPLE_TAG
 
- TCM_SNACK_REJECTED
 
- TCM_SPACE
 
- TCM_TOO_MANY_SEGMENT_DESCS
 
- TCM_TOO_MANY_TARGET_DESCS
 
- TCM_TRANSPORT_OFFLINE
 
- TCM_TRANSPORT_ONLINE
 
- TCM_UNEXPECTED_UNSOLICITED_DATA
 
- TCM_UNKNOWN_MODE_PAGE
 
- TCM_UNSUPPORTED_SCSI_OPCODE
 
- TCM_UNSUPPORTED_SEGMENT_DESC_TYPE_CODE
 
- TCM_UNSUPPORTED_TARGET_DESC_TYPE_CODE
 
- TCM_WRITE_PROTECTED
 
- TCN
 
- TCN1
 
- TCN1_ADDR
 
- TCN2
 
- TCN2_ADDR
 
- TCNT
 
- TCNTH
 
- TCNTINFO_INIT
 
- TCNTL
 
- TCN_ADDR
 
- TCO1_CNT
 
- TCO1_STS
 
- TCO2_CNT
 
- TCO2_STS
 
- TCOBASE
 
- TCOCTL
 
- TCOCTL_EN
 
- TCODE_CYCLE_START
 
- TCODE_HAS_REQUEST_DATA
 
- TCODE_HAS_RESPONSE_DATA
 
- TCODE_IS_BLOCK_PACKET
 
- TCODE_IS_LINK_INTERNAL
 
- TCODE_IS_READ_REQUEST
 
- TCODE_IS_REQUEST
 
- TCODE_IS_RESPONSE
 
- TCODE_LINK_INTERNAL
 
- TCODE_LOCK_BOUNDED_ADD
 
- TCODE_LOCK_COMPARE_SWAP
 
- TCODE_LOCK_FETCH_ADD
 
- TCODE_LOCK_LITTLE_ADD
 
- TCODE_LOCK_MASK_SWAP
 
- TCODE_LOCK_REQUEST
 
- TCODE_LOCK_RESPONSE
 
- TCODE_LOCK_VENDOR_DEPENDENT
 
- TCODE_LOCK_WRAP_ADD
 
- TCODE_PHY_PACKET
 
- TCODE_READ_BLOCK_REQUEST
 
- TCODE_READ_BLOCK_RESPONSE
 
- TCODE_READ_QUADLET_REQUEST
 
- TCODE_READ_QUADLET_RESPONSE
 
- TCODE_STREAM_DATA
 
- TCODE_WRITE_BLOCK_REQUEST
 
- TCODE_WRITE_QUADLET_REQUEST
 
- TCODE_WRITE_RESPONSE
 
- TCOFLUSH
 
- TCONR
 
- TCONRH
 
- TCONRL
 
- TCONX_REQ
 
- TCONX_RSP
 
- TCONX_RSP_EXT
 
- TCON_AUTORELOAD
 
- TCON_CH1_SCLK1_GATE_BIT
 
- TCON_CH1_SCLK1_HALF_BIT
 
- TCON_CH1_SCLK2_DIV_MASK
 
- TCON_CH1_SCLK2_DIV_SHIFT
 
- TCON_CH1_SCLK2_GATE_BIT
 
- TCON_CH1_SCLK2_MUX_MASK
 
- TCON_CH1_SCLK2_MUX_SHIFT
 
- TCON_CH1_SCLK2_PARENTS
 
- TCON_CONTROL_HI
 
- TCON_CONTROL_LO
 
- TCON_DOUBLE_CTL
 
- TCON_EXTENDED_SECINFO
 
- TCON_EXTENDED_SIGNATURES
 
- TCON_INVERT
 
- TCON_INVERT_CTL
 
- TCON_LINK_IN_TREE
 
- TCON_LINK_MASTER
 
- TCON_LINK_PENDING
 
- TCON_MANUALUPDATE
 
- TCON_MISC_SEL_ADDR
 
- TCON_PATTERN_HI
 
- TCON_PATTERN_LO
 
- TCON_START
 
- TCON_TOP_GATE_SRC_REG
 
- TCON_TOP_HDMI_SRC_MSK
 
- TCON_TOP_PORT_DE0_MSK
 
- TCON_TOP_PORT_DE1_MSK
 
- TCON_TOP_PORT_SEL_REG
 
- TCON_TOP_TCON_DSI_GATE
 
- TCON_TOP_TCON_TV0_GATE
 
- TCON_TOP_TCON_TV1_GATE
 
- TCON_TOP_TCON_TV_SETUP_REG
 
- TCOOFF
 
- TCOON
 
- TCOR
 
- TCORA
 
- TCORB
 
- TCO_BASE_OFFSET
 
- TCO_CNT
 
- TCO_CNT_TCOHALT
 
- TCO_DAT_IN
 
- TCO_DAT_OUT
 
- TCO_DEVICE_NAME
 
- TCO_DRIVER_NAME
 
- TCO_MODULE_NAME
 
- TCO_PMC_OFFSET
 
- TCO_PMC_SIZE
 
- TCO_REGS_SIZE
 
- TCO_RESOURCE_ACPI_IO
 
- TCO_RESOURCE_GCR_MEM
 
- TCO_RESOURCE_SMI_EN_IO
 
- TCO_RLD
 
- TCO_STS
 
- TCO_STS_BOOT_STS
 
- TCO_STS_RESET
 
- TCO_STS_TCO2TO_STS
 
- TCO_STS_TCO_INT_STS
 
- TCO_TMR
 
- TCO_VERSION
 
- TCOv1_TMR
 
- TCOv2_TMR
 
- TCPACTIVEOPENS
 
- TCPATTEMPTFAILS
 
- TCPCB_EVER_RETRANS
 
- TCPCB_LOST
 
- TCPCB_REPAIRED
 
- TCPCB_RETRANS
 
- TCPCB_SACKED_ACKED
 
- TCPCB_SACKED_RETRANS
 
- TCPCB_TAGBITS
 
- TCPCS
 
- TCPCURRESTAB
 
- TCPC_ALERT
 
- TCPC_ALERT_CC_STATUS
 
- TCPC_ALERT_FAULT
 
- TCPC_ALERT_MASK
 
- TCPC_ALERT_POWER_STATUS
 
- TCPC_ALERT_RX_BUF_OVF
 
- TCPC_ALERT_RX_HARD_RST
 
- TCPC_ALERT_RX_STATUS
 
- TCPC_ALERT_TX_DISCARDED
 
- TCPC_ALERT_TX_FAILED
 
- TCPC_ALERT_TX_SUCCESS
 
- TCPC_ALERT_VBUS_DISCNCT
 
- TCPC_ALERT_V_ALARM_HI
 
- TCPC_ALERT_V_ALARM_LO
 
- TCPC_BCD_DEV
 
- TCPC_CC_STATUS
 
- TCPC_CC_STATUS_CC1_MASK
 
- TCPC_CC_STATUS_CC1_SHIFT
 
- TCPC_CC_STATUS_CC2_MASK
 
- TCPC_CC_STATUS_CC2_SHIFT
 
- TCPC_CC_STATUS_TERM
 
- TCPC_CC_STATUS_TOGGLING
 
- TCPC_CMD_DISABLE_SINK_VBUS
 
- TCPC_CMD_DISABLE_SRC_VBUS
 
- TCPC_CMD_DISABLE_VBUS_DETECT
 
- TCPC_CMD_ENABLE_VBUS_DETECT
 
- TCPC_CMD_I2C_IDLE
 
- TCPC_CMD_LOOK4CONNECTION
 
- TCPC_CMD_RXONEMORE
 
- TCPC_CMD_SINK_VBUS
 
- TCPC_CMD_SRC_VBUS_DEFAULT
 
- TCPC_CMD_SRC_VBUS_HIGH
 
- TCPC_CMD_WAKE_I2C
 
- TCPC_COMMAND
 
- TCPC_CONFIG_STD_OUTPUT
 
- TCPC_DEV_CAP_1
 
- TCPC_DEV_CAP_2
 
- TCPC_FAULT_CTRL
 
- TCPC_FAULT_STATUS
 
- TCPC_FAULT_STATUS_MASK
 
- TCPC_MSG_HDR_INFO
 
- TCPC_MSG_HDR_INFO_DATA_ROLE
 
- TCPC_MSG_HDR_INFO_PWR_ROLE
 
- TCPC_MSG_HDR_INFO_REV_MASK
 
- TCPC_MSG_HDR_INFO_REV_SHIFT
 
- TCPC_MUX_DP_ENABLED
 
- TCPC_MUX_POLARITY_INVERTED
 
- TCPC_MUX_USB_ENABLED
 
- TCPC_PD_INT_REV
 
- TCPC_PD_REV
 
- TCPC_POWER_CTRL
 
- TCPC_POWER_CTRL_VCONN_ENABLE
 
- TCPC_POWER_STATUS
 
- TCPC_POWER_STATUS_MASK
 
- TCPC_POWER_STATUS_UNINIT
 
- TCPC_POWER_STATUS_VBUS_DET
 
- TCPC_POWER_STATUS_VBUS_PRES
 
- TCPC_PRODUCT_ID
 
- TCPC_ROLE_CTRL
 
- TCPC_ROLE_CTRL_CC1_MASK
 
- TCPC_ROLE_CTRL_CC1_SHIFT
 
- TCPC_ROLE_CTRL_CC2_MASK
 
- TCPC_ROLE_CTRL_CC2_SHIFT
 
- TCPC_ROLE_CTRL_CC_OPEN
 
- TCPC_ROLE_CTRL_CC_RA
 
- TCPC_ROLE_CTRL_CC_RD
 
- TCPC_ROLE_CTRL_CC_RP
 
- TCPC_ROLE_CTRL_DRP
 
- TCPC_ROLE_CTRL_RP_VAL_1_5
 
- TCPC_ROLE_CTRL_RP_VAL_3_0
 
- TCPC_ROLE_CTRL_RP_VAL_DEF
 
- TCPC_ROLE_CTRL_RP_VAL_MASK
 
- TCPC_ROLE_CTRL_RP_VAL_SHIFT
 
- TCPC_RX_BUF_FRAME_TYPE
 
- TCPC_RX_BYTE_CNT
 
- TCPC_RX_DATA
 
- TCPC_RX_DETECT
 
- TCPC_RX_DETECT_HARD_RESET
 
- TCPC_RX_DETECT_SOP
 
- TCPC_RX_HDR
 
- TCPC_STD_INPUT_CAP
 
- TCPC_STD_OUTPUT_CAP
 
- TCPC_TCPC_CTRL
 
- TCPC_TCPC_CTRL_ORIENTATION
 
- TCPC_TC_REV
 
- TCPC_TRANSMIT
 
- TCPC_TRANSMIT_RETRY_MASK
 
- TCPC_TRANSMIT_RETRY_SHIFT
 
- TCPC_TRANSMIT_TYPE_MASK
 
- TCPC_TRANSMIT_TYPE_SHIFT
 
- TCPC_TX_BIST_MODE_2
 
- TCPC_TX_BYTE_CNT
 
- TCPC_TX_CABLE_RESET
 
- TCPC_TX_DATA
 
- TCPC_TX_DISCARDED
 
- TCPC_TX_FAILED
 
- TCPC_TX_HARD_RESET
 
- TCPC_TX_HDR
 
- TCPC_TX_SOP
 
- TCPC_TX_SOP_DEBUG_PRIME
 
- TCPC_TX_SOP_DEBUG_PRIME_PRIME
 
- TCPC_TX_SOP_PRIME
 
- TCPC_TX_SOP_PRIME_PRIME
 
- TCPC_TX_SUCCESS
 
- TCPC_VBUS_SINK_DISCONNECT_THRESH
 
- TCPC_VBUS_STOP_DISCHARGE_THRESH
 
- TCPC_VBUS_VOLTAGE
 
- TCPC_VBUS_VOLTAGE_ALARM_HI_CFG
 
- TCPC_VBUS_VOLTAGE_ALARM_LO_CFG
 
- TCPC_VENDOR_ID
 
- TCPCheckSumErrors
 
- TCPChecksumEnable
 
- TCPChksumErr
 
- TCPChksumValid
 
- TCPDIAG_GETSOCK
 
- TCPDUMP_MAGIC
 
- TCPDetected
 
- TCPESTABRESETS
 
- TCPError
 
- TCPF
 
- TCPF_CA_CWR
 
- TCPF_CA_Disorder
 
- TCPF_CA_Open
 
- TCPF_CA_Recovery
 
- TCPF_CLOSE
 
- TCPF_CLOSE_WAIT
 
- TCPF_CLOSING
 
- TCPF_DELACK_TIMER_DEFERRED
 
- TCPF_ESTABLISHED
 
- TCPF_FIN_WAIT1
 
- TCPF_FIN_WAIT2
 
- TCPF_LAST_ACK
 
- TCPF_LISTEN
 
- TCPF_MTU_REDUCED_DEFERRED
 
- TCPF_NEW_SYN_RECV
 
- TCPF_SYN_RECV
 
- TCPF_SYN_SENT
 
- TCPF_TIME_WAIT
 
- TCPF_TSQ_DEFERRED
 
- TCPF_WRITE_TIMER_DEFERRED
 
- TCPFail
 
- TCPHDR_ACK
 
- TCPHDR_CWR
 
- TCPHDR_ECE
 
- TCPHDR_FIN
 
- TCPHDR_LEN
 
- TCPHDR_POS
 
- TCPHDR_PSH
 
- TCPHDR_RST
 
- TCPHDR_SYN
 
- TCPHDR_SYN_ECN
 
- TCPHDR_URG
 
- TCPHO_MAX
 
- TCPHO_SHIFT
 
- TCPINERRS
 
- TCPINSEGS
 
- TCPIP_CHKSUM_PKTINFO
 
- TCPI_OPT_ECN
 
- TCPI_OPT_ECN_SEEN
 
- TCPI_OPT_SACK
 
- TCPI_OPT_SYN_DATA
 
- TCPI_OPT_TIMESTAMPS
 
- TCPI_OPT_WSCALE
 
- TCPLS_END
 
- TCPLS_MED
 
- TCPLS_NORMAL
 
- TCPLS_START
 
- TCPM_CC_EVENT
 
- TCPM_PSY_FIXED_ONLINE
 
- TCPM_PSY_OFFLINE
 
- TCPM_PSY_PROG_ONLINE
 
- TCPM_RESET_EVENT
 
- TCPM_VBUS_EVENT
 
- TCPOLEN_EXP_FASTOPEN_BASE
 
- TCPOLEN_EXP_SMC_BASE
 
- TCPOLEN_EXP_SMC_BASE_ALIGNED
 
- TCPOLEN_FASTOPEN_BASE
 
- TCPOLEN_MD5SIG
 
- TCPOLEN_MD5SIG_ALIGNED
 
- TCPOLEN_MSS
 
- TCPOLEN_MSS_ALIGNED
 
- TCPOLEN_SACKPERM_ALIGNED
 
- TCPOLEN_SACK_BASE
 
- TCPOLEN_SACK_BASE_ALIGNED
 
- TCPOLEN_SACK_PERBLOCK
 
- TCPOLEN_SACK_PERM
 
- TCPOLEN_TIMESTAMP
 
- TCPOLEN_TSTAMP_ALIGNED
 
- TCPOLEN_WINDOW
 
- TCPOLEN_WSCALE_ALIGNED
 
- TCPON
 
- TCPOPT_DELAYED_ACK_DISABLE
 
- TCPOPT_DHCP_ENABLE
 
- TCPOPT_DNS_SERVER_IP_EN
 
- TCPOPT_EOL
 
- TCPOPT_EXP
 
- TCPOPT_FASTOPEN
 
- TCPOPT_FASTOPEN_MAGIC
 
- TCPOPT_MD5SIG
 
- TCPOPT_MSS
 
- TCPOPT_MSS_G
 
- TCPOPT_MSS_M
 
- TCPOPT_MSS_S
 
- TCPOPT_NAGLE_ALGO_DISABLE
 
- TCPOPT_NAGLE_DISABLE
 
- TCPOPT_NOP
 
- TCPOPT_SACK
 
- TCPOPT_SACK_G
 
- TCPOPT_SACK_M
 
- TCPOPT_SACK_PERM
 
- TCPOPT_SACK_S
 
- TCPOPT_SLP_DA_INFO_EN
 
- TCPOPT_SMC_MAGIC
 
- TCPOPT_SND_WSCALE_G
 
- TCPOPT_SND_WSCALE_M
 
- TCPOPT_SND_WSCALE_S
 
- TCPOPT_TIMER_SCALE
 
- TCPOPT_TIMER_SCALE1
 
- TCPOPT_TIMER_SCALE2
 
- TCPOPT_TIMER_SCALE3
 
- TCPOPT_TIMESTAMP
 
- TCPOPT_TIMESTAMP_EN
 
- TCPOPT_TIMESTAMP_ENABLE
 
- TCPOPT_TIMESTAMP_STAT
 
- TCPOPT_TSTAMP_G
 
- TCPOPT_TSTAMP_M
 
- TCPOPT_TSTAMP_S
 
- TCPOPT_WINDOW
 
- TCPOPT_WINDOW_SCALE_DISABLE
 
- TCPOPT_WSCALE_OK_G
 
- TCPOPT_WSCALE_OK_M
 
- TCPOPT_WSCALE_OK_S
 
- TCPOPT_WSF_DISABLE
 
- TCPOUTRSTS
 
- TCPOUTSEGS
 
- TCPPASSIVEOPENS
 
- TCPRETRANSSEGS
 
- TCPRTOMAX
 
- TCPRTOMIN
 
- TCPUDP_MIB_MAX
 
- TCPU_MAX
 
- TCP_ACK_FILTER_LINK_SPEED_THRESH
 
- TCP_ACK_SET
 
- TCP_ACTION_FIN
 
- TCP_ADDR_CONFIG__COLHI_WIDTH_MASK
 
- TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT
 
- TCP_ADDR_CONFIG__NUM_BANKS_MASK
 
- TCP_ADDR_CONFIG__NUM_BANKS__SHIFT
 
- TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK
 
- TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT
 
- TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK
 
- TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT
 
- TCP_ADD_STATS
 
- TCP_APP_TAB_BITS
 
- TCP_APP_TAB_MASK
 
- TCP_APP_TAB_SIZE
 
- TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK
 
- TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT
 
- TCP_ATO_MIN
 
- TCP_BASE_MSS
 
- TCP_BPF_BASE
 
- TCP_BPF_IPV4
 
- TCP_BPF_IPV6
 
- TCP_BPF_IW
 
- TCP_BPF_NUM_CFGS
 
- TCP_BPF_NUM_PROTS
 
- TCP_BPF_SNDCWND_CLAMP
 
- TCP_BPF_TX
 
- TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK
 
- TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT
 
- TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK
 
- TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT
 
- TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK
 
- TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT
 
- TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK
 
- TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT
 
- TCP_CACHE_POLICIES
 
- TCP_CACHE_POLICY_HIT_EVICT
 
- TCP_CACHE_POLICY_HIT_LRU
 
- TCP_CACHE_POLICY_MISS_EVICT
 
- TCP_CACHE_POLICY_MISS_LRU
 
- TCP_CACHE_STORE_POLICIES
 
- TCP_CACHE_STORE_POLICY_MISS_EVICT
 
- TCP_CACHE_STORE_POLICY_MISS_LRU
 
- TCP_CACHE_STORE_POLICY_WT_EVICT
 
- TCP_CACHE_STORE_POLICY_WT_LRU
 
- TCP_CA_BUF_MAX
 
- TCP_CA_CWR
 
- TCP_CA_Disorder
 
- TCP_CA_Loss
 
- TCP_CA_MAX
 
- TCP_CA_NAME_MAX
 
- TCP_CA_Open
 
- TCP_CA_Recovery
 
- TCP_CA_UNSPEC
 
- TCP_CC_INFO
 
- TCP_CFLAG_MSK
 
- TCP_CFLAG_MSK_MASK
 
- TCP_CHAN_STEER
 
- TCP_CHAN_STEER_HI
 
- TCP_CHAN_STEER_HI__CHAN8_MASK
 
- TCP_CHAN_STEER_HI__CHAN8__SHIFT
 
- TCP_CHAN_STEER_HI__CHAN9_MASK
 
- TCP_CHAN_STEER_HI__CHAN9__SHIFT
 
- TCP_CHAN_STEER_HI__CHANA_MASK
 
- TCP_CHAN_STEER_HI__CHANA__SHIFT
 
- TCP_CHAN_STEER_HI__CHANB_MASK
 
- TCP_CHAN_STEER_HI__CHANB__SHIFT
 
- TCP_CHAN_STEER_HI__CHANC_MASK
 
- TCP_CHAN_STEER_HI__CHANC__SHIFT
 
- TCP_CHAN_STEER_HI__CHAND_MASK
 
- TCP_CHAN_STEER_HI__CHAND__SHIFT
 
- TCP_CHAN_STEER_HI__CHANE_MASK
 
- TCP_CHAN_STEER_HI__CHANE__SHIFT
 
- TCP_CHAN_STEER_HI__CHANF_MASK
 
- TCP_CHAN_STEER_HI__CHANF__SHIFT
 
- TCP_CHAN_STEER_LO
 
- TCP_CHAN_STEER_LO__CHAN0_MASK
 
- TCP_CHAN_STEER_LO__CHAN0__SHIFT
 
- TCP_CHAN_STEER_LO__CHAN1_MASK
 
- TCP_CHAN_STEER_LO__CHAN1__SHIFT
 
- TCP_CHAN_STEER_LO__CHAN2_MASK
 
- TCP_CHAN_STEER_LO__CHAN2__SHIFT
 
- TCP_CHAN_STEER_LO__CHAN3_MASK
 
- TCP_CHAN_STEER_LO__CHAN3__SHIFT
 
- TCP_CHAN_STEER_LO__CHAN4_MASK
 
- TCP_CHAN_STEER_LO__CHAN4__SHIFT
 
- TCP_CHAN_STEER_LO__CHAN5_MASK
 
- TCP_CHAN_STEER_LO__CHAN5__SHIFT
 
- TCP_CHAN_STEER_LO__CHAN6_MASK
 
- TCP_CHAN_STEER_LO__CHAN6__SHIFT
 
- TCP_CHAN_STEER_LO__CHAN7_MASK
 
- TCP_CHAN_STEER_LO__CHAN7__SHIFT
 
- TCP_CHECK_SUM_OFFLOAD
 
- TCP_CHRONO_BUSY
 
- TCP_CHRONO_RWND_LIMITED
 
- TCP_CHRONO_SNDBUF_LIMITED
 
- TCP_CHRONO_UNSPEC
 
- TCP_CKSUM
 
- TCP_CLOSE
 
- TCP_CLOSE_WAIT
 
- TCP_CLOSING
 
- TCP_CM_INQ
 
- TCP_CNTL
 
- TCP_CNTL2__LS_DISABLE_CLOCKS_MASK
 
- TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT
 
- TCP_CNTL2__RETURN_ORDER_OVERRIDE_MASK
 
- TCP_CNTL2__RETURN_ORDER_OVERRIDE__SHIFT
 
- TCP_CNTL2__TAGRAM_ADDR_SWIZZLE_DISABLE_MASK
 
- TCP_CNTL2__TAGRAM_ADDR_SWIZZLE_DISABLE__SHIFT
 
- TCP_CNTL2__TCPF_FMT_MGCG_DISABLE_MASK
 
- TCP_CNTL2__TCPF_FMT_MGCG_DISABLE__SHIFT
 
- TCP_CNTL2__TCPF_LATENCY_BYPASS_DISABLE_MASK
 
- TCP_CNTL2__TCPF_LATENCY_BYPASS_DISABLE__SHIFT
 
- TCP_CNTL2__TCPI_ADRS_IMG_CALC_MGCG_DISABLE_MASK
 
- TCP_CNTL2__TCPI_ADRS_IMG_CALC_MGCG_DISABLE__SHIFT
 
- TCP_CNTL2__TCPI_INNER_BLOCK_MGCG_DISABLE_MASK
 
- TCP_CNTL2__TCPI_INNER_BLOCK_MGCG_DISABLE__SHIFT
 
- TCP_CNTL2__TCPI_WRITE_DATA_MGCG_DISABLE_MASK
 
- TCP_CNTL2__TCPI_WRITE_DATA_MGCG_DISABLE__SHIFT
 
- TCP_CNTL2__V64_COMBINE_ENABLE_MASK
 
- TCP_CNTL2__V64_COMBINE_ENABLE__SHIFT
 
- TCP_CNTL__ASTC_VE_MSB_TOLERANT_MASK
 
- TCP_CNTL__ASTC_VE_MSB_TOLERANT__SHIFT
 
- TCP_CNTL__BIG_PAGE_ADDR_COMBINE_DISABLE_MASK
 
- TCP_CNTL__BIG_PAGE_ADDR_COMBINE_DISABLE__SHIFT
 
- TCP_CNTL__DISABLE_Z_MAP_MASK
 
- TCP_CNTL__DISABLE_Z_MAP__SHIFT
 
- TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK
 
- TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT
 
- TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK
 
- TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT
 
- TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK
 
- TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT
 
- TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK
 
- TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT
 
- TCP_CNTL__FORCE_HIT_MASK
 
- TCP_CNTL__FORCE_HIT__SHIFT
 
- TCP_CNTL__FORCE_MISS_MASK
 
- TCP_CNTL__FORCE_MISS__SHIFT
 
- TCP_CNTL__INV_ALL_VMIDS_MASK
 
- TCP_CNTL__INV_ALL_VMIDS__SHIFT
 
- TCP_CNTL__L0_SIZE_MASK
 
- TCP_CNTL__L0_SIZE__SHIFT
 
- TCP_CNTL__L1_SIZE_MASK
 
- TCP_CNTL__L1_SIZE__SHIFT
 
- TCP_CNTL__LFIFO_SIZE_MASK
 
- TCP_CNTL__LFIFO_SIZE__SHIFT
 
- TCP_CONGESTION
 
- TCP_CONG_NEEDS_ECN
 
- TCP_CONG_NON_RESTRICTED
 
- TCP_CONNECT_ACTIVE
 
- TCP_CONNECT_PASSIVE
 
- TCP_CONNTRACK_CLOSE
 
- TCP_CONNTRACK_CLOSE_WAIT
 
- TCP_CONNTRACK_ESTABLISHED
 
- TCP_CONNTRACK_FIN_WAIT
 
- TCP_CONNTRACK_IGNORE
 
- TCP_CONNTRACK_LAST_ACK
 
- TCP_CONNTRACK_LISTEN
 
- TCP_CONNTRACK_MAX
 
- TCP_CONNTRACK_NONE
 
- TCP_CONNTRACK_RETRANS
 
- TCP_CONNTRACK_SYN_RECV
 
- TCP_CONNTRACK_SYN_SENT
 
- TCP_CONNTRACK_SYN_SENT2
 
- TCP_CONNTRACK_TIMEOUT_MAX
 
- TCP_CONNTRACK_TIME_WAIT
 
- TCP_CONNTRACK_UNACK
 
- TCP_CORK
 
- TCP_CREDIT__LFIFO_CREDIT_MASK
 
- TCP_CREDIT__LFIFO_CREDIT__SHIFT
 
- TCP_CREDIT__REQ_FIFO_CREDIT_MASK
 
- TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT
 
- TCP_CREDIT__TD_CREDIT_MASK
 
- TCP_CREDIT__TD_CREDIT__SHIFT
 
- TCP_CS
 
- TCP_CSUM_OFF
 
- TCP_DATA_OFFSET
 
- TCP_DEC_STATS
 
- TCP_DEFERRED_ALL
 
- TCP_DEFER_ACCEPT
 
- TCP_DELACK_MAX
 
- TCP_DELACK_MIN
 
- TCP_DELACK_TIMER_DEFERRED
 
- TCP_DIR_INPUT
 
- TCP_DIR_INPUT_ONLY
 
- TCP_DIR_OUTPUT
 
- TCP_DPORT
 
- TCP_DPORT_OFF
 
- TCP_DSACK_SEEN
 
- TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK
 
- TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT
 
- TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK
 
- TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT
 
- TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL_MASK
 
- TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL__SHIFT
 
- TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE_MASK
 
- TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE__SHIFT
 
- TCP_DSM_DATA_SEL
 
- TCP_DSM_DISABLE
 
- TCP_DSM_INJECT_SEL
 
- TCP_DSM_INJECT_SEL0
 
- TCP_DSM_INJECT_SEL1
 
- TCP_DSM_INJECT_SEL2
 
- TCP_DSM_INJECT_SEL3
 
- TCP_DSM_SEL0
 
- TCP_DSM_SEL1
 
- TCP_DSM_SEL_BOTH
 
- TCP_DSM_SINGLE_WRITE
 
- TCP_DSM_SINGLE_WRITE_DIS
 
- TCP_DSM_SINGLE_WRITE_EN
 
- TCP_ECN_DEMAND_CWR
 
- TCP_ECN_OK
 
- TCP_ECN_QUEUE_CWR
 
- TCP_ECN_SEEN
 
- TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT_MASK
 
- TCP_EDC_CNT_NEW__CACHE_RAM_DED_COUNT__SHIFT
 
- TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT_MASK
 
- TCP_EDC_CNT_NEW__CACHE_RAM_SEC_COUNT__SHIFT
 
- TCP_EDC_CNT_NEW__CMD_FIFO_SED_COUNT_MASK
 
- TCP_EDC_CNT_NEW__CMD_FIFO_SED_COUNT__SHIFT
 
- TCP_EDC_CNT_NEW__DB_RAM_SED_COUNT_MASK
 
- TCP_EDC_CNT_NEW__DB_RAM_SED_COUNT__SHIFT
 
- TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT_MASK
 
- TCP_EDC_CNT_NEW__LFIFO_RAM_DED_COUNT__SHIFT
 
- TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT_MASK
 
- TCP_EDC_CNT_NEW__LFIFO_RAM_SEC_COUNT__SHIFT
 
- TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT_MASK
 
- TCP_EDC_CNT_NEW__UTCL1_LFIFO0_DED_COUNT__SHIFT
 
- TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT_MASK
 
- TCP_EDC_CNT_NEW__UTCL1_LFIFO0_SEC_COUNT__SHIFT
 
- TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT_MASK
 
- TCP_EDC_CNT_NEW__UTCL1_LFIFO1_DED_COUNT__SHIFT
 
- TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT_MASK
 
- TCP_EDC_CNT_NEW__UTCL1_LFIFO1_SEC_COUNT__SHIFT
 
- TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT_MASK
 
- TCP_EDC_CNT_NEW__VM_FIFO_DED_COUNT__SHIFT
 
- TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT_MASK
 
- TCP_EDC_CNT_NEW__VM_FIFO_SEC_COUNT__SHIFT
 
- TCP_EDC_CNT__DED_COUNT_MASK
 
- TCP_EDC_CNT__DED_COUNT__SHIFT
 
- TCP_EDC_CNT__LFIFO_SED_COUNT_MASK
 
- TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT
 
- TCP_EDC_CNT__SEC_COUNT_MASK
 
- TCP_EDC_CNT__SEC_COUNT__SHIFT
 
- TCP_EDC_CNT__UNUSED_MASK
 
- TCP_EDC_CNT__UNUSED__SHIFT
 
- TCP_EDC_COUNTER__DED_COUNT_MASK
 
- TCP_EDC_COUNTER__DED_COUNT__SHIFT
 
- TCP_EDC_COUNTER__SEC_COUNT_MASK
 
- TCP_EDC_COUNTER__SEC_COUNT__SHIFT
 
- TCP_EDC_MASK
 
- TCP_EDC_SHIFT
 
- TCP_ESTABLISHED
 
- TCP_ESTATS_ACK_LATENCY
 
- TCP_ESTATS_ADDRTYPE_IPV4
 
- TCP_ESTATS_ADDRTYPE_IPV6
 
- TCP_ESTATS_CONN_TIMEOUT
 
- TCP_ESTATS_ESTABLISH
 
- TCP_ESTATS_MAGIC
 
- TCP_ESTATS_NEVENTS
 
- TCP_ESTATS_PERIODIC
 
- TCP_ESTATS_RETRANSMIT_OTHER
 
- TCP_ESTATS_RETRANSMIT_TIMEOUT
 
- TCP_ESTATS_RX_RESET
 
- TCP_ESTATS_SYNACK_RETRANSMIT
 
- TCP_ESTATS_SYN_RETRANSMIT
 
- TCP_ESTATS_TERM
 
- TCP_ESTATS_TIMEOUT
 
- TCP_ESTATS_TX_RESET
 
- TCP_ESTATS_WRITE_TIMEOUT
 
- TCP_EVENT_ADD_ISLE_LEFT
 
- TCP_EVENT_ADD_ISLE_RIGHT
 
- TCP_EVENT_ADD_NEW_ISLE
 
- TCP_EVENT_ADD_PEN
 
- TCP_EVENT_DELETE_ISLES
 
- TCP_EVENT_JOIN
 
- TCP_EVENT_NOP
 
- TCP_Enable_MASK
 
- TCP_Enable_SHIFT
 
- TCP_FASTOPEN
 
- TCP_FASTOPEN_CONNECT
 
- TCP_FASTOPEN_COOKIE_MAX
 
- TCP_FASTOPEN_COOKIE_MIN
 
- TCP_FASTOPEN_COOKIE_SIZE
 
- TCP_FASTOPEN_KEY
 
- TCP_FASTOPEN_KEY_BUF_LENGTH
 
- TCP_FASTOPEN_KEY_LENGTH
 
- TCP_FASTOPEN_KEY_MAX
 
- TCP_FASTOPEN_NO_COOKIE
 
- TCP_FASTRETRANS_THRESH
 
- TCP_FIN_SET
 
- TCP_FIN_TIMEOUT
 
- TCP_FIN_WAIT1
 
- TCP_FIN_WAIT2
 
- TCP_FLAGS_BE16
 
- TCP_FLAGS_OFFSET
 
- TCP_FLAG_ACK
 
- TCP_FLAG_CWR
 
- TCP_FLAG_ECE
 
- TCP_FLAG_FIN
 
- TCP_FLAG_PSH
 
- TCP_FLAG_RST
 
- TCP_FLAG_SYN
 
- TCP_FLAG_URG
 
- TCP_FO_SYSCTL
 
- TCP_FRAG_IN_RTX_QUEUE
 
- TCP_FRAG_IN_WRITE_QUEUE
 
- TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK
 
- TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT
 
- TCP_GATCL1_CNTL__FORCE_MISS_MASK
 
- TCP_GATCL1_CNTL__FORCE_MISS__SHIFT
 
- TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK
 
- TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT
 
- TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK
 
- TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT
 
- TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK
 
- TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT
 
- TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK
 
- TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT
 
- TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK
 
- TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT
 
- TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK
 
- TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT
 
- TCP_HDR_LEN
 
- TCP_HDR_LEN_G
 
- TCP_HDR_LEN_M
 
- TCP_HDR_LEN_S
 
- TCP_HDR_LEN_V
 
- TCP_HDR_SIZE
 
- TCP_HP_BITS
 
- TCP_INC_STATS
 
- TCP_INFINITE_SSTHRESH
 
- TCP_INFO
 
- TCP_INIT_CWND
 
- TCP_INQ
 
- TCP_INVALIDATE__START_MASK
 
- TCP_INVALIDATE__START__SHIFT
 
- TCP_INVALID_TIMEOUT_VAL
 
- TCP_IPV4
 
- TCP_IPV4_HASH_TYPE
 
- TCP_IPV6
 
- TCP_IPV6_HASH_TYPE
 
- TCP_IP_OFFLOAD
 
- TCP_IR_MASK
 
- TCP_IR_SHIFT
 
- TCP_KEEPALIVE_INTVL
 
- TCP_KEEPALIVE_PROBES
 
- TCP_KEEPALIVE_TIME
 
- TCP_KEEPCNT
 
- TCP_KEEPIDLE
 
- TCP_KEEPINTVL
 
- TCP_LARGESEND_PKTINFO
 
- TCP_LAST_ACK
 
- TCP_LINGER2
 
- TCP_LISTEN
 
- TCP_MAXSEG
 
- TCP_MAX_QUICKACKS
 
- TCP_MAX_STATES
 
- TCP_MAX_WSCALE
 
- TCP_MD5SIG
 
- TCP_MD5SIG_EXT
 
- TCP_MD5SIG_FLAG_PREFIX
 
- TCP_MD5SIG_MAXKEYLEN
 
- TCP_MEM_LOOPS
 
- TCP_METRICS_ATTR_ADDR_IPV4
 
- TCP_METRICS_ATTR_ADDR_IPV6
 
- TCP_METRICS_ATTR_AGE
 
- TCP_METRICS_ATTR_FOPEN_COOKIE
 
- TCP_METRICS_ATTR_FOPEN_MSS
 
- TCP_METRICS_ATTR_FOPEN_SYN_DROPS
 
- TCP_METRICS_ATTR_FOPEN_SYN_DROP_TS
 
- TCP_METRICS_ATTR_MAX
 
- TCP_METRICS_ATTR_PAD
 
- TCP_METRICS_ATTR_SADDR_IPV4
 
- TCP_METRICS_ATTR_SADDR_IPV6
 
- TCP_METRICS_ATTR_TW_TSVAL
 
- TCP_METRICS_ATTR_TW_TS_STAMP
 
- TCP_METRICS_ATTR_UNSPEC
 
- TCP_METRICS_ATTR_VALS
 
- TCP_METRICS_CMD_DEL
 
- TCP_METRICS_CMD_GET
 
- TCP_METRICS_CMD_MAX
 
- TCP_METRICS_CMD_UNSPEC
 
- TCP_METRICS_GENL_NAME
 
- TCP_METRICS_GENL_VERSION
 
- TCP_METRICS_RECLAIM_DEPTH
 
- TCP_METRICS_RECLAIM_PTR
 
- TCP_METRICS_TIMEOUT
 
- TCP_METRIC_CWND
 
- TCP_METRIC_MAX
 
- TCP_METRIC_MAX_KERNEL
 
- TCP_METRIC_REORDERING
 
- TCP_METRIC_RTT
 
- TCP_METRIC_RTTVAR
 
- TCP_METRIC_RTTVAR_US
 
- TCP_METRIC_RTT_US
 
- TCP_METRIC_SSTHRESH
 
- TCP_MIB_ACTIVEOPENS
 
- TCP_MIB_ATTEMPTFAILS
 
- TCP_MIB_CSUMERRORS
 
- TCP_MIB_CURRESTAB
 
- TCP_MIB_ESTABRESETS
 
- TCP_MIB_INERRS
 
- TCP_MIB_INSEGS
 
- TCP_MIB_MAX
 
- TCP_MIB_MAXCONN
 
- TCP_MIB_NUM
 
- TCP_MIB_OUTRSTS
 
- TCP_MIB_OUTSEGS
 
- TCP_MIB_PASSIVEOPENS
 
- TCP_MIB_RETRANSSEGS
 
- TCP_MIB_RTOALGORITHM
 
- TCP_MIB_RTOMAX
 
- TCP_MIB_RTOMIN
 
- TCP_MIN_GSO_SIZE
 
- TCP_MIN_MSS
 
- TCP_MIN_SND_MSS
 
- TCP_MSS_DEFAULT
 
- TCP_MSS_DESIRED
 
- TCP_MTU_REDUCED_DEFERRED
 
- TCP_NAGLE_CORK
 
- TCP_NAGLE_OFF
 
- TCP_NAGLE_PUSH
 
- TCP_NEW_SYN_RECV
 
- TCP_NLATTR_SIZE
 
- TCP_NLA_BUSY
 
- TCP_NLA_BYTES_RETRANS
 
- TCP_NLA_BYTES_SENT
 
- TCP_NLA_CA_STATE
 
- TCP_NLA_DATA_SEGS_OUT
 
- TCP_NLA_DELIVERED
 
- TCP_NLA_DELIVERED_CE
 
- TCP_NLA_DELIVERY_RATE
 
- TCP_NLA_DELIVERY_RATE_APP_LMT
 
- TCP_NLA_DSACK_DUPS
 
- TCP_NLA_MIN_RTT
 
- TCP_NLA_PACING_RATE
 
- TCP_NLA_PAD
 
- TCP_NLA_RECUR_RETRANS
 
- TCP_NLA_REORDERING
 
- TCP_NLA_REORD_SEEN
 
- TCP_NLA_RWND_LIMITED
 
- TCP_NLA_SNDBUF_LIMITED
 
- TCP_NLA_SNDQ_SIZE
 
- TCP_NLA_SND_CWND
 
- TCP_NLA_SND_SSTHRESH
 
- TCP_NLA_SRTT
 
- TCP_NLA_TOTAL_RETRANS
 
- TCP_NODELAY
 
- TCP_NONE_SET
 
- TCP_NOTSENT_LOWAT
 
- TCP_NO_QUEUE
 
- TCP_NUM_SACKS
 
- TCP_OFDL_EN
 
- TCP_OFF
 
- TCP_OFFLOAD_ENABLE
 
- TCP_OFFLOAD_PARAMS_DA_CNT_EN_MASK
 
- TCP_OFFLOAD_PARAMS_DA_CNT_EN_SHIFT
 
- TCP_OFFLOAD_PARAMS_DA_EN_MASK
 
- TCP_OFFLOAD_PARAMS_DA_EN_SHIFT
 
- TCP_OFFLOAD_PARAMS_ECN_RECEIVER_EN_MASK
 
- TCP_OFFLOAD_PARAMS_ECN_RECEIVER_EN_SHIFT
 
- TCP_OFFLOAD_PARAMS_ECN_SENDER_EN_MASK
 
- TCP_OFFLOAD_PARAMS_ECN_SENDER_EN_SHIFT
 
- TCP_OFFLOAD_PARAMS_FIN_RECEIVED_MASK
 
- TCP_OFFLOAD_PARAMS_FIN_RECEIVED_SHIFT
 
- TCP_OFFLOAD_PARAMS_FIN_SENT_MASK
 
- TCP_OFFLOAD_PARAMS_FIN_SENT_SHIFT
 
- TCP_OFFLOAD_PARAMS_KA_EN_MASK
 
- TCP_OFFLOAD_PARAMS_KA_EN_SHIFT
 
- TCP_OFFLOAD_PARAMS_NAGLE_EN_MASK
 
- TCP_OFFLOAD_PARAMS_NAGLE_EN_SHIFT
 
- TCP_OFFLOAD_PARAMS_OPT2_DA_EN_MASK
 
- TCP_OFFLOAD_PARAMS_OPT2_DA_EN_SHIFT
 
- TCP_OFFLOAD_PARAMS_OPT2_ECN_EN_MASK
 
- TCP_OFFLOAD_PARAMS_OPT2_ECN_EN_SHIFT
 
- TCP_OFFLOAD_PARAMS_OPT2_KA_EN_MASK
 
- TCP_OFFLOAD_PARAMS_OPT2_KA_EN_SHIFT
 
- TCP_OFFLOAD_PARAMS_OPT2_RESERVED0_MASK
 
- TCP_OFFLOAD_PARAMS_OPT2_RESERVED0_SHIFT
 
- TCP_OFFLOAD_PARAMS_OPT2_TS_EN_MASK
 
- TCP_OFFLOAD_PARAMS_OPT2_TS_EN_SHIFT
 
- TCP_OFFLOAD_PARAMS_RESERVED_MASK
 
- TCP_OFFLOAD_PARAMS_RESERVED_SHIFT
 
- TCP_OFFLOAD_PARAMS_TS_EN_MASK
 
- TCP_OFFLOAD_PARAMS_TS_EN_SHIFT
 
- TCP_OPCODE_ATOMIC
 
- TCP_OPCODE_ATOMIC_CMPSWAP
 
- TCP_OPCODE_GATHERH
 
- TCP_OPCODE_READ
 
- TCP_OPCODE_TYPE
 
- TCP_OPCODE_WBINVL1
 
- TCP_OPCODE_WRITE
 
- TCP_OPTIONS_PADDING
 
- TCP_OPTION_LEN
 
- TCP_OR_UDP_FRAME
 
- TCP_PAGE
 
- TCP_PAWS_24DAYS
 
- TCP_PAWS_MSL
 
- TCP_PAWS_WINDOW
 
- TCP_PCC_MASK
 
- TCP_PCC_SHIFT
 
- TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK
 
- TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT
 
- TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK
 
- TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT
 
- TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK
 
- TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT
 
- TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK
 
- TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT
 
- TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK
 
- TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT
 
- TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK
 
- TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT
 
- TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK
 
- TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT
 
- TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK
 
- TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT
 
- TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK
 
- TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT
 
- TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK
 
- TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT
 
- TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK
 
- TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT
 
- TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK
 
- TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT
 
- TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK
 
- TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT
 
- TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK
 
- TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT
 
- TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK
 
- TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT
 
- TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK
 
- TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT
 
- TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK
 
- TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT
 
- TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK
 
- TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT
 
- TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK
 
- TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT
 
- TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK
 
- TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT
 
- TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK
 
- TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT
 
- TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK
 
- TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT
 
- TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK
 
- TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT
 
- TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK
 
- TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT
 
- TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK
 
- TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT
 
- TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK
 
- TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT
 
- TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK
 
- TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT
 
- TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK
 
- TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT
 
- TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK
 
- TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT
 
- TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK
 
- TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT
 
- TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK
 
- TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT
 
- TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK
 
- TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT
 
- TCP_PERFCOUNTER_FILTER2__REQ_MODE_MASK
 
- TCP_PERFCOUNTER_FILTER2__REQ_MODE__SHIFT
 
- TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE_MASK
 
- TCP_PERFCOUNTER_FILTER_EN__ADDR_MODE__SHIFT
 
- TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK
 
- TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT
 
- TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK
 
- TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT
 
- TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK
 
- TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT
 
- TCP_PERFCOUNTER_FILTER_EN__DIM_MASK
 
- TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT
 
- TCP_PERFCOUNTER_FILTER_EN__DLC_MASK
 
- TCP_PERFCOUNTER_FILTER_EN__DLC__SHIFT
 
- TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK
 
- TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT
 
- TCP_PERFCOUNTER_FILTER_EN__GLC_MASK
 
- TCP_PERFCOUNTER_FILTER_EN__GLC__SHIFT
 
- TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK
 
- TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT
 
- TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK
 
- TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT
 
- TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK
 
- TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT
 
- TCP_PERFCOUNTER_FILTER_EN__REQ_MODE_MASK
 
- TCP_PERFCOUNTER_FILTER_EN__REQ_MODE__SHIFT
 
- TCP_PERFCOUNTER_FILTER_EN__SLC_MASK
 
- TCP_PERFCOUNTER_FILTER_EN__SLC__SHIFT
 
- TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK
 
- TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT
 
- TCP_PERFCOUNTER_FILTER__ADDR_MODE_MASK
 
- TCP_PERFCOUNTER_FILTER__ADDR_MODE__SHIFT
 
- TCP_PERFCOUNTER_FILTER__BUFFER_MASK
 
- TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT
 
- TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK
 
- TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT
 
- TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK
 
- TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT
 
- TCP_PERFCOUNTER_FILTER__DIM_MASK
 
- TCP_PERFCOUNTER_FILTER__DIM__SHIFT
 
- TCP_PERFCOUNTER_FILTER__DLC_MASK
 
- TCP_PERFCOUNTER_FILTER__DLC__SHIFT
 
- TCP_PERFCOUNTER_FILTER__FLAT_MASK
 
- TCP_PERFCOUNTER_FILTER__FLAT__SHIFT
 
- TCP_PERFCOUNTER_FILTER__GLC_MASK
 
- TCP_PERFCOUNTER_FILTER__GLC__SHIFT
 
- TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK
 
- TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT
 
- TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK
 
- TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT
 
- TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK
 
- TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT
 
- TCP_PERFCOUNTER_FILTER__SLC_MASK
 
- TCP_PERFCOUNTER_FILTER__SLC__SHIFT
 
- TCP_PERFCOUNTER_FILTER__SW_MODE_MASK
 
- TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT
 
- TCP_PERFCOUNT_SELECT
 
- TCP_PERF_SEL_ALLOC_STALL_CYCLES
 
- TCP_PERF_SEL_ARR_1D_THICK
 
- TCP_PERF_SEL_ARR_1D_THIN1
 
- TCP_PERF_SEL_ARR_2D_THICK
 
- TCP_PERF_SEL_ARR_2D_THIN1
 
- TCP_PERF_SEL_ARR_2D_XTHICK
 
- TCP_PERF_SEL_ARR_3D_THICK
 
- TCP_PERF_SEL_ARR_3D_THIN1
 
- TCP_PERF_SEL_ARR_3D_XTHICK
 
- TCP_PERF_SEL_ARR_LINEAR_ALIGNED
 
- TCP_PERF_SEL_ARR_LINEAR_GENERAL
 
- TCP_PERF_SEL_ARR_PRT_2D_THICK
 
- TCP_PERF_SEL_ARR_PRT_2D_THIN1
 
- TCP_PERF_SEL_ARR_PRT_3D_THICK
 
- TCP_PERF_SEL_ARR_PRT_3D_THIN1
 
- TCP_PERF_SEL_ARR_PRT_THICK
 
- TCP_PERF_SEL_ARR_PRT_THIN1
 
- TCP_PERF_SEL_ATC
 
- TCP_PERF_SEL_ATCL1_SERIALIZATION_STALL
 
- TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES
 
- TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32
 
- TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64
 
- TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32
 
- TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64
 
- TCP_PERF_SEL_BUF_READ_FMT_16
 
- TCP_PERF_SEL_BUF_READ_FMT_32
 
- TCP_PERF_SEL_BUF_READ_FMT_8
 
- TCP_PERF_SEL_BUF_WRITE_FMT_16
 
- TCP_PERF_SEL_BUF_WRITE_FMT_32
 
- TCP_PERF_SEL_BUF_WRITE_FMT_8
 
- TCP_PERF_SEL_CLIENT_UTCL0_INFLIGHT
 
- TCP_PERF_SEL_CORE_REG_SCLK_VLD
 
- TCP_PERF_SEL_CP_TCP_INVALIDATE
 
- TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL
 
- TCP_PERF_SEL_DEPTH_MICROTILING
 
- TCP_PERF_SEL_DIM_1D
 
- TCP_PERF_SEL_DIM_1D_ARRAY
 
- TCP_PERF_SEL_DIM_2D
 
- TCP_PERF_SEL_DIM_2D_ARRAY
 
- TCP_PERF_SEL_DIM_2D_ARRAY_MSAA
 
- TCP_PERF_SEL_DIM_2D_MSAA
 
- TCP_PERF_SEL_DIM_3D
 
- TCP_PERF_SEL_DIM_CUBE_ARRAY
 
- TCP_PERF_SEL_DISPLAY_MICROTILING
 
- TCP_PERF_SEL_GATCL1_ATCL2_INFLIGHT
 
- TCP_PERF_SEL_GATCL1_LFIFO_FULL
 
- TCP_PERF_SEL_GATCL1_PERMISSION_MISS
 
- TCP_PERF_SEL_GATCL1_REQUEST
 
- TCP_PERF_SEL_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS
 
- TCP_PERF_SEL_GATCL1_STALL_INFLIGHT_MAX
 
- TCP_PERF_SEL_GATCL1_STALL_LFIFO_NOT_RES
 
- TCP_PERF_SEL_GATCL1_STALL_LRU_INFLIGHT
 
- TCP_PERF_SEL_GATCL1_STALL_MISSFIFO_FULL
 
- TCP_PERF_SEL_GATCL1_TRANSLATION_MISS
 
- TCP_PERF_SEL_GATE_EN1
 
- TCP_PERF_SEL_GATE_EN2
 
- TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET
 
- TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET
 
- TCP_PERF_SEL_GL1_REQ_READ
 
- TCP_PERF_SEL_GL1_REQ_READ_LATENCY
 
- TCP_PERF_SEL_GL1_REQ_WRITE
 
- TCP_PERF_SEL_GL1_REQ_WRITE_LATENCY
 
- TCP_PERF_SEL_HOLE_READ_STALL
 
- TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32
 
- TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64
 
- TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32
 
- TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64
 
- TCP_PERF_SEL_IMG_READ_FMT_1
 
- TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE
 
- TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE
 
- TCP_PERF_SEL_IMG_READ_FMT_16
 
- TCP_PERF_SEL_IMG_READ_FMT_16_AS_128
 
- TCP_PERF_SEL_IMG_READ_FMT_16_AS_64
 
- TCP_PERF_SEL_IMG_READ_FMT_32
 
- TCP_PERF_SEL_IMG_READ_FMT_32_AS_128
 
- TCP_PERF_SEL_IMG_READ_FMT_32_AS_16
 
- TCP_PERF_SEL_IMG_READ_FMT_32_AS_8
 
- TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE
 
- TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE
 
- TCP_PERF_SEL_IMG_READ_FMT_8
 
- TCP_PERF_SEL_IMG_READ_FMT_8_AS_32
 
- TCP_PERF_SEL_IMG_READ_FMT_8_AS_64
 
- TCP_PERF_SEL_IMG_READ_FMT_96
 
- TCP_PERF_SEL_IMG_READ_FMT_BC1
 
- TCP_PERF_SEL_IMG_READ_FMT_BC2
 
- TCP_PERF_SEL_IMG_READ_FMT_BC3
 
- TCP_PERF_SEL_IMG_READ_FMT_BC4
 
- TCP_PERF_SEL_IMG_READ_FMT_BC5
 
- TCP_PERF_SEL_IMG_READ_FMT_BC6
 
- TCP_PERF_SEL_IMG_READ_FMT_BC7
 
- TCP_PERF_SEL_IMG_READ_FMT_D16
 
- TCP_PERF_SEL_IMG_READ_FMT_D32
 
- TCP_PERF_SEL_IMG_READ_FMT_D8
 
- TCP_PERF_SEL_IMG_READ_FMT_ETC2_R
 
- TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG
 
- TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB
 
- TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA
 
- TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1
 
- TCP_PERF_SEL_IMG_READ_FMT_I16
 
- TCP_PERF_SEL_IMG_READ_FMT_I32
 
- TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16
 
- TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8
 
- TCP_PERF_SEL_IMG_READ_FMT_I8
 
- TCP_PERF_SEL_IMG_WRITE_FMT_128
 
- TCP_PERF_SEL_IMG_WRITE_FMT_16
 
- TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128
 
- TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64
 
- TCP_PERF_SEL_IMG_WRITE_FMT_32
 
- TCP_PERF_SEL_IMG_WRITE_FMT_64
 
- TCP_PERF_SEL_IMG_WRITE_FMT_8
 
- TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32
 
- TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64
 
- TCP_PERF_SEL_IMG_WRITE_FMT_D16
 
- TCP_PERF_SEL_IMG_WRITE_FMT_D32
 
- TCP_PERF_SEL_IMG_WRITE_FMT_D8
 
- TCP_PERF_SEL_LFIFO_STALL_CYCLES
 
- TCP_PERF_SEL_LOD_STALL_CYCLES
 
- TCP_PERF_SEL_PENDING_STALL_CYCLES
 
- TCP_PERF_SEL_POWER_STALL
 
- TCP_PERF_SEL_READCONFLICT_STALL_CYCLES
 
- TCP_PERF_SEL_READFIFO_STALL_CYCLES
 
- TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES
 
- TCP_PERF_SEL_REQ_MISS_TAGRAM0
 
- TCP_PERF_SEL_REQ_MISS_TAGRAM1
 
- TCP_PERF_SEL_REQ_MISS_TAGRAM2
 
- TCP_PERF_SEL_REQ_MISS_TAGRAM3
 
- TCP_PERF_SEL_RESERVED_154
 
- TCP_PERF_SEL_RFIFO_STALL_CYCLES
 
- TCP_PERF_SEL_ROTATED_MICROTILING
 
- TCP_PERF_SEL_SHOOTDOWN
 
- TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL
 
- TCP_PERF_SEL_TAGRAM0_REQ
 
- TCP_PERF_SEL_TAGRAM1_REQ
 
- TCP_PERF_SEL_TAGRAM2_REQ
 
- TCP_PERF_SEL_TAGRAM3_REQ
 
- TCP_PERF_SEL_TA_REQ
 
- TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET
 
- TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET
 
- TCP_PERF_SEL_TA_REQ_READ
 
- TCP_PERF_SEL_TA_REQ_STATE_READ
 
- TCP_PERF_SEL_TA_REQ_WRITE
 
- TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES
 
- TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES
 
- TCP_PERF_SEL_TA_TCP_STATE_READ
 
- TCP_PERF_SEL_TCC_ATOMIC_REQ
 
- TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ
 
- TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ
 
- TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ
 
- TCP_PERF_SEL_TCC_BYPASS_READ_REQ
 
- TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ
 
- TCP_PERF_SEL_TCC_CC_ATOMIC_REQ
 
- TCP_PERF_SEL_TCC_CC_READ_REQ
 
- TCP_PERF_SEL_TCC_CC_WRITE_REQ
 
- TCP_PERF_SEL_TCC_DATA_BUS_BUSY
 
- TCP_PERF_SEL_TCC_DCC_REQ
 
- TCP_PERF_SEL_TCC_LRU_REQ
 
- TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ
 
- TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ
 
- TCP_PERF_SEL_TCC_NC_ATOMIC_REQ
 
- TCP_PERF_SEL_TCC_NC_READ_REQ
 
- TCP_PERF_SEL_TCC_NC_WRITE_REQ
 
- TCP_PERF_SEL_TCC_NON_READ_REQ
 
- TCP_PERF_SEL_TCC_PHYSICAL_REQ
 
- TCP_PERF_SEL_TCC_READ_REQ
 
- TCP_PERF_SEL_TCC_READ_REQ_LATENCY
 
- TCP_PERF_SEL_TCC_REQ
 
- TCP_PERF_SEL_TCC_STREAM_REQ
 
- TCP_PERF_SEL_TCC_UC_ATOMIC_REQ
 
- TCP_PERF_SEL_TCC_UC_READ_REQ
 
- TCP_PERF_SEL_TCC_UC_WRITE_REQ
 
- TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ
 
- TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ
 
- TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ
 
- TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ
 
- TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ
 
- TCP_PERF_SEL_TCC_VOLATILE_READ_REQ
 
- TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ
 
- TCP_PERF_SEL_TCC_WRITE_REQ
 
- TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY
 
- TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY
 
- TCP_PERF_SEL_TCP_LATENCY
 
- TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES
 
- TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES
 
- TCP_PERF_SEL_TCP_TCR_STARVE_CYCLES
 
- TCP_PERF_SEL_TCR_RDRET_STALL
 
- TCP_PERF_SEL_TCR_TCP_STALL_CYCLES
 
- TCP_PERF_SEL_TC_TA_XNACK_STALL
 
- TCP_PERF_SEL_TD_TCP_STALL_CYCLES
 
- TCP_PERF_SEL_THICK_MICROTILING
 
- TCP_PERF_SEL_THIN_MICROTILING
 
- TCP_PERF_SEL_TOTAL_ACCESSES
 
- TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET
 
- TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET
 
- TCP_PERF_SEL_TOTAL_CACHE_ACCESSES
 
- TCP_PERF_SEL_TOTAL_GLOBAL_READ
 
- TCP_PERF_SEL_TOTAL_GLOBAL_WRITE
 
- TCP_PERF_SEL_TOTAL_HIT_EVICT_READ
 
- TCP_PERF_SEL_TOTAL_HIT_LRU_READ
 
- TCP_PERF_SEL_TOTAL_LOCAL_READ
 
- TCP_PERF_SEL_TOTAL_LOCAL_WRITE
 
- TCP_PERF_SEL_TOTAL_MISS_EVICT_READ
 
- TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE
 
- TCP_PERF_SEL_TOTAL_MISS_LRU_READ
 
- TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE
 
- TCP_PERF_SEL_TOTAL_NON_READ
 
- TCP_PERF_SEL_TOTAL_READ
 
- TCP_PERF_SEL_TOTAL_WBINVL1
 
- TCP_PERF_SEL_TOTAL_WBINVL1_VOL
 
- TCP_PERF_SEL_TOTAL_WRITE
 
- TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES
 
- TCP_PERF_SEL_UNALIGNED
 
- TCP_PERF_SEL_UNORDERED_MTYPE_STALL
 
- TCP_PERF_SEL_UTCL0_LFIFO_FULL
 
- TCP_PERF_SEL_UTCL0_PERMISSION_MISS
 
- TCP_PERF_SEL_UTCL0_REQUEST
 
- TCP_PERF_SEL_UTCL0_SERIALIZATION_STALL
 
- TCP_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX
 
- TCP_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES
 
- TCP_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT
 
- TCP_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL
 
- TCP_PERF_SEL_UTCL0_STALL_MULTI_MISS
 
- TCP_PERF_SEL_UTCL0_STALL_UTCL2_REQ_OUT_OF_CREDITS
 
- TCP_PERF_SEL_UTCL0_TRANSLATION_HIT
 
- TCP_PERF_SEL_UTCL0_TRANSLATION_MISS
 
- TCP_PERF_SEL_UTCL0_UTCL2_INFLIGHT
 
- TCP_PERF_SEL_UTCL1_LFIFO_FULL
 
- TCP_PERF_SEL_UTCL1_PERMISSION_MISS
 
- TCP_PERF_SEL_UTCL1_REQUEST
 
- TCP_PERF_SEL_UTCL1_SERIALIZATION_STALL
 
- TCP_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX
 
- TCP_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES
 
- TCP_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT
 
- TCP_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL
 
- TCP_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS
 
- TCP_PERF_SEL_UTCL1_TRANSLATION_MISS
 
- TCP_PERF_SEL_UTCL1_UTCL2_INFLIGHT
 
- TCP_PERF_SEL_VOLATILE
 
- TCP_PERF_SEL_WRITE_CONFLICT_STALL
 
- TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES
 
- TCP_PINGPONG_THRESH
 
- TCP_PORT_ISCSI
 
- TCP_PROBE_INTERVAL
 
- TCP_PROBE_THRESHOLD
 
- TCP_PS_NOT_REQUIRED
 
- TCP_PS_REQUIRED
 
- TCP_PUSH_BIT
 
- TCP_QUEUES_NR
 
- TCP_QUEUE_SEQ
 
- TCP_QUICKACK
 
- TCP_RACK_LOSS_DETECTION
 
- TCP_RACK_NO_DUPTHRESH
 
- TCP_RACK_RECOVERY_THRESH
 
- TCP_RACK_STATIC_REO_WND
 
- TCP_RECV_QUEUE
 
- TCP_REMNANT
 
- TCP_REPAIR
 
- TCP_REPAIR_OFF
 
- TCP_REPAIR_OFF_NO_WP
 
- TCP_REPAIR_ON
 
- TCP_REPAIR_OPTIONS
 
- TCP_REPAIR_QUEUE
 
- TCP_REPAIR_WINDOW
 
- TCP_RESERVED_BITS
 
- TCP_RESOURCE_PROBE_INTERVAL
 
- TCP_RETR1
 
- TCP_RETR2
 
- TCP_RST_SET
 
- TCP_RTO_MAX
 
- TCP_RTO_MIN
 
- TCP_SACK_SEEN
 
- TCP_SAVED_SYN
 
- TCP_SAVE_SYN
 
- TCP_SCALABLE_AI_CNT
 
- TCP_SCALABLE_MD_SCALE
 
- TCP_SEND_QUEUE
 
- TCP_SEQ_STATE_ESTABLISHED
 
- TCP_SEQ_STATE_LISTENING
 
- TCP_SKB_CB
 
- TCP_SKB_MIN_TRUESIZE
 
- TCP_SPORT
 
- TCP_STATE_MASK
 
- TCP_STATUS__ADRS_BUSY_MASK
 
- TCP_STATUS__ADRS_BUSY__SHIFT
 
- TCP_STATUS__CNTRL_BUSY_MASK
 
- TCP_STATUS__CNTRL_BUSY__SHIFT
 
- TCP_STATUS__FORMAT_BUSY_MASK
 
- TCP_STATUS__FORMAT_BUSY__SHIFT
 
- TCP_STATUS__INPUT_BUSY_MASK
 
- TCP_STATUS__INPUT_BUSY__SHIFT
 
- TCP_STATUS__LFIFO_BUSY_MASK
 
- TCP_STATUS__LFIFO_BUSY__SHIFT
 
- TCP_STATUS__MEMIF_BUSY_MASK
 
- TCP_STATUS__MEMIF_BUSY__SHIFT
 
- TCP_STATUS__OFIFO_BUSY_MASK
 
- TCP_STATUS__OFIFO_BUSY__SHIFT
 
- TCP_STATUS__READ_BUSY_MASK
 
- TCP_STATUS__READ_BUSY__SHIFT
 
- TCP_STATUS__TAGRAMS_BUSY_MASK
 
- TCP_STATUS__TAGRAMS_BUSY__SHIFT
 
- TCP_STATUS__TCP_BUSY_MASK
 
- TCP_STATUS__TCP_BUSY__SHIFT
 
- TCP_STATUS__VM_BUSY_MASK
 
- TCP_STATUS__VM_BUSY__SHIFT
 
- TCP_SYNACK_COOKIE
 
- TCP_SYNACK_FASTOPEN
 
- TCP_SYNACK_NORMAL
 
- TCP_SYNACK_RETRIES
 
- TCP_SYNACK_SET
 
- TCP_SYNCNT
 
- TCP_SYNCOOKIE_PERIOD
 
- TCP_SYNCOOKIE_SYSCTL
 
- TCP_SYNCOOKIE_VALID
 
- TCP_SYNQ_INTERVAL
 
- TCP_SYN_RECV
 
- TCP_SYN_RETRIES
 
- TCP_SYN_SENT
 
- TCP_SYN_SET
 
- TCP_Server_Info
 
- TCP_THIN_DUPACK
 
- TCP_THIN_LINEAR_RETRIES
 
- TCP_THIN_LINEAR_TIMEOUTS
 
- TCP_TIMEOUT_FALLBACK
 
- TCP_TIMEOUT_INIT
 
- TCP_TIMEOUT_MIN
 
- TCP_TIMESTAMP
 
- TCP_TIMEWAIT_LEN
 
- TCP_TIME_WAIT
 
- TCP_TSQ_DEFERRED
 
- TCP_TSTORM_OOO_DROP_AND_PROC_ACK
 
- TCP_TSTORM_OOO_SEND_PURE_ACK
 
- TCP_TSTORM_OOO_SUPPORTED
 
- TCP_TS_HDR_SIZE
 
- TCP_TS_HZ
 
- TCP_TS_OPTION_SIZE
 
- TCP_TW_ACK
 
- TCP_TW_RST
 
- TCP_TW_SUCCESS
 
- TCP_TW_SYN
 
- TCP_TX_DELAY
 
- TCP_ULP
 
- TCP_ULP_BUF_MAX
 
- TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_MASK
 
- TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_SHIFT
 
- TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_MASK
 
- TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_SHIFT
 
- TCP_ULP_MAX
 
- TCP_ULP_NAME_MAX
 
- TCP_UPDATE_PARAMS_FLOW_LABEL_CHANGED_MASK
 
- TCP_UPDATE_PARAMS_FLOW_LABEL_CHANGED_SHIFT
 
- TCP_UPDATE_PARAMS_INITIAL_RCV_WND_CHANGED_MASK
 
- TCP_UPDATE_PARAMS_INITIAL_RCV_WND_CHANGED_SHIFT
 
- TCP_UPDATE_PARAMS_KA_EN_CHANGED_MASK
 
- TCP_UPDATE_PARAMS_KA_EN_CHANGED_SHIFT
 
- TCP_UPDATE_PARAMS_KA_EN_MASK
 
- TCP_UPDATE_PARAMS_KA_EN_SHIFT
 
- TCP_UPDATE_PARAMS_KA_INTERVAL_CHANGED_MASK
 
- TCP_UPDATE_PARAMS_KA_INTERVAL_CHANGED_SHIFT
 
- TCP_UPDATE_PARAMS_KA_MAX_PROBE_CNT_CHANGED_MASK
 
- TCP_UPDATE_PARAMS_KA_MAX_PROBE_CNT_CHANGED_SHIFT
 
- TCP_UPDATE_PARAMS_KA_RESTART_MASK
 
- TCP_UPDATE_PARAMS_KA_RESTART_SHIFT
 
- TCP_UPDATE_PARAMS_KA_TIMEOUT_CHANGED_MASK
 
- TCP_UPDATE_PARAMS_KA_TIMEOUT_CHANGED_SHIFT
 
- TCP_UPDATE_PARAMS_MAX_RT_TIME_CHANGED_MASK
 
- TCP_UPDATE_PARAMS_MAX_RT_TIME_CHANGED_SHIFT
 
- TCP_UPDATE_PARAMS_MSS_CHANGED_MASK
 
- TCP_UPDATE_PARAMS_MSS_CHANGED_SHIFT
 
- TCP_UPDATE_PARAMS_NAGLE_EN_CHANGED_MASK
 
- TCP_UPDATE_PARAMS_NAGLE_EN_CHANGED_SHIFT
 
- TCP_UPDATE_PARAMS_NAGLE_EN_MASK
 
- TCP_UPDATE_PARAMS_NAGLE_EN_SHIFT
 
- TCP_UPDATE_PARAMS_REMOTE_MAC_ADDR_CHANGED_MASK
 
- TCP_UPDATE_PARAMS_REMOTE_MAC_ADDR_CHANGED_SHIFT
 
- TCP_UPDATE_PARAMS_RETRANSMIT_RESTART_MASK
 
- TCP_UPDATE_PARAMS_RETRANSMIT_RESTART_SHIFT
 
- TCP_UPDATE_PARAMS_TOS_OR_TC_CHANGED_MASK
 
- TCP_UPDATE_PARAMS_TOS_OR_TC_CHANGED_SHIFT
 
- TCP_UPDATE_PARAMS_TTL_CHANGED_MASK
 
- TCP_UPDATE_PARAMS_TTL_CHANGED_SHIFT
 
- TCP_URG_NOTYET
 
- TCP_URG_READ
 
- TCP_URG_VALID
 
- TCP_USER_TIMEOUT
 
- TCP_UTCL0_CNTL1__CLIENTID_MASK
 
- TCP_UTCL0_CNTL1__CLIENTID__SHIFT
 
- TCP_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK
 
- TCP_UTCL0_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT
 
- TCP_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK
 
- TCP_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT
 
- TCP_UTCL0_CNTL1__FORCE_MISS_MASK
 
- TCP_UTCL0_CNTL1__FORCE_MISS__SHIFT
 
- TCP_UTCL0_CNTL1__GPUVM_64K_DEFAULT_MASK
 
- TCP_UTCL0_CNTL1__GPUVM_64K_DEFAULT__SHIFT
 
- TCP_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK
 
- TCP_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT
 
- TCP_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK
 
- TCP_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT
 
- TCP_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK
 
- TCP_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT
 
- TCP_UTCL0_CNTL1__REG_INV_ALL_VMID_MASK
 
- TCP_UTCL0_CNTL1__REG_INV_ALL_VMID__SHIFT
 
- TCP_UTCL0_CNTL1__REG_INV_TOGGLE_MASK
 
- TCP_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT
 
- TCP_UTCL0_CNTL1__REG_INV_VMID_MASK
 
- TCP_UTCL0_CNTL1__REG_INV_VMID__SHIFT
 
- TCP_UTCL0_CNTL1__RESP_FAULT_MODE_MASK
 
- TCP_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT
 
- TCP_UTCL0_CNTL1__RESP_MODE_MASK
 
- TCP_UTCL0_CNTL1__RESP_MODE__SHIFT
 
- TCP_UTCL0_CNTL2__ANY_LINE_VALID_MASK
 
- TCP_UTCL0_CNTL2__ANY_LINE_VALID__SHIFT
 
- TCP_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK
 
- TCP_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT
 
- TCP_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK_MASK
 
- TCP_UTCL0_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT
 
- TCP_UTCL0_CNTL2__FORCE_SNOOP_MASK
 
- TCP_UTCL0_CNTL2__FORCE_SNOOP__SHIFT
 
- TCP_UTCL0_CNTL2__GPUVM_16K_DEFAULT_MASK
 
- TCP_UTCL0_CNTL2__GPUVM_16K_DEFAULT__SHIFT
 
- TCP_UTCL0_CNTL2__GPUVM_INV_MODE_MASK
 
- TCP_UTCL0_CNTL2__GPUVM_INV_MODE__SHIFT
 
- TCP_UTCL0_CNTL2__LINE_INVALIDATE_OPT_MASK
 
- TCP_UTCL0_CNTL2__LINE_INVALIDATE_OPT__SHIFT
 
- TCP_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK
 
- TCP_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT
 
- TCP_UTCL0_CNTL2__PERM_MODE_OVRD_MASK
 
- TCP_UTCL0_CNTL2__PERM_MODE_OVRD__SHIFT
 
- TCP_UTCL0_CNTL2__SPARE_MASK
 
- TCP_UTCL0_CNTL2__SPARE__SHIFT
 
- TCP_UTCL0_STATUS__FAULT_DETECTED_MASK
 
- TCP_UTCL0_STATUS__FAULT_DETECTED__SHIFT
 
- TCP_UTCL0_STATUS__PRT_DETECTED_MASK
 
- TCP_UTCL0_STATUS__PRT_DETECTED__SHIFT
 
- TCP_UTCL0_STATUS__RETRY_DETECTED_MASK
 
- TCP_UTCL0_STATUS__RETRY_DETECTED__SHIFT
 
- TCP_UTCL1_CNTL1__CLIENTID_MASK
 
- TCP_UTCL1_CNTL1__CLIENTID__SHIFT
 
- TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK
 
- TCP_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT
 
- TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK
 
- TCP_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT
 
- TCP_UTCL1_CNTL1__FORCE_MISS_MASK
 
- TCP_UTCL1_CNTL1__FORCE_MISS__SHIFT
 
- TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT_MASK
 
- TCP_UTCL1_CNTL1__GPUVM_64K_DEFAULT__SHIFT
 
- TCP_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK
 
- TCP_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT
 
- TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK
 
- TCP_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT
 
- TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK
 
- TCP_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT
 
- TCP_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK
 
- TCP_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT
 
- TCP_UTCL1_CNTL1__REG_INV_TOGGLE_MASK
 
- TCP_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT
 
- TCP_UTCL1_CNTL1__REG_INV_VMID_MASK
 
- TCP_UTCL1_CNTL1__REG_INV_VMID__SHIFT
 
- TCP_UTCL1_CNTL1__RESP_FAULT_MODE_MASK
 
- TCP_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT
 
- TCP_UTCL1_CNTL1__RESP_MODE_MASK
 
- TCP_UTCL1_CNTL1__RESP_MODE__SHIFT
 
- TCP_UTCL1_CNTL2__ANY_LINE_VALID_MASK
 
- TCP_UTCL1_CNTL2__ANY_LINE_VALID__SHIFT
 
- TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K_MASK
 
- TCP_UTCL1_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT
 
- TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK
 
- TCP_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT
 
- TCP_UTCL1_CNTL2__FORCE_SNOOP_MASK
 
- TCP_UTCL1_CNTL2__FORCE_SNOOP__SHIFT
 
- TCP_UTCL1_CNTL2__GPUVM_INV_MODE_MASK
 
- TCP_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT
 
- TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK
 
- TCP_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT
 
- TCP_UTCL1_CNTL2__SPARE_MASK
 
- TCP_UTCL1_CNTL2__SPARE__SHIFT
 
- TCP_UTCL1_STATUS__FAULT_DETECTED_MASK
 
- TCP_UTCL1_STATUS__FAULT_DETECTED__SHIFT
 
- TCP_UTCL1_STATUS__PRT_DETECTED_MASK
 
- TCP_UTCL1_STATUS__PRT_DETECTED__SHIFT
 
- TCP_UTCL1_STATUS__RETRY_DETECTED_MASK
 
- TCP_UTCL1_STATUS__RETRY_DETECTED__SHIFT
 
- TCP_V4_FLOW
 
- TCP_V6_FLOW
 
- TCP_WATCH0_ADDR_H
 
- TCP_WATCH0_ADDR_H__ADDR_MASK
 
- TCP_WATCH0_ADDR_H__ADDR__SHIFT
 
- TCP_WATCH0_ADDR_L
 
- TCP_WATCH0_ADDR_L__ADDR_MASK
 
- TCP_WATCH0_ADDR_L__ADDR__SHIFT
 
- TCP_WATCH0_CNTL
 
- TCP_WATCH0_CNTL__ATC_MASK
 
- TCP_WATCH0_CNTL__ATC__SHIFT
 
- TCP_WATCH0_CNTL__MASK_MASK
 
- TCP_WATCH0_CNTL__MASK__SHIFT
 
- TCP_WATCH0_CNTL__MODE_MASK
 
- TCP_WATCH0_CNTL__MODE__SHIFT
 
- TCP_WATCH0_CNTL__VALID_MASK
 
- TCP_WATCH0_CNTL__VALID__SHIFT
 
- TCP_WATCH0_CNTL__VMID_MASK
 
- TCP_WATCH0_CNTL__VMID__SHIFT
 
- TCP_WATCH1_ADDR_H
 
- TCP_WATCH1_ADDR_H__ADDR_MASK
 
- TCP_WATCH1_ADDR_H__ADDR__SHIFT
 
- TCP_WATCH1_ADDR_L
 
- TCP_WATCH1_ADDR_L__ADDR_MASK
 
- TCP_WATCH1_ADDR_L__ADDR__SHIFT
 
- TCP_WATCH1_CNTL
 
- TCP_WATCH1_CNTL__ATC_MASK
 
- TCP_WATCH1_CNTL__ATC__SHIFT
 
- TCP_WATCH1_CNTL__MASK_MASK
 
- TCP_WATCH1_CNTL__MASK__SHIFT
 
- TCP_WATCH1_CNTL__MODE_MASK
 
- TCP_WATCH1_CNTL__MODE__SHIFT
 
- TCP_WATCH1_CNTL__VALID_MASK
 
- TCP_WATCH1_CNTL__VALID__SHIFT
 
- TCP_WATCH1_CNTL__VMID_MASK
 
- TCP_WATCH1_CNTL__VMID__SHIFT
 
- TCP_WATCH2_ADDR_H
 
- TCP_WATCH2_ADDR_H__ADDR_MASK
 
- TCP_WATCH2_ADDR_H__ADDR__SHIFT
 
- TCP_WATCH2_ADDR_L
 
- TCP_WATCH2_ADDR_L__ADDR_MASK
 
- TCP_WATCH2_ADDR_L__ADDR__SHIFT
 
- TCP_WATCH2_CNTL
 
- TCP_WATCH2_CNTL__ATC_MASK
 
- TCP_WATCH2_CNTL__ATC__SHIFT
 
- TCP_WATCH2_CNTL__MASK_MASK
 
- TCP_WATCH2_CNTL__MASK__SHIFT
 
- TCP_WATCH2_CNTL__MODE_MASK
 
- TCP_WATCH2_CNTL__MODE__SHIFT
 
- TCP_WATCH2_CNTL__VALID_MASK
 
- TCP_WATCH2_CNTL__VALID__SHIFT
 
- TCP_WATCH2_CNTL__VMID_MASK
 
- TCP_WATCH2_CNTL__VMID__SHIFT
 
- TCP_WATCH3_ADDR_H
 
- TCP_WATCH3_ADDR_H__ADDR_MASK
 
- TCP_WATCH3_ADDR_H__ADDR__SHIFT
 
- TCP_WATCH3_ADDR_L
 
- TCP_WATCH3_ADDR_L__ADDR_MASK
 
- TCP_WATCH3_ADDR_L__ADDR__SHIFT
 
- TCP_WATCH3_CNTL
 
- TCP_WATCH3_CNTL__ATC_MASK
 
- TCP_WATCH3_CNTL__ATC__SHIFT
 
- TCP_WATCH3_CNTL__MASK_MASK
 
- TCP_WATCH3_CNTL__MASK__SHIFT
 
- TCP_WATCH3_CNTL__MODE_MASK
 
- TCP_WATCH3_CNTL__MODE__SHIFT
 
- TCP_WATCH3_CNTL__VALID_MASK
 
- TCP_WATCH3_CNTL__VALID__SHIFT
 
- TCP_WATCH3_CNTL__VMID_MASK
 
- TCP_WATCH3_CNTL__VMID__SHIFT
 
- TCP_WATCH_ADDR_H_BITS
 
- TCP_WATCH_ADDR_L_BITS
 
- TCP_WATCH_CNTL_BITS
 
- TCP_WATCH_MODES
 
- TCP_WATCH_MODE_ALL
 
- TCP_WATCH_MODE_ATOMIC
 
- TCP_WATCH_MODE_NONREAD
 
- TCP_WATCH_MODE_READ
 
- TCP_WESTWOOD_INIT_RTT
 
- TCP_WESTWOOD_RTT_MIN
 
- TCP_WINDOW_CLAMP
 
- TCP_WRITE_TIMER_DEFERRED
 
- TCP_YEAH_ALPHA
 
- TCP_YEAH_DELTA
 
- TCP_YEAH_EPSILON
 
- TCP_YEAH_GAMMA
 
- TCP_YEAH_PHY
 
- TCP_YEAH_RHO
 
- TCP_YEAH_ZETA
 
- TCP_ZEROCOPY_RECEIVE
 
- TCQ_ED_ADR
 
- TCQ_F_BUILTIN
 
- TCQ_F_CAN_BYPASS
 
- TCQ_F_CPUSTATS
 
- TCQ_F_INGRESS
 
- TCQ_F_INVISIBLE
 
- TCQ_F_MQROOT
 
- TCQ_F_NOLOCK
 
- TCQ_F_NOPARENT
 
- TCQ_F_OFFLOADED
 
- TCQ_F_ONETXQUEUE
 
- TCQ_F_WARN_NONWC
 
- TCQ_MIN_PRIO_BANDS
 
- TCQ_NOT_EMPTY
 
- TCQ_PLUG_BUFFER
 
- TCQ_PLUG_LIMIT
 
- TCQ_PLUG_RELEASE_INDEFINITE
 
- TCQ_PLUG_RELEASE_ONE
 
- TCQ_PRIO_BANDS
 
- TCQ_RD_PTR
 
- TCQ_ST_ADR
 
- TCQ_WR_PTR
 
- TCR
 
- TCR0
 
- TCR0_AUTO_FIFO
 
- TCR0_CRC
 
- TCR0_DISCONNECT_EN
 
- TCR0_DO_SYNC_NEGO
 
- TCR0_DO_WIDE_NEGO
 
- TCR0_ENABLE_ALT
 
- TCR0_ENABLE_LVDS
 
- TCR0_ENABLE_WIDE
 
- TCR0_IPCK
 
- TCR0_JMBO
 
- TCR0_OFFSET_MASK
 
- TCR0_PERIOD_MASK
 
- TCR0_PIC
 
- TCR0_SYNC_NEGO_DONE
 
- TCR0_TCPCK
 
- TCR0_TIC
 
- TCR0_TX_EMPTY
 
- TCR0_UDPCK
 
- TCR0_VETAG
 
- TCR0_WIDE_NEGO_DONE
 
- TCR1
 
- TCR1_ADDR
 
- TCR2
 
- TCR2_ADDR
 
- TCR2_AS
 
- TCR2_SEP
 
- TCR2_SEP_UPSTREAM
 
- TCRCRC
 
- TCRICV
 
- TCRIT_INT
 
- TCRIT_INT_SOURCE
 
- TCRRCR
 
- TCRTxCP
 
- TCR_A1
 
- TCR_ADDR
 
- TCR_ARE
 
- TCR_ASID16
 
- TCR_ASSERT_CD
 
- TCR_ASSERT_IO
 
- TCR_ASSERT_MSG
 
- TCR_ASSERT_REQ
 
- TCR_AUTOBCNTX
 
- TCR_BASE
 
- TCR_BTS
 
- TCR_CACHE_FLAGS
 
- TCR_CCLR_MASK
 
- TCR_CCLR_NONE
 
- TCR_CCLR_SYNC
 
- TCR_CCLR_TGRA
 
- TCR_CCLR_TGRB
 
- TCR_CCLR_TGRC
 
- TCR_CCLR_TGRD
 
- TCR_CKEG_BOTH
 
- TCR_CKEG_FALLING
 
- TCR_CKEG_MASK
 
- TCR_CKEG_RISING
 
- TCR_CLEAR
 
- TCR_CLEAR_FUJITSU_ERRATUM_010001
 
- TCR_CLKSRCLO
 
- TCR_COLTMC0
 
- TCR_COLTMC1
 
- TCR_CONT
 
- TCR_CONTC
 
- TCR_CPHA
 
- TCR_CPHI
 
- TCR_CPLO
 
- TCR_CPOL
 
- TCR_CRC
 
- TCR_CRC_DIS
 
- TCR_CRC_DIS1
 
- TCR_CRC_DIS2
 
- TCR_CRS_CARE
 
- TCR_DEFAULT
 
- TCR_DIE
 
- TCR_DISCW
 
- TCR_DM
 
- TCR_DS
 
- TCR_EDP
 
- TCR_EL1
 
- TCR_EL2_IRGN0_MASK
 
- TCR_EL2_MASK
 
- TCR_EL2_ORGN0_MASK
 
- TCR_EL2_PS_40B
 
- TCR_EL2_PS_MASK
 
- TCR_EL2_PS_SHIFT
 
- TCR_EL2_RES1
 
- TCR_EL2_SH0_MASK
 
- TCR_EL2_T0SZ_MASK
 
- TCR_EL2_TBI
 
- TCR_EL2_TG0_MASK
 
- TCR_EN
 
- TCR_ENABLE
 
- TCR_ENAMODEHI_CONT
 
- TCR_ENAMODEHI_MASK
 
- TCR_ENAMODEHI_ONCE
 
- TCR_ENAMODELO_CONT
 
- TCR_ENAMODELO_MASK
 
- TCR_ENAMODELO_ONCE
 
- TCR_ENAMODE_DISABLE
 
- TCR_ENAMODE_MASK
 
- TCR_ENAMODE_ONESHOT
 
- TCR_ENAMODE_ONESHOT_MASK
 
- TCR_ENAMODE_PERIODIC
 
- TCR_ENAMODE_PERIODIC_MASK
 
- TCR_EPD0_MASK
 
- TCR_EPD0_SHIFT
 
- TCR_EPD1_MASK
 
- TCR_EPD1_SHIFT
 
- TCR_EPH_LOOP
 
- TCR_EXCECM
 
- TCR_FAKE_IMEM_EN
 
- TCR_FAST_MODE
 
- TCR_FDUPLX
 
- TCR_FIE
 
- TCR_FORCOL
 
- TCR_FP
 
- TCR_FP_MASK
 
- TCR_GET_WP
 
- TCR_HA
 
- TCR_HD
 
- TCR_HS_MODE
 
- TCR_HWPC_TX_EN
 
- TCR_ICV
 
- TCR_INVINPLO
 
- TCR_INVOUTPHI
 
- TCR_INVOUTPLO
 
- TCR_IPS_MASK
 
- TCR_IPS_SHIFT
 
- TCR_IRGN0_MASK
 
- TCR_IRGN0_NC
 
- TCR_IRGN0_SHIFT
 
- TCR_IRGN0_WBWA
 
- TCR_IRGN0_WBnWA
 
- TCR_IRGN0_WT
 
- TCR_IRGN1_MASK
 
- TCR_IRGN1_NC
 
- TCR_IRGN1_SHIFT
 
- TCR_IRGN1_WBWA
 
- TCR_IRGN1_WBnWA
 
- TCR_IRGN1_WT
 
- TCR_IRGN_MASK
 
- TCR_IRGN_NC
 
- TCR_IRGN_WBWA
 
- TCR_IRGN_WBnWA
 
- TCR_IRGN_WT
 
- TCR_KASAN_FLAGS
 
- TCR_KASLR_FLAGS
 
- TCR_LAST_BYTE_SENT
 
- TCR_LB0
 
- TCR_LB1
 
- TCR_LC_CARE
 
- TCR_LE
 
- TCR_LF_EN
 
- TCR_LK
 
- TCR_LOOP
 
- TCR_LRL_OFFSET
 
- TCR_MASTER_READ
 
- TCR_MASTER_WRITE
 
- TCR_MONCSN
 
- TCR_MON_CNS
 
- TCR_MON_CSN
 
- TCR_MXDMA_2048
 
- TCR_MXDMA_OFFSET
 
- TCR_NFD0
 
- TCR_NFD1
 
- TCR_NOCRC
 
- TCR_NORMAL
 
- TCR_OFSET
 
- TCR_ORGN0_MASK
 
- TCR_ORGN0_NC
 
- TCR_ORGN0_SHIFT
 
- TCR_ORGN0_WBWA
 
- TCR_ORGN0_WBnWA
 
- TCR_ORGN0_WT
 
- TCR_ORGN1_MASK
 
- TCR_ORGN1_NC
 
- TCR_ORGN1_SHIFT
 
- TCR_ORGN1_WBWA
 
- TCR_ORGN1_WBnWA
 
- TCR_ORGN1_WT
 
- TCR_ORGN_MASK
 
- TCR_ORGN_NC
 
- TCR_ORGN_WBWA
 
- TCR_ORGN_WBnWA
 
- TCR_ORGN_WT
 
- TCR_PAD_DIS
 
- TCR_PAD_DIS1
 
- TCR_PAD_DIS2
 
- TCR_PAD_EN
 
- TCR_PAD_ENABLE
 
- TCR_PIE
 
- TCR_PQEN
 
- TCR_PWIDHI_MASK
 
- TCR_PWIDLO_MASK
 
- TCR_REG
 
- TCR_RS
 
- TCR_RTFT0
 
- TCR_RTFT1
 
- TCR_RTGOPT
 
- TCR_RTSF
 
- TCR_RXMSK
 
- TCR_SAT
 
- TCR_SH0_INNER
 
- TCR_SH0_MASK
 
- TCR_SH0_SHIFT
 
- TCR_SH1_INNER
 
- TCR_SH1_MASK
 
- TCR_SH1_SHIFT
 
- TCR_SHARED
 
- TCR_SLAVE_ADDR_MASK
 
- TCR_SMP_FLAGS
 
- TCR_SRL_OFFSET
 
- TCR_STANDARD_MODE
 
- TCR_STP
 
- TCR_STP_SQET
 
- TCR_SWFDUP
 
- TCR_SYNCDCFOPT
 
- TCR_T0SZ
 
- TCR_T0SZ_MASK
 
- TCR_T0SZ_OFFSET
 
- TCR_T1SZ
 
- TCR_T1SZ_OFFSET
 
- TCR_TB2BDIS
 
- TCR_TBI0
 
- TCR_TBI1
 
- TCR_TCP_OFDL_EN
 
- TCR_TFI
 
- TCR_TG0_16K
 
- TCR_TG0_4K
 
- TCR_TG0_64K
 
- TCR_TG0_MASK
 
- TCR_TG0_SHIFT
 
- TCR_TG1_16K
 
- TCR_TG1_4K
 
- TCR_TG1_64K
 
- TCR_TG1_MASK
 
- TCR_TG1_SHIFT
 
- TCR_TG_FLAGS
 
- TCR_TIENLO
 
- TCR_TJDIS
 
- TCR_TPSC_CH0_TCLKA
 
- TCR_TPSC_CH0_TCLKB
 
- TCR_TPSC_CH0_TCLKC
 
- TCR_TPSC_CH0_TCLKD
 
- TCR_TPSC_CH1_P256
 
- TCR_TPSC_CH1_TCLKA
 
- TCR_TPSC_CH1_TCLKB
 
- TCR_TPSC_CH1_TCNT2
 
- TCR_TPSC_CH2_P1024
 
- TCR_TPSC_CH2_TCLKA
 
- TCR_TPSC_CH2_TCLKB
 
- TCR_TPSC_CH2_TCLKC
 
- TCR_TPSC_CH34_P1024
 
- TCR_TPSC_CH34_P256
 
- TCR_TPSC_CH34_TCLKA
 
- TCR_TPSC_CH34_TCLKB
 
- TCR_TPSC_CLK1024
 
- TCR_TPSC_CLK16
 
- TCR_TPSC_CLK256
 
- TCR_TPSC_CLK4
 
- TCR_TPSC_CLK64
 
- TCR_TPSC_MASK
 
- TCR_TPSC_P1
 
- TCR_TPSC_P16
 
- TCR_TPSC_P4
 
- TCR_TPSC_P64
 
- TCR_TSFEN
 
- TCR_TSFRST
 
- TCR_TSTATHI
 
- TCR_TSTATLO
 
- TCR_TXMSK
 
- TCR_TXREQ
 
- TCR_TxSZ
 
- TCR_TxSZ_WIDTH
 
- TCR_UNF
 
- TCR_UNIE
 
- TCR_WIE
 
- TCR_WP
 
- TCR_WP_MASK
 
- TCR_WRC
 
- TCR_WRC_MASK
 
- TCS3414_CHANNEL
 
- TCS3414_COMMAND
 
- TCS3414_COMMAND_WORD
 
- TCS3414_CONTROL
 
- TCS3414_CONTROL_ADC_EN
 
- TCS3414_CONTROL_ADC_VALID
 
- TCS3414_CONTROL_POWER
 
- TCS3414_DATA_BLUE
 
- TCS3414_DATA_CLEAR
 
- TCS3414_DATA_GREEN
 
- TCS3414_DATA_RED
 
- TCS3414_DRV_NAME
 
- TCS3414_GAIN
 
- TCS3414_GAIN_MASK
 
- TCS3414_GAIN_SHIFT
 
- TCS3414_ID
 
- TCS3414_INTEG_100MS
 
- TCS3414_INTEG_12MS
 
- TCS3414_INTEG_400MS
 
- TCS3414_INTEG_MASK
 
- TCS3414_TIMING
 
- TCS3472_AIHT
 
- TCS3472_AILT
 
- TCS3472_ATIME
 
- TCS3472_AUTO_INCR
 
- TCS3472_BDATA
 
- TCS3472_CDATA
 
- TCS3472_CHANNEL
 
- TCS3472_COMMAND
 
- TCS3472_CONFIG
 
- TCS3472_CONTROL
 
- TCS3472_CONTROL_AGAIN_MASK
 
- TCS3472_DRV_NAME
 
- TCS3472_ENABLE
 
- TCS3472_ENABLE_AEN
 
- TCS3472_ENABLE_AIEN
 
- TCS3472_ENABLE_PON
 
- TCS3472_GDATA
 
- TCS3472_ID
 
- TCS3472_INTR_CLEAR
 
- TCS3472_PERS
 
- TCS3472_RDATA
 
- TCS3472_SPECIAL_FUNC
 
- TCS3472_STATUS
 
- TCS3472_STATUS_AINT
 
- TCS3472_STATUS_AVALID
 
- TCS3472_WTIME
 
- TCSADRAIN
 
- TCSAFLUSH
 
- TCSANOW
 
- TCSBRK
 
- TCSBRKP
 
- TCSETA
 
- TCSETAF
 
- TCSETAW
 
- TCSETS
 
- TCSETS2
 
- TCSETSF
 
- TCSETSF2
 
- TCSETSW
 
- TCSETSW2
 
- TCSETX
 
- TCSETXF
 
- TCSETXW
 
- TCSH_MASK
 
- TCSOE_MASK
 
- TCSOFF_MASK
 
- TCSR
 
- TCSR0
 
- TCSR1
 
- TCSR_ADM_CRCI_BASE
 
- TCSR_ARHT
 
- TCSR_CAPT
 
- TCSR_ECHODIS
 
- TCSR_ENALL
 
- TCSR_ENIT
 
- TCSR_ENT
 
- TCSR_GENT
 
- TCSR_GLOBAL_CFG0
 
- TCSR_GLOBAL_CFG1
 
- TCSR_LOAD
 
- TCSR_MDT
 
- TCSR_PRESERVE
 
- TCSR_PWMA
 
- TCSR_TINT
 
- TCSR_UDT
 
- TCSR_UNDERWAIT
 
- TCSR_WCSS_CLK_ENABLE
 
- TCSR_WCSS_CLK_MASK
 
- TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK
 
- TCSTATUS_A
 
- TCSTATUS_A_SHIFT
 
- TCSTATUS_DA
 
- TCSTATUS_DA_SHIFT
 
- TCSTATUS_DT
 
- TCSTATUS_DT_SHIFT
 
- TCSTATUS_IXMT
 
- TCSTATUS_IXMT_SHIFT
 
- TCSTATUS_RNST
 
- TCSTATUS_RNST_SHIFT
 
- TCSTATUS_TASID
 
- TCSTATUS_TDS
 
- TCSTATUS_TDS_SHIFT
 
- TCSTATUS_TKSU
 
- TCSTATUS_TKSU_SHIFT
 
- TCSTATUS_TMX
 
- TCSTATUS_TMX_SHIFT
 
- TCSTATUS_TSST
 
- TCSTATUS_TSST_SHIFT
 
- TCSW_MASK
 
- TCS_AMC_MODE_ENABLE
 
- TCS_AMC_MODE_TRIGGER
 
- TCS_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK
 
- TCS_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT
 
- TCS_CGTT_SCLK_CTRL__ON_DELAY_MASK
 
- TCS_CGTT_SCLK_CTRL__ON_DELAY__SHIFT
 
- TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK
 
- TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT
 
- TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK
 
- TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT
 
- TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK
 
- TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT
 
- TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK
 
- TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT
 
- TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK
 
- TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT
 
- TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK
 
- TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT
 
- TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK
 
- TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT
 
- TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK
 
- TCS_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT
 
- TCS_CTRL__RATE_MASK
 
- TCS_CTRL__RATE__SHIFT
 
- TCS_DF_NODASD_SUPT
 
- TCS_DF_NOSCSI_SUPT
 
- TCS_MASK
 
- TCS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK
 
- TCS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT
 
- TCS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK
 
- TCS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT
 
- TCS_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK
 
- TCS_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT
 
- TCS_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK
 
- TCS_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT
 
- TCS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK
 
- TCS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT
 
- TCS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK
 
- TCS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT
 
- TCS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK
 
- TCS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT
 
- TCS_PERFCOUNTER0_SELECT__PERF_MODE1_MASK
 
- TCS_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT
 
- TCS_PERFCOUNTER0_SELECT__PERF_MODE_MASK
 
- TCS_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT
 
- TCS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK
 
- TCS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT
 
- TCS_PERFCOUNTER0_SELECT__PERF_SEL_MASK
 
- TCS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT
 
- TCS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK
 
- TCS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT
 
- TCS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK
 
- TCS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT
 
- TCS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK
 
- TCS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT
 
- TCS_PERFCOUNTER1_SELECT__PERF_MODE_MASK
 
- TCS_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT
 
- TCS_PERFCOUNTER1_SELECT__PERF_SEL_MASK
 
- TCS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT
 
- TCS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK
 
- TCS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT
 
- TCS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK
 
- TCS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT
 
- TCS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK
 
- TCS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT
 
- TCS_PERFCOUNTER2_SELECT__PERF_MODE_MASK
 
- TCS_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT
 
- TCS_PERFCOUNTER2_SELECT__PERF_SEL_MASK
 
- TCS_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT
 
- TCS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK
 
- TCS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT
 
- TCS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK
 
- TCS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT
 
- TCS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK
 
- TCS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT
 
- TCS_PERFCOUNTER3_SELECT__PERF_MODE_MASK
 
- TCS_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT
 
- TCS_PERFCOUNTER3_SELECT__PERF_SEL_MASK
 
- TCS_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT
 
- TCS_PERF_SEL
 
- TCS_PERF_SEL_ATOMIC
 
- TCS_PERF_SEL_BUSY
 
- TCS_PERF_SEL_CHUB_LEVEL
 
- TCS_PERF_SEL_CHUB_TCS_RET_SEND
 
- TCS_PERF_SEL_CLIENT0_REQ
 
- TCS_PERF_SEL_CLIENT10_REQ
 
- TCS_PERF_SEL_CLIENT11_REQ
 
- TCS_PERF_SEL_CLIENT12_REQ
 
- TCS_PERF_SEL_CLIENT13_REQ
 
- TCS_PERF_SEL_CLIENT14_REQ
 
- TCS_PERF_SEL_CLIENT15_REQ
 
- TCS_PERF_SEL_CLIENT16_REQ
 
- TCS_PERF_SEL_CLIENT17_REQ
 
- TCS_PERF_SEL_CLIENT18_REQ
 
- TCS_PERF_SEL_CLIENT19_REQ
 
- TCS_PERF_SEL_CLIENT1_REQ
 
- TCS_PERF_SEL_CLIENT20_REQ
 
- TCS_PERF_SEL_CLIENT21_REQ
 
- TCS_PERF_SEL_CLIENT22_REQ
 
- TCS_PERF_SEL_CLIENT23_REQ
 
- TCS_PERF_SEL_CLIENT24_REQ
 
- TCS_PERF_SEL_CLIENT25_REQ
 
- TCS_PERF_SEL_CLIENT26_REQ
 
- TCS_PERF_SEL_CLIENT27_REQ
 
- TCS_PERF_SEL_CLIENT28_REQ
 
- TCS_PERF_SEL_CLIENT29_REQ
 
- TCS_PERF_SEL_CLIENT2_REQ
 
- TCS_PERF_SEL_CLIENT30_REQ
 
- TCS_PERF_SEL_CLIENT31_REQ
 
- TCS_PERF_SEL_CLIENT32_REQ
 
- TCS_PERF_SEL_CLIENT33_REQ
 
- TCS_PERF_SEL_CLIENT34_REQ
 
- TCS_PERF_SEL_CLIENT35_REQ
 
- TCS_PERF_SEL_CLIENT36_REQ
 
- TCS_PERF_SEL_CLIENT37_REQ
 
- TCS_PERF_SEL_CLIENT38_REQ
 
- TCS_PERF_SEL_CLIENT39_REQ
 
- TCS_PERF_SEL_CLIENT3_REQ
 
- TCS_PERF_SEL_CLIENT40_REQ
 
- TCS_PERF_SEL_CLIENT41_REQ
 
- TCS_PERF_SEL_CLIENT42_REQ
 
- TCS_PERF_SEL_CLIENT43_REQ
 
- TCS_PERF_SEL_CLIENT44_REQ
 
- TCS_PERF_SEL_CLIENT45_REQ
 
- TCS_PERF_SEL_CLIENT46_REQ
 
- TCS_PERF_SEL_CLIENT47_REQ
 
- TCS_PERF_SEL_CLIENT48_REQ
 
- TCS_PERF_SEL_CLIENT49_REQ
 
- TCS_PERF_SEL_CLIENT4_REQ
 
- TCS_PERF_SEL_CLIENT50_REQ
 
- TCS_PERF_SEL_CLIENT51_REQ
 
- TCS_PERF_SEL_CLIENT52_REQ
 
- TCS_PERF_SEL_CLIENT53_REQ
 
- TCS_PERF_SEL_CLIENT54_REQ
 
- TCS_PERF_SEL_CLIENT55_REQ
 
- TCS_PERF_SEL_CLIENT56_REQ
 
- TCS_PERF_SEL_CLIENT57_REQ
 
- TCS_PERF_SEL_CLIENT58_REQ
 
- TCS_PERF_SEL_CLIENT59_REQ
 
- TCS_PERF_SEL_CLIENT5_REQ
 
- TCS_PERF_SEL_CLIENT60_REQ
 
- TCS_PERF_SEL_CLIENT61_REQ
 
- TCS_PERF_SEL_CLIENT62_REQ
 
- TCS_PERF_SEL_CLIENT63_REQ
 
- TCS_PERF_SEL_CLIENT6_REQ
 
- TCS_PERF_SEL_CLIENT7_REQ
 
- TCS_PERF_SEL_CLIENT8_REQ
 
- TCS_PERF_SEL_CLIENT9_REQ
 
- TCS_PERF_SEL_CYCLE
 
- TCS_PERF_SEL_HOLE_FIFO_FULL
 
- TCS_PERF_SEL_HOLE_LEVEL
 
- TCS_PERF_SEL_IB_STALL
 
- TCS_PERF_SEL_IB_TOTAL_REQUESTS_STALL
 
- TCS_PERF_SEL_NONE
 
- TCS_PERF_SEL_READ
 
- TCS_PERF_SEL_REQ
 
- TCS_PERF_SEL_REQ_CREDIT_STALL
 
- TCS_PERF_SEL_REQ_FIFO_FULL
 
- TCS_PERF_SEL_REQ_NO_SRC_DATA_STALL
 
- TCS_PERF_SEL_REQ_STALL
 
- TCS_PERF_SEL_RETURN_ACK
 
- TCS_PERF_SEL_RETURN_DATA
 
- TCS_PERF_SEL_TCA_LEVEL
 
- TCS_PERF_SEL_TCS_CHUB_REQ_SEND
 
- TCS_PERF_SEL_WRITE
 
- TCS_TYPE_NR
 
- TCTL
 
- TCTL1
 
- TCTL1_ADDR
 
- TCTL2
 
- TCTL2_ADDR
 
- TCTL4
 
- TCTL_ADDR
 
- TCTL_CAP_FE
 
- TCTL_CAP_MASK
 
- TCTL_CAP_RE
 
- TCTL_CLKSOURCE_32KHZ
 
- TCTL_CLKSOURCE_MASK
 
- TCTL_CLKSOURCE_STOP
 
- TCTL_CLKSOURCE_SYSCLK
 
- TCTL_CLKSOURCE_SYSCLK_16
 
- TCTL_CLKSOURCE_TIN
 
- TCTL_FRR
 
- TCTL_IRQEN
 
- TCTL_OM
 
- TCTL_TEN
 
- TCTRL1_ACT_RD_DLY
 
- TCTRL1_ACT_RD_DLY_SHIFT
 
- TCTRL1_ACT_WR_DLY
 
- TCTRL1_ACT_WR_DLY_SHIFT
 
- TCTRL1_AUTORFR_CYCLE
 
- TCTRL1_AUTORFR_CYCLE_SHIFT
 
- TCTRL1_BANK_PRESENT
 
- TCTRL1_BANK_PRESENT_SHIFT
 
- TCTRL1_PC_CYCLE
 
- TCTRL1_PC_CYCLE_SHIFT
 
- TCTRL1_PRECHG_ALL
 
- TCTRL1_PRECHG_ALL_SHIFT
 
- TCTRL1_R
 
- TCTRL1_RD_MORE_RAS_PW_SHIFT
 
- TCTRL1_RD_MORE_RAW_PW
 
- TCTRL1_RD_WAIT
 
- TCTRL1_RD_WAIT_SHIFT
 
- TCTRL1_RFR_ENABLE
 
- TCTRL1_RFR_ENABLE_SHIFT
 
- TCTRL1_RFR_INT
 
- TCTRL1_RFR_INT_SHIFT
 
- TCTRL1_R_SHIFT
 
- TCTRL1_SDRAMCLK_DLY
 
- TCTRL1_SDRAMCLK_DLY_SHIFT
 
- TCTRL1_SDRAMCTL_DLY
 
- TCTRL1_SDRAMCTL_DLY_SHIFT
 
- TCTRL1_SET_MODE_REG
 
- TCTRL1_SET_MODE_REG_SHIFT
 
- TCTRL1_WR_MORE_RAS_PW
 
- TCTRL1_WR_MORE_RAS_PW_SHIFT
 
- TCTRL2_AUTOPRECHG_ENBL
 
- TCTRL2_AUTOPRECHG_ENBL_SHIFT
 
- TCTRL2_R
 
- TCTRL2_RDWR_1_DLY
 
- TCTRL2_RDWR_1_DLY_SHIFT
 
- TCTRL2_RDWR_PI_MORE_DLY
 
- TCTRL2_RDWR_PI_MORE_DLY_SHIFT
 
- TCTRL2_RDWR_RD_PI_MORE_DLY
 
- TCTRL2_RDWR_RD_PI_MORE_DLY_SHIFT
 
- TCTRL2_RDWR_RD_TI_DLY
 
- TCTRL2_RDWR_RD_TI_DLY_SHIFT
 
- TCTRL2_RD_MSEL_DLY
 
- TCTRL2_RD_MSEL_DLY_SHIFT
 
- TCTRL2_R_SHIFT
 
- TCTRL2_SDRAM_MODE_REG_DATA
 
- TCTRL2_SDRAM_MODE_REG_DATA_SHIFT
 
- TCTRL2_WRDATA_THLD
 
- TCTRL2_WRDATA_THLD_SHIFT
 
- TCTRL2_WRWR_1_DLY
 
- TCTRL2_WRWR_1_DLY_SHIFT
 
- TCTRL2_WRWR_PI_MORE_DLY
 
- TCTRL2_WRWR_PI_MORE_DLY_SHIFT
 
- TCTRL2_WR_MSEL_DLY
 
- TCTRL2_WR_MSEL_DLY_SHIFT
 
- TCTRL3_ACT_RD_DLY
 
- TCTRL3_ACT_RD_DLY_SHIFT
 
- TCTRL3_ACT_WR_DLY
 
- TCTRL3_ACT_WR_DLY_SHIFT
 
- TCTRL3_AUTO_RFR_CYCLE
 
- TCTRL3_AUTO_RFR_CYCLE_SHIFT
 
- TCTRL3_BANK_PRESENT
 
- TCTRL3_BANK_PRESENT_SHIFT
 
- TCTRL3_PC_CYCLE
 
- TCTRL3_PC_CYCLE_SHIFT
 
- TCTRL3_PRECHG_ALL
 
- TCTRL3_PRECHG_ALL_SHIFT
 
- TCTRL3_R
 
- TCTRL3_RD_MORE_RAW_PW
 
- TCTRL3_RD_MORE_RAW_PW_SHIFT
 
- TCTRL3_RD_WAIT
 
- TCTRL3_RD_WAIT_SHIFT
 
- TCTRL3_RFR_ENABLE
 
- TCTRL3_RFR_ENABLE_SHIFT
 
- TCTRL3_RFR_INT
 
- TCTRL3_RFR_INT_SHIFT
 
- TCTRL3_R_SHIFT
 
- TCTRL3_SDRAM_CLK_DLY
 
- TCTRL3_SDRAM_CLK_DLY_SHIFT
 
- TCTRL3_SDRAM_CTL_DLY
 
- TCTRL3_SDRAM_CTL_DLY_SHIFT
 
- TCTRL3_SET_MODE_REG
 
- TCTRL3_SET_MODE_REG_SHIFT
 
- TCTRL3_WR_MORE_RAW_PW
 
- TCTRL3_WR_MORE_RAW_PW_SHIFT
 
- TCTRL4_AUTO_PRECHG_ENBL
 
- TCTRL4_AUTO_PRECHG_ENBL_SHIFT
 
- TCTRL4_R
 
- TCTRL4_RDWR_RD_PI_MORE_DLY
 
- TCTRL4_RDWR_RD_PI_MORE_DLY_SHIFT
 
- TCTRL4_RDWR_RD_RI_DLY
 
- TCTRL4_RDWR_RD_RI_DLY_SHIFT
 
- TCTRL4_RD_MSEL_DLY
 
- TCTRL4_RD_MSEL_DLY_SHIFT
 
- TCTRL4_RD_WR_PI_MORE_DLY
 
- TCTRL4_RD_WR_PI_MORE_DLY_SHIFT
 
- TCTRL4_RD_WR_TI_DLY
 
- TCTRL4_RD_WR_TI_DLY_SHIFT
 
- TCTRL4_R_SHIFT
 
- TCTRL4_SDRAM_MODE_REG_DATA
 
- TCTRL4_SDRAM_MODE_REG_DATA_SHIFT
 
- TCTRL4_WRDATA_THLD
 
- TCTRL4_WRDATA_THLD_SHIFT
 
- TCTRL4_WR_MSEL_DLY
 
- TCTRL4_WR_MSEL_DLY_SHIFT
 
- TCTRL4_WR_WR_PI_MORE_DLY
 
- TCTRL4_WR_WR_PI_MORE_DLY_SHIFT
 
- TCTRL4_WR_WR_TI_DLY
 
- TCTRL4_WR_WR_TI_DLY_SHIFT
 
- TCTRL_GRESET_LEN
 
- TCTRL_GTS
 
- TCTRL_INIT_CSUM
 
- TCTRL_IPCSEN
 
- TCTRL_PSTRB_REPLAY_COUNTER_SHIFT
 
- TCTRL_PSTRB_REPLAY_DELAY
 
- TCTRL_RFCPAUSE
 
- TCTRL_TFCPAUSE
 
- TCTRL_THDF
 
- TCTRL_TTSE
 
- TCTRL_TUCSEN
 
- TCTRL_TXSCHED_INIT
 
- TCTRL_TXSCHED_MASK
 
- TCTRL_TXSCHED_PRIO
 
- TCTRL_TXSCHED_WRRS
 
- TCTRL_VLINS
 
- TCTR_LOW
 
- TCTRxCP
 
- TCTS
 
- TCT_ABR
 
- TCT_CBR
 
- TCT_FLAG_UBR
 
- TCT_HALT
 
- TCT_IDLE
 
- TCT_LMCR
 
- TCT_RR
 
- TCT_SCD_MASK
 
- TCT_TSIF
 
- TCT_TYPE
 
- TCT_UBR
 
- TCT_VBR
 
- TCU_CHANNEL_STRIDE
 
- TCU_CLK_COUNT
 
- TCU_CLK_OST
 
- TCU_CLK_TIMER0
 
- TCU_CLK_TIMER1
 
- TCU_CLK_TIMER2
 
- TCU_CLK_TIMER3
 
- TCU_CLK_TIMER4
 
- TCU_CLK_TIMER5
 
- TCU_CLK_TIMER6
 
- TCU_CLK_TIMER7
 
- TCU_CLK_WDT
 
- TCU_MBOX_BYTE
 
- TCU_MBOX_BYTE_V
 
- TCU_MBOX_NUM_BYTES
 
- TCU_MBOX_NUM_BYTES_V
 
- TCU_PARENT_EXT
 
- TCU_PARENT_PCLK
 
- TCU_PARENT_RTC
 
- TCU_REG_OST_CNTH
 
- TCU_REG_OST_CNTHBUF
 
- TCU_REG_OST_CNTL
 
- TCU_REG_OST_DR
 
- TCU_REG_OST_TCSR
 
- TCU_REG_TCNT0
 
- TCU_REG_TCNTc
 
- TCU_REG_TCSR0
 
- TCU_REG_TCSRc
 
- TCU_REG_TDFR0
 
- TCU_REG_TDFRc
 
- TCU_REG_TDHR0
 
- TCU_REG_TDHRc
 
- TCU_REG_TECR
 
- TCU_REG_TER
 
- TCU_REG_TESR
 
- TCU_REG_TFCR
 
- TCU_REG_TFR
 
- TCU_REG_TFSR
 
- TCU_REG_TMCR
 
- TCU_REG_TMR
 
- TCU_REG_TMSR
 
- TCU_REG_TSCR
 
- TCU_REG_TSR
 
- TCU_REG_TSSR
 
- TCU_REG_TSTCR
 
- TCU_REG_TSTR
 
- TCU_REG_TSTSR
 
- TCU_REG_WDT_TCER
 
- TCU_REG_WDT_TCNT
 
- TCU_REG_WDT_TCSR
 
- TCU_REG_WDT_TDR
 
- TCU_TCSR_PARENT_CLOCK_MASK
 
- TCU_TCSR_PRESCALE_LSB
 
- TCU_TCSR_PRESCALE_MASK
 
- TCU_TCSR_PWM_EN
 
- TCU_TCSR_PWM_INITL_HIGH
 
- TCU_TCSR_PWM_SD
 
- TCU_TCSR_RESERVED_BITS
 
- TCU_WDT_TCER_TCEN
 
- TCVR_BBCLOCK
 
- TCVR_BBDATA
 
- TCVR_BBOENAB
 
- TCVR_CFG
 
- TCVR_FAILURE
 
- TCVR_FRAME
 
- TCVR_IMASK
 
- TCVR_MPAL
 
- TCVR_PAL_EXTLBACK
 
- TCVR_PAL_LTENABLE
 
- TCVR_PAL_LTSTATUS
 
- TCVR_PAL_MSENSE
 
- TCVR_PAL_SERIAL
 
- TCVR_READ_TRIES
 
- TCVR_REG_SIZE
 
- TCVR_RESET_TRIES
 
- TCVR_SMACHINE
 
- TCVR_STATUS
 
- TCVR_TPAL
 
- TCVR_UNISOLATE_TRIES
 
- TCVR_WRITE_TRIES
 
- TCV_CFG_BENABLE
 
- TCV_CFG_MDIO0
 
- TCV_CFG_MDIO1
 
- TCV_CFG_PDADDR
 
- TCV_CFG_PENABLE
 
- TCV_CFG_PREGADDR
 
- TCV_CFG_PSELECT
 
- TCV_PADDR_ETX
 
- TCV_PADDR_ITX
 
- TCV_STAT_BASIC
 
- TCV_STAT_NORMAL
 
- TCWAW_AND_ADDR_2_DATA
 
- TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA
 
- TCWAW_AND_ADDR_2_DATA__TCWAW
 
- TCW_FLAGS_GET_TIDAW_FORMAT
 
- TCW_FLAGS_INPUT_TIDA
 
- TCW_FLAGS_OUTPUT_TIDA
 
- TCW_FLAGS_TCCB_TIDA
 
- TCW_FLAGS_TIDAW_FORMAT
 
- TCW_FORMAT_DEFAULT
 
- TCW_TIDAW_FORMAT_DEFAULT
 
- TCW_WHITENING_SIZE
 
- TCX0_CLK_RATE
 
- TCXONC
 
- TCXO_CLK_DETECT_REG
 
- TCXO_DET_FAILED
 
- TCXO_ILOAD_INT_REG
 
- TCX_ALT
 
- TCX_BTREGS
 
- TCX_CONTROLPLANE
 
- TCX_DHC
 
- TCX_FLAG_BLANKED
 
- TCX_MMAP_ENTRIES
 
- TCX_RAM24BIT
 
- TCX_RAM8BIT
 
- TCX_SYNC
 
- TCX_TEC
 
- TCX_THC
 
- TCX_THC_MISC_CURS_RES
 
- TCX_THC_MISC_HSYNC_DIS
 
- TCX_THC_MISC_INIT
 
- TCX_THC_MISC_INT
 
- TCX_THC_MISC_INT_ENAB
 
- TCX_THC_MISC_RESET
 
- TCX_THC_MISC_REV_MASK
 
- TCX_THC_MISC_REV_SHIFT
 
- TCX_THC_MISC_SYNC
 
- TCX_THC_MISC_SYNC_ENAB
 
- TCX_THC_MISC_VIDEO
 
- TCX_THC_MISC_VSYNC
 
- TCX_THC_MISC_VSYNC_DIS
 
- TCX_THC_REV_MINREV_MASK
 
- TCX_THC_REV_MINREV_SHIFT
 
- TCX_THC_REV_REV_MASK
 
- TCX_THC_REV_REV_SHIFT
 
- TCX_UNK2
 
- TCX_UNK3
 
- TCX_UNK4
 
- TCX_UNK6
 
- TCX_UNK7
 
- TCYC17
 
- TC_ACT_CONSUMED
 
- TC_ACT_EXT_CMP
 
- TC_ACT_EXT_OPCODE
 
- TC_ACT_EXT_OPCODE_MAX
 
- TC_ACT_EXT_VAL_MASK
 
- TC_ACT_GOTO_CHAIN
 
- TC_ACT_JUMP
 
- TC_ACT_OK
 
- TC_ACT_PIPE
 
- TC_ACT_QUEUED
 
- TC_ACT_RECLASSIFY
 
- TC_ACT_REDIRECT
 
- TC_ACT_REPEAT
 
- TC_ACT_SHOT
 
- TC_ACT_STOLEN
 
- TC_ACT_TRAP
 
- TC_ACT_UNSPEC
 
- TC_ACT_VALUE_MAX
 
- TC_AEN_DISABLE
 
- TC_ATA_RESP
 
- TC_ATA_R_ERR_RECV
 
- TC_BITMASK
 
- TC_BUSY
 
- TC_CAKE_MAX_TINS
 
- TC_CBQ_DEF_EWMA
 
- TC_CBQ_MAXLEVEL
 
- TC_CBQ_MAXPRIO
 
- TC_CBQ_OVL_CLASSIC
 
- TC_CBQ_OVL_DELAY
 
- TC_CBQ_OVL_DROP
 
- TC_CBQ_OVL_LOWPRIO
 
- TC_CBQ_OVL_RCLASSIC
 
- TC_CFG_L1_LOAD_POLICY0
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK
 
- TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT
 
- TC_CFG_L1_LOAD_POLICY1
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK
 
- TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT
 
- TC_CFG_L1_STORE_POLICY
 
- TC_CFG_L1_STORE_POLICY__POLICY_0_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_10_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_11_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_12_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_13_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_14_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_15_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_16_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_17_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_18_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_19_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_1_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_20_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_21_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_22_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_23_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_24_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_25_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_26_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_27_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_28_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_29_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_2_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_30_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_31_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_3_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_4_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_5_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_6_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_7_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_8_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT
 
- TC_CFG_L1_STORE_POLICY__POLICY_9_MASK
 
- TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT
 
- TC_CFG_L1_VOLATILE
 
- TC_CFG_L1_VOLATILE__VOL_MASK
 
- TC_CFG_L1_VOLATILE__VOL__SHIFT
 
- TC_CFG_L2_ATOMIC_POLICY
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK
 
- TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT
 
- TC_CFG_L2_LOAD_POLICY0
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK
 
- TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT
 
- TC_CFG_L2_LOAD_POLICY1
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK
 
- TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT
 
- TC_CFG_L2_STORE_POLICY0
 
- TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK
 
- TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT
 
- TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK
 
- TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT
 
- TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK
 
- TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT
 
- TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK
 
- TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT
 
- TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK
 
- TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT
 
- TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK
 
- TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT
 
- TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK
 
- TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT
 
- TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK
 
- TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT
 
- TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK
 
- TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT
 
- TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK
 
- TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT
 
- TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK
 
- TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT
 
- TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK
 
- TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT
 
- TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK
 
- TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT
 
- TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK
 
- TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT
 
- TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK
 
- TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT
 
- TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK
 
- TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT
 
- TC_CFG_L2_STORE_POLICY1
 
- TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK
 
- TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT
 
- TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK
 
- TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT
 
- TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK
 
- TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT
 
- TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK
 
- TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT
 
- TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK
 
- TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT
 
- TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK
 
- TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT
 
- TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK
 
- TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT
 
- TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK
 
- TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT
 
- TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK
 
- TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT
 
- TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK
 
- TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT
 
- TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK
 
- TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT
 
- TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK
 
- TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT
 
- TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK
 
- TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT
 
- TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK
 
- TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT
 
- TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK
 
- TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT
 
- TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK
 
- TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT
 
- TC_CFG_L2_VOLATILE
 
- TC_CFG_L2_VOLATILE__VOL_MASK
 
- TC_CFG_L2_VOLATILE__VOL__SHIFT
 
- TC_CHUB_REQ_CREDITS
 
- TC_CHUB_REQ_CREDITS_ENUM
 
- TC_CLOCK_GATE_OVERRIDE
 
- TC_CLSBPF_OFFLOAD
 
- TC_CLSBPF_STATS
 
- TC_CLSMATCHALL_DESTROY
 
- TC_CLSMATCHALL_REPLACE
 
- TC_CLSMATCHALL_STATS
 
- TC_CLSU32_DELETE_HNODE
 
- TC_CLSU32_DELETE_KNODE
 
- TC_CLSU32_NEW_HNODE
 
- TC_CLSU32_NEW_KNODE
 
- TC_CLSU32_REPLACE_HNODE
 
- TC_CLSU32_REPLACE_KNODE
 
- TC_CNTL
 
- TC_CONTROL_PHY
 
- TC_COOKIE_MAX_SIZE
 
- TC_CSMI
 
- TC_DEFAULT
 
- TC_EA_CID
 
- TC_EA_CID_CPF
 
- TC_EA_CID_CPG
 
- TC_EA_CID_DCC
 
- TC_EA_CID_FMASK
 
- TC_EA_CID_HTILE
 
- TC_EA_CID_IA
 
- TC_EA_CID_MISC
 
- TC_EA_CID_PA
 
- TC_EA_CID_RT
 
- TC_EA_CID_SQC
 
- TC_EA_CID_STENCIL
 
- TC_EA_CID_TCP
 
- TC_EA_CID_TCPMETA
 
- TC_EA_CID_UTCL2_TPI
 
- TC_EA_CID_WD
 
- TC_EA_CID_Z
 
- TC_EFT_DISABLE
 
- TC_EFT_ENABLE
 
- TC_EM_TEXT_ALGOSIZ
 
- TC_EN
 
- TC_ENDIANISM
 
- TC_ETF_DEADLINE_MODE_ON
 
- TC_ETF_OFFLOAD_ON
 
- TC_ETF_SKIP_SOCK_CHECK
 
- TC_EWRITE
 
- TC_EWRITEA
 
- TC_FBEN
 
- TC_FCE_DEFAULT_RX_SIZE
 
- TC_FCE_DEFAULT_TX_SIZE
 
- TC_FCE_DISABLE
 
- TC_FCE_DISABLE_TRACE
 
- TC_FCE_ENABLE
 
- TC_FCE_OPTIONS
 
- TC_FIRM_TYPE
 
- TC_FIRM_VER
 
- TC_FLAGS
 
- TC_FLAGS_AAL5
 
- TC_FLAGS_CAL0
 
- TC_FLAGS_CAL1
 
- TC_FLAGS_CAL2
 
- TC_FLAGS_CAL3
 
- TC_FLAGS_PACKET
 
- TC_FLAGS_STREAMING
 
- TC_FLAGS_TRANSPARENT_CELL
 
- TC_FLAGS_TRANSPARENT_PAYLOAD
 
- TC_FLAGS_TYPE_ABR
 
- TC_FLAGS_TYPE_CBR
 
- TC_FLAGS_TYPE_UBR
 
- TC_FLAGS_TYPE_VBR
 
- TC_G210_20BIT
 
- TC_G210_40BIT
 
- TC_G210_INV
 
- TC_GATED
 
- TC_GPIO_BIT
 
- TC_GRED_DESTROY
 
- TC_GRED_REPLACE
 
- TC_GRED_STATS
 
- TC_HIGH
 
- TC_HTB_MAXDEPTH
 
- TC_HTB_NUMPRIO
 
- TC_HTB_PROTOVER
 
- TC_H_CLSACT
 
- TC_H_INGRESS
 
- TC_H_MAJ
 
- TC_H_MAJ_MASK
 
- TC_H_MAKE
 
- TC_H_MIN
 
- TC_H_MIN_EGRESS
 
- TC_H_MIN_INGRESS
 
- TC_H_MIN_MASK
 
- TC_H_MIN_PRIORITY
 
- TC_H_ROOT
 
- TC_H_UNSPEC
 
- TC_IDLE_REQUEST
 
- TC_IDREG
 
- TC_KPD_COLUMNS
 
- TC_KPD_DEBOUNCE_PERIOD
 
- TC_KPD_ROWS
 
- TC_KPD_SETTLE_TIME
 
- TC_L2_SIZE
 
- TC_LINKLAYER_ATM
 
- TC_LINKLAYER_ETHERNET
 
- TC_LINKLAYER_MASK
 
- TC_LINKLAYER_UNAWARE
 
- TC_LINK_ADM_RESP
 
- TC_LIVE_STATE_TBT
 
- TC_LIVE_STATE_TC
 
- TC_LSB
 
- TC_MAX_QUEUE
 
- TC_MICRO_TILE_MODE
 
- TC_MODULE
 
- TC_MQPRIO_F_MAX_RATE
 
- TC_MQPRIO_F_MIN_RATE
 
- TC_MQPRIO_F_MODE
 
- TC_MQPRIO_F_SHAPER
 
- TC_MQPRIO_HW_OFFLOAD_MAX
 
- TC_MQPRIO_HW_OFFLOAD_NONE
 
- TC_MQPRIO_HW_OFFLOAD_TCS
 
- TC_MQPRIO_MODE_CHANNEL
 
- TC_MQPRIO_MODE_DCB
 
- TC_MQPRIO_SHAPER_BW_RATE
 
- TC_MQPRIO_SHAPER_DCB
 
- TC_MQ_CREATE
 
- TC_MQ_DESTROY
 
- TC_MQ_GRAFT
 
- TC_MQ_STATS
 
- TC_MSB
 
- TC_NACKS
 
- TC_NACK_DATA_ERROR
 
- TC_NACK_NO_FAULT
 
- TC_NACK_PAGE_FAULT
 
- TC_NACK_PROTECTION_FAULT
 
- TC_NBLANK
 
- TC_NEWCARD
 
- TC_NO_ERROR
 
- TC_OLDCARD
 
- TC_ONLY
 
- TC_OP
 
- TC_OP_ATOMIC_ADD_32
 
- TC_OP_ATOMIC_ADD_64
 
- TC_OP_ATOMIC_ADD_RTN_32
 
- TC_OP_ATOMIC_ADD_RTN_64
 
- TC_OP_ATOMIC_AND_32
 
- TC_OP_ATOMIC_AND_64
 
- TC_OP_ATOMIC_AND_RTN_32
 
- TC_OP_ATOMIC_AND_RTN_64
 
- TC_OP_ATOMIC_CMPSWAP_32
 
- TC_OP_ATOMIC_CMPSWAP_64
 
- TC_OP_ATOMIC_CMPSWAP_RTN_32
 
- TC_OP_ATOMIC_CMPSWAP_RTN_64
 
- TC_OP_ATOMIC_DEC_32
 
- TC_OP_ATOMIC_DEC_64
 
- TC_OP_ATOMIC_DEC_RTN_32
 
- TC_OP_ATOMIC_DEC_RTN_64
 
- TC_OP_ATOMIC_FCMPSWAP_32
 
- TC_OP_ATOMIC_FCMPSWAP_64
 
- TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32
 
- TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64
 
- TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32
 
- TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64
 
- TC_OP_ATOMIC_FCMPSWAP_RTN_32
 
- TC_OP_ATOMIC_FCMPSWAP_RTN_64
 
- TC_OP_ATOMIC_FMAX_32
 
- TC_OP_ATOMIC_FMAX_64
 
- TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32
 
- TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64
 
- TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32
 
- TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64
 
- TC_OP_ATOMIC_FMAX_RTN_32
 
- TC_OP_ATOMIC_FMAX_RTN_64
 
- TC_OP_ATOMIC_FMIN_32
 
- TC_OP_ATOMIC_FMIN_64
 
- TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32
 
- TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64
 
- TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32
 
- TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64
 
- TC_OP_ATOMIC_FMIN_RTN_32
 
- TC_OP_ATOMIC_FMIN_RTN_64
 
- TC_OP_ATOMIC_INC_32
 
- TC_OP_ATOMIC_INC_64
 
- TC_OP_ATOMIC_INC_RTN_32
 
- TC_OP_ATOMIC_INC_RTN_64
 
- TC_OP_ATOMIC_OR_32
 
- TC_OP_ATOMIC_OR_64
 
- TC_OP_ATOMIC_OR_RTN_32
 
- TC_OP_ATOMIC_OR_RTN_64
 
- TC_OP_ATOMIC_SMAX_32
 
- TC_OP_ATOMIC_SMAX_64
 
- TC_OP_ATOMIC_SMAX_RTN_32
 
- TC_OP_ATOMIC_SMAX_RTN_64
 
- TC_OP_ATOMIC_SMIN_32
 
- TC_OP_ATOMIC_SMIN_64
 
- TC_OP_ATOMIC_SMIN_RTN_32
 
- TC_OP_ATOMIC_SMIN_RTN_64
 
- TC_OP_ATOMIC_SUB_32
 
- TC_OP_ATOMIC_SUB_64
 
- TC_OP_ATOMIC_SUB_RTN_32
 
- TC_OP_ATOMIC_SUB_RTN_64
 
- TC_OP_ATOMIC_SWAP_32
 
- TC_OP_ATOMIC_SWAP_64
 
- TC_OP_ATOMIC_SWAP_RTN_32
 
- TC_OP_ATOMIC_SWAP_RTN_64
 
- TC_OP_ATOMIC_UMAX_32
 
- TC_OP_ATOMIC_UMAX_64
 
- TC_OP_ATOMIC_UMAX_RTN_32
 
- TC_OP_ATOMIC_UMAX_RTN_64
 
- TC_OP_ATOMIC_UMIN_32
 
- TC_OP_ATOMIC_UMIN_64
 
- TC_OP_ATOMIC_UMIN_RTN_32
 
- TC_OP_ATOMIC_UMIN_RTN_64
 
- TC_OP_ATOMIC_XOR_32
 
- TC_OP_ATOMIC_XOR_64
 
- TC_OP_ATOMIC_XOR_RTN_32
 
- TC_OP_ATOMIC_XOR_RTN_64
 
- TC_OP_INVL1L2_VOL
 
- TC_OP_INVL2_NC
 
- TC_OP_INVL2_VOL
 
- TC_OP_INV_METADATA
 
- TC_OP_MASKS
 
- TC_OP_MASK_64
 
- TC_OP_MASK_FLUSH_DENROM
 
- TC_OP_MASK_NO_RTN
 
- TC_OP_NOP_ACK
 
- TC_OP_NOP_RTN0
 
- TC_OP_PROBE_FILTER
 
- TC_OP_READ
 
- TC_OP_RESERVED_FOP_32_0
 
- TC_OP_RESERVED_FOP_32_1
 
- TC_OP_RESERVED_FOP_32_2
 
- TC_OP_RESERVED_FOP_64_0
 
- TC_OP_RESERVED_FOP_64_1
 
- TC_OP_RESERVED_FOP_64_2
 
- TC_OP_RESERVED_FOP_FLUSH_DENORM_32_0
 
- TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1
 
- TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2
 
- TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0
 
- TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1
 
- TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2
 
- TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_0
 
- TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1
 
- TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2
 
- TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0
 
- TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1
 
- TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_2
 
- TC_OP_RESERVED_FOP_RTN_32_0
 
- TC_OP_RESERVED_FOP_RTN_32_1
 
- TC_OP_RESERVED_FOP_RTN_32_2
 
- TC_OP_RESERVED_FOP_RTN_64_0
 
- TC_OP_RESERVED_FOP_RTN_64_1
 
- TC_OP_RESERVED_FOP_RTN_64_2
 
- TC_OP_RESERVED_NON_FLOAT_32_0
 
- TC_OP_RESERVED_NON_FLOAT_32_1
 
- TC_OP_RESERVED_NON_FLOAT_32_2
 
- TC_OP_RESERVED_NON_FLOAT_32_3
 
- TC_OP_RESERVED_NON_FLOAT_32_4
 
- TC_OP_RESERVED_NON_FLOAT_64_0
 
- TC_OP_RESERVED_NON_FLOAT_64_1
 
- TC_OP_RESERVED_NON_FLOAT_64_2
 
- TC_OP_RESERVED_NON_FLOAT_64_3
 
- TC_OP_RESERVED_NON_FLOAT_64_4
 
- TC_OP_RESERVED_NON_FLOAT_RTN_32_0
 
- TC_OP_RESERVED_NON_FLOAT_RTN_32_1
 
- TC_OP_RESERVED_NON_FLOAT_RTN_32_2
 
- TC_OP_RESERVED_NON_FLOAT_RTN_32_3
 
- TC_OP_RESERVED_NON_FLOAT_RTN_32_4
 
- TC_OP_RESERVED_NON_FLOAT_RTN_64_0
 
- TC_OP_RESERVED_NON_FLOAT_RTN_64_1
 
- TC_OP_RESERVED_NON_FLOAT_RTN_64_2
 
- TC_OP_RESERVED_NON_FLOAT_RTN_64_3
 
- TC_OP_RESERVED_NON_FLOAT_RTN_64_4
 
- TC_OP_WBINVL1
 
- TC_OP_WBINVL1_SD
 
- TC_OP_WBINVL1_VOL
 
- TC_OP_WBINVL2
 
- TC_OP_WBINVL2_NC
 
- TC_OP_WBINVL2_SD
 
- TC_OP_WBL2_NC
 
- TC_OP_WBL2_VOL
 
- TC_OP_WBL2_WC
 
- TC_OP_WRITE
 
- TC_OVERRUN
 
- TC_PARTIAL_SG_LIST
 
- TC_PATTERN0
 
- TC_PATTERN1
 
- TC_PATTERN2
 
- TC_PATTERN3
 
- TC_POLICE_OK
 
- TC_POLICE_PIPE
 
- TC_POLICE_RECLASSIFY
 
- TC_POLICE_SHOT
 
- TC_POLICE_UNSPEC
 
- TC_PORT_DP_ALT
 
- TC_PORT_LEGACY
 
- TC_PORT_TBT_ALT
 
- TC_PRIO_BESTEFFORT
 
- TC_PRIO_BULK
 
- TC_PRIO_CONTROL
 
- TC_PRIO_DESTROY
 
- TC_PRIO_FILLER
 
- TC_PRIO_GRAFT
 
- TC_PRIO_INTERACTIVE
 
- TC_PRIO_INTERACTIVE_BULK
 
- TC_PRIO_MAX
 
- TC_PRIO_REPLACE
 
- TC_PRIO_STATS
 
- TC_PRR
 
- TC_QOPT_BITMASK
 
- TC_QOPT_MAX_QUEUE
 
- TC_RDBUF
 
- TC_READMOD
 
- TC_RED_ADAPTATIVE
 
- TC_RED_DESTROY
 
- TC_RED_ECN
 
- TC_RED_GRAFT
 
- TC_RED_HARDDROP
 
- TC_RED_REPLACE
 
- TC_RED_STATS
 
- TC_RED_XSTATS
 
- TC_REN
 
- TC_REQ
 
- TC_REQ_SET
 
- TC_RESUME
 
- TC_ROM_OBJECTS
 
- TC_ROM_SIZE
 
- TC_ROM_STRIDE
 
- TC_ROM_WIDTH
 
- TC_ROOT_GRAFT
 
- TC_RTAB_SIZE
 
- TC_RUNNING
 
- TC_SETUP_BLOCK
 
- TC_SETUP_CLSBPF
 
- TC_SETUP_CLSFLOWER
 
- TC_SETUP_CLSMATCHALL
 
- TC_SETUP_CLSU32
 
- TC_SETUP_QDISC_CBS
 
- TC_SETUP_QDISC_ETF
 
- TC_SETUP_QDISC_GRED
 
- TC_SETUP_QDISC_MQ
 
- TC_SETUP_QDISC_MQPRIO
 
- TC_SETUP_QDISC_PRIO
 
- TC_SETUP_QDISC_RED
 
- TC_SETUP_QDISC_TAPRIO
 
- TC_SETUP_ROOT_QDISC
 
- TC_SKB_EXT
 
- TC_SLOT_SIZE
 
- TC_SSP_RESP
 
- TC_STATE_DYNAMIC
 
- TC_STATE_INUSE
 
- TC_STATE_RUNNING
 
- TC_STATE_UNUSED
 
- TC_TAPRIO_CMD_SET_AND_HOLD
 
- TC_TAPRIO_CMD_SET_AND_RELEASE
 
- TC_TAPRIO_CMD_SET_GATES
 
- TC_TASK_CLEARED
 
- TC_TIMEOUT1
 
- TC_TIMEOUT2
 
- TC_TIMEOUT3
 
- TC_U32_EAT
 
- TC_U32_HASH
 
- TC_U32_HTID
 
- TC_U32_KEY
 
- TC_U32_MAXDEPTH
 
- TC_U32_NODE
 
- TC_U32_OFFSET
 
- TC_U32_ROOT
 
- TC_U32_TERMINAL
 
- TC_U32_UNSPEC
 
- TC_U32_USERHTID
 
- TC_U32_VAROFFSET
 
- TC_UNDERRUN
 
- TC_VENDOR
 
- TC_WAITING
 
- TC_WEN
 
- TC_WRITE
 
- TC_WRITESF
 
- TC_YIELDING
 
- TCmd_ClearEofEom
 
- TCmd_ClearTxCRC
 
- TCmd_DisableDleInsertion
 
- TCmd_EnableDleInsertion
 
- TCmd_Null
 
- TCmd_SelectTicrIntLevel
 
- TCmd_SelectTicrTtsaData
 
- TCmd_SelectTicrTxFifostatus
 
- TCmd_SelectTicrdma_level
 
- TCmd_SendAbort
 
- TCmd_SendFrame
 
- TCmd_SetEofEom
 
- TD0
 
- TD0_
 
- TD0_IP_CS
 
- TD0_MSS_SHIFT
 
- TD0_TCP_CS
 
- TD0_UDP_CS
 
- TD1
 
- TD1_
 
- TD1_GTSENV4
 
- TD1_GTSENV6
 
- TD1_IPv4_CS
 
- TD1_IPv6_CS
 
- TD1_MSS_SHIFT
 
- TD1_TCP_CS
 
- TD1_UDP_CS
 
- TD2
 
- TD2_
 
- TD3
 
- TD3_
 
- TD41
 
- TD42
 
- TD43
 
- TD44
 
- TDA10023_OUTPUT_MODE_PARALLEL_A
 
- TDA10023_OUTPUT_MODE_PARALLEL_B
 
- TDA10023_OUTPUT_MODE_PARALLEL_C
 
- TDA10023_OUTPUT_MODE_SERIAL
 
- TDA1002x_H
 
- TDA10045H_CODE_IN
 
- TDA10045H_CONFPLL_M_LSB
 
- TDA10045H_CONFPLL_M_MSB
 
- TDA10045H_CONFPLL_N
 
- TDA10045H_CONFPLL_P
 
- TDA10045H_FWPAGE
 
- TDA10045H_IOFFSET
 
- TDA10045H_MUXOUT
 
- TDA10045H_S_AGC
 
- TDA10045H_UNSURW_LSB
 
- TDA10045H_UNSURW_MSB
 
- TDA10045H_WREF_LSB
 
- TDA10045H_WREF_MID
 
- TDA10045H_WREF_MSB
 
- TDA10045_DEFAULT_FIRMWARE
 
- TDA10046H_AGC_CONF
 
- TDA10046H_AGC_GAINS
 
- TDA10046H_AGC_IF_LEVEL
 
- TDA10046H_AGC_IF_MAX
 
- TDA10046H_AGC_IF_MIN
 
- TDA10046H_AGC_RENORM
 
- TDA10046H_AGC_THR
 
- TDA10046H_AGC_TUN_LEVEL
 
- TDA10046H_AGC_TUN_MAX
 
- TDA10046H_AGC_TUN_MIN
 
- TDA10046H_CODE_CPT
 
- TDA10046H_CODE_IN
 
- TDA10046H_CONFPLL1
 
- TDA10046H_CONFPLL2
 
- TDA10046H_CONFPLL3
 
- TDA10046H_CONF_POLARITY
 
- TDA10046H_CONF_TRISTATE1
 
- TDA10046H_CONF_TRISTATE2
 
- TDA10046H_CVBER_CTRL
 
- TDA10046H_FREQ_OFFSET
 
- TDA10046H_FREQ_PHY2_LSB
 
- TDA10046H_FREQ_PHY2_MSB
 
- TDA10046H_GPIO_OUT_SEL
 
- TDA10046H_GPIO_SELECT
 
- TDA10046H_TIME_WREF1
 
- TDA10046H_TIME_WREF2
 
- TDA10046H_TIME_WREF3
 
- TDA10046H_TIME_WREF4
 
- TDA10046H_TIME_WREF5
 
- TDA10046_AGC_DEFAULT
 
- TDA10046_AGC_IFO_AUTO_NEG
 
- TDA10046_AGC_IFO_AUTO_POS
 
- TDA10046_AGC_TDA827X
 
- TDA10046_DEFAULT_FIRMWARE
 
- TDA10046_FREQ_045
 
- TDA10046_FREQ_052
 
- TDA10046_FREQ_3613
 
- TDA10046_FREQ_3617
 
- TDA10046_GP00
 
- TDA10046_GP00_I
 
- TDA10046_GP01
 
- TDA10046_GP01_I
 
- TDA10046_GP10
 
- TDA10046_GP10_I
 
- TDA10046_GP11
 
- TDA10046_GP11_I
 
- TDA10046_GPTRI
 
- TDA10046_TS_PARALLEL
 
- TDA10046_TS_SERIAL
 
- TDA10046_XTAL_16M
 
- TDA10046_XTAL_4M
 
- TDA10048_AGC_CONF
 
- TDA10048_AGC_GAINS
 
- TDA10048_AGC_IF_LEVEL
 
- TDA10048_AGC_IF_MAX
 
- TDA10048_AGC_IF_MIN
 
- TDA10048_AGC_RENORM
 
- TDA10048_AGC_THRESHOLD_LSB
 
- TDA10048_AGC_THRESHOLD_MSB
 
- TDA10048_AGC_TUN_LEVEL
 
- TDA10048_AGC_TUN_MAX
 
- TDA10048_AGC_TUN_MIN
 
- TDA10048_AUTO
 
- TDA10048_BULKWRITE_200
 
- TDA10048_BULKWRITE_50
 
- TDA10048_CBER_LSB
 
- TDA10048_CBER_MSB
 
- TDA10048_CBER_NMAX_LSB
 
- TDA10048_CBER_NMAX_MSB
 
- TDA10048_CELL_ID_LSB
 
- TDA10048_CELL_ID_MSB
 
- TDA10048_CHANNEL_INFO1
 
- TDA10048_CHANNEL_INFO1_R
 
- TDA10048_CHANNEL_INFO2
 
- TDA10048_CHANNEL_INFO2_R
 
- TDA10048_CLK_16000
 
- TDA10048_CLK_4000
 
- TDA10048_CODE_IN_RAM
 
- TDA10048_CONF_ADC
 
- TDA10048_CONF_ADC_2
 
- TDA10048_CONF_C1_1
 
- TDA10048_CONF_C1_3
 
- TDA10048_CONF_C3_1
 
- TDA10048_CONF_C4_1
 
- TDA10048_CONF_C4_2
 
- TDA10048_CONF_PLL1
 
- TDA10048_CONF_PLL2
 
- TDA10048_CONF_PLL3
 
- TDA10048_CONF_POLARITY
 
- TDA10048_CONF_TRISTATE1
 
- TDA10048_CONF_TRISTATE2
 
- TDA10048_CONF_TS1
 
- TDA10048_CONF_TS2
 
- TDA10048_CONF_XO
 
- TDA10048_CVBER_CTRL
 
- TDA10048_CVBER_LUT
 
- TDA10048_DEFAULT_FIRMWARE
 
- TDA10048_DEFAULT_FIRMWARE_SIZE
 
- TDA10048_DIG_AGC_LEVEL
 
- TDA10048_DSP_AD_LSB
 
- TDA10048_DSP_AD_MSB
 
- TDA10048_DSP_CODE_CPT
 
- TDA10048_DSP_CODE_IN
 
- TDA10048_DSP_REG_LSB
 
- TDA10048_DSP_REG_MSB
 
- TDA10048_EXTTPS_EVEN
 
- TDA10048_EXTTPS_ODD
 
- TDA10048_FREE_REG_1
 
- TDA10048_FREE_REG_2
 
- TDA10048_FREQ_ERROR_LSB
 
- TDA10048_FREQ_ERROR_LSB_R
 
- TDA10048_FREQ_ERROR_MSB
 
- TDA10048_FREQ_ERROR_MSB_R
 
- TDA10048_FREQ_PHY2_LSB
 
- TDA10048_FREQ_PHY2_MSB
 
- TDA10048_GPIO_OUT_SEL
 
- TDA10048_GPIO_SELECT
 
- TDA10048_GPIO_SP_DS0
 
- TDA10048_GPIO_SP_DS1
 
- TDA10048_GPIO_SP_DS2
 
- TDA10048_GPIO_SP_DS3
 
- TDA10048_H
 
- TDA10048_IC_MODE
 
- TDA10048_IDENTITY
 
- TDA10048_IF_3300
 
- TDA10048_IF_3500
 
- TDA10048_IF_36130
 
- TDA10048_IF_3800
 
- TDA10048_IF_4000
 
- TDA10048_IF_4300
 
- TDA10048_IF_4500
 
- TDA10048_IF_4750
 
- TDA10048_IF_5000
 
- TDA10048_INVERSION_OFF
 
- TDA10048_INVERSION_ON
 
- TDA10048_IN_CONF1
 
- TDA10048_IN_CONF2
 
- TDA10048_IN_CONF3
 
- TDA10048_IT_SEL
 
- TDA10048_IT_STAT
 
- TDA10048_NP_OUT
 
- TDA10048_OUT_CONF1
 
- TDA10048_OUT_CONF2
 
- TDA10048_OUT_CONF3
 
- TDA10048_PARALLEL_OUTPUT
 
- TDA10048_SERIAL_OUTPUT
 
- TDA10048_SOFT_IT_C3
 
- TDA10048_SYNC_STATUS
 
- TDA10048_TIME_ERROR
 
- TDA10048_TIME_ERROR_R
 
- TDA10048_TIME_INVWREF_LSB
 
- TDA10048_TIME_INVWREF_MSB
 
- TDA10048_TIME_WREF_LSB
 
- TDA10048_TIME_WREF_MID1
 
- TDA10048_TIME_WREF_MID2
 
- TDA10048_TIME_WREF_MSB
 
- TDA10048_TPS_LENGTH
 
- TDA10048_UNCOR_CPT_LSB
 
- TDA10048_UNCOR_CPT_MSB
 
- TDA10048_UNCOR_CTRL
 
- TDA10048_VBER_LSB
 
- TDA10048_VBER_MID
 
- TDA10048_VBER_MSB
 
- TDA10048_VERSION
 
- TDA1004X_AUTO
 
- TDA1004X_CBER_LSB
 
- TDA1004X_CBER_MSB
 
- TDA1004X_CBER_RESET
 
- TDA1004X_CHIPID
 
- TDA1004X_CONFADC1
 
- TDA1004X_CONFADC2
 
- TDA1004X_CONFC1
 
- TDA1004X_CONFC4
 
- TDA1004X_CONF_TS1
 
- TDA1004X_CONF_TS2
 
- TDA1004X_CVBER_LUT
 
- TDA1004X_DEMOD_TDA10045
 
- TDA1004X_DEMOD_TDA10046
 
- TDA1004X_DSP_ARG
 
- TDA1004X_DSP_CMD
 
- TDA1004X_DSP_DATA1
 
- TDA1004X_DSP_DATA2
 
- TDA1004X_DSSPARE2
 
- TDA1004X_H
 
- TDA1004X_IN_CONF1
 
- TDA1004X_IN_CONF2
 
- TDA1004X_OUT_CONF1
 
- TDA1004X_OUT_CONF2
 
- TDA1004X_SCAN_CPT
 
- TDA1004X_SNR
 
- TDA1004X_STATUS_CD
 
- TDA1004X_UNCOR
 
- TDA1004X_VBER_LSB
 
- TDA1004X_VBER_MID
 
- TDA1004X_VBER_MSB
 
- TDA10071_ARGLEN
 
- TDA10071_FIRMWARE
 
- TDA10071_H
 
- TDA10071_PRIV
 
- TDA10071_TS_PARALLEL
 
- TDA10071_TS_SERIAL
 
- TDA10086_H
 
- TDA10086_XTAL_16M
 
- TDA10086_XTAL_4M
 
- TDA18212_H
 
- TDA18218_H
 
- TDA18218_NUM_REGS
 
- TDA18218_PRIV_H
 
- TDA18250_H
 
- TDA18250_IRQ_CAL
 
- TDA18250_IRQ_HW_INIT
 
- TDA18250_IRQ_TUNE
 
- TDA18250_NUM_REGS
 
- TDA18250_POWER_NORMAL
 
- TDA18250_POWER_STANDBY
 
- TDA18250_PRIV_H
 
- TDA18250_XTAL_FREQ_16MHZ
 
- TDA18250_XTAL_FREQ_24MHZ
 
- TDA18250_XTAL_FREQ_25MHZ
 
- TDA18250_XTAL_FREQ_27MHZ
 
- TDA18250_XTAL_FREQ_30MHZ
 
- TDA18250_XTAL_FREQ_MAX
 
- TDA18271
 
- TDA18271HDC1
 
- TDA18271HDC2
 
- TDA18271_03_BYTE_CHUNK_INIT
 
- TDA18271_08_BYTE_CHUNK_INIT
 
- TDA18271_16_BYTE_CHUNK_INIT
 
- TDA18271_39_BYTE_CHUNK_INIT
 
- TDA18271_ANALOG
 
- TDA18271_CALLBACK_CMD_AGC_ENABLE
 
- TDA18271_CAL_PLL
 
- TDA18271_DIGITAL
 
- TDA18271_GATE_ANALOG
 
- TDA18271_GATE_AUTO
 
- TDA18271_GATE_DIGITAL
 
- TDA18271_MAIN_PLL
 
- TDA18271_MASTER
 
- TDA18271_NUM_REGS
 
- TDA18271_OUTPUT_LT_OFF
 
- TDA18271_OUTPUT_LT_XT_ON
 
- TDA18271_OUTPUT_XT_OFF
 
- TDA18271_SLAVE
 
- TDA19971
 
- TDA19973
 
- TDA1997X_ACLK_128FS
 
- TDA1997X_ACLK_16FS
 
- TDA1997X_ACLK_256FS
 
- TDA1997X_ACLK_32FS
 
- TDA1997X_ACLK_512FS
 
- TDA1997X_ACLK_64FS
 
- TDA1997X_B_CB_11_8
 
- TDA1997X_B_CB_11_8_S
 
- TDA1997X_B_CB_3_0
 
- TDA1997X_B_CB_3_0_S
 
- TDA1997X_B_CB_7_4
 
- TDA1997X_B_CB_7_4_S
 
- TDA1997X_DST
 
- TDA1997X_G_Y_11_8
 
- TDA1997X_G_Y_11_8_S
 
- TDA1997X_G_Y_3_0
 
- TDA1997X_G_Y_3_0_S
 
- TDA1997X_G_Y_7_4
 
- TDA1997X_G_Y_7_4_S
 
- TDA1997X_I2S16
 
- TDA1997X_I2S16_HBR
 
- TDA1997X_I2S16_HBR_DEMUX
 
- TDA1997X_I2S32
 
- TDA1997X_I2S32_HBR_DEMUX
 
- TDA1997X_LAYOUT0
 
- TDA1997X_LAYOUT1
 
- TDA1997X_MBUS_CODES
 
- TDA1997X_NUM_PADS
 
- TDA1997X_NUM_SUPPLIES
 
- TDA1997X_OBA
 
- TDA1997X_PAD_SOURCE
 
- TDA1997X_R_CR_CBCR_11_8
 
- TDA1997X_R_CR_CBCR_11_8_S
 
- TDA1997X_R_CR_CBCR_3_0
 
- TDA1997X_R_CR_CBCR_3_0_S
 
- TDA1997X_R_CR_CBCR_7_4
 
- TDA1997X_R_CR_CBCR_7_4_S
 
- TDA1997X_SPDIF
 
- TDA1997X_SPDIF_HBR_DEMUX
 
- TDA1997X_VP24_V03_00
 
- TDA1997X_VP24_V07_04
 
- TDA1997X_VP24_V11_08
 
- TDA1997X_VP24_V15_12
 
- TDA1997X_VP24_V19_16
 
- TDA1997X_VP24_V23_20
 
- TDA1997X_VP36_03_00
 
- TDA1997X_VP36_07_04
 
- TDA1997X_VP36_11_08
 
- TDA1997X_VP36_15_12
 
- TDA1997X_VP36_19_16
 
- TDA1997X_VP36_23_20
 
- TDA1997X_VP36_27_24
 
- TDA1997X_VP36_31_28
 
- TDA1997X_VP36_35_32
 
- TDA1997X_VP_HIZ
 
- TDA1997X_VP_OUT_EN
 
- TDA1997X_VP_SWP
 
- TDA19988
 
- TDA19989
 
- TDA19989N2
 
- TDA7318_ADDR
 
- TDA7419_ATTENUATOR_LF_REG
 
- TDA7419_ATTENUATOR_LR_REG
 
- TDA7419_ATTENUATOR_RF_REG
 
- TDA7419_ATTENUATOR_RR_REG
 
- TDA7419_ATTENUATOR_SUB_REG
 
- TDA7419_BASS_CENTER_FREQ
 
- TDA7419_BASS_DC_MODE
 
- TDA7419_BASS_Q_FACTOR
 
- TDA7419_BASS_REG
 
- TDA7419_BASS_SOFT_STEP
 
- TDA7419_CLK_FAST_MODE
 
- TDA7419_CLK_SOURCE
 
- TDA7419_COUPLING_MODE
 
- TDA7419_DOUBLE_R_TLV
 
- TDA7419_DOUBLE_R_VALUE
 
- TDA7419_HPF_GAIN
 
- TDA7419_LOUDNESS_ATTEN
 
- TDA7419_LOUDNESS_BOOST
 
- TDA7419_LOUDNESS_CENTER_FREQ
 
- TDA7419_LOUDNESS_REG
 
- TDA7419_LOUDNESS_SOFT_STEP
 
- TDA7419_MAIN_SRC_AUTOZERO
 
- TDA7419_MAIN_SRC_GAIN
 
- TDA7419_MAIN_SRC_REG
 
- TDA7419_MAIN_SRC_SEL
 
- TDA7419_MIDDLE_CENTER_FREQ
 
- TDA7419_MIDDLE_Q_FACTOR
 
- TDA7419_MIDDLE_REG
 
- TDA7419_MIDDLE_SOFT_STEP
 
- TDA7419_MIXING_GAIN_REG
 
- TDA7419_MIXING_LEVEL_REG
 
- TDA7419_MIX_ENABLE
 
- TDA7419_MIX_LF
 
- TDA7419_MIX_RF
 
- TDA7419_MUTE_CLK_REG
 
- TDA7419_MUTE_INFLUENCE
 
- TDA7419_REAR_SPKR_SRC
 
- TDA7419_REF_OUT_SELECT
 
- TDA7419_RESET
 
- TDA7419_RESET_MODE
 
- TDA7419_SA_CLK_AC_REG
 
- TDA7419_SA_Q_FACTOR
 
- TDA7419_SA_RUN
 
- TDA7419_SA_SOURCE
 
- TDA7419_SECOND_SRC_GAIN
 
- TDA7419_SECOND_SRC_REG
 
- TDA7419_SECOND_SRC_SEL
 
- TDA7419_SINGLE_TLV
 
- TDA7419_SINGLE_VALUE
 
- TDA7419_SMOOTHING_FILTER
 
- TDA7419_SOFT_MUTE
 
- TDA7419_SOFT_MUTE_TIME
 
- TDA7419_SOFT_STEP_TIME
 
- TDA7419_SUB_CUT_OFF_FREQ
 
- TDA7419_SUB_ENABLE
 
- TDA7419_SUB_MID_BASS_REG
 
- TDA7419_TESTING_REG
 
- TDA7419_TREBLE_CENTER_FREQ
 
- TDA7419_TREBLE_REG
 
- TDA7419_VOLUME_REG
 
- TDA7419_VOLUME_SOFT_STEP
 
- TDA7432_ATTEN_0DB
 
- TDA7432_BASS
 
- TDA7432_BASS_0DB
 
- TDA7432_BASS_GAIN
 
- TDA7432_BASS_NORM
 
- TDA7432_BASS_SYM
 
- TDA7432_IN
 
- TDA7432_LD
 
- TDA7432_LD_ON
 
- TDA7432_LF
 
- TDA7432_LR
 
- TDA7432_MONO_IN
 
- TDA7432_MUTE
 
- TDA7432_RF
 
- TDA7432_RR
 
- TDA7432_STEREO_IN
 
- TDA7432_TN
 
- TDA7432_TREBLE
 
- TDA7432_TREBLE_0DB
 
- TDA7432_TREBLE_GAIN
 
- TDA7432_VL
 
- TDA7432_VOL_0DB
 
- TDA8083_H
 
- TDA8261_STEP_1000
 
- TDA8261_STEP_125
 
- TDA8261_STEP_2000
 
- TDA8261_STEP_250
 
- TDA8261_STEP_500
 
- TDA8275
 
- TDA8275A
 
- TDA8290
 
- TDA8290_ID
 
- TDA8290_LNA_GP0_HIGH_OFF
 
- TDA8290_LNA_GP0_HIGH_ON
 
- TDA8290_LNA_OFF
 
- TDA8290_LNA_ON_BRIDGE
 
- TDA8295
 
- TDA8295C2_ID
 
- TDA8295_ID
 
- TDA829X_DONT_PROBE
 
- TDA829X_PROBE_TUNER
 
- TDA8425_BA
 
- TDA8425_S1
 
- TDA8425_S1_CH1
 
- TDA8425_S1_CH2
 
- TDA8425_S1_IS
 
- TDA8425_S1_ML
 
- TDA8425_S1_ML_SOUND_A
 
- TDA8425_S1_ML_SOUND_B
 
- TDA8425_S1_ML_STEREO
 
- TDA8425_S1_MU
 
- TDA8425_S1_OFF
 
- TDA8425_S1_STEREO
 
- TDA8425_S1_STEREO_LINEAR
 
- TDA8425_S1_STEREO_MONO
 
- TDA8425_S1_STEREO_PSEUDO
 
- TDA8425_S1_STEREO_SPATIAL
 
- TDA8425_TR
 
- TDA8425_VL
 
- TDA8425_VR
 
- TDA9840_DS_DUAL
 
- TDA9840_DUALA
 
- TDA9840_DUALAB
 
- TDA9840_DUALB
 
- TDA9840_DUALBA
 
- TDA9840_EXTERNAL
 
- TDA9840_LVADJ
 
- TDA9840_MONO
 
- TDA9840_PONRES
 
- TDA9840_SET_BOTH
 
- TDA9840_SET_BOTH_R
 
- TDA9840_SET_EXTERNAL
 
- TDA9840_SET_LANG1
 
- TDA9840_SET_LANG2
 
- TDA9840_SET_MONO
 
- TDA9840_SET_MUTE
 
- TDA9840_SET_STEREO
 
- TDA9840_STADJ
 
- TDA9840_STEREO
 
- TDA9840_ST_STEREO
 
- TDA9840_SW
 
- TDA9840_TEST
 
- TDA9840_TEST_INT1SN
 
- TDA9840_TEST_INTFU
 
- TDA9850_C4
 
- TDA9855_AVL
 
- TDA9855_BA
 
- TDA9855_EXT
 
- TDA9855_E_MONO
 
- TDA9855_INT
 
- TDA9855_LINEAR
 
- TDA9855_LOUD
 
- TDA9855_MUTE
 
- TDA9855_PSEUDO
 
- TDA9855_SPAT_30
 
- TDA9855_SPAT_50
 
- TDA9855_SUR
 
- TDA9855_SW
 
- TDA9855_TR
 
- TDA9855_TZCM
 
- TDA9855_VL
 
- TDA9855_VR
 
- TDA9855_VZCM
 
- TDA985x_A1
 
- TDA985x_A2
 
- TDA985x_A3
 
- TDA985x_ADJ
 
- TDA985x_C5
 
- TDA985x_C6
 
- TDA985x_C7
 
- TDA985x_LMU
 
- TDA985x_MONO
 
- TDA985x_MONOSAP
 
- TDA985x_SAP
 
- TDA985x_SAPP
 
- TDA985x_STEREO
 
- TDA985x_STP
 
- TDA985x_STS
 
- TDA9873_AD
 
- TDA9873_AUTOMUTE
 
- TDA9873_BG
 
- TDA9873_DK1
 
- TDA9873_DK2
 
- TDA9873_DK3
 
- TDA9873_DUAL
 
- TDA9873_EXT_MONO
 
- TDA9873_EXT_STEREO
 
- TDA9873_GAIN_NORMAL
 
- TDA9873_I
 
- TDA9873_IDR_FAST
 
- TDA9873_IDR_NORM
 
- TDA9873_INP_MASK
 
- TDA9873_INTERNAL
 
- TDA9873_M
 
- TDA9873_MOUT_DUALA
 
- TDA9873_MOUT_DUALB
 
- TDA9873_MOUT_EXTL
 
- TDA9873_MOUT_EXTLR
 
- TDA9873_MOUT_EXTM
 
- TDA9873_MOUT_EXTR
 
- TDA9873_MOUT_FMONO
 
- TDA9873_MOUT_MONO
 
- TDA9873_MOUT_MUTE
 
- TDA9873_MOUT_ST
 
- TDA9873_MUTE
 
- TDA9873_PONR
 
- TDA9873_PORTS
 
- TDA9873_PT
 
- TDA9873_STEREO
 
- TDA9873_STEREO_ADJ
 
- TDA9873_SW
 
- TDA9873_TR_DUALA
 
- TDA9873_TR_DUALAB
 
- TDA9873_TR_DUALB
 
- TDA9873_TR_MASK
 
- TDA9873_TR_MONO
 
- TDA9873_TR_REVERSE
 
- TDA9873_TR_STEREO
 
- TDA9873_TST_PORT
 
- TDA9874A_AGCGR
 
- TDA9874A_AMCONR
 
- TDA9874A_AOSR
 
- TDA9874A_C1FRA
 
- TDA9874A_C1FRB
 
- TDA9874A_C1FRC
 
- TDA9874A_C1OLAR
 
- TDA9874A_C2FRA
 
- TDA9874A_C2FRB
 
- TDA9874A_C2FRC
 
- TDA9874A_C2OLAR
 
- TDA9874A_DAICONR
 
- TDA9874A_DCR
 
- TDA9874A_DIC
 
- TDA9874A_DR1
 
- TDA9874A_DR2
 
- TDA9874A_DSR
 
- TDA9874A_ESP
 
- TDA9874A_FMER
 
- TDA9874A_FMMR
 
- TDA9874A_GCONR
 
- TDA9874A_I2SOLAR
 
- TDA9874A_I2SOSR
 
- TDA9874A_LLRA
 
- TDA9874A_LLRB
 
- TDA9874A_MDACOSR
 
- TDA9874A_MSR
 
- TDA9874A_NCONR
 
- TDA9874A_NECR
 
- TDA9874A_NLELR
 
- TDA9874A_NOLAR
 
- TDA9874A_NSR
 
- TDA9874A_NUELR
 
- TDA9874A_SDACOSR
 
- TDA9874A_SIC
 
- TDA9874A_SIFLR
 
- TDA9874A_TR1
 
- TDA9874A_TR2
 
- TDA9875_ABA
 
- TDA9875_ACS
 
- TDA9875_ADCIS
 
- TDA9875_AER
 
- TDA9875_ATR
 
- TDA9875_AVL
 
- TDA9875_AVR
 
- TDA9875_C1LSB
 
- TDA9875_C1MIB
 
- TDA9875_C1MSB
 
- TDA9875_C2LSB
 
- TDA9875_C2MIB
 
- TDA9875_C2MSB
 
- TDA9875_CFG
 
- TDA9875_CH1V
 
- TDA9875_CH2V
 
- TDA9875_DACOS
 
- TDA9875_DCR
 
- TDA9875_DEEM
 
- TDA9875_FMAT
 
- TDA9875_LOSR
 
- TDA9875_MBA
 
- TDA9875_MCS
 
- TDA9875_MSR
 
- TDA9875_MTR
 
- TDA9875_MUT
 
- TDA9875_MUTE_OFF
 
- TDA9875_MUTE_ON
 
- TDA9875_MVL
 
- TDA9875_MVR
 
- TDA9875_SC1
 
- TDA9875_SC2
 
- TDA9887_AUTOMUTE
 
- TDA9887_DEEMPHASIS_50
 
- TDA9887_DEEMPHASIS_75
 
- TDA9887_DEEMPHASIS_MASK
 
- TDA9887_DEEMPHASIS_NONE
 
- TDA9887_GAIN_NORMAL
 
- TDA9887_GATING_18
 
- TDA9887_INTERCARRIER
 
- TDA9887_INTERCARRIER_NTSC
 
- TDA9887_PORT1_ACTIVE
 
- TDA9887_PORT1_INACTIVE
 
- TDA9887_PORT2_ACTIVE
 
- TDA9887_PORT2_INACTIVE
 
- TDA9887_PRESENT
 
- TDA9887_QSS
 
- TDA9887_RIF_41_3
 
- TDA9887_TOP
 
- TDA9887_TOP_MASK
 
- TDA9887_TOP_SET
 
- TDA9989N2
 
- TDA998x_I2S
 
- TDA998x_SPDIF
 
- TDAT
 
- TDATA_LEFT
 
- TDA_Fn_ECC_DB_ERR
 
- TDA_Fn_ECC_SG_ERR
 
- TDA_PCIX_ERR
 
- TDA_SM0_ERR_ALARM
 
- TDA_SM1_ERR_ALARM
 
- TDBCR
 
- TDB_FORMAT1
 
- TDCDPR
 
- TDCE_F
 
- TDCE_S
 
- TDCE_V
 
- TDCP
 
- TDCR
 
- TDCR_ABR
 
- TDCR_BURSTSZ_128B
 
- TDCR_BURSTSZ_16B
 
- TDCR_BURSTSZ_32B
 
- TDCR_BURSTSZ_4B
 
- TDCR_BURSTSZ_64B
 
- TDCR_BURSTSZ_8B
 
- TDCR_BURSTSZ_MSK
 
- TDCR_BURSTSZ_SQU_16B
 
- TDCR_BURSTSZ_SQU_1B
 
- TDCR_BURSTSZ_SQU_2B
 
- TDCR_BURSTSZ_SQU_32B
 
- TDCR_BURSTSZ_SQU_4B
 
- TDCR_BURSTSZ_SQU_8B
 
- TDCR_CDE
 
- TDCR_CHAINMOD
 
- TDCR_CHANACT
 
- TDCR_CHANEN
 
- TDCR_DSTDESCCONT
 
- TDCR_DSTDIR_ADDR_HOLD
 
- TDCR_DSTDIR_ADDR_INC
 
- TDCR_DSTDIR_MSK
 
- TDCR_FETCHND
 
- TDCR_INTMODE
 
- TDCR_PACKMOD
 
- TDCR_SRCDESTCONT
 
- TDCR_SRCDIR_ADDR_HOLD
 
- TDCR_SRCDIR_ADDR_INC
 
- TDCR_SRCDIR_MSK
 
- TDCR_SSPMOD
 
- TDCR_SSZ_12_BITS
 
- TDCR_SSZ_16_BITS
 
- TDCR_SSZ_20_BITS
 
- TDCR_SSZ_24_BITS
 
- TDCR_SSZ_32_BITS
 
- TDCR_SSZ_8_BITS
 
- TDCR_SSZ_MASK
 
- TDCR_SSZ_SHIFT
 
- TDCR_TDCF_MASK
 
- TDCR_TDCF_SHIFT
 
- TDCR_TDCO_MASK
 
- TDCR_TDCO_SHIFT
 
- TDCSR
 
- TDC_MV_AVERAGE__IDDC_MASK
 
- TDC_MV_AVERAGE__IDDC__SHIFT
 
- TDC_MV_AVERAGE__IDDNB_MASK
 
- TDC_MV_AVERAGE__IDDNB__SHIFT
 
- TDC_MV_AVERAGE__IDD_MASK
 
- TDC_MV_AVERAGE__IDD__SHIFT
 
- TDC_STATUS__VDDC_Boost_MASK
 
- TDC_STATUS__VDDC_Boost__SHIFT
 
- TDC_STATUS__VDDC_Throttle_MASK
 
- TDC_STATUS__VDDC_Throttle__SHIFT
 
- TDC_STATUS__VDDNB_Boost_MASK
 
- TDC_STATUS__VDDNB_Boost__SHIFT
 
- TDC_STATUS__VDDNB_Throttle_MASK
 
- TDC_STATUS__VDDNB_Throttle__SHIFT
 
- TDC_STATUS__VDD_Boost_MASK
 
- TDC_STATUS__VDD_Boost__SHIFT
 
- TDC_STATUS__VDD_Throttle_MASK
 
- TDC_STATUS__VDD_Throttle__SHIFT
 
- TDC_VRM_LIMIT__IDDC_MASK
 
- TDC_VRM_LIMIT__IDDC__SHIFT
 
- TDC_VRM_LIMIT__IDDNB_MASK
 
- TDC_VRM_LIMIT__IDDNB__SHIFT
 
- TDC_VRM_LIMIT__IDD_MASK
 
- TDC_VRM_LIMIT__IDD__SHIFT
 
- TDDAR
 
- TDES0_COLLISION_COUNT_MASK
 
- TDES0_COLLISION_COUNT_MASK_
 
- TDES0_COLLISION_COUNT_SHFT_
 
- TDES0_CONTROL_DONE
 
- TDES0_CONTROL_OWN
 
- TDES0_CONTROL_TXDR
 
- TDES0_DEFERRED
 
- TDES0_DEFERRED_
 
- TDES0_ERROR_SUMMARY
 
- TDES0_ERROR_SUMMARY_
 
- TDES0_ERR_MASK
 
- TDES0_EXCESSIVE_COLLISIONS
 
- TDES0_EXCESSIVE_COLLISIONS_
 
- TDES0_EXCESSIVE_DEFERRAL
 
- TDES0_EXCESSIVE_DEFERRAL_
 
- TDES0_FRAME_FLUSHED
 
- TDES0_HEARTBEAT_FAIL_
 
- TDES0_IP_HEADER_ERROR
 
- TDES0_JABBER_TIMEOUT
 
- TDES0_LATE_COLLISION
 
- TDES0_LATE_COLLISION_
 
- TDES0_LOSS_CARRIER
 
- TDES0_LOSS_OF_CARRIER_
 
- TDES0_NO_CARRIER
 
- TDES0_NO_CARRIER_
 
- TDES0_OWN
 
- TDES0_OWN_
 
- TDES0_PAYLOAD_ERROR
 
- TDES0_STATUS_ACR
 
- TDES0_STATUS_DONE
 
- TDES0_STATUS_ES
 
- TDES0_STATUS_OWN
 
- TDES0_STATUS_SOFBR
 
- TDES0_STATUS_TLT
 
- TDES0_STATUS_TRO
 
- TDES0_STATUS_TRT
 
- TDES0_STATUS_TUF
 
- TDES0_TIME_STAMP_STATUS
 
- TDES0_UNDERFLOW_ERROR
 
- TDES0_VLAN_FRAME
 
- TDES1_BUFFER1_SIZE_MASK
 
- TDES1_BUFFER2_SIZE_MASK
 
- TDES1_BUFFER2_SIZE_SHIFT
 
- TDES1_CHECKSUM_INSERTION_MASK
 
- TDES1_CHECKSUM_INSERTION_SHIFT
 
- TDES1_CONTROL_FS
 
- TDES1_CONTROL_IC
 
- TDES1_CONTROL_LS
 
- TDES1_CONTROL_RBS1
 
- TDES1_CONTROL_RBS2
 
- TDES1_CONTROL_TCH
 
- TDES1_CONTROL_TER
 
- TDES1_CRC_DISABLE
 
- TDES1_DISABLE_PADDING
 
- TDES1_END_RING
 
- TDES1_FIRST_SEGMENT
 
- TDES1_FS_
 
- TDES1_IC_
 
- TDES1_INTERRUPT
 
- TDES1_LAST_SEGMENT
 
- TDES1_LS_
 
- TDES1_SECOND_ADDRESS_CHAINED
 
- TDES1_TCH_
 
- TDES1_TER_
 
- TDES1_TIME_STAMP_ENABLE
 
- TDES1_TXCSEN_
 
- TDES2_BUFFER1_SIZE_MASK
 
- TDES2_BUFFER2_SIZE_MASK
 
- TDES2_BUFFER2_SIZE_MASK_SHIFT
 
- TDES2_INTERRUPT_ON_COMPLETION
 
- TDES2_IVT_MASK
 
- TDES2_IVT_SHIFT
 
- TDES2_TIMESTAMP_ENABLE
 
- TDES2_VLAN_TAG_MASK
 
- TDES2_VLAN_TAG_SHIFT
 
- TDES3_CHECKSUM_INSERTION_MASK
 
- TDES3_CHECKSUM_INSERTION_SHIFT
 
- TDES3_COLLISION_COUNT_MASK
 
- TDES3_COLLISION_COUNT_SHIFT
 
- TDES3_CONTEXT_TYPE
 
- TDES3_CONTEXT_TYPE_SHIFT
 
- TDES3_CRC_PAD_CTRL_MASK
 
- TDES3_CTXT_TCMSSV
 
- TDES3_DEFERRED
 
- TDES3_ERROR_SUMMARY
 
- TDES3_EXCESSIVE_COLLISION
 
- TDES3_EXCESSIVE_DEFERRAL
 
- TDES3_FIRST_DESCRIPTOR
 
- TDES3_HDR_LEN_SHIFT
 
- TDES3_IP_HDR_ERROR
 
- TDES3_IVLTV
 
- TDES3_IVTIR_MASK
 
- TDES3_IVTIR_SHIFT
 
- TDES3_JABBER_TIMEOUT
 
- TDES3_LAST_DESCRIPTOR
 
- TDES3_LAST_DESCRIPTOR_SHIFT
 
- TDES3_LATE_COLLISION
 
- TDES3_LOSS_CARRIER
 
- TDES3_NO_CARRIER
 
- TDES3_OWN
 
- TDES3_OWN_SHIFT
 
- TDES3_PACKET_FLUSHED
 
- TDES3_PACKET_SIZE_MASK
 
- TDES3_PAYLOAD_ERROR
 
- TDES3_RS1V
 
- TDES3_RS1V_SHIFT
 
- TDES3_SA_INSERT_CTRL_MASK
 
- TDES3_SA_INSERT_CTRL_SHIFT
 
- TDES3_SLOT_NUMBER_MASK
 
- TDES3_TCP_PKT_PAYLOAD_MASK
 
- TDES3_TCP_SEGMENTATION_ENABLE
 
- TDES3_TIMESTAMP_STATUS
 
- TDES3_TIMESTAMP_STATUS_SHIFT
 
- TDES3_UNDERFLOW_ERROR
 
- TDES3_VLAN_TAG
 
- TDES3_VLTV
 
- TDESC1_BUFFER_ABORT
 
- TDESC1_BUFFER_INDEX
 
- TDESC1_BUFFER_LENGTH
 
- TDESC1_EOF
 
- TDES_COLLISION_COUNT_BIT_NUMBER
 
- TDES_CR
 
- TDES_CR_LOADSEED
 
- TDES_CR_START
 
- TDES_CR_SWRST
 
- TDES_FLAGS_BUSY
 
- TDES_FLAGS_CBC
 
- TDES_FLAGS_CFB
 
- TDES_FLAGS_CFB16
 
- TDES_FLAGS_CFB32
 
- TDES_FLAGS_CFB64
 
- TDES_FLAGS_CFB8
 
- TDES_FLAGS_DMA
 
- TDES_FLAGS_ENCRYPT
 
- TDES_FLAGS_FAST
 
- TDES_FLAGS_INIT
 
- TDES_FLAGS_MODE_MASK
 
- TDES_FLAGS_OFB
 
- TDES_HW_VERSION
 
- TDES_IDATA1R
 
- TDES_IDATA2R
 
- TDES_IDR
 
- TDES_IER
 
- TDES_IMR
 
- TDES_INT_DATARDY
 
- TDES_INT_ENDRX
 
- TDES_INT_ENDTX
 
- TDES_INT_RXBUFF
 
- TDES_INT_TXBUFE
 
- TDES_INT_URAD
 
- TDES_ISR
 
- TDES_ISR_URAT_IDR
 
- TDES_ISR_URAT_MASK
 
- TDES_ISR_URAT_MR
 
- TDES_ISR_URAT_ODR
 
- TDES_ISR_URAT_WO
 
- TDES_IV1R
 
- TDES_IV2R
 
- TDES_KEY1W1R
 
- TDES_KEY1W2R
 
- TDES_KEY2W1R
 
- TDES_KEY2W2R
 
- TDES_KEY3W1R
 
- TDES_KEY3W2R
 
- TDES_MR
 
- TDES_MR_CFBS_16b
 
- TDES_MR_CFBS_32b
 
- TDES_MR_CFBS_64b
 
- TDES_MR_CFBS_8b
 
- TDES_MR_CFBS_MASK
 
- TDES_MR_CKEY_MASK
 
- TDES_MR_CKEY_OFFSET
 
- TDES_MR_CTYPE_MASK
 
- TDES_MR_CTYPE_OFFSET
 
- TDES_MR_CYPHER_DEC
 
- TDES_MR_CYPHER_ENC
 
- TDES_MR_KEYMOD_2KEY
 
- TDES_MR_KEYMOD_3KEY
 
- TDES_MR_LOD
 
- TDES_MR_OPMOD_CBC
 
- TDES_MR_OPMOD_CFB
 
- TDES_MR_OPMOD_ECB
 
- TDES_MR_OPMOD_MASK
 
- TDES_MR_OPMOD_OFB
 
- TDES_MR_SMOD_AUTO
 
- TDES_MR_SMOD_MANUAL
 
- TDES_MR_SMOD_MASK
 
- TDES_MR_SMOD_PDC
 
- TDES_MR_TDESMOD_DES
 
- TDES_MR_TDESMOD_MASK
 
- TDES_MR_TDESMOD_TDES
 
- TDES_MR_TDESMOD_XTEA
 
- TDES_ODATA1R
 
- TDES_ODATA2R
 
- TDES_PTCR
 
- TDES_PTCR_RXTDIS
 
- TDES_PTCR_RXTEN
 
- TDES_PTCR_TXTDIS
 
- TDES_PTCR_TXTEN
 
- TDES_PTSR
 
- TDES_PTSR_RXTEN
 
- TDES_PTSR_TXTEN
 
- TDES_RCR
 
- TDES_RNCR
 
- TDES_RNPR
 
- TDES_RPR
 
- TDES_SECOND_BUFFER_SIZE_BIT_NUMBER
 
- TDES_TCR
 
- TDES_TNCR
 
- TDES_TNPR
 
- TDES_TPR
 
- TDES_XTEARNDR
 
- TDES_XTEARNDR_XTEA_RNDS_MASK
 
- TDES_XTEARNDR_XTEA_RNDS_OFFSET
 
- TDF1ST
 
- TDFAR
 
- TDFE
 
- TDFEND
 
- TDFFR
 
- TDFP_EN
 
- TDFR
 
- TDFR_ADDR
 
- TDFXR
 
- TDFX_ROP_COPY
 
- TDFX_ROP_INVERT
 
- TDFX_ROP_XOR
 
- TDHD1_H
 
- TDIAR
 
- TDIF_REG_DBG_DWORD_ENABLE
 
- TDIF_REG_DBG_FORCE_FRAME
 
- TDIF_REG_DBG_FORCE_VALID
 
- TDIF_REG_DBG_SELECT
 
- TDIF_REG_DBG_SHIFT
 
- TDIF_REG_DEBUG_ERROR_INFO
 
- TDIF_REG_DEBUG_ERROR_INFO_SIZE
 
- TDIF_REG_STOP_ON_ERROR
 
- TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_MASK
 
- TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_SHIFT
 
- TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_MASK
 
- TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_SHIFT
 
- TDIF_TASK_CONTEXT_CRC_SEED_MASK
 
- TDIF_TASK_CONTEXT_CRC_SEED_SHIFT
 
- TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK
 
- TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT
 
- TDIF_TASK_CONTEXT_ERROR_IN_IO_A_MASK
 
- TDIF_TASK_CONTEXT_ERROR_IN_IO_A_SHIFT
 
- TDIF_TASK_CONTEXT_ERROR_IN_IO_B_MASK
 
- TDIF_TASK_CONTEXT_ERROR_IN_IO_B_SHIFT
 
- TDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK
 
- TDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT
 
- TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK
 
- TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT
 
- TDIF_TASK_CONTEXT_FORWARD_GUARD_MASK
 
- TDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT
 
- TDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK
 
- TDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT
 
- TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK
 
- TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT
 
- TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK
 
- TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT
 
- TDIF_TASK_CONTEXT_HOST_INTERFACE_MASK
 
- TDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT
 
- TDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK
 
- TDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT
 
- TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK
 
- TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT
 
- TDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK
 
- TDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT
 
- TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK
 
- TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT
 
- TDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK
 
- TDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT
 
- TDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK
 
- TDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT
 
- TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_MASK
 
- TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_SHIFT
 
- TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_MASK
 
- TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_SHIFT
 
- TDIF_TASK_CONTEXT_REF_TAG_MASK_MASK
 
- TDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT
 
- TDIF_TASK_CONTEXT_RESERVED0_MASK
 
- TDIF_TASK_CONTEXT_RESERVED0_SHIFT
 
- TDIF_TASK_CONTEXT_RESERVED2_MASK
 
- TDIF_TASK_CONTEXT_RESERVED2_SHIFT
 
- TDIF_TASK_CONTEXT_RESERVED3_MASK
 
- TDIF_TASK_CONTEXT_RESERVED3_SHIFT
 
- TDIF_TASK_CONTEXT_RESERVED4_MASK
 
- TDIF_TASK_CONTEXT_RESERVED4_SHIFT
 
- TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK
 
- TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT
 
- TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_MASK
 
- TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_SHIFT
 
- TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_MASK
 
- TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_SHIFT
 
- TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK
 
- TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT
 
- TDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK
 
- TDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT
 
- TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK
 
- TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT
 
- TDIMR
 
- TDIMR_COMP
 
- TDISR
 
- TDISR_COMP
 
- TDIVMODE
 
- TDI_HIGH
 
- TDI_LOW
 
- TDI_MARK
 
- TDK
 
- TDK_AUTO_MODE
 
- TDK_MANU_MODE
 
- TDLAR
 
- TDLR
 
- TDLS
 
- TDLS_BASE_CHANNEL
 
- TDLS_CHANNEL_SWITCH_CMD
 
- TDLS_CHANNEL_SWITCH_NOTIFICATION
 
- TDLS_CHAN_SWITCHING
 
- TDLS_CONFIG_CMD
 
- TDLS_CONFIRM_FIX_LEN
 
- TDLS_ERR_INTERNAL_ERROR
 
- TDLS_ERR_LINK_EXISTS
 
- TDLS_ERR_LINK_NONEXISTENT
 
- TDLS_ERR_MAX_LINKS_EST
 
- TDLS_ERR_NO_ERROR
 
- TDLS_ERR_PEER_STA_UNREACHABLE
 
- TDLS_EVENT_CHAN_SWITCH_RESULT
 
- TDLS_EVENT_CHAN_SWITCH_STOPPED
 
- TDLS_EVENT_LINK_TEAR_DOWN
 
- TDLS_EVENT_START_CHAN_SWITCH
 
- TDLS_IN_BASE_CHAN
 
- TDLS_IN_OFF_CHAN
 
- TDLS_LINK_TEARDOWN
 
- TDLS_MOVE_CH
 
- TDLS_NOT_SETUP
 
- TDLS_OFF_CHANNEL
 
- TDLS_PEER_SETUP_TIMEOUT
 
- TDLS_REQ_FIX_LEN
 
- TDLS_RESP_FIX_LEN
 
- TDLS_SCAN_COEXISTENCE
 
- TDLS_SEND_CHAN_SW_REQ
 
- TDLS_SEND_CHAN_SW_RESP_AND_MOVE_CH
 
- TDLS_SETUP_COMPLETE
 
- TDLS_SETUP_FAILURE
 
- TDLS_SETUP_INPROGRESS
 
- TDLSoption_param
 
- TDM0
 
- TDM1
 
- TDMAE_SHIFT
 
- TDMA_1ANT
 
- TDMA_2ANT
 
- TDMA_4SLOT
 
- TDMA_ARB_EN
 
- TDMA_ARB_MODE_DEFICIT_RR
 
- TDMA_ARB_MODE_RR
 
- TDMA_ARB_MODE_STRICT
 
- TDMA_ARB_MODE_WEIGHT_RR
 
- TDMA_CHANNEL_NUM
 
- TDMA_CONS_INDEX
 
- TDMA_CONTROL
 
- TDMA_CREDIT_MASK
 
- TDMA_CREDIT_SHIFT
 
- TDMA_DAC_SWING_OFF
 
- TDMA_DAC_SWING_ON
 
- TDMA_DEBUG
 
- TDMA_DESC_RING_00_BASE
 
- TDMA_DESC_RING_BASE
 
- TDMA_DESC_RING_COUNT
 
- TDMA_DESC_RING_HEAD_TAIL_PTR
 
- TDMA_DESC_RING_INTR_CONTROL
 
- TDMA_DESC_RING_MAPPING
 
- TDMA_DESC_RING_MAX_HYST
 
- TDMA_DESC_RING_PCP_DEI_VID
 
- TDMA_DESC_RING_PROD_CONS_INDEX
 
- TDMA_DESC_RING_SIZE
 
- TDMA_DISABLED
 
- TDMA_EN
 
- TDMA_EOP_SEL
 
- TDMA_FLOW_PERIOD
 
- TDMA_FREE_HEAD_MASK
 
- TDMA_FREE_LIST_COUNT
 
- TDMA_FREE_LIST_COUNT_MASK
 
- TDMA_FREE_LIST_HEAD_TAIL_PTR
 
- TDMA_FREE_TAIL_MASK
 
- TDMA_FREE_TAIL_SHIFT
 
- TDMA_LE_MODE
 
- TDMA_LL_RAM_INIT_BUSY
 
- TDMA_MAX_XFER_BYTES
 
- TDMA_MEM_TM
 
- TDMA_NAV_OFF
 
- TDMA_NAV_ON
 
- TDMA_NUM_RINGS
 
- TDMA_OVER_HYST_THRESH_STATUS
 
- TDMA_OVER_MAX_THRESH_STATUS
 
- TDMA_PORT_SIZE
 
- TDMA_PROD_INDEX
 
- TDMA_READ_PORT_CMD
 
- TDMA_READ_PORT_CMD_OFFSET
 
- TDMA_READ_PORT_HI
 
- TDMA_READ_PORT_LO
 
- TDMA_READ_PORT_OFFSET
 
- TDMA_READ_PTR
 
- TDMA_READ_PTR_HI
 
- TDMA_REG_MODE
 
- TDMA_SCB_BURST_SIZE
 
- TDMA_SCB_ENDIAN_OVERRIDE
 
- TDMA_STATUS
 
- TDMA_TEST
 
- TDMA_TIER1_ARB_0_CTRL
 
- TDMA_TIER1_ARB_0_QUEUE_EN
 
- TDMA_TIER1_ARB_1_CTRL
 
- TDMA_TIER1_ARB_1_QUEUE_EN
 
- TDMA_TIER1_ARB_2_CTRL
 
- TDMA_TIER1_ARB_2_QUEUE_EN
 
- TDMA_TIER1_ARB_3_CTRL
 
- TDMA_TIER1_ARB_3_QUEUE_EN
 
- TDMA_TIER2_ARB_CTRL
 
- TDMA_TPID
 
- TDMA_TP_OUT_SEL
 
- TDMA_WRITE_PORT_HI
 
- TDMA_WRITE_PORT_LO
 
- TDMA_WRITE_PORT_OFFSET
 
- TDMA_WRITE_PTR
 
- TDMA_WRITE_PTR_HI
 
- TDMC_DBG_SEL
 
- TDMC_DBG_SEL_DBG_SEL
 
- TDMC_INJ_PAR_ERR
 
- TDMC_INJ_PAR_ERR_VAL
 
- TDMC_INTR_DBG
 
- TDMC_INTR_DBG_CONF_PART_ERR
 
- TDMC_INTR_DBG_MBOX_ERR
 
- TDMC_INTR_DBG_MK
 
- TDMC_INTR_DBG_NACK_PKT_RD
 
- TDMC_INTR_DBG_NACK_PREF
 
- TDMC_INTR_DBG_PKT_PART_ERR
 
- TDMC_INTR_DBG_PKT_SIZE_ERR
 
- TDMC_INTR_DBG_PREF_BUF_PAR_ERR
 
- TDMC_INTR_DBG_TX_RING_OFLOW
 
- TDMC_TRAINING_VECTOR
 
- TDMC_TRAINING_VECTOR_VEC
 
- TDMD
 
- TDMD0
 
- TDMD1
 
- TDMD2
 
- TDMD3
 
- TDME_ATM_CONFIG
 
- TDME_CHANNEL
 
- TDME_GETSFR_REQUEST
 
- TDME_SETSFR_CONFIRM
 
- TDME_SETSFR_REQUEST
 
- TDME_SET_REQUEST
 
- TDMIN_CTRL
 
- TDMIN_CTRL_BITNUM
 
- TDMIN_CTRL_BITNUM_MASK
 
- TDMIN_CTRL_ENABLE
 
- TDMIN_CTRL_I2S_MODE
 
- TDMIN_CTRL_IN_BIT_SKEW
 
- TDMIN_CTRL_IN_BIT_SKEW_MASK
 
- TDMIN_CTRL_LSB_FIRST
 
- TDMIN_CTRL_RST_IN
 
- TDMIN_CTRL_RST_OUT
 
- TDMIN_CTRL_SEL_SHIFT
 
- TDMIN_CTRL_WS_INV
 
- TDMIN_MASK0
 
- TDMIN_MASK1
 
- TDMIN_MASK2
 
- TDMIN_MASK3
 
- TDMIN_MUTE0
 
- TDMIN_MUTE1
 
- TDMIN_MUTE2
 
- TDMIN_MUTE3
 
- TDMIN_MUTE_VAL
 
- TDMIN_STAT
 
- TDMIN_SWAP
 
- TDMMAP_HDLC
 
- TDMMAP_UNASSIGNED
 
- TDMMAP_VOICE56K
 
- TDMMAP_VOICE64K
 
- TDMOUT_CTRL0
 
- TDMOUT_CTRL0_BITNUM
 
- TDMOUT_CTRL0_BITNUM_MASK
 
- TDMOUT_CTRL0_ENABLE
 
- TDMOUT_CTRL0_INIT_BITNUM
 
- TDMOUT_CTRL0_INIT_BITNUM_MASK
 
- TDMOUT_CTRL0_RST_IN
 
- TDMOUT_CTRL0_RST_OUT
 
- TDMOUT_CTRL0_SLOTNUM
 
- TDMOUT_CTRL0_SLOTNUM_MASK
 
- TDMOUT_CTRL1
 
- TDMOUT_CTRL1_GAIN_EN
 
- TDMOUT_CTRL1_MSB_POS
 
- TDMOUT_CTRL1_MSB_POS_MASK
 
- TDMOUT_CTRL1_SEL_SHIFT
 
- TDMOUT_CTRL1_TYPE
 
- TDMOUT_CTRL1_TYPE_MASK
 
- TDMOUT_CTRL1_WS_INV
 
- TDMOUT_GAIN0
 
- TDMOUT_GAIN1
 
- TDMOUT_MASK0
 
- TDMOUT_MASK1
 
- TDMOUT_MASK2
 
- TDMOUT_MASK3
 
- TDMOUT_MASK_VAL
 
- TDMOUT_MUTE0
 
- TDMOUT_MUTE1
 
- TDMOUT_MUTE2
 
- TDMOUT_MUTE3
 
- TDMOUT_MUTE_VAL
 
- TDMOUT_STAT
 
- TDMOUT_SWAP
 
- TDMR
 
- TDM_BCK_INV
 
- TDM_BCK_NON_INV
 
- TDM_BCLK_RATE
 
- TDM_CHANNEL_BCK_16
 
- TDM_CHANNEL_BCK_24
 
- TDM_CHANNEL_BCK_32
 
- TDM_CHANNEL_NUM_2
 
- TDM_CHANNEL_NUM_4
 
- TDM_CHANNEL_NUM_8
 
- TDM_CH_START_O30_O31
 
- TDM_CH_START_O32_O33
 
- TDM_CH_START_O34_O35
 
- TDM_CH_START_O36_O37
 
- TDM_CH_ZERO
 
- TDM_DUET
 
- TDM_EN_MASK
 
- TDM_EN_MASK_SFT
 
- TDM_EN_SFT
 
- TDM_EXT
 
- TDM_FIX_VALUE_MASK
 
- TDM_FIX_VALUE_MASK_SFT
 
- TDM_FIX_VALUE_SEL_MASK
 
- TDM_FIX_VALUE_SEL_MASK_SFT
 
- TDM_FIX_VALUE_SEL_SFT
 
- TDM_FIX_VALUE_SFT
 
- TDM_FRAMER_E1
 
- TDM_FRAMER_T1
 
- TDM_I2S_LOOPBACK_CH_MASK
 
- TDM_I2S_LOOPBACK_CH_MASK_SFT
 
- TDM_I2S_LOOPBACK_CH_SFT
 
- TDM_I2S_LOOPBACK_MASK
 
- TDM_I2S_LOOPBACK_MASK_SFT
 
- TDM_I2S_LOOPBACK_SFT
 
- TDM_IFACE_LOOPBACK
 
- TDM_IFACE_PAD
 
- TDM_INTERNAL_LOOPBACK
 
- TDM_KEY
 
- TDM_LCK_INV
 
- TDM_LCK_NON_INV
 
- TDM_NORMAL
 
- TDM_OUT_I2S
 
- TDM_OUT_TDM
 
- TDM_POLO
 
- TDM_PPPOHT_SLIC_MAXIN
 
- TDM_RX_TS
 
- TDM_SPLIT
 
- TDM_TRIAD
 
- TDM_TX_TS
 
- TDM_WLEN_16_BIT
 
- TDM_WLEN_32_BIT
 
- TDNDPR
 
- TDO24M
 
- TDO24M_SPI_BUFF_SIZE
 
- TDO35S
 
- TDO_MARK
 
- TDP_V4_IPHL_MASK
 
- TDR
 
- TDR1
 
- TDR2
 
- TDRE
 
- TDRP
 
- TDRP_ADDR
 
- TDR_ADDR
 
- TDR_ET_OPN
 
- TDR_ET_SRT
 
- TDR_LNK_OK
 
- TDR_MASK_TESTDATA
 
- TDR_SIZE
 
- TDR_TIMEMASK
 
- TDR_XCVR_PRB
 
- TDSAR
 
- TDSELCTRL
 
- TDSK_KEY_SIZE
 
- TDTREQ
 
- TDUE_F
 
- TDUE_S
 
- TDUE_V
 
- TD_AB
 
- TD_AC
 
- TD_ADDR
 
- TD_ADDR_MASK
 
- TD_BOV
 
- TD_BPI
 
- TD_BUFFEROVERRUN
 
- TD_BUFFERUNDERRUN
 
- TD_CC
 
- TD_CC_BITSTUFFING
 
- TD_CC_CRC
 
- TD_CC_DATATOGGLEM
 
- TD_CC_GET
 
- TD_CC_NOERROR
 
- TD_CC_STALL
 
- TD_CGTT_CTRL__OFF_HYSTERESIS_MASK
 
- TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT
 
- TD_CGTT_CTRL__ON_DELAY_MASK
 
- TD_CGTT_CTRL__ON_DELAY__SHIFT
 
- TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK
 
- TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT
 
- TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK
 
- TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT
 
- TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK
 
- TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT
 
- TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK
 
- TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT
 
- TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK
 
- TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT
 
- TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK
 
- TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT
 
- TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK
 
- TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT
 
- TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK
 
- TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT
 
- TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0_MASK
 
- TD_CGTT_CTRL__SOFT_STALL_OVERRIDE0__SHIFT
 
- TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1_MASK
 
- TD_CGTT_CTRL__SOFT_STALL_OVERRIDE1__SHIFT
 
- TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2_MASK
 
- TD_CGTT_CTRL__SOFT_STALL_OVERRIDE2__SHIFT
 
- TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3_MASK
 
- TD_CGTT_CTRL__SOFT_STALL_OVERRIDE3__SHIFT
 
- TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4_MASK
 
- TD_CGTT_CTRL__SOFT_STALL_OVERRIDE4__SHIFT
 
- TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5_MASK
 
- TD_CGTT_CTRL__SOFT_STALL_OVERRIDE5__SHIFT
 
- TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6_MASK
 
- TD_CGTT_CTRL__SOFT_STALL_OVERRIDE6__SHIFT
 
- TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7_MASK
 
- TD_CGTT_CTRL__SOFT_STALL_OVERRIDE7__SHIFT
 
- TD_CNF
 
- TD_CNTL__ARBITER_OLDEST_PRIORITY_MASK
 
- TD_CNTL__ARBITER_OLDEST_PRIORITY__SHIFT
 
- TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK
 
- TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT
 
- TD_CNTL__DISABLE_D16_PACKING_MASK
 
- TD_CNTL__DISABLE_D16_PACKING__SHIFT
 
- TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT_MASK
 
- TD_CNTL__DISABLE_MM_QNAN_COMPARE_RESULT__SHIFT
 
- TD_CNTL__DISABLE_POWER_THROTTLE_MASK
 
- TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT
 
- TD_CNTL__DISABLE_ROUND_TO_ZERO_FOR_LARGE_FLOAT_TO_SMALL_FLOAT_MASK
 
- TD_CNTL__DISABLE_ROUND_TO_ZERO_FOR_LARGE_FLOAT_TO_SMALL_FLOAT__SHIFT
 
- TD_CNTL__DISABLE_SAMPLER_MAX_NORM_NUM_CLAMP_MASK
 
- TD_CNTL__DISABLE_SAMPLER_MAX_NORM_NUM_CLAMP__SHIFT
 
- TD_CNTL__DISABLE_SAMPLER_NEG_SCALED_NUM_CLAMP_MASK
 
- TD_CNTL__DISABLE_SAMPLER_NEG_SCALED_NUM_CLAMP__SHIFT
 
- TD_CNTL__DONE_SCOREBOARD_DEPTH_MASK
 
- TD_CNTL__DONE_SCOREBOARD_DEPTH__SHIFT
 
- TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK
 
- TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT
 
- TD_CNTL__EXTEND_LDS_STALL_MASK
 
- TD_CNTL__EXTEND_LDS_STALL__SHIFT
 
- TD_CNTL__GATHER4_DX9_MODE_MASK
 
- TD_CNTL__GATHER4_DX9_MODE__SHIFT
 
- TD_CNTL__GATHER4_FLOAT_MODE_MASK
 
- TD_CNTL__GATHER4_FLOAT_MODE__SHIFT
 
- TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK
 
- TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT
 
- TD_CNTL__LD_FLOAT_MODE_MASK
 
- TD_CNTL__LD_FLOAT_MODE__SHIFT
 
- TD_CNTL__PAD_STALL_EN_MASK
 
- TD_CNTL__PAD_STALL_EN__SHIFT
 
- TD_CNTL__PRECISION_COMPATIBILITY_MASK
 
- TD_CNTL__PRECISION_COMPATIBILITY__SHIFT
 
- TD_CNTL__SYNC_PHASE_SH_MASK
 
- TD_CNTL__SYNC_PHASE_SH__SHIFT
 
- TD_CNTL__SYNC_PHASE_VC_SMX_MASK
 
- TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT
 
- TD_COMMAND
 
- TD_CR
 
- TD_CS_BORDER_COLOR_ALPHA
 
- TD_CS_BORDER_COLOR_BLUE
 
- TD_CS_BORDER_COLOR_GREEN
 
- TD_CS_BORDER_COLOR_INDEX
 
- TD_CS_BORDER_COLOR_RED
 
- TD_CTRL_ACTIVE
 
- TD_CTRL_ACTLEN_MASK
 
- TD_CTRL_BABBLE
 
- TD_CTRL_BITSTUFF
 
- TD_CTRL_CRCTIMEO
 
- TD_CTRL_C_ERR_MASK
 
- TD_CTRL_C_ERR_SHIFT
 
- TD_CTRL_DBUFERR
 
- TD_CTRL_IOC
 
- TD_CTRL_IOS
 
- TD_CTRL_LS
 
- TD_CTRL_NAK
 
- TD_CTRL_SPD
 
- TD_CTRL_STALLED
 
- TD_CURR_OFFSET
 
- TD_C_DESCR
 
- TD_C_LNCN
 
- TD_C_LNCNL
 
- TD_C_LNCNU
 
- TD_C_MORE
 
- TD_C_NFCS
 
- TD_C_TXFBB
 
- TD_C_XDONE
 
- TD_C_XMTABT
 
- TD_DATA
 
- TD_DATAOVERRUN
 
- TD_DATAUNDERRUN
 
- TD_DE
 
- TD_DEBUG_DATA__DATA_MASK
 
- TD_DEBUG_DATA__DATA__SHIFT
 
- TD_DEBUG_INDEX__INDEX_MASK
 
- TD_DEBUG_INDEX__INDEX__SHIFT
 
- TD_DESC_DMA_NUM
 
- TD_DESC_IS_RX
 
- TD_DEVNOTRESP
 
- TD_DI
 
- TD_DIR_IN
 
- TD_DIR_OUT
 
- TD_DIR_SETUP
 
- TD_DI_SET
 
- TD_DM_DRVN
 
- TD_DM_DRVP
 
- TD_DONE
 
- TD_DP
 
- TD_DPD
 
- TD_DP_IN
 
- TD_DP_OUT
 
- TD_DP_SETUP
 
- TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT_MASK
 
- TD_DSM_CNTL2__TD_CS_FIFO_ENABLE_ERROR_INJECT__SHIFT
 
- TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY_MASK
 
- TD_DSM_CNTL2__TD_CS_FIFO_SELECT_INJECT_DELAY__SHIFT
 
- TD_DSM_CNTL2__TD_INJECT_DELAY_MASK
 
- TD_DSM_CNTL2__TD_INJECT_DELAY__SHIFT
 
- TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT_MASK
 
- TD_DSM_CNTL2__TD_SS_FIFO_HI_ENABLE_ERROR_INJECT__SHIFT
 
- TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY_MASK
 
- TD_DSM_CNTL2__TD_SS_FIFO_HI_SELECT_INJECT_DELAY__SHIFT
 
- TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT_MASK
 
- TD_DSM_CNTL2__TD_SS_FIFO_LO_ENABLE_ERROR_INJECT__SHIFT
 
- TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY_MASK
 
- TD_DSM_CNTL2__TD_SS_FIFO_LO_SELECT_INJECT_DELAY__SHIFT
 
- TD_DSM_CNTL__EN_SINGLE_WR_SEDB_MASK
 
- TD_DSM_CNTL__EN_SINGLE_WR_SEDB__SHIFT
 
- TD_DSM_CNTL__FORCE_SEDB_0_MASK
 
- TD_DSM_CNTL__FORCE_SEDB_0__SHIFT
 
- TD_DSM_CNTL__FORCE_SEDB_1_MASK
 
- TD_DSM_CNTL__FORCE_SEDB_1__SHIFT
 
- TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA_MASK
 
- TD_DSM_CNTL__TD_CS_FIFO_DSM_IRRITATOR_DATA__SHIFT
 
- TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE_MASK
 
- TD_DSM_CNTL__TD_CS_FIFO_ENABLE_SINGLE_WRITE__SHIFT
 
- TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA_MASK
 
- TD_DSM_CNTL__TD_SS_FIFO_HI_DSM_IRRITATOR_DATA__SHIFT
 
- TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE_MASK
 
- TD_DSM_CNTL__TD_SS_FIFO_HI_ENABLE_SINGLE_WRITE__SHIFT
 
- TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA_MASK
 
- TD_DSM_CNTL__TD_SS_FIFO_LO_DSM_IRRITATOR_DATA__SHIFT
 
- TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE_MASK
 
- TD_DSM_CNTL__TD_SS_FIFO_LO_ENABLE_SINGLE_WRITE__SHIFT
 
- TD_EC
 
- TD_EDC_CNT__CS_FIFO_SED_COUNT_MASK
 
- TD_EDC_CNT__CS_FIFO_SED_COUNT__SHIFT
 
- TD_EDC_CNT__SS_FIFO_HI_DED_COUNT_MASK
 
- TD_EDC_CNT__SS_FIFO_HI_DED_COUNT__SHIFT
 
- TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT_MASK
 
- TD_EDC_CNT__SS_FIFO_HI_SEC_COUNT__SHIFT
 
- TD_EDC_CNT__SS_FIFO_LO_DED_COUNT_MASK
 
- TD_EDC_CNT__SS_FIFO_LO_DED_COUNT__SHIFT
 
- TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT_MASK
 
- TD_EDC_CNT__SS_FIFO_LO_SEC_COUNT__SHIFT
 
- TD_EDC_MASK
 
- TD_EDC_SHIFT
 
- TD_ENDP
 
- TD_ENDP_SHIFT
 
- TD_EPI
 
- TD_ERRORS
 
- TD_ERROR_MASK
 
- TD_ES
 
- TD_Enable_MASK
 
- TD_Enable_SHIFT
 
- TD_FLAGS_NETIF_SKB
 
- TD_FLAGS_PRIV_SKB
 
- TD_FLAGS_PS_RETRY
 
- TD_FORMAT_BULK
 
- TD_FORMAT_CONTROL
 
- TD_FORMAT_INT
 
- TD_FORMAT_ISO
 
- TD_FRAME_NUM
 
- TD_FS
 
- TD_FT0
 
- TD_FT1
 
- TD_GS_BORDER_COLOR_ALPHA
 
- TD_GS_BORDER_COLOR_BLUE
 
- TD_GS_BORDER_COLOR_GREEN
 
- TD_GS_BORDER_COLOR_INDEX
 
- TD_GS_BORDER_COLOR_RED
 
- TD_HASH_FUNC
 
- TD_HASH_SIZE
 
- TD_HF
 
- TD_HS_BORDER_COLOR_ALPHA
 
- TD_HS_BORDER_COLOR_BLUE
 
- TD_HS_BORDER_COLOR_GREEN
 
- TD_HS_BORDER_COLOR_INDEX
 
- TD_HS_BORDER_COLOR_RED
 
- TD_I
 
- TD_IC
 
- TD_IOC
 
- TD_IR_MASK
 
- TD_IR_SHIFT
 
- TD_ISO
 
- TD_L
 
- TD_LC
 
- TD_LEN_BIT
 
- TD_LF
 
- TD_LO
 
- TD_LS
 
- TD_LSO
 
- TD_LSP
 
- TD_LS_BORDER_COLOR_ALPHA
 
- TD_LS_BORDER_COLOR_BLUE
 
- TD_LS_BORDER_COLOR_GREEN
 
- TD_LS_BORDER_COLOR_INDEX
 
- TD_LS_BORDER_COLOR_RED
 
- TD_MASK
 
- TD_MSS_MAX
 
- TD_MULTO
 
- TD_NAK
 
- TD_NC
 
- TD_NO
 
- TD_NOTACCESSED
 
- TD_OAM_CELL
 
- TD_OAM_CELL_SEGMENT
 
- TD_OV
 
- TD_PAGE_COUNT
 
- TD_PCC_MASK
 
- TD_PCC_SHIFT
 
- TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK
 
- TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT
 
- TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK
 
- TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT
 
- TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK
 
- TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT
 
- TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK
 
- TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT
 
- TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK
 
- TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT
 
- TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK
 
- TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT
 
- TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK
 
- TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT
 
- TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK
 
- TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT
 
- TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK
 
- TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT
 
- TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK
 
- TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT
 
- TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK
 
- TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT
 
- TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK
 
- TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT
 
- TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK
 
- TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT
 
- TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK
 
- TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT
 
- TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK
 
- TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT
 
- TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK
 
- TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT
 
- TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK
 
- TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT
 
- TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK
 
- TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT
 
- TD_PERFCOUNT_SEL
 
- TD_PERF_SEL_RESERVED_14
 
- TD_PERF_SEL_RESERVED_18
 
- TD_PERF_SEL_RESERVED_19
 
- TD_PERF_SEL_RESERVED_21
 
- TD_PERF_SEL_RESERVED_26
 
- TD_PERF_SEL_RESERVED_27
 
- TD_PERF_SEL_RESERVED_28
 
- TD_PERF_SEL_RESERVED_29
 
- TD_PERF_SEL_RESERVED_39
 
- TD_PERF_SEL_RESERVED_4
 
- TD_PERF_SEL_RESERVED_43
 
- TD_PERF_SEL_RESERVED_44
 
- TD_PERF_SEL_RESERVED_8
 
- TD_PERF_SEL_address_cmd_poison
 
- TD_PERF_SEL_addresscmd_poison
 
- TD_PERF_SEL_atomic_wavefront
 
- TD_PERF_SEL_bicubic_filter_wavefront
 
- TD_PERF_SEL_bypassLerp_wavefront
 
- TD_PERF_SEL_bypass_filter_wavefront
 
- TD_PERF_SEL_coalescable_wavefront
 
- TD_PERF_SEL_coalesced_phase
 
- TD_PERF_SEL_constant_state_full
 
- TD_PERF_SEL_consume_gds_traffic
 
- TD_PERF_SEL_core_state_rams_read
 
- TD_PERF_SEL_d16_data_packed
 
- TD_PERF_SEL_d16_en_wavefront
 
- TD_PERF_SEL_data_poison
 
- TD_PERF_SEL_done_scoreboard_bp_due_to_lds
 
- TD_PERF_SEL_done_scoreboard_bp_due_to_ooo
 
- TD_PERF_SEL_done_scoreboard_is_full
 
- TD_PERF_SEL_done_scoreboard_not_empty
 
- TD_PERF_SEL_eight_phase_wavefront
 
- TD_PERF_SEL_four_comp_wavefront
 
- TD_PERF_SEL_four_phase_forward_wavefront
 
- TD_PERF_SEL_four_phase_wavefront
 
- TD_PERF_SEL_gather4_wavefront
 
- TD_PERF_SEL_gather4h_packed_wavefront
 
- TD_PERF_SEL_gather4h_wavefront
 
- TD_PERF_SEL_gather8h_packed_wavefront
 
- TD_PERF_SEL_gds_stall
 
- TD_PERF_SEL_input_busy
 
- TD_PERF_SEL_input_state_fifo_full
 
- TD_PERF_SEL_ldfptr_wavefront
 
- TD_PERF_SEL_lds_stall
 
- TD_PERF_SEL_lerp_busy
 
- TD_PERF_SEL_load_wavefront
 
- TD_PERF_SEL_local_cg_dyn_sclk_grp0_en
 
- TD_PERF_SEL_local_cg_dyn_sclk_grp1_en
 
- TD_PERF_SEL_local_cg_dyn_sclk_grp4_en
 
- TD_PERF_SEL_local_cg_dyn_sclk_grp5_en
 
- TD_PERF_SEL_lod_warn_from_ta
 
- TD_PERF_SEL_min_max_filter_wavefront
 
- TD_PERF_SEL_mixmode_instruction
 
- TD_PERF_SEL_mixmode_resource
 
- TD_PERF_SEL_nack
 
- TD_PERF_SEL_nofilter_busy
 
- TD_PERF_SEL_nofilter_formatters_turned_off
 
- TD_PERF_SEL_nofilter_pkr_full
 
- TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt
 
- TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt
 
- TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off
 
- TD_PERF_SEL_none
 
- TD_PERF_SEL_null_cycle_output
 
- TD_PERF_SEL_one_comp_wavefront
 
- TD_PERF_SEL_opaque_black_border
 
- TD_PERF_SEL_out_of_order_instr
 
- TD_PERF_SEL_output_busy
 
- TD_PERF_SEL_output_fifo_full
 
- TD_PERF_SEL_pc_stall
 
- TD_PERF_SEL_reference_data_rams_read
 
- TD_PERF_SEL_reg_sclk_vld
 
- TD_PERF_SEL_sample_c_wavefront
 
- TD_PERF_SEL_sample_state_full
 
- TD_PERF_SEL_sampler_lerp_busy
 
- TD_PERF_SEL_sampler_out_busy
 
- TD_PERF_SEL_sampler_pkr_full
 
- TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off
 
- TD_PERF_SEL_sixteen_phase_wavefront
 
- TD_PERF_SEL_start_cycle_0
 
- TD_PERF_SEL_start_cycle_1
 
- TD_PERF_SEL_start_cycle_2
 
- TD_PERF_SEL_start_cycle_3
 
- TD_PERF_SEL_status_packet
 
- TD_PERF_SEL_store_wavefront
 
- TD_PERF_SEL_ta_data_stall
 
- TD_PERF_SEL_tc_cycling_of_nofilter_instr
 
- TD_PERF_SEL_tc_data_stall
 
- TD_PERF_SEL_tc_ram_stall
 
- TD_PERF_SEL_tc_stall
 
- TD_PERF_SEL_tc_td_data_fifo_full
 
- TD_PERF_SEL_tc_td_fifo_full
 
- TD_PERF_SEL_tc_td_ram_fifo_full
 
- TD_PERF_SEL_td_busy
 
- TD_PERF_SEL_td_cycling_of_nofilter_instr
 
- TD_PERF_SEL_td_sp_traffic
 
- TD_PERF_SEL_texels_zeroed_out_by_blend_zero_prt
 
- TD_PERF_SEL_three_comp_wavefront
 
- TD_PERF_SEL_total_num_instr
 
- TD_PERF_SEL_two_comp_wavefront
 
- TD_PERF_SEL_user_defined_border
 
- TD_PERF_SEL_wavefront_dest_is_lds
 
- TD_PERF_SEL_weight_data_rams_read
 
- TD_PERF_SEL_white_border
 
- TD_PERF_SEL_write_ack_wavefront
 
- TD_PID
 
- TD_PIDCHECKFAIL
 
- TD_PIDEPMASK_EP
 
- TD_PIDEPMASK_PID
 
- TD_PIDEP_OFFSET
 
- TD_PID_DATA0
 
- TD_PID_DATA1
 
- TD_PID_IN
 
- TD_PID_TOGGLE
 
- TD_PORTLENMASK_DL
 
- TD_PORTLENMASK_PN
 
- TD_POWER_CNTL__DISABLE_NOFILTER_FORMATTER_POWER_OPT_MASK
 
- TD_POWER_CNTL__DISABLE_NOFILTER_FORMATTER_POWER_OPT__SHIFT
 
- TD_POWER_CNTL__FORCE_NOFILTER_CLK_TO_CORE_MASK
 
- TD_POWER_CNTL__FORCE_NOFILTER_CLK_TO_CORE__SHIFT
 
- TD_POWER_CNTL__FORCE_NOFILTER_D16_FORMATTERS_ON_MASK
 
- TD_POWER_CNTL__FORCE_NOFILTER_D16_FORMATTERS_ON__SHIFT
 
- TD_POWER_CNTL__FORCE_SAMPLER_CLK_TO_CORE_MASK
 
- TD_POWER_CNTL__FORCE_SAMPLER_CLK_TO_CORE__SHIFT
 
- TD_POWER_CNTL__NOFILTER_CLK_VALID_DELAY_MASK
 
- TD_POWER_CNTL__NOFILTER_CLK_VALID_DELAY__SHIFT
 
- TD_POWER_CNTL__SAMPLER_CLK_VALID_DELAY_MASK
 
- TD_POWER_CNTL__SAMPLER_CLK_VALID_DELAY__SHIFT
 
- TD_PS_BORDER_COLOR_ALPHA
 
- TD_PS_BORDER_COLOR_BLUE
 
- TD_PS_BORDER_COLOR_GREEN
 
- TD_PS_BORDER_COLOR_INDEX
 
- TD_PS_BORDER_COLOR_RED
 
- TD_P_CNTRL
 
- TD_P_RPX
 
- TD_P_RPXL
 
- TD_P_RPXU
 
- TD_QUEUE
 
- TD_R
 
- TD_RESERVED_MASK
 
- TD_RESIDUE_OVERFLOW
 
- TD_RETRYCNTMASK_ACT_FLG
 
- TD_RETRYCNTMASK_RTY_CNT
 
- TD_RETRYCNTMASK_TX_TYPE
 
- TD_RETRYCNT_OFFSET
 
- TD_RING_SIZE
 
- TD_RM_CELL
 
- TD_RXER
 
- TD_SCHEDULEOVERRUN
 
- TD_SCRATCH__SCRATCH_MASK
 
- TD_SCRATCH__SCRATCH__SHIFT
 
- TD_SET
 
- TD_STAL
 
- TD_STATUS
 
- TD_STATUSMASK_ACK
 
- TD_STATUSMASK_ERR
 
- TD_STATUSMASK_NAK
 
- TD_STATUSMASK_OVF
 
- TD_STATUSMASK_SEQ
 
- TD_STATUSMASK_SETUP
 
- TD_STATUSMASK_STALL
 
- TD_STATUSMASK_TMOUT
 
- TD_STATUS_ACTIVE
 
- TD_STATUS_DT_ERR
 
- TD_STATUS_HALTED
 
- TD_STATUS_OFFSET
 
- TD_STATUS_TR_ERR
 
- TD_STATUS__BUSY_MASK
 
- TD_STATUS__BUSY__SHIFT
 
- TD_STS_BIT
 
- TD_T
 
- TD_TACT
 
- TD_TBL
 
- TD_TBS1
 
- TD_TBS2
 
- TD_TC
 
- TD_TCH
 
- TD_TDLE
 
- TD_TER
 
- TD_TERMINATE
 
- TD_TFE
 
- TD_TFP
 
- TD_TFP0
 
- TD_TFP1
 
- TD_TO
 
- TD_TOGGLE_CARRY
 
- TD_TOGGLE_DATA0
 
- TD_TOGGLE_DATA1
 
- TD_TOKEN_DEVADDR_SHIFT
 
- TD_TOKEN_EXPLEN_MASK
 
- TD_TOKEN_EXPLEN_SHIFT
 
- TD_TOKEN_PID_MASK
 
- TD_TOKEN_TOGGLE
 
- TD_TOKEN_TOGGLE_SHIFT
 
- TD_TOK_IN
 
- TD_TOK_OUT
 
- TD_TOK_SETUP
 
- TD_TOTAL_BYTES
 
- TD_TWBI
 
- TD_T_DATA0
 
- TD_T_DATA1
 
- TD_T_TOGGLE
 
- TD_UF
 
- TD_UN
 
- TD_UNEXPECTEDPID
 
- TD_VS_BORDER_COLOR_ALPHA
 
- TD_VS_BORDER_COLOR_BLUE
 
- TD_VS_BORDER_COLOR_GREEN
 
- TD_VS_BORDER_COLOR_INDEX
 
- TD_VS_BORDER_COLOR_RED
 
- TD_W
 
- TE
 
- TE0
 
- TE0_TEMPERATURE_READ_ADDR__CSR_ADDR_MASK
 
- TE0_TEMPERATURE_READ_ADDR__CSR_ADDR__SHIFT
 
- TE0_TEMPERATURE_READ_ADDR__RESERVED_MASK
 
- TE0_TEMPERATURE_READ_ADDR__RESERVED__SHIFT
 
- TE0_TEMPERATURE_READ_ADDR__TCEN_ID_MASK
 
- TE0_TEMPERATURE_READ_ADDR__TCEN_ID__SHIFT
 
- TE1
 
- TE1_ALMA
 
- TE1_TEMPERATURE_READ_ADDR__CSR_ADDR_MASK
 
- TE1_TEMPERATURE_READ_ADDR__CSR_ADDR__SHIFT
 
- TE1_TEMPERATURE_READ_ADDR__RESERVED_MASK
 
- TE1_TEMPERATURE_READ_ADDR__RESERVED__SHIFT
 
- TE1_TEMPERATURE_READ_ADDR__TCEN_ID_MASK
 
- TE1_TEMPERATURE_READ_ADDR__TCEN_ID__SHIFT
 
- TE2
 
- TE2_TEMPERATURE_READ_ADDR__CSR_ADDR_MASK
 
- TE2_TEMPERATURE_READ_ADDR__CSR_ADDR__SHIFT
 
- TE2_TEMPERATURE_READ_ADDR__RESERVED_MASK
 
- TE2_TEMPERATURE_READ_ADDR__RESERVED__SHIFT
 
- TE2_TEMPERATURE_READ_ADDR__TCEN_ID_MASK
 
- TE2_TEMPERATURE_READ_ADDR__TCEN_ID__SHIFT
 
- TE3
 
- TE4
 
- TE41
 
- TE414
 
- TE42
 
- TE421
 
- TE43
 
- TE432
 
- TE44
 
- TE443
 
- TEA
 
- TEA575X_AMIF
 
- TEA575X_BIT_BAND_FM
 
- TEA575X_BIT_BAND_LW
 
- TEA575X_BIT_BAND_MASK
 
- TEA575X_BIT_BAND_MW
 
- TEA575X_BIT_BAND_SW
 
- TEA575X_BIT_DUMMY
 
- TEA575X_BIT_FREQ_MASK
 
- TEA575X_BIT_MONO
 
- TEA575X_BIT_PORT_0
 
- TEA575X_BIT_PORT_1
 
- TEA575X_BIT_SEARCH
 
- TEA575X_BIT_SEARCH_10_40
 
- TEA575X_BIT_SEARCH_150_1000
 
- TEA575X_BIT_SEARCH_30_63
 
- TEA575X_BIT_SEARCH_5_28
 
- TEA575X_BIT_SEARCH_MASK
 
- TEA575X_BIT_UPDOWN
 
- TEA575X_CLK
 
- TEA575X_DATA
 
- TEA575X_FMIF
 
- TEA575X_MOST
 
- TEA575X_WREN
 
- TEA5761_FRQSET_SEARCH_MODE
 
- TEA5761_FRQSET_SEARCH_UP
 
- TEA5761_INTREG_BLFLAG
 
- TEA5761_INTREG_BLMSK
 
- TEA5761_INTREG_FRMSK
 
- TEA5761_INTREG_FRRFLAG
 
- TEA5761_INTREG_IFFLAG
 
- TEA5761_INTREG_IFMSK
 
- TEA5761_INTREG_LEVFLAG
 
- TEA5761_INTREG_LEVMSK
 
- TEA5761_TNCTRL_AFM
 
- TEA5761_TNCTRL_AHLSI
 
- TEA5761_TNCTRL_BLIM
 
- TEA5761_TNCTRL_DTC
 
- TEA5761_TNCTRL_HLSI
 
- TEA5761_TNCTRL_IFCTC
 
- TEA5761_TNCTRL_MST
 
- TEA5761_TNCTRL_MU
 
- TEA5761_TNCTRL_PUPD_0
 
- TEA5761_TNCTRL_SMUTE
 
- TEA5761_TNCTRL_SNC
 
- TEA5761_TNCTRL_SSL_0
 
- TEA5761_TNCTRL_SSL_1
 
- TEA5761_TNCTRL_SWP
 
- TEA5761_TNCTRL_SWPM
 
- TEA5761_TUNCHECK_IF_MASK
 
- TEA5761_TUNCHECK_LD
 
- TEA5761_TUNCHECK_LEV_MASK
 
- TEA5761_TUNCHECK_STEREO
 
- TEA5761_TUNCHECK_TUNTO
 
- TEA5764_CHIPID
 
- TEA5764_FRQSET_SM
 
- TEA5764_FRQSET_SUD
 
- TEA5764_INTREG_BLMFLAG
 
- TEA5764_INTREG_BLMSK
 
- TEA5764_INTREG_FRRFLAG
 
- TEA5764_INTREG_FRRMSK
 
- TEA5764_INTREG_IFFLAG
 
- TEA5764_INTREG_IFMSK
 
- TEA5764_INTREG_LEVFLAG
 
- TEA5764_INTREG_LEVMSK
 
- TEA5764_MANID
 
- TEA5764_TESTREG_TRIGFR
 
- TEA5764_TNCTRL_AFM
 
- TEA5764_TNCTRL_AHLSI
 
- TEA5764_TNCTRL_BLIM
 
- TEA5764_TNCTRL_DTC
 
- TEA5764_TNCTRL_HLSI
 
- TEA5764_TNCTRL_IFCTC
 
- TEA5764_TNCTRL_MST
 
- TEA5764_TNCTRL_MU
 
- TEA5764_TNCTRL_PUPD0
 
- TEA5764_TNCTRL_PUPD1
 
- TEA5764_TNCTRL_SMUTE
 
- TEA5764_TNCTRL_SNC
 
- TEA5764_TNCTRL_SSL0
 
- TEA5764_TNCTRL_SSL1
 
- TEA5764_TNCTRL_SWP
 
- TEA5764_TNCTRL_SWPM
 
- TEA5764_TUNCHK_IFCNT
 
- TEA5764_TUNCHK_LD
 
- TEA5764_TUNCHK_LEVEL
 
- TEA5764_TUNCHK_STEREO
 
- TEA5764_TUNCHK_TUNTO
 
- TEA5767_ADC_LEVEL_MASK
 
- TEA5767_BAND_LIMIT_MASK
 
- TEA5767_CHIP_ID_MASK
 
- TEA5767_DEEMPH_75
 
- TEA5767_HIGH_CUT_CTRL
 
- TEA5767_HIGH_LO_13MHz
 
- TEA5767_HIGH_LO_32768
 
- TEA5767_HIGH_LO_INJECT
 
- TEA5767_IF_CNTR_MASK
 
- TEA5767_JAPAN_BAND
 
- TEA5767_LOW_LO_13MHz
 
- TEA5767_LOW_LO_32768
 
- TEA5767_MANID_IDAV
 
- TEA5767_MANID_ID_LSB_MASK
 
- TEA5767_MANID_ID_MSB_MASK
 
- TEA5767_MANID_VERSION_MASK
 
- TEA5767_MONO
 
- TEA5767_MUTE
 
- TEA5767_MUTE_LEFT
 
- TEA5767_MUTE_RIGHT
 
- TEA5767_PLLREF_ENABLE
 
- TEA5767_PORT1_HIGH
 
- TEA5767_PORT2_HIGH
 
- TEA5767_READY_FLAG_MASK
 
- TEA5767_RESERVED_MASK
 
- TEA5767_SEARCH
 
- TEA5767_SEARCH_UP
 
- TEA5767_SOFT_MUTE
 
- TEA5767_SRCH_HIGH_LVL
 
- TEA5767_SRCH_IND
 
- TEA5767_SRCH_LOW_LVL
 
- TEA5767_SRCH_MID_LVL
 
- TEA5767_STDBY
 
- TEA5767_STEREO_MASK
 
- TEA5767_ST_NOISE_CTL
 
- TEA5767_XTAL_32768
 
- TEA5777_AM_FREQ_STEP
 
- TEA5777_AM_IF
 
- TEA5777_FM_FREQ_STEP
 
- TEA5777_FM_IF
 
- TEA5777_R_BLIM_MASK
 
- TEA5777_R_BLIM_SHIFT
 
- TEA5777_R_FM_PLL_MASK
 
- TEA5777_R_FM_PLL_SHIFT
 
- TEA5777_R_FM_STEREO_MASK
 
- TEA5777_R_FM_STEREO_SHIFT
 
- TEA5777_R_LEVEL_MASK
 
- TEA5777_R_LEVEL_SHIFT
 
- TEA5777_R_SFOUND_MASK
 
- TEA5777_R_SFOUND_SHIFT
 
- TEA5777_W_AM_AGCIF_MASK
 
- TEA5777_W_AM_AGCIF_SHIFT
 
- TEA5777_W_AM_AGCRF_MASK
 
- TEA5777_W_AM_AGCRF_SHIFT
 
- TEA5777_W_AM_CALLIGN_MASK
 
- TEA5777_W_AM_CALLIGN_SHIFT
 
- TEA5777_W_AM_CBANK_MASK
 
- TEA5777_W_AM_CBANK_SHIFT
 
- TEA5777_W_AM_DELAY_MASK
 
- TEA5777_W_AM_DELAY_SHIFT
 
- TEA5777_W_AM_FM_MASK
 
- TEA5777_W_AM_FM_SHIFT
 
- TEA5777_W_AM_LNA_MASK
 
- TEA5777_W_AM_LNA_SHIFT
 
- TEA5777_W_AM_LW
 
- TEA5777_W_AM_MW
 
- TEA5777_W_AM_MWLW_MASK
 
- TEA5777_W_AM_MWLW_SHIFT
 
- TEA5777_W_AM_PEAK_MASK
 
- TEA5777_W_AM_PEAK_SHIFT
 
- TEA5777_W_AM_PLL_MASK
 
- TEA5777_W_AM_PLL_SHIFT
 
- TEA5777_W_AM_RFB_MASK
 
- TEA5777_W_AM_RFB_SHIFT
 
- TEA5777_W_AM_STEP_MASK
 
- TEA5777_W_AM_STEP_SHIFT
 
- TEA5777_W_CHP0_MASK
 
- TEA5777_W_CHP0_SHIFT
 
- TEA5777_W_DBUS_MASK
 
- TEA5777_W_DBUS_SHIFT
 
- TEA5777_W_DEEM_MASK
 
- TEA5777_W_DEEM_SHIFT
 
- TEA5777_W_FM_DOFF_MASK
 
- TEA5777_W_FM_DOFF_SHIFT
 
- TEA5777_W_FM_FORCEMONO_MASK
 
- TEA5777_W_FM_FORCEMONO_SHIFT
 
- TEA5777_W_FM_FREF_MASK
 
- TEA5777_W_FM_FREF_SHIFT
 
- TEA5777_W_FM_FREF_VALUE
 
- TEA5777_W_FM_PLL_MASK
 
- TEA5777_W_FM_PLL_SHIFT
 
- TEA5777_W_FM_SDSOFF_MASK
 
- TEA5777_W_FM_SDSOFF_SHIFT
 
- TEA5777_W_FM_STEP_MASK
 
- TEA5777_W_FM_STEP_SHIFT
 
- TEA5777_W_HILO_MASK
 
- TEA5777_W_HILO_SHIFT
 
- TEA5777_W_IFCE_MASK
 
- TEA5777_W_IFCE_SHIFT
 
- TEA5777_W_IFW_MASK
 
- TEA5777_W_IFW_SHIFT
 
- TEA5777_W_INTEXT_MASK
 
- TEA5777_W_INTEXT_SHIFT
 
- TEA5777_W_MUTE_MASK
 
- TEA5777_W_MUTE_SHIFT
 
- TEA5777_W_P0_MASK
 
- TEA5777_W_P0_SHIFT
 
- TEA5777_W_P1_MASK
 
- TEA5777_W_P1_SHIFT
 
- TEA5777_W_PEN0_MASK
 
- TEA5777_W_PEN0_SHIFT
 
- TEA5777_W_PEN1_MASK
 
- TEA5777_W_PEN1_SHIFT
 
- TEA5777_W_PROGBLIM_MASK
 
- TEA5777_W_PROGBLIM_SHIFT
 
- TEA5777_W_SEARCH_MASK
 
- TEA5777_W_SEARCH_SHIFT
 
- TEA5777_W_SLEV_MASK
 
- TEA5777_W_SLEV_SHIFT
 
- TEA5777_W_STB_MASK
 
- TEA5777_W_STB_SHIFT
 
- TEA5777_W_UPDWN_MASK
 
- TEA5777_W_UPDWN_SHIFT
 
- TEA6300_BA
 
- TEA6300_FA
 
- TEA6300_S
 
- TEA6300_S_GMU
 
- TEA6300_S_SA
 
- TEA6300_S_SB
 
- TEA6300_S_SC
 
- TEA6300_TR
 
- TEA6300_VL
 
- TEA6300_VR
 
- TEA6320_BA
 
- TEA6320_FFL
 
- TEA6320_FFR
 
- TEA6320_FRL
 
- TEA6320_FRR
 
- TEA6320_S
 
- TEA6320_S_GMU
 
- TEA6320_S_SA
 
- TEA6320_S_SB
 
- TEA6320_S_SC
 
- TEA6320_S_SD
 
- TEA6320_TR
 
- TEA6320_V
 
- TEA6330T_ADDR
 
- TEA6330T_BASS
 
- TEA6330T_EQN
 
- TEA6330T_FCH
 
- TEA6330T_GMU
 
- TEA6330T_MASTER_SWITCH
 
- TEA6330T_MASTER_VOLUME
 
- TEA6330T_MFN
 
- TEA6330T_SADDR_AUDIO_SWITCH
 
- TEA6330T_SADDR_BASS
 
- TEA6330T_SADDR_FADER
 
- TEA6330T_SADDR_TREBLE
 
- TEA6330T_SADDR_VOLUME_LEFT
 
- TEA6330T_SADDR_VOLUME_RIGHT
 
- TEA6330T_TREBLE
 
- TEA6415C_INPUT1
 
- TEA6415C_INPUT2
 
- TEA6415C_INPUT3
 
- TEA6415C_INPUT4
 
- TEA6415C_INPUT5
 
- TEA6415C_INPUT6
 
- TEA6415C_INPUT7
 
- TEA6415C_INPUT8
 
- TEA6415C_OUTPUT1
 
- TEA6415C_OUTPUT2
 
- TEA6415C_OUTPUT3
 
- TEA6415C_OUTPUT4
 
- TEA6415C_OUTPUT5
 
- TEA6415C_OUTPUT6
 
- TEA6420_GAIN0
 
- TEA6420_GAIN2
 
- TEA6420_GAIN4
 
- TEA6420_GAIN6
 
- TEA6420_INPUT1
 
- TEA6420_INPUT2
 
- TEA6420_INPUT3
 
- TEA6420_INPUT4
 
- TEA6420_INPUT5
 
- TEA6420_INPUT6
 
- TEA6420_OUTPUT1
 
- TEA6420_OUTPUT2
 
- TEA6420_OUTPUT3
 
- TEA6420_OUTPUT4
 
- TEA6420_S_GMU
 
- TEA6420_S_SA
 
- TEA6420_S_SB
 
- TEA6420_S_SC
 
- TEA6420_S_SD
 
- TEA6420_S_SE
 
- TEACORE
 
- TEAM_ATTR_ITEM_OPTION
 
- TEAM_ATTR_ITEM_OPTION_MAX
 
- TEAM_ATTR_ITEM_OPTION_UNSPEC
 
- TEAM_ATTR_ITEM_PORT
 
- TEAM_ATTR_ITEM_PORT_MAX
 
- TEAM_ATTR_ITEM_PORT_UNSPEC
 
- TEAM_ATTR_LIST_OPTION
 
- TEAM_ATTR_LIST_PORT
 
- TEAM_ATTR_MAX
 
- TEAM_ATTR_OPTION_ARRAY_INDEX
 
- TEAM_ATTR_OPTION_CHANGED
 
- TEAM_ATTR_OPTION_DATA
 
- TEAM_ATTR_OPTION_MAX
 
- TEAM_ATTR_OPTION_NAME
 
- TEAM_ATTR_OPTION_PORT_IFINDEX
 
- TEAM_ATTR_OPTION_REMOVED
 
- TEAM_ATTR_OPTION_TYPE
 
- TEAM_ATTR_OPTION_UNSPEC
 
- TEAM_ATTR_PORT_CHANGED
 
- TEAM_ATTR_PORT_DUPLEX
 
- TEAM_ATTR_PORT_IFINDEX
 
- TEAM_ATTR_PORT_LINKUP
 
- TEAM_ATTR_PORT_MAX
 
- TEAM_ATTR_PORT_REMOVED
 
- TEAM_ATTR_PORT_SPEED
 
- TEAM_ATTR_PORT_UNSPEC
 
- TEAM_ATTR_TEAM_IFINDEX
 
- TEAM_ATTR_UNSPEC
 
- TEAM_CMD_MAX
 
- TEAM_CMD_NOOP
 
- TEAM_CMD_OPTIONS_GET
 
- TEAM_CMD_OPTIONS_SET
 
- TEAM_CMD_PORT_LIST_GET
 
- TEAM_DEFAULT_NUM_RX_QUEUES
 
- TEAM_DEFAULT_NUM_TX_QUEUES
 
- TEAM_ENC_FEATURES
 
- TEAM_GENL_CHANGE_EVENT_MC_GRP_NAME
 
- TEAM_GENL_NAME
 
- TEAM_GENL_VERSION
 
- TEAM_MODE_PRIV_LONGS
 
- TEAM_MODE_PRIV_SIZE
 
- TEAM_OPTION_TYPE_BINARY
 
- TEAM_OPTION_TYPE_BOOL
 
- TEAM_OPTION_TYPE_S32
 
- TEAM_OPTION_TYPE_STRING
 
- TEAM_OPTION_TYPE_U32
 
- TEAM_PORT_HASHBITS
 
- TEAM_PORT_HASHENTRIES
 
- TEAM_STRING_MAX_LEN
 
- TEAM_VLAN_FEATURES
 
- TEARING_EFFECT
 
- TEARING_EFFECT_DELAY
 
- TEARING_EFFECT_DELAY_MASK
 
- TEARING_EFFECT_DELAY_SHIFT
 
- TEARING_EFFECT_DSI
 
- TEARING_EFFECT_GPIO
 
- TEARING_EFFECT_MASK
 
- TEARING_EFFECT_OFF
 
- TEARING_EFFECT_SHIFT
 
- TEAR_FX_EN
 
- TEAR_REG
 
- TEA_BLOCK_SIZE
 
- TEA_DELTA
 
- TEA_HASH
 
- TEA_KEY_SIZE
 
- TEA_ROUNDS
 
- TEA_transform
 
- TEC
 
- TECCR
 
- TECHNISAT
 
- TECHNOTREND_S2_4600
 
- TECH_LED_BLINK
 
- TECH_LED_OFF
 
- TECH_LED_ON
 
- TECH_LED_UNDEFINED
 
- TECH_OFFSET
 
- TECNTH
 
- TECNTL
 
- TECNTM
 
- TECR_mskBP
 
- TECR_mskDBG
 
- TECR_mskE
 
- TECR_mskEVIC
 
- TECR_mskHWINT
 
- TECR_mskL
 
- TECR_mskMRE
 
- TECR_mskNMI
 
- TECR_mskSYS
 
- TECR_offBP
 
- TECR_offDBG
 
- TECR_offE
 
- TECR_offEVIC
 
- TECR_offHWINT
 
- TECR_offL
 
- TECR_offMRE
 
- TECR_offNMI
 
- TECR_offSYS
 
- TEDA5
 
- TEDB5
 
- TEDF
 
- TEDF_ADDR
 
- TEEC_ERROR_BAD_PARAMETERS
 
- TEEC_ERROR_COMMUNICATION
 
- TEEC_ERROR_OUT_OF_MEMORY
 
- TEEC_ERROR_SHORT_BUFFER
 
- TEEC_ORIGIN_COMMS
 
- TEEC_SUCCESS
 
- TEE_DESC_PRIVILEGED
 
- TEE_DEVICE_FLAG_REGISTERED
 
- TEE_ERROR_HEALTH_TEST_FAIL
 
- TEE_GEN_CAP_GP
 
- TEE_GEN_CAP_PRIVILEGED
 
- TEE_GEN_CAP_REG_MEM
 
- TEE_IMPL_ID_OPTEE
 
- TEE_IOCTL_LOGIN_APPLICATION
 
- TEE_IOCTL_LOGIN_GROUP
 
- TEE_IOCTL_LOGIN_GROUP_APPLICATION
 
- TEE_IOCTL_LOGIN_PUBLIC
 
- TEE_IOCTL_LOGIN_USER
 
- TEE_IOCTL_LOGIN_USER_APPLICATION
 
- TEE_IOCTL_PARAM_ATTR_MASK
 
- TEE_IOCTL_PARAM_ATTR_META
 
- TEE_IOCTL_PARAM_ATTR_TYPE_MASK
 
- TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INOUT
 
- TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INPUT
 
- TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_OUTPUT
 
- TEE_IOCTL_PARAM_ATTR_TYPE_NONE
 
- TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INOUT
 
- TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT
 
- TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_OUTPUT
 
- TEE_IOCTL_PARAM_SIZE
 
- TEE_IOCTL_SHM_DMA_BUF
 
- TEE_IOCTL_SHM_MAPPED
 
- TEE_IOCTL_UUID_LEN
 
- TEE_IOC_BASE
 
- TEE_IOC_CANCEL
 
- TEE_IOC_CLOSE_SESSION
 
- TEE_IOC_INVOKE
 
- TEE_IOC_MAGIC
 
- TEE_IOC_OPEN_SESSION
 
- TEE_IOC_SHM_ALLOC
 
- TEE_IOC_SHM_REGISTER
 
- TEE_IOC_SUPPL_RECV
 
- TEE_IOC_SUPPL_SEND
 
- TEE_IOC_VERSION
 
- TEE_MAX_ARG_SIZE
 
- TEE_MAX_DEV_NAME_LEN
 
- TEE_NUM_DEVICES
 
- TEE_OPTEE_CAP_TZ
 
- TEE_PRIVATE_H
 
- TEE_SHM_DMA_BUF
 
- TEE_SHM_EXT_DMA_BUF
 
- TEE_SHM_MAPPED
 
- TEE_SHM_POOL
 
- TEE_SHM_REGISTER
 
- TEE_SHM_USER_MAPPED
 
- TEF6862_HI_FREQ
 
- TEF6862_LO_FREQ
 
- TEGRA114
 
- TEGRA114_CLK_ACTMON
 
- TEGRA114_CLK_ADX
 
- TEGRA114_CLK_AMX
 
- TEGRA114_CLK_APBDMA
 
- TEGRA114_CLK_APBIF
 
- TEGRA114_CLK_AUDIO0
 
- TEGRA114_CLK_AUDIO0_2X
 
- TEGRA114_CLK_AUDIO0_MUX
 
- TEGRA114_CLK_AUDIO1
 
- TEGRA114_CLK_AUDIO1_2X
 
- TEGRA114_CLK_AUDIO1_MUX
 
- TEGRA114_CLK_AUDIO2
 
- TEGRA114_CLK_AUDIO2_2X
 
- TEGRA114_CLK_AUDIO2_MUX
 
- TEGRA114_CLK_AUDIO3
 
- TEGRA114_CLK_AUDIO3_2X
 
- TEGRA114_CLK_AUDIO3_MUX
 
- TEGRA114_CLK_AUDIO4
 
- TEGRA114_CLK_AUDIO4_2X
 
- TEGRA114_CLK_AUDIO4_MUX
 
- TEGRA114_CLK_BLINK
 
- TEGRA114_CLK_BSEA
 
- TEGRA114_CLK_BSEV
 
- TEGRA114_CLK_CCLK_G
 
- TEGRA114_CLK_CCLK_LP
 
- TEGRA114_CLK_CEC
 
- TEGRA114_CLK_CILAB
 
- TEGRA114_CLK_CILCD
 
- TEGRA114_CLK_CILE
 
- TEGRA114_CLK_CLK_32K
 
- TEGRA114_CLK_CLK_M
 
- TEGRA114_CLK_CLK_MAX
 
- TEGRA114_CLK_CLK_M_DIV2
 
- TEGRA114_CLK_CLK_M_DIV4
 
- TEGRA114_CLK_CLK_OUT_1
 
- TEGRA114_CLK_CLK_OUT_1_MUX
 
- TEGRA114_CLK_CLK_OUT_2
 
- TEGRA114_CLK_CLK_OUT_2_MUX
 
- TEGRA114_CLK_CLK_OUT_3
 
- TEGRA114_CLK_CLK_OUT_3_MUX
 
- TEGRA114_CLK_CSI
 
- TEGRA114_CLK_CSITE
 
- TEGRA114_CLK_CSUS
 
- TEGRA114_CLK_DAM0
 
- TEGRA114_CLK_DAM1
 
- TEGRA114_CLK_DAM2
 
- TEGRA114_CLK_DDS
 
- TEGRA114_CLK_DFLL_REF
 
- TEGRA114_CLK_DFLL_SOC
 
- TEGRA114_CLK_DISP1
 
- TEGRA114_CLK_DISP2
 
- TEGRA114_CLK_DP2
 
- TEGRA114_CLK_DSIA
 
- TEGRA114_CLK_DSIALP
 
- TEGRA114_CLK_DSIA_MUX
 
- TEGRA114_CLK_DSIB
 
- TEGRA114_CLK_DSIBLP
 
- TEGRA114_CLK_DSIB_MUX
 
- TEGRA114_CLK_DTV
 
- TEGRA114_CLK_D_AUDIO
 
- TEGRA114_CLK_EMC
 
- TEGRA114_CLK_EPP
 
- TEGRA114_CLK_EXTERN1
 
- TEGRA114_CLK_EXTERN2
 
- TEGRA114_CLK_EXTERN3
 
- TEGRA114_CLK_FUSE
 
- TEGRA114_CLK_FUSE_BURN
 
- TEGRA114_CLK_GR2D
 
- TEGRA114_CLK_GR3D
 
- TEGRA114_CLK_HCLK
 
- TEGRA114_CLK_HDA
 
- TEGRA114_CLK_HDA2CODEC_2X
 
- TEGRA114_CLK_HDA2HDMI
 
- TEGRA114_CLK_HDMI
 
- TEGRA114_CLK_HOST1X
 
- TEGRA114_CLK_I2C1
 
- TEGRA114_CLK_I2C2
 
- TEGRA114_CLK_I2C3
 
- TEGRA114_CLK_I2C4
 
- TEGRA114_CLK_I2C5
 
- TEGRA114_CLK_I2CSLOW
 
- TEGRA114_CLK_I2S0
 
- TEGRA114_CLK_I2S0_SYNC
 
- TEGRA114_CLK_I2S1
 
- TEGRA114_CLK_I2S1_SYNC
 
- TEGRA114_CLK_I2S2
 
- TEGRA114_CLK_I2S2_SYNC
 
- TEGRA114_CLK_I2S3
 
- TEGRA114_CLK_I2S3_SYNC
 
- TEGRA114_CLK_I2S4
 
- TEGRA114_CLK_I2S4_SYNC
 
- TEGRA114_CLK_ISP
 
- TEGRA114_CLK_KBC
 
- TEGRA114_CLK_KFUSE
 
- TEGRA114_CLK_LA
 
- TEGRA114_CLK_MC
 
- TEGRA114_CLK_MIPI
 
- TEGRA114_CLK_MIPI_CAL
 
- TEGRA114_CLK_MSELECT
 
- TEGRA114_CLK_MSENC
 
- TEGRA114_CLK_NDFLASH
 
- TEGRA114_CLK_NDSPEED
 
- TEGRA114_CLK_NOR
 
- TEGRA114_CLK_OWR
 
- TEGRA114_CLK_PCLK
 
- TEGRA114_CLK_PERIPH_BANKS
 
- TEGRA114_CLK_PLL_A
 
- TEGRA114_CLK_PLL_A_OUT0
 
- TEGRA114_CLK_PLL_C
 
- TEGRA114_CLK_PLL_C2
 
- TEGRA114_CLK_PLL_C3
 
- TEGRA114_CLK_PLL_C_OUT1
 
- TEGRA114_CLK_PLL_D
 
- TEGRA114_CLK_PLL_D2
 
- TEGRA114_CLK_PLL_D2_OUT0
 
- TEGRA114_CLK_PLL_D_OUT0
 
- TEGRA114_CLK_PLL_E_OUT0
 
- TEGRA114_CLK_PLL_M
 
- TEGRA114_CLK_PLL_M_OUT1
 
- TEGRA114_CLK_PLL_P
 
- TEGRA114_CLK_PLL_P_OUT1
 
- TEGRA114_CLK_PLL_P_OUT2
 
- TEGRA114_CLK_PLL_P_OUT3
 
- TEGRA114_CLK_PLL_P_OUT4
 
- TEGRA114_CLK_PLL_REF
 
- TEGRA114_CLK_PLL_RE_OUT
 
- TEGRA114_CLK_PLL_RE_VCO
 
- TEGRA114_CLK_PLL_U
 
- TEGRA114_CLK_PLL_U_12M
 
- TEGRA114_CLK_PLL_U_480M
 
- TEGRA114_CLK_PLL_U_48M
 
- TEGRA114_CLK_PLL_U_60M
 
- TEGRA114_CLK_PLL_X
 
- TEGRA114_CLK_PLL_X_OUT0
 
- TEGRA114_CLK_PWM
 
- TEGRA114_CLK_RTC
 
- TEGRA114_CLK_SBC1
 
- TEGRA114_CLK_SBC2
 
- TEGRA114_CLK_SBC3
 
- TEGRA114_CLK_SBC4
 
- TEGRA114_CLK_SBC5
 
- TEGRA114_CLK_SBC6
 
- TEGRA114_CLK_SCLK
 
- TEGRA114_CLK_SDMMC1
 
- TEGRA114_CLK_SDMMC2
 
- TEGRA114_CLK_SDMMC3
 
- TEGRA114_CLK_SDMMC4
 
- TEGRA114_CLK_SE
 
- TEGRA114_CLK_SOC_THERM
 
- TEGRA114_CLK_SPDIF
 
- TEGRA114_CLK_SPDIF_2X
 
- TEGRA114_CLK_SPDIF_IN
 
- TEGRA114_CLK_SPDIF_IN_SYNC
 
- TEGRA114_CLK_SPDIF_MUX
 
- TEGRA114_CLK_SPDIF_OUT
 
- TEGRA114_CLK_TIMER
 
- TEGRA114_CLK_TRACE
 
- TEGRA114_CLK_TSEC
 
- TEGRA114_CLK_TSENSOR
 
- TEGRA114_CLK_UARTA
 
- TEGRA114_CLK_UARTB
 
- TEGRA114_CLK_UARTC
 
- TEGRA114_CLK_UARTD
 
- TEGRA114_CLK_USB2
 
- TEGRA114_CLK_USB3
 
- TEGRA114_CLK_USBD
 
- TEGRA114_CLK_VCP
 
- TEGRA114_CLK_VDE
 
- TEGRA114_CLK_VFIR
 
- TEGRA114_CLK_VI
 
- TEGRA114_CLK_VIMCLK_SYNC
 
- TEGRA114_CLK_VI_SENSOR
 
- TEGRA114_CLK_XUSB_DEV
 
- TEGRA114_CLK_XUSB_DEV_SRC
 
- TEGRA114_CLK_XUSB_FALCON_SRC
 
- TEGRA114_CLK_XUSB_FS_SRC
 
- TEGRA114_CLK_XUSB_HOST
 
- TEGRA114_CLK_XUSB_HOST_SRC
 
- TEGRA114_CLK_XUSB_HS_SRC
 
- TEGRA114_CLK_XUSB_SS
 
- TEGRA114_CLK_XUSB_SS_DIV2
 
- TEGRA114_CLK_XUSB_SS_SRC
 
- TEGRA114_MAX_STATES
 
- TEGRA114_MC_RESET
 
- TEGRA114_MC_RESET_2D
 
- TEGRA114_MC_RESET_3D
 
- TEGRA114_MC_RESET_3D2
 
- TEGRA114_MC_RESET_AVPC
 
- TEGRA114_MC_RESET_DC
 
- TEGRA114_MC_RESET_DCB
 
- TEGRA114_MC_RESET_EPP
 
- TEGRA114_MC_RESET_HC
 
- TEGRA114_MC_RESET_HDA
 
- TEGRA114_MC_RESET_ISP
 
- TEGRA114_MC_RESET_MPCORE
 
- TEGRA114_MC_RESET_MPCORELP
 
- TEGRA114_MC_RESET_MPE
 
- TEGRA114_MC_RESET_PPCS
 
- TEGRA114_MC_RESET_VDE
 
- TEGRA114_MC_RESET_VI
 
- TEGRA124
 
- TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK
 
- TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US
 
- TEGRA124_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT
 
- TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK
 
- TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US
 
- TEGRA124_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT
 
- TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK
 
- TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US
 
- TEGRA124_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT
 
- TEGRA124_BPTT
 
- TEGRA124_CAR_BANK_COUNT
 
- TEGRA124_CLK_ACTMON
 
- TEGRA124_CLK_ADX
 
- TEGRA124_CLK_ADX1
 
- TEGRA124_CLK_AFI
 
- TEGRA124_CLK_AMX
 
- TEGRA124_CLK_AMX1
 
- TEGRA124_CLK_APBDMA
 
- TEGRA124_CLK_APBIF
 
- TEGRA124_CLK_AUDIO0
 
- TEGRA124_CLK_AUDIO0_2X
 
- TEGRA124_CLK_AUDIO0_MUX
 
- TEGRA124_CLK_AUDIO1
 
- TEGRA124_CLK_AUDIO1_2X
 
- TEGRA124_CLK_AUDIO1_MUX
 
- TEGRA124_CLK_AUDIO2
 
- TEGRA124_CLK_AUDIO2_2X
 
- TEGRA124_CLK_AUDIO2_MUX
 
- TEGRA124_CLK_AUDIO3
 
- TEGRA124_CLK_AUDIO3_2X
 
- TEGRA124_CLK_AUDIO3_MUX
 
- TEGRA124_CLK_AUDIO4
 
- TEGRA124_CLK_AUDIO4_2X
 
- TEGRA124_CLK_AUDIO4_MUX
 
- TEGRA124_CLK_BLINK
 
- TEGRA124_CLK_BSEA
 
- TEGRA124_CLK_BSEV
 
- TEGRA124_CLK_CCLK_G
 
- TEGRA124_CLK_CCLK_LP
 
- TEGRA124_CLK_CEC
 
- TEGRA124_CLK_CILAB
 
- TEGRA124_CLK_CILCD
 
- TEGRA124_CLK_CILE
 
- TEGRA124_CLK_CLK72MHZ
 
- TEGRA124_CLK_CLK_32K
 
- TEGRA124_CLK_CLK_M
 
- TEGRA124_CLK_CLK_MAX
 
- TEGRA124_CLK_CLK_M_DIV2
 
- TEGRA124_CLK_CLK_M_DIV4
 
- TEGRA124_CLK_CLK_OUT_1
 
- TEGRA124_CLK_CLK_OUT_1_MUX
 
- TEGRA124_CLK_CLK_OUT_2
 
- TEGRA124_CLK_CLK_OUT_2_MUX
 
- TEGRA124_CLK_CLK_OUT_3
 
- TEGRA124_CLK_CLK_OUT_3_MUX
 
- TEGRA124_CLK_CML0
 
- TEGRA124_CLK_CML1
 
- TEGRA124_CLK_CSI
 
- TEGRA124_CLK_CSITE
 
- TEGRA124_CLK_CSUS
 
- TEGRA124_CLK_DAM0
 
- TEGRA124_CLK_DAM1
 
- TEGRA124_CLK_DAM2
 
- TEGRA124_CLK_DDS
 
- TEGRA124_CLK_DFLL_REF
 
- TEGRA124_CLK_DFLL_SOC
 
- TEGRA124_CLK_DISP1
 
- TEGRA124_CLK_DISP2
 
- TEGRA124_CLK_DP2
 
- TEGRA124_CLK_DPAUX
 
- TEGRA124_CLK_DSIA
 
- TEGRA124_CLK_DSIALP
 
- TEGRA124_CLK_DSIB
 
- TEGRA124_CLK_DSIBLP
 
- TEGRA124_CLK_DTV
 
- TEGRA124_CLK_D_AUDIO
 
- TEGRA124_CLK_EMC
 
- TEGRA124_CLK_ENTROPY
 
- TEGRA124_CLK_EXTERN1
 
- TEGRA124_CLK_EXTERN2
 
- TEGRA124_CLK_EXTERN3
 
- TEGRA124_CLK_FUSE
 
- TEGRA124_CLK_FUSE_BURN
 
- TEGRA124_CLK_GPU
 
- TEGRA124_CLK_HCLK
 
- TEGRA124_CLK_HDA
 
- TEGRA124_CLK_HDA2CODEC_2X
 
- TEGRA124_CLK_HDA2HDMI
 
- TEGRA124_CLK_HDMI
 
- TEGRA124_CLK_HDMI_AUDIO
 
- TEGRA124_CLK_HOST1X
 
- TEGRA124_CLK_I2C1
 
- TEGRA124_CLK_I2C2
 
- TEGRA124_CLK_I2C3
 
- TEGRA124_CLK_I2C4
 
- TEGRA124_CLK_I2C5
 
- TEGRA124_CLK_I2C6
 
- TEGRA124_CLK_I2CSLOW
 
- TEGRA124_CLK_I2S0
 
- TEGRA124_CLK_I2S0_SYNC
 
- TEGRA124_CLK_I2S1
 
- TEGRA124_CLK_I2S1_SYNC
 
- TEGRA124_CLK_I2S2
 
- TEGRA124_CLK_I2S2_SYNC
 
- TEGRA124_CLK_I2S3
 
- TEGRA124_CLK_I2S3_SYNC
 
- TEGRA124_CLK_I2S4
 
- TEGRA124_CLK_I2S4_SYNC
 
- TEGRA124_CLK_ISP
 
- TEGRA124_CLK_ISPB
 
- TEGRA124_CLK_KBC
 
- TEGRA124_CLK_KFUSE
 
- TEGRA124_CLK_LA
 
- TEGRA124_CLK_MC
 
- TEGRA124_CLK_MIPI
 
- TEGRA124_CLK_MIPI_CAL
 
- TEGRA124_CLK_MSELECT
 
- TEGRA124_CLK_MSENC
 
- TEGRA124_CLK_NOR
 
- TEGRA124_CLK_OWR
 
- TEGRA124_CLK_PCIE
 
- TEGRA124_CLK_PCLK
 
- TEGRA124_CLK_PLL_A
 
- TEGRA124_CLK_PLL_A_OUT0
 
- TEGRA124_CLK_PLL_C
 
- TEGRA124_CLK_PLL_C2
 
- TEGRA124_CLK_PLL_C3
 
- TEGRA124_CLK_PLL_C4
 
- TEGRA124_CLK_PLL_C_OUT1
 
- TEGRA124_CLK_PLL_C_UD
 
- TEGRA124_CLK_PLL_D
 
- TEGRA124_CLK_PLL_D2
 
- TEGRA124_CLK_PLL_D2_OUT0
 
- TEGRA124_CLK_PLL_DP
 
- TEGRA124_CLK_PLL_D_DSI_OUT
 
- TEGRA124_CLK_PLL_D_OUT0
 
- TEGRA124_CLK_PLL_E
 
- TEGRA124_CLK_PLL_E_MUX
 
- TEGRA124_CLK_PLL_M
 
- TEGRA124_CLK_PLL_M_OUT1
 
- TEGRA124_CLK_PLL_M_UD
 
- TEGRA124_CLK_PLL_P
 
- TEGRA124_CLK_PLL_P_OUT1
 
- TEGRA124_CLK_PLL_P_OUT2
 
- TEGRA124_CLK_PLL_P_OUT3
 
- TEGRA124_CLK_PLL_P_OUT4
 
- TEGRA124_CLK_PLL_P_OUT5
 
- TEGRA124_CLK_PLL_REF
 
- TEGRA124_CLK_PLL_RE_OUT
 
- TEGRA124_CLK_PLL_RE_VCO
 
- TEGRA124_CLK_PLL_U
 
- TEGRA124_CLK_PLL_U_12M
 
- TEGRA124_CLK_PLL_U_480M
 
- TEGRA124_CLK_PLL_U_48M
 
- TEGRA124_CLK_PLL_U_60M
 
- TEGRA124_CLK_PLL_X
 
- TEGRA124_CLK_PLL_X_OUT0
 
- TEGRA124_CLK_PWM
 
- TEGRA124_CLK_RTC
 
- TEGRA124_CLK_SATA
 
- TEGRA124_CLK_SATA_COLD
 
- TEGRA124_CLK_SATA_OOB
 
- TEGRA124_CLK_SBC1
 
- TEGRA124_CLK_SBC2
 
- TEGRA124_CLK_SBC3
 
- TEGRA124_CLK_SBC4
 
- TEGRA124_CLK_SBC5
 
- TEGRA124_CLK_SBC6
 
- TEGRA124_CLK_SCLK
 
- TEGRA124_CLK_SDMMC1
 
- TEGRA124_CLK_SDMMC2
 
- TEGRA124_CLK_SDMMC3
 
- TEGRA124_CLK_SDMMC4
 
- TEGRA124_CLK_SE
 
- TEGRA124_CLK_SOC_THERM
 
- TEGRA124_CLK_SOR0
 
- TEGRA124_CLK_SOR0_LVDS
 
- TEGRA124_CLK_SPDIF
 
- TEGRA124_CLK_SPDIF_2X
 
- TEGRA124_CLK_SPDIF_IN
 
- TEGRA124_CLK_SPDIF_IN_SYNC
 
- TEGRA124_CLK_SPDIF_MUX
 
- TEGRA124_CLK_SPDIF_OUT
 
- TEGRA124_CLK_TIMER
 
- TEGRA124_CLK_TRACE
 
- TEGRA124_CLK_TSEC
 
- TEGRA124_CLK_TSENSOR
 
- TEGRA124_CLK_UARTA
 
- TEGRA124_CLK_UARTB
 
- TEGRA124_CLK_UARTC
 
- TEGRA124_CLK_UARTD
 
- TEGRA124_CLK_USB2
 
- TEGRA124_CLK_USB3
 
- TEGRA124_CLK_USBD
 
- TEGRA124_CLK_VCP
 
- TEGRA124_CLK_VDE
 
- TEGRA124_CLK_VFIR
 
- TEGRA124_CLK_VI
 
- TEGRA124_CLK_VIC03
 
- TEGRA124_CLK_VIM2_CLK
 
- TEGRA124_CLK_VIMCLK_SYNC
 
- TEGRA124_CLK_VI_SENSOR
 
- TEGRA124_CLK_VI_SENSOR2
 
- TEGRA124_CLK_XUSB_DEV
 
- TEGRA124_CLK_XUSB_DEV_SRC
 
- TEGRA124_CLK_XUSB_FALCON_SRC
 
- TEGRA124_CLK_XUSB_FS_SRC
 
- TEGRA124_CLK_XUSB_HOST
 
- TEGRA124_CLK_XUSB_HOST_SRC
 
- TEGRA124_CLK_XUSB_HS_SRC
 
- TEGRA124_CLK_XUSB_SS
 
- TEGRA124_CLK_XUSB_SS_DIV2
 
- TEGRA124_CLK_XUSB_SS_SRC
 
- TEGRA124_EMC_BASE
 
- TEGRA124_EMC_SIZE
 
- TEGRA124_FUNCTION
 
- TEGRA124_FUNC_PCIE
 
- TEGRA124_FUNC_RSVD
 
- TEGRA124_FUNC_SATA
 
- TEGRA124_FUNC_SNPS
 
- TEGRA124_FUNC_UART
 
- TEGRA124_FUNC_USB3
 
- TEGRA124_FUNC_XUSB
 
- TEGRA124_IO_PAD_TABLE
 
- TEGRA124_LANE
 
- TEGRA124_MC_RESET
 
- TEGRA124_MC_RESET_AFI
 
- TEGRA124_MC_RESET_AVPC
 
- TEGRA124_MC_RESET_DC
 
- TEGRA124_MC_RESET_DCB
 
- TEGRA124_MC_RESET_GPU
 
- TEGRA124_MC_RESET_HC
 
- TEGRA124_MC_RESET_HDA
 
- TEGRA124_MC_RESET_ISP2
 
- TEGRA124_MC_RESET_ISP2B
 
- TEGRA124_MC_RESET_MPCORE
 
- TEGRA124_MC_RESET_MPCORELP
 
- TEGRA124_MC_RESET_MSENC
 
- TEGRA124_MC_RESET_PPCS
 
- TEGRA124_MC_RESET_SATA
 
- TEGRA124_MC_RESET_SDMMC1
 
- TEGRA124_MC_RESET_SDMMC2
 
- TEGRA124_MC_RESET_SDMMC3
 
- TEGRA124_MC_RESET_SDMMC4
 
- TEGRA124_MC_RESET_TSEC
 
- TEGRA124_MC_RESET_VDE
 
- TEGRA124_MC_RESET_VI
 
- TEGRA124_MC_RESET_VIC
 
- TEGRA124_MC_RESET_XUSB_DEV
 
- TEGRA124_MC_RESET_XUSB_HOST
 
- TEGRA124_RESET
 
- TEGRA124_RST_DFLL_DVCO
 
- TEGRA124_SOCTHERM_SENSOR_CPU
 
- TEGRA124_SOCTHERM_SENSOR_GPU
 
- TEGRA124_SOCTHERM_SENSOR_MEM
 
- TEGRA124_SOCTHERM_SENSOR_NUM
 
- TEGRA124_SOCTHERM_SENSOR_PLLX
 
- TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK
 
- TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK
 
- TEGRA124_THERMTRIP_ANY_EN_MASK
 
- TEGRA124_THERMTRIP_CPU_EN_MASK
 
- TEGRA124_THERMTRIP_CPU_THRESH_MASK
 
- TEGRA124_THERMTRIP_GPUMEM_THRESH_MASK
 
- TEGRA124_THERMTRIP_GPU_EN_MASK
 
- TEGRA124_THERMTRIP_MEM_EN_MASK
 
- TEGRA124_THERMTRIP_TSENSE_EN_MASK
 
- TEGRA124_THERMTRIP_TSENSE_THRESH_MASK
 
- TEGRA124_THRESH_GRAIN
 
- TEGRA132
 
- TEGRA132_BPTT
 
- TEGRA132_THERMCTL_LVL0_DN_THRESH_MASK
 
- TEGRA132_THERMCTL_LVL0_UP_THRESH_MASK
 
- TEGRA132_THERMTRIP_ANY_EN_MASK
 
- TEGRA132_THERMTRIP_CPU_EN_MASK
 
- TEGRA132_THERMTRIP_CPU_THRESH_MASK
 
- TEGRA132_THERMTRIP_GPUMEM_THRESH_MASK
 
- TEGRA132_THERMTRIP_GPU_EN_MASK
 
- TEGRA132_THERMTRIP_MEM_EN_MASK
 
- TEGRA132_THERMTRIP_TSENSE_EN_MASK
 
- TEGRA132_THERMTRIP_TSENSE_THRESH_MASK
 
- TEGRA132_THRESH_GRAIN
 
- TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS
 
- TEGRA186_ADMA_CH_FIFO_CTRL_RXSIZE
 
- TEGRA186_ADMA_CH_FIFO_CTRL_TXSIZE
 
- TEGRA186_AON_GPIO
 
- TEGRA186_AON_GPIO_PORT
 
- TEGRA186_AON_GPIO_PORT_AA
 
- TEGRA186_AON_GPIO_PORT_EE
 
- TEGRA186_AON_GPIO_PORT_FF
 
- TEGRA186_AON_GPIO_PORT_S
 
- TEGRA186_AON_GPIO_PORT_U
 
- TEGRA186_AON_GPIO_PORT_V
 
- TEGRA186_AON_GPIO_PORT_W
 
- TEGRA186_AON_GPIO_PORT_Z
 
- TEGRA186_BPMP_THERMAL_ZONE_AO
 
- TEGRA186_BPMP_THERMAL_ZONE_AUX
 
- TEGRA186_BPMP_THERMAL_ZONE_CPU
 
- TEGRA186_BPMP_THERMAL_ZONE_GPU
 
- TEGRA186_BPMP_THERMAL_ZONE_PLLX
 
- TEGRA186_CLK_ACLK
 
- TEGRA186_CLK_ACTMON
 
- TEGRA186_CLK_ADSP
 
- TEGRA186_CLK_ADSPNEON
 
- TEGRA186_CLK_AFI
 
- TEGRA186_CLK_AHUB
 
- TEGRA186_CLK_AON_APB
 
- TEGRA186_CLK_AON_CPU_NIC
 
- TEGRA186_CLK_AON_I2C_SLOW
 
- TEGRA186_CLK_AON_NIC
 
- TEGRA186_CLK_AON_TOUCH
 
- TEGRA186_CLK_AON_UART_FST_MIPI_CAL
 
- TEGRA186_CLK_APB2APE
 
- TEGRA186_CLK_APE
 
- TEGRA186_CLK_AUD_MCLK
 
- TEGRA186_CLK_AXI_CBB
 
- TEGRA186_CLK_BPMP_APB
 
- TEGRA186_CLK_BPMP_CPU_NIC
 
- TEGRA186_CLK_BPMP_NIC
 
- TEGRA186_CLK_CAN1
 
- TEGRA186_CLK_CAN1_HOST
 
- TEGRA186_CLK_CAN2
 
- TEGRA186_CLK_CAN2_HOST
 
- TEGRA186_CLK_CEC
 
- TEGRA186_CLK_CLK_32K
 
- TEGRA186_CLK_CLK_M
 
- TEGRA186_CLK_CLK_MAX
 
- TEGRA186_CLK_DBGAPB
 
- TEGRA186_CLK_DFLLDISP_DIV
 
- TEGRA186_CLK_DMIC1
 
- TEGRA186_CLK_DMIC2
 
- TEGRA186_CLK_DMIC3
 
- TEGRA186_CLK_DMIC4
 
- TEGRA186_CLK_DMIC5
 
- TEGRA186_CLK_DP2
 
- TEGRA186_CLK_DPAUX
 
- TEGRA186_CLK_DPAUX1
 
- TEGRA186_CLK_DSI
 
- TEGRA186_CLK_DSIA_LP
 
- TEGRA186_CLK_DSIB
 
- TEGRA186_CLK_DSIB_LP
 
- TEGRA186_CLK_DSIC
 
- TEGRA186_CLK_DSIC_LP
 
- TEGRA186_CLK_DSID
 
- TEGRA186_CLK_DSID_LP
 
- TEGRA186_CLK_DSPK1
 
- TEGRA186_CLK_DSPK2
 
- TEGRA186_CLK_DTV
 
- TEGRA186_CLK_DTV_INPUT
 
- TEGRA186_CLK_EMC
 
- TEGRA186_CLK_EQOS_AXI
 
- TEGRA186_CLK_EQOS_PTP_REF
 
- TEGRA186_CLK_EQOS_RX
 
- TEGRA186_CLK_EQOS_RX_INPUT
 
- TEGRA186_CLK_EQOS_TX
 
- TEGRA186_CLK_EXTPERIPH1
 
- TEGRA186_CLK_EXTPERIPH2
 
- TEGRA186_CLK_EXTPERIPH3
 
- TEGRA186_CLK_EXTPERIPH4
 
- TEGRA186_CLK_FUSE
 
- TEGRA186_CLK_GPC2CLK
 
- TEGRA186_CLK_GPCCLK
 
- TEGRA186_CLK_GPU
 
- TEGRA186_CLK_HDA
 
- TEGRA186_CLK_HDA2CODEC_2X
 
- TEGRA186_CLK_HDA2HDMICODEC
 
- TEGRA186_CLK_HOST1X
 
- TEGRA186_CLK_HSIC_TRK
 
- TEGRA186_CLK_I2C1
 
- TEGRA186_CLK_I2C10
 
- TEGRA186_CLK_I2C12
 
- TEGRA186_CLK_I2C13
 
- TEGRA186_CLK_I2C14
 
- TEGRA186_CLK_I2C2
 
- TEGRA186_CLK_I2C3
 
- TEGRA186_CLK_I2C4
 
- TEGRA186_CLK_I2C5
 
- TEGRA186_CLK_I2C6
 
- TEGRA186_CLK_I2C7
 
- TEGRA186_CLK_I2C8
 
- TEGRA186_CLK_I2C9
 
- TEGRA186_CLK_I2C_SLOW
 
- TEGRA186_CLK_I2S1
 
- TEGRA186_CLK_I2S1_SYNC_INPUT
 
- TEGRA186_CLK_I2S2
 
- TEGRA186_CLK_I2S2_SYNC_INPUT
 
- TEGRA186_CLK_I2S3
 
- TEGRA186_CLK_I2S3_SYNC_INPUT
 
- TEGRA186_CLK_I2S4
 
- TEGRA186_CLK_I2S4_SYNC_INPUT
 
- TEGRA186_CLK_I2S5
 
- TEGRA186_CLK_I2S5_SYNC_INPUT
 
- TEGRA186_CLK_I2S6
 
- TEGRA186_CLK_I2S6_SYNC_INPUT
 
- TEGRA186_CLK_IQC1
 
- TEGRA186_CLK_IQC2
 
- TEGRA186_CLK_ISP
 
- TEGRA186_CLK_KFUSE
 
- TEGRA186_CLK_MAUD
 
- TEGRA186_CLK_MIPI_CAL
 
- TEGRA186_CLK_MPHY_CORE_PLL_FIXED
 
- TEGRA186_CLK_MPHY_IOBIST
 
- TEGRA186_CLK_MPHY_L0_RX_ANA
 
- TEGRA186_CLK_MPHY_L0_RX_LS_BIT
 
- TEGRA186_CLK_MPHY_L0_RX_SYMB
 
- TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT
 
- TEGRA186_CLK_MPHY_L0_TX_SYMB
 
- TEGRA186_CLK_MPHY_L1_RX_ANA
 
- TEGRA186_CLK_MPHY_TX_1MHZ_REF
 
- TEGRA186_CLK_MSS_ENCRYPT
 
- TEGRA186_CLK_NAFLL_AXI_CBB
 
- TEGRA186_CLK_NAFLL_BCPU
 
- TEGRA186_CLK_NAFLL_BPMP
 
- TEGRA186_CLK_NAFLL_DISP
 
- TEGRA186_CLK_NAFLL_GPU
 
- TEGRA186_CLK_NAFLL_ISP
 
- TEGRA186_CLK_NAFLL_MCPU
 
- TEGRA186_CLK_NAFLL_NVDEC
 
- TEGRA186_CLK_NAFLL_NVENC
 
- TEGRA186_CLK_NAFLL_NVJPG
 
- TEGRA186_CLK_NAFLL_SCE
 
- TEGRA186_CLK_NAFLL_SE
 
- TEGRA186_CLK_NAFLL_TSEC
 
- TEGRA186_CLK_NAFLL_TSECB
 
- TEGRA186_CLK_NAFLL_VI
 
- TEGRA186_CLK_NAFLL_VIC
 
- TEGRA186_CLK_NVCSI
 
- TEGRA186_CLK_NVCSILP
 
- TEGRA186_CLK_NVDEC
 
- TEGRA186_CLK_NVDISPLAYHUB
 
- TEGRA186_CLK_NVDISPLAY_DISP
 
- TEGRA186_CLK_NVDISPLAY_DSC
 
- TEGRA186_CLK_NVDISPLAY_P0
 
- TEGRA186_CLK_NVDISPLAY_P1
 
- TEGRA186_CLK_NVDISPLAY_P2
 
- TEGRA186_CLK_NVENC
 
- TEGRA186_CLK_NVJPG
 
- TEGRA186_CLK_OSC
 
- TEGRA186_CLK_PCIE
 
- TEGRA186_CLK_PCIE2_IOBIST
 
- TEGRA186_CLK_PCIERX0
 
- TEGRA186_CLK_PCIERX1
 
- TEGRA186_CLK_PCIERX2
 
- TEGRA186_CLK_PCIERX3
 
- TEGRA186_CLK_PCIERX4
 
- TEGRA186_CLK_PEX_SATA_USB_RX_BYP
 
- TEGRA186_CLK_PEX_USB_PAD0_MGMT
 
- TEGRA186_CLK_PEX_USB_PAD1_MGMT
 
- TEGRA186_CLK_PLLA
 
- TEGRA186_CLK_PLLA1
 
- TEGRA186_CLK_PLLAON
 
- TEGRA186_CLK_PLLBPMPCAM
 
- TEGRA186_CLK_PLLC
 
- TEGRA186_CLK_PLLC2
 
- TEGRA186_CLK_PLLC3
 
- TEGRA186_CLK_PLLC4_OUT
 
- TEGRA186_CLK_PLLC4_OUT0
 
- TEGRA186_CLK_PLLC4_OUT1
 
- TEGRA186_CLK_PLLC4_OUT2
 
- TEGRA186_CLK_PLLC4_OUT_MUX
 
- TEGRA186_CLK_PLLC4_VCO
 
- TEGRA186_CLK_PLLC4_VCO_DIV2
 
- TEGRA186_CLK_PLLC_OUT_AON
 
- TEGRA186_CLK_PLLC_OUT_ISP
 
- TEGRA186_CLK_PLLC_OUT_VE
 
- TEGRA186_CLK_PLLD
 
- TEGRA186_CLK_PLLD2
 
- TEGRA186_CLK_PLLD3
 
- TEGRA186_CLK_PLLDISPHUB
 
- TEGRA186_CLK_PLLDISPHUB_DIV
 
- TEGRA186_CLK_PLLDP
 
- TEGRA186_CLK_PLLD_OUT1
 
- TEGRA186_CLK_PLLE
 
- TEGRA186_CLK_PLLE_PWRSEQ
 
- TEGRA186_CLK_PLLNVCSI
 
- TEGRA186_CLK_PLLP
 
- TEGRA186_CLK_PLLP_DIV8
 
- TEGRA186_CLK_PLLP_OUT0
 
- TEGRA186_CLK_PLLP_OUT5
 
- TEGRA186_CLK_PLLREFE_IDDQ
 
- TEGRA186_CLK_PLLREFE_OUT
 
- TEGRA186_CLK_PLLREFE_OUT1
 
- TEGRA186_CLK_PLLREFE_OUT1_DIV5
 
- TEGRA186_CLK_PLLREFE_OUT_GATED
 
- TEGRA186_CLK_PLLREFE_PEX
 
- TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH
 
- TEGRA186_CLK_PLLREFE_PLL_REF
 
- TEGRA186_CLK_PLLREFE_REF
 
- TEGRA186_CLK_PLLREFE_VCO
 
- TEGRA186_CLK_PLLU
 
- TEGRA186_CLK_PLL_A_OUT0
 
- TEGRA186_CLK_PLL_A_OUT1
 
- TEGRA186_CLK_PLL_P
 
- TEGRA186_CLK_PLL_REF
 
- TEGRA186_CLK_PLL_U_480M
 
- TEGRA186_CLK_PLL_U_48M
 
- TEGRA186_CLK_PWM1
 
- TEGRA186_CLK_PWM2
 
- TEGRA186_CLK_PWM3
 
- TEGRA186_CLK_PWM4
 
- TEGRA186_CLK_PWM5
 
- TEGRA186_CLK_PWM6
 
- TEGRA186_CLK_PWM7
 
- TEGRA186_CLK_PWM8
 
- TEGRA186_CLK_QSPI
 
- TEGRA186_CLK_QSPI_OUT
 
- TEGRA186_CLK_SATA
 
- TEGRA186_CLK_SATA_IOBIST
 
- TEGRA186_CLK_SATA_OOB
 
- TEGRA186_CLK_SCE_APB
 
- TEGRA186_CLK_SCE_CPU_NIC
 
- TEGRA186_CLK_SCE_NIC
 
- TEGRA186_CLK_SDMMC1
 
- TEGRA186_CLK_SDMMC2
 
- TEGRA186_CLK_SDMMC3
 
- TEGRA186_CLK_SDMMC4
 
- TEGRA186_CLK_SDMMC_LEGACY_TM
 
- TEGRA186_CLK_SE
 
- TEGRA186_CLK_SOR0
 
- TEGRA186_CLK_SOR0_OUT
 
- TEGRA186_CLK_SOR0_PAD_CLKOUT
 
- TEGRA186_CLK_SOR1
 
- TEGRA186_CLK_SOR1_OUT
 
- TEGRA186_CLK_SOR1_PAD_CLKOUT
 
- TEGRA186_CLK_SOR_SAFE
 
- TEGRA186_CLK_SPDIFIN_SYNC_INPUT
 
- TEGRA186_CLK_SPDIF_DOUBLER
 
- TEGRA186_CLK_SPDIF_IN
 
- TEGRA186_CLK_SPDIF_OUT
 
- TEGRA186_CLK_SPI1
 
- TEGRA186_CLK_SPI2
 
- TEGRA186_CLK_SPI3
 
- TEGRA186_CLK_SPI4
 
- TEGRA186_CLK_SYNC_DMIC1
 
- TEGRA186_CLK_SYNC_DMIC2
 
- TEGRA186_CLK_SYNC_DMIC3
 
- TEGRA186_CLK_SYNC_DMIC4
 
- TEGRA186_CLK_SYNC_DSPK1
 
- TEGRA186_CLK_SYNC_DSPK2
 
- TEGRA186_CLK_SYNC_I2S1
 
- TEGRA186_CLK_SYNC_I2S2
 
- TEGRA186_CLK_SYNC_I2S3
 
- TEGRA186_CLK_SYNC_I2S4
 
- TEGRA186_CLK_SYNC_I2S5
 
- TEGRA186_CLK_SYNC_I2S6
 
- TEGRA186_CLK_SYNC_SPDIF
 
- TEGRA186_CLK_TACH
 
- TEGRA186_CLK_TSC
 
- TEGRA186_CLK_TSEC
 
- TEGRA186_CLK_TSECB
 
- TEGRA186_CLK_UARTA
 
- TEGRA186_CLK_UARTB
 
- TEGRA186_CLK_UARTC
 
- TEGRA186_CLK_UARTD
 
- TEGRA186_CLK_UARTE
 
- TEGRA186_CLK_UARTF
 
- TEGRA186_CLK_UARTG
 
- TEGRA186_CLK_UART_FST_MIPI_CAL
 
- TEGRA186_CLK_UFSDEV_REF
 
- TEGRA186_CLK_UFSHC
 
- TEGRA186_CLK_UPHY_PLL0_PWRSEQ
 
- TEGRA186_CLK_UPHY_PLL1_PWRSEQ
 
- TEGRA186_CLK_USB2_HSIC_TRK
 
- TEGRA186_CLK_USB2_TRK
 
- TEGRA186_CLK_UTMIP_PLL_PWRSEQ
 
- TEGRA186_CLK_VI
 
- TEGRA186_CLK_VIC
 
- TEGRA186_CLK_VI_I2C
 
- TEGRA186_CLK_XUSB
 
- TEGRA186_CLK_XUSB_CORE_DEV
 
- TEGRA186_CLK_XUSB_CORE_SS
 
- TEGRA186_CLK_XUSB_DEV
 
- TEGRA186_CLK_XUSB_FALCON
 
- TEGRA186_CLK_XUSB_FS
 
- TEGRA186_CLK_XUSB_HOST
 
- TEGRA186_CLK_XUSB_SS
 
- TEGRA186_FIFO_CTRL_DEFAULT
 
- TEGRA186_GPIO_DEBOUNCE_CONTROL
 
- TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD
 
- TEGRA186_GPIO_ENABLE_CONFIG
 
- TEGRA186_GPIO_ENABLE_CONFIG_ENABLE
 
- TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT
 
- TEGRA186_GPIO_ENABLE_CONFIG_OUT
 
- TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL
 
- TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE
 
- TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL
 
- TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK
 
- TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE
 
- TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE
 
- TEGRA186_GPIO_INPUT
 
- TEGRA186_GPIO_INPUT_HIGH
 
- TEGRA186_GPIO_INTERRUPT_CLEAR
 
- TEGRA186_GPIO_INTERRUPT_STATUS
 
- TEGRA186_GPIO_OUTPUT_CONTROL
 
- TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED
 
- TEGRA186_GPIO_OUTPUT_VALUE
 
- TEGRA186_GPIO_OUTPUT_VALUE_HIGH
 
- TEGRA186_IO_PAD_TABLE
 
- TEGRA186_LANE
 
- TEGRA186_MAIN_GPIO
 
- TEGRA186_MAIN_GPIO_PORT
 
- TEGRA186_MAIN_GPIO_PORT_A
 
- TEGRA186_MAIN_GPIO_PORT_B
 
- TEGRA186_MAIN_GPIO_PORT_BB
 
- TEGRA186_MAIN_GPIO_PORT_C
 
- TEGRA186_MAIN_GPIO_PORT_CC
 
- TEGRA186_MAIN_GPIO_PORT_D
 
- TEGRA186_MAIN_GPIO_PORT_E
 
- TEGRA186_MAIN_GPIO_PORT_F
 
- TEGRA186_MAIN_GPIO_PORT_G
 
- TEGRA186_MAIN_GPIO_PORT_H
 
- TEGRA186_MAIN_GPIO_PORT_I
 
- TEGRA186_MAIN_GPIO_PORT_J
 
- TEGRA186_MAIN_GPIO_PORT_K
 
- TEGRA186_MAIN_GPIO_PORT_L
 
- TEGRA186_MAIN_GPIO_PORT_M
 
- TEGRA186_MAIN_GPIO_PORT_N
 
- TEGRA186_MAIN_GPIO_PORT_O
 
- TEGRA186_MAIN_GPIO_PORT_P
 
- TEGRA186_MAIN_GPIO_PORT_Q
 
- TEGRA186_MAIN_GPIO_PORT_R
 
- TEGRA186_MAIN_GPIO_PORT_T
 
- TEGRA186_MAIN_GPIO_PORT_X
 
- TEGRA186_MAIN_GPIO_PORT_Y
 
- TEGRA186_MC_BASE
 
- TEGRA186_POWER_DOMAIN_AUD
 
- TEGRA186_POWER_DOMAIN_DFD
 
- TEGRA186_POWER_DOMAIN_DISP
 
- TEGRA186_POWER_DOMAIN_DISPB
 
- TEGRA186_POWER_DOMAIN_DISPC
 
- TEGRA186_POWER_DOMAIN_GPU
 
- TEGRA186_POWER_DOMAIN_ISPA
 
- TEGRA186_POWER_DOMAIN_MAX
 
- TEGRA186_POWER_DOMAIN_MPE
 
- TEGRA186_POWER_DOMAIN_NVDEC
 
- TEGRA186_POWER_DOMAIN_NVJPG
 
- TEGRA186_POWER_DOMAIN_PCX
 
- TEGRA186_POWER_DOMAIN_SAX
 
- TEGRA186_POWER_DOMAIN_VE
 
- TEGRA186_POWER_DOMAIN_VIC
 
- TEGRA186_POWER_DOMAIN_XUSBA
 
- TEGRA186_POWER_DOMAIN_XUSBB
 
- TEGRA186_POWER_DOMAIN_XUSBC
 
- TEGRA186_RESET_ACTMON
 
- TEGRA186_RESET_ADSP
 
- TEGRA186_RESET_ADSPDBG
 
- TEGRA186_RESET_ADSPINTF
 
- TEGRA186_RESET_ADSPNEON
 
- TEGRA186_RESET_ADSPPERIPH
 
- TEGRA186_RESET_ADSPSCU
 
- TEGRA186_RESET_ADSPWDT
 
- TEGRA186_RESET_ADSP_ALL
 
- TEGRA186_RESET_AFI
 
- TEGRA186_RESET_AON_ACTMON
 
- TEGRA186_RESET_AON_APB
 
- TEGRA186_RESET_AON_DBGRESETN
 
- TEGRA186_RESET_AON_DMA
 
- TEGRA186_RESET_AON_GPIO
 
- TEGRA186_RESET_AON_GTE
 
- TEGRA186_RESET_AON_HSP
 
- TEGRA186_RESET_AON_NIC
 
- TEGRA186_RESET_AON_NRESET
 
- TEGRA186_RESET_AON_NSYSPORESET
 
- TEGRA186_RESET_AON_PRESETDBGN
 
- TEGRA186_RESET_AON_TKE
 
- TEGRA186_RESET_AOPM
 
- TEGRA186_RESET_AOVC
 
- TEGRA186_RESET_APE
 
- TEGRA186_RESET_AUD_MCLK
 
- TEGRA186_RESET_AXI_CBB
 
- TEGRA186_RESET_BPMP_APB
 
- TEGRA186_RESET_BPMP_CVC
 
- TEGRA186_RESET_BPMP_DBGRESETN
 
- TEGRA186_RESET_BPMP_DMA
 
- TEGRA186_RESET_BPMP_GTE
 
- TEGRA186_RESET_BPMP_HSP
 
- TEGRA186_RESET_BPMP_NIC
 
- TEGRA186_RESET_BPMP_NRESET
 
- TEGRA186_RESET_BPMP_NSYSPORESET
 
- TEGRA186_RESET_BPMP_PM
 
- TEGRA186_RESET_BPMP_PM_ACTMON
 
- TEGRA186_RESET_BPMP_PRESETDBGN
 
- TEGRA186_RESET_BPMP_TKE
 
- TEGRA186_RESET_CAN1
 
- TEGRA186_RESET_CAN2
 
- TEGRA186_RESET_CEC
 
- TEGRA186_RESET_CSITE
 
- TEGRA186_RESET_DMIC5
 
- TEGRA186_RESET_DP2
 
- TEGRA186_RESET_DPAUX
 
- TEGRA186_RESET_DPAUX1
 
- TEGRA186_RESET_DSI
 
- TEGRA186_RESET_DSIB
 
- TEGRA186_RESET_DSIC
 
- TEGRA186_RESET_DSID
 
- TEGRA186_RESET_DSIPADCTL
 
- TEGRA186_RESET_DTV
 
- TEGRA186_RESET_DVFS
 
- TEGRA186_RESET_EMCSB_EMC
 
- TEGRA186_RESET_EMCSB_MEM
 
- TEGRA186_RESET_EMC_EMC
 
- TEGRA186_RESET_EMC_MEM
 
- TEGRA186_RESET_ENTROPY
 
- TEGRA186_RESET_EQOS
 
- TEGRA186_RESET_EXTPERIPH1
 
- TEGRA186_RESET_EXTPERIPH2
 
- TEGRA186_RESET_EXTPERIPH3
 
- TEGRA186_RESET_EXTPERIPH4
 
- TEGRA186_RESET_GPCDMA
 
- TEGRA186_RESET_GPIO_CTL0
 
- TEGRA186_RESET_GPIO_CTL1
 
- TEGRA186_RESET_GPIO_CTL2
 
- TEGRA186_RESET_GPIO_CTL3
 
- TEGRA186_RESET_GPIO_CTL4
 
- TEGRA186_RESET_GPIO_CTL5
 
- TEGRA186_RESET_GPU
 
- TEGRA186_RESET_HDA
 
- TEGRA186_RESET_HDA2CODEC_2X
 
- TEGRA186_RESET_HDA2HDMICODEC
 
- TEGRA186_RESET_HOST1X
 
- TEGRA186_RESET_I2C1
 
- TEGRA186_RESET_I2C10
 
- TEGRA186_RESET_I2C12
 
- TEGRA186_RESET_I2C13
 
- TEGRA186_RESET_I2C14
 
- TEGRA186_RESET_I2C2
 
- TEGRA186_RESET_I2C3
 
- TEGRA186_RESET_I2C4
 
- TEGRA186_RESET_I2C5
 
- TEGRA186_RESET_I2C6
 
- TEGRA186_RESET_I2C7
 
- TEGRA186_RESET_I2C8
 
- TEGRA186_RESET_I2C9
 
- TEGRA186_RESET_ISP
 
- TEGRA186_RESET_JTAG2AXI
 
- TEGRA186_RESET_KFUSE
 
- TEGRA186_RESET_LA
 
- TEGRA186_RESET_MIPI_CAL
 
- TEGRA186_RESET_MPHY_CLK_CTL
 
- TEGRA186_RESET_MPHY_IOBIST
 
- TEGRA186_RESET_MPHY_L0_RX
 
- TEGRA186_RESET_MPHY_L0_TX
 
- TEGRA186_RESET_MPHY_L1_RX
 
- TEGRA186_RESET_MPHY_L1_TX
 
- TEGRA186_RESET_NVCSI
 
- TEGRA186_RESET_NVDEC
 
- TEGRA186_RESET_NVDISPLAY0_HEAD0
 
- TEGRA186_RESET_NVDISPLAY0_HEAD1
 
- TEGRA186_RESET_NVDISPLAY0_HEAD2
 
- TEGRA186_RESET_NVDISPLAY0_MISC
 
- TEGRA186_RESET_NVDISPLAY0_WGRP0
 
- TEGRA186_RESET_NVDISPLAY0_WGRP1
 
- TEGRA186_RESET_NVDISPLAY0_WGRP2
 
- TEGRA186_RESET_NVDISPLAY0_WGRP3
 
- TEGRA186_RESET_NVDISPLAY0_WGRP4
 
- TEGRA186_RESET_NVDISPLAY0_WGRP5
 
- TEGRA186_RESET_NVENC
 
- TEGRA186_RESET_NVJPG
 
- TEGRA186_RESET_PCIE
 
- TEGRA186_RESET_PCIEXCLK
 
- TEGRA186_RESET_PEX_USB_UPHY
 
- TEGRA186_RESET_PEX_USB_UPHY_L0
 
- TEGRA186_RESET_PEX_USB_UPHY_L1
 
- TEGRA186_RESET_PEX_USB_UPHY_L2
 
- TEGRA186_RESET_PEX_USB_UPHY_L3
 
- TEGRA186_RESET_PEX_USB_UPHY_L4
 
- TEGRA186_RESET_PEX_USB_UPHY_L5
 
- TEGRA186_RESET_PEX_USB_UPHY_PLL0
 
- TEGRA186_RESET_PEX_USB_UPHY_PLL1
 
- TEGRA186_RESET_PWM1
 
- TEGRA186_RESET_PWM2
 
- TEGRA186_RESET_PWM3
 
- TEGRA186_RESET_PWM4
 
- TEGRA186_RESET_PWM5
 
- TEGRA186_RESET_PWM6
 
- TEGRA186_RESET_PWM7
 
- TEGRA186_RESET_PWM8
 
- TEGRA186_RESET_QSPI
 
- TEGRA186_RESET_SATA
 
- TEGRA186_RESET_SATACOLD
 
- TEGRA186_RESET_SCE_ACTMON
 
- TEGRA186_RESET_SCE_APB
 
- TEGRA186_RESET_SCE_CFG
 
- TEGRA186_RESET_SCE_DBGRESETN
 
- TEGRA186_RESET_SCE_DMA
 
- TEGRA186_RESET_SCE_GTE
 
- TEGRA186_RESET_SCE_HSP
 
- TEGRA186_RESET_SCE_NIC
 
- TEGRA186_RESET_SCE_NRESET
 
- TEGRA186_RESET_SCE_NSYSPORESET
 
- TEGRA186_RESET_SCE_PM
 
- TEGRA186_RESET_SCE_PRESETDBGN
 
- TEGRA186_RESET_SCE_TKE
 
- TEGRA186_RESET_SDMMC1
 
- TEGRA186_RESET_SDMMC2
 
- TEGRA186_RESET_SDMMC3
 
- TEGRA186_RESET_SDMMC4
 
- TEGRA186_RESET_SE
 
- TEGRA186_RESET_SHSP
 
- TEGRA186_RESET_SIZE
 
- TEGRA186_RESET_SOC_THERM
 
- TEGRA186_RESET_SOR0
 
- TEGRA186_RESET_SOR1
 
- TEGRA186_RESET_SPI1
 
- TEGRA186_RESET_SPI2
 
- TEGRA186_RESET_SPI3
 
- TEGRA186_RESET_SPI4
 
- TEGRA186_RESET_TACH
 
- TEGRA186_RESET_TMR
 
- TEGRA186_RESET_TOP_GTE
 
- TEGRA186_RESET_TRIG_SYS
 
- TEGRA186_RESET_TSC
 
- TEGRA186_RESET_TSCTNAON
 
- TEGRA186_RESET_TSCTNBPMP
 
- TEGRA186_RESET_TSCTNSCE
 
- TEGRA186_RESET_TSCTNVI
 
- TEGRA186_RESET_TSEC
 
- TEGRA186_RESET_TSECB
 
- TEGRA186_RESET_UARTA
 
- TEGRA186_RESET_UARTB
 
- TEGRA186_RESET_UARTC
 
- TEGRA186_RESET_UARTD
 
- TEGRA186_RESET_UARTE
 
- TEGRA186_RESET_UARTF
 
- TEGRA186_RESET_UARTG
 
- TEGRA186_RESET_UFSHC
 
- TEGRA186_RESET_UFSHC_AXI_M
 
- TEGRA186_RESET_UFSHC_LP
 
- TEGRA186_RESET_UFSHC_LP_SEQ
 
- TEGRA186_RESET_UPHY
 
- TEGRA186_RESET_VI
 
- TEGRA186_RESET_VIC
 
- TEGRA186_RESET_VI_I2C
 
- TEGRA186_RESET_XUSB_DEV
 
- TEGRA186_RESET_XUSB_HOST
 
- TEGRA186_RESET_XUSB_PADCTL
 
- TEGRA186_RESET_XUSB_SS
 
- TEGRA186_SID_AFI
 
- TEGRA186_SID_AON
 
- TEGRA186_SID_APE
 
- TEGRA186_SID_APE_1
 
- TEGRA186_SID_APE_2
 
- TEGRA186_SID_APE_3
 
- TEGRA186_SID_APE_CAM
 
- TEGRA186_SID_APE_CAM_1X
 
- TEGRA186_SID_BPMP
 
- TEGRA186_SID_CSI
 
- TEGRA186_SID_EQOS
 
- TEGRA186_SID_ETR
 
- TEGRA186_SID_GPCDMA_0
 
- TEGRA186_SID_GPCDMA_1
 
- TEGRA186_SID_GPCDMA_2
 
- TEGRA186_SID_GPCDMA_3
 
- TEGRA186_SID_GPCDMA_4
 
- TEGRA186_SID_GPCDMA_5
 
- TEGRA186_SID_GPCDMA_6
 
- TEGRA186_SID_GPCDMA_7
 
- TEGRA186_SID_GPU
 
- TEGRA186_SID_HDA
 
- TEGRA186_SID_HOST1X
 
- TEGRA186_SID_HOST1X_CTX0
 
- TEGRA186_SID_HOST1X_CTX1
 
- TEGRA186_SID_HOST1X_CTX2
 
- TEGRA186_SID_HOST1X_CTX3
 
- TEGRA186_SID_HOST1X_CTX4
 
- TEGRA186_SID_HOST1X_CTX5
 
- TEGRA186_SID_HOST1X_CTX6
 
- TEGRA186_SID_HOST1X_CTX7
 
- TEGRA186_SID_HOST1X_VM0
 
- TEGRA186_SID_HOST1X_VM1
 
- TEGRA186_SID_HOST1X_VM2
 
- TEGRA186_SID_HOST1X_VM3
 
- TEGRA186_SID_HOST1X_VM4
 
- TEGRA186_SID_HOST1X_VM5
 
- TEGRA186_SID_HOST1X_VM6
 
- TEGRA186_SID_HOST1X_VM7
 
- TEGRA186_SID_INVALID
 
- TEGRA186_SID_ISP
 
- TEGRA186_SID_NVDEC
 
- TEGRA186_SID_NVDISPLAY
 
- TEGRA186_SID_NVENC
 
- TEGRA186_SID_NVJPG
 
- TEGRA186_SID_PASSTHROUGH
 
- TEGRA186_SID_RCE
 
- TEGRA186_SID_RCE_1X
 
- TEGRA186_SID_SATA
 
- TEGRA186_SID_SCE
 
- TEGRA186_SID_SDMMC1
 
- TEGRA186_SID_SDMMC2
 
- TEGRA186_SID_SDMMC3
 
- TEGRA186_SID_SDMMC4
 
- TEGRA186_SID_SE
 
- TEGRA186_SID_SE1
 
- TEGRA186_SID_SE2
 
- TEGRA186_SID_SE3
 
- TEGRA186_SID_SE_VM0
 
- TEGRA186_SID_SE_VM1
 
- TEGRA186_SID_SE_VM2
 
- TEGRA186_SID_SE_VM3
 
- TEGRA186_SID_SE_VM4
 
- TEGRA186_SID_SE_VM5
 
- TEGRA186_SID_SE_VM6
 
- TEGRA186_SID_SE_VM7
 
- TEGRA186_SID_SMMU_TEST
 
- TEGRA186_SID_TSEC
 
- TEGRA186_SID_TSECB
 
- TEGRA186_SID_UFSHC
 
- TEGRA186_SID_VI
 
- TEGRA186_SID_VIC
 
- TEGRA186_SID_XUSB_DEV
 
- TEGRA186_SID_XUSB_HOST
 
- TEGRA194_AON_GPIO
 
- TEGRA194_AON_GPIO_PORT
 
- TEGRA194_AON_GPIO_PORT_AA
 
- TEGRA194_AON_GPIO_PORT_BB
 
- TEGRA194_AON_GPIO_PORT_CC
 
- TEGRA194_AON_GPIO_PORT_DD
 
- TEGRA194_AON_GPIO_PORT_EE
 
- TEGRA194_BPMP_THERMAL_ZONE_AO
 
- TEGRA194_BPMP_THERMAL_ZONE_AUX
 
- TEGRA194_BPMP_THERMAL_ZONE_CPU
 
- TEGRA194_BPMP_THERMAL_ZONE_GPU
 
- TEGRA194_BPMP_THERMAL_ZONE_PLLX
 
- TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX
 
- TEGRA194_CLK_ACLK
 
- TEGRA194_CLK_ACTMON
 
- TEGRA194_CLK_ADSP
 
- TEGRA194_CLK_ADSPNEON
 
- TEGRA194_CLK_AHUB
 
- TEGRA194_CLK_AON_APB
 
- TEGRA194_CLK_AON_CPU_NIC
 
- TEGRA194_CLK_AON_I2C_SLOW
 
- TEGRA194_CLK_AON_NIC
 
- TEGRA194_CLK_AON_TOUCH
 
- TEGRA194_CLK_APB2APE
 
- TEGRA194_CLK_APE
 
- TEGRA194_CLK_AUD_MCLK
 
- TEGRA194_CLK_AXI_CBB
 
- TEGRA194_CLK_BPMP_APB
 
- TEGRA194_CLK_BPMP_CPU_NIC
 
- TEGRA194_CLK_CAN1
 
- TEGRA194_CLK_CAN1_CORE
 
- TEGRA194_CLK_CAN1_HOST
 
- TEGRA194_CLK_CAN2
 
- TEGRA194_CLK_CAN2_CORE
 
- TEGRA194_CLK_CAN2_HOST
 
- TEGRA194_CLK_CEC
 
- TEGRA194_CLK_CLK_32K
 
- TEGRA194_CLK_CLK_M
 
- TEGRA194_CLK_CSI_A
 
- TEGRA194_CLK_CSI_A_PAD
 
- TEGRA194_CLK_CSI_B
 
- TEGRA194_CLK_CSI_B_PAD
 
- TEGRA194_CLK_CSI_C
 
- TEGRA194_CLK_CSI_C_PAD
 
- TEGRA194_CLK_CSI_D
 
- TEGRA194_CLK_CSI_D_PAD
 
- TEGRA194_CLK_CSI_E
 
- TEGRA194_CLK_CSI_E_PAD
 
- TEGRA194_CLK_CSI_F
 
- TEGRA194_CLK_CSI_F_PAD
 
- TEGRA194_CLK_CSI_G
 
- TEGRA194_CLK_CSI_G_PAD
 
- TEGRA194_CLK_CSI_H
 
- TEGRA194_CLK_CSI_H_PAD
 
- TEGRA194_CLK_CVNAS
 
- TEGRA194_CLK_DLA0_CORE
 
- TEGRA194_CLK_DLA0_CORE_MUX
 
- TEGRA194_CLK_DLA0_FALCON
 
- TEGRA194_CLK_DLA0_FALCON_MUX
 
- TEGRA194_CLK_DLA1_CORE
 
- TEGRA194_CLK_DLA1_CORE_MUX
 
- TEGRA194_CLK_DLA1_FALCON
 
- TEGRA194_CLK_DLA1_FALCON_MUX
 
- TEGRA194_CLK_DMIC1
 
- TEGRA194_CLK_DMIC2
 
- TEGRA194_CLK_DMIC3
 
- TEGRA194_CLK_DMIC4
 
- TEGRA194_CLK_DMIC5
 
- TEGRA194_CLK_DPAUX
 
- TEGRA194_CLK_DPAUX1
 
- TEGRA194_CLK_DPAUX2
 
- TEGRA194_CLK_DPAUX3
 
- TEGRA194_CLK_DSPK1
 
- TEGRA194_CLK_DSPK2
 
- TEGRA194_CLK_EMC
 
- TEGRA194_CLK_EMCSA
 
- TEGRA194_CLK_EMCSB
 
- TEGRA194_CLK_EMCSC
 
- TEGRA194_CLK_EMCSD
 
- TEGRA194_CLK_EQOS_AXI
 
- TEGRA194_CLK_EQOS_PTP_REF
 
- TEGRA194_CLK_EQOS_RX
 
- TEGRA194_CLK_EQOS_RX_INPUT
 
- TEGRA194_CLK_EQOS_TX
 
- TEGRA194_CLK_EXTPERIPH1
 
- TEGRA194_CLK_EXTPERIPH2
 
- TEGRA194_CLK_EXTPERIPH3
 
- TEGRA194_CLK_EXTPERIPH4
 
- TEGRA194_CLK_FUSE
 
- TEGRA194_CLK_FUSE_BURN
 
- TEGRA194_CLK_FUSE_SERIAL
 
- TEGRA194_CLK_GPCCLK
 
- TEGRA194_CLK_GPU_PWR
 
- TEGRA194_CLK_HDA
 
- TEGRA194_CLK_HDA2CODEC_2X
 
- TEGRA194_CLK_HDA2HDMICODEC
 
- TEGRA194_CLK_HOST1X
 
- TEGRA194_CLK_HSIC_TRK
 
- TEGRA194_CLK_I2C1
 
- TEGRA194_CLK_I2C10
 
- TEGRA194_CLK_I2C2
 
- TEGRA194_CLK_I2C3
 
- TEGRA194_CLK_I2C4
 
- TEGRA194_CLK_I2C5
 
- TEGRA194_CLK_I2C6
 
- TEGRA194_CLK_I2C7
 
- TEGRA194_CLK_I2C8
 
- TEGRA194_CLK_I2C9
 
- TEGRA194_CLK_I2C_SLOW
 
- TEGRA194_CLK_I2S1
 
- TEGRA194_CLK_I2S1_SYNC_INPUT
 
- TEGRA194_CLK_I2S2
 
- TEGRA194_CLK_I2S2_SYNC_INPUT
 
- TEGRA194_CLK_I2S3
 
- TEGRA194_CLK_I2S3_SYNC_INPUT
 
- TEGRA194_CLK_I2S4
 
- TEGRA194_CLK_I2S4_SYNC_INPUT
 
- TEGRA194_CLK_I2S5
 
- TEGRA194_CLK_I2S5_SYNC_INPUT
 
- TEGRA194_CLK_I2S6
 
- TEGRA194_CLK_I2S6_SYNC_INPUT
 
- TEGRA194_CLK_IQC1
 
- TEGRA194_CLK_IQC1_IN
 
- TEGRA194_CLK_IQC2
 
- TEGRA194_CLK_IQC2_IN
 
- TEGRA194_CLK_ISP
 
- TEGRA194_CLK_KFUSE
 
- TEGRA194_CLK_MAUD
 
- TEGRA194_CLK_MIPI_CAL
 
- TEGRA194_CLK_MPHY_CORE_PLL_FIXED
 
- TEGRA194_CLK_MPHY_FORCE_LS_MODE
 
- TEGRA194_CLK_MPHY_L0_RX_ANA
 
- TEGRA194_CLK_MPHY_L0_RX_LS_BIT
 
- TEGRA194_CLK_MPHY_L0_RX_SYMB
 
- TEGRA194_CLK_MPHY_L0_TX_LS_3XBIT
 
- TEGRA194_CLK_MPHY_L0_TX_SYMB
 
- TEGRA194_CLK_MPHY_L1_RX_ANA
 
- TEGRA194_CLK_MPHY_TX_1MHZ_REF
 
- TEGRA194_CLK_MSS_ENCRYPT
 
- TEGRA194_CLK_NAFLL_AXICBB
 
- TEGRA194_CLK_NAFLL_BPMP
 
- TEGRA194_CLK_NAFLL_CLUSTER0
 
- TEGRA194_CLK_NAFLL_CLUSTER1
 
- TEGRA194_CLK_NAFLL_CLUSTER2
 
- TEGRA194_CLK_NAFLL_CLUSTER3
 
- TEGRA194_CLK_NAFLL_CVNAS
 
- TEGRA194_CLK_NAFLL_DLA
 
- TEGRA194_CLK_NAFLL_DLA_FALCON
 
- TEGRA194_CLK_NAFLL_GPU
 
- TEGRA194_CLK_NAFLL_ISP
 
- TEGRA194_CLK_NAFLL_NVDEC
 
- TEGRA194_CLK_NAFLL_NVDEC1
 
- TEGRA194_CLK_NAFLL_NVDISPLAYHUB
 
- TEGRA194_CLK_NAFLL_NVENC
 
- TEGRA194_CLK_NAFLL_NVENC1
 
- TEGRA194_CLK_NAFLL_NVJPG
 
- TEGRA194_CLK_NAFLL_PVA_CORE
 
- TEGRA194_CLK_NAFLL_PVA_VPS
 
- TEGRA194_CLK_NAFLL_RCE
 
- TEGRA194_CLK_NAFLL_SCE
 
- TEGRA194_CLK_NAFLL_SE
 
- TEGRA194_CLK_NAFLL_TSEC
 
- TEGRA194_CLK_NAFLL_TSECB
 
- TEGRA194_CLK_NAFLL_VI
 
- TEGRA194_CLK_NAFLL_VIC
 
- TEGRA194_CLK_NVCSI
 
- TEGRA194_CLK_NVCSILP
 
- TEGRA194_CLK_NVDEC
 
- TEGRA194_CLK_NVDEC1
 
- TEGRA194_CLK_NVDISPLAYHUB
 
- TEGRA194_CLK_NVDISPLAY_DISP
 
- TEGRA194_CLK_NVDISPLAY_P0
 
- TEGRA194_CLK_NVDISPLAY_P1
 
- TEGRA194_CLK_NVDISPLAY_P2
 
- TEGRA194_CLK_NVDISPLAY_P3
 
- TEGRA194_CLK_NVENC
 
- TEGRA194_CLK_NVENC1
 
- TEGRA194_CLK_NVJPG
 
- TEGRA194_CLK_OSC
 
- TEGRA194_CLK_PEX0_CORE_0
 
- TEGRA194_CLK_PEX0_CORE_0M
 
- TEGRA194_CLK_PEX0_CORE_1
 
- TEGRA194_CLK_PEX0_CORE_1M
 
- TEGRA194_CLK_PEX0_CORE_2
 
- TEGRA194_CLK_PEX0_CORE_2M
 
- TEGRA194_CLK_PEX0_CORE_3
 
- TEGRA194_CLK_PEX0_CORE_3M
 
- TEGRA194_CLK_PEX0_CORE_4
 
- TEGRA194_CLK_PEX0_CORE_4M
 
- TEGRA194_CLK_PEX1_CORE_5
 
- TEGRA194_CLK_PEX1_CORE_5M
 
- TEGRA194_CLK_PEX_REF1
 
- TEGRA194_CLK_PEX_REF2
 
- TEGRA194_CLK_PEX_SATA_USB_RX_BYP
 
- TEGRA194_CLK_PEX_USB_PAD_PLL0_MGMT
 
- TEGRA194_CLK_PEX_USB_PAD_PLL1_MGMT
 
- TEGRA194_CLK_PEX_USB_PAD_PLL2_MGMT
 
- TEGRA194_CLK_PEX_USB_PAD_PLL3_MGMT
 
- TEGRA194_CLK_PLLA
 
- TEGRA194_CLK_PLLA1
 
- TEGRA194_CLK_PLLA1_OUT1
 
- TEGRA194_CLK_PLLAON
 
- TEGRA194_CLK_PLLA_OUT0
 
- TEGRA194_CLK_PLLC
 
- TEGRA194_CLK_PLLC2
 
- TEGRA194_CLK_PLLC3
 
- TEGRA194_CLK_PLLC4
 
- TEGRA194_CLK_PLLC4_MUXED
 
- TEGRA194_CLK_PLLC4_OUT
 
- TEGRA194_CLK_PLLC4_OUT1
 
- TEGRA194_CLK_PLLC4_OUT2
 
- TEGRA194_CLK_PLLC4_VCO_DIV2
 
- TEGRA194_CLK_PLLD
 
- TEGRA194_CLK_PLLD2
 
- TEGRA194_CLK_PLLD3
 
- TEGRA194_CLK_PLLD4
 
- TEGRA194_CLK_PLLDISPHUB
 
- TEGRA194_CLK_PLLDISPHUB_DIV
 
- TEGRA194_CLK_PLLDP
 
- TEGRA194_CLK_PLLE
 
- TEGRA194_CLK_PLLE_HPS
 
- TEGRA194_CLK_PLLNVCSI
 
- TEGRA194_CLK_PLLP
 
- TEGRA194_CLK_PLLP_OUT0
 
- TEGRA194_CLK_PLLREFE_VCOOUT
 
- TEGRA194_CLK_PVA0_AXI
 
- TEGRA194_CLK_PVA0_CPU_AXI
 
- TEGRA194_CLK_PVA0_VPS
 
- TEGRA194_CLK_PVA0_VPS0
 
- TEGRA194_CLK_PVA0_VPS1
 
- TEGRA194_CLK_PVA1_AXI
 
- TEGRA194_CLK_PVA1_CPU_AXI
 
- TEGRA194_CLK_PVA1_VPS
 
- TEGRA194_CLK_PVA1_VPS0
 
- TEGRA194_CLK_PVA1_VPS1
 
- TEGRA194_CLK_PWM1
 
- TEGRA194_CLK_PWM2
 
- TEGRA194_CLK_PWM3
 
- TEGRA194_CLK_PWM4
 
- TEGRA194_CLK_PWM5
 
- TEGRA194_CLK_PWM6
 
- TEGRA194_CLK_PWM7
 
- TEGRA194_CLK_PWM8
 
- TEGRA194_CLK_QSPI0
 
- TEGRA194_CLK_QSPI0_PM
 
- TEGRA194_CLK_QSPI1
 
- TEGRA194_CLK_QSPI1_PM
 
- TEGRA194_CLK_RCE_CPU_NIC
 
- TEGRA194_CLK_RCE_NIC
 
- TEGRA194_CLK_SATA
 
- TEGRA194_CLK_SATA_OOB
 
- TEGRA194_CLK_SCE_CPU_NIC
 
- TEGRA194_CLK_SCE_NIC
 
- TEGRA194_CLK_SDMMC1
 
- TEGRA194_CLK_SDMMC3
 
- TEGRA194_CLK_SDMMC4
 
- TEGRA194_CLK_SDMMC_LEGACY_TM
 
- TEGRA194_CLK_SE
 
- TEGRA194_CLK_SE_FREE
 
- TEGRA194_CLK_SOR0_OUT
 
- TEGRA194_CLK_SOR0_PAD_CLKOUT
 
- TEGRA194_CLK_SOR0_REF
 
- TEGRA194_CLK_SOR1_OUT
 
- TEGRA194_CLK_SOR1_PAD_CLKOUT
 
- TEGRA194_CLK_SOR1_REF
 
- TEGRA194_CLK_SOR2_OUT
 
- TEGRA194_CLK_SOR2_PAD_CLKOUT
 
- TEGRA194_CLK_SOR2_REF
 
- TEGRA194_CLK_SOR3_OUT
 
- TEGRA194_CLK_SOR3_PAD_CLKOUT
 
- TEGRA194_CLK_SOR3_REF
 
- TEGRA194_CLK_SOR_SAFE
 
- TEGRA194_CLK_SPDIFIN_SYNC_INPUT
 
- TEGRA194_CLK_SPI1
 
- TEGRA194_CLK_SPI2
 
- TEGRA194_CLK_SPI3
 
- TEGRA194_CLK_SYNC_DMIC1
 
- TEGRA194_CLK_SYNC_DMIC2
 
- TEGRA194_CLK_SYNC_DMIC3
 
- TEGRA194_CLK_SYNC_DMIC4
 
- TEGRA194_CLK_SYNC_DSPK1
 
- TEGRA194_CLK_SYNC_DSPK2
 
- TEGRA194_CLK_SYNC_I2S1
 
- TEGRA194_CLK_SYNC_I2S2
 
- TEGRA194_CLK_SYNC_I2S3
 
- TEGRA194_CLK_SYNC_I2S4
 
- TEGRA194_CLK_SYNC_I2S5
 
- TEGRA194_CLK_SYNC_I2S6
 
- TEGRA194_CLK_TACH
 
- TEGRA194_CLK_TSC
 
- TEGRA194_CLK_TSC_REF
 
- TEGRA194_CLK_TSEC
 
- TEGRA194_CLK_TSECB
 
- TEGRA194_CLK_UARTA
 
- TEGRA194_CLK_UARTB
 
- TEGRA194_CLK_UARTC
 
- TEGRA194_CLK_UARTD
 
- TEGRA194_CLK_UARTE
 
- TEGRA194_CLK_UARTF
 
- TEGRA194_CLK_UARTG
 
- TEGRA194_CLK_UARTH
 
- TEGRA194_CLK_UART_FST_MIPI_CAL
 
- TEGRA194_CLK_UFSDEV_REF
 
- TEGRA194_CLK_UFSHC
 
- TEGRA194_CLK_UPHY_PLL3
 
- TEGRA194_CLK_USB2_TRK
 
- TEGRA194_CLK_UTMIPLL
 
- TEGRA194_CLK_UTMIPLL_CLKOUT48
 
- TEGRA194_CLK_UTMIPLL_CLKOUT480
 
- TEGRA194_CLK_UTMIPLL_HPS
 
- TEGRA194_CLK_VI
 
- TEGRA194_CLK_VIC
 
- TEGRA194_CLK_VI_CONST
 
- TEGRA194_CLK_XUSB_CORE_DEV
 
- TEGRA194_CLK_XUSB_CORE_HOST
 
- TEGRA194_CLK_XUSB_CORE_MUX
 
- TEGRA194_CLK_XUSB_CORE_SS
 
- TEGRA194_CLK_XUSB_FALCON
 
- TEGRA194_CLK_XUSB_FALCON_HOST
 
- TEGRA194_CLK_XUSB_FALCON_SS
 
- TEGRA194_CLK_XUSB_FS
 
- TEGRA194_CLK_XUSB_FS_DEV
 
- TEGRA194_CLK_XUSB_FS_HOST
 
- TEGRA194_CLK_XUSB_SS
 
- TEGRA194_CLK_XUSB_SS_DEV
 
- TEGRA194_CLK_XUSB_SS_SUPERSPEED
 
- TEGRA194_MAIN_GPIO
 
- TEGRA194_MAIN_GPIO_PORT
 
- TEGRA194_MAIN_GPIO_PORT_A
 
- TEGRA194_MAIN_GPIO_PORT_B
 
- TEGRA194_MAIN_GPIO_PORT_C
 
- TEGRA194_MAIN_GPIO_PORT_D
 
- TEGRA194_MAIN_GPIO_PORT_E
 
- TEGRA194_MAIN_GPIO_PORT_F
 
- TEGRA194_MAIN_GPIO_PORT_FF
 
- TEGRA194_MAIN_GPIO_PORT_G
 
- TEGRA194_MAIN_GPIO_PORT_GG
 
- TEGRA194_MAIN_GPIO_PORT_H
 
- TEGRA194_MAIN_GPIO_PORT_I
 
- TEGRA194_MAIN_GPIO_PORT_J
 
- TEGRA194_MAIN_GPIO_PORT_K
 
- TEGRA194_MAIN_GPIO_PORT_L
 
- TEGRA194_MAIN_GPIO_PORT_M
 
- TEGRA194_MAIN_GPIO_PORT_N
 
- TEGRA194_MAIN_GPIO_PORT_O
 
- TEGRA194_MAIN_GPIO_PORT_P
 
- TEGRA194_MAIN_GPIO_PORT_Q
 
- TEGRA194_MAIN_GPIO_PORT_R
 
- TEGRA194_MAIN_GPIO_PORT_S
 
- TEGRA194_MAIN_GPIO_PORT_T
 
- TEGRA194_MAIN_GPIO_PORT_U
 
- TEGRA194_MAIN_GPIO_PORT_V
 
- TEGRA194_MAIN_GPIO_PORT_W
 
- TEGRA194_MAIN_GPIO_PORT_X
 
- TEGRA194_MAIN_GPIO_PORT_Y
 
- TEGRA194_MAIN_GPIO_PORT_Z
 
- TEGRA194_POWER_DOMAIN_AUD
 
- TEGRA194_POWER_DOMAIN_CV
 
- TEGRA194_POWER_DOMAIN_DISP
 
- TEGRA194_POWER_DOMAIN_DISPB
 
- TEGRA194_POWER_DOMAIN_DISPC
 
- TEGRA194_POWER_DOMAIN_DLAA
 
- TEGRA194_POWER_DOMAIN_DLAB
 
- TEGRA194_POWER_DOMAIN_GPU
 
- TEGRA194_POWER_DOMAIN_ISPA
 
- TEGRA194_POWER_DOMAIN_MAX
 
- TEGRA194_POWER_DOMAIN_NVDECA
 
- TEGRA194_POWER_DOMAIN_NVDECB
 
- TEGRA194_POWER_DOMAIN_NVENCA
 
- TEGRA194_POWER_DOMAIN_NVENCB
 
- TEGRA194_POWER_DOMAIN_NVJPG
 
- TEGRA194_POWER_DOMAIN_PCIEX1A
 
- TEGRA194_POWER_DOMAIN_PCIEX4A
 
- TEGRA194_POWER_DOMAIN_PCIEX8A
 
- TEGRA194_POWER_DOMAIN_PCIEX8B
 
- TEGRA194_POWER_DOMAIN_PVAA
 
- TEGRA194_POWER_DOMAIN_PVAB
 
- TEGRA194_POWER_DOMAIN_SAX
 
- TEGRA194_POWER_DOMAIN_VE
 
- TEGRA194_POWER_DOMAIN_VIC
 
- TEGRA194_POWER_DOMAIN_XUSBA
 
- TEGRA194_POWER_DOMAIN_XUSBB
 
- TEGRA194_POWER_DOMAIN_XUSBC
 
- TEGRA194_RESET_ACTMON
 
- TEGRA194_RESET_ADSP_ALL
 
- TEGRA194_RESET_AFI
 
- TEGRA194_RESET_APE
 
- TEGRA194_RESET_CAN1
 
- TEGRA194_RESET_CAN2
 
- TEGRA194_RESET_CVNAS
 
- TEGRA194_RESET_CVNAS_FCM
 
- TEGRA194_RESET_DLA0
 
- TEGRA194_RESET_DLA1
 
- TEGRA194_RESET_DMIC5
 
- TEGRA194_RESET_DPAUX
 
- TEGRA194_RESET_DPAUX1
 
- TEGRA194_RESET_DPAUX2
 
- TEGRA194_RESET_DPAUX3
 
- TEGRA194_RESET_EQOS
 
- TEGRA194_RESET_GPCDMA
 
- TEGRA194_RESET_GPU
 
- TEGRA194_RESET_HDA
 
- TEGRA194_RESET_HDA2CODEC_2X
 
- TEGRA194_RESET_HDA2HDMICODEC
 
- TEGRA194_RESET_HOST1X
 
- TEGRA194_RESET_I2C1
 
- TEGRA194_RESET_I2C10
 
- TEGRA194_RESET_I2C2
 
- TEGRA194_RESET_I2C3
 
- TEGRA194_RESET_I2C4
 
- TEGRA194_RESET_I2C6
 
- TEGRA194_RESET_I2C7
 
- TEGRA194_RESET_I2C8
 
- TEGRA194_RESET_I2C9
 
- TEGRA194_RESET_ISP
 
- TEGRA194_RESET_MIPI_CAL
 
- TEGRA194_RESET_MPHY_CLK_CTL
 
- TEGRA194_RESET_MPHY_L0_RX
 
- TEGRA194_RESET_MPHY_L0_TX
 
- TEGRA194_RESET_MPHY_L1_RX
 
- TEGRA194_RESET_MPHY_L1_TX
 
- TEGRA194_RESET_NVCSI
 
- TEGRA194_RESET_NVDEC
 
- TEGRA194_RESET_NVDEC1
 
- TEGRA194_RESET_NVDISPLAY0_HEAD0
 
- TEGRA194_RESET_NVDISPLAY0_HEAD1
 
- TEGRA194_RESET_NVDISPLAY0_HEAD2
 
- TEGRA194_RESET_NVDISPLAY0_HEAD3
 
- TEGRA194_RESET_NVDISPLAY0_MISC
 
- TEGRA194_RESET_NVDISPLAY0_WGRP0
 
- TEGRA194_RESET_NVDISPLAY0_WGRP1
 
- TEGRA194_RESET_NVDISPLAY0_WGRP2
 
- TEGRA194_RESET_NVDISPLAY0_WGRP3
 
- TEGRA194_RESET_NVDISPLAY0_WGRP4
 
- TEGRA194_RESET_NVDISPLAY0_WGRP5
 
- TEGRA194_RESET_NVENC
 
- TEGRA194_RESET_NVENC1
 
- TEGRA194_RESET_NVJPG
 
- TEGRA194_RESET_PCIE
 
- TEGRA194_RESET_PCIEXCLK
 
- TEGRA194_RESET_PEX0_COMMON_APB
 
- TEGRA194_RESET_PEX0_CORE_0
 
- TEGRA194_RESET_PEX0_CORE_0_APB
 
- TEGRA194_RESET_PEX0_CORE_1
 
- TEGRA194_RESET_PEX0_CORE_1_APB
 
- TEGRA194_RESET_PEX0_CORE_2
 
- TEGRA194_RESET_PEX0_CORE_2_APB
 
- TEGRA194_RESET_PEX0_CORE_3
 
- TEGRA194_RESET_PEX0_CORE_3_APB
 
- TEGRA194_RESET_PEX0_CORE_4
 
- TEGRA194_RESET_PEX0_CORE_4_APB
 
- TEGRA194_RESET_PEX1_CORE_5
 
- TEGRA194_RESET_PEX1_CORE_5_APB
 
- TEGRA194_RESET_PEX_USB_UPHY
 
- TEGRA194_RESET_PEX_USB_UPHY_L0
 
- TEGRA194_RESET_PEX_USB_UPHY_L1
 
- TEGRA194_RESET_PEX_USB_UPHY_L10
 
- TEGRA194_RESET_PEX_USB_UPHY_L11
 
- TEGRA194_RESET_PEX_USB_UPHY_L2
 
- TEGRA194_RESET_PEX_USB_UPHY_L3
 
- TEGRA194_RESET_PEX_USB_UPHY_L4
 
- TEGRA194_RESET_PEX_USB_UPHY_L5
 
- TEGRA194_RESET_PEX_USB_UPHY_L6
 
- TEGRA194_RESET_PEX_USB_UPHY_L7
 
- TEGRA194_RESET_PEX_USB_UPHY_L8
 
- TEGRA194_RESET_PEX_USB_UPHY_L9
 
- TEGRA194_RESET_PEX_USB_UPHY_PLL0
 
- TEGRA194_RESET_PEX_USB_UPHY_PLL1
 
- TEGRA194_RESET_PEX_USB_UPHY_PLL2
 
- TEGRA194_RESET_PEX_USB_UPHY_PLL3
 
- TEGRA194_RESET_PVA0_ALL
 
- TEGRA194_RESET_PVA1_ALL
 
- TEGRA194_RESET_PWM1
 
- TEGRA194_RESET_PWM2
 
- TEGRA194_RESET_PWM3
 
- TEGRA194_RESET_PWM4
 
- TEGRA194_RESET_PWM5
 
- TEGRA194_RESET_PWM6
 
- TEGRA194_RESET_PWM7
 
- TEGRA194_RESET_PWM8
 
- TEGRA194_RESET_QSPI0
 
- TEGRA194_RESET_QSPI1
 
- TEGRA194_RESET_RCE_ALL
 
- TEGRA194_RESET_RSVD_111
 
- TEGRA194_RESET_RSVD_26
 
- TEGRA194_RESET_RSVD_27
 
- TEGRA194_RESET_RSVD_28
 
- TEGRA194_RESET_RSVD_56
 
- TEGRA194_RESET_RSVD_57
 
- TEGRA194_RESET_RSVD_58
 
- TEGRA194_RESET_RSVD_64
 
- TEGRA194_RESET_RSVD_65
 
- TEGRA194_RESET_RSVD_83
 
- TEGRA194_RESET_RSVD_96
 
- TEGRA194_RESET_SATA
 
- TEGRA194_RESET_SATACOLD
 
- TEGRA194_RESET_SCE_ALL
 
- TEGRA194_RESET_SDMMC1
 
- TEGRA194_RESET_SDMMC3
 
- TEGRA194_RESET_SDMMC4
 
- TEGRA194_RESET_SE
 
- TEGRA194_RESET_SOR0
 
- TEGRA194_RESET_SOR1
 
- TEGRA194_RESET_SOR2
 
- TEGRA194_RESET_SOR3
 
- TEGRA194_RESET_SPI1
 
- TEGRA194_RESET_SPI2
 
- TEGRA194_RESET_SPI3
 
- TEGRA194_RESET_SPI4
 
- TEGRA194_RESET_TACH
 
- TEGRA194_RESET_TSCTNVI
 
- TEGRA194_RESET_TSEC
 
- TEGRA194_RESET_TSECB
 
- TEGRA194_RESET_UARTA
 
- TEGRA194_RESET_UARTB
 
- TEGRA194_RESET_UARTC
 
- TEGRA194_RESET_UARTD
 
- TEGRA194_RESET_UARTE
 
- TEGRA194_RESET_UARTF
 
- TEGRA194_RESET_UARTG
 
- TEGRA194_RESET_UARTH
 
- TEGRA194_RESET_UFSHC
 
- TEGRA194_RESET_UFSHC_AXI_M
 
- TEGRA194_RESET_UFSHC_LP_SEQ
 
- TEGRA194_RESET_VI
 
- TEGRA194_RESET_VIC
 
- TEGRA194_RESET_XUSB_PADCTL
 
- TEGRA20
 
- TEGRA20_AC97_CMD
 
- TEGRA20_AC97_CMD_BUSY
 
- TEGRA20_AC97_CMD_CMD_ADDR_MASK
 
- TEGRA20_AC97_CMD_CMD_ADDR_SHIFT
 
- TEGRA20_AC97_CMD_CMD_DATA_MASK
 
- TEGRA20_AC97_CMD_CMD_DATA_SHIFT
 
- TEGRA20_AC97_CMD_CMD_ID_MASK
 
- TEGRA20_AC97_CMD_CMD_ID_SHIFT
 
- TEGRA20_AC97_CTRL
 
- TEGRA20_AC97_CTRL_COLD_RESET
 
- TEGRA20_AC97_CTRL_DOUBLE_SAMPLING_EN
 
- TEGRA20_AC97_CTRL_HSET_DAC_EN
 
- TEGRA20_AC97_CTRL_IO_CNTRL_EN
 
- TEGRA20_AC97_CTRL_LINE1_DAC_EN
 
- TEGRA20_AC97_CTRL_LINE2_DAC_EN
 
- TEGRA20_AC97_CTRL_PCM_CEN_DAC_EN
 
- TEGRA20_AC97_CTRL_PCM_DAC_EN
 
- TEGRA20_AC97_CTRL_PCM_LFE_EN
 
- TEGRA20_AC97_CTRL_PCM_SUR_EN
 
- TEGRA20_AC97_CTRL_STM2_EN
 
- TEGRA20_AC97_CTRL_STM_EN
 
- TEGRA20_AC97_CTRL_WARM_RESET
 
- TEGRA20_AC97_FIFO1_SCR
 
- TEGRA20_AC97_FIFO_RX1
 
- TEGRA20_AC97_FIFO_SCR_PB_3QRT_MT_EN
 
- TEGRA20_AC97_FIFO_SCR_PB_EMPTY_MT_EN
 
- TEGRA20_AC97_FIFO_SCR_PB_FORCE_MT
 
- TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_MASK
 
- TEGRA20_AC97_FIFO_SCR_PB_MT_CNT_SHIFT
 
- TEGRA20_AC97_FIFO_SCR_PB_NOT_FULL_EN
 
- TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN
 
- TEGRA20_AC97_FIFO_SCR_PB_UNDERRUN_INT_STA
 
- TEGRA20_AC97_FIFO_SCR_REC_3QRT_FULL_EN
 
- TEGRA20_AC97_FIFO_SCR_REC_EMPTY_EN
 
- TEGRA20_AC97_FIFO_SCR_REC_FORCE_MT
 
- TEGRA20_AC97_FIFO_SCR_REC_FULL_EN
 
- TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_MASK
 
- TEGRA20_AC97_FIFO_SCR_REC_MT_CNT_SHIFT
 
- TEGRA20_AC97_FIFO_SCR_REC_OVERRUN_INT_STA
 
- TEGRA20_AC97_FIFO_SCR_REC_QRT_FULL_EN
 
- TEGRA20_AC97_FIFO_TX1
 
- TEGRA20_AC97_STATUS1
 
- TEGRA20_AC97_STATUS1_CODEC1_RDY
 
- TEGRA20_AC97_STATUS1_STANDBY1
 
- TEGRA20_AC97_STATUS1_STA_ADDR1_MASK
 
- TEGRA20_AC97_STATUS1_STA_ADDR1_SHIFT
 
- TEGRA20_AC97_STATUS1_STA_DATA1_MASK
 
- TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT
 
- TEGRA20_AC97_STATUS1_STA_VALID1
 
- TEGRA20_CLK_AC97
 
- TEGRA20_CLK_AFI
 
- TEGRA20_CLK_AHBDMA
 
- TEGRA20_CLK_APBDMA
 
- TEGRA20_CLK_AUDIO
 
- TEGRA20_CLK_AUDIO_2X
 
- TEGRA20_CLK_AVPUCQ
 
- TEGRA20_CLK_BLINK
 
- TEGRA20_CLK_BSEA
 
- TEGRA20_CLK_BSEV
 
- TEGRA20_CLK_CACHE2
 
- TEGRA20_CLK_CCLK
 
- TEGRA20_CLK_CDEV1
 
- TEGRA20_CLK_CDEV2
 
- TEGRA20_CLK_CLK_32K
 
- TEGRA20_CLK_CLK_D
 
- TEGRA20_CLK_CLK_M
 
- TEGRA20_CLK_CLK_MAX
 
- TEGRA20_CLK_COP
 
- TEGRA20_CLK_CPU
 
- TEGRA20_CLK_CRAM2
 
- TEGRA20_CLK_CSI
 
- TEGRA20_CLK_CSITE
 
- TEGRA20_CLK_CSUS
 
- TEGRA20_CLK_CVE
 
- TEGRA20_CLK_DISP1
 
- TEGRA20_CLK_DISP2
 
- TEGRA20_CLK_DSI
 
- TEGRA20_CLK_DVC
 
- TEGRA20_CLK_EMC
 
- TEGRA20_CLK_EPP
 
- TEGRA20_CLK_FUSE
 
- TEGRA20_CLK_GPIO
 
- TEGRA20_CLK_GR2D
 
- TEGRA20_CLK_GR3D
 
- TEGRA20_CLK_HCLK
 
- TEGRA20_CLK_HDMI
 
- TEGRA20_CLK_HOST1X
 
- TEGRA20_CLK_I2C1
 
- TEGRA20_CLK_I2C2
 
- TEGRA20_CLK_I2C3
 
- TEGRA20_CLK_I2S1
 
- TEGRA20_CLK_I2S2
 
- TEGRA20_CLK_IDE
 
- TEGRA20_CLK_IRAMA
 
- TEGRA20_CLK_IRAMB
 
- TEGRA20_CLK_IRAMC
 
- TEGRA20_CLK_IRAMD
 
- TEGRA20_CLK_ISP
 
- TEGRA20_CLK_KBC
 
- TEGRA20_CLK_KFUSE
 
- TEGRA20_CLK_LA
 
- TEGRA20_CLK_MC
 
- TEGRA20_CLK_MIPI
 
- TEGRA20_CLK_MPE
 
- TEGRA20_CLK_NDFLASH
 
- TEGRA20_CLK_NOR
 
- TEGRA20_CLK_OSC
 
- TEGRA20_CLK_OWR
 
- TEGRA20_CLK_PCLK
 
- TEGRA20_CLK_PERIPH_BANKS
 
- TEGRA20_CLK_PEX
 
- TEGRA20_CLK_PLL_A
 
- TEGRA20_CLK_PLL_A_OUT0
 
- TEGRA20_CLK_PLL_C
 
- TEGRA20_CLK_PLL_C_OUT1
 
- TEGRA20_CLK_PLL_D
 
- TEGRA20_CLK_PLL_D_OUT0
 
- TEGRA20_CLK_PLL_E
 
- TEGRA20_CLK_PLL_M
 
- TEGRA20_CLK_PLL_M_OUT1
 
- TEGRA20_CLK_PLL_P
 
- TEGRA20_CLK_PLL_P_OUT1
 
- TEGRA20_CLK_PLL_P_OUT2
 
- TEGRA20_CLK_PLL_P_OUT3
 
- TEGRA20_CLK_PLL_P_OUT4
 
- TEGRA20_CLK_PLL_REF
 
- TEGRA20_CLK_PLL_S
 
- TEGRA20_CLK_PLL_U
 
- TEGRA20_CLK_PLL_X
 
- TEGRA20_CLK_PMC
 
- TEGRA20_CLK_PWM
 
- TEGRA20_CLK_RTC
 
- TEGRA20_CLK_SBC1
 
- TEGRA20_CLK_SBC2
 
- TEGRA20_CLK_SBC3
 
- TEGRA20_CLK_SBC4
 
- TEGRA20_CLK_SCLK
 
- TEGRA20_CLK_SDMMC1
 
- TEGRA20_CLK_SDMMC2
 
- TEGRA20_CLK_SDMMC3
 
- TEGRA20_CLK_SDMMC4
 
- TEGRA20_CLK_SPDIF_IN
 
- TEGRA20_CLK_SPDIF_OUT
 
- TEGRA20_CLK_SPEEDO
 
- TEGRA20_CLK_SPI
 
- TEGRA20_CLK_STAT_MON
 
- TEGRA20_CLK_TIMER
 
- TEGRA20_CLK_TVDAC
 
- TEGRA20_CLK_TVO
 
- TEGRA20_CLK_TWC
 
- TEGRA20_CLK_TWD
 
- TEGRA20_CLK_UARTA
 
- TEGRA20_CLK_UARTB
 
- TEGRA20_CLK_UARTC
 
- TEGRA20_CLK_UARTD
 
- TEGRA20_CLK_UARTE
 
- TEGRA20_CLK_USB2
 
- TEGRA20_CLK_USB3
 
- TEGRA20_CLK_USBD
 
- TEGRA20_CLK_VCP
 
- TEGRA20_CLK_VDE
 
- TEGRA20_CLK_VFIR
 
- TEGRA20_CLK_VI
 
- TEGRA20_CLK_VI_SENSOR
 
- TEGRA20_CLK_XIO
 
- TEGRA20_DAS_DAC_ID_1
 
- TEGRA20_DAS_DAC_ID_2
 
- TEGRA20_DAS_DAC_ID_3
 
- TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL
 
- TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_COUNT
 
- TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P
 
- TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_S
 
- TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P
 
- TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_S
 
- TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P
 
- TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_S
 
- TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE
 
- TEGRA20_DAS_DAC_SEL_DAP1
 
- TEGRA20_DAS_DAC_SEL_DAP2
 
- TEGRA20_DAS_DAC_SEL_DAP3
 
- TEGRA20_DAS_DAC_SEL_DAP4
 
- TEGRA20_DAS_DAC_SEL_DAP5
 
- TEGRA20_DAS_DAP_CTRL_SEL
 
- TEGRA20_DAS_DAP_CTRL_SEL_COUNT
 
- TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P
 
- TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_S
 
- TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P
 
- TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_S
 
- TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P
 
- TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_S
 
- TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P
 
- TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_S
 
- TEGRA20_DAS_DAP_CTRL_SEL_STRIDE
 
- TEGRA20_DAS_DAP_ID_1
 
- TEGRA20_DAS_DAP_ID_2
 
- TEGRA20_DAS_DAP_ID_3
 
- TEGRA20_DAS_DAP_ID_4
 
- TEGRA20_DAS_DAP_ID_5
 
- TEGRA20_DAS_DAP_SEL_DAC1
 
- TEGRA20_DAS_DAP_SEL_DAC2
 
- TEGRA20_DAS_DAP_SEL_DAC3
 
- TEGRA20_DAS_DAP_SEL_DAP1
 
- TEGRA20_DAS_DAP_SEL_DAP2
 
- TEGRA20_DAS_DAP_SEL_DAP3
 
- TEGRA20_DAS_DAP_SEL_DAP4
 
- TEGRA20_DAS_DAP_SEL_DAP5
 
- TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP
 
- TEGRA20_FLOW_CTRL_CSR_WFE_CPU0
 
- TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP
 
- TEGRA20_I2S_BIT_FORMAT_DSP
 
- TEGRA20_I2S_BIT_FORMAT_I2S
 
- TEGRA20_I2S_BIT_FORMAT_LJM
 
- TEGRA20_I2S_BIT_FORMAT_RJM
 
- TEGRA20_I2S_BIT_SIZE_16
 
- TEGRA20_I2S_BIT_SIZE_20
 
- TEGRA20_I2S_BIT_SIZE_24
 
- TEGRA20_I2S_BIT_SIZE_32
 
- TEGRA20_I2S_CTRL
 
- TEGRA20_I2S_CTRL_BIT_FORMAT_DSP
 
- TEGRA20_I2S_CTRL_BIT_FORMAT_I2S
 
- TEGRA20_I2S_CTRL_BIT_FORMAT_LJM
 
- TEGRA20_I2S_CTRL_BIT_FORMAT_MASK
 
- TEGRA20_I2S_CTRL_BIT_FORMAT_RJM
 
- TEGRA20_I2S_CTRL_BIT_FORMAT_SHIFT
 
- TEGRA20_I2S_CTRL_BIT_SIZE_16
 
- TEGRA20_I2S_CTRL_BIT_SIZE_20
 
- TEGRA20_I2S_CTRL_BIT_SIZE_24
 
- TEGRA20_I2S_CTRL_BIT_SIZE_32
 
- TEGRA20_I2S_CTRL_BIT_SIZE_MASK
 
- TEGRA20_I2S_CTRL_BIT_SIZE_SHIFT
 
- TEGRA20_I2S_CTRL_FIFO1_ENABLE
 
- TEGRA20_I2S_CTRL_FIFO1_RX_ENABLE
 
- TEGRA20_I2S_CTRL_FIFO2_ENABLE
 
- TEGRA20_I2S_CTRL_FIFO2_TX_ENABLE
 
- TEGRA20_I2S_CTRL_FIFO_FORMAT_16_LSB
 
- TEGRA20_I2S_CTRL_FIFO_FORMAT_20_LSB
 
- TEGRA20_I2S_CTRL_FIFO_FORMAT_24_LSB
 
- TEGRA20_I2S_CTRL_FIFO_FORMAT_32
 
- TEGRA20_I2S_CTRL_FIFO_FORMAT_MASK
 
- TEGRA20_I2S_CTRL_FIFO_FORMAT_PACKED
 
- TEGRA20_I2S_CTRL_FIFO_FORMAT_SHIFT
 
- TEGRA20_I2S_CTRL_FIFO_LPBK_ENABLE
 
- TEGRA20_I2S_CTRL_IE_FIFO1_ERR
 
- TEGRA20_I2S_CTRL_IE_FIFO2_ERR
 
- TEGRA20_I2S_CTRL_LRCK_L_LOW
 
- TEGRA20_I2S_CTRL_LRCK_MASK
 
- TEGRA20_I2S_CTRL_LRCK_R_LOW
 
- TEGRA20_I2S_CTRL_LRCK_SHIFT
 
- TEGRA20_I2S_CTRL_MASTER_ENABLE
 
- TEGRA20_I2S_CTRL_QE_FIFO1
 
- TEGRA20_I2S_CTRL_QE_FIFO2
 
- TEGRA20_I2S_FIFO1
 
- TEGRA20_I2S_FIFO2
 
- TEGRA20_I2S_FIFO_16_LSB
 
- TEGRA20_I2S_FIFO_20_LSB
 
- TEGRA20_I2S_FIFO_24_LSB
 
- TEGRA20_I2S_FIFO_32
 
- TEGRA20_I2S_FIFO_ATN_LVL_EIGHT_SLOTS
 
- TEGRA20_I2S_FIFO_ATN_LVL_FOUR_SLOTS
 
- TEGRA20_I2S_FIFO_ATN_LVL_ONE_SLOT
 
- TEGRA20_I2S_FIFO_ATN_LVL_TWELVE_SLOTS
 
- TEGRA20_I2S_FIFO_PACKED
 
- TEGRA20_I2S_FIFO_SCR
 
- TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_EIGHT_SLOTS
 
- TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS
 
- TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_MASK
 
- TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_ONE_SLOT
 
- TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_SHIFT
 
- TEGRA20_I2S_FIFO_SCR_FIFO1_ATN_LVL_TWELVE_SLOTS
 
- TEGRA20_I2S_FIFO_SCR_FIFO1_CLR
 
- TEGRA20_I2S_FIFO_SCR_FIFO1_FULL_EMPTY_COUNT_SHIFT
 
- TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_EIGHT_SLOTS
 
- TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS
 
- TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_MASK
 
- TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_ONE_SLOT
 
- TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_SHIFT
 
- TEGRA20_I2S_FIFO_SCR_FIFO2_ATN_LVL_TWELVE_SLOTS
 
- TEGRA20_I2S_FIFO_SCR_FIFO2_CLR
 
- TEGRA20_I2S_FIFO_SCR_FIFO2_FULL_EMPTY_COUNT_SHIFT
 
- TEGRA20_I2S_FIFO_SCR_FIFO_FULL_EMPTY_COUNT_MASK
 
- TEGRA20_I2S_LRCK_LEFT_LOW
 
- TEGRA20_I2S_LRCK_RIGHT_LOW
 
- TEGRA20_I2S_NW_CTRL
 
- TEGRA20_I2S_PCM_CTRL
 
- TEGRA20_I2S_STATUS
 
- TEGRA20_I2S_STATUS_FIFO1_BSY
 
- TEGRA20_I2S_STATUS_FIFO1_ERR
 
- TEGRA20_I2S_STATUS_FIFO1_RDY
 
- TEGRA20_I2S_STATUS_FIFO2_BSY
 
- TEGRA20_I2S_STATUS_FIFO2_ERR
 
- TEGRA20_I2S_STATUS_FIFO2_RDY
 
- TEGRA20_I2S_STATUS_QS_FIFO1
 
- TEGRA20_I2S_STATUS_QS_FIFO2
 
- TEGRA20_I2S_TDM_CTRL
 
- TEGRA20_I2S_TDM_TX_RX_CTRL
 
- TEGRA20_I2S_TIMING
 
- TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK
 
- TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US
 
- TEGRA20_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT
 
- TEGRA20_I2S_TIMING_NON_SYM_ENABLE
 
- TEGRA20_MAX_STATES
 
- TEGRA20_MC_RESET
 
- TEGRA20_MC_RESET_2D
 
- TEGRA20_MC_RESET_3D
 
- TEGRA20_MC_RESET_AVPC
 
- TEGRA20_MC_RESET_DC
 
- TEGRA20_MC_RESET_DCB
 
- TEGRA20_MC_RESET_EPP
 
- TEGRA20_MC_RESET_HC
 
- TEGRA20_MC_RESET_ISP
 
- TEGRA20_MC_RESET_MPCORE
 
- TEGRA20_MC_RESET_MPEA
 
- TEGRA20_MC_RESET_MPEB
 
- TEGRA20_MC_RESET_MPEC
 
- TEGRA20_MC_RESET_PPCS
 
- TEGRA20_MC_RESET_VDE
 
- TEGRA20_MC_RESET_VI
 
- TEGRA20_SPDIF_BIT_MODE_16BIT
 
- TEGRA20_SPDIF_BIT_MODE_20BIT
 
- TEGRA20_SPDIF_BIT_MODE_24BIT
 
- TEGRA20_SPDIF_BIT_MODE_RAW
 
- TEGRA20_SPDIF_CH_STA_RX_A
 
- TEGRA20_SPDIF_CH_STA_RX_B
 
- TEGRA20_SPDIF_CH_STA_RX_C
 
- TEGRA20_SPDIF_CH_STA_RX_D
 
- TEGRA20_SPDIF_CH_STA_RX_E
 
- TEGRA20_SPDIF_CH_STA_RX_F
 
- TEGRA20_SPDIF_CH_STA_TX_A
 
- TEGRA20_SPDIF_CH_STA_TX_B
 
- TEGRA20_SPDIF_CH_STA_TX_C
 
- TEGRA20_SPDIF_CH_STA_TX_D
 
- TEGRA20_SPDIF_CH_STA_TX_E
 
- TEGRA20_SPDIF_CH_STA_TX_F
 
- TEGRA20_SPDIF_CTRL
 
- TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT
 
- TEGRA20_SPDIF_CTRL_BIT_MODE_20BIT
 
- TEGRA20_SPDIF_CTRL_BIT_MODE_24BIT
 
- TEGRA20_SPDIF_CTRL_BIT_MODE_MASK
 
- TEGRA20_SPDIF_CTRL_BIT_MODE_RAW
 
- TEGRA20_SPDIF_CTRL_BIT_MODE_SHIFT
 
- TEGRA20_SPDIF_CTRL_CAP_LC
 
- TEGRA20_SPDIF_CTRL_IE_B
 
- TEGRA20_SPDIF_CTRL_IE_C
 
- TEGRA20_SPDIF_CTRL_IE_P
 
- TEGRA20_SPDIF_CTRL_IE_RXE
 
- TEGRA20_SPDIF_CTRL_IE_TXE
 
- TEGRA20_SPDIF_CTRL_IE_U
 
- TEGRA20_SPDIF_CTRL_LBK_EN
 
- TEGRA20_SPDIF_CTRL_PACK
 
- TEGRA20_SPDIF_CTRL_QE_RU
 
- TEGRA20_SPDIF_CTRL_QE_RX
 
- TEGRA20_SPDIF_CTRL_QE_TU
 
- TEGRA20_SPDIF_CTRL_QE_TX
 
- TEGRA20_SPDIF_CTRL_RX_EN
 
- TEGRA20_SPDIF_CTRL_TC_EN
 
- TEGRA20_SPDIF_CTRL_TU_EN
 
- TEGRA20_SPDIF_CTRL_TX_EN
 
- TEGRA20_SPDIF_DATA_FIFO_CSR
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_MASK
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU1_WORD_FULL
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU2_WORD_FULL
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU3_WORD_FULL
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU4_WORD_FULL
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_RU_CLR
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_MASK
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_SHIFT
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_MASK
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU12_WORD_FULL
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU1_WORD_FULL
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU4_WORD_FULL
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU8_WORD_FULL
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_RX_CLR
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_MASK
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_SHIFT
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_MASK
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU1_WORD_FULL
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU2_WORD_FULL
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU3_WORD_FULL
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU4_WORD_FULL
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_TU_CLR
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_MASK
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_SHIFT
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_MASK
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU12_WORD_FULL
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU1_WORD_FULL
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU4_WORD_FULL
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU8_WORD_FULL
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_TX_CLR
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_MASK
 
- TEGRA20_SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_SHIFT
 
- TEGRA20_SPDIF_DATA_IN
 
- TEGRA20_SPDIF_DATA_IN_DATA_16_MASK
 
- TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_MASK
 
- TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_SHIFT
 
- TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_MASK
 
- TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_SHIFT
 
- TEGRA20_SPDIF_DATA_IN_DATA_16_SHIFT
 
- TEGRA20_SPDIF_DATA_IN_DATA_20_MASK
 
- TEGRA20_SPDIF_DATA_IN_DATA_20_SHIFT
 
- TEGRA20_SPDIF_DATA_IN_DATA_24_MASK
 
- TEGRA20_SPDIF_DATA_IN_DATA_24_SHIFT
 
- TEGRA20_SPDIF_DATA_IN_DATA_C
 
- TEGRA20_SPDIF_DATA_IN_DATA_P
 
- TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_MASK
 
- TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_SHIFT
 
- TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_MASK
 
- TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_SHIFT
 
- TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_MASK
 
- TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_SHIFT
 
- TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_MASK
 
- TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_SHIFT
 
- TEGRA20_SPDIF_DATA_IN_DATA_U
 
- TEGRA20_SPDIF_DATA_IN_DATA_V
 
- TEGRA20_SPDIF_DATA_OUT
 
- TEGRA20_SPDIF_DATA_OUT_DATA_16_MASK
 
- TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_MASK
 
- TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_SHIFT
 
- TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_MASK
 
- TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_SHIFT
 
- TEGRA20_SPDIF_DATA_OUT_DATA_16_SHIFT
 
- TEGRA20_SPDIF_DATA_OUT_DATA_20_MASK
 
- TEGRA20_SPDIF_DATA_OUT_DATA_20_SHIFT
 
- TEGRA20_SPDIF_DATA_OUT_DATA_24_MASK
 
- TEGRA20_SPDIF_DATA_OUT_DATA_24_SHIFT
 
- TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_MASK
 
- TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_SHIFT
 
- TEGRA20_SPDIF_DATA_OUT_DATA_RAW_C
 
- TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_MASK
 
- TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_SHIFT
 
- TEGRA20_SPDIF_DATA_OUT_DATA_RAW_P
 
- TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_MASK
 
- TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_SHIFT
 
- TEGRA20_SPDIF_DATA_OUT_DATA_RAW_U
 
- TEGRA20_SPDIF_DATA_OUT_DATA_RAW_V
 
- TEGRA20_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS
 
- TEGRA20_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS
 
- TEGRA20_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT
 
- TEGRA20_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS
 
- TEGRA20_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS
 
- TEGRA20_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT
 
- TEGRA20_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS
 
- TEGRA20_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS
 
- TEGRA20_SPDIF_STATUS
 
- TEGRA20_SPDIF_STATUS_IS_B
 
- TEGRA20_SPDIF_STATUS_IS_C
 
- TEGRA20_SPDIF_STATUS_IS_P
 
- TEGRA20_SPDIF_STATUS_IS_U
 
- TEGRA20_SPDIF_STATUS_QS_RU
 
- TEGRA20_SPDIF_STATUS_QS_RX
 
- TEGRA20_SPDIF_STATUS_QS_TU
 
- TEGRA20_SPDIF_STATUS_QS_TX
 
- TEGRA20_SPDIF_STATUS_RX_BSY
 
- TEGRA20_SPDIF_STATUS_RX_ERR
 
- TEGRA20_SPDIF_STATUS_TC_BSY
 
- TEGRA20_SPDIF_STATUS_TU_BSY
 
- TEGRA20_SPDIF_STATUS_TX_BSY
 
- TEGRA20_SPDIF_STATUS_TX_ERR
 
- TEGRA20_SPDIF_STROBE_CTRL
 
- TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_MASK
 
- TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT
 
- TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_MASK
 
- TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT
 
- TEGRA20_SPDIF_STROBE_CTRL_PERIOD_MASK
 
- TEGRA20_SPDIF_STROBE_CTRL_PERIOD_SHIFT
 
- TEGRA20_SPDIF_STROBE_CTRL_STROBE
 
- TEGRA20_SPDIF_USR_DAT_TX_A
 
- TEGRA20_SPDIF_USR_STA_RX_A
 
- TEGRA210
 
- TEGRA210_ADMA_CH_FIFO_CTRL_RXSIZE
 
- TEGRA210_ADMA_CH_FIFO_CTRL_TXSIZE
 
- TEGRA210_AHUB_BASE
 
- TEGRA210_BPTT
 
- TEGRA210_CAR_BANK_COUNT
 
- TEGRA210_CLK_ACLK
 
- TEGRA210_CLK_ACTMON
 
- TEGRA210_CLK_ADSP
 
- TEGRA210_CLK_ADSP_NEON
 
- TEGRA210_CLK_AFI
 
- TEGRA210_CLK_AHBDMA
 
- TEGRA210_CLK_APB2APE
 
- TEGRA210_CLK_APBDMA
 
- TEGRA210_CLK_APE
 
- TEGRA210_CLK_AUDIO0
 
- TEGRA210_CLK_AUDIO0_MUX
 
- TEGRA210_CLK_AUDIO1
 
- TEGRA210_CLK_AUDIO1_MUX
 
- TEGRA210_CLK_AUDIO2
 
- TEGRA210_CLK_AUDIO2_MUX
 
- TEGRA210_CLK_AUDIO3
 
- TEGRA210_CLK_AUDIO3_MUX
 
- TEGRA210_CLK_AUDIO4
 
- TEGRA210_CLK_AUDIO4_MUX
 
- TEGRA210_CLK_BLINK
 
- TEGRA210_CLK_BSEV
 
- TEGRA210_CLK_CCLK_G
 
- TEGRA210_CLK_CCLK_LP
 
- TEGRA210_CLK_CEC
 
- TEGRA210_CLK_CILAB
 
- TEGRA210_CLK_CILCD
 
- TEGRA210_CLK_CILE
 
- TEGRA210_CLK_CLK72MHZ
 
- TEGRA210_CLK_CLK_32K
 
- TEGRA210_CLK_CLK_M
 
- TEGRA210_CLK_CLK_MAX
 
- TEGRA210_CLK_CLK_M_DIV2
 
- TEGRA210_CLK_CLK_M_DIV4
 
- TEGRA210_CLK_CLK_OUT_1
 
- TEGRA210_CLK_CLK_OUT_1_MUX
 
- TEGRA210_CLK_CLK_OUT_2
 
- TEGRA210_CLK_CLK_OUT_2_MUX
 
- TEGRA210_CLK_CLK_OUT_3
 
- TEGRA210_CLK_CLK_OUT_3_MUX
 
- TEGRA210_CLK_CML0
 
- TEGRA210_CLK_CML1
 
- TEGRA210_CLK_CSI
 
- TEGRA210_CLK_CSITE
 
- TEGRA210_CLK_CSUS
 
- TEGRA210_CLK_DBGAPB
 
- TEGRA210_CLK_DFLL_REF
 
- TEGRA210_CLK_DFLL_SOC
 
- TEGRA210_CLK_DISP1
 
- TEGRA210_CLK_DISP2
 
- TEGRA210_CLK_DMIC1
 
- TEGRA210_CLK_DMIC1_SYNC_CLK
 
- TEGRA210_CLK_DMIC1_SYNC_CLK_MUX
 
- TEGRA210_CLK_DMIC2
 
- TEGRA210_CLK_DMIC2_SYNC_CLK
 
- TEGRA210_CLK_DMIC2_SYNC_CLK_MUX
 
- TEGRA210_CLK_DMIC3
 
- TEGRA210_CLK_DMIC3_SYNC_CLK
 
- TEGRA210_CLK_DMIC3_SYNC_CLK_MUX
 
- TEGRA210_CLK_DP2
 
- TEGRA210_CLK_DPAUX
 
- TEGRA210_CLK_DPAUX1
 
- TEGRA210_CLK_DSIA
 
- TEGRA210_CLK_DSIALP
 
- TEGRA210_CLK_DSIA_MUX
 
- TEGRA210_CLK_DSIB
 
- TEGRA210_CLK_DSIBLP
 
- TEGRA210_CLK_DSIB_MUX
 
- TEGRA210_CLK_DTV
 
- TEGRA210_CLK_D_AUDIO
 
- TEGRA210_CLK_EMC
 
- TEGRA210_CLK_ENTROPY
 
- TEGRA210_CLK_EXTERN1
 
- TEGRA210_CLK_EXTERN2
 
- TEGRA210_CLK_EXTERN3
 
- TEGRA210_CLK_FUSE
 
- TEGRA210_CLK_FUSE_BURN
 
- TEGRA210_CLK_GPIO
 
- TEGRA210_CLK_GPU
 
- TEGRA210_CLK_HCLK
 
- TEGRA210_CLK_HDA
 
- TEGRA210_CLK_HDA2CODEC_2X
 
- TEGRA210_CLK_HDA2HDMI
 
- TEGRA210_CLK_HOST1X
 
- TEGRA210_CLK_HSIC_TRK
 
- TEGRA210_CLK_I2C1
 
- TEGRA210_CLK_I2C2
 
- TEGRA210_CLK_I2C3
 
- TEGRA210_CLK_I2C4
 
- TEGRA210_CLK_I2C5
 
- TEGRA210_CLK_I2C6
 
- TEGRA210_CLK_I2CSLOW
 
- TEGRA210_CLK_I2S0
 
- TEGRA210_CLK_I2S0_SYNC
 
- TEGRA210_CLK_I2S1
 
- TEGRA210_CLK_I2S1_SYNC
 
- TEGRA210_CLK_I2S2
 
- TEGRA210_CLK_I2S2_SYNC
 
- TEGRA210_CLK_I2S3
 
- TEGRA210_CLK_I2S3_SYNC
 
- TEGRA210_CLK_I2S4
 
- TEGRA210_CLK_I2S4_SYNC
 
- TEGRA210_CLK_IQC1
 
- TEGRA210_CLK_IQC2
 
- TEGRA210_CLK_ISP
 
- TEGRA210_CLK_ISPA
 
- TEGRA210_CLK_ISPB
 
- TEGRA210_CLK_KFUSE
 
- TEGRA210_CLK_LA
 
- TEGRA210_CLK_MAUD
 
- TEGRA210_CLK_MC
 
- TEGRA210_CLK_MIPIBIF
 
- TEGRA210_CLK_MIPI_CAL
 
- TEGRA210_CLK_MSELECT
 
- TEGRA210_CLK_NVDEC
 
- TEGRA210_CLK_NVENC
 
- TEGRA210_CLK_NVJPG
 
- TEGRA210_CLK_OWR
 
- TEGRA210_CLK_PCIE
 
- TEGRA210_CLK_PCLK
 
- TEGRA210_CLK_PLL_A
 
- TEGRA210_CLK_PLL_A1
 
- TEGRA210_CLK_PLL_A_OUT0
 
- TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP
 
- TEGRA210_CLK_PLL_A_OUT_ADSP
 
- TEGRA210_CLK_PLL_C
 
- TEGRA210_CLK_PLL_C2
 
- TEGRA210_CLK_PLL_C3
 
- TEGRA210_CLK_PLL_C4
 
- TEGRA210_CLK_PLL_C4_OUT0
 
- TEGRA210_CLK_PLL_C4_OUT1
 
- TEGRA210_CLK_PLL_C4_OUT2
 
- TEGRA210_CLK_PLL_C4_OUT3
 
- TEGRA210_CLK_PLL_C_OUT1
 
- TEGRA210_CLK_PLL_C_UD
 
- TEGRA210_CLK_PLL_D
 
- TEGRA210_CLK_PLL_D2
 
- TEGRA210_CLK_PLL_D2_OUT0
 
- TEGRA210_CLK_PLL_DP
 
- TEGRA210_CLK_PLL_D_DSI_OUT
 
- TEGRA210_CLK_PLL_D_OUT0
 
- TEGRA210_CLK_PLL_E
 
- TEGRA210_CLK_PLL_E_MUX
 
- TEGRA210_CLK_PLL_G_REF
 
- TEGRA210_CLK_PLL_M
 
- TEGRA210_CLK_PLL_MB
 
- TEGRA210_CLK_PLL_M_OUT1
 
- TEGRA210_CLK_PLL_M_UD
 
- TEGRA210_CLK_PLL_P
 
- TEGRA210_CLK_PLL_P_OUT1
 
- TEGRA210_CLK_PLL_P_OUT2
 
- TEGRA210_CLK_PLL_P_OUT3
 
- TEGRA210_CLK_PLL_P_OUT4
 
- TEGRA210_CLK_PLL_P_OUT5
 
- TEGRA210_CLK_PLL_P_OUT_ADSP
 
- TEGRA210_CLK_PLL_P_OUT_CPU
 
- TEGRA210_CLK_PLL_P_OUT_HSIO
 
- TEGRA210_CLK_PLL_P_OUT_XUSB
 
- TEGRA210_CLK_PLL_REF
 
- TEGRA210_CLK_PLL_RE_OUT
 
- TEGRA210_CLK_PLL_RE_OUT1
 
- TEGRA210_CLK_PLL_RE_VCO
 
- TEGRA210_CLK_PLL_U
 
- TEGRA210_CLK_PLL_U_480M
 
- TEGRA210_CLK_PLL_U_48M
 
- TEGRA210_CLK_PLL_U_60M
 
- TEGRA210_CLK_PLL_U_OUT
 
- TEGRA210_CLK_PLL_U_OUT1
 
- TEGRA210_CLK_PLL_U_OUT2
 
- TEGRA210_CLK_PLL_X
 
- TEGRA210_CLK_PLL_X_OUT0
 
- TEGRA210_CLK_PMC
 
- TEGRA210_CLK_PWM
 
- TEGRA210_CLK_QSPI
 
- TEGRA210_CLK_RTC
 
- TEGRA210_CLK_SATA
 
- TEGRA210_CLK_SATA_OOB
 
- TEGRA210_CLK_SBC1
 
- TEGRA210_CLK_SBC2
 
- TEGRA210_CLK_SBC3
 
- TEGRA210_CLK_SBC4
 
- TEGRA210_CLK_SCLK
 
- TEGRA210_CLK_SCLK_MUX
 
- TEGRA210_CLK_SDMMC1
 
- TEGRA210_CLK_SDMMC2
 
- TEGRA210_CLK_SDMMC3
 
- TEGRA210_CLK_SDMMC4
 
- TEGRA210_CLK_SDMMC_LEGACY
 
- TEGRA210_CLK_SOC_THERM
 
- TEGRA210_CLK_SOR0
 
- TEGRA210_CLK_SOR0_LVDS
 
- TEGRA210_CLK_SOR1
 
- TEGRA210_CLK_SOR1_OUT
 
- TEGRA210_CLK_SOR1_SRC
 
- TEGRA210_CLK_SOR_SAFE
 
- TEGRA210_CLK_SPDIF
 
- TEGRA210_CLK_SPDIF_2X
 
- TEGRA210_CLK_SPDIF_IN
 
- TEGRA210_CLK_SPDIF_IN_SYNC
 
- TEGRA210_CLK_SPDIF_MUX
 
- TEGRA210_CLK_SPDIF_OUT
 
- TEGRA210_CLK_TIMER
 
- TEGRA210_CLK_TSEC
 
- TEGRA210_CLK_TSECB
 
- TEGRA210_CLK_TSENSOR
 
- TEGRA210_CLK_UARTA
 
- TEGRA210_CLK_UARTAPE
 
- TEGRA210_CLK_UARTB
 
- TEGRA210_CLK_UARTC
 
- TEGRA210_CLK_UARTD
 
- TEGRA210_CLK_USB2
 
- TEGRA210_CLK_USB2_HSIC_TRK
 
- TEGRA210_CLK_USB2_TRK
 
- TEGRA210_CLK_USBD
 
- TEGRA210_CLK_VFIR
 
- TEGRA210_CLK_VI
 
- TEGRA210_CLK_VIC03
 
- TEGRA210_CLK_VIM2_CLK
 
- TEGRA210_CLK_VIMCLK_SYNC
 
- TEGRA210_CLK_VI_I2C
 
- TEGRA210_CLK_VI_SENSOR
 
- TEGRA210_CLK_VI_SENSOR2
 
- TEGRA210_CLK_XUSB_DEV
 
- TEGRA210_CLK_XUSB_DEV_SRC
 
- TEGRA210_CLK_XUSB_FALCON_SRC
 
- TEGRA210_CLK_XUSB_FS_SRC
 
- TEGRA210_CLK_XUSB_GATE
 
- TEGRA210_CLK_XUSB_HOST
 
- TEGRA210_CLK_XUSB_HOST_SRC
 
- TEGRA210_CLK_XUSB_HS_SRC
 
- TEGRA210_CLK_XUSB_SS
 
- TEGRA210_CLK_XUSB_SSP_SRC
 
- TEGRA210_CLK_XUSB_SS_DIV2
 
- TEGRA210_CLK_XUSB_SS_SRC
 
- TEGRA210_DISPA_BASE
 
- TEGRA210_FIFO_CTRL_DEFAULT
 
- TEGRA210_I2S_BASE
 
- TEGRA210_I2S_CG
 
- TEGRA210_I2S_CTRL
 
- TEGRA210_I2S_CTRLS
 
- TEGRA210_I2S_SIZE
 
- TEGRA210_IO_PAD_TABLE
 
- TEGRA210_LANE
 
- TEGRA210_MC_BASE
 
- TEGRA210_MC_RESET
 
- TEGRA210_MC_RESET_A9AVP
 
- TEGRA210_MC_RESET_AFI
 
- TEGRA210_MC_RESET_APE
 
- TEGRA210_MC_RESET_AVPC
 
- TEGRA210_MC_RESET_AXIAP
 
- TEGRA210_MC_RESET_DC
 
- TEGRA210_MC_RESET_DCB
 
- TEGRA210_MC_RESET_ETR
 
- TEGRA210_MC_RESET_GPU
 
- TEGRA210_MC_RESET_HC
 
- TEGRA210_MC_RESET_HDA
 
- TEGRA210_MC_RESET_ISP2
 
- TEGRA210_MC_RESET_ISP2B
 
- TEGRA210_MC_RESET_MPCORE
 
- TEGRA210_MC_RESET_NVDEC
 
- TEGRA210_MC_RESET_NVENC
 
- TEGRA210_MC_RESET_NVJPG
 
- TEGRA210_MC_RESET_PPCS
 
- TEGRA210_MC_RESET_SATA
 
- TEGRA210_MC_RESET_SDMMC1
 
- TEGRA210_MC_RESET_SDMMC2
 
- TEGRA210_MC_RESET_SDMMC3
 
- TEGRA210_MC_RESET_SDMMC4
 
- TEGRA210_MC_RESET_SE
 
- TEGRA210_MC_RESET_TSEC
 
- TEGRA210_MC_RESET_TSECB
 
- TEGRA210_MC_RESET_VI
 
- TEGRA210_MC_RESET_VIC
 
- TEGRA210_MC_RESET_XUSB_DEV
 
- TEGRA210_MC_RESET_XUSB_HOST
 
- TEGRA210_RESET
 
- TEGRA210_RST_ADSP
 
- TEGRA210_RST_DFLL_DVCO
 
- TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK
 
- TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK
 
- TEGRA210_THERMTRIP_ANY_EN_MASK
 
- TEGRA210_THERMTRIP_CPU_EN_MASK
 
- TEGRA210_THERMTRIP_CPU_THRESH_MASK
 
- TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK
 
- TEGRA210_THERMTRIP_GPU_EN_MASK
 
- TEGRA210_THERMTRIP_MEM_EN_MASK
 
- TEGRA210_THERMTRIP_TSENSE_EN_MASK
 
- TEGRA210_THERMTRIP_TSENSE_THRESH_MASK
 
- TEGRA210_THRESH_GRAIN
 
- TEGRA210_VIC_BASE
 
- TEGRA30
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_EMPTY
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_CIF_FIFO_FULL
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_EMPTY
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_RX_DMA_FIFO_FULL
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_EMPTY
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_CIF_FIFO_FULL
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_EMPTY
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH0_TX_DMA_FIFO_FULL
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_EMPTY
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_CIF_FIFO_FULL
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_EMPTY
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_RX_DMA_FIFO_FULL
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_EMPTY
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_CIF_FIFO_FULL
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_EMPTY
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH1_TX_DMA_FIFO_FULL
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_EMPTY
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_CIF_FIFO_FULL
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_EMPTY
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_RX_DMA_FIFO_FULL
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_EMPTY
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_CIF_FIFO_FULL
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_EMPTY
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH2_TX_DMA_FIFO_FULL
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_EMPTY
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_CIF_FIFO_FULL
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_EMPTY
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_RX_DMA_FIFO_FULL
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_EMPTY
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_CIF_FIFO_FULL
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_EMPTY
 
- TEGRA30_AHUB_APBDMA_LIVE_STATUS_CH3_TX_DMA_FIFO_FULL
 
- TEGRA30_AHUB_APBIF_INT_MASK
 
- TEGRA30_AHUB_APBIF_INT_SET
 
- TEGRA30_AHUB_APBIF_INT_SOURCE
 
- TEGRA30_AHUB_APBIF_INT_STATUS
 
- TEGRA30_AHUB_AUDIO_RX
 
- TEGRA30_AHUB_AUDIO_RX_COUNT
 
- TEGRA30_AHUB_AUDIO_RX_STRIDE
 
- TEGRA30_AHUB_CHANNEL_CLEAR
 
- TEGRA30_AHUB_CHANNEL_CLEAR_COUNT
 
- TEGRA30_AHUB_CHANNEL_CLEAR_RX_SOFT_RESET
 
- TEGRA30_AHUB_CHANNEL_CLEAR_STRIDE
 
- TEGRA30_AHUB_CHANNEL_CLEAR_TX_SOFT_RESET
 
- TEGRA30_AHUB_CHANNEL_CTRL
 
- TEGRA30_AHUB_CHANNEL_CTRL_COUNT
 
- TEGRA30_AHUB_CHANNEL_CTRL_LOOPBACK
 
- TEGRA30_AHUB_CHANNEL_CTRL_RX_EN
 
- TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_16
 
- TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_8_4
 
- TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_EN
 
- TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK
 
- TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_MASK_US
 
- TEGRA30_AHUB_CHANNEL_CTRL_RX_PACK_SHIFT
 
- TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK
 
- TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_MASK_US
 
- TEGRA30_AHUB_CHANNEL_CTRL_RX_THRESHOLD_SHIFT
 
- TEGRA30_AHUB_CHANNEL_CTRL_STRIDE
 
- TEGRA30_AHUB_CHANNEL_CTRL_TX_EN
 
- TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_16
 
- TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_8_4
 
- TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_EN
 
- TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK
 
- TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_MASK_US
 
- TEGRA30_AHUB_CHANNEL_CTRL_TX_PACK_SHIFT
 
- TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK
 
- TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_MASK_US
 
- TEGRA30_AHUB_CHANNEL_CTRL_TX_THRESHOLD_SHIFT
 
- TEGRA30_AHUB_CHANNEL_RXFIFO
 
- TEGRA30_AHUB_CHANNEL_RXFIFO_COUNT
 
- TEGRA30_AHUB_CHANNEL_RXFIFO_STRIDE
 
- TEGRA30_AHUB_CHANNEL_STATUS
 
- TEGRA30_AHUB_CHANNEL_STATUS_COUNT
 
- TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK
 
- TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_MASK_US
 
- TEGRA30_AHUB_CHANNEL_STATUS_RX_FREE_SHIFT
 
- TEGRA30_AHUB_CHANNEL_STATUS_RX_TRIG
 
- TEGRA30_AHUB_CHANNEL_STATUS_STRIDE
 
- TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK
 
- TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_MASK_US
 
- TEGRA30_AHUB_CHANNEL_STATUS_TX_FREE_SHIFT
 
- TEGRA30_AHUB_CHANNEL_STATUS_TX_TRIG
 
- TEGRA30_AHUB_CHANNEL_TXFIFO
 
- TEGRA30_AHUB_CHANNEL_TXFIFO_COUNT
 
- TEGRA30_AHUB_CHANNEL_TXFIFO_STRIDE
 
- TEGRA30_AHUB_CIF_RX_CTRL
 
- TEGRA30_AHUB_CIF_RX_CTRL_COUNT
 
- TEGRA30_AHUB_CIF_RX_CTRL_STRIDE
 
- TEGRA30_AHUB_CIF_TX_CTRL
 
- TEGRA30_AHUB_CIF_TX_CTRL_COUNT
 
- TEGRA30_AHUB_CIF_TX_CTRL_STRIDE
 
- TEGRA30_AHUB_CONFIG_LINK_CTRL
 
- TEGRA30_AHUB_CONFIG_LINK_CTRL_CG_EN
 
- TEGRA30_AHUB_CONFIG_LINK_CTRL_CLEAR_TIMEOUT_CNTR
 
- TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK
 
- TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_MASK_US
 
- TEGRA30_AHUB_CONFIG_LINK_CTRL_IDLE_CNT_SHIFT
 
- TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK
 
- TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_MASK_US
 
- TEGRA30_AHUB_CONFIG_LINK_CTRL_MASTER_FIFO_FULL_CNT_SHIFT
 
- TEGRA30_AHUB_CONFIG_LINK_CTRL_SOFT_RESET
 
- TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK
 
- TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_MASK_US
 
- TEGRA30_AHUB_CONFIG_LINK_CTRL_TIMEOUT_CNT_SHIFT
 
- TEGRA30_AHUB_DAM_INT_MASK
 
- TEGRA30_AHUB_DAM_INT_SET
 
- TEGRA30_AHUB_DAM_INT_SOURCE
 
- TEGRA30_AHUB_DAM_INT_STATUS
 
- TEGRA30_AHUB_DAM_LIVE_STATUS
 
- TEGRA30_AHUB_DAM_LIVE_STATUS_COUNT
 
- TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_EMPTY
 
- TEGRA30_AHUB_DAM_LIVE_STATUS_RX0FIFO_FULL
 
- TEGRA30_AHUB_DAM_LIVE_STATUS_RX0_ENABLED
 
- TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_EMPTY
 
- TEGRA30_AHUB_DAM_LIVE_STATUS_RX1FIFO_FULL
 
- TEGRA30_AHUB_DAM_LIVE_STATUS_RX1_ENABLED
 
- TEGRA30_AHUB_DAM_LIVE_STATUS_STRIDE
 
- TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_EMPTY
 
- TEGRA30_AHUB_DAM_LIVE_STATUS_TXFIFO_FULL
 
- TEGRA30_AHUB_DAM_LIVE_STATUS_TX_ENABLED
 
- TEGRA30_AHUB_I2S_INT_MASK
 
- TEGRA30_AHUB_I2S_INT_SET
 
- TEGRA30_AHUB_I2S_INT_SOURCE
 
- TEGRA30_AHUB_I2S_INT_STATUS
 
- TEGRA30_AHUB_I2S_LIVE_STATUS
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_EMPTY
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_ENABLED
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_RX_FIFO_FULL
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_EMPTY
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_ENABLED
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S0_TX_FIFO_FULL
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_EMPTY
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_ENABLED
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_RX_FIFO_FULL
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_EMPTY
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_ENABLED
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S1_TX_FIFO_FULL
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_EMPTY
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_ENABLED
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_RX_FIFO_FULL
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_EMPTY
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_ENABLED
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S2_TX_FIFO_FULL
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_EMPTY
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_ENABLED
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_RX_FIFO_FULL
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_EMPTY
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_ENABLED
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S3_TX_FIFO_FULL
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_EMPTY
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_ENABLED
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_RX_FIFO_FULL
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_EMPTY
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_ENABLED
 
- TEGRA30_AHUB_I2S_LIVE_STATUS_I2S4_TX_FIFO_FULL
 
- TEGRA30_AHUB_MISC_CTRL
 
- TEGRA30_AHUB_MISC_CTRL_AUDIO_ACTIVE
 
- TEGRA30_AHUB_MISC_CTRL_AUDIO_CG_EN
 
- TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_MASK
 
- TEGRA30_AHUB_MISC_CTRL_AUDIO_OBS_SEL_SHIFT
 
- TEGRA30_AHUB_RXCIF_APBIF_RX0
 
- TEGRA30_AHUB_RXCIF_APBIF_RX1
 
- TEGRA30_AHUB_RXCIF_APBIF_RX3
 
- TEGRA30_AHUB_RXCIF_DAM0_RX0
 
- TEGRA30_AHUB_RXCIF_DAM0_RX1
 
- TEGRA30_AHUB_RXCIF_DAM1_RX0
 
- TEGRA30_AHUB_RXCIF_DAM2_RX1
 
- TEGRA30_AHUB_RXCIF_DAM3_RX0
 
- TEGRA30_AHUB_RXCIF_DAM3_RX1
 
- TEGRA30_AHUB_RXCIF_I2S0_RX0
 
- TEGRA30_AHUB_RXCIF_I2S1_RX0
 
- TEGRA30_AHUB_RXCIF_I2S2_RX0
 
- TEGRA30_AHUB_RXCIF_I2S3_RX0
 
- TEGRA30_AHUB_RXCIF_I2S4_RX0
 
- TEGRA30_AHUB_RXCIF_SPDIF_RX0
 
- TEGRA30_AHUB_RXCIF_SPDIF_RX1
 
- TEGRA30_AHUB_RXcIF_APBIF_RX2
 
- TEGRA30_AHUB_SPDIF_INT_MASK
 
- TEGRA30_AHUB_SPDIF_INT_SET
 
- TEGRA30_AHUB_SPDIF_INT_SOURCE
 
- TEGRA30_AHUB_SPDIF_INT_STATUS
 
- TEGRA30_AHUB_SPDIF_LIVE_STATUS
 
- TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_EMPTY
 
- TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RXFIFO_FULL
 
- TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_RX_ENABLED
 
- TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_EMPTY
 
- TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TXFIFO_FULL
 
- TEGRA30_AHUB_SPDIF_LIVE_STATUS_DATA_TX_ENABLED
 
- TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_EMPTY
 
- TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RXFIFO_FULL
 
- TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_RX_ENABLED
 
- TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_EMPTY
 
- TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TXFIFO_FULL
 
- TEGRA30_AHUB_SPDIF_LIVE_STATUS_USER_TX_ENABLED
 
- TEGRA30_AHUB_TXCIF_APBIF_TX0
 
- TEGRA30_AHUB_TXCIF_APBIF_TX1
 
- TEGRA30_AHUB_TXCIF_APBIF_TX2
 
- TEGRA30_AHUB_TXCIF_APBIF_TX3
 
- TEGRA30_AHUB_TXCIF_DAM0_TX0
 
- TEGRA30_AHUB_TXCIF_DAM1_TX0
 
- TEGRA30_AHUB_TXCIF_DAM2_TX0
 
- TEGRA30_AHUB_TXCIF_I2S0_TX0
 
- TEGRA30_AHUB_TXCIF_I2S1_TX0
 
- TEGRA30_AHUB_TXCIF_I2S2_TX0
 
- TEGRA30_AHUB_TXCIF_I2S3_TX0
 
- TEGRA30_AHUB_TXCIF_I2S4_TX0
 
- TEGRA30_AHUB_TXCIF_SPDIF_TX0
 
- TEGRA30_AHUB_TXCIF_SPDIF_TX1
 
- TEGRA30_AUDIOCIF_BITS_12
 
- TEGRA30_AUDIOCIF_BITS_16
 
- TEGRA30_AUDIOCIF_BITS_20
 
- TEGRA30_AUDIOCIF_BITS_24
 
- TEGRA30_AUDIOCIF_BITS_28
 
- TEGRA30_AUDIOCIF_BITS_32
 
- TEGRA30_AUDIOCIF_BITS_4
 
- TEGRA30_AUDIOCIF_BITS_8
 
- TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_12
 
- TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16
 
- TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_20
 
- TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_24
 
- TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_28
 
- TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_32
 
- TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_4
 
- TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_8
 
- TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_MASK
 
- TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_SHIFT
 
- TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK
 
- TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_MASK_US
 
- TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT
 
- TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_12
 
- TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16
 
- TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_20
 
- TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_24
 
- TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_28
 
- TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_32
 
- TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_4
 
- TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_8
 
- TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_MASK
 
- TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_SHIFT
 
- TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK
 
- TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_MASK_US
 
- TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT
 
- TEGRA30_AUDIOCIF_CTRL_DIRECTION_MASK
 
- TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX
 
- TEGRA30_AUDIOCIF_CTRL_DIRECTION_SHIFT
 
- TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX
 
- TEGRA30_AUDIOCIF_CTRL_EXPAND_LFSR
 
- TEGRA30_AUDIOCIF_CTRL_EXPAND_MASK
 
- TEGRA30_AUDIOCIF_CTRL_EXPAND_ONE
 
- TEGRA30_AUDIOCIF_CTRL_EXPAND_SHIFT
 
- TEGRA30_AUDIOCIF_CTRL_EXPAND_ZERO
 
- TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK
 
- TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_MASK_US
 
- TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT
 
- TEGRA30_AUDIOCIF_CTRL_MONO_CONV_COPY
 
- TEGRA30_AUDIOCIF_CTRL_MONO_CONV_MASK
 
- TEGRA30_AUDIOCIF_CTRL_MONO_CONV_SHIFT
 
- TEGRA30_AUDIOCIF_CTRL_MONO_CONV_ZERO
 
- TEGRA30_AUDIOCIF_CTRL_REPLICATE_SHIFT
 
- TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_AVG
 
- TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH0
 
- TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_CH1
 
- TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_MASK
 
- TEGRA30_AUDIOCIF_CTRL_STEREO_CONV_SHIFT
 
- TEGRA30_AUDIOCIF_CTRL_TRUNCATE_CHOP
 
- TEGRA30_AUDIOCIF_CTRL_TRUNCATE_MASK
 
- TEGRA30_AUDIOCIF_CTRL_TRUNCATE_ROUND
 
- TEGRA30_AUDIOCIF_CTRL_TRUNCATE_SHIFT
 
- TEGRA30_AUDIOCIF_DIRECTION_RX
 
- TEGRA30_AUDIOCIF_DIRECTION_TX
 
- TEGRA30_AUDIOCIF_EXPAND_LFSR
 
- TEGRA30_AUDIOCIF_EXPAND_ONE
 
- TEGRA30_AUDIOCIF_EXPAND_ZERO
 
- TEGRA30_AUDIOCIF_MONO_CONV_COPY
 
- TEGRA30_AUDIOCIF_MONO_CONV_ZERO
 
- TEGRA30_AUDIOCIF_STEREO_CONV_AVG
 
- TEGRA30_AUDIOCIF_STEREO_CONV_CH0
 
- TEGRA30_AUDIOCIF_STEREO_CONV_CH1
 
- TEGRA30_AUDIOCIF_TRUNCATE_CHOP
 
- TEGRA30_AUDIOCIF_TRUNCATE_ROUND
 
- TEGRA30_CLK_ACTMON
 
- TEGRA30_CLK_AFI
 
- TEGRA30_CLK_AHBDMA
 
- TEGRA30_CLK_APBDMA
 
- TEGRA30_CLK_APBIF
 
- TEGRA30_CLK_ATOMICS
 
- TEGRA30_CLK_AUDIO0
 
- TEGRA30_CLK_AUDIO0_2X
 
- TEGRA30_CLK_AUDIO0_MUX
 
- TEGRA30_CLK_AUDIO1
 
- TEGRA30_CLK_AUDIO1_2X
 
- TEGRA30_CLK_AUDIO1_MUX
 
- TEGRA30_CLK_AUDIO2
 
- TEGRA30_CLK_AUDIO2_2X
 
- TEGRA30_CLK_AUDIO2_MUX
 
- TEGRA30_CLK_AUDIO3
 
- TEGRA30_CLK_AUDIO3_2X
 
- TEGRA30_CLK_AUDIO3_MUX
 
- TEGRA30_CLK_AUDIO4
 
- TEGRA30_CLK_AUDIO4_2X
 
- TEGRA30_CLK_AUDIO4_MUX
 
- TEGRA30_CLK_AUDIO_2X
 
- TEGRA30_CLK_AVPUCQ
 
- TEGRA30_CLK_BLINK
 
- TEGRA30_CLK_BSEA
 
- TEGRA30_CLK_BSEV
 
- TEGRA30_CLK_CCLK_G
 
- TEGRA30_CLK_CCLK_LP
 
- TEGRA30_CLK_CDEV1
 
- TEGRA30_CLK_CDEV2
 
- TEGRA30_CLK_CEC
 
- TEGRA30_CLK_CLK_32K
 
- TEGRA30_CLK_CLK_M
 
- TEGRA30_CLK_CLK_MAX
 
- TEGRA30_CLK_CLK_M_DIV2
 
- TEGRA30_CLK_CLK_M_DIV4
 
- TEGRA30_CLK_CLK_OUT_1
 
- TEGRA30_CLK_CLK_OUT_1_MUX
 
- TEGRA30_CLK_CLK_OUT_2
 
- TEGRA30_CLK_CLK_OUT_2_MUX
 
- TEGRA30_CLK_CLK_OUT_3
 
- TEGRA30_CLK_CLK_OUT_3_MUX
 
- TEGRA30_CLK_CML0
 
- TEGRA30_CLK_CML1
 
- TEGRA30_CLK_COP_CACHE
 
- TEGRA30_CLK_CPU
 
- TEGRA30_CLK_CPU_G
 
- TEGRA30_CLK_CPU_LP
 
- TEGRA30_CLK_CRAM2
 
- TEGRA30_CLK_CSI
 
- TEGRA30_CLK_CSITE
 
- TEGRA30_CLK_CSUS
 
- TEGRA30_CLK_CVE
 
- TEGRA30_CLK_DAM0
 
- TEGRA30_CLK_DAM1
 
- TEGRA30_CLK_DAM2
 
- TEGRA30_CLK_DISP1
 
- TEGRA30_CLK_DISP2
 
- TEGRA30_CLK_DSIA
 
- TEGRA30_CLK_DSIB
 
- TEGRA30_CLK_DTV
 
- TEGRA30_CLK_D_AUDIO
 
- TEGRA30_CLK_EMC
 
- TEGRA30_CLK_EPP
 
- TEGRA30_CLK_EXTERN1
 
- TEGRA30_CLK_EXTERN2
 
- TEGRA30_CLK_EXTERN3
 
- TEGRA30_CLK_FUSE
 
- TEGRA30_CLK_FUSE_BURN
 
- TEGRA30_CLK_GPIO
 
- TEGRA30_CLK_GR2D
 
- TEGRA30_CLK_GR3D
 
- TEGRA30_CLK_GR3D2
 
- TEGRA30_CLK_HCLK
 
- TEGRA30_CLK_HDA
 
- TEGRA30_CLK_HDA2CODEC_2X
 
- TEGRA30_CLK_HDA2HDMI
 
- TEGRA30_CLK_HDMI
 
- TEGRA30_CLK_HOST1X
 
- TEGRA30_CLK_I2C1
 
- TEGRA30_CLK_I2C2
 
- TEGRA30_CLK_I2C3
 
- TEGRA30_CLK_I2C4
 
- TEGRA30_CLK_I2C5
 
- TEGRA30_CLK_I2CSLOW
 
- TEGRA30_CLK_I2S0
 
- TEGRA30_CLK_I2S0_SYNC
 
- TEGRA30_CLK_I2S1
 
- TEGRA30_CLK_I2S1_SYNC
 
- TEGRA30_CLK_I2S2
 
- TEGRA30_CLK_I2S2_SYNC
 
- TEGRA30_CLK_I2S3
 
- TEGRA30_CLK_I2S3_SYNC
 
- TEGRA30_CLK_I2S4
 
- TEGRA30_CLK_I2S4_SYNC
 
- TEGRA30_CLK_IRAMA
 
- TEGRA30_CLK_IRAMB
 
- TEGRA30_CLK_IRAMC
 
- TEGRA30_CLK_IRAMD
 
- TEGRA30_CLK_ISP
 
- TEGRA30_CLK_KBC
 
- TEGRA30_CLK_KFUSE
 
- TEGRA30_CLK_LA
 
- TEGRA30_CLK_MC
 
- TEGRA30_CLK_MIPI
 
- TEGRA30_CLK_MPE
 
- TEGRA30_CLK_MSELECT
 
- TEGRA30_CLK_NDFLASH
 
- TEGRA30_CLK_NDSPEED
 
- TEGRA30_CLK_NOR
 
- TEGRA30_CLK_OWR
 
- TEGRA30_CLK_PCIE
 
- TEGRA30_CLK_PCLK
 
- TEGRA30_CLK_PERIPH_BANKS
 
- TEGRA30_CLK_PLL_A
 
- TEGRA30_CLK_PLL_A_OUT0
 
- TEGRA30_CLK_PLL_C
 
- TEGRA30_CLK_PLL_C_OUT1
 
- TEGRA30_CLK_PLL_D
 
- TEGRA30_CLK_PLL_D2
 
- TEGRA30_CLK_PLL_D2_OUT0
 
- TEGRA30_CLK_PLL_D_OUT0
 
- TEGRA30_CLK_PLL_E
 
- TEGRA30_CLK_PLL_M
 
- TEGRA30_CLK_PLL_M_OUT1
 
- TEGRA30_CLK_PLL_P
 
- TEGRA30_CLK_PLL_P_OUT1
 
- TEGRA30_CLK_PLL_P_OUT2
 
- TEGRA30_CLK_PLL_P_OUT3
 
- TEGRA30_CLK_PLL_P_OUT4
 
- TEGRA30_CLK_PLL_REF
 
- TEGRA30_CLK_PLL_U
 
- TEGRA30_CLK_PLL_X
 
- TEGRA30_CLK_PLL_X_OUT0
 
- TEGRA30_CLK_PMC
 
- TEGRA30_CLK_PWM
 
- TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR
 
- TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS
 
- TEGRA30_CLK_RTC
 
- TEGRA30_CLK_SATA
 
- TEGRA30_CLK_SATA_COLD
 
- TEGRA30_CLK_SATA_OOB
 
- TEGRA30_CLK_SBC1
 
- TEGRA30_CLK_SBC2
 
- TEGRA30_CLK_SBC3
 
- TEGRA30_CLK_SBC4
 
- TEGRA30_CLK_SBC5
 
- TEGRA30_CLK_SBC6
 
- TEGRA30_CLK_SCLK
 
- TEGRA30_CLK_SDMMC1
 
- TEGRA30_CLK_SDMMC2
 
- TEGRA30_CLK_SDMMC3
 
- TEGRA30_CLK_SDMMC4
 
- TEGRA30_CLK_SE
 
- TEGRA30_CLK_SPDIF
 
- TEGRA30_CLK_SPDIF_2X
 
- TEGRA30_CLK_SPDIF_IN
 
- TEGRA30_CLK_SPDIF_IN_SYNC
 
- TEGRA30_CLK_SPDIF_MUX
 
- TEGRA30_CLK_SPDIF_OUT
 
- TEGRA30_CLK_SPEEDO
 
- TEGRA30_CLK_STATMON
 
- TEGRA30_CLK_TIMER
 
- TEGRA30_CLK_TSENSOR
 
- TEGRA30_CLK_TVDAC
 
- TEGRA30_CLK_TVO
 
- TEGRA30_CLK_TWD
 
- TEGRA30_CLK_UARTA
 
- TEGRA30_CLK_UARTB
 
- TEGRA30_CLK_UARTC
 
- TEGRA30_CLK_UARTD
 
- TEGRA30_CLK_UARTE
 
- TEGRA30_CLK_USB2
 
- TEGRA30_CLK_USB3
 
- TEGRA30_CLK_USBD
 
- TEGRA30_CLK_VCP
 
- TEGRA30_CLK_VDE
 
- TEGRA30_CLK_VFIR
 
- TEGRA30_CLK_VI
 
- TEGRA30_CLK_VIMCLK_SYNC
 
- TEGRA30_CLK_VI_SENSOR
 
- TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP
 
- TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP
 
- TEGRA30_FLOW_CTRL_CSR_WFI_CPU0
 
- TEGRA30_FUSE_SATA_CALIB
 
- TEGRA30_I2S_BITS_12
 
- TEGRA30_I2S_BITS_16
 
- TEGRA30_I2S_BITS_20
 
- TEGRA30_I2S_BITS_24
 
- TEGRA30_I2S_BITS_28
 
- TEGRA30_I2S_BITS_32
 
- TEGRA30_I2S_BITS_8
 
- TEGRA30_I2S_BIT_CODE_ALAW
 
- TEGRA30_I2S_BIT_CODE_LINEAR
 
- TEGRA30_I2S_BIT_CODE_ULAW
 
- TEGRA30_I2S_CH_CTRL
 
- TEGRA30_I2S_CH_CTRL_EGDE_CTRL_MASK
 
- TEGRA30_I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE
 
- TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE
 
- TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT
 
- TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK
 
- TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK_US
 
- TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_SHIFT
 
- TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_MASK
 
- TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_NO
 
- TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_ON_HALF_BIT_CLK
 
- TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT
 
- TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_YES
 
- TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_LSB_FIRST
 
- TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_MASK
 
- TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_MSB_FIRST
 
- TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT
 
- TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_MASK
 
- TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_MASK_US
 
- TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_SHIFT
 
- TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_LSB_FIRST
 
- TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_MASK
 
- TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_MSB_FIRST
 
- TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT
 
- TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_MASK
 
- TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_MASK_US
 
- TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_SHIFT
 
- TEGRA30_I2S_CIF_RX_CTRL
 
- TEGRA30_I2S_CIF_TX_CTRL
 
- TEGRA30_I2S_CTRL
 
- TEGRA30_I2S_CTRL_BIT_CODE_ALAW
 
- TEGRA30_I2S_CTRL_BIT_CODE_LINEAR
 
- TEGRA30_I2S_CTRL_BIT_CODE_MASK
 
- TEGRA30_I2S_CTRL_BIT_CODE_SHIFT
 
- TEGRA30_I2S_CTRL_BIT_CODE_ULAW
 
- TEGRA30_I2S_CTRL_BIT_SIZE_12
 
- TEGRA30_I2S_CTRL_BIT_SIZE_16
 
- TEGRA30_I2S_CTRL_BIT_SIZE_20
 
- TEGRA30_I2S_CTRL_BIT_SIZE_24
 
- TEGRA30_I2S_CTRL_BIT_SIZE_28
 
- TEGRA30_I2S_CTRL_BIT_SIZE_32
 
- TEGRA30_I2S_CTRL_BIT_SIZE_8
 
- TEGRA30_I2S_CTRL_BIT_SIZE_MASK
 
- TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT
 
- TEGRA30_I2S_CTRL_CG_EN
 
- TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC
 
- TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK
 
- TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK
 
- TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT
 
- TEGRA30_I2S_CTRL_LPBK_ENABLE
 
- TEGRA30_I2S_CTRL_LRCK_L_LOW
 
- TEGRA30_I2S_CTRL_LRCK_MASK
 
- TEGRA30_I2S_CTRL_LRCK_R_LOW
 
- TEGRA30_I2S_CTRL_LRCK_SHIFT
 
- TEGRA30_I2S_CTRL_MASTER_ENABLE
 
- TEGRA30_I2S_CTRL_OBS_SEL_MASK
 
- TEGRA30_I2S_CTRL_OBS_SEL_SHIFT
 
- TEGRA30_I2S_CTRL_SOFT_RESET
 
- TEGRA30_I2S_CTRL_TX_FLOWCTL_EN
 
- TEGRA30_I2S_CTRL_XFER_EN_RX
 
- TEGRA30_I2S_CTRL_XFER_EN_TX
 
- TEGRA30_I2S_FILTER_LINEAR
 
- TEGRA30_I2S_FILTER_QUAD
 
- TEGRA30_I2S_FLOWCTL
 
- TEGRA30_I2S_FLOWCTL_FILTER_LINEAR
 
- TEGRA30_I2S_FLOWCTL_FILTER_MASK
 
- TEGRA30_I2S_FLOWCTL_FILTER_QUAD
 
- TEGRA30_I2S_FLOWCTL_FILTER_SHIFT
 
- TEGRA30_I2S_FLOW_OVER
 
- TEGRA30_I2S_FLOW_STATUS
 
- TEGRA30_I2S_FLOW_STATUS_COUNTER_CLR
 
- TEGRA30_I2S_FLOW_STATUS_COUNTER_EN
 
- TEGRA30_I2S_FLOW_STATUS_MONITOR_CLR
 
- TEGRA30_I2S_FLOW_STATUS_MONITOR_EN
 
- TEGRA30_I2S_FLOW_STATUS_MONITOR_INT_EN
 
- TEGRA30_I2S_FLOW_STATUS_OVERFLOW
 
- TEGRA30_I2S_FLOW_STATUS_UNDERFLOW
 
- TEGRA30_I2S_FLOW_TOTAL
 
- TEGRA30_I2S_FLOW_UNDER
 
- TEGRA30_I2S_FRAME_FORMAT_FSYNC
 
- TEGRA30_I2S_FRAME_FORMAT_LRCK
 
- TEGRA30_I2S_HIGHZ_NO
 
- TEGRA30_I2S_HIGHZ_ON_HALF_BIT_CLK
 
- TEGRA30_I2S_HIGHZ_YES
 
- TEGRA30_I2S_LCOEF_1_4_0
 
- TEGRA30_I2S_LCOEF_1_4_1
 
- TEGRA30_I2S_LCOEF_1_4_2
 
- TEGRA30_I2S_LCOEF_1_4_3
 
- TEGRA30_I2S_LCOEF_1_4_4
 
- TEGRA30_I2S_LCOEF_1_4_5
 
- TEGRA30_I2S_LCOEF_2_4_0
 
- TEGRA30_I2S_LCOEF_2_4_1
 
- TEGRA30_I2S_LCOEF_2_4_2
 
- TEGRA30_I2S_LCOEF_COEF_MASK
 
- TEGRA30_I2S_LCOEF_COEF_MASK_US
 
- TEGRA30_I2S_LCOEF_COEF_SHIFT
 
- TEGRA30_I2S_LRCK_LEFT_LOW
 
- TEGRA30_I2S_LRCK_RIGHT_LOW
 
- TEGRA30_I2S_LSB_FIRST
 
- TEGRA30_I2S_MSB_FIRST
 
- TEGRA30_I2S_NEG_EDGE
 
- TEGRA30_I2S_OFFSET
 
- TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_MASK
 
- TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_MASK_US
 
- TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT
 
- TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_MASK
 
- TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_MASK_US
 
- TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT
 
- TEGRA30_I2S_POS_EDGE
 
- TEGRA30_I2S_SLOT_CTRL
 
- TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK
 
- TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT
 
- TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK
 
- TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US
 
- TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT
 
- TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK
 
- TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT
 
- TEGRA30_I2S_TIMING
 
- TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK
 
- TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US
 
- TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT
 
- TEGRA30_I2S_TIMING_NON_SYM_ENABLE
 
- TEGRA30_I2S_TX_STEP
 
- TEGRA30_I2S_TX_STEP_MASK
 
- TEGRA30_I2S_TX_STEP_MASK_US
 
- TEGRA30_I2S_TX_STEP_SHIFT
 
- TEGRA30_MC_RESET
 
- TEGRA30_MC_RESET_2D
 
- TEGRA30_MC_RESET_3D
 
- TEGRA30_MC_RESET_3D2
 
- TEGRA30_MC_RESET_AFI
 
- TEGRA30_MC_RESET_AVPC
 
- TEGRA30_MC_RESET_DC
 
- TEGRA30_MC_RESET_DCB
 
- TEGRA30_MC_RESET_EPP
 
- TEGRA30_MC_RESET_HC
 
- TEGRA30_MC_RESET_HDA
 
- TEGRA30_MC_RESET_ISP
 
- TEGRA30_MC_RESET_MPCORE
 
- TEGRA30_MC_RESET_MPCORELP
 
- TEGRA30_MC_RESET_MPE
 
- TEGRA30_MC_RESET_PPCS
 
- TEGRA30_MC_RESET_SATA
 
- TEGRA30_MC_RESET_VDE
 
- TEGRA30_MC_RESET_VI
 
- TEGRA30_PACK_16
 
- TEGRA30_PACK_8_4
 
- TEGRA30_POWER_HOTPLUG_SHUTDOWN
 
- TEGRA_ADMA_BURST_COMPLETE_TIME
 
- TEGRA_APBDMA_AHBSEQ_BURST_1
 
- TEGRA_APBDMA_AHBSEQ_BURST_4
 
- TEGRA_APBDMA_AHBSEQ_BURST_8
 
- TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_128
 
- TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_16
 
- TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32
 
- TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_64
 
- TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_8
 
- TEGRA_APBDMA_AHBSEQ_DATA_SWAP
 
- TEGRA_APBDMA_AHBSEQ_DBL_BUF
 
- TEGRA_APBDMA_AHBSEQ_INTR_ENB
 
- TEGRA_APBDMA_AHBSEQ_WRAP_NONE
 
- TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT
 
- TEGRA_APBDMA_APBSEQ_BUS_WIDTH_128
 
- TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16
 
- TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32
 
- TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64
 
- TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8
 
- TEGRA_APBDMA_APBSEQ_DATA_SWAP
 
- TEGRA_APBDMA_APBSEQ_WRAP_WORD_1
 
- TEGRA_APBDMA_BURST_COMPLETE_TIME
 
- TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET
 
- TEGRA_APBDMA_CHAN_AHBPTR
 
- TEGRA_APBDMA_CHAN_AHBSEQ
 
- TEGRA_APBDMA_CHAN_APBPTR
 
- TEGRA_APBDMA_CHAN_APBSEQ
 
- TEGRA_APBDMA_CHAN_CSR
 
- TEGRA_APBDMA_CHAN_CSRE
 
- TEGRA_APBDMA_CHAN_CSRE_PAUSE
 
- TEGRA_APBDMA_CHAN_STATUS
 
- TEGRA_APBDMA_CHAN_WCOUNT
 
- TEGRA_APBDMA_CHAN_WORD_TRANSFER
 
- TEGRA_APBDMA_CONTROL
 
- TEGRA_APBDMA_CSR_DIR
 
- TEGRA_APBDMA_CSR_ENB
 
- TEGRA_APBDMA_CSR_FLOW
 
- TEGRA_APBDMA_CSR_HOLD
 
- TEGRA_APBDMA_CSR_IE_EOC
 
- TEGRA_APBDMA_CSR_ONCE
 
- TEGRA_APBDMA_CSR_REQ_SEL_MASK
 
- TEGRA_APBDMA_CSR_REQ_SEL_SHIFT
 
- TEGRA_APBDMA_CSR_WCOUNT_MASK
 
- TEGRA_APBDMA_GENERAL
 
- TEGRA_APBDMA_GENERAL_ENABLE
 
- TEGRA_APBDMA_IRQ_MASK
 
- TEGRA_APBDMA_IRQ_MASK_SET
 
- TEGRA_APBDMA_SLAVE_ID_INVALID
 
- TEGRA_APBDMA_STATUS_BUSY
 
- TEGRA_APBDMA_STATUS_COUNT_MASK
 
- TEGRA_APBDMA_STATUS_COUNT_SHIFT
 
- TEGRA_APBDMA_STATUS_HALT
 
- TEGRA_APBDMA_STATUS_ISE_EOC
 
- TEGRA_APBDMA_STATUS_PING_PONG
 
- TEGRA_APB_MISC_BASE
 
- TEGRA_APB_MISC_GP_HIDREV
 
- TEGRA_APB_MISC_SIZE
 
- TEGRA_APB_MISC_VIRT
 
- TEGRA_ARM_INT_DIST_BASE
 
- TEGRA_ARM_INT_DIST_SIZE
 
- TEGRA_ARM_PERIF_BASE
 
- TEGRA_ARM_PERIF_SIZE
 
- TEGRA_ARM_PERIF_VIRT
 
- TEGRA_ASOC_UTILS_SOC_TEGRA114
 
- TEGRA_ASOC_UTILS_SOC_TEGRA124
 
- TEGRA_ASOC_UTILS_SOC_TEGRA20
 
- TEGRA_ASOC_UTILS_SOC_TEGRA30
 
- TEGRA_BO_BOTTOM_UP
 
- TEGRA_BO_TILING_MODE_BLOCK
 
- TEGRA_BO_TILING_MODE_PITCH
 
- TEGRA_BO_TILING_MODE_TILED
 
- TEGRA_BPMP_CLK_HAS_MUX
 
- TEGRA_BPMP_CLK_HAS_SET_RATE
 
- TEGRA_BPMP_CLK_IS_ROOT
 
- TEGRA_BPMP_DUMP_CLOCK_INFO
 
- TEGRA_CEC_H
 
- TEGRA_CEC_HWCTRL_FAST_SIM_MODE
 
- TEGRA_CEC_HWCTRL_RX_LADDR
 
- TEGRA_CEC_HWCTRL_RX_LADDR_MASK
 
- TEGRA_CEC_HWCTRL_RX_NAK_MODE
 
- TEGRA_CEC_HWCTRL_RX_SNOOP
 
- TEGRA_CEC_HWCTRL_TX_NAK_MODE
 
- TEGRA_CEC_HWCTRL_TX_RX_MODE
 
- TEGRA_CEC_HW_CONTROL
 
- TEGRA_CEC_HW_DEBUG_RX
 
- TEGRA_CEC_HW_DEBUG_TX
 
- TEGRA_CEC_HW_DEBUG_TX_DURATION_COUNT_SHIFT
 
- TEGRA_CEC_HW_DEBUG_TX_FORCELOOUT
 
- TEGRA_CEC_HW_DEBUG_TX_STATE_SHIFT
 
- TEGRA_CEC_HW_DEBUG_TX_TXBIT_COUNT_SHIFT
 
- TEGRA_CEC_HW_DEBUG_TX_TXDATABIT_SAMPLE_TIMER
 
- TEGRA_CEC_INPUT_FILTER
 
- TEGRA_CEC_INPUT_FILTER_FIFO_LENGTH_SHIFT
 
- TEGRA_CEC_INPUT_FILTER_MODE
 
- TEGRA_CEC_INT_MASK
 
- TEGRA_CEC_INT_MASK_FILTERED_RX_DATA_PIN_TRANSITION_H2L
 
- TEGRA_CEC_INT_MASK_FILTERED_RX_DATA_PIN_TRANSITION_L2H
 
- TEGRA_CEC_INT_MASK_RX_BUS_ANOMALY_DETECTED
 
- TEGRA_CEC_INT_MASK_RX_BUS_ERROR_DETECTED
 
- TEGRA_CEC_INT_MASK_RX_REGISTER_FULL
 
- TEGRA_CEC_INT_MASK_RX_REGISTER_OVERRUN
 
- TEGRA_CEC_INT_MASK_RX_START_BIT_DETECTED
 
- TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED
 
- TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED
 
- TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD
 
- TEGRA_CEC_INT_MASK_TX_FRAME_TRANSMITTED
 
- TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY
 
- TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN
 
- TEGRA_CEC_INT_STAT
 
- TEGRA_CEC_INT_STAT_FILTERED_RX_DATA_PIN_TRANSITION_H2L
 
- TEGRA_CEC_INT_STAT_FILTERED_RX_DATA_PIN_TRANSITION_L2H
 
- TEGRA_CEC_INT_STAT_RX_BUS_ANOMALY_DETECTED
 
- TEGRA_CEC_INT_STAT_RX_BUS_ERROR_DETECTED
 
- TEGRA_CEC_INT_STAT_RX_REGISTER_FULL
 
- TEGRA_CEC_INT_STAT_RX_REGISTER_OVERRUN
 
- TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED
 
- TEGRA_CEC_INT_STAT_TX_ARBITRATION_FAILED
 
- TEGRA_CEC_INT_STAT_TX_BUS_ANOMALY_DETECTED
 
- TEGRA_CEC_INT_STAT_TX_FRAME_OR_BLOCK_NAKD
 
- TEGRA_CEC_INT_STAT_TX_FRAME_TRANSMITTED
 
- TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY
 
- TEGRA_CEC_INT_STAT_TX_REGISTER_UNDERRUN
 
- TEGRA_CEC_NAME
 
- TEGRA_CEC_RX_REGISTER
 
- TEGRA_CEC_RX_REGISTER_ACK
 
- TEGRA_CEC_RX_REGISTER_EOM
 
- TEGRA_CEC_RX_REGISTER_SHIFT
 
- TEGRA_CEC_RX_TIM0_START_BIT_MAX_DURATION_SHIFT
 
- TEGRA_CEC_RX_TIM0_START_BIT_MAX_LO_TIME_SHIFT
 
- TEGRA_CEC_RX_TIM0_START_BIT_MIN_DURATION_SHIFT
 
- TEGRA_CEC_RX_TIM0_START_BIT_MIN_LO_TIME_SHIFT
 
- TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_DURATION_SHIFT
 
- TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_LO_TIME_SHIFT
 
- TEGRA_CEC_RX_TIM1_DATA_BIT_MIN_DURATION_SHIFT
 
- TEGRA_CEC_RX_TIM1_DATA_BIT_SAMPLE_TIME_SHIFT
 
- TEGRA_CEC_RX_TIM2_END_OF_BLOCK_TIME_SHIFT
 
- TEGRA_CEC_RX_TIMING_0
 
- TEGRA_CEC_RX_TIMING_1
 
- TEGRA_CEC_RX_TIMING_2
 
- TEGRA_CEC_SW_CONTROL
 
- TEGRA_CEC_TX_REGISTER
 
- TEGRA_CEC_TX_REG_BCAST
 
- TEGRA_CEC_TX_REG_DATA_SHIFT
 
- TEGRA_CEC_TX_REG_EOM
 
- TEGRA_CEC_TX_REG_RETRY
 
- TEGRA_CEC_TX_REG_START_BIT
 
- TEGRA_CEC_TX_TIM0_BUS_ERROR_LO_TIME_SHIFT
 
- TEGRA_CEC_TX_TIM0_BUS_XITION_TIME_SHIFT
 
- TEGRA_CEC_TX_TIM0_START_BIT_DURATION_SHIFT
 
- TEGRA_CEC_TX_TIM0_START_BIT_LO_TIME_SHIFT
 
- TEGRA_CEC_TX_TIM1_ACK_NAK_BIT_SAMPLE_TIME_SHIFT
 
- TEGRA_CEC_TX_TIM1_DATA_BIT_DURATION_SHIFT
 
- TEGRA_CEC_TX_TIM1_HI_DATA_BIT_LO_TIME_SHIFT
 
- TEGRA_CEC_TX_TIM1_LO_DATA_BIT_LO_TIME_SHIFT
 
- TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_ADDITIONAL_FRAME_SHIFT
 
- TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_NEW_FRAME_SHIFT
 
- TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_RETRY_FRAME_SHIFT
 
- TEGRA_CEC_TX_TIMING_0
 
- TEGRA_CEC_TX_TIMING_1
 
- TEGRA_CEC_TX_TIMING_2
 
- TEGRA_CLK_DUPLICATE
 
- TEGRA_CLK_OUT_ENB_H
 
- TEGRA_CLK_OUT_ENB_L
 
- TEGRA_CLK_OUT_ENB_U
 
- TEGRA_CLK_PERIPH
 
- TEGRA_CLK_PERIPH_GATE_MAGIC
 
- TEGRA_CLK_PERIPH_MAGIC
 
- TEGRA_CLK_RESET_BASE
 
- TEGRA_CLK_RESET_SIZE
 
- TEGRA_CLK_RESET_VIRT
 
- TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX
 
- TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR
 
- TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET
 
- TEGRA_CLK_RST_DEVICES_H
 
- TEGRA_CLK_RST_DEVICES_L
 
- TEGRA_CLK_RST_DEVICES_U
 
- TEGRA_CSITE_BASE
 
- TEGRA_CSITE_SIZE
 
- TEGRA_DC_H
 
- TEGRA_DFLL_PMU_I2C
 
- TEGRA_DFLL_PMU_PWM
 
- TEGRA_DIVIDER_2
 
- TEGRA_DIVIDER_FIXED
 
- TEGRA_DIVIDER_INT
 
- TEGRA_DIVIDER_ROUND_UP
 
- TEGRA_DIVIDER_UART
 
- TEGRA_DSI_FORMAT_16P
 
- TEGRA_DSI_FORMAT_18NP
 
- TEGRA_DSI_FORMAT_18P
 
- TEGRA_DSI_FORMAT_24P
 
- TEGRA_EMC0_BASE
 
- TEGRA_EMC0_SIZE
 
- TEGRA_EMC1_BASE
 
- TEGRA_EMC1_SIZE
 
- TEGRA_EMC_BASE
 
- TEGRA_EMC_SIZE
 
- TEGRA_EXCEPTION_VECTORS_BASE
 
- TEGRA_EXCEPTION_VECTORS_SIZE
 
- TEGRA_FLOW_CTRL_BASE
 
- TEGRA_FLOW_CTRL_SIZE
 
- TEGRA_FLOW_CTRL_VIRT
 
- TEGRA_FLUSH_CACHE_ALL
 
- TEGRA_FLUSH_CACHE_LOUIS
 
- TEGRA_FUSE_SKU_CALIB_0
 
- TEGRA_FUSE_USB_CALIB_EXT_0
 
- TEGRA_GMI_ADV_ACTIVE_HIGH
 
- TEGRA_GMI_ADV_WIDTH
 
- TEGRA_GMI_BUS_WIDTH_32BIT
 
- TEGRA_GMI_CE_WIDTH
 
- TEGRA_GMI_CONFIG
 
- TEGRA_GMI_CONFIG_GO
 
- TEGRA_GMI_CS_ACTIVE_HIGH
 
- TEGRA_GMI_CS_SELECT
 
- TEGRA_GMI_HOLD_WIDTH
 
- TEGRA_GMI_MAX_CHIP_SELECT
 
- TEGRA_GMI_MUXED_WIDTH
 
- TEGRA_GMI_MUX_MODE
 
- TEGRA_GMI_OE_ACTIVE_HIGH
 
- TEGRA_GMI_OE_WIDTH
 
- TEGRA_GMI_RDY_ACTIVE_HIGH
 
- TEGRA_GMI_RDY_BEFORE_DATA
 
- TEGRA_GMI_TIMING0
 
- TEGRA_GMI_TIMING1
 
- TEGRA_GMI_WAIT_WIDTH
 
- TEGRA_GMI_WE_WIDTH
 
- TEGRA_GPIO
 
- TEGRA_GPIO_PORT_A
 
- TEGRA_GPIO_PORT_AA
 
- TEGRA_GPIO_PORT_B
 
- TEGRA_GPIO_PORT_BB
 
- TEGRA_GPIO_PORT_C
 
- TEGRA_GPIO_PORT_CC
 
- TEGRA_GPIO_PORT_D
 
- TEGRA_GPIO_PORT_DD
 
- TEGRA_GPIO_PORT_E
 
- TEGRA_GPIO_PORT_EE
 
- TEGRA_GPIO_PORT_F
 
- TEGRA_GPIO_PORT_FF
 
- TEGRA_GPIO_PORT_G
 
- TEGRA_GPIO_PORT_H
 
- TEGRA_GPIO_PORT_I
 
- TEGRA_GPIO_PORT_J
 
- TEGRA_GPIO_PORT_K
 
- TEGRA_GPIO_PORT_L
 
- TEGRA_GPIO_PORT_M
 
- TEGRA_GPIO_PORT_N
 
- TEGRA_GPIO_PORT_O
 
- TEGRA_GPIO_PORT_P
 
- TEGRA_GPIO_PORT_Q
 
- TEGRA_GPIO_PORT_R
 
- TEGRA_GPIO_PORT_S
 
- TEGRA_GPIO_PORT_T
 
- TEGRA_GPIO_PORT_U
 
- TEGRA_GPIO_PORT_V
 
- TEGRA_GPIO_PORT_W
 
- TEGRA_GPIO_PORT_X
 
- TEGRA_GPIO_PORT_Y
 
- TEGRA_GPIO_PORT_Z
 
- TEGRA_GR2D_H
 
- TEGRA_GR3D_H
 
- TEGRA_HDMI_H
 
- TEGRA_HSP_DB_MASTER_BPMP
 
- TEGRA_HSP_DB_MASTER_CCPLEX
 
- TEGRA_HSP_MBOX_TYPE_AS
 
- TEGRA_HSP_MBOX_TYPE_DB
 
- TEGRA_HSP_MBOX_TYPE_SM
 
- TEGRA_HSP_MBOX_TYPE_SS
 
- TEGRA_HSP_SM_FLAG_RX
 
- TEGRA_HSP_SM_FLAG_TX
 
- TEGRA_HSP_SM_MASK
 
- TEGRA_HSP_SM_RX
 
- TEGRA_HSP_SM_TX
 
- TEGRA_HUB_H
 
- TEGRA_I2C_IPC_MAX_IN_BUF_SIZE
 
- TEGRA_I2C_IPC_MAX_OUT_BUF_SIZE
 
- TEGRA_INIT_DATA
 
- TEGRA_INIT_DATA_DIV16
 
- TEGRA_INIT_DATA_INT
 
- TEGRA_INIT_DATA_MUX
 
- TEGRA_INIT_DATA_MUX8
 
- TEGRA_INIT_DATA_NODIV
 
- TEGRA_INIT_DATA_TABLE
 
- TEGRA_IO_PAD
 
- TEGRA_IO_PAD_AO_HV
 
- TEGRA_IO_PAD_AUDIO
 
- TEGRA_IO_PAD_AUDIO_HV
 
- TEGRA_IO_PAD_BB
 
- TEGRA_IO_PAD_CAM
 
- TEGRA_IO_PAD_COMP
 
- TEGRA_IO_PAD_CONN
 
- TEGRA_IO_PAD_CSIA
 
- TEGRA_IO_PAD_CSIB
 
- TEGRA_IO_PAD_CSIC
 
- TEGRA_IO_PAD_CSID
 
- TEGRA_IO_PAD_CSIE
 
- TEGRA_IO_PAD_CSIF
 
- TEGRA_IO_PAD_CSIG
 
- TEGRA_IO_PAD_CSIH
 
- TEGRA_IO_PAD_DAP3
 
- TEGRA_IO_PAD_DAP5
 
- TEGRA_IO_PAD_DBG
 
- TEGRA_IO_PAD_DEBUG_NONAO
 
- TEGRA_IO_PAD_DMIC
 
- TEGRA_IO_PAD_DMIC_HV
 
- TEGRA_IO_PAD_DP
 
- TEGRA_IO_PAD_DSI
 
- TEGRA_IO_PAD_DSIB
 
- TEGRA_IO_PAD_DSIC
 
- TEGRA_IO_PAD_DSID
 
- TEGRA_IO_PAD_EDP
 
- TEGRA_IO_PAD_EMMC
 
- TEGRA_IO_PAD_EMMC2
 
- TEGRA_IO_PAD_EQOS
 
- TEGRA_IO_PAD_GPIO
 
- TEGRA_IO_PAD_GP_PWM2
 
- TEGRA_IO_PAD_GP_PWM3
 
- TEGRA_IO_PAD_HDMI
 
- TEGRA_IO_PAD_HDMI_DP0
 
- TEGRA_IO_PAD_HDMI_DP1
 
- TEGRA_IO_PAD_HDMI_DP2
 
- TEGRA_IO_PAD_HDMI_DP3
 
- TEGRA_IO_PAD_HSIC
 
- TEGRA_IO_PAD_HV
 
- TEGRA_IO_PAD_LVDS
 
- TEGRA_IO_PAD_MIPI_BIAS
 
- TEGRA_IO_PAD_NAND
 
- TEGRA_IO_PAD_PEX_BIAS
 
- TEGRA_IO_PAD_PEX_CLK1
 
- TEGRA_IO_PAD_PEX_CLK2
 
- TEGRA_IO_PAD_PEX_CLK2_BIAS
 
- TEGRA_IO_PAD_PEX_CLK3
 
- TEGRA_IO_PAD_PEX_CLK_BIAS
 
- TEGRA_IO_PAD_PEX_CNTRL
 
- TEGRA_IO_PAD_PEX_CTL2
 
- TEGRA_IO_PAD_PEX_L0_RST_N
 
- TEGRA_IO_PAD_PEX_L1_RST_N
 
- TEGRA_IO_PAD_PEX_L5_RST_N
 
- TEGRA_IO_PAD_PWR_CTL
 
- TEGRA_IO_PAD_SDMMC1
 
- TEGRA_IO_PAD_SDMMC1_HV
 
- TEGRA_IO_PAD_SDMMC2
 
- TEGRA_IO_PAD_SDMMC2_HV
 
- TEGRA_IO_PAD_SDMMC3
 
- TEGRA_IO_PAD_SDMMC3_HV
 
- TEGRA_IO_PAD_SDMMC4
 
- TEGRA_IO_PAD_SOC_GPIO10
 
- TEGRA_IO_PAD_SOC_GPIO12
 
- TEGRA_IO_PAD_SOC_GPIO13
 
- TEGRA_IO_PAD_SOC_GPIO53
 
- TEGRA_IO_PAD_SPI
 
- TEGRA_IO_PAD_SPI_HV
 
- TEGRA_IO_PAD_SYS_DDC
 
- TEGRA_IO_PAD_UART
 
- TEGRA_IO_PAD_UART4
 
- TEGRA_IO_PAD_UART5
 
- TEGRA_IO_PAD_UFS
 
- TEGRA_IO_PAD_USB0
 
- TEGRA_IO_PAD_USB1
 
- TEGRA_IO_PAD_USB2
 
- TEGRA_IO_PAD_USB3
 
- TEGRA_IO_PAD_USB_BIAS
 
- TEGRA_IO_PAD_VOLTAGE_1V8
 
- TEGRA_IO_PAD_VOLTAGE_3V3
 
- TEGRA_IO_PIN_DESC
 
- TEGRA_IO_RAIL_HDMI
 
- TEGRA_IO_RAIL_LVDS
 
- TEGRA_IRAM_BASE
 
- TEGRA_IRAM_LPx_RESUME_AREA
 
- TEGRA_IRAM_RESET_BASE
 
- TEGRA_IRAM_RESET_BASE_VIRT
 
- TEGRA_IRAM_RESET_HANDLER_OFFSET
 
- TEGRA_IRAM_RESET_HANDLER_SIZE
 
- TEGRA_IRAM_SIZE
 
- TEGRA_IVC_ALIGN
 
- TEGRA_IVC_STATE_ACK
 
- TEGRA_IVC_STATE_ESTABLISHED
 
- TEGRA_IVC_STATE_SYNC
 
- TEGRA_MAX_NUM_ICTLRS
 
- TEGRA_MAX_SUSPEND_MODE
 
- TEGRA_MC_SECURITY_CARVEOUT_CFG_LOCKED
 
- TEGRA_MDIV_NEW
 
- TEGRA_MUX_AHB_CLK
 
- TEGRA_MUX_APB_CLK
 
- TEGRA_MUX_AUD
 
- TEGRA_MUX_AUDIO_SYNC
 
- TEGRA_MUX_BCL
 
- TEGRA_MUX_BLINK
 
- TEGRA_MUX_CCLA
 
- TEGRA_MUX_CEC
 
- TEGRA_MUX_CLDVFS
 
- TEGRA_MUX_CLK
 
- TEGRA_MUX_CLK12
 
- TEGRA_MUX_CLK_12M_OUT
 
- TEGRA_MUX_CLK_32K_IN
 
- TEGRA_MUX_CORE
 
- TEGRA_MUX_CORE_PWR_REQ
 
- TEGRA_MUX_CPU
 
- TEGRA_MUX_CPU_PWR_REQ
 
- TEGRA_MUX_CRT
 
- TEGRA_MUX_CSI
 
- TEGRA_MUX_DAP
 
- TEGRA_MUX_DAP1
 
- TEGRA_MUX_DAP2
 
- TEGRA_MUX_DAP3
 
- TEGRA_MUX_DAP4
 
- TEGRA_MUX_DAP5
 
- TEGRA_MUX_DDR
 
- TEGRA_MUX_DEV3
 
- TEGRA_MUX_DISPLAYA
 
- TEGRA_MUX_DISPLAYA_ALT
 
- TEGRA_MUX_DISPLAYB
 
- TEGRA_MUX_DMIC1
 
- TEGRA_MUX_DMIC2
 
- TEGRA_MUX_DMIC3
 
- TEGRA_MUX_DP
 
- TEGRA_MUX_DSI_B
 
- TEGRA_MUX_DTV
 
- TEGRA_MUX_EMC_DLL
 
- TEGRA_MUX_EMC_TEST0_DLL
 
- TEGRA_MUX_EMC_TEST1_DLL
 
- TEGRA_MUX_EXTPERIPH1
 
- TEGRA_MUX_EXTPERIPH2
 
- TEGRA_MUX_EXTPERIPH3
 
- TEGRA_MUX_GMI
 
- TEGRA_MUX_GMI_ALT
 
- TEGRA_MUX_GMI_INT
 
- TEGRA_MUX_HDA
 
- TEGRA_MUX_HDCP
 
- TEGRA_MUX_HDMI
 
- TEGRA_MUX_HSI
 
- TEGRA_MUX_I2C1
 
- TEGRA_MUX_I2C2
 
- TEGRA_MUX_I2C3
 
- TEGRA_MUX_I2C4
 
- TEGRA_MUX_I2CP
 
- TEGRA_MUX_I2CPMU
 
- TEGRA_MUX_I2CPWR
 
- TEGRA_MUX_I2CVI
 
- TEGRA_MUX_I2S0
 
- TEGRA_MUX_I2S1
 
- TEGRA_MUX_I2S2
 
- TEGRA_MUX_I2S3
 
- TEGRA_MUX_I2S4
 
- TEGRA_MUX_I2S4A
 
- TEGRA_MUX_I2S4B
 
- TEGRA_MUX_I2S5A
 
- TEGRA_MUX_I2S5B
 
- TEGRA_MUX_IDE
 
- TEGRA_MUX_INVALID
 
- TEGRA_MUX_IQC0
 
- TEGRA_MUX_IQC1
 
- TEGRA_MUX_IRDA
 
- TEGRA_MUX_JTAG
 
- TEGRA_MUX_KBC
 
- TEGRA_MUX_MIO
 
- TEGRA_MUX_MIPI_HS
 
- TEGRA_MUX_NAND
 
- TEGRA_MUX_NAND_ALT
 
- TEGRA_MUX_OSC
 
- TEGRA_MUX_OWR
 
- TEGRA_MUX_PCIE
 
- TEGRA_MUX_PE
 
- TEGRA_MUX_PE0
 
- TEGRA_MUX_PE1
 
- TEGRA_MUX_PE5
 
- TEGRA_MUX_PLLA_OUT
 
- TEGRA_MUX_PLLC_OUT1
 
- TEGRA_MUX_PLLM_OUT1
 
- TEGRA_MUX_PLLP_OUT2
 
- TEGRA_MUX_PLLP_OUT3
 
- TEGRA_MUX_PLLP_OUT4
 
- TEGRA_MUX_PMI
 
- TEGRA_MUX_PWM
 
- TEGRA_MUX_PWM0
 
- TEGRA_MUX_PWM1
 
- TEGRA_MUX_PWM2
 
- TEGRA_MUX_PWM3
 
- TEGRA_MUX_PWRON
 
- TEGRA_MUX_PWR_INTR
 
- TEGRA_MUX_PWR_INT_N
 
- TEGRA_MUX_PWR_ON
 
- TEGRA_MUX_QSPI
 
- TEGRA_MUX_RESET_OUT_N
 
- TEGRA_MUX_RSVD0
 
- TEGRA_MUX_RSVD1
 
- TEGRA_MUX_RSVD2
 
- TEGRA_MUX_RSVD3
 
- TEGRA_MUX_RSVD4
 
- TEGRA_MUX_RTCK
 
- TEGRA_MUX_SATA
 
- TEGRA_MUX_SDIO1
 
- TEGRA_MUX_SDIO2
 
- TEGRA_MUX_SDIO3
 
- TEGRA_MUX_SDIO4
 
- TEGRA_MUX_SDMMC1
 
- TEGRA_MUX_SDMMC2
 
- TEGRA_MUX_SDMMC3
 
- TEGRA_MUX_SDMMC4
 
- TEGRA_MUX_SFLASH
 
- TEGRA_MUX_SHUTDOWN
 
- TEGRA_MUX_SOC
 
- TEGRA_MUX_SOR0
 
- TEGRA_MUX_SOR1
 
- TEGRA_MUX_SPDIF
 
- TEGRA_MUX_SPI1
 
- TEGRA_MUX_SPI2
 
- TEGRA_MUX_SPI2_ALT
 
- TEGRA_MUX_SPI3
 
- TEGRA_MUX_SPI4
 
- TEGRA_MUX_SPI5
 
- TEGRA_MUX_SPI6
 
- TEGRA_MUX_SYS
 
- TEGRA_MUX_SYSCLK
 
- TEGRA_MUX_TEST
 
- TEGRA_MUX_TMDS
 
- TEGRA_MUX_TOUCH
 
- TEGRA_MUX_TRACE
 
- TEGRA_MUX_TWC
 
- TEGRA_MUX_UART
 
- TEGRA_MUX_UARTA
 
- TEGRA_MUX_UARTB
 
- TEGRA_MUX_UARTC
 
- TEGRA_MUX_UARTD
 
- TEGRA_MUX_UARTE
 
- TEGRA_MUX_ULPI
 
- TEGRA_MUX_USB
 
- TEGRA_MUX_VGP1
 
- TEGRA_MUX_VGP2
 
- TEGRA_MUX_VGP3
 
- TEGRA_MUX_VGP4
 
- TEGRA_MUX_VGP5
 
- TEGRA_MUX_VGP6
 
- TEGRA_MUX_VI
 
- TEGRA_MUX_VIMCLK
 
- TEGRA_MUX_VIMCLK2
 
- TEGRA_MUX_VIMCLK2_ALT
 
- TEGRA_MUX_VI_ALT1
 
- TEGRA_MUX_VI_ALT2
 
- TEGRA_MUX_VI_ALT3
 
- TEGRA_MUX_VI_SENSOR_CLK
 
- TEGRA_MUX_XIO
 
- TEGRA_PCIE_LINKUP_TIMEOUT
 
- TEGRA_PERIPH_MANUAL_RESET
 
- TEGRA_PERIPH_NO_DIV
 
- TEGRA_PERIPH_NO_GATE
 
- TEGRA_PERIPH_NO_RESET
 
- TEGRA_PERIPH_ON_APB
 
- TEGRA_PERIPH_WAR_1005168
 
- TEGRA_PINCONFIG_DRIVEN
 
- TEGRA_PINCONFIG_PULL_DOWN
 
- TEGRA_PINCONFIG_PULL_NONE
 
- TEGRA_PINCONFIG_PULL_UP
 
- TEGRA_PINCONFIG_TRISTATE
 
- TEGRA_PINCONF_PACK
 
- TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH
 
- TEGRA_PINCONF_PARAM_DRIVE_TYPE
 
- TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH
 
- TEGRA_PINCONF_PARAM_ENABLE_INPUT
 
- TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE
 
- TEGRA_PINCONF_PARAM_IORESET
 
- TEGRA_PINCONF_PARAM_LOCK
 
- TEGRA_PINCONF_PARAM_LOW_POWER_MODE
 
- TEGRA_PINCONF_PARAM_OPEN_DRAIN
 
- TEGRA_PINCONF_PARAM_PULL
 
- TEGRA_PINCONF_PARAM_RCV_SEL
 
- TEGRA_PINCONF_PARAM_SCHMITT
 
- TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING
 
- TEGRA_PINCONF_PARAM_SLEW_RATE_RISING
 
- TEGRA_PINCONF_PARAM_TRISTATE
 
- TEGRA_PINCONF_UNPACK_ARG
 
- TEGRA_PINCONF_UNPACK_PARAM
 
- TEGRA_PIN_ALS_PROX_INT_PX3
 
- TEGRA_PIN_AP_READY_PV5
 
- TEGRA_PIN_AP_WAKE_BT_PH3
 
- TEGRA_PIN_AP_WAKE_NFC_PH7
 
- TEGRA_PIN_AUD_MCLK_PBB0
 
- TEGRA_PIN_BATT_BCL
 
- TEGRA_PIN_BT_RST_PH4
 
- TEGRA_PIN_BT_WAKE_AP_PH5
 
- TEGRA_PIN_BUTTON_HOME_PY1
 
- TEGRA_PIN_BUTTON_POWER_ON_PX5
 
- TEGRA_PIN_BUTTON_SLIDE_SW_PY0
 
- TEGRA_PIN_BUTTON_VOL_DOWN_PX7
 
- TEGRA_PIN_BUTTON_VOL_UP_PX6
 
- TEGRA_PIN_CAM1_MCLK_PS0
 
- TEGRA_PIN_CAM1_PWDN_PS7
 
- TEGRA_PIN_CAM1_STROBE_PT1
 
- TEGRA_PIN_CAM2_MCLK_PS1
 
- TEGRA_PIN_CAM2_PWDN_PT0
 
- TEGRA_PIN_CAM_AF_EN_PS5
 
- TEGRA_PIN_CAM_FLASH_EN_PS6
 
- TEGRA_PIN_CAM_I2C_SCL_PBB1
 
- TEGRA_PIN_CAM_I2C_SCL_PBB2
 
- TEGRA_PIN_CAM_I2C_SCL_PS2
 
- TEGRA_PIN_CAM_I2C_SDA_PBB2
 
- TEGRA_PIN_CAM_I2C_SDA_PBB3
 
- TEGRA_PIN_CAM_I2C_SDA_PS3
 
- TEGRA_PIN_CAM_MCLK_PCC0
 
- TEGRA_PIN_CAM_RST_PS4
 
- TEGRA_PIN_CLK1_OUT_PW4
 
- TEGRA_PIN_CLK1_REQ_PEE2
 
- TEGRA_PIN_CLK2_OUT_PW5
 
- TEGRA_PIN_CLK2_REQ_PCC5
 
- TEGRA_PIN_CLK3_OUT_PEE0
 
- TEGRA_PIN_CLK3_REQ_PEE1
 
- TEGRA_PIN_CLK_32K_IN
 
- TEGRA_PIN_CLK_32K_OUT_PA0
 
- TEGRA_PIN_CLK_32K_OUT_PY5
 
- TEGRA_PIN_CLK_32_K_IN
 
- TEGRA_PIN_CLK_REQ
 
- TEGRA_PIN_CORE_PWR_REQ
 
- TEGRA_PIN_CPU_PWR_REQ
 
- TEGRA_PIN_CRT_HSYNC
 
- TEGRA_PIN_CRT_HSYNC_PV6
 
- TEGRA_PIN_CRT_VSYNC
 
- TEGRA_PIN_CRT_VSYNC_PV7
 
- TEGRA_PIN_DAP1_DIN_PB1
 
- TEGRA_PIN_DAP1_DIN_PN1
 
- TEGRA_PIN_DAP1_DOUT_PB2
 
- TEGRA_PIN_DAP1_DOUT_PN2
 
- TEGRA_PIN_DAP1_FS_PB0
 
- TEGRA_PIN_DAP1_FS_PN0
 
- TEGRA_PIN_DAP1_SCLK_PB3
 
- TEGRA_PIN_DAP1_SCLK_PN3
 
- TEGRA_PIN_DAP2_DIN_PA4
 
- TEGRA_PIN_DAP2_DIN_PAA2
 
- TEGRA_PIN_DAP2_DOUT_PA5
 
- TEGRA_PIN_DAP2_DOUT_PAA3
 
- TEGRA_PIN_DAP2_FS_PA2
 
- TEGRA_PIN_DAP2_FS_PAA0
 
- TEGRA_PIN_DAP2_SCLK_PA3
 
- TEGRA_PIN_DAP2_SCLK_PAA1
 
- TEGRA_PIN_DAP3_DIN_PP1
 
- TEGRA_PIN_DAP3_DOUT_PP2
 
- TEGRA_PIN_DAP3_FS_PP0
 
- TEGRA_PIN_DAP3_SCLK_PP3
 
- TEGRA_PIN_DAP4_DIN_PJ5
 
- TEGRA_PIN_DAP4_DIN_PP5
 
- TEGRA_PIN_DAP4_DOUT_PJ6
 
- TEGRA_PIN_DAP4_DOUT_PP6
 
- TEGRA_PIN_DAP4_FS_PJ4
 
- TEGRA_PIN_DAP4_FS_PP4
 
- TEGRA_PIN_DAP4_SCLK_PJ7
 
- TEGRA_PIN_DAP4_SCLK_PP7
 
- TEGRA_PIN_DAP_MCLK1_PW4
 
- TEGRA_PIN_DAP_MCLK1_REQ_PEE2
 
- TEGRA_PIN_DAP_MCLK2_PW5
 
- TEGRA_PIN_DDC_SCL
 
- TEGRA_PIN_DDC_SCL_PV4
 
- TEGRA_PIN_DDC_SDA
 
- TEGRA_PIN_DDC_SDA_PV5
 
- TEGRA_PIN_DDR_A0
 
- TEGRA_PIN_DDR_A1
 
- TEGRA_PIN_DDR_A10
 
- TEGRA_PIN_DDR_A11
 
- TEGRA_PIN_DDR_A12
 
- TEGRA_PIN_DDR_A13
 
- TEGRA_PIN_DDR_A14
 
- TEGRA_PIN_DDR_A2
 
- TEGRA_PIN_DDR_A3
 
- TEGRA_PIN_DDR_A4
 
- TEGRA_PIN_DDR_A5
 
- TEGRA_PIN_DDR_A6
 
- TEGRA_PIN_DDR_A7
 
- TEGRA_PIN_DDR_A8
 
- TEGRA_PIN_DDR_A9
 
- TEGRA_PIN_DDR_BA0
 
- TEGRA_PIN_DDR_BA1
 
- TEGRA_PIN_DDR_BA2
 
- TEGRA_PIN_DDR_CAS_N
 
- TEGRA_PIN_DDR_CKE0
 
- TEGRA_PIN_DDR_CKE1
 
- TEGRA_PIN_DDR_CLK
 
- TEGRA_PIN_DDR_CLK_N
 
- TEGRA_PIN_DDR_COMP_PD
 
- TEGRA_PIN_DDR_COMP_PU
 
- TEGRA_PIN_DDR_CS0_N
 
- TEGRA_PIN_DDR_CS1_N
 
- TEGRA_PIN_DDR_DM0
 
- TEGRA_PIN_DDR_DM1
 
- TEGRA_PIN_DDR_DM2
 
- TEGRA_PIN_DDR_DM3
 
- TEGRA_PIN_DDR_DQ0
 
- TEGRA_PIN_DDR_DQ1
 
- TEGRA_PIN_DDR_DQ10
 
- TEGRA_PIN_DDR_DQ11
 
- TEGRA_PIN_DDR_DQ12
 
- TEGRA_PIN_DDR_DQ13
 
- TEGRA_PIN_DDR_DQ14
 
- TEGRA_PIN_DDR_DQ15
 
- TEGRA_PIN_DDR_DQ16
 
- TEGRA_PIN_DDR_DQ17
 
- TEGRA_PIN_DDR_DQ18
 
- TEGRA_PIN_DDR_DQ19
 
- TEGRA_PIN_DDR_DQ2
 
- TEGRA_PIN_DDR_DQ20
 
- TEGRA_PIN_DDR_DQ21
 
- TEGRA_PIN_DDR_DQ22
 
- TEGRA_PIN_DDR_DQ23
 
- TEGRA_PIN_DDR_DQ24
 
- TEGRA_PIN_DDR_DQ25
 
- TEGRA_PIN_DDR_DQ26
 
- TEGRA_PIN_DDR_DQ27
 
- TEGRA_PIN_DDR_DQ28
 
- TEGRA_PIN_DDR_DQ29
 
- TEGRA_PIN_DDR_DQ3
 
- TEGRA_PIN_DDR_DQ30
 
- TEGRA_PIN_DDR_DQ31
 
- TEGRA_PIN_DDR_DQ4
 
- TEGRA_PIN_DDR_DQ5
 
- TEGRA_PIN_DDR_DQ6
 
- TEGRA_PIN_DDR_DQ7
 
- TEGRA_PIN_DDR_DQ8
 
- TEGRA_PIN_DDR_DQ9
 
- TEGRA_PIN_DDR_DQS0N
 
- TEGRA_PIN_DDR_DQS0P
 
- TEGRA_PIN_DDR_DQS1N
 
- TEGRA_PIN_DDR_DQS1P
 
- TEGRA_PIN_DDR_DQS2N
 
- TEGRA_PIN_DDR_DQS2P
 
- TEGRA_PIN_DDR_DQS3N
 
- TEGRA_PIN_DDR_DQS3P
 
- TEGRA_PIN_DDR_ODT
 
- TEGRA_PIN_DDR_QUSE0
 
- TEGRA_PIN_DDR_QUSE1
 
- TEGRA_PIN_DDR_QUSE2
 
- TEGRA_PIN_DDR_QUSE3
 
- TEGRA_PIN_DDR_RAS_N
 
- TEGRA_PIN_DDR_WE_N
 
- TEGRA_PIN_DISABLE
 
- TEGRA_PIN_DMIC1_CLK_PE0
 
- TEGRA_PIN_DMIC1_DAT_PE1
 
- TEGRA_PIN_DMIC2_CLK_PE2
 
- TEGRA_PIN_DMIC2_DAT_PE3
 
- TEGRA_PIN_DMIC3_CLK_PE4
 
- TEGRA_PIN_DMIC3_DAT_PE5
 
- TEGRA_PIN_DP_HPD0_PCC6
 
- TEGRA_PIN_DP_HPD_PFF0
 
- TEGRA_PIN_DSI_B_CLK_N
 
- TEGRA_PIN_DSI_B_CLK_P
 
- TEGRA_PIN_DSI_B_D0_N
 
- TEGRA_PIN_DSI_B_D0_P
 
- TEGRA_PIN_DSI_B_D1_N
 
- TEGRA_PIN_DSI_B_D1_P
 
- TEGRA_PIN_DSI_B_D2_N
 
- TEGRA_PIN_DSI_B_D2_P
 
- TEGRA_PIN_DSI_B_D3_N
 
- TEGRA_PIN_DSI_B_D3_P
 
- TEGRA_PIN_DVFS_CLK_PBB2
 
- TEGRA_PIN_DVFS_CLK_PX2
 
- TEGRA_PIN_DVFS_PWM_PBB1
 
- TEGRA_PIN_DVFS_PWM_PX0
 
- TEGRA_PIN_ENABLE
 
- TEGRA_PIN_FUNCTION
 
- TEGRA_PIN_GEN1_I2C_SCL_PC4
 
- TEGRA_PIN_GEN1_I2C_SCL_PJ1
 
- TEGRA_PIN_GEN1_I2C_SDA_PC5
 
- TEGRA_PIN_GEN1_I2C_SDA_PJ0
 
- TEGRA_PIN_GEN2_I2C_SCL_PJ2
 
- TEGRA_PIN_GEN2_I2C_SCL_PT5
 
- TEGRA_PIN_GEN2_I2C_SDA_PJ3
 
- TEGRA_PIN_GEN2_I2C_SDA_PT6
 
- TEGRA_PIN_GEN3_I2C_SCL_PF0
 
- TEGRA_PIN_GEN3_I2C_SDA_PF1
 
- TEGRA_PIN_GMI_A16_PJ7
 
- TEGRA_PIN_GMI_A17_PB0
 
- TEGRA_PIN_GMI_A18_PB1
 
- TEGRA_PIN_GMI_A19_PK7
 
- TEGRA_PIN_GMI_AD0_PG0
 
- TEGRA_PIN_GMI_AD10_PH2
 
- TEGRA_PIN_GMI_AD11_PH3
 
- TEGRA_PIN_GMI_AD12_PH4
 
- TEGRA_PIN_GMI_AD13_PH5
 
- TEGRA_PIN_GMI_AD14_PH6
 
- TEGRA_PIN_GMI_AD15_PH7
 
- TEGRA_PIN_GMI_AD16_PJ7
 
- TEGRA_PIN_GMI_AD17_PB0
 
- TEGRA_PIN_GMI_AD18_PB1
 
- TEGRA_PIN_GMI_AD19_PK7
 
- TEGRA_PIN_GMI_AD1_PG1
 
- TEGRA_PIN_GMI_AD20_PAA0
 
- TEGRA_PIN_GMI_AD21_PAA1
 
- TEGRA_PIN_GMI_AD22_PAA2
 
- TEGRA_PIN_GMI_AD23_PAA3
 
- TEGRA_PIN_GMI_AD24_PAA4
 
- TEGRA_PIN_GMI_AD25_PAA5
 
- TEGRA_PIN_GMI_AD26_PAA6
 
- TEGRA_PIN_GMI_AD27_PAA7
 
- TEGRA_PIN_GMI_AD2_PG2
 
- TEGRA_PIN_GMI_AD3_PG3
 
- TEGRA_PIN_GMI_AD4_PG4
 
- TEGRA_PIN_GMI_AD5_PG5
 
- TEGRA_PIN_GMI_AD6_PG6
 
- TEGRA_PIN_GMI_AD7_PG7
 
- TEGRA_PIN_GMI_AD8_PH0
 
- TEGRA_PIN_GMI_AD9_PH1
 
- TEGRA_PIN_GMI_ADV_N_PK0
 
- TEGRA_PIN_GMI_CLK_LB
 
- TEGRA_PIN_GMI_CLK_PK1
 
- TEGRA_PIN_GMI_CS0_N_PJ0
 
- TEGRA_PIN_GMI_CS1_N_PJ2
 
- TEGRA_PIN_GMI_CS2_N_PK3
 
- TEGRA_PIN_GMI_CS3_N_PK4
 
- TEGRA_PIN_GMI_CS4_N_PK2
 
- TEGRA_PIN_GMI_CS5_N_PI2
 
- TEGRA_PIN_GMI_CS6_N_PI3
 
- TEGRA_PIN_GMI_CS7_N_PI6
 
- TEGRA_PIN_GMI_DPD_PT7
 
- TEGRA_PIN_GMI_DQS_PI2
 
- TEGRA_PIN_GMI_DQS_P_PJ3
 
- TEGRA_PIN_GMI_HIOR_N_PI1
 
- TEGRA_PIN_GMI_HIOW_N_PI0
 
- TEGRA_PIN_GMI_IORDY_PI5
 
- TEGRA_PIN_GMI_OE_N_PI1
 
- TEGRA_PIN_GMI_RST_N_PI4
 
- TEGRA_PIN_GMI_WAIT_PI7
 
- TEGRA_PIN_GMI_WP_N_PC7
 
- TEGRA_PIN_GMI_WR_N_PI0
 
- TEGRA_PIN_GPIO_W2_AUD_PW2
 
- TEGRA_PIN_GPIO_W3_AUD_PW3
 
- TEGRA_PIN_GPIO_X1_AUD_PBB3
 
- TEGRA_PIN_GPIO_X1_AUD_PX1
 
- TEGRA_PIN_GPIO_X3_AUD_PBB4
 
- TEGRA_PIN_GPIO_X3_AUD_PX3
 
- TEGRA_PIN_GPIO_X4_AUD_PX4
 
- TEGRA_PIN_GPIO_X5_AUD_PX5
 
- TEGRA_PIN_GPIO_X6_AUD_PX6
 
- TEGRA_PIN_GPIO_X7_AUD_PX7
 
- TEGRA_PIN_GPS_EN_PI2
 
- TEGRA_PIN_GPS_RST_PI3
 
- TEGRA_PIN_HDMI_CEC_PCC0
 
- TEGRA_PIN_HDMI_CEC_PEE3
 
- TEGRA_PIN_HDMI_INT_DP_HPD_PCC1
 
- TEGRA_PIN_HDMI_INT_N_PN7
 
- TEGRA_PIN_HDMI_INT_PN7
 
- TEGRA_PIN_JTAG_RTCK
 
- TEGRA_PIN_JTAG_RTCK_PU7
 
- TEGRA_PIN_JTAG_TCK
 
- TEGRA_PIN_JTAG_TDI
 
- TEGRA_PIN_JTAG_TDO
 
- TEGRA_PIN_JTAG_TMS
 
- TEGRA_PIN_JTAG_TRST_N
 
- TEGRA_PIN_KB_COL0_PQ0
 
- TEGRA_PIN_KB_COL1_PQ1
 
- TEGRA_PIN_KB_COL2_PQ2
 
- TEGRA_PIN_KB_COL3_PQ3
 
- TEGRA_PIN_KB_COL4_PQ4
 
- TEGRA_PIN_KB_COL5_PQ5
 
- TEGRA_PIN_KB_COL6_PQ6
 
- TEGRA_PIN_KB_COL7_PQ7
 
- TEGRA_PIN_KB_ROW0_PR0
 
- TEGRA_PIN_KB_ROW10_PS2
 
- TEGRA_PIN_KB_ROW11_PS3
 
- TEGRA_PIN_KB_ROW12_PS4
 
- TEGRA_PIN_KB_ROW13_PS5
 
- TEGRA_PIN_KB_ROW14_PS6
 
- TEGRA_PIN_KB_ROW15_PS7
 
- TEGRA_PIN_KB_ROW16_PT0
 
- TEGRA_PIN_KB_ROW17_PT1
 
- TEGRA_PIN_KB_ROW1_PR1
 
- TEGRA_PIN_KB_ROW2_PR2
 
- TEGRA_PIN_KB_ROW3_PR3
 
- TEGRA_PIN_KB_ROW4_PR4
 
- TEGRA_PIN_KB_ROW5_PR5
 
- TEGRA_PIN_KB_ROW6_PR6
 
- TEGRA_PIN_KB_ROW7_PR7
 
- TEGRA_PIN_KB_ROW8_PS0
 
- TEGRA_PIN_KB_ROW9_PS1
 
- TEGRA_PIN_LCD_BL_EN_PV1
 
- TEGRA_PIN_LCD_BL_PWM_PV0
 
- TEGRA_PIN_LCD_CS0_N_PN4
 
- TEGRA_PIN_LCD_CS1_N_PW0
 
- TEGRA_PIN_LCD_D0_PE0
 
- TEGRA_PIN_LCD_D10_PF2
 
- TEGRA_PIN_LCD_D11_PF3
 
- TEGRA_PIN_LCD_D12_PF4
 
- TEGRA_PIN_LCD_D13_PF5
 
- TEGRA_PIN_LCD_D14_PF6
 
- TEGRA_PIN_LCD_D15_PF7
 
- TEGRA_PIN_LCD_D16_PM0
 
- TEGRA_PIN_LCD_D17_PM1
 
- TEGRA_PIN_LCD_D18_PM2
 
- TEGRA_PIN_LCD_D19_PM3
 
- TEGRA_PIN_LCD_D1_PE1
 
- TEGRA_PIN_LCD_D20_PM4
 
- TEGRA_PIN_LCD_D21_PM5
 
- TEGRA_PIN_LCD_D22_PM6
 
- TEGRA_PIN_LCD_D23_PM7
 
- TEGRA_PIN_LCD_D2_PE2
 
- TEGRA_PIN_LCD_D3_PE3
 
- TEGRA_PIN_LCD_D4_PE4
 
- TEGRA_PIN_LCD_D5_PE5
 
- TEGRA_PIN_LCD_D6_PE6
 
- TEGRA_PIN_LCD_D7_PE7
 
- TEGRA_PIN_LCD_D8_PF0
 
- TEGRA_PIN_LCD_D9_PF1
 
- TEGRA_PIN_LCD_DC0_PN6
 
- TEGRA_PIN_LCD_DC1_PD2
 
- TEGRA_PIN_LCD_DC1_PV7
 
- TEGRA_PIN_LCD_DE_PJ1
 
- TEGRA_PIN_LCD_GPIO1_PV3
 
- TEGRA_PIN_LCD_GPIO2_PV4
 
- TEGRA_PIN_LCD_HSYNC_PJ3
 
- TEGRA_PIN_LCD_M1_PW1
 
- TEGRA_PIN_LCD_PCLK_PB3
 
- TEGRA_PIN_LCD_PWR0_PB2
 
- TEGRA_PIN_LCD_PWR1_PC1
 
- TEGRA_PIN_LCD_PWR2_PC6
 
- TEGRA_PIN_LCD_RST_PV2
 
- TEGRA_PIN_LCD_SCK_PZ4
 
- TEGRA_PIN_LCD_SDIN_PZ2
 
- TEGRA_PIN_LCD_SDOUT_PN5
 
- TEGRA_PIN_LCD_TE_PY2
 
- TEGRA_PIN_LCD_VSYNC_PJ4
 
- TEGRA_PIN_LCD_WR_N_PZ3
 
- TEGRA_PIN_LED_BLINK_PBB0
 
- TEGRA_PIN_LP_DRIVE_DIV_1
 
- TEGRA_PIN_LP_DRIVE_DIV_2
 
- TEGRA_PIN_LP_DRIVE_DIV_4
 
- TEGRA_PIN_LP_DRIVE_DIV_8
 
- TEGRA_PIN_MODEM_WAKE_AP_PX0
 
- TEGRA_PIN_MOTION_INT_PX2
 
- TEGRA_PIN_NFC_EN_PI0
 
- TEGRA_PIN_NFC_INT_PI1
 
- TEGRA_PIN_NUM_GPIOS
 
- TEGRA_PIN_OWC
 
- TEGRA_PIN_OWR
 
- TEGRA_PIN_PA6
 
- TEGRA_PIN_PB0
 
- TEGRA_PIN_PB1
 
- TEGRA_PIN_PBB0
 
- TEGRA_PIN_PBB3
 
- TEGRA_PIN_PBB4
 
- TEGRA_PIN_PBB5
 
- TEGRA_PIN_PBB6
 
- TEGRA_PIN_PBB7
 
- TEGRA_PIN_PC7
 
- TEGRA_PIN_PCC1
 
- TEGRA_PIN_PCC2
 
- TEGRA_PIN_PCC7
 
- TEGRA_PIN_PE6
 
- TEGRA_PIN_PE7
 
- TEGRA_PIN_PEE4
 
- TEGRA_PIN_PEE5
 
- TEGRA_PIN_PEE6
 
- TEGRA_PIN_PEE7
 
- TEGRA_PIN_PEX_L0_CLKREQ_N_PA1
 
- TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2
 
- TEGRA_PIN_PEX_L0_PRSNT_N_PDD0
 
- TEGRA_PIN_PEX_L0_RST_N_PA0
 
- TEGRA_PIN_PEX_L0_RST_N_PDD1
 
- TEGRA_PIN_PEX_L1_CLKREQ_N_PA4
 
- TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6
 
- TEGRA_PIN_PEX_L1_PRSNT_N_PDD4
 
- TEGRA_PIN_PEX_L1_RST_N_PA3
 
- TEGRA_PIN_PEX_L1_RST_N_PDD5
 
- TEGRA_PIN_PEX_L2_CLKREQ_N_PCC7
 
- TEGRA_PIN_PEX_L2_PRSNT_N_PDD7
 
- TEGRA_PIN_PEX_L2_RST_N_PCC6
 
- TEGRA_PIN_PEX_L5_CLKREQ_N_PGG0
 
- TEGRA_PIN_PEX_L5_RST_N_PGG1
 
- TEGRA_PIN_PEX_WAKE_N_PA2
 
- TEGRA_PIN_PEX_WAKE_N_PDD3
 
- TEGRA_PIN_PFF2
 
- TEGRA_PIN_PG0
 
- TEGRA_PIN_PG1
 
- TEGRA_PIN_PG2
 
- TEGRA_PIN_PG3
 
- TEGRA_PIN_PG4
 
- TEGRA_PIN_PG5
 
- TEGRA_PIN_PG6
 
- TEGRA_PIN_PG7
 
- TEGRA_PIN_PH0
 
- TEGRA_PIN_PH1
 
- TEGRA_PIN_PH2
 
- TEGRA_PIN_PH3
 
- TEGRA_PIN_PH4
 
- TEGRA_PIN_PH5
 
- TEGRA_PIN_PH6
 
- TEGRA_PIN_PH7
 
- TEGRA_PIN_PI0
 
- TEGRA_PIN_PI1
 
- TEGRA_PIN_PI2
 
- TEGRA_PIN_PI3
 
- TEGRA_PIN_PI4
 
- TEGRA_PIN_PI5
 
- TEGRA_PIN_PI6
 
- TEGRA_PIN_PI7
 
- TEGRA_PIN_PJ0
 
- TEGRA_PIN_PJ2
 
- TEGRA_PIN_PJ7
 
- TEGRA_PIN_PK0
 
- TEGRA_PIN_PK1
 
- TEGRA_PIN_PK2
 
- TEGRA_PIN_PK3
 
- TEGRA_PIN_PK4
 
- TEGRA_PIN_PK5
 
- TEGRA_PIN_PK6
 
- TEGRA_PIN_PK7
 
- TEGRA_PIN_PL0
 
- TEGRA_PIN_PL1
 
- TEGRA_PIN_PU0
 
- TEGRA_PIN_PU1
 
- TEGRA_PIN_PU2
 
- TEGRA_PIN_PU3
 
- TEGRA_PIN_PU4
 
- TEGRA_PIN_PU5
 
- TEGRA_PIN_PU6
 
- TEGRA_PIN_PULL_DOWN
 
- TEGRA_PIN_PULL_NONE
 
- TEGRA_PIN_PULL_UP
 
- TEGRA_PIN_PV0
 
- TEGRA_PIN_PV1
 
- TEGRA_PIN_PV2
 
- TEGRA_PIN_PV3
 
- TEGRA_PIN_PV4
 
- TEGRA_PIN_PV5
 
- TEGRA_PIN_PV6
 
- TEGRA_PIN_PWR_I2C_SCL_PY3
 
- TEGRA_PIN_PWR_I2C_SCL_PZ6
 
- TEGRA_PIN_PWR_I2C_SDA_PY4
 
- TEGRA_PIN_PWR_I2C_SDA_PZ7
 
- TEGRA_PIN_PWR_INT_N
 
- TEGRA_PIN_PZ0
 
- TEGRA_PIN_PZ1
 
- TEGRA_PIN_PZ2
 
- TEGRA_PIN_PZ3
 
- TEGRA_PIN_PZ4
 
- TEGRA_PIN_PZ5
 
- TEGRA_PIN_QSPI_CS_N_PEE1
 
- TEGRA_PIN_QSPI_IO0_PEE2
 
- TEGRA_PIN_QSPI_IO1_PEE3
 
- TEGRA_PIN_QSPI_IO2_PEE4
 
- TEGRA_PIN_QSPI_IO3_PEE5
 
- TEGRA_PIN_QSPI_SCK_PEE0
 
- TEGRA_PIN_RESET_OUT_N
 
- TEGRA_PIN_SATA_LED_ACTIVE_PA5
 
- TEGRA_PIN_SDIO1_CLK_PZ0
 
- TEGRA_PIN_SDIO1_CMD_PZ1
 
- TEGRA_PIN_SDIO1_DAT0_PY7
 
- TEGRA_PIN_SDIO1_DAT1_PY6
 
- TEGRA_PIN_SDIO1_DAT2_PY5
 
- TEGRA_PIN_SDIO1_DAT3_PY4
 
- TEGRA_PIN_SDIO3_CLK_PA6
 
- TEGRA_PIN_SDIO3_CMD_PA7
 
- TEGRA_PIN_SDIO3_DAT0_PB7
 
- TEGRA_PIN_SDIO3_DAT1_PB6
 
- TEGRA_PIN_SDIO3_DAT2_PB5
 
- TEGRA_PIN_SDIO3_DAT3_PB4
 
- TEGRA_PIN_SDIO3_DAT4_PD1
 
- TEGRA_PIN_SDIO3_DAT5_PD0
 
- TEGRA_PIN_SDIO3_DAT6_PD3
 
- TEGRA_PIN_SDIO3_DAT7_PD4
 
- TEGRA_PIN_SDMMC1_CLK_PM0
 
- TEGRA_PIN_SDMMC1_CLK_PZ0
 
- TEGRA_PIN_SDMMC1_CMD_PM1
 
- TEGRA_PIN_SDMMC1_CMD_PZ1
 
- TEGRA_PIN_SDMMC1_DAT0_PM5
 
- TEGRA_PIN_SDMMC1_DAT0_PY7
 
- TEGRA_PIN_SDMMC1_DAT1_PM4
 
- TEGRA_PIN_SDMMC1_DAT1_PY6
 
- TEGRA_PIN_SDMMC1_DAT2_PM3
 
- TEGRA_PIN_SDMMC1_DAT2_PY5
 
- TEGRA_PIN_SDMMC1_DAT3_PM2
 
- TEGRA_PIN_SDMMC1_DAT3_PY4
 
- TEGRA_PIN_SDMMC1_WP_N_PV3
 
- TEGRA_PIN_SDMMC3_CD_N_PV2
 
- TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5
 
- TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4
 
- TEGRA_PIN_SDMMC3_CLK_PA6
 
- TEGRA_PIN_SDMMC3_CLK_PP0
 
- TEGRA_PIN_SDMMC3_CMD_PA7
 
- TEGRA_PIN_SDMMC3_CMD_PP1
 
- TEGRA_PIN_SDMMC3_DAT0_PB7
 
- TEGRA_PIN_SDMMC3_DAT0_PP5
 
- TEGRA_PIN_SDMMC3_DAT1_PB6
 
- TEGRA_PIN_SDMMC3_DAT1_PP4
 
- TEGRA_PIN_SDMMC3_DAT2_PB5
 
- TEGRA_PIN_SDMMC3_DAT2_PP3
 
- TEGRA_PIN_SDMMC3_DAT3_PB4
 
- TEGRA_PIN_SDMMC3_DAT3_PP2
 
- TEGRA_PIN_SDMMC3_DAT4_PD1
 
- TEGRA_PIN_SDMMC3_DAT5_PD0
 
- TEGRA_PIN_SDMMC3_DAT6_PD3
 
- TEGRA_PIN_SDMMC3_DAT7_PD4
 
- TEGRA_PIN_SDMMC4_CLK_PCC4
 
- TEGRA_PIN_SDMMC4_CMD_PT7
 
- TEGRA_PIN_SDMMC4_DAT0_PAA0
 
- TEGRA_PIN_SDMMC4_DAT1_PAA1
 
- TEGRA_PIN_SDMMC4_DAT2_PAA2
 
- TEGRA_PIN_SDMMC4_DAT3_PAA3
 
- TEGRA_PIN_SDMMC4_DAT4_PAA4
 
- TEGRA_PIN_SDMMC4_DAT5_PAA5
 
- TEGRA_PIN_SDMMC4_DAT6_PAA6
 
- TEGRA_PIN_SDMMC4_DAT7_PAA7
 
- TEGRA_PIN_SDMMC4_RST_N_PCC3
 
- TEGRA_PIN_SHUTDOWN
 
- TEGRA_PIN_SLEW_RATE_FAST
 
- TEGRA_PIN_SLEW_RATE_FASTEST
 
- TEGRA_PIN_SLEW_RATE_SLOW
 
- TEGRA_PIN_SLEW_RATE_SLOWEST
 
- TEGRA_PIN_SPDIF_IN_PCC3
 
- TEGRA_PIN_SPDIF_IN_PK6
 
- TEGRA_PIN_SPDIF_OUT_PCC2
 
- TEGRA_PIN_SPDIF_OUT_PK5
 
- TEGRA_PIN_SPI1_CS0_N_PX6
 
- TEGRA_PIN_SPI1_CS0_PC3
 
- TEGRA_PIN_SPI1_CS1_PC4
 
- TEGRA_PIN_SPI1_MISO_PC1
 
- TEGRA_PIN_SPI1_MISO_PX7
 
- TEGRA_PIN_SPI1_MOSI_PC0
 
- TEGRA_PIN_SPI1_MOSI_PX4
 
- TEGRA_PIN_SPI1_SCK_PC2
 
- TEGRA_PIN_SPI1_SCK_PX5
 
- TEGRA_PIN_SPI2_CS0_N_PX3
 
- TEGRA_PIN_SPI2_CS0_PB7
 
- TEGRA_PIN_SPI2_CS1_N_PW2
 
- TEGRA_PIN_SPI2_CS1_PDD0
 
- TEGRA_PIN_SPI2_CS2_N_PW3
 
- TEGRA_PIN_SPI2_MISO_PB5
 
- TEGRA_PIN_SPI2_MISO_PX1
 
- TEGRA_PIN_SPI2_MOSI_PB4
 
- TEGRA_PIN_SPI2_MOSI_PX0
 
- TEGRA_PIN_SPI2_SCK_PB6
 
- TEGRA_PIN_SPI2_SCK_PX2
 
- TEGRA_PIN_SPI4_CS0_PC6
 
- TEGRA_PIN_SPI4_MISO_PD0
 
- TEGRA_PIN_SPI4_MOSI_PC7
 
- TEGRA_PIN_SPI4_SCK_PC5
 
- TEGRA_PIN_SYS_CLK_REQ_PZ5
 
- TEGRA_PIN_SYS_RESET
 
- TEGRA_PIN_SYS_RESET_N
 
- TEGRA_PIN_TEMP_ALERT_PX4
 
- TEGRA_PIN_TEST_MODE_EN
 
- TEGRA_PIN_TOUCH_CLK_PV7
 
- TEGRA_PIN_TOUCH_INT_PX1
 
- TEGRA_PIN_TOUCH_RST_PV6
 
- TEGRA_PIN_UART1_CTS_PU3
 
- TEGRA_PIN_UART1_RTS_PU2
 
- TEGRA_PIN_UART1_RX_PU1
 
- TEGRA_PIN_UART1_TX_PU0
 
- TEGRA_PIN_UART2_CTS_N_PJ5
 
- TEGRA_PIN_UART2_CTS_PG3
 
- TEGRA_PIN_UART2_RTS_N_PJ6
 
- TEGRA_PIN_UART2_RTS_PG2
 
- TEGRA_PIN_UART2_RXD_PC3
 
- TEGRA_PIN_UART2_RX_PG1
 
- TEGRA_PIN_UART2_TXD_PC2
 
- TEGRA_PIN_UART2_TX_PG0
 
- TEGRA_PIN_UART3_CTS_N_PA1
 
- TEGRA_PIN_UART3_CTS_PD4
 
- TEGRA_PIN_UART3_RTS_N_PC0
 
- TEGRA_PIN_UART3_RTS_PD3
 
- TEGRA_PIN_UART3_RXD_PW7
 
- TEGRA_PIN_UART3_RX_PD2
 
- TEGRA_PIN_UART3_TXD_PW6
 
- TEGRA_PIN_UART3_TX_PD1
 
- TEGRA_PIN_UART4_CTS_PI7
 
- TEGRA_PIN_UART4_RTS_PI6
 
- TEGRA_PIN_UART4_RX_PI5
 
- TEGRA_PIN_UART4_TX_PI4
 
- TEGRA_PIN_ULPI_CLK_PY0
 
- TEGRA_PIN_ULPI_DATA0_PO1
 
- TEGRA_PIN_ULPI_DATA1_PO2
 
- TEGRA_PIN_ULPI_DATA2_PO3
 
- TEGRA_PIN_ULPI_DATA3_PO4
 
- TEGRA_PIN_ULPI_DATA4_PO5
 
- TEGRA_PIN_ULPI_DATA5_PO6
 
- TEGRA_PIN_ULPI_DATA6_PO7
 
- TEGRA_PIN_ULPI_DATA7_PO0
 
- TEGRA_PIN_ULPI_DIR_PY1
 
- TEGRA_PIN_ULPI_NXT_PY2
 
- TEGRA_PIN_ULPI_STP_PY3
 
- TEGRA_PIN_USB_VBUS_EN0_PCC4
 
- TEGRA_PIN_USB_VBUS_EN0_PN4
 
- TEGRA_PIN_USB_VBUS_EN1_PCC5
 
- TEGRA_PIN_USB_VBUS_EN1_PN5
 
- TEGRA_PIN_USB_VBUS_EN2_PFF1
 
- TEGRA_PIN_VI_D0_PT4
 
- TEGRA_PIN_VI_D10_PT2
 
- TEGRA_PIN_VI_D11_PT3
 
- TEGRA_PIN_VI_D1_PD5
 
- TEGRA_PIN_VI_D2_PL0
 
- TEGRA_PIN_VI_D3_PL1
 
- TEGRA_PIN_VI_D4_PL2
 
- TEGRA_PIN_VI_D5_PL3
 
- TEGRA_PIN_VI_D6_PL4
 
- TEGRA_PIN_VI_D7_PL5
 
- TEGRA_PIN_VI_D8_PL6
 
- TEGRA_PIN_VI_D9_PL7
 
- TEGRA_PIN_VI_GP0_PBB1
 
- TEGRA_PIN_VI_GP3_PBB4
 
- TEGRA_PIN_VI_GP4_PBB5
 
- TEGRA_PIN_VI_GP5_PD2
 
- TEGRA_PIN_VI_GP6_PA0
 
- TEGRA_PIN_VI_HSYNC_PD7
 
- TEGRA_PIN_VI_MCLK_PT1
 
- TEGRA_PIN_VI_PCLK_PT0
 
- TEGRA_PIN_VI_VSYNC_PD6
 
- TEGRA_PIN_WIFI_EN_PH0
 
- TEGRA_PIN_WIFI_RST_PH1
 
- TEGRA_PIN_WIFI_WAKE_AP_PH2
 
- TEGRA_PLANE_H
 
- TEGRA_PLLE_CONFIGURE
 
- TEGRA_PLLM
 
- TEGRA_PLLMB
 
- TEGRA_PLLU
 
- TEGRA_PLL_BYPASS
 
- TEGRA_PLL_FIXED
 
- TEGRA_PLL_HAS_CPCON
 
- TEGRA_PLL_HAS_LOCK_ENABLE
 
- TEGRA_PLL_LOCK_MISC
 
- TEGRA_PLL_SET_DCCON
 
- TEGRA_PLL_SET_LFCON
 
- TEGRA_PLL_USE_LOCK
 
- TEGRA_PLL_VCO_OUT
 
- TEGRA_PMC_BASE
 
- TEGRA_PMC_SCRATCH20
 
- TEGRA_PMC_SIZE
 
- TEGRA_PMC_VIRT
 
- TEGRA_PORTSC1_RWC_BITS
 
- TEGRA_POWERGATE_3D
 
- TEGRA_POWERGATE_3D0
 
- TEGRA_POWERGATE_3D1
 
- TEGRA_POWERGATE_AUD
 
- TEGRA_POWERGATE_C0NC
 
- TEGRA_POWERGATE_C1NC
 
- TEGRA_POWERGATE_CELP
 
- TEGRA_POWERGATE_CPU
 
- TEGRA_POWERGATE_CPU0
 
- TEGRA_POWERGATE_CPU1
 
- TEGRA_POWERGATE_CPU2
 
- TEGRA_POWERGATE_CPU3
 
- TEGRA_POWERGATE_DFD
 
- TEGRA_POWERGATE_DIS
 
- TEGRA_POWERGATE_DISB
 
- TEGRA_POWERGATE_HEG
 
- TEGRA_POWERGATE_IRAM
 
- TEGRA_POWERGATE_L2
 
- TEGRA_POWERGATE_MAX
 
- TEGRA_POWERGATE_MPE
 
- TEGRA_POWERGATE_NVDEC
 
- TEGRA_POWERGATE_NVJPG
 
- TEGRA_POWERGATE_PCIE
 
- TEGRA_POWERGATE_SATA
 
- TEGRA_POWERGATE_SOR
 
- TEGRA_POWERGATE_VDEC
 
- TEGRA_POWERGATE_VE2
 
- TEGRA_POWERGATE_VENC
 
- TEGRA_POWERGATE_VIC
 
- TEGRA_POWERGATE_XUSBA
 
- TEGRA_POWERGATE_XUSBB
 
- TEGRA_POWERGATE_XUSBC
 
- TEGRA_RESET_DATA_SIZE
 
- TEGRA_RESET_MASK_LP1
 
- TEGRA_RESET_MASK_LP2
 
- TEGRA_RESET_MASK_PRESENT
 
- TEGRA_RESET_RESETTABLE_STATUS
 
- TEGRA_RESET_STARTUP_LP1
 
- TEGRA_RESET_STARTUP_LP2
 
- TEGRA_RESET_STARTUP_SECONDARY
 
- TEGRA_RESET_TF_PRESENT
 
- TEGRA_REVISION_A01
 
- TEGRA_REVISION_A02
 
- TEGRA_REVISION_A03
 
- TEGRA_REVISION_A03p
 
- TEGRA_REVISION_A04
 
- TEGRA_REVISION_MAX
 
- TEGRA_REVISION_UNKNOWN
 
- TEGRA_RTC_INTR_MASK_MSEC_ALARM
 
- TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM
 
- TEGRA_RTC_INTR_MASK_SEC_ALARM0
 
- TEGRA_RTC_INTR_MASK_SEC_ALARM1
 
- TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM
 
- TEGRA_RTC_INTR_STATUS_MSEC_ALARM
 
- TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM
 
- TEGRA_RTC_INTR_STATUS_SEC_ALARM0
 
- TEGRA_RTC_INTR_STATUS_SEC_ALARM1
 
- TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM
 
- TEGRA_RTC_REG_BUSY
 
- TEGRA_RTC_REG_INTR_MASK
 
- TEGRA_RTC_REG_INTR_STATUS
 
- TEGRA_RTC_REG_MILLI_SECONDS
 
- TEGRA_RTC_REG_MILLI_SECONDS_ALARM0
 
- TEGRA_RTC_REG_SECONDS
 
- TEGRA_RTC_REG_SECONDS_ALARM0
 
- TEGRA_RTC_REG_SECONDS_ALARM1
 
- TEGRA_RTC_REG_SHADOW_SECONDS
 
- TEGRA_SB_BASE
 
- TEGRA_SB_SIZE
 
- TEGRA_SMC_PMC
 
- TEGRA_SMC_PMC_READ
 
- TEGRA_SMC_PMC_WRITE
 
- TEGRA_SOCTHERM_THROT_LEVEL_HIGH
 
- TEGRA_SOCTHERM_THROT_LEVEL_LOW
 
- TEGRA_SOCTHERM_THROT_LEVEL_MED
 
- TEGRA_SOCTHERM_THROT_LEVEL_NONE
 
- TEGRA_SOC_OC_IRQ_1
 
- TEGRA_SOC_OC_IRQ_2
 
- TEGRA_SOC_OC_IRQ_3
 
- TEGRA_SOC_OC_IRQ_4
 
- TEGRA_SOC_OC_IRQ_5
 
- TEGRA_SOC_OC_IRQ_MAX
 
- TEGRA_SUSPEND_LP0
 
- TEGRA_SUSPEND_LP1
 
- TEGRA_SUSPEND_LP2
 
- TEGRA_SUSPEND_NONE
 
- TEGRA_SWGROUP_A9AVP
 
- TEGRA_SWGROUP_AFI
 
- TEGRA_SWGROUP_APE
 
- TEGRA_SWGROUP_AVPC
 
- TEGRA_SWGROUP_AXIAP
 
- TEGRA_SWGROUP_DC
 
- TEGRA_SWGROUP_DCB
 
- TEGRA_SWGROUP_EMUCIF
 
- TEGRA_SWGROUP_EPP
 
- TEGRA_SWGROUP_ETR
 
- TEGRA_SWGROUP_G2
 
- TEGRA_SWGROUP_GPU
 
- TEGRA_SWGROUP_HC
 
- TEGRA_SWGROUP_HDA
 
- TEGRA_SWGROUP_ISP
 
- TEGRA_SWGROUP_ISP2
 
- TEGRA_SWGROUP_ISP2B
 
- TEGRA_SWGROUP_MPCORE
 
- TEGRA_SWGROUP_MPCORELP
 
- TEGRA_SWGROUP_MPE
 
- TEGRA_SWGROUP_MSENC
 
- TEGRA_SWGROUP_NV
 
- TEGRA_SWGROUP_NV2
 
- TEGRA_SWGROUP_NVDEC
 
- TEGRA_SWGROUP_NVENC
 
- TEGRA_SWGROUP_NVJPG
 
- TEGRA_SWGROUP_PPCS
 
- TEGRA_SWGROUP_PTC
 
- TEGRA_SWGROUP_SATA
 
- TEGRA_SWGROUP_SDMMC1A
 
- TEGRA_SWGROUP_SDMMC2A
 
- TEGRA_SWGROUP_SDMMC3A
 
- TEGRA_SWGROUP_SDMMC4A
 
- TEGRA_SWGROUP_SE
 
- TEGRA_SWGROUP_TSEC
 
- TEGRA_SWGROUP_TSECB
 
- TEGRA_SWGROUP_VDE
 
- TEGRA_SWGROUP_VI
 
- TEGRA_SWGROUP_VIC
 
- TEGRA_SWGROUP_XUSB_DEV
 
- TEGRA_SWGROUP_XUSB_HOST
 
- TEGRA_TMR1_BASE
 
- TEGRA_TMR1_SIZE
 
- TEGRA_TMR2_BASE
 
- TEGRA_TMR2_SIZE
 
- TEGRA_TMR3_BASE
 
- TEGRA_TMR3_SIZE
 
- TEGRA_TMR4_BASE
 
- TEGRA_TMR4_SIZE
 
- TEGRA_TMRUS_BASE
 
- TEGRA_TMRUS_SIZE
 
- TEGRA_TX_DMA
 
- TEGRA_TX_PIO
 
- TEGRA_UARTA_BASE
 
- TEGRA_UARTA_SIZE
 
- TEGRA_UARTB_BASE
 
- TEGRA_UARTB_SIZE
 
- TEGRA_UARTC_BASE
 
- TEGRA_UARTC_SIZE
 
- TEGRA_UARTD_BASE
 
- TEGRA_UARTD_SIZE
 
- TEGRA_UARTE_BASE
 
- TEGRA_UARTE_SIZE
 
- TEGRA_UART_DEFAULT_BAUD
 
- TEGRA_UART_DEFAULT_LSR
 
- TEGRA_UART_FCR_IIR_FIFO_EN
 
- TEGRA_UART_FIFO_SIZE
 
- TEGRA_UART_IER_EORD
 
- TEGRA_UART_IRDA_CSR
 
- TEGRA_UART_LSR_ANY
 
- TEGRA_UART_LSR_TXFIFO_FULL
 
- TEGRA_UART_MAXIMUM
 
- TEGRA_UART_MCR_CTS_EN
 
- TEGRA_UART_MCR_RTS_EN
 
- TEGRA_UART_MIN_DMA
 
- TEGRA_UART_RX_DMA_BUFFER_SIZE
 
- TEGRA_UART_SIR_ENABLED
 
- TEGRA_UART_TX_DMA
 
- TEGRA_UART_TX_PIO
 
- TEGRA_UART_TX_TRIG_16B
 
- TEGRA_UART_TX_TRIG_1B
 
- TEGRA_UART_TX_TRIG_4B
 
- TEGRA_UART_TX_TRIG_8B
 
- TEGRA_UART_TYPE
 
- TEGRA_USB_DMA_ALIGN
 
- TEGRA_USB_HOSTPC1_DEVLC
 
- TEGRA_USB_HOSTPC1_DEVLC_PHCD
 
- TEGRA_USB_HOSTPC1_DEVLC_PTS
 
- TEGRA_USB_PHY_PORT_SPEED_FULL
 
- TEGRA_USB_PHY_PORT_SPEED_HIGH
 
- TEGRA_USB_PHY_PORT_SPEED_LOW
 
- TEGRA_USB_PORTSC1
 
- TEGRA_USB_PORTSC1_PHCD
 
- TEGRA_USB_PORTSC1_PTS
 
- TEGRA_VDE_DECODE_H264
 
- TEGRA_VDE_H
 
- TEGRA_VDE_IOCTL_DECODE_H264
 
- TEGRA_VDE_TRACE_H
 
- TEGRA_VIC_H
 
- TEGRA_WAKE_GPIO
 
- TEGRA_WAKE_IRQ
 
- TEGRA_XHCI_SS_HIGH_SPEED
 
- TEGRA_XHCI_SS_LOW_SPEED
 
- TEGRA_XUSB_PADCTL_IDDQ
 
- TEGRA_XUSB_PADCTL_PACK
 
- TEGRA_XUSB_PADCTL_PCIE
 
- TEGRA_XUSB_PADCTL_SATA
 
- TEGRA_XUSB_PADCTL_UNPACK_PARAM
 
- TEGRA_XUSB_PADCTL_UNPACK_VALUE
 
- TEHA5
 
- TEHB5
 
- TEIFree
 
- TEIInit
 
- TEI_ENTITY_ID
 
- TEI_EVENT_COUNT
 
- TEI_SAPI
 
- TEI_STATE_COUNT
 
- TEIrelease
 
- TEKRAM_24C16_NVRAM_ADDRESS
 
- TEKRAM_93C46_NVRAM_ADDRESS
 
- TEKRAM_ACTIVE_NEGATION
 
- TEKRAM_DISCONNECT_ENABLE
 
- TEKRAM_DRIVES_SUP_1GB
 
- TEKRAM_F2_F6_ENABLED
 
- TEKRAM_IMMEDIATE_SEEK
 
- TEKRAM_MORE_THAN_2_DRIVES
 
- TEKRAM_NVRAM_SIZE
 
- TEKRAM_PARITY_CHECK
 
- TEKRAM_REMOVABLE_FLAGS
 
- TEKRAM_RESET_ON_POWER_ON
 
- TEKRAM_SCAN_LUNS
 
- TEKRAM_START_CMD
 
- TEKRAM_SYNC_NEGO
 
- TEKRAM_TAGGED_COMMANDS
 
- TEKRAM_WIDE_NEGO
 
- TELEMETRY_DEVICE_NAME
 
- TELEMETRY_RESOURCE_PMC_SSRAM
 
- TELEMETRY_RESOURCE_PUNIT_SSRAM
 
- TELEM_ACTION_NONE
 
- TELEM_ADD
 
- TELEM_APL_D0IX_ID
 
- TELEM_APL_D3_ID
 
- TELEM_APL_MASK_PCS_STATE
 
- TELEM_APL_PCS_IDLE_BLOCKED_ID
 
- TELEM_APL_PCS_S0IX_BLOCKED_ID
 
- TELEM_APL_PG_ID
 
- TELEM_APL_PSS_IDLE_ID
 
- TELEM_APL_PSS_LTR_BLOCKING_ID
 
- TELEM_APL_PSS_PSTATES_ID
 
- TELEM_APL_PSS_WAKEUP_ID
 
- TELEM_APL_S0IX_DEEP_OCC_ID
 
- TELEM_APL_S0IX_DEEP_RES_ID
 
- TELEM_APL_S0IX_SHLW_OCC_ID
 
- TELEM_APL_S0IX_SHLW_RES_ID
 
- TELEM_APL_S0IX_TOTAL_OCC_ID
 
- TELEM_APL_S0IX_TOTAL_RES_ID
 
- TELEM_ARGS_SIZE_MAX
 
- TELEM_CHECK_AND_PARSE_CTRS
 
- TELEM_CHECK_AND_PARSE_EVTS
 
- TELEM_CLASS_NAME
 
- TELEM_CLEAR_EVENTS
 
- TELEM_CLEAR_SAMPLE_PERIOD
 
- TELEM_CLEAR_VERBOSITY_BITS
 
- TELEM_CPU
 
- TELEM_DEV_NAME
 
- TELEM_DEV_NAME_FMT
 
- TELEM_DISABLE
 
- TELEM_ENABLE_PERIODIC
 
- TELEM_ENABLE_SRAM_EVT_TRACE
 
- TELEM_EVENT_ENABLE
 
- TELEM_EXTRACT_VERBOSITY
 
- TELEM_INFO_NENABLES_MASK
 
- TELEM_INFO_SRAMEVTS_MASK
 
- TELEM_INFO_SRAMEVTS_SHIFT
 
- TELEM_IOSS
 
- TELEM_IOSS_DX_D0IX_EVTS
 
- TELEM_IOSS_PG_EVTS
 
- TELEM_MASK_BIT
 
- TELEM_MASK_BYTE
 
- TELEM_MASK_PCS_STATE
 
- TELEM_MAX_DEV
 
- TELEM_MAX_EVENTS_SRAM
 
- TELEM_MAX_OS_ALLOCATED_EVENTS
 
- TELEM_MAX_PERIOD
 
- TELEM_MIN_PERIOD
 
- TELEM_PMC_SSRAM_OFFSET
 
- TELEM_PSS
 
- TELEM_PSS_IDLE_BLOCKED_EVTS
 
- TELEM_PSS_IDLE_EVTS
 
- TELEM_PSS_LTR_BLOCKING_EVTS
 
- TELEM_PSS_S0IX_BLOCKED_EVTS
 
- TELEM_PSS_S0IX_WAKEUP_EVTS
 
- TELEM_PUNIT_SSRAM_OFFSET
 
- TELEM_RESET
 
- TELEM_RESPONSE_SIZE
 
- TELEM_SAMPLE_PERIOD_INVALID
 
- TELEM_SAMPLING_DEFAULT_PERIOD
 
- TELEM_SET_VERBOSITY_BITS
 
- TELEM_SSRAM_EVTLOG_OFFSET
 
- TELEM_SSRAM_READ_TIMEOUT
 
- TELEM_SSRAM_SIZE
 
- TELEM_SSRAM_STARTTIME_OFFSET
 
- TELEM_TRC_VERBOSITY_MASK
 
- TELEM_UNIT_NONE
 
- TELEM_UPDATE
 
- TELIT_PRODUCT_CC864_DUAL
 
- TELIT_PRODUCT_CC864_SINGLE
 
- TELIT_PRODUCT_DE910_DUAL
 
- TELIT_PRODUCT_LE910
 
- TELIT_PRODUCT_LE910_USBCFG4
 
- TELIT_PRODUCT_LE920
 
- TELIT_PRODUCT_LE920A4_1207
 
- TELIT_PRODUCT_LE920A4_1208
 
- TELIT_PRODUCT_LE920A4_1211
 
- TELIT_PRODUCT_LE920A4_1212
 
- TELIT_PRODUCT_LE920A4_1213
 
- TELIT_PRODUCT_LE920A4_1214
 
- TELIT_PRODUCT_LE922_USBCFG0
 
- TELIT_PRODUCT_LE922_USBCFG1
 
- TELIT_PRODUCT_LE922_USBCFG2
 
- TELIT_PRODUCT_LE922_USBCFG3
 
- TELIT_PRODUCT_LE922_USBCFG5
 
- TELIT_PRODUCT_ME910
 
- TELIT_PRODUCT_ME910_DUAL_MODEM
 
- TELIT_PRODUCT_UC864E
 
- TELIT_PRODUCT_UC864G
 
- TELIT_PRODUCT_UE910_V2
 
- TELIT_VENDOR_ID
 
- TELLDUS_TELLSTICK_PID
 
- TELLDUS_VID
 
- TELNETD_IRQ
 
- TEM
 
- TEMAC_FEATURE_RX_CSUM
 
- TEMAC_FEATURE_TX_CSUM
 
- TEMIC_IRDA
 
- TEMIC_SET_PAL_BG
 
- TEMIC_SET_PAL_DK
 
- TEMIC_SET_PAL_I
 
- TEMIC_SET_PAL_L
 
- TEMIC_SET_PAL_L2
 
- TEMODEO
 
- TEMODER_IP_CHECKSUM_GENERATE
 
- TEMODER_NUM_OF_QUEUES_SHIFT
 
- TEMODER_PERFORMANCE_OPTIMIZATION_MODE1
 
- TEMODER_RMON_STATISTICS
 
- TEMODER_SCHEDULER_ENABLE
 
- TEMODER_TX_RMON_STATISTICS_ENABLE
 
- TEMP
 
- TEMP115C
 
- TEMP11U_TO_REG
 
- TEMP11_FROM_REG
 
- TEMP11_REG_NUM
 
- TEMP11_TO_REG
 
- TEMP1_FROM_REG
 
- TEMP1_TO_REG
 
- TEMP23_FROM_REG
 
- TEMP23_TO_REG
 
- TEMP8U_TO_REG
 
- TEMP8_FROM_REG
 
- TEMP8_REG_NUM
 
- TEMP8_TO_REG
 
- TEMPENV
 
- TEMPENV_MASK
 
- TEMPERATURE
 
- TEMPERATURE_C
 
- TEMPERATURE_CALIB_A_VAL
 
- TEMPERATURE_CALIB_KELVIN_OFFSET
 
- TEMPERATURE_MEASURE_NOW
 
- TEMPERATURE_NOTIFICATION
 
- TEMPERATURE_OFFSET
 
- TEMPERATURE_READ_ADDR__CSR_ADDR_MASK
 
- TEMPERATURE_READ_ADDR__CSR_ADDR__SHIFT
 
- TEMPERATURE_READ_ADDR__RESERVED_MASK
 
- TEMPERATURE_READ_ADDR__RESERVED__SHIFT
 
- TEMPERATURE_READ_ADDR__TCEN_ID_MASK
 
- TEMPERATURE_READ_ADDR__TCEN_ID__SHIFT
 
- TEMPERATURE_SHOW_TEMP_AND_LABEL
 
- TEMPERATURE_USE_OLD_VALUE
 
- TEMPEXT_FROM_REG
 
- TEMPL
 
- TEMPLATE
 
- TEMPLATE_NULLS_VAL
 
- TEMPLATE_SHOW
 
- TEMPLATE_STORE
 
- TEMPLATE_TYPE_FWDUMP
 
- TEMPMON_BASE
 
- TEMPMON_CONTROL
 
- TEMPMON_CONTROL_AUTOSCAN
 
- TEMPMON_CONTROL_INTENABLE
 
- TEMPMON_CONTROL_OVERTEMP
 
- TEMPMON_FANCONTROL
 
- TEMPMON_IMX6Q
 
- TEMPMON_IMX6SX
 
- TEMPMON_IMX7D
 
- TEMPMON_SENSOR0
 
- TEMPMON_SENSOR1
 
- TEMPNAME_TEMPLATE
 
- TEMPSENSE
 
- TEMPSENSOR_GATE
 
- TEMPSI_CFG
 
- TEMPSI_CMD
 
- TEMPSI_RES
 
- TEMP_ADCEN
 
- TEMP_ADCENADDR
 
- TEMP_ADCMUX
 
- TEMP_ADCMUXADDR
 
- TEMP_ADCPNP0
 
- TEMP_ADCPNP0_1
 
- TEMP_ADCPNP1
 
- TEMP_ADCPNP1_1
 
- TEMP_ADCPNP2
 
- TEMP_ADCPNP2_1
 
- TEMP_ADCPNP3
 
- TEMP_ADCPNP3_1
 
- TEMP_ADCVALIDADDR
 
- TEMP_ADCVALIDMASK
 
- TEMP_ADCVALIDMASK_VALID_HIGH
 
- TEMP_ADCVALIDMASK_VALID_POS
 
- TEMP_ADCVOLTADDR
 
- TEMP_ADCVOLTAGESHIFT
 
- TEMP_ADCWRITECTRL
 
- TEMP_ADCWRITECTRL_ADC_MUX_WRITE
 
- TEMP_ADCWRITECTRL_ADC_PNP_WRITE
 
- TEMP_ADD_FROM_REG
 
- TEMP_ADD_TO_REG_HIGH
 
- TEMP_ADD_TO_REG_LOW
 
- TEMP_AHBPOLL
 
- TEMP_AHBPOLL_ADC_POLL_INTERVAL
 
- TEMP_AHBTO
 
- TEMP_ALARM_BASE
 
- TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS
 
- TEMP_ALM_CRIT
 
- TEMP_CAL
 
- TEMP_CH1_CH_REG
 
- TEMP_CH1_C_REG
 
- TEMP_CH1_HV_REG
 
- TEMP_CH1_WH_REG
 
- TEMP_CH1_W_REG
 
- TEMP_CLAMP
 
- TEMP_COLLECTION_TIME
 
- TEMP_COUNT
 
- TEMP_CPU
 
- TEMP_CPU_DTS
 
- TEMP_CPU_LOCAL
 
- TEMP_CRIT
 
- TEMP_CRIT_HYST
 
- TEMP_CRUISE
 
- TEMP_DATA
 
- TEMP_DATA_PENDING
 
- TEMP_EDGE
 
- TEMP_ENABLE
 
- TEMP_EXT
 
- TEMP_FAN_MAP
 
- TEMP_FAULT
 
- TEMP_FRAC_OFFSET
 
- TEMP_FROM_REG
 
- TEMP_FROM_REG10
 
- TEMP_FROM_REG_EXT
 
- TEMP_HOTDIE_MSK
 
- TEMP_HOTSPOT
 
- TEMP_HYST_FROM_REG
 
- TEMP_HYST_TO_REG
 
- TEMP_IDX_LEN
 
- TEMP_INT
 
- TEMP_IRAM_AREA
 
- TEMP_IRQ_EN
 
- TEMP_KELVIN_TO_CELSIUS
 
- TEMP_LIMIT0_DEFAULT
 
- TEMP_LIMIT1_DEFAULT
 
- TEMP_LIMIT2_DEFAULT
 
- TEMP_LIMIT_TO_REG
 
- TEMP_LIQUID0
 
- TEMP_LIQUID1
 
- TEMP_MAPPING_VADDR
 
- TEMP_MAX
 
- TEMP_MAXMIN_FROM_REG
 
- TEMP_MAXMIN_TO_REG
 
- TEMP_MAX_REG
 
- TEMP_MEM
 
- TEMP_MIN
 
- TEMP_MINOR
 
- TEMP_MIN_REG
 
- TEMP_MONCTL0
 
- TEMP_MONCTL1
 
- TEMP_MONCTL1_PERIOD_UNIT
 
- TEMP_MONCTL2
 
- TEMP_MONCTL2_FILTER_INTERVAL
 
- TEMP_MONCTL2_SENSOR_INTERVAL
 
- TEMP_MONIDET0
 
- TEMP_MONIDET1
 
- TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT
 
- TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE
 
- TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE
 
- TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE
 
- TEMP_MSR0
 
- TEMP_MSR0_1
 
- TEMP_MSR1
 
- TEMP_MSR1_1
 
- TEMP_MSR2
 
- TEMP_MSR2_1
 
- TEMP_MSR3
 
- TEMP_MSR3_1
 
- TEMP_MSRCTL0
 
- TEMP_NEGATIVE_BIT
 
- TEMP_NORTHBRIDGE
 
- TEMP_OFFSET_FROM_REG
 
- TEMP_OFFSET_REG
 
- TEMP_OFFSET_TO_REG
 
- TEMP_OTS_OE
 
- TEMP_PERIOD
 
- TEMP_PLX
 
- TEMP_PNPMUXADDR
 
- TEMP_PREFERRED_LIFETIME
 
- TEMP_PSR_R
 
- TEMP_PWM_CTFS
 
- TEMP_PWM_ENABLE
 
- TEMP_PWM_FAN_MAP
 
- TEMP_PWM_HCT
 
- TEMP_PWM_HOT
 
- TEMP_PWM_TTTI
 
- TEMP_PWR
 
- TEMP_RANGE_FROM_REG
 
- TEMP_RANGE_MAX
 
- TEMP_RANGE_MAXSTEPS
 
- TEMP_RANGE_MIN
 
- TEMP_RANGE_TO_REG
 
- TEMP_RDCTRL
 
- TEMP_READ
 
- TEMP_REG
 
- TEMP_REPORTING_THRESHOLDS_CMD
 
- TEMP_RW1C_MASK
 
- TEMP_SEL
 
- TEMP_SEL_MASK
 
- TEMP_SEL_SHIFT
 
- TEMP_SENSOR
 
- TEMP_SENSOR_TYPE
 
- TEMP_SKIN
 
- TEMP_SPARE0
 
- TEMP_STAGE_HYSTERESIS
 
- TEMP_STAGE_STEP
 
- TEMP_STATUS_CHANEN
 
- TEMP_STATUS_CRITFLG
 
- TEMP_STATUS_HIGHFLG
 
- TEMP_STATUS_HOT
 
- TEMP_STATUS_LOWFLG
 
- TEMP_STATUS_OK
 
- TEMP_STATUS_SENSERR
 
- TEMP_STEP_SIZE
 
- TEMP_THERM_REG
 
- TEMP_THRESH_MIN
 
- TEMP_THRESH_STEP
 
- TEMP_TMIN_REG
 
- TEMP_TOLERANCE
 
- TEMP_TO_REG
 
- TEMP_TRANGE_REG
 
- TEMP_TYPE_LOCAL_DIODE
 
- TEMP_TYPE_MASK
 
- TEMP_TYPE_REMOTE_DIODE
 
- TEMP_TYPE_THERMISTOR
 
- TEMP_TYPE_e
 
- TEMP_UNIT_ATTRS
 
- TEMP_VALID_LIFETIME
 
- TEMP_VGA
 
- TEMP_VR_GFX
 
- TEMP_VR_MEM
 
- TEMP_VR_MEM0
 
- TEMP_VR_MEM1
 
- TEMP_VR_SOC
 
- TEMP_WARN
 
- TEMP_WARN_HYST
 
- TEMP_e
 
- TENBASET_ON
 
- TENBTCSR_ECHO_DISABLE
 
- TEND
 
- TEND0_MARK
 
- TEND0_PD_MARK
 
- TEND0_PE_MARK
 
- TEND1_MARK
 
- TEND1_PD_MARK
 
- TEND1_PE_MARK
 
- TENTS_PER_PAGE
 
- TENXPRESS_REQUIRED_DEVS
 
- TEN_BIT_ADDR_DEFAULT
 
- TEN_BIT_ADDR_MASK
 
- TEN_GIG_MAC_EVENT
 
- TEN_THREAD
 
- TEN_UPDATE_EN
 
- TEN_WORD_MSG_SIZE
 
- TEPR
 
- TEP_BIG_ENDIAN
 
- TEP_DISABLE_PLUGINS
 
- TEP_DISABLE_SYS_PLUGINS
 
- TEP_ERRNO__FILTER_MATCH
 
- TEP_ERRNO__SUCCESS
 
- TEP_ERRORS
 
- TEP_EVENT_DELIM
 
- TEP_EVENT_DQUOTE
 
- TEP_EVENT_ERROR
 
- TEP_EVENT_FL_FAILED
 
- TEP_EVENT_FL_ISBPRINT
 
- TEP_EVENT_FL_ISFTRACE
 
- TEP_EVENT_FL_ISFUNCENT
 
- TEP_EVENT_FL_ISFUNCRET
 
- TEP_EVENT_FL_ISPRINT
 
- TEP_EVENT_FL_NOHANDLE
 
- TEP_EVENT_FL_PRINTRAW
 
- TEP_EVENT_ITEM
 
- TEP_EVENT_NEWLINE
 
- TEP_EVENT_NONE
 
- TEP_EVENT_OP
 
- TEP_EVENT_SORT_ID
 
- TEP_EVENT_SORT_NAME
 
- TEP_EVENT_SORT_SYSTEM
 
- TEP_EVENT_SPACE
 
- TEP_EVENT_SQUOTE
 
- TEP_FIELD_IS_ARRAY
 
- TEP_FIELD_IS_DYNAMIC
 
- TEP_FIELD_IS_FLAG
 
- TEP_FIELD_IS_LONG
 
- TEP_FIELD_IS_POINTER
 
- TEP_FIELD_IS_SIGNED
 
- TEP_FIELD_IS_STRING
 
- TEP_FIELD_IS_SYMBOLIC
 
- TEP_FILTER_ARG_BOOLEAN
 
- TEP_FILTER_ARG_EXP
 
- TEP_FILTER_ARG_FIELD
 
- TEP_FILTER_ARG_NONE
 
- TEP_FILTER_ARG_NUM
 
- TEP_FILTER_ARG_OP
 
- TEP_FILTER_ARG_STR
 
- TEP_FILTER_ARG_VALUE
 
- TEP_FILTER_CHAR
 
- TEP_FILTER_CMP_EQ
 
- TEP_FILTER_CMP_GE
 
- TEP_FILTER_CMP_GT
 
- TEP_FILTER_CMP_LE
 
- TEP_FILTER_CMP_LT
 
- TEP_FILTER_CMP_MATCH
 
- TEP_FILTER_CMP_NE
 
- TEP_FILTER_CMP_NONE
 
- TEP_FILTER_CMP_NOT_MATCH
 
- TEP_FILTER_CMP_NOT_REGEX
 
- TEP_FILTER_CMP_REGEX
 
- TEP_FILTER_ERROR_BUFSZ
 
- TEP_FILTER_EXP_ADD
 
- TEP_FILTER_EXP_AND
 
- TEP_FILTER_EXP_DIV
 
- TEP_FILTER_EXP_LSHIFT
 
- TEP_FILTER_EXP_MOD
 
- TEP_FILTER_EXP_MUL
 
- TEP_FILTER_EXP_NONE
 
- TEP_FILTER_EXP_NOT
 
- TEP_FILTER_EXP_OR
 
- TEP_FILTER_EXP_RSHIFT
 
- TEP_FILTER_EXP_SUB
 
- TEP_FILTER_EXP_XOR
 
- TEP_FILTER_FALSE
 
- TEP_FILTER_NUMBER
 
- TEP_FILTER_OP_AND
 
- TEP_FILTER_OP_NOT
 
- TEP_FILTER_OP_OR
 
- TEP_FILTER_STRING
 
- TEP_FILTER_TRUE
 
- TEP_FUNC_ARG_INT
 
- TEP_FUNC_ARG_LONG
 
- TEP_FUNC_ARG_MAX_TYPES
 
- TEP_FUNC_ARG_PTR
 
- TEP_FUNC_ARG_STRING
 
- TEP_FUNC_ARG_VOID
 
- TEP_LITTLE_ENDIAN
 
- TEP_NSEC_OUTPUT
 
- TEP_PLUGIN_ALIAS
 
- TEP_PLUGIN_ALIAS_NAME
 
- TEP_PLUGIN_LOADER
 
- TEP_PLUGIN_LOADER_NAME
 
- TEP_PLUGIN_OPTIONS
 
- TEP_PLUGIN_OPTIONS_NAME
 
- TEP_PLUGIN_UNLOADER
 
- TEP_PLUGIN_UNLOADER_NAME
 
- TEP_PRINT_ATOM
 
- TEP_PRINT_BITMASK
 
- TEP_PRINT_BSTRING
 
- TEP_PRINT_COMM
 
- TEP_PRINT_CPU
 
- TEP_PRINT_DYNAMIC_ARRAY
 
- TEP_PRINT_DYNAMIC_ARRAY_LEN
 
- TEP_PRINT_FIELD
 
- TEP_PRINT_FLAGS
 
- TEP_PRINT_FUNC
 
- TEP_PRINT_HEX
 
- TEP_PRINT_HEX_STR
 
- TEP_PRINT_INFO
 
- TEP_PRINT_INFO_RAW
 
- TEP_PRINT_INT_ARRAY
 
- TEP_PRINT_LATENCY
 
- TEP_PRINT_NAME
 
- TEP_PRINT_NULL
 
- TEP_PRINT_OP
 
- TEP_PRINT_PID
 
- TEP_PRINT_STRING
 
- TEP_PRINT_SYMBOL
 
- TEP_PRINT_TIME
 
- TEP_PRINT_TYPE
 
- TEP_REGISTER_SUCCESS
 
- TEP_REGISTER_SUCCESS_OVERWRITE
 
- TER
 
- TER16x32_IDX
 
- TERA_NUM_CAPTURE
 
- TERA_NUM_PLAYBACK
 
- TEREDO_RS_EVENT_MASK
 
- TEREDO_SEL
 
- TEREDO_WAKE_MASK
 
- TERMINATE_SEQ
 
- TERMINATION_RESISTER_CONTROL
 
- TERMINATION_SELECT
 
- TERMINATOR_SIZE
 
- TERMIOS_FLUSH
 
- TERMIOS_OLD
 
- TERMIOS_TERMIO
 
- TERMIOS_WAIT
 
- TERMPWRCTRL
 
- TERM_BIO
 
- TERM_CTL
 
- TERM_CTL_H
 
- TERM_CTL_L
 
- TERM_CTL_SEL
 
- TERM_DDP_LEN_TAGGED
 
- TERM_DDP_LEN_UNTAGGED
 
- TERM_EN_SW
 
- TERM_ERROR_LAYER_DDP
 
- TERM_ERROR_LAYER_LLP
 
- TERM_ERROR_LAYER_RDMAP
 
- TERM_EVENT_QP_ACCESS_ERR
 
- TERM_EVENT_QP_FATAL
 
- TERM_FLAG_D
 
- TERM_FLAG_M
 
- TERM_FLAG_R
 
- TERM_LVD
 
- TERM_LVD_HI
 
- TERM_LVD_LO
 
- TERM_MASK_ECODE
 
- TERM_MASK_ETYPE
 
- TERM_MASK_LAYER
 
- TERM_MASK_RESVD
 
- TERM_MAX_LENGTH
 
- TERM_POL
 
- TERM_PWR_CONTROL
 
- TERM_RANGE_ADJ
 
- TERM_RDMA_LEN
 
- TERM_SE
 
- TERM_SEL
 
- TERM_SE_HI
 
- TERM_SE_LO
 
- TERM_SIZE
 
- TERM_T1A
 
- TERM_T1B
 
- TERM_T2
 
- TERRATEC
 
- TERRATEC_AF9005
 
- TERRATEC_CINERGY_S
 
- TERRATEC_CINERGY_S2
 
- TERRATEC_CINERGY_S2_BOX
 
- TERRATEC_CINERGY_S2_R2
 
- TERRATEC_CINERGY_S2_R3
 
- TERRATEC_CINERGY_S2_R4
 
- TERR_INTERNAL_LOOPFILTER_AVAILABLE
 
- TERTIARY_MI2S_RX
 
- TERTIARY_MI2S_TX
 
- TERTIARY_TDM_RX_0
 
- TERTIARY_TDM_RX_1
 
- TERTIARY_TDM_RX_2
 
- TERTIARY_TDM_RX_3
 
- TERTIARY_TDM_RX_4
 
- TERTIARY_TDM_RX_5
 
- TERTIARY_TDM_RX_6
 
- TERTIARY_TDM_RX_7
 
- TERTIARY_TDM_TX_0
 
- TERTIARY_TDM_TX_1
 
- TERTIARY_TDM_TX_2
 
- TERTIARY_TDM_TX_3
 
- TERTIARY_TDM_TX_4
 
- TERTIARY_TDM_TX_5
 
- TERTIARY_TDM_TX_6
 
- TERTIARY_TDM_TX_7
 
- TER_CAL_DONE
 
- TER_RESISTORS_ON
 
- TER_RESISTOR_HIGH
 
- TER_RESISTOR_LOW
 
- TESR
 
- TESS_BUSY_CYCLES
 
- TESS_ISOLINE
 
- TESS_NUM_CYCLES_CONNGEN_WORKING
 
- TESS_NUM_CYCLES_PTGEN_WORKING
 
- TESS_NUM_CYCLES_SETUP_WORKING
 
- TESS_QUAD
 
- TESS_STALL_CYCLES_PC
 
- TESS_STARVE_CYCLES_PC
 
- TESS_TRIANGLE
 
- TESS_WORKING_CYCLES
 
- TEST
 
- TEST1
 
- TEST1_AHIZEN
 
- TEST1_LOOPS
 
- TEST1_VERSION_SZ
 
- TEST2
 
- TEST2_LOOPS
 
- TEST2_VERSION_SZ
 
- TEST3_VERSION_SZ
 
- TEST6_VERSION_SZ
 
- TEST7_VERSION_SZ
 
- TESTBUSCR
 
- TESTBUS_CTRL
 
- TESTBUS_CTRL_CH1
 
- TESTBUS_CTRL_CH2
 
- TESTBUS_CTRL_CH3
 
- TESTCASE_END
 
- TESTCASE_START
 
- TESTCFG_HBDIS
 
- TESTCLEARFLAG
 
- TESTCLEARFLAG_FALSE
 
- TESTCLK_SRC_PCLK
 
- TESTCLK_SRC_PLL
 
- TESTCLK_SRC_SCLK
 
- TESTCLK_SRC_XTAL
 
- TESTCSR
 
- TESTFRAMESIZE
 
- TESTFWCMDNUMBER
 
- TESTHI
 
- TESTI_ADR_MASK
 
- TESTI_DAT_MASK
 
- TESTI_WR_EN
 
- TESTLO
 
- TESTLOOPCOUNT
 
- TESTMGR_POISON_BYTE
 
- TESTMGR_POISON_LEN
 
- TESTMODE
 
- TESTMODE_FORCE
 
- TESTO_1_PID
 
- TESTO_3_PID
 
- TESTO_VID
 
- TESTPAGEFLAG
 
- TESTPAGEFLAG_FALSE
 
- TESTPORT
 
- TESTS
 
- TESTSCFLAG
 
- TESTSCFLAG_FALSE
 
- TESTSETFLAG
 
- TESTSETFLAG_FALSE
 
- TESTS_H
 
- TESTVAL
 
- TESTVEC_CONFIG_NAMELEN
 
- TESTVLAN
 
- TEST_AC
 
- TEST_ACCESS_OK
 
- TEST_ACTIVE
 
- TEST_ADD
 
- TEST_ADDC
 
- TEST_ADDC_DOT
 
- TEST_ADD_DOT
 
- TEST_AGE
 
- TEST_AGT_CTRL
 
- TEST_ALIGN_END
 
- TEST_ALLOC_BLOCK_GROUP
 
- TEST_ALLOC_EXTENT_BUFFER
 
- TEST_ALLOC_EXTENT_MAP
 
- TEST_ALLOC_FS_INFO
 
- TEST_ALLOC_INODE
 
- TEST_ALLOC_PATH
 
- TEST_ALLOC_ROOT
 
- TEST_ALPHA
 
- TEST_ANON
 
- TEST_AREA_MAX_SIZE
 
- TEST_ARGS
 
- TEST_ARG_END
 
- TEST_ARG_MEM
 
- TEST_ARG_PTR
 
- TEST_ARG_REG
 
- TEST_ARG_REG_MASKED
 
- TEST_ARM_TO_THUMB_INTERWORK_P
 
- TEST_ARM_TO_THUMB_INTERWORK_R
 
- TEST_ASSERT
 
- TEST_ASSERT_EQUAL
 
- TEST_ASSERT_VAL
 
- TEST_BASIC
 
- TEST_BATTERY
 
- TEST_BB
 
- TEST_BB_R
 
- TEST_BB_X
 
- TEST_BF
 
- TEST_BF_P
 
- TEST_BF_R
 
- TEST_BF_RR
 
- TEST_BF_RX
 
- TEST_BF_X
 
- TEST_BIT
 
- TEST_BIT_DEPTH_10
 
- TEST_BIT_DEPTH_12
 
- TEST_BIT_DEPTH_16
 
- TEST_BIT_DEPTH_6
 
- TEST_BIT_DEPTH_8
 
- TEST_BRANCH_B
 
- TEST_BRANCH_BX
 
- TEST_BRANCH_F
 
- TEST_BRANCH_FX
 
- TEST_BUFFER_SIZE
 
- TEST_BUSY
 
- TEST_BUS_CTL1
 
- TEST_BUS_CTL2
 
- TEST_BUS_EN
 
- TEST_BUS_SEL
 
- TEST_BUS_SUB_SEL_MASK
 
- TEST_C2HINT_WAIT_TIME
 
- TEST_CASES
 
- TEST_CASE_FAILED
 
- TEST_CASE_PASSED
 
- TEST_CGROUP
 
- TEST_CHIP
 
- TEST_CLK_DIV_SEL
 
- TEST_CLK_SEL
 
- TEST_CLK_SEL_0
 
- TEST_CLK_SEL_1
 
- TEST_CLK_SEL_2
 
- TEST_CLK_SEL_3
 
- TEST_CLK_SEL_4
 
- TEST_CLK_SEL_5
 
- TEST_CLK_SEL_6
 
- TEST_CLK_SEL_7
 
- TEST_CLK_SEL_8
 
- TEST_CLK_STABLE_TIME
 
- TEST_CLOCK_MUX_SELECT_DISPCLK_G
 
- TEST_CLOCK_MUX_SELECT_DISPCLK_P
 
- TEST_CLOCK_MUX_SELECT_DISPCLK_R
 
- TEST_CLOCK_MUX_SELECT_DSCCLK_G
 
- TEST_CLOCK_MUX_SELECT_DSCCLK_P
 
- TEST_CLOCK_MUX_SELECT_DSCCLK_R
 
- TEST_CLOCK_MUX_SELECT_ENUM
 
- TEST_CMD_INI_FILE_GENERAL_PARAM
 
- TEST_CMD_INI_FILE_RADIO_PARAM
 
- TEST_CMD_INI_FILE_RF_EXTENDED_PARAM
 
- TEST_CMD_P2G_CAL
 
- TEST_CNTR_EN
 
- TEST_CODE_READING_NO_ACCESS
 
- TEST_CODE_READING_NO_KCORE
 
- TEST_CODE_READING_NO_KERNEL_OBJ
 
- TEST_CODE_READING_NO_VMLINUX
 
- TEST_CODE_READING_OK
 
- TEST_COLOR_FORMAT_RGB
 
- TEST_COLOR_FORMAT_YCBCR422
 
- TEST_COLOR_FORMAT_YCBCR444
 
- TEST_CONTROL
 
- TEST_CONTTX
 
- TEST_COPROCESSOR
 
- TEST_COR
 
- TEST_CORE
 
- TEST_COUNT
 
- TEST_CPUS
 
- TEST_CTL_REG
 
- TEST_CTRL
 
- TEST_CTRL1
 
- TEST_CTRL2
 
- TEST_DATA_LEN
 
- TEST_DATA_REQ_MAX_MSG_LEN_V01
 
- TEST_DATA_REQ_MSG_ID_V01
 
- TEST_DEVICES
 
- TEST_DURATION
 
- TEST_DYN_RANGE_CEA
 
- TEST_DYN_RANGE_VESA
 
- TEST_EEP
 
- TEST_ERROR
 
- TEST_EVENTS
 
- TEST_EXCEL_MASK
 
- TEST_F
 
- TEST_FAIL
 
- TEST_FAILED
 
- TEST_FALG___
 
- TEST_FETCH
 
- TEST_FHI
 
- TEST_FIELD
 
- TEST_FIELD_OFFSET
 
- TEST_FILE_SIZE
 
- TEST_FIM
 
- TEST_FIRMWARE_BUF_SIZE
 
- TEST_FIRMWARE_NAME
 
- TEST_FIRMWARE_NUM_REQS
 
- TEST_FIRST
 
- TEST_FLAG
 
- TEST_FLAGS
 
- TEST_FLAG_FULL_ITBLOCK
 
- TEST_FLAG_NARROW_INSTR
 
- TEST_FLAG_NO_ITBLOCK
 
- TEST_FLAG_VALUE
 
- TEST_FORCE_EN
 
- TEST_FORCE_ENABLE
 
- TEST_FRAME_LEN
 
- TEST_FREEZER
 
- TEST_FTM
 
- TEST_FW_DEV_ATTR
 
- TEST_F_SIGNAL
 
- TEST_F_TIMEOUT
 
- TEST_GENERIC
 
- TEST_GROUP
 
- TEST_GRP_0
 
- TEST_GRP_1
 
- TEST_H2CINT_WAIT_TIME
 
- TEST_HARNESS_MAIN
 
- TEST_HEX
 
- TEST_HEXDUMP_BUF_SIZE
 
- TEST_HITS
 
- TEST_HOST_LOOP_INTERVAL
 
- TEST_HOST_LOOP_N
 
- TEST_HSIZE_SET
 
- TEST_HS_HOST_PORT_SUSPEND_RESUME
 
- TEST_HUGETLB
 
- TEST_IDLE
 
- TEST_INITIATOR
 
- TEST_INSERT_FAIL
 
- TEST_INSTRUCTION
 
- TEST_IO
 
- TEST_IO_OFF
 
- TEST_IRQ
 
- TEST_ISA
 
- TEST_IT
 
- TEST_ITBLOCK
 
- TEST_J
 
- TEST_J_MODE
 
- TEST_J_PID
 
- TEST_K
 
- TEST_KMOD_DEV_ATTR
 
- TEST_KMOD_DRIVER
 
- TEST_KMOD_FS_TYPE
 
- TEST_K_MODE
 
- TEST_K_PID
 
- TEST_LB
 
- TEST_LBACK
 
- TEST_LBCK
 
- TEST_LBEXT
 
- TEST_LBINT
 
- TEST_LBNONE
 
- TEST_LD
 
- TEST_LDARX
 
- TEST_LEN
 
- TEST_LFDX
 
- TEST_LFSX
 
- TEST_LINK
 
- TEST_LIST_LEN
 
- TEST_LOGIC_SEG_NUM
 
- TEST_LOOP
 
- TEST_LVX
 
- TEST_LWZ
 
- TEST_LWZX
 
- TEST_LXVD2X
 
- TEST_MAP_TYPE
 
- TEST_MAX
 
- TEST_MAX_NAME_SIZE_V01
 
- TEST_MED_DATA_SIZE_V01
 
- TEST_MEMORY_SIZE
 
- TEST_MEM_SIZE
 
- TEST_MEM_SLOT_INDEX
 
- TEST_MODE
 
- TEST_MODE_CLIENT
 
- TEST_MODE_CSR
 
- TEST_MODE_DISABLE
 
- TEST_MODE_ENABLE_BIT
 
- TEST_MODE_SELECT
 
- TEST_MODE_SERVER
 
- TEST_MODE_SHIFT
 
- TEST_MODE_UNSET
 
- TEST_MTX_CTX
 
- TEST_MTX_SPIN
 
- TEST_MTX_TRY
 
- TEST_NAME
 
- TEST_NAVDIS
 
- TEST_NOACK
 
- TEST_NOCTS
 
- TEST_NONE
 
- TEST_N_BIT_OP
 
- TEST_OK
 
- TEST_ONE_SHIFT
 
- TEST_OPCODE
 
- TEST_OPTION
 
- TEST_OTHERS
 
- TEST_OUTPUTS
 
- TEST_P
 
- TEST_PACKET
 
- TEST_PACKET_MODE
 
- TEST_PACKET_PID
 
- TEST_PAGES_PER_LOOP
 
- TEST_PARMAN_BASE_COUNT
 
- TEST_PARMAN_BASE_SHIFT
 
- TEST_PARMAN_BULK_MAX_COUNT
 
- TEST_PARMAN_BULK_MAX_MASK
 
- TEST_PARMAN_BULK_MAX_SHIFT
 
- TEST_PARMAN_ITEM_COUNT
 
- TEST_PARMAN_ITEM_MASK
 
- TEST_PARMAN_ITEM_SHIFT
 
- TEST_PARMAN_PRIO_COUNT
 
- TEST_PARMAN_PRIO_MASK
 
- TEST_PARMAN_PRIO_SHIFT
 
- TEST_PARMAN_RESIZE_STEP_COUNT
 
- TEST_PARMAN_RESIZE_STEP_SHIFT
 
- TEST_PARMAN_RUN_BUDGET
 
- TEST_PASS
 
- TEST_PATTERN
 
- TEST_PATTERN_ALL_000H
 
- TEST_PATTERN_ALL_555H
 
- TEST_PATTERN_ALL_AAAH
 
- TEST_PATTERN_ALL_FFFH
 
- TEST_PATTERN_BLACK_BAR_EN
 
- TEST_PATTERN_COLOR_FORMAT_BPC_10
 
- TEST_PATTERN_COLOR_FORMAT_BPC_12
 
- TEST_PATTERN_COLOR_FORMAT_BPC_6
 
- TEST_PATTERN_COLOR_FORMAT_BPC_8
 
- TEST_PATTERN_DISABLED
 
- TEST_PATTERN_DYN_RANGE_CEA
 
- TEST_PATTERN_DYN_RANGE_VESA
 
- TEST_PATTERN_ENABLE
 
- TEST_PATTERN_H_COLOR_BARS
 
- TEST_PATTERN_MODE_COLORSQUARES_RGB
 
- TEST_PATTERN_MODE_COLORSQUARES_YCBCR601
 
- TEST_PATTERN_MODE_COLORSQUARES_YCBCR709
 
- TEST_PATTERN_MODE_DUALRAMP_RGB
 
- TEST_PATTERN_MODE_HORIZONTALBARS
 
- TEST_PATTERN_MODE_SINGLERAMP_RGB
 
- TEST_PATTERN_MODE_VERTICALBARS
 
- TEST_PATTERN_MODE_XR_BIAS_RGB
 
- TEST_PATTERN_VSP_05H
 
- TEST_PATTERN_VSP_0FH
 
- TEST_PATTERN_VSP_50H
 
- TEST_PATTERN_VSP_5AH
 
- TEST_PATTERN_VSP_A5H
 
- TEST_PATTERN_VSP_F0H
 
- TEST_PATTERN_V_COLOR_BARS
 
- TEST_PATTTERN_0
 
- TEST_PATTTERN_1
 
- TEST_PING_REQ_MAX_MSG_LEN_V01
 
- TEST_PING_REQ_MSG_ID_V01
 
- TEST_PIN_DIR_CTRL
 
- TEST_PLATFORM
 
- TEST_POISON1
 
- TEST_POISON2
 
- TEST_POPPC
 
- TEST_POWER_NUM
 
- TEST_PR
 
- TEST_PREFIX
 
- TEST_PRIORITY
 
- TEST_PROBE_DELAY
 
- TEST_PROBE_THRESHOLD
 
- TEST_PRR
 
- TEST_R
 
- TEST_REG
 
- TEST_REGS_ADDR
 
- TEST_REGS_CNT
 
- TEST_RESET
 
- TEST_RETURN
 
- TEST_RMASKED
 
- TEST_RP
 
- TEST_RPR
 
- TEST_RR
 
- TEST_RRP
 
- TEST_RRR
 
- TEST_RRRR
 
- TEST_RRX
 
- TEST_RX
 
- TEST_SCANCODES
 
- TEST_SE0_NAK
 
- TEST_SE0_NAK_MODE
 
- TEST_SE0_NAK_PID
 
- TEST_SEED_MASK
 
- TEST_SEED_SELECT
 
- TEST_SELF
 
- TEST_SET_BITS_SLEEP_MAX
 
- TEST_SET_BITS_SLEEP_MIN
 
- TEST_SET_BITS_TIMEOUT
 
- TEST_SG_TOTAL
 
- TEST_SHMEM
 
- TEST_SICODE_PRIV
 
- TEST_SICODE_SHARE
 
- TEST_SIGNAL
 
- TEST_SILENT
 
- TEST_SINGLE_STEP_GET_DEV_DESC
 
- TEST_SINGLE_STEP_SET_FEATURE
 
- TEST_SIZE
 
- TEST_SKIP
 
- TEST_SOFTINT
 
- TEST_SPEED_RETURN
 
- TEST_START_DRIVER
 
- TEST_START_NUM_THREADS
 
- TEST_START_TEST_CASE
 
- TEST_START_TEST_FS
 
- TEST_STATUS
 
- TEST_STD
 
- TEST_STDCX
 
- TEST_STEP01
 
- TEST_STEP02
 
- TEST_STEP03
 
- TEST_STEP04
 
- TEST_STEP_FAILURE
 
- TEST_STFDX
 
- TEST_STFSX
 
- TEST_STRING
 
- TEST_STRING_2_DICT_0
 
- TEST_STRING_2_DICT_1
 
- TEST_STRING_2_MAX_S1
 
- TEST_STVX
 
- TEST_STXVD2X
 
- TEST_SUPPORTED
 
- TEST_SUSPEND_SECONDS
 
- TEST_SYNC_FIELDS
 
- TEST_SZ
 
- TEST_TARGET
 
- TEST_THUMB_TO_ARM_INTERWORK_P
 
- TEST_TIMEOUT_DEFAULT
 
- TEST_TIME_MASK
 
- TEST_TOTLEN
 
- TEST_TRISTATE
 
- TEST_TX1
 
- TEST_TX2
 
- TEST_TXCTRL
 
- TEST_TXCTRL_HDMI_MODE
 
- TEST_TXPE
 
- TEST_TYPE_MASK
 
- TEST_U64
 
- TEST_UNIT_READY
 
- TEST_UNSUPPORTED
 
- TEST_USB
 
- TEST_X
 
- TEST_echo
 
- TEST_isa_int
 
- TEST_mask
 
- TEST_null
 
- TEST_off
 
- TEST_peek
 
- TEST_poke
 
- TEST_seg
 
- TEST_sub_code
 
- TESTcmd
 
- TESTflag
 
- TESTload
 
- TESTvalue
 
- TEVII_S421
 
- TEVII_S480_1
 
- TEVII_S480_2
 
- TEVII_S482_1
 
- TEVII_S482_2
 
- TEVII_S630
 
- TEVII_S632
 
- TEVII_S650
 
- TEVII_S660
 
- TEVII_S662
 
- TEWS_PCI_DEVICE_ID_TMPC810
 
- TEWS_PCI_VENDOR_ID
 
- TEXASR_ABORT
 
- TEXASR_ABT
 
- TEXASR_AB_LG
 
- TEXASR_DA
 
- TEXASR_EXACT
 
- TEXASR_EX_LG
 
- TEXASR_FC
 
- TEXASR_FC_LG
 
- TEXASR_FO
 
- TEXASR_FP
 
- TEXASR_FS
 
- TEXASR_FS_LG
 
- TEXASR_HV
 
- TEXASR_HV_LG
 
- TEXASR_IC
 
- TEXASR_IFC
 
- TEXASR_NO
 
- TEXASR_NTC
 
- TEXASR_PR
 
- TEXASR_PR_LG
 
- TEXASR_ROT
 
- TEXASR_ROT_LG
 
- TEXASR_SIC
 
- TEXASR_SPD
 
- TEXASR_SUSP
 
- TEXASR_SU_LG
 
- TEXASR_TC
 
- TEXASR_TE
 
- TEXASR_TIC
 
- TEXT
 
- TEXTBOX_HEIGTH_MIN
 
- TEXTBOX_WIDTH_MIN
 
- TEXTSTART
 
- TEXTS_FOR_ZONES
 
- TEXT_ALIGN
 
- TEXT_BLT
 
- TEXT_END
 
- TEXT_FOR_DMA
 
- TEXT_FOR_DMA32
 
- TEXT_FOR_HIGHMEM
 
- TEXT_IMM_BLT
 
- TEXT_LEAF_ATTR
 
- TEXT_LEN
 
- TEXT_MAIN
 
- TEXT_SECTIONS
 
- TEXT_SIZE
 
- TEXT_TEXT
 
- TEXT_TO_ANY_EXIT
 
- TEXT_TO_ANY_INIT
 
- TEXT_TYPE_16_BIT
 
- TEXT_TYPE_8_BIT
 
- TEX_0_OFF
 
- TEX_10_OFF
 
- TEX_1_OFF
 
- TEX_2_OFF
 
- TEX_3_OFF
 
- TEX_4_OFF
 
- TEX_5_OFF
 
- TEX_6_OFF
 
- TEX_7_OFF
 
- TEX_8_OFF
 
- TEX_9_OFF
 
- TEX_ARRAY_MODE
 
- TEX_BANK_HEIGHT
 
- TEX_BANK_WIDTH
 
- TEX_BC_SWIZZLE
 
- TEX_BC_Swizzle_WXYZ
 
- TEX_BC_Swizzle_WZYX
 
- TEX_BC_Swizzle_XWYZ
 
- TEX_BC_Swizzle_XYZW
 
- TEX_BC_Swizzle_YXWZ
 
- TEX_BC_Swizzle_ZYXW
 
- TEX_BORDER_COLOR_TYPE
 
- TEX_BorderColor_OpaqueBlack
 
- TEX_BorderColor_OpaqueWhite
 
- TEX_BorderColor_Register
 
- TEX_BorderColor_TransparentBlack
 
- TEX_CHROMA_KEY
 
- TEX_CLAMP
 
- TEX_CNTL
 
- TEX_COORD_TYPE
 
- TEX_ChromaKey_Blend
 
- TEX_ChromaKey_Disabled
 
- TEX_ChromaKey_Kill
 
- TEX_ChromaKey_RESERVED_3
 
- TEX_Clamp_ClampHalfToBorder
 
- TEX_Clamp_ClampToBorder
 
- TEX_Clamp_ClampToLast
 
- TEX_Clamp_Mirror
 
- TEX_Clamp_MirrorOnceHalfToBorder
 
- TEX_Clamp_MirrorOnceToBorder
 
- TEX_Clamp_MirrorOnceToLast
 
- TEX_Clamp_Repeat
 
- TEX_CoordType_Normalized
 
- TEX_CoordType_Unnormalized
 
- TEX_DEPTH_COMPARE_FUNCTION
 
- TEX_DIM
 
- TEX_DST_SEL_W
 
- TEX_DST_SEL_X
 
- TEX_DST_SEL_Y
 
- TEX_DST_SEL_Z
 
- TEX_DepthCompareFunction_Always
 
- TEX_DepthCompareFunction_Equal
 
- TEX_DepthCompareFunction_Greater
 
- TEX_DepthCompareFunction_GreaterEqual
 
- TEX_DepthCompareFunction_Less
 
- TEX_DepthCompareFunction_LessEqual
 
- TEX_DepthCompareFunction_Never
 
- TEX_DepthCompareFunction_NotEqual
 
- TEX_Dim_1D
 
- TEX_Dim_1DArray
 
- TEX_Dim_2D
 
- TEX_Dim_2DArray
 
- TEX_Dim_2DArray_MSAA
 
- TEX_Dim_2D_MSAA
 
- TEX_Dim_3D
 
- TEX_Dim_CubeMap
 
- TEX_FORMAT_COMP
 
- TEX_FormatComp_RESERVED_3
 
- TEX_FormatComp_Signed
 
- TEX_FormatComp_Unsigned
 
- TEX_FormatComp_UnsignedBiased
 
- TEX_MAX_ANISO_RATIO
 
- TEX_MIP_FILTER
 
- TEX_MaxAnisoRatio_16to1
 
- TEX_MaxAnisoRatio_1to1
 
- TEX_MaxAnisoRatio_2to1
 
- TEX_MaxAnisoRatio_4to1
 
- TEX_MaxAnisoRatio_8to1
 
- TEX_MaxAnisoRatio_RESERVED_5
 
- TEX_MaxAnisoRatio_RESERVED_6
 
- TEX_MaxAnisoRatio_RESERVED_7
 
- TEX_MipFilter_Linear
 
- TEX_MipFilter_None
 
- TEX_MipFilter_Point
 
- TEX_MipFilter_Point_Aniso_Adj
 
- TEX_MipFilter_RESERVED_3
 
- TEX_NUM_BANKS
 
- TEX_PALETTE
 
- TEX_PALETTE_INDEX
 
- TEX_REQUEST_SIZE
 
- TEX_RequestSize_128B
 
- TEX_RequestSize_2X64B
 
- TEX_RequestSize_32B
 
- TEX_RequestSize_64B
 
- TEX_SAMPLER_TYPE
 
- TEX_SIZE_PITCH
 
- TEX_SamplerType_Invalid
 
- TEX_SamplerType_Valid
 
- TEX_TILE_SPLIT
 
- TEX_XYFilter_AnisoLinear
 
- TEX_XYFilter_AnisoPoint
 
- TEX_XYFilter_Linear
 
- TEX_XYFilter_Point
 
- TEX_XY_FILTER
 
- TEX_ZFilter_Linear
 
- TEX_ZFilter_None
 
- TEX_ZFilter_Point
 
- TEX_ZFilter_RESERVED_3
 
- TEX_Z_FILTER
 
- TE_BSS_EAP_DHCP_PROT
 
- TE_BSS_QUIET_PERIOD
 
- TE_BSS_STA_AGGRESSIVE_ASSOC
 
- TE_BSS_STA_ASSOC
 
- TE_CHANNEL_SWITCH_PERIOD
 
- TE_FREERUN
 
- TE_HW_POLLING_EN
 
- TE_LINE_INTERVAL
 
- TE_MAX
 
- TE_MIPI_POLLING_EN
 
- TE_P2P_CLIENT_AGGRESSIVE_ASSOC
 
- TE_P2P_CLIENT_ASSOC
 
- TE_P2P_CLIENT_QUIET_PERIOD
 
- TE_P2P_DEVICE_ACTION_SCAN
 
- TE_P2P_DEVICE_DISCOVERABLE
 
- TE_P2P_DEVICE_FULL_SCAN
 
- TE_P2P_DEVICE_LISTEN
 
- TE_P2P_GO_ASSOC_PROT
 
- TE_P2P_GO_CT_WINDOW
 
- TE_P2P_GO_REPETITIVET_NOA
 
- TE_RCVD
 
- TE_RDY_INT_FLAG
 
- TE_REQ
 
- TE_TIMEOUT
 
- TE_TRIGGER_DSI_PROTOCOL
 
- TE_TRIGGER_GPIO_PIN
 
- TE_V1_DEP_OTHER
 
- TE_V1_DEP_TSF
 
- TE_V1_EVENT_SOCIOPATHIC
 
- TE_V1_FRAG_DUAL
 
- TE_V1_FRAG_ENDLESS
 
- TE_V1_FRAG_MAX_MSK
 
- TE_V1_FRAG_NONE
 
- TE_V1_FRAG_SINGLE
 
- TE_V1_INDEPENDENT
 
- TE_V1_NOTIF_HOST_EVENT_END
 
- TE_V1_NOTIF_HOST_EVENT_START
 
- TE_V1_NOTIF_HOST_FRAG_END
 
- TE_V1_NOTIF_HOST_FRAG_START
 
- TE_V1_NOTIF_INTERNAL_EVENT_END
 
- TE_V1_NOTIF_INTERNAL_EVENT_START
 
- TE_V1_NOTIF_INTERNAL_FRAG_END
 
- TE_V1_NOTIF_INTERNAL_FRAG_START
 
- TE_V1_NOTIF_NONE
 
- TE_V1_REPEAT_ENDLESS
 
- TE_V1_REPEAT_MAX_MSK_V1
 
- TE_V2_ABSENCE
 
- TE_V2_ABSENCE_POS
 
- TE_V2_DEFAULT_POLICY
 
- TE_V2_DEP_OTHER
 
- TE_V2_DEP_TSF
 
- TE_V2_EVENT_SOCIOPATHIC
 
- TE_V2_FRAG_DUAL
 
- TE_V2_FRAG_ENDLESS
 
- TE_V2_FRAG_MAX
 
- TE_V2_FRAG_NONE
 
- TE_V2_FRAG_SINGLE
 
- TE_V2_NOTIF_HOST_EVENT_END
 
- TE_V2_NOTIF_HOST_EVENT_START
 
- TE_V2_NOTIF_HOST_FRAG_END
 
- TE_V2_NOTIF_HOST_FRAG_START
 
- TE_V2_NOTIF_INTERNAL_EVENT_END
 
- TE_V2_NOTIF_INTERNAL_EVENT_START
 
- TE_V2_NOTIF_INTERNAL_FRAG_END
 
- TE_V2_NOTIF_INTERNAL_FRAG_START
 
- TE_V2_PLACEMENT_POS
 
- TE_V2_REPEAT_ENDLESS
 
- TE_V2_REPEAT_MAX
 
- TE_V2_START_IMMEDIATELY
 
- TE_WIDI_TX_SYNC
 
- TF
 
- TF2_SF
 
- TFA0
 
- TFA1
 
- TFA2
 
- TFA2_BIT
 
- TFA2_TST
 
- TFA2_TSV
 
- TFA9879_AMP_MASK
 
- TFA9879_AMP_SHIFT
 
- TFA9879_AT_LVL_MASK
 
- TFA9879_AT_LVL_SHIFT
 
- TFA9879_AT_RATE_MASK
 
- TFA9879_AT_RATE_SHIFT
 
- TFA9879_A_LAW_MASK
 
- TFA9879_A_LAW_SHIFT
 
- TFA9879_BASS_TREBLE
 
- TFA9879_BYPASS_CONTROL
 
- TFA9879_CLIPCTRL_MASK
 
- TFA9879_CLIPCTRL_SHIFT
 
- TFA9879_D1_SLOT_MASK
 
- TFA9879_D1_SLOT_SHIFT
 
- TFA9879_D2_SLOT_MASK
 
- TFA9879_D2_SLOT_SHIFT
 
- TFA9879_DEVICE_CONTROL
 
- TFA9879_DE_PHAS_MASK
 
- TFA9879_DE_PHAS_SHIFT
 
- TFA9879_DRC_BP_MASK
 
- TFA9879_DRC_BP_SHIFT
 
- TFA9879_DYNAMIC_RANGE_COMPR
 
- TFA9879_EQUALIZER_A1
 
- TFA9879_EQUALIZER_A2
 
- TFA9879_EQUALIZER_B1
 
- TFA9879_EQUALIZER_B2
 
- TFA9879_EQUALIZER_C1
 
- TFA9879_EQUALIZER_C2
 
- TFA9879_EQUALIZER_D1
 
- TFA9879_EQUALIZER_D2
 
- TFA9879_EQUALIZER_E1
 
- TFA9879_EQUALIZER_E2
 
- TFA9879_EQ_BP_MASK
 
- TFA9879_EQ_BP_SHIFT
 
- TFA9879_FORMATS
 
- TFA9879_F_BASS_MASK
 
- TFA9879_F_BASS_SHIFT
 
- TFA9879_F_TRBLE_MASK
 
- TFA9879_F_TRBLE_SHIFT
 
- TFA9879_G_BASS_MASK
 
- TFA9879_G_BASS_SHIFT
 
- TFA9879_G_TRBLE_MASK
 
- TFA9879_G_TRBLE_SHIFT
 
- TFA9879_HIGH_PASS_FILTER
 
- TFA9879_HPF_BP_MASK
 
- TFA9879_HPF_BP_SHIFT
 
- TFA9879_HP_CTRL_MASK
 
- TFA9879_HP_CTRL_SHIFT
 
- TFA9879_H_MUTE_MASK
 
- TFA9879_H_MUTE_SHIFT
 
- TFA9879_I2S_FS_11025
 
- TFA9879_I2S_FS_12000
 
- TFA9879_I2S_FS_16000
 
- TFA9879_I2S_FS_22050
 
- TFA9879_I2S_FS_24000
 
- TFA9879_I2S_FS_32000
 
- TFA9879_I2S_FS_44100
 
- TFA9879_I2S_FS_48000
 
- TFA9879_I2S_FS_64000
 
- TFA9879_I2S_FS_8000
 
- TFA9879_I2S_FS_88200
 
- TFA9879_I2S_FS_96000
 
- TFA9879_I2S_FS_MASK
 
- TFA9879_I2S_FS_SHIFT
 
- TFA9879_I2S_SET_I2S_24
 
- TFA9879_I2S_SET_LSB_J_16
 
- TFA9879_I2S_SET_LSB_J_18
 
- TFA9879_I2S_SET_LSB_J_20
 
- TFA9879_I2S_SET_LSB_J_24
 
- TFA9879_I2S_SET_MASK
 
- TFA9879_I2S_SET_MSB_J_24
 
- TFA9879_I2S_SET_SHIFT
 
- TFA9879_IBP_1_MASK
 
- TFA9879_IBP_1_SHIFT
 
- TFA9879_IBP_2_MASK
 
- TFA9879_IBP_2_SHIFT
 
- TFA9879_INPUT_SEL_MASK
 
- TFA9879_INPUT_SEL_SHIFT
 
- TFA9879_I_MODE_I2S
 
- TFA9879_I_MODE_MASK
 
- TFA9879_I_MODE_PCM_IOM2_LONG
 
- TFA9879_I_MODE_PCM_IOM2_SHORT
 
- TFA9879_I_MODE_SHIFT
 
- TFA9879_K0_MASK
 
- TFA9879_K0_SHIFT
 
- TFA9879_K1E_MASK
 
- TFA9879_K1E_SHIFT
 
- TFA9879_K1M_MASK
 
- TFA9879_K1M_SHIFT
 
- TFA9879_K2E_MASK
 
- TFA9879_K2E_SHIFT
 
- TFA9879_K2M_MASK
 
- TFA9879_K2M_SHIFT
 
- TFA9879_L_OCP_MASK
 
- TFA9879_L_OCP_SHIFT
 
- TFA9879_L_OTP_MASK
 
- TFA9879_L_OTP_SHIFT
 
- TFA9879_MISC_CONTROL
 
- TFA9879_MISC_STATUS
 
- TFA9879_MONO_SEL_BOTH
 
- TFA9879_MONO_SEL_LEFT
 
- TFA9879_MONO_SEL_MASK
 
- TFA9879_MONO_SEL_RIGHT
 
- TFA9879_MONO_SEL_SHIFT
 
- TFA9879_OCPOKA_MASK
 
- TFA9879_OCPOKA_SHIFT
 
- TFA9879_OCPOKB_MASK
 
- TFA9879_OCPOKB_SHIFT
 
- TFA9879_OFP_1_MASK
 
- TFA9879_OFP_1_SHIFT
 
- TFA9879_OFP_2_MASK
 
- TFA9879_OFP_2_SHIFT
 
- TFA9879_OPMODE_MASK
 
- TFA9879_OPMODE_SHIFT
 
- TFA9879_OTPOK_MASK
 
- TFA9879_OTPOK_SHIFT
 
- TFA9879_PCM_COMP_MASK
 
- TFA9879_PCM_COMP_SHIFT
 
- TFA9879_PCM_DL_MASK
 
- TFA9879_PCM_DL_SHIFT
 
- TFA9879_PCM_FS_MASK
 
- TFA9879_PCM_FS_SHIFT
 
- TFA9879_PCM_IOM2_FORMAT_1
 
- TFA9879_PCM_IOM2_FORMAT_2
 
- TFA9879_PORA_MASK
 
- TFA9879_PORA_SHIFT
 
- TFA9879_POWERUP_MASK
 
- TFA9879_POWERUP_SHIFT
 
- TFA9879_PS_MASK
 
- TFA9879_PS_SHIFT
 
- TFA9879_P_LIM_MASK
 
- TFA9879_P_LIM_SHIFT
 
- TFA9879_RATES
 
- TFA9879_RESET_MASK
 
- TFA9879_RESET_SHIFT
 
- TFA9879_RL_LVL_MASK
 
- TFA9879_RL_LVL_SHIFT
 
- TFA9879_RL_RATE_MASK
 
- TFA9879_RL_RATE_SHIFT
 
- TFA9879_SCK_POL_INVERSE
 
- TFA9879_SCK_POL_MASK
 
- TFA9879_SCK_POL_NORMAL
 
- TFA9879_SCK_POL_SHIFT
 
- TFA9879_SERIAL_INTERFACE_1
 
- TFA9879_SERIAL_INTERFACE_2
 
- TFA9879_S_MASK
 
- TFA9879_S_MUTE_MASK
 
- TFA9879_S_MUTE_SHIFT
 
- TFA9879_S_SHIFT
 
- TFA9879_T1_MASK
 
- TFA9879_T1_SHIFT
 
- TFA9879_T2_MASK
 
- TFA9879_T2_SHIFT
 
- TFA9879_UFP_1_MASK
 
- TFA9879_UFP_1_SHIFT
 
- TFA9879_UFP_2_MASK
 
- TFA9879_UFP_2_SHIFT
 
- TFA9879_VOLUME_CONTROL
 
- TFA9879_VOL_MASK
 
- TFA9879_VOL_SHIFT
 
- TFA9879_ZR_CRSS_MASK
 
- TFA9879_ZR_CRSS_SHIFT
 
- TFCAPTUREMAX_G
 
- TFCAPTUREMAX_M
 
- TFCAPTUREMAX_S
 
- TFCAPTUREMAX_V
 
- TFCR
 
- TFCS
 
- TFCS_ADDR
 
- TFCS_IDX
 
- TFC_FLAGS
 
- TFC_SESS_DBG
 
- TFC_bits
 
- TFDDone
 
- TFDListPtr0
 
- TFDListPtr1
 
- TFDR
 
- TFD_CLOEXEC
 
- TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH
 
- TFD_CMD_SLOTS
 
- TFD_CREATE_FLAGS
 
- TFD_CTL_COUNT_GET
 
- TFD_CTL_COUNT_SET
 
- TFD_CTL_PAD_GET
 
- TFD_CTL_PAD_SET
 
- TFD_IOC_SET_TICKS
 
- TFD_MAX_PAYLOAD_SIZE
 
- TFD_NEED_IRQ_MASK
 
- TFD_NONBLOCK
 
- TFD_QUEUE_BC_SIZE
 
- TFD_QUEUE_BC_SIZE_GEN3
 
- TFD_QUEUE_CB_SIZE
 
- TFD_QUEUE_SIZE_BC_DUP
 
- TFD_QUEUE_SIZE_MAX
 
- TFD_QUEUE_SIZE_MAX_GEN3
 
- TFD_SETTIME_FLAGS
 
- TFD_SHARED_FCNTL_FLAGS
 
- TFD_SIZE
 
- TFD_TIMER_ABSTIME
 
- TFD_TIMER_CANCEL_ON_SET
 
- TFD_TX_CMD_SLOTS
 
- TFEN_F
 
- TFEN_S
 
- TFEN_V
 
- TFETCH4_16_BYTE
 
- TFETCH4_1_BYTE
 
- TFETCH4_2_BYTE
 
- TFETCH4_4_BYTE
 
- TFETCH4_8_BYTE
 
- TFETCH5_16_BYTE
 
- TFETCH5_1_BYTE
 
- TFETCH5_2_BYTE
 
- TFETCH5_4_BYTE
 
- TFETCH5_8_BYTE
 
- TFETCH6_16_BYTE
 
- TFETCH6_1_BYTE
 
- TFETCH6_2_BYTE
 
- TFETCH6_4_BYTE
 
- TFETCH6_8_BYTE
 
- TFETCH_16_BYTE
 
- TFETCH_1_BYTE
 
- TFETCH_2_BYTE
 
- TFETCH_4_BYTE
 
- TFETCH_8_BYTE
 
- TFETCH_DISABLE
 
- TFE_SHIFT
 
- TFF
 
- TFFEN_SHIFT
 
- TFHCAUSE_HW_ERROR_MAIN_ARRAY
 
- TFHCAUSE_HW_ERROR_PAGESIZE
 
- TFHCAUSE_HW_ERROR_RR
 
- TFHCAUSE_HW_ERROR_VALID
 
- TFHCAUSE_INSTRUCTION_EXCEPTION
 
- TFHCAUSE_NONE
 
- TFHCAUSE_TLB_MISS
 
- TFHCAUSE_TLB_MOD
 
- TFHCAUSE_UNCORRECTIBLE_ERROR
 
- TFHOP_EXCEPTION
 
- TFHOP_NOOP
 
- TFHOP_RESTART
 
- TFHOP_USER_POLLING_MODE
 
- TFHOP_WRITE_ONLY
 
- TFHOP_WRITE_RESTART
 
- TFHSTATE_HW_ERR
 
- TFHSTATE_IDLE
 
- TFHSTATE_INACTIVE
 
- TFHSTATE_MISS_FMM
 
- TFHSTATE_MISS_UPM
 
- TFHSTATE_RESTART_CBR
 
- TFHSTATE_WRITE_TLB
 
- TFHSTATUS_ACTIVE
 
- TFHSTATUS_EXCEPTION
 
- TFHSTATUS_IDLE
 
- TFH_CHUNK_SIZE_128
 
- TFH_CHUNK_SPLIT_MODE
 
- TFH_SRV_DMA_CHNL0_BC
 
- TFH_SRV_DMA_CHNL0_CTRL
 
- TFH_SRV_DMA_CHNL0_DRAM_ADDR
 
- TFH_SRV_DMA_CHNL0_SRAM_ADDR
 
- TFH_SRV_DMA_SNOOP
 
- TFH_SRV_DMA_START
 
- TFH_SRV_DMA_TO_DRIVER
 
- TFH_TFDQ_CBB_TABLE
 
- TFH_TRANSFER_MAX_PENDING_REQ
 
- TFH_TRANSFER_MODE
 
- TFH_TXCMD_UPDATE_CFG
 
- TFIE
 
- TFILE_ERR
 
- TFINVERTMATCH_F
 
- TFINVERTMATCH_S
 
- TFINVERTMATCH_V
 
- TFLENGTH_G
 
- TFLENGTH_M
 
- TFLENGTH_S
 
- TFLENGTH_V
 
- TFMINPKTSIZE_G
 
- TFMINPKTSIZE_M
 
- TFMINPKTSIZE_S
 
- TFMINPKTSIZE_V
 
- TFMT4_10_10_10_2_UINT
 
- TFMT4_10_10_10_2_UNORM
 
- TFMT4_11_11_10_FLOAT
 
- TFMT4_16_16_16_16_FLOAT
 
- TFMT4_16_16_16_16_SINT
 
- TFMT4_16_16_16_16_SNORM
 
- TFMT4_16_16_16_16_UINT
 
- TFMT4_16_16_16_16_UNORM
 
- TFMT4_16_16_FLOAT
 
- TFMT4_16_16_SINT
 
- TFMT4_16_16_SNORM
 
- TFMT4_16_16_UINT
 
- TFMT4_16_16_UNORM
 
- TFMT4_16_FLOAT
 
- TFMT4_16_SINT
 
- TFMT4_16_SNORM
 
- TFMT4_16_UINT
 
- TFMT4_16_UNORM
 
- TFMT4_32_32_32_32_FLOAT
 
- TFMT4_32_32_32_32_SINT
 
- TFMT4_32_32_32_32_UINT
 
- TFMT4_32_32_32_FLOAT
 
- TFMT4_32_32_32_SINT
 
- TFMT4_32_32_32_UINT
 
- TFMT4_32_32_FLOAT
 
- TFMT4_32_32_SINT
 
- TFMT4_32_32_UINT
 
- TFMT4_32_FLOAT
 
- TFMT4_32_SINT
 
- TFMT4_32_UINT
 
- TFMT4_4_4_4_4_UNORM
 
- TFMT4_5_5_5_1_UNORM
 
- TFMT4_5_6_5_UNORM
 
- TFMT4_8_8_8_8_SINT
 
- TFMT4_8_8_8_8_SNORM
 
- TFMT4_8_8_8_8_UINT
 
- TFMT4_8_8_8_8_UNORM
 
- TFMT4_8_8_SINT
 
- TFMT4_8_8_SNORM
 
- TFMT4_8_8_UINT
 
- TFMT4_8_8_UNORM
 
- TFMT4_8_SINT
 
- TFMT4_8_SNORM
 
- TFMT4_8_UINT
 
- TFMT4_8_UNORM
 
- TFMT4_9_9_9_E5_FLOAT
 
- TFMT4_A8_UNORM
 
- TFMT4_ASTC_10x10
 
- TFMT4_ASTC_10x5
 
- TFMT4_ASTC_10x6
 
- TFMT4_ASTC_10x8
 
- TFMT4_ASTC_12x10
 
- TFMT4_ASTC_12x12
 
- TFMT4_ASTC_4x4
 
- TFMT4_ASTC_5x4
 
- TFMT4_ASTC_5x5
 
- TFMT4_ASTC_6x5
 
- TFMT4_ASTC_6x6
 
- TFMT4_ASTC_8x5
 
- TFMT4_ASTC_8x6
 
- TFMT4_ASTC_8x8
 
- TFMT4_ATC_RGB
 
- TFMT4_ATC_RGBA_EXPLICIT
 
- TFMT4_ATC_RGBA_INTERPOLATED
 
- TFMT4_BPTC
 
- TFMT4_BPTC_FLOAT
 
- TFMT4_BPTC_UFLOAT
 
- TFMT4_DXT1
 
- TFMT4_DXT3
 
- TFMT4_DXT5
 
- TFMT4_ETC1
 
- TFMT4_ETC2_R11_SNORM
 
- TFMT4_ETC2_R11_UNORM
 
- TFMT4_ETC2_RG11_SNORM
 
- TFMT4_ETC2_RG11_UNORM
 
- TFMT4_ETC2_RGB8
 
- TFMT4_ETC2_RGB8A1
 
- TFMT4_ETC2_RGBA8
 
- TFMT4_L8_A8_UNORM
 
- TFMT4_RGTC1_SNORM
 
- TFMT4_RGTC1_UNORM
 
- TFMT4_RGTC2_SNORM
 
- TFMT4_RGTC2_UNORM
 
- TFMT4_X8Z24_UNORM
 
- TFMT5_10_10_10_2_UINT
 
- TFMT5_10_10_10_2_UNORM
 
- TFMT5_11_11_10_FLOAT
 
- TFMT5_16_16_16_16_FLOAT
 
- TFMT5_16_16_16_16_SINT
 
- TFMT5_16_16_16_16_SNORM
 
- TFMT5_16_16_16_16_UINT
 
- TFMT5_16_16_16_16_UNORM
 
- TFMT5_16_16_FLOAT
 
- TFMT5_16_16_SINT
 
- TFMT5_16_16_SNORM
 
- TFMT5_16_16_UINT
 
- TFMT5_16_16_UNORM
 
- TFMT5_16_FLOAT
 
- TFMT5_16_SINT
 
- TFMT5_16_SNORM
 
- TFMT5_16_UINT
 
- TFMT5_16_UNORM
 
- TFMT5_32_32_32_32_FLOAT
 
- TFMT5_32_32_32_32_SINT
 
- TFMT5_32_32_32_32_UINT
 
- TFMT5_32_32_32_FLOAT
 
- TFMT5_32_32_32_SINT
 
- TFMT5_32_32_32_UINT
 
- TFMT5_32_32_FLOAT
 
- TFMT5_32_32_SINT
 
- TFMT5_32_32_UINT
 
- TFMT5_32_FLOAT
 
- TFMT5_32_SINT
 
- TFMT5_32_UINT
 
- TFMT5_4_4_4_4_UNORM
 
- TFMT5_5_5_5_1_UNORM
 
- TFMT5_5_6_5_UNORM
 
- TFMT5_8_8_8_8_SINT
 
- TFMT5_8_8_8_8_SNORM
 
- TFMT5_8_8_8_8_UINT
 
- TFMT5_8_8_8_8_UNORM
 
- TFMT5_8_8_8_UNORM
 
- TFMT5_8_8_SINT
 
- TFMT5_8_8_SNORM
 
- TFMT5_8_8_UINT
 
- TFMT5_8_8_UNORM
 
- TFMT5_8_SINT
 
- TFMT5_8_SNORM
 
- TFMT5_8_UINT
 
- TFMT5_8_UNORM
 
- TFMT5_9_9_9_E5_FLOAT
 
- TFMT5_A8_UNORM
 
- TFMT5_ASTC_10x10
 
- TFMT5_ASTC_10x5
 
- TFMT5_ASTC_10x6
 
- TFMT5_ASTC_10x8
 
- TFMT5_ASTC_12x10
 
- TFMT5_ASTC_12x12
 
- TFMT5_ASTC_4x4
 
- TFMT5_ASTC_5x4
 
- TFMT5_ASTC_5x5
 
- TFMT5_ASTC_6x5
 
- TFMT5_ASTC_6x6
 
- TFMT5_ASTC_8x5
 
- TFMT5_ASTC_8x6
 
- TFMT5_ASTC_8x8
 
- TFMT5_BPTC
 
- TFMT5_BPTC_FLOAT
 
- TFMT5_BPTC_UFLOAT
 
- TFMT5_DXT1
 
- TFMT5_DXT3
 
- TFMT5_DXT5
 
- TFMT5_ETC1
 
- TFMT5_ETC2_R11_SNORM
 
- TFMT5_ETC2_R11_UNORM
 
- TFMT5_ETC2_RG11_SNORM
 
- TFMT5_ETC2_RG11_UNORM
 
- TFMT5_ETC2_RGB8
 
- TFMT5_ETC2_RGB8A1
 
- TFMT5_ETC2_RGBA8
 
- TFMT5_L8_A8_UNORM
 
- TFMT5_RGTC1_SNORM
 
- TFMT5_RGTC1_UNORM
 
- TFMT5_RGTC2_SNORM
 
- TFMT5_RGTC2_UNORM
 
- TFMT5_X8Z24_UNORM
 
- TFMT6_10_10_10_2_UINT
 
- TFMT6_10_10_10_2_UNORM
 
- TFMT6_11_11_10_FLOAT
 
- TFMT6_16_16_16_16_FLOAT
 
- TFMT6_16_16_16_16_SINT
 
- TFMT6_16_16_16_16_SNORM
 
- TFMT6_16_16_16_16_UINT
 
- TFMT6_16_16_16_16_UNORM
 
- TFMT6_16_16_FLOAT
 
- TFMT6_16_16_SINT
 
- TFMT6_16_16_SNORM
 
- TFMT6_16_16_UINT
 
- TFMT6_16_16_UNORM
 
- TFMT6_16_FLOAT
 
- TFMT6_16_SINT
 
- TFMT6_16_SNORM
 
- TFMT6_16_UINT
 
- TFMT6_16_UNORM
 
- TFMT6_32_32_32_32_FLOAT
 
- TFMT6_32_32_32_32_SINT
 
- TFMT6_32_32_32_32_UINT
 
- TFMT6_32_32_32_FLOAT
 
- TFMT6_32_32_32_SINT
 
- TFMT6_32_32_32_UINT
 
- TFMT6_32_32_FLOAT
 
- TFMT6_32_32_SINT
 
- TFMT6_32_32_UINT
 
- TFMT6_32_FLOAT
 
- TFMT6_32_SINT
 
- TFMT6_32_UINT
 
- TFMT6_4_4_4_4_UNORM
 
- TFMT6_5_5_5_1_UNORM
 
- TFMT6_5_6_5_UNORM
 
- TFMT6_8_8_8_8_SINT
 
- TFMT6_8_8_8_8_SNORM
 
- TFMT6_8_8_8_8_UINT
 
- TFMT6_8_8_8_8_UNORM
 
- TFMT6_8_8_8_UNORM
 
- TFMT6_8_8_SINT
 
- TFMT6_8_8_SNORM
 
- TFMT6_8_8_UINT
 
- TFMT6_8_8_UNORM
 
- TFMT6_8_SINT
 
- TFMT6_8_SNORM
 
- TFMT6_8_UINT
 
- TFMT6_8_UNORM
 
- TFMT6_9_9_9_E5_FLOAT
 
- TFMT6_A8_UNORM
 
- TFMT6_ASTC_10x10
 
- TFMT6_ASTC_10x5
 
- TFMT6_ASTC_10x6
 
- TFMT6_ASTC_10x8
 
- TFMT6_ASTC_12x10
 
- TFMT6_ASTC_12x12
 
- TFMT6_ASTC_4x4
 
- TFMT6_ASTC_5x4
 
- TFMT6_ASTC_5x5
 
- TFMT6_ASTC_6x5
 
- TFMT6_ASTC_6x6
 
- TFMT6_ASTC_8x5
 
- TFMT6_ASTC_8x6
 
- TFMT6_ASTC_8x8
 
- TFMT6_BPTC
 
- TFMT6_BPTC_FLOAT
 
- TFMT6_BPTC_UFLOAT
 
- TFMT6_DXT1
 
- TFMT6_DXT3
 
- TFMT6_DXT5
 
- TFMT6_ETC1
 
- TFMT6_ETC2_R11_SNORM
 
- TFMT6_ETC2_R11_UNORM
 
- TFMT6_ETC2_RG11_SNORM
 
- TFMT6_ETC2_RG11_UNORM
 
- TFMT6_ETC2_RGB8
 
- TFMT6_ETC2_RGB8A1
 
- TFMT6_ETC2_RGBA8
 
- TFMT6_L8_A8_UNORM
 
- TFMT6_RGTC1_SNORM
 
- TFMT6_RGTC1_UNORM
 
- TFMT6_RGTC2_SNORM
 
- TFMT6_RGTC2_UNORM
 
- TFMT6_X8Z24_UNORM
 
- TFMT_10_10_10_2_UINT
 
- TFMT_10_10_10_2_UNORM
 
- TFMT_11_11_10_FLOAT
 
- TFMT_16_16_16_16_FLOAT
 
- TFMT_16_16_16_16_SINT
 
- TFMT_16_16_16_16_SNORM
 
- TFMT_16_16_16_16_UINT
 
- TFMT_16_16_16_16_UNORM
 
- TFMT_16_16_FLOAT
 
- TFMT_16_16_SINT
 
- TFMT_16_16_SNORM
 
- TFMT_16_16_UINT
 
- TFMT_16_16_UNORM
 
- TFMT_16_FLOAT
 
- TFMT_16_SINT
 
- TFMT_16_SNORM
 
- TFMT_16_UINT
 
- TFMT_16_UNORM
 
- TFMT_2_10_10_10_UINT
 
- TFMT_2_10_10_10_UNORM
 
- TFMT_32_32_32_32_FLOAT
 
- TFMT_32_32_32_32_SINT
 
- TFMT_32_32_32_32_UINT
 
- TFMT_32_32_FLOAT
 
- TFMT_32_32_SINT
 
- TFMT_32_32_UINT
 
- TFMT_32_FLOAT
 
- TFMT_32_SINT
 
- TFMT_32_UINT
 
- TFMT_4_4_4_4_UNORM
 
- TFMT_5_5_5_1_UNORM
 
- TFMT_5_6_5_UNORM
 
- TFMT_8_8_8_8_SINT
 
- TFMT_8_8_8_8_SNORM
 
- TFMT_8_8_8_8_UINT
 
- TFMT_8_8_8_8_UNORM
 
- TFMT_8_8_8_SINT
 
- TFMT_8_8_8_SNORM
 
- TFMT_8_8_8_UINT
 
- TFMT_8_8_8_UNORM
 
- TFMT_8_8_SINT
 
- TFMT_8_8_SNORM
 
- TFMT_8_8_UINT
 
- TFMT_8_8_UNORM
 
- TFMT_8_SINT
 
- TFMT_8_SNORM
 
- TFMT_8_UINT
 
- TFMT_8_UNORM
 
- TFMT_9_9_9_E5_FLOAT
 
- TFMT_A8_UNORM
 
- TFMT_ATC_RGB
 
- TFMT_ATC_RGBA_EXPLICIT
 
- TFMT_ATC_RGBA_INTERPOLATED
 
- TFMT_DXT1
 
- TFMT_DXT3
 
- TFMT_DXT5
 
- TFMT_ETC1
 
- TFMT_ETC2_R11_SNORM
 
- TFMT_ETC2_R11_UNORM
 
- TFMT_ETC2_RG11_SNORM
 
- TFMT_ETC2_RG11_UNORM
 
- TFMT_ETC2_RGB8
 
- TFMT_ETC2_RGB8A1
 
- TFMT_ETC2_RGBA8
 
- TFMT_I420_U
 
- TFMT_I420_V
 
- TFMT_I420_Y
 
- TFMT_L8_A8_UNORM
 
- TFMT_L8_UNORM
 
- TFMT_NV12_64X32
 
- TFMT_NV12_LINEAR
 
- TFMT_UV_64X32
 
- TFMT_UV_LINEAR
 
- TFMT_VU_64X32
 
- TFMT_VU_LINEAR
 
- TFMT_X8Z24_UNORM
 
- TFMT_Y_64X32
 
- TFMT_Y_LINEAR
 
- TFMT_Z16_UNORM
 
- TFMT_Z32_FLOAT
 
- TFN
 
- TFOFFSET_G
 
- TFOFFSET_M
 
- TFOFFSET_S
 
- TFOFFSET_V
 
- TFO_CLIENT_ENABLE
 
- TFO_CLIENT_NO_COOKIE
 
- TFO_SERVER_COOKIE_NOT_REQD
 
- TFO_SERVER_ENABLE
 
- TFO_SERVER_WO_SOCKOPT1
 
- TFP410_ADDR
 
- TFP410_CTL_1
 
- TFP410_CTL_1_BSEL
 
- TFP410_CTL_1_DSEL
 
- TFP410_CTL_1_EDGE
 
- TFP410_CTL_1_HEN
 
- TFP410_CTL_1_PD
 
- TFP410_CTL_1_TDIS
 
- TFP410_CTL_1_VEN
 
- TFP410_CTL_2
 
- TFP410_CTL_2_HTPLG
 
- TFP410_CTL_2_MDI
 
- TFP410_CTL_2_MSEL
 
- TFP410_CTL_2_MSEL_MASK
 
- TFP410_CTL_2_RSEN
 
- TFP410_CTL_2_TSEL
 
- TFP410_CTL_2_VLOW
 
- TFP410_CTL_3
 
- TFP410_CTL_3_CTL
 
- TFP410_CTL_3_CTL_MASK
 
- TFP410_CTL_3_DK
 
- TFP410_CTL_3_DKEN
 
- TFP410_CTL_3_DK_MASK
 
- TFP410_DE_CNT_HI
 
- TFP410_DE_CNT_LO
 
- TFP410_DE_CTL
 
- TFP410_DE_CTL_DEDLY8
 
- TFP410_DE_CTL_DEGEN
 
- TFP410_DE_CTL_HSPOL
 
- TFP410_DE_CTL_VSPOL
 
- TFP410_DE_DLY
 
- TFP410_DE_LIN_HI
 
- TFP410_DE_LIN_LO
 
- TFP410_DE_TOP
 
- TFP410_DID
 
- TFP410_DID_HI
 
- TFP410_DID_LO
 
- TFP410_H_RES_HI
 
- TFP410_H_RES_LO
 
- TFP410_REV
 
- TFP410_USERCFG
 
- TFP410_VID
 
- TFP410_VID_HI
 
- TFP410_VID_LO
 
- TFP410_V_RES_HI
 
- TFP410_V_RES_LO
 
- TFPORT_G
 
- TFPORT_M
 
- TFPORT_S
 
- TFPORT_V
 
- TFRC_CALC_X_ARRSIZE
 
- TFRC_CALC_X_SPLIT
 
- TFRC_INITIAL_TIMEOUT
 
- TFRC_NDUPACK
 
- TFRC_OPT_LOSS_EVENT_RATE
 
- TFRC_OPT_LOSS_INTERVALS
 
- TFRC_OPT_RECEIVE_RATE
 
- TFRC_RSTATE_DATA
 
- TFRC_RSTATE_NO_DATA
 
- TFRC_SMALLEST_P
 
- TFRC_SSTATE_FBACK
 
- TFRC_SSTATE_NO_FBACK
 
- TFRC_SSTATE_NO_SENT
 
- TFRC_T_DELTA
 
- TFRC_T_MBI
 
- TFRG
 
- TFRG_ADDR
 
- TFRG_IDX
 
- TFS
 
- TFSO
 
- TFSPOL_MASK
 
- TFSPOL_SHIFT
 
- TFSSEL_SHIFT
 
- TFTCTL_HWUTSF
 
- TFTCTL_HWUTSFEN
 
- TFTCTL_TBTTSYNC
 
- TFTCTL_TBTTSYNCEN
 
- TFTCTL_TSFCNTREN
 
- TFTCTL_TSFCNTRRD
 
- TFTCTL_TSFCNTRST
 
- TFTCTL_TSFSYNCEN
 
- TFTP_F
 
- TFTP_OPCODE_ACK
 
- TFTP_OPCODE_DATA
 
- TFTP_OPCODE_ERROR
 
- TFTP_OPCODE_READ
 
- TFTP_OPCODE_WRITE
 
- TFTP_PORT
 
- TFTP_S
 
- TFTP_V
 
- TFTR
 
- TFUCR
 
- TFU_SHIFT
 
- TF_ACCEPT_FDS
 
- TF_ACCESS
 
- TF_ADD_FCS
 
- TF_ATTRIBUTES
 
- TF_BACKUP
 
- TF_BLOCK_SIZE
 
- TF_BREAK
 
- TF_BUF_ESBX
 
- TF_BUF_ESDI
 
- TF_BUF_RET
 
- TF_CACHE_DISABLE
 
- TF_CACHE_ENABLE
 
- TF_CACHE_MAINT
 
- TF_CCTRL_CWR_S
 
- TF_CCTRL_ECE_S
 
- TF_CCTRL_RFR_S
 
- TF_CIT_SETUP
 
- TF_CIT_SETUP_DRV
 
- TF_CM_REG_FIELD_LIST
 
- TF_CPU_PM
 
- TF_CPU_PM_S1
 
- TF_CPU_PM_S1_NOFLUSH_L2
 
- TF_CPU_PM_S2
 
- TF_CPU_PM_S2_NO_MC_CLK
 
- TF_CPU_PM_S3
 
- TF_CREATE
 
- TF_DATA_OFFS_ERR
 
- TF_DEBUG_REG_LIST_MASK_DCN10
 
- TF_DEBUG_REG_LIST_SH_DCN10
 
- TF_DEF
 
- TF_DMA_EN
 
- TF_EFFECTIVE
 
- TF_ENP
 
- TF_ERR
 
- TF_EXIT
 
- TF_EXPIRATION
 
- TF_HELPER_REG_FIELD_LIST
 
- TF_HELPER_REG_LIST
 
- TF_INMDT
 
- TF_INPUT
 
- TF_INPUTN
 
- TF_INV_CONN_HANDLE
 
- TF_IRTT_TO
 
- TF_IU_SHORT
 
- TF_LOG
 
- TF_LONG_FORM
 
- TF_MASK
 
- TF_MAX_KEY_SIZE
 
- TF_MIN_KEY_SIZE
 
- TF_MODIFY
 
- TF_MORE
 
- TF_NAK_RECV
 
- TF_NO_SMP_CONN
 
- TF_ONE
 
- TF_ONE_WAY
 
- TF_OPEN_REJECT
 
- TF_OPEN_TO
 
- TF_OWN
 
- TF_PASS_THRU
 
- TF_PHY_DOWN
 
- TF_PM_MODE_LP0
 
- TF_PM_MODE_LP1
 
- TF_PM_MODE_LP1_NO_MC_CLK
 
- TF_PM_MODE_LP2
 
- TF_PM_MODE_LP2_NOFLUSH_L2
 
- TF_REG_FIELD_LIST
 
- TF_REG_FIELD_LIST_DCN2_0
 
- TF_REG_LIST_DCN
 
- TF_REG_LIST_DCN10
 
- TF_REG_LIST_DCN20
 
- TF_REG_LIST_SH_MASK_DCN
 
- TF_REG_LIST_SH_MASK_DCN10
 
- TF_REG_LIST_SH_MASK_DCN20
 
- TF_REQUESTED_N_PENDING
 
- TF_ROOT_OBJECT
 
- TF_RX_PDU_OUT_S
 
- TF_RX_PDU_OUT_V
 
- TF_RX_QUIESCE_S
 
- TF_RX_QUIESCE_V
 
- TF_SET_CPU_BOOT_ADDR_SMC
 
- TF_SF
 
- TF_SHIFT
 
- TF_SMPRSP_TO
 
- TF_SMP_XMIT_RCV_ERR
 
- TF_STATUS_CODE
 
- TF_STP
 
- TF_TLS_ACTIVE_S
 
- TF_TLS_ACTIVE_V
 
- TF_TLS_CONTROL_S
 
- TF_TLS_CONTROL_V
 
- TF_TLS_ENABLE_S
 
- TF_TLS_ENABLE_V
 
- TF_TLS_KEY_SIZE_S
 
- TF_TLS_KEY_SIZE_V
 
- TF_TMF_NO_CONN_HANDLE
 
- TF_TMF_NO_CTX
 
- TF_TMF_NO_TAG
 
- TF_TMF_TAG_FREE
 
- TF_TMF_TASK_DONE
 
- TF_TYPE_BYPASS
 
- TF_TYPE_DISTRIBUTED_POINTS
 
- TF_TYPE_HWPWL
 
- TF_TYPE_PREDEFINED
 
- TF_USED
 
- TF_VBEIB
 
- TG3PCI_CLOCK_CTRL
 
- TG3PCI_DEVICE
 
- TG3PCI_DEVICE_TIGON3_1
 
- TG3PCI_DEVICE_TIGON3_2
 
- TG3PCI_DEVICE_TIGON3_3
 
- TG3PCI_DEVICE_TIGON3_4
 
- TG3PCI_DEVICE_TIGON3_5717
 
- TG3PCI_DEVICE_TIGON3_5717_C
 
- TG3PCI_DEVICE_TIGON3_5718
 
- TG3PCI_DEVICE_TIGON3_5719
 
- TG3PCI_DEVICE_TIGON3_5720
 
- TG3PCI_DEVICE_TIGON3_5725
 
- TG3PCI_DEVICE_TIGON3_5727
 
- TG3PCI_DEVICE_TIGON3_5761S
 
- TG3PCI_DEVICE_TIGON3_5761SE
 
- TG3PCI_DEVICE_TIGON3_5762
 
- TG3PCI_DEVICE_TIGON3_57760
 
- TG3PCI_DEVICE_TIGON3_57761
 
- TG3PCI_DEVICE_TIGON3_57762
 
- TG3PCI_DEVICE_TIGON3_57764
 
- TG3PCI_DEVICE_TIGON3_57765
 
- TG3PCI_DEVICE_TIGON3_57766
 
- TG3PCI_DEVICE_TIGON3_57767
 
- TG3PCI_DEVICE_TIGON3_57780
 
- TG3PCI_DEVICE_TIGON3_57781
 
- TG3PCI_DEVICE_TIGON3_57782
 
- TG3PCI_DEVICE_TIGON3_57785
 
- TG3PCI_DEVICE_TIGON3_57786
 
- TG3PCI_DEVICE_TIGON3_57787
 
- TG3PCI_DEVICE_TIGON3_57788
 
- TG3PCI_DEVICE_TIGON3_57790
 
- TG3PCI_DEVICE_TIGON3_57791
 
- TG3PCI_DEVICE_TIGON3_57795
 
- TG3PCI_DEVICE_TIGON3_5785_F
 
- TG3PCI_DEVICE_TIGON3_5785_G
 
- TG3PCI_DEVICE_TIGON3_5787M
 
- TG3PCI_DEV_STATUS_CTRL
 
- TG3PCI_DMA_RW_CTRL
 
- TG3PCI_DUAL_MAC_CTRL
 
- TG3PCI_GEN15_PRODID_ASICREV
 
- TG3PCI_GEN2_PRODID_ASICREV
 
- TG3PCI_MEM_WIN_BASE_ADDR
 
- TG3PCI_MEM_WIN_DATA
 
- TG3PCI_MISC_HOST_CTRL
 
- TG3PCI_MISC_LOCAL_CTRL
 
- TG3PCI_MSI_DATA
 
- TG3PCI_PCISTATE
 
- TG3PCI_PRODID_ASICREV
 
- TG3PCI_RCV_RET_RING_CON_IDX
 
- TG3PCI_REG_BASE_ADDR
 
- TG3PCI_REG_DATA
 
- TG3PCI_STD_RING_PROD_IDX
 
- TG3PCI_SUBDEVICE_ID_3COM_3C1000T
 
- TG3PCI_SUBDEVICE_ID_3COM_3C940BR01
 
- TG3PCI_SUBDEVICE_ID_3COM_3C996BT
 
- TG3PCI_SUBDEVICE_ID_3COM_3C996SX
 
- TG3PCI_SUBDEVICE_ID_3COM_3C996T
 
- TG3PCI_SUBDEVICE_ID_ACER_57780_A
 
- TG3PCI_SUBDEVICE_ID_ACER_57780_B
 
- TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6
 
- TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9
 
- TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6
 
- TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10
 
- TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12
 
- TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5
 
- TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7
 
- TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1
 
- TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8
 
- TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1
 
- TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2
 
- TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE
 
- TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2
 
- TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING
 
- TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780
 
- TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2
 
- TG3PCI_SUBDEVICE_ID_DELL_5762
 
- TG3PCI_SUBDEVICE_ID_DELL_JAGUAR
 
- TG3PCI_SUBDEVICE_ID_DELL_MERLOT
 
- TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT
 
- TG3PCI_SUBDEVICE_ID_DELL_VIPER
 
- TG3PCI_SUBDEVICE_ID_IBM_5703SAX2
 
- TG3PCI_SUBDEVICE_ID_LENOVO_5787M
 
- TG3PCI_SUBVENDOR_ID_3COM
 
- TG3PCI_SUBVENDOR_ID_BROADCOM
 
- TG3PCI_SUBVENDOR_ID_COMPAQ
 
- TG3PCI_SUBVENDOR_ID_DELL
 
- TG3PCI_SUBVENDOR_ID_IBM
 
- TG3PCI_VENDOR
 
- TG3PCI_VENDOR_BROADCOM
 
- TG3_57766_FW_BASE_ADDR
 
- TG3_57766_FW_HANDSHAKE
 
- TG3_64BIT_REG_HIGH
 
- TG3_64BIT_REG_LOW
 
- TG3_APE_EVENT
 
- TG3_APE_EVENT_STATUS
 
- TG3_APE_FW_FEATURES
 
- TG3_APE_FW_FEATURE_NCSI
 
- TG3_APE_FW_STATUS
 
- TG3_APE_FW_VERSION
 
- TG3_APE_GPIO_MSG
 
- TG3_APE_GPIO_MSG_SHIFT
 
- TG3_APE_HB_INTERVAL
 
- TG3_APE_HOST_BEHAVIOR
 
- TG3_APE_HOST_DRIVER_ID
 
- TG3_APE_HOST_DRVR_STATE
 
- TG3_APE_HOST_DRVR_STATE_START
 
- TG3_APE_HOST_DRVR_STATE_UNLOAD
 
- TG3_APE_HOST_DRVR_STATE_WOL
 
- TG3_APE_HOST_HEARTBEAT_COUNT
 
- TG3_APE_HOST_HEARTBEAT_INT_MS
 
- TG3_APE_HOST_INIT_COUNT
 
- TG3_APE_HOST_SEG_LEN
 
- TG3_APE_HOST_SEG_SIG
 
- TG3_APE_HOST_WOL_SPEED
 
- TG3_APE_HOST_WOL_SPEED_AUTO
 
- TG3_APE_LOCK_GPIO
 
- TG3_APE_LOCK_GRANT
 
- TG3_APE_LOCK_GRC
 
- TG3_APE_LOCK_MEM
 
- TG3_APE_LOCK_PHY0
 
- TG3_APE_LOCK_PHY1
 
- TG3_APE_LOCK_PHY2
 
- TG3_APE_LOCK_PHY3
 
- TG3_APE_LOCK_REQ
 
- TG3_APE_OTP_ADDR
 
- TG3_APE_OTP_CTRL
 
- TG3_APE_OTP_RD_DATA
 
- TG3_APE_OTP_STATUS
 
- TG3_APE_PER_LOCK_GRANT
 
- TG3_APE_PER_LOCK_REQ
 
- TG3_APE_SEG_MSG_BUF_LEN
 
- TG3_APE_SEG_MSG_BUF_OFF
 
- TG3_APE_SEG_SIG
 
- TG3_APE_SHMEM_BASE
 
- TG3_BDINFO_HOST_ADDR
 
- TG3_BDINFO_MAXLEN_FLAGS
 
- TG3_BDINFO_NIC_ADDR
 
- TG3_BDINFO_SIZE
 
- TG3_BPN_SIZE
 
- TG3_CL45_D7_EEERES_STAT
 
- TG3_CL45_D7_EEERES_STAT_LP_1000T
 
- TG3_CL45_D7_EEERES_STAT_LP_100TX
 
- TG3_COPPER_TIMEOUT_SEC
 
- TG3_CORR_ERR_STAT
 
- TG3_CORR_ERR_STAT_CLEAR
 
- TG3_CPMU_CLCK_ORIDE
 
- TG3_CPMU_CLCK_ORIDE_ENABLE
 
- TG3_CPMU_CLCK_STAT
 
- TG3_CPMU_CTRL
 
- TG3_CPMU_DBTMR1_LNKIDLE_2047US
 
- TG3_CPMU_DBTMR1_LNKIDLE_MAX
 
- TG3_CPMU_DBTMR1_PCIEXIT_2047US
 
- TG3_CPMU_DBTMR2_APE_TX_2047US
 
- TG3_CPMU_DBTMR2_TXIDXEQ_2047US
 
- TG3_CPMU_DRV_STATUS
 
- TG3_CPMU_EEEMD_APE_TX_DET_EN
 
- TG3_CPMU_EEEMD_EEE_ENABLE
 
- TG3_CPMU_EEEMD_ERLY_L1_XIT_DET
 
- TG3_CPMU_EEEMD_LPI_ENABLE
 
- TG3_CPMU_EEEMD_LPI_IN_RX
 
- TG3_CPMU_EEEMD_LPI_IN_TX
 
- TG3_CPMU_EEEMD_SND_IDX_DET_EN
 
- TG3_CPMU_EEE_CTRL
 
- TG3_CPMU_EEE_CTRL_EXIT_16_5_US
 
- TG3_CPMU_EEE_CTRL_EXIT_20_1_US
 
- TG3_CPMU_EEE_CTRL_EXIT_36_US
 
- TG3_CPMU_EEE_DBTMR1
 
- TG3_CPMU_EEE_DBTMR2
 
- TG3_CPMU_EEE_LNKIDL_APE_TX_MT
 
- TG3_CPMU_EEE_LNKIDL_CTRL
 
- TG3_CPMU_EEE_LNKIDL_PCIE_NL0
 
- TG3_CPMU_EEE_LNKIDL_UART_IDL
 
- TG3_CPMU_EEE_MODE
 
- TG3_CPMU_HST_ACC
 
- TG3_CPMU_LNK_AWARE_PWRMD
 
- TG3_CPMU_LSPD_1000MB_CLK
 
- TG3_CPMU_LSPD_10MB_CLK
 
- TG3_CPMU_MAC_ORIDE_ENABLE
 
- TG3_CPMU_MUTEX_GNT
 
- TG3_CPMU_MUTEX_REQ
 
- TG3_CPMU_PADRNG_CTL
 
- TG3_CPMU_PADRNG_CTL_RDIV2
 
- TG3_CPMU_PHY_STRAP
 
- TG3_CPMU_PHY_STRAP_IS_SERDES
 
- TG3_CPMU_STATUS
 
- TG3_CPMU_STATUS_FMSK_5717
 
- TG3_CPMU_STATUS_FMSK_5719
 
- TG3_CPMU_STATUS_FSHFT_5719
 
- TG3_CPMU_STATUS_LINK_MASK
 
- TG3_DEF_MSG_ENABLE
 
- TG3_DEF_RX_JUMBO_RING_PENDING
 
- TG3_DEF_RX_MODE
 
- TG3_DEF_RX_RING_PENDING
 
- TG3_DEF_TX_MODE
 
- TG3_DEF_TX_RING_PENDING
 
- TG3_DMA_BYTE_ENAB
 
- TG3_DRV_DATA_FLAG_10_100_ONLY
 
- TG3_DRV_DATA_FLAG_5705_10_100
 
- TG3_EAV_CTL_TSYNC_GPIO_MASK
 
- TG3_EAV_CTL_TSYNC_WDOG0
 
- TG3_EAV_REF_CLCK_CTL
 
- TG3_EAV_REF_CLCK_CTL_RESUME
 
- TG3_EAV_REF_CLCK_CTL_STOP
 
- TG3_EAV_REF_CLCK_LSB
 
- TG3_EAV_REF_CLCK_MSB
 
- TG3_EAV_REF_CLK_CORRECT_CTL
 
- TG3_EAV_REF_CLK_CORRECT_EN
 
- TG3_EAV_REF_CLK_CORRECT_MASK
 
- TG3_EAV_REF_CLK_CORRECT_NEG
 
- TG3_EAV_WATCHDOG0_EN
 
- TG3_EAV_WATCHDOG0_LSB
 
- TG3_EAV_WATCHDOG0_MSB
 
- TG3_EAV_WATCHDOG_MSB_MASK
 
- TG3_EEPROM_MAGIC
 
- TG3_EEPROM_MAGIC_FW
 
- TG3_EEPROM_MAGIC_FW_MSK
 
- TG3_EEPROM_MAGIC_HW
 
- TG3_EEPROM_MAGIC_HW_MSK
 
- TG3_EEPROM_SB_EDH_BLD_MASK
 
- TG3_EEPROM_SB_EDH_BLD_SHFT
 
- TG3_EEPROM_SB_EDH_MAJ_MASK
 
- TG3_EEPROM_SB_EDH_MAJ_SHFT
 
- TG3_EEPROM_SB_EDH_MIN_MASK
 
- TG3_EEPROM_SB_F1R0_EDH_OFF
 
- TG3_EEPROM_SB_F1R2_EDH_OFF
 
- TG3_EEPROM_SB_F1R2_MBA_OFF
 
- TG3_EEPROM_SB_F1R3_EDH_OFF
 
- TG3_EEPROM_SB_F1R4_EDH_OFF
 
- TG3_EEPROM_SB_F1R5_EDH_OFF
 
- TG3_EEPROM_SB_F1R6_EDH_OFF
 
- TG3_EEPROM_SB_FORMAT_1
 
- TG3_EEPROM_SB_FORMAT_MASK
 
- TG3_EEPROM_SB_REVISION_0
 
- TG3_EEPROM_SB_REVISION_2
 
- TG3_EEPROM_SB_REVISION_3
 
- TG3_EEPROM_SB_REVISION_4
 
- TG3_EEPROM_SB_REVISION_5
 
- TG3_EEPROM_SB_REVISION_6
 
- TG3_EEPROM_SB_REVISION_MASK
 
- TG3_EXT_LOOPB_TEST
 
- TG3_FLAGS
 
- TG3_FLAG_1SHOT_MSI
 
- TG3_FLAG_40BIT_DMA_BUG
 
- TG3_FLAG_4K_FIFO_LIMIT
 
- TG3_FLAG_5701_DMA_BUG
 
- TG3_FLAG_5705_PLUS
 
- TG3_FLAG_5717_PLUS
 
- TG3_FLAG_5719_5720_RDMA_BUG
 
- TG3_FLAG_5750_PLUS
 
- TG3_FLAG_5755_PLUS
 
- TG3_FLAG_57765_CLASS
 
- TG3_FLAG_57765_PLUS
 
- TG3_FLAG_5780_CLASS
 
- TG3_FLAG_APE_HAS_NCSI
 
- TG3_FLAG_ASF_NEW_HANDSHAKE
 
- TG3_FLAG_ASPM_WORKAROUND
 
- TG3_FLAG_BROKEN_CHECKSUMS
 
- TG3_FLAG_CHIP_RESETTING
 
- TG3_FLAG_CLKREQ_BUG
 
- TG3_FLAG_CPMU_PRESENT
 
- TG3_FLAG_EEPROM_WRITE_PROT
 
- TG3_FLAG_ENABLE_APE
 
- TG3_FLAG_ENABLE_ASF
 
- TG3_FLAG_ENABLE_RSS
 
- TG3_FLAG_ENABLE_TSS
 
- TG3_FLAG_ERROR_PROCESSED
 
- TG3_FLAG_FLASH
 
- TG3_FLAG_FLUSH_POSTED_WRITES
 
- TG3_FLAG_FW_TSO
 
- TG3_FLAG_HW_AUTONEG
 
- TG3_FLAG_HW_TSO_1
 
- TG3_FLAG_HW_TSO_2
 
- TG3_FLAG_HW_TSO_3
 
- TG3_FLAG_ICH_WORKAROUND
 
- TG3_FLAG_INIT_COMPLETE
 
- TG3_FLAG_IS_5788
 
- TG3_FLAG_IS_NIC
 
- TG3_FLAG_IS_SSB_CORE
 
- TG3_FLAG_JUMBO_CAPABLE
 
- TG3_FLAG_JUMBO_RING_ENABLE
 
- TG3_FLAG_L1PLLPD_EN
 
- TG3_FLAG_LRG_PROD_RING_CAP
 
- TG3_FLAG_MAX_RXPEND_64
 
- TG3_FLAG_MBOX_WRITE_REORDER
 
- TG3_FLAG_MDIOBUS_INITED
 
- TG3_FLAG_NO_FWARE_REPORTED
 
- TG3_FLAG_NO_NVRAM
 
- TG3_FLAG_NO_NVRAM_ADDR_TRANS
 
- TG3_FLAG_NUMBER_OF_FLAGS
 
- TG3_FLAG_NVRAM
 
- TG3_FLAG_NVRAM_BUFFERED
 
- TG3_FLAG_ONE_DMA_AT_ONCE
 
- TG3_FLAG_PAUSE_AUTONEG
 
- TG3_FLAG_PCIX_MODE
 
- TG3_FLAG_PCIX_TARGET_HWBUG
 
- TG3_FLAG_PCI_32BIT
 
- TG3_FLAG_PCI_EXPRESS
 
- TG3_FLAG_PCI_HIGH_SPEED
 
- TG3_FLAG_POLL_CPMU_LINK
 
- TG3_FLAG_POLL_SERDES
 
- TG3_FLAG_PROTECTED_NVRAM
 
- TG3_FLAG_PTP_CAPABLE
 
- TG3_FLAG_RESET_TASK_PENDING
 
- TG3_FLAG_RGMII_EXT_IBND_RX_EN
 
- TG3_FLAG_RGMII_EXT_IBND_TX_EN
 
- TG3_FLAG_RGMII_INBAND_DISABLE
 
- TG3_FLAG_RGMII_MODE
 
- TG3_FLAG_ROBOSWITCH
 
- TG3_FLAG_SHORT_DMA_BUG
 
- TG3_FLAG_SRAM_USE_CONFIG
 
- TG3_FLAG_SUPPORT_MSI
 
- TG3_FLAG_SUPPORT_MSIX
 
- TG3_FLAG_TAGGED_STATUS
 
- TG3_FLAG_TSO_BUG
 
- TG3_FLAG_TSO_CAPABLE
 
- TG3_FLAG_TXD_MBOX_HWBUG
 
- TG3_FLAG_TX_RECOVERY_PENDING
 
- TG3_FLAG_TX_TSTAMP_EN
 
- TG3_FLAG_USE_JUMBO_BDFLAG
 
- TG3_FLAG_USE_LINKCHG_REG
 
- TG3_FLAG_USE_PHYLIB
 
- TG3_FLAG_USING_MSI
 
- TG3_FLAG_USING_MSIX
 
- TG3_FLAG_WOL_CAP
 
- TG3_FLAG_WOL_ENABLE
 
- TG3_FLAG_WOL_SPEED_100MB
 
- TG3_FL_5705
 
- TG3_FL_NOT_5705
 
- TG3_FL_NOT_5750
 
- TG3_FL_NOT_5788
 
- TG3_FW_EVENT_TIMEOUT_USEC
 
- TG3_FW_HDR_LEN
 
- TG3_FW_UPDATE_FREQ_SEC
 
- TG3_FW_UPDATE_TIMEOUT_SEC
 
- TG3_GPIO_MSG_ALL_DRVR_PRES_MASK
 
- TG3_GPIO_MSG_ALL_NEED_VAUX_MASK
 
- TG3_GPIO_MSG_DRVR_PRES
 
- TG3_GPIO_MSG_MASK
 
- TG3_GPIO_MSG_NEED_VAUX
 
- TG3_GRC_LCLCTL_PWRSW_DELAY
 
- TG3_HW_STATUS_SIZE
 
- TG3_INTERRUPT_TEST
 
- TG3_IRQ_MAX_VECS
 
- TG3_IRQ_MAX_VECS_RSS
 
- TG3_JMB_LOOPBACK_FAILED
 
- TG3_KNOWN_PHY_ID
 
- TG3_LINK_TEST
 
- TG3_LOOPBACK_FAILED
 
- TG3_LSO_RD_DMA_CRPTEN_CTRL
 
- TG3_LSO_RD_DMA_CRPTEN_CTRL2
 
- TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K
 
- TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K
 
- TG3_LSO_RD_DMA_TX_LENGTH_WA_5719
 
- TG3_LSO_RD_DMA_TX_LENGTH_WA_5720
 
- TG3_MAC_LOOPB_TEST
 
- TG3_MAJ_NUM
 
- TG3_MAX_MTU
 
- TG3_MAX_UCAST_ADDR
 
- TG3_MEMORY_TEST
 
- TG3_MIN_MTU
 
- TG3_MIN_NUM
 
- TG3_NUM_RDMA_CHANNELS
 
- TG3_NUM_STATS
 
- TG3_NUM_TEST
 
- TG3_NVM_BCVER_MAJMSK
 
- TG3_NVM_BCVER_MAJSFT
 
- TG3_NVM_BCVER_MINMSK
 
- TG3_NVM_DIRENT_SIZE
 
- TG3_NVM_DIRTYPE_ASFINI
 
- TG3_NVM_DIRTYPE_EXTVPD
 
- TG3_NVM_DIRTYPE_LENMSK
 
- TG3_NVM_DIRTYPE_SHIFT
 
- TG3_NVM_DIR_END
 
- TG3_NVM_DIR_START
 
- TG3_NVM_HWSB_CFG1
 
- TG3_NVM_HWSB_CFG1_MAJMSK
 
- TG3_NVM_HWSB_CFG1_MAJSFT
 
- TG3_NVM_HWSB_CFG1_MINMSK
 
- TG3_NVM_HWSB_CFG1_MINSFT
 
- TG3_NVM_PTREV_BCVER
 
- TG3_NVM_VPD_LEN
 
- TG3_NVM_VPD_OFF
 
- TG3_NVRAM_SIZE_128KB
 
- TG3_NVRAM_SIZE_1MB
 
- TG3_NVRAM_SIZE_256KB
 
- TG3_NVRAM_SIZE_2KB
 
- TG3_NVRAM_SIZE_2MB
 
- TG3_NVRAM_SIZE_512KB
 
- TG3_NVRAM_SIZE_64KB
 
- TG3_NVRAM_TEST
 
- TG3_OCIR_FLAG_ACTIVE
 
- TG3_OCIR_LEN
 
- TG3_OCIR_SIG_MAGIC
 
- TG3_OTP_10BTAMP_MASK
 
- TG3_OTP_10BTAMP_SHIFT
 
- TG3_OTP_AGCTGT_MASK
 
- TG3_OTP_AGCTGT_SHIFT
 
- TG3_OTP_DEFAULT
 
- TG3_OTP_HPFFLTR_MASK
 
- TG3_OTP_HPFFLTR_SHIFT
 
- TG3_OTP_HPFOVER_MASK
 
- TG3_OTP_HPFOVER_SHIFT
 
- TG3_OTP_LPFDIS_MASK
 
- TG3_OTP_LPFDIS_SHIFT
 
- TG3_OTP_MAGIC0_VALID
 
- TG3_OTP_RCOFF_MASK
 
- TG3_OTP_RCOFF_SHIFT
 
- TG3_OTP_ROFF_MASK
 
- TG3_OTP_ROFF_SHIFT
 
- TG3_OTP_VDAC_MASK
 
- TG3_OTP_VDAC_SHIFT
 
- TG3_PCIE_DL_LO_FTSMAX
 
- TG3_PCIE_DL_LO_FTSMAX_MSK
 
- TG3_PCIE_DL_LO_FTSMAX_VAL
 
- TG3_PCIE_EIDLE_DELAY
 
- TG3_PCIE_EIDLE_DELAY_13_CLKS
 
- TG3_PCIE_EIDLE_DELAY_MASK
 
- TG3_PCIE_LNKCTL
 
- TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
 
- TG3_PCIE_LNKCTL_L1_PLL_PD_EN
 
- TG3_PCIE_PHY_TSTCTL
 
- TG3_PCIE_PHY_TSTCTL_PCIE10
 
- TG3_PCIE_PHY_TSTCTL_PSCRAM
 
- TG3_PCIE_PL_LO_PHYCTL1
 
- TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN
 
- TG3_PCIE_PL_LO_PHYCTL5
 
- TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ
 
- TG3_PCIE_TLDLPL_PORT
 
- TG3_PHYFLG_10_100_ONLY
 
- TG3_PHYFLG_1G_ON_VAUX_OK
 
- TG3_PHYFLG_5704_A0_BUG
 
- TG3_PHYFLG_ADC_BUG
 
- TG3_PHYFLG_ADJUST_TRIM
 
- TG3_PHYFLG_ANY_SERDES
 
- TG3_PHYFLG_BER_BUG
 
- TG3_PHYFLG_CAPACITIVE_COUPLING
 
- TG3_PHYFLG_DISABLE_1G_HD_ADV
 
- TG3_PHYFLG_EEE_CAP
 
- TG3_PHYFLG_ENABLE_APD
 
- TG3_PHYFLG_IS_CONNECTED
 
- TG3_PHYFLG_IS_FET
 
- TG3_PHYFLG_IS_LOW_POWER
 
- TG3_PHYFLG_JITTER_BUG
 
- TG3_PHYFLG_KEEP_LINK_ON_PWRDN
 
- TG3_PHYFLG_MDIX_STATE
 
- TG3_PHYFLG_MII_SERDES
 
- TG3_PHYFLG_NO_ETH_WIRE_SPEED
 
- TG3_PHYFLG_PARALLEL_DETECT
 
- TG3_PHYFLG_PHY_SERDES
 
- TG3_PHYFLG_SERDES_PREEMPHASIS
 
- TG3_PHYFLG_USER_CONFIGURED
 
- TG3_PHYFLG_USE_MI_INTERRUPT
 
- TG3_PHY_ID_BCM5400
 
- TG3_PHY_ID_BCM5401
 
- TG3_PHY_ID_BCM5411
 
- TG3_PHY_ID_BCM5701
 
- TG3_PHY_ID_BCM5703
 
- TG3_PHY_ID_BCM5704
 
- TG3_PHY_ID_BCM5705
 
- TG3_PHY_ID_BCM5714
 
- TG3_PHY_ID_BCM5718C
 
- TG3_PHY_ID_BCM5718S
 
- TG3_PHY_ID_BCM5719C
 
- TG3_PHY_ID_BCM5720C
 
- TG3_PHY_ID_BCM5750
 
- TG3_PHY_ID_BCM5752
 
- TG3_PHY_ID_BCM5755
 
- TG3_PHY_ID_BCM5756
 
- TG3_PHY_ID_BCM5761
 
- TG3_PHY_ID_BCM5762
 
- TG3_PHY_ID_BCM57765
 
- TG3_PHY_ID_BCM5780
 
- TG3_PHY_ID_BCM5784
 
- TG3_PHY_ID_BCM5787
 
- TG3_PHY_ID_BCM5906
 
- TG3_PHY_ID_BCM8002
 
- TG3_PHY_ID_INVALID
 
- TG3_PHY_ID_MASK
 
- TG3_PHY_ID_REV_MASK
 
- TG3_PHY_LOOPB_TEST
 
- TG3_PHY_MII_ADDR
 
- TG3_PHY_REV_BCM5401_B0
 
- TG3_RAW_IP_ALIGN
 
- TG3_RDMA_LENGTH
 
- TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K
 
- TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK
 
- TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K
 
- TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK
 
- TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX
 
- TG3_RDMA_RSRVCTRL_REG
 
- TG3_RDMA_RSRVCTRL_REG2
 
- TG3_RDMA_RSRVCTRL_TXMRGN_320B
 
- TG3_RDMA_RSRVCTRL_TXMRGN_MASK
 
- TG3_REGISTER_TEST
 
- TG3_REG_BLK_SIZE
 
- TG3_RSS_INDIR_TBL_SIZE
 
- TG3_RSS_MAX_NUM_QS
 
- TG3_RX_COPY_THRESH
 
- TG3_RX_COPY_THRESHOLD
 
- TG3_RX_DMA_TO_MAP_SZ
 
- TG3_RX_JMB_BUFF_RING_SIZE
 
- TG3_RX_JMB_DMA_SZ
 
- TG3_RX_JMB_MAP_SZ
 
- TG3_RX_JMB_MAX_SIZE_5700
 
- TG3_RX_JMB_MAX_SIZE_5717
 
- TG3_RX_JMB_PROD_IDX_REG
 
- TG3_RX_JMB_RING_BYTES
 
- TG3_RX_JMB_RING_SIZE
 
- TG3_RX_OFFSET
 
- TG3_RX_PTP_CTL
 
- TG3_RX_PTP_CTL_ALL_V1_EVENTS
 
- TG3_RX_PTP_CTL_ALL_V2_EVENTS
 
- TG3_RX_PTP_CTL_ANNOUNCE
 
- TG3_RX_PTP_CTL_DELAY_REQ
 
- TG3_RX_PTP_CTL_DELAY_RES
 
- TG3_RX_PTP_CTL_FOLLOW_UP
 
- TG3_RX_PTP_CTL_HWTS_INTERLOCK
 
- TG3_RX_PTP_CTL_MANAGEMENT
 
- TG3_RX_PTP_CTL_PDLAY_REQ
 
- TG3_RX_PTP_CTL_PDLAY_RES
 
- TG3_RX_PTP_CTL_PDRES_FLW_UP
 
- TG3_RX_PTP_CTL_RX_PTP_V1_EN
 
- TG3_RX_PTP_CTL_RX_PTP_V2_EN
 
- TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN
 
- TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN
 
- TG3_RX_PTP_CTL_SIGNALING
 
- TG3_RX_PTP_CTL_SYNC_EVNT
 
- TG3_RX_RCB_RING_BYTES
 
- TG3_RX_RET_MAX_SIZE_5700
 
- TG3_RX_RET_MAX_SIZE_5705
 
- TG3_RX_RET_MAX_SIZE_5717
 
- TG3_RX_STD_BUFF_RING_SIZE
 
- TG3_RX_STD_DMA_SZ
 
- TG3_RX_STD_MAP_SZ
 
- TG3_RX_STD_MAX_SIZE_5700
 
- TG3_RX_STD_MAX_SIZE_5717
 
- TG3_RX_STD_PROD_IDX_REG
 
- TG3_RX_STD_RING_BYTES
 
- TG3_RX_STD_RING_SIZE
 
- TG3_RX_TSTAMP_LSB
 
- TG3_RX_TSTAMP_MSB
 
- TG3_SBROM_IN_SERVICE_LOOP
 
- TG3_SD_NUM_RECS
 
- TG3_SERDES_TIMEOUT_SEC
 
- TG3_SRAM_RXCPU_SCRATCH_BASE_57766
 
- TG3_SRAM_RXCPU_SCRATCH_SIZE_57766
 
- TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700
 
- TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717
 
- TG3_SRAM_RX_STD_BDCACHE_SIZE_5700
 
- TG3_SRAM_RX_STD_BDCACHE_SIZE_5755
 
- TG3_SRAM_RX_STD_BDCACHE_SIZE_5906
 
- TG3_STAT_ADD32
 
- TG3_STD_LOOPBACK_FAILED
 
- TG3_TEMP_CAUTION_OFFSET
 
- TG3_TEMP_MAX_OFFSET
 
- TG3_TEMP_SENSOR_OFFSET
 
- TG3_TSO_IP_HDR_LEN
 
- TG3_TSO_LOOPBACK_FAILED
 
- TG3_TSO_MSS
 
- TG3_TSO_TCP_HDR_LEN
 
- TG3_TSO_TCP_OPT_LEN
 
- TG3_TSTAMP_MASK
 
- TG3_TX_BD_DMA_MAX_2K
 
- TG3_TX_BD_DMA_MAX_4K
 
- TG3_TX_RING_BYTES
 
- TG3_TX_RING_SIZE
 
- TG3_TX_TIMEOUT
 
- TG3_TX_TSTAMP_LSB
 
- TG3_TX_TSTAMP_MSB
 
- TG3_TX_WAKEUP_THRESH
 
- TG3_UCAST_ADDR_IDX
 
- TG3_VER_SIZE
 
- TGAFB_H
 
- TGA_24PLANE_FB_OFFSET
 
- TGA_24PLUSZ_FB_OFFSET
 
- TGA_8PLANE_FB_OFFSET
 
- TGA_BACKGROUND_REG
 
- TGA_BASE_ADDR_REG
 
- TGA_BLOCK_COLOR0_REG
 
- TGA_BLOCK_COLOR1_REG
 
- TGA_BLOCK_COLOR2_REG
 
- TGA_BLOCK_COLOR3_REG
 
- TGA_BLOCK_COLOR4_REG
 
- TGA_BLOCK_COLOR5_REG
 
- TGA_BLOCK_COLOR6_REG
 
- TGA_BLOCK_COLOR7_REG
 
- TGA_BUS_TC
 
- TGA_CLOCK_REG
 
- TGA_CMD_STAT_REG
 
- TGA_COPY64_DST
 
- TGA_COPY64_SRC
 
- TGA_CURSOR_BASE_REG
 
- TGA_CURSOR_XY_REG
 
- TGA_DATA_REG
 
- TGA_DEEP_REG
 
- TGA_FOREGROUND_REG
 
- TGA_HORIZ_ACT_LSB
 
- TGA_HORIZ_ACT_MSB
 
- TGA_HORIZ_BP
 
- TGA_HORIZ_FP
 
- TGA_HORIZ_ODD
 
- TGA_HORIZ_POLARITY
 
- TGA_HORIZ_REG
 
- TGA_HORIZ_SYNC
 
- TGA_INTR_STAT_REG
 
- TGA_MODE_BLOCK_FILL
 
- TGA_MODE_BLOCK_STIPPLE
 
- TGA_MODE_COPY
 
- TGA_MODE_DMA_READ_COPY_D
 
- TGA_MODE_DMA_READ_COPY_ND
 
- TGA_MODE_DMA_WRITE_COPY
 
- TGA_MODE_OPAQUE_FILL
 
- TGA_MODE_OPAQUE_STIPPLE
 
- TGA_MODE_REG
 
- TGA_MODE_SBM_24BPP
 
- TGA_MODE_SBM_8BPP
 
- TGA_MODE_SIMPLE
 
- TGA_MODE_SIMPLEZ
 
- TGA_MODE_TRANSPARENT_FILL
 
- TGA_MODE_TRANSPARENT_STIPPLE
 
- TGA_PIXELMASK_ONESHOT_REG
 
- TGA_PIXELMASK_REG
 
- TGA_PIXELSHIFT_REG
 
- TGA_PLANEMASK_REG
 
- TGA_PLL_BASE_FREQ
 
- TGA_PLL_MAX_FREQ
 
- TGA_RAMDAC_REG
 
- TGA_RAMDAC_SETUP_REG
 
- TGA_RASTEROP_REG
 
- TGA_READ_REG
 
- TGA_REGS_OFFSET
 
- TGA_ROM_OFFSET
 
- TGA_START_REG
 
- TGA_TYPE_24PLANE
 
- TGA_TYPE_24PLUSZ
 
- TGA_TYPE_8PLANE
 
- TGA_VALID_BLANK
 
- TGA_VALID_CURSOR
 
- TGA_VALID_REG
 
- TGA_VALID_VIDEO
 
- TGA_VERT_ACTIVE
 
- TGA_VERT_BP
 
- TGA_VERT_FP
 
- TGA_VERT_POLARITY
 
- TGA_VERT_REG
 
- TGA_VERT_RESERVED
 
- TGA_VERT_SE
 
- TGA_VERT_SYNC
 
- TGA_WRITE_REG
 
- TGC
 
- TGCR
 
- TGCR_PSCHI_MASK
 
- TGCR_RESET
 
- TGCR_RESET_MASK
 
- TGCR_TDDRHI_MASK
 
- TGCR_TIM12RS_SHIFT
 
- TGCR_TIM34RS_SHIFT
 
- TGCR_TIMHIRS
 
- TGCR_TIMLORS
 
- TGCR_TIMMODE_32BIT_CHAINED
 
- TGCR_TIMMODE_32BIT_UNCHAINED
 
- TGCR_TIMMODE_64BIT_GP
 
- TGCR_TIMMODE_64BIT_WDOG
 
- TGCR_TIMMODE_CD32
 
- TGCR_TIMMODE_MASK
 
- TGCR_TIMMODE_SHIFT
 
- TGCR_TIMMODE_UD32
 
- TGCR_TIMMODE_WDT64
 
- TGCR_TIM_UNRESET_MASK
 
- TGCR_UNRESET
 
- TGC_BIT
 
- TGC_TBD0
 
- TGC_TBD1
 
- TGC_TBD2
 
- TGC_TBD3
 
- TGC_TQP
 
- TGC_TQP_AVBMODE1
 
- TGC_TQP_AVBMODE2
 
- TGC_TQP_NONAVB
 
- TGC_TSM0
 
- TGC_TSM1
 
- TGC_TSM2
 
- TGC_TSM3
 
- TGEC_HASH_ADR_MSK
 
- TGEC_HASH_MCAST_EN
 
- TGEC_HASH_MCAST_SHIFT
 
- TGEC_HASH_TABLE_SIZE
 
- TGEC_IMASK_LOC_FAULT
 
- TGEC_IMASK_MDIO_CMD_CMPL
 
- TGEC_IMASK_MDIO_SCAN_EVENT
 
- TGEC_IMASK_REM_FAULT
 
- TGEC_IMASK_RX_ALIGN_ER
 
- TGEC_IMASK_RX_CRC_ER
 
- TGEC_IMASK_RX_ECC_ER
 
- TGEC_IMASK_RX_FIFO_OVFL
 
- TGEC_IMASK_RX_FRAG_FRM
 
- TGEC_IMASK_RX_JAB_FRM
 
- TGEC_IMASK_RX_LEN_ER
 
- TGEC_IMASK_RX_OVRSZ_FRM
 
- TGEC_IMASK_RX_RUNT_FRM
 
- TGEC_IMASK_TX_ECC_ER
 
- TGEC_IMASK_TX_ER
 
- TGEC_IMASK_TX_FIFO_OVFL
 
- TGEC_IMASK_TX_FIFO_UNFL
 
- TGEC_NUM_OF_PADDRS
 
- TGEC_TX_IPG_LENGTH_MASK
 
- TGEN
 
- TGEnableMode
 
- TGFX_DOWN
 
- TGFX_LEFT
 
- TGFX_MAX_DEVICES
 
- TGFX_MAX_PORTS
 
- TGFX_REFRESH_TIME
 
- TGFX_RIGHT
 
- TGFX_THUMB
 
- TGFX_THUMB2
 
- TGFX_TOP
 
- TGFX_TOP2
 
- TGFX_TRIGGER
 
- TGFX_UP
 
- TGHCAUSE_DATA_ERR
 
- TGHCAUSE_LRU_ECC
 
- TGHCAUSE_MUL_ERR
 
- TGHCAUSE_PS_ECC
 
- TGHCAUSE_RR_ECC
 
- TGHCAUSE_SW_FORCE
 
- TGHCAUSE_TLB_ECC
 
- TGHCMD_START
 
- TGHOP_TLBINV
 
- TGHOP_TLBNOP
 
- TGHSTATE_IDLE
 
- TGHSTATE_INTERRUPT_INVAL
 
- TGHSTATE_PE_INVAL
 
- TGHSTATE_RESTART_CTX
 
- TGHSTATE_WAITDONE
 
- TGHSTATUS_ACTIVE
 
- TGHSTATUS_EXCEPTION
 
- TGHSTATUS_IDLE
 
- TGID_OFFSET
 
- TGID_ROLLOVER
 
- TGLDSP_SLEEP
 
- TGLDSP_SLEEP_MODE
 
- TGL_AUX_TBT5_IO_POWER_DOMAINS
 
- TGL_AUX_TBT6_IO_POWER_DOMAINS
 
- TGL_AUX_TC1_IO_POWER_DOMAINS
 
- TGL_AUX_TC2_IO_POWER_DOMAINS
 
- TGL_AUX_TC3_IO_POWER_DOMAINS
 
- TGL_AUX_TC4_IO_POWER_DOMAINS
 
- TGL_AUX_TC5_IO_POWER_DOMAINS
 
- TGL_AUX_TC6_IO_POWER_DOMAINS
 
- TGL_CSR_MAX_FW_SIZE
 
- TGL_CSR_PATH
 
- TGL_CSR_VERSION_REQUIRED
 
- TGL_DDC_BUS_DDI_C
 
- TGL_DDC_BUS_PORT_5
 
- TGL_DDC_BUS_PORT_6
 
- TGL_DDI_IO_TC1_POWER_DOMAINS
 
- TGL_DDI_IO_TC2_POWER_DOMAINS
 
- TGL_DDI_IO_TC3_POWER_DOMAINS
 
- TGL_DDI_IO_TC4_POWER_DOMAINS
 
- TGL_DDI_IO_TC5_POWER_DOMAINS
 
- TGL_DDI_IO_TC6_POWER_DOMAINS
 
- TGL_DE_PORT_AUX_DDIA
 
- TGL_DE_PORT_AUX_DDIB
 
- TGL_DE_PORT_AUX_DDIC
 
- TGL_DFSM_PIPE_D_DISABLE
 
- TGL_DISPLAY_DC_OFF_POWER_DOMAINS
 
- TGL_DMC_DEBUG_DC5_COUNT
 
- TGL_DMC_DEBUG_DC6_COUNT
 
- TGL_DPLL_CFGCR0
 
- TGL_DPLL_CFGCR1
 
- TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL
 
- TGL_LP_DEVICE_ID
 
- TGL_PW_2_POWER_DOMAINS
 
- TGL_PW_3_POWER_DOMAINS
 
- TGL_PW_4_POWER_DOMAINS
 
- TGL_PW_5_POWER_DOMAINS
 
- TGL_PW_CTL_IDX_AUX_TBT1
 
- TGL_PW_CTL_IDX_AUX_TBT2
 
- TGL_PW_CTL_IDX_AUX_TBT3
 
- TGL_PW_CTL_IDX_AUX_TBT4
 
- TGL_PW_CTL_IDX_AUX_TBT5
 
- TGL_PW_CTL_IDX_AUX_TBT6
 
- TGL_PW_CTL_IDX_AUX_TC1
 
- TGL_PW_CTL_IDX_AUX_TC2
 
- TGL_PW_CTL_IDX_AUX_TC3
 
- TGL_PW_CTL_IDX_AUX_TC4
 
- TGL_PW_CTL_IDX_AUX_TC5
 
- TGL_PW_CTL_IDX_AUX_TC6
 
- TGL_PW_CTL_IDX_DDI_TC1
 
- TGL_PW_CTL_IDX_DDI_TC2
 
- TGL_PW_CTL_IDX_DDI_TC3
 
- TGL_PW_CTL_IDX_DDI_TC4
 
- TGL_PW_CTL_IDX_DDI_TC5
 
- TGL_PW_CTL_IDX_DDI_TC6
 
- TGL_PW_CTL_IDX_PW_5
 
- TGL_TRANS_CLK_SEL_DISABLED
 
- TGL_TRANS_CLK_SEL_PORT
 
- TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT
 
- TGL_TRANS_DDI_PORT_MASK
 
- TGL_TRANS_DDI_PORT_SHIFT
 
- TGL_TRANS_DDI_SELECT_PORT
 
- TGPIODIR
 
- TGPIOVAL
 
- TGPIO_BFLR
 
- TGPIO_FLR
 
- TGPIO_ICR
 
- TGPIO_IER
 
- TGPIO_IPR
 
- TGPIO_ISR
 
- TGPIO_LVR
 
- TGPIO_VER
 
- TGPL
 
- TGP_COLOR_ENC_HSV
 
- TGP_COLOR_ENC_LUMA
 
- TGP_COLOR_ENC_RGB
 
- TGP_COLOR_ENC_YCBCR
 
- TGP_DDIC_HPD_ENABLE
 
- TGP_DDIC_HPD_LONG_DETECT
 
- TGP_DDIC_HPD_NO_DETECT
 
- TGP_DDIC_HPD_SHORT_DETECT
 
- TGP_DDIC_HPD_SHORT_LONG_DETECT
 
- TGP_DDIC_HPD_STATUS_MASK
 
- TGP_DDI_HPD_ENABLE_MASK
 
- TGP_TC_HPD_ENABLE_MASK
 
- TGP_THROTTLING_BIT
 
- TGP_THROTTLING_MASK
 
- TGR
 
- TGR128_DIGEST_SIZE
 
- TGR160_DIGEST_SIZE
 
- TGR192_BLOCK_SIZE
 
- TGR192_DIGEST_SIZE
 
- TGReadWriteMode
 
- TGSL
 
- TGSRC_REG_DBG_DWORD_ENABLE_E5
 
- TGSRC_REG_DBG_FORCE_FRAME_E5
 
- TGSRC_REG_DBG_FORCE_VALID_E5
 
- TGSRC_REG_DBG_SELECT_E5
 
- TGSRC_REG_DBG_SHIFT_E5
 
- TGT
 
- TGTPORT_OPTS
 
- TGT_B
 
- TGT_CTX_UPDT_CMD
 
- TGT_DM_CMD
 
- TGT_GB
 
- TGT_GR
 
- TGT_R
 
- TGUI9440
 
- TGUI9660
 
- TG_COMMON_MASK_SH_LIST_DCN
 
- TG_COMMON_MASK_SH_LIST_DCN1_0
 
- TG_COMMON_MASK_SH_LIST_DCN2_0
 
- TG_COMMON_REG_LIST_DCN
 
- TG_COMMON_REG_LIST_DCN1_0
 
- TG_COMMON_REG_LIST_DCN2_0
 
- TG_DIV_VAL
 
- TG_DUTYCTL
 
- TG_GPODR1
 
- TG_GPODR2
 
- TG_GPOSR
 
- TG_HPOSCTL
 
- TG_LO_DIVVAL
 
- TG_LO_SELVAL
 
- TG_PINICTL
 
- TG_PNLCTL
 
- TG_PT_GROUP_NAME_BUF
 
- TG_REG0_COLOR
 
- TG_REG0_LR
 
- TG_REG0_UD
 
- TG_REG0_VQV
 
- TG_REG_FIELD_LIST
 
- TG_REG_FIELD_LIST_DCN1_0
 
- TG_RSTX
 
- TG_R_DIV
 
- TG_SET
 
- TG_TPOSCTL
 
- TG_VCO_BIAS
 
- THASH
 
- THC63_LVDS_IN0
 
- THC63_LVDS_IN1
 
- THC63_RGB_OUT0
 
- THC63_RGB_OUT1
 
- THCTR_PONM
 
- THCTR_THSST
 
- THERM
 
- THERMAL_APIC_VECTOR
 
- THERMAL_ATTRS
 
- THERMAL_AUX0
 
- THERMAL_AUX1
 
- THERMAL_CRITICAL
 
- THERMAL_CSTATE_INVALID
 
- THERMAL_DEVICE_DISABLED
 
- THERMAL_DEVICE_DOWN
 
- THERMAL_DEVICE_ENABLED
 
- THERMAL_DEVICE_POWER_CAPABILITY_CHANGED
 
- THERMAL_DEVICE_UP
 
- THERMAL_DEV_FAULT
 
- THERMAL_DIODE_MODE
 
- THERMAL_ENABLE
 
- THERMAL_EVENT_TEMP_SAMPLE
 
- THERMAL_EVENT_UNSPECIFIED
 
- THERMAL_GENL_ATTR_EVENT
 
- THERMAL_GENL_ATTR_MAX
 
- THERMAL_GENL_ATTR_UNSPEC
 
- THERMAL_GENL_CMD_EVENT
 
- THERMAL_GENL_CMD_MAX
 
- THERMAL_GENL_CMD_UNSPEC
 
- THERMAL_GENL_FAMILY_NAME
 
- THERMAL_GENL_MCAST_GROUP_NAME
 
- THERMAL_GENL_VERSION
 
- THERMAL_GOVERNOR_DECLARE
 
- THERMAL_INT_OUTPUT_GPIO_PINID
 
- THERMAL_LOG_ENABLE
 
- THERMAL_MAX_TRIPS
 
- THERMAL_NAME_LENGTH
 
- THERMAL_NO_LIMIT
 
- THERMAL_NO_TARGET
 
- THERMAL_PAGE_CODE_7H
 
- THERMAL_PAGE_CODE_8H
 
- THERMAL_PDN
 
- THERMAL_PID_REG
 
- THERMAL_PROTECTION_DIS
 
- THERMAL_PROTECTION_TYPE
 
- THERMAL_REVISION_REG
 
- THERMAL_SENSOR
 
- THERMAL_SENSOR_ATTR_TEMP
 
- THERMAL_SMSC_ID_REG
 
- THERMAL_SPEC_POWER
 
- THERMAL_SRSTN
 
- THERMAL_SYSFS
 
- THERMAL_TABLE
 
- THERMAL_TABLE_CHANGED
 
- THERMAL_TABLE_ENTRY
 
- THERMAL_TEMP_INVALID
 
- THERMAL_THROTTLING_EVENT
 
- THERMAL_TREND_DROPPING
 
- THERMAL_TREND_DROP_FULL
 
- THERMAL_TREND_RAISE_FULL
 
- THERMAL_TREND_RAISING
 
- THERMAL_TREND_STABLE
 
- THERMAL_TRIPS_NONE
 
- THERMAL_TRIP_ACTIVE
 
- THERMAL_TRIP_CHANGED
 
- THERMAL_TRIP_CRITICAL
 
- THERMAL_TRIP_HOT
 
- THERMAL_TRIP_PASSIVE
 
- THERMAL_TRIP_VIOLATED
 
- THERMAL_TYPE_ADT7473_WITH_INTERNAL
 
- THERMAL_TYPE_CI
 
- THERMAL_TYPE_EMC2103_WITH_INTERNAL
 
- THERMAL_TYPE_EVERGREEN
 
- THERMAL_TYPE_EXTERNAL
 
- THERMAL_TYPE_EXTERNAL_GPIO
 
- THERMAL_TYPE_KV
 
- THERMAL_TYPE_NI
 
- THERMAL_TYPE_NONE
 
- THERMAL_TYPE_RV6XX
 
- THERMAL_TYPE_RV770
 
- THERMAL_TYPE_SI
 
- THERMAL_TYPE_SUMO
 
- THERMAL_VCC
 
- THERMAL_WEIGHT_DEFAULT
 
- THERMCTL_INTR_DISABLE
 
- THERMCTL_INTR_ENABLE
 
- THERMCTL_INTR_STATUS
 
- THERMCTL_LEVEL0_GROUP_CPU
 
- THERMCTL_LEVEL0_GROUP_GPU
 
- THERMCTL_LEVEL0_GROUP_MEM
 
- THERMCTL_LEVEL0_GROUP_TSENSE
 
- THERMCTL_LVL0_CPU0_CPU_THROT_HEAVY
 
- THERMCTL_LVL0_CPU0_CPU_THROT_LIGHT
 
- THERMCTL_LVL0_CPU0_CPU_THROT_MASK
 
- THERMCTL_LVL0_CPU0_EN_MASK
 
- THERMCTL_LVL0_CPU0_GPU_THROT_HEAVY
 
- THERMCTL_LVL0_CPU0_GPU_THROT_LIGHT
 
- THERMCTL_LVL0_CPU0_GPU_THROT_MASK
 
- THERMCTL_LVL0_CPU0_MEM_THROT_MASK
 
- THERMCTL_LVL0_CPU0_STATUS_MASK
 
- THERMCTL_LVL0_DN_STATS
 
- THERMCTL_LVL0_UP_STATS
 
- THERMCTL_LVL_REG
 
- THERMCTL_LVL_REGS_SIZE
 
- THERMCTL_STATS_CTL
 
- THERMCTL_THERMTRIP_CTL
 
- THERMISTOR_MODE
 
- THERMOCOUPLE_TYPE_B
 
- THERMOCOUPLE_TYPE_E
 
- THERMOCOUPLE_TYPE_J
 
- THERMOCOUPLE_TYPE_K
 
- THERMOCOUPLE_TYPE_N
 
- THERMOCOUPLE_TYPE_R
 
- THERMOCOUPLE_TYPE_S
 
- THERMOCOUPLE_TYPE_T
 
- THERM_FAILURE
 
- THERM_INC_CLK
 
- THERM_INTH_MASK
 
- THERM_INTL_MASK
 
- THERM_INT_HIGH_ENABLE
 
- THERM_INT_LOW_ENABLE
 
- THERM_INT_MASK_HIGH
 
- THERM_INT_MASK_LOW
 
- THERM_INT_PLN_ENABLE
 
- THERM_INT_THRESHOLD0_ENABLE
 
- THERM_INT_THRESHOLD1_ENABLE
 
- THERM_IRQ_CPU_MASK
 
- THERM_IRQ_GPU_MASK
 
- THERM_IRQ_MEM_MASK
 
- THERM_IRQ_TSENSE_MASK
 
- THERM_LOG_THRESHOLD0
 
- THERM_LOG_THRESHOLD1
 
- THERM_MASK_THRESHOLD0
 
- THERM_MASK_THRESHOLD1
 
- THERM_READ_CONFIG
 
- THERM_READ_TEMP
 
- THERM_READ_TH
 
- THERM_READ_TL
 
- THERM_REFCNT
 
- THERM_RESET
 
- THERM_RSVD1_MASK
 
- THERM_RSVD1_SHIFT
 
- THERM_SHIFT_THRESHOLD0
 
- THERM_SHIFT_THRESHOLD1
 
- THERM_START_CONVERT
 
- THERM_STATUS_POWER_LIMIT
 
- THERM_STATUS_PROCHOT
 
- THERM_STATUS_THRESHOLD0
 
- THERM_STATUS_THRESHOLD1
 
- THERM_THERM_HDSEL_MASK
 
- THERM_THERM_HDSEL_SHIFT
 
- THERM_THERM_HD_MASK
 
- THERM_THERM_HD_SHIFT
 
- THERM_THERM_STATE_MASK
 
- THERM_THERM_STATE_SHIFT
 
- THERM_THERM_TS_MASK
 
- THERM_THERM_TS_SHIFT
 
- THERM_UNIT_ATTRS
 
- THERM_USE_PROC
 
- THERM_WRITE_CONFIG
 
- THERM_WRITE_TH
 
- THERM_WRITE_TL
 
- THETA_RF
 
- THE_NILFS_DISCONTINUED
 
- THE_NILFS_FNS
 
- THE_NILFS_GC_RUNNING
 
- THE_NILFS_INIT
 
- THE_NILFS_SB_DIRTY
 
- THE_RXD_MARK
 
- THICK_MICRO_TILING
 
- THINGM
 
- THINKPAD_BD_DATA
 
- THIN_FEATURE_COMPAT_RO_SUPP
 
- THIN_FEATURE_COMPAT_SUPP
 
- THIN_FEATURE_INCOMPAT_SUPP
 
- THIN_INTERRUPT
 
- THIN_MAX_CONCURRENT_LOCKS
 
- THIN_METADATA_BLOCK_SIZE
 
- THIN_METADATA_MAX_SECTORS
 
- THIN_METADATA_MAX_SECTORS_WARNING
 
- THIN_METADATA_NEEDS_CHECK_FLAG
 
- THIN_MICRO_TILING
 
- THIN_SUPERBLOCK_LOCATION
 
- THIN_SUPERBLOCK_MAGIC
 
- THIN_VERSION
 
- THIRD_NIC_PRESENT
 
- THIRD_OPERAND_REG
 
- THIRD_PAGE_GROUP_END
 
- THIRD_PAGE_GROUP_SIZE
 
- THIRD_PAGE_GROUP_START
 
- THIRD_PARTY_COPY_IN
 
- THIRD_PARTY_COPY_OUT
 
- THIRTY_TWO_PIPES
 
- THISCPU
 
- THIS_CPU
 
- THIS_CPU_ADD_HELPER
 
- THIS_CPU_user_pcid_flush_mask
 
- THIS_MODULE
 
- THI_MAL_DIS_Q_FAULT
 
- THI_NO_FAULT
 
- THLD_RX_FULL
 
- THLD_RX_FULL_MASK
 
- THLD_TX_EMPTY
 
- THLD_TX_EMPTY_SHIFT
 
- THMC50_REG_ANALOG_OUT
 
- THMC50_REG_COMPANY_ID
 
- THMC50_REG_CONF
 
- THMC50_REG_CONF_PROGRAMMED
 
- THMC50_REG_CONF_nFANOFF
 
- THMC50_REG_DIE_CODE
 
- THMC50_REG_INTR
 
- THM_11_0__SRCID__THM_DIG_THERM_H2L
 
- THM_11_0__SRCID__THM_DIG_THERM_L2H
 
- THM_9_0__SRCID__THM_DIG_THERM_H2L
 
- THM_9_0__SRCID__THM_DIG_THERM_L2H
 
- THM_AE
 
- THM_ATR
 
- THM_BACO_CNTL__BACO_AEB_ISO_EN_MASK
 
- THM_BACO_CNTL__BACO_AEB_ISO_EN__SHIFT
 
- THM_BACO_CNTL__BACO_ANA_ISO_EN_MASK
 
- THM_BACO_CNTL__BACO_ANA_ISO_EN__SHIFT
 
- THM_BACO_CNTL__BACO_EXIT_MASK
 
- THM_BACO_CNTL__BACO_EXIT__SHIFT
 
- THM_BACO_CNTL__BACO_ISO_EN_MASK
 
- THM_BACO_CNTL__BACO_ISO_EN__SHIFT
 
- THM_BACO_CNTL__BACO_MODE_MASK
 
- THM_BACO_CNTL__BACO_MODE__SHIFT
 
- THM_BACO_CNTL__BACO_PWROKRAW_CNTL_MASK
 
- THM_BACO_CNTL__BACO_PWROKRAW_CNTL__SHIFT
 
- THM_BACO_CNTL__BACO_RESET_EN_MASK
 
- THM_BACO_CNTL__BACO_RESET_EN__SHIFT
 
- THM_BACO_CNTL__BACO_SB_AXI_FENCE_MASK
 
- THM_BACO_CNTL__BACO_SB_AXI_FENCE__SHIFT
 
- THM_BACO_CNTL__BACO_SMNCLK_MUX_MASK
 
- THM_BACO_CNTL__BACO_SMNCLK_MUX__SHIFT
 
- THM_BACO_CNTL__BACO_SOC_REFCLK_OFF_MASK
 
- THM_BACO_CNTL__BACO_SOC_REFCLK_OFF__SHIFT
 
- THM_BACO_CNTL__BACO_SOC_VDCI_RESET_MASK
 
- THM_BACO_CNTL__BACO_SOC_VDCI_RESET__SHIFT
 
- THM_BACO_CNTL__SOC_DOMAIN_IDLE_MASK
 
- THM_BACO_CNTL__SOC_DOMAIN_IDLE__SHIFT
 
- THM_BACO_TIMING0__BACO_ISO_EXIT_CNT_MASK
 
- THM_BACO_TIMING0__BACO_ISO_EXIT_CNT__SHIFT
 
- THM_BACO_TIMING0__BACO_PWROKRAW_EXIT_CNT_MASK
 
- THM_BACO_TIMING0__BACO_PWROKRAW_EXIT_CNT__SHIFT
 
- THM_BACO_TIMING0__BACO_RESET_EXIT_CNT_MASK
 
- THM_BACO_TIMING0__BACO_RESET_EXIT_CNT__SHIFT
 
- THM_BACO_TIMING0__BACO_VDCI_RESET_EXIT_CNT_MASK
 
- THM_BACO_TIMING0__BACO_VDCI_RESET_EXIT_CNT__SHIFT
 
- THM_BACO_TIMING1__BACO_FENCE_EXIT_CNT_MASK
 
- THM_BACO_TIMING1__BACO_FENCE_EXIT_CNT__SHIFT
 
- THM_BACO_TIMING1__BACO_MODE_EXIT_CNT_MASK
 
- THM_BACO_TIMING1__BACO_MODE_EXIT_CNT__SHIFT
 
- THM_BACO_TIMING1__BACO_REFCLK_EXIT_CNT_MASK
 
- THM_BACO_TIMING1__BACO_REFCLK_EXIT_CNT__SHIFT
 
- THM_BACO_TIMING1__BACO_SMNCLK_EXIT_CNT_MASK
 
- THM_BACO_TIMING1__BACO_SMNCLK_EXIT_CNT__SHIFT
 
- THM_BACO_TIMING2__BACO_AEB_ISO_EXIT_CNT_MASK
 
- THM_BACO_TIMING2__BACO_AEB_ISO_EXIT_CNT__SHIFT
 
- THM_BACO_TIMING2__BACO_ANA_ISO_EXIT_CNT_MASK
 
- THM_BACO_TIMING2__BACO_ANA_ISO_EXIT_CNT__SHIFT
 
- THM_BACO_TIMING2__BACO_EXIT_CNT_MASK
 
- THM_BACO_TIMING2__BACO_EXIT_CNT__SHIFT
 
- THM_BACO_TIMING__BACO_RESET_DELAY_MASK
 
- THM_BACO_TIMING__BACO_RESET_DELAY__SHIFT
 
- THM_BASE__INST0_SEG0
 
- THM_BASE__INST0_SEG1
 
- THM_BASE__INST0_SEG2
 
- THM_BASE__INST0_SEG3
 
- THM_BASE__INST0_SEG4
 
- THM_BASE__INST0_SEG5
 
- THM_BASE__INST1_SEG0
 
- THM_BASE__INST1_SEG1
 
- THM_BASE__INST1_SEG2
 
- THM_BASE__INST1_SEG3
 
- THM_BASE__INST1_SEG4
 
- THM_BASE__INST1_SEG5
 
- THM_BASE__INST2_SEG0
 
- THM_BASE__INST2_SEG1
 
- THM_BASE__INST2_SEG2
 
- THM_BASE__INST2_SEG3
 
- THM_BASE__INST2_SEG4
 
- THM_BASE__INST2_SEG5
 
- THM_BASE__INST3_SEG0
 
- THM_BASE__INST3_SEG1
 
- THM_BASE__INST3_SEG2
 
- THM_BASE__INST3_SEG3
 
- THM_BASE__INST3_SEG4
 
- THM_BASE__INST3_SEG5
 
- THM_BASE__INST4_SEG0
 
- THM_BASE__INST4_SEG1
 
- THM_BASE__INST4_SEG2
 
- THM_BASE__INST4_SEG3
 
- THM_BASE__INST4_SEG4
 
- THM_BASE__INST4_SEG5
 
- THM_BASE__INST5_SEG0
 
- THM_BASE__INST5_SEG1
 
- THM_BASE__INST5_SEG2
 
- THM_BASE__INST5_SEG3
 
- THM_BASE__INST5_SEG4
 
- THM_BASE__INST5_SEG5
 
- THM_BASE__INST6_SEG0
 
- THM_BASE__INST6_SEG1
 
- THM_BASE__INST6_SEG2
 
- THM_BASE__INST6_SEG3
 
- THM_BASE__INST6_SEG4
 
- THM_BASE__INST6_SEG5
 
- THM_BASE__INST7_SEG0
 
- THM_BASE__INST7_SEG1
 
- THM_BASE__INST7_SEG2
 
- THM_BASE__INST7_SEG3
 
- THM_BASE__INST7_SEG4
 
- THM_BASE__INST7_SEG5
 
- THM_CEC
 
- THM_CFG_TBAR
 
- THM_CFG_TBAR_HI
 
- THM_CLK_CNTL
 
- THM_CLK_CNTL__CMON_CLK_SEL_MASK
 
- THM_CLK_CNTL__CMON_CLK_SEL__SHIFT
 
- THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK
 
- THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT
 
- THM_CLK_CNTL__TMON_CLK_SEL_MASK
 
- THM_CLK_CNTL__TMON_CLK_SEL__SHIFT
 
- THM_CTA
 
- THM_CTF_DELAY__CTF_DELAY_CNT_MASK
 
- THM_CTF_DELAY__CTF_DELAY_CNT__SHIFT
 
- THM_CTV1
 
- THM_CTV2
 
- THM_DIE1_TEMP__TEMP_MASK
 
- THM_DIE1_TEMP__TEMP__SHIFT
 
- THM_DIE1_TEMP__VALID_MASK
 
- THM_DIE1_TEMP__VALID__SHIFT
 
- THM_DIE2_TEMP__TEMP_MASK
 
- THM_DIE2_TEMP__TEMP__SHIFT
 
- THM_DIE2_TEMP__VALID_MASK
 
- THM_DIE2_TEMP__VALID__SHIFT
 
- THM_DIE3_TEMP__TEMP_MASK
 
- THM_DIE3_TEMP__TEMP__SHIFT
 
- THM_DIE3_TEMP__VALID_MASK
 
- THM_DIE3_TEMP__VALID__SHIFT
 
- THM_DTV
 
- THM_DUMPL
 
- THM_DUMPQ
 
- THM_DUMPW
 
- THM_FUSE0__FUSE_TconZtValue_MASK
 
- THM_FUSE0__FUSE_TconZtValue__SHIFT
 
- THM_FUSE0__FUSE_TmonBGAdj0_MASK
 
- THM_FUSE0__FUSE_TmonBGAdj0__SHIFT
 
- THM_FUSE0__FUSE_TmonBGAdj1_MASK
 
- THM_FUSE0__FUSE_TmonBGAdj1__SHIFT
 
- THM_FUSE0__FUSE_TmonClkDiv_MASK
 
- THM_FUSE0__FUSE_TmonClkDiv__SHIFT
 
- THM_FUSE0__FUSE_TmonForceMaxAcq_MASK
 
- THM_FUSE0__FUSE_TmonForceMaxAcq__SHIFT
 
- THM_FUSE0__FUSE_TmonNumAcq_MASK
 
- THM_FUSE0__FUSE_TmonNumAcq__SHIFT
 
- THM_FUSE0__FUSE_TmonRsInterleave_MASK
 
- THM_FUSE0__FUSE_TmonRsInterleave__SHIFT
 
- THM_FUSE10__FUSE_HtcClkAct_MASK
 
- THM_FUSE10__FUSE_HtcClkAct__SHIFT
 
- THM_FUSE10__FUSE_HtcClkInact_MASK
 
- THM_FUSE10__FUSE_HtcClkInact__SHIFT
 
- THM_FUSE10__FUSE_HtcDis_MASK
 
- THM_FUSE10__FUSE_HtcDis__SHIFT
 
- THM_FUSE10__FUSE_UnusedBits_MASK
 
- THM_FUSE10__FUSE_UnusedBits__SHIFT
 
- THM_FUSE11__PA_SPARE_MASK
 
- THM_FUSE11__PA_SPARE__SHIFT
 
- THM_FUSE12__FusesValid_MASK
 
- THM_FUSE12__FusesValid__SHIFT
 
- THM_FUSE1__FUSE_TconDtValue30_MASK
 
- THM_FUSE1__FUSE_TconDtValue30__SHIFT
 
- THM_FUSE1__FUSE_TconDtValue31_MASK
 
- THM_FUSE1__FUSE_TconDtValue31__SHIFT
 
- THM_FUSE1__FUSE_TconKValue_MASK
 
- THM_FUSE1__FUSE_TconKValue__SHIFT
 
- THM_FUSE1__FUSE_TconPwrDnDelaySlope_MASK
 
- THM_FUSE1__FUSE_TconPwrDnDelaySlope__SHIFT
 
- THM_FUSE1__FUSE_TconPwrDnMaxDelayMult_MASK
 
- THM_FUSE1__FUSE_TconPwrDnMaxDelayMult__SHIFT
 
- THM_FUSE1__FUSE_TconPwrDnMinDelay_MASK
 
- THM_FUSE1__FUSE_TconPwrDnMinDelay__SHIFT
 
- THM_FUSE1__FUSE_TconPwrDnNumSensors_MASK
 
- THM_FUSE1__FUSE_TconPwrDnNumSensors__SHIFT
 
- THM_FUSE1__FUSE_TconPwrDnTmpLmt_MASK
 
- THM_FUSE1__FUSE_TconPwrDnTmpLmt__SHIFT
 
- THM_FUSE1__FUSE_TconPwrUpStaggerTime_MASK
 
- THM_FUSE1__FUSE_TconPwrUpStaggerTime__SHIFT
 
- THM_FUSE1__FUSE_TconTmpAdjLoRes_MASK
 
- THM_FUSE1__FUSE_TconTmpAdjLoRes__SHIFT
 
- THM_FUSE1__FUSE_TconUseSecondary_MASK
 
- THM_FUSE1__FUSE_TconUseSecondary__SHIFT
 
- THM_FUSE1__FUSE_TconZtValue_MASK
 
- THM_FUSE1__FUSE_TconZtValue__SHIFT
 
- THM_FUSE2__FUSE_TconDtValue24_MASK
 
- THM_FUSE2__FUSE_TconDtValue24__SHIFT
 
- THM_FUSE2__FUSE_TconDtValue25_MASK
 
- THM_FUSE2__FUSE_TconDtValue25__SHIFT
 
- THM_FUSE2__FUSE_TconDtValue26_MASK
 
- THM_FUSE2__FUSE_TconDtValue26__SHIFT
 
- THM_FUSE2__FUSE_TconDtValue27_MASK
 
- THM_FUSE2__FUSE_TconDtValue27__SHIFT
 
- THM_FUSE2__FUSE_TconDtValue28_MASK
 
- THM_FUSE2__FUSE_TconDtValue28__SHIFT
 
- THM_FUSE2__FUSE_TconDtValue29_MASK
 
- THM_FUSE2__FUSE_TconDtValue29__SHIFT
 
- THM_FUSE2__FUSE_TconDtValue30_MASK
 
- THM_FUSE2__FUSE_TconDtValue30__SHIFT
 
- THM_FUSE3__FUSE_TconDtValue19_MASK
 
- THM_FUSE3__FUSE_TconDtValue19__SHIFT
 
- THM_FUSE3__FUSE_TconDtValue20_MASK
 
- THM_FUSE3__FUSE_TconDtValue20__SHIFT
 
- THM_FUSE3__FUSE_TconDtValue21_MASK
 
- THM_FUSE3__FUSE_TconDtValue21__SHIFT
 
- THM_FUSE3__FUSE_TconDtValue22_MASK
 
- THM_FUSE3__FUSE_TconDtValue22__SHIFT
 
- THM_FUSE3__FUSE_TconDtValue23_MASK
 
- THM_FUSE3__FUSE_TconDtValue23__SHIFT
 
- THM_FUSE3__FUSE_TconDtValue24_MASK
 
- THM_FUSE3__FUSE_TconDtValue24__SHIFT
 
- THM_FUSE4__FUSE_TconDtValue14_MASK
 
- THM_FUSE4__FUSE_TconDtValue14__SHIFT
 
- THM_FUSE4__FUSE_TconDtValue15_MASK
 
- THM_FUSE4__FUSE_TconDtValue15__SHIFT
 
- THM_FUSE4__FUSE_TconDtValue16_MASK
 
- THM_FUSE4__FUSE_TconDtValue16__SHIFT
 
- THM_FUSE4__FUSE_TconDtValue17_MASK
 
- THM_FUSE4__FUSE_TconDtValue17__SHIFT
 
- THM_FUSE4__FUSE_TconDtValue18_MASK
 
- THM_FUSE4__FUSE_TconDtValue18__SHIFT
 
- THM_FUSE4__FUSE_TconDtValue19_MASK
 
- THM_FUSE4__FUSE_TconDtValue19__SHIFT
 
- THM_FUSE5__FUSE_TconDtValue10_MASK
 
- THM_FUSE5__FUSE_TconDtValue10__SHIFT
 
- THM_FUSE5__FUSE_TconDtValue11_MASK
 
- THM_FUSE5__FUSE_TconDtValue11__SHIFT
 
- THM_FUSE5__FUSE_TconDtValue12_MASK
 
- THM_FUSE5__FUSE_TconDtValue12__SHIFT
 
- THM_FUSE5__FUSE_TconDtValue13_MASK
 
- THM_FUSE5__FUSE_TconDtValue13__SHIFT
 
- THM_FUSE5__FUSE_TconDtValue14_MASK
 
- THM_FUSE5__FUSE_TconDtValue14__SHIFT
 
- THM_FUSE5__FUSE_TconDtValue8_MASK
 
- THM_FUSE5__FUSE_TconDtValue8__SHIFT
 
- THM_FUSE5__FUSE_TconDtValue9_MASK
 
- THM_FUSE5__FUSE_TconDtValue9__SHIFT
 
- THM_FUSE6__FUSE_TconDtValue3_MASK
 
- THM_FUSE6__FUSE_TconDtValue3__SHIFT
 
- THM_FUSE6__FUSE_TconDtValue4_MASK
 
- THM_FUSE6__FUSE_TconDtValue4__SHIFT
 
- THM_FUSE6__FUSE_TconDtValue5_MASK
 
- THM_FUSE6__FUSE_TconDtValue5__SHIFT
 
- THM_FUSE6__FUSE_TconDtValue6_MASK
 
- THM_FUSE6__FUSE_TconDtValue6__SHIFT
 
- THM_FUSE6__FUSE_TconDtValue7_MASK
 
- THM_FUSE6__FUSE_TconDtValue7__SHIFT
 
- THM_FUSE6__FUSE_TconDtValue8_MASK
 
- THM_FUSE6__FUSE_TconDtValue8__SHIFT
 
- THM_FUSE7__FUSE_TconCtValue1_MASK
 
- THM_FUSE7__FUSE_TconCtValue1__SHIFT
 
- THM_FUSE7__FUSE_TconDtValue0_MASK
 
- THM_FUSE7__FUSE_TconDtValue0__SHIFT
 
- THM_FUSE7__FUSE_TconDtValue1_MASK
 
- THM_FUSE7__FUSE_TconDtValue1__SHIFT
 
- THM_FUSE7__FUSE_TconDtValue2_MASK
 
- THM_FUSE7__FUSE_TconDtValue2__SHIFT
 
- THM_FUSE7__FUSE_TconDtValue3_MASK
 
- THM_FUSE7__FUSE_TconDtValue3__SHIFT
 
- THM_FUSE8__FUSE_TconAtValue0_MASK
 
- THM_FUSE8__FUSE_TconAtValue0__SHIFT
 
- THM_FUSE8__FUSE_TconAtValue1_MASK
 
- THM_FUSE8__FUSE_TconAtValue1__SHIFT
 
- THM_FUSE8__FUSE_TconBootDelay_MASK
 
- THM_FUSE8__FUSE_TconBootDelay__SHIFT
 
- THM_FUSE8__FUSE_TconBtValue_MASK
 
- THM_FUSE8__FUSE_TconBtValue__SHIFT
 
- THM_FUSE8__FUSE_TconCtValue0_MASK
 
- THM_FUSE8__FUSE_TconCtValue0__SHIFT
 
- THM_FUSE9__FUSE_HtcHystLmt_MASK
 
- THM_FUSE9__FUSE_HtcHystLmt__SHIFT
 
- THM_FUSE9__FUSE_HtcMsrLock_MASK
 
- THM_FUSE9__FUSE_HtcMsrLock__SHIFT
 
- THM_FUSE9__FUSE_HtcTmpLmt_MASK
 
- THM_FUSE9__FUSE_HtcTmpLmt__SHIFT
 
- THM_FUSE9__FUSE_TconAtValue0_MASK
 
- THM_FUSE9__FUSE_TconAtValue0__SHIFT
 
- THM_FUSE9__FUSE_ThermTripEn_MASK
 
- THM_FUSE9__FUSE_ThermTripEn__SHIFT
 
- THM_FUSE9__FUSE_ThermTripLimit_MASK
 
- THM_FUSE9__FUSE_ThermTripLimit__SHIFT
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_A_MASK
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_A_OVERRIDE_MASK
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_A_OVERRIDE__SHIFT
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_A__SHIFT
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_MASK
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_OVERRIDE_MASK
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_OVERRIDE__SHIFT
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_OE__SHIFT
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_PD_MASK
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_PD__SHIFT
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_PU_MASK
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_PU__SHIFT
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_RXEN_MASK
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_RXEN__SHIFT
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL0_MASK
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL0__SHIFT
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL1_MASK
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL1__SHIFT
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_S0_MASK
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_S0__SHIFT
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_S1_MASK
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_S1__SHIFT
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_SCHMEN_MASK
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_SCHMEN__SHIFT
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_TXIMPSEL_MASK
 
- THM_GPIO_MACO_EN_CTRL__MACO_EN_TXIMPSEL__SHIFT
 
- THM_GPIO_MACO_EN_CTRL__Y_MASK
 
- THM_GPIO_MACO_EN_CTRL__Y__SHIFT
 
- THM_GPIO_PROCHOT_CTRL__A_MASK
 
- THM_GPIO_PROCHOT_CTRL__A_OVERRIDE_MASK
 
- THM_GPIO_PROCHOT_CTRL__A_OVERRIDE__SHIFT
 
- THM_GPIO_PROCHOT_CTRL__A__SHIFT
 
- THM_GPIO_PROCHOT_CTRL__OE_MASK
 
- THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE_MASK
 
- THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE__SHIFT
 
- THM_GPIO_PROCHOT_CTRL__OE__SHIFT
 
- THM_GPIO_PROCHOT_CTRL__PD_MASK
 
- THM_GPIO_PROCHOT_CTRL__PD__SHIFT
 
- THM_GPIO_PROCHOT_CTRL__PU_MASK
 
- THM_GPIO_PROCHOT_CTRL__PU__SHIFT
 
- THM_GPIO_PROCHOT_CTRL__RXEN_MASK
 
- THM_GPIO_PROCHOT_CTRL__RXEN__SHIFT
 
- THM_GPIO_PROCHOT_CTRL__RXSEL0_MASK
 
- THM_GPIO_PROCHOT_CTRL__RXSEL0__SHIFT
 
- THM_GPIO_PROCHOT_CTRL__RXSEL1_MASK
 
- THM_GPIO_PROCHOT_CTRL__RXSEL1__SHIFT
 
- THM_GPIO_PROCHOT_CTRL__S0_MASK
 
- THM_GPIO_PROCHOT_CTRL__S0__SHIFT
 
- THM_GPIO_PROCHOT_CTRL__S1_MASK
 
- THM_GPIO_PROCHOT_CTRL__S1__SHIFT
 
- THM_GPIO_PROCHOT_CTRL__SCHMEN_MASK
 
- THM_GPIO_PROCHOT_CTRL__SCHMEN__SHIFT
 
- THM_GPIO_PROCHOT_CTRL__SN_MASK
 
- THM_GPIO_PROCHOT_CTRL__SN__SHIFT
 
- THM_GPIO_PROCHOT_CTRL__TX12_EN_MASK
 
- THM_GPIO_PROCHOT_CTRL__TX12_EN__SHIFT
 
- THM_GPIO_PROCHOT_CTRL__TXIMPSEL_MASK
 
- THM_GPIO_PROCHOT_CTRL__TXIMPSEL__SHIFT
 
- THM_GPIO_PROCHOT_CTRL__Y_MASK
 
- THM_GPIO_PROCHOT_CTRL__Y__SHIFT
 
- THM_GPIO_PUMPIN_CTRL__A_MASK
 
- THM_GPIO_PUMPIN_CTRL__A_OVERRIDE_MASK
 
- THM_GPIO_PUMPIN_CTRL__A_OVERRIDE__SHIFT
 
- THM_GPIO_PUMPIN_CTRL__A__SHIFT
 
- THM_GPIO_PUMPIN_CTRL__OE_MASK
 
- THM_GPIO_PUMPIN_CTRL__OE_OVERRIDE_MASK
 
- THM_GPIO_PUMPIN_CTRL__OE_OVERRIDE__SHIFT
 
- THM_GPIO_PUMPIN_CTRL__OE__SHIFT
 
- THM_GPIO_PUMPIN_CTRL__PD_MASK
 
- THM_GPIO_PUMPIN_CTRL__PD__SHIFT
 
- THM_GPIO_PUMPIN_CTRL__PU_MASK
 
- THM_GPIO_PUMPIN_CTRL__PU__SHIFT
 
- THM_GPIO_PUMPIN_CTRL__RXEN_MASK
 
- THM_GPIO_PUMPIN_CTRL__RXEN__SHIFT
 
- THM_GPIO_PUMPIN_CTRL__RXSEL0_MASK
 
- THM_GPIO_PUMPIN_CTRL__RXSEL0__SHIFT
 
- THM_GPIO_PUMPIN_CTRL__RXSEL1_MASK
 
- THM_GPIO_PUMPIN_CTRL__RXSEL1__SHIFT
 
- THM_GPIO_PUMPIN_CTRL__S0_MASK
 
- THM_GPIO_PUMPIN_CTRL__S0__SHIFT
 
- THM_GPIO_PUMPIN_CTRL__S1_MASK
 
- THM_GPIO_PUMPIN_CTRL__S1__SHIFT
 
- THM_GPIO_PUMPIN_CTRL__SCHMEN_MASK
 
- THM_GPIO_PUMPIN_CTRL__SCHMEN__SHIFT
 
- THM_GPIO_PUMPIN_CTRL__TXIMPSEL_MASK
 
- THM_GPIO_PUMPIN_CTRL__TXIMPSEL__SHIFT
 
- THM_GPIO_PUMPIN_CTRL__Y_MASK
 
- THM_GPIO_PUMPIN_CTRL__Y__SHIFT
 
- THM_GPIO_PUMPOUT_CTRL__A_MASK
 
- THM_GPIO_PUMPOUT_CTRL__A_OVERRIDE_MASK
 
- THM_GPIO_PUMPOUT_CTRL__A_OVERRIDE__SHIFT
 
- THM_GPIO_PUMPOUT_CTRL__A__SHIFT
 
- THM_GPIO_PUMPOUT_CTRL__OE_MASK
 
- THM_GPIO_PUMPOUT_CTRL__OE_OVERRIDE_MASK
 
- THM_GPIO_PUMPOUT_CTRL__OE_OVERRIDE__SHIFT
 
- THM_GPIO_PUMPOUT_CTRL__OE__SHIFT
 
- THM_GPIO_PUMPOUT_CTRL__PD_MASK
 
- THM_GPIO_PUMPOUT_CTRL__PD__SHIFT
 
- THM_GPIO_PUMPOUT_CTRL__PU_MASK
 
- THM_GPIO_PUMPOUT_CTRL__PU__SHIFT
 
- THM_GPIO_PUMPOUT_CTRL__RXEN_MASK
 
- THM_GPIO_PUMPOUT_CTRL__RXEN__SHIFT
 
- THM_GPIO_PUMPOUT_CTRL__RXSEL0_MASK
 
- THM_GPIO_PUMPOUT_CTRL__RXSEL0__SHIFT
 
- THM_GPIO_PUMPOUT_CTRL__RXSEL1_MASK
 
- THM_GPIO_PUMPOUT_CTRL__RXSEL1__SHIFT
 
- THM_GPIO_PUMPOUT_CTRL__S0_MASK
 
- THM_GPIO_PUMPOUT_CTRL__S0__SHIFT
 
- THM_GPIO_PUMPOUT_CTRL__S1_MASK
 
- THM_GPIO_PUMPOUT_CTRL__S1__SHIFT
 
- THM_GPIO_PUMPOUT_CTRL__SCHMEN_MASK
 
- THM_GPIO_PUMPOUT_CTRL__SCHMEN__SHIFT
 
- THM_GPIO_PUMPOUT_CTRL__TXIMPSEL_MASK
 
- THM_GPIO_PUMPOUT_CTRL__TXIMPSEL__SHIFT
 
- THM_GPIO_PUMPOUT_CTRL__Y_MASK
 
- THM_GPIO_PUMPOUT_CTRL__Y__SHIFT
 
- THM_GPIO_PWM_CTRL__A_MASK
 
- THM_GPIO_PWM_CTRL__A_OVERRIDE_MASK
 
- THM_GPIO_PWM_CTRL__A_OVERRIDE__SHIFT
 
- THM_GPIO_PWM_CTRL__A__SHIFT
 
- THM_GPIO_PWM_CTRL__OE_MASK
 
- THM_GPIO_PWM_CTRL__OE_OVERRIDE_MASK
 
- THM_GPIO_PWM_CTRL__OE_OVERRIDE__SHIFT
 
- THM_GPIO_PWM_CTRL__OE__SHIFT
 
- THM_GPIO_PWM_CTRL__PD_MASK
 
- THM_GPIO_PWM_CTRL__PD__SHIFT
 
- THM_GPIO_PWM_CTRL__PU_MASK
 
- THM_GPIO_PWM_CTRL__PU__SHIFT
 
- THM_GPIO_PWM_CTRL__RXEN_MASK
 
- THM_GPIO_PWM_CTRL__RXEN__SHIFT
 
- THM_GPIO_PWM_CTRL__RXSEL0_MASK
 
- THM_GPIO_PWM_CTRL__RXSEL0__SHIFT
 
- THM_GPIO_PWM_CTRL__RXSEL1_MASK
 
- THM_GPIO_PWM_CTRL__RXSEL1__SHIFT
 
- THM_GPIO_PWM_CTRL__S0_MASK
 
- THM_GPIO_PWM_CTRL__S0__SHIFT
 
- THM_GPIO_PWM_CTRL__S1_MASK
 
- THM_GPIO_PWM_CTRL__S1__SHIFT
 
- THM_GPIO_PWM_CTRL__SCHMEN_MASK
 
- THM_GPIO_PWM_CTRL__SCHMEN__SHIFT
 
- THM_GPIO_PWM_CTRL__TXIMPSEL_MASK
 
- THM_GPIO_PWM_CTRL__TXIMPSEL__SHIFT
 
- THM_GPIO_PWM_CTRL__Y_MASK
 
- THM_GPIO_PWM_CTRL__Y__SHIFT
 
- THM_GPIO_TACHIN_CTRL__A_MASK
 
- THM_GPIO_TACHIN_CTRL__A_OVERRIDE_MASK
 
- THM_GPIO_TACHIN_CTRL__A_OVERRIDE__SHIFT
 
- THM_GPIO_TACHIN_CTRL__A__SHIFT
 
- THM_GPIO_TACHIN_CTRL__OE_MASK
 
- THM_GPIO_TACHIN_CTRL__OE_OVERRIDE_MASK
 
- THM_GPIO_TACHIN_CTRL__OE_OVERRIDE__SHIFT
 
- THM_GPIO_TACHIN_CTRL__OE__SHIFT
 
- THM_GPIO_TACHIN_CTRL__PD_MASK
 
- THM_GPIO_TACHIN_CTRL__PD__SHIFT
 
- THM_GPIO_TACHIN_CTRL__PU_MASK
 
- THM_GPIO_TACHIN_CTRL__PU__SHIFT
 
- THM_GPIO_TACHIN_CTRL__RXEN_MASK
 
- THM_GPIO_TACHIN_CTRL__RXEN__SHIFT
 
- THM_GPIO_TACHIN_CTRL__RXSEL0_MASK
 
- THM_GPIO_TACHIN_CTRL__RXSEL0__SHIFT
 
- THM_GPIO_TACHIN_CTRL__RXSEL1_MASK
 
- THM_GPIO_TACHIN_CTRL__RXSEL1__SHIFT
 
- THM_GPIO_TACHIN_CTRL__S0_MASK
 
- THM_GPIO_TACHIN_CTRL__S0__SHIFT
 
- THM_GPIO_TACHIN_CTRL__S1_MASK
 
- THM_GPIO_TACHIN_CTRL__S1__SHIFT
 
- THM_GPIO_TACHIN_CTRL__SCHMEN_MASK
 
- THM_GPIO_TACHIN_CTRL__SCHMEN__SHIFT
 
- THM_GPIO_TACHIN_CTRL__TXIMPSEL_MASK
 
- THM_GPIO_TACHIN_CTRL__TXIMPSEL__SHIFT
 
- THM_GPIO_TACHIN_CTRL__Y_MASK
 
- THM_GPIO_TACHIN_CTRL__Y__SHIFT
 
- THM_GPIO_THERMTRIP_CTRL__A_MASK
 
- THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE_MASK
 
- THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE__SHIFT
 
- THM_GPIO_THERMTRIP_CTRL__A__SHIFT
 
- THM_GPIO_THERMTRIP_CTRL__CTFEN_MASK
 
- THM_GPIO_THERMTRIP_CTRL__CTFEN__SHIFT
 
- THM_GPIO_THERMTRIP_CTRL__OE_MASK
 
- THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE_MASK
 
- THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE__SHIFT
 
- THM_GPIO_THERMTRIP_CTRL__OE__SHIFT
 
- THM_GPIO_THERMTRIP_CTRL__PD_MASK
 
- THM_GPIO_THERMTRIP_CTRL__PD__SHIFT
 
- THM_GPIO_THERMTRIP_CTRL__PU_MASK
 
- THM_GPIO_THERMTRIP_CTRL__PU__SHIFT
 
- THM_GPIO_THERMTRIP_CTRL__RXEN_MASK
 
- THM_GPIO_THERMTRIP_CTRL__RXEN__SHIFT
 
- THM_GPIO_THERMTRIP_CTRL__RXSEL0_MASK
 
- THM_GPIO_THERMTRIP_CTRL__RXSEL0__SHIFT
 
- THM_GPIO_THERMTRIP_CTRL__RXSEL1_MASK
 
- THM_GPIO_THERMTRIP_CTRL__RXSEL1__SHIFT
 
- THM_GPIO_THERMTRIP_CTRL__S0_MASK
 
- THM_GPIO_THERMTRIP_CTRL__S0__SHIFT
 
- THM_GPIO_THERMTRIP_CTRL__S1_MASK
 
- THM_GPIO_THERMTRIP_CTRL__S1__SHIFT
 
- THM_GPIO_THERMTRIP_CTRL__SCHMEN_MASK
 
- THM_GPIO_THERMTRIP_CTRL__SCHMEN__SHIFT
 
- THM_GPIO_THERMTRIP_CTRL__SN_MASK
 
- THM_GPIO_THERMTRIP_CTRL__SN__SHIFT
 
- THM_GPIO_THERMTRIP_CTRL__TX12_EN_MASK
 
- THM_GPIO_THERMTRIP_CTRL__TX12_EN__SHIFT
 
- THM_GPIO_THERMTRIP_CTRL__TXIMPSEL_MASK
 
- THM_GPIO_THERMTRIP_CTRL__TXIMPSEL__SHIFT
 
- THM_GPIO_THERMTRIP_CTRL__Y_MASK
 
- THM_GPIO_THERMTRIP_CTRL__Y__SHIFT
 
- THM_HTS
 
- THM_HTSHI
 
- THM_HWID
 
- THM_HWIP
 
- THM_ITV
 
- THM_MGTA
 
- THM_MGTV
 
- THM_MMGPC
 
- THM_MPCPC
 
- THM_MPPC
 
- THM_PPEC
 
- THM_PROFILE_MAX
 
- THM_PSC
 
- THM_PTA
 
- THM_PTL
 
- THM_PTV
 
- THM_PWRMGT__SBAXI_CLK_GATE_EN_MASK
 
- THM_PWRMGT__SBAXI_CLK_GATE_EN__SHIFT
 
- THM_PWRMGT__SBTSI_SBRMI_CLK_GATE_EN_MASK
 
- THM_PWRMGT__SBTSI_SBRMI_CLK_GATE_EN__SHIFT
 
- THM_PWRMGT__SB_CLK_GATE_MAX_CNT_MASK
 
- THM_PWRMGT__SB_CLK_GATE_MAX_CNT__SHIFT
 
- THM_SEC
 
- THM_STS
 
- THM_SW_TEMP__SW_TEMP_MASK
 
- THM_SW_TEMP__SW_TEMP__SHIFT
 
- THM_TC1
 
- THM_TC2
 
- THM_TC3
 
- THM_TCON_CSR_CONFIG__TCC_ADDR_MASK
 
- THM_TCON_CSR_CONFIG__TCC_ADDR__SHIFT
 
- THM_TCON_CSR_CONFIG__TCC_READ_OP_MASK
 
- THM_TCON_CSR_CONFIG__TCC_READ_OP__SHIFT
 
- THM_TCON_CSR_DATA__TCC_DATA_MASK
 
- THM_TCON_CSR_DATA__TCC_DATA__SHIFT
 
- THM_TCON_CSR_DATA__TCC_REQ_DONE_MASK
 
- THM_TCON_CSR_DATA__TCC_REQ_DONE__SHIFT
 
- THM_TCON_CUR_TMP__CUR_TEMP_MASK
 
- THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK
 
- THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT
 
- THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL_MASK
 
- THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT
 
- THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL_MASK
 
- THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT
 
- THM_TCON_CUR_TMP__CUR_TEMP__SHIFT
 
- THM_TCON_CUR_TMP__MCM_EN_MASK
 
- THM_TCON_CUR_TMP__MCM_EN__SHIFT
 
- THM_TCON_CUR_TMP__PER_STEP_TIME_DN_MASK
 
- THM_TCON_CUR_TMP__PER_STEP_TIME_DN__SHIFT
 
- THM_TCON_CUR_TMP__PER_STEP_TIME_UP_MASK
 
- THM_TCON_CUR_TMP__PER_STEP_TIME_UP__SHIFT
 
- THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP_MASK
 
- THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT
 
- THM_TCON_CUR_TMP__TMP_SLEW_DN_EN_MASK
 
- THM_TCON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT
 
- THM_TCON_HTC__DIS_PROCHOT_PIN_MASK
 
- THM_TCON_HTC__DIS_PROCHOT_PIN__SHIFT
 
- THM_TCON_HTC__EXTERNAL_PROCHOT_MASK
 
- THM_TCON_HTC__EXTERNAL_PROCHOT__SHIFT
 
- THM_TCON_HTC__HTC_ACTIVE_LOG_MASK
 
- THM_TCON_HTC__HTC_ACTIVE_LOG__SHIFT
 
- THM_TCON_HTC__HTC_ACTIVE_MASK
 
- THM_TCON_HTC__HTC_ACTIVE__SHIFT
 
- THM_TCON_HTC__HTC_APIC_HI_EN_MASK
 
- THM_TCON_HTC__HTC_APIC_HI_EN__SHIFT
 
- THM_TCON_HTC__HTC_APIC_LO_EN_MASK
 
- THM_TCON_HTC__HTC_APIC_LO_EN__SHIFT
 
- THM_TCON_HTC__HTC_DIAG_MASK
 
- THM_TCON_HTC__HTC_DIAG__SHIFT
 
- THM_TCON_HTC__HTC_EN_MASK
 
- THM_TCON_HTC__HTC_EN__SHIFT
 
- THM_TCON_HTC__HTC_HYST_LMT_MASK
 
- THM_TCON_HTC__HTC_HYST_LMT__SHIFT
 
- THM_TCON_HTC__HTC_PSTATE_LIMIT_MASK
 
- THM_TCON_HTC__HTC_PSTATE_LIMIT__SHIFT
 
- THM_TCON_HTC__HTC_P_STATE_EN_MASK
 
- THM_TCON_HTC__HTC_P_STATE_EN__SHIFT
 
- THM_TCON_HTC__HTC_SLEW_SEL_MASK
 
- THM_TCON_HTC__HTC_SLEW_SEL__SHIFT
 
- THM_TCON_HTC__HTC_TMP_LMT_MASK
 
- THM_TCON_HTC__HTC_TMP_LMT__SHIFT
 
- THM_TCON_HTC__HTC_TO_GNB_EN_MASK
 
- THM_TCON_HTC__HTC_TO_GNB_EN__SHIFT
 
- THM_TCON_HTC__HTC_TO_IH_EN_MASK
 
- THM_TCON_HTC__HTC_TO_IH_EN__SHIFT
 
- THM_TCON_HTC__INTERNAL_PROCHOT_MASK
 
- THM_TCON_HTC__INTERNAL_PROCHOT__SHIFT
 
- THM_TCON_HTC__PROCHOT_EVENT_SRC_MASK
 
- THM_TCON_HTC__PROCHOT_EVENT_SRC__SHIFT
 
- THM_TCON_HTC__PROCHOT_TO_GNB_EN_MASK
 
- THM_TCON_HTC__PROCHOT_TO_GNB_EN__SHIFT
 
- THM_TCON_HTC__PROCHOT_TO_IH_EN_MASK
 
- THM_TCON_HTC__PROCHOT_TO_IH_EN__SHIFT
 
- THM_TCON_HTC__RSVD0_MASK
 
- THM_TCON_HTC__RSVD0__SHIFT
 
- THM_TCON_HTC__RSVD1_MASK
 
- THM_TCON_HTC__RSVD1__SHIFT
 
- THM_TCON_HTC__RSVD2_MASK
 
- THM_TCON_HTC__RSVD2__SHIFT
 
- THM_TCON_LOCAL0__HaltPolling_MASK
 
- THM_TCON_LOCAL0__HaltPolling__SHIFT
 
- THM_TCON_LOCAL0__TMON0_PwrDn_Dis_MASK
 
- THM_TCON_LOCAL0__TMON0_PwrDn_Dis__SHIFT
 
- THM_TCON_LOCAL0__TMON1_PwrDn_Dis_MASK
 
- THM_TCON_LOCAL0__TMON1_PwrDn_Dis__SHIFT
 
- THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID_MASK
 
- THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID__SHIFT
 
- THM_TCON_LOCAL11__Tj_Max_TMON1_MASK
 
- THM_TCON_LOCAL11__Tj_Max_TMON1__SHIFT
 
- THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID_MASK
 
- THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID__SHIFT
 
- THM_TCON_LOCAL13__PowerDownTmon0_MASK
 
- THM_TCON_LOCAL13__PowerDownTmon0__SHIFT
 
- THM_TCON_LOCAL13__PowerDownTmon1_MASK
 
- THM_TCON_LOCAL13__PowerDownTmon1__SHIFT
 
- THM_TCON_LOCAL13__boot_done_MASK
 
- THM_TCON_LOCAL13__boot_done__SHIFT
 
- THM_TCON_LOCAL14__boot_done_MASK
 
- THM_TCON_LOCAL14__boot_done__SHIFT
 
- THM_TCON_LOCAL1__PowerDownTmon0_MASK
 
- THM_TCON_LOCAL1__PowerDownTmon0__SHIFT
 
- THM_TCON_LOCAL1__PowerDownTmon1_MASK
 
- THM_TCON_LOCAL1__PowerDownTmon1__SHIFT
 
- THM_TCON_LOCAL1__PwrDn_DelaySlope_MASK
 
- THM_TCON_LOCAL1__PwrDn_DelaySlope__SHIFT
 
- THM_TCON_LOCAL1__PwrDn_Limit_Temp_MASK
 
- THM_TCON_LOCAL1__PwrDn_Limit_Temp__SHIFT
 
- THM_TCON_LOCAL1__PwrDn_MinDelay_MASK
 
- THM_TCON_LOCAL1__PwrDn_MinDelay__SHIFT
 
- THM_TCON_LOCAL1__Turn_Off_TMON0_MASK
 
- THM_TCON_LOCAL1__Turn_Off_TMON0__SHIFT
 
- THM_TCON_LOCAL1__Turn_Off_TMON1_MASK
 
- THM_TCON_LOCAL1__Turn_Off_TMON1__SHIFT
 
- THM_TCON_LOCAL2__PwrDn_MaxDlyMult_MASK
 
- THM_TCON_LOCAL2__PwrDn_MaxDlyMult__SHIFT
 
- THM_TCON_LOCAL2__PwrDn_NumSensors_MASK
 
- THM_TCON_LOCAL2__PwrDn_NumSensors__SHIFT
 
- THM_TCON_LOCAL2__TMON_init_delay_MASK
 
- THM_TCON_LOCAL2__TMON_init_delay__SHIFT
 
- THM_TCON_LOCAL2__TMON_pwrup_stagger_time_MASK
 
- THM_TCON_LOCAL2__TMON_pwrup_stagger_time__SHIFT
 
- THM_TCON_LOCAL2__csrslave_use_corrected_MASK
 
- THM_TCON_LOCAL2__csrslave_use_corrected__SHIFT
 
- THM_TCON_LOCAL2__sbtsi_use_corrected_MASK
 
- THM_TCON_LOCAL2__sbtsi_use_corrected__SHIFT
 
- THM_TCON_LOCAL2__short_stagger_count_MASK
 
- THM_TCON_LOCAL2__short_stagger_count__SHIFT
 
- THM_TCON_LOCAL2__skip_scale_correction_MASK
 
- THM_TCON_LOCAL2__skip_scale_correction__SHIFT
 
- THM_TCON_LOCAL2__smu_use_corrected_MASK
 
- THM_TCON_LOCAL2__smu_use_corrected__SHIFT
 
- THM_TCON_LOCAL2__start_mission_polling_MASK
 
- THM_TCON_LOCAL2__start_mission_polling__SHIFT
 
- THM_TCON_LOCAL2__temp_read_skip_scale_MASK
 
- THM_TCON_LOCAL2__temp_read_skip_scale__SHIFT
 
- THM_TCON_LOCAL3__Global_TMAX_MASK
 
- THM_TCON_LOCAL3__Global_TMAX__SHIFT
 
- THM_TCON_LOCAL4__Global_TMAX_ID_MASK
 
- THM_TCON_LOCAL4__Global_TMAX_ID__SHIFT
 
- THM_TCON_LOCAL5__Global_TMIN_MASK
 
- THM_TCON_LOCAL5__Global_TMIN__SHIFT
 
- THM_TCON_LOCAL6__Global_TMIN_ID_MASK
 
- THM_TCON_LOCAL6__Global_TMIN_ID__SHIFT
 
- THM_TCON_LOCAL7__THERMID_MASK
 
- THM_TCON_LOCAL7__THERMID__SHIFT
 
- THM_TCON_LOCAL8__THERMMAX_MASK
 
- THM_TCON_LOCAL8__THERMMAX__SHIFT
 
- THM_TCON_LOCAL9__Tj_Max_TMON0_MASK
 
- THM_TCON_LOCAL9__Tj_Max_TMON0__SHIFT
 
- THM_TCON_THERM_TRIP__CTF_PAD_POLARITY_MASK
 
- THM_TCON_THERM_TRIP__CTF_PAD_POLARITY__SHIFT
 
- THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED_MASK
 
- THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED__SHIFT
 
- THM_TCON_THERM_TRIP__RSVD0_MASK
 
- THM_TCON_THERM_TRIP__RSVD0__SHIFT
 
- THM_TCON_THERM_TRIP__RSVD1_MASK
 
- THM_TCON_THERM_TRIP__RSVD1__SHIFT
 
- THM_TCON_THERM_TRIP__RSVD2_MASK
 
- THM_TCON_THERM_TRIP__RSVD2__SHIFT
 
- THM_TCON_THERM_TRIP__RSVD3_MASK
 
- THM_TCON_THERM_TRIP__RSVD3__SHIFT
 
- THM_TCON_THERM_TRIP__SW_THERM_TP_MASK
 
- THM_TCON_THERM_TRIP__SW_THERM_TP__SHIFT
 
- THM_TCON_THERM_TRIP__THERM_TP_EN_MASK
 
- THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT
 
- THM_TCON_THERM_TRIP__THERM_TP_LMT_MASK
 
- THM_TCON_THERM_TRIP__THERM_TP_LMT__SHIFT
 
- THM_TCON_THERM_TRIP__THERM_TP_MASK
 
- THM_TCON_THERM_TRIP__THERM_TP_SENSE_MASK
 
- THM_TCON_THERM_TRIP__THERM_TP_SENSE__SHIFT
 
- THM_TCON_THERM_TRIP__THERM_TP__SHIFT
 
- THM_TEN
 
- THM_TES
 
- THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK
 
- THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT
 
- THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK
 
- THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT
 
- THM_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK
 
- THM_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT
 
- THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK
 
- THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT
 
- THM_THERMAL_INT_CTRL__TEMP_THRESHOLD_MASK
 
- THM_THERMAL_INT_CTRL__TEMP_THRESHOLD__SHIFT
 
- THM_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK
 
- THM_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT
 
- THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA_MASK
 
- THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA__SHIFT
 
- THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK
 
- THM_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT
 
- THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK
 
- THM_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT
 
- THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK_MASK
 
- THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK__SHIFT
 
- THM_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK
 
- THM_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT
 
- THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK
 
- THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT
 
- THM_THERMAL_INT_ENA__THERM_INTH_CLR_MASK
 
- THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT
 
- THM_THERMAL_INT_ENA__THERM_INTH_SET_MASK
 
- THM_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT
 
- THM_THERMAL_INT_ENA__THERM_INTL_CLR_MASK
 
- THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT
 
- THM_THERMAL_INT_ENA__THERM_INTL_SET_MASK
 
- THM_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT
 
- THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK
 
- THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT
 
- THM_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK
 
- THM_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT
 
- THM_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK
 
- THM_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT
 
- THM_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK
 
- THM_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT
 
- THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT_MASK
 
- THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT__SHIFT
 
- THM_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK
 
- THM_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT
 
- THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK
 
- THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT
 
- THM_TMON0_COEFF__C_OFFSET_MASK
 
- THM_TMON0_COEFF__C_OFFSET__SHIFT
 
- THM_TMON0_COEFF__D_MASK
 
- THM_TMON0_COEFF__D__SHIFT
 
- THM_TMON0_CTRL2__RDIL_PRESENT_MASK
 
- THM_TMON0_CTRL2__RDIL_PRESENT__SHIFT
 
- THM_TMON0_CTRL2__RDIR_PRESENT_MASK
 
- THM_TMON0_CTRL2__RDIR_PRESENT__SHIFT
 
- THM_TMON0_CTRL__BGADJ_MASK
 
- THM_TMON0_CTRL__BGADJ_MODE_MASK
 
- THM_TMON0_CTRL__BGADJ_MODE__SHIFT
 
- THM_TMON0_CTRL__BGADJ__SHIFT
 
- THM_TMON0_CTRL__DEBUG_MODE_MASK
 
- THM_TMON0_CTRL__DEBUG_MODE__SHIFT
 
- THM_TMON0_CTRL__EN_CFG_SERDES_MASK
 
- THM_TMON0_CTRL__EN_CFG_SERDES__SHIFT
 
- THM_TMON0_CTRL__INT_MEAS_EN_MASK
 
- THM_TMON0_CTRL__INT_MEAS_EN__SHIFT
 
- THM_TMON0_CTRL__POWER_DOWN_MASK
 
- THM_TMON0_CTRL__POWER_DOWN__SHIFT
 
- THM_TMON0_CTRL__TMON_PAUSE_MASK
 
- THM_TMON0_CTRL__TMON_PAUSE__SHIFT
 
- THM_TMON0_DEBUG__DEBUG_RDI_MASK
 
- THM_TMON0_DEBUG__DEBUG_RDI__SHIFT
 
- THM_TMON0_DEBUG__DEBUG_Z_MASK
 
- THM_TMON0_DEBUG__DEBUG_Z__SHIFT
 
- THM_TMON0_INT_DATA__TEMP_MASK
 
- THM_TMON0_INT_DATA__TEMP__SHIFT
 
- THM_TMON0_INT_DATA__VALID_MASK
 
- THM_TMON0_INT_DATA__VALID__SHIFT
 
- THM_TMON0_INT_DATA__Z_MASK
 
- THM_TMON0_INT_DATA__Z__SHIFT
 
- THM_TMON0_RDIL0_DATA__TEMP_MASK
 
- THM_TMON0_RDIL0_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIL0_DATA__VALID_MASK
 
- THM_TMON0_RDIL0_DATA__VALID__SHIFT
 
- THM_TMON0_RDIL0_DATA__Z_MASK
 
- THM_TMON0_RDIL0_DATA__Z__SHIFT
 
- THM_TMON0_RDIL10_DATA__TEMP_MASK
 
- THM_TMON0_RDIL10_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIL10_DATA__VALID_MASK
 
- THM_TMON0_RDIL10_DATA__VALID__SHIFT
 
- THM_TMON0_RDIL10_DATA__Z_MASK
 
- THM_TMON0_RDIL10_DATA__Z__SHIFT
 
- THM_TMON0_RDIL11_DATA__TEMP_MASK
 
- THM_TMON0_RDIL11_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIL11_DATA__VALID_MASK
 
- THM_TMON0_RDIL11_DATA__VALID__SHIFT
 
- THM_TMON0_RDIL11_DATA__Z_MASK
 
- THM_TMON0_RDIL11_DATA__Z__SHIFT
 
- THM_TMON0_RDIL12_DATA__TEMP_MASK
 
- THM_TMON0_RDIL12_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIL12_DATA__VALID_MASK
 
- THM_TMON0_RDIL12_DATA__VALID__SHIFT
 
- THM_TMON0_RDIL12_DATA__Z_MASK
 
- THM_TMON0_RDIL12_DATA__Z__SHIFT
 
- THM_TMON0_RDIL13_DATA__TEMP_MASK
 
- THM_TMON0_RDIL13_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIL13_DATA__VALID_MASK
 
- THM_TMON0_RDIL13_DATA__VALID__SHIFT
 
- THM_TMON0_RDIL13_DATA__Z_MASK
 
- THM_TMON0_RDIL13_DATA__Z__SHIFT
 
- THM_TMON0_RDIL14_DATA__TEMP_MASK
 
- THM_TMON0_RDIL14_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIL14_DATA__VALID_MASK
 
- THM_TMON0_RDIL14_DATA__VALID__SHIFT
 
- THM_TMON0_RDIL14_DATA__Z_MASK
 
- THM_TMON0_RDIL14_DATA__Z__SHIFT
 
- THM_TMON0_RDIL15_DATA__TEMP_MASK
 
- THM_TMON0_RDIL15_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIL15_DATA__VALID_MASK
 
- THM_TMON0_RDIL15_DATA__VALID__SHIFT
 
- THM_TMON0_RDIL15_DATA__Z_MASK
 
- THM_TMON0_RDIL15_DATA__Z__SHIFT
 
- THM_TMON0_RDIL1_DATA__TEMP_MASK
 
- THM_TMON0_RDIL1_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIL1_DATA__VALID_MASK
 
- THM_TMON0_RDIL1_DATA__VALID__SHIFT
 
- THM_TMON0_RDIL1_DATA__Z_MASK
 
- THM_TMON0_RDIL1_DATA__Z__SHIFT
 
- THM_TMON0_RDIL2_DATA__TEMP_MASK
 
- THM_TMON0_RDIL2_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIL2_DATA__VALID_MASK
 
- THM_TMON0_RDIL2_DATA__VALID__SHIFT
 
- THM_TMON0_RDIL2_DATA__Z_MASK
 
- THM_TMON0_RDIL2_DATA__Z__SHIFT
 
- THM_TMON0_RDIL3_DATA__TEMP_MASK
 
- THM_TMON0_RDIL3_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIL3_DATA__VALID_MASK
 
- THM_TMON0_RDIL3_DATA__VALID__SHIFT
 
- THM_TMON0_RDIL3_DATA__Z_MASK
 
- THM_TMON0_RDIL3_DATA__Z__SHIFT
 
- THM_TMON0_RDIL4_DATA__TEMP_MASK
 
- THM_TMON0_RDIL4_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIL4_DATA__VALID_MASK
 
- THM_TMON0_RDIL4_DATA__VALID__SHIFT
 
- THM_TMON0_RDIL4_DATA__Z_MASK
 
- THM_TMON0_RDIL4_DATA__Z__SHIFT
 
- THM_TMON0_RDIL5_DATA__TEMP_MASK
 
- THM_TMON0_RDIL5_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIL5_DATA__VALID_MASK
 
- THM_TMON0_RDIL5_DATA__VALID__SHIFT
 
- THM_TMON0_RDIL5_DATA__Z_MASK
 
- THM_TMON0_RDIL5_DATA__Z__SHIFT
 
- THM_TMON0_RDIL6_DATA__TEMP_MASK
 
- THM_TMON0_RDIL6_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIL6_DATA__VALID_MASK
 
- THM_TMON0_RDIL6_DATA__VALID__SHIFT
 
- THM_TMON0_RDIL6_DATA__Z_MASK
 
- THM_TMON0_RDIL6_DATA__Z__SHIFT
 
- THM_TMON0_RDIL7_DATA__TEMP_MASK
 
- THM_TMON0_RDIL7_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIL7_DATA__VALID_MASK
 
- THM_TMON0_RDIL7_DATA__VALID__SHIFT
 
- THM_TMON0_RDIL7_DATA__Z_MASK
 
- THM_TMON0_RDIL7_DATA__Z__SHIFT
 
- THM_TMON0_RDIL8_DATA__TEMP_MASK
 
- THM_TMON0_RDIL8_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIL8_DATA__VALID_MASK
 
- THM_TMON0_RDIL8_DATA__VALID__SHIFT
 
- THM_TMON0_RDIL8_DATA__Z_MASK
 
- THM_TMON0_RDIL8_DATA__Z__SHIFT
 
- THM_TMON0_RDIL9_DATA__TEMP_MASK
 
- THM_TMON0_RDIL9_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIL9_DATA__VALID_MASK
 
- THM_TMON0_RDIL9_DATA__VALID__SHIFT
 
- THM_TMON0_RDIL9_DATA__Z_MASK
 
- THM_TMON0_RDIL9_DATA__Z__SHIFT
 
- THM_TMON0_RDIR0_DATA__TEMP_MASK
 
- THM_TMON0_RDIR0_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIR0_DATA__VALID_MASK
 
- THM_TMON0_RDIR0_DATA__VALID__SHIFT
 
- THM_TMON0_RDIR0_DATA__Z_MASK
 
- THM_TMON0_RDIR0_DATA__Z__SHIFT
 
- THM_TMON0_RDIR10_DATA__TEMP_MASK
 
- THM_TMON0_RDIR10_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIR10_DATA__VALID_MASK
 
- THM_TMON0_RDIR10_DATA__VALID__SHIFT
 
- THM_TMON0_RDIR10_DATA__Z_MASK
 
- THM_TMON0_RDIR10_DATA__Z__SHIFT
 
- THM_TMON0_RDIR11_DATA__TEMP_MASK
 
- THM_TMON0_RDIR11_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIR11_DATA__VALID_MASK
 
- THM_TMON0_RDIR11_DATA__VALID__SHIFT
 
- THM_TMON0_RDIR11_DATA__Z_MASK
 
- THM_TMON0_RDIR11_DATA__Z__SHIFT
 
- THM_TMON0_RDIR12_DATA__TEMP_MASK
 
- THM_TMON0_RDIR12_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIR12_DATA__VALID_MASK
 
- THM_TMON0_RDIR12_DATA__VALID__SHIFT
 
- THM_TMON0_RDIR12_DATA__Z_MASK
 
- THM_TMON0_RDIR12_DATA__Z__SHIFT
 
- THM_TMON0_RDIR13_DATA__TEMP_MASK
 
- THM_TMON0_RDIR13_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIR13_DATA__VALID_MASK
 
- THM_TMON0_RDIR13_DATA__VALID__SHIFT
 
- THM_TMON0_RDIR13_DATA__Z_MASK
 
- THM_TMON0_RDIR13_DATA__Z__SHIFT
 
- THM_TMON0_RDIR14_DATA__TEMP_MASK
 
- THM_TMON0_RDIR14_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIR14_DATA__VALID_MASK
 
- THM_TMON0_RDIR14_DATA__VALID__SHIFT
 
- THM_TMON0_RDIR14_DATA__Z_MASK
 
- THM_TMON0_RDIR14_DATA__Z__SHIFT
 
- THM_TMON0_RDIR15_DATA__TEMP_MASK
 
- THM_TMON0_RDIR15_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIR15_DATA__VALID_MASK
 
- THM_TMON0_RDIR15_DATA__VALID__SHIFT
 
- THM_TMON0_RDIR15_DATA__Z_MASK
 
- THM_TMON0_RDIR15_DATA__Z__SHIFT
 
- THM_TMON0_RDIR1_DATA__TEMP_MASK
 
- THM_TMON0_RDIR1_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIR1_DATA__VALID_MASK
 
- THM_TMON0_RDIR1_DATA__VALID__SHIFT
 
- THM_TMON0_RDIR1_DATA__Z_MASK
 
- THM_TMON0_RDIR1_DATA__Z__SHIFT
 
- THM_TMON0_RDIR2_DATA__TEMP_MASK
 
- THM_TMON0_RDIR2_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIR2_DATA__VALID_MASK
 
- THM_TMON0_RDIR2_DATA__VALID__SHIFT
 
- THM_TMON0_RDIR2_DATA__Z_MASK
 
- THM_TMON0_RDIR2_DATA__Z__SHIFT
 
- THM_TMON0_RDIR3_DATA__TEMP_MASK
 
- THM_TMON0_RDIR3_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIR3_DATA__VALID_MASK
 
- THM_TMON0_RDIR3_DATA__VALID__SHIFT
 
- THM_TMON0_RDIR3_DATA__Z_MASK
 
- THM_TMON0_RDIR3_DATA__Z__SHIFT
 
- THM_TMON0_RDIR4_DATA__TEMP_MASK
 
- THM_TMON0_RDIR4_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIR4_DATA__VALID_MASK
 
- THM_TMON0_RDIR4_DATA__VALID__SHIFT
 
- THM_TMON0_RDIR4_DATA__Z_MASK
 
- THM_TMON0_RDIR4_DATA__Z__SHIFT
 
- THM_TMON0_RDIR5_DATA__TEMP_MASK
 
- THM_TMON0_RDIR5_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIR5_DATA__VALID_MASK
 
- THM_TMON0_RDIR5_DATA__VALID__SHIFT
 
- THM_TMON0_RDIR5_DATA__Z_MASK
 
- THM_TMON0_RDIR5_DATA__Z__SHIFT
 
- THM_TMON0_RDIR6_DATA__TEMP_MASK
 
- THM_TMON0_RDIR6_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIR6_DATA__VALID_MASK
 
- THM_TMON0_RDIR6_DATA__VALID__SHIFT
 
- THM_TMON0_RDIR6_DATA__Z_MASK
 
- THM_TMON0_RDIR6_DATA__Z__SHIFT
 
- THM_TMON0_RDIR7_DATA__TEMP_MASK
 
- THM_TMON0_RDIR7_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIR7_DATA__VALID_MASK
 
- THM_TMON0_RDIR7_DATA__VALID__SHIFT
 
- THM_TMON0_RDIR7_DATA__Z_MASK
 
- THM_TMON0_RDIR7_DATA__Z__SHIFT
 
- THM_TMON0_RDIR8_DATA__TEMP_MASK
 
- THM_TMON0_RDIR8_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIR8_DATA__VALID_MASK
 
- THM_TMON0_RDIR8_DATA__VALID__SHIFT
 
- THM_TMON0_RDIR8_DATA__Z_MASK
 
- THM_TMON0_RDIR8_DATA__Z__SHIFT
 
- THM_TMON0_RDIR9_DATA__TEMP_MASK
 
- THM_TMON0_RDIR9_DATA__TEMP__SHIFT
 
- THM_TMON0_RDIR9_DATA__VALID_MASK
 
- THM_TMON0_RDIR9_DATA__VALID__SHIFT
 
- THM_TMON0_RDIR9_DATA__Z_MASK
 
- THM_TMON0_RDIR9_DATA__Z__SHIFT
 
- THM_TMON0_REMOTE_END__DATA_MASK
 
- THM_TMON0_REMOTE_END__DATA__SHIFT
 
- THM_TMON0_REMOTE_START__DATA_MASK
 
- THM_TMON0_REMOTE_START__DATA__SHIFT
 
- THM_TMON0_STATUS__CURRENT_RDI_MASK
 
- THM_TMON0_STATUS__CURRENT_RDI__SHIFT
 
- THM_TMON0_STATUS__MEAS_DONE_MASK
 
- THM_TMON0_STATUS__MEAS_DONE__SHIFT
 
- THM_TMON1_COEFF__C_OFFSET_MASK
 
- THM_TMON1_COEFF__C_OFFSET__SHIFT
 
- THM_TMON1_COEFF__D_MASK
 
- THM_TMON1_COEFF__D__SHIFT
 
- THM_TMON1_DEBUG__DEBUG_RDI_MASK
 
- THM_TMON1_DEBUG__DEBUG_RDI__SHIFT
 
- THM_TMON1_DEBUG__DEBUG_Z_MASK
 
- THM_TMON1_DEBUG__DEBUG_Z__SHIFT
 
- THM_TMON1_INT_DATA__TEMP_MASK
 
- THM_TMON1_INT_DATA__TEMP__SHIFT
 
- THM_TMON1_INT_DATA__VALID_MASK
 
- THM_TMON1_INT_DATA__VALID__SHIFT
 
- THM_TMON1_INT_DATA__Z_MASK
 
- THM_TMON1_INT_DATA__Z__SHIFT
 
- THM_TMON1_RDIL0_DATA__TEMP_MASK
 
- THM_TMON1_RDIL0_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIL0_DATA__VALID_MASK
 
- THM_TMON1_RDIL0_DATA__VALID__SHIFT
 
- THM_TMON1_RDIL0_DATA__Z_MASK
 
- THM_TMON1_RDIL0_DATA__Z__SHIFT
 
- THM_TMON1_RDIL10_DATA__TEMP_MASK
 
- THM_TMON1_RDIL10_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIL10_DATA__VALID_MASK
 
- THM_TMON1_RDIL10_DATA__VALID__SHIFT
 
- THM_TMON1_RDIL10_DATA__Z_MASK
 
- THM_TMON1_RDIL10_DATA__Z__SHIFT
 
- THM_TMON1_RDIL11_DATA__TEMP_MASK
 
- THM_TMON1_RDIL11_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIL11_DATA__VALID_MASK
 
- THM_TMON1_RDIL11_DATA__VALID__SHIFT
 
- THM_TMON1_RDIL11_DATA__Z_MASK
 
- THM_TMON1_RDIL11_DATA__Z__SHIFT
 
- THM_TMON1_RDIL12_DATA__TEMP_MASK
 
- THM_TMON1_RDIL12_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIL12_DATA__VALID_MASK
 
- THM_TMON1_RDIL12_DATA__VALID__SHIFT
 
- THM_TMON1_RDIL12_DATA__Z_MASK
 
- THM_TMON1_RDIL12_DATA__Z__SHIFT
 
- THM_TMON1_RDIL13_DATA__TEMP_MASK
 
- THM_TMON1_RDIL13_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIL13_DATA__VALID_MASK
 
- THM_TMON1_RDIL13_DATA__VALID__SHIFT
 
- THM_TMON1_RDIL13_DATA__Z_MASK
 
- THM_TMON1_RDIL13_DATA__Z__SHIFT
 
- THM_TMON1_RDIL14_DATA__TEMP_MASK
 
- THM_TMON1_RDIL14_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIL14_DATA__VALID_MASK
 
- THM_TMON1_RDIL14_DATA__VALID__SHIFT
 
- THM_TMON1_RDIL14_DATA__Z_MASK
 
- THM_TMON1_RDIL14_DATA__Z__SHIFT
 
- THM_TMON1_RDIL15_DATA__TEMP_MASK
 
- THM_TMON1_RDIL15_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIL15_DATA__VALID_MASK
 
- THM_TMON1_RDIL15_DATA__VALID__SHIFT
 
- THM_TMON1_RDIL15_DATA__Z_MASK
 
- THM_TMON1_RDIL15_DATA__Z__SHIFT
 
- THM_TMON1_RDIL1_DATA__TEMP_MASK
 
- THM_TMON1_RDIL1_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIL1_DATA__VALID_MASK
 
- THM_TMON1_RDIL1_DATA__VALID__SHIFT
 
- THM_TMON1_RDIL1_DATA__Z_MASK
 
- THM_TMON1_RDIL1_DATA__Z__SHIFT
 
- THM_TMON1_RDIL2_DATA__TEMP_MASK
 
- THM_TMON1_RDIL2_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIL2_DATA__VALID_MASK
 
- THM_TMON1_RDIL2_DATA__VALID__SHIFT
 
- THM_TMON1_RDIL2_DATA__Z_MASK
 
- THM_TMON1_RDIL2_DATA__Z__SHIFT
 
- THM_TMON1_RDIL3_DATA__TEMP_MASK
 
- THM_TMON1_RDIL3_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIL3_DATA__VALID_MASK
 
- THM_TMON1_RDIL3_DATA__VALID__SHIFT
 
- THM_TMON1_RDIL3_DATA__Z_MASK
 
- THM_TMON1_RDIL3_DATA__Z__SHIFT
 
- THM_TMON1_RDIL4_DATA__TEMP_MASK
 
- THM_TMON1_RDIL4_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIL4_DATA__VALID_MASK
 
- THM_TMON1_RDIL4_DATA__VALID__SHIFT
 
- THM_TMON1_RDIL4_DATA__Z_MASK
 
- THM_TMON1_RDIL4_DATA__Z__SHIFT
 
- THM_TMON1_RDIL5_DATA__TEMP_MASK
 
- THM_TMON1_RDIL5_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIL5_DATA__VALID_MASK
 
- THM_TMON1_RDIL5_DATA__VALID__SHIFT
 
- THM_TMON1_RDIL5_DATA__Z_MASK
 
- THM_TMON1_RDIL5_DATA__Z__SHIFT
 
- THM_TMON1_RDIL6_DATA__TEMP_MASK
 
- THM_TMON1_RDIL6_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIL6_DATA__VALID_MASK
 
- THM_TMON1_RDIL6_DATA__VALID__SHIFT
 
- THM_TMON1_RDIL6_DATA__Z_MASK
 
- THM_TMON1_RDIL6_DATA__Z__SHIFT
 
- THM_TMON1_RDIL7_DATA__TEMP_MASK
 
- THM_TMON1_RDIL7_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIL7_DATA__VALID_MASK
 
- THM_TMON1_RDIL7_DATA__VALID__SHIFT
 
- THM_TMON1_RDIL7_DATA__Z_MASK
 
- THM_TMON1_RDIL7_DATA__Z__SHIFT
 
- THM_TMON1_RDIL8_DATA__TEMP_MASK
 
- THM_TMON1_RDIL8_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIL8_DATA__VALID_MASK
 
- THM_TMON1_RDIL8_DATA__VALID__SHIFT
 
- THM_TMON1_RDIL8_DATA__Z_MASK
 
- THM_TMON1_RDIL8_DATA__Z__SHIFT
 
- THM_TMON1_RDIL9_DATA__TEMP_MASK
 
- THM_TMON1_RDIL9_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIL9_DATA__VALID_MASK
 
- THM_TMON1_RDIL9_DATA__VALID__SHIFT
 
- THM_TMON1_RDIL9_DATA__Z_MASK
 
- THM_TMON1_RDIL9_DATA__Z__SHIFT
 
- THM_TMON1_RDIR0_DATA__TEMP_MASK
 
- THM_TMON1_RDIR0_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIR0_DATA__VALID_MASK
 
- THM_TMON1_RDIR0_DATA__VALID__SHIFT
 
- THM_TMON1_RDIR0_DATA__Z_MASK
 
- THM_TMON1_RDIR0_DATA__Z__SHIFT
 
- THM_TMON1_RDIR10_DATA__TEMP_MASK
 
- THM_TMON1_RDIR10_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIR10_DATA__VALID_MASK
 
- THM_TMON1_RDIR10_DATA__VALID__SHIFT
 
- THM_TMON1_RDIR10_DATA__Z_MASK
 
- THM_TMON1_RDIR10_DATA__Z__SHIFT
 
- THM_TMON1_RDIR11_DATA__TEMP_MASK
 
- THM_TMON1_RDIR11_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIR11_DATA__VALID_MASK
 
- THM_TMON1_RDIR11_DATA__VALID__SHIFT
 
- THM_TMON1_RDIR11_DATA__Z_MASK
 
- THM_TMON1_RDIR11_DATA__Z__SHIFT
 
- THM_TMON1_RDIR12_DATA__TEMP_MASK
 
- THM_TMON1_RDIR12_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIR12_DATA__VALID_MASK
 
- THM_TMON1_RDIR12_DATA__VALID__SHIFT
 
- THM_TMON1_RDIR12_DATA__Z_MASK
 
- THM_TMON1_RDIR12_DATA__Z__SHIFT
 
- THM_TMON1_RDIR13_DATA__TEMP_MASK
 
- THM_TMON1_RDIR13_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIR13_DATA__VALID_MASK
 
- THM_TMON1_RDIR13_DATA__VALID__SHIFT
 
- THM_TMON1_RDIR13_DATA__Z_MASK
 
- THM_TMON1_RDIR13_DATA__Z__SHIFT
 
- THM_TMON1_RDIR14_DATA__TEMP_MASK
 
- THM_TMON1_RDIR14_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIR14_DATA__VALID_MASK
 
- THM_TMON1_RDIR14_DATA__VALID__SHIFT
 
- THM_TMON1_RDIR14_DATA__Z_MASK
 
- THM_TMON1_RDIR14_DATA__Z__SHIFT
 
- THM_TMON1_RDIR15_DATA__TEMP_MASK
 
- THM_TMON1_RDIR15_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIR15_DATA__VALID_MASK
 
- THM_TMON1_RDIR15_DATA__VALID__SHIFT
 
- THM_TMON1_RDIR15_DATA__Z_MASK
 
- THM_TMON1_RDIR15_DATA__Z__SHIFT
 
- THM_TMON1_RDIR1_DATA__TEMP_MASK
 
- THM_TMON1_RDIR1_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIR1_DATA__VALID_MASK
 
- THM_TMON1_RDIR1_DATA__VALID__SHIFT
 
- THM_TMON1_RDIR1_DATA__Z_MASK
 
- THM_TMON1_RDIR1_DATA__Z__SHIFT
 
- THM_TMON1_RDIR2_DATA__TEMP_MASK
 
- THM_TMON1_RDIR2_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIR2_DATA__VALID_MASK
 
- THM_TMON1_RDIR2_DATA__VALID__SHIFT
 
- THM_TMON1_RDIR2_DATA__Z_MASK
 
- THM_TMON1_RDIR2_DATA__Z__SHIFT
 
- THM_TMON1_RDIR3_DATA__TEMP_MASK
 
- THM_TMON1_RDIR3_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIR3_DATA__VALID_MASK
 
- THM_TMON1_RDIR3_DATA__VALID__SHIFT
 
- THM_TMON1_RDIR3_DATA__Z_MASK
 
- THM_TMON1_RDIR3_DATA__Z__SHIFT
 
- THM_TMON1_RDIR4_DATA__TEMP_MASK
 
- THM_TMON1_RDIR4_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIR4_DATA__VALID_MASK
 
- THM_TMON1_RDIR4_DATA__VALID__SHIFT
 
- THM_TMON1_RDIR4_DATA__Z_MASK
 
- THM_TMON1_RDIR4_DATA__Z__SHIFT
 
- THM_TMON1_RDIR5_DATA__TEMP_MASK
 
- THM_TMON1_RDIR5_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIR5_DATA__VALID_MASK
 
- THM_TMON1_RDIR5_DATA__VALID__SHIFT
 
- THM_TMON1_RDIR5_DATA__Z_MASK
 
- THM_TMON1_RDIR5_DATA__Z__SHIFT
 
- THM_TMON1_RDIR6_DATA__TEMP_MASK
 
- THM_TMON1_RDIR6_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIR6_DATA__VALID_MASK
 
- THM_TMON1_RDIR6_DATA__VALID__SHIFT
 
- THM_TMON1_RDIR6_DATA__Z_MASK
 
- THM_TMON1_RDIR6_DATA__Z__SHIFT
 
- THM_TMON1_RDIR7_DATA__TEMP_MASK
 
- THM_TMON1_RDIR7_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIR7_DATA__VALID_MASK
 
- THM_TMON1_RDIR7_DATA__VALID__SHIFT
 
- THM_TMON1_RDIR7_DATA__Z_MASK
 
- THM_TMON1_RDIR7_DATA__Z__SHIFT
 
- THM_TMON1_RDIR8_DATA__TEMP_MASK
 
- THM_TMON1_RDIR8_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIR8_DATA__VALID_MASK
 
- THM_TMON1_RDIR8_DATA__VALID__SHIFT
 
- THM_TMON1_RDIR8_DATA__Z_MASK
 
- THM_TMON1_RDIR8_DATA__Z__SHIFT
 
- THM_TMON1_RDIR9_DATA__TEMP_MASK
 
- THM_TMON1_RDIR9_DATA__TEMP__SHIFT
 
- THM_TMON1_RDIR9_DATA__VALID_MASK
 
- THM_TMON1_RDIR9_DATA__VALID__SHIFT
 
- THM_TMON1_RDIR9_DATA__Z_MASK
 
- THM_TMON1_RDIR9_DATA__Z__SHIFT
 
- THM_TMON1_REMOTE_END__DATA_MASK
 
- THM_TMON1_REMOTE_END__DATA__SHIFT
 
- THM_TMON1_REMOTE_START__DATA_MASK
 
- THM_TMON1_REMOTE_START__DATA__SHIFT
 
- THM_TMON1_STATUS__CURRENT_RDI_MASK
 
- THM_TMON1_STATUS__CURRENT_RDI__SHIFT
 
- THM_TMON1_STATUS__MEAS_DONE_MASK
 
- THM_TMON1_STATUS__MEAS_DONE__SHIFT
 
- THM_TMON2_CSR_RD__READ_DATA_MASK
 
- THM_TMON2_CSR_RD__READ_DATA__SHIFT
 
- THM_TMON2_CSR_WR__CSR_ADDR_MASK
 
- THM_TMON2_CSR_WR__CSR_ADDR__SHIFT
 
- THM_TMON2_CSR_WR__CSR_READ_MASK
 
- THM_TMON2_CSR_WR__CSR_READ__SHIFT
 
- THM_TMON2_CSR_WR__CSR_WRITE_MASK
 
- THM_TMON2_CSR_WR__CSR_WRITE__SHIFT
 
- THM_TMON2_CSR_WR__SPARE_MASK
 
- THM_TMON2_CSR_WR__SPARE__SHIFT
 
- THM_TMON2_CSR_WR__WRITE_DATA_MASK
 
- THM_TMON2_CSR_WR__WRITE_DATA__SHIFT
 
- THM_TMON2_CTRL2__RDIL_PRESENT_MASK
 
- THM_TMON2_CTRL2__RDIL_PRESENT__SHIFT
 
- THM_TMON2_CTRL2__RDIR_PRESENT_MASK
 
- THM_TMON2_CTRL2__RDIR_PRESENT__SHIFT
 
- THM_TMON2_CTRL__BGADJ_MASK
 
- THM_TMON2_CTRL__BGADJ_MODE_MASK
 
- THM_TMON2_CTRL__BGADJ_MODE__SHIFT
 
- THM_TMON2_CTRL__BGADJ__SHIFT
 
- THM_TMON2_CTRL__DEBUG_MODE_MASK
 
- THM_TMON2_CTRL__DEBUG_MODE__SHIFT
 
- THM_TMON2_CTRL__EN_CFG_SERDES_MASK
 
- THM_TMON2_CTRL__EN_CFG_SERDES__SHIFT
 
- THM_TMON2_CTRL__INT_MEAS_EN_MASK
 
- THM_TMON2_CTRL__INT_MEAS_EN__SHIFT
 
- THM_TMON2_CTRL__POWER_DOWN_MASK
 
- THM_TMON2_CTRL__POWER_DOWN__SHIFT
 
- THM_TMON2_CTRL__TMON_PAUSE_MASK
 
- THM_TMON2_CTRL__TMON_PAUSE__SHIFT
 
- THM_TMON2_DEBUG__DEBUG_RDI_MASK
 
- THM_TMON2_DEBUG__DEBUG_RDI__SHIFT
 
- THM_TMON2_DEBUG__DEBUG_Z_MASK
 
- THM_TMON2_DEBUG__DEBUG_Z__SHIFT
 
- THM_TMON2_INT_DATA__TEMP_MASK
 
- THM_TMON2_INT_DATA__TEMP__SHIFT
 
- THM_TMON2_INT_DATA__VALID_MASK
 
- THM_TMON2_INT_DATA__VALID__SHIFT
 
- THM_TMON2_INT_DATA__Z_MASK
 
- THM_TMON2_INT_DATA__Z__SHIFT
 
- THM_TMON2_RDIL0_DATA__TEMP_MASK
 
- THM_TMON2_RDIL0_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIL0_DATA__VALID_MASK
 
- THM_TMON2_RDIL0_DATA__VALID__SHIFT
 
- THM_TMON2_RDIL0_DATA__Z_MASK
 
- THM_TMON2_RDIL0_DATA__Z__SHIFT
 
- THM_TMON2_RDIL10_DATA__TEMP_MASK
 
- THM_TMON2_RDIL10_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIL10_DATA__VALID_MASK
 
- THM_TMON2_RDIL10_DATA__VALID__SHIFT
 
- THM_TMON2_RDIL10_DATA__Z_MASK
 
- THM_TMON2_RDIL10_DATA__Z__SHIFT
 
- THM_TMON2_RDIL11_DATA__TEMP_MASK
 
- THM_TMON2_RDIL11_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIL11_DATA__VALID_MASK
 
- THM_TMON2_RDIL11_DATA__VALID__SHIFT
 
- THM_TMON2_RDIL11_DATA__Z_MASK
 
- THM_TMON2_RDIL11_DATA__Z__SHIFT
 
- THM_TMON2_RDIL12_DATA__TEMP_MASK
 
- THM_TMON2_RDIL12_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIL12_DATA__VALID_MASK
 
- THM_TMON2_RDIL12_DATA__VALID__SHIFT
 
- THM_TMON2_RDIL12_DATA__Z_MASK
 
- THM_TMON2_RDIL12_DATA__Z__SHIFT
 
- THM_TMON2_RDIL13_DATA__TEMP_MASK
 
- THM_TMON2_RDIL13_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIL13_DATA__VALID_MASK
 
- THM_TMON2_RDIL13_DATA__VALID__SHIFT
 
- THM_TMON2_RDIL13_DATA__Z_MASK
 
- THM_TMON2_RDIL13_DATA__Z__SHIFT
 
- THM_TMON2_RDIL14_DATA__TEMP_MASK
 
- THM_TMON2_RDIL14_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIL14_DATA__VALID_MASK
 
- THM_TMON2_RDIL14_DATA__VALID__SHIFT
 
- THM_TMON2_RDIL14_DATA__Z_MASK
 
- THM_TMON2_RDIL14_DATA__Z__SHIFT
 
- THM_TMON2_RDIL15_DATA__TEMP_MASK
 
- THM_TMON2_RDIL15_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIL15_DATA__VALID_MASK
 
- THM_TMON2_RDIL15_DATA__VALID__SHIFT
 
- THM_TMON2_RDIL15_DATA__Z_MASK
 
- THM_TMON2_RDIL15_DATA__Z__SHIFT
 
- THM_TMON2_RDIL1_DATA__TEMP_MASK
 
- THM_TMON2_RDIL1_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIL1_DATA__VALID_MASK
 
- THM_TMON2_RDIL1_DATA__VALID__SHIFT
 
- THM_TMON2_RDIL1_DATA__Z_MASK
 
- THM_TMON2_RDIL1_DATA__Z__SHIFT
 
- THM_TMON2_RDIL2_DATA__TEMP_MASK
 
- THM_TMON2_RDIL2_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIL2_DATA__VALID_MASK
 
- THM_TMON2_RDIL2_DATA__VALID__SHIFT
 
- THM_TMON2_RDIL2_DATA__Z_MASK
 
- THM_TMON2_RDIL2_DATA__Z__SHIFT
 
- THM_TMON2_RDIL3_DATA__TEMP_MASK
 
- THM_TMON2_RDIL3_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIL3_DATA__VALID_MASK
 
- THM_TMON2_RDIL3_DATA__VALID__SHIFT
 
- THM_TMON2_RDIL3_DATA__Z_MASK
 
- THM_TMON2_RDIL3_DATA__Z__SHIFT
 
- THM_TMON2_RDIL4_DATA__TEMP_MASK
 
- THM_TMON2_RDIL4_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIL4_DATA__VALID_MASK
 
- THM_TMON2_RDIL4_DATA__VALID__SHIFT
 
- THM_TMON2_RDIL4_DATA__Z_MASK
 
- THM_TMON2_RDIL4_DATA__Z__SHIFT
 
- THM_TMON2_RDIL5_DATA__TEMP_MASK
 
- THM_TMON2_RDIL5_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIL5_DATA__VALID_MASK
 
- THM_TMON2_RDIL5_DATA__VALID__SHIFT
 
- THM_TMON2_RDIL5_DATA__Z_MASK
 
- THM_TMON2_RDIL5_DATA__Z__SHIFT
 
- THM_TMON2_RDIL6_DATA__TEMP_MASK
 
- THM_TMON2_RDIL6_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIL6_DATA__VALID_MASK
 
- THM_TMON2_RDIL6_DATA__VALID__SHIFT
 
- THM_TMON2_RDIL6_DATA__Z_MASK
 
- THM_TMON2_RDIL6_DATA__Z__SHIFT
 
- THM_TMON2_RDIL7_DATA__TEMP_MASK
 
- THM_TMON2_RDIL7_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIL7_DATA__VALID_MASK
 
- THM_TMON2_RDIL7_DATA__VALID__SHIFT
 
- THM_TMON2_RDIL7_DATA__Z_MASK
 
- THM_TMON2_RDIL7_DATA__Z__SHIFT
 
- THM_TMON2_RDIL8_DATA__TEMP_MASK
 
- THM_TMON2_RDIL8_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIL8_DATA__VALID_MASK
 
- THM_TMON2_RDIL8_DATA__VALID__SHIFT
 
- THM_TMON2_RDIL8_DATA__Z_MASK
 
- THM_TMON2_RDIL8_DATA__Z__SHIFT
 
- THM_TMON2_RDIL9_DATA__TEMP_MASK
 
- THM_TMON2_RDIL9_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIL9_DATA__VALID_MASK
 
- THM_TMON2_RDIL9_DATA__VALID__SHIFT
 
- THM_TMON2_RDIL9_DATA__Z_MASK
 
- THM_TMON2_RDIL9_DATA__Z__SHIFT
 
- THM_TMON2_RDIR0_DATA__TEMP_MASK
 
- THM_TMON2_RDIR0_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIR0_DATA__VALID_MASK
 
- THM_TMON2_RDIR0_DATA__VALID__SHIFT
 
- THM_TMON2_RDIR0_DATA__Z_MASK
 
- THM_TMON2_RDIR0_DATA__Z__SHIFT
 
- THM_TMON2_RDIR10_DATA__TEMP_MASK
 
- THM_TMON2_RDIR10_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIR10_DATA__VALID_MASK
 
- THM_TMON2_RDIR10_DATA__VALID__SHIFT
 
- THM_TMON2_RDIR10_DATA__Z_MASK
 
- THM_TMON2_RDIR10_DATA__Z__SHIFT
 
- THM_TMON2_RDIR11_DATA__TEMP_MASK
 
- THM_TMON2_RDIR11_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIR11_DATA__VALID_MASK
 
- THM_TMON2_RDIR11_DATA__VALID__SHIFT
 
- THM_TMON2_RDIR11_DATA__Z_MASK
 
- THM_TMON2_RDIR11_DATA__Z__SHIFT
 
- THM_TMON2_RDIR12_DATA__TEMP_MASK
 
- THM_TMON2_RDIR12_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIR12_DATA__VALID_MASK
 
- THM_TMON2_RDIR12_DATA__VALID__SHIFT
 
- THM_TMON2_RDIR12_DATA__Z_MASK
 
- THM_TMON2_RDIR12_DATA__Z__SHIFT
 
- THM_TMON2_RDIR13_DATA__TEMP_MASK
 
- THM_TMON2_RDIR13_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIR13_DATA__VALID_MASK
 
- THM_TMON2_RDIR13_DATA__VALID__SHIFT
 
- THM_TMON2_RDIR13_DATA__Z_MASK
 
- THM_TMON2_RDIR13_DATA__Z__SHIFT
 
- THM_TMON2_RDIR14_DATA__TEMP_MASK
 
- THM_TMON2_RDIR14_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIR14_DATA__VALID_MASK
 
- THM_TMON2_RDIR14_DATA__VALID__SHIFT
 
- THM_TMON2_RDIR14_DATA__Z_MASK
 
- THM_TMON2_RDIR14_DATA__Z__SHIFT
 
- THM_TMON2_RDIR15_DATA__TEMP_MASK
 
- THM_TMON2_RDIR15_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIR15_DATA__VALID_MASK
 
- THM_TMON2_RDIR15_DATA__VALID__SHIFT
 
- THM_TMON2_RDIR15_DATA__Z_MASK
 
- THM_TMON2_RDIR15_DATA__Z__SHIFT
 
- THM_TMON2_RDIR1_DATA__TEMP_MASK
 
- THM_TMON2_RDIR1_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIR1_DATA__VALID_MASK
 
- THM_TMON2_RDIR1_DATA__VALID__SHIFT
 
- THM_TMON2_RDIR1_DATA__Z_MASK
 
- THM_TMON2_RDIR1_DATA__Z__SHIFT
 
- THM_TMON2_RDIR2_DATA__TEMP_MASK
 
- THM_TMON2_RDIR2_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIR2_DATA__VALID_MASK
 
- THM_TMON2_RDIR2_DATA__VALID__SHIFT
 
- THM_TMON2_RDIR2_DATA__Z_MASK
 
- THM_TMON2_RDIR2_DATA__Z__SHIFT
 
- THM_TMON2_RDIR3_DATA__TEMP_MASK
 
- THM_TMON2_RDIR3_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIR3_DATA__VALID_MASK
 
- THM_TMON2_RDIR3_DATA__VALID__SHIFT
 
- THM_TMON2_RDIR3_DATA__Z_MASK
 
- THM_TMON2_RDIR3_DATA__Z__SHIFT
 
- THM_TMON2_RDIR4_DATA__TEMP_MASK
 
- THM_TMON2_RDIR4_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIR4_DATA__VALID_MASK
 
- THM_TMON2_RDIR4_DATA__VALID__SHIFT
 
- THM_TMON2_RDIR4_DATA__Z_MASK
 
- THM_TMON2_RDIR4_DATA__Z__SHIFT
 
- THM_TMON2_RDIR5_DATA__TEMP_MASK
 
- THM_TMON2_RDIR5_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIR5_DATA__VALID_MASK
 
- THM_TMON2_RDIR5_DATA__VALID__SHIFT
 
- THM_TMON2_RDIR5_DATA__Z_MASK
 
- THM_TMON2_RDIR5_DATA__Z__SHIFT
 
- THM_TMON2_RDIR6_DATA__TEMP_MASK
 
- THM_TMON2_RDIR6_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIR6_DATA__VALID_MASK
 
- THM_TMON2_RDIR6_DATA__VALID__SHIFT
 
- THM_TMON2_RDIR6_DATA__Z_MASK
 
- THM_TMON2_RDIR6_DATA__Z__SHIFT
 
- THM_TMON2_RDIR7_DATA__TEMP_MASK
 
- THM_TMON2_RDIR7_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIR7_DATA__VALID_MASK
 
- THM_TMON2_RDIR7_DATA__VALID__SHIFT
 
- THM_TMON2_RDIR7_DATA__Z_MASK
 
- THM_TMON2_RDIR7_DATA__Z__SHIFT
 
- THM_TMON2_RDIR8_DATA__TEMP_MASK
 
- THM_TMON2_RDIR8_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIR8_DATA__VALID_MASK
 
- THM_TMON2_RDIR8_DATA__VALID__SHIFT
 
- THM_TMON2_RDIR8_DATA__Z_MASK
 
- THM_TMON2_RDIR8_DATA__Z__SHIFT
 
- THM_TMON2_RDIR9_DATA__TEMP_MASK
 
- THM_TMON2_RDIR9_DATA__TEMP__SHIFT
 
- THM_TMON2_RDIR9_DATA__VALID_MASK
 
- THM_TMON2_RDIR9_DATA__VALID__SHIFT
 
- THM_TMON2_RDIR9_DATA__Z_MASK
 
- THM_TMON2_RDIR9_DATA__Z__SHIFT
 
- THM_TMON2_REMOTE_END__DATA_MASK
 
- THM_TMON2_REMOTE_END__DATA__SHIFT
 
- THM_TMON2_REMOTE_START__DATA_MASK
 
- THM_TMON2_REMOTE_START__DATA__SHIFT
 
- THM_TMON2_STATUS__CURRENT_RDI_MASK
 
- THM_TMON2_STATUS__CURRENT_RDI__SHIFT
 
- THM_TMON2_STATUS__MEAS_DONE_MASK
 
- THM_TMON2_STATUS__MEAS_DONE__SHIFT
 
- THM_TMON3_REMOTE_END__DATA_MASK
 
- THM_TMON3_REMOTE_END__DATA__SHIFT
 
- THM_TMON3_REMOTE_START__DATA_MASK
 
- THM_TMON3_REMOTE_START__DATA__SHIFT
 
- THM_TMON_CONFIG2__A_MASK
 
- THM_TMON_CONFIG2__A__SHIFT
 
- THM_TMON_CONFIG2__B_MASK
 
- THM_TMON_CONFIG2__B__SHIFT
 
- THM_TMON_CONFIG2__C_MASK
 
- THM_TMON_CONFIG2__C__SHIFT
 
- THM_TMON_CONFIG2__K_MASK
 
- THM_TMON_CONFIG2__K__SHIFT
 
- THM_TMON_CONFIG__CONFIG_SOURCE_MASK
 
- THM_TMON_CONFIG__CONFIG_SOURCE__SHIFT
 
- THM_TMON_CONFIG__FORCE_MAX_ACQ_MASK
 
- THM_TMON_CONFIG__FORCE_MAX_ACQ__SHIFT
 
- THM_TMON_CONFIG__NUM_ACQ_MASK
 
- THM_TMON_CONFIG__NUM_ACQ__SHIFT
 
- THM_TMON_CONFIG__RDI_INTERLEAVE_MASK
 
- THM_TMON_CONFIG__RDI_INTERLEAVE__SHIFT
 
- THM_TMON_CONFIG__RE_CALIB_EN_MASK
 
- THM_TMON_CONFIG__RE_CALIB_EN__SHIFT
 
- THM_TMON_CONFIG__Z_MASK
 
- THM_TMON_CONFIG__Z__SHIFT
 
- THM_TOF
 
- THM_TRC
 
- THM_TSCO
 
- THM_TSE
 
- THM_TSES
 
- THM_TSGPEN
 
- THM_TSIU
 
- THM_TSLOCK
 
- THM_TSPC
 
- THM_TSPIEN
 
- THM_TSS
 
- THM_TSTR
 
- THM_TSTTP
 
- THOL0
 
- THOL1
 
- THOL2
 
- THOL3
 
- THOR_JEDEC_ID
 
- THPDA
 
- THP_COLLAPSE_ALLOC
 
- THP_COLLAPSE_ALLOC_FAILED
 
- THP_DEFERRED_SPLIT_PAGE
 
- THP_FAULT_ALLOC
 
- THP_FAULT_FALLBACK
 
- THP_FILE_ALLOC
 
- THP_FILE_MAPPED
 
- THP_SPLIT_PAGE
 
- THP_SPLIT_PAGE_FAILED
 
- THP_SPLIT_PMD
 
- THP_SPLIT_PUD
 
- THP_SWPOUT
 
- THP_SWPOUT_FALLBACK
 
- THP_ZERO_PAGE_ALLOC
 
- THP_ZERO_PAGE_ALLOC_FAILED
 
- THR
 
- THRASH_SIZE
 
- THRD_SIB_FMT
 
- THRD_SIB_FMT_NEW
 
- THREADINFO_GFP
 
- THREADS
 
- THREADS__TABLE_BITS
 
- THREADS__TABLE_SIZE
 
- THREAD_ALIGN
 
- THREAD_ARG_INITIALIZER
 
- THREAD_CLOCK
 
- THREAD_FACTOR
 
- THREAD_FLAGS_TO_CLEAR
 
- THREAD_FLAGS_TO_SET
 
- THREAD_GROUP_ENABLE
 
- THREAD_GROUP_SHARE_L1
 
- THREAD_ID_BITS
 
- THREAD_ID_MASK
 
- THREAD_ID_SHIFT
 
- THREAD_IGNORE
 
- THREAD_IMC_ENABLE
 
- THREAD_IMC_LDBAR_MASK
 
- THREAD_IRQ_SLEEP_MSECS
 
- THREAD_IRQ_SLEEP_SECS
 
- THREAD_KSP
 
- THREAD_MASK
 
- THREAD_MAX
 
- THREAD_NAME_LEN
 
- THREAD_NORMSAVE
 
- THREAD_NOTIFY_COPY
 
- THREAD_NOTIFY_EXIT
 
- THREAD_NOTIFY_FLUSH
 
- THREAD_NOTIFY_SWITCH
 
- THREAD_NUM
 
- THREAD_NUM_MASK
 
- THREAD_POINTER
 
- THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING
 
- THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16
 
- THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8
 
- THREAD_SCHED_IN
 
- THREAD_SHIFT
 
- THREAD_SIZE
 
- THREAD_SIZE_ORDER
 
- THREAD_SLEEPING
 
- THREAD_START_SP
 
- THREAD_TRACE_DRAW
 
- THREAD_TRACE_FINISH
 
- THREAD_TRACE_FLUSH
 
- THREAD_TRACE_MARKER
 
- THREAD_TRACE_START
 
- THREAD_TRACE_STOP
 
- THREAD_WAIT_CPU
 
- THREAD_WAKEUP
 
- THREE_DB_BNDWDTH_THRSHLD_REG
 
- THREE_DIMMS_PRESENT
 
- THREE_D_INST_DISABLE
 
- THREE_D_PIPE_FLUSHED
 
- THREE_PERCENT_OF_10000
 
- THREE_TAP_FILT
 
- THREE_TO_NUM
 
- THREE_WORD_MSG_SIZE
 
- THRESHOLD
 
- THRESHOLDS_EVENTS_TARGET
 
- THRESHOLD_0_G
 
- THRESHOLD_0_M
 
- THRESHOLD_0_S
 
- THRESHOLD_0_V
 
- THRESHOLD_1_G
 
- THRESHOLD_1_M
 
- THRESHOLD_1_S
 
- THRESHOLD_1_V
 
- THRESHOLD_2
 
- THRESHOLD_2_G
 
- THRESHOLD_2_M
 
- THRESHOLD_2_S
 
- THRESHOLD_2_V
 
- THRESHOLD_32
 
- THRESHOLD_3_G
 
- THRESHOLD_3_M
 
- THRESHOLD_3_S
 
- THRESHOLD_3_V
 
- THRESHOLD_ACTIVATE_SWAP_SLOTS_CACHE
 
- THRESHOLD_ADDR
 
- THRESHOLD_APIC_VECTOR
 
- THRESHOLD_DEACTIVATE_SWAP_SLOTS_CACHE
 
- THRESHOLD_EXCEEDED
 
- THRESHOLD_GESTURE
 
- THRESHOLD_GESTURE_DEFAULT
 
- THRESHOLD_INDEX_0
 
- THRESHOLD_INDEX_1
 
- THRESHOLD_INDEX_10
 
- THRESHOLD_INDEX_11
 
- THRESHOLD_INDEX_2
 
- THRESHOLD_INDEX_3
 
- THRESHOLD_INDEX_4
 
- THRESHOLD_INDEX_5
 
- THRESHOLD_INDEX_6
 
- THRESHOLD_INDEX_7
 
- THRESHOLD_INDEX_8
 
- THRESHOLD_INDEX_9
 
- THRESHOLD_INDEX_COUNT
 
- THRESHOLD_LOWER_LIMIT_SHIFT
 
- THRESHOLD_MAX
 
- THRESHOLD_MAX_LIMIT_SHIFT
 
- THRESHOLD_MIN_LIMIT_SHIFT
 
- THRESHOLD_PROP_BUILDER
 
- THRESHOLD_RD
 
- THRESHOLD_RD_IO
 
- THRESHOLD_SLEEP_IN
 
- THRESHOLD_START
 
- THRESHOLD_STOP
 
- THRESHOLD_TOUCH
 
- THRESHOLD_TOUCH_DEFAULT
 
- THRESHOLD_UPPER_LIMIT_SHIFT
 
- THRESHOLD_WR
 
- THRESHOLD_WR_IO
 
- THRESH_ACT
 
- THRESH_CEQ_DEFAULT
 
- THRESH_DLY
 
- THRESH_FF
 
- THRESH_GTE
 
- THRESH_INACT
 
- THRESH_LT
 
- THRESH_MASK
 
- THRESH_MAX
 
- THRESH_MIN
 
- THRESH_TAP
 
- THREX_GSSCH
 
- THREX_GSX
 
- THREX_IYQ
 
- THREX_TO
 
- THREX_TU
 
- THREX_YSCH
 
- THRM1_THRES
 
- THRM1_TID
 
- THRM1_TIE
 
- THRM1_TIN
 
- THRM1_TIV
 
- THRM1_V
 
- THRM3_E
 
- THRM3_SITV
 
- THROTL_IOPS_MAX
 
- THROTL_TG_PENDING
 
- THROTL_TG_WAS_EMPTY
 
- THROTTLED
 
- THROTTLED_TIME
 
- THROTTLER_APCC_BIT
 
- THROTTLER_FIT_BIT
 
- THROTTLER_PADDING_BIT
 
- THROTTLER_PPM_BIT
 
- THROTTLER_PPT0_BIT
 
- THROTTLER_PPT1_BIT
 
- THROTTLER_PPT2_BIT
 
- THROTTLER_PPT3_BIT
 
- THROTTLER_STATUS_BIT_FPPT
 
- THROTTLER_STATUS_BIT_SPL
 
- THROTTLER_STATUS_BIT_SPPT
 
- THROTTLER_STATUS_BIT_SPPT_APU
 
- THROTTLER_STATUS_BIT_TDC_SOC
 
- THROTTLER_STATUS_BIT_TDC_VDD
 
- THROTTLER_STATUS_BIT_THM_CORE
 
- THROTTLER_STATUS_BIT_THM_GFX
 
- THROTTLER_STATUS_BIT_THM_SOC
 
- THROTTLER_STATUS_FIT_BIT
 
- THROTTLER_STATUS_PADDING_BIT
 
- THROTTLER_STATUS_PPM_BIT
 
- THROTTLER_STATUS_PPT_BIT
 
- THROTTLER_STATUS_TDC_GFX_BIT
 
- THROTTLER_STATUS_TDC_SOC_BIT
 
- THROTTLER_STATUS_TEMP_EDGE_BIT
 
- THROTTLER_STATUS_TEMP_HBM_BIT
 
- THROTTLER_STATUS_TEMP_HOTSPOT_BIT
 
- THROTTLER_STATUS_TEMP_LIQUID_BIT
 
- THROTTLER_STATUS_TEMP_PLX_BIT
 
- THROTTLER_STATUS_TEMP_SKIN_BIT
 
- THROTTLER_STATUS_TEMP_VR_GFX_BIT
 
- THROTTLER_STATUS_TEMP_VR_MEM0_BIT
 
- THROTTLER_STATUS_TEMP_VR_MEM1_BIT
 
- THROTTLER_STATUS_TEMP_VR_MEM_BIT
 
- THROTTLER_STATUS_TEMP_VR_SOC_BIT
 
- THROTTLER_TDC_GFX_BIT
 
- THROTTLER_TDC_SOC_BIT
 
- THROTTLER_TEMP_EDGE_BIT
 
- THROTTLER_TEMP_HOTSPOT_BIT
 
- THROTTLER_TEMP_LIQUID0_BIT
 
- THROTTLER_TEMP_LIQUID1_BIT
 
- THROTTLER_TEMP_MEM_BIT
 
- THROTTLER_TEMP_PLX_BIT
 
- THROTTLER_TEMP_SKIN_BIT
 
- THROTTLER_TEMP_VR_GFX_BIT
 
- THROTTLER_TEMP_VR_MEM0_BIT
 
- THROTTLER_TEMP_VR_MEM1_BIT
 
- THROTTLER_TEMP_VR_MEM_BIT
 
- THROTTLER_TEMP_VR_SOC_BIT
 
- THROTTLE_12_5
 
- THROTTLE_CAMSS_AHB_CLK
 
- THROTTLE_CAMSS_AXI_CLK
 
- THROTTLE_CAMSS_BCR
 
- THROTTLE_CAMSS_CXO_CLK
 
- THROTTLE_DEV_CPU
 
- THROTTLE_DEV_GPU
 
- THROTTLE_DEV_SIZE
 
- THROTTLE_HEAVY
 
- THROTTLE_JIFFIES
 
- THROTTLE_LIGHT
 
- THROTTLE_MDSS_AHB_CLK
 
- THROTTLE_MDSS_AXI_CLK
 
- THROTTLE_MDSS_BCR
 
- THROTTLE_MDSS_CXO_CLK
 
- THROTTLE_MSECS
 
- THROTTLE_OC1
 
- THROTTLE_OC2
 
- THROTTLE_OC3
 
- THROTTLE_OC4
 
- THROTTLE_OC5
 
- THROTTLE_RATE_BPS
 
- THROTTLE_RX
 
- THROTTLE_SIZE
 
- THROTTLE_THRESHOLD
 
- THROTTLE_TX
 
- THROTTLE_TX_PKTS
 
- THROTTLE_VIDEO_AHB_CLK
 
- THROTTLE_VIDEO_AXI_CLK
 
- THROTTLE_VIDEO_BCR
 
- THROTTLE_VIDEO_CXO_CLK
 
- THROTTLING_POSTCHANGE
 
- THROTTLING_PRECHANGE
 
- THROT_DELAY_CTRL
 
- THROT_DELAY_LITE
 
- THROT_DELAY_LITE_DELAY_MASK
 
- THROT_DEPTH_DIVIDEND
 
- THROT_GLOBAL_CFG
 
- THROT_GLOBAL_ENB_MASK
 
- THROT_LEVEL_TO_DEPTH
 
- THROT_OFFSET
 
- THROT_PRIORITY_CTRL
 
- THROT_PRIORITY_LITE
 
- THROT_PRIORITY_LITE_PRIO_MASK
 
- THROT_PRIORITY_LOCK
 
- THROT_PRIORITY_LOCK_PRIORITY_MASK
 
- THROT_PSKIP_CTRL
 
- THROT_PSKIP_CTRL_DIVIDEND_MASK
 
- THROT_PSKIP_CTRL_DIVISOR_MASK
 
- THROT_PSKIP_CTRL_ENABLE_MASK
 
- THROT_PSKIP_CTRL_LITE_CPU
 
- THROT_PSKIP_CTRL_VECT2_CPU_MASK
 
- THROT_PSKIP_CTRL_VECT_CPU_MASK
 
- THROT_PSKIP_CTRL_VECT_GPU_MASK
 
- THROT_PSKIP_RAMP
 
- THROT_PSKIP_RAMP_DURATION_MASK
 
- THROT_PSKIP_RAMP_LITE_CPU
 
- THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK
 
- THROT_PSKIP_RAMP_STEP_MASK
 
- THROT_STATUS
 
- THROT_STATUS_BREACH_MASK
 
- THROT_STATUS_ENABLED_MASK
 
- THROT_STATUS_STATE_MASK
 
- THROT_VECT_HIGH
 
- THROT_VECT_LOW
 
- THROT_VECT_MED
 
- THROT_VECT_NONE
 
- THRUPUT_MON_EN
 
- THRUPUT_MON_RATE_MASK
 
- THRUPUT_MON_RATE_SHIFT
 
- THRUSTMASTER_DEVICE_ID_2_IN_1_DT
 
- THRUSTMASTER_USAGE_FF
 
- THRU_ENABLED
 
- THR_INT_INJ
 
- THS7303_CHANNEL_1
 
- THS7303_CHANNEL_2
 
- THS7303_CHANNEL_3
 
- THS7303_FILTER_MODE_1080P
 
- THS7303_FILTER_MODE_480I_576I
 
- THS7303_FILTER_MODE_480P_576P
 
- THS7303_FILTER_MODE_720P_1080I
 
- THS7303_FILTER_MODE_DISABLE
 
- THS7353_H
 
- THS8200_CGMS_CNTL_HEADER
 
- THS8200_CGMS_PAYLOAD_LSB
 
- THS8200_CGMS_PAYLOAD_MSB
 
- THS8200_CHIP_CTL
 
- THS8200_CSC_B11
 
- THS8200_CSC_B12
 
- THS8200_CSC_B21
 
- THS8200_CSC_B22
 
- THS8200_CSC_B31
 
- THS8200_CSC_B32
 
- THS8200_CSC_G11
 
- THS8200_CSC_G12
 
- THS8200_CSC_G21
 
- THS8200_CSC_G22
 
- THS8200_CSC_G31
 
- THS8200_CSC_G32
 
- THS8200_CSC_OFFS1
 
- THS8200_CSC_OFFS12
 
- THS8200_CSC_OFFS23
 
- THS8200_CSC_OFFS3
 
- THS8200_CSC_R11
 
- THS8200_CSC_R12
 
- THS8200_CSC_R21
 
- THS8200_CSC_R22
 
- THS8200_CSC_R31
 
- THS8200_CSC_R32
 
- THS8200_CSM_CLIP_BCB_HIGH
 
- THS8200_CSM_CLIP_BCB_LOW
 
- THS8200_CSM_CLIP_GY_HIGH
 
- THS8200_CSM_CLIP_GY_LOW
 
- THS8200_CSM_CLIP_RCR_HIGH
 
- THS8200_CSM_CLIP_RCR_LOW
 
- THS8200_CSM_GY_CNTL_MULT_MSB
 
- THS8200_CSM_MULT_BCB_LSB
 
- THS8200_CSM_MULT_BCB_RCR_MSB
 
- THS8200_CSM_MULT_GY_LSB
 
- THS8200_CSM_MULT_RCR_BCB_CNTL
 
- THS8200_CSM_MULT_RCR_LSB
 
- THS8200_CSM_SHIFT_BCB
 
- THS8200_CSM_SHIFT_GY
 
- THS8200_CSM_SHIFT_RCR
 
- THS8200_DAC1_CNTL_LSB
 
- THS8200_DAC2_CNTL_LSB
 
- THS8200_DAC3_CNTL_LSB
 
- THS8200_DAC_CNTL_MSB
 
- THS8200_DATA_CNTL
 
- THS8200_DTG1_CBCR_SYNC1_LSB
 
- THS8200_DTG1_CBCR_SYNC2_LSB
 
- THS8200_DTG1_CBCR_SYNC3_LSB
 
- THS8200_DTG1_CBCR_SYNC_MSB
 
- THS8200_DTG1_FIELD_SZ_LSB
 
- THS8200_DTG1_FLD_FLIP_LINECNT_MSB
 
- THS8200_DTG1_FRAME_FIELD_SZ_MSB
 
- THS8200_DTG1_FRAME_SZ_LSB
 
- THS8200_DTG1_LINECNT_LSB
 
- THS8200_DTG1_MODE
 
- THS8200_DTG1_SPEC_A
 
- THS8200_DTG1_SPEC_B
 
- THS8200_DTG1_SPEC_C
 
- THS8200_DTG1_SPEC_D1
 
- THS8200_DTG1_SPEC_DEH_MSB
 
- THS8200_DTG1_SPEC_D_LSB
 
- THS8200_DTG1_SPEC_E_LSB
 
- THS8200_DTG1_SPEC_G_LSB
 
- THS8200_DTG1_SPEC_G_MSB
 
- THS8200_DTG1_SPEC_H_LSB
 
- THS8200_DTG1_SPEC_I_LSB
 
- THS8200_DTG1_SPEC_I_MSB
 
- THS8200_DTG1_SPEC_K1
 
- THS8200_DTG1_SPEC_K_LSB
 
- THS8200_DTG1_SPEC_K_MSB
 
- THS8200_DTG1_TOT_PIXELS_LSB
 
- THS8200_DTG1_TOT_PIXELS_MSB
 
- THS8200_DTG1_VESA_CBAR_SIZE
 
- THS8200_DTG1_Y_SYNC1_LSB
 
- THS8200_DTG1_Y_SYNC2_LSB
 
- THS8200_DTG1_Y_SYNC3_LSB
 
- THS8200_DTG1_Y_SYNC_MSB
 
- THS8200_DTG2_BP10_LSB
 
- THS8200_DTG2_BP11_12_MSB
 
- THS8200_DTG2_BP11_LSB
 
- THS8200_DTG2_BP12_LSB
 
- THS8200_DTG2_BP13_14_MSB
 
- THS8200_DTG2_BP13_LSB
 
- THS8200_DTG2_BP14_LSB
 
- THS8200_DTG2_BP15_16_MSB
 
- THS8200_DTG2_BP15_LSB
 
- THS8200_DTG2_BP16_LSB
 
- THS8200_DTG2_BP1_2_MSB
 
- THS8200_DTG2_BP1_LSB
 
- THS8200_DTG2_BP2_LSB
 
- THS8200_DTG2_BP3_4_MSB
 
- THS8200_DTG2_BP3_LSB
 
- THS8200_DTG2_BP4_LSB
 
- THS8200_DTG2_BP5_6_MSB
 
- THS8200_DTG2_BP5_LSB
 
- THS8200_DTG2_BP6_LSB
 
- THS8200_DTG2_BP7_8_MSB
 
- THS8200_DTG2_BP7_LSB
 
- THS8200_DTG2_BP8_LSB
 
- THS8200_DTG2_BP9_10_MSB
 
- THS8200_DTG2_BP9_LSB
 
- THS8200_DTG2_CNTL
 
- THS8200_DTG2_HLENGTH_HDLY_LSB
 
- THS8200_DTG2_HLENGTH_LSB
 
- THS8200_DTG2_HLENGTH_LSB_HDLY_MSB
 
- THS8200_DTG2_HS_IN_DLY_LSB
 
- THS8200_DTG2_HS_IN_DLY_MSB
 
- THS8200_DTG2_LINETYPE1
 
- THS8200_DTG2_LINETYPE2
 
- THS8200_DTG2_LINETYPE3
 
- THS8200_DTG2_LINETYPE4
 
- THS8200_DTG2_LINETYPE5
 
- THS8200_DTG2_LINETYPE6
 
- THS8200_DTG2_LINETYPE7
 
- THS8200_DTG2_LINETYPE8
 
- THS8200_DTG2_LINE_CNT_LSB
 
- THS8200_DTG2_LINE_CNT_MSB
 
- THS8200_DTG2_PIXEL_CNT_LSB
 
- THS8200_DTG2_PIXEL_CNT_MSB
 
- THS8200_DTG2_VDLY1_LSB
 
- THS8200_DTG2_VDLY2_LSB
 
- THS8200_DTG2_VLENGTH1_LSB
 
- THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB
 
- THS8200_DTG2_VLENGTH2_LSB
 
- THS8200_DTG2_VLENGTH2_MSB_VDLY2_MSB
 
- THS8200_DTG2_VS_IN_DLY_LSB
 
- THS8200_DTG2_VS_IN_DLY_MSB
 
- THS8200_MISC_LPF_LSB
 
- THS8200_MISC_LPF_MSB
 
- THS8200_MISC_PPL_LSB
 
- THS8200_MISC_PPL_MSB
 
- THS8200_REGS_H
 
- THS8200_TST_CNTL1
 
- THS8200_TST_CNTL2
 
- THS8200_VERSION
 
- THS_HEADERCNT
 
- THS_PRE_PROGRAM_EN
 
- THS_SETTLE
 
- THS_TRAILCNT
 
- THS_ZERO_PROGRAM_EN
 
- THUMB
 
- THUNDERBOLT_H_
 
- THUNDERBOLT_SERIES
 
- THUNDERX_NODE
 
- THUNDERX_RNM_ENT_EN
 
- THUNDERX_RNM_RNG_EN
 
- THUNDER_BGX_H
 
- THUNDER_ECAM_QUIRK
 
- THUNDER_PEM_QUIRK
 
- THUNDER_PEM_RES
 
- THUNK
 
- THUNK_TARGET
 
- TH_ALERT
 
- TH_COMMAND_IN
 
- TH_COMMAND_OUT
 
- TH_CONFIGURABLE_MASTERS
 
- TH_DATA_IS_XID
 
- TH_DISCONTACT
 
- TH_FLAGS_SME_ACTIVE
 
- TH_FLAGS_SME_ACTIVE_BIT
 
- TH_HAS_PDU
 
- TH_HEADER_LENGTH
 
- TH_INTR_CD0_MASK
 
- TH_INTR_CU0_MASK
 
- TH_INTR_GD0_MASK
 
- TH_INTR_GU0_MASK
 
- TH_INTR_IGNORE_MASK
 
- TH_INTR_MD0_MASK
 
- TH_INTR_MU0_MASK
 
- TH_INTR_PD0_MASK
 
- TH_INTR_PU0_MASK
 
- TH_INTR_UP_DN_EN
 
- TH_IS_XID
 
- TH_LAST_SEG
 
- TH_LOG
 
- TH_LOG_ENABLED
 
- TH_LOG_STREAM
 
- TH_MMIO_CONFIG
 
- TH_MMIO_END
 
- TH_MMIO_RTIT
 
- TH_MMIO_SW
 
- TH_MSC_MAX
 
- TH_NUMS_TO_DRAIN
 
- TH_NVEC_MAX
 
- TH_OUTPUT_PARM
 
- TH_PCI_CONFIG_BAR
 
- TH_PCI_RTIT_BAR
 
- TH_PCI_STH_SW_BAR
 
- TH_PDU_PART
 
- TH_POSSIBLE_OUTPUTS
 
- TH_PRTY
 
- TH_RETRY
 
- TH_SEG_BLK
 
- TH_SUBDEVICE_MAX
 
- TH_SWEEP_LENGTH
 
- TH_SWEEP_REQ
 
- TH_SWEEP_RESP
 
- TI
 
- TI113X_BCR_CB_READ_DEPTH
 
- TI113X_BCR_CB_WRITE_DEPTH
 
- TI113X_BCR_PCI_READ_DEPTH
 
- TI113X_BCR_PCI_WRITE_DEPTH
 
- TI113X_BUFFER_CONTROL
 
- TI113X_CARD_CONTROL
 
- TI113X_CCR_IFG
 
- TI113X_CCR_PCI_CSC
 
- TI113X_CCR_PCI_IREQ
 
- TI113X_CCR_PCI_IRQ_ENA
 
- TI113X_CCR_RIENB
 
- TI113X_CCR_SPKROUTEN
 
- TI113X_CCR_ZVENABLE
 
- TI113X_DCR_3V_FORCE
 
- TI113X_DCR_5V_FORCE
 
- TI113X_DCR_IMODE_ISA
 
- TI113X_DCR_IMODE_MASK
 
- TI113X_DCR_IMODE_SERIAL
 
- TI113X_DEVICE_CONTROL
 
- TI113X_DMA_0
 
- TI113X_DMA_1
 
- TI113X_IO_OFFSET
 
- TI113X_RETRY_STATUS
 
- TI113X_RSR_CBRETRY
 
- TI113X_RSR_MEXP_CBA
 
- TI113X_RSR_MEXP_CBB
 
- TI113X_RSR_MEXP_PCI
 
- TI113X_RSR_PCIRETRY
 
- TI113X_RSR_TEXP_CBA
 
- TI113X_RSR_TEXP_CBB
 
- TI113X_RSR_TEXP_PCI
 
- TI113X_SCR_ASYNC_IRQ
 
- TI113X_SCR_CB_DPAR
 
- TI113X_SCR_CDMACHAN
 
- TI113X_SCR_CDMA_EN
 
- TI113X_SCR_CDREQEN
 
- TI113X_SCR_CLKRUN_ENA
 
- TI113X_SCR_CLKRUN_SEL
 
- TI113X_SCR_DELAYDOWN
 
- TI113X_SCR_DELAYUP
 
- TI113X_SCR_INTERROGATE
 
- TI113X_SCR_KEEPCLK
 
- TI113X_SCR_PWRSAVINGS
 
- TI113X_SCR_PWRSTREAM
 
- TI113X_SCR_REDUCEZV
 
- TI113X_SCR_SMIENB
 
- TI113X_SCR_SMIROUTE
 
- TI113X_SCR_SMISTATUS
 
- TI113X_SCR_SOCACTIVE
 
- TI113X_SCR_SUBSYSRW
 
- TI113X_SCR_VCCPROT
 
- TI113X_SYSTEM_CONTROL
 
- TI1220_CCR_PORT_SEL
 
- TI122X_CCR_AUD2MUX
 
- TI122X_MFUNC
 
- TI122X_MFUNC0_INTA
 
- TI122X_MFUNC0_MASK
 
- TI122X_MFUNC1_INTB
 
- TI122X_MFUNC1_MASK
 
- TI122X_MFUNC2_MASK
 
- TI122X_MFUNC3_IRQSER
 
- TI122X_MFUNC3_MASK
 
- TI122X_MFUNC4_MASK
 
- TI122X_MFUNC5_MASK
 
- TI122X_MFUNC6_MASK
 
- TI122X_SCR_CBRSVD
 
- TI122X_SCR_INTRTIE
 
- TI122X_SCR_MRBURSTDN
 
- TI122X_SCR_MRBURSTUP
 
- TI122X_SCR_RIMUX
 
- TI122X_SCR_SER_STEP
 
- TI1250_DIAGNOSTIC
 
- TI1250_DIAG_ASYNC_CSC
 
- TI1250_DIAG_PCI_CSC
 
- TI1250_DIAG_PCI_IREQ
 
- TI1250_DIAG_TRUE_VALUE
 
- TI1250_GENERAL_STATUS
 
- TI1250_GPIO0_CONTROL
 
- TI1250_GPIO1_CONTROL
 
- TI1250_GPIO2_CONTROL
 
- TI1250_GPIO3_CONTROL
 
- TI1250_GPIO_MODE_MASK
 
- TI1250_MMC_PORTSEL
 
- TI1250_MMC_ZVEN0
 
- TI1250_MMC_ZVEN1
 
- TI1250_MMC_ZVOUTEN
 
- TI1250_MULTIMEDIA_CTL
 
- TI125X_MFUNC0_INTB
 
- TI12XX_DCR_IMODE_ALL_SERIAL
 
- TI12XX_DCR_IMODE_PCI_ONLY
 
- TI16C752_FLAGS
 
- TI16C752_UARTCLK
 
- TI2
 
- TI8148_REV_ES1_0
 
- TI8148_REV_ES2_0
 
- TI8148_REV_ES2_1
 
- TI814X_CLASS
 
- TI814X_PRM_DSP_MOD
 
- TI814X_PRM_GFX_MOD
 
- TI814X_PRM_HDVICP_MOD
 
- TI814X_PRM_HDVPSS_MOD
 
- TI814X_PRM_ISP_MOD
 
- TI8168_REV_ES1_0
 
- TI8168_REV_ES1_1
 
- TI8168_REV_ES2_0
 
- TI8168_REV_ES2_1
 
- TI816X_CLASS
 
- TI816X_CM_ACTIVE_GEM_CLKDM
 
- TI816X_CM_DEFAULT_DUCATI_CLKDM
 
- TI816X_CM_DEFAULT_L3_MED_CLKDM
 
- TI816X_CM_DEFAULT_L3_SLOW_CLKDM
 
- TI816X_CM_DEFAULT_PCI_CLKDM
 
- TI816X_CM_DEFAULT_SATA_CLKDM
 
- TI816X_CM_IVAHD0_CLKDM
 
- TI816X_CM_IVAHD0_MOD
 
- TI816X_CM_IVAHD1_CLKDM
 
- TI816X_CM_IVAHD1_MOD
 
- TI816X_CM_IVAHD2_CLKDM
 
- TI816X_CM_IVAHD2_MOD
 
- TI816X_CM_SGX_CLKDM
 
- TI816X_PRM_ACTIVE_MOD
 
- TI816X_PRM_IVAHD0_MOD
 
- TI816X_PRM_IVAHD1_MOD
 
- TI816X_PRM_IVAHD2_MOD
 
- TI816X_PRM_SGX_MOD
 
- TI816X_USBPHY0_NORMAL_MODE
 
- TI816X_USBPHY_REFCLK_OSC
 
- TI81XX_ARM_INTC_BASE
 
- TI81XX_CM_ACTIVE_MOD
 
- TI81XX_CM_ALWON_L3_FAST_CLKDM
 
- TI81XX_CM_ALWON_L3_MED_CLKDM
 
- TI81XX_CM_ALWON_L3_SLOW_CLKDM
 
- TI81XX_CM_ALWON_MOD
 
- TI81XX_CM_ALWON_MPU_CLKDM
 
- TI81XX_CM_DEFAULT_MOD
 
- TI81XX_CM_ETHERNET_CLKDM
 
- TI81XX_CM_MMUCFG_CLKDM
 
- TI81XX_CM_MMU_CLKDM
 
- TI81XX_CM_SGX_MOD
 
- TI81XX_CONTROL_DEVBOOT
 
- TI81XX_CONTROL_DEVCONF
 
- TI81XX_CONTROL_DEVICE_ID
 
- TI81XX_CONTROL_STATUS
 
- TI81XX_CTRL_BASE
 
- TI81XX_GLOBAL_RST_COLD
 
- TI81XX_PM_PWSTCTRL
 
- TI81XX_PM_PWSTST
 
- TI81XX_PRCM_BASE
 
- TI81XX_PRM_ALWON_MOD
 
- TI81XX_PRM_DEFAULT_MOD
 
- TI81XX_PRM_DEVICE_MOD
 
- TI81XX_PRM_DEVICE_RSTCTRL
 
- TI81XX_RM_RSTCTRL
 
- TI81XX_SCM_BASE
 
- TI81XX_TAP_BASE
 
- TI81XX_UART1_BASE
 
- TI81XX_UART2_BASE
 
- TI81XX_UART3_BASE
 
- TIA_CF
 
- TIC
 
- TICK
 
- TICKCMP_IRQ_BIT
 
- TICKDEV_MODE_ONESHOT
 
- TICKDEV_MODE_PERIODIC
 
- TICKET_BITS
 
- TICKET_LOCK_INC
 
- TICKET_MASK
 
- TICKET_NEXT
 
- TICKET_SHIFT
 
- TICKET_SLOWPATH_FLAG
 
- TICKLE_ME
 
- TICKS_NS_SHIFT
 
- TICKS_PER_CYCLE
 
- TICKS_PER_HOUR
 
- TICKS_PER_JIFFY
 
- TICKS_PER_SEC
 
- TICKS_PER_SECOND
 
- TICKS_TO_SECS
 
- TICK_BASE_CNT
 
- TICK_BROADCAST_ENTER
 
- TICK_BROADCAST_EXIT
 
- TICK_BROADCAST_FORCE
 
- TICK_BROADCAST_OFF
 
- TICK_BROADCAST_ON
 
- TICK_CALIBRATE
 
- TICK_DEP_BIT_CLOCK_UNSTABLE
 
- TICK_DEP_BIT_PERF_EVENTS
 
- TICK_DEP_BIT_POSIX_TIMER
 
- TICK_DEP_BIT_SCHED
 
- TICK_DEP_MASK_CLOCK_UNSTABLE
 
- TICK_DEP_MASK_NONE
 
- TICK_DEP_MASK_PERF_EVENTS
 
- TICK_DEP_MASK_POSIX_TIMER
 
- TICK_DEP_MASK_SCHED
 
- TICK_DEP_NAMES
 
- TICK_DO_TIMER_BOOT
 
- TICK_DO_TIMER_NONE
 
- TICK_NSEC
 
- TICK_PRIV_BIT
 
- TICK_SCHED_REMOTE_OFFLINE
 
- TICK_SCHED_REMOTE_OFFLINING
 
- TICK_SCHED_REMOTE_RUNNING
 
- TICK_SIZE
 
- TICK_TIMER_LIMIT
 
- TICK_USEC
 
- TICR
 
- TIC_ACK_FROM_PC
 
- TIC_BIT
 
- TIC_DES_FROM_PC
 
- TIC_DES_TO_PC
 
- TIC_FTE0
 
- TIC_FTE1
 
- TIC_OWNER_FROM_PC
 
- TIC_OWNER_TO_PC
 
- TIC_R
 
- TIC_TFUE
 
- TIC_TFWE
 
- TID
 
- TIDAW_FLAGS_DATA_INT
 
- TIDAW_FLAGS_INSERT_CBC
 
- TIDAW_FLAGS_LAST
 
- TIDAW_FLAGS_SKIP
 
- TIDAW_FLAGS_TTIC
 
- TIDFLOW_ERRBITS
 
- TID_ACK_PRN
 
- TID_BIT
 
- TID_CHECK
 
- TID_CLOCKEVENT
 
- TID_CLOCKSOURCE
 
- TID_CNT
 
- TID_CNT_MASK
 
- TID_FLOW_PRN
 
- TID_FTD0
 
- TID_FTD1
 
- TID_FTD2
 
- TID_FTD3
 
- TID_G
 
- TID_MAX_LOAD_COUNT
 
- TID_MAX_TIME_DIFF
 
- TID_MFUD
 
- TID_MFWD
 
- TID_NODE_PRN
 
- TID_OP
 
- TID_OPFN_JKEY_MASK
 
- TID_OPFN_JKEY_SHIFT
 
- TID_OPFN_MAX_LEN_MASK
 
- TID_OPFN_MAX_LEN_SHIFT
 
- TID_OPFN_MAX_READ_MASK
 
- TID_OPFN_MAX_READ_SHIFT
 
- TID_OPFN_MAX_WRITE_MASK
 
- TID_OPFN_MAX_WRITE_SHIFT
 
- TID_OPFN_QP_CTXT_MASK
 
- TID_OPFN_QP_CTXT_SHIFT
 
- TID_OPFN_QP_KDETH_MASK
 
- TID_OPFN_QP_KDETH_SHIFT
 
- TID_OPFN_RESERVED_MASK
 
- TID_OPFN_RESERVED_SHIFT
 
- TID_OPFN_TIMEOUT_MASK
 
- TID_OPFN_TIMEOUT_SHIFT
 
- TID_OPFN_URG_MASK
 
- TID_OPFN_URG_SHIFT
 
- TID_OPFN_VER_MASK
 
- TID_OPFN_VER_SHIFT
 
- TID_PRIV
 
- TID_QID_G
 
- TID_QID_M
 
- TID_QID_S
 
- TID_QID_V
 
- TID_QUEUE_CELL_SPACING
 
- TID_QUEUE_MAX_SIZE
 
- TID_RDMA
 
- TID_RDMA_DEFS_H
 
- TID_RDMA_DESTQP_FLOW_MASK
 
- TID_RDMA_DESTQP_FLOW_SHIFT
 
- TID_RDMA_JKEY
 
- TID_RDMA_KDETH
 
- TID_RDMA_KDETH_DATA
 
- TID_RDMA_MAX_PAGES
 
- TID_RDMA_MAX_READ_SEGS_PER_REQ
 
- TID_RDMA_MAX_SEGMENT_SIZE
 
- TID_RDMA_MAX_WRITE_SEGS_PER_REQ
 
- TID_RDMA_MIN_SEGMENT_SIZE
 
- TID_RDMA_SEGMENT_SHIFT
 
- TID_READ_REQ_PRN
 
- TID_READ_RSP_PRN
 
- TID_READ_SENDER_PRN
 
- TID_REQUEST_ACTIVE
 
- TID_REQUEST_COMPLETE
 
- TID_REQUEST_INACTIVE
 
- TID_REQUEST_INIT
 
- TID_REQUEST_INIT_RESEND
 
- TID_REQUEST_QUEUED
 
- TID_REQUEST_RESEND
 
- TID_REQUEST_RESEND_ACTIVE
 
- TID_REQUEST_RNR_NAK
 
- TID_REQUEST_SYNC
 
- TID_REQ_PRN
 
- TID_RESYNC_PRN
 
- TID_RNR_NAK_INIT
 
- TID_RNR_NAK_SEND
 
- TID_RNR_NAK_SENT
 
- TID_ROUND_VALUE
 
- TID_STEP
 
- TID_TDPD0
 
- TID_TDPD1
 
- TID_TDPD2
 
- TID_TDPD3
 
- TID_TFUD
 
- TID_TFWD
 
- TID_TID_G
 
- TID_TID_M
 
- TID_TID_S
 
- TID_TID_V
 
- TID_TO_WME_AC
 
- TID_UNIT
 
- TID_UNIT_MASK
 
- TID_URO
 
- TID_URW
 
- TID_WINDOW_SZ
 
- TID_WRITE_DATA_PRN
 
- TID_WRITE_REQ_PRN
 
- TID_WRITE_RSPDR_PRN
 
- TID_WRITE_RSP_PRN
 
- TID_WRITE_SENDER_PRN
 
- TIE
 
- TIEQINPARERRINT_F
 
- TIEQINPARERRINT_S
 
- TIEQINPARERRINT_V
 
- TIEQOUTPARERRINT_F
 
- TIEQOUTPARERRINT_S
 
- TIEQOUTPARERRINT_V
 
- TIER
 
- TIER_DISABLE
 
- TIER_TCIEU
 
- TIER_TCIEV
 
- TIER_TGIEA
 
- TIER_TGIEB
 
- TIER_TGIEC
 
- TIER_TGIED
 
- TIER_TTGE
 
- TIER_TTGE2
 
- TIE_BIT
 
- TIE_FTS0
 
- TIE_FTS1
 
- TIE_FTS2
 
- TIE_FTS3
 
- TIE_MFUS
 
- TIE_MFWS
 
- TIE_TDPS0
 
- TIE_TDPS1
 
- TIE_TDPS2
 
- TIE_TDPS3
 
- TIE_TFUS
 
- TIE_TFWS
 
- TIFM_CTRL_FAST_CLK
 
- TIFM_CTRL_LED
 
- TIFM_CTRL_POWER_MASK
 
- TIFM_DMA_EN
 
- TIFM_DMA_RESET
 
- TIFM_DMA_TSIZE
 
- TIFM_DMA_TX
 
- TIFM_FIFO_ENABLE
 
- TIFM_FIFO_INTMASK
 
- TIFM_FIFO_INT_SETALL
 
- TIFM_FIFO_MORE
 
- TIFM_FIFO_READY
 
- TIFM_IRQ_CARDMASK
 
- TIFM_IRQ_ENABLE
 
- TIFM_IRQ_FIFOMASK
 
- TIFM_IRQ_SETALL
 
- TIFM_IRQ_SOCKMASK
 
- TIFM_MMCSD_4BBUS
 
- TIFM_MMCSD_AE
 
- TIFM_MMCSD_AF
 
- TIFM_MMCSD_BRS
 
- TIFM_MMCSD_BUFINT
 
- TIFM_MMCSD_CARD_RO
 
- TIFM_MMCSD_CB
 
- TIFM_MMCSD_CCRC
 
- TIFM_MMCSD_CD
 
- TIFM_MMCSD_CERR
 
- TIFM_MMCSD_CIRQ
 
- TIFM_MMCSD_CLKMASK
 
- TIFM_MMCSD_CMD_AC
 
- TIFM_MMCSD_CMD_ADTC
 
- TIFM_MMCSD_CMD_BC
 
- TIFM_MMCSD_CMD_BCR
 
- TIFM_MMCSD_CTO
 
- TIFM_MMCSD_DCRC
 
- TIFM_MMCSD_DPE
 
- TIFM_MMCSD_DTO
 
- TIFM_MMCSD_EOC
 
- TIFM_MMCSD_EOFB
 
- TIFM_MMCSD_ERRMASK
 
- TIFM_MMCSD_FIFO_SIZE
 
- TIFM_MMCSD_INAB
 
- TIFM_MMCSD_MAX_BLOCK_SIZE
 
- TIFM_MMCSD_OCRB
 
- TIFM_MMCSD_ODTO
 
- TIFM_MMCSD_POWER
 
- TIFM_MMCSD_READ
 
- TIFM_MMCSD_RESET
 
- TIFM_MMCSD_RSP_BUSY
 
- TIFM_MMCSD_RSP_R0
 
- TIFM_MMCSD_RSP_R1
 
- TIFM_MMCSD_RSP_R2
 
- TIFM_MMCSD_RSP_R3
 
- TIFM_MMCSD_RSP_R4
 
- TIFM_MMCSD_RSP_R5
 
- TIFM_MMCSD_RSP_R6
 
- TIFM_MMCSD_RXDE
 
- TIFM_MMCSD_TXDE
 
- TIFM_MS_STAT_BRQ
 
- TIFM_MS_STAT_CED
 
- TIFM_MS_STAT_CNK
 
- TIFM_MS_STAT_CRC
 
- TIFM_MS_STAT_DRQ
 
- TIFM_MS_STAT_EMP
 
- TIFM_MS_STAT_ERR
 
- TIFM_MS_STAT_FUL
 
- TIFM_MS_STAT_MSINT
 
- TIFM_MS_STAT_RDY
 
- TIFM_MS_STAT_TOE
 
- TIFM_MS_SYS_BSY_MASK
 
- TIFM_MS_SYS_DAM
 
- TIFM_MS_SYS_DMA
 
- TIFM_MS_SYS_DRM
 
- TIFM_MS_SYS_DRQSL
 
- TIFM_MS_SYS_FCLR
 
- TIFM_MS_SYS_FDIR
 
- TIFM_MS_SYS_FIFO
 
- TIFM_MS_SYS_INTCLR
 
- TIFM_MS_SYS_INTEN
 
- TIFM_MS_SYS_MSIEN
 
- TIFM_MS_SYS_NOCRC
 
- TIFM_MS_SYS_REI
 
- TIFM_MS_SYS_REO
 
- TIFM_MS_SYS_RESET
 
- TIFM_MS_SYS_SRAC
 
- TIFM_SOCK_STATE_OCCUPIED
 
- TIFM_SOCK_STATE_POWERED
 
- TIFM_TYPE_MS
 
- TIFM_TYPE_SD
 
- TIFM_TYPE_XD
 
- TIF_31BIT
 
- TIF_32BIT
 
- TIF_32BIT_ADDR
 
- TIF_32BIT_FPREGS
 
- TIF_32BIT_REGS
 
- TIF_ADDR32
 
- TIF_ALLWORK_MASK
 
- TIF_BLOCKSTEP
 
- TIF_BLOCK_STEP
 
- TIF_DB_DISABLED
 
- TIF_DELAYED_TRACE
 
- TIF_DIE_IF_KERNEL
 
- TIF_ELF2ABI
 
- TIF_EMULATE_STACK_STORE
 
- TIF_FIXADE
 
- TIF_FORCED_TF
 
- TIF_FOREIGN_FPSTATE
 
- TIF_FPUBOUND
 
- TIF_FREEZE
 
- TIF_FSCHECK
 
- TIF_GUARDED_STORAGE
 
- TIF_HYBRID_FPREGS
 
- TIF_IA32
 
- TIF_IO_BITMAP
 
- TIF_ISOLATE_BP
 
- TIF_ISOLATE_BP_GUEST
 
- TIF_LAZY_MMU_UPDATES
 
- TIF_LOAD_WATCH
 
- TIF_LOGADE
 
- TIF_MCA_INIT
 
- TIF_MCDPER
 
- TIF_MEMDIE
 
- TIF_MSA_CTX_LIVE
 
- TIF_NEED_FPU_LOAD
 
- TIF_NEED_RESCHED
 
- TIF_NOCPUID
 
- TIF_NOERROR
 
- TIF_NOHZ
 
- TIF_NOTIFY_RESUME
 
- TIF_NOTSC
 
- TIF_PATCH_PENDING
 
- TIF_PGSTE
 
- TIF_POLLING_NRFLAG
 
- TIF_RESTART_BLOCK
 
- TIF_RESTOREALL
 
- TIF_RESTORE_RSE
 
- TIF_RESTORE_SIGMASK
 
- TIF_RESTORE_TM
 
- TIF_SECCOMP
 
- TIF_SIGPENDING
 
- TIF_SINGLESTEP
 
- TIF_SINGLE_STEP
 
- TIF_SPEC_FORCE_UPDATE
 
- TIF_SPEC_IB
 
- TIF_SSBD
 
- TIF_SVE
 
- TIF_SVE_VL_INHERIT
 
- TIF_SYSCALL_AUDIT
 
- TIF_SYSCALL_EMU
 
- TIF_SYSCALL_TRACE
 
- TIF_SYSCALL_TRACEPOINT
 
- TIF_TAGGED_ADDR
 
- TIF_UNALIGNED
 
- TIF_UPROBE
 
- TIF_UPROBE_SINGLESTEP
 
- TIF_USEDFPU
 
- TIF_USEDMSA
 
- TIF_USER_RETURN_NOTIFY
 
- TIF_USING_IWMMXT
 
- TIF_WORK_MASK
 
- TIF_X32
 
- TIGER_AUX_CTRL
 
- TIGER_AUX_DATA
 
- TIGER_AUX_IRQMASK
 
- TIGER_AUX_STATUS
 
- TIGER_EXTERN_RESET
 
- TIGER_EXTERN_RESET_OFF
 
- TIGER_EXTERN_RESET_ON
 
- TIGER_IOMASK
 
- TIGER_IPAC_ALE
 
- TIGER_IPAC_PORT
 
- TIGER_IRQ_BIT
 
- TIGER_RESET_ADDR
 
- TIGHT_CBR_MAX
 
- TIGON_I_TX_RING_ENTRIES
 
- TILCDC_DEFAULT_MAX_BANDWIDTH
 
- TILCDC_DEFAULT_MAX_PIXELCLOCK
 
- TILCDC_DEFAULT_MAX_WIDTH
 
- TILCDC_PALETTE_FIRST_ENTRY
 
- TILCDC_PALETTE_SIZE
 
- TILCDC_VBLANK_SAFETY_THRESHOLD_US
 
- TILE2RASTESCAN_BYPASS_MODE
 
- TILE4_2
 
- TILE4_3
 
- TILE4_LINEAR
 
- TILE5_2
 
- TILE5_3
 
- TILE5_LINEAR
 
- TILE6_2
 
- TILE6_3
 
- TILE6_LINEAR
 
- TILECTL
 
- TILECTL_BACKSNOOP_DIS
 
- TILECTL_SWZCTL
 
- TILECTL_TLBPF
 
- TILECTL_TLB_PREFETCH_DIS
 
- TILER_HEIGHT
 
- TILER_PAGE
 
- TILER_PWRACTIVE_HI
 
- TILER_PWRACTIVE_LO
 
- TILER_PWROFF_HI
 
- TILER_PWROFF_LO
 
- TILER_PWRON_HI
 
- TILER_PWRON_LO
 
- TILER_PWRTRANS_HI
 
- TILER_PWRTRANS_LO
 
- TILER_READY_HI
 
- TILER_READY_LO
 
- TILER_WIDTH
 
- TILES_IN_X_LSB_SHIFT
 
- TILES_IN_X_MSB_SHIFT
 
- TILES_IN_X_SHIFT
 
- TILEWALK_X
 
- TILEWALK_Y
 
- TILE_32X32
 
- TILE_FLUSH
 
- TILE_MASK
 
- TILE_SHIFT
 
- TILE_SIZE
 
- TILE_SIZE_16
 
- TILE_SIZE_32
 
- TILE_SIZE_8
 
- TILE_SPLIT
 
- TILFMT_16BIT
 
- TILFMT_32BIT
 
- TILFMT_8BIT
 
- TILFMT_NFORMATS
 
- TILFMT_PAGE
 
- TILING_MASK
 
- TILING_MODE_COUNT
 
- TILING_MODE_INVALID
 
- TILING_MODE_LINEAR
 
- TILING_MODE_TILED
 
- TILVIEW_16BIT
 
- TILVIEW_32BIT
 
- TILVIEW_8BIT
 
- TILVIEW_END
 
- TILVIEW_PAGE
 
- TIL_ADDR
 
- TIM1
 
- TIM10_OC1
 
- TIM11_OC1
 
- TIM12
 
- TIM12RS_UNRESET
 
- TIM12_CH1
 
- TIM12_CH2
 
- TIM12_CK
 
- TIM12_K
 
- TIM12_R
 
- TIM12_TRGO
 
- TIM13
 
- TIM13_CK
 
- TIM13_K
 
- TIM13_OC1
 
- TIM13_R
 
- TIM14
 
- TIM14_CK
 
- TIM14_K
 
- TIM14_OC1
 
- TIM14_R
 
- TIM15
 
- TIM15_CK
 
- TIM15_K
 
- TIM15_R
 
- TIM15_TRGO
 
- TIM16
 
- TIM16_CK
 
- TIM16_K
 
- TIM16_OC1
 
- TIM16_R
 
- TIM17
 
- TIM17_CK
 
- TIM17_K
 
- TIM17_OC1
 
- TIM17_R
 
- TIM1_CH1
 
- TIM1_CH2
 
- TIM1_CH3
 
- TIM1_CH4
 
- TIM1_CK
 
- TIM1_K
 
- TIM1_R
 
- TIM1_TRGO
 
- TIM1_TRGO2
 
- TIM2
 
- TIM2_ACB_MASK
 
- TIM2_BCD
 
- TIM2_CH1
 
- TIM2_CH2
 
- TIM2_CH3
 
- TIM2_CH4
 
- TIM2_CK
 
- TIM2_CLKSEL
 
- TIM2_IHS
 
- TIM2_IOE
 
- TIM2_IPC
 
- TIM2_IVS
 
- TIM2_K
 
- TIM2_PCD_HI_BITS
 
- TIM2_PCD_HI_MASK
 
- TIM2_PCD_HI_SHIFT
 
- TIM2_PCD_LO_BITS
 
- TIM2_PCD_LO_MASK
 
- TIM2_R
 
- TIM2_TRGO
 
- TIM3
 
- TIM34
 
- TIM34RS_UNRESET
 
- TIM3_CH1
 
- TIM3_CH2
 
- TIM3_CH3
 
- TIM3_CH4
 
- TIM3_CK
 
- TIM3_K
 
- TIM3_R
 
- TIM3_TRGO
 
- TIM4
 
- TIM4_CH1
 
- TIM4_CH2
 
- TIM4_CH3
 
- TIM4_CH4
 
- TIM4_CK
 
- TIM4_K
 
- TIM4_R
 
- TIM4_TRGO
 
- TIM5
 
- TIM5_CH1
 
- TIM5_CH2
 
- TIM5_CH3
 
- TIM5_CH4
 
- TIM5_CK
 
- TIM5_K
 
- TIM5_R
 
- TIM5_TRGO
 
- TIM6
 
- TIM6_CK
 
- TIM6_K
 
- TIM6_R
 
- TIM6_TRGO
 
- TIM7
 
- TIM7_CK
 
- TIM7_K
 
- TIM7_R
 
- TIM7_TRGO
 
- TIM8
 
- TIM8_CH1
 
- TIM8_CH2
 
- TIM8_CH3
 
- TIM8_CH4
 
- TIM8_CK
 
- TIM8_K
 
- TIM8_R
 
- TIM8_TRGO
 
- TIM8_TRGO2
 
- TIM9_CH1
 
- TIM9_CH2
 
- TIM9_TRGO
 
- TIMBDMA_32BIT_ADDR
 
- TIMBDMA_ACR
 
- TIMBDMA_IER
 
- TIMBDMA_INSTANCE_OFFSET
 
- TIMBDMA_INSTANCE_TX_OFFSET
 
- TIMBDMA_IPR
 
- TIMBDMA_ISR
 
- TIMBDMA_OFFS_RX_BLR
 
- TIMBDMA_OFFS_RX_BPRR
 
- TIMBDMA_OFFS_RX_DHAR
 
- TIMBDMA_OFFS_RX_DLAR
 
- TIMBDMA_OFFS_RX_ER
 
- TIMBDMA_OFFS_RX_LR
 
- TIMBDMA_OFFS_TX_BLR
 
- TIMBDMA_OFFS_TX_DHAR
 
- TIMBDMA_OFFS_TX_DLAR
 
- TIMBDMA_OFFS_TX_LR
 
- TIMBDMA_RX_EN
 
- TIMBERDALE_NR_IRQS
 
- TIMBUART_BAUDRATE
 
- TIMBUART_CTRL
 
- TIMBUART_CTRL_CTS
 
- TIMBUART_CTRL_FLSHRX
 
- TIMBUART_CTRL_FLSHTX
 
- TIMBUART_CTRL_RTS
 
- TIMBUART_FIFO_SIZE
 
- TIMBUART_IER
 
- TIMBUART_IPR
 
- TIMBUART_ISR
 
- TIMBUART_MAJOR
 
- TIMBUART_MINOR
 
- TIMBUART_RXFIFO
 
- TIMBUART_TXFIFO
 
- TIMB_DMA_DESC_SIZE
 
- TIMB_HW_CONFIG
 
- TIMB_HW_CONFIG_SPI_8BIT
 
- TIMB_HW_VER0
 
- TIMB_HW_VER1
 
- TIMB_HW_VER2
 
- TIMB_HW_VER3
 
- TIMB_HW_VER_MASK
 
- TIMB_REQUIRED_MINOR
 
- TIMB_REV_MAJOR
 
- TIMB_REV_MINOR
 
- TIMB_SUPPORTED_MAJOR
 
- TIMB_SW_RST
 
- TIME
 
- TIME0COUNTERDSP0
 
- TIME0COUNTERDSP1
 
- TIME0COUNTERDSP2
 
- TIME0COUNTERDSP3
 
- TIME0PERENBDSP0
 
- TIME0PERENBDSP1
 
- TIME0PERENBDSP2
 
- TIME0PERENBDSP3
 
- TIME1COUNTERDSP0
 
- TIME1COUNTERDSP1
 
- TIME1COUNTERDSP2
 
- TIME1COUNTERDSP3
 
- TIME1PERENBDSP0
 
- TIME1PERENBDSP1
 
- TIME1PERENBDSP2
 
- TIME1PERENBDSP3
 
- TIME2COUNTERDSP0
 
- TIME2COUNTERDSP1
 
- TIME2COUNTERDSP2
 
- TIME2COUNTERDSP3
 
- TIME2PERENBDSP0
 
- TIME2PERENBDSP1
 
- TIME2PERENBDSP2
 
- TIME2PERENBDSP3
 
- TIME3COUNTERDSP0
 
- TIME3COUNTERDSP1
 
- TIME3COUNTERDSP2
 
- TIME3COUNTERDSP3
 
- TIME3PERENBDSP0
 
- TIME3PERENBDSP1
 
- TIME3PERENBDSP2
 
- TIME3PERENBDSP3
 
- TIME64_MAX
 
- TIME64_MIN
 
- TIMEBASE_1_NS
 
- TIMEBASE_2_NS
 
- TIMECENT_RATIO
 
- TIMECODES
 
- TIMECSR
 
- TIMECSR2
 
- TIMECSR3
 
- TIMECSR_BEACON_EXPECT
 
- TIMECSR_US_64_COUNT
 
- TIMECSR_US_COUNT
 
- TIMEDOUT
 
- TIMED_CHECKER
 
- TIMED_DISCONNECT
 
- TIMED_OUT_MSG
 
- TIMEGAP_USEC_MAX
 
- TIMEGAP_USEC_MIN
 
- TIMEINGUEST
 
- TIMEOUT
 
- TIMEOUTINT_F
 
- TIMEOUTINT_S
 
- TIMEOUTINT_V
 
- TIMEOUTMAINT_F
 
- TIMEOUTMAINT_S
 
- TIMEOUTMAINT_V
 
- TIMEOUTSB4RESET
 
- TIMEOUT_100_MS
 
- TIMEOUT_250MS
 
- TIMEOUT_8051_START
 
- TIMEOUT_AST2150
 
- TIMEOUT_CODE_TO_US
 
- TIMEOUT_COUNT
 
- TIMEOUT_DEFAULT_BOOT_MS
 
- TIMEOUT_DEFAULT_IPC_MS
 
- TIMEOUT_ERROR
 
- TIMEOUT_FOR_FW_RDY_MS
 
- TIMEOUT_FOR_HW_RDY_MS
 
- TIMEOUT_FOR_INPUT_RDY_MS
 
- TIMEOUT_H
 
- TIMEOUT_MAX
 
- TIMEOUT_MIN
 
- TIMEOUT_MS
 
- TIMEOUT_MSEC
 
- TIMEOUT_NO_KEEPALIVE
 
- TIMEOUT_PERIOD_VALUE
 
- TIMEOUT_POLL
 
- TIMEOUT_POWER_UP
 
- TIMEOUT_SECONDARY_MS_MAC
 
- TIMEOUT_SEMAPHORE
 
- TIMEOUT_SEMAPHORE_FORCE
 
- TIMEOUT_SET_PROPERTY
 
- TIMEOUT_SPINS_MAC
 
- TIMEOUT_STEP
 
- TIMEOUT_TBI
 
- TIMEOUT_TDL
 
- TIMEOUT_TIME
 
- TIMEOUT_TOTAL_ELAPSED
 
- TIMEOUT_TSL
 
- TIMEOUT_TX_TUNE
 
- TIMEOUT_TX_TUNE_POWER
 
- TIMEOUT_US
 
- TIMEOUT_USEC
 
- TIMEOUT_USEC_SHORT_SEMA_BLOCKING
 
- TIMEOUT_US_TO_CODE
 
- TIMEOUT_VALUE
 
- TIMEPERFRAME_AVG_FPS
 
- TIMER
 
- TIMER0
 
- TIMER0INT_F
 
- TIMER0INT_S
 
- TIMER0INT_V
 
- TIMER0RX_OFFSET
 
- TIMER0TX_OFFSET
 
- TIMER0_25MHZ
 
- TIMER0_BASE_ADDR
 
- TIMER0_CLR_MASK
 
- TIMER0_CTRL_IE
 
- TIMER0_CTRL_NH
 
- TIMER0_DIV
 
- TIMER0_EN
 
- TIMER0_IRQ
 
- TIMER0_RELOAD
 
- TIMER0_RELOAD_EN
 
- TIMER0_RELOAD_OFF
 
- TIMER0_VAL
 
- TIMER0_VAL_OFF
 
- TIMER1
 
- TIMER10_BASE
 
- TIMER10_IRQ_IDX
 
- TIMER11_EN
 
- TIMER1A
 
- TIMER1B
 
- TIMER1RX_OFFSET
 
- TIMER1TX_OFFSET
 
- TIMER1_25MHZ
 
- TIMER1_2_CONTROL_OFFSET
 
- TIMER1_2_INTERRUPT_MASK_OFFSET
 
- TIMER1_2_INTERRUPT_STATUS_OFFSET
 
- TIMER1_AUTO_RELOAD_OFFSET
 
- TIMER1_BASE
 
- TIMER1_CLR_MASK
 
- TIMER1_COUNT
 
- TIMER1_COUNTER_OFFSET
 
- TIMER1_DIV
 
- TIMER1_EN
 
- TIMER1_ENABLE_BIT
 
- TIMER1_FIXED_ENABLE_BIT
 
- TIMER1_IRQ_IDX
 
- TIMER1_LOAD
 
- TIMER1_MATCH1
 
- TIMER1_MATCH2
 
- TIMER1_MATCH_V1_OFFSET
 
- TIMER1_MATCH_V2_OFFSET
 
- TIMER1_REG_OFFSET
 
- TIMER1_RELOAD
 
- TIMER1_RELOAD_EN
 
- TIMER1_RELOAD_OFF
 
- TIMER1_STATUS_BIT
 
- TIMER1_VAL
 
- TIMER1_VAL_OFF
 
- TIMER2
 
- TIMER2A
 
- TIMER2B
 
- TIMER2_AUTO_RELOAD_OFFSET
 
- TIMER2_BASE
 
- TIMER2_COUNT
 
- TIMER2_COUNTER_OFFSET
 
- TIMER2_LOAD
 
- TIMER2_MATCH1
 
- TIMER2_MATCH2
 
- TIMER2_MATCH_V1_OFFSET
 
- TIMER2_MATCH_V2_OFFSET
 
- TIMER2_REG_OFFSET
 
- TIMER3
 
- TIMER3A
 
- TIMER3B
 
- TIMER3_BASE
 
- TIMER3_COUNT
 
- TIMER3_DEFAULT_VALUE
 
- TIMER3_LOAD
 
- TIMER3_MATCH1
 
- TIMER3_MATCH2
 
- TIMER4_BASE
 
- TIMER64
 
- TIMER64_MODE_DISABLED
 
- TIMER64_MODE_ONE_SHOT
 
- TIMER64_MODE_PERIODIC
 
- TIMER64_RATE
 
- TIMERCOUNT
 
- TIMERINI_MASK
 
- TIMERINI_MASK_SFT
 
- TIMERINI_SFT
 
- TIMERMODE_G
 
- TIMERMODE_M
 
- TIMERMODE_S
 
- TIMERREG_COUNTER0_X
 
- TIMERREG_S
 
- TIMERREG_V
 
- TIMERRESOLUTION_G
 
- TIMERRESOLUTION_M
 
- TIMERRESOLUTION_S
 
- TIMERS1_VIRT_BASE
 
- TIMERS2_VIRT_BASE
 
- TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG
 
- TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT
 
- TIMERS_CONTEXT_ACTIVELC0_MASK
 
- TIMERS_CONTEXT_ACTIVELC0_SHIFT
 
- TIMERS_CONTEXT_ACTIVELC1_MASK
 
- TIMERS_CONTEXT_ACTIVELC1_SHIFT
 
- TIMERS_CONTEXT_ACTIVELC2_MASK
 
- TIMERS_CONTEXT_ACTIVELC2_SHIFT
 
- TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK
 
- TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT
 
- TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK
 
- TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT
 
- TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK
 
- TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT
 
- TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK
 
- TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_SHIFT
 
- TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK
 
- TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT
 
- TIMERS_CONTEXT_RESERVED0_MASK
 
- TIMERS_CONTEXT_RESERVED0_SHIFT
 
- TIMERS_CONTEXT_RESERVED1_MASK
 
- TIMERS_CONTEXT_RESERVED1_SHIFT
 
- TIMERS_CONTEXT_RESERVED2_MASK
 
- TIMERS_CONTEXT_RESERVED2_SHIFT
 
- TIMERS_CONTEXT_RESERVED3_MASK
 
- TIMERS_CONTEXT_RESERVED3_SHIFT
 
- TIMERS_CONTEXT_RESERVED4_MASK
 
- TIMERS_CONTEXT_RESERVED4_SHIFT
 
- TIMERS_CONTEXT_RESERVED5_MASK
 
- TIMERS_CONTEXT_RESERVED5_SHIFT
 
- TIMERS_CONTEXT_RESERVED6_MASK
 
- TIMERS_CONTEXT_RESERVED6_SHIFT
 
- TIMERS_CONTEXT_RESERVED7_MASK
 
- TIMERS_CONTEXT_RESERVED7_SHIFT
 
- TIMERS_CONTEXT_VALIDLC0_MASK
 
- TIMERS_CONTEXT_VALIDLC0_SHIFT
 
- TIMERS_CONTEXT_VALIDLC1_MASK
 
- TIMERS_CONTEXT_VALIDLC1_SHIFT
 
- TIMERS_CONTEXT_VALIDLC2_MASK
 
- TIMERS_CONTEXT_VALIDLC2_SHIFT
 
- TIMERS_PER_GROUP
 
- TIMERS_TICK_SIZE_CHIP
 
- TIMERS_VIRT_BASE
 
- TIMERTICK
 
- TIMERUS_CNTR_1US
 
- TIMERUS_CNTR_FREEZE
 
- TIMERUS_USEC_CFG
 
- TIMERVALUE0_G
 
- TIMERVALUE0_M
 
- TIMERVALUE0_S
 
- TIMERVALUE0_V
 
- TIMERVALUE1_G
 
- TIMERVALUE1_M
 
- TIMERVALUE1_S
 
- TIMERVALUE1_V
 
- TIMERVALUE2_G
 
- TIMERVALUE2_M
 
- TIMERVALUE2_S
 
- TIMERVALUE2_V
 
- TIMERVALUE3_G
 
- TIMERVALUE3_M
 
- TIMERVALUE3_S
 
- TIMERVALUE3_V
 
- TIMERVALUE4_G
 
- TIMERVALUE4_M
 
- TIMERVALUE4_S
 
- TIMERVALUE4_V
 
- TIMERVALUE5_G
 
- TIMERVALUE5_M
 
- TIMERVALUE5_S
 
- TIMERVALUE5_V
 
- TIMER_1MHz
 
- TIMER_1_BASE
 
- TIMER_1_CR_ASPEED_CLOCK
 
- TIMER_1_CR_ASPEED_ENABLE
 
- TIMER_1_CR_ASPEED_INT
 
- TIMER_1_CR_CLOCK
 
- TIMER_1_CR_ENABLE
 
- TIMER_1_CR_INT
 
- TIMER_1_CR_UPDOWN
 
- TIMER_1_INT_MATCH1
 
- TIMER_1_INT_MATCH2
 
- TIMER_1_INT_OVERFLOW
 
- TIMER_2_BASE
 
- TIMER_2_CR_ASPEED_CLOCK
 
- TIMER_2_CR_ASPEED_ENABLE
 
- TIMER_2_CR_ASPEED_INT
 
- TIMER_2_CR_CLOCK
 
- TIMER_2_CR_ENABLE
 
- TIMER_2_CR_INT
 
- TIMER_2_CR_UPDOWN
 
- TIMER_2_INT_MATCH1
 
- TIMER_2_INT_MATCH2
 
- TIMER_2_INT_OVERFLOW
 
- TIMER_3_CR_ASPEED_CLOCK
 
- TIMER_3_CR_ASPEED_ENABLE
 
- TIMER_3_CR_ASPEED_INT
 
- TIMER_3_CR_CLOCK
 
- TIMER_3_CR_ENABLE
 
- TIMER_3_CR_INT
 
- TIMER_3_CR_UPDOWN
 
- TIMER_3_INT_MATCH1
 
- TIMER_3_INT_MATCH2
 
- TIMER_3_INT_OVERFLOW
 
- TIMER_A
 
- TIMER_A370_STATUS
 
- TIMER_ABSTIME
 
- TIMER_ACPI_DECLARE
 
- TIMER_ALARM_HIGH
 
- TIMER_ALARM_LOW
 
- TIMER_ALARM_STATUS
 
- TIMER_ARRAYMASK
 
- TIMER_ARRAYSHIFT
 
- TIMER_ASYNC_OFF
 
- TIMER_ASYNC_SHRINK
 
- TIMER_AS_VAL
 
- TIMER_A_CONTROL
 
- TIMER_A_COUNT
 
- TIMER_A_ENABLE_COUNT
 
- TIMER_A_ENABLE_WATCHDOG
 
- TIMER_B
 
- TIMER_BASE
 
- TIMER_BASEMASK
 
- TIMER_BGLOAD
 
- TIMER_BITS
 
- TIMER_BY_128K
 
- TIMER_BY_1M
 
- TIMER_BY_256K
 
- TIMER_BY_32K
 
- TIMER_C
 
- TIMER_CB
 
- TIMER_CCD
 
- TIMER_CFG
 
- TIMER_CLEAR
 
- TIMER_CLEAR_ALARM
 
- TIMER_CLEAR_INTERRUPT
 
- TIMER_CLEAR_REG
 
- TIMER_CLK
 
- TIMER_CLK_EVT
 
- TIMER_CLK_RST
 
- TIMER_CLK_SRC
 
- TIMER_CLOCK_DIV
 
- TIMER_CLRINT_REG
 
- TIMER_CLR_ON_MATCH
 
- TIMER_CNTL_AUTORELOAD
 
- TIMER_CNTL_CNTEXT
 
- TIMER_CNTL_DIV1
 
- TIMER_CNTL_DIV16
 
- TIMER_CNTL_DIV256
 
- TIMER_CNTL_ENABLE
 
- TIMER_CNTVAL_HI_REG
 
- TIMER_CNTVAL_LO_REG
 
- TIMER_CNTVAL_REG
 
- TIMER_CNT_MASK
 
- TIMER_CONFIG
 
- TIMER_CONTRL
 
- TIMER_CONTROL
 
- TIMER_CONTROL_REG3288
 
- TIMER_CONTROL_REG3399
 
- TIMER_COUNT
 
- TIMER_COUNTDOWN_ENABLE
 
- TIMER_COUNT_R_ACTIVE
 
- TIMER_COUNT_VAL
 
- TIMER_COUNT_W_ACTIVE
 
- TIMER_CPUMASK
 
- TIMER_CR
 
- TIMER_CTL
 
- TIMER_CTL0_REG
 
- TIMER_CTL1_REG
 
- TIMER_CTL2_REG
 
- TIMER_CTL_64BIT_WIDTH
 
- TIMER_CTL_CLK_PRES
 
- TIMER_CTL_CLK_SRC
 
- TIMER_CTL_CLK_SRC_OSC24M
 
- TIMER_CTL_COUNTDOWN_MASK
 
- TIMER_CTL_ENABLE
 
- TIMER_CTL_ENABLE_MASK
 
- TIMER_CTL_MONOTONIC_MASK
 
- TIMER_CTL_ONESHOT
 
- TIMER_CTL_PERIOD_MODE
 
- TIMER_CTL_REG
 
- TIMER_CTL_RELOAD
 
- TIMER_CTLx_REG
 
- TIMER_CTRL
 
- TIMER_CTRL_32BIT
 
- TIMER_CTRL_DIV1
 
- TIMER_CTRL_DIV16
 
- TIMER_CTRL_DIV256
 
- TIMER_CTRL_ENABLE
 
- TIMER_CTRL_IE
 
- TIMER_CTRL_NH
 
- TIMER_CTRL_OFF
 
- TIMER_CTRL_ONESHOT
 
- TIMER_CTRL_PERIODIC
 
- TIMER_CTRL_REG
 
- TIMER_CTRL_VAL
 
- TIMER_CURRENT_OVERFLOW_VALUE
 
- TIMER_CURRENT_VALUE
 
- TIMER_CURRENT_VALUE0
 
- TIMER_CURRENT_VALUE1
 
- TIMER_CURR_REG
 
- TIMER_D
 
- TIMER_DEFERRABLE
 
- TIMER_DISABLE
 
- TIMER_DIV
 
- TIMER_DIV1
 
- TIMER_DIV16
 
- TIMER_DIV256
 
- TIMER_DIVIDER
 
- TIMER_DIVIDER_SHIFT
 
- TIMER_DIVISOR
 
- TIMER_DONE
 
- TIMER_DOWNCOUNT_VAL
 
- TIMER_E
 
- TIMER_EN
 
- TIMER_ENABLE
 
- TIMER_ENABLE_CLR_ON_MATCH_EN
 
- TIMER_ENABLE_EN
 
- TIMER_ENTRY_STATIC
 
- TIMER_EVENT
 
- TIMER_EVENTS_STATUS
 
- TIMER_F
 
- TIMER_FREERUN_CONTROL_OFFSET
 
- TIMER_FREERUN_OFFSET
 
- TIMER_FREQ
 
- TIMER_G
 
- TIMER_H
 
- TIMER_IAA_WATCHDOG
 
- TIMER_IER_VAL
 
- TIMER_INI
 
- TIMER_INT
 
- TIMER_INTCLR
 
- TIMER_INTERVAL
 
- TIMER_INTERVAL_NSEC
 
- TIMER_INTERVAL_RADIOCHK
 
- TIMER_INTERVAL_WATCHDOG
 
- TIMER_INTR_ALL
 
- TIMER_INTR_MASK
 
- TIMER_INTR_MSK
 
- TIMER_INTR_STATE
 
- TIMER_INTVAL_HI_REG
 
- TIMER_INTVAL_LO_REG
 
- TIMER_INTVAL_REG
 
- TIMER_INT_ALL_MASK
 
- TIMER_INT_CLR
 
- TIMER_INT_EN
 
- TIMER_INT_MASK_STS
 
- TIMER_INT_RAW_STS
 
- TIMER_INT_STATUS
 
- TIMER_INT_UNMASK
 
- TIMER_IO_WATCHDOG
 
- TIMER_IRQ
 
- TIMER_IRQSAFE
 
- TIMER_IRQSTAT_REG
 
- TIMER_IRQSTAT_TIMER0_CAUSE
 
- TIMER_IRQSTAT_TIMER0_IR_EN
 
- TIMER_IRQSTAT_TIMER1_CAUSE
 
- TIMER_IRQSTAT_TIMER1_IR_EN
 
- TIMER_IRQSTAT_TIMER2_CAUSE
 
- TIMER_IRQSTAT_TIMER2_IR_EN
 
- TIMER_IRQSTAT_TIMER_CAUSE
 
- TIMER_IRQSTAT_TIMER_IR_EN
 
- TIMER_IRQSTAT_WDT_CAUSE
 
- TIMER_IRQ_ACK
 
- TIMER_IRQ_CLEAR
 
- TIMER_IRQ_EN
 
- TIMER_IRQ_ENABLE
 
- TIMER_IRQ_ENABLED
 
- TIMER_IRQ_EN_REG
 
- TIMER_IRQ_MASK
 
- TIMER_IRQ_STATUS
 
- TIMER_IRQ_ST_REG
 
- TIMER_JIFFIES
 
- TIMER_LFPS_6US
 
- TIMER_LFPS_80US
 
- TIMER_LIMIT_BIT
 
- TIMER_LOAD
 
- TIMER_LOAD_COUNT0
 
- TIMER_LOAD_COUNT1
 
- TIMER_LOAD_HI
 
- TIMER_LOAD_LO
 
- TIMER_LOAD_REG
 
- TIMER_MARGIN
 
- TIMER_MARGIN_DEFAULT
 
- TIMER_MARGIN_MAX
 
- TIMER_MARGIN_MIN
 
- TIMER_MASK
 
- TIMER_MATCH
 
- TIMER_MATCH_VAL
 
- TIMER_MATCH_W_ACTIVE
 
- TIMER_MAX_VAL
 
- TIMER_ME_GLOBAL
 
- TIMER_ME_LOCAL
 
- TIMER_MIGRATING
 
- TIMER_MINUTES
 
- TIMER_MIN_DELTA
 
- TIMER_MIS
 
- TIMER_MODEAB
 
- TIMER_MODE_CONTINOUS
 
- TIMER_MODE_FREE_RUNNING
 
- TIMER_MODE_USER_DEFINED_COUNT
 
- TIMER_MULTIPLIER
 
- TIMER_NAME
 
- TIMER_NUM
 
- TIMER_OFF
 
- TIMER_OFFSET
 
- TIMER_OF_BASE
 
- TIMER_OF_CLOCK
 
- TIMER_OF_DECLARE
 
- TIMER_OF_IRQ
 
- TIMER_OF_TABLES
 
- TIMER_OPTS_DISABLED
 
- TIMER_OPTS_ONESHOT
 
- TIMER_OPTS_PERIODIC
 
- TIMER_OPTS_STATE_MASK
 
- TIMER_OPTS_USE_COMPARE
 
- TIMER_PACKET
 
- TIMER_PCR
 
- TIMER_PCR_INTR_CLR
 
- TIMER_PERIODIC
 
- TIMER_PHYS_BASE
 
- TIMER_PINNED
 
- TIMER_PRIORITY
 
- TIMER_PTIMER
 
- TIMER_PTV
 
- TIMER_PTV_EN
 
- TIMER_PTV_PER
 
- TIMER_RATE
 
- TIMER_RATE_MASK
 
- TIMER_REG_CNT
 
- TIMER_REG_CTL
 
- TIMER_REG_CVAL
 
- TIMER_REG_TMR0CTL
 
- TIMER_REG_TMR0LOAD
 
- TIMER_REG_TMR1CTL
 
- TIMER_REG_TMR1LOAD
 
- TIMER_REG_TMRSTAT
 
- TIMER_REG_TVAL
 
- TIMER_RELOAD
 
- TIMER_RELOAD_VALUE
 
- TIMER_RESOLUTION
 
- TIMER_RETRY
 
- TIMER_RIS
 
- TIMER_SECS
 
- TIMER_SET
 
- TIMER_SLOP
 
- TIMER_SOFTIRQ
 
- TIMER_STATUS
 
- TIMER_STATUS_VAL
 
- TIMER_STOP
 
- TIMER_STS_GPT0_CLR_PEND
 
- TIMER_SYNC_TICKS
 
- TIMER_T0_ID
 
- TIMER_T1_ID
 
- TIMER_T2_ID
 
- TIMER_TIMER1_CTRL
 
- TIMER_TIMER1_STAT
 
- TIMER_TIME_HIGH
 
- TIMER_TIME_LOW
 
- TIMER_TRACE_FLAGMASK
 
- TIMER_VALUE
 
- TIMER_VALUE_HI
 
- TIMER_VALUE_LO
 
- TIMER_VALUE_LO_MASK
 
- TIMER_VALUE_MASK
 
- TIMER_VALUE_SHDW_HI
 
- TIMER_VALUE_SHDW_LO
 
- TIMER_VALUE_SHIFT
 
- TIMER_VIRT_BASE
 
- TIMER_VTIMER
 
- TIMER_WCLK
 
- TIMER_WDT_ID
 
- TIMER_nanosec
 
- TIMERn_CMD
 
- TIMERn_CMD_START
 
- TIMERn_CMD_STOP
 
- TIMERn_CNT
 
- TIMERn_CTRL
 
- TIMERn_CTRL_CLKSEL
 
- TIMERn_CTRL_CLKSEL_PRESCHFPERCLK
 
- TIMERn_CTRL_MODE
 
- TIMERn_CTRL_MODE_DOWN
 
- TIMERn_CTRL_MODE_UP
 
- TIMERn_CTRL_OSMEN
 
- TIMERn_CTRL_PRESC
 
- TIMERn_CTRL_PRESC_1024
 
- TIMERn_IEN
 
- TIMERn_IF
 
- TIMERn_IFC
 
- TIMERn_IFS
 
- TIMERn_IRQ_UF
 
- TIMERn_TOP
 
- TIMESLICING_PRESENT
 
- TIMESTAMPCOLD_RESET
 
- TIMESTAMPRESOLUTION_G
 
- TIMESTAMPRESOLUTION_M
 
- TIMESTAMPRESOLUTION_S
 
- TIMESTAMPS
 
- TIMESTAMP_AFTER
 
- TIMESTAMP_ALL
 
- TIMESTAMP_BEFORE
 
- TIMESTAMP_HEADER_SIZE
 
- TIMESTAMP_HIGH
 
- TIMESTAMP_LOW
 
- TIMESTAMP_REF
 
- TIMESTAMP_SIZE
 
- TIMESTAMP_TIMEZONE_MASK
 
- TIMESTAMP_TYPE_AGREEMENT
 
- TIMESTAMP_TYPE_CUT
 
- TIMESTAMP_TYPE_LOCAL
 
- TIMESTAMP_TYPE_MASK
 
- TIMESTEP
 
- TIMES_SET_FLAGS
 
- TIMEX_EXTEN_FLAG
 
- TIMEX_POTENTIAL_KEY_FLAGS
 
- TIMEX_ROLEX_FPU_MASK
 
- TIME_BAD
 
- TIME_BYP
 
- TIME_CHAR
 
- TIME_CMOS_MAX
 
- TIME_CMOS_MIN
 
- TIME_CNT_EN
 
- TIME_CODE_BACK_MASK
 
- TIME_CODE_B_MASK
 
- TIME_CODE_EVENT_PENDING
 
- TIME_CODE_NEW_MASK
 
- TIME_CODE_N_MASK
 
- TIME_CODE_VALID_MASK
 
- TIME_CODE_V_MASK
 
- TIME_CODE_WAIT_MASK
 
- TIME_CODE_W_MASK
 
- TIME_CONST
 
- TIME_DEL
 
- TIME_DOW_MASK
 
- TIME_DOW_S
 
- TIME_ERROR
 
- TIME_EVENT_CMD
 
- TIME_EVENT_NOTIFICATION
 
- TIME_FF
 
- TIME_FROM_REG
 
- TIME_HORIZON_NS
 
- TIME_HOUR_MASK
 
- TIME_HOUR_S
 
- TIME_INACT
 
- TIME_INS
 
- TIME_IN_RESET_COUNT
 
- TIME_MIN_MASK
 
- TIME_MIN_S
 
- TIME_MSEC_DECODER_STABILIZATION_WAIT
 
- TIME_MSEC_DECODER_WAIT
 
- TIME_MSEC_ENCODER_OK
 
- TIME_MSEC_ENCODER_WAIT
 
- TIME_NAME
 
- TIME_NUM
 
- TIME_OK
 
- TIME_OOP
 
- TIME_PHY_PD_MAX
 
- TIME_PHY_PD_MIN
 
- TIME_PRO_RESET
 
- TIME_PRO_RESET_DONE
 
- TIME_PRO_SYSEX
 
- TIME_QUOTA_CMD
 
- TIME_REG
 
- TIME_REMAINING
 
- TIME_RTC_CHANNEL_MAX
 
- TIME_SCALE
 
- TIME_SEC_MASK
 
- TIME_SETTOD_SEC_MAX
 
- TIME_SLICE_DEFAULT
 
- TIME_SLICE_FOR_FW_RDY_MS
 
- TIME_SLICE_FOR_INPUT_RDY_MS
 
- TIME_STAMP_INT_ENABLE
 
- TIME_STAMP_INT_STAT
 
- TIME_STAMP_INT_STATUS
 
- TIME_STEP_SCALER
 
- TIME_SYMBOLS
 
- TIME_SYMBOLS_HALFGI
 
- TIME_SYNC_EVENT_ID
 
- TIME_THRESH
 
- TIME_TO_POWER_MS
 
- TIME_TO_REG
 
- TIME_TYPE
 
- TIME_T_MAX
 
- TIME_UNIT
 
- TIME_UNIT_CONVERSION
 
- TIME_UNIT_MASK
 
- TIME_UNIT_OFFSET
 
- TIME_UPTIME_SEC_MAX
 
- TIME_WAIT
 
- TIME_WINDOW
 
- TIME_WINDOW1
 
- TIME_WINDOW1_MASK
 
- TIME_WINDOW2
 
- TIME_WINDOW2_MASK
 
- TIME_WINDOW_MAX_MSEC
 
- TIME_WINDOW_MIN_MSEC
 
- TIME_WRAP_AROUND
 
- TIMING
 
- TIMING1_ADC_500MS
 
- TIMINGMASTER_SCB_ADDR
 
- TIMINGOK
 
- TIMING_1
 
- TIMING_2
 
- TIMING_3D_FORMAT_COLUMN_INTERLEAVE
 
- TIMING_3D_FORMAT_DP_HDMI_INBAND_FA
 
- TIMING_3D_FORMAT_FRAME_ALTERNATE
 
- TIMING_3D_FORMAT_HW_FRAME_PACKING
 
- TIMING_3D_FORMAT_INBAND_FA
 
- TIMING_3D_FORMAT_MAX
 
- TIMING_3D_FORMAT_NONE
 
- TIMING_3D_FORMAT_PIXEL_INTERLEAVE
 
- TIMING_3D_FORMAT_ROW_INTERLEAVE
 
- TIMING_3D_FORMAT_SBS_SW_PACKED
 
- TIMING_3D_FORMAT_SIDEBAND_FA
 
- TIMING_3D_FORMAT_SIDE_BY_SIDE
 
- TIMING_3D_FORMAT_SW_FRAME_PACKING
 
- TIMING_3D_FORMAT_TB_SW_PACKED
 
- TIMING_3D_FORMAT_TOP_AND_BOTTOM
 
- TIMING_ADC_DET_1000MS
 
- TIMING_ADC_DET_100MS
 
- TIMING_ADC_DET_150MS
 
- TIMING_ADC_DET_200MS
 
- TIMING_ADC_DET_300MS
 
- TIMING_ADC_DET_400MS
 
- TIMING_ADC_DET_500MS
 
- TIMING_ADC_DET_50MS
 
- TIMING_ADC_DET_600MS
 
- TIMING_ADC_DET_700MS
 
- TIMING_ADC_DET_800MS
 
- TIMING_ADC_DET_900MS
 
- TIMING_AUX_PI_SHIFT
 
- TIMING_AUX_SHIFT
 
- TIMING_BOOT_ACCEL_DIS
 
- TIMING_BYTE_EN
 
- TIMING_CFG_NUM
 
- TIMING_CFG_TCSH
 
- TIMING_CFG_TCSS
 
- TIMING_CFG_TSHSL
 
- TIMING_CLK_SEL_DEF
 
- TIMING_CLK_SEL_MASK
 
- TIMING_CS_EN
 
- TIMING_CTRL
 
- TIMING_DEFAULT_WIDTH
 
- TIMING_INT_AUX_FRAME
 
- TIMING_INT_AUX_FRAME_SEL_VSW
 
- TIMING_INT_CTRL
 
- TIMING_INT_ENABLE
 
- TIMING_INT_MAIN_FRAME
 
- TIMING_INT_MAIN_FRAME_SEL_VSW
 
- TIMING_INT_STATE
 
- TIMING_KEY_PRESS_1000MS
 
- TIMING_KEY_PRESS_100MS
 
- TIMING_KEY_PRESS_200MS
 
- TIMING_KEY_PRESS_300MS
 
- TIMING_KEY_PRESS_400MS
 
- TIMING_KEY_PRESS_500MS
 
- TIMING_KEY_PRESS_600MS
 
- TIMING_KEY_PRESS_700MS
 
- TIMING_KEY_PRESS_800MS
 
- TIMING_KEY_PRESS_900MS
 
- TIMING_LONG_KEY_1000MS
 
- TIMING_LONG_KEY_1100MS
 
- TIMING_LONG_KEY_1200MS
 
- TIMING_LONG_KEY_1300MS
 
- TIMING_LONG_KEY_1400MS
 
- TIMING_LONG_KEY_1500MS
 
- TIMING_LONG_KEY_300MS
 
- TIMING_LONG_KEY_400MS
 
- TIMING_LONG_KEY_500MS
 
- TIMING_LONG_KEY_600MS
 
- TIMING_LONG_KEY_700MS
 
- TIMING_LONG_KEY_800MS
 
- TIMING_LONG_KEY_900MS
 
- TIMING_LSB_FIRST
 
- TIMING_MAIN_PI_SHIFT
 
- TIMING_MAIN_SHIFT
 
- TIMING_MARKER
 
- TIMING_MARKER_RECEIVED
 
- TIMING_MASK
 
- TIMING_MASTER_CONTROL
 
- TIMING_MASTER_MODE
 
- TIMING_MODE
 
- TIMING_MS_MASK
 
- TIMING_NAME
 
- TIMING_OFFSET_0
 
- TIMING_OFFSET_1
 
- TIMING_RECOVERY
 
- TIMING_REG
 
- TIMING_RELAX_NS
 
- TIMING_SOURCE_BASICMODE
 
- TIMING_SOURCE_COUNT
 
- TIMING_SOURCE_CUSTOM
 
- TIMING_SOURCE_CUSTOM_BASE
 
- TIMING_SOURCE_CV
 
- TIMING_SOURCE_DEFAULT
 
- TIMING_SOURCE_EDID_4BYTE
 
- TIMING_SOURCE_EDID_CEA_SVD
 
- TIMING_SOURCE_EDID_CEA_SVD_3D
 
- TIMING_SOURCE_EDID_CEA_SVD_420
 
- TIMING_SOURCE_EDID_CEA_SVD_PREFERRED
 
- TIMING_SOURCE_EDID_CVT_3BYTE
 
- TIMING_SOURCE_EDID_DETAILED
 
- TIMING_SOURCE_EDID_ESTABLISHED
 
- TIMING_SOURCE_EDID_STANDARD
 
- TIMING_SOURCE_EXPLICIT
 
- TIMING_SOURCE_HDMI_VIC
 
- TIMING_SOURCE_IMPLICIT
 
- TIMING_SOURCE_OS_FORCED
 
- TIMING_SOURCE_RANGELIMIT
 
- TIMING_SOURCE_TV
 
- TIMING_SOURCE_UNDEFINED
 
- TIMING_SOURCE_USER_FORCED
 
- TIMING_SOURCE_USER_OVERRIDE
 
- TIMING_SOURCE_VBIOS
 
- TIMING_STROBE_PROG_US
 
- TIMING_STROBE_READ_NS
 
- TIMING_SUPPORT_METHOD_EXPLICIT
 
- TIMING_SUPPORT_METHOD_IMPLICIT
 
- TIMING_SUPPORT_METHOD_NATIVE
 
- TIMING_SUPPORT_METHOD_UNDEFINED
 
- TIMING_SW_WAIT_10MS
 
- TIMING_SW_WAIT_110MS
 
- TIMING_SW_WAIT_130MS
 
- TIMING_SW_WAIT_150MS
 
- TIMING_SW_WAIT_170MS
 
- TIMING_SW_WAIT_190MS
 
- TIMING_SW_WAIT_210MS
 
- TIMING_SW_WAIT_30MS
 
- TIMING_SW_WAIT_50MS
 
- TIMING_SW_WAIT_70MS
 
- TIMING_SW_WAIT_90MS
 
- TIMING_SYNC_WIDTH_MASK
 
- TIMING_TADL
 
- TIMING_TCR_TAR_TRR
 
- TIMING_TCS
 
- TIMING_TC_ENABLE
 
- TIMING_TRACE
 
- TIMING_TRH
 
- TIMING_TRP
 
- TIMING_TRP_RESP
 
- TIMING_TS_NUM
 
- TIMING_TS_WIDTH
 
- TIMING_TWB
 
- TIMING_TWH
 
- TIMING_TWHR
 
- TIMING_TWP
 
- TIMING_WIDTH_FACTOR
 
- TIMING_WIDTH_SHIFT
 
- TIMING_WR_EN
 
- TIMMODE_64BIT_WDOG
 
- TIMOUT_DFLT
 
- TIMO_VAL
 
- TIMR
 
- TIMR_IE
 
- TIMR_IP
 
- TIM_AF_BLK_RST
 
- TIM_AF_CONST
 
- TIM_AF_LF_RST
 
- TIM_AF_RVU_LF_CFG_DEBUG
 
- TIM_ALARM
 
- TIM_ARR
 
- TIM_BDTR
 
- TIM_BDTR_AOE
 
- TIM_BDTR_BK2E
 
- TIM_BDTR_BK2F
 
- TIM_BDTR_BK2F_SHIFT
 
- TIM_BDTR_BK2P
 
- TIM_BDTR_BKE
 
- TIM_BDTR_BKF
 
- TIM_BDTR_BKF_MASK
 
- TIM_BDTR_BKF_SHIFT
 
- TIM_BDTR_BKP
 
- TIM_BDTR_MOE
 
- TIM_CCER
 
- TIM_CCER_CC12E
 
- TIM_CCER_CC12P
 
- TIM_CCER_CC1E
 
- TIM_CCER_CC1NE
 
- TIM_CCER_CC1NP
 
- TIM_CCER_CC1P
 
- TIM_CCER_CC2E
 
- TIM_CCER_CC2P
 
- TIM_CCER_CC34E
 
- TIM_CCER_CC34P
 
- TIM_CCER_CC3E
 
- TIM_CCER_CC3P
 
- TIM_CCER_CC4E
 
- TIM_CCER_CC4P
 
- TIM_CCER_CCXE
 
- TIM_CCER_MASK
 
- TIM_CCMR1
 
- TIM_CCMR2
 
- TIM_CCMR_CC1S
 
- TIM_CCMR_CC1S_TI1
 
- TIM_CCMR_CC1S_TI2
 
- TIM_CCMR_CC2S
 
- TIM_CCMR_CC2S_TI1
 
- TIM_CCMR_CC2S_TI2
 
- TIM_CCMR_CCXS
 
- TIM_CCMR_IC1PSC
 
- TIM_CCMR_IC2PSC
 
- TIM_CCMR_M1
 
- TIM_CCMR_MASK
 
- TIM_CCMR_PE
 
- TIM_CCR1
 
- TIM_CCR2
 
- TIM_CCR3
 
- TIM_CCR4
 
- TIM_CFG_MODE_400_SHIFT
 
- TIM_CFG_OFFSET
 
- TIM_CLOCKS
 
- TIM_CLR_IRQ
 
- TIM_CL_IRQ
 
- TIM_CNT
 
- TIM_CR1
 
- TIM_CR1_ARPE
 
- TIM_CR1_CEN
 
- TIM_CR1_DIR
 
- TIM_CR1_OPM
 
- TIM_CR1_UDIS
 
- TIM_CR2
 
- TIM_CR2_MMS
 
- TIM_CR2_MMS2
 
- TIM_CR2_MMS2_SHIFT
 
- TIM_CR2_MMS_SHIFT
 
- TIM_DCR
 
- TIM_DCR_DBA
 
- TIM_DCR_DBL
 
- TIM_DIER
 
- TIM_DIER_CC1DE
 
- TIM_DIER_CC1IE
 
- TIM_DIER_CC2DE
 
- TIM_DIER_CC3DE
 
- TIM_DIER_CC4DE
 
- TIM_DIER_COMDE
 
- TIM_DIER_TDE
 
- TIM_DIER_UDE
 
- TIM_DIER_UIE
 
- TIM_DIV_SHIFT
 
- TIM_DMAR
 
- TIM_EGR
 
- TIM_EGR_UG
 
- TIM_ELE_ID
 
- TIM_LONG
 
- TIM_MASK
 
- TIM_MIDDLE
 
- TIM_MIN_PVM_SIZE
 
- TIM_NO_DIV_SHIFT
 
- TIM_OFFSET
 
- TIM_PERIODIC_SLAVE_STRETCH_MASK
 
- TIM_PERIODIC_SLAVE_STRETCH_SHIFT
 
- TIM_PRESCALE_SHIFT
 
- TIM_PRE_MASK
 
- TIM_PRIV_LFX_CFG
 
- TIM_PRIV_LFX_INT_CFG
 
- TIM_PSC
 
- TIM_PSC_CLKRATE
 
- TIM_PSC_MAX
 
- TIM_P_SHIFT
 
- TIM_RAND_SLAVE_STRETCH_MASK
 
- TIM_RAND_SLAVE_STRETCH_SHIFT
 
- TIM_RES_TOK
 
- TIM_SMCR
 
- TIM_SMCR_SMS
 
- TIM_SMCR_TS
 
- TIM_SMCR_TS_SHIFT
 
- TIM_SR
 
- TIM_SR_UIF
 
- TIM_START
 
- TIM_STOP
 
- TIM_T_OFF
 
- TIM_T_ON
 
- TIM_T_STEP
 
- TINA2_VOLUME
 
- TINT
 
- TINT0
 
- TINT1
 
- TINT2
 
- TINT3
 
- TINTEN0
 
- TINTEN1
 
- TINTEN2
 
- TINTEN3
 
- TINTM
 
- TINT_SUM
 
- TINY_ATOM_BYTE
 
- TINY_ATOM_DATA_MASK
 
- TINY_ATOM_SIGNED
 
- TINY_SPI_BAUD
 
- TINY_SPI_CONTROL
 
- TINY_SPI_RXDATA
 
- TINY_SPI_STATUS
 
- TINY_SPI_STATUS_TXE
 
- TINY_SPI_STATUS_TXR
 
- TINY_SPI_TXDATA
 
- TIOC0A_A_MARK
 
- TIOC0A_C_MARK
 
- TIOC0A_MARK
 
- TIOC0B_A_MARK
 
- TIOC0B_C_MARK
 
- TIOC0B_MARK
 
- TIOC0C_A_MARK
 
- TIOC0C_C_MARK
 
- TIOC0C_MARK
 
- TIOC0D_A_MARK
 
- TIOC0D_C_MARK
 
- TIOC0D_MARK
 
- TIOC1A_A_MARK
 
- TIOC1A_B_MARK
 
- TIOC1A_C_MARK
 
- TIOC1A_MARK
 
- TIOC1B_A_MARK
 
- TIOC1B_B_MARK
 
- TIOC1B_C_MARK
 
- TIOC1B_MARK
 
- TIOC2A_A_MARK
 
- TIOC2A_B_MARK
 
- TIOC2A_C_MARK
 
- TIOC2A_MARK
 
- TIOC2B_A_MARK
 
- TIOC2B_B_MARK
 
- TIOC2B_C_MARK
 
- TIOC2B_MARK
 
- TIOC3A_A_MARK
 
- TIOC3A_C_MARK
 
- TIOC3A_MARK
 
- TIOC3B_A_MARK
 
- TIOC3B_C_MARK
 
- TIOC3B_MARK
 
- TIOC3C_A_MARK
 
- TIOC3C_C_MARK
 
- TIOC3C_MARK
 
- TIOC3D_A_MARK
 
- TIOC3D_C_MARK
 
- TIOC3D_MARK
 
- TIOC4A_A_MARK
 
- TIOC4A_C_MARK
 
- TIOC4A_MARK
 
- TIOC4B_A_MARK
 
- TIOC4B_C_MARK
 
- TIOC4B_MARK
 
- TIOC4C_A_MARK
 
- TIOC4C_C_MARK
 
- TIOC4C_MARK
 
- TIOC4D_A_MARK
 
- TIOC4D_C_MARK
 
- TIOC4D_MARK
 
- TIOCCBRK
 
- TIOCCONS
 
- TIOCEXBAUD
 
- TIOCEXCL
 
- TIOCGDEV
 
- TIOCGETC
 
- TIOCGETD
 
- TIOCGETP
 
- TIOCGEXCL
 
- TIOCGICOUNT
 
- TIOCGISO7816
 
- TIOCGLCKTRMIOS
 
- TIOCGLTC
 
- TIOCGPGRP
 
- TIOCGPKT
 
- TIOCGPTLCK
 
- TIOCGPTN
 
- TIOCGPTPEER
 
- TIOCGRS485
 
- TIOCGSERIAL
 
- TIOCGSID
 
- TIOCGSOFTCAR
 
- TIOCGWINSZ
 
- TIOCINQ
 
- TIOCLINUX
 
- TIOCL_BLANKEDSCREEN
 
- TIOCL_BLANKSCREEN
 
- TIOCL_GETFGCONSOLE
 
- TIOCL_GETKMSGREDIRECT
 
- TIOCL_GETMOUSEREPORTING
 
- TIOCL_GETSHIFTSTATE
 
- TIOCL_PASTESEL
 
- TIOCL_SCROLLCONSOLE
 
- TIOCL_SELBUTTONMASK
 
- TIOCL_SELCHAR
 
- TIOCL_SELCLEAR
 
- TIOCL_SELLINE
 
- TIOCL_SELLOADLUT
 
- TIOCL_SELMOUSEREPORT
 
- TIOCL_SELPOINTER
 
- TIOCL_SELWORD
 
- TIOCL_SETKMSGREDIRECT
 
- TIOCL_SETSEL
 
- TIOCL_SETVESABLANK
 
- TIOCL_UNBLANKSCREEN
 
- TIOCMBIC
 
- TIOCMBIS
 
- TIOCMBIT
 
- TIOCMGET
 
- TIOCMIWAIT
 
- TIOCMSET
 
- TIOCM_CAR
 
- TIOCM_CD
 
- TIOCM_CTS
 
- TIOCM_DSR
 
- TIOCM_DTR
 
- TIOCM_LE
 
- TIOCM_LOOP
 
- TIOCM_OUT1
 
- TIOCM_OUT2
 
- TIOCM_RI
 
- TIOCM_RNG
 
- TIOCM_RTS
 
- TIOCM_SR
 
- TIOCM_ST
 
- TIOCNOTTY
 
- TIOCNXCL
 
- TIOCOUTQ
 
- TIOCPKT
 
- TIOCPKT_DATA
 
- TIOCPKT_DOSTOP
 
- TIOCPKT_FLUSHREAD
 
- TIOCPKT_FLUSHWRITE
 
- TIOCPKT_IOCTL
 
- TIOCPKT_NOSTOP
 
- TIOCPKT_START
 
- TIOCPKT_STOP
 
- TIOCSBRK
 
- TIOCSCTTY
 
- TIOCSERCONFIG
 
- TIOCSERGETLSR
 
- TIOCSERGETMULTI
 
- TIOCSERGSTRUCT
 
- TIOCSERGWILD
 
- TIOCSERSETMULTI
 
- TIOCSERSWILD
 
- TIOCSER_TEMT
 
- TIOCSETC
 
- TIOCSETD
 
- TIOCSETN
 
- TIOCSETP
 
- TIOCSIG
 
- TIOCSISO7816
 
- TIOCSLCKTRMIOS
 
- TIOCSLTC
 
- TIOCSPGRP
 
- TIOCSPTLCK
 
- TIOCSRS485
 
- TIOCSSERIAL
 
- TIOCSSOFTCAR
 
- TIOCSTART
 
- TIOCSTI
 
- TIOCSTOP
 
- TIOCSWINSZ
 
- TIOCVHANGUP
 
- TIOC_IOCH
 
- TIOC_IOCL
 
- TIOR
 
- TIOR_IC_BOTH
 
- TIOR_IC_FALLING
 
- TIOR_IC_RISING
 
- TIOR_IC_TCNT
 
- TIOR_MASK
 
- TIOR_OC_0_CLEAR
 
- TIOR_OC_0_SET
 
- TIOR_OC_0_TOGGLE
 
- TIOR_OC_1_CLEAR
 
- TIOR_OC_1_SET
 
- TIOR_OC_1_TOGGLE
 
- TIOR_OC_RETAIN
 
- TIP
 
- TIPB_PRIVATE_CNTL_BASE
 
- TIPB_PUBLIC_CNTL_BASE
 
- TIPB_SWITCH_BASE
 
- TIPCF
 
- TIPCF_MASK
 
- TIPCF_SHIFT
 
- TIPC_ACK_RATE
 
- TIPC_ADDR_ID
 
- TIPC_ADDR_MCAST
 
- TIPC_ADDR_NAME
 
- TIPC_ADDR_NAMESEQ
 
- TIPC_BCAST_RCAST
 
- TIPC_BCAST_STATE_NACK
 
- TIPC_BCAST_SYNCH
 
- TIPC_BC_RETR_LIM
 
- TIPC_BLOCK_FLOWCTL
 
- TIPC_BROADCAST_SUPPORT
 
- TIPC_CFG_INVALID_VALUE
 
- TIPC_CFG_NOT_NET_ADMIN
 
- TIPC_CFG_NOT_SUPPORTED
 
- TIPC_CFG_NOT_ZONE_MSTR
 
- TIPC_CFG_NO_REMOTE
 
- TIPC_CFG_SRV
 
- TIPC_CFG_TLV_ERROR
 
- TIPC_CLUSTER_BITS
 
- TIPC_CLUSTER_MASK
 
- TIPC_CLUSTER_OFFSET
 
- TIPC_CLUSTER_SCOPE
 
- TIPC_CLUSTER_SIZE
 
- TIPC_CMD_DISABLE_BEARER
 
- TIPC_CMD_DUMP_LOG
 
- TIPC_CMD_ENABLE_BEARER
 
- TIPC_CMD_GET_BEARER_NAMES
 
- TIPC_CMD_GET_LINKS
 
- TIPC_CMD_GET_MAX_CLUSTERS
 
- TIPC_CMD_GET_MAX_NODES
 
- TIPC_CMD_GET_MAX_PORTS
 
- TIPC_CMD_GET_MAX_PUBL
 
- TIPC_CMD_GET_MAX_SLAVES
 
- TIPC_CMD_GET_MAX_SUBSCR
 
- TIPC_CMD_GET_MAX_ZONES
 
- TIPC_CMD_GET_MEDIA_NAMES
 
- TIPC_CMD_GET_NETID
 
- TIPC_CMD_GET_NODES
 
- TIPC_CMD_GET_REMOTE_MNG
 
- TIPC_CMD_NOOP
 
- TIPC_CMD_NOT_NET_ADMIN
 
- TIPC_CMD_RESET_LINK_STATS
 
- TIPC_CMD_SET_LINK_PRI
 
- TIPC_CMD_SET_LINK_TOL
 
- TIPC_CMD_SET_LINK_WINDOW
 
- TIPC_CMD_SET_LOG_SIZE
 
- TIPC_CMD_SET_MAX_CLUSTERS
 
- TIPC_CMD_SET_MAX_NODES
 
- TIPC_CMD_SET_MAX_PORTS
 
- TIPC_CMD_SET_MAX_PUBL
 
- TIPC_CMD_SET_MAX_SLAVES
 
- TIPC_CMD_SET_MAX_SUBSCR
 
- TIPC_CMD_SET_MAX_ZONES
 
- TIPC_CMD_SET_NETID
 
- TIPC_CMD_SET_NODE_ADDR
 
- TIPC_CMD_SET_REMOTE_MNG
 
- TIPC_CMD_SHOW_LINK_STATS
 
- TIPC_CMD_SHOW_NAME_TABLE
 
- TIPC_CMD_SHOW_PORTS
 
- TIPC_CMD_SHOW_STATS
 
- TIPC_CONNECTING
 
- TIPC_CONN_MSG
 
- TIPC_CONN_SHUTDOWN
 
- TIPC_CONN_TIMEOUT
 
- TIPC_CRITICAL_IMPORTANCE
 
- TIPC_DEF_LINK_PRI
 
- TIPC_DEF_LINK_TOL
 
- TIPC_DEF_LINK_UDP_MTU
 
- TIPC_DEF_LINK_WIN
 
- TIPC_DEF_MON_THRESHOLD
 
- TIPC_DESTNAME
 
- TIPC_DEST_DROPPABLE
 
- TIPC_DIRECT_MSG
 
- TIPC_DISCONNECTING
 
- TIPC_DISC_FAST
 
- TIPC_DISC_INACTIVE
 
- TIPC_DISC_INIT
 
- TIPC_DISC_SLOW
 
- TIPC_DUMP_ALL
 
- TIPC_DUMP_BACKLOGQ
 
- TIPC_DUMP_DEFERDQ
 
- TIPC_DUMP_INPUTQ
 
- TIPC_DUMP_NONE
 
- TIPC_DUMP_SK_BKLGQ
 
- TIPC_DUMP_SK_RCVQ
 
- TIPC_DUMP_SK_SNDQ
 
- TIPC_DUMP_TRANSMQ
 
- TIPC_DUMP_WAKEUP
 
- TIPC_ERRINFO
 
- TIPC_ERR_NO_NAME
 
- TIPC_ERR_NO_NODE
 
- TIPC_ERR_NO_PORT
 
- TIPC_ERR_OVERLOAD
 
- TIPC_ESTABLISHED
 
- TIPC_FILTER_MASK
 
- TIPC_FWD_MSG
 
- TIPC_GAP_ACK_BLOCK
 
- TIPC_GENL_CMD
 
- TIPC_GENL_HDRLEN
 
- TIPC_GENL_NAME
 
- TIPC_GENL_V2_NAME
 
- TIPC_GENL_V2_VERSION
 
- TIPC_GENL_VERSION
 
- TIPC_GROUP_JOIN
 
- TIPC_GROUP_LEAVE
 
- TIPC_GROUP_LOOPBACK
 
- TIPC_GROUP_MEMBER_EVTS
 
- TIPC_GRP_BCAST_MSG
 
- TIPC_GRP_MCAST_MSG
 
- TIPC_GRP_MEMBER_EVT
 
- TIPC_GRP_UCAST_MSG
 
- TIPC_HIGH_IMPORTANCE
 
- TIPC_IMPORTANCE
 
- TIPC_LINK_DOWN_EVT
 
- TIPC_LINK_PROTO_SEQNO
 
- TIPC_LINK_SND_STATE
 
- TIPC_LINK_STATE
 
- TIPC_LINK_UP_EVT
 
- TIPC_LISTEN
 
- TIPC_LOW_IMPORTANCE
 
- TIPC_MAX_BEARER_NAME
 
- TIPC_MAX_IF_NAME
 
- TIPC_MAX_LINK_NAME
 
- TIPC_MAX_LINK_PRI
 
- TIPC_MAX_LINK_TOL
 
- TIPC_MAX_LINK_WIN
 
- TIPC_MAX_MEDIA_NAME
 
- TIPC_MAX_PORT
 
- TIPC_MAX_PUBL
 
- TIPC_MAX_SUBSCR
 
- TIPC_MAX_USER_MSG_SIZE
 
- TIPC_MCAST_BROADCAST
 
- TIPC_MCAST_MSG
 
- TIPC_MCAST_RBCTL
 
- TIPC_MCAST_REPLICAST
 
- TIPC_MEDIA_ADDR_OFFSET
 
- TIPC_MEDIA_INFO_OFFSET
 
- TIPC_MEDIA_INFO_SIZE
 
- TIPC_MEDIA_LINK_PRI
 
- TIPC_MEDIA_TYPE_ETH
 
- TIPC_MEDIA_TYPE_IB
 
- TIPC_MEDIA_TYPE_OFFSET
 
- TIPC_MEDIA_TYPE_UDP
 
- TIPC_MEDIUM_IMPORTANCE
 
- TIPC_METHOD_EXPIRE
 
- TIPC_MIN_BEARER_MTU
 
- TIPC_MIN_LINK_PRI
 
- TIPC_MIN_LINK_TOL
 
- TIPC_MIN_LINK_WIN
 
- TIPC_MIN_PORT
 
- TIPC_MOD_VER
 
- TIPC_NACK_INTV
 
- TIPC_NAMED_MSG
 
- TIPC_NAMETBL_SIZE
 
- TIPC_NLA_BEARER
 
- TIPC_NLA_BEARER_DOMAIN
 
- TIPC_NLA_BEARER_MAX
 
- TIPC_NLA_BEARER_NAME
 
- TIPC_NLA_BEARER_PROP
 
- TIPC_NLA_BEARER_UDP_OPTS
 
- TIPC_NLA_BEARER_UNSPEC
 
- TIPC_NLA_CON_FLAG
 
- TIPC_NLA_CON_INST
 
- TIPC_NLA_CON_MAX
 
- TIPC_NLA_CON_NODE
 
- TIPC_NLA_CON_SOCK
 
- TIPC_NLA_CON_TYPE
 
- TIPC_NLA_CON_UNSPEC
 
- TIPC_NLA_LINK
 
- TIPC_NLA_LINK_ACTIVE
 
- TIPC_NLA_LINK_BROADCAST
 
- TIPC_NLA_LINK_DEST
 
- TIPC_NLA_LINK_MAX
 
- TIPC_NLA_LINK_MTU
 
- TIPC_NLA_LINK_NAME
 
- TIPC_NLA_LINK_PROP
 
- TIPC_NLA_LINK_RX
 
- TIPC_NLA_LINK_STATS
 
- TIPC_NLA_LINK_TX
 
- TIPC_NLA_LINK_UNSPEC
 
- TIPC_NLA_LINK_UP
 
- TIPC_NLA_MAX
 
- TIPC_NLA_MEDIA
 
- TIPC_NLA_MEDIA_MAX
 
- TIPC_NLA_MEDIA_NAME
 
- TIPC_NLA_MEDIA_PROP
 
- TIPC_NLA_MEDIA_UNSPEC
 
- TIPC_NLA_MON
 
- TIPC_NLA_MON_ACTIVATION_THRESHOLD
 
- TIPC_NLA_MON_ACTIVE
 
- TIPC_NLA_MON_BEARER_NAME
 
- TIPC_NLA_MON_LISTGEN
 
- TIPC_NLA_MON_MAX
 
- TIPC_NLA_MON_PEER
 
- TIPC_NLA_MON_PEERCNT
 
- TIPC_NLA_MON_PEER_ADDR
 
- TIPC_NLA_MON_PEER_APPLIED
 
- TIPC_NLA_MON_PEER_DOMGEN
 
- TIPC_NLA_MON_PEER_HEAD
 
- TIPC_NLA_MON_PEER_LOCAL
 
- TIPC_NLA_MON_PEER_MAX
 
- TIPC_NLA_MON_PEER_MEMBERS
 
- TIPC_NLA_MON_PEER_PAD
 
- TIPC_NLA_MON_PEER_UNSPEC
 
- TIPC_NLA_MON_PEER_UP
 
- TIPC_NLA_MON_PEER_UPMAP
 
- TIPC_NLA_MON_REF
 
- TIPC_NLA_MON_UNSPEC
 
- TIPC_NLA_NAME_TABLE
 
- TIPC_NLA_NAME_TABLE_MAX
 
- TIPC_NLA_NAME_TABLE_PUBL
 
- TIPC_NLA_NAME_TABLE_UNSPEC
 
- TIPC_NLA_NET
 
- TIPC_NLA_NET_ADDR
 
- TIPC_NLA_NET_ID
 
- TIPC_NLA_NET_MAX
 
- TIPC_NLA_NET_NODEID
 
- TIPC_NLA_NET_NODEID_W1
 
- TIPC_NLA_NET_UNSPEC
 
- TIPC_NLA_NODE
 
- TIPC_NLA_NODE_ADDR
 
- TIPC_NLA_NODE_MAX
 
- TIPC_NLA_NODE_UNSPEC
 
- TIPC_NLA_NODE_UP
 
- TIPC_NLA_PROP_BROADCAST
 
- TIPC_NLA_PROP_BROADCAST_RATIO
 
- TIPC_NLA_PROP_MAX
 
- TIPC_NLA_PROP_MTU
 
- TIPC_NLA_PROP_PRIO
 
- TIPC_NLA_PROP_TOL
 
- TIPC_NLA_PROP_UNSPEC
 
- TIPC_NLA_PROP_WIN
 
- TIPC_NLA_PUBL
 
- TIPC_NLA_PUBL_KEY
 
- TIPC_NLA_PUBL_LOWER
 
- TIPC_NLA_PUBL_MAX
 
- TIPC_NLA_PUBL_NODE
 
- TIPC_NLA_PUBL_REF
 
- TIPC_NLA_PUBL_SCOPE
 
- TIPC_NLA_PUBL_TYPE
 
- TIPC_NLA_PUBL_UNSPEC
 
- TIPC_NLA_PUBL_UPPER
 
- TIPC_NLA_SOCK
 
- TIPC_NLA_SOCK_ADDR
 
- TIPC_NLA_SOCK_CON
 
- TIPC_NLA_SOCK_COOKIE
 
- TIPC_NLA_SOCK_GROUP
 
- TIPC_NLA_SOCK_GROUP_BC_SEND_NEXT
 
- TIPC_NLA_SOCK_GROUP_CLUSTER_SCOPE
 
- TIPC_NLA_SOCK_GROUP_ID
 
- TIPC_NLA_SOCK_GROUP_INSTANCE
 
- TIPC_NLA_SOCK_GROUP_MAX
 
- TIPC_NLA_SOCK_GROUP_NODE_SCOPE
 
- TIPC_NLA_SOCK_GROUP_OPEN
 
- TIPC_NLA_SOCK_HAS_PUBL
 
- TIPC_NLA_SOCK_INO
 
- TIPC_NLA_SOCK_MAX
 
- TIPC_NLA_SOCK_PAD
 
- TIPC_NLA_SOCK_REF
 
- TIPC_NLA_SOCK_STAT
 
- TIPC_NLA_SOCK_STAT_CONN_CONG
 
- TIPC_NLA_SOCK_STAT_DROP
 
- TIPC_NLA_SOCK_STAT_LINK_CONG
 
- TIPC_NLA_SOCK_STAT_MAX
 
- TIPC_NLA_SOCK_STAT_RCVQ
 
- TIPC_NLA_SOCK_STAT_SENDQ
 
- TIPC_NLA_SOCK_TIPC_STATE
 
- TIPC_NLA_SOCK_TYPE
 
- TIPC_NLA_SOCK_UID
 
- TIPC_NLA_SOCK_UNSPEC
 
- TIPC_NLA_STATS_AVG_QUEUE
 
- TIPC_NLA_STATS_DUPLICATES
 
- TIPC_NLA_STATS_LINK_CONGS
 
- TIPC_NLA_STATS_MAX
 
- TIPC_NLA_STATS_MAX_QUEUE
 
- TIPC_NLA_STATS_MSG_LEN_CNT
 
- TIPC_NLA_STATS_MSG_LEN_P0
 
- TIPC_NLA_STATS_MSG_LEN_P1
 
- TIPC_NLA_STATS_MSG_LEN_P2
 
- TIPC_NLA_STATS_MSG_LEN_P3
 
- TIPC_NLA_STATS_MSG_LEN_P4
 
- TIPC_NLA_STATS_MSG_LEN_P5
 
- TIPC_NLA_STATS_MSG_LEN_P6
 
- TIPC_NLA_STATS_MSG_LEN_TOT
 
- TIPC_NLA_STATS_MSG_PROF_TOT
 
- TIPC_NLA_STATS_RETRANSMITTED
 
- TIPC_NLA_STATS_RX_BUNDLED
 
- TIPC_NLA_STATS_RX_BUNDLES
 
- TIPC_NLA_STATS_RX_DEFERRED
 
- TIPC_NLA_STATS_RX_FRAGMENTED
 
- TIPC_NLA_STATS_RX_FRAGMENTS
 
- TIPC_NLA_STATS_RX_INFO
 
- TIPC_NLA_STATS_RX_NACKS
 
- TIPC_NLA_STATS_RX_PROBES
 
- TIPC_NLA_STATS_RX_STATES
 
- TIPC_NLA_STATS_TX_ACKS
 
- TIPC_NLA_STATS_TX_BUNDLED
 
- TIPC_NLA_STATS_TX_BUNDLES
 
- TIPC_NLA_STATS_TX_FRAGMENTED
 
- TIPC_NLA_STATS_TX_FRAGMENTS
 
- TIPC_NLA_STATS_TX_INFO
 
- TIPC_NLA_STATS_TX_NACKS
 
- TIPC_NLA_STATS_TX_PROBES
 
- TIPC_NLA_STATS_TX_STATES
 
- TIPC_NLA_STATS_UNSPEC
 
- TIPC_NLA_UDP_LOCAL
 
- TIPC_NLA_UDP_MAX
 
- TIPC_NLA_UDP_MULTI_REMOTEIP
 
- TIPC_NLA_UDP_REMOTE
 
- TIPC_NLA_UDP_UNSPEC
 
- TIPC_NLA_UNSPEC
 
- TIPC_NL_BEARER_ADD
 
- TIPC_NL_BEARER_DISABLE
 
- TIPC_NL_BEARER_ENABLE
 
- TIPC_NL_BEARER_GET
 
- TIPC_NL_BEARER_SET
 
- TIPC_NL_CMD_MAX
 
- TIPC_NL_LEGACY
 
- TIPC_NL_LINK_GET
 
- TIPC_NL_LINK_RESET_STATS
 
- TIPC_NL_LINK_SET
 
- TIPC_NL_MEDIA_GET
 
- TIPC_NL_MEDIA_SET
 
- TIPC_NL_MON_GET
 
- TIPC_NL_MON_PEER_GET
 
- TIPC_NL_MON_SET
 
- TIPC_NL_NAME_TABLE_GET
 
- TIPC_NL_NET_GET
 
- TIPC_NL_NET_SET
 
- TIPC_NL_NODE_GET
 
- TIPC_NL_PEER_REMOVE
 
- TIPC_NL_PUBL_GET
 
- TIPC_NL_SOCK_GET
 
- TIPC_NL_UDP_GET_REMOTEIP
 
- TIPC_NL_UNSPEC
 
- TIPC_NODEID_LEN
 
- TIPC_NODE_BITS
 
- TIPC_NODE_CAPABILITIES
 
- TIPC_NODE_ID128
 
- TIPC_NODE_MASK
 
- TIPC_NODE_OFFSET
 
- TIPC_NODE_RECVQ_DEPTH
 
- TIPC_NODE_SCOPE
 
- TIPC_NODE_SIZE
 
- TIPC_NODE_STATE
 
- TIPC_NOTIFY_LINK_DOWN
 
- TIPC_NOTIFY_LINK_UP
 
- TIPC_NOTIFY_NODE_DOWN
 
- TIPC_NOTIFY_NODE_UP
 
- TIPC_NTQ_ALLTYPES
 
- TIPC_OK
 
- TIPC_OPEN
 
- TIPC_PUBLISHED
 
- TIPC_PUBL_SCOPE_NUM
 
- TIPC_REPLICAST_SUPPORT
 
- TIPC_RESERVED_TYPES
 
- TIPC_RETDATA
 
- TIPC_SERVER_NAME_LEN
 
- TIPC_SERVICE_ADDR
 
- TIPC_SERVICE_RANGE
 
- TIPC_SKB_CB
 
- TIPC_SKB_MAX
 
- TIPC_SOCKET_ADDR
 
- TIPC_SOCK_RECVQ_DEPTH
 
- TIPC_SOCK_RECVQ_USED
 
- TIPC_SRC_DROPPABLE
 
- TIPC_SUBSCR_TIMEOUT
 
- TIPC_SUB_CANCEL
 
- TIPC_SUB_CLUSTER_SCOPE
 
- TIPC_SUB_NODE_SCOPE
 
- TIPC_SUB_NO_STATUS
 
- TIPC_SUB_PORTS
 
- TIPC_SUB_SERVICE
 
- TIPC_SYN_BIT
 
- TIPC_SYSTEM_IMPORTANCE
 
- TIPC_TLV_BEARER_CONFIG
 
- TIPC_TLV_BEARER_NAME
 
- TIPC_TLV_ERROR_STRING
 
- TIPC_TLV_LARGE_STRING
 
- TIPC_TLV_LINK_CONFIG
 
- TIPC_TLV_LINK_INFO
 
- TIPC_TLV_LINK_NAME
 
- TIPC_TLV_MEDIA_NAME
 
- TIPC_TLV_NAME_TBL_QUERY
 
- TIPC_TLV_NET_ADDR
 
- TIPC_TLV_NODE_INFO
 
- TIPC_TLV_NONE
 
- TIPC_TLV_PORT_REF
 
- TIPC_TLV_STRING
 
- TIPC_TLV_ULTRA_STRING
 
- TIPC_TLV_UNSIGNED
 
- TIPC_TLV_VOID
 
- TIPC_TOP_SRV
 
- TIPC_TUNNEL_ENHANCED
 
- TIPC_UC_RETR_TIME
 
- TIPC_VERSION
 
- TIPC_WAIT_FOREVER
 
- TIPC_WITHDRAWN
 
- TIPC_ZM_SRV
 
- TIPC_ZONE_BITS
 
- TIPC_ZONE_CLUSTER_MASK
 
- TIPC_ZONE_MASK
 
- TIPC_ZONE_OFFSET
 
- TIPC_ZONE_SCOPE
 
- TIPC_ZONE_SIZE
 
- TIQDIO_NR_INDICATORS
 
- TIQDIO_NR_NONSHARED_IND
 
- TIQDIO_SHARED_IND
 
- TIQN_STATE_ACTIVE
 
- TIQN_STATE_SHUTDOWN
 
- TIR
 
- TIRDID
 
- TIR_CFGA
 
- TIR_CFGB
 
- TIR_CS
 
- TIR_DEN
 
- TIR_EDC
 
- TIR_LCSA
 
- TIR_LCSB
 
- TIR_LCSC
 
- TIR_LCSD
 
- TIR_MSK
 
- TIR_PIEN
 
- TIR_PIERA
 
- TIR_PIERB
 
- TIR_PIPND
 
- TIR_PNDA
 
- TIR_PNDB
 
- TIR_PPNDA
 
- TIR_PPNDB
 
- TIS
 
- TISCI_MSG_RM_UDMAP_FLOW_CFG
 
- TISCI_MSG_RM_UDMAP_FLOW_GET_CFG
 
- TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG
 
- TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_GET_CFG
 
- TISCI_MSG_RM_UDMAP_RX_CH_CFG
 
- TISCI_MSG_RM_UDMAP_RX_CH_GET_CFG
 
- TISCI_MSG_RM_UDMAP_TX_CH_CFG
 
- TISCI_MSG_RM_UDMAP_TX_CH_GET_CFG
 
- TISRC
 
- TIS_ARIS
 
- TIS_AWIS
 
- TIS_BIT
 
- TIS_CRIS
 
- TIS_CWIS
 
- TIS_FRIS
 
- TIS_FTF0
 
- TIS_FTF1
 
- TIS_HID_USR_IDX
 
- TIS_LONG_TIMEOUT
 
- TIS_MEM_LEN
 
- TIS_MRIS
 
- TIS_MWIS
 
- TIS_RESERVED
 
- TIS_SHORT_TIMEOUT
 
- TIS_TFUF
 
- TIS_TFWF
 
- TIS_TIMEOUT_A_MAX
 
- TIS_TIMEOUT_B_MAX
 
- TIS_TIMEOUT_C_MAX
 
- TIS_TIMEOUT_D_MAX
 
- TITAN
 
- TITAN_BASE
 
- TITAN_CAM_CC_CCI_BCR
 
- TITAN_CAM_CC_CPAS_BCR
 
- TITAN_CAM_CC_CSI0PHY_BCR
 
- TITAN_CAM_CC_CSI1PHY_BCR
 
- TITAN_CAM_CC_CSI2PHY_BCR
 
- TITAN_CAM_CC_MCLK0_BCR
 
- TITAN_CAM_CC_MCLK1_BCR
 
- TITAN_CAM_CC_MCLK2_BCR
 
- TITAN_CAM_CC_MCLK3_BCR
 
- TITAN_CAM_CC_TITAN_TOP_BCR
 
- TITAN_CHIP_1050
 
- TITAN_CHIP_1055
 
- TITAN_CHIP_1056
 
- TITAN_CHIP_1060
 
- TITAN_CONF
 
- TITAN_DAC_OFFSET
 
- TITAN_GPIO_DIR_0
 
- TITAN_GPIO_DIR_1
 
- TITAN_GPIO_ENBL_0
 
- TITAN_GPIO_ENBL_1
 
- TITAN_GPIO_INPUT_0
 
- TITAN_GPIO_INPUT_1
 
- TITAN_GPIO_MAX
 
- TITAN_GPIO_OUTPUT_0
 
- TITAN_GPIO_OUTPUT_1
 
- TITAN_HAE_ADDRESS
 
- TITAN_HOSE
 
- TITAN_HOSE_MASK
 
- TITAN_HOSE_SHIFT
 
- TITAN_IACK_SC
 
- TITAN_IO
 
- TITAN_IO_BIAS
 
- TITAN_IO_SPACE
 
- TITAN_IRQ_LAN
 
- TITAN_IRQ_MPCIA
 
- TITAN_IRQ_MPCIB
 
- TITAN_IRQ_USB
 
- TITAN_IRQ_WAN
 
- TITAN_MCHECK_INTERRUPT_MASK
 
- TITAN_MEM
 
- TITAN_MEM_BIAS
 
- TITAN_REGS_ESWITCH_BASE
 
- TITAN_REGS_MAC0
 
- TITAN_REGS_MAC1
 
- TITAN_REGS_MDIO
 
- TITAN_REGS_VLYNQ0
 
- TITAN_REGS_VLYNQ1
 
- TITAN_RESET_BIT_EPHY1
 
- TITAN_TIG_SPACE
 
- TITAN_TOP_GDSC
 
- TITAN__CCHIP_MISC__NXM
 
- TITAN__CCHIP_MISC__NXS__M
 
- TITAN__CCHIP_MISC__NXS__S
 
- TITAN__PCHIP_AGPERROR__ADDR__M
 
- TITAN__PCHIP_AGPERROR__ADDR__S
 
- TITAN__PCHIP_AGPERROR__CMD__M
 
- TITAN__PCHIP_AGPERROR__CMD__S
 
- TITAN__PCHIP_AGPERROR__DAC
 
- TITAN__PCHIP_AGPERROR__ERRMASK
 
- TITAN__PCHIP_AGPERROR__FENCE
 
- TITAN__PCHIP_AGPERROR__HPQFULL
 
- TITAN__PCHIP_AGPERROR__IPTE
 
- TITAN__PCHIP_AGPERROR__LEN__M
 
- TITAN__PCHIP_AGPERROR__LEN__S
 
- TITAN__PCHIP_AGPERROR__LOST
 
- TITAN__PCHIP_AGPERROR__LPQFULL
 
- TITAN__PCHIP_AGPERROR__MWIN
 
- TITAN__PCHIP_AGPERROR__NOWINDOW
 
- TITAN__PCHIP_AGPERROR__PTP
 
- TITAN__PCHIP_AGPERROR__RESCMD
 
- TITAN__PCHIP_PERROR__ADDR__M
 
- TITAN__PCHIP_PERROR__ADDR__S
 
- TITAN__PCHIP_PERROR__APE
 
- TITAN__PCHIP_PERROR__CMD__M
 
- TITAN__PCHIP_PERROR__CMD__S
 
- TITAN__PCHIP_PERROR__DAC
 
- TITAN__PCHIP_PERROR__DCRTO
 
- TITAN__PCHIP_PERROR__DPE
 
- TITAN__PCHIP_PERROR__ERRMASK
 
- TITAN__PCHIP_PERROR__IPTPR
 
- TITAN__PCHIP_PERROR__IPTPW
 
- TITAN__PCHIP_PERROR__LOST
 
- TITAN__PCHIP_PERROR__MWIN
 
- TITAN__PCHIP_PERROR__NDS
 
- TITAN__PCHIP_PERROR__PERR
 
- TITAN__PCHIP_PERROR__SERR
 
- TITAN__PCHIP_PERROR__SGE
 
- TITAN__PCHIP_PERROR__TA
 
- TITAN__PCHIP_SERROR__ADDR__M
 
- TITAN__PCHIP_SERROR__ADDR__S
 
- TITAN__PCHIP_SERROR__CMD__M
 
- TITAN__PCHIP_SERROR__CMD__S
 
- TITAN__PCHIP_SERROR__CRE
 
- TITAN__PCHIP_SERROR__ECCMASK
 
- TITAN__PCHIP_SERROR__ERRMASK
 
- TITAN__PCHIP_SERROR__LOST_CRE
 
- TITAN__PCHIP_SERROR__LOST_UECC
 
- TITAN__PCHIP_SERROR__NXIO
 
- TITAN__PCHIP_SERROR__SRC__M
 
- TITAN__PCHIP_SERROR__SRC__S
 
- TITAN__PCHIP_SERROR__SYN__M
 
- TITAN__PCHIP_SERROR__SYN__S
 
- TITAN__PCHIP_SERROR__UECC
 
- TITAN_cchip
 
- TITAN_dchip
 
- TITAN_pachip0
 
- TITAN_pachip1
 
- TITLE_BAR_HIGHT
 
- TIUMP_GET_FUNC_FROM_CODE
 
- TIUMP_GET_PORT_FROM_CODE
 
- TIUMP_INTERRUPT_CODE_LSR
 
- TIUMP_INTERRUPT_CODE_MSR
 
- TIVO_KIT
 
- TIXX21_SCR_TIEALL
 
- TI_3410_EZ430_ID
 
- TI_3410_PRODUCT_ID
 
- TI_5052_BOOT_PRODUCT_ID
 
- TI_5052_EEPROM_PRODUCT_ID
 
- TI_5052_FIRMWARE_PRODUCT_ID
 
- TI_5152_BOOT_PRODUCT_ID
 
- TI_ABB_FAST_OPP
 
- TI_ABB_NOMINAL_OPP
 
- TI_ABB_SLOW_OPP
 
- TI_ACK_NAK_TO
 
- TI_ACTIVE_CONFIG
 
- TI_ADC141S626
 
- TI_ADC161S626
 
- TI_ADC_DRV_NAME
 
- TI_ADPLL_BYPASS
 
- TI_ADPLL_CLKINP
 
- TI_ADPLL_CLKINPHIF
 
- TI_ADPLL_CLKINPULOW
 
- TI_ADPLL_CLKOUT
 
- TI_ADPLL_CLKOUT2
 
- TI_ADPLL_DCO
 
- TI_ADPLL_DCO_GATE
 
- TI_ADPLL_DIV2
 
- TI_ADPLL_HIF
 
- TI_ADPLL_LJ_CLKDCOLDO
 
- TI_ADPLL_LJ_CLKOUT
 
- TI_ADPLL_LJ_CLKOUTLDO
 
- TI_ADPLL_M2
 
- TI_ADPLL_M2_GATE
 
- TI_ADPLL_M3
 
- TI_ADPLL_N2
 
- TI_ADPLL_NR_CLOCKS
 
- TI_ADPLL_S_CLKOUT
 
- TI_ADPLL_S_CLKOUTHIF
 
- TI_ADPLL_S_CLKOUTX2
 
- TI_ADPLL_S_DCOCLKLDO
 
- TI_ADS7950
 
- TI_ADS7950_CR_CHAN
 
- TI_ADS7950_CR_GPIO
 
- TI_ADS7950_CR_GPIO_DATA
 
- TI_ADS7950_CR_MANUAL
 
- TI_ADS7950_CR_RANGE_5V
 
- TI_ADS7950_CR_WRITE
 
- TI_ADS7950_EXTRACT
 
- TI_ADS7950_GPIO_CMD
 
- TI_ADS7950_GPIO_CMD_SETTINGS
 
- TI_ADS7950_MAN_CMD
 
- TI_ADS7950_MAN_CMD_SETTINGS
 
- TI_ADS7950_MAX_CHAN
 
- TI_ADS7950_NUM_GPIOS
 
- TI_ADS7950_TIMESTAMP_SIZE
 
- TI_ADS7950_VA_MV_ACPI_DEFAULT
 
- TI_ADS7950_V_CHAN
 
- TI_ADS7951
 
- TI_ADS7952
 
- TI_ADS7953
 
- TI_ADS7954
 
- TI_ADS7955
 
- TI_ADS7956
 
- TI_ADS7957
 
- TI_ADS7958
 
- TI_ADS7959
 
- TI_ADS7960
 
- TI_ADS7961
 
- TI_AM335X_XBAR_LINES
 
- TI_BANDGAP_FEATURE_CLK_CTRL
 
- TI_BANDGAP_FEATURE_COUNTER
 
- TI_BANDGAP_FEATURE_COUNTER_DELAY
 
- TI_BANDGAP_FEATURE_ERRATA_814
 
- TI_BANDGAP_FEATURE_FREEZE_BIT
 
- TI_BANDGAP_FEATURE_HISTORY_BUFFER
 
- TI_BANDGAP_FEATURE_MODE_CONFIG
 
- TI_BANDGAP_FEATURE_POWER_SWITCH
 
- TI_BANDGAP_FEATURE_TALERT
 
- TI_BANDGAP_FEATURE_TSHUT
 
- TI_BANDGAP_FEATURE_TSHUT_CONFIG
 
- TI_BANDGAP_FEATURE_UNRELIABLE
 
- TI_BANDGAP_HAS
 
- TI_BIAS
 
- TI_BOARD_REV_COMPACT
 
- TI_BOARD_REV_TI_EP
 
- TI_BOARD_REV_WATCHPORT
 
- TI_BOOT_CONFIG
 
- TI_BREAK
 
- TI_CC3200_LAUNCHPAD_PID
 
- TI_CLKM_CM
 
- TI_CLKM_CM2
 
- TI_CLKM_CTRL
 
- TI_CLKM_CTRL_AUX
 
- TI_CLKM_PLLSS
 
- TI_CLKM_PRM
 
- TI_CLKM_SCRM
 
- TI_CLK_CLKCTRL_COMPAT
 
- TI_CLK_COMPOSITE
 
- TI_CLK_DEVICE_TYPE_GP
 
- TI_CLK_DISABLE_CLKDM_CONTROL
 
- TI_CLK_DIVIDER
 
- TI_CLK_DPLL
 
- TI_CLK_DPLL4_DENY_REPROGRAM
 
- TI_CLK_DPLL_HAS_FREQSEL
 
- TI_CLK_ERRATA_I810
 
- TI_CLK_FIXED
 
- TI_CLK_FIXED_FACTOR
 
- TI_CLK_GATE
 
- TI_CLK_MUX
 
- TI_CLOSE_PORT
 
- TI_CODE_DATA_ERROR
 
- TI_CODE_HARDWARE_ERROR
 
- TI_CODE_MODEM_STATUS
 
- TI_CONFIG2_RS232
 
- TI_CONFIG2_RS422
 
- TI_CONFIG2_RS485
 
- TI_CONFIG2_SWITCHABLE
 
- TI_CONFIG2_WATCHPORT
 
- TI_CPU
 
- TI_CPU_REV_3410
 
- TI_CPU_REV_5052
 
- TI_CSC_H
 
- TI_CURRENT_DS
 
- TI_CWP
 
- TI_DAC_CHANNEL
 
- TI_DEFAULT_CLOSING_WAIT
 
- TI_DOWNLOAD_MAX_PACKET_SIZE
 
- TI_DP83620_PHY_ID
 
- TI_DP83848C_PHY_ID
 
- TI_DRA7_XBAR_INPUTS
 
- TI_DRA7_XBAR_OUTPUTS
 
- TI_DRIVER_AUTHOR
 
- TI_DRIVER_DESC
 
- TI_EMIF_SRAM_SYMBOL_OFFSET
 
- TI_EXTRA_VID_PID_COUNT
 
- TI_FAULT_ADDR
 
- TI_FAULT_CODE
 
- TI_FIRMWARE_BUF_SIZE
 
- TI_FLAGS
 
- TI_FLAG_BYTE_CWP
 
- TI_FLAG_BYTE_FAULT_CODE
 
- TI_FLAG_BYTE_FPDEPTH
 
- TI_FLAG_BYTE_NOERROR
 
- TI_FLAG_BYTE_NOERROR_SHIFT
 
- TI_FLAG_BYTE_WSAVED
 
- TI_FLAG_BYTE_WSTATE
 
- TI_FLAG_CWP_SHIFT
 
- TI_FLAG_FAULT_CODE_SHIFT
 
- TI_FLAG_FPDEPTH_SHIFT
 
- TI_FLAG_WSAVED_SHIFT
 
- TI_FLAG_WSTATE_SHIFT
 
- TI_FPDEPTH
 
- TI_FPREGS
 
- TI_FPSAVED
 
- TI_GET_BOARD_REVISION
 
- TI_GET_CONFIG
 
- TI_GET_CPU_REVISION
 
- TI_GET_DPL
 
- TI_GET_I2C_SIZE
 
- TI_GET_IF
 
- TI_GET_PORT_DEV_INFO
 
- TI_GET_PORT_STATUS
 
- TI_GET_VERSION
 
- TI_GSR
 
- TI_HARDIRQ
 
- TI_I2C_PORT
 
- TI_I2C_SIZE_MASK
 
- TI_IEEE1284_PORT
 
- TI_KPC
 
- TI_KPSR
 
- TI_KREGS
 
- TI_KSP
 
- TI_KUNA_INSN
 
- TI_KUNA_REGS
 
- TI_KWIM
 
- TI_LCR_BREAK
 
- TI_LMU_DATA
 
- TI_LSR_BREAK
 
- TI_LSR_ERROR
 
- TI_LSR_FRAMING_ERROR
 
- TI_LSR_OVERRUN_ERROR
 
- TI_LSR_PARITY_ERROR
 
- TI_LSR_RX_FULL
 
- TI_LSR_TX_EMPTY
 
- TI_MANUF_VERSION_0
 
- TI_MAX_I2C_SIZE
 
- TI_MCR_DTR
 
- TI_MCR_LOOP
 
- TI_MCR_RTS
 
- TI_MODE_BOOT
 
- TI_MODE_CONFIGURING
 
- TI_MODE_DOWNLOAD
 
- TI_MODE_TRANSITIONING
 
- TI_MSGMGR_H
 
- TI_MSR_CD
 
- TI_MSR_CTS
 
- TI_MSR_DELTA_CD
 
- TI_MSR_DELTA_CTS
 
- TI_MSR_DELTA_DSR
 
- TI_MSR_DELTA_MASK
 
- TI_MSR_DELTA_RI
 
- TI_MSR_DSR
 
- TI_MSR_MASK
 
- TI_MSR_RI
 
- TI_NAK
 
- TI_NEW_CHILD
 
- TI_OPEN_PORT
 
- TI_OUI
 
- TI_PHY_DOWN
 
- TI_PIPE_MODE_CONTINUOUS
 
- TI_PIPE_MODE_MASK
 
- TI_PIPE_TIMEOUT_ENABLE
 
- TI_PIPE_TIMEOUT_MASK
 
- TI_PMIC_CLKFREQ_OPREGION_ID
 
- TI_PMIC_CLOCK_OPREGION_ID
 
- TI_PMIC_POWER_OPREGION_ID
 
- TI_PMIC_VR_VAL_OPREGION_ID
 
- TI_PREEMPT
 
- TI_PRE_COUNT
 
- TI_PROTO_ERR
 
- TI_PURGE_INPUT
 
- TI_PURGE_OUTPUT
 
- TI_PURGE_PORT
 
- TI_RAM_PORT
 
- TI_READ_DATA
 
- TI_READ_URB_RUNNING
 
- TI_READ_URB_STOPPED
 
- TI_READ_URB_STOPPING
 
- TI_REG_WINDOW
 
- TI_REQ_TYPE_CLASS
 
- TI_RESET_EXT_DEVICE
 
- TI_RWIN_SPTRS
 
- TI_RW_DATA_ADDR_CODE
 
- TI_RW_DATA_ADDR_DSP
 
- TI_RW_DATA_ADDR_FLASH
 
- TI_RW_DATA_ADDR_GPIO
 
- TI_RW_DATA_ADDR_I2C
 
- TI_RW_DATA_ADDR_IDATA
 
- TI_RW_DATA_ADDR_SFR
 
- TI_RW_DATA_ADDR_XDATA
 
- TI_RW_DATA_BYTE
 
- TI_RW_DATA_DOUBLE_WORD
 
- TI_RW_DATA_UNSPECIFIED
 
- TI_RW_DATA_WORD
 
- TI_SATA_TO
 
- TI_SCI_ADDR_HIGH_MASK
 
- TI_SCI_ADDR_HIGH_SHIFT
 
- TI_SCI_ADDR_LOW_MASK
 
- TI_SCI_DEV_ID_MASK
 
- TI_SCI_DEV_ID_SHIFT
 
- TI_SCI_FLAG_REQ_ACK_ON_PROCESSED
 
- TI_SCI_FLAG_REQ_ACK_ON_RECEIVED
 
- TI_SCI_FLAG_REQ_GENERIC_NORESPONSE
 
- TI_SCI_FLAG_RESP_GENERIC_ACK
 
- TI_SCI_FLAG_RESP_GENERIC_NACK
 
- TI_SCI_IRQ_ID_MASK
 
- TI_SCI_IRQ_ID_SHIFT
 
- TI_SCI_IRQ_SECONDARY_HOST_INVALID
 
- TI_SCI_MSG_ENABLE_WDT
 
- TI_SCI_MSG_FLAG
 
- TI_SCI_MSG_FREE_IRQ
 
- TI_SCI_MSG_GET_CLOCK_FREQ
 
- TI_SCI_MSG_GET_CLOCK_PARENT
 
- TI_SCI_MSG_GET_CLOCK_STATE
 
- TI_SCI_MSG_GET_DEVICE_STATE
 
- TI_SCI_MSG_GET_NUM_CLOCK_PARENTS
 
- TI_SCI_MSG_GET_RESOURCE_RANGE
 
- TI_SCI_MSG_GET_STATUS
 
- TI_SCI_MSG_GOODBYE
 
- TI_SCI_MSG_PROC_HANDOVER
 
- TI_SCI_MSG_PROC_RELEASE
 
- TI_SCI_MSG_PROC_REQUEST
 
- TI_SCI_MSG_QUERY_CLOCK_FREQ
 
- TI_SCI_MSG_RM_PSIL_PAIR
 
- TI_SCI_MSG_RM_PSIL_UNPAIR
 
- TI_SCI_MSG_RM_RING_ALLOCATE
 
- TI_SCI_MSG_RM_RING_CFG
 
- TI_SCI_MSG_RM_RING_FREE
 
- TI_SCI_MSG_RM_RING_GET_CFG
 
- TI_SCI_MSG_RM_RING_RECONFIG
 
- TI_SCI_MSG_RM_RING_RESET
 
- TI_SCI_MSG_RM_UDMAP_FLOW_CFG
 
- TI_SCI_MSG_RM_UDMAP_OPT_FLOW_CFG
 
- TI_SCI_MSG_RM_UDMAP_RX_ALLOC
 
- TI_SCI_MSG_RM_UDMAP_RX_FREE
 
- TI_SCI_MSG_RM_UDMAP_TX_ALLOC
 
- TI_SCI_MSG_RM_UDMAP_TX_FREE
 
- TI_SCI_MSG_SET_CLOCK_FREQ
 
- TI_SCI_MSG_SET_CLOCK_PARENT
 
- TI_SCI_MSG_SET_CLOCK_STATE
 
- TI_SCI_MSG_SET_CONFIG
 
- TI_SCI_MSG_SET_CTRL
 
- TI_SCI_MSG_SET_DEVICE_RESETS
 
- TI_SCI_MSG_SET_DEVICE_STATE
 
- TI_SCI_MSG_SET_IRQ
 
- TI_SCI_MSG_SYS_RESET
 
- TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER
 
- TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID
 
- TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID
 
- TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID
 
- TI_SCI_MSG_VALUE_RM_RING_MODE_VALID
 
- TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID
 
- TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID
 
- TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID
 
- TI_SCI_MSG_VERSION
 
- TI_SCI_MSG_WAKE_REASON
 
- TI_SCI_MSG_WAKE_RESET
 
- TI_SCI_PD_EXCLUSIVE
 
- TI_SCI_PD_SHARED
 
- TI_SCI_RESOURCE_NULL
 
- TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES
 
- TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES
 
- TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES
 
- TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR
 
- TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBVR
 
- TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBRR
 
- TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBVR
 
- TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR
 
- TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR_SB
 
- TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST
 
- TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO
 
- TI_SC_H
 
- TI_SET_CONFIG
 
- TI_SET_DPL
 
- TI_SET_IF
 
- TI_SOFTIRQ
 
- TI_START_PORT
 
- TI_STOP_PORT
 
- TI_SYNCS_RECV
 
- TI_SYSC_DRA7_MCAN
 
- TI_SYSC_OMAP2
 
- TI_SYSC_OMAP2_TIMER
 
- TI_SYSC_OMAP34XX_SR
 
- TI_SYSC_OMAP36XX_SR
 
- TI_SYSC_OMAP3_AES
 
- TI_SYSC_OMAP3_SHAM
 
- TI_SYSC_OMAP4
 
- TI_SYSC_OMAP4_MCASP
 
- TI_SYSC_OMAP4_SIMPLE
 
- TI_SYSC_OMAP4_SR
 
- TI_SYSC_OMAP4_TIMER
 
- TI_SYSC_OMAP4_USB_HOST_FS
 
- TI_SYS_NOERROR
 
- TI_TASK
 
- TI_TEST_PORT
 
- TI_TRANSFER_TIMEOUT
 
- TI_UART1_BASE_ADDR
 
- TI_UART1_PORT
 
- TI_UART2_BASE_ADDR
 
- TI_UART2_PORT
 
- TI_UART_1_5_STOP_BITS
 
- TI_UART_1_STOP_BITS
 
- TI_UART_232
 
- TI_UART_2_STOP_BITS
 
- TI_UART_485_RECEIVER_DISABLED
 
- TI_UART_485_RECEIVER_ENABLED
 
- TI_UART_5_DATA_BITS
 
- TI_UART_6_DATA_BITS
 
- TI_UART_7_DATA_BITS
 
- TI_UART_8_DATA_BITS
 
- TI_UART_DISABLE_DTR
 
- TI_UART_DISABLE_RTS
 
- TI_UART_ENABLE_AUTO_START_DMA
 
- TI_UART_ENABLE_CTS_OUT
 
- TI_UART_ENABLE_DSR_OUT
 
- TI_UART_ENABLE_DTR_IN
 
- TI_UART_ENABLE_MS_INTS
 
- TI_UART_ENABLE_PARITY_CHECKING
 
- TI_UART_ENABLE_RTS_IN
 
- TI_UART_ENABLE_XA_OUT
 
- TI_UART_ENABLE_X_IN
 
- TI_UART_ENABLE_X_OUT
 
- TI_UART_EVEN_PARITY
 
- TI_UART_MARK_PARITY
 
- TI_UART_NO_PARITY
 
- TI_UART_ODD_PARITY
 
- TI_UART_OFFSET_LCR
 
- TI_UART_OFFSET_MCR
 
- TI_UART_SPACE_PARITY
 
- TI_UTRAPS
 
- TI_UWINMASK
 
- TI_VENDOR_ID
 
- TI_VID
 
- TI_VSEND_TIMEOUT_DEFAULT
 
- TI_VSEND_TIMEOUT_FW_DOWNLOAD
 
- TI_WILINK_ST_H
 
- TI_WRITE_DATA
 
- TI_WSAVED
 
- TI_WSTATE
 
- TI_W_SAVED
 
- TI_XBAR_AM335X
 
- TI_XBAR_DRA7
 
- TI_XBAR_EDMA_OFFSET
 
- TI_XBAR_SDMA_OFFSET
 
- TI_XDS100V2_PID
 
- TI_XFSR
 
- TItype
 
- TJBR
 
- TJBR_ADDR
 
- TJMAX_DEFAULT
 
- TJ_3
 
- TK16
 
- TKBS16
 
- TKBS32
 
- TKCC_END
 
- TKCC_START
 
- TKCTL_END
 
- TKCTL_START
 
- TKDCTR16
 
- TKDCTR32
 
- TKEK_KEY_SIZE
 
- TKEYP
 
- TKIMAP_END
 
- TKIMAP_START
 
- TKIP_CRYPT
 
- TKIP_DECRYPT_INVALID_KEYIDX
 
- TKIP_DECRYPT_NO_EXT_IV
 
- TKIP_DECRYPT_OK
 
- TKIP_DECRYPT_REPLAY
 
- TKIP_ENABLED
 
- TKIP_ENCRYPTION
 
- TKIP_H
 
- TKIP_HDR_LEN
 
- TKIP_IV
 
- TKIP_KEYLEN
 
- TKIP_KEY_LEN
 
- TKIP_PN_TO_IV16
 
- TKIP_PN_TO_IV32
 
- TKIP_STATE_NOT_INIT
 
- TKIP_STATE_PHASE1_DONE
 
- TKIP_STATE_PHASE1_HW_UPLOADED
 
- TKIP_SW_DEC_CNT_INC
 
- TKIP_SW_ENC_CNT_INC
 
- TKPB16
 
- TKPB32
 
- TKPCDATAX_END
 
- TKPCDATAX_START
 
- TKS4_MSGBLOCK_SIZE
 
- TKSCADR_END
 
- TKSCADR_START
 
- TKSCCTL_END
 
- TKSCCTL_START
 
- TKSCDATAX_END
 
- TKSCDATAX_START
 
- TKSQ
 
- TKYGNT
 
- TKYGNT_DISABLE
 
- TKYGNT_ENABLE
 
- TK_ADV_FREQ
 
- TK_ADV_TICK
 
- TK_CLEAR_NTP
 
- TK_CLOCK_WAS_SET
 
- TK_MIRROR
 
- TK_OFFS_BOOT
 
- TK_OFFS_MAX
 
- TK_OFFS_REAL
 
- TK_OFFS_TAI
 
- TK_SIZE
 
- TL
 
- TLAN_ACOMMIT
 
- TLAN_ADAPTER_ACTIVITY_LED
 
- TLAN_ADAPTER_BIT_RATE_PHY
 
- TLAN_ADAPTER_NONE
 
- TLAN_ADAPTER_UNMANAGED_PHY
 
- TLAN_ADAPTER_USE_INTERN_10
 
- TLAN_AREG_0
 
- TLAN_AREG_1
 
- TLAN_AREG_2
 
- TLAN_AREG_3
 
- TLAN_BSIZE_REG
 
- TLAN_BUFFERS_PER_LIST
 
- TLAN_CARRIER_LOSS
 
- TLAN_CH_PARM
 
- TLAN_CODE_ERRORS
 
- TLAN_CRC_ERRORS
 
- TLAN_CSTAT_DP_PR
 
- TLAN_CSTAT_EOC
 
- TLAN_CSTAT_FRM_CMP
 
- TLAN_CSTAT_PASS_CRC
 
- TLAN_CSTAT_READY
 
- TLAN_CSTAT_RX_ERROR
 
- TLAN_CSTAT_UNUSED
 
- TLAN_DA_ADR_INC
 
- TLAN_DA_RAM_ADR
 
- TLAN_DBG
 
- TLAN_DEBUG_GNRL
 
- TLAN_DEBUG_LIST
 
- TLAN_DEBUG_PROBE
 
- TLAN_DEBUG_RX
 
- TLAN_DEBUG_TX
 
- TLAN_DEFERRED_TX
 
- TLAN_DEF_DEVICE_ID
 
- TLAN_DEF_MAX_LAT
 
- TLAN_DEF_MIN_LAT
 
- TLAN_DEF_REVISION
 
- TLAN_DEF_SUBCLASS
 
- TLAN_DEF_VENDOR_ID
 
- TLAN_DIO_ADR
 
- TLAN_DIO_DATA
 
- TLAN_DUPLEX_DEFAULT
 
- TLAN_DUPLEX_FULL
 
- TLAN_DUPLEX_HALF
 
- TLAN_EEPROM_ACK
 
- TLAN_EEPROM_SIZE
 
- TLAN_EEPROM_STOP
 
- TLAN_EXCESSCOL_FRMS
 
- TLAN_GOOD_RX_FRMS
 
- TLAN_GOOD_TX_FRMS
 
- TLAN_H
 
- TLAN_HASH_1
 
- TLAN_HASH_2
 
- TLAN_HC_ACK
 
- TLAN_HC_AC_MASK
 
- TLAN_HC_AD_RST
 
- TLAN_HC_CS_MASK
 
- TLAN_HC_EOC
 
- TLAN_HC_GO
 
- TLAN_HC_INT_OFF
 
- TLAN_HC_INT_ON
 
- TLAN_HC_LD_THR
 
- TLAN_HC_LD_TMR
 
- TLAN_HC_NES
 
- TLAN_HC_REQ_INT
 
- TLAN_HC_RT
 
- TLAN_HC_STOP
 
- TLAN_HI_IT_MASK
 
- TLAN_HI_IV_MASK
 
- TLAN_HOST_CMD
 
- TLAN_HOST_INT
 
- TLAN_ID_RX_EOC
 
- TLAN_ID_RX_EOF
 
- TLAN_ID_TX_EOC
 
- TLAN_IGNORE
 
- TLAN_INT_DIS
 
- TLAN_INT_DUMMY
 
- TLAN_INT_NONE
 
- TLAN_INT_NUMBER_OF_INTS
 
- TLAN_INT_RX_EOC
 
- TLAN_INT_RX_EOF
 
- TLAN_INT_STATUS_CHECK
 
- TLAN_INT_STAT_OVERFLOW
 
- TLAN_INT_TX_EOC
 
- TLAN_INT_TX_EOF
 
- TLAN_LAST_BUFFER
 
- TLAN_LATE_COLS
 
- TLAN_LED_ACT
 
- TLAN_LED_LINK
 
- TLAN_LED_REG
 
- TLAN_MAN_TEST
 
- TLAN_MAX_FRAME_SIZE
 
- TLAN_MAX_RX
 
- TLAN_MIN_FRAME_SIZE
 
- TLAN_MULTICOL_FRMS
 
- TLAN_NET_CFG_1CHAN
 
- TLAN_NET_CFG_1FRAG
 
- TLAN_NET_CFG_BIT
 
- TLAN_NET_CFG_MSMASK
 
- TLAN_NET_CFG_MTEST
 
- TLAN_NET_CFG_PEF
 
- TLAN_NET_CFG_PHY_EN
 
- TLAN_NET_CFG_RCLK
 
- TLAN_NET_CFG_RXCRC
 
- TLAN_NET_CFG_TCLK
 
- TLAN_NET_CMD
 
- TLAN_NET_CMD_CAF
 
- TLAN_NET_CMD_CSF
 
- TLAN_NET_CMD_DUPLEX
 
- TLAN_NET_CMD_NOBRX
 
- TLAN_NET_CMD_NRESET
 
- TLAN_NET_CMD_NWRAP
 
- TLAN_NET_CMD_TRFRAM
 
- TLAN_NET_CMD_TXPACE
 
- TLAN_NET_CONFIG
 
- TLAN_NET_MASK
 
- TLAN_NET_MASK_MASK4
 
- TLAN_NET_MASK_MASK5
 
- TLAN_NET_MASK_MASK6
 
- TLAN_NET_MASK_MASK7
 
- TLAN_NET_MASK_RSRVD
 
- TLAN_NET_SIO
 
- TLAN_NET_SIO_ECLOK
 
- TLAN_NET_SIO_EDATA
 
- TLAN_NET_SIO_ETXEN
 
- TLAN_NET_SIO_MCLK
 
- TLAN_NET_SIO_MDATA
 
- TLAN_NET_SIO_MINTEN
 
- TLAN_NET_SIO_MTXEN
 
- TLAN_NET_SIO_NMRST
 
- TLAN_NET_STS
 
- TLAN_NET_STS_HBEAT
 
- TLAN_NET_STS_MIRQ
 
- TLAN_NET_STS_RSRVD
 
- TLAN_NET_STS_RXSTOP
 
- TLAN_NET_STS_TXSTOP
 
- TLAN_NUM_RX_LISTS
 
- TLAN_NUM_TX_LISTS
 
- TLAN_PHY_AN_EN_STAT
 
- TLAN_PHY_CIM_STAT
 
- TLAN_PHY_DUPLEX_FULL
 
- TLAN_PHY_MAX_ADDR
 
- TLAN_PHY_NONE
 
- TLAN_PHY_SPEED_100
 
- TLAN_RECORD
 
- TLAN_RX_OVERRUNS
 
- TLAN_SINGLECOL_FRMS
 
- TLAN_SPEED_10
 
- TLAN_SPEED_100
 
- TLAN_SPEED_DEFAULT
 
- TLAN_TC_AUISEL
 
- TLAN_TC_IGLINK
 
- TLAN_TC_INTEN
 
- TLAN_TC_MTEST
 
- TLAN_TC_NFEW
 
- TLAN_TC_RESERVED
 
- TLAN_TC_SQEEN
 
- TLAN_TC_SWAPOL
 
- TLAN_TC_TINT
 
- TLAN_TIMER_ACTIVITY
 
- TLAN_TIMER_ACT_DELAY
 
- TLAN_TIMER_FINISH_RESET
 
- TLAN_TIMER_PHY_FINISH_AN
 
- TLAN_TIMER_PHY_PDOWN
 
- TLAN_TIMER_PHY_PUP
 
- TLAN_TIMER_PHY_RESET
 
- TLAN_TIMER_PHY_START_LINK
 
- TLAN_TLPHY_CTL
 
- TLAN_TLPHY_ID
 
- TLAN_TLPHY_PAR
 
- TLAN_TLPHY_STS
 
- TLAN_TS_MINT
 
- TLAN_TS_PHOK
 
- TLAN_TS_POLOK
 
- TLAN_TS_RESERVED
 
- TLAN_TS_TPENERGY
 
- TLAN_TX_UNDERUNS
 
- TLAYTECH_PRODUCT_TEU800
 
- TLAYTECH_VENDOR_ID
 
- TLB0_CLASS_00
 
- TLB0_CLASS_01
 
- TLB0_CLASS_10
 
- TLB0_CLASS_11
 
- TLB0_CLASS_MASK
 
- TLB0_EPN_MASK
 
- TLB0_SIZE_16M
 
- TLB0_SIZE_1G
 
- TLB0_SIZE_1M
 
- TLB0_SIZE_4K
 
- TLB0_SIZE_64K
 
- TLB0_SIZE_MASK
 
- TLB0_THDID_0
 
- TLB0_THDID_1
 
- TLB0_THDID_2
 
- TLB0_THDID_3
 
- TLB0_THDID_ALL
 
- TLB0_THDID_MASK
 
- TLB0_V
 
- TLB0_X
 
- TLB1_C
 
- TLB1_E
 
- TLB1_G
 
- TLB1_I
 
- TLB1_M
 
- TLB1_R
 
- TLB1_RESVATTR
 
- TLB1_RPN_MASK
 
- TLB1_SR
 
- TLB1_SW
 
- TLB1_SX
 
- TLB1_U0
 
- TLB1_U1
 
- TLB1_U2
 
- TLB1_U3
 
- TLB1_UR
 
- TLB1_UW
 
- TLB1_UX
 
- TLB1_VF
 
- TLB1_W
 
- TLBBFBS
 
- TLBBFBS_MASK
 
- TLBBFBS_SHIFT
 
- TLBDeleteEntry
 
- TLBFLPTER
 
- TLBF_H
 
- TLBF_T
 
- TLBGetIndex
 
- TLBHANDMISS
 
- TLBIALL
 
- TLBIALLIS
 
- TLBIALLNSNHIS
 
- TLBIASID
 
- TLBIASIDCFG
 
- TLBIASIDCFG_MASK
 
- TLBIASIDCFG_SHIFT
 
- TLBIASID_ASID
 
- TLBIASID_ASID_MASK
 
- TLBIASID_ASID_SHIFT
 
- TLBIEL_INVAL_PAGE
 
- TLBIEL_INVAL_SEL_MASK
 
- TLBIEL_INVAL_SET
 
- TLBIEL_INVAL_SET_LPID
 
- TLBIEL_INVAL_SET_MASK
 
- TLBIEL_INVAL_SET_SHIFT
 
- TLBILX_T_ALL
 
- TLBILX_T_CLASS0
 
- TLBILX_T_CLASS1
 
- TLBILX_T_CLASS2
 
- TLBILX_T_CLASS3
 
- TLBILX_T_FULLMATCH
 
- TLBILX_T_TID
 
- TLBIVA
 
- TLBIVAA
 
- TLBIVAACFG
 
- TLBIVAACFG_MASK
 
- TLBIVAACFG_SHIFT
 
- TLBIVAA_VA
 
- TLBIVAA_VA_MASK
 
- TLBIVAA_VA_SHIFT
 
- TLBIVA_ASID
 
- TLBIVA_ASID_MASK
 
- TLBIVA_ASID_SHIFT
 
- TLBIVA_VA
 
- TLBIVA_VA_MASK
 
- TLBIVA_VA_SHIFT
 
- TLBIVMID
 
- TLBIVMIDCFG
 
- TLBIVMIDCFG_MASK
 
- TLBIVMIDCFG_SHIFT
 
- TLBIVMID_VMID
 
- TLBIVMID_VMID_MASK
 
- TLBIVMID_VMID_SHIFT
 
- TLBIVUTLB
 
- TLBInsertEntry
 
- TLBLCKR
 
- TLBLCKR_TLBIALLCFG
 
- TLBLCKR_TLBIALLCFG_MASK
 
- TLBLCKR_TLBIALLCFG_SHIFT
 
- TLBLKCRWE
 
- TLBLKCRWE_MASK
 
- TLBLKCRWE_SHIFT
 
- TLBLO_HWBITSHIFT
 
- TLBMCFG
 
- TLBMCFG_MASK
 
- TLBMCFG_SHIFT
 
- TLBMF
 
- TLBMF_MASK
 
- TLBMF_SHIFT
 
- TLBMISC_PID
 
- TLBMISC_PID_MASK
 
- TLBMISC_PID_SHIFT
 
- TLBMISC_RD
 
- TLBMISC_WAY
 
- TLBMISC_WAY_MASK
 
- TLBMISC_WAY_SHIFT
 
- TLBMISC_WE
 
- TLBMISS
 
- TLBMISS_FREEUP_REGS
 
- TLBMISS_HANDLER_RESTORE
 
- TLBMISS_HANDLER_SETUP
 
- TLBMISS_HANDLER_SETUP_PGD
 
- TLBMISS_HANDLER_SETUP_PGD_KERNEL
 
- TLBMISS_RESTORE_REGS
 
- TLBProbe
 
- TLBRSW
 
- TLBRSW_INDEX
 
- TLBRSW_INDEX_MASK
 
- TLBRSW_INDEX_SHIFT
 
- TLBRead
 
- TLBSIZE
 
- TLBSIZE_MASK
 
- TLBSIZE_SHIFT
 
- TLBSLPTER
 
- TLBSYNC
 
- TLBTEMP_BASE
 
- TLBTEMP_BASE_1
 
- TLBTEMP_BASE_2
 
- TLBTEMP_SIZE
 
- TLBTR0
 
- TLBTR1
 
- TLBTR1_PA
 
- TLBTR1_PA_MASK
 
- TLBTR1_PA_SHIFT
 
- TLBTR1_VMID
 
- TLBTR1_VMID_MASK
 
- TLBTR1_VMID_SHIFT
 
- TLBTR2
 
- TLBTR2_ASID
 
- TLBTR2_ASID_MASK
 
- TLBTR2_ASID_SHIFT
 
- TLBTR2_NSTID
 
- TLBTR2_NSTID_MASK
 
- TLBTR2_NSTID_SHIFT
 
- TLBTR2_NV
 
- TLBTR2_NV_MASK
 
- TLBTR2_NV_SHIFT
 
- TLBTR2_V
 
- TLBTR2_VA
 
- TLBTR2_VA_MASK
 
- TLBTR2_VA_SHIFT
 
- TLBTR2_V_MASK
 
- TLBTR2_V_SHIFT
 
- TLBWrite
 
- TLBWriteNI
 
- TLB_ASID
 
- TLB_ATTR_MASK
 
- TLB_BARRIER
 
- TLB_BATCH_NR
 
- TLB_CONTROL_DO_NOTHING
 
- TLB_CONTROL_FLUSH_ALL_ASID
 
- TLB_CONTROL_FLUSH_ASID
 
- TLB_CONTROL_FLUSH_ASID_LOCAL
 
- TLB_DATA
 
- TLB_DATA0_2M_4M
 
- TLB_DATA0_4K
 
- TLB_DATA0_4M
 
- TLB_DATA_1G
 
- TLB_DATA_2M_4M
 
- TLB_DATA_4K
 
- TLB_DATA_4K_4M
 
- TLB_DATA_4M
 
- TLB_DATA_kernel_text_attr
 
- TLB_DATA_mskA
 
- TLB_DATA_mskC
 
- TLB_DATA_mskD
 
- TLB_DATA_mskG
 
- TLB_DATA_mskM
 
- TLB_DATA_mskPPN
 
- TLB_DATA_mskV
 
- TLB_DATA_mskX
 
- TLB_DATA_offA
 
- TLB_DATA_offC
 
- TLB_DATA_offD
 
- TLB_DATA_offG
 
- TLB_DATA_offM
 
- TLB_DATA_offPPN
 
- TLB_DATA_offV
 
- TLB_DATA_offX
 
- TLB_DCLEAN
 
- TLB_DUP_ERR
 
- TLB_ENTRY_SIZE
 
- TLB_ENTRY_SIZE_MASK
 
- TLB_EPN_MASK
 
- TLB_ERROR
 
- TLB_EX
 
- TLB_FLUSH_ALL
 
- TLB_FLUSH_ON_TASK_SWITCH
 
- TLB_FLUSH_REASON
 
- TLB_FLUSH_VMA
 
- TLB_G
 
- TLB_HASH_TABLE_SIZE
 
- TLB_HI
 
- TLB_HI_ASID_HIT
 
- TLB_HI_VPN2_HIT
 
- TLB_I
 
- TLB_INDEX_MASK
 
- TLB_INSANE
 
- TLB_INST_1G
 
- TLB_INST_2M_4M
 
- TLB_INST_4K
 
- TLB_INST_4M
 
- TLB_INST_ALL
 
- TLB_INTR_A
 
- TLB_INTR_B
 
- TLB_INVALIDATE
 
- TLB_INVAL_SCOPE_GLOBAL
 
- TLB_INVAL_SCOPE_LPID
 
- TLB_IS_DIRTY
 
- TLB_IS_GLOBAL
 
- TLB_IS_VALID
 
- TLB_L2CLEAN_FR
 
- TLB_LKUP_ERR
 
- TLB_LO
 
- TLB_LOCAL_MM_SHOOTDOWN
 
- TLB_LOCAL_SHOOTDOWN
 
- TLB_LOOP_TIMEOUT
 
- TLB_LO_IDX
 
- TLB_M
 
- TLB_MISC_mskACC_PSZ
 
- TLB_MISC_mskCID
 
- TLB_MISC_offACC_PSZ
 
- TLB_MISC_offCID
 
- TLB_MISS_EPILOG_ERROR
 
- TLB_MISS_EPILOG_ERROR_SPECIAL
 
- TLB_MISS_EPILOG_SUCCESS
 
- TLB_MISS_PROLOG
 
- TLB_MISS_PROLOG_STATS
 
- TLB_MISS_PROLOG_STATS_BOLTED
 
- TLB_MISS_RESTORE
 
- TLB_MISS_RESTORE_STATS
 
- TLB_MISS_RESTORE_STATS_BOLTED
 
- TLB_MISS_STATS_D
 
- TLB_MISS_STATS_I
 
- TLB_MISS_STATS_SAVE_INFO
 
- TLB_MISS_STATS_SAVE_INFO_BOLTED
 
- TLB_MISS_STATS_X
 
- TLB_MISS_STATS_Y
 
- TLB_NR_DYN_ASIDS
 
- TLB_NULL_INDEX
 
- TLB_OFFSET
 
- TLB_PAGESZ
 
- TLB_PAGESZ_MASK
 
- TLB_PERM_MASK
 
- TLB_PTEH
 
- TLB_PTEL
 
- TLB_REMOTE_SEND_IPI
 
- TLB_REMOTE_SHOOTDOWN
 
- TLB_RPN_MASK
 
- TLB_SAVED_R0
 
- TLB_SAVED_R1
 
- TLB_SAVED_R25
 
- TLB_SAVED_TR1
 
- TLB_SAVED_TR2
 
- TLB_SAVED_TR3
 
- TLB_SAVED_TR4
 
- TLB_SFSR
 
- TLB_SPIN_COUNT
 
- TLB_STEP
 
- TLB_SUSPICIOUS
 
- TLB_TAG
 
- TLB_TAG_ACCESS
 
- TLB_TAG_ACCESS_EXT
 
- TLB_TYPE_ITLB
 
- TLB_TYPE_UTLB
 
- TLB_V4_D_FULL
 
- TLB_V4_D_PAGE
 
- TLB_V4_I_FULL
 
- TLB_V4_I_PAGE
 
- TLB_V4_U_FULL
 
- TLB_V4_U_PAGE
 
- TLB_V6_BP
 
- TLB_V6_D_ASID
 
- TLB_V6_D_FULL
 
- TLB_V6_D_PAGE
 
- TLB_V6_I_ASID
 
- TLB_V6_I_FULL
 
- TLB_V6_I_PAGE
 
- TLB_V6_U_ASID
 
- TLB_V6_U_FULL
 
- TLB_V6_U_PAGE
 
- TLB_V7_UIS_ASID
 
- TLB_V7_UIS_BP
 
- TLB_V7_UIS_FULL
 
- TLB_V7_UIS_PAGE
 
- TLB_VALID
 
- TLB_VPN2
 
- TLB_VPN_mskVPN
 
- TLB_VPN_offVPN
 
- TLB_W
 
- TLB_WB
 
- TLB_WR
 
- TLB_ZSEL
 
- TLB_ZSEL_MASK
 
- TLBnCFG_ASSOC
 
- TLBnCFG_ASSOC_SHIFT
 
- TLBnCFG_GTWE
 
- TLBnCFG_HES
 
- TLBnCFG_IND
 
- TLBnCFG_IPROT
 
- TLBnCFG_MAXSIZE
 
- TLBnCFG_MAXSIZE_SHIFT
 
- TLBnCFG_MINSIZE
 
- TLBnCFG_MINSIZE_SHIFT
 
- TLBnCFG_N_ENTRY
 
- TLBnCFG_PT
 
- TLBnPS_128G
 
- TLBnPS_128K
 
- TLBnPS_128M
 
- TLBnPS_16G
 
- TLBnPS_16K
 
- TLBnPS_16M
 
- TLBnPS_1G
 
- TLBnPS_1M
 
- TLBnPS_256G
 
- TLBnPS_256K
 
- TLBnPS_256M
 
- TLBnPS_2G
 
- TLBnPS_2M
 
- TLBnPS_32G
 
- TLBnPS_32K
 
- TLBnPS_32M
 
- TLBnPS_4G
 
- TLBnPS_4K
 
- TLBnPS_4M
 
- TLBnPS_512K
 
- TLBnPS_512M
 
- TLBnPS_64G
 
- TLBnPS_64K
 
- TLBnPS_64M
 
- TLBnPS_8G
 
- TLBnPS_8K
 
- TLBnPS_8M
 
- TLC3541
 
- TLC4541
 
- TLC4541_V_CHAN
 
- TLC591XX_MAX_BRIGHTNESS
 
- TLC591XX_MAX_LEDS
 
- TLC591XX_REG_GRPFREQ
 
- TLC591XX_REG_GRPPWM
 
- TLC591XX_REG_MODE1
 
- TLC591XX_REG_MODE2
 
- TLC591XX_REG_PWM
 
- TLCC_MASK
 
- TLCC_SHIFT_BIT
 
- TLCL
 
- TLCLK_BASE
 
- TLCLK_MAJOR
 
- TLCLK_REG0
 
- TLCLK_REG1
 
- TLCLK_REG2
 
- TLCLK_REG3
 
- TLCLK_REG4
 
- TLCLK_REG5
 
- TLCLK_REG6
 
- TLCLK_REG7
 
- TLCL_ADDR
 
- TLCTLR
 
- TLC_MNG_CONFIG_CMD
 
- TLC_MNG_UPDATE_NOTIF
 
- TLD_INCLK_TH
 
- TLD_OUTCLK_TH
 
- TLFRCR
 
- TLF_LAZY_MMU
 
- TLF_NAPPING
 
- TLF_RUNLATCH
 
- TLF_SLEEPING
 
- TLHDR
 
- TLINK_ERROR_EXPIRE
 
- TLINK_IDLE_EXPIRE
 
- TLK10X_PHY_ID
 
- TLMM_CLK
 
- TLMM_H_CLK
 
- TLMM_H_RESET
 
- TLMM_RESET
 
- TLOCKLONG
 
- TLOCKSHORT
 
- TLPRIEN
 
- TLPRISTAT
 
- TLPTIEN
 
- TLPTISTAT
 
- TLP_BYTE_COUNT
 
- TLP_CFG_DW0
 
- TLP_CFG_DW1
 
- TLP_CFG_DW2
 
- TLP_COMP_STATUS
 
- TLP_FMTTYPE_CFGRD0
 
- TLP_FMTTYPE_CFGRD1
 
- TLP_FMTTYPE_CFGWR0
 
- TLP_FMTTYPE_CFGWR1
 
- TLP_HDR_SIZE
 
- TLP_LOOP
 
- TLP_PAYLOAD_SIZE
 
- TLP_PROGRAM_EN
 
- TLP_RCV_INT_EN
 
- TLP_READ_TAG
 
- TLP_REQ_ID
 
- TLP_RX_INT
 
- TLP_TRSMT_INT_EN
 
- TLP_TX_INT
 
- TLP_WRITE_TAG
 
- TLR0
 
- TLR1
 
- TLSRX_HDR_PKT_CCDX_ERROR_F
 
- TLSRX_HDR_PKT_CCDX_ERROR_G
 
- TLSRX_HDR_PKT_CCDX_ERROR_M
 
- TLSRX_HDR_PKT_CCDX_ERROR_S
 
- TLSRX_HDR_PKT_CCDX_ERROR_V
 
- TLSRX_HDR_PKT_ERROR_M
 
- TLSRX_HDR_PKT_INT_ERROR_F
 
- TLSRX_HDR_PKT_INT_ERROR_G
 
- TLSRX_HDR_PKT_INT_ERROR_M
 
- TLSRX_HDR_PKT_INT_ERROR_S
 
- TLSRX_HDR_PKT_INT_ERROR_V
 
- TLSRX_HDR_PKT_MAC_ERROR_F
 
- TLSRX_HDR_PKT_MAC_ERROR_G
 
- TLSRX_HDR_PKT_MAC_ERROR_M
 
- TLSRX_HDR_PKT_MAC_ERROR_S
 
- TLSRX_HDR_PKT_MAC_ERROR_V
 
- TLSRX_HDR_PKT_PAD_ERROR_F
 
- TLSRX_HDR_PKT_PAD_ERROR_G
 
- TLSRX_HDR_PKT_PAD_ERROR_M
 
- TLSRX_HDR_PKT_PAD_ERROR_S
 
- TLSRX_HDR_PKT_PAD_ERROR_V
 
- TLSRX_HDR_PKT_SPP_ERROR_F
 
- TLSRX_HDR_PKT_SPP_ERROR_G
 
- TLSRX_HDR_PKT_SPP_ERROR_M
 
- TLSRX_HDR_PKT_SPP_ERROR_S
 
- TLSRX_HDR_PKT_SPP_ERROR_V
 
- TLSV4
 
- TLSV6
 
- TLS_1_2_VERSION
 
- TLS_1_2_VERSION_MAJOR
 
- TLS_1_2_VERSION_MINOR
 
- TLS_1_3_VERSION
 
- TLS_1_3_VERSION_MAJOR
 
- TLS_1_3_VERSION_MINOR
 
- TLS_AAD_SPACE_SIZE
 
- TLS_AES_CCM_IV_B0_BYTE
 
- TLS_BASE
 
- TLS_CIPHER_AES_CCM_128
 
- TLS_CIPHER_AES_CCM_128_IV_SIZE
 
- TLS_CIPHER_AES_CCM_128_KEY_SIZE
 
- TLS_CIPHER_AES_CCM_128_REC_SEQ_SIZE
 
- TLS_CIPHER_AES_CCM_128_SALT_SIZE
 
- TLS_CIPHER_AES_CCM_128_TAG_SIZE
 
- TLS_CIPHER_AES_GCM_128
 
- TLS_CIPHER_AES_GCM_128_IV_SIZE
 
- TLS_CIPHER_AES_GCM_128_KEY_SIZE
 
- TLS_CIPHER_AES_GCM_128_REC_SEQ_SIZE
 
- TLS_CIPHER_AES_GCM_128_SALT_SIZE
 
- TLS_CIPHER_AES_GCM_128_TAG_SIZE
 
- TLS_CIPHER_AES_GCM_256
 
- TLS_CIPHER_AES_GCM_256_IV_SIZE
 
- TLS_CIPHER_AES_GCM_256_KEY_SIZE
 
- TLS_CIPHER_AES_GCM_256_REC_SEQ_SIZE
 
- TLS_CIPHER_AES_GCM_256_SALT_SIZE
 
- TLS_CIPHER_AES_GCM_256_TAG_SIZE
 
- TLS_CONF_BASE
 
- TLS_CONF_HW
 
- TLS_CONF_HW_RECORD
 
- TLS_CONF_SW
 
- TLS_CRYPTO_INFO_READY
 
- TLS_DEVICE_NAME_MAX
 
- TLS_DEVICE_RESYNC_NH_MAX_IVAL
 
- TLS_DEVICE_RESYNC_NH_START_IVAL
 
- TLS_DRIVER_STATE_SIZE_RX
 
- TLS_DRIVER_STATE_SIZE_TX
 
- TLS_GENERAL_DYN
 
- TLS_GET_RECORD_TYPE
 
- TLS_HDR_TYPE_ALERT
 
- TLS_HDR_TYPE_CCS
 
- TLS_HDR_TYPE_HANDSHAKE
 
- TLS_HDR_TYPE_HEARTBEAT
 
- TLS_HDR_TYPE_RECORD
 
- TLS_HEADER_LENGTH
 
- TLS_HEADER_SIZE
 
- TLS_HW
 
- TLS_HW_RECORD
 
- TLS_IMM_EXEC
 
- TLS_INFO_CIPHER
 
- TLS_INFO_MAX
 
- TLS_INFO_RXCONF
 
- TLS_INFO_TXCONF
 
- TLS_INFO_UNSPEC
 
- TLS_INFO_VERSION
 
- TLS_KEYCTX_RXAUTH_MODE_M
 
- TLS_KEYCTX_RXAUTH_MODE_S
 
- TLS_KEYCTX_RXAUTH_MODE_V
 
- TLS_KEYCTX_RXCIAU_CTRL_S
 
- TLS_KEYCTX_RXCIAU_CTRL_V
 
- TLS_KEYCTX_RXCIPH_MODE_M
 
- TLS_KEYCTX_RXCIPH_MODE_S
 
- TLS_KEYCTX_RXCIPH_MODE_V
 
- TLS_KEYCTX_RXCK_SIZE_M
 
- TLS_KEYCTX_RXCK_SIZE_S
 
- TLS_KEYCTX_RXCK_SIZE_V
 
- TLS_KEYCTX_RXFLIT_CNT_S
 
- TLS_KEYCTX_RXFLIT_CNT_V
 
- TLS_KEYCTX_RXMK_SIZE_M
 
- TLS_KEYCTX_RXMK_SIZE_S
 
- TLS_KEYCTX_RXMK_SIZE_V
 
- TLS_KEYCTX_RXPROT_VER_M
 
- TLS_KEYCTX_RXPROT_VER_S
 
- TLS_KEYCTX_RXPROT_VER_V
 
- TLS_KEYCTX_RX_SEQCTR_M
 
- TLS_KEYCTX_RX_SEQCTR_S
 
- TLS_KEYCTX_RX_SEQCTR_V
 
- TLS_KEYCTX_RX_VALID_S
 
- TLS_KEYCTX_RX_VALID_V
 
- TLS_KEY_CONTEXT_SZ
 
- TLS_LOCAL_EXEC
 
- TLS_MAX_PAYLOAD_SIZE
 
- TLS_MAX_REC_SEQ_SIZE
 
- TLS_MFS
 
- TLS_NONCE_OFFSET
 
- TLS_NOT_SET
 
- TLS_NUM_CONFIG
 
- TLS_NUM_PROTS
 
- TLS_OFFLOAD_CONTEXT_SIZE_RX
 
- TLS_OFFLOAD_CONTEXT_SIZE_TX
 
- TLS_OFFLOAD_CTX_DIR_RX
 
- TLS_OFFLOAD_CTX_DIR_TX
 
- TLS_OFFLOAD_SYNC_TYPE_CORE_NEXT_HINT
 
- TLS_OFFLOAD_SYNC_TYPE_DRIVER_REQ
 
- TLS_PAYLOAD_MAX_LEN
 
- TLS_PDBOPTS_ARS32
 
- TLS_PDBOPTS_ARS64
 
- TLS_PDBOPTS_EXP_RND_IV
 
- TLS_PDBOPTS_IV_WRTBK
 
- TLS_PDBOPTS_OUTFMT
 
- TLS_RECORD_TYPE_DATA
 
- TLS_RX
 
- TLS_RX_SYNC_RUNNING
 
- TLS_SET_RECORD_TYPE
 
- TLS_SIZE
 
- TLS_SW
 
- TLS_TRUNCATED_HMAC_SIZE
 
- TLS_TX
 
- TLS_TX_SYNC_SCHED
 
- TLS_VERSION_MAJOR
 
- TLS_VERSION_MINOR
 
- TLS_VERSION_NUMBER
 
- TLS_WR_CPL_LEN
 
- TLV320AIC23_ACTIVE
 
- TLV320AIC23_ACT_ON
 
- TLV320AIC23_ADCHP_ON
 
- TLV320AIC23_ADC_OFF
 
- TLV320AIC23_ANLG
 
- TLV320AIC23_BOSR_384fs
 
- TLV320AIC23_BOSR_SHIFT
 
- TLV320AIC23_BYPASS_ON
 
- TLV320AIC23_CLKIN_HALF
 
- TLV320AIC23_CLKIN_SHIFT
 
- TLV320AIC23_CLKOUT_HALF
 
- TLV320AIC23_CLKOUT_SHIFT
 
- TLV320AIC23_CLK_OFF
 
- TLV320AIC23_DACM_MUTE
 
- TLV320AIC23_DAC_OFF
 
- TLV320AIC23_DAC_SELECTED
 
- TLV320AIC23_DEEMP_32K
 
- TLV320AIC23_DEEMP_44K
 
- TLV320AIC23_DEEMP_48K
 
- TLV320AIC23_DEFAULT_IN_VOLUME
 
- TLV320AIC23_DEFAULT_OUT_VOL
 
- TLV320AIC23_DEVICE_PWR_OFF
 
- TLV320AIC23_DIGT
 
- TLV320AIC23_DIGT_FMT
 
- TLV320AIC23_FOR_DSP
 
- TLV320AIC23_FOR_I2S
 
- TLV320AIC23_FOR_LJUST
 
- TLV320AIC23_INSEL_MIC
 
- TLV320AIC23_IN_VOL_MASK
 
- TLV320AIC23_IN_VOL_MAX
 
- TLV320AIC23_IN_VOL_MIN
 
- TLV320AIC23_IN_VOL_RANGE
 
- TLV320AIC23_IWL_16
 
- TLV320AIC23_IWL_20
 
- TLV320AIC23_IWL_24
 
- TLV320AIC23_IWL_32
 
- TLV320AIC23_LCHNVOL
 
- TLV320AIC23_LHV_DEFAULT
 
- TLV320AIC23_LHV_MAX
 
- TLV320AIC23_LHV_MIN
 
- TLV320AIC23_LIM_MUTED
 
- TLV320AIC23_LINE_OFF
 
- TLV320AIC23_LINVOL
 
- TLV320AIC23_LIV_DEFAULT
 
- TLV320AIC23_LIV_MAX
 
- TLV320AIC23_LIV_MIN
 
- TLV320AIC23_LRP_ON
 
- TLV320AIC23_LRSWAP_ON
 
- TLV320AIC23_LRS_ENABLED
 
- TLV320AIC23_LZC_ON
 
- TLV320AIC23_MICB_20DB
 
- TLV320AIC23_MICM_MUTED
 
- TLV320AIC23_MIC_OFF
 
- TLV320AIC23_MS_MASTER
 
- TLV320AIC23_OSC_OFF
 
- TLV320AIC23_OUT_OFF
 
- TLV320AIC23_OUT_VOL_MASK
 
- TLV320AIC23_OUT_VOL_MAX
 
- TLV320AIC23_OUT_VOL_MIN
 
- TLV320AIC23_OUT_VO_RANGE
 
- TLV320AIC23_PWR
 
- TLV320AIC23_RCHNVOL
 
- TLV320AIC23_RESET
 
- TLV320AIC23_RINVOL
 
- TLV320AIC23_SIDETONE_0
 
- TLV320AIC23_SIDETONE_12
 
- TLV320AIC23_SIDETONE_18
 
- TLV320AIC23_SIDETONE_6
 
- TLV320AIC23_SIDETONE_9
 
- TLV320AIC23_SIDETONE_MASK
 
- TLV320AIC23_SRATE
 
- TLV320AIC23_SR_MASK
 
- TLV320AIC23_SR_SHIFT
 
- TLV320AIC23_STA_REG
 
- TLV320AIC23_STE_ENABLED
 
- TLV320AIC23_USB_CLK_ON
 
- TLV320DAC33_MCLK
 
- TLV320DAC33_SLEEPCLK
 
- TLV320_ADDRESS
 
- TLV_ALIGN
 
- TLV_ALIGNTO
 
- TLV_BODY_OFF
 
- TLV_BTCOEX_WL_AGGR_WINSIZE
 
- TLV_BTCOEX_WL_SCANTIME
 
- TLV_BUFFER_SIZE
 
- TLV_CHECK
 
- TLV_CHECK_TYPE
 
- TLV_CONTAINER_ITEM
 
- TLV_DATA
 
- TLV_DB_GAIN_MUTE
 
- TLV_DB_LINEAR_ITEM
 
- TLV_DB_MINMAX_ITEM
 
- TLV_DB_MINMAX_MUTE_ITEM
 
- TLV_DB_RANGE_HEAD
 
- TLV_DB_RANGE_ITEM
 
- TLV_DB_SCALE_ITEM
 
- TLV_DB_SCALE_MASK
 
- TLV_DB_SCALE_MUTE
 
- TLV_FLAGS
 
- TLV_FLAGS_MORE
 
- TLV_FLAGS_MORE_LAST
 
- TLV_FLAGS_MORE_NOT_LAST
 
- TLV_FLAGS_REQUIRED
 
- TLV_FLAGS_REQUIRED_LAST
 
- TLV_FLAGS_REQUIRED_NO
 
- TLV_FLAGS_REQUIRED_YES
 
- TLV_GET_DATA_LEN
 
- TLV_GET_LEN
 
- TLV_HDR_LEN
 
- TLV_ITEM
 
- TLV_ITEMS
 
- TLV_LENGTH
 
- TLV_LEN_OFF
 
- TLV_LEN_SIZE
 
- TLV_LIST_CHECK
 
- TLV_LIST_DATA
 
- TLV_LIST_EMPTY
 
- TLV_LIST_INIT
 
- TLV_LIST_STEP
 
- TLV_MIN
 
- TLV_MPOA_DEVICE_TYPE
 
- TLV_MUTE
 
- TLV_OK
 
- TLV_OUI_LEN
 
- TLV_PUT
 
- TLV_PUT_BTRFS_TIMESPEC
 
- TLV_PUT_DEFINE_INT
 
- TLV_PUT_INT
 
- TLV_PUT_PATH
 
- TLV_PUT_STRING
 
- TLV_PUT_U16
 
- TLV_PUT_U32
 
- TLV_PUT_U64
 
- TLV_PUT_U8
 
- TLV_PUT_UUID
 
- TLV_SET
 
- TLV_SET_LEN
 
- TLV_SET_TYPE
 
- TLV_SPACE
 
- TLV_STEP
 
- TLV_TYPE
 
- TLV_TYPE_API_REV
 
- TLV_TYPE_AUTH_TYPE
 
- TLV_TYPE_AUTO_DS_PARAM
 
- TLV_TYPE_BCASTPROBE
 
- TLV_TYPE_BCNMISS
 
- TLV_TYPE_BGSCAN_START_LATER
 
- TLV_TYPE_BSSID
 
- TLV_TYPE_BSS_MODE
 
- TLV_TYPE_BSS_SCAN_INFO
 
- TLV_TYPE_BSS_SCAN_RSP
 
- TLV_TYPE_CF
 
- TLV_TYPE_CHANLIST
 
- TLV_TYPE_CHANNELBANDLIST
 
- TLV_TYPE_CHANNEL_STATS
 
- TLV_TYPE_CHANRPT_11H_BASIC
 
- TLV_TYPE_CHAN_ATTR_CFG
 
- TLV_TYPE_COALESCE_RULE
 
- TLV_TYPE_CRYPTO_DATA
 
- TLV_TYPE_DOMAIN
 
- TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY
 
- TLV_TYPE_ENGINE_CKV_AUTH_TAG
 
- TLV_TYPE_ENGINE_CKV_CIPHERTEXT
 
- TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE
 
- TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
 
- TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY
 
- TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS
 
- TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY
 
- TLV_TYPE_ENGINE_CKV_IV
 
- TLV_TYPE_FAILCOUNT
 
- TLV_TYPE_GWK_CIPHER
 
- TLV_TYPE_HWRM_REQUEST
 
- TLV_TYPE_HWRM_RESPONSE
 
- TLV_TYPE_IBSS
 
- TLV_TYPE_KEY_MATERIAL
 
- TLV_TYPE_KEY_PARAM_V2
 
- TLV_TYPE_LAST
 
- TLV_TYPE_LEDBEHAVIOR
 
- TLV_TYPE_LED_GPIO
 
- TLV_TYPE_MC_GROUP_INFO
 
- TLV_TYPE_MESH_ID
 
- TLV_TYPE_MGMT_IE
 
- TLV_TYPE_MODIFY_ROCE_CC_GEN1
 
- TLV_TYPE_MULTI_CHAN_INFO
 
- TLV_TYPE_NUMPROBES
 
- TLV_TYPE_NUMSSID_PROBE
 
- TLV_TYPE_NVM
 
- TLV_TYPE_OLD_MESH_ID
 
- TLV_TYPE_PASSTHROUGH
 
- TLV_TYPE_PATCH
 
- TLV_TYPE_PHY_DS
 
- TLV_TYPE_PHY_FH
 
- TLV_TYPE_POWER_CAPABILITY
 
- TLV_TYPE_POWER_GROUP
 
- TLV_TYPE_POWER_TBL_2_4GHZ
 
- TLV_TYPE_POWER_TBL_5GHZ
 
- TLV_TYPE_PS_PARAM
 
- TLV_TYPE_PS_PARAMS_IN_HS
 
- TLV_TYPE_PWK_CIPHER
 
- TLV_TYPE_PWR_CONSTRAINT
 
- TLV_TYPE_QUERY_ROCE_CC_GEN1
 
- TLV_TYPE_RANDOM_MAC
 
- TLV_TYPE_RATES
 
- TLV_TYPE_RATE_DROP_CONTROL
 
- TLV_TYPE_RATE_SCOPE
 
- TLV_TYPE_REASSOCAP
 
- TLV_TYPE_REPEAT_COUNT
 
- TLV_TYPE_ROBUST_COEX
 
- TLV_TYPE_ROCE_SP_COMMAND
 
- TLV_TYPE_RSSI_HIGH
 
- TLV_TYPE_RSSI_LOW
 
- TLV_TYPE_RXBA_SYNC
 
- TLV_TYPE_SCAN_CHANNEL_GAP
 
- TLV_TYPE_SIZE
 
- TLV_TYPE_SNR_HIGH
 
- TLV_TYPE_SNR_LOW
 
- TLV_TYPE_SSID
 
- TLV_TYPE_STA_MAC_ADDR
 
- TLV_TYPE_TDLS_IDLE_TIMEOUT
 
- TLV_TYPE_TSFTIMESTAMP
 
- TLV_TYPE_TX_PAUSE
 
- TLV_TYPE_UAP_AKMP
 
- TLV_TYPE_UAP_AO_TIMER
 
- TLV_TYPE_UAP_BCAST_SSID
 
- TLV_TYPE_UAP_BEACON_PERIOD
 
- TLV_TYPE_UAP_DTIM_PERIOD
 
- TLV_TYPE_UAP_ENCRY_PROTOCOL
 
- TLV_TYPE_UAP_FRAG_THRESHOLD
 
- TLV_TYPE_UAP_MGMT_FRAME
 
- TLV_TYPE_UAP_PS_AO_TIMER
 
- TLV_TYPE_UAP_RATES
 
- TLV_TYPE_UAP_RETRY_LIMIT
 
- TLV_TYPE_UAP_RTS_THRESHOLD
 
- TLV_TYPE_UAP_SSID
 
- TLV_TYPE_UAP_WEP_KEY
 
- TLV_TYPE_UAP_WPA_PASSPHRASE
 
- TLV_TYPE_WAPI_IE
 
- TLV_TYPE_WILDCARDSSID
 
- TLV_TYPE_WMMQSTATUS
 
- TL_PROTOCOLID_COM_CTRL
 
- TL_PROTOCOLID_COM_DATA
 
- TL_PROTOCOLID_SETUP
 
- TL_PRTY
 
- TL_SETUP_MAX_VERSION_QRY
 
- TL_SETUP_SIGNO_CLOSE_MSG
 
- TL_SETUP_SIGNO_CONFIG_DONE_MSG
 
- TL_SETUP_SIGNO_CONFIG_MSG
 
- TL_SETUP_SIGNO_GET_VERSION_QRY
 
- TL_SETUP_SIGNO_GET_VERSION_RSP
 
- TL_SETUP_SIGNO_INFO_MSG
 
- TL_SETUP_SIGNO_INFO_MSG_ACK
 
- TL_SETUP_SIGNO_OPEN_MSG
 
- TL_SETUP_SIGNO_REBOOT_MSG
 
- TL_SETUP_SIGNO_REBOOT_MSG_ACK
 
- TL_SETUP_VERSION
 
- TL_SETUP_VERSION_QRY_TMO
 
- TL_TPGS_PER_HBA
 
- TL_WWN_ADDR_LEN
 
- TM
 
- TM1
 
- TM2TX
 
- TM2_DAI_AIF1
 
- TM2_DAI_AIF2
 
- TM2_TOUCHKEY_BIT_KEYCODE
 
- TM2_TOUCHKEY_BIT_PRESS_EV
 
- TM2_TOUCHKEY_CMD_LED_OFF
 
- TM2_TOUCHKEY_CMD_LED_ON
 
- TM2_TOUCHKEY_DEV_NAME
 
- TM2_TOUCHKEY_LED_VOLTAGE_MAX
 
- TM2_TOUCHKEY_LED_VOLTAGE_MIN
 
- TM5600
 
- TM5600_BOARD_10MOONS_UT330
 
- TM5600_BOARD_10MOONS_UT821
 
- TM5600_BOARD_GENERIC
 
- TM5600_BOARD_TERRATEC_GRABSTER
 
- TM6000
 
- TM6000_AMUX_ADC1
 
- TM6000_AMUX_ADC2
 
- TM6000_AMUX_I2S
 
- TM6000_AMUX_SIF1
 
- TM6000_AMUX_SIF2
 
- TM6000_AUDIO
 
- TM6000_BOARD_ADSTECH_DUAL_TV
 
- TM6000_BOARD_ADSTECH_MINI_DUAL_TV
 
- TM6000_BOARD_FREECOM_AND_SIMILAR
 
- TM6000_BOARD_GENERIC
 
- TM6000_BOARD_UNKNOWN
 
- TM6000_DEF_BUF
 
- TM6000_DVB
 
- TM6000_GPIO_1
 
- TM6000_GPIO_2
 
- TM6000_GPIO_3
 
- TM6000_GPIO_4
 
- TM6000_GPIO_5
 
- TM6000_GPIO_6
 
- TM6000_GPIO_7
 
- TM6000_GPIO_CLK
 
- TM6000_GPIO_DATA
 
- TM6000_INPUT_COMPOSITE1
 
- TM6000_INPUT_COMPOSITE2
 
- TM6000_INPUT_DVB
 
- TM6000_INPUT_RADIO
 
- TM6000_INPUT_SVIDEO
 
- TM6000_INPUT_TV
 
- TM6000_MAXBOARDS
 
- TM6000_MAX_ISO_PACKETS
 
- TM6000_MIN_BUF
 
- TM6000_MODE_ANALOG
 
- TM6000_MODE_DIGITAL
 
- TM6000_MODE_UNKNOWN
 
- TM6000_NUM_URB_BUF
 
- TM6000_QUIRK_NO_USB_DELAY
 
- TM6000_REQ07_RD8_TEST_SEL
 
- TM6000_REQ07_RD9_A_SIM_SEL
 
- TM6000_REQ07_RDA_CLK_SEL
 
- TM6000_REQ07_RDB_OUT_SEL
 
- TM6000_REQ07_RDC_NSEL_I2S
 
- TM6000_REQ07_RDD_GPIO2_MDRV
 
- TM6000_REQ07_RDE_GPIO1_MDRV
 
- TM6000_REQ07_RDF_PWDOWN_ACLK
 
- TM6000_REQ07_RE0_VADC_REF_CTL
 
- TM6000_REQ07_RE1_VADC_DACLIMP
 
- TM6000_REQ07_RE2_VADC_STATUS_CTL
 
- TM6000_REQ07_RE3_VADC_INP_LPF_SEL1
 
- TM6000_REQ07_RE4_VADC_TARGET1
 
- TM6000_REQ07_RE5_VADC_INP_LPF_SEL2
 
- TM6000_REQ07_RE6_VADC_TARGET2
 
- TM6000_REQ07_RE7_VADC_AGAIN_CTL
 
- TM6000_REQ07_RE8_VADC_PWDOWN_CTL
 
- TM6000_REQ07_RE9_VADC_INPUT_CTL1
 
- TM6000_REQ07_REA_VADC_INPUT_CTL2
 
- TM6000_REQ07_REB_VADC_AADC_MODE
 
- TM6000_REQ07_REC_VADC_AADC_LVOL
 
- TM6000_REQ07_RED_VADC_AADC_RVOL
 
- TM6000_REQ07_REE_VADC_CTRL_SEL_CONTROL
 
- TM6000_REQ07_REF_VADC_GAIN_MAP_CTL
 
- TM6000_REQ07_RFD_BIST_ERR_VST_LOW
 
- TM6000_REQ07_RFE_BIST_ERR_VST_HIGH
 
- TM6000_STD
 
- TM6000_URB_MSG_AUDIO
 
- TM6000_URB_MSG_ERR
 
- TM6000_URB_MSG_LEN
 
- TM6000_URB_MSG_PTS
 
- TM6000_URB_MSG_VBI
 
- TM6000_URB_MSG_VIDEO
 
- TM6000_VMUX_VIDEO_A
 
- TM6000_VMUX_VIDEO_AB
 
- TM6000_VMUX_VIDEO_B
 
- TM6010
 
- TM6010_BOARD_BEHOLD_VOYAGER
 
- TM6010_BOARD_BEHOLD_VOYAGER_LITE
 
- TM6010_BOARD_BEHOLD_WANDER
 
- TM6010_BOARD_BEHOLD_WANDER_LITE
 
- TM6010_BOARD_GENERIC
 
- TM6010_BOARD_HAUPPAUGE_900H
 
- TM6010_BOARD_TERRATEC_CINERGY_HYBRID_XE
 
- TM6010_BOARD_TWINHAN_TU501
 
- TM6010_GPIO_0
 
- TM6010_GPIO_1
 
- TM6010_GPIO_2
 
- TM6010_GPIO_3
 
- TM6010_GPIO_4
 
- TM6010_GPIO_5
 
- TM6010_GPIO_6
 
- TM6010_GPIO_7
 
- TM6010_GPIO_9
 
- TM6010_REQ05_R00_MAIN_CTRL
 
- TM6010_REQ05_R01_DEVADDR
 
- TM6010_REQ05_R02_TEST
 
- TM6010_REQ05_R04_SOFN0
 
- TM6010_REQ05_R05_SOFN1
 
- TM6010_REQ05_R06_SOFTM0
 
- TM6010_REQ05_R07_SOFTM1
 
- TM6010_REQ05_R08_PHY_TEST
 
- TM6010_REQ05_R09_VCTL
 
- TM6010_REQ05_R0A_VSTA
 
- TM6010_REQ05_R0B_CX_CFG
 
- TM6010_REQ05_R0C_ENDP0_REG0
 
- TM6010_REQ05_R10_GMASK
 
- TM6010_REQ05_R11_IMASK0
 
- TM6010_REQ05_R12_IMASK1
 
- TM6010_REQ05_R13_IMASK2
 
- TM6010_REQ05_R14_IMASK3
 
- TM6010_REQ05_R15_IMASK4
 
- TM6010_REQ05_R16_IMASK5
 
- TM6010_REQ05_R17_IMASK6
 
- TM6010_REQ05_R18_IMASK7
 
- TM6010_REQ05_R19_ZEROP0
 
- TM6010_REQ05_R1A_ZEROP1
 
- TM6010_REQ05_R1C_FIFO_EMP0
 
- TM6010_REQ05_R1D_FIFO_EMP1
 
- TM6010_REQ05_R20_IRQ_GROUP
 
- TM6010_REQ05_R21_IRQ_SOURCE0
 
- TM6010_REQ05_R22_IRQ_SOURCE1
 
- TM6010_REQ05_R23_IRQ_SOURCE2
 
- TM6010_REQ05_R24_IRQ_SOURCE3
 
- TM6010_REQ05_R25_IRQ_SOURCE4
 
- TM6010_REQ05_R26_IRQ_SOURCE5
 
- TM6010_REQ05_R27_IRQ_SOURCE6
 
- TM6010_REQ05_R28_IRQ_SOURCE7
 
- TM6010_REQ05_R29_SEQ_ERR0
 
- TM6010_REQ05_R2A_SEQ_ERR1
 
- TM6010_REQ05_R2B_SEQ_ABORT0
 
- TM6010_REQ05_R2C_SEQ_ABORT1
 
- TM6010_REQ05_R2D_TX_ZERO0
 
- TM6010_REQ05_R2E_TX_ZERO1
 
- TM6010_REQ05_R2F_IDLE_CNT
 
- TM6010_REQ05_R30_FNO_P1
 
- TM6010_REQ05_R30_FNO_P10
 
- TM6010_REQ05_R30_FNO_P11
 
- TM6010_REQ05_R30_FNO_P12
 
- TM6010_REQ05_R30_FNO_P13
 
- TM6010_REQ05_R30_FNO_P14
 
- TM6010_REQ05_R30_FNO_P15
 
- TM6010_REQ05_R31_FNO_P2
 
- TM6010_REQ05_R32_FNO_P3
 
- TM6010_REQ05_R33_FNO_P4
 
- TM6010_REQ05_R34_FNO_P5
 
- TM6010_REQ05_R35_FNO_P6
 
- TM6010_REQ05_R36_FNO_P7
 
- TM6010_REQ05_R37_FNO_P8
 
- TM6010_REQ05_R38_FNO_P9
 
- TM6010_REQ05_R40_IN_MAXPS_LOW1
 
- TM6010_REQ05_R40_IN_MAXPS_LOW10
 
- TM6010_REQ05_R40_IN_MAXPS_LOW11
 
- TM6010_REQ05_R40_IN_MAXPS_LOW12
 
- TM6010_REQ05_R40_IN_MAXPS_LOW13
 
- TM6010_REQ05_R40_IN_MAXPS_LOW14
 
- TM6010_REQ05_R40_IN_MAXPS_LOW15
 
- TM6010_REQ05_R41_IN_MAXPS_HIGH1
 
- TM6010_REQ05_R41_IN_MAXPS_HIGH10
 
- TM6010_REQ05_R41_IN_MAXPS_HIGH11
 
- TM6010_REQ05_R41_IN_MAXPS_HIGH12
 
- TM6010_REQ05_R41_IN_MAXPS_HIGH13
 
- TM6010_REQ05_R41_IN_MAXPS_HIGH14
 
- TM6010_REQ05_R41_IN_MAXPS_HIGH15
 
- TM6010_REQ05_R42_IN_MAXPS_LOW2
 
- TM6010_REQ05_R43_IN_MAXPS_HIGH2
 
- TM6010_REQ05_R44_IN_MAXPS_LOW3
 
- TM6010_REQ05_R45_IN_MAXPS_HIGH3
 
- TM6010_REQ05_R46_IN_MAXPS_LOW4
 
- TM6010_REQ05_R47_IN_MAXPS_HIGH4
 
- TM6010_REQ05_R48_IN_MAXPS_LOW5
 
- TM6010_REQ05_R49_IN_MAXPS_HIGH5
 
- TM6010_REQ05_R4A_IN_MAXPS_LOW6
 
- TM6010_REQ05_R4B_IN_MAXPS_HIGH6
 
- TM6010_REQ05_R4C_IN_MAXPS_LOW7
 
- TM6010_REQ05_R4D_IN_MAXPS_HIGH7
 
- TM6010_REQ05_R4E_IN_MAXPS_LOW8
 
- TM6010_REQ05_R4F_IN_MAXPS_HIGH8
 
- TM6010_REQ05_R50_IN_MAXPS_LOW9
 
- TM6010_REQ05_R51_IN_MAXPS_HIGH9
 
- TM6010_REQ05_R60_OUT_MAXPS_LOW1
 
- TM6010_REQ05_R60_OUT_MAXPS_LOW10
 
- TM6010_REQ05_R60_OUT_MAXPS_LOW11
 
- TM6010_REQ05_R60_OUT_MAXPS_LOW12
 
- TM6010_REQ05_R60_OUT_MAXPS_LOW13
 
- TM6010_REQ05_R60_OUT_MAXPS_LOW14
 
- TM6010_REQ05_R60_OUT_MAXPS_LOW15
 
- TM6010_REQ05_R61_OUT_MAXPS_HIGH1
 
- TM6010_REQ05_R61_OUT_MAXPS_HIGH10
 
- TM6010_REQ05_R61_OUT_MAXPS_HIGH11
 
- TM6010_REQ05_R61_OUT_MAXPS_HIGH12
 
- TM6010_REQ05_R61_OUT_MAXPS_HIGH13
 
- TM6010_REQ05_R61_OUT_MAXPS_HIGH14
 
- TM6010_REQ05_R61_OUT_MAXPS_HIGH15
 
- TM6010_REQ05_R62_OUT_MAXPS_LOW2
 
- TM6010_REQ05_R63_OUT_MAXPS_HIGH2
 
- TM6010_REQ05_R64_OUT_MAXPS_LOW3
 
- TM6010_REQ05_R65_OUT_MAXPS_HIGH3
 
- TM6010_REQ05_R66_OUT_MAXPS_LOW4
 
- TM6010_REQ05_R67_OUT_MAXPS_HIGH4
 
- TM6010_REQ05_R68_OUT_MAXPS_LOW5
 
- TM6010_REQ05_R69_OUT_MAXPS_HIGH5
 
- TM6010_REQ05_R6A_OUT_MAXPS_LOW6
 
- TM6010_REQ05_R6B_OUT_MAXPS_HIGH6
 
- TM6010_REQ05_R6C_OUT_MAXPS_LOW7
 
- TM6010_REQ05_R6D_OUT_MAXPS_HIGH7
 
- TM6010_REQ05_R6E_OUT_MAXPS_LOW8
 
- TM6010_REQ05_R6F_OUT_MAXPS_HIGH8
 
- TM6010_REQ05_R70_OUT_MAXPS_LOW9
 
- TM6010_REQ05_R71_OUT_MAXPS_HIGH9
 
- TM6010_REQ05_R80_FIFO0
 
- TM6010_REQ05_R81_FIFO1
 
- TM6010_REQ05_R81_FIFO10
 
- TM6010_REQ05_R81_FIFO11
 
- TM6010_REQ05_R81_FIFO12
 
- TM6010_REQ05_R81_FIFO13
 
- TM6010_REQ05_R81_FIFO14
 
- TM6010_REQ05_R81_FIFO15
 
- TM6010_REQ05_R82_FIFO2
 
- TM6010_REQ05_R83_FIFO3
 
- TM6010_REQ05_R84_FIFO4
 
- TM6010_REQ05_R85_FIFO5
 
- TM6010_REQ05_R86_FIFO6
 
- TM6010_REQ05_R87_FIFO7
 
- TM6010_REQ05_R88_FIFO8
 
- TM6010_REQ05_R89_FIFO9
 
- TM6010_REQ05_R90_CFG_FIFO0
 
- TM6010_REQ05_R91_CFG_FIFO1
 
- TM6010_REQ05_R91_CFG_FIFO10
 
- TM6010_REQ05_R91_CFG_FIFO11
 
- TM6010_REQ05_R91_CFG_FIFO12
 
- TM6010_REQ05_R91_CFG_FIFO13
 
- TM6010_REQ05_R91_CFG_FIFO14
 
- TM6010_REQ05_R91_CFG_FIFO15
 
- TM6010_REQ05_R92_CFG_FIFO2
 
- TM6010_REQ05_R93_CFG_FIFO3
 
- TM6010_REQ05_R94_CFG_FIFO4
 
- TM6010_REQ05_R95_CFG_FIFO5
 
- TM6010_REQ05_R96_CFG_FIFO6
 
- TM6010_REQ05_R97_CFG_FIFO7
 
- TM6010_REQ05_R98_CFG_FIFO8
 
- TM6010_REQ05_R99_CFG_FIFO9
 
- TM6010_REQ05_RA0_CTL_FIFO0
 
- TM6010_REQ05_RA1_CTL_FIFO1
 
- TM6010_REQ05_RA1_CTL_FIFO10
 
- TM6010_REQ05_RA1_CTL_FIFO11
 
- TM6010_REQ05_RA1_CTL_FIFO12
 
- TM6010_REQ05_RA1_CTL_FIFO13
 
- TM6010_REQ05_RA1_CTL_FIFO14
 
- TM6010_REQ05_RA1_CTL_FIFO15
 
- TM6010_REQ05_RA2_CTL_FIFO2
 
- TM6010_REQ05_RA3_CTL_FIFO3
 
- TM6010_REQ05_RA4_CTL_FIFO4
 
- TM6010_REQ05_RA5_CTL_FIFO5
 
- TM6010_REQ05_RA6_CTL_FIFO6
 
- TM6010_REQ05_RA7_CTL_FIFO7
 
- TM6010_REQ05_RA8_CTL_FIFO8
 
- TM6010_REQ05_RA9_CTL_FIFO9
 
- TM6010_REQ05_RB0_BC_LOW_FIFO0
 
- TM6010_REQ05_RB1_BC_LOW_FIFO1
 
- TM6010_REQ05_RB1_BC_LOW_FIFO10
 
- TM6010_REQ05_RB1_BC_LOW_FIFO11
 
- TM6010_REQ05_RB1_BC_LOW_FIFO12
 
- TM6010_REQ05_RB1_BC_LOW_FIFO13
 
- TM6010_REQ05_RB1_BC_LOW_FIFO14
 
- TM6010_REQ05_RB1_BC_LOW_FIFO15
 
- TM6010_REQ05_RB2_BC_LOW_FIFO2
 
- TM6010_REQ05_RB3_BC_LOW_FIFO3
 
- TM6010_REQ05_RB4_BC_LOW_FIFO4
 
- TM6010_REQ05_RB5_BC_LOW_FIFO5
 
- TM6010_REQ05_RB6_BC_LOW_FIFO6
 
- TM6010_REQ05_RB7_BC_LOW_FIFO7
 
- TM6010_REQ05_RB8_BC_LOW_FIFO8
 
- TM6010_REQ05_RB9_BC_LOW_FIFO9
 
- TM6010_REQ05_RC0_DATA_FIFO0
 
- TM6010_REQ05_RC4_DATA_FIFO1
 
- TM6010_REQ05_RC4_DATA_FIFO10
 
- TM6010_REQ05_RC4_DATA_FIFO11
 
- TM6010_REQ05_RC4_DATA_FIFO12
 
- TM6010_REQ05_RC4_DATA_FIFO13
 
- TM6010_REQ05_RC4_DATA_FIFO14
 
- TM6010_REQ05_RC4_DATA_FIFO15
 
- TM6010_REQ05_RC8_DATA_FIFO2
 
- TM6010_REQ05_RCC_DATA_FIFO3
 
- TM6010_REQ05_RD0_DATA_FIFO4
 
- TM6010_REQ05_RD4_DATA_FIFO5
 
- TM6010_REQ05_RD8_DATA_FIFO6
 
- TM6010_REQ05_RDC_DATA_FIFO7
 
- TM6010_REQ05_RE0_DATA_FIFO8
 
- TM6010_REQ05_RE4_DATA_FIFO9
 
- TM6010_REQ07_R00_VIDEO_CONTROL0
 
- TM6010_REQ07_R01_VIDEO_CONTROL1
 
- TM6010_REQ07_R02_VIDEO_CONTROL2
 
- TM6010_REQ07_R03_YC_SEP_CONTROL
 
- TM6010_REQ07_R04_LUMA_HAGC_CONTROL
 
- TM6010_REQ07_R05_NOISE_THRESHOLD
 
- TM6010_REQ07_R06_AGC_GATE_THRESHOLD
 
- TM6010_REQ07_R07_OUTPUT_CONTROL
 
- TM6010_REQ07_R08_LUMA_CONTRAST_ADJ
 
- TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ
 
- TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ
 
- TM6010_REQ07_R0B_CHROMA_HUE_PHASE_ADJ
 
- TM6010_REQ07_R0C_CHROMA_AGC_CONTROL
 
- TM6010_REQ07_R0D_CHROMA_KILL_LEVEL
 
- TM6010_REQ07_R0F_CHROMA_AUTO_POSITION
 
- TM6010_REQ07_R10_AGC_PEAK_NOMINAL
 
- TM6010_REQ07_R11_AGC_PEAK_CONTROL
 
- TM6010_REQ07_R12_AGC_GATE_STARTH
 
- TM6010_REQ07_R13_AGC_GATE_STARTL
 
- TM6010_REQ07_R14_AGC_GATE_WIDTH
 
- TM6010_REQ07_R15_AGC_BP_DELAY
 
- TM6010_REQ07_R16_LOCK_COUNT
 
- TM6010_REQ07_R17_HLOOP_MAXSTATE
 
- TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3
 
- TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2
 
- TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1
 
- TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0
 
- TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3
 
- TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2
 
- TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1
 
- TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0
 
- TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME
 
- TM6010_REQ07_R21_HSYNC_PHASE_OFFSET
 
- TM6010_REQ07_R22_HSYNC_PLL_START_TIME
 
- TM6010_REQ07_R23_HSYNC_PLL_END_TIME
 
- TM6010_REQ07_R24_HSYNC_TIP_START_TIME
 
- TM6010_REQ07_R25_HSYNC_TIP_END_TIME
 
- TM6010_REQ07_R26_HSYNC_RISING_EDGE_START
 
- TM6010_REQ07_R27_HSYNC_RISING_EDGE_END
 
- TM6010_REQ07_R28_BACKPORCH_START
 
- TM6010_REQ07_R29_BACKPORCH_END
 
- TM6010_REQ07_R2A_HSYNC_FILTER_START
 
- TM6010_REQ07_R2B_HSYNC_FILTER_END
 
- TM6010_REQ07_R2C_CHROMA_BURST_START
 
- TM6010_REQ07_R2D_CHROMA_BURST_END
 
- TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART
 
- TM6010_REQ07_R2F_ACTIVE_VIDEO_HWIDTH
 
- TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART
 
- TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT
 
- TM6010_REQ07_R32_VSYNC_HLOCK_MIN
 
- TM6010_REQ07_R33_VSYNC_HLOCK_MAX
 
- TM6010_REQ07_R34_VSYNC_AGC_MIN
 
- TM6010_REQ07_R35_VSYNC_AGC_MAX
 
- TM6010_REQ07_R36_VSYNC_VBI_MIN
 
- TM6010_REQ07_R37_VSYNC_VBI_MAX
 
- TM6010_REQ07_R38_VSYNC_THRESHOLD
 
- TM6010_REQ07_R39_VSYNC_TIME_CONSTANT
 
- TM6010_REQ07_R3A_STATUS1
 
- TM6010_REQ07_R3B_STATUS2
 
- TM6010_REQ07_R3C_STATUS3
 
- TM6010_REQ07_R3F_RESET
 
- TM6010_REQ07_R40_TELETEXT_VBI_CODE0
 
- TM6010_REQ07_R41_TELETEXT_VBI_CODE1
 
- TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL
 
- TM6010_REQ07_R43_VBI_DATA_TYPE_LINE7
 
- TM6010_REQ07_R44_VBI_DATA_TYPE_LINE8
 
- TM6010_REQ07_R45_VBI_DATA_TYPE_LINE9
 
- TM6010_REQ07_R46_VBI_DATA_TYPE_LINE10
 
- TM6010_REQ07_R47_VBI_DATA_TYPE_LINE11
 
- TM6010_REQ07_R48_VBI_DATA_TYPE_LINE12
 
- TM6010_REQ07_R49_VBI_DATA_TYPE_LINE13
 
- TM6010_REQ07_R4A_VBI_DATA_TYPE_LINE14
 
- TM6010_REQ07_R4B_VBI_DATA_TYPE_LINE15
 
- TM6010_REQ07_R4C_VBI_DATA_TYPE_LINE16
 
- TM6010_REQ07_R4D_VBI_DATA_TYPE_LINE17
 
- TM6010_REQ07_R4E_VBI_DATA_TYPE_LINE18
 
- TM6010_REQ07_R4F_VBI_DATA_TYPE_LINE19
 
- TM6010_REQ07_R50_VBI_DATA_TYPE_LINE20
 
- TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21
 
- TM6010_REQ07_R52_VBI_DATA_TYPE_LINE22
 
- TM6010_REQ07_R53_VBI_DATA_TYPE_LINE23
 
- TM6010_REQ07_R54_VBI_DATA_TYPE_RLINES
 
- TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN
 
- TM6010_REQ07_R56_VBI_LOOP_FILTER_I_GAIN
 
- TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN
 
- TM6010_REQ07_R58_VBI_CAPTION_DTO1
 
- TM6010_REQ07_R59_VBI_CAPTION_DTO0
 
- TM6010_REQ07_R5A_VBI_TELETEXT_DTO1
 
- TM6010_REQ07_R5B_VBI_TELETEXT_DTO0
 
- TM6010_REQ07_R5C_VBI_WSS625_DTO1
 
- TM6010_REQ07_R5D_VBI_WSS625_DTO0
 
- TM6010_REQ07_R5E_VBI_CAPTION_FRAME_START
 
- TM6010_REQ07_R5F_VBI_WSS625_FRAME_START
 
- TM6010_REQ07_R60_TELETEXT_FRAME_START
 
- TM6010_REQ07_R61_VBI_CCDATA1
 
- TM6010_REQ07_R62_VBI_CCDATA2
 
- TM6010_REQ07_R63_VBI_WSS625_DATA1
 
- TM6010_REQ07_R64_VBI_WSS625_DATA2
 
- TM6010_REQ07_R65_VBI_DATA_STATUS
 
- TM6010_REQ07_R66_VBI_CAPTION_START
 
- TM6010_REQ07_R67_VBI_WSS625_START
 
- TM6010_REQ07_R68_VBI_TELETEXT_START
 
- TM6010_REQ07_R70_HSYNC_DTO_INC_STATUS3
 
- TM6010_REQ07_R71_HSYNC_DTO_INC_STATUS2
 
- TM6010_REQ07_R72_HSYNC_DTO_INC_STATUS1
 
- TM6010_REQ07_R73_HSYNC_DTO_INC_STATUS0
 
- TM6010_REQ07_R74_CHROMA_DTO_INC_STATUS3
 
- TM6010_REQ07_R75_CHROMA_DTO_INC_STATUS2
 
- TM6010_REQ07_R76_CHROMA_DTO_INC_STATUS1
 
- TM6010_REQ07_R77_CHROMA_DTO_INC_STATUS0
 
- TM6010_REQ07_R78_AGC_AGAIN_STATUS
 
- TM6010_REQ07_R79_AGC_DGAIN_STATUS
 
- TM6010_REQ07_R7A_CHROMA_MAG_STATUS
 
- TM6010_REQ07_R7B_CHROMA_GAIN_STATUS1
 
- TM6010_REQ07_R7C_CHROMA_GAIN_STATUS0
 
- TM6010_REQ07_R7D_CORDIC_FREQ_STATUS
 
- TM6010_REQ07_R7F_STATUS_NOISE
 
- TM6010_REQ07_R80_COMB_FILTER_TRESHOLD
 
- TM6010_REQ07_R82_COMB_FILTER_CONFIG
 
- TM6010_REQ07_R83_CHROMA_LOCK_CONFIG
 
- TM6010_REQ07_R84_NOISE_NTSC_C
 
- TM6010_REQ07_R85_NOISE_PAL_C
 
- TM6010_REQ07_R86_NOISE_PHASE_C
 
- TM6010_REQ07_R87_NOISE_PHASE_Y
 
- TM6010_REQ07_R8A_CHROMA_LOOPFILTER_STATE
 
- TM6010_REQ07_R8B_CHROMA_HRESAMPLER
 
- TM6010_REQ07_R8D_CPUMP_DELAY_ADJ
 
- TM6010_REQ07_R8E_CPUMP_ADJ
 
- TM6010_REQ07_R8F_CPUMP_DELAY
 
- TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE
 
- TM6010_REQ07_RC1_TRESHOLD
 
- TM6010_REQ07_RC2_HSYNC_WIDTH
 
- TM6010_REQ07_RC3_HSTART1
 
- TM6010_REQ07_RC4_HSTART0
 
- TM6010_REQ07_RC5_HEND1
 
- TM6010_REQ07_RC6_HEND0
 
- TM6010_REQ07_RC7_VSTART1
 
- TM6010_REQ07_RC8_VSTART0
 
- TM6010_REQ07_RC9_VEND1
 
- TM6010_REQ07_RCA_VEND0
 
- TM6010_REQ07_RCB_DELAY
 
- TM6010_REQ07_RCC_ACTIVE_IF
 
- TM6010_REQ07_RCC_ACTIVE_IF_AUDIO_ENABLE
 
- TM6010_REQ07_RCC_ACTIVE_IF_VIDEO_ENABLE
 
- TM6010_REQ07_RD0_USB_PERIPHERY_CONTROL
 
- TM6010_REQ07_RD1_ADDR_FOR_REQ1
 
- TM6010_REQ07_RD2_ADDR_FOR_REQ2
 
- TM6010_REQ07_RD3_ADDR_FOR_REQ3
 
- TM6010_REQ07_RD4_ADDR_FOR_REQ4
 
- TM6010_REQ07_RD5_POWERSAVE
 
- TM6010_REQ07_RD6_ENDP_REQ1_REQ2
 
- TM6010_REQ07_RD7_ENDP_REQ3_REQ4
 
- TM6010_REQ07_RD8_IR
 
- TM6010_REQ07_RD9_IR_BSIZE
 
- TM6010_REQ07_RDA_IR_WAKEUP_SEL
 
- TM6010_REQ07_RDB_IR_WAKEUP_ADD
 
- TM6010_REQ07_RDC_IR_LEADER1
 
- TM6010_REQ07_RDD_IR_LEADER0
 
- TM6010_REQ07_RDE_IR_PULSE_CNT1
 
- TM6010_REQ07_RDF_IR_PULSE_CNT0
 
- TM6010_REQ07_RE0_DVIDEO_SOURCE
 
- TM6010_REQ07_RE0_DVIDEO_SOURCE_IF
 
- TM6010_REQ07_RE2_OUT_SEL2
 
- TM6010_REQ07_RE3_OUT_SEL1
 
- TM6010_REQ07_RE4_OUT_SEL0
 
- TM6010_REQ07_RE5_REMOTE_WAKEUP
 
- TM6010_REQ07_RE7_PUB_GPIO
 
- TM6010_REQ07_RE8_TYPESEL_MOS_I2S
 
- TM6010_REQ07_RE9_TYPESEL_MOS_TS
 
- TM6010_REQ07_REA_TYPESEL_MOS_CCIR
 
- TM6010_REQ07_RF0_BIST_CRC_RESULT0
 
- TM6010_REQ07_RF1_BIST_CRC_RESULT1
 
- TM6010_REQ07_RF2_BIST_CRC_RESULT2
 
- TM6010_REQ07_RF3_BIST_CRC_RESULT3
 
- TM6010_REQ07_RF4_BIST_ERR_VST2
 
- TM6010_REQ07_RF5_BIST_ERR_VST1
 
- TM6010_REQ07_RF6_BIST_ERR_VST0
 
- TM6010_REQ07_RF7_BIST
 
- TM6010_REQ07_RFE_POWER_DOWN
 
- TM6010_REQ07_RFF_SOFT_RESET
 
- TM6010_REQ08_R00_A_VERSION
 
- TM6010_REQ08_R01_A_INIT
 
- TM6010_REQ08_R02_A_FIX_GAIN_CTRL
 
- TM6010_REQ08_R03_A_AUTO_GAIN_CTRL
 
- TM6010_REQ08_R04_A_SIF_AMP_CTRL
 
- TM6010_REQ08_R05_A_STANDARD_MOD
 
- TM6010_REQ08_R06_A_SOUND_MOD
 
- TM6010_REQ08_R07_A_LEFT_VOL
 
- TM6010_REQ08_R08_A_RIGHT_VOL
 
- TM6010_REQ08_R09_A_MAIN_VOL
 
- TM6010_REQ08_R0A_A_I2S_MOD
 
- TM6010_REQ08_R0B_A_ASD_THRES1
 
- TM6010_REQ08_R0C_A_ASD_THRES2
 
- TM6010_REQ08_R0D_A_AMD_THRES
 
- TM6010_REQ08_R0E_A_MONO_THRES1
 
- TM6010_REQ08_R0F_A_MONO_THRES2
 
- TM6010_REQ08_R10_A_MUTE_THRES1
 
- TM6010_REQ08_R11_A_MUTE_THRES2
 
- TM6010_REQ08_R12_A_AGC_U
 
- TM6010_REQ08_R13_A_AGC_ERR_T
 
- TM6010_REQ08_R14_A_AGC_GAIN_INIT
 
- TM6010_REQ08_R15_A_AGC_STEP_THR
 
- TM6010_REQ08_R16_A_AGC_GAIN_MAX
 
- TM6010_REQ08_R17_A_AGC_GAIN_MIN
 
- TM6010_REQ08_R18_A_TR_CTRL
 
- TM6010_REQ08_R19_A_FH_2FH_GAIN
 
- TM6010_REQ08_R1A_A_NICAM_SER_MAX
 
- TM6010_REQ08_R1B_A_NICAM_SER_MIN
 
- TM6010_REQ08_R1E_A_GAIN_DEEMPH_OUT
 
- TM6010_REQ08_R1F_A_TEST_INTF_SEL
 
- TM6010_REQ08_R20_A_TEST_PIN_SEL
 
- TM6010_REQ08_R21_A_AGC_ERR
 
- TM6010_REQ08_R22_A_AGC_GAIN
 
- TM6010_REQ08_R23_A_NICAM_INFO
 
- TM6010_REQ08_R24_A_SER
 
- TM6010_REQ08_R25_A_C1_AMP
 
- TM6010_REQ08_R26_A_C2_AMP
 
- TM6010_REQ08_R27_A_NOISE_AMP
 
- TM6010_REQ08_R28_A_AUDIO_MODE_RES
 
- TM6010_REQ08_RE0_ADC_REF
 
- TM6010_REQ08_RE1_DAC_CLMP
 
- TM6010_REQ08_RE2_POWER_DOWN_CTRL1
 
- TM6010_REQ08_RE3_ADC_IN1_SEL
 
- TM6010_REQ08_RE4_ADC_IN2_SEL
 
- TM6010_REQ08_RE5_GAIN_PARAM
 
- TM6010_REQ08_RE6_POWER_DOWN_CTRL2
 
- TM6010_REQ08_RE7_REG_GAIN_Y
 
- TM6010_REQ08_RE8_REG_GAIN_C
 
- TM6010_REQ08_RE9_BIAS_CTRL
 
- TM6010_REQ08_REA_BUFF_DRV_CTRL
 
- TM6010_REQ08_REB_SIF_GAIN_CTRL
 
- TM6010_REQ08_REC_REVERSE_YC_CTRL
 
- TM6010_REQ08_RED_GAIN_SEL
 
- TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG
 
- TM6010_REQ08_RF1_AADC_POWER_DOWN
 
- TM6010_REQ08_RF2_LEFT_CHANNEL_VOL
 
- TM6010_REQ08_RF3_RIGHT_CHANNEL_VOL
 
- TMABR_BA
 
- TMAC_AVG_IPG
 
- TMAC_DESC_ECC_DB_ERR
 
- TMAC_DESC_ECC_SG_ERR
 
- TMAC_ECC_DB_ERR
 
- TMAC_ECC_SG_ERR
 
- TMAC_TX_BUF_OVRN
 
- TMAC_TX_CRI_ERR
 
- TMAC_TX_SM_ERR
 
- TMC
 
- TMCA
 
- TMCA_ADDR
 
- TMCEN_BIT
 
- TMCEN_SHIFT
 
- TMCL
 
- TMCL_ADDR
 
- TMCONF
 
- TMCR
 
- TMCS
 
- TMCSR_CNT
 
- TMCSR_EN
 
- TMCSR_SWIT
 
- TMCT
 
- TMCTL_TE
 
- TMCTL_TMD
 
- TMCTL_TSUSP
 
- TMC_AUTHSTATUS
 
- TMC_AUTH_NSID_MASK
 
- TMC_AXICTL
 
- TMC_AXICTL_ARCACHE_MASK
 
- TMC_AXICTL_ARCACHE_OS
 
- TMC_AXICTL_AXCACHE_OS
 
- TMC_AXICTL_CLEAR_MASK
 
- TMC_AXICTL_PROT_CTL_B0
 
- TMC_AXICTL_PROT_CTL_B1
 
- TMC_AXICTL_SCT_GAT_MODE
 
- TMC_AXICTL_WR_BURST_16
 
- TMC_BUFWM
 
- TMC_CBUFLEVEL
 
- TMC_CONFIG_TYPE_ETB
 
- TMC_CONFIG_TYPE_ETF
 
- TMC_CONFIG_TYPE_ETR
 
- TMC_CTL
 
- TMC_CTL_CAPT_EN
 
- TMC_DBAHI
 
- TMC_DBALO
 
- TMC_DEVID_AXIAW_MASK
 
- TMC_DEVID_AXIAW_SHIFT
 
- TMC_DEVID_AXIAW_VALID
 
- TMC_DEVID_NOSCAT
 
- TMC_ETR_AXI_ARCACHE
 
- TMC_ETR_PERF_MIN_BUF_SIZE
 
- TMC_ETR_SAVE_RESTORE
 
- TMC_ETR_SG
 
- TMC_FFCR
 
- TMC_FFCR_EN_FMT
 
- TMC_FFCR_EN_TI
 
- TMC_FFCR_FLUSHMAN_BIT
 
- TMC_FFCR_FON_FLIN
 
- TMC_FFCR_FON_TRIG_EVT
 
- TMC_FFCR_STOP_ON_FLUSH
 
- TMC_FFCR_TRIGON_TRIGIN
 
- TMC_FFSR
 
- TMC_ITATBCTR0
 
- TMC_ITATBCTR1
 
- TMC_ITATBCTR2
 
- TMC_ITATBDATA0
 
- TMC_ITMISCOP0
 
- TMC_ITTRFLIN
 
- TMC_LBUFLEVEL
 
- TMC_MEM_INTF_WIDTH_128BITS
 
- TMC_MEM_INTF_WIDTH_256BITS
 
- TMC_MEM_INTF_WIDTH_32BITS
 
- TMC_MEM_INTF_WIDTH_64BITS
 
- TMC_MODE
 
- TMC_MODE_CIRCULAR_BUFFER
 
- TMC_MODE_HARDWARE_FIFO
 
- TMC_MODE_SOFTWARE_FIFO
 
- TMC_PSCR
 
- TMC_REG_PAIR
 
- TMC_RRD
 
- TMC_RRP
 
- TMC_RRPHI
 
- TMC_RSZ
 
- TMC_RWD
 
- TMC_RWP
 
- TMC_RWPHI
 
- TMC_STS
 
- TMC_STS_FULL
 
- TMC_STS_MEMERR
 
- TMC_STS_TMCREADY_BIT
 
- TMC_STS_TRIGGERED
 
- TMC_TRG
 
- TMD1_DEF
 
- TMD1_ENP
 
- TMD1_ERR
 
- TMD1_MORE
 
- TMD1_ONE
 
- TMD1_OWN
 
- TMD1_OWN_CHIP
 
- TMD1_OWN_HOST
 
- TMD1_STP
 
- TMD3_BUFF
 
- TMD3_LCAR
 
- TMD3_LCOL
 
- TMD3_RTRY
 
- TMD3_TDR
 
- TMD3_UFLO
 
- TMDA
 
- TMDC_ABS
 
- TMDC_ABS_HAT
 
- TMDC_BTN
 
- TMDC_BYTE_DEF
 
- TMDC_BYTE_ID
 
- TMDC_BYTE_REV
 
- TMDC_MAX_LENGTH
 
- TMDC_MAX_START
 
- TMDC_MAX_STROBE
 
- TMDC_MODE_3DRP
 
- TMDC_MODE_AT
 
- TMDC_MODE_FGP
 
- TMDC_MODE_FM
 
- TMDC_MODE_M3DI
 
- TMDMAE
 
- TMDNUM
 
- TMDNUMMASK
 
- TMDR
 
- TMDR1
 
- TMDR1_PCON
 
- TMDR1_SYNCCH_MASK
 
- TMDR1_SYNCCH_SHIFT
 
- TMDR2
 
- TMDR3
 
- TMDR_BFA
 
- TMDR_BFB
 
- TMDR_BFE
 
- TMDR_MD_MASK
 
- TMDR_MD_NORMAL
 
- TMDR_MD_PHASE_1
 
- TMDR_MD_PHASE_2
 
- TMDR_MD_PHASE_3
 
- TMDR_MD_PHASE_4
 
- TMDR_MD_PWM_1
 
- TMDR_MD_PWM_2
 
- TMDR_MD_PWM_COMP_BOTH
 
- TMDR_MD_PWM_COMP_CREST
 
- TMDR_MD_PWM_COMP_TROUGH
 
- TMDR_MD_PWM_SYNC
 
- TMDS
 
- TMDS1EncoderControl
 
- TMDS1XEncoderControl
 
- TMDS1_ENCODER_CONTROL_PARAMETERS
 
- TMDS1_ENCODER_CONTROL_PARAMETERS_LAST
 
- TMDS1_ENCODER_CONTROL_PARAMETERS_V2
 
- TMDS1_ENCODER_CONTROL_PARAMETERS_V3
 
- TMDS1_ENCODER_CONTROL_PS_ALLOCATION
 
- TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST
 
- TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2
 
- TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3
 
- TMDS2EncoderControl
 
- TMDS2_ENCODER_CONTROL_PARAMETERS
 
- TMDS2_ENCODER_CONTROL_PARAMETERS_LAST
 
- TMDS2_ENCODER_CONTROL_PARAMETERS_V2
 
- TMDS2_ENCODER_CONTROL_PARAMETERS_V3
 
- TMDS2_ENCODER_CONTROL_PS_ALLOCATION
 
- TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST
 
- TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2
 
- TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3
 
- TMDSAEncoderControl
 
- TMDSA_CNTL
 
- TMDSA_HDMI_EN
 
- TMDS_296M
 
- TMDS_297M
 
- TMDS_370M
 
- TMDS_371M
 
- TMDS_445M
 
- TMDS_445_5M
 
- TMDS_593M
 
- TMDS_594M
 
- TMDS_CNTL
 
- TMDS_CNTL__TMDS_COLOR_FORMAT_MASK
 
- TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT
 
- TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK
 
- TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT
 
- TMDS_CNTL__TMDS_SYNC_PHASE_MASK
 
- TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT
 
- TMDS_COLOR_FORMAT
 
- TMDS_COLOR_FORMAT_DUAL30BPP
 
- TMDS_COLOR_FORMAT_RESERVED
 
- TMDS_COLOR_FORMAT_TWIN30BPP_LSB
 
- TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP
 
- TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK
 
- TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT
 
- TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK
 
- TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT
 
- TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK
 
- TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT
 
- TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK
 
- TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT
 
- TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK
 
- TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT
 
- TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK
 
- TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT
 
- TMDS_CRC
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK
 
- TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT
 
- TMDS_CTL0_DATA_DELAY
 
- TMDS_CTL0_DATA_DELAY_0PIX
 
- TMDS_CTL0_DATA_DELAY_1PIX
 
- TMDS_CTL0_DATA_DELAY_2PIX
 
- TMDS_CTL0_DATA_DELAY_3PIX
 
- TMDS_CTL0_DATA_DELAY_4PIX
 
- TMDS_CTL0_DATA_DELAY_5PIX
 
- TMDS_CTL0_DATA_DELAY_6PIX
 
- TMDS_CTL0_DATA_DELAY_7PIX
 
- TMDS_CTL0_DATA_INVERT
 
- TMDS_CTL0_DATA_INVERT_EN
 
- TMDS_CTL0_DATA_MODULATION
 
- TMDS_CTL0_DATA_MODULATION_BIT0
 
- TMDS_CTL0_DATA_MODULATION_BIT1
 
- TMDS_CTL0_DATA_MODULATION_BIT2
 
- TMDS_CTL0_DATA_MODULATION_DISABLE
 
- TMDS_CTL0_DATA_NORMAL
 
- TMDS_CTL0_DATA_SEL
 
- TMDS_CTL0_DATA_SEL0_RESERVED
 
- TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE
 
- TMDS_CTL0_DATA_SEL2_VSYNC
 
- TMDS_CTL0_DATA_SEL3_RESERVED
 
- TMDS_CTL0_DATA_SEL4_HSYNC
 
- TMDS_CTL0_DATA_SEL5_SEL7_RESERVED
 
- TMDS_CTL0_DATA_SEL8_RANDOM_DATA
 
- TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA
 
- TMDS_CTL0_PATTERN_OUT_DISABLE
 
- TMDS_CTL0_PATTERN_OUT_EN
 
- TMDS_CTL0_PATTERN_OUT_ENABLE
 
- TMDS_CTL1_DATA_DELAY
 
- TMDS_CTL1_DATA_DELAY_0PIX
 
- TMDS_CTL1_DATA_DELAY_1PIX
 
- TMDS_CTL1_DATA_DELAY_2PIX
 
- TMDS_CTL1_DATA_DELAY_3PIX
 
- TMDS_CTL1_DATA_DELAY_4PIX
 
- TMDS_CTL1_DATA_DELAY_5PIX
 
- TMDS_CTL1_DATA_DELAY_6PIX
 
- TMDS_CTL1_DATA_DELAY_7PIX
 
- TMDS_CTL1_DATA_INVERT
 
- TMDS_CTL1_DATA_INVERT_EN
 
- TMDS_CTL1_DATA_MODULATION
 
- TMDS_CTL1_DATA_MODULATION_BIT0
 
- TMDS_CTL1_DATA_MODULATION_BIT1
 
- TMDS_CTL1_DATA_MODULATION_BIT2
 
- TMDS_CTL1_DATA_MODULATION_DISABLE
 
- TMDS_CTL1_DATA_NORMAL
 
- TMDS_CTL1_DATA_SEL
 
- TMDS_CTL1_DATA_SEL0_RESERVED
 
- TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE
 
- TMDS_CTL1_DATA_SEL2_VSYNC
 
- TMDS_CTL1_DATA_SEL3_RESERVED
 
- TMDS_CTL1_DATA_SEL4_HSYNC
 
- TMDS_CTL1_DATA_SEL5_SEL7_RESERVED
 
- TMDS_CTL1_DATA_SEL8_BLANK_TIME
 
- TMDS_CTL1_DATA_SEL9_SEL15_RESERVED
 
- TMDS_CTL1_PATTERN_OUT_DISABLE
 
- TMDS_CTL1_PATTERN_OUT_EN
 
- TMDS_CTL1_PATTERN_OUT_ENABLE
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK
 
- TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT
 
- TMDS_CTL2_DATA_DELAY
 
- TMDS_CTL2_DATA_DELAY_0PIX
 
- TMDS_CTL2_DATA_DELAY_1PIX
 
- TMDS_CTL2_DATA_DELAY_2PIX
 
- TMDS_CTL2_DATA_DELAY_3PIX
 
- TMDS_CTL2_DATA_DELAY_4PIX
 
- TMDS_CTL2_DATA_DELAY_5PIX
 
- TMDS_CTL2_DATA_DELAY_6PIX
 
- TMDS_CTL2_DATA_DELAY_7PIX
 
- TMDS_CTL2_DATA_INVERT
 
- TMDS_CTL2_DATA_INVERT_EN
 
- TMDS_CTL2_DATA_MODULATION
 
- TMDS_CTL2_DATA_MODULATION_BIT0
 
- TMDS_CTL2_DATA_MODULATION_BIT1
 
- TMDS_CTL2_DATA_MODULATION_BIT2
 
- TMDS_CTL2_DATA_MODULATION_DISABLE
 
- TMDS_CTL2_DATA_NORMAL
 
- TMDS_CTL2_DATA_SEL
 
- TMDS_CTL2_DATA_SEL0_RESERVED
 
- TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE
 
- TMDS_CTL2_DATA_SEL2_VSYNC
 
- TMDS_CTL2_DATA_SEL3_RESERVED
 
- TMDS_CTL2_DATA_SEL4_HSYNC
 
- TMDS_CTL2_DATA_SEL5_SEL7_RESERVED
 
- TMDS_CTL2_DATA_SEL8_BLANK_TIME
 
- TMDS_CTL2_DATA_SEL9_SEL15_RESERVED
 
- TMDS_CTL2_PATTERN_OUT_DISABLE
 
- TMDS_CTL2_PATTERN_OUT_EN
 
- TMDS_CTL2_PATTERN_OUT_ENABLE
 
- TMDS_CTL3_DATA_DELAY
 
- TMDS_CTL3_DATA_DELAY_0PIX
 
- TMDS_CTL3_DATA_DELAY_1PIX
 
- TMDS_CTL3_DATA_DELAY_2PIX
 
- TMDS_CTL3_DATA_DELAY_3PIX
 
- TMDS_CTL3_DATA_DELAY_4PIX
 
- TMDS_CTL3_DATA_DELAY_5PIX
 
- TMDS_CTL3_DATA_DELAY_6PIX
 
- TMDS_CTL3_DATA_DELAY_7PIX
 
- TMDS_CTL3_DATA_INVERT
 
- TMDS_CTL3_DATA_INVERT_EN
 
- TMDS_CTL3_DATA_MODULATION
 
- TMDS_CTL3_DATA_MODULATION_BIT0
 
- TMDS_CTL3_DATA_MODULATION_BIT1
 
- TMDS_CTL3_DATA_MODULATION_BIT2
 
- TMDS_CTL3_DATA_MODULATION_DISABLE
 
- TMDS_CTL3_DATA_NORMAL
 
- TMDS_CTL3_DATA_SEL
 
- TMDS_CTL3_DATA_SEL0_RESERVED
 
- TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE
 
- TMDS_CTL3_DATA_SEL2_VSYNC
 
- TMDS_CTL3_DATA_SEL3_RESERVED
 
- TMDS_CTL3_DATA_SEL4_HSYNC
 
- TMDS_CTL3_DATA_SEL5_SEL7_RESERVED
 
- TMDS_CTL3_DATA_SEL8_BLANK_TIME
 
- TMDS_CTL3_DATA_SEL9_SEL15_RESERVED
 
- TMDS_CTL3_PATTERN_OUT_DISABLE
 
- TMDS_CTL3_PATTERN_OUT_EN
 
- TMDS_CTL3_PATTERN_OUT_ENABLE
 
- TMDS_CTL_BITS__TMDS_CTL0_MASK
 
- TMDS_CTL_BITS__TMDS_CTL0__SHIFT
 
- TMDS_CTL_BITS__TMDS_CTL1_MASK
 
- TMDS_CTL_BITS__TMDS_CTL1__SHIFT
 
- TMDS_CTL_BITS__TMDS_CTL2_MASK
 
- TMDS_CTL_BITS__TMDS_CTL2__SHIFT
 
- TMDS_CTL_BITS__TMDS_CTL3_MASK
 
- TMDS_CTL_BITS__TMDS_CTL3__SHIFT
 
- TMDS_DATA_SYNCHRONIZATION_DSINTSEL
 
- TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS
 
- TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL
 
- TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK
 
- TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT
 
- TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK
 
- TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT
 
- TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK
 
- TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT
 
- TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK
 
- TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT
 
- TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK
 
- TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT
 
- TMDS_DEBUG10__DBG_DIG_TMDS10_MASK
 
- TMDS_DEBUG10__DBG_DIG_TMDS10__SHIFT
 
- TMDS_DEBUG11__DBG_DIG_TMDS11_MASK
 
- TMDS_DEBUG11__DBG_DIG_TMDS11__SHIFT
 
- TMDS_DEBUG12__DBG_LVDS_DEBUG1_MASK
 
- TMDS_DEBUG12__DBG_LVDS_DEBUG1__SHIFT
 
- TMDS_DEBUG13__DBG_LVDS_DEBUG2_MASK
 
- TMDS_DEBUG13__DBG_LVDS_DEBUG2__SHIFT
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_DE_MASK
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_DE__SHIFT
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_IN_MASK
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_IN__SHIFT
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_OUT_MASK
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_COLOR_OUT__SHIFT
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL0_OUT_MASK
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL0_OUT__SHIFT
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL1_OUT_MASK
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL1_OUT__SHIFT
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL2_OUT_MASK
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL2_OUT__SHIFT
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL3_OUT_MASK
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_CTL3_OUT__SHIFT
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_DE_IN_MASK
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_DE_IN__SHIFT
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_HSYNC_IN_MASK
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_HSYNC_IN__SHIFT
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_HSYNC_OUT_MASK
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_HSYNC_OUT__SHIFT
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_PLCTL0_IN_MASK
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_PLCTL0_IN__SHIFT
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_PLDEVS_OUT_MASK
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_PLDEVS_OUT__SHIFT
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_STEREOSYNC_IN_MASK
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_STEREOSYNC_IN__SHIFT
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_VSYNC_IN_MASK
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_VSYNC_IN__SHIFT
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_VSYNC_OUT_MASK
 
- TMDS_DEBUG1__DBG_DIG_TMDS_DATACP_VSYNC_OUT__SHIFT
 
- TMDS_DEBUG1__DBG_DIG_TMDS_PIXCLK_MASK
 
- TMDS_DEBUG1__DBG_DIG_TMDS_PIXCLK__SHIFT
 
- TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_CHAR_A_IN_MASK
 
- TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_CHAR_A_IN__SHIFT
 
- TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_CHAR_B_IN_MASK
 
- TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_CHAR_B_IN__SHIFT
 
- TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_DCB_MASK
 
- TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_DCB__SHIFT
 
- TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_DE_IN_MASK
 
- TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_DE_IN__SHIFT
 
- TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_IN_MASK
 
- TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_IN__SHIFT
 
- TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_TX_MASK
 
- TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_COLOR_TX__SHIFT
 
- TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_DE_TX_MASK
 
- TMDS_DEBUG2__DBG_DIG_TMDS_ENCODER_DE_TX__SHIFT
 
- TMDS_DEBUG2__DBG_DIG_TMDS_PIXCLK_MASK
 
- TMDS_DEBUG2__DBG_DIG_TMDS_PIXCLK__SHIFT
 
- TMDS_DEBUG3__DBG_DIG_TMDS_PIXCLK_MASK
 
- TMDS_DEBUG3__DBG_DIG_TMDS_PIXCLK__SHIFT
 
- TMDS_DEBUG3__DBG_DIG_TMDS_TX_COLOR_DE_IN_MASK
 
- TMDS_DEBUG3__DBG_DIG_TMDS_TX_COLOR_DE_IN__SHIFT
 
- TMDS_DEBUG3__DBG_DIG_TMDS_TX_COLOR_IN_MASK
 
- TMDS_DEBUG3__DBG_DIG_TMDS_TX_COLOR_IN__SHIFT
 
- TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL0_IN_MASK
 
- TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL0_IN__SHIFT
 
- TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL1_IN_MASK
 
- TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL1_IN__SHIFT
 
- TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL2_IN_MASK
 
- TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL2_IN__SHIFT
 
- TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL3_IN_MASK
 
- TMDS_DEBUG3__DBG_DIG_TMDS_TX_CTL3_IN__SHIFT
 
- TMDS_DEBUG3__DBG_DIG_TMDS_TX_HSYNC_IN_MASK
 
- TMDS_DEBUG3__DBG_DIG_TMDS_TX_HSYNC_IN__SHIFT
 
- TMDS_DEBUG3__DBG_DIG_TMDS_TX_PLPIXA_OUT_MASK
 
- TMDS_DEBUG3__DBG_DIG_TMDS_TX_PLPIXA_OUT__SHIFT
 
- TMDS_DEBUG3__DBG_DIG_TMDS_TX_VSYNC_IN_MASK
 
- TMDS_DEBUG3__DBG_DIG_TMDS_TX_VSYNC_IN__SHIFT
 
- TMDS_DEBUG7__DBG_DIG_TMDS7_MASK
 
- TMDS_DEBUG7__DBG_DIG_TMDS7__SHIFT
 
- TMDS_DEBUG8__DBG_DIG_TMDS8_MASK
 
- TMDS_DEBUG8__DBG_DIG_TMDS8__SHIFT
 
- TMDS_DEBUG9__DBG_DIG_TMDS9_MASK
 
- TMDS_DEBUG9__DBG_DIG_TMDS9__SHIFT
 
- TMDS_DEBUG__TMDS_DEBUG_DE_EN_MASK
 
- TMDS_DEBUG__TMDS_DEBUG_DE_EN__SHIFT
 
- TMDS_DEBUG__TMDS_DEBUG_DE_MASK
 
- TMDS_DEBUG__TMDS_DEBUG_DE__SHIFT
 
- TMDS_DEBUG__TMDS_DEBUG_EN_MASK
 
- TMDS_DEBUG__TMDS_DEBUG_EN__SHIFT
 
- TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN_MASK
 
- TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN__SHIFT
 
- TMDS_DEBUG__TMDS_DEBUG_HSYNC_MASK
 
- TMDS_DEBUG__TMDS_DEBUG_HSYNC__SHIFT
 
- TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN_MASK
 
- TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN__SHIFT
 
- TMDS_DEBUG__TMDS_DEBUG_VSYNC_MASK
 
- TMDS_DEBUG__TMDS_DEBUG_VSYNC__SHIFT
 
- TMDS_DVO_MUX_SELECT
 
- TMDS_DVO_MUX_SELECT_B
 
- TMDS_DVO_MUX_SELECT_G
 
- TMDS_DVO_MUX_SELECT_R
 
- TMDS_DVO_MUX_SELECT_RESERVED
 
- TMDS_ICHCSEL
 
- TMDS_Info
 
- TMDS_MAX_PIXEL_CLOCK
 
- TMDS_MIN_PIXEL_CLOCK
 
- TMDS_MUX_SELECT
 
- TMDS_MUX_SELECT_B
 
- TMDS_MUX_SELECT_G
 
- TMDS_MUX_SELECT_R
 
- TMDS_MUX_SELECT_RESERVED
 
- TMDS_NOT_SYNC_PHASE_ON_FRAME_START
 
- TMDS_PIXEL_ENCODING
 
- TMDS_PIXEL_ENCODING_422
 
- TMDS_PIXEL_ENCODING_444
 
- TMDS_PIXEL_ENCODING_444_OR_420
 
- TMDS_PLLRST
 
- TMDS_PLL_EN
 
- TMDS_RAN_PAT_RST
 
- TMDS_REG_TEST_OUTPUTA_CNTLA
 
- TMDS_REG_TEST_OUTPUTA_CNTLA_NA
 
- TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0
 
- TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1
 
- TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2
 
- TMDS_REG_TEST_OUTPUTB_CNTLB
 
- TMDS_REG_TEST_OUTPUTB_CNTLB_NA
 
- TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0
 
- TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1
 
- TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2
 
- TMDS_STEREOSYNC_CTL0
 
- TMDS_STEREOSYNC_CTL1
 
- TMDS_STEREOSYNC_CTL2
 
- TMDS_STEREOSYNC_CTL3
 
- TMDS_STEREOSYNC_CTL_SEL_REG
 
- TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK
 
- TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT
 
- TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK
 
- TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT
 
- TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK
 
- TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT
 
- TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK
 
- TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT
 
- TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK
 
- TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT
 
- TMDS_SYNC_PHASE
 
- TMDS_SYNC_PHASE_ON_FRAME_START
 
- TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT
 
- TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT
 
- TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT
 
- TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT
 
- TMDS_TRANSMITTER_CNTL
 
- TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA
 
- TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB
 
- TMDS_TRANSMITTER_CONTROL_IDSCKSELA
 
- TMDS_TRANSMITTER_CONTROL_IDSCKSELB
 
- TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN
 
- TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK
 
- TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN
 
- TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK
 
- TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS
 
- TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS
 
- TMDS_TRANSMITTER_ENABLE_HPD_MASK
 
- TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK
 
- TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK
 
- TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE
 
- TMDS_TRANSMITTER_HPD_MASK_OVERRIDE
 
- TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE
 
- TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE
 
- TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON
 
- TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON
 
- TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK
 
- TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK
 
- TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK
 
- TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK
 
- TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE
 
- TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE
 
- TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE
 
- TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE
 
- TMDS_TRANSMITTER_PLLSEL_BY_HW
 
- TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW
 
- TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD
 
- TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE
 
- TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE
 
- TMDS_TRANSMITTER_PLL_RST_ON_HPD
 
- TMDS_TRANSMITTER_TDCLK_FROM_PADS
 
- TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK
 
- TMDS_TRANSMITTER_TMCLK_FROM_PADS
 
- TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK
 
- TMD_ENP
 
- TMD_ERR
 
- TMD_MORE
 
- TMD_OWN
 
- TMD_PANEL_HEIGHT
 
- TMD_PANEL_WIDTH
 
- TMD_RESET_TIME
 
- TMD_STP
 
- TMD_VID
 
- TMEDCR
 
- TMEDRGBR
 
- TMEMSIZE
 
- TMEMSIZEREG
 
- TMEM_SPEC_VERSION
 
- TME_ACTIVATE_CRYPTO_AES_XTS_128
 
- TME_ACTIVATE_CRYPTO_ALGS
 
- TME_ACTIVATE_ENABLED
 
- TME_ACTIVATE_KEYID_BITS
 
- TME_ACTIVATE_LOCKED
 
- TME_ACTIVATE_POLICY
 
- TME_ACTIVATE_POLICY_AES_XTS_128
 
- TMF_ABORT_TASK
 
- TMF_ABORT_TASK_SET
 
- TMF_CLEAR_ACA
 
- TMF_CLEAR_TASK_SET
 
- TMF_DSD_LIST_ENABLE
 
- TMF_FAILED
 
- TMF_INITIAL
 
- TMF_I_T_NEXUS_RESET
 
- TMF_LOGICAL_UNIT_RESET
 
- TMF_LUN_RESET
 
- TMF_LU_RESET
 
- TMF_NOT_FOUND
 
- TMF_QUERY_ASYNC_EVENT
 
- TMF_QUERY_TASK
 
- TMF_QUERY_TASK_SET
 
- TMF_QUEUED
 
- TMF_READ_DATA
 
- TMF_RESP_FUNC_COMPLETE
 
- TMF_RESP_FUNC_ESUPP
 
- TMF_RESP_FUNC_FAILED
 
- TMF_RESP_FUNC_SUCC
 
- TMF_RESP_INVALID_FRAME
 
- TMF_RESP_NO_LUN
 
- TMF_RESP_OVERLAPPED_TAG
 
- TMF_SUCCESS
 
- TMF_TARGET_RESET
 
- TMF_TIMEDOUT
 
- TMF_WRITE_DATA
 
- TMGCFG
 
- TMGCFG2
 
- TMGLOCK0
 
- TMGLOCK1
 
- TMGLOCK_QUALITY
 
- TMGOBS
 
- TMGREG0
 
- TMGREG1
 
- TMGREG2
 
- TMGTHFALL
 
- TMGTHRISE
 
- TMHW_LEV_ADJ_ADCLEV_DEFAULT
 
- TMHW_LEV_ADJ_DECLEV_DEFAULT
 
- TMHW_LEV_ADJ_MONOLEV_DEFAULT
 
- TMHW_LEV_ADJ_NICLEV_DEFAULT
 
- TMHW_LEV_ADJ_SAPLEV_DEFAULT
 
- TMICMODE
 
- TMICTX
 
- TMIN
 
- TMIN_MASK
 
- TMIN_SHIFT
 
- TMIOFB_ACC_CHPIX
 
- TMIOFB_ACC_CMGO
 
- TMIOFB_ACC_CMGO_CDHRV
 
- TMIOFB_ACC_CMGO_CDVRV
 
- TMIOFB_ACC_CMGO_CEND
 
- TMIOFB_ACC_CMGO_CMOD
 
- TMIOFB_ACC_CMGO_INT
 
- TMIOFB_ACC_CMGO_RUND
 
- TMIOFB_ACC_CSADR
 
- TMIOFB_ACC_CVPIX
 
- TMIOFB_ACC_DHPIX
 
- TMIOFB_ACC_DSADR
 
- TMIOFB_ACC_DVPIX
 
- TMIOFB_ACC_FILL
 
- TMIOFB_ACC_FLGO
 
- TMIOFB_ACC_FLGO_CEND
 
- TMIOFB_ACC_FLGO_INT
 
- TMIOFB_ACC_FLGO_ROP3
 
- TMIOFB_ACC_LBINI
 
- TMIOFB_ACC_LBK2
 
- TMIOFB_ACC_LDGO
 
- TMIOFB_ACC_LDGO_CEND
 
- TMIOFB_ACC_LDGO_ENDPX
 
- TMIOFB_ACC_LDGO_INT
 
- TMIOFB_ACC_LDGO_LDMOD
 
- TMIOFB_ACC_LDGO_LHRV
 
- TMIOFB_ACC_LDGO_LVRV
 
- TMIOFB_ACC_LDGO_ROP3
 
- TMIOFB_ACC_PHOFS
 
- TMIOFB_ACC_PHPIX
 
- TMIOFB_ACC_POADR
 
- TMIOFB_ACC_PSADR
 
- TMIOFB_ACC_PVOFS
 
- TMIOFB_ACC_PVPIX
 
- TMIOFB_ACC_RSTR
 
- TMIOFB_ACC_SBGO
 
- TMIOFB_ACC_SBGO_CEND
 
- TMIOFB_ACC_SBGO_DHRV
 
- TMIOFB_ACC_SBGO_DVRV
 
- TMIOFB_ACC_SBGO_INT
 
- TMIOFB_ACC_SBGO_SBMD
 
- TMIOFB_ACC_SBGO_SHRV
 
- TMIOFB_ACC_SBGO_SVRV
 
- TMIOFB_ACC_SCGO
 
- TMIOFB_ACC_SCGO_CEND
 
- TMIOFB_ACC_SCGO_DHRV
 
- TMIOFB_ACC_SCGO_DSTXY
 
- TMIOFB_ACC_SCGO_DVRV
 
- TMIOFB_ACC_SCGO_INT
 
- TMIOFB_ACC_SCGO_ROP3
 
- TMIOFB_ACC_SCGO_SHRV
 
- TMIOFB_ACC_SCGO_SVRV
 
- TMIOFB_ACC_SCGO_TRNS
 
- TMIOFB_ACC_SHBINI
 
- TMIOFB_ACC_SHBK2
 
- TMIOFB_ACC_SHPIX
 
- TMIOFB_ACC_SSADR
 
- TMIOFB_ACC_SVBINI
 
- TMIOFB_ACC_SVBK2
 
- TMIOFB_ACC_SVPIX
 
- TMIOFB_ACC_TCLOR
 
- TMIOFB_FIFO_SIZE
 
- TMIO_IRQ_BASE
 
- TMIO_MASK_ALL
 
- TMIO_MASK_CMD
 
- TMIO_MASK_INIT_RCAR2
 
- TMIO_MASK_IRQ
 
- TMIO_MASK_READOP
 
- TMIO_MASK_WRITEOP
 
- TMIO_MAX_BLK_SIZE
 
- TMIO_MMC_32BIT_DATA_PORT
 
- TMIO_MMC_BLKSZ_2BYTES
 
- TMIO_MMC_CLK_ACTUAL
 
- TMIO_MMC_H
 
- TMIO_MMC_HAS_IDLE_WAIT
 
- TMIO_MMC_HAVE_4TAP_HS400
 
- TMIO_MMC_HAVE_CBSY
 
- TMIO_MMC_HAVE_CMD12_CTRL
 
- TMIO_MMC_MIN_DMA_LEN
 
- TMIO_MMC_MIN_RCAR2
 
- TMIO_MMC_SDIO_IRQ
 
- TMIO_MMC_SDIO_STATUS_SETBITS
 
- TMIO_OHCI_DRIVER
 
- TMIO_SDIO_MASK_ALL
 
- TMIO_SDIO_SETBITS_MASK
 
- TMIO_SDIO_STAT_EXPUB52
 
- TMIO_SDIO_STAT_EXWT
 
- TMIO_SDIO_STAT_IOIRQ
 
- TMIO_SD_IRQ
 
- TMIO_STAT_ALWAYS_SET_27
 
- TMIO_STAT_CARD_INSERT
 
- TMIO_STAT_CARD_INSERT_A
 
- TMIO_STAT_CARD_REMOVE
 
- TMIO_STAT_CARD_REMOVE_A
 
- TMIO_STAT_CMDRESPEND
 
- TMIO_STAT_CMDTIMEOUT
 
- TMIO_STAT_CMD_BUSY
 
- TMIO_STAT_CMD_IDX_ERR
 
- TMIO_STAT_CRCFAIL
 
- TMIO_STAT_DAT0
 
- TMIO_STAT_DATAEND
 
- TMIO_STAT_DATATIMEOUT
 
- TMIO_STAT_ILL_ACCESS
 
- TMIO_STAT_ILL_FUNC
 
- TMIO_STAT_RXOVERFLOW
 
- TMIO_STAT_RXRDY
 
- TMIO_STAT_SCLKDIVEN
 
- TMIO_STAT_SIGSTATE
 
- TMIO_STAT_SIGSTATE_A
 
- TMIO_STAT_STOPBIT_ERR
 
- TMIO_STAT_TXRQ
 
- TMIO_STAT_TXUNDERRUN
 
- TMIO_STAT_WRPROTECT
 
- TMIO_STOP_SEC
 
- TMIO_STOP_STP
 
- TMIO_USB_IRQ
 
- TMLD_REG_DBG_DWORD_ENABLE
 
- TMLD_REG_DBG_FORCE_FRAME
 
- TMLD_REG_DBG_FORCE_VALID
 
- TMLD_REG_DBG_SELECT
 
- TMLD_REG_DBG_SHIFT
 
- TMLD_REG_SCBD_STRICT_PRIO
 
- TML_USB_SERIAL_PID
 
- TML_VID
 
- TMOD
 
- TMODCOEF
 
- TMODE
 
- TMODE_RRQ
 
- TMODE_WAQ0
 
- TMODE_WAQ2
 
- TMODE_WSQ
 
- TMODSETUP0_EN
 
- TMODSETUP0_VAL
 
- TMODSETUP1_EN
 
- TMODSETUP1_VAL
 
- TMOD_WIDTH
 
- TMON0_CONFIG__FORCE_MAX_ACQ_MASK
 
- TMON0_CONFIG__FORCE_MAX_ACQ__SHIFT
 
- TMON0_CONFIG__NUM_ACQ_MASK
 
- TMON0_CONFIG__NUM_ACQ__SHIFT
 
- TMON0_CONFIG__RDI_INTERLEAVE_MASK
 
- TMON0_CONFIG__RDI_INTERLEAVE__SHIFT
 
- TMON0_CONFIG__RE_CALIB_EN_MASK
 
- TMON0_CONFIG__RE_CALIB_EN__SHIFT
 
- TMON0_DEBUG0__DEBUG_Z_EN_MASK
 
- TMON0_DEBUG0__DEBUG_Z_EN__SHIFT
 
- TMON0_DEBUG0__DEBUG_Z_MASK
 
- TMON0_DEBUG0__DEBUG_Z__SHIFT
 
- TMON0_DEBUG1__DEBUG_RDI_MASK
 
- TMON0_DEBUG1__DEBUG_RDI__SHIFT
 
- TMON0_INT_DATA__TEMP_Z_DATA_MASK
 
- TMON0_INT_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIL0_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIL0_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIL10_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIL10_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIL11_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIL11_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIL12_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIL12_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIL13_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIL13_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIL14_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIL14_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIL15_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIL15_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIL1_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIL1_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIL2_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIL2_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIL3_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIL3_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIL4_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIL4_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIL5_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIL5_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIL6_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIL6_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIL7_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIL7_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIL8_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIL8_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIL9_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIL9_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIL_PRESENT0__RDIL_PRESENT_7_0_MASK
 
- TMON0_RDIL_PRESENT0__RDIL_PRESENT_7_0__SHIFT
 
- TMON0_RDIL_PRESENT1__RDIL_PRESENT_15_8_MASK
 
- TMON0_RDIL_PRESENT1__RDIL_PRESENT_15_8__SHIFT
 
- TMON0_RDIR0_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIR0_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIR10_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIR10_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIR11_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIR11_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIR12_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIR12_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIR13_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIR13_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIR14_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIR14_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIR15_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIR15_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIR1_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIR1_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIR2_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIR2_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIR3_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIR3_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIR4_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIR4_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIR5_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIR5_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIR6_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIR6_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIR7_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIR7_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIR8_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIR8_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIR9_DATA__TEMP_Z_DATA_MASK
 
- TMON0_RDIR9_DATA__TEMP_Z_DATA__SHIFT
 
- TMON0_RDIR_PRESENT0__RDIR_PRESENT_7_0_MASK
 
- TMON0_RDIR_PRESENT0__RDIR_PRESENT_7_0__SHIFT
 
- TMON0_RDIR_PRESENT1__RDIR_PRESENT_15_8_MASK
 
- TMON0_RDIR_PRESENT1__RDIR_PRESENT_15_8__SHIFT
 
- TMON0_TEMP_CALC_COEFF0__Z_MASK
 
- TMON0_TEMP_CALC_COEFF0__Z__SHIFT
 
- TMON0_TEMP_CALC_COEFF1__A_MASK
 
- TMON0_TEMP_CALC_COEFF1__A__SHIFT
 
- TMON0_TEMP_CALC_COEFF2__B_MASK
 
- TMON0_TEMP_CALC_COEFF2__B__SHIFT
 
- TMON0_TEMP_CALC_COEFF3__C_MASK
 
- TMON0_TEMP_CALC_COEFF3__C__SHIFT
 
- TMON0_TEMP_CALC_COEFF4__K_MASK
 
- TMON0_TEMP_CALC_COEFF4__K__SHIFT
 
- TMON1_CONFIG__FORCE_MAX_ACQ_MASK
 
- TMON1_CONFIG__FORCE_MAX_ACQ__SHIFT
 
- TMON1_CONFIG__NUM_ACQ_MASK
 
- TMON1_CONFIG__NUM_ACQ__SHIFT
 
- TMON1_CONFIG__RDI_INTERLEAVE_MASK
 
- TMON1_CONFIG__RDI_INTERLEAVE__SHIFT
 
- TMON1_CONFIG__RE_CALIB_EN_MASK
 
- TMON1_CONFIG__RE_CALIB_EN__SHIFT
 
- TMON1_DEBUG0__DEBUG_Z_EN_MASK
 
- TMON1_DEBUG0__DEBUG_Z_EN__SHIFT
 
- TMON1_DEBUG0__DEBUG_Z_MASK
 
- TMON1_DEBUG0__DEBUG_Z__SHIFT
 
- TMON1_DEBUG1__DEBUG_RDI_MASK
 
- TMON1_DEBUG1__DEBUG_RDI__SHIFT
 
- TMON1_INT_DATA__TEMP_Z_DATA_MASK
 
- TMON1_INT_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIL0_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIL0_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIL10_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIL10_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIL11_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIL11_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIL12_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIL12_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIL13_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIL13_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIL14_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIL14_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIL15_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIL15_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIL1_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIL1_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIL2_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIL2_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIL3_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIL3_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIL4_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIL4_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIL5_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIL5_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIL6_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIL6_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIL7_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIL7_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIL8_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIL8_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIL9_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIL9_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIL_PRESENT0__RDIL_PRESENT_7_0_MASK
 
- TMON1_RDIL_PRESENT0__RDIL_PRESENT_7_0__SHIFT
 
- TMON1_RDIL_PRESENT1__RDIL_PRESENT_15_8_MASK
 
- TMON1_RDIL_PRESENT1__RDIL_PRESENT_15_8__SHIFT
 
- TMON1_RDIR0_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIR0_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIR10_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIR10_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIR11_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIR11_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIR12_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIR12_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIR13_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIR13_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIR14_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIR14_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIR15_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIR15_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIR1_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIR1_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIR2_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIR2_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIR3_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIR3_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIR4_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIR4_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIR5_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIR5_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIR6_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIR6_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIR7_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIR7_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIR8_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIR8_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIR9_DATA__TEMP_Z_DATA_MASK
 
- TMON1_RDIR9_DATA__TEMP_Z_DATA__SHIFT
 
- TMON1_RDIR_PRESENT0__RDIR_PRESENT_7_0_MASK
 
- TMON1_RDIR_PRESENT0__RDIR_PRESENT_7_0__SHIFT
 
- TMON1_RDIR_PRESENT1__RDIR_PRESENT_15_8_MASK
 
- TMON1_RDIR_PRESENT1__RDIR_PRESENT_15_8__SHIFT
 
- TMON1_TEMP_CALC_COEFF0__Z_MASK
 
- TMON1_TEMP_CALC_COEFF0__Z__SHIFT
 
- TMON1_TEMP_CALC_COEFF1__A_MASK
 
- TMON1_TEMP_CALC_COEFF1__A__SHIFT
 
- TMON1_TEMP_CALC_COEFF2__B_MASK
 
- TMON1_TEMP_CALC_COEFF2__B__SHIFT
 
- TMON1_TEMP_CALC_COEFF3__C_MASK
 
- TMON1_TEMP_CALC_COEFF3__C__SHIFT
 
- TMON1_TEMP_CALC_COEFF4__K_MASK
 
- TMON1_TEMP_CALC_COEFF4__K__SHIFT
 
- TMON_CLK_SEL
 
- TMON_CLK_SEL_MASK
 
- TMON_H
 
- TMON_LOG_FILE
 
- TMON_TRIP_TYPE_HIGH
 
- TMON_TRIP_TYPE_LOW
 
- TMON_TRIP_TYPE_MAX
 
- TMON_TRIP_TYPE_RESET
 
- TMOUTEN
 
- TMOUT_ABORT
 
- TMOUT_FLUSH
 
- TMOUT_GETSTATUS
 
- TMOUT_INDX
 
- TMOUT_INITOUTBOUND
 
- TMOUT_INQUIRY
 
- TMOUT_IOPRESET
 
- TMOUT_LCT
 
- TMOUT_RANGE
 
- TMOUT_SCSI
 
- TMO_E1
 
- TMO_E2
 
- TMO_E3
 
- TMO_E4
 
- TMP006_CONFIG
 
- TMP006_CONFIG_CR_MASK
 
- TMP006_CONFIG_CR_SHIFT
 
- TMP006_CONFIG_DRDY
 
- TMP006_CONFIG_DRDY_EN
 
- TMP006_CONFIG_MOD_MASK
 
- TMP006_CONFIG_RESET
 
- TMP006_DEVICE_ID
 
- TMP006_DEVICE_MAGIC
 
- TMP006_MANUFACTURER_ID
 
- TMP006_MANUFACTURER_MAGIC
 
- TMP006_TAMBIENT
 
- TMP006_TAMBIENT_SHIFT
 
- TMP006_VOBJECT
 
- TMP007_CONFIG
 
- TMP007_CONFIG_ALERT_EN
 
- TMP007_CONFIG_CONV_EN
 
- TMP007_CONFIG_CR_MASK
 
- TMP007_CONFIG_CR_SHIFT
 
- TMP007_CONFIG_TC_EN
 
- TMP007_DEVICE_ID
 
- TMP007_DEVICE_MAGIC
 
- TMP007_MANUFACTURER_ID
 
- TMP007_MANUFACTURER_MAGIC
 
- TMP007_STATUS
 
- TMP007_STATUS_ALERT
 
- TMP007_STATUS_CONV_READY
 
- TMP007_STATUS_DATA_VALID
 
- TMP007_STATUS_LHF
 
- TMP007_STATUS_LLF
 
- TMP007_STATUS_MASK
 
- TMP007_STATUS_OHF
 
- TMP007_STATUS_OLF
 
- TMP007_TDIE
 
- TMP007_TDIE_HIGH_LIMIT
 
- TMP007_TDIE_LOW_LIMIT
 
- TMP007_TEMP_SHIFT
 
- TMP007_TOBJECT
 
- TMP007_TOBJ_HIGH_LIMIT
 
- TMP007_TOBJ_LOW_LIMIT
 
- TMP102_CONFIG_CLEAR
 
- TMP102_CONFIG_SET
 
- TMP102_CONFREG_MASK
 
- TMP102_CONF_AL
 
- TMP102_CONF_CR0
 
- TMP102_CONF_CR1
 
- TMP102_CONF_EM
 
- TMP102_CONF_F0
 
- TMP102_CONF_F1
 
- TMP102_CONF_OS
 
- TMP102_CONF_POL
 
- TMP102_CONF_R0
 
- TMP102_CONF_R1
 
- TMP102_CONF_REG
 
- TMP102_CONF_SD
 
- TMP102_CONF_TM
 
- TMP102_TEMP_REG
 
- TMP102_THIGH_REG
 
- TMP102_TLOW_REG
 
- TMP103_CONFIG
 
- TMP103_CONFIG_MASK
 
- TMP103_CONF_CR0
 
- TMP103_CONF_CR1
 
- TMP103_CONF_FH
 
- TMP103_CONF_FL
 
- TMP103_CONF_ID
 
- TMP103_CONF_LC
 
- TMP103_CONF_M0
 
- TMP103_CONF_M1
 
- TMP103_CONF_REG
 
- TMP103_CONF_SD
 
- TMP103_CONF_SD_MASK
 
- TMP103_TEMP_REG
 
- TMP103_THIGH_REG
 
- TMP103_TLOW_REG
 
- TMP108_CONF_CONVRATE_MASK
 
- TMP108_CONF_CR0
 
- TMP108_CONF_CR1
 
- TMP108_CONF_DEFAULTS
 
- TMP108_CONF_FH
 
- TMP108_CONF_FL
 
- TMP108_CONF_HYS0
 
- TMP108_CONF_HYS1
 
- TMP108_CONF_HYSTERESIS_MASK
 
- TMP108_CONF_ID
 
- TMP108_CONF_M0
 
- TMP108_CONF_M1
 
- TMP108_CONF_MODE_MASK
 
- TMP108_CONF_POL
 
- TMP108_CONF_READ_ONLY
 
- TMP108_CONF_TM
 
- TMP108_CONVERSION_TIME_MS
 
- TMP108_CONVRATE_0P25HZ
 
- TMP108_CONVRATE_16HZ
 
- TMP108_CONVRATE_1HZ
 
- TMP108_CONVRATE_4HZ
 
- TMP108_HYSTERESIS_0C
 
- TMP108_HYSTERESIS_1C
 
- TMP108_HYSTERESIS_2C
 
- TMP108_HYSTERESIS_4C
 
- TMP108_MODE_CONTINUOUS
 
- TMP108_MODE_ONE_SHOT
 
- TMP108_MODE_SHUTDOWN
 
- TMP108_REG_CONF
 
- TMP108_REG_TEMP
 
- TMP108_REG_THIGH
 
- TMP108_REG_TLOW
 
- TMP108_TEMP_MAX_MC
 
- TMP108_TEMP_MIN_MC
 
- TMP401_CONFIG_RANGE
 
- TMP401_CONFIG_READ
 
- TMP401_CONFIG_SHUTDOWN
 
- TMP401_CONFIG_WRITE
 
- TMP401_CONVERSION_RATE_READ
 
- TMP401_CONVERSION_RATE_WRITE
 
- TMP401_DEVICE_ID
 
- TMP401_DEVICE_ID_REG
 
- TMP401_MANUFACTURER_ID
 
- TMP401_MANUFACTURER_ID_REG
 
- TMP401_STATUS
 
- TMP401_STATUS_LOCAL_CRIT
 
- TMP401_STATUS_LOCAL_HIGH
 
- TMP401_STATUS_LOCAL_LOW
 
- TMP401_STATUS_REMOTE_CRIT
 
- TMP401_STATUS_REMOTE_HIGH
 
- TMP401_STATUS_REMOTE_LOW
 
- TMP401_STATUS_REMOTE_OPEN
 
- TMP401_TEMP_CRIT_HYST
 
- TMP411A_DEVICE_ID
 
- TMP411B_DEVICE_ID
 
- TMP411C_DEVICE_ID
 
- TMP421_CONFIG_RANGE
 
- TMP421_CONFIG_REG_1
 
- TMP421_CONFIG_SHUTDOWN
 
- TMP421_CONVERSION_RATE_REG
 
- TMP421_DEVICE_ID
 
- TMP421_DEVICE_ID_REG
 
- TMP421_MANUFACTURER_ID
 
- TMP421_MANUFACTURER_ID_REG
 
- TMP421_STATUS_REG
 
- TMP422_DEVICE_ID
 
- TMP423_DEVICE_ID
 
- TMP431_DEVICE_ID
 
- TMP432_DEVICE_ID
 
- TMP432_STATUS_LOCAL
 
- TMP432_STATUS_REMOTE1
 
- TMP432_STATUS_REMOTE2
 
- TMP435_DEVICE_ID
 
- TMP441_DEVICE_ID
 
- TMP442_DEVICE_ID
 
- TMP451_REG_R_LOCAL_TEMPL
 
- TMPALIAS_MAP_START
 
- TMPBUFLEN
 
- TMPBUFSIZE
 
- TMPFS_MAGIC
 
- TMPL_ADD_SP
 
- TMPL_CALL_HDLR_IDX
 
- TMPL_CALL_IDX
 
- TMPL_EMULATE_IDX
 
- TMPL_END_IDX
 
- TMPL_INSN_IDX
 
- TMPL_MOVE_IDX
 
- TMPL_OP_IDX
 
- TMPL_RESTORE_BEGIN
 
- TMPL_RESTORE_END
 
- TMPL_RESTORE_ORIGN_INSN
 
- TMPL_RET_IDX
 
- TMPL_SUB_SP
 
- TMPL_VAL_IDX
 
- TMPSENS
 
- TMPSENS_CK
 
- TMPSENS_R
 
- TMPSZ
 
- TMP_BUF_MAX
 
- TMP_CLIENT_ID
 
- TMP_REG_1
 
- TMP_REG_2
 
- TMP_REG_3
 
- TMP_SIZE
 
- TMP_VIRT_IMMR
 
- TMR
 
- TMR0
 
- TMR01
 
- TMR0CTL_ENABLE
 
- TMR0CTL_MODE_PERIODIC
 
- TMR0CTL_PRESCALER
 
- TMR0CTL_PRESCALE_DIV
 
- TMR0CTL_PRESCALE_VAL
 
- TMR1
 
- TMR1CTL_ENABLE
 
- TMR1CTL_MODE_FREE_RUNNING
 
- TMR1CTL_MODE_MASK
 
- TMR1CTL_MODE_PERIODIC
 
- TMR1CTL_MODE_SHIFT
 
- TMR1CTL_MODE_TIMEOUT
 
- TMR1CTL_MODE_WDT
 
- TMR1CTL_PRESCALE_65536
 
- TMR1CTL_PRESCALE_MASK
 
- TMR1CTL_PRESCALE_SHIFT
 
- TMR1CTL_RESTART
 
- TMR1_IRQ_NUM
 
- TMR23
 
- TMR2_IRQ_NUM
 
- TMR45
 
- TMRDIV_SHIFT
 
- TMRLUT_HW_CGC_EN
 
- TMRN
 
- TMRN_IMSR0
 
- TMRN_IMSR1
 
- TMRN_INIA0
 
- TMRN_INIA1
 
- TMRN_TMCFG0
 
- TMRN_TMCFG0_NATHRD
 
- TMRN_TMCFG0_NATHRD_SHIFT
 
- TMRN_TMCFG0_NPRIBITS
 
- TMRN_TMCFG0_NPRIBITS_SHIFT
 
- TMRN_TMCFG0_NTHRD
 
- TMRSTAT_TMR0INT
 
- TMRSTAT_TMR1RST
 
- TMR_0_HZ
 
- TMR_16
 
- TMR_32
 
- TMR_8
 
- TMR_ABORT_TASK
 
- TMR_ABORT_TASK_SET
 
- TMR_ALPF
 
- TMR_CCR
 
- TMR_CCR_CS_0
 
- TMR_CCR_CS_1
 
- TMR_CCR_CS_2
 
- TMR_CER
 
- TMR_CLEAR_ACA
 
- TMR_CLEAR_TASK_SET
 
- TMR_CLOCK
 
- TMR_CMR
 
- TMR_CNT0
 
- TMR_CNT1
 
- TMR_CNT2
 
- TMR_CONTINUE
 
- TMR_CR
 
- TMR_CTRL
 
- TMR_CVWR
 
- TMR_DISABLE
 
- TMR_ECHO
 
- TMR_EXTERNAL
 
- TMR_FUNCTION_COMPLETE
 
- TMR_FUNCTION_FAILED
 
- TMR_FUNCTION_REJECTED
 
- TMR_ICR
 
- TMR_IER
 
- TMR_ILR
 
- TMR_INTERNAL
 
- TMR_IRQ_NUM
 
- TMR_LUN_DOES_NOT_EXIST
 
- TMR_LUN_RESET
 
- TMR_ME
 
- TMR_MODE_CLS
 
- TMR_MODE_FSK
 
- TMR_MODE_MIDI
 
- TMR_MODE_SMPTE
 
- TMR_PEMASK_TSREEN
 
- TMR_PEVENT_TSRE
 
- TMR_PLCR
 
- TMR_PLVR
 
- TMR_SPP
 
- TMR_SR
 
- TMR_START
 
- TMR_STOP
 
- TMR_TARGET_COLD_RESET
 
- TMR_TARGET_WARM_RESET
 
- TMR_TASK_DOES_NOT_EXIST
 
- TMR_TASK_MGMT_FUNCTION_NOT_SUPPORTED
 
- TMR_TEMPO
 
- TMR_TIMESIG
 
- TMR_TN_MM
 
- TMR_UNKNOWN
 
- TMR_WAIT_ABS
 
- TMR_WAIT_REL
 
- TMR_WCR
 
- TMR_WFAR
 
- TMR_WICR
 
- TMR_WMER
 
- TMR_WMR
 
- TMR_WSAR
 
- TMR_WSR
 
- TMR_WVR
 
- TMS
 
- TMS320_CLOCK
 
- TMS320_PORT1
 
- TMS320_PORT2
 
- TMSR
 
- TMS_HIGH
 
- TMS_LOW
 
- TMS_MARK
 
- TMTMIR_DEFAULT
 
- TMU
 
- TMU0
 
- TMU00
 
- TMU012
 
- TMU0_0
 
- TMU0_1
 
- TMU0_2
 
- TMU0_3
 
- TMU0_TUNI0
 
- TMU0_TUNI1
 
- TMU0_TUNI2
 
- TMU1
 
- TMU10
 
- TMU1_0
 
- TMU1_1
 
- TMU1_2
 
- TMU1_TUNI0
 
- TMU1_TUNI1
 
- TMU1_TUNI2
 
- TMU2
 
- TMU20
 
- TMU21
 
- TMU2_TICPI
 
- TMU3
 
- TMU30
 
- TMU345
 
- TMU4
 
- TMU40
 
- TMU5
 
- TMU50
 
- TMU51
 
- TMU5_TICPI
 
- TMU6
 
- TMU60
 
- TMU7
 
- TMU70
 
- TMU8
 
- TMU80
 
- TMUGBEINIT
 
- TMU_0_M
 
- TMU_3_M
 
- TMU_ACCESS_EN
 
- TMU_BASE
 
- TMU_BLOCK_OFF
 
- TMU_SUNI
 
- TM_040
 
- TM_ACCESS
 
- TM_ACK_CNT
 
- TM_ADD_BANK4
 
- TM_AGE
 
- TM_ALIGN
 
- TM_ATTR
 
- TM_BANK_WAIT
 
- TM_BUFFER_FLAG_DONE
 
- TM_BUFFER_FLAG_DUMMY_BUFFER
 
- TM_BUFFER_FLAG_EMPTY
 
- TM_BUR
 
- TM_CAUSE_ALIGNMENT
 
- TM_CAUSE_EMULATE
 
- TM_CAUSE_FAC_UNAV
 
- TM_CAUSE_KVM_FAC_UNAV
 
- TM_CAUSE_KVM_RESCHED
 
- TM_CAUSE_MISC
 
- TM_CAUSE_PERSISTENT
 
- TM_CAUSE_RESCHED
 
- TM_CAUSE_SIGNAL
 
- TM_CAUSE_SYSCALL
 
- TM_CAUSE_TLBI
 
- TM_CFG
 
- TM_CFG_CID_PRE_SCAN_ROWS_MASK
 
- TM_CFG_CID_PRE_SCAN_ROWS_SHIFT
 
- TM_CFG_NUM_IDS_MASK
 
- TM_CFG_NUM_IDS_SHIFT
 
- TM_CFG_PARENT_PF_MASK
 
- TM_CFG_PARENT_PF_SHIFT
 
- TM_CFG_PRE_SCAN_OFFSET_MASK
 
- TM_CFG_PRE_SCAN_OFFSET_SHIFT
 
- TM_CFG_TID_OFFSET_MASK
 
- TM_CFG_TID_OFFSET_SHIFT
 
- TM_CFG_TID_PRE_SCAN_ROWS_MASK
 
- TM_CFG_TID_PRE_SCAN_ROWS_SHIFT
 
- TM_CMD_NUM
 
- TM_CMD_PERIOD
 
- TM_CMD_PWM
 
- TM_CMD_RESTART
 
- TM_CMD_TIMEOUT
 
- TM_CMD_VALID
 
- TM_CNT_LDW
 
- TM_CNT_UW
 
- TM_CONN_NUM
 
- TM_CPPR
 
- TM_CREATE
 
- TM_CRITICAL_INT_CLEAR_OFF
 
- TM_CRITICAL_INT_MASK_OFF
 
- TM_CRITICAL_INT_STATUS_OFF
 
- TM_DEBUG
 
- TM_DESL2
 
- TM_ELEM_SIZE
 
- TM_FRAME_L0
 
- TM_FRAME_L1
 
- TM_ILT_LINES
 
- TM_ILT_PAGE_SZ
 
- TM_ILT_PAGE_SZ_HW
 
- TM_ILT_SZ
 
- TM_INC
 
- TM_INT_EN_OFF
 
- TM_IPB
 
- TM_IPB_MASK
 
- TM_IPB_SHIFT
 
- TM_KVM_SCHED
 
- TM_LMT_LDW
 
- TM_LMT_UW
 
- TM_LSMFB
 
- TM_MODIFY
 
- TM_NSR
 
- TM_OFFSET
 
- TM_PAR_CHECK
 
- TM_PIPR
 
- TM_QW0W2_LOGIC_SERV
 
- TM_QW0W2_VU
 
- TM_QW0_NSR_EB
 
- TM_QW0_USER
 
- TM_QW1W2_OS_CAM
 
- TM_QW1W2_VO
 
- TM_QW1_NSR_EO
 
- TM_QW1_OS
 
- TM_QW2W2_POOL_CAM
 
- TM_QW2W2_VP
 
- TM_QW2_HV_POOL
 
- TM_QW3W2_LE
 
- TM_QW3W2_LP
 
- TM_QW3W2_T
 
- TM_QW3W2_VT
 
- TM_QW3_HV_PHYS
 
- TM_QW3_NSR_GRP_LVL
 
- TM_QW3_NSR_HE
 
- TM_QW3_NSR_HE_LSI
 
- TM_QW3_NSR_HE_NONE
 
- TM_QW3_NSR_HE_PHYS
 
- TM_QW3_NSR_HE_POOL
 
- TM_QW3_NSR_I
 
- TM_REG_CFC_AC_CRDCNT_VAL
 
- TM_REG_CFC_CLD_CRDCNT_VAL
 
- TM_REG_CL0_CONT_REGION
 
- TM_REG_CL1_CONT_REGION
 
- TM_REG_CL2_CONT_REGION
 
- TM_REG_CLIN_PRIOR0_CLIENT
 
- TM_REG_CLOUT_CRDCNT0_VAL
 
- TM_REG_CLOUT_CRDCNT1_VAL
 
- TM_REG_CLOUT_CRDCNT2_VAL
 
- TM_REG_CONFIG_CONN_MEM_RT_OFFSET
 
- TM_REG_CONFIG_CONN_MEM_RT_SIZE
 
- TM_REG_CONFIG_TASK_MEM_RT_OFFSET
 
- TM_REG_CONFIG_TASK_MEM_RT_SIZE
 
- TM_REG_DBG_DWORD_ENABLE
 
- TM_REG_DBG_FORCE_FRAME
 
- TM_REG_DBG_FORCE_VALID
 
- TM_REG_DBG_SELECT
 
- TM_REG_DBG_SHIFT
 
- TM_REG_EN_CL0_INPUT
 
- TM_REG_EN_CL1_INPUT
 
- TM_REG_EN_CL2_INPUT
 
- TM_REG_EN_LINEAR0_TIMER
 
- TM_REG_EN_REAL_TIME_CNT
 
- TM_REG_EN_TIMERS
 
- TM_REG_EXP_CRDCNT_VAL
 
- TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET
 
- TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET
 
- TM_REG_LIN0_LOGIC_ADDR
 
- TM_REG_LIN0_MAX_ACTIVE_CID
 
- TM_REG_LIN0_NUM_SCANS
 
- TM_REG_LIN0_PHY_ADDR
 
- TM_REG_LIN0_PHY_ADDR_VALID
 
- TM_REG_LIN0_SCAN_ON
 
- TM_REG_LIN0_SCAN_TIME
 
- TM_REG_LIN0_VNIC_UC
 
- TM_REG_LIN1_LOGIC_ADDR
 
- TM_REG_LIN1_PHY_ADDR
 
- TM_REG_LIN1_PHY_ADDR_VALID
 
- TM_REG_LIN_SETCLR_FIFO_ALFULL_THR
 
- TM_REG_PCIARB_CRDCNT_VAL
 
- TM_REG_PF_ENABLE_CONN
 
- TM_REG_PF_ENABLE_CONN_RT_OFFSET
 
- TM_REG_PF_ENABLE_TASK
 
- TM_REG_PF_ENABLE_TASK_RT_OFFSET
 
- TM_REG_PF_SCAN_ACTIVE_CONN
 
- TM_REG_PF_SCAN_ACTIVE_TASK
 
- TM_REG_PXP_READ_DATA_FIFO_INIT
 
- TM_REG_TIMER_TICK_SIZE
 
- TM_REG_TM_CONTEXT_REGION
 
- TM_REG_TM_INT_MASK
 
- TM_REG_TM_INT_STS
 
- TM_REG_TM_PRTY_MASK
 
- TM_REG_TM_PRTY_STS
 
- TM_REG_TM_PRTY_STS_CLR
 
- TM_REG_VF_ENABLE_CONN_RT_OFFSET
 
- TM_RETRIES
 
- TM_RW_WAIT
 
- TM_SHIFT
 
- TM_SPC_ACK_EBB
 
- TM_SPC_ACK_HV_EL
 
- TM_SPC_ACK_HV_POOL_EL
 
- TM_SPC_ACK_HV_REG
 
- TM_SPC_ACK_OS_EL
 
- TM_SPC_ACK_OS_REG
 
- TM_SPC_PULL_OS_CTX
 
- TM_SPC_PULL_POOL_CTX
 
- TM_SPC_PULL_USR_CTX
 
- TM_SPC_PULL_USR_CTX_OL
 
- TM_SPC_PUSH_USR_CTX
 
- TM_SPC_SET_OS_PENDING
 
- TM_SRAM_TYPE
 
- TM_STATE_ERROR
 
- TM_STATE_IN_PROGRESS
 
- TM_STATE_NONE
 
- TM_Sn_CRITICAL_THRESHOLD_OFF
 
- TM_Sn_STATUS_OFF
 
- TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF
 
- TM_Sn_UPPER_LOWER_THRESHOLD_OFF
 
- TM_TRDY_OFF
 
- TM_UPPER_LOWER_INT_CLEAR_OFF
 
- TM_UPPER_LOWER_INT_MASK_OFF
 
- TM_UPPER_LOWER_INT_STATUS_OFF
 
- TM_WORD0
 
- TM_WORD1
 
- TM_WORD2
 
- TN
 
- TN1010_PHY_ID
 
- TNCL
 
- TNCL_ADDR
 
- TNCSF_BIT
 
- TNCSF_SHIFT
 
- TNC_IN_SYNC
 
- TNC_UNINITIALIZED
 
- TNC_UNSYNCED
 
- TNC_UNSYNC_STARTUP
 
- TNEG
 
- TNETD7200_CLOCK_ID_CPU
 
- TNETD7200_CLOCK_ID_DSP
 
- TNETD7200_CLOCK_ID_USB
 
- TNETD7200_DEF_CPU_CLK
 
- TNETD7200_DEF_DSP_CLK
 
- TNETD7200_DEF_USB_CLK
 
- TNF_FAULT_LOCAL
 
- TNF_MIGRATED
 
- TNF_MIGRATE_FAIL
 
- TNF_NO_GROUP
 
- TNF_SHARED
 
- TNG_BT_SFI_GPIO_DEVICE_WAKEUP
 
- TNG_BT_SFI_GPIO_HOST_WAKEUP
 
- TNG_BT_SFI_GPIO_SHUTDOWN
 
- TNL2TUPENIPV4_F
 
- TNL2TUPENIPV4_S
 
- TNL2TUPENIPV4_V
 
- TNL2TUPENIPV6_F
 
- TNL2TUPENIPV6_S
 
- TNL2TUPENIPV6_V
 
- TNL4TUPENIPV4_F
 
- TNL4TUPENIPV4_S
 
- TNL4TUPENIPV4_V
 
- TNL4TUPENIPV6_F
 
- TNL4TUPENIPV6_S
 
- TNL4TUPENIPV6_V
 
- TNLALLLOOKUP_F
 
- TNLALLLOOKUP_S
 
- TNLALLLOOKUP_V
 
- TNLIP6SEL_F
 
- TNLIP6SEL_S
 
- TNLIP6SEL_V
 
- TNLMAPEN_F
 
- TNLMAPEN_S
 
- TNLMAPEN_V
 
- TNLRATE0_G
 
- TNLRATE0_M
 
- TNLRATE0_S
 
- TNLRATE1_G
 
- TNLRATE1_M
 
- TNLRATE1_S
 
- TNLRATE2_G
 
- TNLRATE2_M
 
- TNLRATE2_S
 
- TNLRATE3_G
 
- TNLRATE3_M
 
- TNLRATE3_S
 
- TNLTCPSEL_F
 
- TNLTCPSEL_S
 
- TNLTCPSEL_V
 
- TNLVRTSEL_F
 
- TNLVRTSEL_S
 
- TNLVRTSEL_V
 
- TNODE_KMALLOC_MAX
 
- TNODE_SIZE
 
- TNODE_VMALLOC_MAX
 
- TNONE
 
- TNPP_F
 
- TNPP_S
 
- TNPP_V
 
- TNR
 
- TNR0
 
- TNR1
 
- TNRADJ
 
- TNRBW
 
- TNRCFG
 
- TNRCFG2
 
- TNRCFG3
 
- TNRCTL2
 
- TNRGAIN
 
- TNRLAUNCH
 
- TNRLD
 
- TNROBSL
 
- TNRRESTE
 
- TNRRF0
 
- TNRRF1
 
- TNRSTEPS
 
- TNRXTAL
 
- TNR_MASK
 
- TNR_SHIFT
 
- TNT_DEMAND_READ
 
- TNT_DEMAND_WRITE
 
- TNT_LLC_ACCESS
 
- TNT_LLC_MISS
 
- TNT_LOCAL_DRAM
 
- TNT_SNP_ANY
 
- TNUM
 
- TNX_FW_REV
 
- TN_CG_THERMAL_INT_CTRL
 
- TN_CURRENT_GNB_TEMP
 
- TN_DIG_THERM_INTH
 
- TN_DIG_THERM_INTH_MASK
 
- TN_DIG_THERM_INTH_SHIFT
 
- TN_DIG_THERM_INTL
 
- TN_DIG_THERM_INTL_MASK
 
- TN_DIG_THERM_INTL_SHIFT
 
- TN_RING_TYPE_VCE1_INDEX
 
- TN_RING_TYPE_VCE2_INDEX
 
- TN_RLC_CLEAR_STATE_RESTORE_BASE
 
- TN_RLC_LB_ALWAYS_ACTIVE_SIMD_MASK
 
- TN_RLC_LB_CNTR_INIT
 
- TN_RLC_LB_CNTR_MAX
 
- TN_RLC_LB_INIT_SIMD_MASK
 
- TN_RLC_LB_PARAMS
 
- TN_RLC_SAVE_AND_RESTORE_BASE
 
- TN_SMC_IND_DATA_0
 
- TN_SMC_IND_INDEX_0
 
- TN_THERM_INT_MASK_HIGH
 
- TN_THERM_INT_MASK_LOW
 
- TO
 
- TOC
 
- TOC_BITMAP1
 
- TOC_BITMAP2
 
- TOD1_MASK
 
- TOD2000_CNTRL1_BUSY
 
- TOD2000_CNTRL1_HOLD
 
- TOD2000_CNTRL3_24HMODE
 
- TOD2000_HOUR1_PM
 
- TOD2_MASK
 
- TOD3000_CNTRL1_FREE
 
- TOD3000_CNTRL1_HOLD
 
- TODDR_MSB_POS
 
- TODO_AUTHENTICATE_TIMEOUT
 
- TODO_FLAGS_FINISH
 
- TODO_FLAGS_START
 
- TODO_JOIN_NET
 
- TODO_NOTHING
 
- TODO_SEND_CCS
 
- TODO_START_NET
 
- TODO_VERIFY_DL_START
 
- TODO_dump_cgraph
 
- TODO_dump_func
 
- TODO_ggc_collect
 
- TODO_rebuild_cgraph_edges
 
- TODO_verify_flow
 
- TODO_verify_il
 
- TODO_verify_rtl_sharing
 
- TODO_verify_ssa
 
- TODO_verify_stmts
 
- TOD_ACC_PIN
 
- TOD_MICRO
 
- TOD_UNIX_EPOCH
 
- TOECS_MASK
 
- TOEQ
 
- TOE_CLASSIFICATION_QID
 
- TOE_CLASS_Q_HDR_BASE
 
- TOE_CLASS_RX_INT_BITS
 
- TOE_CONNECTION_TYPE
 
- TOE_DEFAULT_Q_HDR_BASE
 
- TOE_GMAC0_DEFAULT_QID
 
- TOE_GMAC0_HW_TXQ0_QID
 
- TOE_GMAC0_HW_TXQ1_QID
 
- TOE_GMAC0_HW_TXQ2_QID
 
- TOE_GMAC0_HW_TXQ3_QID
 
- TOE_GMAC0_SW_TXQ0_QID
 
- TOE_GMAC0_SW_TXQ1_QID
 
- TOE_GMAC0_SW_TXQ2_QID
 
- TOE_GMAC0_SW_TXQ3_QID
 
- TOE_GMAC0_SW_TXQ4_QID
 
- TOE_GMAC0_SW_TXQ5_QID
 
- TOE_GMAC1_DEFAULT_QID
 
- TOE_GMAC1_HW_TXQ0_QID
 
- TOE_GMAC1_HW_TXQ1_QID
 
- TOE_GMAC1_HW_TXQ2_QID
 
- TOE_GMAC1_HW_TXQ3_QID
 
- TOE_GMAC1_SW_TXQ0_QID
 
- TOE_GMAC1_SW_TXQ1_QID
 
- TOE_GMAC1_SW_TXQ2_QID
 
- TOE_GMAC1_SW_TXQ3_QID
 
- TOE_GMAC1_SW_TXQ4_QID
 
- TOE_GMAC1_SW_TXQ5_QID
 
- TOE_HW_FREE_QID
 
- TOE_INTR_Q_HDR_BASE
 
- TOE_IQ0_FULL_INT_BIT
 
- TOE_IQ0_INT_BIT
 
- TOE_IQ1_FULL_INT_BIT
 
- TOE_IQ1_INT_BIT
 
- TOE_IQ2_FULL_INT_BIT
 
- TOE_IQ2_INT_BIT
 
- TOE_IQ3_FULL_INT_BIT
 
- TOE_IQ3_INT_BIT
 
- TOE_IQ_ALL_BITS
 
- TOE_IQ_FULL_BITS
 
- TOE_IQ_INT_BITS
 
- TOE_NONTOE_QUE_HDR_BASE
 
- TOE_QH_FULL_INT_BIT
 
- TOE_QL_FULL_INT_BIT
 
- TOE_QUEUE_HDR_ADDR
 
- TOE_Q_HDR_AREA_END
 
- TOE_RX_CSUM_OL
 
- TOE_STATE
 
- TOE_SW_FREE_QID
 
- TOE_TOE_QID
 
- TOE_TOE_QUE_HDR_BASE
 
- TOE_TX_CSUM_OL
 
- TOFFSET
 
- TOFFSET_MASK
 
- TOFFSET_MAXIMUM_ADJUSTMENT
 
- TOFFSET_MINIMUM_ADJUSTMENT
 
- TOFFSET_SET_MARGIN
 
- TOFFSET_SHIFT
 
- TOF_CONFIG_CMD
 
- TOF_LC_NOTIF
 
- TOF_MCSI_DEBUG_NOTIF
 
- TOF_RANGE_ABORT_CMD
 
- TOF_RANGE_REQ_CMD
 
- TOF_RANGE_REQ_EXT_CMD
 
- TOF_RANGE_RESPONSE_NOTIF
 
- TOF_RESPONDER_CONFIG_CMD
 
- TOF_RESPONDER_DYN_CONFIG_CMD
 
- TOF_RESPONDER_STATS
 
- TOG
 
- TOGE
 
- TOGGLE_0
 
- TOGGLE_1
 
- TOGGLE_CURSORING
 
- TOGGLE_GPIO
 
- TOGGLE_PORT
 
- TOGGLE_VALID
 
- TOGGLING_MODE_DRP
 
- TOGGLING_MODE_OFF
 
- TOGGLING_MODE_SNK
 
- TOGGLING_MODE_SRC
 
- TOGT
 
- TOG_REG
 
- TOHDMITX_CTRL0
 
- TOHDMITX_I2S_FORMATS
 
- TOHDMITX_I2S_IN_A
 
- TOHDMITX_I2S_IN_B
 
- TOHDMITX_I2S_IN_C
 
- TOHDMITX_I2S_OUT
 
- TOHDMITX_IN
 
- TOHDMITX_OUT
 
- TOHDMITX_SPDIF_FORMATS
 
- TOHDMITX_SPDIF_IN_A
 
- TOHDMITX_SPDIF_IN_B
 
- TOHDMITX_SPDIF_OUT
 
- TOHDMITX_STREAM
 
- TOHM
 
- TOKEN_ASSIGNMENT
 
- TOKEN_CLOSE_ACTION
 
- TOKEN_CLOSE_CURLY
 
- TOKEN_CLOSE_SQUARE
 
- TOKEN_COMMA
 
- TOKEN_DATA
 
- TOKEN_DATA_LAST
 
- TOKEN_DEBUG
 
- TOKEN_ELEMENT_NAME
 
- TOKEN_END
 
- TOKEN_FRAME
 
- TOKEN_IFNAME
 
- TOKEN_MISMATCH
 
- TOKEN_NUMBER
 
- TOKEN_NVRAM
 
- TOKEN_OPEN_ACTION
 
- TOKEN_OPEN_CURLY
 
- TOKEN_OPEN_SQUARE
 
- TOKEN_PPR
 
- TOKEN_RADIO_OFF
 
- TOKEN_SLAVE_ADDR_READ
 
- TOKEN_SLAVE_ADDR_WRITE
 
- TOKEN_SLEEP
 
- TOKEN_START
 
- TOKEN_STOP
 
- TOKEN_SYNC
 
- TOKEN_TYPE_NAME
 
- TOKEN_VERBOSE
 
- TOKEN_WAKEUP
 
- TOKEN_WIDE
 
- TOKTYPE_CCA_INTERNAL
 
- TOKTYPE_NON_CCA
 
- TOKVER_CCA_AES
 
- TOKVER_CCA_VLSC
 
- TOKVER_PROTECTED_KEY
 
- TOK_DELAY
 
- TOK_SKIP
 
- TOK_TERM
 
- TOK_WRITE
 
- TOLE
 
- TOLERANCE_UNIT_ATTRS
 
- TOLGE
 
- TOLGT
 
- TOLLE
 
- TOLLT
 
- TOLM
 
- TOLNG
 
- TOLNL
 
- TOLOWER
 
- TOLT
 
- TOL_TEMP_TO_REG
 
- TOMATILLO_IOC_PART_WPENAB
 
- TOMATILLO_IOC_PREF_OFF
 
- TOMATILLO_IOC_PREF_OFF_SHIFT
 
- TOMATILLO_IOC_RDLINE_CPENAB
 
- TOMATILLO_IOC_RDLINE_PENAB
 
- TOMATILLO_IOC_RDLINE_PLEN
 
- TOMATILLO_IOC_RDLINE_PLEN_SHIFT
 
- TOMATILLO_IOC_RDMULT_CPENAB
 
- TOMATILLO_IOC_RDMULT_PENAB
 
- TOMATILLO_IOC_RDMULT_PLEN
 
- TOMATILLO_IOC_RDMULT_PLEN_SHIFT
 
- TOMATILLO_IOC_RDONE_CPENAB
 
- TOMATILLO_IOC_RDONE_PENAB
 
- TOMATILLO_IOC_RDONE_PLEN
 
- TOMATILLO_IOC_RDONE_PLEN_SHIFT
 
- TOMATILLO_PCI_IOC_CSR
 
- TOMATILLO_PCI_IOC_DDIAG
 
- TOMATILLO_PCI_IOC_TDIAG
 
- TOMINOR
 
- TOMOYO_ADDRESS_GROUP
 
- TOMOYO_ARGV_ENTRY
 
- TOMOYO_AUDIT
 
- TOMOYO_CONFIG_DISABLED
 
- TOMOYO_CONFIG_ENFORCING
 
- TOMOYO_CONFIG_LEARNING
 
- TOMOYO_CONFIG_MAX_MODE
 
- TOMOYO_CONFIG_PERMISSIVE
 
- TOMOYO_CONFIG_USE_DEFAULT
 
- TOMOYO_CONFIG_WANT_GRANT_LOG
 
- TOMOYO_CONFIG_WANT_REJECT_LOG
 
- TOMOYO_DIF_QUOTA_WARNED
 
- TOMOYO_DIF_TRANSITION_FAILED
 
- TOMOYO_DOMAINPOLICY
 
- TOMOYO_ENVP_ENTRY
 
- TOMOYO_EXCEPTIONPOLICY
 
- TOMOYO_EXEC_ARGC
 
- TOMOYO_EXEC_ENVC
 
- TOMOYO_EXEC_REALPATH
 
- TOMOYO_EXEC_TMPSIZE
 
- TOMOYO_GC_IN_PROGRESS
 
- TOMOYO_GRANTLOG_AUTO
 
- TOMOYO_GRANTLOG_NO
 
- TOMOYO_GRANTLOG_YES
 
- TOMOYO_HASH_BITS
 
- TOMOYO_ID_ACL
 
- TOMOYO_ID_ADDRESS_GROUP
 
- TOMOYO_ID_AGGREGATOR
 
- TOMOYO_ID_CONDITION
 
- TOMOYO_ID_DOMAIN
 
- TOMOYO_ID_GROUP
 
- TOMOYO_ID_MANAGER
 
- TOMOYO_ID_NAME
 
- TOMOYO_ID_NUMBER_GROUP
 
- TOMOYO_ID_PATH_GROUP
 
- TOMOYO_ID_TRANSITION_CONTROL
 
- TOMOYO_MAC_CATEGORY_FILE
 
- TOMOYO_MAC_CATEGORY_MISC
 
- TOMOYO_MAC_CATEGORY_NETWORK
 
- TOMOYO_MAC_ENVIRON
 
- TOMOYO_MAC_FILE_CHGRP
 
- TOMOYO_MAC_FILE_CHMOD
 
- TOMOYO_MAC_FILE_CHOWN
 
- TOMOYO_MAC_FILE_CHROOT
 
- TOMOYO_MAC_FILE_CREATE
 
- TOMOYO_MAC_FILE_EXECUTE
 
- TOMOYO_MAC_FILE_GETATTR
 
- TOMOYO_MAC_FILE_IOCTL
 
- TOMOYO_MAC_FILE_LINK
 
- TOMOYO_MAC_FILE_MKBLOCK
 
- TOMOYO_MAC_FILE_MKCHAR
 
- TOMOYO_MAC_FILE_MKDIR
 
- TOMOYO_MAC_FILE_MKFIFO
 
- TOMOYO_MAC_FILE_MKSOCK
 
- TOMOYO_MAC_FILE_MOUNT
 
- TOMOYO_MAC_FILE_OPEN
 
- TOMOYO_MAC_FILE_PIVOT_ROOT
 
- TOMOYO_MAC_FILE_RENAME
 
- TOMOYO_MAC_FILE_RMDIR
 
- TOMOYO_MAC_FILE_SYMLINK
 
- TOMOYO_MAC_FILE_TRUNCATE
 
- TOMOYO_MAC_FILE_UMOUNT
 
- TOMOYO_MAC_FILE_UNLINK
 
- TOMOYO_MAC_NETWORK_INET_DGRAM_BIND
 
- TOMOYO_MAC_NETWORK_INET_DGRAM_SEND
 
- TOMOYO_MAC_NETWORK_INET_RAW_BIND
 
- TOMOYO_MAC_NETWORK_INET_RAW_SEND
 
- TOMOYO_MAC_NETWORK_INET_STREAM_BIND
 
- TOMOYO_MAC_NETWORK_INET_STREAM_CONNECT
 
- TOMOYO_MAC_NETWORK_INET_STREAM_LISTEN
 
- TOMOYO_MAC_NETWORK_UNIX_DGRAM_BIND
 
- TOMOYO_MAC_NETWORK_UNIX_DGRAM_SEND
 
- TOMOYO_MAC_NETWORK_UNIX_SEQPACKET_BIND
 
- TOMOYO_MAC_NETWORK_UNIX_SEQPACKET_CONNECT
 
- TOMOYO_MAC_NETWORK_UNIX_SEQPACKET_LISTEN
 
- TOMOYO_MAC_NETWORK_UNIX_STREAM_BIND
 
- TOMOYO_MAC_NETWORK_UNIX_STREAM_CONNECT
 
- TOMOYO_MAC_NETWORK_UNIX_STREAM_LISTEN
 
- TOMOYO_MANAGER
 
- TOMOYO_MAX_ACL_GROUPS
 
- TOMOYO_MAX_CONDITION_KEYWORD
 
- TOMOYO_MAX_DOMAIN_INFO_FLAGS
 
- TOMOYO_MAX_GROUP
 
- TOMOYO_MAX_HASH
 
- TOMOYO_MAX_IO_READ_QUEUE
 
- TOMOYO_MAX_MAC_CATEGORY_INDEX
 
- TOMOYO_MAX_MAC_INDEX
 
- TOMOYO_MAX_MEMORY_STAT
 
- TOMOYO_MAX_MKDEV_OPERATION
 
- TOMOYO_MAX_NETWORK_OPERATION
 
- TOMOYO_MAX_PATH2_OPERATION
 
- TOMOYO_MAX_PATH_NUMBER_OPERATION
 
- TOMOYO_MAX_PATH_OPERATION
 
- TOMOYO_MAX_PATH_STAT
 
- TOMOYO_MAX_POLICY
 
- TOMOYO_MAX_POLICY_STAT
 
- TOMOYO_MAX_PREF
 
- TOMOYO_MAX_PROFILES
 
- TOMOYO_MAX_SPECIAL_MOUNT
 
- TOMOYO_MAX_TRANSITION_TYPE
 
- TOMOYO_MEMORY_AUDIT
 
- TOMOYO_MEMORY_POLICY
 
- TOMOYO_MEMORY_QUERY
 
- TOMOYO_MODE_GROUP_EXECUTE
 
- TOMOYO_MODE_GROUP_READ
 
- TOMOYO_MODE_GROUP_WRITE
 
- TOMOYO_MODE_OTHERS_EXECUTE
 
- TOMOYO_MODE_OTHERS_READ
 
- TOMOYO_MODE_OTHERS_WRITE
 
- TOMOYO_MODE_OWNER_EXECUTE
 
- TOMOYO_MODE_OWNER_READ
 
- TOMOYO_MODE_OWNER_WRITE
 
- TOMOYO_MODE_SETGID
 
- TOMOYO_MODE_SETUID
 
- TOMOYO_MODE_STICKY
 
- TOMOYO_MOUNT_BIND
 
- TOMOYO_MOUNT_MAKE_PRIVATE
 
- TOMOYO_MOUNT_MAKE_SHARED
 
- TOMOYO_MOUNT_MAKE_SLAVE
 
- TOMOYO_MOUNT_MAKE_UNBINDABLE
 
- TOMOYO_MOUNT_MOVE
 
- TOMOYO_MOUNT_REMOUNT
 
- TOMOYO_NAME_UNION
 
- TOMOYO_NETWORK_BIND
 
- TOMOYO_NETWORK_CONNECT
 
- TOMOYO_NETWORK_LISTEN
 
- TOMOYO_NETWORK_SEND
 
- TOMOYO_NUMBER_GROUP
 
- TOMOYO_NUMBER_UNION
 
- TOMOYO_PATH1
 
- TOMOYO_PATH1_DEV_MAJOR
 
- TOMOYO_PATH1_DEV_MINOR
 
- TOMOYO_PATH1_GID
 
- TOMOYO_PATH1_INO
 
- TOMOYO_PATH1_MAJOR
 
- TOMOYO_PATH1_MINOR
 
- TOMOYO_PATH1_PARENT
 
- TOMOYO_PATH1_PARENT_GID
 
- TOMOYO_PATH1_PARENT_INO
 
- TOMOYO_PATH1_PARENT_PERM
 
- TOMOYO_PATH1_PARENT_UID
 
- TOMOYO_PATH1_PERM
 
- TOMOYO_PATH1_TYPE
 
- TOMOYO_PATH1_UID
 
- TOMOYO_PATH2
 
- TOMOYO_PATH2_DEV_MAJOR
 
- TOMOYO_PATH2_DEV_MINOR
 
- TOMOYO_PATH2_GID
 
- TOMOYO_PATH2_INO
 
- TOMOYO_PATH2_MAJOR
 
- TOMOYO_PATH2_MINOR
 
- TOMOYO_PATH2_PARENT
 
- TOMOYO_PATH2_PARENT_GID
 
- TOMOYO_PATH2_PARENT_INO
 
- TOMOYO_PATH2_PARENT_PERM
 
- TOMOYO_PATH2_PARENT_UID
 
- TOMOYO_PATH2_PERM
 
- TOMOYO_PATH2_TYPE
 
- TOMOYO_PATH2_UID
 
- TOMOYO_PATH_GROUP
 
- TOMOYO_PREF_MAX_AUDIT_LOG
 
- TOMOYO_PREF_MAX_LEARNING_ENTRY
 
- TOMOYO_PROCESS_STATUS
 
- TOMOYO_PROFILE
 
- TOMOYO_QUERY
 
- TOMOYO_RETRY_REQUEST
 
- TOMOYO_SOCK_MAX
 
- TOMOYO_STAT
 
- TOMOYO_STAT_POLICY_ENFORCING
 
- TOMOYO_STAT_POLICY_LEARNING
 
- TOMOYO_STAT_POLICY_PERMISSIVE
 
- TOMOYO_STAT_POLICY_UPDATES
 
- TOMOYO_SYMLINK_TARGET
 
- TOMOYO_TASK_EGID
 
- TOMOYO_TASK_EUID
 
- TOMOYO_TASK_FSGID
 
- TOMOYO_TASK_FSUID
 
- TOMOYO_TASK_GID
 
- TOMOYO_TASK_PID
 
- TOMOYO_TASK_PPID
 
- TOMOYO_TASK_SGID
 
- TOMOYO_TASK_SUID
 
- TOMOYO_TASK_UID
 
- TOMOYO_TRANSITION_CONTROL_INITIALIZE
 
- TOMOYO_TRANSITION_CONTROL_KEEP
 
- TOMOYO_TRANSITION_CONTROL_NO_INITIALIZE
 
- TOMOYO_TRANSITION_CONTROL_NO_KEEP
 
- TOMOYO_TRANSITION_CONTROL_NO_RESET
 
- TOMOYO_TRANSITION_CONTROL_RESET
 
- TOMOYO_TYPE_APPEND
 
- TOMOYO_TYPE_CHGRP
 
- TOMOYO_TYPE_CHMOD
 
- TOMOYO_TYPE_CHOWN
 
- TOMOYO_TYPE_CHROOT
 
- TOMOYO_TYPE_CREATE
 
- TOMOYO_TYPE_ENV_ACL
 
- TOMOYO_TYPE_EXECUTE
 
- TOMOYO_TYPE_GETATTR
 
- TOMOYO_TYPE_INET_ACL
 
- TOMOYO_TYPE_IOCTL
 
- TOMOYO_TYPE_IS_BLOCK_DEV
 
- TOMOYO_TYPE_IS_CHAR_DEV
 
- TOMOYO_TYPE_IS_DIRECTORY
 
- TOMOYO_TYPE_IS_FIFO
 
- TOMOYO_TYPE_IS_FILE
 
- TOMOYO_TYPE_IS_SOCKET
 
- TOMOYO_TYPE_IS_SYMLINK
 
- TOMOYO_TYPE_LINK
 
- TOMOYO_TYPE_MANUAL_TASK_ACL
 
- TOMOYO_TYPE_MKBLOCK
 
- TOMOYO_TYPE_MKCHAR
 
- TOMOYO_TYPE_MKDEV_ACL
 
- TOMOYO_TYPE_MKDIR
 
- TOMOYO_TYPE_MKFIFO
 
- TOMOYO_TYPE_MKSOCK
 
- TOMOYO_TYPE_MOUNT_ACL
 
- TOMOYO_TYPE_PATH2_ACL
 
- TOMOYO_TYPE_PATH_ACL
 
- TOMOYO_TYPE_PATH_NUMBER_ACL
 
- TOMOYO_TYPE_PIVOT_ROOT
 
- TOMOYO_TYPE_READ
 
- TOMOYO_TYPE_RENAME
 
- TOMOYO_TYPE_RMDIR
 
- TOMOYO_TYPE_SYMLINK
 
- TOMOYO_TYPE_TRUNCATE
 
- TOMOYO_TYPE_UMOUNT
 
- TOMOYO_TYPE_UNIX_ACL
 
- TOMOYO_TYPE_UNLINK
 
- TOMOYO_TYPE_WRITE
 
- TOMOYO_VALUE_TYPE_DECIMAL
 
- TOMOYO_VALUE_TYPE_HEXADECIMAL
 
- TOMOYO_VALUE_TYPE_INVALID
 
- TOMOYO_VALUE_TYPE_OCTAL
 
- TOMOYO_VERSION
 
- TONE
 
- TONEPORT_PCM_DELAY
 
- TONE_AMERICAN_BUSY
 
- TONE_AMERICAN_DIALPBX
 
- TONE_AMERICAN_DIALTONE
 
- TONE_AMERICAN_HANGUP
 
- TONE_AMERICAN_RINGING
 
- TONE_AMERICAN_RINGPBX
 
- TONE_DB_TO_VOXWARE
 
- TONE_DEC
 
- TONE_FREQ
 
- TONE_FREQUENCY
 
- TONE_GERMAN_AUFSCHALTTON
 
- TONE_GERMAN_BUSY
 
- TONE_GERMAN_DIALPBX
 
- TONE_GERMAN_DIALTONE
 
- TONE_GERMAN_GASSENBESETZT
 
- TONE_GERMAN_HANGUP
 
- TONE_GERMAN_OLDBUSY
 
- TONE_GERMAN_OLDDIALPBX
 
- TONE_GERMAN_OLDDIALTONE
 
- TONE_GERMAN_OLDHANGUP
 
- TONE_GERMAN_OLDRINGING
 
- TONE_GERMAN_OLDRINGPBX
 
- TONE_GERMAN_RINGING
 
- TONE_GERMAN_RINGPBX
 
- TONE_INC
 
- TONE_OFF
 
- TONE_SPECIAL_INFO
 
- TONE_VOLUME
 
- TONE_VOXWARE_TO_DB
 
- TONG
 
- TONGA_GB_ADDR_CONFIG_GOLDEN
 
- TONGA_PPTABLE_H
 
- TONGA_PP_SMC_H
 
- TONL
 
- TOOLONG
 
- TOOLSTABLE
 
- TOOLS_ARCH_ALPHA_UAPI_ASM_MMAN_FIX_H
 
- TOOLS_ARCH_ARC_UAPI_ASM_MMAN_FIX_H
 
- TOOLS_ARCH_ARM64_UAPI_ASM_MMAN_FIX_H
 
- TOOLS_ARCH_ARM_UAPI_ASM_MMAN_FIX_H
 
- TOOLS_ARCH_H8300_UAPI_ASM_MMAN_FIX_H
 
- TOOLS_ARCH_HEXAGON_UAPI_ASM_MMAN_FIX_H
 
- TOOLS_ARCH_IA64_UAPI_ASM_MMAN_FIX_H
 
- TOOLS_ARCH_MICROBLAZE_UAPI_ASM_MMAN_FIX_H
 
- TOOLS_ARCH_MIPS_UAPI_ASM_MMAN_FIX_H
 
- TOOLS_ARCH_PARISC_UAPI_ASM_MMAN_FIX_H
 
- TOOLS_ARCH_POWERPC_UAPI_ASM_MMAN_FIX_H
 
- TOOLS_ARCH_S390_UAPI_ASM_MMAN_FIX_H
 
- TOOLS_ARCH_SH_UAPI_ASM_MMAN_FIX_H
 
- TOOLS_ARCH_SPARC_UAPI_ASM_MMAN_FIX_H
 
- TOOLS_ARCH_X86_UAPI_ASM_MMAN_FIX_H
 
- TOOLS_ARCH_XTENSA_UAPI_ASM_MMAN_FIX_H
 
- TOOLS_ASM_X86_CMPXCHG_H
 
- TOOLS_VERSION
 
- TOOL_BUF_LEN
 
- TOOL_FOPS_RDWR
 
- TOO_FAR
 
- TOO_MANY_CLOSE
 
- TOO_MANY_OPEN
 
- TOP0_NR_CLK
 
- TOP1_NR_CLK
 
- TOPAZ_ASR_DISABLE
 
- TOPAZ_ASR_REG_OFFSET
 
- TOPAZ_ASR_TOGGLE
 
- TOPAZ_ASSERT_INTX
 
- TOPAZ_CTL_M2L_INT
 
- TOPAZ_CTL_M2L_INT_MASK
 
- TOPAZ_GB_ADDR_CONFIG_GOLDEN
 
- TOPAZ_IPC_IRQ_WORD
 
- TOPAZ_LH_IPC4_INT
 
- TOPAZ_LH_IPC4_INT_MASK
 
- TOPAZ_PCIE_CFG0_OFFSET
 
- TOPAZ_RC_CTRL_IRQ
 
- TOPAZ_RC_PM_EP_IRQ
 
- TOPAZ_RC_RST_EP_IRQ
 
- TOPAZ_RC_RX_DONE_IRQ
 
- TOPAZ_RC_TX_DONE_IRQ
 
- TOPAZ_RC_TX_STOP_IRQ
 
- TOPAZ_TX_BD_SIZE_DEFAULT
 
- TOPA_ENTRY
 
- TOPA_ENTRY_PAGES
 
- TOPA_ENTRY_SIZE
 
- TOPA_PMI_MARGIN
 
- TOPA_SHIFT
 
- TOPC_NR_CLK
 
- TOPDOWN
 
- TOPHYS
 
- TOPIC97_AUDIO_VIDEO_SWITCH
 
- TOPIC97_AVS_AUDIO_CONTROL
 
- TOPIC97_AVS_VIDEO_CONTROL
 
- TOPIC97_ICR_INTA
 
- TOPIC97_ICR_INTB
 
- TOPIC97_ICR_IRQNP
 
- TOPIC97_ICR_IRQSEL
 
- TOPIC97_ICR_STSIRQNP
 
- TOPIC97_INT_CONTROL
 
- TOPIC97_MISC1
 
- TOPIC97_MISC1_CLOCKRUN_ENABLE
 
- TOPIC97_MISC1_CLOCKRUN_MODE
 
- TOPIC97_MISC1_DETECT_REQ_ENA
 
- TOPIC97_MISC1_R2_LOW_ENABLE
 
- TOPIC97_MISC1_SCK_CLEAR_DIS
 
- TOPIC97_MISC2
 
- TOPIC97_MISC2_SPWRCLK_MASK
 
- TOPIC97_MISC2_SPWRMOD
 
- TOPIC97_MISC2_SPWR_ENABLE
 
- TOPIC97_MISC2_ZV_ENABLE
 
- TOPIC97_MISC2_ZV_MODE
 
- TOPIC97_RCR_CAUDIO_OFF
 
- TOPIC97_RCR_CB_DEV_MASK
 
- TOPIC97_RCR_CB_DEV_SHIFT
 
- TOPIC97_RCR_CLKRUN_ENA
 
- TOPIC97_RCR_IOPLUP
 
- TOPIC97_RCR_RI_DISABLE
 
- TOPIC97_RCR_TESTMODE
 
- TOPIC97_ZOOM_VIDEO_CONTROL
 
- TOPIC97_ZV_CONTROL_ENABLE
 
- TOPIC_CARD_CONTROL
 
- TOPIC_CARD_DETECT
 
- TOPIC_CCR_CCLK
 
- TOPIC_CCR_CLOCK
 
- TOPIC_CCR_INTA
 
- TOPIC_CCR_INTB
 
- TOPIC_CCR_PCICLK
 
- TOPIC_CCR_PCICLK_2
 
- TOPIC_CDR_MODE_PC32
 
- TOPIC_CDR_SW_DETECT
 
- TOPIC_CDR_VS1
 
- TOPIC_CDR_VS2
 
- TOPIC_EXCA_IFC_33V_ENA
 
- TOPIC_EXCA_IF_CONTROL
 
- TOPIC_PCI_CFG_PPBCN
 
- TOPIC_PCI_CFG_PPBCN_WBEN
 
- TOPIC_RCR_BUFOFF_PWROFF
 
- TOPIC_RCR_BUFOFF_SIGOFF
 
- TOPIC_RCR_CAUDIO_INVERT
 
- TOPIC_RCR_REMOVE_RESET
 
- TOPIC_RCR_RESUME_RESET
 
- TOPIC_REGISTER_CONTROL
 
- TOPIC_SCR_IRQSEL
 
- TOPIC_SLOT_CONTROL
 
- TOPIC_SLOT_ID_LOCK
 
- TOPIC_SLOT_ID_WP
 
- TOPIC_SLOT_OFS_MASK
 
- TOPIC_SLOT_PORT_MASK
 
- TOPIC_SLOT_PORT_SHIFT
 
- TOPIC_SLOT_SLOTEN
 
- TOPIC_SLOT_SLOTON
 
- TOPIC_SOCKET_CONTROL
 
- TOPLEVEL
 
- TOPOLOGY
 
- TOPOLOGY_CORE_BITS
 
- TOPOLOGY_DEF_TIMER_SECS
 
- TOPOLOGY_MODE_HW
 
- TOPOLOGY_MODE_PACKAGE
 
- TOPOLOGY_MODE_SINGLE
 
- TOPOLOGY_MODE_UNINITIALIZED
 
- TOPOLOGY_NR_MAG
 
- TOPOLOGY_REGISTER_OFFSET
 
- TOPOLOGY_SD_FLAGS
 
- TOPO_F
 
- TOPO_FL
 
- TOPO_MASK
 
- TOPO_N2N
 
- TOPSTAR_LAPTOP_CLASS
 
- TOPSW_LSBUS
 
- TOPSW_MAIN
 
- TOPSYS_INT
 
- TOPSYS_IRQ_LOWSYS_INT
 
- TOPSYS_IRQ_T120C_INT
 
- TOPSYS_IRQ_T140C_INT
 
- TOPTREE_ID_NUMA
 
- TOPTREE_ID_PHYS
 
- TOP_BOTTOM_END_POINT_DEAVTIVALION_LEVEL
 
- TOP_CHIP_REV_ID_REG
 
- TOP_CLIP
 
- TOP_CLK_CTL_A_MCLK2_EN_ENABLE
 
- TOP_CLK_CTL_A_MCLK_EN_ENABLE
 
- TOP_CLK_CTL_A_MCLK_MCLK2_EN_MASK
 
- TOP_CLK_DIV0
 
- TOP_CLK_GATE0
 
- TOP_CLK_GATE1
 
- TOP_CLK_GATE2
 
- TOP_CLK_GATE3
 
- TOP_CLK_GATE4
 
- TOP_CLK_GATE5
 
- TOP_CLK_GATE6
 
- TOP_CLK_MUX0
 
- TOP_CLK_MUX1
 
- TOP_CLK_MUX2
 
- TOP_CLK_MUX3
 
- TOP_CLK_MUX4
 
- TOP_CLK_MUX5
 
- TOP_CLK_MUX6
 
- TOP_CLK_MUX7
 
- TOP_CLK_MUX9
 
- TOP_CONFIG_INTER_BTM
 
- TOP_CONFIG_INTER_TOP
 
- TOP_CONFIG_PROGRESSIVE
 
- TOP_CONTROL
 
- TOP_CTL_DIG_MCLK_FREQ_F_12_288MHZ
 
- TOP_CTL_DIG_MCLK_FREQ_F_9_6MHZ
 
- TOP_CTL_DIG_MCLK_FREQ_MASK
 
- TOP_DOUTTOP__SCLK_HPM_TARGETCLK
 
- TOP_DOUT_ACLK_BUS1_100
 
- TOP_DOUT_ACLK_BUS1_400
 
- TOP_DOUT_ACLK_BUS2_100
 
- TOP_DOUT_ACLK_BUS2_400
 
- TOP_DOUT_ACLK_BUS3_100
 
- TOP_DOUT_ACLK_BUS3_400
 
- TOP_DOUT_ACLK_BUS4_100
 
- TOP_DOUT_ACLK_BUS4_400
 
- TOP_DOUT_ACLK_DISP_222
 
- TOP_DOUT_ACLK_DISP_333
 
- TOP_DOUT_ACLK_FSYS_200
 
- TOP_DOUT_ACLK_G2D_333
 
- TOP_DOUT_ACLK_GSCL_333
 
- TOP_DOUT_ACLK_GSCL_400
 
- TOP_DOUT_ACLK_GSCL_FIMC
 
- TOP_DOUT_ACLK_ISP1_266
 
- TOP_DOUT_ACLK_ISP1_400
 
- TOP_DOUT_ACLK_MFC_333
 
- TOP_DOUT_ACLK_PERI_66
 
- TOP_DOUT_ACLK_PERI_AUD
 
- TOP_DOUT_SCLK_DISP_PIXEL
 
- TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_A
 
- TOP_DOUT_SCLK_FSYS_MMC0_SDCLKIN_B
 
- TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_A
 
- TOP_DOUT_SCLK_FSYS_MMC1_SDCLKIN_B
 
- TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_A
 
- TOP_DOUT_SCLK_FSYS_MMC2_SDCLKIN_B
 
- TOP_DOUT_SCLK_FSYS_USBDRD30_SUSPEND_CLK
 
- TOP_DOUT_SCLK_ISP1_SENSOR0_A
 
- TOP_DOUT_SCLK_ISP1_SENSOR0_B
 
- TOP_DOUT_SCLK_ISP1_SENSOR1_A
 
- TOP_DOUT_SCLK_ISP1_SENSOR1_B
 
- TOP_DOUT_SCLK_ISP1_SENSOR2_A
 
- TOP_DOUT_SCLK_ISP1_SENSOR2_B
 
- TOP_DOUT_SCLK_ISP1_SPI0_A
 
- TOP_DOUT_SCLK_ISP1_SPI0_B
 
- TOP_DOUT_SCLK_ISP1_SPI1_A
 
- TOP_DOUT_SCLK_ISP1_SPI1_B
 
- TOP_DOUT_SCLK_ISP1_UART
 
- TOP_DOUT_SCLK_PERI_SPI0_A
 
- TOP_DOUT_SCLK_PERI_SPI0_B
 
- TOP_DOUT_SCLK_PERI_SPI1_A
 
- TOP_DOUT_SCLK_PERI_SPI1_B
 
- TOP_DOUT_SCLK_PERI_SPI2_A
 
- TOP_DOUT_SCLK_PERI_SPI2_B
 
- TOP_DOUT_SCLK_PERI_UART0
 
- TOP_DOUT_SCLK_PERI_UART1
 
- TOP_DOUT_SCLK_PERI_UART2
 
- TOP_EDGE
 
- TOP_END_POINT_DETECTION_LEVEL
 
- TOP_FN0_CCCR_REG_32
 
- TOP_FOUT_AUD_PLL
 
- TOP_FOUT_DISP_PLL
 
- TOP_HB
 
- TOP_IOVB
 
- TOP_LB
 
- TOP_LEVEL_CONTAINER
 
- TOP_LEVEL_TRACE_FLAGS
 
- TOP_MEM_FORMAT_DFLT
 
- TOP_MOUT_ACLK_DISP_222
 
- TOP_MOUT_ACLK_DISP_333
 
- TOP_MOUT_ACLK_G2D_333
 
- TOP_MOUT_ACLK_GSCL_333
 
- TOP_MOUT_ACLK_GSCL_400
 
- TOP_MOUT_ACLK_GSCL_FIMC
 
- TOP_MOUT_ACLK_ISP1_266
 
- TOP_MOUT_ACLK_ISP1_400
 
- TOP_MOUT_ACLK_MFC_333
 
- TOP_MOUT_AUDTOP_PLL_USER
 
- TOP_MOUT_AUD_PLL
 
- TOP_MOUT_BUS1_BUSTOP_100
 
- TOP_MOUT_BUS1_BUSTOP_400
 
- TOP_MOUT_BUS2_BUSTOP_100
 
- TOP_MOUT_BUS2_BUSTOP_400
 
- TOP_MOUT_BUS3_BUSTOP_100
 
- TOP_MOUT_BUS3_BUSTOP_400
 
- TOP_MOUT_BUS4_BUSTOP_100
 
- TOP_MOUT_BUS4_BUSTOP_400
 
- TOP_MOUT_BUSTOP_PLL_USER
 
- TOP_MOUT_DISP_DISP_222
 
- TOP_MOUT_DISP_DISP_333
 
- TOP_MOUT_DISP_MEDIA_PIXEL
 
- TOP_MOUT_DISP_PLL
 
- TOP_MOUT_FIMD1
 
- TOP_MOUT_G2D_BUSTOP_333
 
- TOP_MOUT_GSCL_BUSTOP_333
 
- TOP_MOUT_GSCL_BUSTOP_FIMC
 
- TOP_MOUT_ISP1_MEDIA_266
 
- TOP_MOUT_ISP1_MEDIA_400
 
- TOP_MOUT_M2M_MEDIATOP_400
 
- TOP_MOUT_MEDIATOP_PLL_USER
 
- TOP_MOUT_MEMTOP_PLL_USER
 
- TOP_MOUT_MFC_BUSTOP_333
 
- TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_A
 
- TOP_MOUT_SCLK_FSYS_MMC0_SDCLKIN_B
 
- TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_A
 
- TOP_MOUT_SCLK_FSYS_MMC1_SDCLKIN_B
 
- TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_A
 
- TOP_MOUT_SCLK_FSYS_MMC2_SDCLKIN_B
 
- TOP_MOUT_SCLK_FSYS_USB
 
- TOP_MOUT_SCLK_ISP1_SENSOR0
 
- TOP_MOUT_SCLK_ISP1_SENSOR1
 
- TOP_MOUT_SCLK_ISP1_SENSOR2
 
- TOP_MOUT_SCLK_ISP1_SPI0
 
- TOP_MOUT_SCLK_ISP1_SPI1
 
- TOP_MOUT_SCLK_ISP1_UART
 
- TOP_MOUT_SCLK_PERI_SPI0_CLK
 
- TOP_MOUT_SCLK_PERI_SPI1_CLK
 
- TOP_MOUT_SCLK_PERI_SPI2_CLK
 
- TOP_MOUT_SCLK_PERI_UART0_UCLK
 
- TOP_MOUT_SCLK_PERI_UART1_UCLK
 
- TOP_MOUT_SCLK_PERI_UART2_UCLK
 
- TOP_MUX
 
- TOP_NR_CLK
 
- TOP_NR_CLKS
 
- TOP_OF_INIT_STACK
 
- TOP_OF_KERNEL_STACK_PADDING
 
- TOP_PD
 
- TOP_PIN
 
- TOP_PRIORITY
 
- TOP_PTE
 
- TOP_RATE_11M
 
- TOP_RATE_12M
 
- TOP_RATE_18M
 
- TOP_RATE_1M
 
- TOP_RATE_24M
 
- TOP_RATE_2M
 
- TOP_RATE_36M
 
- TOP_RATE_48M
 
- TOP_RATE_54M
 
- TOP_RATE_55M
 
- TOP_RATE_6M
 
- TOP_RATE_9M
 
- TOP_REG
 
- TOP_REG0
 
- TOP_REG1
 
- TOP_REG2
 
- TOP_REG3
 
- TOP_REG4
 
- TOP_REG5
 
- TOP_REG6
 
- TOP_REG7
 
- TOP_REG8
 
- TOP_ROM_TABLE_MAX_OFFSET
 
- TOP_ROM_TABLE_SECTION
 
- TOP_SB
 
- TOP_SCLK_FIMD1
 
- TOP_SCLK_MMC0
 
- TOP_SCLK_MMC1
 
- TOP_SCLK_MMC2
 
- TOP_SIG_CTRL_NORMAL
 
- TOP_SPARE2
 
- TOP_SRV
 
- TOP_TO_BOTTOM
 
- TOR
 
- TORCH
 
- TORCH_EN_SHIFT
 
- TORCH_INTENSITY
 
- TORCH_IOUT1_SHIFT
 
- TORCH_IOUT2_SHIFT
 
- TORCH_IOUT_MASK
 
- TORCH_IOUT_MAX
 
- TORCH_IOUT_MIN
 
- TORCH_IOUT_STEP
 
- TORCH_I_MASK
 
- TORCH_I_SHIFT
 
- TORCH_PIN_EN_MASK
 
- TORCH_PIN_EN_SHIFT
 
- TORCH_RAMP_DN_TIME_MASK
 
- TORCH_RAMP_DN_TIME_SHIFT
 
- TORCH_RAMP_UP_TIME_MASK
 
- TORCH_RAMP_UP_TIME_SHIFT
 
- TORCH_TIMEOUT_MAX
 
- TORCH_TIMEOUT_MIN
 
- TORCH_TMR_NO_TIMER
 
- TOROUT_STRING
 
- TORTURE_FLAG
 
- TORTURE_RANDOM_ADD
 
- TORTURE_RANDOM_MULT
 
- TORTURE_RANDOM_REFRESH
 
- TOS1900_FN_SCAN
 
- TOSA_BT_H
 
- TOSA_CF_PHYS
 
- TOSA_GAFR_ALL_SENSE_BIT
 
- TOSA_GAFR_HIGH_STROBE_BIT
 
- TOSA_GAFR_LOW_STROBE_BIT
 
- TOSA_GPIO_AC_IN
 
- TOSA_GPIO_ALL_SENSE_BIT
 
- TOSA_GPIO_ALL_SENSE_RSHIFT
 
- TOSA_GPIO_BAT0_CRG
 
- TOSA_GPIO_BAT0_LOW
 
- TOSA_GPIO_BAT0_TH_ON
 
- TOSA_GPIO_BAT0_V_ON
 
- TOSA_GPIO_BAT1_CRG
 
- TOSA_GPIO_BAT1_LOW
 
- TOSA_GPIO_BAT1_TH_ON
 
- TOSA_GPIO_BAT1_V_ON
 
- TOSA_GPIO_BAT_LOCKED
 
- TOSA_GPIO_BAT_SW_ON
 
- TOSA_GPIO_BL_C20MA
 
- TOSA_GPIO_BT_LED
 
- TOSA_GPIO_BT_PWR_EN
 
- TOSA_GPIO_BT_RESET
 
- TOSA_GPIO_BU_CHRG_ON
 
- TOSA_GPIO_CARD_VCC_ON
 
- TOSA_GPIO_CF_CD
 
- TOSA_GPIO_CF_IRQ
 
- TOSA_GPIO_CHARGE_OFF
 
- TOSA_GPIO_CHARGE_OFF_JC
 
- TOSA_GPIO_CHRG_ERR_LED
 
- TOSA_GPIO_EAR_IN
 
- TOSA_GPIO_HIGH_STROBE_BIT
 
- TOSA_GPIO_HP_IN
 
- TOSA_GPIO_IRDA_TX
 
- TOSA_GPIO_IR_POWERDWN
 
- TOSA_GPIO_JACKET_DETECT
 
- TOSA_GPIO_JC_CF_IRQ
 
- TOSA_GPIO_KEY_SENSE
 
- TOSA_GPIO_KEY_STROBE
 
- TOSA_GPIO_LOW_STROBE_BIT
 
- TOSA_GPIO_L_MUTE
 
- TOSA_GPIO_MAIN_BAT_LOW
 
- TOSA_GPIO_NOTE_LED
 
- TOSA_GPIO_ON_KEY
 
- TOSA_GPIO_ON_RESET
 
- TOSA_GPIO_POWERON
 
- TOSA_GPIO_PWR_ON
 
- TOSA_GPIO_RECORD_BTN
 
- TOSA_GPIO_RESET
 
- TOSA_GPIO_SD_WP
 
- TOSA_GPIO_SENSE_BIT
 
- TOSA_GPIO_STROBE_BIT
 
- TOSA_GPIO_SYNC
 
- TOSA_GPIO_TC6393XB_CLK
 
- TOSA_GPIO_TC6393XB_INT
 
- TOSA_GPIO_TC6393XB_L3V_ON
 
- TOSA_GPIO_TC6393XB_RDY
 
- TOSA_GPIO_TC6393XB_REST_IN
 
- TOSA_GPIO_TC6393XB_SUSPEND
 
- TOSA_GPIO_TG_ON
 
- TOSA_GPIO_TG_SPI_CS
 
- TOSA_GPIO_TG_SPI_MOSI
 
- TOSA_GPIO_TG_SPI_SCLK
 
- TOSA_GPIO_TP_INT
 
- TOSA_GPIO_USB_IN
 
- TOSA_GPIO_USB_PULLUP
 
- TOSA_GPIO_VGA_LINE
 
- TOSA_GPIO_WLAN_LED
 
- TOSA_GPIO_nSD_DETECT
 
- TOSA_GPIO_nSD_INT
 
- TOSA_HEADSET
 
- TOSA_HP
 
- TOSA_HP_OFF
 
- TOSA_IRQ_GPIO_AC_IN
 
- TOSA_IRQ_GPIO_BAT0_CRG
 
- TOSA_IRQ_GPIO_BAT0_LOW
 
- TOSA_IRQ_GPIO_BAT1_CRG
 
- TOSA_IRQ_GPIO_BAT1_LOW
 
- TOSA_IRQ_GPIO_BAT_LOCKED
 
- TOSA_IRQ_GPIO_CF_CD
 
- TOSA_IRQ_GPIO_CF_IRQ
 
- TOSA_IRQ_GPIO_EAR_IN
 
- TOSA_IRQ_GPIO_JACKET_DETECT
 
- TOSA_IRQ_GPIO_JC_CF_IRQ
 
- TOSA_IRQ_GPIO_KEY_SENSE
 
- TOSA_IRQ_GPIO_MAIN_BAT_LOW
 
- TOSA_IRQ_GPIO_ON_KEY
 
- TOSA_IRQ_GPIO_RECORD_BTN
 
- TOSA_IRQ_GPIO_SYNC
 
- TOSA_IRQ_GPIO_TC6393XB_INT
 
- TOSA_IRQ_GPIO_TP_INT
 
- TOSA_IRQ_GPIO_USB_IN
 
- TOSA_IRQ_GPIO_VGA_LINE
 
- TOSA_IRQ_GPIO_WAKEUP
 
- TOSA_IRQ_GPIO_nSD_DETECT
 
- TOSA_IRQ_GPIO_nSD_INT
 
- TOSA_KEY_ADDRESSBOOK
 
- TOSA_KEY_CALENDAR
 
- TOSA_KEY_CANCEL
 
- TOSA_KEY_CENTER
 
- TOSA_KEY_FN
 
- TOSA_KEY_HOMEPAGE
 
- TOSA_KEY_LIGHT
 
- TOSA_KEY_MAIL
 
- TOSA_KEY_MENU
 
- TOSA_KEY_OK
 
- TOSA_KEY_RECORD
 
- TOSA_KEY_SENSE_NUM
 
- TOSA_KEY_STROBE_NUM
 
- TOSA_KEY_SYNC
 
- TOSA_LCDC_PHYS
 
- TOSA_MIC_INT
 
- TOSA_NR_IRQS
 
- TOSA_SCOOP_AC_IN_OL
 
- TOSA_SCOOP_AUD_PWR_ON
 
- TOSA_SCOOP_GPIO_BASE
 
- TOSA_SCOOP_IO_DIR
 
- TOSA_SCOOP_JC_CARD_LIMIT_SEL
 
- TOSA_SCOOP_JC_GPIO_BASE
 
- TOSA_SCOOP_JC_IO_DIR
 
- TOSA_SCOOP_JC_WLAN_DETECT
 
- TOSA_SCOOP_PHYS
 
- TOSA_SCOOP_PXA_VCORE1
 
- TOSA_SPK_OFF
 
- TOSA_SPK_ON
 
- TOSA_TC6393XB_GPIO_BASE
 
- TOSHIBA_ACPI_DEVICE
 
- TOSHIBA_ACPI_PROC
 
- TOSHIBA_ACPI_SCI
 
- TOSHIBA_ACPI_VERSION
 
- TOSHIBA_DMID
 
- TOSHIBA_ES2_BRIDGE_DPID
 
- TOSHIBA_ES3_APBRIDGE_DPID
 
- TOSHIBA_ES3_GBPHY_DPID
 
- TOSHIBA_IIO_ACCEL_CHANNEL
 
- TOSHIBA_NAND_ID4_IS_BENAND
 
- TOSHIBA_NAND_STATUS_REWRITE_RECOMMENDED
 
- TOSHIBA_PRODUCT_G450
 
- TOSHIBA_PRODUCT_HSDPA_MINICARD
 
- TOSHIBA_RBTX4927_IOC_NAME
 
- TOSHIBA_RBTX4938_IOC_NAME
 
- TOSHIBA_VENDOR_ID
 
- TOSHIBA_WMI_EVENT_GUID
 
- TOSH_DEBUG
 
- TOSH_DEVICE
 
- TOSH_MINOR_DEV
 
- TOSH_PROC
 
- TOSH_SMM
 
- TOSH_STATUS_ECC_HAS_BITFLIPS_T
 
- TOSH_VERSION
 
- TOSTOP
 
- TOS_ALREADY_OPEN
 
- TOS_BITWIDTH
 
- TOS_DATA_NOT_AVAILABLE
 
- TOS_F
 
- TOS_FAILURE
 
- TOS_FIFO_EMPTY
 
- TOS_INPUT_DATA_ERROR
 
- TOS_NOT_INITIALIZED
 
- TOS_NOT_INSTALLED
 
- TOS_NOT_OPENED
 
- TOS_NOT_PRESENT
 
- TOS_NOT_SUPPORTED
 
- TOS_OFF
 
- TOS_OPEN_CLOSE_OK
 
- TOS_PRIO_M
 
- TOS_PRIO_S
 
- TOS_S
 
- TOS_SUCCESS
 
- TOS_SUCCESS2
 
- TOS_TO_SL
 
- TOS_V
 
- TOS_WRITE_PROTECTED
 
- TOTALWIDTH
 
- TOTAL_ATTRS
 
- TOTAL_BLKS
 
- TOTAL_CAM_ENTRY
 
- TOTAL_CHANNELS
 
- TOTAL_CHUNKS
 
- TOTAL_CYCLES
 
- TOTAL_DESC
 
- TOTAL_DESCS_NUM
 
- TOTAL_FIX_BTMAPS
 
- TOTAL_FRAME_BW
 
- TOTAL_HW_TX_QUEUES
 
- TOTAL_KSZ8795_COUNTER_NUM
 
- TOTAL_KSZ9477_COUNTER_NUM
 
- TOTAL_MAX_TX_BUFFER
 
- TOTAL_MEM_SIZE
 
- TOTAL_NUMBER_OF_PORTS
 
- TOTAL_NUM_IF_OUTPUT_FREQ
 
- TOTAL_NUM_OF_TASKS_FMAN_V3H
 
- TOTAL_NUM_OF_TASKS_FMAN_V3L
 
- TOTAL_PKT_LEN_INCL_ALIGN
 
- TOTAL_PORT_COUNTER_NUM
 
- TOTAL_PORT_NUM
 
- TOTAL_QUEUE_ENTRIES
 
- TOTAL_RESERVED_PKT_LEN
 
- TOTAL_RESERVED_PKT_LEN_8812
 
- TOTAL_RESERVED_PKT_LEN_8821
 
- TOTAL_RESOURCES
 
- TOTAL_SAMPLES
 
- TOTAL_SEGS
 
- TOTAL_SG_ENTRY
 
- TOTAL_SIZE_CODE
 
- TOTAL_SIZE_GPR
 
- TOTAL_SIZE_TANKMEM_ADDR
 
- TOTAL_SIZE_TANKMEM_DATA
 
- TOTAL_SLOTS
 
- TOTAL_STEPS
 
- TOTAL_SWITCH_COUNTER_NUM
 
- TOTAL_TABLES
 
- TOTAL_TIME_MASK
 
- TOTAL_TIME_SHIFT
 
- TOTAL_TS_NUM
 
- TOTAL_TX_DUMMY_PACKET_SIZE
 
- TOTAL_XOFF_EN
 
- TOTAL_XOFF_THRESHOLD_MASK
 
- TOTAL_XOFF_THRESHOLD_SHIFT
 
- TOTAL_XON_EN
 
- TOTEMPOLE
 
- TOT_BANDS
 
- TOT_REGS
 
- TOU
 
- TOUCAM_HEADER_SIZE
 
- TOUCAM_TRAILER_SIZE
 
- TOUCH
 
- TOUCHKIT_CMD
 
- TOUCHKIT_CMD_ACTIVE
 
- TOUCHKIT_CMD_CONTROLLER_TYPE
 
- TOUCHKIT_CMD_FIRMWARE_VERSION
 
- TOUCHKIT_CMD_LENGTH
 
- TOUCHKIT_GET_TOUCHED
 
- TOUCHKIT_GET_X
 
- TOUCHKIT_GET_Y
 
- TOUCHKIT_MAX_XC
 
- TOUCHKIT_MAX_YC
 
- TOUCHKIT_SEND_PARMS
 
- TOUCHPAD_PORT
 
- TOUCHPAD_RAW_XY_ORIGIN_LOWER_LEFT
 
- TOUCHPAD_RAW_XY_ORIGIN_UPPER_LEFT
 
- TOUCHSCREEN_VCHANNEL1
 
- TOUCHSCREEN_VCHANNEL2
 
- TOUCH_DETECT
 
- TOUCH_DETECT_PULLUP_CONF_REG
 
- TOUCH_DEVICE_ID
 
- TOUCH_ENDPOINT
 
- TOUCH_EVENT_DOWN
 
- TOUCH_EVENT_ON
 
- TOUCH_EVENT_RESERVED
 
- TOUCH_EVENT_UP
 
- TOUCH_FINGER
 
- TOUCH_GESTURE
 
- TOUCH_INDEX
 
- TOUCH_MAGIC
 
- TOUCH_MASK
 
- TOUCH_NONE
 
- TOUCH_PANEL_IRQ
 
- TOUCH_PANEL_IRQ_EDGE
 
- TOUCH_PAN_CALI_EN
 
- TOUCH_PEN
 
- TOUCH_PEN_DETECT_DEBOUNCE_US
 
- TOUCH_PK_OFFSET_EVENT
 
- TOUCH_PK_OFFSET_FNGR_NUM
 
- TOUCH_PK_OFFSET_REPORT_ID
 
- TOUCH_PK_OFFSET_SCAN_TIME
 
- TOUCH_PK_V1_OFFSET_EVENT
 
- TOUCH_PK_V1_OFFSET_FNGR_NUM
 
- TOUCH_PK_V1_OFFSET_REPORT_ID
 
- TOUCH_PK_V1_OFFSET_SCAN_TIME
 
- TOUCH_SAMPLE_PERIOD_US
 
- TOUCH_SAMPLE_PERIOD_US_RL
 
- TOUCH_SCTIM_US
 
- TOUCH_SHTIM
 
- TOUCH_STATE_DRAG
 
- TOUCH_STATE_MASK
 
- TOUCH_STATE_NONE
 
- TOUCH_STATE_START
 
- TOUCH_STATUS_MASK
 
- TOUCH_THRESHOLD
 
- TOUCH_TIMEOUT
 
- TOUCH_TIMEOUT_SHIFT
 
- TOUCH_TWOFINGER
 
- TOUT_MIN
 
- TOUT_OFFSET
 
- TOVR
 
- TOVR_ADDR
 
- TOYOTA388
 
- TOYOTA794
 
- TO_10ms
 
- TO_250ms
 
- TO_290ms
 
- TO_4ms
 
- TO_5ms
 
- TO_ACCEPT1_FLAG
 
- TO_ACCEPT2_FLAG
 
- TO_ACP_I2S_1
 
- TO_ACP_I2S_2
 
- TO_ALT_FW
 
- TO_ARB
 
- TO_ASSIGN
 
- TO_ATTR_NO
 
- TO_AXIE
 
- TO_BAD
 
- TO_BE_SENT
 
- TO_BE_SUBMITTED
 
- TO_BLOCK
 
- TO_BLUETOOTH
 
- TO_BOOT
 
- TO_BRIGHT
 
- TO_BSB
 
- TO_BSF
 
- TO_CAC
 
- TO_CLK_DIVISION
 
- TO_CLK_MGR_INTERNAL
 
- TO_CORE_ID
 
- TO_CRYPT_OFF
 
- TO_CRYPT_ON
 
- TO_CS_QUEUE_NR
 
- TO_CYCLES
 
- TO_CYCLES64
 
- TO_DCE110_CLK_SRC
 
- TO_DCE110_COMPRESSOR
 
- TO_DCE110_LINK_ENC
 
- TO_DCE110_OPP
 
- TO_DCE110_RES_POOL
 
- TO_DCE112_COMPRESSOR
 
- TO_DCE_ABM
 
- TO_DCE_CLK_MGR
 
- TO_DCE_DMCU
 
- TO_DCE_IPP
 
- TO_DCE_MEM_INPUT
 
- TO_DCE_TRANSFORM
 
- TO_DCN10_DPP
 
- TO_DCN10_DWBC
 
- TO_DCN10_HUBBUB
 
- TO_DCN10_HUBP
 
- TO_DCN10_IPP
 
- TO_DCN10_LINK_ENC
 
- TO_DCN10_MPC
 
- TO_DCN10_OPP
 
- TO_DCN10_RES_POOL
 
- TO_DCN20_DPP
 
- TO_DCN20_DSC
 
- TO_DCN20_DWBC
 
- TO_DCN20_HUBBUB
 
- TO_DCN20_HUBP
 
- TO_DCN20_MMHUBBUB
 
- TO_DCN20_MPC
 
- TO_DCN20_OPP
 
- TO_DCN20_RES_POOL
 
- TO_DCN21_HUBP
 
- TO_DCN21_RES_POOL
 
- TO_DCN_DCCG
 
- TO_DEFAULT_COMMAND
 
- TO_DIS
 
- TO_DISPC_T
 
- TO_DM_AUX
 
- TO_DOWNLOAD_GET_BUSY
 
- TO_DOWNLOAD_GET_READY
 
- TO_DSE
 
- TO_DSI_T
 
- TO_DW0_ENDPOINT
 
- TO_DW0_LENGTH
 
- TO_DW0_MAXPACKET
 
- TO_DW0_MULTI
 
- TO_DW1_DEVICE_ADDR
 
- TO_DW1_HUB_NUM
 
- TO_DW1_PID_TOKEN
 
- TO_DW1_PORT_NUM
 
- TO_DW2_DATA_START_ADDR
 
- TO_DW2_RL
 
- TO_DW3_CERR
 
- TO_DW3_DATA_TOGGLE
 
- TO_DW3_NAKCOUNT
 
- TO_DW3_PING
 
- TO_EUA
 
- TO_FSB
 
- TO_FSF
 
- TO_GET_READY
 
- TO_GOOD
 
- TO_HEAD
 
- TO_HEAD_SIZE
 
- TO_HOST_BUFFER_REQUEST_FAIL
 
- TO_HOST_ID
 
- TO_HOST_INVALID_PACKET
 
- TO_HOST_PORT_CLOSE
 
- TO_HOST_RESULT
 
- TO_HSPEC
 
- TO_HWIRQ
 
- TO_IC
 
- TO_INF
 
- TO_KB
 
- TO_KEKL_QUERY
 
- TO_KEKL_SET
 
- TO_LBL
 
- TO_LEVEL
 
- TO_LOAD
 
- TO_MASK
 
- TO_MB
 
- TO_MCELSIUS
 
- TO_MF
 
- TO_MSEN
 
- TO_MSG
 
- TO_MSPEC
 
- TO_NATIVE
 
- TO_NCSI_DEV_PRIV
 
- TO_NODE
 
- TO_NODE_ADDRSPACE
 
- TO_NODE_CAC
 
- TO_NODE_HSPEC
 
- TO_NODE_MSPEC
 
- TO_NODE_UNCAC
 
- TO_NOP
 
- TO_PHYS
 
- TO_PHYS_MASK
 
- TO_PT
 
- TO_QUEUE_NR
 
- TO_RA
 
- TO_RAXI_AOUTSTDCAPB
 
- TO_RAXI_BEN
 
- TO_RAXI_BOUTSTDCAPB
 
- TO_RBA
 
- TO_RBI
 
- TO_RDC
 
- TO_READ_ATTMSG
 
- TO_READ_CONFIG
 
- TO_READ_FROM_IRQ
 
- TO_REW
 
- TO_RFO
 
- TO_RUN
 
- TO_SA
 
- TO_SAS_TASK
 
- TO_SBA
 
- TO_SCL
 
- TO_SF
 
- TO_SFE
 
- TO_SIGNED48
 
- TO_SIZE
 
- TO_SPRD_HOST
 
- TO_STR
 
- TO_SYNCREG
 
- TO_TBU_DOUTSTDCAPB
 
- TO_TRACE_CHAN_ID
 
- TO_UNASSIGN
 
- TO_UNCAC
 
- TO_UNSIGNED48
 
- TO_US
 
- TO_VLAN
 
- TO_WAXI_OUTSTDCAPB
 
- TO_WRI
 
- TO_WRITE_GET_READY
 
- TO_WTM
 
- TO_XFER_BUF
 
- TO_xAXI_AxQOS
 
- TO_xAXI_BURSTLEN
 
- TO_xAXI_ORD
 
- TP
 
- TP0_OFFSET
 
- TP1000_SPDWN_EN
 
- TP100_SPDWN_EN
 
- TP33_CLK_MARK
 
- TP33_CTRL_MARK
 
- TP33_DATA0_MARK
 
- TP33_DATA10_MARK
 
- TP33_DATA11_MARK
 
- TP33_DATA12_MARK
 
- TP33_DATA13_MARK
 
- TP33_DATA14_MARK
 
- TP33_DATA15_MARK
 
- TP33_DATA1_MARK
 
- TP33_DATA2_MARK
 
- TP33_DATA3_MARK
 
- TP33_DATA4_MARK
 
- TP33_DATA5_MARK
 
- TP33_DATA6_MARK
 
- TP33_DATA7_MARK
 
- TP33_DATA8_MARK
 
- TP33_DATA9_MARK
 
- TP500_SPDWN_EN
 
- TP6800_R10_SIF_TYPE
 
- TP6800_R11_SIF_CONTROL
 
- TP6800_R12_SIF_ADDR_S
 
- TP6800_R13_SIF_TX_DATA
 
- TP6800_R14_SIF_RX_DATA
 
- TP6800_R15_GPIO_PU
 
- TP6800_R16_GPIO_PD
 
- TP6800_R17_GPIO_IO
 
- TP6800_R18_GPIO_DATA
 
- TP6800_R19_SIF_ADDR_S2
 
- TP6800_R1A_SIF_TX_DATA2
 
- TP6800_R1B_SIF_RX_DATA2
 
- TP6800_R21_ENDP_1_CTL
 
- TP6800_R2F_TIMING_CFG
 
- TP6800_R30_SENSOR_CFG
 
- TP6800_R31_PIXEL_START
 
- TP6800_R32_PIXEL_END_L
 
- TP6800_R33_PIXEL_END_H
 
- TP6800_R34_LINE_START
 
- TP6800_R35_LINE_END_L
 
- TP6800_R36_LINE_END_H
 
- TP6800_R37_FRONT_DARK_ST
 
- TP6800_R38_FRONT_DARK_END
 
- TP6800_R39_REAR_DARK_ST_L
 
- TP6800_R3A_REAR_DARK_ST_H
 
- TP6800_R3B_REAR_DARK_END_L
 
- TP6800_R3C_REAR_DARK_END_H
 
- TP6800_R3D_HORIZ_DARK_LINE_L
 
- TP6800_R3E_HORIZ_DARK_LINE_H
 
- TP6800_R3F_FRAME_RATE
 
- TP6800_R50
 
- TP6800_R51
 
- TP6800_R52
 
- TP6800_R53
 
- TP6800_R54_DARK_CFG
 
- TP6800_R55_GAMMA_R
 
- TP6800_R56_GAMMA_G
 
- TP6800_R57_GAMMA_B
 
- TP6800_R5C_EDGE_THRLD
 
- TP6800_R5D_DEMOSAIC_CFG
 
- TP6800_R78_FORMAT
 
- TP6800_R79_QUALITY
 
- TP6800_R7A_BLK_THRLD
 
- TPA6130A2
 
- TPA6130A2_HIZ_L
 
- TPA6130A2_HIZ_R
 
- TPA6130A2_HP_EN_L
 
- TPA6130A2_HP_EN_L_SHIFT
 
- TPA6130A2_HP_EN_R
 
- TPA6130A2_HP_EN_R_SHIFT
 
- TPA6130A2_MODE
 
- TPA6130A2_MODE_BRIDGE
 
- TPA6130A2_MODE_DUAL_MONO
 
- TPA6130A2_MODE_MASK
 
- TPA6130A2_MODE_STEREO
 
- TPA6130A2_MUTE_L
 
- TPA6130A2_MUTE_R
 
- TPA6130A2_PLAT_H
 
- TPA6130A2_REG_CONTROL
 
- TPA6130A2_REG_OUT_IMPEDANCE
 
- TPA6130A2_REG_VERSION
 
- TPA6130A2_REG_VOL_MUTE
 
- TPA6130A2_SWS
 
- TPA6130A2_SWS_SHIFT
 
- TPA6130A2_TERMAL
 
- TPA6130A2_VERSION_MASK
 
- TPA6130A2_VOLUME
 
- TPA6140A2
 
- TPACKET2_HDRLEN
 
- TPACKET3_HDRLEN
 
- TPACKET_ALIGN
 
- TPACKET_ALIGNMENT
 
- TPACKET_HDRLEN
 
- TPACKET_V1
 
- TPACKET_V2
 
- TPACKET_V3
 
- TPACPI_ACPIHANDLE_INIT
 
- TPACPI_ACPI_EC_HID
 
- TPACPI_ACPI_EVENT_PREFIX
 
- TPACPI_ACPI_IBM_HKEY_HID
 
- TPACPI_ACPI_LENOVO_HKEY_HID
 
- TPACPI_ACPI_LENOVO_HKEY_V2_HID
 
- TPACPI_ALSA_DRVNAME
 
- TPACPI_ALSA_MIXERNAME
 
- TPACPI_ALSA_SHRTNAME
 
- TPACPI_BACKLIGHT_DEV_NAME
 
- TPACPI_BEEP_Q1
 
- TPACPI_BRGHT_MODE_AUTO
 
- TPACPI_BRGHT_MODE_EC
 
- TPACPI_BRGHT_MODE_ECNVRAM
 
- TPACPI_BRGHT_MODE_MAX
 
- TPACPI_BRGHT_MODE_UCMS_STEP
 
- TPACPI_BRGHT_Q_ASK
 
- TPACPI_BRGHT_Q_EC
 
- TPACPI_BRGHT_Q_NOEC
 
- TPACPI_COMPARE_KEY
 
- TPACPI_DBG_ALL
 
- TPACPI_DBG_BRGHT
 
- TPACPI_DBG_DISCLOSETASK
 
- TPACPI_DBG_EXIT
 
- TPACPI_DBG_FAN
 
- TPACPI_DBG_HKEY
 
- TPACPI_DBG_INIT
 
- TPACPI_DBG_MIXER
 
- TPACPI_DBG_RFKILL
 
- TPACPI_DESC
 
- TPACPI_DRVR_NAME
 
- TPACPI_DRVR_SHORTNAME
 
- TPACPI_FAN_2FAN
 
- TPACPI_FAN_CMD_ENABLE
 
- TPACPI_FAN_CMD_LEVEL
 
- TPACPI_FAN_CMD_SPEED
 
- TPACPI_FAN_LAST_LEVEL
 
- TPACPI_FAN_NONE
 
- TPACPI_FAN_Q1
 
- TPACPI_FAN_RD_ACPI_GFAN
 
- TPACPI_FAN_RD_TPEC
 
- TPACPI_FAN_WR_ACPI_FANS
 
- TPACPI_FAN_WR_ACPI_SFAN
 
- TPACPI_FAN_WR_NONE
 
- TPACPI_FAN_WR_TPEC
 
- TPACPI_FILE
 
- TPACPI_HANDLE
 
- TPACPI_HKEY_INPUT_PRODUCT
 
- TPACPI_HKEY_INPUT_VERSION
 
- TPACPI_HKEY_NVRAM_GOOD_MASK
 
- TPACPI_HKEY_NVRAM_KNOWN_MASK
 
- TPACPI_HK_Q_INIMASK
 
- TPACPI_HOTKEY_MAP_LEN
 
- TPACPI_HOTKEY_MAP_SIZE
 
- TPACPI_HOTKEY_MAP_TYPESIZE
 
- TPACPI_HWMON_DRVR_NAME
 
- TPACPI_KEYMAP_IBM_GENERIC
 
- TPACPI_KEYMAP_LENOVO_GENERIC
 
- TPACPI_LED_570
 
- TPACPI_LED_BLINK
 
- TPACPI_LED_EC_HLBL
 
- TPACPI_LED_EC_HLCL
 
- TPACPI_LED_EC_HLMS
 
- TPACPI_LED_MAX
 
- TPACPI_LED_NEW
 
- TPACPI_LED_NONE
 
- TPACPI_LED_NUMLEDS
 
- TPACPI_LED_OFF
 
- TPACPI_LED_OLD
 
- TPACPI_LED_ON
 
- TPACPI_LIFE_EXITING
 
- TPACPI_LIFE_INIT
 
- TPACPI_LIFE_RUNNING
 
- TPACPI_MAIL
 
- TPACPI_MATCH_ANY
 
- TPACPI_MATCH_ANY_VERSION
 
- TPACPI_MATCH_UNKNOWN
 
- TPACPI_MAX_ACPI_ARGS
 
- TPACPI_MAX_THERMAL_SENSORS
 
- TPACPI_MAY_SEND_KEY
 
- TPACPI_NAME
 
- TPACPI_NVRAM_KTHREAD_NAME
 
- TPACPI_PARAM
 
- TPACPI_PROC_DIR
 
- TPACPI_QEC_IBM
 
- TPACPI_QEC_LNV
 
- TPACPI_Q_IBM
 
- TPACPI_Q_LNV
 
- TPACPI_Q_LNV3
 
- TPACPI_RFK_BLUETOOTH_SW_ID
 
- TPACPI_RFK_BLUETOOTH_SW_NAME
 
- TPACPI_RFK_RADIO_OFF
 
- TPACPI_RFK_RADIO_ON
 
- TPACPI_RFK_SW_MAX
 
- TPACPI_RFK_UWB_SW_ID
 
- TPACPI_RFK_UWB_SW_NAME
 
- TPACPI_RFK_WWAN_SW_ID
 
- TPACPI_RFK_WWAN_SW_NAME
 
- TPACPI_SAFE_LEDS
 
- TPACPI_SYSFS_VERSION
 
- TPACPI_THERMAL_ACPI_TMP07
 
- TPACPI_THERMAL_ACPI_UPDT
 
- TPACPI_THERMAL_NONE
 
- TPACPI_THERMAL_SENSOR_NA
 
- TPACPI_THERMAL_TPEC_16
 
- TPACPI_THERMAL_TPEC_8
 
- TPACPI_URL
 
- TPACPI_VERSION
 
- TPACPI_VIDEO_570
 
- TPACPI_VIDEO_770
 
- TPACPI_VIDEO_NEW
 
- TPACPI_VIDEO_NONE
 
- TPACPI_VOL_CAP_AUTO
 
- TPACPI_VOL_CAP_MAX
 
- TPACPI_VOL_CAP_MUTEONLY
 
- TPACPI_VOL_CAP_VOLMUTE
 
- TPACPI_VOL_MODE_AUTO
 
- TPACPI_VOL_MODE_EC
 
- TPACPI_VOL_MODE_ECNVRAM
 
- TPACPI_VOL_MODE_MAX
 
- TPACPI_VOL_MODE_UCMS_STEP
 
- TPACPI_VOL_Q_LEVEL
 
- TPACPI_VOL_Q_MUTEONLY
 
- TPACPI_WORKQUEUE_NAME
 
- TPARG_FL_FENTRY
 
- TPARG_FL_KERNEL
 
- TPARG_FL_MASK
 
- TPARG_FL_RETURN
 
- TPAUSE
 
- TPAUSECR
 
- TPAUSER
 
- TPAUSER_BIT
 
- TPAUSER_TPAUSE
 
- TPAUSER_UNLIMITED
 
- TPA_AGG_AGG_ID
 
- TPA_AGG_SIZE
 
- TPA_END_AGG_BUFS
 
- TPA_END_AGG_BUFS_P5
 
- TPA_END_AGG_ID
 
- TPA_END_AGG_ID_P5
 
- TPA_END_ERRORS
 
- TPA_END_GRO
 
- TPA_END_GRO_TS
 
- TPA_END_PAYLOAD_OFF
 
- TPA_END_PAYLOAD_OFF_P5
 
- TPA_END_TPA_SEGS
 
- TPA_GRO
 
- TPA_LRO
 
- TPA_MODE_DISABLED
 
- TPA_MODE_GRO
 
- TPA_MODE_LRO
 
- TPA_SM_ERR_ALARM
 
- TPA_START_AGG_ID
 
- TPA_START_AGG_ID_P5
 
- TPA_START_CFA_CODE
 
- TPA_START_ERROR
 
- TPA_START_ERROR_CODE
 
- TPA_START_HASH_TYPE
 
- TPA_START_HASH_VALID
 
- TPA_START_IS_IPV6
 
- TPA_TSTAMP_OPT_LEN
 
- TPA_TX_FRM_DROP
 
- TPA_UPDATE_DISABLE_COMMAND
 
- TPA_UPDATE_ENABLE_COMMAND
 
- TPA_UPDATE_NONE_COMMAND
 
- TPAchipAGPERR
 
- TPAchipPCTL
 
- TPAchipPERR
 
- TPAchipSERR
 
- TPAchipWSBA
 
- TPC
 
- TPC0_CFG_ARUSER_ASID_MASK
 
- TPC0_CFG_ARUSER_ASID_SHIFT
 
- TPC0_CFG_ARUSER_MMBP_MASK
 
- TPC0_CFG_ARUSER_MMBP_SHIFT
 
- TPC0_CFG_ARUSER_V_MASK
 
- TPC0_CFG_ARUSER_V_SHIFT
 
- TPC0_CFG_AWUSER_ASID_MASK
 
- TPC0_CFG_AWUSER_ASID_SHIFT
 
- TPC0_CFG_AWUSER_MMBP_MASK
 
- TPC0_CFG_AWUSER_MMBP_SHIFT
 
- TPC0_CFG_AWUSER_V_MASK
 
- TPC0_CFG_AWUSER_V_SHIFT
 
- TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_MASK
 
- TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_SHIFT
 
- TPC0_CFG_CFG_SUBTRACT_VALUE_V_MASK
 
- TPC0_CFG_CFG_SUBTRACT_VALUE_V_SHIFT
 
- TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK
 
- TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_SHIFT
 
- TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK
 
- TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_SHIFT
 
- TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_MASK
 
- TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_SHIFT
 
- TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_MASK
 
- TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT
 
- TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_MASK
 
- TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_SHIFT
 
- TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_MASK
 
- TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_SHIFT
 
- TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_MASK
 
- TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_SHIFT
 
- TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_MASK
 
- TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_SHIFT
 
- TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_MASK
 
- TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_SHIFT
 
- TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_MASK
 
- TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_SHIFT
 
- TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_MASK
 
- TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_SHIFT
 
- TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_MASK
 
- TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_SHIFT
 
- TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_MASK
 
- TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_SHIFT
 
- TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_MASK
 
- TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_SHIFT
 
- TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_MASK
 
- TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_SHIFT
 
- TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_MASK
 
- TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_SHIFT
 
- TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_MASK
 
- TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT
 
- TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_MASK
 
- TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_SHIFT
 
- TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_MASK
 
- TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT
 
- TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_MASK
 
- TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT
 
- TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_MASK
 
- TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_SHIFT
 
- TPC0_CFG_KERNEL_SRF_V_MASK
 
- TPC0_CFG_KERNEL_SRF_V_SHIFT
 
- TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_MASK
 
- TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_SHIFT
 
- TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK
 
- TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT
 
- TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK
 
- TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK
 
- TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK
 
- TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK
 
- TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK
 
- TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK
 
- TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK
 
- TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK
 
- TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK
 
- TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK
 
- TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK
 
- TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK
 
- TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK
 
- TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK
 
- TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK
 
- TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK
 
- TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK
 
- TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK
 
- TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK
 
- TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK
 
- TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK
 
- TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK
 
- TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_MASK
 
- TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK
 
- TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK
 
- TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT
 
- TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK
 
- TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT
 
- TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_MASK
 
- TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_SHIFT
 
- TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_MASK
 
- TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_SHIFT
 
- TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_MASK
 
- TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_SHIFT
 
- TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_MASK
 
- TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_SHIFT
 
- TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_MASK
 
- TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_SHIFT
 
- TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_MASK
 
- TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_SHIFT
 
- TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_MASK
 
- TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_SHIFT
 
- TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_MASK
 
- TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_SHIFT
 
- TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_MASK
 
- TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_SHIFT
 
- TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_MASK
 
- TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_SHIFT
 
- TPC0_CFG_LFSR_POLYNOM_V_MASK
 
- TPC0_CFG_LFSR_POLYNOM_V_SHIFT
 
- TPC0_CFG_MAX_OFFSET
 
- TPC0_CFG_MSS_CONFIG_ARCACHE_MASK
 
- TPC0_CFG_MSS_CONFIG_ARCACHE_SHIFT
 
- TPC0_CFG_MSS_CONFIG_AWCACHE_MASK
 
- TPC0_CFG_MSS_CONFIG_AWCACHE_SHIFT
 
- TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_MASK
 
- TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_SHIFT
 
- TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_MASK
 
- TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_SHIFT
 
- TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_MASK
 
- TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT
 
- TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_MASK
 
- TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_SHIFT
 
- TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_MASK
 
- TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT
 
- TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_MASK
 
- TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT
 
- TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_MASK
 
- TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_SHIFT
 
- TPC0_CFG_QM_SRF_V_MASK
 
- TPC0_CFG_QM_SRF_V_SHIFT
 
- TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_MASK
 
- TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_SHIFT
 
- TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK
 
- TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT
 
- TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK
 
- TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT
 
- TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_MASK
 
- TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_MASK
 
- TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_MASK
 
- TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK
 
- TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT
 
- TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK
 
- TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT
 
- TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK
 
- TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT
 
- TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_MASK
 
- TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_MASK
 
- TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_MASK
 
- TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK
 
- TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT
 
- TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK
 
- TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT
 
- TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK
 
- TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT
 
- TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_MASK
 
- TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_MASK
 
- TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_MASK
 
- TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK
 
- TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT
 
- TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK
 
- TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT
 
- TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK
 
- TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT
 
- TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_MASK
 
- TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_MASK
 
- TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_MASK
 
- TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK
 
- TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT
 
- TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK
 
- TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT
 
- TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK
 
- TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT
 
- TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_MASK
 
- TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_MASK
 
- TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_MASK
 
- TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK
 
- TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT
 
- TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK
 
- TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT
 
- TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK
 
- TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT
 
- TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_MASK
 
- TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_MASK
 
- TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_MASK
 
- TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK
 
- TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT
 
- TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK
 
- TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT
 
- TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK
 
- TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT
 
- TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_MASK
 
- TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_MASK
 
- TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_MASK
 
- TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK
 
- TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT
 
- TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK
 
- TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT
 
- TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK
 
- TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT
 
- TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_MASK
 
- TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_MASK
 
- TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET_V_MASK
 
- TPC0_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_MASK
 
- TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_MASK
 
- TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_MASK
 
- TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_SHIFT
 
- TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK
 
- TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT
 
- TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK
 
- TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT
 
- TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK
 
- TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT
 
- TPC0_CFG_QM_TID_BASE_DIM_0_V_MASK
 
- TPC0_CFG_QM_TID_BASE_DIM_0_V_SHIFT
 
- TPC0_CFG_QM_TID_BASE_DIM_1_V_MASK
 
- TPC0_CFG_QM_TID_BASE_DIM_1_V_SHIFT
 
- TPC0_CFG_QM_TID_BASE_DIM_2_V_MASK
 
- TPC0_CFG_QM_TID_BASE_DIM_2_V_SHIFT
 
- TPC0_CFG_QM_TID_BASE_DIM_3_V_MASK
 
- TPC0_CFG_QM_TID_BASE_DIM_3_V_SHIFT
 
- TPC0_CFG_QM_TID_BASE_DIM_4_V_MASK
 
- TPC0_CFG_QM_TID_BASE_DIM_4_V_SHIFT
 
- TPC0_CFG_QM_TID_SIZE_DIM_0_V_MASK
 
- TPC0_CFG_QM_TID_SIZE_DIM_0_V_SHIFT
 
- TPC0_CFG_QM_TID_SIZE_DIM_1_V_MASK
 
- TPC0_CFG_QM_TID_SIZE_DIM_1_V_SHIFT
 
- TPC0_CFG_QM_TID_SIZE_DIM_2_V_MASK
 
- TPC0_CFG_QM_TID_SIZE_DIM_2_V_SHIFT
 
- TPC0_CFG_QM_TID_SIZE_DIM_3_V_MASK
 
- TPC0_CFG_QM_TID_SIZE_DIM_3_V_SHIFT
 
- TPC0_CFG_QM_TID_SIZE_DIM_4_V_MASK
 
- TPC0_CFG_QM_TID_SIZE_DIM_4_V_SHIFT
 
- TPC0_CFG_RESERVED_DESC_END_V_MASK
 
- TPC0_CFG_RESERVED_DESC_END_V_SHIFT
 
- TPC0_CFG_ROUND_CSR_MODE_MASK
 
- TPC0_CFG_ROUND_CSR_MODE_SHIFT
 
- TPC0_CFG_SECTION
 
- TPC0_CFG_SEMAPHORE_V_MASK
 
- TPC0_CFG_SEMAPHORE_V_SHIFT
 
- TPC0_CFG_SFLAGS_V_MASK
 
- TPC0_CFG_SFLAGS_V_SHIFT
 
- TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_MASK
 
- TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_SHIFT
 
- TPC0_CFG_SM_BASE_ADDRESS_LOW_V_MASK
 
- TPC0_CFG_SM_BASE_ADDRESS_LOW_V_SHIFT
 
- TPC0_CFG_STATUS_IQ_EMPTY_MASK
 
- TPC0_CFG_STATUS_IQ_EMPTY_SHIFT
 
- TPC0_CFG_STATUS_NO_INFLIGH_MEM_ACCESSES_MASK
 
- TPC0_CFG_STATUS_NO_INFLIGH_MEM_ACCESSES_SHIFT
 
- TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK
 
- TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT
 
- TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK
 
- TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT
 
- TPC0_CFG_TBUF_BASE_ADDR_HIGH_V_MASK
 
- TPC0_CFG_TBUF_BASE_ADDR_HIGH_V_SHIFT
 
- TPC0_CFG_TBUF_BASE_ADDR_LOW_V_MASK
 
- TPC0_CFG_TBUF_BASE_ADDR_LOW_V_SHIFT
 
- TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_MASK
 
- TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_SHIFT
 
- TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_MASK
 
- TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_SHIFT
 
- TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_MASK
 
- TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_SHIFT
 
- TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_MASK
 
- TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT
 
- TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_MASK
 
- TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_SHIFT
 
- TPC0_CFG_TPC_CMD_QMAN_STOP_MASK
 
- TPC0_CFG_TPC_CMD_QMAN_STOP_SHIFT
 
- TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_MASK
 
- TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_SHIFT
 
- TPC0_CFG_TPC_EXECUTE_V_MASK
 
- TPC0_CFG_TPC_EXECUTE_V_SHIFT
 
- TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK
 
- TPC0_CFG_TPC_INTR_CAUSE_CAUSE_SHIFT
 
- TPC0_CFG_TPC_INTR_MASK_MASK_MASK
 
- TPC0_CFG_TPC_INTR_MASK_MASK_SHIFT
 
- TPC0_CFG_TPC_STALL_V_MASK
 
- TPC0_CFG_TPC_STALL_V_SHIFT
 
- TPC0_CFG_TSB_CONFIG_MAX_OUTSTANDING_MASK
 
- TPC0_CFG_TSB_CONFIG_MAX_OUTSTANDING_SHIFT
 
- TPC0_CFG_TSB_CONFIG_MAX_SIZE_MASK
 
- TPC0_CFG_TSB_CONFIG_MAX_SIZE_SHIFT
 
- TPC0_CFG_TSB_CONFIG_TSB_AGU_MAX_CREDIT_MASK
 
- TPC0_CFG_TSB_CONFIG_TSB_AGU_MAX_CREDIT_SHIFT
 
- TPC0_CFG_TSB_CONFIG_TSB_EU_MAX_CREDIT_MASK
 
- TPC0_CFG_TSB_CONFIG_TSB_EU_MAX_CREDIT_SHIFT
 
- TPC0_CFG_VFLAGS_V_MASK
 
- TPC0_CFG_VFLAGS_V_SHIFT
 
- TPC0_CMDQ_CP_BARRIER_CFG_EBGUARD_MASK
 
- TPC0_CMDQ_CP_BARRIER_CFG_EBGUARD_SHIFT
 
- TPC0_CMDQ_CP_CURRENT_INST_HI_VAL_MASK
 
- TPC0_CMDQ_CP_CURRENT_INST_HI_VAL_SHIFT
 
- TPC0_CMDQ_CP_CURRENT_INST_LO_VAL_MASK
 
- TPC0_CMDQ_CP_CURRENT_INST_LO_VAL_SHIFT
 
- TPC0_CMDQ_CP_DBG_0_VAL_MASK
 
- TPC0_CMDQ_CP_DBG_0_VAL_SHIFT
 
- TPC0_CMDQ_CP_FENCE0_CNT_VAL_MASK
 
- TPC0_CMDQ_CP_FENCE0_CNT_VAL_SHIFT
 
- TPC0_CMDQ_CP_FENCE0_RDATA_INC_VAL_MASK
 
- TPC0_CMDQ_CP_FENCE0_RDATA_INC_VAL_SHIFT
 
- TPC0_CMDQ_CP_FENCE1_CNT_VAL_MASK
 
- TPC0_CMDQ_CP_FENCE1_CNT_VAL_SHIFT
 
- TPC0_CMDQ_CP_FENCE1_RDATA_INC_VAL_MASK
 
- TPC0_CMDQ_CP_FENCE1_RDATA_INC_VAL_SHIFT
 
- TPC0_CMDQ_CP_FENCE2_CNT_VAL_MASK
 
- TPC0_CMDQ_CP_FENCE2_CNT_VAL_SHIFT
 
- TPC0_CMDQ_CP_FENCE2_RDATA_INC_VAL_MASK
 
- TPC0_CMDQ_CP_FENCE2_RDATA_INC_VAL_SHIFT
 
- TPC0_CMDQ_CP_FENCE3_CNT_VAL_MASK
 
- TPC0_CMDQ_CP_FENCE3_CNT_VAL_SHIFT
 
- TPC0_CMDQ_CP_FENCE3_RDATA_INC_VAL_MASK
 
- TPC0_CMDQ_CP_FENCE3_RDATA_INC_VAL_SHIFT
 
- TPC0_CMDQ_CP_LDMA_COMMIT_OFFSET_VAL_MASK
 
- TPC0_CMDQ_CP_LDMA_COMMIT_OFFSET_VAL_SHIFT
 
- TPC0_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET_VAL_MASK
 
- TPC0_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET_VAL_SHIFT
 
- TPC0_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK
 
- TPC0_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT
 
- TPC0_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_MASK
 
- TPC0_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_SHIFT
 
- TPC0_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK
 
- TPC0_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT
 
- TPC0_CMDQ_CP_LDMA_TSIZE_OFFSET_VAL_MASK
 
- TPC0_CMDQ_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT
 
- TPC0_CMDQ_CP_MSG_BASE0_ADDR_HI_VAL_MASK
 
- TPC0_CMDQ_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT
 
- TPC0_CMDQ_CP_MSG_BASE0_ADDR_LO_VAL_MASK
 
- TPC0_CMDQ_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT
 
- TPC0_CMDQ_CP_MSG_BASE1_ADDR_HI_VAL_MASK
 
- TPC0_CMDQ_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT
 
- TPC0_CMDQ_CP_MSG_BASE1_ADDR_LO_VAL_MASK
 
- TPC0_CMDQ_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT
 
- TPC0_CMDQ_CP_MSG_BASE2_ADDR_HI_VAL_MASK
 
- TPC0_CMDQ_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT
 
- TPC0_CMDQ_CP_MSG_BASE2_ADDR_LO_VAL_MASK
 
- TPC0_CMDQ_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT
 
- TPC0_CMDQ_CP_MSG_BASE3_ADDR_HI_VAL_MASK
 
- TPC0_CMDQ_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT
 
- TPC0_CMDQ_CP_MSG_BASE3_ADDR_LO_VAL_MASK
 
- TPC0_CMDQ_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT
 
- TPC0_CMDQ_CP_STS_ERDY_MASK
 
- TPC0_CMDQ_CP_STS_ERDY_SHIFT
 
- TPC0_CMDQ_CP_STS_FENCE_ID_MASK
 
- TPC0_CMDQ_CP_STS_FENCE_ID_SHIFT
 
- TPC0_CMDQ_CP_STS_FENCE_IN_PROGRESS_MASK
 
- TPC0_CMDQ_CP_STS_FENCE_IN_PROGRESS_SHIFT
 
- TPC0_CMDQ_CP_STS_MRDY_MASK
 
- TPC0_CMDQ_CP_STS_MRDY_SHIFT
 
- TPC0_CMDQ_CP_STS_MSG_INFLIGHT_CNT_MASK
 
- TPC0_CMDQ_CP_STS_MSG_INFLIGHT_CNT_SHIFT
 
- TPC0_CMDQ_CP_STS_RRDY_MASK
 
- TPC0_CMDQ_CP_STS_RRDY_SHIFT
 
- TPC0_CMDQ_CP_STS_SW_STOP_MASK
 
- TPC0_CMDQ_CP_STS_SW_STOP_SHIFT
 
- TPC0_CMDQ_CQ_ARUSER_NOSNOOP_MASK
 
- TPC0_CMDQ_CQ_ARUSER_NOSNOOP_SHIFT
 
- TPC0_CMDQ_CQ_ARUSER_WORD_MASK
 
- TPC0_CMDQ_CQ_ARUSER_WORD_SHIFT
 
- TPC0_CMDQ_CQ_BUF_ADDR_VAL_MASK
 
- TPC0_CMDQ_CQ_BUF_ADDR_VAL_SHIFT
 
- TPC0_CMDQ_CQ_BUF_RDATA_VAL_MASK
 
- TPC0_CMDQ_CQ_BUF_RDATA_VAL_SHIFT
 
- TPC0_CMDQ_CQ_CFG0_RESERVED_MASK
 
- TPC0_CMDQ_CQ_CFG0_RESERVED_SHIFT
 
- TPC0_CMDQ_CQ_CFG1_CREDIT_LIM_MASK
 
- TPC0_CMDQ_CQ_CFG1_CREDIT_LIM_SHIFT
 
- TPC0_CMDQ_CQ_CFG1_MAX_INFLIGHT_MASK
 
- TPC0_CMDQ_CQ_CFG1_MAX_INFLIGHT_SHIFT
 
- TPC0_CMDQ_CQ_CTL_CTL_MASK
 
- TPC0_CMDQ_CQ_CTL_CTL_SHIFT
 
- TPC0_CMDQ_CQ_CTL_RPT_MASK
 
- TPC0_CMDQ_CQ_CTL_RPT_SHIFT
 
- TPC0_CMDQ_CQ_CTL_STS_CTL_MASK
 
- TPC0_CMDQ_CQ_CTL_STS_CTL_SHIFT
 
- TPC0_CMDQ_CQ_CTL_STS_RPT_MASK
 
- TPC0_CMDQ_CQ_CTL_STS_RPT_SHIFT
 
- TPC0_CMDQ_CQ_IFIFO_CNT_VAL_MASK
 
- TPC0_CMDQ_CQ_IFIFO_CNT_VAL_SHIFT
 
- TPC0_CMDQ_CQ_PTR_HI_STS_VAL_MASK
 
- TPC0_CMDQ_CQ_PTR_HI_STS_VAL_SHIFT
 
- TPC0_CMDQ_CQ_PTR_HI_VAL_MASK
 
- TPC0_CMDQ_CQ_PTR_HI_VAL_SHIFT
 
- TPC0_CMDQ_CQ_PTR_LO_STS_VAL_MASK
 
- TPC0_CMDQ_CQ_PTR_LO_STS_VAL_SHIFT
 
- TPC0_CMDQ_CQ_PTR_LO_VAL_MASK
 
- TPC0_CMDQ_CQ_PTR_LO_VAL_SHIFT
 
- TPC0_CMDQ_CQ_RD_RATE_LIM_EN_VAL_MASK
 
- TPC0_CMDQ_CQ_RD_RATE_LIM_EN_VAL_SHIFT
 
- TPC0_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK
 
- TPC0_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT
 
- TPC0_CMDQ_CQ_RD_RATE_LIM_SAT_VAL_MASK
 
- TPC0_CMDQ_CQ_RD_RATE_LIM_SAT_VAL_SHIFT
 
- TPC0_CMDQ_CQ_RD_RATE_LIM_TOUT_VAL_MASK
 
- TPC0_CMDQ_CQ_RD_RATE_LIM_TOUT_VAL_SHIFT
 
- TPC0_CMDQ_CQ_STS0_CQ_CREDIT_CNT_MASK
 
- TPC0_CMDQ_CQ_STS0_CQ_CREDIT_CNT_SHIFT
 
- TPC0_CMDQ_CQ_STS0_CQ_FREE_CNT_MASK
 
- TPC0_CMDQ_CQ_STS0_CQ_FREE_CNT_SHIFT
 
- TPC0_CMDQ_CQ_STS1_CQ_BUF_EMPTY_MASK
 
- TPC0_CMDQ_CQ_STS1_CQ_BUF_EMPTY_SHIFT
 
- TPC0_CMDQ_CQ_STS1_CQ_BUSY_MASK
 
- TPC0_CMDQ_CQ_STS1_CQ_BUSY_SHIFT
 
- TPC0_CMDQ_CQ_STS1_CQ_INFLIGHT_CNT_MASK
 
- TPC0_CMDQ_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT
 
- TPC0_CMDQ_CQ_TSIZE_STS_VAL_MASK
 
- TPC0_CMDQ_CQ_TSIZE_STS_VAL_SHIFT
 
- TPC0_CMDQ_CQ_TSIZE_VAL_MASK
 
- TPC0_CMDQ_CQ_TSIZE_VAL_SHIFT
 
- TPC0_CMDQ_GLBL_CFG0_CP_EN_MASK
 
- TPC0_CMDQ_GLBL_CFG0_CP_EN_SHIFT
 
- TPC0_CMDQ_GLBL_CFG0_CQF_EN_MASK
 
- TPC0_CMDQ_GLBL_CFG0_CQF_EN_SHIFT
 
- TPC0_CMDQ_GLBL_CFG0_DMA_EN_MASK
 
- TPC0_CMDQ_GLBL_CFG0_DMA_EN_SHIFT
 
- TPC0_CMDQ_GLBL_CFG0_PQF_EN_MASK
 
- TPC0_CMDQ_GLBL_CFG0_PQF_EN_SHIFT
 
- TPC0_CMDQ_GLBL_CFG1_CP_FLUSH_MASK
 
- TPC0_CMDQ_GLBL_CFG1_CP_FLUSH_SHIFT
 
- TPC0_CMDQ_GLBL_CFG1_CP_STOP_MASK
 
- TPC0_CMDQ_GLBL_CFG1_CP_STOP_SHIFT
 
- TPC0_CMDQ_GLBL_CFG1_CQF_FLUSH_MASK
 
- TPC0_CMDQ_GLBL_CFG1_CQF_FLUSH_SHIFT
 
- TPC0_CMDQ_GLBL_CFG1_CQF_STOP_MASK
 
- TPC0_CMDQ_GLBL_CFG1_CQF_STOP_SHIFT
 
- TPC0_CMDQ_GLBL_CFG1_DMA_FLUSH_MASK
 
- TPC0_CMDQ_GLBL_CFG1_DMA_FLUSH_SHIFT
 
- TPC0_CMDQ_GLBL_CFG1_DMA_STOP_MASK
 
- TPC0_CMDQ_GLBL_CFG1_DMA_STOP_SHIFT
 
- TPC0_CMDQ_GLBL_CFG1_PQF_FLUSH_MASK
 
- TPC0_CMDQ_GLBL_CFG1_PQF_FLUSH_SHIFT
 
- TPC0_CMDQ_GLBL_CFG1_PQF_STOP_MASK
 
- TPC0_CMDQ_GLBL_CFG1_PQF_STOP_SHIFT
 
- TPC0_CMDQ_GLBL_ERR_ADDR_HI_VAL_MASK
 
- TPC0_CMDQ_GLBL_ERR_ADDR_HI_VAL_SHIFT
 
- TPC0_CMDQ_GLBL_ERR_ADDR_LO_VAL_MASK
 
- TPC0_CMDQ_GLBL_ERR_ADDR_LO_VAL_SHIFT
 
- TPC0_CMDQ_GLBL_ERR_CFG_CP_ERR_INT_EN_MASK
 
- TPC0_CMDQ_GLBL_ERR_CFG_CP_ERR_INT_EN_SHIFT
 
- TPC0_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK
 
- TPC0_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT
 
- TPC0_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK
 
- TPC0_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT
 
- TPC0_CMDQ_GLBL_ERR_CFG_CQF_ERR_INT_EN_MASK
 
- TPC0_CMDQ_GLBL_ERR_CFG_CQF_ERR_INT_EN_SHIFT
 
- TPC0_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK
 
- TPC0_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT
 
- TPC0_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK
 
- TPC0_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT
 
- TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK
 
- TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_INT_EN_SHIFT
 
- TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_MASK
 
- TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT
 
- TPC0_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK
 
- TPC0_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT
 
- TPC0_CMDQ_GLBL_ERR_CFG_PQF_ERR_INT_EN_MASK
 
- TPC0_CMDQ_GLBL_ERR_CFG_PQF_ERR_INT_EN_SHIFT
 
- TPC0_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK
 
- TPC0_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT
 
- TPC0_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK
 
- TPC0_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT
 
- TPC0_CMDQ_GLBL_ERR_WDATA_VAL_MASK
 
- TPC0_CMDQ_GLBL_ERR_WDATA_VAL_SHIFT
 
- TPC0_CMDQ_GLBL_NON_SECURE_PROPS_ASID_MASK
 
- TPC0_CMDQ_GLBL_NON_SECURE_PROPS_ASID_SHIFT
 
- TPC0_CMDQ_GLBL_NON_SECURE_PROPS_MMBP_MASK
 
- TPC0_CMDQ_GLBL_NON_SECURE_PROPS_MMBP_SHIFT
 
- TPC0_CMDQ_GLBL_PROT_CP_ERR_PROT_MASK
 
- TPC0_CMDQ_GLBL_PROT_CP_ERR_PROT_SHIFT
 
- TPC0_CMDQ_GLBL_PROT_CP_PROT_MASK
 
- TPC0_CMDQ_GLBL_PROT_CP_PROT_SHIFT
 
- TPC0_CMDQ_GLBL_PROT_CQF_ERR_PROT_MASK
 
- TPC0_CMDQ_GLBL_PROT_CQF_ERR_PROT_SHIFT
 
- TPC0_CMDQ_GLBL_PROT_CQF_PROT_MASK
 
- TPC0_CMDQ_GLBL_PROT_CQF_PROT_SHIFT
 
- TPC0_CMDQ_GLBL_PROT_DMA_ERR_PROT_MASK
 
- TPC0_CMDQ_GLBL_PROT_DMA_ERR_PROT_SHIFT
 
- TPC0_CMDQ_GLBL_PROT_DMA_PROT_MASK
 
- TPC0_CMDQ_GLBL_PROT_DMA_PROT_SHIFT
 
- TPC0_CMDQ_GLBL_PROT_PQF_ERR_PROT_MASK
 
- TPC0_CMDQ_GLBL_PROT_PQF_ERR_PROT_SHIFT
 
- TPC0_CMDQ_GLBL_PROT_PQF_PROT_MASK
 
- TPC0_CMDQ_GLBL_PROT_PQF_PROT_SHIFT
 
- TPC0_CMDQ_GLBL_SECURE_PROPS_ASID_MASK
 
- TPC0_CMDQ_GLBL_SECURE_PROPS_ASID_SHIFT
 
- TPC0_CMDQ_GLBL_SECURE_PROPS_MMBP_MASK
 
- TPC0_CMDQ_GLBL_SECURE_PROPS_MMBP_SHIFT
 
- TPC0_CMDQ_GLBL_STS0_CP_IDLE_MASK
 
- TPC0_CMDQ_GLBL_STS0_CP_IDLE_SHIFT
 
- TPC0_CMDQ_GLBL_STS0_CP_IS_STOP_MASK
 
- TPC0_CMDQ_GLBL_STS0_CP_IS_STOP_SHIFT
 
- TPC0_CMDQ_GLBL_STS0_CQF_IDLE_MASK
 
- TPC0_CMDQ_GLBL_STS0_CQF_IDLE_SHIFT
 
- TPC0_CMDQ_GLBL_STS0_CQF_IS_STOP_MASK
 
- TPC0_CMDQ_GLBL_STS0_CQF_IS_STOP_SHIFT
 
- TPC0_CMDQ_GLBL_STS0_DMA_IDLE_MASK
 
- TPC0_CMDQ_GLBL_STS0_DMA_IDLE_SHIFT
 
- TPC0_CMDQ_GLBL_STS0_DMA_IS_STOP_MASK
 
- TPC0_CMDQ_GLBL_STS0_DMA_IS_STOP_SHIFT
 
- TPC0_CMDQ_GLBL_STS0_PQF_IDLE_MASK
 
- TPC0_CMDQ_GLBL_STS0_PQF_IDLE_SHIFT
 
- TPC0_CMDQ_GLBL_STS0_PQF_IS_STOP_MASK
 
- TPC0_CMDQ_GLBL_STS0_PQF_IS_STOP_SHIFT
 
- TPC0_CMDQ_GLBL_STS1_CP_MSG_WR_ERR_MASK
 
- TPC0_CMDQ_GLBL_STS1_CP_MSG_WR_ERR_SHIFT
 
- TPC0_CMDQ_GLBL_STS1_CP_RD_ERR_MASK
 
- TPC0_CMDQ_GLBL_STS1_CP_RD_ERR_SHIFT
 
- TPC0_CMDQ_GLBL_STS1_CP_STOP_OP_MASK
 
- TPC0_CMDQ_GLBL_STS1_CP_STOP_OP_SHIFT
 
- TPC0_CMDQ_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK
 
- TPC0_CMDQ_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT
 
- TPC0_CMDQ_GLBL_STS1_CQF_RD_ERR_MASK
 
- TPC0_CMDQ_GLBL_STS1_CQF_RD_ERR_SHIFT
 
- TPC0_CMDQ_GLBL_STS1_DMA_RD_ERR_MASK
 
- TPC0_CMDQ_GLBL_STS1_DMA_RD_ERR_SHIFT
 
- TPC0_CMDQ_GLBL_STS1_DMA_RD_MSG_ERR_MASK
 
- TPC0_CMDQ_GLBL_STS1_DMA_RD_MSG_ERR_SHIFT
 
- TPC0_CMDQ_GLBL_STS1_DMA_WR_ERR_MASK
 
- TPC0_CMDQ_GLBL_STS1_DMA_WR_ERR_SHIFT
 
- TPC0_CMDQ_GLBL_STS1_DMA_WR_MSG_ERR_MASK
 
- TPC0_CMDQ_GLBL_STS1_DMA_WR_MSG_ERR_SHIFT
 
- TPC0_CMDQ_GLBL_STS1_PQF_RD_ERR_MASK
 
- TPC0_CMDQ_GLBL_STS1_PQF_RD_ERR_SHIFT
 
- TPC0_CMDQ_MAX_OFFSET
 
- TPC0_CMDQ_SECTION
 
- TPC0_EML_BUSMON_0_MAX_OFFSET
 
- TPC0_EML_BUSMON_0_SECTION
 
- TPC0_EML_BUSMON_1_MAX_OFFSET
 
- TPC0_EML_BUSMON_1_SECTION
 
- TPC0_EML_BUSMON_2_MAX_OFFSET
 
- TPC0_EML_BUSMON_2_SECTION
 
- TPC0_EML_BUSMON_3_MAX_OFFSET
 
- TPC0_EML_BUSMON_3_SECTION
 
- TPC0_EML_CFG_DBG_AGUADD_COUNT_COUNT_MASK
 
- TPC0_EML_CFG_DBG_AGUADD_COUNT_COUNT_SHIFT
 
- TPC0_EML_CFG_DBG_AGUADD_COUNT_MATCH_COUNT_MASK
 
- TPC0_EML_CFG_DBG_AGUADD_COUNT_MATCH_COUNT_SHIFT
 
- TPC0_EML_CFG_DBG_AGUADD_EN_ENABLE0_MASK
 
- TPC0_EML_CFG_DBG_AGUADD_EN_ENABLE0_SHIFT
 
- TPC0_EML_CFG_DBG_AGUADD_EN_ENABLE1_MASK
 
- TPC0_EML_CFG_DBG_AGUADD_EN_ENABLE1_SHIFT
 
- TPC0_EML_CFG_DBG_AGUADD_EN_RW_N0_MASK
 
- TPC0_EML_CFG_DBG_AGUADD_EN_RW_N0_SHIFT
 
- TPC0_EML_CFG_DBG_AGUADD_EN_RW_N1_MASK
 
- TPC0_EML_CFG_DBG_AGUADD_EN_RW_N1_SHIFT
 
- TPC0_EML_CFG_DBG_AGUADD_LSB_HIGH_ADDRESS_MASK
 
- TPC0_EML_CFG_DBG_AGUADD_LSB_HIGH_ADDRESS_SHIFT
 
- TPC0_EML_CFG_DBG_AGUADD_LSB_LOW_ADDRESS_MASK
 
- TPC0_EML_CFG_DBG_AGUADD_LSB_LOW_ADDRESS_SHIFT
 
- TPC0_EML_CFG_DBG_AGUADD_MSB_HIGH_ADDRESS_MASK
 
- TPC0_EML_CFG_DBG_AGUADD_MSB_HIGH_ADDRESS_SHIFT
 
- TPC0_EML_CFG_DBG_AGUADD_MSB_LOW_ADDRESS_MASK
 
- TPC0_EML_CFG_DBG_AGUADD_MSB_LOW_ADDRESS_SHIFT
 
- TPC0_EML_CFG_DBG_AXIHBWADD_COUNT_COUNT_MASK
 
- TPC0_EML_CFG_DBG_AXIHBWADD_COUNT_COUNT_SHIFT
 
- TPC0_EML_CFG_DBG_AXIHBWADD_COUNT_MATCH_MATCH_MASK
 
- TPC0_EML_CFG_DBG_AXIHBWADD_COUNT_MATCH_MATCH_SHIFT
 
- TPC0_EML_CFG_DBG_AXIHBWADD_EN_ENABLE0_MASK
 
- TPC0_EML_CFG_DBG_AXIHBWADD_EN_ENABLE0_SHIFT
 
- TPC0_EML_CFG_DBG_AXIHBWADD_EN_ENABLE1_MASK
 
- TPC0_EML_CFG_DBG_AXIHBWADD_EN_ENABLE1_SHIFT
 
- TPC0_EML_CFG_DBG_AXIHBWADD_EN_RW_N0_MASK
 
- TPC0_EML_CFG_DBG_AXIHBWADD_EN_RW_N0_SHIFT
 
- TPC0_EML_CFG_DBG_AXIHBWADD_EN_RW_N1_MASK
 
- TPC0_EML_CFG_DBG_AXIHBWADD_EN_RW_N1_SHIFT
 
- TPC0_EML_CFG_DBG_AXIHBWADD_LSB_HIGH_ADDRESS_MASK
 
- TPC0_EML_CFG_DBG_AXIHBWADD_LSB_HIGH_ADDRESS_SHIFT
 
- TPC0_EML_CFG_DBG_AXIHBWADD_LSB_LOW_ADDRESS_MASK
 
- TPC0_EML_CFG_DBG_AXIHBWADD_LSB_LOW_ADDRESS_SHIFT
 
- TPC0_EML_CFG_DBG_AXIHBWADD_MSB_HIGH_ADDRESS_MASK
 
- TPC0_EML_CFG_DBG_AXIHBWADD_MSB_HIGH_ADDRESS_SHIFT
 
- TPC0_EML_CFG_DBG_AXIHBWADD_MSB_LOW_ADDRESS_MASK
 
- TPC0_EML_CFG_DBG_AXIHBWADD_MSB_LOW_ADDRESS_SHIFT
 
- TPC0_EML_CFG_DBG_AXIHBWDATA_COUNT_COUNT_MASK
 
- TPC0_EML_CFG_DBG_AXIHBWDATA_COUNT_COUNT_SHIFT
 
- TPC0_EML_CFG_DBG_AXIHBWDATA_DATA_MASK
 
- TPC0_EML_CFG_DBG_AXIHBWDATA_DATA_SHIFT
 
- TPC0_EML_CFG_DBG_AXIHBWDATA_EN_ENABLE_MASK
 
- TPC0_EML_CFG_DBG_AXIHBWDATA_EN_ENABLE_SHIFT
 
- TPC0_EML_CFG_DBG_AXIHBWDATA_EN_RW_N_MASK
 
- TPC0_EML_CFG_DBG_AXIHBWDATA_EN_RW_N_SHIFT
 
- TPC0_EML_CFG_DBG_AXIHBWDAT_COUNT_MATCH_COUNT_MASK
 
- TPC0_EML_CFG_DBG_AXIHBWDAT_COUNT_MATCH_COUNT_SHIFT
 
- TPC0_EML_CFG_DBG_AXILBWADD_COUNT_COUNT_MASK
 
- TPC0_EML_CFG_DBG_AXILBWADD_COUNT_COUNT_SHIFT
 
- TPC0_EML_CFG_DBG_AXILBWADD_COUNT_MATCH_MATCH_MASK
 
- TPC0_EML_CFG_DBG_AXILBWADD_COUNT_MATCH_MATCH_SHIFT
 
- TPC0_EML_CFG_DBG_AXILBWADD_EN_ENABLE0_MASK
 
- TPC0_EML_CFG_DBG_AXILBWADD_EN_ENABLE0_SHIFT
 
- TPC0_EML_CFG_DBG_AXILBWADD_EN_ENABLE1_MASK
 
- TPC0_EML_CFG_DBG_AXILBWADD_EN_ENABLE1_SHIFT
 
- TPC0_EML_CFG_DBG_AXILBWADD_EN_RW_N0_MASK
 
- TPC0_EML_CFG_DBG_AXILBWADD_EN_RW_N0_SHIFT
 
- TPC0_EML_CFG_DBG_AXILBWADD_EN_RW_N1_MASK
 
- TPC0_EML_CFG_DBG_AXILBWADD_EN_RW_N1_SHIFT
 
- TPC0_EML_CFG_DBG_AXILBWADD_LSB_HIGH_ADDRESS_MASK
 
- TPC0_EML_CFG_DBG_AXILBWADD_LSB_HIGH_ADDRESS_SHIFT
 
- TPC0_EML_CFG_DBG_AXILBWADD_LSB_LOW_ADDRESS_MASK
 
- TPC0_EML_CFG_DBG_AXILBWADD_LSB_LOW_ADDRESS_SHIFT
 
- TPC0_EML_CFG_DBG_AXILBWADD_MSB_HIGH_ADDRESS_MASK
 
- TPC0_EML_CFG_DBG_AXILBWADD_MSB_HIGH_ADDRESS_SHIFT
 
- TPC0_EML_CFG_DBG_AXILBWADD_MSB_LOW_ADDRESS_MASK
 
- TPC0_EML_CFG_DBG_AXILBWADD_MSB_LOW_ADDRESS_SHIFT
 
- TPC0_EML_CFG_DBG_AXILBWDATA_COUNT_COUNT_MASK
 
- TPC0_EML_CFG_DBG_AXILBWDATA_COUNT_COUNT_SHIFT
 
- TPC0_EML_CFG_DBG_AXILBWDATA_DATA_MASK
 
- TPC0_EML_CFG_DBG_AXILBWDATA_DATA_SHIFT
 
- TPC0_EML_CFG_DBG_AXILBWDATA_EN_ENABLE_MASK
 
- TPC0_EML_CFG_DBG_AXILBWDATA_EN_ENABLE_SHIFT
 
- TPC0_EML_CFG_DBG_AXILBWDATA_EN_RW_N_MASK
 
- TPC0_EML_CFG_DBG_AXILBWDATA_EN_RW_N_SHIFT
 
- TPC0_EML_CFG_DBG_AXILBWDAT_COUNT_MATCH_MATCH_MASK
 
- TPC0_EML_CFG_DBG_AXILBWDAT_COUNT_MATCH_MATCH_SHIFT
 
- TPC0_EML_CFG_DBG_CNT_BP_DBGSW_EN_MASK
 
- TPC0_EML_CFG_DBG_CNT_BP_DBGSW_EN_SHIFT
 
- TPC0_EML_CFG_DBG_CNT_CORE_RST_MASK
 
- TPC0_EML_CFG_DBG_CNT_CORE_RST_SHIFT
 
- TPC0_EML_CFG_DBG_CNT_DBG_ENTER_MASK
 
- TPC0_EML_CFG_DBG_CNT_DBG_ENTER_SHIFT
 
- TPC0_EML_CFG_DBG_CNT_DBG_EN_MASK
 
- TPC0_EML_CFG_DBG_CNT_DBG_EN_SHIFT
 
- TPC0_EML_CFG_DBG_CNT_DBG_EXIT_MASK
 
- TPC0_EML_CFG_DBG_CNT_DBG_EXIT_SHIFT
 
- TPC0_EML_CFG_DBG_CNT_DCACHE_INV_MASK
 
- TPC0_EML_CFG_DBG_CNT_DCACHE_INV_SHIFT
 
- TPC0_EML_CFG_DBG_CNT_ICACHE_INV_MASK
 
- TPC0_EML_CFG_DBG_CNT_ICACHE_INV_SHIFT
 
- TPC0_EML_CFG_DBG_CNT_SNG_STEP_MASK
 
- TPC0_EML_CFG_DBG_CNT_SNG_STEP_SHIFT
 
- TPC0_EML_CFG_DBG_D0_PC_PC_MASK
 
- TPC0_EML_CFG_DBG_D0_PC_PC_SHIFT
 
- TPC0_EML_CFG_DBG_INST_INSERT_CTL_INSERT_MASK
 
- TPC0_EML_CFG_DBG_INST_INSERT_CTL_INSERT_SHIFT
 
- TPC0_EML_CFG_DBG_INST_INSERT_INST_MASK
 
- TPC0_EML_CFG_DBG_INST_INSERT_INST_SHIFT
 
- TPC0_EML_CFG_DBG_PADD_ADDRESS_MASK
 
- TPC0_EML_CFG_DBG_PADD_ADDRESS_SHIFT
 
- TPC0_EML_CFG_DBG_PADD_COUNT_COUNT_MASK
 
- TPC0_EML_CFG_DBG_PADD_COUNT_COUNT_SHIFT
 
- TPC0_EML_CFG_DBG_PADD_COUNT_MATCH_COUNT_MASK
 
- TPC0_EML_CFG_DBG_PADD_COUNT_MATCH_COUNT_SHIFT
 
- TPC0_EML_CFG_DBG_PADD_EN_ENABLE0_MASK
 
- TPC0_EML_CFG_DBG_PADD_EN_ENABLE0_SHIFT
 
- TPC0_EML_CFG_DBG_PADD_EN_ENABLE1_MASK
 
- TPC0_EML_CFG_DBG_PADD_EN_ENABLE1_SHIFT
 
- TPC0_EML_CFG_DBG_PADD_EN_ENABLE2_MASK
 
- TPC0_EML_CFG_DBG_PADD_EN_ENABLE2_SHIFT
 
- TPC0_EML_CFG_DBG_PADD_EN_ENABLE3_MASK
 
- TPC0_EML_CFG_DBG_PADD_EN_ENABLE3_SHIFT
 
- TPC0_EML_CFG_DBG_PADD_EN_ENABLE4_MASK
 
- TPC0_EML_CFG_DBG_PADD_EN_ENABLE4_SHIFT
 
- TPC0_EML_CFG_DBG_PADD_EN_ENABLE5_MASK
 
- TPC0_EML_CFG_DBG_PADD_EN_ENABLE5_SHIFT
 
- TPC0_EML_CFG_DBG_PADD_EN_ENABLE6_MASK
 
- TPC0_EML_CFG_DBG_PADD_EN_ENABLE6_SHIFT
 
- TPC0_EML_CFG_DBG_PADD_EN_ENABLE7_MASK
 
- TPC0_EML_CFG_DBG_PADD_EN_ENABLE7_SHIFT
 
- TPC0_EML_CFG_DBG_SPADD_COUNT_COUNT_MASK
 
- TPC0_EML_CFG_DBG_SPADD_COUNT_COUNT_SHIFT
 
- TPC0_EML_CFG_DBG_SPADD_COUNT_MATCH_COUNT_MASK
 
- TPC0_EML_CFG_DBG_SPADD_COUNT_MATCH_COUNT_SHIFT
 
- TPC0_EML_CFG_DBG_SPADD_EN_ENABLE0_MASK
 
- TPC0_EML_CFG_DBG_SPADD_EN_ENABLE0_SHIFT
 
- TPC0_EML_CFG_DBG_SPADD_EN_ENABLE1_MASK
 
- TPC0_EML_CFG_DBG_SPADD_EN_ENABLE1_SHIFT
 
- TPC0_EML_CFG_DBG_SPADD_EN_RW_N0_MASK
 
- TPC0_EML_CFG_DBG_SPADD_EN_RW_N0_SHIFT
 
- TPC0_EML_CFG_DBG_SPADD_EN_RW_N1_MASK
 
- TPC0_EML_CFG_DBG_SPADD_EN_RW_N1_SHIFT
 
- TPC0_EML_CFG_DBG_SPADD_HIGH_ADDRESS_MASK
 
- TPC0_EML_CFG_DBG_SPADD_HIGH_ADDRESS_SHIFT
 
- TPC0_EML_CFG_DBG_SPADD_LOW_ADDRESS_MASK
 
- TPC0_EML_CFG_DBG_SPADD_LOW_ADDRESS_SHIFT
 
- TPC0_EML_CFG_DBG_SPDATA_COUNT_COUNT_MASK
 
- TPC0_EML_CFG_DBG_SPDATA_COUNT_COUNT_SHIFT
 
- TPC0_EML_CFG_DBG_SPDATA_COUNT_MATCH_MATCH_MASK
 
- TPC0_EML_CFG_DBG_SPDATA_COUNT_MATCH_MATCH_SHIFT
 
- TPC0_EML_CFG_DBG_SPDATA_DATA_MASK
 
- TPC0_EML_CFG_DBG_SPDATA_DATA_SHIFT
 
- TPC0_EML_CFG_DBG_SPDATA_EN_ENABLE0_MASK
 
- TPC0_EML_CFG_DBG_SPDATA_EN_ENABLE0_SHIFT
 
- TPC0_EML_CFG_DBG_SPDATA_EN_ENABLE1_MASK
 
- TPC0_EML_CFG_DBG_SPDATA_EN_ENABLE1_SHIFT
 
- TPC0_EML_CFG_DBG_SPDATA_EN_RW_N0_MASK
 
- TPC0_EML_CFG_DBG_SPDATA_EN_RW_N0_SHIFT
 
- TPC0_EML_CFG_DBG_SPDATA_EN_RW_N1_MASK
 
- TPC0_EML_CFG_DBG_SPDATA_EN_RW_N1_SHIFT
 
- TPC0_EML_CFG_DBG_STS_CORE_READY_MASK
 
- TPC0_EML_CFG_DBG_STS_CORE_READY_SHIFT
 
- TPC0_EML_CFG_DBG_STS_DBG_CAUSE_MASK
 
- TPC0_EML_CFG_DBG_STS_DBG_CAUSE_SHIFT
 
- TPC0_EML_CFG_DBG_STS_DBG_MODE_MASK
 
- TPC0_EML_CFG_DBG_STS_DBG_MODE_SHIFT
 
- TPC0_EML_CFG_DBG_STS_DCACHE_IDLE_MASK
 
- TPC0_EML_CFG_DBG_STS_DCACHE_IDLE_SHIFT
 
- TPC0_EML_CFG_DBG_STS_DURING_KERNEL_MASK
 
- TPC0_EML_CFG_DBG_STS_DURING_KERNEL_SHIFT
 
- TPC0_EML_CFG_DBG_STS_ICACHE_IDLE_MASK
 
- TPC0_EML_CFG_DBG_STS_ICACHE_IDLE_SHIFT
 
- TPC0_EML_CFG_DBG_STS_MSS_IDLE_MASK
 
- TPC0_EML_CFG_DBG_STS_MSS_IDLE_SHIFT
 
- TPC0_EML_CFG_DBG_STS_QM_IDLE_MASK
 
- TPC0_EML_CFG_DBG_STS_QM_IDLE_SHIFT
 
- TPC0_EML_CFG_DBG_STS_WQ_IDLE_MASK
 
- TPC0_EML_CFG_DBG_STS_WQ_IDLE_SHIFT
 
- TPC0_EML_CFG_DBG_VPADD_COUNT_COUNT_MASK
 
- TPC0_EML_CFG_DBG_VPADD_COUNT_COUNT_SHIFT
 
- TPC0_EML_CFG_DBG_VPADD_COUNT_MATCH_COUNT_MASK
 
- TPC0_EML_CFG_DBG_VPADD_COUNT_MATCH_COUNT_SHIFT
 
- TPC0_EML_CFG_DBG_VPADD_EN_ENABLE0_MASK
 
- TPC0_EML_CFG_DBG_VPADD_EN_ENABLE0_SHIFT
 
- TPC0_EML_CFG_DBG_VPADD_EN_ENABLE1_MASK
 
- TPC0_EML_CFG_DBG_VPADD_EN_ENABLE1_SHIFT
 
- TPC0_EML_CFG_DBG_VPADD_EN_RW_N0_MASK
 
- TPC0_EML_CFG_DBG_VPADD_EN_RW_N0_SHIFT
 
- TPC0_EML_CFG_DBG_VPADD_EN_RW_N1_MASK
 
- TPC0_EML_CFG_DBG_VPADD_EN_RW_N1_SHIFT
 
- TPC0_EML_CFG_DBG_VPADD_HIGH_ADDRESS_MASK
 
- TPC0_EML_CFG_DBG_VPADD_HIGH_ADDRESS_SHIFT
 
- TPC0_EML_CFG_DBG_VPADD_LOW_ADDRESS_MASK
 
- TPC0_EML_CFG_DBG_VPADD_LOW_ADDRESS_SHIFT
 
- TPC0_EML_CFG_MAX_OFFSET
 
- TPC0_EML_CFG_RTTCONFIG_PRIO_MASK
 
- TPC0_EML_CFG_RTTCONFIG_PRIO_SHIFT
 
- TPC0_EML_CFG_RTTCONFIG_TR_EN_MASK
 
- TPC0_EML_CFG_RTTCONFIG_TR_EN_SHIFT
 
- TPC0_EML_CFG_RTTPREDICATE_GEN_MASK
 
- TPC0_EML_CFG_RTTPREDICATE_GEN_SHIFT
 
- TPC0_EML_CFG_RTTPREDICATE_INTV_INTERVAL_MASK
 
- TPC0_EML_CFG_RTTPREDICATE_INTV_INTERVAL_SHIFT
 
- TPC0_EML_CFG_RTTPREDICATE_SPRF_MASK_MASK
 
- TPC0_EML_CFG_RTTPREDICATE_SPRF_MASK_SHIFT
 
- TPC0_EML_CFG_RTTPREDICATE_TR_EN_MASK
 
- TPC0_EML_CFG_RTTPREDICATE_TR_EN_SHIFT
 
- TPC0_EML_CFG_RTTPREDICATE_USE_INTERVAL_MASK
 
- TPC0_EML_CFG_RTTPREDICATE_USE_INTERVAL_SHIFT
 
- TPC0_EML_CFG_RTTTS_COMPRESS_EN_MASK
 
- TPC0_EML_CFG_RTTTS_COMPRESS_EN_SHIFT
 
- TPC0_EML_CFG_RTTTS_GEN_MASK
 
- TPC0_EML_CFG_RTTTS_GEN_SHIFT
 
- TPC0_EML_CFG_RTTTS_INTV_INTERVAL_MASK
 
- TPC0_EML_CFG_RTTTS_INTV_INTERVAL_SHIFT
 
- TPC0_EML_CFG_RTTTS_TR_EN_MASK
 
- TPC0_EML_CFG_RTTTS_TR_EN_SHIFT
 
- TPC0_EML_CFG_SECTION
 
- TPC0_EML_CS_MAX_OFFSET
 
- TPC0_EML_CS_SECTION
 
- TPC0_EML_CTI_MAX_OFFSET
 
- TPC0_EML_CTI_SECTION
 
- TPC0_EML_ETF_MAX_OFFSET
 
- TPC0_EML_ETF_SECTION
 
- TPC0_EML_ETM_R4_MAX_OFFSET
 
- TPC0_EML_ETM_R4_SECTION
 
- TPC0_EML_FUNNEL_MAX_OFFSET
 
- TPC0_EML_FUNNEL_SECTION
 
- TPC0_EML_SPMU_MAX_OFFSET
 
- TPC0_EML_SPMU_SECTION
 
- TPC0_EML_STM_MAX_OFFSET
 
- TPC0_EML_STM_SECTION
 
- TPC0_NRTR_DBG_E_ARB_L_MASK
 
- TPC0_NRTR_DBG_E_ARB_L_SHIFT
 
- TPC0_NRTR_DBG_E_ARB_MAX_CREDIT_MASK
 
- TPC0_NRTR_DBG_E_ARB_MAX_CREDIT_SHIFT
 
- TPC0_NRTR_DBG_E_ARB_N_MASK
 
- TPC0_NRTR_DBG_E_ARB_N_SHIFT
 
- TPC0_NRTR_DBG_E_ARB_S_MASK
 
- TPC0_NRTR_DBG_E_ARB_S_SHIFT
 
- TPC0_NRTR_DBG_E_ARB_W_MASK
 
- TPC0_NRTR_DBG_E_ARB_W_SHIFT
 
- TPC0_NRTR_DBG_L_ARB_E_MASK
 
- TPC0_NRTR_DBG_L_ARB_E_SHIFT
 
- TPC0_NRTR_DBG_L_ARB_MAX_CREDIT_MASK
 
- TPC0_NRTR_DBG_L_ARB_MAX_CREDIT_SHIFT
 
- TPC0_NRTR_DBG_L_ARB_N_MASK
 
- TPC0_NRTR_DBG_L_ARB_N_SHIFT
 
- TPC0_NRTR_DBG_L_ARB_S_MASK
 
- TPC0_NRTR_DBG_L_ARB_S_SHIFT
 
- TPC0_NRTR_DBG_L_ARB_W_MASK
 
- TPC0_NRTR_DBG_L_ARB_W_SHIFT
 
- TPC0_NRTR_DBG_N_ARB_E_MASK
 
- TPC0_NRTR_DBG_N_ARB_E_SHIFT
 
- TPC0_NRTR_DBG_N_ARB_L_MASK
 
- TPC0_NRTR_DBG_N_ARB_L_SHIFT
 
- TPC0_NRTR_DBG_N_ARB_MAX_CREDIT_MASK
 
- TPC0_NRTR_DBG_N_ARB_MAX_CREDIT_SHIFT
 
- TPC0_NRTR_DBG_N_ARB_S_MASK
 
- TPC0_NRTR_DBG_N_ARB_S_SHIFT
 
- TPC0_NRTR_DBG_N_ARB_W_MASK
 
- TPC0_NRTR_DBG_N_ARB_W_SHIFT
 
- TPC0_NRTR_DBG_S_ARB_E_MASK
 
- TPC0_NRTR_DBG_S_ARB_E_SHIFT
 
- TPC0_NRTR_DBG_S_ARB_L_MASK
 
- TPC0_NRTR_DBG_S_ARB_L_SHIFT
 
- TPC0_NRTR_DBG_S_ARB_MAX_CREDIT_MASK
 
- TPC0_NRTR_DBG_S_ARB_MAX_CREDIT_SHIFT
 
- TPC0_NRTR_DBG_S_ARB_N_MASK
 
- TPC0_NRTR_DBG_S_ARB_N_SHIFT
 
- TPC0_NRTR_DBG_S_ARB_W_MASK
 
- TPC0_NRTR_DBG_S_ARB_W_SHIFT
 
- TPC0_NRTR_DBG_W_ARB_E_MASK
 
- TPC0_NRTR_DBG_W_ARB_E_SHIFT
 
- TPC0_NRTR_DBG_W_ARB_L_MASK
 
- TPC0_NRTR_DBG_W_ARB_L_SHIFT
 
- TPC0_NRTR_DBG_W_ARB_MAX_CREDIT_MASK
 
- TPC0_NRTR_DBG_W_ARB_MAX_CREDIT_SHIFT
 
- TPC0_NRTR_DBG_W_ARB_N_MASK
 
- TPC0_NRTR_DBG_W_ARB_N_SHIFT
 
- TPC0_NRTR_DBG_W_ARB_S_MASK
 
- TPC0_NRTR_DBG_W_ARB_S_SHIFT
 
- TPC0_NRTR_HBW_MAX_CRED_RD_RQ_MASK
 
- TPC0_NRTR_HBW_MAX_CRED_RD_RQ_SHIFT
 
- TPC0_NRTR_HBW_MAX_CRED_RD_RS_MASK
 
- TPC0_NRTR_HBW_MAX_CRED_RD_RS_SHIFT
 
- TPC0_NRTR_HBW_MAX_CRED_WR_RQ_MASK
 
- TPC0_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT
 
- TPC0_NRTR_HBW_MAX_CRED_WR_RS_MASK
 
- TPC0_NRTR_HBW_MAX_CRED_WR_RS_SHIFT
 
- TPC0_NRTR_HBW_RANGE_BASE_H_VAL_MASK
 
- TPC0_NRTR_HBW_RANGE_BASE_H_VAL_SHIFT
 
- TPC0_NRTR_HBW_RANGE_BASE_L_VAL_MASK
 
- TPC0_NRTR_HBW_RANGE_BASE_L_VAL_SHIFT
 
- TPC0_NRTR_HBW_RANGE_HIT_IND_MASK
 
- TPC0_NRTR_HBW_RANGE_HIT_IND_SHIFT
 
- TPC0_NRTR_HBW_RANGE_MASK_H_VAL_MASK
 
- TPC0_NRTR_HBW_RANGE_MASK_H_VAL_SHIFT
 
- TPC0_NRTR_HBW_RANGE_MASK_L_VAL_MASK
 
- TPC0_NRTR_HBW_RANGE_MASK_L_VAL_SHIFT
 
- TPC0_NRTR_LBW_MAX_CRED_RD_RQ_MASK
 
- TPC0_NRTR_LBW_MAX_CRED_RD_RQ_SHIFT
 
- TPC0_NRTR_LBW_MAX_CRED_RD_RS_MASK
 
- TPC0_NRTR_LBW_MAX_CRED_RD_RS_SHIFT
 
- TPC0_NRTR_LBW_MAX_CRED_WR_RQ_MASK
 
- TPC0_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT
 
- TPC0_NRTR_LBW_MAX_CRED_WR_RS_MASK
 
- TPC0_NRTR_LBW_MAX_CRED_WR_RS_SHIFT
 
- TPC0_NRTR_LBW_RANGE_BASE_VAL_MASK
 
- TPC0_NRTR_LBW_RANGE_BASE_VAL_SHIFT
 
- TPC0_NRTR_LBW_RANGE_HIT_IND_MASK
 
- TPC0_NRTR_LBW_RANGE_HIT_IND_SHIFT
 
- TPC0_NRTR_LBW_RANGE_MASK_VAL_MASK
 
- TPC0_NRTR_LBW_RANGE_MASK_VAL_SHIFT
 
- TPC0_NRTR_MAX_OFFSET
 
- TPC0_NRTR_NON_LIN_SCRAMB_EN_MASK
 
- TPC0_NRTR_NON_LIN_SCRAMB_EN_SHIFT
 
- TPC0_NRTR_RGLTR_RD_EN_MASK
 
- TPC0_NRTR_RGLTR_RD_EN_SHIFT
 
- TPC0_NRTR_RGLTR_RD_RESULT_VAL_MASK
 
- TPC0_NRTR_RGLTR_RD_RESULT_VAL_SHIFT
 
- TPC0_NRTR_RGLTR_WR_EN_MASK
 
- TPC0_NRTR_RGLTR_WR_EN_SHIFT
 
- TPC0_NRTR_RGLTR_WR_RESULT_VAL_MASK
 
- TPC0_NRTR_RGLTR_WR_RESULT_VAL_SHIFT
 
- TPC0_NRTR_SCRAMB_EN_VAL_MASK
 
- TPC0_NRTR_SCRAMB_EN_VAL_SHIFT
 
- TPC0_NRTR_SECTION
 
- TPC0_NRTR_SPLIT_CFG_B2B_OPT_MASK
 
- TPC0_NRTR_SPLIT_CFG_B2B_OPT_SHIFT
 
- TPC0_NRTR_SPLIT_CFG_DEFAULT_MESH_MASK
 
- TPC0_NRTR_SPLIT_CFG_DEFAULT_MESH_SHIFT
 
- TPC0_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_MASK
 
- TPC0_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_SHIFT
 
- TPC0_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_MASK
 
- TPC0_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_SHIFT
 
- TPC0_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_MASK
 
- TPC0_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_SHIFT
 
- TPC0_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_MASK
 
- TPC0_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_SHIFT
 
- TPC0_NRTR_SPLIT_COEF_VAL_MASK
 
- TPC0_NRTR_SPLIT_COEF_VAL_SHIFT
 
- TPC0_NRTR_SPLIT_RD_RST_TOKEN_VAL_MASK
 
- TPC0_NRTR_SPLIT_RD_RST_TOKEN_VAL_SHIFT
 
- TPC0_NRTR_SPLIT_RD_SAT_VAL_MASK
 
- TPC0_NRTR_SPLIT_RD_SAT_VAL_SHIFT
 
- TPC0_NRTR_SPLIT_RD_TIMEOUT_VAL_MASK
 
- TPC0_NRTR_SPLIT_RD_TIMEOUT_VAL_SHIFT
 
- TPC0_NRTR_SPLIT_WR_SAT_VAL_MASK
 
- TPC0_NRTR_SPLIT_WR_SAT_VAL_SHIFT
 
- TPC0_NRTR_SPLIT_WR_TIMEOUT_VAL_MASK
 
- TPC0_NRTR_SPLIT_WR_TIMEOUT_VAL_SHIFT
 
- TPC0_NRTR_WPLIT_WR_TST_TOLEN_VAL_MASK
 
- TPC0_NRTR_WPLIT_WR_TST_TOLEN_VAL_SHIFT
 
- TPC0_QMAN_BASE_OFFSET
 
- TPC0_QM_CP_BARRIER_CFG_EBGUARD_MASK
 
- TPC0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT
 
- TPC0_QM_CP_CURRENT_INST_HI_VAL_MASK
 
- TPC0_QM_CP_CURRENT_INST_HI_VAL_SHIFT
 
- TPC0_QM_CP_CURRENT_INST_LO_VAL_MASK
 
- TPC0_QM_CP_CURRENT_INST_LO_VAL_SHIFT
 
- TPC0_QM_CP_DBG_0_VAL_MASK
 
- TPC0_QM_CP_DBG_0_VAL_SHIFT
 
- TPC0_QM_CP_FENCE0_CNT_VAL_MASK
 
- TPC0_QM_CP_FENCE0_CNT_VAL_SHIFT
 
- TPC0_QM_CP_FENCE0_RDATA_INC_VAL_MASK
 
- TPC0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT
 
- TPC0_QM_CP_FENCE1_CNT_VAL_MASK
 
- TPC0_QM_CP_FENCE1_CNT_VAL_SHIFT
 
- TPC0_QM_CP_FENCE1_RDATA_INC_VAL_MASK
 
- TPC0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT
 
- TPC0_QM_CP_FENCE2_CNT_VAL_MASK
 
- TPC0_QM_CP_FENCE2_CNT_VAL_SHIFT
 
- TPC0_QM_CP_FENCE2_RDATA_INC_VAL_MASK
 
- TPC0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT
 
- TPC0_QM_CP_FENCE3_CNT_VAL_MASK
 
- TPC0_QM_CP_FENCE3_CNT_VAL_SHIFT
 
- TPC0_QM_CP_FENCE3_RDATA_INC_VAL_MASK
 
- TPC0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT
 
- TPC0_QM_CP_LDMA_COMMIT_OFFSET_VAL_MASK
 
- TPC0_QM_CP_LDMA_COMMIT_OFFSET_VAL_SHIFT
 
- TPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET_VAL_MASK
 
- TPC0_QM_CP_LDMA_DST_BASE_HI_OFFSET_VAL_SHIFT
 
- TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK
 
- TPC0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT
 
- TPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_MASK
 
- TPC0_QM_CP_LDMA_SRC_BASE_HI_OFFSET_VAL_SHIFT
 
- TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK
 
- TPC0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT
 
- TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK
 
- TPC0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT
 
- TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK
 
- TPC0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT
 
- TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK
 
- TPC0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT
 
- TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK
 
- TPC0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT
 
- TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK
 
- TPC0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT
 
- TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK
 
- TPC0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT
 
- TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK
 
- TPC0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT
 
- TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK
 
- TPC0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT
 
- TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK
 
- TPC0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT
 
- TPC0_QM_CP_STS_ERDY_MASK
 
- TPC0_QM_CP_STS_ERDY_SHIFT
 
- TPC0_QM_CP_STS_FENCE_ID_MASK
 
- TPC0_QM_CP_STS_FENCE_ID_SHIFT
 
- TPC0_QM_CP_STS_FENCE_IN_PROGRESS_MASK
 
- TPC0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT
 
- TPC0_QM_CP_STS_MRDY_MASK
 
- TPC0_QM_CP_STS_MRDY_SHIFT
 
- TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK
 
- TPC0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT
 
- TPC0_QM_CP_STS_RRDY_MASK
 
- TPC0_QM_CP_STS_RRDY_SHIFT
 
- TPC0_QM_CP_STS_SW_STOP_MASK
 
- TPC0_QM_CP_STS_SW_STOP_SHIFT
 
- TPC0_QM_CQ_ARUSER_NOSNOOP_MASK
 
- TPC0_QM_CQ_ARUSER_NOSNOOP_SHIFT
 
- TPC0_QM_CQ_ARUSER_WORD_MASK
 
- TPC0_QM_CQ_ARUSER_WORD_SHIFT
 
- TPC0_QM_CQ_BUF_ADDR_VAL_MASK
 
- TPC0_QM_CQ_BUF_ADDR_VAL_SHIFT
 
- TPC0_QM_CQ_BUF_RDATA_VAL_MASK
 
- TPC0_QM_CQ_BUF_RDATA_VAL_SHIFT
 
- TPC0_QM_CQ_CFG0_RESERVED_MASK
 
- TPC0_QM_CQ_CFG0_RESERVED_SHIFT
 
- TPC0_QM_CQ_CFG1_CREDIT_LIM_MASK
 
- TPC0_QM_CQ_CFG1_CREDIT_LIM_SHIFT
 
- TPC0_QM_CQ_CFG1_MAX_INFLIGHT_MASK
 
- TPC0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT
 
- TPC0_QM_CQ_CTL_CTL_MASK
 
- TPC0_QM_CQ_CTL_CTL_SHIFT
 
- TPC0_QM_CQ_CTL_RPT_MASK
 
- TPC0_QM_CQ_CTL_RPT_SHIFT
 
- TPC0_QM_CQ_CTL_STS_CTL_MASK
 
- TPC0_QM_CQ_CTL_STS_CTL_SHIFT
 
- TPC0_QM_CQ_CTL_STS_RPT_MASK
 
- TPC0_QM_CQ_CTL_STS_RPT_SHIFT
 
- TPC0_QM_CQ_IFIFO_CNT_VAL_MASK
 
- TPC0_QM_CQ_IFIFO_CNT_VAL_SHIFT
 
- TPC0_QM_CQ_PTR_HI_STS_VAL_MASK
 
- TPC0_QM_CQ_PTR_HI_STS_VAL_SHIFT
 
- TPC0_QM_CQ_PTR_HI_VAL_MASK
 
- TPC0_QM_CQ_PTR_HI_VAL_SHIFT
 
- TPC0_QM_CQ_PTR_LO_STS_VAL_MASK
 
- TPC0_QM_CQ_PTR_LO_STS_VAL_SHIFT
 
- TPC0_QM_CQ_PTR_LO_VAL_MASK
 
- TPC0_QM_CQ_PTR_LO_VAL_SHIFT
 
- TPC0_QM_CQ_RD_RATE_LIM_EN_VAL_MASK
 
- TPC0_QM_CQ_RD_RATE_LIM_EN_VAL_SHIFT
 
- TPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK
 
- TPC0_QM_CQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT
 
- TPC0_QM_CQ_RD_RATE_LIM_SAT_VAL_MASK
 
- TPC0_QM_CQ_RD_RATE_LIM_SAT_VAL_SHIFT
 
- TPC0_QM_CQ_RD_RATE_LIM_TOUT_VAL_MASK
 
- TPC0_QM_CQ_RD_RATE_LIM_TOUT_VAL_SHIFT
 
- TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_MASK
 
- TPC0_QM_CQ_STS0_CQ_CREDIT_CNT_SHIFT
 
- TPC0_QM_CQ_STS0_CQ_FREE_CNT_MASK
 
- TPC0_QM_CQ_STS0_CQ_FREE_CNT_SHIFT
 
- TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_MASK
 
- TPC0_QM_CQ_STS1_CQ_BUF_EMPTY_SHIFT
 
- TPC0_QM_CQ_STS1_CQ_BUSY_MASK
 
- TPC0_QM_CQ_STS1_CQ_BUSY_SHIFT
 
- TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_MASK
 
- TPC0_QM_CQ_STS1_CQ_INFLIGHT_CNT_SHIFT
 
- TPC0_QM_CQ_TSIZE_STS_VAL_MASK
 
- TPC0_QM_CQ_TSIZE_STS_VAL_SHIFT
 
- TPC0_QM_CQ_TSIZE_VAL_MASK
 
- TPC0_QM_CQ_TSIZE_VAL_SHIFT
 
- TPC0_QM_GLBL_CFG0_CP_EN_MASK
 
- TPC0_QM_GLBL_CFG0_CP_EN_SHIFT
 
- TPC0_QM_GLBL_CFG0_CQF_EN_MASK
 
- TPC0_QM_GLBL_CFG0_CQF_EN_SHIFT
 
- TPC0_QM_GLBL_CFG0_DMA_EN_MASK
 
- TPC0_QM_GLBL_CFG0_DMA_EN_SHIFT
 
- TPC0_QM_GLBL_CFG0_PQF_EN_MASK
 
- TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT
 
- TPC0_QM_GLBL_CFG1_CP_FLUSH_MASK
 
- TPC0_QM_GLBL_CFG1_CP_FLUSH_SHIFT
 
- TPC0_QM_GLBL_CFG1_CP_STOP_MASK
 
- TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT
 
- TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK
 
- TPC0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT
 
- TPC0_QM_GLBL_CFG1_CQF_STOP_MASK
 
- TPC0_QM_GLBL_CFG1_CQF_STOP_SHIFT
 
- TPC0_QM_GLBL_CFG1_DMA_FLUSH_MASK
 
- TPC0_QM_GLBL_CFG1_DMA_FLUSH_SHIFT
 
- TPC0_QM_GLBL_CFG1_DMA_STOP_MASK
 
- TPC0_QM_GLBL_CFG1_DMA_STOP_SHIFT
 
- TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK
 
- TPC0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT
 
- TPC0_QM_GLBL_CFG1_PQF_STOP_MASK
 
- TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT
 
- TPC0_QM_GLBL_ERR_ADDR_HI_VAL_MASK
 
- TPC0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT
 
- TPC0_QM_GLBL_ERR_ADDR_LO_VAL_MASK
 
- TPC0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT
 
- TPC0_QM_GLBL_ERR_CFG_CP_ERR_INT_EN_MASK
 
- TPC0_QM_GLBL_ERR_CFG_CP_ERR_INT_EN_SHIFT
 
- TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK
 
- TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT
 
- TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK
 
- TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT
 
- TPC0_QM_GLBL_ERR_CFG_CQF_ERR_INT_EN_MASK
 
- TPC0_QM_GLBL_ERR_CFG_CQF_ERR_INT_EN_SHIFT
 
- TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK
 
- TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT
 
- TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK
 
- TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT
 
- TPC0_QM_GLBL_ERR_CFG_DMA_ERR_INT_EN_MASK
 
- TPC0_QM_GLBL_ERR_CFG_DMA_ERR_INT_EN_SHIFT
 
- TPC0_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_MASK
 
- TPC0_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT
 
- TPC0_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_MASK
 
- TPC0_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT
 
- TPC0_QM_GLBL_ERR_CFG_PQF_ERR_INT_EN_MASK
 
- TPC0_QM_GLBL_ERR_CFG_PQF_ERR_INT_EN_SHIFT
 
- TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK
 
- TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT
 
- TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK
 
- TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT
 
- TPC0_QM_GLBL_ERR_WDATA_VAL_MASK
 
- TPC0_QM_GLBL_ERR_WDATA_VAL_SHIFT
 
- TPC0_QM_GLBL_NON_SECURE_PROPS_ASID_MASK
 
- TPC0_QM_GLBL_NON_SECURE_PROPS_ASID_SHIFT
 
- TPC0_QM_GLBL_NON_SECURE_PROPS_MMBP_MASK
 
- TPC0_QM_GLBL_NON_SECURE_PROPS_MMBP_SHIFT
 
- TPC0_QM_GLBL_PROT_CP_ERR_PROT_MASK
 
- TPC0_QM_GLBL_PROT_CP_ERR_PROT_SHIFT
 
- TPC0_QM_GLBL_PROT_CP_PROT_MASK
 
- TPC0_QM_GLBL_PROT_CP_PROT_SHIFT
 
- TPC0_QM_GLBL_PROT_CQF_ERR_PROT_MASK
 
- TPC0_QM_GLBL_PROT_CQF_ERR_PROT_SHIFT
 
- TPC0_QM_GLBL_PROT_CQF_PROT_MASK
 
- TPC0_QM_GLBL_PROT_CQF_PROT_SHIFT
 
- TPC0_QM_GLBL_PROT_DMA_ERR_PROT_MASK
 
- TPC0_QM_GLBL_PROT_DMA_ERR_PROT_SHIFT
 
- TPC0_QM_GLBL_PROT_DMA_PROT_MASK
 
- TPC0_QM_GLBL_PROT_DMA_PROT_SHIFT
 
- TPC0_QM_GLBL_PROT_PQF_ERR_PROT_MASK
 
- TPC0_QM_GLBL_PROT_PQF_ERR_PROT_SHIFT
 
- TPC0_QM_GLBL_PROT_PQF_PROT_MASK
 
- TPC0_QM_GLBL_PROT_PQF_PROT_SHIFT
 
- TPC0_QM_GLBL_SECURE_PROPS_ASID_MASK
 
- TPC0_QM_GLBL_SECURE_PROPS_ASID_SHIFT
 
- TPC0_QM_GLBL_SECURE_PROPS_MMBP_MASK
 
- TPC0_QM_GLBL_SECURE_PROPS_MMBP_SHIFT
 
- TPC0_QM_GLBL_STS0_CP_IDLE_MASK
 
- TPC0_QM_GLBL_STS0_CP_IDLE_SHIFT
 
- TPC0_QM_GLBL_STS0_CP_IS_STOP_MASK
 
- TPC0_QM_GLBL_STS0_CP_IS_STOP_SHIFT
 
- TPC0_QM_GLBL_STS0_CQF_IDLE_MASK
 
- TPC0_QM_GLBL_STS0_CQF_IDLE_SHIFT
 
- TPC0_QM_GLBL_STS0_CQF_IS_STOP_MASK
 
- TPC0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT
 
- TPC0_QM_GLBL_STS0_DMA_IDLE_MASK
 
- TPC0_QM_GLBL_STS0_DMA_IDLE_SHIFT
 
- TPC0_QM_GLBL_STS0_DMA_IS_STOP_MASK
 
- TPC0_QM_GLBL_STS0_DMA_IS_STOP_SHIFT
 
- TPC0_QM_GLBL_STS0_PQF_IDLE_MASK
 
- TPC0_QM_GLBL_STS0_PQF_IDLE_SHIFT
 
- TPC0_QM_GLBL_STS0_PQF_IS_STOP_MASK
 
- TPC0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT
 
- TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_MASK
 
- TPC0_QM_GLBL_STS1_CP_MSG_WR_ERR_SHIFT
 
- TPC0_QM_GLBL_STS1_CP_RD_ERR_MASK
 
- TPC0_QM_GLBL_STS1_CP_RD_ERR_SHIFT
 
- TPC0_QM_GLBL_STS1_CP_STOP_OP_MASK
 
- TPC0_QM_GLBL_STS1_CP_STOP_OP_SHIFT
 
- TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_MASK
 
- TPC0_QM_GLBL_STS1_CP_UNDEF_CMD_ERR_SHIFT
 
- TPC0_QM_GLBL_STS1_CQF_RD_ERR_MASK
 
- TPC0_QM_GLBL_STS1_CQF_RD_ERR_SHIFT
 
- TPC0_QM_GLBL_STS1_DMA_RD_ERR_MASK
 
- TPC0_QM_GLBL_STS1_DMA_RD_ERR_SHIFT
 
- TPC0_QM_GLBL_STS1_DMA_RD_MSG_ERR_MASK
 
- TPC0_QM_GLBL_STS1_DMA_RD_MSG_ERR_SHIFT
 
- TPC0_QM_GLBL_STS1_DMA_WR_ERR_MASK
 
- TPC0_QM_GLBL_STS1_DMA_WR_ERR_SHIFT
 
- TPC0_QM_GLBL_STS1_DMA_WR_MSG_ERR_MASK
 
- TPC0_QM_GLBL_STS1_DMA_WR_MSG_ERR_SHIFT
 
- TPC0_QM_GLBL_STS1_PQF_RD_ERR_MASK
 
- TPC0_QM_GLBL_STS1_PQF_RD_ERR_SHIFT
 
- TPC0_QM_MAX_OFFSET
 
- TPC0_QM_PQ_ARUSER_NOSNOOP_MASK
 
- TPC0_QM_PQ_ARUSER_NOSNOOP_SHIFT
 
- TPC0_QM_PQ_ARUSER_WORD_MASK
 
- TPC0_QM_PQ_ARUSER_WORD_SHIFT
 
- TPC0_QM_PQ_BASE_HI_VAL_MASK
 
- TPC0_QM_PQ_BASE_HI_VAL_SHIFT
 
- TPC0_QM_PQ_BASE_LO_VAL_MASK
 
- TPC0_QM_PQ_BASE_LO_VAL_SHIFT
 
- TPC0_QM_PQ_BUF_ADDR_VAL_MASK
 
- TPC0_QM_PQ_BUF_ADDR_VAL_SHIFT
 
- TPC0_QM_PQ_BUF_RDATA_VAL_MASK
 
- TPC0_QM_PQ_BUF_RDATA_VAL_SHIFT
 
- TPC0_QM_PQ_CFG0_RESERVED_MASK
 
- TPC0_QM_PQ_CFG0_RESERVED_SHIFT
 
- TPC0_QM_PQ_CFG1_CREDIT_LIM_MASK
 
- TPC0_QM_PQ_CFG1_CREDIT_LIM_SHIFT
 
- TPC0_QM_PQ_CFG1_MAX_INFLIGHT_MASK
 
- TPC0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT
 
- TPC0_QM_PQ_CI_VAL_MASK
 
- TPC0_QM_PQ_CI_VAL_SHIFT
 
- TPC0_QM_PQ_PI_VAL_MASK
 
- TPC0_QM_PQ_PI_VAL_SHIFT
 
- TPC0_QM_PQ_PUSH0_PTR_LO_MASK
 
- TPC0_QM_PQ_PUSH0_PTR_LO_SHIFT
 
- TPC0_QM_PQ_PUSH1_PTR_HI_MASK
 
- TPC0_QM_PQ_PUSH1_PTR_HI_SHIFT
 
- TPC0_QM_PQ_PUSH2_TSIZE_MASK
 
- TPC0_QM_PQ_PUSH2_TSIZE_SHIFT
 
- TPC0_QM_PQ_PUSH3_CTL_MASK
 
- TPC0_QM_PQ_PUSH3_CTL_SHIFT
 
- TPC0_QM_PQ_PUSH3_RPT_MASK
 
- TPC0_QM_PQ_PUSH3_RPT_SHIFT
 
- TPC0_QM_PQ_RD_RATE_LIM_EN_VAL_MASK
 
- TPC0_QM_PQ_RD_RATE_LIM_EN_VAL_SHIFT
 
- TPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN_VAL_MASK
 
- TPC0_QM_PQ_RD_RATE_LIM_RST_TOKEN_VAL_SHIFT
 
- TPC0_QM_PQ_RD_RATE_LIM_SAT_VAL_MASK
 
- TPC0_QM_PQ_RD_RATE_LIM_SAT_VAL_SHIFT
 
- TPC0_QM_PQ_RD_RATE_LIM_TOUT_VAL_MASK
 
- TPC0_QM_PQ_RD_RATE_LIM_TOUT_VAL_SHIFT
 
- TPC0_QM_PQ_SIZE_VAL_MASK
 
- TPC0_QM_PQ_SIZE_VAL_SHIFT
 
- TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_MASK
 
- TPC0_QM_PQ_STS0_PQ_CREDIT_CNT_SHIFT
 
- TPC0_QM_PQ_STS0_PQ_FREE_CNT_MASK
 
- TPC0_QM_PQ_STS0_PQ_FREE_CNT_SHIFT
 
- TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_MASK
 
- TPC0_QM_PQ_STS1_PQ_BUF_EMPTY_SHIFT
 
- TPC0_QM_PQ_STS1_PQ_BUSY_MASK
 
- TPC0_QM_PQ_STS1_PQ_BUSY_SHIFT
 
- TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_MASK
 
- TPC0_QM_PQ_STS1_PQ_INFLIGHT_CNT_SHIFT
 
- TPC0_QM_SECTION
 
- TPC0_RD_REGULATOR_MAX_OFFSET
 
- TPC0_RD_REGULATOR_SECTION
 
- TPC0_WR_REGULATOR_MAX_OFFSET
 
- TPC0_WR_REGULATOR_SECTION
 
- TPC1_CFG_MAX_OFFSET
 
- TPC1_CFG_SECTION
 
- TPC1_CFG_TPC_STALL_V_SHIFT
 
- TPC1_CMDQ_MAX_OFFSET
 
- TPC1_CMDQ_SECTION
 
- TPC1_EML_BUSMON_0_MAX_OFFSET
 
- TPC1_EML_BUSMON_0_SECTION
 
- TPC1_EML_BUSMON_1_MAX_OFFSET
 
- TPC1_EML_BUSMON_1_SECTION
 
- TPC1_EML_BUSMON_2_MAX_OFFSET
 
- TPC1_EML_BUSMON_2_SECTION
 
- TPC1_EML_BUSMON_3_MAX_OFFSET
 
- TPC1_EML_BUSMON_3_SECTION
 
- TPC1_EML_CFG_MAX_OFFSET
 
- TPC1_EML_CFG_SECTION
 
- TPC1_EML_CS_MAX_OFFSET
 
- TPC1_EML_CS_SECTION
 
- TPC1_EML_CTI_MAX_OFFSET
 
- TPC1_EML_CTI_SECTION
 
- TPC1_EML_ETF_MAX_OFFSET
 
- TPC1_EML_ETF_SECTION
 
- TPC1_EML_ETM_R4_MAX_OFFSET
 
- TPC1_EML_ETM_R4_SECTION
 
- TPC1_EML_FUNNEL_MAX_OFFSET
 
- TPC1_EML_FUNNEL_SECTION
 
- TPC1_EML_SPMU_MAX_OFFSET
 
- TPC1_EML_SPMU_SECTION
 
- TPC1_EML_STM_MAX_OFFSET
 
- TPC1_EML_STM_SECTION
 
- TPC1_QMAN_BASE_OFFSET
 
- TPC1_QM_MAX_OFFSET
 
- TPC1_QM_SECTION
 
- TPC1_RD_REGULATOR_MAX_OFFSET
 
- TPC1_RD_REGULATOR_SECTION
 
- TPC1_RTR_FUNNEL_MAX_OFFSET
 
- TPC1_RTR_FUNNEL_SECTION
 
- TPC1_RTR_MAX_OFFSET
 
- TPC1_RTR_SECTION
 
- TPC1_WR_REGULATOR_MAX_OFFSET
 
- TPC1_WR_REGULATOR_SECTION
 
- TPC2_CFG_MAX_OFFSET
 
- TPC2_CFG_SECTION
 
- TPC2_CFG_TPC_STALL_V_SHIFT
 
- TPC2_CMDQ_MAX_OFFSET
 
- TPC2_CMDQ_SECTION
 
- TPC2_EML_BUSMON_0_MAX_OFFSET
 
- TPC2_EML_BUSMON_0_SECTION
 
- TPC2_EML_BUSMON_1_MAX_OFFSET
 
- TPC2_EML_BUSMON_1_SECTION
 
- TPC2_EML_BUSMON_2_MAX_OFFSET
 
- TPC2_EML_BUSMON_2_SECTION
 
- TPC2_EML_BUSMON_3_MAX_OFFSET
 
- TPC2_EML_BUSMON_3_SECTION
 
- TPC2_EML_CFG_MAX_OFFSET
 
- TPC2_EML_CFG_SECTION
 
- TPC2_EML_CS_MAX_OFFSET
 
- TPC2_EML_CS_SECTION
 
- TPC2_EML_CTI_MAX_OFFSET
 
- TPC2_EML_CTI_SECTION
 
- TPC2_EML_ETF_MAX_OFFSET
 
- TPC2_EML_ETF_SECTION
 
- TPC2_EML_ETM_R4_MAX_OFFSET
 
- TPC2_EML_ETM_R4_SECTION
 
- TPC2_EML_FUNNEL_MAX_OFFSET
 
- TPC2_EML_FUNNEL_SECTION
 
- TPC2_EML_SPMU_MAX_OFFSET
 
- TPC2_EML_SPMU_SECTION
 
- TPC2_EML_STM_MAX_OFFSET
 
- TPC2_EML_STM_SECTION
 
- TPC2_QMAN_BASE_OFFSET
 
- TPC2_QM_MAX_OFFSET
 
- TPC2_QM_SECTION
 
- TPC2_RD_REGULATOR_MAX_OFFSET
 
- TPC2_RD_REGULATOR_SECTION
 
- TPC2_RTR_FUNNEL_MAX_OFFSET
 
- TPC2_RTR_FUNNEL_SECTION
 
- TPC2_RTR_MAX_OFFSET
 
- TPC2_RTR_SECTION
 
- TPC2_WR_REGULATOR_MAX_OFFSET
 
- TPC2_WR_REGULATOR_SECTION
 
- TPC3_CFG_MAX_OFFSET
 
- TPC3_CFG_SECTION
 
- TPC3_CFG_TPC_STALL_V_SHIFT
 
- TPC3_CMDQ_MAX_OFFSET
 
- TPC3_CMDQ_SECTION
 
- TPC3_EML_BUSMON_0_MAX_OFFSET
 
- TPC3_EML_BUSMON_0_SECTION
 
- TPC3_EML_BUSMON_1_MAX_OFFSET
 
- TPC3_EML_BUSMON_1_SECTION
 
- TPC3_EML_BUSMON_2_MAX_OFFSET
 
- TPC3_EML_BUSMON_2_SECTION
 
- TPC3_EML_BUSMON_3_MAX_OFFSET
 
- TPC3_EML_BUSMON_3_SECTION
 
- TPC3_EML_CFG_MAX_OFFSET
 
- TPC3_EML_CFG_SECTION
 
- TPC3_EML_CS_MAX_OFFSET
 
- TPC3_EML_CS_SECTION
 
- TPC3_EML_CTI_MAX_OFFSET
 
- TPC3_EML_CTI_SECTION
 
- TPC3_EML_ETF_MAX_OFFSET
 
- TPC3_EML_ETF_SECTION
 
- TPC3_EML_ETM_R4_MAX_OFFSET
 
- TPC3_EML_ETM_R4_SECTION
 
- TPC3_EML_FUNNEL_MAX_OFFSET
 
- TPC3_EML_FUNNEL_SECTION
 
- TPC3_EML_SPMU_MAX_OFFSET
 
- TPC3_EML_SPMU_SECTION
 
- TPC3_EML_STM_MAX_OFFSET
 
- TPC3_EML_STM_SECTION
 
- TPC3_QMAN_BASE_OFFSET
 
- TPC3_QM_MAX_OFFSET
 
- TPC3_QM_SECTION
 
- TPC3_RD_REGULATOR_MAX_OFFSET
 
- TPC3_RD_REGULATOR_SECTION
 
- TPC3_RTR_FUNNEL_MAX_OFFSET
 
- TPC3_RTR_FUNNEL_SECTION
 
- TPC3_RTR_MAX_OFFSET
 
- TPC3_RTR_SECTION
 
- TPC3_WR_REGULATOR_MAX_OFFSET
 
- TPC3_WR_REGULATOR_SECTION
 
- TPC4_CFG_MAX_OFFSET
 
- TPC4_CFG_SECTION
 
- TPC4_CFG_TPC_STALL_V_SHIFT
 
- TPC4_CMDQ_MAX_OFFSET
 
- TPC4_CMDQ_SECTION
 
- TPC4_EML_BUSMON_0_MAX_OFFSET
 
- TPC4_EML_BUSMON_0_SECTION
 
- TPC4_EML_BUSMON_1_MAX_OFFSET
 
- TPC4_EML_BUSMON_1_SECTION
 
- TPC4_EML_BUSMON_2_MAX_OFFSET
 
- TPC4_EML_BUSMON_2_SECTION
 
- TPC4_EML_BUSMON_3_MAX_OFFSET
 
- TPC4_EML_BUSMON_3_SECTION
 
- TPC4_EML_CFG_MAX_OFFSET
 
- TPC4_EML_CFG_SECTION
 
- TPC4_EML_CS_MAX_OFFSET
 
- TPC4_EML_CS_SECTION
 
- TPC4_EML_CTI_MAX_OFFSET
 
- TPC4_EML_CTI_SECTION
 
- TPC4_EML_ETF_MAX_OFFSET
 
- TPC4_EML_ETF_SECTION
 
- TPC4_EML_ETM_R4_MAX_OFFSET
 
- TPC4_EML_ETM_R4_SECTION
 
- TPC4_EML_FUNNEL_MAX_OFFSET
 
- TPC4_EML_FUNNEL_SECTION
 
- TPC4_EML_SPMU_MAX_OFFSET
 
- TPC4_EML_SPMU_SECTION
 
- TPC4_EML_STM_MAX_OFFSET
 
- TPC4_EML_STM_SECTION
 
- TPC4_QMAN_BASE_OFFSET
 
- TPC4_QM_MAX_OFFSET
 
- TPC4_QM_SECTION
 
- TPC4_RD_REGULATOR_MAX_OFFSET
 
- TPC4_RD_REGULATOR_SECTION
 
- TPC4_RTR_FUNNEL_MAX_OFFSET
 
- TPC4_RTR_FUNNEL_SECTION
 
- TPC4_RTR_MAX_OFFSET
 
- TPC4_RTR_SECTION
 
- TPC4_WR_REGULATOR_MAX_OFFSET
 
- TPC4_WR_REGULATOR_SECTION
 
- TPC5_CFG_MAX_OFFSET
 
- TPC5_CFG_SECTION
 
- TPC5_CFG_TPC_STALL_V_SHIFT
 
- TPC5_CMDQ_MAX_OFFSET
 
- TPC5_CMDQ_SECTION
 
- TPC5_EML_BUSMON_0_MAX_OFFSET
 
- TPC5_EML_BUSMON_0_SECTION
 
- TPC5_EML_BUSMON_1_MAX_OFFSET
 
- TPC5_EML_BUSMON_1_SECTION
 
- TPC5_EML_BUSMON_2_MAX_OFFSET
 
- TPC5_EML_BUSMON_2_SECTION
 
- TPC5_EML_BUSMON_3_MAX_OFFSET
 
- TPC5_EML_BUSMON_3_SECTION
 
- TPC5_EML_CFG_MAX_OFFSET
 
- TPC5_EML_CFG_SECTION
 
- TPC5_EML_CS_MAX_OFFSET
 
- TPC5_EML_CS_SECTION
 
- TPC5_EML_CTI_MAX_OFFSET
 
- TPC5_EML_CTI_SECTION
 
- TPC5_EML_ETF_MAX_OFFSET
 
- TPC5_EML_ETF_SECTION
 
- TPC5_EML_ETM_R4_MAX_OFFSET
 
- TPC5_EML_ETM_R4_SECTION
 
- TPC5_EML_FUNNEL_MAX_OFFSET
 
- TPC5_EML_FUNNEL_SECTION
 
- TPC5_EML_SPMU_MAX_OFFSET
 
- TPC5_EML_SPMU_SECTION
 
- TPC5_EML_STM_MAX_OFFSET
 
- TPC5_EML_STM_SECTION
 
- TPC5_QMAN_BASE_OFFSET
 
- TPC5_QM_MAX_OFFSET
 
- TPC5_QM_SECTION
 
- TPC5_RD_REGULATOR_MAX_OFFSET
 
- TPC5_RD_REGULATOR_SECTION
 
- TPC5_RTR_FUNNEL_MAX_OFFSET
 
- TPC5_RTR_FUNNEL_SECTION
 
- TPC5_RTR_MAX_OFFSET
 
- TPC5_RTR_SECTION
 
- TPC5_WR_REGULATOR_MAX_OFFSET
 
- TPC5_WR_REGULATOR_SECTION
 
- TPC6_CFG_MAX_OFFSET
 
- TPC6_CFG_SECTION
 
- TPC6_CFG_TPC_STALL_V_SHIFT
 
- TPC6_CMDQ_MAX_OFFSET
 
- TPC6_CMDQ_SECTION
 
- TPC6_EML_BUSMON_0_MAX_OFFSET
 
- TPC6_EML_BUSMON_0_SECTION
 
- TPC6_EML_BUSMON_1_MAX_OFFSET
 
- TPC6_EML_BUSMON_1_SECTION
 
- TPC6_EML_BUSMON_2_MAX_OFFSET
 
- TPC6_EML_BUSMON_2_SECTION
 
- TPC6_EML_BUSMON_3_MAX_OFFSET
 
- TPC6_EML_BUSMON_3_SECTION
 
- TPC6_EML_CFG_MAX_OFFSET
 
- TPC6_EML_CFG_SECTION
 
- TPC6_EML_CS_MAX_OFFSET
 
- TPC6_EML_CS_SECTION
 
- TPC6_EML_CTI_MAX_OFFSET
 
- TPC6_EML_CTI_SECTION
 
- TPC6_EML_ETF_MAX_OFFSET
 
- TPC6_EML_ETF_SECTION
 
- TPC6_EML_ETM_R4_MAX_OFFSET
 
- TPC6_EML_ETM_R4_SECTION
 
- TPC6_EML_FUNNEL_MAX_OFFSET
 
- TPC6_EML_FUNNEL_SECTION
 
- TPC6_EML_SPMU_MAX_OFFSET
 
- TPC6_EML_SPMU_SECTION
 
- TPC6_EML_STM_MAX_OFFSET
 
- TPC6_EML_STM_SECTION
 
- TPC6_QMAN_BASE_OFFSET
 
- TPC6_QM_MAX_OFFSET
 
- TPC6_QM_SECTION
 
- TPC6_RD_REGULATOR_MAX_OFFSET
 
- TPC6_RD_REGULATOR_SECTION
 
- TPC6_RTR_FUNNEL_MAX_OFFSET
 
- TPC6_RTR_FUNNEL_SECTION
 
- TPC6_RTR_MAX_OFFSET
 
- TPC6_RTR_SECTION
 
- TPC6_WR_REGULATOR_MAX_OFFSET
 
- TPC6_WR_REGULATOR_SECTION
 
- TPC7_CFG_MAX_OFFSET
 
- TPC7_CFG_SECTION
 
- TPC7_CFG_TPC_STALL_V_SHIFT
 
- TPC7_CMDQ_MAX_OFFSET
 
- TPC7_CMDQ_SECTION
 
- TPC7_EML_BUSMON_0_MAX_OFFSET
 
- TPC7_EML_BUSMON_0_SECTION
 
- TPC7_EML_BUSMON_1_MAX_OFFSET
 
- TPC7_EML_BUSMON_1_SECTION
 
- TPC7_EML_BUSMON_2_MAX_OFFSET
 
- TPC7_EML_BUSMON_2_SECTION
 
- TPC7_EML_BUSMON_3_MAX_OFFSET
 
- TPC7_EML_BUSMON_3_SECTION
 
- TPC7_EML_CFG_MAX_OFFSET
 
- TPC7_EML_CFG_SECTION
 
- TPC7_EML_CS_MAX_OFFSET
 
- TPC7_EML_CTI_MAX_OFFSET
 
- TPC7_EML_CTI_SECTION
 
- TPC7_EML_ETF_MAX_OFFSET
 
- TPC7_EML_ETF_SECTION
 
- TPC7_EML_ETM_R4_MAX_OFFSET
 
- TPC7_EML_ETM_R4_SECTION
 
- TPC7_EML_FUNNEL_MAX_OFFSET
 
- TPC7_EML_FUNNEL_SECTION
 
- TPC7_EML_SPMU_MAX_OFFSET
 
- TPC7_EML_SPMU_SECTION
 
- TPC7_EML_STM_MAX_OFFSET
 
- TPC7_EML_STM_SECTION
 
- TPC7_NRTR_MAX_OFFSET
 
- TPC7_NRTR_SECTION
 
- TPC7_QMAN_BASE_OFFSET
 
- TPC7_QM_MAX_OFFSET
 
- TPC7_QM_SECTION
 
- TPC7_RD_REGULATOR_MAX_OFFSET
 
- TPC7_RD_REGULATOR_SECTION
 
- TPC7_WR_REGULATOR_MAX_OFFSET
 
- TPC7_WR_REGULATOR_SECTION
 
- TPCC
 
- TPCC_MASK
 
- TPCI200_A_ERROR
 
- TPCI200_A_INT0
 
- TPCI200_A_INT1
 
- TPCI200_A_RESET
 
- TPCI200_A_TIMEOUT
 
- TPCI200_B_ERROR
 
- TPCI200_B_INT0
 
- TPCI200_B_INT1
 
- TPCI200_B_RESET
 
- TPCI200_B_TIMEOUT
 
- TPCI200_CFG_MEM_BAR
 
- TPCI200_CLK32
 
- TPCI200_C_ERROR
 
- TPCI200_C_INT0
 
- TPCI200_C_INT1
 
- TPCI200_C_RESET
 
- TPCI200_C_TIMEOUT
 
- TPCI200_DEVICE_ID
 
- TPCI200_D_ERROR
 
- TPCI200_D_INT0
 
- TPCI200_D_INT1
 
- TPCI200_D_RESET
 
- TPCI200_D_TIMEOUT
 
- TPCI200_ERR_INT_EN
 
- TPCI200_ID_SPACE_INTERVAL
 
- TPCI200_ID_SPACE_OFF
 
- TPCI200_ID_SPACE_SIZE
 
- TPCI200_IFACE_SIZE
 
- TPCI200_INT0_EDGE
 
- TPCI200_INT0_EN
 
- TPCI200_INT1_EDGE
 
- TPCI200_INT1_EN
 
- TPCI200_INT_SPACE_INTERVAL
 
- TPCI200_INT_SPACE_OFF
 
- TPCI200_INT_SPACE_SIZE
 
- TPCI200_IOIDINT_SIZE
 
- TPCI200_IO_ID_INT_SPACES_BAR
 
- TPCI200_IO_SPACE_INTERVAL
 
- TPCI200_IO_SPACE_OFF
 
- TPCI200_IO_SPACE_SIZE
 
- TPCI200_IP_INTERFACE_BAR
 
- TPCI200_MEM16_SPACE_BAR
 
- TPCI200_MEM16_SPACE_INTERVAL
 
- TPCI200_MEM16_SPACE_SIZE
 
- TPCI200_MEM8_SPACE_BAR
 
- TPCI200_MEM8_SPACE_INTERVAL
 
- TPCI200_MEM8_SPACE_SIZE
 
- TPCI200_NB_BAR
 
- TPCI200_NB_SLOT
 
- TPCI200_RECOVER_EN
 
- TPCI200_SLOT_INT_MASK
 
- TPCI200_SUBDEVICE_ID
 
- TPCI200_SUBVENDOR_ID
 
- TPCI200_TIME_INT_EN
 
- TPCI200_VENDOR_ID
 
- TPCP_F
 
- TPCP_S
 
- TPCP_V
 
- TPC_ACTION_DECREASE
 
- TPC_ACTION_INCREASE
 
- TPC_ACTION_NO_RESTIRCTION
 
- TPC_ACTION_STAY
 
- TPC_ALARM
 
- TPC_CFG_IDLE_MASK
 
- TPC_CMD
 
- TPC_CMDQ_IDLE_MASK
 
- TPC_CMD_SET
 
- TPC_CODE_SZ_MASK
 
- TPC_DATA_SEL
 
- TPC_DATA_SZ_MASK
 
- TPC_DEFAULT_P0
 
- TPC_DEFAULT_P1
 
- TPC_DEFAULT_P2
 
- TPC_DIR
 
- TPC_ENABLED_MASK
 
- TPC_EN_MSG
 
- TPC_GET_ALARM
 
- TPC_GET_INT
 
- TPC_INVALID
 
- TPC_IN_SZ
 
- TPC_MAX
 
- TPC_MAX_NUM
 
- TPC_MAX_PER_GPC
 
- TPC_MAX_REDUCTION
 
- TPC_NO_REDUCTION
 
- TPC_OUT_SZ
 
- TPC_P0
 
- TPC_P1
 
- TPC_PLL
 
- TPC_PLL_MAX_OFFSET
 
- TPC_PLL_SECTION
 
- TPC_PROCESS_MON_MAX_OFFSET
 
- TPC_PROCESS_MON_SECTION
 
- TPC_QMAN_LENGTH
 
- TPC_QM_IDLE_MASK
 
- TPC_THEMAL_SENSOR_MAX_OFFSET
 
- TPC_THEMAL_SENSOR_SECTION
 
- TPC_UNIT
 
- TPC_WAIT_INT
 
- TPD
 
- TPDRQ_ALIGNMENT
 
- TPDRQ_B_H
 
- TPDRQ_MASK
 
- TPDRQ_S
 
- TPDRQ_T
 
- TPD_ADDR
 
- TPD_ADDR_SHIFT
 
- TPD_ALIGNMENT
 
- TPD_BA
 
- TPD_BUFFER_ADDR_H_SET
 
- TPD_BUFFER_ADDR_L_SET
 
- TPD_BUFLEN_MASK
 
- TPD_BUFLEN_SHIFT
 
- TPD_BUF_LEN_SET
 
- TPD_CCSUMOFFSET_MASK
 
- TPD_CCSUMOFFSET_SHIFT
 
- TPD_CCSUM_EN_MASK
 
- TPD_CCSUM_EN_SHIFT
 
- TPD_CCSUM_EPAD_MASK
 
- TPD_CCSUM_EPAD_SHIFT
 
- TPD_CCSUM_OFFSET_MASK
 
- TPD_CCSUM_OFFSET_SHIFT
 
- TPD_CC_SEGMENT_EN_MASK
 
- TPD_CC_SEGMENT_EN_SHIFT
 
- TPD_CELLTYPE
 
- TPD_CLP
 
- TPD_COALESCE_MASK
 
- TPD_COALESCE_SHIFT
 
- TPD_CON_VTAG_MASK
 
- TPD_CON_VTAG_SHIFT
 
- TPD_CSX_SET
 
- TPD_CUST_CSUM_EN_MASK
 
- TPD_CUST_CSUM_EN_SHIFT
 
- TPD_CVLAN_TAG_SET
 
- TPD_CXSUMOFFSET_MASK
 
- TPD_CXSUMOFFSET_SHIFT
 
- TPD_CXSUMSTART_MASK
 
- TPD_CXSUMSTART_SHIFT
 
- TPD_CXSUM_EN_MASK
 
- TPD_CXSUM_EN_SHIFT
 
- TPD_CXSUM_OFFSET_SET
 
- TPD_DMAINT_MASK
 
- TPD_DMAINT_SHIFT
 
- TPD_END2END_OAMF5
 
- TPD_EOP_MASK
 
- TPD_EOP_SHIFT
 
- TPD_EOS
 
- TPD_ETHTYPE_MASK
 
- TPD_ETHTYPE_SHIFT
 
- TPD_ETH_TYPE_MASK
 
- TPD_ETH_TYPE_SHIFT
 
- TPD_HADDR_SHIFT
 
- TPD_HDRFLAG_MASK
 
- TPD_HDRFLAG_SHIFT
 
- TPD_HEAD_ADDR_MASK
 
- TPD_HEAD_ADDR_SHIFT
 
- TPD_INDEX
 
- TPD_INSTC_SET
 
- TPD_INS_VLTAG_MASK
 
- TPD_INS_VLTAG_SHIFT
 
- TPD_INS_VL_TAG_MASK
 
- TPD_INS_VL_TAG_SHIFT
 
- TPD_INS_VTAG_MASK
 
- TPD_INS_VTAG_SHIFT
 
- TPD_INT
 
- TPD_IPHL_MASK
 
- TPD_IPHL_SHIFT
 
- TPD_IPV4_MASK
 
- TPD_IPV4_PACKET_MASK
 
- TPD_IPV4_PACKET_SHIFT
 
- TPD_IPV4_SET
 
- TPD_IPV4_SHIFT
 
- TPD_IP_CSUM_MASK
 
- TPD_IP_CSUM_SHIFT
 
- TPD_IP_VERSION_MASK
 
- TPD_IP_VERSION_SHIFT
 
- TPD_IP_XSUM_MASK
 
- TPD_IP_XSUM_SHIFT
 
- TPD_L4HDROFFSET_MASK
 
- TPD_L4HDROFFSET_SHIFT
 
- TPD_L4HDR_OFFSET_MASK
 
- TPD_L4HDR_OFFSET_SHIFT
 
- TPD_LEN_MASK
 
- TPD_LSO
 
- TPD_LSOV_SET
 
- TPD_LSO_EN_MASK
 
- TPD_LSO_EN_SHIFT
 
- TPD_LSO_SET
 
- TPD_LSO_V2_MASK
 
- TPD_LSO_V2_SHIFT
 
- TPD_LSO_VER_MASK
 
- TPD_LSO_VER_SHIFT
 
- TPD_LST
 
- TPD_MASK
 
- TPD_MAXIOV
 
- TPD_MSS_MASK
 
- TPD_MSS_SET
 
- TPD_MSS_SHIFT
 
- TPD_NIC_LEN_MASK
 
- TPD_PAYLOAD_OFFSET_SET
 
- TPD_PKTINT_SHIFT
 
- TPD_PKTNT_MASK
 
- TPD_PKT_LEN_SET
 
- TPD_PLOADOFFSET_MASK
 
- TPD_PLOADOFFSET_SHIFT
 
- TPD_RING_SIZE_BMSK
 
- TPD_RING_SIZE_MASK
 
- TPD_RMCELL
 
- TPD_SEGMENT_EN_MASK
 
- TPD_SEGMENT_EN_SHIFT
 
- TPD_SEGMENT_OAMF5
 
- TPD_TAIL_ADDR_MASK
 
- TPD_TAIL_ADDR_SHIFT
 
- TPD_TCPHDRLEN_MASK
 
- TPD_TCPHDRLEN_SHIFT
 
- TPD_TCPHDR_OFFSET_MASK
 
- TPD_TCPHDR_OFFSET_SET
 
- TPD_TCPHDR_OFFSET_SHIFT
 
- TPD_TCP_CSUM_MASK
 
- TPD_TCP_CSUM_SHIFT
 
- TPD_TCP_XSUM_MASK
 
- TPD_TCP_XSUM_SHIFT
 
- TPD_TYP_SET
 
- TPD_UDP_CSUM_MASK
 
- TPD_UDP_CSUM_SHIFT
 
- TPD_UDP_XSUM_MASK
 
- TPD_UDP_XSUM_SHIFT
 
- TPD_USERCELL
 
- TPD_V4_IPHL_SHIFT
 
- TPD_V6_IPHLHI_MASK
 
- TPD_V6_IPHLHI_SHIFT
 
- TPD_V6_IPHLLO_MASK
 
- TPD_V6_IPHLLO_SHIFT
 
- TPD_VLANTAG_MASK
 
- TPD_VLANTAG_SHIFT
 
- TPD_VLAN_SHIFT
 
- TPD_VLTAGGED_MASK
 
- TPD_VLTAGGED_SHIFT
 
- TPD_VL_TAGGED_MASK
 
- TPD_VL_TAGGED_SHIFT
 
- TPER_SYNC_SUPPORTED
 
- TPFH
 
- TPFH_ADDR
 
- TPFIFO_M
 
- TPFIFO_S
 
- TPFIFO_V
 
- TPG110_CHIPID
 
- TPG110_CTRL1
 
- TPG110_CTRL2
 
- TPG110_CTRL2_PM
 
- TPG110_CTRL2_RES_PM_CTRL
 
- TPG110_RES_400X240_D
 
- TPG110_RES_480X272
 
- TPG110_RES_480X272_D
 
- TPG110_RES_480X640
 
- TPG110_RES_640X480
 
- TPG110_RES_800X480
 
- TPG110_RES_MASK
 
- TPG110_TEST
 
- TPGS_EXPLICIT_ALUA
 
- TPGS_IMPLICIT_ALUA
 
- TPGS_MODE_EXPLICIT
 
- TPGS_MODE_IMPLICIT
 
- TPGS_MODE_NONE
 
- TPGS_MODE_UNINITIALIZED
 
- TPGS_NO_ALUA
 
- TPGS_SUPPORT_ALL
 
- TPGS_SUPPORT_LBA_DEPENDENT
 
- TPGS_SUPPORT_NONE
 
- TPGS_SUPPORT_NONOPTIMIZED
 
- TPGS_SUPPORT_OFFLINE
 
- TPGS_SUPPORT_OPTIMIZED
 
- TPGS_SUPPORT_STANDBY
 
- TPGS_SUPPORT_TRANSITION
 
- TPGS_SUPPORT_UNAVAILABLE
 
- TPG_COLOR_100_BLACK
 
- TPG_COLOR_100_BLUE
 
- TPG_COLOR_100_CYAN
 
- TPG_COLOR_100_GREEN
 
- TPG_COLOR_100_MAGENTA
 
- TPG_COLOR_100_RED
 
- TPG_COLOR_100_WHITE
 
- TPG_COLOR_100_YELLOW
 
- TPG_COLOR_75_BLUE
 
- TPG_COLOR_75_CYAN
 
- TPG_COLOR_75_GREEN
 
- TPG_COLOR_75_MAGENTA
 
- TPG_COLOR_75_RED
 
- TPG_COLOR_75_YELLOW
 
- TPG_COLOR_CSC_BLACK
 
- TPG_COLOR_CSC_BLUE
 
- TPG_COLOR_CSC_CYAN
 
- TPG_COLOR_CSC_GREEN
 
- TPG_COLOR_CSC_MAGENTA
 
- TPG_COLOR_CSC_RED
 
- TPG_COLOR_CSC_WHITE
 
- TPG_COLOR_CSC_YELLOW
 
- TPG_COLOR_MAX
 
- TPG_COLOR_RAMP
 
- TPG_COLOR_RANDOM
 
- TPG_COLOR_TEXTBG
 
- TPG_COLOR_TEXTFG
 
- TPG_INSTANCES
 
- TPG_MAX_PAT_LINES
 
- TPG_MAX_PLANES
 
- TPG_MOVE_NEG
 
- TPG_MOVE_NEG_FAST
 
- TPG_MOVE_NEG_SLOW
 
- TPG_MOVE_NONE
 
- TPG_MOVE_POS
 
- TPG_MOVE_POS_FAST
 
- TPG_MOVE_POS_SLOW
 
- TPG_PAT_100_COLORBAR
 
- TPG_PAT_100_COLORSQUARES
 
- TPG_PAT_100_HCOLORBAR
 
- TPG_PAT_75_COLORBAR
 
- TPG_PAT_ALTERNATING_HLINES
 
- TPG_PAT_ALTERNATING_VLINES
 
- TPG_PAT_BLACK
 
- TPG_PAT_BLUE
 
- TPG_PAT_CHECKERS_16X16
 
- TPG_PAT_CHECKERS_1X1
 
- TPG_PAT_CHECKERS_2X2
 
- TPG_PAT_COLOR_CHECKERS_1X1
 
- TPG_PAT_COLOR_CHECKERS_2X2
 
- TPG_PAT_CROSS_10_PIXELS
 
- TPG_PAT_CROSS_1_PIXEL
 
- TPG_PAT_CROSS_2_PIXELS
 
- TPG_PAT_CSC_COLORBAR
 
- TPG_PAT_GRAY_RAMP
 
- TPG_PAT_GREEN
 
- TPG_PAT_NOISE
 
- TPG_PAT_RED
 
- TPG_PAT_WHITE
 
- TPG_PIXEL_ASPECT_NTSC
 
- TPG_PIXEL_ASPECT_PAL
 
- TPG_PIXEL_ASPECT_SQUARE
 
- TPG_QUAL_COLOR
 
- TPG_QUAL_GRAY
 
- TPG_QUAL_NOISE
 
- TPG_STATE_ACTIVE
 
- TPG_STATE_COLD_RESET
 
- TPG_STATE_FREE
 
- TPG_STATE_INACTIVE
 
- TPG_VIDEO_ASPECT_14X9_CENTRE
 
- TPG_VIDEO_ASPECT_16X9_ANAMORPHIC
 
- TPG_VIDEO_ASPECT_16X9_CENTRE
 
- TPG_VIDEO_ASPECT_4X3
 
- TPG_VIDEO_ASPECT_IMAGE
 
- TPH_ST_HINT_BIDIR
 
- TPH_ST_HINT_REQUESTER
 
- TPH_ST_HINT_TARGET
 
- TPH_ST_HINT_TARGET_PRIO
 
- TPIC2810_WS_COMMAND
 
- TPID
 
- TPID3
 
- TPIDRRO_EL0
 
- TPIDR_EL0
 
- TPIDR_EL1
 
- TPIU_CURR_PORTSZ
 
- TPIU_CURR_TESTPATM
 
- TPIU_EXTCTL_INPORT
 
- TPIU_EXTCTL_OUTPORT
 
- TPIU_FFCR
 
- TPIU_FFSR
 
- TPIU_FSYNC_CNTR
 
- TPIU_ITATBCTR0
 
- TPIU_ITATBCTR1
 
- TPIU_ITATBCTR2
 
- TPIU_ITATBDATA0
 
- TPIU_ITTRFLIN
 
- TPIU_ITTRFLINACK
 
- TPIU_SUPP_PORTSZ
 
- TPIU_SUPP_TESTPATM
 
- TPIU_SUPP_TRIGMODES
 
- TPIU_TEST_PATREPCNTR
 
- TPIU_TRIG_CNTRVAL
 
- TPIU_TRIG_MULT
 
- TPI_ATTEMPTS
 
- TPI_AUD_CONFIG
 
- TPI_AUD_MUTE
 
- TPI_DDC_MASTER_EN
 
- TPI_DPD_REG
 
- TPI_HPD_CONNECTION
 
- TPI_HPD_RSEN
 
- TPI_INFO_B0
 
- TPI_INFO_EN
 
- TPI_INFO_FSEL
 
- TPI_INFO_TRANS_EN
 
- TPI_INFO_TRANS_RPT
 
- TPK_MAX_ROOM
 
- TPK_PREFIX
 
- TPK_STR_SIZE
 
- TPL0102_104
 
- TPL0102_CHANNEL
 
- TPL0401_103
 
- TPL1_TPPERF_ACTIVE_CYCLES_ALL
 
- TPL1_TPPERF_ACTIVE_CYCLES_ANY
 
- TPL1_TPPERF_BILINEAR_OPS
 
- TPL1_TPPERF_L1_REQUESTS
 
- TPL1_TPPERF_LATENCY
 
- TPL1_TPPERF_LATENCY_TRANS
 
- TPL1_TPPERF_OUTPUT_TEXELS
 
- TPL1_TPPERF_OUTPUT_TEXELS_ANISO
 
- TPL1_TPPERF_OUTPUT_TEXELS_BILINEAR
 
- TPL1_TPPERF_OUTPUT_TEXELS_MIP
 
- TPL1_TPPERF_OUTPUT_TEXELS_POINT
 
- TPL1_TPPERF_QUADQUADS_SHADOW
 
- TPL1_TPPERF_QUADSQUADS_OFFSET
 
- TPL1_TPPERF_QUADS_1D2D
 
- TPL1_TPPERF_QUADS_3DCUBE
 
- TPL1_TPPERF_QUADS_ARRAY
 
- TPL1_TPPERF_QUADS_GRADIENT
 
- TPL1_TPPERF_QUADS_PROJECTION
 
- TPL1_TPPERF_STALL_CYCLES_BY_ARB
 
- TPL1_TPPERF_TP0_L1_MISSES
 
- TPL1_TPPERF_TP0_L1_REQUESTS
 
- TPL1_TPPERF_TP1_L1_MISSES
 
- TPL1_TPPERF_TP1_L1_REQUESTS
 
- TPL1_TPPERF_TP2_L1_MISSES
 
- TPL1_TPPERF_TP2_L1_REQUESTS
 
- TPL1_TPPERF_TP3_L1_MISSES
 
- TPL1_TPPERF_TP3_L1_REQUESTS
 
- TPL1_TPPERF_ZERO_LOD
 
- TPLA_SIZE
 
- TPLINK_PRODUCT_LTE
 
- TPLINK_PRODUCT_MA180
 
- TPLINK_VENDOR_ID
 
- TPL_ROM_WRITE_EN
 
- TPLnkFail
 
- TPLnkPass
 
- TPM2_CAP_COMMANDS
 
- TPM2_CAP_HANDLES
 
- TPM2_CAP_PCRS
 
- TPM2_CAP_TPM_PROPERTIES
 
- TPM2_CC_ATTR_CHANDLES
 
- TPM2_CC_ATTR_RHANDLE
 
- TPM2_CC_CONTEXT_LOAD
 
- TPM2_CC_CONTEXT_SAVE
 
- TPM2_CC_CREATE
 
- TPM2_CC_CREATE_LOADED
 
- TPM2_CC_CREATE_PRIMARY
 
- TPM2_CC_EVENT_SEQUENCE_COMPLETE
 
- TPM2_CC_FIRST
 
- TPM2_CC_FLUSH_CONTEXT
 
- TPM2_CC_GET_CAPABILITY
 
- TPM2_CC_GET_RANDOM
 
- TPM2_CC_HASH_SEQUENCE_START
 
- TPM2_CC_HIERARCHY_CHANGE_AUTH
 
- TPM2_CC_HIERARCHY_CONTROL
 
- TPM2_CC_LAST
 
- TPM2_CC_LOAD
 
- TPM2_CC_NV_READ
 
- TPM2_CC_PCR_EXTEND
 
- TPM2_CC_PCR_READ
 
- TPM2_CC_SELF_TEST
 
- TPM2_CC_SEQUENCE_COMPLETE
 
- TPM2_CC_SEQUENCE_UPDATE
 
- TPM2_CC_SET_LOCALITY
 
- TPM2_CC_SHUTDOWN
 
- TPM2_CC_STARTUP
 
- TPM2_CC_UNSEAL
 
- TPM2_CC_VERIFY_SIGNATURE
 
- TPM2_DURATION_DEFAULT
 
- TPM2_DURATION_LONG
 
- TPM2_DURATION_LONG_LONG
 
- TPM2_DURATION_MEDIUM
 
- TPM2_DURATION_SHORT
 
- TPM2_HT_HMAC_SESSION
 
- TPM2_HT_POLICY_SESSION
 
- TPM2_HT_TRANSIENT
 
- TPM2_OA_USER_WITH_AUTH
 
- TPM2_PCR_SELECT_MIN
 
- TPM2_PLATFORM_PCR
 
- TPM2_RC_COMMAND_CODE
 
- TPM2_RC_DISABLED
 
- TPM2_RC_FAILURE
 
- TPM2_RC_HANDLE
 
- TPM2_RC_HASH
 
- TPM2_RC_INITIALIZE
 
- TPM2_RC_REFERENCE_H0
 
- TPM2_RC_RETRY
 
- TPM2_RC_SUCCESS
 
- TPM2_RC_TESTING
 
- TPM2_RS_PW
 
- TPM2_SA_CONTINUE_SESSION
 
- TPM2_ST_NO_SESSIONS
 
- TPM2_ST_SESSIONS
 
- TPM2_SU_CLEAR
 
- TPM2_SU_STATE
 
- TPM2_TIMEOUT_A
 
- TPM2_TIMEOUT_B
 
- TPM2_TIMEOUT_C
 
- TPM2_TIMEOUT_D
 
- TPM_ACCESS
 
- TPM_ACCESS_ACTIVE_LOCALITY
 
- TPM_ACCESS_REQUEST_PENDING
 
- TPM_ACCESS_REQUEST_USE
 
- TPM_ACCESS_VALID
 
- TPM_ADDR
 
- TPM_ALG_ERROR
 
- TPM_ALG_KEYEDHASH
 
- TPM_ALG_NULL
 
- TPM_ALG_SHA1
 
- TPM_ALG_SHA256
 
- TPM_ALG_SHA384
 
- TPM_ALG_SHA512
 
- TPM_ALG_SM3_256
 
- TPM_ATMEL_BASE_ADDR_HI
 
- TPM_ATMEL_BASE_ADDR_LO
 
- TPM_BUFSIZE
 
- TPM_BUF_OVERFLOW
 
- TPM_BURST_COUNT
 
- TPM_C0SC
 
- TPM_C0SC_CHF_MASK
 
- TPM_C0SC_CHIE
 
- TPM_C0SC_MODE_MASK
 
- TPM_C0SC_MODE_SHIFT
 
- TPM_C0SC_MODE_SW_COMPARE
 
- TPM_C0V
 
- TPM_CAP_FLAG
 
- TPM_CAP_FLAG_PERM
 
- TPM_CAP_FLAG_VOL
 
- TPM_CAP_PROP
 
- TPM_CAP_PROP_MANUFACTURER
 
- TPM_CAP_PROP_OWNER
 
- TPM_CAP_PROP_PCR
 
- TPM_CAP_PROP_TIS_DURATION
 
- TPM_CAP_PROP_TIS_TIMEOUT
 
- TPM_CAP_VERSION_1_1
 
- TPM_CAP_VERSION_1_2
 
- TPM_CHIP_FLAG_ALWAYS_POWERED
 
- TPM_CHIP_FLAG_HAVE_TIMEOUTS
 
- TPM_CHIP_FLAG_IRQ
 
- TPM_CHIP_FLAG_TPM2
 
- TPM_CHIP_FLAG_VIRTUAL
 
- TPM_CNT
 
- TPM_CTRL_CHAINING
 
- TPM_CTRL_CHAININGACK
 
- TPM_CTRL_DATA
 
- TPM_CTRL_DATA_CHA
 
- TPM_CTRL_DATA_CHA_ACK
 
- TPM_CTRL_ERROR
 
- TPM_CTRL_WTX
 
- TPM_CTRL_WTX_ABORT
 
- TPM_CTRL_WTX_ABORT_ACK
 
- TPM_DAR
 
- TPM_DATA_FIFO
 
- TPM_DATA_FIFO_R
 
- TPM_DATA_FIFO_W
 
- TPM_DATA_OFFSET
 
- TPM_DEBUG
 
- TPM_DID_VID
 
- TPM_DIGEST_SIZE
 
- TPM_DUMMY_BYTE
 
- TPM_ERR_DEACTIVATED
 
- TPM_ERR_DISABLED
 
- TPM_ERR_INVALID_POSTINIT
 
- TPM_FLUSHSPECIFIC_SIZE
 
- TPM_GETRANDOM_SIZE
 
- TPM_GLOBAL_INT_ENABLE
 
- TPM_HEADER_SIZE
 
- TPM_I2C_BUS_DELAY
 
- TPM_I2C_DELAY_RANGE
 
- TPM_I2C_INFINEON_BUFSIZE
 
- TPM_I2C_LONG_TIMEOUT
 
- TPM_I2C_MAX_BUF_SIZE
 
- TPM_I2C_RETRIES
 
- TPM_I2C_RETRY_COUNT
 
- TPM_I2C_RETRY_DELAY_LONG
 
- TPM_I2C_RETRY_DELAY_SHORT
 
- TPM_I2C_SHORT_TIMEOUT
 
- TPM_INFINEON_DEV_VEN_VALUE
 
- TPM_INF_ADDR
 
- TPM_INF_DATA
 
- TPM_INF_IO_MEM
 
- TPM_INF_IO_PORT
 
- TPM_INF_NAK
 
- TPM_INTF_BURST_COUNT_STATIC
 
- TPM_INTF_CAPABILITY
 
- TPM_INTF_CAPS
 
- TPM_INTF_CMD_READY_INT
 
- TPM_INTF_DATA_AVAIL_INT
 
- TPM_INTF_FIFO_AVALAIBLE_INT
 
- TPM_INTF_INT_EDGE_FALLING
 
- TPM_INTF_INT_EDGE_RISING
 
- TPM_INTF_INT_LEVEL_HIGH
 
- TPM_INTF_INT_LEVEL_LOW
 
- TPM_INTF_LOCALITY_CHANGE_INT
 
- TPM_INTF_STS_VALID_INT
 
- TPM_INTF_WAKE_UP_READY_INT
 
- TPM_INT_ENABLE
 
- TPM_INT_STATUS
 
- TPM_INT_VECTOR
 
- TPM_LOADKEY2_SIZE
 
- TPM_LONG
 
- TPM_LONG_LONG
 
- TPM_MASK
 
- TPM_MAX_DIGEST_SIZE
 
- TPM_MAX_ORDINAL
 
- TPM_MAX_RNG_DATA
 
- TPM_MAX_TRIES
 
- TPM_MAX_WTX_PACKAGES
 
- TPM_MEDIUM
 
- TPM_MEMREMAP
 
- TPM_MEMUNMAP
 
- TPM_MINOR
 
- TPM_MOD
 
- TPM_MSLEEP_TIME
 
- TPM_NONCE_SIZE
 
- TPM_NSC_BASE0_HI
 
- TPM_NSC_BASE0_LO
 
- TPM_NSC_BASE1_HI
 
- TPM_NSC_BASE1_LO
 
- TPM_NSC_IRQ
 
- TPM_NUM_DEVICES
 
- TPM_NUM_DURATIONS
 
- TPM_NUM_EVENT_LOG_FILES
 
- TPM_OIAP_SIZE
 
- TPM_OPS_AUTO_STARTUP
 
- TPM_OPS_FLAGS
 
- TPM_ORD_CONTINUE_SELFTEST
 
- TPM_ORD_FLUSHSPECIFIC
 
- TPM_ORD_GETRANDOM
 
- TPM_ORD_GET_CAP
 
- TPM_ORD_GET_RANDOM
 
- TPM_ORD_LOADKEY2
 
- TPM_ORD_OIAP
 
- TPM_ORD_OSAP
 
- TPM_ORD_PCRREAD
 
- TPM_ORD_PCR_EXTEND
 
- TPM_ORD_READPUBEK
 
- TPM_ORD_SAVESTATE
 
- TPM_ORD_SEAL
 
- TPM_ORD_SET_LOCALITY
 
- TPM_ORD_SIGN
 
- TPM_ORD_STARTUP
 
- TPM_ORD_UNBIND
 
- TPM_ORD_UNSEAL
 
- TPM_OSAP_SIZE
 
- TPM_PARAM
 
- TPM_PARAM_WIDTH_MASK
 
- TPM_PARAM_WIDTH_SHIFT
 
- TPM_PCR0
 
- TPM_PCR8
 
- TPM_PPI_FN_GETACT
 
- TPM_PPI_FN_GETOPR
 
- TPM_PPI_FN_GETREQ
 
- TPM_PPI_FN_GETRSP
 
- TPM_PPI_FN_SUBREQ
 
- TPM_PPI_FN_SUBREQ2
 
- TPM_PPI_FN_VERSION
 
- TPM_PPI_REVISION_ID_1
 
- TPM_PPI_REVISION_ID_2
 
- TPM_PPI_VERSION_LEN
 
- TPM_PT_TOTAL_COMMANDS
 
- TPM_RETRY
 
- TPM_RETURN_OFFSET
 
- TPM_RID
 
- TPM_RT_KEY
 
- TPM_SC
 
- TPM_SC_CMOD_DIV_DEFAULT
 
- TPM_SC_CMOD_DIV_MAX
 
- TPM_SC_CMOD_INC_PER_CNT
 
- TPM_SC_TOF_MASK
 
- TPM_SEAL_SIZE
 
- TPM_SHORT
 
- TPM_SIGN_SIZE
 
- TPM_SIZE_OFFSET
 
- TPM_ST33_I2C
 
- TPM_ST33_SPI
 
- TPM_STATUS
 
- TPM_STATUS_CH0F
 
- TPM_STS
 
- TPM_STS3
 
- TPM_STS_COMMAND_READY
 
- TPM_STS_DATA_AVAIL
 
- TPM_STS_DATA_EXPECT
 
- TPM_STS_ERR_VAL
 
- TPM_STS_EXPECT
 
- TPM_STS_GO
 
- TPM_STS_RESPONSE_RETRY
 
- TPM_STS_VALID
 
- TPM_ST_CLEAR
 
- TPM_SUPERIO_ADDR
 
- TPM_TAG_RQU_AUTH1_COMMAND
 
- TPM_TAG_RQU_AUTH2_COMMAND
 
- TPM_TAG_RQU_COMMAND
 
- TPM_TAG_RSP_AUTH1_COMMAND
 
- TPM_TAG_RSP_AUTH2_COMMAND
 
- TPM_TAG_RSP_COMMAND
 
- TPM_TIMEOUT
 
- TPM_TIMEOUT_POLL
 
- TPM_TIMEOUT_RANGE_US
 
- TPM_TIMEOUT_RETRY
 
- TPM_TIMEOUT_USECS_MAX
 
- TPM_TIMEOUT_USECS_MIN
 
- TPM_TIMEOUT_US_HI
 
- TPM_TIMEOUT_US_LOW
 
- TPM_TIS_I2C_DID_VID_9635
 
- TPM_TIS_I2C_DID_VID_9645
 
- TPM_TIS_ITPM_WORKAROUND
 
- TPM_UNBIND_SIZE
 
- TPM_UNDEFINED
 
- TPM_UNSEAL_SIZE
 
- TPM_VID_DID_RID
 
- TPM_VID_INTEL
 
- TPM_VID_STM
 
- TPM_VID_WINBOND
 
- TPM_VL_CHANNEL_CONTROL
 
- TPM_VL_CHANNEL_PERSONALISATION
 
- TPM_VL_CHANNEL_TPM
 
- TPM_VL_CONTROL
 
- TPM_VL_VER
 
- TPM_WARN_DOING_SELFTEST
 
- TPM_WARN_RETRY
 
- TPM_WRITE_DIRECTION
 
- TPM_WTX_MSLEEP_TIME
 
- TPO_PANEL_HEIGHT
 
- TPO_PANEL_WIDTH
 
- TPO_R02_HSYNC_HIGH
 
- TPO_R02_MODE
 
- TPO_R02_MODE_800x480
 
- TPO_R02_NCLK_RISING
 
- TPO_R02_VSYNC_HIGH
 
- TPO_R03_DRIVING_CAP_100
 
- TPO_R03_EN_CP_CLK
 
- TPO_R03_EN_PRE_CHARGE
 
- TPO_R03_EN_PWM
 
- TPO_R03_EN_VGL_PUMP
 
- TPO_R03_NSTANDBY
 
- TPO_R03_SOFTWARE_CTL
 
- TPO_R03_VAL_NORMAL
 
- TPO_R03_VAL_STANDBY
 
- TPO_R04_CP_CLK_FREQ_1H
 
- TPO_R04_NFLIP_H
 
- TPO_R04_NFLIP_V
 
- TPO_R04_VGL_FREQ_1H
 
- TPO_VID
 
- TPPOLL_BEQ
 
- TPPOLL_BKQ
 
- TPPOLL_BQ
 
- TPPOLL_CQ
 
- TPPOLL_HCCAQ
 
- TPPOLL_HQ
 
- TPPOLL_MQ
 
- TPPOLL_SHIFT
 
- TPPOLL_STOPBE
 
- TPPOLL_STOPBK
 
- TPPOLL_STOPHCCA
 
- TPPOLL_STOPHIGH
 
- TPPOLL_STOPMGT
 
- TPPOLL_STOPVI
 
- TPPOLL_STOPVO
 
- TPPOLL_VIQ
 
- TPPOLL_VOQ
 
- TPPoll
 
- TPPoll_BEQ
 
- TPPoll_BKQ
 
- TPPoll_BQ
 
- TPPoll_CQ
 
- TPPoll_HCCAQ
 
- TPPoll_HQ
 
- TPPoll_MQ
 
- TPPoll_SHIFT
 
- TPPoll_StopBE
 
- TPPoll_StopBK
 
- TPPoll_StopHCCA
 
- TPPoll_StopHigh
 
- TPPoll_StopMgt
 
- TPPoll_StopVI
 
- TPPoll_StopVO
 
- TPPoll_VIQ
 
- TPPoll_VOQ
 
- TPQ_LINK_TABLE
 
- TPR
 
- TPRER
 
- TPRER1
 
- TPRER1_ADDR
 
- TPRER2
 
- TPRER2_ADDR
 
- TPRER_ADDR
 
- TPRLO_PAGE_LEN
 
- TPR_THRESHOLD
 
- TPS
 
- TPS51632_DEFAULT_RAMP_DELAY
 
- TPS51632_DVFS_CONTROL_REG
 
- TPS51632_DVFS_FCCM
 
- TPS51632_DVFS_OCA_EN
 
- TPS51632_DVFS_PWMEN
 
- TPS51632_DVFS_PWMRST
 
- TPS51632_DVFS_STEP_20
 
- TPS51632_DVFS_VMAX_PG
 
- TPS51632_FAULT_REG
 
- TPS51632_IMON_REG
 
- TPS51632_MAX_REG
 
- TPS51632_MAX_VOLTAGE
 
- TPS51632_MAX_VSEL
 
- TPS51632_MIN_VOLTAGE
 
- TPS51632_MIN_VSEL
 
- TPS51632_OFFSET_REG
 
- TPS51632_POWER_STATE_MASK
 
- TPS51632_POWER_STATE_MULTI_PHASE_CCM
 
- TPS51632_POWER_STATE_REG
 
- TPS51632_POWER_STATE_SINGLE_PHASE_CCM
 
- TPS51632_POWER_STATE_SINGLE_PHASE_DCM
 
- TPS51632_SLEW_REGS
 
- TPS51632_VMAX_LOCK
 
- TPS51632_VMAX_MASK
 
- TPS51632_VMAX_REG
 
- TPS51632_VOLTAGE_BASE_REG
 
- TPS51632_VOLTAGE_SELECT_REG
 
- TPS51632_VOLTAGE_STEP_10mV
 
- TPS51632_VOLTAGE_STEP_20mV
 
- TPS51632_VOLT_VSEL
 
- TPS51632_VOUT_MASK
 
- TPS51632_VOUT_OFFSET_MASK
 
- TPS53679_PAGE_NUM
 
- TPS53679_PROT_IMVP8_5MV
 
- TPS53679_PROT_VR12_5MV
 
- TPS53679_PROT_VR12_5_10MV
 
- TPS53679_PROT_VR13_10MV
 
- TPS53679_PROT_VR13_5MV
 
- TPS6105X_MODE_SHUTDOWN
 
- TPS6105X_MODE_TORCH
 
- TPS6105X_MODE_TORCH_FLASH
 
- TPS6105X_MODE_VOLTAGE
 
- TPS6105X_REG0_DIMMING_SHIFT
 
- TPS6105X_REG0_MODE_MASK
 
- TPS6105X_REG0_MODE_SHIFT
 
- TPS6105X_REG0_MODE_SHUTDOWN
 
- TPS6105X_REG0_MODE_TORCH
 
- TPS6105X_REG0_MODE_TORCH_FLASH
 
- TPS6105X_REG0_MODE_VOLTAGE
 
- TPS6105X_REG0_TORCHC_0
 
- TPS6105X_REG0_TORCHC_100
 
- TPS6105X_REG0_TORCHC_150
 
- TPS6105X_REG0_TORCHC_200
 
- TPS6105X_REG0_TORCHC_250_400
 
- TPS6105X_REG0_TORCHC_250_500
 
- TPS6105X_REG0_TORCHC_50
 
- TPS6105X_REG0_TORCHC_75
 
- TPS6105X_REG0_TORCHC_MASK
 
- TPS6105X_REG0_TORCHC_SHIFT
 
- TPS6105X_REG0_VOLTAGE_450
 
- TPS6105X_REG0_VOLTAGE_500
 
- TPS6105X_REG0_VOLTAGE_500_2
 
- TPS6105X_REG0_VOLTAGE_525
 
- TPS6105X_REG0_VOLTAGE_MASK
 
- TPS6105X_REG0_VOLTAGE_SHIFT
 
- TPS6105X_REG1_MODE_MASK
 
- TPS6105X_REG1_MODE_SHIFT
 
- TPS6105X_REG1_MODE_SHUTDOWN
 
- TPS6105X_REG1_MODE_TORCH
 
- TPS6105X_REG1_MODE_TORCH_FLASH
 
- TPS6105X_REG1_MODE_VOLTAGE
 
- TPS6105X_REG_0
 
- TPS6105X_REG_1
 
- TPS6105X_REG_2
 
- TPS6105X_REG_3
 
- TPS62360
 
- TPS62360_BASE_VOLTAGE
 
- TPS62360_N_VOLTAGES
 
- TPS62361
 
- TPS62361_BASE_VOLTAGE
 
- TPS62361_N_VOLTAGES
 
- TPS62362
 
- TPS62363
 
- TPS65010
 
- TPS65011
 
- TPS65012
 
- TPS65013
 
- TPS65013_AUA
 
- TPS65023_DCDC_1
 
- TPS65023_DCDC_2
 
- TPS65023_DCDC_3
 
- TPS65023_LDO_1
 
- TPS65023_LDO_2
 
- TPS65023_MASK_LDO1
 
- TPS65023_MASK_LDO2
 
- TPS65023_MASK_LOWBATTZ
 
- TPS65023_MASK_PWRFAILZ
 
- TPS65023_MASK_VDCDC1
 
- TPS65023_MASK_VDCDC2
 
- TPS65023_MASK_VDCDC3
 
- TPS65023_MAX_REG_ID
 
- TPS65023_NUM_DCDC
 
- TPS65023_NUM_LDO
 
- TPS65023_NUM_REGULATOR
 
- TPS65023_PGOODZ_LDO1
 
- TPS65023_PGOODZ_LDO2
 
- TPS65023_PGOODZ_LOWBATTZ
 
- TPS65023_PGOODZ_PWRFAILZ
 
- TPS65023_PGOODZ_VDCDC1
 
- TPS65023_PGOODZ_VDCDC2
 
- TPS65023_PGOODZ_VDCDC3
 
- TPS65023_REGULATOR_DCDC
 
- TPS65023_REGULATOR_LDO
 
- TPS65023_REG_CON_CTRL
 
- TPS65023_REG_CON_CTRL2
 
- TPS65023_REG_CTRL2_CORE_ADJ
 
- TPS65023_REG_CTRL2_DCDC1
 
- TPS65023_REG_CTRL2_DCDC2
 
- TPS65023_REG_CTRL2_DCDC3
 
- TPS65023_REG_CTRL2_GO
 
- TPS65023_REG_CTRL_LDO1_EN
 
- TPS65023_REG_CTRL_LDO2_EN
 
- TPS65023_REG_CTRL_VDCDC1_EN
 
- TPS65023_REG_CTRL_VDCDC2_EN
 
- TPS65023_REG_CTRL_VDCDC3_EN
 
- TPS65023_REG_DEFSLEW
 
- TPS65023_REG_DEF_CORE
 
- TPS65023_REG_LDO_CTRL
 
- TPS65023_REG_MASK
 
- TPS65023_REG_PGOODZ
 
- TPS65023_REG_REG_CTRL
 
- TPS65023_REG_VERSION
 
- TPS6507X_ADCONFIG_AD_ENABLE
 
- TPS6507X_ADCONFIG_CONVERSION_DONE
 
- TPS6507X_ADCONFIG_CONVERT_TS
 
- TPS6507X_ADCONFIG_INPUT_AC_VOLTAGE
 
- TPS6507X_ADCONFIG_INPUT_AD_IN1
 
- TPS6507X_ADCONFIG_INPUT_AD_IN2
 
- TPS6507X_ADCONFIG_INPUT_AD_IN3
 
- TPS6507X_ADCONFIG_INPUT_AD_IN4
 
- TPS6507X_ADCONFIG_INPUT_BAT_CURRENT
 
- TPS6507X_ADCONFIG_INPUT_BAT_VOLTAGE
 
- TPS6507X_ADCONFIG_INPUT_CHARGER_VOLTAGE
 
- TPS6507X_ADCONFIG_INPUT_ISET1_VOLTAGE
 
- TPS6507X_ADCONFIG_INPUT_ISET2_VOLTAGE
 
- TPS6507X_ADCONFIG_INPUT_REAL_TSC
 
- TPS6507X_ADCONFIG_INPUT_SYS_VOLTAGE
 
- TPS6507X_ADCONFIG_INPUT_THRESHOLD_VOLTAGE
 
- TPS6507X_ADCONFIG_INPUT_TSC
 
- TPS6507X_ADCONFIG_INPUT_TS_PIN
 
- TPS6507X_ADCONFIG_POWER_DOWN_TS
 
- TPS6507X_ADCONFIG_START_CONVERSION
 
- TPS6507X_ADCONFIG_VREF_ENABLE
 
- TPS6507X_CHG_AC
 
- TPS6507X_CHG_AC_CURRENT
 
- TPS6507X_CHG_AC_PW_ENABLE
 
- TPS6507X_CHG_USB
 
- TPS6507X_CHG_USB_CURRENT
 
- TPS6507X_CHG_USB_PW_ENABLE
 
- TPS6507X_CON_CTRL1_DCDC1_ENABLE
 
- TPS6507X_CON_CTRL1_DCDC2_ENABLE
 
- TPS6507X_CON_CTRL1_DCDC3_ENABLE
 
- TPS6507X_CON_CTRL1_LDO1_ENABLE
 
- TPS6507X_CON_CTRL1_LDO2_ENABLE
 
- TPS6507X_DCDC_1
 
- TPS6507X_DCDC_2
 
- TPS6507X_DCDC_3
 
- TPS6507X_DEFDCDC1_DCDC1_EXT_ADJ_EN
 
- TPS6507X_DEFDCDC1_DCDC1_MASK
 
- TPS6507X_DEFDCDC2_HIGH_DCDC2_MASK
 
- TPS6507X_DEFDCDC2_LOW_DCDC2_MASK
 
- TPS6507X_DEFDCDC3_HIGH_DCDC3_MASK
 
- TPS6507X_DEFDCDC3_LOW_DCDC3_MASK
 
- TPS6507X_DEFDCDCX_DCDC_MASK
 
- TPS6507X_LDO_1
 
- TPS6507X_LDO_2
 
- TPS6507X_MAX_REGISTER
 
- TPS6507X_MAX_REG_ID
 
- TPS6507X_NUM_DCDC
 
- TPS6507X_NUM_LDO
 
- TPS6507X_NUM_REGULATOR
 
- TPS6507X_REG_AC_USB_APPLIED
 
- TPS6507X_REG_AC_USB_REMOVED
 
- TPS6507X_REG_ADCONFIG
 
- TPS6507X_REG_ADRESULT_1
 
- TPS6507X_REG_ADRESULT_2
 
- TPS6507X_REG_ADRESULT_2_MASK
 
- TPS6507X_REG_CHGCONFIG0
 
- TPS6507X_REG_CHGCONFIG1
 
- TPS6507X_REG_CHGCONFIG2
 
- TPS6507X_REG_CHGCONFIG3
 
- TPS6507X_REG_CON_CTRL1
 
- TPS6507X_REG_CON_CTRL2
 
- TPS6507X_REG_CON_CTRL3
 
- TPS6507X_REG_DEFDCDC1
 
- TPS6507X_REG_DEFDCDC2_HIGH
 
- TPS6507X_REG_DEFDCDC2_LOW
 
- TPS6507X_REG_DEFDCDC3_HIGH
 
- TPS6507X_REG_DEFDCDC3_LOW
 
- TPS6507X_REG_DEFLDO2
 
- TPS6507X_REG_DEFLDO2_LDO2_MASK
 
- TPS6507X_REG_DEFSLEW
 
- TPS6507X_REG_INT
 
- TPS6507X_REG_LDO_CTRL1
 
- TPS6507X_REG_LDO_CTRL1_LDO1_MASK
 
- TPS6507X_REG_MASK_AC_USB
 
- TPS6507X_REG_MASK_PB_IN
 
- TPS6507X_REG_MASK_TSC
 
- TPS6507X_REG_PB_IN_INT
 
- TPS6507X_REG_PGOOD
 
- TPS6507X_REG_PGOODMASK
 
- TPS6507X_REG_PPATH1
 
- TPS6507X_REG_TSCMODE
 
- TPS6507X_REG_TSC_INT
 
- TPS6507X_REG_WLED_CTRL1
 
- TPS6507X_REG_WLED_CTRL2
 
- TPS6507X_TSCMODE_ADC_INPUT
 
- TPS6507X_TSCMODE_DISABLE
 
- TPS6507X_TSCMODE_PRESSURE
 
- TPS6507X_TSCMODE_STANDBY
 
- TPS6507X_TSCMODE_X_PLATE
 
- TPS6507X_TSCMODE_X_POSITION
 
- TPS6507X_TSCMODE_Y_PLATE
 
- TPS6507X_TSCMODE_Y_POSITION
 
- TPS65086_BUCK123CTRL
 
- TPS65086_BUCK1CTRL
 
- TPS65086_BUCK1SLPCTRL
 
- TPS65086_BUCK2CTRL
 
- TPS65086_BUCK2SLPCTRL
 
- TPS65086_BUCK3DECAY
 
- TPS65086_BUCK3SLPCTRL
 
- TPS65086_BUCK3VID
 
- TPS65086_BUCK4CTRL
 
- TPS65086_BUCK4SLPVID
 
- TPS65086_BUCK4VID
 
- TPS65086_BUCK5CTRL
 
- TPS65086_BUCK5SLPVID
 
- TPS65086_BUCK5VID
 
- TPS65086_BUCK6CTRL
 
- TPS65086_BUCK6SLPVID
 
- TPS65086_BUCK6VID
 
- TPS65086_DEVICEID
 
- TPS65086_DEVICEID_OTP_MASK
 
- TPS65086_DEVICEID_PART_MASK
 
- TPS65086_DEVICEID_REV_MASK
 
- TPS65086_DISCHCTRL1
 
- TPS65086_DISCHCTRL2
 
- TPS65086_DISCHCTRL3
 
- TPS65086_FORCESHUTDN
 
- TPS65086_GPO1PG_CTRL1
 
- TPS65086_GPO1PG_CTRL2
 
- TPS65086_GPO2PG_CTRL1
 
- TPS65086_GPO2PG_CTRL2
 
- TPS65086_GPO3PG_CTRL1
 
- TPS65086_GPO3PG_CTRL2
 
- TPS65086_GPO4PG_CTRL1
 
- TPS65086_GPO4PG_CTRL2
 
- TPS65086_GPOCTRL
 
- TPS65086_IRQ
 
- TPS65086_IRQ_DIETEMP
 
- TPS65086_IRQ_DIETEMP_MASK
 
- TPS65086_IRQ_FAULT
 
- TPS65086_IRQ_FAULT_MASK
 
- TPS65086_IRQ_MASK
 
- TPS65086_IRQ_SHUTDN
 
- TPS65086_IRQ_SHUTDN_MASK
 
- TPS65086_LDOA1CTRL
 
- TPS65086_LDOA2CTRL
 
- TPS65086_LDOA2VID
 
- TPS65086_LDOA3CTRL
 
- TPS65086_LDOA3VID
 
- TPS65086_OC_STATUS
 
- TPS65086_PG_DELAY1
 
- TPS65086_PG_DELAY2
 
- TPS65086_PG_STATUS1
 
- TPS65086_PG_STATUS2
 
- TPS65086_PIN_EN_MASK1
 
- TPS65086_PIN_EN_MASK2
 
- TPS65086_PIN_EN_OVR1
 
- TPS65086_PIN_EN_OVR2
 
- TPS65086_PMICSTAT
 
- TPS65086_PWR_FAULT_MASK1
 
- TPS65086_PWR_FAULT_MASK2
 
- TPS65086_PWR_FAULT_STATUS1
 
- TPS65086_PWR_FAULT_STATUS2
 
- TPS65086_REGULATOR
 
- TPS65086_SHUTDNSRC
 
- TPS65086_SWITCH
 
- TPS65086_SWVTT_EN
 
- TPS65086_TEMPCRIT
 
- TPS65086_TEMPHOT
 
- TPS65090_CHARGER_ENABLE
 
- TPS65090_INT1_MASK_BAT_STATUS_CHANGE
 
- TPS65090_INT1_MASK_CHARGING_COMPLETE
 
- TPS65090_INT1_MASK_CHARGING_STATUS_CHANGE
 
- TPS65090_INT1_MASK_OVERLOAD_DCDC1
 
- TPS65090_INT1_MASK_OVERLOAD_DCDC2
 
- TPS65090_INT1_MASK_VAC_STATUS_CHANGE
 
- TPS65090_INT1_MASK_VSYS_STATUS_CHANGE
 
- TPS65090_INT2_MASK_OVERLOAD_DCDC3
 
- TPS65090_INT2_MASK_OVERLOAD_FET1
 
- TPS65090_INT2_MASK_OVERLOAD_FET2
 
- TPS65090_INT2_MASK_OVERLOAD_FET3
 
- TPS65090_INT2_MASK_OVERLOAD_FET4
 
- TPS65090_INT2_MASK_OVERLOAD_FET5
 
- TPS65090_INT2_MASK_OVERLOAD_FET6
 
- TPS65090_INT2_MASK_OVERLOAD_FET7
 
- TPS65090_IRQ_BAT_STATUS_CHANGE
 
- TPS65090_IRQ_CHARGING_COMPLETE
 
- TPS65090_IRQ_CHARGING_STATUS_CHANGE
 
- TPS65090_IRQ_INTERRUPT
 
- TPS65090_IRQ_OVERLOAD_DCDC1
 
- TPS65090_IRQ_OVERLOAD_DCDC2
 
- TPS65090_IRQ_OVERLOAD_DCDC3
 
- TPS65090_IRQ_OVERLOAD_FET1
 
- TPS65090_IRQ_OVERLOAD_FET2
 
- TPS65090_IRQ_OVERLOAD_FET3
 
- TPS65090_IRQ_OVERLOAD_FET4
 
- TPS65090_IRQ_OVERLOAD_FET5
 
- TPS65090_IRQ_OVERLOAD_FET6
 
- TPS65090_IRQ_OVERLOAD_FET7
 
- TPS65090_IRQ_VAC_STATUS_CHANGE
 
- TPS65090_IRQ_VSYS_STATUS_CHANGE
 
- TPS65090_MAX_REG
 
- TPS65090_NOITERM
 
- TPS65090_NUM_REGS
 
- TPS65090_REGULATOR_DCDC1
 
- TPS65090_REGULATOR_DCDC2
 
- TPS65090_REGULATOR_DCDC3
 
- TPS65090_REGULATOR_FET1
 
- TPS65090_REGULATOR_FET2
 
- TPS65090_REGULATOR_FET3
 
- TPS65090_REGULATOR_FET4
 
- TPS65090_REGULATOR_FET5
 
- TPS65090_REGULATOR_FET6
 
- TPS65090_REGULATOR_FET7
 
- TPS65090_REGULATOR_LDO1
 
- TPS65090_REGULATOR_LDO2
 
- TPS65090_REGULATOR_MAX
 
- TPS65090_REG_AD_OUT1
 
- TPS65090_REG_AD_OUT2
 
- TPS65090_REG_CG_CTRL0
 
- TPS65090_REG_CG_CTRL1
 
- TPS65090_REG_CG_CTRL2
 
- TPS65090_REG_CG_CTRL3
 
- TPS65090_REG_CG_CTRL4
 
- TPS65090_REG_CG_CTRL5
 
- TPS65090_REG_CG_STATUS1
 
- TPS65090_REG_CG_STATUS2
 
- TPS65090_REG_INTR_MASK
 
- TPS65090_REG_INTR_MASK2
 
- TPS65090_REG_INTR_STS
 
- TPS65090_REG_INTR_STS2
 
- TPS65090_VACG
 
- TPS65132_ACT_DIS_TIME_SLACK
 
- TPS65132_MAX_REGULATORS
 
- TPS65132_REGULATOR_DESC
 
- TPS65132_REGULATOR_ID_VNEG
 
- TPS65132_REGULATOR_ID_VPOS
 
- TPS65132_REG_APPS_DISP_DISN
 
- TPS65132_REG_APPS_DIS_VNEG
 
- TPS65132_REG_APPS_DIS_VPOS
 
- TPS65132_REG_CONTROL
 
- TPS65132_REG_VNEG
 
- TPS65132_REG_VPOS
 
- TPS65132_VOUT_MASK
 
- TPS65132_VOUT_N_VOLTAGE
 
- TPS65132_VOUT_STEP
 
- TPS65132_VOUT_VMAX
 
- TPS65132_VOUT_VMIN
 
- TPS65217
 
- TPS65217_BL_FDIM_1000HZ
 
- TPS65217_BL_FDIM_100HZ
 
- TPS65217_BL_FDIM_200HZ
 
- TPS65217_BL_FDIM_500HZ
 
- TPS65217_BL_ISET1
 
- TPS65217_BL_ISET2
 
- TPS65217_CHGCONFIG0_ACTIVE
 
- TPS65217_CHGCONFIG0_BATTEMP
 
- TPS65217_CHGCONFIG0_CHGTOUT
 
- TPS65217_CHGCONFIG0_DPPM
 
- TPS65217_CHGCONFIG0_PCHGTOUT
 
- TPS65217_CHGCONFIG0_TERMI
 
- TPS65217_CHGCONFIG0_TREG
 
- TPS65217_CHGCONFIG0_TSUSP
 
- TPS65217_CHGCONFIG1_CHG_EN
 
- TPS65217_CHGCONFIG1_NTC_TYPE
 
- TPS65217_CHGCONFIG1_RESET
 
- TPS65217_CHGCONFIG1_SUSP
 
- TPS65217_CHGCONFIG1_TERM
 
- TPS65217_CHGCONFIG1_TMR_ENABLE
 
- TPS65217_CHGCONFIG1_TMR_MASK
 
- TPS65217_CHGCONFIG2_DYNTMR
 
- TPS65217_CHGCONFIG2_PCHRGT
 
- TPS65217_CHGCONFIG2_TERMIF
 
- TPS65217_CHGCONFIG2_TRANGE
 
- TPS65217_CHGCONFIG2_VOREG_MASK
 
- TPS65217_CHGCONFIG2_VPREGHG
 
- TPS65217_CHGCONFIG3_DPPMTH_MASK
 
- TPS65217_CHGCONFIG3_ICHRG_MASK
 
- TPS65217_CHIPID_CHIP_MASK
 
- TPS65217_CHIPID_REV_MASK
 
- TPS65217_DCDC_1
 
- TPS65217_DCDC_2
 
- TPS65217_DCDC_3
 
- TPS65217_DEFDCDCX_DCDC_MASK
 
- TPS65217_DEFDCDCX_XADJX
 
- TPS65217_DEFLDO1_LDO1_MASK
 
- TPS65217_DEFLDO2_LDO2_MASK
 
- TPS65217_DEFLDO2_TRACK
 
- TPS65217_DEFLDO3_LDO3_EN
 
- TPS65217_DEFLDO3_LDO3_MASK
 
- TPS65217_DEFLDO4_LDO4_EN
 
- TPS65217_DEFLDO4_LDO4_MASK
 
- TPS65217_DEFPG_LDO1PGM
 
- TPS65217_DEFPG_LDO2PGM
 
- TPS65217_DEFPG_PGDLY_MASK
 
- TPS65217_DEFSLEW_GO
 
- TPS65217_DEFSLEW_GODSBL
 
- TPS65217_DEFSLEW_PFM_EN1
 
- TPS65217_DEFSLEW_PFM_EN2
 
- TPS65217_DEFSLEW_PFM_EN3
 
- TPS65217_DEFSLEW_SLEW_MASK
 
- TPS65217_DEFUVLO_UVLOHYS
 
- TPS65217_DEFUVLO_UVLO_MASK
 
- TPS65217_ENABLE_DC1_EN
 
- TPS65217_ENABLE_DC2_EN
 
- TPS65217_ENABLE_DC3_EN
 
- TPS65217_ENABLE_LDO1_EN
 
- TPS65217_ENABLE_LDO2_EN
 
- TPS65217_ENABLE_LS1_EN
 
- TPS65217_ENABLE_LS2_EN
 
- TPS65217_I2C_ID
 
- TPS65217_INT_ACI
 
- TPS65217_INT_ACM
 
- TPS65217_INT_MASK
 
- TPS65217_INT_PBI
 
- TPS65217_INT_PBM
 
- TPS65217_INT_SHIFT
 
- TPS65217_INT_USBI
 
- TPS65217_INT_USBM
 
- TPS65217_IRQ_AC
 
- TPS65217_IRQ_PB
 
- TPS65217_IRQ_USB
 
- TPS65217_LDO_1
 
- TPS65217_LDO_2
 
- TPS65217_LDO_3
 
- TPS65217_LDO_4
 
- TPS65217_MAX_REGISTER
 
- TPS65217_MAX_REG_ID
 
- TPS65217_MUXCTRL_MUX_MASK
 
- TPS65217_NUM_DCDC
 
- TPS65217_NUM_IRQ
 
- TPS65217_NUM_LDO
 
- TPS65217_NUM_REGULATOR
 
- TPS65217_PASSWORD_REGS_UNLOCK
 
- TPS65217_PGOOD_DC1_PG
 
- TPS65217_PGOOD_DC2_PG
 
- TPS65217_PGOOD_DC3_PG
 
- TPS65217_PGOOD_LDO1_PG
 
- TPS65217_PGOOD_LDO2_PG
 
- TPS65217_PGOOD_LDO3_PG
 
- TPS65217_PGOOD_LDO4_PG
 
- TPS65217_PPATH_ACSINK_ENABLE
 
- TPS65217_PPATH_AC_CURRENT_MASK
 
- TPS65217_PPATH_AC_PW_ENABLE
 
- TPS65217_PPATH_USBSINK_ENABLE
 
- TPS65217_PPATH_USB_CURRENT_MASK
 
- TPS65217_PPATH_USB_PW_ENABLE
 
- TPS65217_PROTECT_L1
 
- TPS65217_PROTECT_L2
 
- TPS65217_PROTECT_NONE
 
- TPS65217_REGULATOR
 
- TPS65217_REG_CHGCONFIG0
 
- TPS65217_REG_CHGCONFIG1
 
- TPS65217_REG_CHGCONFIG2
 
- TPS65217_REG_CHGCONFIG3
 
- TPS65217_REG_CHIPID
 
- TPS65217_REG_DEFDCDC1
 
- TPS65217_REG_DEFDCDC2
 
- TPS65217_REG_DEFDCDC3
 
- TPS65217_REG_DEFLDO1
 
- TPS65217_REG_DEFLDO2
 
- TPS65217_REG_DEFLS1
 
- TPS65217_REG_DEFLS2
 
- TPS65217_REG_DEFPG
 
- TPS65217_REG_DEFSLEW
 
- TPS65217_REG_DEFUVLO
 
- TPS65217_REG_ENABLE
 
- TPS65217_REG_INT
 
- TPS65217_REG_MAX
 
- TPS65217_REG_MUXCTRL
 
- TPS65217_REG_PASSWORD
 
- TPS65217_REG_PGOOD
 
- TPS65217_REG_PPATH
 
- TPS65217_REG_SEQ1
 
- TPS65217_REG_SEQ2
 
- TPS65217_REG_SEQ3
 
- TPS65217_REG_SEQ4
 
- TPS65217_REG_SEQ5
 
- TPS65217_REG_SEQ6
 
- TPS65217_REG_STATUS
 
- TPS65217_REG_WLEDCTRL1
 
- TPS65217_REG_WLEDCTRL2
 
- TPS65217_SEQ1_DC1_SEQ_MASK
 
- TPS65217_SEQ1_DC2_SEQ_MASK
 
- TPS65217_SEQ2_DC3_SEQ_MASK
 
- TPS65217_SEQ2_LDO1_SEQ_MASK
 
- TPS65217_SEQ3_LDO2_SEQ_MASK
 
- TPS65217_SEQ3_LDO3_SEQ_MASK
 
- TPS65217_SEQ4_LDO4_SEQ_MASK
 
- TPS65217_SEQ5_DLY1_MASK
 
- TPS65217_SEQ5_DLY2_MASK
 
- TPS65217_SEQ5_DLY3_MASK
 
- TPS65217_SEQ5_DLY4_MASK
 
- TPS65217_SEQ6_DLY5_MASK
 
- TPS65217_SEQ6_DLY6_MASK
 
- TPS65217_SEQ6_INSTDWN
 
- TPS65217_SEQ6_SEQDWN
 
- TPS65217_SEQ6_SEQUP
 
- TPS65217_STATUS_ACPWR
 
- TPS65217_STATUS_OFF
 
- TPS65217_STATUS_PB
 
- TPS65217_STATUS_USBPWR
 
- TPS65217_WLEDCTRL1_FDIM_MASK
 
- TPS65217_WLEDCTRL1_ISEL
 
- TPS65217_WLEDCTRL1_ISINK_ENABLE
 
- TPS65217_WLEDCTRL2_DUTY_MASK
 
- TPS65218
 
- TPS65218_AC_IRQ
 
- TPS65218_CC_AQC_IRQ
 
- TPS65218_CHIPID_CHIP_MASK
 
- TPS65218_CHIPID_REV_MASK
 
- TPS65218_CONFIG1_GPO2_BUF
 
- TPS65218_CONFIG1_IO1_SEL
 
- TPS65218_CONFIG1_PGDLY_MASK
 
- TPS65218_CONFIG1_STRICT
 
- TPS65218_CONFIG1_TRST
 
- TPS65218_CONFIG1_UVLO_2750000
 
- TPS65218_CONFIG1_UVLO_2950000
 
- TPS65218_CONFIG1_UVLO_3250000
 
- TPS65218_CONFIG1_UVLO_3350000
 
- TPS65218_CONFIG1_UVLO_MASK
 
- TPS65218_CONFIG2_DC12_RST
 
- TPS65218_CONFIG2_LS2ILIM_MASK
 
- TPS65218_CONFIG2_LS3ILIM_MASK
 
- TPS65218_CONFIG2_UVLOHYS
 
- TPS65218_CONFIG3_LS1DCHRG
 
- TPS65218_CONFIG3_LS1NPFO
 
- TPS65218_CONFIG3_LS2DCHRG
 
- TPS65218_CONFIG3_LS2NPFO
 
- TPS65218_CONFIG3_LS3DCHRG
 
- TPS65218_CONFIG3_LS3NPFO
 
- TPS65218_CONTROL_CC_AQ
 
- TPS65218_CONTROL_DCDC1_MASK
 
- TPS65218_CONTROL_DCDC1_PFM
 
- TPS65218_CONTROL_DCDC2_MASK
 
- TPS65218_CONTROL_DCDC2_PFM
 
- TPS65218_CONTROL_DCDC3_MASK
 
- TPS65218_CONTROL_DCDC3_PFM
 
- TPS65218_CONTROL_DCDC4_MASK
 
- TPS65218_CONTROL_DCDC4_PFM
 
- TPS65218_CONTROL_LDO1_MASK
 
- TPS65218_CONTROL_OFFNPFO
 
- TPS65218_DCDC_1
 
- TPS65218_DCDC_2
 
- TPS65218_DCDC_3
 
- TPS65218_DCDC_4
 
- TPS65218_DCDC_5
 
- TPS65218_DCDC_6
 
- TPS65218_ENABLE1_DC1_EN
 
- TPS65218_ENABLE1_DC2_EN
 
- TPS65218_ENABLE1_DC3_EN
 
- TPS65218_ENABLE1_DC4_EN
 
- TPS65218_ENABLE1_DC5_EN
 
- TPS65218_ENABLE1_DC6_EN
 
- TPS65218_ENABLE2_GPIO1
 
- TPS65218_ENABLE2_GPIO2
 
- TPS65218_ENABLE2_GPIO3
 
- TPS65218_ENABLE2_LDO1_EN
 
- TPS65218_ENABLE2_LS1_EN
 
- TPS65218_ENABLE2_LS2_EN
 
- TPS65218_ENABLE2_LS3_EN
 
- TPS65218_FLAG_DC1_FLG
 
- TPS65218_FLAG_DC2_FLG
 
- TPS65218_FLAG_DC3_FLG
 
- TPS65218_FLAG_DC4_FLG
 
- TPS65218_FLAG_GPO1_FLG
 
- TPS65218_FLAG_GPO2_FLG
 
- TPS65218_FLAG_GPO3_FLG
 
- TPS65218_FLAG_LDO1_FLG
 
- TPS65218_HOT_IRQ
 
- TPS65218_I2C_ID
 
- TPS65218_INT1_AC
 
- TPS65218_INT1_CC_AQC
 
- TPS65218_INT1_HOT
 
- TPS65218_INT1_PB
 
- TPS65218_INT1_PRGC
 
- TPS65218_INT1_VPRG
 
- TPS65218_INT2_LS1_F
 
- TPS65218_INT2_LS1_I
 
- TPS65218_INT2_LS2_F
 
- TPS65218_INT2_LS2_I
 
- TPS65218_INT2_LS3_F
 
- TPS65218_INT2_LS3_I
 
- TPS65218_INT_MASK1_AC
 
- TPS65218_INT_MASK1_CC_AQC
 
- TPS65218_INT_MASK1_HOT
 
- TPS65218_INT_MASK1_PB
 
- TPS65218_INT_MASK1_PRGC
 
- TPS65218_INT_MASK1_VPRG
 
- TPS65218_INT_MASK2_LS1_F
 
- TPS65218_INT_MASK2_LS1_I
 
- TPS65218_INT_MASK2_LS2_F
 
- TPS65218_INT_MASK2_LS2_I
 
- TPS65218_INT_MASK2_LS3_F
 
- TPS65218_INT_MASK2_LS3_I
 
- TPS65218_INVALID1_IRQ
 
- TPS65218_INVALID2_IRQ
 
- TPS65218_INVALID3_IRQ
 
- TPS65218_INVALID4_IRQ
 
- TPS65218_LDO_1
 
- TPS65218_LS1_F_IRQ
 
- TPS65218_LS1_I_IRQ
 
- TPS65218_LS2_F_IRQ
 
- TPS65218_LS2_I_IRQ
 
- TPS65218_LS3_F_IRQ
 
- TPS65218_LS3_I_IRQ
 
- TPS65218_LS_2
 
- TPS65218_LS_3
 
- TPS65218_MAX_REG_ID
 
- TPS65218_NUM_DCDC
 
- TPS65218_NUM_LDO
 
- TPS65218_NUM_LS
 
- TPS65218_NUM_REGULATOR
 
- TPS65218_PASSWORD_REGS_UNLOCK
 
- TPS65218_PB_IRQ
 
- TPS65218_PRGC_IRQ
 
- TPS65218_PROTECT_L1
 
- TPS65218_PROTECT_NONE
 
- TPS65218_REGULATOR
 
- TPS65218_REG_CHIPID
 
- TPS65218_REG_CONFIG1
 
- TPS65218_REG_CONFIG2
 
- TPS65218_REG_CONFIG3
 
- TPS65218_REG_CONTRL_SLEW_RATE
 
- TPS65218_REG_CONTROL
 
- TPS65218_REG_CONTROL_DCDC1
 
- TPS65218_REG_CONTROL_DCDC2
 
- TPS65218_REG_CONTROL_DCDC3
 
- TPS65218_REG_CONTROL_DCDC4
 
- TPS65218_REG_CONTROL_LDO1
 
- TPS65218_REG_ENABLE1
 
- TPS65218_REG_ENABLE2
 
- TPS65218_REG_FLAG
 
- TPS65218_REG_INT1
 
- TPS65218_REG_INT2
 
- TPS65218_REG_INT_MASK1
 
- TPS65218_REG_INT_MASK2
 
- TPS65218_REG_PASSWORD
 
- TPS65218_REG_SEQ1
 
- TPS65218_REG_SEQ2
 
- TPS65218_REG_SEQ3
 
- TPS65218_REG_SEQ4
 
- TPS65218_REG_SEQ5
 
- TPS65218_REG_SEQ6
 
- TPS65218_REG_SEQ7
 
- TPS65218_REG_STATUS
 
- TPS65218_REV_1_0
 
- TPS65218_REV_1_1
 
- TPS65218_REV_2_0
 
- TPS65218_REV_2_1
 
- TPS65218_SEQ1_DLY1
 
- TPS65218_SEQ1_DLY2
 
- TPS65218_SEQ1_DLY3
 
- TPS65218_SEQ1_DLY4
 
- TPS65218_SEQ1_DLY5
 
- TPS65218_SEQ1_DLY6
 
- TPS65218_SEQ1_DLY7
 
- TPS65218_SEQ1_DLY8
 
- TPS65218_SEQ2_DLY9
 
- TPS65218_SEQ2_DLYFCTR
 
- TPS65218_SEQ3_DC1_SEQ_MASK
 
- TPS65218_SEQ3_DC2_SEQ_MASK
 
- TPS65218_SEQ4_DC3_SEQ_MASK
 
- TPS65218_SEQ4_DC4_SEQ_MASK
 
- TPS65218_SEQ5_DC5_SEQ_MASK
 
- TPS65218_SEQ5_DC6_SEQ_MASK
 
- TPS65218_SEQ6_LDO1_SEQ_MASK
 
- TPS65218_SEQ6_LS1_SEQ_MASK
 
- TPS65218_SEQ7_GPO1_SEQ_MASK
 
- TPS65218_SEQ7_GPO3_SEQ_MASK
 
- TPS65218_SLEW_RATE_GO
 
- TPS65218_SLEW_RATE_GODSBL
 
- TPS65218_SLEW_RATE_SLEW_MASK
 
- TPS65218_STATUS_AC_STATE
 
- TPS65218_STATUS_CC_STAT
 
- TPS65218_STATUS_EE
 
- TPS65218_STATUS_FSEAL
 
- TPS65218_STATUS_PB_STATE
 
- TPS65218_STATUS_STATE_MASK
 
- TPS65218_VPRG_IRQ
 
- TPS658621A
 
- TPS658621CD
 
- TPS658623
 
- TPS658624
 
- TPS658640
 
- TPS658640v2
 
- TPS658643
 
- TPS6586X_DVM
 
- TPS6586X_FIXED_LDO
 
- TPS6586X_GPIOSET1
 
- TPS6586X_GPIOSET2
 
- TPS6586X_ID_LDO_0
 
- TPS6586X_ID_LDO_1
 
- TPS6586X_ID_LDO_2
 
- TPS6586X_ID_LDO_3
 
- TPS6586X_ID_LDO_4
 
- TPS6586X_ID_LDO_5
 
- TPS6586X_ID_LDO_6
 
- TPS6586X_ID_LDO_7
 
- TPS6586X_ID_LDO_8
 
- TPS6586X_ID_LDO_9
 
- TPS6586X_ID_LDO_RTC
 
- TPS6586X_ID_MAX_REGULATOR
 
- TPS6586X_ID_SM_0
 
- TPS6586X_ID_SM_1
 
- TPS6586X_ID_SM_2
 
- TPS6586X_ID_SYS
 
- TPS6586X_INT_ACK1
 
- TPS6586X_INT_ACK2
 
- TPS6586X_INT_ACK3
 
- TPS6586X_INT_ACK4
 
- TPS6586X_INT_ACUSB_OVP
 
- TPS6586X_INT_AC_DET
 
- TPS6586X_INT_ADC
 
- TPS6586X_INT_BAT_DET
 
- TPS6586X_INT_CHG_STAT
 
- TPS6586X_INT_CHG_TEMP
 
- TPS6586X_INT_COMP_DET
 
- TPS6586X_INT_LOW_SYS
 
- TPS6586X_INT_MASK1
 
- TPS6586X_INT_MASK2
 
- TPS6586X_INT_MASK3
 
- TPS6586X_INT_MASK4
 
- TPS6586X_INT_MASK5
 
- TPS6586X_INT_PLDO_0
 
- TPS6586X_INT_PLDO_1
 
- TPS6586X_INT_PLDO_2
 
- TPS6586X_INT_PLDO_3
 
- TPS6586X_INT_PLDO_4
 
- TPS6586X_INT_PLDO_5
 
- TPS6586X_INT_PLDO_6
 
- TPS6586X_INT_PLDO_7
 
- TPS6586X_INT_PLDO_8
 
- TPS6586X_INT_PLDO_9
 
- TPS6586X_INT_PP
 
- TPS6586X_INT_PSM_0
 
- TPS6586X_INT_PSM_1
 
- TPS6586X_INT_PSM_2
 
- TPS6586X_INT_PSM_3
 
- TPS6586X_INT_RESUME
 
- TPS6586X_INT_RTC_ALM1
 
- TPS6586X_INT_RTC_ALM2
 
- TPS6586X_INT_USB_DET
 
- TPS6586X_IRQ
 
- TPS6586X_LDO
 
- TPS6586X_LDO2AV1
 
- TPS6586X_LDO2AV2
 
- TPS6586X_LDO2BV1
 
- TPS6586X_LDO2BV2
 
- TPS6586X_LDO4V1
 
- TPS6586X_LDO4V2
 
- TPS6586X_LDO_LINEAR
 
- TPS6586X_MAX_REGISTER
 
- TPS6586X_REGULATOR
 
- TPS6586X_REGULATOR_LINEAR
 
- TPS6586X_RTC_CL_SEL_12_5PF
 
- TPS6586X_RTC_CL_SEL_1_5PF
 
- TPS6586X_RTC_CL_SEL_6_5PF
 
- TPS6586X_RTC_CL_SEL_7_5PF
 
- TPS6586X_SLEW_RATE_110UV
 
- TPS6586X_SLEW_RATE_1760UV
 
- TPS6586X_SLEW_RATE_220UV
 
- TPS6586X_SLEW_RATE_3520UV
 
- TPS6586X_SLEW_RATE_440UV
 
- TPS6586X_SLEW_RATE_7040UV
 
- TPS6586X_SLEW_RATE_880UV
 
- TPS6586X_SLEW_RATE_INSTANTLY
 
- TPS6586X_SLEW_RATE_MASK
 
- TPS6586X_SLEW_RATE_SET
 
- TPS6586X_SM0SL
 
- TPS6586X_SM0V1
 
- TPS6586X_SM0V2
 
- TPS6586X_SM1SL
 
- TPS6586X_SM1V1
 
- TPS6586X_SM1V2
 
- TPS6586X_SMODE1
 
- TPS6586X_SMODE2
 
- TPS6586X_SUPPLYENA
 
- TPS6586X_SUPPLYENB
 
- TPS6586X_SUPPLYENC
 
- TPS6586X_SUPPLYEND
 
- TPS6586X_SUPPLYENE
 
- TPS6586X_SUPPLYV1
 
- TPS6586X_SUPPLYV2
 
- TPS6586X_SUPPLYV3
 
- TPS6586X_SUPPLYV4
 
- TPS6586X_SUPPLYV5
 
- TPS6586X_SUPPLYV6
 
- TPS6586X_SYS_REGULATOR
 
- TPS6586X_VCC1
 
- TPS6586X_VCC2
 
- TPS6586X_VERSIONCRC
 
- TPS659038_REGEN2_CTRL
 
- TPS65910
 
- TPS65910_ALARM_DAYS
 
- TPS65910_ALARM_HOURS
 
- TPS65910_ALARM_MINUTES
 
- TPS65910_ALARM_MONTHS
 
- TPS65910_ALARM_SECONDS
 
- TPS65910_ALARM_YEARS
 
- TPS65910_BBCH
 
- TPS65910_BCK1
 
- TPS65910_BCK2
 
- TPS65910_BCK3
 
- TPS65910_BCK4
 
- TPS65910_BCK5
 
- TPS65910_DAYS
 
- TPS65910_DCDCCTRL
 
- TPS65910_DEVCTRL
 
- TPS65910_DEVCTRL2
 
- TPS65910_EN1_LDO_ASS
 
- TPS65910_EN1_SMPS_ASS
 
- TPS65910_EN2_LDO_ASS
 
- TPS65910_EN2_SMPS_ASS
 
- TPS65910_EN3_LDO_ASS
 
- TPS65910_GPIO0
 
- TPS65910_GPIO1
 
- TPS65910_GPIO2
 
- TPS65910_GPIO3
 
- TPS65910_GPIO4
 
- TPS65910_GPIO5
 
- TPS65910_GPIO6
 
- TPS65910_GPIO7
 
- TPS65910_GPIO8
 
- TPS65910_GPIO_CFG
 
- TPS65910_GPIO_DEB
 
- TPS65910_GPIO_PUEN
 
- TPS65910_GPIO_SET
 
- TPS65910_GPIO_STS
 
- TPS65910_HOURS
 
- TPS65910_INT_MSK
 
- TPS65910_INT_MSK2
 
- TPS65910_INT_MSK2_GPIO0_F_IT_MSK_MASK
 
- TPS65910_INT_MSK2_GPIO0_F_IT_MSK_SHIFT
 
- TPS65910_INT_MSK2_GPIO0_R_IT_MSK_MASK
 
- TPS65910_INT_MSK2_GPIO0_R_IT_MSK_SHIFT
 
- TPS65910_INT_MSK3
 
- TPS65910_INT_MSK_HOTDIE_IT_MSK_MASK
 
- TPS65910_INT_MSK_HOTDIE_IT_MSK_SHIFT
 
- TPS65910_INT_MSK_PWRHOLD_IT_MSK_MASK
 
- TPS65910_INT_MSK_PWRHOLD_IT_MSK_SHIFT
 
- TPS65910_INT_MSK_PWRON_IT_MSK_MASK
 
- TPS65910_INT_MSK_PWRON_IT_MSK_SHIFT
 
- TPS65910_INT_MSK_PWRON_LP_IT_MSK_MASK
 
- TPS65910_INT_MSK_PWRON_LP_IT_MSK_SHIFT
 
- TPS65910_INT_MSK_RTC_ALARM_IT_MSK_MASK
 
- TPS65910_INT_MSK_RTC_ALARM_IT_MSK_SHIFT
 
- TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_MASK
 
- TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_SHIFT
 
- TPS65910_INT_MSK_VMBDCH_IT_MSK_MASK
 
- TPS65910_INT_MSK_VMBDCH_IT_MSK_SHIFT
 
- TPS65910_INT_MSK_VMBHI_IT_MSK_MASK
 
- TPS65910_INT_MSK_VMBHI_IT_MSK_SHIFT
 
- TPS65910_INT_STS
 
- TPS65910_INT_STS2
 
- TPS65910_INT_STS2_GPIO0_F_IT_MASK
 
- TPS65910_INT_STS2_GPIO0_F_IT_SHIFT
 
- TPS65910_INT_STS2_GPIO0_R_IT_MASK
 
- TPS65910_INT_STS2_GPIO0_R_IT_SHIFT
 
- TPS65910_INT_STS3
 
- TPS65910_INT_STS_HOTDIE_IT_MASK
 
- TPS65910_INT_STS_HOTDIE_IT_SHIFT
 
- TPS65910_INT_STS_PWRHOLD_F_IT_MASK
 
- TPS65910_INT_STS_PWRHOLD_F_IT_SHIFT
 
- TPS65910_INT_STS_PWRON_IT_MASK
 
- TPS65910_INT_STS_PWRON_IT_SHIFT
 
- TPS65910_INT_STS_PWRON_LP_IT_MASK
 
- TPS65910_INT_STS_PWRON_LP_IT_SHIFT
 
- TPS65910_INT_STS_RTC_ALARM_IT_MASK
 
- TPS65910_INT_STS_RTC_ALARM_IT_SHIFT
 
- TPS65910_INT_STS_RTC_PERIOD_IT_MASK
 
- TPS65910_INT_STS_RTC_PERIOD_IT_SHIFT
 
- TPS65910_INT_STS_VMBDCH_IT_MASK
 
- TPS65910_INT_STS_VMBDCH_IT_SHIFT
 
- TPS65910_INT_STS_VMBHI_IT_MASK
 
- TPS65910_INT_STS_VMBHI_IT_SHIFT
 
- TPS65910_IRQ_GPIO_F
 
- TPS65910_IRQ_GPIO_R
 
- TPS65910_IRQ_HOTDIE
 
- TPS65910_IRQ_PWRHOLD
 
- TPS65910_IRQ_PWRON
 
- TPS65910_IRQ_PWRON_LP
 
- TPS65910_IRQ_RTC_ALARM
 
- TPS65910_IRQ_RTC_PERIOD
 
- TPS65910_IRQ_VBAT_VMBDCH
 
- TPS65910_IRQ_VBAT_VMHI
 
- TPS65910_JTAGVERNUM
 
- TPS65910_MAX_REGISTER
 
- TPS65910_MINUTES
 
- TPS65910_MONTHS
 
- TPS65910_NUM_GPIO
 
- TPS65910_NUM_IRQ
 
- TPS65910_NUM_REGS
 
- TPS65910_PUADEN
 
- TPS65910_REF
 
- TPS65910_REG_VAUX1
 
- TPS65910_REG_VAUX2
 
- TPS65910_REG_VAUX33
 
- TPS65910_REG_VBB
 
- TPS65910_REG_VDAC
 
- TPS65910_REG_VDD1
 
- TPS65910_REG_VDD2
 
- TPS65910_REG_VDD3
 
- TPS65910_REG_VDIG1
 
- TPS65910_REG_VDIG2
 
- TPS65910_REG_VIO
 
- TPS65910_REG_VMMC
 
- TPS65910_REG_VPLL
 
- TPS65910_REG_VRTC
 
- TPS65910_RTC_COMP_LSB
 
- TPS65910_RTC_COMP_MSB
 
- TPS65910_RTC_CTRL
 
- TPS65910_RTC_CTRL_AUTO_COMP
 
- TPS65910_RTC_CTRL_GET_TIME
 
- TPS65910_RTC_CTRL_STOP_RTC
 
- TPS65910_RTC_INTERRUPTS
 
- TPS65910_RTC_INTERRUPTS_EVERY
 
- TPS65910_RTC_INTERRUPTS_IT_ALARM
 
- TPS65910_RTC_RESET_STATUS
 
- TPS65910_RTC_RES_PROG
 
- TPS65910_RTC_STATUS
 
- TPS65910_RTC_STATUS_ALARM
 
- TPS65910_SECONDS
 
- TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1
 
- TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2
 
- TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3
 
- TPS65910_SLEEP_KEEP_LDO_ON
 
- TPS65910_SLEEP_KEEP_RES_ON
 
- TPS65910_SLEEP_SET_LDO_OFF
 
- TPS65910_SLEEP_SET_RES_OFF
 
- TPS65910_SPARE
 
- TPS65910_SUPPLY_STATE_ENABLED
 
- TPS65910_THERM
 
- TPS65910_VAUX1
 
- TPS65910_VAUX2
 
- TPS65910_VAUX33
 
- TPS65910_VDAC
 
- TPS65910_VDD1
 
- TPS65910_VDD1_OP
 
- TPS65910_VDD1_SR
 
- TPS65910_VDD2
 
- TPS65910_VDD2_OP
 
- TPS65910_VDD2_SR
 
- TPS65910_VDD3
 
- TPS65910_VDIG1
 
- TPS65910_VDIG2
 
- TPS65910_VIO
 
- TPS65910_VMMC
 
- TPS65910_VPLL
 
- TPS65910_VRTC
 
- TPS65910_WEEKS
 
- TPS65910_YEARS
 
- TPS65911
 
- TPS65911_IRQ_GPIO0_F
 
- TPS65911_IRQ_GPIO0_R
 
- TPS65911_IRQ_GPIO1_F
 
- TPS65911_IRQ_GPIO1_R
 
- TPS65911_IRQ_GPIO2_F
 
- TPS65911_IRQ_GPIO2_R
 
- TPS65911_IRQ_GPIO3_F
 
- TPS65911_IRQ_GPIO3_R
 
- TPS65911_IRQ_GPIO4_F
 
- TPS65911_IRQ_GPIO4_R
 
- TPS65911_IRQ_GPIO5_F
 
- TPS65911_IRQ_GPIO5_R
 
- TPS65911_IRQ_HOTDIE
 
- TPS65911_IRQ_PWRDN
 
- TPS65911_IRQ_PWRHOLD_F
 
- TPS65911_IRQ_PWRHOLD_R
 
- TPS65911_IRQ_PWRON
 
- TPS65911_IRQ_PWRON_LP
 
- TPS65911_IRQ_RTC_ALARM
 
- TPS65911_IRQ_RTC_PERIOD
 
- TPS65911_IRQ_VBAT_VMHI
 
- TPS65911_IRQ_VMBCH2_H
 
- TPS65911_IRQ_VMBCH2_L
 
- TPS65911_IRQ_WTCHDG
 
- TPS65911_LDO1
 
- TPS65911_LDO2
 
- TPS65911_LDO3
 
- TPS65911_LDO4
 
- TPS65911_LDO5
 
- TPS65911_LDO6
 
- TPS65911_LDO7
 
- TPS65911_LDO8
 
- TPS65911_NUM_GPIO
 
- TPS65911_NUM_IRQ
 
- TPS65911_REG_LDO1
 
- TPS65911_REG_LDO2
 
- TPS65911_REG_LDO3
 
- TPS65911_REG_LDO4
 
- TPS65911_REG_LDO5
 
- TPS65911_REG_LDO6
 
- TPS65911_REG_LDO7
 
- TPS65911_REG_LDO8
 
- TPS65911_REG_VDDCTRL
 
- TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP
 
- TPS65911_VDDCTRL
 
- TPS65911_VDDCTRL_OP
 
- TPS65911_VDDCTRL_SR
 
- TPS65911_VMBCH
 
- TPS65911_VMBCH2
 
- TPS65912_CLK32OUT
 
- TPS65912_DCDC1_AVS
 
- TPS65912_DCDC1_CTRL
 
- TPS65912_DCDC1_LIMIT
 
- TPS65912_DCDC1_OP
 
- TPS65912_DCDC2_AVS
 
- TPS65912_DCDC2_CTRL
 
- TPS65912_DCDC2_LIMIT
 
- TPS65912_DCDC2_OP
 
- TPS65912_DCDC3_AVS
 
- TPS65912_DCDC3_CTRL
 
- TPS65912_DCDC3_LIMIT
 
- TPS65912_DCDC3_OP
 
- TPS65912_DCDC4_AVS
 
- TPS65912_DCDC4_CTRL
 
- TPS65912_DCDC4_LIMIT
 
- TPS65912_DCDC4_OP
 
- TPS65912_DEF_VOLT
 
- TPS65912_DEF_VOLT_MAPPING
 
- TPS65912_DEVCTRL
 
- TPS65912_DEVCTRL2
 
- TPS65912_DISCHARGE
 
- TPS65912_DISCHARGE2
 
- TPS65912_EN1_SET1
 
- TPS65912_EN1_SET2
 
- TPS65912_EN2_SET1
 
- TPS65912_EN2_SET2
 
- TPS65912_EN3_SET1
 
- TPS65912_EN3_SET2
 
- TPS65912_EN4_SET1
 
- TPS65912_EN4_SET2
 
- TPS65912_GPIO1
 
- TPS65912_GPIO2
 
- TPS65912_GPIO3
 
- TPS65912_GPIO4
 
- TPS65912_GPIO5
 
- TPS65912_I2C_SPI_CFG
 
- TPS65912_INT_MSK
 
- TPS65912_INT_MSK2
 
- TPS65912_INT_MSK3
 
- TPS65912_INT_MSK4
 
- TPS65912_INT_STS
 
- TPS65912_INT_STS2
 
- TPS65912_INT_STS2_GPIO2_F
 
- TPS65912_INT_STS2_GPIO2_R
 
- TPS65912_INT_STS2_GPIO3_F
 
- TPS65912_INT_STS2_GPIO3_R
 
- TPS65912_INT_STS2_GPIO4_F
 
- TPS65912_INT_STS2_GPIO4_R
 
- TPS65912_INT_STS2_GPIO5_F
 
- TPS65912_INT_STS2_GPIO5_R
 
- TPS65912_INT_STS3
 
- TPS65912_INT_STS3_PGOOD_DCDC1
 
- TPS65912_INT_STS3_PGOOD_DCDC2
 
- TPS65912_INT_STS3_PGOOD_DCDC3
 
- TPS65912_INT_STS3_PGOOD_DCDC4
 
- TPS65912_INT_STS3_PGOOD_LDO1
 
- TPS65912_INT_STS3_PGOOD_LDO2
 
- TPS65912_INT_STS3_PGOOD_LDO3
 
- TPS65912_INT_STS3_PGOOD_LDO4
 
- TPS65912_INT_STS4
 
- TPS65912_INT_STS4_PGOOD_LDO10
 
- TPS65912_INT_STS4_PGOOD_LDO5
 
- TPS65912_INT_STS4_PGOOD_LDO6
 
- TPS65912_INT_STS4_PGOOD_LDO7
 
- TPS65912_INT_STS4_PGOOD_LDO8
 
- TPS65912_INT_STS4_PGOOD_LDO9
 
- TPS65912_INT_STS_GPIO1_F
 
- TPS65912_INT_STS_GPIO1_R
 
- TPS65912_INT_STS_HOTDIE
 
- TPS65912_INT_STS_PWRHOLD_F
 
- TPS65912_INT_STS_PWRHOLD_R
 
- TPS65912_INT_STS_PWRON
 
- TPS65912_INT_STS_PWRON_LP
 
- TPS65912_INT_STS_VMON
 
- TPS65912_IRQ_GPIO1_F
 
- TPS65912_IRQ_GPIO1_R
 
- TPS65912_IRQ_GPIO2_F
 
- TPS65912_IRQ_GPIO2_R
 
- TPS65912_IRQ_GPIO3_F
 
- TPS65912_IRQ_GPIO3_R
 
- TPS65912_IRQ_GPIO4_F
 
- TPS65912_IRQ_GPIO4_R
 
- TPS65912_IRQ_GPIO5_F
 
- TPS65912_IRQ_GPIO5_R
 
- TPS65912_IRQ_HOTDIE
 
- TPS65912_IRQ_PGOOD_DCDC1
 
- TPS65912_IRQ_PGOOD_DCDC2
 
- TPS65912_IRQ_PGOOD_DCDC3
 
- TPS65912_IRQ_PGOOD_DCDC4
 
- TPS65912_IRQ_PGOOD_LDO1
 
- TPS65912_IRQ_PGOOD_LDO10
 
- TPS65912_IRQ_PGOOD_LDO2
 
- TPS65912_IRQ_PGOOD_LDO3
 
- TPS65912_IRQ_PGOOD_LDO4
 
- TPS65912_IRQ_PGOOD_LDO5
 
- TPS65912_IRQ_PGOOD_LDO6
 
- TPS65912_IRQ_PGOOD_LDO7
 
- TPS65912_IRQ_PGOOD_LDO8
 
- TPS65912_IRQ_PGOOD_LDO9
 
- TPS65912_IRQ_PWRHOLD_F
 
- TPS65912_IRQ_PWRHOLD_R
 
- TPS65912_IRQ_PWRON
 
- TPS65912_IRQ_PWRON_LP
 
- TPS65912_IRQ_VMON
 
- TPS65912_KEEP_ON
 
- TPS65912_KEEP_ON2
 
- TPS65912_LDO10
 
- TPS65912_LDO1_AVS
 
- TPS65912_LDO1_LIMIT
 
- TPS65912_LDO1_OP
 
- TPS65912_LDO2_AVS
 
- TPS65912_LDO2_LIMIT
 
- TPS65912_LDO2_OP
 
- TPS65912_LDO3_AVS
 
- TPS65912_LDO3_LIMIT
 
- TPS65912_LDO3_OP
 
- TPS65912_LDO4_AVS
 
- TPS65912_LDO4_LIMIT
 
- TPS65912_LDO4_OP
 
- TPS65912_LDO5
 
- TPS65912_LDO6
 
- TPS65912_LDO7
 
- TPS65912_LDO8
 
- TPS65912_LDO9
 
- TPS65912_LEDA_CTRL1
 
- TPS65912_LEDA_CTRL2
 
- TPS65912_LEDA_CTRL3
 
- TPS65912_LEDA_CTRL4
 
- TPS65912_LEDA_CTRL5
 
- TPS65912_LEDA_CTRL6
 
- TPS65912_LEDA_CTRL7
 
- TPS65912_LEDA_CTRL8
 
- TPS65912_LEDB_CTRL1
 
- TPS65912_LEDB_CTRL2
 
- TPS65912_LEDB_CTRL3
 
- TPS65912_LEDB_CTRL4
 
- TPS65912_LEDB_CTRL5
 
- TPS65912_LEDB_CTRL6
 
- TPS65912_LEDB_CTRL7
 
- TPS65912_LEDB_CTRL8
 
- TPS65912_LEDC_CTRL1
 
- TPS65912_LEDC_CTRL2
 
- TPS65912_LEDC_CTRL3
 
- TPS65912_LEDC_CTRL4
 
- TPS65912_LEDC_CTRL5
 
- TPS65912_LEDC_CTRL6
 
- TPS65912_LEDC_CTRL7
 
- TPS65912_LEDC_CTRL8
 
- TPS65912_LED_RAMP_DOWN_TIME
 
- TPS65912_LED_RAMP_UP_TIME
 
- TPS65912_LED_SEQ_EN
 
- TPS65912_LOADSWITCH
 
- TPS65912_PGOOD
 
- TPS65912_PGOOD2
 
- TPS65912_REGULATOR
 
- TPS65912_SET_OFF1
 
- TPS65912_SET_OFF2
 
- TPS65912_SPARE
 
- TPS65912_THRM
 
- TPS65912_VERNUM
 
- TPS65912_VMON
 
- TPS65917_ENABLE1_LDO_ASSIGN1
 
- TPS65917_ENABLE1_LDO_ASSIGN1_LDO1
 
- TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT
 
- TPS65917_ENABLE1_LDO_ASSIGN1_LDO2
 
- TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT
 
- TPS65917_ENABLE1_LDO_ASSIGN1_LDO4
 
- TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT
 
- TPS65917_ENABLE1_LDO_ASSIGN2
 
- TPS65917_ENABLE1_LDO_ASSIGN2_LDO3
 
- TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT
 
- TPS65917_ENABLE1_LDO_ASSIGN2_LDO5
 
- TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT
 
- TPS65917_ENABLE1_RES_ASSIGN
 
- TPS65917_ENABLE1_RES_ASSIGN_PLLEN
 
- TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT
 
- TPS65917_ENABLE1_RES_ASSIGN_REGEN1
 
- TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT
 
- TPS65917_ENABLE1_RES_ASSIGN_REGEN2
 
- TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT
 
- TPS65917_ENABLE1_RES_ASSIGN_REGEN3
 
- TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT
 
- TPS65917_ENABLE1_SMPS_ASSIGN
 
- TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1
 
- TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT
 
- TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2
 
- TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT
 
- TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3
 
- TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT
 
- TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4
 
- TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT
 
- TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5
 
- TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT
 
- TPS65917_ENABLE2_LDO_ASSIGN1
 
- TPS65917_ENABLE2_LDO_ASSIGN1_LDO1
 
- TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT
 
- TPS65917_ENABLE2_LDO_ASSIGN1_LDO2
 
- TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT
 
- TPS65917_ENABLE2_LDO_ASSIGN1_LDO4
 
- TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT
 
- TPS65917_ENABLE2_LDO_ASSIGN2
 
- TPS65917_ENABLE2_LDO_ASSIGN2_LDO3
 
- TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT
 
- TPS65917_ENABLE2_LDO_ASSIGN2_LDO5
 
- TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT
 
- TPS65917_ENABLE2_RES_ASSIGN
 
- TPS65917_ENABLE2_RES_ASSIGN_PLLEN
 
- TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT
 
- TPS65917_ENABLE2_RES_ASSIGN_REGEN1
 
- TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT
 
- TPS65917_ENABLE2_RES_ASSIGN_REGEN2
 
- TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT
 
- TPS65917_ENABLE2_RES_ASSIGN_REGEN3
 
- TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT
 
- TPS65917_ENABLE2_SMPS_ASSIGN
 
- TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1
 
- TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT
 
- TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2
 
- TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT
 
- TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3
 
- TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT
 
- TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4
 
- TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT
 
- TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5
 
- TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT
 
- TPS65917_EXTERNAL_REQSTR_ID_LDO1
 
- TPS65917_EXTERNAL_REQSTR_ID_LDO2
 
- TPS65917_EXTERNAL_REQSTR_ID_LDO3
 
- TPS65917_EXTERNAL_REQSTR_ID_LDO4
 
- TPS65917_EXTERNAL_REQSTR_ID_LDO5
 
- TPS65917_EXTERNAL_REQSTR_ID_MAX
 
- TPS65917_EXTERNAL_REQSTR_ID_REGEN1
 
- TPS65917_EXTERNAL_REQSTR_ID_REGEN2
 
- TPS65917_EXTERNAL_REQSTR_ID_REGEN3
 
- TPS65917_EXTERNAL_REQSTR_ID_SMPS1
 
- TPS65917_EXTERNAL_REQSTR_ID_SMPS12
 
- TPS65917_EXTERNAL_REQSTR_ID_SMPS2
 
- TPS65917_EXTERNAL_REQSTR_ID_SMPS3
 
- TPS65917_EXTERNAL_REQSTR_ID_SMPS4
 
- TPS65917_EXTERNAL_REQSTR_ID_SMPS5
 
- TPS65917_FSD_IRQ
 
- TPS65917_GPADC_AUTO_0_IRQ
 
- TPS65917_GPADC_AUTO_1_IRQ
 
- TPS65917_GPADC_EOC_SW_IRQ
 
- TPS65917_GPIO_0_IRQ
 
- TPS65917_GPIO_1_IRQ
 
- TPS65917_GPIO_2_IRQ
 
- TPS65917_GPIO_3_IRQ
 
- TPS65917_GPIO_4_IRQ
 
- TPS65917_GPIO_5_IRQ
 
- TPS65917_GPIO_6_IRQ
 
- TPS65917_HOTDIE_IRQ
 
- TPS65917_INT1_LINE_STATE
 
- TPS65917_INT1_LINE_STATE_HOTDIE
 
- TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT
 
- TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY
 
- TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT
 
- TPS65917_INT1_LINE_STATE_PWRDOWN
 
- TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT
 
- TPS65917_INT1_LINE_STATE_PWRON
 
- TPS65917_INT1_LINE_STATE_PWRON_SHIFT
 
- TPS65917_INT1_LINE_STATE_VSYS_MON
 
- TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT
 
- TPS65917_INT1_MASK
 
- TPS65917_INT1_MASK_HOTDIE
 
- TPS65917_INT1_MASK_HOTDIE_SHIFT
 
- TPS65917_INT1_MASK_LONG_PRESS_KEY
 
- TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT
 
- TPS65917_INT1_MASK_PWRDOWN
 
- TPS65917_INT1_MASK_PWRDOWN_SHIFT
 
- TPS65917_INT1_MASK_PWRON
 
- TPS65917_INT1_MASK_PWRON_SHIFT
 
- TPS65917_INT1_MASK_VSYS_MON
 
- TPS65917_INT1_MASK_VSYS_MON_SHIFT
 
- TPS65917_INT1_STATUS
 
- TPS65917_INT1_STATUS_HOTDIE
 
- TPS65917_INT1_STATUS_HOTDIE_SHIFT
 
- TPS65917_INT1_STATUS_LONG_PRESS_KEY
 
- TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT
 
- TPS65917_INT1_STATUS_PWRDOWN
 
- TPS65917_INT1_STATUS_PWRDOWN_SHIFT
 
- TPS65917_INT1_STATUS_PWRON
 
- TPS65917_INT1_STATUS_PWRON_SHIFT
 
- TPS65917_INT1_STATUS_VSYS_MON
 
- TPS65917_INT1_STATUS_VSYS_MON_SHIFT
 
- TPS65917_INT2_LINE_STATE
 
- TPS65917_INT2_LINE_STATE_FSD
 
- TPS65917_INT2_LINE_STATE_FSD_SHIFT
 
- TPS65917_INT2_LINE_STATE_OTP_ERROR
 
- TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT
 
- TPS65917_INT2_LINE_STATE_RESET_IN
 
- TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT
 
- TPS65917_INT2_LINE_STATE_SHORT
 
- TPS65917_INT2_LINE_STATE_SHORT_SHIFT
 
- TPS65917_INT2_LINE_STATE_WDT
 
- TPS65917_INT2_LINE_STATE_WDT_SHIFT
 
- TPS65917_INT2_MASK
 
- TPS65917_INT2_MASK_FSD
 
- TPS65917_INT2_MASK_FSD_SHIFT
 
- TPS65917_INT2_MASK_OTP_ERROR_SHIFT
 
- TPS65917_INT2_MASK_OTP_ERROR_TIMER
 
- TPS65917_INT2_MASK_RESET_IN
 
- TPS65917_INT2_MASK_RESET_IN_SHIFT
 
- TPS65917_INT2_MASK_SHORT
 
- TPS65917_INT2_MASK_SHORT_SHIFT
 
- TPS65917_INT2_MASK_WDT
 
- TPS65917_INT2_MASK_WDT_SHIFT
 
- TPS65917_INT2_STATUS
 
- TPS65917_INT2_STATUS_FSD
 
- TPS65917_INT2_STATUS_FSD_SHIFT
 
- TPS65917_INT2_STATUS_OTP_ERROR
 
- TPS65917_INT2_STATUS_OTP_ERROR_SHIFT
 
- TPS65917_INT2_STATUS_RESET_IN
 
- TPS65917_INT2_STATUS_RESET_IN_SHIFT
 
- TPS65917_INT2_STATUS_SHORT
 
- TPS65917_INT2_STATUS_SHORT_SHIFT
 
- TPS65917_INT2_STATUS_WDT
 
- TPS65917_INT2_STATUS_WDT_SHIFT
 
- TPS65917_INT3_LINE_STATE
 
- TPS65917_INT3_LINE_STATE_GPADC_AUTO_0
 
- TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT
 
- TPS65917_INT3_LINE_STATE_GPADC_AUTO_1
 
- TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT
 
- TPS65917_INT3_LINE_STATE_GPADC_EOC_SW
 
- TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT
 
- TPS65917_INT3_LINE_STATE_VBUS
 
- TPS65917_INT3_LINE_STATE_VBUS_SHIFT
 
- TPS65917_INT3_MASK
 
- TPS65917_INT3_MASK_GPADC_AUTO_0
 
- TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT
 
- TPS65917_INT3_MASK_GPADC_AUTO_1
 
- TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT
 
- TPS65917_INT3_MASK_GPADC_EOC_SW
 
- TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT
 
- TPS65917_INT3_MASK_VBUS
 
- TPS65917_INT3_MASK_VBUS_SHIFT
 
- TPS65917_INT3_STATUS
 
- TPS65917_INT3_STATUS_GPADC_AUTO_0
 
- TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT
 
- TPS65917_INT3_STATUS_GPADC_AUTO_1
 
- TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT
 
- TPS65917_INT3_STATUS_GPADC_EOC_SW
 
- TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT
 
- TPS65917_INT3_STATUS_VBUS
 
- TPS65917_INT3_STATUS_VBUS_SHIFT
 
- TPS65917_INT4_EDGE_DETECT1
 
- TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING
 
- TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT
 
- TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING
 
- TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT
 
- TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING
 
- TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT
 
- TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING
 
- TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT
 
- TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING
 
- TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT
 
- TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING
 
- TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT
 
- TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING
 
- TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT
 
- TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING
 
- TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT
 
- TPS65917_INT4_EDGE_DETECT2
 
- TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING
 
- TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT
 
- TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING
 
- TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT
 
- TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING
 
- TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT
 
- TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING
 
- TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT
 
- TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING
 
- TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT
 
- TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING
 
- TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT
 
- TPS65917_INT4_LINE_STATE
 
- TPS65917_INT4_LINE_STATE_GPIO_0
 
- TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT
 
- TPS65917_INT4_LINE_STATE_GPIO_1
 
- TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT
 
- TPS65917_INT4_LINE_STATE_GPIO_2
 
- TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT
 
- TPS65917_INT4_LINE_STATE_GPIO_3
 
- TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT
 
- TPS65917_INT4_LINE_STATE_GPIO_4
 
- TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT
 
- TPS65917_INT4_LINE_STATE_GPIO_5
 
- TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT
 
- TPS65917_INT4_LINE_STATE_GPIO_6
 
- TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT
 
- TPS65917_INT4_MASK
 
- TPS65917_INT4_MASK_GPIO_0
 
- TPS65917_INT4_MASK_GPIO_0_SHIFT
 
- TPS65917_INT4_MASK_GPIO_1
 
- TPS65917_INT4_MASK_GPIO_1_SHIFT
 
- TPS65917_INT4_MASK_GPIO_2
 
- TPS65917_INT4_MASK_GPIO_2_SHIFT
 
- TPS65917_INT4_MASK_GPIO_3
 
- TPS65917_INT4_MASK_GPIO_3_SHIFT
 
- TPS65917_INT4_MASK_GPIO_4
 
- TPS65917_INT4_MASK_GPIO_4_SHIFT
 
- TPS65917_INT4_MASK_GPIO_5
 
- TPS65917_INT4_MASK_GPIO_5_SHIFT
 
- TPS65917_INT4_MASK_GPIO_6
 
- TPS65917_INT4_MASK_GPIO_6_SHIFT
 
- TPS65917_INT4_STATUS
 
- TPS65917_INT4_STATUS_GPIO_0
 
- TPS65917_INT4_STATUS_GPIO_0_SHIFT
 
- TPS65917_INT4_STATUS_GPIO_1
 
- TPS65917_INT4_STATUS_GPIO_1_SHIFT
 
- TPS65917_INT4_STATUS_GPIO_2
 
- TPS65917_INT4_STATUS_GPIO_2_SHIFT
 
- TPS65917_INT4_STATUS_GPIO_3
 
- TPS65917_INT4_STATUS_GPIO_3_SHIFT
 
- TPS65917_INT4_STATUS_GPIO_4
 
- TPS65917_INT4_STATUS_GPIO_4_SHIFT
 
- TPS65917_INT4_STATUS_GPIO_5
 
- TPS65917_INT4_STATUS_GPIO_5_SHIFT
 
- TPS65917_INT4_STATUS_GPIO_6
 
- TPS65917_INT4_STATUS_GPIO_6_SHIFT
 
- TPS65917_INT_CTRL
 
- TPS65917_INT_CTRL_INT_CLEAR
 
- TPS65917_INT_CTRL_INT_CLEAR_SHIFT
 
- TPS65917_INT_CTRL_INT_PENDING
 
- TPS65917_INT_CTRL_INT_PENDING_SHIFT
 
- TPS65917_LDO1_CTRL
 
- TPS65917_LDO1_CTRL_BYPASS_EN
 
- TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT
 
- TPS65917_LDO1_CTRL_MODE_ACTIVE
 
- TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT
 
- TPS65917_LDO1_CTRL_MODE_SLEEP
 
- TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT
 
- TPS65917_LDO1_CTRL_STATUS
 
- TPS65917_LDO1_CTRL_STATUS_SHIFT
 
- TPS65917_LDO1_CTRL_WR_S
 
- TPS65917_LDO1_CTRL_WR_S_SHIFT
 
- TPS65917_LDO1_VOLTAGE
 
- TPS65917_LDO1_VOLTAGE_VSEL_MASK
 
- TPS65917_LDO1_VOLTAGE_VSEL_SHIFT
 
- TPS65917_LDO2_CTRL
 
- TPS65917_LDO2_CTRL_BYPASS_EN
 
- TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT
 
- TPS65917_LDO2_CTRL_MODE_ACTIVE
 
- TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT
 
- TPS65917_LDO2_CTRL_MODE_SLEEP
 
- TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT
 
- TPS65917_LDO2_CTRL_STATUS
 
- TPS65917_LDO2_CTRL_STATUS_SHIFT
 
- TPS65917_LDO2_CTRL_WR_S
 
- TPS65917_LDO2_CTRL_WR_S_SHIFT
 
- TPS65917_LDO2_VOLTAGE
 
- TPS65917_LDO2_VOLTAGE_VSEL_MASK
 
- TPS65917_LDO2_VOLTAGE_VSEL_SHIFT
 
- TPS65917_LDO3_CTRL
 
- TPS65917_LDO3_CTRL_MODE_ACTIVE
 
- TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT
 
- TPS65917_LDO3_CTRL_MODE_SLEEP
 
- TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT
 
- TPS65917_LDO3_CTRL_STATUS
 
- TPS65917_LDO3_CTRL_STATUS_SHIFT
 
- TPS65917_LDO3_CTRL_WR_S
 
- TPS65917_LDO3_CTRL_WR_S_SHIFT
 
- TPS65917_LDO3_VOLTAGE
 
- TPS65917_LDO3_VOLTAGE_VSEL_MASK
 
- TPS65917_LDO3_VOLTAGE_VSEL_SHIFT
 
- TPS65917_LDO4_CTRL
 
- TPS65917_LDO4_CTRL_MODE_ACTIVE
 
- TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT
 
- TPS65917_LDO4_CTRL_MODE_SLEEP
 
- TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT
 
- TPS65917_LDO4_CTRL_STATUS
 
- TPS65917_LDO4_CTRL_STATUS_SHIFT
 
- TPS65917_LDO4_CTRL_WR_S
 
- TPS65917_LDO4_CTRL_WR_S_SHIFT
 
- TPS65917_LDO4_VOLTAGE
 
- TPS65917_LDO4_VOLTAGE_VSEL_MASK
 
- TPS65917_LDO4_VOLTAGE_VSEL_SHIFT
 
- TPS65917_LDO5_CTRL
 
- TPS65917_LDO5_CTRL_MODE_ACTIVE
 
- TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT
 
- TPS65917_LDO5_CTRL_MODE_SLEEP
 
- TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT
 
- TPS65917_LDO5_CTRL_STATUS
 
- TPS65917_LDO5_CTRL_STATUS_SHIFT
 
- TPS65917_LDO5_CTRL_WR_S
 
- TPS65917_LDO5_CTRL_WR_S_SHIFT
 
- TPS65917_LDO5_VOLTAGE
 
- TPS65917_LDO5_VOLTAGE_VSEL_MASK
 
- TPS65917_LDO5_VOLTAGE_VSEL_SHIFT
 
- TPS65917_LDO_PD_CTRL1
 
- TPS65917_LDO_PD_CTRL1_LDO1
 
- TPS65917_LDO_PD_CTRL1_LDO1_SHIFT
 
- TPS65917_LDO_PD_CTRL1_LDO2
 
- TPS65917_LDO_PD_CTRL1_LDO2_SHIFT
 
- TPS65917_LDO_PD_CTRL1_LDO4
 
- TPS65917_LDO_PD_CTRL1_LDO4_SHIFT
 
- TPS65917_LDO_PD_CTRL2
 
- TPS65917_LDO_PD_CTRL2_LDO3
 
- TPS65917_LDO_PD_CTRL2_LDO3_SHIFT
 
- TPS65917_LDO_PD_CTRL2_LDO5
 
- TPS65917_LDO_PD_CTRL2_LDO5_SHIFT
 
- TPS65917_LDO_PD_CTRL2_LDOVANA
 
- TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT
 
- TPS65917_LDO_PD_CTRL3
 
- TPS65917_LDO_SHORT_STATUS1
 
- TPS65917_LDO_SHORT_STATUS1_LDO1
 
- TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT
 
- TPS65917_LDO_SHORT_STATUS1_LDO2
 
- TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT
 
- TPS65917_LDO_SHORT_STATUS1_LDO4
 
- TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT
 
- TPS65917_LDO_SHORT_STATUS2
 
- TPS65917_LDO_SHORT_STATUS2_LDO3
 
- TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT
 
- TPS65917_LDO_SHORT_STATUS2_LDO5
 
- TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT
 
- TPS65917_LDO_SHORT_STATUS2_LDOVANA
 
- TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT
 
- TPS65917_LDO_SHORT_STATUS3
 
- TPS65917_LONG_PRESS_KEY_IRQ
 
- TPS65917_NSLEEP_LDO_ASSIGN1
 
- TPS65917_NSLEEP_LDO_ASSIGN1_LDO1
 
- TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT
 
- TPS65917_NSLEEP_LDO_ASSIGN1_LDO2
 
- TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT
 
- TPS65917_NSLEEP_LDO_ASSIGN1_LDO4
 
- TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT
 
- TPS65917_NSLEEP_LDO_ASSIGN2
 
- TPS65917_NSLEEP_LDO_ASSIGN2_LDO3
 
- TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT
 
- TPS65917_NSLEEP_LDO_ASSIGN2_LDO5
 
- TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT
 
- TPS65917_NSLEEP_RES_ASSIGN
 
- TPS65917_NSLEEP_RES_ASSIGN_PLL_EN
 
- TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT
 
- TPS65917_NSLEEP_RES_ASSIGN_REGEN1
 
- TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT
 
- TPS65917_NSLEEP_RES_ASSIGN_REGEN2
 
- TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT
 
- TPS65917_NSLEEP_RES_ASSIGN_REGEN3
 
- TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT
 
- TPS65917_NSLEEP_SMPS_ASSIGN
 
- TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1
 
- TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT
 
- TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2
 
- TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT
 
- TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3
 
- TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT
 
- TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4
 
- TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT
 
- TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5
 
- TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT
 
- TPS65917_NUM_IRQ
 
- TPS65917_NUM_REGS
 
- TPS65917_OTP_ERROR_IRQ
 
- TPS65917_PLLEN_CTRL
 
- TPS65917_PLLEN_CTRL_MODE_ACTIVE
 
- TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT
 
- TPS65917_PLLEN_CTRL_MODE_SLEEP
 
- TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT
 
- TPS65917_PLLEN_CTRL_STATUS
 
- TPS65917_PLLEN_CTRL_STATUS_SHIFT
 
- TPS65917_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK
 
- TPS65917_PWRDOWN_IRQ
 
- TPS65917_PWRON_IRQ
 
- TPS65917_REGEN1_CTRL
 
- TPS65917_REGEN1_CTRL_MODE_ACTIVE
 
- TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT
 
- TPS65917_REGEN1_CTRL_MODE_SLEEP
 
- TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT
 
- TPS65917_REGEN1_CTRL_STATUS
 
- TPS65917_REGEN1_CTRL_STATUS_SHIFT
 
- TPS65917_REGEN2_CTRL
 
- TPS65917_REGEN2_CTRL_MODE_ACTIVE
 
- TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT
 
- TPS65917_REGEN2_CTRL_MODE_SLEEP
 
- TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT
 
- TPS65917_REGEN2_CTRL_STATUS
 
- TPS65917_REGEN2_CTRL_STATUS_SHIFT
 
- TPS65917_REGEN3_CTRL
 
- TPS65917_REGEN3_CTRL_MODE_ACTIVE
 
- TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT
 
- TPS65917_REGEN3_CTRL_MODE_SLEEP
 
- TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT
 
- TPS65917_REGEN3_CTRL_STATUS
 
- TPS65917_REGEN3_CTRL_STATUS_SHIFT
 
- TPS65917_REG_LDO1
 
- TPS65917_REG_LDO2
 
- TPS65917_REG_LDO3
 
- TPS65917_REG_LDO4
 
- TPS65917_REG_LDO5
 
- TPS65917_REG_REGEN1
 
- TPS65917_REG_REGEN2
 
- TPS65917_REG_REGEN3
 
- TPS65917_REG_SMPS1
 
- TPS65917_REG_SMPS12
 
- TPS65917_REG_SMPS2
 
- TPS65917_REG_SMPS3
 
- TPS65917_REG_SMPS4
 
- TPS65917_REG_SMPS5
 
- TPS65917_RESERVED
 
- TPS65917_RESERVED1
 
- TPS65917_RESERVED10
 
- TPS65917_RESERVED2
 
- TPS65917_RESERVED3
 
- TPS65917_RESERVED4
 
- TPS65917_RESERVED5
 
- TPS65917_RESERVED6
 
- TPS65917_RESERVED7
 
- TPS65917_RESERVED8
 
- TPS65917_RESERVED9
 
- TPS65917_RESET_IN_IRQ
 
- TPS65917_RESREVED6
 
- TPS65917_SHORT_IRQ
 
- TPS65917_SMPS1_CTRL
 
- TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK
 
- TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT
 
- TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK
 
- TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT
 
- TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN
 
- TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT
 
- TPS65917_SMPS1_CTRL_STATUS_MASK
 
- TPS65917_SMPS1_CTRL_STATUS_SHIFT
 
- TPS65917_SMPS1_CTRL_WR_S
 
- TPS65917_SMPS1_CTRL_WR_S_SHIFT
 
- TPS65917_SMPS1_FORCE
 
- TPS65917_SMPS1_FORCE_CMD
 
- TPS65917_SMPS1_FORCE_CMD_SHIFT
 
- TPS65917_SMPS1_FORCE_VSEL_MASK
 
- TPS65917_SMPS1_FORCE_VSEL_SHIFT
 
- TPS65917_SMPS1_VOLTAGE
 
- TPS65917_SMPS1_VOLTAGE_RANGE
 
- TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT
 
- TPS65917_SMPS1_VOLTAGE_VSEL_MASK
 
- TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT
 
- TPS65917_SMPS2_CTRL
 
- TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK
 
- TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT
 
- TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK
 
- TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT
 
- TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN
 
- TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT
 
- TPS65917_SMPS2_CTRL_STATUS_MASK
 
- TPS65917_SMPS2_CTRL_STATUS_SHIFT
 
- TPS65917_SMPS2_CTRL_WR_S
 
- TPS65917_SMPS2_CTRL_WR_S_SHIFT
 
- TPS65917_SMPS2_FORCE
 
- TPS65917_SMPS2_FORCE_CMD
 
- TPS65917_SMPS2_FORCE_CMD_SHIFT
 
- TPS65917_SMPS2_FORCE_VSEL_MASK
 
- TPS65917_SMPS2_FORCE_VSEL_SHIFT
 
- TPS65917_SMPS2_VOLTAGE
 
- TPS65917_SMPS2_VOLTAGE_RANGE
 
- TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT
 
- TPS65917_SMPS2_VOLTAGE_VSEL_MASK
 
- TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT
 
- TPS65917_SMPS3_CTRL
 
- TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK
 
- TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT
 
- TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK
 
- TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT
 
- TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN
 
- TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT
 
- TPS65917_SMPS3_CTRL_STATUS_MASK
 
- TPS65917_SMPS3_CTRL_STATUS_SHIFT
 
- TPS65917_SMPS3_CTRL_WR_S
 
- TPS65917_SMPS3_CTRL_WR_S_SHIFT
 
- TPS65917_SMPS3_FORCE
 
- TPS65917_SMPS3_FORCE_CMD
 
- TPS65917_SMPS3_FORCE_CMD_SHIFT
 
- TPS65917_SMPS3_FORCE_VSEL_MASK
 
- TPS65917_SMPS3_FORCE_VSEL_SHIFT
 
- TPS65917_SMPS3_VOLTAGE
 
- TPS65917_SMPS3_VOLTAGE_RANGE
 
- TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT
 
- TPS65917_SMPS3_VOLTAGE_VSEL_MASK
 
- TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT
 
- TPS65917_SMPS4_CTRL
 
- TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK
 
- TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT
 
- TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK
 
- TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT
 
- TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN
 
- TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT
 
- TPS65917_SMPS4_CTRL_STATUS_MASK
 
- TPS65917_SMPS4_CTRL_STATUS_SHIFT
 
- TPS65917_SMPS4_CTRL_WR_S
 
- TPS65917_SMPS4_CTRL_WR_S_SHIFT
 
- TPS65917_SMPS4_VOLTAGE
 
- TPS65917_SMPS4_VOLTAGE_RANGE
 
- TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT
 
- TPS65917_SMPS4_VOLTAGE_VSEL_MASK
 
- TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT
 
- TPS65917_SMPS5_CTRL
 
- TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK
 
- TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT
 
- TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK
 
- TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT
 
- TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN
 
- TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT
 
- TPS65917_SMPS5_CTRL_STATUS_MASK
 
- TPS65917_SMPS5_CTRL_STATUS_SHIFT
 
- TPS65917_SMPS5_CTRL_WR_S
 
- TPS65917_SMPS5_CTRL_WR_S_SHIFT
 
- TPS65917_SMPS5_VOLTAGE
 
- TPS65917_SMPS5_VOLTAGE_RANGE
 
- TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT
 
- TPS65917_SMPS5_VOLTAGE_VSEL_MASK
 
- TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT
 
- TPS65917_SMPS_CTRL
 
- TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL
 
- TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT
 
- TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN
 
- TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT
 
- TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN
 
- TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1
 
- TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT
 
- TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2
 
- TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT
 
- TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3
 
- TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT
 
- TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4
 
- TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT
 
- TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5
 
- TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT
 
- TPS65917_SMPS_PD_CTRL
 
- TPS65917_SMPS_PD_CTRL_SMPS1
 
- TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT
 
- TPS65917_SMPS_PD_CTRL_SMPS2
 
- TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT
 
- TPS65917_SMPS_PD_CTRL_SMPS3
 
- TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT
 
- TPS65917_SMPS_PD_CTRL_SMPS4
 
- TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT
 
- TPS65917_SMPS_PD_CTRL_SMPS5
 
- TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT
 
- TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT
 
- TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK
 
- TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT
 
- TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS
 
- TPS65917_SMPS_POWERGOOD_MASK1
 
- TPS65917_SMPS_POWERGOOD_MASK1_SMPS1
 
- TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT
 
- TPS65917_SMPS_POWERGOOD_MASK1_SMPS2
 
- TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT
 
- TPS65917_SMPS_POWERGOOD_MASK1_SMPS3
 
- TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT
 
- TPS65917_SMPS_POWERGOOD_MASK1_SMPS4
 
- TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT
 
- TPS65917_SMPS_POWERGOOD_MASK1_SMPS5
 
- TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT
 
- TPS65917_SMPS_POWERGOOD_MASK2
 
- TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM
 
- TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT
 
- TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT
 
- TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT
 
- TPS65917_SMPS_SHORT_STATUS
 
- TPS65917_SMPS_SHORT_STATUS_SMPS1
 
- TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT
 
- TPS65917_SMPS_SHORT_STATUS_SMPS2
 
- TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT
 
- TPS65917_SMPS_SHORT_STATUS_SMPS3
 
- TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT
 
- TPS65917_SMPS_SHORT_STATUS_SMPS4
 
- TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT
 
- TPS65917_SMPS_SHORT_STATUS_SMPS5
 
- TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT
 
- TPS65917_SMPS_THERMAL_EN
 
- TPS65917_SMPS_THERMAL_EN_SMPS12
 
- TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT
 
- TPS65917_SMPS_THERMAL_EN_SMPS3
 
- TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT
 
- TPS65917_SMPS_THERMAL_EN_SMPS5
 
- TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT
 
- TPS65917_SMPS_THERMAL_STATUS
 
- TPS65917_SMPS_THERMAL_STATUS_SMPS12
 
- TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT
 
- TPS65917_SMPS_THERMAL_STATUS_SMPS3
 
- TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT
 
- TPS65917_SMPS_THERMAL_STATUS_SMPS5
 
- TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT
 
- TPS65917_VBUS_IRQ
 
- TPS65917_VSYS_MON_IRQ
 
- TPS65917_WDT_IRQ
 
- TPS6591X_MAX_NUM_GPIO
 
- TPS6591X_MAX_REGISTER
 
- TPS68470_CLKCFG1_MODE_A_MASK
 
- TPS68470_CLKCFG1_MODE_B_MASK
 
- TPS68470_GPIO_CTL_REG_A
 
- TPS68470_GPIO_CTL_REG_B
 
- TPS68470_GPIO_MODE_IN
 
- TPS68470_GPIO_MODE_IN_PULLUP
 
- TPS68470_GPIO_MODE_MASK
 
- TPS68470_GPIO_MODE_OUT_CMOS
 
- TPS68470_GPIO_MODE_OUT_ODRAIN
 
- TPS68470_N_GPIO
 
- TPS68470_N_LOGIC_OUTPUT
 
- TPS68470_N_REGULAR_GPIO
 
- TPS68470_PLL_EN_MASK
 
- TPS68470_REG_BOOSTDIV
 
- TPS68470_REG_BUCKDIV
 
- TPS68470_REG_CLKCFG1
 
- TPS68470_REG_CLKCFG2
 
- TPS68470_REG_GPCTL0A
 
- TPS68470_REG_GPCTL0B
 
- TPS68470_REG_GPCTL1A
 
- TPS68470_REG_GPCTL1B
 
- TPS68470_REG_GPCTL2A
 
- TPS68470_REG_GPCTL2B
 
- TPS68470_REG_GPCTL3A
 
- TPS68470_REG_GPCTL3B
 
- TPS68470_REG_GPCTL4A
 
- TPS68470_REG_GPCTL4B
 
- TPS68470_REG_GPCTL5A
 
- TPS68470_REG_GPCTL5B
 
- TPS68470_REG_GPCTL6A
 
- TPS68470_REG_GPCTL6B
 
- TPS68470_REG_GPDI
 
- TPS68470_REG_GPDO
 
- TPS68470_REG_MAX
 
- TPS68470_REG_PLLCTL
 
- TPS68470_REG_PLLCTL2
 
- TPS68470_REG_PLLDIV
 
- TPS68470_REG_PLLSWR
 
- TPS68470_REG_POSTDIV
 
- TPS68470_REG_POSTDIV2
 
- TPS68470_REG_RESET
 
- TPS68470_REG_RESET_MASK
 
- TPS68470_REG_REVID
 
- TPS68470_REG_SGPO
 
- TPS68470_REG_S_I2C_CTL
 
- TPS68470_REG_VACTL
 
- TPS68470_REG_VAUX1CTL
 
- TPS68470_REG_VAUX1VAL
 
- TPS68470_REG_VAUX2CTL
 
- TPS68470_REG_VAUX2VAL
 
- TPS68470_REG_VAVAL
 
- TPS68470_REG_VCMCTL
 
- TPS68470_REG_VCMVAL
 
- TPS68470_REG_VDCTL
 
- TPS68470_REG_VDVAL
 
- TPS68470_REG_VIOVAL
 
- TPS68470_REG_VSIOVAL
 
- TPS68470_REG_XTALDIV
 
- TPS68470_S_I2C_CTL_EN_MASK
 
- TPS68470_VACTL_EN_MASK
 
- TPS68470_VAUX1CTL_EN_MASK
 
- TPS68470_VAUX1VAL_AUX1VOLT_MASK
 
- TPS68470_VAUX2CTL_EN_MASK
 
- TPS68470_VAUX2VAL_AUX2VOLT_MASK
 
- TPS68470_VAVAL_AVOLT_MASK
 
- TPS68470_VCMCTL_EN_MASK
 
- TPS68470_VCMVAL_VCVOLT_MASK
 
- TPS68470_VDCTL_EN_MASK
 
- TPS68470_VDVAL_DVOLT_MASK
 
- TPS68470_VIOVAL_IOVOLT_MASK
 
- TPS68470_VSIOVAL_IOVOLT_MASK
 
- TPS80031
 
- TPS80031_ALARM_DAYS_REG
 
- TPS80031_ALARM_HOURS_REG
 
- TPS80031_ALARM_MINUTES_REG
 
- TPS80031_ALARM_MONTHS_REG
 
- TPS80031_ALARM_SECONDS_REG
 
- TPS80031_ALARM_YEARS_REG
 
- TPS80031_BACKUP_REG
 
- TPS80031_BATDEBOUNCING
 
- TPS80031_BBSPOR_CFG
 
- TPS80031_BBSPOR_CHG_EN
 
- TPS80031_BIAS_CFG_STATE
 
- TPS80031_BIAS_CFG_TRANS
 
- TPS80031_BROADCAST_ADDR_ALL
 
- TPS80031_BROADCAST_ADDR_CLK_RST
 
- TPS80031_BROADCAST_ADDR_PROV
 
- TPS80031_BROADCAST_ADDR_REF
 
- TPS80031_CFG_INPUT_PUPD1
 
- TPS80031_CFG_INPUT_PUPD2
 
- TPS80031_CFG_INPUT_PUPD3
 
- TPS80031_CFG_INPUT_PUPD4
 
- TPS80031_CFG_LDO_PD1
 
- TPS80031_CFG_LDO_PD2
 
- TPS80031_CFG_SMPS_PD
 
- TPS80031_CHARGERUSB_CINLIMIT
 
- TPS80031_CHARGERUSB_CTRL1
 
- TPS80031_CHARGERUSB_CTRL2
 
- TPS80031_CHARGERUSB_CTRL3
 
- TPS80031_CHARGERUSB_CTRLLIMIT1
 
- TPS80031_CHARGERUSB_CTRLLIMIT2
 
- TPS80031_CHARGERUSB_INT_MASK
 
- TPS80031_CHARGERUSB_INT_STATUS
 
- TPS80031_CHARGERUSB_STAT1
 
- TPS80031_CHARGERUSB_STATUS_INT1
 
- TPS80031_CHARGERUSB_STATUS_INT2
 
- TPS80031_CHARGERUSB_VICHRG
 
- TPS80031_CHARGERUSB_VICHRG_PC
 
- TPS80031_CHARGERUSB_VOREG
 
- TPS80031_CHARGERUSB_VSYSREG
 
- TPS80031_CHARGE_CONTROL_SUB_INT_MASK
 
- TPS80031_CHRG_EXT_CHRG_STATZ
 
- TPS80031_CLK32KAO_CFG_STATE
 
- TPS80031_CLK32KAO_CFG_TRANS
 
- TPS80031_CLK32KAUDIO_CFG_STATE
 
- TPS80031_CLK32KAUDIO_CFG_TRANS
 
- TPS80031_CLK32KG_CFG_STATE
 
- TPS80031_CLK32KG_CFG_TRANS
 
- TPS80031_CONTROLLER_CTRL1
 
- TPS80031_CONTROLLER_CTRL2
 
- TPS80031_CONTROLLER_INT_MASK
 
- TPS80031_CONTROLLER_INT_MASK_MBAT_REMOVED
 
- TPS80031_CONTROLLER_INT_MASK_MBAT_TEMP
 
- TPS80031_CONTROLLER_INT_MASK_MFAULT_WDG
 
- TPS80031_CONTROLLER_INT_MASK_MLINCH_GATED
 
- TPS80031_CONTROLLER_INT_MASK_MVAC_DET
 
- TPS80031_CONTROLLER_INT_MASK_MVBUS_DET
 
- TPS80031_CONTROLLER_STAT1
 
- TPS80031_CONTROLLER_STAT1_BAT_REMOVED
 
- TPS80031_CONTROLLER_STAT1_BAT_TEMP
 
- TPS80031_CONTROLLER_STAT1_FAULT_WDG
 
- TPS80031_CONTROLLER_STAT1_LINCH_GATED
 
- TPS80031_CONTROLLER_STAT1_VAC_DET
 
- TPS80031_CONTROLLER_STAT1_VBUS_DET
 
- TPS80031_CONTROLLER_VSEL_COMP
 
- TPS80031_CONTROLLER_WDG
 
- TPS80031_CTLI2C_SCL
 
- TPS80031_CTLI2C_SDA
 
- TPS80031_CTRL_P1
 
- TPS80031_DAYS_REG
 
- TPS80031_DEVOFF
 
- TPS80031_DVSI2C_SCL
 
- TPS80031_DVSI2C_SDA
 
- TPS80031_EPROM_REV
 
- TPS80031_EXT_CONTROL_CFG_STATE
 
- TPS80031_EXT_CONTROL_CFG_TRANS
 
- TPS80031_EXT_PWR_REQ
 
- TPS80031_FG_REG_00
 
- TPS80031_FG_REG_01
 
- TPS80031_FG_REG_02
 
- TPS80031_FG_REG_03
 
- TPS80031_FG_REG_04
 
- TPS80031_FG_REG_05
 
- TPS80031_FG_REG_06
 
- TPS80031_FG_REG_07
 
- TPS80031_FG_REG_08
 
- TPS80031_FG_REG_09
 
- TPS80031_FG_REG_10
 
- TPS80031_FG_REG_11
 
- TPS80031_GPADC_CTRL
 
- TPS80031_GPADC_CTRL2
 
- TPS80031_GPADC_START
 
- TPS80031_GPADC_TRIM0
 
- TPS80031_GPADC_TRIM1
 
- TPS80031_GPADC_TRIM10
 
- TPS80031_GPADC_TRIM11
 
- TPS80031_GPADC_TRIM12
 
- TPS80031_GPADC_TRIM13
 
- TPS80031_GPADC_TRIM14
 
- TPS80031_GPADC_TRIM15
 
- TPS80031_GPADC_TRIM16
 
- TPS80031_GPADC_TRIM17
 
- TPS80031_GPADC_TRIM18
 
- TPS80031_GPADC_TRIM2
 
- TPS80031_GPADC_TRIM3
 
- TPS80031_GPADC_TRIM4
 
- TPS80031_GPADC_TRIM5
 
- TPS80031_GPADC_TRIM6
 
- TPS80031_GPADC_TRIM7
 
- TPS80031_GPADC_TRIM8
 
- TPS80031_GPADC_TRIM9
 
- TPS80031_GPCH0_LSB
 
- TPS80031_GPCH0_MSB
 
- TPS80031_GPSELECT_ISB
 
- TPS80031_HOURS_REG
 
- TPS80031_I2C_ID0_ADDR
 
- TPS80031_I2C_ID1_ADDR
 
- TPS80031_I2C_ID2_ADDR
 
- TPS80031_I2C_ID3_ADDR
 
- TPS80031_INT_BAT
 
- TPS80031_INT_BAT_REMOVED
 
- TPS80031_INT_BAT_TEMP_OVRANGE
 
- TPS80031_INT_CC_AUTOCAL
 
- TPS80031_INT_CHRG_CTRL
 
- TPS80031_INT_EXT_CHRG
 
- TPS80031_INT_FAULT_WDG
 
- TPS80031_INT_GPADC_RT
 
- TPS80031_INT_GPADC_SW2_EOC
 
- TPS80031_INT_HOT_DIE
 
- TPS80031_INT_ID
 
- TPS80031_INT_ID_WKUP
 
- TPS80031_INT_INT_CHRG
 
- TPS80031_INT_LINCH_GATED
 
- TPS80031_INT_MMC
 
- TPS80031_INT_MSK_LINE_A
 
- TPS80031_INT_MSK_LINE_B
 
- TPS80031_INT_MSK_LINE_C
 
- TPS80031_INT_MSK_STS_A
 
- TPS80031_INT_MSK_STS_B
 
- TPS80031_INT_MSK_STS_C
 
- TPS80031_INT_NR
 
- TPS80031_INT_PWRON
 
- TPS80031_INT_RES
 
- TPS80031_INT_RES2
 
- TPS80031_INT_RPWRON
 
- TPS80031_INT_RTC_ALARM
 
- TPS80031_INT_RTC_PERIOD
 
- TPS80031_INT_SIM
 
- TPS80031_INT_SPDURATION
 
- TPS80031_INT_STS_A
 
- TPS80031_INT_STS_B
 
- TPS80031_INT_STS_C
 
- TPS80031_INT_SYS_VLOW
 
- TPS80031_INT_VAC_DET
 
- TPS80031_INT_VBUS
 
- TPS80031_INT_VBUSS_WKUP
 
- TPS80031_INT_VBUS_DET
 
- TPS80031_INT_VXX_SHORT
 
- TPS80031_INT_WATCHDOG
 
- TPS80031_IRQ
 
- TPS80031_JTAGVERNUM
 
- TPS80031_KEY_PRESS_DUR_CFG
 
- TPS80031_LDO1_CFG_STATE
 
- TPS80031_LDO1_CFG_TRANS
 
- TPS80031_LDO1_CFG_VOLTAGE
 
- TPS80031_LDO2_CFG_STATE
 
- TPS80031_LDO2_CFG_TRANS
 
- TPS80031_LDO2_CFG_VOLTAGE
 
- TPS80031_LDO3_CFG_STATE
 
- TPS80031_LDO3_CFG_TRANS
 
- TPS80031_LDO3_CFG_VOLTAGE
 
- TPS80031_LDO3_OUTPUT_VIB
 
- TPS80031_LDO4_CFG_STATE
 
- TPS80031_LDO4_CFG_TRANS
 
- TPS80031_LDO4_CFG_VOLTAGE
 
- TPS80031_LDO5_CFG_STATE
 
- TPS80031_LDO5_CFG_TRANS
 
- TPS80031_LDO5_CFG_VOLTAGE
 
- TPS80031_LDO6_CFG_STATE
 
- TPS80031_LDO6_CFG_TRANS
 
- TPS80031_LDO6_CFG_VOLTAGE
 
- TPS80031_LDO7_CFG_STATE
 
- TPS80031_LDO7_CFG_TRANS
 
- TPS80031_LDO7_CFG_VOLTAGE
 
- TPS80031_LDOLN_CFG_STATE
 
- TPS80031_LDOLN_CFG_TRANS
 
- TPS80031_LDOLN_CFG_VOLTAGE
 
- TPS80031_LDOUSB_CFG_STATE
 
- TPS80031_LDOUSB_CFG_TRANS
 
- TPS80031_LDOUSB_CFG_VOLTAGE
 
- TPS80031_LED_PWM_CTRL1
 
- TPS80031_LED_PWM_CTRL2
 
- TPS80031_LINEAR_CHRG_STS
 
- TPS80031_MAX_REGISTER
 
- TPS80031_MINUTES_REG
 
- TPS80031_MISC1
 
- TPS80031_MISC2
 
- TPS80031_MMC
 
- TPS80031_MMCCTRL
 
- TPS80031_MMCDEBOUNCING
 
- TPS80031_MONTHS_REG
 
- TPS80031_NRESPWRON_CFG_STATE
 
- TPS80031_NRESPWRON_CFG_TRANS
 
- TPS80031_NRES_WARM
 
- TPS80031_NUM_SLAVES
 
- TPS80031_PHOENIX_DEV_ON
 
- TPS80031_PHOENIX_LAST_TURNOFF_STS
 
- TPS80031_PHOENIX_MSK_TRANSITION
 
- TPS80031_PHOENIX_SENS_TRANSITION
 
- TPS80031_PHOENIX_SEQ_CFG
 
- TPS80031_PHOENIX_START_CONDITION
 
- TPS80031_PH_CFG_VSYSLOW
 
- TPS80031_PH_STS_BOOT
 
- TPS80031_PREQ1
 
- TPS80031_PREQ1_RES_ASS_A
 
- TPS80031_PREQ1_RES_ASS_B
 
- TPS80031_PREQ1_RES_ASS_C
 
- TPS80031_PREQ2A
 
- TPS80031_PREQ2B
 
- TPS80031_PREQ2C
 
- TPS80031_PREQ2_RES_ASS_A
 
- TPS80031_PREQ2_RES_ASS_B
 
- TPS80031_PREQ2_RES_ASS_C
 
- TPS80031_PREQ3
 
- TPS80031_PREQ3_RES_ASS_A
 
- TPS80031_PREQ3_RES_ASS_B
 
- TPS80031_PREQ3_RES_ASS_C
 
- TPS80031_PRIMARY_WATCHDOG_CFG
 
- TPS80031_PUPD_NORMAL
 
- TPS80031_PUPD_PULLDOWN
 
- TPS80031_PUPD_PULLUP
 
- TPS80031_PWDNSTATUS1
 
- TPS80031_PWDNSTATUS2
 
- TPS80031_PWM1OFF
 
- TPS80031_PWM1ON
 
- TPS80031_PWM2OFF
 
- TPS80031_PWM2ON
 
- TPS80031_PWM_FORCE
 
- TPS80031_PWR_OFF_ON_SLEEP
 
- TPS80031_PWR_ON_ON_SLEEP
 
- TPS80031_PWR_REQ_INPUT_NONE
 
- TPS80031_PWR_REQ_INPUT_PREQ1
 
- TPS80031_PWR_REQ_INPUT_PREQ2
 
- TPS80031_PWR_REQ_INPUT_PREQ3
 
- TPS80031_RC6MHZ_CFG_STATE
 
- TPS80031_RC6MHZ_CFG_TRANS
 
- TPS80031_REGEN1_CFG_STATE
 
- TPS80031_REGEN1_CFG_TRANS
 
- TPS80031_REGEN2_CFG_STATE
 
- TPS80031_REGEN2_CFG_TRANS
 
- TPS80031_REGULATOR_LDO1
 
- TPS80031_REGULATOR_LDO2
 
- TPS80031_REGULATOR_LDO3
 
- TPS80031_REGULATOR_LDO4
 
- TPS80031_REGULATOR_LDO5
 
- TPS80031_REGULATOR_LDO6
 
- TPS80031_REGULATOR_LDO7
 
- TPS80031_REGULATOR_LDOLN
 
- TPS80031_REGULATOR_LDOUSB
 
- TPS80031_REGULATOR_MAX
 
- TPS80031_REGULATOR_REGEN1
 
- TPS80031_REGULATOR_REGEN2
 
- TPS80031_REGULATOR_SMPS1
 
- TPS80031_REGULATOR_SMPS2
 
- TPS80031_REGULATOR_SMPS3
 
- TPS80031_REGULATOR_SMPS4
 
- TPS80031_REGULATOR_SYSEN
 
- TPS80031_REGULATOR_VANA
 
- TPS80031_REGULATOR_VBUS
 
- TPS80031_REGULATOR_VIO
 
- TPS80031_REG_FIXED
 
- TPS80031_REG_LDO
 
- TPS80031_REG_SMPS
 
- TPS80031_RTCH0_LSB
 
- TPS80031_RTCH0_MSB
 
- TPS80031_RTCH1_LSB
 
- TPS80031_RTCH1_MSB
 
- TPS80031_RTC_ALARM_NUM_REGS
 
- TPS80031_RTC_COMP_LSB_REG
 
- TPS80031_RTC_COMP_MSB_REG
 
- TPS80031_RTC_CTRL_REG
 
- TPS80031_RTC_INTERRUPTS_REG
 
- TPS80031_RTC_POR_DAY
 
- TPS80031_RTC_POR_MONTH
 
- TPS80031_RTC_POR_YEAR
 
- TPS80031_RTC_RESET_STATUS_REG
 
- TPS80031_RTC_STATUS_REG
 
- TPS80031_RTC_TIME_NUM_REGS
 
- TPS80031_RTSELECT_ISB
 
- TPS80031_RTSELECT_LSB
 
- TPS80031_RTSELECT_MSB
 
- TPS80031_SECONDS_REG
 
- TPS80031_SIM
 
- TPS80031_SIMCTRL
 
- TPS80031_SIMDEBOUNCING
 
- TPS80031_SLAVE_ID0
 
- TPS80031_SLAVE_ID1
 
- TPS80031_SLAVE_ID2
 
- TPS80031_SLAVE_ID3
 
- TPS80031_SMPS1_CFG_FORCE
 
- TPS80031_SMPS1_CFG_STATE
 
- TPS80031_SMPS1_CFG_STEP
 
- TPS80031_SMPS1_CFG_TRANS
 
- TPS80031_SMPS1_CFG_VOLTAGE
 
- TPS80031_SMPS2_CFG_FORCE
 
- TPS80031_SMPS2_CFG_STATE
 
- TPS80031_SMPS2_CFG_STEP
 
- TPS80031_SMPS2_CFG_TRANS
 
- TPS80031_SMPS2_CFG_VOLTAGE
 
- TPS80031_SMPS3_CFG_FORCE
 
- TPS80031_SMPS3_CFG_STATE
 
- TPS80031_SMPS3_CFG_TRANS
 
- TPS80031_SMPS3_CFG_VOLTAGE
 
- TPS80031_SMPS4_CFG_FORCE
 
- TPS80031_SMPS4_CFG_STATE
 
- TPS80031_SMPS4_CFG_TRANS
 
- TPS80031_SMPS4_CFG_VOLTAGE
 
- TPS80031_SMPS_LDO_SHORT_STS
 
- TPS80031_SMPS_MULT
 
- TPS80031_SMPS_OFFSET
 
- TPS80031_STATE_MASK
 
- TPS80031_STATE_OFF
 
- TPS80031_STATE_ON
 
- TPS80031_STS_HW_CONDITIONS
 
- TPS80031_STS_PWR_GRP_STATE
 
- TPS80031_SYSEN_CFG_STATE
 
- TPS80031_SYSEN_CFG_TRANS
 
- TPS80031_TMP_CFG
 
- TPS80031_TMP_CFG_STATE
 
- TPS80031_TMP_CFG_TRANS
 
- TPS80031_TOGGLE1
 
- TPS80031_TOGGLE2
 
- TPS80031_TOGGLE3
 
- TPS80031_TRANS_ACTIVE_MASK
 
- TPS80031_TRANS_ACTIVE_OFF
 
- TPS80031_TRANS_ACTIVE_ON
 
- TPS80031_TRANS_OFF_ACTIVE
 
- TPS80031_TRANS_OFF_MASK
 
- TPS80031_TRANS_OFF_OFF
 
- TPS80031_TRANS_SLEEP_MASK
 
- TPS80031_TRANS_SLEEP_OFF
 
- TPS80031_TRANS_SLEEP_ON
 
- TPS80031_USBLDO_INPUT_PMID
 
- TPS80031_USBLDO_INPUT_VSYS
 
- TPS80031_USB_ID_CTRL_CLR
 
- TPS80031_USB_ID_CTRL_SET
 
- TPS80031_USB_ID_INT_EN_HI_CLR
 
- TPS80031_USB_ID_INT_EN_HI_SET
 
- TPS80031_USB_ID_INT_EN_LO_CLR
 
- TPS80031_USB_ID_INT_EN_LO_SET
 
- TPS80031_USB_ID_INT_LATCH_CLR
 
- TPS80031_USB_ID_INT_LATCH_SET
 
- TPS80031_USB_ID_INT_SRC
 
- TPS80031_USB_OTG_ADP_CTRL
 
- TPS80031_USB_OTG_ADP_HIGH
 
- TPS80031_USB_OTG_ADP_LOW
 
- TPS80031_USB_OTG_ADP_RISE
 
- TPS80031_USB_OTG_REVISION
 
- TPS80031_USB_PRODUCT_ID_LSB
 
- TPS80031_USB_PRODUCT_ID_MSB
 
- TPS80031_USB_VBUS_CTRL_CLR
 
- TPS80031_USB_VBUS_CTRL_SET
 
- TPS80031_USB_VBUS_INT_EN_HI_CLR
 
- TPS80031_USB_VBUS_INT_EN_HI_SET
 
- TPS80031_USB_VBUS_INT_EN_LO_CLR
 
- TPS80031_USB_VBUS_INT_EN_LO_SET
 
- TPS80031_USB_VBUS_INT_LATCH_CLR
 
- TPS80031_USB_VBUS_INT_LATCH_SET
 
- TPS80031_USB_VBUS_INT_SRC
 
- TPS80031_USB_VENDOR_ID_LSB
 
- TPS80031_USB_VENDOR_ID_MSB
 
- TPS80031_VALIDITY0
 
- TPS80031_VALIDITY1
 
- TPS80031_VALIDITY2
 
- TPS80031_VALIDITY3
 
- TPS80031_VALIDITY4
 
- TPS80031_VALIDITY5
 
- TPS80031_VALIDITY6
 
- TPS80031_VALIDITY7
 
- TPS80031_VANA_CFG_STATE
 
- TPS80031_VANA_CFG_TRANS
 
- TPS80031_VANA_CFG_VOLTAGE
 
- TPS80031_VBUS_CFG_STATE
 
- TPS80031_VBUS_CFG_TRANS
 
- TPS80031_VBUS_DISCHRG_EN_PDN
 
- TPS80031_VBUS_SW_N_ID
 
- TPS80031_VBUS_SW_ONLY
 
- TPS80031_VIBCTRL
 
- TPS80031_VIBMODE
 
- TPS80031_VIO_CFG_FORCE
 
- TPS80031_VIO_CFG_STATE
 
- TPS80031_VIO_CFG_STEP
 
- TPS80031_VIO_CFG_TRANS
 
- TPS80031_VIO_CFG_VOLTAGE
 
- TPS80031_VRTC_CFG_STATE
 
- TPS80031_VRTC_CFG_TRANS
 
- TPS80031_VSYSMIN_HI_CFG_STATE
 
- TPS80031_VSYSMIN_HI_CFG_TRANS
 
- TPS80031_VSYSMIN_HI_THRESHOLD
 
- TPS80031_VSYSMIN_LO_THRESHOLD
 
- TPS80031_WEEKS_REG
 
- TPS80031_YEARS_REG
 
- TPS80032
 
- TPSFRAME
 
- TPSLOCKED
 
- TPSRAM_NAME
 
- TPSRAM_VERSION
 
- TPSRCVBAD
 
- TPSRCVCHANGED
 
- TPSRCVUPDATE
 
- TPS_ACKINT1
 
- TPS_ACKINT2
 
- TPS_CELL_ID_0
 
- TPS_CELL_ID_1
 
- TPS_CHARGE_CURRENT
 
- TPS_CHARGE_ENABLE
 
- TPS_CHARGE_FAST
 
- TPS_CHARGE_POR
 
- TPS_CHARGE_RESET
 
- TPS_CHGCONFIG
 
- TPS_CHGSTATUS
 
- TPS_CHG_AC
 
- TPS_CHG_CHG_TMO
 
- TPS_CHG_PRECHG_TMO
 
- TPS_CHG_TAPER_TMO
 
- TPS_CHG_TEMP_ERR
 
- TPS_CHG_TERM
 
- TPS_CHG_THERM
 
- TPS_CHG_USB
 
- TPS_CURRENT_0
 
- TPS_CURRENT_1
 
- TPS_DEFAULT_MIN_PRESSURE
 
- TPS_DEFGPIO
 
- TPS_ENABLE_LP
 
- TPS_GIVEN_0
 
- TPS_GIVEN_1
 
- TPS_LDO1_ENABLE
 
- TPS_LDO1_OFF
 
- TPS_LDO2_ENABLE
 
- TPS_LDO2_OFF
 
- TPS_LED1_ON
 
- TPS_LED1_PER
 
- TPS_LED2_ON
 
- TPS_LED2_PER
 
- TPS_LP_COREOFF
 
- TPS_MASK1
 
- TPS_MASK2
 
- TPS_MASK3
 
- TPS_MAX_LEN
 
- TPS_MISC_DATA_0
 
- TPS_MISC_DATA_1
 
- TPS_MISC_DATA_2
 
- TPS_MODE_APP
 
- TPS_MODE_BIST
 
- TPS_MODE_BOOT
 
- TPS_MODE_DISC
 
- TPS_PORTINFO_DRP_DFP
 
- TPS_PORTINFO_DRP_DFP_DRD
 
- TPS_PORTINFO_DRP_UFP
 
- TPS_PORTINFO_DRP_UFP_DRD
 
- TPS_PORTINFO_SINK
 
- TPS_PORTINFO_SINK_ACCESSORY
 
- TPS_PORTINFO_SOURCE
 
- TPS_POWER_STATUS_PWROPMODE
 
- TPS_POWER_STATUS_SOURCESINK
 
- TPS_RECEIVED_0
 
- TPS_RECEIVED_1
 
- TPS_REGSTATUS
 
- TPS_REG_CMD1
 
- TPS_REG_COVER
 
- TPS_REG_CTRL_CONF
 
- TPS_REG_DATA1
 
- TPS_REG_INT_CLEAR1
 
- TPS_REG_INT_CLEAR2
 
- TPS_REG_INT_EVENT1
 
- TPS_REG_INT_EVENT2
 
- TPS_REG_INT_MASK1
 
- TPS_REG_INT_MASK2
 
- TPS_REG_INT_PLUG_EVENT
 
- TPS_REG_MODE
 
- TPS_REG_NO_CHG
 
- TPS_REG_ONOFF
 
- TPS_REG_PG_CORE
 
- TPS_REG_PG_LD01
 
- TPS_REG_PG_LD02
 
- TPS_REG_PG_MAIN
 
- TPS_REG_POWER_STATUS
 
- TPS_REG_RX_IDENTITY_SOP
 
- TPS_REG_STATUS
 
- TPS_REG_SYSTEM_CONF
 
- TPS_REG_UVLO
 
- TPS_REG_VID
 
- TPS_STATUS_DATAROLE
 
- TPS_STATUS_ORIENTATION
 
- TPS_STATUS_PLUG_PRESENT
 
- TPS_STATUS_PORTROLE
 
- TPS_STATUS_VCONN
 
- TPS_SUBSET
 
- TPS_SYSCONF_PORTINFO
 
- TPS_TASK_REJECTED
 
- TPS_TASK_TIMEOUT
 
- TPS_VBUS_500MA
 
- TPS_VBUS_CHARGING
 
- TPS_VCORE_0_85V
 
- TPS_VCORE_1_0V
 
- TPS_VCORE_1_1V
 
- TPS_VCORE_1_2V
 
- TPS_VCORE_1_3V
 
- TPS_VCORE_1_4V
 
- TPS_VCORE_1_5V
 
- TPS_VCORE_1_8V
 
- TPS_VCORE_DISCH
 
- TPS_VCORE_LP_0_85V
 
- TPS_VCORE_LP_1_0V
 
- TPS_VCORE_LP_1_1V
 
- TPS_VCORE_LP_1_2V
 
- TPS_VDCDC1
 
- TPS_VDCDC2
 
- TPS_VIB
 
- TPS_VLDO1_2_5V
 
- TPS_VLDO1_2_75V
 
- TPS_VLDO1_3_0V
 
- TPS_VLDO1_ADJ
 
- TPS_VLDO2_1_8V
 
- TPS_VLDO2_2_5V
 
- TPS_VLDO2_2_75V
 
- TPS_VLDO2_3_0V
 
- TPS_VREGS1
 
- TPT_ERR_ACCESS
 
- TPT_ERR_BOUND
 
- TPT_ERR_CRC
 
- TPT_ERR_DDP_QUEUE_NUM
 
- TPT_ERR_DDP_VERSION
 
- TPT_ERR_ECC
 
- TPT_ERR_ECC_PSTAG
 
- TPT_ERR_INTERNAL_ERR
 
- TPT_ERR_INVALIDATE_MR_WITH_MW_BOUND
 
- TPT_ERR_INVALIDATE_SHARED_MR
 
- TPT_ERR_IRD_OVERFLOW
 
- TPT_ERR_MARKER
 
- TPT_ERR_MO
 
- TPT_ERR_MSN
 
- TPT_ERR_MSN_GAP
 
- TPT_ERR_MSN_RANGE
 
- TPT_ERR_OPCODE
 
- TPT_ERR_OUT_OF_RQE
 
- TPT_ERR_PBL_ADDR_BOUND
 
- TPT_ERR_PDID
 
- TPT_ERR_PDU_LEN_ERR
 
- TPT_ERR_QPID
 
- TPT_ERR_RDMA_VERSION
 
- TPT_ERR_RQE_ADDR_BOUND
 
- TPT_ERR_STAG
 
- TPT_ERR_SUCCESS
 
- TPT_ERR_SWFLUSH
 
- TPT_ERR_TBIT
 
- TPT_ERR_WRAP
 
- TPT_LOCAL_READ
 
- TPT_LOCAL_WRITE
 
- TPT_MW
 
- TPT_MW_BIND
 
- TPT_MW_RELAXED_PROTECTION
 
- TPT_NON_SHARED_MR
 
- TPT_REMOTE_READ
 
- TPT_REMOTE_WRITE
 
- TPT_SHARED_MR
 
- TPT_VATO
 
- TPT_ZBTO
 
- TPU
 
- TPU0
 
- TPU0TO0
 
- TPU0TO0_MARK
 
- TPU0TO1
 
- TPU0TO1_MARK
 
- TPU0TO2
 
- TPU0TO2_MARK
 
- TPU0TO2_PORT202_MARK
 
- TPU0TO2_PORT66_MARK
 
- TPU0TO3
 
- TPU0TO3_MARK
 
- TPU1
 
- TPU1TO0
 
- TPU1TO0_MARK
 
- TPU1TO1
 
- TPU1TO2_MARK
 
- TPU1TO3_MARK
 
- TPU2
 
- TPU2TO0_MARK
 
- TPU2TO1_MARK
 
- TPU2TO2_MARK
 
- TPU2TO3_MARK
 
- TPU3
 
- TPU3TO0_MARK
 
- TPU3TO1_MARK
 
- TPU3TO2_MARK
 
- TPU3TO3_MARK
 
- TPU4TO0_MARK
 
- TPU4TO1_MARK
 
- TPU4TO2_MARK
 
- TPU4TO3_MARK
 
- TPUAdapter
 
- TPUTI2_MARK
 
- TPUTI3_MARK
 
- TPUTO0_B_MARK
 
- TPUTO0_C_MARK
 
- TPUTO0_MARK
 
- TPUTO1_B_MARK
 
- TPUTO1_C_MARK
 
- TPUTO1_MARK
 
- TPUTO2_B_MARK
 
- TPUTO2_C_MARK
 
- TPUTO2_MARK
 
- TPUTO3_B_MARK
 
- TPUTO3_C_MARK
 
- TPUTO3_MARK
 
- TPUTO_MARK
 
- TPU_CHANNEL_MAX
 
- TPU_CHANNEL_OFFSET
 
- TPU_CHANNEL_SIZE
 
- TPU_MASK
 
- TPU_PIN_ACTIVE
 
- TPU_PIN_INACTIVE
 
- TPU_PIN_PWM
 
- TPU_TCNTn
 
- TPU_TCR_CCLR_NONE
 
- TPU_TCR_CCLR_TGRA
 
- TPU_TCR_CCLR_TGRB
 
- TPU_TCR_CCLR_TGRC
 
- TPU_TCR_CCLR_TGRD
 
- TPU_TCR_CKEG_BOTH
 
- TPU_TCR_CKEG_FALLING
 
- TPU_TCR_CKEG_RISING
 
- TPU_TCRn
 
- TPU_TGRAn
 
- TPU_TGRBn
 
- TPU_TGRCn
 
- TPU_TGRDn
 
- TPU_TI2A_MARK
 
- TPU_TI2B_MARK
 
- TPU_TI3A_MARK
 
- TPU_TI3B_MARK
 
- TPU_TIERn
 
- TPU_TIOR_IOA_0
 
- TPU_TIOR_IOA_0_CLR
 
- TPU_TIOR_IOA_0_SET
 
- TPU_TIOR_IOA_0_TOGGLE
 
- TPU_TIOR_IOA_1
 
- TPU_TIOR_IOA_1_CLR
 
- TPU_TIOR_IOA_1_SET
 
- TPU_TIOR_IOA_1_TOGGLE
 
- TPU_TIORn
 
- TPU_TMDR_BFA
 
- TPU_TMDR_BFB
 
- TPU_TMDR_BFWT
 
- TPU_TMDR_MD_NORMAL
 
- TPU_TMDR_MD_PWM
 
- TPU_TMDRn
 
- TPU_TO0_MARK
 
- TPU_TO1_MARK
 
- TPU_TO2_MARK
 
- TPU_TO3_MARK
 
- TPU_TPUI
 
- TPU_TSRn
 
- TPU_TSTR
 
- TPVER
 
- TPV_Q
 
- TPV_QI0
 
- TPV_QI1
 
- TPV_QI2
 
- TPV_QL0
 
- TPV_QL1
 
- TPV_QL2
 
- TPV_Q_X
 
- TPWR_OUT
 
- TPWR_SENSE
 
- TP_ABILITIES_BIOSTASK_NAME
 
- TP_ABILITIES_DATA_SIZE
 
- TP_ABILITIES_INST_SIZE
 
- TP_ABILITIES_INTS_PER_SEC
 
- TP_ABILITIES_MWAVEOS_NAME
 
- TP_ACPI_BLTH_GET_PWR_ON_RESUME
 
- TP_ACPI_BLTH_GET_ULTRAPORT_ID
 
- TP_ACPI_BLTH_PWR_OFF_ON_RESUME
 
- TP_ACPI_BLTH_PWR_ON_ON_RESUME
 
- TP_ACPI_BLTH_SAVE_STATE
 
- TP_ACPI_BLUETOOTH_HWPRESENT
 
- TP_ACPI_BLUETOOTH_RADIOSSW
 
- TP_ACPI_BLUETOOTH_RESUMECTRL
 
- TP_ACPI_HKEY_BRGHTDWN_MASK
 
- TP_ACPI_HKEY_BRGHTUP_MASK
 
- TP_ACPI_HKEY_DISPSWTCH_MASK
 
- TP_ACPI_HKEY_DISPXPAND_MASK
 
- TP_ACPI_HKEY_HIBERNATE_MASK
 
- TP_ACPI_HKEY_KBD_LIGHT_MASK
 
- TP_ACPI_HKEY_MUTE_MASK
 
- TP_ACPI_HKEY_THINKPAD_MASK
 
- TP_ACPI_HKEY_VOLDWN_MASK
 
- TP_ACPI_HKEY_VOLUP_MASK
 
- TP_ACPI_HKEY_ZOOM_MASK
 
- TP_ACPI_HOTKEYSCAN_ADAPTIVE_START
 
- TP_ACPI_HOTKEYSCAN_BACK
 
- TP_ACPI_HOTKEYSCAN_BLUETOOTH
 
- TP_ACPI_HOTKEYSCAN_BRIGHTNESS_ZERO
 
- TP_ACPI_HOTKEYSCAN_CALCULATOR
 
- TP_ACPI_HOTKEYSCAN_CAMERA_MODE
 
- TP_ACPI_HOTKEYSCAN_CLIPPING_TOOL
 
- TP_ACPI_HOTKEYSCAN_CLIPPING_TOOL2
 
- TP_ACPI_HOTKEYSCAN_CLOUD
 
- TP_ACPI_HOTKEYSCAN_CONFIG
 
- TP_ACPI_HOTKEYSCAN_EXTENDED_START
 
- TP_ACPI_HOTKEYSCAN_FNBACKSPACE
 
- TP_ACPI_HOTKEYSCAN_FNDELETE
 
- TP_ACPI_HOTKEYSCAN_FNEND
 
- TP_ACPI_HOTKEYSCAN_FNF1
 
- TP_ACPI_HOTKEYSCAN_FNF10
 
- TP_ACPI_HOTKEYSCAN_FNF11
 
- TP_ACPI_HOTKEYSCAN_FNF12
 
- TP_ACPI_HOTKEYSCAN_FNF2
 
- TP_ACPI_HOTKEYSCAN_FNF3
 
- TP_ACPI_HOTKEYSCAN_FNF4
 
- TP_ACPI_HOTKEYSCAN_FNF5
 
- TP_ACPI_HOTKEYSCAN_FNF6
 
- TP_ACPI_HOTKEYSCAN_FNF7
 
- TP_ACPI_HOTKEYSCAN_FNF8
 
- TP_ACPI_HOTKEYSCAN_FNF9
 
- TP_ACPI_HOTKEYSCAN_FNHOME
 
- TP_ACPI_HOTKEYSCAN_FNINSERT
 
- TP_ACPI_HOTKEYSCAN_FNPAGEDOWN
 
- TP_ACPI_HOTKEYSCAN_FNPAGEUP
 
- TP_ACPI_HOTKEYSCAN_FNSPACE
 
- TP_ACPI_HOTKEYSCAN_GESTURES
 
- TP_ACPI_HOTKEYSCAN_KEYBOARD
 
- TP_ACPI_HOTKEYSCAN_MIC_CANCELLATION
 
- TP_ACPI_HOTKEYSCAN_MIC_DOWN
 
- TP_ACPI_HOTKEYSCAN_MIC_UP
 
- TP_ACPI_HOTKEYSCAN_MUTE
 
- TP_ACPI_HOTKEYSCAN_MUTE2
 
- TP_ACPI_HOTKEYSCAN_NEW_TAB
 
- TP_ACPI_HOTKEYSCAN_RELOAD
 
- TP_ACPI_HOTKEYSCAN_ROTATE_DISPLAY
 
- TP_ACPI_HOTKEYSCAN_STAR
 
- TP_ACPI_HOTKEYSCAN_THINKPAD
 
- TP_ACPI_HOTKEYSCAN_UNK1
 
- TP_ACPI_HOTKEYSCAN_UNK10
 
- TP_ACPI_HOTKEYSCAN_UNK11
 
- TP_ACPI_HOTKEYSCAN_UNK12
 
- TP_ACPI_HOTKEYSCAN_UNK13
 
- TP_ACPI_HOTKEYSCAN_UNK2
 
- TP_ACPI_HOTKEYSCAN_UNK3
 
- TP_ACPI_HOTKEYSCAN_UNK4
 
- TP_ACPI_HOTKEYSCAN_UNK5
 
- TP_ACPI_HOTKEYSCAN_UNK6
 
- TP_ACPI_HOTKEYSCAN_UNK7
 
- TP_ACPI_HOTKEYSCAN_UNK8
 
- TP_ACPI_HOTKEYSCAN_UNK9
 
- TP_ACPI_HOTKEYSCAN_VOICE
 
- TP_ACPI_HOTKEYSCAN_VOLUMEDOWN
 
- TP_ACPI_HOTKEYSCAN_VOLUMEUP
 
- TP_ACPI_MULTI_MODE_FLAT
 
- TP_ACPI_MULTI_MODE_INVALID
 
- TP_ACPI_MULTI_MODE_LAPTOP
 
- TP_ACPI_MULTI_MODE_STAND
 
- TP_ACPI_MULTI_MODE_STAND_TENT
 
- TP_ACPI_MULTI_MODE_TABLET
 
- TP_ACPI_MULTI_MODE_TABLET_LIKE
 
- TP_ACPI_MULTI_MODE_TENT
 
- TP_ACPI_MULTI_MODE_UNKNOWN
 
- TP_ACPI_UWB_HWPRESENT
 
- TP_ACPI_UWB_RADIOSSW
 
- TP_ACPI_VIDEO_570_PHS2CMD
 
- TP_ACPI_VIDEO_570_PHS2SET
 
- TP_ACPI_VIDEO_570_PHSCMD
 
- TP_ACPI_VIDEO_570_PHSMASK
 
- TP_ACPI_VIDEO_S_CRT
 
- TP_ACPI_VIDEO_S_DVI
 
- TP_ACPI_VIDEO_S_LCD
 
- TP_ACPI_WAKEUP_BAYEJ
 
- TP_ACPI_WAKEUP_NONE
 
- TP_ACPI_WAKEUP_UNDOCK
 
- TP_ACPI_WANCARD_HWPRESENT
 
- TP_ACPI_WANCARD_RADIOSSW
 
- TP_ACPI_WANCARD_RESUMECTRL
 
- TP_ACPI_WGSV_GET_STATE
 
- TP_ACPI_WGSV_PWR_OFF_ON_RESUME
 
- TP_ACPI_WGSV_PWR_ON_ON_RESUME
 
- TP_ACPI_WGSV_SAVE_STATE
 
- TP_ACPI_WGSV_STATE_BLTHBIOSOFF
 
- TP_ACPI_WGSV_STATE_BLTHEXIST
 
- TP_ACPI_WGSV_STATE_BLTHPWR
 
- TP_ACPI_WGSV_STATE_BLTHPWRRES
 
- TP_ACPI_WGSV_STATE_UWBEXIST
 
- TP_ACPI_WGSV_STATE_UWBPWR
 
- TP_ACPI_WGSV_STATE_WWANBIOSOFF
 
- TP_ACPI_WGSV_STATE_WWANEXIST
 
- TP_ACPI_WGSV_STATE_WWANPWR
 
- TP_ACPI_WGSV_STATE_WWANPWRRES
 
- TP_ADC_SELECT
 
- TP_ARGS
 
- TP_AUTO_REQUEST_SENSE
 
- TP_BUSY_CYCLES
 
- TP_CANCEL_SOFT_TRANS
 
- TP_CCTRL_TABLE_A
 
- TP_CDAT
 
- TP_CFG_ChipletEnable
 
- TP_CFG_DisableLBusTimeout
 
- TP_CFG_EnablePwrMgmt
 
- TP_CFG_GateIOCHRDY
 
- TP_CFG_HBusTimerValue
 
- TP_CFG_IsaMemCmdWidth
 
- TP_CFG_MEMCS16
 
- TP_CFG_M_Multiplier
 
- TP_CFG_N_Divisor
 
- TP_CFG_NumTransfers
 
- TP_CFG_PllBypass
 
- TP_CFG_RerequestTimer
 
- TP_CMM_MM_BASE_A
 
- TP_CMM_MM_MAX_PSTRUCT_A
 
- TP_CMM_MM_PS_FLST_BASE_A
 
- TP_CMM_MM_RX_FLST_BASE_A
 
- TP_CMM_MM_TX_FLST_BASE_A
 
- TP_CMM_TCB_BASE_A
 
- TP_CMM_TIMER_BASE_A
 
- TP_CMOS_BRIGHTNESS_DOWN
 
- TP_CMOS_BRIGHTNESS_UP
 
- TP_CMOS_THINKLIGHT_OFF
 
- TP_CMOS_THINKLIGHT_ON
 
- TP_CMOS_VOLUME_DOWN
 
- TP_CMOS_VOLUME_MUTE
 
- TP_CMOS_VOLUME_UP
 
- TP_COMMAND
 
- TP_CONDITION
 
- TP_CTRL0
 
- TP_CTRL1
 
- TP_CTRL2
 
- TP_CTRL3
 
- TP_C_MIN
 
- TP_DACK_TIMER
 
- TP_DACK_TIMER_A
 
- TP_DATA
 
- TP_DATA_XY_CHANGE
 
- TP_DBG_LA_CONFIG_A
 
- TP_DBG_LA_DATAL_A
 
- TP_DEF_DRAGHYS
 
- TP_DEF_DRIFT_TIME
 
- TP_DEF_EXT_DEV
 
- TP_DEF_INERTIA
 
- TP_DEF_JENKS_CURV
 
- TP_DEF_MB
 
- TP_DEF_MINDRAG
 
- TP_DEF_PTSON
 
- TP_DEF_REACH
 
- TP_DEF_SENS
 
- TP_DEF_SKIPBACK
 
- TP_DEF_SOURCE_TAG
 
- TP_DEF_SPEED
 
- TP_DEF_THRESH
 
- TP_DEF_TWOHAND
 
- TP_DEF_UP_THRESH
 
- TP_DEF_Z_TIME
 
- TP_DISABLE_EXT
 
- TP_DISCONNECT
 
- TP_DOWN_IRQ_EN
 
- TP_DOWN_PENDING
 
- TP_DRAGHYS
 
- TP_DRIFT_TIME
 
- TP_DUAL_EN
 
- TP_EC_AUDIO
 
- TP_EC_AUDIO_LVL_MSK
 
- TP_EC_AUDIO_MUTESW
 
- TP_EC_AUDIO_MUTESW_MSK
 
- TP_EC_BACKLIGHT
 
- TP_EC_BACKLIGHT_CMDMSK
 
- TP_EC_BACKLIGHT_LVLMSK
 
- TP_EC_BACKLIGHT_MAPSW
 
- TP_EC_FAN_AUTO
 
- TP_EC_FAN_FULLSPEED
 
- TP_EC_MUTE_BTN_LATCH
 
- TP_EC_MUTE_BTN_NONE
 
- TP_EC_MUTE_BTN_TOGGLE
 
- TP_EC_THERMAL_TMP0
 
- TP_EC_THERMAL_TMP8
 
- TP_EC_THERMAL_TMP_NA
 
- TP_EC_VOLUME_MAX
 
- TP_ENABLE_EXT
 
- TP_EXT_BTN
 
- TP_EXT_DEV
 
- TP_F
 
- TP_FINWAIT2_TIMER_A
 
- TP_FLAG_PROFILE
 
- TP_FLAG_TRACE
 
- TP_FLM_FREE_PS_CNT_A
 
- TP_FLM_FREE_RX_CNT_A
 
- TP_FLM_FREE_TX_CNT_A
 
- TP_FRAMING_ERROR_F
 
- TP_FRAMING_ERROR_S
 
- TP_FRAMING_ERROR_V
 
- TP_FT_REQ_FILL_RXHASH
 
- TP_GLOBAL_CONFIG_A
 
- TP_HKEY_EV_AC_CHANGED
 
- TP_HKEY_EV_ALARM_BAT_HOT
 
- TP_HKEY_EV_ALARM_BAT_XHOT
 
- TP_HKEY_EV_ALARM_SENSOR_HOT
 
- TP_HKEY_EV_ALARM_SENSOR_XHOT
 
- TP_HKEY_EV_BAYEJ_ACK
 
- TP_HKEY_EV_BRGHT_CHANGED
 
- TP_HKEY_EV_BRGHT_DOWN
 
- TP_HKEY_EV_BRGHT_UP
 
- TP_HKEY_EV_HOTKEY_BASE
 
- TP_HKEY_EV_HOTPLUG_DOCK
 
- TP_HKEY_EV_HOTPLUG_UNDOCK
 
- TP_HKEY_EV_KBD_LIGHT
 
- TP_HKEY_EV_KEY_FN
 
- TP_HKEY_EV_KEY_FN_ESC
 
- TP_HKEY_EV_KEY_NUMLOCK
 
- TP_HKEY_EV_LID_CLOSE
 
- TP_HKEY_EV_LID_OPEN
 
- TP_HKEY_EV_OPTDRV_EJ
 
- TP_HKEY_EV_PALM_DETECTED
 
- TP_HKEY_EV_PALM_UNDETECTED
 
- TP_HKEY_EV_PEN_INSERTED
 
- TP_HKEY_EV_PEN_REMOVED
 
- TP_HKEY_EV_RFKILL_CHANGED
 
- TP_HKEY_EV_TABLET_CHANGED
 
- TP_HKEY_EV_TABLET_NOTEBOOK
 
- TP_HKEY_EV_TABLET_TABLET
 
- TP_HKEY_EV_THM_CSM_COMPLETED
 
- TP_HKEY_EV_THM_TABLE_CHANGED
 
- TP_HKEY_EV_THM_TRANSFM_CHANGED
 
- TP_HKEY_EV_UNDOCK_ACK
 
- TP_HKEY_EV_VOL_DOWN
 
- TP_HKEY_EV_VOL_MUTE
 
- TP_HKEY_EV_VOL_UP
 
- TP_HKEY_EV_WKUP_S3_BATLOW
 
- TP_HKEY_EV_WKUP_S3_BAYEJ
 
- TP_HKEY_EV_WKUP_S3_UNDOCK
 
- TP_HKEY_EV_WKUP_S4_BATLOW
 
- TP_HKEY_EV_WKUP_S4_BAYEJ
 
- TP_HKEY_EV_WKUP_S4_UNDOCK
 
- TP_HOTKEY_TABLET_MASK
 
- TP_HOTKEY_TABLET_NONE
 
- TP_HOTKEY_TABLET_USES_GMMS
 
- TP_HOTKEY_TABLET_USES_MHKG
 
- TP_HWRNGCPRB
 
- TP_ICARSACRT
 
- TP_ICARSAMODEXPO
 
- TP_IDLE_FLG
 
- TP_INERTIA
 
- TP_INGRESS_CONFIG_A
 
- TP_INIT_SRTT_A
 
- TP_INT
 
- TP_INT_CAUSE_A
 
- TP_INT_FIFOC
 
- TP_INT_FIFOS
 
- TP_JENKS_CURV
 
- TP_KEEP_IDLE_A
 
- TP_KEEP_INTVL_A
 
- TP_L1_MISSES
 
- TP_L1_REQUESTS
 
- TP_LC_LENGTH
 
- TP_LC_LONGLN
 
- TP_LINK_FAIL
 
- TP_LINK_PASS
 
- TP_MASK_BURST
 
- TP_MASK_DRIFT
 
- TP_MASK_EXT_DEV
 
- TP_MASK_EXT_TAG
 
- TP_MASK_HARD_TRANS
 
- TP_MASK_MB
 
- TP_MASK_PTSON
 
- TP_MASK_SKIPBACK
 
- TP_MASK_SOURCE_TAG
 
- TP_MASK_STICKY_TWO
 
- TP_MASK_TWOHAND
 
- TP_MAX_RX_COALESCING_SIZE
 
- TP_MB
 
- TP_METRICS_BIT_1F_JITTER
 
- TP_METRICS_BIT_1F_SPIKE
 
- TP_METRICS_BIT_2F_JITTER
 
- TP_METRICS_BIT_2F_SPIKE
 
- TP_METRICS_BIT_ABS_PKT_FORMAT_SET
 
- TP_METRICS_BIT_APA
 
- TP_METRICS_BIT_MTG
 
- TP_METRICS_BIT_PALM
 
- TP_METRICS_BIT_STUBBORN
 
- TP_METRICS_MASK
 
- TP_MIB_CPL_IN_REQ_0_A
 
- TP_MIB_CPL_OUT_RSP_0_A
 
- TP_MIB_DATA_A
 
- TP_MIB_FCOE_BYTE_0_HI_A
 
- TP_MIB_FCOE_DDP_0_A
 
- TP_MIB_FCOE_DROP_0_A
 
- TP_MIB_HDR_IN_ERR_0_A
 
- TP_MIB_INDEX_A
 
- TP_MIB_MAC_IN_ERR_0_A
 
- TP_MIB_OFD_ARP_DROP_A
 
- TP_MIB_OFD_CHN_DROP_0_A
 
- TP_MIB_OFD_VLN_DROP_0_A
 
- TP_MIB_RQE_DFR_PKT_A
 
- TP_MIB_TCP_IN_ERR_0_A
 
- TP_MIB_TCP_IN_SEG_HI_A
 
- TP_MIB_TCP_IN_SEG_LO_A
 
- TP_MIB_TCP_OUT_RST_A
 
- TP_MIB_TCP_OUT_SEG_HI_A
 
- TP_MIB_TCP_OUT_SEG_LO_A
 
- TP_MIB_TCP_RXT_SEG_HI_A
 
- TP_MIB_TCP_RXT_SEG_LO_A
 
- TP_MIB_TCP_V6IN_ERR_0_A
 
- TP_MIB_TCP_V6OUT_RST_A
 
- TP_MIB_TNL_CNG_DROP_0_A
 
- TP_MIB_TNL_DROP_0_A
 
- TP_MIB_USM_PKTS_A
 
- TP_MINDRAG
 
- TP_MODE
 
- TP_MODE_EN
 
- TP_MODE_SELECT
 
- TP_MOD_CONFIG_A
 
- TP_MTU_TABLE_A
 
- TP_NS_MAX
 
- TP_NVRAM_ADDR_BRIGHTNESS
 
- TP_NVRAM_ADDR_HK2
 
- TP_NVRAM_ADDR_MIXER
 
- TP_NVRAM_ADDR_THINKLIGHT
 
- TP_NVRAM_ADDR_VIDEO
 
- TP_NVRAM_HKEY_GROUP_BRIGHTNESS
 
- TP_NVRAM_HKEY_GROUP_HK2
 
- TP_NVRAM_HKEY_GROUP_VOLUME
 
- TP_NVRAM_LEVEL_VOLUME_MAX
 
- TP_NVRAM_MASK_HKT_BRIGHTNESS
 
- TP_NVRAM_MASK_HKT_DISPEXPND
 
- TP_NVRAM_MASK_HKT_DISPLAY
 
- TP_NVRAM_MASK_HKT_HIBERNATE
 
- TP_NVRAM_MASK_HKT_THINKPAD
 
- TP_NVRAM_MASK_HKT_VOLUME
 
- TP_NVRAM_MASK_HKT_ZOOM
 
- TP_NVRAM_MASK_LEVEL_BRIGHTNESS
 
- TP_NVRAM_MASK_LEVEL_VOLUME
 
- TP_NVRAM_MASK_MUTE
 
- TP_NVRAM_MASK_THINKLIGHT
 
- TP_NVRAM_POS_LEVEL_BRIGHTNESS
 
- TP_NVRAM_POS_LEVEL_VOLUME
 
- TP_NW
 
- TP_OUT_CONFIG_A
 
- TP_PACE_TABLE_A
 
- TP_PARA_REG2_A
 
- TP_PARITY
 
- TP_PARITY_INIT
 
- TP_PERS_MAX_A
 
- TP_PERS_MIN_A
 
- TP_PIO_ADDR_A
 
- TP_PIO_DATA_A
 
- TP_PMM_RX_BASE_A
 
- TP_PMM_RX_MAX_PAGE_A
 
- TP_PMM_RX_PAGE_SIZE_A
 
- TP_PMM_TX_BASE_A
 
- TP_PMM_TX_MAX_PAGE_A
 
- TP_PMM_TX_PAGE_SIZE_A
 
- TP_POLL
 
- TP_POR
 
- TP_POR_RESULTS
 
- TP_POR_SUCCESS
 
- TP_POWER0
 
- TP_POWER1
 
- TP_POWER2
 
- TP_POWER3
 
- TP_POWER4
 
- TP_POWER5
 
- TP_POWER6
 
- TP_POWER7
 
- TP_POWER_DOWN
 
- TP_PPR
 
- TP_PROTO
 
- TP_QUADS_1D2D
 
- TP_QUADS_3DCUBE
 
- TP_QUADS_ARRAY
 
- TP_QUADS_GRADIENT
 
- TP_QUADS_OFFSET
 
- TP_QUAD_SHADOW
 
- TP_REACH
 
- TP_READ_ID
 
- TP_READ_MEM
 
- TP_RECALIB
 
- TP_RENEGOTIATE
 
- TP_RSS_CONFIG_A
 
- TP_RSS_CONFIG_CNG_A
 
- TP_RSS_CONFIG_OFD_A
 
- TP_RSS_CONFIG_SYN_A
 
- TP_RSS_CONFIG_TNL_A
 
- TP_RSS_CONFIG_VRT_A
 
- TP_RSS_LKP_TABLE_A
 
- TP_RSS_PF0_CONFIG_A
 
- TP_RSS_PF_MAP_A
 
- TP_RSS_PF_MSK_A
 
- TP_RSS_SECRET_KEY0_A
 
- TP_RSS_VFH_CONFIG_A
 
- TP_RSS_VFL_CONFIG_A
 
- TP_RTO_MIN
 
- TP_RXT_MAX_A
 
- TP_RXT_MIN_A
 
- TP_S
 
- TP_SENS
 
- TP_SENSITIVE_ADJUST
 
- TP_SET
 
- TP_SET_HARD_TRANS
 
- TP_SET_SOFT_TRANS
 
- TP_SHIFT_CNT_A
 
- TP_SPEED
 
- TP_STALL_CYCLES_BY_ARB
 
- TP_STATE_CACHE_MISSES
 
- TP_STATE_CACHE_REQUESTS
 
- TP_STATUS_AVAILABLE
 
- TP_STATUS_BLK_TMO
 
- TP_STATUS_COPY
 
- TP_STATUS_CSUMNOTREADY
 
- TP_STATUS_CSUM_VALID
 
- TP_STATUS_KERNEL
 
- TP_STATUS_LOSING
 
- TP_STATUS_SENDING
 
- TP_STATUS_SEND_REQUEST
 
- TP_STATUS_TS_RAW_HARDWARE
 
- TP_STATUS_TS_SOFTWARE
 
- TP_STATUS_TS_SYS_HARDWARE
 
- TP_STATUS_USER
 
- TP_STATUS_VLAN_TPID_VALID
 
- TP_STATUS_VLAN_VALID
 
- TP_STATUS_WRONG_FORMAT
 
- TP_STOP_QUEUE
 
- TP_STORE_ADDRS
 
- TP_STORE_ADDR_PORTS
 
- TP_STORE_ADDR_PORTS_V4
 
- TP_STORE_SIGINFO
 
- TP_STORE_V4MAPPED
 
- TP_STRUCT__entry
 
- TP_STRUCT__entry_btrfs
 
- TP_STRUCT__entry_fsid
 
- TP_SUSPECT
 
- TP_SYNC
 
- TP_TAGGED_QUEUE
 
- TP_TB_MIN
 
- TP_THRESH
 
- TP_TIMER_RESOLUTION_A
 
- TP_TL_MIN
 
- TP_TMR_RES
 
- TP_TM_PIO_ADDR_A
 
- TP_TM_PIO_DATA_A
 
- TP_TOGGLE
 
- TP_TOGGLE_BURST
 
- TP_TOGGLE_DRIFT
 
- TP_TOGGLE_EXT_DEV
 
- TP_TOGGLE_EXT_TAG
 
- TP_TOGGLE_HARD_TRANS
 
- TP_TOGGLE_MB
 
- TP_TOGGLE_PTSON
 
- TP_TOGGLE_SKIPBACK
 
- TP_TOGGLE_SOURCE_TAG
 
- TP_TOGGLE_STICKY_TWO
 
- TP_TOGGLE_TWOHAND
 
- TP_TPR
 
- TP_TX_MOD_CHANNEL_WEIGHT_A
 
- TP_TX_MOD_Q1_Q0_RATE_LIMIT_A
 
- TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A
 
- TP_TX_MOD_QUEUE_REQ_MAP_A
 
- TP_TX_MOD_QUEUE_WEIGHT0_A
 
- TP_TX_ORATE_A
 
- TP_TX_SCHED_FIFO_A
 
- TP_TX_SCHED_HDR_A
 
- TP_TX_SCHED_PCMD_A
 
- TP_TX_TRATE_A
 
- TP_T_OUT
 
- TP_T_SCRUB
 
- TP_UINT_FIELD
 
- TP_UINT_FIELD__SWAPPED
 
- TP_UP_IRQ_EN
 
- TP_UP_PENDING
 
- TP_UP_THRESH
 
- TP_V
 
- TP_VARIANT_ALPS
 
- TP_VARIANT_ELAN
 
- TP_VARIANT_IBM
 
- TP_VARIANT_NXP
 
- TP_VEC_MAX
 
- TP_VERSION_MAJOR
 
- TP_VERSION_MICRO
 
- TP_VERSION_MINOR
 
- TP_VLAN_PRI_MAP_A
 
- TP_WIDE
 
- TP_WRITE_MEM
 
- TP_ZSENDEP11CPRB
 
- TP_Z_TIME
 
- TP_fast_assign
 
- TP_fast_assign_btrfs
 
- TP_fast_assign_fsid
 
- TP_printk
 
- TP_printk_btrfs
 
- TPchipPCTL
 
- TPchipPERRMASK
 
- TPchipPERROR
 
- TPchipWSBA
 
- TQMX86_DIR_INPUT_MASK
 
- TQMX86_GPIIC
 
- TQMX86_GPIIS
 
- TQMX86_GPII_BITS
 
- TQMX86_GPII_FALLING
 
- TQMX86_GPII_MASK
 
- TQMX86_GPII_RISING
 
- TQMX86_GPIOD
 
- TQMX86_GPIODD
 
- TQMX86_IOBASE
 
- TQMX86_IOBASE_GPIO
 
- TQMX86_IOBASE_I2C
 
- TQMX86_IOBASE_WATCHDOG
 
- TQMX86_IOSIZE
 
- TQMX86_IOSIZE_GPIO
 
- TQMX86_IOSIZE_I2C
 
- TQMX86_IOSIZE_WATCHDOG
 
- TQMX86_NGPI
 
- TQMX86_NGPIO
 
- TQMX86_NGPO
 
- TQMX86_REG_BOARD_ID
 
- TQMX86_REG_BOARD_ID_50UC
 
- TQMX86_REG_BOARD_ID_60EB
 
- TQMX86_REG_BOARD_ID_70EB
 
- TQMX86_REG_BOARD_ID_80UC
 
- TQMX86_REG_BOARD_ID_90UC
 
- TQMX86_REG_BOARD_ID_E38C
 
- TQMX86_REG_BOARD_ID_E38M
 
- TQMX86_REG_BOARD_ID_E39C
 
- TQMX86_REG_BOARD_ID_E39M
 
- TQMX86_REG_BOARD_ID_E39x
 
- TQMX86_REG_BOARD_REV
 
- TQMX86_REG_I2C_DETECT
 
- TQMX86_REG_I2C_DETECT_SOFT
 
- TQMX86_REG_I2C_INT_EN
 
- TQMX86_REG_IO_EXT_INT
 
- TQMX86_REG_IO_EXT_INT_12
 
- TQMX86_REG_IO_EXT_INT_7
 
- TQMX86_REG_IO_EXT_INT_9
 
- TQMX86_REG_IO_EXT_INT_GPIO_SHIFT
 
- TQMX86_REG_IO_EXT_INT_MASK
 
- TQMX86_REG_IO_EXT_INT_NONE
 
- TQMX86_WDCFG
 
- TQMX86_WDCS
 
- TQUEUE_EN0
 
- TQUEUE_EN1
 
- TQUEUE_EN2
 
- TQUEUE_EN3
 
- TQUEUE_EN4
 
- TQUEUE_EN5
 
- TQUEUE_EN6
 
- TQUEUE_EN7
 
- TQUEUE_EN_ALL
 
- TQWake
 
- TR
 
- TR03WT_WT0_MASK
 
- TR03WT_WT1_MASK
 
- TR03WT_WT2_MASK
 
- TR03WT_WT3_MASK
 
- TR0MODE
 
- TR0RST
 
- TR1
 
- TR127
 
- TR127_ADDR
 
- TR1CAPT
 
- TR1K
 
- TR1K_ADDR
 
- TR1PLAY
 
- TR255
 
- TR255_ADDR
 
- TR47WT_WT4_MASK
 
- TR47WT_WT5_MASK
 
- TR47WT_WT6_MASK
 
- TR47WT_WT7_MASK
 
- TR511
 
- TR511_ADDR
 
- TR64
 
- TR64_ADDR
 
- TRA
 
- TRACE
 
- TRACE2
 
- TRACE3
 
- TRACEAUD_FROM_LCDC0_MARK
 
- TRACEAUD_FROM_MEMC_MARK
 
- TRACEAUD_FROM_VIO_MARK
 
- TRACEBUF
 
- TRACECLK_MARK
 
- TRACECTL_MARK
 
- TRACEDATA
 
- TRACEDIR
 
- TRACED_FUNC_FRAME_SIZE
 
- TRACEFS_DEFAULT_MODE
 
- TRACEFS_DEFAULT_PATH
 
- TRACEFS_MAGIC
 
- TRACEIN_CK
 
- TRACEPOINTS_ENABLED
 
- TRACEPOINT_DEFAULT_PRIO
 
- TRACEPOINT_DEFS_H
 
- TRACEPOINT_STR
 
- TRACEREG32_SZ
 
- TRACEREG_SZ
 
- TRACER_BLOCK_SIZE_BYTE
 
- TRACER_BUFFER_CHUNK
 
- TRACER_BUFFER_PAGE_NUM
 
- TRACER_EVENT_TYPE_STRING
 
- TRACER_EVENT_TYPE_TIMESTAMP
 
- TRACER_EVENT_TYPE_UNRECOGNIZED
 
- TRACER_IRQS_OFF
 
- TRACER_MAX_PARAMS
 
- TRACER_OPT
 
- TRACER_PREEMPT_OFF
 
- TRACES_PER_BLOCK
 
- TRACE_3780I
 
- TRACE_ARRAY_FL_GLOBAL
 
- TRACE_ARRAY_SIZE
 
- TRACE_BEGIN
 
- TRACE_BEGIN_CODE
 
- TRACE_BITS
 
- TRACE_BLK
 
- TRACE_BLK_OPT_CGNAME
 
- TRACE_BLK_OPT_CGROUP
 
- TRACE_BLK_OPT_CLASSIC
 
- TRACE_BPRINT
 
- TRACE_BPUTS
 
- TRACE_BRANCH
 
- TRACE_BRANCH_BIT
 
- TRACE_BUFFER_BIT
 
- TRACE_BUFFER_IRQ_BIT
 
- TRACE_BUFFER_MAX_SIZE
 
- TRACE_BUFFER_NMI_BIT
 
- TRACE_BUFFER_SIRQ_BIT
 
- TRACE_BUFFER_SIZE_BYTE
 
- TRACE_BUF_SIZE
 
- TRACE_BUF_SIZE_DEFAULT
 
- TRACE_CGROUP_PATH
 
- TRACE_CGROUP_PATH_LEN
 
- TRACE_CONTEXT_BITS
 
- TRACE_CONTEXT_MASK
 
- TRACE_CTX
 
- TRACE_DEFAULT_FLAGS
 
- TRACE_DEFINE_ENUM
 
- TRACE_DEFINE_SIZEOF
 
- TRACE_DEVICE
 
- TRACE_DISABLE_INTS
 
- TRACE_ENABLE_INTS
 
- TRACE_END_CODE
 
- TRACE_EVENT
 
- TRACE_EVENT_CONDITION
 
- TRACE_EVENT_FLAGS
 
- TRACE_EVENT_FL_CAP_ANY_BIT
 
- TRACE_EVENT_FL_FILTERED_BIT
 
- TRACE_EVENT_FL_IGNORE_ENABLE_BIT
 
- TRACE_EVENT_FL_KPROBE_BIT
 
- TRACE_EVENT_FL_NO_SET_FILTER_BIT
 
- TRACE_EVENT_FL_TRACEPOINT_BIT
 
- TRACE_EVENT_FL_UPROBE_BIT
 
- TRACE_EVENT_FN
 
- TRACE_EVENT_FN_COND
 
- TRACE_EVENT_NOP
 
- TRACE_EVENT_PERF_PERM
 
- TRACE_EVENT_RCU
 
- TRACE_EVENT_TYPE_MAX
 
- TRACE_FILE_ANNOTATE
 
- TRACE_FILE_LAT_FMT
 
- TRACE_FILE_SIZE
 
- TRACE_FILE_TIME_IN_NS
 
- TRACE_FLAGS
 
- TRACE_FLAGS_MAX_SIZE
 
- TRACE_FLAG_HARDIRQ
 
- TRACE_FLAG_IRQS_NOSUPPORT
 
- TRACE_FLAG_IRQS_OFF
 
- TRACE_FLAG_NEED_RESCHED
 
- TRACE_FLAG_NMI
 
- TRACE_FLAG_PREEMPT_RESCHED
 
- TRACE_FLAG_SOFTIRQ
 
- TRACE_FLPY_INT
 
- TRACE_FN
 
- TRACE_FTRACE_BIT
 
- TRACE_FTRACE_IRQ_BIT
 
- TRACE_FTRACE_MAX
 
- TRACE_FTRACE_NMI_BIT
 
- TRACE_FTRACE_SIRQ_BIT
 
- TRACE_FTRACE_START
 
- TRACE_FUNC_OPT_STACK
 
- TRACE_FUNC_SIZE
 
- TRACE_GRAPH_BIT
 
- TRACE_GRAPH_DEPTH_END_BIT
 
- TRACE_GRAPH_DEPTH_START_BIT
 
- TRACE_GRAPH_ENT
 
- TRACE_GRAPH_GRAPH_TIME
 
- TRACE_GRAPH_INDENT
 
- TRACE_GRAPH_NOTRACE_BIT
 
- TRACE_GRAPH_PRINT_ABS_TIME
 
- TRACE_GRAPH_PRINT_CPU
 
- TRACE_GRAPH_PRINT_DURATION
 
- TRACE_GRAPH_PRINT_FILL_MASK
 
- TRACE_GRAPH_PRINT_FILL_SHIFT
 
- TRACE_GRAPH_PRINT_IRQS
 
- TRACE_GRAPH_PRINT_OVERHEAD
 
- TRACE_GRAPH_PRINT_OVERRUN
 
- TRACE_GRAPH_PRINT_PROC
 
- TRACE_GRAPH_PRINT_REL_TIME
 
- TRACE_GRAPH_PRINT_TAIL
 
- TRACE_GRAPH_PROCINFO_LENGTH
 
- TRACE_GRAPH_RET
 
- TRACE_GRAPH_SLEEP_TIME
 
- TRACE_HEADER_MULTI_READ
 
- TRACE_HWLAT
 
- TRACE_IMC_ENABLE
 
- TRACE_IN
 
- TRACE_INCLUDE
 
- TRACE_INCLUDE_FILE
 
- TRACE_INCLUDE_PATH
 
- TRACE_INTERNAL_BIT
 
- TRACE_INTERNAL_IRQ_BIT
 
- TRACE_INTERNAL_NMI_BIT
 
- TRACE_INTERNAL_SIRQ_BIT
 
- TRACE_IOCG_PATH
 
- TRACE_IOCG_PATH_LEN
 
- TRACE_IRQS_FLAGS
 
- TRACE_IRQS_IRET
 
- TRACE_IRQS_IRETQ
 
- TRACE_IRQS_IRETQ_DEBUG
 
- TRACE_IRQS_OFF
 
- TRACE_IRQS_OFF_DEBUG
 
- TRACE_IRQS_OFF_ENTRY
 
- TRACE_IRQS_ON
 
- TRACE_IRQS_ON_DEBUG
 
- TRACE_IRQS_ON_RELOAD
 
- TRACE_IRQS_ON_SYSCALL
 
- TRACE_IRQS_OP
 
- TRACE_IRQS_RELOAD_REGS
 
- TRACE_IRQS_SAVE
 
- TRACE_IRQ_BIT
 
- TRACE_ITEM_CNT
 
- TRACE_ITER_CLEAN
 
- TRACE_ITER_FUNC_FORK
 
- TRACE_ITER_INIT
 
- TRACE_ITER_LAST_BIT
 
- TRACE_ITER_SYM_MASK
 
- TRACE_L
 
- TRACE_LEN
 
- TRACE_LIST_MAX
 
- TRACE_LIST_START
 
- TRACE_M
 
- TRACE_MAKE_SYSTEM_STR
 
- TRACE_MAX_LENGTH
 
- TRACE_MAX_PRINT
 
- TRACE_MMIO_MAP
 
- TRACE_MMIO_RW
 
- TRACE_MODE_MASK
 
- TRACE_MODE_RUN
 
- TRACE_MODE_SI
 
- TRACE_MSG
 
- TRACE_MWAVE
 
- TRACE_NILFS2_TRANSACTION_ABORT
 
- TRACE_NILFS2_TRANSACTION_BEGIN
 
- TRACE_NILFS2_TRANSACTION_COMMIT
 
- TRACE_NILFS2_TRANSACTION_LOCK
 
- TRACE_NILFS2_TRANSACTION_TRYLOCK
 
- TRACE_NILFS2_TRANSACTION_UNLOCK
 
- TRACE_NOP_OPT_ACCEPT
 
- TRACE_NOP_OPT_REFUSE
 
- TRACE_NUM_REGISTERS
 
- TRACE_OFF
 
- TRACE_ON
 
- TRACE_ON_WHAT_BIT
 
- TRACE_OUT
 
- TRACE_PE
 
- TRACE_PFMAJ
 
- TRACE_PFMIN
 
- TRACE_PRINT
 
- TRACE_PRINTKS
 
- TRACE_PS
 
- TRACE_Q
 
- TRACE_RAW_DATA
 
- TRACE_REGISTER_SPACING
 
- TRACE_REG_PERF_ADD
 
- TRACE_REG_PERF_CLOSE
 
- TRACE_REG_PERF_DEL
 
- TRACE_REG_PERF_OPEN
 
- TRACE_REG_PERF_REGISTER
 
- TRACE_REG_PERF_UNREGISTER
 
- TRACE_REG_REGISTER
 
- TRACE_REG_UNREGISTER
 
- TRACE_RESUME
 
- TRACE_RET
 
- TRACE_RS_CLAIM
 
- TRACE_RS_DELETE
 
- TRACE_RS_INSERT
 
- TRACE_RS_TREEDEL
 
- TRACE_SAMPLE_BAR
 
- TRACE_SAMPLE_FOO
 
- TRACE_SAMPLE_ZOO
 
- TRACE_SELFTEST_REGS_FOUND
 
- TRACE_SELFTEST_REGS_NOT_FOUND
 
- TRACE_SELFTEST_REGS_START
 
- TRACE_SEQ_BUF_LEFT
 
- TRACE_SEQ_BUF_SIZE
 
- TRACE_SEQ_BUF_USED
 
- TRACE_SEQ_CHECK
 
- TRACE_SEQ_CHECK_RET
 
- TRACE_SEQ_CHECK_RET0
 
- TRACE_SEQ_CHECK_RET_N
 
- TRACE_SEQ_POISON
 
- TRACE_SEQ__BUFFER_POISONED
 
- TRACE_SEQ__GOOD
 
- TRACE_SEQ__MEM_ALLOC_FAILED
 
- TRACE_SIGNAL_ALREADY_PENDING
 
- TRACE_SIGNAL_DELIVERED
 
- TRACE_SIGNAL_IGNORED
 
- TRACE_SIGNAL_LOSE_INFO
 
- TRACE_SIGNAL_OVERFLOW_FAIL
 
- TRACE_SMAPI
 
- TRACE_STACK
 
- TRACE_STATUS
 
- TRACE_STR_MSG
 
- TRACE_SUSPEND
 
- TRACE_SYMBOL
 
- TRACE_SYSCALLS
 
- TRACE_SYSTEM
 
- TRACE_SYSTEM_STRING
 
- TRACE_SYSTEM_VAR
 
- TRACE_TEXT
 
- TRACE_TO_MEMORY
 
- TRACE_TP3780I
 
- TRACE_TYPE_COUNTER
 
- TRACE_TYPE_HANDLED
 
- TRACE_TYPE_INDENT
 
- TRACE_TYPE_NO_CONSUME
 
- TRACE_TYPE_OUTDENT
 
- TRACE_TYPE_PARTIAL_LINE
 
- TRACE_TYPE_REG
 
- TRACE_TYPE_STRING
 
- TRACE_TYPE_UNHANDLED
 
- TRACE_USER_STACK
 
- TRACE_VEC
 
- TRACE_WAKE
 
- TRACE_WITH_FRAME_BUFFER
 
- TRACING_LOG_ERRS_MAX
 
- TRACING_LOG_LOC_MAX
 
- TRACING_MAP_ARRAY_ELT
 
- TRACING_MAP_BITS_DEFAULT
 
- TRACING_MAP_BITS_MAX
 
- TRACING_MAP_BITS_MIN
 
- TRACING_MAP_ELT
 
- TRACING_MAP_ENTRY
 
- TRACING_MAP_FIELDS_MAX
 
- TRACING_MAP_KEYS_MAX
 
- TRACING_MAP_SORT_KEYS_MAX
 
- TRACING_MAP_VALS_MAX
 
- TRACING_MAP_VARS_MAX
 
- TRACK
 
- TRACKPAD2_BT_REPORT_ID
 
- TRACKPAD2_DIMENSION_X
 
- TRACKPAD2_DIMENSION_Y
 
- TRACKPAD2_MAX_X
 
- TRACKPAD2_MAX_Y
 
- TRACKPAD2_MIN_X
 
- TRACKPAD2_MIN_Y
 
- TRACKPAD2_RES_X
 
- TRACKPAD2_RES_Y
 
- TRACKPAD2_USB_REPORT_ID
 
- TRACKPAD_DIMENSION_X
 
- TRACKPAD_DIMENSION_Y
 
- TRACKPAD_MAX_X
 
- TRACKPAD_MAX_Y
 
- TRACKPAD_MIN_X
 
- TRACKPAD_MIN_Y
 
- TRACKPAD_REPORT_ID
 
- TRACKPAD_RES_X
 
- TRACKPAD_RES_Y
 
- TRACKPOINT_BIT_ATTR
 
- TRACKPOINT_INT_ATTR
 
- TRACKPOINT_SET_POWER_ON_DEFAULT
 
- TRACKPOINT_UPDATE
 
- TRACKSTICK_RANGE_END
 
- TRACKSTICK_RANGE_START
 
- TRACK_ADDRS_COUNT
 
- TRACK_ALLOC
 
- TRACK_FREE
 
- TRACK_MODE_ENABLE
 
- TRACK_ZERO
 
- TRAC_CHANNEL_ACCESS_FAILURE
 
- TRAC_INVALID
 
- TRAC_MASK
 
- TRAC_NO_ACK
 
- TRAC_SUCCESS
 
- TRAC_SUCCESS_DATA_PENDING
 
- TRAC_SUCCESS_WAIT_FOR_ACK
 
- TRAFFIC_HIGH
 
- TRAFFIC_LOAD
 
- TRAFFIC_LOW
 
- TRAFFIC_SHAPER_EN
 
- TRAFFIC_SHAPER_FIXPOINT_FACTOR
 
- TRAFFIC_SHAPER_RD_CLIENT
 
- TRAFFIC_SHAPER_WR_CLIENT
 
- TRAFFIC_TYPE_APERIODIC
 
- TRAFFIC_TYPE_ETH
 
- TRAFFIC_TYPE_PERIODIC
 
- TRAFFIC_TYPE_PORT
 
- TRAFFIC_UltraLOW
 
- TRAIL_BRES_DEC
 
- TRAIL_BRES_ERR
 
- TRAIL_BRES_INC
 
- TRAIL_BRES_T12_ERR_DEC
 
- TRAIL_BRES_T12_INC
 
- TRAIL_CNT_MAX
 
- TRAIL_COUNT_MASK
 
- TRAIL_COUNT_SHIFT
 
- TRAINING_PTN1
 
- TRAINING_PTN2
 
- TRAIN_DONE_D0
 
- TRAIN_DONE_D1
 
- TRAIN_TXEN
 
- TRAMPOLINE_32BIT_CODE_OFFSET
 
- TRAMPOLINE_32BIT_CODE_SIZE
 
- TRAMPOLINE_32BIT_PGTABLE_OFFSET
 
- TRAMPOLINE_32BIT_SIZE
 
- TRAMPOLINE_32BIT_STACK_END
 
- TRAMPOLINE_PHYS_HIGH
 
- TRAMPOLINE_PHYS_LOW
 
- TRAMP_FRAME_SIZE
 
- TRAMP_KVM_BEGIN
 
- TRAMP_REAL_BEGIN
 
- TRAMP_SIZE
 
- TRAMP_SLOT_0
 
- TRAMP_SLOT_1
 
- TRAMP_SLOT_2
 
- TRAMP_SLOT_3
 
- TRAMP_SLOT_4
 
- TRAMP_SLOT_5
 
- TRAMP_STACK_SIZE
 
- TRAMP_TEXT
 
- TRAMP_TRACEBACK
 
- TRAMP_VALIAS
 
- TRAMP_VIRT_BEGIN
 
- TRANCEVIBRATOR_PRODUCT_ID
 
- TRANCEVIBRATOR_VENDOR_ID
 
- TRANS
 
- TRANS2_FIND_FIRST
 
- TRANS2_FIND_NEXT
 
- TRANS2_GET_DFS_REFERRAL
 
- TRANS2_OPEN
 
- TRANS2_QUERY_FILE_INFORMATION
 
- TRANS2_QUERY_FS_INFORMATION
 
- TRANS2_QUERY_PATH_INFORMATION
 
- TRANS2_REPORT_DFS_INCOSISTENCY
 
- TRANS2_SET_FILE_INFORMATION
 
- TRANS2_SET_FS_INFORMATION
 
- TRANS2_SET_PATH_INFORMATION
 
- TRANSACTION2_FFIRST_REQ
 
- TRANSACTION2_FFIRST_RSP
 
- TRANSACTION2_FNEXT_REQ
 
- TRANSACTION2_FNEXT_RSP
 
- TRANSACTION2_GET_DFS_REFER_REQ
 
- TRANSACTION2_GET_DFS_REFER_RSP
 
- TRANSACTION2_QFSI_REQ
 
- TRANSACTION2_QFSI_RSP
 
- TRANSACTION2_QPI_REQ
 
- TRANSACTION2_QPI_RSP
 
- TRANSACTION2_SETFSI_ENC_REQ
 
- TRANSACTION2_SETFSI_REQ
 
- TRANSACTION2_SETFSI_RSP
 
- TRANSACTION2_SPI_REQ
 
- TRANSACTION2_SPI_RSP
 
- TRANSACTION_DONE
 
- TRANSACTION_FAIL
 
- TRANSACTION_TIMEOUT_IN_I2C_CLOCKS
 
- TRANSACT_CHANGE_NOTIFY_REQ
 
- TRANSACT_CHANGE_NOTIFY_RSP
 
- TRANSACT_COMPR_IOCTL_REQ
 
- TRANSACT_IOCTL_REQ
 
- TRANSACT_IOCTL_RSP
 
- TRANSCEIVEA_HSPI_READBACK
 
- TRANSCEIVEB_HSPI_READBACK
 
- TRANSCEIVERA_HSPI_READBACK
 
- TRANSCEIVERB_HSPI_READBACK
 
- TRANSCEIVER_LVD
 
- TRANSCEIVER_OPERATION_MODE
 
- TRANSCEIVER_SE
 
- TRANSCEIVER_SELECT
 
- TRANSCFG
 
- TRANSCFG_ATT
 
- TRANSCFG_RX_WATER_MARK
 
- TRANSCFG_SID_FALCON
 
- TRANSCFG_SID_HW
 
- TRANSCFG_SID_PHY
 
- TRANSCODER_A
 
- TRANSCODER_A_OFFSET
 
- TRANSCODER_B
 
- TRANSCODER_B_OFFSET
 
- TRANSCODER_C
 
- TRANSCODER_C_OFFSET
 
- TRANSCODER_D
 
- TRANSCODER_DSI0_OFFSET
 
- TRANSCODER_DSI1_OFFSET
 
- TRANSCODER_DSI_0
 
- TRANSCODER_DSI_1
 
- TRANSCODER_DSI_A
 
- TRANSCODER_DSI_C
 
- TRANSCODER_D_OFFSET
 
- TRANSCODER_EDP
 
- TRANSCODER_EDP_OFFSET
 
- TRANSFERCOUNT
 
- TRANSFERMODE
 
- TRANSFERRED_1024_BYTES
 
- TRANSFERRED_128_BYTES
 
- TRANSFERRED_2048_BYTES
 
- TRANSFERRED_256_BYTES
 
- TRANSFERRED_4096_BYTES
 
- TRANSFERRED_512_BYTES
 
- TRANSFERRED_64_BYTES
 
- TRANSFERRED_8192_BYTES
 
- TRANSFER_CONTROL
 
- TRANSFER_COUNT
 
- TRANSFER_COUNT_GET_HCOUNT
 
- TRANSFER_COUNT_GET_VCOUNT
 
- TRANSFER_COUNT_SET_HCOUNT
 
- TRANSFER_COUNT_SET_VCOUNT
 
- TRANSFER_DELAY_TICKS
 
- TRANSFER_DIRECTION
 
- TRANSFER_DIR_WRITE
 
- TRANSFER_DONE
 
- TRANSFER_DOUBLE
 
- TRANSFER_EXTENDED
 
- TRANSFER_FRAGMENT
 
- TRANSFER_FUNCTION_BT709
 
- TRANSFER_FUNCTION_GAMMA22
 
- TRANSFER_FUNCTION_GAMMA24
 
- TRANSFER_FUNCTION_GAMMA26
 
- TRANSFER_FUNCTION_HLG
 
- TRANSFER_FUNCTION_HLG12
 
- TRANSFER_FUNCTION_LINEAR
 
- TRANSFER_FUNCTION_PQ
 
- TRANSFER_FUNCTION_SRGB
 
- TRANSFER_FUNCTION_UNITY
 
- TRANSFER_FUNC_BT709
 
- TRANSFER_FUNC_GAMMA_22
 
- TRANSFER_FUNC_GAMMA_26
 
- TRANSFER_FUNC_LINEAR_0_1
 
- TRANSFER_FUNC_LINEAR_0_125
 
- TRANSFER_FUNC_POINTS
 
- TRANSFER_FUNC_PQ2084
 
- TRANSFER_FUNC_PQ2084_INTERIM
 
- TRANSFER_FUNC_SRGB
 
- TRANSFER_FUNC_UNKNOWN
 
- TRANSFER_GO
 
- TRANSFER_INFO
 
- TRANSFER_LENGTH
 
- TRANSFER_MODE
 
- TRANSFER_MODE__VALUE
 
- TRANSFER_MULTI
 
- TRANSFER_PACKED
 
- TRANSFER_PAD
 
- TRANSFER_READ
 
- TRANSFER_READY
 
- TRANSFER_SINGLE
 
- TRANSFER_SIZE
 
- TRANSFER_SIZE_CONTROL
 
- TRANSFER_SPARE_REG
 
- TRANSFER_SPARE_REG__FLAG
 
- TRANSFER_START
 
- TRANSFER_STATUS
 
- TRANSFER_TIMEOUT
 
- TRANSFER_TYPE
 
- TRANSFER_WIDTH
 
- TRANSFER_WRITE
 
- TRANSHDR_SIZE
 
- TRANSHUGE_PAGE_DTOR
 
- TRANSITION_LATENCY
 
- TRANSIT_TO
 
- TRANSLATE_ERROR
 
- TRANSMISSION_MODE_16K
 
- TRANSMISSION_MODE_1K
 
- TRANSMISSION_MODE_2K
 
- TRANSMISSION_MODE_32K
 
- TRANSMISSION_MODE_4K
 
- TRANSMISSION_MODE_8K
 
- TRANSMISSION_MODE_AUTO
 
- TRANSMISSION_MODE_C1
 
- TRANSMISSION_MODE_C3780
 
- TRANSMITTER_ACTION
 
- TRANSMITTER_COLOR_DEPTH_24
 
- TRANSMITTER_COLOR_DEPTH_30
 
- TRANSMITTER_COLOR_DEPTH_36
 
- TRANSMITTER_COLOR_DEPTH_48
 
- TRANSMITTER_CONTROL_ACTIAVATE
 
- TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS
 
- TRANSMITTER_CONTROL_BACKLIGHT_OFF
 
- TRANSMITTER_CONTROL_BACKLIGHT_ON
 
- TRANSMITTER_CONTROL_DEACTIVATE
 
- TRANSMITTER_CONTROL_DISABLE
 
- TRANSMITTER_CONTROL_ENABLE
 
- TRANSMITTER_CONTROL_INIT
 
- TRANSMITTER_CONTROL_LCD_SELF_TEST_STOP
 
- TRANSMITTER_CONTROL_LCD_SETF_TEST_START
 
- TRANSMITTER_CONTROL_POWER_OFF
 
- TRANSMITTER_CONTROL_POWER_ON
 
- TRANSMITTER_CONTROL_SETUP
 
- TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS
 
- TRANSMITTER_COUNT
 
- TRANSMITTER_NUTMEG_CRT
 
- TRANSMITTER_TRAVIS_CRT
 
- TRANSMITTER_TRAVIS_LCD
 
- TRANSMITTER_UNIPHY_A
 
- TRANSMITTER_UNIPHY_B
 
- TRANSMITTER_UNIPHY_C
 
- TRANSMITTER_UNIPHY_D
 
- TRANSMITTER_UNIPHY_E
 
- TRANSMITTER_UNIPHY_F
 
- TRANSMITTER_UNIPHY_G
 
- TRANSMITTER_UNKNOWN
 
- TRANSMIT_DATA
 
- TRANSMIT_DONE
 
- TRANSMIT_KEY
 
- TRANSMIT_STATUS
 
- TRANSMIT_TIMING_MARKER
 
- TRANSNAMSIZ
 
- TRANSP
 
- TRANSPARENT
 
- TRANSPARENT_BITBLT
 
- TRANSPARENT_HUGEPAGE_DEBUG_COW_FLAG
 
- TRANSPARENT_HUGEPAGE_DEFRAG_DIRECT_FLAG
 
- TRANSPARENT_HUGEPAGE_DEFRAG_KHUGEPAGED_FLAG
 
- TRANSPARENT_HUGEPAGE_DEFRAG_KSWAPD_FLAG
 
- TRANSPARENT_HUGEPAGE_DEFRAG_KSWAPD_OR_MADV_FLAG
 
- TRANSPARENT_HUGEPAGE_DEFRAG_REQ_MADV_FLAG
 
- TRANSPARENT_HUGEPAGE_FLAG
 
- TRANSPARENT_HUGEPAGE_REQ_MADV_FLAG
 
- TRANSPARENT_HUGEPAGE_USE_ZERO_PAGE_FLAG
 
- TRANSPARENT_I2C_EN
 
- TRANSPORT_COMPLETE
 
- TRANSPORT_COMPLETE_QF_ERR
 
- TRANSPORT_COMPLETE_QF_OK
 
- TRANSPORT_COMPLETE_QF_WP
 
- TRANSPORT_CTL
 
- TRANSPORT_ENB
 
- TRANSPORT_ERROR
 
- TRANSPORT_FAILED
 
- TRANSPORT_FLAG_PASSTHROUGH
 
- TRANSPORT_FLAG_PASSTHROUGH_ALUA
 
- TRANSPORT_FLAG_PASSTHROUGH_PGR
 
- TRANSPORT_GOOD
 
- TRANSPORT_INFO_IPV4_TCP
 
- TRANSPORT_INFO_IPV4_UDP
 
- TRANSPORT_INFO_IPV6_TCP
 
- TRANSPORT_INFO_IPV6_UDP
 
- TRANSPORT_INFO_NOT_IP
 
- TRANSPORT_INT
 
- TRANSPORT_IQN_LEN
 
- TRANSPORT_ISTATE_PROCESSING
 
- TRANSPORT_NEW_CMD
 
- TRANSPORT_NO_SENSE
 
- TRANSPORT_NO_STATE
 
- TRANSPORT_OFFSET
 
- TRANSPORT_PROBLEM
 
- TRANSPORT_PROCESSING
 
- TRANSPORT_SENSE_BUFFER
 
- TRANSPORT_SPECIFIC_MASK
 
- TRANSPORT_SPECIFIC_SHIFT
 
- TRANSPORT_TUNTAP_MTU
 
- TRANSPORT_TUNTAP_NAME
 
- TRANSPORT_WRITE_PENDING
 
- TRANSSTATUS
 
- TRANS_10BPC
 
- TRANS_12BPC
 
- TRANS_6BPC
 
- TRANS_8BPC
 
- TRANS_ABORT
 
- TRANS_ATTACH
 
- TRANS_BESS
 
- TRANS_BESS_LEN
 
- TRANS_CALL_NMPIPE
 
- TRANS_CHICKEN1
 
- TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
 
- TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE
 
- TRANS_CHICKEN2
 
- TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
 
- TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
 
- TRANS_CHICKEN2_FDI_POLARITY_REVERSED
 
- TRANS_CHICKEN2_FRAME_START_DELAY_MASK
 
- TRANS_CHICKEN2_TIMING_OVERRIDE
 
- TRANS_CLK_SEL
 
- TRANS_CLK_SEL_DISABLED
 
- TRANS_CLK_SEL_PORT
 
- TRANS_CORRUPT_MASK
 
- TRANS_DDI_BFI_ENABLE
 
- TRANS_DDI_BPC_10
 
- TRANS_DDI_BPC_12
 
- TRANS_DDI_BPC_6
 
- TRANS_DDI_BPC_8
 
- TRANS_DDI_BPC_MASK
 
- TRANS_DDI_DP_VC_PAYLOAD_ALLOC
 
- TRANS_DDI_EDP_INPUT_A_ON
 
- TRANS_DDI_EDP_INPUT_A_ONOFF
 
- TRANS_DDI_EDP_INPUT_B_ONOFF
 
- TRANS_DDI_EDP_INPUT_C_ONOFF
 
- TRANS_DDI_EDP_INPUT_MASK
 
- TRANS_DDI_FUNC_CTL
 
- TRANS_DDI_FUNC_CTL2
 
- TRANS_DDI_FUNC_CTL_VAL_TO_PORT
 
- TRANS_DDI_FUNC_ENABLE
 
- TRANS_DDI_HDCP_SIGNALLING
 
- TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE
 
- TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ
 
- TRANS_DDI_HDMI_SCRAMBLING
 
- TRANS_DDI_HDMI_SCRAMBLING_MASK
 
- TRANS_DDI_HIGH_TMDS_CHAR_RATE
 
- TRANS_DDI_MODE_SELECT_DP_MST
 
- TRANS_DDI_MODE_SELECT_DP_SST
 
- TRANS_DDI_MODE_SELECT_DVI
 
- TRANS_DDI_MODE_SELECT_FDI
 
- TRANS_DDI_MODE_SELECT_HDMI
 
- TRANS_DDI_MODE_SELECT_MASK
 
- TRANS_DDI_PHSYNC
 
- TRANS_DDI_PORT_MASK
 
- TRANS_DDI_PORT_SHIFT
 
- TRANS_DDI_PVSYNC
 
- TRANS_DDI_SELECT_PORT
 
- TRANS_DIR_INO
 
- TRANS_DISABLE
 
- TRANS_DISCARD
 
- TRANS_DPLLA_SEL
 
- TRANS_DPLLB_SEL
 
- TRANS_DPLL_ENABLE
 
- TRANS_DP_10BPC
 
- TRANS_DP_12BPC
 
- TRANS_DP_6BPC
 
- TRANS_DP_8BPC
 
- TRANS_DP_AUDIO_ONLY
 
- TRANS_DP_BPC_MASK
 
- TRANS_DP_CTL
 
- TRANS_DP_ENH_FRAMING
 
- TRANS_DP_HSYNC_ACTIVE_HIGH
 
- TRANS_DP_HSYNC_ACTIVE_LOW
 
- TRANS_DP_OUTPUT_ENABLE
 
- TRANS_DP_PORT_SEL
 
- TRANS_DP_PORT_SEL_MASK
 
- TRANS_DP_PORT_SEL_NONE
 
- TRANS_DP_SYNC_MASK
 
- TRANS_DP_VSYNC_ACTIVE_HIGH
 
- TRANS_DP_VSYNC_ACTIVE_LOW
 
- TRANS_DST_KEY_HIGH
 
- TRANS_DST_KEY_LOW
 
- TRANS_ENABLE
 
- TRANS_ERROR
 
- TRANS_EVENT
 
- TRANS_EXTWRITERS
 
- TRANS_FAIL
 
- TRANS_FAIL_INT
 
- TRANS_FAIL_INT_EN
 
- TRANS_FSYNC_DELAY_HB1
 
- TRANS_FSYNC_DELAY_HB2
 
- TRANS_FSYNC_DELAY_HB3
 
- TRANS_FSYNC_DELAY_HB4
 
- TRANS_GRE
 
- TRANS_GRE_LEN
 
- TRANS_HACTIVE_SHIFT
 
- TRANS_HBLANK_END_SHIFT
 
- TRANS_HBLANK_START_SHIFT
 
- TRANS_HSYNC_END_SHIFT
 
- TRANS_HSYNC_START_SHIFT
 
- TRANS_HTOTAL_SHIFT
 
- TRANS_HYBRID
 
- TRANS_HYBRID_LEN
 
- TRANS_INPROGRESS
 
- TRANS_INTERLACED
 
- TRANS_INTERLACE_MASK
 
- TRANS_JOIN
 
- TRANS_JOIN_NOLOCK
 
- TRANS_JOIN_NOSTART
 
- TRANS_L2TPV3
 
- TRANS_L2TPV3_LEN
 
- TRANS_LEGACY_INTERLACED_ILK
 
- TRANS_LEN_MSK
 
- TRANS_MASK_HIGH
 
- TRANS_MASK_LOW
 
- TRANS_MODE_2K
 
- TRANS_MODE_4K
 
- TRANS_MODE_8K
 
- TRANS_MODE_EDMAC
 
- TRANS_MODE_IDMAC
 
- TRANS_MODE_PIO
 
- TRANS_MODE_UNKNOWN
 
- TRANS_MSA_10_BPC
 
- TRANS_MSA_12_BPC
 
- TRANS_MSA_16_BPC
 
- TRANS_MSA_6_BPC
 
- TRANS_MSA_8_BPC
 
- TRANS_MSA_CEA_RANGE
 
- TRANS_MSA_CLRSP_YCBCR
 
- TRANS_MSA_MISC
 
- TRANS_MSA_SAMPLING_444
 
- TRANS_MSA_SYNC_CLK
 
- TRANS_MSA_USE_VSC_SDP
 
- TRANS_NOT_READY
 
- TRANS_NO_DEVICE
 
- TRANS_OK
 
- TRANS_OK_INT
 
- TRANS_OK_INT_EN
 
- TRANS_PEEK_NMPIPE
 
- TRANS_PRIO
 
- TRANS_PRIV
 
- TRANS_PROGRESSIVE
 
- TRANS_QUERY_NMPIPE_INFO
 
- TRANS_QUERY_NMPIPE_STATE
 
- TRANS_QUEUED
 
- TRANS_RAW
 
- TRANS_RAW_LEN
 
- TRANS_RAW_READ_NMPIPE
 
- TRANS_RAW_WRITE_NMPIPE
 
- TRANS_READ_NMPIPE
 
- TRANS_RESULT_FAIL
 
- TRANS_RESULT_OK
 
- TRANS_RUNNING
 
- TRANS_RX_BAD_FRAME_TYPE_ERR
 
- TRANS_RX_BAD_HASH_ERR
 
- TRANS_RX_BREAK_RECEIVE_ERR
 
- TRANS_RX_BREAK_REQUEST_ERR
 
- TRANS_RX_BREAK_TIMEOUT_ERR
 
- TRANS_RX_CLOSE_NORMAL_ERR
 
- TRANS_RX_CLOSE_PHYRESET_ERR
 
- TRANS_RX_CLOSE_TIMEOUT_ERR
 
- TRANS_RX_DATA_LENGTH0_ERR
 
- TRANS_RX_ERR
 
- TRANS_RX_ERR_WITH_BAD_FRM_TYPE
 
- TRANS_RX_ERR_WITH_BAD_HASH
 
- TRANS_RX_ERR_WITH_BREAK_RECEVIED
 
- TRANS_RX_ERR_WITH_BREAK_REQUEST
 
- TRANS_RX_ERR_WITH_BREAK_TIMEOUT
 
- TRANS_RX_ERR_WITH_CLOSE_COMINIT
 
- TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT
 
- TRANS_RX_ERR_WITH_CLOSE_NORMAL
 
- TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE
 
- TRANS_RX_ERR_WITH_DATA_LEN0
 
- TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN
 
- TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR
 
- TRANS_RX_ERR_WITH_RXFIS_CRC_ERR
 
- TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR
 
- TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP
 
- TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR
 
- TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM
 
- TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN
 
- TRANS_RX_FAIL_BASE
 
- TRANS_RX_FRAME_CRC_ERR
 
- TRANS_RX_FRAME_DONE_ERR
 
- TRANS_RX_FRAME_ERRPRM_ERR
 
- TRANS_RX_FRAME_NO_CREDIT_ERR
 
- TRANS_RX_FRAME_NO_EOF_ERR
 
- TRANS_RX_FRAME_OVERRUN_ERR
 
- TRANS_RX_LINK_BUF_OVERRUN_ERR
 
- TRANS_RX_NO_BALANCE_ERR
 
- TRANS_RX_RSVD0_ERR
 
- TRANS_RX_R_ERR
 
- TRANS_RX_SMP_FRAME_LEN_ERR
 
- TRANS_RX_SMP_FRM_LEN_ERR
 
- TRANS_RX_SMP_RESP_TIMEOUT_ERR
 
- TRANS_RX_SSP_FRAME_LEN_ERR
 
- TRANS_RX_SSP_FRM_LEN_ERR
 
- TRANS_RX_TRANS_RX_RSVD1_ERR
 
- TRANS_RX_TRANS_RX_RSVD2_ERR
 
- TRANS_RX_TRANS_RX_RSVD3_ERR
 
- TRANS_RX_WITH_CLOSE_COMINIT_ERR
 
- TRANS_RX_WITH_CLOSE_DWS_TIMEOUT_ERR
 
- TRANS_RX_XRDY_WLEN_ZERO_ERR
 
- TRANS_RX_XRDY_ZERO_ERR
 
- TRANS_SCRMBL1
 
- TRANS_SCRMBL2
 
- TRANS_SET_NMPIPE_STATE
 
- TRANS_SMPL_WIDTH_16
 
- TRANS_SMPL_WIDTH_24
 
- TRANS_SMPL_WIDTH_32
 
- TRANS_SPARE_OFFSET
 
- TRANS_SRC_KEY_HIGH
 
- TRANS_SRC_KEY_LOW
 
- TRANS_START
 
- TRANS_STATE_BLOCKED
 
- TRANS_STATE_COMMIT_DOING
 
- TRANS_STATE_COMMIT_START
 
- TRANS_STATE_COMPLETED
 
- TRANS_STATE_DISABLE
 
- TRANS_STATE_ENABLE
 
- TRANS_STATE_MASK
 
- TRANS_STATE_MAX
 
- TRANS_STATE_RUNNING
 
- TRANS_STATE_UNBLOCKED
 
- TRANS_STATUS_BREAK_CS_CHANGE
 
- TRANS_STATUS_BREAK_DELAY
 
- TRANS_STATUS_BREAK_DESELECT
 
- TRANS_STATUS_BREAK_EOM
 
- TRANS_STATUS_BREAK_NONE
 
- TRANS_STATUS_BREAK_NO_BYTES
 
- TRANS_STATUS_BREAK_TX
 
- TRANS_TAP
 
- TRANS_TAP_LEN
 
- TRANS_TARGET_PERIOD
 
- TRANS_TRANSACT_NMPIPE
 
- TRANS_TRUE
 
- TRANS_TRUE_SIZE
 
- TRANS_TX_ACK_NAK_TIMEOUT_ERR
 
- TRANS_TX_BREAK_RECEIVE_ERR
 
- TRANS_TX_BREAK_REQUEST_ERR
 
- TRANS_TX_BREAK_TIMEOUT_ERR
 
- TRANS_TX_CLOSE_NORMAL_ERR
 
- TRANS_TX_CLOSE_PHYRESET_ERR
 
- TRANS_TX_CLOSE_TIMEOUT_ERR
 
- TRANS_TX_CREDIT_TIMEOUT_ERR
 
- TRANS_TX_ERR
 
- TRANS_TX_ERR_FRAME_TXED
 
- TRANS_TX_ERR_PHY_NOT_ENABLE
 
- TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT
 
- TRANS_TX_ERR_WITH_BREAK_RECEVIED
 
- TRANS_TX_ERR_WITH_BREAK_REQUEST
 
- TRANS_TX_ERR_WITH_BREAK_TIMEOUT
 
- TRANS_TX_ERR_WITH_CLOSE_COMINIT
 
- TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT
 
- TRANS_TX_ERR_WITH_CLOSE_NORMAL
 
- TRANS_TX_ERR_WITH_CLOSE_PHYDISALE
 
- TRANS_TX_ERR_WITH_CLOSE_TIMEOUT
 
- TRANS_TX_ERR_WITH_CREDIT_TIMEOUT
 
- TRANS_TX_ERR_WITH_IPTT_CONFLICT
 
- TRANS_TX_ERR_WITH_NAK_RECEVIED
 
- TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS
 
- TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT
 
- TRANS_TX_FAIL_BASE
 
- TRANS_TX_IPTT_CONFLICT_ERR
 
- TRANS_TX_LOW_PHY_POWER_ERR
 
- TRANS_TX_NAK_RECEIVE_ERR
 
- TRANS_TX_OPEN_BREAK_RECEIVE_ERR
 
- TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT
 
- TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION
 
- TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD
 
- TRANS_TX_OPEN_CNX_ERR_BY_OTHER
 
- TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED
 
- TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER
 
- TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION
 
- TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT
 
- TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED
 
- TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED
 
- TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY
 
- TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION
 
- TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION
 
- TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS
 
- TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR
 
- TRANS_TX_OPEN_REJCT_BAD_DEST_ERR
 
- TRANS_TX_OPEN_REJCT_BY_OTHER_ERR
 
- TRANS_TX_OPEN_REJCT_NO_DEST_ERR
 
- TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR
 
- TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR
 
- TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR
 
- TRANS_TX_OPEN_REJCT_STP_BUSY_ERR
 
- TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR
 
- TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR
 
- TRANS_TX_OPEN_RETRY_ERR
 
- TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED
 
- TRANS_TX_OPEN_TIMEOUT_ERR
 
- TRANS_TX_PHY_NOT_ENABLE_ERR
 
- TRANS_TX_RSVD0_ERR
 
- TRANS_TX_RSVD1_ERR
 
- TRANS_TX_RSVD2_ERR
 
- TRANS_TX_TXFRM_TYPE_ERR
 
- TRANS_TX_TXSMP_LENGTH_ERR
 
- TRANS_TX_WITH_CLOSE_COMINIT_ERR
 
- TRANS_TX_WITH_CLOSE_DWS_TIMEOUT_ERR
 
- TRANS_VACTIVE_SHIFT
 
- TRANS_VBLANK_END_SHIFT
 
- TRANS_VBLANK_START_SHIFT
 
- TRANS_VSYNC_END_SHIFT
 
- TRANS_VSYNC_START_SHIFT
 
- TRANS_VTOTAL_SHIFT
 
- TRANS_WAIT_NMPIPE
 
- TRANS_WRITE_NMPIPE
 
- TRAN_COAL_CAUSE_HI
 
- TRAN_COAL_CAUSE_LO
 
- TRAN_COAL_HI_DONE
 
- TRAN_COAL_LO_DONE
 
- TRAN_DATA
 
- TRAN_SELECT
 
- TRAP
 
- TRAP0_ADDRESS_HI_MASK__Trap0AddrHiMask_MASK
 
- TRAP0_ADDRESS_HI_MASK__Trap0AddrHiMask__SHIFT
 
- TRAP0_ADDRESS_HI__Trap0AddrHi_MASK
 
- TRAP0_ADDRESS_HI__Trap0AddrHi__SHIFT
 
- TRAP0_ADDRESS_LO_MASK__Trap0AddrLoMask_MASK
 
- TRAP0_ADDRESS_LO_MASK__Trap0AddrLoMask__SHIFT
 
- TRAP0_ADDRESS_LO__Trap0AddrLo_MASK
 
- TRAP0_ADDRESS_LO__Trap0AddrLo__SHIFT
 
- TRAP0_COMMAND_MASK__Trap0Cmd0Mask_MASK
 
- TRAP0_COMMAND_MASK__Trap0Cmd0Mask__SHIFT
 
- TRAP0_COMMAND_MASK__Trap0Cmd1Mask_MASK
 
- TRAP0_COMMAND_MASK__Trap0Cmd1Mask__SHIFT
 
- TRAP0_COMMAND__Trap0Cmd0_MASK
 
- TRAP0_COMMAND__Trap0Cmd0__SHIFT
 
- TRAP0_COMMAND__Trap0Cmd1_MASK
 
- TRAP0_COMMAND__Trap0Cmd1__SHIFT
 
- TRAP0_CONTROL0__Trap0CrossTrigger_MASK
 
- TRAP0_CONTROL0__Trap0CrossTrigger__SHIFT
 
- TRAP0_CONTROL0__Trap0En_MASK
 
- TRAP0_CONTROL0__Trap0En__SHIFT
 
- TRAP0_CONTROL0__Trap0SMUIntr_MASK
 
- TRAP0_CONTROL0__Trap0SMUIntr__SHIFT
 
- TRAP0_SIZE
 
- TRAP0_VEC
 
- TRAP10_ADDRESS_HI_MASK__Trap10AddrHiMask_MASK
 
- TRAP10_ADDRESS_HI_MASK__Trap10AddrHiMask__SHIFT
 
- TRAP10_ADDRESS_HI__Trap10AddrHi_MASK
 
- TRAP10_ADDRESS_HI__Trap10AddrHi__SHIFT
 
- TRAP10_ADDRESS_LO_MASK__Trap10AddrLoMask_MASK
 
- TRAP10_ADDRESS_LO_MASK__Trap10AddrLoMask__SHIFT
 
- TRAP10_ADDRESS_LO__Trap10AddrLo_MASK
 
- TRAP10_ADDRESS_LO__Trap10AddrLo__SHIFT
 
- TRAP10_COMMAND_MASK__Trap10Cmd0Mask_MASK
 
- TRAP10_COMMAND_MASK__Trap10Cmd0Mask__SHIFT
 
- TRAP10_COMMAND_MASK__Trap10Cmd1Mask_MASK
 
- TRAP10_COMMAND_MASK__Trap10Cmd1Mask__SHIFT
 
- TRAP10_COMMAND__Trap10Cmd0_MASK
 
- TRAP10_COMMAND__Trap10Cmd0__SHIFT
 
- TRAP10_COMMAND__Trap10Cmd1_MASK
 
- TRAP10_COMMAND__Trap10Cmd1__SHIFT
 
- TRAP10_CONTROL0__Trap10CrossTrigger_MASK
 
- TRAP10_CONTROL0__Trap10CrossTrigger__SHIFT
 
- TRAP10_CONTROL0__Trap10En_MASK
 
- TRAP10_CONTROL0__Trap10En__SHIFT
 
- TRAP10_CONTROL0__Trap10SMUIntr_MASK
 
- TRAP10_CONTROL0__Trap10SMUIntr__SHIFT
 
- TRAP11_ADDRESS_HI_MASK__Trap11AddrHiMask_MASK
 
- TRAP11_ADDRESS_HI_MASK__Trap11AddrHiMask__SHIFT
 
- TRAP11_ADDRESS_HI__Trap11AddrHi_MASK
 
- TRAP11_ADDRESS_HI__Trap11AddrHi__SHIFT
 
- TRAP11_ADDRESS_LO_MASK__Trap11AddrLoMask_MASK
 
- TRAP11_ADDRESS_LO_MASK__Trap11AddrLoMask__SHIFT
 
- TRAP11_ADDRESS_LO__Trap11AddrLo_MASK
 
- TRAP11_ADDRESS_LO__Trap11AddrLo__SHIFT
 
- TRAP11_COMMAND_MASK__Trap11Cmd0Mask_MASK
 
- TRAP11_COMMAND_MASK__Trap11Cmd0Mask__SHIFT
 
- TRAP11_COMMAND_MASK__Trap11Cmd1Mask_MASK
 
- TRAP11_COMMAND_MASK__Trap11Cmd1Mask__SHIFT
 
- TRAP11_COMMAND__Trap11Cmd0_MASK
 
- TRAP11_COMMAND__Trap11Cmd0__SHIFT
 
- TRAP11_COMMAND__Trap11Cmd1_MASK
 
- TRAP11_COMMAND__Trap11Cmd1__SHIFT
 
- TRAP11_CONTROL0__Trap11CrossTrigger_MASK
 
- TRAP11_CONTROL0__Trap11CrossTrigger__SHIFT
 
- TRAP11_CONTROL0__Trap11En_MASK
 
- TRAP11_CONTROL0__Trap11En__SHIFT
 
- TRAP11_CONTROL0__Trap11SMUIntr_MASK
 
- TRAP11_CONTROL0__Trap11SMUIntr__SHIFT
 
- TRAP12_ADDRESS_HI_MASK__Trap12AddrHiMask_MASK
 
- TRAP12_ADDRESS_HI_MASK__Trap12AddrHiMask__SHIFT
 
- TRAP12_ADDRESS_HI__Trap12AddrHi_MASK
 
- TRAP12_ADDRESS_HI__Trap12AddrHi__SHIFT
 
- TRAP12_ADDRESS_LO_MASK__Trap12AddrLoMask_MASK
 
- TRAP12_ADDRESS_LO_MASK__Trap12AddrLoMask__SHIFT
 
- TRAP12_ADDRESS_LO__Trap12AddrLo_MASK
 
- TRAP12_ADDRESS_LO__Trap12AddrLo__SHIFT
 
- TRAP12_COMMAND_MASK__Trap12Cmd0Mask_MASK
 
- TRAP12_COMMAND_MASK__Trap12Cmd0Mask__SHIFT
 
- TRAP12_COMMAND_MASK__Trap12Cmd1Mask_MASK
 
- TRAP12_COMMAND_MASK__Trap12Cmd1Mask__SHIFT
 
- TRAP12_COMMAND__Trap12Cmd0_MASK
 
- TRAP12_COMMAND__Trap12Cmd0__SHIFT
 
- TRAP12_COMMAND__Trap12Cmd1_MASK
 
- TRAP12_COMMAND__Trap12Cmd1__SHIFT
 
- TRAP12_CONTROL0__Trap12CrossTrigger_MASK
 
- TRAP12_CONTROL0__Trap12CrossTrigger__SHIFT
 
- TRAP12_CONTROL0__Trap12En_MASK
 
- TRAP12_CONTROL0__Trap12En__SHIFT
 
- TRAP12_CONTROL0__Trap12SMUIntr_MASK
 
- TRAP12_CONTROL0__Trap12SMUIntr__SHIFT
 
- TRAP13_ADDRESS_HI_MASK__Trap13AddrHiMask_MASK
 
- TRAP13_ADDRESS_HI_MASK__Trap13AddrHiMask__SHIFT
 
- TRAP13_ADDRESS_HI__Trap13AddrHi_MASK
 
- TRAP13_ADDRESS_HI__Trap13AddrHi__SHIFT
 
- TRAP13_ADDRESS_LO_MASK__Trap13AddrLoMask_MASK
 
- TRAP13_ADDRESS_LO_MASK__Trap13AddrLoMask__SHIFT
 
- TRAP13_ADDRESS_LO__Trap13AddrLo_MASK
 
- TRAP13_ADDRESS_LO__Trap13AddrLo__SHIFT
 
- TRAP13_COMMAND_MASK__Trap13Cmd0Mask_MASK
 
- TRAP13_COMMAND_MASK__Trap13Cmd0Mask__SHIFT
 
- TRAP13_COMMAND_MASK__Trap13Cmd1Mask_MASK
 
- TRAP13_COMMAND_MASK__Trap13Cmd1Mask__SHIFT
 
- TRAP13_COMMAND__Trap13Cmd0_MASK
 
- TRAP13_COMMAND__Trap13Cmd0__SHIFT
 
- TRAP13_COMMAND__Trap13Cmd1_MASK
 
- TRAP13_COMMAND__Trap13Cmd1__SHIFT
 
- TRAP13_CONTROL0__Trap13CrossTrigger_MASK
 
- TRAP13_CONTROL0__Trap13CrossTrigger__SHIFT
 
- TRAP13_CONTROL0__Trap13En_MASK
 
- TRAP13_CONTROL0__Trap13En__SHIFT
 
- TRAP13_CONTROL0__Trap13SMUIntr_MASK
 
- TRAP13_CONTROL0__Trap13SMUIntr__SHIFT
 
- TRAP14_ADDRESS_HI_MASK__Trap14AddrHiMask_MASK
 
- TRAP14_ADDRESS_HI_MASK__Trap14AddrHiMask__SHIFT
 
- TRAP14_ADDRESS_HI__Trap14AddrHi_MASK
 
- TRAP14_ADDRESS_HI__Trap14AddrHi__SHIFT
 
- TRAP14_ADDRESS_LO_MASK__Trap14AddrLoMask_MASK
 
- TRAP14_ADDRESS_LO_MASK__Trap14AddrLoMask__SHIFT
 
- TRAP14_ADDRESS_LO__Trap14AddrLo_MASK
 
- TRAP14_ADDRESS_LO__Trap14AddrLo__SHIFT
 
- TRAP14_COMMAND_MASK__Trap14Cmd0Mask_MASK
 
- TRAP14_COMMAND_MASK__Trap14Cmd0Mask__SHIFT
 
- TRAP14_COMMAND_MASK__Trap14Cmd1Mask_MASK
 
- TRAP14_COMMAND_MASK__Trap14Cmd1Mask__SHIFT
 
- TRAP14_COMMAND__Trap14Cmd0_MASK
 
- TRAP14_COMMAND__Trap14Cmd0__SHIFT
 
- TRAP14_COMMAND__Trap14Cmd1_MASK
 
- TRAP14_COMMAND__Trap14Cmd1__SHIFT
 
- TRAP14_CONTROL0__Trap14CrossTrigger_MASK
 
- TRAP14_CONTROL0__Trap14CrossTrigger__SHIFT
 
- TRAP14_CONTROL0__Trap14En_MASK
 
- TRAP14_CONTROL0__Trap14En__SHIFT
 
- TRAP14_CONTROL0__Trap14SMUIntr_MASK
 
- TRAP14_CONTROL0__Trap14SMUIntr__SHIFT
 
- TRAP15_ADDRESS_HI_MASK__Trap15AddrHiMask_MASK
 
- TRAP15_ADDRESS_HI_MASK__Trap15AddrHiMask__SHIFT
 
- TRAP15_ADDRESS_HI__Trap15AddrHi_MASK
 
- TRAP15_ADDRESS_HI__Trap15AddrHi__SHIFT
 
- TRAP15_ADDRESS_LO_MASK__Trap15AddrLoMask_MASK
 
- TRAP15_ADDRESS_LO_MASK__Trap15AddrLoMask__SHIFT
 
- TRAP15_ADDRESS_LO__Trap15AddrLo_MASK
 
- TRAP15_ADDRESS_LO__Trap15AddrLo__SHIFT
 
- TRAP15_COMMAND_MASK__Trap15Cmd0Mask_MASK
 
- TRAP15_COMMAND_MASK__Trap15Cmd0Mask__SHIFT
 
- TRAP15_COMMAND_MASK__Trap15Cmd1Mask_MASK
 
- TRAP15_COMMAND_MASK__Trap15Cmd1Mask__SHIFT
 
- TRAP15_COMMAND__Trap15Cmd0_MASK
 
- TRAP15_COMMAND__Trap15Cmd0__SHIFT
 
- TRAP15_COMMAND__Trap15Cmd1_MASK
 
- TRAP15_COMMAND__Trap15Cmd1__SHIFT
 
- TRAP15_CONTROL0__Trap15CrossTrigger_MASK
 
- TRAP15_CONTROL0__Trap15CrossTrigger__SHIFT
 
- TRAP15_CONTROL0__Trap15En_MASK
 
- TRAP15_CONTROL0__Trap15En__SHIFT
 
- TRAP15_CONTROL0__Trap15SMUIntr_MASK
 
- TRAP15_CONTROL0__Trap15SMUIntr__SHIFT
 
- TRAP1_ADDRESS_HI_MASK__Trap1AddrHiMask_MASK
 
- TRAP1_ADDRESS_HI_MASK__Trap1AddrHiMask__SHIFT
 
- TRAP1_ADDRESS_HI__Trap1AddrHi_MASK
 
- TRAP1_ADDRESS_HI__Trap1AddrHi__SHIFT
 
- TRAP1_ADDRESS_LO_MASK__Trap1AddrLoMask_MASK
 
- TRAP1_ADDRESS_LO_MASK__Trap1AddrLoMask__SHIFT
 
- TRAP1_ADDRESS_LO__Trap1AddrLo_MASK
 
- TRAP1_ADDRESS_LO__Trap1AddrLo__SHIFT
 
- TRAP1_COMMAND_MASK__Trap1Cmd0Mask_MASK
 
- TRAP1_COMMAND_MASK__Trap1Cmd0Mask__SHIFT
 
- TRAP1_COMMAND_MASK__Trap1Cmd1Mask_MASK
 
- TRAP1_COMMAND_MASK__Trap1Cmd1Mask__SHIFT
 
- TRAP1_COMMAND__Trap1Cmd0_MASK
 
- TRAP1_COMMAND__Trap1Cmd0__SHIFT
 
- TRAP1_COMMAND__Trap1Cmd1_MASK
 
- TRAP1_COMMAND__Trap1Cmd1__SHIFT
 
- TRAP1_CONTROL0__Trap1CrossTrigger_MASK
 
- TRAP1_CONTROL0__Trap1CrossTrigger__SHIFT
 
- TRAP1_CONTROL0__Trap1En_MASK
 
- TRAP1_CONTROL0__Trap1En__SHIFT
 
- TRAP1_CONTROL0__Trap1SMUIntr_MASK
 
- TRAP1_CONTROL0__Trap1SMUIntr__SHIFT
 
- TRAP1_VEC
 
- TRAP2_ADDRESS_HI_MASK__Trap2AddrHiMask_MASK
 
- TRAP2_ADDRESS_HI_MASK__Trap2AddrHiMask__SHIFT
 
- TRAP2_ADDRESS_HI__Trap2AddrHi_MASK
 
- TRAP2_ADDRESS_HI__Trap2AddrHi__SHIFT
 
- TRAP2_ADDRESS_LO_MASK__Trap2AddrLoMask_MASK
 
- TRAP2_ADDRESS_LO_MASK__Trap2AddrLoMask__SHIFT
 
- TRAP2_ADDRESS_LO__Trap2AddrLo_MASK
 
- TRAP2_ADDRESS_LO__Trap2AddrLo__SHIFT
 
- TRAP2_COMMAND_MASK__Trap2Cmd0Mask_MASK
 
- TRAP2_COMMAND_MASK__Trap2Cmd0Mask__SHIFT
 
- TRAP2_COMMAND_MASK__Trap2Cmd1Mask_MASK
 
- TRAP2_COMMAND_MASK__Trap2Cmd1Mask__SHIFT
 
- TRAP2_COMMAND__Trap2Cmd0_MASK
 
- TRAP2_COMMAND__Trap2Cmd0__SHIFT
 
- TRAP2_COMMAND__Trap2Cmd1_MASK
 
- TRAP2_COMMAND__Trap2Cmd1__SHIFT
 
- TRAP2_CONTROL0__Trap2CrossTrigger_MASK
 
- TRAP2_CONTROL0__Trap2CrossTrigger__SHIFT
 
- TRAP2_CONTROL0__Trap2En_MASK
 
- TRAP2_CONTROL0__Trap2En__SHIFT
 
- TRAP2_CONTROL0__Trap2SMUIntr_MASK
 
- TRAP2_CONTROL0__Trap2SMUIntr__SHIFT
 
- TRAP2_VEC
 
- TRAP3_ADDRESS_HI_MASK__Trap3AddrHiMask_MASK
 
- TRAP3_ADDRESS_HI_MASK__Trap3AddrHiMask__SHIFT
 
- TRAP3_ADDRESS_HI__Trap3AddrHi_MASK
 
- TRAP3_ADDRESS_HI__Trap3AddrHi__SHIFT
 
- TRAP3_ADDRESS_LO_MASK__Trap3AddrLoMask_MASK
 
- TRAP3_ADDRESS_LO_MASK__Trap3AddrLoMask__SHIFT
 
- TRAP3_ADDRESS_LO__Trap3AddrLo_MASK
 
- TRAP3_ADDRESS_LO__Trap3AddrLo__SHIFT
 
- TRAP3_COMMAND_MASK__Trap3Cmd0Mask_MASK
 
- TRAP3_COMMAND_MASK__Trap3Cmd0Mask__SHIFT
 
- TRAP3_COMMAND_MASK__Trap3Cmd1Mask_MASK
 
- TRAP3_COMMAND_MASK__Trap3Cmd1Mask__SHIFT
 
- TRAP3_COMMAND__Trap3Cmd0_MASK
 
- TRAP3_COMMAND__Trap3Cmd0__SHIFT
 
- TRAP3_COMMAND__Trap3Cmd1_MASK
 
- TRAP3_COMMAND__Trap3Cmd1__SHIFT
 
- TRAP3_CONTROL0__Trap3CrossTrigger_MASK
 
- TRAP3_CONTROL0__Trap3CrossTrigger__SHIFT
 
- TRAP3_CONTROL0__Trap3En_MASK
 
- TRAP3_CONTROL0__Trap3En__SHIFT
 
- TRAP3_CONTROL0__Trap3SMUIntr_MASK
 
- TRAP3_CONTROL0__Trap3SMUIntr__SHIFT
 
- TRAP3_VEC
 
- TRAP4_ADDRESS_HI_MASK__Trap4AddrHiMask_MASK
 
- TRAP4_ADDRESS_HI_MASK__Trap4AddrHiMask__SHIFT
 
- TRAP4_ADDRESS_HI__Trap4AddrHi_MASK
 
- TRAP4_ADDRESS_HI__Trap4AddrHi__SHIFT
 
- TRAP4_ADDRESS_LO_MASK__Trap4AddrLoMask_MASK
 
- TRAP4_ADDRESS_LO_MASK__Trap4AddrLoMask__SHIFT
 
- TRAP4_ADDRESS_LO__Trap4AddrLo_MASK
 
- TRAP4_ADDRESS_LO__Trap4AddrLo__SHIFT
 
- TRAP4_COMMAND_MASK__Trap4Cmd0Mask_MASK
 
- TRAP4_COMMAND_MASK__Trap4Cmd0Mask__SHIFT
 
- TRAP4_COMMAND_MASK__Trap4Cmd1Mask_MASK
 
- TRAP4_COMMAND_MASK__Trap4Cmd1Mask__SHIFT
 
- TRAP4_COMMAND__Trap4Cmd0_MASK
 
- TRAP4_COMMAND__Trap4Cmd0__SHIFT
 
- TRAP4_COMMAND__Trap4Cmd1_MASK
 
- TRAP4_COMMAND__Trap4Cmd1__SHIFT
 
- TRAP4_CONTROL0__Trap4CrossTrigger_MASK
 
- TRAP4_CONTROL0__Trap4CrossTrigger__SHIFT
 
- TRAP4_CONTROL0__Trap4En_MASK
 
- TRAP4_CONTROL0__Trap4En__SHIFT
 
- TRAP4_CONTROL0__Trap4SMUIntr_MASK
 
- TRAP4_CONTROL0__Trap4SMUIntr__SHIFT
 
- TRAP5_ADDRESS_HI_MASK__Trap5AddrHiMask_MASK
 
- TRAP5_ADDRESS_HI_MASK__Trap5AddrHiMask__SHIFT
 
- TRAP5_ADDRESS_HI__Trap5AddrHi_MASK
 
- TRAP5_ADDRESS_HI__Trap5AddrHi__SHIFT
 
- TRAP5_ADDRESS_LO_MASK__Trap5AddrLoMask_MASK
 
- TRAP5_ADDRESS_LO_MASK__Trap5AddrLoMask__SHIFT
 
- TRAP5_ADDRESS_LO__Trap5AddrLo_MASK
 
- TRAP5_ADDRESS_LO__Trap5AddrLo__SHIFT
 
- TRAP5_COMMAND_MASK__Trap5Cmd0Mask_MASK
 
- TRAP5_COMMAND_MASK__Trap5Cmd0Mask__SHIFT
 
- TRAP5_COMMAND_MASK__Trap5Cmd1Mask_MASK
 
- TRAP5_COMMAND_MASK__Trap5Cmd1Mask__SHIFT
 
- TRAP5_COMMAND__Trap5Cmd0_MASK
 
- TRAP5_COMMAND__Trap5Cmd0__SHIFT
 
- TRAP5_COMMAND__Trap5Cmd1_MASK
 
- TRAP5_COMMAND__Trap5Cmd1__SHIFT
 
- TRAP5_CONTROL0__Trap5CrossTrigger_MASK
 
- TRAP5_CONTROL0__Trap5CrossTrigger__SHIFT
 
- TRAP5_CONTROL0__Trap5En_MASK
 
- TRAP5_CONTROL0__Trap5En__SHIFT
 
- TRAP5_CONTROL0__Trap5SMUIntr_MASK
 
- TRAP5_CONTROL0__Trap5SMUIntr__SHIFT
 
- TRAP6_ADDRESS_HI_MASK__Trap6AddrHiMask_MASK
 
- TRAP6_ADDRESS_HI_MASK__Trap6AddrHiMask__SHIFT
 
- TRAP6_ADDRESS_HI__Trap6AddrHi_MASK
 
- TRAP6_ADDRESS_HI__Trap6AddrHi__SHIFT
 
- TRAP6_ADDRESS_LO_MASK__Trap6AddrLoMask_MASK
 
- TRAP6_ADDRESS_LO_MASK__Trap6AddrLoMask__SHIFT
 
- TRAP6_ADDRESS_LO__Trap6AddrLo_MASK
 
- TRAP6_ADDRESS_LO__Trap6AddrLo__SHIFT
 
- TRAP6_COMMAND_MASK__Trap6Cmd0Mask_MASK
 
- TRAP6_COMMAND_MASK__Trap6Cmd0Mask__SHIFT
 
- TRAP6_COMMAND_MASK__Trap6Cmd1Mask_MASK
 
- TRAP6_COMMAND_MASK__Trap6Cmd1Mask__SHIFT
 
- TRAP6_COMMAND__Trap6Cmd0_MASK
 
- TRAP6_COMMAND__Trap6Cmd0__SHIFT
 
- TRAP6_COMMAND__Trap6Cmd1_MASK
 
- TRAP6_COMMAND__Trap6Cmd1__SHIFT
 
- TRAP6_CONTROL0__Trap6CrossTrigger_MASK
 
- TRAP6_CONTROL0__Trap6CrossTrigger__SHIFT
 
- TRAP6_CONTROL0__Trap6En_MASK
 
- TRAP6_CONTROL0__Trap6En__SHIFT
 
- TRAP6_CONTROL0__Trap6SMUIntr_MASK
 
- TRAP6_CONTROL0__Trap6SMUIntr__SHIFT
 
- TRAP7_ADDRESS_HI_MASK__Trap7AddrHiMask_MASK
 
- TRAP7_ADDRESS_HI_MASK__Trap7AddrHiMask__SHIFT
 
- TRAP7_ADDRESS_HI__Trap7AddrHi_MASK
 
- TRAP7_ADDRESS_HI__Trap7AddrHi__SHIFT
 
- TRAP7_ADDRESS_LO_MASK__Trap7AddrLoMask_MASK
 
- TRAP7_ADDRESS_LO_MASK__Trap7AddrLoMask__SHIFT
 
- TRAP7_ADDRESS_LO__Trap7AddrLo_MASK
 
- TRAP7_ADDRESS_LO__Trap7AddrLo__SHIFT
 
- TRAP7_COMMAND_MASK__Trap7Cmd0Mask_MASK
 
- TRAP7_COMMAND_MASK__Trap7Cmd0Mask__SHIFT
 
- TRAP7_COMMAND_MASK__Trap7Cmd1Mask_MASK
 
- TRAP7_COMMAND_MASK__Trap7Cmd1Mask__SHIFT
 
- TRAP7_COMMAND__Trap7Cmd0_MASK
 
- TRAP7_COMMAND__Trap7Cmd0__SHIFT
 
- TRAP7_COMMAND__Trap7Cmd1_MASK
 
- TRAP7_COMMAND__Trap7Cmd1__SHIFT
 
- TRAP7_CONTROL0__Trap7CrossTrigger_MASK
 
- TRAP7_CONTROL0__Trap7CrossTrigger__SHIFT
 
- TRAP7_CONTROL0__Trap7En_MASK
 
- TRAP7_CONTROL0__Trap7En__SHIFT
 
- TRAP7_CONTROL0__Trap7SMUIntr_MASK
 
- TRAP7_CONTROL0__Trap7SMUIntr__SHIFT
 
- TRAP8_ADDRESS_HI_MASK__Trap8AddrHiMask_MASK
 
- TRAP8_ADDRESS_HI_MASK__Trap8AddrHiMask__SHIFT
 
- TRAP8_ADDRESS_HI__Trap8AddrHi_MASK
 
- TRAP8_ADDRESS_HI__Trap8AddrHi__SHIFT
 
- TRAP8_ADDRESS_LO_MASK__Trap8AddrLoMask_MASK
 
- TRAP8_ADDRESS_LO_MASK__Trap8AddrLoMask__SHIFT
 
- TRAP8_ADDRESS_LO__Trap8AddrLo_MASK
 
- TRAP8_ADDRESS_LO__Trap8AddrLo__SHIFT
 
- TRAP8_COMMAND_MASK__Trap8Cmd0Mask_MASK
 
- TRAP8_COMMAND_MASK__Trap8Cmd0Mask__SHIFT
 
- TRAP8_COMMAND_MASK__Trap8Cmd1Mask_MASK
 
- TRAP8_COMMAND_MASK__Trap8Cmd1Mask__SHIFT
 
- TRAP8_COMMAND__Trap8Cmd0_MASK
 
- TRAP8_COMMAND__Trap8Cmd0__SHIFT
 
- TRAP8_COMMAND__Trap8Cmd1_MASK
 
- TRAP8_COMMAND__Trap8Cmd1__SHIFT
 
- TRAP8_CONTROL0__Trap8CrossTrigger_MASK
 
- TRAP8_CONTROL0__Trap8CrossTrigger__SHIFT
 
- TRAP8_CONTROL0__Trap8En_MASK
 
- TRAP8_CONTROL0__Trap8En__SHIFT
 
- TRAP8_CONTROL0__Trap8SMUIntr_MASK
 
- TRAP8_CONTROL0__Trap8SMUIntr__SHIFT
 
- TRAP9_ADDRESS_HI_MASK__Trap9AddrHiMask_MASK
 
- TRAP9_ADDRESS_HI_MASK__Trap9AddrHiMask__SHIFT
 
- TRAP9_ADDRESS_HI__Trap9AddrHi_MASK
 
- TRAP9_ADDRESS_HI__Trap9AddrHi__SHIFT
 
- TRAP9_ADDRESS_LO_MASK__Trap9AddrLoMask_MASK
 
- TRAP9_ADDRESS_LO_MASK__Trap9AddrLoMask__SHIFT
 
- TRAP9_ADDRESS_LO__Trap9AddrLo_MASK
 
- TRAP9_ADDRESS_LO__Trap9AddrLo__SHIFT
 
- TRAP9_COMMAND_MASK__Trap9Cmd0Mask_MASK
 
- TRAP9_COMMAND_MASK__Trap9Cmd0Mask__SHIFT
 
- TRAP9_COMMAND_MASK__Trap9Cmd1Mask_MASK
 
- TRAP9_COMMAND_MASK__Trap9Cmd1Mask__SHIFT
 
- TRAP9_COMMAND__Trap9Cmd0_MASK
 
- TRAP9_COMMAND__Trap9Cmd0__SHIFT
 
- TRAP9_COMMAND__Trap9Cmd1_MASK
 
- TRAP9_COMMAND__Trap9Cmd1__SHIFT
 
- TRAP9_CONTROL0__Trap9CrossTrigger_MASK
 
- TRAP9_CONTROL0__Trap9CrossTrigger__SHIFT
 
- TRAP9_CONTROL0__Trap9En_MASK
 
- TRAP9_CONTROL0__Trap9En__SHIFT
 
- TRAP9_CONTROL0__Trap9SMUIntr_MASK
 
- TRAP9_CONTROL0__Trap9SMUIntr__SHIFT
 
- TRAPAZOID_FILL
 
- TRAPA_BUG_OPCODE
 
- TRAPEZOIDS
 
- TRAPPED_PAGES_MAX
 
- TRAPTL1
 
- TRAPTL1_ARG
 
- TRAP_7INSNS
 
- TRAP_ADDRESS_ERROR
 
- TRAP_ARG
 
- TRAP_ARITHMETIC
 
- TRAP_BLOCK_SZ_SHIFT
 
- TRAP_BRANCH
 
- TRAP_BRKPT
 
- TRAP_DEBUG
 
- TRAP_DIVOVF_ERROR
 
- TRAP_DIVZERO_ERROR
 
- TRAP_DSTREAM_FAULT
 
- TRAP_DTB_DOUBLE_MISS_3
 
- TRAP_DTB_DOUBLE_MISS_4
 
- TRAP_DTB_SINGLE_MISS
 
- TRAP_ENABLE
 
- TRAP_ENTRY
 
- TRAP_ENTRY_INTERRUPT
 
- TRAP_FPU_ERROR
 
- TRAP_FP_DISABLED
 
- TRAP_HANDLER_DECL
 
- TRAP_HWBKPT
 
- TRAP_ID_SYSCALL
 
- TRAP_ILLEGAL_SLOT_INST
 
- TRAP_INSTR
 
- TRAP_INVALID0
 
- TRAP_INVALID1
 
- TRAP_INVALID2
 
- TRAP_INVALID3
 
- TRAP_IRQ
 
- TRAP_IVEC
 
- TRAP_LOAD_IRQ_WORK_PA
 
- TRAP_LOAD_PGD_PHYS
 
- TRAP_LOAD_THREAD_REG
 
- TRAP_LOAD_TRAP_BLOCK
 
- TRAP_MACHINE_CHECK
 
- TRAP_MT_FPCR
 
- TRAP_NMI_IRQ
 
- TRAP_NOARG
 
- TRAP_NOSAVE
 
- TRAP_NOSAVE_7INSNS
 
- TRAP_OPCDEC
 
- TRAP_PER_CPU_CPU_LIST_PA
 
- TRAP_PER_CPU_CPU_MONDO_BLOCK_PA
 
- TRAP_PER_CPU_CPU_MONDO_PA
 
- TRAP_PER_CPU_CPU_MONDO_QMASK
 
- TRAP_PER_CPU_DEV_MONDO_PA
 
- TRAP_PER_CPU_DEV_MONDO_QMASK
 
- TRAP_PER_CPU_FAULT_INFO
 
- TRAP_PER_CPU_IRQ_WORKLIST_PA
 
- TRAP_PER_CPU_NONRESUM_KBUF_PA
 
- TRAP_PER_CPU_NONRESUM_MONDO_PA
 
- TRAP_PER_CPU_NONRESUM_QMASK
 
- TRAP_PER_CPU_PER_CPU_BASE
 
- TRAP_PER_CPU_PGD_PADDR
 
- TRAP_PER_CPU_RESUM_KBUF_PA
 
- TRAP_PER_CPU_RESUM_MONDO_PA
 
- TRAP_PER_CPU_RESUM_QMASK
 
- TRAP_PER_CPU_THREAD
 
- TRAP_PER_CPU_TSB_HUGE
 
- TRAP_PER_CPU_TSB_HUGE_TEMP
 
- TRAP_REPLAY
 
- TRAP_REQUEST0__TrapReqAddrLo_MASK
 
- TRAP_REQUEST0__TrapReqAddrLo__SHIFT
 
- TRAP_REQUEST1__TrapReqAddrHi_MASK
 
- TRAP_REQUEST1__TrapReqAddrHi__SHIFT
 
- TRAP_REQUEST2__TrapAttr_MASK
 
- TRAP_REQUEST2__TrapAttr__SHIFT
 
- TRAP_REQUEST2__TrapReqCmd_MASK
 
- TRAP_REQUEST2__TrapReqCmd__SHIFT
 
- TRAP_REQUEST2__TrapReqLen_MASK
 
- TRAP_REQUEST2__TrapReqLen__SHIFT
 
- TRAP_REQUEST3__TrapReqBlockLevel_MASK
 
- TRAP_REQUEST3__TrapReqBlockLevel__SHIFT
 
- TRAP_REQUEST3__TrapReqChain_MASK
 
- TRAP_REQUEST3__TrapReqChain__SHIFT
 
- TRAP_REQUEST3__TrapReqIO_MASK
 
- TRAP_REQUEST3__TrapReqIO__SHIFT
 
- TRAP_REQUEST3__TrapReqPassPW_MASK
 
- TRAP_REQUEST3__TrapReqPassPW__SHIFT
 
- TRAP_REQUEST3__TrapReqRspPassPW_MASK
 
- TRAP_REQUEST3__TrapReqRspPassPW__SHIFT
 
- TRAP_REQUEST3__TrapReqUnitID_MASK
 
- TRAP_REQUEST3__TrapReqUnitID__SHIFT
 
- TRAP_REQUEST3__TrapReqVC_MASK
 
- TRAP_REQUEST3__TrapReqVC__SHIFT
 
- TRAP_REQUEST4__TrapReqSecLevel_MASK
 
- TRAP_REQUEST4__TrapReqSecLevel__SHIFT
 
- TRAP_REQUEST5__TrapReqDataErr_MASK
 
- TRAP_REQUEST5__TrapReqDataErr__SHIFT
 
- TRAP_REQUEST5__TrapReqDataParity_MASK
 
- TRAP_REQUEST5__TrapReqDataParity__SHIFT
 
- TRAP_REQUEST5__TrapReqDataVC_MASK
 
- TRAP_REQUEST5__TrapReqDataVC__SHIFT
 
- TRAP_REQUEST_DATA0__TrapReqData0_MASK
 
- TRAP_REQUEST_DATA0__TrapReqData0__SHIFT
 
- TRAP_REQUEST_DATA10__TrapReqData10_MASK
 
- TRAP_REQUEST_DATA10__TrapReqData10__SHIFT
 
- TRAP_REQUEST_DATA11__TrapReqData11_MASK
 
- TRAP_REQUEST_DATA11__TrapReqData11__SHIFT
 
- TRAP_REQUEST_DATA12__TrapReqData12_MASK
 
- TRAP_REQUEST_DATA12__TrapReqData12__SHIFT
 
- TRAP_REQUEST_DATA13__TrapReqData13_MASK
 
- TRAP_REQUEST_DATA13__TrapReqData13__SHIFT
 
- TRAP_REQUEST_DATA14__TrapReqData14_MASK
 
- TRAP_REQUEST_DATA14__TrapReqData14__SHIFT
 
- TRAP_REQUEST_DATA15__TrapReqData15_MASK
 
- TRAP_REQUEST_DATA15__TrapReqData15__SHIFT
 
- TRAP_REQUEST_DATA1__TrapReqData1_MASK
 
- TRAP_REQUEST_DATA1__TrapReqData1__SHIFT
 
- TRAP_REQUEST_DATA2__TrapReqData2_MASK
 
- TRAP_REQUEST_DATA2__TrapReqData2__SHIFT
 
- TRAP_REQUEST_DATA3__TrapReqData3_MASK
 
- TRAP_REQUEST_DATA3__TrapReqData3__SHIFT
 
- TRAP_REQUEST_DATA4__TrapReqData4_MASK
 
- TRAP_REQUEST_DATA4__TrapReqData4__SHIFT
 
- TRAP_REQUEST_DATA5__TrapReqData5_MASK
 
- TRAP_REQUEST_DATA5__TrapReqData5__SHIFT
 
- TRAP_REQUEST_DATA6__TrapReqData6_MASK
 
- TRAP_REQUEST_DATA6__TrapReqData6__SHIFT
 
- TRAP_REQUEST_DATA7__TrapReqData7_MASK
 
- TRAP_REQUEST_DATA7__TrapReqData7__SHIFT
 
- TRAP_REQUEST_DATA8__TrapReqData8_MASK
 
- TRAP_REQUEST_DATA8__TrapReqData8__SHIFT
 
- TRAP_REQUEST_DATA9__TrapReqData9_MASK
 
- TRAP_REQUEST_DATA9__TrapReqData9__SHIFT
 
- TRAP_REQUEST_DATASTRB0__TrapReqDataBytEn0_MASK
 
- TRAP_REQUEST_DATASTRB0__TrapReqDataBytEn0__SHIFT
 
- TRAP_REQUEST_DATASTRB1__TrapReqDataBytEn1_MASK
 
- TRAP_REQUEST_DATASTRB1__TrapReqDataBytEn1__SHIFT
 
- TRAP_RESERVED_INST
 
- TRAP_RESET
 
- TRAP_RESPONSE0__TrapRspDataStatus_MASK
 
- TRAP_RESPONSE0__TrapRspDataStatus__SHIFT
 
- TRAP_RESPONSE0__TrapRspPassPW_MASK
 
- TRAP_RESPONSE0__TrapRspPassPW__SHIFT
 
- TRAP_RESPONSE0__TrapRspStatus_MASK
 
- TRAP_RESPONSE0__TrapRspStatus__SHIFT
 
- TRAP_RESPONSE_CONTROL__TrapRspTrigger_MASK
 
- TRAP_RESPONSE_CONTROL__TrapRspTrigger__SHIFT
 
- TRAP_RESPONSE_DATA0__TrapRdRspData0_MASK
 
- TRAP_RESPONSE_DATA0__TrapRdRspData0__SHIFT
 
- TRAP_RESPONSE_DATA10__TrapRdRspData10_MASK
 
- TRAP_RESPONSE_DATA10__TrapRdRspData10__SHIFT
 
- TRAP_RESPONSE_DATA11__TrapRdRspData11_MASK
 
- TRAP_RESPONSE_DATA11__TrapRdRspData11__SHIFT
 
- TRAP_RESPONSE_DATA12__TrapRdRspData12_MASK
 
- TRAP_RESPONSE_DATA12__TrapRdRspData12__SHIFT
 
- TRAP_RESPONSE_DATA13__TrapRdRspData13_MASK
 
- TRAP_RESPONSE_DATA13__TrapRdRspData13__SHIFT
 
- TRAP_RESPONSE_DATA14__TrapRdRspData14_MASK
 
- TRAP_RESPONSE_DATA14__TrapRdRspData14__SHIFT
 
- TRAP_RESPONSE_DATA15__TrapRdRspData15_MASK
 
- TRAP_RESPONSE_DATA15__TrapRdRspData15__SHIFT
 
- TRAP_RESPONSE_DATA1__TrapRdRspData1_MASK
 
- TRAP_RESPONSE_DATA1__TrapRdRspData1__SHIFT
 
- TRAP_RESPONSE_DATA2__TrapRdRspData2_MASK
 
- TRAP_RESPONSE_DATA2__TrapRdRspData2__SHIFT
 
- TRAP_RESPONSE_DATA3__TrapRdRspData3_MASK
 
- TRAP_RESPONSE_DATA3__TrapRdRspData3__SHIFT
 
- TRAP_RESPONSE_DATA4__TrapRdRspData4_MASK
 
- TRAP_RESPONSE_DATA4__TrapRdRspData4__SHIFT
 
- TRAP_RESPONSE_DATA5__TrapRdRspData5_MASK
 
- TRAP_RESPONSE_DATA5__TrapRdRspData5__SHIFT
 
- TRAP_RESPONSE_DATA6__TrapRdRspData6_MASK
 
- TRAP_RESPONSE_DATA6__TrapRdRspData6__SHIFT
 
- TRAP_RESPONSE_DATA7__TrapRdRspData7_MASK
 
- TRAP_RESPONSE_DATA7__TrapRdRspData7__SHIFT
 
- TRAP_RESPONSE_DATA8__TrapRdRspData8_MASK
 
- TRAP_RESPONSE_DATA8__TrapRdRspData8__SHIFT
 
- TRAP_RESPONSE_DATA9__TrapRdRspData9_MASK
 
- TRAP_RESPONSE_DATA9__TrapRdRspData9__SHIFT
 
- TRAP_SAVEFPU
 
- TRAP_STATUS__TrapNumber_MASK
 
- TRAP_STATUS__TrapNumber__SHIFT
 
- TRAP_STATUS__TrapReqValid_MASK
 
- TRAP_STATUS__TrapReqValid__SHIFT
 
- TRAP_SYSCALL
 
- TRAP_S_2_INSTRUCTION
 
- TRAP_TRACE
 
- TRAP_TYPE_CEE
 
- TRAP_TYPE_DAE
 
- TRAP_TYPE_IAE
 
- TRAP_UBC
 
- TRAP_UNALIGNED
 
- TRAP_UNK
 
- TRAP_UTRAP
 
- TRAP_action
 
- TRASH_BUCKET_SIZE
 
- TRASH_GPR
 
- TRAS_WAIT
 
- TRA_PACKET
 
- TRB
 
- TRBA
 
- TRBH
 
- TRBJ
 
- TRBK
 
- TRBL
 
- TRBS_PER_ISOC_SEGMENT
 
- TRBS_PER_SEGMENT
 
- TRB_ADDR_DEV
 
- TRB_BANDWIDTH_EVENT
 
- TRB_BEI
 
- TRB_BSR
 
- TRB_BUFFER
 
- TRB_BUFF_LEN_UP_TO_BOUNDARY
 
- TRB_BURST_LEN
 
- TRB_BURST_LEN_GET
 
- TRB_CHAIN
 
- TRB_CMD_NOOP
 
- TRB_COMPLETION
 
- TRB_CONFIG_EP
 
- TRB_CTRL_RING_SIZE
 
- TRB_CYCLE
 
- TRB_DATA
 
- TRB_DATA_IN
 
- TRB_DATA_OUT
 
- TRB_DC
 
- TRB_DEV_NOTE
 
- TRB_DIR_IN
 
- TRB_DISABLE_SLOT
 
- TRB_DOORBELL
 
- TRB_ENABLE_SLOT
 
- TRB_ENT
 
- TRB_EVAL_CONTEXT
 
- TRB_EVENT_DATA
 
- TRB_FIELD_TO_STREAMID
 
- TRB_FIELD_TO_TYPE
 
- TRB_FIFO_MODE
 
- TRB_FORCE_EVENT
 
- TRB_FORCE_HEADER
 
- TRB_FRAME_ID
 
- TRB_GET_BW
 
- TRB_HC_EVENT
 
- TRB_IDT
 
- TRB_IDT_MAX_SIZE
 
- TRB_INTR_TARGET
 
- TRB_IOC
 
- TRB_ISOC
 
- TRB_ISO_RING_SIZE
 
- TRB_ISP
 
- TRB_LEN
 
- TRB_LINK
 
- TRB_MAX_BUFF_SHIFT
 
- TRB_MAX_BUFF_SIZE
 
- TRB_MFINDEX_WRAP
 
- TRB_NEC_CMD_COMP
 
- TRB_NEC_GET_FW
 
- TRB_NEG_BANDWIDTH
 
- TRB_NORMAL
 
- TRB_NO_SNOOP
 
- TRB_PORT_STATUS
 
- TRB_RESET_DEV
 
- TRB_RESET_EP
 
- TRB_RING_SIZE
 
- TRB_SEGMENT_SHIFT
 
- TRB_SEGMENT_SIZE
 
- TRB_SETUP
 
- TRB_SET_DEQ
 
- TRB_SET_LT
 
- TRB_SIA
 
- TRB_SIZE
 
- TRB_SP
 
- TRB_STATUS
 
- TRB_STOP_RING
 
- TRB_STREAM_ID
 
- TRB_STREAM_ID_BITMASK
 
- TRB_TBC
 
- TRB_TC
 
- TRB_TDL_HS_SIZE
 
- TRB_TDL_HS_SIZE_GET
 
- TRB_TDL_SS_SIZE
 
- TRB_TDL_SS_SIZE_GET
 
- TRB_TD_SIZE
 
- TRB_TD_SIZE_TBC
 
- TRB_TLBPC
 
- TRB_TOGGLE
 
- TRB_TO_BELT
 
- TRB_TO_DEV_SPEED
 
- TRB_TO_EP_ID
 
- TRB_TO_EP_INDEX
 
- TRB_TO_PACKET_TYPE
 
- TRB_TO_ROOTHUB_PORT
 
- TRB_TO_SLOT_ID
 
- TRB_TO_STREAM_ID
 
- TRB_TO_SUSPEND_PORT
 
- TRB_TO_VF_ID
 
- TRB_TO_VF_INTR_TARGET
 
- TRB_TRANSFER
 
- TRB_TR_NOOP
 
- TRB_TSP
 
- TRB_TX_TYPE
 
- TRB_TYPE
 
- TRB_TYPE_BITMASK
 
- TRB_TYPE_LINK
 
- TRB_TYPE_LINK_LE32
 
- TRB_TYPE_NOOP_LE32
 
- TRC
 
- TRC0
 
- TRC1
 
- TRCACATRn
 
- TRCACVRn
 
- TRCAUTHSTATUS
 
- TRCAUXCTLR
 
- TRCBBCTLR
 
- TRCCCCTLR
 
- TRCCIDCCTLR0
 
- TRCCIDCCTLR1
 
- TRCCIDCVRn
 
- TRCCIDR0
 
- TRCCIDR1
 
- TRCCIDR2
 
- TRCCIDR3
 
- TRCCLAIMCLR
 
- TRCCLAIMSET
 
- TRCCNTCTLRn
 
- TRCCNTRLDVRn
 
- TRCCNTVRn
 
- TRCCONFIGR
 
- TRCDEVAFF0
 
- TRCDEVAFF1
 
- TRCDEVARCH
 
- TRCDEVID
 
- TRCDEVTYPE
 
- TRCDVCMRn
 
- TRCDVCVRn
 
- TRCEN_F
 
- TRCEN_S
 
- TRCEN_V
 
- TRCEVENTCTL0R
 
- TRCEVENTCTL1R
 
- TRCEXTINSELR
 
- TRCFIFOEMPTY_F
 
- TRCFIFOEMPTY_S
 
- TRCFIFOEMPTY_V
 
- TRCIDR0
 
- TRCIDR1
 
- TRCIDR10
 
- TRCIDR11
 
- TRCIDR12
 
- TRCIDR13
 
- TRCIDR2
 
- TRCIDR3
 
- TRCIDR4
 
- TRCIDR5
 
- TRCIDR6
 
- TRCIDR7
 
- TRCIDR8
 
- TRCIDR9
 
- TRCIGNOREDROPINPUT_F
 
- TRCIGNOREDROPINPUT_S
 
- TRCIGNOREDROPINPUT_V
 
- TRCIMSPEC0
 
- TRCIMSPECn
 
- TRCITCTRL
 
- TRCKEEPDUPLICATES_F
 
- TRCKEEPDUPLICATES_S
 
- TRCKEEPDUPLICATES_V
 
- TRCLAR
 
- TRCLR
 
- TRCLSR
 
- TRCMULTIFILTER_F
 
- TRCMULTIFILTER_S
 
- TRCMULTIFILTER_V
 
- TRCOSLAR
 
- TRCOSLSR
 
- TRCPDCR
 
- TRCPDCR_PU
 
- TRCPDSR
 
- TRCPIDR0
 
- TRCPIDR1
 
- TRCPIDR2
 
- TRCPIDR3
 
- TRCPIDR4
 
- TRCPIDR5
 
- TRCPIDR6
 
- TRCPIDR7
 
- TRCPRGCTLR
 
- TRCPROCSELR
 
- TRCQCTLR
 
- TRCRSCTLRn
 
- TRCSEQEVRn
 
- TRCSEQRSTEVR
 
- TRCSEQSTR
 
- TRCSSCCRn
 
- TRCSSCSRn
 
- TRCSSPCICRn
 
- TRCSTALLCTLR
 
- TRCSTATR
 
- TRCSTATR_IDLE_BIT
 
- TRCSYNCPR
 
- TRCTRACEIDR
 
- TRCTSCTLR
 
- TRCVDARCCTLR
 
- TRCVDCTLR
 
- TRCVDSACCTLR
 
- TRCVICTLR
 
- TRCVIIECTLR
 
- TRCVIPCSSCTLR
 
- TRCVISSCTLR
 
- TRCVMIDCCTLR0
 
- TRCVMIDCCTLR1
 
- TRCVMIDCVRn
 
- TRC_ABORT
 
- TRC_C6_WAR
 
- TRC_CMD_CHK_STOP
 
- TRC_CMD_DONE
 
- TRC_CMD_FREE
 
- TRC_CORE1_EN
 
- TRC_CORE2_EN
 
- TRC_CORE_PWR
 
- TRC_CTIO_ABORTED
 
- TRC_CTIO_DONE
 
- TRC_CTIO_ERR
 
- TRC_CTIO_STRANGE
 
- TRC_DATA_IN
 
- TRC_DIF_ERR
 
- TRC_DIMM1
 
- TRC_DIMM2
 
- TRC_DIMM3
 
- TRC_DIMM4
 
- TRC_DO_WORK
 
- TRC_DO_WORK_ERR
 
- TRC_FLUSH
 
- TRC_MCH_EN
 
- TRC_NEW_CMD
 
- TRC_PCH_EN
 
- TRC_PORT_NONE
 
- TRC_RSS_DISABLE
 
- TRC_RSS_ENABLE
 
- TRC_SRR_CTIO
 
- TRC_SRR_RSP
 
- TRC_SRR_TERM
 
- TRC_SRR_XRDY
 
- TRC_THM_EN
 
- TRC_XFR_RDY
 
- TRC_XMIT_DATA
 
- TRC_XMIT_STATUS
 
- TRDCSR_ACT
 
- TRDCSR_DEAD
 
- TRDCSR_RUN
 
- TRDCSR_WAK
 
- TRDY
 
- TRDYCLR
 
- TRDYMSK
 
- TRDYRCH
 
- TRDYV
 
- TRDY_DISPL_MARK
 
- TRDY_MASK
 
- TRE
 
- TREBLE_GPR
 
- TRECHKPT
 
- TRECLAIM
 
- TREEMAX
 
- TREESIZE
 
- TREE_COUNT
 
- TREE_DISCONNECT
 
- TREE_EMPTY
 
- TREE_NONEMPTY
 
- TREE_ROOT
 
- TREF_REG
 
- TREF_TREF
 
- TREGS_OFFSET_NAME
 
- TREMFRQ
 
- TREMFRQ_DEPTH
 
- TREMFRQ_FREQUENCY
 
- TRENB
 
- TREND
 
- TREND_SEL_MODE
 
- TREO_DEFAULT_INTENSITY
 
- TREO_LIMIT_MASK
 
- TREO_MAX_INTENSITY
 
- TREO_PERIOD_NS
 
- TREO_PHYS_IO_START
 
- TREO_PHYS_RAM_START
 
- TREO_PRESCALER
 
- TREO_STR_BASE
 
- TREQ
 
- TREQ_asserted
 
- TRE_MASK
 
- TRE_SHIFT
 
- TRF79070A_NFC_TARGET_PROTOCOL
 
- TRF79070A_NFC_TARGET_PROTOCOL_106A
 
- TRF79070A_NFC_TARGET_PROTOCOL_106B
 
- TRF79070A_NFC_TARGET_PROTOCOL_212F
 
- TRF79070A_NFC_TARGET_PROTOCOL_424F
 
- TRF79070A_NFC_TARGET_PROTOCOL_FELICA
 
- TRF79070A_NFC_TARGET_PROTOCOL_NFCBR_106
 
- TRF79070A_NFC_TARGET_PROTOCOL_NFCBR_212
 
- TRF79070A_NFC_TARGET_PROTOCOL_NFCBR_424
 
- TRF79070A_NFC_TARGET_PROTOCOL_PAS_106
 
- TRF79070A_NFC_TARGET_PROTOCOL_PAS_14443B
 
- TRF79070A_NFC_TARGET_PROTOCOL_RF_H
 
- TRF79070A_NFC_TARGET_PROTOCOL_RF_L
 
- TRF7970A_13MHZ_CLOCK_FREQUENCY
 
- TRF7970A_27MHZ_CLOCK_FREQUENCY
 
- TRF7970A_ADJUTABLE_FIFO_IRQ_LEVELS
 
- TRF7970A_ADJUTABLE_FIFO_IRQ_LEVELS_WLH_112
 
- TRF7970A_ADJUTABLE_FIFO_IRQ_LEVELS_WLH_120
 
- TRF7970A_ADJUTABLE_FIFO_IRQ_LEVELS_WLH_124
 
- TRF7970A_ADJUTABLE_FIFO_IRQ_LEVELS_WLH_96
 
- TRF7970A_ADJUTABLE_FIFO_IRQ_LEVELS_WLL_16
 
- TRF7970A_ADJUTABLE_FIFO_IRQ_LEVELS_WLL_32
 
- TRF7970A_ADJUTABLE_FIFO_IRQ_LEVELS_WLL_4
 
- TRF7970A_ADJUTABLE_FIFO_IRQ_LEVELS_WLL_8
 
- TRF7970A_AUTOSUSPEND_DELAY
 
- TRF7970A_CHIP_STATUS_AGC_ON
 
- TRF7970A_CHIP_STATUS_CTRL
 
- TRF7970A_CHIP_STATUS_DIRECT
 
- TRF7970A_CHIP_STATUS_PM_ON
 
- TRF7970A_CHIP_STATUS_REC_ON
 
- TRF7970A_CHIP_STATUS_RF_ON
 
- TRF7970A_CHIP_STATUS_RF_PWR
 
- TRF7970A_CHIP_STATUS_STBY
 
- TRF7970A_CHIP_STATUS_VRS5_3
 
- TRF7970A_CMD_BIT_CONTINUOUS
 
- TRF7970A_CMD_BIT_CTRL
 
- TRF7970A_CMD_BIT_OPCODE
 
- TRF7970A_CMD_BIT_RW
 
- TRF7970A_CMD_BLOCK_RX
 
- TRF7970A_CMD_CLOSE_SLOT
 
- TRF7970A_CMD_DELAY_TRANSMIT
 
- TRF7970A_CMD_DELAY_TRANSMIT_NO_CRC
 
- TRF7970A_CMD_ENABLE_RX
 
- TRF7970A_CMD_EOF
 
- TRF7970A_CMD_FIFO_RESET
 
- TRF7970A_CMD_IDLE
 
- TRF7970A_CMD_RF_COLLISION
 
- TRF7970A_CMD_RF_COLLISION_RESPONSE_0
 
- TRF7970A_CMD_RF_COLLISION_RESPONSE_N
 
- TRF7970A_CMD_RX_GAIN_ADJUST
 
- TRF7970A_CMD_SOFT_INIT
 
- TRF7970A_CMD_TEST_EXT_RF
 
- TRF7970A_CMD_TEST_INT_RF
 
- TRF7970A_CMD_TRANSMIT
 
- TRF7970A_CMD_TRANSMIT_NO_CRC
 
- TRF7970A_COLLISION_IRQ_MASK
 
- TRF7970A_COLLISION_POSITION
 
- TRF7970A_FIFO_IO_REGISTER
 
- TRF7970A_FIFO_SIZE
 
- TRF7970A_FIFO_STATUS
 
- TRF7970A_FIFO_STATUS_OVERFLOW
 
- TRF7970A_GUARD_TIME_15693
 
- TRF7970A_GUARD_TIME_NFCA
 
- TRF7970A_GUARD_TIME_NFCB
 
- TRF7970A_GUARD_TIME_NFCF
 
- TRF7970A_IRQ_STATUS
 
- TRF7970A_IRQ_STATUS_COL
 
- TRF7970A_IRQ_STATUS_CRC_ERROR
 
- TRF7970A_IRQ_STATUS_ERROR
 
- TRF7970A_IRQ_STATUS_FIFO
 
- TRF7970A_IRQ_STATUS_FRAMING_EOF_ERROR
 
- TRF7970A_IRQ_STATUS_NFC_COL_ERROR
 
- TRF7970A_IRQ_STATUS_NFC_PROTO_ERROR
 
- TRF7970A_IRQ_STATUS_NFC_RF
 
- TRF7970A_IRQ_STATUS_NFC_SDD
 
- TRF7970A_IRQ_STATUS_NORESP
 
- TRF7970A_IRQ_STATUS_PARITY_ERROR
 
- TRF7970A_IRQ_STATUS_SRX
 
- TRF7970A_IRQ_STATUS_TX
 
- TRF7970A_ISO14443A_HIGH_BITRATE_OPTIONS
 
- TRF7970A_ISO14443B_TX_OPTIONS
 
- TRF7970A_ISO_CTRL
 
- TRF7970A_ISO_CTRL_14443A_106
 
- TRF7970A_ISO_CTRL_14443A_212
 
- TRF7970A_ISO_CTRL_14443A_424
 
- TRF7970A_ISO_CTRL_14443A_848
 
- TRF7970A_ISO_CTRL_14443B_106
 
- TRF7970A_ISO_CTRL_14443B_212
 
- TRF7970A_ISO_CTRL_14443B_424
 
- TRF7970A_ISO_CTRL_14443B_848
 
- TRF7970A_ISO_CTRL_15693_DBL_1OF256_2669
 
- TRF7970A_ISO_CTRL_15693_DBL_1OF256_667
 
- TRF7970A_ISO_CTRL_15693_DBL_1OF4_2669
 
- TRF7970A_ISO_CTRL_15693_DBL_1OF4_667a
 
- TRF7970A_ISO_CTRL_15693_SGL_1OF256_2648
 
- TRF7970A_ISO_CTRL_15693_SGL_1OF256_662
 
- TRF7970A_ISO_CTRL_15693_SGL_1OF4_2648
 
- TRF7970A_ISO_CTRL_15693_SGL_1OF4_662
 
- TRF7970A_ISO_CTRL_DIR_MODE
 
- TRF7970A_ISO_CTRL_FELICA_212
 
- TRF7970A_ISO_CTRL_FELICA_424
 
- TRF7970A_ISO_CTRL_NFC_ACTIVE
 
- TRF7970A_ISO_CTRL_NFC_CE
 
- TRF7970A_ISO_CTRL_NFC_CE_14443A
 
- TRF7970A_ISO_CTRL_NFC_CE_14443B
 
- TRF7970A_ISO_CTRL_NFC_INITIATOR
 
- TRF7970A_ISO_CTRL_NFC_NFCA_106
 
- TRF7970A_ISO_CTRL_NFC_NFCF_212
 
- TRF7970A_ISO_CTRL_NFC_NFCF_424
 
- TRF7970A_ISO_CTRL_NFC_NFC_CE_MODE
 
- TRF7970A_ISO_CTRL_RFID
 
- TRF7970A_ISO_CTRL_RFID_SPEED_MASK
 
- TRF7970A_ISO_CTRL_RX_CRC_N
 
- TRF7970A_MODULATOR_27MHZ
 
- TRF7970A_MODULATOR_CLK
 
- TRF7970A_MODULATOR_CLK_13_27
 
- TRF7970A_MODULATOR_CLK_3_6
 
- TRF7970A_MODULATOR_CLK_6_13
 
- TRF7970A_MODULATOR_CLK_DISABLED
 
- TRF7970A_MODULATOR_DEPTH
 
- TRF7970A_MODULATOR_DEPTH_ASK10
 
- TRF7970A_MODULATOR_DEPTH_ASK13
 
- TRF7970A_MODULATOR_DEPTH_ASK16
 
- TRF7970A_MODULATOR_DEPTH_ASK22
 
- TRF7970A_MODULATOR_DEPTH_ASK30
 
- TRF7970A_MODULATOR_DEPTH_ASK7
 
- TRF7970A_MODULATOR_DEPTH_ASK8_5
 
- TRF7970A_MODULATOR_DEPTH_OOK
 
- TRF7970A_MODULATOR_EN_ANA
 
- TRF7970A_MODULATOR_EN_OOK
 
- TRF7970A_MODULATOR_SYS_CLK_CTRL
 
- TRF7970A_NFCID1
 
- TRF7970A_NFC_LOW_FIELD_LEVEL
 
- TRF7970A_NFC_LOW_FIELD_LEVEL_CLEX_DIS
 
- TRF7970A_NFC_LOW_FIELD_LEVEL_RFDET
 
- TRF7970A_NFC_TARGET_LEVEL
 
- TRF7970A_NFC_TARGET_LEVEL_HI_RF
 
- TRF7970A_NFC_TARGET_LEVEL_LD_S_10BYTES
 
- TRF7970A_NFC_TARGET_LEVEL_LD_S_4BYTES
 
- TRF7970A_NFC_TARGET_LEVEL_LD_S_7BYTES
 
- TRF7970A_NFC_TARGET_LEVEL_RFDET
 
- TRF7970A_NFC_TARGET_LEVEL_SDD_EN
 
- TRF7970A_QUIRK_EN2_MUST_STAY_LOW
 
- TRF7970A_QUIRK_IRQ_STATUS_READ
 
- TRF7970A_RAM1
 
- TRF7970A_RAM2
 
- TRF7970A_REG_IO_CTRL
 
- TRF7970A_REG_IO_CTRL_AUTO_REG
 
- TRF7970A_REG_IO_CTRL_EN_EXT_PA
 
- TRF7970A_REG_IO_CTRL_IO_LOW
 
- TRF7970A_REG_IO_CTRL_VRS
 
- TRF7970A_RSSI_OSC_STATUS
 
- TRF7970A_RSSI_OSC_STATUS_RSSI_MASK
 
- TRF7970A_RSSI_OSC_STATUS_RSSI_OSC_OK
 
- TRF7970A_RSSI_OSC_STATUS_RSSI_X_MASK
 
- TRF7970A_RX_NO_RESPONSE_WAIT
 
- TRF7970A_RX_SKB_ALLOC_SIZE
 
- TRF7970A_RX_SPECIAL_SETTINGS
 
- TRF7970A_RX_SPECIAL_SETTINGS_AGCR
 
- TRF7970A_RX_SPECIAL_SETTINGS_C212
 
- TRF7970A_RX_SPECIAL_SETTINGS_C424
 
- TRF7970A_RX_SPECIAL_SETTINGS_GD_0DB
 
- TRF7970A_RX_SPECIAL_SETTINGS_GD_10DB
 
- TRF7970A_RX_SPECIAL_SETTINGS_GD_15DB
 
- TRF7970A_RX_SPECIAL_SETTINGS_GD_5DB
 
- TRF7970A_RX_SPECIAL_SETTINGS_HBT
 
- TRF7970A_RX_SPECIAL_SETTINGS_M848
 
- TRF7970A_RX_SPECIAL_SETTINGS_NO_LIM
 
- TRF7970A_RX_WAIT_TIME
 
- TRF7970A_SPECIAL_FCN_REG1
 
- TRF7970A_SPECIAL_FCN_REG1_14_ANTICOLL
 
- TRF7970A_SPECIAL_FCN_REG1_4_BIT_RX
 
- TRF7970A_SPECIAL_FCN_REG1_COL_7_6
 
- TRF7970A_SPECIAL_FCN_REG1_NEXT_SLOT_37US
 
- TRF7970A_SPECIAL_FCN_REG1_PAR43
 
- TRF7970A_SPECIAL_FCN_REG1_SP_DIR_MODE
 
- TRF7970A_SPECIAL_FCN_REG2
 
- TRF7970A_ST_IDLE
 
- TRF7970A_ST_IDLE_RX_BLOCKED
 
- TRF7970A_ST_LISTENING
 
- TRF7970A_ST_LISTENING_MD
 
- TRF7970A_ST_MAX
 
- TRF7970A_ST_PWR_OFF
 
- TRF7970A_ST_RF_OFF
 
- TRF7970A_ST_WAIT_FOR_RX_DATA
 
- TRF7970A_ST_WAIT_FOR_RX_DATA_CONT
 
- TRF7970A_ST_WAIT_FOR_TX_FIFO
 
- TRF7970A_ST_WAIT_TO_ISSUE_EOF
 
- TRF7970A_SUPPORTED_PROTOCOLS
 
- TRF7970A_TEST_REGISTER1
 
- TRF7970A_TEST_REGISTER2
 
- TRF7970A_TX_LENGTH_BYTE1
 
- TRF7970A_TX_LENGTH_BYTE2
 
- TRF7970A_TX_MAX
 
- TRF7970A_TX_PULSE_LENGTH_CTRL
 
- TRF7970A_TX_TIMER_SETTING_H_BYTE
 
- TRF7970A_TX_TIMER_SETTING_L_BYTE
 
- TRF7970A_WAIT_FOR_FIFO_DRAIN_TIMEOUT
 
- TRF7970A_WAIT_FOR_RX_DATA_TIMEOUT
 
- TRF7970A_WAIT_FOR_TX_IRQ
 
- TRF7970A_WAIT_TO_ISSUE_ISO15693_EOF
 
- TRFLAG_NFCA_SHORT_FRAME
 
- TRFLAG_NFCA_STD_FRAME
 
- TRFLAG_NFCA_STD_FRAME_CRC
 
- TRGCLS_SIZE
 
- TRGMII_BASE
 
- TRGMII_CENTRAL_ALIGNED
 
- TRGMII_INTF_DIS
 
- TRGMII_MODE
 
- TRGMII_RCK_CTRL
 
- TRGMII_TCK_CTRL
 
- TRGMII_TD_ODT
 
- TRGMODE_ENABLE
 
- TRGT1GRPPERR_F
 
- TRGT1GRPPERR_S
 
- TRGT1GRPPERR_V
 
- TRGTBUSY0
 
- TRGTMODSELx
 
- TRIALS
 
- TRIBUF_PORT
 
- TRICK0_PHYS
 
- TRICK0_SIZE
 
- TRICK1_PHYS
 
- TRICK1_SIZE
 
- TRICK2_PHYS
 
- TRICK3_PHYS
 
- TRICK3_SIZE
 
- TRICK4_PHYS
 
- TRICK4_SIZE
 
- TRICK5_PHYS
 
- TRICK6_PHYS
 
- TRICK7_PHYS
 
- TRICK_FAST
 
- TRICK_FREEZE
 
- TRICK_NONE
 
- TRICK_SLOW
 
- TRICN_CMD_ATTEMPTS
 
- TRICN_CMD_READ
 
- TRICN_CMD_WRITE
 
- TRICN_CNFG
 
- TRIDENTFB_DEBUG
 
- TRIDENT_DEVICE_ID_DX
 
- TRIDENT_DEVICE_ID_NX
 
- TRIDENT_DEVICE_ID_SI7018
 
- TRID_REG
 
- TRIENODE
 
- TRIES_128
 
- TRIES_256
 
- TRIG0_ACTIVE
 
- TRIG0_ERROR
 
- TRIG1_ACTIVE
 
- TRIG1_ERROR
 
- TRIG2_ACTIVE
 
- TRIG2_ERROR
 
- TRIG3_ACTIVE
 
- TRIG3_ERROR
 
- TRIG4_ACTIVE
 
- TRIG4_ERROR
 
- TRIG5_ACTIVE
 
- TRIG5_ERROR
 
- TRIG6_ACTIVE
 
- TRIG6_ERROR
 
- TRIG7_ACTIVE
 
- TRIG7_ERROR
 
- TRIGCON
 
- TRIGCON_HWTRIGEN
 
- TRIGCON_HWTRIGMASK
 
- TRIGCON_HWTRIG_INV
 
- TRIGCON_SWTRIGCMD
 
- TRIGCON_SWTRIGCMD_W0BUF
 
- TRIGCON_SWTRIGCMD_W1BUF
 
- TRIGCON_SWTRIGCMD_W2BUF
 
- TRIGCON_SWTRIGCMD_W3BUF
 
- TRIGCON_SWTRIGCMD_W4BUF
 
- TRIGCON_SWTRIGEN
 
- TRIGCON_TE_AUTO_MASK
 
- TRIGCON_TRIGEN_F
 
- TRIGCON_TRIGEN_PER_F
 
- TRIGCON_TRIGMODE_W0BUF
 
- TRIGCON_TRIGMODE_W1BUF
 
- TRIGCON_TRIGMODE_W2BUF
 
- TRIGCON_TRIGMODE_W3BUF
 
- TRIGCON_TRIGMODE_W4BUF
 
- TRIGCON_WB_SWTRIGCMD
 
- TRIGGER
 
- TRIGGER_1
 
- TRIGGER_2
 
- TRIGGER_CAPTURE
 
- TRIGGER_CHANNEL
 
- TRIGGER_CHANNEL_0
 
- TRIGGER_CHANNEL_1
 
- TRIGGER_CHANNEL_2
 
- TRIGGER_CMD_GET
 
- TRIGGER_COMPLETED
 
- TRIGGER_DELAY_NEXT_LINE
 
- TRIGGER_DELAY_NEXT_PIXEL
 
- TRIGGER_ERROR
 
- TRIGGER_FCR_MASK
 
- TRIGGER_HIT
 
- TRIGGER_ID_SHIFT
 
- TRIGGER_LINE
 
- TRIGGER_LOC
 
- TRIGGER_MDUMP_ONCE
 
- TRIGGER_NC_MSG_2
 
- TRIGGER_NONE
 
- TRIGGER_OFF
 
- TRIGGER_OFFSET
 
- TRIGGER_ON
 
- TRIGGER_POLARITY_SELECT_CRTC
 
- TRIGGER_POLARITY_SELECT_GENERICA
 
- TRIGGER_POLARITY_SELECT_GENERICB
 
- TRIGGER_POLARITY_SELECT_GENERICC
 
- TRIGGER_POLARITY_SELECT_HSYNCA
 
- TRIGGER_POLARITY_SELECT_HSYNCB
 
- TRIGGER_POLARITY_SELECT_LOGIC_ZERO
 
- TRIGGER_POLARITY_SELECT_VIDEO_CAPTURE
 
- TRIGGER_RCVD
 
- TRIGGER_READY
 
- TRIGGER_REG
 
- TRIGGER_REQ
 
- TRIGGER_RX_QUEUES_NOTIF_CMD
 
- TRIGGER_SEOF
 
- TRIGGER_SOURCE_SELECT_BLONY
 
- TRIGGER_SOURCE_SELECT_CRTC_HSYNCA
 
- TRIGGER_SOURCE_SELECT_CRTC_HSYNCB
 
- TRIGGER_SOURCE_SELECT_CRTC_VSYNCA
 
- TRIGGER_SOURCE_SELECT_CRTC_VSYNCB
 
- TRIGGER_SOURCE_SELECT_GENERICA
 
- TRIGGER_SOURCE_SELECT_GENERICB
 
- TRIGGER_SOURCE_SELECT_GENERICC
 
- TRIGGER_SOURCE_SELECT_GENERICD
 
- TRIGGER_SOURCE_SELECT_GENERICE
 
- TRIGGER_SOURCE_SELECT_GENERICF
 
- TRIGGER_SOURCE_SELECT_GSL_ALLOW_FLIP
 
- TRIGGER_SOURCE_SELECT_GSL_GROUP0
 
- TRIGGER_SOURCE_SELECT_GSL_GROUP1
 
- TRIGGER_SOURCE_SELECT_GSL_GROUP2
 
- TRIGGER_SOURCE_SELECT_HPD1
 
- TRIGGER_SOURCE_SELECT_HPD2
 
- TRIGGER_SOURCE_SELECT_HSYNCA
 
- TRIGGER_SOURCE_SELECT_HSYNCB
 
- TRIGGER_SOURCE_SELECT_LOGIC_ZERO
 
- TRIGGER_SOURCE_SELECT_MANUAL_TRIGGER
 
- TRIGGER_SOURCE_SELECT_VIDEO_CAPTURE
 
- TRIGGER_SOURCE_SELECT_VSYNCA
 
- TRIGGER_SOURCE_SELECT_VSYNCB
 
- TRIGGER_SW
 
- TRIGGER_SW_SEOF
 
- TRIGGER_SW_TE
 
- TRIGGER_TE
 
- TRIGGER_TLR_MASK
 
- TRIGGER_VAL
 
- TRIGGER_WARN_ONCE
 
- TRIG_1
 
- TRIG_1_2
 
- TRIG_7_8
 
- TRIG_ACTIVE
 
- TRIG_ANY
 
- TRIG_BASE
 
- TRIG_BIT_OFFSET
 
- TRIG_BIT_PATTERN_M
 
- TRIG_BOGUS
 
- TRIG_BYTE_OFFSET
 
- TRIG_CASCADE_ENABLE
 
- TRIG_CASCADE_ITERATE_CNT_M
 
- TRIG_CASCADE_TAIL
 
- TRIG_CASCADE_UPS_M
 
- TRIG_CASCADE_UPS_S
 
- TRIG_CNTL
 
- TRIG_COUNT
 
- TRIG_CSEL_MASK
 
- TRIG_CSEL_SHIFT
 
- TRIG_CTRL_M
 
- TRIG_CYCLE_CNT_M
 
- TRIG_CYCLE_CNT_S
 
- TRIG_DIS
 
- TRIG_DMA
 
- TRIG_DONE
 
- TRIG_DONE_S
 
- TRIG_EDGE
 
- TRIG_EN
 
- TRIG_ENABLE
 
- TRIG_ERROR_S
 
- TRIG_EXT
 
- TRIG_FOLLOW
 
- TRIG_GPIO_MASK
 
- TRIG_GPIO_SHIFT
 
- TRIG_GPO_M
 
- TRIG_GPO_S
 
- TRIG_IE
 
- TRIG_IF_LATE
 
- TRIG_INT
 
- TRIG_INT_S
 
- TRIG_INVALID
 
- TRIG_LOAD
 
- TRIG_MASK
 
- TRIG_NAME_MAX
 
- TRIG_NEG_EDGE
 
- TRIG_NEG_PERIOD
 
- TRIG_NEG_PULSE
 
- TRIG_NO
 
- TRIG_NONE
 
- TRIG_NOTIFY
 
- TRIG_NOW
 
- TRIG_OTHER
 
- TRIG_PATTERN_M
 
- TRIG_PATTERN_S
 
- TRIG_PER
 
- TRIG_POS_EDGE
 
- TRIG_POS_PERIOD
 
- TRIG_POS_PULSE
 
- TRIG_PULSE
 
- TRIG_PULSE_WIDTH_M
 
- TRIG_READ
 
- TRIG_REG_OUTPUT
 
- TRIG_RESET
 
- TRIG_ROUND_DOWN
 
- TRIG_ROUND_MASK
 
- TRIG_ROUND_NEAREST
 
- TRIG_ROUND_UP
 
- TRIG_ROUND_UP_NEXT
 
- TRIG_RT
 
- TRIG_SEL_BIT
 
- TRIG_SEL_MASK
 
- TRIG_SEL_SHIFT
 
- TRIG_TIME
 
- TRIG_TIMER
 
- TRIG_TOGGLE
 
- TRIG_TS_INT
 
- TRIG_UNIT_M
 
- TRIG_VAL
 
- TRIG_VAL_MSK
 
- TRIG_WAKE_EOS
 
- TRIG_WR
 
- TRIG_WRITE
 
- TRIM1_TRIM
 
- TRIM2_TRIM
 
- TRIM3_TRIM
 
- TRIM4_TRIM
 
- TRIM5_TRIM
 
- TRIM6_TRIM
 
- TRIM7_TRIM
 
- TRIM8_TRIM
 
- TRIMD
 
- TRIMMER_DEFAULT
 
- TRIMMER_DISABLE_RTC
 
- TRIMMER_SET_CMD
 
- TRIMMER_SHIFT
 
- TRIMMER_VALUE_MASK
 
- TRIM_TMO
 
- TRINIB0
 
- TRINIB1
 
- TRINITY_AT_DFLT
 
- TRINITY_DISPCLK_BYPASS_THRESHOLD
 
- TRINITY_MAX_DEEPSLEEP_DIVIDER_ID
 
- TRINITY_MGCG_SEQUENCE
 
- TRINITY_MINIMUM_ENGINE_CLOCK
 
- TRINITY_NUM_NBPSTATES
 
- TRINITY_POWERSTATE_FLAGS_BAPM_DISABLE
 
- TRINITY_POWERSTATE_FLAGS_NBPS_FORCEHIGH
 
- TRINITY_POWERSTATE_FLAGS_NBPS_LOCKTOHIGH
 
- TRINITY_POWERSTATE_FLAGS_NBPS_LOCKTOLOW
 
- TRINITY_SIZEOF_DPM_STATE_TABLE
 
- TRINITY_SYSLS_SEQUENCE
 
- TRINVTILEDETCT
 
- TRION_PLL_OUT_MASK
 
- TRION_PLL_RUN
 
- TRION_PLL_STANDBY
 
- TRIPP_PRODUCT_ID
 
- TRIPP_VENDOR_ID
 
- TRISTATE
 
- TRISTATE_MEM_EN
 
- TRISTATE_REG_A
 
- TRISTRIP
 
- TRIS_REG
 
- TRITON_ID
 
- TRIZEPS4_BOCR_PHYS
 
- TRIZEPS4_BOCR_VIRT
 
- TRIZEPS4_CD_IRQ
 
- TRIZEPS4_CFSR_PHYS
 
- TRIZEPS4_CFSR_VIRT
 
- TRIZEPS4_DICR_PHYS
 
- TRIZEPS4_DICR_VIRT
 
- TRIZEPS4_DISK_PHYS
 
- TRIZEPS4_DISK_VIRT
 
- TRIZEPS4_DOC_IRQ
 
- TRIZEPS4_ETH_IRQ
 
- TRIZEPS4_ETH_PHYS
 
- TRIZEPS4_FLASH_PHYS
 
- TRIZEPS4_FLASH_SIZE
 
- TRIZEPS4_IRCR_PHYS
 
- TRIZEPS4_IRCR_VIRT
 
- TRIZEPS4_MMC_IRQ
 
- TRIZEPS4_PIC_IRQ
 
- TRIZEPS4_PIC_PHYS
 
- TRIZEPS4_PIC_VIRT
 
- TRIZEPS4_READY_NINT
 
- TRIZEPS4_SDRAM_BASE
 
- TRIZEPS4_SPI_IRQ
 
- TRIZEPS4_UCB1400_IRQ
 
- TRIZEPS4_UPSR_PHYS
 
- TRIZEPS4_UPSR_VIRT
 
- TRI_STATE_BUFFER
 
- TRKID_MAX
 
- TRKID_SGN
 
- TRLUT_HW_CGC_EN
 
- TRL_MULTIPLE_FIXED_LENGTH
 
- TRL_NOMINAL_RATE_0
 
- TRL_NOMINAL_RATE_1
 
- TRL_OFFSET_5
 
- TRL_OFFSET_6
 
- TRL_SINGLE_FIXED_LENGTH
 
- TRL_SINGLE_VARIABLE_LENGTH
 
- TRM290_NO_DMA_WRITES
 
- TRMAX
 
- TRMAX_ADDR
 
- TRMCODE
 
- TRMD
 
- TRMGV
 
- TRMGV_ADDR
 
- TRML_IOP
 
- TRMON_S
 
- TRM_S1040_COMMAND
 
- TRM_S1040_DMA_COMMAND
 
- TRM_S1040_DMA_CONFIG
 
- TRM_S1040_DMA_CONTROL
 
- TRM_S1040_DMA_CXCNT
 
- TRM_S1040_DMA_FIFOCNT
 
- TRM_S1040_DMA_FIFOSTAT
 
- TRM_S1040_DMA_INTEN
 
- TRM_S1040_DMA_STATUS
 
- TRM_S1040_DMA_XCNT
 
- TRM_S1040_DMA_XHIGHADDR
 
- TRM_S1040_DMA_XLOWADDR
 
- TRM_S1040_GEN_CONTROL
 
- TRM_S1040_GEN_EADDRESS
 
- TRM_S1040_GEN_EDATA
 
- TRM_S1040_GEN_NVRAM
 
- TRM_S1040_GEN_STATUS
 
- TRM_S1040_GEN_TIMER
 
- TRM_S1040_ID
 
- TRM_S1040_INTLINE
 
- TRM_S1040_IOBASE
 
- TRM_S1040_ROMBASE
 
- TRM_S1040_SCSI_COMMAND
 
- TRM_S1040_SCSI_CONFIG0
 
- TRM_S1040_SCSI_CONFIG1
 
- TRM_S1040_SCSI_CONFIG2
 
- TRM_S1040_SCSI_CONTROL
 
- TRM_S1040_SCSI_COUNTER
 
- TRM_S1040_SCSI_FIFO
 
- TRM_S1040_SCSI_FIFOCNT
 
- TRM_S1040_SCSI_HOSTID
 
- TRM_S1040_SCSI_IDMSG
 
- TRM_S1040_SCSI_INTEN
 
- TRM_S1040_SCSI_INTSTATUS
 
- TRM_S1040_SCSI_OFFSET
 
- TRM_S1040_SCSI_SIGNAL
 
- TRM_S1040_SCSI_STATUS
 
- TRM_S1040_SCSI_SYNC
 
- TRM_S1040_SCSI_TARGETID
 
- TRM_S1040_SCSI_TCR0
 
- TRM_S1040_SCSI_TCR1
 
- TRM_S1040_SCSI_TIMEOUT
 
- TRNCNT
 
- TRNCTL
 
- TRNCURTS
 
- TRNENSEL
 
- TRNGEN
 
- TRNGMOD
 
- TRNG_CFG_REG_MAX_REFILL_CYCLES_SHIFT
 
- TRNG_CFG_REG_MIN_REFILL_CYCLES_SHIFT
 
- TRNG_CFG_REG_SAMPLE_DIV_SHIFT
 
- TRNG_CNTL_REG_STARTUP_CYCLES_SHIFT
 
- TRNG_CNTL_REG_TRNG_ENABLE
 
- TRNG_CR
 
- TRNG_CTRL
 
- TRNG_DATA
 
- TRNG_DATA_RDY
 
- TRNG_DEF_CLK_DIV_CYCLES
 
- TRNG_DEF_MAX_REFILL_CYCLES
 
- TRNG_DEF_MIN_REFILL_CYCLES
 
- TRNG_DEF_STARTUP_CYCLES
 
- TRNG_INTACK_REG_READY
 
- TRNG_ISR
 
- TRNG_KEY
 
- TRNG_ODATA
 
- TRNG_OUT_REG
 
- TRNG_RETRIES
 
- TRNG_STATUS_REG_READY
 
- TRNIS
 
- TRNQADRX_END
 
- TRNQADRX_START
 
- TRNQAPARMX_END
 
- TRNQAPARMX_START
 
- TRNQCNT
 
- TRNQTIMX_END
 
- TRNQTIMX_START
 
- TRNULLDETCT
 
- TROCR
 
- TRP0_INTERRUPT_ENABLE
 
- TRP_B15V_EN
 
- TRP_BT_EN
 
- TRP_ECC_DB_ERR_SYN0
 
- TRP_ECC_ERROR_CNTR_CLEAR
 
- TRP_ECC_ERROR_STATUS0
 
- TRP_ECC_ERROR_STATUS1
 
- TRP_ECC_SB_ERR_SYN0
 
- TRP_INTERRUPT_0_CLEAR
 
- TRP_INTERRUPT_0_ENABLE
 
- TRP_INTERRUPT_0_STATUS
 
- TRP_SYN_REG_CNT
 
- TRP_VAUX_EN
 
- TRP_WAIT
 
- TRSCER
 
- TRSLAT_RST_B
 
- TRSLAT_SRC_CHOICE
 
- TRSTRT
 
- TRST_MARK
 
- TRSW0EN
 
- TRSW1EN
 
- TRTTE
 
- TRUE
 
- TRUEIDE_MWORD_DMA_TIMING_MASK
 
- TRUEIDE_MWORD_DMA_TIMING_SHIFT
 
- TRUEIDE_PIO_TIMING_MASK
 
- TRUEIDE_PIO_TIMING_SHIFT
 
- TRUE_IDE_IRQS
 
- TRUE_IDE_MODE
 
- TRUE_IDE_MODE_IRQ
 
- TRUNCATE
 
- TRUNCATE_LOG_SYSTEM_INODE
 
- TRUSTED_XATTR
 
- TRUST_MAX
 
- TRU_FORCE_MODEM
 
- TRU_FORCE_MS
 
- TRU_NORMAL
 
- TRVADR
 
- TRVATTL3PTRDW
 
- TRXDMA_CTRL_BEQ_SHIFT
 
- TRXDMA_CTRL_BKQ_SHIFT
 
- TRXDMA_CTRL_HIQ_SHIFT
 
- TRXDMA_CTRL_MGQ_SHIFT
 
- TRXDMA_CTRL_RXDMA_AGG_EN
 
- TRXDMA_CTRL_VIQ_SHIFT
 
- TRXDMA_CTRL_VOQ_SHIFT
 
- TRXDMA_QUEUE_HIGH
 
- TRXDMA_QUEUE_LOW
 
- TRXDMA_QUEUE_NORMAL
 
- TRXDMA_STATUS
 
- TRXPKTBUF_DBG_CTRL
 
- TRXPKTBUF_DBG_DATA
 
- TRX_MAGIC
 
- TRX_MAX_OFFSET
 
- TRX_OFFSETS_DLFWLEN_IDX
 
- TRX_PARSER_MAX_PARTS
 
- TRX_RDL_CHUNK
 
- TRX_REG
 
- TRX_STATE_MASK
 
- TRX_UNCOMP_IMAGE
 
- TRY_DIRECT_IO
 
- TRY_FIXUP_FIELD
 
- TRY_LOCK
 
- TR_100_MDMA_ACCESS_MASK
 
- TR_100_MDMA_ACCESS_SHIFT
 
- TR_100_MDMA_MASK
 
- TR_100_MDMA_RECOVERY_MASK
 
- TR_100_MDMA_RECOVERY_SHIFT
 
- TR_100_PIOREG_MDMA_MASK
 
- TR_100_PIOREG_PIO_MASK
 
- TR_100_PIO_ACCESS_MASK
 
- TR_100_PIO_ACCESS_SHIFT
 
- TR_100_PIO_ADDRSETUP_MASK
 
- TR_100_PIO_ADDRSETUP_SHIFT
 
- TR_100_PIO_MASK
 
- TR_100_PIO_RECOVERY_MASK
 
- TR_100_PIO_RECOVERY_SHIFT
 
- TR_100_UDMAREG_UDMA_EN
 
- TR_100_UDMAREG_UDMA_MASK
 
- TR_128
 
- TR_133_PIOREG_MDMA_MASK
 
- TR_133_PIOREG_PIO_MASK
 
- TR_133_UDMAREG_UDMA_EN
 
- TR_133_UDMAREG_UDMA_MASK
 
- TR_160
 
- TR_33_MDMA_ACCESS_MASK
 
- TR_33_MDMA_ACCESS_SHIFT
 
- TR_33_MDMA_HALFTICK
 
- TR_33_MDMA_MASK
 
- TR_33_MDMA_RECOVERY_MASK
 
- TR_33_MDMA_RECOVERY_SHIFT
 
- TR_33_PIO_ACCESS_MASK
 
- TR_33_PIO_ACCESS_SHIFT
 
- TR_33_PIO_E
 
- TR_33_PIO_MASK
 
- TR_33_PIO_RECOVERY_MASK
 
- TR_33_PIO_RECOVERY_SHIFT
 
- TR_66_MDMA_ACCESS_MASK
 
- TR_66_MDMA_ACCESS_SHIFT
 
- TR_66_MDMA_MASK
 
- TR_66_MDMA_RECOVERY_MASK
 
- TR_66_MDMA_RECOVERY_SHIFT
 
- TR_66_PIO_ACCESS_MASK
 
- TR_66_PIO_ACCESS_SHIFT
 
- TR_66_PIO_ADDRSETUP_MASK
 
- TR_66_PIO_ADDRSETUP_SHIFT
 
- TR_66_PIO_MASK
 
- TR_66_PIO_RECOVERY_MASK
 
- TR_66_PIO_RECOVERY_SHIFT
 
- TR_66_UDMA_ADDRSETUP_MASK
 
- TR_66_UDMA_ADDRSETUP_SHIFT
 
- TR_66_UDMA_EN
 
- TR_66_UDMA_MASK
 
- TR_66_UDMA_RDY2PAUS_MASK
 
- TR_66_UDMA_RDY2PAUS_SHIFT
 
- TR_66_UDMA_WRDATASETUP_MASK
 
- TR_66_UDMA_WRDATASETUP_SHIFT
 
- TR_72
 
- TR_96
 
- TR_ADDR
 
- TR_ALLOCED
 
- TR_ATTACHED
 
- TR_BUF_FMT
 
- TR_CLKCRC
 
- TR_CLKDATA
 
- TR_CLKIBIT0
 
- TR_CLKIBIT1
 
- TR_CLKOBIT0
 
- TR_CLKOBIT1
 
- TR_CLKOSTART
 
- TR_CLKTAG
 
- TR_CLKWSTART
 
- TR_CLKZ
 
- TR_CLR_SCL
 
- TR_CLR_SDA
 
- TR_CONFIG
 
- TR_CYCLE_TOG
 
- TR_DELAY
 
- TR_END
 
- TR_ERROR_COUNT
 
- TR_E_A1_IN
 
- TR_E_A1_OUT
 
- TR_E_A2_IN
 
- TR_E_A2_OUT
 
- TR_FMT
 
- TR_FORMAT_STATUS_BYTE
 
- TR_FORMAT_STATUS_MASK
 
- TR_FORMAT_TOUCH_BIT
 
- TR_HS
 
- TR_LENGTH
 
- TR_MAX_XC
 
- TR_MAX_YC
 
- TR_MIN_XC
 
- TR_MIN_YC
 
- TR_OLEN
 
- TR_PAGE_A0
 
- TR_PAGE_A2
 
- TR_RDY
 
- TR_REQ
 
- TR_SET_SCL
 
- TR_SET_SDA
 
- TR_STD
 
- TR_TOUCHED
 
- TR_WRITE
 
- TRxCBR
 
- TRxCDP
 
- TRxCOI
 
- TRxCTC
 
- TRxCXT
 
- TS
 
- TS0_ADC_DOUT_MASK
 
- TS0_ADC_DOUT_SHIFT
 
- TS0_SCK_MARK
 
- TS0_SDAT_MARK
 
- TS0_SDEN_MARK
 
- TS0_SPSYNC_MARK
 
- TS1VIP_TS2_PORT
 
- TS1_CFG_REG
 
- TS1_EN
 
- TS1_EXT_CLOCK
 
- TS1_FMT0_MASK
 
- TS1_HITTHD_MASK
 
- TS1_HITTHD_POS
 
- TS1_INTRIG_SEL_MASK
 
- TS1_LENGTH_REG
 
- TS1_LITTHD_MASK
 
- TS1_MFREQ_MASK
 
- TS1_PIN_CTL0
 
- TS1_PIN_CTL1
 
- TS1_PORT
 
- TS1_RAMP_COEFF_MASK
 
- TS1_SMP_TIME_MASK
 
- TS1_SMP_TIME_POS
 
- TS1_START
 
- TS1_T0_MASK
 
- TS1_T0_POS
 
- TS1_T0_VAL0
 
- TS1_T0_VAL1
 
- TS1_TS2_PORT
 
- TS1_parallel_mode
 
- TS1_serial_mode
 
- TS2
 
- TS2020_CLK_OUT_DISABLED
 
- TS2020_CLK_OUT_ENABLED
 
- TS2020_CLK_OUT_ENABLED_XTALOUT
 
- TS2020_H
 
- TS2020_M88TS2020
 
- TS2020_M88TS2022
 
- TS2020_XTAL_FREQ
 
- TS209_RTC_GPIO
 
- TS2_CFG_REG
 
- TS2_LENGTH_REG
 
- TS3000_DEVID
 
- TS3000_DEVID_MASK
 
- TS3001_DEVID
 
- TS3001_DEVID_MASK
 
- TS3A227E_JACK_MASK
 
- TS3A227E_NUM_BUTTONS
 
- TS3A227E_REG_ACCESSORY_STATUS
 
- TS3A227E_REG_ADC_OUTPUT
 
- TS3A227E_REG_DEVICE_ID
 
- TS3A227E_REG_INTERRUPT
 
- TS3A227E_REG_INTERRUPT_DISABLE
 
- TS3A227E_REG_KP_INTERRUPT
 
- TS3A227E_REG_KP_THRESHOLD_1
 
- TS3A227E_REG_KP_THRESHOLD_2
 
- TS3A227E_REG_KP_THRESHOLD_3
 
- TS3A227E_REG_SETTING_1
 
- TS3A227E_REG_SETTING_2
 
- TS3A227E_REG_SETTING_3
 
- TS3A227E_REG_SWITCH_CONTROL_1
 
- TS3A227E_REG_SWITCH_CONTROL_2
 
- TS3A227E_REG_SWITCH_STATUS_1
 
- TS3A227E_REG_SWITCH_STATUS_2
 
- TS409_RTC_GPIO
 
- TS4800_WDT_DISABLE
 
- TS4800_WDT_FEED_10S
 
- TS4800_WDT_FEED_2S
 
- TS4900_GPIO_IN
 
- TS4900_GPIO_OE
 
- TS4900_GPIO_OUT
 
- TS5400_PRODUCT_CODE
 
- TS5500_ADC
 
- TS5500_ADC_CONV_BUSY
 
- TS5500_ADC_CONV_BUSY_ADDR
 
- TS5500_ADC_CONV_DELAY
 
- TS5500_ADC_CONV_INIT_LSB_ADDR
 
- TS5500_ADC_CONV_MSB_ADDR
 
- TS5500_ATTR_BOOL
 
- TS5500_DIO1
 
- TS5500_DIO2
 
- TS5500_DIO_GROUP
 
- TS5500_DIO_IN
 
- TS5500_DIO_IN_IRQ
 
- TS5500_DIO_IN_OUT
 
- TS5500_DIO_OUT
 
- TS5500_ERESET
 
- TS5500_ERESET_ITR_ADDR
 
- TS5500_ITR
 
- TS5500_JP1
 
- TS5500_JP2
 
- TS5500_JP3
 
- TS5500_JP4
 
- TS5500_JP5
 
- TS5500_JP6
 
- TS5500_JP7
 
- TS5500_LCD
 
- TS5500_LED
 
- TS5500_LED_JP_ADDR
 
- TS5500_PRODUCT_CODE
 
- TS5500_PRODUCT_CODE_ADDR
 
- TS5500_RS485
 
- TS5500_RS485_AUTO
 
- TS5500_RS485_RTS
 
- TS5500_SRAM
 
- TS5500_SRAM_RS485_ADC_ADDR
 
- TS5600_LCD
 
- TS72XX_BOOTROM_PART_SIZE
 
- TS72XX_CPLDVER_PHYS_BASE
 
- TS72XX_CPLDVER_SIZE
 
- TS72XX_CPLDVER_VIRT_BASE
 
- TS72XX_MODEL_MASK
 
- TS72XX_MODEL_PHYS_BASE
 
- TS72XX_MODEL_SIZE
 
- TS72XX_MODEL_TS7200
 
- TS72XX_MODEL_TS7250
 
- TS72XX_MODEL_TS7260
 
- TS72XX_MODEL_TS7300
 
- TS72XX_MODEL_TS7400
 
- TS72XX_MODEL_VIRT_BASE
 
- TS72XX_NAND_BUSY_ADDR_LINE
 
- TS72XX_NAND_CONTROL_ADDR_LINE
 
- TS72XX_OPTIONS2_PHYS_BASE
 
- TS72XX_OPTIONS2_SIZE
 
- TS72XX_OPTIONS2_TS9420
 
- TS72XX_OPTIONS2_TS9420_BOOT
 
- TS72XX_OPTIONS2_VIRT_BASE
 
- TS72XX_OPTIONS_COM2_RS485
 
- TS72XX_OPTIONS_MAX197
 
- TS72XX_OPTIONS_PHYS_BASE
 
- TS72XX_OPTIONS_SIZE
 
- TS72XX_OPTIONS_VIRT_BASE
 
- TS72XX_REDBOOT_PART_SIZE
 
- TS72XX_RTC_DATA_PHYS_BASE
 
- TS72XX_RTC_INDEX_PHYS_BASE
 
- TS72XX_WDT_CONTROL_PHYS_BASE
 
- TS72XX_WDT_CTRL_1SEC
 
- TS72XX_WDT_CTRL_250MS
 
- TS72XX_WDT_CTRL_2SEC
 
- TS72XX_WDT_CTRL_4SEC
 
- TS72XX_WDT_CTRL_500MS
 
- TS72XX_WDT_CTRL_8SEC
 
- TS72XX_WDT_CTRL_DISABLE
 
- TS72XX_WDT_CTRL_RESERVED
 
- TS72XX_WDT_DEFAULT_TIMEOUT
 
- TS72XX_WDT_FEED_PHYS_BASE
 
- TS72XX_WDT_FEED_VAL
 
- TS73XX_FPGA_CONFIG_LOAD
 
- TS73XX_FPGA_CONFIG_REG
 
- TS73XX_FPGA_DATA_REG
 
- TS73XX_FPGA_LOADER_BASE
 
- TS73XX_FPGA_LOAD_OK
 
- TS73XX_FPGA_RESET
 
- TS73XX_FPGA_RESET_HIGH_DELAY
 
- TS73XX_FPGA_RESET_LOW_DELAY
 
- TS73XX_FPGA_WRITE_DONE
 
- TS73XX_FPGA_WRITE_DONE_TIMEOUT
 
- TS7800_FPGA_MAGIC
 
- TS7800_REV_1
 
- TS7800_REV_2
 
- TS7800_REV_3
 
- TS7800_REV_4
 
- TS7800_REV_5
 
- TS7800_REV_6
 
- TS7800_REV_7
 
- TS7800_REV_8
 
- TS7800_REV_9
 
- TS78XX_FPGA_REGS_PHYS_BASE
 
- TS78XX_FPGA_REGS_SIZE
 
- TS78XX_FPGA_REGS_VIRT_BASE
 
- TS7970_GPIO_IN
 
- TSA6060T_ADDR
 
- TSADCV2_AUTO_CON
 
- TSADCV2_AUTO_EN
 
- TSADCV2_AUTO_PERIOD
 
- TSADCV2_AUTO_PERIOD_HT
 
- TSADCV2_AUTO_PERIOD_HT_TIME
 
- TSADCV2_AUTO_PERIOD_TIME
 
- TSADCV2_AUTO_SRC_EN
 
- TSADCV2_AUTO_TSHUT_POLARITY_HIGH
 
- TSADCV2_COMP_INT
 
- TSADCV2_COMP_SHUT
 
- TSADCV2_DATA
 
- TSADCV2_DATA_MASK
 
- TSADCV2_HIGHT_INT_DEBOUNCE
 
- TSADCV2_HIGHT_INT_DEBOUNCE_COUNT
 
- TSADCV2_HIGHT_TSHUT_DEBOUNCE
 
- TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT
 
- TSADCV2_INT_EN
 
- TSADCV2_INT_PD
 
- TSADCV2_INT_PD_CLEAR_MASK
 
- TSADCV2_INT_SRC_EN
 
- TSADCV2_SHUT_2CRU_SRC_EN
 
- TSADCV2_SHUT_2GPIO_SRC_EN
 
- TSADCV2_USER_CON
 
- TSADCV2_USER_INTER_PD_SOC
 
- TSADCV3_AUTO_PERIOD_HT_TIME
 
- TSADCV3_AUTO_PERIOD_TIME
 
- TSADCV3_AUTO_Q_SEL_EN
 
- TSADCV3_DATA_MASK
 
- TSADCV3_INT_PD_CLEAR_MASK
 
- TSAR_ELEMENT_TSAR_TYPE_DWRR
 
- TSAR_ELEMENT_TSAR_TYPE_ETS
 
- TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN
 
- TSAUXC_AUTT0
 
- TSAUXC_AUTT1
 
- TSAUXC_DISABLE
 
- TSAUXC_EN_CLK0
 
- TSAUXC_EN_CLK1
 
- TSAUXC_EN_TS0
 
- TSAUXC_EN_TS1
 
- TSAUXC_EN_TT0
 
- TSAUXC_EN_TT1
 
- TSAUXC_PLSG
 
- TSAUXC_SAMP_AUT0
 
- TSAUXC_SAMP_AUT1
 
- TSAUXC_ST0
 
- TSAUXC_ST1
 
- TSA_INTRG_FLAGS_CU_STATE_VALID
 
- TSA_INTRG_FLAGS_DEV_STATE_VALID
 
- TSA_INTRG_FLAGS_OP_STATE_VALID
 
- TSBE
 
- TSBITRATE0
 
- TSBITRATE1
 
- TSBITS
 
- TSBMAP_4M_BASE
 
- TSBMAP_8K_BASE
 
- TSB_CAS_TAG
 
- TSB_CAS_TAG_HIGH
 
- TSB_CONFIG_MAP_PTE
 
- TSB_CONFIG_MAP_VADDR
 
- TSB_CONFIG_NENTRIES
 
- TSB_CONFIG_REG_VAL
 
- TSB_CONFIG_RSS_LIMIT
 
- TSB_CONFIG_TSB
 
- TSB_EN
 
- TSB_ENTRY_ALIGNMENT
 
- TSB_EXTENSION_N
 
- TSB_EXTENSION_P
 
- TSB_EXTENSION_S
 
- TSB_FLAGS_CACHE_MISS
 
- TSB_FLAGS_COUNT_VALID
 
- TSB_FLAGS_DCW_OFFSET_VALID
 
- TSB_FLAGS_FORMAT
 
- TSB_FLAGS_TIME_VALID
 
- TSB_FORMAT
 
- TSB_FORMAT_DDPC
 
- TSB_FORMAT_INTRG
 
- TSB_FORMAT_IOSTAT
 
- TSB_FORMAT_NONE
 
- TSB_LOAD_QUAD
 
- TSB_LOAD_TAG
 
- TSB_LOAD_TAG_HIGH
 
- TSB_LOCK_TAG
 
- TSB_PASS_BITS
 
- TSB_REG
 
- TSB_STORE
 
- TSB_SWAP0
 
- TSB_SWAP1
 
- TSB_TAG_INVALID_BIT
 
- TSB_TAG_INVALID_HIGH
 
- TSB_TAG_LOCK_BIT
 
- TSB_TAG_LOCK_HIGH
 
- TSB_TAG_TARGET
 
- TSB_WRITE
 
- TSC
 
- TSC1
 
- TSC10_CMD_DATA1
 
- TSC10_CMD_RATE
 
- TSC10_CMD_RESET
 
- TSC10_RATE_100
 
- TSC10_RATE_130
 
- TSC10_RATE_150
 
- TSC10_RATE_30
 
- TSC10_RATE_50
 
- TSC10_RATE_80
 
- TSC10_RATE_POINT
 
- TSC2005_SPI_MAX_SPEED_HZ
 
- TSC2007_12BIT
 
- TSC2007_8BIT
 
- TSC2007_ACTIVATE_XN
 
- TSC2007_ACTIVATE_YN
 
- TSC2007_ACTIVATE_YP_XN
 
- TSC2007_ADC_OFF_IRQ_EN
 
- TSC2007_ADC_ON_IRQ_DIS0
 
- TSC2007_ADC_ON_IRQ_DIS1
 
- TSC2007_CHAN_IIO
 
- TSC2007_MEASURE_AUX
 
- TSC2007_MEASURE_TEMP0
 
- TSC2007_MEASURE_TEMP1
 
- TSC2007_MEASURE_X
 
- TSC2007_MEASURE_Y
 
- TSC2007_MEASURE_Z1
 
- TSC2007_MEASURE_Z2
 
- TSC2007_POWER_OFF_IRQ_EN
 
- TSC2007_SETUP
 
- TSC200X_CFR0_CLOCK_1MHZ
 
- TSC200X_CFR0_INITVALUE
 
- TSC200X_CFR0_PENMODE
 
- TSC200X_CFR0_PRECHARGE_276US
 
- TSC200X_CFR0_RESOLUTION12
 
- TSC200X_CFR0_RW_MASK
 
- TSC200X_CFR0_STABTIME_1MS
 
- TSC200X_CFR1_BATCHDELAY_4MS
 
- TSC200X_CFR1_INITVALUE
 
- TSC200X_CFR2_AVG_7
 
- TSC200X_CFR2_INITVALUE
 
- TSC200X_CFR2_MAVE_X
 
- TSC200X_CFR2_MAVE_Y
 
- TSC200X_CFR2_MAVE_Z
 
- TSC200X_CFR2_MEDIUM_15
 
- TSC200X_CMD
 
- TSC200X_CMD_12BIT
 
- TSC200X_CMD_NORMAL
 
- TSC200X_CMD_STOP
 
- TSC200X_DATA_REGS
 
- TSC200X_DEF_P_FUZZ
 
- TSC200X_DEF_RESISTOR
 
- TSC200X_DEF_X_FUZZ
 
- TSC200X_DEF_Y_FUZZ
 
- TSC200X_PENUP_TIME_MS
 
- TSC200X_REG_AUX
 
- TSC200X_REG_AUX_HIGH
 
- TSC200X_REG_AUX_LOW
 
- TSC200X_REG_CFR0
 
- TSC200X_REG_CFR1
 
- TSC200X_REG_CFR2
 
- TSC200X_REG_CONV_FUNC
 
- TSC200X_REG_PND0
 
- TSC200X_REG_READ
 
- TSC200X_REG_STATUS
 
- TSC200X_REG_TEMP1
 
- TSC200X_REG_TEMP2
 
- TSC200X_REG_TEMP_HIGH
 
- TSC200X_REG_TEMP_LOW
 
- TSC200X_REG_X
 
- TSC200X_REG_Y
 
- TSC200X_REG_Z1
 
- TSC200X_REG_Z2
 
- TSCADC_CELLS
 
- TSCAN1_ID1
 
- TSCAN1_ID1_VALUE
 
- TSCAN1_ID2
 
- TSCAN1_ID2_VALUE
 
- TSCAN1_JP4
 
- TSCAN1_JP5
 
- TSCAN1_JUMPERS
 
- TSCAN1_LED
 
- TSCAN1_MAXDEV
 
- TSCAN1_MODE
 
- TSCAN1_MODE_ENABLE
 
- TSCAN1_PAGE
 
- TSCAN1_PLD_ADDRESS
 
- TSCAN1_PLD_SIZE
 
- TSCAN1_SJA1000_SIZE
 
- TSCAN1_SJA1000_XTAL
 
- TSCAN1_VERSION
 
- TSCCU_CCU_SHIFT
 
- TSCFG4
 
- TSCFGH
 
- TSCFGL
 
- TSCFGM
 
- TSCL
 
- TSCL_ADDR
 
- TSCM_ADDR_BASE
 
- TSCM_MIDI_IN_PORT_MAX
 
- TSCM_MIDI_OUT_PORT_MAX
 
- TSCM_OFFSET_CLOCK_STATUS
 
- TSCM_OFFSET_FIRMWARE_ARM
 
- TSCM_OFFSET_FIRMWARE_FPGA
 
- TSCM_OFFSET_FIRMWARE_HW
 
- TSCM_OFFSET_FIRMWARE_REGISTER
 
- TSCM_OFFSET_ISOC_RX_CH
 
- TSCM_OFFSET_ISOC_RX_ON
 
- TSCM_OFFSET_ISOC_TX_CH
 
- TSCM_OFFSET_ISOC_TX_ON
 
- TSCM_OFFSET_LED_POWER
 
- TSCM_OFFSET_MIDI_RX_QUAD
 
- TSCM_OFFSET_MIDI_TX_ADDR_HI
 
- TSCM_OFFSET_MIDI_TX_ADDR_LO
 
- TSCM_OFFSET_MIDI_TX_ON
 
- TSCM_OFFSET_MULTIPLEX_MODE
 
- TSCM_OFFSET_RX_PCM_CHANNELS
 
- TSCM_OFFSET_SET_OPTION
 
- TSCM_OFFSET_START_STREAMING
 
- TSCM_OFFSET_TX_PCM_CHANNELS
 
- TSCM_OFFSET_UNKNOWN
 
- TSCR
 
- TSCR_ADEF
 
- TSCR_AFUL
 
- TSCR_AMM
 
- TSCR_ASM
 
- TSCR_DE
 
- TSCR_DEM
 
- TSCR_IACK
 
- TSCR_LOCK
 
- TSCR_MSKA
 
- TSCR_MSKL
 
- TSCR_MSKO
 
- TSCR_NBPACKETS
 
- TSCR_OVR
 
- TSCR_RST
 
- TSCR_RSTN
 
- TSCR_TTM
 
- TSCS42XX_FORMATS
 
- TSCS42XX_PLL_SRC_CNT
 
- TSCS42XX_PLL_SRC_MCLK1
 
- TSCS42XX_PLL_SRC_MCLK2
 
- TSCS42XX_PLL_SRC_XTAL
 
- TSCS42XX_RATES
 
- TSCS454_DAI1_ID
 
- TSCS454_DAI2_ID
 
- TSCS454_DAI3_ID
 
- TSCS454_DAI_COUNT
 
- TSCS454_FORMATS
 
- TSCS454_RATES
 
- TSCUSTAT_CTCSYNCING
 
- TSC_4WIRE_LEAVE
 
- TSC_4WIRE_POST_INDEX
 
- TSC_4WIRE_PRE_INDEX
 
- TSC_4WIRE_X_INDEX
 
- TSC_4WIRE_Y_INDEX
 
- TSC_ABT_CMD
 
- TSC_ACKI
 
- TSC_ADJUST_VALUE
 
- TSC_ALT_PERIOD
 
- TSC_ATNI
 
- TSC_BSYI
 
- TSC_CDI
 
- TSC_CELL
 
- TSC_CELL_DEC_ENABLE_0
 
- TSC_CELL_DEC_ENABLE_1
 
- TSC_CELL_EE_BOOST
 
- TSC_CELL_EE_ENABLE
 
- TSC_CMD_COMP
 
- TSC_DEFAULT_POLL_PERIOD
 
- TSC_DEFAULT_THRESHOLD
 
- TSC_DISABLE
 
- TSC_DIS_SCSIRST
 
- TSC_DIVISOR
 
- TSC_DMA_16BIT
 
- TSC_DMA_8BIT
 
- TSC_EN_BUS_IN
 
- TSC_EN_BUS_OUT
 
- TSC_EN_LATCH
 
- TSC_EN_RESEL
 
- TSC_EN_SCAM
 
- TSC_EN_SCSI2
 
- TSC_EN_SCSI_PAR
 
- TSC_EN_WDACK
 
- TSC_FLUSH_FIFO
 
- TSC_HW_RESELECT
 
- TSC_INITDEFAULT
 
- TSC_INITIATOR
 
- TSC_IOI
 
- TSC_IRQENB_MASK
 
- TSC_IRQ_MASK
 
- TSC_MAX_NUM
 
- TSC_MAX_SAMPLES
 
- TSC_MSGI
 
- TSC_MSG_ACCEPT
 
- TSC_MULTIPLIER
 
- TSC_MULTIPLIER_HIGH
 
- TSC_OFFSET
 
- TSC_OFFSET_HIGH
 
- TSC_OFFSET_VALUE
 
- TSC_PWDN
 
- TSC_RATIO_DEFAULT
 
- TSC_RATIO_MAX
 
- TSC_RATIO_MIN
 
- TSC_RATIO_RSVD
 
- TSC_REFERENCE_KHZ
 
- TSC_REQI
 
- TSC_RST_ACK
 
- TSC_RST_ATN
 
- TSC_RST_BSY
 
- TSC_RST_BUS
 
- TSC_RST_CHIP
 
- TSC_RST_SEQ
 
- TSC_SEL
 
- TSC_SELATNSTOP
 
- TSC_SELI
 
- TSC_SEL_ATN
 
- TSC_SEL_ATN3
 
- TSC_SEL_ATN3_DIRECT_IN
 
- TSC_SEL_ATN3_DIRECT_OUT
 
- TSC_SEL_ATNSTOP
 
- TSC_SEL_ATN_DIRECT_IN
 
- TSC_SEL_ATN_DIRECT_OUT
 
- TSC_SEL_ATN_DMA
 
- TSC_SET_ACK
 
- TSC_SET_ATN
 
- TSC_SLEEP
 
- TSC_TIMER
 
- TSC_WIDE_CPU
 
- TSC_WIDE_SCSI
 
- TSC_XF_DMA_IN
 
- TSC_XF_DMA_IN_DIRECT
 
- TSC_XF_DMA_OUT
 
- TSC_XF_DMA_OUT_DIRECT
 
- TSC_XF_FIFO_IN
 
- TSC_XF_FIFO_OUT
 
- TSDIVN
 
- TSDMAE
 
- TSDMAENABLE
 
- TSDM_REG_AGG_INT_EVENT_0
 
- TSDM_REG_AGG_INT_EVENT_1
 
- TSDM_REG_AGG_INT_EVENT_2
 
- TSDM_REG_AGG_INT_EVENT_3
 
- TSDM_REG_AGG_INT_EVENT_4
 
- TSDM_REG_AGG_INT_T_0
 
- TSDM_REG_AGG_INT_T_1
 
- TSDM_REG_CFC_RSP_START_ADDR
 
- TSDM_REG_CMP_COUNTER_MAX0
 
- TSDM_REG_CMP_COUNTER_MAX1
 
- TSDM_REG_CMP_COUNTER_MAX2
 
- TSDM_REG_CMP_COUNTER_MAX3
 
- TSDM_REG_CMP_COUNTER_START_ADDR
 
- TSDM_REG_DBG_DWORD_ENABLE
 
- TSDM_REG_DBG_FORCE_FRAME
 
- TSDM_REG_DBG_FORCE_VALID
 
- TSDM_REG_DBG_SELECT
 
- TSDM_REG_DBG_SHIFT
 
- TSDM_REG_ENABLE_IN1
 
- TSDM_REG_ENABLE_IN2
 
- TSDM_REG_ENABLE_OUT1
 
- TSDM_REG_ENABLE_OUT2
 
- TSDM_REG_INIT_CREDIT_PXP_CTRL
 
- TSDM_REG_NUM_OF_ACK_AFTER_PLACE
 
- TSDM_REG_NUM_OF_PKT_END_MSG
 
- TSDM_REG_NUM_OF_PXP_ASYNC_REQ
 
- TSDM_REG_NUM_OF_Q0_CMD
 
- TSDM_REG_NUM_OF_Q10_CMD
 
- TSDM_REG_NUM_OF_Q11_CMD
 
- TSDM_REG_NUM_OF_Q1_CMD
 
- TSDM_REG_NUM_OF_Q3_CMD
 
- TSDM_REG_NUM_OF_Q4_CMD
 
- TSDM_REG_NUM_OF_Q5_CMD
 
- TSDM_REG_NUM_OF_Q6_CMD
 
- TSDM_REG_NUM_OF_Q7_CMD
 
- TSDM_REG_NUM_OF_Q8_CMD
 
- TSDM_REG_NUM_OF_Q9_CMD
 
- TSDM_REG_PCK_END_MSG_START_ADDR
 
- TSDM_REG_Q_COUNTER_START_ADDR
 
- TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY
 
- TSDM_REG_SYNC_PARSER_EMPTY
 
- TSDM_REG_SYNC_SYNC_EMPTY
 
- TSDM_REG_TIMER_TICK
 
- TSDM_REG_TSDM_INT_MASK_0
 
- TSDM_REG_TSDM_INT_MASK_1
 
- TSDM_REG_TSDM_INT_STS_0
 
- TSDM_REG_TSDM_INT_STS_1
 
- TSDM_REG_TSDM_PRTY_MASK
 
- TSDM_REG_TSDM_PRTY_STS
 
- TSDM_REG_TSDM_PRTY_STS_CLR
 
- TSDM_TIMER_TICK_RESUL_CHIP
 
- TSD_EXTENSION
 
- TSD_FIXED
 
- TSD_NBR
 
- TSE
 
- TSE2004_DEVID
 
- TSE2004_DEVID_MASK
 
- TSE850_DAPM_SINGLE_EXT
 
- TSEG_ENABLE
 
- TSEMI_CLK1_RESUL_CHIP
 
- TSEM_REG_ARB_CYCLE_SIZE
 
- TSEM_REG_ARB_ELEMENT0
 
- TSEM_REG_ARB_ELEMENT1
 
- TSEM_REG_ARB_ELEMENT2
 
- TSEM_REG_ARB_ELEMENT3
 
- TSEM_REG_ARB_ELEMENT4
 
- TSEM_REG_DBG_DWORD_ENABLE
 
- TSEM_REG_DBG_FORCE_FRAME
 
- TSEM_REG_DBG_FORCE_VALID
 
- TSEM_REG_DBG_FRAME_MODE_BB_K2
 
- TSEM_REG_DBG_MODE1_CFG_BB_K2
 
- TSEM_REG_DBG_SELECT
 
- TSEM_REG_DBG_SHIFT
 
- TSEM_REG_ENABLE_IN
 
- TSEM_REG_ENABLE_OUT
 
- TSEM_REG_FAST_MEMORY
 
- TSEM_REG_FIC0_DISABLE
 
- TSEM_REG_FIC1_DISABLE
 
- TSEM_REG_INT_TABLE
 
- TSEM_REG_MSG_NUM_FIC0
 
- TSEM_REG_MSG_NUM_FIC1
 
- TSEM_REG_MSG_NUM_FOC0
 
- TSEM_REG_MSG_NUM_FOC1
 
- TSEM_REG_MSG_NUM_FOC2
 
- TSEM_REG_MSG_NUM_FOC3
 
- TSEM_REG_PASSIVE_BUFFER
 
- TSEM_REG_PAS_DISABLE
 
- TSEM_REG_PRAM
 
- TSEM_REG_SLEEP_THREADS_VALID
 
- TSEM_REG_SLOW_DBG_ACTIVE_BB_K2
 
- TSEM_REG_SLOW_DBG_EMPTY_BB_K2
 
- TSEM_REG_SLOW_DBG_MODE_BB_K2
 
- TSEM_REG_SLOW_EXT_STORE_EMPTY
 
- TSEM_REG_SYNC_DBG_EMPTY
 
- TSEM_REG_THREADS_LIST
 
- TSEM_REG_TSEM_INT_MASK_0
 
- TSEM_REG_TSEM_INT_MASK_1
 
- TSEM_REG_TSEM_INT_STS_0
 
- TSEM_REG_TSEM_INT_STS_1
 
- TSEM_REG_TSEM_PRTY_MASK_0
 
- TSEM_REG_TSEM_PRTY_MASK_1
 
- TSEM_REG_TSEM_PRTY_STS_0
 
- TSEM_REG_TSEM_PRTY_STS_1
 
- TSEM_REG_TSEM_PRTY_STS_CLR_0
 
- TSEM_REG_TSEM_PRTY_STS_CLR_1
 
- TSEM_REG_TS_0_AS
 
- TSEM_REG_TS_10_AS
 
- TSEM_REG_TS_11_AS
 
- TSEM_REG_TS_12_AS
 
- TSEM_REG_TS_13_AS
 
- TSEM_REG_TS_14_AS
 
- TSEM_REG_TS_15_AS
 
- TSEM_REG_TS_16_AS
 
- TSEM_REG_TS_17_AS
 
- TSEM_REG_TS_18_AS
 
- TSEM_REG_TS_1_AS
 
- TSEM_REG_TS_2_AS
 
- TSEM_REG_TS_3_AS
 
- TSEM_REG_TS_4_AS
 
- TSEM_REG_TS_5_AS
 
- TSEM_REG_TS_6_AS
 
- TSEM_REG_TS_7_AS
 
- TSEM_REG_TS_8_AS
 
- TSEM_REG_TS_9_AS
 
- TSEM_REG_VFPF_ERR_NUM
 
- TSENS_EN
 
- TSENS_SW_RST
 
- TSER_SNM
 
- TSER_SNS
 
- TSE_BUSY_CYCLES
 
- TSE_CLIPPED_PRIM
 
- TSE_EN
 
- TSE_FACENESS_CULLED_PRIM
 
- TSE_INPUT_NULL_PRIM
 
- TSE_INPUT_PRIM
 
- TSE_NEW_PRIM
 
- TSE_NUM_REGS
 
- TSE_OUTPUT_NULL_PRIM
 
- TSE_OUTPUT_VISIBLE_PRIM
 
- TSE_PCS_CONTROL_AN_EN_MASK
 
- TSE_PCS_CONTROL_REG
 
- TSE_PCS_CONTROL_RESTART_AN_MASK
 
- TSE_PCS_CTRL_AUTONEG_SGMII
 
- TSE_PCS_IF_MODE_REG
 
- TSE_PCS_IF_USE_SGMII
 
- TSE_PCS_LINK_TIMER_0_REG
 
- TSE_PCS_LINK_TIMER_1_REG
 
- TSE_PCS_PARTNER_ABILITY_REG
 
- TSE_PCS_PARTNER_DUPLEX_FULL
 
- TSE_PCS_PARTNER_DUPLEX_HALF
 
- TSE_PCS_PARTNER_DUPLEX_MASK
 
- TSE_PCS_PARTNER_SPEED_10
 
- TSE_PCS_PARTNER_SPEED_100
 
- TSE_PCS_PARTNER_SPEED_1000
 
- TSE_PCS_PARTNER_SPEED_MASK
 
- TSE_PCS_SGMII_LINK_TIMER_0
 
- TSE_PCS_SGMII_LINK_TIMER_1
 
- TSE_PCS_SGMII_SPEED_10
 
- TSE_PCS_SGMII_SPEED_100
 
- TSE_PCS_SGMII_SPEED_1000
 
- TSE_PCS_SGMII_SPEED_MASK
 
- TSE_PCS_SIZE
 
- TSE_PCS_STATUS_AN_COMPLETED_MASK
 
- TSE_PCS_STATUS_LINK_MASK
 
- TSE_PCS_STATUS_REG
 
- TSE_PCS_SW_RESET_TIMEOUT
 
- TSE_PCS_SW_RST_MASK
 
- TSE_PCS_USE_SGMII_AN_MASK
 
- TSE_PCS_USE_SGMII_ENA
 
- TSE_PC_STARVE
 
- TSE_POST_CLIP_PRIM
 
- TSE_PRE_CLIP_PRIM
 
- TSE_RAS_STALL
 
- TSE_STALL_BARYPLANE_FIFO_FULL
 
- TSE_STALL_ZPLANE_FIFO_FULL
 
- TSE_STATS_LEN
 
- TSE_TRIVAL_REJ_PRIM
 
- TSE_TX_THRESH
 
- TSE_ZERO_AREA_PRIM
 
- TSE_ZERO_PIXEL_PRIM
 
- TSFEN
 
- TSFIFO_LINEOK
 
- TSFLAGS_ANY
 
- TSFR
 
- TSFR1
 
- TSFRCR
 
- TSFRST
 
- TSFR_8723B
 
- TSFS
 
- TSFS_INTR_MASK
 
- TSFS_SLOPE_MASK
 
- TSFS_SLOPE_SHIFT
 
- TSFTR
 
- TSFTR1_RST
 
- TSFTR_RST
 
- TSF_DATA_SIZE
 
- TSF_ID_A
 
- TSF_ID_B
 
- TSF_ID_C
 
- TSF_ID_D
 
- TSF_SYNC_ADHOC
 
- TSF_SYNC_AP_NONE
 
- TSF_SYNC_INFRA
 
- TSF_SYNC_NONE
 
- TSF_TIMER_DW0
 
- TSF_TIMER_DW0_LOW_WORD
 
- TSF_TIMER_DW1
 
- TSF_TIMER_DW1_HIGH_WORD
 
- TSF_TO_TU
 
- TSF_UPDATE
 
- TSGPEN_CRIT_LOHI
 
- TSGPEN_HOT_LOHI
 
- TSHUT_HIGH_ACTIVE
 
- TSHUT_LOW_ACTIVE
 
- TSHUT_MODE_CRU
 
- TSHUT_MODE_GPIO
 
- TSI0_DATA0
 
- TSI108_CG_PWRUP_STATUS
 
- TSI108_CLK_OFFSET
 
- TSI108_CLK_SIZE
 
- TSI108_CPU_BASE
 
- TSI108_CPU_CURRENT_TASK_PRI
 
- TSI108_CPU_EOI
 
- TSI108_CPU_INTACK
 
- TSI108_CPU_IPI_DISPATCH_0
 
- TSI108_CPU_IPI_DISPATCH_STRIDE
 
- TSI108_CPU_MCACK
 
- TSI108_CPU_STRIDE
 
- TSI108_CPU_WHOAMI
 
- TSI108_DMA_OFFSET
 
- TSI108_DMA_SIZE
 
- TSI108_EC_HASHADDR
 
- TSI108_EC_HASHADDR_AUTOINC
 
- TSI108_EC_HASHADDR_DO1STREAD
 
- TSI108_EC_HASHADDR_MCAST
 
- TSI108_EC_HASHADDR_UNICAST
 
- TSI108_EC_HASHDATA
 
- TSI108_EC_INTMASK
 
- TSI108_EC_INTSTAT
 
- TSI108_EC_PORTCTRL
 
- TSI108_EC_PORTCTRL_HALFDUPLEX
 
- TSI108_EC_PORTCTRL_NOGIG
 
- TSI108_EC_PORTCTRL_STATEN
 
- TSI108_EC_PORTCTRL_STATRST
 
- TSI108_EC_RXCFG
 
- TSI108_EC_RXCFG_BFE
 
- TSI108_EC_RXCFG_MC_HASH
 
- TSI108_EC_RXCFG_MFE
 
- TSI108_EC_RXCFG_RST
 
- TSI108_EC_RXCFG_SE
 
- TSI108_EC_RXCFG_UC_HASH
 
- TSI108_EC_RXCFG_UFE
 
- TSI108_EC_RXCTRL
 
- TSI108_EC_RXCTRL_ABORT
 
- TSI108_EC_RXCTRL_GO
 
- TSI108_EC_RXCTRL_QUEUE0
 
- TSI108_EC_RXERR
 
- TSI108_EC_RXESTAT
 
- TSI108_EC_RXESTAT_Q0_DESCINT
 
- TSI108_EC_RXESTAT_Q0_EOF
 
- TSI108_EC_RXESTAT_Q0_EOQ
 
- TSI108_EC_RXESTAT_Q0_ERR
 
- TSI108_EC_RXQ_BUFCFG
 
- TSI108_EC_RXQ_BUFCFG_BSWP
 
- TSI108_EC_RXQ_BUFCFG_BURST128
 
- TSI108_EC_RXQ_BUFCFG_BURST256
 
- TSI108_EC_RXQ_BUFCFG_BURST32
 
- TSI108_EC_RXQ_BUFCFG_BURST8
 
- TSI108_EC_RXQ_BUFCFG_SFNPORT
 
- TSI108_EC_RXQ_BUFCFG_WSWP
 
- TSI108_EC_RXQ_CFG
 
- TSI108_EC_RXQ_CFG_BSWP
 
- TSI108_EC_RXQ_CFG_DESC_INT
 
- TSI108_EC_RXQ_CFG_EOQ_OWN_INT
 
- TSI108_EC_RXQ_CFG_SFNPORT
 
- TSI108_EC_RXQ_CFG_WSWP
 
- TSI108_EC_RXQ_PTRHIGH
 
- TSI108_EC_RXQ_PTRHIGH_VALID
 
- TSI108_EC_RXQ_PTRLOW
 
- TSI108_EC_RXSTAT
 
- TSI108_EC_RXSTAT_ACTIVE
 
- TSI108_EC_RXSTAT_QUEUE0
 
- TSI108_EC_TXCFG
 
- TSI108_EC_TXCFG_RST
 
- TSI108_EC_TXCTRL
 
- TSI108_EC_TXCTRL_ABORT
 
- TSI108_EC_TXCTRL_GO
 
- TSI108_EC_TXCTRL_IDLEINT
 
- TSI108_EC_TXCTRL_QUEUE0
 
- TSI108_EC_TXERR
 
- TSI108_EC_TXESTAT
 
- TSI108_EC_TXESTAT_Q0_DESCINT
 
- TSI108_EC_TXESTAT_Q0_EOF
 
- TSI108_EC_TXESTAT_Q0_EOQ
 
- TSI108_EC_TXESTAT_Q0_ERR
 
- TSI108_EC_TXQ_BUFCFG
 
- TSI108_EC_TXQ_BUFCFG_BSWP
 
- TSI108_EC_TXQ_BUFCFG_BURST128
 
- TSI108_EC_TXQ_BUFCFG_BURST256
 
- TSI108_EC_TXQ_BUFCFG_BURST32
 
- TSI108_EC_TXQ_BUFCFG_BURST8
 
- TSI108_EC_TXQ_BUFCFG_SFNPORT
 
- TSI108_EC_TXQ_BUFCFG_WSWP
 
- TSI108_EC_TXQ_CFG
 
- TSI108_EC_TXQ_CFG_BSWP
 
- TSI108_EC_TXQ_CFG_DESC_INT
 
- TSI108_EC_TXQ_CFG_EOQ_OWN_INT
 
- TSI108_EC_TXQ_CFG_SFNPORT
 
- TSI108_EC_TXQ_CFG_WSWP
 
- TSI108_EC_TXQ_PTRHIGH
 
- TSI108_EC_TXQ_PTRHIGH_VALID
 
- TSI108_EC_TXQ_PTRLOW
 
- TSI108_EC_TXSTAT
 
- TSI108_EC_TXSTAT_ACTIVE
 
- TSI108_EC_TXSTAT_QUEUE0
 
- TSI108_EC_TXTHRESH
 
- TSI108_EC_TXTHRESH_STARTFILL
 
- TSI108_EC_TXTHRESH_STOPFILL
 
- TSI108_ETH_OFFSET
 
- TSI108_ETH_PORT_NUM
 
- TSI108_ETH_SIZE
 
- TSI108_GPIO_OFFSET
 
- TSI108_GPIO_SIZE
 
- TSI108_GREG_BASE
 
- TSI108_GREG_FEATURE_0
 
- TSI108_GREG_GLOBAL_CONF_0
 
- TSI108_GREG_IPI_STRIDE
 
- TSI108_GREG_IPI_VECTOR_PRI_0
 
- TSI108_GREG_SPURIOUS
 
- TSI108_GREG_TIMER_FREQ
 
- TSI108_GREG_VENDOR_ID
 
- TSI108_HLP_OFFSET
 
- TSI108_HLP_SIZE
 
- TSI108_I2C_OFFSET
 
- TSI108_I2C_SIZE
 
- TSI108_INT_ANY
 
- TSI108_INT_RXABORT
 
- TSI108_INT_RXERROR
 
- TSI108_INT_RXIDLE
 
- TSI108_INT_RXOVERRUN
 
- TSI108_INT_RXQUEUE0
 
- TSI108_INT_RXTHRESH
 
- TSI108_INT_RXWAIT
 
- TSI108_INT_SFN
 
- TSI108_INT_STATCARRY
 
- TSI108_INT_TXABORT
 
- TSI108_INT_TXERROR
 
- TSI108_INT_TXIDLE
 
- TSI108_INT_TXQUEUE0
 
- TSI108_INT_TXTHRESH
 
- TSI108_INT_TXUNDERRUN
 
- TSI108_INT_TXWAIT
 
- TSI108_IRQ
 
- TSI108_IRQ_BASE
 
- TSI108_IRQ_DESTINATION
 
- TSI108_IRQ_DIRECTED
 
- TSI108_IRQ_DISTRIBUTED
 
- TSI108_IRQ_MODE
 
- TSI108_IRQ_REG_BASE
 
- TSI108_IRQ_SPURIOUS
 
- TSI108_IRQ_STRIDE
 
- TSI108_IRQ_VECTOR_PRI
 
- TSI108_MAC_ADDR1
 
- TSI108_MAC_ADDR2
 
- TSI108_MAC_CFG1
 
- TSI108_MAC_CFG1_LOOPBACK
 
- TSI108_MAC_CFG1_RXEN
 
- TSI108_MAC_CFG1_SOFTRST
 
- TSI108_MAC_CFG1_TXEN
 
- TSI108_MAC_CFG2
 
- TSI108_MAC_CFG2_DFLT_PREAMBLE
 
- TSI108_MAC_CFG2_FULLDUPLEX
 
- TSI108_MAC_CFG2_GIG
 
- TSI108_MAC_CFG2_IFACE_MASK
 
- TSI108_MAC_CFG2_NOGIG
 
- TSI108_MAC_CFG2_PADCRC
 
- TSI108_MAC_IFCTRL
 
- TSI108_MAC_IFCTRL_PHYMODE
 
- TSI108_MAC_MII_ADDR
 
- TSI108_MAC_MII_ADDR_PHY
 
- TSI108_MAC_MII_ADDR_REG
 
- TSI108_MAC_MII_CMD
 
- TSI108_MAC_MII_CMD_READ
 
- TSI108_MAC_MII_DATAIN
 
- TSI108_MAC_MII_DATAOUT
 
- TSI108_MAC_MII_IND
 
- TSI108_MAC_MII_IND_BUSY
 
- TSI108_MAC_MII_IND_NOTVALID
 
- TSI108_MAC_MII_IND_SCANNING
 
- TSI108_MAC_MII_MGMT_CFG
 
- TSI108_MAC_MII_MGMT_CLK
 
- TSI108_MAC_MII_MGMT_RST
 
- TSI108_MAX_VECTORS
 
- TSI108_MPIC_OFFSET
 
- TSI108_MPIC_SIZE
 
- TSI108_PBM_PORT
 
- TSI108_PB_AERR
 
- TSI108_PB_ERRCS
 
- TSI108_PB_ERRCS_ES
 
- TSI108_PB_ISR
 
- TSI108_PB_ISR_PBS_RD_ERR
 
- TSI108_PB_OFFSET
 
- TSI108_PB_SIZE
 
- TSI108_PCI_CFG_SIZE
 
- TSI108_PCI_CSR
 
- TSI108_PCI_IRP_CFG_CTL
 
- TSI108_PCI_IRP_ENABLE
 
- TSI108_PCI_IRP_ENABLE_P_INT
 
- TSI108_PCI_IRP_INTAD
 
- TSI108_PCI_IRP_STAT
 
- TSI108_PCI_IRP_STAT_P_INT
 
- TSI108_PCI_OFFSET
 
- TSI108_PCI_P2O_BAR0
 
- TSI108_PCI_P2O_BAR0_UPPER
 
- TSI108_PCI_P2O_BAR2
 
- TSI108_PCI_P2O_BAR2_UPPER
 
- TSI108_PCI_P2O_PAGE_SIZES
 
- TSI108_PCI_PFAB_BAR0
 
- TSI108_PCI_PFAB_BAR0_UPPER
 
- TSI108_PCI_PFAB_IO
 
- TSI108_PCI_PFAB_IO_UPPER
 
- TSI108_PCI_PFAB_MEM32
 
- TSI108_PCI_PFAB_PFM3
 
- TSI108_PCI_PFAB_PFM4
 
- TSI108_PCI_SIZE
 
- TSI108_PHY_BCM54XX
 
- TSI108_PHY_MV88E
 
- TSI108_REG_SIZE
 
- TSI108_RXBUF_SIZE
 
- TSI108_RXRING_LEN
 
- TSI108_RX_BAD
 
- TSI108_RX_CRC
 
- TSI108_RX_EOF
 
- TSI108_RX_FTYPE
 
- TSI108_RX_HASH
 
- TSI108_RX_INT
 
- TSI108_RX_OVER
 
- TSI108_RX_OWN
 
- TSI108_RX_RUNT
 
- TSI108_RX_SKB_SIZE
 
- TSI108_RX_SOF
 
- TSI108_RX_TRUNC
 
- TSI108_RX_VLAN
 
- TSI108_SDRAM_PORT
 
- TSI108_SD_OFFSET
 
- TSI108_SD_SIZE
 
- TSI108_STAT_CARRY1
 
- TSI108_STAT_CARRY1_RXALIGN
 
- TSI108_STAT_CARRY1_RXBYTES
 
- TSI108_STAT_CARRY1_RXDROP
 
- TSI108_STAT_CARRY1_RXFCS
 
- TSI108_STAT_CARRY1_RXFRAG
 
- TSI108_STAT_CARRY1_RXJABBER
 
- TSI108_STAT_CARRY1_RXJUMBO
 
- TSI108_STAT_CARRY1_RXLENGTH
 
- TSI108_STAT_CARRY1_RXMCAST
 
- TSI108_STAT_CARRY1_RXPKTS
 
- TSI108_STAT_CARRY1_RXRUNT
 
- TSI108_STAT_CARRY2
 
- TSI108_STAT_CARRY2_TXBYTES
 
- TSI108_STAT_CARRY2_TXEXCOL
 
- TSI108_STAT_CARRY2_TXEXDEF
 
- TSI108_STAT_CARRY2_TXPAUSE
 
- TSI108_STAT_CARRY2_TXPKTS
 
- TSI108_STAT_CARRY2_TXTCOL
 
- TSI108_STAT_CARRYMASK1
 
- TSI108_STAT_CARRYMASK2
 
- TSI108_STAT_RXALIGN
 
- TSI108_STAT_RXALIGN_CARRY
 
- TSI108_STAT_RXBYTES
 
- TSI108_STAT_RXBYTES_CARRY
 
- TSI108_STAT_RXDROP
 
- TSI108_STAT_RXDROP_CARRY
 
- TSI108_STAT_RXFCS
 
- TSI108_STAT_RXFCS_CARRY
 
- TSI108_STAT_RXFRAG
 
- TSI108_STAT_RXFRAG_CARRY
 
- TSI108_STAT_RXJABBER
 
- TSI108_STAT_RXJABBER_CARRY
 
- TSI108_STAT_RXJUMBO
 
- TSI108_STAT_RXJUMBO_CARRY
 
- TSI108_STAT_RXLENGTH
 
- TSI108_STAT_RXLENGTH_CARRY
 
- TSI108_STAT_RXMCAST
 
- TSI108_STAT_RXMCAST_CARRY
 
- TSI108_STAT_RXPKTS
 
- TSI108_STAT_RXPKTS_CARRY
 
- TSI108_STAT_RXRUNT
 
- TSI108_STAT_RXRUNT_CARRY
 
- TSI108_STAT_TXBYTES
 
- TSI108_STAT_TXBYTES_CARRY
 
- TSI108_STAT_TXEXCOL
 
- TSI108_STAT_TXEXCOL_CARRY
 
- TSI108_STAT_TXEXDEF
 
- TSI108_STAT_TXEXDEF_CARRY
 
- TSI108_STAT_TXPAUSEDROP
 
- TSI108_STAT_TXPAUSEDROP_CARRY
 
- TSI108_STAT_TXPKTS
 
- TSI108_STAT_TXPKTS_CARRY
 
- TSI108_STAT_TXTCOL
 
- TSI108_STAT_TXTCOL_CARRY
 
- TSI108_TIMER_BASE
 
- TSI108_TIMER_BASE_CNT
 
- TSI108_TIMER_CURRENT_CNT
 
- TSI108_TIMER_DESTINATION
 
- TSI108_TIMER_STRIDE
 
- TSI108_TIMER_VECTOR_PRI
 
- TSI108_TXRING_LEN
 
- TSI108_TX_COL
 
- TSI108_TX_CRC
 
- TSI108_TX_EOF
 
- TSI108_TX_HUGE
 
- TSI108_TX_INT
 
- TSI108_TX_INT_FREQ
 
- TSI108_TX_LCOL
 
- TSI108_TX_OK
 
- TSI108_TX_OWN
 
- TSI108_TX_PAD
 
- TSI108_TX_RETRY
 
- TSI108_TX_RLIM
 
- TSI108_TX_SOF
 
- TSI108_TX_UNDER
 
- TSI108_TX_VLAN
 
- TSI108_UART0_OFFSET
 
- TSI108_UART0_SIZE
 
- TSI108_UART1_OFFSET
 
- TSI108_UART1_SIZE
 
- TSI108_VECPRI_POLARITY_MASK
 
- TSI108_VECPRI_POLARITY_NEGATIVE
 
- TSI108_VECPRI_POLARITY_POSITIVE
 
- TSI108_VECPRI_SENSE_EDGE
 
- TSI108_VECPRI_SENSE_LEVEL
 
- TSI108_VECPRI_SENSE_MASK
 
- TSI108_VECPRI_VECTOR_MASK
 
- TSI148_CBAR
 
- TSI148_CRCSR_CBAR_M
 
- TSI148_CRCSR_CSRBCR_BDFAILS
 
- TSI148_CRCSR_CSRBCR_BERRSC
 
- TSI148_CRCSR_CSRBCR_LRSTC
 
- TSI148_CRCSR_CSRBCR_MENC
 
- TSI148_CRCSR_CSRBCR_SFAILC
 
- TSI148_CRCSR_CSRBSR_BDFAILS
 
- TSI148_CRCSR_CSRBSR_BERRS
 
- TSI148_CRCSR_CSRBSR_LISTS
 
- TSI148_CRCSR_CSRBSR_MENS
 
- TSI148_CRCSR_CSRBSR_SFAILS
 
- TSI148_CSRBCR
 
- TSI148_CSRBSR
 
- TSI148_GCSR_CSR
 
- TSI148_GCSR_GAP
 
- TSI148_GCSR_GA_M
 
- TSI148_GCSR_GCTRL_BDFAILS
 
- TSI148_GCSR_GCTRL_LMI0S
 
- TSI148_GCSR_GCTRL_LMI1S
 
- TSI148_GCSR_GCTRL_LMI2S
 
- TSI148_GCSR_GCTRL_LMI3S
 
- TSI148_GCSR_GCTRL_LRST
 
- TSI148_GCSR_GCTRL_MBI0S
 
- TSI148_GCSR_GCTRL_MBI1S
 
- TSI148_GCSR_GCTRL_MBI2S
 
- TSI148_GCSR_GCTRL_MBI3S
 
- TSI148_GCSR_GCTRL_MEN
 
- TSI148_GCSR_GCTRL_SCON
 
- TSI148_GCSR_GCTRL_SFAILEN
 
- TSI148_GCSR_ID
 
- TSI148_GCSR_MBOX0
 
- TSI148_GCSR_MBOX1
 
- TSI148_GCSR_MBOX2
 
- TSI148_GCSR_MBOX3
 
- TSI148_GCSR_SEMA0
 
- TSI148_GCSR_SEMA1
 
- TSI148_H
 
- TSI148_LCSR_BCL
 
- TSI148_LCSR_BCU
 
- TSI148_LCSR_BPCTR
 
- TSI148_LCSR_BPCTR_BPCT_M
 
- TSI148_LCSR_BPGTR
 
- TSI148_LCSR_BPGTR_BPGT_M
 
- TSI148_LCSR_CBAL
 
- TSI148_LCSR_CBAL_M
 
- TSI148_LCSR_CBAU
 
- TSI148_LCSR_CRAT
 
- TSI148_LCSR_CRAT_EN
 
- TSI148_LCSR_CRGAT_AS_A16
 
- TSI148_LCSR_CRGAT_AS_A24
 
- TSI148_LCSR_CRGAT_AS_A32
 
- TSI148_LCSR_CRGAT_AS_A64
 
- TSI148_LCSR_CRGAT_AS_M
 
- TSI148_LCSR_CRGAT_DATA
 
- TSI148_LCSR_CRGAT_EN
 
- TSI148_LCSR_CRGAT_NPRIV
 
- TSI148_LCSR_CRGAT_PGM
 
- TSI148_LCSR_CRGAT_SUPR
 
- TSI148_LCSR_CROL
 
- TSI148_LCSR_CROL_M
 
- TSI148_LCSR_CROU
 
- TSI148_LCSR_CSRAT
 
- TSI148_LCSR_DBS_M
 
- TSI148_LCSR_DCDAL0
 
- TSI148_LCSR_DCDAL1
 
- TSI148_LCSR_DCDAU0
 
- TSI148_LCSR_DCDAU1
 
- TSI148_LCSR_DCLAL0
 
- TSI148_LCSR_DCLAL1
 
- TSI148_LCSR_DCLAL_M
 
- TSI148_LCSR_DCLAU0
 
- TSI148_LCSR_DCLAU1
 
- TSI148_LCSR_DCNT0
 
- TSI148_LCSR_DCNT1
 
- TSI148_LCSR_DCSAL0
 
- TSI148_LCSR_DCSAL1
 
- TSI148_LCSR_DCSAU0
 
- TSI148_LCSR_DCSAU1
 
- TSI148_LCSR_DCTL0
 
- TSI148_LCSR_DCTL1
 
- TSI148_LCSR_DCTL_ABT
 
- TSI148_LCSR_DCTL_DGO
 
- TSI148_LCSR_DCTL_MOD
 
- TSI148_LCSR_DCTL_PAU
 
- TSI148_LCSR_DCTL_PBKS_1024
 
- TSI148_LCSR_DCTL_PBKS_128
 
- TSI148_LCSR_DCTL_PBKS_2048
 
- TSI148_LCSR_DCTL_PBKS_256
 
- TSI148_LCSR_DCTL_PBKS_32
 
- TSI148_LCSR_DCTL_PBKS_4096
 
- TSI148_LCSR_DCTL_PBKS_512
 
- TSI148_LCSR_DCTL_PBKS_64
 
- TSI148_LCSR_DCTL_PBKS_M
 
- TSI148_LCSR_DCTL_PBOT_0
 
- TSI148_LCSR_DCTL_PBOT_1
 
- TSI148_LCSR_DCTL_PBOT_16
 
- TSI148_LCSR_DCTL_PBOT_2
 
- TSI148_LCSR_DCTL_PBOT_32
 
- TSI148_LCSR_DCTL_PBOT_4
 
- TSI148_LCSR_DCTL_PBOT_64
 
- TSI148_LCSR_DCTL_PBOT_8
 
- TSI148_LCSR_DCTL_PBOT_M
 
- TSI148_LCSR_DCTL_VBKS_1024
 
- TSI148_LCSR_DCTL_VBKS_128
 
- TSI148_LCSR_DCTL_VBKS_2048
 
- TSI148_LCSR_DCTL_VBKS_256
 
- TSI148_LCSR_DCTL_VBKS_32
 
- TSI148_LCSR_DCTL_VBKS_4096
 
- TSI148_LCSR_DCTL_VBKS_512
 
- TSI148_LCSR_DCTL_VBKS_64
 
- TSI148_LCSR_DCTL_VBKS_M
 
- TSI148_LCSR_DCTL_VBOT_0
 
- TSI148_LCSR_DCTL_VBOT_1
 
- TSI148_LCSR_DCTL_VBOT_16
 
- TSI148_LCSR_DCTL_VBOT_2
 
- TSI148_LCSR_DCTL_VBOT_32
 
- TSI148_LCSR_DCTL_VBOT_4
 
- TSI148_LCSR_DCTL_VBOT_64
 
- TSI148_LCSR_DCTL_VBOT_8
 
- TSI148_LCSR_DCTL_VBOT_M
 
- TSI148_LCSR_DDAL0
 
- TSI148_LCSR_DDAL1
 
- TSI148_LCSR_DDAT0
 
- TSI148_LCSR_DDAT1
 
- TSI148_LCSR_DDAT_2eSSTM_160
 
- TSI148_LCSR_DDAT_2eSSTM_267
 
- TSI148_LCSR_DDAT_2eSSTM_320
 
- TSI148_LCSR_DDAT_2eSSTM_M
 
- TSI148_LCSR_DDAT_AMODE_A16
 
- TSI148_LCSR_DDAT_AMODE_A24
 
- TSI148_LCSR_DDAT_AMODE_A32
 
- TSI148_LCSR_DDAT_AMODE_A64
 
- TSI148_LCSR_DDAT_AMODE_CRCSR
 
- TSI148_LCSR_DDAT_AMODE_M
 
- TSI148_LCSR_DDAT_AMODE_USER1
 
- TSI148_LCSR_DDAT_AMODE_USER2
 
- TSI148_LCSR_DDAT_AMODE_USER3
 
- TSI148_LCSR_DDAT_AMODE_USER4
 
- TSI148_LCSR_DDAT_DBW_16
 
- TSI148_LCSR_DDAT_DBW_32
 
- TSI148_LCSR_DDAT_DBW_M
 
- TSI148_LCSR_DDAT_PGM
 
- TSI148_LCSR_DDAT_SUP
 
- TSI148_LCSR_DDAT_TM_2eSST
 
- TSI148_LCSR_DDAT_TM_2eSSTB
 
- TSI148_LCSR_DDAT_TM_2eVME
 
- TSI148_LCSR_DDAT_TM_BLT
 
- TSI148_LCSR_DDAT_TM_M
 
- TSI148_LCSR_DDAT_TM_MBLT
 
- TSI148_LCSR_DDAT_TM_SCT
 
- TSI148_LCSR_DDAT_TYP_PCI
 
- TSI148_LCSR_DDAT_TYP_VME
 
- TSI148_LCSR_DDAU0
 
- TSI148_LCSR_DDAU1
 
- TSI148_LCSR_DDBS0
 
- TSI148_LCSR_DDBS1
 
- TSI148_LCSR_DMA0
 
- TSI148_LCSR_DMA1
 
- TSI148_LCSR_DNLAL0
 
- TSI148_LCSR_DNLAL1
 
- TSI148_LCSR_DNLAL_DNLAL_M
 
- TSI148_LCSR_DNLAL_LLA
 
- TSI148_LCSR_DNLAU0
 
- TSI148_LCSR_DNLAU1
 
- TSI148_LCSR_DSAL0
 
- TSI148_LCSR_DSAL1
 
- TSI148_LCSR_DSAT0
 
- TSI148_LCSR_DSAT1
 
- TSI148_LCSR_DSAT_2eSSTM_160
 
- TSI148_LCSR_DSAT_2eSSTM_267
 
- TSI148_LCSR_DSAT_2eSSTM_320
 
- TSI148_LCSR_DSAT_2eSSTM_M
 
- TSI148_LCSR_DSAT_AMODE_A16
 
- TSI148_LCSR_DSAT_AMODE_A24
 
- TSI148_LCSR_DSAT_AMODE_A32
 
- TSI148_LCSR_DSAT_AMODE_A64
 
- TSI148_LCSR_DSAT_AMODE_CRCSR
 
- TSI148_LCSR_DSAT_AMODE_M
 
- TSI148_LCSR_DSAT_AMODE_USER1
 
- TSI148_LCSR_DSAT_AMODE_USER2
 
- TSI148_LCSR_DSAT_AMODE_USER3
 
- TSI148_LCSR_DSAT_AMODE_USER4
 
- TSI148_LCSR_DSAT_DBW_16
 
- TSI148_LCSR_DSAT_DBW_32
 
- TSI148_LCSR_DSAT_DBW_M
 
- TSI148_LCSR_DSAT_NIN
 
- TSI148_LCSR_DSAT_PGM
 
- TSI148_LCSR_DSAT_PSZ
 
- TSI148_LCSR_DSAT_SUP
 
- TSI148_LCSR_DSAT_TM_2eSST
 
- TSI148_LCSR_DSAT_TM_2eSSTB
 
- TSI148_LCSR_DSAT_TM_2eVME
 
- TSI148_LCSR_DSAT_TM_BLT
 
- TSI148_LCSR_DSAT_TM_M
 
- TSI148_LCSR_DSAT_TM_MBLT
 
- TSI148_LCSR_DSAT_TM_SCT
 
- TSI148_LCSR_DSAT_TYP_M
 
- TSI148_LCSR_DSAT_TYP_PAT
 
- TSI148_LCSR_DSAT_TYP_PCI
 
- TSI148_LCSR_DSAT_TYP_VME
 
- TSI148_LCSR_DSAU0
 
- TSI148_LCSR_DSAU1
 
- TSI148_LCSR_DSTA0
 
- TSI148_LCSR_DSTA1
 
- TSI148_LCSR_DSTA_ABT
 
- TSI148_LCSR_DSTA_BSY
 
- TSI148_LCSR_DSTA_DON
 
- TSI148_LCSR_DSTA_MRC
 
- TSI148_LCSR_DSTA_PAU
 
- TSI148_LCSR_DSTA_RTA
 
- TSI148_LCSR_DSTA_SMA
 
- TSI148_LCSR_DSTA_VBE
 
- TSI148_LCSR_EDPAL
 
- TSI148_LCSR_EDPAT
 
- TSI148_LCSR_EDPAT_EDPCL
 
- TSI148_LCSR_EDPAU
 
- TSI148_LCSR_EDPXA
 
- TSI148_LCSR_EDPXS
 
- TSI148_LCSR_GBAL
 
- TSI148_LCSR_GBAL_M
 
- TSI148_LCSR_GBAU
 
- TSI148_LCSR_GCSRAT
 
- TSI148_LCSR_GCSRAT_AS_A16
 
- TSI148_LCSR_GCSRAT_AS_A24
 
- TSI148_LCSR_GCSRAT_AS_A32
 
- TSI148_LCSR_GCSRAT_AS_A64
 
- TSI148_LCSR_GCSRAT_AS_M
 
- TSI148_LCSR_GCSRAT_DATA
 
- TSI148_LCSR_GCSRAT_EN
 
- TSI148_LCSR_GCSRAT_NPRIV
 
- TSI148_LCSR_GCSRAT_PGM
 
- TSI148_LCSR_GCSRAT_SUPR
 
- TSI148_LCSR_INTC
 
- TSI148_LCSR_INTC_ACFLC
 
- TSI148_LCSR_INTC_DMA0C
 
- TSI148_LCSR_INTC_DMA1C
 
- TSI148_LCSR_INTC_IACKC
 
- TSI148_LCSR_INTC_LM0C
 
- TSI148_LCSR_INTC_LM1C
 
- TSI148_LCSR_INTC_LM2C
 
- TSI148_LCSR_INTC_LM3C
 
- TSI148_LCSR_INTC_MB0C
 
- TSI148_LCSR_INTC_MB1C
 
- TSI148_LCSR_INTC_MB2C
 
- TSI148_LCSR_INTC_MB3C
 
- TSI148_LCSR_INTC_PERRC
 
- TSI148_LCSR_INTC_SYSFLC
 
- TSI148_LCSR_INTC_VERRC
 
- TSI148_LCSR_INTC_VIEC
 
- TSI148_LCSR_INTEN
 
- TSI148_LCSR_INTEN_ACFLEN
 
- TSI148_LCSR_INTEN_DMA0EN
 
- TSI148_LCSR_INTEN_DMA1EN
 
- TSI148_LCSR_INTEN_IACKEN
 
- TSI148_LCSR_INTEN_IRQ1EN
 
- TSI148_LCSR_INTEN_IRQ2EN
 
- TSI148_LCSR_INTEN_IRQ3EN
 
- TSI148_LCSR_INTEN_IRQ4EN
 
- TSI148_LCSR_INTEN_IRQ5EN
 
- TSI148_LCSR_INTEN_IRQ6EN
 
- TSI148_LCSR_INTEN_IRQ7EN
 
- TSI148_LCSR_INTEN_LM0EN
 
- TSI148_LCSR_INTEN_LM1EN
 
- TSI148_LCSR_INTEN_LM2EN
 
- TSI148_LCSR_INTEN_LM3EN
 
- TSI148_LCSR_INTEN_MB0EN
 
- TSI148_LCSR_INTEN_MB1EN
 
- TSI148_LCSR_INTEN_MB2EN
 
- TSI148_LCSR_INTEN_MB3EN
 
- TSI148_LCSR_INTEN_PERREN
 
- TSI148_LCSR_INTEN_SYSFLEN
 
- TSI148_LCSR_INTEN_VERREN
 
- TSI148_LCSR_INTEN_VIEEN
 
- TSI148_LCSR_INTEO
 
- TSI148_LCSR_INTEO_ACFLEO
 
- TSI148_LCSR_INTEO_DMA0EO
 
- TSI148_LCSR_INTEO_DMA1EO
 
- TSI148_LCSR_INTEO_IACKEO
 
- TSI148_LCSR_INTEO_IRQ1EO
 
- TSI148_LCSR_INTEO_IRQ2EO
 
- TSI148_LCSR_INTEO_IRQ3EO
 
- TSI148_LCSR_INTEO_IRQ4EO
 
- TSI148_LCSR_INTEO_IRQ5EO
 
- TSI148_LCSR_INTEO_IRQ6EO
 
- TSI148_LCSR_INTEO_IRQ7EO
 
- TSI148_LCSR_INTEO_LM0EO
 
- TSI148_LCSR_INTEO_LM1EO
 
- TSI148_LCSR_INTEO_LM2EO
 
- TSI148_LCSR_INTEO_LM3EO
 
- TSI148_LCSR_INTEO_MB0EO
 
- TSI148_LCSR_INTEO_MB1EO
 
- TSI148_LCSR_INTEO_MB2EO
 
- TSI148_LCSR_INTEO_MB3EO
 
- TSI148_LCSR_INTEO_PERREO
 
- TSI148_LCSR_INTEO_SYSFLEO
 
- TSI148_LCSR_INTEO_VERREO
 
- TSI148_LCSR_INTEO_VIEEO
 
- TSI148_LCSR_INTM1
 
- TSI148_LCSR_INTM1_DMA0M_M
 
- TSI148_LCSR_INTM1_DMA1M_M
 
- TSI148_LCSR_INTM1_LM0M_M
 
- TSI148_LCSR_INTM1_LM1M_M
 
- TSI148_LCSR_INTM1_LM2M_M
 
- TSI148_LCSR_INTM1_LM3M_M
 
- TSI148_LCSR_INTM1_MB0M_M
 
- TSI148_LCSR_INTM1_MB1M_M
 
- TSI148_LCSR_INTM1_MB2M_M
 
- TSI148_LCSR_INTM1_MB3M_M
 
- TSI148_LCSR_INTM2
 
- TSI148_LCSR_INTM2_ACFLM_M
 
- TSI148_LCSR_INTM2_IACKM_M
 
- TSI148_LCSR_INTM2_IRQ1M_M
 
- TSI148_LCSR_INTM2_IRQ2M_M
 
- TSI148_LCSR_INTM2_IRQ3M_M
 
- TSI148_LCSR_INTM2_IRQ4M_M
 
- TSI148_LCSR_INTM2_IRQ5M_M
 
- TSI148_LCSR_INTM2_IRQ6M_M
 
- TSI148_LCSR_INTM2_IRQ7M_M
 
- TSI148_LCSR_INTM2_PERRM_M
 
- TSI148_LCSR_INTM2_SYSFLM_M
 
- TSI148_LCSR_INTM2_VERRM_M
 
- TSI148_LCSR_INTM2_VIEM_M
 
- TSI148_LCSR_INTS
 
- TSI148_LCSR_INTS_ACFLS
 
- TSI148_LCSR_INTS_DMA0S
 
- TSI148_LCSR_INTS_DMA1S
 
- TSI148_LCSR_INTS_IACKS
 
- TSI148_LCSR_INTS_IRQ1S
 
- TSI148_LCSR_INTS_IRQ2S
 
- TSI148_LCSR_INTS_IRQ3S
 
- TSI148_LCSR_INTS_IRQ4S
 
- TSI148_LCSR_INTS_IRQ5S
 
- TSI148_LCSR_INTS_IRQ6S
 
- TSI148_LCSR_INTS_IRQ7S
 
- TSI148_LCSR_INTS_LM0S
 
- TSI148_LCSR_INTS_LM1S
 
- TSI148_LCSR_INTS_LM2S
 
- TSI148_LCSR_INTS_LM3S
 
- TSI148_LCSR_INTS_MB0S
 
- TSI148_LCSR_INTS_MB1S
 
- TSI148_LCSR_INTS_MB2S
 
- TSI148_LCSR_INTS_MB3S
 
- TSI148_LCSR_INTS_PERRS
 
- TSI148_LCSR_INTS_SYSFLS
 
- TSI148_LCSR_INTS_VERRS
 
- TSI148_LCSR_INTS_VIES
 
- TSI148_LCSR_IT0
 
- TSI148_LCSR_IT0_ITAT
 
- TSI148_LCSR_IT0_ITEAL
 
- TSI148_LCSR_IT0_ITEAU
 
- TSI148_LCSR_IT0_ITOFL
 
- TSI148_LCSR_IT0_ITOFU
 
- TSI148_LCSR_IT0_ITSAL
 
- TSI148_LCSR_IT0_ITSAU
 
- TSI148_LCSR_IT1
 
- TSI148_LCSR_IT1_ITAT
 
- TSI148_LCSR_IT1_ITEAL
 
- TSI148_LCSR_IT1_ITEAU
 
- TSI148_LCSR_IT1_ITOFL
 
- TSI148_LCSR_IT1_ITOFU
 
- TSI148_LCSR_IT1_ITSAL
 
- TSI148_LCSR_IT1_ITSAU
 
- TSI148_LCSR_IT2
 
- TSI148_LCSR_IT2_ITAT
 
- TSI148_LCSR_IT2_ITEAL
 
- TSI148_LCSR_IT2_ITEAU
 
- TSI148_LCSR_IT2_ITOFL
 
- TSI148_LCSR_IT2_ITOFU
 
- TSI148_LCSR_IT2_ITSAL
 
- TSI148_LCSR_IT2_ITSAU
 
- TSI148_LCSR_IT3
 
- TSI148_LCSR_IT3_ITAT
 
- TSI148_LCSR_IT3_ITEAL
 
- TSI148_LCSR_IT3_ITEAU
 
- TSI148_LCSR_IT3_ITOFL
 
- TSI148_LCSR_IT3_ITOFU
 
- TSI148_LCSR_IT3_ITSAL
 
- TSI148_LCSR_IT3_ITSAU
 
- TSI148_LCSR_IT4
 
- TSI148_LCSR_IT4_ITAT
 
- TSI148_LCSR_IT4_ITEAL
 
- TSI148_LCSR_IT4_ITEAU
 
- TSI148_LCSR_IT4_ITOFL
 
- TSI148_LCSR_IT4_ITOFU
 
- TSI148_LCSR_IT4_ITSAL
 
- TSI148_LCSR_IT4_ITSAU
 
- TSI148_LCSR_IT5
 
- TSI148_LCSR_IT5_ITAT
 
- TSI148_LCSR_IT5_ITEAL
 
- TSI148_LCSR_IT5_ITEAU
 
- TSI148_LCSR_IT5_ITOFL
 
- TSI148_LCSR_IT5_ITOFU
 
- TSI148_LCSR_IT5_ITSAL
 
- TSI148_LCSR_IT5_ITSAU
 
- TSI148_LCSR_IT6
 
- TSI148_LCSR_IT6_ITAT
 
- TSI148_LCSR_IT6_ITEAL
 
- TSI148_LCSR_IT6_ITEAU
 
- TSI148_LCSR_IT6_ITOFL
 
- TSI148_LCSR_IT6_ITOFU
 
- TSI148_LCSR_IT6_ITSAL
 
- TSI148_LCSR_IT6_ITSAU
 
- TSI148_LCSR_IT7
 
- TSI148_LCSR_IT7_ITAT
 
- TSI148_LCSR_IT7_ITEAL
 
- TSI148_LCSR_IT7_ITEAU
 
- TSI148_LCSR_IT7_ITOFL
 
- TSI148_LCSR_IT7_ITOFU
 
- TSI148_LCSR_IT7_ITSAL
 
- TSI148_LCSR_IT7_ITSAU
 
- TSI148_LCSR_ITAT_2eSST
 
- TSI148_LCSR_ITAT_2eSSTB
 
- TSI148_LCSR_ITAT_2eSSTM_160
 
- TSI148_LCSR_ITAT_2eSSTM_267
 
- TSI148_LCSR_ITAT_2eSSTM_320
 
- TSI148_LCSR_ITAT_2eSSTM_M
 
- TSI148_LCSR_ITAT_2eVME
 
- TSI148_LCSR_ITAT_AS_A16
 
- TSI148_LCSR_ITAT_AS_A24
 
- TSI148_LCSR_ITAT_AS_A32
 
- TSI148_LCSR_ITAT_AS_A64
 
- TSI148_LCSR_ITAT_AS_M
 
- TSI148_LCSR_ITAT_BLT
 
- TSI148_LCSR_ITAT_DATA
 
- TSI148_LCSR_ITAT_EN
 
- TSI148_LCSR_ITAT_MBLT
 
- TSI148_LCSR_ITAT_NPRIV
 
- TSI148_LCSR_ITAT_PGM
 
- TSI148_LCSR_ITAT_SUPR
 
- TSI148_LCSR_ITAT_TH
 
- TSI148_LCSR_ITAT_VFS_128
 
- TSI148_LCSR_ITAT_VFS_256
 
- TSI148_LCSR_ITAT_VFS_512
 
- TSI148_LCSR_ITAT_VFS_64
 
- TSI148_LCSR_ITAT_VFS_M
 
- TSI148_LCSR_ITEAL16_M
 
- TSI148_LCSR_ITEAL24_M
 
- TSI148_LCSR_ITEAL6432_M
 
- TSI148_LCSR_ITOFFL16_M
 
- TSI148_LCSR_ITOFFL24_M
 
- TSI148_LCSR_ITOFFL6432_M
 
- TSI148_LCSR_ITSAL16_M
 
- TSI148_LCSR_ITSAL24_M
 
- TSI148_LCSR_ITSAL6432_M
 
- TSI148_LCSR_LMAT
 
- TSI148_LCSR_LMAT_AS_A16
 
- TSI148_LCSR_LMAT_AS_A24
 
- TSI148_LCSR_LMAT_AS_A32
 
- TSI148_LCSR_LMAT_AS_A64
 
- TSI148_LCSR_LMAT_AS_M
 
- TSI148_LCSR_LMAT_DATA
 
- TSI148_LCSR_LMAT_EN
 
- TSI148_LCSR_LMAT_NPRIV
 
- TSI148_LCSR_LMAT_PGM
 
- TSI148_LCSR_LMAT_SUPR
 
- TSI148_LCSR_LMBAL
 
- TSI148_LCSR_LMBAL_M
 
- TSI148_LCSR_LMBAU
 
- TSI148_LCSR_OFFSET_DCDAL
 
- TSI148_LCSR_OFFSET_DCDAU
 
- TSI148_LCSR_OFFSET_DCLAL
 
- TSI148_LCSR_OFFSET_DCLAU
 
- TSI148_LCSR_OFFSET_DCNT
 
- TSI148_LCSR_OFFSET_DCSAL
 
- TSI148_LCSR_OFFSET_DCSAU
 
- TSI148_LCSR_OFFSET_DCTL
 
- TSI148_LCSR_OFFSET_DDAL
 
- TSI148_LCSR_OFFSET_DDAT
 
- TSI148_LCSR_OFFSET_DDAU
 
- TSI148_LCSR_OFFSET_DDBS
 
- TSI148_LCSR_OFFSET_DNLAL
 
- TSI148_LCSR_OFFSET_DNLAU
 
- TSI148_LCSR_OFFSET_DSAL
 
- TSI148_LCSR_OFFSET_DSAT
 
- TSI148_LCSR_OFFSET_DSAU
 
- TSI148_LCSR_OFFSET_DSTA
 
- TSI148_LCSR_OFFSET_ITAT
 
- TSI148_LCSR_OFFSET_ITEAL
 
- TSI148_LCSR_OFFSET_ITEAU
 
- TSI148_LCSR_OFFSET_ITOFL
 
- TSI148_LCSR_OFFSET_ITOFU
 
- TSI148_LCSR_OFFSET_ITSAL
 
- TSI148_LCSR_OFFSET_ITSAU
 
- TSI148_LCSR_OFFSET_OTAT
 
- TSI148_LCSR_OFFSET_OTBS
 
- TSI148_LCSR_OFFSET_OTEAL
 
- TSI148_LCSR_OFFSET_OTEAU
 
- TSI148_LCSR_OFFSET_OTOFL
 
- TSI148_LCSR_OFFSET_OTOFU
 
- TSI148_LCSR_OFFSET_OTSAL
 
- TSI148_LCSR_OFFSET_OTSAU
 
- TSI148_LCSR_OT0
 
- TSI148_LCSR_OT0_OTAT
 
- TSI148_LCSR_OT0_OTBS
 
- TSI148_LCSR_OT0_OTEAL
 
- TSI148_LCSR_OT0_OTEAU
 
- TSI148_LCSR_OT0_OTOFL
 
- TSI148_LCSR_OT0_OTOFU
 
- TSI148_LCSR_OT0_OTSAL
 
- TSI148_LCSR_OT0_OTSAU
 
- TSI148_LCSR_OT1
 
- TSI148_LCSR_OT1_OTAT
 
- TSI148_LCSR_OT1_OTBS
 
- TSI148_LCSR_OT1_OTEAL
 
- TSI148_LCSR_OT1_OTEAU
 
- TSI148_LCSR_OT1_OTOFL
 
- TSI148_LCSR_OT1_OTOFU
 
- TSI148_LCSR_OT1_OTSAL
 
- TSI148_LCSR_OT1_OTSAU
 
- TSI148_LCSR_OT2
 
- TSI148_LCSR_OT2_OTAT
 
- TSI148_LCSR_OT2_OTBS
 
- TSI148_LCSR_OT2_OTEAL
 
- TSI148_LCSR_OT2_OTEAU
 
- TSI148_LCSR_OT2_OTOFL
 
- TSI148_LCSR_OT2_OTOFU
 
- TSI148_LCSR_OT2_OTSAL
 
- TSI148_LCSR_OT2_OTSAU
 
- TSI148_LCSR_OT3
 
- TSI148_LCSR_OT3_OTAT
 
- TSI148_LCSR_OT3_OTBS
 
- TSI148_LCSR_OT3_OTEAL
 
- TSI148_LCSR_OT3_OTEAU
 
- TSI148_LCSR_OT3_OTOFL
 
- TSI148_LCSR_OT3_OTOFU
 
- TSI148_LCSR_OT3_OTSAL
 
- TSI148_LCSR_OT3_OTSAU
 
- TSI148_LCSR_OT4
 
- TSI148_LCSR_OT4_OTAT
 
- TSI148_LCSR_OT4_OTBS
 
- TSI148_LCSR_OT4_OTEAL
 
- TSI148_LCSR_OT4_OTEAU
 
- TSI148_LCSR_OT4_OTOFL
 
- TSI148_LCSR_OT4_OTOFU
 
- TSI148_LCSR_OT4_OTSAL
 
- TSI148_LCSR_OT4_OTSAU
 
- TSI148_LCSR_OT5
 
- TSI148_LCSR_OT5_OTAT
 
- TSI148_LCSR_OT5_OTBS
 
- TSI148_LCSR_OT5_OTEAL
 
- TSI148_LCSR_OT5_OTEAU
 
- TSI148_LCSR_OT5_OTOFL
 
- TSI148_LCSR_OT5_OTOFU
 
- TSI148_LCSR_OT5_OTSAL
 
- TSI148_LCSR_OT5_OTSAU
 
- TSI148_LCSR_OT6
 
- TSI148_LCSR_OT6_OTAT
 
- TSI148_LCSR_OT6_OTBS
 
- TSI148_LCSR_OT6_OTEAL
 
- TSI148_LCSR_OT6_OTEAU
 
- TSI148_LCSR_OT6_OTOFL
 
- TSI148_LCSR_OT6_OTOFU
 
- TSI148_LCSR_OT6_OTSAL
 
- TSI148_LCSR_OT6_OTSAU
 
- TSI148_LCSR_OT7
 
- TSI148_LCSR_OT7_OTAT
 
- TSI148_LCSR_OT7_OTBS
 
- TSI148_LCSR_OT7_OTEAL
 
- TSI148_LCSR_OT7_OTEAU
 
- TSI148_LCSR_OT7_OTOFL
 
- TSI148_LCSR_OT7_OTOFU
 
- TSI148_LCSR_OT7_OTSAL
 
- TSI148_LCSR_OT7_OTSAU
 
- TSI148_LCSR_OTAT_2eSSTM_160
 
- TSI148_LCSR_OTAT_2eSSTM_267
 
- TSI148_LCSR_OTAT_2eSSTM_320
 
- TSI148_LCSR_OTAT_2eSSTM_M
 
- TSI148_LCSR_OTAT_AMODE_A16
 
- TSI148_LCSR_OTAT_AMODE_A24
 
- TSI148_LCSR_OTAT_AMODE_A32
 
- TSI148_LCSR_OTAT_AMODE_A64
 
- TSI148_LCSR_OTAT_AMODE_CRCSR
 
- TSI148_LCSR_OTAT_AMODE_M
 
- TSI148_LCSR_OTAT_AMODE_USER1
 
- TSI148_LCSR_OTAT_AMODE_USER2
 
- TSI148_LCSR_OTAT_AMODE_USER3
 
- TSI148_LCSR_OTAT_AMODE_USER4
 
- TSI148_LCSR_OTAT_DBW_16
 
- TSI148_LCSR_OTAT_DBW_32
 
- TSI148_LCSR_OTAT_DBW_M
 
- TSI148_LCSR_OTAT_EN
 
- TSI148_LCSR_OTAT_MRPFD
 
- TSI148_LCSR_OTAT_PFS_16
 
- TSI148_LCSR_OTAT_PFS_2
 
- TSI148_LCSR_OTAT_PFS_4
 
- TSI148_LCSR_OTAT_PFS_8
 
- TSI148_LCSR_OTAT_PFS_M
 
- TSI148_LCSR_OTAT_PGM
 
- TSI148_LCSR_OTAT_SUP
 
- TSI148_LCSR_OTAT_TM_2eSST
 
- TSI148_LCSR_OTAT_TM_2eSSTB
 
- TSI148_LCSR_OTAT_TM_2eVME
 
- TSI148_LCSR_OTAT_TM_BLT
 
- TSI148_LCSR_OTAT_TM_M
 
- TSI148_LCSR_OTAT_TM_MBLT
 
- TSI148_LCSR_OTAT_TM_SCT
 
- TSI148_LCSR_OTBS_M
 
- TSI148_LCSR_OTEAL_M
 
- TSI148_LCSR_OTOFFL_M
 
- TSI148_LCSR_OTSAL_M
 
- TSI148_LCSR_PSTAT
 
- TSI148_LCSR_PSTAT_DEVSELS
 
- TSI148_LCSR_PSTAT_FRAMES
 
- TSI148_LCSR_PSTAT_IRDYS
 
- TSI148_LCSR_PSTAT_M66ENS
 
- TSI148_LCSR_PSTAT_REQ64S
 
- TSI148_LCSR_PSTAT_STOPS
 
- TSI148_LCSR_PSTAT_TRDYS
 
- TSI148_LCSR_RMWAL
 
- TSI148_LCSR_RMWAU
 
- TSI148_LCSR_RMWC
 
- TSI148_LCSR_RMWEN
 
- TSI148_LCSR_RMWS
 
- TSI148_LCSR_VCTRL
 
- TSI148_LCSR_VCTRL_ATOEN
 
- TSI148_LCSR_VCTRL_BID_M
 
- TSI148_LCSR_VCTRL_DLT_1024
 
- TSI148_LCSR_VCTRL_DLT_128
 
- TSI148_LCSR_VCTRL_DLT_16
 
- TSI148_LCSR_VCTRL_DLT_16384
 
- TSI148_LCSR_VCTRL_DLT_2048
 
- TSI148_LCSR_VCTRL_DLT_256
 
- TSI148_LCSR_VCTRL_DLT_32
 
- TSI148_LCSR_VCTRL_DLT_32768
 
- TSI148_LCSR_VCTRL_DLT_4096
 
- TSI148_LCSR_VCTRL_DLT_512
 
- TSI148_LCSR_VCTRL_DLT_64
 
- TSI148_LCSR_VCTRL_DLT_8192
 
- TSI148_LCSR_VCTRL_DLT_M
 
- TSI148_LCSR_VCTRL_DLT_OFF
 
- TSI148_LCSR_VCTRL_GTO_128
 
- TSI148_LCSR_VCTRL_GTO_16
 
- TSI148_LCSR_VCTRL_GTO_256
 
- TSI148_LCSR_VCTRL_GTO_32
 
- TSI148_LCSR_VCTRL_GTO_512
 
- TSI148_LCSR_VCTRL_GTO_64
 
- TSI148_LCSR_VCTRL_GTO_8
 
- TSI148_LCSR_VCTRL_GTO_DIS
 
- TSI148_LCSR_VCTRL_GTO_M
 
- TSI148_LCSR_VCTRL_LRE
 
- TSI148_LCSR_VCTRL_LRESET
 
- TSI148_LCSR_VCTRL_NERBB
 
- TSI148_LCSR_VCTRL_ROBIN
 
- TSI148_LCSR_VCTRL_SFAILAI
 
- TSI148_LCSR_VCTRL_SRESET
 
- TSI148_LCSR_VEAL
 
- TSI148_LCSR_VEAT
 
- TSI148_LCSR_VEAT_2EOT
 
- TSI148_LCSR_VEAT_2EST
 
- TSI148_LCSR_VEAT_AM_M
 
- TSI148_LCSR_VEAT_BERR
 
- TSI148_LCSR_VEAT_DS0
 
- TSI148_LCSR_VEAT_DS1
 
- TSI148_LCSR_VEAT_IACK
 
- TSI148_LCSR_VEAT_LWORD
 
- TSI148_LCSR_VEAT_VEOF
 
- TSI148_LCSR_VEAT_VES
 
- TSI148_LCSR_VEAT_VESCL
 
- TSI148_LCSR_VEAT_WRITE
 
- TSI148_LCSR_VEAT_XAM_M
 
- TSI148_LCSR_VEAU
 
- TSI148_LCSR_VIACK1
 
- TSI148_LCSR_VIACK2
 
- TSI148_LCSR_VIACK3
 
- TSI148_LCSR_VIACK4
 
- TSI148_LCSR_VIACK5
 
- TSI148_LCSR_VIACK6
 
- TSI148_LCSR_VIACK7
 
- TSI148_LCSR_VICR
 
- TSI148_LCSR_VICR_BIP
 
- TSI148_LCSR_VICR_CNTS_DIS
 
- TSI148_LCSR_VICR_CNTS_IRQ1
 
- TSI148_LCSR_VICR_CNTS_IRQ2
 
- TSI148_LCSR_VICR_CNTS_M
 
- TSI148_LCSR_VICR_EDGIS_DIS
 
- TSI148_LCSR_VICR_EDGIS_IRQ1
 
- TSI148_LCSR_VICR_EDGIS_IRQ2
 
- TSI148_LCSR_VICR_EDGIS_M
 
- TSI148_LCSR_VICR_IRQ2F_1U
 
- TSI148_LCSR_VICR_IRQ2F_M
 
- TSI148_LCSR_VICR_IRQ2F_NORM
 
- TSI148_LCSR_VICR_IRQ2F_PROG
 
- TSI148_LCSR_VICR_IRQ2F_PULSE
 
- TSI148_LCSR_VICR_IRQC
 
- TSI148_LCSR_VICR_IRQIF_1U
 
- TSI148_LCSR_VICR_IRQIF_M
 
- TSI148_LCSR_VICR_IRQIF_NORM
 
- TSI148_LCSR_VICR_IRQIF_PROG
 
- TSI148_LCSR_VICR_IRQIF_PULSE
 
- TSI148_LCSR_VICR_IRQL_1
 
- TSI148_LCSR_VICR_IRQL_2
 
- TSI148_LCSR_VICR_IRQL_3
 
- TSI148_LCSR_VICR_IRQL_4
 
- TSI148_LCSR_VICR_IRQL_5
 
- TSI148_LCSR_VICR_IRQL_6
 
- TSI148_LCSR_VICR_IRQL_7
 
- TSI148_LCSR_VICR_IRQL_M
 
- TSI148_LCSR_VICR_IRQS
 
- TSI148_LCSR_VICR_STID_M
 
- TSI148_LCSR_VMCTRL
 
- TSI148_LCSR_VMCTRL_ATO_128
 
- TSI148_LCSR_VMCTRL_ATO_128M
 
- TSI148_LCSR_VMCTRL_ATO_2M
 
- TSI148_LCSR_VMCTRL_ATO_32
 
- TSI148_LCSR_VMCTRL_ATO_32M
 
- TSI148_LCSR_VMCTRL_ATO_512
 
- TSI148_LCSR_VMCTRL_ATO_8M
 
- TSI148_LCSR_VMCTRL_ATO_DIS
 
- TSI148_LCSR_VMCTRL_ATO_M
 
- TSI148_LCSR_VMCTRL_DHB
 
- TSI148_LCSR_VMCTRL_DWB
 
- TSI148_LCSR_VMCTRL_RMWEN
 
- TSI148_LCSR_VMCTRL_VFAIR
 
- TSI148_LCSR_VMCTRL_VREL_M
 
- TSI148_LCSR_VMCTRL_VREL_T_B_D
 
- TSI148_LCSR_VMCTRL_VREL_T_D
 
- TSI148_LCSR_VMCTRL_VREL_T_D_R
 
- TSI148_LCSR_VMCTRL_VREL_T_R_D
 
- TSI148_LCSR_VMCTRL_VREQL_M
 
- TSI148_LCSR_VMCTRL_VS
 
- TSI148_LCSR_VMCTRL_VSA
 
- TSI148_LCSR_VMCTRL_VTOFF_0
 
- TSI148_LCSR_VMCTRL_VTOFF_1
 
- TSI148_LCSR_VMCTRL_VTOFF_16
 
- TSI148_LCSR_VMCTRL_VTOFF_2
 
- TSI148_LCSR_VMCTRL_VTOFF_32
 
- TSI148_LCSR_VMCTRL_VTOFF_4
 
- TSI148_LCSR_VMCTRL_VTOFF_64
 
- TSI148_LCSR_VMCTRL_VTOFF_8
 
- TSI148_LCSR_VMCTRL_VTOFF_M
 
- TSI148_LCSR_VMCTRL_VTON_128
 
- TSI148_LCSR_VMCTRL_VTON_16
 
- TSI148_LCSR_VMCTRL_VTON_256
 
- TSI148_LCSR_VMCTRL_VTON_32
 
- TSI148_LCSR_VMCTRL_VTON_4
 
- TSI148_LCSR_VMCTRL_VTON_512
 
- TSI148_LCSR_VMCTRL_VTON_64
 
- TSI148_LCSR_VMCTRL_VTON_8
 
- TSI148_LCSR_VMCTRL_VTON_M
 
- TSI148_LCSR_VMEFL
 
- TSI148_LCSR_VSTAT
 
- TSI148_LCSR_VSTAT_ACFAILS
 
- TSI148_LCSR_VSTAT_BDFAILS
 
- TSI148_LCSR_VSTAT_BRDFL
 
- TSI148_LCSR_VSTAT_CPURST
 
- TSI148_LCSR_VSTAT_GAP
 
- TSI148_LCSR_VSTAT_GA_M
 
- TSI148_LCSR_VSTAT_PURSTS
 
- TSI148_LCSR_VSTAT_SCONS
 
- TSI148_LCSR_VSTAT_SYSFAILS
 
- TSI148_MAX_DMA
 
- TSI148_MAX_MAILBOX
 
- TSI148_MAX_MASTER
 
- TSI148_MAX_SEMAPHORE
 
- TSI148_MAX_SLAVE
 
- TSI148_PCFS_CAPP
 
- TSI148_PCFS_CLASS
 
- TSI148_PCFS_CLAS_M
 
- TSI148_PCFS_CLSZ_M
 
- TSI148_PCFS_CMMD_IOSP
 
- TSI148_PCFS_CMMD_MEMSP
 
- TSI148_PCFS_CMMD_MSTR
 
- TSI148_PCFS_CMMD_PERR
 
- TSI148_PCFS_CMMD_SERR
 
- TSI148_PCFS_CSR
 
- TSI148_PCFS_HEAD_M
 
- TSI148_PCFS_ID
 
- TSI148_PCFS_MBARL
 
- TSI148_PCFS_MBARL_BASEL_M
 
- TSI148_PCFS_MBARL_IOMEM
 
- TSI148_PCFS_MBARL_MTYPE_M
 
- TSI148_PCFS_MBARL_PRE
 
- TSI148_PCFS_MBARU
 
- TSI148_PCFS_MISC0
 
- TSI148_PCFS_MISC1
 
- TSI148_PCFS_MLAT_M
 
- TSI148_PCFS_MSIAL_M
 
- TSI148_PCFS_MSICAP_64BAC
 
- TSI148_PCFS_MSICAP_MMC_M
 
- TSI148_PCFS_MSICAP_MME_M
 
- TSI148_PCFS_MSICAP_MSIEN
 
- TSI148_PCFS_MSIMD_M
 
- TSI148_PCFS_PCIXCAP_DPERE
 
- TSI148_PCFS_PCIXCAP_ERO
 
- TSI148_PCFS_PCIXCAP_MMRBC_M
 
- TSI148_PCFS_PCIXCAP_MOST_M
 
- TSI148_PCFS_PCIXSTAT_133C
 
- TSI148_PCFS_PCIXSTAT_64D
 
- TSI148_PCFS_PCIXSTAT_BN_M
 
- TSI148_PCFS_PCIXSTAT_DC
 
- TSI148_PCFS_PCIXSTAT_DMCRS_M
 
- TSI148_PCFS_PCIXSTAT_DMMRC_M
 
- TSI148_PCFS_PCIXSTAT_DMOST_M
 
- TSI148_PCFS_PCIXSTAT_DN_M
 
- TSI148_PCFS_PCIXSTAT_FN_M
 
- TSI148_PCFS_PCIXSTAT_RSCEM
 
- TSI148_PCFS_PCIXSTAT_SCD
 
- TSI148_PCFS_PCIXSTAT_USC
 
- TSI148_PCFS_PROGIF_M
 
- TSI148_PCFS_REVID_M
 
- TSI148_PCFS_STAT_CAPL
 
- TSI148_PCFS_STAT_DPAR
 
- TSI148_PCFS_STAT_FAST
 
- TSI148_PCFS_STAT_P66M
 
- TSI148_PCFS_STAT_RCPVE
 
- TSI148_PCFS_STAT_RCVMA
 
- TSI148_PCFS_STAT_RCVTA
 
- TSI148_PCFS_STAT_SELTIM
 
- TSI148_PCFS_STAT_SIGSE
 
- TSI148_PCFS_STAT_SIGTA
 
- TSI148_PCFS_SUBCLAS_M
 
- TSI148_PCFS_SUBID
 
- TSI148_PCFS_XCAPP
 
- TSI148_PCFS_XSTAT
 
- TSI2_CLK
 
- TSI2_DATA
 
- TSI2_SYNC
 
- TSI2_VALID
 
- TSI3_CLK
 
- TSI3_DATA
 
- TSI3_SYNC
 
- TSI3_VALID
 
- TSI568_SP_MODE
 
- TSI568_SP_MODE_PW_DIS
 
- TSI578_GLBL_ROUTE_BASE
 
- TSI578_SP_CS_TX
 
- TSI578_SP_CTL_INDEP
 
- TSI578_SP_INT_STATUS
 
- TSI578_SP_LUT_PEINF
 
- TSI578_SP_MODE
 
- TSI578_SP_MODE_GLBL
 
- TSI578_SP_MODE_LUT_512
 
- TSI578_SP_MODE_PW_DIS
 
- TSI721_BDMA_INTE
 
- TSI721_BDMA_MAX_BCOUNT
 
- TSI721_DB_WIN_SIZE
 
- TSI721_DEVCTL
 
- TSI721_DEVCTL_SRBOOT_CMPL
 
- TSI721_DEV_CHAN_INT
 
- TSI721_DEV_CHAN_INTE
 
- TSI721_DEV_INT
 
- TSI721_DEV_INTE
 
- TSI721_DEV_INTSET
 
- TSI721_DEV_INT_BDMA_CH
 
- TSI721_DEV_INT_BDMA_NCH
 
- TSI721_DEV_INT_SMSG_CH
 
- TSI721_DEV_INT_SMSG_NCH
 
- TSI721_DEV_INT_SR2PC_CH
 
- TSI721_DEV_INT_SRIO
 
- TSI721_DMACH_DMA
 
- TSI721_DMACH_MAINT
 
- TSI721_DMACH_MAINT_NBD
 
- TSI721_DMAC_BASE
 
- TSI721_DMAC_CTL
 
- TSI721_DMAC_CTL_INIT
 
- TSI721_DMAC_CTL_SUSP
 
- TSI721_DMAC_DPTRH
 
- TSI721_DMAC_DPTRL
 
- TSI721_DMAC_DPTRL_MASK
 
- TSI721_DMAC_DRDCNT
 
- TSI721_DMAC_DSBH
 
- TSI721_DMAC_DSBL
 
- TSI721_DMAC_DSBL_MASK
 
- TSI721_DMAC_DSRP
 
- TSI721_DMAC_DSRP_MASK
 
- TSI721_DMAC_DSSZ
 
- TSI721_DMAC_DSSZ_SIZE
 
- TSI721_DMAC_DSSZ_SIZE_M
 
- TSI721_DMAC_DSWP
 
- TSI721_DMAC_DSWP_MASK
 
- TSI721_DMAC_DWRCNT
 
- TSI721_DMAC_INT
 
- TSI721_DMAC_INTE
 
- TSI721_DMAC_INTSET
 
- TSI721_DMAC_INT_ALL
 
- TSI721_DMAC_INT_DONE
 
- TSI721_DMAC_INT_ERR
 
- TSI721_DMAC_INT_IOFDONE
 
- TSI721_DMAC_INT_STFULL
 
- TSI721_DMAC_INT_SUSP
 
- TSI721_DMAC_STS
 
- TSI721_DMAC_STS_ABORT
 
- TSI721_DMAC_STS_CS
 
- TSI721_DMAC_STS_RUN
 
- TSI721_DMAD_BCOUNT1
 
- TSI721_DMAD_BCOUNT2
 
- TSI721_DMAD_CFGOFF
 
- TSI721_DMAD_CRF
 
- TSI721_DMAD_DEVID
 
- TSI721_DMAD_DTYPE
 
- TSI721_DMAD_HOPCNT
 
- TSI721_DMAD_IOF
 
- TSI721_DMAD_PRIO
 
- TSI721_DMAD_RADDR0
 
- TSI721_DMAD_RTYPE
 
- TSI721_DMAD_TT
 
- TSI721_DMA_CHNUM
 
- TSI721_DMA_MAXCH
 
- TSI721_DMA_MINSTSSZ
 
- TSI721_DMA_STSBLKSZ
 
- TSI721_I2C_INT_ENABLE
 
- TSI721_IBDMAC_CTL
 
- TSI721_IBDMAC_CTL_INIT
 
- TSI721_IBDMAC_CTL_MASK
 
- TSI721_IBDMAC_CTL_SUSPEND
 
- TSI721_IBDMAC_DQBH
 
- TSI721_IBDMAC_DQBH_MASK
 
- TSI721_IBDMAC_DQBL
 
- TSI721_IBDMAC_DQBL_ADDR
 
- TSI721_IBDMAC_DQBL_MASK
 
- TSI721_IBDMAC_DQRP
 
- TSI721_IBDMAC_DQRP_MASK
 
- TSI721_IBDMAC_DQSZ
 
- TSI721_IBDMAC_DQSZ_MASK
 
- TSI721_IBDMAC_DQWR
 
- TSI721_IBDMAC_DQWR_MASK
 
- TSI721_IBDMAC_FQBH
 
- TSI721_IBDMAC_FQBH_MASK
 
- TSI721_IBDMAC_FQBL
 
- TSI721_IBDMAC_FQBL_MASK
 
- TSI721_IBDMAC_FQRP
 
- TSI721_IBDMAC_FQRP_MASK
 
- TSI721_IBDMAC_FQSZ
 
- TSI721_IBDMAC_FQSZ_ENTRY_INX
 
- TSI721_IBDMAC_FQSZ_MASK
 
- TSI721_IBDMAC_FQTH
 
- TSI721_IBDMAC_FQTH_MASK
 
- TSI721_IBDMAC_FQWP
 
- TSI721_IBDMAC_FQWP_MASK
 
- TSI721_IBDMAC_INT
 
- TSI721_IBDMAC_INTE
 
- TSI721_IBDMAC_INTSET
 
- TSI721_IBDMAC_INT_ALL
 
- TSI721_IBDMAC_INT_DQ_RCV
 
- TSI721_IBDMAC_INT_FQ_LOW
 
- TSI721_IBDMAC_INT_MASK
 
- TSI721_IBDMAC_INT_PC_ERROR
 
- TSI721_IBDMAC_INT_SRTO
 
- TSI721_IBDMAC_INT_SUSPENDED
 
- TSI721_IBDMAC_PWE
 
- TSI721_IBDMAC_PWE_ILL_DEC
 
- TSI721_IBDMAC_PWE_ILL_FMT
 
- TSI721_IBDMAC_PWE_IMP_SP
 
- TSI721_IBDMAC_PWE_MASK
 
- TSI721_IBDMAC_PWE_SRTO
 
- TSI721_IBDMAC_STS
 
- TSI721_IBDMAC_STS_MASK
 
- TSI721_IBSMAC_STS_ABORT
 
- TSI721_IBSMAC_STS_CS
 
- TSI721_IBSMAC_STS_RUN
 
- TSI721_IBWIN_LB
 
- TSI721_IBWIN_LB_BA
 
- TSI721_IBWIN_LB_WEN
 
- TSI721_IBWIN_NUM
 
- TSI721_IBWIN_SIZE
 
- TSI721_IBWIN_SZ
 
- TSI721_IBWIN_SZ_SIZE
 
- TSI721_IBWIN_TLA
 
- TSI721_IBWIN_TLA_ADD
 
- TSI721_IBWIN_TUA
 
- TSI721_IBWIN_UB
 
- TSI721_IB_DEVID
 
- TSI721_IB_DEVID_GLOBAL
 
- TSI721_IB_DEVID_MASK
 
- TSI721_IDB_ENTRY_SIZE
 
- TSI721_IDQ_BASEL
 
- TSI721_IDQ_BASEL_ADDR
 
- TSI721_IDQ_BASEU
 
- TSI721_IDQ_CTL
 
- TSI721_IDQ_INIT
 
- TSI721_IDQ_MASK
 
- TSI721_IDQ_MASK_MASK
 
- TSI721_IDQ_MASK_PATT
 
- TSI721_IDQ_RP
 
- TSI721_IDQ_RP_PTR
 
- TSI721_IDQ_RUN
 
- TSI721_IDQ_SIZE
 
- TSI721_IDQ_SIZE_MAX
 
- TSI721_IDQ_SIZE_MIN
 
- TSI721_IDQ_SIZE_VAL
 
- TSI721_IDQ_STS
 
- TSI721_IDQ_SUSPEND
 
- TSI721_IDQ_WP
 
- TSI721_IDQ_WP_PTR
 
- TSI721_IMD_BCOUNT
 
- TSI721_IMD_CRF
 
- TSI721_IMD_CS
 
- TSI721_IMD_DEVID
 
- TSI721_IMD_DTYPE
 
- TSI721_IMD_HO
 
- TSI721_IMD_LETER
 
- TSI721_IMD_MBOX
 
- TSI721_IMD_PRIO
 
- TSI721_IMD_SSIZE
 
- TSI721_IMD_TT
 
- TSI721_IMD_XMBOX
 
- TSI721_IMSGD_MIN_RING_SIZE
 
- TSI721_IMSGD_RING_SIZE
 
- TSI721_IMSGID_SET
 
- TSI721_IMSG_CHNUM
 
- TSI721_IMSG_MAXCH
 
- TSI721_INT_BDMA_CHAN
 
- TSI721_INT_BDMA_CHAN_M
 
- TSI721_INT_IMSG_CHAN
 
- TSI721_INT_IMSG_CHAN_M
 
- TSI721_INT_OMSG_CHAN
 
- TSI721_INT_OMSG_CHAN_M
 
- TSI721_INT_SR2PC_CHAN
 
- TSI721_INT_SR2PC_CHAN_M
 
- TSI721_LUT_DATA0
 
- TSI721_LUT_DATA0_ADD
 
- TSI721_LUT_DATA0_MNTRD
 
- TSI721_LUT_DATA0_MNTWR
 
- TSI721_LUT_DATA0_NREAD
 
- TSI721_LUT_DATA0_NWR
 
- TSI721_LUT_DATA0_NWR_R
 
- TSI721_LUT_DATA0_RDCRF
 
- TSI721_LUT_DATA0_RDTYPE
 
- TSI721_LUT_DATA0_WRCRF
 
- TSI721_LUT_DATA0_WRTYPE
 
- TSI721_LUT_DATA1
 
- TSI721_LUT_DATA2
 
- TSI721_LUT_DATA2_ADD65
 
- TSI721_LUT_DATA2_DSTID
 
- TSI721_LUT_DATA2_HC
 
- TSI721_LUT_DATA2_TT
 
- TSI721_MAINT_WIN
 
- TSI721_MSG_BUFFER_SIZE
 
- TSI721_MSG_MAX_SIZE
 
- TSI721_MSIXPBA_OFFSET
 
- TSI721_MSIXTBL_OFFSET
 
- TSI721_MSIX_BDMA_INT
 
- TSI721_MSIX_DMACH_DONE
 
- TSI721_MSIX_DMACH_INT
 
- TSI721_MSIX_I2C_INT
 
- TSI721_MSIX_IMSG_DQ_RCV
 
- TSI721_MSIX_IMSG_INT
 
- TSI721_MSIX_MSG_INT
 
- TSI721_MSIX_OMSG_DONE
 
- TSI721_MSIX_OMSG_INT
 
- TSI721_MSIX_PC2SR_INT
 
- TSI721_MSIX_SR2PC_CH_INT
 
- TSI721_MSIX_SR2PC_IDBQ_RCV
 
- TSI721_MSIX_SR2PC_INT
 
- TSI721_MSIX_SRIO_MAC_INT
 
- TSI721_OBDMAC_CTL
 
- TSI721_OBDMAC_CTL_INIT
 
- TSI721_OBDMAC_CTL_MASK
 
- TSI721_OBDMAC_CTL_RETRY_THR
 
- TSI721_OBDMAC_CTL_SUSPEND
 
- TSI721_OBDMAC_DPTRH
 
- TSI721_OBDMAC_DPTRH_MASK
 
- TSI721_OBDMAC_DPTRL
 
- TSI721_OBDMAC_DPTRL_MASK
 
- TSI721_OBDMAC_DRDCNT
 
- TSI721_OBDMAC_DSBH
 
- TSI721_OBDMAC_DSBH_MASK
 
- TSI721_OBDMAC_DSBL
 
- TSI721_OBDMAC_DSBL_MASK
 
- TSI721_OBDMAC_DSRP
 
- TSI721_OBDMAC_DSRP_MASK
 
- TSI721_OBDMAC_DSSZ
 
- TSI721_OBDMAC_DSSZ_MASK
 
- TSI721_OBDMAC_DSWP
 
- TSI721_OBDMAC_DSWP_MASK
 
- TSI721_OBDMAC_DWRCNT
 
- TSI721_OBDMAC_INT
 
- TSI721_OBDMAC_INTE
 
- TSI721_OBDMAC_INTSET
 
- TSI721_OBDMAC_INT_ALL
 
- TSI721_OBDMAC_INT_DONE
 
- TSI721_OBDMAC_INT_ERROR
 
- TSI721_OBDMAC_INT_IOF_DONE
 
- TSI721_OBDMAC_INT_MASK
 
- TSI721_OBDMAC_INT_ST_FULL
 
- TSI721_OBDMAC_INT_SUSPENDED
 
- TSI721_OBDMAC_PWE
 
- TSI721_OBDMAC_PWE_ERROR_EN
 
- TSI721_OBDMAC_PWE_MASK
 
- TSI721_OBDMAC_STS
 
- TSI721_OBDMAC_STS_ABORT
 
- TSI721_OBDMAC_STS_CS
 
- TSI721_OBDMAC_STS_MASK
 
- TSI721_OBDMAC_STS_RUN
 
- TSI721_OBWINLB
 
- TSI721_OBWINLB_BA
 
- TSI721_OBWINLB_WEN
 
- TSI721_OBWINSZ
 
- TSI721_OBWINSZ_SIZE
 
- TSI721_OBWINUB
 
- TSI721_OBWIN_NUM
 
- TSI721_OBWIN_SIZE
 
- TSI721_OMD_BCOUNT
 
- TSI721_OMD_CRF
 
- TSI721_OMD_DEVID
 
- TSI721_OMD_DTYPE
 
- TSI721_OMD_IOF
 
- TSI721_OMD_LETER
 
- TSI721_OMD_MBOX
 
- TSI721_OMD_PRIO
 
- TSI721_OMD_RSRVD
 
- TSI721_OMD_SSIZE
 
- TSI721_OMD_TT
 
- TSI721_OMD_XMBOX
 
- TSI721_OMSGD_MIN_RING_SIZE
 
- TSI721_OMSGD_RING_SIZE
 
- TSI721_OMSG_CHNUM
 
- TSI721_PC2SR_BARS
 
- TSI721_PC2SR_INTE
 
- TSI721_PC2SR_WINS
 
- TSI721_PC2SR_ZONES
 
- TSI721_PCIECFG_EPCTL
 
- TSI721_PCIECFG_MSIXPBA
 
- TSI721_PCIECFG_MSIXTBL
 
- TSI721_REG_SPACE_SIZE
 
- TSI721_RETRY_GEN_CNT
 
- TSI721_RETRY_GEN_CNT_MASK
 
- TSI721_RETRY_RX_CNT
 
- TSI721_RETRY_RX_CNT_MASK
 
- TSI721_RIO_EM_DEV_INT_EN
 
- TSI721_RIO_EM_DEV_INT_EN_INT
 
- TSI721_RIO_EM_INT_ENABLE
 
- TSI721_RIO_EM_INT_ENABLE_PW_RX
 
- TSI721_RIO_EM_INT_STAT
 
- TSI721_RIO_EM_INT_STAT_PW_RX
 
- TSI721_RIO_PW_CTL
 
- TSI721_RIO_PW_CTL_PWC_CONT
 
- TSI721_RIO_PW_CTL_PWC_MODE
 
- TSI721_RIO_PW_CTL_PWC_REL
 
- TSI721_RIO_PW_CTL_PWT_103
 
- TSI721_RIO_PW_CTL_PWT_205
 
- TSI721_RIO_PW_CTL_PWT_410
 
- TSI721_RIO_PW_CTL_PWT_820
 
- TSI721_RIO_PW_CTL_PWT_DIS
 
- TSI721_RIO_PW_CTL_PW_TIMER
 
- TSI721_RIO_PW_MSG_SIZE
 
- TSI721_RIO_PW_RX_CAPT
 
- TSI721_RIO_PW_RX_STAT
 
- TSI721_RIO_PW_RX_STAT_PW_DISC
 
- TSI721_RIO_PW_RX_STAT_PW_SHORT
 
- TSI721_RIO_PW_RX_STAT_PW_TRUNC
 
- TSI721_RIO_PW_RX_STAT_PW_VAL
 
- TSI721_RIO_PW_RX_STAT_WR_SIZE
 
- TSI721_RQRPTO
 
- TSI721_RQRPTO_MASK
 
- TSI721_RQRPTO_VAL
 
- TSI721_SMSG_ECC_COR_LOG
 
- TSI721_SMSG_ECC_COR_LOG_MASK
 
- TSI721_SMSG_ECC_LOG
 
- TSI721_SMSG_ECC_LOG_ECC_COR_M
 
- TSI721_SMSG_ECC_LOG_ECC_NCOR_M
 
- TSI721_SMSG_ECC_LOG_MASK
 
- TSI721_SMSG_ECC_NCOR
 
- TSI721_SMSG_ECC_NCOR_MASK
 
- TSI721_SMSG_INT
 
- TSI721_SMSG_INTE
 
- TSI721_SMSG_INTSET
 
- TSI721_SMSG_INT_ECC_COR
 
- TSI721_SMSG_INT_ECC_COR_CH
 
- TSI721_SMSG_INT_ECC_NCOR
 
- TSI721_SMSG_INT_ECC_NCOR_CH
 
- TSI721_SMSG_INT_MASK
 
- TSI721_SMSG_INT_UNS_RSP
 
- TSI721_SMSG_PWE
 
- TSI721_SR2PC_GEN_INT
 
- TSI721_SR2PC_GEN_INTE
 
- TSI721_SR2PC_PWE
 
- TSI721_SRIO_MAXCH
 
- TSI721_SR_CHINT
 
- TSI721_SR_CHINTE
 
- TSI721_SR_CHINTSET
 
- TSI721_SR_CHINT_ALL
 
- TSI721_SR_CHINT_IDBQRCV
 
- TSI721_SR_CHINT_ODBERR
 
- TSI721_SR_CHINT_ODBOK
 
- TSI721_SR_CHINT_ODBRTRY
 
- TSI721_SR_CHINT_ODBTO
 
- TSI721_SR_CHINT_SUSP
 
- TSI721_USING_MSI
 
- TSI721_USING_MSIX
 
- TSI721_VECT_DMA0_DONE
 
- TSI721_VECT_DMA0_INT
 
- TSI721_VECT_DMA1_DONE
 
- TSI721_VECT_DMA1_INT
 
- TSI721_VECT_DMA2_DONE
 
- TSI721_VECT_DMA2_INT
 
- TSI721_VECT_DMA3_DONE
 
- TSI721_VECT_DMA3_INT
 
- TSI721_VECT_DMA4_DONE
 
- TSI721_VECT_DMA4_INT
 
- TSI721_VECT_DMA5_DONE
 
- TSI721_VECT_DMA5_INT
 
- TSI721_VECT_DMA6_DONE
 
- TSI721_VECT_DMA6_INT
 
- TSI721_VECT_DMA7_DONE
 
- TSI721_VECT_DMA7_INT
 
- TSI721_VECT_IDB
 
- TSI721_VECT_IMB0_INT
 
- TSI721_VECT_IMB0_RCV
 
- TSI721_VECT_IMB1_INT
 
- TSI721_VECT_IMB1_RCV
 
- TSI721_VECT_IMB2_INT
 
- TSI721_VECT_IMB2_RCV
 
- TSI721_VECT_IMB3_INT
 
- TSI721_VECT_IMB3_RCV
 
- TSI721_VECT_MAX
 
- TSI721_VECT_OMB0_DONE
 
- TSI721_VECT_OMB0_INT
 
- TSI721_VECT_OMB1_DONE
 
- TSI721_VECT_OMB1_INT
 
- TSI721_VECT_OMB2_DONE
 
- TSI721_VECT_OMB2_INT
 
- TSI721_VECT_OMB3_DONE
 
- TSI721_VECT_OMB3_INT
 
- TSI721_VECT_PWRX
 
- TSI721_ZONE_SEL
 
- TSI721_ZONE_SEL_GO
 
- TSI721_ZONE_SEL_RD_WRB
 
- TSI721_ZONE_SEL_WIN
 
- TSI721_ZONE_SEL_ZONE
 
- TSID
 
- TSIF
 
- TSIF0_TS_XX1_MARK
 
- TSIF0_TS_XX2_MARK
 
- TSIF0_TS_XX3_MARK
 
- TSIF0_TS_XX4_MARK
 
- TSIF0_TS_XX5_MARK
 
- TSIF1_TS_XX1_MARK
 
- TSIF1_TS_XX2_MARK
 
- TSIF1_TS_XX3_MARK
 
- TSIF1_TS_XX4_MARK
 
- TSIF1_TS_XX5_MARK
 
- TSIF2_TS_XX1_MARK
 
- TSIF2_TS_XX2_MARK
 
- TSIF2_TS_XX3_MARK
 
- TSIF2_TS_XX4_MARK
 
- TSIF2_TS_XX5_MARK
 
- TSIF_H_CLK
 
- TSIF_H_RESET
 
- TSIF_INACTIVITY_TIMERS_CLK
 
- TSIF_INPUT_PARALLEL
 
- TSIF_INPUT_SERIAL
 
- TSIF_NORMAL
 
- TSIF_REF_CLK
 
- TSIF_REF_CLK_SRC
 
- TSIF_REF_SRC
 
- TSIF_RESET
 
- TSIF_TS0_SCK_MARK
 
- TSIF_TS0_SDAT_MARK
 
- TSIF_TS0_SDEN_MARK
 
- TSIF_TS0_SPSYNC_MARK
 
- TSIF_TSIFI
 
- TSINSDELH
 
- TSINTR_AUTT0
 
- TSINTR_AUTT1
 
- TSINTR_RXTS
 
- TSINTR_SYS_WRAP
 
- TSINTR_TADJ
 
- TSINTR_TT0
 
- TSINTR_TT1
 
- TSINTR_TXTS
 
- TSIN_BUF_SIZE
 
- TSIP
 
- TSIZ_DOPNG
 
- TSIZ_NTD_MASK
 
- TSIZ_NTD_SHIFT
 
- TSIZ_PKTCNT_MASK
 
- TSIZ_PKTCNT_SHIFT
 
- TSIZ_SCHINFO_MASK
 
- TSIZ_SCHINFO_SHIFT
 
- TSIZ_SC_MC_PID_DATA0
 
- TSIZ_SC_MC_PID_DATA1
 
- TSIZ_SC_MC_PID_DATA2
 
- TSIZ_SC_MC_PID_MASK
 
- TSIZ_SC_MC_PID_MDATA
 
- TSIZ_SC_MC_PID_SETUP
 
- TSIZ_SC_MC_PID_SHIFT
 
- TSIZ_XFERSIZE_MASK
 
- TSIZ_XFERSIZE_SHIFT
 
- TSI_CTRL_REG
 
- TSI_PEN_DOWN_STATUS
 
- TSI_READ
 
- TSI_READ_PHY
 
- TSI_RIO_PW_RX_STAT_WDPTR
 
- TSI_WRITE
 
- TSI_WRITE_PHY
 
- TSInitialize
 
- TSKG
 
- TSK_ACA
 
- TSK_HEAD_OF_QUEUE
 
- TSK_IOWAIT
 
- TSK_K_BLINK
 
- TSK_K_ESP
 
- TSK_K_FP
 
- TSK_K_REG
 
- TSK_MEMSTALL
 
- TSK_MGMT_IOCB_TYPE
 
- TSK_MGMT_IOCB_TYPE_FX00
 
- TSK_ORDERED
 
- TSK_RUNNING
 
- TSK_SIMPLE
 
- TSK_TRACE_FL_GRAPH
 
- TSK_TRACE_FL_GRAPH_BIT
 
- TSK_TRACE_FL_TRACE
 
- TSK_TRACE_FL_TRACE_BIT
 
- TSK_UNTAGGED
 
- TSL1
 
- TSL2
 
- TSL2550_DRV_NAME
 
- TSL2550_EXTENDED_RANGE
 
- TSL2550_MAX_LUX
 
- TSL2550_PM_OPS
 
- TSL2550_POWER_DOWN
 
- TSL2550_POWER_UP
 
- TSL2550_READ_ADC0
 
- TSL2550_READ_ADC1
 
- TSL2550_STANDARD_RANGE
 
- TSL2563_CLEARINT
 
- TSL2563_CMD
 
- TSL2563_CMD_POWER_OFF
 
- TSL2563_CMD_POWER_ON
 
- TSL2563_CTRL_POWER_MASK
 
- TSL2563_INT_DISBLED
 
- TSL2563_INT_LEVEL
 
- TSL2563_INT_PERSIST
 
- TSL2563_PM_OPS
 
- TSL2563_REG_CTRL
 
- TSL2563_REG_DATA0HIGH
 
- TSL2563_REG_DATA0LOW
 
- TSL2563_REG_DATA1HIGH
 
- TSL2563_REG_DATA1LOW
 
- TSL2563_REG_HIGHHIGH
 
- TSL2563_REG_HIGHLOW
 
- TSL2563_REG_ID
 
- TSL2563_REG_INT
 
- TSL2563_REG_LOWHIGH
 
- TSL2563_REG_LOWLOW
 
- TSL2563_REG_TIMING
 
- TSL2563_TIMING_100MS
 
- TSL2563_TIMING_13MS
 
- TSL2563_TIMING_400MS
 
- TSL2563_TIMING_GAIN1
 
- TSL2563_TIMING_GAIN16
 
- TSL2563_TIMING_MASK
 
- TSL2583_ALS_CHAN0HI
 
- TSL2583_ALS_CHAN0LO
 
- TSL2583_ALS_CHAN1HI
 
- TSL2583_ALS_CHAN1LO
 
- TSL2583_ALS_TIME
 
- TSL2583_CHIPID
 
- TSL2583_CHIP_ID
 
- TSL2583_CHIP_ID_MASK
 
- TSL2583_CMD_ALS_INT_CLR
 
- TSL2583_CMD_REG
 
- TSL2583_CMD_SPL_FN
 
- TSL2583_CNTL_ADC_ENBL
 
- TSL2583_CNTL_PWR_OFF
 
- TSL2583_CNTL_PWR_ON
 
- TSL2583_CNTRL
 
- TSL2583_GAIN
 
- TSL2583_INTERRUPT
 
- TSL2583_INTERRUPT_DISABLED
 
- TSL2583_LUX_CALC_OVER_FLOW
 
- TSL2583_MAX_LUX_TABLE_ENTRIES
 
- TSL2583_POWER_OFF_DELAY_MS
 
- TSL2583_REVID
 
- TSL2583_STA_ADC_INTR
 
- TSL2583_STA_ADC_VALID
 
- TSL2583_TMR_HI
 
- TSL2583_TMR_LO
 
- TSL2772_100_mA
 
- TSL2772_13_mA
 
- TSL2772_25_mA
 
- TSL2772_50_mA
 
- TSL2772_ALS_CHAN0HI
 
- TSL2772_ALS_CHAN0LO
 
- TSL2772_ALS_CHAN1HI
 
- TSL2772_ALS_CHAN1LO
 
- TSL2772_ALS_GAIN_TRIM_MAX
 
- TSL2772_ALS_GAIN_TRIM_MIN
 
- TSL2772_ALS_MAXTHRESHHI
 
- TSL2772_ALS_MAXTHRESHLO
 
- TSL2772_ALS_MINTHRESHHI
 
- TSL2772_ALS_MINTHRESHLO
 
- TSL2772_ALS_PRX_CONFIG
 
- TSL2772_ALS_TIME
 
- TSL2772_BOOT_MAX_SLEEP_TIME
 
- TSL2772_BOOT_MIN_SLEEP_TIME
 
- TSL2772_CHIPID
 
- TSL2772_CHIP_SUSPENDED
 
- TSL2772_CHIP_UNKNOWN
 
- TSL2772_CHIP_WORKING
 
- TSL2772_CMD_ALS_INT_CLR
 
- TSL2772_CMD_AUTOINC_PROTO
 
- TSL2772_CMD_PROXALS_INT_CLR
 
- TSL2772_CMD_PROX_INT_CLR
 
- TSL2772_CMD_REG
 
- TSL2772_CMD_REPEAT_PROTO
 
- TSL2772_CMD_SPL_FN
 
- TSL2772_CNTL_ADC_ENBL
 
- TSL2772_CNTL_ALSPON_ENBL
 
- TSL2772_CNTL_ALS_INT_ENBL
 
- TSL2772_CNTL_INTALSPON_ENBL
 
- TSL2772_CNTL_INTPROXPON_ENBL
 
- TSL2772_CNTL_PROXPON_ENBL
 
- TSL2772_CNTL_PROX_DET_ENBL
 
- TSL2772_CNTL_PROX_INT_ENBL
 
- TSL2772_CNTL_PWRON
 
- TSL2772_CNTL_PWR_ON
 
- TSL2772_CNTL_REG_CLEAR
 
- TSL2772_CNTL_WAIT_TMR_ENBL
 
- TSL2772_CNTRL
 
- TSL2772_DEFAULT_TABLE_BYTES
 
- TSL2772_DEF_LUX_TABLE_SZ
 
- TSL2772_DEVICE_INFO
 
- TSL2772_DIODE0
 
- TSL2772_DIODE1
 
- TSL2772_DIODE_BOTH
 
- TSL2772_GAIN
 
- TSL2772_LUX_CALC_OVER_FLOW
 
- TSL2772_MAX_CONFIG_REG
 
- TSL2772_MAX_LUX_TABLE_SIZE
 
- TSL2772_MAX_PROX_LEDS
 
- TSL2772_NOTUSED
 
- TSL2772_NUM_SUPPLIES
 
- TSL2772_PERSISTENCE
 
- TSL2772_PRX_COUNT
 
- TSL2772_PRX_HI
 
- TSL2772_PRX_LO
 
- TSL2772_PRX_MAXTHRESHHI
 
- TSL2772_PRX_MAXTHRESHLO
 
- TSL2772_PRX_MINTHRESHHI
 
- TSL2772_PRX_MINTHRESHLO
 
- TSL2772_PRX_TIME
 
- TSL2772_REVID
 
- TSL2772_STATUS
 
- TSL2772_STA_ADC_PRX_VALID
 
- TSL2772_STA_ADC_VALID
 
- TSL2772_STA_ALS_INTR
 
- TSL2772_STA_PRX_INTR
 
- TSL2772_STA_PRX_VALID
 
- TSL2772_SUPPLY_VDD
 
- TSL2772_SUPPLY_VDDIO
 
- TSL2772_WAIT_TIME
 
- TSL45311_ID
 
- TSL45313_ID
 
- TSL45315_ID
 
- TSL45317_ID
 
- TSL4531_COMMAND
 
- TSL4531_CONFIG
 
- TSL4531_CONTROL
 
- TSL4531_DATA
 
- TSL4531_DRV_NAME
 
- TSL4531_ID
 
- TSL4531_ID_SHIFT
 
- TSL4531_MODE_NORMAL
 
- TSL4531_MODE_POWERDOWN
 
- TSL4531_MODE_SINGLE_ADC
 
- TSL4531_PM_OPS
 
- TSL4531_TCNTRL_100MS
 
- TSL4531_TCNTRL_200MS
 
- TSL4531_TCNTRL_400MS
 
- TSLB_BYTEORD
 
- TSLB_YLAST
 
- TSLB_YUYV_MASK
 
- TSL_BSEL_A1
 
- TSL_BSEL_A2
 
- TSL_DIS_A1
 
- TSL_DIS_A2
 
- TSL_DOD_A1
 
- TSL_DOD_A2
 
- TSL_EOS
 
- TSL_LF_A1
 
- TSL_LF_A2
 
- TSL_LOW_A1
 
- TSL_LOW_A2
 
- TSL_SDW_A1
 
- TSL_SDW_A2
 
- TSL_SF_A1
 
- TSL_SF_A2
 
- TSL_SIB_A1
 
- TSL_SIB_A2
 
- TSL_WS0
 
- TSL_WS1
 
- TSL_WS2
 
- TSL_WS3
 
- TSL_WS4
 
- TSMASK
 
- TSO
 
- TSOEE
 
- TSOP_G
 
- TSOP_M
 
- TSOP_S
 
- TSOP_V
 
- TSOUT_BUF_SIZE
 
- TSO_FLAGS
 
- TSO_HEADER_SIZE
 
- TSO_IPPROTO_TCP
 
- TSO_MAX_BUFF_SIZE
 
- TSO_MSS0_LEN
 
- TSO_MSS0_POS
 
- TSO_MSS1_LEN
 
- TSO_MSS1_POS
 
- TSO_NUM_DESCRIPTORS
 
- TSO_OFFLOAD_ON
 
- TSP2_NOR_BOOT_BASE
 
- TSP2_NOR_BOOT_SIZE
 
- TSP2_PCI_SLOT0_IRQ_PIN
 
- TSP2_PCI_SLOT0_OFFS
 
- TSP2_RTC_GPIO
 
- TSPEC_TV_SEC
 
- TSPIEN_AUX2_LOHI
 
- TSPIEN_AUX_LOHI
 
- TSPIEN_CRIT_LOHI
 
- TSPIEN_HOT_LOHI
 
- TSQB
 
- TSQF_QUEUED
 
- TSQF_THROTTLED
 
- TSQH
 
- TSQSIZE
 
- TSQT
 
- TSQ_ALIGNMENT
 
- TSQ_LINK_TABLE
 
- TSQ_NUM_ENTRIES
 
- TSQ_QUEUED
 
- TSQ_THROTTLED
 
- TSR
 
- TSR0_AAL0
 
- TSR0_AAL0_SDU
 
- TSR0_AAL5
 
- TSR0_ABR
 
- TSR0_ABT
 
- TSR0_CBR
 
- TSR0_CDH
 
- TSR0_COLS
 
- TSR0_CONN_STATE
 
- TSR0_CRS
 
- TSR0_FDX
 
- TSR0_GMII
 
- TSR0_GROUP
 
- TSR0_HALT_ER
 
- TSR0_LNKFL
 
- TSR0_MARK_CI
 
- TSR0_MARK_ER
 
- TSR0_NCR
 
- TSR0_NCR0
 
- TSR0_NCR1
 
- TSR0_NCR2
 
- TSR0_NCR3
 
- TSR0_OWC
 
- TSR0_OWT
 
- TSR0_PROT
 
- TSR0_PWRSTS1_2
 
- TSR0_PWRSTS7
 
- TSR0_RC_INDEX
 
- TSR0_SHDN
 
- TSR0_TERR
 
- TSR0_UBR
 
- TSR0_UPDATE_GER
 
- TSR0_USE_WMIN
 
- TSR11_ADTF
 
- TSR11_ICR
 
- TSR11_NRM
 
- TSR11_TRM
 
- TSR13_CDF
 
- TSR13_CRM
 
- TSR13_RDF
 
- TSR13_RIF
 
- TSR14_ABR_CLOSE
 
- TSR14_DELETE
 
- TSR1_COL
 
- TSR1_EC
 
- TSR1_LC
 
- TSR1_LOC
 
- TSR1_MCR
 
- TSR1_NC
 
- TSR1_PCR
 
- TSR1_PWRSTS3
 
- TSR1_PWRSTS4_6
 
- TSR1_RETRYTMO
 
- TSR1_TERR
 
- TSR1_TLF
 
- TSR1_TMO
 
- TSR2_ACR
 
- TSR2_COL
 
- TSR2_EC
 
- TSR2_LC
 
- TSR2_LOC
 
- TSR2_NC
 
- TSR2_TLF
 
- TSR3_CRM_CNT
 
- TSR3_NRM_CNT
 
- TSR4_AAL0
 
- TSR4_AAL0_SDU
 
- TSR4_AAL5
 
- TSR4_CRC10
 
- TSR4_FLUSH_CONN
 
- TSR4_NULL_CRC10
 
- TSR4_PROT
 
- TSR4_SESSION_ENDED
 
- TSR9_OPEN_CONN
 
- TSRB_BA
 
- TSRC_BA
 
- TSRD_BA
 
- TSRF
 
- TSR_ACKDATA
 
- TSR_BIT
 
- TSR_CCS0
 
- TSR_CCS1
 
- TSR_CMDAMT
 
- TSR_CMDDMT
 
- TSR_COL
 
- TSR_DE
 
- TSR_DI
 
- TSR_DIS
 
- TSR_EC
 
- TSR_ECOL
 
- TSR_ENW
 
- TSR_ERRORS
 
- TSR_FIS
 
- TSR_JBR
 
- TSR_LC
 
- TSR_LCOL
 
- TSR_LOSS_CRS
 
- TSR_NC
 
- TSR_PIS
 
- TSR_RETRYTMO
 
- TSR_TCFD
 
- TSR_TCFU
 
- TSR_TCFV
 
- TSR_TFFL
 
- TSR_TGFA
 
- TSR_TGFB
 
- TSR_TGFC
 
- TSR_TGFD
 
- TSR_TI
 
- TSR_TJTO
 
- TSR_TMO
 
- TSR_TO
 
- TSR_VALID
 
- TSR_WIS
 
- TSR_WRS
 
- TSS2_RC_LAYER_SHIFT
 
- TSS2_RESMGR_TPM_RC_LAYER
 
- TSSC_CLK
 
- TSSC_CLK_SRC
 
- TSSC_RESET
 
- TSSET1
 
- TSSET1_M
 
- TSSET1_TSASEL_ISDBS
 
- TSSET1_TSASEL_ISDBT
 
- TSSET1_TSASEL_MASK
 
- TSSET1_TSASEL_NONE
 
- TSSET1_TSBSEL_ISDBS
 
- TSSET1_TSBSEL_ISDBT
 
- TSSET1_TSBSEL_MASK
 
- TSSET1_TSBSEL_NONE
 
- TSSET2
 
- TSSET2_M
 
- TSSET3
 
- TSSET3_INTASEL_MASK
 
- TSSET3_INTASEL_NONE
 
- TSSET3_INTASEL_S
 
- TSSET3_INTASEL_T
 
- TSSET3_INTBSEL_MASK
 
- TSSET3_INTBSEL_NONE
 
- TSSET3_INTBSEL_S
 
- TSSET3_INTBSEL_T
 
- TSSET3_M
 
- TSSET_S
 
- TSSI_MUX_EXT
 
- TSSI_MUX_POSTPA
 
- TSSI_MUX_PREPA
 
- TSSPEED
 
- TSSTATEM
 
- TSSTATUS
 
- TSSTATUS2
 
- TSS_ARB_CMP
 
- TSS_BASE_SIZE
 
- TSS_BUSY_RLS
 
- TSS_BUS_SERV
 
- TSS_BYPASS_BIT
 
- TSS_CHECKUM_ENABLE
 
- TSS_CMD_ABTED
 
- TSS_CMD_PH_CMP
 
- TSS_DATA_PH_CMP
 
- TSS_DISC_INT
 
- TSS_FIFO_EMPTY
 
- TSS_FIFO_FULL
 
- TSS_FUNC_COMP
 
- TSS_INT_PENDING
 
- TSS_IOPB_BASE_OFFSET
 
- TSS_IOPB_SIZE
 
- TSS_IPV6_ENABLE_BIT
 
- TSS_IP_CHKSUM_BIT
 
- TSS_IP_FIXED_LEN_BIT
 
- TSS_MAP_RESERVED
 
- TSS_MSG_SEND
 
- TSS_MTU_ENABLE_BIT
 
- TSS_OFFSET_0
 
- TSS_PAR_ERROR
 
- TSS_PH_MASK
 
- TSS_PH_MISMATCH
 
- TSS_PRIVATE_MEMSLOT
 
- TSS_REDIRECTION_SIZE
 
- TSS_RESEL_INT
 
- TSS_SCAM_SEL
 
- TSS_SCSIRST
 
- TSS_SCSIRST_INT
 
- TSS_SCSI_BUS_EN
 
- TSS_SEL_CMP
 
- TSS_SEL_INT
 
- TSS_SEL_TIMEOUT
 
- TSS_SEQ_ACTIVE
 
- TSS_STATUS_RCV
 
- TSS_STATUS_SEND
 
- TSS_TCP_CHKSUM_BIT
 
- TSS_TIMEOUT_0
 
- TSS_UDP_CHKSUM_BIT
 
- TSS_XFER_CMP
 
- TSS_XFER_CNT
 
- TSS_authhmac
 
- TSS_checkhmac1
 
- TSS_checkhmac2
 
- TSS_rawhmac
 
- TSS_sha1
 
- TST100BTCFG_BADLNK_BYPASS
 
- TST100BTCFG_DEF
 
- TST100BTCFG_LITCH_EN
 
- TST100BTCFG_LONGCABL_TH_MASK
 
- TST100BTCFG_LONGCABL_TH_SHIFT
 
- TST100BTCFG_NORMAL_BW_EN
 
- TST100BTCFG_SHORTCABL_TH_MASK
 
- TST100BTCFG_SHORTCABL_TH_SHIFT
 
- TST100BTCFG_VLT_SW
 
- TST10BTCFG_DEF
 
- TST10BTCFG_DIV_MAN_MLT3_EN
 
- TST10BTCFG_INTV_TIMER_MASK
 
- TST10BTCFG_INTV_TIMER_SHIFT
 
- TST10BTCFG_LPBK_DEEP
 
- TST10BTCFG_OFF_DAC_IDLE
 
- TST10BTCFG_TRIGER_TIMER_MASK
 
- TST10BTCFG_TRIGER_TIMER_SHIFT
 
- TSTAMP
 
- TSTAMPS_EN_F
 
- TSTAMPS_EN_S
 
- TSTAMPS_EN_V
 
- TSTAMP_ALL_FRAMES
 
- TSTAMP_ALL_PTP_FRAMES
 
- TSTAMP_DISABLED
 
- TSTAMP_FRAME_PTP_EVENT_ONLY
 
- TSTAMP_OK
 
- TSTAT
 
- TSTAT0_BUFFER_INDEX
 
- TSTAT0_ECOLL
 
- TSTAT0_FA
 
- TSTAT0_LCRS
 
- TSTAT0_NCOLL
 
- TSTAT0_OW
 
- TSTAT0_TXFP
 
- TSTAT0_TXU
 
- TSTAT0_TXWE
 
- TSTAT1
 
- TSTAT1_ADDR
 
- TSTAT2
 
- TSTAT2_ADDR
 
- TSTATE_AG
 
- TSTATE_AM
 
- TSTATE_ASI
 
- TSTATE_CCR
 
- TSTATE_CLE
 
- TSTATE_CWP
 
- TSTATE_GL
 
- TSTATE_ICARRY
 
- TSTATE_ICC
 
- TSTATE_IE
 
- TSTATE_IG
 
- TSTATE_INEG
 
- TSTATE_INITIAL_MM
 
- TSTATE_IOVFL
 
- TSTATE_IZERO
 
- TSTATE_MCDE
 
- TSTATE_MG
 
- TSTATE_MM
 
- TSTATE_PEF
 
- TSTATE_PIL
 
- TSTATE_PRIV
 
- TSTATE_PSO
 
- TSTATE_PSTATE
 
- TSTATE_RED
 
- TSTATE_RMO
 
- TSTATE_SYSCALL
 
- TSTATE_TLE
 
- TSTATE_TSO
 
- TSTATE_XCARRY
 
- TSTATE_XCC
 
- TSTATE_XNEG
 
- TSTATE_XOVFL
 
- TSTATE_XZERO
 
- TSTAT_ADCSYS1_MASK
 
- TSTAT_ADCSYS1_OFFSET
 
- TSTAT_ADCSYS2_MASK
 
- TSTAT_ADCSYS2_OFFSET
 
- TSTAT_ADDR
 
- TSTAT_CAPT
 
- TSTAT_CLEAR_THALT
 
- TSTAT_CLEAR_THALT0
 
- TSTAT_CLEAR_THALT1
 
- TSTAT_CLEAR_THALT2
 
- TSTAT_CLEAR_THALT3
 
- TSTAT_CLEAR_THALT4
 
- TSTAT_CLEAR_THALT5
 
- TSTAT_CLEAR_THALT6
 
- TSTAT_CLEAR_THALT7
 
- TSTAT_CLEAR_THALT_ALL
 
- TSTAT_COMP
 
- TSTAT_CSI2MEM_MASK
 
- TSTAT_CSI2MEM_OFFSET
 
- TSTAT_ENC_MASK
 
- TSTAT_ENC_OFFSET
 
- TSTAT_ENC_ROT_MASK
 
- TSTAT_ENC_ROT_OFFSET
 
- TSTAT_INIT_EDLC
 
- TSTAT_INIT_SEEQ
 
- TSTAT_PF_H264_PAUSE
 
- TSTAT_PF_MASK
 
- TSTAT_PF_OFFSET
 
- TSTAT_PP_MASK
 
- TSTAT_PP_OFFSET
 
- TSTAT_PP_ROT_MASK
 
- TSTAT_PP_ROT_OFFSET
 
- TSTAT_VF_MASK
 
- TSTAT_VF_OFFSET
 
- TSTAT_VF_ROT_MASK
 
- TSTAT_VF_ROT_OFFSET
 
- TSTB
 
- TSTBUS_COMBINED
 
- TSTBUS_DFC
 
- TSTBUS_MAX
 
- TSTBUS_OCSC
 
- TSTBUS_RXUC
 
- TSTBUS_TMRLUT
 
- TSTBUS_TRLUT
 
- TSTBUS_TXUC
 
- TSTBUS_UARM
 
- TSTBUS_UAWM
 
- TSTBUS_UNIPRO
 
- TSTBUS_UTP_HCI
 
- TSTBUS_WRAPPER
 
- TSTCNTL
 
- TSTCNTL_RD
 
- TSTCNTL_READ
 
- TSTCNTL_READ_ADDRESS
 
- TSTCNTL_REG_BANK_SEL
 
- TSTCNTL_TEST_MODE
 
- TSTCNTL_WR
 
- TSTCNTL_WRITE
 
- TSTCNTL_WRITE_ADDRESS
 
- TSTCTL
 
- TSTDAT
 
- TSTDAT_FIXED
 
- TSTDAT_VAL
 
- TSTDISRX
 
- TSTD_60
 
- TSTD_B
 
- TSTD_B1
 
- TSTD_D
 
- TSTD_D1
 
- TSTD_G
 
- TSTD_H
 
- TSTD_I
 
- TSTD_K
 
- TSTD_K1
 
- TSTD_L
 
- TSTD_M
 
- TSTD_N
 
- TSTD_Nc
 
- TSTE_MASK
 
- TSTE_OPC_CBR
 
- TSTE_OPC_JMP
 
- TSTE_OPC_MASK
 
- TSTE_OPC_NULL
 
- TSTE_OPC_VAR
 
- TSTE_PUSH_ACTIVE
 
- TSTE_PUSH_IDLE
 
- TSTMODE_DISABLE
 
- TSTMODE_ENABLE
 
- TSTMSK
 
- TSTORM
 
- TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET
 
- TSTORM_ASSERT_LIST_INDEX_OFFSET
 
- TSTORM_ASSERT_LIST_OFFSET
 
- TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
 
- TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT
 
- TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
 
- TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT
 
- TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
 
- TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT
 
- TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
 
- TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT
 
- TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE
 
- TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT
 
- TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE
 
- TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT
 
- TSTORM_ETH_PRS_INPUT_OFFSET
 
- TSTORM_ETH_PRS_INPUT_SIZE
 
- TSTORM_ETH_RSS_UPDATE_OFFSET
 
- TSTORM_ETH_RSS_UPDATE_SIZE
 
- TSTORM_FATAL_ASSERT_ATTENTION_BIT
 
- TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN
 
- TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT
 
- TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN
 
- TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT
 
- TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN
 
- TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT
 
- TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN
 
- TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT
 
- TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0
 
- TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT
 
- TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1
 
- TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT
 
- TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2
 
- TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT
 
- TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3
 
- TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT
 
- TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK
 
- TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT
 
- TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK
 
- TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT
 
- TSTORM_FCOE_CONN_ST_CTX_MODE_MASK
 
- TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT
 
- TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK
 
- TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT
 
- TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK
 
- TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_SHIFT
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_SHIFT
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT
 
- TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT
 
- TSTORM_FCOE_RX_STATS_OFFSET
 
- TSTORM_FCOE_RX_STATS_SIZE
 
- TSTORM_FUNCTION_COMMON_CONFIG_OFFSET
 
- TSTORM_FUNC_EN_OFFSET
 
- TSTORM_ID
 
- TSTORM_INTEG_TEST_DATA_OFFSET
 
- TSTORM_INTEG_TEST_DATA_SIZE
 
- TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN
 
- TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN_SHIFT
 
- TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN
 
- TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN_SHIFT
 
- TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0
 
- TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT
 
- TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1
 
- TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT
 
- TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2
 
- TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT
 
- TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3
 
- TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT
 
- TSTORM_ISCSI_ERROR_BITMAP_OFFSET
 
- TSTORM_ISCSI_L2_ISCSI_OOO_CID_TABLE_OFFSET
 
- TSTORM_ISCSI_L2_ISCSI_OOO_CLIENT_ID_TABLE_OFFSET
 
- TSTORM_ISCSI_L2_ISCSI_OOO_PROD_OFFSET
 
- TSTORM_ISCSI_NUM_OF_TASKS_OFFSET
 
- TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET
 
- TSTORM_ISCSI_PAGE_SIZE_OFFSET
 
- TSTORM_ISCSI_RQ_SIZE_OFFSET
 
- TSTORM_ISCSI_RX_STATS_OFFSET
 
- TSTORM_ISCSI_RX_STATS_SIZE
 
- TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN
 
- TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN_SHIFT
 
- TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS
 
- TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS_SHIFT
 
- TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE
 
- TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE_SHIFT
 
- TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN
 
- TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT
 
- TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER
 
- TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER_SHIFT
 
- TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN
 
- TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN_SHIFT
 
- TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0
 
- TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0_SHIFT
 
- TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET
 
- TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET
 
- TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET
 
- TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET
 
- TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET
 
- TSTORM_L5CM_TCP_FLAGS_DELAYED_ACK_EN
 
- TSTORM_L5CM_TCP_FLAGS_DELAYED_ACK_SHIFT
 
- TSTORM_L5CM_TCP_FLAGS_RSRV1
 
- TSTORM_L5CM_TCP_FLAGS_RSRV1_SHIFT
 
- TSTORM_L5CM_TCP_FLAGS_TS_ENABLED
 
- TSTORM_L5CM_TCP_FLAGS_TS_ENABLED_SHIFT
 
- TSTORM_L5CM_TCP_FLAGS_VLAN_ID
 
- TSTORM_L5CM_TCP_FLAGS_VLAN_ID_SHIFT
 
- TSTORM_LL2_PORT_STAT_OFFSET
 
- TSTORM_LL2_PORT_STAT_SIZE
 
- TSTORM_LL2_RX_PRODS_OFFSET
 
- TSTORM_LL2_RX_PRODS_SIZE
 
- TSTORM_MAC_FILTER_CONFIG_OFFSET
 
- TSTORM_PORT_STAT_OFFSET
 
- TSTORM_PORT_STAT_SIZE
 
- TSTORM_QZONE_SIZE
 
- TSTORM_QZONE_START
 
- TSTORM_RDMA_ASSERT_LEVEL_OFFSET
 
- TSTORM_RDMA_ASSERT_LEVEL_SIZE
 
- TSTORM_RDMA_QUEUE_STAT_OFFSET
 
- TSTORM_RDMA_QUEUE_STAT_SIZE
 
- TSTORM_RECORD_SLOW_PATH_OFFSET
 
- TSTORM_ROCE_EVENTS_STAT_OFFSET
 
- TSTORM_ROCE_EVENTS_STAT_SIZE
 
- TSTORM_SCSI_BDQ_EXT_PROD_OFFSET
 
- TSTORM_SCSI_BDQ_EXT_PROD_SIZE
 
- TSTORM_SCSI_CMDQ_CONS_OFFSET
 
- TSTORM_SCSI_CMDQ_CONS_SIZE
 
- TSTORM_TCP_MAX_CWND_OFFSET
 
- TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN
 
- TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN_SHIFT
 
- TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN
 
- TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN_SHIFT
 
- TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE
 
- TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE_SHIFT
 
- TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED
 
- TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED_SHIFT
 
- TSTORM_TCP_ST_CONTEXT_SECTION_LAST_ISLE_HAS_FIN
 
- TSTORM_TCP_ST_CONTEXT_SECTION_LAST_ISLE_HAS_FIN_SHIFT
 
- TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN
 
- TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN_SHIFT
 
- TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID
 
- TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID_SHIFT
 
- TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED0
 
- TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED0_SHIFT
 
- TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT
 
- TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT_SHIFT
 
- TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION
 
- TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION_SHIFT
 
- TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD
 
- TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD_SHIFT
 
- TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS
 
- TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS_SHIFT
 
- TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS
 
- TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT
 
- TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS
 
- TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_SHIFT
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_SHIFT
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN_SHIFT
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT
 
- TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT
 
- TSTORM_VF_TO_PF_OFFSET
 
- TSTR
 
- TSTREAD1
 
- TSTWRITE
 
- TST_BUFF
 
- TST_CARR_SUPP
 
- TST_CFG_WRITE_OFF
 
- TST_CFG_WRITE_ON
 
- TST_DC_COMP_LOOP
 
- TST_DDFS
 
- TST_FRC_APERR_1M64
 
- TST_FRC_APERR_2M64
 
- TST_FRC_APERR_M
 
- TST_FRC_APERR_T
 
- TST_FRC_DPERR_MR
 
- TST_FRC_DPERR_MR64
 
- TST_FRC_DPERR_MW
 
- TST_FRC_DPERR_MW64
 
- TST_FRC_DPERR_TR
 
- TST_FRC_DPERR_TW
 
- TST_LCAR
 
- TST_LCOL
 
- TST_LOOPBACK
 
- TST_LUN_READY
 
- TST_RTRY
 
- TST_SWITCH_DONE
 
- TST_SWITCH_PENDING
 
- TST_SWITCH_WAIT
 
- TST_TXFILT0
 
- TST_TXFILT1
 
- TST_TXTEST_ENABLE
 
- TST_TXTEST_PHASE
 
- TST_TXTEST_RATE
 
- TST_TXTEST_RATE_11MBPS
 
- TST_TXTEST_RATE_1MBPS
 
- TST_TXTEST_RATE_2MBPS
 
- TST_TXTEST_RATE_5_5MBPS
 
- TST_TXTEST_RATE_SHIFT
 
- TST_UFLO
 
- TST_UNSCRAM
 
- TST_V
 
- TSUCTRL_CTCRESYNC
 
- TSUNAMI_ALC
 
- TSUNAMI_AV
 
- TSUNAMI_BASE
 
- TSUNAMI_CONF
 
- TSUNAMI_DAC_OFFSET
 
- TSUNAMI_DENAB
 
- TSUNAMI_DV
 
- TSUNAMI_HAE_ADDRESS
 
- TSUNAMI_HOSE
 
- TSUNAMI_IACK_SC
 
- TSUNAMI_IENAB
 
- TSUNAMI_IO
 
- TSUNAMI_IO_BIAS
 
- TSUNAMI_IO_SPACE
 
- TSUNAMI_ITD
 
- TSUNAMI_ME
 
- TSUNAMI_MEM
 
- TSUNAMI_MEM_BIAS
 
- TSUNAMI_MV
 
- TSUNAMI_NF
 
- TSUNAMI_PC
 
- TSUNAMI_PE
 
- TSUNAMI_RCMASK
 
- TSUNAMI_SW
 
- TSUNAMI_cchip
 
- TSUNAMI_dchip
 
- TSUNAMI_pchip0
 
- TSUNAMI_pchip1
 
- TSU_ADQT0
 
- TSU_ADQT1
 
- TSU_ADRH0
 
- TSU_ADSBSY
 
- TSU_ADSBSY_0
 
- TSU_ADSBSY_BIT
 
- TSU_BSYSL0
 
- TSU_BSYSL1
 
- TSU_CTRST
 
- TSU_FCM
 
- TSU_FWEN0
 
- TSU_FWEN0_0
 
- TSU_FWEN0_BIT
 
- TSU_FWEN1
 
- TSU_FWINMK
 
- TSU_FWSL0
 
- TSU_FWSL0_BIT
 
- TSU_FWSL0_FW10
 
- TSU_FWSL0_FW20
 
- TSU_FWSL0_FW30
 
- TSU_FWSL0_FW40
 
- TSU_FWSL0_FW50
 
- TSU_FWSL0_RMSA0
 
- TSU_FWSL1
 
- TSU_FWSLC
 
- TSU_FWSLC_BIT
 
- TSU_FWSLC_CAMSEL00
 
- TSU_FWSLC_CAMSEL01
 
- TSU_FWSLC_CAMSEL02
 
- TSU_FWSLC_CAMSEL03
 
- TSU_FWSLC_CAMSEL10
 
- TSU_FWSLC_CAMSEL11
 
- TSU_FWSLC_CAMSEL12
 
- TSU_FWSLC_CAMSEL13
 
- TSU_FWSLC_POSTENL
 
- TSU_FWSLC_POSTENU
 
- TSU_FWSR
 
- TSU_NSEC_MAX_VAL
 
- TSU_POST1
 
- TSU_POST2
 
- TSU_POST3
 
- TSU_POST4
 
- TSU_PRISL0
 
- TSU_PRISL1
 
- TSU_QTAG0
 
- TSU_QTAG1
 
- TSU_QTAGM0
 
- TSU_QTAGM1
 
- TSU_SEC_MAX_VAL
 
- TSU_TEN
 
- TSU_TEN_0
 
- TSU_TEN_BIT
 
- TSU_VTAG0
 
- TSU_VTAG1
 
- TSU_VTAG_ENABLE
 
- TSU_VTAG_VID_MASK
 
- TSVAL_G
 
- TSVAL_M
 
- TSVAL_S
 
- TSVAL_V
 
- TSV_BACKPRESSUREAPP
 
- TSV_BITMASK
 
- TSV_BYTEOF
 
- TSV_GETBIT
 
- TSV_SIZE
 
- TSV_TOTBYTETXONWIRE
 
- TSV_TXBROADCAST
 
- TSV_TXBYTECNT
 
- TSV_TXCOLLISIONCNT
 
- TSV_TXCONTROLFRAME
 
- TSV_TXCRCERROR
 
- TSV_TXDONE
 
- TSV_TXEXCOLLISION
 
- TSV_TXEXDEFER
 
- TSV_TXGIANT
 
- TSV_TXLATECOLLISION
 
- TSV_TXLENCHKERROR
 
- TSV_TXLENOUTOFRANGE
 
- TSV_TXMULTICAST
 
- TSV_TXPACKETDEFER
 
- TSV_TXPAUSEFRAME
 
- TSV_TXUNDERRUN
 
- TSV_TXVLANTAGFRAME
 
- TSX_CTRL_CPUID_CLEAR
 
- TSX_CTRL_DISABLE
 
- TSX_CTRL_ENABLE
 
- TSX_CTRL_NOT_SUPPORTED
 
- TSX_CTRL_RTM_DISABLE
 
- TSYNC_INTERRUPTS
 
- TSYNC_SIBLINGS
 
- TSYS01_ADC_READ
 
- TSYS01_CONVERSION_START
 
- TSYS01_PROM_READ
 
- TSYS01_PROM_WORDS_NB
 
- TSYS01_RESET
 
- TSYS02D_RESET
 
- TS_107
 
- TS_129
 
- TS_130
 
- TS_131
 
- TS_132
 
- TS_16COL
 
- TS_319
 
- TS_320
 
- TS_ACTION
 
- TS_ADDBA_DELAY
 
- TS_ADD_VALUE
 
- TS_AF_A
 
- TS_AF_D
 
- TS_AGC_LK_TH
 
- TS_AND_SSP0_CS2_REG2_MASK
 
- TS_ANNEX_D_EN
 
- TS_ANNEX_F_EN
 
- TS_APPEND
 
- TS_AUTOLOAD
 
- TS_BD_PKT_STAT
 
- TS_BIAS
 
- TS_BLK
 
- TS_BLKUSE
 
- TS_BLOCK_SIZE
 
- TS_BMON
 
- TS_BUFFER_TIMEOUT
 
- TS_BUFLEN
 
- TS_CAPTURE_LEN
 
- TS_CASCADE_ENABLE
 
- TS_CASCADE_TAIL
 
- TS_CASCADE_UPS_M
 
- TS_CASCADE_UPS_S
 
- TS_CH_XM
 
- TS_CH_XP
 
- TS_CH_YM
 
- TS_CH_YP
 
- TS_CKFPR
 
- TS_CLK
 
- TS_CLK_FREERUN
 
- TS_CLK_GATED
 
- TS_CLK_INVERTED
 
- TS_CLK_NORMAL
 
- TS_CLOCK
 
- TS_CLTD
 
- TS_COMM_LEN
 
- TS_COMP1
 
- TS_COMP2
 
- TS_COMPAT
 
- TS_CONFIG_CLK_SRC_MASK
 
- TS_CONFIG_MAX_CLK_SRC
 
- TS_CONFIG_RESET
 
- TS_CONTROL
 
- TS_CONTROL2
 
- TS_CONTROLLER_AVGDATA_MASK
 
- TS_CONTROLLER_AVGDATA_SHIFT
 
- TS_CONTROLLER_EN_BIT
 
- TS_CONTROLLER_PWR_ADC
 
- TS_CONTROLLER_PWR_BGP
 
- TS_CONTROLLER_PWR_LDO
 
- TS_CONTROLLER_PWR_TS
 
- TS_CPU_MASK
 
- TS_CPU_SHIFT
 
- TS_CTL_DST_PORT
 
- TS_CTL_DST_PORT_SHIFT
 
- TS_CTL_MADDR_ALL
 
- TS_CTL_MADDR_SHIFT
 
- TS_CTRL_M
 
- TS_CTRL_REG_1
 
- TS_CTRL_REG_2
 
- TS_DECODER
 
- TS_DELTA_TEST
 
- TS_DEMUX
 
- TS_DETECT_FALL
 
- TS_DETECT_RISE
 
- TS_DETECT_S
 
- TS_DMA_BYTES
 
- TS_DMA_PACKETS
 
- TS_DRIFT_ADJUST_KEEP
 
- TS_DRIFT_ADJUST_RESET
 
- TS_DRIFT_ADJUST_SET
 
- TS_ENABLE
 
- TS_EVENT_DETECT_M
 
- TS_EVENT_DETECT_S
 
- TS_EVENT_EDGE_M
 
- TS_EVENT_EDGE_S
 
- TS_EVENT_NANOSEC_M
 
- TS_EVENT_OVERFLOW
 
- TS_EVENT_SAMPLE
 
- TS_EVENT_SUB_NANOSEC_M
 
- TS_FIFO_INTR_MASK
 
- TS_FIFO_OVFL_STAT
 
- TS_FILLER
 
- TS_FORMAT
 
- TS_FPR
 
- TS_FPROFFSET
 
- TS_FPRWIDTH
 
- TS_FSM_ALNUM
 
- TS_FSM_ALPHA
 
- TS_FSM_ANY
 
- TS_FSM_ASCII
 
- TS_FSM_CNTRL
 
- TS_FSM_DIGIT
 
- TS_FSM_GRAPH
 
- TS_FSM_HEAD_IGNORE
 
- TS_FSM_LOWER
 
- TS_FSM_MULTI
 
- TS_FSM_PERHAPS
 
- TS_FSM_PRINT
 
- TS_FSM_PUNCT
 
- TS_FSM_RECUR_MAX
 
- TS_FSM_SINGLE
 
- TS_FSM_SPACE
 
- TS_FSM_SPECIFIC
 
- TS_FSM_TYPE_MAX
 
- TS_FSM_UPPER
 
- TS_FSM_WILDCARD
 
- TS_FSM_XDIGIT
 
- TS_FTD
 
- TS_GEN_CNTRL
 
- TS_GPI_M
 
- TS_GPI_S
 
- TS_HEIGHT
 
- TS_HEIGHT_MASK
 
- TS_HEIGHT_MASK_ACTIVY
 
- TS_HEIGHT_MASK_DVBC
 
- TS_HI_BIT
 
- TS_HI_SHIFT
 
- TS_HW_SOP_CNTRL
 
- TS_I386_REGS_POKED
 
- TS_IGNORECASE
 
- TS_INDEX2VAL
 
- TS_INIT
 
- TS_INSERT
 
- TS_INT_ENABLE
 
- TS_INT_GPIO
 
- TS_INT_S
 
- TS_INVALID
 
- TS_IN_USE
 
- TS_LATCOL
 
- TS_LOAD_EN
 
- TS_LOSTCAR
 
- TS_LOW_BIT
 
- TS_LOW_SHIFT
 
- TS_LPK
 
- TS_LPK_L
 
- TS_LPK_M
 
- TS_LT2_EN
 
- TS_LTYPE1_EN
 
- TS_LTYPE2_EN
 
- TS_LUN_CHANGE
 
- TS_MAJOR
 
- TS_MAJOR_1
 
- TS_MAJOR_3
 
- TS_MASK
 
- TS_MAX_BUFSIZE_K
 
- TS_MAX_BUFSIZE_K_ACTIVY
 
- TS_MAX_BUFSIZE_K_DVBC
 
- TS_MAX_PACKETS
 
- TS_MINOR
 
- TS_MIN_BUFSIZE_K
 
- TS_MIN_IFG_MASK
 
- TS_MIN_IFG_SHIFT
 
- TS_MODE_REG
 
- TS_MSG_TYPE_EN_MASK
 
- TS_MSG_TYPE_EN_SHIFT
 
- TS_NAME
 
- TS_NAND_CTRL
 
- TS_NAND_DATA
 
- TS_NBUS_DIRECTION_IN
 
- TS_NBUS_DIRECTION_OUT
 
- TS_NBUS_WRITE_ADR
 
- TS_NBUS_WRITE_VAL
 
- TS_NOT_OPER
 
- TS_NOT_PRESENT
 
- TS_OFFSET_DEC
 
- TS_OFFSET_INC
 
- TS_OFFSET_KEEP
 
- TS_OPT_ECN
 
- TS_OPT_SACK
 
- TS_OPT_WSCALE_MASK
 
- TS_PACKET
 
- TS_PACKET_SIZE
 
- TS_PACKET_SZ
 
- TS_PARALLEL
 
- TS_PAYLOAD_ONLY
 
- TS_PEND
 
- TS_PEND_EN
 
- TS_PEND_RAW
 
- TS_PEN_DOWN
 
- TS_PEN_INTR_MASK
 
- TS_PEN_UP_TIMEOUT
 
- TS_PID_TYPE_MPE
 
- TS_PID_TYPE_PSI_SI
 
- TS_PID_TYPE_TS
 
- TS_PKT_SIZE
 
- TS_POLL_DELAY
 
- TS_POLL_PERIOD
 
- TS_PORT
 
- TS_PRESENT
 
- TS_PRIV_ALIGN
 
- TS_PRIV_ALIGNTO
 
- TS_PUSH
 
- TS_PUSI
 
- TS_QDAT
 
- TS_QUEUE_INX
 
- TS_QUIRK_ALT_OSC
 
- TS_QUIRK_REVERSED
 
- TS_QUIRK_SERIAL
 
- TS_RDY
 
- TS_RECENT_STAMP
 
- TS_RES
 
- TS_RESET
 
- TS_RNG_DATA
 
- TS_RTC_CTRL
 
- TS_RTC_DATA
 
- TS_RX_ANX_ALL_EN
 
- TS_RX_ANX_D_EN
 
- TS_RX_ANX_E_EN
 
- TS_RX_ANX_F_EN
 
- TS_RX_EN
 
- TS_RX_VLAN_LT1_EN
 
- TS_RX_VLAN_LT2_EN
 
- TS_SC
 
- TS_SCK
 
- TS_SCK0_A_MARK
 
- TS_SCK0_B_MARK
 
- TS_SCK0_C_MARK
 
- TS_SCK0_D_MARK
 
- TS_SCK0_MARK
 
- TS_SCK1_B_MARK
 
- TS_SCK1_C_MARK
 
- TS_SCK1_MARK
 
- TS_SCK2_MARK
 
- TS_SCK3_MARK
 
- TS_SCK4_MARK
 
- TS_SCK5_MARK
 
- TS_SCK_B_MARK
 
- TS_SCK_C_MARK
 
- TS_SCK_D_MARK
 
- TS_SCK_MARK
 
- TS_SDAT
 
- TS_SDAT0_A_MARK
 
- TS_SDAT0_B_MARK
 
- TS_SDAT0_C_MARK
 
- TS_SDAT0_D_MARK
 
- TS_SDAT0_MARK
 
- TS_SDAT1_B_MARK
 
- TS_SDAT1_C_MARK
 
- TS_SDAT1_MARK
 
- TS_SDAT2_MARK
 
- TS_SDAT3_MARK
 
- TS_SDAT4_MARK
 
- TS_SDAT5_MARK
 
- TS_SDATA0_B_MARK
 
- TS_SDATA0_C_MARK
 
- TS_SDATA0_D_MARK
 
- TS_SDATA0_MARK
 
- TS_SDATA_B_MARK
 
- TS_SDATA_C_MARK
 
- TS_SDATA_D_MARK
 
- TS_SDATA_MARK
 
- TS_SDAT_MARK
 
- TS_SDEN
 
- TS_SDEN0_A_MARK
 
- TS_SDEN0_B_MARK
 
- TS_SDEN0_C_MARK
 
- TS_SDEN0_D_MARK
 
- TS_SDEN0_MARK
 
- TS_SDEN1_B_MARK
 
- TS_SDEN1_C_MARK
 
- TS_SDEN1_MARK
 
- TS_SDEN2_MARK
 
- TS_SDEN3_MARK
 
- TS_SDEN4_MARK
 
- TS_SDEN5_MARK
 
- TS_SDEN_B_MARK
 
- TS_SDEN_C_MARK
 
- TS_SDEN_D_MARK
 
- TS_SDEN_MARK
 
- TS_SDP0_EN
 
- TS_SDP0_SEL_FC0
 
- TS_SDP0_SEL_FC1
 
- TS_SDP0_SEL_TT0
 
- TS_SDP0_SEL_TT1
 
- TS_SDP1_EN
 
- TS_SDP1_SEL_FC0
 
- TS_SDP1_SEL_FC1
 
- TS_SDP1_SEL_TT0
 
- TS_SDP1_SEL_TT1
 
- TS_SDP2_EN
 
- TS_SDP2_SEL_FC0
 
- TS_SDP2_SEL_FC1
 
- TS_SDP2_SEL_TT0
 
- TS_SDP2_SEL_TT1
 
- TS_SDP3_EN
 
- TS_SDP3_SEL_FC0
 
- TS_SDP3_SEL_FC1
 
- TS_SDP3_SEL_TT0
 
- TS_SDP3_SEL_TT1
 
- TS_SEC_EN
 
- TS_SEC_LEN_MASK
 
- TS_SEC_LEN_SHIFT
 
- TS_SEQ_ID_OFFSET_MASK
 
- TS_SEQ_ID_OFFSET_SHIFT
 
- TS_SEQ_ID_OFS_MASK
 
- TS_SEQ_ID_OFS_SHIFT
 
- TS_SERIAL
 
- TS_SHIFT
 
- TS_SIZE
 
- TS_SKB_CB
 
- TS_SOP_STAT
 
- TS_SPKT
 
- TS_SPSYNC
 
- TS_SPSYNC0_A_MARK
 
- TS_SPSYNC0_B_MARK
 
- TS_SPSYNC0_C_MARK
 
- TS_SPSYNC0_D_MARK
 
- TS_SPSYNC0_MARK
 
- TS_SPSYNC1_B_MARK
 
- TS_SPSYNC1_C_MARK
 
- TS_SPSYNC1_MARK
 
- TS_SPSYNC2_MARK
 
- TS_SPSYNC3_MARK
 
- TS_SPSYNC4_MARK
 
- TS_SPSYNC5_MARK
 
- TS_SPSYNC_B_MARK
 
- TS_SPSYNC_C_MARK
 
- TS_SPSYNC_D_MARK
 
- TS_SPSYNC_MARK
 
- TS_STOP
 
- TS_STREAM
 
- TS_SUB_VALUE
 
- TS_SUCCESS
 
- TS_SUSP
 
- TS_SW_LIM_H
 
- TS_SW_LIM_L
 
- TS_SW_RATE
 
- TS_SYNC
 
- TS_SYS_108M
 
- TS_SYS_WCLK
 
- TS_SZ
 
- TS_TEI
 
- TS_TTL_NONZERO
 
- TS_TX_ANX_ALL_EN
 
- TS_TX_ANX_D_EN
 
- TS_TX_ANX_E_EN
 
- TS_TX_ANX_F_EN
 
- TS_TX_EN
 
- TS_TX_VLAN_LT1_EN
 
- TS_TX_VLAN_LT2_EN
 
- TS_UAC_NOFIX
 
- TS_UAC_NOPRINT
 
- TS_UAC_SIGBUS
 
- TS_UNIT_M
 
- TS_UNI_EN
 
- TS_UNI_EN_SHIFT
 
- TS_UNUSED
 
- TS_USEDFPU
 
- TS_VALERR_CNTRL
 
- TS_VECTOR
 
- TS_VERSION
 
- TS_VERSION_1
 
- TS_VERSION_3
 
- TS_VER_COUNT
 
- TS_VFP_EN
 
- TS_VSRLOWOFFSET
 
- TS_WEOT
 
- TS_WIDTH
 
- TS_WIDTH_ACTIVY
 
- TS_WIDTH_DVBC
 
- TS_WIPER
 
- TS_WIRE_MODE_BIT
 
- TT
 
- TT0
 
- TT110
 
- TT1770
 
- TT1_SHIFT
 
- TT221
 
- TT2_SHIFT
 
- TT3539
 
- TT3650_CMD_CI_RD_ATTR
 
- TT3650_CMD_CI_RD_CTRL
 
- TT3650_CMD_CI_RESET
 
- TT3650_CMD_CI_SET_VIDEO_PORT
 
- TT3650_CMD_CI_TEST
 
- TT3650_CMD_CI_WR_ATTR
 
- TT3650_CMD_CI_WR_CTRL
 
- TT422
 
- TT55
 
- TT885
 
- TTA_GET
 
- TTA_SURE
 
- TTBCR
 
- TTBCR_A1
 
- TTBCR_EAE
 
- TTBCR_EPD0
 
- TTBCR_EPD1
 
- TTBCR_IMP
 
- TTBCR_IRGN0
 
- TTBCR_IRGN1
 
- TTBCR_ORGN0
 
- TTBCR_ORGN1
 
- TTBCR_SH0
 
- TTBCR_SH1
 
- TTBCR_T0SZ
 
- TTBCR_T1SZ
 
- TTBR0
 
- TTBR0_EL1
 
- TTBR0_IRGNH
 
- TTBR0_IRGNH_MASK
 
- TTBR0_IRGNH_SHIFT
 
- TTBR0_IRGNL
 
- TTBR0_IRGNL_MASK
 
- TTBR0_IRGNL_SHIFT
 
- TTBR0_NOS
 
- TTBR0_NOS_MASK
 
- TTBR0_NOS_SHIFT
 
- TTBR0_ORGN
 
- TTBR0_ORGN_MASK
 
- TTBR0_ORGN_SHIFT
 
- TTBR0_PA
 
- TTBR0_PA_MASK
 
- TTBR0_PA_SHIFT
 
- TTBR0_SH
 
- TTBR0_SH_MASK
 
- TTBR0_SH_SHIFT
 
- TTBR1
 
- TTBR1_BADDR_4852_OFFSET
 
- TTBR1_EL1
 
- TTBR1_IRGNH
 
- TTBR1_IRGNH_MASK
 
- TTBR1_IRGNH_SHIFT
 
- TTBR1_IRGNL
 
- TTBR1_IRGNL_MASK
 
- TTBR1_IRGNL_SHIFT
 
- TTBR1_NOS
 
- TTBR1_NOS_MASK
 
- TTBR1_NOS_SHIFT
 
- TTBR1_OFFSET
 
- TTBR1_ORGN
 
- TTBR1_ORGN_MASK
 
- TTBR1_ORGN_SHIFT
 
- TTBR1_PA
 
- TTBR1_PA_MASK
 
- TTBR1_PA_SHIFT
 
- TTBR1_SH
 
- TTBR1_SH_MASK
 
- TTBR1_SH_SHIFT
 
- TTBR1_SIZE
 
- TTBR_ASID_MASK
 
- TTBR_BADDR_MASK_52
 
- TTBR_CNP_BIT
 
- TTBRn_ASID
 
- TTB_C
 
- TTB_EAE
 
- TTB_FLAGS_SMP
 
- TTB_FLAGS_UP
 
- TTB_IMP
 
- TTB_IRGN_NC
 
- TTB_IRGN_WB
 
- TTB_IRGN_WBWA
 
- TTB_IRGN_WT
 
- TTB_NOS
 
- TTB_RGN_NC
 
- TTB_RGN_OC_WB
 
- TTB_RGN_OC_WBWA
 
- TTB_RGN_OC_WT
 
- TTB_RGN_WB
 
- TTB_RGN_WBWA
 
- TTB_RGN_WT
 
- TTB_S
 
- TTCDKB_GPIO_EXT0
 
- TTCDKB_GPIO_EXT1
 
- TTCDKB_NR_IRQS
 
- TTCTRL_TTHA
 
- TTCTRL_TTHA_MASK
 
- TTC_CLK_CNTRL_CSRC_MASK
 
- TTC_CLK_CNTRL_OFFSET
 
- TTC_CLK_CNTRL_PSV_MASK
 
- TTC_CLK_CNTRL_PSV_SHIFT
 
- TTC_CNT_CNTRL_DISABLE_MASK
 
- TTC_CNT_CNTRL_OFFSET
 
- TTC_COUNT_VAL_OFFSET
 
- TTC_IER_OFFSET
 
- TTC_INTR_VAL_OFFSET
 
- TTC_ISR_OFFSET
 
- TTIPEND
 
- TTI_CMD_MEM_OFFSET
 
- TTI_CMD_MEM_STROBE_BEING_EXECUTED
 
- TTI_CMD_MEM_STROBE_NEW_CMD
 
- TTI_CMD_MEM_WE
 
- TTI_DATA1_MEM_TX_TIMER_AC_CI
 
- TTI_DATA1_MEM_TX_TIMER_AC_EN
 
- TTI_DATA1_MEM_TX_TIMER_CI_EN
 
- TTI_DATA1_MEM_TX_TIMER_VAL
 
- TTI_DATA1_MEM_TX_URNG_A
 
- TTI_DATA1_MEM_TX_URNG_B
 
- TTI_DATA1_MEM_TX_URNG_C
 
- TTI_DATA2_MEM_TX_UFC_A
 
- TTI_DATA2_MEM_TX_UFC_B
 
- TTI_DATA2_MEM_TX_UFC_C
 
- TTI_DATA2_MEM_TX_UFC_D
 
- TTI_ECC_DB_ERR
 
- TTI_ECC_SG_ERR
 
- TTI_QL355P_PID
 
- TTI_SM_ERR_ALARM
 
- TTI_T1A_TX_UFC_A
 
- TTI_T1A_TX_UFC_B
 
- TTI_T1A_TX_UFC_C
 
- TTI_T1A_TX_UFC_D
 
- TTI_TX_UFC_A
 
- TTI_TX_UFC_B
 
- TTI_TX_UFC_C
 
- TTI_TX_UFC_D
 
- TTI_TX_URANGE_A
 
- TTI_TX_URANGE_B
 
- TTI_TX_URANGE_C
 
- TTI_VID
 
- TTInit
 
- TTL_OTHER
 
- TTMFP_SOURCE_BASE
 
- TTMS
 
- TTM_BO_MAP_IOMEM_MASK
 
- TTM_BO_VM_NUM_PREFAULT
 
- TTM_MAX_BO_PRIORITY
 
- TTM_MEMORY_ALLOC_RETRIES
 
- TTM_MEMORY_H
 
- TTM_MEMTYPE_FLAG_CMA
 
- TTM_MEMTYPE_FLAG_FIXED
 
- TTM_MEMTYPE_FLAG_MAPPABLE
 
- TTM_MEM_MAX_ZONES
 
- TTM_NUM_MEM_TYPES
 
- TTM_OBJ_EXTRA_SIZE
 
- TTM_OPT_FLAG_ALLOW_RES_EVICT
 
- TTM_OPT_FLAG_FORCE_ALLOC
 
- TTM_PAGE_ALLOC
 
- TTM_PAGE_FLAG_DMA32
 
- TTM_PAGE_FLAG_NO_RETRY
 
- TTM_PAGE_FLAG_PERSISTENT_SWAP
 
- TTM_PAGE_FLAG_SG
 
- TTM_PAGE_FLAG_SWAPPED
 
- TTM_PAGE_FLAG_WRITE
 
- TTM_PAGE_FLAG_ZERO_ALLOC
 
- TTM_PFX
 
- TTM_PL_FLAG_CACHED
 
- TTM_PL_FLAG_CONTIGUOUS
 
- TTM_PL_FLAG_NO_EVICT
 
- TTM_PL_FLAG_PRIV
 
- TTM_PL_FLAG_SYSTEM
 
- TTM_PL_FLAG_TOPDOWN
 
- TTM_PL_FLAG_TT
 
- TTM_PL_FLAG_UNCACHED
 
- TTM_PL_FLAG_VRAM
 
- TTM_PL_FLAG_WC
 
- TTM_PL_MASK_CACHING
 
- TTM_PL_MASK_MEM
 
- TTM_PL_MASK_MEMTYPE
 
- TTM_PL_PRIV
 
- TTM_PL_SYSTEM
 
- TTM_PL_TT
 
- TTM_PL_VRAM
 
- TTM_REF_NUM
 
- TTM_REF_SYNCCPU_READ
 
- TTM_REF_SYNCCPU_WRITE
 
- TTM_REF_USAGE
 
- TTM_SET_MEMORY
 
- TTM_SUSPEND_LOCK
 
- TTM_SUSPEND_LOCK_PENDING
 
- TTM_VT_LOCK
 
- TTM_VT_LOCK_PENDING
 
- TTM_WRITE_LOCK_PENDING
 
- TTMixerInit
 
- TTMixerIoctl
 
- TTO_PRESCL_CTRL0
 
- TTO_PRESCL_CTRL0_DIVA
 
- TTO_PRESCL_CTRL0_DIVB
 
- TTO_PRESCL_CTRL1
 
- TTO_PRESCL_CTRL1_DIVA
 
- TTO_PRESCL_CTRL1_DIVB
 
- TTRS_ANYWAY
 
- TTRS_FULL
 
- TTRS_UNMAPPED
 
- TTS
 
- TTSL0
 
- TTS_ALMOST_EMPTY
 
- TTS_ALMOST_FULL
 
- TTS_READABLE
 
- TTS_SPEAKING
 
- TTS_SPEAKING2
 
- TTS_WRITABLE
 
- TTSetFormat
 
- TTSetGain
 
- TTSetVolume
 
- TTSilence
 
- TTStateInfo
 
- TTUS
 
- TTUSBDECFE_H
 
- TTUSB_BUDGET_NAME
 
- TTUSB_DEC2000T
 
- TTUSB_DEC2540T
 
- TTUSB_DEC3000S
 
- TTUSB_DEC_INTERFACE_IN
 
- TTUSB_DEC_INTERFACE_INITIAL
 
- TTUSB_DEC_INTERFACE_OUT
 
- TTUSB_DEC_PACKET_EMPTY
 
- TTUSB_DEC_PACKET_PVA
 
- TTUSB_DEC_PACKET_SECTION
 
- TTUSB_MAXCHANNEL
 
- TTUSB_MAXFILTER
 
- TTUSB_REV_2_2
 
- TTU_BATCH_FLUSH
 
- TTU_IGNORE_ACCESS
 
- TTU_IGNORE_HWPOISON
 
- TTU_IGNORE_MLOCK
 
- TTU_MIGRATION
 
- TTU_MUNLOCK
 
- TTU_RMAP_LOCKED
 
- TTU_SPLIT_FREEZE
 
- TTU_SPLIT_HUGE_PMD
 
- TTX_REG
 
- TTY3270_CHAR_BUF_SIZE
 
- TTY3270_OUTPUT_BUFFER_SIZE
 
- TTY3270_STRING_PAGES
 
- TTYAUX_MAJOR
 
- TTYB_ALIGN_MASK
 
- TTYB_DEFAULT_MEM_LIMIT
 
- TTYB_NORMAL
 
- TTYNAME
 
- TTYTYPE_MODEM
 
- TTYTYPE_MONITOR
 
- TTYTYPE_RAS_RAW
 
- TTY_BREAK
 
- TTY_BUFFER_PAGE
 
- TTY_CLOSED
 
- TTY_DEBUG_HANGUP
 
- TTY_DEBUG_WAIT_UNTIL_SENT
 
- TTY_DEV_NAME
 
- TTY_DO_WRITE_WAKEUP
 
- TTY_DRIVER_DEVPTS_MEM
 
- TTY_DRIVER_DYNAMIC_ALLOC
 
- TTY_DRIVER_DYNAMIC_DEV
 
- TTY_DRIVER_HARDWARE_BREAK
 
- TTY_DRIVER_INSTALLED
 
- TTY_DRIVER_MAGIC
 
- TTY_DRIVER_REAL_RAW
 
- TTY_DRIVER_RESET_TERMIOS
 
- TTY_DRIVER_TYPE_CONSOLE
 
- TTY_DRIVER_TYPE_PTY
 
- TTY_DRIVER_TYPE_SCC
 
- TTY_DRIVER_TYPE_SERIAL
 
- TTY_DRIVER_TYPE_SYSCONS
 
- TTY_DRIVER_TYPE_SYSTEM
 
- TTY_DRIVER_UNNUMBERED_NODE
 
- TTY_EXCLUSIVE
 
- TTY_FRAME
 
- TTY_HUPPED
 
- TTY_HUPPING
 
- TTY_IO_ERROR
 
- TTY_LDISC_CHANGING
 
- TTY_LDISC_HALTED
 
- TTY_LDISC_MAGIC
 
- TTY_LDISC_OPEN
 
- TTY_LOCK_NORMAL
 
- TTY_LOCK_SLAVE
 
- TTY_MAGIC
 
- TTY_MAJOR
 
- TTY_MAX_COUNT
 
- TTY_NORMAL
 
- TTY_NO_WRITE_SPLIT
 
- TTY_OPENED
 
- TTY_OTHER_CLOSED
 
- TTY_OVERRUN
 
- TTY_PARANOIA_CHECK
 
- TTY_PARITY
 
- TTY_PORT_ACTIVE
 
- TTY_PORT_CHECK_CD
 
- TTY_PORT_CTS_FLOW
 
- TTY_PORT_INITIALIZED
 
- TTY_PORT_KOPENED
 
- TTY_PORT_SUSPENDED
 
- TTY_PTY_LOCK
 
- TTY_ROCKET_MAJOR
 
- TTY_THRESHOLD_THROTTLE
 
- TTY_THRESHOLD_UNTHROTTLE
 
- TTY_THROTTLED
 
- TTY_THROTTLE_SAFE
 
- TTY_UNTHROTTLE_SAFE
 
- TTY_UPDATE_ALL
 
- TTY_UPDATE_ERASE
 
- TTY_UPDATE_INPUT
 
- TTY_UPDATE_LIST
 
- TTY_UPDATE_STATUS
 
- TT_040
 
- TT_5380
 
- TT_5380_BAS
 
- TT_BULK
 
- TT_BW_LIMIT
 
- TT_COMPAT
 
- TT_CONTROL
 
- TT_DATA
 
- TT_DMA
 
- TT_DMASND
 
- TT_DMASND_BAS
 
- TT_DMI_OVERHEAD
 
- TT_GEN
 
- TT_HIGH
 
- TT_HS_OVERHEAD
 
- TT_INSTR
 
- TT_INTERRUPT
 
- TT_ISOCHRONOUS
 
- TT_LOW
 
- TT_MASK
 
- TT_MFP_BAS
 
- TT_MICROFRAMES_MAX
 
- TT_MICROWIRE
 
- TT_MICROWIRE_BAS
 
- TT_MID
 
- TT_MODE_BASIC
 
- TT_MODE_INFCPU
 
- TT_MODE_OFF
 
- TT_MSG
 
- TT_NATIVE
 
- TT_NONE
 
- TT_OFF
 
- TT_OFFSET
 
- TT_ON
 
- TT_PALETTE_BASE
 
- TT_PALETTE_BLUE_MASK
 
- TT_PALETTE_GREEN_MASK
 
- TT_PALETTE_RED_MASK
 
- TT_PORT
 
- TT_PRTY_TAGGED
 
- TT_RESV
 
- TT_RTC
 
- TT_RTC_BAS
 
- TT_SCC_DMA_BAS
 
- TT_SCSI_DMA_BAS
 
- TT_SCU
 
- TT_SCU_BAS
 
- TT_SHIFTER_GRAYMODE
 
- TT_SHIFTER_MODEMASK
 
- TT_SHIFTER_NUMMODE
 
- TT_SHIFTER_PALETTE_MASK
 
- TT_SHIFTER_STHIGH
 
- TT_SHIFTER_STLOW
 
- TT_SHIFTER_STMID
 
- TT_SHIFTER_TTHIGH
 
- TT_SHIFTER_TTLOW
 
- TT_SHIFTER_TTMID
 
- TT_SLOT
 
- TT_THINK_TIME
 
- TT_TMR_DISABLED
 
- TT_TMR_ONESHOT
 
- TT_TMR_PERIODIC
 
- TT_TP
 
- TT_TP_MASK
 
- TT_TP_SHIFT
 
- TT_TU
 
- TT_TU_MASK
 
- TT_TU_SHIFT
 
- TT_TX_BACKOFF_SIZE
 
- TT_VLAN_TAGGED
 
- TU0
 
- TU1
 
- TU100
 
- TU102_DISP
 
- TU102_DISP_CORE_CHANNEL_DMA
 
- TU102_DISP_CURSOR
 
- TU102_DISP_WINDOW_CHANNEL_DMA
 
- TU102_DISP_WINDOW_IMM_CHANNEL_DMA
 
- TU2
 
- TUA9001_CMD_CEN
 
- TUA9001_CMD_RESETN
 
- TUA9001_CMD_RXEN
 
- TUA9001_H
 
- TUA9001_PRIV_H
 
- TUBASE
 
- TUBGETI
 
- TUBGETMOD
 
- TUBGETO
 
- TUBICMD
 
- TUBOCMD
 
- TUBSETMOD
 
- TUCR
 
- TUCR_32_768kHz
 
- TUCR_3_6864MHz
 
- TUCR_3_6864MHzA
 
- TUCR_96MHzPLL
 
- TUCR_CTB
 
- TUCR_Clock
 
- TUCR_DPS
 
- TUCR_FDC
 
- TUCR_FMC
 
- TUCR_MBGPIO
 
- TUCR_MR
 
- TUCR_MainPLL
 
- TUCR_NoMB
 
- TUCR_PMD
 
- TUCR_RCRC
 
- TUCR_TIC
 
- TUCR_TMC
 
- TUCR_TSEL
 
- TUCR_TTST
 
- TUCR_VAL
 
- TUCR_VDD
 
- TUCR_VDDL
 
- TULIP_BAR
 
- TULIP_BUSMODE_SWRESET
 
- TULIP_CMD_FULLDUPLEX
 
- TULIP_CMD_MUSTBEONE
 
- TULIP_CMD_NOHEARTBEAT
 
- TULIP_CMD_OPERMODE
 
- TULIP_CMD_PASSBADPKT
 
- TULIP_CMD_PORTSELECT
 
- TULIP_CMD_PROMISCUOUS
 
- TULIP_CMD_RECEIVEALL
 
- TULIP_CMD_RXRUN
 
- TULIP_CMD_STOREFWD
 
- TULIP_CMD_THRESHOLDCTL
 
- TULIP_CMD_TXRUN
 
- TULIP_CMD_TXTHRSHLDCTL
 
- TULIP_DEBUG
 
- TULIP_DEFAULT_INTR_MASK
 
- TULIP_DSTS_OWNER
 
- TULIP_DSTS_RxMIIERR
 
- TULIP_DSTS_TxDEFERRED
 
- TULIP_GP_PINSET
 
- TULIP_MAX_CACHE_LINE
 
- TULIP_MIN_CACHE_LINE
 
- TULIP_STS_ABNRMLINTR
 
- TULIP_STS_ERI
 
- TULIP_STS_ETI
 
- TULIP_STS_GTE
 
- TULIP_STS_NORMALINTR
 
- TULIP_STS_RXINTR
 
- TULIP_STS_RXNOBUF
 
- TULIP_STS_RXSTOPPED
 
- TULIP_STS_RXS_STOPPED
 
- TULIP_STS_RXWT
 
- TULIP_STS_SYSERROR
 
- TULIP_STS_TXINTR
 
- TULIP_STS_TXJABER
 
- TULIP_STS_TXNOBUF
 
- TULIP_STS_TXSTOPPED
 
- TULIP_STS_TXUNDERFLOW
 
- TULIP_WATCHDOG_RXDISABLE
 
- TULIP_WATCHDOG_TXDISABLE
 
- TUL_DCtrl
 
- TUL_DMACFG
 
- TUL_GCTRL
 
- TUL_GCTRL1
 
- TUL_GCTRL_EEPROM_BIT
 
- TUL_GIMSK
 
- TUL_GINTS
 
- TUL_HACFG0
 
- TUL_HACFG1
 
- TUL_HACFG2
 
- TUL_Int
 
- TUL_Mask
 
- TUL_NVRAM
 
- TUL_PBAD
 
- TUL_PBAD1
 
- TUL_PBAD2
 
- TUL_PBAD3
 
- TUL_PBAD4
 
- TUL_PBAD5
 
- TUL_PBC
 
- TUL_PBIST
 
- TUL_PCLS
 
- TUL_PCMD
 
- TUL_PDID
 
- TUL_PHDT
 
- TUL_PIGNT
 
- TUL_PINTL
 
- TUL_PINTP
 
- TUL_PLTR
 
- TUL_PMGNT
 
- TUL_PPI
 
- TUL_PRAD
 
- TUL_PRID
 
- TUL_PRSVD
 
- TUL_PRSVD1
 
- TUL_PRSVD2
 
- TUL_PRSVD3
 
- TUL_PSC
 
- TUL_PSTUS
 
- TUL_PVID
 
- TUL_SAvail
 
- TUL_SBusId
 
- TUL_SCFG1
 
- TUL_SCmd
 
- TUL_SCnt0
 
- TUL_SCnt1
 
- TUL_SCnt2
 
- TUL_SConfig
 
- TUL_SCtrl0
 
- TUL_SCtrl1
 
- TUL_SDCFG0
 
- TUL_SDCFG1
 
- TUL_SDCFG2
 
- TUL_SDCFG3
 
- TUL_SData
 
- TUL_SFifo
 
- TUL_SFifoCnt
 
- TUL_SIdent
 
- TUL_SInt
 
- TUL_SIntEnable
 
- TUL_SOffset
 
- TUL_SPeriod
 
- TUL_SScsiId
 
- TUL_SSignal
 
- TUL_SStatus0
 
- TUL_SStatus1
 
- TUL_SStatus2
 
- TUL_STest0
 
- TUL_STest1
 
- TUL_STimeOut
 
- TUL_WCtrl
 
- TUL_XAddH
 
- TUL_XAddW
 
- TUL_XCmd
 
- TUL_XCntH
 
- TUL_XCntW
 
- TUL_XCtrl
 
- TUL_XCtrl1
 
- TUL_XFifo
 
- TUL_XStatus
 
- TUMBLER_MUTE_AMP
 
- TUMBLER_MUTE_HP
 
- TUMBLER_MUTE_LINE
 
- TUNATTACHFILTER
 
- TUND
 
- TUNDETACHFILTER
 
- TUND_ADDR
 
- TUNE
 
- TUNER
 
- TUNER_ABSENT
 
- TUNER_ADDR
 
- TUNER_AFC
 
- TUNER_ALPS_TSBB5_PAL_I
 
- TUNER_ALPS_TSBC5_PAL
 
- TUNER_ALPS_TSBE1_PAL
 
- TUNER_ALPS_TSBE5_PAL
 
- TUNER_ALPS_TSBH1_NTSC
 
- TUNER_ALPS_TSHC6_NTSC
 
- TUNER_AUDIO_LANG1
 
- TUNER_AUDIO_LANG2
 
- TUNER_AUDIO_MONO
 
- TUNER_AUDIO_STEREO
 
- TUNER_CHARGE_PUMP
 
- TUNER_DEFAULT
 
- TUNER_DISABLED
 
- TUNER_FL
 
- TUNER_GO
 
- TUNER_HITACHI_NTSC
 
- TUNER_INVERT_IF_SPECTRUM
 
- TUNER_LG
 
- TUNER_LG_NTSC_FM
 
- TUNER_LG_NTSC_NEW_TAPC
 
- TUNER_LG_NTSC_TAPE
 
- TUNER_LG_PAL
 
- TUNER_LG_PAL_FM
 
- TUNER_LG_PAL_I
 
- TUNER_LG_PAL_I_FM
 
- TUNER_LG_PAL_NEW_TAPC
 
- TUNER_LG_TALN
 
- TUNER_LG_TDVS_H06XF
 
- TUNER_LOCKED
 
- TUNER_MICROTUNE_4042FI5
 
- TUNER_MICROTUNE_4049FM5
 
- TUNER_MODE
 
- TUNER_MODE_6MHZ
 
- TUNER_MODE_7MHZ
 
- TUNER_MODE_8MHZ
 
- TUNER_MODE_AF
 
- TUNER_MODE_ANALOG
 
- TUNER_MODE_AUTO_SEEK
 
- TUNER_MODE_AUTO_SEEK_BULK
 
- TUNER_MODE_AUTO_SEEK_PI
 
- TUNER_MODE_DIGITAL
 
- TUNER_MODE_FM_RADIO
 
- TUNER_MODE_LOCK
 
- TUNER_MODE_PRESET
 
- TUNER_MODE_SET
 
- TUNER_MODE_STOP_SEARCH
 
- TUNER_MODE_SUB0
 
- TUNER_MODE_SUB1
 
- TUNER_MODE_SUB2
 
- TUNER_MODE_SUB3
 
- TUNER_MODE_SUB4
 
- TUNER_MODE_SUB5
 
- TUNER_MODE_SUB6
 
- TUNER_MODE_SUB7
 
- TUNER_MODE_SUBALL
 
- TUNER_MODE_SUB_MAX
 
- TUNER_MODE_SWITCH
 
- TUNER_MT2032
 
- TUNER_MUL
 
- TUNER_NONE
 
- TUNER_NORMAL_IF_SPECTRUM
 
- TUNER_NOT_LOCKED
 
- TUNER_NUM_PADS
 
- TUNER_NXP_TDA18271
 
- TUNER_ONLY
 
- TUNER_PAD_AUD_OUT
 
- TUNER_PAD_OUTPUT
 
- TUNER_PAD_RF_INPUT
 
- TUNER_PANASONIC_VP27
 
- TUNER_PARAM_TYPE_DIGITAL
 
- TUNER_PARAM_TYPE_NTSC
 
- TUNER_PARAM_TYPE_PAL
 
- TUNER_PARAM_TYPE_RADIO
 
- TUNER_PARAM_TYPE_SECAM
 
- TUNER_PARTSNIC_PTI_5NF05
 
- TUNER_PHASELOCKED
 
- TUNER_PHILIPS_4IN1
 
- TUNER_PHILIPS_CU1216L
 
- TUNER_PHILIPS_FCV1236D
 
- TUNER_PHILIPS_FM1216ME_MK3
 
- TUNER_PHILIPS_FM1216MK5
 
- TUNER_PHILIPS_FM1236_MK3
 
- TUNER_PHILIPS_FM1256_IH3
 
- TUNER_PHILIPS_FMD1216MEX_MK3
 
- TUNER_PHILIPS_FMD1216ME_MK3
 
- TUNER_PHILIPS_FQ1216AME_MK4
 
- TUNER_PHILIPS_FQ1216LME_MK3
 
- TUNER_PHILIPS_FQ1216ME
 
- TUNER_PHILIPS_FQ1236A_MK4
 
- TUNER_PHILIPS_FQ1236_MK5
 
- TUNER_PHILIPS_FQ1286
 
- TUNER_PHILIPS_NTSC
 
- TUNER_PHILIPS_NTSC_M
 
- TUNER_PHILIPS_PAL
 
- TUNER_PHILIPS_PAL_DK
 
- TUNER_PHILIPS_PAL_I
 
- TUNER_PHILIPS_PAL_MK
 
- TUNER_PHILIPS_SECAM
 
- TUNER_PHILIPS_TD1316
 
- TUNER_PHILIPS_TDA8290
 
- TUNER_PHILIPS_TUV1236D
 
- TUNER_PLL_LOCKED
 
- TUNER_POR
 
- TUNER_RATIO_MASK
 
- TUNER_RATIO_SELECT_166
 
- TUNER_RATIO_SELECT_32
 
- TUNER_RATIO_SELECT_50
 
- TUNER_RATIO_SELECT_62
 
- TUNER_REGS_NUM
 
- TUNER_REG_READ
 
- TUNER_REG_WRITE
 
- TUNER_RS2000
 
- TUNER_RTL2830_MT2060
 
- TUNER_RTL2830_MXL5005S
 
- TUNER_RTL2830_QT1010
 
- TUNER_RTL2832_E4000
 
- TUNER_RTL2832_FC0012
 
- TUNER_RTL2832_FC0013
 
- TUNER_RTL2832_FC2580
 
- TUNER_RTL2832_MAX3543
 
- TUNER_RTL2832_MT2063
 
- TUNER_RTL2832_MT2266
 
- TUNER_RTL2832_MXL5007T
 
- TUNER_RTL2832_R820T
 
- TUNER_RTL2832_R828D
 
- TUNER_RTL2832_SI2157
 
- TUNER_RTL2832_TDA18272
 
- TUNER_RTL2832_TUA9001
 
- TUNER_S0194
 
- TUNER_S7395
 
- TUNER_SAMSUNG_TCPG_6121P30A
 
- TUNER_SAMSUNG_TCPN_2121P30A
 
- TUNER_SET_CONFIG
 
- TUNER_SHARP_2U5JF5540_NTSC
 
- TUNER_SIGNAL
 
- TUNER_SIGNAL_READ
 
- TUNER_SIMPLE_MAX
 
- TUNER_SLEEP
 
- TUNER_SONY_BTF_PB463Z
 
- TUNER_SONY_BTF_PG472Z
 
- TUNER_SONY_BTF_PK467Z
 
- TUNER_SONY_BTF_PXN01Z
 
- TUNER_STATUS_LOCKED
 
- TUNER_STATUS_STEREO
 
- TUNER_STEREO
 
- TUNER_STEREO_MK3
 
- TUNER_Samsung_PAL_TCPM9091PD27
 
- TUNER_TCL_2002MB
 
- TUNER_TCL_2002N
 
- TUNER_TCL_MF02GIP_5N
 
- TUNER_TDA9887
 
- TUNER_TEA5761
 
- TUNER_TEA5767
 
- TUNER_TEMIC_4006FH5_PAL
 
- TUNER_TEMIC_4006FN5_MULTI_PAL
 
- TUNER_TEMIC_4009FN5_MULTI_PAL_FM
 
- TUNER_TEMIC_4009FR5_PAL
 
- TUNER_TEMIC_4012FY5
 
- TUNER_TEMIC_4036FY5_NTSC
 
- TUNER_TEMIC_4039FR5_NTSC
 
- TUNER_TEMIC_4046FM5
 
- TUNER_TEMIC_4066FY5_PAL_I
 
- TUNER_TEMIC_4106FH5
 
- TUNER_TEMIC_4136FY5
 
- TUNER_TEMIC_NTSC
 
- TUNER_TEMIC_PAL
 
- TUNER_TEMIC_PAL_DK
 
- TUNER_TEMIC_PAL_I
 
- TUNER_TENA_9533_DI
 
- TUNER_TENA_TNF_5337
 
- TUNER_THOMSON_DTT7610
 
- TUNER_THOMSON_DTT761X
 
- TUNER_THOMSON_FE6600
 
- TUNER_TNF_5335MF
 
- TUNER_TNF_8831BGFF
 
- TUNER_TYPE_L64724
 
- TUNER_TYPE_MASK
 
- TUNER_TYPE_MB86A15
 
- TUNER_TYPE_MULTI
 
- TUNER_TYPE_NXT200x
 
- TUNER_TYPE_STV0299
 
- TUNER_TYPE_TDA10046
 
- TUNER_TYPE_UNKNOWN
 
- TUNER_UNIT
 
- TUNER_WAKE
 
- TUNER_XC2028
 
- TUNER_XC4000
 
- TUNER_XC5000
 
- TUNER_XC5000C
 
- TUNER_YMEC_TVF66T5_B_DFF
 
- TUNER_YMEC_TVF_5533MF
 
- TUNER_YMEC_TVF_8531MF
 
- TUNE_8PSK
 
- TUNE_AHASH_MAX
 
- TUNE_ATTR
 
- TUNE_ATTR_2
 
- TUNE_ATTR_3
 
- TUNE_CAP_DIV
 
- TUNE_CTRL
 
- TUNE_RSP
 
- TUNE_RX
 
- TUNE_SD18_1V7
 
- TUNE_SD18_1V8
 
- TUNE_SD18_1V9
 
- TUNE_SD18_2V0
 
- TUNE_SD18_2V7
 
- TUNE_SD18_2V8
 
- TUNE_SD18_2V9
 
- TUNE_SD18_3V3
 
- TUNE_SD18_MASK
 
- TUNE_STATUS_ERROR
 
- TUNE_STATUS_IDLE
 
- TUNE_STATUS_LOCKING
 
- TUNE_STATUS_NOT_TUNED
 
- TUNE_STATUS_SIGNAL_DVB_OK
 
- TUNE_STATUS_STREAM_DETECTED
 
- TUNE_STATUS_STREAM_TUNED
 
- TUNE_TX
 
- TUNF
 
- TUNGETDEVNETNS
 
- TUNGETFEATURES
 
- TUNGETFILTER
 
- TUNGETIFF
 
- TUNGETSNDBUF
 
- TUNGETVNETBE
 
- TUNGETVNETHDRSZ
 
- TUNGETVNETLE
 
- TUNING_CTLS_COUNT
 
- TUNING_CTL_END_NID
 
- TUNING_CTL_START_NID
 
- TUNING_DELAY
 
- TUNING_ITERATION_TO_PHASE
 
- TUNING_METHOD_SHIFT
 
- TUNING_WORD_BIT_SIZE
 
- TUNNEL_CLSS_INNER_MAC_VLAN
 
- TUNNEL_CLSS_INNER_MAC_VNI
 
- TUNNEL_CLSS_MAC_VLAN
 
- TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE
 
- TUNNEL_CLSS_MAC_VNI
 
- TUNNEL_CRIT_OPT
 
- TUNNEL_CSUM
 
- TUNNEL_DONT_FRAGMENT
 
- TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE
 
- TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1
 
- TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE
 
- TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST
 
- TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN
 
- TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6
 
- TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4
 
- TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
 
- TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1
 
- TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE
 
- TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST
 
- TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
 
- TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6
 
- TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4
 
- TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE
 
- TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1
 
- TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE
 
- TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST
 
- TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN
 
- TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6
 
- TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4
 
- TUNNEL_ENCAP_FLAG_CSUM
 
- TUNNEL_ENCAP_FLAG_CSUM6
 
- TUNNEL_ENCAP_FLAG_REMCSUM
 
- TUNNEL_ENCAP_FOU
 
- TUNNEL_ENCAP_GUE
 
- TUNNEL_ENCAP_MPLS
 
- TUNNEL_ENCAP_NONE
 
- TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE
 
- TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_GENEVE_UDP_PORT
 
- TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_VXLAN_UDP_PORT
 
- TUNNEL_ENCAP_UDP_PORT_ENTRY_LEN
 
- TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LBN
 
- TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_LEN
 
- TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_OFST
 
- TUNNEL_ENCAP_UDP_PORT_ENTRY_PROTOCOL_WIDTH
 
- TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LBN
 
- TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LEN
 
- TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_OFST
 
- TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_WIDTH
 
- TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN
 
- TUNNEL_ERSPAN_OPT
 
- TUNNEL_GENEVE_OPT
 
- TUNNEL_KEY
 
- TUNNEL_NOCACHE
 
- TUNNEL_NO_KEY
 
- TUNNEL_OAM
 
- TUNNEL_OPTIONS_PRESENT
 
- TUNNEL_PACKET
 
- TUNNEL_PROTOCOL
 
- TUNNEL_REC
 
- TUNNEL_ROUTING
 
- TUNNEL_SEQ
 
- TUNNEL_STRICT
 
- TUNNEL_UDP_CSUM
 
- TUNNEL_UDP_NO_CSUM
 
- TUNNEL_VERSION
 
- TUNNEL_VXLAN_OPT
 
- TUNN_TYPE_IPV4_GENEVE
 
- TUNN_TYPE_IPV4_GRE
 
- TUNN_TYPE_IPV6_GENEVE
 
- TUNN_TYPE_IPV6_GRE
 
- TUNN_TYPE_L2_GENEVE
 
- TUNN_TYPE_L2_GRE
 
- TUNN_TYPE_NONE
 
- TUNN_TYPE_VXLAN
 
- TUNSETCARRIER
 
- TUNSETDEBUG
 
- TUNSETFILTEREBPF
 
- TUNSETGROUP
 
- TUNSETIFF
 
- TUNSETIFINDEX
 
- TUNSETLINK
 
- TUNSETNOCSUM
 
- TUNSETOFFLOAD
 
- TUNSETOWNER
 
- TUNSETPERSIST
 
- TUNSETQUEUE
 
- TUNSETSNDBUF
 
- TUNSETSTEERINGEBPF
 
- TUNSETTXFILTER
 
- TUNSETVNETBE
 
- TUNSETVNETHDRSZ
 
- TUNSETVNETLE
 
- TUN_BW
 
- TUN_FASYNC
 
- TUN_FEATURES
 
- TUN_FLOW_EXPIRE
 
- TUN_FLT_ALLMULTI
 
- TUN_F_CSUM
 
- TUN_F_TSO4
 
- TUN_F_TSO6
 
- TUN_F_TSO_ECN
 
- TUN_F_UFO
 
- TUN_GET_F_FAIL
 
- TUN_MASK_FLOW_ENTRIES
 
- TUN_METADATA_OFFSET
 
- TUN_METADATA_OPTS
 
- TUN_MINOR
 
- TUN_MSG_PTR
 
- TUN_MSG_UBUF
 
- TUN_NUM_FLOW_ENTRIES
 
- TUN_OFFLOADS
 
- TUN_PKT_STRIP
 
- TUN_P_ETHERNET
 
- TUN_P_IPV4
 
- TUN_P_IPV6
 
- TUN_P_MPLS_UC
 
- TUN_P_NSH
 
- TUN_READQ_SIZE
 
- TUN_RFFREQ0
 
- TUN_RFFREQ1
 
- TUN_RFFREQ2
 
- TUN_RFRESTE0
 
- TUN_RFRESTE1
 
- TUN_RX_PAD
 
- TUN_TAP_DEV
 
- TUN_TUN_DEV
 
- TUN_TX_TIMESTAMP
 
- TUN_TYPE_MASK
 
- TUN_USER_FEATURES
 
- TUN_VNET_BE
 
- TUN_VNET_LE
 
- TUN_XDP_FLAG
 
- TUP
 
- TUPDATE_RXCOUNTER
 
- TUPLE_RETURN_COMMON
 
- TUPLE_RETURN_LINK
 
- TUP_EPP_TIMO
 
- TUP_RESERVED
 
- TURBOCHANNEL
 
- TURBOSPARC_BMODE
 
- TURBOSPARC_DCENABLE
 
- TURBOSPARC_ICENABLE
 
- TURBOSPARC_ICSNOOP
 
- TURBOSPARC_MMUENABLE
 
- TURBOSPARC_NOFAULT
 
- TURBOSPARC_PARITYODD
 
- TURBOSPARC_PCENABLE
 
- TURBOSPARC_PSO
 
- TURBOSPARC_SCENABLE
 
- TURBOSPARC_SNENABLE
 
- TURBOSPARC_WTENABLE
 
- TURBOSPARC_uS2
 
- TURBO_POWER_CURRENT_LIMIT
 
- TURBO_QUEUE_AREA_SIZE
 
- TURBO_QUEUE_CAP
 
- TURBO_TDC_MASK
 
- TURBO_TDC_OVR_EN
 
- TURBO_TDC_SHIFT
 
- TURBO_TDP_MASK
 
- TURBO_TDP_OVR_EN
 
- TURING_CHANNEL_GPFIFO_A
 
- TURING_DMA_COPY_A
 
- TURING_Q6SS_AHBM_AON_CLK
 
- TURING_Q6SS_AHBS_AON_CLK
 
- TURING_Q6SS_Q6_AXIM_CLK
 
- TURING_WRAPPER_AON_CLK
 
- TURING_WRAPPER_QOS_AHBS_AON_CLK
 
- TURKS_CGCG_CGLS_DEFAULT_LENGTH
 
- TURKS_CGCG_CGLS_DISABLE_LENGTH
 
- TURKS_CGCG_CGLS_ENABLE_LENGTH
 
- TURKS_GB_ADDR_CONFIG_GOLDEN
 
- TURKS_MGCGCGTSSMCTRL_DFLT
 
- TURKS_MGCG_DEFAULT_LENGTH
 
- TURKS_MGCG_DISABLE_LENGTH
 
- TURKS_MGCG_ENABLE_LENGTH
 
- TURKS_SMC_INT_VECTOR_SIZE
 
- TURKS_SMC_INT_VECTOR_START
 
- TURKS_SMC_UCODE_SIZE
 
- TURKS_SMC_UCODE_START
 
- TURKS_SYSLS_DEFAULT_LENGTH
 
- TURKS_SYSLS_DISABLE_LENGTH
 
- TURKS_SYSLS_ENABLE_LENGTH
 
- TURN_AROUND_ACK_TIMEOUT
 
- TURN_AROUND_TIMEOUT_MASK
 
- TURN_AROUND_TIMEOUT_REG
 
- TURN_OFF_SR
 
- TURN_OFF_SR_ICC_EVENT
 
- TURN_ON
 
- TURN_ON_RF
 
- TURN_ON_SR
 
- TURRIS_MOX_CPU_ID_EMMC
 
- TURRIS_MOX_CPU_ID_SD
 
- TURRIS_MOX_MAX_MODULES
 
- TURRIS_MOX_MODULE_FIRST
 
- TURRIS_MOX_MODULE_LAST
 
- TURRIS_MOX_MODULE_PCI
 
- TURRIS_MOX_MODULE_PCI_BRIDGE
 
- TURRIS_MOX_MODULE_PERIDOT
 
- TURRIS_MOX_MODULE_SFP
 
- TURRIS_MOX_MODULE_TOPAZ
 
- TURRIS_MOX_MODULE_USB3
 
- TUSB1210_VENDOR_SPECIFIC2
 
- TUSB1210_VENDOR_SPECIFIC2_DP_SHIFT
 
- TUSB1210_VENDOR_SPECIFIC2_IHSTX_SHIFT
 
- TUSB1210_VENDOR_SPECIFIC2_ZHSDRV_SHIFT
 
- TUSB6010_ASYNC_CS
 
- TUSB6010_DMACHAN
 
- TUSB6010_GPIO_ENABLE
 
- TUSB6010_GPIO_INT
 
- TUSB6010_OSCCLK_60
 
- TUSB6010_REFCLK_19
 
- TUSB6010_REFCLK_24
 
- TUSB6010_SYNC_CS
 
- TUSB_BASE_OFFSET
 
- TUSB_DEV_CONF
 
- TUSB_DEV_CONF_ID_SEL
 
- TUSB_DEV_CONF_PROD_TEST_MODE
 
- TUSB_DEV_CONF_SOFT_ID
 
- TUSB_DEV_CONF_USB_HOST_MODE
 
- TUSB_DEV_OTG_STAT
 
- TUSB_DEV_OTG_STAT_DM_ENABLE
 
- TUSB_DEV_OTG_STAT_DP_ENABLE
 
- TUSB_DEV_OTG_STAT_HOST_DISCON
 
- TUSB_DEV_OTG_STAT_ID_STATUS
 
- TUSB_DEV_OTG_STAT_LINE_STATE
 
- TUSB_DEV_OTG_STAT_PWR_CLK_GOOD
 
- TUSB_DEV_OTG_STAT_SESS_END
 
- TUSB_DEV_OTG_STAT_SESS_VALID
 
- TUSB_DEV_OTG_STAT_VBUS_SENSE
 
- TUSB_DEV_OTG_STAT_VBUS_VALID
 
- TUSB_DEV_OTG_TIMER
 
- TUSB_DEV_OTG_TIMER_ENABLE
 
- TUSB_DEV_OTG_TIMER_VAL
 
- TUSB_DIDR1_HI
 
- TUSB_DIDR1_HI_CHIP_REV
 
- TUSB_DIDR1_HI_REV_20
 
- TUSB_DIDR1_HI_REV_30
 
- TUSB_DIDR1_HI_REV_31
 
- TUSB_DIDR1_LO
 
- TUSB_DMA_CTRL_REV
 
- TUSB_DMA_EP_MAP
 
- TUSB_DMA_INT_CLEAR
 
- TUSB_DMA_INT_MASK
 
- TUSB_DMA_INT_SET
 
- TUSB_DMA_INT_SRC
 
- TUSB_DMA_REQ_CONF
 
- TUSB_DMA_REQ_CONF_BURST_SIZE
 
- TUSB_DMA_REQ_CONF_DMA_REQ_ASSER
 
- TUSB_DMA_REQ_CONF_DMA_REQ_EN
 
- TUSB_EP0_CONF
 
- TUSB_EP0_CONFIG_DIR_TX
 
- TUSB_EP0_CONFIG_SW_EN
 
- TUSB_EP0_CONFIG_XFR_SIZE
 
- TUSB_EP_CONFIG_SW_EN
 
- TUSB_EP_CONFIG_XFR_SIZE
 
- TUSB_EP_FIFO
 
- TUSB_EP_MAX_PACKET_SIZE_OFFSET
 
- TUSB_EP_RX_OFFSET
 
- TUSB_EP_TX_OFFSET
 
- TUSB_FIFO_BASE
 
- TUSB_GPIO_CONF
 
- TUSB_GPIO_CONF_DMAREQ
 
- TUSB_GPIO_INT_CLEAR
 
- TUSB_GPIO_INT_MASK
 
- TUSB_GPIO_INT_SET
 
- TUSB_GPIO_INT_SRC
 
- TUSB_GPIO_REV
 
- TUSB_INT_CTRL_CONF
 
- TUSB_INT_CTRL_CONF_INT_MODE
 
- TUSB_INT_CTRL_CONF_INT_POLARITY
 
- TUSB_INT_CTRL_CONF_INT_RELCYC
 
- TUSB_INT_CTRL_REV
 
- TUSB_INT_MASK
 
- TUSB_INT_MASK_RESERVED_13
 
- TUSB_INT_MASK_RESERVED_17
 
- TUSB_INT_MASK_RESERVED_8
 
- TUSB_INT_MASK_RESERVED_BITS
 
- TUSB_INT_SRC
 
- TUSB_INT_SRC_CLEAR
 
- TUSB_INT_SRC_DEV_READY
 
- TUSB_INT_SRC_DEV_WAKEUP
 
- TUSB_INT_SRC_ID_STATUS_CHNG
 
- TUSB_INT_SRC_OTG_TIMEOUT
 
- TUSB_INT_SRC_RESERVED_10
 
- TUSB_INT_SRC_RESERVED_18
 
- TUSB_INT_SRC_RESERVED_26
 
- TUSB_INT_SRC_RESERVED_BITS
 
- TUSB_INT_SRC_SET
 
- TUSB_INT_SRC_TXRX_DMA_DONE
 
- TUSB_INT_SRC_USB_IP_CONN
 
- TUSB_INT_SRC_USB_IP_CORE
 
- TUSB_INT_SRC_USB_IP_DISCON
 
- TUSB_INT_SRC_USB_IP_RESUME
 
- TUSB_INT_SRC_USB_IP_RST_BABBLE
 
- TUSB_INT_SRC_USB_IP_RX
 
- TUSB_INT_SRC_USB_IP_SOF
 
- TUSB_INT_SRC_USB_IP_SUSPEND
 
- TUSB_INT_SRC_USB_IP_TX
 
- TUSB_INT_SRC_USB_IP_VBUS_ERR
 
- TUSB_INT_SRC_USB_IP_VBUS_REQ
 
- TUSB_INT_SRC_VBUS_SENSE_CHNG
 
- TUSB_PHY_OTG_CTRL
 
- TUSB_PHY_OTG_CTRL_CLK_MODE
 
- TUSB_PHY_OTG_CTRL_DM_PULLDOWN
 
- TUSB_PHY_OTG_CTRL_DP_PULLDOWN
 
- TUSB_PHY_OTG_CTRL_ENABLE
 
- TUSB_PHY_OTG_CTRL_EXT_RPU
 
- TUSB_PHY_OTG_CTRL_OSC_EN
 
- TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP
 
- TUSB_PHY_OTG_CTRL_OTG_SESS_END_EN
 
- TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN
 
- TUSB_PHY_OTG_CTRL_PD
 
- TUSB_PHY_OTG_CTRL_PHYREF_CLKSEL
 
- TUSB_PHY_OTG_CTRL_PLL_ON
 
- TUSB_PHY_OTG_CTRL_PWR_GOOD
 
- TUSB_PHY_OTG_CTRL_RESET
 
- TUSB_PHY_OTG_CTRL_SUSPENDM
 
- TUSB_PHY_OTG_CTRL_TESTM0
 
- TUSB_PHY_OTG_CTRL_TESTM1
 
- TUSB_PHY_OTG_CTRL_TESTM2
 
- TUSB_PHY_OTG_CTRL_TX_DATA2
 
- TUSB_PHY_OTG_CTRL_TX_ENABLE2
 
- TUSB_PHY_OTG_CTRL_TX_GZ2
 
- TUSB_PHY_OTG_CTRL_WRPROTECT
 
- TUSB_PRCM_CONF
 
- TUSB_PRCM_CONF_SFW_CPEN
 
- TUSB_PRCM_CONF_SYS_CLKSEL
 
- TUSB_PRCM_MNGMT
 
- TUSB_PRCM_MNGMT_15_SW_EN
 
- TUSB_PRCM_MNGMT_33_SW_EN
 
- TUSB_PRCM_MNGMT_5V_CPEN
 
- TUSB_PRCM_MNGMT_DEV_IDLE
 
- TUSB_PRCM_MNGMT_DFT_CLK_DIS
 
- TUSB_PRCM_MNGMT_OTG_ID_PULLUP
 
- TUSB_PRCM_MNGMT_OTG_SESS_END_EN
 
- TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN
 
- TUSB_PRCM_MNGMT_PM_IDLE
 
- TUSB_PRCM_MNGMT_SRP_FIX_EN
 
- TUSB_PRCM_MNGMT_SRP_FIX_TIMER
 
- TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN
 
- TUSB_PRCM_MNGMT_VBUS_VALID_TIMER
 
- TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS
 
- TUSB_PRCM_REV
 
- TUSB_PRCM_WAKEUP_CLEAR
 
- TUSB_PRCM_WAKEUP_MASK
 
- TUSB_PRCM_WAKEUP_RESERVED_BITS
 
- TUSB_PRCM_WAKEUP_SOURCE
 
- TUSB_PRCM_WBUS
 
- TUSB_PRCM_WGPIO_0
 
- TUSB_PRCM_WGPIO_1
 
- TUSB_PRCM_WGPIO_2
 
- TUSB_PRCM_WGPIO_3
 
- TUSB_PRCM_WGPIO_4
 
- TUSB_PRCM_WGPIO_5
 
- TUSB_PRCM_WGPIO_6
 
- TUSB_PRCM_WGPIO_7
 
- TUSB_PRCM_WHOSTDISCON
 
- TUSB_PRCM_WID
 
- TUSB_PRCM_WNORCS
 
- TUSB_PRCM_WVBUS
 
- TUSB_PROD_TEST_RESET
 
- TUSB_PROD_TEST_RESET_VAL
 
- TUSB_PULLUP_1_CTRL
 
- TUSB_PULLUP_2_CTRL
 
- TUSB_REV_10
 
- TUSB_REV_20
 
- TUSB_REV_30
 
- TUSB_REV_31
 
- TUSB_REV_MAJOR
 
- TUSB_REV_MINOR
 
- TUSB_SCRATCH_PAD
 
- TUSB_SYS_REG_BASE
 
- TUSB_USBIP_INT_CLEAR
 
- TUSB_USBIP_INT_MASK
 
- TUSB_USBIP_INT_SET
 
- TUSB_USBIP_INT_SRC
 
- TUSB_VLYNQ_CTRL
 
- TUSB_WAIT_COUNT
 
- TUSER
 
- TUSERCOND
 
- TU_ACK_NAK_TO
 
- TU_AUDIO_MODE_CONTROL
 
- TU_BREAK
 
- TU_CNT_RST_EN
 
- TU_ETH_CQES_PER_PAGE
 
- TU_PHY_DOWN
 
- TU_SATA_TO
 
- TU_SIZE
 
- TU_SIZE_MASK
 
- TU_SIZE_RECOMMENDED
 
- TU_SIZE_SHIFT
 
- TU_STANDARD_AUTO
 
- TU_STANDARD_AUTO_CONTROL
 
- TU_STANDARD_CONTROL
 
- TU_STANDARD_MANUAL
 
- TU_STANDARD_NONE
 
- TU_STANDARD_NTSC_M
 
- TU_STANDARD_PAL_I
 
- TU_SYNCS_RECV
 
- TU_TO_EXP_TIME
 
- TU_TO_JIFFIES
 
- TU_TO_MS
 
- TU_TO_US
 
- TU_TO_USEC
 
- TV
 
- TV1OutputControl
 
- TV1_OUTPUT_CONTROL_PARAMETERS
 
- TV1_OUTPUT_CONTROL_PS_ALLOCATION
 
- TVAUDIO
 
- TVAUDIO_FM_BG_STEREO
 
- TVAUDIO_FM_K_STEREO
 
- TVAUDIO_FM_MONO
 
- TVAUDIO_FM_SAT_STEREO
 
- TVAUDIO_INPUT_EXTERN
 
- TVAUDIO_INPUT_INTERN
 
- TVAUDIO_INPUT_RADIO
 
- TVAUDIO_INPUT_TUNER
 
- TVAUDIO_NICAM_AM
 
- TVAUDIO_NICAM_FM
 
- TVAntiFlickPtrOffset
 
- TVAspect169
 
- TVAspect43
 
- TVAspect43LB
 
- TVCLKBASE_300
 
- TVCLKBASE_315
 
- TVCLK_PM_EN
 
- TVCUNIT_CLOCK_GATE_DISABLE
 
- TVC_CLK_PAD_ENABLE
 
- TVC_HALFDIV_MASK
 
- TVC_HALFDIV_SHIFT
 
- TVC_PADS_ENABLE
 
- TVDAC_A_SENSE
 
- TVDAC_A_SENSE_CTL
 
- TVDAC_B_SENSE
 
- TVDAC_B_SENSE_CTL
 
- TVDAC_C_SENSE
 
- TVDAC_C_SENSE_CTL
 
- TVDAC_SENSE_MASK
 
- TVDAC_STATE_CHG
 
- TVDAC_STATE_CHG_EN
 
- TVDataLen
 
- TVDelayPtr1Offset
 
- TVE200_BGR
 
- TVE200_CTRL
 
- TVE200_CTRL_2
 
- TVE200_CTRL_3
 
- TVE200_CTRL_4
 
- TVE200_CTRL_4_RESET
 
- TVE200_CTRL_BBBP
 
- TVE200_CTRL_BURST_0_WORDS
 
- TVE200_CTRL_BURST_128_WORDS
 
- TVE200_CTRL_BURST_16_WORDS
 
- TVE200_CTRL_BURST_256_WORDS
 
- TVE200_CTRL_BURST_32_WORDS
 
- TVE200_CTRL_BURST_4_WORDS
 
- TVE200_CTRL_BURST_64_WORDS
 
- TVE200_CTRL_BURST_8_WORDS
 
- TVE200_CTRL_CSMODE
 
- TVE200_CTRL_INTERLACE
 
- TVE200_CTRL_IPRESOL_CIF
 
- TVE200_CTRL_IPRESOL_D1
 
- TVE200_CTRL_IPRESOL_VGA
 
- TVE200_CTRL_NONINTERLACE
 
- TVE200_CTRL_NTSC
 
- TVE200_CTRL_RETRYCNT_16
 
- TVE200_CTRL_RETRYCNT_MASK
 
- TVE200_CTRL_TVCLKP
 
- TVE200_CTRL_YCBCRODR_CB0Y0CR0Y1
 
- TVE200_CTRL_YCBCRODR_CB0Y1CR0Y0
 
- TVE200_CTRL_YCBCRODR_CR0Y0CB0Y1
 
- TVE200_CTRL_YCBCRODR_CR0Y1CB0Y0
 
- TVE200_CTRL_YCBCRODR_Y0CB0Y1CR0
 
- TVE200_CTRL_YCBCRODR_Y0CR0Y1CB0
 
- TVE200_CTRL_YCBCRODR_Y1CB0Y0CR0
 
- TVE200_CTRL_YCBCRODR_Y1CR0Y0CB0
 
- TVE200_CTRL_YUV420
 
- TVE200_FIFO_UNDERRUNS
 
- TVE200_INT_BUS_ERR
 
- TVE200_INT_CLR
 
- TVE200_INT_EN
 
- TVE200_INT_STAT
 
- TVE200_INT_U_FIFO_UNDERRUN
 
- TVE200_INT_U_NEXT_FRAME
 
- TVE200_INT_V_FIFO_UNDERRUN
 
- TVE200_INT_V_NEXT_FRAME
 
- TVE200_INT_V_STATUS
 
- TVE200_INT_Y_FIFO_UNDERRUN
 
- TVE200_INT_Y_NEXT_FRAME
 
- TVE200_IPDMOD_RGB555
 
- TVE200_IPDMOD_RGB565
 
- TVE200_IPDMOD_RGB888
 
- TVE200_IPDMOD_YUV420
 
- TVE200_IPDMOD_YUV422
 
- TVE200_TVEEN
 
- TVE200_U_FRAME_BASE_ADDR
 
- TVE200_VSTSTYPE_BITS
 
- TVE200_VSTSTYPE_VAI
 
- TVE200_VSTSTYPE_VBP
 
- TVE200_VSTSTYPE_VFP
 
- TVE200_VSTSTYPE_VSYNC
 
- TVE200_V_FRAME_BASE_ADDR
 
- TVE200_Y_FRAME_BASE_ADDR
 
- TVEEPROM_AUDPROC_INTERNAL
 
- TVEEPROM_AUDPROC_MSP
 
- TVEEPROM_AUDPROC_NONE
 
- TVEEPROM_AUDPROC_OTHER
 
- TVEEPROM_TUNER_FORMAT_ALL
 
- TVENC_AUX_DIV_SHIFT
 
- TVENC_CLOCK_MULTIPLIER
 
- TVENC_MAIN_DIV_SHIFT
 
- TVEUNIT_CLOCK_GATE_DISABLE
 
- TVE_CD_CH_0_LM_EN
 
- TVE_CD_CH_0_REF_LVL
 
- TVE_CD_CH_0_SM_EN
 
- TVE_CD_CH_1_LM_EN
 
- TVE_CD_CH_1_REF_LVL
 
- TVE_CD_CH_1_SM_EN
 
- TVE_CD_CH_2_LM_EN
 
- TVE_CD_CH_2_REF_LVL
 
- TVE_CD_CH_2_SM_EN
 
- TVE_CD_CONT_REG
 
- TVE_CD_EN
 
- TVE_CD_LM_IEN
 
- TVE_CD_MON_END_IEN
 
- TVE_CD_SM_IEN
 
- TVE_COM_CONF_REG
 
- TVE_DAC_DIV2_RATE
 
- TVE_DAC_DIV4_RATE
 
- TVE_DAC_FULL_RATE
 
- TVE_DAC_SAMP_RATE_MASK
 
- TVE_DAC_SAMP_RATE_OFS
 
- TVE_DAC_SAMP_RATE_WIDTH
 
- TVE_DATA_SOURCE_BUS1
 
- TVE_DATA_SOURCE_BUS2
 
- TVE_DATA_SOURCE_EXT
 
- TVE_DATA_SOURCE_MASK
 
- TVE_DATA_SOURCE_TESTGEN
 
- TVE_EN
 
- TVE_FRAME_END_IEN
 
- TVE_INP_VIDEO_FORM
 
- TVE_INP_YCBCR_422
 
- TVE_INP_YCBCR_444
 
- TVE_INT_CONT_REG
 
- TVE_IPU_CLK_EN
 
- TVE_IPU_CLK_EN_OFS
 
- TVE_MODE_TVOUT
 
- TVE_MODE_VGA
 
- TVE_MV_CONT_REG
 
- TVE_P2I_CONV_EN
 
- TVE_STAT_REG
 
- TVE_SYNC_CH_0_EN
 
- TVE_SYNC_CH_1_EN
 
- TVE_SYNC_CH_2_EN
 
- TVE_TST_MODE_REG
 
- TVE_TVDAC0_CONT_REG
 
- TVE_TVDAC1_CONT_REG
 
- TVE_TVDAC2_CONT_REG
 
- TVE_TVDAC_GAIN_MASK
 
- TVE_TVDAC_TEST_MODE_MASK
 
- TVE_TV_OUT_CVBS_0
 
- TVE_TV_OUT_CVBS_0_2
 
- TVE_TV_OUT_CVBS_2
 
- TVE_TV_OUT_DISABLE
 
- TVE_TV_OUT_MODE_MASK
 
- TVE_TV_OUT_RGB
 
- TVE_TV_OUT_SVIDEO_0_1
 
- TVE_TV_OUT_SVIDEO_0_1_CVBS2_2
 
- TVE_TV_OUT_YPBPR
 
- TVE_TV_STAND_HD_1080P30
 
- TVE_TV_STAND_MASK
 
- TVEdgePtr1Offset
 
- TVEncoderControl
 
- TVFUNIT_CLOCK_GATE_DISABLE
 
- TVG_COL1_BLUE
 
- TVG_COL1_GREEN
 
- TVG_COL1_RED
 
- TVG_COL2_BLUE
 
- TVG_COL2_GREEN
 
- TVG_COL2_RED
 
- TVG_COLOR1
 
- TVG_COLOR1_BIS
 
- TVG_COLOR2
 
- TVG_COLOR2_BIS
 
- TVG_CTL
 
- TVG_IMG_SIZE
 
- TVG_LINE_SIZE
 
- TVG_MODE_HSTRIPES
 
- TVG_MODE_MASK
 
- TVG_MODE_SINGLE_COLOR
 
- TVG_MODE_VSTRIPES
 
- TVG_NBLINES
 
- TVG_RUN
 
- TVG_SEL
 
- TVG_STOPMODE_EOF
 
- TVG_STOPMODE_EOL
 
- TVG_STOPMODE_MASK
 
- TVG_STOPMODE_NOW
 
- TVG_STRIPE_SIZE
 
- TVG_STS
 
- TVG_STS_CLR
 
- TVG_STS_CTL
 
- TVG_STS_FLAG
 
- TVG_STS_RUNNING
 
- TVIDA
 
- TVIDEO_DIP_CTL
 
- TVIDEO_DIP_DATA
 
- TVIDEO_DIP_GCP
 
- TVMEMSIZE
 
- TVMode
 
- TVNORMS
 
- TVODA
 
- TVO_AUX_IN_VID_FORMAT
 
- TVO_CNTL
 
- TVO_CSC_AUX_M0
 
- TVO_CSC_AUX_M1
 
- TVO_CSC_AUX_M2
 
- TVO_CSC_AUX_M3
 
- TVO_CSC_AUX_M4
 
- TVO_CSC_AUX_M5
 
- TVO_CSC_AUX_M6
 
- TVO_CSC_AUX_M7
 
- TVO_CSC_MAIN_M0
 
- TVO_CSC_MAIN_M1
 
- TVO_CSC_MAIN_M2
 
- TVO_CSC_MAIN_M3
 
- TVO_CSC_MAIN_M4
 
- TVO_CSC_MAIN_M5
 
- TVO_CSC_MAIN_M6
 
- TVO_CSC_MAIN_M7
 
- TVO_DVO_CONFIG
 
- TVO_DVO_SYNC_SEL
 
- TVO_HDMI_CLIP_VALUE_B_CB
 
- TVO_HDMI_CLIP_VALUE_R_CR
 
- TVO_HDMI_CLIP_VALUE_Y_G
 
- TVO_HDMI_DFV_OBS
 
- TVO_HDMI_FORCE_COLOR_0
 
- TVO_HDMI_FORCE_COLOR_1
 
- TVO_HDMI_SYNC_SEL
 
- TVO_HD_DAC_CFG_OFF
 
- TVO_HD_SYNC_SEL
 
- TVO_IN_FMT_SIGNED
 
- TVO_MAIN_IN_VID_FORMAT
 
- TVO_MIN_HD_HEIGHT
 
- TVO_SYNC_AUX_VTG_SET_REF
 
- TVO_SYNC_DVO_PAD_HSYNC_SHIFT
 
- TVO_SYNC_DVO_PAD_VSYNC_SHIFT
 
- TVO_SYNC_EXT
 
- TVO_SYNC_HD_DCS_SHIFT
 
- TVO_SYNC_MAIN_VTG_SET_REF
 
- TVO_VIP_CLIP_DISABLED
 
- TVO_VIP_CLIP_EAV_SAV
 
- TVO_VIP_CLIP_LIMITED_RANGE_CB_CR
 
- TVO_VIP_CLIP_LIMITED_RANGE_RGB_Y
 
- TVO_VIP_CLIP_MASK
 
- TVO_VIP_CLIP_PROG_RANGE
 
- TVO_VIP_CLIP_SHIFT
 
- TVO_VIP_DVO
 
- TVO_VIP_HDF
 
- TVO_VIP_HDMI
 
- TVO_VIP_REORDER_B_SHIFT
 
- TVO_VIP_REORDER_CB_B_SEL
 
- TVO_VIP_REORDER_CR_R_SEL
 
- TVO_VIP_REORDER_G_SHIFT
 
- TVO_VIP_REORDER_MASK
 
- TVO_VIP_REORDER_R_SHIFT
 
- TVO_VIP_REORDER_Y_G_SEL
 
- TVO_VIP_RND_10BIT_ROUNDED
 
- TVO_VIP_RND_12BIT_ROUNDED
 
- TVO_VIP_RND_8BIT_ROUNDED
 
- TVO_VIP_RND_MASK
 
- TVO_VIP_RND_SHIFT
 
- TVO_VIP_SEL_INPUT_AUX
 
- TVO_VIP_SEL_INPUT_BYPASSED
 
- TVO_VIP_SEL_INPUT_BYPASS_MASK
 
- TVO_VIP_SEL_INPUT_FORCE_COLOR
 
- TVO_VIP_SEL_INPUT_MAIN
 
- TVO_VIP_SEL_INPUT_MASK
 
- TVOverScan
 
- TVOverScanShift
 
- TVP
 
- TVP3026A_XLATCHCTRL_4_3
 
- TVP3026A_XLATCHCTRL_8_3
 
- TVP3026B_XLATCHCTRL_4_3
 
- TVP3026B_XLATCHCTRL_8_3
 
- TVP3026_CLCOLOR0
 
- TVP3026_CLCOLOR1
 
- TVP3026_CLCOLOR2
 
- TVP3026_CLK_SEL
 
- TVP3026_CLOVERSCAN
 
- TVP3026_COL_PAL
 
- TVP3026_CRC_CTL
 
- TVP3026_CRC_LSB
 
- TVP3026_CRC_MSB
 
- TVP3026_CURCOLDATA
 
- TVP3026_CURCOLRDADD
 
- TVP3026_CURCOLWRADD
 
- TVP3026_CURCTRL
 
- TVP3026_CURPOSXH
 
- TVP3026_CURPOSXL
 
- TVP3026_CURPOSYH
 
- TVP3026_CURPOSYL
 
- TVP3026_CURRAMDATA
 
- TVP3026_CURSOR_CTL
 
- TVP3026_CUR_COL_ADDR
 
- TVP3026_CUR_COL_DATA
 
- TVP3026_CUR_RAM
 
- TVP3026_CUR_XHI
 
- TVP3026_CUR_XLOW
 
- TVP3026_CUR_YHI
 
- TVP3026_CUR_YLOW
 
- TVP3026_DATA
 
- TVP3026_GEN_CTL
 
- TVP3026_GEN_IO_CTL
 
- TVP3026_GEN_IO_DATA
 
- TVP3026_ID
 
- TVP3026_INDEX
 
- TVP3026_KEY_BLUE_HI
 
- TVP3026_KEY_BLUE_LOW
 
- TVP3026_KEY_CTL
 
- TVP3026_KEY_GREEN_HI
 
- TVP3026_KEY_GREEN_LOW
 
- TVP3026_KEY_RED_HI
 
- TVP3026_KEY_RED_LOW
 
- TVP3026_LATCH_CTL
 
- TVP3026_LOAD_CLK_DATA
 
- TVP3026_MCLK_CTL
 
- TVP3026_MEM_CLK_DATA
 
- TVP3026_MISC_CTL
 
- TVP3026_MUX_CTL
 
- TVP3026_PALDATA
 
- TVP3026_PALRDADD
 
- TVP3026_PALWRADD
 
- TVP3026_PAL_PAGE
 
- TVP3026_PIXRDMSK
 
- TVP3026_PIX_CLK_DATA
 
- TVP3026_PIX_RD_MSK
 
- TVP3026_PLL_ADDR
 
- TVP3026_RADR_PAL
 
- TVP3026_RESET
 
- TVP3026_SENSE_TEST
 
- TVP3026_SILICON_REV
 
- TVP3026_TEST_DATA
 
- TVP3026_TRUE_COLOR_CTL
 
- TVP3026_WADR_PAL
 
- TVP3026_XCLKCTRL
 
- TVP3026_XCLKCTRL_CLKSTOPPED
 
- TVP3026_XCLKCTRL_DIV1
 
- TVP3026_XCLKCTRL_DIV16
 
- TVP3026_XCLKCTRL_DIV2
 
- TVP3026_XCLKCTRL_DIV32
 
- TVP3026_XCLKCTRL_DIV4
 
- TVP3026_XCLKCTRL_DIV64
 
- TVP3026_XCLKCTRL_DIV8
 
- TVP3026_XCLKCTRL_SRC_CLK0
 
- TVP3026_XCLKCTRL_SRC_CLK0VGA
 
- TVP3026_XCLKCTRL_SRC_CLK1
 
- TVP3026_XCLKCTRL_SRC_CLK2
 
- TVP3026_XCLKCTRL_SRC_DIS
 
- TVP3026_XCLKCTRL_SRC_ECLK2
 
- TVP3026_XCLKCTRL_SRC_NCLK2
 
- TVP3026_XCLKCTRL_SRC_PLL
 
- TVP3026_XCOLKEYBLUEMAX
 
- TVP3026_XCOLKEYBLUEMIN
 
- TVP3026_XCOLKEYCTRL
 
- TVP3026_XCOLKEYCTRL_BLUE_EN
 
- TVP3026_XCOLKEYCTRL_GREEN_EN
 
- TVP3026_XCOLKEYCTRL_NEGATE
 
- TVP3026_XCOLKEYCTRL_OVR_EN
 
- TVP3026_XCOLKEYCTRL_RED_EN
 
- TVP3026_XCOLKEYCTRL_ZOOM1
 
- TVP3026_XCOLKEYCTRL_ZOOM16
 
- TVP3026_XCOLKEYCTRL_ZOOM2
 
- TVP3026_XCOLKEYCTRL_ZOOM32
 
- TVP3026_XCOLKEYCTRL_ZOOM4
 
- TVP3026_XCOLKEYCTRL_ZOOM8
 
- TVP3026_XCOLKEYGREENMAX
 
- TVP3026_XCOLKEYGREENMIN
 
- TVP3026_XCOLKEYOVRMAX
 
- TVP3026_XCOLKEYOVRMIN
 
- TVP3026_XCOLKEYREDMAX
 
- TVP3026_XCOLKEYREDMIN
 
- TVP3026_XCRCBITSEL
 
- TVP3026_XCRCREMH
 
- TVP3026_XCRCREML
 
- TVP3026_XCURCTRL
 
- TVP3026_XCURCTRL_3COLOR
 
- TVP3026_XCURCTRL_BLANK2048
 
- TVP3026_XCURCTRL_BLANK4096
 
- TVP3026_XCURCTRL_DIRECT
 
- TVP3026_XCURCTRL_DIS
 
- TVP3026_XCURCTRL_EVEN
 
- TVP3026_XCURCTRL_INDIRECT
 
- TVP3026_XCURCTRL_INTERLACED
 
- TVP3026_XCURCTRL_ODD
 
- TVP3026_XCURCTRL_XGA
 
- TVP3026_XCURCTRL_XWIN
 
- TVP3026_XGENCTRL
 
- TVP3026_XGENCTRL_BIG_ENDIAN
 
- TVP3026_XGENCTRL_BLACK_0IRE
 
- TVP3026_XGENCTRL_BLACK_75IRE
 
- TVP3026_XGENCTRL_HSYNC_NEG
 
- TVP3026_XGENCTRL_HSYNC_POS
 
- TVP3026_XGENCTRL_LITTLE_ENDIAN
 
- TVP3026_XGENCTRL_NO_SYNC_ON_GREEN
 
- TVP3026_XGENCTRL_OVERSCAN_DIS
 
- TVP3026_XGENCTRL_OVERSCAN_EN
 
- TVP3026_XGENCTRL_SYNC_ON_GREEN
 
- TVP3026_XGENCTRL_VSYNC_NEG
 
- TVP3026_XGENCTRL_VSYNC_POS
 
- TVP3026_XGENIOCTRL
 
- TVP3026_XGENIODATA
 
- TVP3026_XID
 
- TVP3026_XLATCHCTRL
 
- TVP3026_XLATCHCTRL_16_1
 
- TVP3026_XLATCHCTRL_1_1
 
- TVP3026_XLATCHCTRL_2_1
 
- TVP3026_XLATCHCTRL_4_1
 
- TVP3026_XLATCHCTRL_8_1
 
- TVP3026_XLOOPPLLDATA
 
- TVP3026_XMEMPLLCTRL
 
- TVP3026_XMEMPLLCTRL_DIV
 
- TVP3026_XMEMPLLCTRL_MCLK_DOTCLOCK
 
- TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL
 
- TVP3026_XMEMPLLCTRL_RCLK_DOTDIVN
 
- TVP3026_XMEMPLLCTRL_RCLK_LOOPPLL
 
- TVP3026_XMEMPLLCTRL_RCLK_PIXPLL
 
- TVP3026_XMEMPLLCTRL_STROBEMKC4
 
- TVP3026_XMEMPLLDATA
 
- TVP3026_XMISCCTRL
 
- TVP3026_XMISCCTRL_DAC_6BIT
 
- TVP3026_XMISCCTRL_DAC_8BIT
 
- TVP3026_XMISCCTRL_DAC_EXT
 
- TVP3026_XMISCCTRL_DAC_PDOWN
 
- TVP3026_XMISCCTRL_DAC_PUP
 
- TVP3026_XMISCCTRL_PSEL_DIS
 
- TVP3026_XMISCCTRL_PSEL_EN
 
- TVP3026_XMISCCTRL_PSEL_HIGH
 
- TVP3026_XMISCCTRL_PSEL_LOW
 
- TVP3026_XMUXCTRL
 
- TVP3026_XMUXCTRL_MEMORY_16BIT
 
- TVP3026_XMUXCTRL_MEMORY_32BIT
 
- TVP3026_XMUXCTRL_MEMORY_64BIT
 
- TVP3026_XMUXCTRL_MEMORY_8BIT
 
- TVP3026_XMUXCTRL_PIXEL_16BIT
 
- TVP3026_XMUXCTRL_PIXEL_32BIT
 
- TVP3026_XMUXCTRL_PIXEL_4BIT
 
- TVP3026_XMUXCTRL_PIXEL_4BIT_SWAPPED
 
- TVP3026_XMUXCTRL_PIXEL_8BIT
 
- TVP3026_XMUXCTRL_VGA
 
- TVP3026_XPALETTEPAGE
 
- TVP3026_XPIXPLLDATA
 
- TVP3026_XPLLADDR
 
- TVP3026_XPLLADDR_X
 
- TVP3026_XPLLDATA_M
 
- TVP3026_XPLLDATA_N
 
- TVP3026_XPLLDATA_P
 
- TVP3026_XPLLDATA_STAT
 
- TVP3026_XSENSETEST
 
- TVP3026_XSILICONREV
 
- TVP3026_XTESTMODEDATA
 
- TVP3026_XTRUECOLORCTRL
 
- TVP3026_XTRUECOLORCTRL_24_ALTERNATE
 
- TVP3026_XTRUECOLORCTRL_BGRO_8888
 
- TVP3026_XTRUECOLORCTRL_BGR_888
 
- TVP3026_XTRUECOLORCTRL_DIRECTCOLOR
 
- TVP3026_XTRUECOLORCTRL_ORGB_1555
 
- TVP3026_XTRUECOLORCTRL_ORGB_8888
 
- TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR
 
- TVP3026_XTRUECOLORCTRL_RGBO_4444
 
- TVP3026_XTRUECOLORCTRL_RGB_565
 
- TVP3026_XTRUECOLORCTRL_RGB_664
 
- TVP3026_XTRUECOLORCTRL_RGB_888
 
- TVP3026_XTRUECOLORCTRL_TRUECOLOR
 
- TVP3026_XTRUECOLORCTRL_VRAM_SHIFT_ACCEL
 
- TVP3026_XTRUECOLORCTRL_VRAM_SHIFT_TVP
 
- TVP3026_X_DATAREG
 
- TVP5146_CHIP_ID_LSB
 
- TVP5147_CH0
 
- TVP5147_CH1
 
- TVP5147_CHIP_ID_LSB
 
- TVP5147_INPUT
 
- TVP514X_CHIP_ID_MSB
 
- TVP514X_MODULE_NAME
 
- TVP514X_STD_ALL
 
- TVP514X_XCLK_BT656
 
- TVP5150_ACT_VD_CROP_STP_LSB
 
- TVP5150_ACT_VD_CROP_STP_MSB
 
- TVP5150_ACT_VD_CROP_ST_LSB
 
- TVP5150_ACT_VD_CROP_ST_MSB
 
- TVP5150_ANAL_CHL_CTL
 
- TVP5150_AUTOSW_MSK
 
- TVP5150_BLACK_SCREEN
 
- TVP5150_BRIGHT_CTL
 
- TVP5150_CB_GAIN_FACT
 
- TVP5150_CC_DATA_END
 
- TVP5150_CC_DATA_INI
 
- TVP5150_CHROMA_PROC_CTL_1
 
- TVP5150_CHROMA_PROC_CTL_2
 
- TVP5150_COLORSPACE
 
- TVP5150_COLOR_KIL_THSH_CTL
 
- TVP5150_COMPOSITE0
 
- TVP5150_COMPOSITE1
 
- TVP5150_CONF_RAM_ADDR_HIGH
 
- TVP5150_CONF_RAM_ADDR_LOW
 
- TVP5150_CONF_SHARED_PIN
 
- TVP5150_CONTRAST_CTL
 
- TVP5150_CROP_SHIFT
 
- TVP5150_CR_GAIN_FACTOR
 
- TVP5150_DATA_RATE_SEL
 
- TVP5150_FIELD
 
- TVP5150_FIFO_INT_THRESHOLD
 
- TVP5150_FIFO_OUT_CTRL
 
- TVP5150_FIFO_RESET
 
- TVP5150_FIFO_WORD_COUNT
 
- TVP5150_FULL_FIELD_ENA
 
- TVP5150_FULL_FIELD_MODE_REG
 
- TVP5150_GENLOCK
 
- TVP5150_HORIZ_SYNC_START
 
- TVP5150_HUE_CTL
 
- TVP5150_H_MAX
 
- TVP5150_INPUT_NUM
 
- TVP5150_INTT_CONFIG_REG_B
 
- TVP5150_INT_ACTIVE_REG_B
 
- TVP5150_INT_A_LOCK
 
- TVP5150_INT_A_LOCK_STATUS
 
- TVP5150_INT_CONF
 
- TVP5150_INT_ENABLE_REG_A
 
- TVP5150_INT_ENABLE_REG_B
 
- TVP5150_INT_RESET_REG_B
 
- TVP5150_INT_STATUS_REG_A
 
- TVP5150_INT_STATUS_REG_B
 
- TVP5150_LINE_MODE_END
 
- TVP5150_LINE_MODE_INI
 
- TVP5150_LINE_NUMBER_INT
 
- TVP5150_LSB_DEV_ID
 
- TVP5150_LUMA_PROC_CTL_1
 
- TVP5150_LUMA_PROC_CTL_2
 
- TVP5150_LUMA_PROC_CTL_3
 
- TVP5150_MACROVISION_OFF_CTR
 
- TVP5150_MACROVISION_ON_CTR
 
- TVP5150_MAX_CROP_LEFT
 
- TVP5150_MAX_CROP_TOP
 
- TVP5150_MBUS_FMT
 
- TVP5150_MISC_CTL
 
- TVP5150_MISC_CTL_CLOCK_OE
 
- TVP5150_MISC_CTL_GPCL
 
- TVP5150_MISC_CTL_HVLK
 
- TVP5150_MISC_CTL_INTREQ_OE
 
- TVP5150_MISC_CTL_SYNC_OE
 
- TVP5150_MISC_CTL_VBLANK
 
- TVP5150_MISC_CTL_VBLK_GPCL
 
- TVP5150_MISC_CTL_YCBCR_OE
 
- TVP5150_MSB_DEV_ID
 
- TVP5150_NORMAL
 
- TVP5150_NUM_PADS
 
- TVP5150_OP_MODE_CTL
 
- TVP5150_PAD_IF_INPUT
 
- TVP5150_PAD_VID_OUT
 
- TVP5150_PIX_ALIGN_REG_HIGH
 
- TVP5150_PIX_ALIGN_REG_LOW
 
- TVP5150_PWDN
 
- TVP5150_REV_SELECT
 
- TVP5150_ROM_MAJOR_VER
 
- TVP5150_ROM_MINOR_VER
 
- TVP5150_RSTN
 
- TVP5150_SATURATION_CTL
 
- TVP5150_STATUS_REG_1
 
- TVP5150_STATUS_REG_2
 
- TVP5150_STATUS_REG_3
 
- TVP5150_STATUS_REG_4
 
- TVP5150_STATUS_REG_5
 
- TVP5150_SVIDEO
 
- TVP5150_TELETEXT_FIL1_END
 
- TVP5150_TELETEXT_FIL1_INI
 
- TVP5150_TELETEXT_FIL2_END
 
- TVP5150_TELETEXT_FIL2_INI
 
- TVP5150_TELETEXT_FIL_ENA
 
- TVP5150_VBI_FIFO_READ_DATA
 
- TVP5150_VDPOE
 
- TVP5150_VDP_CONF_RAM_DATA
 
- TVP5150_VDP_STATUS_REG
 
- TVP5150_VD_IN_SRC_SEL_1
 
- TVP5150_VERT_BLANKING_START
 
- TVP5150_VERT_BLANKING_STOP
 
- TVP5150_VERT_LN_COUNT_LSB
 
- TVP5150_VERT_LN_COUNT_MSB
 
- TVP5150_VIDEO_STD
 
- TVP5150_VITC_DATA_END
 
- TVP5150_VITC_DATA_INI
 
- TVP5150_VPS_DATA_END
 
- TVP5150_VPS_DATA_INI
 
- TVP5150_V_MAX_525_60
 
- TVP5150_V_MAX_OTHERS
 
- TVP5150_WSS_DATA_END
 
- TVP5150_WSS_DATA_INI
 
- TVP7002_ADC_SETUP
 
- TVP7002_ALC_PLACEMENT
 
- TVP7002_AUTO_LVL_CTL_ENABLE
 
- TVP7002_AUTO_LVL_CTL_FILTER
 
- TVP7002_AVID_START_PIXEL_LSBS
 
- TVP7002_AVID_START_PIXEL_MSBS
 
- TVP7002_AVID_STOP_PIXEL_LSBS
 
- TVP7002_AVID_STOP_PIXEL_MSBS
 
- TVP7002_B_AND_G_COARSE_GAIN
 
- TVP7002_B_COARSE_OFF
 
- TVP7002_B_DGTL_ALC_OUT_LSBS
 
- TVP7002_B_FINE_GAIN
 
- TVP7002_B_FINE_OFF_MSBS
 
- TVP7002_CHIP_REV
 
- TVP7002_CLAMP_START
 
- TVP7002_CLAMP_W
 
- TVP7002_CLK_L_STAT_LSBS
 
- TVP7002_CLK_L_STAT_MSBS
 
- TVP7002_CL_MASK
 
- TVP7002_CL_SHIFT
 
- TVP7002_COARSE_CLAMP_CTL
 
- TVP7002_DGTL_ALC_OUT_MSBS
 
- TVP7002_EOR
 
- TVP7002_FBIT_F_0_START_L_OFF
 
- TVP7002_FBIT_F_1_START_L_OFF
 
- TVP7002_FINE_CLAMP_CTL
 
- TVP7002_FINE_OFF_LSBS
 
- TVP7002_G_COARSE_OFF
 
- TVP7002_G_DGTL_ALC_OUT_LSBS
 
- TVP7002_G_FINE_GAIN
 
- TVP7002_G_FINE_OFF_MSBS
 
- TVP7002_HPLL_AND_CLAMP_CTL
 
- TVP7002_HPLL_CRTL
 
- TVP7002_HPLL_FDBK_DIV_LSBS
 
- TVP7002_HPLL_FDBK_DIV_MSBS
 
- TVP7002_HPLL_PHASE_SEL
 
- TVP7002_HPLL_POST_COAST
 
- TVP7002_HPLL_PRE_COAST
 
- TVP7002_HSOUT_OUT_START
 
- TVP7002_HSYNC_OUT_W
 
- TVP7002_HSYNC_W
 
- TVP7002_INPR_MASK
 
- TVP7002_INPUT
 
- TVP7002_IN_MUX_SEL_1
 
- TVP7002_IN_MUX_SEL_2
 
- TVP7002_IP_SHIFT
 
- TVP7002_L_FRAME_STAT_LSBS
 
- TVP7002_L_FRAME_STAT_MSBS
 
- TVP7002_L_LENGTH_TOL
 
- TVP7002_MISC_CTL_1
 
- TVP7002_MISC_CTL_2
 
- TVP7002_MISC_CTL_3
 
- TVP7002_MISC_CTL_4
 
- TVP7002_MODULE_NAME
 
- TVP7002_MVIS_STRIPPER_W
 
- TVP7002_OUT_FORMATTER
 
- TVP7002_PWR_CTL
 
- TVP7002_READ
 
- TVP7002_RESERVED
 
- TVP7002_RGB_COARSE_CLAMP_CTL
 
- TVP7002_R_COARSE_GAIN
 
- TVP7002_R_COARSE_OFF
 
- TVP7002_R_DGTL_ALC_OUT_LSBS
 
- TVP7002_R_FINE_GAIN
 
- TVP7002_R_FINE_OFF_MSBS
 
- TVP7002_SOG_CLAMP
 
- TVP7002_SOG_COARSE_CLAMP_CTL
 
- TVP7002_SYNC_BYPASS
 
- TVP7002_SYNC_CTL_1
 
- TVP7002_SYNC_DETECT_STAT
 
- TVP7002_SYNC_ON_G_THRS
 
- TVP7002_SYNC_SEPARATOR_THRS
 
- TVP7002_VBLK_F_0_DURATION
 
- TVP7002_VBLK_F_0_START_L_OFF
 
- TVP7002_VBLK_F_1_DURATION
 
- TVP7002_VBLK_F_1_START_L_OFF
 
- TVP7002_VIDEO_BWTH_CTL
 
- TVP7002_VSYNC_ALGN
 
- TVP7002_VSYNC_W
 
- TVP7002_WRITE
 
- TVP7002_YUV_U_B_COEF_LSBS
 
- TVP7002_YUV_U_B_COEF_MSBS
 
- TVP7002_YUV_U_G_COEF_LSBS
 
- TVP7002_YUV_U_G_COEF_MSBS
 
- TVP7002_YUV_U_R_COEF_LSBS
 
- TVP7002_YUV_U_R_COEF_MSBS
 
- TVP7002_YUV_V_B_COEF_LSBS
 
- TVP7002_YUV_V_B_COEF_MSBS
 
- TVP7002_YUV_V_G_COEF_LSBS
 
- TVP7002_YUV_V_G_COEF_MSBS
 
- TVP7002_YUV_V_R_COEF_LSBS
 
- TVP7002_YUV_V_R_COEF_MSBS
 
- TVP7002_YUV_Y_B_COEF_LSBS
 
- TVP7002_YUV_Y_B_COEF_MSBS
 
- TVP7002_YUV_Y_G_COEF_LSBS
 
- TVP7002_YUV_Y_G_COEF_MSBS
 
- TVP7002_YUV_Y_R_COEF_LSBS
 
- TVP7002_YUV_Y_R_COEF_MSBS
 
- TVPADDRW
 
- TVPCADRR
 
- TVPCADRW
 
- TVPCDATA
 
- TVPCRDAT
 
- TVPCXPOH
 
- TVPCXPOL
 
- TVPCYPOH
 
- TVPCYPOL
 
- TVPDCCTL
 
- TVPIDATA
 
- TVPIRBRC
 
- TVPIRCBH
 
- TVPIRCBL
 
- TVPIRCGH
 
- TVPIRCGL
 
- TVPIRCKC
 
- TVPIRCKH
 
- TVPIRCKL
 
- TVPIRCLS
 
- TVPIRCRH
 
- TVPIRCRL
 
- TVPIRDID
 
- TVPIRGEC
 
- TVPIRICC
 
- TVPIRLAC
 
- TVPIRLPD
 
- TVPIRMIC
 
- TVPIRMLC
 
- TVPIRMPD
 
- TVPIRMXC
 
- TVPIRPLA
 
- TVPIRPPD
 
- TVPIRPPG
 
- TVPIRRES
 
- TVPIRREV
 
- TVPIRRML
 
- TVPIRRMM
 
- TVPIRRMS
 
- TVPIRSEN
 
- TVPIRTCC
 
- TVPIRTMD
 
- TVPLL_TURNOFF
 
- TVPPADRR
 
- TVPPDATA
 
- TVPPMASK
 
- TVPhaseIncrPtr1Offset
 
- TVRPLLDIV2XO
 
- TVRUNIT_CLOCK_GATE_DISABLE
 
- TVSO
 
- TVSYNC_IRQ
 
- TVSYNC_IRQ_ENA
 
- TVSYNC_IRQ_ENA_MASK
 
- TVSYNC_IRQ_MASK
 
- TVSet525p1024
 
- TVSetCHOverScan
 
- TVSetHiVision
 
- TVSetNTSC1024
 
- TVSetNTSCJ
 
- TVSetPAL
 
- TVSetPALM
 
- TVSetPALN
 
- TVSetTVSimuMode
 
- TVSetYPbPr525i
 
- TVSetYPbPr525p
 
- TVSetYPbPr750p
 
- TVVCLK
 
- TVVCLKDIV2
 
- TVX_DATA_FORMAT
 
- TVX_DST_SEL
 
- TVX_DstSel_0f
 
- TVX_DstSel_1f
 
- TVX_DstSel_Mask
 
- TVX_DstSel_RESERVED_6
 
- TVX_DstSel_W
 
- TVX_DstSel_X
 
- TVX_DstSel_Y
 
- TVX_DstSel_Z
 
- TVX_ENDIAN_SWAP
 
- TVX_EndianSwap_8in16
 
- TVX_EndianSwap_8in32
 
- TVX_EndianSwap_8in64
 
- TVX_EndianSwap_None
 
- TVX_FMT_1
 
- TVX_FMT_10_10_10_2
 
- TVX_FMT_10_11_11
 
- TVX_FMT_10_11_11_FLOAT
 
- TVX_FMT_11_11_10
 
- TVX_FMT_11_11_10_FLOAT
 
- TVX_FMT_16
 
- TVX_FMT_16_16
 
- TVX_FMT_16_16_16
 
- TVX_FMT_16_16_16_16
 
- TVX_FMT_16_16_16_16_FLOAT
 
- TVX_FMT_16_16_16_FLOAT
 
- TVX_FMT_16_16_FLOAT
 
- TVX_FMT_16_FLOAT
 
- TVX_FMT_1_5_5_5
 
- TVX_FMT_1_REVERSED
 
- TVX_FMT_24_8
 
- TVX_FMT_24_8_FLOAT
 
- TVX_FMT_2_10_10_10
 
- TVX_FMT_32
 
- TVX_FMT_32_32
 
- TVX_FMT_32_32_32
 
- TVX_FMT_32_32_32_32
 
- TVX_FMT_32_32_32_32_FLOAT
 
- TVX_FMT_32_32_32_FLOAT
 
- TVX_FMT_32_32_FLOAT
 
- TVX_FMT_32_AS_8
 
- TVX_FMT_32_AS_8_8
 
- TVX_FMT_32_FLOAT
 
- TVX_FMT_3_3_2
 
- TVX_FMT_4_4
 
- TVX_FMT_4_4_4_4
 
- TVX_FMT_5_5_5_1
 
- TVX_FMT_5_6_5
 
- TVX_FMT_5_9_9_9_SHAREDEXP
 
- TVX_FMT_6_5_5
 
- TVX_FMT_8
 
- TVX_FMT_8_24
 
- TVX_FMT_8_24_FLOAT
 
- TVX_FMT_8_8
 
- TVX_FMT_8_8_8
 
- TVX_FMT_8_8_8_8
 
- TVX_FMT_APC0
 
- TVX_FMT_APC1
 
- TVX_FMT_APC2
 
- TVX_FMT_APC3
 
- TVX_FMT_APC4
 
- TVX_FMT_APC5
 
- TVX_FMT_APC6
 
- TVX_FMT_APC7
 
- TVX_FMT_BC1
 
- TVX_FMT_BC2
 
- TVX_FMT_BC3
 
- TVX_FMT_BC4
 
- TVX_FMT_BC5
 
- TVX_FMT_BG_RG
 
- TVX_FMT_CTX1
 
- TVX_FMT_GB_GR
 
- TVX_FMT_INVALID
 
- TVX_FMT_RESERVED_33
 
- TVX_FMT_RESERVED_36
 
- TVX_FMT_RESERVED_4
 
- TVX_FMT_RESERVED_63
 
- TVX_FMT_X24_8_32_FLOAT
 
- TVX_INST
 
- TVX_Inst_Gather4
 
- TVX_Inst_Gather4_C
 
- TVX_Inst_Gather4_C_O
 
- TVX_Inst_Gather4_O
 
- TVX_Inst_GetBufferResInfo
 
- TVX_Inst_GetGradientsH
 
- TVX_Inst_GetGradientsV
 
- TVX_Inst_GetLOD
 
- TVX_Inst_GetNumberOfSamples
 
- TVX_Inst_GetTextureResInfo
 
- TVX_Inst_KeepGradients
 
- TVX_Inst_LD
 
- TVX_Inst_NormalVertexFetch
 
- TVX_Inst_Pass
 
- TVX_Inst_RESERVED_15
 
- TVX_Inst_RESERVED_2
 
- TVX_Inst_Sample
 
- TVX_Inst_Sample_C
 
- TVX_Inst_Sample_C_G
 
- TVX_Inst_Sample_C_G_LB
 
- TVX_Inst_Sample_C_L
 
- TVX_Inst_Sample_C_LB
 
- TVX_Inst_Sample_C_LZ
 
- TVX_Inst_Sample_G
 
- TVX_Inst_Sample_G_LB
 
- TVX_Inst_Sample_L
 
- TVX_Inst_Sample_LB
 
- TVX_Inst_Sample_LZ
 
- TVX_Inst_SemanticVertexFetch
 
- TVX_Inst_SetGradientsH
 
- TVX_Inst_SetGradientsV
 
- TVX_Inst_SetTextureOffsets
 
- TVX_NUM_FORMAT_ALL
 
- TVX_NumFormatAll_Int
 
- TVX_NumFormatAll_Norm
 
- TVX_NumFormatAll_RESERVED_3
 
- TVX_NumFormatAll_Scaled
 
- TVX_SRC_SEL
 
- TVX_SRFModeAll_NZ
 
- TVX_SRFModeAll_ZCMO
 
- TVX_SRF_MODE_ALL
 
- TVX_SrcSel_0f
 
- TVX_SrcSel_1f
 
- TVX_SrcSel_W
 
- TVX_SrcSel_X
 
- TVX_SrcSel_Y
 
- TVX_SrcSel_Z
 
- TVX_TYPE
 
- TVX_Type_InvalidTextureResource
 
- TVX_Type_InvalidVertexBuffer
 
- TVX_Type_ValidTextureResource
 
- TVX_Type_ValidVertexBuffer
 
- TVYFilterPtr1Offset
 
- TV_AUTO_SCALE
 
- TV_AU_MASK
 
- TV_AU_SHIFT
 
- TV_AVIDEO
 
- TV_AV_MASK
 
- TV_AV_SHIFT
 
- TV_AY_MASK
 
- TV_AY_SHIFT
 
- TV_BLACK_LEVEL_MASK
 
- TV_BLACK_LEVEL_SHIFT
 
- TV_BLANK_LEVEL_MASK
 
- TV_BLANK_LEVEL_SHIFT
 
- TV_BRIGHTNESS_MASK
 
- TV_BRIGHTNESS_SHIFT
 
- TV_BURST_ENA
 
- TV_BURST_END
 
- TV_BURST_LEVEL_MASK
 
- TV_BURST_LEVEL_SHIFT
 
- TV_BURST_START
 
- TV_BU_MASK
 
- TV_BU_SHIFT
 
- TV_BV_MASK
 
- TV_BV_SHIFT
 
- TV_BY_MASK
 
- TV_BY_SHIFT
 
- TV_CC_CONTROL
 
- TV_CC_DATA
 
- TV_CC_DATA_1_MASK
 
- TV_CC_DATA_1_SHIFT
 
- TV_CC_DATA_2_MASK
 
- TV_CC_DATA_2_SHIFT
 
- TV_CC_ENABLE
 
- TV_CC_FID_MASK
 
- TV_CC_FID_SHIFT
 
- TV_CC_HOFF_MASK
 
- TV_CC_HOFF_SHIFT
 
- TV_CC_LINE_MASK
 
- TV_CC_LINE_SHIFT
 
- TV_CC_RDY
 
- TV_CHSCART
 
- TV_CHYPBPR525I
 
- TV_CLK
 
- TV_CLR_KNOBS
 
- TV_CLR_LEVEL
 
- TV_CONTRAST_MASK
 
- TV_CONTRAST_SHIFT
 
- TV_CSC_U
 
- TV_CSC_U2
 
- TV_CSC_V
 
- TV_CSC_V2
 
- TV_CSC_Y
 
- TV_CSC_Y2
 
- TV_CTL
 
- TV_CTL_SAVE
 
- TV_DAC
 
- TV_DAC_CLK
 
- TV_DAC_CNTL
 
- TV_DAC_CNTL_BDACPD
 
- TV_DAC_CNTL_BGADJ_MASK
 
- TV_DAC_CNTL_BGADJ__SHIFT
 
- TV_DAC_CNTL_BGSLEEP
 
- TV_DAC_CNTL_DACADJ_MASK
 
- TV_DAC_CNTL_DACADJ__SHIFT
 
- TV_DAC_CNTL_DETECT
 
- TV_DAC_CNTL_GDACPD
 
- TV_DAC_CNTL_RDACPD
 
- TV_DAC_SAVE
 
- TV_DELAYBYPASS
 
- TV_DMA_FF_UNDERFLOW
 
- TV_DMA_FF_UNDERFLOW_ENA
 
- TV_DMA_FF_UNDERFLOW_ENA_MASK
 
- TV_DMA_FF_UNDERFLOW_MASK
 
- TV_DMA_FRAME_IRQ0
 
- TV_DMA_FRAME_IRQ0_ENA
 
- TV_DMA_FRAME_IRQ0_ENA_MASK
 
- TV_DMA_FRAME_IRQ0_MASK
 
- TV_DMA_FRAME_IRQ1
 
- TV_DMA_FRAME_IRQ1_ENA
 
- TV_DMA_FRAME_IRQ1_ENA_MASK
 
- TV_DMA_FRAME_IRQ1_MASK
 
- TV_ENABLE_RST
 
- TV_ENCODER_CONTROL_PARAMETERS
 
- TV_ENCODER_CONTROL_PS_ALLOCATION
 
- TV_ENC_AHB_CLK
 
- TV_ENC_AHB_RESET
 
- TV_ENC_C0_FIX
 
- TV_ENC_CLK
 
- TV_ENC_ENABLE
 
- TV_ENC_MODE
 
- TV_ENC_OUTPUT_COMPONENT
 
- TV_ENC_OUTPUT_COMPOSITE
 
- TV_ENC_OUTPUT_SVIDEO
 
- TV_ENC_OUTPUT_SVIDEO_COMPOSITE
 
- TV_ENC_PIPE_SEL
 
- TV_ENC_PIPE_SEL_MASK
 
- TV_ENC_PIPE_SEL_SHIFT
 
- TV_ENC_RESET
 
- TV_ENC_SDP_FIX
 
- TV_EQL_END
 
- TV_EQUAL_ENA
 
- TV_FILTER_CTL_1
 
- TV_FILTER_CTL_2
 
- TV_FILTER_CTL_3
 
- TV_FLICK_XMAX
 
- TV_FLICK_XMIN
 
- TV_FLICK_YMAX
 
- TV_FLICK_YMIN
 
- TV_FORMAT_NUM
 
- TV_FRAMEDONE_ENA
 
- TV_FRAMEDONE_ENA_MASK
 
- TV_FRAME_IRQ0
 
- TV_FRAME_IRQ0_ENA
 
- TV_FRAME_IRQ0_ENA_MASK
 
- TV_FRAME_IRQ0_MASK
 
- TV_FRAME_IRQ1
 
- TV_FRAME_IRQ1_ENA
 
- TV_FRAME_IRQ1_ENA_MASK
 
- TV_FRAME_IRQ1_MASK
 
- TV_FUSE_STATE_DISABLED
 
- TV_FUSE_STATE_ENABLED
 
- TV_FUSE_STATE_MASK
 
- TV_FUSE_STATE_NO_MACROVISION
 
- TV_GRA_FF_UNDERFLOW
 
- TV_GRA_FF_UNDERFLOW_ENA
 
- TV_GRA_FF_UNDERFLOW_ENA_MASK
 
- TV_GRA_FF_UNDERFLOW_MASK
 
- TV_GU_MASK
 
- TV_GU_SHIFT
 
- TV_GV_MASK
 
- TV_GV_SHIFT
 
- TV_GY_MASK
 
- TV_GY_SHIFT
 
- TV_HBLANK_END
 
- TV_HBLANK_END_MASK
 
- TV_HBLANK_END_SHIFT
 
- TV_HBLANK_START
 
- TV_HBLANK_START_MASK
 
- TV_HBLANK_START_SHIFT
 
- TV_HBURST_LEN_MASK
 
- TV_HBURST_LEN_SHIFT
 
- TV_HBURST_START_MASK
 
- TV_HBURST_START_SHIFT
 
- TV_HDMI_RESET
 
- TV_HIVISION
 
- TV_HOTPLUG_INT_EN
 
- TV_HOTPLUG_INT_STATUS
 
- TV_HSCALE_FRAC_MASK
 
- TV_HSCALE_FRAC_SHIFT
 
- TV_HSYNC_END
 
- TV_HSYNC_END_MASK
 
- TV_HSYNC_END_SHIFT
 
- TV_HSYNC_START
 
- TV_HTOTAL_MASK
 
- TV_HTOTAL_SHIFT
 
- TV_HUE_MASK
 
- TV_HUE_SHIFT
 
- TV_H_CHROMA
 
- TV_H_CTL_1
 
- TV_H_CTL_2
 
- TV_H_CTL_3
 
- TV_H_LUMA
 
- TV_INTERFACE
 
- TV_LAYER_ALPHA_SEL1
 
- TV_MARGIN_BOTTOM
 
- TV_MARGIN_LEFT
 
- TV_MARGIN_RIGHT
 
- TV_MARGIN_TOP
 
- TV_MASK
 
- TV_MASTER_CNTL
 
- TV_MAX_FREQ
 
- TV_MIN_FREQ
 
- TV_NBR_END_MASK
 
- TV_NBR_END_SHIFT
 
- TV_NORM_HD1080I
 
- TV_NORM_HD480I
 
- TV_NORM_HD480P
 
- TV_NORM_HD576I
 
- TV_NORM_HD576P
 
- TV_NORM_HD720P
 
- TV_NORM_NTSC_J
 
- TV_NORM_NTSC_M
 
- TV_NORM_PAL
 
- TV_NORM_PAL_60
 
- TV_NORM_PAL_M
 
- TV_NORM_PAL_N
 
- TV_NORM_PAL_NC
 
- TV_NTSC
 
- TV_NTSCJ
 
- TV_OVERSAMPLE_2X
 
- TV_OVERSAMPLE_4X
 
- TV_OVERSAMPLE_8X
 
- TV_OVERSAMPLE_MASK
 
- TV_OVERSAMPLE_NONE
 
- TV_PAL
 
- TV_PALM
 
- TV_PALN
 
- TV_PAL_BURST
 
- TV_PED_EVEN_END
 
- TV_PED_EVEN_START
 
- TV_PED_ODD_END
 
- TV_PED_ODD_START
 
- TV_PED_UVDET
 
- TV_PLL_CNTL
 
- TV_PLL_CNTL1
 
- TV_PLL_CNTL2
 
- TV_PROGRESSIVE
 
- TV_RU_MASK
 
- TV_RU_SHIFT
 
- TV_RV_MASK
 
- TV_RV_SHIFT
 
- TV_RY_MASK
 
- TV_RY_SHIFT
 
- TV_SATURATION_MASK
 
- TV_SATURATION_SHIFT
 
- TV_SCART
 
- TV_SCDDA1_INC_MASK
 
- TV_SCDDA1_INC_SHIFT
 
- TV_SCDDA2_INC_MASK
 
- TV_SCDDA2_INC_SHIFT
 
- TV_SCDDA2_SIZE_MASK
 
- TV_SCDDA2_SIZE_SHIFT
 
- TV_SCDDA3_INC_MASK
 
- TV_SCDDA3_INC_SHIFT
 
- TV_SCDDA3_SIZE_MASK
 
- TV_SCDDA3_SIZE_SHIFT
 
- TV_SCFH
 
- TV_SCFL
 
- TV_SCP
 
- TV_SC_CTL_1
 
- TV_SC_CTL_2
 
- TV_SC_CTL_3
 
- TV_SC_DDA1_EN
 
- TV_SC_DDA2_EN
 
- TV_SC_DDA3_EN
 
- TV_SC_RESET_EVERY_2
 
- TV_SC_RESET_EVERY_4
 
- TV_SC_RESET_EVERY_8
 
- TV_SC_RESET_NEVER
 
- TV_SERR_END
 
- TV_SERR_START
 
- TV_SHIFT
 
- TV_SLOW_SYNC
 
- TV_SRC
 
- TV_STANDARD
 
- TV_STD_NTSC
 
- TV_STD_NTSC_J
 
- TV_STD_PAL
 
- TV_STD_PAL_60
 
- TV_STD_PAL_CN
 
- TV_STD_PAL_M
 
- TV_STD_PAL_N
 
- TV_STD_SCART_PAL
 
- TV_STD_SECAM
 
- TV_SVIDEO
 
- TV_SYNC_YGAIN
 
- TV_TEST_MODE_MASK
 
- TV_TEST_MODE_MONITOR_DETECT
 
- TV_TEST_MODE_NORMAL
 
- TV_TEST_MODE_PATTERN_1
 
- TV_TEST_MODE_PATTERN_2
 
- TV_TEST_MODE_PATTERN_3
 
- TV_TEST_MODE_PATTERN_4
 
- TV_TEST_MODE_PATTERN_5
 
- TV_TRILEVEL_SYNC
 
- TV_UV_BURST_AMP
 
- TV_UV_DELAY1
 
- TV_UV_GAIN
 
- TV_VADAPT
 
- TV_VADAPT_MODE_LEAST
 
- TV_VADAPT_MODE_MASK
 
- TV_VADAPT_MODE_MODERATE
 
- TV_VADAPT_MODE_MOST
 
- TV_VBLANK_EVEN_END
 
- TV_VBLANK_EVEN_START
 
- TV_VBLANK_ODD_END
 
- TV_VBLANK_ODD_START
 
- TV_VBLNK_VALID_EN
 
- TV_VBURST_END_F1_MASK
 
- TV_VBURST_END_F1_SHIFT
 
- TV_VBURST_END_F2_MASK
 
- TV_VBURST_END_F2_SHIFT
 
- TV_VBURST_END_F3_MASK
 
- TV_VBURST_END_F3_SHIFT
 
- TV_VBURST_END_F4_MASK
 
- TV_VBURST_END_F4_SHIFT
 
- TV_VBURST_START_F1_MASK
 
- TV_VBURST_START_F1_SHIFT
 
- TV_VBURST_START_F2_MASK
 
- TV_VBURST_START_F2_SHIFT
 
- TV_VBURST_START_F3_MASK
 
- TV_VBURST_START_F3_SHIFT
 
- TV_VBURST_START_F4_MASK
 
- TV_VBURST_START_F4_SHIFT
 
- TV_VEQ_LEN_MASK
 
- TV_VEQ_LEN_SHIFT
 
- TV_VEQ_START_F1_MASK
 
- TV_VEQ_START_F1_SHIFT
 
- TV_VEQ_START_F2_MASK
 
- TV_VEQ_START_F2_SHIFT
 
- TV_VI_END_F1_MASK
 
- TV_VI_END_F1_SHIFT
 
- TV_VI_END_F2_MASK
 
- TV_VI_END_F2_SHIFT
 
- TV_VSCALE_FRAC_MASK
 
- TV_VSCALE_FRAC_SHIFT
 
- TV_VSCALE_INT_MASK
 
- TV_VSCALE_INT_SHIFT
 
- TV_VSCALE_IP_FRAC_MASK
 
- TV_VSCALE_IP_FRAC_SHIFT
 
- TV_VSCALE_IP_INT_MASK
 
- TV_VSCALE_IP_INT_SHIFT
 
- TV_VSYNC_EVEN_END
 
- TV_VSYNC_EVEN_START
 
- TV_VSYNC_LEN_MASK
 
- TV_VSYNC_LEN_SHIFT
 
- TV_VSYNC_ODD_END
 
- TV_VSYNC_ODD_START
 
- TV_VSYNC_START_F1_MASK
 
- TV_VSYNC_START_F1_SHIFT
 
- TV_VSYNC_START_F2_MASK
 
- TV_VSYNC_START_F2_SHIFT
 
- TV_VSYNC_VGA_HS
 
- TV_V_CHROMA
 
- TV_V_CTL_1
 
- TV_V_CTL_2
 
- TV_V_CTL_3
 
- TV_V_CTL_4
 
- TV_V_CTL_5
 
- TV_V_CTL_6
 
- TV_V_CTL_7
 
- TV_V_FILTER_BYPASS
 
- TV_V_LUMA
 
- TV_WIN_POS
 
- TV_WIN_SIZE
 
- TV_XPOS_MASK
 
- TV_XPOS_SHIFT
 
- TV_XSIZE_MASK
 
- TV_XSIZE_SHIFT
 
- TV_YC_SKEW_MASK
 
- TV_YPBPR
 
- TV_YPBPR1080I
 
- TV_YPBPR525I
 
- TV_YPBPR525P
 
- TV_YPBPR750P
 
- TV_YPBPRALL
 
- TV_YPOS_MASK
 
- TV_YPOS_SHIFT
 
- TV_YSIZE_MASK
 
- TV_YSIZE_SHIFT
 
- TV_Y_DELAY1
 
- TV_Y_DELAY2
 
- TVinterface
 
- TW2804_REG_AUTOGAIN
 
- TW2804_REG_BLUE_BALANCE
 
- TW2804_REG_BRIGHTNESS
 
- TW2804_REG_CHROMA_GAIN
 
- TW2804_REG_COLOR_KILLER
 
- TW2804_REG_CONTRAST
 
- TW2804_REG_GAIN
 
- TW2804_REG_HUE
 
- TW2804_REG_RED_BALANCE
 
- TW2804_REG_SATURATION
 
- TW286x_AUDIO_INPUT_GAIN_ADDR
 
- TW286x_AUDIO_OUTPUT_VOL_ADDR
 
- TW286x_AV_STAT_ADDR
 
- TW286x_BRIGHTNESS_ADDR
 
- TW286x_CONTRAST_ADDR
 
- TW286x_HUE_ADDR
 
- TW286x_SATURATIONU_ADDR
 
- TW286x_SATURATIONV_ADDR
 
- TW286x_SHARPNESS
 
- TW5864_ADPCM
 
- TW5864_ADPCM_DEC
 
- TW5864_ADPCM_DEC_RD_WR_PTR
 
- TW5864_ADPCM_ENC
 
- TW5864_ADPCM_ENC_RD_PTR1
 
- TW5864_ADPCM_ENC_RD_PTR2
 
- TW5864_ADPCM_ENC_WR_PTR1
 
- TW5864_ADPCM_ENC_WR_PTR2
 
- TW5864_ADPCM_ENC_XX_MASK
 
- TW5864_ADPCM_ENC_XX_PTR2_SHIFT
 
- TW5864_ADPCM_IN_DATA
 
- TW5864_AD_BIT_MODE
 
- TW5864_AD_INTR_ENB
 
- TW5864_AD_INTR_REG
 
- TW5864_AD_MAST_ENB
 
- TW5864_AD_ORIG_RD_PTR1
 
- TW5864_AD_ORIG_RD_PTR2
 
- TW5864_AD_ORIG_RD_PTR3
 
- TW5864_AD_ORIG_WR_PTR1
 
- TW5864_AD_ORIG_WR_PTR2
 
- TW5864_AD_ORIG_WR_PTR3
 
- TW5864_AD_VSYNC_INTR
 
- TW5864_APP_SOFT_RST
 
- TW5864_ARB12
 
- TW5864_ARB12_ENB
 
- TW5864_ARB12_TIME_OUT_CNT
 
- TW5864_AUD
 
- TW5864_AUDIO_BUF_FLAG
 
- TW5864_AUDIO_BUF_FLAG_SHIFT
 
- TW5864_AUDIO_EOF_INTR
 
- TW5864_AUD_ADPCM
 
- TW5864_AUD_ADPCM_CH_EN
 
- TW5864_AUD_DATA_IN_ENB
 
- TW5864_AUD_DEC_REQ0_ENB
 
- TW5864_AUD_DEC_REQ1_ENB
 
- TW5864_AUD_ENC_REQ_ENB
 
- TW5864_AUD_MODE
 
- TW5864_AUD_ORG_CH_EN
 
- TW5864_AUD_SAMPLE_RATE
 
- TW5864_AUD_SAMPLE_RATE_SHIFT
 
- TW5864_AUD_TYPE
 
- TW5864_AUD_TYPE_SHIFT
 
- TW5864_AU_INTR_REG
 
- TW5864_AU_INTR_REG_SHIFT
 
- TW5864_AU_MAST_ENB_CHN
 
- TW5864_AU_MAST_ENB_CHN_SHIFT
 
- TW5864_BRST_BUSY
 
- TW5864_BRST_END
 
- TW5864_BRST_END_INTR
 
- TW5864_BRST_ERR
 
- TW5864_BRST_ERR_INTR
 
- TW5864_BRST_LENGTH
 
- TW5864_BRST_LENGTH_SHIFT
 
- TW5864_BRST_RW
 
- TW5864_BURST_CNTR_MAX
 
- TW5864_BUSY
 
- TW5864_BUS_D1
 
- TW5864_CAS_LATENCY
 
- TW5864_CFG_1MS_CNT
 
- TW5864_CH_MV_PTR1
 
- TW5864_CH_MV_PTR2
 
- TW5864_CIF_MAP_MD
 
- TW5864_CS2DAT_CNT
 
- TW5864_DATA_MODE
 
- TW5864_DATA_MODE_SHIFT
 
- TW5864_DATA_VLD_WIDTH
 
- TW5864_DDR
 
- TW5864_DDR_AB_SEL
 
- TW5864_DDR_ADDR
 
- TW5864_DDR_BRST_EN
 
- TW5864_DDR_B_OFFSET
 
- TW5864_DDR_CTL
 
- TW5864_DDR_MODE
 
- TW5864_DDR_ON_CHIP_MAP
 
- TW5864_DDR_PAGE_CNTL
 
- TW5864_DDR_PERIODS
 
- TW5864_DDR_PROC_CNTR_MAX_H
 
- TW5864_DDR_PROC_CNTR_MAX_L
 
- TW5864_DDR_REF_CNTR_MAX
 
- TW5864_DDR_SELFTEST_MODE
 
- TW5864_DDR_SELF_TEST_CMD
 
- TW5864_DI_EN
 
- TW5864_DI_MD
 
- TW5864_DPR_BUF_ADDR
 
- TW5864_DPR_BUF_SIZE
 
- TW5864_DPR_BUF_START
 
- TW5864_DSP
 
- TW5864_DSP_CHROM_SW
 
- TW5864_DSP_CODEC
 
- TW5864_DSP_CODEC_MODE
 
- TW5864_DSP_DWN_X
 
- TW5864_DSP_DWN_Y
 
- TW5864_DSP_ENC_CHN
 
- TW5864_DSP_ENC_ORG_PTR_MASK
 
- TW5864_DSP_ENC_ORG_PTR_REG
 
- TW5864_DSP_ENC_ORG_PTR_SHIFT
 
- TW5864_DSP_ENC_REC
 
- TW5864_DSP_ENC_REF_PTR
 
- TW5864_DSP_FLW_CNTL
 
- TW5864_DSP_FRAME_TYPE
 
- TW5864_DSP_FRAME_TYPE_D1
 
- TW5864_DSP_I4x4_OFFSET
 
- TW5864_DSP_I4x4_WEIGHT
 
- TW5864_DSP_INTER_ST
 
- TW5864_DSP_INTRA_MODE
 
- TW5864_DSP_INTRA_MODE_16x16
 
- TW5864_DSP_INTRA_MODE_4x4
 
- TW5864_DSP_INTRA_MODE_4x4_AND_16x16
 
- TW5864_DSP_INTRA_MODE_MASK
 
- TW5864_DSP_INTRA_MODE_SHIFT
 
- TW5864_DSP_LPF_OFFSET
 
- TW5864_DSP_MB_DELAY
 
- TW5864_DSP_MB_QP
 
- TW5864_DSP_MB_WAIT
 
- TW5864_DSP_OSD_ATTRI_BASE
 
- TW5864_DSP_OSD_ENABLE
 
- TW5864_DSP_PIC_MAX_MB
 
- TW5864_DSP_PIC_MAX_MB_X
 
- TW5864_DSP_PIC_MAX_MB_Y
 
- TW5864_DSP_QP
 
- TW5864_DSP_RD_OF
 
- TW5864_DSP_REC_BUF_PTR
 
- TW5864_DSP_REF
 
- TW5864_DSP_REF_FRM
 
- TW5864_DSP_REF_MVP_LAMBDA
 
- TW5864_DSP_REF_PIC
 
- TW5864_DSP_REF_PIC_CHM
 
- TW5864_DSP_REF_PIC_LU
 
- TW5864_DSP_REF_PIC_MAX
 
- TW5864_DSP_RESID_MODE_OFFSET
 
- TW5864_DSP_SEN
 
- TW5864_DSP_SEN_HFULL
 
- TW5864_DSP_SEN_MODE
 
- TW5864_DSP_SEN_MODE_CH0
 
- TW5864_DSP_SEN_MODE_CH1
 
- TW5864_DSP_SEN_PIC_CHM
 
- TW5864_DSP_SEN_PIC_LU
 
- TW5864_DSP_SEN_PIC_MAX
 
- TW5864_DSP_SKIP
 
- TW5864_DSP_SKIP_OFEN
 
- TW5864_DSP_SKIP_OFFSET
 
- TW5864_DSP_WIN_SIZE
 
- TW5864_DSP_WR_OF
 
- TW5864_DUAL_STR
 
- TW5864_DVM_MV_REQ_ENB
 
- TW5864_EMU
 
- TW5864_EMU_EN_BHOST
 
- TW5864_EMU_EN_DDR
 
- TW5864_EMU_EN_LPF
 
- TW5864_EMU_EN_ME
 
- TW5864_EMU_EN_PLBK
 
- TW5864_EMU_EN_SEN
 
- TW5864_ENABLE
 
- TW5864_ENC_BUF_PTR_REC1
 
- TW5864_ENC_BUF_PTR_REC2
 
- TW5864_END_FLAG
 
- TW5864_ERR_CNTR_H_AND_FLAG
 
- TW5864_ERR_CNTR_H_MASK
 
- TW5864_ERR_CNTR_L
 
- TW5864_FRAME
 
- TW5864_FRAME_BUS1
 
- TW5864_FRAME_BUS2
 
- TW5864_FRAME_HEIGHT_BUS_A
 
- TW5864_FRAME_HEIGHT_BUS_B
 
- TW5864_FRAME_WIDTH_BUS_A
 
- TW5864_FRAME_WIDTH_BUS_B
 
- TW5864_FULL_HALF_FLAG
 
- TW5864_FULL_HALF_MODE_SEL
 
- TW5864_GPIO1
 
- TW5864_GPIO2
 
- TW5864_GPIO_DATA
 
- TW5864_GPIO_OEN
 
- TW5864_GPIO_OEN_SHIFT
 
- TW5864_H264EN_BUS0_MAP
 
- TW5864_H264EN_BUS1_MAP
 
- TW5864_H264EN_BUS2_MAP
 
- TW5864_H264EN_BUS3_MAP
 
- TW5864_H264EN_BUS_MAX_CH
 
- TW5864_H264EN_CH_DNS
 
- TW5864_H264EN_CH_EN
 
- TW5864_H264EN_CH_FMT_REG1
 
- TW5864_H264EN_CH_FMT_REG2
 
- TW5864_H264EN_CH_PROG
 
- TW5864_H264EN_CH_STATUS
 
- TW5864_H264EN_RATE_CNTL_HI_WORD
 
- TW5864_H264EN_RATE_CNTL_LO_WORD
 
- TW5864_H264EN_RATE_MAX_LINE_EVEN
 
- TW5864_H264EN_RATE_MAX_LINE_ODD
 
- TW5864_H264EN_RATE_MAX_LINE_ODD_SHIFT
 
- TW5864_H264EN_RATE_MAX_LINE_REG1
 
- TW5864_H264EN_RATE_MAX_LINE_REG2
 
- TW5864_H264REV
 
- TW5864_HD1_MAP_MD
 
- TW5864_HPEL_EN
 
- TW5864_HW_VERSION
 
- TW5864_I2C_PHASE_CFG
 
- TW5864_IIC
 
- TW5864_IIC_DATA
 
- TW5864_IIC_DEV_ADDR
 
- TW5864_IIC_DEV_ADDR_SHIFT
 
- TW5864_IIC_DONE
 
- TW5864_IIC_DONE_INTR
 
- TW5864_IIC_ENB
 
- TW5864_IIC_INTR_ENB
 
- TW5864_IIC_REG_ADDR
 
- TW5864_IIC_REG_ADDR_SHIFT
 
- TW5864_IIC_RW
 
- TW5864_INDIR_AIGAIN1
 
- TW5864_INDIR_AIGAIN2
 
- TW5864_INDIR_AIN_0x06D
 
- TW5864_INDIR_AIN_0x0E3
 
- TW5864_INDIR_AIN_0x0E3_ACLKPPOLI
 
- TW5864_INDIR_AIN_0x0E3_ACLKPPOLO
 
- TW5864_INDIR_AIN_0x0E3_ACLKRPOL
 
- TW5864_INDIR_AIN_0x0E3_AFAUTO
 
- TW5864_INDIR_AIN_0x0E3_AFMD
 
- TW5864_INDIR_AIN_0x0E3_EXT_ADATP
 
- TW5864_INDIR_AIN_0x0E4
 
- TW5864_INDIR_AIN_0x0E4_ADATPDLY
 
- TW5864_INDIR_AIN_0x0E4_ASYNPDLY
 
- TW5864_INDIR_AIN_0x0E4_ASYNRDLY
 
- TW5864_INDIR_AIN_0x0E4_I2S8MODE
 
- TW5864_INDIR_AIN_0x0E4_INLAWMD
 
- TW5864_INDIR_AIN_0x0E4_MASCKMD
 
- TW5864_INDIR_AIN_0x0E4_PBINSWAP
 
- TW5864_INDIR_AIN_A5DETENA
 
- TW5864_INDIR_AIN_LAWMD
 
- TW5864_INDIR_AIN_LAWMD_SHIFT
 
- TW5864_INDIR_AIN_MIX_DERATIO
 
- TW5864_INDIR_AIN_MIX_MUTE
 
- TW5864_INDIR_BD_DET
 
- TW5864_INDIR_CLK0_SEL
 
- TW5864_INDIR_CLK0_SEL_PV2_MASK
 
- TW5864_INDIR_CLK0_SEL_PV2_SHIFT
 
- TW5864_INDIR_CLK0_SEL_PV_MASK
 
- TW5864_INDIR_CLK0_SEL_PV_SHIFT
 
- TW5864_INDIR_CLK0_SEL_VD_MASK
 
- TW5864_INDIR_CLK0_SEL_VD_SHIFT
 
- TW5864_INDIR_CROP_ETC
 
- TW5864_INDIR_CROP_ETC_CROP_EN
 
- TW5864_INDIR_DDRA_DLL_CLK90_SEL
 
- TW5864_INDIR_DDRA_DLL_DQS_SEL0
 
- TW5864_INDIR_DDRA_DLL_DQS_SEL1
 
- TW5864_INDIR_DDRA_DLL_TEST_SEL_AND_TAP_S
 
- TW5864_INDIR_DDRB_DLL_CLK90_SEL
 
- TW5864_INDIR_DDRB_DLL_DQS_SEL0
 
- TW5864_INDIR_DDRB_DLL_DQS_SEL1
 
- TW5864_INDIR_DDRB_DLL_TEST_SEL_AND_TAP_S
 
- TW5864_INDIR_DETECTION_CTL0
 
- TW5864_INDIR_DETECTION_CTL0_BD_CELSENS
 
- TW5864_INDIR_DETECTION_CTL0_MD_DIS
 
- TW5864_INDIR_DETECTION_CTL0_MD_STRB
 
- TW5864_INDIR_DETECTION_CTL0_MD_STRB_EN
 
- TW5864_INDIR_DETECTION_CTL1
 
- TW5864_INDIR_DETECTION_CTL1_MD_PIXEL_OS
 
- TW5864_INDIR_DETECTION_CTL1_MD_TMPSENS
 
- TW5864_INDIR_DETECTION_CTL1_MD_TMPSENS_SHIFT
 
- TW5864_INDIR_DETECTION_CTL2
 
- TW5864_INDIR_DETECTION_CTL2_MD_FIELD
 
- TW5864_INDIR_DETECTION_CTL2_MD_FIELD_SHIFT
 
- TW5864_INDIR_DETECTION_CTL2_MD_LVSENS
 
- TW5864_INDIR_DETECTION_CTL2_MD_REFFLD
 
- TW5864_INDIR_DETECTION_CTL3
 
- TW5864_INDIR_DETECTION_CTL3_MD_CELSENS
 
- TW5864_INDIR_DETECTION_CTL3_MD_CELSENS_SHIFT
 
- TW5864_INDIR_DETECTION_CTL3_MD_SPEED
 
- TW5864_INDIR_DETECTION_CTL4
 
- TW5864_INDIR_DETECTION_CTL4_BD_LVSENS
 
- TW5864_INDIR_DETECTION_CTL4_MD_SPSENS
 
- TW5864_INDIR_DETECTION_CTL4_MD_SPSENS_SHIFT
 
- TW5864_INDIR_DETECTION_CTL5
 
- TW5864_INDIR_DETECTION_CTL5_ND_LVSENS
 
- TW5864_INDIR_DETECTION_CTL5_ND_TMPSENS
 
- TW5864_INDIR_DETECTION_CTL5_ND_TMPSENS_SHIFT
 
- TW5864_INDIR_ID
 
- TW5864_INDIR_INTERRUPT1
 
- TW5864_INDIR_INTERRUPT2
 
- TW5864_INDIR_INTERRUPT_MASK1
 
- TW5864_INDIR_INTERRUPT_MASK2
 
- TW5864_INDIR_INTERRUPT_SUMMARY
 
- TW5864_INDIR_IN_PIC_HEIGHT
 
- TW5864_INDIR_IN_PIC_WIDTH
 
- TW5864_INDIR_MASK_CH_SEL
 
- TW5864_INDIR_MD_BASE_ADDR
 
- TW5864_INDIR_MD_DET
 
- TW5864_INDIR_MD_DI_CELLSENS
 
- TW5864_INDIR_MD_DI_CNT
 
- TW5864_INDIR_MD_DI_LVSENS
 
- TW5864_INDIR_MD_STRB
 
- TW5864_INDIR_MOTION_FLAG
 
- TW5864_INDIR_MOTION_FLAG_BYTE_COUNT
 
- TW5864_INDIR_MOTION_MASK
 
- TW5864_INDIR_MOTION_MASK_BYTE_COUNT
 
- TW5864_INDIR_ND_DET
 
- TW5864_INDIR_NOVID_DET
 
- TW5864_INDIR_OUT_PIC_HEIGHT
 
- TW5864_INDIR_OUT_PIC_WIDTH
 
- TW5864_INDIR_PV_VD_CK_POL
 
- TW5864_INDIR_PV_VD_CK_POL_PV
 
- TW5864_INDIR_PV_VD_CK_POL_VD
 
- TW5864_INDIR_RESET
 
- TW5864_INDIR_RESET_DLL
 
- TW5864_INDIR_RESET_MUX_CORE
 
- TW5864_INDIR_RESET_VD
 
- TW5864_INDIR_RGR_MOTION_SEL
 
- TW5864_INDIR_VD_108_POL
 
- TW5864_INDIR_VD_108_POL_BOTH
 
- TW5864_INDIR_VD_108_POL_VD12
 
- TW5864_INDIR_VD_108_POL_VD34
 
- TW5864_INDIR_VIN_0
 
- TW5864_INDIR_VIN_0_DET50
 
- TW5864_INDIR_VIN_0_FLD
 
- TW5864_INDIR_VIN_0_HLOCK
 
- TW5864_INDIR_VIN_0_MONO
 
- TW5864_INDIR_VIN_0_SLOCK
 
- TW5864_INDIR_VIN_0_VDLOSS
 
- TW5864_INDIR_VIN_0_VLOCK
 
- TW5864_INDIR_VIN_1
 
- TW5864_INDIR_VIN_1_NINTL
 
- TW5864_INDIR_VIN_1_VCR
 
- TW5864_INDIR_VIN_1_VSHP
 
- TW5864_INDIR_VIN_1_VSTD
 
- TW5864_INDIR_VIN_1_WKAIR
 
- TW5864_INDIR_VIN_1_WKAIR1
 
- TW5864_INDIR_VIN_2_HDELAY_XY_LO
 
- TW5864_INDIR_VIN_3_HACTIVE_XY_LO
 
- TW5864_INDIR_VIN_4_VDELAY_XY_LO
 
- TW5864_INDIR_VIN_5_VACTIVE_XY_LO
 
- TW5864_INDIR_VIN_6
 
- TW5864_INDIR_VIN_6_HACTIVE_XY_HI
 
- TW5864_INDIR_VIN_6_HACTIVE_XY_HI_SHIFT
 
- TW5864_INDIR_VIN_6_HDELAY_XY_HI
 
- TW5864_INDIR_VIN_6_VACTIVE_XY_HI
 
- TW5864_INDIR_VIN_6_VDELAY_XY_HI
 
- TW5864_INDIR_VIN_7_HUE
 
- TW5864_INDIR_VIN_8
 
- TW5864_INDIR_VIN_8_CTI
 
- TW5864_INDIR_VIN_8_CTI_SHIFT
 
- TW5864_INDIR_VIN_8_SCURVE
 
- TW5864_INDIR_VIN_8_SHARPNESS
 
- TW5864_INDIR_VIN_9_CNTRST
 
- TW5864_INDIR_VIN_A_BRIGHT
 
- TW5864_INDIR_VIN_B_SAT_U
 
- TW5864_INDIR_VIN_C_SAT_V
 
- TW5864_INDIR_VIN_D
 
- TW5864_INDIR_VIN_D_CSBAD
 
- TW5864_INDIR_VIN_D_CSTRIPE
 
- TW5864_INDIR_VIN_D_CTYPE2
 
- TW5864_INDIR_VIN_D_MCVSN
 
- TW5864_INDIR_VIN_E
 
- TW5864_INDIR_VIN_E_ATREG
 
- TW5864_INDIR_VIN_E_DETSTUS
 
- TW5864_INDIR_VIN_E_STANDARD
 
- TW5864_INDIR_VIN_E_STDNOW
 
- TW5864_INDIR_VIN_E_STDNOW_SHIFT
 
- TW5864_INDIR_VIN_F
 
- TW5864_INDIR_VIN_F_ATSTART
 
- TW5864_INDIR_VIN_F_NTSC44EN
 
- TW5864_INDIR_VIN_F_NTSCEN
 
- TW5864_INDIR_VIN_F_PAL60EN
 
- TW5864_INDIR_VIN_F_PALBEN
 
- TW5864_INDIR_VIN_F_PALCNEN
 
- TW5864_INDIR_VIN_F_PALMEN
 
- TW5864_INDIR_VIN_F_SECAMEN
 
- TW5864_IND_ADDR
 
- TW5864_IND_CTL
 
- TW5864_IND_DATA
 
- TW5864_INPUTS
 
- TW5864_INTERLACING
 
- TW5864_INTRA_EN
 
- TW5864_INTR_AD
 
- TW5864_INTR_AD_VSYNC
 
- TW5864_INTR_ASSERT_H
 
- TW5864_INTR_ASSERT_L
 
- TW5864_INTR_AUD_EOF
 
- TW5864_INTR_BURST
 
- TW5864_INTR_CLR_H
 
- TW5864_INTR_CLR_L
 
- TW5864_INTR_ENABLE_H
 
- TW5864_INTR_ENABLE_L
 
- TW5864_INTR_GPIO
 
- TW5864_INTR_I2C_DONE
 
- TW5864_INTR_JPEG
 
- TW5864_INTR_MV_DSP
 
- TW5864_INTR_OUT_LEVEL
 
- TW5864_INTR_PV_EOF
 
- TW5864_INTR_PV_OVERFLOW
 
- TW5864_INTR_STATUS_H
 
- TW5864_INTR_STATUS_L
 
- TW5864_INTR_TIMER
 
- TW5864_INTR_VIN_LOST
 
- TW5864_INTR_VLC_DONE
 
- TW5864_INTR_VLC_RAM
 
- TW5864_JPEG_MAST_ENB
 
- TW5864_JPEG_REQ_ENB
 
- TW5864_LOAD
 
- TW5864_MASTER_ENB_REG
 
- TW5864_MASTER_MODE
 
- TW5864_MAS_SLICE_END
 
- TW5864_ME_EN
 
- TW5864_ME_MV_VEC
 
- TW5864_ME_MV_VEC1
 
- TW5864_ME_MV_VEC2
 
- TW5864_ME_MV_VEC3
 
- TW5864_ME_MV_VEC4
 
- TW5864_ME_MV_VEC_MAX_OFFSET
 
- TW5864_ME_MV_VEC_START
 
- TW5864_MOTION_SEARCH_ETC
 
- TW5864_MPI_DDR_SEL
 
- TW5864_MPI_DDR_SEL2
 
- TW5864_MPI_DDR_SEL_REG
 
- TW5864_MV
 
- TW5864_MVD_REQ_ENB
 
- TW5864_MVD_TMP_REQ_ENB
 
- TW5864_MVD_VLC_MAST_ENB
 
- TW5864_MV_BK0_FULL
 
- TW5864_MV_BK1_FULL
 
- TW5864_MV_DSP_INTR
 
- TW5864_MV_EOF
 
- TW5864_MV_FLAG_REQ_ENB
 
- TW5864_MV_FLAG_VLD
 
- TW5864_MV_LEN
 
- TW5864_MV_LEN_SHIFT
 
- TW5864_MV_STREAM_BASE_ADDR
 
- TW5864_MV_VECT_VLD
 
- TW5864_NEW_BRST_CMD
 
- TW5864_NORMS
 
- TW5864_PCI_AUD
 
- TW5864_PCI_AUD_FRM_EN
 
- TW5864_PCI_AUD_INTR_ENB
 
- TW5864_PCI_DATA_SEL
 
- TW5864_PCI_DDR_BURST_ENB
 
- TW5864_PCI_FLOW_EN
 
- TW5864_PCI_INF_VERSION
 
- TW5864_PCI_INF_VERSION_SHIFT
 
- TW5864_PCI_INTR_CTL
 
- TW5864_PCI_INTR_STATUS
 
- TW5864_PCI_INTTM_SCALE
 
- TW5864_PCI_JPEG_INTR_ENB
 
- TW5864_PCI_MAST_ENB
 
- TW5864_PCI_PREV_INTR_ENB
 
- TW5864_PCI_PREV_OF_INTR_ENB
 
- TW5864_PCI_PV_CH_EN
 
- TW5864_PCI_PV_CH_STATUS
 
- TW5864_PCI_TAR_BURST_ENB
 
- TW5864_PCI_VLC_BURST_ENB
 
- TW5864_PCI_VLC_INTR_ENB
 
- TW5864_PC_BLOCK_ADPCM_RD_NO
 
- TW5864_PC_BLOCK_ADPCM_RD_NO_MASK
 
- TW5864_PC_BLOCK_ORIG_RD_NO
 
- TW5864_PC_BLOCK_ORIG_RD_NO_MASK
 
- TW5864_PLL_CFG
 
- TW5864_PREV_AND_AU_BUF_FLAG
 
- TW5864_PREV_AND_AU_INTR
 
- TW5864_PREV_BUF_FLAG
 
- TW5864_PREV_EOF_INTR
 
- TW5864_PREV_FRAME_FORMAT_IN
 
- TW5864_PREV_INTR_REG
 
- TW5864_PREV_MAST_ENB
 
- TW5864_PREV_OVERFLOW_ENB
 
- TW5864_PREV_OVERFLOW_INTR
 
- TW5864_PREV_PCI_ENB_CHN
 
- TW5864_PROG_A
 
- TW5864_PROG_B
 
- TW5864_QPEL_EN
 
- TW5864_QUAN_TAB
 
- TW5864_RD_ACK_VLD_MUX
 
- TW5864_REQS_ENABLE
 
- TW5864_RES_TOTAL_BIT
 
- TW5864_RFC_CNT_MAX
 
- TW5864_RFC_CNT_MAX_SHIFT
 
- TW5864_RST_AND_IF_INFO
 
- TW5864_RST_MV_PTR
 
- TW5864_RT_CNTR_CH_FRM
 
- TW5864_RW
 
- TW5864_SENIF_HOR_MIR
 
- TW5864_SENIF_ORG_FRM_PTR1
 
- TW5864_SENIF_ORG_FRM_PTR2
 
- TW5864_SENIF_VER_MIR
 
- TW5864_SEN_EN_CH
 
- TW5864_SINGLE_BUSY
 
- TW5864_SINGLE_ERR
 
- TW5864_SINGLE_PROC
 
- TW5864_SING_ERR_INTR
 
- TW5864_SKIP_EN
 
- TW5864_SLICE
 
- TW5864_SLICE_TOTAL_BIT
 
- TW5864_SPK_ADPCM_EN
 
- TW5864_SPK_ORG_EN
 
- TW5864_SPLL
 
- TW5864_SPLL_CFG
 
- TW5864_SRCH_OPT
 
- TW5864_SRST
 
- TW5864_START_NSLICE
 
- TW5864_SYNC
 
- TW5864_SYNC_ADR_EDGE
 
- TW5864_SYNC_CFG
 
- TW5864_SYSPLL1
 
- TW5864_SYSPLL2
 
- TW5864_SYSPLL3
 
- TW5864_SYSPLL4
 
- TW5864_SYSPLL5
 
- TW5864_SYSPLL_CFG
 
- TW5864_SYSPLL_CP_SEL
 
- TW5864_SYSPLL_CP_SEL_SHIFT
 
- TW5864_SYSPLL_ED_SEL
 
- TW5864_SYSPLL_ICP_SEL
 
- TW5864_SYSPLL_ICP_SEL_SHIFT
 
- TW5864_SYSPLL_IREF
 
- TW5864_SYSPLL_LPF_5PF
 
- TW5864_SYSPLL_LP_X8
 
- TW5864_SYSPLL_LP_X8_SHIFT
 
- TW5864_SYSPLL_M_HI
 
- TW5864_SYSPLL_M_LOW
 
- TW5864_SYSPLL_N_HI
 
- TW5864_SYSPLL_N_LOW
 
- TW5864_SYSPLL_N_LOW_SHIFT
 
- TW5864_SYSPLL_P
 
- TW5864_SYSPLL_PD
 
- TW5864_SYSPLL_P_SHIFT
 
- TW5864_SYSPLL_RST
 
- TW5864_SYSPLL_VCO
 
- TW5864_TCD_CNT_MAX
 
- TW5864_TCD_CNT_MAX_SHIFT
 
- TW5864_TESTLOOP_CHID
 
- TW5864_TESTLOOP_CHID_SHIFT
 
- TW5864_TEST_ADLOOP_EN
 
- TW5864_TIMER_INTR
 
- TW5864_TIMER_INTR_ENB
 
- TW5864_TOTAL_COEF_NO
 
- TW5864_TRAS_CNT_MAX
 
- TW5864_TRIGGER_MODE_H
 
- TW5864_TRIGGER_MODE_L
 
- TW5864_TWR_CNT_MAX
 
- TW5864_TWR_CNT_MAX_SHIFT
 
- TW5864_UNDECLARED_ERROR_FLAGS_0x9218
 
- TW5864_UNDECLARED_H264REV_PART2
 
- TW5864_VLC
 
- TW5864_VLC_A03_DISAB
 
- TW5864_VLC_ADD03_EN
 
- TW5864_VLC_BIT_ALIGN_MASK
 
- TW5864_VLC_BIT_ALIGN_SHIFT
 
- TW5864_VLC_BK0_FULL
 
- TW5864_VLC_BK1_FULL
 
- TW5864_VLC_BUF
 
- TW5864_VLC_BUF_ID
 
- TW5864_VLC_BUF_RDY_MASK
 
- TW5864_VLC_BUF_RDY_SHIFT
 
- TW5864_VLC_BYTE_SWP
 
- TW5864_VLC_CRC_REG
 
- TW5864_VLC_DONE_INTR
 
- TW5864_VLC_DSP_INTR
 
- TW5864_VLC_END_SLICE
 
- TW5864_VLC_INF_SEL
 
- TW5864_VLC_INTRA_CRC_I_REG
 
- TW5864_VLC_INTRA_CRC_O_REG
 
- TW5864_VLC_LENGTH
 
- TW5864_VLC_MAX_LENGTH
 
- TW5864_VLC_OUT_EDGE
 
- TW5864_VLC_OVFL_CNTL
 
- TW5864_VLC_PAR_CRC_REG
 
- TW5864_VLC_PAR_I_REG
 
- TW5864_VLC_PAR_LENGTH_REG
 
- TW5864_VLC_PAR_O_REG
 
- TW5864_VLC_PCI_SEL
 
- TW5864_VLC_RD
 
- TW5864_VLC_RD_BRST
 
- TW5864_VLC_RD_MEM
 
- TW5864_VLC_SLICE_END
 
- TW5864_VLC_SLICE_QP
 
- TW5864_VLC_STREAM_BASE_ADDR
 
- TW5864_VLC_STREAM_CRC
 
- TW5864_VLC_STREAM_LEN_MASK
 
- TW5864_VLC_STREAM_LEN_SHIFT
 
- TW5864_VLC_STREAM_MEM
 
- TW5864_VLC_STREAM_MEM_MAX_OFFSET
 
- TW5864_VLC_STREAM_MEM_START
 
- TW5864_VLC_STRM_REQ_ENB
 
- TW5864_VLC_STR_DELAY
 
- TW5864_VLC_STR_DELAY_SHIFT
 
- TW5864_VLC_VLD
 
- TW5864_WRITE_FLAG
 
- TW6800
 
- TW6801
 
- TW6804
 
- TW686X_AUDIO_PAGE_MAX
 
- TW686X_AUDIO_PERIODS_MAX
 
- TW686X_AUDIO_PERIODS_MIN
 
- TW686X_DEF_PHASE_REF
 
- TW686X_DMA_MODE_CONTIG
 
- TW686X_DMA_MODE_MEMCPY
 
- TW686X_DMA_MODE_SG
 
- TW686X_FIELD_MODE
 
- TW686X_FIFO_ERROR
 
- TW686X_FRAME_MODE
 
- TW686X_INPUTS_PER_CH
 
- TW686X_MAX_FPS
 
- TW686X_MAX_SG_DESC_COUNT
 
- TW686X_MAX_SG_ENTRY_SIZE
 
- TW686X_SG_MODE
 
- TW686X_SG_TABLE_SIZE
 
- TW686X_STD_NTSC_443
 
- TW686X_STD_NTSC_M
 
- TW686X_STD_PAL
 
- TW686X_STD_PAL_60
 
- TW686X_STD_PAL_CN
 
- TW686X_STD_PAL_M
 
- TW686X_STD_SECAM
 
- TW686X_VIDEO_HEIGHT
 
- TW686X_VIDEO_WIDTH
 
- TW686X_VIDSTAT_HLOCK
 
- TW686X_VIDSTAT_VDLOSS
 
- TW68_ACCNTL
 
- TW68_ACKI1
 
- TW68_ACKI2
 
- TW68_ACKI3
 
- TW68_ACKN1
 
- TW68_ACKN2
 
- TW68_ACKN3
 
- TW68_ACNTL
 
- TW68_AGCGAIN
 
- TW68_BOARD_GENERIC_6802
 
- TW68_BOARD_NOAUTO
 
- TW68_BOARD_UNKNOWN
 
- TW68_BRIGHT
 
- TW68_CAP_CTL
 
- TW68_CCVALID
 
- TW68_CC_DATA
 
- TW68_CHROMAGVAL
 
- TW68_CKILL
 
- TW68_CLCNTL1
 
- TW68_CLMD
 
- TW68_CLMPG
 
- TW68_CLMPL
 
- TW68_CNTRL1
 
- TW68_CNTRL2
 
- TW68_COMB
 
- TW68_CONTRAST
 
- TW68_CORING
 
- TW68_CROP_HI
 
- TW68_DET50
 
- TW68_DMAC
 
- TW68_DMAPERR
 
- TW68_DMAPI
 
- TW68_DMAP_EN
 
- TW68_DMAP_EXE
 
- TW68_DMAP_PP
 
- TW68_DMAP_SA
 
- TW68_F2CNT
 
- TW68_F2CROP_HI
 
- TW68_F2HACTIVE_LO
 
- TW68_F2HDELAY_LO
 
- TW68_F2HSCALE_LO
 
- TW68_F2SCALE_HI
 
- TW68_F2VACTIVE_LO
 
- TW68_F2VDELAY_LO
 
- TW68_F2VSCALE_LO
 
- TW68_FDMIS
 
- TW68_FFERR
 
- TW68_FFOF
 
- TW68_FIELD
 
- TW68_FIFO_EN
 
- TW68_FLOCK
 
- TW68_GPDATA
 
- TW68_GPINT
 
- TW68_GPIOC
 
- TW68_GPOE
 
- TW68_HACTIVE_LO
 
- TW68_HDELAY_LO
 
- TW68_HFREF
 
- TW68_HLOCK
 
- TW68_HSCALE_LO
 
- TW68_HSYNC
 
- TW68_HUE
 
- TW68_I2C_INTS
 
- TW68_I2C_RST
 
- TW68_IAGC
 
- TW68_IDCNTL
 
- TW68_INFORM
 
- TW68_INPUT_MAX
 
- TW68_INTMASK
 
- TW68_INTSTAT
 
- TW68_LDLY
 
- TW68_LOOP
 
- TW68_LRDIV
 
- TW68_MAXBOARDS
 
- TW68_MISC1
 
- TW68_MISC2
 
- TW68_MISSCNT
 
- TW68_MVSN
 
- TW68_NORMS
 
- TW68_OPFORM
 
- TW68_PABORT
 
- TW68_PCLAMP
 
- TW68_PEAKWT
 
- TW68_PPERR
 
- TW68_RDLEN
 
- TW68_RESERV2
 
- TW68_RESERV3
 
- TW68_SAT_U
 
- TW68_SAT_V
 
- TW68_SBCLK
 
- TW68_SBDEV
 
- TW68_SBDONE
 
- TW68_SBDONE2
 
- TW68_SBERR
 
- TW68_SBERR2
 
- TW68_SBMODE
 
- TW68_SBMODE_B
 
- TW68_SBRW
 
- TW68_SBRW_B
 
- TW68_SBUSC
 
- TW68_SBUSRD
 
- TW68_SBUSSD
 
- TW68_SBUS_TRIG
 
- TW68_SCALE_HI
 
- TW68_SDIV
 
- TW68_SDT
 
- TW68_SDTR
 
- TW68_SHARP2
 
- TW68_SHARPNESS
 
- TW68_SLOCK
 
- TW68_SSCLK
 
- TW68_SSCLK_B
 
- TW68_SSDAT
 
- TW68_SSDAT_B
 
- TW68_STATUS1
 
- TW68_STATUS2
 
- TW68_SUBSYS
 
- TW68_SYNCT
 
- TW68_TESTREG
 
- TW68_VACTIVE_LO
 
- TW68_VBIC
 
- TW68_VBICNTL
 
- TW68_VBIINST
 
- TW68_VCNTL1
 
- TW68_VCNTL2
 
- TW68_VDELAY_LO
 
- TW68_VDLOSS
 
- TW68_VID_INTS
 
- TW68_VID_INTSX
 
- TW68_VLOCK
 
- TW68_VSCALE_LO
 
- TW68_VSCTL
 
- TW68_VSHARP
 
- TW68_WDLEN
 
- TW68_WREN
 
- TW68_WREN_B
 
- TW9910_MPO_DET50
 
- TW9910_MPO_FIELD
 
- TW9910_MPO_HLOCK
 
- TW9910_MPO_MONO
 
- TW9910_MPO_RTCO
 
- TW9910_MPO_SLOCK
 
- TW9910_MPO_VLOCK
 
- TW9910_MPO_VLOSS
 
- TWAKEUP
 
- TWCR_TOTALH
 
- TWCR_TOTALW
 
- TWCS_MASK
 
- TWC_FRAMEDONE
 
- TWC_FRAMEDONE_ENA
 
- TWC_FRAMEDONE_ENA_MASK
 
- TWC_FRAMEDONE_LEVEL
 
- TWC_FRAMEDONE_LEVEL_MASK
 
- TWC_FRAMEDONE_MASK
 
- TWDEBUG
 
- TWD_TIMER_CONTROL
 
- TWD_TIMER_CONTROL_ENABLE
 
- TWD_TIMER_CONTROL_IT_ENABLE
 
- TWD_TIMER_CONTROL_ONESHOT
 
- TWD_TIMER_CONTROL_PERIODIC
 
- TWD_TIMER_COUNTER
 
- TWD_TIMER_INTSTAT
 
- TWD_TIMER_LOAD
 
- TWD_WDOG_CONTROL
 
- TWD_WDOG_COUNTER
 
- TWD_WDOG_DISABLE
 
- TWD_WDOG_INTSTAT
 
- TWD_WDOG_LOAD
 
- TWD_WDOG_RESETSTAT
 
- TWEAK_SIZE
 
- TWELVE_BYTE_CMD
 
- TWENTY_YEARS
 
- TWHI_MAX
 
- TWHI_MIN
 
- TWHR2_AND_WE_2_RE
 
- TWHR2_AND_WE_2_RE__TWHR2
 
- TWHR2_AND_WE_2_RE__WE_2_RE
 
- TWICE
 
- TWIDJOY_MAX_LENGTH
 
- TWINHAN_TECHNOLOGIES
 
- TWIN_CLR_TMR1
 
- TWIN_CLR_TMR2
 
- TWIN_DMA_CFG
 
- TWIN_DMA_CLR_FF
 
- TWIN_DMA_FDX_T1R3
 
- TWIN_DMA_FDX_T3R1
 
- TWIN_DMA_HDX_R1
 
- TWIN_DMA_HDX_R3
 
- TWIN_DMA_HDX_T1
 
- TWIN_DMA_HDX_T3
 
- TWIN_DTRA_ON
 
- TWIN_DTRB_ON
 
- TWIN_EI
 
- TWIN_EXTCLKA
 
- TWIN_EXTCLKB
 
- TWIN_INT_MSK
 
- TWIN_INT_REG
 
- TWIN_LOOPA_ON
 
- TWIN_LOOPB_ON
 
- TWIN_SCC_MSK
 
- TWIN_SERIAL_CFG
 
- TWIN_SPARE_1
 
- TWIN_SPARE_2
 
- TWIN_TMR1_MSK
 
- TWIN_TMR2_MSK
 
- TWI_CLKDIV
 
- TWI_DEVICE
 
- TWI_IRQEN
 
- TWI_IRQEN_ANACK
 
- TWI_IRQEN_COMPL
 
- TWI_IRQEN_DNACK
 
- TWI_IRQ_ANACK
 
- TWI_IRQ_COMPL
 
- TWI_IRQ_DNACK
 
- TWI_IRQ_RX
 
- TWI_IRQ_TX
 
- TWI_NOSTOP
 
- TWI_SOFT_RESET
 
- TWI_TRANSFER
 
- TWL4030_ACCHGOV
 
- TWL4030_ADCL_EN
 
- TWL4030_ADCR_EN
 
- TWL4030_ADC_CHANNEL
 
- TWL4030_ADJUSTABLE_LDO
 
- TWL4030_ADJUSTABLE_SMPS
 
- TWL4030_AIF_EN
 
- TWL4030_AIF_FORMAT
 
- TWL4030_AIF_FORMAT_CODEC
 
- TWL4030_AIF_FORMAT_LEFT
 
- TWL4030_AIF_FORMAT_RIGHT
 
- TWL4030_AIF_FORMAT_TDM
 
- TWL4030_AIF_SLAVE_EN
 
- TWL4030_AIF_TRI_EN
 
- TWL4030_ALLOW_UNSUPPORTED
 
- TWL4030_APLL_EN
 
- TWL4030_APLL_INFREQ
 
- TWL4030_APLL_INFREQ_19200KHZ
 
- TWL4030_APLL_INFREQ_26000KHZ
 
- TWL4030_APLL_INFREQ_38400KHZ
 
- TWL4030_APLL_RATE
 
- TWL4030_APLL_RATE_11025
 
- TWL4030_APLL_RATE_12000
 
- TWL4030_APLL_RATE_16000
 
- TWL4030_APLL_RATE_22050
 
- TWL4030_APLL_RATE_24000
 
- TWL4030_APLL_RATE_32000
 
- TWL4030_APLL_RATE_44100
 
- TWL4030_APLL_RATE_48000
 
- TWL4030_APLL_RATE_8000
 
- TWL4030_APLL_RATE_96000
 
- TWL4030_ARXL1_VRX_EN
 
- TWL4030_ARXL2_EN
 
- TWL4030_ARXR1_EN
 
- TWL4030_ARXR2_EN
 
- TWL4030_ATXL1_EN
 
- TWL4030_ATXL2_VTXL_EN
 
- TWL4030_ATXR1_EN
 
- TWL4030_ATXR2_VTXR_EN
 
- TWL4030_AUDIO_CELLS
 
- TWL4030_AUDIO_RES_APLL
 
- TWL4030_AUDIO_RES_MAX
 
- TWL4030_AUDIO_RES_POWER
 
- TWL4030_AUXL_EN
 
- TWL4030_AUXR_EN
 
- TWL4030_AVADC_CLK_PRIORITY
 
- TWL4030_BASEADD_AUDIO_VOICE
 
- TWL4030_BASEADD_BACKUP
 
- TWL4030_BASEADD_GPIO
 
- TWL4030_BASEADD_INT
 
- TWL4030_BASEADD_INTBR
 
- TWL4030_BASEADD_INTERRUPTS
 
- TWL4030_BASEADD_KEYPAD
 
- TWL4030_BASEADD_LED
 
- TWL4030_BASEADD_MADC
 
- TWL4030_BASEADD_MAIN_CHARGE
 
- TWL4030_BASEADD_PIH
 
- TWL4030_BASEADD_PM_MASTER
 
- TWL4030_BASEADD_PM_RECEIVER
 
- TWL4030_BASEADD_PRECHARGE
 
- TWL4030_BASEADD_PWM
 
- TWL4030_BASEADD_RTC
 
- TWL4030_BASEADD_SECURED_REG
 
- TWL4030_BASEADD_TEST
 
- TWL4030_BASEADD_USB
 
- TWL4030_BATSTS
 
- TWL4030_BATSTSMCHG
 
- TWL4030_BATSTSPCHG
 
- TWL4030_BBCHEN
 
- TWL4030_BBISEL_1000uA
 
- TWL4030_BBISEL_150uA
 
- TWL4030_BBISEL_25uA
 
- TWL4030_BBISEL_500uA
 
- TWL4030_BBISEL_MASK
 
- TWL4030_BBSEL_2V5
 
- TWL4030_BBSEL_3V0
 
- TWL4030_BBSEL_3V1
 
- TWL4030_BBSEL_3V2
 
- TWL4030_BBSEL_MASK
 
- TWL4030_BB_CFG
 
- TWL4030_BCIAUTOAC
 
- TWL4030_BCIAUTOUSB
 
- TWL4030_BCIAUTOWEN
 
- TWL4030_BCICTL1
 
- TWL4030_BCIICHG
 
- TWL4030_BCIIREF1
 
- TWL4030_BCIIREF2
 
- TWL4030_BCIMDEN
 
- TWL4030_BCIMDKEY
 
- TWL4030_BCIMFEN3
 
- TWL4030_BCIMFKEY
 
- TWL4030_BCIMFSTS1
 
- TWL4030_BCIMFSTS3
 
- TWL4030_BCIMFSTS4
 
- TWL4030_BCIMFTH8
 
- TWL4030_BCIMFTH9
 
- TWL4030_BCIMSTATEC
 
- TWL4030_BCIVAC
 
- TWL4030_BCIVBUS
 
- TWL4030_BCIWDKEY
 
- TWL4030_BCI_BCICTL1
 
- TWL4030_BCI_CGAIN
 
- TWL4030_BCI_ITHEN
 
- TWL4030_BCI_ITHSENS
 
- TWL4030_BCI_MESBAT
 
- TWL4030_BCI_TYPEN
 
- TWL4030_CACHEREGNUM
 
- TWL4030_CGAIN
 
- TWL4030_CKMIC_EN
 
- TWL4030_CLASS_ID
 
- TWL4030_CLK256FS_EN
 
- TWL4030_CLK64_EN
 
- TWL4030_CNCL_OFFSET_START
 
- TWL4030_CODECPDZ
 
- TWL4030_CONFIG_DONE
 
- TWL4030_CORE_NR_IRQS
 
- TWL4030_CVENAC
 
- TWL4030_DATA_WIDTH
 
- TWL4030_DATA_WIDTH_16S_16W
 
- TWL4030_DATA_WIDTH_32S_16W
 
- TWL4030_DATA_WIDTH_32S_24W
 
- TWL4030_DCDC_GLOBAL_CFG
 
- TWL4030_DIGMIC0_EN
 
- TWL4030_DIGMIC1_EN
 
- TWL4030_DIGMIC_LR_SWAP_EN
 
- TWL4030_EAR_GAIN
 
- TWL4030_EXTMUTE
 
- TWL4030_FIXED_LDO
 
- TWL4030_FMLOOP_EN
 
- TWL4030_FORMATS
 
- TWL4030_GPBR1_MADC_HFCLK_EN
 
- TWL4030_GPBR1_REG
 
- TWL4030_GPIO6_PWM0_MUTE
 
- TWL4030_GPIO6_PWM0_MUTE_MASK
 
- TWL4030_GPIO6_PWM0_MUTE_PWM0
 
- TWL4030_GPIO7_VIBRASYNC_PWM1_MASK
 
- TWL4030_GPIO7_VIBRASYNC_PWM1_PWM1
 
- TWL4030_GPIO_MAX
 
- TWL4030_HF_CTL_HB_EN
 
- TWL4030_HF_CTL_LOOP_EN
 
- TWL4030_HF_CTL_RAMP_EN
 
- TWL4030_HF_CTL_REF_EN
 
- TWL4030_HSL_GAIN
 
- TWL4030_HSL_GAIN_0DB
 
- TWL4030_HSL_GAIN_MINUS_6DB
 
- TWL4030_HSL_GAIN_PLUS_6DB
 
- TWL4030_HSL_GAIN_PWR_DOWN
 
- TWL4030_HSMICBIAS_EN
 
- TWL4030_HSMIC_EN
 
- TWL4030_HSR_GAIN
 
- TWL4030_HSR_GAIN_0DB
 
- TWL4030_HSR_GAIN_MINUS_6DB
 
- TWL4030_HSR_GAIN_PLUS_6DB
 
- TWL4030_HSR_GAIN_PWR_DOWN
 
- TWL4030_ICHGEOC
 
- TWL4030_ICHGHIGH
 
- TWL4030_ICHGLOW
 
- TWL4030_INTERRUPTS_BCIEDR1
 
- TWL4030_INTERRUPTS_BCIEDR2
 
- TWL4030_INTERRUPTS_BCIEDR3
 
- TWL4030_INTERRUPTS_BCIIMR1A
 
- TWL4030_INTERRUPTS_BCIIMR1B
 
- TWL4030_INTERRUPTS_BCIIMR2A
 
- TWL4030_INTERRUPTS_BCIIMR2B
 
- TWL4030_INTERRUPTS_BCIISR1A
 
- TWL4030_INTERRUPTS_BCIISR1B
 
- TWL4030_INTERRUPTS_BCIISR2A
 
- TWL4030_INTERRUPTS_BCIISR2B
 
- TWL4030_INTERRUPTS_BCISIHCTRL
 
- TWL4030_INTERRUPTS_BCISIR1
 
- TWL4030_INTERRUPTS_BCISIR2
 
- TWL4030_INT_PWR_EDR
 
- TWL4030_INT_PWR_EDR1
 
- TWL4030_INT_PWR_EDR2
 
- TWL4030_INT_PWR_IMR1
 
- TWL4030_INT_PWR_IMR2
 
- TWL4030_INT_PWR_ISR1
 
- TWL4030_INT_PWR_ISR2
 
- TWL4030_INT_PWR_SIH_CTRL
 
- TWL4030_INT_PWR_SIR
 
- TWL4030_KEYMAP_SIZE
 
- TWL4030_KEYPAD_KEYP_EDR
 
- TWL4030_KEYPAD_KEYP_IMR1
 
- TWL4030_KEYPAD_KEYP_IMR2
 
- TWL4030_KEYPAD_KEYP_ISR1
 
- TWL4030_KEYPAD_KEYP_ISR2
 
- TWL4030_KEYPAD_KEYP_SIH_CTRL
 
- TWL4030_KEYPAD_KEYP_SIR
 
- TWL4030_LEDEN_REG
 
- TWL4030_LEDXON
 
- TWL4030_LEDXPWM
 
- TWL4030_LED_LEDEN_REG
 
- TWL4030_LED_MAX
 
- TWL4030_LED_PINS
 
- TWL4030_LED_TOGGLE
 
- TWL4030_MADC_ADCIN0
 
- TWL4030_MADC_ADCIN1
 
- TWL4030_MADC_ADCIN10
 
- TWL4030_MADC_ADCIN11
 
- TWL4030_MADC_ADCIN12
 
- TWL4030_MADC_ADCIN13
 
- TWL4030_MADC_ADCIN14
 
- TWL4030_MADC_ADCIN15
 
- TWL4030_MADC_ADCIN2
 
- TWL4030_MADC_ADCIN3
 
- TWL4030_MADC_ADCIN4
 
- TWL4030_MADC_ADCIN5
 
- TWL4030_MADC_ADCIN6
 
- TWL4030_MADC_ADCIN7
 
- TWL4030_MADC_ADCIN8
 
- TWL4030_MADC_ADCIN9
 
- TWL4030_MADC_BTEMP
 
- TWL4030_MADC_BUSY
 
- TWL4030_MADC_CTRL1
 
- TWL4030_MADC_CTRL2
 
- TWL4030_MADC_CTRL_SW1
 
- TWL4030_MADC_CTRL_SW2
 
- TWL4030_MADC_EDR
 
- TWL4030_MADC_EOC_SW
 
- TWL4030_MADC_GPCH0_LSB
 
- TWL4030_MADC_ICHG
 
- TWL4030_MADC_IMR1
 
- TWL4030_MADC_IMR2
 
- TWL4030_MADC_IRQ_ONESHOT
 
- TWL4030_MADC_IRQ_REARM
 
- TWL4030_MADC_ISR1
 
- TWL4030_MADC_ISR2
 
- TWL4030_MADC_MADCON
 
- TWL4030_MADC_MAX_CHANNELS
 
- TWL4030_MADC_NUM_METHODS
 
- TWL4030_MADC_RT
 
- TWL4030_MADC_RTAVERAGE_LSB
 
- TWL4030_MADC_RTCH0_LSB
 
- TWL4030_MADC_RTSELECT_LSB
 
- TWL4030_MADC_SIH_CTRL
 
- TWL4030_MADC_SIR
 
- TWL4030_MADC_SW1
 
- TWL4030_MADC_SW1AVERAGE_LSB
 
- TWL4030_MADC_SW1SELECT_LSB
 
- TWL4030_MADC_SW2
 
- TWL4030_MADC_SW2AVERAGE_LSB
 
- TWL4030_MADC_SW2SELECT_LSB
 
- TWL4030_MADC_SW_START
 
- TWL4030_MADC_VBAT
 
- TWL4030_MADC_VBKB
 
- TWL4030_MADC_VBUS
 
- TWL4030_MADC_VCHG
 
- TWL4030_MADC_WAIT
 
- TWL4030_MAINMIC_EN
 
- TWL4030_MAX_COLS
 
- TWL4030_MAX_ROWS
 
- TWL4030_MICAMPL_EN
 
- TWL4030_MICAMPR_EN
 
- TWL4030_MICBIAS1_CTL
 
- TWL4030_MICBIAS1_EN
 
- TWL4030_MICBIAS2_CTL
 
- TWL4030_MICBIAS2_EN
 
- TWL4030_MODULE_AUDIO_VOICE
 
- TWL4030_MODULE_BACKUP
 
- TWL4030_MODULE_GPIO
 
- TWL4030_MODULE_INT
 
- TWL4030_MODULE_INTBR
 
- TWL4030_MODULE_INTERRUPTS
 
- TWL4030_MODULE_INT_PWR
 
- TWL4030_MODULE_KEYPAD
 
- TWL4030_MODULE_KEYPAD_KEYP
 
- TWL4030_MODULE_LAST
 
- TWL4030_MODULE_LED
 
- TWL4030_MODULE_MADC
 
- TWL4030_MODULE_PRECHARGE
 
- TWL4030_MODULE_TEST
 
- TWL4030_MSTATEC_AC
 
- TWL4030_MSTATEC_COMPLETE1
 
- TWL4030_MSTATEC_COMPLETE4
 
- TWL4030_MSTATEC_MASK
 
- TWL4030_MSTATEC_QUICK1
 
- TWL4030_MSTATEC_QUICK7
 
- TWL4030_MSTATEC_USB
 
- TWL4030_OFFSET_CNCL_SEL
 
- TWL4030_OFFSET_CNCL_SEL_ALL
 
- TWL4030_OFFSET_CNCL_SEL_ARX1
 
- TWL4030_OFFSET_CNCL_SEL_ARX2
 
- TWL4030_OFFSET_CNCL_SEL_VRX
 
- TWL4030_OF_MATCH
 
- TWL4030_OPTION_1
 
- TWL4030_OPTION_2
 
- TWL4030_OPT_MODE
 
- TWL4030_OUTPUT_PGA
 
- TWL4030_PMBR1_REG
 
- TWL4030_PM_MASTER_BACKUP_MISC_CFG
 
- TWL4030_PM_MASTER_BACKUP_MISC_STS
 
- TWL4030_PM_MASTER_BACKUP_MISC_TST
 
- TWL4030_PM_MASTER_BOOT_BCI
 
- TWL4030_PM_MASTER_CFG_BOOT
 
- TWL4030_PM_MASTER_CFG_P123_TRANSITION
 
- TWL4030_PM_MASTER_CFG_P1_TRANSITION
 
- TWL4030_PM_MASTER_CFG_P2_TRANSITION
 
- TWL4030_PM_MASTER_CFG_P3_TRANSITION
 
- TWL4030_PM_MASTER_CFG_PWRANA1
 
- TWL4030_PM_MASTER_CFG_PWRANA2
 
- TWL4030_PM_MASTER_GLOBAL_TST
 
- TWL4030_PM_MASTER_KEY_CFG1
 
- TWL4030_PM_MASTER_KEY_CFG2
 
- TWL4030_PM_MASTER_KEY_TST1
 
- TWL4030_PM_MASTER_KEY_TST2
 
- TWL4030_PM_MASTER_MEMORY_ADDRESS
 
- TWL4030_PM_MASTER_MEMORY_DATA
 
- TWL4030_PM_MASTER_P1_SW_EVENTS
 
- TWL4030_PM_MASTER_P2_SW_EVENTS
 
- TWL4030_PM_MASTER_P3_SW_EVENTS
 
- TWL4030_PM_MASTER_PB_CFG
 
- TWL4030_PM_MASTER_PB_WORD_LSB
 
- TWL4030_PM_MASTER_PB_WORD_MSB
 
- TWL4030_PM_MASTER_PROTECT_KEY
 
- TWL4030_PM_MASTER_SEQ_ADD_A2S
 
- TWL4030_PM_MASTER_SEQ_ADD_A2W
 
- TWL4030_PM_MASTER_SEQ_ADD_P2A
 
- TWL4030_PM_MASTER_SEQ_ADD_S2A12
 
- TWL4030_PM_MASTER_SEQ_ADD_S2A3
 
- TWL4030_PM_MASTER_SEQ_ADD_W2P
 
- TWL4030_PM_MASTER_SEQ_ADD_WARM
 
- TWL4030_PM_MASTER_SHUNDAN
 
- TWL4030_PM_MASTER_STS_BOOT
 
- TWL4030_PM_MASTER_STS_HW_CONDITIONS
 
- TWL4030_PM_MASTER_STS_P123_STATE
 
- TWL4030_PRECKL_GAIN
 
- TWL4030_PRECKR_GAIN
 
- TWL4030_PREDL_GAIN
 
- TWL4030_PREDR_GAIN
 
- TWL4030_PWMAOFF_REG
 
- TWL4030_PWMAON_REG
 
- TWL4030_PWMA_REG
 
- TWL4030_PWMBOFF_REG
 
- TWL4030_PWMBON_REG
 
- TWL4030_PWMXCLK_ENABLE
 
- TWL4030_PWMX_BITS
 
- TWL4030_PWMX_ENABLE
 
- TWL4030_PWM_TOGGLE
 
- TWL4030_PWR_NR_IRQS
 
- TWL4030_RAMP_DELAY
 
- TWL4030_RAMP_DELAY_1291MS
 
- TWL4030_RAMP_DELAY_161MS
 
- TWL4030_RAMP_DELAY_20MS
 
- TWL4030_RAMP_DELAY_2581MS
 
- TWL4030_RAMP_DELAY_323MS
 
- TWL4030_RAMP_DELAY_40MS
 
- TWL4030_RAMP_DELAY_645MS
 
- TWL4030_RAMP_DELAY_81MS
 
- TWL4030_RAMP_EN
 
- TWL4030_RATES
 
- TWL4030_REG_ADCMICSEL
 
- TWL4030_REG_ALC_CTL
 
- TWL4030_REG_ALC_SET1
 
- TWL4030_REG_ALC_SET2
 
- TWL4030_REG_ANAMICL
 
- TWL4030_REG_ANAMICR
 
- TWL4030_REG_ANAMIC_GAIN
 
- TWL4030_REG_APLL_CTL
 
- TWL4030_REG_ARX2VTXPGA
 
- TWL4030_REG_ARXL1PGA
 
- TWL4030_REG_ARXL1_APGA_CTL
 
- TWL4030_REG_ARXL2PGA
 
- TWL4030_REG_ARXL2_APGA_CTL
 
- TWL4030_REG_ARXR1PGA
 
- TWL4030_REG_ARXR1_APGA_CTL
 
- TWL4030_REG_ARXR2PGA
 
- TWL4030_REG_ARXR2_APGA_CTL
 
- TWL4030_REG_ATX2ARXPGA
 
- TWL4030_REG_ATXL1PGA
 
- TWL4030_REG_ATXR1PGA
 
- TWL4030_REG_AUDIO_IF
 
- TWL4030_REG_AVADC_CTL
 
- TWL4030_REG_AVDAC_CTL
 
- TWL4030_REG_AVTXL2PGA
 
- TWL4030_REG_AVTXR2PGA
 
- TWL4030_REG_BOOST_CTL
 
- TWL4030_REG_BTPGA
 
- TWL4030_REG_BTSTPGA
 
- TWL4030_REG_BT_IF
 
- TWL4030_REG_CODEC_MODE
 
- TWL4030_REG_DIGMIXING
 
- TWL4030_REG_DTMF_CTL
 
- TWL4030_REG_DTMF_FREQSEL
 
- TWL4030_REG_DTMF_PGA_CTL1
 
- TWL4030_REG_DTMF_PGA_CTL2
 
- TWL4030_REG_DTMF_TONEXT1H
 
- TWL4030_REG_DTMF_TONEXT1L
 
- TWL4030_REG_DTMF_TONEXT2H
 
- TWL4030_REG_DTMF_TONEXT2L
 
- TWL4030_REG_DTMF_TONOFF
 
- TWL4030_REG_DTMF_WANONOFF
 
- TWL4030_REG_EAR_CTL
 
- TWL4030_REG_GPBR1
 
- TWL4030_REG_HFL_CTL
 
- TWL4030_REG_HFR_CTL
 
- TWL4030_REG_HS_GAIN_SET
 
- TWL4030_REG_HS_POPN_SET
 
- TWL4030_REG_HS_SEL
 
- TWL4030_REG_I2S_RX_SCRAMBLE_H
 
- TWL4030_REG_I2S_RX_SCRAMBLE_L
 
- TWL4030_REG_I2S_RX_SCRAMBLE_M
 
- TWL4030_REG_MICBIAS_CTL
 
- TWL4030_REG_MISC_SET_1
 
- TWL4030_REG_MISC_SET_2
 
- TWL4030_REG_OPTION
 
- TWL4030_REG_PCMBTMUX
 
- TWL4030_REG_PRECKL_CTL
 
- TWL4030_REG_PRECKR_CTL
 
- TWL4030_REG_PREDL_CTL
 
- TWL4030_REG_PREDR_CTL
 
- TWL4030_REG_RX_PATH_SEL
 
- TWL4030_REG_SOFTVOL_CTL
 
- TWL4030_REG_UNKNOWN
 
- TWL4030_REG_VAUX1
 
- TWL4030_REG_VAUX2
 
- TWL4030_REG_VAUX2_4030
 
- TWL4030_REG_VAUX3
 
- TWL4030_REG_VAUX4
 
- TWL4030_REG_VDAC
 
- TWL4030_REG_VDD1
 
- TWL4030_REG_VDD2
 
- TWL4030_REG_VDL_APGA_CTL
 
- TWL4030_REG_VIBRA_CTL
 
- TWL4030_REG_VIBRA_PWM_SET
 
- TWL4030_REG_VIBRA_SET
 
- TWL4030_REG_VINTANA1
 
- TWL4030_REG_VINTANA2
 
- TWL4030_REG_VINTDIG
 
- TWL4030_REG_VIO
 
- TWL4030_REG_VMMC1
 
- TWL4030_REG_VMMC2
 
- TWL4030_REG_VOICE_IF
 
- TWL4030_REG_VPLL1
 
- TWL4030_REG_VPLL2
 
- TWL4030_REG_VRX2ARXPGA
 
- TWL4030_REG_VRXPGA
 
- TWL4030_REG_VSIM
 
- TWL4030_REG_VSTPGA
 
- TWL4030_REG_VUSB1V5
 
- TWL4030_REG_VUSB1V8
 
- TWL4030_REG_VUSB3V1
 
- TWL4030_RESCONFIG_UNDEF
 
- TWL4030_ROW_SHIFT
 
- TWL4030_SCRAMBLE_EN
 
- TWL4030_SEL_16K
 
- TWL4030_SIH_CTRL_COR_MASK
 
- TWL4030_SIH_CTRL_EXCLEN_MASK
 
- TWL4030_SIH_CTRL_PENDDIS_MASK
 
- TWL4030_SLEEP_SCRIPT
 
- TWL4030_SMOOTH_ANAVOL_EN
 
- TWL4030_STS_USB_ID
 
- TWL4030_STS_VBUS
 
- TWL4030_SUBMIC_EN
 
- TWL4030_TBATOR1
 
- TWL4030_TBATOR2
 
- TWL4030_TMOVF
 
- TWL4030_TX1IN_SEL
 
- TWL4030_TX2IN_SEL
 
- TWL4030_USBFASTMCHG
 
- TWL4030_USB_CARKIT_ANA_CTRL
 
- TWL4030_USB_SEL_MADC_MCPC
 
- TWL4030_VAUX1_DEDICATED
 
- TWL4030_VAUX1_DEV_GRP
 
- TWL4030_VAUX2
 
- TWL4030_VAUX2_DEDICATED
 
- TWL4030_VAUX2_DEV_GRP
 
- TWL4030_VAUX3_DEDICATED
 
- TWL4030_VAUX3_DEV_GRP
 
- TWL4030_VBATLVL
 
- TWL4030_VBATOV
 
- TWL4030_VBUSOV
 
- TWL4030_VDAC_DEDICATED
 
- TWL4030_VDAC_DEV_GRP
 
- TWL4030_VIBRA_AUDIO_SEL_L1
 
- TWL4030_VIBRA_AUDIO_SEL_L2
 
- TWL4030_VIBRA_AUDIO_SEL_R1
 
- TWL4030_VIBRA_AUDIO_SEL_R2
 
- TWL4030_VIBRA_DIR
 
- TWL4030_VIBRA_DIR_SEL
 
- TWL4030_VIBRA_EN
 
- TWL4030_VIBRA_SEL
 
- TWL4030_VIF_DIN_EN
 
- TWL4030_VIF_DOUT_EN
 
- TWL4030_VIF_EN
 
- TWL4030_VIF_FORMAT
 
- TWL4030_VIF_SLAVE_EN
 
- TWL4030_VIF_SUB_EN
 
- TWL4030_VIF_SWAP
 
- TWL4030_VIF_TRI_EN
 
- TWL4030_VMID_EN
 
- TWL4030_WAKEUP12_SCRIPT
 
- TWL4030_WAKEUP3_SCRIPT
 
- TWL4030_WATCHDOG_CFG_REG_OFFS
 
- TWL4030_WOVF
 
- TWL4030_WRST_SCRIPT
 
- TWL5030_REV_1_0
 
- TWL5030_REV_1_1
 
- TWL5030_REV_1_2
 
- TWL5031
 
- TWL5031_ACCEDR1
 
- TWL5031_ACCIMR1
 
- TWL5031_ACCIMR2
 
- TWL5031_ACCISR1
 
- TWL5031_ACCISR2
 
- TWL5031_ACCSIHCTRL
 
- TWL5031_ACCSIR
 
- TWL5031_ACIIDR_LSB
 
- TWL5031_ACIIDR_MSB
 
- TWL5031_ACIIMR_LSB
 
- TWL5031_ACIIMR_MSB
 
- TWL5031_BASEADD_ACCESSORY
 
- TWL5031_BASEADD_INTERRUPTS
 
- TWL5031_INTERRUPTS_BCIEDR1
 
- TWL5031_INTERRUPTS_BCIEDR2
 
- TWL5031_INTERRUPTS_BCIIMR1
 
- TWL5031_INTERRUPTS_BCIIMR2
 
- TWL5031_INTERRUPTS_BCIISR1
 
- TWL5031_INTERRUPTS_BCIISR2
 
- TWL5031_INTERRUPTS_BCISIHCTRL
 
- TWL5031_INTERRUPTS_BCISIR
 
- TWL5031_MODULE_ACCESSORY
 
- TWL5031_MODULE_INTERRUPTS
 
- TWL6030_ADJUSTABLE_LDO
 
- TWL6030_ADJUSTABLE_SMPS
 
- TWL6030_BACKUP_REG
 
- TWL6030_BASEADD_AUDIO
 
- TWL6030_BASEADD_AUX
 
- TWL6030_BASEADD_CHARGER
 
- TWL6030_BASEADD_DIEID
 
- TWL6030_BASEADD_GASGAUGE
 
- TWL6030_BASEADD_GPADC_CTRL
 
- TWL6030_BASEADD_LED
 
- TWL6030_BASEADD_PIH
 
- TWL6030_BASEADD_PM_MASTER
 
- TWL6030_BASEADD_PM_MISC
 
- TWL6030_BASEADD_PM_PUPD
 
- TWL6030_BASEADD_PM_SLAVE_MISC
 
- TWL6030_BASEADD_PWM
 
- TWL6030_BASEADD_RSV
 
- TWL6030_BASEADD_RTC
 
- TWL6030_BASEADD_SECURED_REG
 
- TWL6030_BASEADD_USB
 
- TWL6030_BASEADD_ZERO
 
- TWL6030_BATDETECT_INT_MASK
 
- TWL6030_CFG_INPUT_PUPD3
 
- TWL6030_CFG_LDO_PD2
 
- TWL6030_CFG_STATE_APP
 
- TWL6030_CFG_STATE_APP_MASK
 
- TWL6030_CFG_STATE_APP_SHIFT
 
- TWL6030_CFG_STATE_GRP_SHIFT
 
- TWL6030_CFG_STATE_OFF
 
- TWL6030_CFG_STATE_OFF2
 
- TWL6030_CFG_STATE_ON
 
- TWL6030_CFG_STATE_SLEEP
 
- TWL6030_CHARGER_CTRL_INT_MASK
 
- TWL6030_CHARGER_FAULT_INT_MASK
 
- TWL6030_CLASS
 
- TWL6030_CLASS_ID
 
- TWL6030_FIXED_LDO
 
- TWL6030_GASGAUGE_INT_MASK
 
- TWL6030_GPADCR
 
- TWL6030_GPADCS
 
- TWL6030_GPADC_CHAN
 
- TWL6030_GPADC_CTRL_P1
 
- TWL6030_GPADC_CTRL_P1_SP1
 
- TWL6030_GPADC_GPCH0_LSB
 
- TWL6030_GPADC_INT_MASK
 
- TWL6030_GPADC_MAX_CHANNELS
 
- TWL6030_GPADC_NUM_TRIM_REGS
 
- TWL6030_GPADC_RT_SW1_EOC_MASK
 
- TWL6030_GPADC_TRIM1
 
- TWL6030_GPADC_USED_CHANNELS
 
- TWL6030_HOTDIE_INT_MASK
 
- TWL6030_LED_MAX
 
- TWL6030_LED_PWM_CTRL1
 
- TWL6030_LED_PWM_CTRL2
 
- TWL6030_MISC2
 
- TWL6030_MMCCTRL
 
- TWL6030_MMCDETECT_INT_MASK
 
- TWL6030_MODULE_GASGAUGE
 
- TWL6030_MODULE_GPADC
 
- TWL6030_MODULE_ID0
 
- TWL6030_MODULE_ID1
 
- TWL6030_MODULE_ID2
 
- TWL6030_MODULE_LAST
 
- TWL6030_NR_IRQS
 
- TWL6030_OF_MATCH
 
- TWL6030_PWMXEN
 
- TWL6030_PWMXR
 
- TWL6030_PWMXS
 
- TWL6030_PWM_TOGGLE
 
- TWL6030_PWR_INT_MASK
 
- TWL6030_REG_CLK32KG
 
- TWL6030_REG_TOGGLE1
 
- TWL6030_REG_V1V29
 
- TWL6030_REG_V1V8
 
- TWL6030_REG_V2V1
 
- TWL6030_REG_VANA
 
- TWL6030_REG_VAUX1_6030
 
- TWL6030_REG_VAUX2_6030
 
- TWL6030_REG_VAUX3_6030
 
- TWL6030_REG_VCXIO
 
- TWL6030_REG_VDAC
 
- TWL6030_REG_VDD1
 
- TWL6030_REG_VDD2
 
- TWL6030_REG_VDD3
 
- TWL6030_REG_VMEM
 
- TWL6030_REG_VMMC
 
- TWL6030_REG_VPP
 
- TWL6030_REG_VRTC
 
- TWL6030_REG_VUSB
 
- TWL6030_REG_VUSIM
 
- TWL6030_RTC_INT_MASK
 
- TWL6030_SIMDETECT_INT_MASK
 
- TWL6030_SMPSLDOA_INT_MASK
 
- TWL6030_SMPSLDOB_INT_MASK
 
- TWL6030_SMPS_MULT
 
- TWL6030_SMPS_OFFSET
 
- TWL6030_TOGGLE3_REG
 
- TWL6030_USBOTG_INT_MASK
 
- TWL6030_VREG_VOLTAGE_WR_S
 
- TWL6032_ADJUSTABLE_LDO
 
- TWL6032_ADJUSTABLE_SMPS
 
- TWL6032_BASEADD_CHARGER
 
- TWL6032_GPADC_CTRL_P1
 
- TWL6032_GPADC_GPCH0_LSB
 
- TWL6032_GPADC_GPCH0_MSB
 
- TWL6032_GPADC_GPSELECT_ISB
 
- TWL6032_GPADC_MAX_CHANNELS
 
- TWL6032_GPADC_USED_CHANNELS
 
- TWL6032_OF_MATCH
 
- TWL6032_REG_LDO1
 
- TWL6032_REG_LDO2
 
- TWL6032_REG_LDO3
 
- TWL6032_REG_LDO4
 
- TWL6032_REG_LDO5
 
- TWL6032_REG_LDO6
 
- TWL6032_REG_LDO7
 
- TWL6032_REG_LDOLN
 
- TWL6032_REG_LDOUSB
 
- TWL6032_REG_SMPS3
 
- TWL6032_REG_SMPS4
 
- TWL6032_REG_VIO
 
- TWL6032_SUBCLASS
 
- TWL6040_ALLINT_MSK
 
- TWL6040_CACHEREGNUM
 
- TWL6040_CELLS
 
- TWL6040_DAI_DL1
 
- TWL6040_DAI_DL2
 
- TWL6040_DAI_LEGACY
 
- TWL6040_DAI_UL
 
- TWL6040_DAI_VIB
 
- TWL6040_FORMATS
 
- TWL6040_GPO1
 
- TWL6040_GPO2
 
- TWL6040_GPO3
 
- TWL6040_GPO_MAX
 
- TWL6040_HFDACENA
 
- TWL6040_HFDRVENA
 
- TWL6040_HFINT
 
- TWL6040_HFMSK
 
- TWL6040_HFPGAENA
 
- TWL6040_HFSWENA
 
- TWL6040_HOOKINT
 
- TWL6040_HOOKMSK
 
- TWL6040_HPLLBP
 
- TWL6040_HPLLENA
 
- TWL6040_HPLLRST
 
- TWL6040_HPLLSEL
 
- TWL6040_HPLLSQRENA
 
- TWL6040_HSDACENA
 
- TWL6040_HSDACMODE
 
- TWL6040_HSDRVENA
 
- TWL6040_HSDRVMODE
 
- TWL6040_HSF_TRIM_LEFT
 
- TWL6040_HSF_TRIM_RIGHT
 
- TWL6040_HSLDOENA
 
- TWL6040_I2CMODE
 
- TWL6040_I2CSEL
 
- TWL6040_INTCLRMODE
 
- TWL6040_IRQ_HF
 
- TWL6040_IRQ_HOOK
 
- TWL6040_IRQ_PLUG
 
- TWL6040_IRQ_READY
 
- TWL6040_IRQ_TH
 
- TWL6040_IRQ_VIB
 
- TWL6040_LED_MODE_HW
 
- TWL6040_LED_MODE_MASK
 
- TWL6040_LED_MODE_OFF
 
- TWL6040_LED_MODE_ON
 
- TWL6040_LPLLENA
 
- TWL6040_LPLLFIN
 
- TWL6040_LPLLRST
 
- TWL6040_LPLLSEL
 
- TWL6040_LSLDOENA
 
- TWL6040_MCLK_12000KHZ
 
- TWL6040_MCLK_19200KHZ
 
- TWL6040_MCLK_26000KHZ
 
- TWL6040_MCLK_38400KHZ
 
- TWL6040_MCLK_MSK
 
- TWL6040_NCPENA
 
- TWL6040_NCPOPEN
 
- TWL6040_NUM_SUPPLIES
 
- TWL6040_OSCENA
 
- TWL6040_OUTHF_0dB
 
- TWL6040_OUTHF_M52dB
 
- TWL6040_OUTHS_0dB
 
- TWL6040_OUTHS_M30dB
 
- TWL6040_PLUGCOMP
 
- TWL6040_PLUGINT
 
- TWL6040_PLUGMSK
 
- TWL6040_RATES
 
- TWL6040_READYINT
 
- TWL6040_READYMSK
 
- TWL6040_REFENA
 
- TWL6040_REG_ACCCTL
 
- TWL6040_REG_ALB
 
- TWL6040_REG_AMICBCTL
 
- TWL6040_REG_ASICID
 
- TWL6040_REG_ASICREV
 
- TWL6040_REG_DLB
 
- TWL6040_REG_DMICBCTL
 
- TWL6040_REG_EARCTL
 
- TWL6040_REG_GPOCTL
 
- TWL6040_REG_HFLCTL
 
- TWL6040_REG_HFLGAIN
 
- TWL6040_REG_HFOTRIM
 
- TWL6040_REG_HFRCTL
 
- TWL6040_REG_HFRGAIN
 
- TWL6040_REG_HKCTL1
 
- TWL6040_REG_HKCTL2
 
- TWL6040_REG_HPPLLCTL
 
- TWL6040_REG_HSGAIN
 
- TWL6040_REG_HSLCTL
 
- TWL6040_REG_HSOTRIM
 
- TWL6040_REG_HSRCTL
 
- TWL6040_REG_INTID
 
- TWL6040_REG_INTMR
 
- TWL6040_REG_LDOCTL
 
- TWL6040_REG_LINEGAIN
 
- TWL6040_REG_LPPLLCTL
 
- TWL6040_REG_LPPLLDIV
 
- TWL6040_REG_MICGAIN
 
- TWL6040_REG_MICLCTL
 
- TWL6040_REG_MICRCTL
 
- TWL6040_REG_NCPCTL
 
- TWL6040_REG_STATUS
 
- TWL6040_REG_TRIM1
 
- TWL6040_REG_TRIM2
 
- TWL6040_REG_TRIM3
 
- TWL6040_REG_VIBCTLL
 
- TWL6040_REG_VIBCTLR
 
- TWL6040_REG_VIBDATL
 
- TWL6040_REG_VIBDATR
 
- TWL6040_RESETSPLIT
 
- TWL6040_REV_ES1_0
 
- TWL6040_REV_ES1_1
 
- TWL6040_REV_ES1_3
 
- TWL6040_SYSCLK_SEL_HPPLL
 
- TWL6040_SYSCLK_SEL_LPPLL
 
- TWL6040_THINT
 
- TWL6040_THMSK
 
- TWL6040_TRIM_HFOTRIM
 
- TWL6040_TRIM_HSOTRIM
 
- TWL6040_TRIM_INVAL
 
- TWL6040_TRIM_TRIM1
 
- TWL6040_TRIM_TRIM2
 
- TWL6040_TRIM_TRIM3
 
- TWL6040_TSHUTDET
 
- TWL6040_UNPLUGINT
 
- TWL6040_VIBCTRL
 
- TWL6040_VIBCTRL_N
 
- TWL6040_VIBCTRL_P
 
- TWL6040_VIBDAT_MAX
 
- TWL6040_VIBENA
 
- TWL6040_VIBINT
 
- TWL6040_VIBLOCDET
 
- TWL6040_VIBMSK
 
- TWL6040_VIBRA_MOD
 
- TWL6040_VIBROCDET
 
- TWL6040_VIBSEL
 
- TWL6041_REV_ES2_0
 
- TWLFIXED_OF_MATCH
 
- TWLO_USEC
 
- TWLSMPS_OF_MATCH
 
- TWL_4030
 
- TWL_6030
 
- TWL_6030_WARM_RESET
 
- TWL_CLASS_IS
 
- TWL_CLEAR_DB_INTERRUPT
 
- TWL_CONTROLLER_READY
 
- TWL_DEV_GRP_P123
 
- TWL_DFLT_DELAY
 
- TWL_DOORBELL_ATTENTION_INTERRUPT
 
- TWL_DOORBELL_CONTROLLER_ERROR
 
- TWL_EEPROM_R_UNLOCK
 
- TWL_HIBDB
 
- TWL_HIBDB_REG_ADDR
 
- TWL_HIBQPH
 
- TWL_HIBQPH_REG_ADDR
 
- TWL_HIBQPL
 
- TWL_HIBQPL_REG_ADDR
 
- TWL_HIMASK
 
- TWL_HIMASK_REG_ADDR
 
- TWL_HISTAT
 
- TWL_HISTATUS_ATTENTION_INTERRUPT
 
- TWL_HISTATUS_RESPONSE_INTERRUPT
 
- TWL_HISTATUS_VALID_INTERRUPT
 
- TWL_HISTAT_REG_ADDR
 
- TWL_HOBDB
 
- TWL_HOBDBC
 
- TWL_HOBDBC_REG_ADDR
 
- TWL_HOBDB_REG_ADDR
 
- TWL_HOBQPH
 
- TWL_HOBQPH_REG_ADDR
 
- TWL_HOBQPL
 
- TWL_HOBQPL_REG_ADDR
 
- TWL_INTBR_GPBR1
 
- TWL_INTBR_PMBR1
 
- TWL_ISSUE_SOFT_RESET
 
- TWL_MASK_INTERRUPTS
 
- TWL_MODULE_LAST
 
- TWL_MODULE_LED
 
- TWL_MODULE_MAIN_CHARGE
 
- TWL_MODULE_PIH
 
- TWL_MODULE_PM_MASTER
 
- TWL_MODULE_PM_RECEIVER
 
- TWL_MODULE_PWM
 
- TWL_MODULE_RTC
 
- TWL_MODULE_SECURED_REG
 
- TWL_MODULE_USB
 
- TWL_OF_MATCH
 
- TWL_PMBR1_PWM0
 
- TWL_PMBR1_PWM0_MUXMASK
 
- TWL_PULL_MODE
 
- TWL_PWM0_OFF
 
- TWL_PWM0_ON
 
- TWL_PWM_MAX
 
- TWL_REMAP_ACTIVE
 
- TWL_REMAP_OFF
 
- TWL_REMAP_SLEEP
 
- TWL_RESOURCE_GROUP_ACTIVE
 
- TWL_RESOURCE_GROUP_RESET
 
- TWL_RESOURCE_GROUP_SLEEP
 
- TWL_RESOURCE_OFF
 
- TWL_RESOURCE_ON
 
- TWL_RESOURCE_RESET
 
- TWL_RESOURCE_SET
 
- TWL_RESOURCE_SET_ACTIVE
 
- TWL_SCRPD3
 
- TWL_SCRPD3_REG_ADDR
 
- TWL_SIL_5030
 
- TWL_SIL_REV
 
- TWL_SIL_TYPE
 
- TWL_SOFT_RESET
 
- TWL_STATUS
 
- TWL_STATUS_OVERRUN_SUBMIT
 
- TWL_STATUS_REG_ADDR
 
- TWL_UNMASK_INTERRUPTS
 
- TWODG
 
- TWODLSCCFG
 
- TWODLSCGRBL
 
- TWODLSCGRBU
 
- TWODLSCGROF
 
- TWODLSCINI
 
- TWODLSCIRQEN
 
- TWODLSCIRQST
 
- TWODLSCOFST
 
- TWODLSCORBL
 
- TWODLSCORBU
 
- TWODLSCOROF
 
- TWOFISH_PARALLEL_BLOCKS
 
- TWOMEG_MEDIA
 
- TWOPOW11
 
- TWO_ADDITIONAL_TRANSACTION
 
- TWO_BANKS
 
- TWO_CHANNEL_4020_BITS
 
- TWO_CHANNEL_SUPPORT
 
- TWO_DB_BNDWDTH_THRSHLD_REG
 
- TWO_D_INST_DISABLE
 
- TWO_FRAGMENTS
 
- TWO_LINES
 
- TWO_MHZ
 
- TWO_MIN
 
- TWO_MINUTES
 
- TWO_MSDU
 
- TWO_PACKETS_MASK
 
- TWO_PART_DEFDIS
 
- TWO_PIN_OD
 
- TWO_PIN_OO
 
- TWO_PIN_PP
 
- TWO_PIPES
 
- TWO_PT_CALIB
 
- TWO_QUADS
 
- TWO_RB_PER_SE
 
- TWO_ROW_ADDR_CYCLES
 
- TWO_ROW_ADDR_CYCLES__FLAG
 
- TWO_SAMPLES
 
- TWO_SHADER_ENGINS
 
- TWO_TAP_FILT
 
- TWPR_TW_MASK
 
- TWPR_TW_SHIFT
 
- TWP_MASK
 
- TWRITE_STR
 
- TWR_WAIT
 
- TWSI
 
- TWSI4_SCL
 
- TWSI4_SDA
 
- TWSIC0_CLKDIV
 
- TWSIC0_EN
 
- TWSIC0_MASKACK
 
- TWSIC0_MODE
 
- TWSIC0_OVMAGIC
 
- TWSIC0_SID
 
- TWSIC0_SID_SHIFT
 
- TWSIC1_ADDR
 
- TWSIC1_ADDR_SHIFT
 
- TWSIC1_DATA
 
- TWSIC1_ERROR
 
- TWSIC1_READ
 
- TWSIC1_RVALID
 
- TWSIC1_WSTAT
 
- TWSIIRQS
 
- TWSI_BUF_WAIT_USEC
 
- TWSI_CTLR_FREQ_MASK
 
- TWSI_CTL_AAK
 
- TWSI_CTL_CE
 
- TWSI_CTL_ENAB
 
- TWSI_CTL_IFLG
 
- TWSI_CTL_STA
 
- TWSI_CTL_STP
 
- TWSI_CTRL_FREQ_100K
 
- TWSI_CTRL_FREQ_200K
 
- TWSI_CTRL_FREQ_300K
 
- TWSI_CTRL_FREQ_400K
 
- TWSI_CTRL_FREQ_SEL_100K
 
- TWSI_CTRL_FREQ_SEL_200K
 
- TWSI_CTRL_FREQ_SEL_300K
 
- TWSI_CTRL_FREQ_SEL_400K
 
- TWSI_CTRL_FREQ_SHIFT
 
- TWSI_CTRL_HW_LDSTART
 
- TWSI_CTRL_HW_LDSTAT
 
- TWSI_CTRL_LD_EXIST
 
- TWSI_CTRL_LD_OFFSET_MASK
 
- TWSI_CTRL_LD_OFFSET_SHIFT
 
- TWSI_CTRL_LD_SLV_ADDR_MASK
 
- TWSI_CTRL_LD_SLV_ADDR_SHIFT
 
- TWSI_CTRL_READ_FREQ_SEL_MASK
 
- TWSI_CTRL_READ_FREQ_SEL_SHIFT
 
- TWSI_CTRL_SMB_SLV_ADDR
 
- TWSI_CTRL_SMB_SLV_ADDR_MASK
 
- TWSI_CTRL_SMB_SLV_ADDR_SHIFT
 
- TWSI_CTRL_SW_LDSTART
 
- TWSI_CTRL_WRITE_FREQ_SEL_MASK
 
- TWSI_CTRL_WRITE_FREQ_SEL_SHIFT
 
- TWSI_DEBUG_DEV_EXIST
 
- TWSI_ENABLE_OPTION1
 
- TWSI_ENABLE_OPTION2
 
- TWSI_ENABLE_OPTION3
 
- TWSI_INT
 
- TWSI_INT_CORE_EN
 
- TWSI_INT_CORE_INT
 
- TWSI_INT_ENA_W1C
 
- TWSI_INT_ENA_W1S
 
- TWSI_INT_SCL
 
- TWSI_INT_SCL_OVR
 
- TWSI_INT_SDA
 
- TWSI_INT_SDA_OVR
 
- TWSI_INT_ST_EN
 
- TWSI_INT_ST_INT
 
- TWSI_INT_TS_EN
 
- TWSI_INT_TS_INT
 
- TWSI_OPTION3_GPIO
 
- TWSI_RD
 
- TWSI_RDY
 
- TWT_SUPPORTED
 
- TWXXXX
 
- TW_9000_ARCH_ID
 
- TW_9550SX_DRAIN_COMPLETED
 
- TW_9750_ARCH_ID
 
- TW_AEN_APORT_TIMEOUT
 
- TW_AEN_CONTROLLER_ERROR
 
- TW_AEN_DEGRADED_MIRROR
 
- TW_AEN_DRIVE_ERROR
 
- TW_AEN_NOT_RETRIEVED
 
- TW_AEN_QUEUE_EMPTY
 
- TW_AEN_QUEUE_FULL
 
- TW_AEN_REBUILD_DONE
 
- TW_AEN_REBUILD_FAIL
 
- TW_AEN_RETRIEVED
 
- TW_AEN_SBUF_FAIL
 
- TW_AEN_SEVERITY_DEBUG
 
- TW_AEN_SEVERITY_ERROR
 
- TW_AEN_SMART_FAIL
 
- TW_AEN_SOFT_RESET
 
- TW_AEN_SYNC_TIME_WITH_HOST
 
- TW_AEN_TABLE_UNDEFINED
 
- TW_AEN_WAIT_TIME
 
- TW_ALIGNMENT_6000
 
- TW_ALIGNMENT_7000
 
- TW_ALIGNMENT_9000
 
- TW_ALIGNMENT_9000_SGL
 
- TW_ALLOCATION_LENGTH
 
- TW_APACHE_MAX_SGL_LENGTH
 
- TW_ATA_PASS_SGL_MAX
 
- TW_AUDIO_INPUT_GAIN_ADDR
 
- TW_AUDIO_OUTPUT_VOL_ADDR
 
- TW_AV_STAT_ADDR
 
- TW_BASE_ADDR
 
- TW_BASE_FW_BRANCH
 
- TW_BASE_FW_BUILD
 
- TW_BASE_FW_SRL
 
- TW_BLOCK_SIZE
 
- TW_BRIGHTNESS_ADDR
 
- TW_BUNDLED_FW_SAFE_TO_FLASH
 
- TW_CHIP_OFFSET_ADDR
 
- TW_CLEAR_ALL_INTERRUPTS
 
- TW_CLEAR_ATTENTION_INTERRUPT
 
- TW_CLEAR_HOST_INTERRUPT
 
- TW_CMD_PACKET
 
- TW_CMD_PACKET_WITH_DATA
 
- TW_COMMAND_ALIGNMENT_MASK
 
- TW_COMMAND_OFFSET
 
- TW_COMMAND_QUEUE_REG_ADDR
 
- TW_COMMAND_QUEUE_REG_ADDR_LARGE
 
- TW_COMMAND_SIZE
 
- TW_CONTRAST_ADDR
 
- TW_CONTROL_CLEAR_ATTENTION_INTERRUPT
 
- TW_CONTROL_CLEAR_ERROR_STATUS
 
- TW_CONTROL_CLEAR_HOST_INTERRUPT
 
- TW_CONTROL_CLEAR_PARITY_ERROR
 
- TW_CONTROL_CLEAR_PCI_ABORT
 
- TW_CONTROL_CLEAR_QUEUE_ERROR
 
- TW_CONTROL_CLEAR_SBUF_WRITE_ERROR
 
- TW_CONTROL_DISABLE_INTERRUPTS
 
- TW_CONTROL_ENABLE_INTERRUPTS
 
- TW_CONTROL_ISSUE_HOST_INTERRUPT
 
- TW_CONTROL_ISSUE_SOFT_RESET
 
- TW_CONTROL_MASK_COMMAND_INTERRUPT
 
- TW_CONTROL_MASK_RESPONSE_INTERRUPT
 
- TW_CONTROL_REG_ADDR
 
- TW_CONTROL_UNMASK_COMMAND_INTERRUPT
 
- TW_CONTROL_UNMASK_RESPONSE_INTERRUPT
 
- TW_CPU_TO_SGL
 
- TW_CTLR_FW_COMPATIBLE
 
- TW_CTLR_FW_RECOMMENDS_FLASH
 
- TW_CURRENT_DRIVER_BRANCH
 
- TW_CURRENT_DRIVER_BUILD
 
- TW_CURRENT_DRIVER_SRL
 
- TW_Cmd_State
 
- TW_Command
 
- TW_Command_Apache
 
- TW_Command_Apache_Header
 
- TW_Command_Full
 
- TW_Compatibility_Info
 
- TW_DEVICE_ID
 
- TW_DEVICE_ID2
 
- TW_DEVICE_NAME
 
- TW_DISABLE_INTERRUPTS
 
- TW_DRIVER
 
- TW_DRIVER_VERSION
 
- TW_Denormal
 
- TW_Device_Extension
 
- TW_ENABLE_AND_CLEAR_INTERRUPTS
 
- TW_ERROR_INVALID_FIELD_IN_CDB
 
- TW_ERROR_LOGICAL_UNIT_NOT_SUPPORTED
 
- TW_ERROR_UNIT_OFFLINE
 
- TW_ESCALADE_MAX_SGL_LENGTH
 
- TW_EVENT_SOURCE_AEN
 
- TW_EVENT_SOURCE_COMMAND
 
- TW_EVENT_SOURCE_DRIVER
 
- TW_EVENT_SOURCE_PCHIP
 
- TW_EXTENDED_INIT_CONNECT
 
- TW_Event
 
- TW_FW_SRL_LUNS_SUPPORTED
 
- TW_HUE_ADDR
 
- TW_INFORMATION_TABLE
 
- TW_INIT_COMMAND_PACKET_SIZE
 
- TW_INIT_COMMAND_PACKET_SIZE_EXTENDED
 
- TW_INIT_MESSAGE_CREDITS
 
- TW_IN_ATTENTION_LOOP
 
- TW_IN_CHRDEV_IOCTL
 
- TW_IN_INTR
 
- TW_IN_RESET
 
- TW_IOCTL
 
- TW_IOCTL_CHRDEV_FREE
 
- TW_IOCTL_CHRDEV_TIMEOUT
 
- TW_IOCTL_ERROR_OS_EFAULT
 
- TW_IOCTL_ERROR_OS_EINTR
 
- TW_IOCTL_ERROR_OS_EINVAL
 
- TW_IOCTL_ERROR_OS_EIO
 
- TW_IOCTL_ERROR_OS_ENODEV
 
- TW_IOCTL_ERROR_OS_ENOMEM
 
- TW_IOCTL_ERROR_OS_ENOTTY
 
- TW_IOCTL_ERROR_OS_ERESTARTSYS
 
- TW_IOCTL_ERROR_STATUS_AEN_CLOBBER
 
- TW_IOCTL_ERROR_STATUS_LOCKED
 
- TW_IOCTL_ERROR_STATUS_NOT_LOCKED
 
- TW_IOCTL_ERROR_STATUS_NO_MORE_EVENTS
 
- TW_IOCTL_FIRMWARE_PASS_THROUGH
 
- TW_IOCTL_GET_COMPATIBILITY_INFO
 
- TW_IOCTL_GET_FIRST_EVENT
 
- TW_IOCTL_GET_LAST_EVENT
 
- TW_IOCTL_GET_LOCK
 
- TW_IOCTL_GET_NEXT_EVENT
 
- TW_IOCTL_GET_PREVIOUS_EVENT
 
- TW_IOCTL_RELEASE_LOCK
 
- TW_IOCTL_TIMEOUT
 
- TW_IOCTL_WAIT_TIME
 
- TW_IO_ADDRESS_RANGE
 
- TW_ISR_DONT_COMPLETE
 
- TW_ISR_DONT_RESULT
 
- TW_Infinity
 
- TW_Initconnect
 
- TW_Ioctl
 
- TW_Ioctl_Buf_Apache
 
- TW_Ioctl_Driver_Command
 
- TW_KR
 
- TW_LENGTH
 
- TW_LIBERATOR_MAX_SGL_LENGTH
 
- TW_LIBERATOR_MAX_SGL_LENGTH_OLD
 
- TW_LUN_OUT
 
- TW_Lock
 
- TW_MASK_COMMAND_INTERRUPT
 
- TW_MAX_AEN_DRAIN
 
- TW_MAX_CDB_LEN
 
- TW_MAX_CMDS_PER_LUN
 
- TW_MAX_IOCTL_SECTORS
 
- TW_MAX_LUNS
 
- TW_MAX_PCI_BUSES
 
- TW_MAX_RESET_TRIES
 
- TW_MAX_RESPONSE_DRAIN
 
- TW_MAX_SECTORS
 
- TW_MAX_SENSE_LENGTH
 
- TW_MAX_SGL_LENGTH
 
- TW_MAX_SLOT
 
- TW_MAX_UNITS
 
- TW_MAX_UNITS_9650SE
 
- TW_MAX_XC
 
- TW_MAX_YC
 
- TW_MESSAGE_SOURCE_CONTROLLER_ERROR
 
- TW_MESSAGE_SOURCE_CONTROLLER_EVENT
 
- TW_MESSAGE_SOURCE_LINUX_DRIVER
 
- TW_MESSAGE_SOURCE_LINUX_OS
 
- TW_MIN_SGL_LENGTH
 
- TW_MIN_XC
 
- TW_MIN_YC
 
- TW_NONE
 
- TW_NOTMFA_OUT
 
- TW_NUMDEVICES
 
- TW_NUM_CHIP
 
- TW_NaN
 
- TW_New_Ioctl
 
- TW_OPRES_IN
 
- TW_OPSGL_IN
 
- TW_OP_AEN_LISTEN
 
- TW_OP_DOWNLOAD_FIRMWARE
 
- TW_OP_EXECUTE_SCSI
 
- TW_OP_FLUSH_CACHE
 
- TW_OP_GET_PARAM
 
- TW_OP_INIT_CONNECTION
 
- TW_OP_NOP
 
- TW_OP_OUT
 
- TW_OP_READ
 
- TW_OP_RESET
 
- TW_OP_SECTOR_INFO
 
- TW_OP_SET_PARAM
 
- TW_OP_VERIFY
 
- TW_OP_WRITE
 
- TW_OS
 
- TW_PADDING_LENGTH
 
- TW_PADDING_LENGTH_LIBERATOR
 
- TW_PADDING_LENGTH_LIBERATOR_OLD
 
- TW_PARAM_BIOSVER
 
- TW_PARAM_BIOSVER_LENGTH
 
- TW_PARAM_FWVER
 
- TW_PARAM_FWVER_LENGTH
 
- TW_PARAM_MODEL
 
- TW_PARAM_MODEL_LENGTH
 
- TW_PARAM_PHYCOUNT
 
- TW_PARAM_PHYCOUNT_LENGTH
 
- TW_PARAM_PHY_SUMMARY_TABLE
 
- TW_PARAM_PORTCOUNT
 
- TW_PARAM_PORTCOUNT_LENGTH
 
- TW_PCI_CLEAR_PARITY_ERRORS
 
- TW_PCI_CLEAR_PCI_ABORT
 
- TW_PLUSALARM
 
- TW_POLL_MAX_RETRIES
 
- TW_PRINTK
 
- TW_Param
 
- TW_Param_Apache
 
- TW_Passthru
 
- TW_Q_LENGTH
 
- TW_Q_START
 
- TW_REQ_LUN_IN
 
- TW_RESID_OUT
 
- TW_RESPONSE_ID_MASK
 
- TW_RESPONSE_QUEUE_REG_ADDR
 
- TW_RESPONSE_QUEUE_REG_ADDR_LARGE
 
- TW_Response_Queue
 
- TW_SATURATION_ADDR
 
- TW_SECTOR_SIZE
 
- TW_SENSE_DATA_LENGTH
 
- TW_SEV_OUT
 
- TW_SGL_OUT
 
- TW_SG_Entry
 
- TW_SG_Entry_ISO
 
- TW_SOFT_RESET
 
- TW_START_MASK
 
- TW_STATUS_ALL_INTERRUPTS
 
- TW_STATUS_ATTENTION_INTERRUPT
 
- TW_STATUS_CHECK_CONDITION
 
- TW_STATUS_CLEARABLE_BITS
 
- TW_STATUS_COMMAND_INTERRUPT
 
- TW_STATUS_COMMAND_QUEUE_EMPTY
 
- TW_STATUS_COMMAND_QUEUE_FULL
 
- TW_STATUS_ERRORS
 
- TW_STATUS_EXPECTED_BITS
 
- TW_STATUS_HOST_INTERRUPT
 
- TW_STATUS_MAJOR_VERSION_MASK
 
- TW_STATUS_MICROCONTROLLER_ERROR
 
- TW_STATUS_MICROCONTROLLER_READY
 
- TW_STATUS_MINOR_VERSION_MASK
 
- TW_STATUS_PCI_ABORT
 
- TW_STATUS_PCI_PARITY_ERROR
 
- TW_STATUS_QUEUE_ERROR
 
- TW_STATUS_REG_ADDR
 
- TW_STATUS_RESPONSE_INTERRUPT
 
- TW_STATUS_RESPONSE_QUEUE_EMPTY
 
- TW_STATUS_SBUF_WRITE_ERROR
 
- TW_STATUS_UNEXPECTED_BITS
 
- TW_STATUS_VALID_INTERRUPT
 
- TW_S_COMPLETED
 
- TW_S_FINISHED
 
- TW_S_INITIAL
 
- TW_S_PENDING
 
- TW_S_POSTED
 
- TW_S_STARTED
 
- TW_Sector
 
- TW_TIMEKEEP_TABLE
 
- TW_UNITHOST_IN
 
- TW_UNIT_INFORMATION_TABLE_BASE
 
- TW_UNIT_ONLINE
 
- TW_UNIT_OUT
 
- TW_UNMASK_COMMAND_INTERRUPT
 
- TW_USING_MSI
 
- TW_Unsupported
 
- TW_VENDOR_ID
 
- TW_VERSION_TABLE
 
- TWstruct
 
- TWunion
 
- TX
 
- TX0BYTE_EP1
 
- TX0BYTE_EP2
 
- TX0BYTE_EP3
 
- TX0BYTE_EP4
 
- TX0BYTE_EP5
 
- TX0BYTE_EP6
 
- TX0BYTE_EP7
 
- TX0BYTE_EP8
 
- TX0_A_MARK
 
- TX0_BB_GAIN_ATTEN
 
- TX0_BB_GAIN_ATTEN_LEVEL_0
 
- TX0_BB_GAIN_ATTEN_LEVEL_1
 
- TX0_BB_GAIN_ATTEN_LEVEL_2
 
- TX0_BB_GAIN_ATTEN_LEVEL_3
 
- TX0_B_MARK
 
- TX0_C_MARK
 
- TX0_DISABLE_STATE
 
- TX0_D_MARK
 
- TX0_ENABLE_STATE
 
- TX0_E_MARK
 
- TX0_MARK
 
- TX0_RF_GAIN_ATTEN
 
- TX0_RF_GAIN_ATTEN_LEVEL_0
 
- TX0_RF_GAIN_ATTEN_LEVEL_1
 
- TX0_RF_GAIN_ATTEN_LEVEL_2
 
- TX0_RF_GAIN_ATTEN_LEVEL_3
 
- TX0_RF_GAIN_CORRECT
 
- TX0_RF_GAIN_CORRECT_GAIN_CORR_0
 
- TX0_RF_GAIN_CORRECT_GAIN_CORR_1
 
- TX0_RF_GAIN_CORRECT_GAIN_CORR_2
 
- TX0_RF_GAIN_CORRECT_GAIN_CORR_3
 
- TX0_SLEEP_STATE
 
- TX0_SNOOZE_STATE
 
- TX10MIDLE_EN
 
- TX1_A_MARK
 
- TX1_BB_GAIN_ATTEN
 
- TX1_BB_GAIN_ATTEN_LEVEL_0
 
- TX1_BB_GAIN_ATTEN_LEVEL_1
 
- TX1_BB_GAIN_ATTEN_LEVEL_2
 
- TX1_BB_GAIN_ATTEN_LEVEL_3
 
- TX1_B_MARK
 
- TX1_C_MARK
 
- TX1_D_MARK
 
- TX1_E_MARK
 
- TX1_MARK
 
- TX1_RF_GAIN_ATTEN
 
- TX1_RF_GAIN_ATTEN_LEVEL_0
 
- TX1_RF_GAIN_ATTEN_LEVEL_1
 
- TX1_RF_GAIN_ATTEN_LEVEL_2
 
- TX1_RF_GAIN_ATTEN_LEVEL_3
 
- TX1_RF_GAIN_CORRECT
 
- TX1_RF_GAIN_CORRECT_GAIN_CORR_0
 
- TX1_RF_GAIN_CORRECT_GAIN_CORR_1
 
- TX1_RF_GAIN_CORRECT_GAIN_CORR_2
 
- TX1_RF_GAIN_CORRECT_GAIN_CORR_3
 
- TX1_SWING_CALC_INIT
 
- TX2_A_MARK
 
- TX2_B_MARK
 
- TX2_C_MARK
 
- TX2_D_MARK
 
- TX2_EVENT_ATTR
 
- TX2_E_MARK
 
- TX2_MARK
 
- TX2_PMU_DMC_CHANNELS
 
- TX2_PMU_HRTIMER_INTERVAL
 
- TX2_PMU_L3_TILES
 
- TX2_PMU_MAX_COUNTERS
 
- TX2_SWING_CALC_INIT
 
- TX33_HDMI
 
- TX3927_CCFG_ACEHOLD
 
- TX3927_CCFG_BEOW
 
- TX3927_CCFG_ENDIAN
 
- TX3927_CCFG_HALT
 
- TX3927_CCFG_PCI3
 
- TX3927_CCFG_PCIXARB
 
- TX3927_CCFG_PLLM
 
- TX3927_CCFG_PPRI
 
- TX3927_CCFG_PSNP
 
- TX3927_CCFG_REG
 
- TX3927_CCFG_TLBOFF
 
- TX3927_CCFG_TOE
 
- TX3927_CCFG_WR
 
- TX3927_DMA_CCR_ACKPOL
 
- TX3927_DMA_CCR_CHDN
 
- TX3927_DMA_CCR_CHNEN
 
- TX3927_DMA_CCR_CHRST
 
- TX3927_DMA_CCR_DBINH
 
- TX3927_DMA_CCR_DNCTL
 
- TX3927_DMA_CCR_DSTINC
 
- TX3927_DMA_CCR_EGREQ
 
- TX3927_DMA_CCR_EXTRQ
 
- TX3927_DMA_CCR_INTENC
 
- TX3927_DMA_CCR_INTENE
 
- TX3927_DMA_CCR_INTENT
 
- TX3927_DMA_CCR_INTRQD
 
- TX3927_DMA_CCR_MEMIO
 
- TX3927_DMA_CCR_ONEAD
 
- TX3927_DMA_CCR_REQPL
 
- TX3927_DMA_CCR_RVBYTE
 
- TX3927_DMA_CCR_SBINH
 
- TX3927_DMA_CCR_SNOP
 
- TX3927_DMA_CCR_SRCINC
 
- TX3927_DMA_CCR_XFACT
 
- TX3927_DMA_CCR_XFSZ
 
- TX3927_DMA_CCR_XFSZ_16W
 
- TX3927_DMA_CCR_XFSZ_1W
 
- TX3927_DMA_CCR_XFSZ_32W
 
- TX3927_DMA_CCR_XFSZ_4W
 
- TX3927_DMA_CCR_XFSZ_8W
 
- TX3927_DMA_CSR_ABCHC
 
- TX3927_DMA_CSR_CFERR
 
- TX3927_DMA_CSR_CHERR
 
- TX3927_DMA_CSR_CHNACT
 
- TX3927_DMA_CSR_DESERR
 
- TX3927_DMA_CSR_EXTDN
 
- TX3927_DMA_CSR_NCHNC
 
- TX3927_DMA_CSR_NTRNFC
 
- TX3927_DMA_CSR_SORERR
 
- TX3927_DMA_MCR_DIS
 
- TX3927_DMA_MCR_EIS
 
- TX3927_DMA_MCR_FIFUM
 
- TX3927_DMA_MCR_LE
 
- TX3927_DMA_MCR_MSTEN
 
- TX3927_DMA_MCR_RPRT
 
- TX3927_DMA_MCR_RSFIF
 
- TX3927_DMA_REG
 
- TX3927_IRC_REG
 
- TX3927_IR_DMA
 
- TX3927_IR_INT0
 
- TX3927_IR_INT1
 
- TX3927_IR_INT2
 
- TX3927_IR_INT3
 
- TX3927_IR_INT4
 
- TX3927_IR_INT5
 
- TX3927_IR_PCI
 
- TX3927_IR_PIO
 
- TX3927_IR_SIO
 
- TX3927_IR_SIO0
 
- TX3927_IR_SIO1
 
- TX3927_IR_TMR
 
- TX3927_NR_SIO
 
- TX3927_NR_TMR
 
- TX3927_NUM_IR
 
- TX3927_PCFG_INTDMA
 
- TX3927_PCFG_INTDMA_ALL
 
- TX3927_PCFG_PCICLKEN
 
- TX3927_PCFG_PCICLKEN_ALL
 
- TX3927_PCFG_SDRCLKEN
 
- TX3927_PCFG_SDRCLKEN_ALL
 
- TX3927_PCFG_SELALL
 
- TX3927_PCFG_SELCS
 
- TX3927_PCFG_SELDMA
 
- TX3927_PCFG_SELDMA_ALL
 
- TX3927_PCFG_SELDONE
 
- TX3927_PCFG_SELDSF
 
- TX3927_PCFG_SELSIO
 
- TX3927_PCFG_SELSIOC
 
- TX3927_PCFG_SELSIOC_ALL
 
- TX3927_PCFG_SELSIO_ALL
 
- TX3927_PCFG_SELTMR
 
- TX3927_PCFG_SELTMR_ALL
 
- TX3927_PCFG_SYSCLKEN
 
- TX3927_PCIC_IDSEL_AD_TO_SLOT
 
- TX3927_PCIC_IIM_ALL
 
- TX3927_PCIC_LBC_CRR
 
- TX3927_PCIC_LBC_EPCAD
 
- TX3927_PCIC_LBC_HRST
 
- TX3927_PCIC_LBC_IBSE
 
- TX3927_PCIC_LBC_ILIDE
 
- TX3927_PCIC_LBC_ILMDE
 
- TX3927_PCIC_LBC_MSDSE
 
- TX3927_PCIC_LBC_SRST
 
- TX3927_PCIC_LBC_TIBSE
 
- TX3927_PCIC_LBC_TMFBSE
 
- TX3927_PCIC_LBIM_ALL
 
- TX3927_PCIC_MAX_DEVNU
 
- TX3927_PCIC_PBAPMC_BMCEN
 
- TX3927_PCIC_PBAPMC_PBAEN
 
- TX3927_PCIC_PBAPMC_RPBA
 
- TX3927_PCIC_PCISTATIM_ALL
 
- TX3927_PCIC_REG
 
- TX3927_PCIC_TC_IF8E
 
- TX3927_PCIC_TC_OF16E
 
- TX3927_PCIC_TC_OF8E
 
- TX3927_PCIC_TIM_ALL
 
- TX3927_PIO_REG
 
- TX3927_REG_BASE
 
- TX3927_REG_SIZE
 
- TX3927_REV_PCODE
 
- TX3927_ROMC_BA
 
- TX3927_ROMC_REG
 
- TX3927_ROMC_SIZE
 
- TX3927_ROMC_WIDTH
 
- TX3927_SDRAMC_REG
 
- TX3927_SIO_REG
 
- TX3927_TMR_REG
 
- TX39_CONF_CWFON
 
- TX39_CONF_DCE
 
- TX39_CONF_DCS_16KB
 
- TX39_CONF_DCS_1KB
 
- TX39_CONF_DCS_2KB
 
- TX39_CONF_DCS_4KB
 
- TX39_CONF_DCS_8KB
 
- TX39_CONF_DCS_MASK
 
- TX39_CONF_DCS_SHIFT
 
- TX39_CONF_DOZE
 
- TX39_CONF_DRSIZE_MASK
 
- TX39_CONF_DRSIZE_SHIFT
 
- TX39_CONF_HALT
 
- TX39_CONF_ICE
 
- TX39_CONF_ICS_16KB
 
- TX39_CONF_ICS_1KB
 
- TX39_CONF_ICS_2KB
 
- TX39_CONF_ICS_4KB
 
- TX39_CONF_ICS_8KB
 
- TX39_CONF_ICS_MASK
 
- TX39_CONF_ICS_SHIFT
 
- TX39_CONF_IRSIZE_MASK
 
- TX39_CONF_IRSIZE_SHIFT
 
- TX39_CONF_LOCK
 
- TX39_CONF_RF_MASK
 
- TX39_CONF_RF_SHIFT
 
- TX39_CONF_WBON
 
- TX39_STOP_STREAMING
 
- TX3C_IRDA_TX_C_MARK
 
- TX3_A_MARK
 
- TX3_B_IRDA_TX_B_MARK
 
- TX3_B_MARK
 
- TX3_C_MARK
 
- TX3_D_IRDA_TX_D_MARK
 
- TX3_D_MARK
 
- TX3_E_IRDA_TX_E_MARK
 
- TX3_E_MARK
 
- TX3_IRDA_TX_MARK
 
- TX3_MARK
 
- TX3_RCH_DBG_MODE_MASK
 
- TX3_RCH_DBG_MODE_MASK_SFT
 
- TX3_RCH_DBG_MODE_SFT
 
- TX422_PORT0
 
- TX422_PORT1
 
- TX4927_ACLC_REG
 
- TX4927_CCFG_ACEHOLD
 
- TX4927_CCFG_BCFG_MASK
 
- TX4927_CCFG_BEOW
 
- TX4927_CCFG_DIVMODE_10
 
- TX4927_CCFG_DIVMODE_12
 
- TX4927_CCFG_DIVMODE_16
 
- TX4927_CCFG_DIVMODE_2
 
- TX4927_CCFG_DIVMODE_2_5
 
- TX4927_CCFG_DIVMODE_3
 
- TX4927_CCFG_DIVMODE_4
 
- TX4927_CCFG_DIVMODE_8
 
- TX4927_CCFG_DIVMODE_MASK
 
- TX4927_CCFG_ENDIAN
 
- TX4927_CCFG_HALT
 
- TX4927_CCFG_PCI66
 
- TX4927_CCFG_PCIARB
 
- TX4927_CCFG_PCIDIVMODE_2_5
 
- TX4927_CCFG_PCIDIVMODE_3
 
- TX4927_CCFG_PCIDIVMODE_5
 
- TX4927_CCFG_PCIDIVMODE_6
 
- TX4927_CCFG_PCIDIVMODE_MASK
 
- TX4927_CCFG_PCIMODE
 
- TX4927_CCFG_REG
 
- TX4927_CCFG_SYSSP_MASK
 
- TX4927_CCFG_TINTDIS
 
- TX4927_CCFG_TOE
 
- TX4927_CCFG_W1CBITS
 
- TX4927_CCFG_WDREXEN
 
- TX4927_CCFG_WDRST
 
- TX4927_CCFG_WR
 
- TX4927_CLKCTR_ACLCKD
 
- TX4927_CLKCTR_ACLRST
 
- TX4927_CLKCTR_DMACKD
 
- TX4927_CLKCTR_DMARST
 
- TX4927_CLKCTR_PCICKD
 
- TX4927_CLKCTR_PCIRST
 
- TX4927_CLKCTR_PIOCKD
 
- TX4927_CLKCTR_PIORST
 
- TX4927_CLKCTR_SIO0CKD
 
- TX4927_CLKCTR_SIO0RST
 
- TX4927_CLKCTR_SIO1CKD
 
- TX4927_CLKCTR_SIO1RST
 
- TX4927_CLKCTR_TM0CKD
 
- TX4927_CLKCTR_TM0RST
 
- TX4927_CLKCTR_TM1CKD
 
- TX4927_CLKCTR_TM1RST
 
- TX4927_CLKCTR_TM2CKD
 
- TX4927_CLKCTR_TM2RST
 
- TX4927_DMA_REG
 
- TX4927_EBUSC_BA
 
- TX4927_EBUSC_CR
 
- TX4927_EBUSC_REG
 
- TX4927_EBUSC_SIZE
 
- TX4927_EBUSC_WIDTH
 
- TX4927_IRC_INT
 
- TX4927_IRC_REG
 
- TX4927_IR_ACLC
 
- TX4927_IR_ACLCPME
 
- TX4927_IR_DMA
 
- TX4927_IR_ECCERR
 
- TX4927_IR_INT
 
- TX4927_IR_PCIC
 
- TX4927_IR_PCIERR
 
- TX4927_IR_PCIPME
 
- TX4927_IR_PDMAC
 
- TX4927_IR_PIO
 
- TX4927_IR_SIO
 
- TX4927_IR_TMR
 
- TX4927_IR_WTOERR
 
- TX4927_NR_SIO
 
- TX4927_NR_TMR
 
- TX4927_NUM_IR
 
- TX4927_NUM_IR_DMA
 
- TX4927_NUM_IR_INT
 
- TX4927_NUM_IR_SIO
 
- TX4927_NUM_IR_TMR
 
- TX4927_NUM_PIO
 
- TX4927_PCFG_DMASEL0_ACL0
 
- TX4927_PCFG_DMASEL0_ACL2
 
- TX4927_PCFG_DMASEL0_DRQ0
 
- TX4927_PCFG_DMASEL0_MASK
 
- TX4927_PCFG_DMASEL0_SIO1
 
- TX4927_PCFG_DMASEL1_ACL1
 
- TX4927_PCFG_DMASEL1_ACL3
 
- TX4927_PCFG_DMASEL1_DRQ1
 
- TX4927_PCFG_DMASEL1_MASK
 
- TX4927_PCFG_DMASEL1_SIO1
 
- TX4927_PCFG_DMASEL2_ACL0
 
- TX4927_PCFG_DMASEL2_ACL1
 
- TX4927_PCFG_DMASEL2_ACL2
 
- TX4927_PCFG_DMASEL2_DRQ2
 
- TX4927_PCFG_DMASEL2_MASK
 
- TX4927_PCFG_DMASEL2_SIO0
 
- TX4927_PCFG_DMASEL3_ACL1
 
- TX4927_PCFG_DMASEL3_ACL3
 
- TX4927_PCFG_DMASEL3_DRQ3
 
- TX4927_PCFG_DMASEL3_MASK
 
- TX4927_PCFG_DMASEL3_SIO0
 
- TX4927_PCFG_DMASEL_ALL
 
- TX4927_PCFG_PCICLKEN
 
- TX4927_PCFG_PCICLKEN_ALL
 
- TX4927_PCFG_SDCLKDLY
 
- TX4927_PCFG_SDCLKDLY_MASK
 
- TX4927_PCFG_SDCLKEN
 
- TX4927_PCFG_SDCLKEN_ALL
 
- TX4927_PCFG_SEL1
 
- TX4927_PCFG_SEL2
 
- TX4927_PCFG_SYSCLKEN
 
- TX4927_PCIC_G2PIOGBASE_BSDIS
 
- TX4927_PCIC_G2PIOGBASE_ECHG
 
- TX4927_PCIC_G2PMnGBASE_BSDIS
 
- TX4927_PCIC_G2PMnGBASE_ECHG
 
- TX4927_PCIC_G2PSTATUS_ALL
 
- TX4927_PCIC_G2PSTATUS_RTOE
 
- TX4927_PCIC_G2PSTATUS_TTOE
 
- TX4927_PCIC_IDSEL_AD_TO_SLOT
 
- TX4927_PCIC_MAX_DEVNU
 
- TX4927_PCIC_P2GIOGBASE_TBSDIS
 
- TX4927_PCIC_P2GIOGBASE_TECHG
 
- TX4927_PCIC_P2GIOGBASE_TIOEN
 
- TX4927_PCIC_P2GMnGBASE_TBSDIS
 
- TX4927_PCIC_P2GMnGBASE_TECHG
 
- TX4927_PCIC_P2GMnGBASE_TMEMEN
 
- TX4927_PCIC_PBACFG_BMCEN
 
- TX4927_PCIC_PBACFG_FIXPA
 
- TX4927_PCIC_PBACFG_PBAEN
 
- TX4927_PCIC_PBACFG_RPBA
 
- TX4927_PCIC_PBASTATUS_ALL
 
- TX4927_PCIC_PBASTATUS_BM
 
- TX4927_PCIC_PCICCFG_G2PIOEN
 
- TX4927_PCIC_PCICCFG_G2PM0EN
 
- TX4927_PCIC_PCICCFG_G2PM1EN
 
- TX4927_PCIC_PCICCFG_G2PM2EN
 
- TX4927_PCIC_PCICCFG_G2PMEN
 
- TX4927_PCIC_PCICCFG_GBWC_MASK
 
- TX4927_PCIC_PCICCFG_HRST
 
- TX4927_PCIC_PCICCFG_ICAEN
 
- TX4927_PCIC_PCICCFG_IRBER
 
- TX4927_PCIC_PCICCFG_SRST
 
- TX4927_PCIC_PCICCFG_TCAR
 
- TX4927_PCIC_PCICSTATUS_ALL
 
- TX4927_PCIC_PCICSTATUS_E2PDONE
 
- TX4927_PCIC_PCICSTATUS_GBE
 
- TX4927_PCIC_PCICSTATUS_IWB
 
- TX4927_PCIC_PCICSTATUS_NIB
 
- TX4927_PCIC_PCICSTATUS_PERR
 
- TX4927_PCIC_PCICSTATUS_PME
 
- TX4927_PCIC_PCICSTATUS_SERR
 
- TX4927_PCIC_PCICSTATUS_TLB
 
- TX4927_PCIC_PCICSTATUS_ZIB
 
- TX4927_PCIC_PCISTATUS_ALL
 
- TX4927_PCIC_PDMCFG_BSWAP
 
- TX4927_PCIC_PDMCFG_CHNEN
 
- TX4927_PCIC_PDMCFG_CHRST
 
- TX4927_PCIC_PDMCFG_ERRIE
 
- TX4927_PCIC_PDMCFG_EXFER
 
- TX4927_PCIC_PDMCFG_NCCMPIE
 
- TX4927_PCIC_PDMCFG_NTCMPIE
 
- TX4927_PCIC_PDMCFG_REQDLY_1024
 
- TX4927_PCIC_PDMCFG_REQDLY_128
 
- TX4927_PCIC_PDMCFG_REQDLY_16
 
- TX4927_PCIC_PDMCFG_REQDLY_256
 
- TX4927_PCIC_PDMCFG_REQDLY_32
 
- TX4927_PCIC_PDMCFG_REQDLY_512
 
- TX4927_PCIC_PDMCFG_REQDLY_64
 
- TX4927_PCIC_PDMCFG_REQDLY_MASK
 
- TX4927_PCIC_PDMCFG_REQDLY_NONE
 
- TX4927_PCIC_PDMCFG_RSTFIFO
 
- TX4927_PCIC_PDMCFG_XFRACT
 
- TX4927_PCIC_PDMCFG_XFRDIRC
 
- TX4927_PCIC_PDMCFG_XFRSIZE_1DW
 
- TX4927_PCIC_PDMCFG_XFRSIZE_1QW
 
- TX4927_PCIC_PDMCFG_XFRSIZE_4QW
 
- TX4927_PCIC_PDMCFG_XFRSIZE_MASK
 
- TX4927_PCIC_PDMSTS_ACCMP
 
- TX4927_PCIC_PDMSTS_ALL_CMP
 
- TX4927_PCIC_PDMSTS_ALL_ERR
 
- TX4927_PCIC_PDMSTS_CFGERR
 
- TX4927_PCIC_PDMSTS_CHNEN
 
- TX4927_PCIC_PDMSTS_CHNERR
 
- TX4927_PCIC_PDMSTS_DATAERR
 
- TX4927_PCIC_PDMSTS_DONEINT
 
- TX4927_PCIC_PDMSTS_ERRINT
 
- TX4927_PCIC_PDMSTS_FIFOCNT_MASK
 
- TX4927_PCIC_PDMSTS_FIFORP_MASK
 
- TX4927_PCIC_PDMSTS_FIFOWP_MASK
 
- TX4927_PCIC_PDMSTS_NCCMP
 
- TX4927_PCIC_PDMSTS_NTCMP
 
- TX4927_PCIC_PDMSTS_PCIERR
 
- TX4927_PCIC_PDMSTS_REQCNT_MASK
 
- TX4927_PCIC_PDMSTS_XFRACT
 
- TX4927_PCIC_REG
 
- TX4927_PIO_REG
 
- TX4927_REG_BASE
 
- TX4927_REG_SIZE
 
- TX4927_REV_PCODE
 
- TX4927_SDRAMC_BA
 
- TX4927_SDRAMC_CR
 
- TX4927_SDRAMC_REG
 
- TX4927_SDRAMC_SIZE
 
- TX4927_SIO_REG
 
- TX4927_TMR_REG
 
- TX4938_ACLC_REG
 
- TX4938_CCFG_ACEHOLD
 
- TX4938_CCFG_BCFG_MASK
 
- TX4938_CCFG_BEOW
 
- TX4938_CCFG_DIVMODE_10
 
- TX4938_CCFG_DIVMODE_12
 
- TX4938_CCFG_DIVMODE_16
 
- TX4938_CCFG_DIVMODE_18
 
- TX4938_CCFG_DIVMODE_2
 
- TX4938_CCFG_DIVMODE_2_5
 
- TX4938_CCFG_DIVMODE_3
 
- TX4938_CCFG_DIVMODE_4
 
- TX4938_CCFG_DIVMODE_4_5
 
- TX4938_CCFG_DIVMODE_8
 
- TX4938_CCFG_DIVMODE_MASK
 
- TX4938_CCFG_ENDIAN
 
- TX4938_CCFG_HALT
 
- TX4938_CCFG_PCI1DMD
 
- TX4938_CCFG_PCI1_66
 
- TX4938_CCFG_PCI66
 
- TX4938_CCFG_PCIARB
 
- TX4938_CCFG_PCIDIVMODE_10
 
- TX4938_CCFG_PCIDIVMODE_11
 
- TX4938_CCFG_PCIDIVMODE_4
 
- TX4938_CCFG_PCIDIVMODE_4_5
 
- TX4938_CCFG_PCIDIVMODE_5
 
- TX4938_CCFG_PCIDIVMODE_5_5
 
- TX4938_CCFG_PCIDIVMODE_8
 
- TX4938_CCFG_PCIDIVMODE_9
 
- TX4938_CCFG_PCIDIVMODE_MASK
 
- TX4938_CCFG_PCIMODE
 
- TX4938_CCFG_REG
 
- TX4938_CCFG_SYSSP_MASK
 
- TX4938_CCFG_TINTDIS
 
- TX4938_CCFG_TOE
 
- TX4938_CCFG_WDREXEN
 
- TX4938_CCFG_WDRST
 
- TX4938_CCFG_WR
 
- TX4938_CLKCTR_ACLCKD
 
- TX4938_CLKCTR_ACLRST
 
- TX4938_CLKCTR_DMA1CKD
 
- TX4938_CLKCTR_DMA1RST
 
- TX4938_CLKCTR_DMACKD
 
- TX4938_CLKCTR_DMARST
 
- TX4938_CLKCTR_ETH0CKD
 
- TX4938_CLKCTR_ETH0RST
 
- TX4938_CLKCTR_ETH1CKD
 
- TX4938_CLKCTR_ETH1RST
 
- TX4938_CLKCTR_NDFCKD
 
- TX4938_CLKCTR_NDFRST
 
- TX4938_CLKCTR_PCIC1CKD
 
- TX4938_CLKCTR_PCIC1RST
 
- TX4938_CLKCTR_PCICKD
 
- TX4938_CLKCTR_PCIRST
 
- TX4938_CLKCTR_PIOCKD
 
- TX4938_CLKCTR_PIORST
 
- TX4938_CLKCTR_SIO0CKD
 
- TX4938_CLKCTR_SIO0RST
 
- TX4938_CLKCTR_SIO1CKD
 
- TX4938_CLKCTR_SIO1RST
 
- TX4938_CLKCTR_SPICKD
 
- TX4938_CLKCTR_SPIRST
 
- TX4938_CLKCTR_SRAMCKD
 
- TX4938_CLKCTR_SRAMRST
 
- TX4938_CLKCTR_TM0CKD
 
- TX4938_CLKCTR_TM0RST
 
- TX4938_CLKCTR_TM1CKD
 
- TX4938_CLKCTR_TM1RST
 
- TX4938_CLKCTR_TM2CKD
 
- TX4938_CLKCTR_TM2RST
 
- TX4938_DMA_CCR_ACKPOL
 
- TX4938_DMA_CCR_CHDN
 
- TX4938_DMA_CCR_CHNEN
 
- TX4938_DMA_CCR_CHRST
 
- TX4938_DMA_CCR_DBINH
 
- TX4938_DMA_CCR_DNCTL
 
- TX4938_DMA_CCR_EGREQ
 
- TX4938_DMA_CCR_EXTRQ
 
- TX4938_DMA_CCR_IMMCHN
 
- TX4938_DMA_CCR_INTENC
 
- TX4938_DMA_CCR_INTENE
 
- TX4938_DMA_CCR_INTENT
 
- TX4938_DMA_CCR_INTRQD
 
- TX4938_DMA_CCR_LE
 
- TX4938_DMA_CCR_MEMIO
 
- TX4938_DMA_CCR_REQPL
 
- TX4938_DMA_CCR_RVBYTE
 
- TX4938_DMA_CCR_SBINH
 
- TX4938_DMA_CCR_SMPCHN
 
- TX4938_DMA_CCR_SNGAD
 
- TX4938_DMA_CCR_USEXFSZ
 
- TX4938_DMA_CCR_XFACT
 
- TX4938_DMA_CCR_XFSZ
 
- TX4938_DMA_CCR_XFSZ_16W
 
- TX4938_DMA_CCR_XFSZ_1W
 
- TX4938_DMA_CCR_XFSZ_2W
 
- TX4938_DMA_CCR_XFSZ_32W
 
- TX4938_DMA_CCR_XFSZ_4W
 
- TX4938_DMA_CCR_XFSZ_8W
 
- TX4938_DMA_CSR_ABCHC
 
- TX4938_DMA_CSR_CFERR
 
- TX4938_DMA_CSR_CHERR
 
- TX4938_DMA_CSR_CHNACT
 
- TX4938_DMA_CSR_CHNEN
 
- TX4938_DMA_CSR_DESERR
 
- TX4938_DMA_CSR_EXTDN
 
- TX4938_DMA_CSR_NCHNC
 
- TX4938_DMA_CSR_NTRNFC
 
- TX4938_DMA_CSR_SORERR
 
- TX4938_DMA_CSR_STLXFER
 
- TX4938_DMA_MCR_DIS
 
- TX4938_DMA_MCR_EIS
 
- TX4938_DMA_MCR_FIFUM
 
- TX4938_DMA_MCR_MSTEN
 
- TX4938_DMA_MCR_RPRT
 
- TX4938_DMA_MCR_RSFIF
 
- TX4938_DMA_REG
 
- TX4938_EBUSC_BA
 
- TX4938_EBUSC_CR
 
- TX4938_EBUSC_REG
 
- TX4938_EBUSC_SIZE
 
- TX4938_EBUSC_WIDTH
 
- TX4938_IRC_INT
 
- TX4938_IRC_REG
 
- TX4938_IR_ACLC
 
- TX4938_IR_ACLCPME
 
- TX4938_IR_DMA
 
- TX4938_IR_ECCERR
 
- TX4938_IR_ETH0
 
- TX4938_IR_ETH1
 
- TX4938_IR_INT
 
- TX4938_IR_NDFMC
 
- TX4938_IR_PCIC
 
- TX4938_IR_PCIC1
 
- TX4938_IR_PCIERR
 
- TX4938_IR_PCIPME
 
- TX4938_IR_PDMAC
 
- TX4938_IR_PIO
 
- TX4938_IR_SIO
 
- TX4938_IR_SPI
 
- TX4938_IR_TMR
 
- TX4938_IR_WTOERR
 
- TX4938_NDFMC_REG
 
- TX4938_NR_SIO
 
- TX4938_NR_TMR
 
- TX4938_NUM_IR
 
- TX4938_NUM_IR_DMA
 
- TX4938_NUM_IR_INT
 
- TX4938_NUM_IR_SIO
 
- TX4938_NUM_IR_TMR
 
- TX4938_NUM_PIO
 
- TX4938_PCFG_ATA_SEL
 
- TX4938_PCFG_DMASEL0_DRQ0
 
- TX4938_PCFG_DMASEL0_SIO1
 
- TX4938_PCFG_DMASEL1_DRQ1
 
- TX4938_PCFG_DMASEL1_SIO1
 
- TX4938_PCFG_DMASEL2_DRQ2
 
- TX4938_PCFG_DMASEL2_SIO0
 
- TX4938_PCFG_DMASEL3_DRQ3
 
- TX4938_PCFG_DMASEL3_SIO0
 
- TX4938_PCFG_DMASEL_ALL
 
- TX4938_PCFG_ETH0_SEL
 
- TX4938_PCFG_ETH1_SEL
 
- TX4938_PCFG_ISA_SEL
 
- TX4938_PCFG_NDF_SEL
 
- TX4938_PCFG_PCICLKEN
 
- TX4938_PCFG_PCICLKEN_ALL
 
- TX4938_PCFG_SDCLKDLY
 
- TX4938_PCFG_SDCLKDLY_MASK
 
- TX4938_PCFG_SDCLKEN
 
- TX4938_PCFG_SDCLKEN_ALL
 
- TX4938_PCFG_SEL1
 
- TX4938_PCFG_SEL2
 
- TX4938_PCFG_SPI_SEL
 
- TX4938_PCFG_SYSCLKEN
 
- TX4938_PCIC1_REG
 
- TX4938_PCIC_REG
 
- TX4938_PIO_REG
 
- TX4938_REG_BASE
 
- TX4938_REG_SIZE
 
- TX4938_REV_PCODE
 
- TX4938_SDRAMC_BA
 
- TX4938_SDRAMC_CR
 
- TX4938_SDRAMC_REG
 
- TX4938_SDRAMC_SIZE
 
- TX4938_SIO_REG
 
- TX4938_SPI_REG
 
- TX4938_SRAMC_REG
 
- TX4938_SRAM_SIZE
 
- TX4938_TMR_REG
 
- TX4939IDE_Add_Ctl
 
- TX4939IDE_AltStat_DevCtl
 
- TX4939IDE_BASE
 
- TX4939IDE_Bxfer_Cnt_Hi
 
- TX4939IDE_Bxfer_Cnt_Lo
 
- TX4939IDE_DMA_Cmd
 
- TX4939IDE_DMA_Stat
 
- TX4939IDE_Data
 
- TX4939IDE_DevHead
 
- TX4939IDE_Dev_TErr
 
- TX4939IDE_Error_Feature
 
- TX4939IDE_H_Rst_Tim
 
- TX4939IDE_IGNORE_INTS
 
- TX4939IDE_INT_ADDRERR
 
- TX4939IDE_INT_BUSERR
 
- TX4939IDE_INT_DEVTIMING
 
- TX4939IDE_INT_HOST
 
- TX4939IDE_INT_REACHMUL
 
- TX4939IDE_INT_TIMER
 
- TX4939IDE_INT_UDMATERM
 
- TX4939IDE_INT_XFEREND
 
- TX4939IDE_Int_Ctl
 
- TX4939IDE_LBA0
 
- TX4939IDE_LBA1
 
- TX4939IDE_LBA2
 
- TX4939IDE_Lo_Burst_Cnt
 
- TX4939IDE_PIO_Addr
 
- TX4939IDE_PRD_Ptr
 
- TX4939IDE_Pkt_Cmd
 
- TX4939IDE_Pkt_Xfer_Ctl
 
- TX4939IDE_Sec
 
- TX4939IDE_Sec_Cnt
 
- TX4939IDE_Start_Lo_Addr
 
- TX4939IDE_Start_TAddr
 
- TX4939IDE_Start_Up_Addr
 
- TX4939IDE_Stat_Cmd
 
- TX4939IDE_Sys_Ctl
 
- TX4939IDE_Up_Burst_Cnt
 
- TX4939IDE_Xfer_Cnt_1
 
- TX4939IDE_Xfer_Cnt_2
 
- TX4939_ACLC_REG
 
- TX4939_ATA_REG
 
- TX4939_ATA_REG_PHYS
 
- TX4939_CCFG_ACEHOLD
 
- TX4939_CCFG_ACKSEL
 
- TX4939_CCFG_ARMODE
 
- TX4939_CCFG_BCFG
 
- TX4939_CCFG_BCFG_MASK
 
- TX4939_CCFG_BEOW
 
- TX4939_CCFG_BESEL
 
- TX4939_CCFG_ENDIAN
 
- TX4939_CCFG_GTOT_1024
 
- TX4939_CCFG_GTOT_2048
 
- TX4939_CCFG_GTOT_4096
 
- TX4939_CCFG_GTOT_512
 
- TX4939_CCFG_GTOT_MASK
 
- TX4939_CCFG_MULCLK_10
 
- TX4939_CCFG_MULCLK_11
 
- TX4939_CCFG_MULCLK_12
 
- TX4939_CCFG_MULCLK_13
 
- TX4939_CCFG_MULCLK_14
 
- TX4939_CCFG_MULCLK_15
 
- TX4939_CCFG_MULCLK_8
 
- TX4939_CCFG_MULCLK_9
 
- TX4939_CCFG_MULCLK_MASK
 
- TX4939_CCFG_PCI66
 
- TX4939_CCFG_PCIARB
 
- TX4939_CCFG_PCIBOOT
 
- TX4939_CCFG_PCIMODE
 
- TX4939_CCFG_PTSEL
 
- TX4939_CCFG_REG
 
- TX4939_CCFG_ROMW
 
- TX4939_CCFG_SSCG
 
- TX4939_CCFG_SYSSP_MASK
 
- TX4939_CCFG_TINTDIS
 
- TX4939_CCFG_TOE
 
- TX4939_CCFG_WDREXEN
 
- TX4939_CCFG_WDRST
 
- TX4939_CCFG_WR
 
- TX4939_CCFG_YDIVMODE_2
 
- TX4939_CCFG_YDIVMODE_3
 
- TX4939_CCFG_YDIVMODE_5
 
- TX4939_CCFG_YDIVMODE_6
 
- TX4939_CCFG_YDIVMODE_MASK
 
- TX4939_CIR_REG
 
- TX4939_CLKCTR_ACLCKD
 
- TX4939_CLKCTR_ACLRST
 
- TX4939_CLKCTR_ATA0CKD
 
- TX4939_CLKCTR_ATA0RST
 
- TX4939_CLKCTR_ATA1CKD
 
- TX4939_CLKCTR_ATA1RST
 
- TX4939_CLKCTR_BROMCKD
 
- TX4939_CLKCTR_BROMRST
 
- TX4939_CLKCTR_CIRCKD
 
- TX4939_CLKCTR_CIRRST
 
- TX4939_CLKCTR_CYPCKD
 
- TX4939_CLKCTR_CYPRST
 
- TX4939_CLKCTR_DMA0CKD
 
- TX4939_CLKCTR_DMA0RST
 
- TX4939_CLKCTR_DMA1CKD
 
- TX4939_CLKCTR_DMA1RST
 
- TX4939_CLKCTR_EPCICKD
 
- TX4939_CLKCTR_EPCIRST
 
- TX4939_CLKCTR_ETH0CKD
 
- TX4939_CLKCTR_ETH0RST
 
- TX4939_CLKCTR_ETH1CKD
 
- TX4939_CLKCTR_ETH1RST
 
- TX4939_CLKCTR_I2CCKD
 
- TX4939_CLKCTR_I2CRST
 
- TX4939_CLKCTR_I2SCKD
 
- TX4939_CLKCTR_I2SRST
 
- TX4939_CLKCTR_IOSCKD
 
- TX4939_CLKCTR_IOSRST
 
- TX4939_CLKCTR_NDCCKD
 
- TX4939_CLKCTR_NDCRST
 
- TX4939_CLKCTR_PCI1CKD
 
- TX4939_CLKCTR_PCI1RST
 
- TX4939_CLKCTR_PCICCKD
 
- TX4939_CLKCTR_PCICRST
 
- TX4939_CLKCTR_SIO0CKD
 
- TX4939_CLKCTR_SIO0RST
 
- TX4939_CLKCTR_SIO1CKD
 
- TX4939_CLKCTR_SIO1RST
 
- TX4939_CLKCTR_SIO2CKD
 
- TX4939_CLKCTR_SIO2RST
 
- TX4939_CLKCTR_SIO3CKD
 
- TX4939_CLKCTR_SIO3RST
 
- TX4939_CLKCTR_SPICKD
 
- TX4939_CLKCTR_SPIRST
 
- TX4939_CLKCTR_SRAMCKD
 
- TX4939_CLKCTR_SRAMRST
 
- TX4939_CLKCTR_SYSCKD
 
- TX4939_CLKCTR_SYSRST
 
- TX4939_CLKCTR_TM0CKD
 
- TX4939_CLKCTR_TM0RST
 
- TX4939_CLKCTR_TM1CKD
 
- TX4939_CLKCTR_TM1RST
 
- TX4939_CLKCTR_TM2CKD
 
- TX4939_CLKCTR_TM2RST
 
- TX4939_CLKCTR_TM3CKD
 
- TX4939_CLKCTR_TM3RST
 
- TX4939_CLKCTR_TM4CKD
 
- TX4939_CLKCTR_TM4RST
 
- TX4939_CLKCTR_TM5CKD
 
- TX4939_CLKCTR_TM5RST
 
- TX4939_CLKCTR_VPCCKD
 
- TX4939_CLKCTR_VPCRST
 
- TX4939_CRYPTO_CSR_CDIV_DIV1
 
- TX4939_CRYPTO_CSR_CDIV_DIV1ALT
 
- TX4939_CRYPTO_CSR_CDIV_DIV2
 
- TX4939_CRYPTO_CSR_CDIV_DIV2ALT
 
- TX4939_CRYPTO_CSR_CDIV_MASK
 
- TX4939_CRYPTO_CSR_CSWAP_BOTH
 
- TX4939_CRYPTO_CSR_CSWAP_IN
 
- TX4939_CRYPTO_CSR_CSWAP_MASK
 
- TX4939_CRYPTO_CSR_CSWAP_NONE
 
- TX4939_CRYPTO_CSR_CSWAP_OUT
 
- TX4939_CRYPTO_CSR_DCINT
 
- TX4939_CRYPTO_CSR_ENCR
 
- TX4939_CRYPTO_CSR_GBINT
 
- TX4939_CRYPTO_CSR_GINTE
 
- TX4939_CRYPTO_CSR_INDXAST
 
- TX4939_CRYPTO_CSR_INDXAST_MASK
 
- TX4939_CRYPTO_CSR_INDXBST
 
- TX4939_CRYPTO_CSR_INDXBST_MASK
 
- TX4939_CRYPTO_CSR_PDINT_ALL
 
- TX4939_CRYPTO_CSR_PDINT_END
 
- TX4939_CRYPTO_CSR_PDINT_MASK
 
- TX4939_CRYPTO_CSR_PDINT_NEXT
 
- TX4939_CRYPTO_CSR_PDINT_NONE
 
- TX4939_CRYPTO_CSR_RSTC
 
- TX4939_CRYPTO_CSR_RSTD
 
- TX4939_CRYPTO_CSR_SAESI
 
- TX4939_CRYPTO_CSR_SAESO
 
- TX4939_CRYPTO_CSR_SDESI
 
- TX4939_CRYPTO_CSR_SDESO
 
- TX4939_CRYPTO_CSR_TOINT
 
- TX4939_CRYPTO_CTX_CMS
 
- TX4939_CRYPTO_CTX_DMS
 
- TX4939_CRYPTO_CTX_ENGINE_AES
 
- TX4939_CRYPTO_CTX_ENGINE_DES
 
- TX4939_CRYPTO_CTX_ENGINE_MASK
 
- TX4939_CRYPTO_CTX_ENGINE_MD5
 
- TX4939_CRYPTO_CTX_ENGINE_SHA1
 
- TX4939_CRYPTO_CTX_TDMS
 
- TX4939_CRYPTO_CTX_UPDATE
 
- TX4939_CRYPTO_DESC_ENCRYPT_IDX
 
- TX4939_CRYPTO_DESC_ENCRYPT_IDX_MASK
 
- TX4939_CRYPTO_DESC_END
 
- TX4939_CRYPTO_DESC_ERR_DIGEST
 
- TX4939_CRYPTO_DESC_ERR_MASK
 
- TX4939_CRYPTO_DESC_ERR_NONE
 
- TX4939_CRYPTO_DESC_ERR_TOUT
 
- TX4939_CRYPTO_DESC_HASH_IDX
 
- TX4939_CRYPTO_DESC_HASH_IDX_MASK
 
- TX4939_CRYPTO_DESC_IB_CNT
 
- TX4939_CRYPTO_DESC_IB_CNT_MASK
 
- TX4939_CRYPTO_DESC_LAST
 
- TX4939_CRYPTO_DESC_OB_CNT
 
- TX4939_CRYPTO_DESC_OB_CNT_MASK
 
- TX4939_CRYPTO_DESC_OWN
 
- TX4939_CRYPTO_DESC_START
 
- TX4939_CRYPTO_DESC_XOR
 
- TX4939_CRYPTO_NR_SET
 
- TX4939_CRYPTO_RCSR_FIN
 
- TX4939_CRYPTO_RCSR_INTE
 
- TX4939_CRYPTO_RCSR_RST
 
- TX4939_CRYPTO_RCSR_ST
 
- TX4939_CRYPTO_REG
 
- TX4939_DDRC_REG
 
- TX4939_DMA_REG
 
- TX4939_EBUSC_BA
 
- TX4939_EBUSC_CR
 
- TX4939_EBUSC_REG
 
- TX4939_EBUSC_SIZE
 
- TX4939_EBUSC_WIDTH
 
- TX4939_I2C_REG
 
- TX4939_I2S_REG
 
- TX4939_IRC_INT
 
- TX4939_IRC_REG
 
- TX4939_IR_ACLC
 
- TX4939_IR_ACLCPME
 
- TX4939_IR_ATA
 
- TX4939_IR_CIPHER
 
- TX4939_IR_CIR
 
- TX4939_IR_DDR
 
- TX4939_IR_DMA
 
- TX4939_IR_ETH
 
- TX4939_IR_I2C
 
- TX4939_IR_I2S
 
- TX4939_IR_INT
 
- TX4939_IR_INTA
 
- TX4939_IR_INTB
 
- TX4939_IR_INTC
 
- TX4939_IR_INTD
 
- TX4939_IR_IRC
 
- TX4939_IR_NDFMC
 
- TX4939_IR_NONE
 
- TX4939_IR_PCIC
 
- TX4939_IR_PCIC1
 
- TX4939_IR_PCIERR
 
- TX4939_IR_PCIPME
 
- TX4939_IR_PDMAC
 
- TX4939_IR_RND
 
- TX4939_IR_RTC
 
- TX4939_IR_SIO
 
- TX4939_IR_SPI
 
- TX4939_IR_TMR
 
- TX4939_IR_VIDEO
 
- TX4939_IR_WTOERR
 
- TX4939_NDFMC_REG
 
- TX4939_NR_SIO
 
- TX4939_NR_TMR
 
- TX4939_NUM_IR
 
- TX4939_NUM_IR_ATA
 
- TX4939_NUM_IR_DMA
 
- TX4939_NUM_IR_ETH
 
- TX4939_NUM_IR_INT
 
- TX4939_NUM_IR_SIO
 
- TX4939_NUM_IR_TMR
 
- TX4939_PCFG_ATA0MODE
 
- TX4939_PCFG_ATA1MODE
 
- TX4939_PCFG_BP_PLL
 
- TX4939_PCFG_DMASEL0
 
- TX4939_PCFG_DMASEL0_DRQ0
 
- TX4939_PCFG_DMASEL1
 
- TX4939_PCFG_DMASEL1_DRQ1
 
- TX4939_PCFG_DMASEL2
 
- TX4939_PCFG_DMASEL2_DRQ2
 
- TX4939_PCFG_DMASEL2_SIO0
 
- TX4939_PCFG_DMASEL3
 
- TX4939_PCFG_DMASEL3_NDFC
 
- TX4939_PCFG_DMASEL3_SIO0
 
- TX4939_PCFG_DMASEL_ALL
 
- TX4939_PCFG_ET0MODE
 
- TX4939_PCFG_ET1MODE
 
- TX4939_PCFG_I2CMODE
 
- TX4939_PCFG_I2SMODE_ACLC
 
- TX4939_PCFG_I2SMODE_GPIO
 
- TX4939_PCFG_I2SMODE_I2S
 
- TX4939_PCFG_I2SMODE_I2S_ALT
 
- TX4939_PCFG_I2SMODE_MASK
 
- TX4939_PCFG_ITMODE
 
- TX4939_PCFG_PCICLKEN
 
- TX4939_PCFG_PCICLKEN_ALL
 
- TX4939_PCFG_SIO2MODE_GPIO
 
- TX4939_PCFG_SIO2MODE_MASK
 
- TX4939_PCFG_SIO2MODE_SIO0
 
- TX4939_PCFG_SIO2MODE_SIO2
 
- TX4939_PCFG_SIO3MODE
 
- TX4939_PCFG_SPEED0
 
- TX4939_PCFG_SPEED1
 
- TX4939_PCFG_SPIMODE
 
- TX4939_PCFG_SYSCLKEN
 
- TX4939_PCFG_VPSMODE
 
- TX4939_PCFG_VSSMODE
 
- TX4939_PCIC1_REG
 
- TX4939_PCIC_REG
 
- TX4939_REG_BASE
 
- TX4939_REG_SIZE
 
- TX4939_REV_MAJ_MIN
 
- TX4939_REV_PCODE
 
- TX4939_RNG_RCSR
 
- TX4939_RNG_RCSR_FIN
 
- TX4939_RNG_RCSR_INTE
 
- TX4939_RNG_RCSR_RST
 
- TX4939_RNG_RCSR_ST
 
- TX4939_RNG_REG
 
- TX4939_RNG_ROR
 
- TX4939_RTCCTL_ALMD
 
- TX4939_RTCCTL_ALME
 
- TX4939_RTCCTL_BUSY
 
- TX4939_RTCCTL_COMMAND
 
- TX4939_RTCCTL_COMMAND_GETALARM
 
- TX4939_RTCCTL_COMMAND_GETTIME
 
- TX4939_RTCCTL_COMMAND_NOP
 
- TX4939_RTCCTL_COMMAND_SETALARM
 
- TX4939_RTCCTL_COMMAND_SETTIME
 
- TX4939_RTCTBC_COMP
 
- TX4939_RTCTBC_PM
 
- TX4939_RTC_REG
 
- TX4939_RTC_REG_RAMSIZE
 
- TX4939_RTC_REG_RWBSIZE
 
- TX4939_SCLK0
 
- TX4939_SIO_REG
 
- TX4939_SPI_REG
 
- TX4939_SRAMC_REG
 
- TX4939_SRAM_SIZE
 
- TX4939_TMR_REG
 
- TX4939_VPC_CSR_GBINT
 
- TX4939_VPC_CSR_GINTE
 
- TX4939_VPC_CSR_RSTD
 
- TX4939_VPC_CSR_RSTVPC
 
- TX4939_VPC_CSR_SWAPI
 
- TX4939_VPC_CSR_SWAPO
 
- TX4939_VPC_CTRLA_DCINT
 
- TX4939_VPC_CTRLA_ENVPC
 
- TX4939_VPC_CTRLA_PBUSY
 
- TX4939_VPC_CTRLA_PDINT_ALL
 
- TX4939_VPC_CTRLA_PDINT_MASK
 
- TX4939_VPC_CTRLA_PDINT_NEXT
 
- TX4939_VPC_CTRLA_PDINT_NONE
 
- TX4939_VPC_CTRLA_UOINT
 
- TX4939_VPC_CTRLA_VDFOR
 
- TX4939_VPC_CTRLA_VDMODE
 
- TX4939_VPC_CTRLA_VDPSN
 
- TX4939_VPC_CTRLA_VDVLDP
 
- TX4939_VPC_DESC_CTRL1_ERR_MASK
 
- TX4939_VPC_DESC_CTRL1_OWN
 
- TX4939_VPC_REG
 
- TX49XX_ICACHE_INDEX_INV_WAR
 
- TX49_CONF_CWFON
 
- TX49_CONF_DC
 
- TX49_CONF_HALT
 
- TX49_CONF_IC
 
- TX4_A_MARK
 
- TX4_B_MARK
 
- TX4_C_MARK
 
- TX4_D_MARK
 
- TX4_E_MARK
 
- TX4_MARK
 
- TX4_PD_RAM
 
- TX5_A_MARK
 
- TX5_B_MARK
 
- TX5_C_MARK
 
- TX5_D_MARK
 
- TX5_E_MARK
 
- TX5_F_MARK
 
- TX5_MARK
 
- TX64_DEV_CNTR_ELEM
 
- TXAAL5_PROTO
 
- TXABORT
 
- TXABTIE
 
- TXABTIF
 
- TXAC
 
- TXACKCSR0
 
- TXACKE
 
- TXACKflag
 
- TXADDR1_ABR
 
- TXADDR1_SET_SIZE
 
- TXAGC
 
- TXAGG_FRAMETAG
 
- TXALCR0
 
- TXALCR1
 
- TXALLOCFID
 
- TXA_CTRL
 
- TXA_DIS_ALLOC
 
- TXA_DIS_ARB
 
- TXA_DIS_FSYNC
 
- TXA_ENA_ALLOC
 
- TXA_ENA_ARB
 
- TXA_ENA_FSYNC
 
- TXA_INT_T_OFF
 
- TXA_INT_T_ON
 
- TXA_INT_T_STEP
 
- TXA_ITI_INI
 
- TXA_ITI_VAL
 
- TXA_LIM_INI
 
- TXA_LIM_T_OFF
 
- TXA_LIM_T_ON
 
- TXA_LIM_T_STEP
 
- TXA_LIM_VAL
 
- TXA_MAX_VAL
 
- TXA_PRIO_XS
 
- TXA_START_RC
 
- TXA_STAT
 
- TXA_STOP_RC
 
- TXA_TEST
 
- TXA_UNDF
 
- TXBAE
 
- TXBB_SIZE
 
- TXBCTRL
 
- TXBCTRL_ABTF
 
- TXBCTRL_MLOA
 
- TXBCTRL_OFF
 
- TXBCTRL_TXERR
 
- TXBCTRL_TXREQ
 
- TXBC_NDTB_MASK
 
- TXBC_NDTB_SHIFT
 
- TXBC_TFQS_MASK
 
- TXBC_TFQS_SHIFT
 
- TXBDAT_OFF
 
- TXBDLC
 
- TXBDLC_OFF
 
- TXBD_CRC
 
- TXBD_DEF
 
- TXBD_HUGEFRAME
 
- TXBD_INTERRUPT
 
- TXBD_LAST
 
- TXBD_LATECOLLISION
 
- TXBD_PADCRC
 
- TXBD_READY
 
- TXBD_RETRYCOUNTMASK
 
- TXBD_RETRYLIMIT
 
- TXBD_RING_SIZE
 
- TXBD_TOE
 
- TXBD_UNDERRUN
 
- TXBD_WRAP
 
- TXBE
 
- TXBEID0
 
- TXBEID0_OFF
 
- TXBEID8
 
- TXBEID8_OFF
 
- TXBF
 
- TXBIT
 
- TXBR
 
- TXBSIDH
 
- TXBSIDH_OFF
 
- TXBSIDL
 
- TXBSIDL_OFF
 
- TXBUFCLR
 
- TXBUFFER_BASE
 
- TXBUFFER_SIZE
 
- TXBUFLEN
 
- TXBUFSIZE
 
- TXBUSY
 
- TXBW
 
- TXB_ELEMENT_SIZE
 
- TXB_RQ
 
- TXB_UNDF
 
- TXC
 
- TXC0_MODE_TXLPF
 
- TXC0_PA_TSSI_EN
 
- TXC0_TSSI_EN
 
- TXC1_OFF_I_MASK
 
- TXC1_OFF_Q_MASK
 
- TXC1_PA_GAIN_2DB
 
- TXC1_PA_GAIN_3DB
 
- TXC1_PA_GAIN_MASK
 
- TXC1_TX_MIX_GAIN
 
- TXCB_DELAY
 
- TXCB_INT_WHEN_DONE
 
- TXCB_INVALID
 
- TXCB_MCR
 
- TXCB_VALID
 
- TXCEIE
 
- TXCF
 
- TXCFF_EMPTY_INT
 
- TXCFF_FULL_INT
 
- TXCFG
 
- TXCFG_ATP
 
- TXCFG_AUTO_FIFO
 
- TXCFG_BRST_DIS
 
- TXCFG_CSI
 
- TXCFG_ECRETRY
 
- TXCFG_EMPTY
 
- TXCFG_HBI
 
- TXCFG_MLB
 
- TXCFG_MXDMA1024
 
- TXCFG_MXDMA128
 
- TXCFG_MXDMA16
 
- TXCFG_MXDMA256
 
- TXCFG_MXDMA32
 
- TXCFG_MXDMA512
 
- TXCFG_MXDMA64
 
- TXCFG_MXDMA8
 
- TXCF_ADDR
 
- TXCHAIN_DEF
 
- TXCHAIN_DEF_HTPHY
 
- TXCHAIN_DEF_NPHY
 
- TXCHAN
 
- TXCHAN_EVT0
 
- TXCHAN_EVT1
 
- TXCHECKSUM_ERROR
 
- TXCHK_CHG_TYPE_DIS1
 
- TXCHK_CHG_TYPE_ENAB1
 
- TXCHK_CHG_TYPE_KERN
 
- TXCHK_CHG_TYPE_USER
 
- TXCHK_PKT_RDY_THRESH
 
- TXCH_MASK
 
- TXCL
 
- TXCLCAL_DONE
 
- TXCLKESC_REG
 
- TXCLKRST
 
- TXCLK_MUX_SELECT_RCLK
 
- TXCLK_TCD
 
- TXCL_ADDR
 
- TXCMD_QUEUE
 
- TXCMD_QUEUE_INX
 
- TXCMD_RESET_RX_PKT_BUFF
 
- TXCMD_RESET_TX_PKT_BUFF
 
- TXCMD_SET_RX_RSSI
 
- TXCMD_SET_TX_DURATION
 
- TXCMD_SET_TX_PWR_TRACKING
 
- TXCMD_TXRA_HISTORY_CTRL
 
- TXCMD_XXXX_CTRL
 
- TXCNAME
 
- TXCOMPLFID
 
- TXCRCEN
 
- TXCRCEXCL
 
- TXCRCINIT
 
- TXCR_FTXQ
 
- TXCR_TCGICMP
 
- TXCR_TCGIP
 
- TXCR_TCGTCP
 
- TXCR_TCGUDP
 
- TXCR_TXCRC
 
- TXCR_TXE
 
- TXCR_TXFCE
 
- TXCR_TXPE
 
- TXCSR0
 
- TXCSR0_ABORT
 
- TXCSR0_KICK_ATIM
 
- TXCSR0_KICK_PRIO
 
- TXCSR0_KICK_TX
 
- TXCSR1
 
- TXCSR1_ACK_CONSUME_TIME
 
- TXCSR1_ACK_TIMEOUT
 
- TXCSR1_AUTORESPONDER
 
- TXCSR1_TSF_OFFSET
 
- TXCSR2
 
- TXCSR2_NUM_ATIM
 
- TXCSR2_NUM_PRIO
 
- TXCSR2_NUM_TXD
 
- TXCSR2_TXD_SIZE
 
- TXCSR3
 
- TXCSR3_TX_RING_REGISTER
 
- TXCSR4
 
- TXCSR4_ATIM_RING_REGISTER
 
- TXCSR5
 
- TXCSR5_PRIO_RING_REGISTER
 
- TXCSR6
 
- TXCSR6_BEACON_RING_REGISTER
 
- TXCSR7
 
- TXCSR7_AR_POWERMANAGEMENT
 
- TXCSR8
 
- TXCSR8_BBP_ID0
 
- TXCSR8_BBP_ID0_VALID
 
- TXCSR8_BBP_ID1
 
- TXCSR8_BBP_ID1_VALID
 
- TXCSR8_BBP_ID2
 
- TXCSR8_BBP_ID2_VALID
 
- TXCSR8_BBP_ID3
 
- TXCSR8_BBP_ID3_VALID
 
- TXCSR9
 
- TXCSR9_OFDM_LENGTH_HIGH
 
- TXCSR9_OFDM_LENGTH_LOW
 
- TXCSR9_OFDM_RATE
 
- TXCSR9_OFDM_SERVICE
 
- TXCS_BURST
 
- TXCS_DEFAULT
 
- TXCS_DMASIZE
 
- TXCS_DMASIZE_128B
 
- TXCS_DMASIZE_256B
 
- TXCS_DMASIZE_512B
 
- TXCS_DMASIZE_64B
 
- TXCS_ENABLE
 
- TXCS_FIFOTH
 
- TXCS_FIFOTH_12QW
 
- TXCS_FIFOTH_16QW
 
- TXCS_FIFOTH_4QW
 
- TXCS_FIFOTH_8QW
 
- TXCS_QUEUE0S
 
- TXCS_QUEUE1S
 
- TXCS_QUEUE2S
 
- TXCS_QUEUE3S
 
- TXCS_QUEUE4S
 
- TXCS_QUEUE5S
 
- TXCS_QUEUE6S
 
- TXCS_QUEUE7S
 
- TXCS_SELECT_QUEUE0
 
- TXCS_SELECT_QUEUE1
 
- TXCS_SELECT_QUEUE2
 
- TXCS_SELECT_QUEUE3
 
- TXCS_SELECT_QUEUE4
 
- TXCS_SELECT_QUEUE5
 
- TXCS_SELECT_QUEUE6
 
- TXCS_SELECT_QUEUE7
 
- TXCTL_802_11
 
- TXCTL_802_3
 
- TXCTL_DMWTLAT
 
- TXCTL_ETHERNET
 
- TXCTL_LLC
 
- TXCTL_NORELEASE
 
- TXCTL_RELEASE
 
- TXCTL_TXEX
 
- TXCTL_TXOK
 
- TXC_ALRGS_ARXCTL
 
- TXC_ALRGS_ATXAMP0
 
- TXC_ALRGS_ATXAMP1
 
- TXC_ALRGS_ATXCTL
 
- TXC_ALRGS_ATXPRE0
 
- TXC_ALRGS_ATXPRE1
 
- TXC_ALT_TXPWR
 
- TXC_AMIC
 
- TXC_AMPDU_FBR
 
- TXC_AMPDU_FIRST
 
- TXC_AMPDU_LAST
 
- TXC_AMPDU_MASK
 
- TXC_AMPDU_MIDDLE
 
- TXC_AMPDU_NONE
 
- TXC_AMPDU_SHIFT
 
- TXC_ARXCTL_RXPD0_LBN
 
- TXC_ARXCTL_RXPD1_LBN
 
- TXC_ARXCTL_RXPD2_LBN
 
- TXC_ARXCTL_RXPD3_LBN
 
- TXC_ATXAMP_0440_mV
 
- TXC_ATXAMP_0580_mV
 
- TXC_ATXAMP_0720_mV
 
- TXC_ATXAMP_0820_BOTH
 
- TXC_ATXAMP_0820_mV
 
- TXC_ATXAMP_1060_mV
 
- TXC_ATXAMP_1120_mV
 
- TXC_ATXAMP_1200_mV
 
- TXC_ATXAMP_1280_mV
 
- TXC_ATXAMP_DEFAULT
 
- TXC_ATXAMP_LANE02_LBN
 
- TXC_ATXAMP_LANE13_LBN
 
- TXC_ATXCTL_TXPD0_LBN
 
- TXC_ATXCTL_TXPD1_LBN
 
- TXC_ATXCTL_TXPD2_LBN
 
- TXC_ATXCTL_TXPD3_LBN
 
- TXC_ATXPRE_DEFAULT
 
- TXC_ATXPRE_NONE
 
- TXC_BIST_CTL
 
- TXC_BIST_CTRL_B10EN_LBN
 
- TXC_BIST_CTRL_ENAB_LBN
 
- TXC_BIST_CTRL_STOP_LBN
 
- TXC_BIST_CTRL_STRT_LBN
 
- TXC_BIST_CTRL_TYPE_CJP
 
- TXC_BIST_CTRL_TYPE_CRP
 
- TXC_BIST_CTRL_TYPE_LBN
 
- TXC_BIST_CTRL_TYPE_TSD
 
- TXC_BIST_CTRL_TYPE_TSR
 
- TXC_BIST_DURATION
 
- TXC_BIST_RX0ERRCNT
 
- TXC_BIST_RX0FRMCNT
 
- TXC_BIST_RX1ERRCNT
 
- TXC_BIST_RX1FRMCNT
 
- TXC_BIST_RX2ERRCNT
 
- TXC_BIST_RX2FRMCNT
 
- TXC_BIST_RX3ERRCNT
 
- TXC_BIST_RX3FRMCNT
 
- TXC_BIST_TXFRMCNT
 
- TXC_BW_40
 
- TXC_CONTROL
 
- TXC_CONTROL_ENABLE
 
- TXC_CONTROL_PORT_ENABLE
 
- TXC_DEBUG
 
- TXC_DEBUG_SELECT
 
- TXC_DFCS
 
- TXC_DMA_MAX
 
- TXC_DMA_MAX_LEN
 
- TXC_FREQBAND_5G
 
- TXC_GLCMD_L01PD_LBN
 
- TXC_GLCMD_L23PD_LBN
 
- TXC_GLCMD_LMTSWRST_LBN
 
- TXC_GLRGS_GLCMD
 
- TXC_GLRGS_GSGQLCTL
 
- TXC_GPIO_DIR
 
- TXC_GPIO_DIR_INPUT
 
- TXC_GPIO_DIR_OUTPUT
 
- TXC_GPIO_OUTPUT
 
- TXC_GSGQLCT_LNSL_LBN
 
- TXC_GSGQLCT_LNSL_WIDTH
 
- TXC_GSGQLCT_SGQLEN_LBN
 
- TXC_HWSEQ
 
- TXC_IGNOREPMQ
 
- TXC_IMMEDACK
 
- TXC_INT_MASK
 
- TXC_INT_MASK_ALL
 
- TXC_INT_MASK_PKTASM_DEAD
 
- TXC_INT_MASK_REORDER_ERR
 
- TXC_INT_MASK_RO_CE
 
- TXC_INT_MASK_RO_UE
 
- TXC_INT_MASK_SF_CE
 
- TXC_INT_MASK_SF_UE
 
- TXC_INT_MASK_VAL
 
- TXC_INT_MASK_VAL_SHIFT
 
- TXC_INT_STAT
 
- TXC_INT_STAT_DBG
 
- TXC_INT_STAT_PKTASM_DEAD
 
- TXC_INT_STAT_REORDER_ERR
 
- TXC_INT_STAT_RO_CE
 
- TXC_INT_STAT_RO_UE
 
- TXC_INT_STAT_SF_CE
 
- TXC_INT_STAT_SF_UE
 
- TXC_INT_STAT_VAL
 
- TXC_INT_STAT_VAL_SHIFT
 
- TXC_INV
 
- TXC_LONGFRAME
 
- TXC_LOOPBACKS
 
- TXC_MAX_REORDER
 
- TXC_MAX_REORDER_PORT0
 
- TXC_MAX_REORDER_PORT1
 
- TXC_MAX_REORDER_PORT2
 
- TXC_MAX_REORDER_PORT3
 
- TXC_MAX_RESET_TIME
 
- TXC_MCTL_RESET_LBN
 
- TXC_MCTL_RXLED_LBN
 
- TXC_MCTL_TXLED_LBN
 
- TXC_MRGS_CTL
 
- TXC_MTDIABLO_CTRL
 
- TXC_MTDIABLO_CTRL_PMA_LOOP_LBN
 
- TXC_PKT_STUFFED
 
- TXC_PKT_STUFFED_PP_PACKETASSY
 
- TXC_PKT_STUFFED_PP_REORDER
 
- TXC_PKT_XMIT
 
- TXC_PKT_XMIT_BYTES
 
- TXC_PKT_XMIT_PKTS
 
- TXC_PORT_CTL
 
- TXC_PORT_CTL_CLR_ALL_STAT
 
- TXC_PORT_DMA
 
- TXC_PORT_PACKET_REQ
 
- TXC_PORT_PACKET_REQ_GATHER_REQ
 
- TXC_PORT_PACKET_REQ_PERR_ABRT
 
- TXC_PORT_PACKET_REQ_PKT_REQ
 
- TXC_PREAMBLE_DATA_FB_SHORT
 
- TXC_PREAMBLE_RTS_FB_SHORT
 
- TXC_PREAMBLE_RTS_MAIN_SHORT
 
- TXC_REQUIRED_DEVS
 
- TXC_RESET_WAIT
 
- TXC_ROECC_CE
 
- TXC_ROECC_CLR_ST
 
- TXC_ROECC_CTL
 
- TXC_ROECC_CTL_1ST_PKT_LINE
 
- TXC_ROECC_CTL_2ND_PKT_LINE
 
- TXC_ROECC_CTL_ALL_PKTS
 
- TXC_ROECC_CTL_ALT_PKTS
 
- TXC_ROECC_CTL_DBL_BIT_ERR
 
- TXC_ROECC_CTL_DISABLE_UE
 
- TXC_ROECC_CTL_LST_PKT_LINE
 
- TXC_ROECC_CTL_ONE_PKT_ONLY
 
- TXC_ROECC_CTL_SNGL_BIT_ERR
 
- TXC_ROECC_ST
 
- TXC_ROECC_ST_ECC_ADDR
 
- TXC_ROECC_UE
 
- TXC_RO_CTL
 
- TXC_RO_CTL_ADDR_FAILED
 
- TXC_RO_CTL_CAPT_ADDR_FAILED
 
- TXC_RO_CTL_CAPT_DMA_FAILED
 
- TXC_RO_CTL_CAPT_LEN_FAILED
 
- TXC_RO_CTL_CLR_FAIL_STATE
 
- TXC_RO_CTL_DMA_FAILED
 
- TXC_RO_CTL_LEN_FAILED
 
- TXC_RO_CTL_RO_ADDR
 
- TXC_RO_CTL_RO_STATE_ADDR
 
- TXC_RO_CTL_RO_STATE_RD
 
- TXC_RO_CTL_RO_STATE_RD_DONE
 
- TXC_RO_CTL_RO_STATE_WR
 
- TXC_RO_CTL_RO_STATE_WR_DONE
 
- TXC_RO_DATA0
 
- TXC_RO_DATA0_DATA0
 
- TXC_RO_DATA1
 
- TXC_RO_DATA1_DATA1
 
- TXC_RO_DATA2
 
- TXC_RO_DATA2_DATA2
 
- TXC_RO_DATA3
 
- TXC_RO_DATA3_DATA3
 
- TXC_RO_DATA4
 
- TXC_RO_DATA4_DATA4
 
- TXC_RO_STATE0
 
- TXC_RO_STATE0_DUPLICATE_TID
 
- TXC_RO_STATE1
 
- TXC_RO_STATE1_UNUSED_TID
 
- TXC_RO_STATE2
 
- TXC_RO_STATE2_TRANS_TIMEOUT
 
- TXC_RO_STATE3
 
- TXC_RO_STATE3_ENAB_RO_WMARK
 
- TXC_RO_STATE3_ENAB_SPC_WMARK
 
- TXC_RO_STATE3_HIGH_RO_USED
 
- TXC_RO_STATE3_NUM_RO_USED
 
- TXC_RO_STATE3_ROFIFO_SPC_AVAIL
 
- TXC_RO_STATE3_RO_SPC_WMARK
 
- TXC_RO_ST_DATA0
 
- TXC_RO_ST_DATA0_DATA0
 
- TXC_RO_ST_DATA1
 
- TXC_RO_ST_DATA1_DATA1
 
- TXC_RO_ST_DATA2
 
- TXC_RO_ST_DATA2_DATA2
 
- TXC_RO_ST_DATA3
 
- TXC_RO_ST_DATA3_DATA3
 
- TXC_RO_TIDS
 
- TXC_RO_TIDS_IN_USE
 
- TXC_SECKEY_MASK
 
- TXC_SECKEY_SHIFT
 
- TXC_SECTYPE_MASK
 
- TXC_SECTYPE_SHIFT
 
- TXC_SENDCTS
 
- TXC_SENDRTS
 
- TXC_SFECC_CTL
 
- TXC_SFECC_CTL_1ST_PKT_LINE
 
- TXC_SFECC_CTL_2ND_PKT_LINE
 
- TXC_SFECC_CTL_ALL_PKTS
 
- TXC_SFECC_CTL_ALT_PKTS
 
- TXC_SFECC_CTL_DBL_BIT_ERR
 
- TXC_SFECC_CTL_DISABLE_UE
 
- TXC_SFECC_CTL_LST_PKT_LINE
 
- TXC_SFECC_CTL_ONE_PKT_ONLY
 
- TXC_SFECC_CTL_SNGL_BIT_ERR
 
- TXC_SFECC_ST
 
- TXC_SFECC_ST_CE
 
- TXC_SFECC_ST_CLR_ST
 
- TXC_SFECC_ST_ECC_ADDR
 
- TXC_SFECC_ST_UE
 
- TXC_SF_DATA0
 
- TXC_SF_DATA0_DATA0
 
- TXC_SF_DATA1
 
- TXC_SF_DATA1_DATA1
 
- TXC_SF_DATA2
 
- TXC_SF_DATA2_DATA2
 
- TXC_SF_DATA3
 
- TXC_SF_DATA3_DATA3
 
- TXC_SF_DATA4
 
- TXC_SF_DATA4_DATA4
 
- TXC_STARTMSDU
 
- TXC_TRAINING_VEC
 
- TXC_TRAINING_VEC_MASK
 
- TXC_UNDF
 
- TXC_USBS_EP1RDY
 
- TXC_USBS_RXFAULT
 
- TXC_USBS_SUSFLAG
 
- TXC_USBS_TXC0
 
- TXC_USBS_TXC1
 
- TXC_USBS_TXC2
 
- TXD
 
- TXD0_MARK
 
- TXD1_MARK
 
- TXD2_MARK
 
- TXD3_MARK
 
- TXD4_MARK
 
- TXD5_MARK
 
- TXD6_MARK
 
- TXD7_MARK
 
- TXDATA0
 
- TXDATA1
 
- TXDATA2
 
- TXDATA3
 
- TXDATADMADIS
 
- TXDATAFIFO_M
 
- TXDATAFIFO_S
 
- TXDATAFIFO_V
 
- TXDATA_SKB_LEN
 
- TXDA_BGREF_EN
 
- TXDA_CAL_LATCH_EN
 
- TXDA_COEFF_CALC_CTRL
 
- TXDA_CYA_AUXDA_CYA
 
- TXDA_DECAP_EN
 
- TXDA_DECAP_EN_DEL
 
- TXDA_DP_AUX_EN
 
- TXDA_DRV_CMN_MODE_EN
 
- TXDA_DRV_IDLE_LOWI_EN
 
- TXDA_DRV_LDO_BG_FB_EN
 
- TXDA_DRV_LDO_BG_REF_EN
 
- TXDA_DRV_LDO_EN
 
- TXDA_DRV_LDO_RBYR_FB_EN
 
- TXDA_DRV_LDO_REDC_SINKIQ
 
- TXDA_DRV_POWER_EN_PH_1_N
 
- TXDA_DRV_POWER_EN_PH_2_N
 
- TXDA_DRV_POWER_ISOLATION_EN
 
- TXDA_DRV_PREDRV_EN
 
- TXDA_DRV_PREDRV_EN_DEL
 
- TXDA_DRV_RST_PULL_DOWN
 
- TXDA_LOW_LEAKAGE_EN
 
- TXDA_LPBK_ISI_GEN_EN
 
- TXDA_LPBK_LINE_EN
 
- TXDA_LPBK_RECOVERED_CLK_EN
 
- TXDA_LPBK_SERIAL_EN
 
- TXDA_MPHY_ENABLE_HS_NT
 
- TXDA_MPHY_SA_MODE
 
- TXDA_UPHY_SUPPLY_EN
 
- TXDA_UPHY_SUPPLY_EN_DEL
 
- TXDCTRL_BUFSZ
 
- TXDCTRL_CENAB
 
- TXDCTRL_COFF
 
- TXDCTRL_CSTART
 
- TXDCTRL_EOF
 
- TXDCTRL_INTME
 
- TXDCTRL_NOCRC
 
- TXDCTRL_SOF
 
- TXDDL_SHIFT
 
- TXDDS_EXTRA_SZ
 
- TXDDS_MFG_SZ
 
- TXDDS_TABLE_SZ
 
- TXDE
 
- TXDEBUG
 
- TXDESC
 
- TXDESC32_ACK_REPORT
 
- TXDESC32_AGG_BREAK
 
- TXDESC32_AGG_ENABLE
 
- TXDESC32_CTS_SELF_ENABLE
 
- TXDESC32_HW_RTS_ENABLE
 
- TXDESC32_HW_SEQ_ENABLE
 
- TXDESC32_QOS
 
- TXDESC32_RETRY_LIMIT_ENABLE
 
- TXDESC32_RETRY_LIMIT_MASK
 
- TXDESC32_RETRY_LIMIT_SHIFT
 
- TXDESC32_RTS_CTS_ENABLE
 
- TXDESC32_RTS_RATE_MASK
 
- TXDESC32_RTS_RATE_SHIFT
 
- TXDESC32_SEQ_MASK
 
- TXDESC32_SEQ_SHIFT
 
- TXDESC32_SHORT_GI
 
- TXDESC32_SHORT_PREAMBLE
 
- TXDESC32_USE_DRIVER_RATE
 
- TXDESC40_AGG_BREAK
 
- TXDESC40_AGG_ENABLE
 
- TXDESC40_BT_INT
 
- TXDESC40_CCA_RTS_MASK
 
- TXDESC40_CCA_RTS_SHIFT
 
- TXDESC40_CTS_SELF_ENABLE
 
- TXDESC40_DATA_RATE_FB_MASK
 
- TXDESC40_DATA_RATE_FB_SHIFT
 
- TXDESC40_GID_SHIFT
 
- TXDESC40_HW_RTS_ENABLE
 
- TXDESC40_HW_SEQ_ENABLE
 
- TXDESC40_LSIG_TXOP_ENABLE
 
- TXDESC40_MACID_MASK
 
- TXDESC40_MACID_SHIFT
 
- TXDESC40_MORE_FRAG
 
- TXDESC40_PAID_MASK
 
- TXDESC40_PAID_SHIFT
 
- TXDESC40_PIFS
 
- TXDESC40_RAW
 
- TXDESC40_RDG_ENABLE
 
- TXDESC40_RDG_NAV_EXT
 
- TXDESC40_RETRY_LIMIT_ENABLE
 
- TXDESC40_RETRY_LIMIT_MASK
 
- TXDESC40_RETRY_LIMIT_SHIFT
 
- TXDESC40_RTS_CTS_ENABLE
 
- TXDESC40_RTS_RATE_MASK
 
- TXDESC40_RTS_RATE_SHIFT
 
- TXDESC40_SEQ_MASK
 
- TXDESC40_SEQ_SHIFT
 
- TXDESC40_SHORT_PREAMBLE
 
- TXDESC40_SPE_RPT
 
- TXDESC40_USE_DRIVER_RATE
 
- TXDESCFIFO_M
 
- TXDESCFIFO_S
 
- TXDESCFIFO_V
 
- TXDESC_2ND_ADDR_CHAINED
 
- TXDESC_40_BYTES
 
- TXDESC_8723B
 
- TXDESC_AGG_EN
 
- TXDESC_AMPDU_DENSITY_SHIFT
 
- TXDESC_BMC
 
- TXDESC_BROADMULTICAST
 
- TXDESC_CCX_TAG
 
- TXDESC_CONTROL_CRC
 
- TXDESC_CONTROL_HUGE
 
- TXDESC_CONTROL_INT
 
- TXDESC_CONTROL_LAST
 
- TXDESC_CONTROL_OVERRIDE
 
- TXDESC_CONTROL_PAD
 
- TXDESC_CONTROL_SIZE
 
- TXDESC_CRC_EN_APPEND
 
- TXDESC_CRC_EN_REPLACE
 
- TXDESC_CSUM_ALL
 
- TXDESC_CSUM_IP
 
- TXDESC_CSUM_IP_PAYLD
 
- TXDESC_DATA_BW
 
- TXDESC_DISABLE_DATA_FB
 
- TXDESC_DISABLE_PAD
 
- TXDESC_END_RING
 
- TXDESC_ERROR_SUMMARY
 
- TXDESC_FIRST_SEG
 
- TXDESC_FIRST_SEGMENT
 
- TXDESC_FLAG_FIRSTPKT
 
- TXDESC_FLAG_INTPROC
 
- TXDESC_FLAG_LASTPKT
 
- TXDESC_FRAME_FLUSHED
 
- TXDESC_FSG
 
- TXDESC_GF
 
- TXDESC_HTC
 
- TXDESC_HWPC
 
- TXDESC_INTERRUPT
 
- TXDESC_IP_HEADER_ERR
 
- TXDESC_JABBER_TIMEOUT
 
- TXDESC_LAST_SEG
 
- TXDESC_LAST_SEGMENT
 
- TXDESC_LINIP
 
- TXDESC_LOCAL_FAULT
 
- TXDESC_LSG
 
- TXDESC_MAX_AGG_SHIFT
 
- TXDESC_MSK
 
- TXDESC_MSS_SHIFT
 
- TXDESC_NAVUSEHDR
 
- TXDESC_NO_ACM
 
- TXDESC_OFFSET
 
- TXDESC_OFFSET_SHT
 
- TXDESC_OFFSET_SZ
 
- TXDESC_OWN
 
- TXDESC_PAYLOAD_CSUM_ERR
 
- TXDESC_PKT_OFFSET_SHIFT
 
- TXDESC_PKT_OFFSET_SZ
 
- TXDESC_PRIME_CH_OFF_LOWER
 
- TXDESC_PRIME_CH_OFF_UPPER
 
- TXDESC_QUEUE_BE
 
- TXDESC_QUEUE_BEACON
 
- TXDESC_QUEUE_BK
 
- TXDESC_QUEUE_CMD
 
- TXDESC_QUEUE_HIGH
 
- TXDESC_QUEUE_MASK
 
- TXDESC_QUEUE_MAX
 
- TXDESC_QUEUE_MGNT
 
- TXDESC_QUEUE_SHIFT
 
- TXDESC_QUEUE_VI
 
- TXDESC_QUEUE_VO
 
- TXDESC_REMOTE_FAULT
 
- TXDESC_RTS_DATA_BW
 
- TXDESC_RTS_PRIME_CH_OFF_LOWER
 
- TXDESC_RTS_PRIME_CH_OFF_UPPER
 
- TXDESC_SA_CTRL_INSERT
 
- TXDESC_SA_CTRL_REPLACE
 
- TXDESC_SC
 
- TXDESC_SEC_AES
 
- TXDESC_SEC_RC4
 
- TXDESC_SIZE
 
- TXDESC_UNDERFLOW_ERR
 
- TXDESC_VLAN_FRAME
 
- TXDISABLE
 
- TXDIS_STATE
 
- TXDMA
 
- TXDMAPRE2FULL
 
- TXDMA_CFG
 
- TXDMA_CFG_BASE
 
- TXDMA_CFG_ENABLE
 
- TXDMA_CFG_FTHRESH
 
- TXDMA_CFG_PIOSEL
 
- TXDMA_CFG_PMODE
 
- TXDMA_CFG_RINGSZ
 
- TXDMA_CFG_RINGSZ_128
 
- TXDMA_CFG_RINGSZ_1K
 
- TXDMA_CFG_RINGSZ_256
 
- TXDMA_CFG_RINGSZ_2K
 
- TXDMA_CFG_RINGSZ_32
 
- TXDMA_CFG_RINGSZ_4K
 
- TXDMA_CFG_RINGSZ_512
 
- TXDMA_CFG_RINGSZ_64
 
- TXDMA_CFG_RINGSZ_8K
 
- TXDMA_DBHI
 
- TXDMA_DBLOW
 
- TXDMA_DHIT0
 
- TXDMA_DHIT1
 
- TXDMA_DLOW
 
- TXDMA_DPHI
 
- TXDMA_DPLOW
 
- TXDMA_EN
 
- TXDMA_FADDR
 
- TXDMA_FRPTR
 
- TXDMA_FSRPTR
 
- TXDMA_FSWPTR
 
- TXDMA_FSZ
 
- TXDMA_FTAG
 
- TXDMA_FWPTR
 
- TXDMA_INIT_VALUE
 
- TXDMA_INT_M
 
- TXDMA_KICK
 
- TXDMA_LSO_INT
 
- TXDMA_MBH
 
- TXDMA_MBH_MBADDR
 
- TXDMA_MBL
 
- TXDMA_MBL_MBADDR
 
- TXDMA_OFFSET_DROP_DATA_EN
 
- TXDMA_PCC_INT
 
- TXDMA_PCC_INT_M
 
- TXDMA_PCNT
 
- TXDMA_PFC_INT
 
- TXDMA_PFC_INT_M
 
- TXDMA_SMACHINE
 
- TXDMA_SM_INT
 
- TXDMA_TDA_INT
 
- TXDMA_TPA_INT
 
- TXDMA_TTI_INT
 
- TXDMA_TXDONE
 
- TXDNRZI
 
- TXDONE_AMPDU
 
- TXDONE_BY_ACK
 
- TXDONE_BY_IRQ
 
- TXDONE_BY_POLL
 
- TXDONE_EXCESSIVE_RETRY
 
- TXDONE_FAILURE
 
- TXDONE_FALLBACK
 
- TXDONE_NO_ACK_REQ
 
- TXDONE_QUEUE
 
- TXDONE_QUEUE_LEN
 
- TXDONE_SUCCESS
 
- TXDONE_UNKNOWN
 
- TXDP
 
- TXDP_HI
 
- TXDSI_DATA_TYPE_NOT_RECOGNISED
 
- TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE
 
- TXDSI_VC_ID_INVALID
 
- TXDUMMY
 
- TXD_ADDR
 
- TXD_BUFFER0_SIZE
 
- TXD_DESC_SIZE
 
- TXD_EOP
 
- TXD_FLAG_ADD_SRC_ADDR
 
- TXD_FLAG_CHOOSE_SRC_ADDR
 
- TXD_FLAG_COAL_NOW
 
- TXD_FLAG_CPU_POST_DMA
 
- TXD_FLAG_CPU_PRE_DMA
 
- TXD_FLAG_END
 
- TXD_FLAG_HWTSTAMP
 
- TXD_FLAG_IP_CSUM
 
- TXD_FLAG_IP_FRAG
 
- TXD_FLAG_IP_FRAG_END
 
- TXD_FLAG_JMB_PKT
 
- TXD_FLAG_NO_CRC
 
- TXD_FLAG_TCPUDP_CSUM
 
- TXD_FLAG_VLAN
 
- TXD_GATHER_CODE
 
- TXD_GATHER_CODE_FIRST
 
- TXD_GATHER_CODE_LAST
 
- TXD_INT_NUMBER
 
- TXD_INT_TYPE_PER_LIST
 
- TXD_INT_TYPE_UTILZ
 
- TXD_LENGTH
 
- TXD_LEN_FLAGS
 
- TXD_LEN_SHIFT
 
- TXD_LIST_OWN_XENA
 
- TXD_MEM_PAGE_CNT
 
- TXD_MSS_SHIFT
 
- TXD_OWN
 
- TXD_PER_EQ_UNIT
 
- TXD_SET_MARKER
 
- TXD_SIZE
 
- TXD_SOP
 
- TXD_TCP_LSO_EN
 
- TXD_TCP_LSO_MSS
 
- TXD_TX_CKO_CONTROL
 
- TXD_TX_CKO_IPV4_EN
 
- TXD_TX_CKO_TCP_EN
 
- TXD_TX_CKO_UDP_EN
 
- TXD_T_CODE
 
- TXD_T_CODE_OK
 
- TXD_UDP_COF_EN
 
- TXD_UFO_EN
 
- TXD_UFO_MSS
 
- TXD_UNDF
 
- TXD_UPDATE
 
- TXD_USE_COUNT
 
- TXD_VLAN_ENABLE
 
- TXD_VLAN_TAG
 
- TXD_VLAN_TAG_SHIFT
 
- TXD_W0_ACK
 
- TXD_W0_AGC
 
- TXD_W0_BURST
 
- TXD_W0_BURST2
 
- TXD_W0_CIPHER
 
- TXD_W0_CIPHER_ALG
 
- TXD_W0_CIPHER_OWNER
 
- TXD_W0_DATABYTE_COUNT
 
- TXD_W0_IFS
 
- TXD_W0_KEY_ID
 
- TXD_W0_KEY_INDEX
 
- TXD_W0_KEY_TABLE
 
- TXD_W0_MORE_FRAG
 
- TXD_W0_NEW_SEQ
 
- TXD_W0_OFDM
 
- TXD_W0_OWNER_NIC
 
- TXD_W0_PACKET_ID
 
- TXD_W0_R2
 
- TXD_W0_RESULT
 
- TXD_W0_RETRY_COUNT
 
- TXD_W0_RETRY_LIMIT
 
- TXD_W0_RETRY_MODE
 
- TXD_W0_RTS
 
- TXD_W0_SD_PTR0
 
- TXD_W0_TIMESTAMP
 
- TXD_W0_TKIP_MIC
 
- TXD_W0_VALID
 
- TXD_W10_BUFFER_PHYSICAL_ADDRESS
 
- TXD_W10_RTS
 
- TXD_W10_TX_RATE
 
- TXD_W11_BUFFER_LENGTH0
 
- TXD_W11_BUFFER_LENGTH1
 
- TXD_W12_BUFFER_LENGTH2
 
- TXD_W12_BUFFER_LENGTH3
 
- TXD_W13_BUFFER_LENGTH4
 
- TXD_W14_SK_BUFFER
 
- TXD_W15_NEXT_SK_BUFFER
 
- TXD_W1_AIFS
 
- TXD_W1_AIFSN
 
- TXD_W1_BUFFER_ADDRESS
 
- TXD_W1_BUFFER_COUNT
 
- TXD_W1_BURST
 
- TXD_W1_CWMAX
 
- TXD_W1_CWMIN
 
- TXD_W1_DMA_DONE
 
- TXD_W1_HOST_Q_ID
 
- TXD_W1_HW_SEQUENCE
 
- TXD_W1_IV_OFFSET
 
- TXD_W1_LAST_SEC0
 
- TXD_W1_LAST_SEC1
 
- TXD_W1_PIGGY_BACK
 
- TXD_W1_SD_LEN0
 
- TXD_W1_SD_LEN1
 
- TXD_W1_VAL
 
- TXD_W2_AIFS
 
- TXD_W2_BUFFER_LENGTH
 
- TXD_W2_CWMAX
 
- TXD_W2_CWMIN
 
- TXD_W2_DATABYTE_COUNT
 
- TXD_W2_IV_OFFSET
 
- TXD_W2_PLCP_LENGTH_HIGH
 
- TXD_W2_PLCP_LENGTH_LOW
 
- TXD_W2_PLCP_SERVICE
 
- TXD_W2_PLCP_SIGNAL
 
- TXD_W2_SD_PTR1
 
- TXD_W3_ICO
 
- TXD_W3_IV
 
- TXD_W3_PLCP_LENGTH_HIGH
 
- TXD_W3_PLCP_LENGTH_HIGH_BUSY
 
- TXD_W3_PLCP_LENGTH_HIGH_REGNUM
 
- TXD_W3_PLCP_LENGTH_LOW
 
- TXD_W3_PLCP_LENGTH_LOW_BUSY
 
- TXD_W3_PLCP_LENGTH_LOW_REGNUM
 
- TXD_W3_PLCP_SERVICE
 
- TXD_W3_PLCP_SERVICE_BUSY
 
- TXD_W3_PLCP_SERVICE_REGNUM
 
- TXD_W3_PLCP_SIGNAL
 
- TXD_W3_PLCP_SIGNAL_BUSY
 
- TXD_W3_PLCP_SIGNAL_REGNUM
 
- TXD_W3_QSEL
 
- TXD_W3_TCO
 
- TXD_W3_UCO
 
- TXD_W3_WIV
 
- TXD_W4_EIV
 
- TXD_W4_IV
 
- TXD_W4_PLCP_LENGTH_HIGH
 
- TXD_W4_PLCP_LENGTH_LOW
 
- TXD_W5_AGC_REG
 
- TXD_W5_AGC_REG_VALID
 
- TXD_W5_BBCR4
 
- TXD_W5_EIV
 
- TXD_W5_FRAME_OFFSET
 
- TXD_W5_PACKET_ID
 
- TXD_W5_PID_SUBTYPE
 
- TXD_W5_PID_TYPE
 
- TXD_W5_TX_POWER
 
- TXD_W5_WAITING_DMA_DONE_INT
 
- TXD_W5_XXX_REG
 
- TXD_W5_XXX_REG_VALID
 
- TXD_W6_BUFFER_PHYSICAL_ADDRESS
 
- TXD_W6_KEY
 
- TXD_W6_SK_BUFF
 
- TXD_W7_BUFFER_PHYSICAL_ADDRESS
 
- TXD_W7_KEY
 
- TXD_W7_RESERVED
 
- TXD_W8_BUFFER_PHYSICAL_ADDRESS
 
- TXD_W8_KEY
 
- TXD_W9_BUFFER_PHYSICAL_ADDRESS
 
- TXD_W9_KEY
 
- TXE
 
- TXE32_PORT_CNTR_ELEM
 
- TXE64_PORT_CNTR_ELEM
 
- TXECC_MULTIBIT_ERROR
 
- TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE
 
- TXECC_SINGLE_BIT_ERROR
 
- TXEFA_EFAI_MASK
 
- TXEFA_EFAI_SHIFT
 
- TXEFC_EFS_MASK
 
- TXEFC_EFS_SHIFT
 
- TXEFS_EFF
 
- TXEFS_EFFL_MASK
 
- TXEFS_EFFL_SHIFT
 
- TXEFS_EFGI_MASK
 
- TXEFS_EFGI_SHIFT
 
- TXEFS_TEFL
 
- TXEMEMPARITYERR_PIOBUF
 
- TXEMEMPARITYERR_PIOLAUNCHFIFO
 
- TXEMEMPARITYERR_PIOPBC
 
- TXEMPTY
 
- TXEN
 
- TXENABLE
 
- TXEND
 
- TXENDPTR_CLP
 
- TXENDPTR_MASK_PDUMODE
 
- TXEND_INIT
 
- TXEN_SHIFT
 
- TXENcfg
 
- TXEOM
 
- TXERR
 
- TXESC_TBDS_64BYTES
 
- TXESC_TBDS_8BYTES
 
- TXESR_TDRBS
 
- TXESR_TDSTR
 
- TXESR_TDWBS
 
- TXESR_TFDBS
 
- TXE_ELEMENT_SIZE
 
- TXE_ERR_INT
 
- TXE_HBUF_DEPTH
 
- TXE_INTR_ALIVENESS
 
- TXE_INTR_ALIVENESS_BIT
 
- TXE_INTR_IN_READY
 
- TXE_INTR_IN_READY_BIT
 
- TXE_INTR_OUT_DB
 
- TXE_INTR_OUT_DB_BIT
 
- TXE_INTR_READINESS
 
- TXE_INTR_READINESS_BIT
 
- TXE_NUM_32_BIT_COUNTER
 
- TXE_NUM_64_BIT_COUNTER
 
- TXE_NUM_CONTEXTS
 
- TXE_NUM_DATA_VL
 
- TXE_NUM_SDMA_ENGINES
 
- TXE_PIO_PARITY
 
- TXE_PIO_SEND
 
- TXE_PIO_SEND_OFFSET
 
- TXE_PIO_SIZE
 
- TXFAE
 
- TXFALSE_CONTROL_ERROR
 
- TXFC
 
- TXFCB_CIP
 
- TXFCB_CTU
 
- TXFCB_DEFAULT
 
- TXFCB_IP
 
- TXFCB_IP6
 
- TXFCB_NPH
 
- TXFCB_TUP
 
- TXFCB_UDP
 
- TXFCB_VLN
 
- TXFCR_FIFO_EN_MASK
 
- TXFCR_FIFO_FLUSH_MASK
 
- TXFCR_OFFSET
 
- TXFD
 
- TXFDPR_TXFPAI
 
- TXFDPR_TXFP_MASK
 
- TXFDPR_TXFP_SHIFT
 
- TXFE
 
- TXFFR
 
- TXFF_EMPTY_TH
 
- TXFF_PG_NUM
 
- TXFF_STATUS
 
- TXFID_QUEUE_MASK
 
- TXFID_RATE_MASK
 
- TXFID_RATE_PROBE_MASK
 
- TXFID_RATE_SHIFT
 
- TXFID_SEQ_MASK
 
- TXFID_SEQ_SHIFT
 
- TXFIFO
 
- TXFIFOCMD_FIFOSEL_SHIFT
 
- TXFIFOCMD_RESET_MASK
 
- TXFIFOCSR
 
- TXFIFOE
 
- TXFIFOMT
 
- TXFIFO_DEFAULT
 
- TXFIFO_EMPTY
 
- TXFIFO_ERR_DET
 
- TXFIFO_FIFOTOP_SHIFT
 
- TXFIFO_FL
 
- TXFIFO_MT
 
- TXFIFO_PRTY_ERR_F
 
- TXFIFO_PRTY_ERR_S
 
- TXFIFO_PRTY_ERR_V
 
- TXFIFO_REG
 
- TXFIFO_SIZE
 
- TXFIFO_SIZE_UNIT
 
- TXFIFO_START_BLK
 
- TXFIFO_START_BLK16
 
- TXFIFO_TEMPTY
 
- TXFIFO_THR_NORMAL
 
- TXFIFO_THR_NORMAL2
 
- TXFIFO_WR
 
- TXFIFO_WR_REQ
 
- TXFILT_DEFAULT_OFDM20
 
- TXFILT_DEFAULT_OFDM40
 
- TXFILT_SHAPING_CCK
 
- TXFILT_SHAPING_OFDM20
 
- TXFILT_SHAPING_OFDM40
 
- TXFLAGS
 
- TXFLAG_64BIT
 
- TXFLAG_CSBUFBEGIN
 
- TXFLAG_CSENABLE
 
- TXFLAG_CSLOCATION
 
- TXFLAG_EOP
 
- TXFLAG_INT
 
- TXFLAG_IPCS
 
- TXFLAG_LSEN
 
- TXFLAG_OWN
 
- TXFLAG_SIZE
 
- TXFLAG_SOP
 
- TXFLAG_TAGON
 
- TXFLAG_TCPCS
 
- TXFLAG_UDPCS
 
- TXFLOW_CNTL
 
- TXFLOW_CTS
 
- TXFLOW_DSR
 
- TXFLOW_XOFF
 
- TXFLOW_XOFF_ANY
 
- TXFLOW_XOFF_BITS
 
- TXFQS_TFFL_MASK
 
- TXFQS_TFFL_SHIFT
 
- TXFQS_TFGI_MASK
 
- TXFQS_TFGI_SHIFT
 
- TXFQS_TFQF
 
- TXFQS_TFQPI_MASK
 
- TXFQS_TFQPI_SHIFT
 
- TXFREEflag
 
- TXFR_TXFID_MASK
 
- TXFR_TXFID_SHIFT
 
- TXFR_TXIC
 
- TXFSRST
 
- TXF_CPU2_FENCE_PTR
 
- TXF_CPU2_FIFO_ITEM_CNT
 
- TXF_CPU2_LOCK_FENCE
 
- TXF_CPU2_NUM
 
- TXF_CPU2_RD_PTR
 
- TXF_CPU2_READ_MODIFY_ADDR
 
- TXF_CPU2_READ_MODIFY_DATA
 
- TXF_CPU2_WR_PTR
 
- TXF_FENCE_PTR
 
- TXF_FIFO_ITEM_CNT
 
- TXF_HIGH_WATER_MARK_SHIFT
 
- TXF_HWM_BMSK
 
- TXF_LARC_NUM
 
- TXF_LOCK_FENCE
 
- TXF_LOW_WATER_MARK_SHIFT
 
- TXF_LWM_BMSK
 
- TXF_RD_PTR
 
- TXF_READ_MODIFY_ADDR
 
- TXF_READ_MODIFY_DATA
 
- TXF_RPTR_RD_PTR
 
- TXF_UR_INT
 
- TXF_WATER_MARK_MASK
 
- TXF_WPTR_MASK
 
- TXF_WPTR_WR_PTR
 
- TXF_WR_PTR
 
- TXGROUP
 
- TXGXS_ECC_DB_ERR
 
- TXGXS_ECC_SG_ERR
 
- TXGXS_ESTORE_UFLOW
 
- TXGXS_TX_SM_ERR
 
- TXHCLKRST
 
- TXHDR_CHAINCONTINUE
 
- TXHDR_CSUM_NONE
 
- TXHDR_CSUM_SCTP
 
- TXHDR_CSUM_TCP
 
- TXHDR_CSUM_UDP
 
- TXHDR_DATAFOLLOWS
 
- TXHDR_EN16COLLISION
 
- TXHDR_ENBABBLEINT
 
- TXHDR_ENCOLLISIONINT
 
- TXHDR_ENSUCCESS
 
- TXHDR_FLAGS
 
- TXHDR_IHL
 
- TXHDR_IHL_SHIFT
 
- TXHDR_IP_VER
 
- TXHDR_L3START
 
- TXHDR_L3START_SHIFT
 
- TXHDR_L4START
 
- TXHDR_L4START_SHIFT
 
- TXHDR_L4STUFF
 
- TXHDR_L4STUFF_SHIFT
 
- TXHDR_LEN
 
- TXHDR_LEN_SHIFT
 
- TXHDR_LLC
 
- TXHDR_PAD
 
- TXHDR_PAD_SHIFT
 
- TXHDR_TRANSMIT
 
- TXHDR_VLAN
 
- TXHI
 
- TXHIGHPWRLEVEL_BT1
 
- TXHIGHPWRLEVEL_BT2
 
- TXHIGHPWRLEVEL_LEVEL1
 
- TXHIGHPWRLEVEL_LEVEL2
 
- TXHIGHPWRLEVEL_NORMAL
 
- TXHI_ENTRIES
 
- TXI
 
- TXI1
 
- TXIC
 
- TXID_ASSIGN
 
- TXID_AUTO
 
- TXID_AUTO_CT3_MSK
 
- TXID_AUTO_CT3_OFF
 
- TXID_AUTO_CTB_MSK
 
- TXID_AUTO_CTB_OFF
 
- TXID_ENTRY
 
- TXID_PR_ARG
 
- TXID_PR_FMT
 
- TXIE
 
- TXIENB
 
- TXIE_RES
 
- TXIE_SET
 
- TXIE_UNC
 
- TXIF
 
- TXINFO_DESC_SIZE
 
- TXINFO_SIZE
 
- TXINFO_W0_QSEL
 
- TXINFO_W0_SW_USE_LAST_ROUND
 
- TXINFO_W0_USB_DMA_NEXT_VALID
 
- TXINFO_W0_USB_DMA_TX_BURST
 
- TXINFO_W0_USB_DMA_TX_PKT_LEN
 
- TXINFO_W0_WIV
 
- TXINT
 
- TXINTE
 
- TXINT_CNT_MASK
 
- TXINT_EN
 
- TXINT_MASK
 
- TXINT_THR_MASK
 
- TXINT_TIME_SEL
 
- TXIQCAL_DONE
 
- TXLBA
 
- TXLD
 
- TXLOGGING
 
- TXLOG_ACTION_IRQ
 
- TXLOG_ACTION_NBUFS
 
- TXLOG_ACTION_TBUSY
 
- TXLOG_ACTION_TXMIT
 
- TXLOW
 
- TXLO_ENTRIES
 
- TXMAC
 
- TXMAC_BYTE_CNT
 
- TXMAC_BYTE_CNT_COUNT
 
- TXMAC_FRM_CNT
 
- TXMAC_FRM_CNT_COUNT
 
- TXMAC_INT_M
 
- TXMASK
 
- TXMAX
 
- TXMCR_CSMA_RETRIES_MASK
 
- TXMCR_CSMA_RETRIES_SHIFT
 
- TXMCR_MIN_BE_MASK
 
- TXMCR_MIN_BE_SHIFT
 
- TXMCS_BACKOFF
 
- TXMCS_CARRIEREXT
 
- TXMCS_CARRIERSENSE
 
- TXMCS_COLLISION
 
- TXMCS_CRC
 
- TXMCS_DEFAULT
 
- TXMCS_DEFER
 
- TXMCS_FBURST
 
- TXMCS_IFG1
 
- TXMCS_IFG1_12_6
 
- TXMCS_IFG1_16_8
 
- TXMCS_IFG1_20_10
 
- TXMCS_IFG1_8_4
 
- TXMCS_IFG2
 
- TXMCS_IFG2_10_6
 
- TXMCS_IFG2_12_7
 
- TXMCS_IFG2_6_4
 
- TXMCS_IFG2_8_5
 
- TXMCS_PADDING
 
- TXMCS_TTHOLD
 
- TXMCS_TTHOLD_1_2
 
- TXMCS_TTHOLD_1_4
 
- TXMCS_TTHOLD_1_8
 
- TXMCS_TTHOLD_FULL
 
- TXMIN
 
- TXMODE_BYHAND
 
- TXMODE_DMA
 
- TXNLCR0
 
- TXNLCR1
 
- TXN_DMIC_CTL_CLK_SEL_DIV16
 
- TXN_DMIC_CTL_CLK_SEL_DIV2
 
- TXN_DMIC_CTL_CLK_SEL_DIV3
 
- TXN_DMIC_CTL_CLK_SEL_DIV4
 
- TXN_DMIC_CTL_CLK_SEL_DIV6
 
- TXN_DMIC_CTL_CLK_SEL_MASK
 
- TXN_LOCK
 
- TXN_SLEEP
 
- TXN_SLEEP_DROP_LOCK
 
- TXN_UNLOCK
 
- TXN_WAKEUP
 
- TXOFF
 
- TXOFFSET
 
- TXON
 
- TXOPTIONCNTRL
 
- TXOP_BACKOFF
 
- TXOP_BE
 
- TXOP_BK
 
- TXOP_CTRL_CFG
 
- TXOP_CTRL_CFG_AC_TRUN_EN
 
- TXOP_CTRL_CFG_EXT_CCA_DLY
 
- TXOP_CTRL_CFG_EXT_CCA_EN
 
- TXOP_CTRL_CFG_EXT_CWMIN
 
- TXOP_CTRL_CFG_LSIG_TXOP_EN
 
- TXOP_CTRL_CFG_MIMO_PS_TRUN_EN
 
- TXOP_CTRL_CFG_RESERVED_TRUN_EN
 
- TXOP_CTRL_CFG_TIMEOUT_TRUN_EN
 
- TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN
 
- TXOP_CTRL_CFG_USER_MODE_TRUN_EN
 
- TXOP_HLDR_ADDR0
 
- TXOP_HLDR_ADDR1
 
- TXOP_HLDR_ET
 
- TXOP_HTTXOP
 
- TXOP_PIFS
 
- TXOP_SIFS
 
- TXOP_STALL_CTRL
 
- TXOP_THRES_CFG
 
- TXOP_UNIT
 
- TXOP_VI
 
- TXOP_VO
 
- TXORD
 
- TXOUTCFF_EMPTY_INT
 
- TXOUTCFF_FULL_INT
 
- TXOVERIDE
 
- TXOWN
 
- TXP
 
- TXP1
 
- TXP1EN
 
- TXP2
 
- TXP2EN
 
- TXPAD
 
- TXPATH_FLUSH
 
- TXPAUSE
 
- TXPBIT
 
- TXPDR
 
- TXPF
 
- TXPFC_PF_EN
 
- TXPFC_VLAN_EN
 
- TXPFC_VLAN_TAG
 
- TXPF_ADDR
 
- TXPIC_INT_M
 
- TXPKTBUF_PGBNDY
 
- TXPKTCOUNT_LEN
 
- TXPKTCOUNT_POS
 
- TXPKT_BUF_SELECT
 
- TXPKT_CSUM_END_S
 
- TXPKT_CSUM_END_V
 
- TXPKT_CSUM_LOC_S
 
- TXPKT_CSUM_LOC_V
 
- TXPKT_CSUM_START_S
 
- TXPKT_CSUM_START_V
 
- TXPKT_CSUM_TYPE_S
 
- TXPKT_CSUM_TYPE_V
 
- TXPKT_ETHHDR_LEN_S
 
- TXPKT_ETHHDR_LEN_V
 
- TXPKT_INS_OVLAN_F
 
- TXPKT_INS_OVLAN_S
 
- TXPKT_INS_OVLAN_V
 
- TXPKT_INTF_S
 
- TXPKT_INTF_V
 
- TXPKT_IPCSUM_DIS_F
 
- TXPKT_IPCSUM_DIS_S
 
- TXPKT_IPCSUM_DIS_V
 
- TXPKT_IPHDR_LEN_S
 
- TXPKT_IPHDR_LEN_V
 
- TXPKT_L4CSUM_DIS_F
 
- TXPKT_L4CSUM_DIS_S
 
- TXPKT_L4CSUM_DIS_V
 
- TXPKT_NUM_CTRL
 
- TXPKT_OPCODE_S
 
- TXPKT_OPCODE_V
 
- TXPKT_OVLAN_IDX_S
 
- TXPKT_OVLAN_IDX_V
 
- TXPKT_PF_S
 
- TXPKT_PF_V
 
- TXPKT_T5_OVLAN_IDX_S
 
- TXPKT_T5_OVLAN_IDX_V
 
- TXPKT_TSTAMP_F
 
- TXPKT_TSTAMP_S
 
- TXPKT_TSTAMP_V
 
- TXPKT_VF_S
 
- TXPKT_VF_V
 
- TXPKT_VF_VLD_F
 
- TXPKT_VF_VLD_S
 
- TXPKT_VF_VLD_V
 
- TXPKT_VLAN_S
 
- TXPKT_VLAN_V
 
- TXPKT_VLAN_VLD_F
 
- TXPKT_VLAN_VLD_S
 
- TXPKT_VLAN_VLD_V
 
- TXPLA_RST
 
- TXPL_MASK
 
- TXPMD_CONTROL1
 
- TXPMD_CONTROL1_TX_SSC_EN_FRC
 
- TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL
 
- TXPMD_REG_BANK
 
- TXPMD_TX_FREQ_CTRL_CONTROL1
 
- TXPMD_TX_FREQ_CTRL_CONTROL2
 
- TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK
 
- TXPMD_TX_FREQ_CTRL_CONTROL3
 
- TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK
 
- TXPNTR
 
- TXPOLL_CNT_MASK
 
- TXPOLL_CNT_SHIFT_BIT
 
- TXPOLL_TIME_SEL
 
- TXPOWER_A_FROM_DEV
 
- TXPOWER_DEFAULT
 
- TXPOWER_FROM_DEV
 
- TXPOWER_G_FROM_DEV
 
- TXPOWER_TO_DEV
 
- TXPRINTK
 
- TXPTR
 
- TXPWRL_0
 
- TXPWRL_10
 
- TXPWRL_20
 
- TXPWRL_30
 
- TXPWRL_MASK
 
- TXPWRL_SHIFT
 
- TXPWRS_0
 
- TXPWRS_0_5
 
- TXPWRS_1_2
 
- TXPWRS_1_9
 
- TXPWRS_2_8
 
- TXPWRS_3_7
 
- TXPWRS_4_9
 
- TXPWRS_6_3
 
- TXPWRS_MASK
 
- TXPWRS_SHIFT
 
- TXPWRTRACK_CFG
 
- TXPWRTRACK_MAX_IDX
 
- TXPWR_LMT_ETSI
 
- TXPWR_LMT_FCC
 
- TXPWR_LMT_MAX_REGULATION_NUM
 
- TXPWR_LMT_MKK
 
- TXPWR_LMT_WW
 
- TXPWR_TRACK_TABLE_SIZE
 
- TXP_ABORT
 
- TXP_ALPHA_ENABLE
 
- TXP_ALPHA_INVERT
 
- TXP_BUSY
 
- TXP_BYTE_ENABLE_MASK
 
- TXP_BYTE_ENABLE_SHIFT
 
- TXP_CHECK_AND_PRINT
 
- TXP_DIM
 
- TXP_DITHER
 
- TXP_DST_CTRL
 
- TXP_DST_PITCH
 
- TXP_DST_PTR
 
- TXP_EI
 
- TXP_FIELD
 
- TXP_FIRST_CCK
 
- TXP_FIRST_MCS_20_CDD
 
- TXP_FIRST_MCS_20_SDM
 
- TXP_FIRST_MCS_20_SISO
 
- TXP_FIRST_MCS_20_STBC
 
- TXP_FIRST_MCS_40_CDD
 
- TXP_FIRST_MCS_40_SDM
 
- TXP_FIRST_MCS_40_SISO
 
- TXP_FIRST_MCS_40_STBC
 
- TXP_FIRST_OFDM
 
- TXP_FIRST_OFDM_20_CDD
 
- TXP_FIRST_OFDM_40_CDD
 
- TXP_FIRST_OFDM_40_SISO
 
- TXP_FIRST_SISO_MCS_20
 
- TXP_FORMAT_ABGR4444
 
- TXP_FORMAT_ABGR8888
 
- TXP_FORMAT_ARGB4444
 
- TXP_FORMAT_ARGB8888
 
- TXP_FORMAT_BGR565
 
- TXP_FORMAT_BGR888
 
- TXP_FORMAT_BGRA4444
 
- TXP_FORMAT_BGRA8888
 
- TXP_FORMAT_MASK
 
- TXP_FORMAT_RGB565
 
- TXP_FORMAT_RGB888
 
- TXP_FORMAT_RGBA4444
 
- TXP_FORMAT_RGBA8888
 
- TXP_FORMAT_SHIFT
 
- TXP_GO
 
- TXP_HEIGHT_MASK
 
- TXP_HEIGHT_SHIFT
 
- TXP_LAST_CCK
 
- TXP_LAST_MCS_20_CDD
 
- TXP_LAST_MCS_20_SDM
 
- TXP_LAST_MCS_20_SISO
 
- TXP_LAST_MCS_20_STBC
 
- TXP_LAST_MCS_40_CDD
 
- TXP_LAST_MCS_40_SDM
 
- TXP_LAST_MCS_40_SISO
 
- TXP_LAST_MCS_40_STBC
 
- TXP_LAST_OFDM
 
- TXP_LAST_OFDM_20_CDD
 
- TXP_LAST_OFDM_40_CDD
 
- TXP_LAST_OFDM_40_SISO
 
- TXP_LAST_SISO_MCS_20
 
- TXP_LINEAR_UTILE
 
- TXP_LT_TILE_WIDTH_SHIFT
 
- TXP_MCS_32
 
- TXP_NUM_RATES
 
- TXP_PILOT_MASK
 
- TXP_PILOT_SHIFT
 
- TXP_POWERDOWN
 
- TXP_PROGRESS
 
- TXP_READ
 
- TXP_SIZE
 
- TXP_TEST_MODE
 
- TXP_TFORMAT
 
- TXP_TRANSPOSE
 
- TXP_T_TILE_WIDTH_SHIFT
 
- TXP_VERSION_MASK
 
- TXP_VERSION_SHIFT
 
- TXP_VSTART_AT_EOF
 
- TXP_WIDTH_MASK
 
- TXP_WIDTH_SHIFT
 
- TXP_WRITE
 
- TXQ0_NUM_TPD_PREF_DEF
 
- TXQCR_AETFE
 
- TXQCR_METFE
 
- TXQCR_TXQMAM
 
- TXQLEN
 
- TXQUEUESTOP_THRESHHOLD
 
- TXQ_BW_CONF
 
- TXQ_BW_TOKENS
 
- TXQ_BW_WRR_CONF
 
- TXQ_CFGV
 
- TXQ_CMD_SHIFT
 
- TXQ_CMD_SLOT_RESET
 
- TXQ_CMD_SMP
 
- TXQ_CMD_SSP
 
- TXQ_CMD_SSP_FREE_LIST
 
- TXQ_CMD_STP
 
- TXQ_COMMAND
 
- TXQ_CSERR_INT
 
- TXQ_CTRL
 
- TXQ_CTRL_BURST_MODE_EN
 
- TXQ_CTRL_EN
 
- TXQ_CTRL_ENH_MODE
 
- TXQ_CTRL_IP_OPTION_EN
 
- TXQ_CTRL_LS_8023_EN
 
- TXQ_CTRL_NUM_TPD_BURST_MASK
 
- TXQ_CTRL_NUM_TPD_BURST_SHIFT
 
- TXQ_CTRL_PEDING_CLR
 
- TXQ_CTRL_TPD_BURST_NUM_MASK
 
- TXQ_CTRL_TPD_BURST_NUM_SHIFT
 
- TXQ_CTRL_TPD_FETCH_TH_MASK
 
- TXQ_CTRL_TPD_FETCH_TH_SHIFT
 
- TXQ_CTRL_TXF_BURST_NUM_MASK
 
- TXQ_CTRL_TXF_BURST_NUM_SHIFT
 
- TXQ_CURRENT_DESC_PTR
 
- TXQ_EMPTY_INT
 
- TXQ_EN
 
- TXQ_ETH
 
- TXQ_FIX_PRIO_CONF
 
- TXQ_FIX_PRIO_CONF_MOVED
 
- TXQ_FLAG_BACKOFF_DISABLE
 
- TXQ_FLAG_COMPRESSION_ENABLE
 
- TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE
 
- TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE
 
- TXQ_FLAG_TXDESCINT_ENABLE
 
- TXQ_FLAG_TXEOLINT_ENABLE
 
- TXQ_FLAG_TXINT_ENABLE
 
- TXQ_FLAG_TXURNINT_ENABLE
 
- TXQ_HP
 
- TXQ_LAST_PKT_DB
 
- TXQ_LENERR_INT
 
- TXQ_LP
 
- TXQ_MODE
 
- TXQ_MODE_I
 
- TXQ_MODE_INITIATOR
 
- TXQ_MODE_TARGET
 
- TXQ_NENTRIES
 
- TXQ_NUM
 
- TXQ_NUM_TPD_BURST_DEF
 
- TXQ_NUM_TPD_BURST_MASK
 
- TXQ_NUM_TPD_BURST_SHIFT
 
- TXQ_OFLD
 
- TXQ_PAUSE_THD_MASK
 
- TXQ_PGADD
 
- TXQ_PHY_MASK
 
- TXQ_PHY_SHIFT
 
- TXQ_PRIO_HI
 
- TXQ_PRI_HIGH
 
- TXQ_PRI_NORMAL
 
- TXQ_RUNNING
 
- TXQ_SLOT_MASK
 
- TXQ_SRS_MASK
 
- TXQ_SRS_SHIFT
 
- TXQ_STATS_LEN
 
- TXQ_STOP_THRES
 
- TXQ_TO_INT
 
- TXQ_TXF_BURST_NUM_MASK
 
- TXQ_TXF_BURST_NUM_SHIFT
 
- TXR
 
- TXRDYE
 
- TXRDY_PAYLOAD_LEN
 
- TXREADPTR_GET_PTR
 
- TXREADPTR_MASK_DELTA
 
- TXREQTO_EN
 
- TXREQTO_VAL
 
- TXREQ_FLAGS_REQ_ACK
 
- TXREQ_FLAGS_REQ_DISABLE_SH
 
- TXREQ_LEN
 
- TXREQ_NAME_LEN
 
- TXRESET
 
- TXRETRIES
 
- TXRN_MASK
 
- TXROT
 
- TXRPTFF_RDPTR
 
- TXRPTFF_WTPTR
 
- TXRQST_RES
 
- TXRQST_SET
 
- TXRQST_UNC
 
- TXRST
 
- TXRTS
 
- TXRXBUFSIZE
 
- TXRXQ_PCNT
 
- TXRXQ_PCNT_RX0Q
 
- TXRXQ_PCNT_TX0Q
 
- TXRXQ_PCNT_TX1Q
 
- TXRXQ_PCNT_TX2Q
 
- TXRX_BUF_LEN_DEFAULT
 
- TXRX_CSR0
 
- TXRX_CSR0_ALGORITHM
 
- TXRX_CSR0_AUTO_TX_SEQ
 
- TXRX_CSR0_DISABLE_RX
 
- TXRX_CSR0_DROP_ACK_CTS
 
- TXRX_CSR0_DROP_BROADCAST
 
- TXRX_CSR0_DROP_CONTROL
 
- TXRX_CSR0_DROP_CRC
 
- TXRX_CSR0_DROP_MULTICAST
 
- TXRX_CSR0_DROP_NOT_TO_ME
 
- TXRX_CSR0_DROP_PHYSICAL
 
- TXRX_CSR0_DROP_TO_DS
 
- TXRX_CSR0_DROP_VERSION_ERROR
 
- TXRX_CSR0_IV_OFFSET
 
- TXRX_CSR0_KEY_ID
 
- TXRX_CSR0_RX_ACK_TIMEOUT
 
- TXRX_CSR0_TSF_OFFSET
 
- TXRX_CSR0_TX_WITHOUT_WAITING
 
- TXRX_CSR1
 
- TXRX_CSR10
 
- TXRX_CSR10_AUTORESPOND_PREAMBLE
 
- TXRX_CSR11
 
- TXRX_CSR12
 
- TXRX_CSR12_LOW_TSFTIMER
 
- TXRX_CSR13
 
- TXRX_CSR13_HIGH_TSFTIMER
 
- TXRX_CSR14
 
- TXRX_CSR15
 
- TXRX_CSR16
 
- TXRX_CSR17
 
- TXRX_CSR18
 
- TXRX_CSR18_INTERVAL
 
- TXRX_CSR18_OFFSET
 
- TXRX_CSR19
 
- TXRX_CSR19_BEACON_GEN
 
- TXRX_CSR19_TBCN
 
- TXRX_CSR19_TSF_COUNT
 
- TXRX_CSR19_TSF_SYNC
 
- TXRX_CSR1_ACK_TIMEOUT
 
- TXRX_CSR1_AUTO_SEQUENCE
 
- TXRX_CSR1_BBP_ID0
 
- TXRX_CSR1_BBP_ID0_VALID
 
- TXRX_CSR1_BBP_ID1
 
- TXRX_CSR1_BBP_ID1_VALID
 
- TXRX_CSR1_BBP_ID2
 
- TXRX_CSR1_BBP_ID2_VALID
 
- TXRX_CSR1_BBP_ID3
 
- TXRX_CSR1_BBP_ID3_VALID
 
- TXRX_CSR1_TSF_OFFSET
 
- TXRX_CSR2
 
- TXRX_CSR20
 
- TXRX_CSR20_BCN_EXPECT_WINDOW
 
- TXRX_CSR20_OFFSET
 
- TXRX_CSR21
 
- TXRX_CSR2_BBP_ID0
 
- TXRX_CSR2_BBP_ID0_VALID
 
- TXRX_CSR2_BBP_ID1
 
- TXRX_CSR2_BBP_ID1_VALID
 
- TXRX_CSR2_BBP_ID2
 
- TXRX_CSR2_BBP_ID2_VALID
 
- TXRX_CSR2_BBP_ID3
 
- TXRX_CSR2_BBP_ID3_VALID
 
- TXRX_CSR2_DISABLE_RX
 
- TXRX_CSR2_DROP_BROADCAST
 
- TXRX_CSR2_DROP_CONTROL
 
- TXRX_CSR2_DROP_CRC
 
- TXRX_CSR2_DROP_MULTICAST
 
- TXRX_CSR2_DROP_NOT_TO_ME
 
- TXRX_CSR2_DROP_PHYSICAL
 
- TXRX_CSR2_DROP_TODS
 
- TXRX_CSR2_DROP_VERSION_ERROR
 
- TXRX_CSR3
 
- TXRX_CSR3_BBP_ID0
 
- TXRX_CSR3_BBP_ID0_VALID
 
- TXRX_CSR3_BBP_ID1
 
- TXRX_CSR3_BBP_ID1_VALID
 
- TXRX_CSR3_BBP_ID2
 
- TXRX_CSR3_BBP_ID2_VALID
 
- TXRX_CSR3_BBP_ID3
 
- TXRX_CSR3_BBP_ID3_VALID
 
- TXRX_CSR4
 
- TXRX_CSR4_ACK_CTS_PSM
 
- TXRX_CSR4_AUTORESPOND_ENABLE
 
- TXRX_CSR4_AUTORESPOND_PREAMBLE
 
- TXRX_CSR4_CNTL_ACK_POLICY
 
- TXRX_CSR4_LONG_RETRY_LIMIT
 
- TXRX_CSR4_OFDM_TX_FALLBACK_CCK
 
- TXRX_CSR4_OFDM_TX_RATE_DOWN
 
- TXRX_CSR4_OFDM_TX_RATE_STEP
 
- TXRX_CSR4_SHORT_RETRY_LIMIT
 
- TXRX_CSR4_TX_ACK_TIMEOUT
 
- TXRX_CSR5
 
- TXRX_CSR5_BBP_ID0
 
- TXRX_CSR5_BBP_ID0_VALID
 
- TXRX_CSR5_BBP_ID1
 
- TXRX_CSR5_BBP_ID1_VALID
 
- TXRX_CSR6
 
- TXRX_CSR6_BBP_ID0
 
- TXRX_CSR6_BBP_ID0_VALID
 
- TXRX_CSR6_BBP_ID1
 
- TXRX_CSR6_BBP_ID1_VALID
 
- TXRX_CSR7
 
- TXRX_CSR7_ACK_CTS_12MBS
 
- TXRX_CSR7_ACK_CTS_18MBS
 
- TXRX_CSR7_ACK_CTS_6MBS
 
- TXRX_CSR7_ACK_CTS_9MBS
 
- TXRX_CSR7_BBP_ID0
 
- TXRX_CSR7_BBP_ID0_VALID
 
- TXRX_CSR7_BBP_ID1
 
- TXRX_CSR7_BBP_ID1_VALID
 
- TXRX_CSR8
 
- TXRX_CSR8_ACK_CTS_24MBS
 
- TXRX_CSR8_ACK_CTS_36MBS
 
- TXRX_CSR8_ACK_CTS_48MBS
 
- TXRX_CSR8_ACK_CTS_54MBS
 
- TXRX_CSR8_BBP_ID0
 
- TXRX_CSR8_BBP_ID0_VALID
 
- TXRX_CSR8_BBP_ID1
 
- TXRX_CSR8_BBP_ID1_VALID
 
- TXRX_CSR9
 
- TXRX_CSR9_BEACON_GEN
 
- TXRX_CSR9_BEACON_INTERVAL
 
- TXRX_CSR9_TBTT_ENABLE
 
- TXRX_CSR9_TIMESTAMP_COMPENSATE
 
- TXRX_CSR9_TSF_SYNC
 
- TXRX_CSR9_TSF_TICKING
 
- TXRX_DEASSERT_CS
 
- TXRX_LENGTH_MASK
 
- TXRX_RING_MAP
 
- TXRX_WRITE
 
- TXS
 
- TXSBND
 
- TXSCALE_TABLE_SIZE
 
- TXSCHQ_FREE_ALL
 
- TXSCHQ_HWREGMAP
 
- TXSCHQ_IDX
 
- TXSCHQ_IDX_MASK
 
- TXSCHQ_IDX_SHIFT
 
- TXSCH_MAP
 
- TXSCH_MAP_FLAGS
 
- TXSCH_MAP_FUNC
 
- TXSCH_TL1_DFLT_RR_PRIO
 
- TXSCH_TL1_DFLT_RR_QTM
 
- TXSEL
 
- TXSERCLR
 
- TXSFD
 
- TXSHRMT
 
- TXSM
 
- TXSMRST
 
- TXSOM
 
- TXSQ_MAGIC
 
- TXSR_TXFID_GET
 
- TXSR_TXFID_MASK
 
- TXSR_TXFID_SHIFT
 
- TXSR_TXLC
 
- TXSR_TXMC
 
- TXSSZ
 
- TXSTART_INIT
 
- TXSTATE
 
- TXSTATS
 
- TXSTATUS_ABORT_SENT
 
- TXSTATUS_ALL
 
- TXSTATUS_ALL_SENT
 
- TXSTATUS_COLLISIONS_GET
 
- TXSTATUS_CRC_SENT
 
- TXSTATUS_DEFER
 
- TXSTATUS_EOF
 
- TXSTATUS_EOF_SENT
 
- TXSTATUS_EOM_SENT
 
- TXSTATUS_ERROR
 
- TXSTATUS_EXCESSCOLL
 
- TXSTATUS_EXCESSDEFER
 
- TXSTATUS_FIFO_EMPTY
 
- TXSTATUS_IDLE_SENT
 
- TXSTATUS_LATECOLL
 
- TXSTATUS_LEN
 
- TXSTATUS_NODESC
 
- TXSTATUS_PREAMBLE_SENT
 
- TXSTATUS_READ_INTERVAL
 
- TXSTATUS_TIMEOUT
 
- TXSTATUS_UNDERRUN
 
- TXSTAT_16COLLISIONS
 
- TXSTAT_BABBLED
 
- TXSTAT_COLLISION
 
- TXSTAT_DONE
 
- TXSTOPPED
 
- TXSTRT
 
- TXSTRTM
 
- TXSTS_FSPCAVAIL_MASK
 
- TXSTS_FSPCAVAIL_SHIFT
 
- TXSTS_QSPCAVAIL_MASK
 
- TXSTS_QSPCAVAIL_SHIFT
 
- TXSTS_QTOP_CHNEP_MASK
 
- TXSTS_QTOP_CHNEP_SHIFT
 
- TXSTS_QTOP_ODD
 
- TXSTS_QTOP_TERMINATE
 
- TXSTS_QTOP_TOKEN_MASK
 
- TXSTS_QTOP_TOKEN_SHIFT
 
- TXSYMPTOM_AUTO_P
 
- TXS_ACTIVE
 
- TXS_BR0
 
- TXS_BR1
 
- TXS_BR2
 
- TXS_BR3
 
- TXS_BUSY
 
- TXS_DTRXC
 
- TXS_ECLK
 
- TXS_FID_MASK
 
- TXS_FID_SHIFT
 
- TXS_IBRG
 
- TXS_IDLE
 
- TXS_IDLE2
 
- TXS_MU_MASK
 
- TXS_MU_SHIFT
 
- TXS_NEWFRAME
 
- TXS_PTX_MASK
 
- TXS_PTX_SHIFT
 
- TXS_RCLK
 
- TXS_SEQ_MASK
 
- TXS_STATUS_MASK
 
- TXS_TIMEOUT
 
- TXS_V
 
- TXS_WAIT
 
- TXTCR_HEAP_BASE
 
- TXTCR_HEAP_SIZE
 
- TXTDMS
 
- TXTH
 
- TXTH_MASK
 
- TXTIME_ASSIST_IS_ENABLED
 
- TXTL_DEFAULT
 
- TXTL_DMA
 
- TXTRAFFIC_INT_M
 
- TXTRHD_FULLDUPLEX
 
- TXTRHD_HALFDUPLEX
 
- TXTRHD_TXP
 
- TXTRHD_TXPEN
 
- TXTRHD_TXP_SHIFT
 
- TXTRHD_TXREN
 
- TXTRHD_TXRL
 
- TXTRHD_TXRL_SHIFT
 
- TXTS_IE
 
- TXTS_RDY
 
- TXT_IMM_BLT_CMD
 
- TXT_PRIV_CONFIG_REGS_BASE
 
- TXT_PUB_CONFIG_REGS_BASE
 
- TXUC_HW_CGC_EN
 
- TXUDR
 
- TXVAL_VALID_INIT
 
- TXW4C_IRA
 
- TXWBFLAG_ALLERR
 
- TXWBFLAG_COL
 
- TXWBFLAG_INT
 
- TXWBFLAG_OWN
 
- TXWBFLAG_TMOUT
 
- TXWBFLAG_TRYOUT
 
- TXWI_DESC_SIZE_4WORDS
 
- TXWI_DESC_SIZE_5WORDS
 
- TXWI_W0_AMPDU
 
- TXWI_W0_BW
 
- TXWI_W0_CF_ACK
 
- TXWI_W0_FRAG
 
- TXWI_W0_IFS
 
- TXWI_W0_MCS
 
- TXWI_W0_MIMO_PS
 
- TXWI_W0_MPDU_DENSITY
 
- TXWI_W0_PHYMODE
 
- TXWI_W0_SHORT_GI
 
- TXWI_W0_STBC
 
- TXWI_W0_TS
 
- TXWI_W0_TX_OP
 
- TXWI_W1_ACK
 
- TXWI_W1_BW_WIN_SIZE
 
- TXWI_W1_MPDU_TOTAL_BYTE_COUNT
 
- TXWI_W1_NSEQ
 
- TXWI_W1_PACKETID
 
- TXWI_W1_PACKETID_ENTRY
 
- TXWI_W1_PACKETID_QUEUE
 
- TXWI_W1_WIRELESS_CLI_ID
 
- TXWI_W2_IV
 
- TXWI_W3_EIV
 
- TXWRITEPTR_GET_PTR
 
- TXX9DMAC_H
 
- TXX9NDFMC_NS_TO_CYC
 
- TXX9_CE
 
- TXX9_CLOCKSOURCE_BITS
 
- TXX9_DIRECTMAP_BASE
 
- TXX9_DMA_CCR_ACKPOL
 
- TXX9_DMA_CCR_CHDN
 
- TXX9_DMA_CCR_CHNEN
 
- TXX9_DMA_CCR_CHRST
 
- TXX9_DMA_CCR_DBINH
 
- TXX9_DMA_CCR_DNCTL
 
- TXX9_DMA_CCR_EGREQ
 
- TXX9_DMA_CCR_EXTRQ
 
- TXX9_DMA_CCR_IMMCHN
 
- TXX9_DMA_CCR_INTENC
 
- TXX9_DMA_CCR_INTENE
 
- TXX9_DMA_CCR_INTENT
 
- TXX9_DMA_CCR_INTRQD
 
- TXX9_DMA_CCR_LE
 
- TXX9_DMA_CCR_MEMIO
 
- TXX9_DMA_CCR_REQPL
 
- TXX9_DMA_CCR_RVBYTE
 
- TXX9_DMA_CCR_SBINH
 
- TXX9_DMA_CCR_SMPCHN
 
- TXX9_DMA_CCR_SNGAD
 
- TXX9_DMA_CCR_USEXFSZ
 
- TXX9_DMA_CCR_XFACT
 
- TXX9_DMA_CCR_XFSZ
 
- TXX9_DMA_CCR_XFSZ_1
 
- TXX9_DMA_CCR_XFSZ_2
 
- TXX9_DMA_CCR_XFSZ_4
 
- TXX9_DMA_CCR_XFSZ_8
 
- TXX9_DMA_CCR_XFSZ_X16
 
- TXX9_DMA_CCR_XFSZ_X32
 
- TXX9_DMA_CCR_XFSZ_X4
 
- TXX9_DMA_CCR_XFSZ_X8
 
- TXX9_DMA_CSR_ABCHC
 
- TXX9_DMA_CSR_CFERR
 
- TXX9_DMA_CSR_CHERR
 
- TXX9_DMA_CSR_CHNEN
 
- TXX9_DMA_CSR_DESERR
 
- TXX9_DMA_CSR_EXTDN
 
- TXX9_DMA_CSR_NCHNC
 
- TXX9_DMA_CSR_NTRNFC
 
- TXX9_DMA_CSR_SORERR
 
- TXX9_DMA_CSR_STLXFER
 
- TXX9_DMA_CSR_XFACT
 
- TXX9_DMA_INITIAL_DESC_COUNT
 
- TXX9_DMA_MAX_COUNT
 
- TXX9_DMA_MAX_NR_CHANNELS
 
- TXX9_DMA_MCR_DIS
 
- TXX9_DMA_MCR_EIS
 
- TXX9_DMA_MCR_FIFUM
 
- TXX9_DMA_MCR_LE
 
- TXX9_DMA_MCR_MSTEN
 
- TXX9_DMA_MCR_RPRT
 
- TXX9_DMA_MCR_RSFIF
 
- TXX9_DMA_REG32
 
- TXX9_DMA_USE_SIMPLE_CHAIN
 
- TXX9_IMCLK
 
- TXX9_IOCLED_MAXLEDS
 
- TXX9_IRQ_BASE
 
- TXX9_NDFDTR
 
- TXX9_NDFIMR
 
- TXX9_NDFISR
 
- TXX9_NDFMCR
 
- TXX9_NDFMCR_ALE
 
- TXX9_NDFMCR_BSPRT
 
- TXX9_NDFMCR_CE
 
- TXX9_NDFMCR_CLE
 
- TXX9_NDFMCR_CS
 
- TXX9_NDFMCR_CS_MASK
 
- TXX9_NDFMCR_DMAREQ_128
 
- TXX9_NDFMCR_DMAREQ_256
 
- TXX9_NDFMCR_DMAREQ_512
 
- TXX9_NDFMCR_DMAREQ_MASK
 
- TXX9_NDFMCR_DMAREQ_NODMA
 
- TXX9_NDFMCR_ECC_ALL
 
- TXX9_NDFMCR_ECC_OFF
 
- TXX9_NDFMCR_ECC_ON
 
- TXX9_NDFMCR_ECC_READ
 
- TXX9_NDFMCR_ECC_RESET
 
- TXX9_NDFMCR_WE
 
- TXX9_NDFMCR_X16
 
- TXX9_NDFRSTR
 
- TXX9_NDFRSTR_RST
 
- TXX9_NDFSPR
 
- TXX9_NDFSR
 
- TXX9_NDFSR_BUSY
 
- TXX9_NDFSR_DMARUN
 
- TXX9_PCI_ERR_IGNORE
 
- TXX9_PCI_ERR_PANIC
 
- TXX9_PCI_ERR_REPORT
 
- TXX9_PCI_OPT_CLK_33
 
- TXX9_PCI_OPT_CLK_66
 
- TXX9_PCI_OPT_CLK_AUTO
 
- TXX9_PCI_OPT_CLK_MASK
 
- TXX9_PCI_OPT_PICMG
 
- TXX9_REGION_SIZE
 
- TXX9_SIBGR
 
- TXX9_SIBGR_BCLK_MASK
 
- TXX9_SIBGR_BCLK_T0
 
- TXX9_SIBGR_BCLK_T2
 
- TXX9_SIBGR_BCLK_T4
 
- TXX9_SIBGR_BCLK_T6
 
- TXX9_SIBGR_BRD_MASK
 
- TXX9_SICISR
 
- TXX9_SICISR_CTSS
 
- TXX9_SICISR_OERS
 
- TXX9_SICISR_RBRKD
 
- TXX9_SICISR_TRDY
 
- TXX9_SICISR_TXALS
 
- TXX9_SICISR_UBRKD
 
- TXX9_SIDICR
 
- TXX9_SIDICR_CTSAC
 
- TXX9_SIDICR_RDE
 
- TXX9_SIDICR_RIE
 
- TXX9_SIDICR_SPIE
 
- TXX9_SIDICR_STIE_CTSS
 
- TXX9_SIDICR_STIE_MASK
 
- TXX9_SIDICR_STIE_OERS
 
- TXX9_SIDICR_STIE_RBRKD
 
- TXX9_SIDICR_STIE_TRDY
 
- TXX9_SIDICR_STIE_TXALS
 
- TXX9_SIDICR_STIE_UBRKD
 
- TXX9_SIDICR_TDE
 
- TXX9_SIDICR_TIE
 
- TXX9_SIDISR
 
- TXX9_SIDISR_ERI
 
- TXX9_SIDISR_RDIS
 
- TXX9_SIDISR_RFDN_MASK
 
- TXX9_SIDISR_STIS
 
- TXX9_SIDISR_TDIS
 
- TXX9_SIDISR_TOUT
 
- TXX9_SIDISR_UBRK
 
- TXX9_SIDISR_UFER
 
- TXX9_SIDISR_UOER
 
- TXX9_SIDISR_UPER
 
- TXX9_SIDISR_UVALID
 
- TXX9_SIFCR
 
- TXX9_SIFCR_FRSTE
 
- TXX9_SIFCR_RDIL_1
 
- TXX9_SIFCR_RDIL_12
 
- TXX9_SIFCR_RDIL_4
 
- TXX9_SIFCR_RDIL_8
 
- TXX9_SIFCR_RDIL_MASK
 
- TXX9_SIFCR_RDIL_MAX
 
- TXX9_SIFCR_RFRST
 
- TXX9_SIFCR_SWRST
 
- TXX9_SIFCR_TDIL_1
 
- TXX9_SIFCR_TDIL_4
 
- TXX9_SIFCR_TDIL_8
 
- TXX9_SIFCR_TDIL_MASK
 
- TXX9_SIFCR_TDIL_MAX
 
- TXX9_SIFCR_TFRST
 
- TXX9_SIFLCR
 
- TXX9_SIFLCR_RCS
 
- TXX9_SIFLCR_RSDE
 
- TXX9_SIFLCR_RTSSC
 
- TXX9_SIFLCR_RTSTL_MASK
 
- TXX9_SIFLCR_RTSTL_MAX
 
- TXX9_SIFLCR_TBRK
 
- TXX9_SIFLCR_TES
 
- TXX9_SIFLCR_TSDE
 
- TXX9_SILCR
 
- TXX9_SILCR_SCS_IMCLK
 
- TXX9_SILCR_SCS_IMCLK_BG
 
- TXX9_SILCR_SCS_MASK
 
- TXX9_SILCR_SCS_SCLK
 
- TXX9_SILCR_SCS_SCLK_BG
 
- TXX9_SILCR_UEPS
 
- TXX9_SILCR_UMODE_7BIT
 
- TXX9_SILCR_UMODE_8BIT
 
- TXX9_SILCR_UMODE_MASK
 
- TXX9_SILCR_UPEN
 
- TXX9_SILCR_USBL_1BIT
 
- TXX9_SILCR_USBL_2BIT
 
- TXX9_SILCR_USBL_MASK
 
- TXX9_SIO_RX_FIFO
 
- TXX9_SIO_TX_FIFO
 
- TXX9_SIRFIFO
 
- TXX9_SITFIFO
 
- TXX9_TIMER_BITS
 
- TXX9_TTY_MAJOR
 
- TXX9_TTY_MINOR_START
 
- TXX9_TTY_NAME
 
- TXXGXS_INT_M
 
- TXXG_CONF1_VAL
 
- TX_1024_TO_1518_PKT
 
- TX_10G_PORT_BASE
 
- TX_10M_IDLE_EN
 
- TX_10M_PS_EN
 
- TX_128_TO_255_PKT
 
- TX_1519_TO_MAX_PKT
 
- TX_16_COL
 
- TX_16_COL_ENBL
 
- TX_1S
 
- TX_256_511_PKT
 
- TX_2S
 
- TX_3945_STATUS_DIRECT_DONE
 
- TX_3945_STATUS_FAIL_ABORTED
 
- TX_3945_STATUS_FAIL_BT_RETRY
 
- TX_3945_STATUS_FAIL_DEST_PS
 
- TX_3945_STATUS_FAIL_FIFO_UNDERRUN
 
- TX_3945_STATUS_FAIL_FRAG_DROPPED
 
- TX_3945_STATUS_FAIL_FRAME_FLUSHED
 
- TX_3945_STATUS_FAIL_INSUFFICIENT_CF_POLL
 
- TX_3945_STATUS_FAIL_LIFE_EXPIRE
 
- TX_3945_STATUS_FAIL_LONG_LIMIT
 
- TX_3945_STATUS_FAIL_MGMNT_ABORT
 
- TX_3945_STATUS_FAIL_NEXT_FRAG
 
- TX_3945_STATUS_FAIL_NO_BEACON_ON_RADAR
 
- TX_3945_STATUS_FAIL_SHORT_LIMIT
 
- TX_3945_STATUS_FAIL_STA_INVALID
 
- TX_3945_STATUS_FAIL_TID_DISABLE
 
- TX_3945_STATUS_FAIL_TX_LOCKED
 
- TX_3945_STATUS_SUCCESS
 
- TX_3S
 
- TX_4S
 
- TX_512_TO_1023_PKT
 
- TX_64_PKT
 
- TX_65_TO_127_PKT
 
- TX_AAL5_LIMIT
 
- TX_ABORT
 
- TX_ABORT_REQUIRED_MSK
 
- TX_ABR
 
- TX_AC3_CAPABILITIES
 
- TX_AC3_ENABLE
 
- TX_ACTRL0
 
- TX_ACTRL0_TXPOL_FLIP
 
- TX_AC_BE_FIFO
 
- TX_AC_BK_FIFO
 
- TX_AC_VI_FIFO
 
- TX_AC_VO_FIFO
 
- TX_ADDR_MD
 
- TX_ADDR_MD_MODE32
 
- TX_AFTER_381
 
- TX_AFTER_ALL
 
- TX_AGG_CNT
 
- TX_AGG_CNT0
 
- TX_AGG_CNT0_AGG_SIZE_1_COUNT
 
- TX_AGG_CNT0_AGG_SIZE_2_COUNT
 
- TX_AGG_CNT1
 
- TX_AGG_CNT1_AGG_SIZE_3_COUNT
 
- TX_AGG_CNT1_AGG_SIZE_4_COUNT
 
- TX_AGG_CNT2
 
- TX_AGG_CNT2_AGG_SIZE_5_COUNT
 
- TX_AGG_CNT2_AGG_SIZE_6_COUNT
 
- TX_AGG_CNT3
 
- TX_AGG_CNT3_AGG_SIZE_7_COUNT
 
- TX_AGG_CNT3_AGG_SIZE_8_COUNT
 
- TX_AGG_CNT4
 
- TX_AGG_CNT4_AGG_SIZE_10_COUNT
 
- TX_AGG_CNT4_AGG_SIZE_9_COUNT
 
- TX_AGG_CNT5
 
- TX_AGG_CNT5_AGG_SIZE_11_COUNT
 
- TX_AGG_CNT5_AGG_SIZE_12_COUNT
 
- TX_AGG_CNT6
 
- TX_AGG_CNT6_AGG_SIZE_13_COUNT
 
- TX_AGG_CNT6_AGG_SIZE_14_COUNT
 
- TX_AGG_CNT7
 
- TX_AGG_CNT7_AGG_SIZE_15_COUNT
 
- TX_AGG_CNT7_AGG_SIZE_16_COUNT
 
- TX_AGG_CNT_AGG_TX_COUNT
 
- TX_AGG_CNT_NON_AGG_TX_COUNT
 
- TX_AGG_MAX_THRESHOLD
 
- TX_ALC_CFG_0
 
- TX_ALC_CFG_0_CH_INIT_0
 
- TX_ALC_CFG_0_CH_INIT_1
 
- TX_ALC_CFG_0_LIMIT_0
 
- TX_ALC_CFG_0_LIMIT_1
 
- TX_ALC_CFG_1
 
- TX_ALC_CFG_1_RF_TOS_DLY
 
- TX_ALC_CFG_1_RF_TOS_ENABLE
 
- TX_ALC_CFG_1_RF_TOS_TIMEOUT
 
- TX_ALC_CFG_1_ROS_BUSY_EN
 
- TX_ALC_CFG_1_TX0_GAIN_FINE
 
- TX_ALC_CFG_1_TX0_RF_GAIN_ATTEN
 
- TX_ALC_CFG_1_TX1_GAIN_FINE
 
- TX_ALC_CFG_1_TX1_RF_GAIN_ATTEN
 
- TX_ALC_CFG_1_TX_TEMP_COMP
 
- TX_ALC_VGA3
 
- TX_ALC_VGA3_TX0_ALC_VGA2
 
- TX_ALC_VGA3_TX0_ALC_VGA3
 
- TX_ALC_VGA3_TX1_ALC_VGA2
 
- TX_ALC_VGA3_TX1_ALC_VGA3
 
- TX_ALIGN
 
- TX_AMPLITUDE
 
- TX_AMP_VAL
 
- TX_ANA_CTRL_REG_1
 
- TX_ANA_CTRL_REG_2
 
- TX_ANA_CTRL_REG_3
 
- TX_ANA_CTRL_REG_4
 
- TX_ANA_CTRL_REG_5
 
- TX_ANNOUNCE
 
- TX_ANTL_SHT
 
- TX_ANT_CCK_SHT
 
- TX_ANT_CONFIGURATION_CMD
 
- TX_ANT_HT_SHT
 
- TX_ANY_COL_ENBL
 
- TX_APPEND_FCS
 
- TX_AREA_END
 
- TX_AREA_START
 
- TX_ASYNC
 
- TX_ATIM_FIFO
 
- TX_ATTN_MASK
 
- TX_ATTN_SHIFT
 
- TX_ATTN_SMASK
 
- TX_AUDIO_INPUT_LEVEL_RANGE_SET
 
- TX_AUDIO_LEVEL_TEST
 
- TX_AUDIO_LEVEL_TEST_THRESHOLD
 
- TX_AUTHENTICATE_LENGTH
 
- TX_AUTHENTICATE_LENGTH_LSB
 
- TX_AUTHENTICATE_LENGTH_MSB
 
- TX_AUTO_NEG_MASK
 
- TX_AUTO_NEG_SHIFT
 
- TX_BACKOFF_SEED_MASK
 
- TX_BACK_OFF_LIM
 
- TX_BANDWIDTH
 
- TX_BAND_CFG
 
- TX_BAND_CFG_A
 
- TX_BAND_CFG_BG
 
- TX_BAND_CFG_HT40_MINUS
 
- TX_BAND_SET
 
- TX_BASE_ADDR
 
- TX_BASE_ADDRH
 
- TX_BASE_ADDRL
 
- TX_BASE_PTR
 
- TX_BASE_PTR0
 
- TX_BASE_PTR1
 
- TX_BASE_PTR2
 
- TX_BASE_PTR3
 
- TX_BASE_PTR4
 
- TX_BASE_PTR5
 
- TX_BATCH_SIZE
 
- TX_BCAST
 
- TX_BCAST_PKTS
 
- TX_BCMC_FIFO
 
- TX_BD
 
- TX_BD_CFA_ACTION
 
- TX_BD_CFA_ACTION_SHIFT
 
- TX_BD_CFA_META_KEY
 
- TX_BD_CFA_META_KEY_SHIFT
 
- TX_BD_CFA_META_KEY_VLAN
 
- TX_BD_CFA_META_MASK
 
- TX_BD_CFA_META_PRI_MASK
 
- TX_BD_CFA_META_PRI_SHIFT
 
- TX_BD_CFA_META_TPID_MASK
 
- TX_BD_CFA_META_TPID_SHIFT
 
- TX_BD_CFA_META_VID_MASK
 
- TX_BD_CRC
 
- TX_BD_CS
 
- TX_BD_DF
 
- TX_BD_FLAGS_BD_CNT
 
- TX_BD_FLAGS_BD_CNT_SHIFT
 
- TX_BD_FLAGS_COAL_NOW
 
- TX_BD_FLAGS_CONN_FAULT
 
- TX_BD_FLAGS_DONT_GEN_CRC
 
- TX_BD_FLAGS_END
 
- TX_BD_FLAGS_IPID_FMT
 
- TX_BD_FLAGS_IP_CKSUM
 
- TX_BD_FLAGS_LHINT
 
- TX_BD_FLAGS_LHINT_1024_TO_2047
 
- TX_BD_FLAGS_LHINT_2048_AND_LARGER
 
- TX_BD_FLAGS_LHINT_512_AND_SMALLER
 
- TX_BD_FLAGS_LHINT_512_TO_1023
 
- TX_BD_FLAGS_LHINT_SHIFT
 
- TX_BD_FLAGS_LSO
 
- TX_BD_FLAGS_NO_CMPL
 
- TX_BD_FLAGS_NO_CRC
 
- TX_BD_FLAGS_PACKET_END
 
- TX_BD_FLAGS_STAMP
 
- TX_BD_FLAGS_START
 
- TX_BD_FLAGS_SW_FLAGS
 
- TX_BD_FLAGS_SW_LSO
 
- TX_BD_FLAGS_SW_OPTION_WORD
 
- TX_BD_FLAGS_SW_SNAP
 
- TX_BD_FLAGS_TCP6_OFF0_MSK
 
- TX_BD_FLAGS_TCP6_OFF0_SHL
 
- TX_BD_FLAGS_TCP6_OFF4_SHL
 
- TX_BD_FLAGS_TCP_UDP_CHKSUM
 
- TX_BD_FLAGS_TCP_UDP_CKSUM
 
- TX_BD_FLAGS_T_IPID
 
- TX_BD_FLAGS_T_IP_CHKSUM
 
- TX_BD_FLAGS_VLAN_TAG
 
- TX_BD_HSIZE
 
- TX_BD_HSIZE_SHIFT
 
- TX_BD_IRQ
 
- TX_BD_LC
 
- TX_BD_LEN
 
- TX_BD_LEN_MASK
 
- TX_BD_LEN_SHIFT
 
- TX_BD_NUM
 
- TX_BD_NUM_DEFAULT
 
- TX_BD_NUM_MAX
 
- TX_BD_NUM_VAL
 
- TX_BD_PAD
 
- TX_BD_POFF
 
- TX_BD_READY
 
- TX_BD_RETRY
 
- TX_BD_RETRY_MASK
 
- TX_BD_RING_LEN
 
- TX_BD_RL
 
- TX_BD_STATS
 
- TX_BD_TCP6_OFF2_SHL
 
- TX_BD_TYPE
 
- TX_BD_TYPE_LONG_TX_BD
 
- TX_BD_TYPE_SHORT_TX_BD
 
- TX_BD_UR
 
- TX_BD_WRAP
 
- TX_BID_ERROR
 
- TX_BINTERVAL
 
- TX_BIST_CTRL
 
- TX_BIST_UDDWR
 
- TX_BIT_CHAN
 
- TX_BIT_MASK
 
- TX_BIT_SHIFT
 
- TX_BLOCKED_CMD_RESERVE
 
- TX_BOF_LIM_DEF
 
- TX_BQ_ALEMPTY_INT
 
- TX_BQ_ALEMPTY_TH
 
- TX_BQ_ALFULL_INT
 
- TX_BQ_ALFULL_TH
 
- TX_BQ_DEPTH
 
- TX_BQ_EMPTY_INT
 
- TX_BQ_FULL_INT
 
- TX_BQ_OUT_INT
 
- TX_BQ_RD_ADDR
 
- TX_BQ_REG_EN
 
- TX_BQ_START_ADDR
 
- TX_BQ_VLDDESC_CNT
 
- TX_BQ_WR_ADDR
 
- TX_BROADCAST_PACKET_COUNTER
 
- TX_BUF
 
- TX_BUFF
 
- TX_BUFFERS
 
- TX_BUFFER_EMPTIED
 
- TX_BUFFER_INFO_FLAG_ACTIVE
 
- TX_BUFFER_INFO_FLAG_IGNORE_SYNC
 
- TX_BUFFER_INFO_FLAG_SKB_FRAGMENT
 
- TX_BUFFER_INFO_FLAG_TIMESTAMP_REQUESTED
 
- TX_BUFFS_AVAIL
 
- TX_BUFF_ADDR
 
- TX_BUFF_COUNT
 
- TX_BUFF_MASK
 
- TX_BUFF_MOD_MASK
 
- TX_BUFF_RINGSIZE
 
- TX_BUFF_SIZE
 
- TX_BUFLIMIT
 
- TX_BUF_ALLOC
 
- TX_BUF_BASE
 
- TX_BUF_BRS
 
- TX_BUF_EFC
 
- TX_BUF_ESI
 
- TX_BUF_FDF
 
- TX_BUF_L
 
- TX_BUF_LEN
 
- TX_BUF_MM_MASK
 
- TX_BUF_MM_SHIFT
 
- TX_BUF_RTR
 
- TX_BUF_SIZE
 
- TX_BUF_SIZE_MAX
 
- TX_BUF_TOT_LEN
 
- TX_BUF_XTD
 
- TX_BUG_FIFO_LIMIT
 
- TX_BURST_MASK
 
- TX_BURST_SIZE_16_64BIT
 
- TX_BURST_SIZE_4_64BIT
 
- TX_BUSY
 
- TX_BUS_ERROR
 
- TX_BUS_MASTER_COMPLETE
 
- TX_BW_BURST
 
- TX_BW_BURST_MOVED
 
- TX_BW_CONTROL_ABSENT
 
- TX_BW_CONTROL_NEW_LAYOUT
 
- TX_BW_CONTROL_OLD_LAYOUT
 
- TX_BW_MTU
 
- TX_BW_MTU_MOVED
 
- TX_BW_RATE
 
- TX_BW_RATE_MOVED
 
- TX_BYPASS_8B10B_ENABLE
 
- TX_BYTES
 
- TX_BYTES_TRANSFERRED
 
- TX_BYTE_COUNTER
 
- TX_CATBUF1
 
- TX_CATBUF2
 
- TX_CELL_COUNT_OFF
 
- TX_CFG
 
- TX_CFGCLKFREQVAL
 
- TX_CFG_A
 
- TX_CFG_A_TX_HP_WB_EN_
 
- TX_CFG_A_TX_HP_WB_ON_INT_TMR_
 
- TX_CFG_A_TX_HP_WB_THRES_MASK_
 
- TX_CFG_A_TX_HP_WB_THRES_SET_
 
- TX_CFG_A_TX_PF_PRI_THRES_MASK_
 
- TX_CFG_A_TX_PF_PRI_THRES_SET_
 
- TX_CFG_A_TX_PF_THRES_MASK_
 
- TX_CFG_A_TX_PF_THRES_SET_
 
- TX_CFG_A_TX_TMR_HPWB_SEL_IOC_
 
- TX_CFG_B
 
- TX_CFG_B_TDMABL_512_
 
- TX_CFG_B_TX_RING_LEN_MASK_
 
- TX_CFG_C
 
- TX_CFG_COMPWB_Q1
 
- TX_CFG_COMPWB_Q2
 
- TX_CFG_COMPWB_Q3
 
- TX_CFG_COMPWB_Q4
 
- TX_CFG_CTX_SEL_MASK
 
- TX_CFG_CTX_SEL_SHIFT
 
- TX_CFG_C_TX_DMA_INT_EN_AUTO_CLR_
 
- TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_
 
- TX_CFG_C_TX_INT_EN_R2C_
 
- TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_
 
- TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_
 
- TX_CFG_DESC_RING0_MASK
 
- TX_CFG_DESC_RING0_SHIFT
 
- TX_CFG_DESC_RINGN_MASK
 
- TX_CFG_DESC_RINGN_SHIFT
 
- TX_CFG_DMA_EN
 
- TX_CFG_DMA_RDPIPE_DIS
 
- TX_CFG_EN
 
- TX_CFG_FIFO_FLUSH_
 
- TX_CFG_FIFO_PIO_SEL
 
- TX_CFG_INTR_COMPWB_DIS
 
- TX_CFG_ON_
 
- TX_CFG_PACED_MODE
 
- TX_CFG_PREAM
 
- TX_CFG_RESET
 
- TX_CFG_STOP_
 
- TX_CFG_STOP_TX_
 
- TX_CFG_TXD_DUMP_
 
- TX_CFG_TXSAO_
 
- TX_CFG_TXS_DUMP_
 
- TX_CFG_TX_ON_
 
- TX_CHANGE
 
- TX_CHANNEL_CONFIG_COMMAND_OFF
 
- TX_CHANNEL_CONFIG_DATA_OFF
 
- TX_CHANNEL_CONFIG_MULT
 
- TX_CHANNEL_PORT_OFF
 
- TX_CHANS
 
- TX_CHAN_CTRL_REG
 
- TX_CHAN_S
 
- TX_CHAN_V
 
- TX_CHECKSUM_ERROR
 
- TX_CHNL_CTRL
 
- TX_CHNL_STS
 
- TX_CIC_FULL
 
- TX_CID
 
- TX_CLEAN_BATCHSIZE
 
- TX_CLEAN_INTERVAL
 
- TX_CLEAR
 
- TX_CLEAR_WB
 
- TX_CLK_110
 
- TX_CLK_1200
 
- TX_CLK_150
 
- TX_CLK_1800
 
- TX_CLK_19200
 
- TX_CLK_2000
 
- TX_CLK_2400
 
- TX_CLK_300
 
- TX_CLK_38400
 
- TX_CLK_4800
 
- TX_CLK_600
 
- TX_CLK_75
 
- TX_CLK_9600
 
- TX_CLK_CGC_ON
 
- TX_CLK_DELAY_MSK
 
- TX_CLK_DELAY_SHFT
 
- TX_CLK_GATE_EN
 
- TX_CLK_POL_MASK
 
- TX_CLK_POL_RISING
 
- TX_CLK_SEL_MASK
 
- TX_CLK_SEL_SRG
 
- TX_CLK_SHIFT_BASE
 
- TX_CLK_STOP_EN
 
- TX_CLOCK_DIVIDER_REG
 
- TX_CL_CAL
 
- TX_CMD
 
- TX_CMDDESC_SIZE_RTL8192S
 
- TX_CMD_A_16_BYTE_ALGN_
 
- TX_CMD_A_32_BYTE_ALGN_
 
- TX_CMD_A_4_BYTE_ALGN_
 
- TX_CMD_A_BUF_END_ALGN_
 
- TX_CMD_A_BUF_SIZE_
 
- TX_CMD_A_DATA_OFFSET_
 
- TX_CMD_A_FCS
 
- TX_CMD_A_FCS_
 
- TX_CMD_A_FIRST_SEG_
 
- TX_CMD_A_ICE_
 
- TX_CMD_A_IGE_
 
- TX_CMD_A_INT_16_BYTE_ALGN_
 
- TX_CMD_A_INT_32_BYTE_ALGN_
 
- TX_CMD_A_INT_4_BYTE_ALGN_
 
- TX_CMD_A_INT_BUF_END_ALGN_
 
- TX_CMD_A_INT_DATA_OFFSET_
 
- TX_CMD_A_INT_FIRST_SEG_
 
- TX_CMD_A_INT_LAST_SEG_
 
- TX_CMD_A_INT_ON_COMP_
 
- TX_CMD_A_IPE
 
- TX_CMD_A_IPE_
 
- TX_CMD_A_IVTG
 
- TX_CMD_A_IVTG_
 
- TX_CMD_A_LAST_SEG_
 
- TX_CMD_A_LEN
 
- TX_CMD_A_LEN_MASK_
 
- TX_CMD_A_LSO
 
- TX_CMD_A_LSO_
 
- TX_CMD_A_ON_COMP_
 
- TX_CMD_A_RVTG
 
- TX_CMD_A_RVTG_
 
- TX_CMD_A_TPE
 
- TX_CMD_A_TPE_
 
- TX_CMD_B_ADD_CRC_DISABLE_
 
- TX_CMD_B_ADD_CRC_DIS_
 
- TX_CMD_B_CSUM_ENABLE
 
- TX_CMD_B_DISABLE_PADDING_
 
- TX_CMD_B_DIS_PADDING_
 
- TX_CMD_B_FRAME_LENGTH_
 
- TX_CMD_B_MSS
 
- TX_CMD_B_MSS_MASK_
 
- TX_CMD_B_MSS_MIN_
 
- TX_CMD_B_MSS_SHIFT
 
- TX_CMD_B_MSS_SHIFT_
 
- TX_CMD_B_PKT_BYTE_LENGTH_
 
- TX_CMD_B_PKT_TAG_
 
- TX_CMD_B_VTAG
 
- TX_CMD_B_VTAG_CFI_MASK_
 
- TX_CMD_B_VTAG_MASK_
 
- TX_CMD_B_VTAG_PRI_MASK_
 
- TX_CMD_B_VTAG_VID_MASK_
 
- TX_CMD_FLG_ACK
 
- TX_CMD_FLG_ACK_MSK
 
- TX_CMD_FLG_AGG_CCMP_MSK
 
- TX_CMD_FLG_ANT_A_MSK
 
- TX_CMD_FLG_ANT_B_MSK
 
- TX_CMD_FLG_ANT_SEL_MSK
 
- TX_CMD_FLG_BAR
 
- TX_CMD_FLG_BT_DIS
 
- TX_CMD_FLG_BT_PRIO_POS
 
- TX_CMD_FLG_CALIB
 
- TX_CMD_FLG_CSI_FDBK2HOST
 
- TX_CMD_FLG_CTS_MSK
 
- TX_CMD_FLG_DUR
 
- TX_CMD_FLG_DUR_MSK
 
- TX_CMD_FLG_EXEC_PAPD
 
- TX_CMD_FLG_FULL_TXOP_PROT_MSK
 
- TX_CMD_FLG_FW_DROP
 
- TX_CMD_FLG_HCCA_CHUNK
 
- TX_CMD_FLG_HT_NDPA
 
- TX_CMD_FLG_IGNORE_BT
 
- TX_CMD_FLG_IMM_BA_RSP_MASK
 
- TX_CMD_FLG_KEEP_SEQ_CTL
 
- TX_CMD_FLG_MH_PAD
 
- TX_CMD_FLG_MH_PAD_MSK
 
- TX_CMD_FLG_MORE_FRAG
 
- TX_CMD_FLG_MORE_FRAG_MSK
 
- TX_CMD_FLG_PAPD_TYPE
 
- TX_CMD_FLG_PROT_REQUIRE
 
- TX_CMD_FLG_PROT_REQUIRE_MSK
 
- TX_CMD_FLG_RESP_TO_DRV
 
- TX_CMD_FLG_RTS_MSK
 
- TX_CMD_FLG_SEQ_CTL
 
- TX_CMD_FLG_SEQ_CTL_MSK
 
- TX_CMD_FLG_STA_RATE
 
- TX_CMD_FLG_STA_RATE_MSK
 
- TX_CMD_FLG_TKIP_MIC_DONE
 
- TX_CMD_FLG_TSF
 
- TX_CMD_FLG_TSF_MSK
 
- TX_CMD_FLG_TXOP_PROT
 
- TX_CMD_FLG_VHT_NDPA
 
- TX_CMD_FLG_WRITE_TX_POWER
 
- TX_CMD_LIFE_TIME_DEFAULT
 
- TX_CMD_LIFE_TIME_EXPIRED_FRAME
 
- TX_CMD_LIFE_TIME_INFINITE
 
- TX_CMD_LIFE_TIME_PROBE_RESP
 
- TX_CMD_OFFLD_AMSDU
 
- TX_CMD_OFFLD_IP_HDR
 
- TX_CMD_OFFLD_L3_EN
 
- TX_CMD_OFFLD_L4_EN
 
- TX_CMD_OFFLD_MH_SIZE
 
- TX_CMD_OFFLD_PAD
 
- TX_CMD_PORT
 
- TX_CMD_SEC_CCM
 
- TX_CMD_SEC_EXT
 
- TX_CMD_SEC_GCMP
 
- TX_CMD_SEC_KEY128
 
- TX_CMD_SEC_KEY_FROM_TABLE
 
- TX_CMD_SEC_MSK
 
- TX_CMD_SEC_SHIFT
 
- TX_CMD_SEC_TKIP
 
- TX_CMD_SEC_WEP
 
- TX_CMD_SEC_WEP_KEY_IDX_MSK
 
- TX_CMD_SEC_WEP_KEY_IDX_POS
 
- TX_CMP_ERRORS_BUFFER_ERROR
 
- TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT
 
- TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG
 
- TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR
 
- TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS
 
- TX_CMP_ERRORS_DMA_ERROR
 
- TX_CMP_ERRORS_EXCESSIVE_BD_LEN
 
- TX_CMP_ERRORS_HINT_TOO_SHORT
 
- TX_CMP_ERRORS_ZERO_LENGTH_PKT
 
- TX_CMP_FLAGS_ERROR
 
- TX_CMP_FLAGS_PUSH
 
- TX_CMP_TYPE
 
- TX_CMP_V
 
- TX_CMP_VALID
 
- TX_CNTL_CSR
 
- TX_CNTL_CSR_ABORT_TX_AC0
 
- TX_CNTL_CSR_ABORT_TX_AC1
 
- TX_CNTL_CSR_ABORT_TX_AC2
 
- TX_CNTL_CSR_ABORT_TX_AC3
 
- TX_CNTL_CSR_ABORT_TX_MGMT
 
- TX_CNTL_CSR_KICK_TX_AC0
 
- TX_CNTL_CSR_KICK_TX_AC1
 
- TX_CNTL_CSR_KICK_TX_AC2
 
- TX_CNTL_CSR_KICK_TX_AC3
 
- TX_CNTL_CSR_KICK_TX_MGMT
 
- TX_CNTRL0_2DEFER
 
- TX_CNTRL0_APPEND_FCS
 
- TX_CNTRL0_HALFDUPLEX
 
- TX_CNTRL0_PAD_EN
 
- TX_CNTRL0_RETRY
 
- TX_CNTRL0_RMII
 
- TX_CNTRL0_TX_EN
 
- TX_CNTRL1_RETRIES
 
- TX_CNT_INUSE_MASK
 
- TX_COAL_INTS_ONLY
 
- TX_COE_EN
 
- TX_COLL_CNT_MASK
 
- TX_COL_COUNT
 
- TX_COL_COUNT_MASK
 
- TX_COL_COUNT_OVRFLOW_ENBL
 
- TX_COL_DEF
 
- TX_COL_OVRFLW
 
- TX_COL_THR
 
- TX_COMMAND
 
- TX_COMPLETE
 
- TX_COMPLETE_REQUIRED_BIT
 
- TX_COMPLETE_STATUS_NOLINK
 
- TX_COMPLETE_STATUS_OTHER
 
- TX_COMPLETE_STATUS_RETRIES
 
- TX_COMPLETE_STATUS_SUCCESS
 
- TX_COMPLETE_STATUS_TIMEOUT
 
- TX_COMPL_Q_ADDR_SIZE
 
- TX_COMPWB_LSB_MASK
 
- TX_COMPWB_LSB_SHIFT
 
- TX_COMPWB_MSB_MASK
 
- TX_COMPWB_MSB_SHIFT
 
- TX_COMPWB_NEXT
 
- TX_COMPWB_SIZE
 
- TX_COMP_Q
 
- TX_CONFIG
 
- TX_CONFIG_OFF
 
- TX_CONTEXT_DESC2_MSS_INDEX
 
- TX_CONTEXT_DESC2_MSS_LEN
 
- TX_CONTEXT_DESC2_MSS_POS
 
- TX_CONTEXT_DESC2_MSS_WIDTH
 
- TX_CONTEXT_DESC3_CTXT_INDEX
 
- TX_CONTEXT_DESC3_CTXT_LEN
 
- TX_CONTEXT_DESC3_CTXT_POS
 
- TX_CONTEXT_DESC3_CTXT_WIDTH
 
- TX_CONTEXT_DESC3_TCMSSV_INDEX
 
- TX_CONTEXT_DESC3_TCMSSV_LEN
 
- TX_CONTEXT_DESC3_TCMSSV_POS
 
- TX_CONTEXT_DESC3_TCMSSV_WIDTH
 
- TX_CONTEXT_DESC3_VLTV_INDEX
 
- TX_CONTEXT_DESC3_VLTV_LEN
 
- TX_CONTEXT_DESC3_VLTV_POS
 
- TX_CONTEXT_DESC3_VLTV_WIDTH
 
- TX_CONTEXT_DESC3_VT_INDEX
 
- TX_CONTEXT_DESC3_VT_LEN
 
- TX_CONTEXT_DESC3_VT_POS
 
- TX_CONTEXT_DESC3_VT_WIDTH
 
- TX_CONTINUE
 
- TX_CONTROL_CALC_CSUM_MASK
 
- TX_CONTROL_FRAME_COUNTER
 
- TX_COUNTEVT
 
- TX_CPU_BASE
 
- TX_CPU_MODE
 
- TX_CPU_PGMCTR
 
- TX_CPU_SCRATCH_BASE
 
- TX_CPU_SCRATCH_SIZE
 
- TX_CPU_STATE
 
- TX_CP_CAN_ID
 
- TX_CQ_LEN
 
- TX_CRC1
 
- TX_CRC2
 
- TX_CS
 
- TX_CSUM_CRC16
 
- TX_CSUM_CRC32
 
- TX_CSUM_CRC32C
 
- TX_CSUM_FCOE
 
- TX_CSUM_IP
 
- TX_CSUM_NONE
 
- TX_CSUM_SUCCESS
 
- TX_CSUM_TCP
 
- TX_CSUM_TCPIP
 
- TX_CSUM_TCPIP6
 
- TX_CSUM_TSO
 
- TX_CSUM_UDP
 
- TX_CSUM_UDPIP
 
- TX_CSUM_UDPIP6
 
- TX_CS_CONF_PART_ERR
 
- TX_CS_DBG
 
- TX_CS_DBG_PKT_CNT
 
- TX_CS_LASTMARK
 
- TX_CS_LASTMARK_SHIFT
 
- TX_CS_MB
 
- TX_CS_MBOX_ERR
 
- TX_CS_MK
 
- TX_CS_MMK
 
- TX_CS_NACK_PKT_RD
 
- TX_CS_NACK_PREF
 
- TX_CS_N_DELAY_MSK
 
- TX_CS_N_DELAY_SHFT
 
- TX_CS_PKT_CNT
 
- TX_CS_PKT_CNT_SHIFT
 
- TX_CS_PKT_PRT_ERR
 
- TX_CS_PKT_SIZE_ERR
 
- TX_CS_PREF_BUF_PAR_ERR
 
- TX_CS_RST
 
- TX_CS_RST_STATE
 
- TX_CS_SNG_STATE
 
- TX_CS_STOP_N_GO
 
- TX_CS_TX_RING_OFLOW
 
- TX_CTL_CMD
 
- TX_CTL_CT_MASK
 
- TX_CTL_CT_SHIFT
 
- TX_CTL_ET_MASK
 
- TX_CTL_ET_SHIFT
 
- TX_CTL_FIFO
 
- TX_CTL_NT_MASK
 
- TX_CTL_NT_SHIFT
 
- TX_CTL_OFFSET
 
- TX_CTL_PKTS
 
- TX_CTRL_DUPLEX
 
- TX_CTRL_FMODE
 
- TX_CTRL_SBENAB
 
- TX_CTRL_SMALL_SLOT
 
- TX_CTRL_TXE
 
- TX_CTX_IDX
 
- TX_CTX_IDX0
 
- TX_CTX_IDX1
 
- TX_CTX_IDX2
 
- TX_CTX_IDX3
 
- TX_CTX_IDX4
 
- TX_CTX_IDX5
 
- TX_CUR1_2X
 
- TX_CURBUF_ADDR
 
- TX_CURBUF_LENGTH
 
- TX_CURDESC_PTR
 
- TX_CUR_16_MA
 
- TX_DAC_FREQUENCY
 
- TX_DATA
 
- TX_DATA_12_BITS
 
- TX_DATA_24_BITS
 
- TX_DATA_DDR_MODE
 
- TX_DATA_DELAY_MSK
 
- TX_DATA_DELAY_SHFT
 
- TX_DATA_FIFO
 
- TX_DATA_OE_DELAY_MSK
 
- TX_DATA_OE_DELAY_SHFT
 
- TX_DATA_RESET
 
- TX_DATA_SDR_MODE
 
- TX_DBG
 
- TX_DCNT
 
- TX_DC_ENTRIES
 
- TX_DC_ENTRIES_ORDER
 
- TX_DEAUTHENTICATE_LENGTH
 
- TX_DEAUTHENTICATE_LENGTH_LSB
 
- TX_DEAUTHENTICATE_LENGTH_MSB
 
- TX_DEBUG
 
- TX_DEEMPH_GEN1_VAL
 
- TX_DEEMPH_GEN2_3_5DB_VAL
 
- TX_DEEMPH_GEN2_6DB_VAL
 
- TX_DEFAULT_STEERING
 
- TX_DEFERRAL_PACKET_COUNTER
 
- TX_DEFERRED
 
- TX_DEF_PENDING
 
- TX_DELETE
 
- TX_DESC
 
- TX_DESC0_DMA_OWN
 
- TX_DESC0_PKT_LATE_COL
 
- TX_DESC0_RX_PKT_EXS_COL
 
- TX_DESC1_BUF_SIZE_MASK
 
- TX_DESC1_END
 
- TX_DESC1_FIFO_COMPLETE
 
- TX_DESC1_FTS
 
- TX_DESC1_INTR_COMPLETE
 
- TX_DESC1_LTS
 
- TX_DESC2_ADDRESS_PHYS
 
- TX_DESC2_ADDRESS_VIRT
 
- TX_DESCRIPTOR
 
- TX_DESCRIPTORS
 
- TX_DESCRIPTOR_PORT_OFF
 
- TX_DESCRIPTOR_REG_OFF
 
- TX_DESCR_SIZE
 
- TX_DESCS
 
- TX_DESC_AGGR_SUBFRAME_SIZE
 
- TX_DESC_BASE
 
- TX_DESC_BUFLEN_MASK
 
- TX_DESC_BUFLEN_SHIFT
 
- TX_DESC_C
 
- TX_DESC_CIPHER_LENGTH_OFFSET
 
- TX_DESC_CIPHER_TYPE_OFFSET
 
- TX_DESC_CNT
 
- TX_DESC_COUNT
 
- TX_DESC_CSUM_EN
 
- TX_DESC_CSUM_START_MASK
 
- TX_DESC_CSUM_START_SHIFT
 
- TX_DESC_CSUM_STUFF_MASK
 
- TX_DESC_CSUM_STUFF_SHIFT
 
- TX_DESC_DATA0_BUF_LENGTH_MASK_
 
- TX_DESC_DATA0_DTYPE_DATA_
 
- TX_DESC_DATA0_DTYPE_EXT_
 
- TX_DESC_DATA0_DTYPE_MASK_
 
- TX_DESC_DATA0_EXT_
 
- TX_DESC_DATA0_EXT_LSO_
 
- TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_
 
- TX_DESC_DATA0_FCS_
 
- TX_DESC_DATA0_FS_
 
- TX_DESC_DATA0_ICE_
 
- TX_DESC_DATA0_IOC_
 
- TX_DESC_DATA0_IPE_
 
- TX_DESC_DATA0_LS_
 
- TX_DESC_DATA0_TPE_
 
- TX_DESC_DATA0_TSE_
 
- TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_
 
- TX_DESC_DEF
 
- TX_DESC_DEF0
 
- TX_DESC_DEF1
 
- TX_DESC_E
 
- TX_DESC_EOF
 
- TX_DESC_FLAGS_OFFSET
 
- TX_DESC_FLITS
 
- TX_DESC_HOST_LENGTH_OFFSET
 
- TX_DESC_INFO
 
- TX_DESC_INTME
 
- TX_DESC_KEY_INDEX_OFFSET
 
- TX_DESC_LEN_MASK
 
- TX_DESC_MARK
 
- TX_DESC_MAX
 
- TX_DESC_MAX0
 
- TX_DESC_MAX1
 
- TX_DESC_MIN
 
- TX_DESC_MIN0
 
- TX_DESC_MIN1
 
- TX_DESC_NEXT
 
- TX_DESC_NEXT_DESC_OFFSET
 
- TX_DESC_NEXT_OFFSET
 
- TX_DESC_NO_CRC
 
- TX_DESC_NUM
 
- TX_DESC_NUM_8822B
 
- TX_DESC_NUM_92E
 
- TX_DESC_NUM_MASK
 
- TX_DESC_NUM_PTR
 
- TX_DESC_NUM_PTR_SHIFT
 
- TX_DESC_PACKET_TYPE_OFFSET
 
- TX_DESC_PER_IOCB
 
- TX_DESC_PER_OAL
 
- TX_DESC_POS_OFFSET
 
- TX_DESC_QSEL_BEACON
 
- TX_DESC_QSEL_H2C
 
- TX_DESC_QSEL_HIGH
 
- TX_DESC_QSEL_MGMT
 
- TX_DESC_QSEL_TID0
 
- TX_DESC_QSEL_TID1
 
- TX_DESC_QSEL_TID10
 
- TX_DESC_QSEL_TID11
 
- TX_DESC_QSEL_TID12
 
- TX_DESC_QSEL_TID13
 
- TX_DESC_QSEL_TID14
 
- TX_DESC_QSEL_TID15
 
- TX_DESC_QSEL_TID2
 
- TX_DESC_QSEL_TID3
 
- TX_DESC_QSEL_TID4
 
- TX_DESC_QSEL_TID5
 
- TX_DESC_QSEL_TID6
 
- TX_DESC_QSEL_TID7
 
- TX_DESC_QSEL_TID8
 
- TX_DESC_QSEL_TID9
 
- TX_DESC_Q_ADDR_SIZE
 
- TX_DESC_RATE_OFFSET
 
- TX_DESC_RETRY_OFFSET
 
- TX_DESC_RINGN_INDEX
 
- TX_DESC_RINGN_SIZE
 
- TX_DESC_RINGSIZE
 
- TX_DESC_RING_INDEX
 
- TX_DESC_RING_SIZE
 
- TX_DESC_SAD
 
- TX_DESC_SAD_SHIFT
 
- TX_DESC_SIZE
 
- TX_DESC_SIZE_OFFSET
 
- TX_DESC_SIZE_RTL8192S
 
- TX_DESC_SOF
 
- TX_DESC_SOP
 
- TX_DESC_SPACING
 
- TX_DESC_STATUS_OFFSET
 
- TX_DESC_TABLE_SZ
 
- TX_DESC_TR_LEN
 
- TX_DESC_TR_LEN_SHIFT
 
- TX_DESC_TYPE
 
- TX_DEVICE_BUFF_SIZE
 
- TX_DIAG_BGREF_PREDRV_DELAY
 
- TX_DIAG_TX_DRV
 
- TX_DIED
 
- TX_DIG_CTRL_REG_2
 
- TX_DIR
 
- TX_DIS
 
- TX_DISABLED
 
- TX_DISP_RFU0_LANE0__rfu_value0_MASK
 
- TX_DISP_RFU0_LANE0__rfu_value0__SHIFT
 
- TX_DISP_RFU0_LANE1__rfu_value0_MASK
 
- TX_DISP_RFU0_LANE1__rfu_value0__SHIFT
 
- TX_DISP_RFU0_LANE2__rfu_value0_MASK
 
- TX_DISP_RFU0_LANE2__rfu_value0__SHIFT
 
- TX_DISP_RFU0_LANE3__rfu_value0_MASK
 
- TX_DISP_RFU0_LANE3__rfu_value0__SHIFT
 
- TX_DISP_RFU10_LANE0__rfu_value10_MASK
 
- TX_DISP_RFU10_LANE0__rfu_value10__SHIFT
 
- TX_DISP_RFU10_LANE1__rfu_value10_MASK
 
- TX_DISP_RFU10_LANE1__rfu_value10__SHIFT
 
- TX_DISP_RFU10_LANE2__rfu_value10_MASK
 
- TX_DISP_RFU10_LANE2__rfu_value10__SHIFT
 
- TX_DISP_RFU10_LANE3__rfu_value10_MASK
 
- TX_DISP_RFU10_LANE3__rfu_value10__SHIFT
 
- TX_DISP_RFU11_LANE0__rfu_value11_MASK
 
- TX_DISP_RFU11_LANE0__rfu_value11__SHIFT
 
- TX_DISP_RFU11_LANE1__rfu_value11_MASK
 
- TX_DISP_RFU11_LANE1__rfu_value11__SHIFT
 
- TX_DISP_RFU11_LANE2__rfu_value11_MASK
 
- TX_DISP_RFU11_LANE2__rfu_value11__SHIFT
 
- TX_DISP_RFU11_LANE3__rfu_value11_MASK
 
- TX_DISP_RFU11_LANE3__rfu_value11__SHIFT
 
- TX_DISP_RFU12_LANE0__rfu_value12_MASK
 
- TX_DISP_RFU12_LANE0__rfu_value12__SHIFT
 
- TX_DISP_RFU12_LANE1__rfu_value12_MASK
 
- TX_DISP_RFU12_LANE1__rfu_value12__SHIFT
 
- TX_DISP_RFU12_LANE2__rfu_value12_MASK
 
- TX_DISP_RFU12_LANE2__rfu_value12__SHIFT
 
- TX_DISP_RFU12_LANE3__rfu_value12_MASK
 
- TX_DISP_RFU12_LANE3__rfu_value12__SHIFT
 
- TX_DISP_RFU1_LANE0__rfu_value1_MASK
 
- TX_DISP_RFU1_LANE0__rfu_value1__SHIFT
 
- TX_DISP_RFU1_LANE1__rfu_value1_MASK
 
- TX_DISP_RFU1_LANE1__rfu_value1__SHIFT
 
- TX_DISP_RFU1_LANE2__rfu_value1_MASK
 
- TX_DISP_RFU1_LANE2__rfu_value1__SHIFT
 
- TX_DISP_RFU1_LANE3__rfu_value1_MASK
 
- TX_DISP_RFU1_LANE3__rfu_value1__SHIFT
 
- TX_DISP_RFU2_LANE0__rfu_value2_MASK
 
- TX_DISP_RFU2_LANE0__rfu_value2__SHIFT
 
- TX_DISP_RFU2_LANE1__rfu_value2_MASK
 
- TX_DISP_RFU2_LANE1__rfu_value2__SHIFT
 
- TX_DISP_RFU2_LANE2__rfu_value2_MASK
 
- TX_DISP_RFU2_LANE2__rfu_value2__SHIFT
 
- TX_DISP_RFU2_LANE3__rfu_value2_MASK
 
- TX_DISP_RFU2_LANE3__rfu_value2__SHIFT
 
- TX_DISP_RFU3_LANE0__rfu_value3_MASK
 
- TX_DISP_RFU3_LANE0__rfu_value3__SHIFT
 
- TX_DISP_RFU3_LANE1__rfu_value3_MASK
 
- TX_DISP_RFU3_LANE1__rfu_value3__SHIFT
 
- TX_DISP_RFU3_LANE2__rfu_value3_MASK
 
- TX_DISP_RFU3_LANE2__rfu_value3__SHIFT
 
- TX_DISP_RFU3_LANE3__rfu_value3_MASK
 
- TX_DISP_RFU3_LANE3__rfu_value3__SHIFT
 
- TX_DISP_RFU4_LANE0__rfu_value4_MASK
 
- TX_DISP_RFU4_LANE0__rfu_value4__SHIFT
 
- TX_DISP_RFU4_LANE1__rfu_value4_MASK
 
- TX_DISP_RFU4_LANE1__rfu_value4__SHIFT
 
- TX_DISP_RFU4_LANE2__rfu_value4_MASK
 
- TX_DISP_RFU4_LANE2__rfu_value4__SHIFT
 
- TX_DISP_RFU4_LANE3__rfu_value4_MASK
 
- TX_DISP_RFU4_LANE3__rfu_value4__SHIFT
 
- TX_DISP_RFU5_LANE0__rfu_value5_MASK
 
- TX_DISP_RFU5_LANE0__rfu_value5__SHIFT
 
- TX_DISP_RFU5_LANE1__rfu_value5_MASK
 
- TX_DISP_RFU5_LANE1__rfu_value5__SHIFT
 
- TX_DISP_RFU5_LANE2__rfu_value5_MASK
 
- TX_DISP_RFU5_LANE2__rfu_value5__SHIFT
 
- TX_DISP_RFU5_LANE3__rfu_value5_MASK
 
- TX_DISP_RFU5_LANE3__rfu_value5__SHIFT
 
- TX_DISP_RFU6_LANE0__rfu_value6_MASK
 
- TX_DISP_RFU6_LANE0__rfu_value6__SHIFT
 
- TX_DISP_RFU6_LANE1__rfu_value6_MASK
 
- TX_DISP_RFU6_LANE1__rfu_value6__SHIFT
 
- TX_DISP_RFU6_LANE2__rfu_value6_MASK
 
- TX_DISP_RFU6_LANE2__rfu_value6__SHIFT
 
- TX_DISP_RFU6_LANE3__rfu_value6_MASK
 
- TX_DISP_RFU6_LANE3__rfu_value6__SHIFT
 
- TX_DISP_RFU7_LANE0__rfu_value7_MASK
 
- TX_DISP_RFU7_LANE0__rfu_value7__SHIFT
 
- TX_DISP_RFU7_LANE1__rfu_value7_MASK
 
- TX_DISP_RFU7_LANE1__rfu_value7__SHIFT
 
- TX_DISP_RFU7_LANE2__rfu_value7_MASK
 
- TX_DISP_RFU7_LANE2__rfu_value7__SHIFT
 
- TX_DISP_RFU7_LANE3__rfu_value7_MASK
 
- TX_DISP_RFU7_LANE3__rfu_value7__SHIFT
 
- TX_DISP_RFU8_LANE0__rfu_value8_MASK
 
- TX_DISP_RFU8_LANE0__rfu_value8__SHIFT
 
- TX_DISP_RFU8_LANE1__rfu_value8_MASK
 
- TX_DISP_RFU8_LANE1__rfu_value8__SHIFT
 
- TX_DISP_RFU8_LANE2__rfu_value8_MASK
 
- TX_DISP_RFU8_LANE2__rfu_value8__SHIFT
 
- TX_DISP_RFU8_LANE3__rfu_value8_MASK
 
- TX_DISP_RFU8_LANE3__rfu_value8__SHIFT
 
- TX_DISP_RFU9_LANE0__rfu_value9_MASK
 
- TX_DISP_RFU9_LANE0__rfu_value9__SHIFT
 
- TX_DISP_RFU9_LANE1__rfu_value9_MASK
 
- TX_DISP_RFU9_LANE1__rfu_value9__SHIFT
 
- TX_DISP_RFU9_LANE2__rfu_value9_MASK
 
- TX_DISP_RFU9_LANE2__rfu_value9__SHIFT
 
- TX_DISP_RFU9_LANE3__rfu_value9_MASK
 
- TX_DISP_RFU9_LANE3__rfu_value9__SHIFT
 
- TX_DLE_PSI
 
- TX_DMA1_SM_MASK
 
- TX_DMA2_SM_MASK
 
- TX_DMAREQEN
 
- TX_DMA_ADDR
 
- TX_DMA_BUF
 
- TX_DMA_BURST
 
- TX_DMA_CHKSUM
 
- TX_DMA_DESP2_DEF
 
- TX_DMA_DONE
 
- TX_DMA_DRAIN_RETRIES
 
- TX_DMA_DST_CSR
 
- TX_DMA_DST_CSR_DEST_AC0
 
- TX_DMA_DST_CSR_DEST_AC1
 
- TX_DMA_DST_CSR_DEST_AC2
 
- TX_DMA_DST_CSR_DEST_AC3
 
- TX_DMA_DST_CSR_DEST_MGMT
 
- TX_DMA_EN
 
- TX_DMA_ENABLE
 
- TX_DMA_ERR
 
- TX_DMA_ERROR
 
- TX_DMA_FPORT_MASK
 
- TX_DMA_FPORT_SHIFT
 
- TX_DMA_GRANT
 
- TX_DMA_IDLE
 
- TX_DMA_INS_VLAN
 
- TX_DMA_INTR
 
- TX_DMA_LEN
 
- TX_DMA_LS0
 
- TX_DMA_LS1
 
- TX_DMA_OWNER_CPU
 
- TX_DMA_PAUSE
 
- TX_DMA_PLEN0
 
- TX_DMA_PLEN1
 
- TX_DMA_PRE_ST
 
- TX_DMA_PRE_ST_SHADOW_HD
 
- TX_DMA_REQUEST
 
- TX_DMA_RUNNING
 
- TX_DMA_SDL
 
- TX_DMA_STATUS_DU
 
- TX_DMA_SWC
 
- TX_DMA_TRIG_EN
 
- TX_DMA_TSO
 
- TX_DONE
 
- TX_DONE_MASK
 
- TX_DONE_SHIFT
 
- TX_DOT11_MGMT
 
- TX_DP_STOR
 
- TX_DP_STORE_TOT_TXUSED_MASK_
 
- TX_DP_STORE_URX_TXUSED_MASK_
 
- TX_DRIVER_POLARITY
 
- TX_DROP
 
- TX_DROP_FRAME_COUNTER
 
- TX_DRTH_VAL_INC
 
- TX_DRTH_VAL_LIMIT
 
- TX_DRTH_VAL_START
 
- TX_DRV_LVL
 
- TX_DRV_LVL_MUX
 
- TX_DS
 
- TX_DSI_DATA_TYPE_NOT_RECOGNIZED
 
- TX_DSI_VC_ID_INVALID
 
- TX_DS_TAGL_BIT
 
- TX_DTX_IDX
 
- TX_DTX_IDX0
 
- TX_DTX_IDX1
 
- TX_DTX_IDX2
 
- TX_DTX_IDX3
 
- TX_DTX_IDX4
 
- TX_DTX_IDX5
 
- TX_DVDD_BIT_1_0625V
 
- TX_DV_GATE_EN0
 
- TX_DYN_WM_ENA
 
- TX_EARLY
 
- TX_EARLY_COLLISIONS
 
- TX_EARLY_THRESH
 
- TX_ECC_MULTI_BIT_ERROR
 
- TX_ECC_SINGLE_BIT_ERROR
 
- TX_ECHO_SKB_MAX
 
- TX_EMPTY
 
- TX_EMPTY_STATUS
 
- TX_EMP_POST1_LVL
 
- TX_EMP_POST1_LVL_MUX
 
- TX_EN
 
- TX_ENABLE
 
- TX_ENABLE_BIT
 
- TX_ENABLE_INTERRUPT
 
- TX_ENABLE_MASK
 
- TX_ENCRYPT_FAIL
 
- TX_END
 
- TX_ENP
 
- TX_ENTRY_LPI_MODE
 
- TX_ENT_MSK
 
- TX_ENT_MSK_CONF_PART_ERR
 
- TX_ENT_MSK_MBOX_ERR
 
- TX_ENT_MSK_MK
 
- TX_ENT_MSK_NACK_PKT_RD
 
- TX_ENT_MSK_NACK_PREF
 
- TX_ENT_MSK_PKT_PRT_ERR
 
- TX_ENT_MSK_PKT_SIZE_ERR
 
- TX_ENT_MSK_PREF_BUF_ECC_ERR
 
- TX_ENT_MSK_TX_RING_OFLOW
 
- TX_EN_INT
 
- TX_EOT
 
- TX_EPQ_BASE
 
- TX_EQ_MASK
 
- TX_EQ_SETTINGS
 
- TX_EQ_SHIFT
 
- TX_EQ_SMASK
 
- TX_ERROR
 
- TX_ERRORS_CSL
 
- TX_ERRORS_DEF
 
- TX_ERRORS_EXDEF
 
- TX_ERRORS_LC
 
- TX_ERRORS_RC_MASK
 
- TX_ERRORS_RC_SHIFT
 
- TX_ERRORS_RL
 
- TX_ERRORS_UN
 
- TX_ERROR_CODE
 
- TX_ERROR_PERIOD
 
- TX_ERR_DET
 
- TX_ER_NAK
 
- TX_ER_STALL
 
- TX_ER_TIMEOUT
 
- TX_ER_UNDERUN
 
- TX_ESC_CLK_DIVISION
 
- TX_ETHER_PKT
 
- TX_EVENT
 
- TX_EVENT_MM_MASK
 
- TX_EVENT_MM_SHIFT
 
- TX_EXCEEDC
 
- TX_EXCESSIVE_COLLISION_PACKET_COUNTER
 
- TX_EXCESSIVE_DEFERRAL_PACKET_COUNTER
 
- TX_EXC_COLL
 
- TX_EXC_DEF
 
- TX_EXIT_LPI_MODE
 
- TX_EXPIRED
 
- TX_EXTRA_DELAY_ENABLE
 
- TX_EXTRA_DELAY_MASK
 
- TX_E_BW_UPDATE
 
- TX_E_CLEANUP_DONE
 
- TX_E_FAIL
 
- TX_E_START
 
- TX_E_STARTED
 
- TX_E_STOP
 
- TX_E_STOPPED
 
- TX_FALSE_CONTROL_ERROR
 
- TX_FAST_ELT
 
- TX_FAST_SPND
 
- TX_FBK_CFG_3S_0
 
- TX_FBK_CFG_3S_1
 
- TX_FCM_DRV_MAIN_EN
 
- TX_FCM_FULL_MARGIN
 
- TX_FCS_ERROR_COUNTER
 
- TX_FD_NUM
 
- TX_FIFO
 
- TX_FIFOADDR
 
- TX_FIFOEMPTY
 
- TX_FIFOFULL
 
- TX_FIFOSEGSIZE
 
- TX_FIFO_ALL_EMPTY
 
- TX_FIFO_ALMOST_EMPTY_INTR
 
- TX_FIFO_ALMOST_FULL_INTR
 
- TX_FIFO_BUFF_NO_SNOOP
 
- TX_FIFO_DEPTH
 
- TX_FIFO_DEPTH_MSK
 
- TX_FIFO_DEPTH_SHFT
 
- TX_FIFO_DS_NO_SNOOP
 
- TX_FIFO_EMPTY
 
- TX_FIFO_EMPTY_COUNT_MAX
 
- TX_FIFO_EMPTY_INTR
 
- TX_FIFO_ENABLE
 
- TX_FIFO_ENABLE_MASK
 
- TX_FIFO_FIRSTNLAST_LIST
 
- TX_FIFO_FIRST_LIST
 
- TX_FIFO_FULL
 
- TX_FIFO_FULL_INTR
 
- TX_FIFO_HALF_EMPTY
 
- TX_FIFO_HC
 
- TX_FIFO_INF
 
- TX_FIFO_INF_FREE_
 
- TX_FIFO_INF_TDFREE_
 
- TX_FIFO_INF_TSUSED_
 
- TX_FIFO_INTERNAL_MAX_NUM
 
- TX_FIFO_INTS
 
- TX_FIFO_LAST_LIST
 
- TX_FIFO_LAST_TXD_NUM
 
- TX_FIFO_LC
 
- TX_FIFO_LOW_THRESHOLD
 
- TX_FIFO_LVL
 
- TX_FIFO_MAX_NUM
 
- TX_FIFO_MAX_NUM_9000
 
- TX_FIFO_NOT_FULL
 
- TX_FIFO_NUMBER_MSK
 
- TX_FIFO_OVERFLOW
 
- TX_FIFO_PARTITION_0_LEN
 
- TX_FIFO_PARTITION_0_PRI
 
- TX_FIFO_PARTITION_1_LEN
 
- TX_FIFO_PARTITION_1_PRI
 
- TX_FIFO_PARTITION_2_LEN
 
- TX_FIFO_PARTITION_2_PRI
 
- TX_FIFO_PARTITION_3_LEN
 
- TX_FIFO_PARTITION_3_PRI
 
- TX_FIFO_PARTITION_4_LEN
 
- TX_FIFO_PARTITION_4_PRI
 
- TX_FIFO_PARTITION_5_LEN
 
- TX_FIFO_PARTITION_5_PRI
 
- TX_FIFO_PARTITION_6_LEN
 
- TX_FIFO_PARTITION_6_PRI
 
- TX_FIFO_PARTITION_7_LEN
 
- TX_FIFO_PARTITION_7_PRI
 
- TX_FIFO_PARTITION_EN
 
- TX_FIFO_PARTITION_PRI_0
 
- TX_FIFO_PARTITION_PRI_1
 
- TX_FIFO_PARTITION_PRI_2
 
- TX_FIFO_PARTITION_PRI_3
 
- TX_FIFO_PARTITION_PRI_4
 
- TX_FIFO_PARTITION_PRI_5
 
- TX_FIFO_PARTITION_PRI_6
 
- TX_FIFO_PARTITION_PRI_7
 
- TX_FIFO_PRI_0
 
- TX_FIFO_PRI_1
 
- TX_FIFO_PRI_2
 
- TX_FIFO_PRI_3
 
- TX_FIFO_PRI_4
 
- TX_FIFO_PRI_5
 
- TX_FIFO_PRI_6
 
- TX_FIFO_PRI_7
 
- TX_FIFO_RESET_BIT
 
- TX_FIFO_RST
 
- TX_FIFO_RST_MASK
 
- TX_FIFO_SC
 
- TX_FIFO_SECTIONS_TX_AVAIL_10G
 
- TX_FIFO_SECTIONS_TX_AVAIL_1G
 
- TX_FIFO_SECTIONS_TX_AVAIL_MASK
 
- TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G
 
- TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G
 
- TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G
 
- TX_FIFO_SECTIONS_TX_EMPTY_MASK
 
- TX_FIFO_SIZE
 
- TX_FIFO_SIZE_REG
 
- TX_FIFO_SPACE
 
- TX_FIFO_SPECIAL_FUNC
 
- TX_FIFO_SYNC_HI
 
- TX_FIFO_THRESH
 
- TX_FIFO_UNDER
 
- TX_FIFO_UNDERRUN
 
- TX_FIFO_UNDR
 
- TX_FIFO_URGENT_THRESHOLD
 
- TX_FIFO_WC
 
- TX_FIFO_WIDTH_MSK
 
- TX_FIFO_WIDTH_SHFT
 
- TX_FIFO_WORDS_REG
 
- TX_FILL_THRESH
 
- TX_FINISH
 
- TX_FINISH_CACHE_INV
 
- TX_FIRM_OWN
 
- TX_FIRST_DEFERRAL
 
- TX_FIRST_DESC
 
- TX_FIX_VALUE_MASK
 
- TX_FIX_VALUE_MASK_SFT
 
- TX_FIX_VALUE_SFT
 
- TX_FLAG_BITS
 
- TX_FLOW_EN
 
- TX_FLOW_ON_BIT
 
- TX_FLTH_VAL
 
- TX_FLUSH
 
- TX_FLUSH_CNTL
 
- TX_FORCE
 
- TX_FORCE_S
 
- TX_FORCE_V
 
- TX_FRAGMENT_FRAME_COUNTER
 
- TX_FRAME
 
- TX_FRAME_ABORTED
 
- TX_FRAME_CAPPED
 
- TX_FRAME_FLAG_IN_PROGRESS
 
- TX_FRAME_NOTCAP
 
- TX_FRAME_PORT
 
- TX_FRAME_TYPE
 
- TX_FREE
 
- TX_FREE_BUFFER_COUNT_OFF
 
- TX_FREE_DESC_CNT
 
- TX_FREE_MEM
 
- TX_FS
 
- TX_FSM_HIBERN8
 
- TX_FSYNC_ERR_INT
 
- TX_FSYNC_INT
 
- TX_FSYNC_MASK
 
- TX_GAIN_TABLE_LENGTH
 
- TX_GAP
 
- TX_GEN_CRC
 
- TX_GET_DMA_BUFFER
 
- TX_GLOBALHIBERNATE
 
- TX_GMF_AE_THR
 
- TX_GMF_CTRL_T
 
- TX_GMF_EA
 
- TX_GMF_RLEV
 
- TX_GMF_RP
 
- TX_GMF_RSTP
 
- TX_GMF_WLEV
 
- TX_GMF_WP
 
- TX_GMF_WSP
 
- TX_GUARD_BAND
 
- TX_HALF_FULL_DET
 
- TX_HALF_FULL_MASK
 
- TX_HARDRST_MSK
 
- TX_HARDRST_OFF
 
- TX_HDR_LEN
 
- TX_HDR_PORT_0
 
- TX_HDR_PORT_1
 
- TX_HDR_SENT
 
- TX_HDR_WRB_COMPL
 
- TX_HDR_WRB_EVT
 
- TX_HDR_WRB_NUM_MASK
 
- TX_HDR_WRB_NUM_SHIFT
 
- TX_HEAD
 
- TX_HEADER_0
 
- TX_HEADER_1
 
- TX_HEADER_LEN
 
- TX_HEADER_LENGTH
 
- TX_HEADROOM
 
- TX_HEAD_WRITEBACK_ADDRH
 
- TX_HEAD_WRITEBACK_ADDRL
 
- TX_HIBERN8TIME_CAPABILITY
 
- TX_HIBERN8_CONTROL
 
- TX_HIGHPWR_LEVEL_NORMAL
 
- TX_HIGHPWR_LEVEL_NORMAL1
 
- TX_HIGHPWR_LEVEL_NORMAL2
 
- TX_HIGH_PWR_LEVEL_LEVEL1
 
- TX_HIGH_PWR_LEVEL_LEVEL2
 
- TX_HIGH_PWR_LEVEL_NORMAL
 
- TX_HIGH_Z
 
- TX_HIGH_Z_TM_EN
 
- TX_HIQ_BASE
 
- TX_HOST_COMMAND_TYPE
 
- TX_HPF_CUT_OFF_FREQ_MASK
 
- TX_HSGEAR
 
- TX_HSRATE_SERIES
 
- TX_HS_PREPARE_LENGTH
 
- TX_HS_SLEWRATE
 
- TX_HS_SYNC_LENGTH
 
- TX_HS_UNTERMINATED_LINE_DRIVE_ENABLE
 
- TX_HW_AP_MODE_PKT_LIFETIME_TU
 
- TX_HW_ATTR_EAPOL_FRAME
 
- TX_HW_ATTR_HEADER_PAD
 
- TX_HW_ATTR_HOST_ENCRYPT
 
- TX_HW_ATTR_LAST_WORD_PAD
 
- TX_HW_ATTR_OFST_HEADER_PAD
 
- TX_HW_ATTR_OFST_LAST_WORD_PAD
 
- TX_HW_ATTR_OFST_RATE_POLICY
 
- TX_HW_ATTR_OFST_SAVE_RETRIES
 
- TX_HW_ATTR_OFST_SESSION_COUNTER
 
- TX_HW_ATTR_OFST_TX_CMPLT_REQ
 
- TX_HW_ATTR_RATE_POLICY
 
- TX_HW_ATTR_SAVE_RETRIES
 
- TX_HW_ATTR_SESSION_COUNTER
 
- TX_HW_ATTR_TX_CMPLT_REQ
 
- TX_HW_ATTR_TX_DUMMY_REQ
 
- TX_HW_ERROR
 
- TX_HW_FLOW_CTL_EN
 
- TX_HW_MGMT_PKT_LIFETIME_TU
 
- TX_HW_RESULT_QUEUE_LEN
 
- TX_HW_RESULT_QUEUE_LEN_MASK
 
- TX_I2S_CTL_TX_I2S_FS_RATE_F_16_KHZ
 
- TX_I2S_CTL_TX_I2S_FS_RATE_F_192_KHZ
 
- TX_I2S_CTL_TX_I2S_FS_RATE_F_32_KHZ
 
- TX_I2S_CTL_TX_I2S_FS_RATE_F_48_KHZ
 
- TX_I2S_CTL_TX_I2S_FS_RATE_F_8_KHZ
 
- TX_I2S_CTL_TX_I2S_FS_RATE_F_96_KHZ
 
- TX_I2S_CTL_TX_I2S_FS_RATE_MASK
 
- TX_I2S_CTL_TX_I2S_MODE_16
 
- TX_I2S_CTL_TX_I2S_MODE_32
 
- TX_I2S_CTL_TX_I2S_MODE_MASK
 
- TX_IDENT_MASK
 
- TX_IDENT_SHIFT
 
- TX_IDLE
 
- TX_IDLE_JAM_SEQ_TEST
 
- TX_IDX
 
- TX_ID_DWORD0
 
- TX_ID_DWORD1
 
- TX_ID_DWORD2
 
- TX_ID_DWORD3
 
- TX_ID_DWORD4
 
- TX_ID_DWORD5
 
- TX_ID_DWORD6
 
- TX_IHL_SHIFT
 
- TX_INDX_FIFO_SYNC_RST
 
- TX_INFO_RPTR
 
- TX_INFO_WPTR
 
- TX_INIT
 
- TX_INT
 
- TX_INTERRUPTABLE
 
- TX_INTR
 
- TX_INTR_COAL
 
- TX_INTS
 
- TX_INT_PATTERN
 
- TX_IN_BURST_PERIOD
 
- TX_IN_GAP_PERIOD
 
- TX_IN_PROGRESS
 
- TX_IN_PROGRESS_BIT
 
- TX_IPG_JAM_DATA
 
- TX_IPG_JAM_DEF
 
- TX_IPSEC
 
- TX_IPSEC_CMD
 
- TX_IPV4_EN
 
- TX_IPV6_EN
 
- TX_IP_CKSUM
 
- TX_IP_OFFSET_ENTRY_MAX
 
- TX_IP_PKT
 
- TX_IQ_CAL
 
- TX_IQ_ON_AGC_CAL
 
- TX_IRQ_NO_COALESC
 
- TX_IRQ_NO_CREDIT
 
- TX_IRQ_NO_LLI_TIMER
 
- TX_IRQ_NO_PENDING
 
- TX_IRQ_NO_RESEND_TIMER
 
- TX_IRQ_REG
 
- TX_ISOCHRONOUS
 
- TX_ISOC_COMM_CHANNEL_MASK
 
- TX_ISOC_COMM_CHANNEL_SHIFT
 
- TX_ISOC_COMM_IS_ACTIVATED
 
- TX_JABBER
 
- TX_JABBER_FRAME_COUNTER
 
- TX_JAB_TIMEOUT
 
- TX_JAM_IPG_DEF
 
- TX_JAM_IPG_VAL
 
- TX_JAM_LEN_DEF
 
- TX_JAM_LEN_VAL
 
- TX_JBR
 
- TX_JBR_ENBL
 
- TX_JUMBO_TASK_TH_MASK
 
- TX_JUMBO_TASK_TH_SHIFT
 
- TX_KEY_NOT_FOUND
 
- TX_L2_EN
 
- TX_L3_CHECKSUM
 
- TX_LARGE_FIFO
 
- TX_LAST_DESC
 
- TX_LATEC
 
- TX_LATE_COL
 
- TX_LATE_COLL
 
- TX_LATE_COLLISION
 
- TX_LATE_COLLISION_PACKET_COUNTER
 
- TX_LATE_COLL_ABORT
 
- TX_LATE_COL_ENBL
 
- TX_LCC_ENABLE
 
- TX_LCC_SEQUENCER
 
- TX_LED_CTRL
 
- TX_LED_INI
 
- TX_LED_TST
 
- TX_LED_VAL
 
- TX_LEN
 
- TX_LENGTHS_CNT_DWN_VAL_MSK
 
- TX_LENGTHS_IPG_CRS_MASK
 
- TX_LENGTHS_IPG_CRS_SHIFT
 
- TX_LENGTHS_IPG_MASK
 
- TX_LENGTHS_IPG_SHIFT
 
- TX_LENGTHS_JMB_FRM_LEN_MSK
 
- TX_LENGTHS_SLOT_TIME_MASK
 
- TX_LENGTHS_SLOT_TIME_SHIFT
 
- TX_LEN_MAX
 
- TX_LEN_PORT
 
- TX_LEN_SHIFT
 
- TX_LEVEL
 
- TX_LINE_INVALID_COUNT_REG
 
- TX_LINE_VALID_COUNT_REG
 
- TX_LINK_CFG
 
- TX_LINK_CFG_MFB_ENABLE
 
- TX_LINK_CFG_REMOTE_MFB
 
- TX_LINK_CFG_REMOTE_MFB_LIFETIME
 
- TX_LINK_CFG_REMOTE_MFS
 
- TX_LINK_CFG_REMOTE_UMFS_ENABLE
 
- TX_LINK_CFG_TX_CF_ACK_EN
 
- TX_LINK_CFG_TX_MRQ_EN
 
- TX_LINK_CFG_TX_RDG_EN
 
- TX_LINK_NOT_VALID
 
- TX_LNA_GAIN
 
- TX_LOG_LEN
 
- TX_LOG_MASK1
 
- TX_LOG_MASK1_MASK
 
- TX_LOG_MASK2
 
- TX_LOG_MASK2_MASK
 
- TX_LOG_PAGE_HDL
 
- TX_LOG_PAGE_HDL_HANDLE
 
- TX_LOG_PAGE_RELO1
 
- TX_LOG_PAGE_RELO1_RELO
 
- TX_LOG_PAGE_RELO2
 
- TX_LOG_PAGE_RELO2_RELO
 
- TX_LOG_PAGE_VLD
 
- TX_LOG_PAGE_VLD_FUNC
 
- TX_LOG_PAGE_VLD_FUNC_SHIFT
 
- TX_LOG_PAGE_VLD_PAGE0
 
- TX_LOG_PAGE_VLD_PAGE1
 
- TX_LOG_RING_SIZE
 
- TX_LOG_VAL1
 
- TX_LOG_VAL1_VALUE
 
- TX_LOG_VAL2
 
- TX_LOG_VAL2_VALUE
 
- TX_LOOP_BACK
 
- TX_LOQ_BASE
 
- TX_LOSS_CARRIER
 
- TX_LOST_CRS
 
- TX_LOST_CRS_ENBL
 
- TX_LOW_WATER
 
- TX_LOW_WATERMARK
 
- TX_LS
 
- TX_LS_PREPARE_LENGTH
 
- TX_LS_TERMINATED_LINE_DRIVE_ENABLE
 
- TX_MAC_INTR
 
- TX_MAP_PAGE
 
- TX_MAP_SINGLE
 
- TX_MARGINING
 
- TX_MARGINING_MUX
 
- TX_MAT_SET
 
- TX_MAX_BURST
 
- TX_MAX_CNT
 
- TX_MAX_CNT0
 
- TX_MAX_CNT1
 
- TX_MAX_CNT2
 
- TX_MAX_CNT3
 
- TX_MAX_CNT4
 
- TX_MAX_CNT5
 
- TX_MAX_COUNT
 
- TX_MAX_FRAGS
 
- TX_MAX_NUM_DPE
 
- TX_MAX_PENDING
 
- TX_MAX_PKT
 
- TX_MAX_PKT_G2
 
- TX_MAX_PKT_OG
 
- TX_MAX_RINGS
 
- TX_MAX_RING_SIZE
 
- TX_MAX_SEND_CNT
 
- TX_MAX_TSS_RINGS
 
- TX_MCAST
 
- TX_MCAST_PKTS
 
- TX_MCOL_MASK
 
- TX_MCOL_SHIFT_BIT
 
- TX_MCS_MAP
 
- TX_MEDIUM_FIFO
 
- TX_MEM_TEST_FAILED
 
- TX_MEM_TEST_FINISHED
 
- TX_MFF_CTRL1
 
- TX_MFF_CTRL2
 
- TX_MFF_EA
 
- TX_MFF_LEV
 
- TX_MFF_PC
 
- TX_MFF_RP
 
- TX_MFF_TST1
 
- TX_MFF_TST2
 
- TX_MFF_WAF
 
- TX_MFF_WP
 
- TX_MFF_WSP
 
- TX_MIN_ACTIVATETIME
 
- TX_MIN_PENDING
 
- TX_MIQ_BASE
 
- TX_MODE
 
- TX_MODE_BIG_BCKOFF_ENABLE
 
- TX_MODE_CNT_DN_MODE
 
- TX_MODE_CTRL_DTS_MASK
 
- TX_MODE_ENABLE
 
- TX_MODE_FIRST_IN_BURST
 
- TX_MODE_FLOW_CTRL_ENABLE
 
- TX_MODE_IN_BURST_SEQ
 
- TX_MODE_JMB_FRM_LEN
 
- TX_MODE_LONG_PAUSE_ENABLE
 
- TX_MODE_MBUF_LOCKUP_FIX
 
- TX_MODE_MSK
 
- TX_MODE_NO_BURST
 
- TX_MODE_RESET
 
- TX_MODQ_WEIGHT0_S
 
- TX_MODQ_WEIGHT0_V
 
- TX_MODQ_WEIGHT1_S
 
- TX_MODQ_WEIGHT1_V
 
- TX_MODQ_WEIGHT2_S
 
- TX_MODQ_WEIGHT2_V
 
- TX_MODQ_WEIGHT3_S
 
- TX_MODQ_WEIGHT3_V
 
- TX_MOD_QUEUE_REQ_MAP_S
 
- TX_MOD_QUEUE_REQ_MAP_V
 
- TX_MSDU_LIFETIME_DEF
 
- TX_MSDU_LIFETIME_MAX
 
- TX_MSDU_LIFETIME_MIN
 
- TX_MSP_TDR_TSR
 
- TX_MSS_MIN
 
- TX_MULT
 
- TX_MULTICAST_PACKET_COUNTER
 
- TX_MULTIQ_STEERING
 
- TX_MULTI_COLLISION_PACKET_COUNTER
 
- TX_MULT_G2
 
- TX_MULT_OG
 
- TX_MUX_CTL_CF_NEG_3DB_150HZ
 
- TX_MUX_CTL_CF_NEG_3DB_4HZ
 
- TX_MUX_CTL_CF_NEG_3DB_75HZ
 
- TX_MUX_CTL_CUT_OFF_FREQ_MASK
 
- TX_MUX_CTL_CUT_OFF_FREQ_SHIFT
 
- TX_MUX_CTL_HPF_BP_SEL_BYPASS
 
- TX_MUX_CTL_HPF_BP_SEL_MASK
 
- TX_MUX_CTL_HPF_BP_SEL_NO_BYPASS
 
- TX_NAMES
 
- TX_NAMES_SIZE
 
- TX_NARROW_BW_1DIV2
 
- TX_NARROW_BW_1DIV4
 
- TX_NARROW_BW_1DIV8
 
- TX_NARROW_BW_MSK
 
- TX_NEXT
 
- TX_NICBUF_SIZE_BUG
 
- TX_NOBUFF
 
- TX_NORMAL_DESC2_HL_B1L_INDEX
 
- TX_NORMAL_DESC2_HL_B1L_LEN
 
- TX_NORMAL_DESC2_HL_B1L_POS
 
- TX_NORMAL_DESC2_HL_B1L_WIDTH
 
- TX_NORMAL_DESC2_IC_INDEX
 
- TX_NORMAL_DESC2_IC_LEN
 
- TX_NORMAL_DESC2_IC_POS
 
- TX_NORMAL_DESC2_IC_WIDTH
 
- TX_NORMAL_DESC2_TTSE_INDEX
 
- TX_NORMAL_DESC2_TTSE_LEN
 
- TX_NORMAL_DESC2_TTSE_POS
 
- TX_NORMAL_DESC2_TTSE_WIDTH
 
- TX_NORMAL_DESC2_VLAN_INSERT
 
- TX_NORMAL_DESC2_VTIR_INDEX
 
- TX_NORMAL_DESC2_VTIR_LEN
 
- TX_NORMAL_DESC2_VTIR_POS
 
- TX_NORMAL_DESC2_VTIR_WIDTH
 
- TX_NORMAL_DESC3_CIC_INDEX
 
- TX_NORMAL_DESC3_CIC_LEN
 
- TX_NORMAL_DESC3_CIC_POS
 
- TX_NORMAL_DESC3_CIC_WIDTH
 
- TX_NORMAL_DESC3_CPC_INDEX
 
- TX_NORMAL_DESC3_CPC_LEN
 
- TX_NORMAL_DESC3_CPC_POS
 
- TX_NORMAL_DESC3_CPC_WIDTH
 
- TX_NORMAL_DESC3_CTXT_INDEX
 
- TX_NORMAL_DESC3_CTXT_LEN
 
- TX_NORMAL_DESC3_CTXT_POS
 
- TX_NORMAL_DESC3_CTXT_WIDTH
 
- TX_NORMAL_DESC3_FD_INDEX
 
- TX_NORMAL_DESC3_FD_LEN
 
- TX_NORMAL_DESC3_FD_POS
 
- TX_NORMAL_DESC3_FD_WIDTH
 
- TX_NORMAL_DESC3_FL_INDEX
 
- TX_NORMAL_DESC3_FL_LEN
 
- TX_NORMAL_DESC3_FL_POS
 
- TX_NORMAL_DESC3_FL_WIDTH
 
- TX_NORMAL_DESC3_LD_INDEX
 
- TX_NORMAL_DESC3_LD_LEN
 
- TX_NORMAL_DESC3_LD_POS
 
- TX_NORMAL_DESC3_LD_WIDTH
 
- TX_NORMAL_DESC3_OWN_INDEX
 
- TX_NORMAL_DESC3_OWN_LEN
 
- TX_NORMAL_DESC3_OWN_POS
 
- TX_NORMAL_DESC3_OWN_WIDTH
 
- TX_NORMAL_DESC3_TCPHDRLEN_INDEX
 
- TX_NORMAL_DESC3_TCPHDRLEN_LEN
 
- TX_NORMAL_DESC3_TCPHDRLEN_POS
 
- TX_NORMAL_DESC3_TCPHDRLEN_WIDTH
 
- TX_NORMAL_DESC3_TCPPL_INDEX
 
- TX_NORMAL_DESC3_TCPPL_LEN
 
- TX_NORMAL_DESC3_TCPPL_POS
 
- TX_NORMAL_DESC3_TCPPL_WIDTH
 
- TX_NORMAL_DESC3_TSE_INDEX
 
- TX_NORMAL_DESC3_TSE_LEN
 
- TX_NORMAL_DESC3_TSE_POS
 
- TX_NORMAL_DESC3_TSE_WIDTH
 
- TX_NORMAL_DESC3_VNP_INDEX
 
- TX_NORMAL_DESC3_VNP_WIDTH
 
- TX_NORMAL_DESC3_VXLAN_PACKET
 
- TX_NORMAL_OPERATION
 
- TX_NOTIFY_DELAYED_GENERALERROR
 
- TX_NOTIFY_DELAYED_OK
 
- TX_NOTIFY_DELAYED_UNREACHABLE
 
- TX_NOTIFY_GENERALERROR
 
- TX_NOTIFY_OK
 
- TX_NOTIFY_PENDING
 
- TX_NOTIFY_TPQFULL
 
- TX_NOTIFY_UNREACHABLE
 
- TX_NOT_ALMOST_EMPTY_BIT
 
- TX_NOT_ALMOST_FULL_BIT
 
- TX_NOT_EMPTY_BIT
 
- TX_NOT_FULL_BIT
 
- TX_NOW
 
- TX_NO_BUFFER
 
- TX_NO_CARRIER
 
- TX_NO_CRC
 
- TX_NO_DEV
 
- TX_NO_EQ_MASK
 
- TX_NO_EQ_SHIFT
 
- TX_NO_EQ_SMASK
 
- TX_NO_ERROR
 
- TX_NO_OP
 
- TX_NO_SPC
 
- TX_NUMBER
 
- TX_NUMBER_AUDIO
 
- TX_NUMBER_MIDI
 
- TX_NUM_FIFO
 
- TX_NXTDESC_PTR
 
- TX_OCTS
 
- TX_OFF
 
- TX_OFFLOAD_CSUM
 
- TX_OFFLOAD_INVALID
 
- TX_OFFLOAD_TSO
 
- TX_OFFLOAD_VLAN
 
- TX_OFFSET_3
 
- TX_OK
 
- TX_OK_ENBL
 
- TX_ON
 
- TX_ONE_COL
 
- TX_OUT_AMP
 
- TX_OVERFLOW_DET
 
- TX_OVERFLOW_MASK
 
- TX_OVERHEAD
 
- TX_OVERRUN_BIT
 
- TX_OVERSIZE_FRAME_COUNTER
 
- TX_OVERSIZE_PKT
 
- TX_P0
 
- TX_P1
 
- TX_P2
 
- TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX
 
- TX_PACKET_ATTRIBUTES_CSUM_ENABLE_LEN
 
- TX_PACKET_ATTRIBUTES_CSUM_ENABLE_POS
 
- TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH
 
- TX_PACKET_ATTRIBUTES_PTP_INDEX
 
- TX_PACKET_ATTRIBUTES_PTP_LEN
 
- TX_PACKET_ATTRIBUTES_PTP_POS
 
- TX_PACKET_ATTRIBUTES_PTP_WIDTH
 
- TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX
 
- TX_PACKET_ATTRIBUTES_TSO_ENABLE_LEN
 
- TX_PACKET_ATTRIBUTES_TSO_ENABLE_POS
 
- TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH
 
- TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX
 
- TX_PACKET_ATTRIBUTES_VLAN_CTAG_LEN
 
- TX_PACKET_ATTRIBUTES_VLAN_CTAG_POS
 
- TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH
 
- TX_PACKET_ATTRIBUTES_VXLAN_INDEX
 
- TX_PACKET_ATTRIBUTES_VXLAN_WIDTH
 
- TX_PACKET_COUNTER
 
- TX_PACKET_DROPPED
 
- TX_PACKET_EXCLUDE_DIFFERED_DATA_CHUNKS
 
- TX_PACKET_MODE_BURST_FIRST
 
- TX_PACKET_MODE_BURST_SEQ
 
- TX_PACKET_MODE_MSK
 
- TX_PACKET_MODE_REGULAR
 
- TX_PACKET_RAM
 
- TX_PACKET_SEQ_TEST
 
- TX_PACKET_SHIFT_BYTES
 
- TX_PACKET_TRANSMISSION_SPEED_MASK
 
- TX_PACKET_TYPE_DATA
 
- TX_PACKET_TYPE_MGMT
 
- TX_PAD_EN
 
- TX_PAGES
 
- TX_PAGE_BOUNDARY
 
- TX_PAGE_BOUNDARY_8723B
 
- TX_PAGE_BOUNDARY_88E
 
- TX_PAGE_NUM_HI_PQ
 
- TX_PAGE_NUM_HI_PQ_8192E
 
- TX_PAGE_NUM_HI_PQ_8723B
 
- TX_PAGE_NUM_LO_PQ
 
- TX_PAGE_NUM_LO_PQ_8192E
 
- TX_PAGE_NUM_LO_PQ_8723B
 
- TX_PAGE_NUM_NORM_PQ
 
- TX_PAGE_NUM_NORM_PQ_8192E
 
- TX_PAGE_NUM_NORM_PQ_8723B
 
- TX_PAGE_NUM_PUBQ
 
- TX_PAGE_NUM_PUBQ_8192E
 
- TX_PAGE_NUM_PUBQ_8723B
 
- TX_PAGE_SIZE_SHIFT
 
- TX_PARITY_BIT
 
- TX_PATTERN
 
- TX_PAUSE
 
- TX_PAUSED
 
- TX_PAUSE_CONTROL_FRAME_COUNTER
 
- TX_PAUSE_EN
 
- TX_PAUSE_FRAME_HONERED_COUNTER
 
- TX_PAUSE_PKTS
 
- TX_PA_CFG_IGNORE_FRM_ERR
 
- TX_PA_CFG_IGNORE_L2_ERR
 
- TX_PA_CFG_IGNORE_LLC_CTRL
 
- TX_PA_CFG_IGNORE_SNAP_OUI
 
- TX_PCI_JUM_DIS
 
- TX_PCI_JUM_ENA
 
- TX_PEER_NOT_FOUND
 
- TX_PENDED_QUEUE_LENGTH
 
- TX_PI
 
- TX_PIC_INTR
 
- TX_PIN_CFG
 
- TX_PIN_CFG_LNA_PE_A0_EN
 
- TX_PIN_CFG_LNA_PE_A0_POL
 
- TX_PIN_CFG_LNA_PE_A1_EN
 
- TX_PIN_CFG_LNA_PE_A1_POL
 
- TX_PIN_CFG_LNA_PE_A2_EN
 
- TX_PIN_CFG_LNA_PE_A2_POL
 
- TX_PIN_CFG_LNA_PE_G0_EN
 
- TX_PIN_CFG_LNA_PE_G0_POL
 
- TX_PIN_CFG_LNA_PE_G1_EN
 
- TX_PIN_CFG_LNA_PE_G1_POL
 
- TX_PIN_CFG_LNA_PE_G2_EN
 
- TX_PIN_CFG_LNA_PE_G2_POL
 
- TX_PIN_CFG_PA_PE_A0_EN
 
- TX_PIN_CFG_PA_PE_A0_POL
 
- TX_PIN_CFG_PA_PE_A1_EN
 
- TX_PIN_CFG_PA_PE_A1_POL
 
- TX_PIN_CFG_PA_PE_A2_EN
 
- TX_PIN_CFG_PA_PE_A2_POL
 
- TX_PIN_CFG_PA_PE_DISABLE
 
- TX_PIN_CFG_PA_PE_G0_EN
 
- TX_PIN_CFG_PA_PE_G0_POL
 
- TX_PIN_CFG_PA_PE_G1_EN
 
- TX_PIN_CFG_PA_PE_G1_POL
 
- TX_PIN_CFG_PA_PE_G2_EN
 
- TX_PIN_CFG_PA_PE_G2_POL
 
- TX_PIN_CFG_RFRX_EN
 
- TX_PIN_CFG_RFRX_POL
 
- TX_PIN_CFG_RFTR_EN
 
- TX_PIN_CFG_RFTR_POL
 
- TX_PIN_CFG_TRSW_EN
 
- TX_PIN_CFG_TRSW_POL
 
- TX_PIN_EN_MASK
 
- TX_PIN_EN_SHIFT
 
- TX_PKTS
 
- TX_PKT_ALIGNMENT
 
- TX_PKT_HEADER_INS_VLAN_MASK
 
- TX_PKT_HEADER_INS_VLAN_SHIFT
 
- TX_PKT_HEADER_SIZE_MASK
 
- TX_PKT_HEADER_SIZE_SHIFT
 
- TX_PKT_HEADER_VLAN_TAG_MASK
 
- TX_PKT_HEADER_VLAN_TAG_SHIFT
 
- TX_PKT_INT
 
- TX_PKT_INT1
 
- TX_PKT_INT2
 
- TX_PKT_INT3
 
- TX_PKT_PENDING
 
- TX_PKT_RESET
 
- TX_PKT_RETRY
 
- TX_PKT_SENT
 
- TX_PKT_STATUS_ABORT_COL_MASK
 
- TX_PKT_STATUS_ABORT_COL_SHIFT
 
- TX_PKT_STATUS_BCAST_MASK
 
- TX_PKT_STATUS_BCAST_SHIFT
 
- TX_PKT_STATUS_CTRL_MASK
 
- TX_PKT_STATUS_CTRL_SHIFT
 
- TX_PKT_STATUS_DEFER_MASK
 
- TX_PKT_STATUS_DEFER_SHIFT
 
- TX_PKT_STATUS_EXC_DEFER_MASK
 
- TX_PKT_STATUS_EXC_DEFER_SHIFT
 
- TX_PKT_STATUS_LATE_COL_MASK
 
- TX_PKT_STATUS_LATE_COL_SHIFT
 
- TX_PKT_STATUS_MCAST_MASK
 
- TX_PKT_STATUS_MCAST_SHIFT
 
- TX_PKT_STATUS_MULTI_COL_MASK
 
- TX_PKT_STATUS_MULTI_COL_SHIFT
 
- TX_PKT_STATUS_OK_MASK
 
- TX_PKT_STATUS_OK_SHIFT
 
- TX_PKT_STATUS_PAUSE_MASK
 
- TX_PKT_STATUS_PAUSE_SHIFT
 
- TX_PKT_STATUS_SINGLE_COL_MASK
 
- TX_PKT_STATUS_SINGLE_COL_SHIFT
 
- TX_PKT_STATUS_SIZE_MASK
 
- TX_PKT_STATUS_SIZE_SHIFT
 
- TX_PKT_STATUS_UNDERRUN_MASK
 
- TX_PKT_STATUS_UNDERRUN_SHIFT
 
- TX_PKT_STATUS_UPDATE_MASK
 
- TX_PKT_STATUS_UPDATE_SHIFT
 
- TX_PLL_TRIM
 
- TX_POINTER_END
 
- TX_POLARITY_INVERSION_MASK
 
- TX_POLARITY_INVERSION_SHIFT
 
- TX_POLICY_CACHE_SIZE
 
- TX_POLL_DEMAND
 
- TX_POOL_SHIFT
 
- TX_PORT0
 
- TX_PORT_STEERING
 
- TX_POSTCUR_MASK
 
- TX_POSTCUR_SHIFT
 
- TX_POSTCUR_SMASK
 
- TX_POST_MUX
 
- TX_POWER_ATHEROAP_THRESH_HIGH
 
- TX_POWER_ATHEROAP_THRESH_LOW
 
- TX_POWER_IL_ILLEGAL_VOLTAGE
 
- TX_POWER_IL_VOLTAGE_CODES_PER_03V
 
- TX_POWER_INDEX
 
- TX_POWER_IWL_ILLEGAL_VOLTAGE
 
- TX_POWER_NEAR_FIELD_THRESH_8812
 
- TX_POWER_NEAR_FIELD_THRESH_AP
 
- TX_POWER_NEAR_FIELD_THRESH_HIGH
 
- TX_POWER_NEAR_FIELD_THRESH_LOW
 
- TX_POWER_NEAR_FIELD_THRESH_LVL1
 
- TX_POWER_NEAR_FIELD_THRESH_LVL2
 
- TX_POWER_PA_DETECT_MSK
 
- TX_POWER_PA_NOT_ACTIVE
 
- TX_PQ
 
- TX_PRECUR_MASK
 
- TX_PRECUR_SHIFT
 
- TX_PRECUR_SMASK
 
- TX_PRESET_TABLE_ATTN
 
- TX_PRESET_TABLE_MAX
 
- TX_PRESET_TABLE_POSTCUR
 
- TX_PRESET_TABLE_PRECUR
 
- TX_PRESET_TABLE_QSFP_TX_CDR
 
- TX_PRESET_TABLE_QSFP_TX_CDR_APPLY
 
- TX_PRESET_TABLE_QSFP_TX_EQ
 
- TX_PRESET_TABLE_QSFP_TX_EQ_APPLY
 
- TX_PRESET_TABLE_RESERVED
 
- TX_PRE_MUX
 
- TX_PRIORITY_MAPPING
 
- TX_PRIORITY_STEERING
 
- TX_PROG_ALMOST_REG
 
- TX_PSC_A0
 
- TX_PSC_A1
 
- TX_PSC_A2
 
- TX_PSC_A3
 
- TX_PTP_VER_MASK
 
- TX_PTP_VER_SHIFT
 
- TX_PWMGEAR
 
- TX_PWM_BURST_CLOSURE_EXTENSION
 
- TX_PWM_G6_G7_SYNC_LENGTH
 
- TX_PWR_BY_RATE_NUM_BAND
 
- TX_PWR_BY_RATE_NUM_RATE
 
- TX_PWR_BY_RATE_NUM_RF
 
- TX_PWR_BY_RATE_NUM_SECTION
 
- TX_PWR_CFG_0
 
- TX_PWR_CFG_0B_12MBS_18MBS
 
- TX_PWR_CFG_0B_1MBS_2MBS
 
- TX_PWR_CFG_0B_5MBS_11MBS
 
- TX_PWR_CFG_0B_6MBS_9MBS
 
- TX_PWR_CFG_0_11MBS
 
- TX_PWR_CFG_0_12MBS
 
- TX_PWR_CFG_0_18MBS
 
- TX_PWR_CFG_0_1MBS
 
- TX_PWR_CFG_0_2MBS
 
- TX_PWR_CFG_0_55MBS
 
- TX_PWR_CFG_0_6MBS
 
- TX_PWR_CFG_0_9MBS
 
- TX_PWR_CFG_0_CCK1_CH0
 
- TX_PWR_CFG_0_CCK1_CH1
 
- TX_PWR_CFG_0_CCK5_CH0
 
- TX_PWR_CFG_0_CCK5_CH1
 
- TX_PWR_CFG_0_EXT
 
- TX_PWR_CFG_0_EXT_CCK1_CH2
 
- TX_PWR_CFG_0_EXT_CCK5_CH2
 
- TX_PWR_CFG_0_EXT_IDX
 
- TX_PWR_CFG_0_EXT_OFDM12_CH2
 
- TX_PWR_CFG_0_EXT_OFDM6_CH2
 
- TX_PWR_CFG_0_IDX
 
- TX_PWR_CFG_0_OFDM12_CH0
 
- TX_PWR_CFG_0_OFDM12_CH1
 
- TX_PWR_CFG_0_OFDM6_CH0
 
- TX_PWR_CFG_0_OFDM6_CH1
 
- TX_PWR_CFG_1
 
- TX_PWR_CFG_1B_24MBS_36MBS
 
- TX_PWR_CFG_1B_48MBS
 
- TX_PWR_CFG_1B_MCS0_MCS1
 
- TX_PWR_CFG_1B_MCS2_MCS3
 
- TX_PWR_CFG_1_24MBS
 
- TX_PWR_CFG_1_36MBS
 
- TX_PWR_CFG_1_48MBS
 
- TX_PWR_CFG_1_54MBS
 
- TX_PWR_CFG_1_EXT
 
- TX_PWR_CFG_1_EXT_IDX
 
- TX_PWR_CFG_1_EXT_MCS0_CH2
 
- TX_PWR_CFG_1_EXT_MCS2_CH2
 
- TX_PWR_CFG_1_EXT_OFDM24_CH2
 
- TX_PWR_CFG_1_EXT_OFDM48_CH2
 
- TX_PWR_CFG_1_IDX
 
- TX_PWR_CFG_1_MCS0
 
- TX_PWR_CFG_1_MCS0_CH0
 
- TX_PWR_CFG_1_MCS0_CH1
 
- TX_PWR_CFG_1_MCS1
 
- TX_PWR_CFG_1_MCS2
 
- TX_PWR_CFG_1_MCS2_CH0
 
- TX_PWR_CFG_1_MCS2_CH1
 
- TX_PWR_CFG_1_MCS3
 
- TX_PWR_CFG_1_OFDM24_CH0
 
- TX_PWR_CFG_1_OFDM24_CH1
 
- TX_PWR_CFG_1_OFDM48_CH0
 
- TX_PWR_CFG_1_OFDM48_CH1
 
- TX_PWR_CFG_2
 
- TX_PWR_CFG_2B_MCS10_MCS11
 
- TX_PWR_CFG_2B_MCS4_MCS5
 
- TX_PWR_CFG_2B_MCS6_MCS7
 
- TX_PWR_CFG_2B_MCS8_MCS9
 
- TX_PWR_CFG_2_EXT
 
- TX_PWR_CFG_2_EXT_IDX
 
- TX_PWR_CFG_2_EXT_MCS10_CH2
 
- TX_PWR_CFG_2_EXT_MCS4_CH2
 
- TX_PWR_CFG_2_EXT_MCS6_CH2
 
- TX_PWR_CFG_2_EXT_MCS8_CH2
 
- TX_PWR_CFG_2_IDX
 
- TX_PWR_CFG_2_MCS10
 
- TX_PWR_CFG_2_MCS10_CH0
 
- TX_PWR_CFG_2_MCS10_CH1
 
- TX_PWR_CFG_2_MCS11
 
- TX_PWR_CFG_2_MCS4
 
- TX_PWR_CFG_2_MCS4_CH0
 
- TX_PWR_CFG_2_MCS4_CH1
 
- TX_PWR_CFG_2_MCS5
 
- TX_PWR_CFG_2_MCS6
 
- TX_PWR_CFG_2_MCS6_CH0
 
- TX_PWR_CFG_2_MCS6_CH1
 
- TX_PWR_CFG_2_MCS7
 
- TX_PWR_CFG_2_MCS8
 
- TX_PWR_CFG_2_MCS8_CH0
 
- TX_PWR_CFG_2_MCS8_CH1
 
- TX_PWR_CFG_2_MCS9
 
- TX_PWR_CFG_3
 
- TX_PWR_CFG_3B_MCS12_MCS13
 
- TX_PWR_CFG_3B_MCS14
 
- TX_PWR_CFG_3B_STBC_MCS0_MCS1
 
- TX_PWR_CFG_3B_STBC_MCS2_MSC3
 
- TX_PWR_CFG_3_EXT
 
- TX_PWR_CFG_3_EXT_IDX
 
- TX_PWR_CFG_3_EXT_MCS12_CH2
 
- TX_PWR_CFG_3_EXT_MCS14_CH2
 
- TX_PWR_CFG_3_EXT_STBC0_CH2
 
- TX_PWR_CFG_3_EXT_STBC2_CH2
 
- TX_PWR_CFG_3_IDX
 
- TX_PWR_CFG_3_MCS12
 
- TX_PWR_CFG_3_MCS12_CH0
 
- TX_PWR_CFG_3_MCS12_CH1
 
- TX_PWR_CFG_3_MCS13
 
- TX_PWR_CFG_3_MCS14
 
- TX_PWR_CFG_3_MCS14_CH0
 
- TX_PWR_CFG_3_MCS14_CH1
 
- TX_PWR_CFG_3_MCS15
 
- TX_PWR_CFG_3_STBC0_CH0
 
- TX_PWR_CFG_3_STBC0_CH1
 
- TX_PWR_CFG_3_STBC2_CH0
 
- TX_PWR_CFG_3_STBC2_CH1
 
- TX_PWR_CFG_3_UNKNOWN1
 
- TX_PWR_CFG_3_UNKNOWN2
 
- TX_PWR_CFG_3_UNKNOWN3
 
- TX_PWR_CFG_3_UNKNOWN4
 
- TX_PWR_CFG_4
 
- TX_PWR_CFG_4B_STBC_MCS4_MCS5
 
- TX_PWR_CFG_4B_STBC_MCS6
 
- TX_PWR_CFG_4_EXT
 
- TX_PWR_CFG_4_EXT_IDX
 
- TX_PWR_CFG_4_EXT_STBC4_CH2
 
- TX_PWR_CFG_4_EXT_STBC6_CH2
 
- TX_PWR_CFG_4_IDX
 
- TX_PWR_CFG_4_STBC4_CH0
 
- TX_PWR_CFG_4_STBC4_CH1
 
- TX_PWR_CFG_4_STBC6_CH0
 
- TX_PWR_CFG_4_STBC6_CH1
 
- TX_PWR_CFG_4_UNKNOWN5
 
- TX_PWR_CFG_4_UNKNOWN6
 
- TX_PWR_CFG_4_UNKNOWN7
 
- TX_PWR_CFG_4_UNKNOWN8
 
- TX_PWR_CFG_5
 
- TX_PWR_CFG_5_IDX
 
- TX_PWR_CFG_5_MCS16_CH0
 
- TX_PWR_CFG_5_MCS16_CH1
 
- TX_PWR_CFG_5_MCS16_CH2
 
- TX_PWR_CFG_5_MCS18_CH0
 
- TX_PWR_CFG_5_MCS18_CH1
 
- TX_PWR_CFG_5_MCS18_CH2
 
- TX_PWR_CFG_6
 
- TX_PWR_CFG_6_IDX
 
- TX_PWR_CFG_6_MCS20_CH0
 
- TX_PWR_CFG_6_MCS20_CH1
 
- TX_PWR_CFG_6_MCS20_CH2
 
- TX_PWR_CFG_6_MCS22_CH0
 
- TX_PWR_CFG_6_MCS22_CH1
 
- TX_PWR_CFG_6_MCS22_CH2
 
- TX_PWR_CFG_7
 
- TX_PWR_CFG_7B_54MBS
 
- TX_PWR_CFG_7B_MCS7
 
- TX_PWR_CFG_7_IDX
 
- TX_PWR_CFG_7_MCS7_CH0
 
- TX_PWR_CFG_7_MCS7_CH1
 
- TX_PWR_CFG_7_MCS7_CH2
 
- TX_PWR_CFG_7_OFDM54_CH0
 
- TX_PWR_CFG_7_OFDM54_CH1
 
- TX_PWR_CFG_7_OFDM54_CH2
 
- TX_PWR_CFG_8
 
- TX_PWR_CFG_8B_MCS15
 
- TX_PWR_CFG_8_IDX
 
- TX_PWR_CFG_8_MCS15_CH0
 
- TX_PWR_CFG_8_MCS15_CH1
 
- TX_PWR_CFG_8_MCS15_CH2
 
- TX_PWR_CFG_8_MCS23_CH0
 
- TX_PWR_CFG_8_MCS23_CH1
 
- TX_PWR_CFG_8_MCS23_CH2
 
- TX_PWR_CFG_9
 
- TX_PWR_CFG_9B_STBC_MCS7
 
- TX_PWR_CFG_9_IDX
 
- TX_PWR_CFG_9_STBC7_CH0
 
- TX_PWR_CFG_9_STBC7_CH1
 
- TX_PWR_CFG_9_STBC7_CH2
 
- TX_PWR_CFG_IDX_COUNT
 
- TX_PWR_CFG_RATE0
 
- TX_PWR_CFG_RATE1
 
- TX_PWR_CFG_RATE2
 
- TX_PWR_CFG_RATE3
 
- TX_PWR_CFG_RATE4
 
- TX_PWR_CFG_RATE5
 
- TX_PWR_CFG_RATE6
 
- TX_PWR_CFG_RATE7
 
- TX_PWR_SAFETY_CHK
 
- TX_Q
 
- TX_QCHECK_PERIOD
 
- TX_QLEN
 
- TX_QSTAT_INC
 
- TX_QUEUE
 
- TX_QUEUED
 
- TX_QUEUE_CFG_ENABLE_QUEUE
 
- TX_QUEUE_CFG_TFD_SHORT_FORMAT
 
- TX_QUEUE_ENTRIES
 
- TX_QUEUE_G
 
- TX_QUEUE_LEN
 
- TX_QUEUE_LENGTH
 
- TX_QUEUE_LEN_RESTART
 
- TX_QUEUE_M
 
- TX_QUEUE_NO
 
- TX_QUEUE_NUM
 
- TX_QUEUE_NUM_MSK
 
- TX_QUEUE_PRIO_HIGH
 
- TX_QUEUE_PRIO_LOW
 
- TX_QUEUE_REG_OFFSET
 
- TX_QUEUE_S
 
- TX_QUEUE_SIZE
 
- TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK
 
- TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT
 
- TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK
 
- TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT
 
- TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK
 
- TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT
 
- TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK
 
- TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT
 
- TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK
 
- TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT
 
- TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK
 
- TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT
 
- TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK
 
- TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT
 
- TX_QUEUE_V
 
- TX_QUIET_EN
 
- TX_Q_ENTRIES
 
- TX_Q_LEN
 
- TX_Q_LIMIT
 
- TX_RADIOTAP_PRESENT
 
- TX_RAMBIST_RAM32A_PASS
 
- TX_RAMBIST_RAM32B_PASS
 
- TX_RAMBIST_RAM33A_PASS
 
- TX_RAMBIST_RAM33B_PASS
 
- TX_RAMBIST_START
 
- TX_RAMBIST_STATE
 
- TX_RAMBIST_SUMMARY
 
- TX_RATES
 
- TX_RATE_11BG_AUTO
 
- TX_RATE_11B_AUTO
 
- TX_RATE_11M
 
- TX_RATE_11MBIT
 
- TX_RATE_11M_FIXED
 
- TX_RATE_11_AUTO
 
- TX_RATE_11_MBIT
 
- TX_RATE_12M
 
- TX_RATE_18M
 
- TX_RATE_1M
 
- TX_RATE_1MBIT
 
- TX_RATE_1M_FIXED
 
- TX_RATE_1_2M_AUTO
 
- TX_RATE_1_MBIT
 
- TX_RATE_24M
 
- TX_RATE_2M
 
- TX_RATE_2MBIT
 
- TX_RATE_2M_FIXED
 
- TX_RATE_2_MBIT
 
- TX_RATE_36M
 
- TX_RATE_48M
 
- TX_RATE_54M
 
- TX_RATE_5M
 
- TX_RATE_5M_FIXED
 
- TX_RATE_5_5MBIT
 
- TX_RATE_5_5_MBIT
 
- TX_RATE_6M
 
- TX_RATE_9M
 
- TX_RATE_AUTO
 
- TX_RATE_FIXED
 
- TX_RATE_FULL_AUTO
 
- TX_RATE_MANUAL_AUTO
 
- TX_RATE_MASK
 
- TX_RATE_REG
 
- TX_RATE_UNIT
 
- TX_RCVDET_CTRL
 
- TX_RCVDET_EN_TMR
 
- TX_RCVDET_ST_TMR
 
- TX_RDY
 
- TX_READ
 
- TX_READY
 
- TX_READ_ALLOC_L3
 
- TX_RECLAIM_CHUNK
 
- TX_RECLAIM_PERIOD
 
- TX_RECLAIM_TIMER_CHUNK
 
- TX_REFCLKFREQ
 
- TX_REG_BANK
 
- TX_REG_DESC_SIZE
 
- TX_REG_OFFSET
 
- TX_REG_OFFSET_DESC0
 
- TX_REG_OFFSET_DESC1
 
- TX_REG_OFFSET_DESC2
 
- TX_REG_STEP_0V
 
- TX_REG_STEP_N_25MV
 
- TX_REG_STEP_N_50MV
 
- TX_REG_STEP_N_75MV
 
- TX_REG_STEP_P_25MV
 
- TX_REG_STEP_P_50MV
 
- TX_RELEASE_TO_PPE
 
- TX_REPORT1
 
- TX_REPORT2
 
- TX_REPORT_CTRL_TIMER_ENABLE
 
- TX_REQ_CURRENT
 
- TX_REQ_NEXT
 
- TX_RESCAL_CODE_MASK
 
- TX_RESCAL_CODE_OFFSET
 
- TX_RESERVED
 
- TX_RESET_DONE
 
- TX_RESET_MULTI_IDX
 
- TX_RESET_TRIES
 
- TX_RESUME_BUNDLE_THRESHOLD
 
- TX_RES_INIT_RATE_INDEX_MSK
 
- TX_RES_INV_RATE_INDEX_MSK
 
- TX_RES_RATE_TABLE_COLOR_MSK
 
- TX_RES_RATE_TABLE_COLOR_POS
 
- TX_RES_RATE_TABLE_COL_GET
 
- TX_RETIME_SRC_CLKGEN
 
- TX_RETIME_SRC_CLK_125
 
- TX_RETIME_SRC_NA
 
- TX_RETIME_SRC_PHYCLK
 
- TX_RETIME_SRC_TXCLK
 
- TX_RETRY
 
- TX_RETRY_COUNT_REG
 
- TX_RETRY_EN
 
- TX_RETRY_EXCEEDED
 
- TX_RF_FREQUENCY
 
- TX_RF_GAIN
 
- TX_RING
 
- TX_RING_ALLOC_SIZE
 
- TX_RING_BASE
 
- TX_RING_BUFFERS
 
- TX_RING_BUFFER_SIZE
 
- TX_RING_BYTES
 
- TX_RING_CSR0
 
- TX_RING_CSR0_AC0_RING_SIZE
 
- TX_RING_CSR0_AC1_RING_SIZE
 
- TX_RING_CSR0_AC2_RING_SIZE
 
- TX_RING_CSR0_AC3_RING_SIZE
 
- TX_RING_CSR1
 
- TX_RING_CSR1_HCCA_RING_SIZE
 
- TX_RING_CSR1_MGMT_RING_SIZE
 
- TX_RING_CSR1_TXD_SIZE
 
- TX_RING_DEFAULT
 
- TX_RING_DR_MOD_MASK
 
- TX_RING_ENTRIES
 
- TX_RING_GAP
 
- TX_RING_HDL
 
- TX_RING_HDL_HEAD
 
- TX_RING_HDL_HEAD_SHIFT
 
- TX_RING_HDL_WRAP
 
- TX_RING_KICK
 
- TX_RING_KICK_TAIL
 
- TX_RING_KICK_WRAP
 
- TX_RING_LEN_BITS
 
- TX_RING_MASK
 
- TX_RING_MAX
 
- TX_RING_MAXSIZE
 
- TX_RING_MAX_LEN
 
- TX_RING_MIN
 
- TX_RING_MIN_LEN
 
- TX_RING_MOD_MASK
 
- TX_RING_NR
 
- TX_RING_SIZE
 
- TX_RING_SIZE_POW
 
- TX_RING_SZ
 
- TX_RING_SZ_MASK
 
- TX_RNG_CFIG
 
- TX_RNG_CFIG_LEN
 
- TX_RNG_CFIG_LEN_SHIFT
 
- TX_RNG_CFIG_STADDR
 
- TX_RNG_CFIG_STADDR_BASE
 
- TX_RNG_ERR_LOGH
 
- TX_RNG_ERR_LOGH_ERR
 
- TX_RNG_ERR_LOGH_ERRADDR
 
- TX_RNG_ERR_LOGH_ERRCODE
 
- TX_RNG_ERR_LOGH_MERR
 
- TX_RNG_ERR_LOGL
 
- TX_RNG_ERR_LOGL_ERRADDR
 
- TX_RPT1_PKT_LEN
 
- TX_RPT2_ITEM_SIZE
 
- TX_RQ_ALEMPTY_INT
 
- TX_RQ_ALEMPTY_TH
 
- TX_RQ_ALFULL_INT
 
- TX_RQ_ALFULL_TH
 
- TX_RQ_DEPTH
 
- TX_RQ_EMPTY_INT
 
- TX_RQ_FREE_DESC_CNT
 
- TX_RQ_FULL_INT
 
- TX_RQ_INT_THRESHOLD
 
- TX_RQ_IN_INT
 
- TX_RQ_IN_TIMEOUT
 
- TX_RQ_IN_TIMEOUT_INT
 
- TX_RQ_IN_TIMEOUT_TH
 
- TX_RQ_RD_ADDR
 
- TX_RQ_REG_EN
 
- TX_RQ_START_ADDR
 
- TX_RQ_WR_ADDR
 
- TX_RST
 
- TX_RTS_CFG
 
- TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT
 
- TX_RTS_CFG_RTS_FBK_EN
 
- TX_RTS_CFG_RTS_THRES
 
- TX_RTY_CFG
 
- TX_RTY_CFG_AGG_RTY_MODE
 
- TX_RTY_CFG_LONG_RTY_LIMIT
 
- TX_RTY_CFG_LONG_RTY_THRE
 
- TX_RTY_CFG_NON_AGG_RTY_MODE
 
- TX_RTY_CFG_SHORT_RTY_LIMIT
 
- TX_RTY_CFG_TX_AUTO_FB_ENABLE
 
- TX_RUN
 
- TX_RUNNING
 
- TX_RUNT
 
- TX_RX_1024_1518_BYTE_FRAME
 
- TX_RX_128_255_BYTE_FRAME
 
- TX_RX_1519_1522_VLAN_BYTE_FRAME
 
- TX_RX_256_511_BYTE_FRAME
 
- TX_RX_512_1023_BYTE_FRAME
 
- TX_RX_64_127_BYTE_FRAME
 
- TX_RX_64_BYTE_FRAME
 
- TX_RX_CFG0_BASE
 
- TX_RX_CFG0_RSVD
 
- TX_RX_CFG0_SIZE
 
- TX_RX_CFG1_BASE
 
- TX_RX_DESC_REQ
 
- TX_RX_RING
 
- TX_RX_THR_CTRL
 
- TX_RX_TYPE_MASK
 
- TX_SBE
 
- TX_SCOL_MASK
 
- TX_SCOL_SHIFT_BIT
 
- TX_SEC_CNT0
 
- TX_SEL
 
- TX_SELE_EQ
 
- TX_SELE_HQ
 
- TX_SELE_LQ
 
- TX_SELE_NQ
 
- TX_SEND
 
- TX_SENDSTALL
 
- TX_SEND_OK_BITS
 
- TX_SENTSTALL
 
- TX_SEQ_TO_INDEX
 
- TX_SERVICE_INT
 
- TX_SESSION_MISMATCH
 
- TX_SET
 
- TX_SETTINGS
 
- TX_SETUP
 
- TX_SET_CONFIG
 
- TX_SFD_GPIO_MASK
 
- TX_SFD_GPIO_SHIFT
 
- TX_SHOVE_S
 
- TX_SHOVE_V
 
- TX_SINGLE_COLLISION_PACKET_COUNTER
 
- TX_SIZE
 
- TX_SIZE_ADJUST1
 
- TX_SLEW_CAL_MAN_EN
 
- TX_SLEW_SW_120_PS
 
- TX_SLEW_SW_40_PS
 
- TX_SLEW_SW_80_PS
 
- TX_SLOT
 
- TX_SLOTS_PER_FRAME
 
- TX_SLOT_8CH
 
- TX_SLOT_MONO
 
- TX_SLOT_STEREO
 
- TX_SMALL_FIFO
 
- TX_SMALL_PACKET
 
- TX_SM_1_CACHE_MASK
 
- TX_SM_1_CBQ_ARB_MASK
 
- TX_SM_1_CHAIN_MASK
 
- TX_SM_1_CSUM_MASK
 
- TX_SM_1_FIFO_LOAD_MASK
 
- TX_SM_1_FIFO_UNLOAD_MASK
 
- TX_SM_2_COMP_WB_MASK
 
- TX_SM_2_KICK_MASK
 
- TX_SM_2_SUB_LOAD_MASK
 
- TX_SNAPSHOT_LOCKED
 
- TX_SPDSEL_20DEC
 
- TX_SPDSEL_40DEC
 
- TX_SPDSEL_80DEC
 
- TX_SPEED
 
- TX_SPND
 
- TX_SQE_ERROR
 
- TX_SQE_ERROR_ENBL
 
- TX_SRAM
 
- TX_SRAM_END
 
- TX_SRAM_POOL_FREE
 
- TX_SRAM_POOL_START
 
- TX_SS_BURST
 
- TX_START
 
- TX_START_128_BYTES
 
- TX_START_4_BYTES
 
- TX_START_64_BYTES
 
- TX_START_ALL_BYTES
 
- TX_STATS_ENUM_LAST
 
- TX_STATUS
 
- TX_STATUS_ABORT_MSK
 
- TX_STATUS_ACK_RCV
 
- TX_STATUS_AMPDU
 
- TX_STATUS_APP_CRC
 
- TX_STATUS_BA_BMAP03_MASK
 
- TX_STATUS_BA_BMAP03_SHIFT
 
- TX_STATUS_BA_BMAP47_MASK
 
- TX_STATUS_BA_BMAP47_SHIFT
 
- TX_STATUS_BE
 
- TX_STATUS_BRCM_TAG_NO_ACT
 
- TX_STATUS_BRCM_TAG_ONE_QUEUE
 
- TX_STATUS_BRCM_TAG_ONE_TSB
 
- TX_STATUS_BRCM_TAG_ZERO
 
- TX_STATUS_COUNT_REG
 
- TX_STATUS_DATA_OUT_COUNT_MASK
 
- TX_STATUS_DELAY_MSK
 
- TX_STATUS_DESC_READY_POS
 
- TX_STATUS_DIRECT_DONE
 
- TX_STATUS_ENTRY
 
- TX_STATUS_FAIL
 
- TX_STATUS_FAIL_BT_RETRY
 
- TX_STATUS_FAIL_DEST_PS
 
- TX_STATUS_FAIL_DRAIN_FLOW
 
- TX_STATUS_FAIL_FIFO_FLUSHED
 
- TX_STATUS_FAIL_FIFO_UNDERRUN
 
- TX_STATUS_FAIL_FRAG_DROPPED
 
- TX_STATUS_FAIL_FW_DROP
 
- TX_STATUS_FAIL_HOST_ABORTED
 
- TX_STATUS_FAIL_INSUFFICIENT_CF_POLL
 
- TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY
 
- TX_STATUS_FAIL_LIFE_EXPIRE
 
- TX_STATUS_FAIL_LONG_LIMIT
 
- TX_STATUS_FAIL_NO_BEACON_ON_RADAR
 
- TX_STATUS_FAIL_PASSIVE_NO_RX
 
- TX_STATUS_FAIL_RFKILL_FLUSH
 
- TX_STATUS_FAIL_SHORT_LIMIT
 
- TX_STATUS_FAIL_SMALL_CF_POLL
 
- TX_STATUS_FAIL_STA_COLOR_MISMATCH
 
- TX_STATUS_FAIL_STA_INVALID
 
- TX_STATUS_FAIL_TID_DISABLE
 
- TX_STATUS_FAIL_UNDERRUN
 
- TX_STATUS_FIFO
 
- TX_STATUS_FIFO_PEEK
 
- TX_STATUS_FRM_RTX_MASK
 
- TX_STATUS_FRM_RTX_SHIFT
 
- TX_STATUS_IND
 
- TX_STATUS_INTERMEDIATE
 
- TX_STATUS_INTERNAL_ABORT
 
- TX_STATUS_LINK_UP
 
- TX_STATUS_MASK
 
- TX_STATUS_MSK
 
- TX_STATUS_NO_ACK
 
- TX_STATUS_ODI_OVERRUN
 
- TX_STATUS_ODI_UNDERRUN
 
- TX_STATUS_OFF
 
- TX_STATUS_OWR_CRC
 
- TX_STATUS_PMINDCTD
 
- TX_STATUS_POSTPONE
 
- TX_STATUS_POSTPONE_BT_PRIO
 
- TX_STATUS_POSTPONE_CALC_TTAK
 
- TX_STATUS_POSTPONE_DELAY
 
- TX_STATUS_POSTPONE_FEW_BYTES
 
- TX_STATUS_POSTPONE_QUIET_PERIOD
 
- TX_STATUS_PS
 
- TX_STATUS_READING
 
- TX_STATUS_RTS_RTX_MASK
 
- TX_STATUS_RTS_RTX_SHIFT
 
- TX_STATUS_SENT_XOFF
 
- TX_STATUS_SENT_XON
 
- TX_STATUS_SKIP_BYTES
 
- TX_STATUS_SUCCESS
 
- TX_STATUS_SUPR_BADCH
 
- TX_STATUS_SUPR_EXPTIME
 
- TX_STATUS_SUPR_FLUSH
 
- TX_STATUS_SUPR_FRAG
 
- TX_STATUS_SUPR_MASK
 
- TX_STATUS_SUPR_PMQ
 
- TX_STATUS_SUPR_SHIFT
 
- TX_STATUS_SUPR_TBTT
 
- TX_STATUS_SUPR_UF
 
- TX_STATUS_UNEXP
 
- TX_STATUS_UNEXP_AMPDU
 
- TX_STATUS_UR
 
- TX_STATUS_VALID
 
- TX_STATUS_VLAN_NO_ACT
 
- TX_STATUS_VLAN_PCP_TSB
 
- TX_STATUS_VLAN_QUEUE
 
- TX_STATUS_VLAN_VID_TSB
 
- TX_STATUS_XOFFED
 
- TX_STAT_ADD
 
- TX_STAT_INC
 
- TX_STAT_M
 
- TX_STA_CNT0
 
- TX_STA_CNT0_TX_BEACON_COUNT
 
- TX_STA_CNT0_TX_FAIL_COUNT
 
- TX_STA_CNT1
 
- TX_STA_CNT1_TX_RETRANSMIT
 
- TX_STA_CNT1_TX_SUCCESS
 
- TX_STA_CNT2
 
- TX_STA_CNT2_TX_UNDER_FLOW_COUNT
 
- TX_STA_CNT2_TX_ZERO_LEN_COUNT
 
- TX_STA_ERR
 
- TX_STA_FIFO
 
- TX_STA_FIFO_BW
 
- TX_STA_FIFO_MCS
 
- TX_STA_FIFO_PHYMODE
 
- TX_STA_FIFO_PID_ENTRY
 
- TX_STA_FIFO_PID_QUEUE
 
- TX_STA_FIFO_PID_TYPE
 
- TX_STA_FIFO_SGI
 
- TX_STA_FIFO_SUCCESS_RATE
 
- TX_STA_FIFO_TX_ACK_REQUIRED
 
- TX_STA_FIFO_TX_AGGRE
 
- TX_STA_FIFO_TX_SUCCESS
 
- TX_STA_FIFO_VALID
 
- TX_STA_FIFO_WCID
 
- TX_STFW_DIS
 
- TX_STFW_ENA
 
- TX_STOP_BIT_LEN_1
 
- TX_STOP_BIT_LEN_1_5
 
- TX_STOP_BIT_LEN_2
 
- TX_STOP_BIT_LEN_MSK
 
- TX_STOP_THRESH
 
- TX_STP
 
- TX_STS_COLL_CNT_
 
- TX_STS_DEFERRED_
 
- TX_STS_ES_
 
- TX_STS_EXCESS_COL_
 
- TX_STS_LATE_COLL_
 
- TX_STS_LATE_COL_
 
- TX_STS_LOC_
 
- TX_STS_LOST_CARRIER_
 
- TX_STS_MANY_COLL_
 
- TX_STS_MANY_DEFER_
 
- TX_STS_NO_CARRIER_
 
- TX_STS_NO_CARR_
 
- TX_STS_TAG_
 
- TX_STS_UNDERRUN_
 
- TX_SUBMIT
 
- TX_SUCCESS
 
- TX_SUSPENDED
 
- TX_SWITCHING
 
- TX_SW_CFG0
 
- TX_SW_CFG1
 
- TX_SW_CFG2
 
- TX_SYMBOL_CLK_REQ_FORCE
 
- TX_SYNC_SEL_MASK
 
- TX_SYNC_SHIFT_BASE
 
- TX_SYNC_SOURCE
 
- TX_SYNC_SRG_AUTO
 
- TX_SYNC_SRG_PROG
 
- TX_TAGH
 
- TX_TAGH_TSR_BIT
 
- TX_TAGL
 
- TX_TAIL
 
- TX_TAILDESC_PTR
 
- TX_TAIL_SET_DMAC_INT_EN_
 
- TX_TAIL_SET_TOP_INT_EN_
 
- TX_TAIL_SET_TOP_INT_VEC_EN_
 
- TX_TARGET_ABORT_LEN
 
- TX_TCPV6_PKT
 
- TX_TCP_LSO
 
- TX_TCP_LSO6
 
- TX_TCP_PKT
 
- TX_TC_INT
 
- TX_TERMINAL_CTRL_50_OHM
 
- TX_TERM_LOAD_DIS
 
- TX_TEST_MODE_16MHz
 
- TX_TEST_MODE_2_29MHz
 
- TX_TEST_MODE_2_66MHz
 
- TX_TEST_MODE_3_2MHz
 
- TX_TEST_MODE_4MHz
 
- TX_TEST_MODE_5_33MHz
 
- TX_TEST_MODE_8MHz
 
- TX_THR
 
- TX_THRESH
 
- TX_THRESHOLD
 
- TX_THRESHOLD_DECREMENT
 
- TX_THRESHOLD_DISABLE
 
- TX_THRESHOLD_INCREMENT
 
- TX_THRESHOLD_KEEP_LIMIT
 
- TX_THRESHOLD_MAX
 
- TX_THRESHOLD_START
 
- TX_THRESHOLD_STOP
 
- TX_THRESHOLD_TIMER_MS
 
- TX_THRESH_CE4100_DFLT
 
- TX_THRESH_DFLT
 
- TX_THRESH_HI
 
- TX_THRESH_LO
 
- TX_THRESH_QUARK_X1000_DFLT
 
- TX_TIMEO
 
- TX_TIMEOUT
 
- TX_TIMEOUT_CFG
 
- TX_TIMEOUT_CFG_MPDU_LIFETIME
 
- TX_TIMEOUT_CFG_RX_ACK_TIMEOUT
 
- TX_TIMEOUT_CFG_TX_OP_TIMEOUT
 
- TX_TIMEOUT_JIFFIES
 
- TX_TIMEOUT_NSECS
 
- TX_TIMEOUT_THRESHOLD
 
- TX_TIMEO_LIMIT
 
- TX_TIMESTAMPING_EN
 
- TX_TIMESTAMP_EVENT_LEN
 
- TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LBN
 
- TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_LEN
 
- TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST
 
- TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_WIDTH
 
- TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN
 
- TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LEN
 
- TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST
 
- TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_WIDTH
 
- TX_TIMESTAMP_EVENT_TX_EV_COMPLETION
 
- TX_TIMESTAMP_EVENT_TX_EV_CTPIO_COMPLETION
 
- TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_HI
 
- TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_LO
 
- TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI
 
- TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO
 
- TX_TIMESTAMP_EVENT_TX_EV_TYPE_LBN
 
- TX_TIMESTAMP_EVENT_TX_EV_TYPE_LEN
 
- TX_TIMESTAMP_EVENT_TX_EV_TYPE_OFST
 
- TX_TIMESTAMP_EVENT_TX_EV_TYPE_WIDTH
 
- TX_TINY_BUF_BLOCK
 
- TX_TINY_BUF_LEN
 
- TX_TLSHDR_LEN
 
- TX_TNL_TYPE_GENEVE
 
- TX_TNL_TYPE_NVGRE
 
- TX_TNL_TYPE_OPAQUE
 
- TX_TNL_TYPE_VXLAN
 
- TX_TOTAL_COLLISION_COUNTER
 
- TX_TOTAL_DISCARDS
 
- TX_TOTAL_PAGE_NUM
 
- TX_TOTAL_PAGE_NUMBER
 
- TX_TOTAL_PAGE_NUMBER_8723B
 
- TX_TOTAL_PAGE_NUMBER_88E
 
- TX_TOTAL_PAGE_NUM_8192E
 
- TX_TOTAL_PAGE_NUM_8723B
 
- TX_TOTAL_SIZE
 
- TX_TPD
 
- TX_TPD_MIN_IPG_MASK
 
- TX_TPD_MIN_IPG_SHIFT
 
- TX_TRAFFIC_INTR
 
- TX_TRAFFIC_INT_n
 
- TX_TRAINING_EN
 
- TX_TRANSFER
 
- TX_TRANS_LEN_MSK
 
- TX_TRIGGER
 
- TX_TSO_OFFLOAD_THRESH_MASK
 
- TX_TSPEC_ACTION_DOWNGRADE
 
- TX_TSPEC_ACTION_NONE
 
- TX_TSPEC_ACTION_STOP_DOWNGRADE
 
- TX_TSR
 
- TX_TSS_CID
 
- TX_TSTAMP_TIMEOUT
 
- TX_TS_EN
 
- TX_TS_ENABLE
 
- TX_TS_FIFO_SYNC_RST
 
- TX_TS_FLAG_ONE_STEP_SYNC
 
- TX_TS_FLAG_TIMESTAMPING_ENABLED
 
- TX_TWO_PART_DEFF_DISABLE
 
- TX_TXBF_CFG_0
 
- TX_TXBF_CFG_1
 
- TX_TXBF_CFG_2
 
- TX_TXBF_CFG_3
 
- TX_TXCC_CAL_SCLR_MULT
 
- TX_TXCC_CPOST_MULT_00
 
- TX_TXCC_CPOST_MULT_01
 
- TX_TXCC_CPOST_MULT_10
 
- TX_TXCC_CPOST_MULT_11
 
- TX_TXCC_MGNFS_MULT_000
 
- TX_TXCC_MGNFS_MULT_001
 
- TX_TXCC_MGNFS_MULT_010
 
- TX_TXCC_MGNFS_MULT_011
 
- TX_TXCC_MGNFS_MULT_100
 
- TX_TXCC_MGNFS_MULT_101
 
- TX_TXCC_MGNFS_MULT_110
 
- TX_TXCC_MGNFS_MULT_111
 
- TX_TXCC_MGNLS_MULT_000
 
- TX_TXCC_MGNLS_MULT_001
 
- TX_TXCC_MGNLS_MULT_010
 
- TX_TXCC_MGNLS_MULT_011
 
- TX_TXCC_MGNLS_MULT_100
 
- TX_TXCC_MGNLS_MULT_101
 
- TX_TXCC_MGNLS_MULT_110
 
- TX_TXCC_MGNLS_MULT_111
 
- TX_TXMAXPKTSZ
 
- TX_TXMAXPKTSZ_MSK
 
- TX_TXPKTRDY
 
- TX_TX_EARLY_TH_MASK
 
- TX_TX_EARLY_TH_SHIFT
 
- TX_TYPE
 
- TX_T_DONE
 
- TX_UBR
 
- TX_UBR_CAPPED
 
- TX_UCAST
 
- TX_UCAST_PKTS
 
- TX_UDPV6_PKT
 
- TX_UDP_PKT
 
- TX_ULD
 
- TX_ULP_MODE_G
 
- TX_ULP_MODE_M
 
- TX_ULP_MODE_S
 
- TX_ULP_MODE_V
 
- TX_UNAVAILABLE_PRIORITY
 
- TX_UNDERRUN
 
- TX_UNDERRUN_ENBL
 
- TX_UNDERRUN_ERR_INT
 
- TX_UNDERRUN_IDX
 
- TX_UNDERSIZE_FRAME_COUNTER
 
- TX_UNDERSIZE_PKT
 
- TX_UNLINK
 
- TX_URB_COUNT
 
- TX_URG_S
 
- TX_URG_V
 
- TX_USAGE
 
- TX_UT_MODE
 
- TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420
 
- TX_VBOOSTLEVEL_OVRD_IN_VBOOST_DEFAULT
 
- TX_VCI_MASK
 
- TX_VDD12_11
 
- TX_VDD12_12
 
- TX_VDD12_13
 
- TX_VDD12_VDD
 
- TX_VDD15_14
 
- TX_VDD15_15
 
- TX_VDD15_16
 
- TX_VDD15_17
 
- TX_VLAN_STEERING
 
- TX_VLAN_TAG
 
- TX_VLAN_TAG_OFF
 
- TX_VLAN_TAG_ON
 
- TX_VMARGIN_MASK
 
- TX_VMARGIN_OFFSET
 
- TX_VOL_CTL_CFG_MUTE_EN_ENABLE
 
- TX_VOL_CTL_CFG_MUTE_EN_MASK
 
- TX_W1C_BITS
 
- TX_WAKE_DESC_CNT
 
- TX_WAKE_THRESHOLD
 
- TX_WATCHDOG
 
- TX_WATERMARK
 
- TX_WORD_LEN_MSK
 
- TX_WORK_PER_LOOP
 
- TX_XDP
 
- TX_XGXS_INTR
 
- TX_XOFF
 
- TX_ZERO_PADDING
 
- TX_mask
 
- TX_state
 
- TXcmd
 
- TXrptr
 
- TXwptr
 
- TXx9_IRCER_ICE
 
- TXx9_IRCR_DOWN
 
- TXx9_IRCR_EDGE
 
- TXx9_IRCR_HIGH
 
- TXx9_IRCR_LOW
 
- TXx9_IRCR_UP
 
- TXx9_IRCSR_IF
 
- TXx9_IRCSR_ILV_MASK
 
- TXx9_IRCSR_IVL_MASK
 
- TXx9_IRSCR_EIClrE
 
- TXx9_IRSCR_EIClr_MASK
 
- TXx9_MAX_IR
 
- TXx9_SPCR0
 
- TXx9_SPCR0_IFSPSE
 
- TXx9_SPCR0_RBSIE
 
- TXx9_SPCR0_RXIFL_MASK
 
- TXx9_SPCR0_SBOS
 
- TXx9_SPCR0_SIDIE
 
- TXx9_SPCR0_SOEIE
 
- TXx9_SPCR0_SPHA
 
- TXx9_SPCR0_SPOL
 
- TXx9_SPCR0_TBSIE
 
- TXx9_SPCR0_TXIFL_MASK
 
- TXx9_SPCR1
 
- TXx9_SPDR
 
- TXx9_SPFS
 
- TXx9_SPMCR
 
- TXx9_SPMCR_ACTIVE
 
- TXx9_SPMCR_BCLR
 
- TXx9_SPMCR_CONFIG
 
- TXx9_SPMCR_OPMODE
 
- TXx9_SPMCR_SPSTP
 
- TXx9_SPSR
 
- TXx9_SPSR_IFSD
 
- TXx9_SPSR_RBSI
 
- TXx9_SPSR_RBS_MASK
 
- TXx9_SPSR_SIDLE
 
- TXx9_SPSR_SPOE
 
- TXx9_SPSR_SRRDY
 
- TXx9_SPSR_STRDY
 
- TXx9_SPSR_TBSI
 
- TXx9_SPSR_TBS_MASK
 
- TXx9_TMITMR_TIIE
 
- TXx9_TMITMR_TZCE
 
- TXx9_TMTCR_CCDE
 
- TXx9_TMTCR_CCS
 
- TXx9_TMTCR_CRE
 
- TXx9_TMTCR_ECES
 
- TXx9_TMTCR_TCE
 
- TXx9_TMTCR_TMODE_ITVL
 
- TXx9_TMTCR_TMODE_MASK
 
- TXx9_TMTCR_TMODE_PGEN
 
- TXx9_TMTCR_TMODE_WDOG
 
- TXx9_TMTISR_TIIS
 
- TXx9_TMTISR_TPIAS
 
- TXx9_TMTISR_TPIBS
 
- TXx9_TMWTMR_TWC
 
- TXx9_TMWTMR_TWIE
 
- TXx9_TMWTMR_WDIS
 
- TYP
 
- TYPE
 
- TYPE0
 
- TYPE0_TASK_CXT_SIZE
 
- TYPE1
 
- TYPE1_HDR_OFFSET
 
- TYPE1_TASK_CXT_SIZE
 
- TYPE2
 
- TYPE2_INTR
 
- TYPE2_MASK
 
- TYPE2_SHIFT
 
- TYPE3
 
- TYPE4
 
- TYPE4_MAX_PAYLOAD
 
- TYPE5
 
- TYPE50_CRB1_FMT
 
- TYPE50_CRB2_FMT
 
- TYPE50_CRB3_FMT
 
- TYPE50_MEB1_FMT
 
- TYPE50_MEB2_FMT
 
- TYPE50_MEB3_FMT
 
- TYPE50_TYPE_CODE
 
- TYPE6
 
- TYPE80_RSP_CODE
 
- TYPE82_RSP_CODE
 
- TYPE86_FMT2
 
- TYPE86_RSP_CODE
 
- TYPE87_RSP_CODE
 
- TYPE88_RSP_CODE
 
- TYPECHECK_H_INCLUDED
 
- TYPEC_ACCESSORY_AUDIO
 
- TYPEC_ACCESSORY_DEBUG
 
- TYPEC_ACCESSORY_NONE
 
- TYPEC_ANY_MODE
 
- TYPEC_CC_OPEN
 
- TYPEC_CC_RA
 
- TYPEC_CC_RD
 
- TYPEC_CC_RP_1_5
 
- TYPEC_CC_RP_3_0
 
- TYPEC_CC_RP_DEF
 
- TYPEC_DEVICE
 
- TYPEC_DP_STATE_A
 
- TYPEC_DP_STATE_B
 
- TYPEC_DP_STATE_C
 
- TYPEC_DP_STATE_D
 
- TYPEC_DP_STATE_E
 
- TYPEC_DP_STATE_F
 
- TYPEC_HOST
 
- TYPEC_MAX_ACCESSORY
 
- TYPEC_MODAL_STATE
 
- TYPEC_MODE_AUDIO
 
- TYPEC_MODE_DEBUG
 
- TYPEC_NO_PREFERRED_ROLE
 
- TYPEC_ORIENTATION_NONE
 
- TYPEC_ORIENTATION_NORMAL
 
- TYPEC_ORIENTATION_REVERSE
 
- TYPEC_PLUG_SOP_P
 
- TYPEC_PLUG_SOP_PP
 
- TYPEC_POLARITY_CC1
 
- TYPEC_POLARITY_CC2
 
- TYPEC_PORT_DFP
 
- TYPEC_PORT_DRD
 
- TYPEC_PORT_DRP
 
- TYPEC_PORT_SNK
 
- TYPEC_PORT_SRC
 
- TYPEC_PORT_UFP
 
- TYPEC_PWR_MODE_1_5A
 
- TYPEC_PWR_MODE_3_0A
 
- TYPEC_PWR_MODE_PD
 
- TYPEC_PWR_MODE_USB
 
- TYPEC_SINK
 
- TYPEC_SOURCE
 
- TYPEC_STATE_MODAL
 
- TYPEC_STATE_SAFE
 
- TYPEC_STATE_USB
 
- TYPEDATUM_PROPERTY_ATTRIBUTE
 
- TYPEDATUM_PROPERTY_PRIMARY
 
- TYPEDO
 
- TYPEIO
 
- TYPEM
 
- TYPEN
 
- TYPEO
 
- TYPERANGE_0_TO_2
 
- TYPERANGE_0_TO_32767
 
- TYPERANGE_0_TO_3600
 
- TYPERANGE_0_TO_65535
 
- TYPERANGE_1_TO_65535
 
- TYPERANGE_2_TO_3600
 
- TYPERANGE_512_TO_16777215
 
- TYPERANGE_AUTH
 
- TYPERANGE_BOOL_AND
 
- TYPERANGE_BOOL_OR
 
- TYPERANGE_DIGEST
 
- TYPERANGE_ISCSINAME
 
- TYPERANGE_SESSIONTYPE
 
- TYPERANGE_TARGETADDRESS
 
- TYPERANGE_UTF8
 
- TYPERESET
 
- TYPESEL_LEN
 
- TYPESEL_POS
 
- TYPESEL_SET
 
- TYPE_01
 
- TYPE_32BITSPACE
 
- TYPE_3_POLE
 
- TYPE_4_POLE_OMTP
 
- TYPE_4_POLE_STANDARD
 
- TYPE_AC0DMA
 
- TYPE_ACL
 
- TYPE_ACLTAB
 
- TYPE_ADCV1
 
- TYPE_ADCV11
 
- TYPE_ADCV12
 
- TYPE_ADCV2
 
- TYPE_ADCV3
 
- TYPE_AFPF
 
- TYPE_AFVF
 
- TYPE_ALIGN
 
- TYPE_ALL
 
- TYPE_ALNA0
 
- TYPE_ALNA1
 
- TYPE_ALNA2
 
- TYPE_ALNA3
 
- TYPE_AM437USB2
 
- TYPE_AND
 
- TYPE_AND_DATA_SIZE
 
- TYPE_ANY
 
- TYPE_AP
 
- TYPE_APA0
 
- TYPE_APA1
 
- TYPE_ASSOCIATION_REQUEST
 
- TYPE_ATIMDMA
 
- TYPE_ATIO_QUEUE
 
- TYPE_ATTR_DIR
 
- TYPE_AUTH
 
- TYPE_AVAILABLE_EFUSE_BYTES_BANK
 
- TYPE_AVAILABLE_EFUSE_BYTES_TOTAL
 
- TYPE_AVG
 
- TYPE_A_DRIVING
 
- TYPE_A_QUERY_SWITCH_OK
 
- TYPE_A_SWITCH_BUSY
 
- TYPE_Am53CF94
 
- TYPE_B57330V2103
 
- TYPE_B57891S0103
 
- TYPE_BEACON
 
- TYPE_BEACONDMA
 
- TYPE_BEGIN
 
- TYPE_BENIGN_PRI
 
- TYPE_BENIGN_SEC
 
- TYPE_BITMAP
 
- TYPE_BLOCKED
 
- TYPE_BOOL_AND
 
- TYPE_BOOL_OR
 
- TYPE_BSS_AP_ORD
 
- TYPE_BULK
 
- TYPE_BULK_OR_INT
 
- TYPE_BUS_I2C
 
- TYPE_BUS_PCI
 
- TYPE_BUS_PCIe
 
- TYPE_BUS_USB
 
- TYPE_BYTESEQ
 
- TYPE_B_DRIVING
 
- TYPE_B_QUERY_SWITCH_OK
 
- TYPE_B_SWITCH_BUSY
 
- TYPE_CALIBRATION_DATA
 
- TYPE_CARD
 
- TYPE_CARD_VIA686
 
- TYPE_CARD_VIA8233
 
- TYPE_CARD_VIA82XX_MODEM
 
- TYPE_CMD
 
- TYPE_CODE0
 
- TYPE_COLS
 
- TYPE_COMM
 
- TYPE_COMMAND
 
- TYPE_COMPLEX
 
- TYPE_COUNT
 
- TYPE_CRITICAL_PRI
 
- TYPE_CRITICAL_SEC
 
- TYPE_CRQ
 
- TYPE_CSQ
 
- TYPE_CTRL
 
- TYPE_CTRL_FAN1_MASK
 
- TYPE_CTRL_FAN_DIVISION
 
- TYPE_CTRL_FAN_MASK
 
- TYPE_CTRL_FAN_MODE
 
- TYPE_CTRL_FAN_PERIOD
 
- TYPE_CTRL_FAN_TYPE_EN
 
- TYPE_C_DRIVING
 
- TYPE_C_QUERY_SWITCH_OK
 
- TYPE_C_SWITCH_BUSY
 
- TYPE_DATA
 
- TYPE_DD
 
- TYPE_DELBA_RECEIVE
 
- TYPE_DELBA_SENT
 
- TYPE_DELETED
 
- TYPE_DIR
 
- TYPE_DIRECT
 
- TYPE_DIRENTRY
 
- TYPE_DISK
 
- TYPE_DIV1
 
- TYPE_DIV2
 
- TYPE_DM9000A
 
- TYPE_DM9000B
 
- TYPE_DM9000E
 
- TYPE_DNUM
 
- TYPE_DONE
 
- TYPE_DRA7USB2
 
- TYPE_D_DRIVING
 
- TYPE_D_QUERY_SWITCH_OK
 
- TYPE_D_SWITCH_BUSY
 
- TYPE_ED
 
- TYPE_EFUSE_CONTENT_LEN_BANK
 
- TYPE_EFUSE_MAP_LEN
 
- TYPE_EFUSE_MAX_SECTION
 
- TYPE_EFUSE_PROTECT_BYTES_BANK
 
- TYPE_EFUSE_REAL_CONTENT_LEN
 
- TYPE_ENCLOSURE
 
- TYPE_EQ
 
- TYPE_EQ_BIT
 
- TYPE_EQ_DNUM
 
- TYPE_ERASE
 
- TYPE_ERROR
 
- TYPE_ETHER
 
- TYPE_ETH_WORK_MESSAGE_POS
 
- TYPE_EVENT
 
- TYPE_EVT
 
- TYPE_EXTEND
 
- TYPE_EmFAS216
 
- TYPE_FATAL
 
- TYPE_FAULT
 
- TYPE_FILE
 
- TYPE_FIXEDFACTOR
 
- TYPE_FSL
 
- TYPE_G2D_3X
 
- TYPE_G2D_4X
 
- TYPE_GATE
 
- TYPE_GLNA0
 
- TYPE_GLNA1
 
- TYPE_GLNA2
 
- TYPE_GLNA3
 
- TYPE_GLOBAL
 
- TYPE_GMK1
 
- TYPE_GMK2
 
- TYPE_GPA0
 
- TYPE_GPA1
 
- TYPE_GPIO_OUTPUT
 
- TYPE_GRLIB
 
- TYPE_GSM_SPACE
 
- TYPE_GUID
 
- TYPE_HD
 
- TYPE_HERC
 
- TYPE_HERCCOLOR
 
- TYPE_HERCPLUS
 
- TYPE_HS
 
- TYPE_HX
 
- TYPE_I2C0
 
- TYPE_IBSS_STTN_ORD
 
- TYPE_ID
 
- TYPE_INBOUND
 
- TYPE_INDIRECT
 
- TYPE_INST
 
- TYPE_INT
 
- TYPE_INTR
 
- TYPE_INVALID
 
- TYPE_IOACCEL2_CMD
 
- TYPE_IOCB
 
- TYPE_IS
 
- TYPE_ISL1208
 
- TYPE_ISL1209
 
- TYPE_ISL1218
 
- TYPE_ISL1219
 
- TYPE_ISO
 
- TYPE_ISOC
 
- TYPE_LDST
 
- TYPE_LED
 
- TYPE_LINEAR_APIC_EVENT
 
- TYPE_LINEAR_APIC_INST_FETCH
 
- TYPE_LINEAR_APIC_INST_READ
 
- TYPE_LINEAR_APIC_INST_WRITE
 
- TYPE_LINK
 
- TYPE_LOCAL
 
- TYPE_LONGHAUL_V1
 
- TYPE_LONGHAUL_V2
 
- TYPE_LP3974
 
- TYPE_LP3979
 
- TYPE_MAESTRO
 
- TYPE_MAESTRO2
 
- TYPE_MAESTRO2E
 
- TYPE_MAIN
 
- TYPE_MASK
 
- TYPE_MAX
 
- TYPE_MAX77686
 
- TYPE_MAX77693
 
- TYPE_MAX77693_NUM
 
- TYPE_MAX77693_UNKNOWN
 
- TYPE_MAX77802
 
- TYPE_MAX77843
 
- TYPE_MAX8966
 
- TYPE_MAX8997
 
- TYPE_MAX8998
 
- TYPE_MAXRD
 
- TYPE_MAXTD
 
- TYPE_MAXTYPE
 
- TYPE_MAX_CHANNELS
 
- TYPE_MBOX
 
- TYPE_MDA
 
- TYPE_MEDIUM_CHANGER
 
- TYPE_MENLO
 
- TYPE_MMC
 
- TYPE_MMS114
 
- TYPE_MMS152
 
- TYPE_MOD
 
- TYPE_MOV_FROM_DR
 
- TYPE_MOV_TO_DR
 
- TYPE_MPC5121
 
- TYPE_MPC5125
 
- TYPE_MS
 
- TYPE_MSG
 
- TYPE_MSK
 
- TYPE_MSP7120
 
- TYPE_MSP7130
 
- TYPE_MSPRO
 
- TYPE_MUX
 
- TYPE_NAKED_ADDR
 
- TYPE_NAKED_CMD
 
- TYPE_NAME_LENGTH
 
- TYPE_NAME_POINTER
 
- TYPE_NCPXXWB473
 
- TYPE_NCPXXWF104
 
- TYPE_NCPXXWL333
 
- TYPE_NCPXXXH103
 
- TYPE_NCR53C90
 
- TYPE_NCR53C90A
 
- TYPE_NCR53C9x
 
- TYPE_ND
 
- TYPE_NETSEC_SKB
 
- TYPE_NETSEC_XDP_NDO
 
- TYPE_NETSEC_XDP_TX
 
- TYPE_NOAVG
 
- TYPE_NODEV
 
- TYPE_NONE
 
- TYPE_NON_FATAL
 
- TYPE_NORMAL
 
- TYPE_NO_LUN
 
- TYPE_NUMBER
 
- TYPE_NUMBER_RANGE
 
- TYPE_OCORES
 
- TYPE_OFFSET
 
- TYPE_ONE_POINT_TRIMMING
 
- TYPE_ONE_POINT_TRIMMING_25
 
- TYPE_ONE_POINT_TRIMMING_85
 
- TYPE_OR
 
- TYPE_OSD
 
- TYPE_OTHER
 
- TYPE_OUTBOUND
 
- TYPE_PADDING
 
- TYPE_PCI1730
 
- TYPE_PCI1733
 
- TYPE_PCI1734
 
- TYPE_PCI1735
 
- TYPE_PCI1736
 
- TYPE_PCI1739
 
- TYPE_PCI1750
 
- TYPE_PCI1751
 
- TYPE_PCI1752
 
- TYPE_PCI1753
 
- TYPE_PCI1753E
 
- TYPE_PCI1754
 
- TYPE_PCI1756
 
- TYPE_PCI1761
 
- TYPE_PCI1762
 
- TYPE_PCMCIA
 
- TYPE_PHYSICAL_APIC_EVENT
 
- TYPE_PHYSICAL_APIC_INST
 
- TYPE_PI
 
- TYPE_PI2
 
- TYPE_PLL
 
- TYPE_PMK1
 
- TYPE_POWERSAVER
 
- TYPE_PRINTER
 
- TYPE_PROCESSOR
 
- TYPE_PV88080_AA
 
- TYPE_PV88080_BA
 
- TYPE_QLFAS216
 
- TYPE_QUEUE
 
- TYPE_RAID
 
- TYPE_RAW_BEACON_ENTRY
 
- TYPE_RBC
 
- TYPE_READ
 
- TYPE_READ_ID
 
- TYPE_REASSOCIATION_REQUEST
 
- TYPE_REF
 
- TYPE_REQUEST_QUEUE
 
- TYPE_RESERVED
 
- TYPE_RESET
 
- TYPE_RESPONSE_QUEUE
 
- TYPE_RFKILL
 
- TYPE_ROGUE_AP_DATA
 
- TYPE_ROM
 
- TYPE_RT8973A
 
- TYPE_RUNNING
 
- TYPE_RXDMA0
 
- TYPE_RXDMA1
 
- TYPE_RXPD
 
- TYPE_S3C2410
 
- TYPE_S3C2412
 
- TYPE_S3C2440
 
- TYPE_S3C6400
 
- TYPE_S3C6410
 
- TYPE_S3C64XX
 
- TYPE_S5
 
- TYPE_S5PC110
 
- TYPE_S5PV210
 
- TYPE_SCANNER
 
- TYPE_SCTP_ABORT
 
- TYPE_SCTP_ASCONF
 
- TYPE_SCTP_ASCONF_ACK
 
- TYPE_SCTP_AUTH
 
- TYPE_SCTP_COOKIE_ACK
 
- TYPE_SCTP_COOKIE_ECHO
 
- TYPE_SCTP_DATA
 
- TYPE_SCTP_ECN_CWR
 
- TYPE_SCTP_ECN_ECNE
 
- TYPE_SCTP_ERROR
 
- TYPE_SCTP_EVENT_TIMEOUT_AUTOCLOSE
 
- TYPE_SCTP_EVENT_TIMEOUT_HEARTBEAT
 
- TYPE_SCTP_EVENT_TIMEOUT_NONE
 
- TYPE_SCTP_EVENT_TIMEOUT_RECONF
 
- TYPE_SCTP_EVENT_TIMEOUT_SACK
 
- TYPE_SCTP_EVENT_TIMEOUT_T1_COOKIE
 
- TYPE_SCTP_EVENT_TIMEOUT_T1_INIT
 
- TYPE_SCTP_EVENT_TIMEOUT_T2_SHUTDOWN
 
- TYPE_SCTP_EVENT_TIMEOUT_T3_RTX
 
- TYPE_SCTP_EVENT_TIMEOUT_T4_RTO
 
- TYPE_SCTP_EVENT_TIMEOUT_T5_SHUTDOWN_GUARD
 
- TYPE_SCTP_FUNC
 
- TYPE_SCTP_FWD_TSN
 
- TYPE_SCTP_HEARTBEAT
 
- TYPE_SCTP_HEARTBEAT_ACK
 
- TYPE_SCTP_INIT
 
- TYPE_SCTP_INIT_ACK
 
- TYPE_SCTP_OTHER_ICMP_PROTO_UNREACH
 
- TYPE_SCTP_OTHER_NO_PENDING_TSN
 
- TYPE_SCTP_PRIMITIVE_ABORT
 
- TYPE_SCTP_PRIMITIVE_ASCONF
 
- TYPE_SCTP_PRIMITIVE_ASSOCIATE
 
- TYPE_SCTP_PRIMITIVE_RECONF
 
- TYPE_SCTP_PRIMITIVE_REQUESTHEARTBEAT
 
- TYPE_SCTP_PRIMITIVE_SEND
 
- TYPE_SCTP_PRIMITIVE_SHUTDOWN
 
- TYPE_SCTP_RECONF
 
- TYPE_SCTP_SACK
 
- TYPE_SCTP_SHUTDOWN
 
- TYPE_SCTP_SHUTDOWN_ACK
 
- TYPE_SCTP_SHUTDOWN_COMPLETE
 
- TYPE_SD
 
- TYPE_SECOND_GEN
 
- TYPE_SHIFT
 
- TYPE_SHT
 
- TYPE_SIFIVE_REV0
 
- TYPE_SM5502
 
- TYPE_SRAM
 
- TYPE_SRB
 
- TYPE_STA
 
- TYPE_STATUS
 
- TYPE_STAT_DATA
 
- TYPE_STOP_MARKER
 
- TYPE_STREAM
 
- TYPE_STRING
 
- TYPE_SWAP
 
- TYPE_SWEEP_ORD
 
- TYPE_SWPB
 
- TYPE_SYMLINK
 
- TYPE_SYNCDMA
 
- TYPE_TAPE
 
- TYPE_TGT_CMD
 
- TYPE_TGT_TMCMD
 
- TYPE_TWIN
 
- TYPE_TWO_POINT_TRIMMING
 
- TYPE_TXDMA0
 
- TYPE_UINT16
 
- TYPE_UINT32
 
- TYPE_UINT64
 
- TYPE_UINT8
 
- TYPE_UNKNOWN
 
- TYPE_UNUSED
 
- TYPE_UPCASE
 
- TYPE_USB1
 
- TYPE_USB2
 
- TYPE_USERSPACE
 
- TYPE_VALUE_LIST
 
- TYPE_VIA686
 
- TYPE_VIA8233
 
- TYPE_VIA8233A
 
- TYPE_VOLUME
 
- TYPE_WAITING
 
- TYPE_WLUN
 
- TYPE_WORM
 
- TYPE_WRITE
 
- TYPE_ZBC
 
- TYPHOON_BOOTCMD_BOOT
 
- TYPHOON_BOOTCMD_DNLD_COMPLETE
 
- TYPHOON_BOOTCMD_REG_BOOT_RECORD
 
- TYPHOON_BOOTCMD_RUNTIME_IMAGE
 
- TYPHOON_BOOTCMD_SEG_AVAILABLE
 
- TYPHOON_BOOTCMD_WAKEUP
 
- TYPHOON_BSVR
 
- TYPHOON_CMD_CREATE_SA
 
- TYPHOON_CMD_DELETE_SA
 
- TYPHOON_CMD_DESC
 
- TYPHOON_CMD_ENABLE_WAKE_EVENTS
 
- TYPHOON_CMD_GET_CMD_LVL
 
- TYPHOON_CMD_GET_IPSEC_ENABLE
 
- TYPHOON_CMD_GOTO_SLEEP
 
- TYPHOON_CMD_HALT
 
- TYPHOON_CMD_HELLO_RESP
 
- TYPHOON_CMD_IRQ_COALESCE_CTRL
 
- TYPHOON_CMD_READ_IPSEC_INFO
 
- TYPHOON_CMD_READ_MAC_ADDRESS
 
- TYPHOON_CMD_READ_MEDIA_STATUS
 
- TYPHOON_CMD_READ_STATS
 
- TYPHOON_CMD_READ_VERSIONS
 
- TYPHOON_CMD_RESPOND
 
- TYPHOON_CMD_RX_DISABLE
 
- TYPHOON_CMD_RX_ENABLE
 
- TYPHOON_CMD_SET_MAC_ADDRESS
 
- TYPHOON_CMD_SET_MAX_PKT_SIZE
 
- TYPHOON_CMD_SET_MULTICAST_HASH
 
- TYPHOON_CMD_SET_OFFLOAD_TASKS
 
- TYPHOON_CMD_SET_RX_FILTER
 
- TYPHOON_CMD_TX_DISABLE
 
- TYPHOON_CMD_TX_ENABLE
 
- TYPHOON_CMD_VLAN_TYPE_WRITE
 
- TYPHOON_CMD_XCVR_SELECT
 
- TYPHOON_CRYPTO_3DES
 
- TYPHOON_CRYPTO_DES
 
- TYPHOON_CRYPTO_NONE
 
- TYPHOON_CRYPTO_VARIABLE
 
- TYPHOON_DESC_VALID
 
- TYPHOON_FIBER
 
- TYPHOON_FRAG_DESC
 
- TYPHOON_FX95
 
- TYPHOON_FX95SVR
 
- TYPHOON_FX97
 
- TYPHOON_FX97SVR
 
- TYPHOON_FXM
 
- TYPHOON_INTR_ALL
 
- TYPHOON_INTR_ARM2HOST0
 
- TYPHOON_INTR_ARM2HOST1
 
- TYPHOON_INTR_ARM2HOST2
 
- TYPHOON_INTR_ARM2HOST3
 
- TYPHOON_INTR_BOOTCMD
 
- TYPHOON_INTR_DMA0
 
- TYPHOON_INTR_DMA1
 
- TYPHOON_INTR_DMA2
 
- TYPHOON_INTR_DMA3
 
- TYPHOON_INTR_ENABLE_ALL
 
- TYPHOON_INTR_HOST_INT
 
- TYPHOON_INTR_MASTER_ABORT
 
- TYPHOON_INTR_NONE
 
- TYPHOON_INTR_RESERVED
 
- TYPHOON_INTR_SELF
 
- TYPHOON_INTR_TARGET_ABORT
 
- TYPHOON_IPSEC_GEN_IV
 
- TYPHOON_IPSEC_USE_IV
 
- TYPHOON_LINK_100MBPS
 
- TYPHOON_LINK_10MBPS
 
- TYPHOON_LINK_BAD
 
- TYPHOON_LINK_DUPLEX_MASK
 
- TYPHOON_LINK_FULL_DUPLEX
 
- TYPHOON_LINK_GOOD
 
- TYPHOON_LINK_HALF_DUPLEX
 
- TYPHOON_LINK_SPEED_MASK
 
- TYPHOON_LINK_STAT_MASK
 
- TYPHOON_MAX
 
- TYPHOON_MCAST_HASH_DISABLE
 
- TYPHOON_MCAST_HASH_ENABLE
 
- TYPHOON_MCAST_HASH_SET
 
- TYPHOON_MEDIA_STAT_CARRIER_SENSE
 
- TYPHOON_MEDIA_STAT_COLLISION_DETECT
 
- TYPHOON_MEDIA_STAT_CRC_STRIP_DISABLE
 
- TYPHOON_MEDIA_STAT_NO_LINK
 
- TYPHOON_MEDIA_STAT_POLARITY_REV
 
- TYPHOON_OFFLOAD_BCAST_THROTTLE
 
- TYPHOON_OFFLOAD_DHCP_PREVENT
 
- TYPHOON_OFFLOAD_FILTERING
 
- TYPHOON_OFFLOAD_IPSEC
 
- TYPHOON_OFFLOAD_IP_CHKSUM
 
- TYPHOON_OFFLOAD_TCP_CHKSUM
 
- TYPHOON_OFFLOAD_TCP_SEGMENT
 
- TYPHOON_OFFLOAD_UDP_CHKSUM
 
- TYPHOON_OFFLOAD_VLAN
 
- TYPHOON_OPT_DESC
 
- TYPHOON_OPT_IPSEC
 
- TYPHOON_OPT_TCP_SEG
 
- TYPHOON_OPT_TYPE_MASK
 
- TYPHOON_REG_ARM2HOST0
 
- TYPHOON_REG_ARM2HOST1
 
- TYPHOON_REG_ARM2HOST2
 
- TYPHOON_REG_ARM2HOST3
 
- TYPHOON_REG_BOOT_CHECKSUM
 
- TYPHOON_REG_BOOT_DATA_HI
 
- TYPHOON_REG_BOOT_DATA_LO
 
- TYPHOON_REG_BOOT_DEST_ADDR
 
- TYPHOON_REG_BOOT_LENGTH
 
- TYPHOON_REG_BOOT_RECORD_ADDR_HI
 
- TYPHOON_REG_BOOT_RECORD_ADDR_LO
 
- TYPHOON_REG_CMD_READY
 
- TYPHOON_REG_COMMAND
 
- TYPHOON_REG_DOWNLOAD_BOOT_ADDR
 
- TYPHOON_REG_DOWNLOAD_HMAC_0
 
- TYPHOON_REG_DOWNLOAD_HMAC_1
 
- TYPHOON_REG_DOWNLOAD_HMAC_2
 
- TYPHOON_REG_DOWNLOAD_HMAC_3
 
- TYPHOON_REG_DOWNLOAD_HMAC_4
 
- TYPHOON_REG_HEARTBEAT
 
- TYPHOON_REG_HOST2ARM0
 
- TYPHOON_REG_HOST2ARM1
 
- TYPHOON_REG_HOST2ARM2
 
- TYPHOON_REG_HOST2ARM3
 
- TYPHOON_REG_HOST2ARM4
 
- TYPHOON_REG_HOST2ARM5
 
- TYPHOON_REG_HOST2ARM6
 
- TYPHOON_REG_HOST2ARM7
 
- TYPHOON_REG_INTR_ENABLE
 
- TYPHOON_REG_INTR_MASK
 
- TYPHOON_REG_INTR_STATUS
 
- TYPHOON_REG_SELF_INTERRUPT
 
- TYPHOON_REG_SOFT_RESET
 
- TYPHOON_REG_STATUS
 
- TYPHOON_REG_TX_HI_READY
 
- TYPHOON_REG_TX_LO_READY
 
- TYPHOON_RESET_ALL
 
- TYPHOON_RESET_NONE
 
- TYPHOON_RESET_TIMEOUT_NOSLEEP
 
- TYPHOON_RESET_TIMEOUT_SLEEP
 
- TYPHOON_RESP_DESC
 
- TYPHOON_RESP_ERROR
 
- TYPHOON_RX_DESC
 
- TYPHOON_RX_ERROR
 
- TYPHOON_RX_ERR_ALIGN
 
- TYPHOON_RX_ERR_BAD_SSD
 
- TYPHOON_RX_ERR_CRC
 
- TYPHOON_RX_ERR_DRIBBLE
 
- TYPHOON_RX_ERR_FIFO_UNDERRUN
 
- TYPHOON_RX_ERR_INTERNAL
 
- TYPHOON_RX_ERR_OVERSIZE
 
- TYPHOON_RX_ERR_RUNT
 
- TYPHOON_RX_ESP_FORMAT_ERR
 
- TYPHOON_RX_FILTERED
 
- TYPHOON_RX_FILTER_ALL_MCAST
 
- TYPHOON_RX_FILTER_BROADCAST
 
- TYPHOON_RX_FILTER_DIRECTED
 
- TYPHOON_RX_FILTER_MASK
 
- TYPHOON_RX_FILTER_MCAST_HASH
 
- TYPHOON_RX_FILTER_PROMISCOUS
 
- TYPHOON_RX_INNER_AH_FAIL
 
- TYPHOON_RX_INNER_AH_GOOD
 
- TYPHOON_RX_INNER_ESP_FAIL
 
- TYPHOON_RX_INNER_ESP_GOOD
 
- TYPHOON_RX_IPSEC
 
- TYPHOON_RX_IP_CHK_FAIL
 
- TYPHOON_RX_IP_CHK_GOOD
 
- TYPHOON_RX_IP_FRAG
 
- TYPHOON_RX_OUTER_AH_FAIL
 
- TYPHOON_RX_OUTER_AH_GOOD
 
- TYPHOON_RX_OUTER_ESP_FAIL
 
- TYPHOON_RX_OUTER_ESP_GOOD
 
- TYPHOON_RX_PROTO_IP
 
- TYPHOON_RX_PROTO_IPX
 
- TYPHOON_RX_PROTO_MASK
 
- TYPHOON_RX_PROTO_UNKNOWN
 
- TYPHOON_RX_TCP_CHK_FAIL
 
- TYPHOON_RX_TCP_CHK_GOOD
 
- TYPHOON_RX_UDP_CHK_FAIL
 
- TYPHOON_RX_UDP_CHK_GOOD
 
- TYPHOON_RX_UNKNOWN_SA
 
- TYPHOON_RX_VLAN
 
- TYPHOON_SA_DIR_RX
 
- TYPHOON_SA_DIR_TX
 
- TYPHOON_SA_ENCRYPT_3DES
 
- TYPHOON_SA_ENCRYPT_3DES_2KEY
 
- TYPHOON_SA_ENCRYPT_3DES_3KEY
 
- TYPHOON_SA_ENCRYPT_CBC
 
- TYPHOON_SA_ENCRYPT_DES
 
- TYPHOON_SA_ENCRYPT_ECB
 
- TYPHOON_SA_ENCRYPT_ENABLE
 
- TYPHOON_SA_GENERATE_INDEX
 
- TYPHOON_SA_HASH_ENABLE
 
- TYPHOON_SA_HASH_MD5
 
- TYPHOON_SA_HASH_SHA1
 
- TYPHOON_SA_MODE_AH
 
- TYPHOON_SA_MODE_ESP
 
- TYPHOON_SA_MODE_NULL
 
- TYPHOON_SA_SPECIFY_INDEX
 
- TYPHOON_STATUS_HALTED
 
- TYPHOON_STATUS_RUNNING
 
- TYPHOON_STATUS_SECOND_INIT
 
- TYPHOON_STATUS_SLEEPING
 
- TYPHOON_STATUS_WAITING_FOR_BOOT
 
- TYPHOON_STATUS_WAITING_FOR_HOST
 
- TYPHOON_STATUS_WAITING_FOR_SEGMENT
 
- TYPHOON_SVR
 
- TYPHOON_SVR95
 
- TYPHOON_SVR97
 
- TYPHOON_TSO_FIRST
 
- TYPHOON_TSO_LAST
 
- TYPHOON_TX
 
- TYPHOON_TX95
 
- TYPHOON_TX97
 
- TYPHOON_TXM
 
- TYPHOON_TX_DESC
 
- TYPHOON_TX_PF_INSERT_VLAN
 
- TYPHOON_TX_PF_INTERNAL
 
- TYPHOON_TX_PF_IPSEC
 
- TYPHOON_TX_PF_IP_CHKSUM
 
- TYPHOON_TX_PF_NO_CRC
 
- TYPHOON_TX_PF_PAD_FRAME
 
- TYPHOON_TX_PF_RESERVED
 
- TYPHOON_TX_PF_TCP_CHKSUM
 
- TYPHOON_TX_PF_TCP_SEGMENT
 
- TYPHOON_TX_PF_UDP_CHKSUM
 
- TYPHOON_TX_PF_VLAN_MASK
 
- TYPHOON_TX_PF_VLAN_PRIORITY
 
- TYPHOON_TX_PF_VLAN_TAG_SHIFT
 
- TYPHOON_TYPE_MASK
 
- TYPHOON_UDELAY
 
- TYPHOON_WAIT_TIMEOUT
 
- TYPHOON_WAKEUP_NEEDS_RESET
 
- TYPHOON_WAKE_ARP
 
- TYPHOON_WAKE_ICMP_ECHO
 
- TYPHOON_WAKE_LINK_EVENT
 
- TYPHOON_WAKE_MAGIC_PKT
 
- TYPHOON_XCVR_100FULL
 
- TYPHOON_XCVR_100HALF
 
- TYPHOON_XCVR_10FULL
 
- TYPHOON_XCVR_10HALF
 
- TYPHOON_XCVR_AUTONEG
 
- TYP_4S
 
- TYP_8S
 
- TYP_ACK_FROM_PC
 
- TYP_E1
 
- TZC1
 
- TZC2
 
- TZIC_DSMINT
 
- TZIC_ENCLEAR0
 
- TZIC_ENSET0
 
- TZIC_HIPND
 
- TZIC_ID0
 
- TZIC_IMPID
 
- TZIC_INTCNTL
 
- TZIC_INTSEC0
 
- TZIC_INTTYPE
 
- TZIC_NUM_IRQS
 
- TZIC_PND0
 
- TZIC_PRIOMASK
 
- TZIC_PRIORITY0
 
- TZIC_SRCCLAR0
 
- TZIC_SRCSET0
 
- TZIC_SWINT
 
- TZIC_SYNCCTRL
 
- TZIC_WAKEUP0
 
- TZONE
 
- TZONE_RECORD_SIZE
 
- TZONE_TYPE_ACPI
 
- TZONE_TYPE_NR
 
- TZONE_TYPE_PCH
 
- TZPC
 
- TZ_LEFT_ALIGN
 
- T_0_15
 
- T_100MSEC
 
- T_10MSEC
 
- T_16_19
 
- T_1SEC
 
- T_20MSEC
 
- T_20_39
 
- T_40MSEC
 
- T_40_59
 
- T_500MSEC
 
- T_50MSEC
 
- T_60_79
 
- T_A
 
- T_ACQ
 
- T_ACTS_TPL_BASE
 
- T_ANALOG_TV
 
- T_A_AIDL_BDIS
 
- T_A_BIDL_ADIS
 
- T_A_DRV_RSM
 
- T_A_SRP_RSPNS
 
- T_A_WAIT_BCON
 
- T_A_WAIT_VRISE
 
- T_BA_TPL_BASE
 
- T_BCN0_TPL_BASE
 
- T_BCN1_TPL_BASE
 
- T_BC_LVL_DEBOUNCE_DELAY_MS
 
- T_BUF_SIZE
 
- T_B_ASE0_BRST
 
- T_B_DATA_PLS
 
- T_B_SE0_SRP
 
- T_B_SRP_FAIL
 
- T_B_SRP_INIT
 
- T_CKESR_MASK
 
- T_CKESR_SHIFT
 
- T_CKE_MASK
 
- T_CKE_SHIFT
 
- T_CLASSIC
 
- T_CM
 
- T_CNF
 
- T_COMMIT
 
- T_COMMIT_CALLBACK
 
- T_COMMIT_DFLUSH
 
- T_COMMIT_JFLUSH
 
- T_CONNECTIONSTATE
 
- T_CORE_BITS
 
- T_CORE_VAL
 
- T_CPORTFLAGS
 
- T_CPORTMODE
 
- T_CPU1_HV_REG
 
- T_CREDITSTOSEND
 
- T_CSL
 
- T_CSTA_MASK
 
- T_CSTA_SHIFT
 
- T_CT
 
- T_CT_S
 
- T_DATA
 
- T_DEF
 
- T_ERRORS_REPORT
 
- T_ETH_INDIRECTION_TABLE_SIZE
 
- T_ETH_MAC_COMMAND_INVALIDATE
 
- T_ETH_MAC_COMMAND_SET
 
- T_ETH_PACKET_ACTION_GFT_EVENTID
 
- T_ETH_PACKET_MATCH_RFS_EVENTID
 
- T_ETH_RSS_KEY
 
- T_ETH_RSS_KEY_SIZE
 
- T_EXDEF
 
- T_FAIR_COEF
 
- T_FAULT_RECOVER
 
- T_FCOE_NUMBER_OF_CACHED_T2_ENTRIES
 
- T_FINISHED
 
- T_FLUSH
 
- T_F_FWD
 
- T_HB
 
- T_HOLD
 
- T_HOST_REQ_POLL
 
- T_HPOWER_LEVEL
 
- T_HS_EXIT
 
- T_HS_PREP
 
- T_HS_TRAIL
 
- T_HS_ZERO
 
- T_I
 
- T_INIT_JIFFIES
 
- T_I_S
 
- T_L
 
- T_LC
 
- T_LIST
 
- T_LOCALBUFFERSPACE
 
- T_LOCKED
 
- T_LPX
 
- T_LSP
 
- T_L_S
 
- T_MASK
 
- T_MEM_BITS
 
- T_MEM_VAL
 
- T_NAK
 
- T_NEO
 
- T_NS
 
- T_NULL
 
- T_NULL_TPL_BASE
 
- T_NUMCPORTS
 
- T_NUMTESTFEATURES
 
- T_ODT_MASK
 
- T_ODT_SHIFT
 
- T_ONLINE
 
- T_OWN
 
- T_P
 
- T_PAD
 
- T_PCIBUS
 
- T_PDLL_UL_MASK
 
- T_PDLL_UL_SHIFT
 
- T_PEERBUFFERSPACE
 
- T_PEERCPORTID
 
- T_PEERDEVICEID
 
- T_PHY_RESET_MS
 
- T_PID
 
- T_PID_DATA0
 
- T_PID_DATA1
 
- T_PID_SHIFT
 
- T_PLAY
 
- T_PROBE_INIT
 
- T_PROBE_RETRY
 
- T_PROTOCOLID
 
- T_PRS_TPL_BASE
 
- T_QNULL_TPL_BASE
 
- T_R
 
- T_RADIO
 
- T_RAM_ACCESS_SZ
 
- T_RAS_MASK
 
- T_RAS_MAX_MASK
 
- T_RAS_MAX_SHIFT
 
- T_RAS_SHIFT
 
- T_RC
 
- T_RCD_MASK
 
- T_RCD_SHIFT
 
- T_RC_MASK
 
- T_RC_SHIFT
 
- T_REC
 
- T_RECORD
 
- T_REFI_15_6
 
- T_REFI_3_9
 
- T_REFI_7_8
 
- T_REG_32
 
- T_REG_64
 
- T_REMDEV
 
- T_REMDEVALL
 
- T_REQUEST_TAG
 
- T_RESET_US
 
- T_REW
 
- T_RFC_110
 
- T_RFC_130
 
- T_RFC_160
 
- T_RFC_210
 
- T_RFC_300
 
- T_RFC_350
 
- T_RFC_90
 
- T_RFC_MASK
 
- T_RFC_SHIFT
 
- T_RISEFALL
 
- T_RL
 
- T_RP_MASK
 
- T_RP_SHIFT
 
- T_RRD_MASK
 
- T_RRD_SHIFT
 
- T_RR_TPL_BASE
 
- T_RTP_MASK
 
- T_RTP_SHIFT
 
- T_RTW_MASK
 
- T_RTW_SHIFT
 
- T_RUN
 
- T_RUNNING
 
- T_RXTOKENVALUE
 
- T_R_S
 
- T_SATA0_AHCI_HBA_CAP_BKDR
 
- T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP
 
- T_SATA0_AHCI_HBA_CAP_BKDR_SALP
 
- T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP
 
- T_SATA0_AHCI_HBA_CAP_BKDR_SNCQ
 
- T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM
 
- T_SATA0_AHCI_IDP1
 
- T_SATA0_AHCI_IDP1_DATA
 
- T_SATA0_BKDOOR_CC
 
- T_SATA0_BKDOOR_CC_CLASS_CODE
 
- T_SATA0_BKDOOR_CC_CLASS_CODE_MASK
 
- T_SATA0_BKDOOR_CC_PROG_IF
 
- T_SATA0_BKDOOR_CC_PROG_IF_MASK
 
- T_SATA0_CFG2NVOOB_2
 
- T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW
 
- T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK
 
- T_SATA0_CFG_1
 
- T_SATA0_CFG_1_BUS_MASTER
 
- T_SATA0_CFG_1_IO_SPACE
 
- T_SATA0_CFG_1_MEMORY_SPACE
 
- T_SATA0_CFG_1_SERR
 
- T_SATA0_CFG_35
 
- T_SATA0_CFG_35_IDP_INDEX
 
- T_SATA0_CFG_35_IDP_INDEX_MASK
 
- T_SATA0_CFG_9
 
- T_SATA0_CFG_9_BASE_ADDRESS
 
- T_SATA0_CFG_MISC
 
- T_SATA0_CFG_PHY_1
 
- T_SATA0_CFG_PHY_1_PADS_IDDQ_EN
 
- T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN
 
- T_SATA0_CFG_SATA
 
- T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN
 
- T_SATA0_CHX_PHY_CTRL11
 
- T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ
 
- T_SATA0_CHX_PHY_CTRL17_0
 
- T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1
 
- T_SATA0_CHX_PHY_CTRL18_0
 
- T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2
 
- T_SATA0_CHX_PHY_CTRL1_GEN1
 
- T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK
 
- T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT
 
- T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK
 
- T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT
 
- T_SATA0_CHX_PHY_CTRL1_GEN2
 
- T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK
 
- T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT
 
- T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK
 
- T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT
 
- T_SATA0_CHX_PHY_CTRL2
 
- T_SATA0_CHX_PHY_CTRL20_0
 
- T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1
 
- T_SATA0_CHX_PHY_CTRL21_0
 
- T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2
 
- T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1
 
- T_SATA0_INDEX
 
- T_SATA0_NVOOB
 
- T_SATA0_NVOOB_COMMA_CNT
 
- T_SATA0_NVOOB_COMMA_CNT_MASK
 
- T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH
 
- T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK
 
- T_SATA0_NVOOB_SQUELCH_FILTER_MODE
 
- T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK
 
- T_SATA_CFG_PHY_0
 
- T_SATA_CFG_PHY_0_MASK_SQUELCH
 
- T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD
 
- T_SEL
 
- T_SHORT
 
- T_SOLO
 
- T_SRC_CBUS_DEGLITCH
 
- T_SRC_CBUS_FLOAT
 
- T_SRC_RXSENSE_DEGLITCH
 
- T_SRC_VBUS_CBUS_TO_STABLE
 
- T_STAL
 
- T_START
 
- T_STOP
 
- T_SW
 
- T_SWITCH
 
- T_TC
 
- T_TC0TXMAXSDUSIZE
 
- T_TC1TXMAXSDUSIZE
 
- T_TC_S
 
- T_TDQSCKMAX_MASK
 
- T_TDQSCKMAX_SHIFT
 
- T_TIMEOUT
 
- T_TM_S
 
- T_TO
 
- T_TRAFFICCLASS
 
- T_TXTOKENVALUE
 
- T_TX_FIFO_TXRAM_BASE
 
- T_UN
 
- T_UN_S
 
- T_VID
 
- T_W
 
- T_WR_MASK
 
- T_WR_SHIFT
 
- T_WTR_MASK
 
- T_WTR_SHIFT
 
- T_W_S
 
- T_XP_MASK
 
- T_XP_SHIFT
 
- T_XRI_TAG
 
- T_XSNR_MASK
 
- T_XSNR_SHIFT
 
- T_XSRD_MASK
 
- T_XSRD_SHIFT
 
- T_X_INC
 
- T_Y_INC
 
- T_ZQCL_DEFAULT_NS
 
- T_ZQCS_DEFAULT_NS
 
- T_ZQINIT_DEFAULT_NS
 
- T_ZQ_DDRMODE_MASK
 
- T_ZQ_OFST
 
- TakeABreakPt
 
- TapeController
 
- TapePeripheral
 
- TargetAssistExtRequest_t
 
- TargetAssistRequest_t
 
- TargetCmdBufferPostBaseListReply_t
 
- TargetCmdBufferPostBaseRequest_t
 
- TargetCmdBufferPostErrorReply_t
 
- TargetCmdBufferPostListRequest_t
 
- TargetCmdBufferPostReply_t
 
- TargetCmdBufferPostRequest_t
 
- TargetErr
 
- TargetErrorReply_t
 
- TargetModeAbortReply_t
 
- TargetModeAbort_t
 
- TargetScsiSpiStatusIU_t
 
- TargetStatusSendRequest_t
 
- Tbit
 
- Tekram_nvram
 
- Tekram_target
 
- TermProfile
 
- TerminalPeripheral
 
- TestAdapterCommand
 
- TestClearPageDoubleMap
 
- TestClearPageFsCache
 
- TestCommandResponse
 
- TestD0
 
- TestD4
 
- TestD8
 
- TestSetPageDoubleMap
 
- TestSetPageFsCache
 
- TextModeIndex
 
- Thermal
 
- ThermalMeterVal
 
- ThermometerRead
 
- ThreeComHomeConnectLite
 
- ThreeDramMemType
 
- ThreshA1_in
 
- ThreshA1_out
 
- ThreshA2_in
 
- ThreshA2_out
 
- Ti3026_calcclock
 
- Ti3026_init
 
- Ti3026_preinit
 
- Ti3026_reset
 
- Ti3026_restore
 
- Ti3026_setpclk
 
- TileSplit
 
- TileType
 
- TimeOut
 
- TimeStamp
 
- Timer
 
- Timer10X
 
- TimerInt
 
- TimerIntr
 
- Timer_10ms
 
- Timer_2
 
- Timercnt
 
- Timeup
 
- Timon_table_entry
 
- TlSetupRebootMsgAck
 
- Tms
 
- Tn_32MODE_CNF_MASK
 
- Tn_FSB_EN_CNF_MASK
 
- Tn_FSB_EN_CNF_SHIFT
 
- Tn_FSB_INT_ADDR_MASK
 
- Tn_FSB_INT_ADDR_SHIFT
 
- Tn_FSB_INT_DELCAP_MASK
 
- Tn_FSB_INT_DELCAP_SHIFT
 
- Tn_FSB_INT_VAL_MASK
 
- Tn_INT_ENB_CNF_MASK
 
- Tn_INT_ROUTE_CAP_MASK
 
- Tn_INT_ROUTE_CAP_SHIFT
 
- Tn_INT_ROUTE_CNF_MASK
 
- Tn_INT_ROUTE_CNF_SHIFT
 
- Tn_INT_TYPE_CNF_MASK
 
- Tn_PER_INT_CAP_MASK
 
- Tn_SIZE_CAP_MASK
 
- Tn_TYPE_CNF_MASK
 
- Tn_VAL_SET_CNF_MASK
 
- Tnco01
 
- Tnco02
 
- Tnco03
 
- Tom2Enabled
 
- Tom2ForceMemTypeWB
 
- ToolboxBeaconRequest_t
 
- ToolboxCleanRequest_t
 
- ToolboxDiagDataUploadRequest_t
 
- ToolboxFcManageRequest_t
 
- ToolboxIstwiReadWriteRequest_t
 
- ToolboxMemMoveRequest_t
 
- ToolboxReply_t
 
- ToptroIndus
 
- TotalReset
 
- Total_ports
 
- Trace
 
- Tracec
 
- Tracecv
 
- Tracev
 
- Tracevv
 
- TransTable_struct
 
- TransceiverA_HSPI_Readback
 
- TransceiverB_HSPI_Readback
 
- TranslateRxSignalStuff819xUsb
 
- Transmit
 
- TransmitPacket
 
- TransportAddress
 
- TransportAddress_ip6Address
 
- TransportAddress_ipAddress
 
- TriggerRFThermalMeter
 
- TrueCModeIndex
 
- TruncToValidBPP
 
- TsAddBaProcess
 
- TsInactTimeout
 
- TsInitAddBA
 
- TsInitDelBA
 
- TsSetupTimeOut
 
- TsStartAddBaProcess
 
- Tssi_Mea_Value
 
- Tssi_Report_Value1
 
- Tssi_Report_Value2
 
- Tsunami
 
- TunerControl
 
- TunerReg
 
- Tuner_Power_OFF
 
- Tuner_Power_ON
 
- TurboSparc
 
- Twinkle
 
- TwisterParamVals
 
- TwoMemOp
 
- Twoword_add
 
- Twoword_subtract
 
- Tx5
 
- Tx6
 
- Tx7
 
- Tx8
 
- TxATP
 
- TxAborted
 
- TxAddr0
 
- TxAutoPad
 
- TxAvailable
 
- TxBBGainTableLength
 
- TxBaInactTimeout
 
- TxBackoff10
 
- TxBackoff11
 
- TxBackoff12
 
- TxBackoff13
 
- TxBackoff14
 
- TxBackoff15
 
- TxBackoff2
 
- TxBackoff3
 
- TxBackoff4
 
- TxBackoff5
 
- TxBackoff6
 
- TxBackoff7
 
- TxBackoff8
 
- TxBackoff9
 
- TxBranchSel
 
- TxBroadcast
 
- TxBroadcastFramesTransmittedOK
 
- TxBufCount
 
- TxBufOvr
 
- TxCNT0
 
- TxCNT1
 
- TxCRC
 
- TxCRCEn
 
- TxCRC_ENAB
 
- TxCSI
 
- TxCalTCP
 
- TxCareLostCrs
 
- TxCarrierIgn
 
- TxCarrierLost
 
- TxCheckStuck
 
- TxChecksum
 
- TxClearAbt
 
- TxCmd
 
- TxColCntMask
 
- TxColCntShift
 
- TxCollRetry
 
- TxComplIntrStatus
 
- TxComplProducerWrEn
 
- TxComplQAddr32bit
 
- TxComplQAddr64bit
 
- TxComplThreshShift
 
- TxComplete
 
- TxCompletionAddr
 
- TxConfig
 
- TxConfigBits
 
- TxConfig_bits
 
- TxConsumerIdx
 
- TxControl
 
- TxCountToDataRate
 
- TxCsense
 
- TxCtlHdr
 
- TxCtrl
 
- TxCurPtr
 
- TxD
 
- TxDComplete
 
- TxDESC
 
- TxDIS
 
- TxDMABurstSizeShift
 
- TxDMABurstThresh
 
- TxDMAComplete
 
- TxDMACtrl
 
- TxDMAError
 
- TxDMAIndicate
 
- TxDMALateError
 
- TxDMAPollPeriod
 
- TxDMAShift
 
- TxDMAUrgentThresh
 
- TxDRNT
 
- TxDRNT_10
 
- TxDRNT_100
 
- TxDRNT_shift
 
- TxDataRate
 
- TxDefer
 
- TxDeferTimerExp
 
- TxDepth_Reg
 
- TxDesc
 
- TxDescCtrl
 
- TxDescID
 
- TxDescIntr
 
- TxDescQAddr32bit
 
- TxDescQAddr64bit
 
- TxDescSpace128
 
- TxDescSpace256
 
- TxDescSpace32
 
- TxDescSpace64
 
- TxDescSpaceUnlim
 
- TxDescStartAddr
 
- TxDescStartAddrHigh
 
- TxDescStartAddrLow
 
- TxDescType0
 
- TxDescType1
 
- TxDescType2
 
- TxDescType3
 
- TxDescType4
 
- TxDescUnavail
 
- TxDied
 
- TxDisable
 
- TxDmaOkLowDesc
 
- TxDone
 
- TxDrthMask
 
- TxENA
 
- TxENAB
 
- TxENABLE
 
- TxENDPKT_INT
 
- TxEOM
 
- TxEOPError
 
- TxERR
 
- TxEmpty
 
- TxEnable
 
- TxEnabled
 
- TxEnb
 
- TxEnbFCS
 
- TxEnbHuge
 
- TxEnbPad
 
- TxEnbPrem
 
- TxErr
 
- TxErrMask
 
- TxError
 
- TxErrorMask
 
- TxExcessColl
 
- TxExcessCollExp
 
- TxExdCollNum
 
- TxFD
 
- TxFIFOAllSent
 
- TxFIFOEnable
 
- TxFIFOUnder
 
- TxFIFOUnderflow
 
- TxFIFO_LVL
 
- TxFIFO_element
 
- TxFILLT
 
- TxFILLT_shift
 
- TxFid
 
- TxFifo
 
- TxFlowControlEnable
 
- TxFlowCtrl
 
- TxFlowEnable
 
- TxFlthMask
 
- TxFrameId
 
- TxFramesLostDueToInternalMACTransmissionError
 
- TxFramesOK
 
- TxFree
 
- TxFreeThreshold
 
- TxFullDuplex
 
- TxFullDx
 
- TxGFPEnable
 
- TxGfpMem
 
- TxHBI
 
- TxHDescStartAddrHigh
 
- TxHDescStartAddrLow
 
- TxHalt
 
- TxHeartIgn
 
- TxHiPriFIFOThreshShift
 
- TxHighPwrLevel_100
 
- TxHighPwrLevel_15
 
- TxHighPwrLevel_35
 
- TxHighPwrLevel_50
 
- TxHighPwrLevel_70
 
- TxHighPwrLevel_BT1
 
- TxHighPwrLevel_BT2
 
- TxHighPwrLevel_Level1
 
- TxHighPwrLevel_Level2
 
- TxHighPwrLevel_Normal
 
- TxHostOwns
 
- TxHostToFIFO
 
- TxIDLE
 
- TxIFG
 
- TxIFG84
 
- TxIFG88
 
- TxIFG92
 
- TxIFG96
 
- TxIFGShift
 
- TxINT_ENAB
 
- TxIdle
 
- TxIgnoreColl
 
- TxIndicate
 
- TxInterFrameGapShift
 
- TxIntr
 
- TxIntrCtrl
 
- TxIntrSel
 
- TxIntrUploaded
 
- TxJabber
 
- TxJumboFrames
 
- TxJumboFramesReceivedOK
 
- TxJumboOctetsReceivedOK
 
- TxLateColl
 
- TxLateCollExp
 
- TxLimit
 
- TxLinkFail
 
- TxListPtr
 
- TxLoopBack
 
- TxMACEnable
 
- TxMLB
 
- TxMXDMA_shift
 
- TxMacControl
 
- TxMacLoop
 
- TxMaxCol
 
- TxMaxSizeError
 
- TxMode
 
- TxMultiColl
 
- TxMulticast
 
- TxMulticastFramesTransmittedOK
 
- TxMultipleColl
 
- TxMxdmaMask
 
- TxMxdma_128
 
- TxMxdma_16
 
- TxMxdma_256
 
- TxMxdma_32
 
- TxMxdma_4
 
- TxMxdma_512
 
- TxMxdma_64
 
- TxMxdma_8
 
- TxNBITS_MASK
 
- TxN_MASK
 
- TxNccShift
 
- TxNetworkCollExp
 
- TxNeverGiveUp
 
- TxNoBackOff
 
- TxNoBackoff
 
- TxNoBuf
 
- TxNoDMACompletion
 
- TxNoFCS
 
- TxNormalCollExp
 
- TxOK
 
- TxOWC
 
- TxOctetsHigh
 
- TxOctetsLow
 
- TxOctetsTransmittedOK
 
- TxOff
 
- TxOkBytes
 
- TxOn
 
- TxOutBytes
 
- TxOutOfWindow
 
- TxOutputEnable
 
- TxOwn
 
- TxPAUSE
 
- TxPAUSEEND
 
- TxPAUSEMACCtrlFramesTransmitted
 
- TxPD_CONTROL_WDS_FRAME
 
- TxPD_MESH_FRAME
 
- TxPacketMax
 
- TxPadLenShift
 
- TxParityError
 
- TxPause
 
- TxPktPend
 
- TxPoll
 
- TxPoll_8125
 
- TxPowerInfo24G
 
- TxProducerIdx
 
- TxPtr
 
- TxQ0Empty
 
- TxQ0Int
 
- TxQ1Empty
 
- TxQ1Int
 
- TxQed
 
- TxQueued
 
- TxRCMP
 
- TxRESET
 
- TxResGrant
 
- TxReset
 
- TxResetBit
 
- TxResetDone
 
- TxRetryShift
 
- TxRingAddr
 
- TxRingHiAddr
 
- TxRingPtr
 
- TxRingWrap
 
- TxSTAT
 
- TxSingleColl
 
- TxSize1024To1518
 
- TxSize128To255
 
- TxSize1519ToMax
 
- TxSize256To511
 
- TxSize512To1023
 
- TxSize64
 
- TxSize65To127
 
- TxSlowMode
 
- TxStartDemand
 
- TxStartThresh
 
- TxStatOK
 
- TxState
 
- TxStationAddr
 
- TxStatus
 
- TxStatus0
 
- TxStatusBits
 
- TxStopped
 
- TxSts
 
- TxSummary
 
- TxSwInt
 
- TxTagError
 
- TxThresh
 
- TxThreshMask
 
- TxThreshMax
 
- TxThreshold
 
- TxTransmitSystemError
 
- TxTrigger
 
- TxTsDeleteBA
 
- TxUIE
 
- TxURN
 
- TxUnderrun
 
- TxUnicast
 
- TxUnicastFramesTransmittedOK
 
- TxVersionMask
 
- TxVlanTag
 
- TxWaitSel
 
- TxXcoll
 
- TxXdefer
 
- Tx_10Stat
 
- Tx_BUF_EMP
 
- Tx_Beacon_param
 
- Tx_COE_EN_
 
- Tx_Comp
 
- Tx_Defer
 
- Tx_En
 
- Tx_EnComp
 
- Tx_EnExColl
 
- Tx_EnExDefer
 
- Tx_EnLCarr
 
- Tx_EnLateColl
 
- Tx_EnTxPar
 
- Tx_EnUnder
 
- Tx_ExColl
 
- Tx_FBack
 
- Tx_FlowCtl
 
- Tx_Halted
 
- Tx_IntTx
 
- Tx_LateColl
 
- Tx_NCarr
 
- Tx_NoCRC
 
- Tx_NoPad
 
- Tx_Paused
 
- Tx_Retry_Count_Reg
 
- Tx_SQErr
 
- Tx_TXDefer
 
- Tx_TxColl_MASK
 
- Tx_TxHalt
 
- Tx_TxPar
 
- Tx_Under
 
- Tx_enable
 
- Tx_flowOff
 
- TxdFreeBytes
 
- TxsFreeUnit
 
- Txstatusall
 
[..]