[..]
- R
- R0
- R00
- R00_DAC_CLK
- R00_EN_ADC
- R00_EN_DAC
- R00_EN_DEC
- R00_EN_INT
- R00_ID
- R00_ID1
- R00_MT9V011_CHIP_VERSION
- R00_PART_CONTROL
- R01
- R01_ID2
- R01_MT9V011_ROWSTART
- R01_R1
- R01_SEL_SOURCE
- R01_SFORI_I2S
- R01_SFORI_LSB16
- R01_SFORI_LSB18
- R01_SFORI_LSB20
- R01_SFORI_MASK
- R01_SFORI_MSB
- R01_SFORO_I2S
- R01_SFORO_LSB16
- R01_SFORO_LSB18
- R01_SFORO_LSB20
- R01_SFORO_LSB24
- R01_SFORO_MASK
- R01_SFORO_MSB
- R01_SIM
- R01_TIMING_CONTROL_LOW
- R02
- R02_EN_AVC
- R02_ID3
- R02_MT9V011_COLSTART
- R02_PON_ADCL
- R02_PON_ADCR
- R02_PON_AVC
- R02_PON_BIAS
- R02_PON_DAC
- R02_PON_HP
- R02_PON_LNA
- R02_PON_PGAL
- R02_PON_PGAR
- R02_PON_PLL
- R02_R2
- R03
- R03_MT9V011_HEIGHT
- R03_R3
- R03_TABLE_ADDR
- R03_THERMO1
- R04
- R04_MT9V011_WIDTH
- R04_R4
- R04_THERMO2
- R04_WTRAM_DATA_L
- R05
- R05_MT9V011_HBLANK
- R05_POWER1
- R05_R5
- R05_WTRAM_DATA_M
- R06
- R06_MT9V011_VBLANK
- R06_POWER2
- R06_R6
- R06_WTRAM_DATA_H
- R07
- R07_GPIO
- R07_MD1
- R07_MT9V011_OUT_CTRL
- R07_TABLE_LEN
- R08
- R08_IRQ1
- R08_PSM1
- R08_RAM_WRITE_ACTION
- R09
- R0900_AGCRF1CFG
- R0900_AGCRF2CFG
- R0900_BCHERR
- R0900_CFGEXT
- R0900_CLKI2CFG
- R0900_CLKOUT1CFG
- R0900_CLKOUT27CFG
- R0900_CLKOUT2CFG
- R0900_CLKOUT3CFG
- R0900_CS0CFG
- R0900_CS1CFG
- R0900_DACR1
- R0900_DACR2
- R0900_DATA71CFG
- R0900_DATA72CFG
- R0900_DATA73CFG
- R0900_DIRCLKCFG
- R0900_DISEQCO1CFG
- R0900_DISEQCO2CFG
- R0900_DPN1CFG
- R0900_DPN2CFG
- R0900_DPN3CFG
- R0900_ERROR1CFG
- R0900_ERROR2CFG
- R0900_ERROR3CFG
- R0900_FILTCTRL
- R0900_FSKRAGC
- R0900_FSKRAGCR
- R0900_FSKRALPHA
- R0900_FSKRDET0
- R0900_FSKRDET1
- R0900_FSKRDF0
- R0900_FSKRDF1
- R0900_FSKRDTH0
- R0900_FSKRDTH1
- R0900_FSKRFC0
- R0900_FSKRFC1
- R0900_FSKRFC2
- R0900_FSKRK1
- R0900_FSKRK2
- R0900_FSKRLOSS
- R0900_FSKRPLTH0
- R0900_FSKRPLTH1
- R0900_FSKRSTEPM
- R0900_FSKRSTEPP
- R0900_FSKTCTRL
- R0900_FSKTDELTAF0
- R0900_FSKTDELTAF1
- R0900_FSKTFC0
- R0900_FSKTFC1
- R0900_FSKTFC2
- R0900_GAINLLR_NF10
- R0900_GAINLLR_NF11
- R0900_GAINLLR_NF12
- R0900_GAINLLR_NF13
- R0900_GAINLLR_NF14
- R0900_GAINLLR_NF15
- R0900_GAINLLR_NF16
- R0900_GAINLLR_NF17
- R0900_GAINLLR_NF4
- R0900_GAINLLR_NF5
- R0900_GAINLLR_NF6
- R0900_GAINLLR_NF7
- R0900_GAINLLR_NF8
- R0900_GAINLLR_NF9
- R0900_GENCFG
- R0900_GPIO10CFG
- R0900_GPIO11CFG
- R0900_GPIO12CFG
- R0900_GPIO13CFG
- R0900_GPIO1CFG
- R0900_GPIO2CFG
- R0900_GPIO3CFG
- R0900_GPIO4CFG
- R0900_GPIO5CFG
- R0900_GPIO6CFG
- R0900_GPIO7CFG
- R0900_GPIO8CFG
- R0900_GPIO9CFG
- R0900_I2CCFG
- R0900_IOPVALUE0
- R0900_IOPVALUE1
- R0900_IOPVALUE2
- R0900_IOPVALUE3
- R0900_IOPVALUE4
- R0900_IOPVALUE5
- R0900_IOPVALUE6
- R0900_IRQMASK0
- R0900_IRQMASK1
- R0900_IRQMASK2
- R0900_IRQMASK3
- R0900_IRQSTATUS0
- R0900_IRQSTATUS1
- R0900_IRQSTATUS2
- R0900_IRQSTATUS3
- R0900_LDPCERR0
- R0900_LDPCERR1
- R0900_MID
- R0900_NBITERNOERR
- R0900_NBITER_NF10
- R0900_NBITER_NF11
- R0900_NBITER_NF12
- R0900_NBITER_NF13
- R0900_NBITER_NF14
- R0900_NBITER_NF15
- R0900_NBITER_NF16
- R0900_NBITER_NF17
- R0900_NBITER_NF4
- R0900_NBITER_NF5
- R0900_NBITER_NF6
- R0900_NBITER_NF7
- R0900_NBITER_NF8
- R0900_NBITER_NF9
- R0900_NCOARSE
- R0900_OUTCFG
- R0900_P1_ACLC
- R0900_P1_ACLC2S216A
- R0900_P1_ACLC2S232A
- R0900_P1_ACLC2S28
- R0900_P1_ACLC2S2Q
- R0900_P1_ACRDIV
- R0900_P1_ACRPRESC
- R0900_P1_AGC1ADJ
- R0900_P1_AGC1AMM
- R0900_P1_AGC1CFG
- R0900_P1_AGC1CN
- R0900_P1_AGC1QUAD
- R0900_P1_AGC1REF
- R0900_P1_AGC2I0
- R0900_P1_AGC2I1
- R0900_P1_AGC2O
- R0900_P1_AGC2REF
- R0900_P1_AGCIQIN0
- R0900_P1_AGCIQIN1
- R0900_P1_BBFCRCKO0
- R0900_P1_BBFCRCKO1
- R0900_P1_BCLC
- R0900_P1_BCLC2S216A
- R0900_P1_BCLC2S232A
- R0900_P1_BCLC2S28
- R0900_P1_BCLC2S2Q
- R0900_P1_CAR2CFG
- R0900_P1_CARCFG
- R0900_P1_CARFREQ
- R0900_P1_CARHDR
- R0900_P1_CCIACC
- R0900_P1_CCIQUANT
- R0900_P1_CCIR0
- R0900_P1_CCITHRES
- R0900_P1_CFR0
- R0900_P1_CFR1
- R0900_P1_CFR2
- R0900_P1_CFR20
- R0900_P1_CFR21
- R0900_P1_CFR22
- R0900_P1_CFR2AVRGE0
- R0900_P1_CFR2AVRGE1
- R0900_P1_CFR2CFR1
- R0900_P1_CFRICFG
- R0900_P1_CFRINC0
- R0900_P1_CFRINC1
- R0900_P1_CFRINIT0
- R0900_P1_CFRINIT1
- R0900_P1_CFRLOW0
- R0900_P1_CFRLOW1
- R0900_P1_CFRUP0
- R0900_P1_CFRUP1
- R0900_P1_CORRELABS
- R0900_P1_CORRELEXP
- R0900_P1_CORRELMANT
- R0900_P1_DEMOD
- R0900_P1_DFLSTR0
- R0900_P1_DFLSTR1
- R0900_P1_DISRXCTL
- R0900_P1_DISRXDATA
- R0900_P1_DISRX_ST0
- R0900_P1_DISRX_ST1
- R0900_P1_DISTXCTL
- R0900_P1_DISTXDATA
- R0900_P1_DISTXSTATUS
- R0900_P1_DMDCFG2
- R0900_P1_DMDCFG3
- R0900_P1_DMDCFG4
- R0900_P1_DMDCFGMD
- R0900_P1_DMDFLYW
- R0900_P1_DMDISTATE
- R0900_P1_DMDMODCOD
- R0900_P1_DMDPLHSTAT
- R0900_P1_DMDREG
- R0900_P1_DMDRESADR
- R0900_P1_DMDRESCFG
- R0900_P1_DMDRESDATA0
- R0900_P1_DMDRESDATA1
- R0900_P1_DMDRESDATA2
- R0900_P1_DMDRESDATA3
- R0900_P1_DMDRESDATA4
- R0900_P1_DMDRESDATA5
- R0900_P1_DMDRESDATA6
- R0900_P1_DMDRESDATA7
- R0900_P1_DMDSTATE
- R0900_P1_DMDT0M
- R0900_P1_DSTATUS
- R0900_P1_DSTATUS2
- R0900_P1_DSTATUS3
- R0900_P1_EQUAI1
- R0900_P1_EQUAI2
- R0900_P1_EQUAI3
- R0900_P1_EQUAI4
- R0900_P1_EQUAI5
- R0900_P1_EQUAI6
- R0900_P1_EQUAI7
- R0900_P1_EQUAI8
- R0900_P1_EQUALCFG
- R0900_P1_EQUAQ1
- R0900_P1_EQUAQ2
- R0900_P1_EQUAQ3
- R0900_P1_EQUAQ4
- R0900_P1_EQUAQ5
- R0900_P1_EQUAQ6
- R0900_P1_EQUAQ7
- R0900_P1_EQUAQ8
- R0900_P1_ERRCNT10
- R0900_P1_ERRCNT11
- R0900_P1_ERRCNT12
- R0900_P1_ERRCNT20
- R0900_P1_ERRCNT21
- R0900_P1_ERRCNT22
- R0900_P1_ERRCTRL1
- R0900_P1_ERRCTRL2
- R0900_P1_F22RX
- R0900_P1_F22TX
- R0900_P1_FBERCPT0
- R0900_P1_FBERCPT1
- R0900_P1_FBERCPT2
- R0900_P1_FBERCPT3
- R0900_P1_FBERCPT4
- R0900_P1_FBERERR0
- R0900_P1_FBERERR1
- R0900_P1_FBERERR2
- R0900_P1_FECM
- R0900_P1_FECSPY
- R0900_P1_FFECFG
- R0900_P1_FFEI1
- R0900_P1_FFEI2
- R0900_P1_FFEI3
- R0900_P1_FFEI4
- R0900_P1_FFEQ1
- R0900_P1_FFEQ2
- R0900_P1_FFEQ3
- R0900_P1_FFEQ4
- R0900_P1_FSPYBER
- R0900_P1_FSPYCFG
- R0900_P1_FSPYDATA
- R0900_P1_FSPYOUT
- R0900_P1_FSTATUS
- R0900_P1_GAUSSR0
- R0900_P1_HYSTTHRESH
- R0900_P1_I2CRPT
- R0900_P1_IDCCOMP
- R0900_P1_IQCONST
- R0900_P1_ISIBITENA
- R0900_P1_ISIENTRY
- R0900_P1_ISYMB
- R0900_P1_KDIV12
- R0900_P1_KDIV23
- R0900_P1_KDIV34
- R0900_P1_KDIV56
- R0900_P1_KDIV67
- R0900_P1_KDIV78
- R0900_P1_KREFTMG
- R0900_P1_KREFTMG2
- R0900_P1_LDI
- R0900_P1_LDT
- R0900_P1_LDT2
- R0900_P1_LOCKTIME0
- R0900_P1_LOCKTIME1
- R0900_P1_LOCKTIME2
- R0900_P1_LOCKTIME3
- R0900_P1_MATSTR0
- R0900_P1_MATSTR1
- R0900_P1_MODCODLST0
- R0900_P1_MODCODLST1
- R0900_P1_MODCODLST2
- R0900_P1_MODCODLST3
- R0900_P1_MODCODLST4
- R0900_P1_MODCODLST5
- R0900_P1_MODCODLST6
- R0900_P1_MODCODLST7
- R0900_P1_MODCODLST8
- R0900_P1_MODCODLST9
- R0900_P1_MODCODLSTA
- R0900_P1_MODCODLSTB
- R0900_P1_MODCODLSTC
- R0900_P1_MODCODLSTD
- R0900_P1_MODCODLSTE
- R0900_P1_MODCODLSTF
- R0900_P1_NCO2FR0
- R0900_P1_NCO2FR1
- R0900_P1_NCO2MAX0
- R0900_P1_NCO2MAX1
- R0900_P1_NNOSDATA0
- R0900_P1_NNOSDATA1
- R0900_P1_NNOSDATAT0
- R0900_P1_NNOSDATAT1
- R0900_P1_NNOSPLH0
- R0900_P1_NNOSPLH1
- R0900_P1_NNOSPLHT0
- R0900_P1_NNOSPLHT1
- R0900_P1_NOSCFG
- R0900_P1_NOSDATA0
- R0900_P1_NOSDATA1
- R0900_P1_NOSDATAT0
- R0900_P1_NOSDATAT1
- R0900_P1_NOSPLH0
- R0900_P1_NOSPLH1
- R0900_P1_NOSPLHT0
- R0900_P1_NOSPLHT1
- R0900_P1_PDELCTRL1
- R0900_P1_PDELCTRL2
- R0900_P1_PDELCTRL3
- R0900_P1_PDELSTATUS1
- R0900_P1_PDELSTATUS2
- R0900_P1_PLHMODCOD
- R0900_P1_PLROOT0
- R0900_P1_PLROOT1
- R0900_P1_PLROOT2
- R0900_P1_POWERI
- R0900_P1_POWERQ
- R0900_P1_PRVIT
- R0900_P1_QDCCOMP
- R0900_P1_QSYMB
- R0900_P1_RTC
- R0900_P1_RTCS2
- R0900_P1_SFR0
- R0900_P1_SFR1
- R0900_P1_SFR2
- R0900_P1_SFR3
- R0900_P1_SFRINIT0
- R0900_P1_SFRINIT1
- R0900_P1_SFRLOW0
- R0900_P1_SFRLOW1
- R0900_P1_SFRLOWRATIO
- R0900_P1_SFRSTEP
- R0900_P1_SFRUP0
- R0900_P1_SFRUP1
- R0900_P1_SFRUPRATIO
- R0900_P1_SMAPCOEF5
- R0900_P1_SMAPCOEF6
- R0900_P1_SMAPCOEF7
- R0900_P1_SYNCDSTR0
- R0900_P1_SYNCDSTR1
- R0900_P1_SYNCSTR
- R0900_P1_TCTL4
- R0900_P1_TMGCFG
- R0900_P1_TMGCFG2
- R0900_P1_TMGLOCK0
- R0900_P1_TMGLOCK1
- R0900_P1_TMGOBS
- R0900_P1_TMGREG0
- R0900_P1_TMGREG1
- R0900_P1_TMGREG2
- R0900_P1_TMGTHFALL
- R0900_P1_TMGTHRISE
- R0900_P1_TNRADJ
- R0900_P1_TNRBW
- R0900_P1_TNRCFG
- R0900_P1_TNRCFG2
- R0900_P1_TNRCFG3
- R0900_P1_TNRCTL2
- R0900_P1_TNRGAIN
- R0900_P1_TNRLAUNCH
- R0900_P1_TNRLD
- R0900_P1_TNROBSL
- R0900_P1_TNRRESTE
- R0900_P1_TNRRF0
- R0900_P1_TNRRF1
- R0900_P1_TNRSTEPS
- R0900_P1_TNRXTAL
- R0900_P1_TSBITRATE0
- R0900_P1_TSBITRATE1
- R0900_P1_TSCFG4
- R0900_P1_TSCFGH
- R0900_P1_TSCFGL
- R0900_P1_TSCFGM
- R0900_P1_TSDIVN
- R0900_P1_TSINSDELH
- R0900_P1_TSSPEED
- R0900_P1_TSSTATEM
- R0900_P1_TSSTATUS
- R0900_P1_TSSTATUS2
- R0900_P1_TSTDISRX
- R0900_P1_UPCRCKO0
- R0900_P1_UPCRCKO1
- R0900_P1_UPLSTR0
- R0900_P1_UPLSTR1
- R0900_P1_VAVSRVIT
- R0900_P1_VERROR
- R0900_P1_VITCURPUN
- R0900_P1_VITSCALE
- R0900_P1_VSTATUSVIT
- R0900_P1_VTH12
- R0900_P1_VTH23
- R0900_P1_VTH34
- R0900_P1_VTH56
- R0900_P1_VTH67
- R0900_P1_VTH78
- R0900_P1_VTHINUSE
- R0900_P2_ACLC
- R0900_P2_ACLC2S216A
- R0900_P2_ACLC2S232A
- R0900_P2_ACLC2S28
- R0900_P2_ACLC2S2Q
- R0900_P2_ACRDIV
- R0900_P2_ACRPRESC
- R0900_P2_AGC1ADJ
- R0900_P2_AGC1AMM
- R0900_P2_AGC1CFG
- R0900_P2_AGC1CN
- R0900_P2_AGC1QUAD
- R0900_P2_AGC1REF
- R0900_P2_AGC2I0
- R0900_P2_AGC2I1
- R0900_P2_AGC2O
- R0900_P2_AGC2REF
- R0900_P2_AGCIQIN0
- R0900_P2_AGCIQIN1
- R0900_P2_BBFCRCKO0
- R0900_P2_BBFCRCKO1
- R0900_P2_BCLC
- R0900_P2_BCLC2S216A
- R0900_P2_BCLC2S232A
- R0900_P2_BCLC2S28
- R0900_P2_BCLC2S2Q
- R0900_P2_CAR2CFG
- R0900_P2_CARCFG
- R0900_P2_CARFREQ
- R0900_P2_CARHDR
- R0900_P2_CCIACC
- R0900_P2_CCIQUANT
- R0900_P2_CCIR0
- R0900_P2_CCITHRES
- R0900_P2_CFR0
- R0900_P2_CFR1
- R0900_P2_CFR2
- R0900_P2_CFR20
- R0900_P2_CFR21
- R0900_P2_CFR22
- R0900_P2_CFR2AVRGE0
- R0900_P2_CFR2AVRGE1
- R0900_P2_CFR2CFR1
- R0900_P2_CFRICFG
- R0900_P2_CFRINC0
- R0900_P2_CFRINC1
- R0900_P2_CFRINIT0
- R0900_P2_CFRINIT1
- R0900_P2_CFRLOW0
- R0900_P2_CFRLOW1
- R0900_P2_CFRUP0
- R0900_P2_CFRUP1
- R0900_P2_CORRELABS
- R0900_P2_CORRELEXP
- R0900_P2_CORRELMANT
- R0900_P2_DEMOD
- R0900_P2_DFLSTR0
- R0900_P2_DFLSTR1
- R0900_P2_DISRXCTL
- R0900_P2_DISRXDATA
- R0900_P2_DISRX_ST0
- R0900_P2_DISRX_ST1
- R0900_P2_DISTXCTL
- R0900_P2_DISTXDATA
- R0900_P2_DISTXSTATUS
- R0900_P2_DMDCFG2
- R0900_P2_DMDCFG3
- R0900_P2_DMDCFG4
- R0900_P2_DMDCFGMD
- R0900_P2_DMDFLYW
- R0900_P2_DMDISTATE
- R0900_P2_DMDMODCOD
- R0900_P2_DMDPLHSTAT
- R0900_P2_DMDREG
- R0900_P2_DMDRESADR
- R0900_P2_DMDRESCFG
- R0900_P2_DMDRESDATA0
- R0900_P2_DMDRESDATA1
- R0900_P2_DMDRESDATA2
- R0900_P2_DMDRESDATA3
- R0900_P2_DMDRESDATA4
- R0900_P2_DMDRESDATA5
- R0900_P2_DMDRESDATA6
- R0900_P2_DMDRESDATA7
- R0900_P2_DMDSTATE
- R0900_P2_DMDT0M
- R0900_P2_DSTATUS
- R0900_P2_DSTATUS2
- R0900_P2_DSTATUS3
- R0900_P2_EQUAI1
- R0900_P2_EQUAI2
- R0900_P2_EQUAI3
- R0900_P2_EQUAI4
- R0900_P2_EQUAI5
- R0900_P2_EQUAI6
- R0900_P2_EQUAI7
- R0900_P2_EQUAI8
- R0900_P2_EQUALCFG
- R0900_P2_EQUAQ1
- R0900_P2_EQUAQ2
- R0900_P2_EQUAQ3
- R0900_P2_EQUAQ4
- R0900_P2_EQUAQ5
- R0900_P2_EQUAQ6
- R0900_P2_EQUAQ7
- R0900_P2_EQUAQ8
- R0900_P2_ERRCNT10
- R0900_P2_ERRCNT11
- R0900_P2_ERRCNT12
- R0900_P2_ERRCNT20
- R0900_P2_ERRCNT21
- R0900_P2_ERRCNT22
- R0900_P2_ERRCTRL1
- R0900_P2_ERRCTRL2
- R0900_P2_F22RX
- R0900_P2_F22TX
- R0900_P2_FBERCPT0
- R0900_P2_FBERCPT1
- R0900_P2_FBERCPT2
- R0900_P2_FBERCPT3
- R0900_P2_FBERCPT4
- R0900_P2_FBERERR0
- R0900_P2_FBERERR1
- R0900_P2_FBERERR2
- R0900_P2_FECM
- R0900_P2_FECSPY
- R0900_P2_FFECFG
- R0900_P2_FFEI1
- R0900_P2_FFEI2
- R0900_P2_FFEI3
- R0900_P2_FFEI4
- R0900_P2_FFEQ1
- R0900_P2_FFEQ2
- R0900_P2_FFEQ3
- R0900_P2_FFEQ4
- R0900_P2_FSPYBER
- R0900_P2_FSPYCFG
- R0900_P2_FSPYDATA
- R0900_P2_FSPYOUT
- R0900_P2_FSTATUS
- R0900_P2_GAUSSR0
- R0900_P2_HYSTTHRESH
- R0900_P2_I2CRPT
- R0900_P2_IDCCOMP
- R0900_P2_IQCONST
- R0900_P2_ISIBITENA
- R0900_P2_ISIENTRY
- R0900_P2_ISYMB
- R0900_P2_KDIV12
- R0900_P2_KDIV23
- R0900_P2_KDIV34
- R0900_P2_KDIV56
- R0900_P2_KDIV67
- R0900_P2_KDIV78
- R0900_P2_KREFTMG
- R0900_P2_KREFTMG2
- R0900_P2_LDI
- R0900_P2_LDT
- R0900_P2_LDT2
- R0900_P2_LOCKTIME0
- R0900_P2_LOCKTIME1
- R0900_P2_LOCKTIME2
- R0900_P2_LOCKTIME3
- R0900_P2_MATSTR0
- R0900_P2_MATSTR1
- R0900_P2_MODCODLST0
- R0900_P2_MODCODLST1
- R0900_P2_MODCODLST2
- R0900_P2_MODCODLST3
- R0900_P2_MODCODLST4
- R0900_P2_MODCODLST5
- R0900_P2_MODCODLST6
- R0900_P2_MODCODLST7
- R0900_P2_MODCODLST8
- R0900_P2_MODCODLST9
- R0900_P2_MODCODLSTA
- R0900_P2_MODCODLSTB
- R0900_P2_MODCODLSTC
- R0900_P2_MODCODLSTD
- R0900_P2_MODCODLSTE
- R0900_P2_MODCODLSTF
- R0900_P2_NCO2FR0
- R0900_P2_NCO2FR1
- R0900_P2_NCO2MAX0
- R0900_P2_NCO2MAX1
- R0900_P2_NNOSDATA0
- R0900_P2_NNOSDATA1
- R0900_P2_NNOSDATAT0
- R0900_P2_NNOSDATAT1
- R0900_P2_NNOSPLH0
- R0900_P2_NNOSPLH1
- R0900_P2_NNOSPLHT0
- R0900_P2_NNOSPLHT1
- R0900_P2_NOSCFG
- R0900_P2_NOSDATA0
- R0900_P2_NOSDATA1
- R0900_P2_NOSDATAT0
- R0900_P2_NOSDATAT1
- R0900_P2_NOSPLH0
- R0900_P2_NOSPLH1
- R0900_P2_NOSPLHT0
- R0900_P2_NOSPLHT1
- R0900_P2_PDELCTRL1
- R0900_P2_PDELCTRL2
- R0900_P2_PDELCTRL3
- R0900_P2_PDELSTATUS1
- R0900_P2_PDELSTATUS2
- R0900_P2_PLHMODCOD
- R0900_P2_PLROOT0
- R0900_P2_PLROOT1
- R0900_P2_PLROOT2
- R0900_P2_POWERI
- R0900_P2_POWERQ
- R0900_P2_PRVIT
- R0900_P2_QDCCOMP
- R0900_P2_QSYMB
- R0900_P2_RTC
- R0900_P2_RTCS2
- R0900_P2_SFR0
- R0900_P2_SFR1
- R0900_P2_SFR2
- R0900_P2_SFR3
- R0900_P2_SFRINIT0
- R0900_P2_SFRINIT1
- R0900_P2_SFRLOW0
- R0900_P2_SFRLOW1
- R0900_P2_SFRLOWRATIO
- R0900_P2_SFRSTEP
- R0900_P2_SFRUP0
- R0900_P2_SFRUP1
- R0900_P2_SFRUPRATIO
- R0900_P2_SMAPCOEF5
- R0900_P2_SMAPCOEF6
- R0900_P2_SMAPCOEF7
- R0900_P2_SYNCDSTR0
- R0900_P2_SYNCDSTR1
- R0900_P2_SYNCSTR
- R0900_P2_TCTL4
- R0900_P2_TMGCFG
- R0900_P2_TMGCFG2
- R0900_P2_TMGLOCK0
- R0900_P2_TMGLOCK1
- R0900_P2_TMGOBS
- R0900_P2_TMGREG0
- R0900_P2_TMGREG1
- R0900_P2_TMGREG2
- R0900_P2_TMGTHFALL
- R0900_P2_TMGTHRISE
- R0900_P2_TNRADJ
- R0900_P2_TNRBW
- R0900_P2_TNRCFG
- R0900_P2_TNRCFG2
- R0900_P2_TNRCFG3
- R0900_P2_TNRCTL2
- R0900_P2_TNRGAIN
- R0900_P2_TNRLAUNCH
- R0900_P2_TNRLD
- R0900_P2_TNROBSL
- R0900_P2_TNRRESTE
- R0900_P2_TNRRF0
- R0900_P2_TNRRF1
- R0900_P2_TNRSTEPS
- R0900_P2_TNRXTAL
- R0900_P2_TSBITRATE0
- R0900_P2_TSBITRATE1
- R0900_P2_TSCFG4
- R0900_P2_TSCFGH
- R0900_P2_TSCFGL
- R0900_P2_TSCFGM
- R0900_P2_TSDIVN
- R0900_P2_TSINSDELH
- R0900_P2_TSSPEED
- R0900_P2_TSSTATEM
- R0900_P2_TSSTATUS
- R0900_P2_TSSTATUS2
- R0900_P2_TSTDISRX
- R0900_P2_UPCRCKO0
- R0900_P2_UPCRCKO1
- R0900_P2_UPLSTR0
- R0900_P2_UPLSTR1
- R0900_P2_VAVSRVIT
- R0900_P2_VERROR
- R0900_P2_VITCURPUN
- R0900_P2_VITSCALE
- R0900_P2_VSTATUSVIT
- R0900_P2_VTH12
- R0900_P2_VTH23
- R0900_P2_VTH34
- R0900_P2_VTH56
- R0900_P2_VTH67
- R0900_P2_VTH78
- R0900_P2_VTHINUSE
- R0900_PLLSTAT
- R0900_RCCFG2
- R0900_SCLT1CFG
- R0900_SCLT2CFG
- R0900_SDAT1CFG
- R0900_SDAT2CFG
- R0900_STDBYCFG
- R0900_STOPCLK1
- R0900_STOPCLK2
- R0900_STROUT1CFG
- R0900_STROUT2CFG
- R0900_STROUT3CFG
- R0900_STRSTATUS1
- R0900_STRSTATUS2
- R0900_STRSTATUS3
- R0900_SYNTCTRL
- R0900_TSGENERAL
- R0900_TSGENERAL1X
- R0900_TSTRES0
- R0900_TSTTNR0
- R0900_TSTTNR1
- R0900_TSTTNR2
- R0900_TSTTNR3
- R0900_TSTTNR4
- R09_IRQ2
- R09_MD2
- R09_MT9V011_SHUTTER_WIDTH
- R0A
- R0A_IRQ3
- R0A_MD3
- R0A_MT9V011_CLK_SPEED
- R0B
- R0B_IRQ4
- R0B_MD4
- R0B_MT9V011_RESTART
- R0C
- R0C_AD_WIDTHL
- R0C_AGC11
- R0C_MD5
- R0C_MT9V011_SHUTTER_DELAY
- R0D
- R0D_AD_WIDTHH
- R0D_AGC12
- R0D_MD6
- R0D_MT9V011_RESET
- R0E
- R0E_AD_HEIGHTL
- R0E_AGC13
- R0E_MD7
- R0F
- R0F_AD_HEIGHTH
- R0F_AGC14
- R0F_MD8
- R0H
- R0_BASE1
- R0_CHK_FLAG
- R0_LOWER
- R0_OFF
- R0_UPPER
- R1
- R10
- R10000_LLSC_WAR
- R100CNT
- R100_CP_PACKET0_GET_REG
- R100_MAX_CB
- R100_TRACK_COMP_DXT1
- R100_TRACK_COMP_DXT35
- R100_TRACK_COMP_NONE
- R100_TRACK_MAX_TEXTURE
- R104_VERSION
- R10BIO_Degraded
- R10BIO_FailFast
- R10BIO_IsRecover
- R10BIO_IsReshape
- R10BIO_IsSync
- R10BIO_MadeGood
- R10BIO_Previous
- R10BIO_ReadError
- R10BIO_Uptodate
- R10BIO_WriteError
- R10KCBARRIER
- R10K_CONF_CT
- R10K_CONF_DC
- R10K_CONF_DN
- R10K_CONF_EC
- R10K_CONF_IC
- R10K_CONF_PE
- R10K_CONF_PM
- R10K_CONF_SB
- R10K_CONF_SC
- R10K_CONF_SK
- R10K_CONF_SS
- R10K_DIAG_D_BRC
- R10K_DIAG_D_BTAC
- R10K_DIAG_E_GHIST
- R10_1610_MCLK_OFF
- R10_1610_MCLK_ON
- R10_1610_MMC2_DAT3
- R10_AD_COL_BEGINL
- R10_CD1
- R10_LT1
- R10_OFF
- R11
- R11_1610_CF_IOIS16
- R11_AD_COL_BEGINH
- R11_CD2
- R11_LT2
- R11_OFF
- R12
- R128_3D_RNDR_GEN_INDX_PRIM
- R128_AGP_OFFSET
- R128_AGP_TEX_HEAP
- R128_AUX1_SC_BOTTOM
- R128_AUX1_SC_EN
- R128_AUX1_SC_LEFT
- R128_AUX1_SC_MODE_NAND
- R128_AUX1_SC_MODE_OR
- R128_AUX1_SC_RIGHT
- R128_AUX1_SC_TOP
- R128_AUX2_SC_BOTTOM
- R128_AUX2_SC_EN
- R128_AUX2_SC_LEFT
- R128_AUX2_SC_MODE_NAND
- R128_AUX2_SC_MODE_OR
- R128_AUX2_SC_RIGHT
- R128_AUX2_SC_TOP
- R128_AUX3_SC_BOTTOM
- R128_AUX3_SC_EN
- R128_AUX3_SC_LEFT
- R128_AUX3_SC_MODE_NAND
- R128_AUX3_SC_MODE_OR
- R128_AUX3_SC_RIGHT
- R128_AUX3_SC_TOP
- R128_AUX_SC_CNTL
- R128_BACK
- R128_BROKEN_CCE
- R128_BRUSH_DATA0
- R128_BUFFER_FREE
- R128_BUFFER_SIZE
- R128_BUFFER_USED
- R128_BUS_CNTL
- R128_BUS_MASTER_DIS
- R128_CCE_PACKET0
- R128_CCE_PACKET0_REG_MASK
- R128_CCE_PACKET1
- R128_CCE_PACKET1_REG0_MASK
- R128_CCE_PACKET1_REG1_MASK
- R128_CCE_PACKET2
- R128_CCE_PACKET3
- R128_CCE_PACKET_COUNT_MASK
- R128_CCE_PACKET_MASK
- R128_CCE_VC_CNTL_NUM_SHIFT
- R128_CCE_VC_CNTL_PRIM_TYPE_LINE
- R128_CCE_VC_CNTL_PRIM_TYPE_NONE
- R128_CCE_VC_CNTL_PRIM_TYPE_POINT
- R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE
- R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN
- R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST
- R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP
- R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2
- R128_CCE_VC_CNTL_PRIM_WALK_IND
- R128_CCE_VC_CNTL_PRIM_WALK_LIST
- R128_CCE_VC_CNTL_PRIM_WALK_RING
- R128_CLOCK_CNTL_DATA
- R128_CLOCK_CNTL_INDEX
- R128_CNTL_BITBLT_MULTI
- R128_CNTL_HOSTDATA_BLT
- R128_CNTL_PAINT_MULTI
- R128_CONSTANT_COLOR_C
- R128_CRTC_OFFSET
- R128_CRTC_OFFSET_CNTL
- R128_CRTC_OFFSET_FLIP_CNTL
- R128_CRTC_VBLANK_INT
- R128_CRTC_VBLANK_INT_AK
- R128_CRTC_VBLANK_INT_EN
- R128_DATATYPE_ARGB1555
- R128_DATATYPE_ARGB4444
- R128_DATATYPE_ARGB8888
- R128_DATATYPE_AYUV444
- R128_DATATYPE_CI16
- R128_DATATYPE_CI4
- R128_DATATYPE_CI8
- R128_DATATYPE_RGB332
- R128_DATATYPE_RGB565
- R128_DATATYPE_RGB8
- R128_DATATYPE_RGB888
- R128_DATATYPE_VQ
- R128_DATATYPE_VYUY422
- R128_DATATYPE_Y8
- R128_DATATYPE_YVYU422
- R128_DEPTH
- R128_DP_GUI_MASTER_CNTL
- R128_DP_SRC_SOURCE_HOST_DATA
- R128_DP_SRC_SOURCE_MEMORY
- R128_DP_WRITE_MASK
- R128_DST_PITCH_OFFSET_C
- R128_DST_TILE
- R128_EVENT_CRTC_OFFSET
- R128_FIFO_DEBUG
- R128_FORCE_GCP
- R128_FORCE_PIPE3D_CP
- R128_FORCE_RCP
- R128_FRONT
- R128_GEN_INT_CNTL
- R128_GEN_INT_STATUS
- R128_GEN_RESET_CNTL
- R128_GMC_AUX_CLIP_DIS
- R128_GMC_BRUSH_NONE
- R128_GMC_BRUSH_SOLID_COLOR
- R128_GMC_CLR_CMP_CNTL_DIS
- R128_GMC_DST_16BPP
- R128_GMC_DST_24BPP
- R128_GMC_DST_32BPP
- R128_GMC_DST_DATATYPE_SHIFT
- R128_GMC_DST_PITCH_OFFSET_CNTL
- R128_GMC_SRC_DATATYPE_COLOR
- R128_GMC_SRC_PITCH_OFFSET_CNTL
- R128_GMC_WR_MSK_DIS
- R128_GUI_ACTIVE
- R128_GUI_FIFOCNT_MASK
- R128_GUI_SCRATCH_REG0
- R128_GUI_SCRATCH_REG1
- R128_GUI_SCRATCH_REG2
- R128_GUI_SCRATCH_REG3
- R128_GUI_SCRATCH_REG4
- R128_GUI_SCRATCH_REG5
- R128_GUI_STAT
- R128_HOSTDATA_BLIT_OFFSET
- R128_INDEX_PRIM_OFFSET
- R128_LAST_DISPATCH_REG
- R128_LAST_FRAME_REG
- R128_LINES
- R128_LINE_STRIP
- R128_LOCAL_TEX_HEAP
- R128_LOG_TEX_GRANULARITY
- R128_MAX_TEXTURE_LEVELS
- R128_MAX_TEXTURE_UNITS
- R128_MAX_USEC_TIMEOUT
- R128_MAX_VB_AGE
- R128_MAX_VB_VERTS
- R128_MCLK_CNTL
- R128_NR_CONTEXT_REGS
- R128_NR_SAREA_CLIPRECTS
- R128_NR_TEX_HEAPS
- R128_NR_TEX_REGIONS
- R128_PARAM_IRQ_NR
- R128_PCIGART_TABLE_SIZE
- R128_PCI_GART_PAGE
- R128_PC_BUSY
- R128_PC_FLUSH_ALL
- R128_PC_FLUSH_GUI
- R128_PC_GUI_CTLSTAT
- R128_PC_NGUI_CTLSTAT
- R128_PC_RI_GUI
- R128_PERFORMANCE_BOXES
- R128_PLL_WR_EN
- R128_PM4_128BM_64INDBM
- R128_PM4_128PIO_64INDBM
- R128_PM4_192BM
- R128_PM4_192PIO
- R128_PM4_64BM_128INDBM
- R128_PM4_64BM_64VCBM_64INDBM
- R128_PM4_64PIO_128INDBM
- R128_PM4_64PIO_64VCBM_64INDBM
- R128_PM4_64PIO_64VCPIO_64INDPIO
- R128_PM4_BUFFER_ADDR
- R128_PM4_BUFFER_CNTL
- R128_PM4_BUFFER_CNTL_NOUPDATE
- R128_PM4_BUFFER_DL_DONE
- R128_PM4_BUFFER_DL_RPTR
- R128_PM4_BUFFER_DL_RPTR_ADDR
- R128_PM4_BUFFER_DL_WPTR
- R128_PM4_BUFFER_OFFSET
- R128_PM4_BUFFER_WM_CNTL
- R128_PM4_BUSY
- R128_PM4_FIFOCNT_MASK
- R128_PM4_FIFO_DATA_EVEN
- R128_PM4_FIFO_DATA_ODD
- R128_PM4_GUI_ACTIVE
- R128_PM4_IW_INDOFF
- R128_PM4_IW_INDSIZE
- R128_PM4_MASK
- R128_PM4_MICROCODE_ADDR
- R128_PM4_MICROCODE_DATAH
- R128_PM4_MICROCODE_DATAL
- R128_PM4_MICROCODE_RADDR
- R128_PM4_MICRO_CNTL
- R128_PM4_MICRO_FREERUN
- R128_PM4_NONPM4
- R128_PM4_STAT
- R128_PM4_VC_FPU_SETUP
- R128_POINTS
- R128_PRIM_TEX_CNTL_C
- R128_READ
- R128_READ8
- R128_READ_PLL
- R128_REQUIRE_QUIESCENCE
- R128_RING_HIGH_MARK
- R128_ROP3_P
- R128_ROP3_S
- R128_SCALE_3D_CNTL
- R128_SEC_TEXTURE_BORDER_COLOR_C
- R128_SEC_TEX_CNTL_C
- R128_SETUP_CNTL
- R128_SOFT_RESET_GUI
- R128_STEN_REF_MASK_C
- R128_TEX_CACHE_FLUSH
- R128_TEX_CNTL_C
- R128_TRIANGLES
- R128_TRIANGLE_FAN
- R128_TRIANGLE_STRIP
- R128_UPLOAD_ALL
- R128_UPLOAD_CLIPRECTS
- R128_UPLOAD_CONTEXT
- R128_UPLOAD_CORE
- R128_UPLOAD_MASKS
- R128_UPLOAD_SETUP
- R128_UPLOAD_TEX0
- R128_UPLOAD_TEX0IMAGES
- R128_UPLOAD_TEX1
- R128_UPLOAD_TEX1IMAGES
- R128_UPLOAD_WINDOW
- R128_VERBOSE
- R128_WAIT_UNTIL
- R128_WAIT_UNTIL_PAGE_FLIPPED
- R128_WATERMARK_K
- R128_WATERMARK_L
- R128_WATERMARK_M
- R128_WATERMARK_N
- R128_WB_WM_SHIFT
- R128_WINDOW_XY_OFFSET
- R128_WMA_SHIFT
- R128_WMB_SHIFT
- R128_WMC_SHIFT
- R128_WRITE
- R128_WRITE8
- R128_WRITE_PLL
- R12_AGC21
- R12_CD3
- R12_OFF
- R13
- R13_1610_UART1_TX
- R13_1610_USB1_SPEED
- R13_1710_USB1_SE0
- R13_AGC22
- R13_CD4
- R13_MTM
- R13_OFF
- R14
- R14_1610_UART1_CTS
- R14_AD_ROW_BEGINL
- R14_AGC23
- R14_CD5
- R14_OFF
- R14_SDET_ON
- R14_SILENCE
- R15
- R15_AD_ROWBEGINH
- R15_AGC24
- R15_CD6
- R15_OFF
- R16
- R16_AGC25
- R16_CD7
- R16_OFF
- R17
- R17_AGC31
- R17_OFF
- R17_PD1
- R18
- R18_1510_GPIO0
- R18_1510_USB_GPIO0
- R18_1610_MMC2_CLKIN
- R18_1610_SPIF_DOUT
- R18_1710_GPIO0
- R18_AGC32
- R18_DESC
- R18_DEVICE_ID_1G
- R18_OFF
- R18_PD2
- R18_USB_VBUS
- R19
- R19_1510_GPIO1
- R19_AGC33
- R19_DESC
- R19_OFF
- R19_XTOUT
- R1A_AGCK
- R1A_IF1
- R1B
- R1BIO_BehindIO
- R1BIO_Degraded
- R1BIO_FailFast
- R1BIO_IsSync
- R1BIO_MadeGood
- R1BIO_ReadError
- R1BIO_Returned
- R1BIO_Uptodate
- R1BIO_WriteError
- R1B_GAIN1
- R1B_IF2
- R1C_AD_EXPOSE_TIMEL
- R1C_AGC2B
- R1C_GAIN2
- R1D
- R1DF_MASK
- R1DM
- R1D_GAIN3
- R1D_PSM2
- R1E_MT9V011_DIGITAL_ZOOM
- R1E_PSM3
- R1E_WI_FI
- R1FE_MASK
- R1F_PSM4
- R1F_RF_BPF
- R1H
- R1MS_MASK
- R1ST
- R1_ADDRESS_ERROR
- R1_APP_CMD
- R1_BASE1
- R1_BASE2
- R1_BLOCK_LEN_ERROR
- R1_CARD_ECC_DISABLED
- R1_CARD_ECC_FAILED
- R1_CARD_IS_LOCKED
- R1_CC_ERROR
- R1_CID_CSD_OVERWRITE
- R1_CLKSEL_DSP
- R1_CLKSEL_DSP_IF
- R1_CLKSEL_GFX
- R1_CLKSEL_L3
- R1_CLKSEL_L4
- R1_CLKSEL_MDM
- R1_CLKSEL_MPU
- R1_CLKSEL_USB
- R1_CM_CLKSEL1_CORE_VAL
- R1_CM_CLKSEL_DSP_VAL
- R1_CM_CLKSEL_GFX_VAL
- R1_CM_CLKSEL_MDM_VAL
- R1_CM_CLKSEL_MPU_VAL
- R1_COM_CRC_ERROR
- R1_CURRENT_STATE
- R1_ERASE_PARAM
- R1_ERASE_RESET
- R1_ERASE_SEQ_ERROR
- R1_ERROR
- R1_EXCEPTION_EVENT
- R1_ILLEGAL_COMMAND
- R1_LOCK_UNLOCK_FAILED
- R1_OFF
- R1_OUT_OF_RANGE
- R1_OVERRUN
- R1_READY_FOR_DATA
- R1_SPI_ADDRESS
- R1_SPI_COM_CRC
- R1_SPI_ERASE_RESET
- R1_SPI_ERASE_SEQ
- R1_SPI_IDLE
- R1_SPI_ILLEGAL_COMMAND
- R1_SPI_PARAMETER
- R1_STATE_DATA
- R1_STATE_DIS
- R1_STATE_IDENT
- R1_STATE_IDLE
- R1_STATE_PRG
- R1_STATE_RCV
- R1_STATE_READY
- R1_STATE_STBY
- R1_STATE_TRAN
- R1_STATUS
- R1_SWITCH_ERROR
- R1_UNDERRUN
- R1_WP_ERASE_SKIP
- R1_WP_VIOLATION
- R2
- R20
- R200_BORDER_MODE_D3D
- R200_BORDER_MODE_OGL
- R200_CLAMP_S_CLAMP_BORDER
- R200_CLAMP_S_CLAMP_GL
- R200_CLAMP_S_CLAMP_LAST
- R200_CLAMP_S_MASK
- R200_CLAMP_S_MIRROR
- R200_CLAMP_S_MIRROR_CLAMP_BORDER
- R200_CLAMP_S_MIRROR_CLAMP_GL
- R200_CLAMP_S_MIRROR_CLAMP_LAST
- R200_CLAMP_S_WRAP
- R200_CLAMP_T_CLAMP_BORDER
- R200_CLAMP_T_CLAMP_GL
- R200_CLAMP_T_CLAMP_LAST
- R200_CLAMP_T_MASK
- R200_CLAMP_T_MIRROR
- R200_CLAMP_T_MIRROR_CLAMP_BORDER
- R200_CLAMP_T_MIRROR_CLAMP_GL
- R200_CLAMP_T_MIRROR_CLAMP_LAST
- R200_CLAMP_T_WRAP
- R200_CMD
- R200_CP_PACKET3_3D_DRAW_IMMD_2
- R200_DVI_I2C_PIN_SEL
- R200_EMIT_ATF_TFACTOR
- R200_EMIT_MATRIX_SELECT_0
- R200_EMIT_OUTPUT_VTX_COMP_SEL
- R200_EMIT_PP_AFS_0
- R200_EMIT_PP_AFS_1
- R200_EMIT_PP_CNTL_X
- R200_EMIT_PP_CUBIC_FACES_0
- R200_EMIT_PP_CUBIC_FACES_1
- R200_EMIT_PP_CUBIC_FACES_2
- R200_EMIT_PP_CUBIC_FACES_3
- R200_EMIT_PP_CUBIC_FACES_4
- R200_EMIT_PP_CUBIC_FACES_5
- R200_EMIT_PP_CUBIC_OFFSETS_0
- R200_EMIT_PP_CUBIC_OFFSETS_1
- R200_EMIT_PP_CUBIC_OFFSETS_2
- R200_EMIT_PP_CUBIC_OFFSETS_3
- R200_EMIT_PP_CUBIC_OFFSETS_4
- R200_EMIT_PP_CUBIC_OFFSETS_5
- R200_EMIT_PP_TAM_DEBUG3
- R200_EMIT_PP_TRI_PERF_CNTL
- R200_EMIT_PP_TXCBLEND_0
- R200_EMIT_PP_TXCBLEND_1
- R200_EMIT_PP_TXCBLEND_2
- R200_EMIT_PP_TXCBLEND_3
- R200_EMIT_PP_TXCBLEND_4
- R200_EMIT_PP_TXCBLEND_5
- R200_EMIT_PP_TXCBLEND_6
- R200_EMIT_PP_TXCBLEND_7
- R200_EMIT_PP_TXCTLALL_0
- R200_EMIT_PP_TXCTLALL_1
- R200_EMIT_PP_TXCTLALL_2
- R200_EMIT_PP_TXCTLALL_3
- R200_EMIT_PP_TXCTLALL_4
- R200_EMIT_PP_TXCTLALL_5
- R200_EMIT_PP_TXFILTER_0
- R200_EMIT_PP_TXFILTER_1
- R200_EMIT_PP_TXFILTER_2
- R200_EMIT_PP_TXFILTER_3
- R200_EMIT_PP_TXFILTER_4
- R200_EMIT_PP_TXFILTER_5
- R200_EMIT_PP_TXOFFSET_0
- R200_EMIT_PP_TXOFFSET_1
- R200_EMIT_PP_TXOFFSET_2
- R200_EMIT_PP_TXOFFSET_3
- R200_EMIT_PP_TXOFFSET_4
- R200_EMIT_PP_TXOFFSET_5
- R200_EMIT_RB3D_BLENDCOLOR
- R200_EMIT_RB3D_DEPTHXY_OFFSET
- R200_EMIT_RE_AUX_SCISSOR_CNTL
- R200_EMIT_RE_POINTSIZE
- R200_EMIT_RE_SCISSOR_TL_0
- R200_EMIT_RE_SCISSOR_TL_1
- R200_EMIT_RE_SCISSOR_TL_2
- R200_EMIT_SE_VAP_CNTL_STATUS
- R200_EMIT_SE_VTX_STATE_CNTL
- R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0
- R200_EMIT_TCL_LIGHT_MODEL_CTL_0
- R200_EMIT_TCL_POINT_SPRITE_CNTL
- R200_EMIT_TCL_UCP_VERT_BLEND_CTL
- R200_EMIT_TEX_PROC_CTL_2
- R200_EMIT_TFACTOR_0
- R200_EMIT_VAP_CTL
- R200_EMIT_VAP_PVS_CNTL
- R200_EMIT_VTE_CNTL
- R200_EMIT_VTX_FMT_0
- R200_FORCE_INORDER_PROC
- R200_FP2_DVO_RATE_SEL_SDR
- R200_FP2_SOURCE_SEL_CRTC1
- R200_FP2_SOURCE_SEL_CRTC2
- R200_FP2_SOURCE_SEL_MASK
- R200_FP2_SOURCE_SEL_RMX
- R200_FP2_SOURCE_SEL_TRANS_UNIT
- R200_FP_SOURCE_SEL_CRTC1
- R200_FP_SOURCE_SEL_CRTC2
- R200_FP_SOURCE_SEL_MASK
- R200_FP_SOURCE_SEL_RMX
- R200_FP_SOURCE_SEL_TRANS
- R200_KILL_LT_ZERO
- R200_MAG_FILTER_LINEAR
- R200_MAG_FILTER_MASK
- R200_MAG_FILTER_NEAREST
- R200_MAX_ANISO_16_TO_1
- R200_MAX_ANISO_1_TO_1
- R200_MAX_ANISO_2_TO_1
- R200_MAX_ANISO_4_TO_1
- R200_MAX_ANISO_8_TO_1
- R200_MAX_ANISO_MASK
- R200_MAX_MIP_LEVEL_MASK
- R200_MAX_MIP_LEVEL_SHIFT
- R200_MIN_FILTER_ANISO_LINEAR
- R200_MIN_FILTER_ANISO_NEAREST
- R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR
- R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST
- R200_MIN_FILTER_LINEAR
- R200_MIN_FILTER_LINEAR_MIP_LINEAR
- R200_MIN_FILTER_LINEAR_MIP_NEAREST
- R200_MIN_FILTER_MASK
- R200_MIN_FILTER_NEAREST
- R200_MIN_FILTER_NEAREST_MIP_LINEAR
- R200_MIN_FILTER_NEAREST_MIP_NEAREST
- R200_OUTPUT_COLOR_0
- R200_OUTPUT_COLOR_1
- R200_OUTPUT_DISCRETE_FOG
- R200_OUTPUT_PT_SIZE
- R200_OUTPUT_TEX_0
- R200_OUTPUT_TEX_1
- R200_OUTPUT_TEX_2
- R200_OUTPUT_TEX_3
- R200_OUTPUT_TEX_4
- R200_OUTPUT_TEX_5
- R200_OUTPUT_TEX_MASK
- R200_OUTPUT_XYZW
- R200_PATTERN_ENABLE
- R200_PERSPECTIVE_ENABLE
- R200_POINT_SMOOTH
- R200_PP_CNTL_X
- R200_PP_CUBIC_FACES_0
- R200_PP_CUBIC_FACES_1
- R200_PP_CUBIC_FACES_2
- R200_PP_CUBIC_FACES_3
- R200_PP_CUBIC_FACES_4
- R200_PP_CUBIC_FACES_5
- R200_PP_CUBIC_OFFSET_F1_0
- R200_PP_CUBIC_OFFSET_F1_1
- R200_PP_CUBIC_OFFSET_F1_2
- R200_PP_CUBIC_OFFSET_F1_3
- R200_PP_CUBIC_OFFSET_F1_4
- R200_PP_CUBIC_OFFSET_F1_5
- R200_PP_CUBIC_OFFSET_F2_0
- R200_PP_CUBIC_OFFSET_F2_1
- R200_PP_CUBIC_OFFSET_F2_2
- R200_PP_CUBIC_OFFSET_F2_3
- R200_PP_CUBIC_OFFSET_F2_4
- R200_PP_CUBIC_OFFSET_F2_5
- R200_PP_CUBIC_OFFSET_F3_0
- R200_PP_CUBIC_OFFSET_F3_1
- R200_PP_CUBIC_OFFSET_F3_2
- R200_PP_CUBIC_OFFSET_F3_3
- R200_PP_CUBIC_OFFSET_F3_4
- R200_PP_CUBIC_OFFSET_F3_5
- R200_PP_CUBIC_OFFSET_F4_0
- R200_PP_CUBIC_OFFSET_F4_1
- R200_PP_CUBIC_OFFSET_F4_2
- R200_PP_CUBIC_OFFSET_F4_3
- R200_PP_CUBIC_OFFSET_F4_4
- R200_PP_CUBIC_OFFSET_F4_5
- R200_PP_CUBIC_OFFSET_F5_0
- R200_PP_CUBIC_OFFSET_F5_1
- R200_PP_CUBIC_OFFSET_F5_2
- R200_PP_CUBIC_OFFSET_F5_3
- R200_PP_CUBIC_OFFSET_F5_4
- R200_PP_CUBIC_OFFSET_F5_5
- R200_PP_TFACTOR_0
- R200_PP_TFACTOR_1
- R200_PP_TFACTOR_2
- R200_PP_TFACTOR_3
- R200_PP_TFACTOR_4
- R200_PP_TFACTOR_5
- R200_PP_TXABLEND2_0
- R200_PP_TXABLEND_0
- R200_PP_TXCBLEND2_0
- R200_PP_TXCBLEND_0
- R200_PP_TXFILTER_0
- R200_PP_TXFILTER_1
- R200_PP_TXFILTER_2
- R200_PP_TXFILTER_3
- R200_PP_TXFILTER_4
- R200_PP_TXFILTER_5
- R200_PP_TXFORMAT_0
- R200_PP_TXFORMAT_1
- R200_PP_TXFORMAT_2
- R200_PP_TXFORMAT_3
- R200_PP_TXFORMAT_4
- R200_PP_TXFORMAT_5
- R200_PP_TXFORMAT_X_0
- R200_PP_TXFORMAT_X_1
- R200_PP_TXFORMAT_X_2
- R200_PP_TXFORMAT_X_3
- R200_PP_TXFORMAT_X_4
- R200_PP_TXFORMAT_X_5
- R200_PP_TXMULTI_CTL_0
- R200_PP_TXMULTI_CTL_1
- R200_PP_TXMULTI_CTL_2
- R200_PP_TXMULTI_CTL_3
- R200_PP_TXMULTI_CTL_4
- R200_PP_TXMULTI_CTL_5
- R200_PP_TXOFFSET_0
- R200_PP_TXOFFSET_1
- R200_PP_TXOFFSET_2
- R200_PP_TXOFFSET_3
- R200_PP_TXOFFSET_4
- R200_PP_TXOFFSET_5
- R200_PP_TXPITCH_0
- R200_PP_TXPITCH_1
- R200_PP_TXPITCH_2
- R200_PP_TXPITCH_3
- R200_PP_TXPITCH_4
- R200_PP_TXPITCH_5
- R200_PP_TXSIZE_0
- R200_PP_TXSIZE_1
- R200_PP_TXSIZE_2
- R200_PP_TXSIZE_3
- R200_PP_TXSIZE_4
- R200_PP_TXSIZE_5
- R200_RB3D_DC_2D_CACHE_AUTOFREE
- R200_RB3D_DC_3D_CACHE_AUTOFREE
- R200_RE_CNTL
- R200_SCISSOR_ENABLE
- R200_SEL_DDC1
- R200_SEL_DDC2
- R200_SEL_DDC3
- R200_SE_TCL_OUTPUT_VTX_COMP_SEL
- R200_SE_TCL_OUTPUT_VTX_FMT_0
- R200_SE_TCL_OUTPUT_VTX_FMT_1
- R200_SE_VAP_CNTL
- R200_SE_VAP_CNTL_STATUS
- R200_SE_VTE_CNTL
- R200_SE_VTX_FMT_0
- R200_SE_VTX_FMT_1
- R200_SE_VTX_STATE_CNTL
- R200_STIPPLE_ENABLE
- R200_SURF_TILE_COLOR_BOTH
- R200_SURF_TILE_COLOR_MACRO
- R200_SURF_TILE_COLOR_MICRO
- R200_SURF_TILE_DEPTH_16BPP
- R200_SURF_TILE_DEPTH_32BPP
- R200_SURF_TILE_NONE
- R200_TRACK_MAX_TEXTURE
- R200_TXA_ARG_A_CURRENT_ALPHA
- R200_TXA_ARG_A_CURRENT_BLUE
- R200_TXA_ARG_A_DIFFUSE_ALPHA
- R200_TXA_ARG_A_DIFFUSE_BLUE
- R200_TXA_ARG_A_MASK
- R200_TXA_ARG_A_R0_ALPHA
- R200_TXA_ARG_A_R0_BLUE
- R200_TXA_ARG_A_R1_ALPHA
- R200_TXA_ARG_A_R1_BLUE
- R200_TXA_ARG_A_R2_ALPHA
- R200_TXA_ARG_A_R2_BLUE
- R200_TXA_ARG_A_R3_ALPHA
- R200_TXA_ARG_A_R3_BLUE
- R200_TXA_ARG_A_R4_ALPHA
- R200_TXA_ARG_A_R4_BLUE
- R200_TXA_ARG_A_R5_ALPHA
- R200_TXA_ARG_A_R5_BLUE
- R200_TXA_ARG_A_SHIFT
- R200_TXA_ARG_A_SPECULAR_ALPHA
- R200_TXA_ARG_A_SPECULAR_BLUE
- R200_TXA_ARG_A_TFACTOR1_ALPHA
- R200_TXA_ARG_A_TFACTOR1_BLUE
- R200_TXA_ARG_A_TFACTOR_ALPHA
- R200_TXA_ARG_A_TFACTOR_BLUE
- R200_TXA_ARG_A_ZERO
- R200_TXA_ARG_B_CURRENT_ALPHA
- R200_TXA_ARG_B_CURRENT_BLUE
- R200_TXA_ARG_B_DIFFUSE_ALPHA
- R200_TXA_ARG_B_DIFFUSE_BLUE
- R200_TXA_ARG_B_MASK
- R200_TXA_ARG_B_R0_ALPHA
- R200_TXA_ARG_B_R0_BLUE
- R200_TXA_ARG_B_R1_ALPHA
- R200_TXA_ARG_B_R1_BLUE
- R200_TXA_ARG_B_R2_ALPHA
- R200_TXA_ARG_B_R2_BLUE
- R200_TXA_ARG_B_R3_ALPHA
- R200_TXA_ARG_B_R3_BLUE
- R200_TXA_ARG_B_R4_ALPHA
- R200_TXA_ARG_B_R4_BLUE
- R200_TXA_ARG_B_R5_ALPHA
- R200_TXA_ARG_B_R5_BLUE
- R200_TXA_ARG_B_SHIFT
- R200_TXA_ARG_B_SPECULAR_ALPHA
- R200_TXA_ARG_B_SPECULAR_BLUE
- R200_TXA_ARG_B_TFACTOR1_ALPHA
- R200_TXA_ARG_B_TFACTOR1_BLUE
- R200_TXA_ARG_B_TFACTOR_ALPHA
- R200_TXA_ARG_B_TFACTOR_BLUE
- R200_TXA_ARG_B_ZERO
- R200_TXA_ARG_C_CURRENT_ALPHA
- R200_TXA_ARG_C_CURRENT_BLUE
- R200_TXA_ARG_C_DIFFUSE_ALPHA
- R200_TXA_ARG_C_DIFFUSE_BLUE
- R200_TXA_ARG_C_MASK
- R200_TXA_ARG_C_R0_ALPHA
- R200_TXA_ARG_C_R0_BLUE
- R200_TXA_ARG_C_R1_ALPHA
- R200_TXA_ARG_C_R1_BLUE
- R200_TXA_ARG_C_R2_ALPHA
- R200_TXA_ARG_C_R2_BLUE
- R200_TXA_ARG_C_R3_ALPHA
- R200_TXA_ARG_C_R3_BLUE
- R200_TXA_ARG_C_R4_ALPHA
- R200_TXA_ARG_C_R4_BLUE
- R200_TXA_ARG_C_R5_ALPHA
- R200_TXA_ARG_C_R5_BLUE
- R200_TXA_ARG_C_SHIFT
- R200_TXA_ARG_C_SPECULAR_ALPHA
- R200_TXA_ARG_C_SPECULAR_BLUE
- R200_TXA_ARG_C_TFACTOR1_ALPHA
- R200_TXA_ARG_C_TFACTOR1_BLUE
- R200_TXA_ARG_C_TFACTOR_ALPHA
- R200_TXA_ARG_C_TFACTOR_BLUE
- R200_TXA_ARG_C_ZERO
- R200_TXA_BIAS_ARG_A
- R200_TXA_BIAS_ARG_B
- R200_TXA_BIAS_ARG_C
- R200_TXA_CLAMP_0_1
- R200_TXA_CLAMP_8_8
- R200_TXA_CLAMP_MASK
- R200_TXA_CLAMP_SHIFT
- R200_TXA_CLAMP_WRAP
- R200_TXA_COMP_ARG_A
- R200_TXA_COMP_ARG_A_SHIFT
- R200_TXA_COMP_ARG_B
- R200_TXA_COMP_ARG_B_SHIFT
- R200_TXA_COMP_ARG_C
- R200_TXA_COMP_ARG_C_SHIFT
- R200_TXA_DOT_ALPHA
- R200_TXA_NEG_ARG_A
- R200_TXA_NEG_ARG_B
- R200_TXA_NEG_ARG_C
- R200_TXA_OP_CND0
- R200_TXA_OP_CONDITIONAL
- R200_TXA_OP_LERP
- R200_TXA_OP_MADD
- R200_TXA_OP_MASK
- R200_TXA_OUTPUT_REG_MASK
- R200_TXA_OUTPUT_REG_NONE
- R200_TXA_OUTPUT_REG_R0
- R200_TXA_OUTPUT_REG_R1
- R200_TXA_OUTPUT_REG_R2
- R200_TXA_OUTPUT_REG_R3
- R200_TXA_OUTPUT_REG_R4
- R200_TXA_OUTPUT_REG_R5
- R200_TXA_REPL_ARG_A_MASK
- R200_TXA_REPL_ARG_A_SHIFT
- R200_TXA_REPL_ARG_B_MASK
- R200_TXA_REPL_ARG_B_SHIFT
- R200_TXA_REPL_ARG_C_MASK
- R200_TXA_REPL_ARG_C_SHIFT
- R200_TXA_REPL_GREEN
- R200_TXA_REPL_NORMAL
- R200_TXA_REPL_RED
- R200_TXA_SCALE_1X
- R200_TXA_SCALE_2X
- R200_TXA_SCALE_4X
- R200_TXA_SCALE_8X
- R200_TXA_SCALE_ARG_A
- R200_TXA_SCALE_ARG_B
- R200_TXA_SCALE_ARG_C
- R200_TXA_SCALE_INV2
- R200_TXA_SCALE_INV4
- R200_TXA_SCALE_INV8
- R200_TXA_SCALE_MASK
- R200_TXA_SCALE_SHIFT
- R200_TXA_TFACTOR1_SEL_MASK
- R200_TXA_TFACTOR1_SEL_SHIFT
- R200_TXA_TFACTOR_SEL_MASK
- R200_TXA_TFACTOR_SEL_SHIFT
- R200_TXC_ARG_A_CURRENT_ALPHA
- R200_TXC_ARG_A_CURRENT_COLOR
- R200_TXC_ARG_A_DIFFUSE_ALPHA
- R200_TXC_ARG_A_DIFFUSE_COLOR
- R200_TXC_ARG_A_MASK
- R200_TXC_ARG_A_R0_ALPHA
- R200_TXC_ARG_A_R0_COLOR
- R200_TXC_ARG_A_R1_ALPHA
- R200_TXC_ARG_A_R1_COLOR
- R200_TXC_ARG_A_R2_ALPHA
- R200_TXC_ARG_A_R2_COLOR
- R200_TXC_ARG_A_R3_ALPHA
- R200_TXC_ARG_A_R3_COLOR
- R200_TXC_ARG_A_R4_ALPHA
- R200_TXC_ARG_A_R4_COLOR
- R200_TXC_ARG_A_R5_ALPHA
- R200_TXC_ARG_A_R5_COLOR
- R200_TXC_ARG_A_SHIFT
- R200_TXC_ARG_A_SPECULAR_ALPHA
- R200_TXC_ARG_A_SPECULAR_COLOR
- R200_TXC_ARG_A_TFACTOR1_ALPHA
- R200_TXC_ARG_A_TFACTOR1_COLOR
- R200_TXC_ARG_A_TFACTOR_ALPHA
- R200_TXC_ARG_A_TFACTOR_COLOR
- R200_TXC_ARG_A_ZERO
- R200_TXC_ARG_B_CURRENT_ALPHA
- R200_TXC_ARG_B_CURRENT_COLOR
- R200_TXC_ARG_B_DIFFUSE_ALPHA
- R200_TXC_ARG_B_DIFFUSE_COLOR
- R200_TXC_ARG_B_MASK
- R200_TXC_ARG_B_R0_ALPHA
- R200_TXC_ARG_B_R0_COLOR
- R200_TXC_ARG_B_R1_ALPHA
- R200_TXC_ARG_B_R1_COLOR
- R200_TXC_ARG_B_R2_ALPHA
- R200_TXC_ARG_B_R2_COLOR
- R200_TXC_ARG_B_R3_ALPHA
- R200_TXC_ARG_B_R3_COLOR
- R200_TXC_ARG_B_R4_ALPHA
- R200_TXC_ARG_B_R4_COLOR
- R200_TXC_ARG_B_R5_ALPHA
- R200_TXC_ARG_B_R5_COLOR
- R200_TXC_ARG_B_SHIFT
- R200_TXC_ARG_B_SPECULAR_ALPHA
- R200_TXC_ARG_B_SPECULAR_COLOR
- R200_TXC_ARG_B_TFACTOR1_ALPHA
- R200_TXC_ARG_B_TFACTOR1_COLOR
- R200_TXC_ARG_B_TFACTOR_ALPHA
- R200_TXC_ARG_B_TFACTOR_COLOR
- R200_TXC_ARG_B_ZERO
- R200_TXC_ARG_C_CURRENT_ALPHA
- R200_TXC_ARG_C_CURRENT_COLOR
- R200_TXC_ARG_C_DIFFUSE_ALPHA
- R200_TXC_ARG_C_DIFFUSE_COLOR
- R200_TXC_ARG_C_MASK
- R200_TXC_ARG_C_R0_ALPHA
- R200_TXC_ARG_C_R0_COLOR
- R200_TXC_ARG_C_R1_ALPHA
- R200_TXC_ARG_C_R1_COLOR
- R200_TXC_ARG_C_R2_ALPHA
- R200_TXC_ARG_C_R2_COLOR
- R200_TXC_ARG_C_R3_ALPHA
- R200_TXC_ARG_C_R3_COLOR
- R200_TXC_ARG_C_R4_ALPHA
- R200_TXC_ARG_C_R4_COLOR
- R200_TXC_ARG_C_R5_ALPHA
- R200_TXC_ARG_C_R5_COLOR
- R200_TXC_ARG_C_SHIFT
- R200_TXC_ARG_C_SPECULAR_ALPHA
- R200_TXC_ARG_C_SPECULAR_COLOR
- R200_TXC_ARG_C_TFACTOR1_ALPHA
- R200_TXC_ARG_C_TFACTOR1_COLOR
- R200_TXC_ARG_C_TFACTOR_ALPHA
- R200_TXC_ARG_C_TFACTOR_COLOR
- R200_TXC_ARG_C_ZERO
- R200_TXC_BIAS_ARG_A
- R200_TXC_BIAS_ARG_B
- R200_TXC_BIAS_ARG_C
- R200_TXC_CLAMP_0_1
- R200_TXC_CLAMP_8_8
- R200_TXC_CLAMP_MASK
- R200_TXC_CLAMP_SHIFT
- R200_TXC_CLAMP_WRAP
- R200_TXC_COMP_ARG_A
- R200_TXC_COMP_ARG_A_SHIFT
- R200_TXC_COMP_ARG_B
- R200_TXC_COMP_ARG_B_SHIFT
- R200_TXC_COMP_ARG_C
- R200_TXC_COMP_ARG_C_SHIFT
- R200_TXC_NEG_ARG_A
- R200_TXC_NEG_ARG_B
- R200_TXC_NEG_ARG_C
- R200_TXC_OP_CND0
- R200_TXC_OP_CONDITIONAL
- R200_TXC_OP_DOT2_ADD
- R200_TXC_OP_DOT3
- R200_TXC_OP_DOT4
- R200_TXC_OP_LERP
- R200_TXC_OP_MADD
- R200_TXC_OP_MASK
- R200_TXC_OUTPUT_MASK_B
- R200_TXC_OUTPUT_MASK_G
- R200_TXC_OUTPUT_MASK_GB
- R200_TXC_OUTPUT_MASK_MASK
- R200_TXC_OUTPUT_MASK_NONE
- R200_TXC_OUTPUT_MASK_R
- R200_TXC_OUTPUT_MASK_RB
- R200_TXC_OUTPUT_MASK_RG
- R200_TXC_OUTPUT_MASK_RGB
- R200_TXC_OUTPUT_REG_MASK
- R200_TXC_OUTPUT_REG_NONE
- R200_TXC_OUTPUT_REG_R0
- R200_TXC_OUTPUT_REG_R1
- R200_TXC_OUTPUT_REG_R2
- R200_TXC_OUTPUT_REG_R3
- R200_TXC_OUTPUT_REG_R4
- R200_TXC_OUTPUT_REG_R5
- R200_TXC_REPL_ARG_A_MASK
- R200_TXC_REPL_ARG_A_SHIFT
- R200_TXC_REPL_ARG_B_MASK
- R200_TXC_REPL_ARG_B_SHIFT
- R200_TXC_REPL_ARG_C_MASK
- R200_TXC_REPL_ARG_C_SHIFT
- R200_TXC_REPL_BLUE
- R200_TXC_REPL_GREEN
- R200_TXC_REPL_NORMAL
- R200_TXC_REPL_RED
- R200_TXC_SCALE_1X
- R200_TXC_SCALE_2X
- R200_TXC_SCALE_4X
- R200_TXC_SCALE_8X
- R200_TXC_SCALE_ARG_A
- R200_TXC_SCALE_ARG_B
- R200_TXC_SCALE_ARG_C
- R200_TXC_SCALE_INV2
- R200_TXC_SCALE_INV4
- R200_TXC_SCALE_INV8
- R200_TXC_SCALE_MASK
- R200_TXC_SCALE_SHIFT
- R200_TXC_TFACTOR1_SEL_MASK
- R200_TXC_TFACTOR1_SEL_SHIFT
- R200_TXC_TFACTOR_SEL_MASK
- R200_TXC_TFACTOR_SEL_SHIFT
- R200_TXFORMAT_ABGR8888
- R200_TXFORMAT_AI88
- R200_TXFORMAT_ALPHA_IN_MAP
- R200_TXFORMAT_ALPHA_MASK_ENABLE
- R200_TXFORMAT_ARGB1555
- R200_TXFORMAT_ARGB4444
- R200_TXFORMAT_ARGB8888
- R200_TXFORMAT_AVYU4444
- R200_TXFORMAT_BGR111110
- R200_TXFORMAT_CHROMA_KEY_ENABLE
- R200_TXFORMAT_CUBIC_MAP_ENABLE
- R200_TXFORMAT_DVDU88
- R200_TXFORMAT_DXT1
- R200_TXFORMAT_DXT23
- R200_TXFORMAT_DXT45
- R200_TXFORMAT_F5_HEIGHT_MASK
- R200_TXFORMAT_F5_HEIGHT_SHIFT
- R200_TXFORMAT_F5_WIDTH_MASK
- R200_TXFORMAT_F5_WIDTH_SHIFT
- R200_TXFORMAT_FORMAT_MASK
- R200_TXFORMAT_FORMAT_SHIFT
- R200_TXFORMAT_GR1616
- R200_TXFORMAT_HEIGHT_MASK
- R200_TXFORMAT_HEIGHT_SHIFT
- R200_TXFORMAT_I8
- R200_TXFORMAT_LDVDU655
- R200_TXFORMAT_LDVDU8888
- R200_TXFORMAT_LOOKUP_DISABLE
- R200_TXFORMAT_NON_POWER2
- R200_TXFORMAT_RGB332
- R200_TXFORMAT_RGB565
- R200_TXFORMAT_RGBA8888
- R200_TXFORMAT_ST_ROUTE_MASK
- R200_TXFORMAT_ST_ROUTE_SHIFT
- R200_TXFORMAT_ST_ROUTE_STQ0
- R200_TXFORMAT_ST_ROUTE_STQ1
- R200_TXFORMAT_ST_ROUTE_STQ2
- R200_TXFORMAT_ST_ROUTE_STQ3
- R200_TXFORMAT_ST_ROUTE_STQ4
- R200_TXFORMAT_ST_ROUTE_STQ5
- R200_TXFORMAT_VYUY422
- R200_TXFORMAT_WIDTH_MASK
- R200_TXFORMAT_WIDTH_SHIFT
- R200_TXFORMAT_Y8
- R200_TXFORMAT_YVYU422
- R200_TXO_ENDIAN_BYTE_SWAP
- R200_TXO_ENDIAN_HALFDW_SWAP
- R200_TXO_ENDIAN_NO_SWAP
- R200_TXO_ENDIAN_WORD_SWAP
- R200_TXO_MACRO_LINEAR
- R200_TXO_MACRO_TILE
- R200_TXO_MICRO_LINEAR
- R200_TXO_MICRO_TILE
- R200_TXO_OFFSET_MASK
- R200_TXO_OFFSET_SHIFT
- R200_UPDATE_USER_COLOR_0_ENA_MASK
- R200_VAP_D3D_TEX_DEFAULT
- R200_VAP_DX_CLIP_SPACE_DEF
- R200_VAP_FORCE_W_TO_ONE
- R200_VAP_SINGLE_BUF_STATE_ENABLE
- R200_VAP_TCL_ENABLE
- R200_VAP_VF_MAX_VTX_NUM
- R200_VAP_VF_MAX_VTX_NUM__SHIFT
- R200_VC_16BIT_SWAP
- R200_VC_32BIT_SWAP
- R200_VC_NO_SWAP
- R200_VF_MAX_VTX_INDX
- R200_VF_MIN_VTX_INDX
- R200_VPORT_X_OFFSET_ENA
- R200_VPORT_X_SCALE_ENA
- R200_VPORT_Y_OFFSET_ENA
- R200_VPORT_Y_SCALE_ENA
- R200_VPORT_Z_OFFSET_ENA
- R200_VPORT_Z_SCALE_ENA
- R200_VTX_COLOR_0_SHIFT
- R200_VTX_COLOR_1_SHIFT
- R200_VTX_COLOR_2_SHIFT
- R200_VTX_COLOR_3_SHIFT
- R200_VTX_COLOR_4_SHIFT
- R200_VTX_COLOR_5_SHIFT
- R200_VTX_COLOR_6_SHIFT
- R200_VTX_COLOR_7_SHIFT
- R200_VTX_COLOR_MASK
- R200_VTX_COLOR_NOT_PRESENT
- R200_VTX_DISCRETE_FOG
- R200_VTX_FP_RGB
- R200_VTX_FP_RGBA
- R200_VTX_N0
- R200_VTX_N1
- R200_VTX_PK_RGBA
- R200_VTX_POINT_SIZE
- R200_VTX_PV_MATRIX_SEL
- R200_VTX_SHININESS_0
- R200_VTX_SHININESS_1
- R200_VTX_STQ0_D3D
- R200_VTX_STQ1_D3D
- R200_VTX_STQ2_D3D
- R200_VTX_STQ3_D3D
- R200_VTX_STQ4_D3D
- R200_VTX_STQ5_D3D
- R200_VTX_ST_DENORMALIZED
- R200_VTX_TEX0_COMP_CNT_SHIFT
- R200_VTX_TEX1_COMP_CNT_SHIFT
- R200_VTX_TEX2_COMP_CNT_SHIFT
- R200_VTX_TEX3_COMP_CNT_SHIFT
- R200_VTX_TEX4_COMP_CNT_SHIFT
- R200_VTX_TEX5_COMP_CNT_SHIFT
- R200_VTX_W0
- R200_VTX_W0_FMT
- R200_VTX_W0_NORMALIZE
- R200_VTX_W1
- R200_VTX_WEIGHT_COUNT_SHIFT
- R200_VTX_XY
- R200_VTX_XY1
- R200_VTX_XY_FMT
- R200_VTX_Z0
- R200_VTX_Z1
- R200_VTX_Z_FMT
- R200_WRAPEN_S
- R200_WRAPEN_T
- R200_YUV_TEMPERATURE_COOL
- R200_YUV_TEMPERATURE_HOT
- R200_YUV_TEMPERATURE_MASK
- R200_YUV_TO_RGB
- R204_CMD_ARG
- R2057_AFELOOPBACK_AACI_RESP_CORE0
- R2057_AFELOOPBACK_AACI_RESP_CORE1
- R2057_AFEREG_CONFIG
- R2057_AFE_SET_VCM_I_CORE0
- R2057_AFE_SET_VCM_I_CORE1
- R2057_AFE_SET_VCM_Q_CORE0
- R2057_AFE_SET_VCM_Q_CORE1
- R2057_AFE_STATUS_VCM_IQADC_CORE0
- R2057_AFE_STATUS_VCM_IQADC_CORE1
- R2057_AFE_STATUS_VCM_I_CORE0
- R2057_AFE_STATUS_VCM_I_CORE1
- R2057_AFE_STATUS_VCM_Q_CORE0
- R2057_AFE_STATUS_VCM_Q_CORE1
- R2057_AFE_VCM_CAL_MASTER_CORE0
- R2057_AFE_VCM_CAL_MASTER_CORE1
- R2057_BACKUP1_CORE0
- R2057_BACKUP1_CORE1
- R2057_BACKUP2_CORE0
- R2057_BACKUP2_CORE1
- R2057_BACKUP3_CORE0
- R2057_BACKUP3_CORE1
- R2057_BACKUP4_CORE0
- R2057_BACKUP4_CORE1
- R2057_BANDGAP_CONFIG
- R2057_BANDGAP_RCAL_TRIM
- R2057_BUFS_MISC_LPFBW_CORE0
- R2057_BUFS_MISC_LPFBW_CORE1
- R2057_CLPO_CONFIG
- R2057_CMOSBUF_RX2GI_IDACS
- R2057_CMOSBUF_RX2GQ_IDACS
- R2057_CMOSBUF_RX5GI_IDACS
- R2057_CMOSBUF_RX5GQ_IDACS
- R2057_CMOSBUF_RX_RCCR
- R2057_CMOSBUF_SHAREIQ_PTAT
- R2057_CMOSBUF_TX2GI_IDACS
- R2057_CMOSBUF_TX2GQ_IDACS
- R2057_CMOSBUF_TX5GI_IDACS
- R2057_CMOSBUF_TX5GQ_IDACS
- R2057_CMOSBUF_TX_RCCR
- R2057_CP_KPD_IDAC
- R2057_DACBUF_IDACS_BW_CORE0
- R2057_DACBUF_IDACS_BW_CORE1
- R2057_DACBUF_VINCM_CORE0
- R2057_DACBUF_VINCM_CORE1
- R2057_GPAIO_CONFIG
- R2057_GPAIO_SEL0
- R2057_GPAIO_SEL1
- R2057_IDCODE
- R2057_IPA2G_BIAS_FILTER_CORE0
- R2057_IPA2G_BIAS_FILTER_CORE1
- R2057_IPA2G_CASCOFFV_CORE0
- R2057_IPA2G_CASCOFFV_CORE1
- R2057_IPA2G_CASCONV_CORE0
- R2057_IPA2G_CASCONV_CORE1
- R2057_IPA2G_GAIN_CORE0
- R2057_IPA2G_GAIN_CORE1
- R2057_IPA2G_IMAIN_CORE0
- R2057_IPA2G_IMAIN_CORE1
- R2057_IPA2G_TUNEV_CASCV_PTAT_CORE0
- R2057_IPA2G_TUNEV_CASCV_PTAT_CORE1
- R2057_IPA5G_BIAS_FILTER_CORE0
- R2057_IPA5G_BIAS_FILTER_CORE1
- R2057_IPA5G_CASCOFFV_PU_CORE0
- R2057_IPA5G_CASCOFFV_PU_CORE1
- R2057_IPA5G_CASCONV_CORE0
- R2057_IPA5G_CASCONV_CORE1
- R2057_IPA5G_GAIN_CORE0
- R2057_IPA5G_GAIN_CORE1
- R2057_IPA5G_IAUX_CORE0
- R2057_IPA5G_IAUX_CORE1
- R2057_IPA5G_IMAIN_CORE0
- R2057_IPA5G_IMAIN_CORE1
- R2057_IPA5G_PTAT_CORE0
- R2057_IPA5G_PTAT_CORE1
- R2057_IQTEST_SEL_PU
- R2057_JTAGXTAL_SIZE_CPBIAS_FILTRES
- R2057_LNA15G_INPUT_MATCH_TUNE_CORE0
- R2057_LNA15G_INPUT_MATCH_TUNE_CORE1
- R2057_LNA1_IMAIN_PTAT_PU_CORE0
- R2057_LNA1_IMAIN_PTAT_PU_CORE1
- R2057_LNA2G_GAIN_CORE0
- R2057_LNA2G_GAIN_CORE1
- R2057_LNA2G_TUNE_CORE0
- R2057_LNA2G_TUNE_CORE1
- R2057_LNA2_IAUX_PTAT_CORE0
- R2057_LNA2_IAUX_PTAT_CORE1
- R2057_LNA2_IMAIN_PTAT_PU_CORE0
- R2057_LNA2_IMAIN_PTAT_PU_CORE1
- R2057_LNA5G_GAIN_CORE0
- R2057_LNA5G_GAIN_CORE1
- R2057_LNA5G_RFEN_CORE0
- R2057_LNA5G_RFEN_CORE1
- R2057_LNA5G_TUNE_CORE0
- R2057_LNA5G_TUNE_CORE1
- R2057_LOGEN_INDBUF2G_IBOOST
- R2057_LOGEN_INDBUF2G_IDAC
- R2057_LOGEN_INDBUF2G_TUNE
- R2057_LOGEN_INDBUF5G_IBOOST
- R2057_LOGEN_INDBUF5G_IDAC
- R2057_LOGEN_INDBUF5G_TUNE
- R2057_LOGEN_MX2G_IDACS
- R2057_LOGEN_MX2G_TUNE
- R2057_LOGEN_MX5G_IDACS
- R2057_LOGEN_MX5G_RCCR
- R2057_LOGEN_MX5G_TUNE
- R2057_LOGEN_PTAT_RESETS
- R2057_LOGEN_PUS
- R2057_LOGEN_SEL_PKDET
- R2057_LPFBYP_DCLOOP_BYP_IDAC_CORE0
- R2057_LPFBYP_DCLOOP_BYP_IDAC_CORE1
- R2057_LPFSEL_TXRX_RXBB_PUS_CORE0
- R2057_LPFSEL_TXRX_RXBB_PUS_CORE1
- R2057_LPF_GAIN_CORE0
- R2057_LPF_GAIN_CORE1
- R2057_LPF_IDACS_CORE0
- R2057_LPF_IDACS_CORE1
- R2057_LPF_RESP_RXBUF_BW_CORE0
- R2057_LPF_RESP_RXBUF_BW_CORE1
- R2057_LPF_VCMREF_TXBUF_VCMREF_CORE0
- R2057_LPF_VCMREF_TXBUF_VCMREF_CORE1
- R2057_NB_IDACS_I_CORE0
- R2057_NB_IDACS_I_CORE1
- R2057_NB_IDACS_Q_CORE0
- R2057_NB_IDACS_Q_CORE1
- R2057_NB_MASTER_CORE0
- R2057_NB_MASTER_CORE1
- R2057_OVR_REG0
- R2057_OVR_REG1
- R2057_OVR_REG2
- R2057_OVR_REG3
- R2057_OVR_REG4
- R2057_PAD2G_BOOST_PU_CORE0
- R2057_PAD2G_BOOST_PU_CORE1
- R2057_PAD2G_CASCV_GAIN_CORE0
- R2057_PAD2G_CASCV_GAIN_CORE1
- R2057_PAD2G_IDACS_CORE0
- R2057_PAD2G_IDACS_CORE1
- R2057_PAD2G_PTATS_CORE0
- R2057_PAD2G_PTATS_CORE1
- R2057_PAD2G_TUNE_PUS_CORE0
- R2057_PAD2G_TUNE_PUS_CORE1
- R2057_PAD5G_CASCOFFV_GAIN_PUS_CORE0
- R2057_PAD5G_CASCOFFV_GAIN_PUS_CORE1
- R2057_PAD5G_CASCV_IMAIN_CORE0
- R2057_PAD5G_CASCV_IMAIN_CORE1
- R2057_PAD5G_CLASS_PTATS2_CORE0
- R2057_PAD5G_CLASS_PTATS2_CORE1
- R2057_PAD5G_PTATS1_CORE0
- R2057_PAD5G_PTATS1_CORE1
- R2057_PAD5G_TUNE_MISC_PUS_CORE0
- R2057_PAD5G_TUNE_MISC_PUS_CORE1
- R2057_PAD_BIAS_FILTER_BWS_CORE0
- R2057_PAD_BIAS_FILTER_BWS_CORE1
- R2057_PGA_BOOSTPTAT_IMAIN_CORE0
- R2057_PGA_BOOSTPTAT_IMAIN_CORE1
- R2057_PGA_BOOST_TUNE_CORE0
- R2057_PGA_BOOST_TUNE_CORE1
- R2057_PGA_GAIN_CORE0
- R2057_PGA_GAIN_CORE1
- R2057_PGA_PTAT_TXGM5G_PU_CORE0
- R2057_PGA_PTAT_TXGM5G_PU_CORE1
- R2057_RCAL_CONFIG
- R2057_RCAL_STATUS
- R2057_RCCAL_BCAP_VAL
- R2057_RCCAL_CAP_SIZE
- R2057_RCCAL_DONE_OSCCAP
- R2057_RCCAL_HPC_VAL
- R2057_RCCAL_MASTER
- R2057_RCCAL_N0_0
- R2057_RCCAL_N0_1
- R2057_RCCAL_N1_0
- R2057_RCCAL_N1_1
- R2057_RCCAL_OVERRIDES
- R2057_RCCAL_SCAP_VAL
- R2057_RCCAL_START_R1_Q1_P1
- R2057_RCCAL_TRC0
- R2057_RCCAL_TRC1
- R2057_RCCAL_X1
- R2057_RFPLL_IDACS
- R2057_RFPLL_LOOPFILTER_C1
- R2057_RFPLL_LOOPFILTER_C2
- R2057_RFPLL_LOOPFILTER_C3
- R2057_RFPLL_LOOPFILTER_R1
- R2057_RFPLL_LOOPFILTER_R2
- R2057_RFPLL_MASTER
- R2057_RFPLL_MISC_CAL_RESETN
- R2057_RFPLL_MISC_EN
- R2057_RFPLL_MMD0
- R2057_RFPLL_MMD1
- R2057_RFPLL_PFD_RESET_PW
- R2057_RFPLL_REFMASTER_SPAREXTALSIZE
- R2057_RSSI_GPAIOSEL_W1_IDACS_CORE0
- R2057_RSSI_GPAIOSEL_W1_IDACS_CORE1
- R2057_RSSI_MASTER_CORE0
- R2057_RSSI_MASTER_CORE1
- R2057_RXBB_BIAS_MASTER_CORE0
- R2057_RXBB_BIAS_MASTER_CORE1
- R2057_RXBB_CC_CORE0
- R2057_RXBB_CC_CORE1
- R2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE0
- R2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE1
- R2057_RXBB_RCCAL_HPC_CORE0
- R2057_RXBB_RCCAL_HPC_CORE1
- R2057_RXBB_SPARE1_CORE0
- R2057_RXBB_SPARE1_CORE1
- R2057_RXBB_SPARE2_CORE0
- R2057_RXBB_SPARE2_CORE1
- R2057_RXBB_SPARE3_CORE0
- R2057_RXBB_SPARE3_CORE1
- R2057_RXBB_VGABUF_IDACS_CORE0
- R2057_RXBB_VGABUF_IDACS_CORE1
- R2057_RXBUF_DEGEN_CORE0
- R2057_RXBUF_DEGEN_CORE1
- R2057_RXGM_CMFBITAIL_AUXPTAT_CORE0
- R2057_RXGM_CMFBITAIL_AUXPTAT_CORE1
- R2057_RXMIX2G_LODC_QI_CORE0
- R2057_RXMIX2G_LODC_QI_CORE1
- R2057_RXMIX2G_PUS_CORE0
- R2057_RXMIX2G_PUS_CORE1
- R2057_RXMIX2G_VCMREFS_CORE0
- R2057_RXMIX2G_VCMREFS_CORE1
- R2057_RXMIX5G_LODC_QI_CORE0
- R2057_RXMIX5G_LODC_QI_CORE1
- R2057_RXMIX5G_PUS_CORE0
- R2057_RXMIX5G_PUS_CORE1
- R2057_RXMIX5G_VCMREFS_CORE0
- R2057_RXMIX5G_VCMREFS_CORE1
- R2057_RXMIX_CMFBITAIL_PU_CORE0
- R2057_RXMIX_CMFBITAIL_PU_CORE1
- R2057_RXMIX_ICORE_RXGM_IAUX_CORE0
- R2057_RXMIX_ICORE_RXGM_IAUX_CORE1
- R2057_RXRFBIAS_BANDSEL_CORE0
- R2057_RXRFBIAS_BANDSEL_CORE1
- R2057_RXRFBIAS_IBOOST_PU_CORE0
- R2057_RXRFBIAS_IBOOST_PU_CORE1
- R2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE0
- R2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE1
- R2057_RXTXBIAS_CONFIG_CORE0
- R2057_RXTXBIAS_CONFIG_CORE1
- R2057_SPARE11_CORE0
- R2057_SPARE11_CORE1
- R2057_SPARE12_CORE0
- R2057_SPARE12_CORE1
- R2057_SPARE13_CORE0
- R2057_SPARE13_CORE1
- R2057_SPARE14_CORE0
- R2057_SPARE14_CORE1
- R2057_SPARE15_CORE0
- R2057_SPARE15_CORE1
- R2057_SPARE16_CORE0
- R2057_SPARE16_CORE1
- R2057_SPARE7_CORE1
- R2057_SPARE8_CORE1
- R2057_TEMPSENSE_CONFIG
- R2057_TIA_CONFIG_CORE0
- R2057_TIA_CONFIG_CORE1
- R2057_TIA_IBIAS1_CORE0
- R2057_TIA_IBIAS1_CORE1
- R2057_TIA_IBIAS2_CORE0
- R2057_TIA_IBIAS2_CORE1
- R2057_TIA_IQGAIN_CORE0
- R2057_TIA_IQGAIN_CORE1
- R2057_TIA_SPARE_I_CORE0
- R2057_TIA_SPARE_I_CORE1
- R2057_TIA_SPARE_Q_CORE0
- R2057_TIA_SPARE_Q_CORE1
- R2057_TR2G_CONFIG1_CORE0_NU
- R2057_TR2G_CONFIG1_CORE1_NU
- R2057_TR2G_CONFIG2_CORE0_NU
- R2057_TR2G_CONFIG2_CORE1_NU
- R2057_TR5G_CONFIG2_CORE0_NU
- R2057_TR5G_CONFIG2_CORE1_NU
- R2057_TSSI2G_SPARE1_CORE0
- R2057_TSSI2G_SPARE1_CORE1
- R2057_TSSI2G_SPARE2_CORE0
- R2057_TSSI2G_SPARE2_CORE1
- R2057_TSSI5G_SPARE1_CORE0
- R2057_TSSI5G_SPARE1_CORE1
- R2057_TSSI5G_SPARE2_CORE0
- R2057_TSSI5G_SPARE2_CORE1
- R2057_TX0_IQCAL_GAIN_BW
- R2057_TX0_IQCAL_IDAC
- R2057_TX0_IQCAL_VCM_HG
- R2057_TX0_LOFT_COARSE_I
- R2057_TX0_LOFT_COARSE_Q
- R2057_TX0_LOFT_FINE_I
- R2057_TX0_LOFT_FINE_Q
- R2057_TX0_TSSIA
- R2057_TX0_TSSIG
- R2057_TX0_TSSI_MISC1
- R2057_TX0_TSSI_VCM
- R2057_TX0_TXRXCOUPLE_2G_ATTEN
- R2057_TX0_TXRXCOUPLE_2G_PWRUP
- R2057_TX0_TXRXCOUPLE_5G_ATTEN
- R2057_TX0_TXRXCOUPLE_5G_PWRUP
- R2057_TX0_TX_SSI_MASTER
- R2057_TX0_TX_SSI_MUX
- R2057_TX1_IQCAL_GAIN_BW
- R2057_TX1_IQCAL_IDAC
- R2057_TX1_IQCAL_VCM_HG
- R2057_TX1_LOFT_COARSE_I
- R2057_TX1_LOFT_COARSE_Q
- R2057_TX1_LOFT_FINE_I
- R2057_TX1_LOFT_FINE_Q
- R2057_TX1_TSSIA
- R2057_TX1_TSSIG
- R2057_TX1_TSSI_MISC1
- R2057_TX1_TSSI_VCM
- R2057_TX1_TXRXCOUPLE_2G_ATTEN
- R2057_TX1_TXRXCOUPLE_2G_PWRUP
- R2057_TX1_TXRXCOUPLE_5G_ATTEN
- R2057_TX1_TXRXCOUPLE_5G_PWRUP
- R2057_TX1_TX_SSI_MASTER
- R2057_TX1_TX_SSI_MUX
- R2057_TX2G_BIAS_RESETS_CORE0
- R2057_TX2G_BIAS_RESETS_CORE1
- R2057_TX5G_BIAS_RESETS_CORE0
- R2057_TX5G_BIAS_RESETS_CORE1
- R2057_TX5G_PKDET_CORE0
- R2057_TX5G_PKDET_CORE1
- R2057_TXBUF_GAIN_CORE0
- R2057_TXBUF_GAIN_CORE1
- R2057_TXBUF_IDACS_CORE0
- R2057_TXBUF_IDACS_CORE1
- R2057_TXBUF_VINCM_CORE0
- R2057_TXBUF_VINCM_CORE1
- R2057_TXGM2G_PKDET_PUS_CORE0
- R2057_TXGM2G_PKDET_PUS_CORE1
- R2057_TXGM_GAIN_CORE0
- R2057_TXGM_GAIN_CORE1
- R2057_TXGM_IDAC_BLEED_CORE0
- R2057_TXGM_IDAC_BLEED_CORE1
- R2057_TXGM_TXRF_PUS_CORE0
- R2057_TXGM_TXRF_PUS_CORE1
- R2057_TXLPF_RCCAL_CORE0
- R2057_TXLPF_RCCAL_CORE1
- R2057_TXMIX2G_LODC_CORE0
- R2057_TXMIX2G_LODC_CORE1
- R2057_TXMIX2G_TUNE_BOOST_PU_CORE0
- R2057_TXMIX2G_TUNE_BOOST_PU_CORE1
- R2057_TXMIX5G_BOOST_TUNE_CORE0
- R2057_TXMIX5G_BOOST_TUNE_CORE1
- R2057_TXMIX5G_IBOOST_PAD_IAUX_CORE0
- R2057_TXMIX5G_IBOOST_PAD_IAUX_CORE1
- R2057_VCM_MASK
- R2057_VCOBUF_IDACS
- R2057_VCOBUF_TUNE
- R2057_VCOCAL_BIASRESET_RFPLLREG_VOUT
- R2057_VCOCAL_COUNTVAL0
- R2057_VCOCAL_COUNTVAL1
- R2057_VCOCAL_DELAY_AFTER_CLOSELOOP
- R2057_VCOCAL_DELAY_AFTER_OPENLOOP
- R2057_VCOCAL_DELAY_AFTER_REFRESH
- R2057_VCOCAL_DELAY_BEFORE_OPENLOOP
- R2057_VCOCAL_INTCLK_COUNT
- R2057_VCOCAL_MASTER
- R2057_VCOCAL_NUMCAPCHANGE
- R2057_VCOCAL_READCAP0
- R2057_VCOCAL_READCAP1
- R2057_VCOCAL_STATUS
- R2057_VCOCAL_WINSIZE
- R2057_VCOMONITOR_VTH_H
- R2057_VCOMONITOR_VTH_L
- R2057_VCO_ALCREF_BBPLLXTAL_SIZE
- R2057_VCO_FORCECAP0
- R2057_VCO_FORCECAPEN_FORCECAP1
- R2057_VCO_VARCSIZE_IDAC
- R2057_W12G_BW_LNA2G_PUS_CORE0
- R2057_W12G_BW_LNA2G_PUS_CORE1
- R2057_W15G_BW_LNA5G_PUS_CORE0
- R2057_W15G_BW_LNA5G_PUS_CORE1
- R2057_W2_IDACS0_I_CORE0
- R2057_W2_IDACS0_I_CORE1
- R2057_W2_IDACS0_Q_CORE0
- R2057_W2_IDACS0_Q_CORE1
- R2057_W2_IDACS1_I_CORE0
- R2057_W2_IDACS1_I_CORE1
- R2057_W2_IDACS1_Q_CORE0
- R2057_W2_IDACS1_Q_CORE1
- R2057_W2_MASTER_CORE0
- R2057_W2_MASTER_CORE1
- R2057_XTALPUOVR_PINCTRL
- R2057_XTAL_BUF_SIZE
- R2057_XTAL_CONFIG1
- R2057_XTAL_CONFIG2
- R2057_XTAL_ICORE_SIZE
- R2057_XTAL_PULLCAP_SIZE
- R2057v7_DACBUF_VINCM_CORE0
- R2057v7_IQTEST_SEL_PU2
- R2057v7_LOGEN_PUS1
- R2057v7_OVR_REG1
- R2057v7_OVR_REG10
- R2057v7_OVR_REG11
- R2057v7_OVR_REG12
- R2057v7_OVR_REG13
- R2057v7_OVR_REG14
- R2057v7_OVR_REG15
- R2057v7_OVR_REG16
- R2057v7_OVR_REG18
- R2057v7_OVR_REG19
- R2057v7_OVR_REG2
- R2057v7_OVR_REG20
- R2057v7_OVR_REG21
- R2057v7_OVR_REG23
- R2057v7_OVR_REG24
- R2057v7_OVR_REG25
- R2057v7_OVR_REG26
- R2057v7_OVR_REG27
- R2057v7_OVR_REG28
- R2057v7_OVR_REG5
- R2057v7_OVR_REG6
- R2057v7_OVR_REG7
- R2057v7_OVR_REG8
- R2057v7_OVR_REG9
- R2057v7_RCCAL_MASTER
- R2057v7_TR2G_CONFIG3_CORE0_NU
- R2057v7_TR2G_CONFIG3_CORE1_NU
- R2059_ALL
- R2059_C1
- R2059_C2
- R2059_C3
- R2059_RCAL_CONFIG
- R2059_RCAL_STATUS
- R2059_RCCAL_DONE_OSCCAP
- R2059_RCCAL_MASTER
- R2059_RCCAL_START_R1_Q1_P1
- R2059_RCCAL_TRC0
- R2059_RCCAL_X1
- R2059_RFPLL_MASTER
- R2059_RFPLL_MISC_CAL_RESETN
- R2059_RFPLL_MISC_EN
- R2059_XTAL_CONFIG2
- R208_DATAIO
- R20C_RESP
- R20_AGC11
- R20_DESC
- R20_GAIN_G1L
- R20_IR_MIX
- R20_MT9V011_READ_MODE
- R20_OFF
- R21
- R21C_STATUS
- R21_AGC12
- R21_GAIN_G1H
- R21_IF_AGC
- R21_MT_ADC
- R21_OFF
- R22
- R224_MODE
- R226_BLOCKSIZE
- R228_POWER
- R22_AGC13
- R22_DESC
- R22_GAIN_RL
- R22_IF1
- R22_OFF
- R22_SEL_LNA
- R22_SEL_MIC
- R22_SKIP_DCFIL
- R23
- R230_DATA
- R23_AGC21
- R23_AGC_EN
- R23_GAIN_RH
- R23_IF2
- R23_OFF
- R24
- R24_AGC22
- R24_GAIN_BL
- R24_IF3
- R24_OFF
- R25
- R25_AAGC
- R25_GAIN_BH
- R25_OFF
- R25_REF
- R26
- R26_GAIN_G2L
- R26_IF
- R26_OFF
- R26_RC
- R27
- R27_GAIN_G2H
- R27_OFF
- R27_RF1
- R27_RSSI
- R28
- R28_IRCAL1
- R28_OFF
- R28_QUANT
- R28_RF2
- R29
- R29_IRCAL2
- R29_LINE
- R29_OFF
- R29_RF3
- R2A_HIGH_BUDGET
- R2A_IRCAL3
- R2A_MSM1
- R2B
- R2BGR
- R2B_IRCAL4
- R2B_LOW_BUDGET
- R2B_MSM2
- R2B_MT9V011_GREEN_1_GAIN
- R2C_MT9V011_BLUE_GAIN
- R2C_POLARITY
- R2C_PS1
- R2C_RFCAL1
- R2D
- R2DF_MASK
- R2DM
- R2D_FPGA_IRQ_BASE
- R2D_MT9V011_RED_GAIN
- R2D_NR_IRL
- R2D_POINT
- R2D_PS2
- R2D_RFCAL2
- R2E0_INIT
- R2E4_STATUS_RESP
- R2E_MT9V011_GREEN_2_GAIN
- R2E_POINTH
- R2E_PS3
- R2E_RFCAL3
- R2F0_RESET
- R2FE_MASK
- R2F_POINTB
- R2F_RFCAL4
- R2F_RSSI1
- R2H
- R2I_DLY_ENC_0
- R2I_DLY_ENC_1
- R2I_DLY_ENC_2
- R2I_DLY_ENC_3
- R2MS_MASK
- R2T_PHY_DELAY
- R2_CARD_DT
- R2_CLKSEL_DSP
- R2_CLKSEL_DSP_IF
- R2_CLKSEL_GFX
- R2_CLKSEL_L3
- R2_CLKSEL_L4
- R2_CLKSEL_MDM
- R2_CLKSEL_MPU
- R2_CLKSEL_USB
- R2_CM_CLKSEL1_CORE_VAL
- R2_CM_CLKSEL_DSP_VAL
- R2_CM_CLKSEL_GFX_VAL
- R2_CM_CLKSEL_MDM_VAL
- R2_CM_CLKSEL_MPU_VAL
- R2_OFF
- R2_SPI_CARD_ECC_ERROR
- R2_SPI_CARD_LOCKED
- R2_SPI_CC_ERROR
- R2_SPI_CSD_OVERWRITE
- R2_SPI_ERASE_PARAM
- R2_SPI_ERROR
- R2_SPI_LOCK_UNLOCK_FAIL
- R2_SPI_OUT_OF_RANGE
- R2_SPI_WP_ERASE_SKIP
- R2_SPI_WP_VIOLATION
- R2_STACK_OFFSET
- R2x2x_CTRL2_PON
- R2x2x_CTRL2_VDET
- R2x2x_CTRL2_XSTP
- R3
- R30
- R300_221C_CLEAR
- R300_221C_NORMAL
- R300_2288_R300
- R300_2288_RV350
- R300_AA_DISABLE
- R300_AA_ENABLE
- R300_AA_SUBSAMPLES_2
- R300_AA_SUBSAMPLES_3
- R300_AA_SUBSAMPLES_4
- R300_AA_SUBSAMPLES_6
- R300_ALPHA_TEST_ENABLE
- R300_ALPHA_TEST_EQUAL
- R300_ALPHA_TEST_FAIL
- R300_ALPHA_TEST_GEQUAL
- R300_ALPHA_TEST_GREATER
- R300_ALPHA_TEST_LEQUAL
- R300_ALPHA_TEST_LESS
- R300_ALPHA_TEST_NEQUAL
- R300_ALPHA_TEST_OP_MASK
- R300_ALPHA_TEST_PASS
- R300_ANISO_THRESHOLD_MASK
- R300_BACK_PTYPE_LINE
- R300_BACK_PTYPE_POINT
- R300_BACK_PTYPE_TRIANGE
- R300_BLEND_ENABLE
- R300_BLEND_GL_CONST_ALPHA
- R300_BLEND_GL_CONST_COLOR
- R300_BLEND_GL_DST_ALPHA
- R300_BLEND_GL_DST_COLOR
- R300_BLEND_GL_ONE
- R300_BLEND_GL_ONE_MINUS_CONST_ALPHA
- R300_BLEND_GL_ONE_MINUS_CONST_COLOR
- R300_BLEND_GL_ONE_MINUS_DST_ALPHA
- R300_BLEND_GL_ONE_MINUS_DST_COLOR
- R300_BLEND_GL_ONE_MINUS_SRC_ALPHA
- R300_BLEND_GL_ONE_MINUS_SRC_COLOR
- R300_BLEND_GL_SRC_ALPHA
- R300_BLEND_GL_SRC_ALPHA_SATURATE
- R300_BLEND_GL_SRC_COLOR
- R300_BLEND_GL_ZERO
- R300_BLEND_MASK
- R300_BLEND_NO_SEPARATE
- R300_BLEND_UNKNOWN
- R300_CHROMA_KEY_BLEND
- R300_CHROMA_KEY_FORCE
- R300_CHROMA_KEY_MODE_DISABLE
- R300_CLIPRECT_MASK
- R300_CLIPRECT_OFFSET
- R300_CLIPRECT_X_MASK
- R300_CLIPRECT_X_SHIFT
- R300_CLIPRECT_Y_MASK
- R300_CLIPRECT_Y_SHIFT
- R300_CLIP_0
- R300_CLIP_1
- R300_CLIP_10
- R300_CLIP_2
- R300_CLIP_20
- R300_CLIP_21
- R300_CLIP_210
- R300_CLIP_3
- R300_CLIP_30
- R300_CLIP_31
- R300_CLIP_310
- R300_CLIP_32
- R300_CLIP_320
- R300_CLIP_321
- R300_CLIP_3210
- R300_CLIP_OUT
- R300_CMD_CP_DELAY
- R300_CMD_DMA_DISCARD
- R300_CMD_END3D
- R300_CMD_PACKET0
- R300_CMD_PACKET3
- R300_CMD_PACKET3_CLEAR
- R300_CMD_PACKET3_RAW
- R300_CMD_R500FP
- R300_CMD_SCRATCH
- R300_CMD_VPU
- R300_CMD_WAIT
- R300_COLORMASK0_A
- R300_COLORMASK0_B
- R300_COLORMASK0_G
- R300_COLORMASK0_R
- R300_COLOROFFSET_MASK
- R300_COLORPITCH_MASK
- R300_COLOR_ENDIAN_DWORD_SWAP
- R300_COLOR_ENDIAN_NO_SWAP
- R300_COLOR_ENDIAN_WORD_SWAP
- R300_COLOR_FORMAT_ARGB8888
- R300_COLOR_FORMAT_RGB565
- R300_COLOR_MICROTILE_ENABLE
- R300_COLOR_MICROTILE_SQUARE_ENABLE
- R300_COLOR_ROUND_NEAREST
- R300_COLOR_ROUND_TRUNC
- R300_COLOR_TILE_ENABLE
- R300_COMB_FCN_ADD_CLAMP
- R300_COMB_FCN_ADD_NOCLAMP
- R300_COMB_FCN_MAX
- R300_COMB_FCN_MIN
- R300_COMB_FCN_RSUB_CLAMP
- R300_COMB_FCN_RSUB_NOCLAMP
- R300_COMB_FCN_SUB_CLAMP
- R300_COMB_FCN_SUB_NOCLAMP
- R300_CP_CMD_BITBLT_MULTI
- R300_CP_COLOR_FORMAT_ARGB1555
- R300_CP_COLOR_FORMAT_ARGB4444
- R300_CP_COLOR_FORMAT_ARGB8888
- R300_CP_COLOR_FORMAT_CI8
- R300_CP_COLOR_FORMAT_RGB332
- R300_CP_COLOR_FORMAT_RGB565
- R300_CP_COLOR_FORMAT_RGB8
- R300_CP_PACKET0_REG_MASK
- R300_CP_RESYNC_ADDR
- R300_CP_RESYNC_DATA
- R300_CRTC2_TILE_X0_Y0
- R300_CRTC_MACRO_TILE_EN
- R300_CRTC_MACRO_TILE_EN_RIGHT
- R300_CRTC_MICRO_TILE_BUFFER_AUTO
- R300_CRTC_MICRO_TILE_BUFFER_DIS
- R300_CRTC_MICRO_TILE_BUFFER_DOUBLE
- R300_CRTC_MICRO_TILE_BUFFER_MASK
- R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO
- R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS
- R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE
- R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK
- R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE
- R300_CRTC_MICRO_TILE_BUFFER_SINGLE
- R300_CRTC_MICRO_TILE_EN
- R300_CRTC_MICRO_TILE_EN_RIGHT
- R300_CRTC_TILE_X0_Y0
- R300_CRTC_X_Y_MODE_EN
- R300_CRTC_X_Y_MODE_EN_RIGHT
- R300_CUBE_FIFO_HIGHWATER_COL_SHIFT
- R300_CULL_BACK
- R300_CULL_FRONT
- R300_DC_AUTOFLUSH_ENABLE
- R300_DC_DC_DISABLE_IGNORE_PE
- R300_DEPTHENDIAN_DWORD_SWAP
- R300_DEPTHENDIAN_HALF_DWORD_SWAP
- R300_DEPTHENDIAN_NO_SWAP
- R300_DEPTHENDIAN_WORD_SWAP
- R300_DEPTHFORMAT_16BIT_13E3
- R300_DEPTHFORMAT_16BIT_INT_Z
- R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL
- R300_DEPTHMACROTILE_DISABLE
- R300_DEPTHMACROTILE_ENABLE
- R300_DEPTHMICROTILE_LINEAR
- R300_DEPTHMICROTILE_TILED
- R300_DEPTHMICROTILE_TILED_SQUARE
- R300_DEPTHPITCH_MASK
- R300_DEPTHX_OFFSET_MASK
- R300_DEPTHX_OFFSET_SHIFT
- R300_DEPTHY_OFFSET_MASK
- R300_DEPTHY_OFFSET_SHIFT
- R300_DISABLE_MC_MCLKA
- R300_DISABLE_MC_MCLKB
- R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF
- R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF
- R300_DST_BLEND_SHIFT
- R300_DST_PIPE_CONFIG
- R300_DVOCLK_ALWAYS_ONb
- R300_EASY_TX_FORMAT
- R300_EB_UNK1
- R300_EB_UNK1_SHIFT
- R300_EB_UNK2
- R300_EDGE_ANISO_EDGE_DIAG
- R300_EDGE_ANISO_EDGE_ONLY
- R300_ENABLE_TILING
- R300_FAST_FILL_DISABLE
- R300_FAST_FILL_ENABLE
- R300_FCN_MASK
- R300_FOG_COLOR_B
- R300_FOG_COLOR_G
- R300_FOG_COLOR_R
- R300_FOG_ENABLE
- R300_FOG_MODE_EXP
- R300_FOG_MODE_EXP2
- R300_FOG_MODE_LINEAR
- R300_FOG_MODE_MASK
- R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE
- R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE
- R300_FP2_DVO_CLOCK_MODE_SINGLE
- R300_FP2_DVO_DUAL_CHANNEL_EN
- R300_FPI0_ARG0C_ABS
- R300_FPI0_ARG0C_MASK
- R300_FPI0_ARG0C_NEG
- R300_FPI0_ARG0C_SHIFT
- R300_FPI0_ARG1C_ABS
- R300_FPI0_ARG1C_MASK
- R300_FPI0_ARG1C_NEG
- R300_FPI0_ARG1C_SHIFT
- R300_FPI0_ARG2C_ABS
- R300_FPI0_ARG2C_MASK
- R300_FPI0_ARG2C_NEG
- R300_FPI0_ARG2C_SHIFT
- R300_FPI0_ARGC_HALF
- R300_FPI0_ARGC_ONE
- R300_FPI0_ARGC_SRC0A
- R300_FPI0_ARGC_SRC0CA_WZY
- R300_FPI0_ARGC_SRC0C_XXX
- R300_FPI0_ARGC_SRC0C_XYZ
- R300_FPI0_ARGC_SRC0C_YYY
- R300_FPI0_ARGC_SRC0C_YZX
- R300_FPI0_ARGC_SRC0C_ZXY
- R300_FPI0_ARGC_SRC0C_ZZZ
- R300_FPI0_ARGC_SRC1A
- R300_FPI0_ARGC_SRC1CA_WZY
- R300_FPI0_ARGC_SRC1C_LRP
- R300_FPI0_ARGC_SRC1C_XXX
- R300_FPI0_ARGC_SRC1C_XYZ
- R300_FPI0_ARGC_SRC1C_YYY
- R300_FPI0_ARGC_SRC1C_YZX
- R300_FPI0_ARGC_SRC1C_ZXY
- R300_FPI0_ARGC_SRC1C_ZZZ
- R300_FPI0_ARGC_SRC2A
- R300_FPI0_ARGC_SRC2CA_WZY
- R300_FPI0_ARGC_SRC2C_XXX
- R300_FPI0_ARGC_SRC2C_XYZ
- R300_FPI0_ARGC_SRC2C_YYY
- R300_FPI0_ARGC_SRC2C_YZX
- R300_FPI0_ARGC_SRC2C_ZXY
- R300_FPI0_ARGC_SRC2C_ZZZ
- R300_FPI0_ARGC_ZERO
- R300_FPI0_INSERT_NOP
- R300_FPI0_OUTC_CMP
- R300_FPI0_OUTC_CMPH
- R300_FPI0_OUTC_DP3
- R300_FPI0_OUTC_DP4
- R300_FPI0_OUTC_FRC
- R300_FPI0_OUTC_MAD
- R300_FPI0_OUTC_MAX
- R300_FPI0_OUTC_MIN
- R300_FPI0_OUTC_REPL_ALPHA
- R300_FPI0_OUTC_SAT
- R300_FPI0_SPECIAL_LRP
- R300_FPI1_DSTC_MASK
- R300_FPI1_DSTC_OUTPUT_MASK_SHIFT
- R300_FPI1_DSTC_OUTPUT_X
- R300_FPI1_DSTC_OUTPUT_Y
- R300_FPI1_DSTC_OUTPUT_Z
- R300_FPI1_DSTC_REG_MASK_SHIFT
- R300_FPI1_DSTC_REG_X
- R300_FPI1_DSTC_REG_Y
- R300_FPI1_DSTC_REG_Z
- R300_FPI1_DSTC_SHIFT
- R300_FPI1_SRC0C_CONST
- R300_FPI1_SRC0C_MASK
- R300_FPI1_SRC0C_SHIFT
- R300_FPI1_SRC1C_CONST
- R300_FPI1_SRC1C_MASK
- R300_FPI1_SRC1C_SHIFT
- R300_FPI1_SRC2C_CONST
- R300_FPI1_SRC2C_MASK
- R300_FPI1_SRC2C_SHIFT
- R300_FPI1_SRC_MASK
- R300_FPI2_ARG0A_ABS
- R300_FPI2_ARG0A_MASK
- R300_FPI2_ARG0A_NEG
- R300_FPI2_ARG0A_SHIFT
- R300_FPI2_ARG1A_ABS
- R300_FPI2_ARG1A_MASK
- R300_FPI2_ARG1A_NEG
- R300_FPI2_ARG1A_SHIFT
- R300_FPI2_ARG2A_ABS
- R300_FPI2_ARG2A_MASK
- R300_FPI2_ARG2A_NEG
- R300_FPI2_ARG2A_SHIFT
- R300_FPI2_ARGA_HALF
- R300_FPI2_ARGA_ONE
- R300_FPI2_ARGA_SRC0A
- R300_FPI2_ARGA_SRC0C_X
- R300_FPI2_ARGA_SRC0C_Y
- R300_FPI2_ARGA_SRC0C_Z
- R300_FPI2_ARGA_SRC1A
- R300_FPI2_ARGA_SRC1A_LRP
- R300_FPI2_ARGA_SRC1C_X
- R300_FPI2_ARGA_SRC1C_Y
- R300_FPI2_ARGA_SRC1C_Z
- R300_FPI2_ARGA_SRC2A
- R300_FPI2_ARGA_SRC2C_X
- R300_FPI2_ARGA_SRC2C_Y
- R300_FPI2_ARGA_SRC2C_Z
- R300_FPI2_ARGA_ZERO
- R300_FPI2_OUTA_CMP
- R300_FPI2_OUTA_DP4
- R300_FPI2_OUTA_EX2
- R300_FPI2_OUTA_FRC
- R300_FPI2_OUTA_LG2
- R300_FPI2_OUTA_MAD
- R300_FPI2_OUTA_MAX
- R300_FPI2_OUTA_MIN
- R300_FPI2_OUTA_RCP
- R300_FPI2_OUTA_RSQ
- R300_FPI2_OUTA_SAT
- R300_FPI2_SPECIAL_LRP
- R300_FPI2_UNKNOWN_31
- R300_FPI3_DSTA_DEPTH
- R300_FPI3_DSTA_MASK
- R300_FPI3_DSTA_OUTPUT
- R300_FPI3_DSTA_REG
- R300_FPI3_DSTA_SHIFT
- R300_FPI3_SRC0A_CONST
- R300_FPI3_SRC0A_MASK
- R300_FPI3_SRC0A_SHIFT
- R300_FPI3_SRC1A_CONST
- R300_FPI3_SRC1A_MASK
- R300_FPI3_SRC1A_SHIFT
- R300_FPI3_SRC2A_CONST
- R300_FPI3_SRC2A_MASK
- R300_FPI3_SRC2A_SHIFT
- R300_FPI3_SRC_MASK
- R300_FPITX_DST_MASK
- R300_FPITX_DST_SHIFT
- R300_FPITX_IMAGE_MASK
- R300_FPITX_IMAGE_SHIFT
- R300_FPITX_OPCODE_MASK
- R300_FPITX_OPCODE_SHIFT
- R300_FPITX_OP_KIL
- R300_FPITX_OP_TEX
- R300_FPITX_OP_TXB
- R300_FPITX_OP_TXP
- R300_FPITX_SRC_CONST
- R300_FPITX_SRC_MASK
- R300_FPITX_SRC_SHIFT
- R300_FRONT_FACE_CCW
- R300_FRONT_FACE_CW
- R300_FRONT_PTYPE_LINE
- R300_FRONT_PTYPE_POINT
- R300_FRONT_PTYPE_TRIANGE
- R300_GA_DEADLOCK_CNTL
- R300_GA_ENHANCE
- R300_GA_FASTSYNC_CNTL
- R300_GA_POLY_MODE
- R300_GA_ROUND_MODE
- R300_GB_AA_CONFIG
- R300_GB_DEPTH_SELECT_1_1_W
- R300_GB_DEPTH_SELECT_Z
- R300_GB_ENABLE
- R300_GB_FIFO_SIZE
- R300_GB_FIFO_SIZE_128
- R300_GB_FIFO_SIZE_256
- R300_GB_FIFO_SIZE_32
- R300_GB_FIFO_SIZE_64
- R300_GB_FOG_SELECT_1_1_W
- R300_GB_FOG_SELECT_C0A
- R300_GB_FOG_SELECT_C1A
- R300_GB_FOG_SELECT_C2A
- R300_GB_FOG_SELECT_C3A
- R300_GB_FOG_SELECT_Z
- R300_GB_LINE_STUFF_ENABLE
- R300_GB_MSPOS0
- R300_GB_MSPOS0__MSBD0_X
- R300_GB_MSPOS0__MSBD0_Y
- R300_GB_MSPOS0__MS_X0_SHIFT
- R300_GB_MSPOS0__MS_X1_SHIFT
- R300_GB_MSPOS0__MS_X2_SHIFT
- R300_GB_MSPOS0__MS_Y0_SHIFT
- R300_GB_MSPOS0__MS_Y1_SHIFT
- R300_GB_MSPOS0__MS_Y2_SHIFT
- R300_GB_MSPOS1
- R300_GB_MSPOS1__MSBD1
- R300_GB_MSPOS1__MS_X3_SHIFT
- R300_GB_MSPOS1__MS_X4_SHIFT
- R300_GB_MSPOS1__MS_X5_SHIFT
- R300_GB_MSPOS1__MS_Y3_SHIFT
- R300_GB_MSPOS1__MS_Y4_SHIFT
- R300_GB_MSPOS1__MS_Y5_SHIFT
- R300_GB_POINT_STUFF_ENABLE
- R300_GB_SELECT
- R300_GB_STENCIL_AUTO_ENABLE
- R300_GB_SUBPIXEL_1_12
- R300_GB_SUBPIXEL_1_16
- R300_GB_SUPER_SIZE_1
- R300_GB_SUPER_SIZE_128
- R300_GB_SUPER_SIZE_16
- R300_GB_SUPER_SIZE_2
- R300_GB_SUPER_SIZE_32
- R300_GB_SUPER_SIZE_4
- R300_GB_SUPER_SIZE_64
- R300_GB_SUPER_SIZE_8
- R300_GB_SUPER_TILE_A
- R300_GB_SUPER_TILE_B
- R300_GB_SUPER_X_SHIFT
- R300_GB_SUPER_Y_SHIFT
- R300_GB_TEX0_SOURCE_SHIFT
- R300_GB_TEX1_SOURCE_SHIFT
- R300_GB_TEX2_SOURCE_SHIFT
- R300_GB_TEX3_SOURCE_SHIFT
- R300_GB_TEX4_SOURCE_SHIFT
- R300_GB_TEX5_SOURCE_SHIFT
- R300_GB_TEX6_SOURCE_SHIFT
- R300_GB_TEX7_SOURCE_SHIFT
- R300_GB_TEX_REPLICATE
- R300_GB_TEX_ST
- R300_GB_TEX_STR
- R300_GB_TILE_CONFIG
- R300_GB_TILE_ENABLE
- R300_GB_TILE_PIPE_COUNT_R300
- R300_GB_TILE_PIPE_COUNT_R420
- R300_GB_TILE_PIPE_COUNT_RV300
- R300_GB_TILE_PIPE_COUNT_RV410
- R300_GB_TILE_SIZE_16
- R300_GB_TILE_SIZE_32
- R300_GB_TILE_SIZE_8
- R300_GB_TRIANGLE_STUFF_ENABLE
- R300_GB_UNK31
- R300_GB_VAP_RASTER_VTX_FMT_0
- R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT
- R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT
- R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT
- R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT
- R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE
- R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT
- R300_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT
- R300_GB_VAP_RASTER_VTX_FMT_1
- R300_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT
- R300_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT
- R300_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT
- R300_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT
- R300_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT
- R300_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT
- R300_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT
- R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT
- R300_GB_W_SELECT_1
- R300_GB_W_SELECT_1_W
- R300_GEOMETRY_ROUND_NEAREST
- R300_GEOMETRY_ROUND_TRUNC
- R300_HIZ_DISABLE
- R300_HIZ_ENABLE
- R300_HIZ_MAX
- R300_HIZ_MIN
- R300_HPD_SEL
- R300_INPUT_CNTL_0_COLOR
- R300_INPUT_CNTL_COLOR
- R300_INPUT_CNTL_NORMAL
- R300_INPUT_CNTL_POS
- R300_INPUT_CNTL_TC0
- R300_INPUT_CNTL_TC1
- R300_INPUT_CNTL_TC2
- R300_INPUT_CNTL_TC3
- R300_INPUT_CNTL_TC4
- R300_INPUT_CNTL_TC5
- R300_INPUT_CNTL_TC6
- R300_INPUT_CNTL_TC7
- R300_INPUT_ROUTE_COMPONENTS_1
- R300_INPUT_ROUTE_COMPONENTS_2
- R300_INPUT_ROUTE_COMPONENTS_3
- R300_INPUT_ROUTE_COMPONENTS_4
- R300_INPUT_ROUTE_COMPONENTS_RGBA
- R300_INPUT_ROUTE_ENABLE
- R300_INPUT_ROUTE_FLOAT
- R300_INPUT_ROUTE_FLOAT_COLOR
- R300_INPUT_ROUTE_IMMEDIATE_MODE
- R300_INPUT_ROUTE_SELECT_MASK
- R300_INPUT_ROUTE_SELECT_ONE
- R300_INPUT_ROUTE_SELECT_W
- R300_INPUT_ROUTE_SELECT_X
- R300_INPUT_ROUTE_SELECT_Y
- R300_INPUT_ROUTE_SELECT_Z
- R300_INPUT_ROUTE_SELECT_ZERO
- R300_INPUT_ROUTE_UNSIGNED_BYTE
- R300_INPUT_ROUTE_W_SHIFT
- R300_INPUT_ROUTE_X_SHIFT
- R300_INPUT_ROUTE_Y_SHIFT
- R300_INPUT_ROUTE_Z_SHIFT
- R300_INVERT_13E3_LEADING_ONES
- R300_INVERT_13E3_LEADING_ZEROS
- R300_LINESIZE_MASK
- R300_LINESIZE_MAX
- R300_LINESIZE_SHIFT
- R300_LINE_CNT_HO
- R300_LINE_CNT_VE
- R300_LOD_BIAS_MASK
- R300_LVDS_SRC_SEL_CRTC1
- R300_LVDS_SRC_SEL_CRTC2
- R300_LVDS_SRC_SEL_MASK
- R300_LVDS_SRC_SEL_RMX
- R300_MAX_CB
- R300_MC_COORD_TRUNCATE_DISABLE
- R300_MC_COORD_TRUNCATE_MPEG
- R300_MC_DISP0R_INIT_LAT_MASK
- R300_MC_DISP0R_INIT_LAT_SHIFT
- R300_MC_DISP1R_INIT_LAT_MASK
- R300_MC_DISP1R_INIT_LAT_SHIFT
- R300_MC_IDLE
- R300_MC_IND_ADDR_MASK
- R300_MC_IND_DATA
- R300_MC_IND_INDEX
- R300_MC_IND_WR_EN
- R300_MC_INIT_GFX_LAT_TIMER
- R300_MC_INIT_MISC_LAT_TIMER
- R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT
- R300_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT
- R300_MC_MISC__MC_DISP1R_INIT_LAT_SHIFT
- R300_MC_MISC__MC_E2R_INIT_LAT_SHIFT
- R300_MC_MISC__MC_FIXED_INIT_LAT_SHIFT
- R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT
- R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT
- R300_MC_MISC__MC_G3D2R_INIT_LAT_SHIFT
- R300_MC_MISC__MC_G3D3R_INIT_LAT_SHIFT
- R300_MC_MISC__MC_GLOBR_INIT_LAT_SHIFT
- R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT
- R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT
- R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT
- R300_MC_MISC__MC_TX0R_INIT_LAT_SHIFT
- R300_MC_MISC__MC_TX1R_INIT_LAT_SHIFT
- R300_MC_MISC__MC_VF_INIT_LAT_SHIFT
- R300_MC_READ_CNTL_AB
- R300_MC_READ_CNTL_CD_mcind
- R300_MC_ROUND_MPEG4
- R300_MC_ROUND_NORMAL
- R300_MEM_NUM_CHANNELS_MASK
- R300_MEM_PWRUP_COMPLETE
- R300_MEM_PWRUP_COMPL_C
- R300_MEM_PWRUP_COMPL_D
- R300_MEM_RBS_POSITION_A_MASK
- R300_MEM_RBS_POSITION_C_MASK
- R300_MEM_USE_CD_CH_ONLY
- R300_MSBD0_X_SHIFT
- R300_MSBD0_Y_SHIFT
- R300_MSBD1_SHIFT
- R300_MS_X0_SHIFT
- R300_MS_X1_SHIFT
- R300_MS_X2_SHIFT
- R300_MS_X3_SHIFT
- R300_MS_X4_SHIFT
- R300_MS_X5_SHIFT
- R300_MS_Y0_SHIFT
- R300_MS_Y1_SHIFT
- R300_MS_Y2_SHIFT
- R300_MS_Y3_SHIFT
- R300_MS_Y4_SHIFT
- R300_MS_Y5_SHIFT
- R300_NEW_WAIT_2D_2D_CLEAN
- R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN
- R300_NEW_WAIT_2D_3D
- R300_NEW_WAIT_3D_3D_CLEAN
- R300_OCCLUSION_ON
- R300_OFIFO_HIGHWATER_SHIFT
- R300_P2G2CLK_ALWAYS_ONb
- R300_P2G2CLK_DAC_ALWAYS_ONb
- R300_PACKET3_3D_DRAW_INDX_2
- R300_PACKET3_3D_DRAW_VBUF
- R300_PACKET3_3D_DRAW_VBUF_2
- R300_PACKET3_3D_LOAD_VBPNTR
- R300_PACKET3_INDX_BUFFER
- R300_PFS_CNTL_0
- R300_PFS_CNTL_1
- R300_PFS_CNTL_2
- R300_PFS_CNTL_ALU_END_MASK
- R300_PFS_CNTL_ALU_END_SHIFT
- R300_PFS_CNTL_ALU_OFFSET_MASK
- R300_PFS_CNTL_ALU_OFFSET_SHIFT
- R300_PFS_CNTL_FIRST_NODE_HAS_TEX
- R300_PFS_CNTL_LAST_NODES_MASK
- R300_PFS_CNTL_LAST_NODES_SHIFT
- R300_PFS_CNTL_TEX_END_MASK
- R300_PFS_CNTL_TEX_END_SHIFT
- R300_PFS_CNTL_TEX_OFFSET_MASK
- R300_PFS_CNTL_TEX_OFFSET_SHIFT
- R300_PFS_INSTR0_0
- R300_PFS_INSTR1_0
- R300_PFS_INSTR2_0
- R300_PFS_INSTR3_0
- R300_PFS_NODE_0
- R300_PFS_NODE_1
- R300_PFS_NODE_2
- R300_PFS_NODE_3
- R300_PFS_NODE_ALU_END_MASK
- R300_PFS_NODE_ALU_END_SHIFT
- R300_PFS_NODE_ALU_OFFSET_MASK
- R300_PFS_NODE_ALU_OFFSET_SHIFT
- R300_PFS_NODE_OUTPUT_COLOR
- R300_PFS_NODE_OUTPUT_DEPTH
- R300_PFS_NODE_TEX_END_MASK
- R300_PFS_NODE_TEX_END_SHIFT
- R300_PFS_NODE_TEX_OFFSET_MASK
- R300_PFS_NODE_TEX_OFFSET_SHIFT
- R300_PFS_PARAM_0_W
- R300_PFS_PARAM_0_X
- R300_PFS_PARAM_0_Y
- R300_PFS_PARAM_0_Z
- R300_PFS_PARAM_31_W
- R300_PFS_PARAM_31_X
- R300_PFS_PARAM_31_Y
- R300_PFS_PARAM_31_Z
- R300_PFS_TEXI_0
- R300_PIPE_AUTO_CONFIG
- R300_PIPE_COUNT_R300
- R300_PIPE_COUNT_R420
- R300_PIPE_COUNT_R420_3P
- R300_PIPE_COUNT_RV350
- R300_PIXCLK_DVO_ALWAYS_ONb
- R300_PIXCLK_TRANS_ALWAYS_ONb
- R300_PIXCLK_TVO_ALWAYS_ONb
- R300_PM_BACK_FILL
- R300_PM_BACK_LINE
- R300_PM_BACK_POINT
- R300_PM_ENABLED
- R300_PM_FRONT_FILL
- R300_PM_FRONT_LINE
- R300_PM_FRONT_POINT
- R300_POINTSIZE_MAX
- R300_POINTSIZE_X_MASK
- R300_POINTSIZE_X_SHIFT
- R300_POINTSIZE_Y_MASK
- R300_POINTSIZE_Y_SHIFT
- R300_PPLL_REF_DIV_ACC_MASK
- R300_PPLL_REF_DIV_ACC_SHIFT
- R300_PP_ALPHA_TEST
- R300_PRIM_COLOR_ORDER_BGRA
- R300_PRIM_COLOR_ORDER_RGBA
- R300_PRIM_NUM_VERTICES_MASK
- R300_PRIM_NUM_VERTICES_SHIFT
- R300_PRIM_TYPE_3VRT_LINE_LIST
- R300_PRIM_TYPE_3VRT_POINT_LIST
- R300_PRIM_TYPE_LINE
- R300_PRIM_TYPE_LINE_LOOP
- R300_PRIM_TYPE_LINE_STRIP
- R300_PRIM_TYPE_MASK
- R300_PRIM_TYPE_NONE
- R300_PRIM_TYPE_POINT
- R300_PRIM_TYPE_POINT_SPRITES
- R300_PRIM_TYPE_POLYGON
- R300_PRIM_TYPE_QUADS
- R300_PRIM_TYPE_QUAD_STRIP
- R300_PRIM_TYPE_RECT_LIST
- R300_PRIM_TYPE_TRI_FAN
- R300_PRIM_TYPE_TRI_LIST
- R300_PRIM_TYPE_TRI_STRIP
- R300_PRIM_TYPE_TRI_TYPE2
- R300_PRIM_WALK_IND
- R300_PRIM_WALK_LIST
- R300_PRIM_WALK_MASK
- R300_PRIM_WALK_RING
- R300_PTE_READABLE
- R300_PTE_UNSNOOPED
- R300_PTE_WRITEABLE
- R300_PVS_CNTL_1_POS_END_SHIFT
- R300_PVS_CNTL_1_PROGRAM_END_SHIFT
- R300_PVS_CNTL_1_PROGRAM_START_SHIFT
- R300_PVS_CNTL_2_PARAM_COUNT_SHIFT
- R300_PVS_CNTL_2_PARAM_OFFSET_SHIFT
- R300_PVS_CNTL_3_PROGRAM_UNKNOWN2_SHIFT
- R300_PVS_CNTL_3_PROGRAM_UNKNOWN_SHIFT
- R300_PVS_UPLOAD_PARAMETERS
- R300_PVS_UPLOAD_POINTSIZE
- R300_PVS_UPLOAD_PROGRAM
- R300_RB2D_DSTCACHE_MODE
- R300_RB3D_AARESOLVE_CTL
- R300_RB3D_AARESOLVE_OFFSET
- R300_RB3D_AARESOLVE_PITCH
- R300_RB3D_ABLEND
- R300_RB3D_BLEND_COLOR
- R300_RB3D_CBLEND
- R300_RB3D_COLORMASK
- R300_RB3D_COLOROFFSET0
- R300_RB3D_COLOROFFSET1
- R300_RB3D_COLOROFFSET2
- R300_RB3D_COLOROFFSET3
- R300_RB3D_COLORPITCH0
- R300_RB3D_COLORPITCH1
- R300_RB3D_COLORPITCH2
- R300_RB3D_COLORPITCH3
- R300_RB3D_DC_FINISH
- R300_RB3D_DC_FLUSH
- R300_RB3D_DC_FREE
- R300_RB3D_DSTCACHE_CTLSTAT
- R300_RB3D_DSTCACHE_UNKNOWN_02
- R300_RB3D_DSTCACHE_UNKNOWN_0A
- R300_RB3D_ZCACHE_CTLSTAT
- R300_RD_COMP_DISABLE
- R300_RD_COMP_ENABLE
- R300_REF_ALPHA_MASK
- R300_RE_CLIPRECT_BR_0
- R300_RE_CLIPRECT_BR_1
- R300_RE_CLIPRECT_BR_2
- R300_RE_CLIPRECT_BR_3
- R300_RE_CLIPRECT_CNTL
- R300_RE_CLIPRECT_TL_0
- R300_RE_CLIPRECT_TL_1
- R300_RE_CLIPRECT_TL_2
- R300_RE_CLIPRECT_TL_3
- R300_RE_CULL_CNTL
- R300_RE_FOG_SCALE
- R300_RE_FOG_START
- R300_RE_FOG_STATE
- R300_RE_LINE_CNT
- R300_RE_OCCLUSION_CNTL
- R300_RE_POINTSIZE
- R300_RE_POLYGON_MODE
- R300_RE_SCISSORS_BR
- R300_RE_SCISSORS_TL
- R300_RE_SHADE
- R300_RE_SHADE_MODEL
- R300_RE_SHADE_MODEL_FLAT
- R300_RE_SHADE_MODEL_SMOOTH
- R300_RE_UNK4238
- R300_RE_ZBIAS_CNTL
- R300_RE_ZBIAS_T_CONSTANT
- R300_RE_ZBIAS_T_FACTOR
- R300_RE_ZBIAS_W_CONSTANT
- R300_RE_ZBIAS_W_FACTOR
- R300_RS_CFIFO_SIZE_SHIFT
- R300_RS_CNTL_0
- R300_RS_CNTL_0_UNKNOWN_18
- R300_RS_CNTL_1
- R300_RS_CNTL_CI_CNT_SHIFT
- R300_RS_CNTL_TC_CNT_MASK
- R300_RS_CNTL_TC_CNT_SHIFT
- R300_RS_HIGHWATER_COL_SHIFT
- R300_RS_HIGHWATER_TEX_SHIFT
- R300_RS_INTERP_0
- R300_RS_INTERP_1
- R300_RS_INTERP_1_UNKNOWN
- R300_RS_INTERP_2
- R300_RS_INTERP_2_UNKNOWN
- R300_RS_INTERP_3
- R300_RS_INTERP_3_UNKNOWN
- R300_RS_INTERP_4
- R300_RS_INTERP_5
- R300_RS_INTERP_6
- R300_RS_INTERP_7
- R300_RS_INTERP_SRC_MASK
- R300_RS_INTERP_SRC_SHIFT
- R300_RS_INTERP_USED
- R300_RS_ROUTE_0
- R300_RS_ROUTE_0_COLOR
- R300_RS_ROUTE_0_COLOR_DEST_MASK
- R300_RS_ROUTE_0_COLOR_DEST_SHIFT
- R300_RS_ROUTE_1
- R300_RS_ROUTE_1_COLOR1
- R300_RS_ROUTE_1_COLOR1_DEST_MASK
- R300_RS_ROUTE_1_COLOR1_DEST_SHIFT
- R300_RS_ROUTE_1_UNKNOWN11
- R300_RS_ROUTE_2
- R300_RS_ROUTE_3
- R300_RS_ROUTE_4
- R300_RS_ROUTE_5
- R300_RS_ROUTE_6
- R300_RS_ROUTE_7
- R300_RS_ROUTE_DEST_MASK
- R300_RS_ROUTE_DEST_SHIFT
- R300_RS_ROUTE_ENABLE
- R300_RS_ROUTE_SOURCE_INTERP_0
- R300_RS_ROUTE_SOURCE_INTERP_1
- R300_RS_ROUTE_SOURCE_INTERP_2
- R300_RS_ROUTE_SOURCE_INTERP_3
- R300_RS_ROUTE_SOURCE_INTERP_4
- R300_RS_ROUTE_SOURCE_INTERP_5
- R300_RS_ROUTE_SOURCE_INTERP_6
- R300_RS_ROUTE_SOURCE_INTERP_7
- R300_RS_TFIFO_SIZE_SHIFT
- R300_SCISSORS_OFFSET
- R300_SCISSORS_X_MASK
- R300_SCISSORS_X_SHIFT
- R300_SCISSORS_Y_MASK
- R300_SCISSORS_Y_SHIFT
- R300_SCLK_CBA_MAX_DYN_STOP_LAT
- R300_SCLK_CNTL2
- R300_SCLK_FORCE_CBA
- R300_SCLK_FORCE_GA
- R300_SCLK_FORCE_PX
- R300_SCLK_FORCE_SR
- R300_SCLK_FORCE_SU
- R300_SCLK_FORCE_TCL
- R300_SCLK_FORCE_TX
- R300_SCLK_FORCE_US
- R300_SCLK_FORCE_VAP
- R300_SCLK_GA_MAX_DYN_STOP_LAT
- R300_SCLK_TCL_MAX_DYN_STOP_LAT
- R300_SC_BFIFO_SIZE_SHIFT
- R300_SC_EDGERULE
- R300_SC_HYPERZ
- R300_SC_HYPERZ_ADJ_128
- R300_SC_HYPERZ_ADJ_16
- R300_SC_HYPERZ_ADJ_2
- R300_SC_HYPERZ_ADJ_256
- R300_SC_HYPERZ_ADJ_32
- R300_SC_HYPERZ_ADJ_4
- R300_SC_HYPERZ_ADJ_64
- R300_SC_HYPERZ_ADJ_8
- R300_SC_HYPERZ_DISABLE
- R300_SC_HYPERZ_ENABLE
- R300_SC_HYPERZ_HZ_Z0MAX
- R300_SC_HYPERZ_HZ_Z0MAX_NO
- R300_SC_HYPERZ_HZ_Z0MIN
- R300_SC_HYPERZ_HZ_Z0MIN_NO
- R300_SC_HYPERZ_MAX
- R300_SC_HYPERZ_MIN
- R300_SC_IFIFO_SIZE_SHIFT
- R300_SC_TZFIFO_SIZE_SHIFT
- R300_SE_VPORT_XOFFSET
- R300_SE_VPORT_XSCALE
- R300_SE_VPORT_YOFFSET
- R300_SE_VPORT_YSCALE
- R300_SE_VPORT_ZOFFSET
- R300_SE_VPORT_ZSCALE
- R300_SE_VTE_CNTL
- R300_SRC_BLEND_SHIFT
- R300_STENCILMASK_MASK
- R300_STENCILMASK_SHIFT
- R300_STENCILREF_MASK
- R300_STENCILREF_SHIFT
- R300_STENCILWRITEMASK_MASK
- R300_STENCILWRITEMASK_SHIFT
- R300_STENCIL_ENABLE
- R300_STENCIL_FRONT_BACK
- R300_SUBPIXEL_1_12
- R300_SUBPIXEL_1_16
- R300_SURF_TILE_BOTH
- R300_SURF_TILE_COLOR_MACRO
- R300_SURF_TILE_DEPTH_32BPP
- R300_SURF_TILE_MACRO
- R300_SURF_TILE_MICRO
- R300_SURF_TILE_NONE
- R300_SU_REG_DEST
- R300_S_BACK_FUNC_SHIFT
- R300_S_BACK_SFAIL_OP_SHIFT
- R300_S_BACK_ZFAIL_OP_SHIFT
- R300_S_BACK_ZPASS_OP_SHIFT
- R300_S_FRONT_FUNC_SHIFT
- R300_S_FRONT_SFAIL_OP_SHIFT
- R300_S_FRONT_ZFAIL_OP_SHIFT
- R300_S_FRONT_ZPASS_OP_SHIFT
- R300_TILE_SIZE_16
- R300_TILE_SIZE_32
- R300_TILE_SIZE_8
- R300_TRACK_MAX_TEXTURE
- R300_TXO_ENDIAN_BYTE_SWAP
- R300_TXO_ENDIAN_HALFDW_SWAP
- R300_TXO_ENDIAN_NO_SWAP
- R300_TXO_ENDIAN_WORD_SWAP
- R300_TXO_MACRO_TILE
- R300_TXO_MICRO_TILE
- R300_TXO_MICRO_TILE_SQUARE
- R300_TXO_OFFSET_MASK
- R300_TXO_OFFSET_SHIFT
- R300_TX_BORDER_COLOR_0
- R300_TX_CHROMA_KEY_0
- R300_TX_CLAMP
- R300_TX_CLAMP_TO_BORDER
- R300_TX_CLAMP_TO_EDGE
- R300_TX_ENABLE
- R300_TX_ENABLE_0
- R300_TX_ENABLE_1
- R300_TX_ENABLE_10
- R300_TX_ENABLE_11
- R300_TX_ENABLE_12
- R300_TX_ENABLE_13
- R300_TX_ENABLE_14
- R300_TX_ENABLE_15
- R300_TX_ENABLE_2
- R300_TX_ENABLE_3
- R300_TX_ENABLE_4
- R300_TX_ENABLE_5
- R300_TX_ENABLE_6
- R300_TX_ENABLE_7
- R300_TX_ENABLE_8
- R300_TX_ENABLE_9
- R300_TX_FILTER1_0
- R300_TX_FILTER_0
- R300_TX_FLUSH
- R300_TX_FORMAT_0
- R300_TX_FORMAT_A8R8G8B8
- R300_TX_FORMAT_ALPHA_1CH
- R300_TX_FORMAT_ALPHA_2CH
- R300_TX_FORMAT_ALPHA_4CH
- R300_TX_FORMAT_ALPHA_NONE
- R300_TX_FORMAT_ATI2N
- R300_TX_FORMAT_A_SHIFT
- R300_TX_FORMAT_B8G8_B8G8
- R300_TX_FORMAT_B_SHIFT
- R300_TX_FORMAT_CONST_W
- R300_TX_FORMAT_CONST_X
- R300_TX_FORMAT_CONST_Y
- R300_TX_FORMAT_CONST_Z
- R300_TX_FORMAT_CUBIC_MAP
- R300_TX_FORMAT_CUT_W
- R300_TX_FORMAT_CUT_Z
- R300_TX_FORMAT_D3DMFT_CxV8U8
- R300_TX_FORMAT_DXT1
- R300_TX_FORMAT_DXT3
- R300_TX_FORMAT_DXT5
- R300_TX_FORMAT_FL_I16
- R300_TX_FORMAT_FL_I16A16
- R300_TX_FORMAT_FL_I32
- R300_TX_FORMAT_FL_I32A32
- R300_TX_FORMAT_FL_R16G16B16A16
- R300_TX_FORMAT_FL_R32G32B32A32
- R300_TX_FORMAT_G8R8_G8B8
- R300_TX_FORMAT_G_SHIFT
- R300_TX_FORMAT_ONE
- R300_TX_FORMAT_R_SHIFT
- R300_TX_FORMAT_UNK25
- R300_TX_FORMAT_W
- R300_TX_FORMAT_W16Z16Y16X16
- R300_TX_FORMAT_W1Z5Y5X5
- R300_TX_FORMAT_W2Z10Y10X10
- R300_TX_FORMAT_W4Z4Y4X4
- R300_TX_FORMAT_W8Z8Y8X8
- R300_TX_FORMAT_X
- R300_TX_FORMAT_X16
- R300_TX_FORMAT_X8
- R300_TX_FORMAT_Y
- R300_TX_FORMAT_Y16X16
- R300_TX_FORMAT_Y4X4
- R300_TX_FORMAT_Y8X8
- R300_TX_FORMAT_YUV_MODE
- R300_TX_FORMAT_Z
- R300_TX_FORMAT_Z10Y11X11
- R300_TX_FORMAT_Z11Y11X10
- R300_TX_FORMAT_Z3Y3X2
- R300_TX_FORMAT_Z5Y6X5
- R300_TX_FORMAT_Z6Y5X5
- R300_TX_FORMAT_ZERO
- R300_TX_HEIGHTMASK_MASK
- R300_TX_HEIGHTMASK_SHIFT
- R300_TX_INVALTAGS
- R300_TX_MAG_FILTER_LINEAR
- R300_TX_MAG_FILTER_MASK
- R300_TX_MAG_FILTER_NEAREST
- R300_TX_MAX_ANISO_16_TO_1
- R300_TX_MAX_ANISO_1_TO_1
- R300_TX_MAX_ANISO_2_TO_1
- R300_TX_MAX_ANISO_4_TO_1
- R300_TX_MAX_ANISO_8_TO_1
- R300_TX_MAX_ANISO_MASK
- R300_TX_MAX_MIP_LEVEL_MASK
- R300_TX_MAX_MIP_LEVEL_SHIFT
- R300_TX_MIN_FILTER_ANISO_LINEAR
- R300_TX_MIN_FILTER_ANISO_NEAREST
- R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR
- R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST
- R300_TX_MIN_FILTER_LINEAR
- R300_TX_MIN_FILTER_LINEAR_MIP_LINEAR
- R300_TX_MIN_FILTER_LINEAR_MIP_NEAREST
- R300_TX_MIN_FILTER_MASK
- R300_TX_MIN_FILTER_NEAREST
- R300_TX_MIN_FILTER_NEAREST_MIP_LINEAR
- R300_TX_MIN_FILTER_NEAREST_MIP_NEAREST
- R300_TX_MIRRORED
- R300_TX_OFFSET_0
- R300_TX_PITCH_0
- R300_TX_REPEAT
- R300_TX_SIZE_0
- R300_TX_SIZE_PROJECTED
- R300_TX_SIZE_TXPITCH_EN
- R300_TX_TRI_PERF_0_8
- R300_TX_TRI_PERF_1_4
- R300_TX_TRI_PERF_1_8
- R300_TX_TRI_PERF_3_8
- R300_TX_UNK23
- R300_TX_WIDTHMASK_MASK
- R300_TX_WIDTHMASK_SHIFT
- R300_TX_WRAP_Q_MASK
- R300_TX_WRAP_Q_SHIFT
- R300_TX_WRAP_S_MASK
- R300_TX_WRAP_S_SHIFT
- R300_TX_WRAP_T_MASK
- R300_TX_WRAP_T_SHIFT
- R300_US_OFIFO_SIZE_SHIFT
- R300_US_RAM_SIZE_SHIFT
- R300_US_WFIFO_SIZE_SHIFT
- R300_VAP_CLIP_X_0
- R300_VAP_CLIP_X_1
- R300_VAP_CLIP_Y_0
- R300_VAP_CLIP_Y_1
- R300_VAP_CNTL
- R300_VAP_CNTL_STATUS
- R300_VAP_INPUT_CNTL_0
- R300_VAP_INPUT_CNTL_1
- R300_VAP_INPUT_ROUTE_0_0
- R300_VAP_INPUT_ROUTE_0_1
- R300_VAP_INPUT_ROUTE_0_2
- R300_VAP_INPUT_ROUTE_0_3
- R300_VAP_INPUT_ROUTE_0_4
- R300_VAP_INPUT_ROUTE_0_5
- R300_VAP_INPUT_ROUTE_0_6
- R300_VAP_INPUT_ROUTE_0_7
- R300_VAP_INPUT_ROUTE_1_0
- R300_VAP_INPUT_ROUTE_1_1
- R300_VAP_INPUT_ROUTE_1_2
- R300_VAP_INPUT_ROUTE_1_3
- R300_VAP_INPUT_ROUTE_1_4
- R300_VAP_INPUT_ROUTE_1_5
- R300_VAP_INPUT_ROUTE_1_6
- R300_VAP_INPUT_ROUTE_1_7
- R300_VAP_INPUT_ROUTE_END
- R300_VAP_INPUT_ROUTE_IDX_MASK
- R300_VAP_INPUT_ROUTE_IDX_SHIFT
- R300_VAP_OUTPUT_VTX_FMT_0
- R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT
- R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT
- R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT
- R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT
- R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT
- R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT
- R300_VAP_OUTPUT_VTX_FMT_1
- R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT
- R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT
- R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT
- R300_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT
- R300_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT
- R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT
- R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT
- R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT
- R300_VAP_PVS_CNTL_1
- R300_VAP_PVS_CNTL_2
- R300_VAP_PVS_CNTL_3
- R300_VAP_PVS_STATE_FLUSH_REG
- R300_VAP_PVS_UPLOAD_ADDRESS
- R300_VAP_PVS_UPLOAD_DATA
- R300_VAP_TCL_BYPASS
- R300_VAP_UNKNOWN_221C
- R300_VAP_UNKNOWN_2288
- R300_VAP_VF_CNTL
- R300_VAP_VF_CNTL__COLOR_ORDER__SHIFT
- R300_VAP_VF_CNTL__INDEX_SIZE_32bit
- R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT
- R300_VAP_VF_CNTL__PRIM_LINES
- R300_VAP_VF_CNTL__PRIM_LINE_LOOP
- R300_VAP_VF_CNTL__PRIM_LINE_STRIP
- R300_VAP_VF_CNTL__PRIM_NONE
- R300_VAP_VF_CNTL__PRIM_POINTS
- R300_VAP_VF_CNTL__PRIM_POLYGON
- R300_VAP_VF_CNTL__PRIM_QUADS
- R300_VAP_VF_CNTL__PRIM_QUAD_STRIP
- R300_VAP_VF_CNTL__PRIM_TRIANGLES
- R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN
- R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP
- R300_VAP_VF_CNTL__PRIM_TYPE__SHIFT
- R300_VAP_VF_CNTL__PRIM_WALK_INDICES
- R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED
- R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED
- R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST
- R300_VAP_VF_CNTL__PRIM_WALK__SHIFT
- R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT
- R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT
- R300_VAP_VTX_COLOR_B
- R300_VAP_VTX_COLOR_G
- R300_VAP_VTX_COLOR_PKD
- R300_VAP_VTX_COLOR_R
- R300_VAP_VTX_END_OF_PKT
- R300_VAP_VTX_POS_0_X_1
- R300_VAP_VTX_POS_0_X_2
- R300_VAP_VTX_POS_0_Y_1
- R300_VAP_VTX_POS_0_Y_2
- R300_VAP_VTX_POS_0_Z_2
- R300_VC_16BIT_SWAP
- R300_VC_32BIT_SWAP
- R300_VC_NO_SWAP
- R300_VPI_IN_NEG_W
- R300_VPI_IN_NEG_X
- R300_VPI_IN_NEG_Y
- R300_VPI_IN_NEG_Z
- R300_VPI_IN_REG_CLASS_ATTRIBUTE
- R300_VPI_IN_REG_CLASS_MASK
- R300_VPI_IN_REG_CLASS_NONE
- R300_VPI_IN_REG_CLASS_PARAMETER
- R300_VPI_IN_REG_CLASS_TEMPORARY
- R300_VPI_IN_REG_INDEX_MASK
- R300_VPI_IN_REG_INDEX_SHIFT
- R300_VPI_IN_SELECT_MASK
- R300_VPI_IN_SELECT_ONE
- R300_VPI_IN_SELECT_W
- R300_VPI_IN_SELECT_X
- R300_VPI_IN_SELECT_Y
- R300_VPI_IN_SELECT_Z
- R300_VPI_IN_SELECT_ZERO
- R300_VPI_IN_W_SHIFT
- R300_VPI_IN_X_SHIFT
- R300_VPI_IN_Y_SHIFT
- R300_VPI_IN_Z_SHIFT
- R300_VPI_OUT_OP_ADD
- R300_VPI_OUT_OP_ARL
- R300_VPI_OUT_OP_DOT
- R300_VPI_OUT_OP_DST
- R300_VPI_OUT_OP_EX2
- R300_VPI_OUT_OP_EXP
- R300_VPI_OUT_OP_FRC
- R300_VPI_OUT_OP_LG2
- R300_VPI_OUT_OP_LIT
- R300_VPI_OUT_OP_LOG
- R300_VPI_OUT_OP_MAD
- R300_VPI_OUT_OP_MAD_2
- R300_VPI_OUT_OP_MAX
- R300_VPI_OUT_OP_MIN
- R300_VPI_OUT_OP_MUL
- R300_VPI_OUT_OP_POW
- R300_VPI_OUT_OP_RCP
- R300_VPI_OUT_OP_RSQ
- R300_VPI_OUT_OP_SGE
- R300_VPI_OUT_OP_SLT
- R300_VPI_OUT_OP_UNK12
- R300_VPI_OUT_OP_UNK129
- R300_VPI_OUT_OP_UNK67
- R300_VPI_OUT_OP_UNK73
- R300_VPI_OUT_REG_CLASS_ADDR
- R300_VPI_OUT_REG_CLASS_MASK
- R300_VPI_OUT_REG_CLASS_RESULT
- R300_VPI_OUT_REG_CLASS_TEMPORARY
- R300_VPI_OUT_REG_INDEX_MASK
- R300_VPI_OUT_REG_INDEX_SHIFT
- R300_VPI_OUT_WRITE_W
- R300_VPI_OUT_WRITE_X
- R300_VPI_OUT_WRITE_Y
- R300_VPI_OUT_WRITE_Z
- R300_VPORT_X_OFFSET_ENA
- R300_VPORT_X_SCALE_ENA
- R300_VPORT_Y_OFFSET_ENA
- R300_VPORT_Y_SCALE_ENA
- R300_VPORT_Z_OFFSET_ENA
- R300_VPORT_Z_SCALE_ENA
- R300_VTX_ST_DENORMALIZED
- R300_VTX_W0_FMT
- R300_VTX_W0_NORMALIZE
- R300_VTX_XY_FMT
- R300_VTX_Z_FMT
- R300_WAIT_2D
- R300_WAIT_2D_CLEAN
- R300_WAIT_3D
- R300_WAIT_3D_CLEAN
- R300_WR_COMP_DISABLE
- R300_WR_COMP_ENABLE
- R300_ZB_BW_CNTL
- R300_ZB_CB_CLEAR_CACHE_LINEAR
- R300_ZB_CB_CLEAR_RMW
- R300_ZB_CNTL
- R300_ZB_DEPTHCLEARVALUE
- R300_ZB_DEPTHOFFSET
- R300_ZB_DEPTHPITCH
- R300_ZB_DEPTHXY_OFFSET
- R300_ZB_FORMAT
- R300_ZB_HIZ_DWORD
- R300_ZB_HIZ_OFFSET
- R300_ZB_HIZ_PITCH
- R300_ZB_HIZ_RDINDEX
- R300_ZB_HIZ_WRINDEX
- R300_ZB_STENCILREFMASK
- R300_ZB_ZCACHE_CTLSTAT
- R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY
- R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE
- R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE
- R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT
- R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE
- R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT
- R300_ZB_ZMASK_DWORD
- R300_ZB_ZMASK_OFFSET
- R300_ZB_ZMASK_PITCH
- R300_ZB_ZMASK_RDINDEX
- R300_ZB_ZMASK_WRINDEX
- R300_ZB_ZPASS_ADDR
- R300_ZB_ZPASS_DATA
- R300_ZB_ZSTENCILCNTL
- R300_ZB_ZTOP
- R300_ZC_FLUSH
- R300_ZC_FLUSH_ALL
- R300_ZC_FREE
- R300_ZS_ALWAYS
- R300_ZS_DECR
- R300_ZS_DECR_WRAP
- R300_ZS_EQUAL
- R300_ZS_GEQUAL
- R300_ZS_GREATER
- R300_ZS_INCR
- R300_ZS_INCR_WRAP
- R300_ZS_INVERT
- R300_ZS_KEEP
- R300_ZS_LEQUAL
- R300_ZS_LESS
- R300_ZS_MASK
- R300_ZS_NEVER
- R300_ZS_NOTEQUAL
- R300_ZS_REPLACE
- R300_ZS_ZERO
- R300_ZTOP_DISABLE
- R300_ZTOP_ENABLE
- R300_Z_ENABLE
- R300_Z_FUNC_SHIFT
- R300_Z_SIGNED_COMPARE
- R300_Z_WRITE_ENABLE
- R30XX_CONF_AC
- R30XX_CONF_DBR
- R30XX_CONF_FDM
- R30XX_CONF_FPINT
- R30XX_CONF_HALT
- R30XX_CONF_LOCK
- R30XX_CONF_REV
- R30XX_CONF_RF
- R30XX_CONF_SB
- R30_OFF
- R30_POINTBH
- R30_RFCAL5
- R30_RSSI2
- R31
- R31_IRQ_CTRL
- R31_OFF
- R31_RFCAL6
- R31_UPD
- R32
- R32_DUMMY
- R32_RFCAL7
- R33_RFCAL8
- R33_TEST
- R34_MD1
- R34_RFCAL9
- R34_VID
- R35_MT9V011_GLOBAL_GAIN
- R35_RFCAL10
- R35_SD1
- R35_VIDH
- R367CAB_AGC_CTL
- R367CAB_AGC_IF_CFG
- R367CAB_AGC_IF_HTH_H
- R367CAB_AGC_IF_HTH_L
- R367CAB_AGC_IF_LTH_H
- R367CAB_AGC_IF_LTH_L
- R367CAB_AGC_PWM_CFG
- R367CAB_AGC_PWM_IFCMD_H
- R367CAB_AGC_PWM_IFCMD_L
- R367CAB_AGC_PWM_RFCMD_H
- R367CAB_AGC_PWM_RFCMD_L
- R367CAB_AGC_PWR_RD_H
- R367CAB_AGC_PWR_RD_L
- R367CAB_AGC_PWR_RD_M
- R367CAB_AGC_PWR_REF_H
- R367CAB_AGC_PWR_REF_L
- R367CAB_AGC_RF_CFG
- R367CAB_AGC_RF_TH_H
- R367CAB_AGC_RF_TH_L
- R367CAB_ALLPASSFILT1
- R367CAB_ALLPASSFILT10
- R367CAB_ALLPASSFILT11
- R367CAB_ALLPASSFILT2
- R367CAB_ALLPASSFILT3
- R367CAB_ALLPASSFILT4
- R367CAB_ALLPASSFILT5
- R367CAB_ALLPASSFILT6
- R367CAB_ALLPASSFILT7
- R367CAB_ALLPASSFILT8
- R367CAB_ALLPASSFILT9
- R367CAB_ANACTRL
- R367CAB_ANADIGCTRL
- R367CAB_AUX_CLK
- R367CAB_BERT_0
- R367CAB_BERT_1
- R367CAB_BERT_2
- R367CAB_BERT_3
- R367CAB_CTRL_1
- R367CAB_CTRL_2
- R367CAB_CTRL_STATUS
- R367CAB_DAC0R
- R367CAB_DAC1R
- R367CAB_DUAL_AD12
- R367CAB_EQU_CRL_BISTH_HI
- R367CAB_EQU_CRL_BISTH_LO
- R367CAB_EQU_CRL_LD_SEN
- R367CAB_EQU_CRL_LD_VAL
- R367CAB_EQU_CRL_LIMITER
- R367CAB_EQU_CRL_LPF_GAIN
- R367CAB_EQU_CRL_TFR
- R367CAB_EQU_CTR_CRL_CONTROL_H
- R367CAB_EQU_CTR_CRL_CONTROL_L
- R367CAB_EQU_CTR_HIPOW_H
- R367CAB_EQU_CTR_HIPOW_L
- R367CAB_EQU_CTR_LPF_GAIN
- R367CAB_EQU_ERR_GAIN
- R367CAB_EQU_FFE_LEAKAGE
- R367CAB_EQU_FFE_MAINTAP
- R367CAB_EQU_FFE_MAINTAP_POS
- R367CAB_EQU_GAIN_NARROW
- R367CAB_EQU_GAIN_WIDE
- R367CAB_EQU_GAMMA_HI
- R367CAB_EQU_GAMMA_LO
- R367CAB_EQU_GLOBAL_GAIN
- R367CAB_EQU_I_EQU_HI
- R367CAB_EQU_I_EQU_LO
- R367CAB_EQU_I_TESTTAP_H
- R367CAB_EQU_I_TESTTAP_L
- R367CAB_EQU_I_TESTTAP_M
- R367CAB_EQU_MAPPER
- R367CAB_EQU_MODULUS_MAP
- R367CAB_EQU_PNT_GAIN
- R367CAB_EQU_Q_EQU_HI
- R367CAB_EQU_Q_EQU_LO
- R367CAB_EQU_Q_TESTTAP_H
- R367CAB_EQU_Q_TESTTAP_L
- R367CAB_EQU_Q_TESTTAP_M
- R367CAB_EQU_RADIUS
- R367CAB_EQU_SNR_HI
- R367CAB_EQU_SNR_LO
- R367CAB_EQU_SWEEP_RANGE_HI
- R367CAB_EQU_SWEEP_RANGE_LO
- R367CAB_EQU_SWEEP_RATE
- R367CAB_EQU_TAP_CTRL
- R367CAB_EQU_TESTAP_CFG
- R367CAB_FEC_AC_CTR_0
- R367CAB_FEC_AC_CTR_1
- R367CAB_FEC_AC_CTR_2
- R367CAB_FEC_AC_CTR_3
- R367CAB_FEC_STATUS
- R367CAB_FREESYS1
- R367CAB_FREESYS2
- R367CAB_FREESYS3
- R367CAB_FSM_CONFIG
- R367CAB_FSM_CTL
- R367CAB_FSM_EQA1_HTH
- R367CAB_FSM_SNR0_HTH
- R367CAB_FSM_SNR0_LTH
- R367CAB_FSM_SNR1_HTH
- R367CAB_FSM_SNR1_LTH
- R367CAB_FSM_SNR2_HTH
- R367CAB_FSM_STATE
- R367CAB_FSM_STS
- R367CAB_FSM_TEMPO
- R367CAB_GPIO_CFG
- R367CAB_GPIO_CMD
- R367CAB_I2CRPT
- R367CAB_ID
- R367CAB_IOCFG0
- R367CAB_IOCFG1
- R367CAB_IOCFG2
- R367CAB_IQDEM_ADJ_AGC_REF
- R367CAB_IQDEM_ADJ_COEFF0
- R367CAB_IQDEM_ADJ_COEFF1
- R367CAB_IQDEM_ADJ_COEFF2
- R367CAB_IQDEM_ADJ_COEFF3
- R367CAB_IQDEM_ADJ_COEFF4
- R367CAB_IQDEM_ADJ_COEFF5
- R367CAB_IQDEM_ADJ_COEFF6
- R367CAB_IQDEM_ADJ_COEFF7
- R367CAB_IQDEM_ADJ_EN
- R367CAB_IQDEM_CFG
- R367CAB_IQDEM_DCRM_CFG_HH
- R367CAB_IQDEM_DCRM_CFG_HL
- R367CAB_IQDEM_DCRM_CFG_LH
- R367CAB_IQDEM_DCRM_CFG_LL
- R367CAB_IQDEM_GAIN_SRC_H
- R367CAB_IQDEM_GAIN_SRC_L
- R367CAB_IQ_QAM
- R367CAB_IT_EN1
- R367CAB_IT_EN2
- R367CAB_IT_STATUS1
- R367CAB_IT_STATUS2
- R367CAB_MIX_NCO_HH
- R367CAB_MIX_NCO_HL
- R367CAB_MIX_NCO_LL
- R367CAB_OUTFORMAT_0
- R367CAB_OUTFORMAT_1
- R367CAB_PLLMDIV
- R367CAB_PLLNDIV
- R367CAB_PLLSETUP
- R367CAB_RE_STATUS_0
- R367CAB_RE_STATUS_1
- R367CAB_RE_STATUS_2
- R367CAB_RE_STATUS_3
- R367CAB_RF_AGC1
- R367CAB_RF_AGC2
- R367CAB_RS_COUNTER_0
- R367CAB_RS_COUNTER_1
- R367CAB_RS_COUNTER_2
- R367CAB_RS_COUNTER_3
- R367CAB_RS_COUNTER_4
- R367CAB_RS_COUNTER_5
- R367CAB_SDFR
- R367CAB_SMOOTHER_2
- R367CAB_SRC_NCO_HH
- R367CAB_SRC_NCO_HL
- R367CAB_SRC_NCO_LH
- R367CAB_SRC_NCO_LL
- R367CAB_TEST_CTL
- R367CAB_TOPCTRL
- R367CAB_TRL_AGC_CFG
- R367CAB_TRL_LOCKDET_HTH
- R367CAB_TRL_LOCKDET_LTH
- R367CAB_TRL_LOCKDET_TRGVAL
- R367CAB_TRL_LPF_ACQ_GAIN
- R367CAB_TRL_LPF_CFG
- R367CAB_TRL_LPF_OUT_GAIN
- R367CAB_TRL_LPF_TRK_GAIN
- R367CAB_TSMF_CTRL_0
- R367CAB_TSMF_CTRL_1
- R367CAB_TSMF_CTRL_3
- R367CAB_TSTBIST
- R367CAB_TSTBUS
- R367CAB_TSTRES
- R367CAB_TS_ON_ID_0
- R367CAB_TS_ON_ID_1
- R367CAB_TS_ON_ID_2
- R367CAB_TS_ON_ID_3
- R367CAB_TS_STATUS_0
- R367CAB_TS_STATUS_1
- R367CAB_TS_STATUS_2
- R367CAB_TS_STATUS_3
- R367CAB_T_O_ID_0
- R367CAB_T_O_ID_1
- R367CAB_T_O_ID_2
- R367CAB_T_O_ID_3
- R367TER_AGC12C
- R367TER_AGC1MAX
- R367TER_AGC1MIN
- R367TER_AGC1VAL1
- R367TER_AGC1VAL2
- R367TER_AGC2MAX
- R367TER_AGC2MIN
- R367TER_AGC2PGA
- R367TER_AGC2TH
- R367TER_AGC2VAL1
- R367TER_AGC2VAL2
- R367TER_AGCCTRL1
- R367TER_AGCCTRL2
- R367TER_AGCR
- R367TER_AGCTAR_LOCK_LSBS
- R367TER_AGC_CTL
- R367TER_AGC_GAIN1
- R367TER_AGC_GAIN2
- R367TER_AGC_MANUAL1
- R367TER_AGC_MANUAL2
- R367TER_AGC_TARG
- R367TER_ALPHALSB
- R367TER_ALPHAMSB
- R367TER_ALPHANOISE
- R367TER_ALPHA_NOPISE_FREQ
- R367TER_ANACTRL
- R367TER_ANADIGCTRL
- R367TER_AUTORELOCK
- R367TER_AUT_AGC_TARGETMSB
- R367TER_AUT_CFG
- R367TER_AUT_GAIN_EN
- R367TER_AUX_CLK
- R367TER_BDI_CTL
- R367TER_BER_THR_LSB
- R367TER_BER_THR_MSB
- R367TER_BER_THR_VMSB
- R367TER_CAS_CTL
- R367TER_CAS_DAGCGAIN
- R367TER_CAS_FREQ
- R367TER_CCD
- R367TER_CHC_CTL
- R367TER_CHC_DUMMY
- R367TER_CHC_SNR
- R367TER_CHC_SNR_TARG
- R367TER_CHPFREE
- R367TER_COMAGC_TARMSB
- R367TER_COM_AGC_CFG
- R367TER_COM_AGC_GAIN1
- R367TER_COM_AGC_TAR_ENMODE
- R367TER_CONSTCARR1
- R367TER_CONSTCARR2
- R367TER_CONSTMODE
- R367TER_CONSTMU_LSB
- R367TER_CONSTMU_MAX_LSB
- R367TER_CONSTMU_MAX_MSB
- R367TER_CONSTMU_MSB
- R367TER_COR_CTL
- R367TER_COR_INTEN
- R367TER_COR_INTSTAT
- R367TER_COR_MODEGUARD
- R367TER_COR_STAT
- R367TER_CRL_CTL
- R367TER_CRL_FLAG
- R367TER_CRL_FREQ1
- R367TER_CRL_FREQ2
- R367TER_CRL_FREQ3
- R367TER_CRL_TARGET1
- R367TER_CRL_TARGET2
- R367TER_CRL_TARGET3
- R367TER_CRL_TARGET4
- R367TER_CTL_FFTOSNUM
- R367TER_DAC0R
- R367TER_DAC1R
- R367TER_DCOFFSET
- R367TER_DEBG_LT10
- R367TER_DEBG_LT11
- R367TER_DEBG_LT12
- R367TER_DEBG_LT13
- R367TER_DEBG_LT14
- R367TER_DEBG_LT15
- R367TER_DEBG_LT16
- R367TER_DEBG_LT17
- R367TER_DEBG_LT18
- R367TER_DEBG_LT19
- R367TER_DEBG_LT1A
- R367TER_DEBG_LT1B
- R367TER_DEBG_LT1C
- R367TER_DEBG_LT1D
- R367TER_DEBG_LT1E
- R367TER_DEBG_LT1F
- R367TER_DEBUG_LT1
- R367TER_DEBUG_LT2
- R367TER_DEBUG_LT3
- R367TER_DEBUG_LT4
- R367TER_DEBUG_LT5
- R367TER_DEBUG_LT6
- R367TER_DEBUG_LT7
- R367TER_DEBUG_LT8
- R367TER_DEBUG_LT9
- R367TER_DEC_NCO1
- R367TER_DEC_NCO2
- R367TER_DEC_NCO3
- R367TER_DEMAPVIT
- R367TER_DIG_AGC_R
- R367TER_DMP_CTL
- R367TER_DUAL_AD12
- R367TER_EN_PROCESS
- R367TER_EPQ
- R367TER_EPQAUTO
- R367TER_EPQ_ADJUST
- R367TER_EPQ_CFG
- R367TER_EPQ_STATUS
- R367TER_EPQ_THRES
- R367TER_EPQ_TPS_ID_CELL
- R367TER_ERRCNT1H
- R367TER_ERRCNT1L
- R367TER_ERRCNT1M
- R367TER_ERRCNT2H
- R367TER_ERRCNT2L
- R367TER_ERRCNT2M
- R367TER_ERRCTRL1
- R367TER_ERRCTRL2
- R367TER_ERROR_CRL1
- R367TER_ERROR_CRL2
- R367TER_ERROR_CRL3
- R367TER_ERROR_CRL4
- R367TER_FBERCPT0
- R367TER_FBERCPT1
- R367TER_FBERCPT2
- R367TER_FBERCPT3
- R367TER_FBERCPT4
- R367TER_FBERERR0
- R367TER_FBERERR1
- R367TER_FBERERR2
- R367TER_FECM
- R367TER_FECSPY
- R367TER_FEPATH_CFG
- R367TER_FE_LOOP_OPEN
- R367TER_FFEC1PRG
- R367TER_FFT_CTL
- R367TER_FGOODPACK
- R367TER_FILT_CHANNEL_EST
- R367TER_FPACKCNT
- R367TER_FREESTFE_1
- R367TER_FREESTFE_2
- R367TER_FREESYS1
- R367TER_FREESYS2
- R367TER_FREESYS3
- R367TER_FREQOFF1
- R367TER_FREQOFF2
- R367TER_FREQOFF3
- R367TER_FSPYBER
- R367TER_FSPYCFG
- R367TER_FSPYDATA
- R367TER_FSPYDISTL
- R367TER_FSPYDISTM
- R367TER_FSPYMISC
- R367TER_FSPYOBS0
- R367TER_FSPYOBS1
- R367TER_FSPYOBS2
- R367TER_FSPYOBS3
- R367TER_FSPYOBS4
- R367TER_FSPYOBS5
- R367TER_FSPYOBS6
- R367TER_FSPYOBS7
- R367TER_FSPYOUT
- R367TER_FSTATESL
- R367TER_FSTATESM
- R367TER_FSTATUS
- R367TER_FVERROR
- R367TER_FVITCURPUN
- R367TER_FVSTATUSVIT
- R367TER_GAIN_SRC1
- R367TER_GAIN_SRC2
- R367TER_GPIO_CFG
- R367TER_GPIO_CMD
- R367TER_GPLSB
- R367TER_GPMSB
- R367TER_GP_CTL
- R367TER_I2CRPT
- R367TER_ICONSTEL
- R367TER_ID
- R367TER_IIRCX_COEFF1_LSB
- R367TER_IIRCX_COEFF1_MSB
- R367TER_IIRCX_COEFF2_LSB
- R367TER_IIRCX_COEFF2_MSB
- R367TER_IIRCX_COEFF3_LSB
- R367TER_IIRCX_COEFF3_MSB
- R367TER_IIRCX_COEFF4_LSB
- R367TER_IIRCX_COEFF4_MSB
- R367TER_IIRCX_COEFF5_LSB
- R367TER_IIRCX_COEFF5_MSB
- R367TER_IIR_CELLNB
- R367TER_INCTHRES_COR1
- R367TER_INCTHRES_COR2
- R367TER_INCTHRES_DET1
- R367TER_INCTHRES_DET2
- R367TER_INC_CTL
- R367TER_INC_DEROT1
- R367TER_INC_DEROT2
- R367TER_INR_THRESHOLD
- R367TER_INT_X_0
- R367TER_INT_X_1
- R367TER_INT_X_2
- R367TER_INT_X_3
- R367TER_IOCFG0
- R367TER_IOCFG1
- R367TER_IOCFG2
- R367TER_KDIV12
- R367TER_KDIV23
- R367TER_KDIV34
- R367TER_KDIV56
- R367TER_KDIV67
- R367TER_KDIV78
- R367TER_LOCKN
- R367TER_LOCK_DET_MSB
- R367TER_MAXGP_LSB
- R367TER_MAXGP_MSB
- R367TER_MIN_ERRX_MSB
- R367TER_MSC_REV
- R367TER_MULSB
- R367TER_MUMSB
- R367TER_OMEGALSB
- R367TER_OMEGAMSB
- R367TER_OMEGA_CTL
- R367TER_OVF_RATE1
- R367TER_OVF_RATE2
- R367TER_PAD_COMP_CTRL
- R367TER_PAD_COMP_RD
- R367TER_PAD_COMP_WR
- R367TER_PILOTMU_ACCU
- R367TER_PILOT_ACCU
- R367TER_PIR_CTL
- R367TER_PLLMDIV
- R367TER_PLLNDIV
- R367TER_PLLSETUP
- R367TER_PMC1_FOR
- R367TER_PMC1_FUNC
- R367TER_PMC2_FUNC
- R367TER_PPM_CPAMP
- R367TER_PPM_CPAMP_DIR
- R367TER_PPM_CPAMP_INV
- R367TER_PPM_CTL1
- R367TER_PPM_OFFSET1
- R367TER_PPM_OFFSET2
- R367TER_PPM_STATE_MAC
- R367TER_PRVIT
- R367TER_QCONSTEL
- R367TER_RATIO_PILOT
- R367TER_RC1SPEED
- R367TER_RCCFGH
- R367TER_RCCFGL
- R367TER_RCCFGM
- R367TER_RCDEBUGL
- R367TER_RCDEBUGM
- R367TER_RCFBERCPT0
- R367TER_RCFBERCPT1
- R367TER_RCFBERCPT2
- R367TER_RCFBERCPT3
- R367TER_RCFBERCPT4
- R367TER_RCFBERERR0
- R367TER_RCFBERERR1
- R367TER_RCFBERERR2
- R367TER_RCFECSPY
- R367TER_RCFGOODPACK
- R367TER_RCFPACKCNT
- R367TER_RCFSPYBER
- R367TER_RCFSPYCFG
- R367TER_RCFSPYDATA
- R367TER_RCFSPYDISTL
- R367TER_RCFSPYDISTM
- R367TER_RCFSPYMISC
- R367TER_RCFSPYOBS0
- R367TER_RCFSPYOBS1
- R367TER_RCFSPYOBS2
- R367TER_RCFSPYOBS3
- R367TER_RCFSPYOBS4
- R367TER_RCFSPYOBS5
- R367TER_RCFSPYOBS6
- R367TER_RCFSPYOBS7
- R367TER_RCFSPYOUT
- R367TER_RCFSTATESL
- R367TER_RCFSTATESM
- R367TER_RCFSTATUS
- R367TER_RCINSDELH
- R367TER_RCINSDELL
- R367TER_RCINSDELM
- R367TER_RCOBSCFG
- R367TER_RCOBSL
- R367TER_RCOBSM
- R367TER_RCSPEED
- R367TER_RCSTATUS
- R367TER_RESERVED_1
- R367TER_RESERVED_2
- R367TER_RESERVED_3
- R367TER_RF_AGC1
- R367TER_RF_AGC2
- R367TER_SCAT_NB
- R367TER_SCR_CTL
- R367TER_SDFR
- R367TER_SDI_SMOOTHER
- R367TER_SELOUT
- R367TER_SFAVSR
- R367TER_SFDEMAP
- R367TER_SFDILSTKL
- R367TER_SFDILSTKM
- R367TER_SFDLYH
- R367TER_SFDLYL
- R367TER_SFDLYM
- R367TER_SFDLYSETH
- R367TER_SFDLYSETL
- R367TER_SFDLYSETM
- R367TER_SFECINFO
- R367TER_SFECSTATUS
- R367TER_SFERRCNTH
- R367TER_SFERRCNTL
- R367TER_SFERRCNTM
- R367TER_SFERRCTRL
- R367TER_SFERROR
- R367TER_SFKDIV12
- R367TER_SFKDIV23
- R367TER_SFKDIV34
- R367TER_SFKDIV56
- R367TER_SFKDIV67
- R367TER_SFKDIV78
- R367TER_SFOBSCFG
- R367TER_SFOBSL
- R367TER_SFOBSM
- R367TER_SFSTATUS
- R367TER_SIGPOWER
- R367TER_SNR
- R367TER_SNR_CARRIER1
- R367TER_SNR_CARRIER2
- R367TER_SPECTR_CFG
- R367TER_STATUS
- R367TER_STATUS_ERR_DA
- R367TER_SYMBCFG
- R367TER_SYMBFIFOL
- R367TER_SYMBFIFOM
- R367TER_SYMBOFFSL
- R367TER_SYMBOFFSM
- R367TER_SYMBRATEL
- R367TER_SYMBRATEM
- R367TER_SYMBSTATUS
- R367TER_SYR_CHCADJ1
- R367TER_SYR_CHCADJ2
- R367TER_SYR_CTL
- R367TER_SYR_FFTADJ1
- R367TER_SYR_FFTADJ2
- R367TER_SYR_FLAG
- R367TER_SYR_NCO1
- R367TER_SYR_NCO2
- R367TER_SYR_OFF
- R367TER_SYR_OFFSET1
- R367TER_SYR_OFFSET2
- R367TER_SYR_STAT
- R367TER_SYR_TARGET_CHCADJT_LSB
- R367TER_SYR_TARGET_CHCADJT_MSB
- R367TER_SYR_TARGET_FFTADJT_LSB
- R367TER_SYR_TARGET_FFTADJT_MSB
- R367TER_SYR_UPDATE
- R367TER_TESTSELECT
- R367TER_TIMOFF1
- R367TER_TIMOFF2
- R367TER_TOPCTRL
- R367TER_TOP_TRACK
- R367TER_TPS_CTL
- R367TER_TPS_ID_CELL1
- R367TER_TPS_ID_CELL2
- R367TER_TPS_RCVD1
- R367TER_TPS_RCVD2
- R367TER_TPS_RCVD3
- R367TER_TPS_RCVD4
- R367TER_TPS_RCVD5_SET1
- R367TER_TPS_SET2
- R367TER_TPS_SET3
- R367TER_TPS_SFRAME_CTL
- R367TER_TRACKER_FREE1
- R367TER_TRACKER_FREE2
- R367TER_TRL_CHC
- R367TER_TRL_CTL
- R367TER_TRL_NOMRATE1
- R367TER_TRL_NOMRATE2
- R367TER_TRL_TARGET1
- R367TER_TRL_TARGET2
- R367TER_TRL_TIME1
- R367TER_TRL_TIME2
- R367TER_TSBITRATEL
- R367TER_TSBITRATEM
- R367TER_TSBLOCLENL
- R367TER_TSBLOCLENM
- R367TER_TSBUFSTATH
- R367TER_TSBUFSTATL
- R367TER_TSBUFSTATM
- R367TER_TSCFGH
- R367TER_TSCFGL
- R367TER_TSCFGM
- R367TER_TSDEBUGL
- R367TER_TSDEBUGM
- R367TER_TSDILSTKL
- R367TER_TSDILSTKM
- R367TER_TSDIVN
- R367TER_TSDIVPL
- R367TER_TSDIVPM
- R367TER_TSDIVQL
- R367TER_TSDIVQM
- R367TER_TSDLYH
- R367TER_TSDLYL
- R367TER_TSDLYM
- R367TER_TSDLYSETH
- R367TER_TSDLYSETL
- R367TER_TSDLYSETM
- R367TER_TSFSYNC
- R367TER_TSGENERAL
- R367TER_TSGSTATUS
- R367TER_TSINSDELH
- R367TER_TSINSDELL
- R367TER_TSINSDELM
- R367TER_TSM_AP0
- R367TER_TSM_AP1
- R367TER_TSM_AP2
- R367TER_TSM_AP3
- R367TER_TSM_AP4
- R367TER_TSM_AP5
- R367TER_TSM_AP6
- R367TER_TSM_AP7
- R367TER_TSNPDAV
- R367TER_TSOBSCFG
- R367TER_TSOBSL
- R367TER_TSOBSM
- R367TER_TSPACKLENL
- R367TER_TSPACKLENM
- R367TER_TSSPEED
- R367TER_TSSTATEL
- R367TER_TSSTATEM
- R367TER_TSSTATUS
- R367TER_TSSTATUS2
- R367TER_TSSYNC
- R367TER_TSTBIST
- R367TER_TSTBISTRES0
- R367TER_TSTBISTRES1
- R367TER_TSTBISTRES2
- R367TER_TSTBISTRES3
- R367TER_TSTBUS
- R367TER_TSTERR
- R367TER_TSTRATE
- R367TER_TSTRES
- R367TER_TSTSFERR
- R367TER_TSTSFMET
- R367TER_TSTTS1
- R367TER_TSTTS2
- R367TER_TSTTS3
- R367TER_TSTTS4
- R367TER_TSTTSRC
- R367TER_TSTTSRS
- R367TER_TSTTSSF1
- R367TER_TSTTSSF2
- R367TER_TSTTSSF3
- R367TER_TSYNC
- R367TER_VAVSRVIT
- R367TER_VERROR
- R367TER_VITCURPUN
- R367TER_VITSCALE
- R367TER_VSTATUSVIT
- R367TER_VTH12
- R367TER_VTH23
- R367TER_VTH34
- R367TER_VTH56
- R367TER_VTH67
- R367TER_VTH78
- R367TER_VTHINUSE
- R36_PID
- R36_RFCALRAM1
- R36_SD2
- R37_PIDH
- R37_RFCALRAM2
- R37_SD3
- R38_MARGIN
- R38_SD4
- R3964_BCC
- R3964_BREAK
- R3964_CHECKSUM
- R3964_DEBUG
- R3964_ENABLE_SIGNALS
- R3964_ERROR
- R3964_FRAME
- R3964_IDLE
- R3964_MASTER
- R3964_MAX_BLOCKS_IN_RX_QUEUE
- R3964_MAX_MSG_COUNT
- R3964_MAX_RETRIES
- R3964_MSG_ACK
- R3964_MSG_DATA
- R3964_MTU
- R3964_NO_TX_ROOM
- R3964_OK
- R3964_OVERFLOW
- R3964_OVERRUN
- R3964_PARITY
- R3964_READ_TELEGRAM
- R3964_RECEIVING
- R3964_SETPRIORITY
- R3964_SIG_ACK
- R3964_SIG_ALL
- R3964_SIG_DATA
- R3964_SIG_NONE
- R3964_SLAVE
- R3964_TO_NO_BUF
- R3964_TO_QVZ
- R3964_TO_RX_PANIC
- R3964_TO_ZVZ
- R3964_TRANSMITTING
- R3964_TX_FAIL
- R3964_TX_REQUEST
- R3964_UNKNOWN
- R3964_USE_BCC
- R3964_USE_SIGIO
- R3964_WAIT_FOR_BCC
- R3964_WAIT_FOR_RX_BUF
- R3964_WAIT_FOR_RX_REPEAT
- R3964_WAIT_FOR_TX_ACK
- R3964_WAIT_ZVZ_BEFORE_TX_RETRY
- R39_FMAX1
- R39_SD5
- R39_Test1
- R3A_FMAX2
- R3A_SD_TEST
- R3B
- R3B_REGU
- R3B_Test3
- R3C_RCCAL1
- R3D
- R3DI_DSP_DOWNLOADED
- R3DI_DSP_DOWNLOADING
- R3DI_EFX_FILE
- R3DI_FRONT_MIC
- R3DI_GPIO_DSP_DOWNLOADED
- R3DI_GPIO_DSP_DOWNLOADING
- R3DI_HEADPHONE_OUT
- R3DI_LINE_OUT
- R3DI_MIC_SELECT_BIT
- R3DI_OUT_SELECT_BIT
- R3DI_REAR_MIC
- R3D_RCCAL2
- R3E_IRCAL1
- R3F_IRCAL2
- R3H
- R3K_ENTRYLO_D
- R3K_ENTRYLO_G
- R3K_ENTRYLO_N
- R3K_ENTRYLO_V
- R3_OFF
- R3_TO_LWREG
- R3_TO_LWREG_V
- R3_TO_LWREG_VM
- R3_TO_LWREG_VM_V
- R4
- R4000_WAR
- R400_GB_PIPE_SELECT
- R4030_ADDR_INTR
- R4030_CHNL_ENABLE
- R4030_CHNL_WRITE
- R4030_MEM_INTR
- R4030_MODE_ATIME_120
- R4030_MODE_ATIME_160
- R4030_MODE_ATIME_200
- R4030_MODE_ATIME_240
- R4030_MODE_ATIME_280
- R4030_MODE_ATIME_320
- R4030_MODE_ATIME_40
- R4030_MODE_ATIME_80
- R4030_MODE_BURST
- R4030_MODE_FAST_ACK
- R4030_MODE_INTR_EN
- R4030_MODE_WIDTH_16
- R4030_MODE_WIDTH_32
- R4030_MODE_WIDTH_8
- R4030_TC_INTR
- R40_IRCAL3
- R41_IRCAL4
- R420D_H
- R420_TV_DAC_BDACPD
- R420_TV_DAC_DACADJ_MASK
- R420_TV_DAC_GDACPD
- R420_TV_DAC_RDACPD
- R420_TV_DAC_TVENABLE
- R42_IRCAL5
- R43_PD1
- R4400_WAR
- R444_ENABLE
- R444_RGBX
- R44_PD2
- R45_PD
- R4600_HIT_CACHEOP_WAR_IMPL
- R4600_V1_HIT_CACHEOP_WAR
- R4600_V1_INDEX_ICACHEOP_WAR
- R4600_V2_HIT_CACHEOP_WAR
- R46_CPUMP
- R47_LNAPOL
- R48_SMOOTH1
- R49_SMOOTH2
- R4A_SMOOTH3
- R4B_XTALOSC1
- R4C_XTALOSC2
- R4D_XTALFLX1
- R4E_XTALFLX2
- R4F_XTALFLX3
- R4K_CONF_SB
- R4K_CONF_SS
- R4K_CONF_SW
- R4K_HIT
- R4K_INDEX
- R4K_OPTS
- R4_18V_PRESENT
- R4_DRD
- R4_DWR
- R4_EVICT
- R4_EXTEND_CFG
- R4_GEN
- R4_IRD
- R4_MEMORY_PRESENT
- R4_MSG
- R4_OFF
- R4_PREF
- R4_RD
- R4_SNOOP
- R4_WR
- R5
- R500FP_CONSTANT_CLAMP
- R500FP_CONSTANT_TYPE
- R500_BMASK_DISABLE
- R500_BMASK_ENABLE
- R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE
- R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE
- R500_COVERED_PTR_MASKING_DISABLE
- R500_COVERED_PTR_MASKING_ENABLE
- R500_DYN_SCLK_PWMEM_PIPE
- R500_GA_US_VECTOR_DATA
- R500_GA_US_VECTOR_INDEX
- R500_HIZ_EQUAL_REJECT_DISABLE
- R500_HIZ_EQUAL_REJECT_ENABLE
- R500_HIZ_FP_EXP_BITS_1
- R500_HIZ_FP_EXP_BITS_2
- R500_HIZ_FP_EXP_BITS_3
- R500_HIZ_FP_EXP_BITS_4
- R500_HIZ_FP_EXP_BITS_5
- R500_HIZ_FP_EXP_BITS_DISABLE
- R500_HIZ_FP_INVERT_LEADING_ONES
- R500_HIZ_FP_INVERT_LEADING_ZEROS
- R500_LVTMA_CLOCK_ENABLE
- R500_LVTMA_PWRSEQ_CNTL
- R500_LVTMA_PWRSEQ_STATE
- R500_LVTMA_TRANSMITTER_CONTROL
- R500_LVTMA_TRANSMITTER_ENABLE
- R500_OP_FIFO_SIZE_EIGTHS
- R500_OP_FIFO_SIZE_FULL
- R500_OP_FIFO_SIZE_HALF
- R500_OP_FIFO_SIZE_QUATER
- R500_PEQ_PACKING_DISABLE
- R500_PEQ_PACKING_ENABLE
- R500_RB3D_COLOR_CLEAR_VALUE_AR
- R500_RB3D_CONSTANT_COLOR_AR
- R500_RS_INST_0
- R500_RS_IP_0
- R500_SEQUAL_OPTIMIZE_DISABLE
- R500_SEQUAL_OPTIMIZE_ENABLE
- R500_STENCILMASK_MASK
- R500_STENCILMASK_SHIFT
- R500_STENCILREF_MASK
- R500_STENCILREF_SHIFT
- R500_STENCILWRITEMASK_MASK
- R500_STENCILWRITEMASK_SHIFT
- R500_SU_REG_DEST
- R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE
- R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE
- R500_US_CODE_ADDR
- R500_US_CONFIG
- R500_US_FC_CTRL
- R500_VAP_INDEX_OFFSET
- R500_ZB_FIFO_SIZE
- R500_ZB_STENCILREFMASK_BF
- R500_ZEQUAL_OPTIMIZE_DISABLE
- R500_ZEQUAL_OPTIMIZE_ENABLE
- R50_XTALFLX4
- R511_CAM_DELAY
- R511_CAM_EDGE
- R511_CAM_LINE_MODE
- R511_CAM_LNCNT
- R511_CAM_LNDIV
- R511_CAM_OPTS
- R511_CAM_PXCNT
- R511_CAM_PXDIV
- R511_CAM_UV_EN
- R511_COMP_EN
- R511_COMP_LUT_EN
- R511_DRAM_FLOW_CTL
- R511_FIFO_OPTS
- R511_I2C_CTL
- R511_SNAP_FRAME
- R511_SNAP_LNCNT
- R511_SNAP_LNDIV
- R511_SNAP_OPTS
- R511_SNAP_PXCNT
- R511_SNAP_PXDIV
- R511_SNAP_UV_EN
- R511_SYS_LED_CTL
- R518_GPIO_CTL
- R518_GPIO_OUT
- R518_I2C_CTL
- R51_XTALFLX5
- R51x_COMP_LUT_BEGIN
- R51x_FIFO_PSIZE
- R51x_I2C_DATA
- R51x_I2C_R_SID
- R51x_I2C_SADDR_2
- R51x_I2C_SADDR_3
- R51x_I2C_W_SID
- R51x_SYS_CUST_ID
- R51x_SYS_INIT
- R51x_SYS_RESET
- R51x_SYS_SNAP
- R520_MC_AGP_BASE
- R520_MC_AGP_BASE_2
- R520_MC_AGP_LOCATION
- R520_MC_AGP_START_MASK
- R520_MC_AGP_START_SHIFT
- R520_MC_AGP_TOP_MASK
- R520_MC_AGP_TOP_SHIFT
- R520_MC_CHANNEL_SIZE
- R520_MC_CNTL0
- R520_MC_FB_LOCATION
- R520_MC_FB_START_MASK
- R520_MC_FB_START_SHIFT
- R520_MC_FB_TOP_MASK
- R520_MC_FB_TOP_SHIFT
- R520_MC_IND_DATA
- R520_MC_IND_INDEX
- R520_MC_IND_WR_EN
- R520_MC_STATUS
- R520_MC_STATUS_IDLE
- R520_MEM_NUM_CHANNELS_MASK
- R520_MEM_NUM_CHANNELS_SHIFT
- R52_IRLOOP0
- R53_IRLOOP1
- R54_IRLOOP2
- R55_IRLOOP3
- R56_IRLOOP4
- R57_PLL_LOG
- R58_AGC2_UP1
- R592_FIFO_DMA
- R592_FIFO_DMA_SETTINGS
- R592_FIFO_DMA_SETTINGS_CAP
- R592_FIFO_DMA_SETTINGS_DIR
- R592_FIFO_DMA_SETTINGS_EN
- R592_FIFO_PIO
- R592_IO
- R592_IO_16
- R592_IO_18
- R592_IO_22
- R592_IO_26
- R592_IO_DIRECTION
- R592_IO_MODE
- R592_IO_MODE_PARALLEL
- R592_IO_MODE_SERIAL
- R592_IO_RESET
- R592_IO_SERIAL1
- R592_IO_SERIAL2
- R592_LFIFO_SIZE
- R592_POWER
- R592_POWER_0
- R592_POWER_1
- R592_POWER_20
- R592_POWER_3
- R592_REG38
- R592_REG38_CHANGE
- R592_REG38_DONE
- R592_REG38_SHIFT
- R592_REG_3C
- R592_REG_MSC
- R592_REG_MSC_FIFO_DMA_DONE
- R592_REG_MSC_FIFO_DMA_ERR
- R592_REG_MSC_FIFO_EMPTY
- R592_REG_MSC_FIFO_MISMATH
- R592_REG_MSC_FIFO_USER_ORN
- R592_REG_MSC_IRQ_INSERT
- R592_REG_MSC_IRQ_REMOVE
- R592_REG_MSC_LED
- R592_REG_MSC_PRSNT
- R592_SFIFO
- R592_SFIFO_PACKET
- R592_SFIFO_SIZE
- R592_STATUS
- R592_STATUS_CED
- R592_STATUS_P_BREQ
- R592_STATUS_P_CED
- R592_STATUS_P_CMDNACK
- R592_STATUS_P_INTERR
- R592_STATUS_RDY
- R592_STATUS_RECV_ERR
- R592_STATUS_SEND_ERR
- R592_STATUS_SFIFO_EMPTY
- R592_STATUS_SFIFO_FULL
- R592_STATUS_SFIFO_INPUT
- R592_TPC_EXEC
- R592_TPC_EXEC_BIG_FIFO
- R592_TPC_EXEC_LEN_SHIFT
- R592_TPC_EXEC_TPC_SHIFT
- R59_AGC2_UP2
- R5A_H3H5
- R5B_AGC_AUTO
- R5C_AGC_DEBUG
- R5C_EXTRA_PAGE_IN_USE
- R5C_FULL_STRIPE_FLUSH_BATCH
- R5C_JOURNAL_MODE_WRITE_BACK
- R5C_JOURNAL_MODE_WRITE_THROUGH
- R5C_LOG_CRITICAL
- R5C_LOG_TIGHT
- R5C_RADIX_COUNT_SHIFT
- R5C_RECLAIM_STRIPE_GROUP
- R5C_RECLAIM_WAKEUP_INTERVAL
- R5F_ESR0_SHIFT
- R5F_ESR1_SHIFT
- R5F_ESR2_SHIFT
- R5F_ESR3_SHIFT
- R5F_ESR4_SHIFT
- R5K_CONF_SE
- R5K_CONF_SS
- R5K_Page_Invalidate_S
- R5LOG_MAGIC
- R5LOG_PAYLOAD_DATA
- R5LOG_PAYLOAD_FLAG_DISCARD
- R5LOG_PAYLOAD_FLAG_FLUSH_STRIPE
- R5LOG_PAYLOAD_FLAG_RESHAPED
- R5LOG_PAYLOAD_FLAG_RESHAPING
- R5LOG_PAYLOAD_FLUSH
- R5LOG_PAYLOAD_PARITY
- R5LOG_VERSION
- R5L_POOL_SIZE
- R5L_RECOVERY_PAGE_POOL_SIZE
- R5_ALLOC_MORE
- R5_COM_CRC_ERROR
- R5_DESC
- R5_DID_ALLOC
- R5_DOUBLE_LOCKED
- R5_Discard
- R5_ERROR
- R5_Expanded
- R5_FUNCTION_NUMBER
- R5_HASH
- R5_ILLEGAL_COMMAND
- R5_INACTIVE_BLOCKED
- R5_IO_CURRENT_STATE
- R5_InJournal
- R5_Insync
- R5_LOCKED
- R5_MadeGood
- R5_MadeGoodRepl
- R5_NeedReplace
- R5_OFF
- R5_OUT_OF_RANGE
- R5_OVERWRITE
- R5_OrigPageUPTDODATE
- R5_Overlap
- R5_ReWrite
- R5_ReadError
- R5_ReadNoMerge
- R5_ReadRepl
- R5_STATUS
- R5_SkipCopy
- R5_SyncIO
- R5_UPTODATE
- R5_WantFUA
- R5_WantReplace
- R5_Wantcompute
- R5_Wantdrain
- R5_Wantfill
- R5_Wantread
- R5_Wantwrite
- R5_WriteError
- R6
- R600D_H
- R600_AH_DFLT
- R600_ASI_DFLT
- R600_AUDIO_CLK_SRCSEL
- R600_AUDIO_CONFIG_DEFAULT
- R600_AUDIO_CONN_LIST
- R600_AUDIO_CONN_LIST_LEN
- R600_AUDIO_ENABLE
- R600_AUDIO_IMPLEMENTATION_ID
- R600_AUDIO_NID1_NODE_COUNT
- R600_AUDIO_NID1_TYPE
- R600_AUDIO_NID2_CAPS
- R600_AUDIO_NID3_CAPS
- R600_AUDIO_NID3_PIN_CAPS
- R600_AUDIO_PIN_SENSE
- R600_AUDIO_PIN_WIDGET_CNTL
- R600_AUDIO_PLAYING
- R600_AUDIO_PLL1_DIV
- R600_AUDIO_PLL1_MUL
- R600_AUDIO_PLL2_DIV
- R600_AUDIO_PLL2_MUL
- R600_AUDIO_RATE_BPS_CHANNEL
- R600_AUDIO_REVISION_ID
- R600_AUDIO_ROOT_NODE_COUNT
- R600_AUDIO_STATUS_BITS
- R600_AUDIO_SUPPORTED_CODEC
- R600_AUDIO_SUPPORTED_POWER_STATES
- R600_AUDIO_SUPPORTED_SIZE_RATE
- R600_AUDIO_TIMING
- R600_AUDIO_VENDOR_ID
- R600_BACKBIASRESPONSETIME_DFLT
- R600_BIF_FB_EN
- R600_BIOS_0_SCRATCH
- R600_BIOS_1_SCRATCH
- R600_BIOS_2_SCRATCH
- R600_BIOS_3_SCRATCH
- R600_BIOS_4_SCRATCH
- R600_BIOS_5_SCRATCH
- R600_BIOS_6_SCRATCH
- R600_BIOS_7_SCRATCH
- R600_BIOS_ROM_DIS
- R600_BLACKOUT_MASK
- R600_BLIT_SHADERS_H
- R600_BSP_DFLT
- R600_BSU_DFLT
- R600_BUS_CNTL
- R600_CG_SPLL_FUNC_CNTL
- R600_CG_SPLL_STATUS
- R600_CHANSIZE
- R600_CHANSIZE_OVERRIDE
- R600_CITF_CNTL
- R600_CONFIG_APER_SIZE
- R600_CONFIG_CNTL
- R600_CONFIG_F0_BASE
- R600_CONFIG_MEMSIZE
- R600_CP_PACKET0_GET_REG
- R600_CP_PACKET0_REG_MASK
- R600_CP_RB_BASE
- R600_CP_RB_CNTL
- R600_CP_RB_RPTR
- R600_CP_RB_RPTR_ADDR
- R600_CP_RB_RPTR_ADDR_HI
- R600_CP_RB_RPTR_WR
- R600_CP_RB_WPTR
- R600_CP_RB_WPTR_ADDR
- R600_CP_RB_WPTR_ADDR_HI
- R600_CP_RB_WPTR_DELAY
- R600_CTXCGTT3DRPHC_DFLT
- R600_CTXCGTT3DRSDC_DFLT
- R600_CTXSW_VID_LOWER_GPIO_CNTL
- R600_D1GRPH_ALPHA_CROSSBAR
- R600_D1GRPH_ALPHA_SEL_A
- R600_D1GRPH_ALPHA_SEL_B
- R600_D1GRPH_ALPHA_SEL_G
- R600_D1GRPH_ALPHA_SEL_R
- R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1
- R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1
- R600_D1GRPH_ARRAY_MODE_LINEAR_ALIGNED
- R600_D1GRPH_ARRAY_MODE_LINEAR_GENERAL
- R600_D1GRPH_BLUE_CROSSBAR
- R600_D1GRPH_BLUE_SEL_A
- R600_D1GRPH_BLUE_SEL_B
- R600_D1GRPH_BLUE_SEL_G
- R600_D1GRPH_BLUE_SEL_R
- R600_D1GRPH_ENDIAN_SWAP
- R600_D1GRPH_GREEN_CROSSBAR
- R600_D1GRPH_GREEN_SEL_A
- R600_D1GRPH_GREEN_SEL_B
- R600_D1GRPH_GREEN_SEL_G
- R600_D1GRPH_GREEN_SEL_R
- R600_D1GRPH_RED_CROSSBAR
- R600_D1GRPH_RED_SEL_A
- R600_D1GRPH_RED_SEL_B
- R600_D1GRPH_RED_SEL_G
- R600_D1GRPH_RED_SEL_R
- R600_D1GRPH_SWAP_CONTROL
- R600_D1GRPH_SWAP_ENDIAN_16BIT
- R600_D1GRPH_SWAP_ENDIAN_32BIT
- R600_D1GRPH_SWAP_ENDIAN_64BIT
- R600_D1GRPH_SWAP_ENDIAN_NONE
- R600_DISPLAY_WATERMARK_HIGH
- R600_DISPLAY_WATERMARK_LOW
- R600_DTC_DFLT_00
- R600_DTC_DFLT_01
- R600_DTC_DFLT_02
- R600_DTC_DFLT_03
- R600_DTC_DFLT_04
- R600_DTC_DFLT_05
- R600_DTC_DFLT_06
- R600_DTC_DFLT_07
- R600_DTC_DFLT_08
- R600_DTC_DFLT_09
- R600_DTC_DFLT_10
- R600_DTC_DFLT_11
- R600_DTC_DFLT_12
- R600_DTC_DFLT_13
- R600_DTC_DFLT_14
- R600_ENDINGVCOSTEPPCT_DFLT
- R600_FB_READ_EN
- R600_FB_WRITE_EN
- R600_FCTU_DFLT
- R600_FCT_DFLT
- R600_GENERAL_PWRMGT
- R600_GICST_DFLT
- R600_HDP_NONSURFACE_BASE
- R600_HIGH_VID_LOWER_GPIO_CNTL
- R600_LHP_DFLT
- R600_LMP_DFLT
- R600_LOGICAL_PAGE_NUMBER_MASK
- R600_LOGICAL_PAGE_NUMBER_SHIFT
- R600_LOWER_GPIO_ENABLE
- R600_LOW_VID_LOWER_GPIO_CNTL
- R600_LVTMA_CLOCK_ENABLE
- R600_LVTMA_PWRSEQ_CNTL
- R600_LVTMA_PWRSEQ_STATE
- R600_LVTMA_TRANSMITTER_CONTROL
- R600_LVTMA_TRANSMITTER_ENABLE
- R600_MC_AGP_BOT_MASK
- R600_MC_AGP_BOT_SHIFT
- R600_MC_AGP_TOP_MASK
- R600_MC_AGP_TOP_SHIFT
- R600_MC_FB_BASE_MASK
- R600_MC_FB_BASE_SHIFT
- R600_MC_FB_TOP_MASK
- R600_MC_FB_TOP_SHIFT
- R600_MC_VM_AGP_BASE
- R600_MC_VM_AGP_BOT
- R600_MC_VM_AGP_TOP
- R600_MC_VM_FB_LOCATION
- R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
- R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR
- R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR
- R600_MEDIUM_VID_LOWER_GPIO_CNTL
- R600_MPLLLOCKTIME_DFLT
- R600_MPLLRESETTIME_DFLT
- R600_OPEN_DRAIN_PADS
- R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE
- R600_PCIE_LC_RENEGOTIATE_EN
- R600_PCIE_LC_RENEGOTIATION_SUPPORT
- R600_PCIE_LC_SHORT_RECONFIG_EN
- R600_PCIE_LC_UPCONFIGURE_DIS
- R600_PCIE_LC_UPCONFIGURE_SUPPORT
- R600_PCIE_PORT_DATA
- R600_PCIE_PORT_INDEX
- R600_PFP_UCODE_SIZE
- R600_PM4_UCODE_SIZE
- R600_PM_DISPLAY_GAP_IGNORE
- R600_PM_DISPLAY_GAP_VBLANK
- R600_PM_DISPLAY_GAP_VBLANK_OR_WM
- R600_PM_DISPLAY_GAP_WATERMARK
- R600_PM_NUMBER_OF_ACTIVITY_LEVELS
- R600_PM_NUMBER_OF_MCLKS
- R600_PM_NUMBER_OF_SCLKS
- R600_PM_NUMBER_OF_TC
- R600_PM_NUMBER_OF_VOLTAGE_LEVELS
- R600_POWER_LEVEL_CTXSW
- R600_POWER_LEVEL_HIGH
- R600_POWER_LEVEL_LOW
- R600_POWER_LEVEL_MEDIUM
- R600_PTE_FRAG_256KB
- R600_PTE_FRAG_4KB
- R600_PTE_FRAG_64KB
- R600_PTE_GART_MASK
- R600_PTE_READABLE
- R600_PTE_SNOOPED
- R600_PTE_SYSTEM
- R600_PTE_VALID
- R600_PTE_WRITEABLE
- R600_RAMCFG
- R600_RB_BLKSZ
- R600_RB_BUFSZ
- R600_RB_NO_UPDATE
- R600_RB_RPTR_WR_ENA
- R600_RCU_DATA
- R600_RCU_INDEX
- R600_REFERENCEDIVIDER_DFLT
- R600_RING_TYPE_DMA_INDEX
- R600_RING_TYPE_UVD_INDEX
- R600_RLC_UCODE_SIZE
- R600_RLP_DFLT
- R600_RMP_DFLT
- R600_ROM_CNTL
- R600_SCK_OVERWRITE
- R600_SCK_PRESCALE_CRYSTAL_CLK_MASK
- R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT
- R600_SCRATCH_REG_OFFSET
- R600_SPLLSTEPTIME_DFLT
- R600_SPLLSTEPUNIT_DFLT
- R600_SPLL_BYPASS_EN
- R600_SPLL_CHG_STATUS
- R600_SSTU_DFLT
- R600_SST_DFLT
- R600_TARGET_AND_CURRENT_PROFILE_INDEX
- R600_TD_AUTO
- R600_TD_DFLT
- R600_TD_DOWN
- R600_TD_UP
- R600_TEMP_RANGE_MAX
- R600_TEMP_RANGE_MIN
- R600_TPC_DFLT
- R600_TPU_DFLT
- R600_UTC_DFLT_00
- R600_UTC_DFLT_01
- R600_UTC_DFLT_02
- R600_UTC_DFLT_03
- R600_UTC_DFLT_04
- R600_UTC_DFLT_05
- R600_UTC_DFLT_06
- R600_UTC_DFLT_07
- R600_UTC_DFLT_08
- R600_UTC_DFLT_09
- R600_UTC_DFLT_10
- R600_UTC_DFLT_11
- R600_UTC_DFLT_12
- R600_UTC_DFLT_13
- R600_UTC_DFLT_14
- R600_UVD_CTX_DATA
- R600_UVD_CTX_INDEX
- R600_VCOSTEPPCT_DFLT
- R600_VDDC3DOORPHC_DFLT
- R600_VDDC3DOORSDC_DFLT
- R600_VDDC3DOORSU_DFLT
- R600_VOLTAGERESPONSETIME_DFLT
- R600_VRC_DFLT
- R600_VRU_DFLT
- R600_WB_DMA_RING_TEST_OFFSET
- R600_WB_DMA_RPTR_OFFSET
- R600_WB_EVENT_OFFSET
- R600_WB_IH_WPTR_OFFSET
- R601_SEL
- R6040_IO_SIZE
- R64CNT
- R6XX_MAX_BACKENDS
- R6XX_MAX_BACKENDS_MASK
- R6XX_MAX_PIPES
- R6XX_MAX_PIPES_MASK
- R6XX_MAX_SH_GPRS
- R6XX_MAX_SH_STACK_ENTRIES
- R6XX_MAX_SH_THREADS
- R6XX_MAX_SIMDS
- R6XX_MAX_SIMDS_MASK
- R6XX_MAX_TEMP_GPRS
- R6_OFF
- R7
- R700_D1CUR_SURFACE_ADDRESS_HIGH
- R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
- R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
- R700_D2CUR_SURFACE_ADDRESS_HIGH
- R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH
- R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH
- R700_LOGICAL_PAGE_NUMBER_MASK
- R700_LOGICAL_PAGE_NUMBER_SHIFT
- R700_MC_AGP_BOT_MASK
- R700_MC_AGP_BOT_SHIFT
- R700_MC_AGP_TOP_MASK
- R700_MC_AGP_TOP_SHIFT
- R700_MC_CITF_CNTL
- R700_MC_FB_BASE_MASK
- R700_MC_FB_BASE_SHIFT
- R700_MC_FB_TOP_MASK
- R700_MC_FB_TOP_SHIFT
- R700_MC_VM_AGP_BASE
- R700_MC_VM_AGP_BOT
- R700_MC_VM_AGP_TOP
- R700_MC_VM_FB_LOCATION
- R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR
- R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR
- R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR
- R700_PFP_UCODE_SIZE
- R700_PM4_UCODE_SIZE
- R700_RLC_UCODE_SIZE
- R700_TARGET_AND_CURRENT_PROFILE_INDEX
- R76_BLKPCOR
- R76_WHTPCOR
- R7P
- R7S72100_CLK_ADC
- R7S72100_CLK_ADCPWR
- R7S72100_CLK_CAN
- R7S72100_CLK_CDROM
- R7S72100_CLK_CEU
- R7S72100_CLK_CORESIGHT
- R7S72100_CLK_DOC0
- R7S72100_CLK_DOC1
- R7S72100_CLK_DRC0
- R7S72100_CLK_DRC1
- R7S72100_CLK_ETHAVB
- R7S72100_CLK_ETHER
- R7S72100_CLK_G
- R7S72100_CLK_I
- R7S72100_CLK_I2C0
- R7S72100_CLK_I2C1
- R7S72100_CLK_I2C2
- R7S72100_CLK_I2C3
- R7S72100_CLK_IEBUS
- R7S72100_CLK_IMR0
- R7S72100_CLK_IMR1
- R7S72100_CLK_IMRDISP
- R7S72100_CLK_IRDA
- R7S72100_CLK_JCU
- R7S72100_CLK_LIN0
- R7S72100_CLK_LIN1
- R7S72100_CLK_MLB
- R7S72100_CLK_MMCIF
- R7S72100_CLK_MTU2
- R7S72100_CLK_NAND
- R7S72100_CLK_OSTM0
- R7S72100_CLK_OSTM1
- R7S72100_CLK_PIX0
- R7S72100_CLK_PIX1
- R7S72100_CLK_PLL
- R7S72100_CLK_PWM
- R7S72100_CLK_RGPVG2
- R7S72100_CLK_RTC
- R7S72100_CLK_SCI0
- R7S72100_CLK_SCI1
- R7S72100_CLK_SCIF0
- R7S72100_CLK_SCIF1
- R7S72100_CLK_SCIF2
- R7S72100_CLK_SCIF3
- R7S72100_CLK_SCIF4
- R7S72100_CLK_SCIF5
- R7S72100_CLK_SCIF6
- R7S72100_CLK_SCIF7
- R7S72100_CLK_SCUX
- R7S72100_CLK_SDHI00
- R7S72100_CLK_SDHI01
- R7S72100_CLK_SDHI10
- R7S72100_CLK_SDHI11
- R7S72100_CLK_SG0
- R7S72100_CLK_SG1
- R7S72100_CLK_SG2
- R7S72100_CLK_SG3
- R7S72100_CLK_SPDIF
- R7S72100_CLK_SPI0
- R7S72100_CLK_SPI1
- R7S72100_CLK_SPI2
- R7S72100_CLK_SPI3
- R7S72100_CLK_SPI4
- R7S72100_CLK_SPIBSC0
- R7S72100_CLK_SPIBSC1
- R7S72100_CLK_SSI0
- R7S72100_CLK_SSI1
- R7S72100_CLK_SSI2
- R7S72100_CLK_SSI3
- R7S72100_CLK_SSI4
- R7S72100_CLK_SSI5
- R7S72100_CLK_USB0
- R7S72100_CLK_USB1
- R7S72100_CLK_VDC50
- R7S72100_CLK_VDC51
- R7S72100_CLK_VDEC0
- R7S72100_CLK_VDEC1
- R7S9210_CLK_B
- R7S9210_CLK_G
- R7S9210_CLK_I
- R7S9210_CLK_P0
- R7S9210_CLK_P1
- R7S9210_CLK_P1C
- R7XX_MAX_BACKENDS
- R7XX_MAX_BACKENDS_MASK
- R7XX_MAX_PIPES
- R7XX_MAX_PIPES_MASK
- R7XX_MAX_SH_GPRS
- R7XX_MAX_SH_STACK_ENTRIES
- R7XX_MAX_SH_THREADS
- R7XX_MAX_SIMDS
- R7XX_MAX_SIMDS_MASK
- R7XX_MAX_TEMP_GPRS
- R7_OFF
- R7p
- R8
- R8152_PHY_ID
- R8168DP_1_MDIO_ACCESS_BIT
- R8169_MSG_DEFAULT
- R8169_REGS_SIZE
- R8169_RX_BUF_SIZE
- R8169_RX_RING_BYTES
- R8169_TX_RING_BYTES
- R8180_HW
- R8180_MAX_RETRY
- R8180_WX_H
- R8190P_DEF_H
- R8192E_PM_H
- R8192U_H
- R8192_HW
- R8192_MAX_RETRY
- R819XUSB_CMDPKT_H
- R819x_WX_H
- R820T_H
- R82600_BRIDGE_ID
- R82600_DRAMC
- R82600_DRBA
- R82600_EAP
- R82600_NR_CHANS
- R82600_NR_CSROWS
- R82600_NR_DIMMS
- R82600_SDRAMC
- R83_AD_IDH
- R852_CARD_IRQ_CD
- R852_CARD_IRQ_ENABLE
- R852_CARD_IRQ_GENABLE
- R852_CARD_IRQ_INSERT
- R852_CARD_IRQ_MASK
- R852_CARD_IRQ_REMOVE
- R852_CARD_IRQ_STA
- R852_CARD_IRQ_UNK1
- R852_CARD_STA
- R852_CARD_STA_ABSENT
- R852_CARD_STA_BUSY
- R852_CARD_STA_CD
- R852_CARD_STA_PRESENT
- R852_CARD_STA_RO
- R852_CTL
- R852_CTL_CARDENABLE
- R852_CTL_COMMAND
- R852_CTL_DATA
- R852_CTL_ECC_ACCESS
- R852_CTL_ECC_ENABLE
- R852_CTL_ON
- R852_CTL_RESET
- R852_CTL_WRITE
- R852_DATALINE
- R852_DMA1
- R852_DMA2
- R852_DMA_ADDR
- R852_DMA_CAP
- R852_DMA_INTERNAL
- R852_DMA_IRQ_ENABLE
- R852_DMA_IRQ_ERROR
- R852_DMA_IRQ_INTERNAL
- R852_DMA_IRQ_MASK
- R852_DMA_IRQ_MEMORY
- R852_DMA_IRQ_STA
- R852_DMA_LEN
- R852_DMA_MEMORY
- R852_DMA_READ
- R852_DMA_SETTINGS
- R852_ECC_CORRECT
- R852_ECC_CORRECTABLE
- R852_ECC_ERR_BIT_MSK
- R852_ECC_FAIL
- R852_HW
- R852_HW_ENABLED
- R852_HW_UNKNOWN
- R852_SMBIT
- R8A66597_ADDR
- R8A66597_BASE_BUFNUM
- R8A66597_BASE_PIPENUM_BULK
- R8A66597_BASE_PIPENUM_INT
- R8A66597_BASE_PIPENUM_ISOC
- R8A66597_BFRE
- R8A66597_BUF_BSIZE
- R8A66597_BULK
- R8A66597_CNTMD
- R8A66597_DBLB
- R8A66597_DEV_PM_OPS
- R8A66597_DIR
- R8A66597_EPNUM
- R8A66597_INT
- R8A66597_ISO
- R8A66597_MAX_BUFNUM
- R8A66597_MAX_DEVICE
- R8A66597_MAX_DMA_CHANNEL
- R8A66597_MAX_NUM_BULK
- R8A66597_MAX_NUM_INT
- R8A66597_MAX_NUM_ISOC
- R8A66597_MAX_NUM_PIPE
- R8A66597_MAX_ROOT_HUB
- R8A66597_MAX_SAMPLING
- R8A66597_PIPE_NO_DMA
- R8A66597_PLATDATA_XTAL_12MHZ
- R8A66597_PLATDATA_XTAL_24MHZ
- R8A66597_PLATDATA_XTAL_48MHZ
- R8A66597_RH_POLL_TIME
- R8A66597_SHTNAK
- R8A66597_SIZE
- R8A66597_TYP
- R8A73A4_CLK_B
- R8A73A4_CLK_CMT1
- R8A73A4_CLK_DMAC
- R8A73A4_CLK_HP
- R8A73A4_CLK_I
- R8A73A4_CLK_IIC0
- R8A73A4_CLK_IIC1
- R8A73A4_CLK_IIC2
- R8A73A4_CLK_IIC3
- R8A73A4_CLK_IIC4
- R8A73A4_CLK_IIC5
- R8A73A4_CLK_IIC6
- R8A73A4_CLK_IIC7
- R8A73A4_CLK_IIC8
- R8A73A4_CLK_INTC_SYS
- R8A73A4_CLK_IRQC
- R8A73A4_CLK_M1
- R8A73A4_CLK_M2
- R8A73A4_CLK_M3
- R8A73A4_CLK_MAIN
- R8A73A4_CLK_MMCIF0
- R8A73A4_CLK_MMCIF1
- R8A73A4_CLK_PLL0
- R8A73A4_CLK_PLL1
- R8A73A4_CLK_PLL2
- R8A73A4_CLK_PLL2H
- R8A73A4_CLK_PLL2S
- R8A73A4_CLK_SCIFA0
- R8A73A4_CLK_SCIFA1
- R8A73A4_CLK_SCIFB0
- R8A73A4_CLK_SCIFB1
- R8A73A4_CLK_SCIFB2
- R8A73A4_CLK_SCIFB3
- R8A73A4_CLK_SDHI0
- R8A73A4_CLK_SDHI1
- R8A73A4_CLK_SDHI2
- R8A73A4_CLK_THERMAL
- R8A73A4_CLK_Z
- R8A73A4_CLK_Z2
- R8A73A4_CLK_ZS
- R8A73A4_CLK_ZX
- R8A73A4_PIN_IO_PU_PD
- R8A73A4_PIN_O
- R8A7740_CLK_B
- R8A7740_CLK_CEU20
- R8A7740_CLK_CEU21
- R8A7740_CLK_CMT1
- R8A7740_CLK_CP
- R8A7740_CLK_DMAC1
- R8A7740_CLK_DMAC2
- R8A7740_CLK_DMAC3
- R8A7740_CLK_FSI
- R8A7740_CLK_GETHER
- R8A7740_CLK_HP
- R8A7740_CLK_HPP
- R8A7740_CLK_I
- R8A7740_CLK_IIC0
- R8A7740_CLK_IIC1
- R8A7740_CLK_INTCA
- R8A7740_CLK_LCDC0
- R8A7740_CLK_LCDC1
- R8A7740_CLK_M1
- R8A7740_CLK_M3
- R8A7740_CLK_MMC
- R8A7740_CLK_PLLC0
- R8A7740_CLK_PLLC1
- R8A7740_CLK_PLLC2
- R8A7740_CLK_R
- R8A7740_CLK_S
- R8A7740_CLK_SCIFA0
- R8A7740_CLK_SCIFA1
- R8A7740_CLK_SCIFA2
- R8A7740_CLK_SCIFA3
- R8A7740_CLK_SCIFA4
- R8A7740_CLK_SCIFA5
- R8A7740_CLK_SCIFA6
- R8A7740_CLK_SCIFA7
- R8A7740_CLK_SCIFB
- R8A7740_CLK_SDHI0
- R8A7740_CLK_SDHI1
- R8A7740_CLK_SDHI2
- R8A7740_CLK_SUBCK
- R8A7740_CLK_SUBCK2
- R8A7740_CLK_SYSTEM
- R8A7740_CLK_TMU0
- R8A7740_CLK_TMU1
- R8A7740_CLK_TPU0
- R8A7740_CLK_USB24S
- R8A7740_CLK_USBDMAC
- R8A7740_CLK_USBF
- R8A7740_CLK_USBFUNC
- R8A7740_CLK_USBH
- R8A7740_CLK_USBP
- R8A7740_CLK_USBPHY
- R8A7740_CLK_ZB
- R8A7740_CLK_ZG
- R8A7740_PIN_IO
- R8A7740_PIN_IO_PD
- R8A7740_PIN_IO_PU
- R8A7740_PIN_IO_PU_PD
- R8A7740_PIN_I_PD
- R8A7740_PIN_I_PU
- R8A7740_PIN_I_PU_PD
- R8A7740_PIN_O
- R8A7740_PIN_O_PU_PD
- R8A7743_CLK_B
- R8A7743_CLK_CL
- R8A7743_CLK_CP
- R8A7743_CLK_DDR
- R8A7743_CLK_HP
- R8A7743_CLK_LB
- R8A7743_CLK_M2
- R8A7743_CLK_MMC0
- R8A7743_CLK_MP
- R8A7743_CLK_OSC
- R8A7743_CLK_P
- R8A7743_CLK_QSPI
- R8A7743_CLK_R
- R8A7743_CLK_RCAN
- R8A7743_CLK_SD0
- R8A7743_CLK_SD2
- R8A7743_CLK_SD3
- R8A7743_CLK_SDH
- R8A7743_CLK_Z
- R8A7743_CLK_ZB3
- R8A7743_CLK_ZB3D2
- R8A7743_CLK_ZG
- R8A7743_CLK_ZS
- R8A7743_CLK_ZT
- R8A7743_CLK_ZTR
- R8A7743_CLK_ZTRD2
- R8A7743_CLK_ZX
- R8A7743_PD_ALWAYS_ON
- R8A7743_PD_CA15_CPU0
- R8A7743_PD_CA15_CPU1
- R8A7743_PD_CA15_SCU
- R8A7743_PD_SGX
- R8A7744_CLK_B
- R8A7744_CLK_CL
- R8A7744_CLK_CP
- R8A7744_CLK_DDR
- R8A7744_CLK_HP
- R8A7744_CLK_LB
- R8A7744_CLK_M2
- R8A7744_CLK_MMC0
- R8A7744_CLK_MP
- R8A7744_CLK_OSC
- R8A7744_CLK_P
- R8A7744_CLK_QSPI
- R8A7744_CLK_R
- R8A7744_CLK_RCAN
- R8A7744_CLK_SD0
- R8A7744_CLK_SD2
- R8A7744_CLK_SD3
- R8A7744_CLK_SDH
- R8A7744_CLK_Z
- R8A7744_CLK_ZB3
- R8A7744_CLK_ZB3D2
- R8A7744_CLK_ZG
- R8A7744_CLK_ZS
- R8A7744_CLK_ZT
- R8A7744_CLK_ZTR
- R8A7744_CLK_ZTRD2
- R8A7744_CLK_ZX
- R8A7744_PD_ALWAYS_ON
- R8A7744_PD_CA15_CPU0
- R8A7744_PD_CA15_CPU1
- R8A7744_PD_CA15_SCU
- R8A7744_PD_SGX
- R8A7745_CLK_B
- R8A7745_CLK_CL
- R8A7745_CLK_CP
- R8A7745_CLK_CPEX
- R8A7745_CLK_DDR
- R8A7745_CLK_HP
- R8A7745_CLK_LB
- R8A7745_CLK_M2
- R8A7745_CLK_MMC0
- R8A7745_CLK_MP
- R8A7745_CLK_OSC
- R8A7745_CLK_P
- R8A7745_CLK_QSPI
- R8A7745_CLK_R
- R8A7745_CLK_RCAN
- R8A7745_CLK_SD0
- R8A7745_CLK_SD2
- R8A7745_CLK_SD3
- R8A7745_CLK_SDH
- R8A7745_CLK_Z2
- R8A7745_CLK_ZB3
- R8A7745_CLK_ZB3D2
- R8A7745_CLK_ZG
- R8A7745_CLK_ZS
- R8A7745_CLK_ZT
- R8A7745_CLK_ZTR
- R8A7745_CLK_ZTRD2
- R8A7745_CLK_ZX
- R8A7745_PD_ALWAYS_ON
- R8A7745_PD_CA7_CPU0
- R8A7745_PD_CA7_CPU1
- R8A7745_PD_CA7_SCU
- R8A7745_PD_SGX
- R8A77470_CLK_B
- R8A77470_CLK_CL
- R8A77470_CLK_CP
- R8A77470_CLK_CPEX
- R8A77470_CLK_HP
- R8A77470_CLK_LB
- R8A77470_CLK_M2
- R8A77470_CLK_MP
- R8A77470_CLK_OSC
- R8A77470_CLK_P
- R8A77470_CLK_QSPI
- R8A77470_CLK_R
- R8A77470_CLK_RCAN
- R8A77470_CLK_SD0
- R8A77470_CLK_SD1
- R8A77470_CLK_SD2
- R8A77470_CLK_SDH
- R8A77470_CLK_Z2
- R8A77470_CLK_ZB3
- R8A77470_CLK_ZS
- R8A77470_CLK_ZT
- R8A77470_CLK_ZTR
- R8A77470_CLK_ZTRD2
- R8A77470_CLK_ZX
- R8A77470_PD_ALWAYS_ON
- R8A77470_PD_CA7_CPU0
- R8A77470_PD_CA7_CPU1
- R8A77470_PD_CA7_SCU
- R8A77470_PD_SGX
- R8A774A1_CLK_CANFD
- R8A774A1_CLK_CL
- R8A774A1_CLK_CP
- R8A774A1_CLK_CPEX
- R8A774A1_CLK_CR
- R8A774A1_CLK_CRD2
- R8A774A1_CLK_CSI0
- R8A774A1_CLK_HDMI
- R8A774A1_CLK_LB
- R8A774A1_CLK_MSO
- R8A774A1_CLK_OSC
- R8A774A1_CLK_R
- R8A774A1_CLK_RPC
- R8A774A1_CLK_RPCD2
- R8A774A1_CLK_S0D1
- R8A774A1_CLK_S0D12
- R8A774A1_CLK_S0D2
- R8A774A1_CLK_S0D3
- R8A774A1_CLK_S0D4
- R8A774A1_CLK_S0D6
- R8A774A1_CLK_S0D8
- R8A774A1_CLK_S1D2
- R8A774A1_CLK_S1D4
- R8A774A1_CLK_S2D1
- R8A774A1_CLK_S2D2
- R8A774A1_CLK_S2D4
- R8A774A1_CLK_S3D1
- R8A774A1_CLK_S3D2
- R8A774A1_CLK_S3D4
- R8A774A1_CLK_SD0
- R8A774A1_CLK_SD0H
- R8A774A1_CLK_SD1
- R8A774A1_CLK_SD1H
- R8A774A1_CLK_SD2
- R8A774A1_CLK_SD2H
- R8A774A1_CLK_SD3
- R8A774A1_CLK_SD3H
- R8A774A1_CLK_Z
- R8A774A1_CLK_Z2
- R8A774A1_CLK_ZB3
- R8A774A1_CLK_ZB3D2
- R8A774A1_CLK_ZB3D4
- R8A774A1_CLK_ZG
- R8A774A1_CLK_ZT
- R8A774A1_CLK_ZTR
- R8A774A1_CLK_ZTRD2
- R8A774A1_CLK_ZX
- R8A774A1_PD_3DG_A
- R8A774A1_PD_3DG_B
- R8A774A1_PD_A2VC0
- R8A774A1_PD_A2VC1
- R8A774A1_PD_A3VC
- R8A774A1_PD_ALWAYS_ON
- R8A774A1_PD_CA53_CPU0
- R8A774A1_PD_CA53_CPU1
- R8A774A1_PD_CA53_CPU2
- R8A774A1_PD_CA53_CPU3
- R8A774A1_PD_CA53_SCU
- R8A774A1_PD_CA57_CPU0
- R8A774A1_PD_CA57_CPU1
- R8A774A1_PD_CA57_SCU
- R8A774C0_CLK_CANFD
- R8A774C0_CLK_CL
- R8A774C0_CLK_CP
- R8A774C0_CLK_CPEX
- R8A774C0_CLK_CR
- R8A774C0_CLK_CRD2
- R8A774C0_CLK_CSI0
- R8A774C0_CLK_LB
- R8A774C0_CLK_LV0
- R8A774C0_CLK_LV1
- R8A774C0_CLK_MSO
- R8A774C0_CLK_OSC
- R8A774C0_CLK_R
- R8A774C0_CLK_RPC
- R8A774C0_CLK_RPCD2
- R8A774C0_CLK_S0D1
- R8A774C0_CLK_S0D12
- R8A774C0_CLK_S0D24
- R8A774C0_CLK_S0D3
- R8A774C0_CLK_S0D6
- R8A774C0_CLK_S0D6C
- R8A774C0_CLK_S1D1
- R8A774C0_CLK_S1D2
- R8A774C0_CLK_S1D4
- R8A774C0_CLK_S2D1
- R8A774C0_CLK_S2D2
- R8A774C0_CLK_S2D4
- R8A774C0_CLK_S3D1
- R8A774C0_CLK_S3D1C
- R8A774C0_CLK_S3D2
- R8A774C0_CLK_S3D2C
- R8A774C0_CLK_S3D4
- R8A774C0_CLK_S3D4C
- R8A774C0_CLK_SD0
- R8A774C0_CLK_SD0H
- R8A774C0_CLK_SD1
- R8A774C0_CLK_SD1H
- R8A774C0_CLK_SD3
- R8A774C0_CLK_SD3H
- R8A774C0_CLK_Z2
- R8A774C0_CLK_Z2D
- R8A774C0_CLK_ZA2
- R8A774C0_CLK_ZA8
- R8A774C0_CLK_ZB3
- R8A774C0_CLK_ZB3D2
- R8A774C0_CLK_ZG
- R8A774C0_CLK_ZT
- R8A774C0_CLK_ZTR
- R8A774C0_CLK_ZX
- R8A774C0_PD_3DG_A
- R8A774C0_PD_3DG_B
- R8A774C0_PD_A2VC1
- R8A774C0_PD_A3VC
- R8A774C0_PD_ALWAYS_ON
- R8A774C0_PD_CA53_CPU0
- R8A774C0_PD_CA53_CPU1
- R8A774C0_PD_CA53_SCU
- R8A7778_CLK_B
- R8A7778_CLK_ETHER
- R8A7778_CLK_HSCIF0
- R8A7778_CLK_HSCIF1
- R8A7778_CLK_HSPI
- R8A7778_CLK_I2C0
- R8A7778_CLK_I2C1
- R8A7778_CLK_I2C2
- R8A7778_CLK_I2C3
- R8A7778_CLK_MMC
- R8A7778_CLK_OUT
- R8A7778_CLK_P
- R8A7778_CLK_PLLA
- R8A7778_CLK_PLLB
- R8A7778_CLK_S
- R8A7778_CLK_S1
- R8A7778_CLK_SCIF0
- R8A7778_CLK_SCIF1
- R8A7778_CLK_SCIF2
- R8A7778_CLK_SCIF3
- R8A7778_CLK_SCIF4
- R8A7778_CLK_SCIF5
- R8A7778_CLK_SDHI0
- R8A7778_CLK_SDHI1
- R8A7778_CLK_SDHI2
- R8A7778_CLK_SRU
- R8A7778_CLK_SRU_SRC0
- R8A7778_CLK_SRU_SRC1
- R8A7778_CLK_SRU_SRC2
- R8A7778_CLK_SRU_SRC3
- R8A7778_CLK_SRU_SRC4
- R8A7778_CLK_SRU_SRC5
- R8A7778_CLK_SRU_SRC6
- R8A7778_CLK_SRU_SRC7
- R8A7778_CLK_SRU_SRC8
- R8A7778_CLK_SSI0
- R8A7778_CLK_SSI1
- R8A7778_CLK_SSI2
- R8A7778_CLK_SSI3
- R8A7778_CLK_SSI4
- R8A7778_CLK_SSI5
- R8A7778_CLK_SSI6
- R8A7778_CLK_SSI7
- R8A7778_CLK_SSI8
- R8A7778_CLK_TMU0
- R8A7778_CLK_TMU1
- R8A7778_CLK_TMU2
- R8A7778_CLK_USB
- R8A7778_CLK_VIN0
- R8A7778_CLK_VIN1
- R8A7779_CLK_B
- R8A7779_CLK_DU
- R8A7779_CLK_ETHER
- R8A7779_CLK_HSCIF0
- R8A7779_CLK_HSCIF1
- R8A7779_CLK_HSPI
- R8A7779_CLK_I2C0
- R8A7779_CLK_I2C1
- R8A7779_CLK_I2C2
- R8A7779_CLK_I2C3
- R8A7779_CLK_MMC0
- R8A7779_CLK_MMC1
- R8A7779_CLK_OUT
- R8A7779_CLK_P
- R8A7779_CLK_PCIE
- R8A7779_CLK_PLLA
- R8A7779_CLK_S
- R8A7779_CLK_S1
- R8A7779_CLK_SATA
- R8A7779_CLK_SCIF0
- R8A7779_CLK_SCIF1
- R8A7779_CLK_SCIF2
- R8A7779_CLK_SCIF3
- R8A7779_CLK_SCIF4
- R8A7779_CLK_SCIF5
- R8A7779_CLK_SDHI0
- R8A7779_CLK_SDHI1
- R8A7779_CLK_SDHI2
- R8A7779_CLK_SDHI3
- R8A7779_CLK_TMU0
- R8A7779_CLK_TMU1
- R8A7779_CLK_TMU2
- R8A7779_CLK_USB01
- R8A7779_CLK_USB2
- R8A7779_CLK_VIN0
- R8A7779_CLK_VIN1
- R8A7779_CLK_VIN2
- R8A7779_CLK_VIN3
- R8A7779_CLK_Z
- R8A7779_CLK_ZS
- R8A7779_PD_ALWAYS_ON
- R8A7779_PD_ARM1
- R8A7779_PD_ARM2
- R8A7779_PD_ARM3
- R8A7779_PD_IMP
- R8A7779_PD_SGX
- R8A7779_PD_VDP
- R8A7779_SCU_BASE
- R8A7790_CLK_2DDMAC
- R8A7790_CLK_3DG
- R8A7790_CLK_ADSP
- R8A7790_CLK_ADSP_MOD
- R8A7790_CLK_AUDIO_DMAC0
- R8A7790_CLK_AUDIO_DMAC1
- R8A7790_CLK_B
- R8A7790_CLK_CL
- R8A7790_CLK_CMT0
- R8A7790_CLK_CMT1
- R8A7790_CLK_CP
- R8A7790_CLK_DDR
- R8A7790_CLK_DU0
- R8A7790_CLK_DU1
- R8A7790_CLK_DU2
- R8A7790_CLK_EHCI
- R8A7790_CLK_ETHER
- R8A7790_CLK_ETHERAVB
- R8A7790_CLK_FDP1_0
- R8A7790_CLK_FDP1_1
- R8A7790_CLK_FDP1_2
- R8A7790_CLK_GPIO0
- R8A7790_CLK_GPIO1
- R8A7790_CLK_GPIO2
- R8A7790_CLK_GPIO3
- R8A7790_CLK_GPIO4
- R8A7790_CLK_GPIO5
- R8A7790_CLK_HP
- R8A7790_CLK_HSCIF0
- R8A7790_CLK_HSCIF1
- R8A7790_CLK_HSUSB
- R8A7790_CLK_I
- R8A7790_CLK_I2C0
- R8A7790_CLK_I2C1
- R8A7790_CLK_I2C2
- R8A7790_CLK_I2C3
- R8A7790_CLK_IIC0
- R8A7790_CLK_IIC1
- R8A7790_CLK_IIC2
- R8A7790_CLK_IICDVFS
- R8A7790_CLK_IMP
- R8A7790_CLK_INTC_SYS
- R8A7790_CLK_IRQC
- R8A7790_CLK_JPU
- R8A7790_CLK_LB
- R8A7790_CLK_LVDS0
- R8A7790_CLK_LVDS1
- R8A7790_CLK_M2
- R8A7790_CLK_MAIN
- R8A7790_CLK_MLB
- R8A7790_CLK_MMC0
- R8A7790_CLK_MMC1
- R8A7790_CLK_MMCIF0
- R8A7790_CLK_MMCIF1
- R8A7790_CLK_MP
- R8A7790_CLK_MSIOF0
- R8A7790_CLK_MSIOF1
- R8A7790_CLK_MSIOF2
- R8A7790_CLK_MSIOF3
- R8A7790_CLK_OSC
- R8A7790_CLK_P
- R8A7790_CLK_PCIEC
- R8A7790_CLK_PLL0
- R8A7790_CLK_PLL1
- R8A7790_CLK_PLL3
- R8A7790_CLK_PWM
- R8A7790_CLK_QSPI
- R8A7790_CLK_QSPI_MOD
- R8A7790_CLK_R
- R8A7790_CLK_RCAN
- R8A7790_CLK_RCAN0
- R8A7790_CLK_RCAN1
- R8A7790_CLK_SATA0
- R8A7790_CLK_SATA1
- R8A7790_CLK_SCIF0
- R8A7790_CLK_SCIF1
- R8A7790_CLK_SCIF2
- R8A7790_CLK_SCIFA0
- R8A7790_CLK_SCIFA1
- R8A7790_CLK_SCIFA2
- R8A7790_CLK_SCIFB0
- R8A7790_CLK_SCIFB1
- R8A7790_CLK_SCIFB2
- R8A7790_CLK_SCU_ALL
- R8A7790_CLK_SCU_CTU0_MIX0
- R8A7790_CLK_SCU_CTU1_MIX1
- R8A7790_CLK_SCU_DVC0
- R8A7790_CLK_SCU_DVC1
- R8A7790_CLK_SCU_SRC0
- R8A7790_CLK_SCU_SRC1
- R8A7790_CLK_SCU_SRC2
- R8A7790_CLK_SCU_SRC3
- R8A7790_CLK_SCU_SRC4
- R8A7790_CLK_SCU_SRC5
- R8A7790_CLK_SCU_SRC6
- R8A7790_CLK_SCU_SRC7
- R8A7790_CLK_SCU_SRC8
- R8A7790_CLK_SCU_SRC9
- R8A7790_CLK_SD0
- R8A7790_CLK_SD1
- R8A7790_CLK_SD2
- R8A7790_CLK_SD3
- R8A7790_CLK_SDH
- R8A7790_CLK_SDHI0
- R8A7790_CLK_SDHI1
- R8A7790_CLK_SDHI2
- R8A7790_CLK_SDHI3
- R8A7790_CLK_SSI0
- R8A7790_CLK_SSI1
- R8A7790_CLK_SSI2
- R8A7790_CLK_SSI3
- R8A7790_CLK_SSI4
- R8A7790_CLK_SSI5
- R8A7790_CLK_SSI6
- R8A7790_CLK_SSI7
- R8A7790_CLK_SSI8
- R8A7790_CLK_SSI9
- R8A7790_CLK_SSI_ALL
- R8A7790_CLK_SSP
- R8A7790_CLK_SSP1
- R8A7790_CLK_SSPRS
- R8A7790_CLK_SSUSB
- R8A7790_CLK_SYS_DMAC0
- R8A7790_CLK_SYS_DMAC1
- R8A7790_CLK_THERMAL
- R8A7790_CLK_TMU0
- R8A7790_CLK_TMU1
- R8A7790_CLK_TMU2
- R8A7790_CLK_TMU3
- R8A7790_CLK_TPU0
- R8A7790_CLK_USBDMAC0
- R8A7790_CLK_USBDMAC1
- R8A7790_CLK_VCP0
- R8A7790_CLK_VCP1
- R8A7790_CLK_VIN0
- R8A7790_CLK_VIN1
- R8A7790_CLK_VIN2
- R8A7790_CLK_VIN3
- R8A7790_CLK_VPC0
- R8A7790_CLK_VPC1
- R8A7790_CLK_VSP1_DU0
- R8A7790_CLK_VSP1_DU1
- R8A7790_CLK_VSP1_R
- R8A7790_CLK_VSP1_S
- R8A7790_CLK_Z
- R8A7790_CLK_Z2
- R8A7790_CLK_ZB3
- R8A7790_CLK_ZB3D2
- R8A7790_CLK_ZG
- R8A7790_CLK_ZS
- R8A7790_CLK_ZT
- R8A7790_CLK_ZTR
- R8A7790_CLK_ZTRD2
- R8A7790_CLK_ZX
- R8A7790_PD_ALWAYS_ON
- R8A7790_PD_CA15_CPU0
- R8A7790_PD_CA15_CPU1
- R8A7790_PD_CA15_CPU2
- R8A7790_PD_CA15_CPU3
- R8A7790_PD_CA15_SCU
- R8A7790_PD_CA7_CPU0
- R8A7790_PD_CA7_CPU1
- R8A7790_PD_CA7_CPU2
- R8A7790_PD_CA7_CPU3
- R8A7790_PD_CA7_SCU
- R8A7790_PD_IMP
- R8A7790_PD_RGX
- R8A7790_PD_SH_4A
- R8A7791_CLK_2DDMAC
- R8A7791_CLK_3DG
- R8A7791_CLK_ADSP
- R8A7791_CLK_ADSP_MOD
- R8A7791_CLK_AUDIO_DMAC0
- R8A7791_CLK_AUDIO_DMAC1
- R8A7791_CLK_B
- R8A7791_CLK_CL
- R8A7791_CLK_CMT0
- R8A7791_CLK_CMT1
- R8A7791_CLK_CP
- R8A7791_CLK_DDR
- R8A7791_CLK_DU0
- R8A7791_CLK_DU1
- R8A7791_CLK_EHCI
- R8A7791_CLK_ETHER
- R8A7791_CLK_ETHERAVB
- R8A7791_CLK_FDP1_0
- R8A7791_CLK_FDP1_1
- R8A7791_CLK_GPIO0
- R8A7791_CLK_GPIO1
- R8A7791_CLK_GPIO2
- R8A7791_CLK_GPIO3
- R8A7791_CLK_GPIO4
- R8A7791_CLK_GPIO5
- R8A7791_CLK_GPIO6
- R8A7791_CLK_GPIO7
- R8A7791_CLK_GYROADC
- R8A7791_CLK_HP
- R8A7791_CLK_HSCIF0
- R8A7791_CLK_HSCIF1
- R8A7791_CLK_HSCIF2
- R8A7791_CLK_HSUSB
- R8A7791_CLK_I
- R8A7791_CLK_I2C0
- R8A7791_CLK_I2C1
- R8A7791_CLK_I2C2
- R8A7791_CLK_I2C3
- R8A7791_CLK_I2C4
- R8A7791_CLK_I2C5
- R8A7791_CLK_IIC0
- R8A7791_CLK_IIC1
- R8A7791_CLK_IICDVFS
- R8A7791_CLK_INTC_SYS
- R8A7791_CLK_IPMMU_SGX
- R8A7791_CLK_IRQC
- R8A7791_CLK_JPU
- R8A7791_CLK_LB
- R8A7791_CLK_LVDS0
- R8A7791_CLK_M2
- R8A7791_CLK_MAIN
- R8A7791_CLK_MLB
- R8A7791_CLK_MMC0
- R8A7791_CLK_MMCIF0
- R8A7791_CLK_MP
- R8A7791_CLK_MSIOF0
- R8A7791_CLK_MSIOF1
- R8A7791_CLK_MSIOF2
- R8A7791_CLK_OSC
- R8A7791_CLK_P
- R8A7791_CLK_PCIEC
- R8A7791_CLK_PLL0
- R8A7791_CLK_PLL1
- R8A7791_CLK_PLL3
- R8A7791_CLK_PWM
- R8A7791_CLK_QSPI
- R8A7791_CLK_QSPI_MOD
- R8A7791_CLK_R
- R8A7791_CLK_RCAN
- R8A7791_CLK_RCAN0
- R8A7791_CLK_RCAN1
- R8A7791_CLK_SATA0
- R8A7791_CLK_SATA1
- R8A7791_CLK_SCIF0
- R8A7791_CLK_SCIF1
- R8A7791_CLK_SCIF2
- R8A7791_CLK_SCIF3
- R8A7791_CLK_SCIF4
- R8A7791_CLK_SCIF5
- R8A7791_CLK_SCIFA0
- R8A7791_CLK_SCIFA1
- R8A7791_CLK_SCIFA2
- R8A7791_CLK_SCIFA3
- R8A7791_CLK_SCIFA4
- R8A7791_CLK_SCIFA5
- R8A7791_CLK_SCIFB0
- R8A7791_CLK_SCIFB1
- R8A7791_CLK_SCIFB2
- R8A7791_CLK_SCU_ALL
- R8A7791_CLK_SCU_CTU0_MIX0
- R8A7791_CLK_SCU_CTU1_MIX1
- R8A7791_CLK_SCU_DVC0
- R8A7791_CLK_SCU_DVC1
- R8A7791_CLK_SCU_SRC0
- R8A7791_CLK_SCU_SRC1
- R8A7791_CLK_SCU_SRC2
- R8A7791_CLK_SCU_SRC3
- R8A7791_CLK_SCU_SRC4
- R8A7791_CLK_SCU_SRC5
- R8A7791_CLK_SCU_SRC6
- R8A7791_CLK_SCU_SRC7
- R8A7791_CLK_SCU_SRC8
- R8A7791_CLK_SCU_SRC9
- R8A7791_CLK_SD0
- R8A7791_CLK_SD2
- R8A7791_CLK_SD3
- R8A7791_CLK_SDH
- R8A7791_CLK_SDHI0
- R8A7791_CLK_SDHI1
- R8A7791_CLK_SDHI2
- R8A7791_CLK_SSI0
- R8A7791_CLK_SSI1
- R8A7791_CLK_SSI2
- R8A7791_CLK_SSI3
- R8A7791_CLK_SSI4
- R8A7791_CLK_SSI5
- R8A7791_CLK_SSI6
- R8A7791_CLK_SSI7
- R8A7791_CLK_SSI8
- R8A7791_CLK_SSI9
- R8A7791_CLK_SSI_ALL
- R8A7791_CLK_SSP
- R8A7791_CLK_SSP1
- R8A7791_CLK_SSPRS
- R8A7791_CLK_SSUSB
- R8A7791_CLK_SYS_DMAC0
- R8A7791_CLK_SYS_DMAC1
- R8A7791_CLK_THERMAL
- R8A7791_CLK_TMU0
- R8A7791_CLK_TMU1
- R8A7791_CLK_TMU2
- R8A7791_CLK_TMU3
- R8A7791_CLK_TPU0
- R8A7791_CLK_USBDMAC0
- R8A7791_CLK_USBDMAC1
- R8A7791_CLK_VCP0
- R8A7791_CLK_VIN0
- R8A7791_CLK_VIN1
- R8A7791_CLK_VIN2
- R8A7791_CLK_VPC0
- R8A7791_CLK_VSP1_DU0
- R8A7791_CLK_VSP1_DU1
- R8A7791_CLK_VSP1_S
- R8A7791_CLK_Z
- R8A7791_CLK_ZB3
- R8A7791_CLK_ZB3D2
- R8A7791_CLK_ZG
- R8A7791_CLK_ZS
- R8A7791_CLK_ZT
- R8A7791_CLK_ZTR
- R8A7791_CLK_ZTRD2
- R8A7791_CLK_ZX
- R8A7791_PD_ALWAYS_ON
- R8A7791_PD_CA15_CPU0
- R8A7791_PD_CA15_CPU1
- R8A7791_PD_CA15_SCU
- R8A7791_PD_SGX
- R8A7791_PD_SH_4A
- R8A7792_CLK_AUDIO_DMAC0
- R8A7792_CLK_B
- R8A7792_CLK_CAN0
- R8A7792_CLK_CAN1
- R8A7792_CLK_CL
- R8A7792_CLK_CMT0
- R8A7792_CLK_CMT1
- R8A7792_CLK_CP
- R8A7792_CLK_CPEX
- R8A7792_CLK_DDR
- R8A7792_CLK_DU0
- R8A7792_CLK_DU1
- R8A7792_CLK_ETHERAVB
- R8A7792_CLK_GPIO0
- R8A7792_CLK_GPIO1
- R8A7792_CLK_GPIO10
- R8A7792_CLK_GPIO11
- R8A7792_CLK_GPIO2
- R8A7792_CLK_GPIO3
- R8A7792_CLK_GPIO4
- R8A7792_CLK_GPIO5
- R8A7792_CLK_GPIO6
- R8A7792_CLK_GPIO7
- R8A7792_CLK_GPIO8
- R8A7792_CLK_GPIO9
- R8A7792_CLK_HP
- R8A7792_CLK_HSCIF0
- R8A7792_CLK_HSCIF1
- R8A7792_CLK_I
- R8A7792_CLK_I2C0
- R8A7792_CLK_I2C1
- R8A7792_CLK_I2C2
- R8A7792_CLK_I2C3
- R8A7792_CLK_I2C4
- R8A7792_CLK_I2C5
- R8A7792_CLK_IICDVFS
- R8A7792_CLK_IMP
- R8A7792_CLK_INTC_SYS
- R8A7792_CLK_IRQC
- R8A7792_CLK_JPU
- R8A7792_CLK_LB
- R8A7792_CLK_M2
- R8A7792_CLK_MAIN
- R8A7792_CLK_MP
- R8A7792_CLK_MSIOF0
- R8A7792_CLK_MSIOF1
- R8A7792_CLK_OSC
- R8A7792_CLK_P
- R8A7792_CLK_PLL0
- R8A7792_CLK_PLL1
- R8A7792_CLK_PLL3
- R8A7792_CLK_PWM
- R8A7792_CLK_QSPI
- R8A7792_CLK_QSPI_MOD
- R8A7792_CLK_R
- R8A7792_CLK_RCAN
- R8A7792_CLK_SCIF0
- R8A7792_CLK_SCIF1
- R8A7792_CLK_SCIF2
- R8A7792_CLK_SCIF3
- R8A7792_CLK_SD
- R8A7792_CLK_SDHI0
- R8A7792_CLK_SSI3
- R8A7792_CLK_SSI4
- R8A7792_CLK_SSI_ALL
- R8A7792_CLK_SYS_DMAC0
- R8A7792_CLK_SYS_DMAC1
- R8A7792_CLK_THERMAL
- R8A7792_CLK_TMU0
- R8A7792_CLK_TMU1
- R8A7792_CLK_TMU2
- R8A7792_CLK_TMU3
- R8A7792_CLK_TPU0
- R8A7792_CLK_VIN0
- R8A7792_CLK_VIN1
- R8A7792_CLK_VIN2
- R8A7792_CLK_VIN3
- R8A7792_CLK_VIN4
- R8A7792_CLK_VIN5
- R8A7792_CLK_VSP1DU0
- R8A7792_CLK_VSP1DU1
- R8A7792_CLK_VSP1_SY
- R8A7792_CLK_Z
- R8A7792_CLK_ZB3
- R8A7792_CLK_ZB3D2
- R8A7792_CLK_ZG
- R8A7792_CLK_ZS
- R8A7792_CLK_ZT
- R8A7792_CLK_ZTR
- R8A7792_CLK_ZTRD2
- R8A7792_CLK_ZX
- R8A7792_PD_ALWAYS_ON
- R8A7792_PD_CA15_CPU0
- R8A7792_PD_CA15_CPU1
- R8A7792_PD_CA15_SCU
- R8A7792_PD_IMP
- R8A7792_PD_SGX
- R8A7793_CLK_2DDMAC
- R8A7793_CLK_3DG
- R8A7793_CLK_ADSP
- R8A7793_CLK_ADSP_MOD
- R8A7793_CLK_AUDIO_DMAC0
- R8A7793_CLK_AUDIO_DMAC1
- R8A7793_CLK_B
- R8A7793_CLK_CL
- R8A7793_CLK_CMT0
- R8A7793_CLK_CMT1
- R8A7793_CLK_CP
- R8A7793_CLK_DDR
- R8A7793_CLK_DU0
- R8A7793_CLK_DU1
- R8A7793_CLK_EHCI
- R8A7793_CLK_ETHER
- R8A7793_CLK_FDP1_0
- R8A7793_CLK_FDP1_1
- R8A7793_CLK_GPIO0
- R8A7793_CLK_GPIO1
- R8A7793_CLK_GPIO2
- R8A7793_CLK_GPIO3
- R8A7793_CLK_GPIO4
- R8A7793_CLK_GPIO5
- R8A7793_CLK_GPIO6
- R8A7793_CLK_GPIO7
- R8A7793_CLK_HP
- R8A7793_CLK_HSCIF0
- R8A7793_CLK_HSCIF1
- R8A7793_CLK_HSCIF2
- R8A7793_CLK_HSUSB
- R8A7793_CLK_I
- R8A7793_CLK_I2C0
- R8A7793_CLK_I2C1
- R8A7793_CLK_I2C2
- R8A7793_CLK_I2C3
- R8A7793_CLK_I2C4
- R8A7793_CLK_I2C5
- R8A7793_CLK_IIC0
- R8A7793_CLK_IIC1
- R8A7793_CLK_IICDVFS
- R8A7793_CLK_INTC_SYS
- R8A7793_CLK_IPMMU_SGX
- R8A7793_CLK_IRQC
- R8A7793_CLK_LB
- R8A7793_CLK_LVDS0
- R8A7793_CLK_M2
- R8A7793_CLK_MAIN
- R8A7793_CLK_MMC0
- R8A7793_CLK_MMCIF0
- R8A7793_CLK_MP
- R8A7793_CLK_MSIOF0
- R8A7793_CLK_MSIOF1
- R8A7793_CLK_MSIOF2
- R8A7793_CLK_OSC
- R8A7793_CLK_P
- R8A7793_CLK_PCIEC
- R8A7793_CLK_PLL0
- R8A7793_CLK_PLL1
- R8A7793_CLK_PLL3
- R8A7793_CLK_PWM
- R8A7793_CLK_QSPI
- R8A7793_CLK_QSPI_MOD
- R8A7793_CLK_R
- R8A7793_CLK_RCAN
- R8A7793_CLK_RCAN0
- R8A7793_CLK_RCAN1
- R8A7793_CLK_SATA0
- R8A7793_CLK_SATA1
- R8A7793_CLK_SCIF0
- R8A7793_CLK_SCIF1
- R8A7793_CLK_SCIF2
- R8A7793_CLK_SCIF3
- R8A7793_CLK_SCIF4
- R8A7793_CLK_SCIF5
- R8A7793_CLK_SCIFA0
- R8A7793_CLK_SCIFA1
- R8A7793_CLK_SCIFA2
- R8A7793_CLK_SCIFA3
- R8A7793_CLK_SCIFA4
- R8A7793_CLK_SCIFA5
- R8A7793_CLK_SCIFB0
- R8A7793_CLK_SCIFB1
- R8A7793_CLK_SCIFB2
- R8A7793_CLK_SCU_ALL
- R8A7793_CLK_SCU_CTU0_MIX0
- R8A7793_CLK_SCU_CTU1_MIX1
- R8A7793_CLK_SCU_DVC0
- R8A7793_CLK_SCU_DVC1
- R8A7793_CLK_SCU_SRC0
- R8A7793_CLK_SCU_SRC1
- R8A7793_CLK_SCU_SRC2
- R8A7793_CLK_SCU_SRC3
- R8A7793_CLK_SCU_SRC4
- R8A7793_CLK_SCU_SRC5
- R8A7793_CLK_SCU_SRC6
- R8A7793_CLK_SCU_SRC7
- R8A7793_CLK_SCU_SRC8
- R8A7793_CLK_SCU_SRC9
- R8A7793_CLK_SD0
- R8A7793_CLK_SD2
- R8A7793_CLK_SD3
- R8A7793_CLK_SDH
- R8A7793_CLK_SDHI0
- R8A7793_CLK_SDHI1
- R8A7793_CLK_SDHI2
- R8A7793_CLK_SSI0
- R8A7793_CLK_SSI1
- R8A7793_CLK_SSI2
- R8A7793_CLK_SSI3
- R8A7793_CLK_SSI4
- R8A7793_CLK_SSI5
- R8A7793_CLK_SSI6
- R8A7793_CLK_SSI7
- R8A7793_CLK_SSI8
- R8A7793_CLK_SSI9
- R8A7793_CLK_SSI_ALL
- R8A7793_CLK_SSP
- R8A7793_CLK_SSP1
- R8A7793_CLK_SSPRS
- R8A7793_CLK_SSUSB
- R8A7793_CLK_SYS_DMAC0
- R8A7793_CLK_SYS_DMAC1
- R8A7793_CLK_THERMAL
- R8A7793_CLK_TMU0
- R8A7793_CLK_TMU1
- R8A7793_CLK_TMU2
- R8A7793_CLK_TMU3
- R8A7793_CLK_TPU0
- R8A7793_CLK_USBDMAC0
- R8A7793_CLK_USBDMAC1
- R8A7793_CLK_VCP0
- R8A7793_CLK_VIN0
- R8A7793_CLK_VIN1
- R8A7793_CLK_VIN2
- R8A7793_CLK_VPC0
- R8A7793_CLK_VSP1_DU0
- R8A7793_CLK_VSP1_DU1
- R8A7793_CLK_VSP1_S
- R8A7793_CLK_Z
- R8A7793_CLK_ZB3
- R8A7793_CLK_ZB3D2
- R8A7793_CLK_ZG
- R8A7793_CLK_ZS
- R8A7793_CLK_ZT
- R8A7793_CLK_ZTR
- R8A7793_CLK_ZTRD2
- R8A7793_CLK_ZX
- R8A7793_PD_ALWAYS_ON
- R8A7793_PD_CA15_CPU0
- R8A7793_PD_CA15_CPU1
- R8A7793_PD_CA15_SCU
- R8A7793_PD_SGX
- R8A7793_PD_SH_4A
- R8A7794_CLK_2DDMAC
- R8A7794_CLK_3DG
- R8A7794_CLK_ADSP
- R8A7794_CLK_AUDIO_DMAC0
- R8A7794_CLK_B
- R8A7794_CLK_CL
- R8A7794_CLK_CMT0
- R8A7794_CLK_CMT1
- R8A7794_CLK_CP
- R8A7794_CLK_CPEX
- R8A7794_CLK_DDR
- R8A7794_CLK_DU0
- R8A7794_CLK_DU1
- R8A7794_CLK_EHCI
- R8A7794_CLK_ETHER
- R8A7794_CLK_ETHERAVB
- R8A7794_CLK_FDP1_0
- R8A7794_CLK_GPIO0
- R8A7794_CLK_GPIO1
- R8A7794_CLK_GPIO2
- R8A7794_CLK_GPIO3
- R8A7794_CLK_GPIO4
- R8A7794_CLK_GPIO5
- R8A7794_CLK_GPIO6
- R8A7794_CLK_HP
- R8A7794_CLK_HSCIF0
- R8A7794_CLK_HSCIF1
- R8A7794_CLK_HSCIF2
- R8A7794_CLK_HSUSB
- R8A7794_CLK_I
- R8A7794_CLK_I2C0
- R8A7794_CLK_I2C1
- R8A7794_CLK_I2C2
- R8A7794_CLK_I2C3
- R8A7794_CLK_I2C4
- R8A7794_CLK_I2C5
- R8A7794_CLK_IIC0
- R8A7794_CLK_IIC1
- R8A7794_CLK_INTC_SYS
- R8A7794_CLK_IRQC
- R8A7794_CLK_LB
- R8A7794_CLK_M2
- R8A7794_CLK_MAIN
- R8A7794_CLK_MMC0
- R8A7794_CLK_MMCIF0
- R8A7794_CLK_MP
- R8A7794_CLK_MSIOF0
- R8A7794_CLK_MSIOF1
- R8A7794_CLK_MSIOF2
- R8A7794_CLK_OSC
- R8A7794_CLK_P
- R8A7794_CLK_PLL0
- R8A7794_CLK_PLL1
- R8A7794_CLK_PLL3
- R8A7794_CLK_PWM
- R8A7794_CLK_QSPI
- R8A7794_CLK_QSPI_MOD
- R8A7794_CLK_R
- R8A7794_CLK_RCAN
- R8A7794_CLK_RCAN0
- R8A7794_CLK_RCAN1
- R8A7794_CLK_SCIF0
- R8A7794_CLK_SCIF1
- R8A7794_CLK_SCIF2
- R8A7794_CLK_SCIF3
- R8A7794_CLK_SCIF4
- R8A7794_CLK_SCIF5
- R8A7794_CLK_SCIFA0
- R8A7794_CLK_SCIFA1
- R8A7794_CLK_SCIFA2
- R8A7794_CLK_SCIFA3
- R8A7794_CLK_SCIFA4
- R8A7794_CLK_SCIFA5
- R8A7794_CLK_SCIFB0
- R8A7794_CLK_SCIFB1
- R8A7794_CLK_SCIFB2
- R8A7794_CLK_SCU_ALL
- R8A7794_CLK_SCU_CTU0_MIX0
- R8A7794_CLK_SCU_CTU1_MIX1
- R8A7794_CLK_SCU_DVC0
- R8A7794_CLK_SCU_DVC1
- R8A7794_CLK_SCU_SRC1
- R8A7794_CLK_SCU_SRC2
- R8A7794_CLK_SCU_SRC3
- R8A7794_CLK_SCU_SRC4
- R8A7794_CLK_SCU_SRC5
- R8A7794_CLK_SCU_SRC6
- R8A7794_CLK_SD0
- R8A7794_CLK_SD2
- R8A7794_CLK_SD3
- R8A7794_CLK_SDH
- R8A7794_CLK_SDHI0
- R8A7794_CLK_SDHI1
- R8A7794_CLK_SDHI2
- R8A7794_CLK_SSI0
- R8A7794_CLK_SSI1
- R8A7794_CLK_SSI2
- R8A7794_CLK_SSI3
- R8A7794_CLK_SSI4
- R8A7794_CLK_SSI5
- R8A7794_CLK_SSI6
- R8A7794_CLK_SSI7
- R8A7794_CLK_SSI8
- R8A7794_CLK_SSI9
- R8A7794_CLK_SSI_ALL
- R8A7794_CLK_SYS_DMAC0
- R8A7794_CLK_SYS_DMAC1
- R8A7794_CLK_TMU0
- R8A7794_CLK_TMU1
- R8A7794_CLK_TMU2
- R8A7794_CLK_TMU3
- R8A7794_CLK_USBDMAC0
- R8A7794_CLK_USBDMAC1
- R8A7794_CLK_VCP0
- R8A7794_CLK_VIN0
- R8A7794_CLK_VIN1
- R8A7794_CLK_VPC0
- R8A7794_CLK_VSP1_DU0
- R8A7794_CLK_VSP1_S
- R8A7794_CLK_Z2
- R8A7794_CLK_ZB3
- R8A7794_CLK_ZB3D2
- R8A7794_CLK_ZG
- R8A7794_CLK_ZS
- R8A7794_CLK_ZT
- R8A7794_CLK_ZTR
- R8A7794_CLK_ZTRD2
- R8A7794_CLK_ZX
- R8A7794_PD_ALWAYS_ON
- R8A7794_PD_CA7_CPU0
- R8A7794_PD_CA7_CPU1
- R8A7794_PD_CA7_SCU
- R8A7794_PD_SGX
- R8A7794_PD_SH_4A
- R8A7795_CLK_CANFD
- R8A7795_CLK_CL
- R8A7795_CLK_CP
- R8A7795_CLK_CPEX
- R8A7795_CLK_CR
- R8A7795_CLK_CRD2
- R8A7795_CLK_CSI0
- R8A7795_CLK_HDMI
- R8A7795_CLK_LB
- R8A7795_CLK_MSO
- R8A7795_CLK_OSC
- R8A7795_CLK_R
- R8A7795_CLK_RPC
- R8A7795_CLK_RPCD2
- R8A7795_CLK_S0D1
- R8A7795_CLK_S0D12
- R8A7795_CLK_S0D2
- R8A7795_CLK_S0D3
- R8A7795_CLK_S0D4
- R8A7795_CLK_S0D6
- R8A7795_CLK_S0D8
- R8A7795_CLK_S1D1
- R8A7795_CLK_S1D2
- R8A7795_CLK_S1D4
- R8A7795_CLK_S2D1
- R8A7795_CLK_S2D2
- R8A7795_CLK_S2D4
- R8A7795_CLK_S3D1
- R8A7795_CLK_S3D2
- R8A7795_CLK_S3D4
- R8A7795_CLK_SD0
- R8A7795_CLK_SD0H
- R8A7795_CLK_SD1
- R8A7795_CLK_SD1H
- R8A7795_CLK_SD2
- R8A7795_CLK_SD2H
- R8A7795_CLK_SD3
- R8A7795_CLK_SD3H
- R8A7795_CLK_SSP1
- R8A7795_CLK_SSP2
- R8A7795_CLK_SSPRS
- R8A7795_CLK_Z
- R8A7795_CLK_Z2
- R8A7795_CLK_ZB3
- R8A7795_CLK_ZB3D2
- R8A7795_CLK_ZG
- R8A7795_CLK_ZR
- R8A7795_CLK_ZT
- R8A7795_CLK_ZTR
- R8A7795_CLK_ZTRD2
- R8A7795_CLK_ZX
- R8A7795_PD_3DG_A
- R8A7795_PD_3DG_B
- R8A7795_PD_3DG_C
- R8A7795_PD_3DG_D
- R8A7795_PD_3DG_E
- R8A7795_PD_A2VC0
- R8A7795_PD_A2VC1
- R8A7795_PD_A3IR
- R8A7795_PD_A3VC
- R8A7795_PD_A3VP
- R8A7795_PD_ALWAYS_ON
- R8A7795_PD_CA53_CPU0
- R8A7795_PD_CA53_CPU1
- R8A7795_PD_CA53_CPU2
- R8A7795_PD_CA53_CPU3
- R8A7795_PD_CA53_SCU
- R8A7795_PD_CA57_CPU0
- R8A7795_PD_CA57_CPU1
- R8A7795_PD_CA57_CPU2
- R8A7795_PD_CA57_CPU3
- R8A7795_PD_CA57_SCU
- R8A7795_PD_CR7
- R8A77965_CLK_CANFD
- R8A77965_CLK_CL
- R8A77965_CLK_CP
- R8A77965_CLK_CPEX
- R8A77965_CLK_CR
- R8A77965_CLK_CRD2
- R8A77965_CLK_CSI0
- R8A77965_CLK_HDMI
- R8A77965_CLK_LB
- R8A77965_CLK_MSO
- R8A77965_CLK_OSC
- R8A77965_CLK_R
- R8A77965_CLK_RPC
- R8A77965_CLK_RPCD2
- R8A77965_CLK_S0D1
- R8A77965_CLK_S0D12
- R8A77965_CLK_S0D2
- R8A77965_CLK_S0D3
- R8A77965_CLK_S0D4
- R8A77965_CLK_S0D6
- R8A77965_CLK_S0D8
- R8A77965_CLK_S1D1
- R8A77965_CLK_S1D2
- R8A77965_CLK_S1D4
- R8A77965_CLK_S2D1
- R8A77965_CLK_S2D2
- R8A77965_CLK_S2D4
- R8A77965_CLK_S3D1
- R8A77965_CLK_S3D2
- R8A77965_CLK_S3D4
- R8A77965_CLK_SD0
- R8A77965_CLK_SD0H
- R8A77965_CLK_SD1
- R8A77965_CLK_SD1H
- R8A77965_CLK_SD2
- R8A77965_CLK_SD2H
- R8A77965_CLK_SD3
- R8A77965_CLK_SD3H
- R8A77965_CLK_SSP1
- R8A77965_CLK_SSP2
- R8A77965_CLK_SSPRS
- R8A77965_CLK_Z
- R8A77965_CLK_ZB3
- R8A77965_CLK_ZB3D2
- R8A77965_CLK_ZG
- R8A77965_CLK_ZR
- R8A77965_CLK_ZT
- R8A77965_CLK_ZTR
- R8A77965_CLK_ZTRD2
- R8A77965_CLK_ZX
- R8A77965_PD_3DG_A
- R8A77965_PD_3DG_B
- R8A77965_PD_A2VC1
- R8A77965_PD_A3VC
- R8A77965_PD_A3VP
- R8A77965_PD_ALWAYS_ON
- R8A77965_PD_CA57_CPU0
- R8A77965_PD_CA57_CPU1
- R8A77965_PD_CA57_SCU
- R8A77965_PD_CR7
- R8A7796_CLK_CANFD
- R8A7796_CLK_CL
- R8A7796_CLK_CP
- R8A7796_CLK_CPEX
- R8A7796_CLK_CR
- R8A7796_CLK_CRD2
- R8A7796_CLK_CSI0
- R8A7796_CLK_HDMI
- R8A7796_CLK_LB
- R8A7796_CLK_MSO
- R8A7796_CLK_OSC
- R8A7796_CLK_R
- R8A7796_CLK_RPC
- R8A7796_CLK_RPCD2
- R8A7796_CLK_S0D1
- R8A7796_CLK_S0D12
- R8A7796_CLK_S0D2
- R8A7796_CLK_S0D3
- R8A7796_CLK_S0D4
- R8A7796_CLK_S0D6
- R8A7796_CLK_S0D8
- R8A7796_CLK_S1D1
- R8A7796_CLK_S1D2
- R8A7796_CLK_S1D4
- R8A7796_CLK_S2D1
- R8A7796_CLK_S2D2
- R8A7796_CLK_S2D4
- R8A7796_CLK_S3D1
- R8A7796_CLK_S3D2
- R8A7796_CLK_S3D4
- R8A7796_CLK_SD0
- R8A7796_CLK_SD0H
- R8A7796_CLK_SD1
- R8A7796_CLK_SD1H
- R8A7796_CLK_SD2
- R8A7796_CLK_SD2H
- R8A7796_CLK_SD3
- R8A7796_CLK_SD3H
- R8A7796_CLK_SSP1
- R8A7796_CLK_SSP2
- R8A7796_CLK_SSPRS
- R8A7796_CLK_Z
- R8A7796_CLK_Z2
- R8A7796_CLK_ZB3
- R8A7796_CLK_ZB3D2
- R8A7796_CLK_ZB3D4
- R8A7796_CLK_ZG
- R8A7796_CLK_ZR
- R8A7796_CLK_ZT
- R8A7796_CLK_ZTR
- R8A7796_CLK_ZTRD2
- R8A7796_CLK_ZX
- R8A7796_PD_3DG_A
- R8A7796_PD_3DG_B
- R8A7796_PD_A2VC0
- R8A7796_PD_A2VC1
- R8A7796_PD_A3IR
- R8A7796_PD_A3VC
- R8A7796_PD_ALWAYS_ON
- R8A7796_PD_CA53_CPU0
- R8A7796_PD_CA53_CPU1
- R8A7796_PD_CA53_CPU2
- R8A7796_PD_CA53_CPU3
- R8A7796_PD_CA53_SCU
- R8A7796_PD_CA57_CPU0
- R8A7796_PD_CA57_CPU1
- R8A7796_PD_CA57_SCU
- R8A7796_PD_CR7
- R8A77970_CLK_CANFD
- R8A77970_CLK_CL
- R8A77970_CLK_CP
- R8A77970_CLK_CPEX
- R8A77970_CLK_CR
- R8A77970_CLK_CRD2
- R8A77970_CLK_CSI0
- R8A77970_CLK_DDR
- R8A77970_CLK_FRAY
- R8A77970_CLK_LB
- R8A77970_CLK_MSO
- R8A77970_CLK_OSC
- R8A77970_CLK_R
- R8A77970_CLK_RPC
- R8A77970_CLK_RPCD2
- R8A77970_CLK_S1D1
- R8A77970_CLK_S1D2
- R8A77970_CLK_S1D4
- R8A77970_CLK_S2D1
- R8A77970_CLK_S2D2
- R8A77970_CLK_S2D4
- R8A77970_CLK_SD0
- R8A77970_CLK_SD0H
- R8A77970_CLK_Z2
- R8A77970_CLK_ZB3
- R8A77970_CLK_ZB3D2
- R8A77970_CLK_ZR
- R8A77970_CLK_ZT
- R8A77970_CLK_ZTR
- R8A77970_CLK_ZTRD2
- R8A77970_CLK_ZX
- R8A77970_PD_A2CN
- R8A77970_PD_A2DP
- R8A77970_PD_A2IR0
- R8A77970_PD_A2IR1
- R8A77970_PD_A2SC0
- R8A77970_PD_A2SC1
- R8A77970_PD_A3IR
- R8A77970_PD_ALWAYS_ON
- R8A77970_PD_CA53_CPU0
- R8A77970_PD_CA53_CPU1
- R8A77970_PD_CA53_SCU
- R8A77980_CLK_CANFD
- R8A77980_CLK_CL
- R8A77980_CLK_CP
- R8A77980_CLK_CPEX
- R8A77980_CLK_CSI0
- R8A77980_CLK_LB
- R8A77980_CLK_MSO
- R8A77980_CLK_OSC
- R8A77980_CLK_R
- R8A77980_CLK_RPC
- R8A77980_CLK_RPCD2
- R8A77980_CLK_S0D1
- R8A77980_CLK_S0D12
- R8A77980_CLK_S0D2
- R8A77980_CLK_S0D24
- R8A77980_CLK_S0D3
- R8A77980_CLK_S0D4
- R8A77980_CLK_S0D6
- R8A77980_CLK_S1D1
- R8A77980_CLK_S1D2
- R8A77980_CLK_S1D4
- R8A77980_CLK_S2D1
- R8A77980_CLK_S2D2
- R8A77980_CLK_S2D4
- R8A77980_CLK_S3D1
- R8A77980_CLK_S3D2
- R8A77980_CLK_S3D4
- R8A77980_CLK_SD0
- R8A77980_CLK_SD0H
- R8A77980_CLK_Z2
- R8A77980_CLK_ZB3
- R8A77980_CLK_ZB3D2
- R8A77980_CLK_ZB3D4
- R8A77980_CLK_ZR
- R8A77980_CLK_ZT
- R8A77980_CLK_ZTR
- R8A77980_CLK_ZTRD2
- R8A77980_CLK_ZX
- R8A77980_PD_A2CN
- R8A77980_PD_A2DP0
- R8A77980_PD_A2DP1
- R8A77980_PD_A2IR0
- R8A77980_PD_A2IR1
- R8A77980_PD_A2IR2
- R8A77980_PD_A2IR3
- R8A77980_PD_A2IR4
- R8A77980_PD_A2IR5
- R8A77980_PD_A2SC0
- R8A77980_PD_A2SC1
- R8A77980_PD_A2SC2
- R8A77980_PD_A2SC3
- R8A77980_PD_A2SC4
- R8A77980_PD_A3IR
- R8A77980_PD_A3VIP0
- R8A77980_PD_A3VIP1
- R8A77980_PD_A3VIP2
- R8A77980_PD_ALWAYS_ON
- R8A77980_PD_CA53_CPU0
- R8A77980_PD_CA53_CPU1
- R8A77980_PD_CA53_CPU2
- R8A77980_PD_CA53_CPU3
- R8A77980_PD_CA53_SCU
- R8A77980_PD_CR7
- R8A77990_CLK_CANFD
- R8A77990_CLK_CL
- R8A77990_CLK_CP
- R8A77990_CLK_CPEX
- R8A77990_CLK_CR
- R8A77990_CLK_CRD2
- R8A77990_CLK_CSI0
- R8A77990_CLK_LB
- R8A77990_CLK_LV0
- R8A77990_CLK_LV1
- R8A77990_CLK_MSO
- R8A77990_CLK_OSC
- R8A77990_CLK_R
- R8A77990_CLK_RPC
- R8A77990_CLK_RPCD2
- R8A77990_CLK_S0D1
- R8A77990_CLK_S0D12
- R8A77990_CLK_S0D24
- R8A77990_CLK_S0D3
- R8A77990_CLK_S0D6
- R8A77990_CLK_S0D6C
- R8A77990_CLK_S1D1
- R8A77990_CLK_S1D2
- R8A77990_CLK_S1D4
- R8A77990_CLK_S2D1
- R8A77990_CLK_S2D2
- R8A77990_CLK_S2D4
- R8A77990_CLK_S3D1
- R8A77990_CLK_S3D1C
- R8A77990_CLK_S3D2
- R8A77990_CLK_S3D2C
- R8A77990_CLK_S3D4
- R8A77990_CLK_S3D4C
- R8A77990_CLK_SD0
- R8A77990_CLK_SD0H
- R8A77990_CLK_SD1
- R8A77990_CLK_SD1H
- R8A77990_CLK_SD3
- R8A77990_CLK_SD3H
- R8A77990_CLK_Z2
- R8A77990_CLK_Z2D
- R8A77990_CLK_ZA2
- R8A77990_CLK_ZA8
- R8A77990_CLK_ZB3
- R8A77990_CLK_ZB3D2
- R8A77990_CLK_ZG
- R8A77990_CLK_ZR
- R8A77990_CLK_ZT
- R8A77990_CLK_ZTR
- R8A77990_CLK_ZX
- R8A77990_PD_3DG_A
- R8A77990_PD_3DG_B
- R8A77990_PD_A2VC1
- R8A77990_PD_A3VC
- R8A77990_PD_ALWAYS_ON
- R8A77990_PD_CA53_CPU0
- R8A77990_PD_CA53_CPU1
- R8A77990_PD_CA53_SCU
- R8A77990_PD_CR7
- R8A77995_CLK_CANFD
- R8A77995_CLK_CL
- R8A77995_CLK_CP
- R8A77995_CLK_CPEX
- R8A77995_CLK_CR
- R8A77995_CLK_CRD2
- R8A77995_CLK_LB
- R8A77995_CLK_LV0
- R8A77995_CLK_LV1
- R8A77995_CLK_MSO
- R8A77995_CLK_OSC
- R8A77995_CLK_R
- R8A77995_CLK_RPC
- R8A77995_CLK_RPCD2
- R8A77995_CLK_S0D1
- R8A77995_CLK_S1D1
- R8A77995_CLK_S1D2
- R8A77995_CLK_S1D4
- R8A77995_CLK_S1D4C
- R8A77995_CLK_S2D1
- R8A77995_CLK_S2D2
- R8A77995_CLK_S2D4
- R8A77995_CLK_S3D1
- R8A77995_CLK_S3D1C
- R8A77995_CLK_S3D2
- R8A77995_CLK_S3D2C
- R8A77995_CLK_S3D4
- R8A77995_CLK_S3D4C
- R8A77995_CLK_SD0
- R8A77995_CLK_SD0H
- R8A77995_CLK_Z2
- R8A77995_CLK_Z2D
- R8A77995_CLK_ZA2
- R8A77995_CLK_ZA8
- R8A77995_CLK_ZB3
- R8A77995_CLK_ZB3D2
- R8A77995_CLK_ZG
- R8A77995_CLK_ZT
- R8A77995_CLK_ZTR
- R8A77995_CLK_ZX
- R8A77995_PD_ALWAYS_ON
- R8A77995_PD_CA53_CPU0
- R8A77995_PD_CA53_SCU
- R8_OFF
- R9
- R91_AD_SLOPEREG
- R94_AD_BITCONTROL
- R9A06G032_CLK125
- R9A06G032_CLK25
- R9A06G032_CLK50
- R9A06G032_CLKOUT
- R9A06G032_CLKOUT_D10
- R9A06G032_CLKOUT_D16
- R9A06G032_CLKOUT_D160
- R9A06G032_CLKOUT_D1OR2
- R9A06G032_CLKOUT_D20
- R9A06G032_CLKOUT_D40
- R9A06G032_CLKOUT_D5
- R9A06G032_CLKOUT_D8
- R9A06G032_CLK_25_PG4
- R9A06G032_CLK_25_PG5
- R9A06G032_CLK_25_PG6
- R9A06G032_CLK_25_PG7
- R9A06G032_CLK_25_PG8
- R9A06G032_CLK_48
- R9A06G032_CLK_48_PG4
- R9A06G032_CLK_48_PG_F
- R9A06G032_CLK_A7MP
- R9A06G032_CLK_ADC
- R9A06G032_CLK_CM3
- R9A06G032_CLK_CRYPTO
- R9A06G032_CLK_DDRC
- R9A06G032_CLK_DDRPHY_PCLK
- R9A06G032_CLK_DDRPHY_PLLCLK
- R9A06G032_CLK_DDRPHY_PLLCLK_D4
- R9A06G032_CLK_ECAT100
- R9A06G032_CLK_ECAT100_D4
- R9A06G032_CLK_ECAT25
- R9A06G032_CLK_FW
- R9A06G032_CLK_HSR100
- R9A06G032_CLK_HSR100_D2
- R9A06G032_CLK_HSR50
- R9A06G032_CLK_HW_RTOS
- R9A06G032_CLK_I2C0
- R9A06G032_CLK_I2C1
- R9A06G032_CLK_MII_REF
- R9A06G032_CLK_NAND
- R9A06G032_CLK_NOUSBP2_PG6
- R9A06G032_CLK_P1_PG2
- R9A06G032_CLK_P1_PG3
- R9A06G032_CLK_P1_PG4
- R9A06G032_CLK_P4_PG3
- R9A06G032_CLK_P4_PG4
- R9A06G032_CLK_P5_PG1
- R9A06G032_CLK_P6_PG1
- R9A06G032_CLK_P6_PG2
- R9A06G032_CLK_P6_PG3
- R9A06G032_CLK_P6_PG4
- R9A06G032_CLK_PCI_USB
- R9A06G032_CLK_PLL_USB
- R9A06G032_CLK_QSPI0
- R9A06G032_CLK_QSPI1
- R9A06G032_CLK_REF_SYNC
- R9A06G032_CLK_REF_SYNC_D4
- R9A06G032_CLK_REF_SYNC_D8
- R9A06G032_CLK_RGMII_REF
- R9A06G032_CLK_RMII_REF
- R9A06G032_CLK_SDIO0
- R9A06G032_CLK_SDIO1
- R9A06G032_CLK_SERCOS100
- R9A06G032_CLK_SERCOS100_D2
- R9A06G032_CLK_SERCOS50
- R9A06G032_CLK_SLCD
- R9A06G032_CLK_SPI0
- R9A06G032_CLK_SPI1
- R9A06G032_CLK_SPI2
- R9A06G032_CLK_SPI3
- R9A06G032_CLK_SPI4
- R9A06G032_CLK_SPI5
- R9A06G032_CLK_SWITCH
- R9A06G032_CLK_UART0
- R9A06G032_CLK_UART1
- R9A06G032_CLK_UART2
- R9A06G032_CLK_UART3
- R9A06G032_CLK_UART4
- R9A06G032_CLK_UART5
- R9A06G032_CLK_UART6
- R9A06G032_CLK_UART7
- R9A06G032_CLOCK_COUNT
- R9A06G032_DIV_ADC
- R9A06G032_DIV_CA7
- R9A06G032_DIV_I2C
- R9A06G032_DIV_MOTOR
- R9A06G032_DIV_NAND
- R9A06G032_DIV_P1_PG
- R9A06G032_DIV_P2_PG
- R9A06G032_DIV_P3_PG
- R9A06G032_DIV_P4_PG
- R9A06G032_DIV_P5_PG
- R9A06G032_DIV_P6_PG
- R9A06G032_DIV_QSPI0
- R9A06G032_DIV_QSPI1
- R9A06G032_DIV_REF_SYNC
- R9A06G032_DIV_SDIO0
- R9A06G032_DIV_SDIO1
- R9A06G032_DIV_SWITCH
- R9A06G032_DIV_UART
- R9A06G032_HCLK_ADC
- R9A06G032_HCLK_CAN0
- R9A06G032_HCLK_CAN1
- R9A06G032_HCLK_CM3
- R9A06G032_HCLK_CRYPTO_EIP150
- R9A06G032_HCLK_CRYPTO_EIP93
- R9A06G032_HCLK_DDRC
- R9A06G032_HCLK_DELTASIGMA
- R9A06G032_HCLK_DMA0
- R9A06G032_HCLK_DMA1
- R9A06G032_HCLK_ECAT125
- R9A06G032_HCLK_GMAC0
- R9A06G032_HCLK_GMAC1
- R9A06G032_HCLK_GPIO0
- R9A06G032_HCLK_GPIO1
- R9A06G032_HCLK_GPIO2
- R9A06G032_HCLK_HSR
- R9A06G032_HCLK_I2C0
- R9A06G032_HCLK_I2C1
- R9A06G032_HCLK_LCD
- R9A06G032_HCLK_MSEBI_M
- R9A06G032_HCLK_MSEBI_S
- R9A06G032_HCLK_NAND
- R9A06G032_HCLK_PG19
- R9A06G032_HCLK_PG20
- R9A06G032_HCLK_PG3
- R9A06G032_HCLK_PG4
- R9A06G032_HCLK_PG_I
- R9A06G032_HCLK_PINCONFIG
- R9A06G032_HCLK_PWMPTO
- R9A06G032_HCLK_QSPI0
- R9A06G032_HCLK_QSPI1
- R9A06G032_HCLK_ROM
- R9A06G032_HCLK_RSV
- R9A06G032_HCLK_RTC
- R9A06G032_HCLK_SDIO0
- R9A06G032_HCLK_SDIO1
- R9A06G032_HCLK_SEMAP
- R9A06G032_HCLK_SERCOS
- R9A06G032_HCLK_SGPIO0
- R9A06G032_HCLK_SGPIO1
- R9A06G032_HCLK_SGPIO2
- R9A06G032_HCLK_SGPIO3
- R9A06G032_HCLK_SGPIO4
- R9A06G032_HCLK_SPI0
- R9A06G032_HCLK_SPI1
- R9A06G032_HCLK_SPI2
- R9A06G032_HCLK_SPI3
- R9A06G032_HCLK_SPI4
- R9A06G032_HCLK_SPI5
- R9A06G032_HCLK_SWITCH
- R9A06G032_HCLK_SWITCH_RG
- R9A06G032_HCLK_TIMER0
- R9A06G032_HCLK_TIMER1
- R9A06G032_HCLK_UART0
- R9A06G032_HCLK_UART1
- R9A06G032_HCLK_UART2
- R9A06G032_HCLK_UART3
- R9A06G032_HCLK_UART4
- R9A06G032_HCLK_UART5
- R9A06G032_HCLK_UART6
- R9A06G032_HCLK_UART7
- R9A06G032_HCLK_USBF
- R9A06G032_HCLK_USBH
- R9A06G032_HCLK_USBPM
- R9A06G032_MSEBIM_CLK
- R9A06G032_MSEBIS_CLK
- R9A06G032_RTOS_MDC
- R9A06G032_UART_GROUP_012
- R9A06G032_UART_GROUP_34567
- R9_16XX_GPIO18
- R9_16XX_UART2_RX
- R9_OFF
- R9_USB0_VM
- R9_USB2_VM
- RA
- RA0
- RA1
- RA2
- RA3
- RA5
- RA8_CONTROL
- RAA_SP
- RAA_WSP
- RAB0
- RAB0bh
- RAB0bl
- RAB0d
- RAB1
- RAB1bh
- RAB1bl
- RAB1d
- RAB2
- RAB2bh
- RAB2bl
- RAB2d
- RAC
- RACCFG_MASK
- RACENDATA_SHIFT
- RACENINST_SHIFT
- RACENPREF_MASK
- RACK
- RACKMETER_MAGIC_GPIO
- RACK_H
- RACK_L
- RACPREFDATA_SHIFT
- RACPREFINST_SHIFT
- RACR
- RAC_CONFIG0_REG
- RAC_CONFIG1_REG
- RAC_CPU_SHIFT
- RAC_CTS_MARK
- RAC_DATA_INST_EN_MASK
- RAC_DCD_MARK
- RAC_DSR_MARK
- RAC_DTR_MARK
- RAC_ENABLED
- RAC_PME_ENABLE
- RAC_RI_MARK
- RAC_RTS_MARK
- RAC_RXD_MARK
- RAC_SDFS_ENABLE
- RAC_SUSPENDED
- RAC_TXD_MARK
- RADACAL_WRITE
- RADAR_DETECTED_EVENT_ID
- RADAR_REPORT_REG0_AGC_TOTAL_GAIN_LSB
- RADAR_REPORT_REG0_AGC_TOTAL_GAIN_MASK
- RADAR_REPORT_REG0_PULSE_DELTA_DIFF_LSB
- RADAR_REPORT_REG0_PULSE_DELTA_DIFF_MASK
- RADAR_REPORT_REG0_PULSE_DELTA_PEAK_LSB
- RADAR_REPORT_REG0_PULSE_DELTA_PEAK_MASK
- RADAR_REPORT_REG0_PULSE_IS_CHIRP_LSB
- RADAR_REPORT_REG0_PULSE_IS_CHIRP_MASK
- RADAR_REPORT_REG0_PULSE_IS_MAX_WIDTH_LSB
- RADAR_REPORT_REG0_PULSE_IS_MAX_WIDTH_MASK
- RADAR_REPORT_REG0_PULSE_SIDX_LSB
- RADAR_REPORT_REG0_PULSE_SIDX_MASK
- RADAR_REPORT_REG1_PULSE_AGC_MB_GAIN_LSB
- RADAR_REPORT_REG1_PULSE_AGC_MB_GAIN_MASK
- RADAR_REPORT_REG1_PULSE_DUR_LSB
- RADAR_REPORT_REG1_PULSE_DUR_MASK
- RADAR_REPORT_REG1_PULSE_SRCH_FFT_VALID_LSB
- RADAR_REPORT_REG1_PULSE_SRCH_FFT_VALID_MASK
- RADAR_REPORT_REG1_PULSE_SUBCHAN_MASK_LSB
- RADAR_REPORT_REG1_PULSE_SUBCHAN_MASK_MASK
- RADAR_REPORT_REG1_PULSE_TSF_OFFSET_LSB
- RADAR_REPORT_REG1_PULSE_TSF_OFFSET_MASK
- RADAR_SPEC
- RADAR_TYPE_BIN5
- RADAR_TYPE_CHIRP
- RADAR_TYPE_ETSI_1
- RADAR_TYPE_ETSI_2
- RADAR_TYPE_ETSI_3
- RADAR_TYPE_FRA
- RADAR_TYPE_ITU_E
- RADAR_TYPE_ITU_K
- RADAR_TYPE_NONE
- RADAR_TYPE_REGULAR
- RADAR_TYPE_STG2
- RADAR_TYPE_STG3
- RADAR_TYPE_UNCLASSIFIED
- RADC_BUF_CLK
- RADC_PWR_ON
- RADC_VOL
- RADDR
- RADDR_1
- RADDR_2
- RADEONFB_CONN_LIMIT
- RADEON_ABORT_HW_DVI_I2C
- RADEON_ACC_MODE_CHANGE
- RADEON_ACC_REQ_CRT1
- RADEON_ACC_REQ_CRT2
- RADEON_ACC_REQ_DFP1
- RADEON_ACC_REQ_DFP2
- RADEON_ACC_REQ_LCD1
- RADEON_ACC_REQ_TV1
- RADEON_ACC_REQ_TV2
- RADEON_ACPI_H
- RADEON_ACTIVE_HILO_LAT_MASK
- RADEON_ACTIVE_HILO_LAT_SHIFT
- RADEON_ADAPTER_ID
- RADEON_AGP_1X_MODE
- RADEON_AGP_2X_MODE
- RADEON_AGP_4X_MODE
- RADEON_AGP_APER_SIZE_128MB
- RADEON_AGP_APER_SIZE_16MB
- RADEON_AGP_APER_SIZE_256MB
- RADEON_AGP_APER_SIZE_32MB
- RADEON_AGP_APER_SIZE_4MB
- RADEON_AGP_APER_SIZE_64MB
- RADEON_AGP_APER_SIZE_8MB
- RADEON_AGP_APER_SIZE_MASK
- RADEON_AGP_BASE
- RADEON_AGP_BASE_2
- RADEON_AGP_CNTL
- RADEON_AGP_COMMAND
- RADEON_AGP_COMMAND_PCI_CONFIG
- RADEON_AGP_ENABLE
- RADEON_AGP_FW_MODE
- RADEON_AGP_MODE_MASK
- RADEON_AGP_PLL_CNTL
- RADEON_AGP_STATUS
- RADEON_AGPv3_4X_MODE
- RADEON_AGPv3_8X_MODE
- RADEON_AGPv3_MODE
- RADEON_AIC_CNTL
- RADEON_AIC_HI_ADDR
- RADEON_AIC_LO_ADDR
- RADEON_AIC_PT_BASE
- RADEON_ALPHA_ARG_A_CURRENT_ALPHA
- RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA
- RADEON_ALPHA_ARG_A_MASK
- RADEON_ALPHA_ARG_A_SHIFT
- RADEON_ALPHA_ARG_A_SPECULAR_ALPHA
- RADEON_ALPHA_ARG_A_T0_ALPHA
- RADEON_ALPHA_ARG_A_T1_ALPHA
- RADEON_ALPHA_ARG_A_T2_ALPHA
- RADEON_ALPHA_ARG_A_T3_ALPHA
- RADEON_ALPHA_ARG_A_TFACTOR_ALPHA
- RADEON_ALPHA_ARG_A_ZERO
- RADEON_ALPHA_ARG_B_CURRENT_ALPHA
- RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA
- RADEON_ALPHA_ARG_B_MASK
- RADEON_ALPHA_ARG_B_SHIFT
- RADEON_ALPHA_ARG_B_SPECULAR_ALPHA
- RADEON_ALPHA_ARG_B_T0_ALPHA
- RADEON_ALPHA_ARG_B_T1_ALPHA
- RADEON_ALPHA_ARG_B_T2_ALPHA
- RADEON_ALPHA_ARG_B_T3_ALPHA
- RADEON_ALPHA_ARG_B_TFACTOR_ALPHA
- RADEON_ALPHA_ARG_B_ZERO
- RADEON_ALPHA_ARG_C_CURRENT_ALPHA
- RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA
- RADEON_ALPHA_ARG_C_MASK
- RADEON_ALPHA_ARG_C_SHIFT
- RADEON_ALPHA_ARG_C_SPECULAR_ALPHA
- RADEON_ALPHA_ARG_C_T0_ALPHA
- RADEON_ALPHA_ARG_C_T1_ALPHA
- RADEON_ALPHA_ARG_C_T2_ALPHA
- RADEON_ALPHA_ARG_C_T3_ALPHA
- RADEON_ALPHA_ARG_C_TFACTOR_ALPHA
- RADEON_ALPHA_ARG_C_ZERO
- RADEON_ALPHA_ARG_MASK
- RADEON_ALPHA_BLEND_ENABLE
- RADEON_ALPHA_SHADE_FLAT
- RADEON_ALPHA_SHADE_GOURAUD
- RADEON_ALPHA_SHADE_MASK
- RADEON_ALPHA_SHADE_SOLID
- RADEON_ALPHA_TEST_ENABLE
- RADEON_ALPHA_TEST_EQUAL
- RADEON_ALPHA_TEST_FAIL
- RADEON_ALPHA_TEST_GEQUAL
- RADEON_ALPHA_TEST_GREATER
- RADEON_ALPHA_TEST_LEQUAL
- RADEON_ALPHA_TEST_LESS
- RADEON_ALPHA_TEST_NEQUAL
- RADEON_ALPHA_TEST_OP_MASK
- RADEON_ALPHA_TEST_PASS
- RADEON_ALT_PHASE_EN
- RADEON_AMBIENT_SOURCE_SHIFT
- RADEON_ANTI_ALIAS_LINE
- RADEON_ANTI_ALIAS_LINE_POLY
- RADEON_ANTI_ALIAS_NONE
- RADEON_ANTI_ALIAS_POLY
- RADEON_ASIC_RESET_DATA
- RADEON_ATTRDR
- RADEON_ATTRDW
- RADEON_ATTRX
- RADEON_AUDIO_AUTO
- RADEON_AUDIO_DISABLE
- RADEON_AUDIO_ENABLE
- RADEON_AUD_ASYNC_RST
- RADEON_AUTO_PWRUP_EN
- RADEON_AUX1_SC_BOTTOM
- RADEON_AUX1_SC_EN
- RADEON_AUX1_SC_LEFT
- RADEON_AUX1_SC_MODE_NAND
- RADEON_AUX1_SC_MODE_OR
- RADEON_AUX1_SC_RIGHT
- RADEON_AUX1_SC_TOP
- RADEON_AUX2_SC_BOTTOM
- RADEON_AUX2_SC_EN
- RADEON_AUX2_SC_LEFT
- RADEON_AUX2_SC_MODE_NAND
- RADEON_AUX2_SC_MODE_OR
- RADEON_AUX2_SC_RIGHT
- RADEON_AUX2_SC_TOP
- RADEON_AUX3_SC_BOTTOM
- RADEON_AUX3_SC_EN
- RADEON_AUX3_SC_LEFT
- RADEON_AUX3_SC_MODE_NAND
- RADEON_AUX3_SC_MODE_OR
- RADEON_AUX3_SC_RIGHT
- RADEON_AUX3_SC_TOP
- RADEON_AUX_SC_CNTL
- RADEON_AUX_WINDOW_HORZ_CNTL
- RADEON_AUX_WINDOW_VERT_CNTL
- RADEON_B3MEM_RESET_MASK
- RADEON_BACK
- RADEON_BADVTX_CULL_DISABLE
- RADEON_BASE_CODE
- RADEON_BENCHMARK_COMMON_MODES_N
- RADEON_BENCHMARK_COPY_BLIT
- RADEON_BENCHMARK_COPY_DMA
- RADEON_BENCHMARK_ITERATIONS
- RADEON_BFACE_CULL
- RADEON_BFACE_SOLID
- RADEON_BIOS_0_SCRATCH
- RADEON_BIOS_1_SCRATCH
- RADEON_BIOS_2_SCRATCH
- RADEON_BIOS_3_SCRATCH
- RADEON_BIOS_4_SCRATCH
- RADEON_BIOS_5_SCRATCH
- RADEON_BIOS_6_SCRATCH
- RADEON_BIOS_7_SCRATCH
- RADEON_BIOS_NUM_SCRATCH
- RADEON_BIOS_ROM
- RADEON_BIST
- RADEON_BLANK_LEVEL_SHIFT
- RADEON_BLEND_CTL_ADD
- RADEON_BLEND_CTL_ADDSIGNED
- RADEON_BLEND_CTL_BLEND
- RADEON_BLEND_CTL_DOT3
- RADEON_BLEND_CTL_MASK
- RADEON_BLEND_CTL_SUBTRACT
- RADEON_BLEND_OP_COUNT_MASK
- RADEON_BLEND_OP_COUNT_SHIFT
- RADEON_BLU_MX_FORCE_DAC_DATA
- RADEON_BORDER_MODE_D3D
- RADEON_BORDER_MODE_OGL
- RADEON_BRES_CNTL_SHIFT
- RADEON_BRUSH_DATA0
- RADEON_BRUSH_DATA1
- RADEON_BRUSH_DATA10
- RADEON_BRUSH_DATA11
- RADEON_BRUSH_DATA12
- RADEON_BRUSH_DATA13
- RADEON_BRUSH_DATA14
- RADEON_BRUSH_DATA15
- RADEON_BRUSH_DATA16
- RADEON_BRUSH_DATA17
- RADEON_BRUSH_DATA18
- RADEON_BRUSH_DATA19
- RADEON_BRUSH_DATA2
- RADEON_BRUSH_DATA20
- RADEON_BRUSH_DATA21
- RADEON_BRUSH_DATA22
- RADEON_BRUSH_DATA23
- RADEON_BRUSH_DATA24
- RADEON_BRUSH_DATA25
- RADEON_BRUSH_DATA26
- RADEON_BRUSH_DATA27
- RADEON_BRUSH_DATA28
- RADEON_BRUSH_DATA29
- RADEON_BRUSH_DATA3
- RADEON_BRUSH_DATA30
- RADEON_BRUSH_DATA31
- RADEON_BRUSH_DATA32
- RADEON_BRUSH_DATA33
- RADEON_BRUSH_DATA34
- RADEON_BRUSH_DATA35
- RADEON_BRUSH_DATA36
- RADEON_BRUSH_DATA37
- RADEON_BRUSH_DATA38
- RADEON_BRUSH_DATA39
- RADEON_BRUSH_DATA4
- RADEON_BRUSH_DATA40
- RADEON_BRUSH_DATA41
- RADEON_BRUSH_DATA42
- RADEON_BRUSH_DATA43
- RADEON_BRUSH_DATA44
- RADEON_BRUSH_DATA45
- RADEON_BRUSH_DATA46
- RADEON_BRUSH_DATA47
- RADEON_BRUSH_DATA48
- RADEON_BRUSH_DATA49
- RADEON_BRUSH_DATA5
- RADEON_BRUSH_DATA50
- RADEON_BRUSH_DATA51
- RADEON_BRUSH_DATA52
- RADEON_BRUSH_DATA53
- RADEON_BRUSH_DATA54
- RADEON_BRUSH_DATA55
- RADEON_BRUSH_DATA56
- RADEON_BRUSH_DATA57
- RADEON_BRUSH_DATA58
- RADEON_BRUSH_DATA59
- RADEON_BRUSH_DATA6
- RADEON_BRUSH_DATA60
- RADEON_BRUSH_DATA61
- RADEON_BRUSH_DATA62
- RADEON_BRUSH_DATA63
- RADEON_BRUSH_DATA7
- RADEON_BRUSH_DATA8
- RADEON_BRUSH_DATA9
- RADEON_BRUSH_SCALE
- RADEON_BRUSH_Y_X
- RADEON_BUFFER_SIZE
- RADEON_BUF_SWAP_32BIT
- RADEON_BUMPED_MAP_T0
- RADEON_BUMPED_MAP_T1
- RADEON_BUMPED_MAP_T2
- RADEON_BUMP_MAP_ENABLE
- RADEON_BUS_BIOS_DIS_ROM
- RADEON_BUS_CNTL
- RADEON_BUS_CNTL1
- RADEON_BUS_MASTER_DIS
- RADEON_BUS_MSTR_DISCONNECT_EN
- RADEON_BUS_RD_ABORT_EN
- RADEON_BUS_RD_DISCARD_EN
- RADEON_BUS_READ_BURST
- RADEON_BUS_WAIT_ON_LOCK_EN
- RADEON_BUS_WRT_BURST
- RADEON_CACHE_CNTL
- RADEON_CACHE_LINE
- RADEON_CAP0_ANC2_OFFSET
- RADEON_CAP0_ANC3_OFFSET
- RADEON_CAP0_ANC_EVEN_OFFSET
- RADEON_CAP0_ANC_H_WINDOW
- RADEON_CAP0_ANC_ODD_OFFSET
- RADEON_CAP0_BUF0_EVEN_OFFSET
- RADEON_CAP0_BUF0_OFFSET
- RADEON_CAP0_BUF1_EVEN_OFFSET
- RADEON_CAP0_BUF1_OFFSET
- RADEON_CAP0_BUF_PITCH
- RADEON_CAP0_BUF_STATUS
- RADEON_CAP0_CONFIG
- RADEON_CAP0_CONFIG_ANC_DECODE_EN
- RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE
- RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE
- RADEON_CAP0_CONFIG_BUF_TYPE_ALT
- RADEON_CAP0_CONFIG_BUF_TYPE_FRAME
- RADEON_CAP0_CONFIG_CONTINUOS
- RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE
- RADEON_CAP0_CONFIG_FAKE_FIELD_EN
- RADEON_CAP0_CONFIG_FORMAT_BROOKTREE
- RADEON_CAP0_CONFIG_FORMAT_CCIR656
- RADEON_CAP0_CONFIG_FORMAT_TRANSPORT
- RADEON_CAP0_CONFIG_FORMAT_VIP
- RADEON_CAP0_CONFIG_FORMAT_ZV
- RADEON_CAP0_CONFIG_HORZ_DECIMATOR
- RADEON_CAP0_CONFIG_HORZ_DIVIDE_2
- RADEON_CAP0_CONFIG_HORZ_DIVIDE_4
- RADEON_CAP0_CONFIG_MIRROR_EN
- RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE
- RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN
- RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME
- RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN
- RADEON_CAP0_CONFIG_START_BUF_GET
- RADEON_CAP0_CONFIG_START_BUF_SET
- RADEON_CAP0_CONFIG_START_FIELD_EVEN
- RADEON_CAP0_CONFIG_VBI_DIVIDE_2
- RADEON_CAP0_CONFIG_VBI_DIVIDE_4
- RADEON_CAP0_CONFIG_VBI_EN
- RADEON_CAP0_CONFIG_VERT_DIVIDE_2
- RADEON_CAP0_CONFIG_VERT_DIVIDE_4
- RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422
- RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422
- RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV
- RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN
- RADEON_CAP0_DEBUG
- RADEON_CAP0_H_WINDOW
- RADEON_CAP0_ONESHOT_BUF_OFFSET
- RADEON_CAP0_PORT_MODE_CNTL
- RADEON_CAP0_TRIG_CNTL
- RADEON_CAP0_VBI0_OFFSET
- RADEON_CAP0_VBI1_OFFSET
- RADEON_CAP0_VBI2_OFFSET
- RADEON_CAP0_VBI3_OFFSET
- RADEON_CAP0_VBI_H_WINDOW
- RADEON_CAP0_VBI_V_WINDOW
- RADEON_CAP0_VIDEO_SYNC_TEST
- RADEON_CAP0_V_WINDOW
- RADEON_CAP1_ANC_EVEN_OFFSET
- RADEON_CAP1_ANC_H_WINDOW
- RADEON_CAP1_ANC_ODD_OFFSET
- RADEON_CAP1_BUF0_EVEN_OFFSET
- RADEON_CAP1_BUF0_OFFSET
- RADEON_CAP1_BUF1_EVEN_OFFSET
- RADEON_CAP1_BUF1_OFFSET
- RADEON_CAP1_BUF_PITCH
- RADEON_CAP1_BUF_STATUS
- RADEON_CAP1_CONFIG
- RADEON_CAP1_DEBUG
- RADEON_CAP1_DWNSC_XRATIO
- RADEON_CAP1_H_WINDOW
- RADEON_CAP1_ONESHOT_BUF_OFFSET
- RADEON_CAP1_PORT_MODE_CNTL
- RADEON_CAP1_TRIG_CNTL
- RADEON_CAP1_VBI_EVEN_OFFSET
- RADEON_CAP1_VBI_H_WINDOW
- RADEON_CAP1_VBI_ODD_OFFSET
- RADEON_CAP1_VBI_V_WINDOW
- RADEON_CAP1_VIDEO_SYNC_TEST
- RADEON_CAP1_V_WINDOW
- RADEON_CAP1_XSHARPNESS
- RADEON_CAPABILITIES_ID
- RADEON_CAPABILITIES_PTR
- RADEON_CAPABILITIES_PTR_PCI_CONFIG
- RADEON_CAP_ID_AGP
- RADEON_CAP_ID_EXP
- RADEON_CAP_ID_NULL
- RADEON_CAP_LIST
- RADEON_CAP_PTR_MASK
- RADEON_CARD_AGP
- RADEON_CARD_PCI
- RADEON_CARD_PCIE
- RADEON_CFG_ATI_REV_A11
- RADEON_CFG_ATI_REV_A12
- RADEON_CFG_ATI_REV_A13
- RADEON_CFG_ATI_REV_ID_MASK
- RADEON_CFG_VGA_IO_DIS
- RADEON_CFG_VGA_RAM_EN
- RADEON_CG_BLOCK_BIF
- RADEON_CG_BLOCK_GFX
- RADEON_CG_BLOCK_HDP
- RADEON_CG_BLOCK_MC
- RADEON_CG_BLOCK_SDMA
- RADEON_CG_BLOCK_UVD
- RADEON_CG_BLOCK_VCE
- RADEON_CG_NO1_DEBUG_0
- RADEON_CG_NO1_DEBUG_MASK
- RADEON_CG_SUPPORT_BIF_LS
- RADEON_CG_SUPPORT_GFX_CGCG
- RADEON_CG_SUPPORT_GFX_CGLS
- RADEON_CG_SUPPORT_GFX_CGTS
- RADEON_CG_SUPPORT_GFX_CGTS_LS
- RADEON_CG_SUPPORT_GFX_CP_LS
- RADEON_CG_SUPPORT_GFX_MGCG
- RADEON_CG_SUPPORT_GFX_MGLS
- RADEON_CG_SUPPORT_GFX_RLC_LS
- RADEON_CG_SUPPORT_HDP_LS
- RADEON_CG_SUPPORT_HDP_MGCG
- RADEON_CG_SUPPORT_MC_LS
- RADEON_CG_SUPPORT_MC_MGCG
- RADEON_CG_SUPPORT_SDMA_LS
- RADEON_CG_SUPPORT_SDMA_MGCG
- RADEON_CG_SUPPORT_UVD_MGCG
- RADEON_CG_SUPPORT_VCE_MGCG
- RADEON_CHROMA_FUNC_EQUAL
- RADEON_CHROMA_FUNC_FAIL
- RADEON_CHROMA_FUNC_NEQUAL
- RADEON_CHROMA_FUNC_PASS
- RADEON_CHROMA_KEY_NEAREST
- RADEON_CHROMA_KEY_ZERO
- RADEON_CHUNK_ID_CONST_IB
- RADEON_CHUNK_ID_FLAGS
- RADEON_CHUNK_ID_IB
- RADEON_CHUNK_ID_RELOCS
- RADEON_CLAMP_S_CLAMP_BORDER
- RADEON_CLAMP_S_CLAMP_GL
- RADEON_CLAMP_S_CLAMP_LAST
- RADEON_CLAMP_S_MASK
- RADEON_CLAMP_S_MIRROR
- RADEON_CLAMP_S_MIRROR_CLAMP_BORDER
- RADEON_CLAMP_S_MIRROR_CLAMP_GL
- RADEON_CLAMP_S_MIRROR_CLAMP_LAST
- RADEON_CLAMP_S_WRAP
- RADEON_CLAMP_TX
- RADEON_CLAMP_T_CLAMP_BORDER
- RADEON_CLAMP_T_CLAMP_GL
- RADEON_CLAMP_T_CLAMP_LAST
- RADEON_CLAMP_T_MASK
- RADEON_CLAMP_T_MIRROR
- RADEON_CLAMP_T_MIRROR_CLAMP_BORDER
- RADEON_CLAMP_T_MIRROR_CLAMP_GL
- RADEON_CLAMP_T_MIRROR_CLAMP_LAST
- RADEON_CLAMP_T_WRAP
- RADEON_CLEAR_FASTZ
- RADEON_CLK_PIN_CNTL
- RADEON_CLK_PWRMGT_CNTL
- RADEON_CLOCK_CNTL_DATA
- RADEON_CLOCK_CNTL_INDEX
- RADEON_CLRCMP_FLIP_ENABLE
- RADEON_CLR_CMP_CLR_3D
- RADEON_CLR_CMP_CLR_DST
- RADEON_CLR_CMP_CLR_SRC
- RADEON_CLR_CMP_CNTL
- RADEON_CLR_CMP_MASK
- RADEON_CLR_CMP_MASK_3D
- RADEON_CLR_CMP_MSK
- RADEON_CLR_CMP_SRC_SOURCE
- RADEON_CMDFIFO_ENTRIES_MASK
- RADEON_CMDFIFO_ENTRIES_SHIFT
- RADEON_CMD_DMA_DISCARD
- RADEON_CMD_PACKET
- RADEON_CMD_PACKET3
- RADEON_CMD_PACKET3_CLIP
- RADEON_CMD_SCALARS
- RADEON_CMD_SCALARS2
- RADEON_CMD_VECLINEAR
- RADEON_CMD_VECTORS
- RADEON_CMD_WAIT
- RADEON_CMP_BLU_EN
- RADEON_CMP_MIX_AND
- RADEON_CMP_MIX_MASK
- RADEON_CMP_MIX_OR
- RADEON_COLOROFFSET_MASK
- RADEON_COLORPITCH_MASK
- RADEON_COLOR_ARG_A_CURRENT_ALPHA
- RADEON_COLOR_ARG_A_CURRENT_COLOR
- RADEON_COLOR_ARG_A_DIFFUSE_ALPHA
- RADEON_COLOR_ARG_A_DIFFUSE_COLOR
- RADEON_COLOR_ARG_A_MASK
- RADEON_COLOR_ARG_A_SHIFT
- RADEON_COLOR_ARG_A_SPECULAR_ALPHA
- RADEON_COLOR_ARG_A_SPECULAR_COLOR
- RADEON_COLOR_ARG_A_T0_ALPHA
- RADEON_COLOR_ARG_A_T0_COLOR
- RADEON_COLOR_ARG_A_T1_ALPHA
- RADEON_COLOR_ARG_A_T1_COLOR
- RADEON_COLOR_ARG_A_T2_ALPHA
- RADEON_COLOR_ARG_A_T2_COLOR
- RADEON_COLOR_ARG_A_T3_ALPHA
- RADEON_COLOR_ARG_A_T3_COLOR
- RADEON_COLOR_ARG_A_TFACTOR_ALPHA
- RADEON_COLOR_ARG_A_TFACTOR_COLOR
- RADEON_COLOR_ARG_A_ZERO
- RADEON_COLOR_ARG_B_CURRENT_ALPHA
- RADEON_COLOR_ARG_B_CURRENT_COLOR
- RADEON_COLOR_ARG_B_DIFFUSE_ALPHA
- RADEON_COLOR_ARG_B_DIFFUSE_COLOR
- RADEON_COLOR_ARG_B_MASK
- RADEON_COLOR_ARG_B_SHIFT
- RADEON_COLOR_ARG_B_SPECULAR_ALPHA
- RADEON_COLOR_ARG_B_SPECULAR_COLOR
- RADEON_COLOR_ARG_B_T0_ALPHA
- RADEON_COLOR_ARG_B_T0_COLOR
- RADEON_COLOR_ARG_B_T1_ALPHA
- RADEON_COLOR_ARG_B_T1_COLOR
- RADEON_COLOR_ARG_B_T2_ALPHA
- RADEON_COLOR_ARG_B_T2_COLOR
- RADEON_COLOR_ARG_B_T3_ALPHA
- RADEON_COLOR_ARG_B_T3_COLOR
- RADEON_COLOR_ARG_B_TFACTOR_ALPHA
- RADEON_COLOR_ARG_B_TFACTOR_COLOR
- RADEON_COLOR_ARG_B_ZERO
- RADEON_COLOR_ARG_C_CURRENT_ALPHA
- RADEON_COLOR_ARG_C_CURRENT_COLOR
- RADEON_COLOR_ARG_C_DIFFUSE_ALPHA
- RADEON_COLOR_ARG_C_DIFFUSE_COLOR
- RADEON_COLOR_ARG_C_MASK
- RADEON_COLOR_ARG_C_SHIFT
- RADEON_COLOR_ARG_C_SPECULAR_ALPHA
- RADEON_COLOR_ARG_C_SPECULAR_COLOR
- RADEON_COLOR_ARG_C_T0_ALPHA
- RADEON_COLOR_ARG_C_T0_COLOR
- RADEON_COLOR_ARG_C_T1_ALPHA
- RADEON_COLOR_ARG_C_T1_COLOR
- RADEON_COLOR_ARG_C_T2_ALPHA
- RADEON_COLOR_ARG_C_T2_COLOR
- RADEON_COLOR_ARG_C_T3_ALPHA
- RADEON_COLOR_ARG_C_T3_COLOR
- RADEON_COLOR_ARG_C_TFACTOR_ALPHA
- RADEON_COLOR_ARG_C_TFACTOR_COLOR
- RADEON_COLOR_ARG_C_ZERO
- RADEON_COLOR_ARG_MASK
- RADEON_COLOR_ENDIAN_DWORD_SWAP
- RADEON_COLOR_ENDIAN_NO_SWAP
- RADEON_COLOR_ENDIAN_WORD_SWAP
- RADEON_COLOR_FORMAT_ARGB1555
- RADEON_COLOR_FORMAT_ARGB4444
- RADEON_COLOR_FORMAT_ARGB8888
- RADEON_COLOR_FORMAT_RGB332
- RADEON_COLOR_FORMAT_RGB565
- RADEON_COLOR_FORMAT_RGB8
- RADEON_COLOR_FORMAT_Y8
- RADEON_COLOR_FORMAT_YUV422_VYUY
- RADEON_COLOR_FORMAT_YUV422_YVYU
- RADEON_COLOR_FORMAT_aYUV444
- RADEON_COLOR_MICROTILE_ENABLE
- RADEON_COLOR_TILE_ENABLE
- RADEON_COMB_FCN_ADD_CLAMP
- RADEON_COMB_FCN_ADD_NOCLAMP
- RADEON_COMB_FCN_MASK
- RADEON_COMB_FCN_SUB_CLAMP
- RADEON_COMB_FCN_SUB_NOCLAMP
- RADEON_COMMAND
- RADEON_COMPOSITE_SHADOW_ID
- RADEON_COMP_ARG_A
- RADEON_COMP_ARG_A_SHIFT
- RADEON_COMP_ARG_B
- RADEON_COMP_ARG_B_SHIFT
- RADEON_COMP_ARG_C
- RADEON_COMP_ARG_C_SHIFT
- RADEON_COMP_ARG_SHIFT
- RADEON_CONFIG_APER_0_BASE
- RADEON_CONFIG_APER_1_BASE
- RADEON_CONFIG_APER_SIZE
- RADEON_CONFIG_BONDS
- RADEON_CONFIG_CNTL
- RADEON_CONFIG_MEMSIZE
- RADEON_CONFIG_MEMSIZE_EMBEDDED
- RADEON_CONFIG_REG_1_BASE
- RADEON_CONFIG_REG_APER_SIZE
- RADEON_CONFIG_XSTRAP
- RADEON_CONSTANT_COLOR_C
- RADEON_CONSTANT_COLOR_MASK
- RADEON_CONSTANT_COLOR_ONE
- RADEON_CONSTANT_COLOR_ZERO
- RADEON_CP_CSQ2_STAT
- RADEON_CP_CSQ_ADDR
- RADEON_CP_CSQ_APER_INDIRECT
- RADEON_CP_CSQ_APER_PRIMARY
- RADEON_CP_CSQ_CNTL
- RADEON_CP_CSQ_DATA
- RADEON_CP_CSQ_MODE
- RADEON_CP_CSQ_STAT
- RADEON_CP_IB_BASE
- RADEON_CP_IB_BUFSZ
- RADEON_CP_MAX_DYN_STOP_LAT
- RADEON_CP_ME_RAM_ADDR
- RADEON_CP_ME_RAM_DATAH
- RADEON_CP_ME_RAM_DATAL
- RADEON_CP_ME_RAM_RADDR
- RADEON_CP_PACKET0
- RADEON_CP_PACKET0_GET_ONE_REG_WR
- RADEON_CP_PACKET0_ONE_REG_WR
- RADEON_CP_PACKET0_REG_MASK
- RADEON_CP_PACKET1
- RADEON_CP_PACKET1_REG0_MASK
- RADEON_CP_PACKET1_REG1_MASK
- RADEON_CP_PACKET2
- RADEON_CP_PACKET3
- RADEON_CP_PACKET3_3D_DRAW_IMMD
- RADEON_CP_PACKET3_3D_DRAW_INDX
- RADEON_CP_PACKET3_3D_DRAW_VBUF
- RADEON_CP_PACKET3_3D_LOAD_VBPNTR
- RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM
- RADEON_CP_PACKET3_CNTL_BITBLT
- RADEON_CP_PACKET3_CNTL_BITBLT_MULTI
- RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT
- RADEON_CP_PACKET3_CNTL_PAINT
- RADEON_CP_PACKET3_CNTL_PAINT_MULTI
- RADEON_CP_PACKET3_CNTL_POLYLINE
- RADEON_CP_PACKET3_CNTL_POLYSCANLINES
- RADEON_CP_PACKET3_CNTL_SMALLTEXT
- RADEON_CP_PACKET3_CNTL_TRANS_BITBLT
- RADEON_CP_PACKET3_GET_OPCODE
- RADEON_CP_PACKET3_LOAD_MICROCODE
- RADEON_CP_PACKET3_LOAD_PALETTE
- RADEON_CP_PACKET3_NEXT_CHAR
- RADEON_CP_PACKET3_NOP
- RADEON_CP_PACKET3_PLY_NEXTSCAN
- RADEON_CP_PACKET3_SET_SCISSORS
- RADEON_CP_PACKET3_WAIT_FOR_IDLE
- RADEON_CP_PACKET_COUNT_MASK
- RADEON_CP_PACKET_GET_COUNT
- RADEON_CP_PACKET_GET_TYPE
- RADEON_CP_PACKET_MASK
- RADEON_CP_PACKET_MAX_DWORDS
- RADEON_CP_RB_BASE
- RADEON_CP_RB_CNTL
- RADEON_CP_RB_RPTR
- RADEON_CP_RB_RPTR_ADDR
- RADEON_CP_RB_RPTR_WR
- RADEON_CP_RB_WPTR
- RADEON_CP_RB_WPTR_DELAY
- RADEON_CP_STAT
- RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA
- RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA
- RADEON_CP_VC_CNTL_MAOS_ENABLE
- RADEON_CP_VC_CNTL_NUM_SHIFT
- RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST
- RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST
- RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
- RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP
- RADEON_CP_VC_CNTL_PRIM_TYPE_NONE
- RADEON_CP_VC_CNTL_PRIM_TYPE_POINT
- RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST
- RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
- RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
- RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP
- RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2
- RADEON_CP_VC_CNTL_PRIM_WALK_IND
- RADEON_CP_VC_CNTL_PRIM_WALK_LIST
- RADEON_CP_VC_CNTL_PRIM_WALK_RING
- RADEON_CP_VC_CNTL_TCL_DISABLE
- RADEON_CP_VC_CNTL_TCL_ENABLE
- RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE
- RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE
- RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK
- RADEON_CP_VC_FRMT_FPALPHA
- RADEON_CP_VC_FRMT_FPCOLOR
- RADEON_CP_VC_FRMT_FPFOG
- RADEON_CP_VC_FRMT_FPSPEC
- RADEON_CP_VC_FRMT_N0
- RADEON_CP_VC_FRMT_N1
- RADEON_CP_VC_FRMT_PKCOLOR
- RADEON_CP_VC_FRMT_PKSPEC
- RADEON_CP_VC_FRMT_Q0
- RADEON_CP_VC_FRMT_Q1
- RADEON_CP_VC_FRMT_Q2
- RADEON_CP_VC_FRMT_Q3
- RADEON_CP_VC_FRMT_ST0
- RADEON_CP_VC_FRMT_ST1
- RADEON_CP_VC_FRMT_ST2
- RADEON_CP_VC_FRMT_ST3
- RADEON_CP_VC_FRMT_W0
- RADEON_CP_VC_FRMT_W1
- RADEON_CP_VC_FRMT_XY
- RADEON_CP_VC_FRMT_XY1
- RADEON_CP_VC_FRMT_Z
- RADEON_CP_VC_FRMT_Z1
- RADEON_CRC_CMDFIFO_ADDR
- RADEON_CRC_CMDFIFO_DOUT
- RADEON_CRT1_ATTACHED_COLOR
- RADEON_CRT1_ATTACHED_MASK
- RADEON_CRT1_ATTACHED_MONO
- RADEON_CRT1_CRTC_MASK
- RADEON_CRT1_CRTC_SHIFT
- RADEON_CRT1_ON
- RADEON_CRT2_ATTACHED_COLOR
- RADEON_CRT2_ATTACHED_MASK
- RADEON_CRT2_ATTACHED_MONO
- RADEON_CRT2_CRTC_MASK
- RADEON_CRT2_CRTC_SHIFT
- RADEON_CRT2_DISP1_SEL
- RADEON_CRT2_ON
- RADEON_CRTC2_CRNT_FRAME
- RADEON_CRTC2_CRT2_ON
- RADEON_CRTC2_CSYNC_EN
- RADEON_CRTC2_CUR_EN
- RADEON_CRTC2_CUR_MODE_MASK
- RADEON_CRTC2_DBL_SCAN_EN
- RADEON_CRTC2_DISP_DIS
- RADEON_CRTC2_DISP_REQ_EN_B
- RADEON_CRTC2_EN
- RADEON_CRTC2_GEN_CNTL
- RADEON_CRTC2_GUI_TRIG_VLINE
- RADEON_CRTC2_HSYNC_DIS
- RADEON_CRTC2_HSYNC_TRISTAT
- RADEON_CRTC2_H_DISP
- RADEON_CRTC2_H_DISP_SHIFT
- RADEON_CRTC2_H_SYNC_POL
- RADEON_CRTC2_H_SYNC_STRT_CHAR
- RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT
- RADEON_CRTC2_H_SYNC_STRT_PIX
- RADEON_CRTC2_H_SYNC_STRT_WID
- RADEON_CRTC2_H_SYNC_WID
- RADEON_CRTC2_H_SYNC_WID_SHIFT
- RADEON_CRTC2_H_TOTAL
- RADEON_CRTC2_H_TOTAL_DISP
- RADEON_CRTC2_H_TOTAL_SHIFT
- RADEON_CRTC2_ICON_EN
- RADEON_CRTC2_INTERLACE_EN
- RADEON_CRTC2_OFFSET
- RADEON_CRTC2_OFFSET_CNTL
- RADEON_CRTC2_OFFSET_FLIP_CNTL
- RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET
- RADEON_CRTC2_OFFSET__OFFSET_LOCK
- RADEON_CRTC2_PITCH
- RADEON_CRTC2_PIX_WIDTH_MASK
- RADEON_CRTC2_PIX_WIDTH_SHIFT
- RADEON_CRTC2_STATUS
- RADEON_CRTC2_SYNC_TRISTAT
- RADEON_CRTC2_TILE_EN
- RADEON_CRTC2_VBLANK_CUR
- RADEON_CRTC2_VBLANK_MASK
- RADEON_CRTC2_VBLANK_SAVE
- RADEON_CRTC2_VBLANK_SAVE_CLEAR
- RADEON_CRTC2_VBLANK_STAT
- RADEON_CRTC2_VBLANK_STAT_ACK
- RADEON_CRTC2_VLINE_CRNT_VLINE
- RADEON_CRTC2_VSYNC_DIS
- RADEON_CRTC2_VSYNC_TRISTAT
- RADEON_CRTC2_V_DISP
- RADEON_CRTC2_V_DISP_SHIFT
- RADEON_CRTC2_V_SYNC_POL
- RADEON_CRTC2_V_SYNC_STRT
- RADEON_CRTC2_V_SYNC_STRT_SHIFT
- RADEON_CRTC2_V_SYNC_STRT_WID
- RADEON_CRTC2_V_SYNC_WID
- RADEON_CRTC2_V_SYNC_WID_SHIFT
- RADEON_CRTC2_V_TOTAL
- RADEON_CRTC2_V_TOTAL_DISP
- RADEON_CRTC2_V_TOTAL_SHIFT
- RADEON_CRTC8_DATA
- RADEON_CRTC8_IDX
- RADEON_CRTC_AUTO_HORZ_CENTER_EN
- RADEON_CRTC_AUTO_VERT_CENTER_EN
- RADEON_CRTC_CRNT_FRAME
- RADEON_CRTC_CRNT_VLINE_MASK
- RADEON_CRTC_CRT_ON
- RADEON_CRTC_CSYNC_EN
- RADEON_CRTC_CUR_EN
- RADEON_CRTC_CUR_MODE_24BPP
- RADEON_CRTC_CUR_MODE_MASK
- RADEON_CRTC_CUR_MODE_MONO
- RADEON_CRTC_CUR_MODE_SHIFT
- RADEON_CRTC_DBL_SCAN_EN
- RADEON_CRTC_DISPLAY_DIS
- RADEON_CRTC_DISPLAY_DIS_BYTE
- RADEON_CRTC_DISP_REQ_EN_B
- RADEON_CRTC_EN
- RADEON_CRTC_EXT_CNTL
- RADEON_CRTC_EXT_CNTL_DPMS_BYTE
- RADEON_CRTC_EXT_DISP_EN
- RADEON_CRTC_GEN_CNTL
- RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN
- RADEON_CRTC_GUI_TRIG_OFFSET_RIGHT_EN
- RADEON_CRTC_GUI_TRIG_VLINE
- RADEON_CRTC_HSYNC_DIS
- RADEON_CRTC_HSYNC_DIS_BYTE
- RADEON_CRTC_H_CUTOFF_ACTIVE_EN
- RADEON_CRTC_H_DISP
- RADEON_CRTC_H_DISP_SHIFT
- RADEON_CRTC_H_SYNC_POL
- RADEON_CRTC_H_SYNC_STRT_CHAR
- RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT
- RADEON_CRTC_H_SYNC_STRT_PIX
- RADEON_CRTC_H_SYNC_STRT_WID
- RADEON_CRTC_H_SYNC_WID
- RADEON_CRTC_H_SYNC_WID_SHIFT
- RADEON_CRTC_H_TOTAL
- RADEON_CRTC_H_TOTAL_DISP
- RADEON_CRTC_H_TOTAL_SHIFT
- RADEON_CRTC_ICON_EN
- RADEON_CRTC_INTERLACE_EN
- RADEON_CRTC_MORE_CNTL
- RADEON_CRTC_OFFSET
- RADEON_CRTC_OFFSET_CNTL
- RADEON_CRTC_OFFSET_FLIP_CNTL
- RADEON_CRTC_OFFSET_RIGHT
- RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET
- RADEON_CRTC_OFFSET__OFFSET_LOCK
- RADEON_CRTC_PITCH
- RADEON_CRTC_PITCH__RIGHT_SHIFT
- RADEON_CRTC_PITCH__SHIFT
- RADEON_CRTC_STATUS
- RADEON_CRTC_STEREO_OFFSET_EN
- RADEON_CRTC_SYNC_TRISTAT
- RADEON_CRTC_TILE_EN
- RADEON_CRTC_TILE_EN_RIGHT
- RADEON_CRTC_TILE_LINE_RIGHT_SHIFT
- RADEON_CRTC_TILE_LINE_SHIFT
- RADEON_CRTC_VBLANK_CUR
- RADEON_CRTC_VBLANK_MASK
- RADEON_CRTC_VBLANK_SAVE
- RADEON_CRTC_VBLANK_SAVE_CLEAR
- RADEON_CRTC_VBLANK_STAT
- RADEON_CRTC_VBLANK_STAT_ACK
- RADEON_CRTC_VGA_XOVERSCAN
- RADEON_CRTC_VLINE_CRNT_VLINE
- RADEON_CRTC_VSTAT_MODE_MASK
- RADEON_CRTC_VSYNC_DIS
- RADEON_CRTC_VSYNC_DIS_BYTE
- RADEON_CRTC_V_CUTOFF_ACTIVE_EN
- RADEON_CRTC_V_DISP
- RADEON_CRTC_V_DISP_SHIFT
- RADEON_CRTC_V_SYNC_POL
- RADEON_CRTC_V_SYNC_STRT
- RADEON_CRTC_V_SYNC_STRT_SHIFT
- RADEON_CRTC_V_SYNC_STRT_WID
- RADEON_CRTC_V_SYNC_WID
- RADEON_CRTC_V_SYNC_WID_SHIFT
- RADEON_CRTC_V_TOTAL
- RADEON_CRTC_V_TOTAL_DISP
- RADEON_CRTC_V_TOTAL_SHIFT
- RADEON_CRT_ASYNC_RST
- RADEON_CRT_DPMS_ON
- RADEON_CRT_FIFO_CE_EN
- RADEON_CSQ_CNT_PRIMARY_MASK
- RADEON_CSQ_PRIBM_INDBM
- RADEON_CSQ_PRIBM_INDDIS
- RADEON_CSQ_PRIDIS_INDDIS
- RADEON_CSQ_PRIPIO_INDBM
- RADEON_CSQ_PRIPIO_INDDIS
- RADEON_CSQ_PRIPIO_INDPIO
- RADEON_CSQ_RPTR_INDIRECT_MASK
- RADEON_CSQ_RPTR_PRIMARY_MASK
- RADEON_CSQ_WPTR_INDIRECT_MASK
- RADEON_CSQ_WPTR_PRIMARY_MASK
- RADEON_CS_END_OF_FRAME
- RADEON_CS_KEEP_TILING_FLAGS
- RADEON_CS_MAX_PRIORITY
- RADEON_CS_NUM_BUCKETS
- RADEON_CS_RING_COMPUTE
- RADEON_CS_RING_DMA
- RADEON_CS_RING_GFX
- RADEON_CS_RING_UVD
- RADEON_CS_RING_VCE
- RADEON_CS_USE_VM
- RADEON_CULL_BACK
- RADEON_CULL_FRONT
- RADEON_CULL_FRONT_IS_CCW
- RADEON_CULL_FRONT_IS_CW
- RADEON_CUR2_CLR0
- RADEON_CUR2_CLR1
- RADEON_CUR2_HORZ_VERT_OFF
- RADEON_CUR2_HORZ_VERT_POSN
- RADEON_CUR2_LOCK
- RADEON_CUR2_OFFSET
- RADEON_CUR_CLR0
- RADEON_CUR_CLR1
- RADEON_CUR_HORZ_VERT_OFF
- RADEON_CUR_HORZ_VERT_POSN
- RADEON_CUR_LOCK
- RADEON_CUR_OFFSET
- RADEON_CV1_CRTC_MASK
- RADEON_CV1_CRTC_SHIFT
- RADEON_CV1_ON
- RADEON_CY_FILT_BLEND_SHIFT
- RADEON_C_GRN_EN
- RADEON_DAC2_CMP_EN
- RADEON_DAC2_CMP_OUTPUT
- RADEON_DAC2_CMP_OUT_B
- RADEON_DAC2_CMP_OUT_G
- RADEON_DAC2_CMP_OUT_R
- RADEON_DAC2_DAC2_CLK_SEL
- RADEON_DAC2_DAC_CLK_SEL
- RADEON_DAC2_FORCE_BLANK_OFF_EN
- RADEON_DAC2_FORCE_DATA_EN
- RADEON_DAC2_PALETTE_ACC_CTL
- RADEON_DAC2_TV_CLK_SEL
- RADEON_DAC_8BIT_EN
- RADEON_DAC_BLANKING
- RADEON_DAC_CMP_EN
- RADEON_DAC_CMP_OUTPUT
- RADEON_DAC_CNTL
- RADEON_DAC_CNTL2
- RADEON_DAC_CRC_SIG
- RADEON_DAC_DATA
- RADEON_DAC_DITHER_EN
- RADEON_DAC_EXT_CNTL
- RADEON_DAC_FORCE_BLANK_OFF_EN
- RADEON_DAC_FORCE_DATA_EN
- RADEON_DAC_FORCE_DATA_MASK
- RADEON_DAC_FORCE_DATA_SEL_B
- RADEON_DAC_FORCE_DATA_SEL_G
- RADEON_DAC_FORCE_DATA_SEL_MASK
- RADEON_DAC_FORCE_DATA_SEL_R
- RADEON_DAC_FORCE_DATA_SEL_RGB
- RADEON_DAC_FORCE_DATA_SHIFT
- RADEON_DAC_MACRO_CNTL
- RADEON_DAC_MASK
- RADEON_DAC_MASK_ALL
- RADEON_DAC_PDWN
- RADEON_DAC_PDWN_B
- RADEON_DAC_PDWN_G
- RADEON_DAC_PDWN_R
- RADEON_DAC_RANGE_CNTL
- RADEON_DAC_RANGE_CNTL_MASK
- RADEON_DAC_RANGE_CNTL_PS2
- RADEON_DAC_R_INDEX
- RADEON_DAC_TVO_EN
- RADEON_DAC_VGA_ADR_EN
- RADEON_DAC_W_INDEX
- RADEON_DDA_CONFIG
- RADEON_DDA_ON_OFF
- RADEON_DEBUGFS_MAX_COMPONENTS
- RADEON_DEFAULT_OFFSET
- RADEON_DEFAULT_PITCH
- RADEON_DEFAULT_SC_BOTTOM_MAX
- RADEON_DEFAULT_SC_BOTTOM_RIGHT
- RADEON_DEFAULT_SC_RIGHT_MAX
- RADEON_DEFAULT_UVD_HANDLES
- RADEON_DEPTH
- RADEON_DEPTHPITCH_MASK
- RADEON_DEPTHXY_OFFSET_ENABLE
- RADEON_DEPTH_ENDIAN_DWORD_SWAP
- RADEON_DEPTH_ENDIAN_NO_SWAP
- RADEON_DEPTH_ENDIAN_WORD_SWAP
- RADEON_DEPTH_FORMAT_16BIT_FLOAT_W
- RADEON_DEPTH_FORMAT_16BIT_INT_Z
- RADEON_DEPTH_FORMAT_24BIT_FLOAT_W
- RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z
- RADEON_DEPTH_FORMAT_24BIT_INT_Z
- RADEON_DEPTH_FORMAT_32BIT_FLOAT_W
- RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z
- RADEON_DEPTH_FORMAT_32BIT_INT_Z
- RADEON_DEPTH_FORMAT_MASK
- RADEON_DESTINATION_3D_CLR_CMP_MSK
- RADEON_DESTINATION_3D_CLR_CMP_VAL
- RADEON_DEVICE_ID
- RADEON_DFP1_ATTACHED
- RADEON_DFP1_CRTC_MASK
- RADEON_DFP1_CRTC_SHIFT
- RADEON_DFP1_ON
- RADEON_DFP2_ATTACHED
- RADEON_DFP2_CRTC_MASK
- RADEON_DFP2_CRTC_SHIFT
- RADEON_DFP2_ON
- RADEON_DFP_DPMS_ON
- RADEON_DIFFUSE_SHADE_FLAT
- RADEON_DIFFUSE_SHADE_GOURAUD
- RADEON_DIFFUSE_SHADE_MASK
- RADEON_DIFFUSE_SHADE_SOLID
- RADEON_DIFFUSE_SOURCE_SHIFT
- RADEON_DIFFUSE_SPECULAR_COMBINE
- RADEON_DIG_TMDS_ENABLE_RST
- RADEON_DISP2_MERGE_CNTL
- RADEON_DISP2_RGB_OFFSET_EN
- RADEON_DISPLAY2_BASE_ADDR
- RADEON_DISPLAY_BASE_ADDR
- RADEON_DISPLAY_ROT_00
- RADEON_DISPLAY_ROT_180
- RADEON_DISPLAY_ROT_270
- RADEON_DISPLAY_ROT_90
- RADEON_DISPLAY_ROT_MASK
- RADEON_DISPLAY_SWITCHING_DIS
- RADEON_DISP_ALPHA_MODE_GLOBAL
- RADEON_DISP_ALPHA_MODE_KEY
- RADEON_DISP_ALPHA_MODE_MASK
- RADEON_DISP_ALPHA_MODE_PER_PIXEL
- RADEON_DISP_D1D2_GRPH_RST
- RADEON_DISP_D1D2_OV0_RST
- RADEON_DISP_D1D2_SUBPIC_RST
- RADEON_DISP_D3_GRPH_RST
- RADEON_DISP_D3_OV0_RST
- RADEON_DISP_D3_REG_RST
- RADEON_DISP_D3_RST
- RADEON_DISP_D3_SUBPIC_RST
- RADEON_DISP_DAC2_SOURCE_CRTC2
- RADEON_DISP_DAC2_SOURCE_MASK
- RADEON_DISP_DAC_SOURCE_CRTC2
- RADEON_DISP_DAC_SOURCE_LTU
- RADEON_DISP_DAC_SOURCE_MASK
- RADEON_DISP_DAC_SOURCE_RMX
- RADEON_DISP_DYN_STOP_LAT_MASK
- RADEON_DISP_GRPH_ALPHA_MASK
- RADEON_DISP_HW_DEBUG
- RADEON_DISP_LIN_TRANS_BYPASS
- RADEON_DISP_LIN_TRANS_GRPH_A
- RADEON_DISP_LIN_TRANS_GRPH_B
- RADEON_DISP_LIN_TRANS_GRPH_C
- RADEON_DISP_LIN_TRANS_GRPH_D
- RADEON_DISP_LIN_TRANS_GRPH_E
- RADEON_DISP_LIN_TRANS_GRPH_F
- RADEON_DISP_MERGE_CNTL
- RADEON_DISP_MISC_CNTL
- RADEON_DISP_OUTPUT_CNTL
- RADEON_DISP_OV0_ALPHA_MASK
- RADEON_DISP_PWR_MAN
- RADEON_DISP_PWR_MAN_D3_CRTC2_EN
- RADEON_DISP_PWR_MAN_D3_CRTC_EN
- RADEON_DISP_PWR_MAN_DPMS_OFF
- RADEON_DISP_PWR_MAN_DPMS_ON
- RADEON_DISP_PWR_MAN_DPMS_STANDBY
- RADEON_DISP_PWR_MAN_DPMS_SUSPEND
- RADEON_DISP_RGB_OFFSET_EN
- RADEON_DISP_TRANS_MATRIX_ALPHA_MSB
- RADEON_DISP_TRANS_MATRIX_GRAPHICS
- RADEON_DISP_TRANS_MATRIX_MASK
- RADEON_DISP_TRANS_MATRIX_VIDEO
- RADEON_DISP_TVDAC_SOURCE_CRTC
- RADEON_DISP_TVDAC_SOURCE_CRTC2
- RADEON_DISP_TVDAC_SOURCE_LTU
- RADEON_DISP_TVDAC_SOURCE_MASK
- RADEON_DISP_TVDAC_SOURCE_RMX
- RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb
- RADEON_DISP_TV_OUT_CNTL
- RADEON_DISP_TV_PATH_SRC_CRTC1
- RADEON_DISP_TV_PATH_SRC_CRTC2
- RADEON_DISP_TV_SOURCE_CRTC
- RADEON_DISP_TV_SOURCE_LTU
- RADEON_DIS_OUT_OF_PCI_GART_ACCESS
- RADEON_DITHER_ENABLE
- RADEON_DITHER_INIT
- RADEON_DITHER_MODE
- RADEON_DLL_READY
- RADEON_DONT_USE_XTALIN
- RADEON_DOT_ALPHA_DONT_REPLICATE
- RADEON_DPMS_MASK
- RADEON_DPMS_OFF
- RADEON_DPMS_ON
- RADEON_DPMS_STANDBY
- RADEON_DPMS_SUSPEND
- RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL
- RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL
- RADEON_DPM_EVENT_SRC_ANALOG
- RADEON_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL
- RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL
- RADEON_DPM_EVENT_SRC_DIGITAL
- RADEON_DPM_EVENT_SRC_EXTERNAL
- RADEON_DPM_FORCED_LEVEL_AUTO
- RADEON_DPM_FORCED_LEVEL_HIGH
- RADEON_DPM_FORCED_LEVEL_LOW
- RADEON_DP_BRUSH_BKGD_CLR
- RADEON_DP_BRUSH_FRGD_CLR
- RADEON_DP_CNTL
- RADEON_DP_CNTL_XDIR_YDIR_YMAJOR
- RADEON_DP_DATATYPE
- RADEON_DP_DST_TILE_BOTH
- RADEON_DP_DST_TILE_LINEAR
- RADEON_DP_DST_TILE_MACRO
- RADEON_DP_DST_TILE_MICRO
- RADEON_DP_GUI_MASTER_CNTL
- RADEON_DP_GUI_MASTER_CNTL_C
- RADEON_DP_MIX
- RADEON_DP_SRC_BKGD_CLR
- RADEON_DP_SRC_FRGD_CLR
- RADEON_DP_SRC_SOURCE_HOST_DATA
- RADEON_DP_SRC_SOURCE_MASK
- RADEON_DP_SRC_SOURCE_MEMORY
- RADEON_DP_WRITE_MASK
- RADEON_DRIVER_BRIGHTNESS_EN
- RADEON_DRIVER_CRITICAL
- RADEON_DRV_LOADED
- RADEON_DSTCACHE_CTLSTAT
- RADEON_DST_BLEND_GL_DST_ALPHA
- RADEON_DST_BLEND_GL_DST_COLOR
- RADEON_DST_BLEND_GL_ONE
- RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA
- RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR
- RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA
- RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR
- RADEON_DST_BLEND_GL_SRC_ALPHA
- RADEON_DST_BLEND_GL_SRC_COLOR
- RADEON_DST_BLEND_GL_ZERO
- RADEON_DST_BLEND_MASK
- RADEON_DST_BRES_DEC
- RADEON_DST_BRES_ERR
- RADEON_DST_BRES_INC
- RADEON_DST_BRES_LNTH
- RADEON_DST_BRES_LNTH_SUB
- RADEON_DST_HEIGHT
- RADEON_DST_HEIGHT_WIDTH
- RADEON_DST_HEIGHT_WIDTH_8
- RADEON_DST_HEIGHT_WIDTH_BW
- RADEON_DST_HEIGHT_Y
- RADEON_DST_LINE_END
- RADEON_DST_LINE_PATCOUNT
- RADEON_DST_LINE_START
- RADEON_DST_OFFSET
- RADEON_DST_PITCH
- RADEON_DST_PITCH_OFFSET
- RADEON_DST_PITCH_OFFSET_C
- RADEON_DST_TILE_BOTH
- RADEON_DST_TILE_LINEAR
- RADEON_DST_TILE_MACRO
- RADEON_DST_TILE_MICRO
- RADEON_DST_WIDTH
- RADEON_DST_WIDTH_HEIGHT
- RADEON_DST_WIDTH_X
- RADEON_DST_WIDTH_X_INCY
- RADEON_DST_X
- RADEON_DST_X_DIR_LEFT_TO_RIGHT
- RADEON_DST_X_LEFT_TO_RIGHT
- RADEON_DST_X_SUB
- RADEON_DST_X_Y
- RADEON_DST_Y
- RADEON_DST_Y_DIR_TOP_TO_BOTTOM
- RADEON_DST_Y_MAJOR
- RADEON_DST_Y_SUB
- RADEON_DST_Y_TOP_TO_BOTTOM
- RADEON_DST_Y_X
- RADEON_DVI_I2C_CNTL_0
- RADEON_DVI_I2C_CNTL_1
- RADEON_DVI_I2C_DATA
- RADEON_DVS_ASYNC_RST
- RADEON_DYN_STOP_LAT_MASK
- RADEON_DYN_STOP_MODE_MASK
- RADEON_EMISSIVE_SOURCE_SHIFT
- RADEON_EMIT_PP_BORDER_COLOR_0
- RADEON_EMIT_PP_BORDER_COLOR_1
- RADEON_EMIT_PP_BORDER_COLOR_2
- RADEON_EMIT_PP_CNTL
- RADEON_EMIT_PP_CUBIC_FACES_0
- RADEON_EMIT_PP_CUBIC_FACES_1
- RADEON_EMIT_PP_CUBIC_FACES_2
- RADEON_EMIT_PP_CUBIC_OFFSETS_T0
- RADEON_EMIT_PP_CUBIC_OFFSETS_T1
- RADEON_EMIT_PP_CUBIC_OFFSETS_T2
- RADEON_EMIT_PP_LUM_MATRIX
- RADEON_EMIT_PP_MISC
- RADEON_EMIT_PP_ROT_MATRIX_0
- RADEON_EMIT_PP_TEX_SIZE_0
- RADEON_EMIT_PP_TEX_SIZE_1
- RADEON_EMIT_PP_TEX_SIZE_2
- RADEON_EMIT_PP_TXFILTER_0
- RADEON_EMIT_PP_TXFILTER_1
- RADEON_EMIT_PP_TXFILTER_2
- RADEON_EMIT_RB3D_COLORPITCH
- RADEON_EMIT_RB3D_STENCILREFMASK
- RADEON_EMIT_RE_LINE_PATTERN
- RADEON_EMIT_RE_MISC
- RADEON_EMIT_SE_CNTL
- RADEON_EMIT_SE_CNTL_STATUS
- RADEON_EMIT_SE_LINE_WIDTH
- RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED
- RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT
- RADEON_EMIT_SE_VPORT_XSCALE
- RADEON_EMIT_SE_ZBIAS_FACTOR
- RADEON_ENGIN_DYNCLK_MODE
- RADEON_ENG_DISPLAY_SELECT_CRTC0
- RADEON_ENG_DISPLAY_SELECT_CRTC1
- RADEON_EXCL_HORZ_BACK_PORCH_MASK
- RADEON_EXCL_HORZ_END_MASK
- RADEON_EXCL_HORZ_EXCLUSIVE_EN
- RADEON_EXCL_HORZ_START_MASK
- RADEON_EXCL_VERT_END_MASK
- RADEON_EXCL_VERT_START_MASK
- RADEON_EXT_DESKTOP_MODE
- RADEON_FACE_HEIGHT_1_MASK
- RADEON_FACE_HEIGHT_1_SHIFT
- RADEON_FACE_HEIGHT_2_MASK
- RADEON_FACE_HEIGHT_2_SHIFT
- RADEON_FACE_HEIGHT_3_MASK
- RADEON_FACE_HEIGHT_3_SHIFT
- RADEON_FACE_HEIGHT_4_MASK
- RADEON_FACE_HEIGHT_4_SHIFT
- RADEON_FACE_WIDTH_1_MASK
- RADEON_FACE_WIDTH_1_SHIFT
- RADEON_FACE_WIDTH_2_MASK
- RADEON_FACE_WIDTH_2_SHIFT
- RADEON_FACE_WIDTH_3_MASK
- RADEON_FACE_WIDTH_3_SHIFT
- RADEON_FACE_WIDTH_4_MASK
- RADEON_FACE_WIDTH_4_SHIFT
- RADEON_FAMILY_H
- RADEON_FAMILY_MASK
- RADEON_FCP0_SRC_GND
- RADEON_FCP0_SRC_HREF
- RADEON_FCP0_SRC_HREFb
- RADEON_FCP0_SRC_PCICLK
- RADEON_FCP0_SRC_PCLK
- RADEON_FCP0_SRC_PCLKb
- RADEON_FCP_CNTL
- RADEON_FENCE_JIFFIES_TIMEOUT
- RADEON_FFACE_CULL
- RADEON_FFACE_CULL_CCW
- RADEON_FFACE_CULL_CW
- RADEON_FFACE_CULL_DIR_MASK
- RADEON_FFACE_CULL_MASK
- RADEON_FFACE_SOLID
- RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT
- RADEON_FILTER_COEF_MASK
- RADEON_FILTER_HARDCODED_COEF
- RADEON_FILTER_HC_COEF_HORZ_UV
- RADEON_FILTER_HC_COEF_HORZ_Y
- RADEON_FILTER_HC_COEF_VERT_UV
- RADEON_FILTER_HC_COEF_VERT_Y
- RADEON_FILTER_PROGRAMMABLE_COEF
- RADEON_FLAGS_MASK
- RADEON_FLAT_SHADE_VTX_0
- RADEON_FLAT_SHADE_VTX_1
- RADEON_FLAT_SHADE_VTX_2
- RADEON_FLAT_SHADE_VTX_LAST
- RADEON_FLIP_NONE
- RADEON_FLIP_PENDING
- RADEON_FLIP_SUBMITTED
- RADEON_FLUSH_1
- RADEON_FLUSH_2
- RADEON_FLUSH_3
- RADEON_FLUSH_4
- RADEON_FLUSH_5
- RADEON_FLUSH_6
- RADEON_FLUSH_7
- RADEON_FMT_DITHER_DISABLE
- RADEON_FMT_DITHER_ENABLE
- RADEON_FOG_3D_TABLE_DENSITY
- RADEON_FOG_3D_TABLE_END
- RADEON_FOG_3D_TABLE_START
- RADEON_FOG_COLOR_MASK
- RADEON_FOG_ENABLE
- RADEON_FOG_SHADE_FLAT
- RADEON_FOG_SHADE_GOURAUD
- RADEON_FOG_SHADE_MASK
- RADEON_FOG_SHADE_SOLID
- RADEON_FOG_TABLE
- RADEON_FOG_TABLE_DATA
- RADEON_FOG_TABLE_INDEX
- RADEON_FOG_USE_DEPTH
- RADEON_FOG_USE_DIFFUSE_ALPHA
- RADEON_FOG_USE_SPEC_ALPHA
- RADEON_FOG_VERTEX
- RADEON_FORCEON_AIC
- RADEON_FORCEON_MC
- RADEON_FORCEON_MCLKA
- RADEON_FORCEON_MCLKB
- RADEON_FORCEON_YCLKA
- RADEON_FORCEON_YCLKB
- RADEON_FORCE_BURST_ALWAYS
- RADEON_FORCE_W_TO_ONE
- RADEON_FORCE_Z_DIRTY
- RADEON_FP2_BLANK_EN
- RADEON_FP2_CRC_EN
- RADEON_FP2_CRC_READ_EN
- RADEON_FP2_DETECT_INT_POL
- RADEON_FP2_DETECT_MASK
- RADEON_FP2_DETECT_SENSE
- RADEON_FP2_DETECT_STAT
- RADEON_FP2_DETECT_STAT_ACK
- RADEON_FP2_DVO_EN
- RADEON_FP2_DVO_RATE_SEL_SDR
- RADEON_FP2_FP_POL
- RADEON_FP2_GEN_CNTL
- RADEON_FP2_LCD_CNTL_MASK
- RADEON_FP2_LP_POL
- RADEON_FP2_ON
- RADEON_FP2_PAD_FLOP_EN
- RADEON_FP2_PANEL_FORMAT
- RADEON_FP2_SCK_POL
- RADEON_FP2_SRC_SEL_CRTC2
- RADEON_FP2_SRC_SEL_MASK
- RADEON_FP_BLANK_EN
- RADEON_FP_CHIP_SCALE_EN
- RADEON_FP_CRTC_DONT_SHADOW_HEND
- RADEON_FP_CRTC_DONT_SHADOW_HPAR
- RADEON_FP_CRTC_DONT_SHADOW_VPAR
- RADEON_FP_CRTC_H_DISP_MASK
- RADEON_FP_CRTC_H_DISP_SHIFT
- RADEON_FP_CRTC_H_TOTAL_DISP
- RADEON_FP_CRTC_H_TOTAL_MASK
- RADEON_FP_CRTC_H_TOTAL_SHIFT
- RADEON_FP_CRTC_LOCK_8DOT
- RADEON_FP_CRTC_USE_SHADOW_VEND
- RADEON_FP_CRTC_V_DISP_MASK
- RADEON_FP_CRTC_V_DISP_SHIFT
- RADEON_FP_CRTC_V_TOTAL_DISP
- RADEON_FP_CRTC_V_TOTAL_MASK
- RADEON_FP_CRTC_V_TOTAL_SHIFT
- RADEON_FP_CRT_SYNC_ALT
- RADEON_FP_CRT_SYNC_SEL
- RADEON_FP_DETECT_INT_POL
- RADEON_FP_DETECT_MASK
- RADEON_FP_DETECT_SENSE
- RADEON_FP_DETECT_STAT
- RADEON_FP_DETECT_STAT_ACK
- RADEON_FP_DFP_SYNC_SEL
- RADEON_FP_EN_TMDS
- RADEON_FP_FPON
- RADEON_FP_GEN_CNTL
- RADEON_FP_H2_SYNC_STRT_WID
- RADEON_FP_HORZ2_STRETCH
- RADEON_FP_HORZ_STRETCH
- RADEON_FP_HORZ_VERT_ACTIVE
- RADEON_FP_H_SYNC_STRT_CHAR_MASK
- RADEON_FP_H_SYNC_STRT_CHAR_SHIFT
- RADEON_FP_H_SYNC_STRT_WID
- RADEON_FP_H_SYNC_WID_MASK
- RADEON_FP_H_SYNC_WID_SHIFT
- RADEON_FP_PANEL_FORMAT
- RADEON_FP_PANEL_SCALABLE
- RADEON_FP_PANEL_SCALE_EN
- RADEON_FP_RMX_HVSYNC_CONTROL_EN
- RADEON_FP_SEL_CRTC1
- RADEON_FP_SEL_CRTC2
- RADEON_FP_TMDS_EN
- RADEON_FP_USE_SHADOW_EN
- RADEON_FP_V2_SYNC_STRT_WID
- RADEON_FP_VERT2_STRETCH
- RADEON_FP_VERT_STRETCH
- RADEON_FP_V_SYNC_STRT_MASK
- RADEON_FP_V_SYNC_STRT_SHIFT
- RADEON_FP_V_SYNC_STRT_WID
- RADEON_FP_V_SYNC_WID_MASK
- RADEON_FP_V_SYNC_WID_SHIFT
- RADEON_FRONT
- RADEON_GART_PAGE_DUMMY
- RADEON_GART_PAGE_READ
- RADEON_GART_PAGE_SNOOP
- RADEON_GART_PAGE_VALID
- RADEON_GART_PAGE_WRITE
- RADEON_GART_TEX_HEAP
- RADEON_GEM_CPU_ACCESS
- RADEON_GEM_DOMAIN_CPU
- RADEON_GEM_DOMAIN_GTT
- RADEON_GEM_DOMAIN_VRAM
- RADEON_GEM_GTT_UC
- RADEON_GEM_GTT_WC
- RADEON_GEM_MAX_SURFACES
- RADEON_GEM_NO_BACKING_STORE
- RADEON_GEM_NO_CPU_ACCESS
- RADEON_GEM_OP_GET_INITIAL_DOMAIN
- RADEON_GEM_OP_SET_INITIAL_DOMAIN
- RADEON_GEM_USERPTR_ANONONLY
- RADEON_GEM_USERPTR_READONLY
- RADEON_GEM_USERPTR_REGISTER
- RADEON_GEM_USERPTR_VALIDATE
- RADEON_GENENB
- RADEON_GENFC_RD
- RADEON_GENFC_WT
- RADEON_GENMO_RD
- RADEON_GENMO_WT
- RADEON_GENS0
- RADEON_GENS1
- RADEON_GEN_INT_CNTL
- RADEON_GEN_INT_STATUS
- RADEON_GMC_3D_FCN_EN
- RADEON_GMC_AUX_CLIP_DIS
- RADEON_GMC_BRUSH_1X8_COLOR
- RADEON_GMC_BRUSH_1X8_MONO_FG_BG
- RADEON_GMC_BRUSH_1X8_MONO_FG_LA
- RADEON_GMC_BRUSH_32x1_MONO_FG_BG
- RADEON_GMC_BRUSH_32x1_MONO_FG_LA
- RADEON_GMC_BRUSH_32x32_MONO_FG_BG
- RADEON_GMC_BRUSH_32x32_MONO_FG_LA
- RADEON_GMC_BRUSH_8X8_MONO_FG_BG
- RADEON_GMC_BRUSH_8X8_MONO_FG_LA
- RADEON_GMC_BRUSH_8x8_COLOR
- RADEON_GMC_BRUSH_DATATYPE_MASK
- RADEON_GMC_BRUSH_NONE
- RADEON_GMC_BRUSH_SOLID_COLOR
- RADEON_GMC_BYTE_LSB_TO_MSB
- RADEON_GMC_BYTE_MSB_TO_LSB
- RADEON_GMC_BYTE_PIX_ORDER
- RADEON_GMC_CLR_CMP_CNTL_DIS
- RADEON_GMC_CONVERSION_TEMP
- RADEON_GMC_CONVERSION_TEMP_6500
- RADEON_GMC_CONVERSION_TEMP_9300
- RADEON_GMC_DST_15BPP
- RADEON_GMC_DST_16BPP
- RADEON_GMC_DST_24BPP
- RADEON_GMC_DST_32BPP
- RADEON_GMC_DST_8BPP_CI
- RADEON_GMC_DST_8BPP_RGB
- RADEON_GMC_DST_ARGB4444
- RADEON_GMC_DST_AYUV444
- RADEON_GMC_DST_CLIPPING
- RADEON_GMC_DST_DATATYPE_MASK
- RADEON_GMC_DST_DATATYPE_SHIFT
- RADEON_GMC_DST_PITCH_OFFSET_CNTL
- RADEON_GMC_DST_RGB8
- RADEON_GMC_DST_VYUY
- RADEON_GMC_DST_Y8
- RADEON_GMC_DST_YVYU
- RADEON_GMC_LD_BRUSH_Y_X
- RADEON_GMC_ROP3_MASK
- RADEON_GMC_SRC_CLIPPING
- RADEON_GMC_SRC_DATATYPE_COLOR
- RADEON_GMC_SRC_DATATYPE_MASK
- RADEON_GMC_SRC_DATATYPE_MONO_FG_BG
- RADEON_GMC_SRC_DATATYPE_MONO_FG_LA
- RADEON_GMC_SRC_PITCH_OFFSET_CNTL
- RADEON_GMC_WR_MSK_DIS
- RADEON_GPIOPAD_A
- RADEON_GPIOPAD_EN
- RADEON_GPIOPAD_MASK
- RADEON_GPIOPAD_Y
- RADEON_GPIO_A_0
- RADEON_GPIO_A_1
- RADEON_GPIO_CRT2_DDC
- RADEON_GPIO_DVI_DDC
- RADEON_GPIO_EN_0
- RADEON_GPIO_EN_1
- RADEON_GPIO_MASK_0
- RADEON_GPIO_MASK_1
- RADEON_GPIO_MONID
- RADEON_GPIO_MONIDB
- RADEON_GPIO_VGA_DDC
- RADEON_GPIO_Y_0
- RADEON_GPIO_Y_1
- RADEON_GPIO_Y_SHIFT_0
- RADEON_GPIO_Y_SHIFT_1
- RADEON_GPU_PAGE_ALIGN
- RADEON_GPU_PAGE_MASK
- RADEON_GPU_PAGE_SHIFT
- RADEON_GPU_PAGE_SIZE
- RADEON_GRAPHIC_KEY_FN_EQ
- RADEON_GRAPHIC_KEY_FN_FALSE
- RADEON_GRAPHIC_KEY_FN_MASK
- RADEON_GRAPHIC_KEY_FN_NE
- RADEON_GRAPHIC_KEY_FN_TRUE
- RADEON_GRN_MX_FORCE_DAC_DATA
- RADEON_GRPH2_BUFFER_CNTL
- RADEON_GRPH2_BUFFER_SIZE
- RADEON_GRPH2_CRITICAL_AT_SOF
- RADEON_GRPH2_CRITICAL_CNTL
- RADEON_GRPH2_CRITICAL_POINT_MASK
- RADEON_GRPH2_CRITICAL_POINT_SHIFT
- RADEON_GRPH2_START_REQ_MASK
- RADEON_GRPH2_START_REQ_SHIFT
- RADEON_GRPH2_STOP_CNTL
- RADEON_GRPH2_STOP_REQ_MASK
- RADEON_GRPH2_STOP_REQ_SHIFT
- RADEON_GRPH8_DATA
- RADEON_GRPH8_IDX
- RADEON_GRPH_BUFFER_CNTL
- RADEON_GRPH_BUFFER_SIZE
- RADEON_GRPH_CRITICAL_AT_SOF
- RADEON_GRPH_CRITICAL_CNTL
- RADEON_GRPH_CRITICAL_POINT_MASK
- RADEON_GRPH_CRITICAL_POINT_SHIFT
- RADEON_GRPH_START_REQ_MASK
- RADEON_GRPH_START_REQ_SHIFT
- RADEON_GRPH_STOP_CNTL
- RADEON_GRPH_STOP_REQ_MASK
- RADEON_GRPH_STOP_REQ_SHIFT
- RADEON_GUI_IDLE_MASK
- RADEON_GUI_IDLE_STAT
- RADEON_GUI_IDLE_STAT_ACK
- RADEON_GUI_SCRATCH_REG0
- RADEON_GUI_SCRATCH_REG1
- RADEON_GUI_SCRATCH_REG2
- RADEON_GUI_SCRATCH_REG3
- RADEON_GUI_SCRATCH_REG4
- RADEON_GUI_SCRATCH_REG5
- RADEON_HAS_HIERZ
- RADEON_HCODE_TABLE_SEL_MASK
- RADEON_HCODE_TABLE_SEL_SHIFT
- RADEON_HDP_APER_CNTL
- RADEON_HDP_READ_BUFFER_INVALIDATE
- RADEON_HDP_SOFT_RESET
- RADEON_HEADER
- RADEON_HORZ_AUTO_RATIO
- RADEON_HORZ_AUTO_RATIO_INC
- RADEON_HORZ_FP_LOOP_STRETCH
- RADEON_HORZ_PANEL_SHIFT
- RADEON_HORZ_PANEL_SIZE
- RADEON_HORZ_STRETCH_BLEND
- RADEON_HORZ_STRETCH_ENABLE
- RADEON_HORZ_STRETCH_PIXREP
- RADEON_HORZ_STRETCH_RATIO_MASK
- RADEON_HORZ_STRETCH_RATIO_MAX
- RADEON_HOST_BIG_ENDIAN_EN
- RADEON_HOST_DATA0
- RADEON_HOST_DATA1
- RADEON_HOST_DATA2
- RADEON_HOST_DATA3
- RADEON_HOST_DATA4
- RADEON_HOST_DATA5
- RADEON_HOST_DATA6
- RADEON_HOST_DATA7
- RADEON_HOST_DATA_LAST
- RADEON_HOST_DATA_SWAP_16BIT
- RADEON_HOST_DATA_SWAP_32BIT
- RADEON_HOST_DATA_SWAP_HDW
- RADEON_HOST_DATA_SWAP_NONE
- RADEON_HOST_FIFO_RD
- RADEON_HOST_FIFO_RD_ACK
- RADEON_HOST_FIFO_WT
- RADEON_HOST_FIFO_WT_ACK
- RADEON_HOST_PATH_CNTL
- RADEON_HPD_1
- RADEON_HPD_2
- RADEON_HPD_3
- RADEON_HPD_4
- RADEON_HPD_5
- RADEON_HPD_6
- RADEON_HPD_NONE
- RADEON_HP_LIN_RD_CACHE_DIS
- RADEON_HSYNC_DELAY_MASK
- RADEON_HSYNC_DELAY_SHIFT
- RADEON_HTOTAL2_CNTL
- RADEON_HTOTAL_CNTL
- RADEON_HTOT_CNTL_VGA_EN
- RADEON_HW_NEEDS_DVI_I2C
- RADEON_HW_USING_DVI_I2C
- RADEON_H_INC_MASK
- RADEON_H_INC_SHIFT
- RADEON_I2C_ABORT
- RADEON_I2C_ADDR_COUNT_SHIFT
- RADEON_I2C_CNTL_0
- RADEON_I2C_CNTL_1
- RADEON_I2C_DATA
- RADEON_I2C_DATA_COUNT_SHIFT
- RADEON_I2C_DONE
- RADEON_I2C_DRIVE_EN
- RADEON_I2C_DRIVE_SEL
- RADEON_I2C_EN
- RADEON_I2C_GO
- RADEON_I2C_HALT
- RADEON_I2C_INTRA_BYTE_DELAY_SHIFT
- RADEON_I2C_NACK
- RADEON_I2C_PRESCALE_SHIFT
- RADEON_I2C_RECEIVE
- RADEON_I2C_SEL
- RADEON_I2C_SOFT_RST
- RADEON_I2C_START
- RADEON_I2C_STOP
- RADEON_I2C_TIME_LIMIT_SHIFT
- RADEON_IB_POOL_SIZE
- RADEON_IB_VM_MAX_SIZE
- RADEON_IDCT_AUTH
- RADEON_IDCT_AUTH_CONTROL
- RADEON_IDCT_CONTROL
- RADEON_IDCT_LEVELS
- RADEON_IDCT_RUNS
- RADEON_IDLE_LOOP_MS
- RADEON_INDEX_PRIM_OFFSET
- RADEON_INDIRECT1_START_MASK
- RADEON_INDIRECT1_START_SHIFT
- RADEON_INDIRECT2_START_MASK
- RADEON_INDIRECT2_START_SHIFT
- RADEON_INFO_ACCEL_WORKING
- RADEON_INFO_ACCEL_WORKING2
- RADEON_INFO_ACTIVE_CU_COUNT
- RADEON_INFO_BACKEND_MAP
- RADEON_INFO_CIK_MACROTILE_MODE_ARRAY
- RADEON_INFO_CLOCK_CRYSTAL_FREQ
- RADEON_INFO_CRTC_FROM_ID
- RADEON_INFO_CURRENT_GPU_MCLK
- RADEON_INFO_CURRENT_GPU_SCLK
- RADEON_INFO_CURRENT_GPU_TEMP
- RADEON_INFO_DEVICE_ID
- RADEON_INFO_FASTFB_WORKING
- RADEON_INFO_FUSION_GART_WORKING
- RADEON_INFO_GPU_RESET_COUNTER
- RADEON_INFO_GTT_USAGE
- RADEON_INFO_IB_VM_MAX_SIZE
- RADEON_INFO_MAX_PIPES
- RADEON_INFO_MAX_SCLK
- RADEON_INFO_MAX_SE
- RADEON_INFO_MAX_SH_PER_SE
- RADEON_INFO_NUM_BACKENDS
- RADEON_INFO_NUM_BYTES_MOVED
- RADEON_INFO_NUM_GB_PIPES
- RADEON_INFO_NUM_TILE_PIPES
- RADEON_INFO_NUM_Z_PIPES
- RADEON_INFO_READ_REG
- RADEON_INFO_RING_WORKING
- RADEON_INFO_SI_BACKEND_ENABLED_MASK
- RADEON_INFO_SI_CP_DMA_COMPUTE
- RADEON_INFO_SI_TILE_MODE_ARRAY
- RADEON_INFO_TILING_CONFIG
- RADEON_INFO_TIMESTAMP
- RADEON_INFO_VA_START
- RADEON_INFO_VA_UNMAP_WORKING
- RADEON_INFO_VCE_FB_VERSION
- RADEON_INFO_VCE_FW_VERSION
- RADEON_INFO_VRAM_USAGE
- RADEON_INFO_WANT_CMASK
- RADEON_INFO_WANT_HYPERZ
- RADEON_INTERRUPT_LINE
- RADEON_INTERRUPT_PIN
- RADEON_IO_BASE
- RADEON_IO_MCLK_DYN_ENABLE
- RADEON_IO_MCLK_MAX_DYN_STOP_LAT
- RADEON_ISYNC_ANY2D_IDLE3D
- RADEON_ISYNC_ANY3D_IDLE2D
- RADEON_ISYNC_CNTL
- RADEON_ISYNC_CPSCRATCH_IDLEGUI
- RADEON_ISYNC_TRIG2D_IDLE3D
- RADEON_ISYNC_TRIG3D_IDLE2D
- RADEON_ISYNC_WAIT_IDLEGUI
- RADEON_IS_AGP
- RADEON_IS_IGP
- RADEON_IS_IGPGART
- RADEON_IS_MOBILITY
- RADEON_IS_PCI
- RADEON_IS_PCIE
- RADEON_IS_PX
- RADEON_IT_MODELVIEW_0_SHIFT
- RADEON_IT_MODELVIEW_1_SHIFT
- RADEON_IT_MODELVIEW_2_SHIFT
- RADEON_IT_MODELVIEW_3_SHIFT
- RADEON_LATENCY
- RADEON_LCD1_ATTACHED
- RADEON_LCD1_CRTC_MASK
- RADEON_LCD1_CRTC_SHIFT
- RADEON_LCD1_ON
- RADEON_LCD_DPMS_ON
- RADEON_LEAD_BRES_DEC
- RADEON_LEAD_BRES_LNTH
- RADEON_LEAD_BRES_LNTH_SUB
- RADEON_LIGHTING_ENABLE
- RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN
- RADEON_LIGHT_0_DUAL_CONE
- RADEON_LIGHT_0_ENABLE
- RADEON_LIGHT_0_ENABLE_AMBIENT
- RADEON_LIGHT_0_ENABLE_RANGE_ATTEN
- RADEON_LIGHT_0_ENABLE_SPECULAR
- RADEON_LIGHT_0_IS_LOCAL
- RADEON_LIGHT_0_IS_SPOT
- RADEON_LIGHT_0_SHIFT
- RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN
- RADEON_LIGHT_1_DUAL_CONE
- RADEON_LIGHT_1_ENABLE
- RADEON_LIGHT_1_ENABLE_AMBIENT
- RADEON_LIGHT_1_ENABLE_RANGE_ATTEN
- RADEON_LIGHT_1_ENABLE_SPECULAR
- RADEON_LIGHT_1_IS_LOCAL
- RADEON_LIGHT_1_IS_SPOT
- RADEON_LIGHT_1_SHIFT
- RADEON_LIGHT_2_SHIFT
- RADEON_LIGHT_3_SHIFT
- RADEON_LIGHT_4_SHIFT
- RADEON_LIGHT_5_SHIFT
- RADEON_LIGHT_6_SHIFT
- RADEON_LIGHT_7_SHIFT
- RADEON_LIGHT_ALPHA
- RADEON_LIGHT_IN_MODELSPACE
- RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY
- RADEON_LIGHT_TWOSIDE
- RADEON_LINES
- RADEON_LINE_CURRENT_COUNT_SHIFT
- RADEON_LINE_CURRENT_PTR_SHIFT
- RADEON_LINE_PATTERN_AUTO_RESET
- RADEON_LINE_PATTERN_BIG_BIT_ORDER
- RADEON_LINE_PATTERN_LITTLE_BIT_ORDER
- RADEON_LINE_PATTERN_MASK
- RADEON_LINE_PATTERN_START_SHIFT
- RADEON_LINE_REPEAT_COUNT_SHIFT
- RADEON_LINE_STRIP
- RADEON_LM_SOURCE_STATE_MULT
- RADEON_LM_SOURCE_STATE_PREMULT
- RADEON_LM_SOURCE_VERTEX_DIFFUSE
- RADEON_LM_SOURCE_VERTEX_SPECULAR
- RADEON_LOCAL_LIGHT_VEC_GL
- RADEON_LOCAL_TEX_HEAP
- RADEON_LOCAL_VIEWER
- RADEON_LOD_BIAS_MASK
- RADEON_LOD_BIAS_SHIFT
- RADEON_LOG_TEX_GRANULARITY
- RADEON_LVDS_2_GREY
- RADEON_LVDS_4_GREY
- RADEON_LVDS_BLON
- RADEON_LVDS_BL_CLK_SEL
- RADEON_LVDS_BL_MOD_EN
- RADEON_LVDS_BL_MOD_LEVEL_MASK
- RADEON_LVDS_BL_MOD_LEVEL_SHIFT
- RADEON_LVDS_DIGON
- RADEON_LVDS_DISPLAY_DIS
- RADEON_LVDS_DTM_POL_LOW
- RADEON_LVDS_EN
- RADEON_LVDS_FPDI_EN
- RADEON_LVDS_FP_POL_LOW
- RADEON_LVDS_GEN_CNTL
- RADEON_LVDS_HSYNC_DELAY_SHIFT
- RADEON_LVDS_LP_POL_LOW
- RADEON_LVDS_NO_FM
- RADEON_LVDS_ON
- RADEON_LVDS_PANEL_FORMAT
- RADEON_LVDS_PANEL_TYPE
- RADEON_LVDS_PLL_CNTL
- RADEON_LVDS_PLL_EN
- RADEON_LVDS_PLL_RESET
- RADEON_LVDS_PWRSEQ_DELAY1_SHIFT
- RADEON_LVDS_PWRSEQ_DELAY2_SHIFT
- RADEON_LVDS_RST_FM
- RADEON_LVDS_SEL_CRTC2
- RADEON_LVDS_SS_GEN_CNTL
- RADEON_MAG_FILTER_LINEAR
- RADEON_MAG_FILTER_MASK
- RADEON_MAG_FILTER_NEAREST
- RADEON_MAX_AFMT_BLOCKS
- RADEON_MAX_ANISO_16_TO_1
- RADEON_MAX_ANISO_1_TO_1
- RADEON_MAX_ANISO_2_TO_1
- RADEON_MAX_ANISO_4_TO_1
- RADEON_MAX_ANISO_8_TO_1
- RADEON_MAX_ANISO_MASK
- RADEON_MAX_BIOS_CONNECTOR
- RADEON_MAX_BL_LEVEL
- RADEON_MAX_CRTCS
- RADEON_MAX_DOORBELLS
- RADEON_MAX_FETCH_MASK
- RADEON_MAX_FETCH_SHIFT
- RADEON_MAX_HPD_PINS
- RADEON_MAX_I2C_BUS
- RADEON_MAX_LATENCY
- RADEON_MAX_MIP_LEVEL_MASK
- RADEON_MAX_MIP_LEVEL_SHIFT
- RADEON_MAX_STATE_PACKETS
- RADEON_MAX_SURFACES
- RADEON_MAX_TEXTURE_LEVELS
- RADEON_MAX_TEXTURE_UNITS
- RADEON_MAX_USEC_TIMEOUT
- RADEON_MAX_UVD_HANDLES
- RADEON_MAX_UV_ADR_MASK
- RADEON_MAX_UV_ADR_SHIFT
- RADEON_MAX_VCE_HANDLES
- RADEON_MAX_VCE_LEVELS
- RADEON_MCLKA_SRC_SEL_MASK
- RADEON_MCLK_CNTL
- RADEON_MCLK_MISC
- RADEON_MC_AGP_LOCATION
- RADEON_MC_AGP_START_MASK
- RADEON_MC_AGP_START_SHIFT
- RADEON_MC_AGP_TOP_MASK
- RADEON_MC_AGP_TOP_SHIFT
- RADEON_MC_BUSY
- RADEON_MC_ENABLE
- RADEON_MC_FB_LOCATION
- RADEON_MC_FB_START_MASK
- RADEON_MC_FB_START_SHIFT
- RADEON_MC_FB_TOP_MASK
- RADEON_MC_FB_TOP_SHIFT
- RADEON_MC_IDLE
- RADEON_MC_MCLK_DYN_ENABLE
- RADEON_MC_MCLK_MAX_DYN_STOP_LAT
- RADEON_MC_STATUS
- RADEON_MDGPIO_A
- RADEON_MDGPIO_EN
- RADEON_MDGPIO_MASK
- RADEON_MDGPIO_Y
- RADEON_MEM_ADDR_CONFIG
- RADEON_MEM_BASE
- RADEON_MEM_CFG_TYPE_DDR
- RADEON_MEM_CNTL
- RADEON_MEM_INIT_LAT_TIMER
- RADEON_MEM_INTF_CNTL
- RADEON_MEM_NUM_CHANNELS_MASK
- RADEON_MEM_PWRUP_COMPLETE
- RADEON_MEM_PWRUP_COMPL_A
- RADEON_MEM_PWRUP_COMPL_B
- RADEON_MEM_REGION_FB
- RADEON_MEM_REGION_GART
- RADEON_MEM_SDRAM_MODE_REG
- RADEON_MEM_STR_CNTL
- RADEON_MEM_TIMING_CNTL
- RADEON_MEM_USE_B_CH_ONLY
- RADEON_MEM_VGA_RP_SEL
- RADEON_MEM_VGA_WP_SEL
- RADEON_MIN_FILTER_ANISO_LINEAR
- RADEON_MIN_FILTER_ANISO_NEAREST
- RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR
- RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST
- RADEON_MIN_FILTER_LINEAR
- RADEON_MIN_FILTER_LINEAR_MIP_LINEAR
- RADEON_MIN_FILTER_LINEAR_MIP_NEAREST
- RADEON_MIN_FILTER_MASK
- RADEON_MIN_FILTER_NEAREST
- RADEON_MIN_FILTER_NEAREST_MIP_LINEAR
- RADEON_MIN_FILTER_NEAREST_MIP_NEAREST
- RADEON_MIN_GRANT
- RADEON_MIN_MMIO_SIZE
- RADEON_MM_APER
- RADEON_MM_DATA
- RADEON_MM_INDEX
- RADEON_MODELPROJECT_0_SHIFT
- RADEON_MODELPROJECT_1_SHIFT
- RADEON_MODELPROJECT_2_SHIFT
- RADEON_MODELPROJECT_3_SHIFT
- RADEON_MODELVIEW_0_SHIFT
- RADEON_MODELVIEW_1_SHIFT
- RADEON_MODELVIEW_2_SHIFT
- RADEON_MODELVIEW_3_SHIFT
- RADEON_MODE_H
- RADEON_MODE_OVERCLOCK_MARGIN
- RADEON_MPLL_CNTL
- RADEON_MPLL_FB_DIV_MASK
- RADEON_MPLL_FB_DIV_SHIFT
- RADEON_MPP_GP_CONFIG
- RADEON_MPP_TB_CONFIG
- RADEON_MSI_REARM_EN
- RADEON_M_SPLL_REF_DIV_MASK
- RADEON_M_SPLL_REF_DIV_SHIFT
- RADEON_M_SPLL_REF_FB_DIV
- RADEON_NB_TOM
- RADEON_NEW_MEMMAP
- RADEON_NONSURF_AP0_SWP_16BPP
- RADEON_NONSURF_AP0_SWP_32BPP
- RADEON_NONSURF_AP1_SWP_16BPP
- RADEON_NONSURF_AP1_SWP_32BPP
- RADEON_NORMALIZE_NORMALS
- RADEON_NORMAL_BLEND_OP_ENABLE
- RADEON_NR_SAREA_CLIPRECTS
- RADEON_NR_TEX_HEAPS
- RADEON_NR_TEX_REGIONS
- RADEON_NUM_RINGS
- RADEON_NUM_SYNCS
- RADEON_NUM_VM
- RADEON_N_VIF_COUNT
- RADEON_OFFSET_ALIGN
- RADEON_OFFSET_MASK
- RADEON_OFFSET_SHIFT
- RADEON_OUTPUT_CSC_BYPASS
- RADEON_OUTPUT_CSC_TVRGB
- RADEON_OUTPUT_CSC_YCBCR601
- RADEON_OUTPUT_CSC_YCBCR709
- RADEON_OV0_AUTO_FLIP_CNTL
- RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE
- RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD
- RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN
- RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN
- RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN
- RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM
- RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD
- RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE
- RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD
- RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT
- RADEON_OV0_BASE_ADDR
- RADEON_OV0_COLOUR_CNTL
- RADEON_OV0_DEINTERLACE_PATTERN
- RADEON_OV0_EXCLUSIVE_HORZ
- RADEON_OV0_EXCLUSIVE_VERT
- RADEON_OV0_FILTER_CNTL
- RADEON_OV0_FLAG_CNTL
- RADEON_OV0_FOUR_TAP_COEF_0
- RADEON_OV0_FOUR_TAP_COEF_1
- RADEON_OV0_FOUR_TAP_COEF_2
- RADEON_OV0_FOUR_TAP_COEF_3
- RADEON_OV0_FOUR_TAP_COEF_4
- RADEON_OV0_GAMMA_000_00F
- RADEON_OV0_GAMMA_010_01F
- RADEON_OV0_GAMMA_020_03F
- RADEON_OV0_GAMMA_040_07F
- RADEON_OV0_GAMMA_080_0BF
- RADEON_OV0_GAMMA_0C0_0FF
- RADEON_OV0_GAMMA_100_13F
- RADEON_OV0_GAMMA_140_17F
- RADEON_OV0_GAMMA_180_1BF
- RADEON_OV0_GAMMA_1C0_1FF
- RADEON_OV0_GAMMA_200_23F
- RADEON_OV0_GAMMA_240_27F
- RADEON_OV0_GAMMA_280_2BF
- RADEON_OV0_GAMMA_2C0_2FF
- RADEON_OV0_GAMMA_300_33F
- RADEON_OV0_GAMMA_340_37F
- RADEON_OV0_GAMMA_380_3BF
- RADEON_OV0_GAMMA_3C0_3FF
- RADEON_OV0_GRAPHICS_KEY_CLR_HIGH
- RADEON_OV0_GRAPHICS_KEY_CLR_LOW
- RADEON_OV0_H_INC
- RADEON_OV0_KEY_CNTL
- RADEON_OV0_LIN_TRANS_A
- RADEON_OV0_LIN_TRANS_B
- RADEON_OV0_LIN_TRANS_C
- RADEON_OV0_LIN_TRANS_D
- RADEON_OV0_LIN_TRANS_E
- RADEON_OV0_LIN_TRANS_F
- RADEON_OV0_P1_BLANK_LINES_AT_TOP
- RADEON_OV0_P1_H_ACCUM_INIT
- RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT
- RADEON_OV0_P1_V_ACCUM_INIT
- RADEON_OV0_P1_V_ACCUM_INIT_MASK
- RADEON_OV0_P1_X_START_END
- RADEON_OV0_P23_BLANK_LINES_AT_TOP
- RADEON_OV0_P23_H_ACCUM_INIT
- RADEON_OV0_P23_V_ACCUM_INIT
- RADEON_OV0_P2_X_START_END
- RADEON_OV0_P3_X_START_END
- RADEON_OV0_REG_LOAD_CNTL
- RADEON_OV0_SCALE_CNTL
- RADEON_OV0_STEP_BY
- RADEON_OV0_TEST
- RADEON_OV0_VIDEO_KEY_CLR_HIGH
- RADEON_OV0_VIDEO_KEY_CLR_LOW
- RADEON_OV0_VID_BUF0_BASE_ADRS
- RADEON_OV0_VID_BUF1_BASE_ADRS
- RADEON_OV0_VID_BUF2_BASE_ADRS
- RADEON_OV0_VID_BUF3_BASE_ADRS
- RADEON_OV0_VID_BUF4_BASE_ADRS
- RADEON_OV0_VID_BUF5_BASE_ADRS
- RADEON_OV0_VID_BUF_PITCH0_VALUE
- RADEON_OV0_VID_BUF_PITCH1_VALUE
- RADEON_OV0_V_INC
- RADEON_OV0_Y_X_END
- RADEON_OV0_Y_X_START
- RADEON_OV1_Y_X_END
- RADEON_OV1_Y_X_START
- RADEON_OVR2_CLR
- RADEON_OVR2_WID_LEFT_RIGHT
- RADEON_OVR2_WID_TOP_BOTTOM
- RADEON_OVR_CLR
- RADEON_OVR_WID_LEFT_RIGHT
- RADEON_OVR_WID_TOP_BOTTOM
- RADEON_P1_ACTIVE_LINES_M1
- RADEON_P1_BLNK_LN_AT_TOP_M1_MASK
- RADEON_P23_ACTIVE_LINES_M1
- RADEON_P23_BLNK_LN_AT_TOP_M1_MASK
- RADEON_P2PLL_ATOMIC_UPDATE_EN
- RADEON_P2PLL_ATOMIC_UPDATE_R
- RADEON_P2PLL_ATOMIC_UPDATE_VSYNC
- RADEON_P2PLL_ATOMIC_UPDATE_W
- RADEON_P2PLL_CNTL
- RADEON_P2PLL_DIV_0
- RADEON_P2PLL_FB0_DIV_MASK
- RADEON_P2PLL_POST0_DIV_MASK
- RADEON_P2PLL_PVG_MASK
- RADEON_P2PLL_PVG_SHIFT
- RADEON_P2PLL_REF_DIV
- RADEON_P2PLL_REF_DIV_MASK
- RADEON_P2PLL_RESET
- RADEON_P2PLL_SLEEP
- RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN
- RADEON_PACKET3_NOP
- RADEON_PACKET_TYPE0
- RADEON_PACKET_TYPE1
- RADEON_PACKET_TYPE2
- RADEON_PACKET_TYPE3
- RADEON_PALETTE_30_DATA
- RADEON_PALETTE_DATA
- RADEON_PALETTE_INDEX
- RADEON_PARAM_CARD_TYPE
- RADEON_PARAM_DEVICE_ID
- RADEON_PARAM_FB_LOCATION
- RADEON_PARAM_GART_BASE
- RADEON_PARAM_GART_BUFFER_OFFSET
- RADEON_PARAM_GART_TEX_HANDLE
- RADEON_PARAM_IRQ_NR
- RADEON_PARAM_LAST_CLEAR
- RADEON_PARAM_LAST_DISPATCH
- RADEON_PARAM_LAST_FRAME
- RADEON_PARAM_NUM_GB_PIPES
- RADEON_PARAM_NUM_Z_PIPES
- RADEON_PARAM_REGISTER_HANDLE
- RADEON_PARAM_SAREA_HANDLE
- RADEON_PARAM_SCRATCH_OFFSET
- RADEON_PARAM_STATUS_HANDLE
- RADEON_PARAM_VBLANK_CRTC
- RADEON_PATTERN_ENABLE
- RADEON_PCIE_DATA
- RADEON_PCIE_GEN1
- RADEON_PCIE_GEN2
- RADEON_PCIE_GEN3
- RADEON_PCIE_GEN_INVALID
- RADEON_PCIE_INDEX
- RADEON_PCIE_LC_LINK_WIDTH_CNTL
- RADEON_PCIE_LC_LINK_WIDTH_MASK
- RADEON_PCIE_LC_LINK_WIDTH_RD_MASK
- RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT
- RADEON_PCIE_LC_LINK_WIDTH_SHIFT
- RADEON_PCIE_LC_LINK_WIDTH_X0
- RADEON_PCIE_LC_LINK_WIDTH_X1
- RADEON_PCIE_LC_LINK_WIDTH_X12
- RADEON_PCIE_LC_LINK_WIDTH_X16
- RADEON_PCIE_LC_LINK_WIDTH_X2
- RADEON_PCIE_LC_LINK_WIDTH_X4
- RADEON_PCIE_LC_LINK_WIDTH_X8
- RADEON_PCIE_LC_RECONFIG_LATER
- RADEON_PCIE_LC_RECONFIG_NOW
- RADEON_PCIE_LC_SHORT_RECONFIG_EN
- RADEON_PCIE_SPEED_25
- RADEON_PCIE_SPEED_50
- RADEON_PCIE_SPEED_80
- RADEON_PCIE_TX_DISCARD_RD_ADDR_HI
- RADEON_PCIE_TX_DISCARD_RD_ADDR_LO
- RADEON_PCIE_TX_GART_BASE
- RADEON_PCIE_TX_GART_CHK_RW_VALID_EN
- RADEON_PCIE_TX_GART_CNTL
- RADEON_PCIE_TX_GART_EN
- RADEON_PCIE_TX_GART_END_HI
- RADEON_PCIE_TX_GART_END_LO
- RADEON_PCIE_TX_GART_ERROR
- RADEON_PCIE_TX_GART_INVALIDATE_TLB
- RADEON_PCIE_TX_GART_MODE_32_128_CACHE
- RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE
- RADEON_PCIE_TX_GART_START_HI
- RADEON_PCIE_TX_GART_START_LO
- RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO
- RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD
- RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU
- RADEON_PCIGART_TRANSLATE_EN
- RADEON_PCI_GART_PAGE
- RADEON_PG_SUPPORT_ACP
- RADEON_PG_SUPPORT_CP
- RADEON_PG_SUPPORT_GDS
- RADEON_PG_SUPPORT_GFX_DMG
- RADEON_PG_SUPPORT_GFX_PG
- RADEON_PG_SUPPORT_GFX_SMG
- RADEON_PG_SUPPORT_RLC_SMU_HS
- RADEON_PG_SUPPORT_SAMU
- RADEON_PG_SUPPORT_SDMA
- RADEON_PG_SUPPORT_UVD
- RADEON_PG_SUPPORT_VCE
- RADEON_PITCH_SHIFT
- RADEON_PIX2CLK_ALWAYS_ONb
- RADEON_PIX2CLK_DAC_ALWAYS_ONb
- RADEON_PIX2CLK_SRC_SEL_BYTECLK
- RADEON_PIX2CLK_SRC_SEL_CPUCLK
- RADEON_PIX2CLK_SRC_SEL_MASK
- RADEON_PIX2CLK_SRC_SEL_P2PLLCLK
- RADEON_PIX2CLK_SRC_SEL_PSCANCLK
- RADEON_PIXCLKS_CNTL
- RADEON_PIXCLK_ALWAYS_ONb
- RADEON_PIXCLK_BLEND_ALWAYS_ONb
- RADEON_PIXCLK_DAC_ALWAYS_ONb
- RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb
- RADEON_PIXCLK_GV_ALWAYS_ONb
- RADEON_PIXCLK_LVDS_ALWAYS_ONb
- RADEON_PIXCLK_TMDS_ALWAYS_ONb
- RADEON_PIXCLK_TV_SRC_SEL
- RADEON_PLANAR_YUV_ENABLE
- RADEON_PLANE_3D_MASK_C
- RADEON_PLANE_MASK_ENABLE
- RADEON_PLL2_DIV_SEL_MASK
- RADEON_PLL_DIV_SEL
- RADEON_PLL_IS_LCD
- RADEON_PLL_LEGACY
- RADEON_PLL_MASK_READ_B
- RADEON_PLL_NO_ODD_POST_DIV
- RADEON_PLL_PREFER_CLOSEST_LOWER
- RADEON_PLL_PREFER_HIGH_FB_DIV
- RADEON_PLL_PREFER_HIGH_POST_DIV
- RADEON_PLL_PREFER_HIGH_REF_DIV
- RADEON_PLL_PREFER_LOW_FB_DIV
- RADEON_PLL_PREFER_LOW_POST_DIV
- RADEON_PLL_PREFER_LOW_REF_DIV
- RADEON_PLL_PREFER_MINM_OVER_MAXP
- RADEON_PLL_PWRMGT_CNTL
- RADEON_PLL_TEST_CNTL
- RADEON_PLL_USE_BIOS_DIVS
- RADEON_PLL_USE_FRAC_FB_DIV
- RADEON_PLL_USE_POST_DIV
- RADEON_PLL_USE_REF_DIV
- RADEON_PLL_WR_EN
- RADEON_PMI_CAP_ID
- RADEON_PMI_DATA
- RADEON_PMI_NXT_CAP_PTR
- RADEON_PMI_PMCSR_REG
- RADEON_PMI_PMC_REG
- RADEON_PMI_REGISTER
- RADEON_PM_MODE_NO_DISPLAY
- RADEON_PM_MODE_SEL
- RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
- RADEON_POINTS
- RADEON_POSITION_BLEND_OP_ENABLE
- RADEON_PPLL_ATOMIC_UPDATE_EN
- RADEON_PPLL_ATOMIC_UPDATE_R
- RADEON_PPLL_ATOMIC_UPDATE_VSYNC
- RADEON_PPLL_ATOMIC_UPDATE_W
- RADEON_PPLL_CNTL
- RADEON_PPLL_DIV_0
- RADEON_PPLL_DIV_1
- RADEON_PPLL_DIV_2
- RADEON_PPLL_DIV_3
- RADEON_PPLL_FB3_DIV_MASK
- RADEON_PPLL_POST3_DIV_MASK
- RADEON_PPLL_PVG_MASK
- RADEON_PPLL_PVG_SHIFT
- RADEON_PPLL_REF_DIV
- RADEON_PPLL_REF_DIV_MASK
- RADEON_PPLL_RESET
- RADEON_PPLL_SLEEP
- RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
- RADEON_PP_BORDER_COLOR_0
- RADEON_PP_BORDER_COLOR_1
- RADEON_PP_BORDER_COLOR_2
- RADEON_PP_CNTL
- RADEON_PP_CUBIC_FACES_0
- RADEON_PP_CUBIC_FACES_1
- RADEON_PP_CUBIC_FACES_2
- RADEON_PP_CUBIC_OFFSET_T0_0
- RADEON_PP_CUBIC_OFFSET_T0_1
- RADEON_PP_CUBIC_OFFSET_T0_2
- RADEON_PP_CUBIC_OFFSET_T0_3
- RADEON_PP_CUBIC_OFFSET_T0_4
- RADEON_PP_CUBIC_OFFSET_T1_0
- RADEON_PP_CUBIC_OFFSET_T1_1
- RADEON_PP_CUBIC_OFFSET_T1_2
- RADEON_PP_CUBIC_OFFSET_T1_3
- RADEON_PP_CUBIC_OFFSET_T1_4
- RADEON_PP_CUBIC_OFFSET_T2_0
- RADEON_PP_CUBIC_OFFSET_T2_1
- RADEON_PP_CUBIC_OFFSET_T2_2
- RADEON_PP_CUBIC_OFFSET_T2_3
- RADEON_PP_CUBIC_OFFSET_T2_4
- RADEON_PP_FOG_COLOR
- RADEON_PP_LUM_MATRIX
- RADEON_PP_MISC
- RADEON_PP_ROT_MATRIX_0
- RADEON_PP_ROT_MATRIX_1
- RADEON_PP_TEX_PITCH_0
- RADEON_PP_TEX_PITCH_1
- RADEON_PP_TEX_PITCH_2
- RADEON_PP_TEX_SIZE_0
- RADEON_PP_TEX_SIZE_1
- RADEON_PP_TEX_SIZE_2
- RADEON_PP_TFACTOR_0
- RADEON_PP_TFACTOR_1
- RADEON_PP_TFACTOR_2
- RADEON_PP_TXABLEND_0
- RADEON_PP_TXABLEND_1
- RADEON_PP_TXABLEND_2
- RADEON_PP_TXCBLEND_0
- RADEON_PP_TXCBLEND_1
- RADEON_PP_TXCBLEND_2
- RADEON_PP_TXFILTER_0
- RADEON_PP_TXFILTER_1
- RADEON_PP_TXFILTER_2
- RADEON_PP_TXFORMAT_0
- RADEON_PP_TXFORMAT_1
- RADEON_PP_TXFORMAT_2
- RADEON_PP_TXOFFSET_0
- RADEON_PP_TXOFFSET_1
- RADEON_PP_TXOFFSET_2
- RADEON_PRE_WRITE_LIMIT_SHIFT
- RADEON_PRE_WRITE_TIMER_SHIFT
- RADEON_PWR_MNGMT_CNTL_STATUS
- RADEON_PX_QUIRK_DISABLE_PX
- RADEON_RB2D_DC_BUSY
- RADEON_RB2D_DC_FLUSH
- RADEON_RB2D_DC_FLUSH_ALL
- RADEON_RB2D_DC_FREE
- RADEON_RB2D_DSTCACHE_CTLSTAT
- RADEON_RB2D_DSTCACHE_MODE
- RADEON_RB3D_BLENDCNTL
- RADEON_RB3D_CNTL
- RADEON_RB3D_COLOROFFSET
- RADEON_RB3D_COLORPITCH
- RADEON_RB3D_COLOR_FORMAT_SHIFT
- RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH
- RADEON_RB3D_DC_2D_CACHE_DISABLE
- RADEON_RB3D_DC_2D_CACHE_LINESIZE_128
- RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH
- RADEON_RB3D_DC_3D_CACHE_DISABLE
- RADEON_RB3D_DC_3D_CACHE_LINESIZE_128
- RADEON_RB3D_DC_BUSY
- RADEON_RB3D_DC_CACHE_DISABLE
- RADEON_RB3D_DC_CACHE_ENABLE
- RADEON_RB3D_DC_DISABLE_RI_FILL
- RADEON_RB3D_DC_DISABLE_RI_READ
- RADEON_RB3D_DC_FLUSH
- RADEON_RB3D_DC_FLUSH_ALL
- RADEON_RB3D_DC_FORCE_RMW
- RADEON_RB3D_DC_FREE
- RADEON_RB3D_DEPTHOFFSET
- RADEON_RB3D_DEPTHPITCH
- RADEON_RB3D_DSTCACHE_CTLSTAT
- RADEON_RB3D_DSTCACHE_MODE
- RADEON_RB3D_PLANEMASK
- RADEON_RB3D_ROPCNTL
- RADEON_RB3D_STENCILREFMASK
- RADEON_RB3D_ZCACHE_CTLSTAT
- RADEON_RB3D_ZCACHE_MODE
- RADEON_RB3D_ZC_FLUSH_ALL
- RADEON_RB3D_ZPASS_ADDR
- RADEON_RB3D_ZPASS_DATA
- RADEON_RB3D_ZSTENCILCNTL
- RADEON_RBBM_ACTIVE
- RADEON_RBBM_CMDFIFO_ADDR
- RADEON_RBBM_CMDFIFO_DATA
- RADEON_RBBM_FIFOCNT_MASK
- RADEON_RBBM_GUICNTL
- RADEON_RBBM_SOFT_RESET
- RADEON_RBBM_STATUS
- RADEON_RB_BLKSZ_MASK
- RADEON_RB_BLKSZ_SHIFT
- RADEON_RB_BUFSZ_MASK
- RADEON_RB_BUFSZ_SHIFT
- RADEON_RB_NO_UPDATE
- RADEON_RB_RPTR_WR_ENA
- RADEON_RECLOCK_DELAY_MS
- RADEON_RED_MX_FORCE_DAC_DATA
- RADEON_REF_ALPHA_MASK
- RADEON_REGPROG_INF
- RADEON_REGSIZE
- RADEON_REG_BASE
- RADEON_REG_LD_CTL_FLIP_READBACK
- RADEON_REG_LD_CTL_LOCK
- RADEON_REG_LD_CTL_LOCK_READBACK
- RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP
- RADEON_REG_LD_CTL_VBLANK_DURING_LOCK
- RADEON_RELOC_PRIO_MASK
- RADEON_REQUIRE_QUIESCENCE
- RADEON_REQ_Y_FIRST
- RADEON_RESCALE_NORMALS
- RADEON_RESET_COMPUTE
- RADEON_RESET_CP
- RADEON_RESET_DISPLAY
- RADEON_RESET_DMA
- RADEON_RESET_DMA1
- RADEON_RESET_GFX
- RADEON_RESET_GRBM
- RADEON_RESET_IH
- RADEON_RESET_MC
- RADEON_RESET_RLC
- RADEON_RESET_SEM
- RADEON_RESET_VMC
- RADEON_RESTART_FIELD
- RADEON_RESTART_PHASE_FIX
- RADEON_REVISION_ID
- RADEON_RE_HEIGHT_SHIFT
- RADEON_RE_LEFT_SHIFT
- RADEON_RE_LINE_PATTERN
- RADEON_RE_LINE_STATE
- RADEON_RE_MISC
- RADEON_RE_SOLID_COLOR
- RADEON_RE_SYNC_NOW_SEL_MASK
- RADEON_RE_TOP_LEFT
- RADEON_RE_TOP_SHIFT
- RADEON_RE_WIDTH_HEIGHT
- RADEON_RE_WIDTH_SHIFT
- RADEON_RGB_ATTEN_SEL
- RADEON_RGB_ATTEN_VAL
- RADEON_RGB_CONVERT_BY_PASS
- RADEON_RGB_DITHER_EN
- RADEON_RGB_SRC_SEL_CRTC1
- RADEON_RGB_SRC_SEL_CRTC2
- RADEON_RGB_SRC_SEL_MASK
- RADEON_RGB_SRC_SEL_RMX
- RADEON_RIGHT_HAND_CUBE_D3D
- RADEON_RIGHT_HAND_CUBE_OGL
- RADEON_RING_TYPE_GFX_INDEX
- RADEON_RNG_BASED_FOG
- RADEON_ROP3_D
- RADEON_ROP3_DPa
- RADEON_ROP3_DPan
- RADEON_ROP3_DPna
- RADEON_ROP3_DPno
- RADEON_ROP3_DPo
- RADEON_ROP3_DPon
- RADEON_ROP3_DPx
- RADEON_ROP3_DSa
- RADEON_ROP3_DSan
- RADEON_ROP3_DSna
- RADEON_ROP3_DSno
- RADEON_ROP3_DSo
- RADEON_ROP3_DSon
- RADEON_ROP3_DSx
- RADEON_ROP3_DSxn
- RADEON_ROP3_Dn
- RADEON_ROP3_ONE
- RADEON_ROP3_P
- RADEON_ROP3_PDna
- RADEON_ROP3_PDno
- RADEON_ROP3_PDxn
- RADEON_ROP3_Pn
- RADEON_ROP3_S
- RADEON_ROP3_SDna
- RADEON_ROP3_SDno
- RADEON_ROP3_Sn
- RADEON_ROP3_ZERO
- RADEON_ROP_AND
- RADEON_ROP_AND_INVERTED
- RADEON_ROP_AND_REVERSE
- RADEON_ROP_CLEAR
- RADEON_ROP_COPY
- RADEON_ROP_COPY_INVERTED
- RADEON_ROP_ENABLE
- RADEON_ROP_EQUIV
- RADEON_ROP_INVERT
- RADEON_ROP_MASK
- RADEON_ROP_NAND
- RADEON_ROP_NOOP
- RADEON_ROP_NOR
- RADEON_ROP_OR
- RADEON_ROP_OR_INVERTED
- RADEON_ROP_OR_REVERSE
- RADEON_ROP_SET
- RADEON_ROP_XOR
- RADEON_ROUND_ENABLE
- RADEON_ROUND_MODE_ROUND
- RADEON_ROUND_MODE_ROUND_EVEN
- RADEON_ROUND_MODE_ROUND_ODD
- RADEON_ROUND_MODE_TRUNC
- RADEON_ROUND_PREC_16TH_PIX
- RADEON_ROUND_PREC_4TH_PIX
- RADEON_ROUND_PREC_8TH_PIX
- RADEON_ROUND_PREC_HALF_PIX
- RADEON_SCALER_ADAPTIVE_DEINT
- RADEON_SCALER_BURST_PER_PLANE
- RADEON_SCALER_COMCORE_SHIFT_UP_ONE
- RADEON_SCALER_CRTC_SEL
- RADEON_SCALER_DIS_LIMIT
- RADEON_SCALER_DOUBLE_BUFFER
- RADEON_SCALER_ENABLE
- RADEON_SCALER_GAMMA_SEL_BRIGHT
- RADEON_SCALER_GAMMA_SEL_G14
- RADEON_SCALER_GAMMA_SEL_G18
- RADEON_SCALER_GAMMA_SEL_G22
- RADEON_SCALER_GAMMA_SEL_MASK
- RADEON_SCALER_HORZ_PICK_NEAREST
- RADEON_SCALER_INT_EMU
- RADEON_SCALER_LIN_TRANS_BYPASS
- RADEON_SCALER_SIGNED_UV
- RADEON_SCALER_SMART_SWITCH
- RADEON_SCALER_SOFT_RESET
- RADEON_SCALER_SOURCE_15BPP
- RADEON_SCALER_SOURCE_16BPP
- RADEON_SCALER_SOURCE_32BPP
- RADEON_SCALER_SOURCE_VYUY422
- RADEON_SCALER_SOURCE_YUV12
- RADEON_SCALER_SOURCE_YUV9
- RADEON_SCALER_SOURCE_YVYU422
- RADEON_SCALER_SURFAC_FORMAT
- RADEON_SCALER_TEMPORAL_DEINT
- RADEON_SCALER_VERT_PICK_NEAREST
- RADEON_SCALE_1X
- RADEON_SCALE_2X
- RADEON_SCALE_4X
- RADEON_SCALE_DITHER_ENABLE
- RADEON_SCALE_MASK
- RADEON_SCALE_SHIFT
- RADEON_SCISSOR_ENABLE
- RADEON_SCK_PRESCALE_MASK
- RADEON_SCK_PRESCALE_SHIFT
- RADEON_SCLK_CNTL
- RADEON_SCLK_DOWN
- RADEON_SCLK_DYN_START_CNTL
- RADEON_SCLK_FORCEON_MASK
- RADEON_SCLK_FORCE_CP
- RADEON_SCLK_FORCE_DISP1
- RADEON_SCLK_FORCE_DISP2
- RADEON_SCLK_FORCE_E2
- RADEON_SCLK_FORCE_HDP
- RADEON_SCLK_FORCE_IDCT
- RADEON_SCLK_FORCE_OV0
- RADEON_SCLK_FORCE_PB
- RADEON_SCLK_FORCE_RB
- RADEON_SCLK_FORCE_RE
- RADEON_SCLK_FORCE_SE
- RADEON_SCLK_FORCE_SUBPIC
- RADEON_SCLK_FORCE_TAM
- RADEON_SCLK_FORCE_TDM
- RADEON_SCLK_FORCE_TOP
- RADEON_SCLK_FORCE_TV_SCLK
- RADEON_SCLK_FORCE_VIP
- RADEON_SCLK_MORE_CNTL
- RADEON_SCLK_MORE_FORCEON
- RADEON_SCLK_MORE_MAX_DYN_STOP_LAT
- RADEON_SCLK_SRC_SEL_MASK
- RADEON_SCLK_UP
- RADEON_SCRATCH_ADDR
- RADEON_SCRATCH_REG0
- RADEON_SCRATCH_REG1
- RADEON_SCRATCH_REG2
- RADEON_SCRATCH_REG3
- RADEON_SCRATCH_REG4
- RADEON_SCRATCH_REG5
- RADEON_SCRATCH_REG_OFFSET
- RADEON_SCRATCH_UMSK
- RADEON_SCREEN_BLANKING
- RADEON_SC_BOTTOM
- RADEON_SC_BOTTOM_RIGHT
- RADEON_SC_BOTTOM_RIGHT_C
- RADEON_SC_LEFT
- RADEON_SC_RIGHT
- RADEON_SC_SIGN_MASK_HI
- RADEON_SC_SIGN_MASK_LO
- RADEON_SC_TOP
- RADEON_SC_TOP_LEFT
- RADEON_SC_TOP_LEFT_C
- RADEON_SDRAM_MODE_MASK
- RADEON_SDRAM_MODE_REG
- RADEON_SEPROM_CNTL1
- RADEON_SEQ8_DATA
- RADEON_SEQ8_IDX
- RADEON_SETPARAM_FB_LOCATION
- RADEON_SETPARAM_NEW_MEMMAP
- RADEON_SETPARAM_PCIGART_LOCATION
- RADEON_SETPARAM_PCIGART_TABLE_SIZE
- RADEON_SETPARAM_SWITCH_TILING
- RADEON_SETPARAM_VBLANK_CRTC
- RADEON_SET_UP_LEVEL_SHIFT
- RADEON_SE_CNTL
- RADEON_SE_CNTL_STATUS
- RADEON_SE_COORD_FMT
- RADEON_SE_LINE_WIDTH
- RADEON_SE_PORT_DATA0
- RADEON_SE_TCL_LIGHT_MODEL_CTL
- RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA
- RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE
- RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN
- RADEON_SE_TCL_MATERIAL_AMBIENT_RED
- RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA
- RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE
- RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN
- RADEON_SE_TCL_MATERIAL_DIFFUSE_RED
- RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA
- RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE
- RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN
- RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED
- RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA
- RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE
- RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN
- RADEON_SE_TCL_MATERIAL_SPECULAR_RED
- RADEON_SE_TCL_MATRIX_SELECT_0
- RADEON_SE_TCL_MATRIX_SELECT_1
- RADEON_SE_TCL_OUTPUT_VTX_FMT
- RADEON_SE_TCL_OUTPUT_VTX_SEL
- RADEON_SE_TCL_PER_LIGHT_CTL_0
- RADEON_SE_TCL_PER_LIGHT_CTL_1
- RADEON_SE_TCL_PER_LIGHT_CTL_2
- RADEON_SE_TCL_PER_LIGHT_CTL_3
- RADEON_SE_TCL_SHININESS
- RADEON_SE_TCL_TEXTURE_PROC_CTL
- RADEON_SE_TCL_UCP_VERT_BLEND_CTL
- RADEON_SE_VF_CNTL
- RADEON_SE_VPORT_XOFFSET
- RADEON_SE_VPORT_XSCALE
- RADEON_SE_VPORT_YOFFSET
- RADEON_SE_VPORT_YSCALE
- RADEON_SE_VPORT_ZOFFSET
- RADEON_SE_VPORT_ZSCALE
- RADEON_SE_VTX_FMT
- RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK
- RADEON_SE_VTX_FMT_FPALPHA
- RADEON_SE_VTX_FMT_FPCOLOR
- RADEON_SE_VTX_FMT_FPFOG
- RADEON_SE_VTX_FMT_FPSPEC
- RADEON_SE_VTX_FMT_N0
- RADEON_SE_VTX_FMT_N1
- RADEON_SE_VTX_FMT_PKCOLOR
- RADEON_SE_VTX_FMT_PKSPEC
- RADEON_SE_VTX_FMT_Q0
- RADEON_SE_VTX_FMT_Q1
- RADEON_SE_VTX_FMT_Q2
- RADEON_SE_VTX_FMT_Q3
- RADEON_SE_VTX_FMT_ST0
- RADEON_SE_VTX_FMT_ST1
- RADEON_SE_VTX_FMT_ST2
- RADEON_SE_VTX_FMT_ST3
- RADEON_SE_VTX_FMT_W0
- RADEON_SE_VTX_FMT_W1
- RADEON_SE_VTX_FMT_XY
- RADEON_SE_VTX_FMT_XY1
- RADEON_SE_VTX_FMT_Z
- RADEON_SE_VTX_FMT_Z1
- RADEON_SE_ZBIAS_CONSTANT
- RADEON_SE_ZBIAS_FACTOR
- RADEON_SHADOW_ENABLE
- RADEON_SHADOW_FUNC_EQUAL
- RADEON_SHADOW_FUNC_NEQUAL
- RADEON_SHADOW_ID_AUTO_INC
- RADEON_SHADOW_PASS_1
- RADEON_SHADOW_PASS_2
- RADEON_SIGNED_ALPHA_MASK
- RADEON_SIGNED_ALPHA_SHIFT
- RADEON_SIGNED_RGB_MASK
- RADEON_SIGNED_RGB_SHIFT
- RADEON_SINGLE_CRTC
- RADEON_SLEW_RATE_LIMIT
- RADEON_SNAPSHOT_F_COUNT
- RADEON_SNAPSHOT_VH_COUNTS
- RADEON_SNAPSHOT_VIF_COUNT
- RADEON_SOFT_RESET_CP
- RADEON_SOFT_RESET_E2
- RADEON_SOFT_RESET_GRPH_PP
- RADEON_SOFT_RESET_HDP
- RADEON_SOFT_RESET_HI
- RADEON_SOFT_RESET_PP
- RADEON_SOFT_RESET_RB
- RADEON_SOFT_RESET_RE
- RADEON_SOFT_RESET_SE
- RADEON_SPECULAR_ENABLE
- RADEON_SPECULAR_LIGHTS
- RADEON_SPECULAR_SHADE_FLAT
- RADEON_SPECULAR_SHADE_GOURAUD
- RADEON_SPECULAR_SHADE_MASK
- RADEON_SPECULAR_SHADE_SOLID
- RADEON_SPECULAR_SOURCE_SHIFT
- RADEON_SPLL_CNTL
- RADEON_SPLL_FB_DIV_MASK
- RADEON_SPLL_FB_DIV_SHIFT
- RADEON_SPLL_PCP_MASK
- RADEON_SPLL_PCP_SHIFT
- RADEON_SPLL_PDC_MASK
- RADEON_SPLL_PDC_SHIFT
- RADEON_SPLL_PVG_MASK
- RADEON_SPLL_PVG_SHIFT
- RADEON_SPLL_RESET
- RADEON_SPLL_SLEEP
- RADEON_SRC_BLEND_GL_DST_ALPHA
- RADEON_SRC_BLEND_GL_DST_COLOR
- RADEON_SRC_BLEND_GL_ONE
- RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA
- RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR
- RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA
- RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR
- RADEON_SRC_BLEND_GL_SRC_ALPHA
- RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE
- RADEON_SRC_BLEND_GL_SRC_COLOR
- RADEON_SRC_BLEND_GL_ZERO
- RADEON_SRC_BLEND_MASK
- RADEON_SRC_CMP_EQ_COLOR
- RADEON_SRC_CMP_NEQ_COLOR
- RADEON_SRC_OFFSET
- RADEON_SRC_PITCH
- RADEON_SRC_PITCH_OFFSET
- RADEON_SRC_SC_BOTTOM
- RADEON_SRC_SC_BOTTOM_RIGHT
- RADEON_SRC_SC_RIGHT
- RADEON_SRC_X
- RADEON_SRC_X_Y
- RADEON_SRC_Y
- RADEON_SRC_Y_X
- RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR
- RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR
- RADEON_SS_LIGHT_DCD_ADDR
- RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR
- RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR
- RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR
- RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR
- RADEON_SS_SHININESS
- RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR
- RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR
- RADEON_STATUS
- RADEON_STATUS_PCI_CONFIG
- RADEON_STENCIL
- RADEON_STENCIL_ENABLE
- RADEON_STENCIL_FAIL_DEC
- RADEON_STENCIL_FAIL_INC
- RADEON_STENCIL_FAIL_INVERT
- RADEON_STENCIL_FAIL_KEEP
- RADEON_STENCIL_FAIL_MASK
- RADEON_STENCIL_FAIL_REPLACE
- RADEON_STENCIL_FAIL_ZERO
- RADEON_STENCIL_MASK_SHIFT
- RADEON_STENCIL_REF_MASK
- RADEON_STENCIL_REF_SHIFT
- RADEON_STENCIL_TEST_ALWAYS
- RADEON_STENCIL_TEST_EQUAL
- RADEON_STENCIL_TEST_GEQUAL
- RADEON_STENCIL_TEST_GREATER
- RADEON_STENCIL_TEST_LEQUAL
- RADEON_STENCIL_TEST_LESS
- RADEON_STENCIL_TEST_MASK
- RADEON_STENCIL_TEST_NEQUAL
- RADEON_STENCIL_TEST_NEVER
- RADEON_STENCIL_VALUE_MASK
- RADEON_STENCIL_WRITEMASK_SHIFT
- RADEON_STENCIL_WRITE_MASK
- RADEON_STENCIL_ZFAIL_DEC
- RADEON_STENCIL_ZFAIL_INC
- RADEON_STENCIL_ZFAIL_INVERT
- RADEON_STENCIL_ZFAIL_KEEP
- RADEON_STENCIL_ZFAIL_MASK
- RADEON_STENCIL_ZFAIL_REPLACE
- RADEON_STENCIL_ZFAIL_ZERO
- RADEON_STENCIL_ZPASS_DEC
- RADEON_STENCIL_ZPASS_INC
- RADEON_STENCIL_ZPASS_INVERT
- RADEON_STENCIL_ZPASS_KEEP
- RADEON_STENCIL_ZPASS_MASK
- RADEON_STENCIL_ZPASS_REPLACE
- RADEON_STENCIL_ZPASS_ZERO
- RADEON_STIPPLE_BIG_BIT_ORDER
- RADEON_STIPPLE_COORD_MASK
- RADEON_STIPPLE_ENABLE
- RADEON_STIPPLE_LITTLE_BIT_ORDER
- RADEON_STIPPLE_X_OFFSET_MASK
- RADEON_STIPPLE_X_OFFSET_SHIFT
- RADEON_STIPPLE_Y_OFFSET_MASK
- RADEON_STIPPLE_Y_OFFSET_SHIFT
- RADEON_SUBPIC_CNTL
- RADEON_SUB_CLASS
- RADEON_SURFACE0_INFO
- RADEON_SURFACE0_LOWER_BOUND
- RADEON_SURFACE0_UPPER_BOUND
- RADEON_SURFACE1_INFO
- RADEON_SURFACE1_LOWER_BOUND
- RADEON_SURFACE1_UPPER_BOUND
- RADEON_SURFACE2_INFO
- RADEON_SURFACE2_LOWER_BOUND
- RADEON_SURFACE2_UPPER_BOUND
- RADEON_SURFACE3_INFO
- RADEON_SURFACE3_LOWER_BOUND
- RADEON_SURFACE3_UPPER_BOUND
- RADEON_SURFACE4_INFO
- RADEON_SURFACE4_LOWER_BOUND
- RADEON_SURFACE4_UPPER_BOUND
- RADEON_SURFACE5_INFO
- RADEON_SURFACE5_LOWER_BOUND
- RADEON_SURFACE5_UPPER_BOUND
- RADEON_SURFACE6_INFO
- RADEON_SURFACE6_LOWER_BOUND
- RADEON_SURFACE6_UPPER_BOUND
- RADEON_SURFACE7_INFO
- RADEON_SURFACE7_LOWER_BOUND
- RADEON_SURFACE7_UPPER_BOUND
- RADEON_SURFACE_CNTL
- RADEON_SURF_AP0_SWP_16BPP
- RADEON_SURF_AP0_SWP_32BPP
- RADEON_SURF_AP1_SWP_16BPP
- RADEON_SURF_AP1_SWP_32BPP
- RADEON_SURF_TILE_COLOR_BOTH
- RADEON_SURF_TILE_COLOR_MACRO
- RADEON_SURF_TILE_DEPTH_16BPP
- RADEON_SURF_TILE_DEPTH_32BPP
- RADEON_SURF_TRANSLATION_DIS
- RADEON_SWITCH_TO_BLUE
- RADEON_SW_CAN_USE_DVI_I2C
- RADEON_SW_DONE_USING_DVI_I2C
- RADEON_SW_INT_ENABLE
- RADEON_SW_INT_FIRE
- RADEON_SW_INT_TEST
- RADEON_SW_INT_TEST_ACK
- RADEON_SW_SEMAPHORE
- RADEON_SW_WANTS_TO_USE_DVI_I2C
- RADEON_SYNC_IN
- RADEON_SYNC_OE
- RADEON_SYNC_OUT
- RADEON_SYNC_PD
- RADEON_SYNC_PUB
- RADEON_SYNC_TIP_LEVEL
- RADEON_SYS_HOTKEY
- RADEON_T0_EQ_TCUR
- RADEON_T1_EQ_TCUR
- RADEON_T2_EQ_TCUR
- RADEON_T3_EQ_TCUR
- RADEON_TABLE1_BOT_ADR_MASK
- RADEON_TABLE1_BOT_ADR_SHIFT
- RADEON_TABLE3_TOP_ADR_MASK
- RADEON_TABLE3_TOP_ADR_SHIFT
- RADEON_TCL_BYPASS
- RADEON_TCL_BYPASS_DISABLE
- RADEON_TCL_COMPUTE_DIFFUSE
- RADEON_TCL_COMPUTE_SPECULAR
- RADEON_TCL_COMPUTE_XYZW
- RADEON_TCL_FOG_DISABLE
- RADEON_TCL_FOG_EXP
- RADEON_TCL_FOG_EXP2
- RADEON_TCL_FOG_LINEAR
- RADEON_TCL_FOG_MASK
- RADEON_TCL_FORCE_INORDER_PROC
- RADEON_TCL_FORCE_NAN_IF_COLOR_NAN
- RADEON_TCL_TEX_0_OUTPUT_SHIFT
- RADEON_TCL_TEX_1_OUTPUT_SHIFT
- RADEON_TCL_TEX_2_OUTPUT_SHIFT
- RADEON_TCL_TEX_3_OUTPUT_SHIFT
- RADEON_TCL_TEX_COMPUTED_TEX_0
- RADEON_TCL_TEX_COMPUTED_TEX_1
- RADEON_TCL_TEX_COMPUTED_TEX_2
- RADEON_TCL_TEX_COMPUTED_TEX_3
- RADEON_TCL_TEX_INPUT_TEX_0
- RADEON_TCL_TEX_INPUT_TEX_1
- RADEON_TCL_TEX_INPUT_TEX_2
- RADEON_TCL_TEX_INPUT_TEX_3
- RADEON_TCL_VTX_FP_ALPHA
- RADEON_TCL_VTX_FP_DIFFUSE
- RADEON_TCL_VTX_FP_FOG
- RADEON_TCL_VTX_FP_SPEC
- RADEON_TCL_VTX_NORM0
- RADEON_TCL_VTX_NORM1
- RADEON_TCL_VTX_PK_DIFFUSE
- RADEON_TCL_VTX_PK_SPEC
- RADEON_TCL_VTX_Q0
- RADEON_TCL_VTX_Q1
- RADEON_TCL_VTX_Q2
- RADEON_TCL_VTX_Q3
- RADEON_TCL_VTX_ST0
- RADEON_TCL_VTX_ST1
- RADEON_TCL_VTX_ST2
- RADEON_TCL_VTX_ST3
- RADEON_TCL_VTX_W0
- RADEON_TCL_VTX_W1
- RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT
- RADEON_TCL_VTX_XY1
- RADEON_TCL_VTX_Z0
- RADEON_TCL_VTX_Z1
- RADEON_TEST_COPY_BLIT
- RADEON_TEST_COPY_DMA
- RADEON_TEST_DEBUG_CNTL
- RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN
- RADEON_TEST_DEBUG_MUX
- RADEON_TEST_DEBUG_OUT
- RADEON_TEX1_W_ROUTING_USE_Q1
- RADEON_TEX1_W_ROUTING_USE_W0
- RADEON_TEXGEN_0_INPUT_SHIFT
- RADEON_TEXGEN_1_INPUT_SHIFT
- RADEON_TEXGEN_2_INPUT_SHIFT
- RADEON_TEXGEN_3_INPUT_SHIFT
- RADEON_TEXGEN_INPUT_EYE
- RADEON_TEXGEN_INPUT_EYE_NORMAL
- RADEON_TEXGEN_INPUT_EYE_NORMALIZED
- RADEON_TEXGEN_INPUT_EYE_REFLECT
- RADEON_TEXGEN_INPUT_MASK
- RADEON_TEXGEN_INPUT_OBJ
- RADEON_TEXGEN_INPUT_TEXCOORD_0
- RADEON_TEXGEN_INPUT_TEXCOORD_1
- RADEON_TEXGEN_INPUT_TEXCOORD_2
- RADEON_TEXGEN_INPUT_TEXCOORD_3
- RADEON_TEXGEN_TEXMAT_0_ENABLE
- RADEON_TEXGEN_TEXMAT_1_ENABLE
- RADEON_TEXGEN_TEXMAT_2_ENABLE
- RADEON_TEXGEN_TEXMAT_3_ENABLE
- RADEON_TEXMAT_0_ENABLE
- RADEON_TEXMAT_0_SHIFT
- RADEON_TEXMAT_1_ENABLE
- RADEON_TEXMAT_1_SHIFT
- RADEON_TEXMAT_2_ENABLE
- RADEON_TEXMAT_2_SHIFT
- RADEON_TEXMAT_3_ENABLE
- RADEON_TEXMAT_3_SHIFT
- RADEON_TEX_0_ENABLE
- RADEON_TEX_1_ENABLE
- RADEON_TEX_2_ENABLE
- RADEON_TEX_3D_ENABLE_0
- RADEON_TEX_3D_ENABLE_1
- RADEON_TEX_3_ENABLE
- RADEON_TEX_BLEND_0_ENABLE
- RADEON_TEX_BLEND_1_ENABLE
- RADEON_TEX_BLEND_2_ENABLE
- RADEON_TEX_BLEND_3_ENABLE
- RADEON_TEX_BLEND_ENABLE_MASK
- RADEON_TEX_ENABLE_MASK
- RADEON_TEX_USIZE_MASK
- RADEON_TEX_USIZE_SHIFT
- RADEON_TEX_VSIZE_MASK
- RADEON_TEX_VSIZE_SHIFT
- RADEON_TILING_EG_BANKH_MASK
- RADEON_TILING_EG_BANKH_SHIFT
- RADEON_TILING_EG_BANKW_MASK
- RADEON_TILING_EG_BANKW_SHIFT
- RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK
- RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT
- RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK
- RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT
- RADEON_TILING_EG_TILE_SPLIT_MASK
- RADEON_TILING_EG_TILE_SPLIT_SHIFT
- RADEON_TILING_MACRO
- RADEON_TILING_MICRO
- RADEON_TILING_MICRO_SQUARE
- RADEON_TILING_SURFACE
- RADEON_TILING_SWAP_16BIT
- RADEON_TILING_SWAP_32BIT
- RADEON_TMDS_PLL_CNTL
- RADEON_TMDS_TRANSMITTER_CNTL
- RADEON_TMDS_TRANSMITTER_PLLEN
- RADEON_TMDS_TRANSMITTER_PLLRST
- RADEON_TRAIL_BRES_DEC
- RADEON_TRAIL_BRES_ERR
- RADEON_TRAIL_BRES_INC
- RADEON_TRAIL_X
- RADEON_TRAIL_X_SUB
- RADEON_TRIANGLES
- RADEON_TRIANGLE_FAN
- RADEON_TRIANGLE_STRIP
- RADEON_TV1_ATTACHED_COMP
- RADEON_TV1_ATTACHED_MASK
- RADEON_TV1_ATTACHED_SVIDEO
- RADEON_TV1_CRTC_MASK
- RADEON_TV1_CRTC_SHIFT
- RADEON_TV1_ON
- RADEON_TVCLK_ALWAYS_ONb
- RADEON_TVCLK_SRC_SEL_TVPLL
- RADEON_TVCLK_TURNOFF
- RADEON_TVOUT_SCALE_EN
- RADEON_TVPCP_MASK
- RADEON_TVPCP_SHIFT
- RADEON_TVPDC_MASK
- RADEON_TVPDC_SHIFT
- RADEON_TVPLL_PWRMGT_OFF
- RADEON_TVPLL_REFCLK_SEL
- RADEON_TVPLL_RESET
- RADEON_TVPLL_SLEEP
- RADEON_TVPLL_TEST_DIS
- RADEON_TVPVG_MASK
- RADEON_TVPVG_SHIFT
- RADEON_TV_ASYNC_RST
- RADEON_TV_CRC_CNTL
- RADEON_TV_DAC_BDACDET
- RADEON_TV_DAC_BDACPD
- RADEON_TV_DAC_BGADJ_MASK
- RADEON_TV_DAC_BGADJ_SHIFT
- RADEON_TV_DAC_BGSLEEP
- RADEON_TV_DAC_CMPOUT
- RADEON_TV_DAC_CNTL
- RADEON_TV_DAC_DACADJ_MASK
- RADEON_TV_DAC_DACADJ_SHIFT
- RADEON_TV_DAC_GDACDET
- RADEON_TV_DAC_GDACPD
- RADEON_TV_DAC_NBLANK
- RADEON_TV_DAC_NHOLD
- RADEON_TV_DAC_PEDESTAL
- RADEON_TV_DAC_RDACDET
- RADEON_TV_DAC_RDACPD
- RADEON_TV_DAC_STD_MASK
- RADEON_TV_DAC_STD_NTSC
- RADEON_TV_DAC_STD_PAL
- RADEON_TV_DAC_STD_PS2
- RADEON_TV_DAC_STD_RS343
- RADEON_TV_DPMS_ON
- RADEON_TV_DTO_EN
- RADEON_TV_ENABLE_RST
- RADEON_TV_FCOUNT
- RADEON_TV_FIFO_ASYNC_RST
- RADEON_TV_FIFO_CE_EN
- RADEON_TV_FORCE_DAC_DATA_SHIFT
- RADEON_TV_FRESTART
- RADEON_TV_FTOTAL
- RADEON_TV_GAIN_LIMIT_SETTINGS
- RADEON_TV_HCOUNT
- RADEON_TV_HDISP
- RADEON_TV_HOST_RD_WT_CNTL
- RADEON_TV_HOST_READ_DATA
- RADEON_TV_HOST_WRITE_DATA
- RADEON_TV_HRESTART
- RADEON_TV_HSTART
- RADEON_TV_HTOTAL
- RADEON_TV_LINEAR_GAIN_SETTINGS
- RADEON_TV_M0HI_MASK
- RADEON_TV_M0HI_SHIFT
- RADEON_TV_M0LO_MASK
- RADEON_TV_MASTER_CNTL
- RADEON_TV_MAX_FIFO_ADDR
- RADEON_TV_MAX_FIFO_ADDR_INTERNAL
- RADEON_TV_MODULATOR_CNTL1
- RADEON_TV_MODULATOR_CNTL2
- RADEON_TV_MONITOR_DETECT_EN
- RADEON_TV_N0HI_MASK
- RADEON_TV_N0HI_SHIFT
- RADEON_TV_N0LO_MASK
- RADEON_TV_N0LO_SHIFT
- RADEON_TV_ON
- RADEON_TV_PLL_CNTL
- RADEON_TV_PLL_CNTL1
- RADEON_TV_PLL_FINE_CNTL
- RADEON_TV_PRE_DAC_MUX_CNTL
- RADEON_TV_P_MASK
- RADEON_TV_P_SHIFT
- RADEON_TV_RGB_CNTL
- RADEON_TV_SLIP_EN
- RADEON_TV_SYNC_CNTL
- RADEON_TV_SYNC_IO_DRIVE
- RADEON_TV_TIMING_CNTL
- RADEON_TV_UPSAMP_AND_GAIN_CNTL
- RADEON_TV_UV_ADR
- RADEON_TV_U_BURST_LEVEL_MASK
- RADEON_TV_VCOUNT
- RADEON_TV_VDISP
- RADEON_TV_VRESTART
- RADEON_TV_VSCALER_CNTL1
- RADEON_TV_VSCALER_CNTL2
- RADEON_TV_VTOTAL
- RADEON_TV_V_BURST_LEVEL_MASK
- RADEON_TV_V_BURST_LEVEL_SHIFT
- RADEON_TV_Y_FALL_CNTL
- RADEON_TV_Y_RISE_CNTL
- RADEON_TV_Y_SAW_TOOTH_CNTL
- RADEON_TXFORMAT_AI88
- RADEON_TXFORMAT_ALPHA_IN_MAP
- RADEON_TXFORMAT_ALPHA_MASK_ENABLE
- RADEON_TXFORMAT_APPLE_YUV_MODE
- RADEON_TXFORMAT_ARGB1555
- RADEON_TXFORMAT_ARGB4444
- RADEON_TXFORMAT_ARGB8888
- RADEON_TXFORMAT_CHROMA_KEY_ENABLE
- RADEON_TXFORMAT_CUBIC_MAP_ENABLE
- RADEON_TXFORMAT_DUDV88
- RADEON_TXFORMAT_DXT1
- RADEON_TXFORMAT_DXT23
- RADEON_TXFORMAT_DXT45
- RADEON_TXFORMAT_ENDIAN_16BPP_SWAP
- RADEON_TXFORMAT_ENDIAN_32BPP_SWAP
- RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP
- RADEON_TXFORMAT_ENDIAN_NO_SWAP
- RADEON_TXFORMAT_F5_HEIGHT_MASK
- RADEON_TXFORMAT_F5_HEIGHT_SHIFT
- RADEON_TXFORMAT_F5_WIDTH_MASK
- RADEON_TXFORMAT_F5_WIDTH_SHIFT
- RADEON_TXFORMAT_FORMAT_MASK
- RADEON_TXFORMAT_FORMAT_SHIFT
- RADEON_TXFORMAT_HEIGHT_MASK
- RADEON_TXFORMAT_HEIGHT_SHIFT
- RADEON_TXFORMAT_I8
- RADEON_TXFORMAT_LDUDUV8888
- RADEON_TXFORMAT_LDUDV655
- RADEON_TXFORMAT_NON_POWER2
- RADEON_TXFORMAT_PERSPECTIVE_ENABLE
- RADEON_TXFORMAT_RGB332
- RADEON_TXFORMAT_RGB565
- RADEON_TXFORMAT_RGBA8888
- RADEON_TXFORMAT_SHADOW16
- RADEON_TXFORMAT_SHADOW32
- RADEON_TXFORMAT_ST_ROUTE_MASK
- RADEON_TXFORMAT_ST_ROUTE_STQ0
- RADEON_TXFORMAT_ST_ROUTE_STQ1
- RADEON_TXFORMAT_ST_ROUTE_STQ2
- RADEON_TXFORMAT_VYUY422
- RADEON_TXFORMAT_WIDTH_MASK
- RADEON_TXFORMAT_WIDTH_SHIFT
- RADEON_TXFORMAT_Y8
- RADEON_TXFORMAT_YVYU422
- RADEON_TXO_ENDIAN_BYTE_SWAP
- RADEON_TXO_ENDIAN_HALFDW_SWAP
- RADEON_TXO_ENDIAN_NO_SWAP
- RADEON_TXO_ENDIAN_WORD_SWAP
- RADEON_TXO_MACRO_LINEAR
- RADEON_TXO_MACRO_TILE
- RADEON_TXO_MICRO_LINEAR
- RADEON_TXO_MICRO_TILE_OPT
- RADEON_TXO_MICRO_TILE_X2
- RADEON_TXO_OFFSET_MASK
- RADEON_TXO_OFFSET_SHIFT
- RADEON_UCP_ENABLE_0
- RADEON_UCP_ENABLE_1
- RADEON_UCP_ENABLE_2
- RADEON_UCP_ENABLE_3
- RADEON_UCP_ENABLE_4
- RADEON_UCP_ENABLE_5
- RADEON_UCP_IN_CLIP_SPACE
- RADEON_UCP_IN_MODEL_SPACE
- RADEON_UPLOAD_ALL
- RADEON_UPLOAD_BUMPMAP
- RADEON_UPLOAD_CLIPRECTS
- RADEON_UPLOAD_CONTEXT
- RADEON_UPLOAD_CONTEXT_ALL
- RADEON_UPLOAD_LINE
- RADEON_UPLOAD_MASKS
- RADEON_UPLOAD_MISC
- RADEON_UPLOAD_SETUP
- RADEON_UPLOAD_TCL
- RADEON_UPLOAD_TEX0
- RADEON_UPLOAD_TEX0IMAGES
- RADEON_UPLOAD_TEX1
- RADEON_UPLOAD_TEX1IMAGES
- RADEON_UPLOAD_TEX2
- RADEON_UPLOAD_TEX2IMAGES
- RADEON_UPLOAD_VERTFMT
- RADEON_UPLOAD_VIEWPORT
- RADEON_UPLOAD_ZBIAS
- RADEON_USEC_IB_TEST_TIMEOUT
- RADEON_USE_COMP_ZBUF
- RADEON_USE_HIERZ
- RADEON_UVD_HEAP_SIZE
- RADEON_UVD_SESSION_SIZE
- RADEON_UVD_STACK_SIZE
- RADEON_UVFLT_EN
- RADEON_UVRAM_READ_MARGIN_SHIFT
- RADEON_UVUPSAMP_EN
- RADEON_UV_GAIN_LIMIT_SHIFT
- RADEON_UV_GAIN_SHIFT
- RADEON_UV_INC_MASK
- RADEON_UV_INC_SHIFT
- RADEON_UV_OUTPUT_DITHER_EN
- RADEON_UV_OUTPUT_POST_SCALE_SHIFT
- RADEON_UV_POST_SCALE_BYPASS
- RADEON_UV_TO_BUF_DITHER_EN
- RADEON_VA_IB_OFFSET
- RADEON_VA_MAP
- RADEON_VA_RESERVED_SIZE
- RADEON_VA_RESULT_ERROR
- RADEON_VA_RESULT_OK
- RADEON_VA_RESULT_VA_EXIST
- RADEON_VA_UNMAP
- RADEON_VCE_LEVEL_AC_ALL
- RADEON_VCE_LEVEL_DC_EE
- RADEON_VCE_LEVEL_DC_GP_HIGH
- RADEON_VCE_LEVEL_DC_GP_LOW
- RADEON_VCE_LEVEL_DC_LL_HIGH
- RADEON_VCE_LEVEL_DC_LL_LOW
- RADEON_VCLK_ECP_CNTL
- RADEON_VCLK_SRC_SEL_BYTECLK
- RADEON_VCLK_SRC_SEL_CPUCLK
- RADEON_VCLK_SRC_SEL_MASK
- RADEON_VCLK_SRC_SEL_PPLLCLK
- RADEON_VCLK_SRC_SEL_PSCANCLK
- RADEON_VCODE_TABLE_SEL_MASK
- RADEON_VCODE_TABLE_SEL_SHIFT
- RADEON_VC_16BIT_SWAP
- RADEON_VC_32BIT_SWAP
- RADEON_VC_HALF_DWORD_SWAP
- RADEON_VC_NO_SWAP
- RADEON_VENDOR_ID
- RADEON_VERSION
- RADEON_VERTEX_BLEND_SRC_0_PRIMARY
- RADEON_VERTEX_BLEND_SRC_0_SECONDARY
- RADEON_VERTEX_BLEND_SRC_1_PRIMARY
- RADEON_VERTEX_BLEND_SRC_1_SECONDARY
- RADEON_VERTEX_BLEND_SRC_2_PRIMARY
- RADEON_VERTEX_BLEND_SRC_2_SECONDARY
- RADEON_VERTEX_BLEND_SRC_3_PRIMARY
- RADEON_VERTEX_BLEND_SRC_3_SECONDARY
- RADEON_VERTEX_BLEND_WGT_MINUS_ONE
- RADEON_VERT_AUTO_RATIO_EN
- RADEON_VERT_AUTO_RATIO_INC
- RADEON_VERT_PANEL_SHIFT
- RADEON_VERT_PANEL_SIZE
- RADEON_VERT_STRETCH_BLEND
- RADEON_VERT_STRETCH_ENABLE
- RADEON_VERT_STRETCH_LINEREP
- RADEON_VERT_STRETCH_RATIO_MASK
- RADEON_VERT_STRETCH_RATIO_MAX
- RADEON_VERT_STRETCH_RATIO_SHIFT
- RADEON_VERT_STRETCH_RESERVED
- RADEON_VF_COLOR_ORDER_RGBA
- RADEON_VF_INDEX_SIZE_SHIFT
- RADEON_VF_NUM_VERTICES_SHIFT
- RADEON_VF_PRIM_TYPE_LINE_LIST
- RADEON_VF_PRIM_TYPE_LINE_LIST_3
- RADEON_VF_PRIM_TYPE_LINE_LOOP
- RADEON_VF_PRIM_TYPE_LINE_STRIP
- RADEON_VF_PRIM_TYPE_POINT_LIST
- RADEON_VF_PRIM_TYPE_POINT_LIST_3
- RADEON_VF_PRIM_TYPE_POLYGON
- RADEON_VF_PRIM_TYPE_QUAD_LIST
- RADEON_VF_PRIM_TYPE_QUAD_STRIP
- RADEON_VF_PRIM_TYPE_RECTANGLE_LIST
- RADEON_VF_PRIM_TYPE_SPIRIT_LIST
- RADEON_VF_PRIM_TYPE_TRIANGLE_FAN
- RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG
- RADEON_VF_PRIM_TYPE_TRIANGLE_LIST
- RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP
- RADEON_VF_PRIM_WALK_DATA
- RADEON_VF_PRIM_WALK_INDEX
- RADEON_VF_PRIM_WALK_LIST
- RADEON_VF_PRIM_WALK_STATE
- RADEON_VF_PROG_STREAM_ENA
- RADEON_VF_RADEON_MODE
- RADEON_VF_TCL_OUTPUT_CTL_ENA
- RADEON_VGA_ATI_LINEAR
- RADEON_VGA_DDA_CONFIG
- RADEON_VGA_DDA_ON_OFF
- RADEON_VIDEOMUX_CNTL
- RADEON_VIDEO_KEY_FN_EQ
- RADEON_VIDEO_KEY_FN_FALSE
- RADEON_VIDEO_KEY_FN_MASK
- RADEON_VIDEO_KEY_FN_NE
- RADEON_VIDEO_KEY_FN_TRUE
- RADEON_VID_BUFFER_CONTROL
- RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK
- RADEON_VIF_BUF0_BASE_ADRS_MASK
- RADEON_VIF_BUF0_PITCH_SEL
- RADEON_VIF_BUF0_TILE_ADRS
- RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK
- RADEON_VIF_BUF1_BASE_ADRS_MASK
- RADEON_VIF_BUF1_PITCH_SEL
- RADEON_VIF_BUF1_TILE_ADRS
- RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK
- RADEON_VIF_BUF2_BASE_ADRS_MASK
- RADEON_VIF_BUF2_PITCH_SEL
- RADEON_VIF_BUF2_TILE_ADRS
- RADEON_VIN_ASYNC_RST
- RADEON_VIPH_BM_CHUNK
- RADEON_VIPH_CH0_ABCNT
- RADEON_VIPH_CH0_ADDR
- RADEON_VIPH_CH0_DATA
- RADEON_VIPH_CH0_SBCNT
- RADEON_VIPH_CH1_ABCNT
- RADEON_VIPH_CH1_ADDR
- RADEON_VIPH_CH1_DATA
- RADEON_VIPH_CH1_SBCNT
- RADEON_VIPH_CH2_ABCNT
- RADEON_VIPH_CH2_ADDR
- RADEON_VIPH_CH2_DATA
- RADEON_VIPH_CH2_SBCNT
- RADEON_VIPH_CH3_ABCNT
- RADEON_VIPH_CH3_ADDR
- RADEON_VIPH_CH3_DATA
- RADEON_VIPH_CH3_SBCNT
- RADEON_VIPH_CONTROL
- RADEON_VIPH_DV_INT
- RADEON_VIPH_DV_LAT
- RADEON_VIPH_EN
- RADEON_VIPH_REG_ADDR
- RADEON_VIPH_REG_DATA
- RADEON_VIPH_TIMEOUT_STAT
- RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS
- RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK
- RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT
- RADEON_VIP_BUSY
- RADEON_VIP_IDLE
- RADEON_VIP_RESET
- RADEON_VLINE_STAT
- RADEON_VM_PAGE_READABLE
- RADEON_VM_PAGE_SNOOPED
- RADEON_VM_PAGE_SYSTEM
- RADEON_VM_PAGE_VALID
- RADEON_VM_PAGE_WRITEABLE
- RADEON_VM_PTB_ALIGN
- RADEON_VM_PTB_ALIGN_MASK
- RADEON_VM_PTB_ALIGN_SIZE
- RADEON_VM_PTE_COUNT
- RADEON_VPORT_XY_XFORM_ENABLE
- RADEON_VPORT_Z_XFORM_ENABLE
- RADEON_VS_EYE_VECTOR_ADDR
- RADEON_VS_FOG_PARAM_ADDR
- RADEON_VS_GLOBAL_AMBIENT_ADDR
- RADEON_VS_LIGHT_AMBIENT_ADDR
- RADEON_VS_LIGHT_ATTENUATION_ADDR
- RADEON_VS_LIGHT_DIFFUSE_ADDR
- RADEON_VS_LIGHT_DIRPOS_ADDR
- RADEON_VS_LIGHT_HWVSPOT_ADDR
- RADEON_VS_LIGHT_SPECULAR_ADDR
- RADEON_VS_MATRIX_0_ADDR
- RADEON_VS_MATRIX_10_ADDR
- RADEON_VS_MATRIX_11_ADDR
- RADEON_VS_MATRIX_12_ADDR
- RADEON_VS_MATRIX_13_ADDR
- RADEON_VS_MATRIX_14_ADDR
- RADEON_VS_MATRIX_15_ADDR
- RADEON_VS_MATRIX_1_ADDR
- RADEON_VS_MATRIX_2_ADDR
- RADEON_VS_MATRIX_3_ADDR
- RADEON_VS_MATRIX_4_ADDR
- RADEON_VS_MATRIX_5_ADDR
- RADEON_VS_MATRIX_6_ADDR
- RADEON_VS_MATRIX_7_ADDR
- RADEON_VS_MATRIX_8_ADDR
- RADEON_VS_MATRIX_9_ADDR
- RADEON_VS_MATRIX_EYE2CLIP_ADDR
- RADEON_VS_UCP_ADDR
- RADEON_VTX_PIX_CENTER_D3D
- RADEON_VTX_PIX_CENTER_OGL
- RADEON_VTX_ST0_NONPARAMETRIC
- RADEON_VTX_ST0_PRE_MULT_1_OVER_W0
- RADEON_VTX_ST1_NONPARAMETRIC
- RADEON_VTX_ST1_PRE_MULT_1_OVER_W0
- RADEON_VTX_ST2_NONPARAMETRIC
- RADEON_VTX_ST2_PRE_MULT_1_OVER_W0
- RADEON_VTX_ST3_NONPARAMETRIC
- RADEON_VTX_ST3_PRE_MULT_1_OVER_W0
- RADEON_VTX_W0_IS_NOT_1_OVER_W0
- RADEON_VTX_W0_NORMALIZE
- RADEON_VTX_XY_PRE_MULT_1_OVER_W0
- RADEON_VTX_Z_PRE_MULT_1_OVER_W0
- RADEON_WAIT_2D
- RADEON_WAIT_2D_IDLE
- RADEON_WAIT_2D_IDLECLEAN
- RADEON_WAIT_3D
- RADEON_WAIT_3D_IDLE
- RADEON_WAIT_3D_IDLECLEAN
- RADEON_WAIT_AGP_FLUSH
- RADEON_WAIT_BOTH_CRTC_PFLIP
- RADEON_WAIT_CMDFIFO
- RADEON_WAIT_CRTC_PFLIP
- RADEON_WAIT_CRTC_VLINE
- RADEON_WAIT_DMA_GUI_IDLE
- RADEON_WAIT_DMA_VID_IDLE
- RADEON_WAIT_FE_CRTC_VLINE
- RADEON_WAIT_HOST_IDLECLEAN
- RADEON_WAIT_IDLE_TIMEOUT
- RADEON_WAIT_OV0_FLIP
- RADEON_WAIT_RE_CRTC_VLINE
- RADEON_WAIT_UNTIL
- RADEON_WAIT_VAP_IDLE
- RADEON_WAIT_VBLANK_TIMEOUT
- RADEON_WB_CP1_RPTR_OFFSET
- RADEON_WB_CP2_RPTR_OFFSET
- RADEON_WB_CP_RPTR_OFFSET
- RADEON_WB_RING0_NEXT_RPTR
- RADEON_WB_SCRATCH_OFFSET
- RADEON_WIDELINE_ENABLE
- RADEON_WRAPEN_S
- RADEON_WRAPEN_T
- RADEON_XCLK_CNTL
- RADEON_XCRT_CNT_EN
- RADEON_XDLL_CNTL
- RADEON_XPLL_CNTL
- RADEON_X_MPLL_REF_FB_DIV
- RADEON_YFLT_EN
- RADEON_YUPSAMP_EN
- RADEON_YUV_TEMPERATURE_COOL
- RADEON_YUV_TEMPERATURE_HOT
- RADEON_YUV_TEMPERATURE_MASK
- RADEON_YUV_TO_RGB
- RADEON_Y_COEF_EN
- RADEON_Y_DEL_W_SIG_SHIFT
- RADEON_Y_FALL_PING_PONG
- RADEON_Y_GAIN_LIMIT_SHIFT
- RADEON_Y_GAIN_SHIFT
- RADEON_Y_OUTPUT_DITHER_EN
- RADEON_Y_RED_EN
- RADEON_Y_RISE_PING_PONG
- RADEON_Y_W_EN
- RADEON_ZBIAS_ENABLE_LINE
- RADEON_ZBIAS_ENABLE_POINT
- RADEON_ZBIAS_ENABLE_TRI
- RADEON_Z_COMPRESSION_ENABLE
- RADEON_Z_ENABLE
- RADEON_Z_TEST_ALWAYS
- RADEON_Z_TEST_EQUAL
- RADEON_Z_TEST_GEQUAL
- RADEON_Z_TEST_GREATER
- RADEON_Z_TEST_LEQUAL
- RADEON_Z_TEST_LESS
- RADEON_Z_TEST_MASK
- RADEON_Z_TEST_NEQUAL
- RADEON_Z_TEST_NEVER
- RADEON_Z_WRITE_ENABLE
- RADIOA_1T
- RADIOA_1TARRAYLENGTH
- RADIOA_1T_ARRAYLENGTH
- RADIOA_2T
- RADIOA_2TARRAYLENGTH
- RADIOA_2T_ARRAYLENGTH
- RADIOA_2T_INT_PA_ARRAYLENGTH
- RADIOB_1T
- RADIOB_1TARRAYLENGTH
- RADIOB_2T
- RADIOB_2TARRAYLENGTH
- RADIOB_2T_ARRAYLENGTH
- RADIOB_2T_INT_PA_ARRAYLENGTH
- RADIOB_ARRAYLENGTH
- RADIOB_GM_ARRAYLENGTH
- RADIOPWR_OVERRIDE_DEF
- RADIOREGS
- RADIOREGS3
- RADIOREGS7
- RADIOREGS7_2G
- RADIOSHACK_PRODUCT_ID
- RADIOSHACK_VENDOR_ID
- RADIOTYPE_802_11
- RADIOTYPE_DEFAULT
- RADIOTYPE_LEGACY
- RADIO_2055_CAL_COUNTER_OUT
- RADIO_2055_CAL_COUNTER_OUT2
- RADIO_2055_CAL_CVAR_CNTRL
- RADIO_2055_CAL_LPO_CNTRL
- RADIO_2055_CAL_LPO_ENABLE
- RADIO_2055_CAL_MISC
- RADIO_2055_CAL_RCAL_READ_TS
- RADIO_2055_CAL_RCCAL_READ_TS
- RADIO_2055_CAL_RVAR_CNTRL
- RADIO_2055_CAL_TS
- RADIO_2055_CORE1_B0_NBRSSI_VCM
- RADIO_2055_CORE1_GEN_SPARE2
- RADIO_2055_CORE1_LGBUF_A_IDAC
- RADIO_2055_CORE1_LGBUF_A_TUNE
- RADIO_2055_CORE1_LGBUF_DIV
- RADIO_2055_CORE1_LGBUF_G_IDAC
- RADIO_2055_CORE1_LGBUF_G_TUNE
- RADIO_2055_CORE1_LGBUF_IDACFIL_OVR
- RADIO_2055_CORE1_LGBUF_SPARE
- RADIO_2055_CORE1_LNA_GAINBST
- RADIO_2055_CORE1_RXBB_BUFI_LPFCMP
- RADIO_2055_CORE1_RXBB_BUFO_CTRL
- RADIO_2055_CORE1_RXBB_LPF
- RADIO_2055_CORE1_RXBB_MIDAC_HIPAS
- RADIO_2055_CORE1_RXBB_RCCAL_CTRL
- RADIO_2055_CORE1_RXBB_REGULATOR
- RADIO_2055_CORE1_RXBB_RSSI_CTRL1
- RADIO_2055_CORE1_RXBB_RSSI_CTRL2
- RADIO_2055_CORE1_RXBB_RSSI_CTRL3
- RADIO_2055_CORE1_RXBB_RSSI_CTRL4
- RADIO_2055_CORE1_RXBB_RSSI_CTRL5
- RADIO_2055_CORE1_RXBB_SPARE1
- RADIO_2055_CORE1_RXBB_VGA1_IDAC
- RADIO_2055_CORE1_RXBB_VGA2_IDAC
- RADIO_2055_CORE1_RXBB_VGA3_IDAC
- RADIO_2055_CORE1_RXRF_RCAL
- RADIO_2055_CORE1_RXRF_REG1
- RADIO_2055_CORE1_RXRF_REG2
- RADIO_2055_CORE1_RXRF_SPC1
- RADIO_2055_CORE1_RXTXBB_RCAL
- RADIO_2055_CORE1_TXBB_LPF1
- RADIO_2055_CORE1_TXBB_RCCAL_CTRL
- RADIO_2055_CORE1_TXRF_CNTR_PAD1
- RADIO_2055_CORE1_TXRF_CNTR_PGA1
- RADIO_2055_CORE1_TXRF_IQCAL1
- RADIO_2055_CORE1_TXRF_IQCAL2
- RADIO_2055_CORE1_TXRF_PAD_TSSI1
- RADIO_2055_CORE1_TXRF_PAD_TSSI2
- RADIO_2055_CORE1_TXRF_RCAL
- RADIO_2055_CORE1_TXRF_SGM_PAD
- RADIO_2055_CORE1_TXRF_SGM_PGA
- RADIO_2055_CORE1_TX_BB_MXGM
- RADIO_2055_CORE1_TX_LPF_MXGM_IDAC
- RADIO_2055_CORE1_TX_MX_BGTRIM
- RADIO_2055_CORE1_TX_PAD_IDAC1
- RADIO_2055_CORE1_TX_PAD_IDAC2
- RADIO_2055_CORE1_TX_PGA_PAD_TN
- RADIO_2055_CORE1_TX_RFPGA_IDAC
- RADIO_2055_CORE1_TX_RF_SPARE
- RADIO_2055_CORE1_TX_VOS_CNCL
- RADIO_2055_CORE2_B0_NBRSSI_VCM
- RADIO_2055_CORE2_GEN_SPARE2
- RADIO_2055_CORE2_LGBUF_A_IDAC
- RADIO_2055_CORE2_LGBUF_A_TUNE
- RADIO_2055_CORE2_LGBUF_DIV
- RADIO_2055_CORE2_LGBUF_G_IDAC
- RADIO_2055_CORE2_LGBUF_G_TUNE
- RADIO_2055_CORE2_LGBUF_IDACFIL_OVR
- RADIO_2055_CORE2_LGBUF_SPARE
- RADIO_2055_CORE2_LNA_GAINBST
- RADIO_2055_CORE2_RXBB_BUFI_LPFCMP
- RADIO_2055_CORE2_RXBB_BUFO_CTRL
- RADIO_2055_CORE2_RXBB_LPF
- RADIO_2055_CORE2_RXBB_MIDAC_HIPAS
- RADIO_2055_CORE2_RXBB_RCCAL_CTRL
- RADIO_2055_CORE2_RXBB_REGULATOR
- RADIO_2055_CORE2_RXBB_RSSI_CTRL1
- RADIO_2055_CORE2_RXBB_RSSI_CTRL2
- RADIO_2055_CORE2_RXBB_RSSI_CTRL3
- RADIO_2055_CORE2_RXBB_RSSI_CTRL4
- RADIO_2055_CORE2_RXBB_RSSI_CTRL5
- RADIO_2055_CORE2_RXBB_SPARE1
- RADIO_2055_CORE2_RXBB_VGA1_IDAC
- RADIO_2055_CORE2_RXBB_VGA2_IDAC
- RADIO_2055_CORE2_RXBB_VGA3_IDAC
- RADIO_2055_CORE2_RXRF_RCAL
- RADIO_2055_CORE2_RXRF_REG1
- RADIO_2055_CORE2_RXRF_REG2
- RADIO_2055_CORE2_RXRF_SPC1
- RADIO_2055_CORE2_RXTXBB_RCAL
- RADIO_2055_CORE2_TXBB_LPF1
- RADIO_2055_CORE2_TXBB_RCCAL_CTRL
- RADIO_2055_CORE2_TXRF_CNTR_PAD1
- RADIO_2055_CORE2_TXRF_CNTR_PGA1
- RADIO_2055_CORE2_TXRF_IQCAL1
- RADIO_2055_CORE2_TXRF_IQCAL2
- RADIO_2055_CORE2_TXRF_PAD_TSSI1
- RADIO_2055_CORE2_TXRF_PAD_TSSI2
- RADIO_2055_CORE2_TXRF_RCAL
- RADIO_2055_CORE2_TXRF_SGM_PAD
- RADIO_2055_CORE2_TXRF_SGM_PGA
- RADIO_2055_CORE2_TX_BB_MXGM
- RADIO_2055_CORE2_TX_LPF_MXGM_IDAC
- RADIO_2055_CORE2_TX_MX_BGTRIM
- RADIO_2055_CORE2_TX_PAD_IDAC1
- RADIO_2055_CORE2_TX_PAD_IDAC2
- RADIO_2055_CORE2_TX_PGA_PAD_TN
- RADIO_2055_CORE2_TX_RFPGA_IDAC
- RADIO_2055_CORE2_TX_RF_SPARE
- RADIO_2055_CORE2_TX_VOS_CNCL
- RADIO_2055_COUPLE_RX_MASK
- RADIO_2055_COUPLE_TX_MASK
- RADIO_2055_GAINBST_CODE
- RADIO_2055_GAINBST_DISABLE
- RADIO_2055_GAINBST_GAIN_DB
- RADIO_2055_GAINBST_VAL_MASK
- RADIO_2055_GEN_SPARE
- RADIO_2055_JTAGCTRL_MASK
- RADIO_2055_JTAGSYNC_MASK
- RADIO_2055_LGBUF_CEN_BUF
- RADIO_2055_LGEN_BIAS_CNT
- RADIO_2055_LGEN_BIAS_IDAC
- RADIO_2055_LGEN_DIV
- RADIO_2055_LGEN_IDAC1
- RADIO_2055_LGEN_IDAC2
- RADIO_2055_LGEN_RCAL
- RADIO_2055_LGEN_SPARE2
- RADIO_2055_LGEN_TUNE1
- RADIO_2055_LGEN_TUNE2
- RADIO_2055_MASTER_CNTRL1
- RADIO_2055_MASTER_CNTRL2
- RADIO_2055_NBRSSI_PD
- RADIO_2055_NBRSSI_SEL
- RADIO_2055_NBRSSI_VCM_I_MASK
- RADIO_2055_NBRSSI_VCM_I_SHIFT
- RADIO_2055_NBRSSI_VCM_Q_MASK
- RADIO_2055_NBRSSI_VCM_Q_SHIFT
- RADIO_2055_PAD_DRIVER
- RADIO_2055_PD_CORE1_LGBUF
- RADIO_2055_PD_CORE1_RSSI_MISC
- RADIO_2055_PD_CORE1_RXTX
- RADIO_2055_PD_CORE1_TX
- RADIO_2055_PD_CORE2_LGBUF
- RADIO_2055_PD_CORE2_RSSI_MISC
- RADIO_2055_PD_CORE2_RXTX
- RADIO_2055_PD_CORE2_TX
- RADIO_2055_PD_LGEN
- RADIO_2055_PD_PLL_TS
- RADIO_2055_PLL_CAL_VTH
- RADIO_2055_PLL_CP_REGULATOR
- RADIO_2055_PLL_IDAC_CPOPAMP
- RADIO_2055_PLL_LF_C1
- RADIO_2055_PLL_LF_C2
- RADIO_2055_PLL_LF_R1
- RADIO_2055_PLL_PFD_CP
- RADIO_2055_PLL_RCAL
- RADIO_2055_PLL_REF
- RADIO_2055_PLL_RF_VTH
- RADIO_2055_PRG_GC_HPVGA23_21
- RADIO_2055_PRG_GC_HPVGA23_22
- RADIO_2055_PRG_GC_HPVGA23_23
- RADIO_2055_PRG_GC_HPVGA23_24
- RADIO_2055_PRG_GC_HPVGA23_25
- RADIO_2055_PRG_GC_HPVGA23_26
- RADIO_2055_PRG_GC_HPVGA23_27
- RADIO_2055_PRG_GC_HPVGA23_28
- RADIO_2055_PRG_GC_HPVGA23_29
- RADIO_2055_PRG_GC_HPVGA23_30
- RADIO_2055_PWRDET_LGBUF_CORE1
- RADIO_2055_PWRDET_LGBUF_CORE2
- RADIO_2055_PWRDET_LGEN
- RADIO_2055_PWRDET_RXTX_CORE1
- RADIO_2055_PWRDET_RXTX_CORE2
- RADIO_2055_RCAL_DONE
- RADIO_2055_READ_OFF
- RADIO_2055_RF_MMD_IDAC0
- RADIO_2055_RF_MMD_IDAC1
- RADIO_2055_RF_MMD_SPARE
- RADIO_2055_RF_PLL_MOD0
- RADIO_2055_RF_PLL_MOD1
- RADIO_2055_RRCAL_RST_N
- RADIO_2055_RRCAL_START
- RADIO_2055_RRCCAL_CNTRL_SPARE
- RADIO_2055_RRCCAL_N_OPT_SEL
- RADIO_2055_RXMX_GC_MASK
- RADIO_2055_SP_LPF_BW_SELECT_CORE1
- RADIO_2055_SP_LPF_BW_SELECT_CORE2
- RADIO_2055_SP_PD_MISC_CORE1
- RADIO_2055_SP_PD_MISC_CORE2
- RADIO_2055_SP_PIN_PD
- RADIO_2055_SP_RSSI_CORE1
- RADIO_2055_SP_RSSI_CORE2
- RADIO_2055_SP_RX_GC1_CORE1
- RADIO_2055_SP_RX_GC1_CORE2
- RADIO_2055_SP_RX_GC2_CORE1
- RADIO_2055_SP_RX_GC2_CORE2
- RADIO_2055_SP_TX_GC1_CORE1
- RADIO_2055_SP_TX_GC1_CORE2
- RADIO_2055_SP_TX_GC2_CORE1
- RADIO_2055_SP_TX_GC2_CORE2
- RADIO_2055_VCO_CAL1
- RADIO_2055_VCO_CAL10
- RADIO_2055_VCO_CAL11
- RADIO_2055_VCO_CAL12
- RADIO_2055_VCO_CAL13
- RADIO_2055_VCO_CAL14
- RADIO_2055_VCO_CAL15
- RADIO_2055_VCO_CAL16
- RADIO_2055_VCO_CAL2
- RADIO_2055_VCO_CAL3
- RADIO_2055_VCO_CAL4
- RADIO_2055_VCO_CAL5
- RADIO_2055_VCO_CAL6
- RADIO_2055_VCO_CAL7
- RADIO_2055_VCO_CAL8
- RADIO_2055_VCO_CAL9
- RADIO_2055_VCO_CAP_TAIL
- RADIO_2055_VCO_IDAC_VCO
- RADIO_2055_VCO_KVCO
- RADIO_2055_VCO_REGULATOR
- RADIO_2055_WBRSSI_G1_PD
- RADIO_2055_WBRSSI_G1_SEL
- RADIO_2055_WBRSSI_G2_PD
- RADIO_2055_WBRSSI_G2_SEL
- RADIO_2055_WBRSSI_VCM_IQ_MASK
- RADIO_2055_WBRSSI_VCM_IQ_SHIFT
- RADIO_2055_XO_CNTRL1
- RADIO_2055_XO_CNTRL2
- RADIO_2055_XO_MISC
- RADIO_2055_XO_REGULATOR
- RADIO_2056_ALLRX
- RADIO_2056_ALLTX
- RADIO_2056_BB_LPF_PU
- RADIO_2056_LNA1_A_PU
- RADIO_2056_LNA1_G_PU
- RADIO_2056_LNA2_A_PU
- RADIO_2056_LNA2_G_PU
- RADIO_2056_MIXA_PU_GM
- RADIO_2056_MIXA_PU_I
- RADIO_2056_MIXA_PU_Q
- RADIO_2056_MIXG_PU_GM
- RADIO_2056_MIXG_PU_I
- RADIO_2056_MIXG_PU_Q
- RADIO_2056_NB_PU
- RADIO_2056_RSSI_NB_SEL
- RADIO_2056_RSSI_VCM_SHIFT
- RADIO_2056_RSSI_W1_SEL
- RADIO_2056_RSSI_W2_SEL
- RADIO_2056_RX0
- RADIO_2056_RX1
- RADIO_2056_RX_AACI_MASTER
- RADIO_2056_RX_BB_LPF_MASTER
- RADIO_2056_RX_BIASPOLE_LNAA1_IDAC
- RADIO_2056_RX_BIASPOLE_LNAG1_IDAC
- RADIO_2056_RX_COM_CTRL
- RADIO_2056_RX_COM_OVR
- RADIO_2056_RX_COM_PU
- RADIO_2056_RX_COM_RCAL
- RADIO_2056_RX_COM_RC_RXHPF
- RADIO_2056_RX_COM_RC_RXLPF
- RADIO_2056_RX_COM_RC_TXLPF
- RADIO_2056_RX_COM_RESET
- RADIO_2056_RX_IDCODE
- RADIO_2056_RX_LNA1A_MISC
- RADIO_2056_RX_LNA1G_MISC
- RADIO_2056_RX_LNAA2_IDAC
- RADIO_2056_RX_LNAA_GAIN
- RADIO_2056_RX_LNAA_MASTER
- RADIO_2056_RX_LNAA_TUNE
- RADIO_2056_RX_LNAG2_IDAC
- RADIO_2056_RX_LNAG_GAIN
- RADIO_2056_RX_LNAG_MASTER
- RADIO_2056_RX_LNAG_TUNE
- RADIO_2056_RX_LNA_A_SLOPE
- RADIO_2056_RX_LNA_G_SLOPE
- RADIO_2056_RX_MIXA_BIAS_AUX
- RADIO_2056_RX_MIXA_BIAS_MAIN
- RADIO_2056_RX_MIXA_BIAS_MISC
- RADIO_2056_RX_MIXA_CMFB_IDAC
- RADIO_2056_RX_MIXA_CORE_IDAC
- RADIO_2056_RX_MIXA_CTRLPTAT
- RADIO_2056_RX_MIXA_LOB_BIAS
- RADIO_2056_RX_MIXA_MASTER
- RADIO_2056_RX_MIXA_MAST_BIAS
- RADIO_2056_RX_MIXA_VCM
- RADIO_2056_RX_MIXG_BIAS_AUX
- RADIO_2056_RX_MIXG_BIAS_MAIN
- RADIO_2056_RX_MIXG_BIAS_MISC
- RADIO_2056_RX_MIXG_CMFB_IDAC
- RADIO_2056_RX_MIXG_CORE_IDAC
- RADIO_2056_RX_MIXG_CTRLPTAT
- RADIO_2056_RX_MIXG_LOB_BIAS
- RADIO_2056_RX_MIXG_MASTER
- RADIO_2056_RX_MIXG_MAST_BIAS
- RADIO_2056_RX_MIXG_VCM
- RADIO_2056_RX_RESERVED_ADDR0
- RADIO_2056_RX_RESERVED_ADDR16
- RADIO_2056_RX_RESERVED_ADDR17
- RADIO_2056_RX_RESERVED_ADDR18
- RADIO_2056_RX_RESERVED_ADDR19
- RADIO_2056_RX_RESERVED_ADDR2
- RADIO_2056_RX_RESERVED_ADDR20
- RADIO_2056_RX_RESERVED_ADDR21
- RADIO_2056_RX_RESERVED_ADDR22
- RADIO_2056_RX_RESERVED_ADDR23
- RADIO_2056_RX_RESERVED_ADDR24
- RADIO_2056_RX_RESERVED_ADDR25
- RADIO_2056_RX_RESERVED_ADDR26
- RADIO_2056_RX_RESERVED_ADDR27
- RADIO_2056_RX_RESERVED_ADDR28
- RADIO_2056_RX_RESERVED_ADDR29
- RADIO_2056_RX_RESERVED_ADDR3
- RADIO_2056_RX_RESERVED_ADDR30
- RADIO_2056_RX_RESERVED_ADDR31
- RADIO_2056_RX_RESERVED_ADDR4
- RADIO_2056_RX_RESERVED_ADDR5
- RADIO_2056_RX_RESERVED_ADDR6
- RADIO_2056_RX_RESERVED_ADDR7
- RADIO_2056_RX_RSSI_GAIN
- RADIO_2056_RX_RSSI_MISC
- RADIO_2056_RX_RSSI_NB_IDAC
- RADIO_2056_RX_RSSI_POLE
- RADIO_2056_RX_RSSI_PU
- RADIO_2056_RX_RSSI_SEL
- RADIO_2056_RX_RSSI_WB1_IDAC
- RADIO_2056_RX_RSSI_WB2I_IDAC_1
- RADIO_2056_RX_RSSI_WB2I_IDAC_2
- RADIO_2056_RX_RSSI_WB2Q_IDAC_1
- RADIO_2056_RX_RSSI_WB2Q_IDAC_2
- RADIO_2056_RX_RXHPF_OFF0
- RADIO_2056_RX_RXHPF_OFF1
- RADIO_2056_RX_RXHPF_OFF2
- RADIO_2056_RX_RXHPF_OFF3
- RADIO_2056_RX_RXHPF_OFF4
- RADIO_2056_RX_RXHPF_OFF5
- RADIO_2056_RX_RXHPF_OFF6
- RADIO_2056_RX_RXHPF_OFF7
- RADIO_2056_RX_RXIQCAL_RXMUX
- RADIO_2056_RX_RXLPF_BIAS_DCCANCEL
- RADIO_2056_RX_RXLPF_CC_OP
- RADIO_2056_RX_RXLPF_GAIN
- RADIO_2056_RX_RXLPF_HP_CORNER_BW
- RADIO_2056_RX_RXLPF_IDAC
- RADIO_2056_RX_RXLPF_INVCM_BODY
- RADIO_2056_RX_RXLPF_OFF_0
- RADIO_2056_RX_RXLPF_OFF_1
- RADIO_2056_RX_RXLPF_OFF_2
- RADIO_2056_RX_RXLPF_OFF_3
- RADIO_2056_RX_RXLPF_OFF_4
- RADIO_2056_RX_RXLPF_OPAMPBIAS_HIGHQ
- RADIO_2056_RX_RXLPF_OPAMPBIAS_LOWQ
- RADIO_2056_RX_RXLPF_OUTVCM
- RADIO_2056_RX_RXLPF_Q_BW
- RADIO_2056_RX_RXLPF_RCCAL_HPC
- RADIO_2056_RX_RXLPF_RCCAL_LPC
- RADIO_2056_RX_RXSPARE1
- RADIO_2056_RX_RXSPARE10
- RADIO_2056_RX_RXSPARE11
- RADIO_2056_RX_RXSPARE12
- RADIO_2056_RX_RXSPARE13
- RADIO_2056_RX_RXSPARE14
- RADIO_2056_RX_RXSPARE15
- RADIO_2056_RX_RXSPARE16
- RADIO_2056_RX_RXSPARE2
- RADIO_2056_RX_RXSPARE3
- RADIO_2056_RX_RXSPARE4
- RADIO_2056_RX_RXSPARE5
- RADIO_2056_RX_RXSPARE6
- RADIO_2056_RX_RXSPARE7
- RADIO_2056_RX_RXSPARE8
- RADIO_2056_RX_RXSPARE9
- RADIO_2056_RX_STATUS_HPC_RC
- RADIO_2056_RX_STATUS_LNAA_GAIN
- RADIO_2056_RX_STATUS_LNAG_GAIN
- RADIO_2056_RX_STATUS_MIXTIA_GAIN
- RADIO_2056_RX_STATUS_RXLPF_BUF_BW
- RADIO_2056_RX_STATUS_RXLPF_GAIN
- RADIO_2056_RX_STATUS_RXLPF_Q
- RADIO_2056_RX_STATUS_RXLPF_RC
- RADIO_2056_RX_STATUS_RXLPF_VGA_HPC
- RADIO_2056_RX_STATUS_VGA_BUF_GAIN
- RADIO_2056_RX_TIA_GAIN
- RADIO_2056_RX_TIA_IMISC
- RADIO_2056_RX_TIA_IOPAMP
- RADIO_2056_RX_TIA_MASTER
- RADIO_2056_RX_TIA_QMISC
- RADIO_2056_RX_TIA_QOPAMP
- RADIO_2056_RX_TIA_SPARE1
- RADIO_2056_RX_TIA_SPARE2
- RADIO_2056_RX_TXFBMIX_A
- RADIO_2056_RX_TXFBMIX_G
- RADIO_2056_RX_UNUSED
- RADIO_2056_RX_VGABUF_BIAS
- RADIO_2056_RX_VGABUF_GAIN_BW
- RADIO_2056_RX_VGA_BIAS
- RADIO_2056_RX_VGA_BIAS_DCCANCEL
- RADIO_2056_RX_VGA_GAIN
- RADIO_2056_RX_VGA_HP_CORNER_BW
- RADIO_2056_RX_VGA_MASTER
- RADIO_2056_SYN
- RADIO_2056_SYN_AFEREG
- RADIO_2056_SYN_CALEN
- RADIO_2056_SYN_COM_CTRL
- RADIO_2056_SYN_COM_OVR
- RADIO_2056_SYN_COM_PU
- RADIO_2056_SYN_COM_RCAL
- RADIO_2056_SYN_COM_RC_RXHPF
- RADIO_2056_SYN_COM_RC_RXLPF
- RADIO_2056_SYN_COM_RC_TXLPF
- RADIO_2056_SYN_COM_RESET
- RADIO_2056_SYN_GPIO_MASTER1
- RADIO_2056_SYN_GPIO_MASTER2
- RADIO_2056_SYN_IDCODE
- RADIO_2056_SYN_LOGENBUF2
- RADIO_2056_SYN_LOGEN_ACL1
- RADIO_2056_SYN_LOGEN_ACL2
- RADIO_2056_SYN_LOGEN_ACL3
- RADIO_2056_SYN_LOGEN_ACL4
- RADIO_2056_SYN_LOGEN_ACL5
- RADIO_2056_SYN_LOGEN_ACL6
- RADIO_2056_SYN_LOGEN_ACLCAL1
- RADIO_2056_SYN_LOGEN_ACLCAL2
- RADIO_2056_SYN_LOGEN_ACLCAL3
- RADIO_2056_SYN_LOGEN_ACLOUT
- RADIO_2056_SYN_LOGEN_ACL_WAITCNT
- RADIO_2056_SYN_LOGEN_BIAS_RESET
- RADIO_2056_SYN_LOGEN_BUF1
- RADIO_2056_SYN_LOGEN_BUF3
- RADIO_2056_SYN_LOGEN_BUF4
- RADIO_2056_SYN_LOGEN_BUF5
- RADIO_2056_SYN_LOGEN_BUF5_OVRVAL
- RADIO_2056_SYN_LOGEN_BUF6
- RADIO_2056_SYN_LOGEN_BUF6_OVRVAL
- RADIO_2056_SYN_LOGEN_CBUFRX1
- RADIO_2056_SYN_LOGEN_CBUFRX1_OVRVAL
- RADIO_2056_SYN_LOGEN_CBUFRX2
- RADIO_2056_SYN_LOGEN_CBUFRX2_OVRVAL
- RADIO_2056_SYN_LOGEN_CBUFRX3
- RADIO_2056_SYN_LOGEN_CBUFRX3_OVRVAL
- RADIO_2056_SYN_LOGEN_CBUFRX4
- RADIO_2056_SYN_LOGEN_CBUFRX4_OVRVAL
- RADIO_2056_SYN_LOGEN_CBUFTX1
- RADIO_2056_SYN_LOGEN_CBUFTX1_OVRVAL
- RADIO_2056_SYN_LOGEN_CBUFTX2
- RADIO_2056_SYN_LOGEN_CBUFTX2_OVRVAL
- RADIO_2056_SYN_LOGEN_CBUFTX3
- RADIO_2056_SYN_LOGEN_CBUFTX3_OVRVAL
- RADIO_2056_SYN_LOGEN_CBUFTX4
- RADIO_2056_SYN_LOGEN_CBUFTX4_OVRVAL
- RADIO_2056_SYN_LOGEN_CMOSRX1
- RADIO_2056_SYN_LOGEN_CMOSRX1_OVRVAL
- RADIO_2056_SYN_LOGEN_CMOSRX2
- RADIO_2056_SYN_LOGEN_CMOSRX2_OVRVAL
- RADIO_2056_SYN_LOGEN_CMOSRX3
- RADIO_2056_SYN_LOGEN_CMOSRX3_OVRVAL
- RADIO_2056_SYN_LOGEN_CMOSRX4
- RADIO_2056_SYN_LOGEN_CMOSRX4_OVRVAL
- RADIO_2056_SYN_LOGEN_CMOSTX1
- RADIO_2056_SYN_LOGEN_CMOSTX1_OVRVAL
- RADIO_2056_SYN_LOGEN_CMOSTX2
- RADIO_2056_SYN_LOGEN_CMOSTX2_OVRVAL
- RADIO_2056_SYN_LOGEN_CMOSTX3
- RADIO_2056_SYN_LOGEN_CMOSTX3_OVRVAL
- RADIO_2056_SYN_LOGEN_CMOSTX4
- RADIO_2056_SYN_LOGEN_CMOSTX4_OVRVAL
- RADIO_2056_SYN_LOGEN_CORE_ACL_OVR
- RADIO_2056_SYN_LOGEN_CORE_CALVALID
- RADIO_2056_SYN_LOGEN_DIV1
- RADIO_2056_SYN_LOGEN_DIV2
- RADIO_2056_SYN_LOGEN_DIV3
- RADIO_2056_SYN_LOGEN_MIXER1
- RADIO_2056_SYN_LOGEN_MIXER2
- RADIO_2056_SYN_LOGEN_MIXER3
- RADIO_2056_SYN_LOGEN_MIXER3_OVRVAL
- RADIO_2056_SYN_LOGEN_PEAKDET1
- RADIO_2056_SYN_LOGEN_PU0
- RADIO_2056_SYN_LOGEN_PU1
- RADIO_2056_SYN_LOGEN_PU2
- RADIO_2056_SYN_LOGEN_PU3
- RADIO_2056_SYN_LOGEN_PU5
- RADIO_2056_SYN_LOGEN_PU6
- RADIO_2056_SYN_LOGEN_PU7
- RADIO_2056_SYN_LOGEN_PU8
- RADIO_2056_SYN_LOGEN_RCCR1
- RADIO_2056_SYN_LOGEN_RX_CMOS_ACL_OVR
- RADIO_2056_SYN_LOGEN_RX_CMOS_CALVALID
- RADIO_2056_SYN_LOGEN_RX_DIFF_ACL_OVR
- RADIO_2056_SYN_LOGEN_TX_CMOS_ACL_OVR
- RADIO_2056_SYN_LOGEN_TX_CMOS_VALID
- RADIO_2056_SYN_LOGEN_TX_DIFF_ACL_OVR
- RADIO_2056_SYN_LOGEN_VCOBUF1
- RADIO_2056_SYN_LOGEN_VCOBUF2
- RADIO_2056_SYN_LOGEN_VCOBUF2_OVRVAL
- RADIO_2056_SYN_LPO
- RADIO_2056_SYN_PLL_BIAS_RESET
- RADIO_2056_SYN_PLL_CP1
- RADIO_2056_SYN_PLL_CP2
- RADIO_2056_SYN_PLL_CP3
- RADIO_2056_SYN_PLL_LOOPFILTER1
- RADIO_2056_SYN_PLL_LOOPFILTER2
- RADIO_2056_SYN_PLL_LOOPFILTER3
- RADIO_2056_SYN_PLL_LOOPFILTER4
- RADIO_2056_SYN_PLL_LOOPFILTER5
- RADIO_2056_SYN_PLL_MAST1
- RADIO_2056_SYN_PLL_MAST2
- RADIO_2056_SYN_PLL_MAST3
- RADIO_2056_SYN_PLL_MMD1
- RADIO_2056_SYN_PLL_MMD2
- RADIO_2056_SYN_PLL_MONITOR1
- RADIO_2056_SYN_PLL_MONITOR2
- RADIO_2056_SYN_PLL_PFD
- RADIO_2056_SYN_PLL_REFDIV
- RADIO_2056_SYN_PLL_STATUS1
- RADIO_2056_SYN_PLL_STATUS2
- RADIO_2056_SYN_PLL_STATUS3
- RADIO_2056_SYN_PLL_VCO1
- RADIO_2056_SYN_PLL_VCO2
- RADIO_2056_SYN_PLL_VCOCAL1
- RADIO_2056_SYN_PLL_VCOCAL10
- RADIO_2056_SYN_PLL_VCOCAL11
- RADIO_2056_SYN_PLL_VCOCAL12
- RADIO_2056_SYN_PLL_VCOCAL13
- RADIO_2056_SYN_PLL_VCOCAL2
- RADIO_2056_SYN_PLL_VCOCAL4
- RADIO_2056_SYN_PLL_VCOCAL5
- RADIO_2056_SYN_PLL_VCOCAL6
- RADIO_2056_SYN_PLL_VCOCAL7
- RADIO_2056_SYN_PLL_VCOCAL8
- RADIO_2056_SYN_PLL_VCOCAL9
- RADIO_2056_SYN_PLL_VREG
- RADIO_2056_SYN_PLL_XTAL0
- RADIO_2056_SYN_PLL_XTAL1
- RADIO_2056_SYN_PLL_XTAL3
- RADIO_2056_SYN_PLL_XTAL4
- RADIO_2056_SYN_PLL_XTAL5
- RADIO_2056_SYN_PLL_XTAL6
- RADIO_2056_SYN_RCAL_CODE_OUT
- RADIO_2056_SYN_RCAL_MASTER
- RADIO_2056_SYN_RCCAL_CTRL0
- RADIO_2056_SYN_RCCAL_CTRL1
- RADIO_2056_SYN_RCCAL_CTRL10
- RADIO_2056_SYN_RCCAL_CTRL11
- RADIO_2056_SYN_RCCAL_CTRL2
- RADIO_2056_SYN_RCCAL_CTRL3
- RADIO_2056_SYN_RCCAL_CTRL4
- RADIO_2056_SYN_RCCAL_CTRL5
- RADIO_2056_SYN_RCCAL_CTRL6
- RADIO_2056_SYN_RCCAL_CTRL7
- RADIO_2056_SYN_RCCAL_CTRL8
- RADIO_2056_SYN_RCCAL_CTRL9
- RADIO_2056_SYN_RESERVED_ADDR0
- RADIO_2056_SYN_RESERVED_ADDR16
- RADIO_2056_SYN_RESERVED_ADDR17
- RADIO_2056_SYN_RESERVED_ADDR18
- RADIO_2056_SYN_RESERVED_ADDR19
- RADIO_2056_SYN_RESERVED_ADDR2
- RADIO_2056_SYN_RESERVED_ADDR20
- RADIO_2056_SYN_RESERVED_ADDR21
- RADIO_2056_SYN_RESERVED_ADDR22
- RADIO_2056_SYN_RESERVED_ADDR23
- RADIO_2056_SYN_RESERVED_ADDR24
- RADIO_2056_SYN_RESERVED_ADDR25
- RADIO_2056_SYN_RESERVED_ADDR26
- RADIO_2056_SYN_RESERVED_ADDR27
- RADIO_2056_SYN_RESERVED_ADDR28
- RADIO_2056_SYN_RESERVED_ADDR29
- RADIO_2056_SYN_RESERVED_ADDR3
- RADIO_2056_SYN_RESERVED_ADDR30
- RADIO_2056_SYN_RESERVED_ADDR31
- RADIO_2056_SYN_RESERVED_ADDR4
- RADIO_2056_SYN_RESERVED_ADDR5
- RADIO_2056_SYN_RESERVED_ADDR6
- RADIO_2056_SYN_RESERVED_ADDR7
- RADIO_2056_SYN_TEMPPROCSENSE
- RADIO_2056_SYN_TEMPPROCSENSEIDAC
- RADIO_2056_SYN_TEMPPROCSENSERCAL
- RADIO_2056_SYN_TOPBIAS_MASTER
- RADIO_2056_SYN_TOPBIAS_RCAL
- RADIO_2056_SYN_VDDCAL_IDAC
- RADIO_2056_SYN_VDDCAL_MASTER
- RADIO_2056_SYN_VDDCAL_STATUS
- RADIO_2056_SYN_ZCAL_SPARE1
- RADIO_2056_SYN_ZCAL_SPARE2
- RADIO_2056_TIA_PU
- RADIO_2056_TX0
- RADIO_2056_TX1
- RADIO_2056_TX_BB_GM_MASTER
- RADIO_2056_TX_COM_CTRL
- RADIO_2056_TX_COM_OVR
- RADIO_2056_TX_COM_PU
- RADIO_2056_TX_COM_RCAL
- RADIO_2056_TX_COM_RC_RXHPF
- RADIO_2056_TX_COM_RC_RXLPF
- RADIO_2056_TX_COM_RC_TXLPF
- RADIO_2056_TX_COM_RESET
- RADIO_2056_TX_GMBB_GM
- RADIO_2056_TX_GMBB_IDAC
- RADIO_2056_TX_GMBB_IDAC0
- RADIO_2056_TX_GMBB_IDAC1
- RADIO_2056_TX_GMBB_IDAC2
- RADIO_2056_TX_GMBB_IDAC3
- RADIO_2056_TX_GMBB_IDAC4
- RADIO_2056_TX_GMBB_IDAC5
- RADIO_2056_TX_GMBB_IDAC6
- RADIO_2056_TX_GMBB_IDAC7
- RADIO_2056_TX_IDCODE
- RADIO_2056_TX_INTPAA_BOOST_TUNE
- RADIO_2056_TX_INTPAA_CASCBIAS
- RADIO_2056_TX_INTPAA_GAIN
- RADIO_2056_TX_INTPAA_IAUX_DYN
- RADIO_2056_TX_INTPAA_IAUX_STAT
- RADIO_2056_TX_INTPAA_IMAIN_DYN
- RADIO_2056_TX_INTPAA_IMAIN_STAT
- RADIO_2056_TX_INTPAA_MASTER
- RADIO_2056_TX_INTPAA_PASLOPE
- RADIO_2056_TX_INTPAA_PA_MISC
- RADIO_2056_TX_INTPAG_BOOST_TUNE
- RADIO_2056_TX_INTPAG_CASCBIAS
- RADIO_2056_TX_INTPAG_GAIN
- RADIO_2056_TX_INTPAG_IAUX_DYN
- RADIO_2056_TX_INTPAG_IAUX_STAT
- RADIO_2056_TX_INTPAG_IMAIN_DYN
- RADIO_2056_TX_INTPAG_IMAIN_STAT
- RADIO_2056_TX_INTPAG_MASTER
- RADIO_2056_TX_INTPAG_PASLOPE
- RADIO_2056_TX_INTPAG_PA_MISC
- RADIO_2056_TX_IQCAL_GAIN_BW
- RADIO_2056_TX_IQCAL_IDAC
- RADIO_2056_TX_IQCAL_VCM_HG
- RADIO_2056_TX_LOFT_COARSE_I
- RADIO_2056_TX_LOFT_COARSE_Q
- RADIO_2056_TX_LOFT_FINE_I
- RADIO_2056_TX_LOFT_FINE_Q
- RADIO_2056_TX_MIXA_BOOST_TUNE
- RADIO_2056_TX_MIXA_MASTER
- RADIO_2056_TX_MIXG
- RADIO_2056_TX_MIXG_BOOST_TUNE
- RADIO_2056_TX_PADA_BOOST_TUNE
- RADIO_2056_TX_PADA_CASCBIAS
- RADIO_2056_TX_PADA_GAIN
- RADIO_2056_TX_PADA_IDAC
- RADIO_2056_TX_PADA_MASTER
- RADIO_2056_TX_PADA_SLOPE
- RADIO_2056_TX_PADG_BOOST_TUNE
- RADIO_2056_TX_PADG_CASCBIAS
- RADIO_2056_TX_PADG_GAIN
- RADIO_2056_TX_PADG_IDAC
- RADIO_2056_TX_PADG_MASTER
- RADIO_2056_TX_PADG_SLOPE
- RADIO_2056_TX_PA_SPARE1
- RADIO_2056_TX_PA_SPARE2
- RADIO_2056_TX_PGAA_BOOST_TUNE
- RADIO_2056_TX_PGAA_GAIN
- RADIO_2056_TX_PGAA_IDAC
- RADIO_2056_TX_PGAA_MASTER
- RADIO_2056_TX_PGAA_MISC
- RADIO_2056_TX_PGAA_SLOPE
- RADIO_2056_TX_PGAG_BOOST_TUNE
- RADIO_2056_TX_PGAG_GAIN
- RADIO_2056_TX_PGAG_IDAC
- RADIO_2056_TX_PGAG_MASTER
- RADIO_2056_TX_PGAG_MISC
- RADIO_2056_TX_PGAG_SLOPE
- RADIO_2056_TX_RESERVED_ADDR0
- RADIO_2056_TX_RESERVED_ADDR16
- RADIO_2056_TX_RESERVED_ADDR17
- RADIO_2056_TX_RESERVED_ADDR18
- RADIO_2056_TX_RESERVED_ADDR19
- RADIO_2056_TX_RESERVED_ADDR2
- RADIO_2056_TX_RESERVED_ADDR20
- RADIO_2056_TX_RESERVED_ADDR21
- RADIO_2056_TX_RESERVED_ADDR22
- RADIO_2056_TX_RESERVED_ADDR23
- RADIO_2056_TX_RESERVED_ADDR24
- RADIO_2056_TX_RESERVED_ADDR25
- RADIO_2056_TX_RESERVED_ADDR26
- RADIO_2056_TX_RESERVED_ADDR27
- RADIO_2056_TX_RESERVED_ADDR28
- RADIO_2056_TX_RESERVED_ADDR29
- RADIO_2056_TX_RESERVED_ADDR3
- RADIO_2056_TX_RESERVED_ADDR30
- RADIO_2056_TX_RESERVED_ADDR31
- RADIO_2056_TX_RESERVED_ADDR4
- RADIO_2056_TX_RESERVED_ADDR5
- RADIO_2056_TX_RESERVED_ADDR6
- RADIO_2056_TX_RESERVED_ADDR7
- RADIO_2056_TX_RXIQCAL_TXMUX
- RADIO_2056_TX_STATUS_GM_TXLPF_GAIN
- RADIO_2056_TX_STATUS_INTPA_GAIN
- RADIO_2056_TX_STATUS_PAD_GAIN
- RADIO_2056_TX_STATUS_PGA_GAIN
- RADIO_2056_TX_STATUS_TXLPF_BW
- RADIO_2056_TX_STATUS_TXLPF_RC
- RADIO_2056_TX_TSSIA
- RADIO_2056_TX_TSSIG
- RADIO_2056_TX_TSSI_MISC1
- RADIO_2056_TX_TSSI_MISC2
- RADIO_2056_TX_TSSI_MISC3
- RADIO_2056_TX_TSSI_VCM
- RADIO_2056_TX_TXLPF_BW
- RADIO_2056_TX_TXLPF_GAIN
- RADIO_2056_TX_TXLPF_IDAC
- RADIO_2056_TX_TXLPF_IDAC_0
- RADIO_2056_TX_TXLPF_IDAC_1
- RADIO_2056_TX_TXLPF_IDAC_2
- RADIO_2056_TX_TXLPF_IDAC_3
- RADIO_2056_TX_TXLPF_IDAC_4
- RADIO_2056_TX_TXLPF_IDAC_5
- RADIO_2056_TX_TXLPF_IDAC_6
- RADIO_2056_TX_TXLPF_MASTER
- RADIO_2056_TX_TXLPF_MISC
- RADIO_2056_TX_TXLPF_OPAMP_IDAC
- RADIO_2056_TX_TXLPF_RCCAL
- RADIO_2056_TX_TXLPF_RCCAL_OFF0
- RADIO_2056_TX_TXLPF_RCCAL_OFF1
- RADIO_2056_TX_TXLPF_RCCAL_OFF2
- RADIO_2056_TX_TXLPF_RCCAL_OFF3
- RADIO_2056_TX_TXLPF_RCCAL_OFF4
- RADIO_2056_TX_TXLPF_RCCAL_OFF5
- RADIO_2056_TX_TXLPF_RCCAL_OFF6
- RADIO_2056_TX_TXSPARE1
- RADIO_2056_TX_TXSPARE10
- RADIO_2056_TX_TXSPARE11
- RADIO_2056_TX_TXSPARE12
- RADIO_2056_TX_TXSPARE13
- RADIO_2056_TX_TXSPARE14
- RADIO_2056_TX_TXSPARE15
- RADIO_2056_TX_TXSPARE16
- RADIO_2056_TX_TXSPARE2
- RADIO_2056_TX_TXSPARE3
- RADIO_2056_TX_TXSPARE4
- RADIO_2056_TX_TXSPARE5
- RADIO_2056_TX_TXSPARE6
- RADIO_2056_TX_TXSPARE7
- RADIO_2056_TX_TXSPARE8
- RADIO_2056_TX_TXSPARE9
- RADIO_2056_TX_TX_AMP_DET
- RADIO_2056_TX_TX_COM_MASTER1
- RADIO_2056_TX_TX_COM_MASTER2
- RADIO_2056_TX_TX_SSI_MASTER
- RADIO_2056_TX_TX_SSI_MUX
- RADIO_2056_VCM_MASK
- RADIO_2056_W1_PU
- RADIO_2056_W2_PU
- RADIO_2057_AFELOOPBACK_AACI_RESP_CORE0
- RADIO_2057_AFELOOPBACK_AACI_RESP_CORE1
- RADIO_2057_AFEREG_CONFIG
- RADIO_2057_AFE_SET_VCM_I_CORE0
- RADIO_2057_AFE_SET_VCM_I_CORE1
- RADIO_2057_AFE_SET_VCM_Q_CORE0
- RADIO_2057_AFE_SET_VCM_Q_CORE1
- RADIO_2057_AFE_STATUS_VCM_IQADC_CORE0
- RADIO_2057_AFE_STATUS_VCM_IQADC_CORE1
- RADIO_2057_AFE_STATUS_VCM_I_CORE0
- RADIO_2057_AFE_STATUS_VCM_I_CORE1
- RADIO_2057_AFE_STATUS_VCM_Q_CORE0
- RADIO_2057_AFE_STATUS_VCM_Q_CORE1
- RADIO_2057_AFE_VCM_CAL_MASTER_CORE0
- RADIO_2057_AFE_VCM_CAL_MASTER_CORE1
- RADIO_2057_BACKUP1_CORE0
- RADIO_2057_BACKUP1_CORE1
- RADIO_2057_BACKUP2_CORE0
- RADIO_2057_BACKUP2_CORE1
- RADIO_2057_BACKUP3_CORE0
- RADIO_2057_BACKUP3_CORE1
- RADIO_2057_BACKUP4_CORE0
- RADIO_2057_BACKUP4_CORE1
- RADIO_2057_BANDGAP_CONFIG
- RADIO_2057_BANDGAP_RCAL_TRIM
- RADIO_2057_BUFS_MISC_LPFBW_CORE0
- RADIO_2057_BUFS_MISC_LPFBW_CORE1
- RADIO_2057_CLPO_CONFIG
- RADIO_2057_CMOSBUF_RX2GI_IDACS
- RADIO_2057_CMOSBUF_RX2GQ_IDACS
- RADIO_2057_CMOSBUF_RX5GI_IDACS
- RADIO_2057_CMOSBUF_RX5GQ_IDACS
- RADIO_2057_CMOSBUF_RX_RCCR
- RADIO_2057_CMOSBUF_SHAREIQ_PTAT
- RADIO_2057_CMOSBUF_TX2GI_IDACS
- RADIO_2057_CMOSBUF_TX2GQ_IDACS
- RADIO_2057_CMOSBUF_TX5GI_IDACS
- RADIO_2057_CMOSBUF_TX5GQ_IDACS
- RADIO_2057_CMOSBUF_TX_RCCR
- RADIO_2057_CP_KPD_IDAC
- RADIO_2057_DACBUF_IDACS_BW_CORE0
- RADIO_2057_DACBUF_IDACS_BW_CORE1
- RADIO_2057_DACBUF_VINCM_CORE0
- RADIO_2057_DACBUF_VINCM_CORE1
- RADIO_2057_GPAIO_CONFIG
- RADIO_2057_GPAIO_SEL0
- RADIO_2057_GPAIO_SEL1
- RADIO_2057_IDCODE
- RADIO_2057_IPA2G_BIAS_FILTER_CORE0
- RADIO_2057_IPA2G_BIAS_FILTER_CORE1
- RADIO_2057_IPA2G_CASCOFFV_CORE0
- RADIO_2057_IPA2G_CASCOFFV_CORE1
- RADIO_2057_IPA2G_CASCONV_CORE0
- RADIO_2057_IPA2G_CASCONV_CORE1
- RADIO_2057_IPA2G_GAIN_CORE0
- RADIO_2057_IPA2G_GAIN_CORE1
- RADIO_2057_IPA2G_IMAIN_CORE0
- RADIO_2057_IPA2G_IMAIN_CORE1
- RADIO_2057_IPA2G_TUNEV_CASCV_PTAT_CORE0
- RADIO_2057_IPA2G_TUNEV_CASCV_PTAT_CORE1
- RADIO_2057_IPA5G_BIAS_FILTER_CORE0
- RADIO_2057_IPA5G_BIAS_FILTER_CORE1
- RADIO_2057_IPA5G_CASCOFFV_PU_CORE0
- RADIO_2057_IPA5G_CASCOFFV_PU_CORE1
- RADIO_2057_IPA5G_CASCONV_CORE0
- RADIO_2057_IPA5G_CASCONV_CORE1
- RADIO_2057_IPA5G_GAIN_CORE0
- RADIO_2057_IPA5G_GAIN_CORE1
- RADIO_2057_IPA5G_IAUX_CORE0
- RADIO_2057_IPA5G_IAUX_CORE1
- RADIO_2057_IPA5G_IMAIN_CORE0
- RADIO_2057_IPA5G_IMAIN_CORE1
- RADIO_2057_IPA5G_PTAT_CORE0
- RADIO_2057_IPA5G_PTAT_CORE1
- RADIO_2057_IQTEST_SEL_PU
- RADIO_2057_JTAGXTAL_SIZE_CPBIAS_FILTRES
- RADIO_2057_LNA15G_INPUT_MATCH_TUNE_CORE0
- RADIO_2057_LNA15G_INPUT_MATCH_TUNE_CORE1
- RADIO_2057_LNA1_IMAIN_PTAT_PU_CORE0
- RADIO_2057_LNA1_IMAIN_PTAT_PU_CORE1
- RADIO_2057_LNA2G_GAIN_CORE0
- RADIO_2057_LNA2G_GAIN_CORE1
- RADIO_2057_LNA2G_TUNE_CORE0
- RADIO_2057_LNA2G_TUNE_CORE1
- RADIO_2057_LNA2_IAUX_PTAT_CORE0
- RADIO_2057_LNA2_IAUX_PTAT_CORE1
- RADIO_2057_LNA2_IMAIN_PTAT_PU_CORE0
- RADIO_2057_LNA2_IMAIN_PTAT_PU_CORE1
- RADIO_2057_LNA5G_GAIN_CORE0
- RADIO_2057_LNA5G_GAIN_CORE1
- RADIO_2057_LNA5G_RFEN_CORE0
- RADIO_2057_LNA5G_RFEN_CORE1
- RADIO_2057_LNA5G_TUNE_CORE0
- RADIO_2057_LNA5G_TUNE_CORE1
- RADIO_2057_LOGEN_INDBUF2G_IBOOST
- RADIO_2057_LOGEN_INDBUF2G_IDAC
- RADIO_2057_LOGEN_INDBUF2G_TUNE
- RADIO_2057_LOGEN_INDBUF5G_IBOOST
- RADIO_2057_LOGEN_INDBUF5G_IDAC
- RADIO_2057_LOGEN_INDBUF5G_TUNE
- RADIO_2057_LOGEN_MX2G_IDACS
- RADIO_2057_LOGEN_MX2G_TUNE
- RADIO_2057_LOGEN_MX5G_IDACS
- RADIO_2057_LOGEN_MX5G_RCCR
- RADIO_2057_LOGEN_MX5G_TUNE
- RADIO_2057_LOGEN_PTAT_RESETS
- RADIO_2057_LOGEN_PUS
- RADIO_2057_LOGEN_SEL_PKDET
- RADIO_2057_LPFBYP_DCLOOP_BYP_IDAC_CORE0
- RADIO_2057_LPFBYP_DCLOOP_BYP_IDAC_CORE1
- RADIO_2057_LPFSEL_TXRX_RXBB_PUS_CORE0
- RADIO_2057_LPFSEL_TXRX_RXBB_PUS_CORE1
- RADIO_2057_LPF_GAIN_CORE0
- RADIO_2057_LPF_GAIN_CORE1
- RADIO_2057_LPF_IDACS_CORE0
- RADIO_2057_LPF_IDACS_CORE1
- RADIO_2057_LPF_RESP_RXBUF_BW_CORE0
- RADIO_2057_LPF_RESP_RXBUF_BW_CORE1
- RADIO_2057_LPF_VCMREF_TXBUF_VCMREF_CORE0
- RADIO_2057_LPF_VCMREF_TXBUF_VCMREF_CORE1
- RADIO_2057_NB_IDACS_I_CORE0
- RADIO_2057_NB_IDACS_I_CORE1
- RADIO_2057_NB_IDACS_Q_CORE0
- RADIO_2057_NB_IDACS_Q_CORE1
- RADIO_2057_NB_MASTER_CORE0
- RADIO_2057_NB_MASTER_CORE1
- RADIO_2057_OVR_REG0
- RADIO_2057_OVR_REG1
- RADIO_2057_OVR_REG2
- RADIO_2057_OVR_REG3
- RADIO_2057_OVR_REG4
- RADIO_2057_PAD2G_BOOST_PU_CORE0
- RADIO_2057_PAD2G_BOOST_PU_CORE1
- RADIO_2057_PAD2G_CASCV_GAIN_CORE0
- RADIO_2057_PAD2G_CASCV_GAIN_CORE1
- RADIO_2057_PAD2G_IDACS_CORE0
- RADIO_2057_PAD2G_IDACS_CORE1
- RADIO_2057_PAD2G_PTATS_CORE0
- RADIO_2057_PAD2G_PTATS_CORE1
- RADIO_2057_PAD2G_TUNE_PUS_CORE0
- RADIO_2057_PAD2G_TUNE_PUS_CORE1
- RADIO_2057_PAD5G_CASCOFFV_GAIN_PUS_CORE0
- RADIO_2057_PAD5G_CASCOFFV_GAIN_PUS_CORE1
- RADIO_2057_PAD5G_CASCV_IMAIN_CORE0
- RADIO_2057_PAD5G_CASCV_IMAIN_CORE1
- RADIO_2057_PAD5G_CLASS_PTATS2_CORE0
- RADIO_2057_PAD5G_CLASS_PTATS2_CORE1
- RADIO_2057_PAD5G_PTATS1_CORE0
- RADIO_2057_PAD5G_PTATS1_CORE1
- RADIO_2057_PAD5G_TUNE_MISC_PUS_CORE0
- RADIO_2057_PAD5G_TUNE_MISC_PUS_CORE1
- RADIO_2057_PAD_BIAS_FILTER_BWS_CORE0
- RADIO_2057_PAD_BIAS_FILTER_BWS_CORE1
- RADIO_2057_PGA_BOOSTPTAT_IMAIN_CORE0
- RADIO_2057_PGA_BOOSTPTAT_IMAIN_CORE1
- RADIO_2057_PGA_BOOST_TUNE_CORE0
- RADIO_2057_PGA_BOOST_TUNE_CORE1
- RADIO_2057_PGA_GAIN_CORE0
- RADIO_2057_PGA_GAIN_CORE1
- RADIO_2057_PGA_PTAT_TXGM5G_PU_CORE0
- RADIO_2057_PGA_PTAT_TXGM5G_PU_CORE1
- RADIO_2057_RCAL_CONFIG
- RADIO_2057_RCAL_STATUS
- RADIO_2057_RCCAL_BCAP_VAL
- RADIO_2057_RCCAL_CAP_SIZE
- RADIO_2057_RCCAL_DONE_OSCCAP
- RADIO_2057_RCCAL_HPC_VAL
- RADIO_2057_RCCAL_MASTER
- RADIO_2057_RCCAL_N0_0
- RADIO_2057_RCCAL_N0_1
- RADIO_2057_RCCAL_N1_0
- RADIO_2057_RCCAL_N1_1
- RADIO_2057_RCCAL_OVERRIDES
- RADIO_2057_RCCAL_SCAP_VAL
- RADIO_2057_RCCAL_START_R1_Q1_P1
- RADIO_2057_RCCAL_TRC0
- RADIO_2057_RCCAL_TRC1
- RADIO_2057_RCCAL_X1
- RADIO_2057_READ_OFF
- RADIO_2057_RFPLL_IDACS
- RADIO_2057_RFPLL_LOOPFILTER_C1
- RADIO_2057_RFPLL_LOOPFILTER_C2
- RADIO_2057_RFPLL_LOOPFILTER_C3
- RADIO_2057_RFPLL_LOOPFILTER_R1
- RADIO_2057_RFPLL_LOOPFILTER_R2
- RADIO_2057_RFPLL_MASTER
- RADIO_2057_RFPLL_MISC_CAL_RESETN
- RADIO_2057_RFPLL_MISC_EN
- RADIO_2057_RFPLL_MMD0
- RADIO_2057_RFPLL_MMD1
- RADIO_2057_RFPLL_PFD_RESET_PW
- RADIO_2057_RFPLL_REFMASTER_SPAREXTALSIZE
- RADIO_2057_RSSI_GPAIOSEL_W1_IDACS_CORE0
- RADIO_2057_RSSI_GPAIOSEL_W1_IDACS_CORE1
- RADIO_2057_RSSI_MASTER_CORE0
- RADIO_2057_RSSI_MASTER_CORE1
- RADIO_2057_RXBB_BIAS_MASTER_CORE0
- RADIO_2057_RXBB_BIAS_MASTER_CORE1
- RADIO_2057_RXBB_CC_CORE0
- RADIO_2057_RXBB_CC_CORE1
- RADIO_2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE0
- RADIO_2057_RXBB_GPAIOSEL_RXLPF_RCCAL_CORE1
- RADIO_2057_RXBB_RCCAL_HPC_CORE0
- RADIO_2057_RXBB_RCCAL_HPC_CORE1
- RADIO_2057_RXBB_SPARE1_CORE0
- RADIO_2057_RXBB_SPARE1_CORE1
- RADIO_2057_RXBB_SPARE2_CORE0
- RADIO_2057_RXBB_SPARE2_CORE1
- RADIO_2057_RXBB_SPARE3_CORE0
- RADIO_2057_RXBB_SPARE3_CORE1
- RADIO_2057_RXBB_VGABUF_IDACS_CORE0
- RADIO_2057_RXBB_VGABUF_IDACS_CORE1
- RADIO_2057_RXBUF_DEGEN_CORE0
- RADIO_2057_RXBUF_DEGEN_CORE1
- RADIO_2057_RXGM_CMFBITAIL_AUXPTAT_CORE0
- RADIO_2057_RXGM_CMFBITAIL_AUXPTAT_CORE1
- RADIO_2057_RXMIX2G_LODC_QI_CORE0
- RADIO_2057_RXMIX2G_LODC_QI_CORE1
- RADIO_2057_RXMIX2G_PUS_CORE0
- RADIO_2057_RXMIX2G_PUS_CORE1
- RADIO_2057_RXMIX2G_VCMREFS_CORE0
- RADIO_2057_RXMIX2G_VCMREFS_CORE1
- RADIO_2057_RXMIX5G_LODC_QI_CORE0
- RADIO_2057_RXMIX5G_LODC_QI_CORE1
- RADIO_2057_RXMIX5G_PUS_CORE0
- RADIO_2057_RXMIX5G_PUS_CORE1
- RADIO_2057_RXMIX5G_VCMREFS_CORE0
- RADIO_2057_RXMIX5G_VCMREFS_CORE1
- RADIO_2057_RXMIX_CMFBITAIL_PU_CORE0
- RADIO_2057_RXMIX_CMFBITAIL_PU_CORE1
- RADIO_2057_RXMIX_ICORE_RXGM_IAUX_CORE0
- RADIO_2057_RXMIX_ICORE_RXGM_IAUX_CORE1
- RADIO_2057_RXRFBIAS_BANDSEL_CORE0
- RADIO_2057_RXRFBIAS_BANDSEL_CORE1
- RADIO_2057_RXRFBIAS_IBOOST_PU_CORE0
- RADIO_2057_RXRFBIAS_IBOOST_PU_CORE1
- RADIO_2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE0
- RADIO_2057_RXRF_IABAND_RXGM_IMAIN_PTAT_CORE1
- RADIO_2057_RXTXBIAS_CONFIG_CORE0
- RADIO_2057_RXTXBIAS_CONFIG_CORE1
- RADIO_2057_SPARE11_CORE0
- RADIO_2057_SPARE11_CORE1
- RADIO_2057_SPARE12_CORE0
- RADIO_2057_SPARE12_CORE1
- RADIO_2057_SPARE13_CORE0
- RADIO_2057_SPARE13_CORE1
- RADIO_2057_SPARE14_CORE0
- RADIO_2057_SPARE14_CORE1
- RADIO_2057_SPARE15_CORE0
- RADIO_2057_SPARE15_CORE1
- RADIO_2057_SPARE16_CORE0
- RADIO_2057_SPARE16_CORE1
- RADIO_2057_SPARE7_CORE1
- RADIO_2057_SPARE8_CORE1
- RADIO_2057_TEMPSENSE_CONFIG
- RADIO_2057_TIA_CONFIG_CORE0
- RADIO_2057_TIA_CONFIG_CORE1
- RADIO_2057_TIA_IBIAS1_CORE0
- RADIO_2057_TIA_IBIAS1_CORE1
- RADIO_2057_TIA_IBIAS2_CORE0
- RADIO_2057_TIA_IBIAS2_CORE1
- RADIO_2057_TIA_IQGAIN_CORE0
- RADIO_2057_TIA_IQGAIN_CORE1
- RADIO_2057_TIA_SPARE_I_CORE0
- RADIO_2057_TIA_SPARE_I_CORE1
- RADIO_2057_TIA_SPARE_Q_CORE0
- RADIO_2057_TIA_SPARE_Q_CORE1
- RADIO_2057_TR2G_CONFIG1_CORE0_NU
- RADIO_2057_TR2G_CONFIG1_CORE1_NU
- RADIO_2057_TR2G_CONFIG2_CORE0_NU
- RADIO_2057_TR2G_CONFIG2_CORE1_NU
- RADIO_2057_TR5G_CONFIG2_CORE0_NU
- RADIO_2057_TR5G_CONFIG2_CORE1_NU
- RADIO_2057_TSSI2G_SPARE1_CORE0
- RADIO_2057_TSSI2G_SPARE1_CORE1
- RADIO_2057_TSSI2G_SPARE2_CORE0
- RADIO_2057_TSSI2G_SPARE2_CORE1
- RADIO_2057_TSSI5G_SPARE1_CORE0
- RADIO_2057_TSSI5G_SPARE1_CORE1
- RADIO_2057_TSSI5G_SPARE2_CORE0
- RADIO_2057_TSSI5G_SPARE2_CORE1
- RADIO_2057_TX0_IQCAL_GAIN_BW
- RADIO_2057_TX0_IQCAL_IDAC
- RADIO_2057_TX0_IQCAL_VCM_HG
- RADIO_2057_TX0_LOFT_COARSE_I
- RADIO_2057_TX0_LOFT_COARSE_Q
- RADIO_2057_TX0_LOFT_FINE_I
- RADIO_2057_TX0_LOFT_FINE_Q
- RADIO_2057_TX0_TSSIA
- RADIO_2057_TX0_TSSIG
- RADIO_2057_TX0_TSSI_MISC1
- RADIO_2057_TX0_TSSI_VCM
- RADIO_2057_TX0_TXRXCOUPLE_2G_ATTEN
- RADIO_2057_TX0_TXRXCOUPLE_2G_PWRUP
- RADIO_2057_TX0_TXRXCOUPLE_5G_ATTEN
- RADIO_2057_TX0_TXRXCOUPLE_5G_PWRUP
- RADIO_2057_TX0_TX_SSI_MASTER
- RADIO_2057_TX0_TX_SSI_MUX
- RADIO_2057_TX1_IQCAL_GAIN_BW
- RADIO_2057_TX1_IQCAL_IDAC
- RADIO_2057_TX1_IQCAL_VCM_HG
- RADIO_2057_TX1_LOFT_COARSE_I
- RADIO_2057_TX1_LOFT_COARSE_Q
- RADIO_2057_TX1_LOFT_FINE_I
- RADIO_2057_TX1_LOFT_FINE_Q
- RADIO_2057_TX1_TSSIA
- RADIO_2057_TX1_TSSIG
- RADIO_2057_TX1_TSSI_MISC1
- RADIO_2057_TX1_TSSI_VCM
- RADIO_2057_TX1_TXRXCOUPLE_2G_ATTEN
- RADIO_2057_TX1_TXRXCOUPLE_2G_PWRUP
- RADIO_2057_TX1_TXRXCOUPLE_5G_ATTEN
- RADIO_2057_TX1_TXRXCOUPLE_5G_PWRUP
- RADIO_2057_TX1_TX_SSI_MASTER
- RADIO_2057_TX1_TX_SSI_MUX
- RADIO_2057_TX2G_BIAS_RESETS_CORE0
- RADIO_2057_TX2G_BIAS_RESETS_CORE1
- RADIO_2057_TX5G_BIAS_RESETS_CORE0
- RADIO_2057_TX5G_BIAS_RESETS_CORE1
- RADIO_2057_TX5G_PKDET_CORE0
- RADIO_2057_TX5G_PKDET_CORE1
- RADIO_2057_TXBUF_GAIN_CORE0
- RADIO_2057_TXBUF_GAIN_CORE1
- RADIO_2057_TXBUF_IDACS_CORE0
- RADIO_2057_TXBUF_IDACS_CORE1
- RADIO_2057_TXBUF_VINCM_CORE0
- RADIO_2057_TXBUF_VINCM_CORE1
- RADIO_2057_TXGM2G_PKDET_PUS_CORE0
- RADIO_2057_TXGM2G_PKDET_PUS_CORE1
- RADIO_2057_TXGM_GAIN_CORE0
- RADIO_2057_TXGM_GAIN_CORE1
- RADIO_2057_TXGM_IDAC_BLEED_CORE0
- RADIO_2057_TXGM_IDAC_BLEED_CORE1
- RADIO_2057_TXGM_TXRF_PUS_CORE0
- RADIO_2057_TXGM_TXRF_PUS_CORE1
- RADIO_2057_TXLPF_RCCAL_CORE0
- RADIO_2057_TXLPF_RCCAL_CORE1
- RADIO_2057_TXMIX2G_LODC_CORE0
- RADIO_2057_TXMIX2G_LODC_CORE1
- RADIO_2057_TXMIX2G_TUNE_BOOST_PU_CORE0
- RADIO_2057_TXMIX2G_TUNE_BOOST_PU_CORE1
- RADIO_2057_TXMIX5G_BOOST_TUNE_CORE0
- RADIO_2057_TXMIX5G_BOOST_TUNE_CORE1
- RADIO_2057_TXMIX5G_IBOOST_PAD_IAUX_CORE0
- RADIO_2057_TXMIX5G_IBOOST_PAD_IAUX_CORE1
- RADIO_2057_VCM_MASK
- RADIO_2057_VCOBUF_IDACS
- RADIO_2057_VCOBUF_TUNE
- RADIO_2057_VCOCAL_BIASRESET_RFPLLREG_VOUT
- RADIO_2057_VCOCAL_COUNTVAL0
- RADIO_2057_VCOCAL_COUNTVAL1
- RADIO_2057_VCOCAL_DELAY_AFTER_CLOSELOOP
- RADIO_2057_VCOCAL_DELAY_AFTER_OPENLOOP
- RADIO_2057_VCOCAL_DELAY_AFTER_REFRESH
- RADIO_2057_VCOCAL_DELAY_BEFORE_OPENLOOP
- RADIO_2057_VCOCAL_INTCLK_COUNT
- RADIO_2057_VCOCAL_MASTER
- RADIO_2057_VCOCAL_NUMCAPCHANGE
- RADIO_2057_VCOCAL_READCAP0
- RADIO_2057_VCOCAL_READCAP1
- RADIO_2057_VCOCAL_STATUS
- RADIO_2057_VCOCAL_WINSIZE
- RADIO_2057_VCOMONITOR_VTH_H
- RADIO_2057_VCOMONITOR_VTH_L
- RADIO_2057_VCO_ALCREF_BBPLLXTAL_SIZE
- RADIO_2057_VCO_FORCECAP0
- RADIO_2057_VCO_FORCECAPEN_FORCECAP1
- RADIO_2057_VCO_VARCSIZE_IDAC
- RADIO_2057_W12G_BW_LNA2G_PUS_CORE0
- RADIO_2057_W12G_BW_LNA2G_PUS_CORE1
- RADIO_2057_W15G_BW_LNA5G_PUS_CORE0
- RADIO_2057_W15G_BW_LNA5G_PUS_CORE1
- RADIO_2057_W2_IDACS0_I_CORE0
- RADIO_2057_W2_IDACS0_I_CORE1
- RADIO_2057_W2_IDACS0_Q_CORE0
- RADIO_2057_W2_IDACS0_Q_CORE1
- RADIO_2057_W2_IDACS1_I_CORE0
- RADIO_2057_W2_IDACS1_I_CORE1
- RADIO_2057_W2_IDACS1_Q_CORE0
- RADIO_2057_W2_IDACS1_Q_CORE1
- RADIO_2057_W2_MASTER_CORE0
- RADIO_2057_W2_MASTER_CORE1
- RADIO_2057_XTALPUOVR_PINCTRL
- RADIO_2057_XTAL_BUF_SIZE
- RADIO_2057_XTAL_CONFIG1
- RADIO_2057_XTAL_CONFIG2
- RADIO_2057_XTAL_ICORE_SIZE
- RADIO_2057_XTAL_PULLCAP_SIZE
- RADIO_2057v7_DACBUF_VINCM_CORE0
- RADIO_2057v7_IQTEST_SEL_PU2
- RADIO_2057v7_LOGEN_PUS1
- RADIO_2057v7_OVR_REG1
- RADIO_2057v7_OVR_REG10
- RADIO_2057v7_OVR_REG11
- RADIO_2057v7_OVR_REG12
- RADIO_2057v7_OVR_REG13
- RADIO_2057v7_OVR_REG14
- RADIO_2057v7_OVR_REG15
- RADIO_2057v7_OVR_REG16
- RADIO_2057v7_OVR_REG18
- RADIO_2057v7_OVR_REG19
- RADIO_2057v7_OVR_REG2
- RADIO_2057v7_OVR_REG20
- RADIO_2057v7_OVR_REG21
- RADIO_2057v7_OVR_REG23
- RADIO_2057v7_OVR_REG24
- RADIO_2057v7_OVR_REG25
- RADIO_2057v7_OVR_REG26
- RADIO_2057v7_OVR_REG27
- RADIO_2057v7_OVR_REG28
- RADIO_2057v7_OVR_REG5
- RADIO_2057v7_OVR_REG6
- RADIO_2057v7_OVR_REG7
- RADIO_2057v7_OVR_REG8
- RADIO_2057v7_OVR_REG9
- RADIO_2057v7_RCCAL_MASTER
- RADIO_2057v7_TR2G_CONFIG3_CORE0_NU
- RADIO_2057v7_TR2G_CONFIG3_CORE1_NU
- RADIO_2064_READ_OFF
- RADIO_2064_REG000
- RADIO_2064_REG001
- RADIO_2064_REG002
- RADIO_2064_REG003
- RADIO_2064_REG004
- RADIO_2064_REG005
- RADIO_2064_REG006
- RADIO_2064_REG007
- RADIO_2064_REG008
- RADIO_2064_REG009
- RADIO_2064_REG00A
- RADIO_2064_REG00B
- RADIO_2064_REG00C
- RADIO_2064_REG00D
- RADIO_2064_REG00E
- RADIO_2064_REG00F
- RADIO_2064_REG010
- RADIO_2064_REG011
- RADIO_2064_REG012
- RADIO_2064_REG013
- RADIO_2064_REG014
- RADIO_2064_REG015
- RADIO_2064_REG016
- RADIO_2064_REG017
- RADIO_2064_REG018
- RADIO_2064_REG019
- RADIO_2064_REG01A
- RADIO_2064_REG01B
- RADIO_2064_REG01C
- RADIO_2064_REG01D
- RADIO_2064_REG01E
- RADIO_2064_REG01F
- RADIO_2064_REG020
- RADIO_2064_REG021
- RADIO_2064_REG022
- RADIO_2064_REG023
- RADIO_2064_REG024
- RADIO_2064_REG025
- RADIO_2064_REG026
- RADIO_2064_REG027
- RADIO_2064_REG028
- RADIO_2064_REG029
- RADIO_2064_REG02A
- RADIO_2064_REG02B
- RADIO_2064_REG02C
- RADIO_2064_REG02D
- RADIO_2064_REG02E
- RADIO_2064_REG02F
- RADIO_2064_REG030
- RADIO_2064_REG031
- RADIO_2064_REG032
- RADIO_2064_REG033
- RADIO_2064_REG034
- RADIO_2064_REG035
- RADIO_2064_REG036
- RADIO_2064_REG037
- RADIO_2064_REG038
- RADIO_2064_REG039
- RADIO_2064_REG03A
- RADIO_2064_REG03B
- RADIO_2064_REG03C
- RADIO_2064_REG03D
- RADIO_2064_REG03E
- RADIO_2064_REG03F
- RADIO_2064_REG040
- RADIO_2064_REG041
- RADIO_2064_REG042
- RADIO_2064_REG043
- RADIO_2064_REG044
- RADIO_2064_REG045
- RADIO_2064_REG046
- RADIO_2064_REG047
- RADIO_2064_REG048
- RADIO_2064_REG049
- RADIO_2064_REG04A
- RADIO_2064_REG04B
- RADIO_2064_REG04C
- RADIO_2064_REG04D
- RADIO_2064_REG04E
- RADIO_2064_REG04F
- RADIO_2064_REG050
- RADIO_2064_REG051
- RADIO_2064_REG052
- RADIO_2064_REG053
- RADIO_2064_REG054
- RADIO_2064_REG055
- RADIO_2064_REG056
- RADIO_2064_REG057
- RADIO_2064_REG058
- RADIO_2064_REG059
- RADIO_2064_REG05A
- RADIO_2064_REG05B
- RADIO_2064_REG05C
- RADIO_2064_REG05D
- RADIO_2064_REG05E
- RADIO_2064_REG05F
- RADIO_2064_REG060
- RADIO_2064_REG061
- RADIO_2064_REG062
- RADIO_2064_REG063
- RADIO_2064_REG064
- RADIO_2064_REG065
- RADIO_2064_REG066
- RADIO_2064_REG067
- RADIO_2064_REG068
- RADIO_2064_REG069
- RADIO_2064_REG06A
- RADIO_2064_REG06B
- RADIO_2064_REG06C
- RADIO_2064_REG06D
- RADIO_2064_REG06E
- RADIO_2064_REG06F
- RADIO_2064_REG070
- RADIO_2064_REG071
- RADIO_2064_REG072
- RADIO_2064_REG073
- RADIO_2064_REG074
- RADIO_2064_REG075
- RADIO_2064_REG076
- RADIO_2064_REG077
- RADIO_2064_REG078
- RADIO_2064_REG079
- RADIO_2064_REG07A
- RADIO_2064_REG07B
- RADIO_2064_REG07C
- RADIO_2064_REG07D
- RADIO_2064_REG07E
- RADIO_2064_REG07F
- RADIO_2064_REG080
- RADIO_2064_REG081
- RADIO_2064_REG082
- RADIO_2064_REG083
- RADIO_2064_REG084
- RADIO_2064_REG085
- RADIO_2064_REG086
- RADIO_2064_REG087
- RADIO_2064_REG088
- RADIO_2064_REG089
- RADIO_2064_REG08A
- RADIO_2064_REG08B
- RADIO_2064_REG08C
- RADIO_2064_REG08D
- RADIO_2064_REG08E
- RADIO_2064_REG08F
- RADIO_2064_REG090
- RADIO_2064_REG091
- RADIO_2064_REG092
- RADIO_2064_REG093
- RADIO_2064_REG094
- RADIO_2064_REG095
- RADIO_2064_REG096
- RADIO_2064_REG097
- RADIO_2064_REG098
- RADIO_2064_REG099
- RADIO_2064_REG09A
- RADIO_2064_REG09B
- RADIO_2064_REG09C
- RADIO_2064_REG09D
- RADIO_2064_REG09E
- RADIO_2064_REG09F
- RADIO_2064_REG0A0
- RADIO_2064_REG0A1
- RADIO_2064_REG0A2
- RADIO_2064_REG0A3
- RADIO_2064_REG0A4
- RADIO_2064_REG0A5
- RADIO_2064_REG0A6
- RADIO_2064_REG0A7
- RADIO_2064_REG0A8
- RADIO_2064_REG0A9
- RADIO_2064_REG0AA
- RADIO_2064_REG0AB
- RADIO_2064_REG0AC
- RADIO_2064_REG0AD
- RADIO_2064_REG0AE
- RADIO_2064_REG0AF
- RADIO_2064_REG0B0
- RADIO_2064_REG0B1
- RADIO_2064_REG0B2
- RADIO_2064_REG0B3
- RADIO_2064_REG0B4
- RADIO_2064_REG0B5
- RADIO_2064_REG0B6
- RADIO_2064_REG0B7
- RADIO_2064_REG0B8
- RADIO_2064_REG0B9
- RADIO_2064_REG0BA
- RADIO_2064_REG0BB
- RADIO_2064_REG0BC
- RADIO_2064_REG0BD
- RADIO_2064_REG0BE
- RADIO_2064_REG0BF
- RADIO_2064_REG0C0
- RADIO_2064_REG0C1
- RADIO_2064_REG0C2
- RADIO_2064_REG0C3
- RADIO_2064_REG0C4
- RADIO_2064_REG0C5
- RADIO_2064_REG0C6
- RADIO_2064_REG0C7
- RADIO_2064_REG0C8
- RADIO_2064_REG0C9
- RADIO_2064_REG0CA
- RADIO_2064_REG0CB
- RADIO_2064_REG0CC
- RADIO_2064_REG0CD
- RADIO_2064_REG0CE
- RADIO_2064_REG0CF
- RADIO_2064_REG0D0
- RADIO_2064_REG0D1
- RADIO_2064_REG0D2
- RADIO_2064_REG0D3
- RADIO_2064_REG0D4
- RADIO_2064_REG0D5
- RADIO_2064_REG0D6
- RADIO_2064_REG0D7
- RADIO_2064_REG0D8
- RADIO_2064_REG0D9
- RADIO_2064_REG0DA
- RADIO_2064_REG0DB
- RADIO_2064_REG0DC
- RADIO_2064_REG0DD
- RADIO_2064_REG0DE
- RADIO_2064_REG0DF
- RADIO_2064_REG0E0
- RADIO_2064_REG0E1
- RADIO_2064_REG0E2
- RADIO_2064_REG0E3
- RADIO_2064_REG0E4
- RADIO_2064_REG0E5
- RADIO_2064_REG0E6
- RADIO_2064_REG0E7
- RADIO_2064_REG0E8
- RADIO_2064_REG0E9
- RADIO_2064_REG0EA
- RADIO_2064_REG0EB
- RADIO_2064_REG0EC
- RADIO_2064_REG0ED
- RADIO_2064_REG0EE
- RADIO_2064_REG0EF
- RADIO_2064_REG0F0
- RADIO_2064_REG0F1
- RADIO_2064_REG0F2
- RADIO_2064_REG0F3
- RADIO_2064_REG0F4
- RADIO_2064_REG0F5
- RADIO_2064_REG0F6
- RADIO_2064_REG0F7
- RADIO_2064_REG0F8
- RADIO_2064_REG0F9
- RADIO_2064_REG0FA
- RADIO_2064_REG0FB
- RADIO_2064_REG0FC
- RADIO_2064_REG0FD
- RADIO_2064_REG0FE
- RADIO_2064_REG0FF
- RADIO_2064_REG100
- RADIO_2064_REG101
- RADIO_2064_REG102
- RADIO_2064_REG103
- RADIO_2064_REG104
- RADIO_2064_REG105
- RADIO_2064_REG106
- RADIO_2064_REG107
- RADIO_2064_REG108
- RADIO_2064_REG109
- RADIO_2064_REG10A
- RADIO_2064_REG10B
- RADIO_2064_REG10C
- RADIO_2064_REG10D
- RADIO_2064_REG10E
- RADIO_2064_REG10F
- RADIO_2064_REG110
- RADIO_2064_REG111
- RADIO_2064_REG112
- RADIO_2064_REG113
- RADIO_2064_REG114
- RADIO_2064_REG115
- RADIO_2064_REG116
- RADIO_2064_REG117
- RADIO_2064_REG118
- RADIO_2064_REG119
- RADIO_2064_REG11A
- RADIO_2064_REG11B
- RADIO_2064_REG11C
- RADIO_2064_REG11D
- RADIO_2064_REG11E
- RADIO_2064_REG11F
- RADIO_2064_REG120
- RADIO_2064_REG121
- RADIO_2064_REG122
- RADIO_2064_REG123
- RADIO_2064_REG124
- RADIO_2064_REG125
- RADIO_2064_REG126
- RADIO_2064_REG127
- RADIO_2064_REG128
- RADIO_2064_REG129
- RADIO_2064_REG12A
- RADIO_2064_REG12B
- RADIO_2064_REG12C
- RADIO_2064_REG12D
- RADIO_2064_REG12E
- RADIO_2064_REG12F
- RADIO_2064_REG130
- RADIO_BAND_2_4GHZ
- RADIO_BAND_5GHZ
- RADIO_BAND_JAPAN_4_9_GHZ
- RADIO_CAPABILITIES
- RADIO_CFG
- RADIO_CFG_FAMILY_EXT_NVM
- RADIO_DEFAULT_CORE
- RADIO_DS
- RADIO_FH
- RADIO_FW_VERSION
- RADIO_HW_VERSION
- RADIO_IDCODE
- RADIO_LED_ON
- RADIO_MIMO_CORESEL_ALLRX
- RADIO_MIMO_CORESEL_ALLRXTX
- RADIO_MIMO_CORESEL_ALLTX
- RADIO_MIMO_CORESEL_CORE1
- RADIO_MIMO_CORESEL_CORE2
- RADIO_MIMO_CORESEL_CORE3
- RADIO_MIMO_CORESEL_CORE4
- RADIO_MIMO_CORESEL_OFF
- RADIO_OFF
- RADIO_OFF_ADVANCE
- RADIO_OFF_AUTO_WAKEUP
- RADIO_ON
- RADIO_ON_ADVANCE
- RADIO_PARAMS_UPDATE
- RADIO_PREAMBLE_AUTO
- RADIO_PREAMBLE_LONG
- RADIO_PREAMBLE_SHORT
- RADIO_REGISTER_NUM
- RADIO_REGISTER_SIZE
- RADIO_REG_MAX_READ
- RADIO_REG_SYS_MANUAL_DFT_0
- RADIO_RSP_ADDR_POS
- RADIO_RSP_RD_CMD
- RADIO_TEA5764_XTAL
- RADIO_TMA
- RADIX_BASE
- RADIX_KERN_IO_END
- RADIX_KERN_IO_SIZE
- RADIX_KERN_IO_START
- RADIX_KERN_MAP_SIZE
- RADIX_KERN_VIRT_START
- RADIX_PGD_BAD_BITS
- RADIX_PGD_INDEX_SIZE
- RADIX_PGD_SHIFT
- RADIX_PGD_TABLE_SIZE
- RADIX_PGD_VAL_BITS
- RADIX_PGTABLE_EADDR_SIZE
- RADIX_PGTABLE_RANGE
- RADIX_PMD_BAD_BITS
- RADIX_PMD_FRAG_NR
- RADIX_PMD_FRAG_SIZE_SHIFT
- RADIX_PMD_INDEX_SIZE
- RADIX_PMD_SHIFT
- RADIX_PMD_TABLE_SIZE
- RADIX_PMD_VAL_BITS
- RADIX_PTE_FRAG_NR
- RADIX_PTE_FRAG_SIZE_SHIFT
- RADIX_PTE_INDEX_SIZE
- RADIX_PTE_NONE_MASK
- RADIX_PTE_TABLE_SIZE
- RADIX_PUD_BAD_BITS
- RADIX_PUD_INDEX_SIZE
- RADIX_PUD_SHIFT
- RADIX_PUD_TABLE_SIZE
- RADIX_PUD_VAL_BITS
- RADIX_TREE
- RADIX_TREE_ENTRY_MASK
- RADIX_TREE_INDEX_BITS
- RADIX_TREE_INIT
- RADIX_TREE_INTERNAL_NODE
- RADIX_TREE_ITER_CONTIG
- RADIX_TREE_ITER_TAGGED
- RADIX_TREE_ITER_TAG_MASK
- RADIX_TREE_MAP_MASK
- RADIX_TREE_MAP_SHIFT
- RADIX_TREE_MAP_SIZE
- RADIX_TREE_MAX_PATH
- RADIX_TREE_MAX_TAGS
- RADIX_TREE_PRELOAD_SIZE
- RADIX_TREE_RETRY
- RADIX_TREE_TAG_LONGS
- RADIX_VMALLOC_END
- RADIX_VMALLOC_SIZE
- RADIX_VMALLOC_START
- RADIX_VMEMMAP_END
- RADIX_VMEMMAP_SIZE
- RADIX_VMEMMAP_START
- RAF0_BCSTREJ
- RAF0_MCSTREJ
- RAF0_RST
- RAGCN_ATTACK
- RAGCN_DECAY
- RAGC_CTRL_A
- RAGC_CTRL_B
- RAGC_CTRL_C
- RAGE128_MPP_TB_CONFIG
- RAH1
- RAH2
- RAID0_ALT_MULTIZONE_LAYOUT
- RAID0_ORIG_LAYOUT
- RAID0_VALID_FLAGS
- RAID10_BROCKEN_USE_FAR_SETS
- RAID10_FAR_COPIES_SHIFT
- RAID10_OFFSET
- RAID10_USE_FAR_SETS
- RAID10_VALID_FLAGS
- RAID1_VALID_FLAGS
- RAID45_VALID_FLAGS
- RAID5_P_STRIPE
- RAID6_NEON_WRAPPER
- RAID6_OK
- RAID6_PQ_BAD
- RAID6_P_BAD
- RAID6_Q_BAD
- RAID6_Q_STRIPE
- RAID6_TIME_JIFFIES_LG2
- RAID6_USE_EMPTY_ZERO_PAGE
- RAID6_VALID_FLAGS
- RAID_1_PEER_CMDS
- RAID_AUTORUN
- RAID_BYPASS_CONFIGURED
- RAID_BYPASS_ENABLED
- RAID_BYPASS_STATUS
- RAID_CHANNEL
- RAID_CONTEXT
- RAID_CONTEXT_G35
- RAID_CONTEXT_NSEG_MASK
- RAID_CONTEXT_NSEG_SHIFT
- RAID_CONTEXT_TYPE_MASK
- RAID_CONTEXT_TYPE_SHIFT
- RAID_CONTEXT_UNION
- RAID_CTLR_LUNID
- RAID_CTX_R56_LOG_ARM_MASK
- RAID_CTX_R56_LOG_ARM_SHIFT
- RAID_CTX_R56_P_ARM_MASK
- RAID_CTX_R56_P_ARM_SHIFT
- RAID_CTX_R56_Q_ARM_MASK
- RAID_CTX_SPANARM_ARM_MASK
- RAID_CTX_SPANARM_ARM_SHIFT
- RAID_CTX_SPANARM_SPAN_MASK
- RAID_CTX_SPANARM_SPAN_SHIFT
- RAID_LEVEL_0
- RAID_LEVEL_1
- RAID_LEVEL_10
- RAID_LEVEL_1E
- RAID_LEVEL_3
- RAID_LEVEL_4
- RAID_LEVEL_5
- RAID_LEVEL_50
- RAID_LEVEL_6
- RAID_LEVEL_JBOD
- RAID_LEVEL_LINEAR
- RAID_LEVEL_UNKNOWN
- RAID_MAP_DESC_TYPE_ARRAY_INFO
- RAID_MAP_DESC_TYPE_COUNT
- RAID_MAP_DESC_TYPE_DEVHDL_INFO
- RAID_MAP_DESC_TYPE_SPAN_INFO
- RAID_MAP_DESC_TYPE_TGTID_INFO
- RAID_MAP_ENCRYPTION_ENABLED
- RAID_MAP_FLAG_ENCRYPT_ON
- RAID_MAP_MAX_ENTRIES
- RAID_MAX_RESYNC
- RAID_NUM_ATTRS
- RAID_PATH
- RAID_PHYS_DISK0_ERROR_DATA
- RAID_PHYS_DISK0_INQUIRY_DATA
- RAID_PHYS_DISK0_SETTINGS
- RAID_PHYS_DISK0_STATUS
- RAID_PHYS_DISK1_PATH
- RAID_STATE_ACTIVE
- RAID_STATE_DEGRADED
- RAID_STATE_OFFLINE
- RAID_STATE_RESYNCING
- RAID_STATE_UNKNOWN
- RAID_UNKNOWN
- RAID_VERSION
- RAID_VOL0_PHYS_DISK
- RAID_VOL0_SETTINGS
- RAID_VOL0_STATUS
- RAIL_LDO
- RAIL_SD
- RAISE
- RAL
- RAL1
- RAL2
- RALINKCSR
- RALINKCSR_AR_BBP_DATA0
- RALINKCSR_AR_BBP_DATA1
- RALINKCSR_AR_BBP_ID0
- RALINKCSR_AR_BBP_ID1
- RALINKCSR_AR_BBP_VALID0
- RALINKCSR_AR_BBP_VALID1
- RALINK_CLKCFG1
- RALINK_CPU_IRQ_COUNTER
- RALINK_CPU_IRQ_FE
- RALINK_CPU_IRQ_INTC
- RALINK_CPU_IRQ_PCI
- RALINK_CPU_IRQ_WIFI
- RALINK_GPIOMODE
- RALINK_INTC_IRQ_BASE
- RALINK_INTC_IRQ_COUNT
- RALINK_INTC_IRQ_PERFC
- RALINK_INT_PCIE0
- RALINK_PCI0_BAR0SETUP_ADDR
- RALINK_PCI0_CLASS
- RALINK_PCI0_ID
- RALINK_PCI0_IMBASEBAR0_ADDR
- RALINK_PCI0_STATUS
- RALINK_PCI0_SUBID
- RALINK_PCIE0_CLK_EN
- RALINK_PCIEPHY_P0_CTL_OFFSET
- RALINK_PCIE_CLK_GEN
- RALINK_PCIE_CLK_GEN1
- RALINK_PCI_BAR0SETUP_ADDR
- RALINK_PCI_CLASS
- RALINK_PCI_CONFIG_ADDR
- RALINK_PCI_CONFIG_DATA
- RALINK_PCI_CONFIG_DATA_VIRT_REG
- RALINK_PCI_ID
- RALINK_PCI_IMBASEBAR0_ADDR
- RALINK_PCI_IOBASE
- RALINK_PCI_IO_MAP_BASE
- RALINK_PCI_MEMBASE
- RALINK_PCI_MEMORY_BASE
- RALINK_PCI_PCICFG_ADDR
- RALINK_PCI_PCIENA
- RALINK_PCI_PCIMSK_ADDR
- RALINK_PCI_STATUS
- RALINK_PCI_SUBID
- RALINK_RF
- RALINK_SPI_WAIT_MAX_LOOP
- RALINK_UNKNOWN
- RALINK_WDT_PRESCALE
- RALINK_WDT_TIMEOUT
- RALN
- RALN_ADDR
- RALN_IDX
- RAM
- RAMA_ACCESS
- RAMB_ACCESS
- RAMCFG
- RAMCLK_GATE_D
- RAMCR
- RAMCR_CACHE_L2E
- RAMCR_CACHE_L2FC
- RAMDACTiming
- RAMDAC_BYPASS
- RAMDAC_DAC8BIT
- RAMDAC_DACPWRDN
- RAMDAC_DATA
- RAMDAC_INDEX
- RAMDAC_OFFSET
- RAMDAC_RAMPWRDN
- RAMDAC_VID_32FB_0
- RAMDAC_VID_32FB_1
- RAMDAC_VID_8FB_0
- RAMDAC_VID_8FB_1
- RAMDAC_VID_CFG
- RAMDAC_VID_WH
- RAMDAC_VID_XXXFB
- RAMDAC_VID_YYYFB
- RAMDAC_VID_ZZZFB
- RAMDAC_VREFEN
- RAMDISK_FLAGS
- RAMDISK_IMAGE_START_MASK
- RAMDISK_LOAD_FLAG
- RAMDISK_MAJOR
- RAMDISK_PROMPT_FLAG
- RAMEND
- RAMFS_DEFAULT_MODE
- RAMFS_MAGIC
- RAMIPS_SYS_TYPE_LEN
- RAMOOPS_FLAG_FTRACE_PER_CPU
- RAMOOPS_KERNMSG_HDR
- RAMPDOWN
- RAMPSM
- RAMPUP
- RAMP_DELAY_12_MVUS
- RAMP_RATE_13P75MV
- RAMP_RATE_27P5MV
- RAMP_RATE_55MV
- RAMP_RATE_NO_CTRL
- RAMP_US_TO_CODE
- RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS
- RAMROD_CMD_ID_COMMON_CFC_DEL
- RAMROD_CMD_ID_COMMON_CFC_DEL_WB
- RAMROD_CMD_ID_COMMON_FUNCTION_START
- RAMROD_CMD_ID_COMMON_FUNCTION_STOP
- RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE
- RAMROD_CMD_ID_COMMON_SET_TIMESYNC
- RAMROD_CMD_ID_COMMON_START_TRAFFIC
- RAMROD_CMD_ID_COMMON_STAT_QUERY
- RAMROD_CMD_ID_COMMON_STOP_TRAFFIC
- RAMROD_CMD_ID_COMMON_UNUSED
- RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES
- RAMROD_CMD_ID_ETH_CLIENT_SETUP
- RAMROD_CMD_ID_ETH_CLIENT_UPDATE
- RAMROD_CMD_ID_ETH_EMPTY
- RAMROD_CMD_ID_ETH_FILTER_RULES
- RAMROD_CMD_ID_ETH_FORWARD_SETUP
- RAMROD_CMD_ID_ETH_HALT
- RAMROD_CMD_ID_ETH_MULTICAST_RULES
- RAMROD_CMD_ID_ETH_RSS_UPDATE
- RAMROD_CMD_ID_ETH_SET_MAC
- RAMROD_CMD_ID_ETH_TERMINATE
- RAMROD_CMD_ID_ETH_TPA_UPDATE
- RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP
- RAMROD_CMD_ID_ETH_UNUSED
- RAMROD_COMP_WAIT
- RAMROD_CONT
- RAMROD_DRV_CLR_ONLY
- RAMROD_EXEC
- RAMROD_RESTORE
- RAMROD_RETRY
- RAMROD_RX
- RAMROD_TX
- RAMSIZE_128K
- RAMTOP
- RAM_384K_ACCESS_FROM_TA
- RAM_ADR_RAN
- RAM_BASE
- RAM_BUFFER
- RAM_CLUT
- RAM_DBG_ADDR
- RAM_DBG_ADDR_FR
- RAM_DBG_ADDR_FW
- RAM_DBG_DATA
- RAM_DL_SEL
- RAM_ECC_DB_ERR
- RAM_END
- RAM_FROM_PC
- RAM_INCREMENT
- RAM_IT_FROM_PC
- RAM_IT_TO_PC
- RAM_LINES_TO_BYTES
- RAM_LINES_TO_DWORDS
- RAM_LINE_SIZE
- RAM_OFFSET_MASK
- RAM_SEL_MASK
- RAM_SEL_SHIFT
- RAM_SIZE
- RAM_SPEED
- RAM_SPLIT
- RAM_SZ
- RAM_SZ_16KB
- RAM_SZ_2KB
- RAM_SZ_32KB
- RAM_SZ_4KB
- RAM_SZ_64KB
- RAM_SZ_8KB
- RAM_TEST_DONE
- RAM_TEST_HOST_ERROR
- RAM_TEST_INTRAM_ERROR
- RAM_TEST_MODE
- RAM_TEST_RISC_ERROR
- RAM_TEST_SCSI_ERROR
- RAM_TEST_STATUS
- RAM_TEST_SUCCESS
- RAM_TO_PC
- RAM_WIDTH
- RANDID0
- RANDID1
- RANDID2
- RANDID3
- RANDOM_BOOT_ID
- RANDOM_COUNT
- RANDOM_DATAIN_PDU_OFFSETS
- RANDOM_DATAIN_SEQ_OFFSETS
- RANDOM_DATAOUT_PDU_OFFSETS
- RANDOM_DATA_LIB_BASE
- RANDOM_DPI_DISPLAY_RESOLUTION
- RANDOM_ENTROPY_COUNT
- RANDOM_IRQ
- RANDOM_POOLSIZE
- RANDOM_R2T_OFFSETS
- RANDOM_READ_THRESH
- RANDOM_RSP_SIZE
- RANDOM_SIZE
- RANDOM_SKIP
- RANDOM_UUID
- RANDOM_WRITE
- RANDOM_WRITE_THRESH
- RAND_ACC_IND
- RAND_SEED
- RAND_SEED_MASK
- RAND_SEED_MASK_
- RANGE
- RANGE0_PWM
- RANGE0_PWM_FEEDBACK_DIV
- RANGE0_PWM_FEEDBACK_DIV_MASK
- RANGE0_PWM_FEEDBACK_DIV_SHIFT
- RANGE0_PWM_MASK
- RANGE0_PWM_SHIFT
- RANGE0_SLOW_CLK_FEEDBACK_DIV
- RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK
- RANGE0_SLOW_CLK_FEEDBACK_DIV_SHIFT
- RANGE1_PWM
- RANGE1_PWM_FEEDBACK_DIV
- RANGE1_PWM_FEEDBACK_DIV_MASK
- RANGE1_PWM_FEEDBACK_DIV_SHIFT
- RANGE1_PWM_MASK
- RANGE1_PWM_SHIFT
- RANGE2_PWM
- RANGE2_PWM_FEEDBACK_DIV
- RANGE2_PWM_FEEDBACK_DIV_MASK
- RANGE2_PWM_FEEDBACK_DIV_SHIFT
- RANGE2_PWM_MASK
- RANGE2_PWM_SHIFT
- RANGE3_PWM
- RANGE3_PWM_MASK
- RANGE3_PWM_SHIFT
- RANGEOK
- RANGE_00
- RANGE_0_133_FT
- RANGE_0_40_M
- RANGE_122_162_M
- RANGE_133_266_FT
- RANGE_162_200_M
- RANGE_266_399_FT
- RANGE_399_533_FT
- RANGE_40_81_M
- RANGE_533_655_FT
- RANGE_81_122_M
- RANGE_BOUNDARY_HOLE
- RANGE_BOUNDARY_PREALLOC_EXTENT
- RANGE_BOUNDARY_WRITTEN_EXTENT
- RANGE_CAL_I2C_ADDR
- RANGE_CHECK
- RANGE_CORE
- RANGE_EN
- RANGE_FF
- RANGE_FROM_REG
- RANGE_HAS_ACCUMULATOR
- RANGE_HAS_IRQ
- RANGE_LENGTH
- RANGE_MACHINE
- RANGE_MAX
- RANGE_MAX_IRQS
- RANGE_MULTI_QUEUE
- RANGE_NUM
- RANGE_OFFSET
- RANGE_PACKAGE
- RANGE_PM_16g
- RANGE_PM_2g
- RANGE_PM_4g
- RANGE_PM_8g
- RANGE_PROTECTION_FAULT_ENABLE_DEFAULT
- RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT
- RANGE_PWM_FEEDBACK_DIV_EN
- RANGE_RESERVED
- RANGE_SLOW_CLK_FEEDBACK_DIV_EN
- RANGE_THREAD
- RANGE_TO_REG
- RANGE_ext
- RANGE_mA
- RANGE_unitless
- RANKOFFSET
- RANKOFFSET_MASK
- RANK_B0_BASE
- RANK_CNT_BITS
- RANK_DISABLE
- RANK_EVEN_ERR_CNT
- RANK_EVEN_ERR_THRSLD
- RANK_EVEN_OV
- RANK_MAX_VAL_MASK
- RANK_ODD_ERR_CNT
- RANK_ODD_ERR_THRSLD
- RANK_ODD_OV
- RANK_PRESENT_MASK
- RANK_WIDTH_BITS
- RANN_FLAG_IS_GATE
- RAOPT
- RAP
- RAPK
- RAPL_AMD_F17H
- RAPL_CNTR_WIDTH
- RAPL_CORES
- RAPL_CORES_ENERGY_STATUS
- RAPL_CORES_POWER_LIMIT
- RAPL_CORE_POLICY
- RAPL_DOMAIN_DRAM
- RAPL_DOMAIN_MAX
- RAPL_DOMAIN_PACKAGE
- RAPL_DOMAIN_PLATFORM
- RAPL_DOMAIN_PP0
- RAPL_DOMAIN_PP1
- RAPL_DOMAIN_REG_INFO
- RAPL_DOMAIN_REG_LIMIT
- RAPL_DOMAIN_REG_MAX
- RAPL_DOMAIN_REG_PERF
- RAPL_DOMAIN_REG_POLICY
- RAPL_DOMAIN_REG_STATUS
- RAPL_DRAM
- RAPL_DRAM_PERF_STATUS
- RAPL_DRAM_POWER_INFO
- RAPL_EVENT_ATTR_STR
- RAPL_EVENT_MASK
- RAPL_GFX
- RAPL_PER_CORE_ENERGY
- RAPL_PKG
- RAPL_PKG_PERF_STATUS
- RAPL_PKG_POWER_INFO
- RAPL_POWER_GRANULARITY
- RAPL_PRIMITIVE_DERIVED
- RAPL_PRIMITIVE_DUMMY
- RAPL_TIME_GRANULARITY
- RAP_RAP
- RAQ
- RAQ2_SCSI_IRQ
- RARE_INST
- RARFRC
- RARL
- RARROW_CHAR
- RARU
- RAR_IDX
- RAR_SUCCESS
- RAR_VB
- RAS
- RAS0
- RAS0_DCD_XHLT
- RAS0_VCSEL
- RAS0_VPSEL
- RAS1
- RAS1_UTREG
- RAS2
- RAS2_NNI
- RAS2_UBS
- RAS2_USEL
- RASENABLES
- RASL_MARK
- RASPBERRYPI_FREQ_INTERVAL
- RASSERT
- RASTER_CONFIG_PKR_MAP_0
- RASTER_CONFIG_PKR_MAP_1
- RASTER_CONFIG_PKR_MAP_2
- RASTER_CONFIG_PKR_MAP_3
- RASTER_CONFIG_PKR_XSEL2_0
- RASTER_CONFIG_PKR_XSEL2_1
- RASTER_CONFIG_PKR_XSEL2_2
- RASTER_CONFIG_PKR_XSEL2_3
- RASTER_CONFIG_PKR_XSEL_0
- RASTER_CONFIG_PKR_XSEL_1
- RASTER_CONFIG_PKR_XSEL_2
- RASTER_CONFIG_PKR_XSEL_3
- RASTER_CONFIG_PKR_YSEL_0
- RASTER_CONFIG_PKR_YSEL_1
- RASTER_CONFIG_PKR_YSEL_2
- RASTER_CONFIG_PKR_YSEL_3
- RASTER_CONFIG_RB_MAP_0
- RASTER_CONFIG_RB_MAP_1
- RASTER_CONFIG_RB_MAP_2
- RASTER_CONFIG_RB_MAP_3
- RASTER_CONFIG_RB_XSEL2_0
- RASTER_CONFIG_RB_XSEL2_1
- RASTER_CONFIG_RB_XSEL2_2
- RASTER_CONFIG_RB_XSEL2_3
- RASTER_CONFIG_RB_XSEL_0
- RASTER_CONFIG_RB_XSEL_1
- RASTER_CONFIG_RB_YSEL_0
- RASTER_CONFIG_RB_YSEL_1
- RASTER_CONFIG_SC_MAP_0
- RASTER_CONFIG_SC_MAP_1
- RASTER_CONFIG_SC_MAP_2
- RASTER_CONFIG_SC_MAP_3
- RASTER_CONFIG_SC_XSEL_16_WIDE_TILE
- RASTER_CONFIG_SC_XSEL_32_WIDE_TILE
- RASTER_CONFIG_SC_XSEL_64_WIDE_TILE
- RASTER_CONFIG_SC_XSEL_8_WIDE_TILE
- RASTER_CONFIG_SC_YSEL_16_WIDE_TILE
- RASTER_CONFIG_SC_YSEL_32_WIDE_TILE
- RASTER_CONFIG_SC_YSEL_64_WIDE_TILE
- RASTER_CONFIG_SC_YSEL_8_WIDE_TILE
- RASTER_CONFIG_SE_MAP_0
- RASTER_CONFIG_SE_MAP_1
- RASTER_CONFIG_SE_MAP_2
- RASTER_CONFIG_SE_MAP_3
- RASTER_CONFIG_SE_PAIR_MAP_0
- RASTER_CONFIG_SE_PAIR_MAP_1
- RASTER_CONFIG_SE_PAIR_MAP_2
- RASTER_CONFIG_SE_PAIR_MAP_3
- RASTER_CONFIG_SE_PAIR_XSEL_128_WIDE_TILE
- RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE
- RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE
- RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE
- RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE
- RASTER_CONFIG_SE_PAIR_YSEL_128_WIDE_TILE
- RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE
- RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE
- RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE
- RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE
- RASTER_CONFIG_SE_XSEL_128_WIDE_TILE
- RASTER_CONFIG_SE_XSEL_16_WIDE_TILE
- RASTER_CONFIG_SE_XSEL_32_WIDE_TILE
- RASTER_CONFIG_SE_XSEL_64_WIDE_TILE
- RASTER_CONFIG_SE_XSEL_8_WIDE_TILE
- RASTER_CONFIG_SE_YSEL_128_WIDE_TILE
- RASTER_CONFIG_SE_YSEL_16_WIDE_TILE
- RASTER_CONFIG_SE_YSEL_32_WIDE_TILE
- RASTER_CONFIG_SE_YSEL_64_WIDE_TILE
- RASTER_CONFIG_SE_YSEL_8_WIDE_TILE
- RASU_MARK
- RAS_24M_CLK_ENB
- RAS_32K_CLK_ENB
- RAS_48M_CLK_ENB
- RAS_4X4_PRIM
- RAS_4X4_TILES
- RAS_8X4_4X8_PRIM
- RAS_8X8_PRIM
- RAS_8X8_TILES
- RAS_AHB_CLK_ENB
- RAS_APB_CLK_ENB
- RAS_BASE
- RAS_BCI_SIGNATURE0__SIGNATURE_MASK
- RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT
- RAS_BCI_SIGNATURE1__SIGNATURE_MASK
- RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT
- RAS_BUSY_CYCLES
- RAS_CATFAT_ERROR
- RAS_CATFAT_ERROR_MASK
- RAS_CB_SIGNATURE0__SIGNATURE_MASK
- RAS_CB_SIGNATURE0__SIGNATURE__SHIFT
- RAS_CLK_ENB
- RAS_DB_SIGNATURE0__SIGNATURE_MASK
- RAS_DB_SIGNATURE0__SIGNATURE__SHIFT
- RAS_DEFAULT_FLAGS
- RAS_ERROR_INJECT
- RAS_FULLY_COVERED_8X8_TILES
- RAS_FULLY_COVERED_SUPER_TILES
- RAS_GLOBAL_STATUS_HI__NBIF1PortAErr_MASK
- RAS_GLOBAL_STATUS_HI__NBIF1PortAErr__SHIFT
- RAS_GLOBAL_STATUS_HI__NBIF1PortBErr_MASK
- RAS_GLOBAL_STATUS_HI__NBIF1PortBErr__SHIFT
- RAS_GLOBAL_STATUS_HI__PCIE0PortAErr_MASK
- RAS_GLOBAL_STATUS_HI__PCIE0PortAErr__SHIFT
- RAS_GLOBAL_STATUS_HI__PCIE0PortBErr_MASK
- RAS_GLOBAL_STATUS_HI__PCIE0PortBErr__SHIFT
- RAS_GLOBAL_STATUS_HI__PCIE0PortCErr_MASK
- RAS_GLOBAL_STATUS_HI__PCIE0PortCErr__SHIFT
- RAS_GLOBAL_STATUS_HI__PCIE0PortDErr_MASK
- RAS_GLOBAL_STATUS_HI__PCIE0PortDErr__SHIFT
- RAS_GLOBAL_STATUS_HI__PCIE0PortEErr_MASK
- RAS_GLOBAL_STATUS_HI__PCIE0PortEErr__SHIFT
- RAS_GLOBAL_STATUS_HI__PCIE0PortFErr_MASK
- RAS_GLOBAL_STATUS_HI__PCIE0PortFErr__SHIFT
- RAS_GLOBAL_STATUS_HI__PCIE0PortGErr_MASK
- RAS_GLOBAL_STATUS_HI__PCIE0PortGErr__SHIFT
- RAS_GLOBAL_STATUS_LO__APML_NMI_MASK
- RAS_GLOBAL_STATUS_LO__APML_NMI__SHIFT
- RAS_GLOBAL_STATUS_LO__APML_SyncFld_MASK
- RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private_MASK
- RAS_GLOBAL_STATUS_LO__APML_SyncFld_Private__SHIFT
- RAS_GLOBAL_STATUS_LO__APML_SyncFld__SHIFT
- RAS_GLOBAL_STATUS_LO__HPLGWA_NMI_MASK
- RAS_GLOBAL_STATUS_LO__HPLGWA_NMI__SHIFT
- RAS_GLOBAL_STATUS_LO__HPLGWA_SCI_MASK
- RAS_GLOBAL_STATUS_LO__HPLGWA_SCI__SHIFT
- RAS_GLOBAL_STATUS_LO__HPLGWA_SMI_MASK
- RAS_GLOBAL_STATUS_LO__HPLGWA_SMI__SHIFT
- RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI_MASK
- RAS_GLOBAL_STATUS_LO__PIN_SyncFld_NMI__SHIFT
- RAS_GLOBAL_STATUS_LO__ParityErrCorr_MASK
- RAS_GLOBAL_STATUS_LO__ParityErrCorr__SHIFT
- RAS_GLOBAL_STATUS_LO__ParityErrFatal_MASK
- RAS_GLOBAL_STATUS_LO__ParityErrFatal__SHIFT
- RAS_GLOBAL_STATUS_LO__ParityErrNonFatal_MASK
- RAS_GLOBAL_STATUS_LO__ParityErrNonFatal__SHIFT
- RAS_GLOBAL_STATUS_LO__ParityErrSerr_MASK
- RAS_GLOBAL_STATUS_LO__ParityErrSerr__SHIFT
- RAS_GLOBAL_STATUS_LO__SW_NMI_MASK
- RAS_GLOBAL_STATUS_LO__SW_NMI__SHIFT
- RAS_GLOBAL_STATUS_LO__SW_SCI_MASK
- RAS_GLOBAL_STATUS_LO__SW_SCI__SHIFT
- RAS_GLOBAL_STATUS_LO__SW_SMI_MASK
- RAS_GLOBAL_STATUS_LO__SW_SMI__SHIFT
- RAS_H
- RAS_IA_SIGNATURE0__SIGNATURE_MASK
- RAS_IA_SIGNATURE0__SIGNATURE__SHIFT
- RAS_IA_SIGNATURE1__SIGNATURE_MASK
- RAS_IA_SIGNATURE1__SIGNATURE__SHIFT
- RAS_MARK
- RAS_NONFAT_ERROR
- RAS_NONFAT_ERROR_MASK
- RAS_PA_SIGNATURE0__SIGNATURE_MASK
- RAS_PA_SIGNATURE0__SIGNATURE__SHIFT
- RAS_PLL1_CLK_ENB
- RAS_PLL2_CLK_ENB
- RAS_PORT
- RAS_SCRATCH_0__SCRATCH_0_MASK
- RAS_SCRATCH_0__SCRATCH_0__SHIFT
- RAS_SCRATCH_1__SCRATCH_1_MASK
- RAS_SCRATCH_1__SCRATCH_1__SHIFT
- RAS_SC_SIGNATURE0__SIGNATURE_MASK
- RAS_SC_SIGNATURE0__SIGNATURE__SHIFT
- RAS_SC_SIGNATURE1__SIGNATURE_MASK
- RAS_SC_SIGNATURE1__SIGNATURE__SHIFT
- RAS_SC_SIGNATURE2__SIGNATURE_MASK
- RAS_SC_SIGNATURE2__SIGNATURE__SHIFT
- RAS_SC_SIGNATURE3__SIGNATURE_MASK
- RAS_SC_SIGNATURE3__SIGNATURE__SHIFT
- RAS_SC_SIGNATURE4__SIGNATURE_MASK
- RAS_SC_SIGNATURE4__SIGNATURE__SHIFT
- RAS_SC_SIGNATURE5__SIGNATURE_MASK
- RAS_SC_SIGNATURE5__SIGNATURE__SHIFT
- RAS_SC_SIGNATURE6__SIGNATURE_MASK
- RAS_SC_SIGNATURE6__SIGNATURE__SHIFT
- RAS_SC_SIGNATURE7__SIGNATURE_MASK
- RAS_SC_SIGNATURE7__SIGNATURE__SHIFT
- RAS_SIGNATURE_CONTROL__ENABLE_MASK
- RAS_SIGNATURE_CONTROL__ENABLE__SHIFT
- RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK
- RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT
- RAS_SPI_SIGNATURE0__SIGNATURE_MASK
- RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT
- RAS_SPI_SIGNATURE1__SIGNATURE_MASK
- RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT
- RAS_SQ_SIGNATURE0__SIGNATURE_MASK
- RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT
- RAS_STALL_CYCLES_BY_RB
- RAS_STALL_CYCLES_BY_VSC
- RAS_STARVE_CYCLES_BY_TSE
- RAS_SUPERTILE_CYCLES
- RAS_SUPER_TILES
- RAS_SX_SIGNATURE0__SIGNATURE_MASK
- RAS_SX_SIGNATURE0__SIGNATURE__SHIFT
- RAS_SX_SIGNATURE1__SIGNATURE_MASK
- RAS_SX_SIGNATURE1__SIGNATURE__SHIFT
- RAS_SX_SIGNATURE2__SIGNATURE_MASK
- RAS_SX_SIGNATURE2__SIGNATURE__SHIFT
- RAS_SX_SIGNATURE3__SIGNATURE_MASK
- RAS_SX_SIGNATURE3__SIGNATURE__SHIFT
- RAS_SYNT0_CLK_ENB
- RAS_SYNT1_CLK_ENB
- RAS_SYNT2_CLK_ENB
- RAS_SYNT3_CLK_ENB
- RAS_TA_SIGNATURE0__SIGNATURE_MASK
- RAS_TA_SIGNATURE0__SIGNATURE__SHIFT
- RAS_TA_SIGNATURE1__SIGNATURE_MASK
- RAS_TA_SIGNATURE1__SIGNATURE__SHIFT
- RAS_TD_SIGNATURE0__SIGNATURE_MASK
- RAS_TD_SIGNATURE0__SIGNATURE__SHIFT
- RAS_TILE_CYCLES
- RAS_UMC_INJECT_ADDR_LIMIT
- RAS_VGT_SIGNATURE0__SIGNATURE_MASK
- RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT
- RATE
- RATE155
- RATE25
- RATECTRL
- RATEEST_HSIZE
- RATEID_IDX
- RATEID_IDX_B
- RATEID_IDX_BG
- RATEID_IDX_BGN_20M_1SS_BN
- RATEID_IDX_BGN_20M_2SS_BN
- RATEID_IDX_BGN_3SS
- RATEID_IDX_BGN_40M_1SS
- RATEID_IDX_BGN_40M_2SS
- RATEID_IDX_G
- RATEID_IDX_GN_N1SS
- RATEID_IDX_GN_N2SS
- RATEID_IDX_MIX1
- RATEID_IDX_MIX2
- RATEID_IDX_VHT_1SS
- RATEID_IDX_VHT_2SS
- RATEID_IDX_VHT_3SS
- RATELIMIT_CALC_SHIFT
- RATELIMIT_MSG_ON_RELEASE
- RATELIMIT_STATE_INIT
- RATELIMIT_STATE_INIT_DISABLED
- RATESIZE
- RATES_24_OFFS
- RATES_52_OFFS
- RATES_MASK
- RATES_MASK_3945
- RATETAB_ENT
- RATE_100M
- RATE_10G
- RATE_10M
- RATE_11025
- RATE_11M
- RATE_11MBPS
- RATE_11M_IDX
- RATE_11M_IDX_TBL
- RATE_11M_IEEE
- RATE_11M_MASK
- RATE_11M_PLCP
- RATE_11Mb
- RATE_12000
- RATE_12M
- RATE_12MBPS
- RATE_12M_IDX
- RATE_12M_IDX_TBL
- RATE_12M_IEEE
- RATE_12M_MASK
- RATE_12M_PLCP
- RATE_12Mb
- RATE_14700
- RATE_16000
- RATE_17640
- RATE_18M
- RATE_18MBPS
- RATE_18M_IDX
- RATE_18M_IDX_TBL
- RATE_18M_IEEE
- RATE_18M_MASK
- RATE_18M_PLCP
- RATE_18Mb
- RATE_19200
- RATE_1G
- RATE_1M
- RATE_1MBPS
- RATE_1M_IDX
- RATE_1M_IDX_TBL
- RATE_1M_IEEE
- RATE_1M_MASK
- RATE_1M_PLCP
- RATE_1Mb
- RATE_22050
- RATE_22MBPS
- RATE_24000
- RATE_24M
- RATE_24MBPS
- RATE_24M_IDX
- RATE_24M_IDX_TBL
- RATE_24M_IEEE
- RATE_24M_MASK
- RATE_24M_PLCP
- RATE_24Mb
- RATE_25G
- RATE_29400
- RATE_2M
- RATE_2MBPS
- RATE_2M_IDX
- RATE_2M_IDX_TBL
- RATE_2M_IEEE
- RATE_2M_MASK
- RATE_2M_PLCP
- RATE_2Mb
- RATE_32000
- RATE_32K
- RATE_36M
- RATE_36MBPS
- RATE_36M_IDX
- RATE_36M_IDX_TBL
- RATE_36M_IEEE
- RATE_36M_MASK
- RATE_36M_PLCP
- RATE_36Mb
- RATE_44100
- RATE_48000
- RATE_48M
- RATE_48MBPS
- RATE_48M_IDX
- RATE_48M_IDX_TBL
- RATE_48M_IEEE
- RATE_48M_MASK
- RATE_48M_PLCP
- RATE_48Mb
- RATE_5000CPS
- RATE_54M
- RATE_54MBPS
- RATE_54M_IDX
- RATE_54M_IDX_TBL
- RATE_54M_IEEE
- RATE_54M_MASK
- RATE_54M_PLCP
- RATE_54Mb
- RATE_5M
- RATE_5M_IDX
- RATE_5M_IDX_TBL
- RATE_5M_IEEE
- RATE_5M_MASK
- RATE_5M_PLCP
- RATE_5_5M
- RATE_5_5MBPS
- RATE_5_5Mb
- RATE_60M_IDX
- RATE_60M_IEEE
- RATE_60M_MASK
- RATE_60M_PLCP
- RATE_6M
- RATE_6MBPS
- RATE_6M_IDX
- RATE_6M_IDX_TBL
- RATE_6M_IEEE
- RATE_6M_MASK
- RATE_6M_PLCP
- RATE_6Mb
- RATE_7350
- RATE_8000
- RATE_8820
- RATE_9600
- RATE_9M
- RATE_9MBPS
- RATE_9M_IDX
- RATE_9M_IDX_TBL
- RATE_9M_IEEE
- RATE_9M_MASK
- RATE_9M_PLCP
- RATE_9Mb
- RATE_ADAPTIVE_TH_HIGH
- RATE_ADAPTIVE_TH_LOW_20M
- RATE_ADAPTIVE_TH_LOW_40M
- RATE_ADPT_1SS_MASK
- RATE_ADPT_2SS_MASK
- RATE_ADPT_MCS32_MASK
- RATE_ALL_CCK
- RATE_ALL_OFDM_1SS
- RATE_ALL_OFDM_2SS
- RATE_ALL_OFDM_AG
- RATE_ANT_NUM
- RATE_AUTO
- RATE_BITMAP_ALL
- RATE_COUNT
- RATE_COUNT_3945
- RATE_COUNT_LEGACY
- RATE_CR0063
- RATE_CR0364
- RATE_CR1000
- RATE_CR2500
- RATE_CTRL_CAPA_VHT_EXT_NSS_BW
- RATE_CTRL_ENABLE
- RATE_DEC
- RATE_DECREASE_TH
- RATE_DISCRETE
- RATE_FLUSH
- RATE_FLUSH_MAX
- RATE_FLUSH_MIN
- RATE_GOVERNOR_STATUS
- RATE_HE_DUAL_CARRIER_MODE
- RATE_HE_DUAL_CARRIER_MODE_MSK
- RATE_HIGH_TH
- RATE_HT_MCS_GF_MSK
- RATE_HT_MCS_GF_POS
- RATE_HT_MCS_INDEX_MSK
- RATE_HT_MCS_NSS_MSK
- RATE_HT_MCS_NSS_POS
- RATE_HT_MCS_RATE_CODE_MSK
- RATE_IDX
- RATE_ID_SHT
- RATE_INC
- RATE_INCREASE_TH
- RATE_INDEX_11MBPS
- RATE_INDEX_12MBPS
- RATE_INDEX_18MBPS
- RATE_INDEX_1MBPS
- RATE_INDEX_22MBPS
- RATE_INDEX_24MBPS
- RATE_INDEX_2MBPS
- RATE_INDEX_36MBPS
- RATE_INDEX_48MBPS
- RATE_INDEX_54MBPS
- RATE_INDEX_5_5MBPS
- RATE_INDEX_6MBPS
- RATE_INDEX_9MBPS
- RATE_INDEX_ENUM_MAX_SIZE
- RATE_INDEX_MAX
- RATE_INDEX_MSB
- RATE_INDEX_WITHOUT_SGI_MASK
- RATE_INFO_BW_10
- RATE_INFO_BW_160
- RATE_INFO_BW_20
- RATE_INFO_BW_40
- RATE_INFO_BW_5
- RATE_INFO_BW_80
- RATE_INFO_BW_HE_RU
- RATE_INFO_ENABLE
- RATE_INFO_FLAGS_DMG
- RATE_INFO_FLAGS_EDMG
- RATE_INFO_FLAGS_HE_MCS
- RATE_INFO_FLAGS_MCS
- RATE_INFO_FLAGS_SHORT_GI
- RATE_INFO_FLAGS_VHT_MCS
- RATE_INVALID
- RATE_INVM_IDX
- RATE_INVM_IDX_TBL
- RATE_IN_242X
- RATE_IN_243X
- RATE_IN_24XX
- RATE_IN_3430ES1
- RATE_IN_3430ES2PLUS
- RATE_IN_3430ES2PLUS_36XX
- RATE_IN_34XX
- RATE_IN_36XX
- RATE_IN_3XXX
- RATE_IN_4430
- RATE_IN_4460
- RATE_IN_44XX
- RATE_IN_AM33XX
- RATE_IN_TI814X
- RATE_IN_TI816X
- RATE_LEGACY_RATE_MSK
- RATE_LOW
- RATE_MANUAL
- RATE_MASK
- RATE_MASK_11MBPS
- RATE_MASK_1MBPS
- RATE_MASK_2MBPS
- RATE_MASK_5_5MBPS
- RATE_MAX_WINDOW
- RATE_MCS
- RATE_MCS0
- RATE_MCS1
- RATE_MCS10
- RATE_MCS11
- RATE_MCS12
- RATE_MCS13
- RATE_MCS14
- RATE_MCS15
- RATE_MCS2
- RATE_MCS3
- RATE_MCS4
- RATE_MCS5
- RATE_MCS6
- RATE_MCS7
- RATE_MCS8
- RATE_MCS9
- RATE_MCS_0_20
- RATE_MCS_0_40
- RATE_MCS_1_20
- RATE_MCS_1_40
- RATE_MCS_2_20
- RATE_MCS_2_40
- RATE_MCS_3_20
- RATE_MCS_3_40
- RATE_MCS_4_20
- RATE_MCS_4_40
- RATE_MCS_5_20
- RATE_MCS_5_40
- RATE_MCS_6_20
- RATE_MCS_6_40
- RATE_MCS_7_20
- RATE_MCS_7_40
- RATE_MCS_ANT_ABC_MSK
- RATE_MCS_ANT_AB_MSK
- RATE_MCS_ANT_A_MSK
- RATE_MCS_ANT_B_MSK
- RATE_MCS_ANT_C_MSK
- RATE_MCS_ANT_MSK
- RATE_MCS_ANT_POS
- RATE_MCS_BF_MSK
- RATE_MCS_BF_POS
- RATE_MCS_CCK_MSK
- RATE_MCS_CCK_POS
- RATE_MCS_CHAN_WIDTH_160
- RATE_MCS_CHAN_WIDTH_20
- RATE_MCS_CHAN_WIDTH_40
- RATE_MCS_CHAN_WIDTH_80
- RATE_MCS_CHAN_WIDTH_MSK
- RATE_MCS_CHAN_WIDTH_POS
- RATE_MCS_CODE_MSK
- RATE_MCS_DUP_MSK
- RATE_MCS_DUP_POS
- RATE_MCS_FLAGS_POS
- RATE_MCS_GF_MSK
- RATE_MCS_GF_POS
- RATE_MCS_HE_106T_MSK
- RATE_MCS_HE_106T_POS
- RATE_MCS_HE_GI_LTF_MSK
- RATE_MCS_HE_GI_LTF_POS
- RATE_MCS_HE_MSK
- RATE_MCS_HE_POS
- RATE_MCS_HE_TYPE_EXT_SU
- RATE_MCS_HE_TYPE_MSK
- RATE_MCS_HE_TYPE_MU
- RATE_MCS_HE_TYPE_POS
- RATE_MCS_HE_TYPE_SU
- RATE_MCS_HE_TYPE_TRIG
- RATE_MCS_HT40_MSK
- RATE_MCS_HT40_POS
- RATE_MCS_HT_DUP_MSK
- RATE_MCS_HT_DUP_POS
- RATE_MCS_HT_MSK
- RATE_MCS_HT_POS
- RATE_MCS_LDPC_MSK
- RATE_MCS_LDPC_POS
- RATE_MCS_RATE_MSK
- RATE_MCS_SGI_MSK
- RATE_MCS_SGI_POS
- RATE_MCS_SPATIAL_MSK
- RATE_MCS_SPATIAL_POS
- RATE_MCS_STBC_MSK
- RATE_MCS_STBC_POS
- RATE_MCS_VHT_MSK
- RATE_MCS_VHT_POS
- RATE_METER_RAM
- RATE_MIMO2_12M_PLCP
- RATE_MIMO2_18M_PLCP
- RATE_MIMO2_24M_PLCP
- RATE_MIMO2_36M_PLCP
- RATE_MIMO2_48M_PLCP
- RATE_MIMO2_54M_PLCP
- RATE_MIMO2_60M_PLCP
- RATE_MIMO2_6M_PLCP
- RATE_MIMO2_INVM_PLCP
- RATE_MIN_FAILURE_TH
- RATE_MIN_SUCCESS_TH
- RATE_MODE_CCK
- RATE_MODE_HT_GREENFIELD
- RATE_MODE_HT_MIX
- RATE_MODE_OFDM
- RATE_OPS
- RATE_POS
- RATE_RATIO_M
- RATE_REFTIM_ENABLE
- RATE_REG_BITMAP_ALL
- RATE_RETRY_TH
- RATE_RO_OPS
- RATE_RRSR_CCK_ONLY_1M
- RATE_RRSR_WITHOUT_CCK
- RATE_SCALE_FLUSH_INTVL
- RATE_SCALE_SWITCH
- RATE_SECTION
- RATE_SET_MAX_SIZE
- RATE_SISO_12M_PLCP
- RATE_SISO_18M_PLCP
- RATE_SISO_24M_PLCP
- RATE_SISO_36M_PLCP
- RATE_SISO_48M_PLCP
- RATE_SISO_54M_PLCP
- RATE_SISO_60M_PLCP
- RATE_SISO_6M_PLCP
- RATE_SISO_INVM_PLCP
- RATE_THRESHOLD
- RATE_TLV_MAX_SIZE
- RATE_TO_BASE100KBPS
- RATE_TO_U64
- RATE_TYPE_ACCESS
- RATE_VHT_MCS_NSS_MSK
- RATE_VHT_MCS_NSS_POS
- RATE_VHT_MCS_RATE_CODE_MSK
- RATE_WIN_FLUSH
- RATIO_MAX
- RATIO_REG_SIZE
- RATIO_SCALE
- RATIO_SCALE_LOG
- RATIO_SHIFT
- RATOC_PRODUCT_ID
- RATOC_PRODUCT_ID_SCU18
- RATOC_PRODUCT_ID_USB60F
- RATOC_VENDOR_ID
- RATR0
- RATR_11M
- RATR_12M
- RATR_18M
- RATR_1M
- RATR_24M
- RATR_2M
- RATR_36M
- RATR_48M
- RATR_54M
- RATR_55M
- RATR_6M
- RATR_9M
- RATR_INX_WIRELESS_A
- RATR_INX_WIRELESS_AC_24N
- RATR_INX_WIRELESS_AC_5N
- RATR_INX_WIRELESS_AC_N
- RATR_INX_WIRELESS_B
- RATR_INX_WIRELESS_G
- RATR_INX_WIRELESS_GB
- RATR_INX_WIRELESS_MC
- RATR_INX_WIRELESS_N
- RATR_INX_WIRELESS_NB
- RATR_INX_WIRELESS_NG
- RATR_INX_WIRELESS_NGB
- RATR_MCS0
- RATR_MCS1
- RATR_MCS10
- RATR_MCS11
- RATR_MCS12
- RATR_MCS13
- RATR_MCS14
- RATR_MCS15
- RATR_MCS2
- RATR_MCS3
- RATR_MCS4
- RATR_MCS5
- RATR_MCS6
- RATR_MCS7
- RATR_MCS8
- RATR_MCS9
- RATR_TABLE_MODE
- RATS_TA1_PRESENT_MASK
- RATS_TB1_PRESENT_MASK
- RAT_OP
- RAVB_ALIGN
- RAVB_BE
- RAVB_DEF_MSG_ENABLE
- RAVB_NC
- RAVB_QUEUE
- RAVB_RXTSTAMP_ENABLED
- RAVB_RXTSTAMP_TYPE
- RAVB_RXTSTAMP_TYPE_ALL
- RAVB_RXTSTAMP_TYPE_V2_L2_EVENT
- RAVB_RXTSTAMP_VALID
- RAVB_STATS_LEN
- RAVB_TXTSTAMP_ENABLED
- RAVB_TXTSTAMP_VALID
- RAVEN1_F0
- RAVEN2_A0
- RAVEN2_GB_ADDR_CONFIG_GOLDEN
- RAVEN_A0
- RAVEN_B0
- RAVEN_GB_ADDR_CONFIG_GOLDEN
- RAVEN_PP_SMC_H
- RAVEN_UNKNOWN
- RAVE_SP_BACKLIGHT_LCD_EN
- RAVE_SP_CHECKSUM_8B2C
- RAVE_SP_CHECKSUM_CCITT
- RAVE_SP_CHECKSUM_SIZE
- RAVE_SP_CMD_BOOT_SOURCE
- RAVE_SP_CMD_CONTROL_EVENTS
- RAVE_SP_CMD_GET_BOARD_COPPER_REV
- RAVE_SP_CMD_GET_BOOTLOADER_VERSION
- RAVE_SP_CMD_GET_FIRMWARE_VERSION
- RAVE_SP_CMD_GET_GPIO_STATE
- RAVE_SP_CMD_GET_I2C_DEVICE_STATUS
- RAVE_SP_CMD_GET_SP_SILICON_REV
- RAVE_SP_CMD_PET_WDT
- RAVE_SP_CMD_REQ_COPPER_REV
- RAVE_SP_CMD_RESET
- RAVE_SP_CMD_RESET_REASON
- RAVE_SP_CMD_RMB_EEPROM
- RAVE_SP_CMD_SET_BACKLIGHT
- RAVE_SP_CMD_STATUS
- RAVE_SP_CMD_SW_WDT
- RAVE_SP_DLE
- RAVE_SP_EEPROM_HEADER_BIG
- RAVE_SP_EEPROM_HEADER_MAX
- RAVE_SP_EEPROM_HEADER_SMALL
- RAVE_SP_EEPROM_PAGE_SIZE
- RAVE_SP_EEPROM_READ
- RAVE_SP_EEPROM_WRITE
- RAVE_SP_ETX
- RAVE_SP_EVNT_BASE
- RAVE_SP_EVNT_BUTTON_PRESS
- RAVE_SP_EXPECT_DATA
- RAVE_SP_EXPECT_ESCAPED_DATA
- RAVE_SP_EXPECT_SOF
- RAVE_SP_MAX_DATA_SIZE
- RAVE_SP_RESET_BYTE
- RAVE_SP_RESET_DELAY_MS
- RAVE_SP_RESET_REASON_NORMAL
- RAVE_SP_RX_BUFFER_SIZE
- RAVE_SP_STX
- RAVE_SP_STX_ETX_SIZE
- RAVE_SP_TX_BUFFER_SIZE
- RAVG
- RAW
- RAW3215_BUFFER_SIZE
- RAW3215_FIXED
- RAW3215_FLUSHING
- RAW3215_FREE
- RAW3215_INBUF_SIZE
- RAW3215_MAX_BYTES
- RAW3215_MAX_NEWLINE
- RAW3215_MIN_SPACE
- RAW3215_MIN_WRITE
- RAW3215_NR_CCWS
- RAW3215_READ
- RAW3215_STOPPED
- RAW3215_THROTTLED
- RAW3215_TIMEOUT
- RAW3215_TIMER_RUNS
- RAW3215_WORKING
- RAW3215_WRITE
- RAW3270_FIRSTMINOR
- RAW3270_FLAGS_14BITADDR
- RAW3270_FLAGS_BUSY
- RAW3270_FLAGS_CONSOLE
- RAW3270_FLAGS_FROZEN
- RAW3270_MAXDEVS
- RAW3270_STATE_INIT
- RAW3270_STATE_READMOD
- RAW3270_STATE_READY
- RAW3270_STATE_RESET
- RAW3270_STATE_W4ATTN
- RAW3270_VIEW_LOCK_BH
- RAW3270_VIEW_LOCK_IRQ
- RAWCLK_FREQ_MASK
- RAWCLK_FREQ_VLV
- RAWCT
- RAWNODE_CLASS_INODE_CACHE
- RAWNODE_CLASS_XATTR_DATUM
- RAWNODE_CLASS_XATTR_REF
- RAW_BASE_ADR
- RAW_BPL
- RAW_BUF_SIZE
- RAW_DATA_MAX_SIZE
- RAW_ENABLE
- RAW_FORMAT
- RAW_FROM_REG
- RAW_GETBIND
- RAW_HEADER_BYTES
- RAW_HTABLE_SIZE
- RAW_INIT_NOTIFIER_HEAD
- RAW_INT
- RAW_INT_CRT_VSYNC
- RAW_INT_PANEL_VSYNC
- RAW_INT_VGA_VSYNC
- RAW_INT_ZVPORT0_VSYNC
- RAW_INT_ZVPORT1_VSYNC
- RAW_IOCTL
- RAW_IS_INODE
- RAW_LINES
- RAW_MAJOR
- RAW_NODE_SWIN_BASE
- RAW_NOTIFIER_HEAD
- RAW_NOTIFIER_INIT
- RAW_PAYLOAD_DIGITAL
- RAW_PAYLOAD_HCI
- RAW_PAYLOAD_LLCP
- RAW_PAYLOAD_NCI
- RAW_PAYLOAD_PROPRIETARY
- RAW_PKT
- RAW_PMU_INT
- RAW_REQUEST
- RAW_SETBIND
- RAW_TO_ACPI
- RAW_VALID_HOOKS
- RAX
- RAXI_AOUTSTDCAPB_MASK
- RAXI_BEN_MASK
- RAXI_BOUTSTDCAPB_MASK
- RAYDAT_DS_CHANNELS
- RAYDAT_QS_CHANNELS
- RAYDAT_SS_CHANNELS
- RAYDIUM_ACK_NULL
- RAYDIUM_PATH_READY
- RAYDIUM_TS_BLDR
- RAYDIUM_TS_MAIN
- RAYDIUM_WAIT_READY
- RAY_DO_CMD
- RAY_IOCG_PARMS
- RAY_IOCS_PARMS
- RAY_IPX_TYPE
- RA_CFOLONGDUMP
- RA_CFOSHORTDUMP
- RA_CFO_LONG_DUMP
- RA_CFO_SHORT_DUMP
- RA_DOWN_ARROW
- RA_FIND_NEXT_SENT
- RA_FIND_PREV_SENT
- RA_FLOOR_TABLE_SIZE
- RA_FLOOR_UP_GAP
- RA_LSSIWRITE_8821A
- RA_MASK
- RA_MASK_CCK_IN_HT
- RA_MASK_CCK_IN_VHT
- RA_MASK_CCK_RATES
- RA_MASK_HT_RATES
- RA_MASK_HT_RATES_1SS
- RA_MASK_HT_RATES_2SS
- RA_MASK_HT_RATES_3SS
- RA_MASK_OFDM_IN_HT_2G
- RA_MASK_OFDM_IN_HT_5G
- RA_MASK_OFDM_IN_VHT
- RA_MASK_OFDM_RATES
- RA_MASK_VHT_RATES
- RA_MASK_VHT_RATES_1SS
- RA_MASK_VHT_RATES_2SS
- RA_MASK_VHT_RATES_3SS
- RA_NEXT_LINE
- RA_NEXT_SENT
- RA_NOTHING
- RA_OFFSET_HT_CCK
- RA_OFFSET_HT_OFDM1
- RA_OFFSET_HT_OFDM2
- RA_OFFSET_HT_OFDM3
- RA_OFFSET_HT_OFDM4
- RA_OFFSET_LEGACY_OFDM1
- RA_OFFSET_LEGACY_OFDM2
- RA_PIREAD_8821A
- RA_PREV_LINE
- RA_PREV_SENT
- RA_RFE_CTRL_8812
- RA_RFE_INV
- RA_RFE_PINMUX
- RA_RSSIDUMP
- RA_RSSI_DUMP
- RA_RXIQC_AB
- RA_RXIQC_CD
- RA_RXSNRDUMP
- RA_RX_SNR_DUMP
- RA_SIREAD_8821A
- RA_T
- RA_TIMER
- RA_TXPWRTRAING
- RA_TXSCALE
- RB
- RB1
- RB2
- RB2D_DC_AUTOFLUSH_ENABLE
- RB2D_DC_BUSY
- RB2D_DC_DC_DISABLE_IGNORE_PE
- RB2D_DC_FLUSH_2D
- RB2D_DC_FLUSH_ALL
- RB2D_DC_FREE_2D
- RB2D_DSTCACHE_CTLSTAT_broken
- RB2D_DSTCACHE_MODE
- RB3D_CNTL
- RB3D_DC_FINISH
- RB3D_DC_FLUSH
- RB3D_DC_FREE
- RB3D_DSTCACHE_CTLSTAT
- RB4_A8_UNORM
- RB4_R10G10B10A2_UINT
- RB4_R10G10B10A2_UNORM
- RB4_R11G11B10_FLOAT
- RB4_R16G16B16A16_FLOAT
- RB4_R16G16B16A16_SINT
- RB4_R16G16B16A16_SNORM
- RB4_R16G16B16A16_UINT
- RB4_R16G16B16A16_UNORM
- RB4_R16G16_FLOAT
- RB4_R16G16_SINT
- RB4_R16G16_SNORM
- RB4_R16G16_UINT
- RB4_R16G16_UNORM
- RB4_R16_FLOAT
- RB4_R16_SINT
- RB4_R16_SNORM
- RB4_R16_UINT
- RB4_R16_UNORM
- RB4_R32G32B32A32_FLOAT
- RB4_R32G32B32A32_SINT
- RB4_R32G32B32A32_UINT
- RB4_R32G32_FLOAT
- RB4_R32G32_SINT
- RB4_R32G32_UINT
- RB4_R32_FLOAT
- RB4_R32_SINT
- RB4_R32_UINT
- RB4_R4G4B4A4_UNORM
- RB4_R5G5B5A1_UNORM
- RB4_R5G6B5_UNORM
- RB4_R8G8B8A8_SINT
- RB4_R8G8B8A8_SNORM
- RB4_R8G8B8A8_UINT
- RB4_R8G8B8A8_UNORM
- RB4_R8G8B8_UNORM
- RB4_R8G8_SINT
- RB4_R8G8_SNORM
- RB4_R8G8_UINT
- RB4_R8G8_UNORM
- RB4_R8_SINT
- RB4_R8_SNORM
- RB4_R8_UINT
- RB4_R8_UNORM
- RB500_CF_IO_DELAY
- RB500_CF_MAXPORTS
- RB500_CF_REG_BASE
- RB500_CF_REG_CTRL
- RB500_CF_REG_DBUF32
- RB500_CF_REG_ERR
- RB532_BTN_KSYM
- RB532_BTN_RATE
- RB5_A8_UNORM
- RB5_R10G10B10A2_UINT
- RB5_R10G10B10A2_UNORM
- RB5_R11G11B10_FLOAT
- RB5_R16G16B16A16_FLOAT
- RB5_R16G16B16A16_SINT
- RB5_R16G16B16A16_SNORM
- RB5_R16G16B16A16_UINT
- RB5_R16G16B16A16_UNORM
- RB5_R16G16_FLOAT
- RB5_R16G16_SINT
- RB5_R16G16_SNORM
- RB5_R16G16_UINT
- RB5_R16G16_UNORM
- RB5_R16_FLOAT
- RB5_R16_SINT
- RB5_R16_SNORM
- RB5_R16_UINT
- RB5_R16_UNORM
- RB5_R32G32B32A32_FLOAT
- RB5_R32G32B32A32_SINT
- RB5_R32G32B32A32_UINT
- RB5_R32G32_FLOAT
- RB5_R32G32_SINT
- RB5_R32G32_UINT
- RB5_R32_FLOAT
- RB5_R32_SINT
- RB5_R32_UINT
- RB5_R4G4B4A4_UNORM
- RB5_R5G5B5A1_UNORM
- RB5_R5G6B5_UNORM
- RB5_R8G8B8A8_SINT
- RB5_R8G8B8A8_SNORM
- RB5_R8G8B8A8_UINT
- RB5_R8G8B8A8_UNORM
- RB5_R8G8B8_UNORM
- RB5_R8G8_SINT
- RB5_R8G8_SNORM
- RB5_R8G8_UINT
- RB5_R8G8_UNORM
- RB5_R8_SINT
- RB5_R8_SNORM
- RB5_R8_UINT
- RB5_R8_UNORM
- RB6_A8_UNORM
- RB6_ACCESS_REG
- RB6_MAGIC_NUMBER_RST
- RB6_R10G10B10A2_UINT
- RB6_R10G10B10A2_UNORM
- RB6_R11G11B10_FLOAT
- RB6_R16G16B16A16_FLOAT
- RB6_R16G16B16A16_SINT
- RB6_R16G16B16A16_SNORM
- RB6_R16G16B16A16_UINT
- RB6_R16G16B16A16_UNORM
- RB6_R16G16_FLOAT
- RB6_R16G16_SINT
- RB6_R16G16_SNORM
- RB6_R16G16_UINT
- RB6_R16G16_UNORM
- RB6_R16_FLOAT
- RB6_R16_SINT
- RB6_R16_SNORM
- RB6_R16_UINT
- RB6_R16_UNORM
- RB6_R32G32B32A32_FLOAT
- RB6_R32G32B32A32_SINT
- RB6_R32G32B32A32_UINT
- RB6_R32G32_FLOAT
- RB6_R32G32_SINT
- RB6_R32G32_UINT
- RB6_R32_FLOAT
- RB6_R32_SINT
- RB6_R32_UINT
- RB6_R4G4B4A4_UNORM
- RB6_R5G5B5A1_UNORM
- RB6_R5G6B5_UNORM
- RB6_R8G8B8A8_SINT
- RB6_R8G8B8A8_SNORM
- RB6_R8G8B8A8_UINT
- RB6_R8G8B8A8_UNORM
- RB6_R8G8B8_UNORM
- RB6_R8G8_SINT
- RB6_R8G8_SNORM
- RB6_R8G8_UINT
- RB6_R8G8_UNORM
- RB6_R8_SINT
- RB6_R8_SNORM
- RB6_R8_UINT
- RB6_R8_UNORM
- RB6_X8Z24_UNORM
- RBASE
- RBBC0
- RBBC1
- RBBISTDN
- RBBISTEN
- RBBISTFAIL
- RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK_MASK
- RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT
- RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR_MASK
- RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_ADDR__SHIFT
- RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK_MASK
- RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT
- RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP_MASK
- RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_OP__SHIFT
- RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK
- RBBMIF_INT_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT
- RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2_MASK
- RBBMIF_STATUS_2__RBBMIF_TIMEOUT_CLIENTS_DEC_2__SHIFT
- RBBMIF_STATUS_FLAG__RBBMIF_ACK_TIMEOUT_MASK
- RBBMIF_STATUS_FLAG__RBBMIF_ACK_TIMEOUT__SHIFT
- RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY_MASK
- RBBMIF_STATUS_FLAG__RBBMIF_FIFO_EMPTY__SHIFT
- RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL_MASK
- RBBMIF_STATUS_FLAG__RBBMIF_FIFO_FULL__SHIFT
- RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR_MASK
- RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_ADDR__SHIFT
- RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG_MASK
- RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_FLAG__SHIFT
- RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE_MASK
- RBBMIF_STATUS_FLAG__RBBMIF_INVALID_ACCESS_TYPE__SHIFT
- RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT_MASK
- RBBMIF_STATUS_FLAG__RBBMIF_READ_TIMEOUT__SHIFT
- RBBMIF_STATUS_FLAG__RBBMIF_STATE_MASK
- RBBMIF_STATUS_FLAG__RBBMIF_STATE__SHIFT
- RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK_MASK
- RBBMIF_STATUS__RBBMIF_TIMEOUT_ACK__SHIFT
- RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC_MASK
- RBBMIF_STATUS__RBBMIF_TIMEOUT_CLIENTS_DEC__SHIFT
- RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK_MASK
- RBBMIF_STATUS__RBBMIF_TIMEOUT_MASK__SHIFT
- RBBMIF_STATUS__RBBMIF_TIMEOUT_OP_MASK
- RBBMIF_STATUS__RBBMIF_TIMEOUT_OP__SHIFT
- RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS_MASK
- RBBMIF_STATUS__RBBMIF_TIMEOUT_RDWR_STATUS__SHIFT
- RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS_2__CLIENT32_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS_2__CLIENT33_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS_2__CLIENT34_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS_2__CLIENT35_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS_2__CLIENT36_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS_2__CLIENT37_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT0_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT10_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT11_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT12_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT13_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT14_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT15_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT16_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT17_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT18_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT19_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT1_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT20_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT21_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT22_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT23_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT24_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT25_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT26_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT27_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT28_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT29_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT2_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT30_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT31_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT3_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT4_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT5_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT6_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT7_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT8_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS_MASK
- RBBMIF_TIMEOUT_DIS__CLIENT9_TIMEOUT_DIS__SHIFT
- RBBMIF_TIMEOUT__RBBMIF_ACK_HOLD_MASK
- RBBMIF_TIMEOUT__RBBMIF_ACK_HOLD__SHIFT
- RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY_MASK
- RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_DELAY__SHIFT
- RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD_MASK
- RBBMIF_TIMEOUT__RBBMIF_TIMEOUT_TO_REQ_HOLD__SHIFT
- RBBMTIMER_CLK
- RBBMTIMER_CLK_SRC
- RBBM_AHB_STATUS_BUSY
- RBBM_AHB_STATUS_LONG_STALL
- RBBM_AHB_STATUS_STALLED
- RBBM_AHB_STATUS_TXFR
- RBBM_AHB_STATUS_TXFR_ERROR
- RBBM_AHB_STATUS_TXFR_SPLIT
- RBBM_ALAWYS_ON
- RBBM_ALWAYS_ON
- RBBM_ANY_ARB_BUSY
- RBBM_ANY_CCU_BUSY
- RBBM_ANY_MARB_BUSY
- RBBM_ANY_RB_BUSY
- RBBM_ANY_SP_BUSY
- RBBM_ANY_TEX_BUSY
- RBBM_ANY_TPL1_BUSY
- RBBM_ANY_USP_BUSY
- RBBM_CMDFIFO_ADDR
- RBBM_CMDFIFO_DATAH
- RBBM_CMDFIFO_DATAL
- RBBM_CMDFIFO_STAT
- RBBM_CNTL
- RBBM_CNTL_alt_1
- RBBM_COM_BUSY
- RBBM_CP_BUSY_GFX_CORE_IDLE
- RBBM_DCOM_BUSY
- RBBM_DEBUG
- RBBM_DPM_BUSY
- RBBM_ERROR_MASK
- RBBM_GUICNTL
- RBBM_HLSQ_BUSY
- RBBM_PC_DCALL_BUSY
- RBBM_PC_VSD_BUSY
- RBBM_RAS_BUSY
- RBBM_RBBM_STATUS_MASKED
- RBBM_SOFT_RESET
- RBBM_SOFT_RESET_alt_1
- RBBM_STATUS
- RBBM_STATUS_MASKED
- RBBM_STATUS_alt_1
- RBBM_TESS_BUSY
- RBBM_TSE_BUSY
- RBBM_UCHE_BUSY
- RBBM_VBIF_BUSY
- RBBM_VFD_BUSY
- RBBM_VPC_BUSY
- RBBM_VSC_BUSY
- RBC
- RBCA
- RBCA_ADDR
- RBCH
- RBCL
- RBCPR_BCR
- RBCPR_CLK
- RBCPR_CLK_SRC
- RBCR
- RBCSR
- RBCTL
- RBC_BA
- RBC_CA
- RBC_MEM_SIZE
- RBC_RA
- RBC_SOFT_RESET
- RBC_ZERO
- RBDAT
- RBDR_SIZE
- RBDR_SIZE0
- RBDR_SIZE1
- RBDR_SIZE2
- RBDR_SIZE3
- RBDR_SIZE4
- RBDR_SIZE5
- RBDR_SIZE6
- RBDR_THRESH
- RBD_ALLOC_SIZE_DEFAULT
- RBD_BLK_SIZE
- RBD_DEBUG
- RBD_DEFAULT_OBJ_ORDER
- RBD_DEV_FLAG_EXISTS
- RBD_DEV_FLAG_REMOVING
- RBD_DIRECTORY
- RBD_DRV_NAME
- RBD_EXCLUSIVE_DEFAULT
- RBD_FEATURES_ALL
- RBD_FEATURES_SUPPORTED
- RBD_FEATURE_DATA_POOL
- RBD_FEATURE_DEEP_FLATTEN
- RBD_FEATURE_EXCLUSIVE_LOCK
- RBD_FEATURE_FAST_DIFF
- RBD_FEATURE_LAYERING
- RBD_FEATURE_OBJECT_MAP
- RBD_FEATURE_OPERATIONS
- RBD_FEATURE_STRIPINGV2
- RBD_FETCH_IDLE
- RBD_FLAG_FAST_DIFF_INVALID
- RBD_FLAG_OBJECT_MAP_INVALID
- RBD_HEADER_PREFIX
- RBD_HEADER_SIGNATURE
- RBD_HEADER_TEXT
- RBD_HEADER_VERSION
- RBD_ID_PREFIX
- RBD_IMAGE_ID_LEN_MAX
- RBD_IMAGE_NAME_LEN_MAX
- RBD_IMG_EXCLUSIVE_LOCK
- RBD_IMG_OBJECT_REQUESTS
- RBD_IMG_START
- RBD_INFO
- RBD_LAST
- RBD_LOCK_COOKIE_PREFIX
- RBD_LOCK_NAME
- RBD_LOCK_ON_READ_DEFAULT
- RBD_LOCK_STATE_LOCKED
- RBD_LOCK_STATE_RELEASING
- RBD_LOCK_STATE_UNLOCKED
- RBD_LOCK_TAG
- RBD_LOCK_TIMEOUT_DEFAULT
- RBD_MASK
- RBD_MAX_OBJ_ORDER
- RBD_MAX_PARENT_CHAIN_LEN
- RBD_MAX_SNAP_COUNT
- RBD_MAX_SNAP_NAME_LEN
- RBD_MINORS_PER_MAJOR
- RBD_MIN_OBJ_ORDER
- RBD_NOTIFY_OP_ACQUIRED_LOCK
- RBD_NOTIFY_OP_HEADER_UPDATE
- RBD_NOTIFY_OP_RELEASED_LOCK
- RBD_NOTIFY_OP_REQUEST_LOCK
- RBD_NOTIFY_TIMEOUT
- RBD_OBJECT_MAP_PREFIX
- RBD_OBJ_COPYUP_OBJECT_MAPS
- RBD_OBJ_COPYUP_READ_PARENT
- RBD_OBJ_COPYUP_START
- RBD_OBJ_COPYUP_WRITE_OBJECT
- RBD_OBJ_FLAG_COPYUP_ENABLED
- RBD_OBJ_FLAG_COPYUP_ZEROS
- RBD_OBJ_FLAG_DELETION
- RBD_OBJ_FLAG_MAY_EXIST
- RBD_OBJ_FLAG_NOOP_FOR_NONEXISTENT
- RBD_OBJ_PREFIX_LEN_MAX
- RBD_OBJ_READ_OBJECT
- RBD_OBJ_READ_PARENT
- RBD_OBJ_READ_START
- RBD_OBJ_WRITE_COPYUP
- RBD_OBJ_WRITE_OBJECT
- RBD_OBJ_WRITE_POST_OBJECT_MAP
- RBD_OBJ_WRITE_PRE_OBJECT_MAP
- RBD_OBJ_WRITE_START
- RBD_QUEUE_DEPTH_DEFAULT
- RBD_READ_ONLY_DEFAULT
- RBD_RETRY_DELAY
- RBD_SINGLE_MAJOR_PART_SHIFT
- RBD_SIZE
- RBD_SNAP_DEV_NAME_PREFIX
- RBD_SNAP_HEAD_NAME
- RBD_SUFFIX
- RBD_TRIM_DEFAULT
- RBD_USED
- RBD_V1_DATA_FORMAT
- RBD_V2_DATA_FORMAT
- RBD_WATCH_STATE_ERROR
- RBD_WATCH_STATE_REGISTERED
- RBD_WATCH_STATE_UNREGISTERED
- RBEIR
- RBERRADDR_RD
- RBFP_BFPWT
- RBFP_CME
- RBFP_DLP
- RBFP_RBS
- RBFP_RBSVAL
- RBF_DECOMPRESS_OFFSET
- RBF_ENCRYPTION_MODE_OFFSET
- RBG_SOFT_RESET
- RBG_SOFT_RESET_OFFSET
- RBIOS16
- RBIOS32
- RBIOS8
- RBIO_CACHE_BIT
- RBIO_CACHE_READY_BIT
- RBIO_CACHE_SIZE
- RBIO_RMW_LOCKED_BIT
- RBIT
- RBLUE_TOOTH
- RBM_POISONED_REQ_MASK
- RBN
- RBNDA
- RBNDB
- RBOOT_SIZE
- RBOPT
- RBP
- RBPL_MASK
- RBPL_TABLE_SIZE
- RBP_IDX_OFFSET
- RBP_INT_ENB
- RBP_MASK
- RBP_QSIZE
- RBP_TAIL
- RBP_THRESH
- RBR
- RBRQ_AAL5_PROT
- RBRQ_ADDR
- RBRQ_ALIGNMENT
- RBRQ_BUFLEN
- RBRQ_CID
- RBRQ_CON_CLOSED
- RBRQ_COUNT
- RBRQ_CRC_ERR
- RBRQ_END_PDU
- RBRQ_HBUF_ERR
- RBRQ_LEN_ERR
- RBRQ_MASK
- RBRQ_SIZE
- RBRQ_THRESH
- RBRQ_TIME
- RBR_BLKSIZE_16K
- RBR_BLKSIZE_32K
- RBR_BLKSIZE_4K
- RBR_BLKSIZE_8K
- RBR_BUFSZ0_1K
- RBR_BUFSZ0_256
- RBR_BUFSZ0_2K
- RBR_BUFSZ0_512
- RBR_BUFSZ1_1K
- RBR_BUFSZ1_2K
- RBR_BUFSZ1_4K
- RBR_BUFSZ1_8K
- RBR_BUFSZ2_16K
- RBR_BUFSZ2_2K
- RBR_BUFSZ2_4K
- RBR_BUFSZ2_8K
- RBR_CFIG_A
- RBR_CFIG_A_LEN
- RBR_CFIG_A_LEN_SHIFT
- RBR_CFIG_A_STADDR
- RBR_CFIG_A_STADDR_BASE
- RBR_CFIG_B
- RBR_CFIG_B_BLKSIZE
- RBR_CFIG_B_BLKSIZE_SHIFT
- RBR_CFIG_B_BUFSZ0
- RBR_CFIG_B_BUFSZ0_SHIFT
- RBR_CFIG_B_BUFSZ1
- RBR_CFIG_B_BUFSZ1_SHIFT
- RBR_CFIG_B_BUFSZ2
- RBR_CFIG_B_BUFSZ2_SHIFT
- RBR_CFIG_B_VLD0
- RBR_CFIG_B_VLD1
- RBR_CFIG_B_VLD2
- RBR_DESCR_ADDR_SHIFT
- RBR_HDH
- RBR_HDH_HEAD_H
- RBR_HDL
- RBR_HDL_HEAD_L
- RBR_KICK
- RBR_KICK_BKADD
- RBR_REFILL_MIN
- RBR_STAT
- RBR_STAT_QLEN
- RBS
- RBSEL
- RBSShift
- RBS_BASE_OFF
- RBTN_SLIDER
- RBTN_TOGGLE
- RBTN_UNKNOWN
- RBTX4927_BRAMRTC_BASE
- RBTX4927_ETHER_ADDR
- RBTX4927_ETHER_BASE
- RBTX4927_IMASK_ADDR
- RBTX4927_IMSTAT_ADDR
- RBTX4927_INTB_PCIA
- RBTX4927_INTB_PCIB
- RBTX4927_INTB_PCIC
- RBTX4927_INTB_PCID
- RBTX4927_INTF_PCIA
- RBTX4927_INTF_PCIB
- RBTX4927_INTF_PCIC
- RBTX4927_INTF_PCID
- RBTX4927_IRQ_IOC
- RBTX4927_IRQ_IOCINT
- RBTX4927_IRQ_IOC_PCIA
- RBTX4927_IRQ_IOC_PCIB
- RBTX4927_IRQ_IOC_PCIC
- RBTX4927_IRQ_IOC_PCID
- RBTX4927_ISA_IO_OFFSET
- RBTX4927_LED_ADDR
- RBTX4927_NR_IRQ_IOC
- RBTX4927_PCIIO
- RBTX4927_PCIIO_SIZE
- RBTX4927_PCIMEM
- RBTX4927_PCIMEM_SIZE
- RBTX4927_PCIRESET_ADDR
- RBTX4927_RTL_8019_BASE
- RBTX4927_RTL_8019_IRQ
- RBTX4927_SOFTINT_ADDR
- RBTX4927_SOFTRESETLOCK_ADDR
- RBTX4927_SOFTRESET_ADDR
- RBTX4938_BDIPSW_ADDR
- RBTX4938_CONFIG1_ADDR
- RBTX4938_CONFIG2_ADDR
- RBTX4938_CONFIG3_ADDR
- RBTX4938_DIPSW_ADDR
- RBTX4938_ETHER_ADDR
- RBTX4938_ETHER_BASE
- RBTX4938_FPGA_REG_ADDR
- RBTX4938_FPGA_REV_ADDR
- RBTX4938_IMASK2_ADDR
- RBTX4938_IMASK_ADDR
- RBTX4938_IMSTAT2_ADDR
- RBTX4938_IMSTAT_ADDR
- RBTX4938_INTB_ATA
- RBTX4938_INTB_I2S
- RBTX4938_INTB_ISA0
- RBTX4938_INTB_ISA11
- RBTX4938_INTB_ISA12
- RBTX4938_INTB_ISA15
- RBTX4938_INTB_MODEM
- RBTX4938_INTB_PCIA
- RBTX4938_INTB_PCIB
- RBTX4938_INTB_PCIC
- RBTX4938_INTB_PCID
- RBTX4938_INTB_RTC
- RBTX4938_INTB_SW
- RBTX4938_INTB_SWINT
- RBTX4938_INTF_ATA
- RBTX4938_INTF_I2S
- RBTX4938_INTF_ISA0
- RBTX4938_INTF_ISA11
- RBTX4938_INTF_ISA12
- RBTX4938_INTF_ISA15
- RBTX4938_INTF_MODEM
- RBTX4938_INTF_PCIA
- RBTX4938_INTF_PCIB
- RBTX4938_INTF_PCIC
- RBTX4938_INTF_PCID
- RBTX4938_INTF_RTC
- RBTX4938_INTF_SW
- RBTX4938_INTF_SWINT
- RBTX4938_INTPOL_ADDR
- RBTX4938_IRC_INT
- RBTX4938_IRQ_END
- RBTX4938_IRQ_ETHER
- RBTX4938_IRQ_IOC
- RBTX4938_IRQ_IOCINT
- RBTX4938_IRQ_IOC_ATA
- RBTX4938_IRQ_IOC_MODEM
- RBTX4938_IRQ_IOC_PCIA
- RBTX4938_IRQ_IOC_PCIB
- RBTX4938_IRQ_IOC_PCIC
- RBTX4938_IRQ_IOC_PCID
- RBTX4938_IRQ_IOC_RTC
- RBTX4938_IRQ_IOC_SWINT
- RBTX4938_IRQ_IRC
- RBTX4938_IRQ_IRC_ACLC
- RBTX4938_IRQ_IRC_ACLCPME
- RBTX4938_IRQ_IRC_DMA
- RBTX4938_IRQ_IRC_ECCERR
- RBTX4938_IRQ_IRC_INT
- RBTX4938_IRQ_IRC_NDFMC
- RBTX4938_IRQ_IRC_PCIC
- RBTX4938_IRQ_IRC_PCIC1
- RBTX4938_IRQ_IRC_PCIERR
- RBTX4938_IRQ_IRC_PCIPME
- RBTX4938_IRQ_IRC_PDMAC
- RBTX4938_IRQ_IRC_PIO
- RBTX4938_IRQ_IRC_SIO
- RBTX4938_IRQ_IRC_SPI
- RBTX4938_IRQ_IRC_TMR
- RBTX4938_IRQ_IRC_WTOERR
- RBTX4938_ISTAT2_ADDR
- RBTX4938_ISTAT_ADDR
- RBTX4938_LED_ADDR
- RBTX4938_NR_IRQ_IOC
- RBTX4938_PCIRESET_ADDR
- RBTX4938_PIOSEL_ADDR
- RBTX4938_RTL_8019_BASE
- RBTX4938_RTL_8019_IRQ
- RBTX4938_SFPWR_ADDR
- RBTX4938_SFVOL_ADDR
- RBTX4938_SOFTINT_ADDR
- RBTX4938_SOFTRESETLOCK_ADDR
- RBTX4938_SOFTRESET_ADDR
- RBTX4938_SOFT_INT0
- RBTX4938_SOFT_INT1
- RBTX4938_SPICS_ADDR
- RBTX4938_TIMER_INT
- RBTX4939_7SEG_ADDR
- RBTX4939_AUDI_ADDR
- RBTX4939_BDIPSW_ADDR
- RBTX4939_BOARD_REV_ADDR
- RBTX4939_CONFIG1_ADDR
- RBTX4939_CONFIG2_ADDR
- RBTX4939_CONFIG3_ADDR
- RBTX4939_CONFIG4_ADDR
- RBTX4939_ETHER_ADDR
- RBTX4939_ETHER_BASE
- RBTX4939_IEN_ADDR
- RBTX4939_IFAC1_ADDR
- RBTX4939_IFAC2_ADDR
- RBTX4939_IOC_REG_ADDR
- RBTX4939_IOC_REV_ADDR
- RBTX4939_IPOL_ADDR
- RBTX4939_IRQ_END
- RBTX4939_IRQ_ETHER
- RBTX4939_IRQ_IOC
- RBTX4939_IRQ_IOCINT
- RBTX4939_ISAGPIO_ADDR
- RBTX4939_ISASTAT_ADDR
- RBTX4939_MAX_7SEGLEDS
- RBTX4939_NR_IRQ_IOC
- RBTX4939_PCISTAT_ADDR
- RBTX4939_PE1_ADDR
- RBTX4939_PE1_ATA
- RBTX4939_PE1_RMII
- RBTX4939_PE2_ADDR
- RBTX4939_PE2_CIR
- RBTX4939_PE2_GPIO
- RBTX4939_PE2_SIO0
- RBTX4939_PE2_SIO2
- RBTX4939_PE2_SIO3
- RBTX4939_PE2_SPI
- RBTX4939_PE3_ADDR
- RBTX4939_PE3_VP
- RBTX4939_PE3_VP_P
- RBTX4939_PE3_VP_S
- RBTX4939_RESETEN_ADDR
- RBTX4939_RESETSTAT_ADDR
- RBTX4939_ROME_ADDR
- RBTX4939_SOFTINT_ADDR
- RBTX4939_SOFTRESET_ADDR
- RBTX4939_SPICS_ADDR
- RBTX4939_UDIPSW_ADDR
- RBTX4939_USTAT_ADDR
- RBTX4939_VPRESET_ADDR
- RBTX4939_VPSIN_ADDR
- RBTX4939_VPSOUT_ADDR
- RBTX4939_VP_ADDR
- RBU
- RBUFFER_HEAD_MASK
- RBUFFER_SIZE_MASK
- RBUFFER_START_MASK
- RBUFFER_TAIL_MASK
- RBUFSIZE
- RBUF_4B_ALGN
- RBUF_64B_EN
- RBUF_ACPI
- RBUF_ACPI_EN
- RBUF_ACPI_EN_LITE
- RBUF_ADDR_HI
- RBUF_ADDR_LO
- RBUF_ALIGN_2B
- RBUF_BAD_DIS
- RBUF_BAD_PKT_DISC
- RBUF_BASE
- RBUF_BRCM_TAG_STRIP
- RBUF_BYTE_SZ
- RBUF_CHK_CTRL
- RBUF_CONTROL
- RBUF_CRC_REPLACE
- RBUF_CTRL
- RBUF_EEE_EN
- RBUF_ENERGY_CTRL
- RBUF_ERR_CNT_V2
- RBUF_ERR_CNT_V3PLUS
- RBUF_ERR_PKT_CNTR
- RBUF_EVENT_HIGH
- RBUF_EVENT_LOW
- RBUF_FLTR_LEN_MASK
- RBUF_FLTR_LEN_SHIFT
- RBUF_FLUSH_CTRL_V1
- RBUF_HEAD_LEN
- RBUF_HFB_256B
- RBUF_HFB_CTRL_V1
- RBUF_HFB_EN
- RBUF_HFB_FILTER_EN_MASK
- RBUF_HFB_FILTER_EN_SHIFT
- RBUF_HFB_LEN_V1
- RBUF_LEN
- RBUF_LEN_HI
- RBUF_LEN_LOW
- RBUF_MPD
- RBUF_OK_TO_SEND_MASK
- RBUF_OK_TO_SEND_MODE
- RBUF_OK_TO_SEND_SHIFT
- RBUF_OVFL_CNT_V2
- RBUF_OVFL_CNT_V3PLUS
- RBUF_OVFL_DISC_CNTR
- RBUF_PKT_RDY_THRESH
- RBUF_PM_EN
- RBUF_RESUME_THRESH_MASK
- RBUF_RESUME_THRESH_SHIFT
- RBUF_RSB_EN
- RBUF_RSB_SWAP0
- RBUF_RSB_SWAP1
- RBUF_RXCHK_EN
- RBUF_SIZE_MASK
- RBUF_SKIP_FCS
- RBUF_STATUS
- RBUF_STATUS_ACPI_INTR_ACTIVE
- RBUF_STATUS_MPD_INTR_ACTIVE
- RBUF_STATUS_WOL
- RBUF_TBUF_SIZE_CTRL
- RBUF_WOL_MODE
- RBURST_1024
- RBURST_128
- RBURST_16
- RBURST_256
- RBURST_32
- RBURST_4
- RBURST_64
- RBURST_DISABLE
- RBUSY_SHIFT
- RBV_BASE
- RBV_DEPTH
- RBV_MONID
- RBV_VIDOFF
- RBWAR
- RBX
- RB_128K_STRIPING
- RB_16BIT_BLENDER_UNITS_ACTIVE
- RB_1M_STRIPING
- RB_256K_STRIPING
- RB_32K_STRIPING
- RB_512K_STRIPING
- RB_64K_STRIPING
- RB_8BIT_BLENDER_UNITS_ACTIVE
- RB_A2R10G10B10_UINT
- RB_A2R10G10B10_UNORM
- RB_A8_UNORM
- RB_ADDR
- RB_ALIGNED
- RB_ALIGNED_META_SURF
- RB_ALIGNMENT
- RB_ALIGN_DATA
- RB_BACKEND_DISABLE
- RB_BACKEND_DISABLE_MASK
- RB_BACKEND_DISABLE_SHIFT
- RB_BLACK
- RB_BLKSZ
- RB_BUFFER_OFF
- RB_BUFSZ
- RB_BUSY_CYCLES
- RB_BUSY_CYCLES_BINNING
- RB_BUSY_CYCLES_RENDERING
- RB_BUSY_CYCLES_RESOLVE
- RB_BYPTR
- RB_BYVAL
- RB_CACHE_STALL_FIFO_FULL
- RB_CACHE_STALL_MISS
- RB_CFOLONGDUMP
- RB_CFOSHORTDUMP
- RB_CFO_LONG_DUMP
- RB_CFO_SHORT_DUMP
- RB_CLEAR_NODE
- RB_CLKSEL_DSP
- RB_CLKSEL_DSP_IF
- RB_CLKSEL_GFX
- RB_CLKSEL_L3
- RB_CLKSEL_L4
- RB_CLKSEL_MDM
- RB_CLKSEL_MPU
- RB_CLKSEL_USB
- RB_CMP3WAY
- RB_CM_CLKSEL1_CORE_VAL
- RB_CM_CLKSEL_DSP_VAL
- RB_CM_CLKSEL_GFX_VAL
- RB_CM_CLKSEL_MDM_VAL
- RB_CM_CLKSEL_MPU_VAL
- RB_COMPUTE_PASS
- RB_CONGESTED_REMOTE
- RB_COPY_CLEAR
- RB_COPY_DEPTH_STENCIL
- RB_COPY_RESOLVE
- RB_CP_CACHE_FLUSH
- RB_CP_CONTEXT_DONE
- RB_CP_ZPASS_DONE
- RB_CTRL
- RB_CTX_IRQ
- RB_CTX_MAX
- RB_CTX_NMI
- RB_CTX_NORMAL
- RB_CTX_SOFTIRQ
- RB_C_READ
- RB_C_READ_LATENCY
- RB_C_WRITE
- RB_DECLARE_CALLBACKS
- RB_DECLARE_CALLBACKS_MAX
- RB_DELAY_US
- RB_DIS_OP_MD
- RB_DIS_STFWD
- RB_EMPTY_NODE
- RB_EMPTY_ROOT
- RB_ENA_OP_MD
- RB_ENA_STFWD
- RB_END
- RB_EVENT_HDR_SIZE
- RB_EVNT_HDR_SIZE
- RB_EVNT_MIN_SIZE
- RB_FIRST
- RB_FLAG_MASK
- RB_FLUSH
- RB_FL_OVERWRITE
- RB_GMEM_CH0_READ
- RB_GMEM_CH0_WRITE
- RB_GMEM_CH1_READ
- RB_GMEM_CH1_WRITE
- RB_GREATER
- RB_HEAD_OFF_MASK
- RB_HEAD_WRAP_CNT_MAX
- RB_HEAD_WRAP_CNT_OFF
- RB_INSERT
- RB_INT_ENABLE
- RB_INT_STAT
- RB_LAST
- RB_LEAST_PENDING
- RB_LEN_TIME_EXTEND
- RB_LEN_TIME_STAMP
- RB_LEV
- RB_LSSIWRITE_8821A
- RB_MAP_PKR0
- RB_MAP_PKR0_MASK
- RB_MAP_PKR1
- RB_MAP_PKR1_MASK
- RB_MARB_UCHE_TRANSACTIONS
- RB_MASK
- RB_MAX_SMALL_DATA
- RB_MISSED_EVENTS
- RB_MISSED_FLAGS
- RB_MISSED_STORED
- RB_MSK
- RB_NEXT
- RB_NO_UPDATE
- RB_OVERFLOW
- RB_PAGE_HEAD
- RB_PAGE_MOVED
- RB_PAGE_NORMAL
- RB_PAGE_UPDATE
- RB_PC
- RB_PIN_ENABLED
- RB_PIN_ENABLED__BANK
- RB_PIREAD_8821A
- RB_POWER0
- RB_POWER1
- RB_POWER2
- RB_POWER3
- RB_POWER4
- RB_POWER5
- RB_POWER6
- RB_POWER7
- RB_PREFER_LOCAL
- RB_PREFER_REMOTE
- RB_PREV
- RB_R10G10B10A2_UINT
- RB_R10G10B10A2_UNORM
- RB_R11G11B10_FLOAT
- RB_R16G16B16A16_FLOAT
- RB_R16G16B16A16_SINT
- RB_R16G16B16A16_SNORM
- RB_R16G16B16A16_UINT
- RB_R16G16B16A16_UNORM
- RB_R16G16_FLOAT
- RB_R16G16_SINT
- RB_R16G16_SNORM
- RB_R16G16_UINT
- RB_R16G16_UNORM
- RB_R16_FLOAT
- RB_R16_SINT
- RB_R16_SNORM
- RB_R16_UINT
- RB_R16_UNORM
- RB_R32G32B32A32_FLOAT
- RB_R32G32B32A32_SINT
- RB_R32G32B32A32_UINT
- RB_R32G32_FLOAT
- RB_R32G32_SINT
- RB_R32G32_UINT
- RB_R32_FLOAT
- RB_R32_SINT
- RB_R32_UINT
- RB_R4G4B4A4_UNORM
- RB_R5G5B5A1_UNORM
- RB_R5G6B5_UNORM
- RB_R8G8B8A8_SINT
- RB_R8G8B8A8_SNORM
- RB_R8G8B8A8_UINT
- RB_R8G8B8A8_UNORM
- RB_R8G8B8_UNORM
- RB_R8G8_SNORM
- RB_R8G8_UNORM
- RB_R8_SINT
- RB_R8_UINT
- RB_R8_UNORM
- RB_RAS_RB_Z_QUADS
- RB_RBPERF_ACTIVE_CYCLES_ALL
- RB_RBPERF_ACTIVE_CYCLES_ANY
- RB_RBPERF_CP_CACHE_FLUSH
- RB_RBPERF_CP_CONTEXT_DONE
- RB_RBPERF_CP_ZPASS_DONE
- RB_RBPERF_GMEM_CH0_READ
- RB_RBPERF_GMEM_CH0_WRITE
- RB_RBPERF_GMEM_CH1_READ
- RB_RBPERF_GMEM_CH1_WRITE
- RB_RBPERF_RAS_EARLY_Z_QUADS
- RB_RBPERF_RB_MARB_DATA
- RB_RBPERF_SP_RB_QUAD
- RB_RBPERF_STALL_CYCLES_BY_HLSQ
- RB_RBPERF_STALL_CYCLES_BY_MARB
- RB_RBPERF_STARVE_CYCLES_BY_MARB
- RB_RBPERF_STARVE_CYCLES_BY_RAS
- RB_RBPERF_STARVE_CYCLES_BY_SP
- RB_RB_HLSQ_TRANSACTIONS
- RB_RB_RB_MARB_DATA
- RB_RED
- RB_RENDERING_PASS
- RB_RESERVED
- RB_RESOLVE_PASS
- RB_RFE_CTRL_8812
- RB_RFE_INV
- RB_RFE_PINMUX
- RB_ROOT
- RB_ROOT_CACHED
- RB_ROUND_ROBIN
- RB_RP
- RB_RPTR_SWAP
- RB_RPTR_SWAP_32BIT
- RB_RPTR_WR_ENA
- RB_RSSIDUMP
- RB_RSSI_DUMP
- RB_RST_CLR
- RB_RST_SET
- RB_RXIQC_AB
- RB_RXIQC_CD
- RB_RXSNRDUMP
- RB_RX_LTHP
- RB_RX_LTPP
- RB_RX_SNR_DUMP
- RB_RX_UTHP
- RB_RX_UTPP
- RB_SAMPLER_UNITS_ACTIVE
- RB_SEARCH
- RB_SIREAD_8821A
- RB_SIZE
- RB_SP_RB_QUAD
- RB_STALL_BY_UCHE
- RB_STALL_CYCLES_BY_HLSQ
- RB_STALL_CYCLES_BY_MARB
- RB_STALL_FIFO0_FULL
- RB_STALL_FIFO1_FULL
- RB_STALL_FIFO2_FULL
- RB_STALL_FIFO3_FULL
- RB_START
- RB_STARVE_CYCLES_BY_MARB
- RB_STARVE_CYCLES_BY_RAS
- RB_STARVE_CYCLES_BY_SP
- RB_S_FAIL
- RB_TAIL_OFF_MASK
- RB_TAIL_SIZE_MASK
- RB_TEST_BUFFER_SIZE
- RB_TILING_PASS
- RB_TOTAL_PASS
- RB_TREE_LATCH_H
- RB_TST1
- RB_TST2
- RB_TXPWRTRAING
- RB_TXSCALE
- RB_UNALIGNED_META_SURF
- RB_USB2PHY_PU
- RB_USB2PHY_SUSPM
- RB_WARN_ON
- RB_WP
- RB_WRITE_INTCNT
- RB_WRITE_MASK
- RB_XSEL
- RB_XSEL2
- RB_XSEL2_MASK
- RB_YSEL
- RB_Z_FAIL
- RB_Z_PASS
- RB_Z_READ
- RB_Z_READ_LATENCY
- RB_Z_WRITE
- RC
- RC1
- RC16_LEN
- RC2
- RC2ERR
- RC2WARN
- RC32434_AF_SPARE_2
- RC32434_AF_SPARE_3
- RC32434_AF_SPARE_4
- RC32434_AF_SPARE_6
- RC32434_CPU_GPIO
- RC32434_CTC_EN_BIT
- RC32434_CTC_TO_BIT
- RC32434_DCST_CAS_BIT
- RC32434_DCST_CS_BIT
- RC32434_DCST_CS_MSK
- RC32434_DCST_MSK
- RC32434_DCST_RAS_BIT
- RC32434_DCST_WE_BIT
- RC32434_DDR0_AP_BIT
- RC32434_DDR0_AP_MSK
- RC32434_DDR0_ATA_BIT
- RC32434_DDR0_ATA_MSK
- RC32434_DDR0_ATP_BIT
- RC32434_DDR0_ATP_MSK
- RC32434_DDR0_CL_BIT
- RC32434_DDR0_CL_MSK
- RC32434_DDR0_DBM_BIT
- RC32434_DDR0_DBM_MSK
- RC32434_DDR0_DBW_BIT
- RC32434_DDR0_DBW_MSK
- RC32434_DDR0_DTYPE_BIT
- RC32434_DDR0_DTYPE_MSK
- RC32434_DDR0_PS_BIT
- RC32434_DDR0_PS_MSK
- RC32434_DDR0_RCD_BIT
- RC32434_DDR0_RCD_MSK
- RC32434_DDR0_RE_BIT
- RC32434_DDR0_RE_MSK
- RC32434_DDR0_RFC_BIT
- RC32434_DDR0_RFC_MSK
- RC32434_DDR0_RP_BIT
- RC32434_DDR0_RP_MSK
- RC32434_DDR0_SDS_BIT
- RC32434_DDR0_SDS_MSK
- RC32434_DDR0_WR_BIT
- RC32434_DDR0_WR_MSK
- RC32434_DDRC_ACE_BIT
- RC32434_DDRC_CES_BIT
- RC32434_DDRC_MSK
- RC32434_DLLED_DBE_BIT
- RC32434_DLLED_DTE_BIT
- RC32434_DLLED_MSK
- RC32434_DLLTA_ADDR_BIT
- RC32434_DLLTA_ADDR_MSK
- RC32434_DSCT_BA_BIT
- RC32434_DSCT_BA_MSK
- RC32434_DSCT_CKE_BIT
- RC32434_ERR_SAE
- RC32434_ERR_UCR
- RC32434_ERR_UCW
- RC32434_ERR_UDR
- RC32434_ERR_UDW
- RC32434_ERR_UPR
- RC32434_ERR_UPW
- RC32434_ERR_WNE
- RC32434_ERR_WRE
- RC32434_ERR_WTO
- RC32434_LLC_AS_BIT
- RC32434_LLC_AS_MSK
- RC32434_LLC_EAO_BIT
- RC32434_LLC_EAO_MSK
- RC32434_LLC_EO_BIT
- RC32434_LLC_EO_MSK
- RC32434_LLC_FS_BIT
- RC32434_LLC_FS_MSK
- RC32434_LLC_SP_BIT
- RC32434_LLC_SP_MSK
- RC32434_LLFC_EAN_BIT
- RC32434_LLFC_FF_BIT
- RC32434_LLFC_MEN_BIT
- RC32434_LLFC_MSK
- RC32434_MP_BIT_22
- RC32434_MP_BIT_23
- RC32434_MP_BIT_24
- RC32434_MP_BIT_25
- RC32434_NR_IRQS
- RC32434_PCI_MSU_GPIO
- RC32434_QSC_BDP_BIT
- RC32434_QSC_BDP_MSK
- RC32434_QSC_DBSP_BIT
- RC32434_QSC_DBSP_MSK
- RC32434_QSC_DB_BIT
- RC32434_QSC_DB_MSK
- RC32434_QSC_DM_BIT
- RC32434_QSC_DM_MSK
- RC32434_QSC_DQSBS_BIT
- RC32434_QSC_DQSBS_MSK
- RC32434_RCOMP_BIT
- RC32434_RCOMP_MSK
- RC32434_RCOUNT_BIT
- RC32434_RCOUNT_MSK
- RC32434_RTC_CE_BIT
- RC32434_RTC_MSK
- RC32434_RTC_RQE_BIT
- RC32434_RTC_TO_BIT
- RC32434_UART0_CTS
- RC32434_UART0_RTS
- RC32434_UART0_SIN
- RC32434_UART0_SOUT
- RC32434_WTC_EN
- RC32434_WTC_TO
- RC48_CK
- RC4_KEY_SIZE
- RC5T583_DS_DC0
- RC5T583_DS_DC1
- RC5T583_DS_DC2
- RC5T583_DS_DC3
- RC5T583_DS_LDO0
- RC5T583_DS_LDO1
- RC5T583_DS_LDO2
- RC5T583_DS_LDO3
- RC5T583_DS_LDO4
- RC5T583_DS_LDO5
- RC5T583_DS_LDO6
- RC5T583_DS_LDO7
- RC5T583_DS_LDO8
- RC5T583_DS_LDO9
- RC5T583_DS_MAX
- RC5T583_DS_NONE
- RC5T583_DS_PSO0
- RC5T583_DS_PSO1
- RC5T583_DS_PSO2
- RC5T583_DS_PSO3
- RC5T583_DS_PSO4
- RC5T583_DS_PSO5
- RC5T583_DS_PSO6
- RC5T583_DS_PSO7
- RC5T583_EXT_PWRREQ1_CONTROL
- RC5T583_EXT_PWRREQ2_CONTROL
- RC5T583_GPIO0
- RC5T583_GPIO1
- RC5T583_GPIO2
- RC5T583_GPIO3
- RC5T583_GPIO4
- RC5T583_GPIO5
- RC5T583_GPIO6
- RC5T583_GPIO7
- RC5T583_GPIO_EN_INT
- RC5T583_GPIO_GPDEB
- RC5T583_GPIO_GPEDGE1
- RC5T583_GPIO_GPEDGE2
- RC5T583_GPIO_GPINV
- RC5T583_GPIO_GPOFUNC
- RC5T583_GPIO_IOOUT
- RC5T583_GPIO_IOSEL
- RC5T583_GPIO_MON_IOIN
- RC5T583_GPIO_PDEN
- RC5T583_GPIO_PGSEL
- RC5T583_INTC_INTEN
- RC5T583_INTC_INTMON
- RC5T583_INTC_INTPOL
- RC5T583_INT_EN_ADC1
- RC5T583_INT_EN_ADC2
- RC5T583_INT_EN_ADC3
- RC5T583_INT_EN_DCDC
- RC5T583_INT_EN_RTC
- RC5T583_INT_EN_SYS1
- RC5T583_INT_EN_SYS2
- RC5T583_INT_IR_ADCEND
- RC5T583_INT_IR_ADCH
- RC5T583_INT_IR_ADCL
- RC5T583_INT_IR_DCDC
- RC5T583_INT_IR_GPIOF
- RC5T583_INT_IR_GPIOR
- RC5T583_INT_IR_RTC
- RC5T583_INT_IR_SYS1
- RC5T583_INT_IR_SYS2
- RC5T583_INT_MON_DCDC
- RC5T583_INT_MON_GRP
- RC5T583_INT_MON_RTC
- RC5T583_INT_MON_SYS1
- RC5T583_INT_MON_SYS2
- RC5T583_IRQ
- RC5T583_IRQ_ACOK
- RC5T583_IRQ_ADCEND
- RC5T583_IRQ_AIN1H
- RC5T583_IRQ_AIN1L
- RC5T583_IRQ_AIN2H
- RC5T583_IRQ_AIN2L
- RC5T583_IRQ_AIN3H
- RC5T583_IRQ_AIN3L
- RC5T583_IRQ_CLKSTP
- RC5T583_IRQ_CTC
- RC5T583_IRQ_DALE
- RC5T583_IRQ_DC0LIM
- RC5T583_IRQ_DC1LIM
- RC5T583_IRQ_DC2LIM
- RC5T583_IRQ_DC3LIM
- RC5T583_IRQ_EN_PWRREQ1
- RC5T583_IRQ_EN_PWRREQ2
- RC5T583_IRQ_GPIO0
- RC5T583_IRQ_GPIO1
- RC5T583_IRQ_GPIO2
- RC5T583_IRQ_GPIO3
- RC5T583_IRQ_GPIO4
- RC5T583_IRQ_GPIO5
- RC5T583_IRQ_GPIO6
- RC5T583_IRQ_GPIO7
- RC5T583_IRQ_LIDOPEN
- RC5T583_IRQ_ONKEY
- RC5T583_IRQ_ONKEY_OFF
- RC5T583_IRQ_PREOT
- RC5T583_IRQ_PRE_VINDET
- RC5T583_IRQ_VBATH
- RC5T583_IRQ_VBATL
- RC5T583_IRQ_VIN3H
- RC5T583_IRQ_VIN3L
- RC5T583_IRQ_VIN8H
- RC5T583_IRQ_VIN8L
- RC5T583_IRQ_WALE
- RC5T583_IRQ_WD
- RC5T583_IRQ_YALE
- RC5T583_MAX_GPEDGE_REG
- RC5T583_MAX_GPIO
- RC5T583_MAX_INTERRUPT_EN_REGS
- RC5T583_MAX_INTERRUPT_MASK_REGS
- RC5T583_MAX_IRQS
- RC5T583_MAX_REG
- RC5T583_NUM_REGS
- RC5T583_REG
- RC5T583_REGULATOR_DC0
- RC5T583_REGULATOR_DC1
- RC5T583_REGULATOR_DC2
- RC5T583_REGULATOR_DC3
- RC5T583_REGULATOR_LDO0
- RC5T583_REGULATOR_LDO1
- RC5T583_REGULATOR_LDO2
- RC5T583_REGULATOR_LDO3
- RC5T583_REGULATOR_LDO4
- RC5T583_REGULATOR_LDO5
- RC5T583_REGULATOR_LDO6
- RC5T583_REGULATOR_LDO7
- RC5T583_REGULATOR_LDO8
- RC5T583_REGULATOR_LDO9
- RC5T583_REGULATOR_MAX
- RC5T583_REG_DC0CTL
- RC5T583_REG_DC0DAC
- RC5T583_REG_DC0DAC_DS
- RC5T583_REG_DC0LATCTL
- RC5T583_REG_DC1CTL
- RC5T583_REG_DC1DAC
- RC5T583_REG_DC1DAC_DS
- RC5T583_REG_DC1LATCTL
- RC5T583_REG_DC2CTL
- RC5T583_REG_DC2DAC
- RC5T583_REG_DC2DAC_DS
- RC5T583_REG_DC2LATCTL
- RC5T583_REG_DC3CTL
- RC5T583_REG_DC3DAC
- RC5T583_REG_DC3DAC_DS
- RC5T583_REG_DC3LATCTL
- RC5T583_REG_LDO0DAC
- RC5T583_REG_LDO0DAC_DS
- RC5T583_REG_LDO1DAC
- RC5T583_REG_LDO1DAC_DS
- RC5T583_REG_LDO2DAC
- RC5T583_REG_LDO2DAC_DS
- RC5T583_REG_LDO3DAC
- RC5T583_REG_LDO3DAC_DS
- RC5T583_REG_LDO4DAC
- RC5T583_REG_LDO4DAC_DS
- RC5T583_REG_LDO5DAC
- RC5T583_REG_LDO5DAC_DS
- RC5T583_REG_LDO6DAC
- RC5T583_REG_LDO6DAC_DS
- RC5T583_REG_LDO7DAC
- RC5T583_REG_LDO7DAC_DS
- RC5T583_REG_LDO8DAC
- RC5T583_REG_LDO8DAC_DS
- RC5T583_REG_LDO9DAC
- RC5T583_REG_LDO9DAC_DS
- RC5T583_REG_LDODIS1
- RC5T583_REG_LDODIS2
- RC5T583_REG_LDOEN1
- RC5T583_REG_LDOEN2
- RC5T583_REG_SR0CTL
- RC5T583_REG_SR1CTL
- RC5T583_REG_SR2CTL
- RC5T583_REG_SR3CTL
- RC5T583_RTC_ADJ
- RC5T583_RTC_AD_HOUR
- RC5T583_RTC_AD_MIN
- RC5T583_RTC_AW_HOUR
- RC5T583_RTC_AW_MIN
- RC5T583_RTC_AW_WEEK
- RC5T583_RTC_AY_DAY
- RC5T583_RTC_AY_HOUR
- RC5T583_RTC_AY_MIN
- RC5T583_RTC_AY_MONTH
- RC5T583_RTC_AY_YEAR
- RC5T583_RTC_CTL1
- RC5T583_RTC_CTL2
- RC5T583_RTC_DAY
- RC5T583_RTC_HOUR
- RC5T583_RTC_MIN
- RC5T583_RTC_MONTH
- RC5T583_RTC_SEC
- RC5T583_RTC_WDAY
- RC5T583_RTC_YEAR
- RC5T583_SLPSEQ1
- RC5T583_SLPSEQ10
- RC5T583_SLPSEQ11
- RC5T583_SLPSEQ2
- RC5T583_SLPSEQ3
- RC5T583_SLPSEQ4
- RC5T583_SLPSEQ5
- RC5T583_SLPSEQ6
- RC5T583_SLPSEQ7
- RC5T583_SLPSEQ8
- RC5T583_SLPSEQ9
- RC5T619
- RC5X_NBITS
- RC5X_SPACE
- RC5_ADDR
- RC5_BIT_END
- RC5_BIT_START
- RC5_INSTR
- RC5_NBITS
- RC5_START
- RC5_START_PULSE
- RC5_START_SPACE
- RC5_SZ_NBITS
- RC5_TIME_BASE
- RC5_TOGGLE
- RC5_TRAILER
- RC5_UNIT
- RC6_0_NBITS
- RC6_6A_32_NBITS
- RC6_6A_KATHREIN_CC
- RC6_6A_LCC_MASK
- RC6_6A_MCE_CC
- RC6_6A_MCE_TOGGLE_MASK
- RC6_6A_NBITS
- RC6_6A_ZOTAC_CC
- RC6_BIT_END
- RC6_BIT_START
- RC6_CARRIER
- RC6_CLKDIV
- RC6_CTRL
- RC6_CTX_BASE
- RC6_CTX_BASE_MASK
- RC6_CTX_IN_DRAM
- RC6_DATA0
- RC6_DATA1
- RC6_DATA2
- RC6_DATA3
- RC6_DATA4
- RC6_HEADER_NBITS
- RC6_LOCATION
- RC6_MODE_0
- RC6_MODE_6A
- RC6_MODE_MASK
- RC6_MODE_UNKNOWN
- RC6_PREFIX_PULSE
- RC6_PREFIX_SPACE
- RC6_STARTBIT_MASK
- RC6_SUFFIX_SPACE
- RC6_TIME_BASE
- RC6_TOGGLE_END
- RC6_TOGGLE_START
- RC6_UNIT
- RCA
- RCA4_TYPE_MASK_ALL
- RCA4_TYPE_MASK_BLK_LAYOUT
- RCA4_TYPE_MASK_DIR_DLG
- RCA4_TYPE_MASK_FILE_LAYOUT
- RCA4_TYPE_MASK_OBJ_LAYOUT_MAX
- RCA4_TYPE_MASK_OBJ_LAYOUT_MIN
- RCA4_TYPE_MASK_OTHER_LAYOUT_MAX
- RCA4_TYPE_MASK_OTHER_LAYOUT_MIN
- RCA4_TYPE_MASK_RDATA_DLG
- RCA4_TYPE_MASK_WDATA_DLG
- RCAMO
- RCAMO_8723B
- RCAN0
- RCAN1
- RCAN2
- RCANFD_CANFDCLK
- RCANFD_CCFG
- RCANFD_CCTR
- RCANFD_CCTR_ALIE
- RCANFD_CCTR_BEIE
- RCANFD_CCTR_BLIE
- RCANFD_CCTR_BOEIE
- RCANFD_CCTR_BOM_BEND
- RCANFD_CCTR_BOM_BENTRY
- RCANFD_CCTR_BOM_ISO
- RCANFD_CCTR_BOM_MASK
- RCANFD_CCTR_BORIE
- RCANFD_CCTR_CHDMC_CHLT
- RCANFD_CCTR_CHDMC_COPM
- RCANFD_CCTR_CHDMC_CRESET
- RCANFD_CCTR_CHMDC_MASK
- RCANFD_CCTR_CSLPR
- RCANFD_CCTR_CTME
- RCANFD_CCTR_EOCOIE
- RCANFD_CCTR_EPIE
- RCANFD_CCTR_ERRD
- RCANFD_CCTR_EWIE
- RCANFD_CCTR_OLIE
- RCANFD_CCTR_SOCOIE
- RCANFD_CCTR_TAIE
- RCANFD_CCTR_TDCVFIE
- RCANFD_CERFL
- RCANFD_CERFL_ADERR
- RCANFD_CERFL_AERR
- RCANFD_CERFL_ALF
- RCANFD_CERFL_B0ERR
- RCANFD_CERFL_B1ERR
- RCANFD_CERFL_BEF
- RCANFD_CERFL_BLF
- RCANFD_CERFL_BOEF
- RCANFD_CERFL_BORF
- RCANFD_CERFL_CERR
- RCANFD_CERFL_EPF
- RCANFD_CERFL_ERR
- RCANFD_CERFL_EWF
- RCANFD_CERFL_FERR
- RCANFD_CERFL_OVLF
- RCANFD_CERFL_SERR
- RCANFD_CFCC
- RCANFD_CFCC_CFDC
- RCANFD_CFCC_CFE
- RCANFD_CFCC_CFIM
- RCANFD_CFCC_CFM
- RCANFD_CFCC_CFPLS
- RCANFD_CFCC_CFTML
- RCANFD_CFCC_CFTXIE
- RCANFD_CFFDCSTS_CFBRS
- RCANFD_CFFDCSTS_CFESI
- RCANFD_CFFDCSTS_CFFDF
- RCANFD_CFFIFO_IDX
- RCANFD_CFG_BRP
- RCANFD_CFG_SJW
- RCANFD_CFG_TSEG1
- RCANFD_CFG_TSEG2
- RCANFD_CFID_CFIDE
- RCANFD_CFID_CFID_MASK
- RCANFD_CFID_CFRTR
- RCANFD_CFPCTR
- RCANFD_CFPTR_CFDLC
- RCANFD_CFPTR_CFPTR
- RCANFD_CFPTR_CFTS
- RCANFD_CFRISTS
- RCANFD_CFSTS
- RCANFD_CFSTS_CFEMP
- RCANFD_CFSTS_CFFLL
- RCANFD_CFSTS_CFMC
- RCANFD_CFSTS_CFMLT
- RCANFD_CFSTS_CFTXIF
- RCANFD_CFTISTS
- RCANFD_CHANNELS_MASK
- RCANFD_CHANNEL_NUMRULES
- RCANFD_CSTS
- RCANFD_CSTS_BOSTS
- RCANFD_CSTS_COMSTS
- RCANFD_CSTS_CRSTSTS
- RCANFD_CSTS_EPSTS
- RCANFD_CSTS_HLTSTS
- RCANFD_CSTS_RECCNT
- RCANFD_CSTS_RECSTS
- RCANFD_CSTS_SLPSTS
- RCANFD_CSTS_TECCNT
- RCANFD_CSTS_TRMSTS
- RCANFD_C_CFDF
- RCANFD_C_CFID
- RCANFD_C_CFOFFSET
- RCANFD_C_CFPTR
- RCANFD_C_GAFL_OFFSET
- RCANFD_C_RFDF
- RCANFD_C_RFID
- RCANFD_C_RFOFFSET
- RCANFD_C_RFPTR
- RCANFD_C_RMDF0
- RCANFD_C_RMDF1
- RCANFD_C_RMID
- RCANFD_C_RMPTR
- RCANFD_C_RPGACC
- RCANFD_C_THLACC
- RCANFD_C_TMDF0
- RCANFD_C_TMDF1
- RCANFD_C_TMID
- RCANFD_C_TMPTR
- RCANFD_DCFG_DBRP
- RCANFD_DCFG_DSJW
- RCANFD_DCFG_DTSEG1
- RCANFD_DCFG_DTSEG2
- RCANFD_DRV_NAME
- RCANFD_EXTCLK
- RCANFD_FDCFG_TDCE
- RCANFD_FDCFG_TDCO
- RCANFD_FDCFG_TDCOC
- RCANFD_FESTS
- RCANFD_FFSTS
- RCANFD_FIFO_DEPTH
- RCANFD_FMSTS
- RCANFD_F_CFDCFG
- RCANFD_F_CFDCRC
- RCANFD_F_CFDCTR
- RCANFD_F_CFDF
- RCANFD_F_CFDSTS
- RCANFD_F_CFFDCSTS
- RCANFD_F_CFID
- RCANFD_F_CFOFFSET
- RCANFD_F_CFPTR
- RCANFD_F_DCFG
- RCANFD_F_GAFL_OFFSET
- RCANFD_F_RFDF
- RCANFD_F_RFFDSTS
- RCANFD_F_RFID
- RCANFD_F_RFOFFSET
- RCANFD_F_RFPTR
- RCANFD_F_RMDF
- RCANFD_F_RMFDSTS
- RCANFD_F_RMID
- RCANFD_F_RMPTR
- RCANFD_F_RPGACC
- RCANFD_F_THLACC
- RCANFD_F_TMDF
- RCANFD_F_TMFDCTR
- RCANFD_F_TMID
- RCANFD_F_TMPTR
- RCANFD_GAFLCFG0
- RCANFD_GAFLCFG1
- RCANFD_GAFLCFG_GETRNC
- RCANFD_GAFLCFG_SETRNC
- RCANFD_GAFLECTR
- RCANFD_GAFLECTR_AFLDAE
- RCANFD_GAFLECTR_AFLPN
- RCANFD_GAFLID
- RCANFD_GAFLID_GAFLLB
- RCANFD_GAFLM
- RCANFD_GAFLP0
- RCANFD_GAFLP1
- RCANFD_GAFLP1_GAFLFDP
- RCANFD_GAFL_PAGENUM
- RCANFD_GCFG
- RCANFD_GCFG_CMPOC
- RCANFD_GCFG_DCE
- RCANFD_GCFG_DCS
- RCANFD_GCFG_EEFE
- RCANFD_GCFG_TPRI
- RCANFD_GCTR
- RCANFD_GCTR_CFMPOFIE
- RCANFD_GCTR_DEIE
- RCANFD_GCTR_GMDC_GOPM
- RCANFD_GCTR_GMDC_GRESET
- RCANFD_GCTR_GMDC_GTEST
- RCANFD_GCTR_GMDC_MASK
- RCANFD_GCTR_GSLPR
- RCANFD_GCTR_MEIE
- RCANFD_GCTR_THLEIE
- RCANFD_GCTR_TSRST
- RCANFD_GERFL
- RCANFD_GERFL_CMPOF
- RCANFD_GERFL_DEF
- RCANFD_GERFL_EEF0
- RCANFD_GERFL_EEF1
- RCANFD_GERFL_ERR
- RCANFD_GERFL_MES
- RCANFD_GERFL_THLES
- RCANFD_GLOCKK
- RCANFD_GRMCFG
- RCANFD_GRMCFG_RCMC
- RCANFD_GSTS
- RCANFD_GSTS_GHLTSTS
- RCANFD_GSTS_GNOPM
- RCANFD_GSTS_GRAMINIT
- RCANFD_GSTS_GRSTSTS
- RCANFD_GSTS_GSLPSTS
- RCANFD_GTINTSTS0
- RCANFD_GTINTSTS1
- RCANFD_GTSC
- RCANFD_GTSTCFG
- RCANFD_GTSTCTR
- RCANFD_NAPI_WEIGHT
- RCANFD_NCFG_NBRP
- RCANFD_NCFG_NSJW
- RCANFD_NCFG_NTSEG1
- RCANFD_NCFG_NTSEG2
- RCANFD_NUM_CHANNELS
- RCANFD_RFCC
- RCANFD_RFCC_RFDC
- RCANFD_RFCC_RFE
- RCANFD_RFCC_RFIE
- RCANFD_RFCC_RFIM
- RCANFD_RFCC_RFPLS
- RCANFD_RFFDSTS_RFBRS
- RCANFD_RFFDSTS_RFESI
- RCANFD_RFFDSTS_RFFDF
- RCANFD_RFFIFO_IDX
- RCANFD_RFID_RFIDE
- RCANFD_RFID_RFRTR
- RCANFD_RFISTS
- RCANFD_RFPCTR
- RCANFD_RFPTR_RFDLC
- RCANFD_RFPTR_RFPTR
- RCANFD_RFPTR_RFTS
- RCANFD_RFSTS
- RCANFD_RFSTS_RFEMP
- RCANFD_RFSTS_RFFLL
- RCANFD_RFSTS_RFIF
- RCANFD_RFSTS_RFMLT
- RCANFD_RMNB
- RCANFD_RMND
- RCANFD_THLCC
- RCANFD_THLPCTR
- RCANFD_THLSTS
- RCANFD_TMC
- RCANFD_TMIEC
- RCANFD_TMSTS
- RCANFD_TMTARSTS
- RCANFD_TMTASTS
- RCANFD_TMTCSTS
- RCANFD_TMTRSTS
- RCANFD_TXQCC
- RCANFD_TXQPCTR
- RCANFD_TXQSTS
- RCAN_M
- RCAN_P
- RCAP_F
- RCAP_S
- RCAP_V
- RCAR3_THERMAL_GRAN
- RCAR_AHBPCI_PCICOM_OFFSET
- RCAR_AHBPCI_WIN1_CTR_REG
- RCAR_AHBPCI_WIN1_DEVICE
- RCAR_AHBPCI_WIN1_HOST
- RCAR_AHBPCI_WIN2_CTR_REG
- RCAR_AHBPCI_WIN_CTR_CFG
- RCAR_AHBPCI_WIN_CTR_MEM
- RCAR_AHB_BUS_CTR_REG
- RCAR_AHB_BUS_MMODE_BYTE_BURST
- RCAR_AHB_BUS_MMODE_HBUS_REQ
- RCAR_AHB_BUS_MMODE_HTRANS
- RCAR_AHB_BUS_MMODE_WR_INCR
- RCAR_AHB_BUS_MODE
- RCAR_AHB_BUS_SMODE_READYCTR
- RCAR_BUS_MASK_DATA
- RCAR_BUS_PHASE_DATA
- RCAR_BUS_PHASE_START
- RCAR_BUS_PHASE_STOP
- RCAR_CAN_BCR_BPR
- RCAR_CAN_BCR_SJW
- RCAR_CAN_BCR_TSEG1
- RCAR_CAN_BCR_TSEG2
- RCAR_CAN_CTLR_BOM
- RCAR_CAN_CTLR_BOM_ENT
- RCAR_CAN_CTLR_CANM
- RCAR_CAN_CTLR_CANM_FORCE_RESET
- RCAR_CAN_CTLR_CANM_HALT
- RCAR_CAN_CTLR_CANM_RESET
- RCAR_CAN_CTLR_IDFM
- RCAR_CAN_CTLR_IDFM_MIXED
- RCAR_CAN_CTLR_MBM
- RCAR_CAN_CTLR_MLM
- RCAR_CAN_CTLR_SLPM
- RCAR_CAN_DRV_NAME
- RCAR_CAN_ECSR_ADEF
- RCAR_CAN_ECSR_AEF
- RCAR_CAN_ECSR_BE0F
- RCAR_CAN_ECSR_BE1F
- RCAR_CAN_ECSR_CEF
- RCAR_CAN_ECSR_EDPM
- RCAR_CAN_ECSR_FEF
- RCAR_CAN_ECSR_SEF
- RCAR_CAN_EIER_BEIE
- RCAR_CAN_EIER_BLIE
- RCAR_CAN_EIER_BOEIE
- RCAR_CAN_EIER_BORIE
- RCAR_CAN_EIER_EPIE
- RCAR_CAN_EIER_EWIE
- RCAR_CAN_EIER_OLIE
- RCAR_CAN_EIER_ORIE
- RCAR_CAN_EIFR_BEIF
- RCAR_CAN_EIFR_BLIF
- RCAR_CAN_EIFR_BOEIF
- RCAR_CAN_EIFR_BORIF
- RCAR_CAN_EIFR_EPIF
- RCAR_CAN_EIFR_EWIF
- RCAR_CAN_EIFR_OLIF
- RCAR_CAN_EIFR_ORIF
- RCAR_CAN_FIDCR_IDE
- RCAR_CAN_FIDCR_RTR
- RCAR_CAN_FIFO_DEPTH
- RCAR_CAN_IDE
- RCAR_CAN_IER_ERSIE
- RCAR_CAN_IER_RXFIE
- RCAR_CAN_IER_TXFIE
- RCAR_CAN_ISR_ERSF
- RCAR_CAN_ISR_RXFF
- RCAR_CAN_ISR_TXFF
- RCAR_CAN_MIER1_RXFIE
- RCAR_CAN_MIER1_TXFIE
- RCAR_CAN_NAPI_WEIGHT
- RCAR_CAN_N_MBX
- RCAR_CAN_N_RX_MKREGS1
- RCAR_CAN_N_RX_MKREGS2
- RCAR_CAN_RFCR_RFE
- RCAR_CAN_RFCR_RFEST
- RCAR_CAN_RTR
- RCAR_CAN_RX_FIFO_MBX
- RCAR_CAN_SID_SHIFT
- RCAR_CAN_STR_RSTST
- RCAR_CAN_TFCR_TFE
- RCAR_CAN_TFCR_TFUST
- RCAR_CAN_TFCR_TFUST_SHIFT
- RCAR_CAN_TX_FIFO_MBX
- RCAR_CSI2_SINK
- RCAR_CSI2_SOURCE_VC0
- RCAR_CSI2_SOURCE_VC1
- RCAR_CSI2_SOURCE_VC2
- RCAR_CSI2_SOURCE_VC3
- RCAR_DMABUFCR
- RCAR_DMABUFCR_MBU
- RCAR_DMABUFCR_ULB
- RCAR_DMACHCLR
- RCAR_DMACHCR
- RCAR_DMACHCRB
- RCAR_DMACHCRB_DCNT
- RCAR_DMACHCRB_DPTR_MASK
- RCAR_DMACHCRB_DPTR_SHIFT
- RCAR_DMACHCRB_DRST
- RCAR_DMACHCRB_DTS
- RCAR_DMACHCRB_PRI
- RCAR_DMACHCRB_SLM_CLK
- RCAR_DMACHCRB_SLM_NORMAL
- RCAR_DMACHCR_CAE
- RCAR_DMACHCR_CAIE
- RCAR_DMACHCR_DE
- RCAR_DMACHCR_DM_DEC
- RCAR_DMACHCR_DM_FIXED
- RCAR_DMACHCR_DM_INC
- RCAR_DMACHCR_DPB
- RCAR_DMACHCR_DPM_DISABLED
- RCAR_DMACHCR_DPM_ENABLED
- RCAR_DMACHCR_DPM_INFINITE
- RCAR_DMACHCR_DPM_REPEAT
- RCAR_DMACHCR_DSE
- RCAR_DMACHCR_DSIE
- RCAR_DMACHCR_IE
- RCAR_DMACHCR_RPT_DAR
- RCAR_DMACHCR_RPT_SAR
- RCAR_DMACHCR_RPT_TCR
- RCAR_DMACHCR_RS_AUTO
- RCAR_DMACHCR_RS_DMARS
- RCAR_DMACHCR_SM_DEC
- RCAR_DMACHCR_SM_FIXED
- RCAR_DMACHCR_SM_INC
- RCAR_DMACHCR_TE
- RCAR_DMACHCR_TS_16B
- RCAR_DMACHCR_TS_1B
- RCAR_DMACHCR_TS_2B
- RCAR_DMACHCR_TS_32B
- RCAR_DMACHCR_TS_4B
- RCAR_DMACHCR_TS_64B
- RCAR_DMACHCR_TS_8B
- RCAR_DMAC_CHAN_OFFSET
- RCAR_DMAC_DESCS_PER_PAGE
- RCAR_DMAC_MAX_CHANNELS
- RCAR_DMAC_MAX_SG_LEN
- RCAR_DMAC_MEMCPY_XFER_SIZE
- RCAR_DMAC_XFER_CHUNKS_PER_PAGE
- RCAR_DMADAR
- RCAR_DMADPBASE
- RCAR_DMADPBASE_MASK
- RCAR_DMADPBASE_SEL
- RCAR_DMADPCR
- RCAR_DMADPCR_DIPT
- RCAR_DMADPSEC
- RCAR_DMAFIXDAR
- RCAR_DMAFIXDPBASE
- RCAR_DMAFIXSAR
- RCAR_DMAISTA
- RCAR_DMAOR
- RCAR_DMAOR_AE
- RCAR_DMAOR_DME
- RCAR_DMAOR_PRI_FIXED
- RCAR_DMAOR_PRI_ROUND_ROBIN
- RCAR_DMARS
- RCAR_DMASAR
- RCAR_DMASEC
- RCAR_DMATCR
- RCAR_DMATCRB
- RCAR_DMATCR_MASK
- RCAR_DMATSR
- RCAR_DMATSRB
- RCAR_DRIF_BUF_DONE
- RCAR_DRIF_BUF_OVERFLOW
- RCAR_DRIF_DEFAULT_HWBUF_SIZE
- RCAR_DRIF_DEFAULT_NUM_HWBUFS
- RCAR_DRIF_DRV_NAME
- RCAR_DRIF_MAX_CHANNEL
- RCAR_DRIF_MAX_DEVS
- RCAR_DRIF_MDR_BITLEN
- RCAR_DRIF_MDR_GRPCNT
- RCAR_DRIF_MDR_WDCNT
- RCAR_DRIF_NUM_HWBUFS
- RCAR_DRIF_RDREQ
- RCAR_DRIF_REOF
- RCAR_DRIF_RFFUL
- RCAR_DRIF_RFOVF
- RCAR_DRIF_RFSERR
- RCAR_DRIF_RFUDF
- RCAR_DRIF_SICTR
- RCAR_DRIF_SICTR_RESET
- RCAR_DRIF_SICTR_RX_EN
- RCAR_DRIF_SICTR_RX_RISING_EDGE
- RCAR_DRIF_SIFCTR
- RCAR_DRIF_SIIER
- RCAR_DRIF_SIRFDR
- RCAR_DRIF_SIRMDR1
- RCAR_DRIF_SIRMDR1_DTDL_0
- RCAR_DRIF_SIRMDR1_DTDL_0PT5
- RCAR_DRIF_SIRMDR1_DTDL_1
- RCAR_DRIF_SIRMDR1_DTDL_1PT5
- RCAR_DRIF_SIRMDR1_DTDL_2
- RCAR_DRIF_SIRMDR1_LSB_FIRST
- RCAR_DRIF_SIRMDR1_MSB_FIRST
- RCAR_DRIF_SIRMDR1_SYNCAC_POL_HIGH
- RCAR_DRIF_SIRMDR1_SYNCAC_POL_LOW
- RCAR_DRIF_SIRMDR1_SYNCDL_0
- RCAR_DRIF_SIRMDR1_SYNCDL_0PT5
- RCAR_DRIF_SIRMDR1_SYNCDL_1
- RCAR_DRIF_SIRMDR1_SYNCDL_1PT5
- RCAR_DRIF_SIRMDR1_SYNCDL_2
- RCAR_DRIF_SIRMDR1_SYNCDL_3
- RCAR_DRIF_SIRMDR1_SYNCMD_FRAME
- RCAR_DRIF_SIRMDR1_SYNCMD_LR
- RCAR_DRIF_SIRMDR2
- RCAR_DRIF_SIRMDR3
- RCAR_DRIF_SISTR
- RCAR_DRIF_SITMDR1
- RCAR_DRIF_SITMDR1_PCON
- RCAR_DRIF_SITMDR2
- RCAR_DRIF_SITMDR3
- RCAR_DU_COLORKEY_MASK
- RCAR_DU_COLORKEY_NONE
- RCAR_DU_COLORKEY_SOURCE
- RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
- RCAR_DU_FEATURE_INTERLACED
- RCAR_DU_FEATURE_TVM_SYNC
- RCAR_DU_FEATURE_VSP1_SOURCE
- RCAR_DU_MAX_CRTCS
- RCAR_DU_MAX_GROUPS
- RCAR_DU_MAX_VSPS
- RCAR_DU_NUM_HW_PLANES
- RCAR_DU_NUM_KMS_PLANES
- RCAR_DU_OF_DTB
- RCAR_DU_OF_OVERLAY
- RCAR_DU_OUTPUT_DPAD0
- RCAR_DU_OUTPUT_DPAD1
- RCAR_DU_OUTPUT_HDMI0
- RCAR_DU_OUTPUT_HDMI1
- RCAR_DU_OUTPUT_LVDS0
- RCAR_DU_OUTPUT_LVDS1
- RCAR_DU_OUTPUT_MAX
- RCAR_DU_OUTPUT_TCON
- RCAR_DU_PLANE_MEMORY
- RCAR_DU_PLANE_VSPD0
- RCAR_DU_PLANE_VSPD1
- RCAR_DU_QUIRK_ALIGN_128B
- RCAR_GEN1_SATA
- RCAR_GEN2
- RCAR_GEN2_PHY_CTL1
- RCAR_GEN2_PHY_CTL1_REG
- RCAR_GEN2_PHY_CTL1_SS
- RCAR_GEN2_PHY_CTL2
- RCAR_GEN2_PHY_CTL2_REG
- RCAR_GEN2_PHY_CTL3
- RCAR_GEN2_PHY_CTL3_REG
- RCAR_GEN2_PHY_CTL4
- RCAR_GEN2_PHY_CTL4_REG
- RCAR_GEN2_PHY_CTL5
- RCAR_GEN2_PHY_CTL5_DC
- RCAR_GEN2_PHY_CTL5_REG
- RCAR_GEN2_PHY_CTL5_TR
- RCAR_GEN2_SATA
- RCAR_GEN3
- RCAR_GEN3_SATA
- RCAR_GYROADC_100MS_ADDED_DATA
- RCAR_GYROADC_10MS_AVG_DATA
- RCAR_GYROADC_1_25MS_LENGTH
- RCAR_GYROADC_CHAN
- RCAR_GYROADC_CLOCK_LENGTH
- RCAR_GYROADC_FIFO_STATUS
- RCAR_GYROADC_FIFO_STATUS_EMPTY
- RCAR_GYROADC_FIFO_STATUS_ERROR
- RCAR_GYROADC_FIFO_STATUS_FULL
- RCAR_GYROADC_INTENR
- RCAR_GYROADC_INTENR_INTEN
- RCAR_GYROADC_INTR
- RCAR_GYROADC_INTR_INT
- RCAR_GYROADC_MODEL_DEFAULT
- RCAR_GYROADC_MODEL_R8A7792
- RCAR_GYROADC_MODE_SELECT
- RCAR_GYROADC_MODE_SELECT_1_MB88101A
- RCAR_GYROADC_MODE_SELECT_2_ADCS7476
- RCAR_GYROADC_MODE_SELECT_3_MAX1162
- RCAR_GYROADC_REALTIME_DATA
- RCAR_GYROADC_RUNTIME_PM_DELAY_MS
- RCAR_GYROADC_SAMPLE_RATE
- RCAR_GYROADC_START_STOP
- RCAR_GYROADC_START_STOP_START
- RCAR_H1
- RCAR_H2
- RCAR_HDMI_PHY_OPMODE_PLLCFG
- RCAR_HDMI_PHY_PLLCURRGMPCTRL
- RCAR_HDMI_PHY_PLLDIVCTRL
- RCAR_IRQ_ACK_RECV
- RCAR_IRQ_ACK_SEND
- RCAR_IRQ_RECV
- RCAR_IRQ_SEND
- RCAR_IRQ_STOP
- RCAR_LVDS_MODE_JEIDA
- RCAR_LVDS_MODE_MIRROR
- RCAR_LVDS_MODE_VESA
- RCAR_LVDS_QUIRK_DUAL_LINK
- RCAR_LVDS_QUIRK_EXT_PLL
- RCAR_LVDS_QUIRK_GEN3_LVEN
- RCAR_LVDS_QUIRK_LANES
- RCAR_LVDS_QUIRK_PWD
- RCAR_M1
- RCAR_M3
- RCAR_MAX_GPIO_PER_BANK
- RCAR_MIN_DMA_LEN
- RCAR_PCIAHB_PREFETCH0
- RCAR_PCIAHB_PREFETCH16
- RCAR_PCIAHB_PREFETCH4
- RCAR_PCIAHB_PREFETCH8
- RCAR_PCIAHB_WIN1_CTR_REG
- RCAR_PCIAHB_WIN2_CTR_REG
- RCAR_PCI_ACCESS_READ
- RCAR_PCI_ACCESS_WRITE
- RCAR_PCI_ARBITER_CTR_REG
- RCAR_PCI_ARBITER_PCIBP_MODE
- RCAR_PCI_ARBITER_PCIREQ0
- RCAR_PCI_ARBITER_PCIREQ1
- RCAR_PCI_INT_A
- RCAR_PCI_INT_ALLERRORS
- RCAR_PCI_INT_B
- RCAR_PCI_INT_ENABLE_REG
- RCAR_PCI_INT_PERR
- RCAR_PCI_INT_PME
- RCAR_PCI_INT_REMABORT
- RCAR_PCI_INT_RESERR
- RCAR_PCI_INT_SIGRETABORT
- RCAR_PCI_INT_SIGSERR
- RCAR_PCI_INT_SIGTABORT
- RCAR_PCI_INT_STATUS_REG
- RCAR_PCI_INT_WIN1ERR
- RCAR_PCI_INT_WIN2ERR
- RCAR_PCI_MAX_RESOURCES
- RCAR_PCI_UNIT_REV_REG
- RCAR_PD_ALWAYS_ON
- RCAR_PWMCNT
- RCAR_PWMCNT_CYC0_MASK
- RCAR_PWMCNT_CYC0_SHIFT
- RCAR_PWMCNT_PH0_MASK
- RCAR_PWMCNT_PH0_SHIFT
- RCAR_PWMCR
- RCAR_PWMCR_CC0_MASK
- RCAR_PWMCR_CC0_SHIFT
- RCAR_PWMCR_CCMD
- RCAR_PWMCR_EN0
- RCAR_PWMCR_SS0
- RCAR_PWMCR_SYNC
- RCAR_PWM_MAX_CYCLE
- RCAR_PWM_MAX_DIVISION
- RCAR_R8A7790_ES1_SATA
- RCAR_SDR_BUFFER_SIZE
- RCAR_SUPPORTED_CLOCKS
- RCAR_USB3_AXH_STA
- RCAR_USB3_AXH_STA_B2_PLL_ACTIVE
- RCAR_USB3_AXH_STA_B3_PLL_ACTIVE
- RCAR_USB3_AXH_STA_PLL_ACTIVE_MASK
- RCAR_USB3_CONF1
- RCAR_USB3_CONF1_VAL
- RCAR_USB3_CONF2
- RCAR_USB3_CONF2_VAL
- RCAR_USB3_CONF3
- RCAR_USB3_CONF3_VAL
- RCAR_USB3_DL_CTRL
- RCAR_USB3_DL_CTRL_ENABLE
- RCAR_USB3_DL_CTRL_FW_SET_DATA0
- RCAR_USB3_DL_CTRL_FW_SUCCESS
- RCAR_USB3_FW_DATA0
- RCAR_USB3_INT_ENA
- RCAR_USB3_INT_ENA_VAL
- RCAR_USB3_INT_HSE_ENA
- RCAR_USB3_INT_PME_ENA
- RCAR_USB3_INT_XHC_ENA
- RCAR_USB3_LCLK
- RCAR_USB3_LCLK_ENA_VAL
- RCAR_USB3_RX_POL
- RCAR_USB3_RX_POL_VAL
- RCAR_USB3_TX_POL
- RCAR_USB3_TX_POL_VAL
- RCAR_USBCTR_DIRPD
- RCAR_USBCTR_PCIAHB_WIN1_1G
- RCAR_USBCTR_PCIAHB_WIN1_256M
- RCAR_USBCTR_PCIAHB_WIN1_2G
- RCAR_USBCTR_PCIAHB_WIN1_512M
- RCAR_USBCTR_PCIAHB_WIN1_MASK
- RCAR_USBCTR_PCIAHB_WIN2_EN
- RCAR_USBCTR_PCICLK_MASK
- RCAR_USBCTR_PLL_RST
- RCAR_USBCTR_REG
- RCAR_USBCTR_USBH_RST
- RCAR_VIN_NUM
- RCAR_XHCI_FIRMWARE_V2
- RCAR_XHCI_FIRMWARE_V3
- RCBABASE
- RCBLK
- RCBMAXAVG
- RCBMINAVG
- RCBR
- RCBV2_COM_CFG_TSO_MODE_REG
- RCBV2_COM_CFG_USER_REG
- RCBV2_RX_RING_INT_STS_REG
- RCBV2_TX_RING_INT_STS_REG
- RCB_CFG_BD_NUM_REG
- RCB_CFG_OVERTIME_INT_NUM_REG
- RCB_CFG_OVERTIME_REG
- RCB_CFG_PKTLINE_INT_NUM_REG
- RCB_CFG_PKTLINE_REG
- RCB_COMMON_REG_OFFSET
- RCB_COMM_BASE_TO_RING_BASE
- RCB_COM_AXI_ERR_STS
- RCB_COM_AXI_WR_ERR_INTMASK
- RCB_COM_CFG_ENDIAN_REG
- RCB_COM_CFG_FA_B
- RCB_COM_CFG_FA_REG
- RCB_COM_CFG_FNA_B
- RCB_COM_CFG_FNA_REG
- RCB_COM_CFG_INIT_FLAG_REG
- RCB_COM_CFG_PKT_REG
- RCB_COM_CFG_PKT_TC_BP_REG
- RCB_COM_CFG_PPE_TNL_CLKEN_REG
- RCB_COM_CFG_RINVLD_REG
- RCB_COM_CFG_SYS_FSH_REG
- RCB_COM_CHK_TX_FBD_NUM_REG
- RCB_COM_EBD_SRAM_ERR_REG
- RCB_COM_INTMASK_ECC_ERR_REG
- RCB_COM_INTMSK_TX_PKT_REG
- RCB_COM_INTSTS_ECC_ERR_REG
- RCB_COM_RCB_FBD_CRT_EN
- RCB_COM_RCB_RD_BD_BUSY
- RCB_COM_RINT_TX_PKT_REG
- RCB_COM_RXRING_ERR_REG
- RCB_COM_SF_CFG_BD_RINT_STS
- RCB_COM_SF_CFG_INTMASK_BD
- RCB_COM_SF_CFG_INTMASK_RING
- RCB_COM_SF_CFG_RING
- RCB_COM_SF_CFG_RING_STS
- RCB_COM_TSO_MODE_B
- RCB_COM_TXRING_ERR_REG
- RCB_COM_TX_FBD_ERR_REG
- RCB_DEFAULT_BUFFER_SIZE
- RCB_ECC_ERR_ADDR0_REG
- RCB_ECC_ERR_ADDR3_REG
- RCB_ECC_ERR_ADDR4_REG
- RCB_ECC_ERR_ADDR5_REG
- RCB_FLG_COAL_INT_ONLY
- RCB_FLG_EXT_RX_BD
- RCB_FLG_IEEE_SNAP_SUM
- RCB_FLG_IP_SUM
- RCB_FLG_NO_PSEUDO_HDR
- RCB_FLG_RNG_DISABLE
- RCB_FLG_TCP_UDP_SUM
- RCB_FLG_TX_HOST_RING
- RCB_FLG_VLAN_ASSIST
- RCB_INT_FLAG_MAX
- RCB_INT_FLAG_RX
- RCB_INT_FLAG_TX
- RCB_IRQ_INITED
- RCB_IRQ_NOT_INITED
- RCB_NOF_ALLOC_RX_BUFF_ONCE
- RCB_PORT_CFG_OVERTIME_REG
- RCB_PORT_INT_GAPTIME_REG
- RCB_REG_BASEADDR_H
- RCB_REG_BASEADDR_L
- RCB_REG_BD_LEN
- RCB_REG_BD_NUM
- RCB_REG_FBDNUM
- RCB_REG_HEAD
- RCB_REG_OFFSET
- RCB_REG_PKTLINE
- RCB_REG_PKTNUM_RECORD
- RCB_REG_TAIL
- RCB_RESET_TRY_TIMES
- RCB_RESET_WAIT_TIMES
- RCB_RING_ASID_REG
- RCB_RING_CFG_VF_NUM_REG
- RCB_RING_COULD_BE_RST
- RCB_RING_INTMSK_RXWL_REG
- RCB_RING_INTMSK_RX_OVERTIME_REG
- RCB_RING_INTMSK_TXWL_REG
- RCB_RING_INTMSK_TX_OVERTIME_REG
- RCB_RING_INTSTS_RX_OVERTIME_REG
- RCB_RING_INTSTS_RX_RING_REG
- RCB_RING_INTSTS_TX_OVERTIME_REG
- RCB_RING_INTSTS_TX_RING_REG
- RCB_RING_NAME_LEN
- RCB_RING_PREFETCH_EN_REG
- RCB_RING_RX_RING_BASEADDR_H_REG
- RCB_RING_RX_RING_BASEADDR_L_REG
- RCB_RING_RX_RING_BD_LEN_REG
- RCB_RING_RX_RING_BD_NUM_REG
- RCB_RING_RX_RING_FBDNUM_REG
- RCB_RING_RX_RING_HEAD_REG
- RCB_RING_RX_RING_PKTLINE_REG
- RCB_RING_RX_RING_PKTNUM_RECORD_REG
- RCB_RING_RX_RING_TAIL_REG
- RCB_RING_RX_VM_REG
- RCB_RING_T0_BE_RST
- RCB_RING_TX_RING_BASEADDR_H_REG
- RCB_RING_TX_RING_BASEADDR_L_REG
- RCB_RING_TX_RING_BD_LEN_REG
- RCB_RING_TX_RING_BD_NUM_REG
- RCB_RING_TX_RING_FBDNUM_REG
- RCB_RING_TX_RING_HEAD_REG
- RCB_RING_TX_RING_OFFSET_REG
- RCB_RING_TX_RING_PKTLINE_REG
- RCB_RING_TX_RING_PKTNUM_RECORD_REG
- RCB_RING_TX_RING_TAIL_REG
- RCB_RING_WRR_WEIGHT_REG
- RCB_SRAM_ECC_CHK0_REG
- RCB_SRAM_ECC_CHK1_REG
- RCB_SRAM_ECC_CHK2_REG
- RCB_SRAM_ECC_CHK3_REG
- RCB_SRAM_ECC_CHK4_REG
- RCB_SRAM_ECC_CHK5_REG
- RCB_SRAM_ECC_CHK_EN_REG
- RCC3EXITDONE_CPU_0__RCC3EXITDONE_MASK
- RCC3EXITDONE_CPU_0__RCC3EXITDONE__SHIFT
- RCC3EXITDONE_CPU_1__RCC3EXITDONE_MASK
- RCC3EXITDONE_CPU_1__RCC3EXITDONE__SHIFT
- RCC3ON_CPU_0__CK_RCC3ON_MASK
- RCC3ON_CPU_0__CK_RCC3ON__SHIFT
- RCC3ON_CPU_0__RCC3_AVG_DIV_MASK
- RCC3ON_CPU_0__RCC3_AVG_DIV__SHIFT
- RCC3ON_CPU_0__RCC3_AVG_EN_MASK
- RCC3ON_CPU_0__RCC3_AVG_EN__SHIFT
- RCC3ON_CPU_0__RCC3_DIDT_TIMER_MASK
- RCC3ON_CPU_0__RCC3_DIDT_TIMER__SHIFT
- RCC3ON_CPU_0__RCC3_PSM_CLK_DIV_MASK
- RCC3ON_CPU_0__RCC3_PSM_CLK_DIV__SHIFT
- RCC3ON_CPU_0__RCC3_PSM_EN_MASK
- RCC3ON_CPU_0__RCC3_PSM_EN__SHIFT
- RCC3ON_CPU_0__RCC3_WAKE_MIN_14_0_MASK
- RCC3ON_CPU_0__RCC3_WAKE_MIN_14_0__SHIFT
- RCC3ON_CPU_1__CK_RCC3ON_MASK
- RCC3ON_CPU_1__CK_RCC3ON__SHIFT
- RCC3ON_CPU_1__RCC3_AVG_DIV_MASK
- RCC3ON_CPU_1__RCC3_AVG_DIV__SHIFT
- RCC3ON_CPU_1__RCC3_AVG_EN_MASK
- RCC3ON_CPU_1__RCC3_AVG_EN__SHIFT
- RCC3ON_CPU_1__RCC3_DIDT_TIMER_MASK
- RCC3ON_CPU_1__RCC3_DIDT_TIMER__SHIFT
- RCC3ON_CPU_1__RCC3_PSM_CLK_DIV_MASK
- RCC3ON_CPU_1__RCC3_PSM_CLK_DIV__SHIFT
- RCC3ON_CPU_1__RCC3_PSM_EN_MASK
- RCC3ON_CPU_1__RCC3_PSM_EN__SHIFT
- RCC3ON_CPU_1__RCC3_WAKE_MIN_14_0_MASK
- RCC3ON_CPU_1__RCC3_WAKE_MIN_14_0__SHIFT
- RCC3_TARGETPSMREF_CPU_0__RCC3_TARGETPSMREF_MASK
- RCC3_TARGETPSMREF_CPU_0__RCC3_TARGETPSMREF__SHIFT
- RCC3_TARGETPSMREF_CPU_1__RCC3_TARGETPSMREF_MASK
- RCC3_TARGETPSMREF_CPU_1__RCC3_TARGETPSMREF__SHIFT
- RCC3_WAKEMIN_CPU_0__RCC3_WAKE_MIN_46_15_MASK
- RCC3_WAKEMIN_CPU_0__RCC3_WAKE_MIN_46_15__SHIFT
- RCC3_WAKEMIN_CPU_1__RCC3_WAKE_MIN_46_15_MASK
- RCC3_WAKEMIN_CPU_1__RCC3_WAKE_MIN_46_15__SHIFT
- RCCAONSEC
- RCCK0_AFESETTING
- RCCK0_AFESSTTING
- RCCK0_CCA
- RCCK0_CCA_CNT
- RCCK0_DEBUGPORT
- RCCK0_DSPPARAMETER1
- RCCK0_DSPPARAMETER2
- RCCK0_FACOUNTERLOWER
- RCCK0_FACOUNTERUPPER
- RCCK0_FALSEALARMREPORT
- RCCK0_RXAGC1
- RCCK0_RXAGC2
- RCCK0_RXHP
- RCCK0_RXREPORT
- RCCK0_SYSTEM
- RCCK0_TRSSIREPORT
- RCCK0_TXFILTER1
- RCCK0_TXFILTER2
- RCCK_RX
- RCCK_SYSTEM
- RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__MASK
- RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT
- RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__MASK
- RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT
- RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__MASK
- RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT
- RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__MASK
- RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT
- RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__MASK
- RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT
- RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__MASK
- RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT
- RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__MASK
- RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT
- RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__MASK
- RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT
- RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__MASK
- RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT
- RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__MASK
- RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__MASK
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__MASK
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__MASK
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__MASK
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__MASK
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__MASK
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__MASK
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__MASK
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__MASK
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__MASK
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__MASK
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__MASK
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__MASK
- RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT
- RCCP_F
- RCCP_S
- RCCP_V
- RCCR
- RCCR_DEM01
- RCCR_DEM23
- RCCR_DR0M
- RCCR_DR0QP_HIGH
- RCCR_DR0QP_LOW
- RCCR_DR0QP_MASK
- RCCR_DR0QP_MED
- RCCR_DR1M
- RCCR_DR1QP_HIGH
- RCCR_DR1QP_LOW
- RCCR_DR1QP_MASK
- RCCR_DR1QP_MED
- RCCR_DR2M
- RCCR_DR2QP_HIGH
- RCCR_DR2QP_LOW
- RCCR_DR2QP_MASK
- RCCR_DR2QP_MED
- RCCR_DR3M
- RCCR_DR3QP_HIGH
- RCCR_DR3QP_LOW
- RCCR_DR3QP_MASK
- RCCR_DR3QP_MED
- RCCR_EDM0
- RCCR_EDM1
- RCCR_EDM2
- RCCR_EDM3
- RCCR_EIE
- RCCR_ERAM_0KB
- RCCR_ERAM_10KB
- RCCR_ERAM_12KB
- RCCR_ERAM_2KB
- RCCR_ERAM_4KB
- RCCR_ERAM_6KB
- RCCR_ERAM_8KB
- RCCR_ERAM_MASK
- RCCR_SCD
- RCCR_TIME
- RCCR_TIMEP
- RCCR_TIMEP_MASK
- RCCR_TIME_MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__MASK
- RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT
- RCCTL
- RCCUNIT_CLKGATE_DIS
- RCC_ADCCKSELR
- RCC_AHB1ENR
- RCC_AHB2ENR
- RCC_AHB2ENSETR
- RCC_AHB3ENR
- RCC_AHB3ENSETR
- RCC_AHB4ENR
- RCC_AHB4ENSETR
- RCC_AHB5ENSETR
- RCC_AHB6ENSETR
- RCC_AHB6LPENSETR
- RCC_APB1DIVR
- RCC_APB1ENSETR
- RCC_APB1HENR
- RCC_APB1LENR
- RCC_APB2DIVR
- RCC_APB2ENR
- RCC_APB2ENSETR
- RCC_APB3DIVR
- RCC_APB3ENR
- RCC_APB3ENSETR
- RCC_APB4DIVR
- RCC_APB4ENR
- RCC_APB4ENSETR
- RCC_APB5DIVR
- RCC_APB5ENSETR
- RCC_ASSCKSELR
- RCC_AXIDIVR
- RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK
- RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__MASK
- RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT
- RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK
- RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__MASK
- RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT
- RCC_BDCR
- RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK
- RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT
- RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK
- RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT
- RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK
- RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT
- RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK
- RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT
- RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK
- RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT
- RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK
- RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT
- RCC_BIF_STRAP0__STRAP_CLK_PM_EN_PIN_MASK
- RCC_BIF_STRAP0__STRAP_CLK_PM_EN_PIN__SHIFT
- RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK
- RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT
- RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN_MASK
- RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN__SHIFT
- RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK
- RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT
- RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK
- RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT
- RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK
- RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT
- RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK
- RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT
- RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK
- RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT
- RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK
- RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT
- RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK
- RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT
- RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK
- RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT
- RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK
- RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT
- RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK
- RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
- RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK
- RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT
- RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK
- RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT
- RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK
- RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT
- RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK
- RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT
- RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK
- RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT
- RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK
- RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT
- RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK
- RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT
- RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK
- RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT
- RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK
- RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT
- RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK
- RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT
- RCC_BIF_STRAP1__STRAP_DLF_EN_MASK
- RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT
- RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK
- RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT
- RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK
- RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT
- RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK
- RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT
- RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK
- RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT
- RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK
- RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT
- RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK
- RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT
- RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK
- RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT
- RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK
- RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT
- RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK
- RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT
- RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK
- RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT
- RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK
- RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT
- RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK
- RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT
- RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK
- RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT
- RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK
- RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT
- RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK
- RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT
- RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK
- RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT
- RCC_BIF_STRAP1__STRAP_TRUE_PM_STATUS_EN_MASK
- RCC_BIF_STRAP1__STRAP_TRUE_PM_STATUS_EN__SHIFT
- RCC_BIF_STRAP1__WRITE_DISABLE_MASK
- RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT
- RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK
- RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT
- RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK
- RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT
- RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK
- RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT
- RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK
- RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT
- RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK
- RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT
- RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK
- RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT
- RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK
- RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT
- RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK
- RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT
- RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK
- RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT
- RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK
- RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT
- RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK
- RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT
- RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK
- RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT
- RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK
- RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT
- RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK
- RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT
- RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK
- RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT
- RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK
- RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT
- RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK
- RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT
- RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK
- RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT
- RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK
- RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT
- RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK
- RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT
- RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK
- RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT
- RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK
- RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT
- RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK
- RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT
- RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK
- RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT
- RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK
- RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT
- RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK
- RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT
- RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK
- RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT
- RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK
- RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT
- RCC_BIF_STRAP6__RESERVED_BIF_STRAP3_MASK
- RCC_BIF_STRAP6__RESERVED_BIF_STRAP3__SHIFT
- RCC_BUSNUM_CNTL1__ID_MASK_MASK
- RCC_BUSNUM_CNTL1__ID_MASK__MASK
- RCC_BUSNUM_CNTL1__ID_MASK__SHIFT
- RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK
- RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__MASK
- RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT
- RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK
- RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__MASK
- RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT
- RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK
- RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__MASK
- RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT
- RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK
- RCC_BUSNUM_CNTL2__HDPREG_CNTL__MASK
- RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT
- RCC_BUSNUM_LIST0__ID0_MASK
- RCC_BUSNUM_LIST0__ID0__MASK
- RCC_BUSNUM_LIST0__ID0__SHIFT
- RCC_BUSNUM_LIST0__ID1_MASK
- RCC_BUSNUM_LIST0__ID1__MASK
- RCC_BUSNUM_LIST0__ID1__SHIFT
- RCC_BUSNUM_LIST0__ID2_MASK
- RCC_BUSNUM_LIST0__ID2__MASK
- RCC_BUSNUM_LIST0__ID2__SHIFT
- RCC_BUSNUM_LIST0__ID3_MASK
- RCC_BUSNUM_LIST0__ID3__MASK
- RCC_BUSNUM_LIST0__ID3__SHIFT
- RCC_BUSNUM_LIST1__ID4_MASK
- RCC_BUSNUM_LIST1__ID4__MASK
- RCC_BUSNUM_LIST1__ID4__SHIFT
- RCC_BUSNUM_LIST1__ID5_MASK
- RCC_BUSNUM_LIST1__ID5__MASK
- RCC_BUSNUM_LIST1__ID5__SHIFT
- RCC_BUSNUM_LIST1__ID6_MASK
- RCC_BUSNUM_LIST1__ID6__MASK
- RCC_BUSNUM_LIST1__ID6__SHIFT
- RCC_BUSNUM_LIST1__ID7_MASK
- RCC_BUSNUM_LIST1__ID7__MASK
- RCC_BUSNUM_LIST1__ID7__SHIFT
- RCC_BUSY
- RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK
- RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__MASK
- RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT
- RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK
- RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__MASK
- RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT
- RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK
- RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__MASK
- RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT
- RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK
- RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__MASK
- RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT
- RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK
- RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__MASK
- RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT
- RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK
- RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__MASK
- RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT
- RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK
- RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__MASK
- RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT
- RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK
- RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__MASK
- RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT
- RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK
- RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__MASK
- RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT
- RCC_BUS_CNTL__PMI_BM_DIS_MASK
- RCC_BUS_CNTL__PMI_BM_DIS__MASK
- RCC_BUS_CNTL__PMI_BM_DIS__SHIFT
- RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK
- RCC_BUS_CNTL__PMI_IO_DIS_DN__MASK
- RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT
- RCC_BUS_CNTL__PMI_IO_DIS_MASK
- RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK
- RCC_BUS_CNTL__PMI_IO_DIS_UP__MASK
- RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT
- RCC_BUS_CNTL__PMI_IO_DIS__MASK
- RCC_BUS_CNTL__PMI_IO_DIS__SHIFT
- RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK
- RCC_BUS_CNTL__PMI_MEM_DIS_DN__MASK
- RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT
- RCC_BUS_CNTL__PMI_MEM_DIS_MASK
- RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK
- RCC_BUS_CNTL__PMI_MEM_DIS_UP__MASK
- RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT
- RCC_BUS_CNTL__PMI_MEM_DIS__MASK
- RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT
- RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK
- RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__MASK
- RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT
- RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK
- RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__MASK
- RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT
- RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK
- RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__MASK
- RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT
- RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK
- RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__MASK
- RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT
- RCC_CECCKSELR
- RCC_CFGR
- RCC_CLR
- RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK
- RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__MASK
- RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT
- RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK
- RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__MASK
- RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT
- RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK
- RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__MASK
- RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT
- RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK
- RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__MASK
- RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT
- RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK
- RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT
- RCC_CONFIG_APER_SIZE__APER_SIZE_MASK
- RCC_CONFIG_APER_SIZE__APER_SIZE__MASK
- RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT
- RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK
- RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__MASK
- RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT
- RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK
- RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__MASK
- RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT
- RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK
- RCC_CONFIG_CNTL__GRPH_ADRSEL__MASK
- RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT
- RCC_CONFIG_F0_BASE__F0_BASE_MASK
- RCC_CONFIG_F0_BASE__F0_BASE__MASK
- RCC_CONFIG_F0_BASE__F0_BASE__SHIFT
- RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__MASK
- RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK
- RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__MASK
- RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT
- RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_CONFIG_RESERVED__CONFIG_RESERVED__MASK
- RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_CPERCKSELR
- RCC_CR
- RCC_CSR
- RCC_D1CCIPR
- RCC_D1CFGR
- RCC_D2CCIP1R
- RCC_D2CCIP2R
- RCC_D2CFGR
- RCC_D3CCIPR
- RCC_D3CFGR
- RCC_DBGCFGR
- RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK
- RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT
- RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK
- RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT
- RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK
- RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT
- RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK
- RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT
- RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK
- RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT
- RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK
- RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT
- RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK
- RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT
- RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK
- RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT
- RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK
- RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT
- RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS_MASK
- RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT
- RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK
- RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT
- RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_MASK
- RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK
- RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT
- RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT
- RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK
- RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT
- RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_MASK
- RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK
- RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT
- RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT
- RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK
- RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT
- RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK
- RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT
- RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK
- RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT
- RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK
- RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT
- RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK
- RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT
- RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK
- RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT
- RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK
- RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT
- RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK
- RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT
- RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK
- RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT
- RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK
- RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT
- RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK
- RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT
- RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK
- RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK
- RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT
- RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK
- RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK
- RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT
- RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK
- RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT
- RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK
- RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT
- RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK
- RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT
- RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK
- RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT
- RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK
- RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT
- RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK
- RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT
- RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK
- RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT
- RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK
- RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT
- RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK
- RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT
- RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK
- RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT
- RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK
- RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT
- RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK
- RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT
- RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK
- RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT
- RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK
- RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT
- RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK
- RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT
- RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK
- RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT
- RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS_MASK
- RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT
- RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK
- RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT
- RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_MASK
- RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK
- RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT
- RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT
- RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK
- RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT
- RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_MASK
- RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK
- RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT
- RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT
- RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK
- RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT
- RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK
- RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT
- RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK
- RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT
- RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK
- RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT
- RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK
- RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT
- RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK
- RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT
- RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK
- RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT
- RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK
- RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT
- RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK
- RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT
- RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK
- RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT
- RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK
- RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT
- RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK
- RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK
- RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT
- RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK
- RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK
- RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT
- RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK
- RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT
- RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK
- RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT
- RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK
- RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT
- RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK
- RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT
- RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK
- RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT
- RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK
- RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT
- RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK
- RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT
- RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__MASK
- RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK
- RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT
- RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF10_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF10_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF11_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF11_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF12_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF12_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF13_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF13_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF14_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF14_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF15_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF15_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF16_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF16_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF16_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF16_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF16_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF17_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF17_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF17_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF17_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF17_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF18_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF18_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF18_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF18_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF18_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF19_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF19_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF19_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF19_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF19_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF20_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF20_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF20_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF20_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF20_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF21_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF21_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF21_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF21_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF21_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF22_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF22_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF22_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF22_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF22_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF23_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF23_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF23_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF23_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF23_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF24_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF24_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF24_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF24_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF24_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF24_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF24_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF24_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF24_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF24_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF24_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF24_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF24_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF24_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF24_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF24_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF24_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF24_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF25_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF25_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF25_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF25_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF25_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF25_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF25_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF25_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF25_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF25_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF25_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF25_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF25_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF25_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF25_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF25_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF25_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF25_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF26_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF26_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF26_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF26_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF26_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF26_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF26_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF26_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF26_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF26_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF26_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF26_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF26_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF26_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF26_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF26_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF26_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF26_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF27_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF27_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF27_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF27_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF27_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF27_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF27_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF27_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF27_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF27_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF27_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF27_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF27_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF27_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF27_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF27_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF27_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF27_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF28_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF28_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF28_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF28_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF28_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF28_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF28_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF28_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF28_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF28_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF28_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF28_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF28_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF28_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF28_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF28_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF28_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF28_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF29_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF29_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF29_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF29_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF29_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF29_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF29_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF29_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF29_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF29_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF29_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF29_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF29_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF29_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF29_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF29_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF29_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF29_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF30_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF30_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF30_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF30_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF30_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF30_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF30_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF30_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF30_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF30_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF30_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF30_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF30_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF30_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF30_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF30_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF30_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF30_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF8_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF8_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK
- RCC_DEV0_EPF0_VF9_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK
- RCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT
- RCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_DEV0_EPF0_VF9_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__MASK
- RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP7__STRAP_TPH_EN_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP7__STRAP_TPH_EN_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F1__SHIFT
- RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F1_MASK
- RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F1__SHIFT
- RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EN_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EN_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP5__STRAP_AUX_CURRENT_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP5__STRAP_AUX_CURRENT_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP5__STRAP_SATAIDP_EN_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP5__STRAP_SATAIDP_EN_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP5__STRAP_USB_DBESELD_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP5__STRAP_USB_DBESELD_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP5__STRAP_USB_DBESEL_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP5__STRAP_USB_DBESEL_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP6__STRAP_APER1_EN_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP6__STRAP_APER1_EN_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP6__STRAP_APER1_EN_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F2__MASK
- RCC_DEV0_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP7__STRAP_ROM_APER_EN_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP7__STRAP_ROM_APER_EN_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP7__STRAP_TPH_EN_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP7__STRAP_TPH_EN_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F2__SHIFT
- RCC_DEV0_EPF2_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F2_MASK
- RCC_DEV0_EPF2_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F2__SHIFT
- RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EN_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EN_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP5__STRAP_AUX_CURRENT_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP5__STRAP_AUX_CURRENT_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESELD_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESELD_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESELD_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESEL_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESEL_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESEL_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F3__MASK
- RCC_DEV0_EPF3_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP6__STRAP_APER1_EN_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP6__STRAP_APER1_EN_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP7__STRAP_TPH_EN_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP7__STRAP_TPH_EN_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F3__SHIFT
- RCC_DEV0_EPF3_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F3_MASK
- RCC_DEV0_EPF3_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F3__SHIFT
- RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP0__STRAP_DEVICE_ID_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP0__STRAP_DEVICE_ID_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP0__STRAP_DEVICE_ID_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP0__STRAP_MINOR_REV_ID_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP0__STRAP_MINOR_REV_ID_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP0__STRAP_MINOR_REV_ID_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP2__STRAP_PASID_EN_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP2__STRAP_PASID_EN_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP2__STRAP_VC_EN_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP2__STRAP_VC_EN_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP2__STRAP_VC_EN_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP3__STRAP_MSIX_EN_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP3__STRAP_MSIX_EN_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP3__STRAP_MSIX_EN_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP3__STRAP_MSI_EN_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP3__STRAP_MSI_EN_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP3__STRAP_MSI_EN_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP3__STRAP_SUBSYS_ID_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP3__STRAP_SUBSYS_ID_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP3__STRAP_SUBSYS_ID_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_EN_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_EN_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_EN_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP4__STRAP_FLR_EN_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP4__STRAP_FLR_EN_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP4__STRAP_FLR_EN_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP4__STRAP_PME_SUPPORT_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP4__STRAP_PME_SUPPORT_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP4__STRAP_PME_SUPPORT_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESELD_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESELD_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESELD_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESEL_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESEL_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESEL_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP6__STRAP_APER0_EN_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP6__STRAP_APER0_EN_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP6__STRAP_APER0_EN_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP6__STRAP_APER1_EN_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP6__STRAP_APER1_EN_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP6__STRAP_APER2_EN_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP6__STRAP_APER2_EN_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F4__MASK
- RCC_DEV0_EPF4_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP7__STRAP_TPH_EN_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP7__STRAP_TPH_EN_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F4__SHIFT
- RCC_DEV0_EPF4_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F4_MASK
- RCC_DEV0_EPF4_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F4__SHIFT
- RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP0__STRAP_DEVICE_ID_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP0__STRAP_DEVICE_ID_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP0__STRAP_DEVICE_ID_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP0__STRAP_MINOR_REV_ID_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP0__STRAP_MINOR_REV_ID_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP0__STRAP_MINOR_REV_ID_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP2__STRAP_PASID_EN_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP2__STRAP_PASID_EN_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP2__STRAP_VC_EN_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP2__STRAP_VC_EN_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP2__STRAP_VC_EN_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP3__STRAP_MSIX_EN_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP3__STRAP_MSIX_EN_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP3__STRAP_MSIX_EN_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP3__STRAP_MSI_EN_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP3__STRAP_MSI_EN_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP3__STRAP_MSI_EN_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP3__STRAP_SUBSYS_ID_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP3__STRAP_SUBSYS_ID_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP3__STRAP_SUBSYS_ID_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP5__STRAP_USB_DBESELD_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP5__STRAP_USB_DBESELD_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP5__STRAP_USB_DBESEL_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP5__STRAP_USB_DBESEL_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP6__STRAP_APER0_EN_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP6__STRAP_APER0_EN_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP6__STRAP_APER0_EN_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP6__STRAP_APER1_EN_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP6__STRAP_APER1_EN_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP6__STRAP_APER2_EN_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP6__STRAP_APER2_EN_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F5__MASK
- RCC_DEV0_EPF5_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F5__SHIFT
- RCC_DEV0_EPF5_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV0_F5_MASK
- RCC_DEV0_EPF5_STRAP7__STRAP_MSIX_TABLE_SIZE_DEV0_F5__SHIFT
- RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP0__STRAP_DEVICE_ID_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP0__STRAP_DEVICE_ID_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP0__STRAP_DEVICE_ID_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP0__STRAP_MINOR_REV_ID_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP0__STRAP_MINOR_REV_ID_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP0__STRAP_MINOR_REV_ID_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP2__STRAP_PASID_EN_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP2__STRAP_PASID_EN_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP2__STRAP_VC_EN_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP2__STRAP_VC_EN_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP2__STRAP_VC_EN_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP3__STRAP_MSIX_EN_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP3__STRAP_MSIX_EN_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP3__STRAP_MSIX_EN_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP3__STRAP_MSI_EN_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP3__STRAP_MSI_EN_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP3__STRAP_MSI_EN_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP3__STRAP_SUBSYS_ID_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP3__STRAP_SUBSYS_ID_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP3__STRAP_SUBSYS_ID_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_EN_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_EN_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_EN_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP4__STRAP_FLR_EN_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP4__STRAP_FLR_EN_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP4__STRAP_FLR_EN_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP4__STRAP_PME_SUPPORT_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP4__STRAP_PME_SUPPORT_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP4__STRAP_PME_SUPPORT_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP6__STRAP_APER0_EN_DEV0_F6_MASK
- RCC_DEV0_EPF6_STRAP6__STRAP_APER0_EN_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP6__STRAP_APER0_EN_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP6__STRAP_APER1_EN_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP6__STRAP_APER1_EN_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP6__STRAP_APER2_EN_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP6__STRAP_APER2_EN_DEV0_F6__SHIFT
- RCC_DEV0_EPF6_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F6__MASK
- RCC_DEV0_EPF6_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F6__SHIFT
- RCC_DEV0_EPF7_STRAP0__STRAP_D1_SUPPORT_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP0__STRAP_D1_SUPPORT_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP0__STRAP_D2_SUPPORT_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP0__STRAP_D2_SUPPORT_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP0__STRAP_DEVICE_ID_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP0__STRAP_DEVICE_ID_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP0__STRAP_FUNC_EN_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP0__STRAP_FUNC_EN_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP0__STRAP_MINOR_REV_ID_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP0__STRAP_MINOR_REV_ID_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP2__STRAP_ACS_EN_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP2__STRAP_ACS_EN_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP2__STRAP_AER_EN_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP2__STRAP_AER_EN_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP2__STRAP_DPA_EN_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP2__STRAP_DPA_EN_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP2__STRAP_VC_EN_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP2__STRAP_VC_EN_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP3__STRAP_MSIX_EN_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP3__STRAP_MSIX_EN_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP3__STRAP_MSI_EN_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP3__STRAP_MSI_EN_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP3__STRAP_PMC_DSI_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP3__STRAP_PMC_DSI_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP3__STRAP_PWR_EN_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP3__STRAP_PWR_EN_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP3__STRAP_SUBSYS_ID_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP3__STRAP_SUBSYS_ID_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_EN_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_EN_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP4__STRAP_FLR_EN_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP4__STRAP_FLR_EN_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP4__STRAP_PME_SUPPORT_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP4__STRAP_PME_SUPPORT_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP6__STRAP_APER0_EN_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP6__STRAP_APER0_EN_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP6__STRAP_APER1_EN_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP6__STRAP_APER1_EN_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP6__STRAP_APER2_EN_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP6__STRAP_APER2_EN_DEV0_F7__SHIFT
- RCC_DEV0_EPF7_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F7__MASK
- RCC_DEV0_EPF7_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F7__SHIFT
- RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK
- RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__MASK
- RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT
- RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK
- RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__MASK
- RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT
- RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK
- RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__MASK
- RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK
- RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__MASK
- RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK
- RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__MASK
- RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK
- RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__MASK
- RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK
- RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__MASK
- RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK
- RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__MASK
- RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK
- RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__MASK
- RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK
- RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__MASK
- RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK
- RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__MASK
- RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK
- RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__MASK
- RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK
- RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__MASK
- RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK
- RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__MASK
- RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK
- RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__MASK
- RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK
- RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__MASK
- RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK
- RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__MASK
- RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK
- RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__MASK
- RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK
- RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__MASK
- RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0_MASK
- RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__MASK
- RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK
- RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__MASK
- RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK
- RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__MASK
- RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK
- RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__MASK
- RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK
- RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__MASK
- RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK
- RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__MASK
- RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK
- RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK
- RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK
- RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__MASK
- RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK
- RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK
- RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK
- RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__MASK
- RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK
- RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__MASK
- RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK
- RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__MASK
- RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK
- RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__MASK
- RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK
- RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__MASK
- RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK
- RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__MASK
- RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK
- RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__MASK
- RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK
- RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK
- RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__MASK
- RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK
- RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__MASK
- RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK
- RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__MASK
- RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK
- RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__MASK
- RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK
- RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__MASK
- RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK
- RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__MASK
- RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK
- RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK
- RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK
- RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__MASK
- RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK
- RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK
- RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK
- RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK
- RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK
- RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK
- RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__MASK
- RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK
- RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK
- RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__MASK
- RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK
- RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__MASK
- RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK
- RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__MASK
- RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK
- RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__MASK
- RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK
- RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__MASK
- RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK
- RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK
- RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK
- RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK
- RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK
- RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT
- RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK
- RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT
- RCC_DEV1_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP0__STRAP_DEVICE_ID_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP0__STRAP_DEVICE_ID_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP0__STRAP_DEVICE_ID_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP0__STRAP_FUNC_EN_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP0__STRAP_FUNC_EN_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP0__STRAP_FUNC_EN_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP2__STRAP_ACS_EN_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP2__STRAP_ACS_EN_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP2__STRAP_ACS_EN_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP2__STRAP_AER_EN_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP2__STRAP_AER_EN_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP2__STRAP_AER_EN_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP2__STRAP_ARI_EN_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP2__STRAP_ARI_EN_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP2__STRAP_ARI_EN_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP2__STRAP_DPA_EN_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP2__STRAP_DPA_EN_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP2__STRAP_DPA_EN_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP2__STRAP_PASID_EN_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP2__STRAP_PASID_EN_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP2__STRAP_VC_EN_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP2__STRAP_VC_EN_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP2__STRAP_VC_EN_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP3__STRAP_MSIX_EN_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP3__STRAP_MSIX_EN_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP3__STRAP_MSIX_EN_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP3__STRAP_MSI_EN_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP3__STRAP_MSI_EN_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP3__STRAP_MSI_EN_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP3__STRAP_PMC_DSI_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP3__STRAP_PMC_DSI_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP3__STRAP_PMC_DSI_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP3__STRAP_PWR_EN_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP3__STRAP_PWR_EN_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP3__STRAP_PWR_EN_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP4__STRAP_FLR_EN_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP4__STRAP_FLR_EN_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP4__STRAP_FLR_EN_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP5__STRAP_SATA_DID_RAID_EN_0_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP5__STRAP_SATA_DID_RAID_EN_0_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP5__STRAP_SATA_DID_RAID_EN_1_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP5__STRAP_SATA_DID_RAID_EN_1_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP6__STRAP_APER0_EN_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP6__STRAP_APER0_EN_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP6__STRAP_APER0_EN_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F0__MASK
- RCC_DEV1_EPF0_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP7__STRAP_TPH_EN_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP7__STRAP_TPH_EN_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV1_F0__SHIFT
- RCC_DEV1_EPF0_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV1_F0_MASK
- RCC_DEV1_EPF0_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV1_F0__SHIFT
- RCC_DEV1_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP0__STRAP_DEVICE_ID_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP0__STRAP_DEVICE_ID_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP0__STRAP_FUNC_EN_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP0__STRAP_FUNC_EN_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP2__STRAP_ACS_EN_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP2__STRAP_ACS_EN_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP2__STRAP_AER_EN_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP2__STRAP_AER_EN_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP2__STRAP_DPA_EN_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP2__STRAP_DPA_EN_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP2__STRAP_VC_EN_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP2__STRAP_VC_EN_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP3__STRAP_MSIX_EN_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP3__STRAP_MSIX_EN_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP3__STRAP_MSI_EN_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP3__STRAP_MSI_EN_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP3__STRAP_PMC_DSI_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP3__STRAP_PMC_DSI_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP3__STRAP_PWR_EN_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP3__STRAP_PWR_EN_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP4__STRAP_FLR_EN_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP4__STRAP_FLR_EN_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP6__STRAP_APER0_EN_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP6__STRAP_APER0_EN_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP6__STRAP_APER1_EN_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP6__STRAP_APER1_EN_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP6__STRAP_APER2_EN_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP6__STRAP_APER2_EN_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP6__STRAP_APER3_EN_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP6__STRAP_APER3_EN_DEV1_F1__SHIFT
- RCC_DEV1_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F1__MASK
- RCC_DEV1_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F1__SHIFT
- RCC_DEV1_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP0__STRAP_DEVICE_ID_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP0__STRAP_DEVICE_ID_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP0__STRAP_FUNC_EN_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP0__STRAP_FUNC_EN_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP2__STRAP_ACS_EN_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP2__STRAP_ACS_EN_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP2__STRAP_AER_EN_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP2__STRAP_AER_EN_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP2__STRAP_DPA_EN_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP2__STRAP_DPA_EN_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP2__STRAP_VC_EN_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP2__STRAP_VC_EN_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP3__STRAP_MSIX_EN_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP3__STRAP_MSIX_EN_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP3__STRAP_MSI_EN_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP3__STRAP_MSI_EN_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP3__STRAP_PMC_DSI_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP3__STRAP_PMC_DSI_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP3__STRAP_PWR_EN_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP3__STRAP_PWR_EN_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP4__STRAP_FLR_EN_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP4__STRAP_FLR_EN_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP6__STRAP_APER0_EN_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP6__STRAP_APER0_EN_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP6__STRAP_APER1_EN_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP6__STRAP_APER1_EN_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP6__STRAP_APER2_EN_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP6__STRAP_APER2_EN_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP6__STRAP_APER3_EN_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP6__STRAP_APER3_EN_DEV1_F2__SHIFT
- RCC_DEV1_EPF2_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F2__MASK
- RCC_DEV1_EPF2_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F2__SHIFT
- RCC_DEV1_PORT_STRAP0__STRAP_ACS_EN_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP0__STRAP_ACS_EN_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP0__STRAP_ACS_EN_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP0__STRAP_AER_EN_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP0__STRAP_AER_EN_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP0__STRAP_AER_EN_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP0__STRAP_ARI_EN_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP0__STRAP_ARI_EN_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP0__STRAP_ARI_EN_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV1_MASK
- RCC_DEV1_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV1__MASK
- RCC_DEV1_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1_MASK
- RCC_DEV1_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1__MASK
- RCC_DEV1_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP2__STRAP_DSN_EN_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP2__STRAP_DSN_EN_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP2__STRAP_DSN_EN_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV1_MASK
- RCC_DEV1_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV1__MASK
- RCC_DEV1_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP2__STRAP_ECN1P1_EN_DEV1_MASK
- RCC_DEV1_PORT_STRAP2__STRAP_ECN1P1_EN_DEV1__MASK
- RCC_DEV1_PORT_STRAP2__STRAP_ECN1P1_EN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV1_MASK
- RCC_DEV1_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV1__MASK
- RCC_DEV1_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV1_MASK
- RCC_DEV1_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV1__MASK
- RCC_DEV1_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV1_MASK
- RCC_DEV1_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV1__MASK
- RCC_DEV1_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV1_MASK
- RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV1__MASK
- RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV1_MASK
- RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV1__MASK
- RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV1_MASK
- RCC_DEV1_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV1__MASK
- RCC_DEV1_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP2__STRAP_GEN2_EN_DEV1_MASK
- RCC_DEV1_PORT_STRAP2__STRAP_GEN2_EN_DEV1__MASK
- RCC_DEV1_PORT_STRAP2__STRAP_GEN2_EN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV1_MASK
- RCC_DEV1_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV1__MASK
- RCC_DEV1_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV1_MASK
- RCC_DEV1_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV1__MASK
- RCC_DEV1_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV1_MASK
- RCC_DEV1_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV1__MASK
- RCC_DEV1_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV1_MASK
- RCC_DEV1_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV1__MASK
- RCC_DEV1_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV1_MASK
- RCC_DEV1_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV1__MASK
- RCC_DEV1_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV1_MASK
- RCC_DEV1_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV1__MASK
- RCC_DEV1_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV1_MASK
- RCC_DEV1_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV1__MASK
- RCC_DEV1_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1_MASK
- RCC_DEV1_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1__MASK
- RCC_DEV1_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DEV1_MASK
- RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DEV1__MASK
- RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV1_MASK
- RCC_DEV1_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV1__MASK
- RCC_DEV1_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP3__STRAP_MSI_EN_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP3__STRAP_MSI_EN_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP3__STRAP_MSI_EN_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV1_MASK
- RCC_DEV1_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV1__MASK
- RCC_DEV1_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV1_MASK
- RCC_DEV1_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV1__MASK
- RCC_DEV1_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1_MASK
- RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1__MASK
- RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1_MASK
- RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1__MASK
- RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1_MASK
- RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1__MASK
- RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1_MASK
- RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1__MASK
- RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DEV1_MASK
- RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DEV1__MASK
- RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV1_MASK
- RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV1__MASK
- RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV1_MASK
- RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV1__MASK
- RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV1_MASK
- RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV1__MASK
- RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV1_MASK
- RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV1__MASK
- RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV1_MASK
- RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV1__MASK
- RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV1_MASK
- RCC_DEV1_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV1_MASK
- RCC_DEV1_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV1__MASK
- RCC_DEV1_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV1_MASK
- RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV1__MASK
- RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV1_MASK
- RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV1__MASK
- RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1_MASK
- RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1__MASK
- RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP5__STRAP_SSID_EN_DEV1_MASK
- RCC_DEV1_PORT_STRAP5__STRAP_SSID_EN_DEV1__MASK
- RCC_DEV1_PORT_STRAP5__STRAP_SSID_EN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DEV1_MASK
- RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DEV1__MASK
- RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP5__STRAP_VC_EN_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP5__STRAP_VC_EN_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP5__STRAP_VC_EN_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV1_MASK
- RCC_DEV1_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV1_MASK
- RCC_DEV1_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV1_MASK
- RCC_DEV1_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV1__MASK
- RCC_DEV1_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV1_MASK
- RCC_DEV1_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV1_MASK
- RCC_DEV1_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV1_MASK
- RCC_DEV1_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV1_MASK
- RCC_DEV1_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV1_MASK
- RCC_DEV1_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1_MASK
- RCC_DEV1_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1__MASK
- RCC_DEV1_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV1_MASK
- RCC_DEV1_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP7__STRAP_DN_DEVNUM_DEV1_MASK
- RCC_DEV1_PORT_STRAP7__STRAP_DN_DEVNUM_DEV1__MASK
- RCC_DEV1_PORT_STRAP7__STRAP_DN_DEVNUM_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP7__STRAP_DN_FUNCID_DEV1_MASK
- RCC_DEV1_PORT_STRAP7__STRAP_DN_FUNCID_DEV1__MASK
- RCC_DEV1_PORT_STRAP7__STRAP_DN_FUNCID_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV1_MASK
- RCC_DEV1_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV1__MASK
- RCC_DEV1_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP7__STRAP_PORT_NUMBER_DEV1_MASK
- RCC_DEV1_PORT_STRAP7__STRAP_PORT_NUMBER_DEV1__MASK
- RCC_DEV1_PORT_STRAP7__STRAP_PORT_NUMBER_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP7__STRAP_RP_BUSNUM_DEV1_MASK
- RCC_DEV1_PORT_STRAP7__STRAP_RP_BUSNUM_DEV1__MASK
- RCC_DEV1_PORT_STRAP7__STRAP_RP_BUSNUM_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV1_MASK
- RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV1_MASK
- RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV1_MASK
- RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV1_MASK
- RCC_DEV1_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV1_MASK
- RCC_DEV1_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV1__SHIFT
- RCC_DEV1_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV1_MASK
- RCC_DEV1_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV1__SHIFT
- RCC_DEV2_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP0__STRAP_DEVICE_ID_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP0__STRAP_DEVICE_ID_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP0__STRAP_FUNC_EN_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP0__STRAP_FUNC_EN_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP2__STRAP_ACS_EN_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP2__STRAP_ACS_EN_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP2__STRAP_AER_EN_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP2__STRAP_AER_EN_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP2__STRAP_ARI_EN_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP2__STRAP_ARI_EN_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP2__STRAP_DPA_EN_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP2__STRAP_DPA_EN_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP2__STRAP_PASID_EN_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP2__STRAP_PASID_EN_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP2__STRAP_VC_EN_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP2__STRAP_VC_EN_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP3__STRAP_MSIX_EN_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP3__STRAP_MSIX_EN_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP3__STRAP_MSI_EN_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP3__STRAP_MSI_EN_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP3__STRAP_PMC_DSI_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP3__STRAP_PMC_DSI_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP3__STRAP_PWR_EN_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP3__STRAP_PWR_EN_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP4__STRAP_FLR_EN_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP4__STRAP_FLR_EN_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP5__STRAP_SATA_DID_RAID_EN_0_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP5__STRAP_SATA_DID_RAID_EN_0_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP5__STRAP_SATA_DID_RAID_EN_1_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP5__STRAP_SATA_DID_RAID_EN_1_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP6__STRAP_APER0_EN_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP6__STRAP_APER0_EN_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP7__STRAP_TPH_EN_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP7__STRAP_TPH_EN_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV2_F0__SHIFT
- RCC_DEV2_EPF0_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV2_F0_MASK
- RCC_DEV2_EPF0_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV2_F0__SHIFT
- RCC_DEV2_PORT_STRAP0__STRAP_ACS_EN_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP0__STRAP_ACS_EN_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP0__STRAP_AER_EN_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP0__STRAP_AER_EN_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP0__STRAP_ARI_EN_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP0__STRAP_ARI_EN_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV2_MASK
- RCC_DEV2_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV2_MASK
- RCC_DEV2_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP2__STRAP_DSN_EN_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP2__STRAP_DSN_EN_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV2_MASK
- RCC_DEV2_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP2__STRAP_ECN1P1_EN_DEV2_MASK
- RCC_DEV2_PORT_STRAP2__STRAP_ECN1P1_EN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV2_MASK
- RCC_DEV2_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV2_MASK
- RCC_DEV2_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV2_MASK
- RCC_DEV2_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV2_MASK
- RCC_DEV2_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV2_MASK
- RCC_DEV2_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV2_MASK
- RCC_DEV2_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP2__STRAP_GEN2_EN_DEV2_MASK
- RCC_DEV2_PORT_STRAP2__STRAP_GEN2_EN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV2_MASK
- RCC_DEV2_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV2_MASK
- RCC_DEV2_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV2_MASK
- RCC_DEV2_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV2_MASK
- RCC_DEV2_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV2_MASK
- RCC_DEV2_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV2_MASK
- RCC_DEV2_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV2_MASK
- RCC_DEV2_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV2_MASK
- RCC_DEV2_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP3__STRAP_LTR_EN_DEV2_MASK
- RCC_DEV2_PORT_STRAP3__STRAP_LTR_EN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP3__STRAP_LTR_EN_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP3__STRAP_LTR_EN_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV2_MASK
- RCC_DEV2_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP3__STRAP_MSI_EN_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP3__STRAP_MSI_EN_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV2_MASK
- RCC_DEV2_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV2_MASK
- RCC_DEV2_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV2_MASK
- RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV2_MASK
- RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV2_MASK
- RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV2_MASK
- RCC_DEV2_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP3__STRAP_PM_SUPPORT_DEV2_MASK
- RCC_DEV2_PORT_STRAP3__STRAP_PM_SUPPORT_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV2_MASK
- RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV2_MASK
- RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV2_MASK
- RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV2_MASK
- RCC_DEV2_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV2_MASK
- RCC_DEV2_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV2_MASK
- RCC_DEV2_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV2_MASK
- RCC_DEV2_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV2_MASK
- RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV2_MASK
- RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV2_MASK
- RCC_DEV2_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP5__STRAP_SSID_EN_DEV2_MASK
- RCC_DEV2_PORT_STRAP5__STRAP_SSID_EN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP5__STRAP_TwoVC_EN_DEV2_MASK
- RCC_DEV2_PORT_STRAP5__STRAP_TwoVC_EN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP5__STRAP_VC_EN_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP5__STRAP_VC_EN_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV2_MASK
- RCC_DEV2_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV2_MASK
- RCC_DEV2_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV2_MASK
- RCC_DEV2_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV2_MASK
- RCC_DEV2_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV2_MASK
- RCC_DEV2_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV2_MASK
- RCC_DEV2_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV2_MASK
- RCC_DEV2_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV2_MASK
- RCC_DEV2_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV2_MASK
- RCC_DEV2_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV2_MASK
- RCC_DEV2_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP7__STRAP_DN_DEVNUM_DEV2_MASK
- RCC_DEV2_PORT_STRAP7__STRAP_DN_DEVNUM_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP7__STRAP_DN_FUNCID_DEV2_MASK
- RCC_DEV2_PORT_STRAP7__STRAP_DN_FUNCID_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV2_MASK
- RCC_DEV2_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP7__STRAP_PORT_NUMBER_DEV2_MASK
- RCC_DEV2_PORT_STRAP7__STRAP_PORT_NUMBER_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP7__STRAP_RP_BUSNUM_DEV2_MASK
- RCC_DEV2_PORT_STRAP7__STRAP_RP_BUSNUM_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV2_MASK
- RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV2_MASK
- RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV2_MASK
- RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV2_MASK
- RCC_DEV2_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV2_MASK
- RCC_DEV2_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV2__SHIFT
- RCC_DEV2_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV2_MASK
- RCC_DEV2_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV2__SHIFT
- RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK
- RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__MASK
- RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT
- RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK
- RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__MASK
- RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT
- RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK
- RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__MASK
- RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT
- RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK
- RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__MASK
- RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT
- RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK
- RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__MASK
- RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT
- RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK
- RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__MASK
- RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT
- RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK
- RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__MASK
- RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT
- RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK
- RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__MASK
- RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT
- RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__MASK
- RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_DSICKSELR
- RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK
- RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT
- RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK
- RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT
- RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
- RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
- RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
- RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
- RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
- RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
- RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
- RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
- RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK
- RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT
- RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
- RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
- RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
- RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
- RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK
- RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT
- RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
- RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
- RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK
- RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT
- RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK
- RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT
- RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
- RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
- RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK
- RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT
- RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK
- RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT
- RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK
- RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT
- RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
- RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
- RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
- RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
- RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
- RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
- RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
- RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
- RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK
- RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT
- RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
- RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
- RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
- RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
- RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK
- RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT
- RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
- RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
- RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK
- RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT
- RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK
- RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT
- RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
- RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
- RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK
- RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT
- RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK
- RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT
- RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK
- RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT
- RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
- RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
- RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
- RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
- RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
- RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
- RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
- RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
- RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK
- RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT
- RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
- RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
- RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
- RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
- RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
- RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
- RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK
- RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT
- RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK
- RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT
- RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
- RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
- RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK
- RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT
- RCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK
- RCC_DWNP_DEV1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT
- RCC_DWNP_DEV1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK
- RCC_DWNP_DEV1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT
- RCC_DWNP_DEV1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
- RCC_DWNP_DEV1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
- RCC_DWNP_DEV1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
- RCC_DWNP_DEV1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
- RCC_DWNP_DEV1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
- RCC_DWNP_DEV1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
- RCC_DWNP_DEV1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
- RCC_DWNP_DEV1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
- RCC_DWNP_DEV1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK
- RCC_DWNP_DEV1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT
- RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
- RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
- RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
- RCC_DWNP_DEV1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
- RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
- RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
- RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK
- RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT
- RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK
- RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT
- RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
- RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
- RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK
- RCC_DWNP_DEV1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT
- RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK
- RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT
- RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK
- RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT
- RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK
- RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT
- RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK
- RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT
- RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK
- RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT
- RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK
- RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT
- RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK
- RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT
- RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK
- RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT
- RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK
- RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT
- RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK
- RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT
- RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED_MASK
- RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT
- RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK
- RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT
- RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK
- RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT
- RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK
- RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT
- RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK
- RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT
- RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK
- RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT
- RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK
- RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT
- RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK
- RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT
- RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK
- RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT
- RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK
- RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT
- RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK
- RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT
- RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK
- RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT
- RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK
- RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT
- RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK
- RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT
- RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK
- RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT
- RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK
- RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT
- RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK
- RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT
- RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK
- RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT
- RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK
- RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT
- RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK
- RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT
- RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK
- RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT
- RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK
- RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT
- RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK
- RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT
- RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK
- RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT
- RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK
- RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT
- RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK
- RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT
- RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK
- RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT
- RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK
- RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT
- RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK
- RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT
- RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK
- RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT
- RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK
- RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT
- RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK
- RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT
- RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK
- RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT
- RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK
- RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT
- RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK
- RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT
- RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK
- RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT
- RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK
- RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT
- RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED_MASK
- RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT
- RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK
- RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT
- RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK
- RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT
- RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK
- RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT
- RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK
- RCC_DWN_DEV1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT
- RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK
- RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT
- RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK
- RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT
- RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK
- RCC_DWN_DEV1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT
- RCC_DWN_DEV1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK
- RCC_DWN_DEV1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT
- RCC_DWN_DEV1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK
- RCC_DWN_DEV1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT
- RCC_DWN_DEV1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK
- RCC_DWN_DEV1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT
- RCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK
- RCC_DWN_DEV1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT
- RCC_DWN_DEV1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK
- RCC_DWN_DEV1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT
- RCC_DWN_DEV1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK
- RCC_DWN_DEV1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT
- RCC_DWN_DEV1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK
- RCC_DWN_DEV1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT
- RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK
- RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK
- RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK
- RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK
- RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK
- RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK
- RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK
- RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK
- RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK
- RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
- RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK
- RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK
- RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK
- RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK
- RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK
- RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK
- RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK
- RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
- RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
- RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
- RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK
- RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK
- RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK
- RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK
- RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK
- RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK
- RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK
- RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
- RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK
- RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK
- RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK
- RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK
- RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK
- RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK
- RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK
- RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK
- RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK
- RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK
- RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK
- RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK
- RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
- RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
- RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK
- RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK
- RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK
- RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK
- RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK
- RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
- RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK
- RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK
- RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK
- RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
- RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK
- RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK
- RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK
- RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK
- RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK
- RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK
- RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK
- RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK
- RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK
- RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK
- RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK
- RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK
- RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK
- RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK
- RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK
- RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK
- RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK
- RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK
- RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK
- RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK
- RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK
- RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT
- RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK
- RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT
- RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK
- RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK
- RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK
- RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK
- RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK
- RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK
- RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK
- RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK
- RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK
- RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
- RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK
- RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK
- RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK
- RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK
- RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK
- RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK
- RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK
- RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
- RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
- RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
- RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK
- RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK
- RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK
- RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK
- RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK
- RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK
- RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK
- RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
- RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK
- RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK
- RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK
- RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK
- RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK
- RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK
- RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK
- RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK
- RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK
- RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK
- RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK
- RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK
- RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
- RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
- RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK
- RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK
- RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK
- RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK
- RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK
- RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
- RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK
- RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK
- RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK
- RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
- RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK
- RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK
- RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK
- RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK
- RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK
- RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK
- RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK
- RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK
- RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK
- RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK
- RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK
- RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK
- RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK
- RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK
- RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK
- RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK
- RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK
- RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK
- RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK
- RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK
- RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK
- RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT
- RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK
- RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT
- RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK
- RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK
- RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK
- RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK
- RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK
- RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK
- RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK
- RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK
- RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
- RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK
- RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK
- RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK
- RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK
- RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK
- RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK
- RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK
- RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
- RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
- RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
- RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK
- RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK
- RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK
- RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK
- RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK
- RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK
- RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK
- RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
- RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK
- RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK
- RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK
- RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK
- RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK
- RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK
- RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK
- RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK
- RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK
- RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK
- RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK
- RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK
- RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
- RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
- RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK
- RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK
- RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK
- RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK
- RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
- RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK
- RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK
- RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK
- RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
- RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK
- RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK
- RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK
- RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK
- RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK
- RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK
- RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK
- RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK
- RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK
- RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK
- RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK
- RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK
- RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK
- RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK
- RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK
- RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK
- RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK
- RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK
- RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK
- RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT
- RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK
- RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT
- RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK
- RCC_EP_DEV1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT
- RCC_EP_DEV1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK
- RCC_EP_DEV1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT
- RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK
- RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT
- RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK
- RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT
- RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK
- RCC_EP_DEV1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT
- RCC_EP_DEV1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK
- RCC_EP_DEV1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT
- RCC_EP_DEV1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK
- RCC_EP_DEV1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT
- RCC_EP_DEV1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK
- RCC_EP_DEV1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT
- RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK
- RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK
- RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK
- RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK
- RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK
- RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK
- RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK
- RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK
- RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT
- RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK
- RCC_EP_DEV1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT
- RCC_EP_DEV1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK
- RCC_EP_DEV1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT
- RCC_EP_DEV1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK
- RCC_EP_DEV1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT
- RCC_EP_DEV1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK
- RCC_EP_DEV1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT
- RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK
- RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT
- RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK
- RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT
- RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK
- RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT
- RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK
- RCC_EP_DEV1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT
- RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK
- RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT
- RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK
- RCC_EP_DEV1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT
- RCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK
- RCC_EP_DEV1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT
- RCC_EP_DEV1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK
- RCC_EP_DEV1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT
- RCC_EP_DEV1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK
- RCC_EP_DEV1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT
- RCC_EP_DEV1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK
- RCC_EP_DEV1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT
- RCC_EP_DEV1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK
- RCC_EP_DEV1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT
- RCC_EP_DEV1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK
- RCC_EP_DEV1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT
- RCC_EP_DEV1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK
- RCC_EP_DEV1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT
- RCC_EP_DEV1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK
- RCC_EP_DEV1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT
- RCC_EP_DEV1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK
- RCC_EP_DEV1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT
- RCC_EP_DEV1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK
- RCC_EP_DEV1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT
- RCC_EP_DEV1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK
- RCC_EP_DEV1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT
- RCC_EP_DEV1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK
- RCC_EP_DEV1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT
- RCC_EP_DEV1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK
- RCC_EP_DEV1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT
- RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK
- RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT
- RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK
- RCC_EP_DEV1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT
- RCC_EP_DEV1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK
- RCC_EP_DEV1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT
- RCC_EP_DEV1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK
- RCC_EP_DEV1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT
- RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK
- RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT
- RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK
- RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT
- RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK
- RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
- RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK
- RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT
- RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK
- RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT
- RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK
- RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT
- RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK
- RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT
- RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK
- RCC_EP_DEV1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT
- RCC_EP_DEV1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK
- RCC_EP_DEV1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT
- RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK
- RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT
- RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK
- RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT
- RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK
- RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT
- RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK
- RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT
- RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK
- RCC_EP_DEV1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT
- RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK
- RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT
- RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK
- RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT
- RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK
- RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT
- RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK
- RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT
- RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK
- RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT
- RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK
- RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT
- RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK
- RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT
- RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK
- RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT
- RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK
- RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT
- RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK
- RCC_EP_DEV1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT
- RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK
- RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT
- RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK
- RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT
- RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK
- RCC_EP_DEV1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT
- RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK
- RCC_EP_DEV1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT
- RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK
- RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__MASK
- RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT
- RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK
- RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__MASK
- RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT
- RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK
- RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT
- RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_ETHCKSELR
- RCC_FDCANCKSELR
- RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK
- RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__MASK
- RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT
- RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK
- RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__MASK
- RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT
- RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK
- RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__MASK
- RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT
- RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK
- RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__MASK
- RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT
- RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK
- RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT
- RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK
- RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT
- RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS_MASK
- RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__MASK
- RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT
- RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS_MASK
- RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__MASK
- RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT
- RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK
- RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__MASK
- RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT
- RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK
- RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__MASK
- RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT
- RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK
- RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__MASK
- RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT
- RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK
- RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__MASK
- RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT
- RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK
- RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__MASK
- RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT
- RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK
- RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__MASK
- RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT
- RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK
- RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__MASK
- RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT
- RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS_MASK
- RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__MASK
- RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT
- RCC_FMCCKSELR
- RCC_GPUCKSELR
- RCC_GPUIOV_REGION__LFB_REGION_MASK
- RCC_GPUIOV_REGION__LFB_REGION__SHIFT
- RCC_GPUIOV_REGION__MAX_REGION_MASK
- RCC_GPUIOV_REGION__MAX_REGION__SHIFT
- RCC_HOST_BUSNUM__HOST_ID_MASK
- RCC_HOST_BUSNUM__HOST_ID__MASK
- RCC_HOST_BUSNUM__HOST_ID__SHIFT
- RCC_HSICFGR
- RCC_I2C12CKSELR
- RCC_I2C35CKSELR
- RCC_I2C46CKSELR
- RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__MASK
- RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__MASK
- RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_LPTIM1CKSELR
- RCC_LPTIM23CKSELR
- RCC_LPTIM45CKSELR
- RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK
- RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__MASK
- RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT
- RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK
- RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT
- RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK
- RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT
- RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK
- RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT
- RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK
- RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT
- RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK
- RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT
- RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK
- RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT
- RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK
- RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT
- RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK
- RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT
- RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK
- RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT
- RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK
- RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT
- RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK
- RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT
- RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK
- RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT
- RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK
- RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT
- RCC_MASK
- RCC_MCO1CFGR
- RCC_MCO2CFGR
- RCC_MCUDIVR
- RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK
- RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__MASK
- RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT
- RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK
- RCC_MH_ARB_CNTL__MH_ARB_MODE__MASK
- RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT
- RCC_MPCKDIVR
- RCC_MPCKSELR
- RCC_MSSCKSELR
- RCC_OCENSETR
- RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK
- RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__MASK
- RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT
- RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK
- RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__MASK
- RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT
- RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK
- RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__MASK
- RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT
- RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK
- RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__MASK
- RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT
- RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK
- RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__MASK
- RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT
- RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK
- RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__MASK
- RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT
- RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK
- RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__MASK
- RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT
- RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK
- RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__MASK
- RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT
- RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK
- RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__MASK
- RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT
- RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK
- RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__MASK
- RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT
- RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK
- RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__MASK
- RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT
- RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK
- RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__MASK
- RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT
- RCC_PEER_REG_RANGE0__END_ADDR_MASK
- RCC_PEER_REG_RANGE0__END_ADDR__MASK
- RCC_PEER_REG_RANGE0__END_ADDR__SHIFT
- RCC_PEER_REG_RANGE0__START_ADDR_MASK
- RCC_PEER_REG_RANGE0__START_ADDR__MASK
- RCC_PEER_REG_RANGE0__START_ADDR__SHIFT
- RCC_PEER_REG_RANGE1__END_ADDR_MASK
- RCC_PEER_REG_RANGE1__END_ADDR__MASK
- RCC_PEER_REG_RANGE1__END_ADDR__SHIFT
- RCC_PEER_REG_RANGE1__START_ADDR_MASK
- RCC_PEER_REG_RANGE1__START_ADDR__MASK
- RCC_PEER_REG_RANGE1__START_ADDR__SHIFT
- RCC_PFC_ACP_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK
- RCC_PFC_ACP_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT
- RCC_PFC_ACP_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK
- RCC_PFC_ACP_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT
- RCC_PFC_ACP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK
- RCC_PFC_ACP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_ACP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK
- RCC_PFC_ACP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_ACP_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK
- RCC_PFC_ACP_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT
- RCC_PFC_ACP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK
- RCC_PFC_ACP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_ACP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK
- RCC_PFC_ACP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_ACP_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK
- RCC_PFC_ACP_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT
- RCC_PFC_ACP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK
- RCC_PFC_ACP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT
- RCC_PFC_ACP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK
- RCC_PFC_ACP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK
- RCC_PFC_ACP_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT
- RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK
- RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT
- RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK
- RCC_PFC_AMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT
- RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK
- RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK
- RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK
- RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT
- RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK
- RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK
- RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK
- RCC_PFC_AMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT
- RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK
- RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT
- RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK
- RCC_PFC_AMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK
- RCC_PFC_AMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT
- RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK
- RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT
- RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK
- RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT
- RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK
- RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK
- RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK
- RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT
- RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK
- RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK
- RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK
- RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT
- RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK
- RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT
- RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK
- RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK
- RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT
- RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__MASK
- RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT
- RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__MASK
- RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT
- RCC_PFC_AZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK
- RCC_PFC_AZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT
- RCC_PFC_AZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK
- RCC_PFC_AZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT
- RCC_PFC_AZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK
- RCC_PFC_AZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_AZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK
- RCC_PFC_AZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_AZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK
- RCC_PFC_AZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT
- RCC_PFC_AZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK
- RCC_PFC_AZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_AZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK
- RCC_PFC_AZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_AZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK
- RCC_PFC_AZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT
- RCC_PFC_AZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK
- RCC_PFC_AZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT
- RCC_PFC_AZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK
- RCC_PFC_AZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK
- RCC_PFC_AZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT
- RCC_PFC_GBE0_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK
- RCC_PFC_GBE0_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT
- RCC_PFC_GBE0_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK
- RCC_PFC_GBE0_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT
- RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK
- RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK
- RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK
- RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT
- RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK
- RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK
- RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK
- RCC_PFC_GBE0_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT
- RCC_PFC_GBE0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK
- RCC_PFC_GBE0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT
- RCC_PFC_GBE0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK
- RCC_PFC_GBE0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK
- RCC_PFC_GBE0_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT
- RCC_PFC_GBE1_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK
- RCC_PFC_GBE1_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT
- RCC_PFC_GBE1_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK
- RCC_PFC_GBE1_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT
- RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK
- RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK
- RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK
- RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT
- RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK
- RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK
- RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK
- RCC_PFC_GBE1_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT
- RCC_PFC_GBE1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK
- RCC_PFC_GBE1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT
- RCC_PFC_GBE1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK
- RCC_PFC_GBE1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK
- RCC_PFC_GBE1_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT
- RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__MASK
- RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__MASK
- RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__MASK
- RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT
- RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__MASK
- RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__MASK
- RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__MASK
- RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT
- RCC_PFC_MP2_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK
- RCC_PFC_MP2_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT
- RCC_PFC_MP2_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK
- RCC_PFC_MP2_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT
- RCC_PFC_MP2_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK
- RCC_PFC_MP2_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_MP2_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK
- RCC_PFC_MP2_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_MP2_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK
- RCC_PFC_MP2_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT
- RCC_PFC_MP2_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK
- RCC_PFC_MP2_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_MP2_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK
- RCC_PFC_MP2_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_MP2_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK
- RCC_PFC_MP2_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT
- RCC_PFC_MP2_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK
- RCC_PFC_MP2_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT
- RCC_PFC_MP2_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK
- RCC_PFC_MP2_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK
- RCC_PFC_MP2_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT
- RCC_PFC_PD_CONTROLLER_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK
- RCC_PFC_PD_CONTROLLER_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT
- RCC_PFC_PD_CONTROLLER_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK
- RCC_PFC_PD_CONTROLLER_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT
- RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK
- RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK
- RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK
- RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT
- RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK
- RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK
- RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK
- RCC_PFC_PD_CONTROLLER_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT
- RCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK
- RCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT
- RCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK
- RCC_PFC_PD_CONTROLLER_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK
- RCC_PFC_PD_CONTROLLER_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT
- RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__MASK
- RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT
- RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__MASK
- RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT
- RCC_PFC_PSP_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK
- RCC_PFC_PSP_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT
- RCC_PFC_PSP_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK
- RCC_PFC_PSP_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT
- RCC_PFC_PSP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK
- RCC_PFC_PSP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_PSP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK
- RCC_PFC_PSP_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_PSP_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK
- RCC_PFC_PSP_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT
- RCC_PFC_PSP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK
- RCC_PFC_PSP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_PSP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK
- RCC_PFC_PSP_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_PSP_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK
- RCC_PFC_PSP_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT
- RCC_PFC_PSP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK
- RCC_PFC_PSP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT
- RCC_PFC_PSP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK
- RCC_PFC_PSP_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK
- RCC_PFC_PSP_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT
- RCC_PFC_SATA_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK
- RCC_PFC_SATA_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT
- RCC_PFC_SATA_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK
- RCC_PFC_SATA_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT
- RCC_PFC_SATA_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK
- RCC_PFC_SATA_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_SATA_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK
- RCC_PFC_SATA_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_SATA_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK
- RCC_PFC_SATA_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT
- RCC_PFC_SATA_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK
- RCC_PFC_SATA_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_SATA_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK
- RCC_PFC_SATA_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_SATA_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK
- RCC_PFC_SATA_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT
- RCC_PFC_SATA_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK
- RCC_PFC_SATA_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT
- RCC_PFC_SATA_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK
- RCC_PFC_SATA_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK
- RCC_PFC_SATA_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT
- RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__MASK
- RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT
- RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__MASK
- RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT
- RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__MASK
- RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT
- RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__MASK
- RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT
- RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__MASK
- RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT
- RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__MASK
- RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT
- RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__MASK
- RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT
- RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__MASK
- RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT
- RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__MASK
- RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT
- RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__MASK
- RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT
- RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__MASK
- RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT
- RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__MASK
- RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT
- RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__MASK
- RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT
- RCC_PFC_USB3_0_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK
- RCC_PFC_USB3_0_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT
- RCC_PFC_USB3_0_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK
- RCC_PFC_USB3_0_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT
- RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK
- RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK
- RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK
- RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT
- RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK
- RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK
- RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK
- RCC_PFC_USB3_0_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT
- RCC_PFC_USB3_0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK
- RCC_PFC_USB3_0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT
- RCC_PFC_USB3_0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK
- RCC_PFC_USB3_0_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK
- RCC_PFC_USB3_0_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT
- RCC_PFC_USB3_1_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK
- RCC_PFC_USB3_1_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT
- RCC_PFC_USB3_1_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK
- RCC_PFC_USB3_1_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT
- RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK
- RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK
- RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK
- RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT
- RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK
- RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK
- RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK
- RCC_PFC_USB3_1_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT
- RCC_PFC_USB3_1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK
- RCC_PFC_USB3_1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT
- RCC_PFC_USB3_1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK
- RCC_PFC_USB3_1_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK
- RCC_PFC_USB3_1_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT
- RCC_PFC_USB_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK
- RCC_PFC_USB_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT
- RCC_PFC_USB_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK
- RCC_PFC_USB_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT
- RCC_PFC_USB_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK
- RCC_PFC_USB_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_USB_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK
- RCC_PFC_USB_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_USB_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK
- RCC_PFC_USB_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT
- RCC_PFC_USB_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK
- RCC_PFC_USB_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT
- RCC_PFC_USB_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK
- RCC_PFC_USB_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT
- RCC_PFC_USB_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK
- RCC_PFC_USB_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT
- RCC_PFC_USB_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK
- RCC_PFC_USB_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT
- RCC_PFC_USB_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK
- RCC_PFC_USB_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK
- RCC_PFC_USB_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT
- RCC_PF_0_0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_PF_0_0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_PF_0_0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_PF_0_0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_PF_0_0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_PF_0_0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_PF_0_0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_PF_0_0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_PF_0_0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_PF_0_0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_PF_0_0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_PF_0_1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK
- RCC_PF_0_1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT
- RCC_PF_0_1_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK
- RCC_PF_0_1_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT
- RCC_PF_0_1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK
- RCC_PF_0_1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT
- RCC_PF_0_1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK
- RCC_PF_0_1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT
- RCC_PF_0_1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK
- RCC_PF_0_1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT
- RCC_PF_0_1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK
- RCC_PF_0_1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT
- RCC_PF_0_1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK
- RCC_PF_0_1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT
- RCC_PF_0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK
- RCC_PF_0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT
- RCC_PF_0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK
- RCC_PF_0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT
- RCC_PF_0_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK
- RCC_PF_0_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT
- RCC_PF_0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_PF_0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_PF_0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_PF_0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_PF_0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK
- RCC_PF_0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT
- RCC_PF_0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK
- RCC_PF_0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT
- RCC_PF_0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_PF_0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_PF_0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_PF_0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_PF_0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK
- RCC_PF_0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT
- RCC_PF_0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK
- RCC_PF_0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT
- RCC_PF_0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK
- RCC_PF_0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT
- RCC_PF_0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK
- RCC_PF_0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT
- RCC_PF_0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK
- RCC_PF_0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT
- RCC_PF_0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK
- RCC_PF_0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT
- RCC_PLL1CFGR1
- RCC_PLL1CFGR2
- RCC_PLL1CR
- RCC_PLL1DIVR
- RCC_PLL1FRACR
- RCC_PLL2CFGR1
- RCC_PLL2CFGR2
- RCC_PLL2CR
- RCC_PLL2DIVR
- RCC_PLL2FRACR
- RCC_PLL3CFGR1
- RCC_PLL3CFGR2
- RCC_PLL3CR
- RCC_PLL3DIVR
- RCC_PLL3FRACR
- RCC_PLL4CFGR1
- RCC_PLL4CFGR2
- RCC_PLL4CR
- RCC_PLLCFGR
- RCC_PLLCKSELR
- RCC_QSPICKSELR
- RCC_RCK12SELR
- RCC_RCK3SELR
- RCC_RCK4SELR
- RCC_RDLSICR
- RCC_RESET_EN__DB_APER_RESET_EN_MASK
- RCC_RESET_EN__DB_APER_RESET_EN__MASK
- RCC_RESET_EN__DB_APER_RESET_EN__SHIFT
- RCC_RNG1CKSELR
- RCC_RNG2CKSELR
- RCC_RTCDIVR
- RCC_SAI1CKSELR
- RCC_SAI2CKSELR
- RCC_SAI3CKSELR
- RCC_SAI4CKSELR
- RCC_SDMMC12CKSELR
- RCC_SDMMC3CKSELR
- RCC_SHIFT_BIT
- RCC_SPDIFCKSELR
- RCC_SPI2S1CKSELR
- RCC_SPI2S23CKSELR
- RCC_SPI2S45CKSELR
- RCC_SPI6CKSELR
- RCC_STAT
- RCC_STGENCKSELR
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CLK_PM_EN_PIN_MASK
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CLK_PM_EN_PIN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN_MASK
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK
- RCC_STRAP0_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK
- RCC_STRAP0_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK
- RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_TRUE_PM_STATUS_EN_MASK
- RCC_STRAP0_RCC_BIF_STRAP1__STRAP_TRUE_PM_STATUS_EN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP1__WRITE_DISABLE_MASK
- RCC_STRAP0_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK
- RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK
- RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK
- RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK
- RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK
- RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK
- RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK
- RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK
- RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK
- RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK
- RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK
- RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK
- RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK
- RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK
- RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK
- RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK
- RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK
- RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK
- RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK
- RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK
- RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK
- RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK
- RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK
- RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK
- RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK
- RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK
- RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK
- RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK
- RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT
- RCC_STRAP0_RCC_BIF_STRAP6__RESERVED_BIF_STRAP3_MASK
- RCC_STRAP0_RCC_BIF_STRAP6__RESERVED_BIF_STRAP3__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK
- RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_EN_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_EN_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F1_MASK
- RCC_STRAP0_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F1__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT
- RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK
- RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CLK_PM_EN_PIN_MASK
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CLK_PM_EN_PIN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN_MASK
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS_PIN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN_MASK
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MEM_AP_SIZE_PIN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR_MASK
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN_MASK
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN_MASK
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_DN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR_MASK
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_TC_ERR__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN_MASK
- RCC_STRAP1_RCC_BIF_STRAP0__STRAP_VGA_DIS_PIN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK
- RCC_STRAP1_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK
- RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN_MASK
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_MMREG_WR_POSTED_EN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS_MASK
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_S5_REGS_ACCESS_DIS__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_TRUE_PM_STATUS_EN_MASK
- RCC_STRAP1_RCC_BIF_STRAP1__STRAP_TRUE_PM_STATUS_EN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP1__WRITE_DISABLE_MASK
- RCC_STRAP1_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK
- RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK
- RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK
- RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK
- RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK
- RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK
- RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK
- RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK
- RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK
- RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK
- RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK
- RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK
- RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK
- RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK
- RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK
- RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK
- RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK
- RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK
- RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK
- RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK
- RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK
- RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK
- RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK
- RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK
- RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK
- RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK
- RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK
- RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK
- RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT
- RCC_STRAP1_RCC_BIF_STRAP6__RESERVED_BIF_STRAP3_MASK
- RCC_STRAP1_RCC_BIF_STRAP6__RESERVED_BIF_STRAP3__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK
- RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_CPLR_SUPPORTED_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_EN_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_EN_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_DEV_SPC_MODE_SUPPORTED_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_LOCATION_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F1_MASK
- RCC_STRAP1_RCC_DEV0_EPF1_STRAP7__STRAP_TPH_REQR_ST_TABLE_SIZE_DEV0_F1__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT
- RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK
- RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT
- RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK
- RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT
- RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK
- RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT
- RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK
- RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT
- RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK
- RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT
- RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK
- RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT
- RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK
- RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT
- RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK
- RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT
- RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK
- RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT
- RCC_TIMG1PRER
- RCC_TIMG2PRER
- RCC_UART1CKSELR
- RCC_UART24CKSELR
- RCC_UART35CKSELR
- RCC_UART6CKSELR
- RCC_UART78CKSELR
- RCC_USBCKSELR
- RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK
- RCC_VDM_SUPPORT__AMPTP_SUPPORT__MASK
- RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT
- RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK
- RCC_VDM_SUPPORT__MCTP_SUPPORT__MASK
- RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT
- RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK
- RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__MASK
- RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT
- RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK
- RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__MASK
- RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT
- RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK
- RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__MASK
- RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT
- RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK
- RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__MASK
- RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT
- RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK
- RCC_XDMA_LO__BIF_XDMA_APER_EN__MASK
- RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT
- RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK
- RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__MASK
- RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT
- RCD0
- RCD0bh
- RCD0bl
- RCD0d
- RCD1
- RCD1bh
- RCD1bl
- RCD1d
- RCD2
- RCDA
- RCDE
- RCDE_ADDR
- RCDNEI
- RCDPLL
- RCD_EN
- RCENTSYNC
- RCFW_BLOCKED_CMD_WAIT_COUNT
- RCFW_CMDQ_TRIG_VAL
- RCFW_CMD_IS_BLOCKING
- RCFW_CMD_PREP
- RCFW_CMD_WAIT_TIME_MS
- RCFW_COMM_BASE_OFFSET
- RCFW_COMM_CONS_PCI_BAR_REGION
- RCFW_COMM_PCI_BAR_REGION
- RCFW_COMM_SIZE
- RCFW_COMM_TRIG_OFFSET
- RCFW_DBR_BASE_PAGE_SHIFT
- RCFW_DBR_PCI_BAR_REGION
- RCFW_MAX_COOKIE_VALUE
- RCFW_PF_COMM_PROD_OFFSET
- RCFW_VF_COMM_PROD_OFFSET
- RCG_CFG_OFFSET
- RCG_D_OFFSET
- RCG_M_OFFSET
- RCG_N_OFFSET
- RCIP_F
- RCIP_S
- RCIP_V
- RCISH
- RCISH_MASK
- RCISH_SHIFT
- RCI_SIGNATURE
- RCKCR_CKSEL
- RCKPOL_MASK
- RCKPOL_SHIFT
- RCKP_GET_CONFIG
- RCKP_GET_PORTS
- RCKP_GET_VERSION
- RCKP_RESET_RM2
- RCKP_SET_CONFIG
- RCKSEL_SHIFT
- RCK_CTRL_RGMII_1000
- RCK_CTRL_RGMII_10_100
- RCLK_MON
- RCLR
- RCLRVALUE
- RCMABR_BA
- RCMCONFIG
- RCMDQUEUE
- RCMLBM_BA
- RCMM_PREFIX_PULSE
- RCMM_PULSE_0
- RCMM_PULSE_1
- RCMM_PULSE_2
- RCMM_PULSE_3
- RCMM_UNIT
- RCMODE_TIMEOUT
- RCMPM_BIT
- RCMPM_SHIFT
- RCMRSRB_BA
- RCMR_CMP
- RCMR_CMP_1
- RCMR_CMP_2
- RCMR_CMP_CFG
- RCMR_MATCHEN
- RCMTA_SIZE
- RCM_BSSID_OFFSET
- RCM_F_BSSID_0_OFFSET
- RCM_F_BSSID_1_OFFSET
- RCM_F_BSSID_2_OFFSET
- RCM_INC_DATA
- RCM_INC_MASK_H
- RCM_INC_MASK_L
- RCM_INDEX_MASK
- RCM_MAC_OFFSET
- RCM_MEM_SIZE
- RCM_SIZE
- RCM_WEP_TA0_OFFSET
- RCM_WEP_TA1_OFFSET
- RCM_WEP_TA2_OFFSET
- RCM_WEP_TA3_OFFSET
- RCN
- RCNR
- RCNSH
- RCNSH_MASK
- RCNSH_SHIFT
- RCNT
- RCNTCFG_INIT
- RCNTINFO_INIT
- RCNT_MASK
- RCODE_ADDRESS_ERROR
- RCODE_BUSY
- RCODE_CANCELLED
- RCODE_COMPLETE
- RCODE_CONFLICT_ERROR
- RCODE_DATA_ERROR
- RCODE_GENERATION
- RCODE_NO_ACK
- RCODE_SEND_ERROR
- RCODE_TYPE_ERROR
- RCOMPAND
- RCOMP_SCALAR
- RCOMP_SCALAR_MASK
- RCON
- RCONF
- RCONFIG_ANTA
- RCONFIG_ANTB
- RCONFIG_PMPD_ANTA
- RCONFIG_PMPD_ANTB
- RCONFIG_RAM64x16
- RCONFIG_ram64x16
- RCOSH
- RCOSH_MASK
- RCOSH_SHIFT
- RCP14_DBGAUTHSTATUS
- RCP14_DBGBCR0
- RCP14_DBGBCR1
- RCP14_DBGBCR10
- RCP14_DBGBCR11
- RCP14_DBGBCR12
- RCP14_DBGBCR13
- RCP14_DBGBCR14
- RCP14_DBGBCR15
- RCP14_DBGBCR2
- RCP14_DBGBCR3
- RCP14_DBGBCR4
- RCP14_DBGBCR5
- RCP14_DBGBCR6
- RCP14_DBGBCR7
- RCP14_DBGBCR8
- RCP14_DBGBCR9
- RCP14_DBGBVR0
- RCP14_DBGBVR1
- RCP14_DBGBVR10
- RCP14_DBGBVR11
- RCP14_DBGBVR12
- RCP14_DBGBVR13
- RCP14_DBGBVR14
- RCP14_DBGBVR15
- RCP14_DBGBVR2
- RCP14_DBGBVR3
- RCP14_DBGBVR4
- RCP14_DBGBVR5
- RCP14_DBGBVR6
- RCP14_DBGBVR7
- RCP14_DBGBVR8
- RCP14_DBGBVR9
- RCP14_DBGBXVR0
- RCP14_DBGBXVR1
- RCP14_DBGBXVR10
- RCP14_DBGBXVR11
- RCP14_DBGBXVR12
- RCP14_DBGBXVR13
- RCP14_DBGBXVR14
- RCP14_DBGBXVR15
- RCP14_DBGBXVR2
- RCP14_DBGBXVR3
- RCP14_DBGBXVR4
- RCP14_DBGBXVR5
- RCP14_DBGBXVR6
- RCP14_DBGBXVR7
- RCP14_DBGBXVR8
- RCP14_DBGBXVR9
- RCP14_DBGCLAIMCLR
- RCP14_DBGCLAIMSET
- RCP14_DBGDEVID
- RCP14_DBGDEVID1
- RCP14_DBGDEVID2
- RCP14_DBGDIDR
- RCP14_DBGDRAR
- RCP14_DBGDRCR
- RCP14_DBGDSAR
- RCP14_DBGDSCCR
- RCP14_DBGDSCRext
- RCP14_DBGDSCRint
- RCP14_DBGDSMCR
- RCP14_DBGDTRRXext
- RCP14_DBGDTRRXint
- RCP14_DBGDTRTXext
- RCP14_DBGECR
- RCP14_DBGITCTRL
- RCP14_DBGOSDLR
- RCP14_DBGOSLSR
- RCP14_DBGOSSRR
- RCP14_DBGPRCR
- RCP14_DBGPRSR
- RCP14_DBGVCR
- RCP14_DBGWCR0
- RCP14_DBGWCR1
- RCP14_DBGWCR10
- RCP14_DBGWCR11
- RCP14_DBGWCR12
- RCP14_DBGWCR13
- RCP14_DBGWCR14
- RCP14_DBGWCR15
- RCP14_DBGWCR2
- RCP14_DBGWCR3
- RCP14_DBGWCR4
- RCP14_DBGWCR5
- RCP14_DBGWCR6
- RCP14_DBGWCR7
- RCP14_DBGWCR8
- RCP14_DBGWCR9
- RCP14_DBGWFAR
- RCP14_DBGWVR0
- RCP14_DBGWVR1
- RCP14_DBGWVR10
- RCP14_DBGWVR11
- RCP14_DBGWVR12
- RCP14_DBGWVR13
- RCP14_DBGWVR14
- RCP14_DBGWVR15
- RCP14_DBGWVR2
- RCP14_DBGWVR3
- RCP14_DBGWVR4
- RCP14_DBGWVR5
- RCP14_DBGWVR6
- RCP14_DBGWVR7
- RCP14_DBGWVR8
- RCP14_DBGWVR9
- RCP14_ETMACTR0
- RCP14_ETMACTR1
- RCP14_ETMACTR10
- RCP14_ETMACTR11
- RCP14_ETMACTR12
- RCP14_ETMACTR13
- RCP14_ETMACTR14
- RCP14_ETMACTR15
- RCP14_ETMACTR2
- RCP14_ETMACTR3
- RCP14_ETMACTR4
- RCP14_ETMACTR5
- RCP14_ETMACTR6
- RCP14_ETMACTR7
- RCP14_ETMACTR8
- RCP14_ETMACTR9
- RCP14_ETMACVR0
- RCP14_ETMACVR1
- RCP14_ETMACVR10
- RCP14_ETMACVR11
- RCP14_ETMACVR12
- RCP14_ETMACVR13
- RCP14_ETMACVR14
- RCP14_ETMACVR15
- RCP14_ETMACVR2
- RCP14_ETMACVR3
- RCP14_ETMACVR4
- RCP14_ETMACVR5
- RCP14_ETMACVR6
- RCP14_ETMACVR7
- RCP14_ETMACVR8
- RCP14_ETMACVR9
- RCP14_ETMASICCR
- RCP14_ETMAUTHSTATUS
- RCP14_ETMAUXCR
- RCP14_ETMCCER
- RCP14_ETMCCR
- RCP14_ETMCIDCMR
- RCP14_ETMCIDCVR0
- RCP14_ETMCIDCVR1
- RCP14_ETMCIDCVR2
- RCP14_ETMCIDR0
- RCP14_ETMCIDR1
- RCP14_ETMCIDR2
- RCP14_ETMCIDR3
- RCP14_ETMCLAIMCLR
- RCP14_ETMCLAIMSET
- RCP14_ETMCNTENR0
- RCP14_ETMCNTENR1
- RCP14_ETMCNTENR2
- RCP14_ETMCNTENR3
- RCP14_ETMCNTRLDEVR0
- RCP14_ETMCNTRLDEVR1
- RCP14_ETMCNTRLDEVR2
- RCP14_ETMCNTRLDEVR3
- RCP14_ETMCNTRLDVR0
- RCP14_ETMCNTRLDVR1
- RCP14_ETMCNTRLDVR2
- RCP14_ETMCNTRLDVR3
- RCP14_ETMCNTVR0
- RCP14_ETMCNTVR1
- RCP14_ETMCNTVR2
- RCP14_ETMCNTVR3
- RCP14_ETMCR
- RCP14_ETMDCMR0
- RCP14_ETMDCMR10
- RCP14_ETMDCMR12
- RCP14_ETMDCMR14
- RCP14_ETMDCMR2
- RCP14_ETMDCMR4
- RCP14_ETMDCMR6
- RCP14_ETMDCMR8
- RCP14_ETMDCVR0
- RCP14_ETMDCVR10
- RCP14_ETMDCVR12
- RCP14_ETMDCVR14
- RCP14_ETMDCVR2
- RCP14_ETMDCVR4
- RCP14_ETMDCVR6
- RCP14_ETMDCVR8
- RCP14_ETMDEVID
- RCP14_ETMDEVTYPE
- RCP14_ETMEIBCR
- RCP14_ETMEXTINSELR
- RCP14_ETMEXTOUTEVR0
- RCP14_ETMEXTOUTEVR1
- RCP14_ETMEXTOUTEVR2
- RCP14_ETMEXTOUTEVR3
- RCP14_ETMFFLR
- RCP14_ETMFFRR
- RCP14_ETMIDR
- RCP14_ETMIDR2
- RCP14_ETMIMPSPEC0
- RCP14_ETMIMPSPEC1
- RCP14_ETMIMPSPEC2
- RCP14_ETMIMPSPEC3
- RCP14_ETMIMPSPEC4
- RCP14_ETMIMPSPEC5
- RCP14_ETMIMPSPEC6
- RCP14_ETMIMPSPEC7
- RCP14_ETMITCTRL
- RCP14_ETMLSR
- RCP14_ETMOSLSR
- RCP14_ETMOSSRR
- RCP14_ETMPDCR
- RCP14_ETMPDSR
- RCP14_ETMPIDR0
- RCP14_ETMPIDR1
- RCP14_ETMPIDR2
- RCP14_ETMPIDR3
- RCP14_ETMPIDR4
- RCP14_ETMPIDR5
- RCP14_ETMPIDR6
- RCP14_ETMPIDR7
- RCP14_ETMSCR
- RCP14_ETMSQ12EVR
- RCP14_ETMSQ13EVR
- RCP14_ETMSQ21EVR
- RCP14_ETMSQ23EVR
- RCP14_ETMSQ31EVR
- RCP14_ETMSQ32EVR
- RCP14_ETMSQR
- RCP14_ETMSR
- RCP14_ETMSYNCFR
- RCP14_ETMTECR1
- RCP14_ETMTECR2
- RCP14_ETMTEEVR
- RCP14_ETMTESSEICR
- RCP14_ETMTRACEIDR
- RCP14_ETMTRIGGER
- RCP14_ETMTSEVR
- RCP14_ETMTSSCR
- RCP14_ETMVDCR1
- RCP14_ETMVDCR2
- RCP14_ETMVDCR3
- RCP14_ETMVDEVR
- RCP14_ETMVMIDCVR
- RCPM_POWMGTCSR_LPM20_RQ
- RCPM_POWMGTCSR_LPM20_ST
- RCPM_POWMGTCSR_P_LPM20_ST
- RCPM_POWMGTCSR_SLP
- RCPREVBSYTDNAVG
- RCPREVBSYTUPAVG
- RCP_CONFIG
- RCQDA
- RCQ_BD
- RCQ_DESC_CNT
- RCQ_SUPPORT
- RCQ_TH_HI
- RCQ_TH_LO
- RCR
- RCR1
- RCR1_AF
- RCR1_AIE
- RCR1_CF
- RCR1_CIE
- RCR2
- RCR2_ADJ
- RCR2_PEF
- RCR2_PESMASK
- RCR2_RESET
- RCR2_RTCEN
- RCR2_START
- RCRCFIG_A
- RCRCFIG_A_LEN
- RCRCFIG_A_LEN_SHIFT
- RCRCFIG_A_STADDR
- RCRCFIG_A_STADDR_BASE
- RCRCFIG_B
- RCRCFIG_B_ENTOUT
- RCRCFIG_B_PTHRES
- RCRCFIG_B_PTHRES_SHIFT
- RCRCFIG_B_TIMEOUT
- RCRCFIG_B_TIMEOUT_SHIFT
- RCRCODE
- RCRCR
- RCRSTAT_A
- RCRSTAT_A_QLEN
- RCRSTAT_B
- RCRSTAT_B_TIPTR_H
- RCRSTAT_C
- RCRSTAT_C_TIPTR_L
- RCRTxCP
- RCRU
- RCR_9356SEL
- RCR_AAP
- RCR_AB
- RCR_ABORT_ENB
- RCR_ACCEPT_ADDR3
- RCR_ACCEPT_AP
- RCR_ACCEPT_BA_SSN
- RCR_ACCEPT_BCAST
- RCR_ACCEPT_CRC32
- RCR_ACCEPT_CTRL_FRAME
- RCR_ACCEPT_DATA_FRAME
- RCR_ACCEPT_ICV
- RCR_ACCEPT_MCAST
- RCR_ACCEPT_MGMT_FRAME
- RCR_ACCEPT_PHYS_MATCH
- RCR_ACCEPT_PM
- RCR_ACF
- RCR_ACKTXBW
- RCR_ACPT_ALL
- RCR_ACRC32
- RCR_ADD3
- RCR_ADF
- RCR_AICV
- RCR_AL
- RCR_ALL
- RCR_ALMUL
- RCR_AM
- RCR_AMF
- RCR_AP
- RCR_APM
- RCR_APPEND_FCS
- RCR_APPEND_ICV
- RCR_APPEND_MIC
- RCR_APPEND_PHYSTAT
- RCR_APPFCS
- RCR_APP_BA_SSN
- RCR_APP_FCS
- RCR_APP_ICV
- RCR_APP_MIC
- RCR_APP_PHYSTS
- RCR_APP_PHYST_RXFF
- RCR_APP_PHYST_STAFF
- RCR_APWRMGT
- RCR_AR
- RCR_AS
- RCR_BAD
- RCR_BIT
- RCR_BM_DATA_EN
- RCR_BM_DATA_PKT_INT_ENABLE
- RCR_BROADCAST
- RCR_BSSID
- RCR_BTS
- RCR_CARRY
- RCR_CBSSID
- RCR_CBSSID_BCN
- RCR_CBSSID_DATA
- RCR_CHECK_BSSID_BEACON
- RCR_CHECK_BSSID_MATCH
- RCR_CLEAR
- RCR_DEFAULT
- RCR_DIE
- RCR_DIS_AES_2BYTE
- RCR_DIS_CRC
- RCR_DIS_ENC_2BYTE
- RCR_DIS_LONG
- RCR_DM
- RCR_DS
- RCR_EFFS
- RCR_EN
- RCR_ENABLE
- RCR_ENCF
- RCR_ENCS1
- RCR_ENCS2
- RCR_ENMARP
- RCR_ENMBID
- RCR_ENTRY_DCF_ERR
- RCR_ENTRY_ERROR
- RCR_ENTRY_L2_LEN
- RCR_ENTRY_L2_LEN_SHIFT
- RCR_ENTRY_MULTI
- RCR_ENTRY_NOPORT
- RCR_ENTRY_PKTBUFSZ
- RCR_ENTRY_PKTBUFSZ_SHIFT
- RCR_ENTRY_PKT_BUF_ADDR
- RCR_ENTRY_PKT_BUF_ADDR_SHIFT
- RCR_ENTRY_PKT_TYPE
- RCR_ENTRY_PKT_TYPE_SHIFT
- RCR_ENTRY_PROMISC
- RCR_ENTRY_ZERO_COPY
- RCR_ERRCRC
- RCR_ESF
- RCR_ETS0
- RCR_ETS2
- RCR_EnCS1
- RCR_EnCS2
- RCR_FIFO_OFFSET
- RCR_FILTER_MASK
- RCR_FILT_CAR
- RCR_FL
- RCR_FLSH
- RCR_FLSH_FLSH
- RCR_FORCE_ACK
- RCR_GOOD
- RCR_HTC_LOC_CTRL
- RCR_LE
- RCR_LK
- RCR_LSIGEN
- RCR_LSIG_ENABLE
- RCR_MFBEN
- RCR_MULTICAST
- RCR_MULTI_BSSID_ENABLE
- RCR_MXDMA_OFFSET
- RCR_NONQOS_VHT
- RCR_NORMAL
- RCR_ONLYERLPKT
- RCR_OP_DATA_SEG_GRAN_LOG2
- RCR_OP_HELD_DATA_GRAN_LOG2
- RCR_OP_INLINE_DATA_GRAN_LOG2
- RCR_OP_MAX_CONCURR_COPIES
- RCR_OP_MAX_DESC_LIST_LEN
- RCR_OP_MAX_SEGMENT_LEN
- RCR_OP_MAX_SG_DESC_COUNT
- RCR_OP_MAX_TARGET_DESC_COUNT
- RCR_OP_TOTAL_CONCURR_COPIES
- RCR_OnlyErlPkt
- RCR_PKT_TYPE_OTHER
- RCR_PKT_TYPE_SCTP
- RCR_PKT_TYPE_TCP
- RCR_PKT_TYPE_UDP
- RCR_PRMS
- RCR_PRMSC
- RCR_PROM
- RCR_PROMISC
- RCR_REG
- RCR_RFCL
- RCR_RFI
- RCR_RS
- RCR_RSVD_BIT10
- RCR_RSVD_BIT15
- RCR_RSVD_BIT19
- RCR_RSVD_BIT20
- RCR_RSVD_BIT21
- RCR_RSVD_BIT25
- RCR_RUNT
- RCR_RXALLTYPE
- RCR_RXDESC_LK_EN
- RCR_RXEN
- RCR_RXFTH
- RCR_RXFTH0
- RCR_RXSHFT_EN
- RCR_RX_ABORT
- RCR_RX_TCPOFDL_EN
- RCR_SA_COPY_STATUS
- RCR_SA_FAILED_SEGMENT_DETAILS
- RCR_SA_OPERATING_PARAMETERS
- RCR_SA_RECEIVE_DATA
- RCR_SEP
- RCR_SHIFT
- RCR_SOFTRESET
- RCR_SOFTRST
- RCR_SSID
- RCR_STRIP_CRC
- RCR_TCPOFLD_EN
- RCR_TIM_PARSER_EN
- RCR_TIM_PARSER_ENABLE
- RCR_UC_DATA_EN
- RCR_UC_DATA_PKT_INT_ENABLE
- RCR_UNICAST
- RCR_VHT_ACK
- RCR_WPAERR
- RCR_WTDIS
- RCS0
- RCS0_HW
- RCS380P_PRODUCT_ID
- RCS380S_PRODUCT_ID
- RCSE
- RCSE_ADDR
- RCSR
- RCSR_CSUM
- RCSR_DISCARD
- RCSR_GPR
- RCSR_HWR
- RCSR_IP
- RCSR_IP_BAD
- RCSR_SMR
- RCSR_SWR
- RCSR_TCP
- RCSR_TCP_BAD
- RCSR_UDP
- RCSR_UDP_BAD
- RCSR_WDR
- RCS_AS_CONTEXT_SWITCH
- RCS_BASE
- RCS_BUFFER_BUSY
- RCS_BUFFER_FREE
- RCS_BUFFER_RELEASE
- RCS_CMD_STREAMER_ERR
- RCS_COMPLETE
- RCS_DEBUG
- RCS_FAILED
- RCS_ID
- RCS_L3_PARITY_ERR
- RCS_MI_USER_INTERRUPT
- RCS_MMIO_SYNC_FLUSH
- RCS_MONITOR_BUFF_HALF_FULL
- RCS_PAGE_DIRECTORY_FAULT
- RCS_PIPE_CONTROL
- RCS_WATCHDOG_EXCEEDED
- RCTRL_CHECKSUMMING
- RCTRL_EMEN
- RCTRL_EXTHASH
- RCTRL_FILREN
- RCTRL_GHTX
- RCTRL_GRS
- RCTRL_IPCSEN
- RCTRL_LFC
- RCTRL_MPROM
- RCTRL_PADDING
- RCTRL_PAL_MASK
- RCTRL_PAL_SHIFT
- RCTRL_PROM
- RCTRL_PRSDEP_INIT
- RCTRL_PRSDEP_MASK
- RCTRL_PRSFM
- RCTRL_REQ_PARSER
- RCTRL_RSF
- RCTRL_RTSE
- RCTRL_TS_ENABLE
- RCTRL_TUCSEN
- RCTRL_UPROM
- RCTRL_VLAN
- RCTRL_VLEX
- RCTRxCP
- RCUPEI
- RCUPERF_SHUTDOWN
- RCUTORTURENAME_LEN
- RCUTORTURE_MAX_EXTEND
- RCUTORTURE_RDR_BH
- RCUTORTURE_RDR_IRQ
- RCUTORTURE_RDR_MASK
- RCUTORTURE_RDR_MAX_LOOPS
- RCUTORTURE_RDR_MAX_SEGS
- RCUTORTURE_RDR_NBITS
- RCUTORTURE_RDR_PREEMPT
- RCUTORTURE_RDR_RBH
- RCUTORTURE_RDR_RCU
- RCUTORTURE_RDR_SCHED
- RCUTORTURE_RDR_SHIFT
- RCU_ABBR
- RCU_ALTVDDNB_NOTIFY
- RCU_BOOST_DELAY_JIFFIES
- RCU_BOOST_MARGIN
- RCU_CBLIST_INITIALIZER
- RCU_CBLIST_NSEGS
- RCU_CCF_BITS0
- RCU_CCF_BITS1
- RCU_CCF_DWORDS0
- RCU_CCF_DWORDS1
- RCU_CFG1_DIS_THR_MASK
- RCU_CFG1_DIS_THR_SHIFT
- RCU_CFG1_TX_PEE
- RCU_DONE_TAIL
- RCU_DYNTICK_CTRL_CTR
- RCU_DYNTICK_CTRL_MASK
- RCU_EXP_BLKD
- RCU_EXP_TASKS
- RCU_FANOUT
- RCU_FANOUT_1
- RCU_FANOUT_2
- RCU_FANOUT_3
- RCU_FANOUT_4
- RCU_FANOUT_LEAF
- RCU_FLAVOR
- RCU_FQS_NAME_INIT
- RCU_FW_VERSION
- RCU_GNB_PWR_REP_TIMER_CNTL
- RCU_GPU_BOOST_DISABLE
- RCU_GP_BLKD
- RCU_GP_CLEANED
- RCU_GP_CLEANUP
- RCU_GP_DOING_FQS
- RCU_GP_DONE_GPS
- RCU_GP_FLAG_FQS
- RCU_GP_FLAG_INIT
- RCU_GP_IDLE
- RCU_GP_INIT
- RCU_GP_ONOFF
- RCU_GP_TASKS
- RCU_GP_WAIT_FQS
- RCU_GP_WAIT_GPS
- RCU_IDLE_GP_DELAY
- RCU_IDLE_LAZY_GP_DELAY
- RCU_IND_DATA
- RCU_IND_INDEX
- RCU_INITIALIZER
- RCU_INIT_POINTER
- RCU_JIFFIES_FQS_DIV
- RCU_JIFFIES_TILL_FORCE_QS
- RCU_KTHREAD_MAX
- RCU_KTHREAD_OFFCPU
- RCU_KTHREAD_RUNNING
- RCU_KTHREAD_STOPPED
- RCU_KTHREAD_WAITING
- RCU_KTHREAD_YIELDING
- RCU_LCLK_SCALING_CNTL
- RCU_LOCKDEP_WARN
- RCU_MISC_CTRL__BREAK_PT1_DONE_MASK
- RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT
- RCU_MISC_CTRL__BREAK_PT2_DONE_MASK
- RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT
- RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK
- RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT
- RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK
- RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT
- RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK
- RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT
- RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK
- RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT
- RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK
- RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT
- RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK
- RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT
- RCU_MISC_CTRL__SAMU_START_MASK
- RCU_MISC_CTRL__SAMU_START__SHIFT
- RCU_NAME
- RCU_NAME_RAW
- RCU_NEST_BIAS
- RCU_NEST_NMAX
- RCU_NEST_PMAX
- RCU_NEXT_READY_TAIL
- RCU_NEXT_TAIL
- RCU_NOCB_WAKE
- RCU_NOCB_WAKE_FORCE
- RCU_NOCB_WAKE_NOT
- RCU_NODE_NAME_INIT
- RCU_NONIDLE
- RCU_NUM_LVLS
- RCU_POINTER_INITIALIZER
- RCU_PWR_GATING_CNTL
- RCU_PWR_GATING_CNTL_2
- RCU_PWR_GATING_CNTL_3
- RCU_PWR_GATING_CNTL_4
- RCU_PWR_GATING_CNTL_5
- RCU_PWR_GATING_SEQ0
- RCU_PWR_GATING_SEQ1
- RCU_SAM_BYTES
- RCU_SAM_RTL_BYTES
- RCU_SCHEDULER_INACTIVE
- RCU_SCHEDULER_INIT
- RCU_SCHEDULER_RUNNING
- RCU_SEGCBLIST_INITIALIZER
- RCU_SEQ_CTR_SHIFT
- RCU_SEQ_STATE_MASK
- RCU_SMU_BYTES
- RCU_SMU_RTL_BYTES
- RCU_SOFTIRQ
- RCU_STALL_DELAY_DELTA
- RCU_STALL_RAT_DELAY
- RCU_STATUS
- RCU_SclkDpmTdpLimit01
- RCU_SclkDpmTdpLimit23
- RCU_SclkDpmTdpLimit47
- RCU_SclkDpmTdpLimitPG
- RCU_TASKS_FLAVOR
- RCU_TASK_STALL_TIMEOUT
- RCU_THROTTLE_MARGIN
- RCU_TORTURE_PIPE_LEN
- RCU_TRIVIAL_FLAVOR
- RCU_UC_EVENTS
- RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK
- RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT
- RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK
- RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT
- RCU_UC_EVENTS__FCH_HALT_MASK
- RCU_UC_EVENTS__FCH_HALT__SHIFT
- RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK
- RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT
- RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK
- RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT
- RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK
- RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT
- RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK
- RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT
- RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK
- RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT
- RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK
- RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT
- RCU_UC_EVENTS__SMU_DC_efuse_status_invalid_MASK
- RCU_UC_EVENTS__SMU_DC_efuse_status_invalid__SHIFT
- RCU_UC_EVENTS__TP_Tester_MASK
- RCU_UC_EVENTS__TP_Tester__SHIFT
- RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK
- RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT
- RCU_UC_EVENTS__boot_seq_done_MASK
- RCU_UC_EVENTS__boot_seq_done__SHIFT
- RCU_UC_EVENTS__drv_rst_mode_MASK
- RCU_UC_EVENTS__drv_rst_mode__SHIFT
- RCU_UC_EVENTS__irq31_sel_MASK
- RCU_UC_EVENTS__irq31_sel__SHIFT
- RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK
- RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT
- RCU_VIRT_RESET_REQ__PF_MASK
- RCU_VIRT_RESET_REQ__PF__SHIFT
- RCU_VIRT_RESET_REQ__VF_MASK
- RCU_VIRT_RESET_REQ__VF__SHIFT
- RCU_VR9_BE_AHB1S
- RCU_WAIT_TAIL
- RCVBDI_JUMBO_PROD_IDX
- RCVBDI_JUMBO_THRESH
- RCVBDI_MINI_PROD_IDX
- RCVBDI_MINI_THRESH
- RCVBDI_MODE
- RCVBDI_MODE_ENABLE
- RCVBDI_MODE_RCB_ATTN_ENAB
- RCVBDI_MODE_RESET
- RCVBDI_STATUS
- RCVBDI_STATUS_RCB_ATTN
- RCVBDI_STD_PROD_IDX
- RCVBDI_STD_THRESH
- RCVBRST
- RCVBUF_DEF
- RCVBUF_MAX
- RCVBUF_MIN
- RCVCCO
- RCVCCOM
- RCVCC_JUMP_PROD_IDX
- RCVCC_MINI_PROD_IDX
- RCVCC_MODE
- RCVCC_MODE_ATTN_ENABLE
- RCVCC_MODE_ENABLE
- RCVCC_MODE_RESET
- RCVCC_STATUS
- RCVCC_STATUS_ERROR_ATTN
- RCVCC_STD_PROD_IDX
- RCVCTRL_COMMON_MODS
- RCVCTRL_PIBP
- RCVCTRL_PORT_MODS
- RCVD
- RCVDBDI_BD_PROD_IDX_0
- RCVDBDI_BD_PROD_IDX_1
- RCVDBDI_BD_PROD_IDX_10
- RCVDBDI_BD_PROD_IDX_11
- RCVDBDI_BD_PROD_IDX_12
- RCVDBDI_BD_PROD_IDX_13
- RCVDBDI_BD_PROD_IDX_14
- RCVDBDI_BD_PROD_IDX_15
- RCVDBDI_BD_PROD_IDX_2
- RCVDBDI_BD_PROD_IDX_3
- RCVDBDI_BD_PROD_IDX_4
- RCVDBDI_BD_PROD_IDX_5
- RCVDBDI_BD_PROD_IDX_6
- RCVDBDI_BD_PROD_IDX_7
- RCVDBDI_BD_PROD_IDX_8
- RCVDBDI_BD_PROD_IDX_9
- RCVDBDI_HWDIAG
- RCVDBDI_JUMBO_BD
- RCVDBDI_JUMBO_CON_IDX
- RCVDBDI_MINI_BD
- RCVDBDI_MINI_CON_IDX
- RCVDBDI_MODE
- RCVDBDI_MODE_ENABLE
- RCVDBDI_MODE_FRM_TOO_BIG
- RCVDBDI_MODE_INV_RING_SZ
- RCVDBDI_MODE_JUMBOBD_NEEDED
- RCVDBDI_MODE_LRG_RING_SZ
- RCVDBDI_MODE_RESET
- RCVDBDI_SPLIT_FRAME_MINSZ
- RCVDBDI_STATUS
- RCVDBDI_STATUS_FRM_TOO_BIG
- RCVDBDI_STATUS_INV_RING_SZ
- RCVDBDI_STATUS_JUMBOBD_NEEDED
- RCVDBDI_STD_BD
- RCVDBDI_STD_CON_IDX
- RCVDCC_MODE
- RCVDCC_MODE_ATTN_ENABLE
- RCVDCC_MODE_ENABLE
- RCVDCC_MODE_RESET
- RCVD_ACK_VAL
- RCVD_TRIGGER_VAL
- RCVE
- RCVENDM
- RCVERR_CHECK_TIME
- RCVFCSE
- RCVFC_MASK
- RCVFC_SH
- RCVFWU
- RCVFW_16
- RCVFW_32
- RCVFW_64
- RCVHQ_RCV_TYPE_EAGER
- RCVHQ_RCV_TYPE_ERROR
- RCVHQ_RCV_TYPE_EXPECTED
- RCVHQ_RCV_TYPE_NON_KD
- RCVID_SHIFT
- RCVINT
- RCVLPC_CONFIG
- RCVLPC_COS_CNTL_BASE
- RCVLPC_DMA_HIPRIO_WQ_FULL_CNT
- RCVLPC_DMA_WQ_FULL_CNT
- RCVLPC_DROP_FILTER_CNT
- RCVLPC_IN_DISCARDS_CNT
- RCVLPC_IN_ERRORS_CNT
- RCVLPC_LOCK
- RCVLPC_LOCK_GRANT_MASK
- RCVLPC_LOCK_GRANT_SHIFT
- RCVLPC_LOCK_REQ_MASK
- RCVLPC_LOCK_REQ_SHIFT
- RCVLPC_MODE
- RCVLPC_MODE_CLASS0_ATTN_ENAB
- RCVLPC_MODE_ENABLE
- RCVLPC_MODE_MAPOOR_AATTN_ENAB
- RCVLPC_MODE_RESET
- RCVLPC_MODE_STAT_OFLOW_ENAB
- RCVLPC_NON_EMPTY_BITS
- RCVLPC_NON_EMPTY_BITS_MASK
- RCVLPC_NO_RCV_BD_CNT
- RCVLPC_RCV_THRESH_HIT_CNT
- RCVLPC_SELLST_BASE
- RCVLPC_STATSCTRL
- RCVLPC_STATSCTRL_ENABLE
- RCVLPC_STATSCTRL_FASTUPD
- RCVLPC_STATSENAB_ASF_FIX
- RCVLPC_STATSENAB_DACK_FIX
- RCVLPC_STATSENAB_LNGBRST_RFIX
- RCVLPC_STATS_ENABLE
- RCVLPC_STATS_INCMASK
- RCVLPC_STATUS
- RCVLPC_STATUS_CLASS0
- RCVLPC_STATUS_MAPOOR
- RCVLPC_STATUS_STAT_OFLOW
- RCVLSC_MODE
- RCVLSC_MODE_ATTN_ENABLE
- RCVLSC_MODE_ENABLE
- RCVLSC_MODE_RESET
- RCVLSC_STATUS
- RCVLSC_STATUS_ERROR_ATTN
- RCVMODE_AUTO
- RCVMODE_DVBS
- RCVMODE_DVBS2
- RCVMODE_NONE
- RCVPKT_LENGTH
- RCVPOST_BUF_SIZE
- RCVR_DETECT
- RCVSET
- RCV_ALL
- RCV_ARRAY
- RCV_ARRAY_CNT
- RCV_ARRAY_RT_ADDR_MASK
- RCV_ARRAY_RT_ADDR_SHIFT
- RCV_ARRAY_RT_BUF_SIZE_SHIFT
- RCV_ARRAY_RT_WRITE_ENABLE_SMASK
- RCV_AUTO_DMA
- RCV_AVAIL_TIME_OUT
- RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK
- RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT
- RCV_BTH_QP
- RCV_BTH_QP_KDETH_QP_MASK
- RCV_BTH_QP_KDETH_QP_SHIFT
- RCV_BUFFER_SIZE
- RCV_BUFF_K_DA
- RCV_BUFF_K_DATA
- RCV_BUFF_K_DESCR
- RCV_BUFF_K_FC
- RCV_BUFF_K_PADDING
- RCV_BUFF_K_SA
- RCV_BUFF_RINGSIZE
- RCV_BUFF_SZ
- RCV_BUFSIZ_M
- RCV_BUFSIZ_MASK
- RCV_BUFSIZ_S
- RCV_BUFSIZ_V
- RCV_BUFS_DEF
- RCV_BUFS_MAX
- RCV_BUFS_MIN
- RCV_BUF_BLOCK_SIZE
- RCV_BUF_COUNT
- RCV_BUF_ERR
- RCV_BUF_OVFL_CNT
- RCV_BUF_UNITSZ
- RCV_BYPASS
- RCV_BYPASS_BYPASS_CONTEXT_MASK
- RCV_BYPASS_BYPASS_CONTEXT_SHIFT
- RCV_BYPASS_BYPASS_CONTEXT_SMASK
- RCV_BYPASS_HDR_SIZE_MASK
- RCV_BYPASS_HDR_SIZE_SHIFT
- RCV_BYPASS_HDR_SIZE_SMASK
- RCV_CONTEXTS
- RCV_CONTEXT_EGR_STALL
- RCV_COUNTER_ARRAY32
- RCV_COUNTER_ARRAY64
- RCV_COUNTS
- RCV_CRC
- RCV_CTRL
- RCV_CTRL_RCV_BYPASS_ENABLE_SMASK
- RCV_CTRL_RCV_EXTENDED_PSN_ENABLE_SMASK
- RCV_CTRL_RCV_PARTITION_KEY_ENABLE_SMASK
- RCV_CTRL_RCV_PORT_ENABLE_SMASK
- RCV_CTRL_RCV_QP_MAP_ENABLE_SMASK
- RCV_CTRL_RCV_RSM_ENABLE_SMASK
- RCV_CTRL_RX_RBUF_INIT_SMASK
- RCV_CTXT_CTRL
- RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK
- RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK
- RCV_CTXT_CTRL_EGR_BUF_SIZE_MASK
- RCV_CTXT_CTRL_EGR_BUF_SIZE_SHIFT
- RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK
- RCV_CTXT_CTRL_ENABLE_SMASK
- RCV_CTXT_CTRL_INTR_AVAIL_SMASK
- RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK
- RCV_CTXT_CTRL_TAIL_UPD_SMASK
- RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK
- RCV_CTXT_STATUS
- RCV_DATA_PKT_CNT
- RCV_DESC_RINGSIZE
- RCV_DMA
- RCV_DMA_ALL
- RCV_DONG
- RCV_DROP
- RCV_DROP0
- RCV_DWORD_CNT
- RCV_EBP_CNT
- RCV_EGRBUF
- RCV_EGR_CTRL
- RCV_EGR_CTRL_EGR_BASE_INDEX_MASK
- RCV_EGR_CTRL_EGR_BASE_INDEX_SHIFT
- RCV_EGR_CTRL_EGR_CNT_MASK
- RCV_EGR_CTRL_EGR_CNT_SHIFT
- RCV_EGR_INDEX_HEAD
- RCV_EGR_INDEX_HEAD_HEAD_MASK
- RCV_EGR_INDEX_HEAD_HEAD_SHIFT
- RCV_ELS_REQ
- RCV_ELS_REQ64
- RCV_EN
- RCV_END
- RCV_ERR
- RCV_ERR_CLEAR
- RCV_ERR_INFO
- RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SC_SMASK
- RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK
- RCV_ERR_MASK
- RCV_ERR_PRN
- RCV_ERR_STATUS
- RCV_ERR_STATUS_RX_CSR_PARITY_ERR_SMASK
- RCV_ERR_STATUS_RX_CSR_READ_BAD_ADDR_ERR_SMASK
- RCV_ERR_STATUS_RX_CSR_WRITE_BAD_ADDR_ERR_SMASK
- RCV_ERR_STATUS_RX_DC_INTF_PARITY_ERR_SMASK
- RCV_ERR_STATUS_RX_DC_SOP_EOP_PARITY_ERR_SMASK
- RCV_ERR_STATUS_RX_DMA_CSR_COR_ERR_SMASK
- RCV_ERR_STATUS_RX_DMA_CSR_PARITY_ERR_SMASK
- RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK
- RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_COR_ERR_SMASK
- RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK
- RCV_ERR_STATUS_RX_DMA_DQ_FSM_ENCODING_ERR_SMASK
- RCV_ERR_STATUS_RX_DMA_EQ_FSM_ENCODING_ERR_SMASK
- RCV_ERR_STATUS_RX_DMA_FLAG_COR_ERR_SMASK
- RCV_ERR_STATUS_RX_DMA_FLAG_UNC_ERR_SMASK
- RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_COR_ERR_SMASK
- RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK
- RCV_ERR_STATUS_RX_HQ_INTR_CSR_PARITY_ERR_SMASK
- RCV_ERR_STATUS_RX_HQ_INTR_FSM_ERR_SMASK
- RCV_ERR_STATUS_RX_LOOKUP_CSR_PARITY_ERR_SMASK
- RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_COR_ERR_SMASK
- RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_ERR_SMASK
- RCV_ERR_STATUS_RX_LOOKUP_DES_PART2_PARITY_ERR_SMASK
- RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_COR_ERR_SMASK
- RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_UNC_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_BAD_LOOKUP_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_COR_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_UNC_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_CSR_QENT_CNT_PARITY_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_CSR_QEOPDW_PARITY_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_CSR_QHD_PTR_PARITY_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_CSR_QHEAD_BUF_NUM_PARITY_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_CSR_QNEXT_BUF_PARITY_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_CSR_QNUM_OF_PKT_PARITY_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_CSR_QTL_PTR_PARITY_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_CSR_QVLD_BIT_PARITY_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_CTX_ID_PARITY_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_DATA_COR_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_DATA_UNC_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_DESC_PART1_COR_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_DESC_PART1_UNC_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_DESC_PART2_COR_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_DESC_PART2_UNC_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_EMPTY_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_FL_INITDONE_PARITY_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_FL_RD_ADDR_PARITY_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_FL_WR_ADDR_PARITY_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_FREE_LIST_COR_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_FREE_LIST_UNC_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_FULL_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_COR_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_UNC_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_COR_ERR_SMASK
- RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_UNC_ERR_SMASK
- RCV_ERR_STATUS_RX_RCV_CSR_PARITY_ERR_SMASK
- RCV_ERR_STATUS_RX_RCV_DATA_COR_ERR_SMASK
- RCV_ERR_STATUS_RX_RCV_DATA_UNC_ERR_SMASK
- RCV_ERR_STATUS_RX_RCV_FSM_ENCODING_ERR_SMASK
- RCV_ERR_STATUS_RX_RCV_HDR_COR_ERR_SMASK
- RCV_ERR_STATUS_RX_RCV_HDR_UNC_ERR_SMASK
- RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_COR_ERR_SMASK
- RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_UNC_ERR_SMASK
- RCV_FIXED_DATA
- RCV_FRAG_LEN
- RCV_FRAM
- RCV_HDRQ
- RCV_HDR_ADDR
- RCV_HDR_CNT
- RCV_HDR_CNT_CNT_MASK
- RCV_HDR_CNT_CNT_SHIFT
- RCV_HDR_ENT_SIZE
- RCV_HDR_ENT_SIZE_ENT_SIZE_MASK
- RCV_HDR_ENT_SIZE_ENT_SIZE_SHIFT
- RCV_HDR_HEAD
- RCV_HDR_HEAD_COUNTER_MASK
- RCV_HDR_HEAD_COUNTER_SHIFT
- RCV_HDR_HEAD_HEAD_MASK
- RCV_HDR_HEAD_HEAD_SHIFT
- RCV_HDR_HEAD_HEAD_SMASK
- RCV_HDR_OVFL_CNT
- RCV_HDR_SIZE
- RCV_HDR_SIZE_HDR_SIZE_MASK
- RCV_HDR_SIZE_HDR_SIZE_SHIFT
- RCV_HDR_TAIL
- RCV_HDR_TAIL_ADDR
- RCV_ICRC_ERR_CNT
- RCV_INCREMENT
- RCV_INT
- RCV_IO
- RCV_ISQ
- RCV_KEY_CTRL
- RCV_KEY_CTRL_JOB_KEY_ENABLE_SMASK
- RCV_KEY_CTRL_JOB_KEY_VALUE_MASK
- RCV_KEY_CTRL_JOB_KEY_VALUE_SHIFT
- RCV_LAZY_FC_MASK
- RCV_LAZY_FC_SHIFT
- RCV_LAZY_TO_MASK
- RCV_LENGTH_ERR_CNT
- RCV_MEMORY
- RCV_MULTICAST
- RCV_MUX_MASK
- RCV_MUX_MUTE
- RCV_MUX_OPEN
- RCV_MUX_TEST_MODE
- RCV_MUX_VOICE_PLAYBACK
- RCV_NOBUF
- RCV_OFLO
- RCV_OWN
- RCV_PARANOIA_CHECK
- RCV_PARTITION_KEY
- RCV_PARTITION_KEY_PARTITION_KEY_A_MASK
- RCV_PARTITION_KEY_PARTITION_KEY_B_SHIFT
- RCV_PKT_DONE
- RCV_PKT_LIMIT
- RCV_PKT_OK
- RCV_POLLING
- RCV_PONG
- RCV_QP_MAP_TABLE
- RCV_RING_BASE_ADDR0
- RCV_RING_JUMBO
- RCV_RING_LEN0
- RCV_RING_LRO
- RCV_RING_NORMAL
- RCV_RSM_CFG
- RCV_RSM_CFG_ENABLE_OR_CHAIN_RSM0_MASK
- RCV_RSM_CFG_ENABLE_OR_CHAIN_RSM0_SHIFT
- RCV_RSM_CFG_OFFSET_SHIFT
- RCV_RSM_CFG_PACKET_TYPE_SHIFT
- RCV_RSM_MAP_TABLE
- RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK
- RCV_RSM_MATCH
- RCV_RSM_MATCH_MASK1_SHIFT
- RCV_RSM_MATCH_MASK2_SHIFT
- RCV_RSM_MATCH_VALUE1_SHIFT
- RCV_RSM_MATCH_VALUE2_SHIFT
- RCV_RSM_SELECT
- RCV_RSM_SELECT_FIELD1_OFFSET_SHIFT
- RCV_RSM_SELECT_FIELD2_OFFSET_SHIFT
- RCV_RSM_SELECT_INDEX1_OFFSET_SHIFT
- RCV_RSM_SELECT_INDEX1_WIDTH_SHIFT
- RCV_RSM_SELECT_INDEX2_OFFSET_SHIFT
- RCV_RSM_SELECT_INDEX2_WIDTH_SHIFT
- RCV_RULE_CFG_DEFAULT_CLASS
- RCV_RULE_DISABLE_MASK
- RCV_SCE
- RCV_SEQ_FIELDS64
- RCV_SHIFT
- RCV_SHORT_ERR_CNT
- RCV_SHUTDOWN
- RCV_SKB_FAIL
- RCV_START
- RCV_STATUS
- RCV_STATUS_RX_PKT_IN_PROGRESS_SMASK
- RCV_STATUS_RX_RBUF_INIT_DONE_SMASK
- RCV_STATUS_RX_RBUF_PKT_PENDING_SMASK
- RCV_TEMP_READINGS
- RCV_TID_CTRL
- RCV_TID_CTRL_TID_BASE_INDEX_MASK
- RCV_TID_CTRL_TID_BASE_INDEX_SHIFT
- RCV_TID_CTRL_TID_PAIR_CNT_MASK
- RCV_TID_CTRL_TID_PAIR_CNT_SHIFT
- RCV_TID_FLOW_GEN_MISMATCH_CNT
- RCV_TID_FLOW_SEQ_MISMATCH_CNT
- RCV_TID_FLOW_TABLE
- RCV_TID_FLOW_TABLE_CTRL_FLOW_VALID_SMASK
- RCV_TID_FLOW_TABLE_CTRL_HDR_SUPP_EN_SMASK
- RCV_TID_FLOW_TABLE_CTRL_KEEP_AFTER_SEQ_ERR_SMASK
- RCV_TID_FLOW_TABLE_CTRL_KEEP_ON_GEN_ERR_SMASK
- RCV_TID_FLOW_TABLE_STATUS_GEN_MISMATCH_SMASK
- RCV_TID_FLOW_TABLE_STATUS_SEQ_MISMATCH_SMASK
- RCV_TID_FULL_ERR_CNT
- RCV_TID_VALID_ERR_CNT
- RCV_VIA_SKB
- RCV_VL15
- RCV_WITH_RXON
- RCV_WSCALE
- RCWAKERW
- RCWSR7_FM1_CLK_SEL
- RCWSR7_FM2_CLK_SEL
- RCWSR7_HWA_ASYNC_DIV
- RCW_PCI_HOST
- RCX
- RCX_SW_EXIT
- RC_AGAIN
- RC_BAR_CONFIG
- RC_BIT_MODEL_TOTAL
- RC_BIT_MODEL_TOTAL_BITS
- RC_BPG_OFFSET_SHIFT
- RC_CHK
- RC_CHOP
- RC_CONFIG
- RC_CONTROL_CONFIG
- RC_CSUMLEN
- RC_DEV_MAX
- RC_DOIT
- RC_DONE
- RC_DOWN
- RC_DRIVER_IR_RAW
- RC_DRIVER_IR_RAW_TX
- RC_DRIVER_SCANCODE
- RC_DROPIT
- RC_EXPIRE
- RC_FILTER_ATTR
- RC_FILTER_MAX
- RC_FILTER_NORMAL
- RC_FILTER_WAKEUP
- RC_FLAGS_AAL5
- RC_FLAGS_BFPP
- RC_FLAGS_BFPS
- RC_FLAGS_BFPS_BFP
- RC_FLAGS_BFPS_BFP0
- RC_FLAGS_BFPS_BFP01
- RC_FLAGS_BFPS_BFP07
- RC_FLAGS_BFPS_BFP1
- RC_FLAGS_BFPS_BFP2
- RC_FLAGS_BFPS_BFP23
- RC_FLAGS_BFPS_BFP27
- RC_FLAGS_BFPS_BFP3
- RC_FLAGS_BFPS_BFP4
- RC_FLAGS_BFPS_BFP45
- RC_FLAGS_BFPS_BFP47
- RC_FLAGS_BFPS_BFP5
- RC_FLAGS_BFPS_BFP6
- RC_FLAGS_BFPS_BFP67
- RC_FLAGS_BFPS_BFP7
- RC_FLAGS_CRC10
- RC_FLAGS_HOAM
- RC_FLAGS_ML
- RC_FLAGS_NAM
- RC_FLAGS_PRI
- RC_FLAGS_RXBM_CIF
- RC_FLAGS_RXBM_PMB
- RC_FLAGS_RXBM_POS
- RC_FLAGS_RXBM_PSB
- RC_FLAGS_RXBM_SAF
- RC_FLAGS_RXBM_STR
- RC_FLAGS_TEP
- RC_FLAGS_TEVC
- RC_FLAGS_TRANSC
- RC_FLAGS_TRANSP
- RC_FLAGS_TRBRM
- RC_FTC_ECC_DB_ERR
- RC_FTC_ECC_SG_ERR
- RC_FTC_SM_ERR_ALARM
- RC_INCORRECT_LUN
- RC_INIT_BYTES
- RC_INPROG
- RC_INVALID_INFO_UNIT
- RC_MAP_ADSTECH_DVB_T_PCI
- RC_MAP_ALINK_DTU_M
- RC_MAP_ANYSEE
- RC_MAP_APAC_VIEWCOMP
- RC_MAP_ASTROMETA_T2HYBRID
- RC_MAP_ASUS_PC39
- RC_MAP_ASUS_PS3_100
- RC_MAP_ATI_TV_WONDER_HD_600
- RC_MAP_ATI_X10
- RC_MAP_AVERMEDIA
- RC_MAP_AVERMEDIA_A16D
- RC_MAP_AVERMEDIA_CARDBUS
- RC_MAP_AVERMEDIA_DVBT
- RC_MAP_AVERMEDIA_M135A
- RC_MAP_AVERMEDIA_M733A_RM_K6
- RC_MAP_AVERMEDIA_RM_KS
- RC_MAP_AVERTV_303
- RC_MAP_AZUREWAVE_AD_TU700
- RC_MAP_BEHOLD
- RC_MAP_BEHOLD_COLUMBUS
- RC_MAP_BUDGET_CI_OLD
- RC_MAP_CEC
- RC_MAP_CINERGY
- RC_MAP_CINERGY_1400
- RC_MAP_D680_DMB
- RC_MAP_DELOCK_61959
- RC_MAP_DIB0700_NEC_TABLE
- RC_MAP_DIB0700_RC5_TABLE
- RC_MAP_DIGITALNOW_TINYTWIN
- RC_MAP_DIGITTRADE
- RC_MAP_DM1105_NEC
- RC_MAP_DNTV_LIVE_DVBT_PRO
- RC_MAP_DNTV_LIVE_DVB_T
- RC_MAP_DTT200U
- RC_MAP_DVBSKY
- RC_MAP_DVICO_MCE
- RC_MAP_DVICO_PORTABLE
- RC_MAP_EMPTY
- RC_MAP_EM_TERRATEC
- RC_MAP_ENCORE_ENLTV
- RC_MAP_ENCORE_ENLTV2
- RC_MAP_ENCORE_ENLTV_FM53
- RC_MAP_EVGA_INDTUBE
- RC_MAP_EZTV
- RC_MAP_FLYDVB
- RC_MAP_FLYVIDEO
- RC_MAP_FUSIONHDTV_MCE
- RC_MAP_GADMEI_RM008Z
- RC_MAP_GEEKBOX
- RC_MAP_GENIUS_TVGO_A11MCE
- RC_MAP_GOTVIEW7135
- RC_MAP_HAUPPAUGE
- RC_MAP_HAUPPAUGE_NEW
- RC_MAP_HISI_POPLAR
- RC_MAP_HISI_TV_DEMO
- RC_MAP_IMON_MCE
- RC_MAP_IMON_PAD
- RC_MAP_IMON_RSC
- RC_MAP_IODATA_BCTV7E
- RC_MAP_IT913X_V1
- RC_MAP_IT913X_V2
- RC_MAP_KAIOMY
- RC_MAP_KHADAS
- RC_MAP_KII_PRO
- RC_MAP_KWORLD_315U
- RC_MAP_KWORLD_PC150U
- RC_MAP_KWORLD_PLUS_TV_ANALOG
- RC_MAP_LEADTEK_Y04G0051
- RC_MAP_LME2510
- RC_MAP_MANLI
- RC_MAP_MEDION_X10
- RC_MAP_MEDION_X10_DIGITAINER
- RC_MAP_MEDION_X10_OR2X
- RC_MAP_MSI_DIGIVOX_II
- RC_MAP_MSI_DIGIVOX_III
- RC_MAP_MSI_TVANYWHERE
- RC_MAP_MSI_TVANYWHERE_PLUS
- RC_MAP_NEBULA
- RC_MAP_NEC_TERRATEC_CINERGY_XS
- RC_MAP_NORWOOD
- RC_MAP_NPGTECH
- RC_MAP_ODROID
- RC_MAP_PCTV_SEDNA
- RC_MAP_PINNACLE_COLOR
- RC_MAP_PINNACLE_GREY
- RC_MAP_PINNACLE_PCTV_HD
- RC_MAP_PIXELVIEW
- RC_MAP_PIXELVIEW_002T
- RC_MAP_PIXELVIEW_MK12
- RC_MAP_PIXELVIEW_NEW
- RC_MAP_POWERCOLOR_REAL_ANGEL
- RC_MAP_PROTEUS_2309
- RC_MAP_PURPLETV
- RC_MAP_PV951
- RC_MAP_RC5_TV
- RC_MAP_RC6_MCE
- RC_MAP_REAL_AUDIO_220_32_KEYS
- RC_MAP_REDDO
- RC_MAP_SNAPSTREAM_FIREFLY
- RC_MAP_STREAMZAP
- RC_MAP_SU3000
- RC_MAP_TANGO
- RC_MAP_TANIX_TX3MINI
- RC_MAP_TANIX_TX5MAX
- RC_MAP_TBS_NEC
- RC_MAP_TECHNISAT_TS35
- RC_MAP_TECHNISAT_USB2
- RC_MAP_TERRATEC_CINERGY_C_PCI
- RC_MAP_TERRATEC_CINERGY_S2_HD
- RC_MAP_TERRATEC_CINERGY_XS
- RC_MAP_TERRATEC_SLIM
- RC_MAP_TERRATEC_SLIM_2
- RC_MAP_TEVII_NEC
- RC_MAP_TIVO
- RC_MAP_TOTAL_MEDIA_IN_HAND
- RC_MAP_TOTAL_MEDIA_IN_HAND_02
- RC_MAP_TREKSTOR
- RC_MAP_TT_1500
- RC_MAP_TWINHAN_DTV_CAB_CI
- RC_MAP_TWINHAN_VP1027_DVBS
- RC_MAP_VIDEOMATE_K100
- RC_MAP_VIDEOMATE_S350
- RC_MAP_VIDEOMATE_TV_PVR
- RC_MAP_WETEK_HUB
- RC_MAP_WETEK_PLAY2
- RC_MAP_WINFAST
- RC_MAP_WINFAST_USBII_DELUXE
- RC_MAP_X96MAX
- RC_MAP_XBOX_DVD
- RC_MAP_ZX_IRDEC
- RC_MAX_QP_SHIFT
- RC_MIN_QP_SHIFT
- RC_MODEL_TOTAL_BITS
- RC_MOVE_BITS
- RC_MSG_SIZE_V1_20
- RC_NOCACHE
- RC_NO_KEY
- RC_OP
- RC_OP_FLUSH_ENABLE
- RC_OVERLAPPED_TAG
- RC_PCIE_RST_OUTPUT
- RC_PCIE_RST_OUTPUT_SHIFT
- RC_PENDOWN
- RC_PENUP
- RC_PRCn_ECC_DB_ERR
- RC_PRCn_ECC_SG_ERR
- RC_PRCn_SM_ERR_ALARM
- RC_PROTO_BIT_ALL_IR_DECODER
- RC_PROTO_BIT_ALL_IR_ENCODER
- RC_PROTO_BIT_CEC
- RC_PROTO_BIT_IMON
- RC_PROTO_BIT_JVC
- RC_PROTO_BIT_MCIR2_KBD
- RC_PROTO_BIT_MCIR2_MSE
- RC_PROTO_BIT_NEC
- RC_PROTO_BIT_NEC32
- RC_PROTO_BIT_NECX
- RC_PROTO_BIT_NONE
- RC_PROTO_BIT_OTHER
- RC_PROTO_BIT_RC5
- RC_PROTO_BIT_RC5X_20
- RC_PROTO_BIT_RC5_SZ
- RC_PROTO_BIT_RC6_0
- RC_PROTO_BIT_RC6_6A_20
- RC_PROTO_BIT_RC6_6A_24
- RC_PROTO_BIT_RC6_6A_32
- RC_PROTO_BIT_RC6_MCE
- RC_PROTO_BIT_RCMM12
- RC_PROTO_BIT_RCMM24
- RC_PROTO_BIT_RCMM32
- RC_PROTO_BIT_SANYO
- RC_PROTO_BIT_SHARP
- RC_PROTO_BIT_SONY12
- RC_PROTO_BIT_SONY15
- RC_PROTO_BIT_SONY20
- RC_PROTO_BIT_UNKNOWN
- RC_PROTO_BIT_XBOX_DVD
- RC_PROTO_BIT_XMP
- RC_PROTO_CEC
- RC_PROTO_IMON
- RC_PROTO_JVC
- RC_PROTO_MCIR2_KBD
- RC_PROTO_MCIR2_MSE
- RC_PROTO_NEC
- RC_PROTO_NEC32
- RC_PROTO_NECX
- RC_PROTO_OTHER
- RC_PROTO_RC5
- RC_PROTO_RC5X_20
- RC_PROTO_RC5_SZ
- RC_PROTO_RC6_0
- RC_PROTO_RC6_6A_20
- RC_PROTO_RC6_6A_24
- RC_PROTO_RC6_6A_32
- RC_PROTO_RC6_MCE
- RC_PROTO_RCMM12
- RC_PROTO_RCMM24
- RC_PROTO_RCMM32
- RC_PROTO_SANYO
- RC_PROTO_SHARP
- RC_PROTO_SONY12
- RC_PROTO_SONY15
- RC_PROTO_SONY20
- RC_PROTO_UNKNOWN
- RC_PROTO_XBOX_DVD
- RC_PROTO_XMP
- RC_QP_SCALING_INTERVAL
- RC_RDA_FAIL_WR_Rn
- RC_RDY
- RC_REGION_0_ADDR_TRANS_H
- RC_REGION_0_ADDR_TRANS_L
- RC_REGION_0_PASS_BITS
- RC_REGION_0_TYPE_MASK
- RC_REPEAT_DELAY
- RC_REPLBUFF
- RC_REPLSTAT
- RC_REPLY
- RC_RND
- RC_SCANCODE_NEC
- RC_SCANCODE_NEC32
- RC_SCANCODE_NECX
- RC_SCANCODE_OTHER
- RC_SCANCODE_RC5
- RC_SCANCODE_RC5_SZ
- RC_SCANCODE_RC6_0
- RC_SCANCODE_RC6_6A
- RC_SCANCODE_UNKNOWN
- RC_SHIFT_BITS
- RC_STATUS_IDLE
- RC_STATUS_MASK
- RC_STATUS_MEAS
- RC_STATUS_PHY_RDY
- RC_STATUS_RX
- RC_STATUS_TX
- RC_SW_TARGET_STATE_MASK
- RC_SW_TARGET_STATE_SHIFT
- RC_TMF_COMPLETE
- RC_TMF_FAILED
- RC_TMF_NOT_SUPPORTED
- RC_TMF_SUCCEEDED
- RC_TOP_BITS
- RC_TOP_VALUE
- RC_UNUSED
- RC_UP
- RC_UT_MODE
- RC_VALID
- RC_VAL_READ
- RC_VOP_TIMING
- RClut
- RCmd_ClearRxCRC
- RCmd_EnterHuntmode
- RCmd_Null
- RCmd_SelectRicrIntLevel
- RCmd_SelectRicrRtsaData
- RCmd_SelectRicrRxFifostatus
- RCmd_SelectRicrdma_level
- RD
- RD1
- RD2
- RD88F5181L_FXO_NOR_BOOT_BASE
- RD88F5181L_FXO_NOR_BOOT_SIZE
- RD88F5181L_GE_NOR_BOOT_BASE
- RD88F5181L_GE_NOR_BOOT_SIZE
- RD88F5182_GPIO_LED
- RD88F5182_NOR_BASE
- RD88F5182_NOR_BOOT_BASE
- RD88F5182_NOR_BOOT_SIZE
- RD88F5182_NOR_SIZE
- RD88F5182_PCI_SLOT0_IRQ_A_PIN
- RD88F5182_PCI_SLOT0_IRQ_B_PIN
- RD88F5182_PCI_SLOT0_OFFS
- RDA
- RDAC2LCH
- RDAC2MONOMIX
- RDAC2RCH
- RDAC_FORCED_QUIESENCE
- RDAC_LOG
- RDAC_LOG_BITS
- RDAC_LOG_FAILOVER
- RDAC_LOG_LEVEL
- RDAC_LOG_SENSE
- RDAC_LUN_OWNED
- RDAC_LUN_UNOWNED
- RDAC_MODE
- RDAC_MODE_AVT
- RDAC_MODE_IOSHIP
- RDAC_MODE_TRANSFER_SPECIFIED_LUNS
- RDAC_NAME
- RDAC_NON_PREFERRED
- RDAC_PAGE_CODE_REDUNDANT_CONTROLLER
- RDAC_PREFERRED
- RDAC_PWR_ON
- RDAC_QUIESCENCE_TIME
- RDAC_RETRIES
- RDAC_RETRY_COUNT
- RDAC_STATE_ACTIVE
- RDAC_STATE_PASSIVE
- RDAC_TIMEOUT
- RDAC_VOL
- RDAR1
- RDATA
- RDATAQ
- RDATASIZE
- RDATDLY
- RDAYAR
- RDAYCNT
- RDA_FRM_ECC_DB_N_AERR
- RDA_FRM_ECC_SG_ERR
- RDA_HWTIMER_LOCKVAL_H
- RDA_HWTIMER_LOCKVAL_L
- RDA_INTC_FINALSTATUS
- RDA_INTC_MASK_CLR
- RDA_INTC_MASK_SET
- RDA_IRQ_MASK_ALL
- RDA_MISC_ERR
- RDA_NR_IRQS
- RDA_OSTIMER_CTRL
- RDA_OSTIMER_CTRL_ENABLE
- RDA_OSTIMER_CTRL_LOAD
- RDA_OSTIMER_CTRL_REPEAT
- RDA_OSTIMER_LOADVAL_L
- RDA_PCIX_ERR
- RDA_RXD_ECC_DB_SERR
- RDA_RXDn_ECC_DB_ERR
- RDA_RXDn_ECC_SG_ERR
- RDA_SM0_ERR_ALARM
- RDA_SM1_ERR_ALARM
- RDA_TIMER_IRQ_CLR
- RDA_TIMER_IRQ_CLR_OSTIMER
- RDA_TIMER_IRQ_MASK_CLR
- RDA_TIMER_IRQ_MASK_OSTIMER
- RDA_TIMER_IRQ_MASK_SET
- RDA_UART_AFC_LEVEL
- RDA_UART_CLK_ENABLED
- RDA_UART_CMD_CLR
- RDA_UART_CMD_SET
- RDA_UART_CONSOLE
- RDA_UART_CTRL
- RDA_UART_CTS
- RDA_UART_DBITS_8
- RDA_UART_DCD
- RDA_UART_DCTS
- RDA_UART_DEV_NAME
- RDA_UART_DIV_MODE
- RDA_UART_DMA_EN
- RDA_UART_DSR
- RDA_UART_DTR
- RDA_UART_DTR_FALL
- RDA_UART_DTR_FALL_U
- RDA_UART_DTR_RISE
- RDA_UART_DTR_RISE_U
- RDA_UART_ENABLE
- RDA_UART_FLOW_CNT_EN
- RDA_UART_IRDA_EN
- RDA_UART_IRQ_CAUSE
- RDA_UART_IRQ_MASK
- RDA_UART_IRQ_TRIGGERS
- RDA_UART_LOOP_BACK_EN
- RDA_UART_PARITY
- RDA_UART_PARITY_EN
- RDA_UART_PARITY_EVEN
- RDA_UART_PARITY_MARK
- RDA_UART_PARITY_ODD
- RDA_UART_PARITY_SPACE
- RDA_UART_PORT_NUM
- RDA_UART_RI
- RDA_UART_RTS
- RDA_UART_RXTX_BUFFER
- RDA_UART_RX_ACTIVE
- RDA_UART_RX_BREAK_INT
- RDA_UART_RX_BREAK_LEN
- RDA_UART_RX_DATA
- RDA_UART_RX_DATA_AVAILABLE
- RDA_UART_RX_DATA_AVAILABLE_U
- RDA_UART_RX_DMA_DONE
- RDA_UART_RX_DMA_DONE_U
- RDA_UART_RX_DMA_TIMEOUT
- RDA_UART_RX_DMA_TIMEOUT_U
- RDA_UART_RX_FIFO
- RDA_UART_RX_FIFO_MASK
- RDA_UART_RX_FIFO_RESET
- RDA_UART_RX_FRAMING_ERR
- RDA_UART_RX_LINE_ERR
- RDA_UART_RX_LINE_ERR_U
- RDA_UART_RX_LOCK_ERR
- RDA_UART_RX_OVERFLOW_ERR
- RDA_UART_RX_PARITY_ERR
- RDA_UART_RX_TIMEOUT
- RDA_UART_RX_TIMEOUT_U
- RDA_UART_RX_TRIGGER
- RDA_UART_STATUS
- RDA_UART_TX_ACTIVE
- RDA_UART_TX_BREAK_CONTROL
- RDA_UART_TX_DATA
- RDA_UART_TX_DATA_NEEDED
- RDA_UART_TX_DATA_NEEDED_U
- RDA_UART_TX_DMA_DONE
- RDA_UART_TX_DMA_DONE_U
- RDA_UART_TX_FIFO
- RDA_UART_TX_FIFO_MASK
- RDA_UART_TX_FIFO_RESET
- RDA_UART_TX_FIFO_SIZE
- RDA_UART_TX_FINISH_N_WAIT
- RDA_UART_TX_MODEM_STATUS
- RDA_UART_TX_MODEM_STATUS_U
- RDA_UART_TX_OVERFLOW_ERR
- RDA_UART_TX_SBITS_2
- RDA_UART_TX_TRIGGER
- RDBG
- RDBNUM_MASK
- RDBNUM_SHIFT
- RDBSIZE_MASK
- RDBSIZE_SHIFT
- RDB_ALLOCATION_LIMIT
- RDC321X_GPIO_CTRL_REG1
- RDC321X_GPIO_CTRL_REG2
- RDC321X_GPIO_DATA_REG1
- RDC321X_GPIO_DATA_REG2
- RDC321X_NUM_GPIO
- RDC321X_WDT_CTRL
- RDCON
- RDCR
- RDCRB
- RDCSR
- RDCTL
- RDC_8820_INT
- RDC_8820_PIO_0_DISABLE
- RDC_8820_PIO_0_ENABLE
- RDC_8820_RESET
- RDC_CLS_TMR
- RDC_RED_PARA
- RDC_RED_PARA_THRE
- RDC_RED_PARA_THRE_SHIFT
- RDC_RED_PARA_THRE_SYN
- RDC_RED_PARA_THRE_SYN_SHIFT
- RDC_RED_PARA_WIN
- RDC_RED_PARA_WIN_SHIFT
- RDC_RED_PARA_WIN_SYN
- RDC_RED_PARA_WIN_SYN_SHIFT
- RDC_TBL
- RDC_TBL_RDC
- RDC_WDT_CNT
- RDC_WDT_EN
- RDC_WDT_INTERVAL
- RDC_WDT_IRT
- RDC_WDT_MASK
- RDC_WDT_RST
- RDC_WDT_WIF
- RDC_WDT_WTI
- RDDAR
- RDDATA
- RDDATAflag
- RDD_CAC_END
- RDD_CAC_START
- RDD_DET_MODE
- RDD_DET_STOP
- RDD_DISABLE_DFS_CAL
- RDD_NORMAL_START
- RDD_PULSE_DBG
- RDD_READ_PULSE
- RDD_RESUME_BF
- RDD_START
- RDD_STOP
- RDEE
- RDEND
- RDEP
- RDEP_MONT_DEAR
- RDEP_MONT_ETB
- RDEP_MONT_IEAR
- RDERR_ADDR_OFF
- RDERR_INT_ENABLE
- RDES0_COLLISION
- RDES0_COLLISION_SEEN_
- RDES0_CRC_ERROR
- RDES0_CRC_ERROR_
- RDES0_DA_FILTER_FAIL
- RDES0_DESCRIPTOR_ERROR
- RDES0_DESCRIPTOR_ERROR_
- RDES0_DRIBBLING
- RDES0_DRIBBLING_BIT_
- RDES0_ERROR_SUMMARY
- RDES0_ERROR_SUMMARY_
- RDES0_FIRST_DESCRIPTOR
- RDES0_FIRST_DESCRIPTOR_
- RDES0_FRAME_LENGTH_MASK_
- RDES0_FRAME_LENGTH_SHFT_
- RDES0_FRAME_LEN_MASK
- RDES0_FRAME_LEN_SHIFT
- RDES0_FRAME_TOO_LONG_
- RDES0_FRAME_TYPE
- RDES0_FRAME_TYPE_
- RDES0_IPC_CSUM_ERROR
- RDES0_LAST_DESCRIPTOR
- RDES0_LAST_DESCRIPTOR_
- RDES0_LENGTH_ERROR
- RDES0_LENGTH_ERROR_
- RDES0_MII_ERROR
- RDES0_MII_ERROR_
- RDES0_MULTICAST_FRAME_
- RDES0_OVERFLOW_ERROR
- RDES0_OWN
- RDES0_OWN_
- RDES0_PAYLOAD_CSUM_ERR
- RDES0_RECEIVE_WATCHDOG
- RDES0_RUNT_FRAME_
- RDES0_SA_FILTER_FAIL
- RDES0_STATUS_CRC16E
- RDES0_STATUS_CRC32E
- RDES0_STATUS_DA0
- RDES0_STATUS_DA1
- RDES0_STATUS_DE
- RDES0_STATUS_ES
- RDES0_STATUS_FL
- RDES0_STATUS_FS
- RDES0_STATUS_ICVE
- RDES0_STATUS_LS
- RDES0_STATUS_OWN
- RDES0_STATUS_PCF
- RDES0_STATUS_RXDR
- RDES0_STATUS_RXTOE
- RDES0_STATUS_SFDE
- RDES0_STATUS_SIGE
- RDES0_STATUS_SQL
- RDES0_VLAN_TAG
- RDES0_VLAN_TAG_MASK
- RDES0_WATCHDOG_TIMEOUT_
- RDES1_BUFFER1_SIZE_MASK
- RDES1_BUFFER2_SIZE_MASK
- RDES1_BUFFER2_SIZE_SHIFT
- RDES1_CONTROL_RBS1
- RDES1_CONTROL_RBS2
- RDES1_CONTROL_RCH
- RDES1_CONTROL_RER
- RDES1_DISABLE_IC
- RDES1_END_RING
- RDES1_IPV4_HEADER
- RDES1_IPV6_HEADER
- RDES1_IP_CSUM_BYPASSED
- RDES1_IP_CSUM_ERROR
- RDES1_IP_HDR_ERROR
- RDES1_IP_PAYLOAD_TYPE_MASK
- RDES1_IP_TYPE1_CSUM_MASK
- RDES1_PTP_MSG_TYPE_MASK
- RDES1_PTP_PACKET_TYPE
- RDES1_PTP_VER
- RDES1_RER_
- RDES1_SECOND_ADDRESS_CHAINED
- RDES1_STATUS_RSSI
- RDES1_TIMESTAMP_AVAILABLE
- RDES1_TIMESTAMP_AVAILABLE_SHIFT
- RDES1_TIMESTAMP_DROPPED
- RDES2_DA_FILTER_FAIL
- RDES2_HASH_FILTER_STATUS
- RDES2_HASH_VALUE_MATCH_MASK
- RDES2_L3_FILTER_MATCH
- RDES2_L3_L4_FILT_NB_MATCH_MASK
- RDES2_L3_L4_FILT_NB_MATCH_SHIFT
- RDES2_L3_L4_HEADER_SIZE_MASK
- RDES2_L4_FILTER_MATCH
- RDES2_MAC_ADDR_MATCH_MASK
- RDES2_SA_FILTER_FAIL
- RDES2_VLAN_FILTER_STATUS
- RDES3_BUFFER1_VALID_ADDR
- RDES3_BUFFER2_VALID_ADDR
- RDES3_CONTEXT_DESCRIPTOR
- RDES3_CONTEXT_DESCRIPTOR_SHIFT
- RDES3_CRC_ERROR
- RDES3_DRIBBLE_ERROR
- RDES3_ERROR_SUMMARY
- RDES3_FIRST_DESCRIPTOR
- RDES3_GIANT_PACKET
- RDES3_INT_ON_COMPLETION_EN
- RDES3_LAST_DESCRIPTOR
- RDES3_OVERFLOW_ERROR
- RDES3_OWN
- RDES3_PACKET_LEN_TYPE_MASK
- RDES3_PACKET_SIZE_MASK
- RDES3_RDES0_VALID
- RDES3_RDES1_VALID
- RDES3_RDES2_VALID
- RDES3_RECEIVE_ERROR
- RDES3_RECEIVE_WATCHDOG
- RDESC1_BUFFER_INDEX
- RDESC1_BUFFER_LENGTH
- RDESC1_NSOF
- RDES_EXT_DELAY_REQ
- RDES_EXT_DELAY_RESP
- RDES_EXT_FOLLOW_UP
- RDES_EXT_NO_PTP
- RDES_EXT_PDELAY_FOLLOW_UP
- RDES_EXT_PDELAY_REQ
- RDES_EXT_PDELAY_RESP
- RDES_EXT_SYNC
- RDES_FRAME_LENGTH_BIT_NUMBER
- RDES_PTP_ANNOUNCE
- RDES_PTP_MANAGEMENT
- RDES_PTP_PKT_RESERVED_TYPE
- RDES_PTP_SIGNALING
- RDETH_EEN_MASK
- RDEV
- RDF
- RDF1ST
- RDFAR
- RDFEND
- RDFFR
- RDFIFO
- RDFXR
- RDF_CODE
- RDF_HAS_PAGE_COUNT
- RDF_NULLIO
- RDGV
- RDH5
- RDH6
- RDHWR
- RDI
- RDI0
- RDI1
- RDI2
- RDIAR
- RDIF_REG_DBG_DWORD_ENABLE
- RDIF_REG_DBG_FORCE_FRAME
- RDIF_REG_DBG_FORCE_VALID
- RDIF_REG_DBG_SELECT
- RDIF_REG_DBG_SHIFT
- RDIF_REG_DEBUG_ERROR_INFO
- RDIF_REG_DEBUG_ERROR_INFO_SIZE
- RDIF_REG_STOP_ON_ERROR
- RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_MASK
- RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_SHIFT
- RDIF_TASK_CONTEXT_CRC_SEED_MASK
- RDIF_TASK_CONTEXT_CRC_SEED_SHIFT
- RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK
- RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT
- RDIF_TASK_CONTEXT_ERROR_IN_IO_MASK
- RDIF_TASK_CONTEXT_ERROR_IN_IO_SHIFT
- RDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK
- RDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT
- RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK
- RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT
- RDIF_TASK_CONTEXT_FORWARD_GUARD_MASK
- RDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT
- RDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK
- RDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT
- RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK
- RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT
- RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK
- RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT
- RDIF_TASK_CONTEXT_HOST_INTERFACE_MASK
- RDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT
- RDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK
- RDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT
- RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK
- RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT
- RDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK
- RDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT
- RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK
- RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT
- RDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK
- RDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT
- RDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK
- RDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT
- RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_MASK
- RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_SHIFT
- RDIF_TASK_CONTEXT_REF_TAG_MASK_MASK
- RDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT
- RDIF_TASK_CONTEXT_RESERVED0_MASK
- RDIF_TASK_CONTEXT_RESERVED0_SHIFT
- RDIF_TASK_CONTEXT_RESERVED1_MASK
- RDIF_TASK_CONTEXT_RESERVED1_SHIFT
- RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK
- RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT
- RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_MASK
- RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_SHIFT
- RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK
- RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT
- RDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK
- RDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT
- RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK
- RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT
- RDINDOOR
- RDISABLE
- RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING
- RDIST_FLAGS_RD_TABLES_PREALLOCATED
- RDI_DEV_ASSIGN
- RDI_DEV_ENTRY
- RDK2_DIAG
- RDK2_DMAADDR
- RDK2_DMACTL
- RDK2_DMALOCCOUNT
- RDK2_DMAPCICOUNT
- RDK2_DMASTAT
- RDK2_DMA_MODE
- RDK2_FAST_TIMES
- RDK2_FPGAREV
- RDK2_GPIOCTL
- RDK2_IRQENB
- RDK2_IRQSTAT
- RDK2_LEDSW
- RDK2_LOCCTLRDK
- RDK_EPLD_BUSWIDTH
- RDK_EPLD_DMA_TIMEOUT_ENABLE
- RDK_EPLD_DPPULL
- RDK_EPLD_IO_REGISTER1
- RDK_EPLD_IO_REGISTER2
- RDK_EPLD_RESET_INTERRUPT_ENABLE
- RDK_EPLD_REVISION_REGISTER
- RDK_EPLD_STATUS_REGISTER
- RDK_EPLD_USB_EOT
- RDK_EPLD_USB_LRESET
- RDK_EPLD_USB_POWERDOWN
- RDK_EPLD_USB_RESET
- RDK_EPLD_USB_WAKEUP
- RDK_EPLD_USER
- RDLAR
- RDLCH
- RDLVLGATETO_MASK
- RDLVLGATETO_SHIFT
- RDLVLTO_MASK
- RDLVLTO_SHIFT
- RDL_1_HP
- RDL_2_SP
- RDL_3_HP
- RDL_4_SP
- RDL_5_SP
- RDL_6_SP
- RDL_7_SP
- RDL_8_SP
- RDL_MAX
- RDL_NONE
- RDMA0_SOUT_DPI0
- RDMA0_SOUT_DPI1
- RDMA0_SOUT_DSI1
- RDMA0_SOUT_DSI2
- RDMA0_SOUT_DSI3
- RDMA1_SOUT_DPI0
- RDMA1_SOUT_DPI1
- RDMA1_SOUT_DSI1
- RDMA1_SOUT_DSI2
- RDMA1_SOUT_DSI3
- RDMA2_SOUT_DPI0
- RDMA2_SOUT_DPI1
- RDMA2_SOUT_DSI1
- RDMA2_SOUT_DSI2
- RDMA2_SOUT_DSI3
- RDMACG_MAX_STR
- RDMACG_RESOURCE_HCA_HANDLE
- RDMACG_RESOURCE_HCA_OBJECT
- RDMACG_RESOURCE_MAX
- RDMACG_RESOURCE_TYPE_MAX
- RDMACG_RESOURCE_TYPE_STAT
- RDMAC_MODE
- RDMAC_MODE_ADDROFLOW_ENAB
- RDMAC_MODE_BD_SBD_CRPT_ENAB
- RDMAC_MODE_ENABLE
- RDMAC_MODE_FIFOOFLOW_ENAB
- RDMAC_MODE_FIFOOREAD_ENAB
- RDMAC_MODE_FIFOURUN_ENAB
- RDMAC_MODE_FIFO_LONG_BURST
- RDMAC_MODE_FIFO_SIZE_128
- RDMAC_MODE_H2BNC_VLAN_DET
- RDMAC_MODE_IPV4_LSO_EN
- RDMAC_MODE_IPV6_LSO_EN
- RDMAC_MODE_JMB_2K_MMRR
- RDMAC_MODE_LNGREAD_ENAB
- RDMAC_MODE_MBUF_RBD_CRPT_ENAB
- RDMAC_MODE_MBUF_SBD_CRPT_ENAB
- RDMAC_MODE_MSTABORT_ENAB
- RDMAC_MODE_MULT_DMA_RD_DIS
- RDMAC_MODE_PARITYERR_ENAB
- RDMAC_MODE_RESET
- RDMAC_MODE_SPLIT_ENABLE
- RDMAC_MODE_SPLIT_RESET
- RDMAC_MODE_TGTABORT_ENAB
- RDMAC_STATUS
- RDMAC_STATUS_ADDROFLOW
- RDMAC_STATUS_FIFOOFLOW
- RDMAC_STATUS_FIFOOREAD
- RDMAC_STATUS_FIFOURUN
- RDMAC_STATUS_LNGREAD
- RDMAC_STATUS_MSTABORT
- RDMAC_STATUS_PARITYERR
- RDMAC_STATUS_TGTABORT
- RDMAEN
- RDMAEXTENSIONS
- RDMAE_SHIFT
- RDMAP_ACCESS
- RDMAP_ACC_VIOL
- RDMAP_BASE_BOUNDS
- RDMAP_CANT_INV_STAG
- RDMAP_CATASTROPHIC_GLOBAL
- RDMAP_CATASTROPHIC_LOCAL
- RDMAP_ECODE_ACCESS_RIGHTS
- RDMAP_ECODE_BASE_BOUNDS
- RDMAP_ECODE_CANNOT_INVALIDATE
- RDMAP_ECODE_CATASTROPHIC_GLOBAL
- RDMAP_ECODE_CATASTROPHIC_STREAM
- RDMAP_ECODE_INVALID_STAG
- RDMAP_ECODE_OPCODE
- RDMAP_ECODE_STAG_NOT_ASSOC
- RDMAP_ECODE_TO_WRAP
- RDMAP_ECODE_UNSPECIFIED
- RDMAP_ECODE_VERSION
- RDMAP_ETYPE_CATASTROPHIC
- RDMAP_ETYPE_REMOTE_OPERATION
- RDMAP_ETYPE_REMOTE_PROTECTION
- RDMAP_GLOBAL_CATA
- RDMAP_INV_BOUNDS
- RDMAP_INV_OPCODE
- RDMAP_INV_RDMAP_VER
- RDMAP_INV_STAG
- RDMAP_INV_VERS
- RDMAP_LOCAL_CATA
- RDMAP_MASK_OPCODE
- RDMAP_MASK_RESERVED
- RDMAP_MASK_VERSION
- RDMAP_NOT_SUPPORTED
- RDMAP_RDMA_READ_REQ
- RDMAP_RDMA_READ_RESP
- RDMAP_RDMA_WRITE
- RDMAP_REMOTE_OP
- RDMAP_REMOTE_PROT
- RDMAP_SEND
- RDMAP_SEND_INVAL
- RDMAP_SEND_SE
- RDMAP_SEND_SE_INVAL
- RDMAP_STAG_NOT_ASSOC
- RDMAP_STREAM_CATA
- RDMAP_TERMINATE
- RDMAP_TO_WRAP
- RDMAP_UNASSOC_STAG
- RDMAP_UNEXPECTED_OP
- RDMAP_UNSPECIFIED
- RDMAP_UNTAGGED_QN_COUNT
- RDMAP_UNTAGGED_QN_RDMA_READ
- RDMAP_UNTAGGED_QN_SEND
- RDMAP_UNTAGGED_QN_TERMINATE
- RDMAP_VERSION
- RDMAXPRT_CONN_PENDING
- RDMA_ACCESS_AUTO
- RDMA_ACCESS_AUTO2
- RDMA_ACCESS_AUTO3
- RDMA_ACCESS_MAN
- RDMA_AHB_END_ADDR_1
- RDMA_AHB_END_ADDR_2
- RDMA_AHB_END_ADDR_3
- RDMA_AHB_END_ADDR_4
- RDMA_AHB_END_ADDR_5
- RDMA_AHB_END_ADDR_6
- RDMA_AHB_END_ADDR_7
- RDMA_AHB_END_ADDR_MAN
- RDMA_AHB_START_ADDR_1
- RDMA_AHB_START_ADDR_2
- RDMA_AHB_START_ADDR_3
- RDMA_AHB_START_ADDR_4
- RDMA_AHB_START_ADDR_5
- RDMA_AHB_START_ADDR_6
- RDMA_AHB_START_ADDR_7
- RDMA_AHB_START_ADDR_MAN
- RDMA_AH_ATTR_TYPE_IB
- RDMA_AH_ATTR_TYPE_OPA
- RDMA_AH_ATTR_TYPE_ROCE
- RDMA_AH_ATTR_TYPE_UNDEFINED
- RDMA_ATOMIC_UAPI
- RDMA_BP_STATUS
- RDMA_BUF_DATA_OFFSET_MASK
- RDMA_BUF_DATA_OFFSET_SHIFT
- RDMA_CAPABLE
- RDMA_CDU_TASK_SEG_TYPE
- RDMA_CLASS_PORT_INFO_IB
- RDMA_CLASS_PORT_INFO_OPA
- RDMA_CMD_O_N
- RDMA_CMD_O_P
- RDMA_CM_ADDR_BOUND
- RDMA_CM_ADDR_QUERY
- RDMA_CM_ADDR_RESOLVED
- RDMA_CM_CONNECT
- RDMA_CM_DESTROYING
- RDMA_CM_DEVICE_REMOVAL
- RDMA_CM_DISCONNECT
- RDMA_CM_EVENT_ADDR_CHANGE
- RDMA_CM_EVENT_ADDR_ERROR
- RDMA_CM_EVENT_ADDR_RESOLVED
- RDMA_CM_EVENT_CONNECT_ERROR
- RDMA_CM_EVENT_CONNECT_REQUEST
- RDMA_CM_EVENT_CONNECT_RESPONSE
- RDMA_CM_EVENT_DEVICE_REMOVAL
- RDMA_CM_EVENT_DISCONNECTED
- RDMA_CM_EVENT_ESTABLISHED
- RDMA_CM_EVENT_LIST
- RDMA_CM_EVENT_MULTICAST_ERROR
- RDMA_CM_EVENT_MULTICAST_JOIN
- RDMA_CM_EVENT_REJECTED
- RDMA_CM_EVENT_ROUTE_ERROR
- RDMA_CM_EVENT_ROUTE_RESOLVED
- RDMA_CM_EVENT_TIMEWAIT_EXIT
- RDMA_CM_EVENT_UNREACHABLE
- RDMA_CM_H
- RDMA_CM_IB_H
- RDMA_CM_IDLE
- RDMA_CM_LISTEN
- RDMA_CM_ROUTE_QUERY
- RDMA_CM_ROUTE_RESOLVED
- RDMA_CONNECTION_TYPE
- RDMA_CONNECT_RETRY_MAX
- RDMA_CONS_INDEX
- RDMA_CONS_INDEX_MASK
- RDMA_CONTROL
- RDMA_CORE_CAP_AF_IB
- RDMA_CORE_CAP_ETH_AH
- RDMA_CORE_CAP_IB_CM
- RDMA_CORE_CAP_IB_GRH_REQUIRED
- RDMA_CORE_CAP_IB_MAD
- RDMA_CORE_CAP_IB_SA
- RDMA_CORE_CAP_IB_SMI
- RDMA_CORE_CAP_IW_CM
- RDMA_CORE_CAP_OPA_AH
- RDMA_CORE_CAP_OPA_MAD
- RDMA_CORE_CAP_PROT_IB
- RDMA_CORE_CAP_PROT_IWARP
- RDMA_CORE_CAP_PROT_RAW_PACKET
- RDMA_CORE_CAP_PROT_ROCE
- RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP
- RDMA_CORE_CAP_PROT_USNIC
- RDMA_CORE_H
- RDMA_CORE_PORT_IBA_IB
- RDMA_CORE_PORT_IBA_ROCE
- RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP
- RDMA_CORE_PORT_IB_GRH_REQUIRED
- RDMA_CORE_PORT_INTEL_OPA
- RDMA_CORE_PORT_IWARP
- RDMA_CORE_PORT_RAW_PACKET
- RDMA_CORE_PORT_USNIC
- RDMA_COUNTER_MASK_QP_TYPE
- RDMA_COUNTER_MODE_AUTO
- RDMA_COUNTER_MODE_MANUAL
- RDMA_COUNTER_MODE_MAX
- RDMA_COUNTER_MODE_NONE
- RDMA_CQE_COMMON_RESERVED2_MASK
- RDMA_CQE_COMMON_RESERVED2_SHIFT
- RDMA_CQE_COMMON_TOGGLE_BIT_MASK
- RDMA_CQE_COMMON_TOGGLE_BIT_SHIFT
- RDMA_CQE_COMMON_TYPE_MASK
- RDMA_CQE_COMMON_TYPE_SHIFT
- RDMA_CQE_REQUESTER_RESERVED5_MASK
- RDMA_CQE_REQUESTER_RESERVED5_SHIFT
- RDMA_CQE_REQUESTER_TOGGLE_BIT_MASK
- RDMA_CQE_REQUESTER_TOGGLE_BIT_SHIFT
- RDMA_CQE_REQUESTER_TYPE_MASK
- RDMA_CQE_REQUESTER_TYPE_SHIFT
- RDMA_CQE_REQ_STS_BAD_RESPONSE_ERR
- RDMA_CQE_REQ_STS_LOCAL_LENGTH_ERR
- RDMA_CQE_REQ_STS_LOCAL_PROTECTION_ERR
- RDMA_CQE_REQ_STS_LOCAL_QP_OPERATION_ERR
- RDMA_CQE_REQ_STS_MEMORY_MGT_OPERATION_ERR
- RDMA_CQE_REQ_STS_OK
- RDMA_CQE_REQ_STS_REMOTE_ACCESS_ERR
- RDMA_CQE_REQ_STS_REMOTE_INVALID_REQUEST_ERR
- RDMA_CQE_REQ_STS_REMOTE_OPERATION_ERR
- RDMA_CQE_REQ_STS_RNR_NAK_RETRY_CNT_ERR
- RDMA_CQE_REQ_STS_SIG_ERR
- RDMA_CQE_REQ_STS_TRANSPORT_RETRY_CNT_ERR
- RDMA_CQE_REQ_STS_WORK_REQUEST_FLUSHED_ERR
- RDMA_CQE_REQ_STS_XRC_VOILATION_ERR
- RDMA_CQE_RESPONDER_IMM_FLG_MASK
- RDMA_CQE_RESPONDER_IMM_FLG_SHIFT
- RDMA_CQE_RESPONDER_INV_FLG_MASK
- RDMA_CQE_RESPONDER_INV_FLG_SHIFT
- RDMA_CQE_RESPONDER_RDMA_FLG_MASK
- RDMA_CQE_RESPONDER_RDMA_FLG_SHIFT
- RDMA_CQE_RESPONDER_RESERVED2_MASK
- RDMA_CQE_RESPONDER_RESERVED2_SHIFT
- RDMA_CQE_RESPONDER_TOGGLE_BIT_MASK
- RDMA_CQE_RESPONDER_TOGGLE_BIT_SHIFT
- RDMA_CQE_RESPONDER_TYPE_MASK
- RDMA_CQE_RESPONDER_TYPE_SHIFT
- RDMA_CQE_RESP_STS_LOCAL_ACCESS_ERR
- RDMA_CQE_RESP_STS_LOCAL_LENGTH_ERR
- RDMA_CQE_RESP_STS_LOCAL_PROTECTION_ERR
- RDMA_CQE_RESP_STS_LOCAL_QP_OPERATION_ERR
- RDMA_CQE_RESP_STS_MEMORY_MGT_OPERATION_ERR
- RDMA_CQE_RESP_STS_OK
- RDMA_CQE_RESP_STS_REMOTE_INVALID_REQUEST_ERR
- RDMA_CQE_RESP_STS_WORK_REQUEST_FLUSHED_ERR
- RDMA_CQE_TYPE_INVALID
- RDMA_CQE_TYPE_REQUESTER
- RDMA_CQE_TYPE_RESPONDER_RQ
- RDMA_CQE_TYPE_RESPONDER_SRQ
- RDMA_CQE_TYPE_RESPONDER_XRC_SRQ
- RDMA_CQ_DISABLE
- RDMA_CQ_OP
- RDMA_CQ_SETUP
- RDMA_CREATE_AH_SLEEPABLE
- RDMA_CTRL
- RDMA_CTRL_QP_SETUP
- RDMA_DEBUG
- RDMA_DESC_RAM_INIT_BUSY
- RDMA_DESTROY_AH_SLEEPABLE
- RDMA_DEV_REGISTERED
- RDMA_DIF_BLOCK_4096
- RDMA_DIF_BLOCK_512
- RDMA_DIF_CRC_SEED_0000
- RDMA_DIF_CRC_SEED_FFFF
- RDMA_DIF_DIR_RX
- RDMA_DIF_DIR_TX
- RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_APP_TAG_MASK
- RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_APP_TAG_SHIFT
- RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_CRC_MASK
- RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_CRC_SHIFT
- RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_REF_TAG_MASK
- RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_REF_TAG_SHIFT
- RDMA_DIF_ERROR_RESULT_RESERVED0_MASK
- RDMA_DIF_ERROR_RESULT_RESERVED0_SHIFT
- RDMA_DIF_ERROR_RESULT_TOGGLE_BIT_MASK
- RDMA_DIF_ERROR_RESULT_TOGGLE_BIT_SHIFT
- RDMA_DIF_PARAMS_APP_ESCAPE_MASK
- RDMA_DIF_PARAMS_APP_ESCAPE_SHIFT
- RDMA_DIF_PARAMS_BLOCK_GUARD_TYPE_MASK
- RDMA_DIF_PARAMS_BLOCK_GUARD_TYPE_SHIFT
- RDMA_DIF_PARAMS_BLOCK_SIZE_MASK
- RDMA_DIF_PARAMS_BLOCK_SIZE_SHIFT
- RDMA_DIF_PARAMS_CRC_SEED_MASK
- RDMA_DIF_PARAMS_CRC_SEED_SHIFT
- RDMA_DIF_PARAMS_IO_DIRECTION_FLG_MASK
- RDMA_DIF_PARAMS_IO_DIRECTION_FLG_SHIFT
- RDMA_DIF_PARAMS_REF_ESCAPE_MASK
- RDMA_DIF_PARAMS_REF_ESCAPE_SHIFT
- RDMA_DIF_PARAMS_RESERVED4_MASK
- RDMA_DIF_PARAMS_RESERVED4_SHIFT
- RDMA_DIF_PARAMS_RUNT_VALID_FLG_MASK
- RDMA_DIF_PARAMS_RUNT_VALID_FLG_SHIFT
- RDMA_DIF_PARAMS_RX_REF_TAG_CONST_MASK
- RDMA_DIF_PARAMS_RX_REF_TAG_CONST_SHIFT
- RDMA_DIF_PARAMS_VALIDATE_APP_TAG_MASK
- RDMA_DIF_PARAMS_VALIDATE_APP_TAG_SHIFT
- RDMA_DIF_PARAMS_VALIDATE_CRC_GUARD_MASK
- RDMA_DIF_PARAMS_VALIDATE_CRC_GUARD_SHIFT
- RDMA_DIF_PARAMS_VALIDATE_REF_TAG_MASK
- RDMA_DIF_PARAMS_VALIDATE_REF_TAG_SHIFT
- RDMA_DIM_PARAMS_NUM_PROFILES
- RDMA_DIM_START_PROFILE
- RDMA_DISABLED
- RDMA_DISC_EN
- RDMA_DONE
- RDMA_DRIVER_BNXT_RE
- RDMA_DRIVER_CXGB3
- RDMA_DRIVER_CXGB4
- RDMA_DRIVER_EFA
- RDMA_DRIVER_HFI1
- RDMA_DRIVER_HNS
- RDMA_DRIVER_I40IW
- RDMA_DRIVER_MLX4
- RDMA_DRIVER_MLX5
- RDMA_DRIVER_MTHCA
- RDMA_DRIVER_NES
- RDMA_DRIVER_OCRDMA
- RDMA_DRIVER_QEDR
- RDMA_DRIVER_QIB
- RDMA_DRIVER_RXE
- RDMA_DRIVER_SIW
- RDMA_DRIVER_UNKNOWN
- RDMA_DRIVER_USNIC
- RDMA_DRIVER_VMW_PVRDMA
- RDMA_EN
- RDMA_ENABLED
- RDMA_END_ADDR_HI
- RDMA_END_ADDR_LO
- RDMA_ENGINE_EN
- RDMA_EOF_ABNORMAL_INT
- RDMA_ERROR
- RDMA_EVENT_CREATE_CQ
- RDMA_EVENT_CREATE_SRQ
- RDMA_EVENT_DEREGISTER_MR
- RDMA_EVENT_DESTROY_CQ
- RDMA_EVENT_DESTROY_SRQ
- RDMA_EVENT_FUNC_CLOSE
- RDMA_EVENT_FUNC_INIT
- RDMA_EVENT_MODIFY_SRQ
- RDMA_EVENT_REGISTER_MR
- RDMA_EVENT_RESIZE_CQ
- RDMA_EVENT_UNUSED
- RDMA_FIFO_PSEUDO_SIZE
- RDMA_FIFO_SIZE
- RDMA_FIFO_UNDERFLOW_EN
- RDMA_FIFO_UNDERFLOW_INT
- RDMA_FRAME_END_INT
- RDMA_FRAME_START_INT
- RDMA_GET_MEM
- RDMA_GET_MIB
- RDMA_GET_PARAMS
- RDMA_HDR_FLAG
- RDMA_HW_STATS_DEFAULT_LIFESPAN
- RDMA_IB_IP_PS_IB
- RDMA_IB_IP_PS_MASK
- RDMA_IB_IP_PS_TCP
- RDMA_IB_IP_PS_UDP
- RDMA_INTR_THRESH_MASK
- RDMA_IOCTL_MAGIC
- RDMA_LE_MODE
- RDMA_MATRIX_ENABLE
- RDMA_MATRIX_INT_MTX_BT601_to_RGB
- RDMA_MATRIX_INT_MTX_SEL
- RDMA_MAX_CQS
- RDMA_MAX_DATA_SIZE_IN_WQE
- RDMA_MAX_PDS
- RDMA_MAX_PORTS
- RDMA_MAX_PRIVATE_DATA
- RDMA_MAX_SGE_PER_RQ_WQE
- RDMA_MAX_SGE_PER_SQ_WQE
- RDMA_MAX_SGE_PER_SRQ
- RDMA_MAX_SRQS
- RDMA_MAX_SRQ_WQE_SIZE
- RDMA_MAX_TIDS
- RDMA_MAX_XRC_SRQS
- RDMA_MBDONE_INTR
- RDMA_MC_JOIN_FLAG_FULLMEMBER
- RDMA_MC_JOIN_FLAG_RESERVED
- RDMA_MC_JOIN_FLAG_SENDONLY_FULLMEMBER
- RDMA_MEM_GMC
- RDMA_MEM_SEL
- RDMA_MODE_MEMORY
- RDMA_MSG
- RDMA_MSGP
- RDMA_NETDEV_IPOIB
- RDMA_NETDEV_OPA_VNIC
- RDMA_NETWORK_IB
- RDMA_NETWORK_IPV4
- RDMA_NETWORK_IPV6
- RDMA_NETWORK_ROCE_V1
- RDMA_NLA_F_MANDATORY
- RDMA_NLA_TYPE_MASK
- RDMA_NLDEV_ATTR_CAP_FLAGS
- RDMA_NLDEV_ATTR_CHARDEV
- RDMA_NLDEV_ATTR_CHARDEV_ABI
- RDMA_NLDEV_ATTR_CHARDEV_NAME
- RDMA_NLDEV_ATTR_CHARDEV_TYPE
- RDMA_NLDEV_ATTR_CHARDEV_TYPE_SIZE
- RDMA_NLDEV_ATTR_DEV_DIM
- RDMA_NLDEV_ATTR_DEV_INDEX
- RDMA_NLDEV_ATTR_DEV_NAME
- RDMA_NLDEV_ATTR_DEV_NODE_TYPE
- RDMA_NLDEV_ATTR_DEV_PROTOCOL
- RDMA_NLDEV_ATTR_DRIVER
- RDMA_NLDEV_ATTR_DRIVER_ENTRY
- RDMA_NLDEV_ATTR_DRIVER_PRINT_TYPE
- RDMA_NLDEV_ATTR_DRIVER_S32
- RDMA_NLDEV_ATTR_DRIVER_S64
- RDMA_NLDEV_ATTR_DRIVER_STRING
- RDMA_NLDEV_ATTR_DRIVER_U32
- RDMA_NLDEV_ATTR_DRIVER_U64
- RDMA_NLDEV_ATTR_EMPTY_STRING
- RDMA_NLDEV_ATTR_ENTRY_STRLEN
- RDMA_NLDEV_ATTR_FW_VERSION
- RDMA_NLDEV_ATTR_LID
- RDMA_NLDEV_ATTR_LINK_TYPE
- RDMA_NLDEV_ATTR_LMC
- RDMA_NLDEV_ATTR_MAX
- RDMA_NLDEV_ATTR_NDEV_INDEX
- RDMA_NLDEV_ATTR_NDEV_NAME
- RDMA_NLDEV_ATTR_NODE_GUID
- RDMA_NLDEV_ATTR_PAD
- RDMA_NLDEV_ATTR_PORT_INDEX
- RDMA_NLDEV_ATTR_PORT_PHYS_STATE
- RDMA_NLDEV_ATTR_PORT_STATE
- RDMA_NLDEV_ATTR_RES_CM_ID
- RDMA_NLDEV_ATTR_RES_CM_IDN
- RDMA_NLDEV_ATTR_RES_CM_ID_ENTRY
- RDMA_NLDEV_ATTR_RES_CQ
- RDMA_NLDEV_ATTR_RES_CQE
- RDMA_NLDEV_ATTR_RES_CQN
- RDMA_NLDEV_ATTR_RES_CQ_ENTRY
- RDMA_NLDEV_ATTR_RES_CTXN
- RDMA_NLDEV_ATTR_RES_DST_ADDR
- RDMA_NLDEV_ATTR_RES_IOVA
- RDMA_NLDEV_ATTR_RES_KERN_NAME
- RDMA_NLDEV_ATTR_RES_LKEY
- RDMA_NLDEV_ATTR_RES_LOCAL_DMA_LKEY
- RDMA_NLDEV_ATTR_RES_LQPN
- RDMA_NLDEV_ATTR_RES_MR
- RDMA_NLDEV_ATTR_RES_MRLEN
- RDMA_NLDEV_ATTR_RES_MRN
- RDMA_NLDEV_ATTR_RES_MR_ENTRY
- RDMA_NLDEV_ATTR_RES_PATH_MIG_STATE
- RDMA_NLDEV_ATTR_RES_PD
- RDMA_NLDEV_ATTR_RES_PDN
- RDMA_NLDEV_ATTR_RES_PD_ENTRY
- RDMA_NLDEV_ATTR_RES_PID
- RDMA_NLDEV_ATTR_RES_POLL_CTX
- RDMA_NLDEV_ATTR_RES_PS
- RDMA_NLDEV_ATTR_RES_QP
- RDMA_NLDEV_ATTR_RES_QP_ENTRY
- RDMA_NLDEV_ATTR_RES_RKEY
- RDMA_NLDEV_ATTR_RES_RQPN
- RDMA_NLDEV_ATTR_RES_RQ_PSN
- RDMA_NLDEV_ATTR_RES_SQ_PSN
- RDMA_NLDEV_ATTR_RES_SRC_ADDR
- RDMA_NLDEV_ATTR_RES_STATE
- RDMA_NLDEV_ATTR_RES_SUMMARY
- RDMA_NLDEV_ATTR_RES_SUMMARY_ENTRY
- RDMA_NLDEV_ATTR_RES_SUMMARY_ENTRY_CURR
- RDMA_NLDEV_ATTR_RES_SUMMARY_ENTRY_NAME
- RDMA_NLDEV_ATTR_RES_TYPE
- RDMA_NLDEV_ATTR_RES_UNSAFE_GLOBAL_RKEY
- RDMA_NLDEV_ATTR_RES_USECNT
- RDMA_NLDEV_ATTR_SM_LID
- RDMA_NLDEV_ATTR_STAT_AUTO_MODE_MASK
- RDMA_NLDEV_ATTR_STAT_COUNTER
- RDMA_NLDEV_ATTR_STAT_COUNTER_ENTRY
- RDMA_NLDEV_ATTR_STAT_COUNTER_ID
- RDMA_NLDEV_ATTR_STAT_HWCOUNTERS
- RDMA_NLDEV_ATTR_STAT_HWCOUNTER_ENTRY
- RDMA_NLDEV_ATTR_STAT_HWCOUNTER_ENTRY_NAME
- RDMA_NLDEV_ATTR_STAT_HWCOUNTER_ENTRY_VALUE
- RDMA_NLDEV_ATTR_STAT_MODE
- RDMA_NLDEV_ATTR_STAT_RES
- RDMA_NLDEV_ATTR_SUBNET_PREFIX
- RDMA_NLDEV_ATTR_SYS_IMAGE_GUID
- RDMA_NLDEV_ATTR_UNSPEC
- RDMA_NLDEV_ATTR_UVERBS_DRIVER_ID
- RDMA_NLDEV_CMD_DELLINK
- RDMA_NLDEV_CMD_GET
- RDMA_NLDEV_CMD_GET_CHARDEV
- RDMA_NLDEV_CMD_NEWLINK
- RDMA_NLDEV_CMD_PORT_GET
- RDMA_NLDEV_CMD_RES_CM_ID_GET
- RDMA_NLDEV_CMD_RES_CQ_GET
- RDMA_NLDEV_CMD_RES_GET
- RDMA_NLDEV_CMD_RES_MR_GET
- RDMA_NLDEV_CMD_RES_PD_GET
- RDMA_NLDEV_CMD_RES_QP_GET
- RDMA_NLDEV_CMD_SET
- RDMA_NLDEV_CMD_STAT_DEL
- RDMA_NLDEV_CMD_STAT_GET
- RDMA_NLDEV_CMD_STAT_SET
- RDMA_NLDEV_CMD_SYS_GET
- RDMA_NLDEV_CMD_SYS_SET
- RDMA_NLDEV_CMD_UNSPEC
- RDMA_NLDEV_NET_NS_FD
- RDMA_NLDEV_NUM_OPS
- RDMA_NLDEV_PRINT_TYPE_HEX
- RDMA_NLDEV_PRINT_TYPE_UNSPEC
- RDMA_NLDEV_SYS_ATTR_NETNS_MODE
- RDMA_NL_ADMIN_PERM
- RDMA_NL_GET_CLIENT
- RDMA_NL_GET_OP
- RDMA_NL_GET_TYPE
- RDMA_NL_GROUP_IWPM
- RDMA_NL_GROUP_LS
- RDMA_NL_IWCM
- RDMA_NL_IWPM_ADD_MAPPING
- RDMA_NL_IWPM_HANDLE_ERR
- RDMA_NL_IWPM_HELLO
- RDMA_NL_IWPM_MAPINFO
- RDMA_NL_IWPM_MAPINFO_NUM
- RDMA_NL_IWPM_NUM_OPS
- RDMA_NL_IWPM_QUERY_MAPPING
- RDMA_NL_IWPM_REG_PID
- RDMA_NL_IWPM_REMOTE_INFO
- RDMA_NL_IWPM_REMOVE_MAPPING
- RDMA_NL_LS
- RDMA_NL_LS_F_ERR
- RDMA_NL_LS_NUM_OPS
- RDMA_NL_LS_OP_IP_RESOLVE
- RDMA_NL_LS_OP_RESOLVE
- RDMA_NL_LS_OP_SET_TIMEOUT
- RDMA_NL_NLDEV
- RDMA_NL_NUM_CLIENTS
- RDMA_NL_NUM_GROUPS
- RDMA_NL_RSVD
- RDMA_NODE_IB_CA
- RDMA_NODE_IB_ROUTER
- RDMA_NODE_IB_SWITCH
- RDMA_NODE_RNIC
- RDMA_NODE_UNSPECIFIED
- RDMA_NODE_USNIC
- RDMA_NODE_USNIC_UDP
- RDMA_NOMSG
- RDMA_NUM_STATISTIC_COUNTERS
- RDMA_NUM_STATISTIC_COUNTERS_BB
- RDMA_NUM_STATISTIC_COUNTERS_K2
- RDMA_OFST
- RDMA_OPCODE_MASK
- RDMA_OPTION_IB
- RDMA_OPTION_IB_PATH
- RDMA_OPTION_ID
- RDMA_OPTION_ID_ACK_TIMEOUT
- RDMA_OPTION_ID_AFONLY
- RDMA_OPTION_ID_REUSEADDR
- RDMA_OPTION_ID_TOS
- RDMA_OUTPUT_VALID_FIFO_THRESHOLD
- RDMA_OVERRIDE
- RDMA_PROD_INDEX
- RDMA_PROD_INDEX_MASK
- RDMA_PROTOCOL_IB
- RDMA_PROTOCOL_IBOE
- RDMA_PROTOCOL_IWARP
- RDMA_PROTOCOL_USNIC_UDP
- RDMA_PS_IB
- RDMA_PS_IPOIB
- RDMA_PS_TCP
- RDMA_PS_UDP
- RDMA_PWM_VAL32_DATA_AGG_CMD_MASK
- RDMA_PWM_VAL32_DATA_AGG_CMD_SHIFT
- RDMA_PWM_VAL32_DATA_BYPASS_EN_MASK
- RDMA_PWM_VAL32_DATA_BYPASS_EN_SHIFT
- RDMA_PWM_VAL32_DATA_CONN_TYPE_IS_IWARP_MASK
- RDMA_PWM_VAL32_DATA_CONN_TYPE_IS_IWARP_SHIFT
- RDMA_PWM_VAL32_DATA_RESERVED_MASK
- RDMA_PWM_VAL32_DATA_RESERVED_SHIFT
- RDMA_PWM_VAL32_DATA_SET_16B_VAL_MASK
- RDMA_PWM_VAL32_DATA_SET_16B_VAL_SHIFT
- RDMA_RAMROD_CREATE_CQ
- RDMA_RAMROD_CREATE_SRQ
- RDMA_RAMROD_DEREGISTER_MR
- RDMA_RAMROD_DESTROY_CQ
- RDMA_RAMROD_DESTROY_SRQ
- RDMA_RAMROD_FUNC_CLOSE
- RDMA_RAMROD_FUNC_INIT
- RDMA_RAMROD_MODIFY_SRQ
- RDMA_RAMROD_REGISTER_MR
- RDMA_RAMROD_RESIZE_CQ
- RDMA_RAMROD_UNUSED
- RDMA_READ_PTR
- RDMA_READ_PTR_HI
- RDMA_READ_PTR_LO
- RDMA_READ_REQUEST
- RDMA_READ_REQ_OPCODE
- RDMA_READ_RESPONSE_FIRST
- RDMA_READ_RESPONSE_LAST
- RDMA_READ_RESPONSE_MIDDLE
- RDMA_READ_RESPONSE_ONLY
- RDMA_READ_UAPI_ATOMIC
- RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK
- RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT
- RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK
- RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT
- RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK
- RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT
- RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK
- RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT
- RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK
- RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT
- RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK
- RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT
- RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK
- RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT
- RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK
- RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT
- RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK
- RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT
- RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK
- RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT
- RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK
- RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT
- RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK
- RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT
- RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK
- RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_SHIFT
- RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK
- RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT
- RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK
- RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT
- RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK
- RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT
- RDMA_REG_MODE
- RDMA_REG_UPDATE_INT
- RDMA_REMOVE_ABORT
- RDMA_REMOVE_CLOSE
- RDMA_REMOVE_DESTROY
- RDMA_REMOVE_DRIVER_REMOVE
- RDMA_REQ_RD_ATOMIC_ELM_SIZE
- RDMA_RESERVED_LKEY
- RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK
- RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT
- RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK
- RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT
- RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK
- RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT
- RDMA_RESOLVE_TIMEOUT
- RDMA_RESP_RD_ATOMIC_ELM_SIZE
- RDMA_RESTRACK_CM_ID
- RDMA_RESTRACK_COUNTER
- RDMA_RESTRACK_CQ
- RDMA_RESTRACK_CTX
- RDMA_RESTRACK_MAX
- RDMA_RESTRACK_MR
- RDMA_RESTRACK_PD
- RDMA_RESTRACK_QP
- RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR
- RDMA_RETURN_NIG_DRAIN_REQ
- RDMA_RETURN_OK
- RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR
- RDMA_RETURN_RESIZE_CQ_ERR
- RDMA_RING_BUF_SIZE
- RDMA_RING_CFG
- RDMA_RING_PAGE_SIZE
- RDMA_RING_SIZE_SHIFT
- RDMA_RQ_SGE_L_KEY_HI_MASK
- RDMA_RQ_SGE_L_KEY_HI_SHIFT
- RDMA_RQ_SGE_L_KEY_LO_MASK
- RDMA_RQ_SGE_L_KEY_LO_SHIFT
- RDMA_RQ_SGE_NUM_SGES_MASK
- RDMA_RQ_SGE_NUM_SGES_SHIFT
- RDMA_RW_MR
- RDMA_RW_MULTI_WR
- RDMA_RW_SIG_MR
- RDMA_RW_SINGLE_WR
- RDMA_RX_BYPASS_PRIO
- RDMA_RX_KERNEL_PRIO
- RDMA_SCB_BURST_SIZE
- RDMA_SQ_ATOMIC_WQE_1ST_COMP_FLG_MASK
- RDMA_SQ_ATOMIC_WQE_1ST_COMP_FLG_SHIFT
- RDMA_SQ_ATOMIC_WQE_1ST_INLINE_FLG_MASK
- RDMA_SQ_ATOMIC_WQE_1ST_INLINE_FLG_SHIFT
- RDMA_SQ_ATOMIC_WQE_1ST_INV_FENCE_FLG_MASK
- RDMA_SQ_ATOMIC_WQE_1ST_INV_FENCE_FLG_SHIFT
- RDMA_SQ_ATOMIC_WQE_1ST_RD_FENCE_FLG_MASK
- RDMA_SQ_ATOMIC_WQE_1ST_RD_FENCE_FLG_SHIFT
- RDMA_SQ_ATOMIC_WQE_1ST_RESERVED0_MASK
- RDMA_SQ_ATOMIC_WQE_1ST_RESERVED0_SHIFT
- RDMA_SQ_ATOMIC_WQE_1ST_SE_FLG_MASK
- RDMA_SQ_ATOMIC_WQE_1ST_SE_FLG_SHIFT
- RDMA_SQ_ATOMIC_WQE_COMP_FLG_MASK
- RDMA_SQ_ATOMIC_WQE_COMP_FLG_SHIFT
- RDMA_SQ_ATOMIC_WQE_DIF_ON_HOST_FLG_MASK
- RDMA_SQ_ATOMIC_WQE_DIF_ON_HOST_FLG_SHIFT
- RDMA_SQ_ATOMIC_WQE_INLINE_FLG_MASK
- RDMA_SQ_ATOMIC_WQE_INLINE_FLG_SHIFT
- RDMA_SQ_ATOMIC_WQE_INV_FENCE_FLG_MASK
- RDMA_SQ_ATOMIC_WQE_INV_FENCE_FLG_SHIFT
- RDMA_SQ_ATOMIC_WQE_RD_FENCE_FLG_MASK
- RDMA_SQ_ATOMIC_WQE_RD_FENCE_FLG_SHIFT
- RDMA_SQ_ATOMIC_WQE_RESERVED0_MASK
- RDMA_SQ_ATOMIC_WQE_RESERVED0_SHIFT
- RDMA_SQ_ATOMIC_WQE_SE_FLG_MASK
- RDMA_SQ_ATOMIC_WQE_SE_FLG_SHIFT
- RDMA_SQ_BIND_WQE_1ST_COMP_FLG_MASK
- RDMA_SQ_BIND_WQE_1ST_COMP_FLG_SHIFT
- RDMA_SQ_BIND_WQE_1ST_INLINE_FLG_MASK
- RDMA_SQ_BIND_WQE_1ST_INLINE_FLG_SHIFT
- RDMA_SQ_BIND_WQE_1ST_INV_FENCE_FLG_MASK
- RDMA_SQ_BIND_WQE_1ST_INV_FENCE_FLG_SHIFT
- RDMA_SQ_BIND_WQE_1ST_RD_FENCE_FLG_MASK
- RDMA_SQ_BIND_WQE_1ST_RD_FENCE_FLG_SHIFT
- RDMA_SQ_BIND_WQE_1ST_RESERVED0_MASK
- RDMA_SQ_BIND_WQE_1ST_RESERVED0_SHIFT
- RDMA_SQ_BIND_WQE_1ST_SE_FLG_MASK
- RDMA_SQ_BIND_WQE_1ST_SE_FLG_SHIFT
- RDMA_SQ_BIND_WQE_2ND_ENABLE_ATOMIC_MASK
- RDMA_SQ_BIND_WQE_2ND_ENABLE_ATOMIC_SHIFT
- RDMA_SQ_BIND_WQE_2ND_LOCAL_READ_MASK
- RDMA_SQ_BIND_WQE_2ND_LOCAL_READ_SHIFT
- RDMA_SQ_BIND_WQE_2ND_LOCAL_WRITE_MASK
- RDMA_SQ_BIND_WQE_2ND_LOCAL_WRITE_SHIFT
- RDMA_SQ_BIND_WQE_2ND_REMOTE_READ_MASK
- RDMA_SQ_BIND_WQE_2ND_REMOTE_READ_SHIFT
- RDMA_SQ_BIND_WQE_2ND_REMOTE_WRITE_MASK
- RDMA_SQ_BIND_WQE_2ND_REMOTE_WRITE_SHIFT
- RDMA_SQ_BIND_WQE_2ND_RESERVED1_MASK
- RDMA_SQ_BIND_WQE_2ND_RESERVED1_SHIFT
- RDMA_SQ_BIND_WQE_2ND_RESERVED2_MASK
- RDMA_SQ_BIND_WQE_2ND_RESERVED2_SHIFT
- RDMA_SQ_BIND_WQE_2ND_ZERO_BASED_MASK
- RDMA_SQ_BIND_WQE_2ND_ZERO_BASED_SHIFT
- RDMA_SQ_BIND_WQE_COMP_FLG_MASK
- RDMA_SQ_BIND_WQE_COMP_FLG_SHIFT
- RDMA_SQ_BIND_WQE_DIF_ON_HOST_FLG_MASK
- RDMA_SQ_BIND_WQE_DIF_ON_HOST_FLG_SHIFT
- RDMA_SQ_BIND_WQE_ENABLE_ATOMIC_MASK
- RDMA_SQ_BIND_WQE_ENABLE_ATOMIC_SHIFT
- RDMA_SQ_BIND_WQE_INLINE_FLG_MASK
- RDMA_SQ_BIND_WQE_INLINE_FLG_SHIFT
- RDMA_SQ_BIND_WQE_INV_FENCE_FLG_MASK
- RDMA_SQ_BIND_WQE_INV_FENCE_FLG_SHIFT
- RDMA_SQ_BIND_WQE_LOCAL_READ_MASK
- RDMA_SQ_BIND_WQE_LOCAL_READ_SHIFT
- RDMA_SQ_BIND_WQE_LOCAL_WRITE_MASK
- RDMA_SQ_BIND_WQE_LOCAL_WRITE_SHIFT
- RDMA_SQ_BIND_WQE_RD_FENCE_FLG_MASK
- RDMA_SQ_BIND_WQE_RD_FENCE_FLG_SHIFT
- RDMA_SQ_BIND_WQE_REMOTE_READ_MASK
- RDMA_SQ_BIND_WQE_REMOTE_READ_SHIFT
- RDMA_SQ_BIND_WQE_REMOTE_WRITE_MASK
- RDMA_SQ_BIND_WQE_REMOTE_WRITE_SHIFT
- RDMA_SQ_BIND_WQE_RESERVED0_MASK
- RDMA_SQ_BIND_WQE_RESERVED0_SHIFT
- RDMA_SQ_BIND_WQE_RESERVED1_MASK
- RDMA_SQ_BIND_WQE_RESERVED1_SHIFT
- RDMA_SQ_BIND_WQE_RESERVED2_MASK
- RDMA_SQ_BIND_WQE_RESERVED2_SHIFT
- RDMA_SQ_BIND_WQE_SE_FLG_MASK
- RDMA_SQ_BIND_WQE_SE_FLG_SHIFT
- RDMA_SQ_BIND_WQE_ZERO_BASED_MASK
- RDMA_SQ_BIND_WQE_ZERO_BASED_SHIFT
- RDMA_SQ_COMMON_WQE_COMP_FLG_MASK
- RDMA_SQ_COMMON_WQE_COMP_FLG_SHIFT
- RDMA_SQ_COMMON_WQE_INLINE_FLG_MASK
- RDMA_SQ_COMMON_WQE_INLINE_FLG_SHIFT
- RDMA_SQ_COMMON_WQE_INV_FENCE_FLG_MASK
- RDMA_SQ_COMMON_WQE_INV_FENCE_FLG_SHIFT
- RDMA_SQ_COMMON_WQE_RD_FENCE_FLG_MASK
- RDMA_SQ_COMMON_WQE_RD_FENCE_FLG_SHIFT
- RDMA_SQ_COMMON_WQE_RESERVED0_MASK
- RDMA_SQ_COMMON_WQE_RESERVED0_SHIFT
- RDMA_SQ_COMMON_WQE_SE_FLG_MASK
- RDMA_SQ_COMMON_WQE_SE_FLG_SHIFT
- RDMA_SQ_FMR_WQE_1ST_COMP_FLG_MASK
- RDMA_SQ_FMR_WQE_1ST_COMP_FLG_SHIFT
- RDMA_SQ_FMR_WQE_1ST_DIF_ON_HOST_FLG_MASK
- RDMA_SQ_FMR_WQE_1ST_DIF_ON_HOST_FLG_SHIFT
- RDMA_SQ_FMR_WQE_1ST_INLINE_FLG_MASK
- RDMA_SQ_FMR_WQE_1ST_INLINE_FLG_SHIFT
- RDMA_SQ_FMR_WQE_1ST_INV_FENCE_FLG_MASK
- RDMA_SQ_FMR_WQE_1ST_INV_FENCE_FLG_SHIFT
- RDMA_SQ_FMR_WQE_1ST_RD_FENCE_FLG_MASK
- RDMA_SQ_FMR_WQE_1ST_RD_FENCE_FLG_SHIFT
- RDMA_SQ_FMR_WQE_1ST_RESERVED0_MASK
- RDMA_SQ_FMR_WQE_1ST_RESERVED0_SHIFT
- RDMA_SQ_FMR_WQE_1ST_SE_FLG_MASK
- RDMA_SQ_FMR_WQE_1ST_SE_FLG_SHIFT
- RDMA_SQ_FMR_WQE_2ND_BIND_EN_MASK
- RDMA_SQ_FMR_WQE_2ND_BIND_EN_SHIFT
- RDMA_SQ_FMR_WQE_2ND_ENABLE_ATOMIC_MASK
- RDMA_SQ_FMR_WQE_2ND_ENABLE_ATOMIC_SHIFT
- RDMA_SQ_FMR_WQE_2ND_LOCAL_READ_MASK
- RDMA_SQ_FMR_WQE_2ND_LOCAL_READ_SHIFT
- RDMA_SQ_FMR_WQE_2ND_LOCAL_WRITE_MASK
- RDMA_SQ_FMR_WQE_2ND_LOCAL_WRITE_SHIFT
- RDMA_SQ_FMR_WQE_2ND_PAGE_SIZE_LOG_MASK
- RDMA_SQ_FMR_WQE_2ND_PAGE_SIZE_LOG_SHIFT
- RDMA_SQ_FMR_WQE_2ND_REMOTE_READ_MASK
- RDMA_SQ_FMR_WQE_2ND_REMOTE_READ_SHIFT
- RDMA_SQ_FMR_WQE_2ND_REMOTE_WRITE_MASK
- RDMA_SQ_FMR_WQE_2ND_REMOTE_WRITE_SHIFT
- RDMA_SQ_FMR_WQE_2ND_RESERVED1_MASK
- RDMA_SQ_FMR_WQE_2ND_RESERVED1_SHIFT
- RDMA_SQ_FMR_WQE_2ND_RESERVED2_MASK
- RDMA_SQ_FMR_WQE_2ND_RESERVED2_SHIFT
- RDMA_SQ_FMR_WQE_2ND_ZERO_BASED_MASK
- RDMA_SQ_FMR_WQE_2ND_ZERO_BASED_SHIFT
- RDMA_SQ_FMR_WQE_BIND_EN_MASK
- RDMA_SQ_FMR_WQE_BIND_EN_SHIFT
- RDMA_SQ_FMR_WQE_COMP_FLG_MASK
- RDMA_SQ_FMR_WQE_COMP_FLG_SHIFT
- RDMA_SQ_FMR_WQE_DIF_ON_HOST_FLG_MASK
- RDMA_SQ_FMR_WQE_DIF_ON_HOST_FLG_SHIFT
- RDMA_SQ_FMR_WQE_ENABLE_ATOMIC_MASK
- RDMA_SQ_FMR_WQE_ENABLE_ATOMIC_SHIFT
- RDMA_SQ_FMR_WQE_INLINE_FLG_MASK
- RDMA_SQ_FMR_WQE_INLINE_FLG_SHIFT
- RDMA_SQ_FMR_WQE_INV_FENCE_FLG_MASK
- RDMA_SQ_FMR_WQE_INV_FENCE_FLG_SHIFT
- RDMA_SQ_FMR_WQE_LOCAL_READ_MASK
- RDMA_SQ_FMR_WQE_LOCAL_READ_SHIFT
- RDMA_SQ_FMR_WQE_LOCAL_WRITE_MASK
- RDMA_SQ_FMR_WQE_LOCAL_WRITE_SHIFT
- RDMA_SQ_FMR_WQE_PAGE_SIZE_LOG_MASK
- RDMA_SQ_FMR_WQE_PAGE_SIZE_LOG_SHIFT
- RDMA_SQ_FMR_WQE_RD_FENCE_FLG_MASK
- RDMA_SQ_FMR_WQE_RD_FENCE_FLG_SHIFT
- RDMA_SQ_FMR_WQE_REMOTE_READ_MASK
- RDMA_SQ_FMR_WQE_REMOTE_READ_SHIFT
- RDMA_SQ_FMR_WQE_REMOTE_WRITE_MASK
- RDMA_SQ_FMR_WQE_REMOTE_WRITE_SHIFT
- RDMA_SQ_FMR_WQE_RESERVED0_MASK
- RDMA_SQ_FMR_WQE_RESERVED0_SHIFT
- RDMA_SQ_FMR_WQE_RESERVED1_MASK
- RDMA_SQ_FMR_WQE_RESERVED1_SHIFT
- RDMA_SQ_FMR_WQE_RESERVED2_MASK
- RDMA_SQ_FMR_WQE_RESERVED2_SHIFT
- RDMA_SQ_FMR_WQE_SE_FLG_MASK
- RDMA_SQ_FMR_WQE_SE_FLG_SHIFT
- RDMA_SQ_FMR_WQE_ZERO_BASED_MASK
- RDMA_SQ_FMR_WQE_ZERO_BASED_SHIFT
- RDMA_SQ_LOCAL_INV_WQE_COMP_FLG_MASK
- RDMA_SQ_LOCAL_INV_WQE_COMP_FLG_SHIFT
- RDMA_SQ_LOCAL_INV_WQE_DIF_ON_HOST_FLG_MASK
- RDMA_SQ_LOCAL_INV_WQE_DIF_ON_HOST_FLG_SHIFT
- RDMA_SQ_LOCAL_INV_WQE_INLINE_FLG_MASK
- RDMA_SQ_LOCAL_INV_WQE_INLINE_FLG_SHIFT
- RDMA_SQ_LOCAL_INV_WQE_INV_FENCE_FLG_MASK
- RDMA_SQ_LOCAL_INV_WQE_INV_FENCE_FLG_SHIFT
- RDMA_SQ_LOCAL_INV_WQE_RD_FENCE_FLG_MASK
- RDMA_SQ_LOCAL_INV_WQE_RD_FENCE_FLG_SHIFT
- RDMA_SQ_LOCAL_INV_WQE_RESERVED0_MASK
- RDMA_SQ_LOCAL_INV_WQE_RESERVED0_SHIFT
- RDMA_SQ_LOCAL_INV_WQE_SE_FLG_MASK
- RDMA_SQ_LOCAL_INV_WQE_SE_FLG_SHIFT
- RDMA_SQ_RDMA_WQE_1ST_COMP_FLG_MASK
- RDMA_SQ_RDMA_WQE_1ST_COMP_FLG_SHIFT
- RDMA_SQ_RDMA_WQE_1ST_DIF_ON_HOST_FLG_MASK
- RDMA_SQ_RDMA_WQE_1ST_DIF_ON_HOST_FLG_SHIFT
- RDMA_SQ_RDMA_WQE_1ST_INLINE_FLG_MASK
- RDMA_SQ_RDMA_WQE_1ST_INLINE_FLG_SHIFT
- RDMA_SQ_RDMA_WQE_1ST_INV_FENCE_FLG_MASK
- RDMA_SQ_RDMA_WQE_1ST_INV_FENCE_FLG_SHIFT
- RDMA_SQ_RDMA_WQE_1ST_RD_FENCE_FLG_MASK
- RDMA_SQ_RDMA_WQE_1ST_RD_FENCE_FLG_SHIFT
- RDMA_SQ_RDMA_WQE_1ST_READ_INV_FLG_MASK
- RDMA_SQ_RDMA_WQE_1ST_READ_INV_FLG_SHIFT
- RDMA_SQ_RDMA_WQE_1ST_RESERVED0_MASK
- RDMA_SQ_RDMA_WQE_1ST_RESERVED0_SHIFT
- RDMA_SQ_RDMA_WQE_1ST_SE_FLG_MASK
- RDMA_SQ_RDMA_WQE_1ST_SE_FLG_SHIFT
- RDMA_SQ_RDMA_WQE_2ND_DIF_BLOCK_SIZE_MASK
- RDMA_SQ_RDMA_WQE_2ND_DIF_BLOCK_SIZE_SHIFT
- RDMA_SQ_RDMA_WQE_2ND_DIF_FIRST_SEGMENT_FLG_MASK
- RDMA_SQ_RDMA_WQE_2ND_DIF_FIRST_SEGMENT_FLG_SHIFT
- RDMA_SQ_RDMA_WQE_2ND_DIF_LAST_SEGMENT_FLG_MASK
- RDMA_SQ_RDMA_WQE_2ND_DIF_LAST_SEGMENT_FLG_SHIFT
- RDMA_SQ_RDMA_WQE_2ND_RESERVED1_MASK
- RDMA_SQ_RDMA_WQE_2ND_RESERVED1_SHIFT
- RDMA_SQ_RDMA_WQE_COMP_FLG_MASK
- RDMA_SQ_RDMA_WQE_COMP_FLG_SHIFT
- RDMA_SQ_RDMA_WQE_DIF_BLOCK_SIZE_MASK
- RDMA_SQ_RDMA_WQE_DIF_BLOCK_SIZE_SHIFT
- RDMA_SQ_RDMA_WQE_DIF_ON_HOST_FLG_MASK
- RDMA_SQ_RDMA_WQE_DIF_ON_HOST_FLG_SHIFT
- RDMA_SQ_RDMA_WQE_INLINE_FLG_MASK
- RDMA_SQ_RDMA_WQE_INLINE_FLG_SHIFT
- RDMA_SQ_RDMA_WQE_INV_FENCE_FLG_MASK
- RDMA_SQ_RDMA_WQE_INV_FENCE_FLG_SHIFT
- RDMA_SQ_RDMA_WQE_RD_FENCE_FLG_MASK
- RDMA_SQ_RDMA_WQE_RD_FENCE_FLG_SHIFT
- RDMA_SQ_RDMA_WQE_READ_INV_FLG_MASK
- RDMA_SQ_RDMA_WQE_READ_INV_FLG_SHIFT
- RDMA_SQ_RDMA_WQE_RESERVED1_MASK
- RDMA_SQ_RDMA_WQE_RESERVED1_SHIFT
- RDMA_SQ_RDMA_WQE_RESERVED2_MASK
- RDMA_SQ_RDMA_WQE_RESERVED2_SHIFT
- RDMA_SQ_RDMA_WQE_SE_FLG_MASK
- RDMA_SQ_RDMA_WQE_SE_FLG_SHIFT
- RDMA_SQ_REQ_TYPE_ATOMIC_ADD
- RDMA_SQ_REQ_TYPE_ATOMIC_CMP_AND_SWAP
- RDMA_SQ_REQ_TYPE_BIND
- RDMA_SQ_REQ_TYPE_FAST_MR
- RDMA_SQ_REQ_TYPE_INVALID
- RDMA_SQ_REQ_TYPE_LOCAL_INVALIDATE
- RDMA_SQ_REQ_TYPE_RDMA_RD
- RDMA_SQ_REQ_TYPE_RDMA_WR
- RDMA_SQ_REQ_TYPE_RDMA_WR_WITH_IMM
- RDMA_SQ_REQ_TYPE_SEND
- RDMA_SQ_REQ_TYPE_SEND_WITH_IMM
- RDMA_SQ_REQ_TYPE_SEND_WITH_INVALIDATE
- RDMA_SQ_SEND_WQE_1ST_COMP_FLG_MASK
- RDMA_SQ_SEND_WQE_1ST_COMP_FLG_SHIFT
- RDMA_SQ_SEND_WQE_1ST_INLINE_FLG_MASK
- RDMA_SQ_SEND_WQE_1ST_INLINE_FLG_SHIFT
- RDMA_SQ_SEND_WQE_1ST_INV_FENCE_FLG_MASK
- RDMA_SQ_SEND_WQE_1ST_INV_FENCE_FLG_SHIFT
- RDMA_SQ_SEND_WQE_1ST_RD_FENCE_FLG_MASK
- RDMA_SQ_SEND_WQE_1ST_RD_FENCE_FLG_SHIFT
- RDMA_SQ_SEND_WQE_1ST_RESERVED0_MASK
- RDMA_SQ_SEND_WQE_1ST_RESERVED0_SHIFT
- RDMA_SQ_SEND_WQE_1ST_SE_FLG_MASK
- RDMA_SQ_SEND_WQE_1ST_SE_FLG_SHIFT
- RDMA_SQ_SEND_WQE_COMP_FLG_MASK
- RDMA_SQ_SEND_WQE_COMP_FLG_SHIFT
- RDMA_SQ_SEND_WQE_DIF_ON_HOST_FLG_MASK
- RDMA_SQ_SEND_WQE_DIF_ON_HOST_FLG_SHIFT
- RDMA_SQ_SEND_WQE_INLINE_FLG_MASK
- RDMA_SQ_SEND_WQE_INLINE_FLG_SHIFT
- RDMA_SQ_SEND_WQE_INV_FENCE_FLG_MASK
- RDMA_SQ_SEND_WQE_INV_FENCE_FLG_SHIFT
- RDMA_SQ_SEND_WQE_RD_FENCE_FLG_MASK
- RDMA_SQ_SEND_WQE_RD_FENCE_FLG_SHIFT
- RDMA_SQ_SEND_WQE_RESERVED0_MASK
- RDMA_SQ_SEND_WQE_RESERVED0_SHIFT
- RDMA_SQ_SEND_WQE_SE_FLG_MASK
- RDMA_SQ_SEND_WQE_SE_FLG_SHIFT
- RDMA_SRC_I_N
- RDMA_SRC_I_P
- RDMA_SRC_O_N
- RDMA_SRC_O_P
- RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_MASK
- RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_SHIFT
- RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_MASK
- RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_SHIFT
- RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_MASK
- RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_SHIFT
- RDMA_SSIU_I_N
- RDMA_SSIU_I_P
- RDMA_SSIU_O_N
- RDMA_SSIU_O_P
- RDMA_SSI_I_N
- RDMA_SSI_O_N
- RDMA_START_ADDR_HI
- RDMA_START_ADDR_LO
- RDMA_STATE
- RDMA_STATUS
- RDMA_STATUS2
- RDMA_STATUS3
- RDMA_TARGET_LINE_INT
- RDMA_TASK_TYPE
- RDMA_TEST
- RDMA_TID_FMR
- RDMA_TID_MW
- RDMA_TID_REGISTERED_MR
- RDMA_TIMEOUT_MASK
- RDMA_TIMEOUT_SHIFT
- RDMA_TP_OUT_SEL
- RDMA_TRANSPORT_IB
- RDMA_TRANSPORT_IWARP
- RDMA_TRANSPORT_UNSPECIFIED
- RDMA_TRANSPORT_USNIC
- RDMA_TRANSPORT_USNIC_UDP
- RDMA_UAPI_PTR
- RDMA_UDP_QKEY
- RDMA_USER_CM_ABI_VERSION
- RDMA_USER_CM_CMD_ACCEPT
- RDMA_USER_CM_CMD_BIND
- RDMA_USER_CM_CMD_BIND_IP
- RDMA_USER_CM_CMD_CONNECT
- RDMA_USER_CM_CMD_CREATE_ID
- RDMA_USER_CM_CMD_DESTROY_ID
- RDMA_USER_CM_CMD_DISCONNECT
- RDMA_USER_CM_CMD_GET_EVENT
- RDMA_USER_CM_CMD_GET_OPTION
- RDMA_USER_CM_CMD_INIT_QP_ATTR
- RDMA_USER_CM_CMD_JOIN_IP_MCAST
- RDMA_USER_CM_CMD_JOIN_MCAST
- RDMA_USER_CM_CMD_LEAVE_MCAST
- RDMA_USER_CM_CMD_LISTEN
- RDMA_USER_CM_CMD_MIGRATE_ID
- RDMA_USER_CM_CMD_NOTIFY
- RDMA_USER_CM_CMD_QUERY
- RDMA_USER_CM_CMD_QUERY_ROUTE
- RDMA_USER_CM_CMD_REJECT
- RDMA_USER_CM_CMD_RESOLVE_ADDR
- RDMA_USER_CM_CMD_RESOLVE_IP
- RDMA_USER_CM_CMD_RESOLVE_ROUTE
- RDMA_USER_CM_CMD_SET_OPTION
- RDMA_USER_CM_H
- RDMA_USER_CM_QUERY_ADDR
- RDMA_USER_CM_QUERY_GID
- RDMA_USER_CM_QUERY_PATH
- RDMA_USER_IOCTL_CMDS_H
- RDMA_USER_IOCTL_H
- RDMA_USER_RXE_H
- RDMA_VERBS_IOCTL
- RDMA_WRITE_FIRST
- RDMA_WRITE_LAST
- RDMA_WRITE_LAST_WITH_IMMEDIATE
- RDMA_WRITE_MIDDLE
- RDMA_WRITE_ONLY
- RDMA_WRITE_ONLY_WITH_IMMEDIATE
- RDMA_WRITE_PTR
- RDMA_WRITE_PTR_HI
- RDMA_WRITE_PTR_LO
- RDMA_WRITE_UAPI_ATOMIC
- RDMA_XOFF_THRESH_SHIFT
- RDMA_XON_XOFF_THRESH
- RDMA_XON_XOFF_THRESH_MASK
- RDMC_MEM_ADDR
- RDMC_MEM_ADDR_ADDR
- RDMC_MEM_ADDR_PRE_SHAD
- RDMC_MEM_DAT0
- RDMC_MEM_DAT0_DATA
- RDMC_MEM_DAT1
- RDMC_MEM_DAT1_DATA
- RDMC_MEM_DAT2
- RDMC_MEM_DAT2_DATA
- RDMC_MEM_DAT3
- RDMC_MEM_DAT3_DATA
- RDMC_MEM_DAT4
- RDMC_MEM_DAT4_DATA
- RDMC_PRE_PAR_ERR
- RDMC_PRE_PAR_ERR_ADDR
- RDMC_PRE_PAR_ERR_ERR
- RDMC_PRE_PAR_ERR_MERR
- RDMC_SHA_PAR_ERR
- RDMC_SHA_PAR_ERR_ADDR
- RDMC_SHA_PAR_ERR_ERR
- RDMC_SHA_PAR_ERR_MERR
- RDMC_TRAINING_VECTOR
- RDMC_TRAINING_VECTOR_TRAINING_VECTOR
- RDMD0
- RDMEM
- RDMLR
- RDMN
- RDMR
- RDMUX
- RDM_CFG0
- RDM_CFG0_POLY
- RDM_CFG1
- RDM_CFG1_RDM_EN
- RDM_CFG1_SEED
- RDM_DAT_OUT_1
- RDM_DAT_OUT_2
- RDM_RX_DMA_DESC_CACHE_INIT_DONE_ADR
- RDM_RX_DMA_DESC_CACHE_INIT_DONE_DEFAULT
- RDM_RX_DMA_DESC_CACHE_INIT_DONE_MSK
- RDM_RX_DMA_DESC_CACHE_INIT_DONE_MSKN
- RDM_RX_DMA_DESC_CACHE_INIT_DONE_SHIFT
- RDM_RX_DMA_DESC_CACHE_INIT_DONE_WIDTH
- RDNOP
- RDOC3
- RDOCM
- RDONCE
- RDOORBELL32
- RDOORBELL64
- RDOUTDOOR
- RDO_BATT
- RDO_BATT_MAX_PWR
- RDO_BATT_MAX_PWR_SHIFT
- RDO_BATT_OP_PWR
- RDO_BATT_OP_PWR_SHIFT
- RDO_CAP_MISMATCH
- RDO_CURR_MASK
- RDO_FIXED
- RDO_FIXED_MAX_CURR_SHIFT
- RDO_FIXED_OP_CURR_SHIFT
- RDO_GIVE_BACK
- RDO_NO_SUSPEND
- RDO_OBJ
- RDO_OBJ_POS_MASK
- RDO_OBJ_POS_SHIFT
- RDO_PROG
- RDO_PROG_CURR_MASK
- RDO_PROG_CURR_MA_STEP
- RDO_PROG_CURR_SHIFT
- RDO_PROG_VOLT_MASK
- RDO_PROG_VOLT_MV_STEP
- RDO_PROG_VOLT_SHIFT
- RDO_PWR_MASK
- RDO_USB_COMM
- RDP
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON_MASK
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN_MASK
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN__SHIFT
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS_MASK
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS__SHIFT
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN_MASK
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN__SHIFT
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN_MASK
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN__SHIFT
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN_MASK
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN__SHIFT
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN_MASK
- RDPCSTX0_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN__SHIFT
- RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK
- RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT
- RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK
- RDPCSTX0_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK
- RDPCSTX0_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT
- RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0_MASK
- RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0__SHIFT
- RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1_MASK
- RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1__SHIFT
- RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2_MASK
- RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2__SHIFT
- RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3_MASK
- RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3__SHIFT
- RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB_MASK
- RDPCSTX0_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB__SHIFT
- RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE_MASK
- RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE__SHIFT
- RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MASK
- RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX_MASK
- RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX__SHIFT
- RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT__SHIFT
- RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN_MASK
- RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN__SHIFT
- RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT_MASK
- RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT__SHIFT
- RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP_MASK
- RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP__SHIFT
- RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK_MASK
- RDPCSTX0_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK
- RDPCSTX0_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT
- RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK
- RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT
- RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK
- RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT
- RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK
- RDPCSTX0_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK
- RDPCSTX0_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK
- RDPCSTX0_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT
- RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK
- RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT
- RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK
- RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT
- RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK
- RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT
- RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK
- RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK
- RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT
- RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK
- RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK
- RDPCSTX0_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT
- RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK
- RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT
- RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK
- RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT
- RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK
- RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK
- RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT
- RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK
- RDPCSTX0_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK
- RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT
- RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK
- RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK
- RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT
- RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK
- RDPCSTX0_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK
- RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK
- RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK
- RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT
- RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK
- RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT
- RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK
- RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT
- RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK
- RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT
- RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK
- RDPCSTX0_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT
- RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK
- RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT
- RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK
- RDPCSTX0_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT
- RDPCSTX0_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK
- RDPCSTX0_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT
- RDPCSTX0_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK
- RDPCSTX0_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT
- RDPCSTX0_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK
- RDPCSTX0_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT
- RDPCSTX0_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK
- RDPCSTX0_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT
- RDPCSTX0_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK
- RDPCSTX0_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT
- RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK
- RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT
- RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK
- RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT
- RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK
- RDPCSTX0_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON_MASK
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN_MASK
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN__SHIFT
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS_MASK
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS__SHIFT
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN_MASK
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN__SHIFT
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN_MASK
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN__SHIFT
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN_MASK
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN__SHIFT
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN_MASK
- RDPCSTX1_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN__SHIFT
- RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK
- RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT
- RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK
- RDPCSTX1_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK
- RDPCSTX1_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT
- RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0_MASK
- RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0__SHIFT
- RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1_MASK
- RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1__SHIFT
- RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2_MASK
- RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2__SHIFT
- RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3_MASK
- RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3__SHIFT
- RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB_MASK
- RDPCSTX1_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB__SHIFT
- RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE_MASK
- RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE__SHIFT
- RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MASK
- RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX_MASK
- RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX__SHIFT
- RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT__SHIFT
- RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN_MASK
- RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN__SHIFT
- RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT_MASK
- RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT__SHIFT
- RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP_MASK
- RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP__SHIFT
- RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK_MASK
- RDPCSTX1_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK
- RDPCSTX1_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT
- RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK
- RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT
- RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK
- RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT
- RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK
- RDPCSTX1_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK
- RDPCSTX1_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK
- RDPCSTX1_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT
- RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK
- RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT
- RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK
- RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT
- RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK
- RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT
- RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK
- RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK
- RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT
- RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK
- RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK
- RDPCSTX1_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT
- RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK
- RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT
- RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK
- RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT
- RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK
- RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK
- RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT
- RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK
- RDPCSTX1_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK
- RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT
- RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK
- RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK
- RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT
- RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK
- RDPCSTX1_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK
- RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK
- RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK
- RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT
- RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK
- RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT
- RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK
- RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT
- RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK
- RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT
- RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK
- RDPCSTX1_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT
- RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK
- RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT
- RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK
- RDPCSTX1_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT
- RDPCSTX1_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK
- RDPCSTX1_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT
- RDPCSTX1_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK
- RDPCSTX1_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT
- RDPCSTX1_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK
- RDPCSTX1_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT
- RDPCSTX1_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK
- RDPCSTX1_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT
- RDPCSTX1_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK
- RDPCSTX1_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT
- RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK
- RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT
- RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK
- RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT
- RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK
- RDPCSTX1_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON_MASK
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN_MASK
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN__SHIFT
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS_MASK
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS__SHIFT
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN_MASK
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN__SHIFT
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN_MASK
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN__SHIFT
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN_MASK
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN__SHIFT
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN_MASK
- RDPCSTX2_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN__SHIFT
- RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK
- RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT
- RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK
- RDPCSTX2_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK
- RDPCSTX2_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT
- RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0_MASK
- RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0__SHIFT
- RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1_MASK
- RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1__SHIFT
- RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2_MASK
- RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2__SHIFT
- RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3_MASK
- RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3__SHIFT
- RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB_MASK
- RDPCSTX2_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB__SHIFT
- RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE_MASK
- RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE__SHIFT
- RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MASK
- RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX_MASK
- RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX__SHIFT
- RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT__SHIFT
- RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN_MASK
- RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN__SHIFT
- RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT_MASK
- RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT__SHIFT
- RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP_MASK
- RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP__SHIFT
- RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK_MASK
- RDPCSTX2_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK
- RDPCSTX2_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT
- RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK
- RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT
- RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK
- RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT
- RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK
- RDPCSTX2_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK
- RDPCSTX2_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK
- RDPCSTX2_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT
- RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK
- RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT
- RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK
- RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT
- RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK
- RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT
- RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK
- RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK
- RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT
- RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK
- RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK
- RDPCSTX2_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT
- RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK
- RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT
- RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK
- RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT
- RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK
- RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK
- RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT
- RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK
- RDPCSTX2_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK
- RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT
- RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK
- RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK
- RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT
- RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK
- RDPCSTX2_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK
- RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK
- RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK
- RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT
- RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK
- RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT
- RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK
- RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT
- RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK
- RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT
- RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK
- RDPCSTX2_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT
- RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK
- RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT
- RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK
- RDPCSTX2_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT
- RDPCSTX2_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK
- RDPCSTX2_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT
- RDPCSTX2_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK
- RDPCSTX2_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT
- RDPCSTX2_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK
- RDPCSTX2_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT
- RDPCSTX2_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK
- RDPCSTX2_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT
- RDPCSTX2_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK
- RDPCSTX2_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT
- RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK
- RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT
- RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK
- RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT
- RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK
- RDPCSTX2_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON_MASK
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN_MASK
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN__SHIFT
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS_MASK
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS__SHIFT
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN_MASK
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN__SHIFT
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN_MASK
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN__SHIFT
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN_MASK
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN__SHIFT
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN_MASK
- RDPCSTX3_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN__SHIFT
- RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK
- RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT
- RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK
- RDPCSTX3_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK
- RDPCSTX3_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT
- RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0_MASK
- RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0__SHIFT
- RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1_MASK
- RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1__SHIFT
- RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2_MASK
- RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2__SHIFT
- RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3_MASK
- RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3__SHIFT
- RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB_MASK
- RDPCSTX3_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB__SHIFT
- RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE_MASK
- RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE__SHIFT
- RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MASK
- RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX_MASK
- RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX__SHIFT
- RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT__SHIFT
- RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN_MASK
- RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN__SHIFT
- RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT_MASK
- RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT__SHIFT
- RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP_MASK
- RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP__SHIFT
- RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK_MASK
- RDPCSTX3_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK
- RDPCSTX3_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT
- RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK
- RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT
- RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK
- RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT
- RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK
- RDPCSTX3_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK
- RDPCSTX3_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK
- RDPCSTX3_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT
- RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK
- RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT
- RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK
- RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT
- RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK
- RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT
- RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK
- RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK
- RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT
- RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK
- RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK
- RDPCSTX3_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT
- RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK
- RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT
- RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK
- RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT
- RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK
- RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK
- RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT
- RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK
- RDPCSTX3_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK
- RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT
- RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK
- RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK
- RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT
- RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK
- RDPCSTX3_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK
- RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK
- RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK
- RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT
- RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK
- RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT
- RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK
- RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT
- RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK
- RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT
- RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK
- RDPCSTX3_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT
- RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK
- RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT
- RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK
- RDPCSTX3_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT
- RDPCSTX3_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK
- RDPCSTX3_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT
- RDPCSTX3_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK
- RDPCSTX3_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT
- RDPCSTX3_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK
- RDPCSTX3_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT
- RDPCSTX3_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK
- RDPCSTX3_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT
- RDPCSTX3_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK
- RDPCSTX3_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT
- RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK
- RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT
- RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK
- RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT
- RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK
- RDPCSTX3_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN_MASK
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_EXT_REFCLK_EN__SHIFT
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON_MASK
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_CLOCK_ON__SHIFT
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN_MASK
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_EN__SHIFT
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS_MASK
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_OCLACLK_GATE_DIS__SHIFT
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS_MASK
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_BYPASS__SHIFT
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON_MASK
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_CLOCK_ON__SHIFT
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN_MASK
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_EN__SHIFT
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS_MASK
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SRAMCLK_GATE_DIS__SHIFT
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON_MASK
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN_MASK
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_EN__SHIFT
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS_MASK
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_GATE_DIS__SHIFT
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN_MASK
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX0_EN__SHIFT
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN_MASK
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX1_EN__SHIFT
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN_MASK
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX2_EN__SHIFT
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN_MASK
- RDPCSTX4_RDPCSTX_CLOCK_CNTL__RDPCS_SYMCLK_DIV2_TX3_EN__SHIFT
- RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY_MASK
- RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_EMPTY__SHIFT
- RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL_MASK
- RDPCSTX4_RDPCSTX_CNTL2__RDPCS_CR_CONVERT_FIFO_FULL__SHIFT
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET_MASK
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_CBUS_SOFT_RESET__SHIFT
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN_MASK
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_CR_REGISTER_BLOCK_EN__SHIFT
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS_MASK
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_DPALT_BLOCK_STATUS__SHIFT
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN_MASK
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_NON_DPALT_REGISTER_BLOCK_EN__SHIFT
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET_MASK
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_SRAM_SOFT_RESET__SHIFT
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN_MASK
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_EN__SHIFT
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN_MASK
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE0_EN__SHIFT
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN_MASK
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE1_EN__SHIFT
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN_MASK
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE2_EN__SHIFT
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN_MASK
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_LANE3_EN__SHIFT
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY_MASK
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_RD_START_DELAY__SHIFT
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_START_MASK
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_FIFO_START__SHIFT
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET_MASK
- RDPCSTX4_RDPCSTX_CNTL__RDPCS_TX_SOFT_RESET__SHIFT
- RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0_MASK
- RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC0__SHIFT
- RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1_MASK
- RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC1__SHIFT
- RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2_MASK
- RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC2__SHIFT
- RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3_MASK
- RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_SRC3__SHIFT
- RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB_MASK
- RDPCSTX4_RDPCSTX_DEBUG_CONFIG2__RDPCS_DBG_OCLA_VALID_REPLACE_MSB__SHIFT
- RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE_MASK
- RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_EXPIRE__SHIFT
- RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MASK
- RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX_MASK
- RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT_MAX__SHIFT
- RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_CR_COUNT__SHIFT
- RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN_MASK
- RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_EN__SHIFT
- RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT_MASK
- RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_8BIT__SHIFT
- RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP_MASK
- RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_ASYNC_SWAP__SHIFT
- RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK_MASK
- RDPCSTX4_RDPCSTX_DEBUG_CONFIG__RDPCS_DBG_SEL_TEST_CLK__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_CONTROL_SPARE__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_DIS_BLOCK_REG__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG__RDPCS_DMCU_DPALT_FORCE_SYMCLK_DIV2_DIS__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED_MASK
- RDPCSTX4_RDPCSTX_DMCU_DPALT_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_RESERVED__SHIFT
- RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS_MASK
- RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_ALLOW_DRIVER_ACCESS__SHIFT
- RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE_MASK
- RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DPALT_CONTROL_SPARE__SHIFT
- RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED_MASK
- RDPCSTX4_RDPCSTX_DPALT_CONTROL_REG__RDPCS_DRIVER_ACCESS_BLOCKED__SHIFT
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR_MASK
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_CLR__SHIFT
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK_MASK
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE_MASK__SHIFT
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_4LANE_TOGGLE__SHIFT
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR_MASK
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_CLR__SHIFT
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK_MASK
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE_MASK__SHIFT
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_DPALT_DISABLE_TOGGLE__SHIFT
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR_MASK
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_ERROR_CLR__SHIFT
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK_MASK
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_ERROR_MASK__SHIFT
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW_MASK
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_REG_FIFO_OVERFLOW__SHIFT
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR_MASK
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX0_FIFO_ERROR__SHIFT
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR_MASK
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX1_FIFO_ERROR__SHIFT
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR_MASK
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX2_FIFO_ERROR__SHIFT
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR_MASK
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX3_FIFO_ERROR__SHIFT
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR_MASK
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_ERROR_CLR__SHIFT
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK_MASK
- RDPCSTX4_RDPCSTX_INTERRUPT_CONTROL__RDPCS_TX_FIFO_ERROR_MASK__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_MUX_SEL__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_CR_PARA_SEL__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_DTB_OUT__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_HDMIMODE_ENABLE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_CLKDET_RESULT__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_REF_RANGE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RESET__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_ACK__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_RTUNE_REQ__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_APB_RESET_N__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TCA_PHY_RESET__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_PHY_TEST_POWERDOWN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_BYPASS__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_EXT_LD_DONE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL0__RDPCS_SRAM_INIT_DONE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL10__RDPCS_PHY_DP_MPLLB_FRACN_REM__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_MPLLB_MULTIPLIER__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_DP_REF_CLK_MPLLB_DIV__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_DIV__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL11__RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_SSC_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_STATE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_TX_CLK_DIV__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL12__RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_CLK_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_FORCE_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL13__RDPCS_PHY_DP_MPLLB_INIT_CAL_DISABLE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_CAL_FORCE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_FRACN_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL14__RDPCS_PHY_DP_MPLLB_PMIX_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX0_VREGDRV_BYP__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX1_VREGDRV_BYP__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX2_VREGDRV_BYP__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_DP_TX3_VREGDRV_BYP__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SSTX_VREGDRV_BYP__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL15__RDPCS_PHY_SUP_PRE_HP__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_CMN_OUT_GENERIC_BUS__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX0_OUT_GENERIC_BUS__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX1_OUT_GENERIC_BUS__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX2_OUT_GENERIC_BUS__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL16__RDPCS_PHY_DP_TX3_OUT_GENERIC_BUS__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_CMN_IN_GENERIC_BUS__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX0_IN_GENERIC_BUS__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX1_IN_GENERIC_BUS__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX2_IN_GENERIC_BUS__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL17__RDPCS_PHY_DP_TX3_IN_GENERIC_BUS__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_ANA_PWR_STABLE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_DP_PG_RESET__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PCS_PWR_STABLE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PG_MODE_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL1__RDPCS_PHY_PMA_PWR_STABLE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP4_POR__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_RX2TX_PAR_LB_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE0_TX2RX_SER_LB_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_RX2TX_PAR_LB_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE1_TX2RX_SER_LB_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_RX2TX_PAR_LB_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE2_TX2RX_SER_LB_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_RX2TX_PAR_LB_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL2__RDPCS_PHY_DP_LANE3_TX2RX_SER_LB_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_ACK__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_CLK_RDY__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DATA_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_DISABLE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_REQ__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX0_RESET__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_ACK__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_CLK_RDY__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DATA_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_DISABLE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_REQ__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX1_RESET__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_ACK__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_CLK_RDY__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DATA_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_DISABLE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_REQ__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX2_RESET__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_ACK__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_CLK_RDY__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DATA_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_DISABLE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_REQ__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL3__RDPCS_PHY_DP_TX3_RESET__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_BYPASS_EQ_CALC__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_HP_PROT_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_INVERT__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX0_TERM_CTRL__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_BYPASS_EQ_CALC__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_HP_PROT_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_INVERT__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX1_TERM_CTRL__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_BYPASS_EQ_CALC__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_HP_PROT_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_INVERT__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX2_TERM_CTRL__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_BYPASS_EQ_CALC__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_HP_PROT_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_INVERT__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL4__RDPCS_PHY_DP_TX3_TERM_CTRL__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_REQ__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_DETRX_RESULT__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_LPD__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_RATE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX0_WIDTH__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_REQ__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_DETRX_RESULT__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_LPD__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_RATE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX1_WIDTH__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_REQ__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_DETRX_RESULT__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_LPD__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_RATE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX2_WIDTH__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_REQ__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_DETRX_RESULT__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_LPD__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_RATE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL5__RDPCS_PHY_DP_TX3_WIDTH__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_ACK__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DISABLE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DPALT_DP4__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_REF_CLK_REQ__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_MPLL_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX0_PSTATE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_MPLL_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX1_PSTATE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_MPLL_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX2_PSTATE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_MPLL_EN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL6__RDPCS_PHY_DP_TX3_PSTATE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_DEN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL7__RDPCS_PHY_DP_MPLLB_FRACN_QUOT__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL8__RDPCS_PHY_DP_MPLLB_SSC_PEAK__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD_MASK
- RDPCSTX4_RDPCSTX_PHY_CNTL9__RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD__SHIFT
- RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS_MASK
- RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_CP_INT_GS__SHIFT
- RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO_MASK
- RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_FREQ_VCO__SHIFT
- RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I_MASK
- RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_MPLLB_V2I__SHIFT
- RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN_MASK
- RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_MAIN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST_MASK
- RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_POST__SHIFT
- RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE_MASK
- RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_DP_TX0_EQ_PRE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL_MASK
- RDPCSTX4_RDPCSTX_PHY_FUSE0__RDPCS_PHY_RX_VREF_CTRL__SHIFT
- RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT_MASK
- RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_INT__SHIFT
- RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP_MASK
- RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_MPLLB_CP_PROP__SHIFT
- RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN_MASK
- RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_MAIN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST_MASK
- RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_POST__SHIFT
- RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE_MASK
- RDPCSTX4_RDPCSTX_PHY_FUSE1__RDPCS_PHY_DP_TX1_EQ_PRE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS_MASK
- RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_MPLLB_CP_PROP_GS__SHIFT
- RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN_MASK
- RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_MAIN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST_MASK
- RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_POST__SHIFT
- RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE_MASK
- RDPCSTX4_RDPCSTX_PHY_FUSE2__RDPCS_PHY_DP_TX2_EQ_PRE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE_MASK
- RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_FINETUNE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE_MASK
- RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DCO_RANGE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN_MASK
- RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_MAIN__SHIFT
- RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST_MASK
- RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_POST__SHIFT
- RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE_MASK
- RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_DP_TX3_EQ_PRE__SHIFT
- RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL_MASK
- RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_SUP_RX_VCO_VREF_SEL__SHIFT
- RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL_MASK
- RDPCSTX4_RDPCSTX_PHY_FUSE3__RDPCS_PHY_TX_VBOOST_LVL__SHIFT
- RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL_MASK
- RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_REF_LD_VAL__SHIFT
- RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL_MASK
- RDPCSTX4_RDPCSTX_PHY_RX_LD_VAL__RDPCS_PHY_RX_VCO_LD_VAL__SHIFT
- RDPCSTX4_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA_MASK
- RDPCSTX4_RDPCSTX_PLL_UPDATE_DATA__RDPCS_PLL_UPDATE_DATA__SHIFT
- RDPCSTX4_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH_MASK
- RDPCSTX4_RDPCSTX_SCRATCH__RDPCSTX_SCRATCH__SHIFT
- RDPCSTX4_RDPCSTX_SPARE__RDPCSTX_SPARE_MASK
- RDPCSTX4_RDPCSTX_SPARE__RDPCSTX_SPARE__SHIFT
- RDPCSTX4_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR_MASK
- RDPCSTX4_RDPCS_TX_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT
- RDPCSTX4_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA_MASK
- RDPCSTX4_RDPCS_TX_CR_DATA__RDPCS_TX_CR_DATA__SHIFT
- RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS_MASK
- RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_DIS__SHIFT
- RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE_MASK
- RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_FORCE__SHIFT
- RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE_MASK
- RDPCSTX4_RDPCS_TX_SRAM_CNTL__RDPCS_MEM_PWR_PWR_STATE__SHIFT
- RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN
- RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS
- RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON
- RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN
- RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS
- RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON
- RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN
- RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS
- RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN
- RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET
- RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET
- RDPCSTX_CNTL_RDPCS_TX_FIFO_EN
- RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN
- RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET
- RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE
- RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK
- RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE
- RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK
- RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK
- RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK
- RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF
- RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL
- RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL
- RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE
- RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE
- RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE
- RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV
- RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV
- RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV
- RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL
- RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT
- RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE
- RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH
- RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE
- RDPCS_CBUS_SOFT_RESET_DISABLE
- RDPCS_CBUS_SOFT_RESET_ENABLE
- RDPCS_DPALT_4LANE_TOGGLE_2LANE
- RDPCS_DPALT_4LANE_TOGGLE_4LANE
- RDPCS_DPALT_4LANE_TOGGLE_MASK_DISABLE
- RDPCS_DPALT_4LANE_TOGGLE_MASK_ENABLE
- RDPCS_DPALT_DISABLE_TOGGLE_DISABLE
- RDPCS_DPALT_DISABLE_TOGGLE_ENABLE
- RDPCS_DPALT_DISABLE_TOGGLE_MASK_DISABLE
- RDPCS_DPALT_DISABLE_TOGGLE_MASK_ENABLE
- RDPCS_EXT_REFCLK_DISABLE
- RDPCS_EXT_REFCLK_ENABLE
- RDPCS_EXT_REFCLK_EN_DISABLE
- RDPCS_EXT_REFCLK_EN_ENABLE
- RDPCS_MEM_POWER_CTRL_POFF_FOR_NO_PERIPHERY
- RDPCS_MEM_POWER_CTRL_POFF_FOR_RM3
- RDPCS_MEM_POWER_CTRL_POFF_FOR_SD
- RDPCS_MEM_POWER_CTRL_POFF_FOR_STANDARD
- RDPCS_MEM_PWR_DEEP_SLEEP
- RDPCS_MEM_PWR_LIGHT_SLEEP
- RDPCS_MEM_PWR_NO_FORCE
- RDPCS_MEM_PWR_PWR_STATE_DEEP_SLEEP
- RDPCS_MEM_PWR_PWR_STATE_LIGHT_SLEEP
- RDPCS_MEM_PWR_PWR_STATE_ON
- RDPCS_MEM_PWR_PWR_STATE_SHUT_DOWN
- RDPCS_MEM_PWR_SHUT_DOWN
- RDPCS_PHY_CR_MUX_SEL_FOR_DC
- RDPCS_PHY_CR_MUX_SEL_FOR_USB
- RDPCS_PHY_CR_PARA_SEL_CR
- RDPCS_PHY_CR_PARA_SEL_JTAG
- RDPCS_PHY_DP_MPLLB_TX_CLK_DIV
- RDPCS_PHY_DP_MPLLB_TX_CLK_DIV10
- RDPCS_PHY_DP_MPLLB_TX_CLK_DIV2
- RDPCS_PHY_DP_MPLLB_TX_CLK_DIV3
- RDPCS_PHY_DP_MPLLB_TX_CLK_DIV4
- RDPCS_PHY_DP_MPLLB_TX_CLK_DIV5
- RDPCS_PHY_DP_MPLLB_TX_CLK_DIV6
- RDPCS_PHY_DP_MPLLB_TX_CLK_DIV8
- RDPCS_PHY_DP_REF_CLK_MPLLB_DIV1
- RDPCS_PHY_DP_REF_CLK_MPLLB_DIV16
- RDPCS_PHY_DP_REF_CLK_MPLLB_DIV2
- RDPCS_PHY_DP_REF_CLK_MPLLB_DIV3
- RDPCS_PHY_DP_REF_CLK_MPLLB_DIV8
- RDPCS_PHY_DP_TX_DETRX_RESULT_DETECT
- RDPCS_PHY_DP_TX_DETRX_RESULT_NO_DETECT
- RDPCS_PHY_DP_TX_RATE
- RDPCS_PHY_DP_TX_RATE_DIV2
- RDPCS_PHY_DP_TX_RATE_DIV4
- RDPCS_PHY_DP_TX_TERM_CTRL_40
- RDPCS_PHY_DP_TX_TERM_CTRL_42
- RDPCS_PHY_DP_TX_TERM_CTRL_44
- RDPCS_PHY_DP_TX_TERM_CTRL_46
- RDPCS_PHY_DP_TX_TERM_CTRL_48
- RDPCS_PHY_DP_TX_TERM_CTRL_50
- RDPCS_PHY_DP_TX_TERM_CTRL_52
- RDPCS_PHY_DP_TX_TERM_CTRL_54
- RDPCS_PHY_DP_TX_WIDTH_10
- RDPCS_PHY_DP_TX_WIDTH_16
- RDPCS_PHY_DP_TX_WIDTH_20
- RDPCS_PHY_DP_TX_WIDTH_8
- RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0
- RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1
- RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2
- RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3
- RDPCS_PHY_REF_RANGE_0
- RDPCS_PHY_REF_RANGE_1
- RDPCS_PHY_REF_RANGE_2
- RDPCS_PHY_REF_RANGE_3
- RDPCS_PHY_REF_RANGE_4
- RDPCS_PHY_REF_RANGE_5
- RDPCS_PHY_REF_RANGE_6
- RDPCS_PHY_REF_RANGE_7
- RDPCS_REG_FIFO_ERROR_MASK_DISABLE
- RDPCS_REG_FIFO_ERROR_MASK_ENABLE
- RDPCS_SRAMCLK_BYPASS
- RDPCS_SRAMCLK_DISABLE
- RDPCS_SRAMCLK_ENABLE
- RDPCS_SRAMCLK_GATE_DISABLE
- RDPCS_SRAMCLK_GATE_ENABLE
- RDPCS_SRAMCLK_NOT_BYPASS
- RDPCS_SRAM_EXT_LD_DONE
- RDPCS_SRAM_EXT_LD_NOT_DONE
- RDPCS_SRAM_INIT_DONE
- RDPCS_SRAM_INIT_NOT_DONE
- RDPCS_SRAM_SRAM_RESET_DISABLE
- RDPCS_SYMCLK_DIV2_CLOCK_OFF
- RDPCS_SYMCLK_DIV2_CLOCK_ON
- RDPCS_SYMCLK_DIV2_DISABLE
- RDPCS_SYMCLK_DIV2_ENABLE
- RDPCS_SYMCLK_DIV2_GATE_DISABLE
- RDPCS_SYMCLK_DIV2_GATE_ENABLE
- RDPCS_SYMCLK_SRAMCLK_CLOCK_OFF
- RDPCS_SYMCLK_SRAMCLK_CLOCK_ON
- RDPCS_TEST_CLK_SEL
- RDPCS_TEST_CLK_SEL_CFGCLK
- RDPCS_TEST_CLK_SEL_DP_MPLLB_DIV_CLK
- RDPCS_TEST_CLK_SEL_DP_TX0_WORD_CLK
- RDPCS_TEST_CLK_SEL_DP_TX1_WORD_CLK
- RDPCS_TEST_CLK_SEL_DP_TX2_WORD_CLK
- RDPCS_TEST_CLK_SEL_DP_TX3_WORD_CLK
- RDPCS_TEST_CLK_SEL_EXT_CR_CLK
- RDPCS_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK
- RDPCS_TEST_CLK_SEL_NONE
- RDPCS_TEST_CLK_SEL_PHY_REF_DIG_CLK
- RDPCS_TEST_CLK_SEL_REF_DIG_FR_clk
- RDPCS_TEST_CLK_SEL_SRAMCLK
- RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS
- RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4
- RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS
- RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4
- RDPCS_TEST_CLK_SEL_dtb_out0
- RDPCS_TEST_CLK_SEL_dtb_out1
- RDPCS_TX_FIFO_DISABLE
- RDPCS_TX_FIFO_ENABLE
- RDPCS_TX_FIFO_ERROR_MASK_DISABLE
- RDPCS_TX_FIFO_ERROR_MASK_ENABLE
- RDPCS_TX_FIFO_LANE_DISABLE
- RDPCS_TX_FIFO_LANE_ENABLE
- RDPCS_TX_SOFT_RESET_DISABLE
- RDPCS_TX_SOFT_RESET_ENABLE
- RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE
- RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE
- RDPE_F
- RDPE_S
- RDPE_V
- RDPKTLN
- RDPMC_BASE_LLC
- RDPMC_BASE_NB
- RDPQ_MAX_CHUNK_COUNT
- RDPQ_MAX_INDEX_IN_ONE_CHUNK
- RDP_BBC_DESC_TAG
- RDP_CAP_UNKNOWN
- RDP_CAP_USER_CONFIGURED
- RDP_FEC_DESC_TAG
- RDP_LINK_ERROR_STATUS_DESC_TAG
- RDP_LINK_SERVICE_DESC_TAG
- RDP_NPORT_ID_SIZE
- RDP_N_PORT_DESC_TAG
- RDP_OED_DESC_TAG
- RDP_OED_RXPOWER
- RDP_OED_TEMPERATURE
- RDP_OED_TXBIAS
- RDP_OED_TXPOWER
- RDP_OED_TYPE_SHIFT
- RDP_OED_VOLTAGE
- RDP_OET_HIGH_ALARM
- RDP_OET_HIGH_WARNING
- RDP_OET_LOW_ALARM
- RDP_OET_LOW_WARNING
- RDP_OPD_DESC_TAG
- RDP_PORT_NAMES_DESC_TAG
- RDP_PORT_SPEED_DESC_TAG
- RDP_PS_10GB
- RDP_PS_128GB
- RDP_PS_16GB
- RDP_PS_1GB
- RDP_PS_256GB
- RDP_PS_2GB
- RDP_PS_32GB
- RDP_PS_4GB
- RDP_PS_64GB
- RDP_PS_8GB
- RDP_PS_NOT_ESTABLISHED
- RDP_PS_UNKNOWN
- RDP_SFP_DESC_TAG
- RDP_STEP
- RDQDA
- RDR
- RDR1
- RDR2
- RDRAND_INT
- RDRAND_LONG
- RDRAND_RETRY_LOOPS
- RDRB
- RDRE
- RDROM
- RDRP
- RDRP_ADDR
- RDRV_DEGRADED
- RDRV_DELETED
- RDRV_OFFLINE
- RDRV_OPTIMAL
- RDR_ACD_BASE_ADDR_HI
- RDR_ACD_BASE_ADDR_LO
- RDR_ACKLATTO
- RDR_AERCC
- RDR_AERCEMSK
- RDR_AERCESTA
- RDR_AERHL0
- RDR_AERHL1
- RDR_AERHL2
- RDR_AERHL3
- RDR_AERUEMSK
- RDR_AERUESEV
- RDR_AERUESTA
- RDR_AERXCAP
- RDR_BASE_ADDR_HI
- RDR_BASE_ADDR_LO
- RDR_CFG
- RDR_CFG0
- RDR_CFG1
- RDR_CFG2
- RDR_CFG3
- RDR_CFG4
- RDR_CFG5
- RDR_CFG6
- RDR_CFG7
- RDR_CFG8
- RDR_CFG9
- RDR_CFGA
- RDR_CFGB
- RDR_CFGC
- RDR_CFGD
- RDR_CFGE
- RDR_CFGF
- RDR_CLKOUT_MARK
- RDR_DATA_BASE_ADDR_HI
- RDR_DATA_BASE_ADDR_LO
- RDR_DESC_SIZE
- RDR_DLLCTRL
- RDR_DLLSTAT
- RDR_DMA_CFG
- RDR_EPOCH_SIZE
- RDR_L0S_EXIT_LAT
- RDR_LIST_SIZE
- RDR_LP_BUFFER_SIZE
- RDR_MACCTRL0
- RDR_MACCTRL1
- RDR_MACCTRL2
- RDR_MACSTAT0
- RDR_MACSTAT1
- RDR_MAC_LB_DATA
- RDR_MSIARL
- RDR_MSIARU
- RDR_MSICAP
- RDR_MSIDATA
- RDR_NANTENNAS
- RDR_NTIERS
- RDR_NTIER_SIZE
- RDR_PECAP
- RDR_PEDEVCAP
- RDR_PEDEVSC
- RDR_PELINKCAP
- RDR_PELINKSC
- RDR_PMCSR
- RDR_PMICAP
- RDR_PREP_COUNT
- RDR_PREP_PNTR
- RDR_PROC_COUNT
- RDR_PROC_PNTR
- RDR_RDRCTL0
- RDR_RDRCTL1
- RDR_RDRSTAT0
- RDR_RDRSTAT1
- RDR_REPLAYTO
- RDR_REQCTRL
- RDR_REQEPA
- RDR_REQRCAL
- RDR_REQRCAU
- RDR_REQSTAT
- RDR_RING_SIZE
- RDR_RX_VCR0_FC
- RDR_RX_VCR1_FC
- RDR_RX_VCR2_FC
- RDR_RX_VCR3_FC
- RDR_STAT
- RDR_SUSSYSTEM_ID_CFG
- RDR_THRESH
- RDR_TIER_SIZE
- RDR_TLCTL0
- RDR_TLCTL1
- RDR_TLSTAT0
- RDR_TLSTAT1
- RDR_TL_TEST
- RDR_VCARB0
- RDR_VCARB1
- RDR_VCARB2
- RDR_VCARB3
- RDR_VCARB4
- RDR_VCARB5
- RDR_VCARB6
- RDR_VCARB7
- RDR_VCCAP1
- RDR_VCCAP2
- RDR_VCR01_CTL
- RDR_VCR0_CAP
- RDR_VCR0_CTRL
- RDR_VCR0_STAT
- RDR_VCR1_CAP
- RDR_VCR1_CTRL
- RDR_VCR1_STAT
- RDR_VCR23_CTL
- RDR_VCR2_CAP
- RDR_VCR2_CTRL
- RDR_VCR2_STAT
- RDR_VCR3_CAP
- RDR_VCR3_CTRL
- RDR_VCR3_STAT
- RDR_VCSC
- RDR_VCXCAP
- RDR_VENDOR_DEVICE_ID_CFG
- RDR_VPDCAP
- RDR_VPDDATA
- RDS5
- RDS6
- RDS6_INFO_CONNECTIONS
- RDS6_INFO_IB_CONNECTIONS
- RDS6_INFO_RECV_MESSAGES
- RDS6_INFO_RETRANS_MESSAGES
- RDS6_INFO_SEND_MESSAGES
- RDS6_INFO_SOCKETS
- RDS6_INFO_TCP_SOCKETS
- RDSA
- RDSAR1
- RDSA_RDSA
- RDSB
- RDSB_RDSB
- RDSC
- RDSC_RDSC
- RDSD
- RDSD_RDSD
- RDSEED_INT
- RDSEED_LONG
- RDSEND
- RDSOFFSET
- RDSPL5
- RDSPL6
- RDSRE
- RDST
- RDSTA_IF0
- RDSTA_IF1
- RDSTA_IFMASK
- RDSTA_SKVN
- RDSTA_SKVT
- RDSTK
- RDS_ALTFREQ
- RDS_ATOMIC_TYPE_CSWP
- RDS_ATOMIC_TYPE_FADD
- RDS_BLK_B_SET
- RDS_BLOCK
- RDS_BLOCK_CLEAR
- RDS_BLOCK_LOAD
- RDS_BLOCK_SIZE
- RDS_BOUND_KEY_LEN
- RDS_BUFFER
- RDS_BUSYMASK
- RDS_CANCEL_SENT_TO
- RDS_CARRIAGE_RETURN
- RDS_CLK_MARK
- RDS_CLOCKMASK
- RDS_CMSG_ATOMIC_CSWP
- RDS_CMSG_ATOMIC_FADD
- RDS_CMSG_CONG_UPDATE
- RDS_CMSG_MASKED_ATOMIC_CSWP
- RDS_CMSG_MASKED_ATOMIC_FADD
- RDS_CMSG_RDMA_ARGS
- RDS_CMSG_RDMA_DEST
- RDS_CMSG_RDMA_MAP
- RDS_CMSG_RDMA_STATUS
- RDS_CMSG_RXPATH_LATENCY
- RDS_CMSG_ZCOPY_COMPLETION
- RDS_CMSG_ZCOPY_COOKIE
- RDS_CM_PORT
- RDS_CNTRL_SET
- RDS_CONFIG_DATA_SET
- RDS_CONG_MAP_BYTES
- RDS_CONG_MAP_PAGES
- RDS_CONG_MAP_PAGE_BITS
- RDS_CONG_MONITOR
- RDS_CONG_MONITOR_BIT
- RDS_CONG_MONITOR_MASK
- RDS_CONG_MONITOR_SIZE
- RDS_CONNECTION_HASH_BITS
- RDS_CONNECTION_HASH_ENTRIES
- RDS_CONNECTION_HASH_MASK
- RDS_CONN_CONNECTING
- RDS_CONN_DISCONNECTING
- RDS_CONN_DOWN
- RDS_CONN_ERROR
- RDS_CONN_RESETTING
- RDS_CONN_UP
- RDS_DATA
- RDS_DATAMASK
- RDS_DATASHIFT
- RDS_DATA_ENB
- RDS_DATA_GET
- RDS_DATA_MARK
- RDS_DATA_SET
- RDS_DESTROY_PENDING
- RDS_DEV_SET
- RDS_EXTHDR_GEN_NUM
- RDS_EXTHDR_NONE
- RDS_EXTHDR_NPATHS
- RDS_EXTHDR_RDMA
- RDS_EXTHDR_RDMA_DEST
- RDS_EXTHDR_VERSION
- RDS_FLAG_ACK_REQUIRED
- RDS_FLAG_CONG_BITMAP
- RDS_FLAG_PROBE_PORT
- RDS_FLAG_RETRANSMITTED
- RDS_FRAG_SHIFT
- RDS_FRAG_SIZE
- RDS_FREE_MR
- RDS_GET_MR
- RDS_GET_MR_FOR_DEST
- RDS_HEADER_EXT_SPACE
- RDS_HS_PROBE
- RDS_IB_ABI_VERSION
- RDS_IB_ACK_WR_ID
- RDS_IB_DEFAULT_FR_WR
- RDS_IB_DEFAULT_RECV_WR
- RDS_IB_DEFAULT_RETRY_COUNT
- RDS_IB_DEFAULT_SEND_WR
- RDS_IB_GID_LEN
- RDS_IB_MAX_SGE
- RDS_IB_MR_1M_POOL
- RDS_IB_MR_8K_POOL
- RDS_IB_RECV_SGE
- RDS_IB_RECYCLE_BATCH_COUNT
- RDS_IB_SUPPORTED_PROTOCOLS
- RDS_IB_WC_MAX
- RDS_INFO_CONNECTIONS
- RDS_INFO_CONNECTION_FLAG_CONNECTED
- RDS_INFO_CONNECTION_FLAG_CONNECTING
- RDS_INFO_CONNECTION_FLAG_SENDING
- RDS_INFO_CONNECTION_STATS
- RDS_INFO_COUNTERS
- RDS_INFO_FIRST
- RDS_INFO_IB_CONNECTIONS
- RDS_INFO_IWARP_CONNECTIONS
- RDS_INFO_LAST
- RDS_INFO_MESSAGE_FLAG_ACK
- RDS_INFO_MESSAGE_FLAG_FAST_ACK
- RDS_INFO_RECV_MESSAGES
- RDS_INFO_RETRANS_MESSAGES
- RDS_INFO_SEND_MESSAGES
- RDS_INFO_SOCKETS
- RDS_INFO_TCP_SOCKETS
- RDS_IN_XMIT
- RDS_LL_SEND_FULL
- RDS_MAX_ADV_CREDIT
- RDS_MAX_MSG_SIZE
- RDS_MAX_ZCOOKIES
- RDS_MEM_SET
- RDS_MPATH_HASH
- RDS_MPATH_WORKERS
- RDS_MR_1M_MSG_SIZE
- RDS_MR_1M_POOL_SIZE
- RDS_MR_8K_MSG_SIZE
- RDS_MR_8K_POOL_SIZE
- RDS_MR_8K_SCALE
- RDS_MR_DEAD
- RDS_MSG_ACK_REQUIRED
- RDS_MSG_FLUSH
- RDS_MSG_HAS_ACK_SEQ
- RDS_MSG_MAPPED
- RDS_MSG_ON_CONN
- RDS_MSG_ON_SOCK
- RDS_MSG_PAGEVEC
- RDS_MSG_RETRANSMITTED
- RDS_MSG_RX_CMSG
- RDS_MSG_RX_DGRAM_DELIVERED
- RDS_MSG_RX_DGRAM_REASSEMBLE
- RDS_MSG_RX_DGRAM_TRACE_MAX
- RDS_MSG_RX_END
- RDS_MSG_RX_HDR
- RDS_MSG_RX_HDR_TO_DGRAM_START
- RDS_MSG_RX_START
- RDS_MSK_B_SET
- RDS_OUT
- RDS_PAUSE_DUR_SET
- RDS_PAUSE_LVL_SET
- RDS_PI_CODE
- RDS_PI_MASK_SET
- RDS_PI_SET
- RDS_PORT
- RDS_PROTOCOL
- RDS_PROTOCOL_3_0
- RDS_PROTOCOL_3_1
- RDS_PROTOCOL_4_0
- RDS_PROTOCOL_4_1
- RDS_PROTOCOL_COMPAT_VERSION
- RDS_PROTOCOL_MAJOR
- RDS_PROTOCOL_MINOR
- RDS_PROTOCOL_VERSION
- RDS_PTYTATP
- RDS_RADIOTEXT_2A
- RDS_RADIOTEXT_BLK_SIZE
- RDS_RADIOTEXT_INDEX_MAX
- RDS_RDMA_CANCELED
- RDS_RDMA_DONTWAIT
- RDS_RDMA_DROPPED
- RDS_RDMA_FENCE
- RDS_RDMA_INVALIDATE
- RDS_RDMA_NOTIFY_ME
- RDS_RDMA_OTHER_ERROR
- RDS_RDMA_READWRITE
- RDS_RDMA_REJ_INCOMPAT
- RDS_RDMA_REMOTE_ERROR
- RDS_RDMA_RESOLVE_TIMEOUT_MS
- RDS_RDMA_SILENT
- RDS_RDMA_SUCCESS
- RDS_RDMA_USE_ONCE
- RDS_RECONNECT_PENDING
- RDS_RECVERR
- RDS_RECV_REFILL
- RDS_REGISTER_NUM
- RDS_REPORT
- RDS_REPORT_SIZE
- RDS_REP_SET
- RDS_RESET
- RDS_RXVALUE
- RDS_RX_FLAG
- RDS_RX_MAX_TRACES
- RDS_STATIONNAME
- RDS_STATUS
- RDS_SYNC_GET
- RDS_SYSTEM_SET
- RDS_TCP_PORT
- RDS_TCP_RCVBUF
- RDS_TCP_SNDBUF
- RDS_TEXT
- RDS_TIMEDATE
- RDS_TRANS_COUNT
- RDS_TRANS_IB
- RDS_TRANS_IWARP
- RDS_TRANS_LOOP
- RDS_TRANS_NONE
- RDS_TRANS_TCP
- RDTCTRL_GROUP
- RDTGROUP_SUPER_MAGIC
- RDTICK
- RDTMON_GROUP
- RDTREQ
- RDT_DELETED
- RDT_FLAG_CMT
- RDT_FLAG_L2_CAT
- RDT_FLAG_L2_CDP
- RDT_FLAG_L3_CAT
- RDT_FLAG_L3_CDP
- RDT_FLAG_MBA
- RDT_FLAG_MBM_LOCAL
- RDT_FLAG_MBM_TOTAL
- RDT_MODE_EXCLUSIVE
- RDT_MODE_PSEUDO_LOCKED
- RDT_MODE_PSEUDO_LOCKSETUP
- RDT_MODE_SHAREABLE
- RDT_NUM_GROUP
- RDT_NUM_MODES
- RDT_NUM_RESOURCES
- RDT_OPT
- RDT_RESOURCE_L2
- RDT_RESOURCE_L2CODE
- RDT_RESOURCE_L2DATA
- RDT_RESOURCE_L3
- RDT_RESOURCE_L3CODE
- RDT_RESOURCE_L3DATA
- RDT_RESOURCE_MBA
- RDWRLOCK_DMAP
- RDWRLOCK_IMAP
- RDWRLOCK_NORMAL
- RDWRLVLFULL_START
- RDWR_224
- RDWR_227
- RDWR_EN_HI_CNT
- RDWR_EN_HI_CNT__VALUE
- RDWR_EN_LO_CNT
- RDWR_EN_LO_CNT__VALUE
- RDWR_FWE_MARK
- RDWR_MARK
- RDWR_STATUS_DONE
- RDWR_STATUS_FAILURE
- RDWR_STATUS_SUCCESS
- RDW_ALL_NWRITE
- RDW_ALL_NWRITE_R
- RDW_DEFAULT
- RDW_HARPOON
- RDW_LAST_NWRITE_R
- RDX
- RDYTODS_RETURNTOEXE
- RDY_16BYTE
- RDY_2_DS
- RDY_2_XP70_RST
- RDY_32BYTE
- RDY_64BYTE
- RDY_ACT
- RDY_CHG
- RDY_EN
- RDY_GPIO_62
- RDY_GPIO_PIN
- RDY_MACON
- RDY_MAGIC
- RDY_MAGIC_SIZE
- RDY_MARK
- RD_2ndL_HITE
- RD_2ndL_HITM
- RD_2ndL_HITS
- RD_2ndL_MISS
- RD_3rdL_HITE
- RD_3rdL_HITM
- RD_3rdL_HITS
- RD_3rdL_MISS
- RD_ACCESS
- RD_ACCESS_ERR_MASK
- RD_ADDR_MASK
- RD_ADDR_SHIFT
- RD_ATTMSG
- RD_BITS
- RD_BLOCKSIZE
- RD_BUF
- RD_BUFFER_CONTENTS
- RD_BUFF_BACK
- RD_BUFF_FRONT
- RD_CACHE_3BITS
- RD_CACHE_4BITS
- RD_CE
- RD_CH_ADDR
- RD_CH_CTRL
- RD_CH_EN
- RD_CH_SIZE
- RD_CH_SPACE
- RD_CH_STRIDE
- RD_CMD
- RD_CMDSTREAM
- RD_CMDSTREAM_ADDR
- RD_CONTEXT
- RD_CS
- RD_CTRL
- RD_DB
- RD_DCS
- RD_DEV
- RD_DEVICE_QUEUE_DEPTH
- RD_DMA_ATTR_DEFAULT
- RD_DT
- RD_ES
- RD_FB_CMD_REG
- RD_FF
- RD_FIFO
- RD_FIFO_CFG
- RD_FIFO_RESET
- RD_FIFO_STATUS
- RD_FL
- RD_FLUSH
- RD_FRAG_SHADER
- RD_FRM_IMPA
- RD_FRM_IMPS
- RD_FRM_LLCA
- RD_FRM_LLCS
- RD_FRM_MAC
- RD_FRM_SMT
- RD_FS
- RD_FSC_MARK
- RD_FS_LOCAL
- RD_FT
- RD_GATT
- RD_GPIO_PIN
- RD_GPUADDR
- RD_GPU_ID
- RD_HARP32
- RD_HARPOON
- RD_HBA_VERSION
- RD_INT_FIFO_SIZE
- RD_IPV4_CS
- RD_IPV6_CS
- RD_LE
- RD_LENGTH
- RD_LEN_BIT
- RD_LS
- RD_MAILBOX_REG
- RD_MARK
- RD_MASK
- RD_MAX_ALLOCATION_SIZE
- RD_MAX_DEVICE_QUEUE_DEPTH
- RD_MCP_VERSION
- RD_MF
- RD_N
- RD_NCONV_ACCU_REQ
- RD_NONE
- RD_N_MARK
- RD_OF
- RD_OFS
- RD_PARAM
- RD_PROGRAM
- RD_PROT
- RD_RACT
- RD_RBL
- RD_RBS1
- RD_RBS2
- RD_RCH
- RD_RDLE
- RD_RE
- RD_REG
- RD_REGISTER
- RD_REGISTER_LEGACY
- RD_REGISTER_UNROLL
- RD_REGP
- RD_REG_BYTE
- RD_REG_BYTE_RELAXED
- RD_REG_DWORD
- RD_REG_DWORD_RELAXED
- RD_REG_WORD
- RD_REG_WORD_PIO
- RD_REG_WORD_RELAXED
- RD_REG_WORD_dmasync
- RD_RER
- RD_RF
- RD_RFE
- RD_RFL
- RD_RFP
- RD_RFP0
- RD_RFP1
- RD_RFS1
- RD_RFS10
- RD_RFS2
- RD_RFS3
- RD_RFS4
- RD_RFS5
- RD_RFS6
- RD_RFS7
- RD_RFS8
- RD_RFS9
- RD_RING_SIZE
- RD_RJ
- RD_SH
- RD_SIZE
- RD_STALLED
- RD_STATE
- RD_STATUS
- RD_STATUS_REG
- RD_STS_ACT_POL_RAM
- RD_STS_BIT
- RD_STS_RATE_METER_RAM
- RD_STS_SHIFT
- RD_STS_STAT_RAM
- RD_STS_TCAM
- RD_S_ERFBB
- RD_S_MSRABT
- RD_S_MSVALID
- RD_S_RES1
- RD_S_RES2
- RD_S_SADRRG
- RD_S_SEAC
- RD_S_SEAC0
- RD_S_SEAC1
- RD_S_SEAC2
- RD_S_SFRMERR
- RD_S_SFRMTY
- RD_S_SSRCRTG
- RD_TAP
- RD_TAP_MASK
- RD_TCP_CS
- RD_TEST
- RD_TL
- RD_UDP_CS
- RD_VALUE_MASK
- RD_VCHAN_ID
- RD_VERT_SHADER
- RD_WR_B_MARK
- RD_WR_MARK
- RD_WR_N_MARK
- RD_Y
- RD__FSC_MARK
- RDxR_DOW_MASK
- RDxR_DOW_S
- RDxR_HOUR_MASK
- RDxR_HOUR_S
- RDxR_MIN_MASK
- RDxR_MIN_S
- RDxR_SEC_MASK
- RDxR_WOM_MASK
- RDxR_WOM_S
- RE
- RE1
- RE2
- READ
- READ16_EEPROM
- READ1_1
- READ1_1_2
- READ1_1_3
- READ1_2
- READ2
- READABLE_MAP
- READAHEAD_SZ
- READA_BACK
- READA_FORWARD
- READA_NONE
- READB
- READBACK_ADD_HALF
- READBACK_NEGATE
- READBACK_VALUE_MASK
- READBACK_VALUE_SHIFT
- READCFG32
- READCHAN
- READCHAN_BLERB
- READCHAN_BLERC
- READCHAN_BLERD
- READCHAN_READCHAN
- READDBA_LIMIT
- READEF1BYTE
- READEF2BYTE
- READEF4BYTE
- READER_PUNCH_DEVTYPE
- READING_NULL
- READING_PUNC
- READING_PUNC_DEC
- READING_PUNC_INC
- READING_SHADOW_PAGE_TABLES
- READING_U16
- READING_U32
- READING_U8
- READL
- READLEN
- READMEM
- READMODE_LINE
- READMODE_MULTIPLE
- READMODE_PLAIN
- READONLY_SEGMENT_START
- READRDP
- READREG
- READRSPERR_F
- READRSPERR_S
- READRSPERR_V
- READSAFE_TIMEOUT
- READUCTLDATA
- READWRITE_SEGMENT_START
- READX_REQ
- READY
- READY_FLAG
- READY_FOR_TX
- READY_FOR_TX_ENBL
- READY_FOR_TX_NOW
- READY_LEVEL
- READY_MASK
- READY_STATE
- READY_boot
- READY_kernel
- READ_10
- READ_12
- READ_12BIT_DFR
- READ_12BIT_SER
- READ_16
- READ_256_BITS
- READ_32
- READ_512_BITS
- READ_6
- READ_ACCESSES
- READ_ADDR
- READ_AGC_FORMATTER
- READ_AHEAD
- READ_AHEAD_COMPLETED_WITH_ERROR
- READ_ALLSLOT
- READ_ALLSTAT
- READ_ALL_DOC
- READ_AND_CONFIG
- READ_AND_CONFIG_MP
- READ_AND_CONFIG_TC
- READ_ARRAY
- READ_ATTR
- READ_ATTRIBUTE
- READ_AUDIO_CONTROL
- READ_AUDIO_STATUS
- READ_BACKWARD
- READ_BALANCE_RR
- READ_BANDWIDTH
- READ_BB_REG
- READ_BCR
- READ_BIT
- READ_BLOCK_ID
- READ_BLOCK_LEN
- READ_BLOCK_LIMITS
- READ_BLOCK_SIZE
- READ_BLUE_GAIN_FORMATTER
- READ_BQ_REGISTER
- READ_BUF
- READ_BUFFER
- READ_BUFFERS
- READ_BUFFER_DROP
- READ_BUFFER_SIZE
- READ_BUFF_LOG
- READ_BUF_SIZE
- READ_BUSSTATUS
- READ_BUS_MODE
- READ_BUS_STATUS
- READ_BYTE
- READ_BYTES
- READ_BYTES_WAIT_INT
- READ_BYTE_COUNT
- READ_CALIB_BUF
- READ_CAPACITY
- READ_CAPACITY_RETRIES_ON_RESET
- READ_CAP_LEN
- READ_CFG
- READ_CMD
- READ_CMD_MEM
- READ_CMD_MR
- READ_CMD_MRL
- READ_CMD_MRM
- READ_COMPLETED
- READ_COMPLETED_WITH_ERR
- READ_COMPLETED_WITH_ERROR
- READ_COND
- READ_CONFIG_8LD
- READ_CONFIG_DATA
- READ_CONFIG_VAR
- READ_CONTROL
- READ_COUNT
- READ_COUNTER
- READ_CSR_E_STAT
- READ_CSR_ME2FUNCTION_MAP_A
- READ_CSR_ME2FUNCTION_MAP_B
- READ_CSR_RING_HEAD
- READ_CSR_RING_TAIL
- READ_CTLRSTATUS
- READ_CURRENT_TEMPERATURE
- READ_CYCLE_MASK
- READ_DATA
- READ_DATA_0
- READ_DATA_1
- READ_DATA_DATA_MASK
- READ_DATA_DATA_SHIFT
- READ_DATA_FIELD_ID_MASK
- READ_DATA_FIELD_ID_SHIFT
- READ_DATA_LANE_ID_MASK
- READ_DATA_LANE_ID_SHIFT
- READ_DATA_SIZE_REG
- READ_DATA_STAGE
- READ_DATA_VALID
- READ_DAT_UTIL_STOP
- READ_DCIN_VOLTAGE
- READ_DEFECT_DATA
- READ_DEFECT_DATA_TIMEOUT
- READ_DEMOD
- READ_DEV_CHAR
- READ_DQS_BYPASS_MODE
- READ_DQS_DELAY
- READ_DQS_DELAY_MASK
- READ_DSP_TIMEOUT
- READ_DUMP
- READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
- READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION
- READ_EEPROM
- READ_EEPROM2
- READ_EEPROM_REQ
- READ_EEPROM_STATUS
- READ_EFUSE
- READ_EFUSE_VALUE_PARAMETER
- READ_ELEMENT_STATUS
- READ_ELEMENT_STATUS_TIMEOUT
- READ_EMU_RAM
- READ_EMU_REGISTER
- READ_EN
- READ_ERR
- READ_ERROR_STATUS
- READ_ETHERNET_ADDRESS
- READ_EV
- READ_EVENT_LOG_VAR
- READ_EVENT_STATUS
- READ_EVENT_STATUS_NO_RESET
- READ_EXTERNAL_BATTERY_CHARGE_LEVEL
- READ_EXTERNAL_KEYBOARD_LAYOUT
- READ_EXTERNAL_STATUS
- READ_EXTERNAL_VGA_PORT
- READ_EXTSLOTSTATUS
- READ_FINISHED_WITH_ACK
- READ_FLASH_BYTE_COMMAND
- READ_FL_BUF
- READ_FMANT_TUNE_VALUE
- READ_FORMAT_CAPACITIES
- READ_FORWARD
- READ_FROM_PCI
- READ_FX2_REG_REQ
- READ_GET
- READ_HARDWARE_VERSION
- READ_HARD_CFG
- READ_HEADER
- READ_HORIZONTAL_POINTER_VOLTAGE
- READ_HOST_REG
- READ_HPCOPTIONS
- READ_I2C
- READ_ID
- READ_IDLE_INTERVAL_DVFS
- READ_IDLE_INTERVAL_NORMAL
- READ_IDLE_MSG_TYPE_MASK
- READ_IDLE_MSG_TYPE_SHIFT
- READ_ID_CODES
- READ_IMPLIES_EXEC
- READ_INDEX
- READ_INDEX_REG
- READ_INLINE
- READ_INPUT_INFO
- READ_INTERNAL_BATTERY_CHARGE_LEVEL
- READ_INTERNAL_BATTERY_VOLTAGE
- READ_INTERNAL_KEYBOARD_LAYOUT
- READ_IO_IO_HIGH
- READ_IO_IO_LOW
- READ_LATENCY
- READ_LATENCY_MASK_4D
- READ_LATENCY_MASK_4D5
- READ_LATENCY_SHDW_MASK
- READ_LATENCY_SHDW_SHIFT
- READ_LATENCY_SHIFT_4D
- READ_LATENCY_SHIFT_4D5
- READ_LINE
- READ_LNK_VAR
- READ_LOCATION_LAST
- READ_LOCATION_OFFSET
- READ_LOCATION_SIZE
- READ_LOCK
- READ_LOCK_VOID
- READ_LOC_AMP_ASSOC
- READ_LOC_AMP_ASSOC_FINAL
- READ_LOC_AMP_INFO
- READ_LONG
- READ_MAC_ADDR
- READ_MASK
- READ_MAX_TEMPERATURE
- READ_MEDIA_SERIAL_NUMBER
- READ_MEM
- READ_MEMORY
- READ_MESSAGE_ID
- READ_MICROCONTROLLER_ROM_CHECKSUM
- READ_MICROCONTROLLER_VERSION
- READ_MICROCONTROLLER_VOLTAGE
- READ_MIN_TEMPERATURE
- READ_MMIO_UPPER32
- READ_MODE
- READ_MODE__VALUE
- READ_MOSTLY_DATA
- READ_MULTIPLE
- READ_MULTIPLE_BLOCK
- READ_MUX
- READ_NEXT_PAIR
- READ_NEXT_RF_PAIR
- READ_NVM_CHUNK_NOT_VALID_ADDRESS
- READ_NVM_CHUNK_SUCCEED
- READ_NV_VAR
- READ_ONCE
- READ_ONCE_NOCHECK
- READ_ONCE_TASK_STACK
- READ_OP
- READ_PAGE_DATA
- READ_PARTIAL_BLOCK
- READ_PATH_FMT
- READ_PEND
- READ_PERMANENT_PARAMETERS
- READ_PER_CPU_CNTR
- READ_PHY
- READ_PID_NUMBER_REQ
- READ_PORT
- READ_PORT_ULONG
- READ_POSITION
- READ_POSITION_LEN
- READ_POS_BUF
- READ_POWERON_CYCLES
- READ_POWERON_SECONDS
- READ_PRAM
- READ_PREVIOUS
- READ_PROM
- READ_PROTECTION_FAULT_ENABLE_DEFAULT
- READ_PROTECTION_FAULT_ENABLE_INTERRUPT
- READ_PUBEK_RESULT_MIN_BODY_SIZE
- READ_RADIO_REG2
- READ_RADIO_REG3
- READ_RADIO_REG4
- READ_RAM
- READ_RAW_ENABLE
- READ_RAW_Y_MEAN_FORMATTER
- READ_RCONF_VAR
- READ_REAL_TIME_CLOCK
- READ_REAL_TIME_CLOCK_ALARM
- READ_RED_GAIN_FORMATTER
- READ_REG
- READ_REG16
- READ_REG32
- READ_REG64
- READ_REG8
- READ_REGISTER
- READ_REG_CMD
- READ_REG_MASK
- READ_REG_NUM
- READ_REMOTE_REQ
- READ_REQ
- READ_REQUEST_PRIORITY_HIGH
- READ_REQUEST_PRIORITY_LOW
- READ_REQUEST_PRIORITY_MASK
- READ_REQUEST_PRIORITY_SHIFT
- READ_REQ_SIZE
- READ_RESET_STATUS
- READ_RESP
- READ_RETRY_REMOTE_CANCELED
- READ_REVERSE
- READ_REVLEVEL
- READ_REV_VAR
- READ_RF
- READ_RF_REG
- READ_ROM
- READ_RPI_VAR
- READ_RSP
- READ_RSP_SIZE
- READ_RX_TAGS_LEN
- READ_SBUS_RECEIVER
- READ_SECTORS
- READ_SEQ
- READ_SERIAL_NUMBER
- READ_SFR
- READ_SHADOW_REG
- READ_SHUTTER_FORMATTER
- READ_SINGLE_BLOCK
- READ_SIZE
- READ_SLOTLATCHLOWREG
- READ_SLOTSTATUS
- READ_SLOT_LATCH
- READ_SOURCE
- READ_SPARM_VAR
- READ_SS_DATA
- READ_START_VLD
- READ_STATE
- READ_STATUS
- READ_STATUS_REG
- READ_STATUS_SIZE
- READ_STATUS_STAGE
- READ_STATUS_VAR
- READ_STOP_VLD
- READ_STR
- READ_STS
- READ_SUBSYS_DATA
- READ_SYSTEM_VARIANT
- READ_TC_INT
- READ_TDO
- READ_TIMEOUT
- READ_TIME_CMD
- READ_TOC
- READ_TSSI
- READ_TUNER_REG_REQ
- READ_TYPE
- READ_U16
- READ_U32
- READ_U8
- READ_UNLOADS_DW
- READ_UNLOCK
- READ_USER_CONFIGURATION_AREA
- READ_VERTICAL_POINTER_VOLTAGE
- READ_WAIT_USEC
- READ_WB_REG_CASE
- READ_WEIGHT
- READ_WEIGHT_MASK
- READ_WEIGHT_SHIFT
- READ_WORD
- READ_WRITE_BUFFER_SIZE
- READ_WRITE_I2C
- READ_WRITE_LDIO
- READ_WRITE_LOCK_LEVEL
- READ_WRITE_SYSPDIO
- READ_X
- READ_XRI_VAR
- READ_X_POS_LOWER
- READ_X_POS_UPPER
- READ_Y
- READ_Y_POS_LOWER
- READ_Y_POS_UPPER
- READ_Z1
- READ_Z2
- READ_xD_ID
- REALLOC_STATE_FN
- REALLY_SLOW_IO
- REALMODE_END_SIGNATURE
- REALM_SZ
- REALTEK_FDX
- REALTEK_POWER_SEQUENCE_8723B
- REALTEK_SMI_ACK_RETRY_COUNT
- REALTEK_SMI_HW_START_DELAY
- REALTEK_SMI_HW_STOP_DELAY
- REALTEK_USB_CMD_IDX
- REALTEK_USB_CMD_REQ
- REALTEK_USB_DEVICE
- REALTEK_USB_READ
- REALTEK_USB_VENQT_CMD_IDX
- REALTEK_USB_VENQT_CMD_REQ
- REALTEK_USB_VENQT_MAX_BUF_SIZE
- REALTEK_USB_VENQT_READ
- REALTEK_USB_VENQT_WRITE
- REALTEK_USB_WRITE
- REALTEK_VENDOR_ID
- REALTIME_COUNTER_BASE
- REALVIEW_CLCD_EB
- REALVIEW_CLCD_PB1176
- REALVIEW_CLCD_PB11MP
- REALVIEW_CLCD_PBA8
- REALVIEW_CLCD_PBX
- REALVIEW_EB_REVB_SYS_PLD_CTRL1
- REALVIEW_FLASHPROT
- REALVIEW_REBOOT_EB
- REALVIEW_REBOOT_PB1176
- REALVIEW_REBOOT_PB11MP
- REALVIEW_REBOOT_PBA8
- REALVIEW_REBOOT_PBX
- REALVIEW_SYS_FLAGSSET_OFFSET
- REALVIEW_SYS_ID_OFFSET
- REALVIEW_SYS_LOCK_OFFSET
- REALVIEW_SYS_PLD_CTRL1
- REAL_HPAGE_PER_HPAGE
- REAL_HPAGE_SHIFT
- REAL_HPAGE_SIZE
- REAL_INITRD_SIZE
- REAL_MAX_AMBS_PER_CHANNEL
- REAL_MODE
- REAL_MODE_PSW
- REAL_MODE_TIMEOUT
- REAL_RX_BUF_SIZE
- REAPTIMEOUT_AC
- REAPTIMEOUT_NODE
- REAR_CODECOUT_SCB_ADDR
- REAR_LINE_IN
- REAR_MIC
- REAR_MIXER_SCB_ADDR
- REASON
- REASON_CODE_MASK
- REASON_CODE_SHIFT
- REASON_FP
- REASON_ILLEGAL
- REASON_PRIVILEGED
- REASON_TM
- REASON_TRAP
- REASSIGN_BLOCKS
- REASSOC_LIMIT
- REASSOC_REQ_TYPE
- REASSOC_RESP_TYPE
- REASSOC_TO
- REASS_ABR
- REASS_BASE
- REASS_COMMAND_REG
- REASS_DESC_BASE
- REASS_INTR_STATUS_REG
- REASS_MASK_REG
- REASS_QUEUE_BASE
- REASS_RAM_SIZE
- REASS_TABLE
- REASS_TABLE_BASE
- REASS_TABLE_SZ
- REAUTH_LIMIT
- REAUTH_TO
- REBASE_ADDR_BASE_MASK
- REBASE_ADDR_BASE_SHIFT
- REBOOT
- REBOOT_COLD
- REBOOT_COMMAND
- REBOOT_FLAG
- REBOOT_GPIO
- REBOOT_H
- REBOOT_HARD
- REBOOT_SOFT
- REBOOT_UNDEFINED
- REBOOT_VECTOR
- REBOOT_WARM
- REBUILD_DDB_LIST
- REBUILD_DUE_TO_FTRACE_MCOUNT_RECORD
- REC
- REC656IF
- RECALC_SECTORS
- RECALC_WRITE_SUPER
- RECALIBRATE_ERRORS
- RECALIBRATE_POINTING_STICK
- RECALIBRATING
- RECCR
- RECEIVED_ACKNOWLEDGE_TRIGGER
- RECEIVED_CRC_WAS_LOST
- RECEIVED_PAYLOAD_WAS_LOST
- RECEIVED_RESET_TRIGGER
- RECEIVED_TEAR_EFFECT_TRIGGER
- RECEIVED_UNASSIGNED_TRIGGER
- RECEIVER_ACTION
- RECEIVE_ALL
- RECEIVE_BUFFER_ALIGN_SIZE
- RECEIVE_BUFFER_REGISTER
- RECEIVE_BUF_MAX
- RECEIVE_COPY_RESULTS
- RECEIVE_DATA
- RECEIVE_DATA_B3_IND
- RECEIVE_DEBUGMSG
- RECEIVE_DIAGNOSTIC
- RECEIVE_FREE_NCCI
- RECEIVE_INIT
- RECEIVE_MESSAGE
- RECEIVE_MSG_AVAIL
- RECEIVE_N
- RECEIVE_NEW_NCCI
- RECEIVE_OBJECT_BITS
- RECEIVE_POLL
- RECEIVE_POLLDWORD
- RECEIVE_RELEASE
- RECEIVE_ROOM
- RECEIVE_START
- RECEIVE_STATUS
- RECEIVE_STOP
- RECEIVE_TASK_READY
- RECEIVING
- RECENTCY_DIRTY
- RECENTCY_MIN
- RECENT_IO
- RECENT_IO_BITS
- RECEPTION_STATISTICS_PER_SLICES_S
- RECFBDA
- RECFBDB
- RECFBDC
- RECFBDD
- RECFBDE
- RECFB_DIMMA
- RECFB_DIMMB
- RECFB_DIMMC
- RECFB_DIMMD
- RECFB_DIMME
- RECFB_DIMMF
- RECFGLOG
- RECLAIM_DISTANCE
- RECLAIM_MAX_FREE_SPACE
- RECLAIM_MAX_FREE_SPACE_SHIFT
- RECLAIM_OFF
- RECLAIM_UNMAP
- RECLAIM_WB_ANON
- RECLAIM_WB_ASYNC
- RECLAIM_WB_FILE
- RECLAIM_WB_LRU
- RECLAIM_WB_MIXED
- RECLAIM_WB_SYNC
- RECLAIM_WRITE
- RECLAIM_ZONE
- RECLEVEL_GAIN_TO_VOXWARE
- RECLEVEL_VOXWARE_TO_GAIN
- RECMEMA
- RECMEMA_BANK
- RECMEMA_RANK
- RECMEMB
- RECMEMB_CAS
- RECMEMB_IS_WR
- RECMEMB_RAS
- RECNTH
- RECNTL
- RECNTM
- RECOMBBUF
- RECOMTIMEOUTH_LEN
- RECOMTIMEOUTH_POS
- RECOMTIMEOUTL_LEN
- RECOMTIMEOUTL_POS
- RECONCILE_IRQ_STATE
- RECONFIG_DEVICE_ATTR
- RECONNECT
- RECONNECTS_USB
- RECONNECT_MAX_SIZE
- RECONNECT_ORB_LOGIN_ID
- RECONNECT_USB
- RECONN_TARGET
- RECON_THRESHOLD
- RECONflag
- RECORD_BLOCK_COUNTER
- RECORD_BUFS
- RECORD_CMDLINE
- RECORD_CONTROL
- RECORD_COUNT
- RECORD_COUNT_LEN
- RECORD_COUNT_TAG
- RECORD_END
- RECORD_EVENT_DISPLACE
- RECORD_EVENT_LIFTOFF
- RECORD_EVENT_NONE
- RECORD_EVENT_TOUCHDOWN
- RECORD_FILE_MAGIC
- RECORD_FUNCTION_CHECK
- RECORD_FUNCTION_IDENT
- RECORD_FUNCTION_TAG
- RECORD_FUNCTON_TAG_LEN
- RECORD_GCOV_VERSION
- RECORD_MCOUNT_64
- RECORD_MIXER_SCB_ADDR
- RECORD_MODE_HELP
- RECORD_MUTE
- RECORD_RS_FAILED
- RECORD_SIZE_HELP
- RECORD_START
- RECORD_SUFFIX
- RECORD_TGID
- RECORD_TIME_STAMP
- RECORD_VALID
- RECOVERED_ERROR
- RECOVERY
- RECOVERY_CLEANUP
- RECOVERY_CLK_CNT
- RECOVERY_IDLE_TO_RECOVER_FMW
- RECOVERY_INTR
- RECOVERY_MODE
- RECOVERY_MODE_NEXT_HSYNC
- RECOVERY_MODE_NEXT_STOP_POINT
- RECOVERY_MODE_NEXT_VSYNC
- RECOVERY_NDELAY
- RECOVER_BUFFERED_DATA
- RECOVER_ERR
- RECOVER_SIZE_INC
- RECS_PER_LEAF
- RECTLIST
- RECT_EXPAND_ONE_COLOR_CLIP
- RECT_EXPAND_ONE_COLOR_CLIP_POINT0_X
- RECT_EXPAND_ONE_COLOR_CLIP_POINT0_Y
- RECT_EXPAND_ONE_COLOR_CLIP_POINT1_X
- RECT_EXPAND_ONE_COLOR_CLIP_POINT1_Y
- RECT_EXPAND_ONE_COLOR_COLOR
- RECT_EXPAND_ONE_COLOR_DATA
- RECT_EXPAND_ONE_COLOR_DATA_MAX_DWORDS
- RECT_EXPAND_ONE_COLOR_POINT
- RECT_EXPAND_ONE_COLOR_POINT_X
- RECT_EXPAND_ONE_COLOR_POINT_Y
- RECT_EXPAND_ONE_COLOR_SIZE
- RECT_EXPAND_ONE_COLOR_SIZE_HEIGHT
- RECT_EXPAND_ONE_COLOR_SIZE_WIDTH
- RECT_EXPAND_TWO_COLOR_CLIP
- RECT_EXPAND_TWO_COLOR_CLIP_POINT0_X
- RECT_EXPAND_TWO_COLOR_CLIP_POINT0_Y
- RECT_EXPAND_TWO_COLOR_CLIP_POINT1_X
- RECT_EXPAND_TWO_COLOR_CLIP_POINT1_Y
- RECT_EXPAND_TWO_COLOR_COLOR_0
- RECT_EXPAND_TWO_COLOR_COLOR_1
- RECT_EXPAND_TWO_COLOR_DATA
- RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS
- RECT_EXPAND_TWO_COLOR_POINT
- RECT_EXPAND_TWO_COLOR_POINT_X
- RECT_EXPAND_TWO_COLOR_POINT_Y
- RECT_EXPAND_TWO_COLOR_SIZE_IN
- RECT_EXPAND_TWO_COLOR_SIZE_IN_HEIGHT
- RECT_EXPAND_TWO_COLOR_SIZE_IN_WIDTH
- RECT_EXPAND_TWO_COLOR_SIZE_OUT
- RECT_EXPAND_TWO_COLOR_SIZE_OUT_HEIGHT
- RECT_EXPAND_TWO_COLOR_SIZE_OUT_WIDTH
- RECT_FORMAT
- RECT_FORMAT_DEPTH16
- RECT_FORMAT_DEPTH24
- RECT_FORMAT_DEPTH8
- RECT_HEIGHT
- RECT_SOLID_COLOR
- RECT_SOLID_RECTS
- RECT_SOLID_RECTS_HEIGHT
- RECT_SOLID_RECTS_MAX_RECTS
- RECT_SOLID_RECTS_WIDTH
- RECT_SOLID_RECTS_X
- RECT_SOLID_RECTS_Y
- RECT_WIDTH
- RECV
- RECVBUFF_ALIGN_SZ
- RECVFRAME_HDR_ALIGN
- RECVQ
- RECV_16K
- RECV_1K
- RECV_2K
- RECV_32K
- RECV_4K
- RECV_64K
- RECV_8K
- RECV_ACKED_BY_PEER
- RECV_ALIVE
- RECV_ALL
- RECV_BLK_CNT
- RECV_BLK_SZ
- RECV_BLK_TH
- RECV_BUFFER_SIZE
- RECV_BUFF_SIZE
- RECV_BUF_MAP
- RECV_BULK_IN_ADDR
- RECV_CMD
- RECV_CMD_SEQ
- RECV_CONTROL
- RECV_DATA
- RECV_DISCARD
- RECV_FILTER_MATCH_TYPE_EQ
- RECV_FILTER_MATCH_TYPE_NE
- RECV_IDLE
- RECV_INT_IN_ADDR
- RECV_MAX_DATA_LEN
- RECV_MSG
- RECV_NUM_BLOCKS
- RECV_PACKET_PROCESS
- RECV_PACKET_PROCESS_COMPLETE
- RECV_PACKET_PROCESS_CONTINUE
- RECV_QID
- RECV_READY
- RECV_SIZE
- RECV_WAIT_ACL_HEADER
- RECV_WAIT_DATA
- RECV_WAIT_EVENT_HEADER
- RECV_WAIT_NSH
- RECV_WAIT_PACKET_TYPE
- RECV_WAIT_SCO_HEADER
- RECV_WATCHDOG_DISABLE
- RECYCLE_THRESHOLD
- REC_ACTION_NEED_RESET
- REC_ACTION_NONE
- REC_ACTION_RECOVERED
- REC_BANK
- REC_CAS
- REC_ECC_LOCATOR_EVEN
- REC_ECC_LOCATOR_ODD
- REC_FAILED_NUM
- REC_FILT_CONTROL
- REC_INV_SQRT_BITS
- REC_INV_SQRT_CACHE
- REC_INV_SQRT_SHIFT
- REC_MASTER_ABORT
- REC_NUM_DEFAULT
- REC_OVERRUN
- REC_OVERRUN_IRQ
- REC_POWER
- REC_RANK
- REC_RAS
- REC_RDWR
- REC_RETRY_COUNT
- REC_SIZE
- REC_STACK_SIZE
- RED
- REDHAT_PCI_VENDOR_ID
- REDIRECT
- REDIRECTION_TABLE_ENTRY_HIGH_0__Destination_id_0_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_0__Destination_id_0__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_10__Destination_id_10_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_10__Destination_id_10__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_11__Destination_id_11_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_11__Destination_id_11__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_12__Destination_id_12_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_12__Destination_id_12__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_13__Destination_id_13_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_13__Destination_id_13__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_14__Destination_id_14_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_14__Destination_id_14__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_15__Destination_id_15_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_15__Destination_id_15__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_16__Destination_id_16_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_16__Destination_id_16__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_17__Destination_id_17_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_17__Destination_id_17__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_18__Destination_id_18_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_18__Destination_id_18__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_19__Destination_id_19_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_19__Destination_id_19__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_1__Destination_id_1_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_1__Destination_id_1__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_20__Destination_id_20_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_20__Destination_id_20__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_21__Destination_id_21_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_21__Destination_id_21__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_22__Destination_id_22_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_22__Destination_id_22__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_23__Destination_id_23_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_23__Destination_id_23__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_24__Destination_id_24_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_24__Destination_id_24__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_25__Destination_id_25_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_25__Destination_id_25__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_26__Destination_id_26_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_26__Destination_id_26__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_27__Destination_id_27_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_27__Destination_id_27__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_28__Destination_id_28_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_28__Destination_id_28__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_29__Destination_id_29_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_29__Destination_id_29__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_2__Destination_id_2_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_2__Destination_id_2__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_30__Destination_id_30_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_30__Destination_id_30__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_31__Destination_id_31_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_31__Destination_id_31__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_3__Destination_id_3_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_3__Destination_id_3__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_4__Destination_id_4_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_4__Destination_id_4__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_5__Destination_id_5_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_5__Destination_id_5__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_6__Destination_id_6_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_6__Destination_id_6__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_7__Destination_id_7_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_7__Destination_id_7__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_8__Destination_id_8_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_8__Destination_id_8__SHIFT
- REDIRECTION_TABLE_ENTRY_HIGH_9__Destination_id_9_MASK
- REDIRECTION_TABLE_ENTRY_HIGH_9__Destination_id_9__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_0__Delivery_Mode_0_MASK
- REDIRECTION_TABLE_ENTRY_LOW_0__Delivery_Mode_0__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_0__Delivery_status_0_MASK
- REDIRECTION_TABLE_ENTRY_LOW_0__Delivery_status_0__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_0__Destination_Mode_0_MASK
- REDIRECTION_TABLE_ENTRY_LOW_0__Destination_Mode_0__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_0__Interrupt_Pin_Polarity_0_MASK
- REDIRECTION_TABLE_ENTRY_LOW_0__Interrupt_Pin_Polarity_0__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_0__Mask_0_MASK
- REDIRECTION_TABLE_ENTRY_LOW_0__Mask_0__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_0__Remote_IRR_0_MASK
- REDIRECTION_TABLE_ENTRY_LOW_0__Remote_IRR_0__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_0__Trigger_Mode_0_MASK
- REDIRECTION_TABLE_ENTRY_LOW_0__Trigger_Mode_0__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_0__Vector_0_MASK
- REDIRECTION_TABLE_ENTRY_LOW_0__Vector_0__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_10__Delivery_Mode_10_MASK
- REDIRECTION_TABLE_ENTRY_LOW_10__Delivery_Mode_10__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_10__Delivery_status_10_MASK
- REDIRECTION_TABLE_ENTRY_LOW_10__Delivery_status_10__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_10__Destination_Mode_10_MASK
- REDIRECTION_TABLE_ENTRY_LOW_10__Destination_Mode_10__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_10__Interrupt_Pin_Polarity_10_MASK
- REDIRECTION_TABLE_ENTRY_LOW_10__Interrupt_Pin_Polarity_10__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_10__Mask_10_MASK
- REDIRECTION_TABLE_ENTRY_LOW_10__Mask_10__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_10__Remote_IRR_10_MASK
- REDIRECTION_TABLE_ENTRY_LOW_10__Remote_IRR_10__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_10__Trigger_Mode_10_MASK
- REDIRECTION_TABLE_ENTRY_LOW_10__Trigger_Mode_10__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_10__Vector_10_MASK
- REDIRECTION_TABLE_ENTRY_LOW_10__Vector_10__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_11__Delivery_Mode_11_MASK
- REDIRECTION_TABLE_ENTRY_LOW_11__Delivery_Mode_11__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_11__Delivery_status_11_MASK
- REDIRECTION_TABLE_ENTRY_LOW_11__Delivery_status_11__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_11__Destination_Mode_11_MASK
- REDIRECTION_TABLE_ENTRY_LOW_11__Destination_Mode_11__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_11__Interrupt_Pin_Polarity_11_MASK
- REDIRECTION_TABLE_ENTRY_LOW_11__Interrupt_Pin_Polarity_11__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_11__Mask_11_MASK
- REDIRECTION_TABLE_ENTRY_LOW_11__Mask_11__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_11__Remote_IRR_11_MASK
- REDIRECTION_TABLE_ENTRY_LOW_11__Remote_IRR_11__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_11__Trigger_Mode_11_MASK
- REDIRECTION_TABLE_ENTRY_LOW_11__Trigger_Mode_11__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_11__Vector_11_MASK
- REDIRECTION_TABLE_ENTRY_LOW_11__Vector_11__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_12__Delivery_Mode_12_MASK
- REDIRECTION_TABLE_ENTRY_LOW_12__Delivery_Mode_12__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_12__Delivery_status_12_MASK
- REDIRECTION_TABLE_ENTRY_LOW_12__Delivery_status_12__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_12__Destination_Mode_12_MASK
- REDIRECTION_TABLE_ENTRY_LOW_12__Destination_Mode_12__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_12__Interrupt_Pin_Polarity_12_MASK
- REDIRECTION_TABLE_ENTRY_LOW_12__Interrupt_Pin_Polarity_12__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_12__Mask_12_MASK
- REDIRECTION_TABLE_ENTRY_LOW_12__Mask_12__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_12__Remote_IRR_12_MASK
- REDIRECTION_TABLE_ENTRY_LOW_12__Remote_IRR_12__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_12__Trigger_Mode_12_MASK
- REDIRECTION_TABLE_ENTRY_LOW_12__Trigger_Mode_12__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_12__Vector_12_MASK
- REDIRECTION_TABLE_ENTRY_LOW_12__Vector_12__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_13__Delivery_Mode_13_MASK
- REDIRECTION_TABLE_ENTRY_LOW_13__Delivery_Mode_13__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_13__Delivery_status_13_MASK
- REDIRECTION_TABLE_ENTRY_LOW_13__Delivery_status_13__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_13__Destination_Mode_13_MASK
- REDIRECTION_TABLE_ENTRY_LOW_13__Destination_Mode_13__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_13__Interrupt_Pin_Polarity_13_MASK
- REDIRECTION_TABLE_ENTRY_LOW_13__Interrupt_Pin_Polarity_13__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_13__Mask_13_MASK
- REDIRECTION_TABLE_ENTRY_LOW_13__Mask_13__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_13__Remote_IRR_13_MASK
- REDIRECTION_TABLE_ENTRY_LOW_13__Remote_IRR_13__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_13__Trigger_Mode_13_MASK
- REDIRECTION_TABLE_ENTRY_LOW_13__Trigger_Mode_13__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_13__Vector_13_MASK
- REDIRECTION_TABLE_ENTRY_LOW_13__Vector_13__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_14__Delivery_Mode_14_MASK
- REDIRECTION_TABLE_ENTRY_LOW_14__Delivery_Mode_14__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_14__Delivery_status_14_MASK
- REDIRECTION_TABLE_ENTRY_LOW_14__Delivery_status_14__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_14__Destination_Mode_14_MASK
- REDIRECTION_TABLE_ENTRY_LOW_14__Destination_Mode_14__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_14__Interrupt_Pin_Polarity_14_MASK
- REDIRECTION_TABLE_ENTRY_LOW_14__Interrupt_Pin_Polarity_14__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_14__Mask_14_MASK
- REDIRECTION_TABLE_ENTRY_LOW_14__Mask_14__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_14__Remote_IRR_14_MASK
- REDIRECTION_TABLE_ENTRY_LOW_14__Remote_IRR_14__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_14__Trigger_Mode_14_MASK
- REDIRECTION_TABLE_ENTRY_LOW_14__Trigger_Mode_14__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_14__Vector_14_MASK
- REDIRECTION_TABLE_ENTRY_LOW_14__Vector_14__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_15__Delivery_Mode_15_MASK
- REDIRECTION_TABLE_ENTRY_LOW_15__Delivery_Mode_15__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_15__Delivery_status_15_MASK
- REDIRECTION_TABLE_ENTRY_LOW_15__Delivery_status_15__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_15__Destination_Mode_15_MASK
- REDIRECTION_TABLE_ENTRY_LOW_15__Destination_Mode_15__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_15__Interrupt_Pin_Polarity_15_MASK
- REDIRECTION_TABLE_ENTRY_LOW_15__Interrupt_Pin_Polarity_15__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_15__Mask_15_MASK
- REDIRECTION_TABLE_ENTRY_LOW_15__Mask_15__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_15__Remote_IRR_15_MASK
- REDIRECTION_TABLE_ENTRY_LOW_15__Remote_IRR_15__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_15__Trigger_Mode_15_MASK
- REDIRECTION_TABLE_ENTRY_LOW_15__Trigger_Mode_15__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_15__Vector_15_MASK
- REDIRECTION_TABLE_ENTRY_LOW_15__Vector_15__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_16__Delivery_Mode_16_MASK
- REDIRECTION_TABLE_ENTRY_LOW_16__Delivery_Mode_16__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_16__Delivery_status_16_MASK
- REDIRECTION_TABLE_ENTRY_LOW_16__Delivery_status_16__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_16__Destination_Mode_16_MASK
- REDIRECTION_TABLE_ENTRY_LOW_16__Destination_Mode_16__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_16__Interrupt_Pin_Polarity_16_MASK
- REDIRECTION_TABLE_ENTRY_LOW_16__Interrupt_Pin_Polarity_16__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_16__Mask_16_MASK
- REDIRECTION_TABLE_ENTRY_LOW_16__Mask_16__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_16__Remote_IRR_16_MASK
- REDIRECTION_TABLE_ENTRY_LOW_16__Remote_IRR_16__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_16__Trigger_Mode_16_MASK
- REDIRECTION_TABLE_ENTRY_LOW_16__Trigger_Mode_16__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_16__Vector_16_MASK
- REDIRECTION_TABLE_ENTRY_LOW_16__Vector_16__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_17__Delivery_Mode_17_MASK
- REDIRECTION_TABLE_ENTRY_LOW_17__Delivery_Mode_17__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_17__Delivery_status_17_MASK
- REDIRECTION_TABLE_ENTRY_LOW_17__Delivery_status_17__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_17__Destination_Mode_17_MASK
- REDIRECTION_TABLE_ENTRY_LOW_17__Destination_Mode_17__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_17__Interrupt_Pin_Polarity_17_MASK
- REDIRECTION_TABLE_ENTRY_LOW_17__Interrupt_Pin_Polarity_17__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_17__Mask_17_MASK
- REDIRECTION_TABLE_ENTRY_LOW_17__Mask_17__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_17__Remote_IRR_17_MASK
- REDIRECTION_TABLE_ENTRY_LOW_17__Remote_IRR_17__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_17__Trigger_Mode_17_MASK
- REDIRECTION_TABLE_ENTRY_LOW_17__Trigger_Mode_17__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_17__Vector_17_MASK
- REDIRECTION_TABLE_ENTRY_LOW_17__Vector_17__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_18__Delivery_Mode_18_MASK
- REDIRECTION_TABLE_ENTRY_LOW_18__Delivery_Mode_18__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_18__Delivery_status_18_MASK
- REDIRECTION_TABLE_ENTRY_LOW_18__Delivery_status_18__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_18__Destination_Mode_18_MASK
- REDIRECTION_TABLE_ENTRY_LOW_18__Destination_Mode_18__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_18__Interrupt_Pin_Polarity_18_MASK
- REDIRECTION_TABLE_ENTRY_LOW_18__Interrupt_Pin_Polarity_18__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_18__Mask_18_MASK
- REDIRECTION_TABLE_ENTRY_LOW_18__Mask_18__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_18__Remote_IRR_18_MASK
- REDIRECTION_TABLE_ENTRY_LOW_18__Remote_IRR_18__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_18__Trigger_Mode_18_MASK
- REDIRECTION_TABLE_ENTRY_LOW_18__Trigger_Mode_18__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_18__Vector_18_MASK
- REDIRECTION_TABLE_ENTRY_LOW_18__Vector_18__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_19__Delivery_Mode_19_MASK
- REDIRECTION_TABLE_ENTRY_LOW_19__Delivery_Mode_19__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_19__Delivery_status_19_MASK
- REDIRECTION_TABLE_ENTRY_LOW_19__Delivery_status_19__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_19__Destination_Mode_19_MASK
- REDIRECTION_TABLE_ENTRY_LOW_19__Destination_Mode_19__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_19__Interrupt_Pin_Polarity_19_MASK
- REDIRECTION_TABLE_ENTRY_LOW_19__Interrupt_Pin_Polarity_19__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_19__Mask_19_MASK
- REDIRECTION_TABLE_ENTRY_LOW_19__Mask_19__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_19__Remote_IRR_19_MASK
- REDIRECTION_TABLE_ENTRY_LOW_19__Remote_IRR_19__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_19__Trigger_Mode_19_MASK
- REDIRECTION_TABLE_ENTRY_LOW_19__Trigger_Mode_19__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_19__Vector_19_MASK
- REDIRECTION_TABLE_ENTRY_LOW_19__Vector_19__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_1__Delivery_Mode_1_MASK
- REDIRECTION_TABLE_ENTRY_LOW_1__Delivery_Mode_1__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_1__Delivery_status_1_MASK
- REDIRECTION_TABLE_ENTRY_LOW_1__Delivery_status_1__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_1__Destination_Mode_1_MASK
- REDIRECTION_TABLE_ENTRY_LOW_1__Destination_Mode_1__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_1__Interrupt_Pin_Polarity_1_MASK
- REDIRECTION_TABLE_ENTRY_LOW_1__Interrupt_Pin_Polarity_1__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_1__Mask_1_MASK
- REDIRECTION_TABLE_ENTRY_LOW_1__Mask_1__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_1__Remote_IRR_1_MASK
- REDIRECTION_TABLE_ENTRY_LOW_1__Remote_IRR_1__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_1__Trigger_Mode_1_MASK
- REDIRECTION_TABLE_ENTRY_LOW_1__Trigger_Mode_1__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_1__Vector_1_MASK
- REDIRECTION_TABLE_ENTRY_LOW_1__Vector_1__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_20__Delivery_Mode_20_MASK
- REDIRECTION_TABLE_ENTRY_LOW_20__Delivery_Mode_20__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_20__Delivery_status_20_MASK
- REDIRECTION_TABLE_ENTRY_LOW_20__Delivery_status_20__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_20__Destination_Mode_20_MASK
- REDIRECTION_TABLE_ENTRY_LOW_20__Destination_Mode_20__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_20__Interrupt_Pin_Polarity_20_MASK
- REDIRECTION_TABLE_ENTRY_LOW_20__Interrupt_Pin_Polarity_20__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_20__Mask_20_MASK
- REDIRECTION_TABLE_ENTRY_LOW_20__Mask_20__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_20__Remote_IRR_20_MASK
- REDIRECTION_TABLE_ENTRY_LOW_20__Remote_IRR_20__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_20__Trigger_Mode_20_MASK
- REDIRECTION_TABLE_ENTRY_LOW_20__Trigger_Mode_20__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_20__Vector_20_MASK
- REDIRECTION_TABLE_ENTRY_LOW_20__Vector_20__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_21__Delivery_Mode_21_MASK
- REDIRECTION_TABLE_ENTRY_LOW_21__Delivery_Mode_21__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_21__Delivery_status_21_MASK
- REDIRECTION_TABLE_ENTRY_LOW_21__Delivery_status_21__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_21__Destination_Mode_21_MASK
- REDIRECTION_TABLE_ENTRY_LOW_21__Destination_Mode_21__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_21__Interrupt_Pin_Polarity_21_MASK
- REDIRECTION_TABLE_ENTRY_LOW_21__Interrupt_Pin_Polarity_21__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_21__Mask_21_MASK
- REDIRECTION_TABLE_ENTRY_LOW_21__Mask_21__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_21__Remote_IRR_21_MASK
- REDIRECTION_TABLE_ENTRY_LOW_21__Remote_IRR_21__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_21__Trigger_Mode_21_MASK
- REDIRECTION_TABLE_ENTRY_LOW_21__Trigger_Mode_21__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_21__Vector_21_MASK
- REDIRECTION_TABLE_ENTRY_LOW_21__Vector_21__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_22__Delivery_Mode_22_MASK
- REDIRECTION_TABLE_ENTRY_LOW_22__Delivery_Mode_22__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_22__Delivery_status_22_MASK
- REDIRECTION_TABLE_ENTRY_LOW_22__Delivery_status_22__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_22__Destination_Mode_22_MASK
- REDIRECTION_TABLE_ENTRY_LOW_22__Destination_Mode_22__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_22__Interrupt_Pin_Polarity_22_MASK
- REDIRECTION_TABLE_ENTRY_LOW_22__Interrupt_Pin_Polarity_22__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_22__Mask_22_MASK
- REDIRECTION_TABLE_ENTRY_LOW_22__Mask_22__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_22__Remote_IRR_22_MASK
- REDIRECTION_TABLE_ENTRY_LOW_22__Remote_IRR_22__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_22__Trigger_Mode_22_MASK
- REDIRECTION_TABLE_ENTRY_LOW_22__Trigger_Mode_22__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_22__Vector_22_MASK
- REDIRECTION_TABLE_ENTRY_LOW_22__Vector_22__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_23__Delivery_Mode_23_MASK
- REDIRECTION_TABLE_ENTRY_LOW_23__Delivery_Mode_23__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_23__Delivery_status_23_MASK
- REDIRECTION_TABLE_ENTRY_LOW_23__Delivery_status_23__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_23__Destination_Mode_23_MASK
- REDIRECTION_TABLE_ENTRY_LOW_23__Destination_Mode_23__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_23__Interrupt_Pin_Polarity_23_MASK
- REDIRECTION_TABLE_ENTRY_LOW_23__Interrupt_Pin_Polarity_23__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_23__Mask_23_MASK
- REDIRECTION_TABLE_ENTRY_LOW_23__Mask_23__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_23__Remote_IRR_23_MASK
- REDIRECTION_TABLE_ENTRY_LOW_23__Remote_IRR_23__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_23__Trigger_Mode_23_MASK
- REDIRECTION_TABLE_ENTRY_LOW_23__Trigger_Mode_23__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_23__Vector_23_MASK
- REDIRECTION_TABLE_ENTRY_LOW_23__Vector_23__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_24__Delivery_Mode_24_MASK
- REDIRECTION_TABLE_ENTRY_LOW_24__Delivery_Mode_24__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_24__Delivery_status_24_MASK
- REDIRECTION_TABLE_ENTRY_LOW_24__Delivery_status_24__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_24__Destination_Mode_24_MASK
- REDIRECTION_TABLE_ENTRY_LOW_24__Destination_Mode_24__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_24__Interrupt_Pin_Polarity_24_MASK
- REDIRECTION_TABLE_ENTRY_LOW_24__Interrupt_Pin_Polarity_24__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_24__Mask_24_MASK
- REDIRECTION_TABLE_ENTRY_LOW_24__Mask_24__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_24__Remote_IRR_24_MASK
- REDIRECTION_TABLE_ENTRY_LOW_24__Remote_IRR_24__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_24__Trigger_Mode_24_MASK
- REDIRECTION_TABLE_ENTRY_LOW_24__Trigger_Mode_24__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_24__Vector_24_MASK
- REDIRECTION_TABLE_ENTRY_LOW_24__Vector_24__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_25__Delivery_Mode_25_MASK
- REDIRECTION_TABLE_ENTRY_LOW_25__Delivery_Mode_25__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_25__Delivery_status_25_MASK
- REDIRECTION_TABLE_ENTRY_LOW_25__Delivery_status_25__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_25__Destination_Mode_25_MASK
- REDIRECTION_TABLE_ENTRY_LOW_25__Destination_Mode_25__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_25__Interrupt_Pin_Polarity_25_MASK
- REDIRECTION_TABLE_ENTRY_LOW_25__Interrupt_Pin_Polarity_25__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_25__Mask_25_MASK
- REDIRECTION_TABLE_ENTRY_LOW_25__Mask_25__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_25__Remote_IRR_25_MASK
- REDIRECTION_TABLE_ENTRY_LOW_25__Remote_IRR_25__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_25__Trigger_Mode_25_MASK
- REDIRECTION_TABLE_ENTRY_LOW_25__Trigger_Mode_25__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_25__Vector_25_MASK
- REDIRECTION_TABLE_ENTRY_LOW_25__Vector_25__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_26__Delivery_Mode_26_MASK
- REDIRECTION_TABLE_ENTRY_LOW_26__Delivery_Mode_26__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_26__Delivery_status_26_MASK
- REDIRECTION_TABLE_ENTRY_LOW_26__Delivery_status_26__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_26__Destination_Mode_26_MASK
- REDIRECTION_TABLE_ENTRY_LOW_26__Destination_Mode_26__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_26__Interrupt_Pin_Polarity_26_MASK
- REDIRECTION_TABLE_ENTRY_LOW_26__Interrupt_Pin_Polarity_26__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_26__Mask_26_MASK
- REDIRECTION_TABLE_ENTRY_LOW_26__Mask_26__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_26__Remote_IRR_26_MASK
- REDIRECTION_TABLE_ENTRY_LOW_26__Remote_IRR_26__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_26__Trigger_Mode_26_MASK
- REDIRECTION_TABLE_ENTRY_LOW_26__Trigger_Mode_26__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_26__Vector_26_MASK
- REDIRECTION_TABLE_ENTRY_LOW_26__Vector_26__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_27__Delivery_Mode_27_MASK
- REDIRECTION_TABLE_ENTRY_LOW_27__Delivery_Mode_27__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_27__Delivery_status_27_MASK
- REDIRECTION_TABLE_ENTRY_LOW_27__Delivery_status_27__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_27__Destination_Mode_27_MASK
- REDIRECTION_TABLE_ENTRY_LOW_27__Destination_Mode_27__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_27__Interrupt_Pin_Polarity_27_MASK
- REDIRECTION_TABLE_ENTRY_LOW_27__Interrupt_Pin_Polarity_27__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_27__Mask_27_MASK
- REDIRECTION_TABLE_ENTRY_LOW_27__Mask_27__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_27__Remote_IRR_27_MASK
- REDIRECTION_TABLE_ENTRY_LOW_27__Remote_IRR_27__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_27__Trigger_Mode_27_MASK
- REDIRECTION_TABLE_ENTRY_LOW_27__Trigger_Mode_27__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_27__Vector_27_MASK
- REDIRECTION_TABLE_ENTRY_LOW_27__Vector_27__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_28__Delivery_Mode_28_MASK
- REDIRECTION_TABLE_ENTRY_LOW_28__Delivery_Mode_28__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_28__Delivery_status_28_MASK
- REDIRECTION_TABLE_ENTRY_LOW_28__Delivery_status_28__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_28__Destination_Mode_28_MASK
- REDIRECTION_TABLE_ENTRY_LOW_28__Destination_Mode_28__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_28__Interrupt_Pin_Polarity_28_MASK
- REDIRECTION_TABLE_ENTRY_LOW_28__Interrupt_Pin_Polarity_28__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_28__Mask_28_MASK
- REDIRECTION_TABLE_ENTRY_LOW_28__Mask_28__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_28__Remote_IRR_28_MASK
- REDIRECTION_TABLE_ENTRY_LOW_28__Remote_IRR_28__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_28__Trigger_Mode_28_MASK
- REDIRECTION_TABLE_ENTRY_LOW_28__Trigger_Mode_28__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_28__Vector_28_MASK
- REDIRECTION_TABLE_ENTRY_LOW_28__Vector_28__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_29__Delivery_Mode_29_MASK
- REDIRECTION_TABLE_ENTRY_LOW_29__Delivery_Mode_29__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_29__Delivery_status_29_MASK
- REDIRECTION_TABLE_ENTRY_LOW_29__Delivery_status_29__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_29__Destination_Mode_29_MASK
- REDIRECTION_TABLE_ENTRY_LOW_29__Destination_Mode_29__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_29__Interrupt_Pin_Polarity_29_MASK
- REDIRECTION_TABLE_ENTRY_LOW_29__Interrupt_Pin_Polarity_29__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_29__Mask_29_MASK
- REDIRECTION_TABLE_ENTRY_LOW_29__Mask_29__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_29__Remote_IRR_29_MASK
- REDIRECTION_TABLE_ENTRY_LOW_29__Remote_IRR_29__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_29__Trigger_Mode_29_MASK
- REDIRECTION_TABLE_ENTRY_LOW_29__Trigger_Mode_29__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_29__Vector_29_MASK
- REDIRECTION_TABLE_ENTRY_LOW_29__Vector_29__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_2__Delivery_Mode_2_MASK
- REDIRECTION_TABLE_ENTRY_LOW_2__Delivery_Mode_2__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_2__Delivery_status_2_MASK
- REDIRECTION_TABLE_ENTRY_LOW_2__Delivery_status_2__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_2__Destination_Mode_2_MASK
- REDIRECTION_TABLE_ENTRY_LOW_2__Destination_Mode_2__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_2__Interrupt_Pin_Polarity_2_MASK
- REDIRECTION_TABLE_ENTRY_LOW_2__Interrupt_Pin_Polarity_2__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_2__Mask_2_MASK
- REDIRECTION_TABLE_ENTRY_LOW_2__Mask_2__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_2__Remote_IRR_2_MASK
- REDIRECTION_TABLE_ENTRY_LOW_2__Remote_IRR_2__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_2__Trigger_Mode_2_MASK
- REDIRECTION_TABLE_ENTRY_LOW_2__Trigger_Mode_2__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_2__Vector_2_MASK
- REDIRECTION_TABLE_ENTRY_LOW_2__Vector_2__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_30__Delivery_Mode_30_MASK
- REDIRECTION_TABLE_ENTRY_LOW_30__Delivery_Mode_30__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_30__Delivery_status_30_MASK
- REDIRECTION_TABLE_ENTRY_LOW_30__Delivery_status_30__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_30__Destination_Mode_30_MASK
- REDIRECTION_TABLE_ENTRY_LOW_30__Destination_Mode_30__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_30__Interrupt_Pin_Polarity_30_MASK
- REDIRECTION_TABLE_ENTRY_LOW_30__Interrupt_Pin_Polarity_30__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_30__Mask_30_MASK
- REDIRECTION_TABLE_ENTRY_LOW_30__Mask_30__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_30__Remote_IRR_30_MASK
- REDIRECTION_TABLE_ENTRY_LOW_30__Remote_IRR_30__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_30__Trigger_Mode_30_MASK
- REDIRECTION_TABLE_ENTRY_LOW_30__Trigger_Mode_30__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_30__Vector_30_MASK
- REDIRECTION_TABLE_ENTRY_LOW_30__Vector_30__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_31__Delivery_Mode_31_MASK
- REDIRECTION_TABLE_ENTRY_LOW_31__Delivery_Mode_31__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_31__Delivery_status_31_MASK
- REDIRECTION_TABLE_ENTRY_LOW_31__Delivery_status_31__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_31__Destination_Mode_31_MASK
- REDIRECTION_TABLE_ENTRY_LOW_31__Destination_Mode_31__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_31__Interrupt_Pin_Polarity_31_MASK
- REDIRECTION_TABLE_ENTRY_LOW_31__Interrupt_Pin_Polarity_31__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_31__Mask_31_MASK
- REDIRECTION_TABLE_ENTRY_LOW_31__Mask_31__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_31__Remote_IRR_31_MASK
- REDIRECTION_TABLE_ENTRY_LOW_31__Remote_IRR_31__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_31__Trigger_Mode_31_MASK
- REDIRECTION_TABLE_ENTRY_LOW_31__Trigger_Mode_31__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_31__Vector_31_MASK
- REDIRECTION_TABLE_ENTRY_LOW_31__Vector_31__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_3__Delivery_Mode_3_MASK
- REDIRECTION_TABLE_ENTRY_LOW_3__Delivery_Mode_3__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_3__Delivery_status_3_MASK
- REDIRECTION_TABLE_ENTRY_LOW_3__Delivery_status_3__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_3__Destination_Mode_3_MASK
- REDIRECTION_TABLE_ENTRY_LOW_3__Destination_Mode_3__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_3__Interrupt_Pin_Polarity_3_MASK
- REDIRECTION_TABLE_ENTRY_LOW_3__Interrupt_Pin_Polarity_3__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_3__Mask_3_MASK
- REDIRECTION_TABLE_ENTRY_LOW_3__Mask_3__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_3__Remote_IRR_3_MASK
- REDIRECTION_TABLE_ENTRY_LOW_3__Remote_IRR_3__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_3__Trigger_Mode_3_MASK
- REDIRECTION_TABLE_ENTRY_LOW_3__Trigger_Mode_3__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_3__Vector_3_MASK
- REDIRECTION_TABLE_ENTRY_LOW_3__Vector_3__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_4__Delivery_Mode_4_MASK
- REDIRECTION_TABLE_ENTRY_LOW_4__Delivery_Mode_4__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_4__Delivery_status_4_MASK
- REDIRECTION_TABLE_ENTRY_LOW_4__Delivery_status_4__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_4__Destination_Mode_4_MASK
- REDIRECTION_TABLE_ENTRY_LOW_4__Destination_Mode_4__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_4__Interrupt_Pin_Polarity_4_MASK
- REDIRECTION_TABLE_ENTRY_LOW_4__Interrupt_Pin_Polarity_4__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_4__Mask_4_MASK
- REDIRECTION_TABLE_ENTRY_LOW_4__Mask_4__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_4__Remote_IRR_4_MASK
- REDIRECTION_TABLE_ENTRY_LOW_4__Remote_IRR_4__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_4__Trigger_Mode_4_MASK
- REDIRECTION_TABLE_ENTRY_LOW_4__Trigger_Mode_4__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_4__Vector_4_MASK
- REDIRECTION_TABLE_ENTRY_LOW_4__Vector_4__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_5__Delivery_Mode_5_MASK
- REDIRECTION_TABLE_ENTRY_LOW_5__Delivery_Mode_5__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_5__Delivery_status_5_MASK
- REDIRECTION_TABLE_ENTRY_LOW_5__Delivery_status_5__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_5__Destination_Mode_5_MASK
- REDIRECTION_TABLE_ENTRY_LOW_5__Destination_Mode_5__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_5__Interrupt_Pin_Polarity_5_MASK
- REDIRECTION_TABLE_ENTRY_LOW_5__Interrupt_Pin_Polarity_5__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_5__Mask_5_MASK
- REDIRECTION_TABLE_ENTRY_LOW_5__Mask_5__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_5__Remote_IRR_5_MASK
- REDIRECTION_TABLE_ENTRY_LOW_5__Remote_IRR_5__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_5__Trigger_Mode_5_MASK
- REDIRECTION_TABLE_ENTRY_LOW_5__Trigger_Mode_5__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_5__Vector_5_MASK
- REDIRECTION_TABLE_ENTRY_LOW_5__Vector_5__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_6__Delivery_Mode_6_MASK
- REDIRECTION_TABLE_ENTRY_LOW_6__Delivery_Mode_6__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_6__Delivery_status_6_MASK
- REDIRECTION_TABLE_ENTRY_LOW_6__Delivery_status_6__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_6__Destination_Mode_6_MASK
- REDIRECTION_TABLE_ENTRY_LOW_6__Destination_Mode_6__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_6__Interrupt_Pin_Polarity_6_MASK
- REDIRECTION_TABLE_ENTRY_LOW_6__Interrupt_Pin_Polarity_6__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_6__Mask_6_MASK
- REDIRECTION_TABLE_ENTRY_LOW_6__Mask_6__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_6__Remote_IRR_6_MASK
- REDIRECTION_TABLE_ENTRY_LOW_6__Remote_IRR_6__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_6__Trigger_Mode_6_MASK
- REDIRECTION_TABLE_ENTRY_LOW_6__Trigger_Mode_6__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_6__Vector_6_MASK
- REDIRECTION_TABLE_ENTRY_LOW_6__Vector_6__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_7__Delivery_Mode_7_MASK
- REDIRECTION_TABLE_ENTRY_LOW_7__Delivery_Mode_7__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_7__Delivery_status_7_MASK
- REDIRECTION_TABLE_ENTRY_LOW_7__Delivery_status_7__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_7__Destination_Mode_7_MASK
- REDIRECTION_TABLE_ENTRY_LOW_7__Destination_Mode_7__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_7__Interrupt_Pin_Polarity_7_MASK
- REDIRECTION_TABLE_ENTRY_LOW_7__Interrupt_Pin_Polarity_7__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_7__Mask_7_MASK
- REDIRECTION_TABLE_ENTRY_LOW_7__Mask_7__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_7__Remote_IRR_7_MASK
- REDIRECTION_TABLE_ENTRY_LOW_7__Remote_IRR_7__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_7__Trigger_Mode_7_MASK
- REDIRECTION_TABLE_ENTRY_LOW_7__Trigger_Mode_7__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_7__Vector_7_MASK
- REDIRECTION_TABLE_ENTRY_LOW_7__Vector_7__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_8__Delivery_Mode_8_MASK
- REDIRECTION_TABLE_ENTRY_LOW_8__Delivery_Mode_8__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_8__Delivery_status_8_MASK
- REDIRECTION_TABLE_ENTRY_LOW_8__Delivery_status_8__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_8__Destination_Mode_8_MASK
- REDIRECTION_TABLE_ENTRY_LOW_8__Destination_Mode_8__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_8__Interrupt_Pin_Polarity_8_MASK
- REDIRECTION_TABLE_ENTRY_LOW_8__Interrupt_Pin_Polarity_8__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_8__Mask_8_MASK
- REDIRECTION_TABLE_ENTRY_LOW_8__Mask_8__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_8__Remote_IRR_8_MASK
- REDIRECTION_TABLE_ENTRY_LOW_8__Remote_IRR_8__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_8__Trigger_Mode_8_MASK
- REDIRECTION_TABLE_ENTRY_LOW_8__Trigger_Mode_8__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_8__Vector_8_MASK
- REDIRECTION_TABLE_ENTRY_LOW_8__Vector_8__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_9__Delivery_Mode_9_MASK
- REDIRECTION_TABLE_ENTRY_LOW_9__Delivery_Mode_9__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_9__Delivery_status_9_MASK
- REDIRECTION_TABLE_ENTRY_LOW_9__Delivery_status_9__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_9__Destination_Mode_9_MASK
- REDIRECTION_TABLE_ENTRY_LOW_9__Destination_Mode_9__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_9__Interrupt_Pin_Polarity_9_MASK
- REDIRECTION_TABLE_ENTRY_LOW_9__Interrupt_Pin_Polarity_9__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_9__Mask_9_MASK
- REDIRECTION_TABLE_ENTRY_LOW_9__Mask_9__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_9__Remote_IRR_9_MASK
- REDIRECTION_TABLE_ENTRY_LOW_9__Remote_IRR_9__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_9__Trigger_Mode_9_MASK
- REDIRECTION_TABLE_ENTRY_LOW_9__Trigger_Mode_9__SHIFT
- REDIRECTION_TABLE_ENTRY_LOW_9__Vector_9_MASK
- REDIRECTION_TABLE_ENTRY_LOW_9__Vector_9__SHIFT
- REDIR_ERROR
- REDIR_RES_MAX
- REDIR_SUCCESS
- REDMEMA
- REDMEMB
- REDRESTORES
- REDSAVES
- REDUCED_DEBOUNCE
- REDUCED_POWER_SCLK_HILEN
- REDUCED_POWER_SCLK_LOLEN
- REDUCED_SPEED_SCLK_EN
- REDUCED_SPEED_SCLK_MODE
- REDUCED_SPEED_SCLK_SEL
- REDUCED_TX_HEADROOM
- REDUCE_CHAIN_0
- REDUCE_CHAIN_1
- REDUCE_EXCHANGES_CNT
- REDUCE_FLS
- REDUCE_REPORTING
- REDUCE_TX_POWER_CMD
- REDWOOD_GB_ADDR_CONFIG_GOLDEN
- REDWOOD_MGCGCGTSSMCTRL_DFLT
- REDWOOD_SMC_INT_VECTOR_SIZE
- REDWOOD_SMC_INT_VECTOR_START
- REDWOOD_SMC_UCODE_SIZE
- REDWOOD_SMC_UCODE_START
- REDZONE_ALIGN
- RED_ABOVE_MAX_TRESH
- RED_ACTIVE
- RED_BALANCE_DEFAULT
- RED_BELOW_MIN_THRESH
- RED_BETWEEN_TRESH
- RED_DEFAULT
- RED_DIS_CNT
- RED_DIS_CNT_COUNT
- RED_DIS_CNT_OFLOW
- RED_DONT_MARK
- RED_ECC_LOCATOR
- RED_GAIN_DEFAULT
- RED_HARD_MARK
- RED_INACTIVE
- RED_LED
- RED_MASK
- RED_ONE_PERCENT
- RED_PROB_MARK
- RED_RAN_INIT
- RED_RAN_INIT_OPMODE
- RED_RAN_INIT_VAL
- RED_SHIFT
- RED_STAB_MASK
- RED_STAB_SIZE
- RED_START
- RED_STAT_RAM
- RED_X_INC
- RED_X_INC__ALIAS__
- RED_Y_INC
- REED_SOLOMON_CTRL_REG
- REED_SOLOMON_ERROR_COUNT_REG_L
- REENABLE_IRQS
- REF
- REF125CK_MARK
- REF1CLK
- REF2CLK
- REF2USB_EN_MASK
- REF2USB_TX_EN
- REF2USB_TX_LPF_EN
- REF2USB_TX_OUT_EN
- REF3CLK
- REF4CLK
- REF50CK_MARK
- REF5CLK
- REFCLK
- REFCLKDIV
- REFCLKDIV_MASK
- REFCLKI1R
- REFCLKI3R
- REFCLKI4R
- REFCLKMODE
- REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY_MASK
- REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_OFF_DELAY__SHIFT
- REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY_MASK
- REFCLK_CGTT_BLK_CTRL_REG__REFCLK_TURN_ON_DELAY__SHIFT
- REFCLK_CLK_CORE
- REFCLK_CLOCK_EN
- REFCLK_CLOCK_EN_ALLOW_SRC
- REFCLK_CLOCK_EN_ALLOW_SRC_SEL
- REFCLK_CLOCK_EN_PCIE_REFCLK
- REFCLK_CLOCK_EN_XTALIN_CLK
- REFCLK_CNTL__REFCLK_CLOCK_EN_MASK
- REFCLK_CNTL__REFCLK_CLOCK_EN__SHIFT
- REFCLK_CNTL__REFCLK_SRC_SEL_MASK
- REFCLK_CNTL__REFCLK_SRC_SEL__SHIFT
- REFCLK_DRV_DSBL
- REFCLK_FREQ
- REFCLK_FREQ_MASK
- REFCLK_LSE
- REFCLK_SEL
- REFCLK_SRC_SEL
- REFCLK_SRC_SEL_CPL_REFCLK
- REFCLK_SRC_SEL_DISPPLL
- REFCLK_SRC_SEL_PCIE_REFCLK
- REFCLK_SRC_SEL_XTALIN
- REFCLK_X0_EXT_CLK
- REFCLK_XO_CRYSTAL
- REFCLOCK_MHz
- REFCLOCK_kHz
- REFCNTBT_AGBLOCK_BITLEN
- REFCNTBT_COWFLAG_BITLEN
- REFCOUNT
- REFCOUNT_CHECK_LE_ZERO
- REFCOUNT_CHECK_LT_ZERO
- REFCOUNT_ERROR
- REFCOUNT_INIT
- REFCOUNT_MAX
- REFCOUNT_SATURATED
- REFCOUNT_WARN
- REFDIV_VAL_100M
- REFDIV_VAL_50M
- REFERENCE_CTR
- REFERENCE_PERF
- REFERRAL3
- REFER_TO_DP_SOF
- REFER_TO_OTG_SOF
- REFILE_ANYWAY
- REFILE_NOTEMPTY
- REFILL_BUFFER_SIZE
- REFIRE_CMD
- REFLECT
- REFOUT_MARK
- REFO_ACTIVE
- REFO_DIVSW_EN
- REFO_DIV_MASK
- REFO_DIV_SHIFT
- REFO_OE
- REFO_ON
- REFO_SEL_MASK
- REFO_SEL_SHIFT
- REFO_TRIM_MASK
- REFO_TRIM_MAX
- REFO_TRIM_REG
- REFO_TRIM_SHIFT
- REFRESH
- REFRESHRATE
- REFRESH_AB_CTRL
- REFRESH_CD_CTRL
- REFRESH_EN_MASK
- REFRESH_EN_SHIFT
- REFRESH_INTERVAL
- REFRESH_RATE_DIVISOR
- REFRESH_RATE_DIVISOR_MASK
- REFRESH_RATE_DIVISOR_SHIFT
- REFRESH_RATE_MASK
- REFRESH_RATE_SHIFT
- REFRESH_SEQ0
- REFRESH_SEQ1
- REFRESH_SIZE
- REFRESH_START
- REFRESH_THRESHOLD
- REFRESH_TIME_NS
- REFS_PER_BLOCK
- REFS_PER_FRAME
- REFTAG_ERR
- REF_2_PERST_MAX
- REF_2_PERST_MIN
- REF_ALWAYS
- REF_BIAS_CUR_SEL
- REF_CHK_ERR
- REF_CLK
- REF_CLK1_8kHz
- REF_CLK2_19_44MHz
- REF_CLKO_MARK
- REF_CLK_24M
- REF_CLK_27M
- REF_CLK_CORE
- REF_CLK_CYC_PER_DVCO_SAMPLE
- REF_CLK_DIV_BY_5
- REF_CLK_DPLL
- REF_CLK_DPLLA
- REF_CLK_FREQ
- REF_CLK_FREQ_19_2_MHZ
- REF_CLK_FREQ_26_MHZ
- REF_CLK_FREQ_38_4_MHZ
- REF_CLK_FREQ_52_MHZ
- REF_CLK_FREQ_INVAL
- REF_CLK_FULL
- REF_CLK_FULL_DD
- REF_CLK_GATE
- REF_CLK_GATE_DIV
- REF_CLK_GEAR
- REF_CLK_MASK
- REF_CLK_MUX_DD
- REF_CLK_PM_CPU
- REF_CLK_STABLE_TIME
- REF_CLOCK_RATE
- REF_CMU
- REF_CONTIG_LEFT
- REF_CONTIG_LEFTRIGHT
- REF_CONTIG_NONE
- REF_CONTIG_RIGHT
- REF_DECREMENT
- REF_DIV_1
- REF_DIV_2595
- REF_DIV_4
- REF_EMPTY_NODE
- REF_EQUAL
- REF_ERR_CALIB_PARAM_SET
- REF_ERR_CALIB_PERIODICITY_SET
- REF_EVT
- REF_FREF_SEL_25
- REF_FREQ
- REF_FREQ_13M
- REF_FREQ_19M2
- REF_FREQ_19_2
- REF_FREQ_2595
- REF_FREQ_26M
- REF_FREQ_26_0
- REF_FREQ_33_6
- REF_FREQ_38M4
- REF_FREQ_38_4
- REF_FREQ_40_0
- REF_FREQ_NUM
- REF_GEQUAL
- REF_GP_MAX_CLIENT
- REF_GP_NO_CLIENTS
- REF_GREATER
- REF_INCREMENT
- REF_LEQUAL
- REF_LESS
- REF_LINK_NODE
- REF_MAX
- REF_MIN
- REF_NEVER
- REF_NOISE_LVL_MRGN_THRSHLD_REG
- REF_NORMAL
- REF_NOTEQUAL
- REF_OBSOLETE
- REF_OFF
- REF_ON
- REF_PATH
- REF_PHANDLE
- REF_PRISTINE
- REF_RATE
- REF_RCMI
- REF_REG_RET
- REF_REG_SP
- REF_SET
- REF_SSP_EN
- REF_ST_MASK
- REF_ST_SHIFT
- REF_UNCHECKED
- REF_USE_PAD
- REF_VMBCH_SEL_MASK
- REF_VMBCH_SEL_SHIFT
- REG
- REG0
- REG04
- REG04_AEC_SET
- REG04_DEF
- REG04_HFLIP_IMG
- REG04_HREF_EN
- REG04_VFLIP_IMG
- REG04_VREF_EN
- REG08
- REG08_DEF
- REG0C_IMG_FLIP
- REG0C_IMG_MIRROR
- REG0_ADDR
- REG0_DATA
- REG0_INIT_VAL
- REG0_RATE_MASK
- REG1
- REG13_AEC_EN
- REG13_AGC_EN
- REG15_GAIN_MSB
- REG16
- REG1_ADDR
- REG1_DATA
- REG1_ENABLE
- REG1_IRQSEL_FALL
- REG1_IRQSEL_MASK
- REG1_IRQSEL_NEC_MODE
- REG1_IRQSEL_RISE
- REG1_IRQSEL_RISE_FALL
- REG1_MODE_MASK
- REG1_MODE_SHIFT
- REG1_RESET
- REG1_TIME_IV_MASK
- REG2
- REG28
- REG2A
- REG2ADDR
- REG2PAGE
- REG2_ADDR
- REG2_DATA
- REG2_MODE_MASK
- REG2_MODE_SHIFT
- REG3
- REG32
- REG32_PCLK_DIV_2
- REG32_PCLK_DIV_4
- REG3_ADDR
- REG3_DATA
- REG45
- REG4_SPEED_MASK
- REG50080_FLIP_TYPE_ASYNC
- REG50080_FLIP_TYPE_MASK
- REG53
- REG5A
- REG5D
- REG5E
- REG5F
- REG60
- REG64
- REG64_IDX
- REG8
- REG8_1
- REG8_2
- REG8_8
- REG9
- REG9_SPEED_MASK
- REGA
- REGADDRPTR
- REGAD_MASK
- REGAINED_BSS_EVENT_ID
- REGALLOC
- REGAMMA_BYPASS
- REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK
- REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT
- REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK
- REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT
- REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK
- REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT
- REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK
- REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT
- REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK
- REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK
- REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT
- REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK
- REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK
- REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT
- REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK
- REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK
- REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT
- REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK
- REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK
- REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT
- REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK
- REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK
- REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT
- REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK
- REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK
- REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT
- REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK
- REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK
- REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT
- REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK
- REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK
- REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT
- REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK
- REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK
- REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT
- REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK
- REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK
- REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT
- REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK
- REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK
- REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT
- REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK
- REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK
- REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT
- REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK
- REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK
- REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT
- REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK
- REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK
- REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT
- REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK
- REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK
- REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT
- REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK
- REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK
- REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT
- REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK
- REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK
- REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT
- REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT
- REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK
- REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT
- REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK
- REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT
- REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK
- REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT
- REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK
- REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT
- REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK
- REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK
- REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT
- REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK
- REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK
- REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT
- REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK
- REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK
- REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT
- REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK
- REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK
- REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT
- REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK
- REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK
- REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT
- REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK
- REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK
- REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT
- REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK
- REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK
- REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT
- REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK
- REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK
- REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT
- REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK
- REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK
- REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT
- REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK
- REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK
- REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT
- REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK
- REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK
- REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT
- REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK
- REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK
- REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT
- REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK
- REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK
- REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT
- REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK
- REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK
- REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT
- REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK
- REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK
- REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT
- REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK
- REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT
- REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK
- REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT
- REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK
- REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK
- REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT
- REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT
- REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK
- REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT
- REGAMMA_CONTROL__OVL_REGAMMA_MODE_MASK
- REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT
- REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK
- REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT
- REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK
- REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT
- REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK
- REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT
- REGAMMA_PROG_A
- REGAMMA_PROG_B
- REGAMMA_SRGB_24
- REGAMMA_XVYCC_222
- REGA_DEVC
- REGA_DLB
- REGA_MODE_DATA
- REGA_MODE_MIXED
- REGA_MODE_PRO
- REGA_RESET
- REGA_SLB
- REGB
- REGBASE
- REGB_CEE
- REGB_DIRATE
- REGB_ENABLE_RESET
- REGB_MCDIV
- REGB_SCDIV
- REGB_STOP_CLOCK
- REGC38_TH
- REGCACHE_COMPRESSED
- REGCACHE_FLAT
- REGCACHE_NONE
- REGCACHE_RBTREE
- REGCTL1
- REGCTL2
- REGC_PUADC
- REGC_PUDAC
- REGC_PUDEV
- REGC_PUREF
- REGC_REFUSE
- REGDATA
- REGDEF
- REGDMN_CAP1_CHAN_HAL49GHZ
- REGDMN_CAP1_CHAN_HALF_RATE
- REGDMN_CAP1_CHAN_QUARTER_RATE
- REGDMN_EEPROM_EEREGCAP_EN_FCC_MIDBAND
- REGDMN_EEPROM_EEREGCAP_EN_KK_MIDBAND
- REGDMN_EEPROM_EEREGCAP_EN_KK_NEW_11A
- REGDMN_EEPROM_EEREGCAP_EN_KK_U1_EVEN
- REGDMN_EEPROM_EEREGCAP_EN_KK_U1_ODD
- REGDMN_EEPROM_EEREGCAP_EN_KK_U2
- REGDMN_MODE_108A
- REGDMN_MODE_108G
- REGDMN_MODE_11A
- REGDMN_MODE_11AC_VHT160
- REGDMN_MODE_11AC_VHT20
- REGDMN_MODE_11AC_VHT40MINUS
- REGDMN_MODE_11AC_VHT40PLUS
- REGDMN_MODE_11AC_VHT80
- REGDMN_MODE_11AC_VHT80_80
- REGDMN_MODE_11A_HALF_RATE
- REGDMN_MODE_11A_QUARTER_RATE
- REGDMN_MODE_11B
- REGDMN_MODE_11G
- REGDMN_MODE_11NA_HT20
- REGDMN_MODE_11NA_HT40MINUS
- REGDMN_MODE_11NA_HT40PLUS
- REGDMN_MODE_11NG_HT20
- REGDMN_MODE_11NG_HT40MINUS
- REGDMN_MODE_11NG_HT40PLUS
- REGDMN_MODE_ALL
- REGDMN_MODE_PUREG
- REGDMN_MODE_TURBO
- REGDMN_MODE_XR
- REGDOMAINSZ
- REGDUMP
- REGDUMP_HEADER_ENGINE_SHIFT
- REGDUMP_HEADER_FEATURE_SHIFT
- REGDUMP_HEADER_OMIT_ENGINE_SHIFT
- REGDUMP_HEADER_SIZE
- REGDUMP_LINE_SIZE
- REGD_COMMON_H
- REGD_H
- REGD_IGS
- REGD_MUTE
- REGD_OGS
- REGD_RMOD
- REGD_SOURCE_CACHED
- REGD_SOURCE_CRDA
- REGD_SOURCE_INTERNAL_DB
- REGED
- REGED_CLK_OUT_DIS
- REGEN_MAX_RETRY
- REGE_DA
- REGE_IBYP
- REGFIELD_MAX
- REGF_ALB
- REGF_INV
- REGF_SEEN
- REGI
- REGIDX_010
- REGIDX_014
- REGIDX_018
- REGIDX_020
- REGIDX_024
- REGIDX_02C
- REGIDX_030
- REGIDX_214
- REGIDX_2E0
- REGIDX_2E4
- REGIDX_2E8
- REGIDX_2EC
- REGIDX_2F0
- REGIDX_2F4
- REGIDX_2F8
- REGIDX_PLL
- REGIDX_RFC
- REGIN_INPUT
- REGIN_VALID
- REGION
- REGION3_KERNEL
- REGION3_KERNEL_RO
- REGIONSIZE_COARSE
- REGIONSIZE_FINE
- REGION_ACCESS_SIZE_LIMIT
- REGION_ACCESS_SIZE_MASK
- REGION_BASE
- REGION_CRC_INT
- REGION_DISJOINT
- REGION_ENTRY_INVALID
- REGION_ENTRY_LENGTH
- REGION_ENTRY_NOEXEC
- REGION_ENTRY_OFFSET
- REGION_ENTRY_ORIGIN
- REGION_ENTRY_PROTECT
- REGION_ENTRY_TYPE
- REGION_ID
- REGION_INTERSECTS
- REGION_LENGTH
- REGION_MAPPING
- REGION_MASK
- REGION_MIXED
- REGION_NUMBER
- REGION_OFFSET
- REGION_OFFSET_TO_PHYS
- REGION_SEL1_MASK
- REGION_SEL1_SHIFT
- REGION_SEL2_MASK
- REGION_SEL2_SHIFT
- REGION_SHIFT
- REGION_TYPE
- REGION_TYPE_EXCLUSIVE
- REGION_TYPE_SHARED_READ
- REGION_TYPE_SHARED_WRITE
- REGION_TYPE_UNUSED
- REGISTER
- REGISTER0
- REGISTER0_HSCLOCKCONFIG
- REGISTER0_THS_SETTLE_MASK
- REGISTER0_THS_SETTLE_SHIFT
- REGISTER0_THS_TERM_MASK
- REGISTER0_THS_TERM_SHIFT
- REGISTER1
- REGISTER1_CLOCK_MISS_DETECTOR_STATUS
- REGISTER1_CTRLCLK_DIV_FACTOR_MASK
- REGISTER1_CTRLCLK_DIV_FACTOR_SHIFT
- REGISTER1_DPHY_HS_SYNC_PATTERN_SHIFT
- REGISTER1_RESET_DONE_CTRLCLK
- REGISTER1_TCLK_SETTLE_MASK
- REGISTER1_TCLK_SETTLE_SHIFT
- REGISTER1_TCLK_TERM_MASK
- REGISTER1_TCLK_TERM_SHIFT
- REGISTER2
- REGISTERED_DIMM
- REGISTERS
- REGISTERS_BASE
- REGISTERS_DOWN_SIZE
- REGISTERS_STR
- REGISTERS_WORK_SIZE
- REGISTER_AA
- REGISTER_AB
- REGISTER_ACCESS
- REGISTER_AND_IGNORE_EXISTING_KEY
- REGISTER_AND_MOVE
- REGISTER_AZ
- REGISTER_BASED
- REGISTER_BB
- REGISTER_BUSY_COUNT
- REGISTER_BUSY_DELAY
- REGISTER_BZ
- REGISTER_CLK
- REGISTER_CZ
- REGISTER_DESC_WITH_BITS_PER_IRQ
- REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED
- REGISTER_DESC_WITH_LENGTH
- REGISTER_DESC_WITH_LENGTH_UACCESS
- REGISTER_DSI0_CLK
- REGISTER_DSI1_CLK
- REGISTER_DUMP_COUNT
- REGISTER_DUMP_LEN_MAX
- REGISTER_DZ
- REGISTER_FLD_WAIT
- REGISTER_GATE
- REGISTER_ITS_DESC
- REGISTER_ITS_DESC_UACCESS
- REGISTER_LENGTH
- REGISTER_LINK_STATUS
- REGISTER_M
- REGISTER_OSC_CLK
- REGISTER_PCM_CLK
- REGISTER_PER_CLK
- REGISTER_PLL
- REGISTER_PLL_DIV
- REGISTER_PROTOCOL
- REGISTER_READ
- REGISTER_READ_AUX
- REGISTER_READ_WITH_AUX
- REGISTER_REPORT
- REGISTER_REPORT_SIZE
- REGISTER_REVISION_ED
- REGISTER_REVISION_EZ
- REGISTER_REVISION_FA
- REGISTER_REVISION_FB
- REGISTER_REVISION_FC
- REGISTER_REVISION_FZ
- REGISTER_S
- REGISTER_STRIDE
- REGISTER_TABLE
- REGISTER_TABLE_AA
- REGISTER_TABLE_AZ
- REGISTER_TABLE_BB
- REGISTER_TABLE_BB_CZ
- REGISTER_TABLE_BZ
- REGISTER_TABLE_CZ
- REGISTER_TABLE_DIMENSIONS
- REGISTER_TABLE_DZ
- REGISTER_TIMEOUT
- REGISTER_TIMEOUT_FIRMWARE
- REGISTER_USB_BUSY_COUNT
- REGISTER_V
- REGISTER_VPU_CLK
- REGISTER_WRITE
- REGISTER_WRITE16
- REGISTER_WRITE8
- REGISTER_WRITE_AUX
- REGISTER_WRITE_WITH_AUX
- REGJ
- REGLEN_0bit
- REGLEN_16bit
- REGLEN_8bit
- REGLOAD
- REGLOCK_PWRSEQ
- REGLOCK_VREG
- REGMACH64_H
- REGMAP_ALLOW_WRITE_DEBUGFS
- REGMAP_ENDIAN_BIG
- REGMAP_ENDIAN_DEFAULT
- REGMAP_ENDIAN_LITTLE
- REGMAP_ENDIAN_NATIVE
- REGMAP_IRQ_MAIN_REG_OFFSET
- REGMAP_IRQ_REG
- REGMAP_IRQ_REG_LINE
- REGMASK
- REGMASK_BITS
- REGMODE16
- REGMODE32
- REGMODE8
- REGOUT_INVALID
- REGOUT_VALID
- REGPROG_INF
- REGRDBLEN_BMSK
- REGRDBLEN_SHFT
- REGS
- REGSET_ARCV2
- REGSET_CMN
- REGSET_COMPAT_GPR
- REGSET_COMPAT_VFP
- REGSET_DSCR
- REGSET_DSP
- REGSET_EBB
- REGSET_F
- REGSET_FP
- REGSET_FPR
- REGSET_FPU
- REGSET_FP_MODE
- REGSET_GENERAL
- REGSET_GPR
- REGSET_HW_BREAK
- REGSET_HW_WATCH
- REGSET_IOPERM32
- REGSET_IOPERM64
- REGSET_MSA
- REGSET_PACA_KEYS
- REGSET_PACG_KEYS
- REGSET_PAC_MASK
- REGSET_PKEY
- REGSET_PMR
- REGSET_PPR
- REGSET_SPE
- REGSET_SVE
- REGSET_SYSTEM_CALL
- REGSET_TAR
- REGSET_TIE
- REGSET_TLS
- REGSET_TM_CDSCR
- REGSET_TM_CFPR
- REGSET_TM_CGPR
- REGSET_TM_CPPR
- REGSET_TM_CTAR
- REGSET_TM_CVMX
- REGSET_TM_CVSX
- REGSET_TM_SPR
- REGSET_VFP
- REGSET_VMX
- REGSET_VSX
- REGSET_X
- REGSET_XFP
- REGSET_XSTATE
- REGSIZE
- REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET
- REGSPEC_CFG_I_RX_WORDMODE0_SET
- REGSPEC_CFG_I_TX_WORDMODE0_SET
- REGSPEC_RESET_F1_MASK
- REGSPEC_TEST_MODE_SET
- REGSTORE
- REGS_A3700
- REGS_ADDR
- REGS_AX
- REGS_BP
- REGS_BX
- REGS_CE4100
- REGS_COUNT
- REGS_CS
- REGS_CX
- REGS_DI
- REGS_DS
- REGS_DX
- REGS_EFLAGS
- REGS_END
- REGS_ES
- REGS_GSC_H_
- REGS_H
- REGS_IN_ENTRY
- REGS_IP
- REGS_IP_INDEX
- REGS_OFFSET_NAME
- REGS_PER_GTF
- REGS_PER_LINE
- REGS_PXA2XX
- REGS_PXA3XX
- REGS_PXA910
- REGS_R10
- REGS_R11
- REGS_R12
- REGS_R13
- REGS_R14
- REGS_R15
- REGS_R8
- REGS_R9
- REGS_RESTORE
- REGS_SAVE
- REGS_SI
- REGS_SIZE
- REGS_SP
- REGS_SP_INDEX
- REGS_SS
- REGTBL_NUM
- REGTYPE_STR_LEN
- REGULAR_BLINK
- REGULAR_FILE_FOUND
- REGULAR_PID_TBL_REG_ADDRESS_0
- REGULAR_PID_TBL_REG_ADDRESS_1
- REGULAR_PID_TBL_REG_ADDRESS_2
- REGULAR_PID_TBL_REG_ADDRESS_3
- REGULAR_PID_TBL_REG_ADDRESS_4
- REGULAR_PID_TBL_REG_ADDRESS_5
- REGULAR_PID_TBL_REG_ADDRESS_6
- REGULAR_PID_TBL_REG_ADDRESS_7
- REGULAR_PRESET
- REGULAR_RX_BUF_SIZE
- REGULATORY_AND_NVM_GROUP
- REGULATORY_COUNTRY_IE_FOLLOW_POWER
- REGULATORY_COUNTRY_IE_IGNORE
- REGULATORY_CUSTOM_REG
- REGULATORY_DISABLE_BEACON_HINTS
- REGULATORY_ENABLE_RELAX_NO_IR
- REGULATORY_IGNORE_STALE_KICKOFF
- REGULATORY_STRICT_REG
- REGULATORY_WIPHY_SELF_MANAGED
- REGULATOR_ACTIVE_DISCHARGE_DEFAULT
- REGULATOR_ACTIVE_DISCHARGE_DISABLE
- REGULATOR_ACTIVE_DISCHARGE_ENABLE
- REGULATOR_CHANGE_BYPASS
- REGULATOR_CHANGE_CURRENT
- REGULATOR_CHANGE_DRMS
- REGULATOR_CHANGE_MODE
- REGULATOR_CHANGE_STATUS
- REGULATOR_CHANGE_VOLTAGE
- REGULATOR_CONSUMER
- REGULATOR_CURRENT
- REGULATOR_DCDC
- REGULATOR_ERROR_FAIL
- REGULATOR_ERROR_OVER_CURRENT
- REGULATOR_ERROR_OVER_TEMP
- REGULATOR_ERROR_REGULATION_OUT
- REGULATOR_ERROR_UNDER_VOLTAGE
- REGULATOR_EVENT_ABORT_DISABLE
- REGULATOR_EVENT_ABORT_VOLTAGE_CHANGE
- REGULATOR_EVENT_DISABLE
- REGULATOR_EVENT_ENABLE
- REGULATOR_EVENT_FAIL
- REGULATOR_EVENT_FORCE_DISABLE
- REGULATOR_EVENT_OVER_CURRENT
- REGULATOR_EVENT_OVER_TEMP
- REGULATOR_EVENT_PRE_DISABLE
- REGULATOR_EVENT_PRE_VOLTAGE_CHANGE
- REGULATOR_EVENT_REGULATION_OUT
- REGULATOR_EVENT_UNDER_VOLTAGE
- REGULATOR_EVENT_VOLTAGE_CHANGE
- REGULATOR_INIT
- REGULATOR_IRQ_MASK
- REGULATOR_LDO
- REGULATOR_LINEAR_RANGE
- REGULATOR_MAX1586
- REGULATOR_MAX8952
- REGULATOR_MODE
- REGULATOR_MODE_FAST
- REGULATOR_MODE_IDLE
- REGULATOR_MODE_INVALID
- REGULATOR_MODE_NORMAL
- REGULATOR_MODE_STANDBY
- REGULATOR_SLAVE
- REGULATOR_STATES_NUM
- REGULATOR_STATUS_BYPASS
- REGULATOR_STATUS_ERROR
- REGULATOR_STATUS_FAST
- REGULATOR_STATUS_IDLE
- REGULATOR_STATUS_NORMAL
- REGULATOR_STATUS_OFF
- REGULATOR_STATUS_ON
- REGULATOR_STATUS_STANDBY
- REGULATOR_STATUS_UNDEFINED
- REGULATOR_SUPPLY
- REGULATOR_TPS6507X
- REGULATOR_VOLTAGE
- REGWRBLEN_BMSK
- REGWRBLEN_SHFT
- REGWRITE_BUFFER_FLUSH
- REG_
- REG_0
- REG_000
- REG_001
- REG_002
- REG_003
- REG_03
- REG_04
- REG_07
- REG_09
- REG_0A
- REG_0B
- REG_0C
- REG_1
- REG_10
- REG_11
- REG_12
- REG_13
- REG_14
- REG_15
- REG_15b0
- REG_16b1
- REG_16b3
- REG_1F_SYMBOLRATE_BYTE0
- REG_1_1_EN
- REG_1_1_RDY
- REG_1_8_EN
- REG_1_8_RDY
- REG_2
- REG_20_SYMBOLRATE_BYTE1
- REG_21
- REG_21_SYMBOLRATE_BYTE2
- REG_22
- REG_23
- REG_24
- REG_25
- REG_26
- REG_27
- REG_2E
- REG_3
- REG_32
- REG_32BIT
- REG_32BIT_POS
- REG_32K_CTRL
- REG_33
- REG_34
- REG_35
- REG_37
- REG_38
- REG_39
- REG_3WIRE
- REG_3WIRE2
- REG_4
- REG_40
- REG_42
- REG_43
- REG_44
- REG_45
- REG_4E
- REG_50080
- REG_50080_TO_PIPE
- REG_50080_TO_PLANE
- REG_6
- REG_600
- REG_64BIT
- REG_64BIT_32BIT
- REG_7
- REG_7D
- REG_7E
- REG_8
- REG_8192E_LDOV12_CTRL
- REG_84
- REG_9
- REG_9346CR
- REG_9346CR_8723B
- REG_A
- REG_A2
- REG_A2XX_A220_GRAS_CONTROL
- REG_A2XX_A220_RB_LRZ_VSC_CONTROL
- REG_A2XX_A220_VSC_BIN_SIZE
- REG_A2XX_A225_GRAS_UCP0X
- REG_A2XX_A225_GRAS_UCP5W
- REG_A2XX_A225_GRAS_UCP_ENABLED
- REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX
- REG_A2XX_A225_RB_COLOR_INFO3
- REG_A2XX_CLEAR_COLOR
- REG_A2XX_COHER_BASE_PM4
- REG_A2XX_COHER_DEST_BASE_0
- REG_A2XX_COHER_SIZE_PM4
- REG_A2XX_COHER_STATUS_PM4
- REG_A2XX_CP_PERFCOUNTER_HI
- REG_A2XX_CP_PERFCOUNTER_LO
- REG_A2XX_CP_PERFCOUNTER_SELECT
- REG_A2XX_CP_PERFMON_CNTL
- REG_A2XX_CP_PFP_UCODE_ADDR
- REG_A2XX_CP_PFP_UCODE_DATA
- REG_A2XX_CP_REG_TEST_0
- REG_A2XX_CP_SET_MARKER_0
- REG_A2XX_CP_SET_PSEUDO_REG_
- REG_A2XX_CP_SET_PSEUDO_REG__0
- REG_A2XX_CP_SET_PSEUDO_REG__1
- REG_A2XX_CP_SET_PSEUDO_REG__2
- REG_A2XX_GRAS_DEBUG_CNTL
- REG_A2XX_GRAS_DEBUG_DATA
- REG_A2XX_MASTER_INT_SIGNAL
- REG_A2XX_MH_ARBITER_CONFIG
- REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1
- REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG2
- REG_A2XX_MH_INTERRUPT_CLEAR
- REG_A2XX_MH_INTERRUPT_MASK
- REG_A2XX_MH_INTERRUPT_STATUS
- REG_A2XX_MH_MMU_CONFIG
- REG_A2XX_MH_MMU_INVALIDATE
- REG_A2XX_MH_MMU_MPU_BASE
- REG_A2XX_MH_MMU_MPU_END
- REG_A2XX_MH_MMU_PAGE_FAULT
- REG_A2XX_MH_MMU_PT_BASE
- REG_A2XX_MH_MMU_TRAN_ERROR
- REG_A2XX_MH_MMU_VA_RANGE
- REG_A2XX_NQWAIT_UNTIL
- REG_A2XX_PA_CL_CLIP_CNTL
- REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ
- REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ
- REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ
- REG_A2XX_PA_CL_GB_VERT_DISC_ADJ
- REG_A2XX_PA_CL_VPORT_XOFFSET
- REG_A2XX_PA_CL_VPORT_XSCALE
- REG_A2XX_PA_CL_VPORT_YOFFSET
- REG_A2XX_PA_CL_VPORT_YSCALE
- REG_A2XX_PA_CL_VPORT_ZOFFSET
- REG_A2XX_PA_CL_VPORT_ZSCALE
- REG_A2XX_PA_CL_VTE_CNTL
- REG_A2XX_PA_SC_AA_CONFIG
- REG_A2XX_PA_SC_AA_MASK
- REG_A2XX_PA_SC_LINE_CNTL
- REG_A2XX_PA_SC_LINE_STIPPLE
- REG_A2XX_PA_SC_SCREEN_SCISSOR_BR
- REG_A2XX_PA_SC_SCREEN_SCISSOR_TL
- REG_A2XX_PA_SC_VIZ_QUERY
- REG_A2XX_PA_SC_VIZ_QUERY_STATUS
- REG_A2XX_PA_SC_WINDOW_OFFSET
- REG_A2XX_PA_SC_WINDOW_SCISSOR_BR
- REG_A2XX_PA_SC_WINDOW_SCISSOR_TL
- REG_A2XX_PA_SU_DEBUG_CNTL
- REG_A2XX_PA_SU_DEBUG_DATA
- REG_A2XX_PA_SU_FACE_DATA
- REG_A2XX_PA_SU_LINE_CNTL
- REG_A2XX_PA_SU_POINT_MINMAX
- REG_A2XX_PA_SU_POINT_SIZE
- REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET
- REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE
- REG_A2XX_PA_SU_SC_MODE_CNTL
- REG_A2XX_PA_SU_VTX_CNTL
- REG_A2XX_PC_DEBUG_CNTL
- REG_A2XX_PC_DEBUG_DATA
- REG_A2XX_RBBM_CNTL
- REG_A2XX_RBBM_DEBUG
- REG_A2XX_RBBM_DEBUG_CNTL
- REG_A2XX_RBBM_DEBUG_OUT
- REG_A2XX_RBBM_INT_ACK
- REG_A2XX_RBBM_INT_CNTL
- REG_A2XX_RBBM_INT_STATUS
- REG_A2XX_RBBM_PATCH_RELEASE
- REG_A2XX_RBBM_PERFCOUNTER1_HI
- REG_A2XX_RBBM_PERFCOUNTER1_LO
- REG_A2XX_RBBM_PERFCOUNTER1_SELECT
- REG_A2XX_RBBM_PERIPHID1
- REG_A2XX_RBBM_PERIPHID2
- REG_A2XX_RBBM_PM_OVERRIDE1
- REG_A2XX_RBBM_PM_OVERRIDE2
- REG_A2XX_RBBM_READ_ERROR
- REG_A2XX_RBBM_SOFT_RESET
- REG_A2XX_RBBM_STATUS
- REG_A2XX_RB_ALPHA_REF
- REG_A2XX_RB_BC_CONTROL
- REG_A2XX_RB_BLEND_ALPHA
- REG_A2XX_RB_BLEND_BLUE
- REG_A2XX_RB_BLEND_CONTROL
- REG_A2XX_RB_BLEND_GREEN
- REG_A2XX_RB_BLEND_RED
- REG_A2XX_RB_COLORCONTROL
- REG_A2XX_RB_COLOR_DEST_MASK
- REG_A2XX_RB_COLOR_INFO
- REG_A2XX_RB_COLOR_MASK
- REG_A2XX_RB_COPY_CONTROL
- REG_A2XX_RB_COPY_DEST_BASE
- REG_A2XX_RB_COPY_DEST_INFO
- REG_A2XX_RB_COPY_DEST_OFFSET
- REG_A2XX_RB_COPY_DEST_PITCH
- REG_A2XX_RB_DEBUG_CNTL
- REG_A2XX_RB_DEBUG_DATA
- REG_A2XX_RB_DEPTHCONTROL
- REG_A2XX_RB_DEPTH_CLEAR
- REG_A2XX_RB_DEPTH_INFO
- REG_A2XX_RB_EDRAM_INFO
- REG_A2XX_RB_FOG_COLOR
- REG_A2XX_RB_MODECONTROL
- REG_A2XX_RB_SAMPLE_COUNT_CTL
- REG_A2XX_RB_SAMPLE_POS
- REG_A2XX_RB_STENCILREFMASK
- REG_A2XX_RB_STENCILREFMASK_BF
- REG_A2XX_RB_SURFACE_INFO
- REG_A2XX_SQ_CF_BOOLEANS
- REG_A2XX_SQ_CF_LOOP
- REG_A2XX_SQ_CONSTANT_0
- REG_A2XX_SQ_CONTEXT_MISC
- REG_A2XX_SQ_DEBUG_CONST_MGR_FSM
- REG_A2XX_SQ_DEBUG_EXP_ALLOC
- REG_A2XX_SQ_DEBUG_FSM_ALU_0
- REG_A2XX_SQ_DEBUG_FSM_ALU_1
- REG_A2XX_SQ_DEBUG_GPR_PIX
- REG_A2XX_SQ_DEBUG_GPR_VTX
- REG_A2XX_SQ_DEBUG_INPUT_FSM
- REG_A2XX_SQ_DEBUG_MISC
- REG_A2XX_SQ_DEBUG_MISC_0
- REG_A2XX_SQ_DEBUG_MISC_1
- REG_A2XX_SQ_DEBUG_PIX_TB_0
- REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM
- REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0
- REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1
- REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2
- REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3
- REG_A2XX_SQ_DEBUG_PTR_BUFF
- REG_A2XX_SQ_DEBUG_TB_STATUS_SEL
- REG_A2XX_SQ_DEBUG_TP_FSM
- REG_A2XX_SQ_DEBUG_VTX_TB_0
- REG_A2XX_SQ_DEBUG_VTX_TB_1
- REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM
- REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG
- REG_A2XX_SQ_FETCH_0
- REG_A2XX_SQ_FLOW_CONTROL
- REG_A2XX_SQ_GPR_MANAGEMENT
- REG_A2XX_SQ_INST_STORE_MANAGMENT
- REG_A2XX_SQ_INTERPOLATOR_CNTL
- REG_A2XX_SQ_INT_ACK
- REG_A2XX_SQ_INT_CNTL
- REG_A2XX_SQ_INT_STATUS
- REG_A2XX_SQ_PROGRAM_CNTL
- REG_A2XX_SQ_PS_CONST
- REG_A2XX_SQ_PS_PROGRAM
- REG_A2XX_SQ_TEX_0
- REG_A2XX_SQ_TEX_1
- REG_A2XX_SQ_TEX_2
- REG_A2XX_SQ_TEX_3
- REG_A2XX_SQ_TEX_4
- REG_A2XX_SQ_TEX_5
- REG_A2XX_SQ_VS_CONST
- REG_A2XX_SQ_VS_PROGRAM
- REG_A2XX_SQ_WRAPPING_0
- REG_A2XX_SQ_WRAPPING_1
- REG_A2XX_TC_CNTL_STATUS
- REG_A2XX_TP0_CHICKEN
- REG_A2XX_UNKNOWN_2010
- REG_A2XX_VGT_CURRENT_BIN_ID_MAX
- REG_A2XX_VGT_CURRENT_BIN_ID_MIN
- REG_A2XX_VGT_DRAW_INITIATOR
- REG_A2XX_VGT_ENHANCE
- REG_A2XX_VGT_EVENT_INITIATOR
- REG_A2XX_VGT_IMMED_DATA
- REG_A2XX_VGT_INDX_OFFSET
- REG_A2XX_VGT_MAX_VTX_INDX
- REG_A2XX_VGT_MIN_VTX_INDX
- REG_A2XX_VGT_OUT_DEALLOC_CNTL
- REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL
- REG_A2XX_VSC_PIPE
- REG_A2XX_VSC_PIPE_CONFIG
- REG_A2XX_VSC_PIPE_DATA_ADDRESS
- REG_A2XX_VSC_PIPE_DATA_LENGTH
- REG_A3XX_CP_AHB_FAULT
- REG_A3XX_CP_HW_FAULT
- REG_A3XX_CP_MEQ_ADDR
- REG_A3XX_CP_MEQ_DATA
- REG_A3XX_CP_MERCIU_ADDR
- REG_A3XX_CP_MERCIU_DATA
- REG_A3XX_CP_MERCIU_DATA2
- REG_A3XX_CP_PERFCOUNTER_SELECT
- REG_A3XX_CP_PFP_UCODE_ADDR
- REG_A3XX_CP_PFP_UCODE_DATA
- REG_A3XX_CP_PROTECT
- REG_A3XX_CP_PROTECT_CTRL
- REG_A3XX_CP_PROTECT_REG
- REG_A3XX_CP_PROTECT_STATUS
- REG_A3XX_CP_ROQ_ADDR
- REG_A3XX_CP_ROQ_DATA
- REG_A3XX_CP_WFI_PEND_CTR
- REG_A3XX_GRAS_CL_CLIP_CNTL
- REG_A3XX_GRAS_CL_GB_CLIP_ADJ
- REG_A3XX_GRAS_CL_USER_PLANE
- REG_A3XX_GRAS_CL_USER_PLANE_W
- REG_A3XX_GRAS_CL_USER_PLANE_X
- REG_A3XX_GRAS_CL_USER_PLANE_Y
- REG_A3XX_GRAS_CL_USER_PLANE_Z
- REG_A3XX_GRAS_CL_VPORT_XOFFSET
- REG_A3XX_GRAS_CL_VPORT_XSCALE
- REG_A3XX_GRAS_CL_VPORT_YOFFSET
- REG_A3XX_GRAS_CL_VPORT_YSCALE
- REG_A3XX_GRAS_CL_VPORT_ZOFFSET
- REG_A3XX_GRAS_CL_VPORT_ZSCALE
- REG_A3XX_GRAS_PERFCOUNTER0_SELECT
- REG_A3XX_GRAS_PERFCOUNTER1_SELECT
- REG_A3XX_GRAS_PERFCOUNTER2_SELECT
- REG_A3XX_GRAS_PERFCOUNTER3_SELECT
- REG_A3XX_GRAS_SC_CONTROL
- REG_A3XX_GRAS_SC_SCREEN_SCISSOR_BR
- REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL
- REG_A3XX_GRAS_SC_WINDOW_SCISSOR_BR
- REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL
- REG_A3XX_GRAS_SU_MODE_CONTROL
- REG_A3XX_GRAS_SU_POINT_MINMAX
- REG_A3XX_GRAS_SU_POINT_SIZE
- REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET
- REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE
- REG_A3XX_GRAS_TSE_DEBUG_ECO
- REG_A3XX_HLSQ_CL_CONTROL_0_REG
- REG_A3XX_HLSQ_CL_CONTROL_1_REG
- REG_A3XX_HLSQ_CL_GLOBAL_WORK
- REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET
- REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE
- REG_A3XX_HLSQ_CL_KERNEL_CONST_REG
- REG_A3XX_HLSQ_CL_KERNEL_GROUP
- REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO
- REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG
- REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG
- REG_A3XX_HLSQ_CL_NDRANGE_0_REG
- REG_A3XX_HLSQ_CL_WG_OFFSET_REG
- REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG
- REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG
- REG_A3XX_HLSQ_CONTROL_0_REG
- REG_A3XX_HLSQ_CONTROL_1_REG
- REG_A3XX_HLSQ_CONTROL_2_REG
- REG_A3XX_HLSQ_CONTROL_3_REG
- REG_A3XX_HLSQ_FS_CONTROL_REG
- REG_A3XX_HLSQ_PERFCOUNTER0_SELECT
- REG_A3XX_HLSQ_PERFCOUNTER1_SELECT
- REG_A3XX_HLSQ_PERFCOUNTER2_SELECT
- REG_A3XX_HLSQ_PERFCOUNTER3_SELECT
- REG_A3XX_HLSQ_PERFCOUNTER4_SELECT
- REG_A3XX_HLSQ_PERFCOUNTER5_SELECT
- REG_A3XX_HLSQ_VS_CONTROL_REG
- REG_A3XX_PA_SC_AA_CONFIG
- REG_A3XX_PC_PERFCOUNTER0_SELECT
- REG_A3XX_PC_PERFCOUNTER1_SELECT
- REG_A3XX_PC_PERFCOUNTER2_SELECT
- REG_A3XX_PC_PERFCOUNTER3_SELECT
- REG_A3XX_PC_PRIM_VTX_CNTL
- REG_A3XX_PC_RESTART_INDEX
- REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL
- REG_A3XX_PC_VSTREAM_CONTROL
- REG_A3XX_RBBM_AHB_CMD
- REG_A3XX_RBBM_AHB_CTL0
- REG_A3XX_RBBM_AHB_CTL1
- REG_A3XX_RBBM_AHB_ERROR_STATUS
- REG_A3XX_RBBM_CLOCK_CTL
- REG_A3XX_RBBM_DEBUG_BUS_CTL
- REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS
- REG_A3XX_RBBM_GPR0_CTL
- REG_A3XX_RBBM_GPU_BUSY_MASKED
- REG_A3XX_RBBM_HW_CONFIGURATION
- REG_A3XX_RBBM_HW_RELEASE
- REG_A3XX_RBBM_HW_VERSION
- REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL
- REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL0
- REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL1
- REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL2
- REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3
- REG_A3XX_RBBM_INT_0_MASK
- REG_A3XX_RBBM_INT_0_STATUS
- REG_A3XX_RBBM_INT_CLEAR_CMD
- REG_A3XX_RBBM_INT_SET_CMD
- REG_A3XX_RBBM_NQWAIT_UNTIL
- REG_A3XX_RBBM_PERFCOUNTER0_SELECT
- REG_A3XX_RBBM_PERFCOUNTER1_SELECT
- REG_A3XX_RBBM_PERFCTR_CP_0_HI
- REG_A3XX_RBBM_PERFCTR_CP_0_LO
- REG_A3XX_RBBM_PERFCTR_CTL
- REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI
- REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO
- REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI
- REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO
- REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI
- REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO
- REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI
- REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO
- REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI
- REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO
- REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI
- REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO
- REG_A3XX_RBBM_PERFCTR_LOAD_CMD0
- REG_A3XX_RBBM_PERFCTR_LOAD_CMD1
- REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI
- REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO
- REG_A3XX_RBBM_PERFCTR_PC_0_HI
- REG_A3XX_RBBM_PERFCTR_PC_0_LO
- REG_A3XX_RBBM_PERFCTR_PC_1_HI
- REG_A3XX_RBBM_PERFCTR_PC_1_LO
- REG_A3XX_RBBM_PERFCTR_PC_2_HI
- REG_A3XX_RBBM_PERFCTR_PC_2_LO
- REG_A3XX_RBBM_PERFCTR_PC_3_HI
- REG_A3XX_RBBM_PERFCTR_PC_3_LO
- REG_A3XX_RBBM_PERFCTR_PWR_0_HI
- REG_A3XX_RBBM_PERFCTR_PWR_0_LO
- REG_A3XX_RBBM_PERFCTR_PWR_1_HI
- REG_A3XX_RBBM_PERFCTR_PWR_1_LO
- REG_A3XX_RBBM_PERFCTR_RAS_0_HI
- REG_A3XX_RBBM_PERFCTR_RAS_0_LO
- REG_A3XX_RBBM_PERFCTR_RAS_1_HI
- REG_A3XX_RBBM_PERFCTR_RAS_1_LO
- REG_A3XX_RBBM_PERFCTR_RBBM_0_HI
- REG_A3XX_RBBM_PERFCTR_RBBM_0_LO
- REG_A3XX_RBBM_PERFCTR_RBBM_1_HI
- REG_A3XX_RBBM_PERFCTR_RBBM_1_LO
- REG_A3XX_RBBM_PERFCTR_RB_0_HI
- REG_A3XX_RBBM_PERFCTR_RB_0_LO
- REG_A3XX_RBBM_PERFCTR_RB_1_HI
- REG_A3XX_RBBM_PERFCTR_RB_1_LO
- REG_A3XX_RBBM_PERFCTR_SP_0_HI
- REG_A3XX_RBBM_PERFCTR_SP_0_LO
- REG_A3XX_RBBM_PERFCTR_SP_1_HI
- REG_A3XX_RBBM_PERFCTR_SP_1_LO
- REG_A3XX_RBBM_PERFCTR_SP_2_HI
- REG_A3XX_RBBM_PERFCTR_SP_2_LO
- REG_A3XX_RBBM_PERFCTR_SP_3_HI
- REG_A3XX_RBBM_PERFCTR_SP_3_LO
- REG_A3XX_RBBM_PERFCTR_SP_4_HI
- REG_A3XX_RBBM_PERFCTR_SP_4_LO
- REG_A3XX_RBBM_PERFCTR_SP_5_HI
- REG_A3XX_RBBM_PERFCTR_SP_5_LO
- REG_A3XX_RBBM_PERFCTR_SP_6_HI
- REG_A3XX_RBBM_PERFCTR_SP_6_LO
- REG_A3XX_RBBM_PERFCTR_SP_7_HI
- REG_A3XX_RBBM_PERFCTR_SP_7_LO
- REG_A3XX_RBBM_PERFCTR_TP_0_HI
- REG_A3XX_RBBM_PERFCTR_TP_0_LO
- REG_A3XX_RBBM_PERFCTR_TP_1_HI
- REG_A3XX_RBBM_PERFCTR_TP_1_LO
- REG_A3XX_RBBM_PERFCTR_TP_2_HI
- REG_A3XX_RBBM_PERFCTR_TP_2_LO
- REG_A3XX_RBBM_PERFCTR_TP_3_HI
- REG_A3XX_RBBM_PERFCTR_TP_3_LO
- REG_A3XX_RBBM_PERFCTR_TP_4_HI
- REG_A3XX_RBBM_PERFCTR_TP_4_LO
- REG_A3XX_RBBM_PERFCTR_TP_5_HI
- REG_A3XX_RBBM_PERFCTR_TP_5_LO
- REG_A3XX_RBBM_PERFCTR_TSE_0_HI
- REG_A3XX_RBBM_PERFCTR_TSE_0_LO
- REG_A3XX_RBBM_PERFCTR_TSE_1_HI
- REG_A3XX_RBBM_PERFCTR_TSE_1_LO
- REG_A3XX_RBBM_PERFCTR_UCHE_0_HI
- REG_A3XX_RBBM_PERFCTR_UCHE_0_LO
- REG_A3XX_RBBM_PERFCTR_UCHE_1_HI
- REG_A3XX_RBBM_PERFCTR_UCHE_1_LO
- REG_A3XX_RBBM_PERFCTR_UCHE_2_HI
- REG_A3XX_RBBM_PERFCTR_UCHE_2_LO
- REG_A3XX_RBBM_PERFCTR_UCHE_3_HI
- REG_A3XX_RBBM_PERFCTR_UCHE_3_LO
- REG_A3XX_RBBM_PERFCTR_UCHE_4_HI
- REG_A3XX_RBBM_PERFCTR_UCHE_4_LO
- REG_A3XX_RBBM_PERFCTR_UCHE_5_HI
- REG_A3XX_RBBM_PERFCTR_UCHE_5_LO
- REG_A3XX_RBBM_PERFCTR_VFD_0_HI
- REG_A3XX_RBBM_PERFCTR_VFD_0_LO
- REG_A3XX_RBBM_PERFCTR_VFD_1_HI
- REG_A3XX_RBBM_PERFCTR_VFD_1_LO
- REG_A3XX_RBBM_PERFCTR_VPC_0_HI
- REG_A3XX_RBBM_PERFCTR_VPC_0_LO
- REG_A3XX_RBBM_PERFCTR_VPC_1_HI
- REG_A3XX_RBBM_PERFCTR_VPC_1_LO
- REG_A3XX_RBBM_PM_OVERRIDE2
- REG_A3XX_RBBM_RBBM_CTL
- REG_A3XX_RBBM_SP_HYST_CNT
- REG_A3XX_RBBM_STATUS
- REG_A3XX_RBBM_SW_RESET_CMD
- REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL
- REG_A3XX_RB_ALPHA_REF
- REG_A3XX_RB_BLEND_ALPHA
- REG_A3XX_RB_BLEND_BLUE
- REG_A3XX_RB_BLEND_GREEN
- REG_A3XX_RB_BLEND_RED
- REG_A3XX_RB_CLEAR_COLOR_DW0
- REG_A3XX_RB_CLEAR_COLOR_DW1
- REG_A3XX_RB_CLEAR_COLOR_DW2
- REG_A3XX_RB_CLEAR_COLOR_DW3
- REG_A3XX_RB_COPY_CONTROL
- REG_A3XX_RB_COPY_DEST_BASE
- REG_A3XX_RB_COPY_DEST_INFO
- REG_A3XX_RB_COPY_DEST_PITCH
- REG_A3XX_RB_DEBUG_ECO_CONTROLS_ADDR
- REG_A3XX_RB_DEPTH_CLEAR
- REG_A3XX_RB_DEPTH_CONTROL
- REG_A3XX_RB_DEPTH_INFO
- REG_A3XX_RB_DEPTH_PITCH
- REG_A3XX_RB_FRAME_BUFFER_DIMENSION
- REG_A3XX_RB_GMEM_BASE_ADDR
- REG_A3XX_RB_LRZ_VSC_CONTROL
- REG_A3XX_RB_MODE_CONTROL
- REG_A3XX_RB_MRT
- REG_A3XX_RB_MRT_BLEND_CONTROL
- REG_A3XX_RB_MRT_BUF_BASE
- REG_A3XX_RB_MRT_BUF_INFO
- REG_A3XX_RB_MRT_CONTROL
- REG_A3XX_RB_MSAA_CONTROL
- REG_A3XX_RB_PERFCOUNTER0_SELECT
- REG_A3XX_RB_PERFCOUNTER1_SELECT
- REG_A3XX_RB_RENDER_CONTROL
- REG_A3XX_RB_SAMPLE_COUNT_ADDR
- REG_A3XX_RB_SAMPLE_COUNT_CONTROL
- REG_A3XX_RB_STENCILREFMASK
- REG_A3XX_RB_STENCILREFMASK_BF
- REG_A3XX_RB_STENCIL_CLEAR
- REG_A3XX_RB_STENCIL_CONTROL
- REG_A3XX_RB_STENCIL_INFO
- REG_A3XX_RB_STENCIL_PITCH
- REG_A3XX_RB_WINDOW_OFFSET
- REG_A3XX_RB_Z_CLAMP_MAX
- REG_A3XX_RB_Z_CLAMP_MIN
- REG_A3XX_SP_FS_CTRL_REG0
- REG_A3XX_SP_FS_CTRL_REG1
- REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0
- REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1
- REG_A3XX_SP_FS_IMAGE_OUTPUT
- REG_A3XX_SP_FS_IMAGE_OUTPUT_REG
- REG_A3XX_SP_FS_LENGTH_REG
- REG_A3XX_SP_FS_MRT
- REG_A3XX_SP_FS_MRT_REG
- REG_A3XX_SP_FS_OBJ_OFFSET_REG
- REG_A3XX_SP_FS_OBJ_START_REG
- REG_A3XX_SP_FS_OUTPUT_REG
- REG_A3XX_SP_FS_PVT_MEM_ADDR_REG
- REG_A3XX_SP_FS_PVT_MEM_PARAM_REG
- REG_A3XX_SP_FS_PVT_MEM_SIZE_REG
- REG_A3XX_SP_GLOBAL_MEM_ADDR
- REG_A3XX_SP_GLOBAL_MEM_SIZE
- REG_A3XX_SP_PERFCOUNTER0_SELECT
- REG_A3XX_SP_PERFCOUNTER1_SELECT
- REG_A3XX_SP_PERFCOUNTER2_SELECT
- REG_A3XX_SP_PERFCOUNTER3_SELECT
- REG_A3XX_SP_PERFCOUNTER4_SELECT
- REG_A3XX_SP_PERFCOUNTER5_SELECT
- REG_A3XX_SP_PERFCOUNTER6_SELECT
- REG_A3XX_SP_PERFCOUNTER7_SELECT
- REG_A3XX_SP_SP_CTRL_REG
- REG_A3XX_SP_VS_CTRL_REG0
- REG_A3XX_SP_VS_CTRL_REG1
- REG_A3XX_SP_VS_LENGTH_REG
- REG_A3XX_SP_VS_OBJ_OFFSET_REG
- REG_A3XX_SP_VS_OBJ_START_REG
- REG_A3XX_SP_VS_OUT
- REG_A3XX_SP_VS_OUT_REG
- REG_A3XX_SP_VS_PARAM_REG
- REG_A3XX_SP_VS_PVT_MEM_ADDR_REG
- REG_A3XX_SP_VS_PVT_MEM_PARAM_REG
- REG_A3XX_SP_VS_PVT_MEM_SIZE_REG
- REG_A3XX_SP_VS_VPC_DST
- REG_A3XX_SP_VS_VPC_DST_REG
- REG_A3XX_SQ_GPR_MANAGEMENT
- REG_A3XX_SQ_INST_STORE_MANAGMENT
- REG_A3XX_TEX_CONST_0
- REG_A3XX_TEX_CONST_1
- REG_A3XX_TEX_CONST_2
- REG_A3XX_TEX_CONST_3
- REG_A3XX_TEX_SAMP_0
- REG_A3XX_TEX_SAMP_1
- REG_A3XX_TP0_CHICKEN
- REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR
- REG_A3XX_TPL1_TP_FS_TEX_OFFSET
- REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR
- REG_A3XX_TPL1_TP_VS_TEX_OFFSET
- REG_A3XX_TP_PERFCOUNTER0_SELECT
- REG_A3XX_TP_PERFCOUNTER1_SELECT
- REG_A3XX_TP_PERFCOUNTER2_SELECT
- REG_A3XX_TP_PERFCOUNTER3_SELECT
- REG_A3XX_TP_PERFCOUNTER4_SELECT
- REG_A3XX_TP_PERFCOUNTER5_SELECT
- REG_A3XX_UCHE_CACHE_INVALIDATE0_REG
- REG_A3XX_UCHE_CACHE_INVALIDATE1_REG
- REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG
- REG_A3XX_UCHE_PERFCOUNTER0_SELECT
- REG_A3XX_UCHE_PERFCOUNTER1_SELECT
- REG_A3XX_UCHE_PERFCOUNTER2_SELECT
- REG_A3XX_UCHE_PERFCOUNTER3_SELECT
- REG_A3XX_UCHE_PERFCOUNTER4_SELECT
- REG_A3XX_UCHE_PERFCOUNTER5_SELECT
- REG_A3XX_UNKNOWN_0C3D
- REG_A3XX_UNKNOWN_0E43
- REG_A3XX_UNKNOWN_0EA6
- REG_A3XX_UNKNOWN_0EE0
- REG_A3XX_UNKNOWN_0F03
- REG_A3XX_VBIF_ABIT_SORT
- REG_A3XX_VBIF_ABIT_SORT_CONF
- REG_A3XX_VBIF_ARB_CTL
- REG_A3XX_VBIF_CLKON
- REG_A3XX_VBIF_DDR_OUT_MAX_BURST
- REG_A3XX_VBIF_FIXED_SORT_EN
- REG_A3XX_VBIF_FIXED_SORT_SEL0
- REG_A3XX_VBIF_FIXED_SORT_SEL1
- REG_A3XX_VBIF_GATE_OFF_WRREQ_EN
- REG_A3XX_VBIF_IN_RD_LIM_CONF0
- REG_A3XX_VBIF_IN_RD_LIM_CONF1
- REG_A3XX_VBIF_IN_WR_LIM_CONF0
- REG_A3XX_VBIF_IN_WR_LIM_CONF1
- REG_A3XX_VBIF_OUT_AXI_AMEMTYPE_CONF0
- REG_A3XX_VBIF_OUT_AXI_AOOO
- REG_A3XX_VBIF_OUT_AXI_AOOO_EN
- REG_A3XX_VBIF_OUT_RD_LIM_CONF0
- REG_A3XX_VBIF_OUT_WR_LIM_CONF0
- REG_A3XX_VBIF_PERF_CNT0_HI
- REG_A3XX_VBIF_PERF_CNT0_LO
- REG_A3XX_VBIF_PERF_CNT1_HI
- REG_A3XX_VBIF_PERF_CNT1_LO
- REG_A3XX_VBIF_PERF_CNT_CLR
- REG_A3XX_VBIF_PERF_CNT_EN
- REG_A3XX_VBIF_PERF_CNT_SEL
- REG_A3XX_VBIF_PERF_PWR_CNT0_HI
- REG_A3XX_VBIF_PERF_PWR_CNT0_LO
- REG_A3XX_VBIF_PERF_PWR_CNT1_HI
- REG_A3XX_VBIF_PERF_PWR_CNT1_LO
- REG_A3XX_VBIF_PERF_PWR_CNT2_HI
- REG_A3XX_VBIF_PERF_PWR_CNT2_LO
- REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB
- REG_A3XX_VFD_CONTROL_0
- REG_A3XX_VFD_CONTROL_1
- REG_A3XX_VFD_DECODE
- REG_A3XX_VFD_DECODE_INSTR
- REG_A3XX_VFD_FETCH
- REG_A3XX_VFD_FETCH_INSTR_0
- REG_A3XX_VFD_FETCH_INSTR_1
- REG_A3XX_VFD_INDEX_MAX
- REG_A3XX_VFD_INDEX_MIN
- REG_A3XX_VFD_INDEX_OFFSET
- REG_A3XX_VFD_INSTANCEID_OFFSET
- REG_A3XX_VFD_PERFCOUNTER0_SELECT
- REG_A3XX_VFD_PERFCOUNTER1_SELECT
- REG_A3XX_VFD_VS_THREADING_THRESHOLD
- REG_A3XX_VGT_BIN_BASE
- REG_A3XX_VGT_BIN_SIZE
- REG_A3XX_VGT_CL_INITIATOR
- REG_A3XX_VGT_DRAW_INITIATOR
- REG_A3XX_VGT_EVENT_INITIATOR
- REG_A3XX_VGT_IMMED_DATA
- REG_A3XX_VPC_ATTR
- REG_A3XX_VPC_PACK
- REG_A3XX_VPC_PERFCOUNTER0_SELECT
- REG_A3XX_VPC_PERFCOUNTER1_SELECT
- REG_A3XX_VPC_VARYING_INTERP
- REG_A3XX_VPC_VARYING_INTERP_MODE
- REG_A3XX_VPC_VARYING_PS_REPL
- REG_A3XX_VPC_VARYING_PS_REPL_MODE
- REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0
- REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_1
- REG_A3XX_VPC_VPC_DEBUG_RAM_READ
- REG_A3XX_VPC_VPC_DEBUG_RAM_SEL
- REG_A3XX_VSC_BIN_CONTROL
- REG_A3XX_VSC_BIN_SIZE
- REG_A3XX_VSC_PIPE
- REG_A3XX_VSC_PIPE_CONFIG
- REG_A3XX_VSC_PIPE_DATA_ADDRESS
- REG_A3XX_VSC_PIPE_DATA_LENGTH
- REG_A3XX_VSC_SIZE_ADDRESS
- REG_A4XX_CP_CNTL
- REG_A4XX_CP_DEBUG
- REG_A4XX_CP_DEBUG_ECO_CONTROL
- REG_A4XX_CP_DRAW_INDIRECT_0
- REG_A4XX_CP_DRAW_INDIRECT_1
- REG_A4XX_CP_DRAW_INDX_INDIRECT_0
- REG_A4XX_CP_DRAW_INDX_INDIRECT_1
- REG_A4XX_CP_DRAW_INDX_INDIRECT_2
- REG_A4XX_CP_DRAW_INDX_INDIRECT_3
- REG_A4XX_CP_DRAW_STATE_ADDR
- REG_A4XX_CP_EVENTS_IN_FLIGHT
- REG_A4XX_CP_EXEC_CS_INDIRECT_0
- REG_A4XX_CP_EXEC_CS_INDIRECT_1
- REG_A4XX_CP_EXEC_CS_INDIRECT_2
- REG_A4XX_CP_HW_FAULT
- REG_A4XX_CP_IB1_BASE
- REG_A4XX_CP_IB1_BUFSZ
- REG_A4XX_CP_IB2_BASE
- REG_A4XX_CP_IB2_BUFSZ
- REG_A4XX_CP_MEQ_ADDR
- REG_A4XX_CP_MEQ_DATA
- REG_A4XX_CP_MERCIU_ADDR
- REG_A4XX_CP_MERCIU_DATA
- REG_A4XX_CP_MERCIU_DATA2
- REG_A4XX_CP_MERCIU_SIZE
- REG_A4XX_CP_MERCIU_STAT
- REG_A4XX_CP_ME_CNTL
- REG_A4XX_CP_ME_NRT_ADDR
- REG_A4XX_CP_ME_NRT_DATA
- REG_A4XX_CP_ME_RAM_DATA
- REG_A4XX_CP_ME_RAM_RADDR
- REG_A4XX_CP_ME_RAM_WADDR
- REG_A4XX_CP_ME_RB_DONE_DATA
- REG_A4XX_CP_PERFCOMBINER_SELECT
- REG_A4XX_CP_PERFCTR_CP_SEL_0
- REG_A4XX_CP_PERFCTR_CP_SEL_1
- REG_A4XX_CP_PERFCTR_CP_SEL_2
- REG_A4XX_CP_PERFCTR_CP_SEL_3
- REG_A4XX_CP_PERFCTR_CP_SEL_4
- REG_A4XX_CP_PERFCTR_CP_SEL_5
- REG_A4XX_CP_PERFCTR_CP_SEL_6
- REG_A4XX_CP_PERFCTR_CP_SEL_7
- REG_A4XX_CP_PFP_UCODE_ADDR
- REG_A4XX_CP_PFP_UCODE_DATA
- REG_A4XX_CP_PREEMPT
- REG_A4XX_CP_PROTECT
- REG_A4XX_CP_PROTECT_CTRL
- REG_A4XX_CP_PROTECT_REG
- REG_A4XX_CP_PROTECT_STATUS
- REG_A4XX_CP_QUEUE_THRESH2
- REG_A4XX_CP_RB_BASE
- REG_A4XX_CP_RB_CNTL
- REG_A4XX_CP_RB_RPTR
- REG_A4XX_CP_RB_RPTR_ADDR
- REG_A4XX_CP_RB_WPTR
- REG_A4XX_CP_ROQ_ADDR
- REG_A4XX_CP_ROQ_DATA
- REG_A4XX_CP_SCRATCH
- REG_A4XX_CP_SCRATCH_ADDR
- REG_A4XX_CP_SCRATCH_REG
- REG_A4XX_CP_SCRATCH_UMASK
- REG_A4XX_CP_STQ_AVAIL
- REG_A4XX_CP_ST_BASE
- REG_A4XX_CP_WFI_PEND_CTR
- REG_A4XX_GRAS_ALPHA_CONTROL
- REG_A4XX_GRAS_CLEAR_CNTL
- REG_A4XX_GRAS_CL_CLIP_CNTL
- REG_A4XX_GRAS_CL_GB_CLIP_ADJ
- REG_A4XX_GRAS_CL_VPORT_XOFFSET_0
- REG_A4XX_GRAS_CL_VPORT_XSCALE_0
- REG_A4XX_GRAS_CL_VPORT_YOFFSET_0
- REG_A4XX_GRAS_CL_VPORT_YSCALE_0
- REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0
- REG_A4XX_GRAS_CL_VPORT_ZSCALE_0
- REG_A4XX_GRAS_DEBUG_ECO_CONTROL
- REG_A4XX_GRAS_DEPTH_CONTROL
- REG_A4XX_GRAS_PERFCTR_RAS_SEL_0
- REG_A4XX_GRAS_PERFCTR_RAS_SEL_1
- REG_A4XX_GRAS_PERFCTR_RAS_SEL_2
- REG_A4XX_GRAS_PERFCTR_RAS_SEL_3
- REG_A4XX_GRAS_PERFCTR_TSE_SEL_0
- REG_A4XX_GRAS_PERFCTR_TSE_SEL_1
- REG_A4XX_GRAS_PERFCTR_TSE_SEL_2
- REG_A4XX_GRAS_PERFCTR_TSE_SEL_3
- REG_A4XX_GRAS_SC_CONTROL
- REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR
- REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL
- REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR
- REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL
- REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR
- REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL
- REG_A4XX_GRAS_SU_MODE_CONTROL
- REG_A4XX_GRAS_SU_POINT_MINMAX
- REG_A4XX_GRAS_SU_POINT_SIZE
- REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP
- REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET
- REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE
- REG_A4XX_GRAS_TSE_STATUS
- REG_A4XX_HLSQ_CL_CONTROL_0
- REG_A4XX_HLSQ_CL_CONTROL_1
- REG_A4XX_HLSQ_CL_KERNEL_CONST
- REG_A4XX_HLSQ_CL_KERNEL_GROUP_X
- REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y
- REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z
- REG_A4XX_HLSQ_CL_NDRANGE_0
- REG_A4XX_HLSQ_CL_NDRANGE_1
- REG_A4XX_HLSQ_CL_NDRANGE_2
- REG_A4XX_HLSQ_CL_NDRANGE_3
- REG_A4XX_HLSQ_CL_NDRANGE_4
- REG_A4XX_HLSQ_CL_NDRANGE_5
- REG_A4XX_HLSQ_CL_NDRANGE_6
- REG_A4XX_HLSQ_CL_WG_OFFSET
- REG_A4XX_HLSQ_CONTROL_0_REG
- REG_A4XX_HLSQ_CONTROL_1_REG
- REG_A4XX_HLSQ_CONTROL_2_REG
- REG_A4XX_HLSQ_CONTROL_3_REG
- REG_A4XX_HLSQ_CONTROL_4_REG
- REG_A4XX_HLSQ_CS_CONTROL_REG
- REG_A4XX_HLSQ_DEBUG_ECO_CONTROL
- REG_A4XX_HLSQ_DS_CONTROL_REG
- REG_A4XX_HLSQ_FS_CONTROL_REG
- REG_A4XX_HLSQ_GS_CONTROL_REG
- REG_A4XX_HLSQ_HS_CONTROL_REG
- REG_A4XX_HLSQ_MODE_CONTROL
- REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_0
- REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_1
- REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_2
- REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_3
- REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_4
- REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_5
- REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_6
- REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_7
- REG_A4XX_HLSQ_PERF_PIPE_MASK
- REG_A4XX_HLSQ_TIMEOUT_THRESHOLD
- REG_A4XX_HLSQ_UPDATE_CONTROL
- REG_A4XX_HLSQ_VS_CONTROL_REG
- REG_A4XX_PC_BINNING_COMMAND
- REG_A4XX_PC_BIN_BASE
- REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE
- REG_A4XX_PC_GS_PARAM
- REG_A4XX_PC_HS_PARAM
- REG_A4XX_PC_PERFCTR_PC_SEL_0
- REG_A4XX_PC_PERFCTR_PC_SEL_1
- REG_A4XX_PC_PERFCTR_PC_SEL_2
- REG_A4XX_PC_PERFCTR_PC_SEL_3
- REG_A4XX_PC_PERFCTR_PC_SEL_4
- REG_A4XX_PC_PERFCTR_PC_SEL_5
- REG_A4XX_PC_PERFCTR_PC_SEL_6
- REG_A4XX_PC_PERFCTR_PC_SEL_7
- REG_A4XX_PC_PRIM_VTX_CNTL
- REG_A4XX_PC_PRIM_VTX_CNTL2
- REG_A4XX_PC_RESTART_INDEX
- REG_A4XX_PC_TESSFACTOR_ADDR
- REG_A4XX_PC_VSTREAM_CONTROL
- REG_A4XX_RBBM_AHB_CMD
- REG_A4XX_RBBM_AHB_CTL0
- REG_A4XX_RBBM_AHB_CTL1
- REG_A4XX_RBBM_AHB_DEBUG_CTL
- REG_A4XX_RBBM_AHB_ERROR_STATUS
- REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS
- REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS
- REG_A4XX_RBBM_AHB_STATUS
- REG_A4XX_RBBM_ALWAYSON_COUNTER_HI
- REG_A4XX_RBBM_ALWAYSON_COUNTER_LO
- REG_A4XX_RBBM_BLOCK_SW_RESET_CMD
- REG_A4XX_RBBM_CFG_DEBBUS_SEL_A
- REG_A4XX_RBBM_CFG_DEBBUS_SEL_B
- REG_A4XX_RBBM_CFG_DEBBUS_SEL_C
- REG_A4XX_RBBM_CFG_DEBBUS_SEL_D
- REG_A4XX_RBBM_CLOCK_CTL
- REG_A4XX_RBBM_CLOCK_CTL2
- REG_A4XX_RBBM_CLOCK_CTL2_RB
- REG_A4XX_RBBM_CLOCK_CTL2_RB_REG
- REG_A4XX_RBBM_CLOCK_CTL2_SP
- REG_A4XX_RBBM_CLOCK_CTL2_SP_REG
- REG_A4XX_RBBM_CLOCK_CTL2_TP
- REG_A4XX_RBBM_CLOCK_CTL2_TP_REG
- REG_A4XX_RBBM_CLOCK_CTL2_UCHE
- REG_A4XX_RBBM_CLOCK_CTL3_UCHE
- REG_A4XX_RBBM_CLOCK_CTL4_UCHE
- REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM
- REG_A4XX_RBBM_CLOCK_CTL_HLSQ
- REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU
- REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG
- REG_A4XX_RBBM_CLOCK_CTL_RB
- REG_A4XX_RBBM_CLOCK_CTL_RB_REG
- REG_A4XX_RBBM_CLOCK_CTL_SP
- REG_A4XX_RBBM_CLOCK_CTL_SP_REG
- REG_A4XX_RBBM_CLOCK_CTL_TP
- REG_A4XX_RBBM_CLOCK_CTL_TP_REG
- REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM
- REG_A4XX_RBBM_CLOCK_CTL_UCHE
- REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM
- REG_A4XX_RBBM_CLOCK_DELAY_GPC
- REG_A4XX_RBBM_CLOCK_DELAY_HLSQ
- REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1
- REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG
- REG_A4XX_RBBM_CLOCK_DELAY_SP
- REG_A4XX_RBBM_CLOCK_DELAY_SP_REG
- REG_A4XX_RBBM_CLOCK_DELAY_TP
- REG_A4XX_RBBM_CLOCK_DELAY_TP_REG
- REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM
- REG_A4XX_RBBM_CLOCK_DELAY_UCHE
- REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM
- REG_A4XX_RBBM_CLOCK_HYST_GPC
- REG_A4XX_RBBM_CLOCK_HYST_HLSQ
- REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU
- REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG
- REG_A4XX_RBBM_CLOCK_HYST_SP
- REG_A4XX_RBBM_CLOCK_HYST_SP_REG
- REG_A4XX_RBBM_CLOCK_HYST_TP
- REG_A4XX_RBBM_CLOCK_HYST_TP_REG
- REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM
- REG_A4XX_RBBM_CLOCK_HYST_UCHE
- REG_A4XX_RBBM_CLOCK_MODE_GPC
- REG_A4XX_RBBM_CLOCK_STATUS
- REG_A4XX_RBBM_EXT_TRACE_BUS_CTL
- REG_A4XX_RBBM_GPU_BUSY_MASKED
- REG_A4XX_RBBM_HW_CONFIGURATION
- REG_A4XX_RBBM_HW_VERSION
- REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL
- REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4
- REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5
- REG_A4XX_RBBM_INT_0_MASK
- REG_A4XX_RBBM_INT_0_STATUS
- REG_A4XX_RBBM_INT_CLEAR_CMD
- REG_A4XX_RBBM_PERFCTR_CCU_0_HI
- REG_A4XX_RBBM_PERFCTR_CCU_0_LO
- REG_A4XX_RBBM_PERFCTR_CCU_1_HI
- REG_A4XX_RBBM_PERFCTR_CCU_1_LO
- REG_A4XX_RBBM_PERFCTR_CCU_2_HI
- REG_A4XX_RBBM_PERFCTR_CCU_2_LO
- REG_A4XX_RBBM_PERFCTR_CCU_3_HI
- REG_A4XX_RBBM_PERFCTR_CCU_3_LO
- REG_A4XX_RBBM_PERFCTR_CP_0_HI
- REG_A4XX_RBBM_PERFCTR_CP_0_LO
- REG_A4XX_RBBM_PERFCTR_CP_1_HI
- REG_A4XX_RBBM_PERFCTR_CP_1_LO
- REG_A4XX_RBBM_PERFCTR_CP_2_HI
- REG_A4XX_RBBM_PERFCTR_CP_2_LO
- REG_A4XX_RBBM_PERFCTR_CP_3_HI
- REG_A4XX_RBBM_PERFCTR_CP_3_LO
- REG_A4XX_RBBM_PERFCTR_CP_4_HI
- REG_A4XX_RBBM_PERFCTR_CP_4_LO
- REG_A4XX_RBBM_PERFCTR_CP_5_HI
- REG_A4XX_RBBM_PERFCTR_CP_5_LO
- REG_A4XX_RBBM_PERFCTR_CP_6_HI
- REG_A4XX_RBBM_PERFCTR_CP_6_LO
- REG_A4XX_RBBM_PERFCTR_CP_7_HI
- REG_A4XX_RBBM_PERFCTR_CP_7_LO
- REG_A4XX_RBBM_PERFCTR_CTL
- REG_A4XX_RBBM_PERFCTR_HLSQ_0_HI
- REG_A4XX_RBBM_PERFCTR_HLSQ_0_LO
- REG_A4XX_RBBM_PERFCTR_HLSQ_1_HI
- REG_A4XX_RBBM_PERFCTR_HLSQ_1_LO
- REG_A4XX_RBBM_PERFCTR_HLSQ_2_HI
- REG_A4XX_RBBM_PERFCTR_HLSQ_2_LO
- REG_A4XX_RBBM_PERFCTR_HLSQ_3_HI
- REG_A4XX_RBBM_PERFCTR_HLSQ_3_LO
- REG_A4XX_RBBM_PERFCTR_HLSQ_4_HI
- REG_A4XX_RBBM_PERFCTR_HLSQ_4_LO
- REG_A4XX_RBBM_PERFCTR_HLSQ_5_HI
- REG_A4XX_RBBM_PERFCTR_HLSQ_5_LO
- REG_A4XX_RBBM_PERFCTR_HLSQ_6_HI
- REG_A4XX_RBBM_PERFCTR_HLSQ_6_LO
- REG_A4XX_RBBM_PERFCTR_HLSQ_7_HI
- REG_A4XX_RBBM_PERFCTR_HLSQ_7_LO
- REG_A4XX_RBBM_PERFCTR_LOAD_CMD0
- REG_A4XX_RBBM_PERFCTR_LOAD_CMD1
- REG_A4XX_RBBM_PERFCTR_LOAD_CMD2
- REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI
- REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO
- REG_A4XX_RBBM_PERFCTR_PC_0_HI
- REG_A4XX_RBBM_PERFCTR_PC_0_LO
- REG_A4XX_RBBM_PERFCTR_PC_1_HI
- REG_A4XX_RBBM_PERFCTR_PC_1_LO
- REG_A4XX_RBBM_PERFCTR_PC_2_HI
- REG_A4XX_RBBM_PERFCTR_PC_2_LO
- REG_A4XX_RBBM_PERFCTR_PC_3_HI
- REG_A4XX_RBBM_PERFCTR_PC_3_LO
- REG_A4XX_RBBM_PERFCTR_PC_4_HI
- REG_A4XX_RBBM_PERFCTR_PC_4_LO
- REG_A4XX_RBBM_PERFCTR_PC_5_HI
- REG_A4XX_RBBM_PERFCTR_PC_5_LO
- REG_A4XX_RBBM_PERFCTR_PC_6_HI
- REG_A4XX_RBBM_PERFCTR_PC_6_LO
- REG_A4XX_RBBM_PERFCTR_PC_7_HI
- REG_A4XX_RBBM_PERFCTR_PC_7_LO
- REG_A4XX_RBBM_PERFCTR_PWR_0_HI
- REG_A4XX_RBBM_PERFCTR_PWR_0_LO
- REG_A4XX_RBBM_PERFCTR_PWR_1_HI
- REG_A4XX_RBBM_PERFCTR_PWR_1_LO
- REG_A4XX_RBBM_PERFCTR_RAS_0_HI
- REG_A4XX_RBBM_PERFCTR_RAS_0_LO
- REG_A4XX_RBBM_PERFCTR_RAS_1_HI
- REG_A4XX_RBBM_PERFCTR_RAS_1_LO
- REG_A4XX_RBBM_PERFCTR_RAS_2_HI
- REG_A4XX_RBBM_PERFCTR_RAS_2_LO
- REG_A4XX_RBBM_PERFCTR_RAS_3_HI
- REG_A4XX_RBBM_PERFCTR_RAS_3_LO
- REG_A4XX_RBBM_PERFCTR_RBBM_0_HI
- REG_A4XX_RBBM_PERFCTR_RBBM_0_LO
- REG_A4XX_RBBM_PERFCTR_RBBM_1_HI
- REG_A4XX_RBBM_PERFCTR_RBBM_1_LO
- REG_A4XX_RBBM_PERFCTR_RBBM_2_HI
- REG_A4XX_RBBM_PERFCTR_RBBM_2_LO
- REG_A4XX_RBBM_PERFCTR_RBBM_3_HI
- REG_A4XX_RBBM_PERFCTR_RBBM_3_LO
- REG_A4XX_RBBM_PERFCTR_RBBM_SEL_0
- REG_A4XX_RBBM_PERFCTR_RBBM_SEL_1
- REG_A4XX_RBBM_PERFCTR_RBBM_SEL_2
- REG_A4XX_RBBM_PERFCTR_RBBM_SEL_3
- REG_A4XX_RBBM_PERFCTR_RB_0_HI
- REG_A4XX_RBBM_PERFCTR_RB_0_LO
- REG_A4XX_RBBM_PERFCTR_RB_1_HI
- REG_A4XX_RBBM_PERFCTR_RB_1_LO
- REG_A4XX_RBBM_PERFCTR_RB_2_HI
- REG_A4XX_RBBM_PERFCTR_RB_2_LO
- REG_A4XX_RBBM_PERFCTR_RB_3_HI
- REG_A4XX_RBBM_PERFCTR_RB_3_LO
- REG_A4XX_RBBM_PERFCTR_RB_4_HI
- REG_A4XX_RBBM_PERFCTR_RB_4_LO
- REG_A4XX_RBBM_PERFCTR_RB_5_HI
- REG_A4XX_RBBM_PERFCTR_RB_5_LO
- REG_A4XX_RBBM_PERFCTR_RB_6_HI
- REG_A4XX_RBBM_PERFCTR_RB_6_LO
- REG_A4XX_RBBM_PERFCTR_RB_7_HI
- REG_A4XX_RBBM_PERFCTR_RB_7_LO
- REG_A4XX_RBBM_PERFCTR_SP_0_HI
- REG_A4XX_RBBM_PERFCTR_SP_0_LO
- REG_A4XX_RBBM_PERFCTR_SP_10_HI
- REG_A4XX_RBBM_PERFCTR_SP_10_LO
- REG_A4XX_RBBM_PERFCTR_SP_11_HI
- REG_A4XX_RBBM_PERFCTR_SP_11_LO
- REG_A4XX_RBBM_PERFCTR_SP_1_HI
- REG_A4XX_RBBM_PERFCTR_SP_1_LO
- REG_A4XX_RBBM_PERFCTR_SP_2_HI
- REG_A4XX_RBBM_PERFCTR_SP_2_LO
- REG_A4XX_RBBM_PERFCTR_SP_3_HI
- REG_A4XX_RBBM_PERFCTR_SP_3_LO
- REG_A4XX_RBBM_PERFCTR_SP_4_HI
- REG_A4XX_RBBM_PERFCTR_SP_4_LO
- REG_A4XX_RBBM_PERFCTR_SP_5_HI
- REG_A4XX_RBBM_PERFCTR_SP_5_LO
- REG_A4XX_RBBM_PERFCTR_SP_6_HI
- REG_A4XX_RBBM_PERFCTR_SP_6_LO
- REG_A4XX_RBBM_PERFCTR_SP_7_HI
- REG_A4XX_RBBM_PERFCTR_SP_7_LO
- REG_A4XX_RBBM_PERFCTR_SP_8_HI
- REG_A4XX_RBBM_PERFCTR_SP_8_LO
- REG_A4XX_RBBM_PERFCTR_SP_9_HI
- REG_A4XX_RBBM_PERFCTR_SP_9_LO
- REG_A4XX_RBBM_PERFCTR_TP_0_HI
- REG_A4XX_RBBM_PERFCTR_TP_0_LO
- REG_A4XX_RBBM_PERFCTR_TP_1_HI
- REG_A4XX_RBBM_PERFCTR_TP_1_LO
- REG_A4XX_RBBM_PERFCTR_TP_2_HI
- REG_A4XX_RBBM_PERFCTR_TP_2_LO
- REG_A4XX_RBBM_PERFCTR_TP_3_HI
- REG_A4XX_RBBM_PERFCTR_TP_3_LO
- REG_A4XX_RBBM_PERFCTR_TP_4_HI
- REG_A4XX_RBBM_PERFCTR_TP_4_LO
- REG_A4XX_RBBM_PERFCTR_TP_5_HI
- REG_A4XX_RBBM_PERFCTR_TP_5_LO
- REG_A4XX_RBBM_PERFCTR_TP_6_HI
- REG_A4XX_RBBM_PERFCTR_TP_6_LO
- REG_A4XX_RBBM_PERFCTR_TP_7_HI
- REG_A4XX_RBBM_PERFCTR_TP_7_LO
- REG_A4XX_RBBM_PERFCTR_TSE_0_HI
- REG_A4XX_RBBM_PERFCTR_TSE_0_LO
- REG_A4XX_RBBM_PERFCTR_TSE_1_HI
- REG_A4XX_RBBM_PERFCTR_TSE_1_LO
- REG_A4XX_RBBM_PERFCTR_TSE_2_HI
- REG_A4XX_RBBM_PERFCTR_TSE_2_LO
- REG_A4XX_RBBM_PERFCTR_TSE_3_HI
- REG_A4XX_RBBM_PERFCTR_TSE_3_LO
- REG_A4XX_RBBM_PERFCTR_UCHE_0_HI
- REG_A4XX_RBBM_PERFCTR_UCHE_0_LO
- REG_A4XX_RBBM_PERFCTR_UCHE_1_HI
- REG_A4XX_RBBM_PERFCTR_UCHE_1_LO
- REG_A4XX_RBBM_PERFCTR_UCHE_2_HI
- REG_A4XX_RBBM_PERFCTR_UCHE_2_LO
- REG_A4XX_RBBM_PERFCTR_UCHE_3_HI
- REG_A4XX_RBBM_PERFCTR_UCHE_3_LO
- REG_A4XX_RBBM_PERFCTR_UCHE_4_HI
- REG_A4XX_RBBM_PERFCTR_UCHE_4_LO
- REG_A4XX_RBBM_PERFCTR_UCHE_5_HI
- REG_A4XX_RBBM_PERFCTR_UCHE_5_LO
- REG_A4XX_RBBM_PERFCTR_UCHE_6_HI
- REG_A4XX_RBBM_PERFCTR_UCHE_6_LO
- REG_A4XX_RBBM_PERFCTR_UCHE_7_HI
- REG_A4XX_RBBM_PERFCTR_UCHE_7_LO
- REG_A4XX_RBBM_PERFCTR_VFD_0_HI
- REG_A4XX_RBBM_PERFCTR_VFD_0_LO
- REG_A4XX_RBBM_PERFCTR_VFD_1_HI
- REG_A4XX_RBBM_PERFCTR_VFD_1_LO
- REG_A4XX_RBBM_PERFCTR_VFD_2_HI
- REG_A4XX_RBBM_PERFCTR_VFD_2_LO
- REG_A4XX_RBBM_PERFCTR_VFD_3_HI
- REG_A4XX_RBBM_PERFCTR_VFD_3_LO
- REG_A4XX_RBBM_PERFCTR_VFD_4_HI
- REG_A4XX_RBBM_PERFCTR_VFD_4_LO
- REG_A4XX_RBBM_PERFCTR_VFD_5_HI
- REG_A4XX_RBBM_PERFCTR_VFD_5_LO
- REG_A4XX_RBBM_PERFCTR_VFD_6_HI
- REG_A4XX_RBBM_PERFCTR_VFD_6_LO
- REG_A4XX_RBBM_PERFCTR_VFD_7_HI
- REG_A4XX_RBBM_PERFCTR_VFD_7_LO
- REG_A4XX_RBBM_PERFCTR_VPC_0_HI
- REG_A4XX_RBBM_PERFCTR_VPC_0_LO
- REG_A4XX_RBBM_PERFCTR_VPC_1_HI
- REG_A4XX_RBBM_PERFCTR_VPC_1_LO
- REG_A4XX_RBBM_PERFCTR_VPC_2_HI
- REG_A4XX_RBBM_PERFCTR_VPC_2_LO
- REG_A4XX_RBBM_PERFCTR_VPC_3_HI
- REG_A4XX_RBBM_PERFCTR_VPC_3_LO
- REG_A4XX_RBBM_PERFCTR_VSC_0_HI
- REG_A4XX_RBBM_PERFCTR_VSC_0_LO
- REG_A4XX_RBBM_PERFCTR_VSC_1_HI
- REG_A4XX_RBBM_PERFCTR_VSC_1_LO
- REG_A4XX_RBBM_POWER_CNTL_IP
- REG_A4XX_RBBM_POWER_STATUS
- REG_A4XX_RBBM_RAM_ACC_63_32
- REG_A4XX_RBBM_RBBM_CTL
- REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL
- REG_A4XX_RBBM_RESET_CYCLES
- REG_A4XX_RBBM_SP_HYST_CNT
- REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0
- REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1
- REG_A4XX_RBBM_STATUS
- REG_A4XX_RBBM_SW_RESET_CMD
- REG_A4XX_RBBM_VBIF_DEBUG_CTL
- REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL
- REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2
- REG_A4XX_RB_ALPHA_CONTROL
- REG_A4XX_RB_BIN_OFFSET
- REG_A4XX_RB_BLEND_ALPHA
- REG_A4XX_RB_BLEND_ALPHA_F32
- REG_A4XX_RB_BLEND_BLUE
- REG_A4XX_RB_BLEND_BLUE_F32
- REG_A4XX_RB_BLEND_GREEN
- REG_A4XX_RB_BLEND_GREEN_F32
- REG_A4XX_RB_BLEND_RED
- REG_A4XX_RB_BLEND_RED_F32
- REG_A4XX_RB_CLEAR_COLOR_DW0
- REG_A4XX_RB_CLEAR_COLOR_DW1
- REG_A4XX_RB_CLEAR_COLOR_DW2
- REG_A4XX_RB_CLEAR_COLOR_DW3
- REG_A4XX_RB_COPY_CONTROL
- REG_A4XX_RB_COPY_DEST_BASE
- REG_A4XX_RB_COPY_DEST_INFO
- REG_A4XX_RB_COPY_DEST_PITCH
- REG_A4XX_RB_DEPTH_CLEAR
- REG_A4XX_RB_DEPTH_CONTROL
- REG_A4XX_RB_DEPTH_INFO
- REG_A4XX_RB_DEPTH_PITCH
- REG_A4XX_RB_DEPTH_PITCH2
- REG_A4XX_RB_FRAME_BUFFER_DIMENSION
- REG_A4XX_RB_FS_OUTPUT
- REG_A4XX_RB_FS_OUTPUT_REG
- REG_A4XX_RB_GMEM_BASE_ADDR
- REG_A4XX_RB_MODE_CONTROL
- REG_A4XX_RB_MRT
- REG_A4XX_RB_MRT_BASE
- REG_A4XX_RB_MRT_BLEND_CONTROL
- REG_A4XX_RB_MRT_BUF_INFO
- REG_A4XX_RB_MRT_CONTROL
- REG_A4XX_RB_MRT_CONTROL3
- REG_A4XX_RB_MSAA_CONTROL
- REG_A4XX_RB_PERFCTR_CCU_SEL_0
- REG_A4XX_RB_PERFCTR_CCU_SEL_1
- REG_A4XX_RB_PERFCTR_CCU_SEL_2
- REG_A4XX_RB_PERFCTR_CCU_SEL_3
- REG_A4XX_RB_PERFCTR_RB_SEL_0
- REG_A4XX_RB_PERFCTR_RB_SEL_1
- REG_A4XX_RB_PERFCTR_RB_SEL_2
- REG_A4XX_RB_PERFCTR_RB_SEL_3
- REG_A4XX_RB_PERFCTR_RB_SEL_4
- REG_A4XX_RB_PERFCTR_RB_SEL_5
- REG_A4XX_RB_PERFCTR_RB_SEL_6
- REG_A4XX_RB_PERFCTR_RB_SEL_7
- REG_A4XX_RB_RENDER_COMPONENTS
- REG_A4XX_RB_RENDER_CONTROL
- REG_A4XX_RB_RENDER_CONTROL2
- REG_A4XX_RB_SAMPLE_COUNT_CONTROL
- REG_A4XX_RB_STENCILREFMASK
- REG_A4XX_RB_STENCILREFMASK_BF
- REG_A4XX_RB_STENCIL_CONTROL
- REG_A4XX_RB_STENCIL_CONTROL2
- REG_A4XX_RB_STENCIL_INFO
- REG_A4XX_RB_STENCIL_PITCH
- REG_A4XX_RB_VPORT_Z_CLAMP
- REG_A4XX_RB_VPORT_Z_CLAMP_MAX
- REG_A4XX_RB_VPORT_Z_CLAMP_MIN
- REG_A4XX_SP_CS_CTRL_REG0
- REG_A4XX_SP_CS_LENGTH_REG
- REG_A4XX_SP_CS_OBJ_OFFSET_REG
- REG_A4XX_SP_CS_OBJ_START
- REG_A4XX_SP_CS_PVT_MEM_ADDR
- REG_A4XX_SP_CS_PVT_MEM_PARAM
- REG_A4XX_SP_CS_PVT_MEM_SIZE
- REG_A4XX_SP_DS_LENGTH_REG
- REG_A4XX_SP_DS_OBJ_OFFSET_REG
- REG_A4XX_SP_DS_OBJ_START
- REG_A4XX_SP_DS_OUT
- REG_A4XX_SP_DS_OUT_REG
- REG_A4XX_SP_DS_PARAM_REG
- REG_A4XX_SP_DS_PVT_MEM_ADDR
- REG_A4XX_SP_DS_PVT_MEM_PARAM
- REG_A4XX_SP_DS_VPC_DST
- REG_A4XX_SP_DS_VPC_DST_REG
- REG_A4XX_SP_FS_CTRL_REG0
- REG_A4XX_SP_FS_CTRL_REG1
- REG_A4XX_SP_FS_LENGTH_REG
- REG_A4XX_SP_FS_MRT
- REG_A4XX_SP_FS_MRT_REG
- REG_A4XX_SP_FS_OBJ_OFFSET_REG
- REG_A4XX_SP_FS_OBJ_START
- REG_A4XX_SP_FS_OUTPUT_REG
- REG_A4XX_SP_FS_PVT_MEM_ADDR
- REG_A4XX_SP_FS_PVT_MEM_PARAM
- REG_A4XX_SP_GS_LENGTH_REG
- REG_A4XX_SP_GS_OBJ_OFFSET_REG
- REG_A4XX_SP_GS_OBJ_START
- REG_A4XX_SP_GS_OUT
- REG_A4XX_SP_GS_OUT_REG
- REG_A4XX_SP_GS_PARAM_REG
- REG_A4XX_SP_GS_PVT_MEM_ADDR
- REG_A4XX_SP_GS_PVT_MEM_PARAM
- REG_A4XX_SP_GS_VPC_DST
- REG_A4XX_SP_GS_VPC_DST_REG
- REG_A4XX_SP_HS_LENGTH_REG
- REG_A4XX_SP_HS_OBJ_OFFSET_REG
- REG_A4XX_SP_HS_OBJ_START
- REG_A4XX_SP_HS_PVT_MEM_ADDR
- REG_A4XX_SP_HS_PVT_MEM_PARAM
- REG_A4XX_SP_INSTR_CACHE_CTRL
- REG_A4XX_SP_MODE_CONTROL
- REG_A4XX_SP_PERFCTR_SP_SEL_0
- REG_A4XX_SP_PERFCTR_SP_SEL_1
- REG_A4XX_SP_PERFCTR_SP_SEL_10
- REG_A4XX_SP_PERFCTR_SP_SEL_11
- REG_A4XX_SP_PERFCTR_SP_SEL_2
- REG_A4XX_SP_PERFCTR_SP_SEL_3
- REG_A4XX_SP_PERFCTR_SP_SEL_4
- REG_A4XX_SP_PERFCTR_SP_SEL_5
- REG_A4XX_SP_PERFCTR_SP_SEL_6
- REG_A4XX_SP_PERFCTR_SP_SEL_7
- REG_A4XX_SP_PERFCTR_SP_SEL_8
- REG_A4XX_SP_PERFCTR_SP_SEL_9
- REG_A4XX_SP_SP_CTRL_REG
- REG_A4XX_SP_VS_CTRL_REG0
- REG_A4XX_SP_VS_CTRL_REG1
- REG_A4XX_SP_VS_LENGTH_REG
- REG_A4XX_SP_VS_OBJ_OFFSET_REG
- REG_A4XX_SP_VS_OBJ_START
- REG_A4XX_SP_VS_OUT
- REG_A4XX_SP_VS_OUT_REG
- REG_A4XX_SP_VS_PARAM_REG
- REG_A4XX_SP_VS_PVT_MEM_ADDR
- REG_A4XX_SP_VS_PVT_MEM_PARAM
- REG_A4XX_SP_VS_STATUS
- REG_A4XX_SP_VS_VPC_DST
- REG_A4XX_SP_VS_VPC_DST_REG
- REG_A4XX_SSBO_0_0
- REG_A4XX_SSBO_0_1
- REG_A4XX_SSBO_0_2
- REG_A4XX_SSBO_0_3
- REG_A4XX_SSBO_1_0
- REG_A4XX_SSBO_1_1
- REG_A4XX_TEX_CONST_0
- REG_A4XX_TEX_CONST_1
- REG_A4XX_TEX_CONST_2
- REG_A4XX_TEX_CONST_3
- REG_A4XX_TEX_CONST_4
- REG_A4XX_TEX_CONST_5
- REG_A4XX_TEX_CONST_6
- REG_A4XX_TEX_CONST_7
- REG_A4XX_TEX_SAMP_0
- REG_A4XX_TEX_SAMP_1
- REG_A4XX_TPL1_DEBUG_ECO_CONTROL
- REG_A4XX_TPL1_PERFCTR_TP_SEL_0
- REG_A4XX_TPL1_PERFCTR_TP_SEL_1
- REG_A4XX_TPL1_PERFCTR_TP_SEL_2
- REG_A4XX_TPL1_PERFCTR_TP_SEL_3
- REG_A4XX_TPL1_PERFCTR_TP_SEL_4
- REG_A4XX_TPL1_PERFCTR_TP_SEL_5
- REG_A4XX_TPL1_PERFCTR_TP_SEL_6
- REG_A4XX_TPL1_PERFCTR_TP_SEL_7
- REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR
- REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR
- REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR
- REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR
- REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR
- REG_A4XX_TPL1_TP_FS_TEX_COUNT
- REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR
- REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR
- REG_A4XX_TPL1_TP_MODE_CONTROL
- REG_A4XX_TPL1_TP_TEX_COUNT
- REG_A4XX_TPL1_TP_TEX_OFFSET
- REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR
- REG_A4XX_UCHE_CACHE_MODE_CONTROL
- REG_A4XX_UCHE_CACHE_STATUS
- REG_A4XX_UCHE_CACHE_WAYS_VFD
- REG_A4XX_UCHE_INVALIDATE0
- REG_A4XX_UCHE_INVALIDATE1
- REG_A4XX_UCHE_PERFCTR_UCHE_SEL_0
- REG_A4XX_UCHE_PERFCTR_UCHE_SEL_1
- REG_A4XX_UCHE_PERFCTR_UCHE_SEL_2
- REG_A4XX_UCHE_PERFCTR_UCHE_SEL_3
- REG_A4XX_UCHE_PERFCTR_UCHE_SEL_4
- REG_A4XX_UCHE_PERFCTR_UCHE_SEL_5
- REG_A4XX_UCHE_PERFCTR_UCHE_SEL_6
- REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7
- REG_A4XX_UCHE_TRAP_BASE_HI
- REG_A4XX_UCHE_TRAP_BASE_LO
- REG_A4XX_UNKNOWN_0CC5
- REG_A4XX_UNKNOWN_0CC6
- REG_A4XX_UNKNOWN_0D01
- REG_A4XX_UNKNOWN_0E42
- REG_A4XX_UNKNOWN_0EC2
- REG_A4XX_UNKNOWN_2001
- REG_A4XX_UNKNOWN_209B
- REG_A4XX_UNKNOWN_20EF
- REG_A4XX_UNKNOWN_2152
- REG_A4XX_UNKNOWN_2153
- REG_A4XX_UNKNOWN_2154
- REG_A4XX_UNKNOWN_2155
- REG_A4XX_UNKNOWN_2156
- REG_A4XX_UNKNOWN_2157
- REG_A4XX_UNKNOWN_21C3
- REG_A4XX_UNKNOWN_21E6
- REG_A4XX_UNKNOWN_2209
- REG_A4XX_UNKNOWN_22D7
- REG_A4XX_UNKNOWN_2352
- REG_A4XX_VBIF_ABIT_SORT
- REG_A4XX_VBIF_ABIT_SORT_CONF
- REG_A4XX_VBIF_CLKON
- REG_A4XX_VBIF_GATE_OFF_WRREQ_EN
- REG_A4XX_VBIF_IN_RD_LIM_CONF0
- REG_A4XX_VBIF_IN_RD_LIM_CONF1
- REG_A4XX_VBIF_IN_WR_LIM_CONF0
- REG_A4XX_VBIF_IN_WR_LIM_CONF1
- REG_A4XX_VBIF_PERF_CNT_EN0
- REG_A4XX_VBIF_PERF_CNT_EN1
- REG_A4XX_VBIF_PERF_CNT_EN2
- REG_A4XX_VBIF_PERF_CNT_EN3
- REG_A4XX_VBIF_PERF_CNT_HIGH0
- REG_A4XX_VBIF_PERF_CNT_HIGH1
- REG_A4XX_VBIF_PERF_CNT_HIGH2
- REG_A4XX_VBIF_PERF_CNT_HIGH3
- REG_A4XX_VBIF_PERF_CNT_LOW0
- REG_A4XX_VBIF_PERF_CNT_LOW1
- REG_A4XX_VBIF_PERF_CNT_LOW2
- REG_A4XX_VBIF_PERF_CNT_LOW3
- REG_A4XX_VBIF_PERF_CNT_SEL0
- REG_A4XX_VBIF_PERF_CNT_SEL1
- REG_A4XX_VBIF_PERF_CNT_SEL2
- REG_A4XX_VBIF_PERF_CNT_SEL3
- REG_A4XX_VBIF_PERF_PWR_CNT_EN0
- REG_A4XX_VBIF_PERF_PWR_CNT_EN1
- REG_A4XX_VBIF_PERF_PWR_CNT_EN2
- REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB
- REG_A4XX_VBIF_VERSION
- REG_A4XX_VFD_CONTROL_0
- REG_A4XX_VFD_CONTROL_1
- REG_A4XX_VFD_CONTROL_2
- REG_A4XX_VFD_CONTROL_3
- REG_A4XX_VFD_CONTROL_4
- REG_A4XX_VFD_DEBUG_CONTROL
- REG_A4XX_VFD_DECODE
- REG_A4XX_VFD_DECODE_INSTR
- REG_A4XX_VFD_FETCH
- REG_A4XX_VFD_FETCH_INSTR_0
- REG_A4XX_VFD_FETCH_INSTR_1
- REG_A4XX_VFD_FETCH_INSTR_2
- REG_A4XX_VFD_FETCH_INSTR_3
- REG_A4XX_VFD_INDEX_OFFSET
- REG_A4XX_VFD_PERFCTR_VFD_SEL_0
- REG_A4XX_VFD_PERFCTR_VFD_SEL_1
- REG_A4XX_VFD_PERFCTR_VFD_SEL_2
- REG_A4XX_VFD_PERFCTR_VFD_SEL_3
- REG_A4XX_VFD_PERFCTR_VFD_SEL_4
- REG_A4XX_VFD_PERFCTR_VFD_SEL_5
- REG_A4XX_VFD_PERFCTR_VFD_SEL_6
- REG_A4XX_VFD_PERFCTR_VFD_SEL_7
- REG_A4XX_VGT_CL_INITIATOR
- REG_A4XX_VGT_EVENT_INITIATOR
- REG_A4XX_VPC_ATTR
- REG_A4XX_VPC_DEBUG_ECO_CONTROL
- REG_A4XX_VPC_DEBUG_RAM_READ
- REG_A4XX_VPC_DEBUG_RAM_SEL
- REG_A4XX_VPC_PACK
- REG_A4XX_VPC_PERFCTR_VPC_SEL_0
- REG_A4XX_VPC_PERFCTR_VPC_SEL_1
- REG_A4XX_VPC_PERFCTR_VPC_SEL_2
- REG_A4XX_VPC_PERFCTR_VPC_SEL_3
- REG_A4XX_VPC_SO_FLUSH_WADDR_3
- REG_A4XX_VPC_VARYING_INTERP
- REG_A4XX_VPC_VARYING_INTERP_MODE
- REG_A4XX_VPC_VARYING_PS_REPL
- REG_A4XX_VPC_VARYING_PS_REPL_MODE
- REG_A4XX_VSC_BIN_SIZE
- REG_A4XX_VSC_DEBUG_ECO_CONTROL
- REG_A4XX_VSC_PERFCTR_VSC_SEL_0
- REG_A4XX_VSC_PERFCTR_VSC_SEL_1
- REG_A4XX_VSC_PIPE_CONFIG
- REG_A4XX_VSC_PIPE_CONFIG_REG
- REG_A4XX_VSC_PIPE_DATA_ADDRESS
- REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG
- REG_A4XX_VSC_PIPE_DATA_LENGTH
- REG_A4XX_VSC_PIPE_DATA_LENGTH_REG
- REG_A4XX_VSC_PIPE_PARTIAL_POSN_1
- REG_A4XX_VSC_SIZE_ADDRESS
- REG_A4XX_VSC_SIZE_ADDRESS2
- REG_A5XX_CCU_POWER_COUNTER_0_HI
- REG_A5XX_CCU_POWER_COUNTER_0_LO
- REG_A5XX_CCU_POWER_COUNTER_1_HI
- REG_A5XX_CCU_POWER_COUNTER_1_LO
- REG_A5XX_CP_ADDR_MODE_CNTL
- REG_A5XX_CP_AHB_FAULT
- REG_A5XX_CP_CHICKEN_DBG
- REG_A5XX_CP_CNTL
- REG_A5XX_CP_CONTEXT_SWITCH_CNTL
- REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI
- REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO
- REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI
- REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO
- REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI
- REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO
- REG_A5XX_CP_CRASH_DUMP_CNTL
- REG_A5XX_CP_CRASH_SCRIPT_BASE_HI
- REG_A5XX_CP_CRASH_SCRIPT_BASE_LO
- REG_A5XX_CP_DRAW_INDIRECT_2
- REG_A5XX_CP_DRAW_INDX_INDIRECT_1
- REG_A5XX_CP_DRAW_INDX_INDIRECT_2
- REG_A5XX_CP_DRAW_INDX_INDIRECT_3
- REG_A5XX_CP_DRAW_INDX_INDIRECT_4
- REG_A5XX_CP_DRAW_INDX_INDIRECT_5
- REG_A5XX_CP_DRAW_STATE_ADDR
- REG_A5XX_CP_DRAW_STATE_DATA
- REG_A5XX_CP_EXEC_CS_INDIRECT_1
- REG_A5XX_CP_EXEC_CS_INDIRECT_2
- REG_A5XX_CP_EXEC_CS_INDIRECT_3
- REG_A5XX_CP_HW_FAULT
- REG_A5XX_CP_IB1_BASE
- REG_A5XX_CP_IB1_BASE_HI
- REG_A5XX_CP_IB1_BUFSZ
- REG_A5XX_CP_IB2_BASE
- REG_A5XX_CP_IB2_BASE_HI
- REG_A5XX_CP_IB2_BUFSZ
- REG_A5XX_CP_INTERRUPT_STATUS
- REG_A5XX_CP_MEQ_DBG_ADDR
- REG_A5XX_CP_MEQ_DBG_DATA
- REG_A5XX_CP_MEQ_THRESHOLDS
- REG_A5XX_CP_MERCIU_DBG_ADDR
- REG_A5XX_CP_MERCIU_DBG_DATA_1
- REG_A5XX_CP_MERCIU_DBG_DATA_2
- REG_A5XX_CP_MERCIU_SIZE
- REG_A5XX_CP_ME_INSTR_BASE_HI
- REG_A5XX_CP_ME_INSTR_BASE_LO
- REG_A5XX_CP_ME_NRT_ADDR_HI
- REG_A5XX_CP_ME_NRT_ADDR_LO
- REG_A5XX_CP_ME_NRT_DATA
- REG_A5XX_CP_ME_STAT_ADDR
- REG_A5XX_CP_ME_STAT_DATA
- REG_A5XX_CP_ME_UCODE_DBG_ADDR
- REG_A5XX_CP_ME_UCODE_DBG_DATA
- REG_A5XX_CP_PERFCTR_CP_SEL_0
- REG_A5XX_CP_PERFCTR_CP_SEL_1
- REG_A5XX_CP_PERFCTR_CP_SEL_2
- REG_A5XX_CP_PERFCTR_CP_SEL_3
- REG_A5XX_CP_PERFCTR_CP_SEL_4
- REG_A5XX_CP_PERFCTR_CP_SEL_5
- REG_A5XX_CP_PERFCTR_CP_SEL_6
- REG_A5XX_CP_PERFCTR_CP_SEL_7
- REG_A5XX_CP_PFP_INSTR_BASE_HI
- REG_A5XX_CP_PFP_INSTR_BASE_LO
- REG_A5XX_CP_PFP_ME_CNTL
- REG_A5XX_CP_PFP_STAT_ADDR
- REG_A5XX_CP_PFP_STAT_DATA
- REG_A5XX_CP_PFP_UCODE_DBG_ADDR
- REG_A5XX_CP_PFP_UCODE_DBG_DATA
- REG_A5XX_CP_POWERCTR_CP_SEL_0
- REG_A5XX_CP_POWERCTR_CP_SEL_1
- REG_A5XX_CP_POWERCTR_CP_SEL_2
- REG_A5XX_CP_POWERCTR_CP_SEL_3
- REG_A5XX_CP_POWER_COUNTER_0_HI
- REG_A5XX_CP_POWER_COUNTER_0_LO
- REG_A5XX_CP_POWER_COUNTER_1_HI
- REG_A5XX_CP_POWER_COUNTER_1_LO
- REG_A5XX_CP_POWER_COUNTER_2_HI
- REG_A5XX_CP_POWER_COUNTER_2_LO
- REG_A5XX_CP_POWER_COUNTER_3_HI
- REG_A5XX_CP_POWER_COUNTER_3_LO
- REG_A5XX_CP_PROTECT
- REG_A5XX_CP_PROTECT_CNTL
- REG_A5XX_CP_PROTECT_REG
- REG_A5XX_CP_PROTECT_STATUS
- REG_A5XX_CP_RB_BASE
- REG_A5XX_CP_RB_BASE_HI
- REG_A5XX_CP_RB_CNTL
- REG_A5XX_CP_RB_RPTR
- REG_A5XX_CP_RB_RPTR_ADDR
- REG_A5XX_CP_RB_RPTR_ADDR_HI
- REG_A5XX_CP_RB_WPTR
- REG_A5XX_CP_ROQ_DBG_ADDR
- REG_A5XX_CP_ROQ_DBG_DATA
- REG_A5XX_CP_ROQ_THRESHOLDS_1
- REG_A5XX_CP_ROQ_THRESHOLDS_2
- REG_A5XX_CP_SCRATCH
- REG_A5XX_CP_SCRATCH_REG
- REG_A5XX_CP_WFI_PEND_CTR
- REG_A5XX_GDPM_CONFIG1
- REG_A5XX_GDPM_CONFIG2
- REG_A5XX_GDPM_INT_EN
- REG_A5XX_GDPM_INT_MASK
- REG_A5XX_GPMU_ALWAYS_ON_COUNTER_HI
- REG_A5XX_GPMU_ALWAYS_ON_COUNTER_LO
- REG_A5XX_GPMU_ALWAYS_ON_COUNTER_RESET
- REG_A5XX_GPMU_BASE_LEAKAGE
- REG_A5XX_GPMU_BEC_ENABLE
- REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL
- REG_A5XX_GPMU_CM3_SYSRESET
- REG_A5XX_GPMU_DATA_RAM_BASE
- REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD
- REG_A5XX_GPMU_GENERAL_0
- REG_A5XX_GPMU_GENERAL_1
- REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL
- REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS
- REG_A5XX_GPMU_GPMU_PWR_THRESHOLD
- REG_A5XX_GPMU_GPMU_VOLTAGE
- REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK
- REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_STATUS
- REG_A5XX_GPMU_INST_RAM_BASE
- REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_0_1
- REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_2_3
- REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_0_1
- REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_2_3
- REG_A5XX_GPMU_POWER_COUNTER_0_HI
- REG_A5XX_GPMU_POWER_COUNTER_0_LO
- REG_A5XX_GPMU_POWER_COUNTER_1_HI
- REG_A5XX_GPMU_POWER_COUNTER_1_LO
- REG_A5XX_GPMU_POWER_COUNTER_2_HI
- REG_A5XX_GPMU_POWER_COUNTER_2_LO
- REG_A5XX_GPMU_POWER_COUNTER_3_HI
- REG_A5XX_GPMU_POWER_COUNTER_3_LO
- REG_A5XX_GPMU_POWER_COUNTER_4_HI
- REG_A5XX_GPMU_POWER_COUNTER_4_LO
- REG_A5XX_GPMU_POWER_COUNTER_5_HI
- REG_A5XX_GPMU_POWER_COUNTER_5_LO
- REG_A5XX_GPMU_POWER_COUNTER_ENABLE
- REG_A5XX_GPMU_POWER_COUNTER_SELECT_0
- REG_A5XX_GPMU_POWER_COUNTER_SELECT_1
- REG_A5XX_GPMU_PWR_COL_BINNING_CTRL
- REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL
- REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST
- REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY
- REG_A5XX_GPMU_RBBM_INTR_INFO
- REG_A5XX_GPMU_RBCCU_CLOCK_CNTL
- REG_A5XX_GPMU_RBCCU_POWER_CNTL
- REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS
- REG_A5XX_GPMU_SP_POWER_CNTL
- REG_A5XX_GPMU_SP_PWR_CLK_STATUS
- REG_A5XX_GPMU_TEMP_SENSOR_CONFIG
- REG_A5XX_GPMU_TEMP_SENSOR_ID
- REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK
- REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_STATUS
- REG_A5XX_GPMU_TEMP_VAL
- REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL
- REG_A5XX_GPMU_WFI_CONFIG
- REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1
- REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_0
- REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_2
- REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_4
- REG_A5XX_GPU_CS_ENABLE_REG
- REG_A5XX_GPU_CS_SENSOR_GENERAL_STATUS
- REG_A5XX_GRAS_2D_BLIT_CNTL
- REG_A5XX_GRAS_2D_DST_INFO
- REG_A5XX_GRAS_2D_SRC_INFO
- REG_A5XX_GRAS_ADDR_MODE_CNTL
- REG_A5XX_GRAS_CL_CNTL
- REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ
- REG_A5XX_GRAS_CL_VPORT_XOFFSET_0
- REG_A5XX_GRAS_CL_VPORT_XSCALE_0
- REG_A5XX_GRAS_CL_VPORT_YOFFSET_0
- REG_A5XX_GRAS_CL_VPORT_YSCALE_0
- REG_A5XX_GRAS_CL_VPORT_ZOFFSET_0
- REG_A5XX_GRAS_CL_VPORT_ZSCALE_0
- REG_A5XX_GRAS_CNTL
- REG_A5XX_GRAS_LRZ_BUFFER_BASE_HI
- REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO
- REG_A5XX_GRAS_LRZ_BUFFER_PITCH
- REG_A5XX_GRAS_LRZ_CNTL
- REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI
- REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO
- REG_A5XX_GRAS_PERFCTR_LRZ_SEL_0
- REG_A5XX_GRAS_PERFCTR_LRZ_SEL_1
- REG_A5XX_GRAS_PERFCTR_LRZ_SEL_2
- REG_A5XX_GRAS_PERFCTR_LRZ_SEL_3
- REG_A5XX_GRAS_PERFCTR_RAS_SEL_0
- REG_A5XX_GRAS_PERFCTR_RAS_SEL_1
- REG_A5XX_GRAS_PERFCTR_RAS_SEL_2
- REG_A5XX_GRAS_PERFCTR_RAS_SEL_3
- REG_A5XX_GRAS_PERFCTR_TSE_SEL_0
- REG_A5XX_GRAS_PERFCTR_TSE_SEL_1
- REG_A5XX_GRAS_PERFCTR_TSE_SEL_2
- REG_A5XX_GRAS_PERFCTR_TSE_SEL_3
- REG_A5XX_GRAS_SC_BIN_CNTL
- REG_A5XX_GRAS_SC_CNTL
- REG_A5XX_GRAS_SC_DEST_MSAA_CNTL
- REG_A5XX_GRAS_SC_RAS_MSAA_CNTL
- REG_A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0
- REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL
- REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0
- REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0
- REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0
- REG_A5XX_GRAS_SC_WINDOW_SCISSOR_BR
- REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL
- REG_A5XX_GRAS_SU_CNTL
- REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL
- REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO
- REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL
- REG_A5XX_GRAS_SU_LAYERED
- REG_A5XX_GRAS_SU_POINT_MINMAX
- REG_A5XX_GRAS_SU_POINT_SIZE
- REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET
- REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP
- REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE
- REG_A5XX_HLSQ_ADDR_MODE_CNTL
- REG_A5XX_HLSQ_CONTROL_0_REG
- REG_A5XX_HLSQ_CONTROL_1_REG
- REG_A5XX_HLSQ_CONTROL_2_REG
- REG_A5XX_HLSQ_CONTROL_3_REG
- REG_A5XX_HLSQ_CONTROL_4_REG
- REG_A5XX_HLSQ_CS_CNTL
- REG_A5XX_HLSQ_CS_CNTL_0
- REG_A5XX_HLSQ_CS_CNTL_1
- REG_A5XX_HLSQ_CS_CONFIG
- REG_A5XX_HLSQ_CS_CONSTLEN
- REG_A5XX_HLSQ_CS_INSTRLEN
- REG_A5XX_HLSQ_CS_KERNEL_GROUP_X
- REG_A5XX_HLSQ_CS_KERNEL_GROUP_Y
- REG_A5XX_HLSQ_CS_KERNEL_GROUP_Z
- REG_A5XX_HLSQ_CS_NDRANGE_0
- REG_A5XX_HLSQ_CS_NDRANGE_1
- REG_A5XX_HLSQ_CS_NDRANGE_2
- REG_A5XX_HLSQ_CS_NDRANGE_3
- REG_A5XX_HLSQ_CS_NDRANGE_4
- REG_A5XX_HLSQ_CS_NDRANGE_5
- REG_A5XX_HLSQ_CS_NDRANGE_6
- REG_A5XX_HLSQ_DBG_AHB_READ_APERTURE
- REG_A5XX_HLSQ_DBG_ECO_CNTL
- REG_A5XX_HLSQ_DBG_READ_SEL
- REG_A5XX_HLSQ_DS_CNTL
- REG_A5XX_HLSQ_DS_CONFIG
- REG_A5XX_HLSQ_DS_CONSTLEN
- REG_A5XX_HLSQ_DS_INSTRLEN
- REG_A5XX_HLSQ_FS_CNTL
- REG_A5XX_HLSQ_FS_CONFIG
- REG_A5XX_HLSQ_FS_CONSTLEN
- REG_A5XX_HLSQ_FS_INSTRLEN
- REG_A5XX_HLSQ_GS_CNTL
- REG_A5XX_HLSQ_GS_CONFIG
- REG_A5XX_HLSQ_GS_CONSTLEN
- REG_A5XX_HLSQ_GS_INSTRLEN
- REG_A5XX_HLSQ_HS_CNTL
- REG_A5XX_HLSQ_HS_CONFIG
- REG_A5XX_HLSQ_HS_CONSTLEN
- REG_A5XX_HLSQ_HS_INSTRLEN
- REG_A5XX_HLSQ_MODE_CNTL
- REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_0
- REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_1
- REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_2
- REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_3
- REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_4
- REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_5
- REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_6
- REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_7
- REG_A5XX_HLSQ_SPTP_RDSEL
- REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0
- REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1
- REG_A5XX_HLSQ_UPDATE_CNTL
- REG_A5XX_HLSQ_VS_CNTL
- REG_A5XX_HLSQ_VS_CONFIG
- REG_A5XX_HLSQ_VS_CONSTLEN
- REG_A5XX_HLSQ_VS_INSTRLEN
- REG_A5XX_PC_ADDR_MODE_CNTL
- REG_A5XX_PC_DBG_ECO_CNTL
- REG_A5XX_PC_GS_LAYERED
- REG_A5XX_PC_GS_PARAM
- REG_A5XX_PC_HS_PARAM
- REG_A5XX_PC_INDEX_BUF_HI
- REG_A5XX_PC_INDEX_BUF_LO
- REG_A5XX_PC_MAX_INDEX
- REG_A5XX_PC_MODE_CNTL
- REG_A5XX_PC_PERFCTR_PC_SEL_0
- REG_A5XX_PC_PERFCTR_PC_SEL_1
- REG_A5XX_PC_PERFCTR_PC_SEL_2
- REG_A5XX_PC_PERFCTR_PC_SEL_3
- REG_A5XX_PC_PERFCTR_PC_SEL_4
- REG_A5XX_PC_PERFCTR_PC_SEL_5
- REG_A5XX_PC_PERFCTR_PC_SEL_6
- REG_A5XX_PC_PERFCTR_PC_SEL_7
- REG_A5XX_PC_POWER_CNTL
- REG_A5XX_PC_PRIMITIVE_CNTL
- REG_A5XX_PC_PRIM_VTX_CNTL
- REG_A5XX_PC_RASTER_CNTL
- REG_A5XX_PC_RESTART_INDEX
- REG_A5XX_PC_START_INDEX
- REG_A5XX_PC_TESSFACTOR_ADDR_HI
- REG_A5XX_PC_TESSFACTOR_ADDR_LO
- REG_A5XX_RBBM_AHB_CMD
- REG_A5XX_RBBM_AHB_CNTL0
- REG_A5XX_RBBM_AHB_CNTL1
- REG_A5XX_RBBM_AHB_CNTL2
- REG_A5XX_RBBM_AHB_DBG_CNTL
- REG_A5XX_RBBM_AHB_ERROR
- REG_A5XX_RBBM_AHB_ERROR_STATUS
- REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS
- REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS
- REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS
- REG_A5XX_RBBM_ALWAYSON_COUNTER_HI
- REG_A5XX_RBBM_ALWAYSON_COUNTER_LO
- REG_A5XX_RBBM_BLOCK_SW_RESET_CMD
- REG_A5XX_RBBM_BLOCK_SW_RESET_CMD2
- REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_0
- REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_1
- REG_A5XX_RBBM_CFG_DBGBUS_CLRC
- REG_A5XX_RBBM_CFG_DBGBUS_CNTLM
- REG_A5XX_RBBM_CFG_DBGBUS_CNTLT
- REG_A5XX_RBBM_CFG_DBGBUS_COUNT0
- REG_A5XX_RBBM_CFG_DBGBUS_COUNT1
- REG_A5XX_RBBM_CFG_DBGBUS_COUNT2
- REG_A5XX_RBBM_CFG_DBGBUS_COUNT3
- REG_A5XX_RBBM_CFG_DBGBUS_COUNT4
- REG_A5XX_RBBM_CFG_DBGBUS_COUNT5
- REG_A5XX_RBBM_CFG_DBGBUS_EVENT_LOGIC
- REG_A5XX_RBBM_CFG_DBGBUS_IDX
- REG_A5XX_RBBM_CFG_DBGBUS_IVTE_0
- REG_A5XX_RBBM_CFG_DBGBUS_IVTE_1
- REG_A5XX_RBBM_CFG_DBGBUS_IVTE_2
- REG_A5XX_RBBM_CFG_DBGBUS_IVTE_3
- REG_A5XX_RBBM_CFG_DBGBUS_IVTL_0
- REG_A5XX_RBBM_CFG_DBGBUS_IVTL_1
- REG_A5XX_RBBM_CFG_DBGBUS_IVTL_2
- REG_A5XX_RBBM_CFG_DBGBUS_IVTL_3
- REG_A5XX_RBBM_CFG_DBGBUS_LOADIVT
- REG_A5XX_RBBM_CFG_DBGBUS_LOADREG
- REG_A5XX_RBBM_CFG_DBGBUS_MASKE_0
- REG_A5XX_RBBM_CFG_DBGBUS_MASKE_1
- REG_A5XX_RBBM_CFG_DBGBUS_MASKE_2
- REG_A5XX_RBBM_CFG_DBGBUS_MASKE_3
- REG_A5XX_RBBM_CFG_DBGBUS_MASKL_0
- REG_A5XX_RBBM_CFG_DBGBUS_MASKL_1
- REG_A5XX_RBBM_CFG_DBGBUS_MASKL_2
- REG_A5XX_RBBM_CFG_DBGBUS_MASKL_3
- REG_A5XX_RBBM_CFG_DBGBUS_MISR0
- REG_A5XX_RBBM_CFG_DBGBUS_MISR1
- REG_A5XX_RBBM_CFG_DBGBUS_NIBBLEE
- REG_A5XX_RBBM_CFG_DBGBUS_OPE
- REG_A5XX_RBBM_CFG_DBGBUS_OPL
- REG_A5XX_RBBM_CFG_DBGBUS_OVER
- REG_A5XX_RBBM_CFG_DBGBUS_PTRC0
- REG_A5XX_RBBM_CFG_DBGBUS_PTRC1
- REG_A5XX_RBBM_CFG_DBGBUS_SEL_A
- REG_A5XX_RBBM_CFG_DBGBUS_SEL_B
- REG_A5XX_RBBM_CFG_DBGBUS_SEL_C
- REG_A5XX_RBBM_CFG_DBGBUS_SEL_D
- REG_A5XX_RBBM_CFG_DBGBUS_TRACE_ADDR
- REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF0
- REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF1
- REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF2
- REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF3
- REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF4
- REG_A5XX_RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT
- REG_A5XX_RBBM_CLOCK_CNTL
- REG_A5XX_RBBM_CLOCK_CNTL2_RAC
- REG_A5XX_RBBM_CLOCK_CNTL2_RB0
- REG_A5XX_RBBM_CLOCK_CNTL2_RB1
- REG_A5XX_RBBM_CLOCK_CNTL2_RB2
- REG_A5XX_RBBM_CLOCK_CNTL2_RB3
- REG_A5XX_RBBM_CLOCK_CNTL2_SP0
- REG_A5XX_RBBM_CLOCK_CNTL2_SP1
- REG_A5XX_RBBM_CLOCK_CNTL2_SP2
- REG_A5XX_RBBM_CLOCK_CNTL2_SP3
- REG_A5XX_RBBM_CLOCK_CNTL2_TP0
- REG_A5XX_RBBM_CLOCK_CNTL2_TP1
- REG_A5XX_RBBM_CLOCK_CNTL2_TP2
- REG_A5XX_RBBM_CLOCK_CNTL2_TP3
- REG_A5XX_RBBM_CLOCK_CNTL2_UCHE
- REG_A5XX_RBBM_CLOCK_CNTL3_TP0
- REG_A5XX_RBBM_CLOCK_CNTL3_TP1
- REG_A5XX_RBBM_CLOCK_CNTL3_TP2
- REG_A5XX_RBBM_CLOCK_CNTL3_TP3
- REG_A5XX_RBBM_CLOCK_CNTL3_UCHE
- REG_A5XX_RBBM_CLOCK_CNTL4_UCHE
- REG_A5XX_RBBM_CLOCK_CNTL_CCU0
- REG_A5XX_RBBM_CLOCK_CNTL_CCU1
- REG_A5XX_RBBM_CLOCK_CNTL_CCU2
- REG_A5XX_RBBM_CLOCK_CNTL_CCU3
- REG_A5XX_RBBM_CLOCK_CNTL_GPMU
- REG_A5XX_RBBM_CLOCK_CNTL_RAC
- REG_A5XX_RBBM_CLOCK_CNTL_RB0
- REG_A5XX_RBBM_CLOCK_CNTL_RB1
- REG_A5XX_RBBM_CLOCK_CNTL_RB2
- REG_A5XX_RBBM_CLOCK_CNTL_RB3
- REG_A5XX_RBBM_CLOCK_CNTL_SP0
- REG_A5XX_RBBM_CLOCK_CNTL_SP1
- REG_A5XX_RBBM_CLOCK_CNTL_SP2
- REG_A5XX_RBBM_CLOCK_CNTL_SP3
- REG_A5XX_RBBM_CLOCK_CNTL_TP0
- REG_A5XX_RBBM_CLOCK_CNTL_TP1
- REG_A5XX_RBBM_CLOCK_CNTL_TP2
- REG_A5XX_RBBM_CLOCK_CNTL_TP3
- REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM
- REG_A5XX_RBBM_CLOCK_CNTL_UCHE
- REG_A5XX_RBBM_CLOCK_DELAY2_TP0
- REG_A5XX_RBBM_CLOCK_DELAY2_TP1
- REG_A5XX_RBBM_CLOCK_DELAY2_TP2
- REG_A5XX_RBBM_CLOCK_DELAY2_TP3
- REG_A5XX_RBBM_CLOCK_DELAY3_TP0
- REG_A5XX_RBBM_CLOCK_DELAY3_TP1
- REG_A5XX_RBBM_CLOCK_DELAY3_TP2
- REG_A5XX_RBBM_CLOCK_DELAY3_TP3
- REG_A5XX_RBBM_CLOCK_DELAY_GPC
- REG_A5XX_RBBM_CLOCK_DELAY_GPMU
- REG_A5XX_RBBM_CLOCK_DELAY_HLSQ
- REG_A5XX_RBBM_CLOCK_DELAY_RAC
- REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0
- REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1
- REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2
- REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3
- REG_A5XX_RBBM_CLOCK_DELAY_SP0
- REG_A5XX_RBBM_CLOCK_DELAY_SP1
- REG_A5XX_RBBM_CLOCK_DELAY_SP2
- REG_A5XX_RBBM_CLOCK_DELAY_SP3
- REG_A5XX_RBBM_CLOCK_DELAY_TP0
- REG_A5XX_RBBM_CLOCK_DELAY_TP1
- REG_A5XX_RBBM_CLOCK_DELAY_TP2
- REG_A5XX_RBBM_CLOCK_DELAY_TP3
- REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM
- REG_A5XX_RBBM_CLOCK_DELAY_UCHE
- REG_A5XX_RBBM_CLOCK_DELAY_VFD
- REG_A5XX_RBBM_CLOCK_HYST2_TP0
- REG_A5XX_RBBM_CLOCK_HYST2_TP1
- REG_A5XX_RBBM_CLOCK_HYST2_TP2
- REG_A5XX_RBBM_CLOCK_HYST2_TP3
- REG_A5XX_RBBM_CLOCK_HYST3_TP0
- REG_A5XX_RBBM_CLOCK_HYST3_TP1
- REG_A5XX_RBBM_CLOCK_HYST3_TP2
- REG_A5XX_RBBM_CLOCK_HYST3_TP3
- REG_A5XX_RBBM_CLOCK_HYST_GPC
- REG_A5XX_RBBM_CLOCK_HYST_GPMU
- REG_A5XX_RBBM_CLOCK_HYST_RAC
- REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0
- REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1
- REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2
- REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3
- REG_A5XX_RBBM_CLOCK_HYST_SP0
- REG_A5XX_RBBM_CLOCK_HYST_SP1
- REG_A5XX_RBBM_CLOCK_HYST_SP2
- REG_A5XX_RBBM_CLOCK_HYST_SP3
- REG_A5XX_RBBM_CLOCK_HYST_TP0
- REG_A5XX_RBBM_CLOCK_HYST_TP1
- REG_A5XX_RBBM_CLOCK_HYST_TP2
- REG_A5XX_RBBM_CLOCK_HYST_TP3
- REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM
- REG_A5XX_RBBM_CLOCK_HYST_UCHE
- REG_A5XX_RBBM_CLOCK_HYST_VFD
- REG_A5XX_RBBM_CLOCK_MODE_GPC
- REG_A5XX_RBBM_CLOCK_MODE_VFD
- REG_A5XX_RBBM_DBG_LO_HI_GPIO
- REG_A5XX_RBBM_EXT_TRACE_BUS_CNTL
- REG_A5XX_RBBM_EXT_VBIF_DBG_CNTL
- REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL
- REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11
- REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12
- REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13
- REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14
- REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15
- REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16
- REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17
- REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18
- REG_A5XX_RBBM_INT_0_MASK
- REG_A5XX_RBBM_INT_0_STATUS
- REG_A5XX_RBBM_INT_CLEAR_CMD
- REG_A5XX_RBBM_ISDB_CNT
- REG_A5XX_RBBM_PERFCTR_CCU_0_HI
- REG_A5XX_RBBM_PERFCTR_CCU_0_LO
- REG_A5XX_RBBM_PERFCTR_CCU_1_HI
- REG_A5XX_RBBM_PERFCTR_CCU_1_LO
- REG_A5XX_RBBM_PERFCTR_CCU_2_HI
- REG_A5XX_RBBM_PERFCTR_CCU_2_LO
- REG_A5XX_RBBM_PERFCTR_CCU_3_HI
- REG_A5XX_RBBM_PERFCTR_CCU_3_LO
- REG_A5XX_RBBM_PERFCTR_CMP_0_HI
- REG_A5XX_RBBM_PERFCTR_CMP_0_LO
- REG_A5XX_RBBM_PERFCTR_CMP_1_HI
- REG_A5XX_RBBM_PERFCTR_CMP_1_LO
- REG_A5XX_RBBM_PERFCTR_CMP_2_HI
- REG_A5XX_RBBM_PERFCTR_CMP_2_LO
- REG_A5XX_RBBM_PERFCTR_CMP_3_HI
- REG_A5XX_RBBM_PERFCTR_CMP_3_LO
- REG_A5XX_RBBM_PERFCTR_CNTL
- REG_A5XX_RBBM_PERFCTR_CP_0_HI
- REG_A5XX_RBBM_PERFCTR_CP_0_LO
- REG_A5XX_RBBM_PERFCTR_CP_1_HI
- REG_A5XX_RBBM_PERFCTR_CP_1_LO
- REG_A5XX_RBBM_PERFCTR_CP_2_HI
- REG_A5XX_RBBM_PERFCTR_CP_2_LO
- REG_A5XX_RBBM_PERFCTR_CP_3_HI
- REG_A5XX_RBBM_PERFCTR_CP_3_LO
- REG_A5XX_RBBM_PERFCTR_CP_4_HI
- REG_A5XX_RBBM_PERFCTR_CP_4_LO
- REG_A5XX_RBBM_PERFCTR_CP_5_HI
- REG_A5XX_RBBM_PERFCTR_CP_5_LO
- REG_A5XX_RBBM_PERFCTR_CP_6_HI
- REG_A5XX_RBBM_PERFCTR_CP_6_LO
- REG_A5XX_RBBM_PERFCTR_CP_7_HI
- REG_A5XX_RBBM_PERFCTR_CP_7_LO
- REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED
- REG_A5XX_RBBM_PERFCTR_HLSQ_0_HI
- REG_A5XX_RBBM_PERFCTR_HLSQ_0_LO
- REG_A5XX_RBBM_PERFCTR_HLSQ_1_HI
- REG_A5XX_RBBM_PERFCTR_HLSQ_1_LO
- REG_A5XX_RBBM_PERFCTR_HLSQ_2_HI
- REG_A5XX_RBBM_PERFCTR_HLSQ_2_LO
- REG_A5XX_RBBM_PERFCTR_HLSQ_3_HI
- REG_A5XX_RBBM_PERFCTR_HLSQ_3_LO
- REG_A5XX_RBBM_PERFCTR_HLSQ_4_HI
- REG_A5XX_RBBM_PERFCTR_HLSQ_4_LO
- REG_A5XX_RBBM_PERFCTR_HLSQ_5_HI
- REG_A5XX_RBBM_PERFCTR_HLSQ_5_LO
- REG_A5XX_RBBM_PERFCTR_HLSQ_6_HI
- REG_A5XX_RBBM_PERFCTR_HLSQ_6_LO
- REG_A5XX_RBBM_PERFCTR_HLSQ_7_HI
- REG_A5XX_RBBM_PERFCTR_HLSQ_7_LO
- REG_A5XX_RBBM_PERFCTR_LOAD_CMD0
- REG_A5XX_RBBM_PERFCTR_LOAD_CMD1
- REG_A5XX_RBBM_PERFCTR_LOAD_CMD2
- REG_A5XX_RBBM_PERFCTR_LOAD_CMD3
- REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI
- REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO
- REG_A5XX_RBBM_PERFCTR_LRZ_0_HI
- REG_A5XX_RBBM_PERFCTR_LRZ_0_LO
- REG_A5XX_RBBM_PERFCTR_LRZ_1_HI
- REG_A5XX_RBBM_PERFCTR_LRZ_1_LO
- REG_A5XX_RBBM_PERFCTR_LRZ_2_HI
- REG_A5XX_RBBM_PERFCTR_LRZ_2_LO
- REG_A5XX_RBBM_PERFCTR_LRZ_3_HI
- REG_A5XX_RBBM_PERFCTR_LRZ_3_LO
- REG_A5XX_RBBM_PERFCTR_PC_0_HI
- REG_A5XX_RBBM_PERFCTR_PC_0_LO
- REG_A5XX_RBBM_PERFCTR_PC_1_HI
- REG_A5XX_RBBM_PERFCTR_PC_1_LO
- REG_A5XX_RBBM_PERFCTR_PC_2_HI
- REG_A5XX_RBBM_PERFCTR_PC_2_LO
- REG_A5XX_RBBM_PERFCTR_PC_3_HI
- REG_A5XX_RBBM_PERFCTR_PC_3_LO
- REG_A5XX_RBBM_PERFCTR_PC_4_HI
- REG_A5XX_RBBM_PERFCTR_PC_4_LO
- REG_A5XX_RBBM_PERFCTR_PC_5_HI
- REG_A5XX_RBBM_PERFCTR_PC_5_LO
- REG_A5XX_RBBM_PERFCTR_PC_6_HI
- REG_A5XX_RBBM_PERFCTR_PC_6_LO
- REG_A5XX_RBBM_PERFCTR_PC_7_HI
- REG_A5XX_RBBM_PERFCTR_PC_7_LO
- REG_A5XX_RBBM_PERFCTR_RAS_0_HI
- REG_A5XX_RBBM_PERFCTR_RAS_0_LO
- REG_A5XX_RBBM_PERFCTR_RAS_1_HI
- REG_A5XX_RBBM_PERFCTR_RAS_1_LO
- REG_A5XX_RBBM_PERFCTR_RAS_2_HI
- REG_A5XX_RBBM_PERFCTR_RAS_2_LO
- REG_A5XX_RBBM_PERFCTR_RAS_3_HI
- REG_A5XX_RBBM_PERFCTR_RAS_3_LO
- REG_A5XX_RBBM_PERFCTR_RBBM_0_HI
- REG_A5XX_RBBM_PERFCTR_RBBM_0_LO
- REG_A5XX_RBBM_PERFCTR_RBBM_1_HI
- REG_A5XX_RBBM_PERFCTR_RBBM_1_LO
- REG_A5XX_RBBM_PERFCTR_RBBM_2_HI
- REG_A5XX_RBBM_PERFCTR_RBBM_2_LO
- REG_A5XX_RBBM_PERFCTR_RBBM_3_HI
- REG_A5XX_RBBM_PERFCTR_RBBM_3_LO
- REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0
- REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1
- REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2
- REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3
- REG_A5XX_RBBM_PERFCTR_RB_0_HI
- REG_A5XX_RBBM_PERFCTR_RB_0_LO
- REG_A5XX_RBBM_PERFCTR_RB_1_HI
- REG_A5XX_RBBM_PERFCTR_RB_1_LO
- REG_A5XX_RBBM_PERFCTR_RB_2_HI
- REG_A5XX_RBBM_PERFCTR_RB_2_LO
- REG_A5XX_RBBM_PERFCTR_RB_3_HI
- REG_A5XX_RBBM_PERFCTR_RB_3_LO
- REG_A5XX_RBBM_PERFCTR_RB_4_HI
- REG_A5XX_RBBM_PERFCTR_RB_4_LO
- REG_A5XX_RBBM_PERFCTR_RB_5_HI
- REG_A5XX_RBBM_PERFCTR_RB_5_LO
- REG_A5XX_RBBM_PERFCTR_RB_6_HI
- REG_A5XX_RBBM_PERFCTR_RB_6_LO
- REG_A5XX_RBBM_PERFCTR_RB_7_HI
- REG_A5XX_RBBM_PERFCTR_RB_7_LO
- REG_A5XX_RBBM_PERFCTR_SP_0_HI
- REG_A5XX_RBBM_PERFCTR_SP_0_LO
- REG_A5XX_RBBM_PERFCTR_SP_10_HI
- REG_A5XX_RBBM_PERFCTR_SP_10_LO
- REG_A5XX_RBBM_PERFCTR_SP_11_HI
- REG_A5XX_RBBM_PERFCTR_SP_11_LO
- REG_A5XX_RBBM_PERFCTR_SP_1_HI
- REG_A5XX_RBBM_PERFCTR_SP_1_LO
- REG_A5XX_RBBM_PERFCTR_SP_2_HI
- REG_A5XX_RBBM_PERFCTR_SP_2_LO
- REG_A5XX_RBBM_PERFCTR_SP_3_HI
- REG_A5XX_RBBM_PERFCTR_SP_3_LO
- REG_A5XX_RBBM_PERFCTR_SP_4_HI
- REG_A5XX_RBBM_PERFCTR_SP_4_LO
- REG_A5XX_RBBM_PERFCTR_SP_5_HI
- REG_A5XX_RBBM_PERFCTR_SP_5_LO
- REG_A5XX_RBBM_PERFCTR_SP_6_HI
- REG_A5XX_RBBM_PERFCTR_SP_6_LO
- REG_A5XX_RBBM_PERFCTR_SP_7_HI
- REG_A5XX_RBBM_PERFCTR_SP_7_LO
- REG_A5XX_RBBM_PERFCTR_SP_8_HI
- REG_A5XX_RBBM_PERFCTR_SP_8_LO
- REG_A5XX_RBBM_PERFCTR_SP_9_HI
- REG_A5XX_RBBM_PERFCTR_SP_9_LO
- REG_A5XX_RBBM_PERFCTR_TP_0_HI
- REG_A5XX_RBBM_PERFCTR_TP_0_LO
- REG_A5XX_RBBM_PERFCTR_TP_1_HI
- REG_A5XX_RBBM_PERFCTR_TP_1_LO
- REG_A5XX_RBBM_PERFCTR_TP_2_HI
- REG_A5XX_RBBM_PERFCTR_TP_2_LO
- REG_A5XX_RBBM_PERFCTR_TP_3_HI
- REG_A5XX_RBBM_PERFCTR_TP_3_LO
- REG_A5XX_RBBM_PERFCTR_TP_4_HI
- REG_A5XX_RBBM_PERFCTR_TP_4_LO
- REG_A5XX_RBBM_PERFCTR_TP_5_HI
- REG_A5XX_RBBM_PERFCTR_TP_5_LO
- REG_A5XX_RBBM_PERFCTR_TP_6_HI
- REG_A5XX_RBBM_PERFCTR_TP_6_LO
- REG_A5XX_RBBM_PERFCTR_TP_7_HI
- REG_A5XX_RBBM_PERFCTR_TP_7_LO
- REG_A5XX_RBBM_PERFCTR_TSE_0_HI
- REG_A5XX_RBBM_PERFCTR_TSE_0_LO
- REG_A5XX_RBBM_PERFCTR_TSE_1_HI
- REG_A5XX_RBBM_PERFCTR_TSE_1_LO
- REG_A5XX_RBBM_PERFCTR_TSE_2_HI
- REG_A5XX_RBBM_PERFCTR_TSE_2_LO
- REG_A5XX_RBBM_PERFCTR_TSE_3_HI
- REG_A5XX_RBBM_PERFCTR_TSE_3_LO
- REG_A5XX_RBBM_PERFCTR_UCHE_0_HI
- REG_A5XX_RBBM_PERFCTR_UCHE_0_LO
- REG_A5XX_RBBM_PERFCTR_UCHE_1_HI
- REG_A5XX_RBBM_PERFCTR_UCHE_1_LO
- REG_A5XX_RBBM_PERFCTR_UCHE_2_HI
- REG_A5XX_RBBM_PERFCTR_UCHE_2_LO
- REG_A5XX_RBBM_PERFCTR_UCHE_3_HI
- REG_A5XX_RBBM_PERFCTR_UCHE_3_LO
- REG_A5XX_RBBM_PERFCTR_UCHE_4_HI
- REG_A5XX_RBBM_PERFCTR_UCHE_4_LO
- REG_A5XX_RBBM_PERFCTR_UCHE_5_HI
- REG_A5XX_RBBM_PERFCTR_UCHE_5_LO
- REG_A5XX_RBBM_PERFCTR_UCHE_6_HI
- REG_A5XX_RBBM_PERFCTR_UCHE_6_LO
- REG_A5XX_RBBM_PERFCTR_UCHE_7_HI
- REG_A5XX_RBBM_PERFCTR_UCHE_7_LO
- REG_A5XX_RBBM_PERFCTR_VFD_0_HI
- REG_A5XX_RBBM_PERFCTR_VFD_0_LO
- REG_A5XX_RBBM_PERFCTR_VFD_1_HI
- REG_A5XX_RBBM_PERFCTR_VFD_1_LO
- REG_A5XX_RBBM_PERFCTR_VFD_2_HI
- REG_A5XX_RBBM_PERFCTR_VFD_2_LO
- REG_A5XX_RBBM_PERFCTR_VFD_3_HI
- REG_A5XX_RBBM_PERFCTR_VFD_3_LO
- REG_A5XX_RBBM_PERFCTR_VFD_4_HI
- REG_A5XX_RBBM_PERFCTR_VFD_4_LO
- REG_A5XX_RBBM_PERFCTR_VFD_5_HI
- REG_A5XX_RBBM_PERFCTR_VFD_5_LO
- REG_A5XX_RBBM_PERFCTR_VFD_6_HI
- REG_A5XX_RBBM_PERFCTR_VFD_6_LO
- REG_A5XX_RBBM_PERFCTR_VFD_7_HI
- REG_A5XX_RBBM_PERFCTR_VFD_7_LO
- REG_A5XX_RBBM_PERFCTR_VPC_0_HI
- REG_A5XX_RBBM_PERFCTR_VPC_0_LO
- REG_A5XX_RBBM_PERFCTR_VPC_1_HI
- REG_A5XX_RBBM_PERFCTR_VPC_1_LO
- REG_A5XX_RBBM_PERFCTR_VPC_2_HI
- REG_A5XX_RBBM_PERFCTR_VPC_2_LO
- REG_A5XX_RBBM_PERFCTR_VPC_3_HI
- REG_A5XX_RBBM_PERFCTR_VPC_3_LO
- REG_A5XX_RBBM_PERFCTR_VSC_0_HI
- REG_A5XX_RBBM_PERFCTR_VSC_0_LO
- REG_A5XX_RBBM_PERFCTR_VSC_1_HI
- REG_A5XX_RBBM_PERFCTR_VSC_1_LO
- REG_A5XX_RBBM_READ_AHB_THROUGH_DBG
- REG_A5XX_RBBM_SECVID_TRUST_CNTL
- REG_A5XX_RBBM_SECVID_TRUST_CONFIG
- REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL
- REG_A5XX_RBBM_SECVID_TSB_CNTL
- REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_HI
- REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_LO
- REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI
- REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO
- REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE
- REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_HI
- REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_LO
- REG_A5XX_RBBM_STATUS
- REG_A5XX_RBBM_STATUS3
- REG_A5XX_RBBM_SW_RESET_CMD
- REG_A5XX_RB_2D_BLIT_CNTL
- REG_A5XX_RB_2D_DST_FLAGS_HI
- REG_A5XX_RB_2D_DST_FLAGS_LO
- REG_A5XX_RB_2D_DST_HI
- REG_A5XX_RB_2D_DST_INFO
- REG_A5XX_RB_2D_DST_LO
- REG_A5XX_RB_2D_DST_SIZE
- REG_A5XX_RB_2D_SRC_FLAGS_HI
- REG_A5XX_RB_2D_SRC_FLAGS_LO
- REG_A5XX_RB_2D_SRC_HI
- REG_A5XX_RB_2D_SRC_INFO
- REG_A5XX_RB_2D_SRC_LO
- REG_A5XX_RB_2D_SRC_SIZE
- REG_A5XX_RB_2D_SRC_SOLID_DW0
- REG_A5XX_RB_2D_SRC_SOLID_DW1
- REG_A5XX_RB_2D_SRC_SOLID_DW2
- REG_A5XX_RB_2D_SRC_SOLID_DW3
- REG_A5XX_RB_ADDR_MODE_CNTL
- REG_A5XX_RB_ALPHA_CONTROL
- REG_A5XX_RB_BLEND_ALPHA
- REG_A5XX_RB_BLEND_ALPHA_F32
- REG_A5XX_RB_BLEND_BLUE
- REG_A5XX_RB_BLEND_BLUE_F32
- REG_A5XX_RB_BLEND_CNTL
- REG_A5XX_RB_BLEND_GREEN
- REG_A5XX_RB_BLEND_GREEN_F32
- REG_A5XX_RB_BLEND_RED
- REG_A5XX_RB_BLEND_RED_F32
- REG_A5XX_RB_BLIT_CNTL
- REG_A5XX_RB_BLIT_DST_ARRAY_PITCH
- REG_A5XX_RB_BLIT_DST_HI
- REG_A5XX_RB_BLIT_DST_LO
- REG_A5XX_RB_BLIT_DST_PITCH
- REG_A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH
- REG_A5XX_RB_BLIT_FLAG_DST_HI
- REG_A5XX_RB_BLIT_FLAG_DST_LO
- REG_A5XX_RB_BLIT_FLAG_DST_PITCH
- REG_A5XX_RB_CCU_CNTL
- REG_A5XX_RB_CLEAR_CNTL
- REG_A5XX_RB_CLEAR_COLOR_DW0
- REG_A5XX_RB_CLEAR_COLOR_DW1
- REG_A5XX_RB_CLEAR_COLOR_DW2
- REG_A5XX_RB_CLEAR_COLOR_DW3
- REG_A5XX_RB_CNTL
- REG_A5XX_RB_DBG_ECO_CNTL
- REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH
- REG_A5XX_RB_DEPTH_BUFFER_BASE_HI
- REG_A5XX_RB_DEPTH_BUFFER_BASE_LO
- REG_A5XX_RB_DEPTH_BUFFER_INFO
- REG_A5XX_RB_DEPTH_BUFFER_PITCH
- REG_A5XX_RB_DEPTH_CNTL
- REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_HI
- REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO
- REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH
- REG_A5XX_RB_DEPTH_PLANE_CNTL
- REG_A5XX_RB_DEST_MSAA_CNTL
- REG_A5XX_RB_FS_OUTPUT_CNTL
- REG_A5XX_RB_MODE_CNTL
- REG_A5XX_RB_MRT
- REG_A5XX_RB_MRT_ARRAY_PITCH
- REG_A5XX_RB_MRT_BASE_HI
- REG_A5XX_RB_MRT_BASE_LO
- REG_A5XX_RB_MRT_BLEND_CONTROL
- REG_A5XX_RB_MRT_BUF_INFO
- REG_A5XX_RB_MRT_CONTROL
- REG_A5XX_RB_MRT_FLAG_BUFFER
- REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI
- REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO
- REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH
- REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH
- REG_A5XX_RB_MRT_PITCH
- REG_A5XX_RB_PERFCTR_CCU_SEL_0
- REG_A5XX_RB_PERFCTR_CCU_SEL_1
- REG_A5XX_RB_PERFCTR_CCU_SEL_2
- REG_A5XX_RB_PERFCTR_CCU_SEL_3
- REG_A5XX_RB_PERFCTR_CMP_SEL_0
- REG_A5XX_RB_PERFCTR_CMP_SEL_1
- REG_A5XX_RB_PERFCTR_CMP_SEL_2
- REG_A5XX_RB_PERFCTR_CMP_SEL_3
- REG_A5XX_RB_PERFCTR_RB_SEL_0
- REG_A5XX_RB_PERFCTR_RB_SEL_1
- REG_A5XX_RB_PERFCTR_RB_SEL_2
- REG_A5XX_RB_PERFCTR_RB_SEL_3
- REG_A5XX_RB_PERFCTR_RB_SEL_4
- REG_A5XX_RB_PERFCTR_RB_SEL_5
- REG_A5XX_RB_PERFCTR_RB_SEL_6
- REG_A5XX_RB_PERFCTR_RB_SEL_7
- REG_A5XX_RB_POWERCTR_CCU_SEL_0
- REG_A5XX_RB_POWERCTR_CCU_SEL_1
- REG_A5XX_RB_POWERCTR_RB_SEL_0
- REG_A5XX_RB_POWERCTR_RB_SEL_1
- REG_A5XX_RB_POWERCTR_RB_SEL_2
- REG_A5XX_RB_POWERCTR_RB_SEL_3
- REG_A5XX_RB_POWER_COUNTER_0_HI
- REG_A5XX_RB_POWER_COUNTER_0_LO
- REG_A5XX_RB_POWER_COUNTER_1_HI
- REG_A5XX_RB_POWER_COUNTER_1_LO
- REG_A5XX_RB_POWER_COUNTER_2_HI
- REG_A5XX_RB_POWER_COUNTER_2_LO
- REG_A5XX_RB_POWER_COUNTER_3_HI
- REG_A5XX_RB_POWER_COUNTER_3_LO
- REG_A5XX_RB_RAS_MSAA_CNTL
- REG_A5XX_RB_RENDER_CNTL
- REG_A5XX_RB_RENDER_COMPONENTS
- REG_A5XX_RB_RENDER_CONTROL0
- REG_A5XX_RB_RENDER_CONTROL1
- REG_A5XX_RB_RESOLVE_CNTL_1
- REG_A5XX_RB_RESOLVE_CNTL_2
- REG_A5XX_RB_RESOLVE_CNTL_3
- REG_A5XX_RB_SAMPLE_COUNT_ADDR_HI
- REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO
- REG_A5XX_RB_SAMPLE_COUNT_CONTROL
- REG_A5XX_RB_STENCILREFMASK
- REG_A5XX_RB_STENCILREFMASK_BF
- REG_A5XX_RB_STENCIL_ARRAY_PITCH
- REG_A5XX_RB_STENCIL_BASE_HI
- REG_A5XX_RB_STENCIL_BASE_LO
- REG_A5XX_RB_STENCIL_CONTROL
- REG_A5XX_RB_STENCIL_INFO
- REG_A5XX_RB_STENCIL_PITCH
- REG_A5XX_RB_WINDOW_OFFSET
- REG_A5XX_SP_ADDR_MODE_CNTL
- REG_A5XX_SP_BLEND_CNTL
- REG_A5XX_SP_CS_CONFIG
- REG_A5XX_SP_CS_CTRL_REG0
- REG_A5XX_SP_CS_OBJ_START_HI
- REG_A5XX_SP_CS_OBJ_START_LO
- REG_A5XX_SP_DBG_ECO_CNTL
- REG_A5XX_SP_DS_CONFIG
- REG_A5XX_SP_DS_CTRL_REG0
- REG_A5XX_SP_DS_OBJ_START_HI
- REG_A5XX_SP_DS_OBJ_START_LO
- REG_A5XX_SP_FS_CONFIG
- REG_A5XX_SP_FS_CONFIG_MAX_CONST
- REG_A5XX_SP_FS_CTRL_REG0
- REG_A5XX_SP_FS_MRT
- REG_A5XX_SP_FS_MRT_REG
- REG_A5XX_SP_FS_OBJ_START_HI
- REG_A5XX_SP_FS_OBJ_START_LO
- REG_A5XX_SP_FS_OUTPUT
- REG_A5XX_SP_FS_OUTPUT_CNTL
- REG_A5XX_SP_FS_OUTPUT_REG
- REG_A5XX_SP_GS_CONFIG
- REG_A5XX_SP_GS_CTRL_REG0
- REG_A5XX_SP_GS_OBJ_START_HI
- REG_A5XX_SP_GS_OBJ_START_LO
- REG_A5XX_SP_HS_CONFIG
- REG_A5XX_SP_HS_CTRL_REG0
- REG_A5XX_SP_HS_OBJ_START_HI
- REG_A5XX_SP_HS_OBJ_START_LO
- REG_A5XX_SP_MODE_CNTL
- REG_A5XX_SP_PERFCTR_SP_SEL_0
- REG_A5XX_SP_PERFCTR_SP_SEL_1
- REG_A5XX_SP_PERFCTR_SP_SEL_10
- REG_A5XX_SP_PERFCTR_SP_SEL_11
- REG_A5XX_SP_PERFCTR_SP_SEL_2
- REG_A5XX_SP_PERFCTR_SP_SEL_3
- REG_A5XX_SP_PERFCTR_SP_SEL_4
- REG_A5XX_SP_PERFCTR_SP_SEL_5
- REG_A5XX_SP_PERFCTR_SP_SEL_6
- REG_A5XX_SP_PERFCTR_SP_SEL_7
- REG_A5XX_SP_PERFCTR_SP_SEL_8
- REG_A5XX_SP_PERFCTR_SP_SEL_9
- REG_A5XX_SP_POWERCTR_SP_SEL_0
- REG_A5XX_SP_POWERCTR_SP_SEL_1
- REG_A5XX_SP_POWERCTR_SP_SEL_2
- REG_A5XX_SP_POWERCTR_SP_SEL_3
- REG_A5XX_SP_POWER_COUNTER_0_HI
- REG_A5XX_SP_POWER_COUNTER_0_LO
- REG_A5XX_SP_POWER_COUNTER_1_HI
- REG_A5XX_SP_POWER_COUNTER_1_LO
- REG_A5XX_SP_POWER_COUNTER_2_HI
- REG_A5XX_SP_POWER_COUNTER_2_LO
- REG_A5XX_SP_POWER_COUNTER_3_HI
- REG_A5XX_SP_POWER_COUNTER_3_LO
- REG_A5XX_SP_PRIMITIVE_CNTL
- REG_A5XX_SP_SP_CNTL
- REG_A5XX_SP_VS_CONFIG
- REG_A5XX_SP_VS_CONFIG_MAX_CONST
- REG_A5XX_SP_VS_CTRL_REG0
- REG_A5XX_SP_VS_OBJ_START_HI
- REG_A5XX_SP_VS_OBJ_START_LO
- REG_A5XX_SP_VS_OUT
- REG_A5XX_SP_VS_OUT_REG
- REG_A5XX_SP_VS_VPC_DST
- REG_A5XX_SP_VS_VPC_DST_REG
- REG_A5XX_SSBO_0_0
- REG_A5XX_SSBO_0_1
- REG_A5XX_SSBO_0_2
- REG_A5XX_SSBO_0_3
- REG_A5XX_SSBO_1_0
- REG_A5XX_SSBO_1_1
- REG_A5XX_SSBO_2_0
- REG_A5XX_SSBO_2_1
- REG_A5XX_TEX_CONST_0
- REG_A5XX_TEX_CONST_1
- REG_A5XX_TEX_CONST_10
- REG_A5XX_TEX_CONST_11
- REG_A5XX_TEX_CONST_2
- REG_A5XX_TEX_CONST_3
- REG_A5XX_TEX_CONST_4
- REG_A5XX_TEX_CONST_5
- REG_A5XX_TEX_CONST_6
- REG_A5XX_TEX_CONST_7
- REG_A5XX_TEX_CONST_8
- REG_A5XX_TEX_CONST_9
- REG_A5XX_TEX_SAMP_0
- REG_A5XX_TEX_SAMP_1
- REG_A5XX_TEX_SAMP_2
- REG_A5XX_TEX_SAMP_3
- REG_A5XX_TPL1_ADDR_MODE_CNTL
- REG_A5XX_TPL1_CS_TEX_CONST_HI
- REG_A5XX_TPL1_CS_TEX_CONST_LO
- REG_A5XX_TPL1_CS_TEX_COUNT
- REG_A5XX_TPL1_CS_TEX_SAMP_HI
- REG_A5XX_TPL1_CS_TEX_SAMP_LO
- REG_A5XX_TPL1_DS_TEX_CONST_HI
- REG_A5XX_TPL1_DS_TEX_CONST_LO
- REG_A5XX_TPL1_DS_TEX_COUNT
- REG_A5XX_TPL1_DS_TEX_SAMP_HI
- REG_A5XX_TPL1_DS_TEX_SAMP_LO
- REG_A5XX_TPL1_FS_TEX_CONST_HI
- REG_A5XX_TPL1_FS_TEX_CONST_LO
- REG_A5XX_TPL1_FS_TEX_COUNT
- REG_A5XX_TPL1_FS_TEX_SAMP_HI
- REG_A5XX_TPL1_FS_TEX_SAMP_LO
- REG_A5XX_TPL1_GS_TEX_CONST_HI
- REG_A5XX_TPL1_GS_TEX_CONST_LO
- REG_A5XX_TPL1_GS_TEX_COUNT
- REG_A5XX_TPL1_GS_TEX_SAMP_HI
- REG_A5XX_TPL1_GS_TEX_SAMP_LO
- REG_A5XX_TPL1_HS_TEX_CONST_HI
- REG_A5XX_TPL1_HS_TEX_CONST_LO
- REG_A5XX_TPL1_HS_TEX_COUNT
- REG_A5XX_TPL1_HS_TEX_SAMP_HI
- REG_A5XX_TPL1_HS_TEX_SAMP_LO
- REG_A5XX_TPL1_MODE_CNTL
- REG_A5XX_TPL1_PERFCTR_TP_SEL_0
- REG_A5XX_TPL1_PERFCTR_TP_SEL_1
- REG_A5XX_TPL1_PERFCTR_TP_SEL_2
- REG_A5XX_TPL1_PERFCTR_TP_SEL_3
- REG_A5XX_TPL1_PERFCTR_TP_SEL_4
- REG_A5XX_TPL1_PERFCTR_TP_SEL_5
- REG_A5XX_TPL1_PERFCTR_TP_SEL_6
- REG_A5XX_TPL1_PERFCTR_TP_SEL_7
- REG_A5XX_TPL1_POWERCTR_TP_SEL_0
- REG_A5XX_TPL1_POWERCTR_TP_SEL_1
- REG_A5XX_TPL1_POWERCTR_TP_SEL_2
- REG_A5XX_TPL1_POWERCTR_TP_SEL_3
- REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_HI
- REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO
- REG_A5XX_TPL1_TP_DEST_MSAA_CNTL
- REG_A5XX_TPL1_TP_FS_ROTATION_CNTL
- REG_A5XX_TPL1_TP_RAS_MSAA_CNTL
- REG_A5XX_TPL1_VS_TEX_CONST_HI
- REG_A5XX_TPL1_VS_TEX_CONST_LO
- REG_A5XX_TPL1_VS_TEX_COUNT
- REG_A5XX_TPL1_VS_TEX_SAMP_HI
- REG_A5XX_TPL1_VS_TEX_SAMP_LO
- REG_A5XX_TP_POWER_COUNTER_0_HI
- REG_A5XX_TP_POWER_COUNTER_0_LO
- REG_A5XX_TP_POWER_COUNTER_1_HI
- REG_A5XX_TP_POWER_COUNTER_1_LO
- REG_A5XX_TP_POWER_COUNTER_2_HI
- REG_A5XX_TP_POWER_COUNTER_2_LO
- REG_A5XX_TP_POWER_COUNTER_3_HI
- REG_A5XX_TP_POWER_COUNTER_3_LO
- REG_A5XX_UCHE_ADDR_MODE_CNTL
- REG_A5XX_UCHE_CACHE_INVALIDATE
- REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_HI
- REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_LO
- REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_HI
- REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO
- REG_A5XX_UCHE_CACHE_WAYS
- REG_A5XX_UCHE_DBG_ECO_CNTL
- REG_A5XX_UCHE_DBG_ECO_CNTL_2
- REG_A5XX_UCHE_GMEM_RANGE_MAX_HI
- REG_A5XX_UCHE_GMEM_RANGE_MAX_LO
- REG_A5XX_UCHE_GMEM_RANGE_MIN_HI
- REG_A5XX_UCHE_GMEM_RANGE_MIN_LO
- REG_A5XX_UCHE_PERFCTR_UCHE_SEL_0
- REG_A5XX_UCHE_PERFCTR_UCHE_SEL_1
- REG_A5XX_UCHE_PERFCTR_UCHE_SEL_2
- REG_A5XX_UCHE_PERFCTR_UCHE_SEL_3
- REG_A5XX_UCHE_PERFCTR_UCHE_SEL_4
- REG_A5XX_UCHE_PERFCTR_UCHE_SEL_5
- REG_A5XX_UCHE_PERFCTR_UCHE_SEL_6
- REG_A5XX_UCHE_PERFCTR_UCHE_SEL_7
- REG_A5XX_UCHE_POWERCTR_UCHE_SEL_0
- REG_A5XX_UCHE_POWERCTR_UCHE_SEL_1
- REG_A5XX_UCHE_POWERCTR_UCHE_SEL_2
- REG_A5XX_UCHE_POWERCTR_UCHE_SEL_3
- REG_A5XX_UCHE_POWER_COUNTER_0_HI
- REG_A5XX_UCHE_POWER_COUNTER_0_LO
- REG_A5XX_UCHE_POWER_COUNTER_1_HI
- REG_A5XX_UCHE_POWER_COUNTER_1_LO
- REG_A5XX_UCHE_POWER_COUNTER_2_HI
- REG_A5XX_UCHE_POWER_COUNTER_2_LO
- REG_A5XX_UCHE_POWER_COUNTER_3_HI
- REG_A5XX_UCHE_POWER_COUNTER_3_LO
- REG_A5XX_UCHE_SVM_CNTL
- REG_A5XX_UCHE_TRAP_BASE_HI
- REG_A5XX_UCHE_TRAP_BASE_LO
- REG_A5XX_UCHE_TRAP_LOG_HI
- REG_A5XX_UCHE_TRAP_LOG_LO
- REG_A5XX_UCHE_WRITE_THRU_BASE_HI
- REG_A5XX_UCHE_WRITE_THRU_BASE_LO
- REG_A5XX_UNKNOWN_0BC5
- REG_A5XX_UNKNOWN_0BC6
- REG_A5XX_UNKNOWN_2100
- REG_A5XX_UNKNOWN_2180
- REG_A5XX_UNKNOWN_2184
- REG_A5XX_UNKNOWN_E001
- REG_A5XX_UNKNOWN_E004
- REG_A5XX_UNKNOWN_E292
- REG_A5XX_UNKNOWN_E293
- REG_A5XX_UNKNOWN_E29A
- REG_A5XX_UNKNOWN_E389
- REG_A5XX_UNKNOWN_E5AB
- REG_A5XX_UNKNOWN_E5C2
- REG_A5XX_UNKNOWN_E5DB
- REG_A5XX_UNKNOWN_E5F2
- REG_A5XX_UNKNOWN_E602
- REG_A5XX_UNKNOWN_E62B
- REG_A5XX_UNKNOWN_E65B
- REG_A5XX_UNKNOWN_E7C0
- REG_A5XX_UNKNOWN_E7C5
- REG_A5XX_UNKNOWN_E7CA
- REG_A5XX_UNKNOWN_E7CF
- REG_A5XX_UNKNOWN_E7D4
- REG_A5XX_UNKNOWN_E7D9
- REG_A5XX_VBIF_ABIT_SORT
- REG_A5XX_VBIF_ABIT_SORT_CONF
- REG_A5XX_VBIF_CLKON
- REG_A5XX_VBIF_GATE_OFF_WRREQ_EN
- REG_A5XX_VBIF_IN_RD_LIM_CONF0
- REG_A5XX_VBIF_IN_RD_LIM_CONF1
- REG_A5XX_VBIF_PERF_CNT_CLR0
- REG_A5XX_VBIF_PERF_CNT_CLR1
- REG_A5XX_VBIF_PERF_CNT_CLR2
- REG_A5XX_VBIF_PERF_CNT_CLR3
- REG_A5XX_VBIF_PERF_CNT_EN0
- REG_A5XX_VBIF_PERF_CNT_EN1
- REG_A5XX_VBIF_PERF_CNT_EN2
- REG_A5XX_VBIF_PERF_CNT_EN3
- REG_A5XX_VBIF_PERF_CNT_HIGH0
- REG_A5XX_VBIF_PERF_CNT_HIGH1
- REG_A5XX_VBIF_PERF_CNT_HIGH2
- REG_A5XX_VBIF_PERF_CNT_HIGH3
- REG_A5XX_VBIF_PERF_CNT_LOW0
- REG_A5XX_VBIF_PERF_CNT_LOW1
- REG_A5XX_VBIF_PERF_CNT_LOW2
- REG_A5XX_VBIF_PERF_CNT_LOW3
- REG_A5XX_VBIF_PERF_CNT_SEL0
- REG_A5XX_VBIF_PERF_CNT_SEL1
- REG_A5XX_VBIF_PERF_CNT_SEL2
- REG_A5XX_VBIF_PERF_CNT_SEL3
- REG_A5XX_VBIF_PERF_PWR_CNT_EN0
- REG_A5XX_VBIF_PERF_PWR_CNT_EN1
- REG_A5XX_VBIF_PERF_PWR_CNT_EN2
- REG_A5XX_VBIF_PERF_PWR_CNT_HIGH0
- REG_A5XX_VBIF_PERF_PWR_CNT_HIGH1
- REG_A5XX_VBIF_PERF_PWR_CNT_HIGH2
- REG_A5XX_VBIF_PERF_PWR_CNT_LOW0
- REG_A5XX_VBIF_PERF_PWR_CNT_LOW1
- REG_A5XX_VBIF_PERF_PWR_CNT_LOW2
- REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB
- REG_A5XX_VBIF_TEST_BUS1_CTRL0
- REG_A5XX_VBIF_TEST_BUS1_CTRL1
- REG_A5XX_VBIF_TEST_BUS2_CTRL0
- REG_A5XX_VBIF_TEST_BUS2_CTRL1
- REG_A5XX_VBIF_TEST_BUS_OUT
- REG_A5XX_VBIF_TEST_BUS_OUT_CTRL
- REG_A5XX_VBIF_VERSION
- REG_A5XX_VBIF_XIN_HALT_CTRL0
- REG_A5XX_VBIF_XIN_HALT_CTRL1
- REG_A5XX_VFD_ADDR_MODE_CNTL
- REG_A5XX_VFD_CONTROL_0
- REG_A5XX_VFD_CONTROL_1
- REG_A5XX_VFD_CONTROL_2
- REG_A5XX_VFD_CONTROL_3
- REG_A5XX_VFD_CONTROL_4
- REG_A5XX_VFD_CONTROL_5
- REG_A5XX_VFD_DECODE
- REG_A5XX_VFD_DECODE_INSTR
- REG_A5XX_VFD_DECODE_STEP_RATE
- REG_A5XX_VFD_DEST_CNTL
- REG_A5XX_VFD_DEST_CNTL_INSTR
- REG_A5XX_VFD_FETCH
- REG_A5XX_VFD_FETCH_BASE_HI
- REG_A5XX_VFD_FETCH_BASE_LO
- REG_A5XX_VFD_FETCH_SIZE
- REG_A5XX_VFD_FETCH_STRIDE
- REG_A5XX_VFD_INDEX_OFFSET
- REG_A5XX_VFD_INSTANCE_START_OFFSET
- REG_A5XX_VFD_MODE_CNTL
- REG_A5XX_VFD_PERFCTR_VFD_SEL_0
- REG_A5XX_VFD_PERFCTR_VFD_SEL_1
- REG_A5XX_VFD_PERFCTR_VFD_SEL_2
- REG_A5XX_VFD_PERFCTR_VFD_SEL_3
- REG_A5XX_VFD_PERFCTR_VFD_SEL_4
- REG_A5XX_VFD_PERFCTR_VFD_SEL_5
- REG_A5XX_VFD_PERFCTR_VFD_SEL_6
- REG_A5XX_VFD_PERFCTR_VFD_SEL_7
- REG_A5XX_VFD_POWER_CNTL
- REG_A5XX_VPC_ADDR_MODE_CNTL
- REG_A5XX_VPC_CNTL_0
- REG_A5XX_VPC_DBG_ECO_CNTL
- REG_A5XX_VPC_FS_PRIMITIVEID_CNTL
- REG_A5XX_VPC_GS_SIV_CNTL
- REG_A5XX_VPC_MODE_CNTL
- REG_A5XX_VPC_PACK
- REG_A5XX_VPC_PERFCTR_VPC_SEL_0
- REG_A5XX_VPC_PERFCTR_VPC_SEL_1
- REG_A5XX_VPC_PERFCTR_VPC_SEL_2
- REG_A5XX_VPC_PERFCTR_VPC_SEL_3
- REG_A5XX_VPC_SO
- REG_A5XX_VPC_SO_BUFFER_BASE_HI
- REG_A5XX_VPC_SO_BUFFER_BASE_LO
- REG_A5XX_VPC_SO_BUFFER_OFFSET
- REG_A5XX_VPC_SO_BUFFER_SIZE
- REG_A5XX_VPC_SO_BUF_CNTL
- REG_A5XX_VPC_SO_CNTL
- REG_A5XX_VPC_SO_FLUSH_BASE_HI
- REG_A5XX_VPC_SO_FLUSH_BASE_LO
- REG_A5XX_VPC_SO_NCOMP
- REG_A5XX_VPC_SO_OVERRIDE
- REG_A5XX_VPC_SO_PROG
- REG_A5XX_VPC_VAR
- REG_A5XX_VPC_VARYING_INTERP
- REG_A5XX_VPC_VARYING_INTERP_MODE
- REG_A5XX_VPC_VARYING_PS_REPL
- REG_A5XX_VPC_VARYING_PS_REPL_MODE
- REG_A5XX_VPC_VAR_DISABLE
- REG_A5XX_VSC_ADDR_MODE_CNTL
- REG_A5XX_VSC_BIN_SIZE
- REG_A5XX_VSC_PERFCTR_VSC_SEL_0
- REG_A5XX_VSC_PERFCTR_VSC_SEL_1
- REG_A5XX_VSC_PIPE_CONFIG
- REG_A5XX_VSC_PIPE_CONFIG_REG
- REG_A5XX_VSC_PIPE_DATA_ADDRESS
- REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI
- REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO
- REG_A5XX_VSC_PIPE_DATA_LENGTH
- REG_A5XX_VSC_PIPE_DATA_LENGTH_REG
- REG_A5XX_VSC_RESOLVE_CNTL
- REG_A5XX_VSC_SIZE_ADDRESS_HI
- REG_A5XX_VSC_SIZE_ADDRESS_LO
- REG_A6XX_CP_ADDR_MODE_CNTL
- REG_A6XX_CP_AHB_CNTL
- REG_A6XX_CP_ALWAYS_ON_COUNTER_HI
- REG_A6XX_CP_ALWAYS_ON_COUNTER_LO
- REG_A6XX_CP_APERTURE_CNTL_CD
- REG_A6XX_CP_APERTURE_CNTL_HOST
- REG_A6XX_CP_CHICKEN_DBG
- REG_A6XX_CP_CONTEXT_SWITCH_CNTL
- REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI
- REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO
- REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI
- REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO
- REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI
- REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO
- REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI
- REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO
- REG_A6XX_CP_CRASH_DUMP_CNTL
- REG_A6XX_CP_CRASH_DUMP_STATUS
- REG_A6XX_CP_CRASH_SCRIPT_BASE_HI
- REG_A6XX_CP_CRASH_SCRIPT_BASE_LO
- REG_A6XX_CP_DBG_ECO_CNTL
- REG_A6XX_CP_DRAW_STATE_ADDR
- REG_A6XX_CP_DRAW_STATE_DATA
- REG_A6XX_CP_HW_FAULT
- REG_A6XX_CP_IB1_BASE
- REG_A6XX_CP_IB1_BASE_HI
- REG_A6XX_CP_IB1_REM_SIZE
- REG_A6XX_CP_IB2_BASE
- REG_A6XX_CP_IB2_BASE_HI
- REG_A6XX_CP_IB2_REM_SIZE
- REG_A6XX_CP_INTERRUPT_STATUS
- REG_A6XX_CP_MEM_POOL_DBG_ADDR
- REG_A6XX_CP_MEM_POOL_DBG_DATA
- REG_A6XX_CP_MEM_POOL_SIZE
- REG_A6XX_CP_MISC_CNTL
- REG_A6XX_CP_PERFCTR_CP_SEL_0
- REG_A6XX_CP_PERFCTR_CP_SEL_1
- REG_A6XX_CP_PERFCTR_CP_SEL_10
- REG_A6XX_CP_PERFCTR_CP_SEL_11
- REG_A6XX_CP_PERFCTR_CP_SEL_12
- REG_A6XX_CP_PERFCTR_CP_SEL_13
- REG_A6XX_CP_PERFCTR_CP_SEL_2
- REG_A6XX_CP_PERFCTR_CP_SEL_3
- REG_A6XX_CP_PERFCTR_CP_SEL_4
- REG_A6XX_CP_PERFCTR_CP_SEL_5
- REG_A6XX_CP_PERFCTR_CP_SEL_6
- REG_A6XX_CP_PERFCTR_CP_SEL_7
- REG_A6XX_CP_PERFCTR_CP_SEL_8
- REG_A6XX_CP_PERFCTR_CP_SEL_9
- REG_A6XX_CP_PROTECT
- REG_A6XX_CP_PROTECT_CNTL
- REG_A6XX_CP_PROTECT_REG
- REG_A6XX_CP_PROTECT_STATUS
- REG_A6XX_CP_RB_BASE
- REG_A6XX_CP_RB_BASE_HI
- REG_A6XX_CP_RB_CNTL
- REG_A6XX_CP_RB_RPTR
- REG_A6XX_CP_RB_RPTR_ADDR_HI
- REG_A6XX_CP_RB_RPTR_ADDR_LO
- REG_A6XX_CP_RB_WPTR
- REG_A6XX_CP_ROQ_DBG_ADDR
- REG_A6XX_CP_ROQ_DBG_DATA
- REG_A6XX_CP_ROQ_THRESHOLDS_1
- REG_A6XX_CP_ROQ_THRESHOLDS_2
- REG_A6XX_CP_SCRATCH
- REG_A6XX_CP_SCRATCH_REG
- REG_A6XX_CP_SQE_CNTL
- REG_A6XX_CP_SQE_INSTR_BASE_HI
- REG_A6XX_CP_SQE_INSTR_BASE_LO
- REG_A6XX_CP_SQE_STAT_ADDR
- REG_A6XX_CP_SQE_STAT_DATA
- REG_A6XX_CP_SQE_UCODE_DBG_ADDR
- REG_A6XX_CP_SQE_UCODE_DBG_DATA
- REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0
- REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1
- REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM
- REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT
- REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0
- REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1
- REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2
- REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3
- REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0
- REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1
- REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2
- REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3
- REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A
- REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B
- REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C
- REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D
- REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1
- REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2
- REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0
- REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1
- REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0
- REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1
- REG_A6XX_DBGC_CFG_DBGBUS_CNTLM
- REG_A6XX_DBGC_CFG_DBGBUS_CNTLT
- REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0
- REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1
- REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2
- REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3
- REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0
- REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1
- REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2
- REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3
- REG_A6XX_DBGC_CFG_DBGBUS_SEL_A
- REG_A6XX_DBGC_CFG_DBGBUS_SEL_B
- REG_A6XX_DBGC_CFG_DBGBUS_SEL_C
- REG_A6XX_DBGC_CFG_DBGBUS_SEL_D
- REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1
- REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2
- REG_A6XX_GMU_AHB_FENCE_RANGE_0
- REG_A6XX_GMU_AHB_FENCE_RANGE_1
- REG_A6XX_GMU_AHB_FENCE_STATUS
- REG_A6XX_GMU_ALWAYS_ON_COUNTER_H
- REG_A6XX_GMU_ALWAYS_ON_COUNTER_L
- REG_A6XX_GMU_AO_AHB_FENCE_CTRL
- REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR
- REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK
- REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS
- REG_A6XX_GMU_AO_INTERRUPT_EN
- REG_A6XX_GMU_AO_SPARE_CNTL
- REG_A6XX_GMU_BOOT_KMD_LM_HANDSHAKE
- REG_A6XX_GMU_BOOT_SLUMBER_OPTION
- REG_A6XX_GMU_CM3_BOOT_CONFIG
- REG_A6XX_GMU_CM3_CFG
- REG_A6XX_GMU_CM3_DTCM_START
- REG_A6XX_GMU_CM3_FW_BUSY
- REG_A6XX_GMU_CM3_FW_INIT_RESULT
- REG_A6XX_GMU_CM3_ITCM_START
- REG_A6XX_GMU_CM3_SYSRESET
- REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE
- REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0
- REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1
- REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H
- REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L
- REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H
- REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L
- REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H
- REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L
- REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H
- REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L
- REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H
- REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L
- REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H
- REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L
- REG_A6XX_GMU_DCVS_ACK_OPTION
- REG_A6XX_GMU_DCVS_BW_SETTING
- REG_A6XX_GMU_DCVS_PERF_SETTING
- REG_A6XX_GMU_DCVS_RETURN
- REG_A6XX_GMU_GENERAL_1
- REG_A6XX_GMU_GENERAL_7
- REG_A6XX_GMU_GMU2HOST_INTR_CLR
- REG_A6XX_GMU_GMU2HOST_INTR_INFO
- REG_A6XX_GMU_GMU2HOST_INTR_MASK
- REG_A6XX_GMU_GMU2HOST_INTR_SET
- REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE
- REG_A6XX_GMU_GPU_NAP_CTRL
- REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL
- REG_A6XX_GMU_GX_VOTE_IDX
- REG_A6XX_GMU_HFI_CTRL_INIT
- REG_A6XX_GMU_HFI_CTRL_STATUS
- REG_A6XX_GMU_HFI_MMAP_ADDR
- REG_A6XX_GMU_HFI_QTBL_ADDR
- REG_A6XX_GMU_HFI_QTBL_INFO
- REG_A6XX_GMU_HFI_SFR_ADDR
- REG_A6XX_GMU_HFI_VERSION_INFO
- REG_A6XX_GMU_HOST2GMU_INTR_CLR
- REG_A6XX_GMU_HOST2GMU_INTR_EN_0
- REG_A6XX_GMU_HOST2GMU_INTR_EN_1
- REG_A6XX_GMU_HOST2GMU_INTR_EN_2
- REG_A6XX_GMU_HOST2GMU_INTR_EN_3
- REG_A6XX_GMU_HOST2GMU_INTR_INFO_0
- REG_A6XX_GMU_HOST2GMU_INTR_INFO_1
- REG_A6XX_GMU_HOST2GMU_INTR_INFO_2
- REG_A6XX_GMU_HOST2GMU_INTR_INFO_3
- REG_A6XX_GMU_HOST2GMU_INTR_RAW_INFO
- REG_A6XX_GMU_HOST2GMU_INTR_SET
- REG_A6XX_GMU_ISENSE_CTRL
- REG_A6XX_GMU_LLM_GLM_SLEEP_CTRL
- REG_A6XX_GMU_LLM_GLM_SLEEP_STATUS
- REG_A6XX_GMU_MX_VOTE_IDX
- REG_A6XX_GMU_NMI_CONTROL_STATUS
- REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL
- REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST
- REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST
- REG_A6XX_GMU_RBBM_INT_UNMASKED_STATUS
- REG_A6XX_GMU_RPMH_CTRL
- REG_A6XX_GMU_RPMH_HYST_CTRL
- REG_A6XX_GMU_RSCC_CONTROL_ACK
- REG_A6XX_GMU_RSCC_CONTROL_REQ
- REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS
- REG_A6XX_GMU_SYS_BUS_CONFIG
- REG_A6XX_GPU_CC_GX_DOMAIN_MISC
- REG_A6XX_GPU_CC_GX_GDSCR
- REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL1
- REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL2
- REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL3
- REG_A6XX_GPU_CS_AMP_CALIBRATION_DONE
- REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_0
- REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_2
- REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_4
- REG_A6XX_GPU_CS_AMP_PERIOD_CTRL
- REG_A6XX_GPU_CS_A_SENSOR_CTRL_0
- REG_A6XX_GPU_CS_A_SENSOR_CTRL_2
- REG_A6XX_GPU_CS_ENABLE_REG
- REG_A6XX_GPU_CS_SENSOR_GENERAL_STATUS
- REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL
- REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL
- REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL
- REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK
- REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS
- REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2
- REG_A6XX_GPU_GMU_CX_GMU_ISENSE_CTRL
- REG_A6XX_GPU_GMU_CX_GMU_PWR_THRESHOLD
- REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE
- REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL
- REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0
- REG_A6XX_GRAS_2D_BLIT_CNTL
- REG_A6XX_GRAS_2D_BLIT_INFO
- REG_A6XX_GRAS_2D_DST_BR
- REG_A6XX_GRAS_2D_DST_TL
- REG_A6XX_GRAS_2D_SRC_BR_X
- REG_A6XX_GRAS_2D_SRC_BR_Y
- REG_A6XX_GRAS_2D_SRC_TL_X
- REG_A6XX_GRAS_2D_SRC_TL_Y
- REG_A6XX_GRAS_ADDR_MODE_CNTL
- REG_A6XX_GRAS_BIN_CONTROL
- REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ
- REG_A6XX_GRAS_CL_VPORT_XOFFSET_0
- REG_A6XX_GRAS_CL_VPORT_XSCALE_0
- REG_A6XX_GRAS_CL_VPORT_YOFFSET_0
- REG_A6XX_GRAS_CL_VPORT_YSCALE_0
- REG_A6XX_GRAS_CL_VPORT_ZOFFSET_0
- REG_A6XX_GRAS_CL_VPORT_ZSCALE_0
- REG_A6XX_GRAS_CNTL
- REG_A6XX_GRAS_DEST_MSAA_CNTL
- REG_A6XX_GRAS_LRZ_BUFFER_BASE_HI
- REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO
- REG_A6XX_GRAS_LRZ_BUFFER_PITCH
- REG_A6XX_GRAS_LRZ_CNTL
- REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI
- REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO
- REG_A6XX_GRAS_PERFCTR_LRZ_SEL_0
- REG_A6XX_GRAS_PERFCTR_LRZ_SEL_1
- REG_A6XX_GRAS_PERFCTR_LRZ_SEL_2
- REG_A6XX_GRAS_PERFCTR_LRZ_SEL_3
- REG_A6XX_GRAS_PERFCTR_RAS_SEL_0
- REG_A6XX_GRAS_PERFCTR_RAS_SEL_1
- REG_A6XX_GRAS_PERFCTR_RAS_SEL_2
- REG_A6XX_GRAS_PERFCTR_RAS_SEL_3
- REG_A6XX_GRAS_PERFCTR_TSE_SEL_0
- REG_A6XX_GRAS_PERFCTR_TSE_SEL_1
- REG_A6XX_GRAS_PERFCTR_TSE_SEL_2
- REG_A6XX_GRAS_PERFCTR_TSE_SEL_3
- REG_A6XX_GRAS_RAS_MSAA_CNTL
- REG_A6XX_GRAS_RESOLVE_CNTL_1
- REG_A6XX_GRAS_RESOLVE_CNTL_2
- REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0
- REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0
- REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0
- REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0
- REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR
- REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL
- REG_A6XX_GRAS_SU_CNTL
- REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO
- REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL
- REG_A6XX_GRAS_SU_POINT_MINMAX
- REG_A6XX_GRAS_SU_POINT_SIZE
- REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET
- REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP
- REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE
- REG_A6XX_GRAS_UNKNOWN_8000
- REG_A6XX_GRAS_UNKNOWN_8001
- REG_A6XX_GRAS_UNKNOWN_8004
- REG_A6XX_GRAS_UNKNOWN_8099
- REG_A6XX_GRAS_UNKNOWN_809B
- REG_A6XX_GRAS_UNKNOWN_80A0
- REG_A6XX_GRAS_UNKNOWN_80A4
- REG_A6XX_GRAS_UNKNOWN_80A5
- REG_A6XX_GRAS_UNKNOWN_80A6
- REG_A6XX_GRAS_UNKNOWN_80AF
- REG_A6XX_GRAS_UNKNOWN_8101
- REG_A6XX_GRAS_UNKNOWN_8109
- REG_A6XX_GRAS_UNKNOWN_8110
- REG_A6XX_GRAS_UNKNOWN_8600
- REG_A6XX_HLSQ_ADDR_MODE_CNTL
- REG_A6XX_HLSQ_CONTROL_1_REG
- REG_A6XX_HLSQ_CONTROL_2_REG
- REG_A6XX_HLSQ_CONTROL_3_REG
- REG_A6XX_HLSQ_CONTROL_4_REG
- REG_A6XX_HLSQ_CONTROL_5_REG
- REG_A6XX_HLSQ_CS_CNTL_0
- REG_A6XX_HLSQ_CS_KERNEL_GROUP_X
- REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y
- REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z
- REG_A6XX_HLSQ_CS_NDRANGE_0
- REG_A6XX_HLSQ_CS_NDRANGE_1
- REG_A6XX_HLSQ_CS_NDRANGE_2
- REG_A6XX_HLSQ_CS_NDRANGE_3
- REG_A6XX_HLSQ_CS_NDRANGE_4
- REG_A6XX_HLSQ_CS_NDRANGE_5
- REG_A6XX_HLSQ_CS_NDRANGE_6
- REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE
- REG_A6XX_HLSQ_DBG_READ_SEL
- REG_A6XX_HLSQ_DS_CNTL
- REG_A6XX_HLSQ_FS_CNTL
- REG_A6XX_HLSQ_GS_CNTL
- REG_A6XX_HLSQ_HS_CNTL
- REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_0
- REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_1
- REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_2
- REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_3
- REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_4
- REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL_5
- REG_A6XX_HLSQ_UNKNOWN_B980
- REG_A6XX_HLSQ_UNKNOWN_BB11
- REG_A6XX_HLSQ_UNKNOWN_BE00
- REG_A6XX_HLSQ_UNKNOWN_BE01
- REG_A6XX_HLSQ_UNKNOWN_BE04
- REG_A6XX_HLSQ_UPDATE_CNTL
- REG_A6XX_HLSQ_VS_CNTL
- REG_A6XX_PC_ADDR_MODE_CNTL
- REG_A6XX_PC_DBG_ECO_CNTL
- REG_A6XX_PC_MODE_CNTL
- REG_A6XX_PC_PERFCTR_PC_SEL_0
- REG_A6XX_PC_PERFCTR_PC_SEL_1
- REG_A6XX_PC_PERFCTR_PC_SEL_2
- REG_A6XX_PC_PERFCTR_PC_SEL_3
- REG_A6XX_PC_PERFCTR_PC_SEL_4
- REG_A6XX_PC_PERFCTR_PC_SEL_5
- REG_A6XX_PC_PERFCTR_PC_SEL_6
- REG_A6XX_PC_PERFCTR_PC_SEL_7
- REG_A6XX_PC_PRIMITIVE_CNTL_0
- REG_A6XX_PC_PRIMITIVE_CNTL_1
- REG_A6XX_PC_RESTART_INDEX
- REG_A6XX_PC_TESSFACTOR_ADDR_HI
- REG_A6XX_PC_TESSFACTOR_ADDR_LO
- REG_A6XX_PC_UNKNOWN_9801
- REG_A6XX_PC_UNKNOWN_9805
- REG_A6XX_PC_UNKNOWN_9806
- REG_A6XX_PC_UNKNOWN_9980
- REG_A6XX_PC_UNKNOWN_9981
- REG_A6XX_PC_UNKNOWN_9990
- REG_A6XX_PC_UNKNOWN_9B06
- REG_A6XX_PC_UNKNOWN_9B07
- REG_A6XX_PC_UNKNOWN_9E72
- REG_A6XX_PDC_GPU_ENABLE_PDC
- REG_A6XX_PDC_GPU_SEQ_MEM_0
- REG_A6XX_PDC_GPU_SEQ_START_ADDR
- REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR
- REG_A6XX_PDC_GPU_TCS0_CMD0_DATA
- REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID
- REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK
- REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK
- REG_A6XX_PDC_GPU_TCS0_CONTROL
- REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR
- REG_A6XX_PDC_GPU_TCS1_CMD0_DATA
- REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID
- REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK
- REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK
- REG_A6XX_PDC_GPU_TCS1_CONTROL
- REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR
- REG_A6XX_PDC_GPU_TCS2_CMD0_DATA
- REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID
- REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK
- REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK
- REG_A6XX_PDC_GPU_TCS2_CONTROL
- REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR
- REG_A6XX_PDC_GPU_TCS3_CMD0_DATA
- REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID
- REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK
- REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK
- REG_A6XX_PDC_GPU_TCS3_CONTROL
- REG_A6XX_RBBM_BLOCK_SW_RESET_CMD
- REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2
- REG_A6XX_RBBM_CLOCK_CNTL
- REG_A6XX_RBBM_CLOCK_CNTL2_RAC
- REG_A6XX_RBBM_CLOCK_CNTL2_RB0
- REG_A6XX_RBBM_CLOCK_CNTL2_RB1
- REG_A6XX_RBBM_CLOCK_CNTL2_RB2
- REG_A6XX_RBBM_CLOCK_CNTL2_RB3
- REG_A6XX_RBBM_CLOCK_CNTL2_SP0
- REG_A6XX_RBBM_CLOCK_CNTL2_SP1
- REG_A6XX_RBBM_CLOCK_CNTL2_SP2
- REG_A6XX_RBBM_CLOCK_CNTL2_SP3
- REG_A6XX_RBBM_CLOCK_CNTL2_TP0
- REG_A6XX_RBBM_CLOCK_CNTL2_TP1
- REG_A6XX_RBBM_CLOCK_CNTL2_TP2
- REG_A6XX_RBBM_CLOCK_CNTL2_TP3
- REG_A6XX_RBBM_CLOCK_CNTL2_UCHE
- REG_A6XX_RBBM_CLOCK_CNTL3_TP0
- REG_A6XX_RBBM_CLOCK_CNTL3_TP1
- REG_A6XX_RBBM_CLOCK_CNTL3_TP2
- REG_A6XX_RBBM_CLOCK_CNTL3_TP3
- REG_A6XX_RBBM_CLOCK_CNTL3_UCHE
- REG_A6XX_RBBM_CLOCK_CNTL4_TP0
- REG_A6XX_RBBM_CLOCK_CNTL4_TP1
- REG_A6XX_RBBM_CLOCK_CNTL4_TP2
- REG_A6XX_RBBM_CLOCK_CNTL4_TP3
- REG_A6XX_RBBM_CLOCK_CNTL4_UCHE
- REG_A6XX_RBBM_CLOCK_CNTL_CCU0
- REG_A6XX_RBBM_CLOCK_CNTL_CCU1
- REG_A6XX_RBBM_CLOCK_CNTL_CCU2
- REG_A6XX_RBBM_CLOCK_CNTL_CCU3
- REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX
- REG_A6XX_RBBM_CLOCK_CNTL_RAC
- REG_A6XX_RBBM_CLOCK_CNTL_RB0
- REG_A6XX_RBBM_CLOCK_CNTL_RB1
- REG_A6XX_RBBM_CLOCK_CNTL_RB2
- REG_A6XX_RBBM_CLOCK_CNTL_RB3
- REG_A6XX_RBBM_CLOCK_CNTL_SP0
- REG_A6XX_RBBM_CLOCK_CNTL_SP1
- REG_A6XX_RBBM_CLOCK_CNTL_SP2
- REG_A6XX_RBBM_CLOCK_CNTL_SP3
- REG_A6XX_RBBM_CLOCK_CNTL_TP0
- REG_A6XX_RBBM_CLOCK_CNTL_TP1
- REG_A6XX_RBBM_CLOCK_CNTL_TP2
- REG_A6XX_RBBM_CLOCK_CNTL_TP3
- REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM
- REG_A6XX_RBBM_CLOCK_CNTL_UCHE
- REG_A6XX_RBBM_CLOCK_DELAY2_TP0
- REG_A6XX_RBBM_CLOCK_DELAY2_TP1
- REG_A6XX_RBBM_CLOCK_DELAY2_TP2
- REG_A6XX_RBBM_CLOCK_DELAY2_TP3
- REG_A6XX_RBBM_CLOCK_DELAY3_TP0
- REG_A6XX_RBBM_CLOCK_DELAY3_TP1
- REG_A6XX_RBBM_CLOCK_DELAY3_TP2
- REG_A6XX_RBBM_CLOCK_DELAY3_TP3
- REG_A6XX_RBBM_CLOCK_DELAY4_TP0
- REG_A6XX_RBBM_CLOCK_DELAY4_TP1
- REG_A6XX_RBBM_CLOCK_DELAY4_TP2
- REG_A6XX_RBBM_CLOCK_DELAY4_TP3
- REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX
- REG_A6XX_RBBM_CLOCK_DELAY_GPC
- REG_A6XX_RBBM_CLOCK_DELAY_HLSQ
- REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2
- REG_A6XX_RBBM_CLOCK_DELAY_RAC
- REG_A6XX_RBBM_CLOCK_DELAY_SP0
- REG_A6XX_RBBM_CLOCK_DELAY_SP1
- REG_A6XX_RBBM_CLOCK_DELAY_SP2
- REG_A6XX_RBBM_CLOCK_DELAY_SP3
- REG_A6XX_RBBM_CLOCK_DELAY_TP0
- REG_A6XX_RBBM_CLOCK_DELAY_TP1
- REG_A6XX_RBBM_CLOCK_DELAY_TP2
- REG_A6XX_RBBM_CLOCK_DELAY_TP3
- REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM
- REG_A6XX_RBBM_CLOCK_DELAY_UCHE
- REG_A6XX_RBBM_CLOCK_DELAY_VFD
- REG_A6XX_RBBM_CLOCK_HYST2_TP0
- REG_A6XX_RBBM_CLOCK_HYST2_TP1
- REG_A6XX_RBBM_CLOCK_HYST2_TP2
- REG_A6XX_RBBM_CLOCK_HYST2_TP3
- REG_A6XX_RBBM_CLOCK_HYST3_TP0
- REG_A6XX_RBBM_CLOCK_HYST3_TP1
- REG_A6XX_RBBM_CLOCK_HYST3_TP2
- REG_A6XX_RBBM_CLOCK_HYST3_TP3
- REG_A6XX_RBBM_CLOCK_HYST4_TP0
- REG_A6XX_RBBM_CLOCK_HYST4_TP1
- REG_A6XX_RBBM_CLOCK_HYST4_TP2
- REG_A6XX_RBBM_CLOCK_HYST4_TP3
- REG_A6XX_RBBM_CLOCK_HYST_GMU_GX
- REG_A6XX_RBBM_CLOCK_HYST_GPC
- REG_A6XX_RBBM_CLOCK_HYST_RAC
- REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0
- REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1
- REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2
- REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3
- REG_A6XX_RBBM_CLOCK_HYST_SP0
- REG_A6XX_RBBM_CLOCK_HYST_SP1
- REG_A6XX_RBBM_CLOCK_HYST_SP2
- REG_A6XX_RBBM_CLOCK_HYST_SP3
- REG_A6XX_RBBM_CLOCK_HYST_TP0
- REG_A6XX_RBBM_CLOCK_HYST_TP1
- REG_A6XX_RBBM_CLOCK_HYST_TP2
- REG_A6XX_RBBM_CLOCK_HYST_TP3
- REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM
- REG_A6XX_RBBM_CLOCK_HYST_UCHE
- REG_A6XX_RBBM_CLOCK_HYST_VFD
- REG_A6XX_RBBM_CLOCK_MODE_GPC
- REG_A6XX_RBBM_CLOCK_MODE_HLSQ
- REG_A6XX_RBBM_CLOCK_MODE_VFD
- REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL
- REG_A6XX_RBBM_INT_0_MASK
- REG_A6XX_RBBM_INT_0_STATUS
- REG_A6XX_RBBM_INT_CLEAR_CMD
- REG_A6XX_RBBM_ISDB_CNT
- REG_A6XX_RBBM_PERFCTR_CCU_0_HI
- REG_A6XX_RBBM_PERFCTR_CCU_0_LO
- REG_A6XX_RBBM_PERFCTR_CCU_1_HI
- REG_A6XX_RBBM_PERFCTR_CCU_1_LO
- REG_A6XX_RBBM_PERFCTR_CCU_2_HI
- REG_A6XX_RBBM_PERFCTR_CCU_2_LO
- REG_A6XX_RBBM_PERFCTR_CCU_3_HI
- REG_A6XX_RBBM_PERFCTR_CCU_3_LO
- REG_A6XX_RBBM_PERFCTR_CCU_4_HI
- REG_A6XX_RBBM_PERFCTR_CCU_4_LO
- REG_A6XX_RBBM_PERFCTR_CMP_0_HI
- REG_A6XX_RBBM_PERFCTR_CMP_0_LO
- REG_A6XX_RBBM_PERFCTR_CMP_1_HI
- REG_A6XX_RBBM_PERFCTR_CMP_1_LO
- REG_A6XX_RBBM_PERFCTR_CMP_2_HI
- REG_A6XX_RBBM_PERFCTR_CMP_2_LO
- REG_A6XX_RBBM_PERFCTR_CMP_3_HI
- REG_A6XX_RBBM_PERFCTR_CMP_3_LO
- REG_A6XX_RBBM_PERFCTR_CNTL
- REG_A6XX_RBBM_PERFCTR_CP_0_HI
- REG_A6XX_RBBM_PERFCTR_CP_0_LO
- REG_A6XX_RBBM_PERFCTR_CP_10_HI
- REG_A6XX_RBBM_PERFCTR_CP_10_LO
- REG_A6XX_RBBM_PERFCTR_CP_11_HI
- REG_A6XX_RBBM_PERFCTR_CP_11_LO
- REG_A6XX_RBBM_PERFCTR_CP_12_HI
- REG_A6XX_RBBM_PERFCTR_CP_12_LO
- REG_A6XX_RBBM_PERFCTR_CP_13_HI
- REG_A6XX_RBBM_PERFCTR_CP_13_LO
- REG_A6XX_RBBM_PERFCTR_CP_1_HI
- REG_A6XX_RBBM_PERFCTR_CP_1_LO
- REG_A6XX_RBBM_PERFCTR_CP_2_HI
- REG_A6XX_RBBM_PERFCTR_CP_2_LO
- REG_A6XX_RBBM_PERFCTR_CP_3_HI
- REG_A6XX_RBBM_PERFCTR_CP_3_LO
- REG_A6XX_RBBM_PERFCTR_CP_4_HI
- REG_A6XX_RBBM_PERFCTR_CP_4_LO
- REG_A6XX_RBBM_PERFCTR_CP_5_HI
- REG_A6XX_RBBM_PERFCTR_CP_5_LO
- REG_A6XX_RBBM_PERFCTR_CP_6_HI
- REG_A6XX_RBBM_PERFCTR_CP_6_LO
- REG_A6XX_RBBM_PERFCTR_CP_7_HI
- REG_A6XX_RBBM_PERFCTR_CP_7_LO
- REG_A6XX_RBBM_PERFCTR_CP_8_HI
- REG_A6XX_RBBM_PERFCTR_CP_8_LO
- REG_A6XX_RBBM_PERFCTR_CP_9_HI
- REG_A6XX_RBBM_PERFCTR_CP_9_LO
- REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED
- REG_A6XX_RBBM_PERFCTR_HLSQ_0_HI
- REG_A6XX_RBBM_PERFCTR_HLSQ_0_LO
- REG_A6XX_RBBM_PERFCTR_HLSQ_1_HI
- REG_A6XX_RBBM_PERFCTR_HLSQ_1_LO
- REG_A6XX_RBBM_PERFCTR_HLSQ_2_HI
- REG_A6XX_RBBM_PERFCTR_HLSQ_2_LO
- REG_A6XX_RBBM_PERFCTR_HLSQ_3_HI
- REG_A6XX_RBBM_PERFCTR_HLSQ_3_LO
- REG_A6XX_RBBM_PERFCTR_HLSQ_4_HI
- REG_A6XX_RBBM_PERFCTR_HLSQ_4_LO
- REG_A6XX_RBBM_PERFCTR_HLSQ_5_HI
- REG_A6XX_RBBM_PERFCTR_HLSQ_5_LO
- REG_A6XX_RBBM_PERFCTR_LOAD_CMD0
- REG_A6XX_RBBM_PERFCTR_LOAD_CMD1
- REG_A6XX_RBBM_PERFCTR_LOAD_CMD2
- REG_A6XX_RBBM_PERFCTR_LOAD_CMD3
- REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI
- REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO
- REG_A6XX_RBBM_PERFCTR_LRZ_0_HI
- REG_A6XX_RBBM_PERFCTR_LRZ_0_LO
- REG_A6XX_RBBM_PERFCTR_LRZ_1_HI
- REG_A6XX_RBBM_PERFCTR_LRZ_1_LO
- REG_A6XX_RBBM_PERFCTR_LRZ_2_HI
- REG_A6XX_RBBM_PERFCTR_LRZ_2_LO
- REG_A6XX_RBBM_PERFCTR_LRZ_3_HI
- REG_A6XX_RBBM_PERFCTR_LRZ_3_LO
- REG_A6XX_RBBM_PERFCTR_PC_0_HI
- REG_A6XX_RBBM_PERFCTR_PC_0_LO
- REG_A6XX_RBBM_PERFCTR_PC_1_HI
- REG_A6XX_RBBM_PERFCTR_PC_1_LO
- REG_A6XX_RBBM_PERFCTR_PC_2_HI
- REG_A6XX_RBBM_PERFCTR_PC_2_LO
- REG_A6XX_RBBM_PERFCTR_PC_3_HI
- REG_A6XX_RBBM_PERFCTR_PC_3_LO
- REG_A6XX_RBBM_PERFCTR_PC_4_HI
- REG_A6XX_RBBM_PERFCTR_PC_4_LO
- REG_A6XX_RBBM_PERFCTR_PC_5_HI
- REG_A6XX_RBBM_PERFCTR_PC_5_LO
- REG_A6XX_RBBM_PERFCTR_PC_6_HI
- REG_A6XX_RBBM_PERFCTR_PC_6_LO
- REG_A6XX_RBBM_PERFCTR_PC_7_HI
- REG_A6XX_RBBM_PERFCTR_PC_7_LO
- REG_A6XX_RBBM_PERFCTR_RAS_0_HI
- REG_A6XX_RBBM_PERFCTR_RAS_0_LO
- REG_A6XX_RBBM_PERFCTR_RAS_1_HI
- REG_A6XX_RBBM_PERFCTR_RAS_1_LO
- REG_A6XX_RBBM_PERFCTR_RAS_2_HI
- REG_A6XX_RBBM_PERFCTR_RAS_2_LO
- REG_A6XX_RBBM_PERFCTR_RAS_3_HI
- REG_A6XX_RBBM_PERFCTR_RAS_3_LO
- REG_A6XX_RBBM_PERFCTR_RBBM_0_HI
- REG_A6XX_RBBM_PERFCTR_RBBM_0_LO
- REG_A6XX_RBBM_PERFCTR_RBBM_1_HI
- REG_A6XX_RBBM_PERFCTR_RBBM_1_LO
- REG_A6XX_RBBM_PERFCTR_RBBM_2_HI
- REG_A6XX_RBBM_PERFCTR_RBBM_2_LO
- REG_A6XX_RBBM_PERFCTR_RBBM_3_HI
- REG_A6XX_RBBM_PERFCTR_RBBM_3_LO
- REG_A6XX_RBBM_PERFCTR_RBBM_SEL_0
- REG_A6XX_RBBM_PERFCTR_RBBM_SEL_1
- REG_A6XX_RBBM_PERFCTR_RBBM_SEL_2
- REG_A6XX_RBBM_PERFCTR_RBBM_SEL_3
- REG_A6XX_RBBM_PERFCTR_RB_0_HI
- REG_A6XX_RBBM_PERFCTR_RB_0_LO
- REG_A6XX_RBBM_PERFCTR_RB_1_HI
- REG_A6XX_RBBM_PERFCTR_RB_1_LO
- REG_A6XX_RBBM_PERFCTR_RB_2_HI
- REG_A6XX_RBBM_PERFCTR_RB_2_LO
- REG_A6XX_RBBM_PERFCTR_RB_3_HI
- REG_A6XX_RBBM_PERFCTR_RB_3_LO
- REG_A6XX_RBBM_PERFCTR_RB_4_HI
- REG_A6XX_RBBM_PERFCTR_RB_4_LO
- REG_A6XX_RBBM_PERFCTR_RB_5_HI
- REG_A6XX_RBBM_PERFCTR_RB_5_LO
- REG_A6XX_RBBM_PERFCTR_RB_6_HI
- REG_A6XX_RBBM_PERFCTR_RB_6_LO
- REG_A6XX_RBBM_PERFCTR_RB_7_HI
- REG_A6XX_RBBM_PERFCTR_RB_7_LO
- REG_A6XX_RBBM_PERFCTR_SP_0_HI
- REG_A6XX_RBBM_PERFCTR_SP_0_LO
- REG_A6XX_RBBM_PERFCTR_SP_10_HI
- REG_A6XX_RBBM_PERFCTR_SP_10_LO
- REG_A6XX_RBBM_PERFCTR_SP_11_HI
- REG_A6XX_RBBM_PERFCTR_SP_11_LO
- REG_A6XX_RBBM_PERFCTR_SP_12_HI
- REG_A6XX_RBBM_PERFCTR_SP_12_LO
- REG_A6XX_RBBM_PERFCTR_SP_13_HI
- REG_A6XX_RBBM_PERFCTR_SP_13_LO
- REG_A6XX_RBBM_PERFCTR_SP_14_HI
- REG_A6XX_RBBM_PERFCTR_SP_14_LO
- REG_A6XX_RBBM_PERFCTR_SP_15_HI
- REG_A6XX_RBBM_PERFCTR_SP_15_LO
- REG_A6XX_RBBM_PERFCTR_SP_16_HI
- REG_A6XX_RBBM_PERFCTR_SP_16_LO
- REG_A6XX_RBBM_PERFCTR_SP_17_HI
- REG_A6XX_RBBM_PERFCTR_SP_17_LO
- REG_A6XX_RBBM_PERFCTR_SP_18_HI
- REG_A6XX_RBBM_PERFCTR_SP_18_LO
- REG_A6XX_RBBM_PERFCTR_SP_19_HI
- REG_A6XX_RBBM_PERFCTR_SP_19_LO
- REG_A6XX_RBBM_PERFCTR_SP_1_HI
- REG_A6XX_RBBM_PERFCTR_SP_1_LO
- REG_A6XX_RBBM_PERFCTR_SP_20_HI
- REG_A6XX_RBBM_PERFCTR_SP_20_LO
- REG_A6XX_RBBM_PERFCTR_SP_21_HI
- REG_A6XX_RBBM_PERFCTR_SP_21_LO
- REG_A6XX_RBBM_PERFCTR_SP_22_HI
- REG_A6XX_RBBM_PERFCTR_SP_22_LO
- REG_A6XX_RBBM_PERFCTR_SP_23_HI
- REG_A6XX_RBBM_PERFCTR_SP_23_LO
- REG_A6XX_RBBM_PERFCTR_SP_2_HI
- REG_A6XX_RBBM_PERFCTR_SP_2_LO
- REG_A6XX_RBBM_PERFCTR_SP_3_HI
- REG_A6XX_RBBM_PERFCTR_SP_3_LO
- REG_A6XX_RBBM_PERFCTR_SP_4_HI
- REG_A6XX_RBBM_PERFCTR_SP_4_LO
- REG_A6XX_RBBM_PERFCTR_SP_5_HI
- REG_A6XX_RBBM_PERFCTR_SP_5_LO
- REG_A6XX_RBBM_PERFCTR_SP_6_HI
- REG_A6XX_RBBM_PERFCTR_SP_6_LO
- REG_A6XX_RBBM_PERFCTR_SP_7_HI
- REG_A6XX_RBBM_PERFCTR_SP_7_LO
- REG_A6XX_RBBM_PERFCTR_SP_8_HI
- REG_A6XX_RBBM_PERFCTR_SP_8_LO
- REG_A6XX_RBBM_PERFCTR_SP_9_HI
- REG_A6XX_RBBM_PERFCTR_SP_9_LO
- REG_A6XX_RBBM_PERFCTR_TP_0_HI
- REG_A6XX_RBBM_PERFCTR_TP_0_LO
- REG_A6XX_RBBM_PERFCTR_TP_10_HI
- REG_A6XX_RBBM_PERFCTR_TP_10_LO
- REG_A6XX_RBBM_PERFCTR_TP_11_HI
- REG_A6XX_RBBM_PERFCTR_TP_11_LO
- REG_A6XX_RBBM_PERFCTR_TP_1_HI
- REG_A6XX_RBBM_PERFCTR_TP_1_LO
- REG_A6XX_RBBM_PERFCTR_TP_2_HI
- REG_A6XX_RBBM_PERFCTR_TP_2_LO
- REG_A6XX_RBBM_PERFCTR_TP_3_HI
- REG_A6XX_RBBM_PERFCTR_TP_3_LO
- REG_A6XX_RBBM_PERFCTR_TP_4_HI
- REG_A6XX_RBBM_PERFCTR_TP_4_LO
- REG_A6XX_RBBM_PERFCTR_TP_5_HI
- REG_A6XX_RBBM_PERFCTR_TP_5_LO
- REG_A6XX_RBBM_PERFCTR_TP_6_HI
- REG_A6XX_RBBM_PERFCTR_TP_6_LO
- REG_A6XX_RBBM_PERFCTR_TP_7_HI
- REG_A6XX_RBBM_PERFCTR_TP_7_LO
- REG_A6XX_RBBM_PERFCTR_TP_8_HI
- REG_A6XX_RBBM_PERFCTR_TP_8_LO
- REG_A6XX_RBBM_PERFCTR_TP_9_HI
- REG_A6XX_RBBM_PERFCTR_TP_9_LO
- REG_A6XX_RBBM_PERFCTR_TSE_0_HI
- REG_A6XX_RBBM_PERFCTR_TSE_0_LO
- REG_A6XX_RBBM_PERFCTR_TSE_1_HI
- REG_A6XX_RBBM_PERFCTR_TSE_1_LO
- REG_A6XX_RBBM_PERFCTR_TSE_2_HI
- REG_A6XX_RBBM_PERFCTR_TSE_2_LO
- REG_A6XX_RBBM_PERFCTR_TSE_3_HI
- REG_A6XX_RBBM_PERFCTR_TSE_3_LO
- REG_A6XX_RBBM_PERFCTR_UCHE_0_HI
- REG_A6XX_RBBM_PERFCTR_UCHE_0_LO
- REG_A6XX_RBBM_PERFCTR_UCHE_10_HI
- REG_A6XX_RBBM_PERFCTR_UCHE_10_LO
- REG_A6XX_RBBM_PERFCTR_UCHE_11_HI
- REG_A6XX_RBBM_PERFCTR_UCHE_11_LO
- REG_A6XX_RBBM_PERFCTR_UCHE_1_HI
- REG_A6XX_RBBM_PERFCTR_UCHE_1_LO
- REG_A6XX_RBBM_PERFCTR_UCHE_2_HI
- REG_A6XX_RBBM_PERFCTR_UCHE_2_LO
- REG_A6XX_RBBM_PERFCTR_UCHE_3_HI
- REG_A6XX_RBBM_PERFCTR_UCHE_3_LO
- REG_A6XX_RBBM_PERFCTR_UCHE_4_HI
- REG_A6XX_RBBM_PERFCTR_UCHE_4_LO
- REG_A6XX_RBBM_PERFCTR_UCHE_5_HI
- REG_A6XX_RBBM_PERFCTR_UCHE_5_LO
- REG_A6XX_RBBM_PERFCTR_UCHE_6_HI
- REG_A6XX_RBBM_PERFCTR_UCHE_6_LO
- REG_A6XX_RBBM_PERFCTR_UCHE_7_HI
- REG_A6XX_RBBM_PERFCTR_UCHE_7_LO
- REG_A6XX_RBBM_PERFCTR_UCHE_8_HI
- REG_A6XX_RBBM_PERFCTR_UCHE_8_LO
- REG_A6XX_RBBM_PERFCTR_UCHE_9_HI
- REG_A6XX_RBBM_PERFCTR_UCHE_9_LO
- REG_A6XX_RBBM_PERFCTR_VFD_0_HI
- REG_A6XX_RBBM_PERFCTR_VFD_0_LO
- REG_A6XX_RBBM_PERFCTR_VFD_1_HI
- REG_A6XX_RBBM_PERFCTR_VFD_1_LO
- REG_A6XX_RBBM_PERFCTR_VFD_2_HI
- REG_A6XX_RBBM_PERFCTR_VFD_2_LO
- REG_A6XX_RBBM_PERFCTR_VFD_3_HI
- REG_A6XX_RBBM_PERFCTR_VFD_3_LO
- REG_A6XX_RBBM_PERFCTR_VFD_4_HI
- REG_A6XX_RBBM_PERFCTR_VFD_4_LO
- REG_A6XX_RBBM_PERFCTR_VFD_5_HI
- REG_A6XX_RBBM_PERFCTR_VFD_5_LO
- REG_A6XX_RBBM_PERFCTR_VFD_6_HI
- REG_A6XX_RBBM_PERFCTR_VFD_6_LO
- REG_A6XX_RBBM_PERFCTR_VFD_7_HI
- REG_A6XX_RBBM_PERFCTR_VFD_7_LO
- REG_A6XX_RBBM_PERFCTR_VPC_0_HI
- REG_A6XX_RBBM_PERFCTR_VPC_0_LO
- REG_A6XX_RBBM_PERFCTR_VPC_1_HI
- REG_A6XX_RBBM_PERFCTR_VPC_1_LO
- REG_A6XX_RBBM_PERFCTR_VPC_2_HI
- REG_A6XX_RBBM_PERFCTR_VPC_2_LO
- REG_A6XX_RBBM_PERFCTR_VPC_3_HI
- REG_A6XX_RBBM_PERFCTR_VPC_3_LO
- REG_A6XX_RBBM_PERFCTR_VPC_4_HI
- REG_A6XX_RBBM_PERFCTR_VPC_4_LO
- REG_A6XX_RBBM_PERFCTR_VPC_5_HI
- REG_A6XX_RBBM_PERFCTR_VPC_5_LO
- REG_A6XX_RBBM_PERFCTR_VSC_0_HI
- REG_A6XX_RBBM_PERFCTR_VSC_0_LO
- REG_A6XX_RBBM_PERFCTR_VSC_1_HI
- REG_A6XX_RBBM_PERFCTR_VSC_1_LO
- REG_A6XX_RBBM_RAC_THRESHOLD_CNT
- REG_A6XX_RBBM_SECVID_TRUST_CNTL
- REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL
- REG_A6XX_RBBM_SECVID_TSB_CNTL
- REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI
- REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO
- REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE
- REG_A6XX_RBBM_SP_HYST_CNT
- REG_A6XX_RBBM_STATUS
- REG_A6XX_RBBM_STATUS3
- REG_A6XX_RBBM_SW_RESET_CMD
- REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL
- REG_A6XX_RBBM_VBIF_GX_RESET_STATUS
- REG_A6XX_RB_2D_BLIT_CNTL
- REG_A6XX_RB_2D_DST_FLAGS_HI
- REG_A6XX_RB_2D_DST_FLAGS_LO
- REG_A6XX_RB_2D_DST_HI
- REG_A6XX_RB_2D_DST_INFO
- REG_A6XX_RB_2D_DST_LO
- REG_A6XX_RB_2D_DST_SIZE
- REG_A6XX_RB_2D_SRC_SOLID_C0
- REG_A6XX_RB_2D_SRC_SOLID_C1
- REG_A6XX_RB_2D_SRC_SOLID_C2
- REG_A6XX_RB_2D_SRC_SOLID_C3
- REG_A6XX_RB_ADDR_MODE_CNTL
- REG_A6XX_RB_ALPHA_CONTROL
- REG_A6XX_RB_BIN_CONTROL
- REG_A6XX_RB_BIN_CONTROL2
- REG_A6XX_RB_BLEND_ALPHA_F32
- REG_A6XX_RB_BLEND_BLUE_F32
- REG_A6XX_RB_BLEND_CNTL
- REG_A6XX_RB_BLEND_GREEN_F32
- REG_A6XX_RB_BLEND_RED_F32
- REG_A6XX_RB_BLIT_BASE_GMEM
- REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0
- REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1
- REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2
- REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3
- REG_A6XX_RB_BLIT_DST_ARRAY_PITCH
- REG_A6XX_RB_BLIT_DST_HI
- REG_A6XX_RB_BLIT_DST_INFO
- REG_A6XX_RB_BLIT_DST_LO
- REG_A6XX_RB_BLIT_DST_PITCH
- REG_A6XX_RB_BLIT_FLAG_DST_HI
- REG_A6XX_RB_BLIT_FLAG_DST_LO
- REG_A6XX_RB_BLIT_INFO
- REG_A6XX_RB_BLIT_SCISSOR_BR
- REG_A6XX_RB_BLIT_SCISSOR_TL
- REG_A6XX_RB_CCU_CNTL
- REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE
- REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH
- REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM
- REG_A6XX_RB_DEPTH_BUFFER_BASE_HI
- REG_A6XX_RB_DEPTH_BUFFER_BASE_LO
- REG_A6XX_RB_DEPTH_BUFFER_INFO
- REG_A6XX_RB_DEPTH_BUFFER_PITCH
- REG_A6XX_RB_DEPTH_CNTL
- REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_HI
- REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO
- REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH
- REG_A6XX_RB_DEPTH_PLANE_CNTL
- REG_A6XX_RB_DEST_MSAA_CNTL
- REG_A6XX_RB_DITHER_CNTL
- REG_A6XX_RB_FS_OUTPUT_CNTL0
- REG_A6XX_RB_FS_OUTPUT_CNTL1
- REG_A6XX_RB_LRZ_CNTL
- REG_A6XX_RB_MRT
- REG_A6XX_RB_MRT_ARRAY_PITCH
- REG_A6XX_RB_MRT_BASE_GMEM
- REG_A6XX_RB_MRT_BASE_HI
- REG_A6XX_RB_MRT_BASE_LO
- REG_A6XX_RB_MRT_BLEND_CONTROL
- REG_A6XX_RB_MRT_BUF_INFO
- REG_A6XX_RB_MRT_CONTROL
- REG_A6XX_RB_MRT_FLAG_BUFFER
- REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI
- REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO
- REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH
- REG_A6XX_RB_MRT_PITCH
- REG_A6XX_RB_MSAA_CNTL
- REG_A6XX_RB_NC_MODE_CNTL
- REG_A6XX_RB_PERFCTR_CCU_SEL_0
- REG_A6XX_RB_PERFCTR_CCU_SEL_1
- REG_A6XX_RB_PERFCTR_CCU_SEL_2
- REG_A6XX_RB_PERFCTR_CCU_SEL_3
- REG_A6XX_RB_PERFCTR_CCU_SEL_4
- REG_A6XX_RB_PERFCTR_CMP_SEL_0
- REG_A6XX_RB_PERFCTR_CMP_SEL_1
- REG_A6XX_RB_PERFCTR_CMP_SEL_2
- REG_A6XX_RB_PERFCTR_CMP_SEL_3
- REG_A6XX_RB_PERFCTR_RB_SEL_0
- REG_A6XX_RB_PERFCTR_RB_SEL_1
- REG_A6XX_RB_PERFCTR_RB_SEL_2
- REG_A6XX_RB_PERFCTR_RB_SEL_3
- REG_A6XX_RB_PERFCTR_RB_SEL_4
- REG_A6XX_RB_PERFCTR_RB_SEL_5
- REG_A6XX_RB_PERFCTR_RB_SEL_6
- REG_A6XX_RB_PERFCTR_RB_SEL_7
- REG_A6XX_RB_RAS_MSAA_CNTL
- REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD
- REG_A6XX_RB_RENDER_CNTL
- REG_A6XX_RB_RENDER_COMPONENTS
- REG_A6XX_RB_RENDER_CONTROL0
- REG_A6XX_RB_RENDER_CONTROL1
- REG_A6XX_RB_SAMPLE_COUNT_ADDR_HI
- REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO
- REG_A6XX_RB_SAMPLE_COUNT_CONTROL
- REG_A6XX_RB_SRGB_CNTL
- REG_A6XX_RB_STENCILMASK
- REG_A6XX_RB_STENCILREF
- REG_A6XX_RB_STENCILWRMASK
- REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH
- REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM
- REG_A6XX_RB_STENCIL_BUFFER_BASE_HI
- REG_A6XX_RB_STENCIL_BUFFER_BASE_LO
- REG_A6XX_RB_STENCIL_BUFFER_PITCH
- REG_A6XX_RB_STENCIL_CONTROL
- REG_A6XX_RB_STENCIL_INFO
- REG_A6XX_RB_UNKNOWN_8804
- REG_A6XX_RB_UNKNOWN_8805
- REG_A6XX_RB_UNKNOWN_8806
- REG_A6XX_RB_UNKNOWN_8810
- REG_A6XX_RB_UNKNOWN_8811
- REG_A6XX_RB_UNKNOWN_8818
- REG_A6XX_RB_UNKNOWN_8819
- REG_A6XX_RB_UNKNOWN_881A
- REG_A6XX_RB_UNKNOWN_881B
- REG_A6XX_RB_UNKNOWN_881C
- REG_A6XX_RB_UNKNOWN_881D
- REG_A6XX_RB_UNKNOWN_881E
- REG_A6XX_RB_UNKNOWN_8878
- REG_A6XX_RB_UNKNOWN_8879
- REG_A6XX_RB_UNKNOWN_88D0
- REG_A6XX_RB_UNKNOWN_88F0
- REG_A6XX_RB_UNKNOWN_8C01
- REG_A6XX_RB_UNKNOWN_8E01
- REG_A6XX_RB_UNKNOWN_8E04
- REG_A6XX_RB_WINDOW_OFFSET
- REG_A6XX_RB_WINDOW_OFFSET2
- REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR
- REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA
- REG_A6XX_RSCC_OVERRIDE_START_ADDR
- REG_A6XX_RSCC_PDC_MATCH_VALUE_HI
- REG_A6XX_RSCC_PDC_MATCH_VALUE_LO
- REG_A6XX_RSCC_PDC_SEQ_START_ADDR
- REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0
- REG_A6XX_RSCC_SEQ_BUSY_DRV0
- REG_A6XX_RSCC_SEQ_MEM_0_DRV0
- REG_A6XX_RSCC_TCS0_DRV0_STATUS
- REG_A6XX_RSCC_TCS1_DRV0_STATUS
- REG_A6XX_RSCC_TCS2_DRV0_STATUS
- REG_A6XX_RSCC_TCS3_DRV0_STATUS
- REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0
- REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0
- REG_A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0
- REG_A6XX_RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0
- REG_A6XX_SP_ADDR_MODE_CNTL
- REG_A6XX_SP_BLEND_CNTL
- REG_A6XX_SP_CS_CTRL_REG0
- REG_A6XX_SP_CS_INSTRLEN
- REG_A6XX_SP_CS_OBJ_START_HI
- REG_A6XX_SP_CS_OBJ_START_LO
- REG_A6XX_SP_CS_TEX_CONST_HI
- REG_A6XX_SP_CS_TEX_CONST_LO
- REG_A6XX_SP_CS_TEX_SAMP_HI
- REG_A6XX_SP_CS_TEX_SAMP_LO
- REG_A6XX_SP_DS_CONFIG
- REG_A6XX_SP_DS_CTRL_REG0
- REG_A6XX_SP_DS_INSTRLEN
- REG_A6XX_SP_DS_OBJ_START_HI
- REG_A6XX_SP_DS_OBJ_START_LO
- REG_A6XX_SP_DS_TEX_CONST_HI
- REG_A6XX_SP_DS_TEX_CONST_LO
- REG_A6XX_SP_DS_TEX_COUNT
- REG_A6XX_SP_DS_TEX_SAMP_HI
- REG_A6XX_SP_DS_TEX_SAMP_LO
- REG_A6XX_SP_FS_CONFIG
- REG_A6XX_SP_FS_CTRL_REG0
- REG_A6XX_SP_FS_INSTRLEN
- REG_A6XX_SP_FS_MRT
- REG_A6XX_SP_FS_MRT_REG
- REG_A6XX_SP_FS_OBJ_START_HI
- REG_A6XX_SP_FS_OBJ_START_LO
- REG_A6XX_SP_FS_OUTPUT
- REG_A6XX_SP_FS_OUTPUT_CNTL0
- REG_A6XX_SP_FS_OUTPUT_CNTL1
- REG_A6XX_SP_FS_OUTPUT_REG
- REG_A6XX_SP_FS_RENDER_COMPONENTS
- REG_A6XX_SP_FS_TEX_CONST_HI
- REG_A6XX_SP_FS_TEX_CONST_LO
- REG_A6XX_SP_FS_TEX_COUNT
- REG_A6XX_SP_FS_TEX_SAMP_HI
- REG_A6XX_SP_FS_TEX_SAMP_LO
- REG_A6XX_SP_GS_CONFIG
- REG_A6XX_SP_GS_CTRL_REG0
- REG_A6XX_SP_GS_INSTRLEN
- REG_A6XX_SP_GS_OBJ_START_HI
- REG_A6XX_SP_GS_OBJ_START_LO
- REG_A6XX_SP_GS_TEX_CONST_HI
- REG_A6XX_SP_GS_TEX_CONST_LO
- REG_A6XX_SP_GS_TEX_COUNT
- REG_A6XX_SP_GS_TEX_SAMP_HI
- REG_A6XX_SP_GS_TEX_SAMP_LO
- REG_A6XX_SP_GS_UNKNOWN_A871
- REG_A6XX_SP_HS_CONFIG
- REG_A6XX_SP_HS_CTRL_REG0
- REG_A6XX_SP_HS_INSTRLEN
- REG_A6XX_SP_HS_OBJ_START_HI
- REG_A6XX_SP_HS_OBJ_START_LO
- REG_A6XX_SP_HS_TEX_CONST_HI
- REG_A6XX_SP_HS_TEX_CONST_LO
- REG_A6XX_SP_HS_TEX_COUNT
- REG_A6XX_SP_HS_TEX_SAMP_HI
- REG_A6XX_SP_HS_TEX_SAMP_LO
- REG_A6XX_SP_HS_UNKNOWN_A831
- REG_A6XX_SP_NC_MODE_CNTL
- REG_A6XX_SP_PERFCTR_SP_SEL_0
- REG_A6XX_SP_PERFCTR_SP_SEL_1
- REG_A6XX_SP_PERFCTR_SP_SEL_10
- REG_A6XX_SP_PERFCTR_SP_SEL_11
- REG_A6XX_SP_PERFCTR_SP_SEL_12
- REG_A6XX_SP_PERFCTR_SP_SEL_13
- REG_A6XX_SP_PERFCTR_SP_SEL_14
- REG_A6XX_SP_PERFCTR_SP_SEL_15
- REG_A6XX_SP_PERFCTR_SP_SEL_16
- REG_A6XX_SP_PERFCTR_SP_SEL_17
- REG_A6XX_SP_PERFCTR_SP_SEL_18
- REG_A6XX_SP_PERFCTR_SP_SEL_19
- REG_A6XX_SP_PERFCTR_SP_SEL_2
- REG_A6XX_SP_PERFCTR_SP_SEL_20
- REG_A6XX_SP_PERFCTR_SP_SEL_21
- REG_A6XX_SP_PERFCTR_SP_SEL_22
- REG_A6XX_SP_PERFCTR_SP_SEL_23
- REG_A6XX_SP_PERFCTR_SP_SEL_3
- REG_A6XX_SP_PERFCTR_SP_SEL_4
- REG_A6XX_SP_PERFCTR_SP_SEL_5
- REG_A6XX_SP_PERFCTR_SP_SEL_6
- REG_A6XX_SP_PERFCTR_SP_SEL_7
- REG_A6XX_SP_PERFCTR_SP_SEL_8
- REG_A6XX_SP_PERFCTR_SP_SEL_9
- REG_A6XX_SP_PRIMITIVE_CNTL
- REG_A6XX_SP_PS_2D_SRC_FLAGS_HI
- REG_A6XX_SP_PS_2D_SRC_FLAGS_LO
- REG_A6XX_SP_PS_2D_SRC_HI
- REG_A6XX_SP_PS_2D_SRC_INFO
- REG_A6XX_SP_PS_2D_SRC_LO
- REG_A6XX_SP_PS_2D_SRC_PITCH
- REG_A6XX_SP_PS_2D_SRC_SIZE
- REG_A6XX_SP_SRGB_CNTL
- REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_HI
- REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO
- REG_A6XX_SP_TP_DEST_MSAA_CNTL
- REG_A6XX_SP_TP_RAS_MSAA_CNTL
- REG_A6XX_SP_TP_UNKNOWN_B304
- REG_A6XX_SP_TP_UNKNOWN_B309
- REG_A6XX_SP_TP_WINDOW_OFFSET
- REG_A6XX_SP_UNKNOWN_A0F8
- REG_A6XX_SP_UNKNOWN_A81B
- REG_A6XX_SP_UNKNOWN_A982
- REG_A6XX_SP_UNKNOWN_A99E
- REG_A6XX_SP_UNKNOWN_A9A8
- REG_A6XX_SP_UNKNOWN_AB00
- REG_A6XX_SP_UNKNOWN_AB20
- REG_A6XX_SP_UNKNOWN_ACC0
- REG_A6XX_SP_UNKNOWN_AE00
- REG_A6XX_SP_UNKNOWN_AE03
- REG_A6XX_SP_UNKNOWN_AE04
- REG_A6XX_SP_UNKNOWN_AE0F
- REG_A6XX_SP_UNKNOWN_B182
- REG_A6XX_SP_UNKNOWN_B183
- REG_A6XX_SP_UNKNOWN_B600
- REG_A6XX_SP_UNKNOWN_B605
- REG_A6XX_SP_VS_CONFIG
- REG_A6XX_SP_VS_CTRL_REG0
- REG_A6XX_SP_VS_INSTRLEN
- REG_A6XX_SP_VS_OBJ_START_HI
- REG_A6XX_SP_VS_OBJ_START_LO
- REG_A6XX_SP_VS_OUT
- REG_A6XX_SP_VS_OUT_REG
- REG_A6XX_SP_VS_TEX_CONST_HI
- REG_A6XX_SP_VS_TEX_CONST_LO
- REG_A6XX_SP_VS_TEX_COUNT
- REG_A6XX_SP_VS_TEX_SAMP_HI
- REG_A6XX_SP_VS_TEX_SAMP_LO
- REG_A6XX_SP_VS_VPC_DST
- REG_A6XX_SP_VS_VPC_DST_REG
- REG_A6XX_SP_WINDOW_OFFSET
- REG_A6XX_TEX_CONST_0
- REG_A6XX_TEX_CONST_1
- REG_A6XX_TEX_CONST_10
- REG_A6XX_TEX_CONST_11
- REG_A6XX_TEX_CONST_12
- REG_A6XX_TEX_CONST_13
- REG_A6XX_TEX_CONST_14
- REG_A6XX_TEX_CONST_15
- REG_A6XX_TEX_CONST_2
- REG_A6XX_TEX_CONST_3
- REG_A6XX_TEX_CONST_4
- REG_A6XX_TEX_CONST_5
- REG_A6XX_TEX_CONST_6
- REG_A6XX_TEX_CONST_7
- REG_A6XX_TEX_CONST_8
- REG_A6XX_TEX_CONST_9
- REG_A6XX_TEX_SAMP_0
- REG_A6XX_TEX_SAMP_1
- REG_A6XX_TEX_SAMP_2
- REG_A6XX_TEX_SAMP_3
- REG_A6XX_TPL1_ADDR_MODE_CNTL
- REG_A6XX_TPL1_NC_MODE_CNTL
- REG_A6XX_TPL1_PERFCTR_TP_SEL_0
- REG_A6XX_TPL1_PERFCTR_TP_SEL_1
- REG_A6XX_TPL1_PERFCTR_TP_SEL_10
- REG_A6XX_TPL1_PERFCTR_TP_SEL_11
- REG_A6XX_TPL1_PERFCTR_TP_SEL_2
- REG_A6XX_TPL1_PERFCTR_TP_SEL_3
- REG_A6XX_TPL1_PERFCTR_TP_SEL_4
- REG_A6XX_TPL1_PERFCTR_TP_SEL_5
- REG_A6XX_TPL1_PERFCTR_TP_SEL_6
- REG_A6XX_TPL1_PERFCTR_TP_SEL_7
- REG_A6XX_TPL1_PERFCTR_TP_SEL_8
- REG_A6XX_TPL1_PERFCTR_TP_SEL_9
- REG_A6XX_UCHE_ADDR_MODE_CNTL
- REG_A6XX_UCHE_CACHE_WAYS
- REG_A6XX_UCHE_CLIENT_PF
- REG_A6XX_UCHE_FILTER_CNTL
- REG_A6XX_UCHE_GMEM_RANGE_MAX_HI
- REG_A6XX_UCHE_GMEM_RANGE_MAX_LO
- REG_A6XX_UCHE_GMEM_RANGE_MIN_HI
- REG_A6XX_UCHE_GMEM_RANGE_MIN_LO
- REG_A6XX_UCHE_MODE_CNTL
- REG_A6XX_UCHE_PERFCTR_UCHE_SEL_0
- REG_A6XX_UCHE_PERFCTR_UCHE_SEL_1
- REG_A6XX_UCHE_PERFCTR_UCHE_SEL_10
- REG_A6XX_UCHE_PERFCTR_UCHE_SEL_11
- REG_A6XX_UCHE_PERFCTR_UCHE_SEL_2
- REG_A6XX_UCHE_PERFCTR_UCHE_SEL_3
- REG_A6XX_UCHE_PERFCTR_UCHE_SEL_4
- REG_A6XX_UCHE_PERFCTR_UCHE_SEL_5
- REG_A6XX_UCHE_PERFCTR_UCHE_SEL_6
- REG_A6XX_UCHE_PERFCTR_UCHE_SEL_7
- REG_A6XX_UCHE_PERFCTR_UCHE_SEL_8
- REG_A6XX_UCHE_PERFCTR_UCHE_SEL_9
- REG_A6XX_UCHE_TRAP_BASE_HI
- REG_A6XX_UCHE_TRAP_BASE_LO
- REG_A6XX_UCHE_UNKNOWN_0E12
- REG_A6XX_UCHE_WRITE_RANGE_MAX_HI
- REG_A6XX_UCHE_WRITE_RANGE_MAX_LO
- REG_A6XX_UCHE_WRITE_THRU_BASE_HI
- REG_A6XX_UCHE_WRITE_THRU_BASE_LO
- REG_A6XX_VBIF_CLKON
- REG_A6XX_VBIF_GATE_OFF_WRREQ_EN
- REG_A6XX_VBIF_PERF_CNT_HIGH0
- REG_A6XX_VBIF_PERF_CNT_HIGH1
- REG_A6XX_VBIF_PERF_CNT_HIGH2
- REG_A6XX_VBIF_PERF_CNT_HIGH3
- REG_A6XX_VBIF_PERF_CNT_LOW0
- REG_A6XX_VBIF_PERF_CNT_LOW1
- REG_A6XX_VBIF_PERF_CNT_LOW2
- REG_A6XX_VBIF_PERF_CNT_LOW3
- REG_A6XX_VBIF_PERF_CNT_SEL0
- REG_A6XX_VBIF_PERF_CNT_SEL1
- REG_A6XX_VBIF_PERF_CNT_SEL2
- REG_A6XX_VBIF_PERF_CNT_SEL3
- REG_A6XX_VBIF_PERF_PWR_CNT_EN0
- REG_A6XX_VBIF_PERF_PWR_CNT_EN1
- REG_A6XX_VBIF_PERF_PWR_CNT_EN2
- REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0
- REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1
- REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2
- REG_A6XX_VBIF_PERF_PWR_CNT_LOW0
- REG_A6XX_VBIF_PERF_PWR_CNT_LOW1
- REG_A6XX_VBIF_PERF_PWR_CNT_LOW2
- REG_A6XX_VBIF_TEST_BUS1_CTRL0
- REG_A6XX_VBIF_TEST_BUS1_CTRL1
- REG_A6XX_VBIF_TEST_BUS2_CTRL0
- REG_A6XX_VBIF_TEST_BUS2_CTRL1
- REG_A6XX_VBIF_TEST_BUS_OUT
- REG_A6XX_VBIF_TEST_BUS_OUT_CTRL
- REG_A6XX_VBIF_VERSION
- REG_A6XX_VBIF_XIN_HALT_CTRL0
- REG_A6XX_VBIF_XIN_HALT_CTRL1
- REG_A6XX_VFD_ADDR_MODE_CNTL
- REG_A6XX_VFD_CONTROL_0
- REG_A6XX_VFD_CONTROL_1
- REG_A6XX_VFD_CONTROL_2
- REG_A6XX_VFD_CONTROL_3
- REG_A6XX_VFD_CONTROL_4
- REG_A6XX_VFD_CONTROL_5
- REG_A6XX_VFD_CONTROL_6
- REG_A6XX_VFD_DECODE
- REG_A6XX_VFD_DECODE_INSTR
- REG_A6XX_VFD_DECODE_STEP_RATE
- REG_A6XX_VFD_DEST_CNTL
- REG_A6XX_VFD_DEST_CNTL_INSTR
- REG_A6XX_VFD_FETCH
- REG_A6XX_VFD_FETCH_BASE_HI
- REG_A6XX_VFD_FETCH_BASE_LO
- REG_A6XX_VFD_FETCH_SIZE
- REG_A6XX_VFD_FETCH_STRIDE
- REG_A6XX_VFD_INDEX_OFFSET
- REG_A6XX_VFD_INSTANCE_START_OFFSET
- REG_A6XX_VFD_MODE_CNTL
- REG_A6XX_VFD_PERFCTR_VFD_SEL_0
- REG_A6XX_VFD_PERFCTR_VFD_SEL_1
- REG_A6XX_VFD_PERFCTR_VFD_SEL_2
- REG_A6XX_VFD_PERFCTR_VFD_SEL_3
- REG_A6XX_VFD_PERFCTR_VFD_SEL_4
- REG_A6XX_VFD_PERFCTR_VFD_SEL_5
- REG_A6XX_VFD_PERFCTR_VFD_SEL_6
- REG_A6XX_VFD_PERFCTR_VFD_SEL_7
- REG_A6XX_VFD_UNKNOWN_A008
- REG_A6XX_VFD_UNKNOWN_A009
- REG_A6XX_VPC_ADDR_MODE_CNTL
- REG_A6XX_VPC_CNTL_0
- REG_A6XX_VPC_GS_SIV_CNTL
- REG_A6XX_VPC_PACK
- REG_A6XX_VPC_PERFCTR_VPC_SEL_0
- REG_A6XX_VPC_PERFCTR_VPC_SEL_1
- REG_A6XX_VPC_PERFCTR_VPC_SEL_2
- REG_A6XX_VPC_PERFCTR_VPC_SEL_3
- REG_A6XX_VPC_PERFCTR_VPC_SEL_4
- REG_A6XX_VPC_PERFCTR_VPC_SEL_5
- REG_A6XX_VPC_SO
- REG_A6XX_VPC_SO_BUFFER_BASE_HI
- REG_A6XX_VPC_SO_BUFFER_BASE_LO
- REG_A6XX_VPC_SO_BUFFER_OFFSET
- REG_A6XX_VPC_SO_BUFFER_SIZE
- REG_A6XX_VPC_SO_BUF_CNTL
- REG_A6XX_VPC_SO_CNTL
- REG_A6XX_VPC_SO_FLUSH_BASE_HI
- REG_A6XX_VPC_SO_FLUSH_BASE_LO
- REG_A6XX_VPC_SO_NCOMP
- REG_A6XX_VPC_SO_OVERRIDE
- REG_A6XX_VPC_SO_PROG
- REG_A6XX_VPC_UNKNOWN_9101
- REG_A6XX_VPC_UNKNOWN_9107
- REG_A6XX_VPC_UNKNOWN_9108
- REG_A6XX_VPC_UNKNOWN_9210
- REG_A6XX_VPC_UNKNOWN_9211
- REG_A6XX_VPC_UNKNOWN_9236
- REG_A6XX_VPC_UNKNOWN_9300
- REG_A6XX_VPC_UNKNOWN_9600
- REG_A6XX_VPC_UNKNOWN_9602
- REG_A6XX_VPC_VAR
- REG_A6XX_VPC_VARYING_INTERP
- REG_A6XX_VPC_VARYING_INTERP_MODE
- REG_A6XX_VPC_VARYING_PS_REPL
- REG_A6XX_VPC_VARYING_PS_REPL_MODE
- REG_A6XX_VPC_VAR_DISABLE
- REG_A6XX_VSC_ADDR_MODE_CNTL
- REG_A6XX_VSC_BIN_COUNT
- REG_A6XX_VSC_BIN_SIZE
- REG_A6XX_VSC_PERFCTR_VSC_SEL_0
- REG_A6XX_VSC_PERFCTR_VSC_SEL_1
- REG_A6XX_VSC_PIPE_CONFIG
- REG_A6XX_VSC_PIPE_CONFIG_REG
- REG_A6XX_VSC_PIPE_DATA2_ADDRESS_HI
- REG_A6XX_VSC_PIPE_DATA2_ADDRESS_LO
- REG_A6XX_VSC_PIPE_DATA2_ARRAY_PITCH
- REG_A6XX_VSC_PIPE_DATA2_PITCH
- REG_A6XX_VSC_PIPE_DATA_ADDRESS_HI
- REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO
- REG_A6XX_VSC_PIPE_DATA_ARRAY_PITCH
- REG_A6XX_VSC_PIPE_DATA_PITCH
- REG_A6XX_VSC_SIZE
- REG_A6XX_VSC_SIZE_ADDRESS_HI
- REG_A6XX_VSC_SIZE_ADDRESS_LO
- REG_A6XX_VSC_SIZE_REG
- REG_AAF_CRESTF_DBX8
- REG_ACBB0
- REG_ACBBRXFIR
- REG_ACCESS_MASK
- REG_ACCESS_R
- REG_ACCESS_RW
- REG_ACCESS_TEST
- REG_ACCESS_W
- REG_ACGG2TBL
- REG_ACI_CRESTF_DBX8
- REG_ACKH
- REG_ACKL
- REG_ACKTMOUT
- REG_ACKTO
- REG_ACKTO_8723B
- REG_ACKTO_CCK
- REG_ACK_SYNC
- REG_ACLK_MON
- REG_ACLK_MON_8723B
- REG_ACL_INT_ENABLE
- REG_ACL_INT_STATUS
- REG_ACMAVG
- REG_ACMHWCTRL
- REG_ACMHWCTRL_8723B
- REG_ACMRSTCTRL
- REG_ACM_HW_CTRL
- REG_ACM_RST_CTRL
- REG_ACOM
- REG_ACP_PACKET_TYPE
- REG_ACR_CTS_0
- REG_ACR_CTS_1
- REG_ACR_CTS_2
- REG_ACR_N_0
- REG_ACR_N_1
- REG_ACR_N_2
- REG_ACTL
- REG_ACTL2
- REG_ACT_LINES_PER_FRAME
- REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0_MASK
- REG_ADAPT_pciecore0_CONTROL__ACCESS_MODE_pciecore0__SHIFT
- REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0_MASK
- REG_ADAPT_pif0_CONTROL__ACCESS_MODE_pif0__SHIFT
- REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr_MASK
- REG_ADAPT_pwregr_CONTROL__ACCESS_MODE_pwregr__SHIFT
- REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt_MASK
- REG_ADAPT_pwregt_CONTROL__ACCESS_MODE_pwregt__SHIFT
- REG_ADC
- REG_ADC160
- REG_ADC40
- REG_ADCCLK
- REG_ADCFSM
- REG_ADCINI
- REG_ADCL
- REG_ADC_ANA_1
- REG_ADC_CFG
- REG_ADC_CONFIG
- REG_ADC_GC
- REG_ADC_GS
- REG_ADC_HC0
- REG_ADC_HC1
- REG_ADC_HC2
- REG_ADC_HC3
- REG_ADC_HC4
- REG_ADC_HS
- REG_ADC_R0
- REG_ADC_RBK
- REG_ADC_RESET
- REG_ADC_RI1
- REG_ADC_RI2
- REG_ADC_RI3
- REG_ADC_RI4
- REG_ADC_RI5
- REG_ADC_RI6
- REG_ADC_RI8
- REG_ADDR
- REG_ADDR1
- REG_ADDR2
- REG_ADDR4
- REG_ADDR_AI
- REG_ADDR_EXT
- REG_ADDR_H
- REG_ADDR_JUMP
- REG_ADDR_LEN
- REG_ADDR_LOW_MASK
- REG_ADDR_MASK
- REG_ADDR_POS
- REG_ADDR_SET
- REG_ADDR_SHIFT
- REG_ADDU
- REG_ADI_ARM_CMD_STS
- REG_ADI_ARM_FIFO_STS
- REG_ADI_CHN_ADDR
- REG_ADI_CHN_EN
- REG_ADI_CHN_EN1
- REG_ADI_CHN_PRIH
- REG_ADI_CHN_PRIL
- REG_ADI_CTRL0
- REG_ADI_EVT_FIFO_STS
- REG_ADI_GSSI_CFG0
- REG_ADI_GSSI_CFG1
- REG_ADI_INT_CLR
- REG_ADI_INT_EN
- REG_ADI_INT_MASK
- REG_ADI_INT_RAW
- REG_ADI_RD_CMD
- REG_ADI_RD_DATA
- REG_ADI_STS
- REG_ADP_BC
- REG_ADP_BC_ACA_ENABLE
- REG_ADP_BC_ACA_PIN_FLOAT
- REG_ADP_BC_ACA_PIN_GND
- REG_ADP_BC_ACA_PIN_RANGE_A
- REG_ADP_BC_ACA_PIN_RANGE_B
- REG_ADP_BC_ACA_PIN_RANGE_C
- REG_ADP_BC_ADP_CHARGE
- REG_ADP_BC_ADP_DISCHARGE
- REG_ADP_BC_ADP_PRB_EN
- REG_ADP_BC_ADP_PROBE
- REG_ADP_BC_ADP_SENSE
- REG_ADP_BC_A_VALID
- REG_ADP_BC_B_VALID
- REG_ADP_BC_CHARGE_DETECT
- REG_ADP_BC_CHARGE_SEL
- REG_ADP_BC_DCD_ENABLE
- REG_ADP_BC_DEVICE_SESS_VLD
- REG_ADP_BC_DRV_VBUS
- REG_ADP_BC_ID_DIG
- REG_ADP_BC_ID_PULLUP
- REG_ADP_BC_OTG_DISABLE
- REG_ADP_BC_SESS_END
- REG_ADP_BC_VBUS_VALID
- REG_ADP_BC_VBUS_VLD_EXT
- REG_ADP_BC_VBUS_VLD_EXT_SEL
- REG_ADP_BC_VDAT_DET_EN_B
- REG_ADP_BC_VDAT_SRC_EN_B
- REG_ADRENO_CP_RB_BASE
- REG_ADRENO_CP_RB_BASE_HI
- REG_ADRENO_CP_RB_CNTL
- REG_ADRENO_CP_RB_RPTR
- REG_ADRENO_CP_RB_RPTR_ADDR
- REG_ADRENO_CP_RB_RPTR_ADDR_HI
- REG_ADRENO_CP_RB_WPTR
- REG_ADRENO_DEFINE
- REG_ADRENO_REGISTER_MAX
- REG_ADRENO_SKIP
- REG_ADVFH
- REG_ADVFL
- REG_AD_CONTROL
- REG_AEB
- REG_AEC
- REG_AECH
- REG_AECHH
- REG_AECHM
- REG_AESKEY1
- REG_AESKEY10
- REG_AESKEY11
- REG_AESKEY12
- REG_AESKEY13
- REG_AESKEY14
- REG_AESKEY15
- REG_AESKEY16
- REG_AESKEY2
- REG_AESKEY3
- REG_AESKEY4
- REG_AESKEY5
- REG_AESKEY6
- REG_AESKEY7
- REG_AESKEY8
- REG_AESKEY9
- REG_AEW
- REG_AE_ALL
- REG_AE_CENTER
- REG_AE_INDEX_00
- REG_AE_INDEX_05_NEG
- REG_AE_INDEX_05_POS
- REG_AE_INDEX_10_NEG
- REG_AE_INDEX_10_POS
- REG_AE_INDEX_15_NEG
- REG_AE_INDEX_15_POS
- REG_AE_INDEX_20_NEG
- REG_AE_INDEX_20_POS
- REG_AE_LOCK
- REG_AE_OFF
- REG_AE_SPOT
- REG_AE_UNLOCK
- REG_AFCBW
- REG_AFCCTRL
- REG_AFCFEI
- REG_AFCLSB
- REG_AFCMSB
- REG_AFC_CFG
- REG_AFC_KI_KP
- REG_AFC_RANGE
- REG_AFC_READ
- REG_AFE_COARSE_GAIN_CH1
- REG_AFE_COARSE_GAIN_CH2
- REG_AFE_COARSE_GAIN_CH3
- REG_AFE_COARSE_GAIN_CH4
- REG_AFE_CTRL1
- REG_AFE_CTRL2
- REG_AFE_CTRL3
- REG_AFE_CTRL4
- REG_AFE_CTRL_4_8723B
- REG_AFE_FINE_GAIN_CVBS_LUMA_LSB
- REG_AFE_FINE_GAIN_CVBS_LUMA_MSB
- REG_AFE_FINE_GAIN_PB_B_LSB
- REG_AFE_FINE_GAIN_PB_B_MSB
- REG_AFE_FINE_GAIN_PR_R_LSB
- REG_AFE_FINE_GAIN_PR_R_MSB
- REG_AFE_FINE_GAIN_Y_G_CHROMA_LSB
- REG_AFE_FINE_GAIN_Y_G_CHROMA_MSB
- REG_AFE_GAIN_CTRL
- REG_AFE_LDO_CTRL
- REG_AFE_MISC
- REG_AFE_MISC_8723B
- REG_AFE_PLL_CTRL
- REG_AFE_PLL_CTRL_8723B
- REG_AFE_XTAL_CTRL
- REG_AFE_XTAL_CTRL_8723B
- REG_AFE_XTAL_CTRL_EXT
- REG_AFE_XTAL_CTRL_EXT_8723B
- REG_AFP
- REG_AF_BUSY
- REG_AF_EXE_AUTO
- REG_AF_EXE_CAF
- REG_AF_FAIL
- REG_AF_IDLE
- REG_AF_MACRO
- REG_AF_NORMAL
- REG_AF_POWEROFF
- REG_AF_STATUS
- REG_AF_STATUS_FOCUSED
- REG_AF_STATUS_FOCUSING
- REG_AF_STATUS_INVALID
- REG_AF_STATUS_UNFOCUSED
- REG_AF_STOP
- REG_AF_SUCCESS
- REG_AF_TOUCH_POSITION
- REG_AGC2_CLKDIV
- REG_AGC2_KACQ
- REG_AGC2_KLOC
- REG_AGC2_MIN
- REG_AGC2_OUTPUT
- REG_AGCREF
- REG_AGCSTAT
- REG_AGCSWSH
- REG_AGCTHRESH1
- REG_AGCTHRESH2
- REG_AGCTHRESH3
- REG_AGCTR_A
- REG_AGCTR_B
- REG_AGC_CFG1
- REG_AGC_CFG2
- REG_AGC_CFG3
- REG_AGC_CFG4
- REG_AGC_CFG5
- REG_AGC_CFG6
- REG_AGC_CRESTF_DBX8
- REG_AGC_DECREMENT_DELAY
- REG_AGC_DECREMENT_SPEED_CONTROL
- REG_AGC_GAIN_STATUS_LSB
- REG_AGC_GAIN_STATUS_MSB
- REG_AGC_HOLD_LOOP
- REG_AGC_IF_SLR
- REG_AGC_IF_TRI
- REG_AGC_INCREMENT_DELAY
- REG_AGC_INCREMENT_SPEED
- REG_AGC_LOCK
- REG_AGC_MAX
- REG_AGC_MIN
- REG_AGC_PWM_VAL
- REG_AGC_TARGET
- REG_AGC_UNFREEZE_THR
- REG_AGC_WHITE_PEAK_PROCESSING
- REG_AGE_INC
- REG_AGE_TIMER
- REG_AGGLEN_LMT
- REG_AGGR_BREAK_TIME
- REG_AGGR_BREAK_TIME_8723B
- REG_AGGR_SETUP
- REG_AHSIZE
- REG_AHSTART
- REG_AICR_CONFIG1_MASK
- REG_AICR_CONFIG1_OFFSET
- REG_AIC_H
- REG_AIP_CLKSEL
- REG_AIP_CNTRL_0
- REG_AKSV_1
- REG_ALARM
- REG_ALARM1_DATE
- REG_ALARM1_HOUR
- REG_ALARM1_MIN
- REG_ALARM1_MONTH
- REG_ALARM1_SEC
- REG_ALARM1_WEEKDAY
- REG_ALARM1_YEAR
- REG_ALARM2_DATE
- REG_ALARM2_HOUR
- REG_ALARM2_MIN
- REG_ALARM2_MONTH
- REG_ALARM2_SEC
- REG_ALARM2_WEEKDAY
- REG_ALARM2_YEAR
- REG_ALARM_DAYS_REG
- REG_ALARM_HOURS_REG
- REG_ALARM_MINUTES_REG
- REG_ALARM_MONTHS_REG
- REG_ALARM_SECONDS_REG
- REG_ALARM_YEARS_REG
- REG_ALIAS_CLEAR
- REG_ALICE0_BW_I2C
- REG_ALICE0_MODE_CTRL
- REG_ALICE0_ZONE_CTRL
- REG_ALT
- REG_ALTERNATE_STATUS
- REG_AMBIENT_LIGHT
- REG_AMPDU_BURST_MODE
- REG_AMPDU_BURST_MODE_8723B
- REG_AMPDU_MAX_LENGTH_8723B
- REG_AMPDU_MAX_LENGTH_8812
- REG_AMPDU_MAX_TIME
- REG_AMPDU_MAX_TIME_8723B
- REG_AMPDU_MAX_TIME_V1
- REG_AMPDU_MIN_SPACE
- REG_ANALOG_AUDIO_DETECTED
- REG_ANALOG_CHROMA_DETECTED
- REG_ANALOG_LUMA_DETECTED
- REG_ANAPAR
- REG_ANAPARLDO_POW_MAC
- REG_ANAPAR_XTAL_0
- REG_ANA_GENERAL
- REG_ANTMAP
- REG_ANTMAP0
- REG_ANTWT
- REG_ANTWTPD
- REG_APE_PLL_CTRL_EXT
- REG_APIEXCP_OFFSET
- REG_APIMASK_OFFSET
- REG_API_V
- REG_APOLL_TIMER_CTRL
- REG_APSD_CTRL
- REG_APS_FSMCO
- REG_APS_FSMCO_8723B
- REG_ARC_CLKCTL
- REG_ARFR0
- REG_ARFR0_8723B
- REG_ARFR1
- REG_ARFR1_8723B
- REG_ARFR1_V1
- REG_ARFR2
- REG_ARFR3
- REG_ARFR4
- REG_ARFR5
- REG_ARFRH0
- REG_ARFRH1_V1
- REG_ARFRH4
- REG_ARFRH5
- REG_ARG0
- REG_ARG1
- REG_ARG2
- REG_ARG3
- REG_ARG4
- REG_ARG5
- REG_ARGUMENT
- REG_ARRAY_SIZE
- REG_ARR_CCM
- REG_AR_BASE
- REG_AR_FAULT_ADDR
- REG_ASC
- REG_ASR56K
- REG_ASR76K
- REG_ASRCCR
- REG_ASRCDR
- REG_ASRCDR1
- REG_ASRCDR2
- REG_ASRCFG
- REG_ASRCNCR
- REG_ASRCSR
- REG_ASRCTR
- REG_ASRDI
- REG_ASRDIA
- REG_ASRDIB
- REG_ASRDIC
- REG_ASRDO
- REG_ASRDOA
- REG_ASRDOB
- REG_ASRDOC
- REG_ASRDx
- REG_ASRFST
- REG_ASRFSTA
- REG_ASRFSTB
- REG_ASRFSTC
- REG_ASRIDRH
- REG_ASRIDRHA
- REG_ASRIDRHB
- REG_ASRIDRHC
- REG_ASRIDRL
- REG_ASRIDRLA
- REG_ASRIDRLB
- REG_ASRIDRLC
- REG_ASRIER
- REG_ASRMCR
- REG_ASRMCR1
- REG_ASRMCR1A
- REG_ASRMCR1B
- REG_ASRMCR1C
- REG_ASRMCRA
- REG_ASRMCRB
- REG_ASRMCRC
- REG_ASRPM1
- REG_ASRPM2
- REG_ASRPM3
- REG_ASRPM4
- REG_ASRPM5
- REG_ASRRA
- REG_ASRRB
- REG_ASRRC
- REG_ASRSTR
- REG_ASRTFR1
- REG_ASSIGN
- REG_ASSOEAR0
- REG_ASSOEAR1
- REG_ASSOEAR2
- REG_ASSOEAR3
- REG_ASSOEAR4
- REG_ASSOEAR5
- REG_ASSOEAR6
- REG_ASSOEAR7
- REG_ASSOSAR0
- REG_ASSOSAR1
- REG_ASTAT
- REG_ASTAT3
- REG_ATIMWND
- REG_ATIMWND_1
- REG_ATIMWND_8723B
- REG_AT_COMPAT
- REG_AUDCFG
- REG_AUDIO_BEEP
- REG_AUDIO_CLOCK
- REG_AUDIO_DIV
- REG_AUDIO_ENABLE
- REG_AUDIO_FLAGS
- REG_AUDIO_FREQ
- REG_AUDIO_LAYOUT
- REG_AUDIO_MUTE
- REG_AUDIO_OUT_ENABLE
- REG_AUDIO_OUT_HIZ
- REG_AUDIO_PATH
- REG_AUDIO_VOLUME
- REG_AUTH_BYTECNT0
- REG_AUTH_BYTECNT1
- REG_AUTH_BYTECNT2
- REG_AUTH_BYTECNT3
- REG_AUTH_EXP_MAC0
- REG_AUTH_EXP_MAC1
- REG_AUTH_EXP_MAC2
- REG_AUTH_EXP_MAC3
- REG_AUTH_EXP_MAC4
- REG_AUTH_EXP_MAC5
- REG_AUTH_EXP_MAC6
- REG_AUTH_EXP_MAC7
- REG_AUTH_INFO_NONCE0
- REG_AUTH_INFO_NONCE1
- REG_AUTH_INFO_NONCE2
- REG_AUTH_INFO_NONCE3
- REG_AUTH_IV0
- REG_AUTH_IV1
- REG_AUTH_IV10
- REG_AUTH_IV11
- REG_AUTH_IV12
- REG_AUTH_IV13
- REG_AUTH_IV14
- REG_AUTH_IV15
- REG_AUTH_IV2
- REG_AUTH_IV3
- REG_AUTH_IV4
- REG_AUTH_IV5
- REG_AUTH_IV6
- REG_AUTH_IV7
- REG_AUTH_IV8
- REG_AUTH_IV9
- REG_AUTH_KEY0
- REG_AUTH_KEY1
- REG_AUTH_KEY10
- REG_AUTH_KEY11
- REG_AUTH_KEY12
- REG_AUTH_KEY13
- REG_AUTH_KEY14
- REG_AUTH_KEY15
- REG_AUTH_KEY2
- REG_AUTH_KEY3
- REG_AUTH_KEY4
- REG_AUTH_KEY5
- REG_AUTH_KEY6
- REG_AUTH_KEY7
- REG_AUTH_KEY8
- REG_AUTH_KEY9
- REG_AUTH_SEG_CFG
- REG_AUTH_SEG_SIZE
- REG_AUTH_SEG_START
- REG_AUTOBAUD
- REG_AUTOMODES
- REG_AUTOSWITCH_MASK
- REG_AUTOTUNE
- REG_AUTO_CFG
- REG_AUTO_HIBERNATE_IDLE_TIMER
- REG_AUTO_LLT
- REG_AUTO_LLT_V1
- REG_AUTO_RESET
- REG_AUTO_STATUS
- REG_AUTO_TX1
- REG_AUTO_TX2
- REG_AVB_STRATEGY__2
- REG_AVGU
- REG_AVGV
- REG_AVGY
- REG_AVG_WINDOW_END_X_HIGH
- REG_AVG_WINDOW_END_X_LOW
- REG_AVG_WINDOW_END_Y_HIGH
- REG_AVG_WINDOW_END_Y_LOW
- REG_AVID_START_PIXEL_LSB
- REG_AVID_START_PIXEL_MSB
- REG_AVID_STOP_PIXEL_LSB
- REG_AVID_STOP_PIXEL_MSB
- REG_AVPLLCTL0
- REG_AVPLLCTL31
- REG_AVPLLCTL62
- REG_AVSIZE
- REG_AVSTART
- REG_AWB_AUTO
- REG_AWB_B_GAIN_H
- REG_AWB_B_GAIN_L
- REG_AWB_CLOUDY
- REG_AWB_CTRL00
- REG_AWB_CTRL01
- REG_AWB_CTRL02
- REG_AWB_CTRL03
- REG_AWB_CTRL04
- REG_AWB_CTRL12
- REG_AWB_CTRL13
- REG_AWB_CTRL14
- REG_AWB_DAYLIGHT
- REG_AWB_FLUORESCENT_1
- REG_AWB_FLUORESCENT_2
- REG_AWB_G_GAIN_H
- REG_AWB_G_GAIN_L
- REG_AWB_HORIZON
- REG_AWB_INCANDESCENT
- REG_AWB_LEDLIGHT
- REG_AWB_LOCAL_LIMIT
- REG_AWB_LOCK
- REG_AWB_MANUAL_CONTROL
- REG_AWB_PRESET
- REG_AWB_R_GAIN_H
- REG_AWB_R_GAIN_L
- REG_AWB_SHADE
- REG_AWB_UNLOCK
- REG_AW_FAULT_ADDR
- REG_AX
- REG_AXXX_CP_BIN_MASK_HI
- REG_AXXX_CP_BIN_MASK_LO
- REG_AXXX_CP_BIN_SELECT_HI
- REG_AXXX_CP_BIN_SELECT_LO
- REG_AXXX_CP_CSQ_AVAIL
- REG_AXXX_CP_CSQ_IB1_STAT
- REG_AXXX_CP_CSQ_IB2_STAT
- REG_AXXX_CP_CSQ_RB_STAT
- REG_AXXX_CP_DEBUG
- REG_AXXX_CP_IB1_BASE
- REG_AXXX_CP_IB1_BUFSZ
- REG_AXXX_CP_IB2_BASE
- REG_AXXX_CP_IB2_BUFSZ
- REG_AXXX_CP_INT_ACK
- REG_AXXX_CP_INT_CNTL
- REG_AXXX_CP_INT_STATUS
- REG_AXXX_CP_MEQ_AVAIL
- REG_AXXX_CP_MEQ_STAT
- REG_AXXX_CP_MEQ_THRESHOLDS
- REG_AXXX_CP_ME_CF_EVENT_ADDR
- REG_AXXX_CP_ME_CF_EVENT_DATA
- REG_AXXX_CP_ME_CF_EVENT_SRC
- REG_AXXX_CP_ME_CNTL
- REG_AXXX_CP_ME_NRT_ADDR
- REG_AXXX_CP_ME_NRT_DATA
- REG_AXXX_CP_ME_PS_EVENT_ADDR
- REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM
- REG_AXXX_CP_ME_PS_EVENT_DATA
- REG_AXXX_CP_ME_PS_EVENT_DATA_SWM
- REG_AXXX_CP_ME_PS_EVENT_SRC
- REG_AXXX_CP_ME_RAM_DATA
- REG_AXXX_CP_ME_RAM_RADDR
- REG_AXXX_CP_ME_RAM_WADDR
- REG_AXXX_CP_ME_RDADDR
- REG_AXXX_CP_ME_STATUS
- REG_AXXX_CP_ME_VS_EVENT_ADDR
- REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM
- REG_AXXX_CP_ME_VS_EVENT_DATA
- REG_AXXX_CP_ME_VS_EVENT_DATA_SWM
- REG_AXXX_CP_ME_VS_EVENT_SRC
- REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR
- REG_AXXX_CP_ME_VS_FETCH_DONE_DATA
- REG_AXXX_CP_ME_VS_FETCH_DONE_SRC
- REG_AXXX_CP_MIU_TAG_STAT
- REG_AXXX_CP_NON_PREFETCH_CNTRS
- REG_AXXX_CP_QUEUE_THRESHOLDS
- REG_AXXX_CP_RB_BASE
- REG_AXXX_CP_RB_CNTL
- REG_AXXX_CP_RB_RPTR
- REG_AXXX_CP_RB_RPTR_ADDR
- REG_AXXX_CP_RB_RPTR_WR
- REG_AXXX_CP_RB_WPTR
- REG_AXXX_CP_RB_WPTR_BASE
- REG_AXXX_CP_RB_WPTR_DELAY
- REG_AXXX_CP_SCRATCH_REG0
- REG_AXXX_CP_SCRATCH_REG1
- REG_AXXX_CP_SCRATCH_REG2
- REG_AXXX_CP_SCRATCH_REG3
- REG_AXXX_CP_SCRATCH_REG4
- REG_AXXX_CP_SCRATCH_REG5
- REG_AXXX_CP_SCRATCH_REG6
- REG_AXXX_CP_SCRATCH_REG7
- REG_AXXX_CP_STAT
- REG_AXXX_CP_STATE_DEBUG_DATA
- REG_AXXX_CP_STATE_DEBUG_INDEX
- REG_AXXX_CP_STQ_AVAIL
- REG_AXXX_CP_STQ_ST_STAT
- REG_AXXX_CP_ST_BASE
- REG_AXXX_CP_ST_BUFSZ
- REG_AXXX_SCRATCH_ADDR
- REG_AXXX_SCRATCH_UMSK
- REG_A_BASE
- REG_B
- REG_B8
- REG_BACAMCMD
- REG_BACAMCONTENT
- REG_BACKDOOR_DBI_DATA
- REG_BACKDOOR_DBI_RDATA
- REG_BACKDOOR_DBI_WDATA
- REG_BACKEND_AGC_CONTROL
- REG_BACKLIGHT_CTRL
- REG_BACK_PRESSURE
- REG_BAND
- REG_BANDWIDTH
- REG_BANK
- REG_BANK_J
- REG_BANK_K
- REG_BANK_T
- REG_BANK_W
- REG_BANK_X
- REG_BANK_Y
- REG_BAR
- REG_BAR_MODE_CTRL
- REG_BAR_MODE_CTRL_8723B
- REG_BASE
- REG_BASEBAND_CTRL
- REG_BASE_ADDR
- REG_BASE_ADDR_CSEQCIO
- REG_BASE_ADDR_EXSI
- REG_BASE_CPU_NUMBER
- REG_BAT_CELL_COUNT
- REG_BAT_CHARGE
- REG_BAT_CHARGE_STATUS
- REG_BAT_CURRENT_HIGH
- REG_BAT_CURRENT_LOW
- REG_BAT_DESIGN_CAP_HIGH
- REG_BAT_DESIGN_CAP_LOW
- REG_BAT_DESIGN_VOL_HIGH
- REG_BAT_DESIGN_VOL_LOW
- REG_BAT_FULLCHG_CAP_HIGH
- REG_BAT_FULLCHG_CAP_LOW
- REG_BAT_POWER
- REG_BAT_RELATIVE_CAP_HIGH
- REG_BAT_RELATIVE_CAP_LOW
- REG_BAT_STATE
- REG_BAT_STATUS
- REG_BAT_TEMPERATURE_HIGH
- REG_BAT_TEMPERATURE_LOW
- REG_BAT_VENDOR
- REG_BAT_VOLTAGE_HIGH
- REG_BAT_VOLTAGE_LOW
- REG_BAUDRATE
- REG_BAVE
- REG_BAVG
- REG_BAYER10
- REG_BAYER8
- REG_BBAT
- REG_BBIAS
- REG_BBPSF_CTRL
- REG_BBREG0
- REG_BBREG1
- REG_BBREG2
- REG_BBREG3
- REG_BBREG4
- REG_BBREG6
- REG_BB_ACCEESS_CTRL
- REG_BB_ACCESS_DATA
- REG_BB_PAD_CTRL
- REG_BCICTL2
- REG_BCM6328_OTP
- REG_BCNDMATIM
- REG_BCNDMATIM_8723B
- REG_BCNQ1_BDNY
- REG_BCNQ1_BDNY_V1
- REG_BCNQ_BDNY
- REG_BCNQ_BDNY_V1
- REG_BCNQ_DESA
- REG_BCNQ_DESA_8723B
- REG_BCNQ_INFO
- REG_BCNQ_INFORMATION
- REG_BCNQ_INFORMATION_8723B
- REG_BCNTCFG
- REG_BCNTCFG_8723B
- REG_BCN_CTRL
- REG_BCN_CTRL_1
- REG_BCN_CTRL_1_8723B
- REG_BCN_CTRL_8723B
- REG_BCN_CTRL_CLINT0
- REG_BCN_INTERVAL
- REG_BCN_INTERVAL_8723B
- REG_BCN_MAX_ERR
- REG_BCN_MAX_ERR_8723B
- REG_BCN_PREDL_ITV
- REG_BCN_PSR_RPT
- REG_BCN_PSR_RPT_8723B
- REG_BCTL
- REG_BD50MAX
- REG_BD50ST
- REG_BD60MAX
- REG_BD60ST
- REG_BEACON_CTRL
- REG_BEACON_CTRL_1
- REG_BEACON_DMA_TIME
- REG_BEACON_TCFG
- REG_BEQ_DESA
- REG_BEQ_DESA_8723B
- REG_BEQ_INFO
- REG_BEQ_INFORMATION
- REG_BEQ_INFORMATION_8723B
- REG_BEQ_TXBD_IDX
- REG_BEQ_TXBD_NUM
- REG_BER_AVAIL
- REG_BER_BIT
- REG_BER_PKT
- REG_BER_RST
- REG_BE_ADMTIME
- REG_BFMEE_SEL
- REG_BFMEE_SEL_8723B
- REG_BFMER0_INFO
- REG_BFMER0_INFO_8723B
- REG_BFMER1_INFO
- REG_BFMER1_INFO_8723B
- REG_BGAIN
- REG_BGCTRL
- REG_BGR_BIAS
- REG_BIM_BUFFER_ADDR
- REG_BIM_BUFFER_DATA_HI
- REG_BIM_BUFFER_DATA_LOW
- REG_BIM_CFG
- REG_BIM_DIAG
- REG_BIM_DIAG_MUX
- REG_BIM_LOCAL_DEV_EN
- REG_BIM_RAM_BIST
- REG_BIST0_CTRL
- REG_BIST1_CTRL
- REG_BIST_8BIT_PATTERN
- REG_BIST_CTRL
- REG_BIST_DURATION_0
- REG_BIST_DURATION_1
- REG_BIST_DURATION_2
- REG_BIST_ROM_RPT
- REG_BIST_RPT
- REG_BIST_SCAN
- REG_BIST_TEST_SEL
- REG_BIST_VIDEO_MODE
- REG_BIT
- REG_BITRATE_LSB
- REG_BITRATE_MSB
- REG_BIT_WAIT
- REG_BKQ_DESA
- REG_BKQ_DESA_8723B
- REG_BKQ_INFO
- REG_BKQ_INFORMATION
- REG_BKQ_INFORMATION_8723B
- REG_BKQ_TXBD_IDX
- REG_BKQ_TXBD_NUM
- REG_BLADE_ID
- REG_BLKEOL_MODE
- REG_BLKERR_POL
- REG_BLKLINE_MODE
- REG_BLKSIZE
- REG_BLK_BU
- REG_BLK_GY
- REG_BLK_MODE_BLANKING_PKT
- REG_BLK_MODE_LP
- REG_BLK_MODE_NULL_PKT
- REG_BLK_RV
- REG_BLOCK_EN
- REG_BLOCK_LOCK
- REG_BLUE
- REG_BLUETOOTH
- REG_BLUE_GAIN
- REG_BL_CONF_1
- REG_BL_CONF_2
- REG_BL_CONF_3
- REG_BL_CONF_4
- REG_BL_ERROR
- REG_BL_FILE
- REG_BL_STATUS
- REG_BMCO
- REG_BMCTL
- REG_BMCTL_ENABLE_RX
- REG_BMCTL_ENABLE_TX
- REG_BMSTS
- REG_BMSTS_RX_ACTIVE
- REG_BM_CFG
- REG_BOOST
- REG_BOOTLOADER_V
- REG_BOS
- REG_BOTH_EDGE
- REG_BP
- REG_BRGCTRL_OFFSET
- REG_BRIGHT
- REG_BRIGHTNESS
- REG_BROADCASTADRS
- REG_BROC_COUNTER
- REG_BRT
- REG_BRT_A
- REG_BRT_B
- REG_BSSID
- REG_BSSID1
- REG_BSSID1_8723B
- REG_BSSID_8723B
- REG_BSTAT
- REG_BT_COEX_BRK_TABLE
- REG_BT_COEX_TABLE
- REG_BT_COEX_TABLE0
- REG_BT_COEX_TABLE1
- REG_BT_COEX_TABLE2
- REG_BT_COEX_TABLE3
- REG_BT_COEX_TABLE4
- REG_BT_COEX_TABLE_8723B
- REG_BT_COEX_TABLE_H
- REG_BT_COEX_TABLE_H1
- REG_BT_COEX_TABLE_H2
- REG_BT_COEX_TABLE_H3
- REG_BT_COEX_V2
- REG_BT_CONTROL_8723BU
- REG_BT_PATCH_STATUS_8723B
- REG_BT_STAT_CTRL
- REG_BT_TDMA_TIME
- REG_BT_WIFI_ANTENNA_SWITCH_8723B
- REG_BUCK
- REG_BUCKE
- REG_BUCKI
- REG_BUFFERCFG
- REG_BUFFER_OUT
- REG_BUFWIN
- REG_BUF_ADDR
- REG_BUF_DATA
- REG_BUS
- REG_BUSPD
- REG_BUS_WIDTH
- REG_BWOPMODE
- REG_BW_OPMODE
- REG_BYPASS_CCI
- REG_BYPASS_DEINTERLEAVER
- REG_BYTES_PER_IRQ_WORD
- REG_B_AVE
- REG_C
- REG_C0
- REG_C2HEVT
- REG_C2HEVT_CLEAR
- REG_C2HEVT_CLEAR_8723B
- REG_C2HEVT_CMD_ID_8723B
- REG_C2HEVT_CMD_LEN_8723B
- REG_C2HEVT_CMD_LEN_88XX
- REG_C2HEVT_CMD_SEQ_88XX
- REG_C2HEVT_MSG_NORMAL
- REG_C2HEVT_MSG_NORMAL_8723B
- REG_C2HEVT_MSG_TEST
- REG_C2hEVT_CMD_CONTENT_88XX
- REG_C38_TH
- REG_CACHE_BASE
- REG_CACHE_SIZE
- REG_CAF_STATUS_FIND_SEARCH_DIR
- REG_CAF_STATUS_FOCUSED
- REG_CAF_STATUS_FOCUSING
- REG_CAF_STATUS_UNFOCUSED
- REG_CALB32K_CTRL
- REG_CALIBRATE
- REG_CALIB_PHASE_LIGHT_A
- REG_CALIB_PHASE_LIGHT_B
- REG_CALIB_PHASE_TEMP_A
- REG_CALIB_PHASE_TEMP_B
- REG_CAL_CFG
- REG_CAL_TIMER
- REG_CAL_TIMER_8723B
- REG_CAMCMD
- REG_CAMCMD_8723B
- REG_CAMDBG
- REG_CAMDBG_8723B
- REG_CAMERA_CONTROL
- REG_CAMERA_STATUS
- REG_CAMREAD
- REG_CAMREAD_8723B
- REG_CAMWRITE
- REG_CAMWRITE_8723B
- REG_CAM_CMD
- REG_CAM_DEBUG
- REG_CAM_READ
- REG_CAM_WRITE
- REG_CAPACITY
- REG_CAPACITY_LEVEL
- REG_CAPA_160MHZ_ALLOWED
- REG_CAPA_40MHZ_FORBIDDEN
- REG_CAPA_80MHZ_ALLOWED
- REG_CAPA_BF_CCD_HIGH_BAND
- REG_CAPA_BF_CCD_LOW_BAND
- REG_CAPA_DC_HIGH_ENABLED
- REG_CAPA_MCS_8_ALLOWED
- REG_CAPA_MCS_9_ALLOWED
- REG_CAPLENGTH
- REG_CAPTURE
- REG_CAP_ANTI_SHAKE
- REG_CAP_NONE
- REG_CAP_START_MAIN
- REG_CAP_START_THUMB
- REG_CARD_ID_AND_BUILD
- REG_CARD_RESET
- REG_CARD_STATUS
- REG_CARRIER_OFFSET
- REG_CAWR
- REG_CA_I2S
- REG_CBCR
- REG_CBER_AVAIL
- REG_CBER_BIT
- REG_CBER_ERR
- REG_CBER_RST
- REG_CBUS3_CNVT
- REG_CBUS_DISC_INTR0
- REG_CBUS_DISC_INTR0_MASK
- REG_CBUS_INT_0
- REG_CBUS_INT_0_MASK
- REG_CBUS_INT_1
- REG_CBUS_INT_1_MASK
- REG_CBUS_LINK_CTRL_8
- REG_CBUS_MSC_COMPAT_CTRL
- REG_CBUS_RX_DISC_INT0
- REG_CBUS_RX_DISC_INT0_MASK
- REG_CBUS_STATUS
- REG_CBUS_VENDOR_ID
- REG_CCA1
- REG_CCA2
- REG_CCA2ND
- REG_CCAEDTH
- REG_CCAMSK
- REG_CCANRX
- REG_CCASEL
- REG_CCK0_AFE_SETTING
- REG_CCK0_SYSTEM
- REG_CCKPATH
- REG_CCKSB
- REG_CCKTXONLY
- REG_CCK_CHECK
- REG_CCK_CHECK_8723B
- REG_CCK_FACNT
- REG_CCK_SOURCE
- REG_CCLK_ON
- REG_CCONR
- REG_CCR
- REG_CCR1_CONFIG4_MASK
- REG_CCR1_CONFIG4_OFFSET
- REG_CCR2_AFREQ_MASK
- REG_CCR2_AFREQ_OFFSET
- REG_CCR2_DFREQ_MASK
- REG_CCR2_DFREQ_OFFSET
- REG_CDDTXP
- REG_CDR
- REG_CDR0
- REG_CDR_CFG
- REG_CEC_CAL_XOSC_CTRL1
- REG_CEC_CLK
- REG_CEC_DES_FREQ2
- REG_CEC_ENAMODS
- REG_CEC_FRO_IM_CLK_CTRL
- REG_CEC_INTSTATUS
- REG_CEC_RXSHPDINT
- REG_CEC_RXSHPDINTENA
- REG_CEC_RXSHPDLEV
- REG_CENTRAL_TAP
- REG_CER
- REG_CFG
- REG_CFG1
- REG_CFG2
- REG_CFG_RCGR
- REG_CFIS
- REG_CFIXB_SEPIA
- REG_CFIXR_SEPIA
- REG_CGR1_GODL_MASK
- REG_CGR1_GODL_OFFSET
- REG_CGR1_GODR_MASK
- REG_CGR1_GODR_OFFSET
- REG_CGR2_GO1R_MASK
- REG_CGR2_GO1R_OFFSET
- REG_CGR3_GO1L_MASK
- REG_CGR3_GO1L_OFFSET
- REG_CGU_DBG_SEL
- REG_CH
- REG_CHANGE
- REG_CHANNEL_MASK
- REG_CHARGECONFIG
- REG_CHARGEDELAY
- REG_CHECKSUM
- REG_CHECK_SIGNAL
- REG_CHIPID
- REG_CHIPREV
- REG_CHIP_ID
- REG_CHIP_ID0
- REG_CHIP_ID0__1
- REG_CHIP_ID1
- REG_CHIP_ID1__1
- REG_CHIP_ID2__1
- REG_CHIP_ID3__1
- REG_CHIP_ID_41
- REG_CHIP_ID_42
- REG_CHIP_ID_B
- REG_CHIP_ID_HIGH
- REG_CHIP_ID_LOW
- REG_CHIP_ID_LSB
- REG_CHIP_ID_MSB
- REG_CHIP_INIT
- REG_CHIP_MODE
- REG_CHIP_REVCODE
- REG_CHLF
- REG_CHROMA_CONTROL1
- REG_CHROMA_CONTROL2
- REG_CHROMA_OFF
- REG_CHROMA_ON
- REG_CH_FREQ0
- REG_CH_FREQ1
- REG_CH_FREQ2
- REG_CH_STAT_B
- REG_CIP_CTRL00
- REG_CIP_CTRL01
- REG_CIR_ITHR
- REG_CIR_NTHR
- REG_CI_RLM_AVG
- REG_CI_SCHED_CFG
- REG_CKG1
- REG_CKG2
- REG_CLEAR
- REG_CLEARGPIODATAOUT1
- REG_CLEARGPIODATAOUT2
- REG_CLEARGPIODATAOUT3
- REG_CLEAR_HOST_INT
- REG_CLEAR_LOST_LOCK
- REG_CLK
- REG_CLKCTRL
- REG_CLKDIV
- REG_CLKDIV_DIV
- REG_CLKDIV_DIV__MASK
- REG_CLKEN
- REG_CLKENABLE
- REG_CLKF
- REG_CLKRC
- REG_CLKSELECT0
- REG_CLKSELECT1
- REG_CLKSELECT2
- REG_CLKSELECT3
- REG_CLKSWITCH0
- REG_CLKSWITCH1
- REG_CLKTRK
- REG_CLK_A_RATE
- REG_CLK_A_STATUS
- REG_CLK_B_RATE
- REG_CLK_B_STATUS
- REG_CLK_CFG
- REG_CLK_DIV_FS
- REG_CLK_DIV_HS
- REG_CLK_GATING_CTRL
- REG_CLK_MAX_RATE
- REG_CLK_MIN_RATE
- REG_CLK_OUT_CFG
- REG_CLOCK
- REG_CLOCK_CONTROL
- REG_CLR
- REG_CLR_BIT
- REG_CL_INTRD
- REG_CMATRIX_BASE
- REG_CMATRIX_SIGN
- REG_CMBDISDMA_TIMER
- REG_CMB_RX_PKT_CNT
- REG_CMB_TX_PKT_CNT
- REG_CMB_WRITE_TH
- REG_CMB_WRITE_TIMER
- REG_CMD
- REG_CMDBUF0_ADDR
- REG_CMDBUF1_ADDR
- REG_CMDBUF_ADDR
- REG_CMDQ_DESA_NODEF
- REG_CMDRD_ADDR
- REG_CMDRD_ADDRH
- REG_CMDRD_ADDRL
- REG_CMDRD_PAGE
- REG_CMDWR_ADDR
- REG_CMDWR_ADDRH
- REG_CMDWR_ADDRL
- REG_CMDWR_PAGE
- REG_CMD_ABORT
- REG_CMD_ACK
- REG_CMD_BUF
- REG_CMD_CLEARPC
- REG_CMD_CLEARTX
- REG_CMD_CONT
- REG_CMD_ESTAR
- REG_CMD_MASTEREN
- REG_CMD_MBOX_ADDRESS
- REG_CMD_NACK
- REG_CMD_RCGR
- REG_CMD_RESET
- REG_CMD_RXDIS
- REG_CMD_RXEN
- REG_CMD_START
- REG_CMD_STOP
- REG_CMD_TXDIS
- REG_CMD_TXEN
- REG_CMTP_REG10
- REG_CMTP_REG11
- REG_CMTP_REG6
- REG_CMTP_REG7
- REG_CMTP_REG8
- REG_CMTP_REG9
- REG_CMTP_REGA
- REG_CMTP_REGB
- REG_CMTP_REGC
- REG_CMTP_REGD
- REG_CMTP_REGE
- REG_CMTP_REGF
- REG_CMU_RESET_ISP_SYS_PWR_REG
- REG_CMU_SYSCLK_ISP_SYS_PWR_REG
- REG_CMX_MISC_CTRL
- REG_CMX_SIGN
- REG_CM_CFG
- REG_CNTL1
- REG_CNTL2
- REG_CNTL3
- REG_CNTR0_IV0
- REG_CNTR1_IV1
- REG_CNTR2_IV2
- REG_CNTR3_IV3
- REG_CNTR_MASK
- REG_CNTR_MASK0
- REG_CNTR_MASK1
- REG_CNTR_MASK2
- REG_CNT_CTRL
- REG_COARSE_INTEGRATION_TIME_
- REG_COC_CTL0
- REG_COC_CTL1
- REG_COC_CTL11
- REG_COC_CTL14
- REG_COC_CTL15
- REG_COC_CTL17
- REG_COC_CTL18
- REG_COC_CTL19
- REG_COC_CTL1A
- REG_COC_CTL2
- REG_COC_CTL3
- REG_COC_CTL6
- REG_COC_CTL7
- REG_COC_CTL9
- REG_COC_CTLA
- REG_COC_CTLB
- REG_COC_CTLC
- REG_COC_CTLD
- REG_COC_CTLE
- REG_COC_CTLF
- REG_COC_INTR
- REG_COC_INTR_MASK
- REG_COC_MISC_CTL0
- REG_COC_STAT_0
- REG_COC_STAT_1
- REG_COC_STAT_2
- REG_COC_STAT_3
- REG_COC_STAT_4
- REG_COC_STAT_5
- REG_COLOR_EFFECT_OFF
- REG_COLOR_EFFECT_ON
- REG_COLOR_KILLER
- REG_COM1
- REG_COM10
- REG_COM11
- REG_COM12
- REG_COM13
- REG_COM14
- REG_COM15
- REG_COM16
- REG_COM17
- REG_COM2
- REG_COM21
- REG_COM22
- REG_COM23
- REG_COM3
- REG_COM4
- REG_COM5
- REG_COM6
- REG_COM7
- REG_COM8
- REG_COM9
- REG_COMA
- REG_COMB
- REG_COMC
- REG_COMD
- REG_COME
- REG_COMF
- REG_COMG
- REG_COMH
- REG_COMI
- REG_COMJ
- REG_COMK
- REG_COML
- REG_COMM
- REG_COMMAND
- REG_COMMAND_MAILBOX_PTR
- REG_COMMAND_RX_BUF_ONE
- REG_COMMAND_RX_BUF_TWO
- REG_COMMAND_RX_WIN_ONE
- REG_COMMAND_RX_WIN_TWO
- REG_COMMAND_TX_BUF_ONE
- REG_COMMAND_TX_BUF_TWO
- REG_COMMECNT
- REG_COMPARE
- REG_COMPARE_1
- REG_COMPARE_2
- REG_COMP_PB_SATURATION
- REG_COMP_PR_SATURATION
- REG_COMP_Y_BRIGHTNESS
- REG_COMP_Y_CONTRAST
- REG_CON
- REG_CON0
- REG_CON1
- REG_CONF1
- REG_CONFIG
- REG_CONFIG1
- REG_CONFIG2
- REG_CONFIG3
- REG_CONFIG4
- REG_CONFIG5
- REG_CONFIG_ANT_A
- REG_CONFIG_ANT_B
- REG_CONFIG_CLK_32k_ALTSEL
- REG_CONFIG_CLK_DIV_MASK
- REG_CONFIG_CLK_EN
- REG_CONFIG_CLK_SEL_MASK
- REG_CONFIG_FLIP_TEST_PATTERN
- REG_CONFIG_MIRROR_FLIP
- REG_CONFIG_TEST_TRIG
- REG_CONTRAS
- REG_CONTRAST
- REG_CONTROL
- REG_CONTROL1
- REG_CONTROL1_CAP_SEL
- REG_CONTROL1_STOP
- REG_CONTROL3
- REG_CONTROL3_BLF
- REG_CONTROL3_PM_BLD
- REG_CONTROL3_PM_DSM
- REG_CONTROL3_PM_MASK
- REG_CONTROL3_PM_VDD
- REG_CONTROLLER_CAPABILITIES
- REG_CONTROLLER_DEV_ID
- REG_CONTROLLER_ENABLE
- REG_CONTROLLER_PROD_ID
- REG_CONTROLLER_STATUS
- REG_CONTROL_BAUD_RATE_115200
- REG_CONTROL_BAUD_RATE_230400
- REG_CONTROL_BAUD_RATE_460800
- REG_CONTROL_BAUD_RATE_57600
- REG_CONTROL_BT_ON
- REG_CONTROL_BT_RESET
- REG_CONTROL_BT_RES_PU
- REG_CONTROL_CARD_RESET
- REG_CONTROL_INTERRUPT
- REG_CONTROL_RTS
- REG_CONT_UNMUTE_INPUTS
- REG_CONT_VALSMPTE
- REG_CONV_RES
- REG_CON_ACTACK
- REG_CON_EN
- REG_CON_LASTACK
- REG_CON_MOD
- REG_CON_MOD_MASK
- REG_CON_MOD_REGISTER_RX
- REG_CON_MOD_REGISTER_TX
- REG_CON_MOD_RX
- REG_CON_MOD_TX
- REG_CON_SDA_CFG
- REG_CON_START
- REG_CON_STA_CFG
- REG_CON_STOP
- REG_CON_STO_CFG
- REG_CON_TUNING_MASK
- REG_CORE_TABLE_OFFSET
- REG_COUNT
- REG_COUNTER_HI
- REG_COUNTER_LO
- REG_CPLD_CONFIG
- REG_CPLL_SPEED_CONTROL
- REG_CPSR
- REG_CPUPLLCTL0
- REG_CPUPLLCTL4
- REG_CPU_DMEM_CON
- REG_CPU_MGQ_INFORMATION
- REG_CPU_STATE_ADDR
- REG_CPU_TRANSFER_SEL
- REG_CPWM
- REG_CPWM_8723B
- REG_CP_BLIT_0
- REG_CP_BLIT_1
- REG_CP_BLIT_2
- REG_CP_BLIT_3
- REG_CP_BLIT_4
- REG_CP_COMPUTE_CHECKPOINT_0
- REG_CP_COMPUTE_CHECKPOINT_1
- REG_CP_COMPUTE_CHECKPOINT_2
- REG_CP_COMPUTE_CHECKPOINT_3
- REG_CP_COMPUTE_CHECKPOINT_4
- REG_CP_COMPUTE_CHECKPOINT_5
- REG_CP_COMPUTE_CHECKPOINT_6
- REG_CP_COMPUTE_CHECKPOINT_7
- REG_CP_COND_WRITE5_0
- REG_CP_COND_WRITE5_1
- REG_CP_COND_WRITE5_2
- REG_CP_COND_WRITE5_3
- REG_CP_COND_WRITE5_4
- REG_CP_COND_WRITE5_5
- REG_CP_COND_WRITE5_6
- REG_CP_COND_WRITE5_7
- REG_CP_COND_WRITE_0
- REG_CP_COND_WRITE_1
- REG_CP_COND_WRITE_2
- REG_CP_COND_WRITE_3
- REG_CP_COND_WRITE_4
- REG_CP_COND_WRITE_5
- REG_CP_DISPATCH_COMPUTE_0
- REG_CP_DISPATCH_COMPUTE_1
- REG_CP_DISPATCH_COMPUTE_2
- REG_CP_DISPATCH_COMPUTE_3
- REG_CP_DRAW_INDX_0
- REG_CP_DRAW_INDX_1
- REG_CP_DRAW_INDX_2
- REG_CP_DRAW_INDX_2_0
- REG_CP_DRAW_INDX_2_1
- REG_CP_DRAW_INDX_2_2
- REG_CP_DRAW_INDX_3
- REG_CP_DRAW_INDX_4
- REG_CP_DRAW_INDX_OFFSET_0
- REG_CP_DRAW_INDX_OFFSET_1
- REG_CP_DRAW_INDX_OFFSET_2
- REG_CP_DRAW_INDX_OFFSET_3
- REG_CP_DRAW_INDX_OFFSET_4
- REG_CP_DRAW_INDX_OFFSET_5
- REG_CP_EVENT_WRITE_0
- REG_CP_EVENT_WRITE_1
- REG_CP_EVENT_WRITE_2
- REG_CP_EVENT_WRITE_3
- REG_CP_EXEC_CS_0
- REG_CP_EXEC_CS_1
- REG_CP_EXEC_CS_2
- REG_CP_EXEC_CS_3
- REG_CP_LOAD_STATE4_0
- REG_CP_LOAD_STATE4_1
- REG_CP_LOAD_STATE4_2
- REG_CP_LOAD_STATE6_0
- REG_CP_LOAD_STATE6_1
- REG_CP_LOAD_STATE6_2
- REG_CP_LOAD_STATE_0
- REG_CP_LOAD_STATE_1
- REG_CP_MEM_TO_MEM_0
- REG_CP_MEM_TO_REG_0
- REG_CP_MEM_TO_REG_1
- REG_CP_MEM_TO_REG_2
- REG_CP_PERFCOUNTER_ACTION_0
- REG_CP_PERFCOUNTER_ACTION_1
- REG_CP_PERFCOUNTER_ACTION_2
- REG_CP_REG_TO_MEM_0
- REG_CP_REG_TO_MEM_1
- REG_CP_REG_TO_MEM_2
- REG_CP_SET_BIN_0
- REG_CP_SET_BIN_1
- REG_CP_SET_BIN_2
- REG_CP_SET_BIN_DATA5_0
- REG_CP_SET_BIN_DATA5_1
- REG_CP_SET_BIN_DATA5_2
- REG_CP_SET_BIN_DATA5_3
- REG_CP_SET_BIN_DATA5_4
- REG_CP_SET_BIN_DATA5_5
- REG_CP_SET_BIN_DATA5_6
- REG_CP_SET_BIN_DATA_0
- REG_CP_SET_BIN_DATA_1
- REG_CP_SET_DRAW_STATE_
- REG_CP_SET_DRAW_STATE__0
- REG_CP_SET_DRAW_STATE__1
- REG_CP_SET_DRAW_STATE__2
- REG_CP_SET_RENDER_MODE_0
- REG_CP_SET_RENDER_MODE_1
- REG_CP_SET_RENDER_MODE_2
- REG_CP_SET_RENDER_MODE_3
- REG_CP_SET_RENDER_MODE_4
- REG_CP_SET_RENDER_MODE_5
- REG_CP_SET_RENDER_MODE_6
- REG_CP_SET_RENDER_MODE_7
- REG_CR
- REG_CR1_BYPASS_OFFSET
- REG_CR1_DACSEL_OFFSET
- REG_CR1_DAC_MUTE_OFFSET
- REG_CR1_HP_DIS_OFFSET
- REG_CR1_MONO_OFFSET
- REG_CR1_SB_MICBIAS_OFFSET
- REG_CR2_ADC_ADWL_MASK
- REG_CR2_ADC_ADWL_OFFSET
- REG_CR2_ADC_HPF_OFFSET
- REG_CR2_DAC_ADWL_MASK
- REG_CR2_DAC_ADWL_OFFSET
- REG_CR2_DAC_DEEMP_OFFSET
- REG_CR3_INSEL_MASK
- REG_CR3_INSEL_OFFSET
- REG_CR3_MICDIFF_OFFSET
- REG_CR3_MICSTEREO_OFFSET
- REG_CR3_SB_MIC1_OFFSET
- REG_CR3_SB_MIC2_OFFSET
- REG_CR3_SIDETONE1_OFFSET
- REG_CR3_SIDETONE2_OFFSET
- REG_CRC
- REG_CRCR
- REG_CRC_CFG
- REG_CRC_CNT
- REG_CRC_FTL_COUNTER
- REG_CRM_NUMBER
- REG_CRT_DETECT
- REG_CR_8723B
- REG_CR_BASICCAN_INITIAL
- REG_CR_BASICCAN_INITIAL_MASK
- REG_CR_EXT
- REG_CS
- REG_CSCDR
- REG_CSCIR
- REG_CSI2_CTRL0
- REG_CSI2_DPHY3
- REG_CSI2_DPHY5
- REG_CSI2_DPHY6
- REG_CSI_RPT_PARAM_BW20
- REG_CSI_RPT_PARAM_BW20_8723B
- REG_CSI_RPT_PARAM_BW40
- REG_CSI_RPT_PARAM_BW40_8723B
- REG_CSI_RPT_PARAM_BW80
- REG_CSI_RPT_PARAM_BW80_8723B
- REG_CSMB_CTRL
- REG_CSR
- REG_CTCH
- REG_CTCL
- REG_CTCM
- REG_CTCTRL
- REG_CTHINT
- REG_CTI_CONTROL
- REG_CTI_DELAY
- REG_CTL
- REG_CTL_GEN
- REG_CTL_MD
- REG_CTL_RXEN
- REG_CTRL
- REG_CTRL0
- REG_CTRL1
- REG_CTRL15
- REG_CTRL2
- REG_CTRL_ACK_IGNORE
- REG_CTRL_ARBDIS
- REG_CTRL_AUTOACK
- REG_CTRL_AUTOSE
- REG_CTRL_AUTOSN
- REG_CTRL_BITO_160PCC
- REG_CTRL_BITO_40PCC
- REG_CTRL_BITO_80PCC
- REG_CTRL_BITO_OFF
- REG_CTRL_BITO__MASK
- REG_CTRL_CLHR__MASK
- REG_CTRL_CLKDIVEXT_MASK
- REG_CTRL_CLKDIVEXT_SHIFT
- REG_CTRL_CLKDIV_MASK
- REG_CTRL_CLKDIV_SHIFT
- REG_CTRL_CLKPHA
- REG_CTRL_CLKPOL
- REG_CTRL_CLK_DETECTED
- REG_CTRL_CLK_DET_RST
- REG_CTRL_CLTO_OFF
- REG_CTRL_CLTO__MASK
- REG_CTRL_COMMON_ON
- REG_CTRL_EN
- REG_CTRL_ENABLE
- REG_CTRL_ERROR
- REG_CTRL_FSEL_MASK
- REG_CTRL_FSEL_SHIFT
- REG_CTRL_GCAMEN
- REG_CTRL_GIBITO
- REG_CTRL_INTR_SEL
- REG_CTRL_MSBF
- REG_CTRL_PORT_RESET
- REG_CTRL_POWER_ON_RESET
- REG_CTRL_REF_CLK_SEL_MASK
- REG_CTRL_REF_CLK_SEL_SHIFT
- REG_CTRL_ROTATE
- REG_CTRL_SLAVE
- REG_CTRL_SLEEPM
- REG_CTRL_SOFT_HRESET
- REG_CTRL_SOFT_PRST
- REG_CTRL_SOF_SENT_RCVD_TGL
- REG_CTRL_SOF_TOGGLE_OUT
- REG_CTRL_SS_SCALEDOWN_MODE_MASK
- REG_CTRL_START
- REG_CTRL_STATUS
- REG_CTRL_SYNC
- REG_CTRL_THREAD_ID_MASK
- REG_CTRL_TXBIL
- REG_CTRL_TX_BITSTUFF_ENN
- REG_CTRL_TX_BITSTUFF_ENN_H
- REG_CTS2TO
- REG_CTS2TO_8723B
- REG_CTSTS
- REG_CTS_C0S0_ACT
- REG_CTS_C0S0_EN
- REG_CTS_CTL
- REG_CTS_LENGTH
- REG_CTS_N
- REG_CTS_OFFSET
- REG_CTS_STAT
- REG_CTWND
- REG_CTWND_8723B
- REG_CT_THRHLD
- REG_CURPAGE
- REG_CURPAGE_00H
- REG_CURRENT
- REG_CVR
- REG_CX
- REG_CYCLE_COUNT
- REG_CYLINDER_HIGH
- REG_CYLINDER_LOW
- REG_C_N
- REG_D
- REG_DAL
- REG_DARFRC
- REG_DARFRCH
- REG_DARFRC_8723B
- REG_DATA
- REG_DATABUF
- REG_DATAMODUL
- REG_DATA_CONTROL
- REG_DATA_LENGTH
- REG_DATA_SC
- REG_DATA_SC_8723B
- REG_DATA_SUBCHANNEL
- REG_DATA_TIMER
- REG_DATA_WINDOW
- REG_DATE_AND_TIME_STAMPS
- REG_DAYS
- REG_DAYS_REG
- REG_DBG
- REG_DBG_AUTOALG_EN
- REG_DBG_SEL
- REG_DBG_SEL_8723B
- REG_DBG_UART
- REG_DBI
- REG_DBI_ADDR
- REG_DBI_ADDR_8723B
- REG_DBI_CTRL
- REG_DBI_FLAG
- REG_DBI_FLAG_8723B
- REG_DBI_FLAG_V1
- REG_DBI_RDATA
- REG_DBI_RDATA_8723B
- REG_DBI_WDATA
- REG_DBI_WDATA_8723B
- REG_DBI_WDATA_V1
- REG_DBLC1
- REG_DBLC_B
- REG_DBLC_GB
- REG_DBLC_GR
- REG_DBLC_R
- REG_DBLV
- REG_DB_DIN0
- REG_DB_DIN1
- REG_DB_DOUT0
- REG_DB_DOUT1
- REG_DB_IN
- REG_DB_OUT
- REG_DB_STAT
- REG_DB_STATMASK
- REG_DCBAAP_HIGH
- REG_DCBAAP_LOW
- REG_DCDC_EN
- REG_DCDC_SET
- REG_DCIH_LENGTH
- REG_DCIH_OFFSET
- REG_DCKA_I_0
- REG_DCKA_I_1
- REG_DCKA_Q_0
- REG_DCKA_Q_1
- REG_DCKB_I_0
- REG_DCKB_I_1
- REG_DCKB_Q_0
- REG_DCKB_Q_1
- REG_DCOM_ADDR
- REG_DCOM_CONTROL_BYTE
- REG_DCOM_DATA
- REG_DCPU_RESET
- REG_DCP_CFG
- REG_DCP_DD_CFG
- REG_DCP_DLM_AVG
- REG_DCT0_CONFIG_HIGH
- REG_DCTL
- REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_MASK
- REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK
- REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT
- REG_DC_AUDIO_INPUT_PORT_CONNECTIVITY__REG_INPUT_PORT_CONNECTIVITY__SHIFT
- REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_MASK
- REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK
- REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT
- REG_DC_AUDIO_PORT_CONNECTIVITY__REG_PORT_CONNECTIVITY__SHIFT
- REG_DC_OFFSET_CTRL
- REG_DC_OFFSET_DAC
- REG_DDC_ABORT_INT
- REG_DDC_ABORT_INT_MASK
- REG_DDC_ADDR
- REG_DDC_CMD
- REG_DDC_DATA
- REG_DDC_DELAY_CNT
- REG_DDC_DIN_CNT1
- REG_DDC_DIN_CNT2
- REG_DDC_DISABLE
- REG_DDC_DOUT_CNT
- REG_DDC_DRIVE
- REG_DDC_MANUAL
- REG_DDC_OFFS
- REG_DDC_OFFSET
- REG_DDC_SEGM
- REG_DDC_SEGM_ADDR
- REG_DDC_STATE
- REG_DDC_STATUS
- REG_DDMA_CH0CTRL
- REG_DDMA_CH0DA
- REG_DDMA_CH0SA
- REG_DDRA
- REG_DDRB
- REG_DDRC
- REG_DDRD
- REG_DD_CFG
- REG_DEBOUNCE_DIS1
- REG_DEBOUNCE_DIS2
- REG_DEBOUNCE_DIS3
- REG_DEBUG
- REG_DEBUG_BUF_CNT
- REG_DEBUG_DATA0
- REG_DEBUG_DATA1
- REG_DEEP_COLOR_CTRL
- REG_DEEP_COLOR_MODE
- REG_DEEP_PLL7_BYP
- REG_DEFAULT_SLAVE_ADDR
- REG_DEF_AUDIO_GAIN
- REG_DELAYCFG0
- REG_DELAYCFG1
- REG_DELAYCFG2
- REG_DELOCK_DELAY
- REG_DEMOD_RUN
- REG_DENOISE_OFFSET1
- REG_DENOISE_OFFSET2
- REG_DENOISE_THRESH1
- REG_DENOISE_THRESH2
- REG_DENORM
- REG_DENORM_10G
- REG_DESC_BASE_ADDR_HI
- REG_DESC_CMB_ADDR_LO
- REG_DESC_LEN_U
- REG_DESC_LEN_V
- REG_DESC_LEN_Y
- REG_DESC_RFD_ADDR_LO
- REG_DESC_RFD_RRD_RING_SIZE
- REG_DESC_RRD_ADDR_LO
- REG_DESC_SMB_ADDR_LO
- REG_DESC_TPD_ADDR_LO
- REG_DESC_TPD_RING_SIZE
- REG_DESIGN_CAPACITY
- REG_DESIGN_CAPACITY_CHARGE
- REG_DESIGN_VOLTAGE_MAX
- REG_DESIGN_VOLTAGE_MIN
- REG_DETECTED_PN_MODE
- REG_DETECT_5V
- REG_DEVADDR_H
- REG_DEVADDR_L
- REG_DEVICE_CAP
- REG_DEVICE_CONTROL
- REG_DEVICE_CTRL
- REG_DEVICE_HEAD
- REG_DEVID
- REG_DEVID2
- REG_DEVREV2
- REG_DEV_ID
- REG_DEV_IDH
- REG_DEV_IDL
- REG_DEV_MAC_SEL_MASK
- REG_DEV_MAC_SEL_SHIFT
- REG_DEV_REV
- REG_DEV_SERIALNUM_CTRL
- REG_DEV_SERIAL_NUM_EN_MASK
- REG_DEV_SERIAL_NUM_EN_SHIFT
- REG_DEV_SETUP
- REG_DE_FREF
- REG_DE_START_LSB
- REG_DE_START_MSB
- REG_DE_STOP_LSB
- REG_DE_STOP_MSB
- REG_DFIRBW
- REG_DIAG
- REG_DIDT
- REG_DIFF_CTL
- REG_DIFF_ST
- REG_DIOMAPPING1
- REG_DIOMAPPING2
- REG_DIP_FLAGS
- REG_DIP_IF_FLAGS
- REG_DIR
- REG_DIR_DATA_READ
- REG_DIR_DATA_WRITE
- REG_DISC_CTRL1
- REG_DISC_CTRL4
- REG_DISC_CTRL5
- REG_DISC_CTRL8
- REG_DISC_CTRL9
- REG_DISC_STAT1
- REG_DISC_STAT2
- REG_DISPLAY_BRIGHTNESS
- REG_DISPLAY_CONTROL_1
- REG_DISPLAY_CONTROL_2
- REG_DISPLAY_CONTROL_3
- REG_DISPLAY_LCD
- REG_DISPLAY_SETUP
- REG_DISPLAY_SETUP_ON
- REG_DISTANCE
- REG_DISTANCE_BIAS
- REG_DIS_DPD
- REG_DIS_TXREQ_CLR
- REG_DIS_TXREQ_CLR_8723B
- REG_DITHERING_CTRL
- REG_DIV_CTL1
- REG_DIV_CTL_MAIN
- REG_DI_FMT
- REG_DLR_BEACON_INTERVAL__4
- REG_DLR_BEACON_TIMEOUT__4
- REG_DLR_CLASS__1
- REG_DLR_CTRL__1
- REG_DLR_DEST_ADDR_0
- REG_DLR_DEST_ADDR_1
- REG_DLR_DEST_ADDR_2
- REG_DLR_DEST_ADDR_3
- REG_DLR_DEST_ADDR_4
- REG_DLR_DEST_ADDR_5
- REG_DLR_IP_ADDR__4
- REG_DLR_PORT_MAP__4
- REG_DLR_PRECEDENCE__1
- REG_DLR_SRC_PORT__4
- REG_DLR_STATE__1
- REG_DLR_TIMEOUT_WINDOW__4
- REG_DLR_VLAN_ID__2
- REG_DLY
- REG_DMA1REQ
- REG_DMAADDR
- REG_DMACR
- REG_DMAENABLE_CLEAR
- REG_DMAENABLE_SET
- REG_DMAR
- REG_DMAW
- REG_DMA_BASE
- REG_DMA_BLEN_CTRL
- REG_DMA_CTRL
- REG_DMA_DBG
- REG_DMA_DESC_U
- REG_DMA_DESC_V
- REG_DMA_DESC_Y
- REG_DMA_FIFO_STATE
- REG_DMA_MISC
- REG_DMA_MISC_INT_AUTO_CLEAR
- REG_DMC
- REG_DM_CFG0
- REG_DM_CFG1
- REG_DM_LNH
- REG_DM_LNL
- REG_DNCTRL
- REG_DOC_CFG4
- REG_DOC_CTL0
- REG_DOC_CTL6
- REG_DOC_CTL7
- REG_DOC_CTL8
- REG_DOC_CTL9
- REG_DOC_CTLA
- REG_DOC_CTLE
- REG_DOC_STAT_8
- REG_DOC_STAT_9
- REG_DODT
- REG_DOFF_CTL
- REG_DOFF_ST
- REG_DOMAIN_DOC
- REG_DOMAIN_ETSI
- REG_DOMAIN_FCC
- REG_DOMAIN_FRANCE
- REG_DOMAIN_ISRAEL
- REG_DOMAIN_MKK
- REG_DOMAIN_MKK1
- REG_DOMAIN_SPAIN
- REG_DOORBELLOFF
- REG_DO_FMT
- REG_DPD
- REG_DPDT_CTRL
- REG_DPD_AGC
- REG_DPD_CTL0
- REG_DPD_CTL0_S0
- REG_DPD_CTL0_S1
- REG_DPD_CTL11
- REG_DPD_CTL12
- REG_DPD_CTL15
- REG_DPD_CTL16
- REG_DPD_CTL1_S0
- REG_DPD_CTL1_S1
- REG_DPD_LUT0
- REG_DPD_LUT3
- REG_DR
- REG_DR0
- REG_DR1
- REG_DRIFT_CLK_A_REG
- REG_DRIFT_CLK_B_REG
- REG_DRIVER_CODE_READ
- REG_DRIVER_EARLY_INT
- REG_DRIVER_OUTPUT_CONTROL
- REG_DRIVER_RANGE
- REG_DROP_CNT
- REG_DRVERLYINT
- REG_DRVERLYINT_8723B
- REG_DS
- REG_DSI_10nm_PHY_CMN_CLK_CFG0
- REG_DSI_10nm_PHY_CMN_CLK_CFG1
- REG_DSI_10nm_PHY_CMN_CTRL_0
- REG_DSI_10nm_PHY_CMN_CTRL_1
- REG_DSI_10nm_PHY_CMN_CTRL_2
- REG_DSI_10nm_PHY_CMN_GLBL_CTRL
- REG_DSI_10nm_PHY_CMN_LANE_CFG0
- REG_DSI_10nm_PHY_CMN_LANE_CFG1
- REG_DSI_10nm_PHY_CMN_LANE_CTRL0
- REG_DSI_10nm_PHY_CMN_LANE_CTRL1
- REG_DSI_10nm_PHY_CMN_LANE_CTRL2
- REG_DSI_10nm_PHY_CMN_LANE_CTRL3
- REG_DSI_10nm_PHY_CMN_LANE_CTRL4
- REG_DSI_10nm_PHY_CMN_LANE_STATUS0
- REG_DSI_10nm_PHY_CMN_LANE_STATUS1
- REG_DSI_10nm_PHY_CMN_PHY_STATUS
- REG_DSI_10nm_PHY_CMN_PLL_CNTRL
- REG_DSI_10nm_PHY_CMN_RBUF_CTRL
- REG_DSI_10nm_PHY_CMN_REVISION_ID0
- REG_DSI_10nm_PHY_CMN_REVISION_ID1
- REG_DSI_10nm_PHY_CMN_REVISION_ID2
- REG_DSI_10nm_PHY_CMN_REVISION_ID3
- REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0
- REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1
- REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10
- REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11
- REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2
- REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3
- REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4
- REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5
- REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6
- REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7
- REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8
- REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9
- REG_DSI_10nm_PHY_CMN_VREG_CTRL
- REG_DSI_10nm_PHY_LN
- REG_DSI_10nm_PHY_LN_CFG0
- REG_DSI_10nm_PHY_LN_CFG1
- REG_DSI_10nm_PHY_LN_CFG2
- REG_DSI_10nm_PHY_LN_CFG3
- REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL
- REG_DSI_10nm_PHY_LN_LPRX_CTRL
- REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL
- REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL
- REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL
- REG_DSI_10nm_PHY_LN_PIN_SWAP
- REG_DSI_10nm_PHY_LN_TEST_DATAPATH
- REG_DSI_10nm_PHY_LN_TX_DCTRL
- REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE
- REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE
- REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO
- REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE
- REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS
- REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS
- REG_DSI_10nm_PHY_PLL_CMODE
- REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE
- REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE
- REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE
- REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1
- REG_DSI_10nm_PHY_PLL_DSM_DIVIDER
- REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER
- REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1
- REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1
- REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1
- REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE
- REG_DSI_10nm_PHY_PLL_IFILT
- REG_DSI_10nm_PHY_PLL_OUTDIV
- REG_DSI_10nm_PHY_PLL_PFILT
- REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1
- REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO
- REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1
- REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1
- REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1
- REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY
- REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE
- REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE
- REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1
- REG_DSI_10nm_PHY_PLL_SSC_CONTROL
- REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1
- REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1
- REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1
- REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1
- REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1
- REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1
- REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES
- REG_DSI_14nm_PHY_CMN_CLK_CFG0
- REG_DSI_14nm_PHY_CMN_CLK_CFG1
- REG_DSI_14nm_PHY_CMN_CTRL_0
- REG_DSI_14nm_PHY_CMN_CTRL_1
- REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL
- REG_DSI_14nm_PHY_CMN_HW_CFG0
- REG_DSI_14nm_PHY_CMN_HW_CFG1
- REG_DSI_14nm_PHY_CMN_HW_CFG2
- REG_DSI_14nm_PHY_CMN_HW_CFG3
- REG_DSI_14nm_PHY_CMN_HW_CFG4
- REG_DSI_14nm_PHY_CMN_HW_TRIGGER
- REG_DSI_14nm_PHY_CMN_LDO_CNTRL
- REG_DSI_14nm_PHY_CMN_PLL_CNTRL
- REG_DSI_14nm_PHY_CMN_REVISION_ID0
- REG_DSI_14nm_PHY_CMN_REVISION_ID1
- REG_DSI_14nm_PHY_CMN_REVISION_ID2
- REG_DSI_14nm_PHY_CMN_REVISION_ID3
- REG_DSI_14nm_PHY_CMN_SW_CFG0
- REG_DSI_14nm_PHY_CMN_SW_CFG1
- REG_DSI_14nm_PHY_CMN_SW_CFG2
- REG_DSI_14nm_PHY_LN
- REG_DSI_14nm_PHY_LN_CFG0
- REG_DSI_14nm_PHY_LN_CFG1
- REG_DSI_14nm_PHY_LN_CFG2
- REG_DSI_14nm_PHY_LN_CFG3
- REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0
- REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1
- REG_DSI_14nm_PHY_LN_TEST_DATAPATH
- REG_DSI_14nm_PHY_LN_TEST_STR
- REG_DSI_14nm_PHY_LN_TIMING_CTRL_10
- REG_DSI_14nm_PHY_LN_TIMING_CTRL_11
- REG_DSI_14nm_PHY_LN_TIMING_CTRL_4
- REG_DSI_14nm_PHY_LN_TIMING_CTRL_5
- REG_DSI_14nm_PHY_LN_TIMING_CTRL_6
- REG_DSI_14nm_PHY_LN_TIMING_CTRL_7
- REG_DSI_14nm_PHY_LN_TIMING_CTRL_8
- REG_DSI_14nm_PHY_LN_TIMING_CTRL_9
- REG_DSI_14nm_PHY_LN_VREG_CNTRL
- REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN
- REG_DSI_14nm_PHY_PLL_CP_SET_CUR
- REG_DSI_14nm_PHY_PLL_DEC_START
- REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1
- REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2
- REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3
- REG_DSI_14nm_PHY_PLL_IE_TRIM
- REG_DSI_14nm_PHY_PLL_IPTAT_TRIM
- REG_DSI_14nm_PHY_PLL_IP_TRIM
- REG_DSI_14nm_PHY_PLL_KVCO_CODE
- REG_DSI_14nm_PHY_PLL_KVCO_COUNT1
- REG_DSI_14nm_PHY_PLL_KVCO_COUNT2
- REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1
- REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2
- REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1
- REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2
- REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3
- REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN
- REG_DSI_14nm_PHY_PLL_PLL_BANDGAP
- REG_DSI_14nm_PHY_PLL_PLL_CRCTRL
- REG_DSI_14nm_PHY_PLL_PLL_ICPCSET
- REG_DSI_14nm_PHY_PLL_PLL_ICPMSET
- REG_DSI_14nm_PHY_PLL_PLL_ICP_SET
- REG_DSI_14nm_PHY_PLL_PLL_LPF1
- REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV
- REG_DSI_14nm_PHY_PLL_PLL_MISC1
- REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE
- REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL
- REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2
- REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3
- REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4
- REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5
- REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS
- REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1
- REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2
- REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER
- REG_DSI_14nm_PHY_PLL_SSC_PER1
- REG_DSI_14nm_PHY_PLL_SSC_PER2
- REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1
- REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2
- REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET
- REG_DSI_14nm_PHY_PLL_TXCLK_EN
- REG_DSI_14nm_PHY_PLL_VCO_COUNT1
- REG_DSI_14nm_PHY_PLL_VCO_COUNT2
- REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1
- REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2
- REG_DSI_14nm_PHY_PLL_VREF_CFG1
- REG_DSI_20nm_PHY_BIST_CTRL_0
- REG_DSI_20nm_PHY_BIST_CTRL_1
- REG_DSI_20nm_PHY_BIST_CTRL_2
- REG_DSI_20nm_PHY_BIST_CTRL_3
- REG_DSI_20nm_PHY_BIST_CTRL_4
- REG_DSI_20nm_PHY_BIST_CTRL_5
- REG_DSI_20nm_PHY_CTRL_0
- REG_DSI_20nm_PHY_CTRL_1
- REG_DSI_20nm_PHY_CTRL_2
- REG_DSI_20nm_PHY_CTRL_3
- REG_DSI_20nm_PHY_CTRL_4
- REG_DSI_20nm_PHY_GLBL_TEST_CTRL
- REG_DSI_20nm_PHY_LDO_CNTRL
- REG_DSI_20nm_PHY_LN
- REG_DSI_20nm_PHY_LNCK_CFG_0
- REG_DSI_20nm_PHY_LNCK_CFG_1
- REG_DSI_20nm_PHY_LNCK_CFG_2
- REG_DSI_20nm_PHY_LNCK_CFG_3
- REG_DSI_20nm_PHY_LNCK_CFG_4
- REG_DSI_20nm_PHY_LNCK_DEBUG_SEL
- REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH
- REG_DSI_20nm_PHY_LNCK_TEST_STR0
- REG_DSI_20nm_PHY_LNCK_TEST_STR1
- REG_DSI_20nm_PHY_LN_CFG_0
- REG_DSI_20nm_PHY_LN_CFG_1
- REG_DSI_20nm_PHY_LN_CFG_2
- REG_DSI_20nm_PHY_LN_CFG_3
- REG_DSI_20nm_PHY_LN_CFG_4
- REG_DSI_20nm_PHY_LN_DEBUG_SEL
- REG_DSI_20nm_PHY_LN_TEST_DATAPATH
- REG_DSI_20nm_PHY_LN_TEST_STR_0
- REG_DSI_20nm_PHY_LN_TEST_STR_1
- REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG
- REG_DSI_20nm_PHY_REGULATOR_CTRL_0
- REG_DSI_20nm_PHY_REGULATOR_CTRL_1
- REG_DSI_20nm_PHY_REGULATOR_CTRL_2
- REG_DSI_20nm_PHY_REGULATOR_CTRL_3
- REG_DSI_20nm_PHY_REGULATOR_CTRL_4
- REG_DSI_20nm_PHY_REGULATOR_CTRL_5
- REG_DSI_20nm_PHY_STRENGTH_0
- REG_DSI_20nm_PHY_STRENGTH_1
- REG_DSI_20nm_PHY_TIMING_CTRL_0
- REG_DSI_20nm_PHY_TIMING_CTRL_1
- REG_DSI_20nm_PHY_TIMING_CTRL_10
- REG_DSI_20nm_PHY_TIMING_CTRL_11
- REG_DSI_20nm_PHY_TIMING_CTRL_2
- REG_DSI_20nm_PHY_TIMING_CTRL_3
- REG_DSI_20nm_PHY_TIMING_CTRL_4
- REG_DSI_20nm_PHY_TIMING_CTRL_5
- REG_DSI_20nm_PHY_TIMING_CTRL_6
- REG_DSI_20nm_PHY_TIMING_CTRL_7
- REG_DSI_20nm_PHY_TIMING_CTRL_8
- REG_DSI_20nm_PHY_TIMING_CTRL_9
- REG_DSI_28nm_8960_PHY_BIST_CTRL_0
- REG_DSI_28nm_8960_PHY_BIST_CTRL_1
- REG_DSI_28nm_8960_PHY_BIST_CTRL_2
- REG_DSI_28nm_8960_PHY_BIST_CTRL_3
- REG_DSI_28nm_8960_PHY_BIST_CTRL_4
- REG_DSI_28nm_8960_PHY_CTRL_0
- REG_DSI_28nm_8960_PHY_CTRL_1
- REG_DSI_28nm_8960_PHY_CTRL_2
- REG_DSI_28nm_8960_PHY_CTRL_3
- REG_DSI_28nm_8960_PHY_LDO_CTRL
- REG_DSI_28nm_8960_PHY_LN
- REG_DSI_28nm_8960_PHY_LNCK_CFG_0
- REG_DSI_28nm_8960_PHY_LNCK_CFG_1
- REG_DSI_28nm_8960_PHY_LNCK_CFG_2
- REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH
- REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0
- REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1
- REG_DSI_28nm_8960_PHY_LN_CFG_0
- REG_DSI_28nm_8960_PHY_LN_CFG_1
- REG_DSI_28nm_8960_PHY_LN_CFG_2
- REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH
- REG_DSI_28nm_8960_PHY_LN_TEST_STR_0
- REG_DSI_28nm_8960_PHY_LN_TEST_STR_1
- REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0
- REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1
- REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2
- REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3
- REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4
- REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER
- REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS
- REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0
- REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1
- REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2
- REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG
- REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0
- REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1
- REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2
- REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3
- REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4
- REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5
- REG_DSI_28nm_8960_PHY_PLL_CTRL_0
- REG_DSI_28nm_8960_PHY_PLL_CTRL_1
- REG_DSI_28nm_8960_PHY_PLL_CTRL_10
- REG_DSI_28nm_8960_PHY_PLL_CTRL_11
- REG_DSI_28nm_8960_PHY_PLL_CTRL_12
- REG_DSI_28nm_8960_PHY_PLL_CTRL_13
- REG_DSI_28nm_8960_PHY_PLL_CTRL_14
- REG_DSI_28nm_8960_PHY_PLL_CTRL_15
- REG_DSI_28nm_8960_PHY_PLL_CTRL_16
- REG_DSI_28nm_8960_PHY_PLL_CTRL_17
- REG_DSI_28nm_8960_PHY_PLL_CTRL_18
- REG_DSI_28nm_8960_PHY_PLL_CTRL_19
- REG_DSI_28nm_8960_PHY_PLL_CTRL_2
- REG_DSI_28nm_8960_PHY_PLL_CTRL_20
- REG_DSI_28nm_8960_PHY_PLL_CTRL_3
- REG_DSI_28nm_8960_PHY_PLL_CTRL_4
- REG_DSI_28nm_8960_PHY_PLL_CTRL_5
- REG_DSI_28nm_8960_PHY_PLL_CTRL_6
- REG_DSI_28nm_8960_PHY_PLL_CTRL_7
- REG_DSI_28nm_8960_PHY_PLL_CTRL_8
- REG_DSI_28nm_8960_PHY_PLL_CTRL_9
- REG_DSI_28nm_8960_PHY_PLL_RDY
- REG_DSI_28nm_8960_PHY_STRENGTH_0
- REG_DSI_28nm_8960_PHY_STRENGTH_1
- REG_DSI_28nm_8960_PHY_STRENGTH_2
- REG_DSI_28nm_8960_PHY_TIMING_CTRL_0
- REG_DSI_28nm_8960_PHY_TIMING_CTRL_1
- REG_DSI_28nm_8960_PHY_TIMING_CTRL_10
- REG_DSI_28nm_8960_PHY_TIMING_CTRL_11
- REG_DSI_28nm_8960_PHY_TIMING_CTRL_2
- REG_DSI_28nm_8960_PHY_TIMING_CTRL_3
- REG_DSI_28nm_8960_PHY_TIMING_CTRL_4
- REG_DSI_28nm_8960_PHY_TIMING_CTRL_5
- REG_DSI_28nm_8960_PHY_TIMING_CTRL_6
- REG_DSI_28nm_8960_PHY_TIMING_CTRL_7
- REG_DSI_28nm_8960_PHY_TIMING_CTRL_8
- REG_DSI_28nm_8960_PHY_TIMING_CTRL_9
- REG_DSI_28nm_PHY_BIST_CTRL_0
- REG_DSI_28nm_PHY_BIST_CTRL_1
- REG_DSI_28nm_PHY_BIST_CTRL_2
- REG_DSI_28nm_PHY_BIST_CTRL_3
- REG_DSI_28nm_PHY_BIST_CTRL_4
- REG_DSI_28nm_PHY_BIST_CTRL_5
- REG_DSI_28nm_PHY_CTRL_0
- REG_DSI_28nm_PHY_CTRL_1
- REG_DSI_28nm_PHY_CTRL_2
- REG_DSI_28nm_PHY_CTRL_3
- REG_DSI_28nm_PHY_CTRL_4
- REG_DSI_28nm_PHY_GLBL_TEST_CTRL
- REG_DSI_28nm_PHY_LDO_CNTRL
- REG_DSI_28nm_PHY_LN
- REG_DSI_28nm_PHY_LNCK_CFG_0
- REG_DSI_28nm_PHY_LNCK_CFG_1
- REG_DSI_28nm_PHY_LNCK_CFG_2
- REG_DSI_28nm_PHY_LNCK_CFG_3
- REG_DSI_28nm_PHY_LNCK_CFG_4
- REG_DSI_28nm_PHY_LNCK_DEBUG_SEL
- REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH
- REG_DSI_28nm_PHY_LNCK_TEST_STR0
- REG_DSI_28nm_PHY_LNCK_TEST_STR1
- REG_DSI_28nm_PHY_LN_CFG_0
- REG_DSI_28nm_PHY_LN_CFG_1
- REG_DSI_28nm_PHY_LN_CFG_2
- REG_DSI_28nm_PHY_LN_CFG_3
- REG_DSI_28nm_PHY_LN_CFG_4
- REG_DSI_28nm_PHY_LN_DEBUG_SEL
- REG_DSI_28nm_PHY_LN_TEST_DATAPATH
- REG_DSI_28nm_PHY_LN_TEST_STR_0
- REG_DSI_28nm_PHY_LN_TEST_STR_1
- REG_DSI_28nm_PHY_PLL_AMUX_CFG
- REG_DSI_28nm_PHY_PLL_CAL_CFG0
- REG_DSI_28nm_PHY_PLL_CAL_CFG1
- REG_DSI_28nm_PHY_PLL_CAL_CFG10
- REG_DSI_28nm_PHY_PLL_CAL_CFG11
- REG_DSI_28nm_PHY_PLL_CAL_CFG2
- REG_DSI_28nm_PHY_PLL_CAL_CFG3
- REG_DSI_28nm_PHY_PLL_CAL_CFG4
- REG_DSI_28nm_PHY_PLL_CAL_CFG5
- REG_DSI_28nm_PHY_PLL_CAL_CFG6
- REG_DSI_28nm_PHY_PLL_CAL_CFG7
- REG_DSI_28nm_PHY_PLL_CAL_CFG8
- REG_DSI_28nm_PHY_PLL_CAL_CFG9
- REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG
- REG_DSI_28nm_PHY_PLL_CTRL_42
- REG_DSI_28nm_PHY_PLL_CTRL_43
- REG_DSI_28nm_PHY_PLL_CTRL_44
- REG_DSI_28nm_PHY_PLL_CTRL_45
- REG_DSI_28nm_PHY_PLL_CTRL_46
- REG_DSI_28nm_PHY_PLL_CTRL_47
- REG_DSI_28nm_PHY_PLL_CTRL_48
- REG_DSI_28nm_PHY_PLL_CTRL_54
- REG_DSI_28nm_PHY_PLL_DEBUG_BUS0
- REG_DSI_28nm_PHY_PLL_DEBUG_BUS1
- REG_DSI_28nm_PHY_PLL_DEBUG_BUS2
- REG_DSI_28nm_PHY_PLL_DEBUG_BUS3
- REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL
- REG_DSI_28nm_PHY_PLL_DMUX_CFG
- REG_DSI_28nm_PHY_PLL_EFUSE_CFG
- REG_DSI_28nm_PHY_PLL_GLB_CFG
- REG_DSI_28nm_PHY_PLL_LKDET_CFG0
- REG_DSI_28nm_PHY_PLL_LKDET_CFG1
- REG_DSI_28nm_PHY_PLL_LKDET_CFG2
- REG_DSI_28nm_PHY_PLL_LPFC1_CFG
- REG_DSI_28nm_PHY_PLL_LPFC2_CFG
- REG_DSI_28nm_PHY_PLL_LPFR_CFG
- REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG
- REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG
- REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG
- REG_DSI_28nm_PHY_PLL_PWRGEN_CFG
- REG_DSI_28nm_PHY_PLL_REFCLK_CFG
- REG_DSI_28nm_PHY_PLL_SDM_CFG0
- REG_DSI_28nm_PHY_PLL_SDM_CFG1
- REG_DSI_28nm_PHY_PLL_SDM_CFG2
- REG_DSI_28nm_PHY_PLL_SDM_CFG3
- REG_DSI_28nm_PHY_PLL_SDM_CFG4
- REG_DSI_28nm_PHY_PLL_SSC_CFG0
- REG_DSI_28nm_PHY_PLL_SSC_CFG1
- REG_DSI_28nm_PHY_PLL_SSC_CFG2
- REG_DSI_28nm_PHY_PLL_SSC_CFG3
- REG_DSI_28nm_PHY_PLL_STATUS
- REG_DSI_28nm_PHY_PLL_TEST_CFG
- REG_DSI_28nm_PHY_PLL_VCOLPF_CFG
- REG_DSI_28nm_PHY_PLL_VREG_CFG
- REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG
- REG_DSI_28nm_PHY_REGULATOR_CTRL_0
- REG_DSI_28nm_PHY_REGULATOR_CTRL_1
- REG_DSI_28nm_PHY_REGULATOR_CTRL_2
- REG_DSI_28nm_PHY_REGULATOR_CTRL_3
- REG_DSI_28nm_PHY_REGULATOR_CTRL_4
- REG_DSI_28nm_PHY_REGULATOR_CTRL_5
- REG_DSI_28nm_PHY_STRENGTH_0
- REG_DSI_28nm_PHY_STRENGTH_1
- REG_DSI_28nm_PHY_TIMING_CTRL_0
- REG_DSI_28nm_PHY_TIMING_CTRL_1
- REG_DSI_28nm_PHY_TIMING_CTRL_10
- REG_DSI_28nm_PHY_TIMING_CTRL_11
- REG_DSI_28nm_PHY_TIMING_CTRL_2
- REG_DSI_28nm_PHY_TIMING_CTRL_3
- REG_DSI_28nm_PHY_TIMING_CTRL_4
- REG_DSI_28nm_PHY_TIMING_CTRL_5
- REG_DSI_28nm_PHY_TIMING_CTRL_6
- REG_DSI_28nm_PHY_TIMING_CTRL_7
- REG_DSI_28nm_PHY_TIMING_CTRL_8
- REG_DSI_28nm_PHY_TIMING_CTRL_9
- REG_DSI_6G_HW_VERSION
- REG_DSI_8x60_PHY_CAL_CTRL
- REG_DSI_8x60_PHY_CAL_HW_TRIGGER
- REG_DSI_8x60_PHY_CAL_STATUS
- REG_DSI_8x60_PHY_CTRL_0
- REG_DSI_8x60_PHY_CTRL_1
- REG_DSI_8x60_PHY_CTRL_2
- REG_DSI_8x60_PHY_CTRL_3
- REG_DSI_8x60_PHY_REGULATOR_CTRL_0
- REG_DSI_8x60_PHY_REGULATOR_CTRL_1
- REG_DSI_8x60_PHY_REGULATOR_CTRL_2
- REG_DSI_8x60_PHY_REGULATOR_CTRL_3
- REG_DSI_8x60_PHY_REGULATOR_CTRL_4
- REG_DSI_8x60_PHY_STRENGTH_0
- REG_DSI_8x60_PHY_STRENGTH_1
- REG_DSI_8x60_PHY_STRENGTH_2
- REG_DSI_8x60_PHY_STRENGTH_3
- REG_DSI_8x60_PHY_TIMING_CTRL_0
- REG_DSI_8x60_PHY_TIMING_CTRL_1
- REG_DSI_8x60_PHY_TIMING_CTRL_10
- REG_DSI_8x60_PHY_TIMING_CTRL_11
- REG_DSI_8x60_PHY_TIMING_CTRL_2
- REG_DSI_8x60_PHY_TIMING_CTRL_3
- REG_DSI_8x60_PHY_TIMING_CTRL_4
- REG_DSI_8x60_PHY_TIMING_CTRL_5
- REG_DSI_8x60_PHY_TIMING_CTRL_6
- REG_DSI_8x60_PHY_TIMING_CTRL_7
- REG_DSI_8x60_PHY_TIMING_CTRL_8
- REG_DSI_8x60_PHY_TIMING_CTRL_9
- REG_DSI_8x60_PHY_TPA_CTRL_1
- REG_DSI_8x60_PHY_TPA_CTRL_2
- REG_DSI_ACK_ERR_STATUS
- REG_DSI_ACTIVE_H
- REG_DSI_ACTIVE_HSYNC
- REG_DSI_ACTIVE_V
- REG_DSI_ACTIVE_VSYNC_HPOS
- REG_DSI_ACTIVE_VSYNC_VPOS
- REG_DSI_CLKOUT_TIMING_CTRL
- REG_DSI_CLK_CTRL
- REG_DSI_CLK_STATUS
- REG_DSI_CMD_CFG0
- REG_DSI_CMD_CFG1
- REG_DSI_CMD_DMA_CTRL
- REG_DSI_CMD_MDP_STREAM_CTRL
- REG_DSI_CMD_MDP_STREAM_TOTAL
- REG_DSI_CTRL
- REG_DSI_DLN0_PHY_ERR
- REG_DSI_DMA_BASE
- REG_DSI_DMA_LEN
- REG_DSI_EOT_PACKET_CTRL
- REG_DSI_ERR_INT_MASK0
- REG_DSI_FIFO_STATUS
- REG_DSI_INTR_CTRL
- REG_DSI_LANE_CTRL
- REG_DSI_LANE_SWAP_CTRL
- REG_DSI_PHY_PLL_CTRL_0
- REG_DSI_PHY_PLL_CTRL_1
- REG_DSI_PHY_PLL_CTRL_10
- REG_DSI_PHY_PLL_CTRL_11
- REG_DSI_PHY_PLL_CTRL_12
- REG_DSI_PHY_PLL_CTRL_13
- REG_DSI_PHY_PLL_CTRL_14
- REG_DSI_PHY_PLL_CTRL_15
- REG_DSI_PHY_PLL_CTRL_16
- REG_DSI_PHY_PLL_CTRL_17
- REG_DSI_PHY_PLL_CTRL_18
- REG_DSI_PHY_PLL_CTRL_19
- REG_DSI_PHY_PLL_CTRL_2
- REG_DSI_PHY_PLL_CTRL_20
- REG_DSI_PHY_PLL_CTRL_3
- REG_DSI_PHY_PLL_CTRL_4
- REG_DSI_PHY_PLL_CTRL_5
- REG_DSI_PHY_PLL_CTRL_6
- REG_DSI_PHY_PLL_CTRL_7
- REG_DSI_PHY_PLL_CTRL_8
- REG_DSI_PHY_PLL_CTRL_9
- REG_DSI_PHY_PLL_STATUS
- REG_DSI_PHY_RESET
- REG_DSI_RDBK
- REG_DSI_RDBK_DATA
- REG_DSI_RDBK_DATA_CTRL
- REG_DSI_RESET
- REG_DSI_STATUS0
- REG_DSI_TIMEOUT_STATUS
- REG_DSI_TOTAL
- REG_DSI_TRIG_CTRL
- REG_DSI_TRIG_DMA
- REG_DSI_T_CLK_PRE_EXTEND
- REG_DSI_VERSION
- REG_DSI_VID_CFG0
- REG_DSI_VID_CFG1
- REG_DSP_CLOCK
- REG_DSP_RESET
- REG_DUAL_TSF_RST
- REG_DUAL_TSF_RST_8723B
- REG_DUMMY
- REG_DUMMY_PAGE4_V1
- REG_DUMP_COUNT_QCA988X
- REG_DUMP_LEN_SHIFT
- REG_DUTY
- REG_DV3318_OCPCTL
- REG_DV3318_OCPSTAT
- REG_DVB_STANDARD
- REG_DVP_CTRL02
- REG_DWARFNUM_END
- REG_DWARFNUM_NAME
- REG_DWBCN0_CTRL
- REG_DWBCN0_CTRL_8723B
- REG_DWBCN1_CTRL
- REG_DWBCN1_CTRL_8723B
- REG_DYMENTH
- REG_DYMENTH0
- REG_DYMPRITH
- REG_DYMTHMIN
- REG_E
- REG_EADR
- REG_EADR0
- REG_EADR1
- REG_EADR2
- REG_EADR3
- REG_EADR4
- REG_EADR5
- REG_EADR6
- REG_EADR7
- REG_EAR2
- REG_EARLY_MODE_CONTROL
- REG_EARLY_MODE_CONTROL_8188E
- REG_EARLY_MODE_CONTROL_8723B
- REG_EAX
- REG_EBP
- REG_EBX
- REG_ECIR
- REG_ECIR2
- REG_ECPU_CONTROL
- REG_ECSR
- REG_ECX
- REG_EDATA
- REG_EDCA_BE_PARAM
- REG_EDCA_BE_PARAM_8723B
- REG_EDCA_BK_PARAM
- REG_EDCA_BK_PARAM_8723B
- REG_EDCA_RANDOM_GEN
- REG_EDCA_VI_PARAM
- REG_EDCA_VI_PARAM_8723B
- REG_EDCA_VO_PARAM
- REG_EDCA_VO_PARAM_8723B
- REG_EDGE
- REG_EDGE_OFF
- REG_EDGE_ON
- REG_EDGE_POL
- REG_EDGE_POL_EDGE
- REG_EDGE_POL_LOW
- REG_EDGE_POL_MASK
- REG_EDI
- REG_EDID_CTRL
- REG_EDID_DATA_0
- REG_EDID_ENABLE
- REG_EDID_FIFO_ADDR
- REG_EDID_FIFO_ADDR_MON
- REG_EDID_FIFO_RD_DATA
- REG_EDID_FIFO_WR_DATA
- REG_EDID_IN_BYTE0
- REG_EDID_IN_BYTE128
- REG_EDID_IN_CKSUM_A
- REG_EDID_IN_CKSUM_B
- REG_EDID_IN_SPA_AB_A
- REG_EDID_IN_SPA_AB_B
- REG_EDID_IN_SPA_CD_A
- REG_EDID_IN_SPA_CD_B
- REG_EDID_IN_SPA_SUB
- REG_EDID_IN_VERSION
- REG_EDID_START_EXT
- REG_EDP_28nm_PHY_PLL_AMUX_CFG
- REG_EDP_28nm_PHY_PLL_CAL_CFG0
- REG_EDP_28nm_PHY_PLL_CAL_CFG1
- REG_EDP_28nm_PHY_PLL_CAL_CFG10
- REG_EDP_28nm_PHY_PLL_CAL_CFG11
- REG_EDP_28nm_PHY_PLL_CAL_CFG2
- REG_EDP_28nm_PHY_PLL_CAL_CFG3
- REG_EDP_28nm_PHY_PLL_CAL_CFG4
- REG_EDP_28nm_PHY_PLL_CAL_CFG5
- REG_EDP_28nm_PHY_PLL_CAL_CFG6
- REG_EDP_28nm_PHY_PLL_CAL_CFG7
- REG_EDP_28nm_PHY_PLL_CAL_CFG8
- REG_EDP_28nm_PHY_PLL_CAL_CFG9
- REG_EDP_28nm_PHY_PLL_CHGPUMP_CFG
- REG_EDP_28nm_PHY_PLL_DEBUG_BUS_SEL
- REG_EDP_28nm_PHY_PLL_DMUX_CFG
- REG_EDP_28nm_PHY_PLL_EFUSE_CFG
- REG_EDP_28nm_PHY_PLL_GLB_CFG
- REG_EDP_28nm_PHY_PLL_LKDET_CFG0
- REG_EDP_28nm_PHY_PLL_LKDET_CFG1
- REG_EDP_28nm_PHY_PLL_LKDET_CFG2
- REG_EDP_28nm_PHY_PLL_LPFC1_CFG
- REG_EDP_28nm_PHY_PLL_LPFC2_CFG
- REG_EDP_28nm_PHY_PLL_LPFR_CFG
- REG_EDP_28nm_PHY_PLL_POSTDIV1_CFG
- REG_EDP_28nm_PHY_PLL_POSTDIV2_CFG
- REG_EDP_28nm_PHY_PLL_POSTDIV3_CFG
- REG_EDP_28nm_PHY_PLL_PWRGEN_CFG
- REG_EDP_28nm_PHY_PLL_REFCLK_CFG
- REG_EDP_28nm_PHY_PLL_SDM_CFG0
- REG_EDP_28nm_PHY_PLL_SDM_CFG1
- REG_EDP_28nm_PHY_PLL_SDM_CFG2
- REG_EDP_28nm_PHY_PLL_SDM_CFG3
- REG_EDP_28nm_PHY_PLL_SDM_CFG4
- REG_EDP_28nm_PHY_PLL_SSC_CFG0
- REG_EDP_28nm_PHY_PLL_SSC_CFG1
- REG_EDP_28nm_PHY_PLL_SSC_CFG2
- REG_EDP_28nm_PHY_PLL_SSC_CFG3
- REG_EDP_28nm_PHY_PLL_TEST_CFG
- REG_EDP_28nm_PHY_PLL_VCOLPF_CFG
- REG_EDP_28nm_PHY_PLL_VREG_CFG
- REG_EDP_ACTIVE_HOR_VER
- REG_EDP_AUX_CTRL
- REG_EDP_AUX_DATA
- REG_EDP_AUX_STATUS
- REG_EDP_AUX_TRANS_CTRL
- REG_EDP_CONFIGURATION_CTRL
- REG_EDP_HSYNC_VSYNC_WIDTH_POLARITY
- REG_EDP_INTERRUPT_REG_1
- REG_EDP_INTERRUPT_REG_2
- REG_EDP_INTERRUPT_TRANS_NUM
- REG_EDP_MAINLINK_CTRL
- REG_EDP_MAINLINK_READY
- REG_EDP_MISC1_MISC0
- REG_EDP_PHY_CTRL
- REG_EDP_PHY_GLB_CFG
- REG_EDP_PHY_GLB_MISC9
- REG_EDP_PHY_GLB_PD_CTL
- REG_EDP_PHY_GLB_PHY_STATUS
- REG_EDP_PHY_GLB_VM_CFG0
- REG_EDP_PHY_GLB_VM_CFG1
- REG_EDP_PHY_LN
- REG_EDP_PHY_LN_PD_CTL
- REG_EDP_SOFTWARE_MVID
- REG_EDP_SOFTWARE_NVID
- REG_EDP_START_HOR_VER_FROM_SYNC
- REG_EDP_STATE_CTRL
- REG_EDP_TOTAL_HOR_VER
- REG_EDX
- REG_EEPROM
- REG_EEPROM_CTRL
- REG_EEPROM_DATA_LO
- REG_EE_VPD
- REG_EE_VPD_8723B
- REG_EFFECTIVE_IN_ADEEN
- REG_EFFECTIVE_IN_ADEEN_FRMEND
- REG_EFFECTIVE_IN_VSYNC
- REG_EFFECTIVE_IN_VSYNC_FRMEND
- REG_EFFECT_EMBOSS
- REG_EFFECT_NEGA
- REG_EFFECT_OFF
- REG_EFFECT_OUTLINE
- REG_EFFECT_WATERCOLOR
- REG_EFUSE_ACCESS
- REG_EFUSE_ACCESS_8723
- REG_EFUSE_BURN_GNT_8723B
- REG_EFUSE_CLK
- REG_EFUSE_CTRL
- REG_EFUSE_CTRL_8723B
- REG_EFUSE_DOUT
- REG_EFUSE_TEST
- REG_EFUSE_TEST_8723B
- REG_EGR_CONTROL
- REG_EIFS
- REG_EIFS_8723B
- REG_EMITTER_DAC
- REG_EMSCINTR
- REG_EMSCINTR1
- REG_EMSCINTRMASK
- REG_EMSCINTRMASK1
- REG_EMSCRFIFOBCNTH
- REG_EMSCRFIFOBCNTL
- REG_EMSC_RCV_READ_PORT
- REG_EMSC_XMIT_WRITE_PORT
- REG_ENABLE
- REG_ENABLE_SPACE
- REG_ENABLE_TX_RX
- REG_ENA_ACLK
- REG_ENA_AP
- REG_ENA_VP_0
- REG_ENA_VP_1
- REG_ENA_VP_2
- REG_ENCCK
- REG_ENCR_CCM_INT_CNTR0
- REG_ENCR_CCM_INT_CNTR1
- REG_ENCR_CCM_INT_CNTR2
- REG_ENCR_CCM_INT_CNTR3
- REG_ENCR_KEY0
- REG_ENCR_KEY1
- REG_ENCR_KEY2
- REG_ENCR_KEY3
- REG_ENCR_KEY4
- REG_ENCR_KEY5
- REG_ENCR_KEY6
- REG_ENCR_KEY7
- REG_ENCR_SEG_CFG
- REG_ENCR_SEG_SIZE
- REG_ENCR_SEG_START
- REG_ENCR_XTS_DU_SIZE
- REG_ENCR_XTS_KEY0
- REG_ENCR_XTS_KEY1
- REG_ENCR_XTS_KEY2
- REG_ENCR_XTS_KEY3
- REG_ENCR_XTS_KEY4
- REG_ENCR_XTS_KEY5
- REG_ENCR_XTS_KEY6
- REG_ENCR_XTS_KEY7
- REG_ENC_CNTRL
- REG_ENDP_INTR
- REG_ENFN
- REG_ENFORCE_GRACE_MS
- REG_ENGINES_AVAIL
- REG_ENHANCE_ACOUSTICS1
- REG_ENHANCE_ACOUSTICS2
- REG_ENTROPY_DATA
- REG_ENTROPY_IV
- REG_ENTROPY_KEY0
- REG_ENTROPY_KEYN
- REG_ENTROPY_MODE
- REG_ENTROPY_RAND_REG
- REG_ENTROPY_RESET
- REG_ENTROPY_START
- REG_ENTROPY_STATUS
- REG_ENTRY
- REG_ENTRY_MODE
- REG_ENTXCCK
- REG_EN_CTL
- REG_EN_INTRD
- REG_EN_MASK
- REG_EN_OSC_PERIOD_LSB
- REG_EN_RST_ERROR
- REG_EP_NUM
- REG_EQ_AUTO_CONTROL
- REG_EQ_MAN_CTRL0
- REG_EQ_MAN_CTRL1
- REG_ERRCTRL_OFFSET
- REG_ERROR
- REG_ERR_IER
- REG_ERR_ISDR
- REG_ERR_ISR
- REG_ESAI_ECR
- REG_ESAI_ERDR
- REG_ESAI_ESR
- REG_ESAI_ETDR
- REG_ESAI_PCRC
- REG_ESAI_PRRC
- REG_ESAI_RCCR
- REG_ESAI_RCR
- REG_ESAI_RFCR
- REG_ESAI_RFSR
- REG_ESAI_RSMA
- REG_ESAI_RSMB
- REG_ESAI_RX0
- REG_ESAI_RX1
- REG_ESAI_RX2
- REG_ESAI_RX3
- REG_ESAI_SAICR
- REG_ESAI_SAISR
- REG_ESAI_TCCR
- REG_ESAI_TCR
- REG_ESAI_TFCR
- REG_ESAI_TFSR
- REG_ESAI_TSMA
- REG_ESAI_TSMB
- REG_ESAI_TSR
- REG_ESAI_TX0
- REG_ESAI_TX1
- REG_ESAI_TX2
- REG_ESAI_TX3
- REG_ESAI_TX4
- REG_ESAI_TX5
- REG_ESAI_xCCR
- REG_ESAI_xCR
- REG_ESAI_xFCR
- REG_ESAI_xFSR
- REG_ESAI_xSMA
- REG_ESAI_xSMB
- REG_ESI
- REG_ESLOTG1
- REG_ESLOTG23
- REG_ESLOTG45
- REG_ESLOTG67
- REG_ESP
- REG_EVENT_CAUSE
- REG_EVENT_MAILBOX_PTR
- REG_EXHCH
- REG_EXHCL
- REG_EXPANSION_ROM_RUN_END
- REG_EXPANSION_ROM_RUN_START
- REG_EXTCAP_DBC_CAPABILITY
- REG_EXTCAP_DBC_CONTROL
- REG_EXTCAP_DBC_CONT_HIGH
- REG_EXTCAP_DBC_CONT_LOW
- REG_EXTCAP_DBC_DEVINFO1
- REG_EXTCAP_DBC_DEVINFO2
- REG_EXTCAP_DBC_DOORBELL
- REG_EXTCAP_DBC_ERDP_HIGH
- REG_EXTCAP_DBC_ERDP_LOW
- REG_EXTCAP_DBC_ERSTSIZE
- REG_EXTCAP_DBC_ERST_HIGH
- REG_EXTCAP_DBC_ERST_LOW
- REG_EXTCAP_DBC_PORTSC
- REG_EXTCAP_DBC_STATUS
- REG_EXTCAP_MANTISSA1
- REG_EXTCAP_MANTISSA2
- REG_EXTCAP_MANTISSA3
- REG_EXTCAP_MANTISSA4
- REG_EXTCAP_MANTISSA5
- REG_EXTCAP_MANTISSA6
- REG_EXTCAP_NAME
- REG_EXTCAP_PORTINFO
- REG_EXTCAP_PORTTYPE
- REG_EXTCAP_REVISION
- REG_EXTCAP_USBLEGCTLSTS
- REG_EXTCAP_USBLEGSUP
- REG_EXTEND1
- REG_EXTEND2
- REG_EXTEND3
- REG_EXTPA_CFG
- REG_EXTPA_MSC
- REG_EXT_CTRL
- REG_EXT_FCC_DFS_HT40
- REG_EXT_FCC_MIDBAND
- REG_EXT_INTF_CONTROL
- REG_EXT_JAPAN_DFS_HT40
- REG_EXT_JAPAN_MIDBAND
- REG_EXT_JAPAN_NONDFS_HT40
- REG_F0
- REG_F0_REG_MASK
- REG_F1_MISC_MASK
- REG_FACT
- REG_FAMILY_ID
- REG_FANCOUNT_LOW
- REG_FAN_AUTO_MAN_SWITCH
- REG_FAN_CONF1
- REG_FAN_CONTROL
- REG_FAN_ENABLE
- REG_FAN_SPEED_HIGH
- REG_FAN_SPEED_LEVEL
- REG_FAN_SPEED_LOW
- REG_FAN_STATUS
- REG_FAN_TACH_HI
- REG_FAN_TACH_LO
- REG_FAN_TARGET_HI
- REG_FAN_TARGET_LO
- REG_FAR
- REG_FAST_EDCA_BEBK_SETTING
- REG_FAST_EDCA_CTRL
- REG_FAST_EDCA_CTRL_8723B
- REG_FAST_EDCA_VOVI_SETTING
- REG_FAST_INTR_STAT
- REG_FAST_SWTICH_CONTROL
- REG_FAST_SWTICH_SCART_DELAY
- REG_FAULT
- REG_FBIT_VBIT_CONTROL1
- REG_FBIT_VBIT_CONTROL2
- REG_FBPR_AR
- REG_FBPR_BAR
- REG_FBPR_BARE
- REG_FBPR_FPC
- REG_FBRD
- REG_FB_ADDR
- REG_FC4_VNPORT
- REG_FCCTR13
- REG_FCCTR14
- REG_FCCTR15
- REG_FCCTR50
- REG_FCF_INVALID_QID
- REG_FCGC
- REG_FCINTR0
- REG_FCINTR1
- REG_FCINTR2
- REG_FCINTR3
- REG_FCINTR4
- REG_FCINTR5
- REG_FCINTR6
- REG_FCINTR7
- REG_FCNT
- REG_FCR
- REG_FD
- REG_FDACSR
- REG_FDCFG
- REG_FDCFG_RXFIFOSIZE
- REG_FDCFG_RXFIFOSIZE_SHIFT
- REG_FDCFG_RXINTTHRES
- REG_FDCFG_RXINTTHRES_DISABLED
- REG_FDCFG_RXINTTHRES_FULL
- REG_FDCFG_RXINTTHRES_NEARFULL
- REG_FDCFG_RXINTTHRES_NOTEMPTY
- REG_FDCFG_RXINTTHRES_SHIFT
- REG_FDCFG_TXFIFOSIZE
- REG_FDCFG_TXFIFOSIZE_SHIFT
- REG_FDCFG_TXINTTHRES
- REG_FDCFG_TXINTTHRES_DISABLED
- REG_FDCFG_TXINTTHRES_EMPTY
- REG_FDCFG_TXINTTHRES_NEAREMPTY
- REG_FDCFG_TXINTTHRES_NOTFULL
- REG_FDCFG_TXINTTHRES_SHIFT
- REG_FDEV_LSB
- REG_FDEV_MSB
- REG_FDHM0
- REG_FDRX
- REG_FDSTAT
- REG_FDSTAT_RXCHAN
- REG_FDSTAT_RXCHAN_SHIFT
- REG_FDSTAT_RXCOUNT
- REG_FDSTAT_RXCOUNT_SHIFT
- REG_FDSTAT_RXE
- REG_FDSTAT_RXF
- REG_FDSTAT_TXCOUNT
- REG_FDSTAT_TXCOUNT_SHIFT
- REG_FDSTAT_TXE
- REG_FDSTAT_TXF
- REG_FDTX
- REG_FDW_E
- REG_FDW_S
- REG_FD_OFF
- REG_FE
- REG_FEATURE
- REG_FEATURES
- REG_FEAT_POWERDOWN
- REG_FEC_LOCK
- REG_FEILSB
- REG_FEIMSB
- REG_FER
- REG_FF
- REG_FFILT_CFG
- REG_FIELD
- REG_FIELDBUS_TYPE
- REG_FIELDBUS_V
- REG_FIELD_FOR_EACH_SENSOR11
- REG_FIELD_FOR_EACH_SENSOR16
- REG_FIELD_GET
- REG_FIELD_MASK
- REG_FIELD_PREP
- REG_FIELD_SHIFT
- REG_FIFO
- REG_FIFO0
- REG_FIFO0CNT
- REG_FIFO0THR
- REG_FIFO1
- REG_FIFO1CNT
- REG_FIFO1THR
- REG_FIFOPAGE
- REG_FIFOPAGE_8723B
- REG_FIFOPAGE_CTRL_2
- REG_FIFOPAGE_INFO_1
- REG_FIFOPAGE_INFO_2
- REG_FIFOPAGE_INFO_3
- REG_FIFOPAGE_INFO_4
- REG_FIFOPAGE_INFO_5
- REG_FIFO_COUNT
- REG_FIFO_DEPTH_DWORDS
- REG_FIFO_DEPTH_ELEMENTS
- REG_FIFO_DROP_CNT
- REG_FIFO_ELEMENT_ACCESS_MASK
- REG_FIFO_ELEMENT_ACCESS_SHIFT
- REG_FIFO_ELEMENT_ADDRESS_MASK
- REG_FIFO_ELEMENT_ADDRESS_SHIFT
- REG_FIFO_ELEMENT_ADDR_FACTOR
- REG_FIFO_ELEMENT_DWORDS
- REG_FIFO_ELEMENT_ERROR_MASK
- REG_FIFO_ELEMENT_ERROR_SHIFT
- REG_FIFO_ELEMENT_IS_PF_VF_VAL
- REG_FIFO_ELEMENT_MASTER_MASK
- REG_FIFO_ELEMENT_MASTER_SHIFT
- REG_FIFO_ELEMENT_PF_MASK
- REG_FIFO_ELEMENT_PF_SHIFT
- REG_FIFO_ELEMENT_PORT_MASK
- REG_FIFO_ELEMENT_PORT_SHIFT
- REG_FIFO_ELEMENT_PRIVILEGE_MASK
- REG_FIFO_ELEMENT_PRIVILEGE_SHIFT
- REG_FIFO_ELEMENT_PROTECTION_MASK
- REG_FIFO_ELEMENT_PROTECTION_SHIFT
- REG_FIFO_ELEMENT_VF_MASK
- REG_FIFO_ELEMENT_VF_SHIFT
- REG_FIFO_LATENCY_VAL
- REG_FIFO_READ_DATA
- REG_FIFO_SIZES
- REG_FIFO_THRESH
- REG_FILE_MODE
- REG_FILONOFF
- REG_FILTERS_CTRL
- REG_FILTER_SEL
- REG_FILTER_SEL_SHIFT
- REG_FILTER_STRENGTH
- REG_FILT_TIME
- REG_FIQ_CONTROL
- REG_FIRMWARE_VERSION
- REG_FIRST_SCREEN_DRIVE_POS
- REG_FIXED
- REG_FLAG
- REG_FLAGS0
- REG_FLAGS1
- REG_FLASH
- REG_FLASH_AUTO
- REG_FLASH_BR
- REG_FLASH_CTRL
- REG_FLASH_OFF
- REG_FLASH_ON
- REG_FLASH_RW_MEM
- REG_FLASH_TOUT
- REG_FLD_MOD
- REG_FLD_WAIT
- REG_FLOW_CTRL
- REG_FL_CONF_1
- REG_FL_CONF_2
- REG_FL_CONF_3
- REG_FMETHR
- REG_FMETHR_8723B
- REG_FMT
- REG_FMTHR
- REG_FMT_DEC
- REG_FMT_DE_ACT
- REG_FMT_HEX
- REG_FMT_H_ACT
- REG_FMT_H_BACK
- REG_FMT_H_FRONT
- REG_FMT_H_SYNC
- REG_FMT_H_TOT
- REG_FMT_V_ACT
- REG_FMT_V_BACK_F1
- REG_FMT_V_BACK_F2
- REG_FMT_V_FRONT_F1
- REG_FMT_V_FRONT_F2
- REG_FMT_V_SYNC
- REG_FMT_V_TOT
- REG_FM_FREQ
- REG_FN_ERR
- REG_FN_MODIFY_BASE
- REG_FN_TEST_BASE
- REG_FN_WRITE_BASE
- REG_FORCE_FMT
- REG_FORMAT_CTRL00
- REG_FP
- REG_FPCR
- REG_FPGA0_ANALOG1
- REG_FPGA0_ANALOG2
- REG_FPGA0_ANALOG3
- REG_FPGA0_ANALOG4
- REG_FPGA0_IQK
- REG_FPGA0_POWER_SAVE
- REG_FPGA0_PSD_FUNC
- REG_FPGA0_RF_MODE
- REG_FPGA0_RF_TIMING1
- REG_FPGA0_RF_TIMING2
- REG_FPGA0_TX_GAIN
- REG_FPGA0_TX_INFO
- REG_FPGA0_XAB_RF_PARM
- REG_FPGA0_XAB_RF_SW_CTRL
- REG_FPGA0_XA_HSSI_PARM1
- REG_FPGA0_XA_HSSI_PARM2
- REG_FPGA0_XA_LSSI_PARM
- REG_FPGA0_XA_LSSI_READBACK
- REG_FPGA0_XA_RF_INT_OE
- REG_FPGA0_XA_RF_PARM
- REG_FPGA0_XA_RF_SW_CTRL
- REG_FPGA0_XB_HSSI_PARM1
- REG_FPGA0_XB_HSSI_PARM2
- REG_FPGA0_XB_LSSI_PARM
- REG_FPGA0_XB_LSSI_READBACK
- REG_FPGA0_XB_RF_INT_OE
- REG_FPGA0_XB_RF_PARM
- REG_FPGA0_XB_RF_SW_CTRL
- REG_FPGA0_XCD_RF_PARM
- REG_FPGA0_XCD_RF_SW_CTRL
- REG_FPGA0_XCD_SWITCH_CTRL
- REG_FPGA0_XC_RF_PARM
- REG_FPGA0_XC_RF_SW_CTRL
- REG_FPGA0_XD_RF_PARM
- REG_FPGA0_XD_RF_SW_CTRL
- REG_FPGA1_RF_MODE
- REG_FPGA1_TX_INFO
- REG_FPGA_DDNA
- REG_FPGA_HW_ID
- REG_FPGA_SSID
- REG_FPREG0
- REG_FPREG15
- REG_FPSCR
- REG_FPS_30
- REG_FPUL
- REG_FQD_BARE
- REG_FR
- REG_FRAJH
- REG_FRAJL
- REG_FRAME
- REG_FRAME_CYCLE_CONTROL
- REG_FRAME_DATABITS
- REG_FRAME_DATABITS__MASK
- REG_FRAME_ERR_CNT
- REG_FRAME_LENGTH_LINES
- REG_FRAME_LENGTH_LINES_
- REG_FRARL
- REG_FREF_F1_S
- REG_FREF_F2_S
- REG_FREQ_LUT
- REG_FREQ_SYNC_RANGE
- REG_FRF_LSB
- REG_FRF_MID
- REG_FRF_MSB
- REG_FROMOFFSET
- REG_FSIMR
- REG_FSIMR_8723B
- REG_FSISR
- REG_FSISR_8723B
- REG_FSTAT
- REG_FTIMR
- REG_FTIMR_8723B
- REG_FTISR
- REG_FTM
- REG_FULL_CHARGE_CAPACITY
- REG_FULL_CHARGE_CAPACITY_CHARGE
- REG_FWDLY
- REG_FWHW_TXQ_CTRL
- REG_FWHW_TXQ_CTRL_8723B
- REG_FWIMR
- REG_FWIMR_8723B
- REG_FWISR
- REG_FWISR_8723B
- REG_FW_APIVER
- REG_FW_BCN_DIS_CNT
- REG_FW_DBG7
- REG_FW_RESET_TSF_CNT_0
- REG_FW_RESET_TSF_CNT_1
- REG_FW_REVISION
- REG_FW_SENSOR_ID
- REG_FW_START_ADDRESS
- REG_FW_STS
- REG_FW_STS_CIO_RESET_REQ
- REG_FW_STS_ICM_EN
- REG_FW_STS_ICM_EN_CPU
- REG_FW_STS_ICM_EN_INVERT
- REG_FW_STS_NVM_AUTH_DONE
- REG_FW_UPD_RDPTR
- REG_FW_UPD_RDPTR_8723B
- REG_FW_VERSION
- REG_GAIN
- REG_GAIN_BIAS
- REG_GAIN_DB_END
- REG_GAIN_DB_START
- REG_GAIN_MUX
- REG_GAIN_RAW_END
- REG_GAIN_RAW_START
- REG_GAM1
- REG_GAM2
- REG_GAM3
- REG_GAMMA_CONTROL_1
- REG_GAMMA_CONTROL_10
- REG_GAMMA_CONTROL_2
- REG_GAMMA_CONTROL_3
- REG_GAMMA_CONTROL_4
- REG_GAMMA_CONTROL_5
- REG_GAMMA_CONTROL_6
- REG_GAMMA_CONTROL_7
- REG_GAMMA_CONTROL_8
- REG_GAMMA_CONTROL_9
- REG_GATECLK
- REG_GATE_SCAN_CONTROL
- REG_GAVG
- REG_GBBIAS
- REG_GBD_PACKET_TYPE
- REG_GBOS
- REG_GBR
- REG_GB_AVE
- REG_GC360_CLKCTL
- REG_GCCR
- REG_GCIECR
- REG_GCISCR
- REG_GCRBBR
- REG_GCRBEXHR
- REG_GCRBHR
- REG_GCRBLR
- REG_GCRBTR
- REG_GEN3_CTSR
- REG_GEN3_IRQCTL
- REG_GEN3_IRQEN
- REG_GEN3_IRQMSK
- REG_GEN3_IRQSTR
- REG_GEN3_IRQTEMP1
- REG_GEN3_IRQTEMP2
- REG_GEN3_IRQTEMP3
- REG_GEN3_TEMP
- REG_GEN3_THCODE1
- REG_GEN3_THCODE2
- REG_GEN3_THCODE3
- REG_GEN3_THCTR
- REG_GENCTL
- REG_GENERAL_OPTION
- REG_GENMASK
- REG_GEN_PURP_0
- REG_GET
- REG_GET_2
- REG_GET_3
- REG_GET_4
- REG_GET_5
- REG_GET_6
- REG_GET_7
- REG_GET_8
- REG_GET_FIELD
- REG_GET_MASK
- REG_GFIX
- REG_GFX3DCORE_CLKCTL
- REG_GFX3DEXTRA_CLKCTL
- REG_GFX3DSYS_CLKCTL
- REG_GFX3D_RESET
- REG_GGAIN
- REG_GIINTMSK
- REG_GIINTMSK_ENABLE
- REG_GIM_P_INT_BLK_0
- REG_GIM_P_INT_DST_10
- REG_GIM_P_INT_DST_11
- REG_GIM_P_INT_DST_25
- REG_GIM_P_INT_DST_26
- REG_GIM_P_INT_EN_0
- REG_GIM_P_INT_POL_0
- REG_GIM_P_INT_SENS_0
- REG_GLOBAL
- REG_GLOBAL_OPTIONS
- REG_GLOBAL_RR_INDEX__1
- REG_GL_CSR
- REG_GL_FCR
- REG_GL_GPIOR
- REG_GL_IMASK
- REG_GMCO
- REG_GOPROC
- REG_GOPROC_OEM_KEY
- REG_GOPROC_QC_KEY
- REG_GPHY_CTRL
- REG_GPIO
- REG_GPIODATADIR1
- REG_GPIODATADIR2
- REG_GPIODATADIR3
- REG_GPIODATAIN1
- REG_GPIODATAIN2
- REG_GPIODATAIN3
- REG_GPIODATAOUT1
- REG_GPIODATAOUT2
- REG_GPIODATAOUT3
- REG_GPIOPUPDCTR1
- REG_GPIOPUPDCTR2
- REG_GPIOPUPDCTR3
- REG_GPIOPUPDCTR4
- REG_GPIOPUPDCTR5
- REG_GPIO_CTRL
- REG_GPIO_CTRL1
- REG_GPIO_DAT_OUT1
- REG_GPIO_DAT_OUT2
- REG_GPIO_DAT_OUT3
- REG_GPIO_DAT_STAT1
- REG_GPIO_DAT_STAT2
- REG_GPIO_DAT_STAT3
- REG_GPIO_DEBEN1
- REG_GPIO_DEBEN2
- REG_GPIO_DEBEN3
- REG_GPIO_DIR1
- REG_GPIO_DIR2
- REG_GPIO_DIR3
- REG_GPIO_DMA_CTL
- REG_GPIO_EDR1
- REG_GPIO_EDR2
- REG_GPIO_EDR3
- REG_GPIO_EDR4
- REG_GPIO_EDR5
- REG_GPIO_EXT_CTRL
- REG_GPIO_IMR1A
- REG_GPIO_IMR1B
- REG_GPIO_IMR2A
- REG_GPIO_IMR2B
- REG_GPIO_IMR3A
- REG_GPIO_IMR3B
- REG_GPIO_IN
- REG_GPIO_INPUT1
- REG_GPIO_INPUT2
- REG_GPIO_INTM
- REG_GPIO_INTM_8723B
- REG_GPIO_INT_EN1
- REG_GPIO_INT_EN2
- REG_GPIO_INT_EN3
- REG_GPIO_INT_LVL1
- REG_GPIO_INT_LVL2
- REG_GPIO_INT_LVL3
- REG_GPIO_INT_STAT1
- REG_GPIO_INT_STAT2
- REG_GPIO_INT_STAT3
- REG_GPIO_IO_SEL
- REG_GPIO_IO_SEL_2
- REG_GPIO_IO_SEL_8723B
- REG_GPIO_ISR1A
- REG_GPIO_ISR1B
- REG_GPIO_ISR2A
- REG_GPIO_ISR2B
- REG_GPIO_ISR3A
- REG_GPIO_ISR3B
- REG_GPIO_MUXCFG
- REG_GPIO_MUXCFG_8723B
- REG_GPIO_OUT
- REG_GPIO_OUTPUT
- REG_GPIO_OUTSTS
- REG_GPIO_PIN_CTRL
- REG_GPIO_PIN_CTRL_2
- REG_GPIO_PIN_CTRL_8723B
- REG_GPIO_PULL1
- REG_GPIO_PULL2
- REG_GPIO_PULL3
- REG_GPIO_SIH_CTRL
- REG_GPIO_STATUS_8723B
- REG_GPI_EM1
- REG_GPI_EM2
- REG_GPI_EM3
- REG_GPPUPDCTR1
- REG_GPR
- REG_GP_CFG
- REG_GP_DRV
- REG_GP_HALT
- REG_GP_HALTED
- REG_GP_IN
- REG_GP_OUT
- REG_GP_REG0_LSB
- REG_GP_REG0_MSB
- REG_GRCOM
- REG_GREEN1_GAIN
- REG_GREEN2_GAIN
- REG_GROS
- REG_GROUPED_PARAMETER_HOLD
- REG_GROUPED_PARAMETER_HOLD_
- REG_GROUP_ACCESS
- REG_GROUP_ADDRESS_00
- REG_GROUP_ADDRESS_01
- REG_GROUP_ADDRESS_02
- REG_GROUP_ADDRESS_03
- REG_GROUP_CMD
- REG_GROUP_DATA
- REG_GROUP_QUERY
- REG_GRR
- REG_GR_AVE
- REG_GSP
- REG_GSSR
- REG_GST
- REG_GSWCK_EN
- REG_GTH_DESTOVR
- REG_GTH_GSWTDEST
- REG_GTH_GTHOPT0
- REG_GTH_GTHOPT1
- REG_GTH_LENGTH
- REG_GTH_OFFSET
- REG_GTH_SCR
- REG_GTH_SCR2
- REG_GTH_SCRPD0
- REG_GTH_SCRPD1
- REG_GTH_SCRPD2
- REG_GTH_SCRPD3
- REG_GTH_SMCR0
- REG_GTH_SMCR1
- REG_GTH_SMCR2
- REG_GTH_SMCR3
- REG_GTH_STAT
- REG_GTH_SWDEST0
- REG_GUSB2PHYCFG0
- REG_GUSB3PIPECTL0
- REG_G_ACTIVE_PREV_CFG
- REG_G_ACTUAL_C_FR_TIME
- REG_G_ACTUAL_C_OUT_RATE
- REG_G_ACTUAL_P_FR_TIME
- REG_G_ACTUAL_P_OUT_RATE
- REG_G_CAPZOOM_IN_HEIGHT
- REG_G_CAPZOOM_IN_WIDTH
- REG_G_CAPZOOM_IN_XOFFS
- REG_G_CAPZOOM_IN_YOFFS
- REG_G_CAP_IN_HEIGHT
- REG_G_CAP_IN_WIDTH
- REG_G_CAP_IN_XOFFS
- REG_G_CAP_IN_YOFFS
- REG_G_ENABLE_PREV
- REG_G_ENABLE_PREV_CHG
- REG_G_INPUTS_CHANGE_REQ
- REG_G_NEW_CFG_SYNC
- REG_G_PREVREQ_IN_HEIGHT
- REG_G_PREVREQ_IN_WIDTH
- REG_G_PREVREQ_IN_XOFFS
- REG_G_PREVREQ_IN_YOFFS
- REG_G_PREVZOOM_IN_HEIGHT
- REG_G_PREVZOOM_IN_WIDTH
- REG_G_PREVZOOM_IN_XOFFS
- REG_G_PREVZOOM_IN_YOFFS
- REG_G_PREV_CFG_BYPASS_CHANGED
- REG_G_PREV_CFG_CHG
- REG_G_PREV_CFG_ERROR
- REG_G_PREV_IN_HEIGHT
- REG_G_PREV_IN_WIDTH
- REG_G_PREV_IN_XOFFS
- REG_G_PREV_IN_YOFFS
- REG_G_PREV_OPEN_AFTER_CH
- REG_G_SPEC_EFFECTS
- REG_GbAVE
- REG_H
- REG_H2CQ_CSR
- REG_H2C_HEAD
- REG_H2C_INFO
- REG_H2C_MSG_DRV2FW_INFO
- REG_H2C_PKT_READADDR
- REG_H2C_PKT_WRITEADDR
- REG_H2C_READ_ADDR
- REG_H2C_TAIL
- REG_HAEC
- REG_HAECC1
- REG_HAECC2
- REG_HAECC3
- REG_HAECC4
- REG_HAECC5
- REG_HAECC6
- REG_HAECC7
- REG_HARDWARE_THERMAL_CONTROL
- REG_HCCPARAMS1
- REG_HCCPARAMS2
- REG_HCI_OPT_CTRL
- REG_HCSPARAMS1
- REG_HCSPARAMS2
- REG_HCSPARAMS3
- REG_HDAQ_DESA_NODEF
- REG_HDCP2X_AUTH_STAT
- REG_HDCP2X_CTRL_0
- REG_HDCP2X_CTRL_1
- REG_HDCP2X_DDCM_STS
- REG_HDCP2X_GP_OUT0
- REG_HDCP2X_INTR0
- REG_HDCP2X_INTR0_MASK
- REG_HDCP2X_MISC_CTRL
- REG_HDCP2X_POLL_CS
- REG_HDCP2X_RPT_RCVID_OUT
- REG_HDCP2X_RPT_RCVR_ID0
- REG_HDCP2X_RPT_SMNG_IN
- REG_HDCP2X_RPT_SMNG_K
- REG_HDCP2X_TP1
- REG_HDCP_BCAPS
- REG_HDCP_CTRL
- REG_HDCP_DDC_ADDR
- REG_HDCP_DE_CTRL
- REG_HDCP_EP_FILT_CTRL
- REG_HDCP_KDS
- REG_HDCP_KEY_CTRL
- REG_HDCP_KIDX
- REG_HDMI_28nm_PHY_PLL_AMUX_CFG
- REG_HDMI_28nm_PHY_PLL_CAL_CFG0
- REG_HDMI_28nm_PHY_PLL_CAL_CFG1
- REG_HDMI_28nm_PHY_PLL_CAL_CFG10
- REG_HDMI_28nm_PHY_PLL_CAL_CFG11
- REG_HDMI_28nm_PHY_PLL_CAL_CFG2
- REG_HDMI_28nm_PHY_PLL_CAL_CFG3
- REG_HDMI_28nm_PHY_PLL_CAL_CFG4
- REG_HDMI_28nm_PHY_PLL_CAL_CFG5
- REG_HDMI_28nm_PHY_PLL_CAL_CFG6
- REG_HDMI_28nm_PHY_PLL_CAL_CFG7
- REG_HDMI_28nm_PHY_PLL_CAL_CFG8
- REG_HDMI_28nm_PHY_PLL_CAL_CFG9
- REG_HDMI_28nm_PHY_PLL_CHGPUMP_CFG
- REG_HDMI_28nm_PHY_PLL_DEBUG_BUS_SEL
- REG_HDMI_28nm_PHY_PLL_DMUX_CFG
- REG_HDMI_28nm_PHY_PLL_EFUSE_CFG
- REG_HDMI_28nm_PHY_PLL_GLB_CFG
- REG_HDMI_28nm_PHY_PLL_LKDET_CFG0
- REG_HDMI_28nm_PHY_PLL_LKDET_CFG1
- REG_HDMI_28nm_PHY_PLL_LKDET_CFG2
- REG_HDMI_28nm_PHY_PLL_LPFC1_CFG
- REG_HDMI_28nm_PHY_PLL_LPFC2_CFG
- REG_HDMI_28nm_PHY_PLL_LPFR_CFG
- REG_HDMI_28nm_PHY_PLL_POSTDIV1_CFG
- REG_HDMI_28nm_PHY_PLL_POSTDIV2_CFG
- REG_HDMI_28nm_PHY_PLL_POSTDIV3_CFG
- REG_HDMI_28nm_PHY_PLL_PWRGEN_CFG
- REG_HDMI_28nm_PHY_PLL_REFCLK_CFG
- REG_HDMI_28nm_PHY_PLL_SDM_CFG0
- REG_HDMI_28nm_PHY_PLL_SDM_CFG1
- REG_HDMI_28nm_PHY_PLL_SDM_CFG2
- REG_HDMI_28nm_PHY_PLL_SDM_CFG3
- REG_HDMI_28nm_PHY_PLL_SDM_CFG4
- REG_HDMI_28nm_PHY_PLL_SSC_CFG0
- REG_HDMI_28nm_PHY_PLL_SSC_CFG1
- REG_HDMI_28nm_PHY_PLL_SSC_CFG2
- REG_HDMI_28nm_PHY_PLL_SSC_CFG3
- REG_HDMI_28nm_PHY_PLL_TEST_CFG
- REG_HDMI_28nm_PHY_PLL_VCOLPF_CFG
- REG_HDMI_28nm_PHY_PLL_VREG_CFG
- REG_HDMI_8960_PHY_DEBUG_BUS_SEL
- REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG
- REG_HDMI_8960_PHY_PLL_DEBUG_BUS0
- REG_HDMI_8960_PHY_PLL_DEBUG_BUS1
- REG_HDMI_8960_PHY_PLL_DEBUG_BUS2
- REG_HDMI_8960_PHY_PLL_DEBUG_SEL
- REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG
- REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG
- REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0
- REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1
- REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2
- REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0
- REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1
- REG_HDMI_8960_PHY_PLL_MISC0
- REG_HDMI_8960_PHY_PLL_MISC1
- REG_HDMI_8960_PHY_PLL_MISC2
- REG_HDMI_8960_PHY_PLL_MISC3
- REG_HDMI_8960_PHY_PLL_MISC4
- REG_HDMI_8960_PHY_PLL_MISC5
- REG_HDMI_8960_PHY_PLL_MISC6
- REG_HDMI_8960_PHY_PLL_PWRDN_B
- REG_HDMI_8960_PHY_PLL_REFCLK_CFG
- REG_HDMI_8960_PHY_PLL_SDM_CFG0
- REG_HDMI_8960_PHY_PLL_SDM_CFG1
- REG_HDMI_8960_PHY_PLL_SDM_CFG2
- REG_HDMI_8960_PHY_PLL_SDM_CFG3
- REG_HDMI_8960_PHY_PLL_SDM_CFG4
- REG_HDMI_8960_PHY_PLL_SSC_CFG0
- REG_HDMI_8960_PHY_PLL_SSC_CFG1
- REG_HDMI_8960_PHY_PLL_SSC_CFG2
- REG_HDMI_8960_PHY_PLL_SSC_CFG3
- REG_HDMI_8960_PHY_PLL_STATUS0
- REG_HDMI_8960_PHY_PLL_STATUS1
- REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0
- REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1
- REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2
- REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3
- REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4
- REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5
- REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6
- REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7
- REG_HDMI_8960_PHY_REG0
- REG_HDMI_8960_PHY_REG1
- REG_HDMI_8960_PHY_REG10
- REG_HDMI_8960_PHY_REG11
- REG_HDMI_8960_PHY_REG12
- REG_HDMI_8960_PHY_REG13
- REG_HDMI_8960_PHY_REG14
- REG_HDMI_8960_PHY_REG15
- REG_HDMI_8960_PHY_REG2
- REG_HDMI_8960_PHY_REG3
- REG_HDMI_8960_PHY_REG4
- REG_HDMI_8960_PHY_REG5
- REG_HDMI_8960_PHY_REG6
- REG_HDMI_8960_PHY_REG7
- REG_HDMI_8960_PHY_REG8
- REG_HDMI_8960_PHY_REG9
- REG_HDMI_8960_PHY_REG_BIST_CFG
- REG_HDMI_8960_PHY_REG_MISC0
- REG_HDMI_8996_PHY_CFG
- REG_HDMI_8996_PHY_CLOCK
- REG_HDMI_8996_PHY_DEBUG_BUS0
- REG_HDMI_8996_PHY_DEBUG_BUS1
- REG_HDMI_8996_PHY_DEBUG_BUS2
- REG_HDMI_8996_PHY_DEBUG_BUS3
- REG_HDMI_8996_PHY_DEBUG_BUS_SEL
- REG_HDMI_8996_PHY_LANE_BIST_CONFIG
- REG_HDMI_8996_PHY_MISC1
- REG_HDMI_8996_PHY_MISC2
- REG_HDMI_8996_PHY_MISC3_STATUS
- REG_HDMI_8996_PHY_MISC4_STATUS
- REG_HDMI_8996_PHY_MISR_CLEAR
- REG_HDMI_8996_PHY_MODE
- REG_HDMI_8996_PHY_PD_CTL
- REG_HDMI_8996_PHY_PHY_REVISION_ID0
- REG_HDMI_8996_PHY_PHY_REVISION_ID1
- REG_HDMI_8996_PHY_PHY_REVISION_ID2
- REG_HDMI_8996_PHY_PHY_REVISION_ID3
- REG_HDMI_8996_PHY_POST_MISR_STATUS0
- REG_HDMI_8996_PHY_POST_MISR_STATUS1
- REG_HDMI_8996_PHY_POST_MISR_STATUS2
- REG_HDMI_8996_PHY_POST_MISR_STATUS3
- REG_HDMI_8996_PHY_PRE_MISR_STATUS0
- REG_HDMI_8996_PHY_PRE_MISR_STATUS1
- REG_HDMI_8996_PHY_PRE_MISR_STATUS2
- REG_HDMI_8996_PHY_PRE_MISR_STATUS3
- REG_HDMI_8996_PHY_STATUS
- REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG0
- REG_HDMI_8996_PHY_TX0_TX1_BIST_CFG1
- REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN0
- REG_HDMI_8996_PHY_TX0_TX1_BIST_PATTERN1
- REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS0
- REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS1
- REG_HDMI_8996_PHY_TX0_TX1_BIST_STATUS2
- REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL
- REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE0
- REG_HDMI_8996_PHY_TX0_TX1_PRBS_SEED_BYTE1
- REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG0
- REG_HDMI_8996_PHY_TX2_TX3_BIST_CFG1
- REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN0
- REG_HDMI_8996_PHY_TX2_TX3_BIST_PATTERN1
- REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS0
- REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS1
- REG_HDMI_8996_PHY_TX2_TX3_BIST_STATUS2
- REG_HDMI_8996_PHY_TX2_TX3_LANE_CTL
- REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE0
- REG_HDMI_8996_PHY_TX2_TX3_PRBS_SEED_BYTE1
- REG_HDMI_8996_PHY_TXCAL_CFG0
- REG_HDMI_8996_PHY_TXCAL_CFG1
- REG_HDMI_8x60_PHY_REG0
- REG_HDMI_8x60_PHY_REG1
- REG_HDMI_8x60_PHY_REG10
- REG_HDMI_8x60_PHY_REG11
- REG_HDMI_8x60_PHY_REG12
- REG_HDMI_8x60_PHY_REG2
- REG_HDMI_8x60_PHY_REG3
- REG_HDMI_8x60_PHY_REG4
- REG_HDMI_8x60_PHY_REG5
- REG_HDMI_8x60_PHY_REG6
- REG_HDMI_8x60_PHY_REG7
- REG_HDMI_8x60_PHY_REG8
- REG_HDMI_8x60_PHY_REG9
- REG_HDMI_8x74_ANA_CFG0
- REG_HDMI_8x74_ANA_CFG1
- REG_HDMI_8x74_BIST_CFG0
- REG_HDMI_8x74_BIST_PATN0
- REG_HDMI_8x74_BIST_PATN1
- REG_HDMI_8x74_BIST_PATN2
- REG_HDMI_8x74_BIST_PATN3
- REG_HDMI_8x74_PD_CTRL0
- REG_HDMI_8x74_PD_CTRL1
- REG_HDMI_ACR
- REG_HDMI_ACR_0
- REG_HDMI_ACR_1
- REG_HDMI_ACR_PKT_CTRL
- REG_HDMI_ACTIVE_HSYNC
- REG_HDMI_ACTIVE_VSYNC
- REG_HDMI_AUDIO_CFG
- REG_HDMI_AUDIO_INFO0
- REG_HDMI_AUDIO_INFO1
- REG_HDMI_AUDIO_PKT_CTRL1
- REG_HDMI_AUDIO_PKT_CTRL2
- REG_HDMI_AUD_INT
- REG_HDMI_AVI_INFO
- REG_HDMI_CEC_ADDR
- REG_HDMI_CEC_CEC_RETRANSMIT
- REG_HDMI_CEC_COMPL_CTL
- REG_HDMI_CEC_CTRL
- REG_HDMI_CEC_INT
- REG_HDMI_CEC_RD_DATA
- REG_HDMI_CEC_RD_ERR_RESP_LO
- REG_HDMI_CEC_RD_FILTER
- REG_HDMI_CEC_RD_RANGE
- REG_HDMI_CEC_RD_START_RANGE
- REG_HDMI_CEC_RD_TOTAL_RANGE
- REG_HDMI_CEC_REFTIMER
- REG_HDMI_CEC_STATUS
- REG_HDMI_CEC_TIME
- REG_HDMI_CEC_WR_CHECK_CONFIG
- REG_HDMI_CEC_WR_DATA
- REG_HDMI_CEC_WR_RANGE
- REG_HDMI_CTRL
- REG_HDMI_DDC_ARBITRATION
- REG_HDMI_DDC_CTRL
- REG_HDMI_DDC_DATA
- REG_HDMI_DDC_HW_STATUS
- REG_HDMI_DDC_INT_CTRL
- REG_HDMI_DDC_REF
- REG_HDMI_DDC_SETUP
- REG_HDMI_DDC_SPEED
- REG_HDMI_DDC_SW_STATUS
- REG_HDMI_FLAGS
- REG_HDMI_FRAME_CTRL
- REG_HDMI_GC
- REG_HDMI_GENERIC0
- REG_HDMI_GENERIC0_HDR
- REG_HDMI_GENERIC1
- REG_HDMI_GENERIC1_HDR
- REG_HDMI_GEN_PKT_CTRL
- REG_HDMI_HDCP_CTRL
- REG_HDMI_HDCP_DDC_CTRL_0
- REG_HDMI_HDCP_DDC_CTRL_1
- REG_HDMI_HDCP_DDC_STATUS
- REG_HDMI_HDCP_DEBUG_CTRL
- REG_HDMI_HDCP_ENTROPY_CTRL0
- REG_HDMI_HDCP_ENTROPY_CTRL1
- REG_HDMI_HDCP_INT_CTRL
- REG_HDMI_HDCP_LINK0_STATUS
- REG_HDMI_HDCP_RCVPORT_DATA0
- REG_HDMI_HDCP_RCVPORT_DATA1
- REG_HDMI_HDCP_RCVPORT_DATA10
- REG_HDMI_HDCP_RCVPORT_DATA11
- REG_HDMI_HDCP_RCVPORT_DATA12
- REG_HDMI_HDCP_RCVPORT_DATA2_0
- REG_HDMI_HDCP_RCVPORT_DATA2_1
- REG_HDMI_HDCP_RCVPORT_DATA3
- REG_HDMI_HDCP_RCVPORT_DATA4
- REG_HDMI_HDCP_RCVPORT_DATA5
- REG_HDMI_HDCP_RCVPORT_DATA6
- REG_HDMI_HDCP_RCVPORT_DATA7
- REG_HDMI_HDCP_RCVPORT_DATA8
- REG_HDMI_HDCP_RCVPORT_DATA9
- REG_HDMI_HDCP_RESET
- REG_HDMI_HDCP_SHA_CTRL
- REG_HDMI_HDCP_SHA_DATA
- REG_HDMI_HDCP_SHA_STATUS
- REG_HDMI_HDCP_SW_LOWER_AKSV
- REG_HDMI_HDCP_SW_UPPER_AKSV
- REG_HDMI_HPD_CTRL
- REG_HDMI_HPD_INT_CTRL
- REG_HDMI_HPD_INT_STATUS
- REG_HDMI_I2C_TRANSACTION
- REG_HDMI_I2C_TRANSACTION_REG
- REG_HDMI_INFOFRAME_CTRL0
- REG_HDMI_INFOFRAME_CTRL1
- REG_HDMI_INFO_RST
- REG_HDMI_PHY_CTRL
- REG_HDMI_PHY_QSERDES_COM_ATB_SEL1
- REG_HDMI_PHY_QSERDES_COM_ATB_SEL2
- REG_HDMI_PHY_QSERDES_COM_BG_CTRL
- REG_HDMI_PHY_QSERDES_COM_BG_TIMER
- REG_HDMI_PHY_QSERDES_COM_BG_TRIM
- REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN
- REG_HDMI_PHY_QSERDES_COM_BIAS_EN_CTRL_BY_PSM
- REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1
- REG_HDMI_PHY_QSERDES_COM_CLK_EP_DIV
- REG_HDMI_PHY_QSERDES_COM_CLK_SELECT
- REG_HDMI_PHY_QSERDES_COM_CML_SYSCLK_SEL
- REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG
- REG_HDMI_PHY_QSERDES_COM_CMN_MISC1
- REG_HDMI_PHY_QSERDES_COM_CMN_MISC2
- REG_HDMI_PHY_QSERDES_COM_CMN_RATE_OVERRIDE
- REG_HDMI_PHY_QSERDES_COM_CMN_RSVD0
- REG_HDMI_PHY_QSERDES_COM_CMN_RSVD1
- REG_HDMI_PHY_QSERDES_COM_CMN_RSVD2
- REG_HDMI_PHY_QSERDES_COM_CMN_RSVD3
- REG_HDMI_PHY_QSERDES_COM_CMN_RSVD4
- REG_HDMI_PHY_QSERDES_COM_CMN_RSVD5
- REG_HDMI_PHY_QSERDES_COM_CMN_STATUS
- REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV
- REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE1
- REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV_MODE2
- REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN
- REG_HDMI_PHY_QSERDES_COM_CORE_CLK_IN_SYNC_SEL
- REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0
- REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE1
- REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE2
- REG_HDMI_PHY_QSERDES_COM_C_READY_STATUS
- REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS0
- REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS1
- REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS2
- REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS3
- REG_HDMI_PHY_QSERDES_COM_DEBUG_BUS_SEL
- REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0
- REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE1
- REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE2
- REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0
- REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE1
- REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE2
- REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0
- REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE1
- REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE2
- REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0
- REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE1
- REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE2
- REG_HDMI_PHY_QSERDES_COM_EP_CLOCK_DETECT_CTRL
- REG_HDMI_PHY_QSERDES_COM_FREQ_UPDATE
- REG_HDMI_PHY_QSERDES_COM_HSCLK_SEL
- REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_BINCODE_STATUS
- REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_EN
- REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0
- REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE1
- REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE2
- REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0
- REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE1
- REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE2
- REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_INITVAL
- REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0
- REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE1
- REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE2
- REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0
- REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE1
- REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE2
- REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0
- REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE1
- REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE2
- REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_CFG
- REG_HDMI_PHY_QSERDES_COM_LOCK_CMP_EN
- REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_CTRL
- REG_HDMI_PHY_QSERDES_COM_PHASE_SEL_DC
- REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE1_STATUS
- REG_HDMI_PHY_QSERDES_COM_PLLCAL_CODE2_STATUS
- REG_HDMI_PHY_QSERDES_COM_PLL_ANALOG
- REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE0
- REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE1
- REG_HDMI_PHY_QSERDES_COM_PLL_CCTRL_MODE2
- REG_HDMI_PHY_QSERDES_COM_PLL_CNTRL
- REG_HDMI_PHY_QSERDES_COM_PLL_EN
- REG_HDMI_PHY_QSERDES_COM_PLL_IVCO
- REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE0
- REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE1
- REG_HDMI_PHY_QSERDES_COM_PLL_RCTRL_MODE2
- REG_HDMI_PHY_QSERDES_COM_POST_DIV
- REG_HDMI_PHY_QSERDES_COM_POST_DIV_MUX
- REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM
- REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL
- REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL2
- REG_HDMI_PHY_QSERDES_COM_RESET_SM_STATUS
- REG_HDMI_PHY_QSERDES_COM_RESTRIM_CODE_STATUS
- REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL
- REG_HDMI_PHY_QSERDES_COM_RESTRIM_CTRL2
- REG_HDMI_PHY_QSERDES_COM_RES_TRIM_CONTROL2
- REG_HDMI_PHY_QSERDES_COM_SAR
- REG_HDMI_PHY_QSERDES_COM_SAR_CLK
- REG_HDMI_PHY_QSERDES_COM_SAR_CODE_OUT_STATUS
- REG_HDMI_PHY_QSERDES_COM_SAR_CODE_READY_STATUS
- REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER1
- REG_HDMI_PHY_QSERDES_COM_SSC_ADJ_PER2
- REG_HDMI_PHY_QSERDES_COM_SSC_EN_CENTER
- REG_HDMI_PHY_QSERDES_COM_SSC_PER1
- REG_HDMI_PHY_QSERDES_COM_SSC_PER2
- REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1
- REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2
- REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL
- REG_HDMI_PHY_QSERDES_COM_SW_RESET
- REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE
- REG_HDMI_PHY_QSERDES_COM_SYSCLK_DET_COMP_STATUS
- REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL
- REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL
- REG_HDMI_PHY_QSERDES_COM_VCOCAL_DEADMAN_CTRL
- REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE0
- REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE1
- REG_HDMI_PHY_QSERDES_COM_VCO_TUNE1_MODE2
- REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE0
- REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE1
- REG_HDMI_PHY_QSERDES_COM_VCO_TUNE2_MODE2
- REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL
- REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL1
- REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_INITVAL2
- REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP
- REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL1
- REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAXVAL2
- REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL1
- REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MINVAL2
- REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER1
- REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_TIMER2
- REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL1
- REG_HDMI_PHY_QSERDES_TX_LX_ATB_SEL2
- REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT1
- REG_HDMI_PHY_QSERDES_TX_LX_BIST_ERROR_COUNT2
- REG_HDMI_PHY_QSERDES_TX_LX_BIST_INVERT
- REG_HDMI_PHY_QSERDES_TX_LX_BIST_MODE_LANENO
- REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN1
- REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN2
- REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN3
- REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN4
- REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN5
- REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN6
- REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN7
- REG_HDMI_PHY_QSERDES_TX_LX_BIST_PATTERN8
- REG_HDMI_PHY_QSERDES_TX_LX_BIST_STATUS
- REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE
- REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_ONE
- REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_THREE
- REG_HDMI_PHY_QSERDES_TX_LX_CMN_CONTROL_TWO
- REG_HDMI_PHY_QSERDES_TX_LX_DEBUG_BUS_SEL
- REG_HDMI_PHY_QSERDES_TX_LX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN
- REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES
- REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE
- REG_HDMI_PHY_QSERDES_TX_LX_IDAC_CAL_LANE_MODE_CONFIGURATION
- REG_HDMI_PHY_QSERDES_TX_LX_INTERFACE_SELECT
- REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE
- REG_HDMI_PHY_QSERDES_TX_LX_LPB_EN
- REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN
- REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH1
- REG_HDMI_PHY_QSERDES_TX_LX_PERL_LENGTH2
- REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED1
- REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED2
- REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED3
- REG_HDMI_PHY_QSERDES_TX_LX_PRBS_SEED4
- REG_HDMI_PHY_QSERDES_TX_LX_PRE_STALL_LDO_BOOST_EN
- REG_HDMI_PHY_QSERDES_TX_LX_PWM_CTRL
- REG_HDMI_PHY_QSERDES_TX_LX_PWM_ENCODED_OR_DATA
- REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND0_1
- REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_1_DIVIDER_BAND2
- REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND0_1
- REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_2_DIVIDER_BAND2
- REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND0_1
- REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_3_DIVIDER_BAND2
- REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND0_1
- REG_HDMI_PHY_QSERDES_TX_LX_PWM_GEAR_4_DIVIDER_BAND2
- REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL
- REG_HDMI_PHY_QSERDES_TX_LX_RCV_DETECT_LVL_2
- REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN
- REG_HDMI_PHY_QSERDES_TX_LX_RESET_GEN_MUXES
- REG_HDMI_PHY_QSERDES_TX_LX_RESET_TSYNC_EN
- REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET
- REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_RX
- REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_TX
- REG_HDMI_PHY_QSERDES_TX_LX_SERDES_BYP_EN_OUT
- REG_HDMI_PHY_QSERDES_TX_LX_SLEW_CNTL
- REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN
- REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV
- REG_HDMI_PHY_QSERDES_TX_LX_TX_ALOG_INTF_OBSV_CNTL
- REG_HDMI_PHY_QSERDES_TX_LX_TX_BAND
- REG_HDMI_PHY_QSERDES_TX_LX_TX_BOOST_LVL_UP_DN
- REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL
- REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET
- REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL
- REG_HDMI_PHY_QSERDES_TX_LX_TX_IDLE_LVL_LARGE_AMP
- REG_HDMI_PHY_QSERDES_TX_LX_TX_INTERFACE_MODE
- REG_HDMI_PHY_QSERDES_TX_LX_TX_POL_INV
- REG_HDMI_PHY_QSERDES_TX_LX_TX_POST2_EMPH
- REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1
- REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2
- REG_HDMI_SOFT_RST
- REG_HDMI_TOTAL
- REG_HDMI_USEC_REFTIMER
- REG_HDMI_VBI_PKT_CTRL
- REG_HDMI_VENSPEC_INFO0
- REG_HDMI_VENSPEC_INFO1
- REG_HDMI_VENSPEC_INFO2
- REG_HDMI_VENSPEC_INFO3
- REG_HDMI_VENSPEC_INFO4
- REG_HDMI_VENSPEC_INFO5
- REG_HDMI_VENSPEC_INFO6
- REG_HDMI_VERSION
- REG_HDMI_VSYNC_ACTIVE_F2
- REG_HDMI_VSYNC_TOTAL_F2
- REG_HDX
- REG_HEAD
- REG_HGQ_INFO
- REG_HGQ_INFORMATION
- REG_HGQ_INFORMATION_8723B
- REG_HI0Q_TXBD_IDX
- REG_HI0Q_TXBD_NUM
- REG_HI1Q_TXBD_IDX
- REG_HI1Q_TXBD_NUM
- REG_HI2Q_TXBD_IDX
- REG_HI2Q_TXBD_NUM
- REG_HI3Q_TXBD_IDX
- REG_HI3Q_TXBD_NUM
- REG_HI4Q_TXBD_IDX
- REG_HI4Q_TXBD_NUM
- REG_HI5Q_TXBD_IDX
- REG_HI5Q_TXBD_NUM
- REG_HI6Q_TXBD_IDX
- REG_HI6Q_TXBD_NUM
- REG_HI7Q_TXBD_IDX
- REG_HI7Q_TXBD_NUM
- REG_HIDDEN_GUEST
- REG_HIDDEN_USER
- REG_HID_CFG
- REG_HIGH_LOW_WM
- REG_HIGH_PRIORITY_TXRX
- REG_HIMR
- REG_HIMR0
- REG_HIMR0_8723B
- REG_HIMR1
- REG_HIMR1_8723B
- REG_HIMRE
- REG_HIMRE_88E
- REG_HIMR_88E
- REG_HISR
- REG_HISR0
- REG_HISR0_8723B
- REG_HISR1
- REG_HISR1_8723B
- REG_HISRE
- REG_HISRE_88E
- REG_HISR_88E
- REG_HMBOX_0
- REG_HMBOX_1
- REG_HMBOX_2
- REG_HMBOX_3
- REG_HMBOX_EXT0_8723B
- REG_HMBOX_EXT1_8723B
- REG_HMBOX_EXT2_8723B
- REG_HMBOX_EXT3_8723B
- REG_HMBOX_EXT_0
- REG_HMBOX_EXT_1
- REG_HMBOX_EXT_2
- REG_HMBOX_EXT_3
- REG_HMEBOX0
- REG_HMEBOX0_EX
- REG_HMEBOX1
- REG_HMEBOX1_EX
- REG_HMEBOX2
- REG_HMEBOX2_EX
- REG_HMEBOX3
- REG_HMEBOX3_EX
- REG_HMEBOX_0
- REG_HMEBOX_0_8723B
- REG_HMEBOX_1
- REG_HMEBOX_1_8723B
- REG_HMEBOX_2
- REG_HMEBOX_2_8723B
- REG_HMEBOX_3
- REG_HMEBOX_3_8723B
- REG_HMEBOX_DBG_0_8723B
- REG_HMEBOX_DBG_1_8723B
- REG_HMEBOX_DBG_2_8723B
- REG_HMEBOX_DBG_3_8723B
- REG_HMEBOX_E0
- REG_HMEBOX_E1
- REG_HMEBOX_E2
- REG_HMEBOX_E3
- REG_HMEBOX_EXT0_8723B
- REG_HMEBOX_EXT1_8723B
- REG_HMEBOX_EXT2_8723B
- REG_HMEBOX_EXT3_8723B
- REG_HMEBOX_EXT_0
- REG_HMEBOX_EXT_1
- REG_HMEBOX_EXT_2
- REG_HMEBOX_EXT_3
- REG_HMETFR
- REG_HMETFR_8723B
- REG_HMTFR
- REG_HMTP_CTRL
- REG_HOP_COUNT
- REG_HORIZONTAL_SHAKE_INCREMENT
- REG_HOST_RXF0_MB0_LO
- REG_HOST_RXF0_MB1_LO
- REG_HOST_RXF0_PAGE0_LO
- REG_HOST_RXF0_PAGE0_VLD
- REG_HOST_RXF0_PAGE1_LO
- REG_HOST_RXF0_PAGE1_VLD
- REG_HOST_RXF0_PAGEOFF
- REG_HOST_RXF1_MB0_LO
- REG_HOST_RXF1_MB1_LO
- REG_HOST_RXF1_PAGE0_LO
- REG_HOST_RXF1_PAGE0_VLD
- REG_HOST_RXF1_PAGE1_LO
- REG_HOST_RXF1_PAGE1_VLD
- REG_HOST_RXF1_PAGEOFF
- REG_HOST_RXF2_MB0_LO
- REG_HOST_RXF2_MB1_LO
- REG_HOST_RXF2_PAGE0_LO
- REG_HOST_RXF2_PAGE0_VLD
- REG_HOST_RXF2_PAGE1_LO
- REG_HOST_RXF2_PAGE1_VLD
- REG_HOST_RXF2_PAGEOFF
- REG_HOST_RXF3_MB0_LO
- REG_HOST_RXF3_MB1_LO
- REG_HOST_RXF3_PAGE0_LO
- REG_HOST_RXF3_PAGE0_VLD
- REG_HOST_RXF3_PAGE1_LO
- REG_HOST_RXF3_PAGE1_VLD
- REG_HOST_RXF3_PAGEOFF
- REG_HOST_RXFPAGE_SIZE
- REG_HOST_SMB_ADDR_LO
- REG_HOST_SUSP_CNT
- REG_HOST_TX_CMB_LO
- REG_HOURS
- REG_HOURS_REG
- REG_HOUTSIZE
- REG_HPD_AUTO_CTRL
- REG_HPD_CTRL
- REG_HPD_DURATION
- REG_HPD_MAN_CTRL
- REG_HPD_POWER
- REG_HPON_FSM
- REG_HPON_FSM_8723B
- REG_HP_CFG
- REG_HP_DATA_RAM_DATA
- REG_HP_DATA_RAM_FDB_ADDR
- REG_HP_FLOW_DB0
- REG_HP_FLOW_DBN
- REG_HP_INSTR_RAM_ADDR
- REG_HP_INSTR_RAM_DATA_HI
- REG_HP_INSTR_RAM_DATA_LOW
- REG_HP_INSTR_RAM_DATA_MID
- REG_HP_RAM_BIST
- REG_HP_STATE_MACHINE
- REG_HP_STATUS0
- REG_HP_STATUS1
- REG_HP_STATUS2
- REG_HQ0_DESA
- REG_HQ1_DESA
- REG_HQ2_DESA
- REG_HQ3_DESA
- REG_HQ4_DESA
- REG_HQ5_DESA
- REG_HQ6_DESA
- REG_HQ7_DESA
- REG_HQ_DESA
- REG_HQ_DESA_8723B
- REG_HREF
- REG_HREF_E
- REG_HREF_S
- REG_HRXCTRL3
- REG_HRXINTH
- REG_HRXINTL
- REG_HSIMR
- REG_HSIMR_8723B
- REG_HSISR
- REG_HSISR_8723B
- REG_HSPI_XA_READBACK
- REG_HSPI_XB_READBACK
- REG_HSR_ALU_AGE_PERIOD__4
- REG_HSR_ALU_CTRL_0__1
- REG_HSR_ALU_CTRL_1__1
- REG_HSR_ALU_CTRL_2__2
- REG_HSR_ALU_CTRL__4
- REG_HSR_ALU_ENTRY_0__2
- REG_HSR_ALU_ENTRY_1__2
- REG_HSR_ALU_ENTRY_3__2
- REG_HSR_ALU_INDEX_0
- REG_HSR_ALU_INDEX_1
- REG_HSR_ALU_INDEX_2
- REG_HSR_ALU_INDEX_3
- REG_HSR_ALU_INT_MASK__1
- REG_HSR_ALU_INT_STATUS__1
- REG_HSR_ALU_VAL_A
- REG_HSR_ALU_VAL_B
- REG_HSR_ALU_VAL_C
- REG_HSR_ALU_VAL_D
- REG_HSR_ALU_VAL_E
- REG_HSR_ALU_VAL_F
- REG_HSR_ALU_VAL_G
- REG_HSR_PORT_MAP__4
- REG_HSTART
- REG_HSTOP
- REG_HSTRT
- REG_HSYEN
- REG_HSYMTMRH
- REG_HSYMTMRL
- REG_HSYNC_START_PIXEL_LSB
- REG_HSYNC_START_PIXEL_MSB
- REG_HSYNC_STOP_PIXEL_LSB
- REG_HSYNC_STOP_PIXEL_MSB
- REG_HSYNE
- REG_HSYNS
- REG_HSYST
- REG_HS_DET
- REG_HS_E
- REG_HS_HREF
- REG_HS_NAK_RATE
- REG_HS_PIX_START_LSB
- REG_HS_PIX_START_MSB
- REG_HS_PIX_STOP_LSB
- REG_HS_PIX_STOP_MSB
- REG_HS_S
- REG_HS_WIDTH
- REG_HTSTFWT
- REG_HTXCTRL
- REG_HTXINTH
- REG_HTXINTL
- REG_HT_LINK
- REG_HT_SINGLE_AMPDU
- REG_HT_SINGLE_AMPDU_8723B
- REG_HUE
- REG_HV
- REG_HVF_CNTRL_0
- REG_HVF_CNTRL_1
- REG_HVSIZEOFF
- REG_HWCFG
- REG_HWREV
- REG_HWREV_2
- REG_HWSEQ_CTRL
- REG_HWSEQ_CTRL_8723B
- REG_HW_TPI_ADDR
- REG_HW_TRAP1
- REG_H_PER
- REG_H_RESL
- REG_I2C_GATE
- REG_I2C_MASTER
- REG_I2C_R
- REG_I2C_SEQ_STATUS
- REG_I2C_STATUS
- REG_I2C_W
- REG_I2S_FORMAT
- REG_IBE
- REG_IBRD
- REG_ICR
- REG_ICTL
- REG_ICTL_MASK
- REG_ICTL_MASK_ALL
- REG_ICTL_MASK_DEV_STOP_REQ
- REG_ICTL_MASK_INFO_UPDATE
- REG_ICTL_MASK_RX_DATA
- REG_ICTL_MASK_TXRX_STOP_DONE
- REG_ICTL_MASK_TXRX_STOP_REQ
- REG_ID
- REG_ID2
- REG_IDCODE_15_8
- REG_IDCODE_16_23
- REG_IDCODE_31_24
- REG_IDCODE_7_0
- REG_IDLECONFIG
- REG_IDLE_STAT
- REG_IDLE_STATUS
- REG_IDT_TABLE
- REG_IDT_TABLE0
- REG_IDT_TABLE1
- REG_IDT_TABLE2
- REG_IDT_TABLE3
- REG_IDT_TABLE4
- REG_IDT_TABLE5
- REG_IDT_TABLE6
- REG_IDT_TABLE7
- REG_ID_LSB
- REG_ID_MSB
- REG_IE
- REG_IEC_OFFSET
- REG_IEEE_ADDR_0
- REG_IEEE_ADDR_1
- REG_IEEE_ADDR_2
- REG_IEEE_ADDR_3
- REG_IEEE_ADDR_4
- REG_IEEE_ADDR_5
- REG_IEEE_ADDR_6
- REG_IEEE_ADDR_7
- REG_IEN
- REG_IER
- REG_IEV
- REG_IF
- REG_IF1_HB0
- REG_IF2_HB0
- REG_IF3_HB0
- REG_IF4_HB0
- REG_IF5_HB0
- REG_IFACE_MODE
- REG_IFC
- REG_IFC__MASK
- REG_IFLS
- REG_IFR_RAMP_DOWN_DONE_OFFSET
- REG_IFR_RAMP_UP_DONE_OFFSET
- REG_IFS
- REG_IFS_OFFSET
- REG_IF_ACK
- REG_IF_ADDR
- REG_IF_ARBLOST
- REG_IF_BITO
- REG_IF_BUSERR
- REG_IF_BUSHOLD
- REG_IF_CLTO
- REG_IF_FREQ
- REG_IF_FREQ_SHIFT
- REG_IF_MSTOP
- REG_IF_NACK
- REG_IF_RSTART
- REG_IF_RXDATAV
- REG_IF_RXUF
- REG_IF_SSTOP
- REG_IF_START
- REG_IF_TXBL
- REG_IF_TXC
- REG_IF_TXOF
- REG_IGNORE_ONE
- REG_IGNORE_RANGE
- REG_IGN_GNTBT4
- REG_IGN_GNT_BT1
- REG_IIRF_CFG
- REG_ILL_ACC_ADDR
- REG_ILL_ACC_TYPE
- REG_IMAC
- REG_IMASK_CLEAR
- REG_IMASK_SET
- REG_IMGOFFSET
- REG_IMGPITCH
- REG_IMGSIZE
- REG_IMPULSIVE_NOISE_REM
- REG_IMR
- REG_IMSC
- REG_IN
- REG_INDAD0
- REG_INDAD1
- REG_INDAD2
- REG_INDAD3
- REG_INDAD4
- REG_INDAD5
- REG_INDEXED_THRESHOLD
- REG_INDI_CFG
- REG_INDI_CTRL
- REG_IND_AB
- REG_IND_AP
- REG_IND_CTRL_0
- REG_IND_CTRL_1
- REG_IND_DATA_0
- REG_IND_DATA_1
- REG_IND_DATA_2
- REG_IND_DATA_3
- REG_IND_DATA_4
- REG_IND_DATA_5
- REG_IND_DATA_6
- REG_IND_DATA_7
- REG_IND_DATA_8
- REG_IND_DATA_CHECK
- REG_IND_DATA_HI
- REG_IND_DATA_LO
- REG_IND_DATA_PME_EEE_ACL
- REG_IND_MIB_CHECK
- REG_INFO_CTRL
- REG_INFO_EXCEED
- REG_INF_BURST
- REG_ING_CONTROL
- REG_ING_FFILT_BE_EN
- REG_ING_FFILT_ETYPE
- REG_ING_FFILT_MASK0
- REG_ING_FFILT_MASK1
- REG_ING_FFILT_MASK2
- REG_ING_FFILT_UM_EN
- REG_ING_FFILT_VAL0
- REG_ING_FFILT_VAL1
- REG_INIDATA_RATE_SEL
- REG_INIRTS_RATE_SEL
- REG_INIT
- REG_INIT_DONE
- REG_INIT_TSFTR
- REG_INMAIL_CMD
- REG_INMAIL_CMD_MASK
- REG_INMAIL_DATA
- REG_INMAIL_ERROR
- REG_INMAIL_OP_REQUEST
- REG_INPUT_READOUT00
- REG_INPUT_READOUT01
- REG_INPUT_READOUT02
- REG_INPUT_SEL
- REG_INST
- REG_INTCON
- REG_INTCOND
- REG_INTCTRL
- REG_INTEN
- REG_INTEN_RX
- REG_INTEN_TX
- REG_INTERFACE_MIPI
- REG_INTERRUPT
- REG_INTERRUPT_ACK
- REG_INTERRUPT_ACTIVE
- REG_INTERRUPT_CLEAR0
- REG_INTERRUPT_CLEAR1
- REG_INTERRUPT_ENABLE
- REG_INTERRUPT_MASK
- REG_INTERRUPT_MASK0
- REG_INTERRUPT_MASK1
- REG_INTERRUPT_NO_CLEAR
- REG_INTERRUPT_RAW_STATUS0
- REG_INTERRUPT_RAW_STATUS1
- REG_INTERRUPT_STATUS
- REG_INTERRUPT_STATUS0
- REG_INTERRUPT_STATUS1
- REG_INTERRUPT_TRIG
- REG_INTR
- REG_INTR1
- REG_INTR1_MASK
- REG_INTR2
- REG_INTR2_MASK
- REG_INTR3
- REG_INTR3_MASK
- REG_INTR5
- REG_INTR5_MASK
- REG_INTR7
- REG_INTR7_MASK
- REG_INTR8
- REG_INTR8_MASK
- REG_INTR9
- REG_INTR9_MASK
- REG_INTRD
- REG_INTR_MASK
- REG_INTR_STATE
- REG_INTR_STATUS
- REG_INTR_STATUS_ALIAS
- REG_INTSTAT
- REG_INTSTSC
- REG_INTSTSP
- REG_INTSTS_RX
- REG_INTSTS_TX
- REG_INT_AF
- REG_INT_ALL
- REG_INT_BRF
- REG_INT_BTF
- REG_INT_CAPTURE
- REG_INT_CLEAR
- REG_INT_CTLR
- REG_INT_CTRL
- REG_INT_EN
- REG_INT_ENABLE
- REG_INT_FD
- REG_INT_FLAGS_0
- REG_INT_FLAGS_1
- REG_INT_FLAGS_2
- REG_INT_FLG_CLR_AFE
- REG_INT_FLG_CLR_AUDIO
- REG_INT_FLG_CLR_DDC
- REG_INT_FLG_CLR_HDCP
- REG_INT_FLG_CLR_INFO
- REG_INT_FLG_CLR_MODE
- REG_INT_FLG_CLR_RATE
- REG_INT_FLG_CLR_SUS
- REG_INT_FLG_CLR_TOP
- REG_INT_FRAMESYNC
- REG_INT_LENS_INIT
- REG_INT_MASK
- REG_INT_MASK_AFE
- REG_INT_MASK_AUDIO
- REG_INT_MASK_DDC
- REG_INT_MASK_HDCP
- REG_INT_MASK_INFO
- REG_INT_MASK_MODE
- REG_INT_MASK_RATE
- REG_INT_MASK_SUS
- REG_INT_MASK_TOP
- REG_INT_MBRF
- REG_INT_MBTF
- REG_INT_MIG
- REG_INT_MIG_8723B
- REG_INT_MODE
- REG_INT_MSK_LINE_A
- REG_INT_MSK_LINE_B
- REG_INT_MSK_LINE_C
- REG_INT_MSK_STS_A
- REG_INT_MSK_STS_B
- REG_INT_MSK_STS_C
- REG_INT_NAKRCV
- REG_INT_RETRIG_TIMER
- REG_INT_SOUND
- REG_INT_START
- REG_INT_STAT
- REG_INT_STATUS
- REG_INT_STOP
- REG_INT_STS_A
- REG_INT_STS_B
- REG_INT_STS_C
- REG_INT_THROTTLING_RATE
- REG_INT_TIME
- REG_INT_TIMER_CTRL
- REG_INT_VEC_ALLOC_BASE
- REG_INT_VEC_ALLOC_BITS
- REG_INT_VEC_ALLOC_MASK
- REG_INT_VEC_ALLOC_REGS
- REG_INT_ZOOM
- REG_INVALID
- REG_INVERSION
- REG_INVERSION_ON
- REG_IN_ARRAY
- REG_IN_CHUNK
- REG_IN_DMAC
- REG_IN_FLASH_MODE
- REG_IN_ONE
- REG_IN_RANGE
- REG_IOA
- REG_IOB
- REG_IOC
- REG_IOD
- REG_IOE
- REG_IO_BASE
- REG_IO_CONTROL
- REG_IO_CTRL
- REG_IO_CTRL00
- REG_IO_CTRL01
- REG_IO_CTRL02
- REG_IO_CTRL_1
- REG_IO_STATE
- REG_IP
- REG_IPC_OFFSET
- REG_IPD
- REG_IP_IDX
- REG_IP_REV_1
- REG_IP_REV_2
- REG_IQKFAILMSK
- REG_IQKSTAT
- REG_IQK_AGC_CONT
- REG_IQK_AGC_PTS
- REG_IQK_AGC_RSP
- REG_IQK_CTL1
- REG_IR0_ERDP_HIGH
- REG_IR0_ERDP_LOW
- REG_IR0_ERSTBA_HIGH
- REG_IR0_ERSTBA_LOW
- REG_IR0_ERSTSZ
- REG_IR0_IMAN
- REG_IR0_IMOD
- REG_IRC
- REG_IRQ1_EN0
- REG_IRQ1_EN1
- REG_IRQ1_SRC0
- REG_IRQ1_SRC1
- REG_IRQ2_EN0
- REG_IRQ2_EN1
- REG_IRQCLR
- REG_IRQENABLE
- REG_IRQFLAGS1
- REG_IRQFLAGS2
- REG_IRQMASK
- REG_IRQSTAT
- REG_IRQSTATRAW
- REG_IRQSTATUS
- REG_IRQWAKEUP
- REG_IRQ_MODRT_TIMER_INIT
- REG_IRQ_MODU_TIMER2_INIT
- REG_IRQ_MODU_TIMER_INIT
- REG_IR_BASICCAN_INITIAL
- REG_IR_PELICAN_INITIAL
- REG_IS
- REG_ISCR
- REG_ISOEN
- REG_ISO_100
- REG_ISO_200
- REG_ISO_400
- REG_ISO_50
- REG_ISO_800
- REG_ISO_AUTO
- REG_ISO_TX_CONFIG
- REG_ISP_CTRL00
- REG_ISP_CTRL01
- REG_ISP_CTRL02
- REG_ISP_CTRL_01
- REG_ISR
- REG_ISRC1_PACKET_TYPE
- REG_ISRC2_PACKET_TYPE
- REG_ISR_MASKED
- REG_IS_MASK
- REG_IS_MASK_EPID
- REG_IS_MASK_IS_ASSERT
- REG_IVFM_MODE
- REG_I_A
- REG_I_B
- REG_I_BLOCK_INTERNAL_PLL_CALC
- REG_I_CTRL
- REG_I_ERROR_INFO
- REG_I_INCLK_FREQ_H
- REG_I_INCLK_FREQ_L
- REG_I_INIT_PARAMS_UPDATED
- REG_I_MAX_OUTRATE_4KHZ
- REG_I_MIN_OUTRATE_4KHZ
- REG_I_OPCLK_4KHZ
- REG_I_USE_NMIPI_CLOCKS
- REG_I_USE_NPVI_CLOCKS
- REG_I_USE_REGS_API
- REG_JPEG
- REG_KEEPER
- REG_KEY1_DLT_H
- REG_KEY1_DLT_L
- REG_KEY1_REF_H
- REG_KEY1_REF_L
- REG_KEY1_THRESHOLD
- REG_KEY2_DLT_H
- REG_KEY2_DLT_L
- REG_KEY2_REF_H
- REG_KEY2_REF_L
- REG_KEY2_THRESHOLD
- REG_KEY3_DLT_H
- REG_KEY3_DLT_L
- REG_KEY3_REF_H
- REG_KEY3_REF_L
- REG_KEY3_THRESHOLD
- REG_KEY4_DLT_H
- REG_KEY4_DLT_L
- REG_KEY4_REF_H
- REG_KEY4_REF_L
- REG_KEY4_THRESHOLD
- REG_KEY_EVENT_A
- REG_KEY_EVENT_B
- REG_KEY_EVENT_C
- REG_KEY_EVENT_D
- REG_KEY_EVENT_E
- REG_KEY_EVENT_F
- REG_KEY_EVENT_G
- REG_KEY_EVENT_H
- REG_KEY_EVENT_I
- REG_KEY_EVENT_J
- REG_KEY_LCK_EC
- REG_KEY_STATE
- REG_KP_GPIO1
- REG_KP_GPIO2
- REG_KP_GPIO3
- REG_KP_LCK_TIMER
- REG_KP_LOCK
- REG_KRR
- REG_L
- REG_L1AEC
- REG_L1PKWT
- REG_L1WT
- REG_L1_PHYS
- REG_LATENCY_RD
- REG_LBDLY
- REG_LBEG
- REG_LBMODE
- REG_LCC
- REG_LCCFB
- REG_LCCFR
- REG_LCD_AC_DRIVEING_CONTROL
- REG_LCNT_NLIN
- REG_LCNT_PR
- REG_LCOUNT
- REG_LCRH_RX
- REG_LCRH_TX
- REG_LDO
- REG_LDO3
- REG_LDO4
- REG_LDOA15_CTRL
- REG_LDOHCI12_CTRL
- REG_LDOV12D_CTRL
- REG_LDO_EFUSE_CTRL
- REG_LDO_SET
- REG_LDO_SW_CTRL
- REG_LED
- REG_LED1_FLASH_BR
- REG_LED1_TORCH_BR
- REG_LEDCFG
- REG_LEDCFG0
- REG_LEDCFG0_8723B
- REG_LEDCFG1
- REG_LEDCFG1_8723B
- REG_LEDCFG2
- REG_LEDCFG2_8723B
- REG_LEDCFG3
- REG_LEDCFG3_8723B
- REG_LED_0_CNTRL
- REG_LED_1_CNTRL
- REG_LED_2_CNTRL
- REG_LED_CFG
- REG_LED_CNTRL
- REG_LED_CTRL
- REG_LED_TEST
- REG_LEN
- REG_LENC_BLUE_A1
- REG_LENC_BLUE_A2_B2
- REG_LENC_BLUE_B1
- REG_LENC_BLUE_X0_H
- REG_LENC_BLUE_X0_L
- REG_LENC_BLUE_Y0_H
- REG_LENC_BLUE_Y0_L
- REG_LENC_GREEN_A1
- REG_LENC_GREEN_A2_B2
- REG_LENC_GREEN_B1
- REG_LENC_GREEN_X0_H
- REG_LENC_GREEN_X0_L
- REG_LENC_GREEN_Y0_H
- REG_LENC_GREEN_Y0_L
- REG_LENC_RED_A1
- REG_LENC_RED_A2_B2
- REG_LENC_RED_B1
- REG_LENC_RED_X0_H
- REG_LENC_RED_X0_L
- REG_LENC_RED_Y0_H
- REG_LENC_RED_Y0_L
- REG_LEND
- REG_LEN_PER_LINE
- REG_LID_DETECT
- REG_LIFECTRL_CTRL
- REG_LIFECTRL_CTRL_8723B
- REG_LIFETIME_CTRL
- REG_LIFETIME_EN
- REG_LIGHT_AUTO
- REG_LIGHT_OFF
- REG_LIGHT_ON
- REG_LIMM
- REG_LINECTRL
- REG_LINECTRL2
- REG_LINES_PER_FRAME
- REG_LINE_DURATION
- REG_LINE_LENGTH_PCK_
- REG_LINKCTRL_OFFSET
- REG_LINKERR_OFFSET
- REG_LINK_CTRL
- REG_LIODNR
- REG_LISTEN1
- REG_LISTEN2
- REG_LISTEN3
- REG_LIVE_DONE
- REG_LIVE_NONE
- REG_LIVE_READ
- REG_LIVE_READ32
- REG_LIVE_READ64
- REG_LIVE_WRITTEN
- REG_LLT_INIT
- REG_LLT_INIT_8723B
- REG_LMAC
- REG_LM_DDC
- REG_LNA
- REG_LNK_CTRL_A
- REG_LNK_CTRL_B
- REG_LO1B1
- REG_LO1B2
- REG_LO1C1
- REG_LO1C2
- REG_LO2C1
- REG_LO2C2
- REG_LO2C3
- REG_LOAD_PTR
- REG_LOCAL_DATA
- REG_LOCAL_STATUS
- REG_LOCK
- REG_LOCK_STATUS
- REG_LOCK_TIMEOUT
- REG_LOGIN_VAR
- REG_LOOPBACK
- REG_LOTO
- REG_LOWBAT
- REG_LOW_PRIORITY_TXRX
- REG_LO_STATUS
- REG_LPI_CTRL
- REG_LPI_DECISN_TIMER
- REG_LPI_WAIT
- REG_LPLDO_CTRL
- REG_LPLDO_CTRL_8723B
- REG_LPNAV_CTRL
- REG_LR
- REG_LRB
- REG_LS_BYTE
- REG_LTSSM_ID_CTRL
- REG_LTSSM_TEST_MODE
- REG_LUMA_CONTROL1
- REG_LUMA_CONTROL2
- REG_LUMA_CONTROL3
- REG_M
- REG_M3_CTRL
- REG_M3_P0CTRL
- REG_M3_POSTM
- REG_M3_SCTRL
- REG_MAC0
- REG_MAC1
- REG_MACAR1
- REG_MACAR2
- REG_MACAR3
- REG_MACH
- REG_MACID
- REG_MACID1
- REG_MACID1_8723B
- REG_MACID_8723B
- REG_MACID_DROP_8732A
- REG_MACID_PKT_DROP0
- REG_MACID_PKT_DROP0_8723B
- REG_MACID_PKT_SLEEP_8723B
- REG_MACID_SLEEP
- REG_MACID_SLEEP_1_8732B
- REG_MACID_SLEEP_2_8732B
- REG_MACID_SLEEP_3_8732B
- REG_MACL
- REG_MAC_ADDR0
- REG_MAC_ADDRN
- REG_MAC_ADDR_FILTER0
- REG_MAC_ADDR_FILTER0_MASK
- REG_MAC_ADDR_FILTER1
- REG_MAC_ADDR_FILTER2
- REG_MAC_ADDR_FILTER2_1_MASK
- REG_MAC_ALIGN_ERR
- REG_MAC_ATTEMPTS_PEAK
- REG_MAC_ATTEMPT_LIMIT
- REG_MAC_COLL_EXCESS
- REG_MAC_COLL_FIRST
- REG_MAC_COLL_LATE
- REG_MAC_COLL_NORMAL
- REG_MAC_CR
- REG_MAC_CR_8723B
- REG_MAC_CTRL
- REG_MAC_CTRL_CFG
- REG_MAC_CTRL_MASK
- REG_MAC_CTRL_STATUS
- REG_MAC_CTRL_TYPE
- REG_MAC_FCS_ERR
- REG_MAC_FRAMESIZE_MAX
- REG_MAC_FRAMESIZE_MIN
- REG_MAC_HALF_DUPLX_CTRL
- REG_MAC_HASH_TABLE0
- REG_MAC_HASH_TABLEN
- REG_MAC_HIGH_ADDR
- REG_MAC_IPG0
- REG_MAC_IPG1
- REG_MAC_IPG2
- REG_MAC_IPG_IFG
- REG_MAC_JAM_SIZE
- REG_MAC_LEN_ERR
- REG_MAC_LOW_ADDR
- REG_MAC_LS_ADDRESS
- REG_MAC_MS_ADDRESS
- REG_MAC_PA_SIZE
- REG_MAC_PHY_CTRL
- REG_MAC_PHY_CTRL_NORMAL
- REG_MAC_PINMUX_CFG
- REG_MAC_PINMUX_CFG_8723B
- REG_MAC_PLL_CTRL_EXT_8723B
- REG_MAC_RANDOM_SEED
- REG_MAC_RECV_FRAME
- REG_MAC_RX_CFG
- REG_MAC_RX_CODE_ERR
- REG_MAC_RX_MASK
- REG_MAC_RX_RESET
- REG_MAC_RX_STATUS
- REG_MAC_RX_STATUS_BIN
- REG_MAC_RX_STATUS_END
- REG_MAC_SEND_PAUSE
- REG_MAC_SLOT_TIME
- REG_MAC_SPEC_SIFS
- REG_MAC_SPEC_SIFS_8723B
- REG_MAC_STATE_MACHINE
- REG_MAC_STATUS
- REG_MAC_STA_ADDR
- REG_MAC_TIMER_DEFER
- REG_MAC_TX_CFG
- REG_MAC_TX_MASK
- REG_MAC_TX_RESET
- REG_MAC_TX_RUNNING
- REG_MAC_TX_STATUS
- REG_MAC_TX_STATUS_BIN
- REG_MAC_TX_STATUS_END
- REG_MAC_TX_STICKY
- REG_MAC_XIF_CFG
- REG_MAGIC_NUMBER
- REG_MAILBOX
- REG_MAINCNT0
- REG_MAINCNT1
- REG_MAINCNT2
- REG_MAINCNT3
- REG_MAIN_CNTRL0
- REG_MANU
- REG_MANUAL_TIMER_INIT
- REG_MANUFACTURER
- REG_MANUFACTURER_DATA
- REG_MANV
- REG_MAN_HDMI_SET
- REG_MAN_SUS_HDMI_SEL
- REG_MAR
- REG_MARH
- REG_MARL
- REG_MARM
- REG_MAR_8723B
- REG_MASK
- REG_MASTER_CTRL
- REG_MAT_CONTRL
- REG_MAX
- REG_MAXFRMLEN
- REG_MAX_AGGR_NUM
- REG_MAX_AGGR_NUM_8723B
- REG_MAX_CHANNEL
- REG_MAX_CRDA_TIMEOUTS
- REG_MAX_EP
- REG_MAX_LEN
- REG_MAX_PWR
- REG_MAX_RXHIGH
- REG_MAX_RXLOW
- REG_MBATT
- REG_MBBAR_OFFSET
- REG_MBCR_OFFSET
- REG_MBD
- REG_MBIDCAMCFG
- REG_MBIDCAMCFG_8723B
- REG_MBID_NUM
- REG_MBID_NUM_8723B
- REG_MBIGEN_CLEAR_OFFSET
- REG_MBIGEN_TYPE_OFFSET
- REG_MBIGEN_VEC_OFFSET
- REG_MBIST_DONE
- REG_MBIST_FAIL
- REG_MBIST_START
- REG_MBMR_OFFSET
- REG_MBSSID_BCN_SPACE
- REG_MB_RFD01_CONS_IDX
- REG_MB_RFD0_PROD_IDX
- REG_MB_RXD_RD_IDX
- REG_MB_RXF1_RADDR
- REG_MB_RXF2_RADDR
- REG_MB_RXF3_RADDR
- REG_MB_TPD_PROD_IDX
- REG_MB_TXD_WR_IDX
- REG_MCAST_HASH_TABLE0
- REG_MCAST_HASH_TABLE1
- REG_MCCR_OFFSET
- REG_MCC_NORMAL
- REG_MCC_OFF
- REG_MCI_H
- REG_MCP
- REG_MCR
- REG_MCRER_OFFSET
- REG_MCTL
- REG_MCUFWDL
- REG_MCUFWDL_8723B
- REG_MCUFW_CTRL
- REG_MCUTSTCFG
- REG_MCUTST_1
- REG_MCUTST_1_8723B
- REG_MCUTST_WOWLAN
- REG_MCUTST_WOWLAN_8723B
- REG_MCU_FW_DL
- REG_MDIO
- REG_MDIO_CTL
- REG_MDIO_CTL_8723B
- REG_MDIO_CTRL
- REG_MDIO_DATA
- REG_MDIO_EXTN
- REG_MDIO_RDATA
- REG_MDIO_RDATA_8723B
- REG_MDIO_V1
- REG_MDIO_WDATA
- REG_MDIO_WDATA_8723B
- REG_MDP4_CS_CONTROLLER0
- REG_MDP4_CS_CONTROLLER1
- REG_MDP4_DISP_INTF_SEL
- REG_MDP4_DISP_STATUS
- REG_MDP4_DMA
- REG_MDP4_DMA_BLEND_TRANS_HIGH
- REG_MDP4_DMA_BLEND_TRANS_LOW
- REG_MDP4_DMA_CONFIG
- REG_MDP4_DMA_CSC
- REG_MDP4_DMA_CSC_MV
- REG_MDP4_DMA_CSC_MV_VAL
- REG_MDP4_DMA_CSC_POST_BV
- REG_MDP4_DMA_CSC_POST_BV_VAL
- REG_MDP4_DMA_CSC_POST_LV
- REG_MDP4_DMA_CSC_POST_LV_VAL
- REG_MDP4_DMA_CSC_PRE_BV
- REG_MDP4_DMA_CSC_PRE_BV_VAL
- REG_MDP4_DMA_CSC_PRE_LV
- REG_MDP4_DMA_CSC_PRE_LV_VAL
- REG_MDP4_DMA_CURSOR_BASE
- REG_MDP4_DMA_CURSOR_BLEND_CONFIG
- REG_MDP4_DMA_CURSOR_BLEND_PARAM
- REG_MDP4_DMA_CURSOR_POS
- REG_MDP4_DMA_CURSOR_SIZE
- REG_MDP4_DMA_DST_SIZE
- REG_MDP4_DMA_E_KICK
- REG_MDP4_DMA_E_QUANT
- REG_MDP4_DMA_FETCH_CONFIG
- REG_MDP4_DMA_P_KICK
- REG_MDP4_DMA_P_OP_MODE
- REG_MDP4_DMA_SRC_BASE
- REG_MDP4_DMA_SRC_SIZE
- REG_MDP4_DMA_SRC_STRIDE
- REG_MDP4_DMA_S_KICK
- REG_MDP4_DMA_S_OP_MODE
- REG_MDP4_DSI
- REG_MDP4_DSI_ACTIVE_HCTL
- REG_MDP4_DSI_ACTIVE_VEND
- REG_MDP4_DSI_ACTIVE_VSTART
- REG_MDP4_DSI_BORDER_CLR
- REG_MDP4_DSI_CTRL_POLARITY
- REG_MDP4_DSI_DISPLAY_HCTRL
- REG_MDP4_DSI_DISPLAY_VEND
- REG_MDP4_DSI_DISPLAY_VSTART
- REG_MDP4_DSI_ENABLE
- REG_MDP4_DSI_HSYNC_CTRL
- REG_MDP4_DSI_HSYNC_SKEW
- REG_MDP4_DSI_TEST_CNTL
- REG_MDP4_DSI_UNDERFLOW_CLR
- REG_MDP4_DSI_VSYNC_LEN
- REG_MDP4_DSI_VSYNC_PERIOD
- REG_MDP4_DTV
- REG_MDP4_DTV_ACTIVE_HCTL
- REG_MDP4_DTV_ACTIVE_VEND
- REG_MDP4_DTV_ACTIVE_VSTART
- REG_MDP4_DTV_BORDER_CLR
- REG_MDP4_DTV_CTRL_POLARITY
- REG_MDP4_DTV_DISPLAY_HCTRL
- REG_MDP4_DTV_DISPLAY_VEND
- REG_MDP4_DTV_DISPLAY_VSTART
- REG_MDP4_DTV_ENABLE
- REG_MDP4_DTV_HSYNC_CTRL
- REG_MDP4_DTV_HSYNC_SKEW
- REG_MDP4_DTV_TEST_CNTL
- REG_MDP4_DTV_UNDERFLOW_CLR
- REG_MDP4_DTV_VSYNC_LEN
- REG_MDP4_DTV_VSYNC_PERIOD
- REG_MDP4_EBI2_LCD0
- REG_MDP4_EBI2_LCD1
- REG_MDP4_INTR_CLEAR
- REG_MDP4_INTR_ENABLE
- REG_MDP4_INTR_STATUS
- REG_MDP4_LAYERMIXER2_IN_CFG
- REG_MDP4_LAYERMIXER_IN_CFG
- REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD
- REG_MDP4_LCDC
- REG_MDP4_LCDC_ACTIVE_HCTL
- REG_MDP4_LCDC_ACTIVE_VEND
- REG_MDP4_LCDC_ACTIVE_VSTART
- REG_MDP4_LCDC_BORDER_CLR
- REG_MDP4_LCDC_CTRL_POLARITY
- REG_MDP4_LCDC_DISPLAY_HCTRL
- REG_MDP4_LCDC_DISPLAY_VEND
- REG_MDP4_LCDC_DISPLAY_VSTART
- REG_MDP4_LCDC_ENABLE
- REG_MDP4_LCDC_HSYNC_CTRL
- REG_MDP4_LCDC_HSYNC_SKEW
- REG_MDP4_LCDC_LVDS_INTF_CTL
- REG_MDP4_LCDC_LVDS_MUX_CTL
- REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0
- REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4
- REG_MDP4_LCDC_LVDS_PHY_RESET
- REG_MDP4_LCDC_TEST_CNTL
- REG_MDP4_LCDC_UNDERFLOW_CLR
- REG_MDP4_LCDC_VSYNC_LEN
- REG_MDP4_LCDC_VSYNC_PERIOD
- REG_MDP4_LUTN
- REG_MDP4_LUTN_LUT
- REG_MDP4_LUTN_LUT_VAL
- REG_MDP4_LVDS_PHY_CFG0
- REG_MDP4_LVDS_PHY_CFG2
- REG_MDP4_LVDS_PHY_PLL_CTRL_0
- REG_MDP4_LVDS_PHY_PLL_CTRL_1
- REG_MDP4_LVDS_PHY_PLL_CTRL_2
- REG_MDP4_LVDS_PHY_PLL_CTRL_3
- REG_MDP4_LVDS_PHY_PLL_CTRL_5
- REG_MDP4_LVDS_PHY_PLL_CTRL_6
- REG_MDP4_LVDS_PHY_PLL_CTRL_7
- REG_MDP4_LVDS_PHY_PLL_CTRL_8
- REG_MDP4_LVDS_PHY_PLL_CTRL_9
- REG_MDP4_LVDS_PHY_PLL_LOCKED
- REG_MDP4_OVERLAY_FLUSH
- REG_MDP4_OVLP
- REG_MDP4_OVLP0_KICK
- REG_MDP4_OVLP1_KICK
- REG_MDP4_OVLP2_KICK
- REG_MDP4_OVLP_BASE
- REG_MDP4_OVLP_CFG
- REG_MDP4_OVLP_CSC
- REG_MDP4_OVLP_CSC_CONFIG
- REG_MDP4_OVLP_CSC_MV
- REG_MDP4_OVLP_CSC_MV_VAL
- REG_MDP4_OVLP_CSC_POST_BV
- REG_MDP4_OVLP_CSC_POST_BV_VAL
- REG_MDP4_OVLP_CSC_POST_LV
- REG_MDP4_OVLP_CSC_POST_LV_VAL
- REG_MDP4_OVLP_CSC_PRE_BV
- REG_MDP4_OVLP_CSC_PRE_BV_VAL
- REG_MDP4_OVLP_CSC_PRE_LV
- REG_MDP4_OVLP_CSC_PRE_LV_VAL
- REG_MDP4_OVLP_OPMODE
- REG_MDP4_OVLP_SIZE
- REG_MDP4_OVLP_STAGE
- REG_MDP4_OVLP_STAGE_BG_ALPHA
- REG_MDP4_OVLP_STAGE_CO3
- REG_MDP4_OVLP_STAGE_CO3_SEL
- REG_MDP4_OVLP_STAGE_FG_ALPHA
- REG_MDP4_OVLP_STAGE_OP
- REG_MDP4_OVLP_STAGE_TRANSP_HIGH0
- REG_MDP4_OVLP_STAGE_TRANSP_HIGH1
- REG_MDP4_OVLP_STAGE_TRANSP_LOW0
- REG_MDP4_OVLP_STAGE_TRANSP_LOW1
- REG_MDP4_OVLP_STRIDE
- REG_MDP4_OVLP_TRANSP_HIGH0
- REG_MDP4_OVLP_TRANSP_HIGH1
- REG_MDP4_OVLP_TRANSP_LOW0
- REG_MDP4_OVLP_TRANSP_LOW1
- REG_MDP4_PIPE
- REG_MDP4_PIPE_CSC
- REG_MDP4_PIPE_CSC_MV
- REG_MDP4_PIPE_CSC_MV_VAL
- REG_MDP4_PIPE_CSC_POST_BV
- REG_MDP4_PIPE_CSC_POST_BV_VAL
- REG_MDP4_PIPE_CSC_POST_LV
- REG_MDP4_PIPE_CSC_POST_LV_VAL
- REG_MDP4_PIPE_CSC_PRE_BV
- REG_MDP4_PIPE_CSC_PRE_BV_VAL
- REG_MDP4_PIPE_CSC_PRE_LV
- REG_MDP4_PIPE_CSC_PRE_LV_VAL
- REG_MDP4_PIPE_DST_SIZE
- REG_MDP4_PIPE_DST_XY
- REG_MDP4_PIPE_FETCH_CONFIG
- REG_MDP4_PIPE_OP_MODE
- REG_MDP4_PIPE_PHASEX_STEP
- REG_MDP4_PIPE_PHASEY_STEP
- REG_MDP4_PIPE_SOLID_COLOR
- REG_MDP4_PIPE_SRCP0_BASE
- REG_MDP4_PIPE_SRCP1_BASE
- REG_MDP4_PIPE_SRCP2_BASE
- REG_MDP4_PIPE_SRCP3_BASE
- REG_MDP4_PIPE_SRC_FORMAT
- REG_MDP4_PIPE_SRC_SIZE
- REG_MDP4_PIPE_SRC_STRIDE_A
- REG_MDP4_PIPE_SRC_STRIDE_B
- REG_MDP4_PIPE_SRC_UNPACK
- REG_MDP4_PIPE_SRC_XY
- REG_MDP4_PIPE_SSTILE_FRAME_SIZE
- REG_MDP4_PORTMAP_MODE
- REG_MDP4_READ_CNFG
- REG_MDP4_RESET_STATUS
- REG_MDP4_VERSION
- REG_MDP4_VG2_CONST_COLOR
- REG_MDP4_VG2_SRC_FORMAT
- REG_MDP5_AD
- REG_MDP5_AD_AL
- REG_MDP5_AD_AL_FILT
- REG_MDP5_AD_AL_MIN
- REG_MDP5_AD_AMP_LIM
- REG_MDP5_AD_BL
- REG_MDP5_AD_BL_MAX
- REG_MDP5_AD_BL_MINMAX
- REG_MDP5_AD_BL_OUT
- REG_MDP5_AD_BW_LVL
- REG_MDP5_AD_BYPASS
- REG_MDP5_AD_CALC_DONE
- REG_MDP5_AD_CALIB_AB
- REG_MDP5_AD_CALIB_CD
- REG_MDP5_AD_CFG_BUF
- REG_MDP5_AD_CON_CTRL_0
- REG_MDP5_AD_CON_CTRL_1
- REG_MDP5_AD_CTRL_0
- REG_MDP5_AD_CTRL_1
- REG_MDP5_AD_DITH
- REG_MDP5_AD_DITH_CTRL
- REG_MDP5_AD_FRAME_SIZE
- REG_MDP5_AD_LOGO_POS
- REG_MDP5_AD_LUT_AL
- REG_MDP5_AD_LUT_CC
- REG_MDP5_AD_LUT_FI
- REG_MDP5_AD_MODE_SEL
- REG_MDP5_AD_SLOPE
- REG_MDP5_AD_START_CALC
- REG_MDP5_AD_STR_LIM
- REG_MDP5_AD_STR_MAN
- REG_MDP5_AD_STR_OUT
- REG_MDP5_AD_TARG_STR
- REG_MDP5_AD_TFILT_CTRL
- REG_MDP5_AD_VAR
- REG_MDP5_CTL
- REG_MDP5_CTL_FLUSH
- REG_MDP5_CTL_LAYER
- REG_MDP5_CTL_LAYER_EXT
- REG_MDP5_CTL_LAYER_EXT_REG
- REG_MDP5_CTL_LAYER_REG
- REG_MDP5_CTL_OP
- REG_MDP5_CTL_PACK_3D
- REG_MDP5_CTL_START
- REG_MDP5_DISP_INTF_SEL
- REG_MDP5_DSPP
- REG_MDP5_DSPP_DITHER_DEPTH
- REG_MDP5_DSPP_GAMUT_BASE
- REG_MDP5_DSPP_GC_BASE
- REG_MDP5_DSPP_HIST_CTL_BASE
- REG_MDP5_DSPP_HIST_LUT_BASE
- REG_MDP5_DSPP_HIST_LUT_SWAP
- REG_MDP5_DSPP_OP_MODE
- REG_MDP5_DSPP_PA_BASE
- REG_MDP5_DSPP_PCC_BASE
- REG_MDP5_HIST_INTR_CLEAR
- REG_MDP5_HIST_INTR_EN
- REG_MDP5_HIST_INTR_STATUS
- REG_MDP5_HW_VERSION
- REG_MDP5_IGC
- REG_MDP5_IGC_LUT
- REG_MDP5_IGC_LUT_REG
- REG_MDP5_INTF
- REG_MDP5_INTF_ACTIVE_HCTL
- REG_MDP5_INTF_ACTIVE_VEND_F0
- REG_MDP5_INTF_ACTIVE_VEND_F1
- REG_MDP5_INTF_ACTIVE_VSTART_F0
- REG_MDP5_INTF_ACTIVE_VSTART_F1
- REG_MDP5_INTF_BORDER_COLOR
- REG_MDP5_INTF_CONFIG
- REG_MDP5_INTF_DEFLICKER_CONFIG
- REG_MDP5_INTF_DEFLICKER_STRNG_COEFF
- REG_MDP5_INTF_DEFLICKER_WEAK_COEFF
- REG_MDP5_INTF_DISPLAY_HCTL
- REG_MDP5_INTF_DISPLAY_VEND_F0
- REG_MDP5_INTF_DISPLAY_VEND_F1
- REG_MDP5_INTF_DISPLAY_VSTART_F0
- REG_MDP5_INTF_DISPLAY_VSTART_F1
- REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN
- REG_MDP5_INTF_FRAME_COUNT
- REG_MDP5_INTF_FRAME_LINE_COUNT_EN
- REG_MDP5_INTF_HSYNC_CTL
- REG_MDP5_INTF_HSYNC_SKEW
- REG_MDP5_INTF_LINE_COUNT
- REG_MDP5_INTF_PANEL_FORMAT
- REG_MDP5_INTF_POLARITY_CTL
- REG_MDP5_INTF_TEST_CTL
- REG_MDP5_INTF_TIMING_ENGINE_EN
- REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME
- REG_MDP5_INTF_TPG_COMPONENT_LIMITS
- REG_MDP5_INTF_TPG_ENABLE
- REG_MDP5_INTF_TPG_INITIAL_VALUE
- REG_MDP5_INTF_TPG_MAIN_CONTROL
- REG_MDP5_INTF_TPG_RECTANGLE
- REG_MDP5_INTF_TPG_RGB_MAPPING
- REG_MDP5_INTF_TPG_VIDEO_CONFIG
- REG_MDP5_INTF_TP_COLOR0
- REG_MDP5_INTF_TP_COLOR1
- REG_MDP5_INTF_UNDERFLOW_COLOR
- REG_MDP5_INTF_VSYNC_LEN_F0
- REG_MDP5_INTF_VSYNC_LEN_F1
- REG_MDP5_INTF_VSYNC_PERIOD_F0
- REG_MDP5_INTF_VSYNC_PERIOD_F1
- REG_MDP5_INTR_CLEAR
- REG_MDP5_INTR_EN
- REG_MDP5_INTR_STATUS
- REG_MDP5_LM
- REG_MDP5_LM_BLEND
- REG_MDP5_LM_BLEND_BG_ALPHA
- REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0
- REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1
- REG_MDP5_LM_BLEND_BG_TRANSP_LOW0
- REG_MDP5_LM_BLEND_BG_TRANSP_LOW1
- REG_MDP5_LM_BLEND_COLOR_OUT
- REG_MDP5_LM_BLEND_FG_ALPHA
- REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0
- REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1
- REG_MDP5_LM_BLEND_FG_TRANSP_LOW0
- REG_MDP5_LM_BLEND_FG_TRANSP_LOW1
- REG_MDP5_LM_BLEND_OP_MODE
- REG_MDP5_LM_BORDER_COLOR_0
- REG_MDP5_LM_BORDER_COLOR_1
- REG_MDP5_LM_CURSOR_BASE_ADDR
- REG_MDP5_LM_CURSOR_BLEND_CONFIG
- REG_MDP5_LM_CURSOR_BLEND_PARAM
- REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0
- REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1
- REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0
- REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1
- REG_MDP5_LM_CURSOR_FORMAT
- REG_MDP5_LM_CURSOR_IMG_SIZE
- REG_MDP5_LM_CURSOR_SIZE
- REG_MDP5_LM_CURSOR_START_XY
- REG_MDP5_LM_CURSOR_STRIDE
- REG_MDP5_LM_CURSOR_XY
- REG_MDP5_LM_GC_LUT_BASE
- REG_MDP5_LM_OUT_SIZE
- REG_MDP5_PIPE
- REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0
- REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1
- REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2
- REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3
- REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4
- REG_MDP5_PIPE_CSC_1_POST_BIAS
- REG_MDP5_PIPE_CSC_1_POST_BIAS_REG
- REG_MDP5_PIPE_CSC_1_POST_CLAMP
- REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG
- REG_MDP5_PIPE_CSC_1_PRE_BIAS
- REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG
- REG_MDP5_PIPE_CSC_1_PRE_CLAMP
- REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG
- REG_MDP5_PIPE_CURRENT_SRC0_ADDR
- REG_MDP5_PIPE_CURRENT_SRC1_ADDR
- REG_MDP5_PIPE_CURRENT_SRC2_ADDR
- REG_MDP5_PIPE_CURRENT_SRC3_ADDR
- REG_MDP5_PIPE_DECIMATION
- REG_MDP5_PIPE_FETCH_CONFIG
- REG_MDP5_PIPE_HIST_CTL_BASE
- REG_MDP5_PIPE_HIST_LUT_BASE
- REG_MDP5_PIPE_HIST_LUT_SWAP
- REG_MDP5_PIPE_OP_MODE
- REG_MDP5_PIPE_OUT_SIZE
- REG_MDP5_PIPE_OUT_XY
- REG_MDP5_PIPE_REQPRIO_FIFO_WM_0
- REG_MDP5_PIPE_REQPRIO_FIFO_WM_1
- REG_MDP5_PIPE_REQPRIO_FIFO_WM_2
- REG_MDP5_PIPE_SCALE_CONFIG
- REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X
- REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y
- REG_MDP5_PIPE_SCALE_INIT_PHASE_X
- REG_MDP5_PIPE_SCALE_INIT_PHASE_Y
- REG_MDP5_PIPE_SCALE_PHASE_STEP_X
- REG_MDP5_PIPE_SCALE_PHASE_STEP_Y
- REG_MDP5_PIPE_SRC0_ADDR
- REG_MDP5_PIPE_SRC1_ADDR
- REG_MDP5_PIPE_SRC2_ADDR
- REG_MDP5_PIPE_SRC3_ADDR
- REG_MDP5_PIPE_SRC_ADDR_SW_STATUS
- REG_MDP5_PIPE_SRC_CONSTANT_COLOR
- REG_MDP5_PIPE_SRC_FORMAT
- REG_MDP5_PIPE_SRC_IMG_SIZE
- REG_MDP5_PIPE_SRC_OP_MODE
- REG_MDP5_PIPE_SRC_SIZE
- REG_MDP5_PIPE_SRC_STRIDE_A
- REG_MDP5_PIPE_SRC_STRIDE_B
- REG_MDP5_PIPE_SRC_UNPACK
- REG_MDP5_PIPE_SRC_XY
- REG_MDP5_PIPE_STILE_FRAME_SIZE
- REG_MDP5_PIPE_SW_PIX_EXT
- REG_MDP5_PIPE_SW_PIX_EXT_LR
- REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS
- REG_MDP5_PIPE_SW_PIX_EXT_TB
- REG_MDP5_PIPE_VC1_RANGE
- REG_MDP5_PP
- REG_MDP5_PP_AUTOREFRESH_CONFIG
- REG_MDP5_PP_FBC_BUDGET_CTL
- REG_MDP5_PP_FBC_LOSSY_MODE
- REG_MDP5_PP_FBC_MODE
- REG_MDP5_PP_INT_COUNT_VAL
- REG_MDP5_PP_OUT_LINE_COUNT
- REG_MDP5_PP_PP_LINE_COUNT
- REG_MDP5_PP_RD_PTR_IRQ
- REG_MDP5_PP_START_POS
- REG_MDP5_PP_SYNC_CONFIG_HEIGHT
- REG_MDP5_PP_SYNC_CONFIG_VSYNC
- REG_MDP5_PP_SYNC_THRESH
- REG_MDP5_PP_SYNC_WRCOUNT
- REG_MDP5_PP_TEAR_CHECK_EN
- REG_MDP5_PP_VSYNC_INIT_VAL
- REG_MDP5_PP_WR_PTR_IRQ
- REG_MDP5_SMP_ALLOC_R
- REG_MDP5_SMP_ALLOC_R_REG
- REG_MDP5_SMP_ALLOC_W
- REG_MDP5_SMP_ALLOC_W_REG
- REG_MDP5_SPARE_0
- REG_MDP5_SPLIT_DPL_EN
- REG_MDP5_SPLIT_DPL_LOWER
- REG_MDP5_SPLIT_DPL_UPPER
- REG_MDP5_WB
- REG_MDP5_WB_ALPHA_X_VALUE
- REG_MDP5_WB_CSC_COMP_POSTBIAS
- REG_MDP5_WB_CSC_COMP_POSTBIAS_REG
- REG_MDP5_WB_CSC_COMP_POSTCLAMP
- REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG
- REG_MDP5_WB_CSC_COMP_PREBIAS
- REG_MDP5_WB_CSC_COMP_PREBIAS_REG
- REG_MDP5_WB_CSC_COMP_PRECLAMP
- REG_MDP5_WB_CSC_COMP_PRECLAMP_REG
- REG_MDP5_WB_CSC_MATRIX_COEFF_0
- REG_MDP5_WB_CSC_MATRIX_COEFF_1
- REG_MDP5_WB_CSC_MATRIX_COEFF_2
- REG_MDP5_WB_CSC_MATRIX_COEFF_3
- REG_MDP5_WB_CSC_MATRIX_COEFF_4
- REG_MDP5_WB_DITHER_MATRIX_ROW0
- REG_MDP5_WB_DITHER_MATRIX_ROW1
- REG_MDP5_WB_DITHER_MATRIX_ROW2
- REG_MDP5_WB_DITHER_MATRIX_ROW3
- REG_MDP5_WB_DST0_ADDR
- REG_MDP5_WB_DST1_ADDR
- REG_MDP5_WB_DST2_ADDR
- REG_MDP5_WB_DST3_ADDR
- REG_MDP5_WB_DST_DITHER_BITDEPTH
- REG_MDP5_WB_DST_FORMAT
- REG_MDP5_WB_DST_OP_MODE
- REG_MDP5_WB_DST_PACK_PATTERN
- REG_MDP5_WB_DST_WRITE_CONFIG
- REG_MDP5_WB_DST_YSTRIDE0
- REG_MDP5_WB_DST_YSTRIDE1
- REG_MDP5_WB_N16_INIT_PHASE_X_0_3
- REG_MDP5_WB_N16_INIT_PHASE_X_1_2
- REG_MDP5_WB_N16_INIT_PHASE_Y_0_3
- REG_MDP5_WB_N16_INIT_PHASE_Y_1_2
- REG_MDP5_WB_OUT_SIZE
- REG_MDP5_WB_ROTATION_DNSCALER
- REG_MDSS_HW_INTR_STATUS
- REG_MDSS_HW_VERSION
- REG_MDT_INT_0
- REG_MDT_INT_0_MASK
- REG_MDT_INT_1
- REG_MDT_INT_1_MASK
- REG_MDT_RCV_CTRL
- REG_MDT_RCV_READ_PORT
- REG_MDT_RCV_TIMEOUT
- REG_MDT_RFIFO_STAT
- REG_MDT_SM_STAT
- REG_MDT_XFIFO_STAT
- REG_MDT_XMIT_CTRL
- REG_MDT_XMIT_TIMEOUT
- REG_MDT_XMIT_WRITE_PORT
- REG_MD_SET
- REG_MD_STAT
- REG_MEAR_OFFSET
- REG_MEMPLLCTL0
- REG_MEMPLLCTL4
- REG_MEM_BASE
- REG_MEM_BIST
- REG_MEM_LIM
- REG_MESR_OFFSET
- REG_MFG_ID
- REG_MFINDEX
- REG_MGQ_BDNY
- REG_MGQ_DESA
- REG_MGQ_DESA_8723B
- REG_MGQ_INFO
- REG_MGQ_INFORMATION
- REG_MGQ_INFORMATION_8723B
- REG_MGQ_TXBD_IDX
- REG_MGQ_TXBD_NUM
- REG_MHL3_TX_ZONE_CTL
- REG_MHLTX_CTL6
- REG_MHL_CBUS_CTL0
- REG_MHL_CBUS_CTL1
- REG_MHL_COC_CTL0
- REG_MHL_COC_CTL1
- REG_MHL_COC_CTL3
- REG_MHL_COC_CTL4
- REG_MHL_COC_CTL5
- REG_MHL_DEVCAP_0
- REG_MHL_DOC_CTL0
- REG_MHL_DP_CTL0
- REG_MHL_DP_CTL1
- REG_MHL_DP_CTL2
- REG_MHL_DP_CTL3
- REG_MHL_DP_CTL4
- REG_MHL_DP_CTL5
- REG_MHL_DP_CTL6
- REG_MHL_DP_CTL7
- REG_MHL_DP_CTL8
- REG_MHL_EXTDEVCAP_0
- REG_MHL_EXTSTAT_0
- REG_MHL_INT_0
- REG_MHL_INT_0_MASK
- REG_MHL_INT_1_MASK
- REG_MHL_INT_2_MASK
- REG_MHL_INT_3_MASK
- REG_MHL_PLL_CTL0
- REG_MHL_PLL_CTL2
- REG_MHL_SCRPAD_0
- REG_MHL_STAT_0
- REG_MHL_TOP_CTL
- REG_MICFIL_CTRL1
- REG_MICFIL_CTRL2
- REG_MICFIL_DATACH0
- REG_MICFIL_DATACH1
- REG_MICFIL_DATACH2
- REG_MICFIL_DATACH3
- REG_MICFIL_DATACH4
- REG_MICFIL_DATACH5
- REG_MICFIL_DATACH6
- REG_MICFIL_DATACH7
- REG_MICFIL_DC_CTRL
- REG_MICFIL_FIFO_CTRL
- REG_MICFIL_FIFO_STAT
- REG_MICFIL_OUT_CTRL
- REG_MICFIL_OUT_STAT
- REG_MICFIL_STAT
- REG_MICFIL_VAD0_CTRL1
- REG_MICFIL_VAD0_CTRL2
- REG_MICFIL_VAD0_NCONFIG
- REG_MICFIL_VAD0_NDATA
- REG_MICFIL_VAD0_SCONFIG
- REG_MICFIL_VAD0_STAT
- REG_MICFIL_VAD0_ZCD
- REG_MIC_DET
- REG_MIDH
- REG_MIDL
- REG_MIF_BIT_BANG_CLOCK
- REG_MIF_BIT_BANG_DATA
- REG_MIF_BIT_BANG_OUTPUT_EN
- REG_MIF_CFG
- REG_MIF_FRAME
- REG_MIF_MASK
- REG_MIF_STATE_MACHINE
- REG_MIF_STATUS
- REG_MIICMD
- REG_MIICMD_READ
- REG_MIICMD_WRITE
- REG_MIIDATA
- REG_MIIM_CMD
- REG_MIIM_DATA
- REG_MIIM_PRESCALE
- REG_MIIM_STATUS
- REG_MIISTS
- REG_MIISTS_BUSY
- REG_MII_ADDR
- REG_MII_ADDR_READ
- REG_MII_ADDR_WRITE
- REG_MII_DATA0
- REG_MII_DATA1
- REG_MII_DATA2
- REG_MII_DATA3
- REG_MII_PAGE
- REG_MII_PAGE_ENABLE
- REG_MINUS_BIM_DATAPATH_TEST
- REG_MINUTES
- REG_MINUTES_REG
- REG_MIN_CHANNEL
- REG_MIRROR_FLIP_CONTROL
- REG_MIS
- REG_MISC
- REG_MISC2
- REG_MISC_10G
- REG_MISC_AB
- REG_MISC_CFG
- REG_MISC_CTRL
- REG_MISC_STAT
- REG_MMAC
- REG_MMCR_OFFSET
- REG_MMSS_CC_AHB
- REG_MMSS_CC_CLK
- REG_MMSS_CC_CLK_CC
- REG_MMSS_CC_CLK_MD
- REG_MMSS_CC_CLK_NS
- REG_MMSS_CC_DSI2_PIXEL_CC
- REG_MMSS_CC_DSI2_PIXEL_CC2
- REG_MMSS_CC_DSI2_PIXEL_NS
- REG_MMU0_FAULT_VA
- REG_MMU0_INT_ID
- REG_MMU0_INVLD_PA
- REG_MMU1_FAULT_VA
- REG_MMU1_INT_ID
- REG_MMU1_INVLD_PA
- REG_MMU_CFG
- REG_MMU_CPE_DONE
- REG_MMU_CTRL
- REG_MMU_CTRL_REG
- REG_MMU_DCM
- REG_MMU_DCM_DIS
- REG_MMU_FAULT_ST
- REG_MMU_FAULT_ST1
- REG_MMU_FAULT_VA
- REG_MMU_FLUSH
- REG_MMU_FLUSH_ENTRY
- REG_MMU_INT_CONTROL
- REG_MMU_INT_CONTROL0
- REG_MMU_INT_ID
- REG_MMU_INT_MAIN_CONTROL
- REG_MMU_INVALIDATE
- REG_MMU_INVLD_END_A
- REG_MMU_INVLD_PA
- REG_MMU_INVLD_START_A
- REG_MMU_INV_SEL
- REG_MMU_IVRP_PADDR
- REG_MMU_PT_BASE_ADDR
- REG_MMU_STANDARD_AXI_MODE
- REG_MMU_STATUS
- REG_MMU_VERSION
- REG_MMU_VLD_PA_RNG
- REG_MOD
- REG_MODE
- REG_MODEL_NAME
- REG_MODE_CFG
- REG_MODE_REC_CFG1
- REG_MODE_REC_CFG2
- REG_MODE_REC_STS
- REG_MODE_SELECT
- REG_MODULE_SW_V
- REG_MOD_PELICAN_INITIAL
- REG_MONITOR
- REG_MONTHS
- REG_MONTHS_REG
- REG_MPLS_BIT0
- REG_MPLS_BIT1
- REG_MPLS_BIT2
- REG_MPLS_BIT3
- REG_MPLS_BITMASK
- REG_MRC
- REG_MRCM
- REG_MRXADDR
- REG_MRXADDR_VALID
- REG_MRXCNT
- REG_MRXFIFO
- REG_MRXRADDR
- REG_MSCH
- REG_MSCR_OFFSET
- REG_MSC_1ST_TRANSMIT_DATA
- REG_MSC_2ND_TRANSMIT_DATA
- REG_MSC_CMD_OR_OFFSET
- REG_MSC_COMMAND_START
- REG_MSC_HEARTBEAT_CTRL
- REG_MSC_MR_ABORT_INT
- REG_MSC_MR_ABORT_INT_MASK
- REG_MSC_MR_MSC_MSG_RCVD_1ST_DATA
- REG_MSC_MR_MSC_MSG_RCVD_2ND_DATA
- REG_MSC_MT_ABORT_INT
- REG_MSC_MT_ABORT_INT_MASK
- REG_MSC_MT_RCVD_DATA0
- REG_MSC_MT_RCVD_DATA1
- REG_MSPR_OFFSET
- REG_MSR
- REG_MSRER_OFFSET
- REG_MSRSR_OFFSET
- REG_MSU_LENGTH
- REG_MSU_MINTCTL
- REG_MSU_MSC0BAR
- REG_MSU_MSC0CTL
- REG_MSU_MSC0MWP
- REG_MSU_MSC0NWSA
- REG_MSU_MSC0SIZE
- REG_MSU_MSC0STS
- REG_MSU_MSC1BAR
- REG_MSU_MSC1CTL
- REG_MSU_MSC1MWP
- REG_MSU_MSC1NWSA
- REG_MSU_MSC1SIZE
- REG_MSU_MSC1STS
- REG_MSU_MSUPARAMS
- REG_MSU_MSUSTS
- REG_MSU_OFFSET
- REG_MS_BYTE
- REG_MTU
- REG_MTX
- REG_MTXCNT
- REG_MTXFIFO
- REG_MTXS
- REG_MULCA_COUNTER
- REG_MULTI_BCNQ_EN
- REG_MULTI_BCNQ_OFFSET
- REG_MULTI_BCNQ_OFFSET_8723B
- REG_MULTI_FUNC_CTRL
- REG_MULTI_FUNC_CTRL_8723B
- REG_MUTE
- REG_MUTE_CTRL
- REG_MUTE_ST
- REG_MUX_AP
- REG_MUX_VP_VIP_OUT
- REG_MVFP
- REG_N
- REG_NAV_CTRL
- REG_NAV_PROT_LEN
- REG_NAV_PROT_LEN_8723B
- REG_NAV_UPPER
- REG_NAV_UPPER_8723B
- REG_NCTL0
- REG_NDIV_FRAC0
- REG_NDIV_FRAC1
- REG_NDIV_FRAC2
- REG_NDIV_INT
- REG_NDPA_OPT_CTRL
- REG_NDPA_OPT_CTRL_8723B
- REG_NEED_CPU_HANDLE
- REG_NHM_TH3_TO_TH0_8723B
- REG_NHM_TH7_TO_TH4_8723B
- REG_NHM_TH9_TH10_8723B
- REG_NHM_TIMER_8723B
- REG_NLINE_LSB
- REG_NLINE_MSB
- REG_NM
- REG_NOA_DESC_COUNT
- REG_NOA_DESC_DURATION
- REG_NOA_DESC_INTERVAL
- REG_NOA_DESC_SEL
- REG_NOA_DESC_START
- REG_NODEADRS
- REG_NOMASK_TXBT
- REG_NONE
- REG_NORMALIZER
- REG_NORMALIZER_10G
- REG_NORMAL_SIE_EP
- REG_NORMAL_SIE_EP_TX
- REG_NORMAL_SIE_GPS_EP
- REG_NORMAL_SIE_MAC_ADDR
- REG_NORMAL_SIE_OPTIONAL
- REG_NORMAL_SIE_OPTIONAL2
- REG_NORMAL_SIE_PHY
- REG_NORMAL_SIE_PID
- REG_NORMAL_SIE_STRING
- REG_NORMAL_SIE_VID
- REG_NORTHBRIDGE_CAP
- REG_NORTHBRIDGE_CAPABILITIES
- REG_NOSUPPORT
- REG_NO_MASK
- REG_NPIX_LSB
- REG_NPIX_MSB
- REG_NQOS_SEQ
- REG_NSEC
- REG_NULL
- REG_NUM_BYTES
- REG_NUM_INVALID
- REG_NUM_PER_LINE
- REG_NUM_REMAIN_MASK
- REG_NUM_SEND
- REG_NXT_CEQE
- REG_NXT_SE_CEQE
- REG_OCL_BW0
- REG_OCL_BW1
- REG_OCL_BW2
- REG_OCL_BW3
- REG_OCL_BW4
- REG_OCL_BWS
- REG_OCL_CFG1
- REG_OCL_CFG13
- REG_OCP
- REG_OCPCTL
- REG_OCPGLITCH
- REG_OCPPARA1
- REG_OCPPARA2
- REG_OCPSTAT
- REG_OEA
- REG_OEB
- REG_OEC
- REG_OED
- REG_OEE
- REG_OF
- REG_OFDM0_AGCR_SSI_TABLE
- REG_OFDM0_AGC_PARM1
- REG_OFDM0_ENERGY_CCA_THRES
- REG_OFDM0_FA_RSTC
- REG_OFDM0_RX_D_SYNC_PATH
- REG_OFDM0_RX_IQ_EXT_ANTA
- REG_OFDM0_TRX_PATH_ENABLE
- REG_OFDM0_TR_MUX_PAR
- REG_OFDM0_TX_PSDO_NOISE_WEIGHT
- REG_OFDM0_XA_AGC_CORE1
- REG_OFDM0_XA_AGC_CORE2
- REG_OFDM0_XA_RX_IQ_IMBALANCE
- REG_OFDM0_XA_TX_IQ_IMBALANCE
- REG_OFDM0_XB_AGC_CORE1
- REG_OFDM0_XB_AGC_CORE2
- REG_OFDM0_XB_RX_IQ_IMBALANCE
- REG_OFDM0_XB_TX_IQ_IMBALANCE
- REG_OFDM0_XC_AGC_CORE1
- REG_OFDM0_XC_AGC_CORE2
- REG_OFDM0_XC_TX_AFE
- REG_OFDM0_XC_TX_IQ_IMBALANCE
- REG_OFDM0_XD_AGC_CORE1
- REG_OFDM0_XD_AGC_CORE2
- REG_OFDM0_XD_TX_AFE
- REG_OFDM0_XD_TX_IQ_IMBALANCE
- REG_OFDM1_LSTF
- REG_OFDM1_TRX_PATH_ENABLE
- REG_OFDM_FACNT
- REG_OFDM_FACNT1
- REG_OFDM_FACNT2
- REG_OFDM_FACNT3
- REG_OFDM_FACNT4
- REG_OFDM_FACNT5
- REG_OFDM_TXCNT
- REG_OFF
- REG_OFFSET
- REG_OFFSET_BUFFER_STATUS
- REG_OFFSET_BULK_IN
- REG_OFFSET_BULK_OUT
- REG_OFFSET_COMMAND_BASE
- REG_OFFSET_DATA_BASE
- REG_OFFSET_END
- REG_OFFSET_INDEX
- REG_OFFSET_IN_BITS
- REG_OFFSET_MASK
- REG_OFFSET_MAX_BASELINE
- REG_OFFSET_MIN_BASELINE
- REG_OFFSET_MODE
- REG_OFFSET_NAME
- REG_OFFSET_NAME_32
- REG_OFFSET_NAME_64
- REG_OFFSET_POWER_MODE
- REG_OFFSET_QUERY_BASE
- REG_OFFSET_SYNC_CONTROL
- REG_OFF_ADDRESS_DEST
- REG_OFF_ADDRESS_SOURCE
- REG_OFF_CHAN_SIZE
- REG_OFF_CTRL
- REG_OFF_CYCLES
- REG_OFF_OFFSET
- REG_OFON
- REG_OFS
- REG_OFS_4
- REG_OFS_NONE
- REG_OIF_CFG_CHG
- REG_OIF_EN_MIPI_LANES
- REG_OIF_EN_PACKETS
- REG_OOKAVG
- REG_OOKFIX
- REG_OOKPEAK
- REG_OPERATION_MODE
- REG_OPMODE
- REG_OPT_CTRL
- REG_OPT_CTRL_8723B
- REG_OP_ALLOC
- REG_OP_DATA1
- REG_OP_ISFREE
- REG_OP_PIX_CLK_DIV
- REG_OP_RELEASE
- REG_OP_STATUS
- REG_OP_SYS_CLK_DIV
- REG_ORDER
- REG_ORIG_R0
- REG_ORITXCODE
- REG_ORITXCODE2
- REG_OSC1
- REG_OSCILLATOR_CONTROL
- REG_OSC_CLK
- REG_OSC_CONTROL
- REG_OSC_DIVIDER
- REG_OTP_CTRL
- REG_OTP_DBYTE510
- REG_OTP_PROGRAMMING_ID_KEY
- REG_OTP_VCM_PROGRAMMING
- REG_OTP_VCM_STATUS_ENABLE
- REG_OUT
- REG_OUT5V
- REG_OUTMAIL_CMD
- REG_OUTMAIL_CMD_OPMODE_MASK
- REG_OUTMAIL_CMD_OPMODE_SHIFT
- REG_OUTPUT_CFG
- REG_OUTPUT_DRIVE
- REG_OUTPUT_FORMAT
- REG_OUTPUT_FORMATTER1
- REG_OUTPUT_FORMATTER2
- REG_OUTPUT_FORMATTER3
- REG_OUTPUT_FORMATTER4
- REG_OUTPUT_FORMATTER5
- REG_OUTPUT_FORMATTER6
- REG_OUTPUT_LEN_PER_LINE
- REG_OUTPUT_SELECT00
- REG_OUTPUT_SELECT01
- REG_OUTPUT_SELECT02
- REG_OUTPUT_VALUE00
- REG_OUTPUT_VALUE01
- REG_OUTPUT_VALUE02
- REG_OUTSIZE_LSB
- REG_OUT_DMAC
- REG_OUT_HEIGHT_HIGH
- REG_OUT_HEIGHT_LOW
- REG_OUT_SEL
- REG_OUT_TOTAL_HEIGHT_HIGH
- REG_OUT_TOTAL_HEIGHT_LOW
- REG_OUT_TOTAL_WIDTH_HIGH
- REG_OUT_TOTAL_WIDTH_LOW
- REG_OUT_WIDTH_HIGH
- REG_OUT_WIDTH_LOW
- REG_OVERFLOW
- REG_OVERSAMP
- REG_OWNER_EPID
- REG_O_CHUNK
- REG_O_ONE
- REG_O_RANGE
- REG_O_ZERO
- REG_O_ZERO_RANGE
- REG_P1CR2
- REG_P1CR4
- REG_P1MBCR
- REG_P1MBSR
- REG_P1SR
- REG_P2MBCR
- REG_P2MBSR
- REG_P2P_CTWIN
- REG_PACKETCONFIG1
- REG_PACKETCONFIG2
- REG_PACKET_LEN
- REG_PACON0
- REG_PACON1
- REG_PACON2
- REG_PAD_CTRL1
- REG_PAD_CTRL1_8723B
- REG_PAGE
- REG_PAGE1_ADDR
- REG_PAGE2_ADDR
- REG_PAGE3_ADDR
- REG_PAGE7_ADDR
- REG_PAGE8_ADDR
- REG_PAGESIZE
- REG_PAGE_CBUS_ADDR
- REG_PAGE_FAULT_ADDR
- REG_PAGE_MHLSPEC_ADDR
- REG_PAIR
- REG_PALEVEL
- REG_PANEL_INFO
- REG_PANIDH
- REG_PANIDL
- REG_PAN_ID0
- REG_PAN_ID1
- REG_PARAMETER
- REG_PARAMP
- REG_PART_REV
- REG_PATCH_VERSION
- REG_PATTERN_HEIGHT
- REG_PATTERN_PARAM
- REG_PATTERN_SET
- REG_PATTERN_TEST
- REG_PATTERN_TEST_ARRAY
- REG_PATTERN_WIDTH
- REG_PAUSE_10G
- REG_PAUSE_CFG
- REG_PAUSE_OFF_TH
- REG_PAUSE_ON_TH
- REG_PAYLOAD_LENGTH
- REG_PA_BIAS
- REG_PA_BIAS_DFL
- REG_PA_CFG
- REG_PA_RR
- REG_PBP
- REG_PBP_8723B
- REG_PC
- REG_PCAR
- REG_PCIE_C2H_MSG_REQUEST
- REG_PCIE_CAP_LIST
- REG_PCIE_CTRL2
- REG_PCIE_CTRL_REG
- REG_PCIE_CTRL_REG_8723B
- REG_PCIE_DEV_MISC_CTRL
- REG_PCIE_DLL_TX_CTRL1
- REG_PCIE_ERROR_COUNT
- REG_PCIE_HCPWM
- REG_PCIE_HCPWM_8723B
- REG_PCIE_HIMR
- REG_PCIE_HIMRE
- REG_PCIE_HISR
- REG_PCIE_HISRE
- REG_PCIE_HISR_EN
- REG_PCIE_HRPWM
- REG_PCIE_HRPWM_8723B
- REG_PCIE_IND_ACC_ADDR
- REG_PCIE_IND_ACC_DATA
- REG_PCIE_MIO_INTD
- REG_PCIE_MIO_INTF
- REG_PCIE_MIX_CFG
- REG_PCIE_MULTIFET_CTRL_8723B
- REG_PCIE_PHYMISC
- REG_PCIE_PHYMISC2
- REG_PCI_ERR_STATUS
- REG_PCI_ERR_STATUS_MASK
- REG_PCI_INTBRG_CTRL
- REG_PCI_STSCMD
- REG_PCLK
- REG_PCR
- REG_PCS_CFG
- REG_PCS_CTRL
- REG_PCS_DATAPATH_MODE
- REG_PCS_INTR_STATUS
- REG_PCS_MII_ADVERT
- REG_PCS_MII_CTRL
- REG_PCS_MII_LPA
- REG_PCS_MII_STATUS
- REG_PCS_PACKET_COUNT
- REG_PCS_SERDES_CTRL
- REG_PCS_SERDES_STATE
- REG_PCS_SHARED_OUTPUT_SEL
- REG_PCS_STATE_MACHINE
- REG_PCS_STATUS_DBG
- REG_PC_ON_RECOVERY
- REG_PC_RRT
- REG_PC_WRT
- REG_PDERRCNT
- REG_PDMFTH
- REG_PD_AUX
- REG_PECI_ENABLE
- REG_PERF_STATE
- REG_PERIOD
- REG_PFDR_BARE
- REG_PFDR_CFG
- REG_PFDR_FPC
- REG_PFDR_FP_HEAD
- REG_PFDR_FP_LWIT
- REG_PFDR_FP_TAIL
- REG_PGA_VALID
- REG_PHASE
- REG_PHASE_EXP
- REG_PHYBIST
- REG_PHYCTL_A10
- REG_PHYCTL_A33
- REG_PHYS_ADDR
- REG_PHYS_ADDR_V7
- REG_PHYS_BASE
- REG_PHYS_BASE_V7
- REG_PHYTUNE
- REG_PHY_10BOP
- REG_PHY_ANA
- REG_PHY_ANE
- REG_PHY_ANLPAR
- REG_PHY_CTRL
- REG_PHY_CTRL_OFFSET
- REG_PHY_ECTRL1
- REG_PHY_ECTRL2
- REG_PHY_ENABLE
- REG_PHY_FTMAC100_READ
- REG_PHY_FTMAC100_WRITE
- REG_PHY_ID1
- REG_PHY_ID2
- REG_PHY_OTGCTL
- REG_PHY_QPDS
- REG_PHY_REVISION
- REG_PHY_STATUS
- REG_PHY_WRITE_DATA
- REG_PID
- REG_PIDH
- REG_PIDL
- REG_PIDn
- REG_PIFS
- REG_PIFS_8723B
- REG_PIH_ISR_P1
- REG_PIH_ISR_P2
- REG_PIH_SIR
- REG_PINMUX0
- REG_PINMUX1
- REG_PINMUX5
- REG_PINTCL_REG
- REG_PINTEN_REG
- REG_PINTST_REG
- REG_PIN_03_SEL
- REG_PIN_47_SEL
- REG_PIN_SEL_SHIFT
- REG_PIO_CLR_PC
- REG_PIO_CLR_PCOMP
- REG_PIO_CLR_PMASK
- REG_PIO_CLR_POUT
- REG_PIO_PC
- REG_PIO_PCOMP
- REG_PIO_PIN
- REG_PIO_PMASK
- REG_PIO_POUT
- REG_PIO_SET_PC
- REG_PIO_SET_PCOMP
- REG_PIO_SET_PMASK
- REG_PIO_SET_POUT
- REG_PITEN
- REG_PIX_REPEAT
- REG_PKTBUF_DBG_ADDR
- REG_PKTBUF_DBG_CTRL
- REG_PKTBUF_DBG_CTRL_8723B
- REG_PKTBUF_DBG_DATA_H
- REG_PKTBUF_DBG_DATA_H_8723B
- REG_PKTBUF_DBG_DATA_L
- REG_PKTBUF_DBG_DATA_L_8723B
- REG_PKT_BE_BK_LIFE_TIME
- REG_PKT_BE_BK_LIFE_TIME_8723B
- REG_PKT_BUFF_ACCESS_CTRL
- REG_PKT_BUFF_ACCESS_CTRL_8723B
- REG_PKT_CFG
- REG_PKT_FILTER_0
- REG_PKT_FILTER_1
- REG_PKT_LIFE_TIME
- REG_PKT_LOSE_RPT
- REG_PKT_MON_CTRL
- REG_PKT_VO_VI_LIFE_TIME
- REG_PKT_VO_VI_LIFE_TIME_8723B
- REG_PLLSTATUS
- REG_PLL_CFG
- REG_PLL_CLK_SPEED
- REG_PLL_DIVL
- REG_PLL_MULTIPLIER
- REG_PLL_SCG1
- REG_PLL_SCG2
- REG_PLL_SCGN1
- REG_PLL_SCGN2
- REG_PLL_SCGR1
- REG_PLL_SCGR2
- REG_PLL_SERIAL_1
- REG_PLL_SERIAL_2
- REG_PLL_SERIAL_3
- REG_PLUS_ALIASN_CLEAR
- REG_PLUS_ALIAS_CLEAR_1
- REG_PLUS_INTRN_MASK
- REG_PLUS_INTRN_STATUS
- REG_PLUS_INTRN_STATUS_ALIAS
- REG_PLUS_INTR_MASK_1
- REG_PLUS_INTR_STATUS_1
- REG_PLUS_INTR_STATUS_ALIAS_1
- REG_PLUS_PROBE_MUX_SELECT
- REG_PLUS_RX_AE1_THRESH
- REG_PLUS_RX_CB1_HI
- REG_PLUS_RX_CB1_LOW
- REG_PLUS_RX_CBN_HI
- REG_PLUS_RX_CBN_LOW
- REG_PLUS_RX_COMP1
- REG_PLUS_RX_COMP1_HEAD
- REG_PLUS_RX_COMP1_TAIL
- REG_PLUS_RX_COMPN_HEAD
- REG_PLUS_RX_COMPN_TAIL
- REG_PLUS_RX_DB1_HI
- REG_PLUS_RX_DB1_LOW
- REG_PLUS_RX_KICK1
- REG_PM8058_VREG_EN_GRP_5_4
- REG_PM8058_VREG_EN_MSM
- REG_PMAP_TABLE
- REG_PMC
- REG_PMC_DBG_CTRL2
- REG_PMC_DBG_CTRL2_8723B
- REG_PMPD_ANAEN
- REG_PMR1_SB_ADC_OFFSET
- REG_PMR1_SB_DAC_OFFSET
- REG_PMR1_SB_IND_OFFSET
- REG_PMR1_SB_LIN_OFFSET
- REG_PMR1_SB_MIX_OFFSET
- REG_PMR1_SB_OUT_OFFSET
- REG_PMR2_GIM_OFFSET
- REG_PMR2_LRGI_OFFSET
- REG_PMR2_LRGOD_OFFSET
- REG_PMR2_RLGI_OFFSET
- REG_PMR2_RLGOD_OFFSET
- REG_PMR2_SB_MC_OFFSET
- REG_PMR2_SB_OFFSET
- REG_PMR2_SB_SLEEP_OFFSET
- REG_PMU_ISP_ARM_CONFIGURATION
- REG_PMU_ISP_ARM_OPTION
- REG_PMU_ISP_ARM_STATUS
- REG_PMU_ISP_ARM_SYS
- REG_PMU_UNK1
- REG_PM_CTRL
- REG_PM_CTRLSTAT
- REG_PNO_STATUS
- REG_POISON
- REG_PON_CBIAS
- REG_PON_CLK
- REG_PON_DES
- REG_PON_EQ
- REG_PON_MUX
- REG_PON_OUT
- REG_PON_OVR_EN
- REG_PON_PLL
- REG_PON_RES
- REG_PON_RESCAL
- REG_PORT
- REG_PORTA
- REG_PORTB
- REG_PORTC
- REG_PORTD
- REG_PORT_1_CTRL_0
- REG_PORT_1_CTRL_1
- REG_PORT_1_CTRL_10
- REG_PORT_1_CTRL_12
- REG_PORT_1_CTRL_13
- REG_PORT_1_CTRL_14
- REG_PORT_1_CTRL_15
- REG_PORT_1_CTRL_16
- REG_PORT_1_CTRL_17
- REG_PORT_1_CTRL_2
- REG_PORT_1_CTRL_3
- REG_PORT_1_CTRL_4
- REG_PORT_1_CTRL_5
- REG_PORT_1_CTRL_7
- REG_PORT_1_CTRL_9
- REG_PORT_1_IN_RATE_0
- REG_PORT_1_IN_RATE_1
- REG_PORT_1_IN_RATE_2
- REG_PORT_1_IN_RATE_3
- REG_PORT_1_LINK_MD_CTRL
- REG_PORT_1_LINK_MD_RESULT
- REG_PORT_1_OUT_RATE_0
- REG_PORT_1_OUT_RATE_1
- REG_PORT_1_OUT_RATE_2
- REG_PORT_1_OUT_RATE_3
- REG_PORT_1_RATE_CTRL_0
- REG_PORT_1_RATE_CTRL_1
- REG_PORT_1_RATE_CTRL_2
- REG_PORT_1_RATE_CTRL_3
- REG_PORT_1_RATE_LIMIT
- REG_PORT_1_STATUS_0
- REG_PORT_1_STATUS_1
- REG_PORT_1_STATUS_2
- REG_PORT_1_STATUS_3
- REG_PORT_2_CTRL_0
- REG_PORT_2_CTRL_1
- REG_PORT_2_CTRL_10
- REG_PORT_2_CTRL_12
- REG_PORT_2_CTRL_13
- REG_PORT_2_CTRL_14
- REG_PORT_2_CTRL_15
- REG_PORT_2_CTRL_16
- REG_PORT_2_CTRL_17
- REG_PORT_2_CTRL_2
- REG_PORT_2_CTRL_3
- REG_PORT_2_CTRL_4
- REG_PORT_2_CTRL_5
- REG_PORT_2_CTRL_7
- REG_PORT_2_CTRL_9
- REG_PORT_2_IN_RATE_0
- REG_PORT_2_IN_RATE_1
- REG_PORT_2_IN_RATE_2
- REG_PORT_2_IN_RATE_3
- REG_PORT_2_LINK_MD_CTRL
- REG_PORT_2_LINK_MD_RESULT
- REG_PORT_2_OUT_RATE_0
- REG_PORT_2_OUT_RATE_1
- REG_PORT_2_OUT_RATE_2
- REG_PORT_2_OUT_RATE_3
- REG_PORT_2_RATE_CTRL_0
- REG_PORT_2_RATE_CTRL_1
- REG_PORT_2_RATE_CTRL_2
- REG_PORT_2_RATE_CTRL_3
- REG_PORT_2_RATE_LIMIT
- REG_PORT_2_STATUS_0
- REG_PORT_2_STATUS_1
- REG_PORT_2_STATUS_2
- REG_PORT_2_STATUS_3
- REG_PORT_3_CTRL_0
- REG_PORT_3_CTRL_1
- REG_PORT_3_CTRL_10
- REG_PORT_3_CTRL_12
- REG_PORT_3_CTRL_13
- REG_PORT_3_CTRL_14
- REG_PORT_3_CTRL_15
- REG_PORT_3_CTRL_16
- REG_PORT_3_CTRL_17
- REG_PORT_3_CTRL_2
- REG_PORT_3_CTRL_3
- REG_PORT_3_CTRL_4
- REG_PORT_3_CTRL_5
- REG_PORT_3_CTRL_7
- REG_PORT_3_CTRL_9
- REG_PORT_3_IN_RATE_0
- REG_PORT_3_IN_RATE_1
- REG_PORT_3_IN_RATE_2
- REG_PORT_3_IN_RATE_3
- REG_PORT_3_LINK_MD_CTRL
- REG_PORT_3_LINK_MD_RESULT
- REG_PORT_3_OUT_RATE_0
- REG_PORT_3_OUT_RATE_1
- REG_PORT_3_OUT_RATE_2
- REG_PORT_3_OUT_RATE_3
- REG_PORT_3_RATE_CTRL_0
- REG_PORT_3_RATE_CTRL_1
- REG_PORT_3_RATE_CTRL_2
- REG_PORT_3_RATE_CTRL_3
- REG_PORT_3_RATE_LIMIT
- REG_PORT_3_STATUS_0
- REG_PORT_3_STATUS_1
- REG_PORT_3_STATUS_2
- REG_PORT_3_STATUS_3
- REG_PORT_4_CTRL_0
- REG_PORT_4_CTRL_1
- REG_PORT_4_CTRL_10
- REG_PORT_4_CTRL_12
- REG_PORT_4_CTRL_13
- REG_PORT_4_CTRL_14
- REG_PORT_4_CTRL_15
- REG_PORT_4_CTRL_16
- REG_PORT_4_CTRL_17
- REG_PORT_4_CTRL_2
- REG_PORT_4_CTRL_3
- REG_PORT_4_CTRL_4
- REG_PORT_4_CTRL_5
- REG_PORT_4_CTRL_7
- REG_PORT_4_CTRL_9
- REG_PORT_4_IN_RATE_0
- REG_PORT_4_IN_RATE_1
- REG_PORT_4_IN_RATE_2
- REG_PORT_4_IN_RATE_3
- REG_PORT_4_LINK_MD_CTRL
- REG_PORT_4_LINK_MD_RESULT
- REG_PORT_4_OUT_RATE_0
- REG_PORT_4_OUT_RATE_1
- REG_PORT_4_OUT_RATE_2
- REG_PORT_4_OUT_RATE_3
- REG_PORT_4_RATE_CTRL_0
- REG_PORT_4_RATE_CTRL_1
- REG_PORT_4_RATE_CTRL_2
- REG_PORT_4_RATE_CTRL_3
- REG_PORT_4_RATE_LIMIT
- REG_PORT_4_STATUS_0
- REG_PORT_4_STATUS_1
- REG_PORT_4_STATUS_2
- REG_PORT_4_STATUS_3
- REG_PORT_5_CTRL_0
- REG_PORT_5_CTRL_1
- REG_PORT_5_CTRL_12
- REG_PORT_5_CTRL_13
- REG_PORT_5_CTRL_14
- REG_PORT_5_CTRL_15
- REG_PORT_5_CTRL_16
- REG_PORT_5_CTRL_17
- REG_PORT_5_CTRL_2
- REG_PORT_5_CTRL_3
- REG_PORT_5_CTRL_4
- REG_PORT_5_CTRL_5
- REG_PORT_5_CTRL_6
- REG_PORT_5_IN_RATE_0
- REG_PORT_5_IN_RATE_1
- REG_PORT_5_IN_RATE_2
- REG_PORT_5_IN_RATE_3
- REG_PORT_5_OUT_RATE_0
- REG_PORT_5_OUT_RATE_1
- REG_PORT_5_OUT_RATE_2
- REG_PORT_5_OUT_RATE_3
- REG_PORT_5_RATE_CTRL_0
- REG_PORT_5_RATE_CTRL_1
- REG_PORT_5_RATE_CTRL_2
- REG_PORT_5_RATE_CTRL_3
- REG_PORT_5_RATE_LIMIT
- REG_PORT_ACL_0
- REG_PORT_ACL_1
- REG_PORT_ACL_2
- REG_PORT_ACL_3
- REG_PORT_ACL_4
- REG_PORT_ACL_5
- REG_PORT_ACL_6
- REG_PORT_ACL_7
- REG_PORT_ACL_8
- REG_PORT_ACL_9
- REG_PORT_ACL_A
- REG_PORT_ACL_B
- REG_PORT_ACL_BYTE_EN_LSB
- REG_PORT_ACL_BYTE_EN_MSB
- REG_PORT_ACL_C
- REG_PORT_ACL_CTRL_0
- REG_PORT_ACL_CTRL_1
- REG_PORT_ACL_D
- REG_PORT_ACL_E
- REG_PORT_ACL_F
- REG_PORT_AVB_SR_1_TYPE
- REG_PORT_AVB_SR_1_VID
- REG_PORT_AVB_SR_2_TYPE
- REG_PORT_AVB_SR_2_VID
- REG_PORT_CTRL_0
- REG_PORT_CTRL_1
- REG_PORT_CTRL_10
- REG_PORT_CTRL_12
- REG_PORT_CTRL_13
- REG_PORT_CTRL_2
- REG_PORT_CTRL_5
- REG_PORT_CTRL_7
- REG_PORT_CTRL_9
- REG_PORT_CTRL_VID
- REG_PORT_CUSTOM_VID
- REG_PORT_DEFAULT_VID
- REG_PORT_FAIL
- REG_PORT_INT_MASK
- REG_PORT_INT_STATUS
- REG_PORT_IN_RATE_0
- REG_PORT_IN_RATE_1
- REG_PORT_IN_RATE_2
- REG_PORT_IN_RATE_3
- REG_PORT_IN_RATE_4
- REG_PORT_IN_RATE_5
- REG_PORT_IN_RATE_6
- REG_PORT_IN_RATE_7
- REG_PORT_LINK_MD_CTRL
- REG_PORT_LINK_MD_RESULT
- REG_PORT_LUE_CTRL
- REG_PORT_LUE_MSTP_INDEX
- REG_PORT_LUE_MSTP_STATE
- REG_PORT_MAC_CTRL_0
- REG_PORT_MAC_CTRL_1
- REG_PORT_MAC_CTRL_2
- REG_PORT_MAC_IN_RATE_LIMIT
- REG_PORT_MIB_CTRL_STAT__4
- REG_PORT_MIB_DATA
- REG_PORT_MRI_AUTHEN_CTRL
- REG_PORT_MRI_INDEX__4
- REG_PORT_MRI_MAC_CTRL
- REG_PORT_MRI_MIRROR_CTRL
- REG_PORT_MRI_POLICE_CTRL__4
- REG_PORT_MRI_PRIO_CTRL
- REG_PORT_MRI_TC_MAP__4
- REG_PORT_MTI_CREDIT_INCREMENT
- REG_PORT_MTI_HI_WATER_MARK
- REG_PORT_MTI_LO_WATER_MARK
- REG_PORT_MTI_QUEUE_CTRL_0
- REG_PORT_MTI_QUEUE_CTRL_0__4
- REG_PORT_MTI_QUEUE_CTRL_1
- REG_PORT_MTI_QUEUE_CTRL_2__2
- REG_PORT_MTI_QUEUE_CTRL_3__2
- REG_PORT_MTI_QUEUE_CTRL_4__2
- REG_PORT_MTI_QUEUE_INDEX__4
- REG_PORT_OUT_RATE_0
- REG_PORT_OUT_RATE_1
- REG_PORT_OUT_RATE_2
- REG_PORT_OUT_RATE_3
- REG_PORT_PHY_1000_CTRL
- REG_PORT_PHY_1000_STATUS
- REG_PORT_PHY_AUTO_NEGOTIATION
- REG_PORT_PHY_CTRL
- REG_PORT_PHY_DIGITAL_DEBUG_1
- REG_PORT_PHY_DIGITAL_DEBUG_2
- REG_PORT_PHY_DIGITAL_DEBUG_3
- REG_PORT_PHY_DIGITAL_STATUS
- REG_PORT_PHY_EXTENDED_STATUS
- REG_PORT_PHY_ID_HI
- REG_PORT_PHY_ID_LO
- REG_PORT_PHY_INT_ENABLE
- REG_PORT_PHY_INT_STATUS
- REG_PORT_PHY_LINK_MD
- REG_PORT_PHY_MMD_INDEX_DATA
- REG_PORT_PHY_MMD_SETUP
- REG_PORT_PHY_PHY_CTRL
- REG_PORT_PHY_PMA_STATUS
- REG_PORT_PHY_REMOTE_CAPABILITY
- REG_PORT_PHY_REMOTE_LB_LED
- REG_PORT_PHY_RXER_COUNTER
- REG_PORT_PHY_STATUS
- REG_PORT_PME_CTRL
- REG_PORT_PME_STATUS
- REG_PORT_POLICE_BURST_SIZE__4
- REG_PORT_POLICE_COLOR_0__4
- REG_PORT_POLICE_COLOR_1__4
- REG_PORT_POLICE_COLOR_2__4
- REG_PORT_POLICE_COLOR_3__4
- REG_PORT_POLICE_RATE__4
- REG_PORT_POS
- REG_PORT_QM_CTRL__4
- REG_PORT_QM_QUEUE_INDEX__4
- REG_PORT_QM_TX_CNT_0__4
- REG_PORT_QM_TX_CNT_1__4
- REG_PORT_QM_WATER_MARK__4
- REG_PORT_RATE_CTRL_0
- REG_PORT_RATE_CTRL_1
- REG_PORT_RATE_CTRL_2
- REG_PORT_RATE_CTRL_3
- REG_PORT_RATE_LIMIT
- REG_PORT_SGMII_ADDR__4
- REG_PORT_SGMII_DATA__4
- REG_PORT_STATUS_0
- REG_PORT_STATUS_1
- REG_PORT_STATUS_2
- REG_PORT_STATUS_3
- REG_PORT_VLAN_MEMBERSHIP__4
- REG_PORT_WRED_PM_CTRL_0__4
- REG_PORT_WRED_PM_CTRL_1__4
- REG_PORT_WRED_QUEUE_CTRL_0__4
- REG_PORT_WRED_QUEUE_CTRL_1__4
- REG_PORT_WRED_QUEUE_PMON__4
- REG_PORT_XMII_CTRL_0
- REG_PORT_XMII_CTRL_1
- REG_POS
- REG_POSNEG
- REG_POWERON
- REG_POWER_CONTROL
- REG_POWER_CONTROL_1
- REG_POWER_CONTROL_2
- REG_POWER_CONTROL_3
- REG_POWER_CONTROL_4
- REG_POWER_MANAGEMENT_1
- REG_POWER_MANAGEMENT_2
- REG_POWER_OFF_IN_PROCESS
- REG_POWER_STAGE1
- REG_POWER_STAGE1_8723B
- REG_POWER_STAGE2
- REG_POWER_STAGE2_8723B
- REG_POWER_STATUS
- REG_PR
- REG_PRAMPG
- REG_PREAMBLE_LSB
- REG_PREAMBLE_MSB
- REG_PRECNT_CTRL
- REG_PRE_BIT0POS
- REG_PRE_BIT1POS
- REG_PRE_BIT2POS
- REG_PRE_BIT3POS
- REG_PRE_CAC_EXPIRY_GRACE_MS
- REG_PRE_ERR_CNT
- REG_PRE_ISP_CTRL00
- REG_PRE_PLL_CLK_DIV
- REG_PRE_RW_MODE
- REG_PROCESSOR_TDP
- REG_PROCESS_CTRL
- REG_PRODUCTID
- REG_PRODUCTID_EXT
- REG_PRODUCT_ID
- REG_PROTOCOL_GEN_QUERY_OFFSET
- REG_PROT_MODE_CTRL
- REG_PROT_MODE_CTRL_8723B
- REG_PR_ARG
- REG_PR_FMT
- REG_PS
- REG_PSHFT
- REG_PSR
- REG_PSSTATUS
- REG_PSTIMER
- REG_PSTIMER_8723B
- REG_PS_LOCK
- REG_PS_RX_INFO
- REG_PS_RX_INFO_8723B
- REG_PTCL_ERR_STATUS
- REG_PTI_CTL
- REG_PTI_LENGTH
- REG_PTI_OFFSET
- REG_PTP_CLK_CTRL
- REG_PTP_CTRL_STAT__4
- REG_PTP_DOMAIN_VERSION
- REG_PTP_INT_STATUS__4
- REG_PTP_MSG_CONF1
- REG_PTP_MSG_CONF2
- REG_PTP_PORT_ASYM_DELAY__2
- REG_PTP_PORT_LINK_DELAY__4
- REG_PTP_PORT_PDRESP_TS
- REG_PTP_PORT_PDRESP_TS_H
- REG_PTP_PORT_PDRESP_TS_L
- REG_PTP_PORT_RX_DELAY__2
- REG_PTP_PORT_SYNC_TS
- REG_PTP_PORT_SYNC_TS_H
- REG_PTP_PORT_SYNC_TS_L
- REG_PTP_PORT_TX_DELAY__2
- REG_PTP_PORT_TX_INT_ENABLE__2
- REG_PTP_PORT_TX_INT_STATUS__2
- REG_PTP_PORT_XDELAY_TS
- REG_PTP_PORT_XDELAY_TS_H
- REG_PTP_PORT_XDELAY_TS_L
- REG_PTP_RATE_DURATION
- REG_PTP_RATE_DURATION_H
- REG_PTP_RATE_DURATION_L
- REG_PTP_RTC_NANOSEC
- REG_PTP_RTC_NANOSEC_H
- REG_PTP_RTC_NANOSEC_L
- REG_PTP_RTC_SEC
- REG_PTP_RTC_SEC_H
- REG_PTP_RTC_SEC_L
- REG_PTP_RTC_SUB_NANOSEC__2
- REG_PTP_SUBNANOSEC_RATE
- REG_PTP_SUBNANOSEC_RATE_H
- REG_PTP_SUBNANOSEC_RATE_L
- REG_PTP_TRIG_STATUS__4
- REG_PTP_UNIT_INDEX__4
- REG_PTR
- REG_PTR_CCM_COOL_WHITE
- REG_PTR_CCM_DL50
- REG_PTR_CCM_DL65
- REG_PTR_CCM_HORIZON
- REG_PTR_CCM_INCANDESCENT
- REG_PTR_CCM_OUTDOOR
- REG_PTR_CCM_WARM_WHITE
- REG_PT_BASE_ADDR
- REG_PT_CHSMO
- REG_PULL
- REG_PULLEN
- REG_PWD_SRST
- REG_PWM
- REG_PWM_A
- REG_PWM_B
- REG_PWM_BASE
- REG_PWM_CONFIG_BASE
- REG_PWM_MAX_BASE
- REG_PWM_MIN_BASE
- REG_PWM_OUTHIGH
- REG_PWM_OUTLOW
- REG_PWRDN
- REG_PWREN
- REG_PWR_CONTROL
- REG_PWR_CR3
- REG_PWR_DATA
- REG_PWR_DATA_8723B
- REG_PXCNT_NPIX
- REG_PXCNT_PR
- REG_P_CAP_MIRROR
- REG_P_CAP_ROTATION
- REG_P_CLK_INDEX
- REG_P_COLORTEMP
- REG_P_FMT
- REG_P_FR_RATE_Q_TYPE
- REG_P_FR_RATE_TYPE
- REG_P_FR_TIME_Q_TYPE
- REG_P_FR_TIME_TYPE
- REG_P_GAMMA_INDEX
- REG_P_GLAMOUR
- REG_P_MAX_FR_TIME
- REG_P_MAX_OUT_RATE
- REG_P_MIN_FR_TIME
- REG_P_MIN_OUT_RATE
- REG_P_OUT_HEIGHT
- REG_P_OUT_WIDTH
- REG_P_PREV_MIRROR
- REG_P_PVI_MASK
- REG_P_SATURATION
- REG_P_SHARP_BLUR
- REG_Q0_INFO
- REG_Q1_INFO
- REG_Q2_INFO
- REG_Q3_INFO
- REG_QCSP_BAR
- REG_QCSP_BARE
- REG_QCSP_DD_CFG
- REG_QCSP_IO_CFG
- REG_QCSP_LIO_CFG
- REG_QFPROM_CONFIG_ROW0_LSB
- REG_QMU_DATA_HI
- REG_QMU_DATA_LO
- REG_QOS_SEQ
- REG_QRFCR
- REG_QUEUE_CTRL
- REG_R0
- REG_R1
- REG_R10
- REG_R11
- REG_R12
- REG_R13
- REG_R14
- REG_R15
- REG_R2
- REG_R2T_SIFS
- REG_R3
- REG_R4
- REG_R5
- REG_R6
- REG_R7
- REG_R8
- REG_R9
- REG_RA
- REG_RAGE128_H
- REG_RAMPCTRL
- REG_RAMSIZE
- REG_RAM_ADDRESS_SET
- REG_RAM_ADDR_POS_H
- REG_RAM_ADDR_POS_V
- REG_RAM_BIST_CMD
- REG_RAM_BIST_RESULT
- REG_RAM_R
- REG_RAM_RESET
- REG_RAM_W
- REG_RAM_WRITE_MASK1
- REG_RAM_WRITE_MASK2
- REG_RARFRC
- REG_RARFRCH
- REG_RARFRC_8723B
- REG_RATE_CTRL
- REG_RAVE
- REG_RAVG
- REG_RAWIRQSTATUS
- REG_RAW_FW_STATUS_ADDR
- REG_RA_TRY_RATE_AGG_LMT
- REG_RA_TRY_RATE_AGG_LMT_8723B
- REG_RB
- REG_RBIAS
- REG_RC
- REG_RCAL_START
- REG_RCAMO
- REG_RCR
- REG_RCR_8723B
- REG_RC_CFG
- REG_RC_VAR44
- REG_RD
- REG_RD16
- REG_RD8
- REG_RDAT
- REG_RDCONF
- REG_RDG_PIFS
- REG_RDG_PIFS_8723B
- REG_RD_CTRL
- REG_RD_CTRL_8723B
- REG_RD_DMAE
- REG_RD_IND
- REG_RD_NAV_NXT
- REG_RD_NAV_NXT_8723B
- REG_RD_RESP_PKT_TH
- REG_RD_RESP_PKT_TH_8723B
- REG_RE
- REG_READ
- REG_READH
- REG_READL
- REG_READ_ARRAY
- REG_READ_AUX
- REG_READ_D
- REG_READ_FIELD
- REG_READ_LATCH
- REG_READ_MODE
- REG_READ_MULTI
- REG_READ_TIMEOUT
- REG_READ_WITH_AUX
- REG_RECALIB_PERIOD
- REG_RECVEND
- REG_RECVPTR
- REG_RED
- REG_RED_GAIN
- REG_REF0
- REG_REF1
- REG_REF2
- REG_REFLINE_LSB
- REG_REFLINE_MSB
- REG_REFPIX_LSB
- REG_REFPIX_MSB
- REG_REG0
- REG_REG04
- REG_REG0C
- REG_REG0E
- REG_REG12
- REG_REG13
- REG_REG14
- REG_REG15
- REG_REG16
- REG_REG34
- REG_REG38
- REG_REG55
- REG_REG76
- REG_REG_BASE
- REG_REMAINING_CAPACITY
- REG_REMAINING_CAPACITY_CHARGE
- REG_REMCNTH
- REG_REMCNTL
- REG_REMOTE1_HYSTERSIS
- REG_REMOTE2_HYSTERSIS
- REG_REPORTED_TEMPERATURE
- REG_REQ_ALREADY_SET
- REG_REQ_CONSTELLATION
- REG_REQ_IGNORE
- REG_REQ_INTERSECT
- REG_REQ_OK
- REG_RESERVED
- REG_RESERVED1
- REG_RESERVED2
- REG_RESERVED3
- REG_RESERVED_A
- REG_RESET
- REG_RESET_OFF
- REG_RESET_REGISTER
- REG_RESET_STATUS0
- REG_RESET_STATUS1
- REG_RESET_TRIGGER
- REG_RESPONSE0
- REG_RESPONSE1
- REG_RESPONSE2
- REG_RESPONSE3
- REG_RESPONSE_COMMAND
- REG_RESPONSE_RATE_SET
- REG_RESP_SIFP_CCK_8723B
- REG_RESP_SIFS_CCK
- REG_RESP_SIFS_OFDM
- REG_RESP_SIFS_OFDM_8723B
- REG_RESULT
- REG_RESULT_H
- REG_RET
- REG_RETRY_LIMIT
- REG_REV3_QCSP_DD_CFG
- REG_REV3_QCSP_IO_CFG
- REG_REV3_QCSP_LIO_CFG
- REG_REVISION
- REG_REVISION_NUMBER_H
- REG_REVISION_NUMBER_L
- REG_REV_ID
- REG_RFCON0
- REG_RFCON1
- REG_RFCON2
- REG_RFCON3
- REG_RFCON5
- REG_RFCON6
- REG_RFCON7
- REG_RFCON8
- REG_RFCTL
- REG_RFD0_HEAD_ADDR_LO
- REG_RFD_FREE_THRESH
- REG_RFD_NIC_LEN
- REG_RFD_RING_SIZE
- REG_RFD_RRD_IDX
- REG_RFECTL
- REG_RFEINV
- REG_RFESEL0
- REG_RFESEL8
- REG_RFESEL_CTRL
- REG_RFE_BUFFER
- REG_RFE_CTRL8
- REG_RFE_CTRL_ANTA_SRC
- REG_RFE_CTRL_E
- REG_RFE_INV16
- REG_RFE_INV8
- REG_RFE_PATH_SELECT
- REG_RFSTATE
- REG_RF_BB_CMD_ADDR
- REG_RF_BB_CMD_DATA
- REG_RF_BB_GAIN_OFFSET
- REG_RF_CTRL
- REG_RF_CTRL_8723B
- REG_RGAIN
- REG_RGB444
- REG_RGMII_0_CNTRL
- REG_RGMII_1_CNTRL
- REG_RGMII_2_CNTRL
- REG_RGMII_CNTRL_P
- REG_RING_INTERRUPT_BASE
- REG_RING_NOTIFY_BASE
- REG_RIS
- REG_RISC_COUNT
- REG_RISC_STRT_ADD
- REG_RL
- REG_RLC_RCC_COUNTER
- REG_RL_8723B
- REG_RMCO
- REG_RMW
- REG_RMW_BUFFER_FLUSH
- REG_RMW_FIELD
- REG_ROM_TABLE_ADDR
- REG_ROM_TABLE_DATA
- REG_ROM_VERSION
- REG_ROS
- REG_ROUTE
- REG_ROUTE_CLKPEN
- REG_ROUTE_LOCATION
- REG_ROUTE_LOCATION__MASK
- REG_ROUTE_RXPEN
- REG_ROUTE_SCLPEN
- REG_ROUTE_SDAPEN
- REG_ROUTE_TXPEN
- REG_ROWINT_SET
- REG_ROWINT_SET_INT_ACT_HIGH
- REG_ROWINT_SET_INT_EN
- REG_RPF_AEP_COUNTER
- REG_RPT_CIP
- REG_RPT_CNTRL
- REG_RP_COUNTER
- REG_RQPN
- REG_RQPN_8723B
- REG_RQPN_CTRL_1
- REG_RQPN_CTRL_2
- REG_RQPN_NPQ
- REG_RQPN_NPQ_8723B
- REG_RRB
- REG_RRD0_HEAD_ADDR_LO
- REG_RRD_RING_SIZE
- REG_RRSR
- REG_RRSR_8723B
- REG_RSSI
- REG_RSSICONFIG
- REG_RSSITHRESH
- REG_RSSIVALUE
- REG_RSSI_ENABLE
- REG_RSSI_PAD_CTRL
- REG_RSS_HASH_FLAG
- REG_RSS_HASH_VALUE
- REG_RSS_KEY0
- REG_RSS_KEY1
- REG_RSS_KEY2
- REG_RSS_KEY3
- REG_RSS_KEY4
- REG_RSS_KEY5
- REG_RSS_KEY6
- REG_RSS_KEY7
- REG_RSS_KEY8
- REG_RSS_KEY9
- REG_RSTB_SEL
- REG_RSTEN
- REG_RST_ALL
- REG_RST_CRC
- REG_RSVD3
- REG_RSVD3_8723B
- REG_RSVD5
- REG_RSVD5_8723B
- REG_RSVD6
- REG_RSVD6_8723B
- REG_RSV_CTRL
- REG_RSV_CTRL_8723B
- REG_RTA
- REG_RTB
- REG_RTC_AE1
- REG_RTC_COMP_LSB_REG
- REG_RTC_COMP_MSB_REG
- REG_RTC_CONTROL
- REG_RTC_CONTROLM
- REG_RTC_CTRL_REG
- REG_RTC_DATE
- REG_RTC_END
- REG_RTC_HOUR
- REG_RTC_INTERRUPTS_REG
- REG_RTC_MIN
- REG_RTC_MONTH
- REG_RTC_NONE
- REG_RTC_SEC
- REG_RTC_SET
- REG_RTC_STAT
- REG_RTC_STATUS_REG
- REG_RTC_UPDATE0
- REG_RTC_WEEKDAY
- REG_RTC_YEAR
- REG_RTS_MAX_AGGR_NUM
- REG_RTS_MAX_AGGR_NUM_8723B
- REG_RT_AUTO_CTRL
- REG_RT_MAN_CTRL
- REG_RULE
- REG_RULE_EXT
- REG_RUNTIMEOFF
- REG_RUNT_TLC_COUNTER
- REG_RWCAM
- REG_RXAGCCTL
- REG_RXAGCCTL0
- REG_RXBW
- REG_RXCAL0
- REG_RXCAL1
- REG_RXCCAMSK
- REG_RXCCKSEL
- REG_RXCR
- REG_RXCTL
- REG_RXCTL_DEFAULT
- REG_RXCTL_RPPI
- REG_RXDATA
- REG_RXDATAP
- REG_RXDATAX
- REG_RXDATAX_FERR
- REG_RXDATAX_PERR
- REG_RXDATAX_RXDATA__MASK
- REG_RXDCURADD
- REG_RXDENQ
- REG_RXDESC
- REG_RXDMA_AGG_PG_TH
- REG_RXDMA_AGG_PG_TH_8723B
- REG_RXDMA_CONTROL
- REG_RXDMA_CONTROL_8723B
- REG_RXDMA_MODE_CTRL_8723B
- REG_RXDMA_PRO
- REG_RXDMA_PRO_8723B
- REG_RXDMA_STATUS
- REG_RXDMA_STATUS_8723B
- REG_RXDQBADD
- REG_RXDQBLEN
- REG_RXD_BASE_ADDR_LO
- REG_RXD_BUF_NUM
- REG_RXD_DMA_CTRL
- REG_RXERR_RPT
- REG_RXF0_BASE_ADDR_HI
- REG_RXF1_BASE_ADDR_HI
- REG_RXF2_BASE_ADDR_HI
- REG_RXF3_BASE_ADDR_HI
- REG_RXFDPR
- REG_RXFE_CFG
- REG_RXFF_BNDY
- REG_RXFF_PTR
- REG_RXFF_PTR_8723B
- REG_RXFLTMAP0
- REG_RXFLTMAP0_8723B
- REG_RXFLTMAP1
- REG_RXFLTMAP1_8723B
- REG_RXFLTMAP2
- REG_RXFLTMAP2_8723B
- REG_RXFLUSH
- REG_RXFNCTL
- REG_RXIGI
- REG_RXIGI_A
- REG_RXIGI_B
- REG_RXINT_RAI_EN
- REG_RXINT_RAL
- REG_RXINT_ROI_EN
- REG_RXINT_RPEI_EN
- REG_RXMCR
- REG_RXMIR
- REG_RXPB
- REG_RXPKTBUF_CTRL
- REG_RXPKTBUF_CTRL_8723B
- REG_RXPKTBUF_DBG
- REG_RXPKT_NUM
- REG_RXPKT_NUM_8723B
- REG_RXPSEL
- REG_RXPSF_CTRL
- REG_RXPSF_TYPE_CTRL
- REG_RXQCR
- REG_RXQ_CTRL
- REG_RXQ_JMBOSZ_RRDTIM
- REG_RXQ_RRD_PAUSE_THRESH
- REG_RXQ_RXF_PAUSE_THRESH
- REG_RXQ_TXBD_IDX
- REG_RXR_BASE_ADDRESS
- REG_RXSB
- REG_RXSR
- REG_RXSRAM_CTL
- REG_RXSTA_CLEARALL
- REG_RXSTA_GET_AC
- REG_RXSTA_RA
- REG_RXSTA_ROI
- REG_RXSTA_RPE
- REG_RXSTSENQ
- REG_RXSTSQBADD
- REG_RXSTSQBLEN
- REG_RXSTSQCURADD
- REG_RXTIMEOUT1
- REG_RXTIMEOUT2
- REG_RXTSF_OFFSET_CCK
- REG_RXTSF_OFFSET_CCK_8723B
- REG_RXTSF_OFFSET_OFDM
- REG_RXTSF_OFFSET_OFDM_8723B
- REG_RX_AE_THRESH
- REG_RX_BAD_BYTES
- REG_RX_BASE_ADDR_HI
- REG_RX_BIST
- REG_RX_BLANK
- REG_RX_BLANK_ALIAS_READ
- REG_RX_BREAK
- REG_RX_BUF_SIZE
- REG_RX_CB_HI
- REG_RX_CB_LOW
- REG_RX_CCK
- REG_RX_CFG
- REG_RX_COMP
- REG_RX_COMP_HEAD
- REG_RX_COMP_TAIL
- REG_RX_CONFIG
- REG_RX_CONTROL
- REG_RX_CTRL_FIFO_ADDR
- REG_RX_CTRL_FIFO_DATA_HI
- REG_RX_CTRL_FIFO_DATA_LOW
- REG_RX_CTRL_FIFO_DATA_MID
- REG_RX_CTRL_FIFO_READ_PTR
- REG_RX_CTRL_FIFO_WRITE_PTR
- REG_RX_DB_HI
- REG_RX_DB_LOW
- REG_RX_DEBUG
- REG_RX_DESA
- REG_RX_DESA_8723B
- REG_RX_DLK_TIME
- REG_RX_DLK_TIME_8723B
- REG_RX_DMA_CTRL_8723B
- REG_RX_DRVINFO_SZ
- REG_RX_DRVINFO_SZ_8723B
- REG_RX_FIFO
- REG_RX_FIFO_ADDR
- REG_RX_FIFO_CTRL
- REG_RX_FIFO_DATA_HI_T0
- REG_RX_FIFO_DATA_HI_T1
- REG_RX_FIFO_DATA_LOW
- REG_RX_FIFO_FULLNESS
- REG_RX_FIFO_READ_PTR
- REG_RX_FIFO_TAG
- REG_RX_FIFO_WRITE_PTR
- REG_RX_FILTER
- REG_RX_GAIN_EN
- REG_RX_HASH_TABLE
- REG_RX_HDMI_CLR_BUFFER
- REG_RX_HDMI_CTRL0
- REG_RX_HDMI_CTRL2
- REG_RX_HDMI_CTRL3
- REG_RX_HDMI_MON_PKT_HEADER1
- REG_RX_HDMI_VSIF_MHL_MON
- REG_RX_HEADER_PAGE_PTR_HI
- REG_RX_HEADER_PAGE_PTR_LOW
- REG_RX_HPD_HEAC
- REG_RX_IPP_FIFO_ADDR
- REG_RX_IPP_FIFO_DATA_HI_T0
- REG_RX_IPP_FIFO_DATA_HI_T1
- REG_RX_IPP_FIFO_DATA_LOW
- REG_RX_IPP_FIFO_READ_PTR
- REG_RX_IPP_FIFO_SHADOW_READ_PTR
- REG_RX_IPP_FIFO_SHADOW_WRITE_PTR
- REG_RX_IPP_FIFO_TAG
- REG_RX_IPP_PACKET_COUNT
- REG_RX_IQK
- REG_RX_IQK_PI_A
- REG_RX_IQK_PI_B
- REG_RX_IQK_TONE_A
- REG_RX_IQK_TONE_B
- REG_RX_KICK
- REG_RX_M
- REG_RX_MTU_PAGE_PTR_HI
- REG_RX_MTU_PAGE_PTR_LOW
- REG_RX_OFDM
- REG_RX_OK_BYTES
- REG_RX_OPTIONS_BASE
- REG_RX_OPTIONS_E2E_HOP_MASK
- REG_RX_OPTIONS_E2E_HOP_SHIFT
- REG_RX_PAGE_SIZE
- REG_RX_PAUSE_THRESH
- REG_RX_PKT_LIMIT
- REG_RX_PKT_LIMIT_8723B
- REG_RX_POLL_DEMAND
- REG_RX_POWER_AFTER_IQK_A
- REG_RX_POWER_AFTER_IQK_A_2
- REG_RX_POWER_AFTER_IQK_B
- REG_RX_POWER_AFTER_IQK_B_2
- REG_RX_POWER_BEFORE_IQK_A
- REG_RX_POWER_BEFORE_IQK_A_2
- REG_RX_POWER_BEFORE_IQK_B
- REG_RX_POWER_BEFORE_IQK_B_2
- REG_RX_RED
- REG_RX_RING_BASE
- REG_RX_RXBD_NUM
- REG_RX_TABLE_ADDR
- REG_RX_TABLE_DATA_HI
- REG_RX_TABLE_DATA_LOW
- REG_RX_TABLE_DATA_MID
- REG_RX_TO_RX
- REG_RX_WAIT_CCA
- REG_RX_WAIT_RIFS
- REG_RX_WORK_DMA_PTR_HI
- REG_RX_WORK_DMA_PTR_LOW
- REG_RX_XGMII_PROT_ERR
- REG_R_AVE
- REG_R_CONFIG
- REG_S
- REG_S0S1_PATH_SWITCH
- REG_SADDR
- REG_SADDRMASK
- REG_SADRH
- REG_SADRL
- REG_SAFE_BM_SIZE
- REG_SAMPLE_RATE
- REG_SAMPLE_RATE_INQUIRY
- REG_SAMPLE_TIME
- REG_SAMSUNG_ELECTRO
- REG_SAMSUNG_OPTICS
- REG_SAMSUNG_TECHWIN
- REG_SAR
- REG_SAT
- REG_SATURATION
- REG_SATURN_PCFG
- REG_SBD
- REG_SBEC
- REG_SC
- REG_SCALAR
- REG_SCALE_M
- REG_SCALING_MODE
- REG_SCALING_XSC
- REG_SCALING_YSC
- REG_SCART_DELAY
- REG_SCENE_AGAINST_LIGHT
- REG_SCENE_BEACH_SNOW
- REG_SCENE_CANDLE
- REG_SCENE_DAWN_DUSK
- REG_SCENE_FALL
- REG_SCENE_FIRE
- REG_SCENE_LANDSCAPE
- REG_SCENE_NIGHT
- REG_SCENE_NORMAL
- REG_SCENE_PARTY_INDOOR
- REG_SCENE_PORTRAIT
- REG_SCENE_SPORTS
- REG_SCENE_SUNSET
- REG_SCENE_TEXT
- REG_SCH_TXCMD
- REG_SCH_TXCMD_8723B
- REG_SCH_TX_CMD
- REG_SCLK_DEEP_SLEEP_EXIT__REG_sclk_deep_sleep_exit_MASK
- REG_SCLK_DEEP_SLEEP_EXIT__REG_sclk_deep_sleep_exit__SHIFT
- REG_SCOTRK
- REG_SCSI_DATA
- REG_SCSI_DATA_NOACK
- REG_SC_CHIP_ID_H
- REG_SC_CHIP_ID_L
- REG_SC_CLKRST0
- REG_SC_CLKRST1
- REG_SC_CLKRST2
- REG_SC_CLKRST3
- REG_SC_CNT
- REG_SC_CTRL
- REG_SC_CTRL_MODE
- REG_SC_PLL_CTRL0
- REG_SC_PLL_CTRL1
- REG_SC_PLL_CTRL2
- REG_SC_PLL_CTRL3
- REG_SC_PWC
- REG_SC_SCCB_ID
- REG_SC_SUB_ID
- REG_SDID
- REG_SDIO0XIN_CLKCTL
- REG_SDIO1XIN_CLKCTL
- REG_SDIO_CTRL
- REG_SDIO_CTRL_8723B
- REG_SDIO_DLLMST_CLKCTL
- REG_SD_STOP_SDCLK_CFG
- REG_SE
- REG_SECCFG
- REG_SECCFG_8723B
- REG_SECCON0
- REG_SECCON1
- REG_SECCR2
- REG_SECHI
- REG_SECLO
- REG_SECONDARY_CCA_CTRL
- REG_SECONDARY_CCA_CTRL_8723B
- REG_SECONDS
- REG_SECONDS_OS
- REG_SECONDS_REG
- REG_SECOND_LOCALBUS_END
- REG_SECOND_LOCALBUS_START
- REG_SECOND_SCREEN_DRIVE_POS
- REG_SECR
- REG_SECTOR_COUNT
- REG_SECTOR_NUMBER
- REG_SECURITY_CFG
- REG_SEEN
- REG_SEG_SIZE
- REG_SELECT_BANK
- REG_SELFCTL
- REG_SELFCTL_RESET
- REG_SEL_CLK
- REG_SEPARATOR_LINE
- REG_SERDES
- REG_SERDES_COM_CNT
- REG_SERDES_CONF
- REG_SERDES_LOCK
- REG_SERDES_STAT
- REG_SERDES_TEST
- REG_SERIALIZER
- REG_SERIAL_NO
- REG_SERIAL_NUMBER
- REG_SER_CONTROL
- REG_SET
- REG_SETGPIODATAOUT1
- REG_SETGPIODATAOUT2
- REG_SETGPIODATAOUT3
- REG_SET_10
- REG_SET_2
- REG_SET_3
- REG_SET_4
- REG_SET_5
- REG_SET_6
- REG_SET_7
- REG_SET_8
- REG_SET_9
- REG_SET_AND_CHECK
- REG_SET_BIT
- REG_SET_FIELD
- REG_SET_HOST_INT
- REG_SET_MASK
- REG_SET_N
- REG_SET_PAGE
- REG_SET_SEEN
- REG_SFDR_CFG
- REG_SFDR_IN_USE
- REG_SFD_15_4
- REG_SFPB_GPREG
- REG_SF_BGAIN
- REG_SF_BGAIN_CHG
- REG_SF_FLICKER_QUANT
- REG_SF_FLICKER_QUANT_CHG
- REG_SF_GGAIN
- REG_SF_GGAIN_CHG
- REG_SF_RGAIN
- REG_SF_RGAIN_CHG
- REG_SF_USR_EXPOSURE_CHG
- REG_SF_USR_EXPOSURE_H
- REG_SF_USR_EXPOSURE_L
- REG_SF_USR_TOT_GAIN
- REG_SF_USR_TOT_GAIN_CHG
- REG_SF_WBGAIN_CHG
- REG_SGCR1
- REG_SGCR2
- REG_SGCR3
- REG_SGNSET
- REG_SHADOW_START
- REG_SHARPENMT_OFFSET1
- REG_SHARPENMT_OFFSET2
- REG_SHARPENMT_THRESH1
- REG_SHARPENMT_THRESH2
- REG_SHARPEN_THRESH1
- REG_SHARPEN_THRESH2
- REG_SHORTS
- REG_SHORT_ADDR_0
- REG_SHORT_ADDR_1
- REG_SHUTDOWN
- REG_SHUTDOWN_HIGH
- REG_SHUTDOWN_LOW
- REG_SID
- REG_SIFS
- REG_SIFS_CCK
- REG_SIFS_CTX
- REG_SIFS_CTX_8723B
- REG_SIFS_OFDM
- REG_SIFS_TRX
- REG_SIFS_TRX_8723B
- REG_SINGLE_AMPDU_CTRL
- REG_SIZE
- REG_SI_TRANSFER_SEL
- REG_SKIP
- REG_SLAVE
- REG_SLAVE1
- REG_SLAVE2
- REG_SLAVE3
- REG_SLAVE_ADDR
- REG_SLAVE_CR
- REG_SLAVE_DR
- REG_SLAVE_IMR
- REG_SLAVE_ISR
- REG_SLAVE_SR
- REG_SLAVE_TR
- REG_SLCS
- REG_SLEEP
- REG_SLOT
- REG_SLOT_8723B
- REG_SLPACK
- REG_SLPCAL0
- REG_SLPCAL1
- REG_SLPCAL2
- REG_SLPCON0
- REG_SLPCON1
- REG_SLV_MEM_DATA
- REG_SLV_REG_DATA
- REG_SM0CFG2_REG
- REG_SM0CTL0_REG
- REG_SM0CTL1_REG
- REG_SM0D0_REG
- REG_SM0D1_REG
- REG_SMARTFAN_EN
- REG_SMB_STAT_TIMER
- REG_SMB_TIMER
- REG_SMI_SECUR_CON_ADDR
- REG_SMI_SECUR_CON_BASE
- REG_SMI_SECUR_CON_OFFSET
- REG_SMPS_OFFSET
- REG_SMSTA
- REG_SND_PTCL_CTRL
- REG_SND_PTCL_CTRL_8723B
- REG_SOF
- REG_SOFTRESET
- REG_SOFTRST
- REG_SOFTWARE_RESET
- REG_SOFTWARE_STANDBY
- REG_SP
- REG_SPACE_SIZE
- REG_SPCB
- REG_SPCC
- REG_SPCD
- REG_SPCE
- REG_SPDIF_SCR
- REG_SPDIF_SIC
- REG_SPDIF_SIE
- REG_SPDIF_SIS
- REG_SPDIF_SRCD
- REG_SPDIF_SRCSH
- REG_SPDIF_SRCSL
- REG_SPDIF_SRFM
- REG_SPDIF_SRL
- REG_SPDIF_SRPC
- REG_SPDIF_SRQ
- REG_SPDIF_SRR
- REG_SPDIF_SRU
- REG_SPDIF_STC
- REG_SPDIF_STCSCH
- REG_SPDIF_STCSCL
- REG_SPDIF_STL
- REG_SPDIF_STR
- REG_SPEC_SIFS
- REG_SPEC_SIFS_8723B
- REG_SPHY_CNTRL
- REG_SPI4_DBG_CNT
- REG_SPI4_DBG_GRANT
- REG_SPI4_DBG_INH
- REG_SPI4_DBG_SETUP
- REG_SPI4_DBG_STATUS
- REG_SPI4_DESKEW
- REG_SPI4_EGR_SETUP0
- REG_SPI4_ING_SETUP0
- REG_SPI4_ING_SETUP1
- REG_SPI4_ING_SETUP2
- REG_SPI4_MISC
- REG_SPI4_STATUS
- REG_SPI4_STICKY
- REG_SPI4_TEST
- REG_SPIBURSTCNT
- REG_SPIBURSTSTAT
- REG_SPID
- REG_SPI_ADDR
- REG_SPI_DATA
- REG_SPI_FLASH_CONFIG
- REG_SPI_FLASH_CTRL
- REG_SPI_FLASH_OP_CHIP_ERASE
- REG_SPI_FLASH_OP_PROGRAM
- REG_SPI_FLASH_OP_RDID
- REG_SPI_FLASH_OP_RDSR
- REG_SPI_FLASH_OP_READ
- REG_SPI_FLASH_OP_SC_ERASE
- REG_SPI_FLASH_OP_WREN
- REG_SPI_FLASH_OP_WRSR
- REG_SPS0_CTRL
- REG_SPS0_CTRL_6
- REG_SPS0_CTRL_8723B
- REG_SPS_OCP_CFG
- REG_SPS_OCP_CFG_8723B
- REG_SR
- REG_SRAM_ADR
- REG_SRAM_DATA_0
- REG_SRAM_DATA_1
- REG_SRAM_DATA_2
- REG_SRAM_DATA_3
- REG_SRAM_DATA_BLK_TYPE
- REG_SRAM_PKTH_ADDR
- REG_SRAM_RD_STRB
- REG_SRAM_RFD0_INFO
- REG_SRAM_RFD1_INFO
- REG_SRAM_RFD2_INFO
- REG_SRAM_RFD3_INFO
- REG_SRAM_RFD_ADDR
- REG_SRAM_RFD_LEN
- REG_SRAM_RRD_ADDR
- REG_SRAM_RRD_LEN
- REG_SRAM_RXF_ADDR
- REG_SRAM_RXF_LEN
- REG_SRAM_RXRAM_END
- REG_SRAM_TCPH_ADDR
- REG_SRAM_TCPH_PATH_ADDR
- REG_SRAM_TPD_ADDR
- REG_SRAM_TPD_LEN
- REG_SRAM_TRD_ADDR
- REG_SRAM_TRD_LEN
- REG_SRAM_TXF_ADDR
- REG_SRAM_TXF_LEN
- REG_SRAM_TXRAM_END
- REG_SRAM_WR_STRB
- REG_SRCIDR
- REG_SR_BASICCAN_INITIAL
- REG_SR_PELICAN_INITIAL
- REG_SSI_SACADD
- REG_SSI_SACCDIS
- REG_SSI_SACCEN
- REG_SSI_SACCST
- REG_SSI_SACDAT
- REG_SSI_SACNT
- REG_SSI_SATAG
- REG_SSI_SCR
- REG_SSI_SFCSR
- REG_SSI_SIER
- REG_SSI_SISR
- REG_SSI_SOR
- REG_SSI_SRCCR
- REG_SSI_SRCR
- REG_SSI_SRMSK
- REG_SSI_SRX0
- REG_SSI_SRX1
- REG_SSI_STCCR
- REG_SSI_STCR
- REG_SSI_STMSK
- REG_SSI_STR
- REG_SSI_STX0
- REG_SSI_STX1
- REG_SSI_SxCCR
- REG_SSI_SxCR
- REG_SSI_SxMSK
- REG_STANDBY
- REG_STANDBY_SOFT_RST
- REG_START
- REG_START_ARM_BOOT
- REG_START_INIT
- REG_START_OSCILLATION
- REG_START_SYNCHRO
- REG_STAT
- REG_STATE
- REG_STATE_BUSHOLD
- REG_STATE_BUSY
- REG_STATE_MASTER
- REG_STATE_NACKED
- REG_STATE_NEW
- REG_STATE_REGISTERED
- REG_STATE_STATE_ADDR
- REG_STATE_STATE_ADDRACK
- REG_STATE_STATE_DATA
- REG_STATE_STATE_DATAACK
- REG_STATE_STATE_IDLE
- REG_STATE_STATE_START
- REG_STATE_STATE_WAIT
- REG_STATE_STATE__MASK
- REG_STATE_TRANSMITTER
- REG_STATE_UNREGISTERED
- REG_STATE_UNUSED
- REG_STATUS
- REG_STATUS1
- REG_STATUS2
- REG_STATUS4
- REG_STATUS_1
- REG_STATUS_AES_1
- REG_STATUS_AES_2
- REG_STATUS_AES_3
- REG_STATUS_AES_4
- REG_STATUS_AES_SYNC
- REG_STATUS_BOOT_DELAY_COUNT_DONE
- REG_STATUS_BOOT_GPIO_SETTING_OK
- REG_STATUS_BOOT_INTERRUPTS_EN
- REG_STATUS_BOOT_I_PLL_DONE
- REG_STATUS_BOOT_I_PLL_LOCKTIME_DONE
- REG_STATUS_BOOT_PLL_INIT_OK
- REG_STATUS_BOOT_READ_CAL_DATA_OK
- REG_STATUS_BOOT_R_PLL_DONE
- REG_STATUS_BOOT_R_PLL_LOCKTIME_DONE
- REG_STATUS_BOOT_SENSOR_INIT_OK
- REG_STATUS_BOOT_SRAM_TIMING_OK
- REG_STATUS_BOOT_STABLE_AE_AWB_OK
- REG_STATUS_BOOT_SUB_MAIN_ENTER
- REG_STATUS_BUSY
- REG_STATUS_CURRENT
- REG_STATUS_EXCEPTION_OCCURED
- REG_STATUS_IDLE
- REG_STATUS_INTER_SYNC
- REG_STATUS_ISP_COMMAND_COMPLETED
- REG_STATUS_LOCK
- REG_STATUS_OPTIONS
- REG_STATUS_OPT_ANALOG_BOARD
- REG_STATUS_OPT_COMPANION_MASK
- REG_STATUS_OPT_DAUGHTER_MASK
- REG_STATUS_OPT_NO_COMPANION
- REG_STATUS_OPT_NO_DAUGHTER
- REG_STATUS_OPT_NO_VIDEO_SIGNAL
- REG_STATUS_PABORT
- REG_STATUS_PACK
- REG_STATUS_PCONT
- REG_STATUS_PNACK
- REG_STATUS_PSTART
- REG_STATUS_PSTOP
- REG_STATUS_REQUEST
- REG_STATUS_RXDATAV
- REG_STATUS_SYNC
- REG_STATUS_SYNC_128000
- REG_STATUS_SYNC_176400
- REG_STATUS_SYNC_192000
- REG_STATUS_SYNC_32000
- REG_STATUS_SYNC_44100
- REG_STATUS_SYNC_48000
- REG_STATUS_SYNC_64000
- REG_STATUS_SYNC_88200
- REG_STATUS_SYNC_96000
- REG_STATUS_TXBL
- REG_STATUS_TXC
- REG_STATUS_TXENS
- REG_STATUS_WORD_CLOCK
- REG_STAT_BUSY
- REG_STAT_FAULT
- REG_STAT_FWVER
- REG_STAT_RPT
- REG_STAT_STALE
- REG_STAT_STICKY10G
- REG_STAT_TGOOD
- REG_STBC_SETTING
- REG_STBC_SETTING_8723B
- REG_STCH
- REG_STCL
- REG_STCM
- REG_STEPCONFIG
- REG_STEPDELAY
- REG_STH_GERR
- REG_STH_LENGTH
- REG_STH_OFFSET
- REG_STH_STHCAP0
- REG_STH_STHCAP1
- REG_STH_TRIG
- REG_STH_TRIG_TS
- REG_STH_XSYNC
- REG_STH_XSYNC_TS
- REG_STICKY_RX
- REG_STICKY_TX
- REG_STICK_BIT
- REG_STIM
- REG_STOPBITS
- REG_STP
- REG_STRENGTH
- REG_STRENGTH_CARRIER
- REG_STRENGTH_MASK
- REG_STRIDE
- REG_STROBE_CFG
- REG_STROBE_SRC
- REG_STRUCT_INIT
- REG_STR_SIZE
- REG_STS_CMD
- REG_STS_RXD_OV
- REG_STS_RXS_OV
- REG_STS_RX_FILTER
- REG_STS_RX_PAUSE
- REG_ST_ABCR
- REG_ST_ABIMSC
- REG_ST_DMAWM
- REG_ST_ITCR
- REG_ST_ITIP
- REG_ST_TIMEOUT
- REG_ST_XFCR
- REG_ST_XOFF1
- REG_ST_XOFF2
- REG_ST_XON1
- REG_ST_XON2
- REG_SUBU
- REG_SUPPLIES2
- REG_SUS_CLOCK_GOOD
- REG_SUS_SET_RGB0
- REG_SUS_SET_RGB1
- REG_SUS_SET_RGB2
- REG_SUS_SET_RGB3
- REG_SUS_SET_RGB4
- REG_SUS_STATUS
- REG_SVC_MODE
- REG_SWAP_I_Q
- REG_SWEEP_STEP
- REG_SWITCH_CNTRL
- REG_SWITCH_CTRL_14
- REG_SWITCH_REG_MAX
- REG_SWITCH_REVISION
- REG_SWITCH_STATUS
- REG_SW_ALU_CTRL__4
- REG_SW_ALU_INDEX_0
- REG_SW_ALU_INDEX_1
- REG_SW_ALU_STAT_CTRL__4
- REG_SW_ALU_VAL_A
- REG_SW_ALU_VAL_B
- REG_SW_ALU_VAL_C
- REG_SW_ALU_VAL_D
- REG_SW_AMPDU_BURST_MODE_CTRL
- REG_SW_APB_TIMEOUT_ADDR__4
- REG_SW_CLASS_D_IP_CTRL__4
- REG_SW_CTRL_0
- REG_SW_CTRL_1
- REG_SW_CTRL_10
- REG_SW_CTRL_11
- REG_SW_CTRL_12
- REG_SW_CTRL_13
- REG_SW_CTRL_15
- REG_SW_CTRL_16
- REG_SW_CTRL_17
- REG_SW_CTRL_18
- REG_SW_CTRL_19
- REG_SW_CTRL_2
- REG_SW_CTRL_20
- REG_SW_CTRL_21
- REG_SW_CTRL_3
- REG_SW_CTRL_4
- REG_SW_CTRL_5
- REG_SW_CTRL_6
- REG_SW_CTRL_9
- REG_SW_EEE_QM_CTRL__2
- REG_SW_EEE_TXQ_WAIT_TIME__2
- REG_SW_GENERIC0
- REG_SW_GENERIC3
- REG_SW_GLOBAL_OUTPUT_CTRL__1
- REG_SW_GLOBAL_SERIAL_CTRL_0
- REG_SW_HSR_TPID__2
- REG_SW_IBA_RESULT__4
- REG_SW_IBA_STATES__4
- REG_SW_IBA_STATUS__4
- REG_SW_IBA_SYNC__1
- REG_SW_IBA__4
- REG_SW_ID_AND_ENABLE
- REG_SW_INT_MASK__4
- REG_SW_INT_STATUS__4
- REG_SW_IO_STRENGTH__1
- REG_SW_ISP_TPID__2
- REG_SW_LOAD_COMPLETE
- REG_SW_LUE_CTRL_0
- REG_SW_LUE_CTRL_1
- REG_SW_LUE_CTRL_2
- REG_SW_LUE_CTRL_3
- REG_SW_LUE_INDEX_0__2
- REG_SW_LUE_INDEX_1__2
- REG_SW_LUE_INDEX_2__2
- REG_SW_LUE_INT_ENABLE
- REG_SW_LUE_INT_STATUS
- REG_SW_LUE_UNK_MCAST_CTRL__4
- REG_SW_LUE_UNK_UCAST_CTRL__4
- REG_SW_LUE_UNK_VID_CTRL__4
- REG_SW_MAC_802_1P_MAP_0
- REG_SW_MAC_802_1P_MAP_1
- REG_SW_MAC_802_1P_MAP_2
- REG_SW_MAC_802_1P_MAP_3
- REG_SW_MAC_ADDR_0
- REG_SW_MAC_ADDR_1
- REG_SW_MAC_ADDR_2
- REG_SW_MAC_ADDR_3
- REG_SW_MAC_ADDR_4
- REG_SW_MAC_ADDR_5
- REG_SW_MAC_CTRL_0
- REG_SW_MAC_CTRL_1
- REG_SW_MAC_CTRL_2
- REG_SW_MAC_CTRL_3
- REG_SW_MAC_CTRL_4
- REG_SW_MAC_CTRL_5
- REG_SW_MAC_CTRL_6
- REG_SW_MAC_ISP_CTRL
- REG_SW_MAC_TOS_CTRL
- REG_SW_MAC_TOS_PRIO_0
- REG_SW_MAC_TOS_PRIO_1
- REG_SW_MAC_TOS_PRIO_10
- REG_SW_MAC_TOS_PRIO_11
- REG_SW_MAC_TOS_PRIO_12
- REG_SW_MAC_TOS_PRIO_13
- REG_SW_MAC_TOS_PRIO_14
- REG_SW_MAC_TOS_PRIO_15
- REG_SW_MAC_TOS_PRIO_16
- REG_SW_MAC_TOS_PRIO_17
- REG_SW_MAC_TOS_PRIO_18
- REG_SW_MAC_TOS_PRIO_19
- REG_SW_MAC_TOS_PRIO_2
- REG_SW_MAC_TOS_PRIO_20
- REG_SW_MAC_TOS_PRIO_21
- REG_SW_MAC_TOS_PRIO_22
- REG_SW_MAC_TOS_PRIO_23
- REG_SW_MAC_TOS_PRIO_24
- REG_SW_MAC_TOS_PRIO_25
- REG_SW_MAC_TOS_PRIO_26
- REG_SW_MAC_TOS_PRIO_27
- REG_SW_MAC_TOS_PRIO_28
- REG_SW_MAC_TOS_PRIO_29
- REG_SW_MAC_TOS_PRIO_3
- REG_SW_MAC_TOS_PRIO_30
- REG_SW_MAC_TOS_PRIO_31
- REG_SW_MAC_TOS_PRIO_4
- REG_SW_MAC_TOS_PRIO_5
- REG_SW_MAC_TOS_PRIO_6
- REG_SW_MAC_TOS_PRIO_7
- REG_SW_MAC_TOS_PRIO_8
- REG_SW_MAC_TOS_PRIO_9
- REG_SW_MRI_CTRL_0
- REG_SW_MRI_CTRL_8
- REG_SW_MTU__2
- REG_SW_OPERATION
- REG_SW_OUT
- REG_SW_PHY_INT_ENABLE
- REG_SW_PHY_INT_STATUS
- REG_SW_PME_CTRL
- REG_SW_PORT_INT_MASK__4
- REG_SW_PORT_INT_STATUS__4
- REG_SW_POWER_MANAGEMENT_CTRL
- REG_SW_QM_CTRL__4
- REG_SW_RESET
- REG_SW_UNK_IP_MCAST_CTRL
- REG_SW_UNK_MCAST_CTRL
- REG_SW_UNK_UCAST_CTRL
- REG_SW_UNK_VID_CTRL
- REG_SW_VLAN_CTRL
- REG_SW_VLAN_ENTRY_INDEX__2
- REG_SW_VLAN_ENTRY_PORTS__4
- REG_SW_VLAN_ENTRY_UNTAG__4
- REG_SW_VLAN_ENTRY__4
- REG_SYMTICKH
- REG_SYMTICKL
- REG_SYNCVALUE1
- REG_SYNCVALUE2
- REG_SYNCVALUE3
- REG_SYNCVALUE4
- REG_SYNCVALUE5
- REG_SYNCVALUE6
- REG_SYNCVALUE7
- REG_SYNCVALUE8
- REG_SYNC_CONFIG
- REG_SYNC_CONTROL
- REG_SYNC_WORD0
- REG_SYNC_WORD1
- REG_SYNC_WORD2
- REG_SYNT
- REG_SYNT_CAL
- REG_SYSCALL
- REG_SYSINIT
- REG_SYSPLLCTL0
- REG_SYSPLLCTL4
- REG_SYSTEM_ON_CTRL
- REG_SYSTEM_R
- REG_SYSTEM_SETUP
- REG_SYSTEM_SETUP_OSC_ON
- REG_SYSTEM_W
- REG_SYS_CFG
- REG_SYS_CFG1
- REG_SYS_CFG1_8723B
- REG_SYS_CFG2
- REG_SYS_CFG_8723B
- REG_SYS_CLKR
- REG_SYS_CLKR_8723B
- REG_SYS_CLK_CTRL
- REG_SYS_CLK_SELECT
- REG_SYS_CTRL1
- REG_SYS_EEPROM_CTRL
- REG_SYS_FUNC
- REG_SYS_FUNC_EN
- REG_SYS_FUNC_EN_8723B
- REG_SYS_ISO_CTRL
- REG_SYS_ISO_CTRL_8723B
- REG_SYS_PW_CTRL
- REG_SYS_SDIO_CTRL
- REG_SYS_STATUS1
- REG_SYS_STATUS2
- REG_SYS_SWR_CTRL1
- REG_SYS_SWR_CTRL2
- REG_SYS_SWR_CTRL3
- REG_SZ
- REG_T0
- REG_T1
- REG_T2
- REG_T2T_SIFS
- REG_TA
- REG_TABLE_END
- REG_TABLE_LEN
- REG_TACH_BASE
- REG_TACH_MIN_BASE
- REG_TAIL
- REG_TB
- REG_TBG_CNTRL_0
- REG_TBG_CNTRL_1
- REG_TBI_CONFIG
- REG_TBI_STATUS
- REG_TBTT_PROHIBIT
- REG_TBTT_PROHIBIT_8723B
- REG_TC0_CTRL
- REG_TC0_CTRL_8723B
- REG_TC1_CTRL
- REG_TC1_CTRL_8723B
- REG_TC2_CTRL
- REG_TC2_CTRL_8723B
- REG_TC3_CTRL
- REG_TC3_CTRL_8723B
- REG_TC4_CTRL
- REG_TC4_CTRL_8723B
- REG_TCFG0
- REG_TCFG1
- REG_TCMPB
- REG_TCNTB
- REG_TCON
- REG_TCR
- REG_TCR_8723B
- REG_TCUNIT_BASE
- REG_TCUNIT_BASE_8723B
- REG_TDAT
- REG_TDECTRL
- REG_TDMLLCTL
- REG_TDP_LIMIT3
- REG_TDP_RUNNING_AVERAGE
- REG_TEMP
- REG_TEMP1
- REG_TEMP2
- REG_TEMPERATURE
- REG_TEMPERATURE_BIAS
- REG_TEMPERATURE_VALUE
- REG_TEMP_BASE
- REG_TEMP_LSB
- REG_TEMP_MAX_ALARM
- REG_TEMP_MAX_BASE
- REG_TEMP_MIN_ALARM
- REG_TEMP_MIN_BASE
- REG_TEMP_OFFSET_BASE
- REG_TEMP_PECI_LSB
- REG_TEMP_THERM_BASE
- REG_TEMP_TMIN_BASE
- REG_TEMP_TRANGE_BASE
- REG_TERM
- REG_TEST
- REG_TESTDAGC
- REG_TESTMODE
- REG_TESTPA1
- REG_TESTPA2
- REG_TEST_ADDR_MASK
- REG_TEST_AUDIO_FREQ
- REG_TEST_CLK
- REG_TEST_DATA_IN_MASK
- REG_TEST_DATA_OUT_MASK
- REG_TEST_DATA_OUT_SEL
- REG_TEST_DISABLE_ID_PULLUP
- REG_TEST_EN_MASK
- REG_TEST_MODE
- REG_TEST_NCTS_CTRL
- REG_TEST_SEED
- REG_TEST_SIE_CHIRP_K
- REG_TEST_SIE_MAC_ADDR
- REG_TEST_SIE_OPTIONAL
- REG_TEST_SIE_PHY
- REG_TEST_SIE_PID
- REG_TEST_SIE_STRING
- REG_TEST_SIE_VID
- REG_TEST_TXCTRL
- REG_TEST_USB_TXQS
- REG_TEST_VA_TEST_EN_B_MASK
- REG_TE_EN
- REG_THROT
- REG_THRUPUT_MON_CTRL
- REG_THSCR
- REG_THSSR
- REG_TIMB_FIFO
- REG_TIMB_IAR
- REG_TIMB_IER
- REG_TIMB_ISR
- REG_TIMB_RST
- REG_TIMEOUT
- REG_TIMER0
- REG_TIMER0_8723B
- REG_TIMER0_SRC_SEL
- REG_TIMER1
- REG_TIMER1_8723B
- REG_TIMER_D
- REG_TIMER_RETRY_MASK
- REG_TIMER_RETRY_SHIFT
- REG_TIMER_TRDY_MASK
- REG_TIMER_TRDY_SHIFT
- REG_TIME_TO_EMPTY
- REG_TIME_TO_FULL
- REG_TIMING_CTRL
- REG_TIMING_DVPHO_H
- REG_TIMING_DVPHO_L
- REG_TIMING_DVPVO_H
- REG_TIMING_DVPVO_L
- REG_TIMING_HOFFS_H
- REG_TIMING_HOFFS_L
- REG_TIMING_HORIZ_FORMAT
- REG_TIMING_HS_H
- REG_TIMING_HS_L
- REG_TIMING_HTS_H
- REG_TIMING_HTS_L
- REG_TIMING_HW_H
- REG_TIMING_HW_L
- REG_TIMING_VERT_FORMAT
- REG_TIMING_VH_H
- REG_TIMING_VH_L
- REG_TIMING_VOFFS_H
- REG_TIMING_VOFFS_L
- REG_TIMING_VS_H
- REG_TIMING_VS_L
- REG_TIMING_VTS_H
- REG_TIMING_VTS_L
- REG_TIMING_XINC
- REG_TIMING_YINC
- REG_TINT_CSTAT
- REG_TINT_TPD_THRESH
- REG_TLB_INVALIDATE
- REG_TMDS0_CCTRL1
- REG_TMDS_CCTRL
- REG_TMDS_CH_EN
- REG_TMDS_CLK_EN
- REG_TMDS_CSTAT_P3
- REG_TMDS_CTRL4
- REG_TMOUT_INT
- REG_TMR_CFG0
- REG_TMR_CFG1
- REG_TMR_CTRL
- REG_TMR_RLD0
- REG_TMR_RLD1
- REG_TOG
- REG_TOK_LIST0
- REG_TOK_LIST1
- REG_TOK_RDATA0
- REG_TOK_RDATA1
- REG_TOK_WDATA0
- REG_TOK_WDATA1
- REG_TOP_BOTTOM
- REG_TORCH_BR
- REG_TORCH_CFG
- REG_TORCH_CTRL
- REG_TORCH_TIME
- REG_TOS_PRIO_CTRL_0
- REG_TOS_PRIO_CTRL_1
- REG_TOS_PRIO_CTRL_10
- REG_TOS_PRIO_CTRL_11
- REG_TOS_PRIO_CTRL_12
- REG_TOS_PRIO_CTRL_13
- REG_TOS_PRIO_CTRL_14
- REG_TOS_PRIO_CTRL_15
- REG_TOS_PRIO_CTRL_2
- REG_TOS_PRIO_CTRL_3
- REG_TOS_PRIO_CTRL_4
- REG_TOS_PRIO_CTRL_5
- REG_TOS_PRIO_CTRL_6
- REG_TOS_PRIO_CTRL_7
- REG_TOS_PRIO_CTRL_8
- REG_TOS_PRIO_CTRL_9
- REG_TOTAL_NUM
- REG_TOUCHDATA
- REG_TO_DCPU_MBOX
- REG_TO_HOST_MBOX
- REG_TO_PTGS
- REG_TO_SIGNED
- REG_TPCHK_UP0
- REG_TPCHK_UP1
- REG_TPD_BASE_ADDR_LO
- REG_TPD_CONS_IDX
- REG_TPD_IDX
- REG_TPD_PRI0_ADDR_LO
- REG_TPD_PRI0_CIDX
- REG_TPD_PRI0_PIDX
- REG_TPD_PRI1_ADDR_LO
- REG_TPD_PRI1_CIDX
- REG_TPD_PRI1_PIDX
- REG_TPD_RING_SIZE
- REG_TPERR_CNT
- REG_TPGEN_UP0
- REG_TPGEN_UP1
- REG_TPI_AVI_CHSUM
- REG_TPI_BSTATUS1
- REG_TPI_BSTATUS2
- REG_TPI_CBUS_START
- REG_TPI_COPP_DATA1
- REG_TPI_COPP_DATA2
- REG_TPI_DS_BCAPS
- REG_TPI_DTD_B2
- REG_TPI_HW_OPT3
- REG_TPI_INFO_B0
- REG_TPI_INFO_FSEL
- REG_TPI_INPUT
- REG_TPI_INTR_EN
- REG_TPI_INTR_ST0
- REG_TPI_OUTPUT
- REG_TPI_SC
- REG_TPSAM_P0
- REG_TPSAM_P1
- REG_TPS_CONFIG
- REG_TPS_MANUAL
- REG_TR
- REG_TRACK_FILTER
- REG_TRAFFIC_SHAPER_BUCKET
- REG_TRAFFIC_SHAPER_CONTROL
- REG_TRANSLATION_ENABLE
- REG_TRANSMITPTR
- REG_TRGMIICK_EN
- REG_TRIG
- REG_TRIG_CTRL__4
- REG_TRIG_CYCLE_CNT
- REG_TRIG_CYCLE_WIDTH
- REG_TRIG_ITERATE_TIME
- REG_TRIG_PULSE_WIDTH__4
- REG_TRIG_RRD_THRESH
- REG_TRIG_RXTIMER
- REG_TRIG_TARGET_NANOSEC
- REG_TRIG_TARGET_SEC
- REG_TRIG_TPD_THRESH
- REG_TRIG_TXTIMER
- REG_TRISGPIO
- REG_TRSW
- REG_TRXCTRL
- REG_TRXDMA_CTRL
- REG_TRXDMA_CTRL_8723B
- REG_TRXFF_BNDY
- REG_TRXFF_BNDY_8723B
- REG_TRXFF_STATUS
- REG_TRXFF_STATUS_8723B
- REG_TRXHSICNUMS
- REG_TRXINTH
- REG_TRXINTL
- REG_TRXINTMH
- REG_TRXPTCL_CTL
- REG_TRXPTCL_CTL_8723B
- REG_TRXSPINUMS
- REG_TRXSTA2
- REG_TRXTOTNUMS
- REG_TSCR
- REG_TSCTRL
- REG_TSCU_LENGTH
- REG_TSCU_OFFSET
- REG_TSCU_TSCUSTAT
- REG_TSCU_TSUCTRL
- REG_TSC_BASIC_SETING
- REG_TSC_DEBUG_MODE
- REG_TSC_DEBUG_MODE2
- REG_TSC_FLOW_CONTROL
- REG_TSC_INT_EN
- REG_TSC_INT_SIG_EN
- REG_TSC_INT_STATUS
- REG_TSC_MEASURE_VALUE
- REG_TSC_PRE_CHARGE_TIME
- REG_TSFSC
- REG_TSFTIMER_HCI
- REG_TSFTR
- REG_TSFTR1
- REG_TSFTR_8723B
- REG_TSFTR_SYN_OFFSET
- REG_TSLB
- REG_TSPORT_RESET
- REG_TSTHRCATA
- REG_TSTHRHI
- REG_TSTHRLO
- REG_TSTHRRPEX
- REG_TSTHRRQPI
- REG_TSTIMER
- REG_TS_CLK_FREERUN
- REG_TS_CLK_MODE
- REG_TS_CTRL_STAT__4
- REG_TS_DATA_MODE
- REG_TS_ERRBIT_USE
- REG_TS_EVENT_0_NANOSEC
- REG_TS_EVENT_0_SEC
- REG_TS_EVENT_0_SUB_NANOSEC
- REG_TS_EVENT_1_NANOSEC
- REG_TS_EVENT_1_SEC
- REG_TS_EVENT_1_SUB_NANOSEC
- REG_TS_EVENT_2_NANOSEC
- REG_TS_EVENT_2_SEC
- REG_TS_EVENT_2_SUB_NANOSEC
- REG_TS_EVENT_3_NANOSEC
- REG_TS_EVENT_3_SEC
- REG_TS_EVENT_3_SUB_NANOSEC
- REG_TS_EVENT_4_NANOSEC
- REG_TS_EVENT_4_SEC
- REG_TS_EVENT_4_SUB_NANOSEC
- REG_TS_EVENT_5_NANOSEC
- REG_TS_EVENT_5_SEC
- REG_TS_EVENT_5_SUB_NANOSEC
- REG_TS_EVENT_6_NANOSEC
- REG_TS_EVENT_6_SEC
- REG_TS_EVENT_6_SUB_NANOSEC
- REG_TS_EVENT_7_NANOSEC
- REG_TS_EVENT_7_SEC
- REG_TS_EVENT_7_SUB_NANOSEC
- REG_TS_MASK0
- REG_TS_PARALLEL_MODE
- REG_TS_PKT_LEN_204
- REG_TS_PKT_LEN_AUTO
- REG_TS_SAMPLE_EDGE
- REG_TS_SERIAL
- REG_TS_SLR
- REG_TS_TRI
- REG_TS_VALID_MODE
- REG_TTL
- REG_TTXHSICNUMS
- REG_TTXINTH
- REG_TTXINTL
- REG_TTXNUMB
- REG_TTXSPINUMS
- REG_TTXTOTNUMS
- REG_TUNE
- REG_TUNER_BASEBAND
- REG_TUNE_COMP_DIS_TUNE
- REG_TUNE_HOST_DM_PULLDOWN
- REG_TUNE_HOST_DP_PULLDOWN
- REG_TUNE_OTG_TUNE
- REG_TUNE_SQRX_TUNE_MASK
- REG_TUNE_TX_FSLS_TUNE_MASK
- REG_TUNE_TX_HSXV_TUNE_MASK
- REG_TUNE_TX_PREEMP_AMP_TUNE_MASK
- REG_TUNE_TX_PREEMP_PULSE_TUNE
- REG_TUNE_TX_RES_TUNE_MASK
- REG_TUNE_TX_RISE_TUNE_MASK
- REG_TUNE_TX_VREF_TUNE_MASK
- REG_TUP
- REG_TWSIC0
- REG_TWSIC1
- REG_TWSI_CTRL
- REG_TWSI_DEBUG
- REG_TX3
- REG_TX33
- REG_TX4
- REG_TXANT
- REG_TXANTSEG
- REG_TXBCON0
- REG_TXBCON1
- REG_TXBF_CTRL
- REG_TXBF_CTRL_8723B
- REG_TXBWCTL
- REG_TXCLK
- REG_TXCR
- REG_TXCTL
- REG_TXCTL_ENABLE
- REG_TXDATA
- REG_TXDENQ
- REG_TXDFIR
- REG_TXDFIR0
- REG_TXDMA_OFFSET_CHK
- REG_TXDMA_OFFSET_CHK_8723B
- REG_TXDMA_PQ_MAP
- REG_TXDMA_STATUS
- REG_TXDMA_STATUS_8723B
- REG_TXDQBADD
- REG_TXDQBLEN
- REG_TXDQCURADD
- REG_TXD_BASE_ADDR_LO
- REG_TXD_MEM_SIZE
- REG_TXF0
- REG_TXF1
- REG_TXF2
- REG_TXF3
- REG_TXF4
- REG_TXF5
- REG_TXF6
- REG_TXF7
- REG_TXFDPR
- REG_TXF_WATER_MARK
- REG_TXG1CON
- REG_TXG2CON
- REG_TXLGMAP
- REG_TXMCR
- REG_TXMIR
- REG_TXNCON
- REG_TXPAUSE
- REG_TXPAUSE_8723B
- REG_TXPB
- REG_TXPEND
- REG_TXPKTBUF_BCNQ_BDNY
- REG_TXPKTBUF_BCNQ_BDNY1_8723B
- REG_TXPKTBUF_BCNQ_BDNY_8723B
- REG_TXPKTBUF_DBG
- REG_TXPKTBUF_IV_HIGH
- REG_TXPKTBUF_IV_LOW
- REG_TXPKTBUF_MGQ_BDNY
- REG_TXPKTBUF_MGQ_BDNY_8723B
- REG_TXPKTBUF_WMAC_LBK_BF_HD
- REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B
- REG_TXPKT_EMPTY
- REG_TXPKT_EMPTY_8723B
- REG_TXPSEL
- REG_TXPSEL1
- REG_TXQCR
- REG_TXQ_CTRL
- REG_TXRPT_START_OFFSET
- REG_TXR_BASE_ADDRESS
- REG_TXSF2
- REG_TXSF6
- REG_TXSR
- REG_TXSTAT
- REG_TXSTBL
- REG_TXSTSQBADD
- REG_TXSTSQBLEN
- REG_TXSTSQCURADD
- REG_TXS_BASE_ADDR_LO
- REG_TXS_MEM_SIZE
- REG_TXTIME
- REG_TX_ABORT_AGE
- REG_TX_ABORT_SHORT
- REG_TX_ABORT_TAXI
- REG_TX_ABORT_UNDERRUN
- REG_TX_AGC_A_CCK1_MCS32
- REG_TX_AGC_A_MCS03_MCS00
- REG_TX_AGC_A_MCS07_MCS04
- REG_TX_AGC_A_MCS11_MCS08
- REG_TX_AGC_A_MCS15_MCS12
- REG_TX_AGC_A_RATE18_06
- REG_TX_AGC_A_RATE54_24
- REG_TX_AGC_B_CCK11_A_CCK2_11
- REG_TX_AGC_B_CCK1_55_MCS32
- REG_TX_AGC_B_MCS03_MCS00
- REG_TX_AGC_B_MCS07_MCS04
- REG_TX_AGC_B_MCS11_MCS08
- REG_TX_AGC_B_MCS15_MCS12
- REG_TX_AGC_B_RATE18_06
- REG_TX_AGC_B_RATE54_24
- REG_TX_BASE_ADDR_HI
- REG_TX_CCK_BBON
- REG_TX_CCK_RFON
- REG_TX_CFG
- REG_TX_COL_COUNTER
- REG_TX_COMP0
- REG_TX_COMPN
- REG_TX_COMPWB_DB_HI
- REG_TX_COMPWB_DB_LOW
- REG_TX_CUT_THRESH
- REG_TX_DATA_PTR_HI
- REG_TX_DATA_PTR_LOW
- REG_TX_DB0_HI
- REG_TX_DB0_LOW
- REG_TX_DBN_HI
- REG_TX_DBN_LOW
- REG_TX_DENORM_DISCARD
- REG_TX_EARLY_TH
- REG_TX_FD
- REG_TX_FIFO_ADDR
- REG_TX_FIFO_CTRL
- REG_TX_FIFO_DATA_HI_T0
- REG_TX_FIFO_DATA_HI_T1
- REG_TX_FIFO_DATA_LOW
- REG_TX_FIFO_PKT_CNT
- REG_TX_FIFO_READ_PTR
- REG_TX_FIFO_SHADOW_READ_PTR
- REG_TX_FIFO_SHADOW_WRITE_PTR
- REG_TX_FIFO_SIZE
- REG_TX_FIFO_TAG
- REG_TX_FIFO_WRITE_PTR
- REG_TX_FSK_TEST
- REG_TX_HANG_CTRL
- REG_TX_IFG
- REG_TX_IP_BIST_CNTLSTA
- REG_TX_IP_BIST_CONF_HIGH
- REG_TX_IP_BIST_CONF_LOW
- REG_TX_IP_BIST_INST_HIGH
- REG_TX_IP_BIST_INST_LOW
- REG_TX_IP_BIST_PAT_HIGH
- REG_TX_IP_BIST_PAT_LOW
- REG_TX_IQK
- REG_TX_IQK_PI_A
- REG_TX_IQK_PI_B
- REG_TX_IQK_TONE_A
- REG_TX_IQK_TONE_B
- REG_TX_JUMBO_TASK_TH_TPD_IPG
- REG_TX_KICK0
- REG_TX_KICKN
- REG_TX_M
- REG_TX_MAXBURST_0
- REG_TX_MAXBURST_1
- REG_TX_MAXBURST_2
- REG_TX_MAXBURST_3
- REG_TX_OFDM_BBON
- REG_TX_OFDM_RFON
- REG_TX_OK_BYTES
- REG_TX_OPTIONS_BASE
- REG_TX_POLL_DEMAND
- REG_TX_POWER_AFTER_IQK_A
- REG_TX_POWER_AFTER_IQK_B
- REG_TX_POWER_BEFORE_IQK_A
- REG_TX_POWER_BEFORE_IQK_B
- REG_TX_PTCL_CTRL
- REG_TX_PTCL_CTRL_8723B
- REG_TX_RAMBIST
- REG_TX_REPORT_CTRL
- REG_TX_REPORT_TIME
- REG_TX_RING_BASE
- REG_TX_RPT_CTRL
- REG_TX_RPT_TIME
- REG_TX_SM_1
- REG_TX_SM_2
- REG_TX_TO_RX
- REG_TX_TO_TX
- REG_TX_TSO_OFFLOAD_THRESH
- REG_TX_ZONE_CTL1
- REG_TYPE_0
- REG_TYPE_ANY
- REG_TYPE_BASE
- REG_TYPE_DST
- REG_TYPE_DST_PLANE2
- REG_TYPE_ID
- REG_TYPE_INDEX
- REG_TYPE_INVALID
- REG_TYPE_MASK
- REG_TYPE_MSK
- REG_TYPE_NONE
- REG_TYPE_NOPC
- REG_TYPE_NOPCWB
- REG_TYPE_NOPCX
- REG_TYPE_NOSP
- REG_TYPE_NOSPPC
- REG_TYPE_NOSPPCX
- REG_TYPE_PAT
- REG_TYPE_PC
- REG_TYPE_R32
- REG_TYPE_R64
- REG_TYPE_RM
- REG_TYPE_SAMEAS16
- REG_TYPE_SP
- REG_TYPE_SRC
- REG_TYPE_SRC_PLANE2
- REG_TYPE_STR
- REG_TYPE_XMM
- REG_T_BANDWIDTH
- REG_U0BAR
- REG_U1BAR
- REG_U2BAR
- REG_U32
- REG_U64
- REG_UAPSD_TID
- REG_UAPSD_TID_8723B
- REG_UART_CTRL
- REG_UART_RX_DESA
- REG_UART_TX_DESA
- REG_UBAR
- REG_UFS_CCAP
- REG_UFS_CFG1
- REG_UFS_CFG2
- REG_UFS_CFG2_CGC_EN_ALL
- REG_UFS_CRYPTOCAP
- REG_UFS_HW_VERSION
- REG_UFS_LOCAL_PORT_ID_REG
- REG_UFS_PA_ERR_CODE
- REG_UFS_PA_LINK_STARTUP_TIMER
- REG_UFS_RETRY_TIMER_REG
- REG_UFS_SYS1CLK_1US
- REG_UFS_TX_SYMBOL_CLK_NS_US
- REG_UFS_VERSION
- REG_UIC_COMMAND
- REG_UIC_COMMAND_ARG_1
- REG_UIC_COMMAND_ARG_2
- REG_UIC_COMMAND_ARG_3
- REG_UIC_ERROR_CODE_DATA_LINK_LAYER
- REG_UIC_ERROR_CODE_DME
- REG_UIC_ERROR_CODE_NETWORK_LAYER
- REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER
- REG_UIC_ERROR_CODE_TRANSPORT_LAYER
- REG_UNALLOCATED_ADDR_READ
- REG_UNALLOCATED_ADDR_WRITE
- REG_UNCOR_CNT
- REG_UNKNOWN
- REG_UNKNOWN_24C
- REG_UNKNOWN_27C
- REG_UNKNOWN_350
- REG_UNLOCK1
- REG_UNLOCK2
- REG_UNLOCK_TEST_REG
- REG_UNONCE0
- REG_UNONCE1
- REG_UNONCE10
- REG_UNONCE11
- REG_UNONCE12
- REG_UNONCE2
- REG_UNONCE3
- REG_UNONCE4
- REG_UNONCE5
- REG_UNONCE6
- REG_UNONCE7
- REG_UNONCE8
- REG_UNONCE9
- REG_UN_used_register
- REG_UOFF
- REG_UPDATE
- REG_UPDATE_10
- REG_UPDATE_14
- REG_UPDATE_19
- REG_UPDATE_2
- REG_UPDATE_20
- REG_UPDATE_3
- REG_UPDATE_4
- REG_UPDATE_5
- REG_UPDATE_6
- REG_UPDATE_7
- REG_UPDATE_8
- REG_UPDATE_9
- REG_UPDATE_N
- REG_UPDATE_SEQ_2
- REG_UPDATE_SEQ_3
- REG_USAT
- REG_USB
- REG_USB0_FLAG
- REG_USB1_FLAG
- REG_USB2_FLAG
- REG_USBCMD
- REG_USBCTL
- REG_USBSTS
- REG_USB_AGG_TH
- REG_USB_AGG_THRESH
- REG_USB_AGG_TIMEOUT
- REG_USB_AGG_TO
- REG_USB_CHIRP_K
- REG_USB_DMA_AGG_TO
- REG_USB_HCPWM
- REG_USB_HIMR
- REG_USB_HIMRE
- REG_USB_HISR
- REG_USB_HISRE
- REG_USB_HRPWM
- REG_USB_High_NORMAL_Queue_Select_MAC0
- REG_USB_High_NORMAL_Queue_Select_MAC1
- REG_USB_INFO
- REG_USB_MAC_ADDR
- REG_USB_OPTIONAL
- REG_USB_PHY
- REG_USB_PID
- REG_USB_SIE_INTF
- REG_USB_SPECIAL_OPTION
- REG_USB_VID
- REG_USER
- REG_USER1
- REG_USER2
- REG_USER3
- REG_USER4
- REG_USER_BRIGHTNESS
- REG_USER_CONTRAST
- REG_USER_MR
- REG_USER_SATURATION
- REG_USER_SHARPBLUR
- REG_USER_SHARPNESS
- REG_USE_EXT_ADC
- REG_USTIME_EDCA
- REG_USTIME_EDCA_8723B
- REG_USTIME_TSF
- REG_USTIME_TSF_8723B
- REG_UTP_TASK_REQ_DOOR_BELL
- REG_UTP_TASK_REQ_LIST_BASE_H
- REG_UTP_TASK_REQ_LIST_BASE_L
- REG_UTP_TASK_REQ_LIST_CLEAR
- REG_UTP_TASK_REQ_LIST_RUN_STOP
- REG_UTP_TRANSFER_REQ_DOOR_BELL
- REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL
- REG_UTP_TRANSFER_REQ_LIST_BASE_H
- REG_UTP_TRANSFER_REQ_LIST_BASE_L
- REG_UTP_TRANSFER_REQ_LIST_CLEAR
- REG_UTP_TRANSFER_REQ_LIST_RUN_STOP
- REG_UTSRST
- REG_V0BAR
- REG_V1BAR
- REG_V2BAR
- REG_V5_FAULT_AR_VA
- REG_V5_FAULT_AW_VA
- REG_V5_INT_CLEAR
- REG_V5_INT_STATUS
- REG_V5_MMU_FLUSH_ALL
- REG_V5_MMU_FLUSH_END
- REG_V5_MMU_FLUSH_ENTRY
- REG_V5_MMU_FLUSH_RANGE
- REG_V5_MMU_FLUSH_START
- REG_V5_PT_BASE_PFN
- REG_VAL
- REG_VBLK_START_LINE_LSB
- REG_VBLK_START_LINE_MSB
- REG_VBLK_STOP_LINE_LSB
- REG_VBLK_STOP_LINE_MSB
- REG_VBUS_ADDRESS_ACCESS1
- REG_VBUS_ADDRESS_ACCESS2
- REG_VBUS_ADDRESS_ACCESS3
- REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR
- REG_VBUS_DATA_ACCESS_VBUS_ADDR_INCR
- REG_VBUS_OTG
- REG_VCO_CTRL
- REG_VCR_TRICK_MODE_CONTROL
- REG_VDP_CTRL
- REG_VDP_FIFO_INTERRUPT_THRLD
- REG_VDP_FIFO_OUTPUT_CONTROL
- REG_VDP_FIFO_RESET
- REG_VDP_FIFO_WORD_COUNT
- REG_VDP_FULL_FIELD_ENABLE
- REG_VDP_FULL_FIELD_MODE
- REG_VDP_GLOBAL_LINE_MODE
- REG_VDP_LINE_NUMBER_INTERRUPT
- REG_VDP_LINE_START
- REG_VDP_LINE_STOP
- REG_VDP_MATRIX
- REG_VDP_PIXEL_ALIGNMENT_LSB
- REG_VDP_PIXEL_ALIGNMENT_MSB
- REG_VDP_TTX_FILTER_1_MASK1
- REG_VDP_TTX_FILTER_1_MASK2
- REG_VDP_TTX_FILTER_1_MASK3
- REG_VDP_TTX_FILTER_1_MASK4
- REG_VDP_TTX_FILTER_1_MASK5
- REG_VDP_TTX_FILTER_2_MASK1
- REG_VDP_TTX_FILTER_2_MASK2
- REG_VDP_TTX_FILTER_2_MASK3
- REG_VDP_TTX_FILTER_2_MASK4
- REG_VDP_TTX_FILTER_2_MASK5
- REG_VDP_TTX_FILTER_CONTROL
- REG_VENDID
- REG_VENDOR_ID
- REG_VER
- REG_VERSION
- REG_VERSION_ID
- REG_VERSION_LSB
- REG_VERSION_MSB
- REG_VERTICAL_LINE_COUNT_LSB
- REG_VERTICAL_LINE_COUNT_MSB
- REG_VERT_SCROLL_CONTROL
- REG_VFIFO_READ_START_H
- REG_VFIFO_READ_START_L
- REG_VGAG
- REG_VHREF_CTRL
- REG_VID
- REG_VIDEO_STD
- REG_VIDEO_STD_STATUS
- REG_VIDFORMAT
- REG_VID_MODE
- REG_VID_OVRRD
- REG_VIP_CLKCTL
- REG_VIP_CNTRL_0
- REG_VIP_CNTRL_1
- REG_VIP_CNTRL_2
- REG_VIP_CNTRL_3
- REG_VIP_CNTRL_4
- REG_VIP_CNTRL_5
- REG_VIQ_DESA
- REG_VIQ_DESA_8723B
- REG_VIQ_INFO
- REG_VIQ_INFORMATION
- REG_VIQ_INFORMATION_8723B
- REG_VIQ_TXBD_IDX
- REG_VIQ_TXBD_NUM
- REG_VIRTUAL_READ
- REG_VIRTUAL_WRITE
- REG_VIRT_BASE
- REG_VI_ADMTIME
- REG_VMON_ENABLE
- REG_VND_IDH
- REG_VND_IDL
- REG_VNPORT
- REG_VOFF
- REG_VOLTAGE
- REG_VOLTAGE_BASE
- REG_VOLTAGE_LOW
- REG_VOLTAGE_MAX_BASE
- REG_VOLTAGE_MIN_BASE
- REG_VOLT_LUT
- REG_VOQ_DESA
- REG_VOQ_DESA_8723B
- REG_VOQ_INFO
- REG_VOQ_INFORMATION
- REG_VOQ_INFORMATION_8723B
- REG_VOQ_TXBD_IDX
- REG_VOQ_TXBD_NUM
- REG_VOUTSIZE
- REG_VO_ADMTIME
- REG_VP03_00_CTRL
- REG_VP07_04_CTRL
- REG_VP11_08_CTRL
- REG_VP15_12_CTRL
- REG_VP19_16_CTRL
- REG_VP23_20_CTRL
- REG_VP27_24_CTRL
- REG_VP31_28_CTRL
- REG_VP35_32_CTRL
- REG_VPD_CAP
- REG_VPD_DATA
- REG_VPI_VAR
- REG_VPT
- REG_VREF
- REG_VREF_DDR
- REG_VREF_F1_S
- REG_VREF_F1_WIDTH
- REG_VREF_F2_S
- REG_VREF_F2_WIDTH
- REG_VRTC_MEAS1
- REG_VSAT
- REG_VSET0
- REG_VSET1
- REG_VSET2
- REG_VSET3
- REG_VSTART
- REG_VSTOP
- REG_VSTRT
- REG_VSYNC_START_LINE_LSB
- REG_VSYNC_START_LINE_MSB
- REG_VSYNC_STOP_LINE_LSB
- REG_VSYNC_STOP_LINE_MSB
- REG_VS_F1_LINE_S
- REG_VS_F1_LINE_WIDTH
- REG_VS_F1_PIX_E
- REG_VS_F1_PIX_S
- REG_VS_F2_LINE_S
- REG_VS_F2_LINE_WIDTH
- REG_VS_F2_PIX_E
- REG_VS_F2_PIX_S
- REG_VS_LINE_END_1_LSB
- REG_VS_LINE_END_1_MSB
- REG_VS_LINE_END_2_LSB
- REG_VS_LINE_END_2_MSB
- REG_VS_LINE_STRT_1_LSB
- REG_VS_LINE_STRT_1_MSB
- REG_VS_LINE_STRT_2_LSB
- REG_VS_LINE_STRT_2_MSB
- REG_VS_PIX_END_1_LSB
- REG_VS_PIX_END_1_MSB
- REG_VS_PIX_END_2_LSB
- REG_VS_PIX_END_2_MSB
- REG_VS_PIX_STRT_1_LSB
- REG_VS_PIX_STRT_1_MSB
- REG_VS_PIX_STRT_2_LSB
- REG_VS_PIX_STRT_2_MSB
- REG_VS_VREF
- REG_VTT
- REG_VTT_MAX
- REG_VTT_MIN
- REG_VT_PIX_CLK_DIV
- REG_VT_SYS_CLK_DIV
- REG_VWIN_END_1_LSB
- REG_VWIN_END_1_MSB
- REG_VWIN_END_2_LSB
- REG_VWIN_END_2_MSB
- REG_VWIN_START_1_LSB
- REG_VWIN_START_1_MSB
- REG_VWIN_START_2_LSB
- REG_VWIN_START_2_MSB
- REG_V_PER
- REG_W0
- REG_W1
- REG_WAIT
- REG_WAKECON
- REG_WAKETIMEH
- REG_WAKETIMEL
- REG_WAKEUP_TIME
- REG_WAKEUP_TIME_NS
- REG_WATCH_DOG
- REG_WB
- REG_WCAMI
- REG_WD30
- REG_WDG_CTRL
- REG_WDG_LOAD_HIGH
- REG_WDG_LOAD_LOW
- REG_WDG_LOCK
- REG_WDL_CFG
- REG_WDOG_AND_BOOT
- REG_WDR_AUTO
- REG_WDR_OFF
- REG_WDR_ON
- REG_WDT_ISP
- REG_WEEKDAYS
- REG_WEEKS_REG
- REG_WIDTH
- REG_WIDTH_16
- REG_WIDTH_32
- REG_WIDTH_MASK
- REG_WIDTH_TEST
- REG_WIFI_BT_INFO
- REG_WINDOW_HEIGHT_HIGH
- REG_WINDOW_HEIGHT_LOW
- REG_WINDOW_START_X_HIGH
- REG_WINDOW_START_X_LOW
- REG_WINDOW_START_Y_HIGH
- REG_WINDOW_START_Y_LOW
- REG_WINDOW_WIDTH_HIGH
- REG_WINDOW_WIDTH_LOW
- REG_WKFMCAM_CMD
- REG_WKFMCAM_CMD_8723B
- REG_WKFMCAM_NUM
- REG_WKFMCAM_NUM_8723B
- REG_WKFMCAM_NUM_88E
- REG_WKFMCAM_RWD
- REG_WKFMCAM_RWD_8723B
- REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1
- REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1
- REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1
- REG_WLAN
- REG_WLAN_ACT_CONTROL_8723B
- REG_WLRF1
- REG_WL_BT_PWR_CTRL
- REG_WMAC_LBK_BF_HD
- REG_WMAC_OPTION_FUNCTION
- REG_WMAC_OPTION_FUNCTION_1
- REG_WMAC_RESP_TXINFO
- REG_WMAC_TRXPTCL_CTL
- REG_WMAC_TRXPTCL_CTL_H
- REG_WOL_CTRL
- REG_WOL_EVENT
- REG_WOL_PATTERN_LEN
- REG_WOL_PTLEN1
- REG_WOL_PTLEN2
- REG_WORDS_PER_ACT_LINE
- REG_WORDS_PER_LINE
- REG_WOWLAN_GTK_DBG1
- REG_WOWLAN_GTK_DBG2
- REG_WOWLAN_WAKE_REASON
- REG_WOW_CTRL
- REG_WOW_CTRL_8723B
- REG_WOW_H
- REG_WQ_CS_CFG
- REG_WQ_DC0_DD_CFG
- REG_WQ_DC1_DD_CFG
- REG_WQ_DCn_DD_CFG
- REG_WQ_DEF_ENC_WQID
- REG_WQ_PC_DD_CFG
- REG_WQ_SC_DD_CFG
- REG_WR
- REG_WR16
- REG_WR16_RELAXED
- REG_WR8
- REG_WRCONF
- REG_WRITE
- REG_WRITE16
- REG_WRITE8
- REG_WRITEH
- REG_WRITEL
- REG_WRITE_ARRAY
- REG_WRITE_AUX
- REG_WRITE_D
- REG_WRITE_DATA_TO_GRAM
- REG_WRITE_ENABLE
- REG_WRITE_UPDATE
- REG_WRITE_WITH_AUX
- REG_WR_ADDRH
- REG_WR_ADDRL
- REG_WR_DMAE
- REG_WR_DMAE_LEN
- REG_WR_IND
- REG_WR_RELAXED
- REG_WS
- REG_WTSR_SMPL_CNTL
- REG_XAUI_CODE_GRP_CNT
- REG_XAUI_CONF_A
- REG_XAUI_CONF_B
- REG_XAUI_CONF_TEST_A
- REG_XAUI_STAT_A
- REG_XAUI_STAT_B
- REG_XAUI_STAT_C
- REG_XCK_OUT_CTRL
- REG_XFREG0
- REG_XFREG15
- REG_XM_PG_COUNTER
- REG_XP_COUNTER
- REG_X_ADDR_END
- REG_X_ADDR_START
- REG_X_OUTPUT_SIZE
- REG_Y0BAR
- REG_Y1BAR
- REG_Y2BAR
- REG_YAVE
- REG_YBRIGHT
- REG_YEARS
- REG_YEARS_REG
- REG_YGAIN
- REG_YOFF
- REG_YUV422
- REG_Y_ADDR_END
- REG_Y_ADDR_START
- REG_Y_OUTPUT_SIZE
- REG_ZX_CFG_ERR_IRQ
- REG_ZX_CFG_ERR_IRQ_RAW
- REG_ZX_CTRL
- REG_ZX_DMA_ARB
- REG_ZX_DMA_GRP_PRIO
- REG_ZX_DST_ADDR
- REG_ZX_DST_ERR_IRQ
- REG_ZX_DST_ERR_IRQ_RAW
- REG_ZX_DST_ZY_STEP
- REG_ZX_LLI_ADDR
- REG_ZX_SRC_ADDR
- REG_ZX_SRC_ERR_IRQ
- REG_ZX_SRC_ERR_IRQ_RAW
- REG_ZX_SRC_ZY_STEP
- REG_ZX_STATUS
- REG_ZX_TC_IRQ
- REG_ZX_TC_IRQ_RAW
- REG_ZX_TX_X_COUNT
- REG_ZX_TX_ZY_COUNT
- REG_offset_AR
- REG_offset_BAR
- REGx
- REHASH_INTERVAL
- REISER2FS_JR_SUPER_MAGIC_STRING
- REISER2FS_SUPER_MAGIC_STRING
- REISERFS_3_5
- REISERFS_3_6
- REISERFS_ACL_VERSION
- REISERFS_APPEND_FL
- REISERFS_ATTRS
- REISERFS_BARRIER_FLUSH
- REISERFS_BARRIER_NONE
- REISERFS_COMPR_FL
- REISERFS_CONVERT
- REISERFS_DATA_LOG
- REISERFS_DATA_ORDERED
- REISERFS_DATA_WRITEBACK
- REISERFS_DEBUG_CODE
- REISERFS_DISK_OFFSET_IN_BYTES
- REISERFS_ERROR_CONTINUE
- REISERFS_ERROR_FS
- REISERFS_ERROR_PANIC
- REISERFS_ERROR_RO
- REISERFS_EXPOSE_PRIVROOT
- REISERFS_FIRST_BLOCK
- REISERFS_FULL_KEY_LEN
- REISERFS_GRPQUOTA
- REISERFS_HASHED_RELOCATION
- REISERFS_I
- REISERFS_IMMUTABLE_FL
- REISERFS_INHERIT_MASK
- REISERFS_IOC32_GETFLAGS
- REISERFS_IOC32_GETVERSION
- REISERFS_IOC32_SETFLAGS
- REISERFS_IOC32_SETVERSION
- REISERFS_IOC32_UNPACK
- REISERFS_IOC_GETFLAGS
- REISERFS_IOC_GETVERSION
- REISERFS_IOC_SETFLAGS
- REISERFS_IOC_SETVERSION
- REISERFS_IOC_UNPACK
- REISERFS_JOURNAL_OFFSET_IN_BYTES
- REISERFS_KERNEL_MEM
- REISERFS_LARGETAIL
- REISERFS_LINK_MAX
- REISERFS_MAXQUOTAS
- REISERFS_MAX_BITMAP_NODES
- REISERFS_MAX_NAME
- REISERFS_MIN_BITMAP_NODES
- REISERFS_NOATIME_FL
- REISERFS_NODUMP_FL
- REISERFS_NOTAIL_FL
- REISERFS_NO_BORDER
- REISERFS_NO_UNHASHED_RELOCATION
- REISERFS_OLD_DISK_OFFSET_IN_BYTES
- REISERFS_OLD_FORMAT
- REISERFS_OPT_ALLOWEMPTY
- REISERFS_POSIXACL
- REISERFS_PREALLOCATE
- REISERFS_QUOTA_DEL_BLOCKS
- REISERFS_QUOTA_INIT_BLOCKS
- REISERFS_QUOTA_OPTS
- REISERFS_QUOTA_TRANS_BLOCKS
- REISERFS_ROOT_OBJECTID
- REISERFS_ROOT_PARENT_OBJECTID
- REISERFS_SB
- REISERFS_SECRM_FL
- REISERFS_SHORT_KEY_LEN
- REISERFS_SMALLTAIL
- REISERFS_STANDARD_BLKSIZE
- REISERFS_SUPER_MAGIC
- REISERFS_SUPER_MAGIC_STRING
- REISERFS_SYNC_FL
- REISERFS_TEST1
- REISERFS_TEST2
- REISERFS_TEST3
- REISERFS_TEST4
- REISERFS_UNRM_FL
- REISERFS_UNSUPPORTED_OPT
- REISERFS_USER_MEM
- REISERFS_USRQUOTA
- REISERFS_VALID_FS
- REISERFS_VERSION_1
- REISERFS_VERSION_2
- REISERFS_XATTRS_USER
- REISERFS_XATTR_MAGIC
- REISTIM
- REISTIMEN
- REISWAITEN
- REJ
- REJECT
- REJECT_TO_OPEN_LIMIT_TIME
- REJECT_UNKNOWN
- REJOIN_NET_COMPLETE
- RELATED_REQUEST
- RELATIVECALL_OPCODE
- RELATIVEJUMP_OPCODE
- RELATIVEJUMP_SIZE
- RELATIVE_ADDR_SIZE
- RELATIVE_IDENTIFIERS
- RELAX
- RELAXED
- RELAXED_IRD_NEGOTIATION
- RELAX_SPIN_COUNT
- RELAYFS_CHANNEL_VERSION
- RELEASE
- RELEASED
- RELEASES_PER_BO
- RELEASE_10
- RELEASE_ALL
- RELEASE_BOOT
- RELEASE_CPU_RESET
- RELEASE_CPU_RESET_BIT
- RELEASE_LD
- RELEASE_LENGTH
- RELEASE_MASK
- RELEASE_MEM_cache_policy_enum
- RELEASE_MEM_data_sel_enum
- RELEASE_MEM_dst_sel_enum
- RELEASE_MEM_event_index_enum
- RELEASE_MEM_int_sel_enum
- RELEASE_PD
- RELEASE_RECOVERY
- RELEASE_RESOURCES
- RELEASE_SIZE
- RELEASE_SPINUP_HOLD
- RELEASE_THRESHOLD
- RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17_MASK
- RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_17__SHIFT
- RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18_MASK
- RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_18__SHIFT
- RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19_MASK
- RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_19__SHIFT
- RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20_MASK
- RELEASE_TO_STALL_LUT_17_20__FIRST_PATTERN_20__SHIFT
- RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1_MASK
- RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_1__SHIFT
- RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2_MASK
- RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_2__SHIFT
- RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3_MASK
- RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_3__SHIFT
- RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4_MASK
- RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_4__SHIFT
- RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5_MASK
- RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_5__SHIFT
- RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6_MASK
- RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_6__SHIFT
- RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7_MASK
- RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_7__SHIFT
- RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8_MASK
- RELEASE_TO_STALL_LUT_1_8__FIRST_PATTERN_8__SHIFT
- RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10_MASK
- RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_10__SHIFT
- RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11_MASK
- RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_11__SHIFT
- RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12_MASK
- RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_12__SHIFT
- RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13_MASK
- RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_13__SHIFT
- RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14_MASK
- RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_14__SHIFT
- RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15_MASK
- RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_15__SHIFT
- RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16_MASK
- RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_16__SHIFT
- RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9_MASK
- RELEASE_TO_STALL_LUT_9_16__FIRST_PATTERN_9__SHIFT
- RELEVANT_IFLAG
- RELINK_TIME_MASK
- RELOAD
- RELOADABLE_CTX_SHARED_MODE
- RELOAD_CONFIGURATION_REGISTERS
- RELOAD_SEG
- RELOAD_VALUE
- RELOC
- RELOCATED
- RELOCATE_ENTRY
- RELOCATION_RESERVED_NODES
- RELOCK_FIRST_MS
- RELOCS_H
- RELOC_FAILED
- RELOC_HIDE
- RELOC_KVAR
- RELOC_LABEL
- RELOC_LABELH
- RELOC_LABEL_A
- RELOC_LABEL_B
- RELOC_MASK
- RELOC_OP_ABS
- RELOC_OP_NONE
- RELOC_OP_PAGE
- RELOC_OP_PREL
- RELOC_REACHABLE
- RELOC_REGISTER
- RELOC_SOFTC
- RELOC_TYPE
- RELOGIN_TOV
- RELO_BR_GO_ABORT
- RELO_BR_GO_CALL_POP_REGS
- RELO_BR_GO_CALL_PUSH_REGS
- RELO_BR_GO_OUT
- RELO_BR_HELPER
- RELO_BR_NEXT_PKT
- RELO_BR_REL
- RELO_CALL
- RELO_DATA
- RELO_IMMED_REL
- RELO_LD64
- RELO_NONE
- RELO_NORMAL_VEC
- RELSZ
- REL_ADR
- REL_CNT
- REL_DIAL
- REL_HWHEEL
- REL_HWHEEL_HI_RES
- REL_MAX
- REL_MISC
- REL_RESERVED
- REL_RX
- REL_RY
- REL_RZ
- REL_TYPE
- REL_VERSION
- REL_WHEEL
- REL_WHEEL_HI_RES
- REL_X
- REL_X_REG
- REL_X_SIGN_BIT
- REL_Y
- REL_Y_REG
- REL_Y_SIGN_BIT
- REL_Z
- REM
- REMAIN
- REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID
- REMAP1
- REMAP2
- REMAPPED_FB_LEN
- REMAP_BATCH_SIZE
- REMAP_FILE_ADVISORY
- REMAP_FILE_CAN_SHORTEN
- REMAP_FILE_DEDUP
- REMAP_HDP_MEM_FLUSH_CNTL_IND__ADDRESS_MASK
- REMAP_HDP_MEM_FLUSH_CNTL_IND__ADDRESS__SHIFT
- REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK
- REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__MASK
- REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT
- REMAP_HDP_REG_FLUSH_CNTL_IND__ADDRESS_MASK
- REMAP_HDP_REG_FLUSH_CNTL_IND__ADDRESS__SHIFT
- REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK
- REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__MASK
- REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT
- REMAP_OFFSET
- REMAP_SIZE
- REMEMBER_STATE_CHANGE
- REMOCON_A_MARK
- REMOCON_B_MARK
- REMOCON_C_MARK
- REMOCON_MARK
- REMODER_DYNAMIC_MAX_FRAME_LENGTH
- REMODER_DYNAMIC_MIN_FRAME_LENGTH
- REMODER_IP_ADDRESS_ALIGNMENT
- REMODER_IP_CHECKSUM_CHECK
- REMODER_NUM_OF_QUEUES_SHIFT
- REMODER_RMON_STATISTICS
- REMODER_RX_EXTENDED_FEATURES
- REMODER_RX_EXTENDED_FILTERING
- REMODER_RX_QOS_MODE_SHIFT
- REMODER_RX_RMON_STATISTICS_ENABLE
- REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT
- REMODER_VLAN_OPERATION_TAGGED_SHIFT
- REMOTE
- REMOTE2_CRIT
- REMOTE2_EMERG
- REMOTE2_HIGH
- REMOTE2_LOW
- REMOTE2_TEMP
- REMOTEPROC_H
- REMOTEPROC_INTERNAL_H
- REMOTE_BOARD
- REMOTE_BUTTON_LEFT
- REMOTE_BUTTON_MIDDLE
- REMOTE_BUTTON_RIGHT
- REMOTE_CONDIS_INDICATE_STATUS_MSG
- REMOTE_CONDIS_MP_ACTIVATE_VC_CMPLT
- REMOTE_CONDIS_MP_ACTIVATE_VC_MSG
- REMOTE_CONDIS_MP_CREATE_VC_CMPLT
- REMOTE_CONDIS_MP_CREATE_VC_MSG
- REMOTE_CONDIS_MP_DEACTIVATE_VC_CMPLT
- REMOTE_CONDIS_MP_DEACTIVATE_VC_MSG
- REMOTE_CONDIS_MP_DELETE_VC_CMPLT
- REMOTE_CONDIS_MP_DELETE_VC_MSG
- REMOTE_CRIT
- REMOTE_DEVICE_ID
- REMOTE_DEVICE_ID_MASK
- REMOTE_DEVICE_ID_SHIFT
- REMOTE_DEVICE_REV_MASK
- REMOTE_DEVICE_REV_SHIFT
- REMOTE_DEV_STATES
- REMOTE_DISPLAY_DISABLE
- REMOTE_DISPLAY_ENABLE
- REMOTE_DISTANCE
- REMOTE_DOUBLE_CLICK
- REMOTE_EEEADV_1000BT
- REMOTE_EEEADV_100BT
- REMOTE_EMERG
- REMOTE_FAULT_INT
- REMOTE_HIGH
- REMOTE_HUB_ADDR
- REMOTE_HUB_CLR_INTR
- REMOTE_HUB_L
- REMOTE_HUB_PTR
- REMOTE_HUB_S
- REMOTE_HUB_SEND_INTR
- REMOTE_KEY_PRESSED
- REMOTE_KEY_REPEAT
- REMOTE_LNI_INFO
- REMOTE_LOOPBACK
- REMOTE_LOW
- REMOTE_NO_KEY_PRESSED
- REMOTE_OFFSET
- REMOTE_PG
- REMOTE_QUEUE_SIZE
- REMOTE_SCALARS_INBUFS
- REMOTE_SCALARS_INHANDLES
- REMOTE_SCALARS_LENGTH
- REMOTE_SCALARS_OUTBUFS
- REMOTE_SCALARS_OUTHANDLES
- REMOTE_TEMP
- REMOTE_TX_RATE_MASK
- REMOTE_TX_RATE_SHIFT
- REMOTE_UNWIND_LIBUNWIND
- REMOTE_WAKEUP_ISSUED
- REMOTE_WAKEUP_SUPPORT
- REMOTE_WAKE_CONFIG_CMD
- REMOTE_WAKE_ENABLE
- REMOVE
- REMOVE_ALL
- REMOVE_CLAMPING
- REMOVE_CLIENT
- REMOVE_DCTOL_MARGIN_BIT
- REMOVE_DEVICES
- REMOVE_FMAX_MARGIN_BIT
- REMOVE_JDATA
- REMOVE_MANAGED_RESOURCE
- REMOVE_META
- REMOVE_NOT_SUPPORTED
- REMOVE_PLATFORM_MARGIN_BIT
- REMOVE_SLOT_ATTR_NAME
- REMOVE_STA
- REM_CHASSIS_ID_STAT_LEN
- REM_CNTR_STAT
- REM_LTL_ERR_ILLTRAN
- REM_LTL_ERR_IMPSPEC
- REM_LTL_ERR_UNSOLR
- REM_LTL_ERR_UNSUPTR
- REM_PED_IMPL_SPEC
- REM_PED_LINK_OK2U
- REM_PED_LINK_TO
- REM_PED_LINK_U2OK
- REM_PED_LINK_UPDA
- REM_PORT_ID_STAT_LEN
- REM_STA_SUCCESS_MSK
- RENAME_EXCHANGE
- RENAME_NOREPLACE
- RENAME_REQ
- RENAME_RSP
- RENAME_WHITEOUT
- RENCLK_GATE_D1
- RENCLK_GATE_D2
- RENDER
- RENDER_CLASS
- RENDER_HWS_PGA_GEN7
- RENDER_POS
- RENDER_RING_BASE
- RENDER_TIMES_MAX_COUNT
- RENEG
- RENEGO_ENA
- RENESAS_SDHI_H
- RENESAS_USBHS_PIPE
- RENESAS_USB_DRIVER_H
- RENESAS_USB_FIFO_H
- RENESAS_USB_H
- RENESAS_USB_MOD_H
- RENESAS_USB_PIPE_H
- RENEWCAPS
- RENG_EXECUTE_ON_PWR_UP
- RENG_EXECUTE_ON_REG_UPDATE
- RENOIR_A0
- RENOIR_UMD_PSTATE_FCLK
- RENOIR_UMD_PSTATE_GFXCLK
- RENOIR_UMD_PSTATE_SOCCLK
- REN_CMND
- REN_DATA
- REN_STRB
- REOFEN
- REOG_MERCED_PORT
- REORDER_ENTRY_NUM
- REORDER_TIMEOUT
- REORDER_WAIT_TIME
- REORDER_WIN_SIZE
- REO_IOC_ID
- REO_MERCED_PORT
- REP1W2_EN
- REP82_ERROR_CHECKPT_FAILURE
- REP82_ERROR_EVEN_MOD_IN_OPND
- REP82_ERROR_FILTERED_BY_HYPERVISOR
- REP82_ERROR_FORMAT_FIELD
- REP82_ERROR_INVALID_COMMAND
- REP82_ERROR_INVALID_COMM_CD
- REP82_ERROR_INVALID_DOMAIN_PENDING
- REP82_ERROR_INVALID_DOMAIN_PRECHECK
- REP82_ERROR_INVALID_MSG_LEN
- REP82_ERROR_INVALID_SPECIAL_CMD
- REP82_ERROR_MACHINE_FAILURE
- REP82_ERROR_MALFORMED_MSG
- REP82_ERROR_MESSAGE_LENGTH
- REP82_ERROR_MESSAGE_TYPE
- REP82_ERROR_OPERAND_INVALID
- REP82_ERROR_OPERAND_SIZE
- REP82_ERROR_PACKET_TRUNCATED
- REP82_ERROR_PREEMPT_FAILURE
- REP82_ERROR_RESERVD_FIELD
- REP82_ERROR_RESERVED_FIELD
- REP82_ERROR_RESERVED_FIELDO
- REP82_ERROR_TRANSPORT_FAIL
- REP82_ERROR_WORD_ALIGNMENT
- REP82_ERROR_ZERO_BUFFER_LEN
- REP88_ERROR_INVALID_KEY
- REP88_ERROR_KEY_TYPE
- REP88_ERROR_MESSAGE_LENGTH
- REP88_ERROR_MESSAGE_MALFORMD
- REP88_ERROR_MESSAGE_TYPE
- REP88_ERROR_MODULE_FAILURE
- REP88_ERROR_OPERAND
- REP88_ERROR_OPERAND_EVEN_MOD
- REP88_ERROR_RESERVED_FIELD
- REP8_01
- REP8_7f
- REP8_80
- REPAPER_BORDER_BYTE_NONE
- REPAPER_BORDER_BYTE_SET
- REPAPER_BORDER_BYTE_ZERO
- REPAPER_COMPENSATE
- REPAPER_INVERSE
- REPAPER_NORMAL
- REPAPER_RID_G2_COG_ID
- REPAPER_WHITE
- REPARSE_INDEX_KEY
- REPARSE_POINT
- REPEAT
- REPEATS
- REPEAT_1
- REPEAT_10
- REPEAT_11
- REPEAT_12
- REPEAT_2
- REPEAT_3
- REPEAT_4
- REPEAT_5
- REPEAT_6
- REPEAT_7
- REPEAT_8
- REPEAT_9
- REPEAT_BITS
- REPEAT_BITS_MAX
- REPEAT_BYTE
- REPEAT_CNT
- REPEAT_DELAY
- REPEAT_EN
- REPEAT_INTERVAL
- REPEAT_SEARCH
- REPE_PREFIX
- REPLAY
- REPLAYONLY
- REPLAY_DONE
- REPLAY_MEM_LS_EN
- REPLAY_NEEDED
- REPLAY_UNNEEDED
- REPLICATE_F
- REPLICATE_S
- REPLICATE_V
- REPLICATOR_IDFILTER0
- REPLICATOR_IDFILTER1
- REPLY_ADD_STA
- REPLY_ALIVE
- REPLY_BEACON_FILTERING_CMD
- REPLY_BT_COEX_PRIO_TABLE
- REPLY_BT_COEX_PROFILE_NOTIF
- REPLY_BT_COEX_PROT_ENV
- REPLY_BT_CONFIG
- REPLY_CARD_STATE_CMD
- REPLY_CHANNEL_SWITCH
- REPLY_CHAN_F
- REPLY_CHAN_S
- REPLY_CHAN_V
- REPLY_COMPRESSED_BA
- REPLY_CT_KILL_CONFIG_CMD
- REPLY_D3_CONFIG
- REPLY_ECHO
- REPLY_ERROR
- REPLY_FRAME_SIZE
- REPLY_FREE_POOL_SIZE
- REPLY_LEDS_CMD
- REPLY_MAX
- REPLY_PHY_CALIBRATION_CMD
- REPLY_QOS_PARAM
- REPLY_QUIET_CMD
- REPLY_REMOVE_ALL_STA
- REPLY_REMOVE_STA
- REPLY_RX
- REPLY_RXON
- REPLY_RXON_ASSOC
- REPLY_RXON_TIMING
- REPLY_RX_MPDU_CMD
- REPLY_RX_PHY_CMD
- REPLY_SCAN_ABORT_CMD
- REPLY_SCAN_CMD
- REPLY_SF_CFG_CMD
- REPLY_SPECTRUM_MEASUREMENT_CMD
- REPLY_STATISTICS_CMD
- REPLY_THERMAL_MNG_BACKOFF
- REPLY_TRUNCATED
- REPLY_TX
- REPLY_TXFIFO_FLUSH
- REPLY_TX_BEACON
- REPLY_TX_LINK_QUALITY_CMD
- REPLY_TX_POWER_DBM_CMD
- REPLY_TX_POWER_DBM_CMD_V1
- REPLY_TX_PWR_TABLE_CMD
- REPLY_WEPKEY
- REPLY_WIPAN_DEACTIVATION_COMPLETE
- REPLY_WIPAN_NOA_NOTIFICATION
- REPLY_WIPAN_P2P_CHANNEL_SWITCH
- REPLY_WIPAN_PARAMS
- REPLY_WIPAN_QOS_PARAM
- REPLY_WIPAN_RXON
- REPLY_WIPAN_RXON_ASSOC
- REPLY_WIPAN_RXON_TIMING
- REPLY_WIPAN_WEPKEY
- REPLY_WOWLAN_GET_STATUS
- REPLY_WOWLAN_KEK_KCK_MATERIAL
- REPLY_WOWLAN_PATTERNS
- REPLY_WOWLAN_TKIP_PARAMS
- REPLY_WOWLAN_TSC_RSC_PARAMS
- REPLY_WOWLAN_WAKEUP_FILTER
- REPNE_PREFIX
- REPORTED_BIT
- REPORT_ALLOCATION
- REPORT_BIT_AD0
- REPORT_BIT_AD1
- REPORT_BIT_HAS_PRESSURE
- REPORT_BIT_PRESSED
- REPORT_BL_ERASE_MEMORY
- REPORT_BL_READ_MEMORY
- REPORT_BL_WRITE_MEMORY
- REPORT_BRIGHTNESS
- REPORT_BRIGHTNESS_KEY_EVENTS
- REPORT_BSSINFO_CTRL_FLAGS
- REPORT_CONTRAST
- REPORT_DEVICE_TYPE
- REPORT_DEVID
- REPORT_EE_DATA
- REPORT_EE_READ
- REPORT_EE_WRITE
- REPORT_ERASE_MEMORY
- REPORT_ERROR_CODE
- REPORT_EXIT_FLASHER
- REPORT_EXIT_KEYBOARD
- REPORT_FAILURE
- REPORT_FAILURES_IN_FN
- REPORT_HEAD
- REPORT_HOOK_VERSION
- REPORT_ID_DJ_LONG
- REPORT_ID_DJ_SHORT
- REPORT_ID_HIDPP_LONG
- REPORT_ID_HIDPP_SHORT
- REPORT_ID_HIDPP_VERY_LONG
- REPORT_IR_DATA
- REPORT_KEY_STATE
- REPORT_LCD_CMD
- REPORT_LCD_CMD_DATA
- REPORT_LCD_DATA
- REPORT_LED_STATE
- REPORT_LUNS
- REPORT_LUNS_CHANGED
- REPORT_MAX_SIZE
- REPORT_MEMORY
- REPORT_MODE_MOUSE
- REPORT_MODE_MTTOUCH
- REPORT_MODE_VENDOR
- REPORT_OUTPUT_KEY_EVENTS
- REPORT_PHYS_LUN_DEV_FLAG_AIO_ENABLED
- REPORT_RATE_1ST_BIT
- REPORT_RATE_40
- REPORT_RATE_80
- REPORT_RATE_MSK
- REPORT_RATE_OFFSET
- REPORT_READ_MEMORY
- REPORT_RESET
- REPORT_RESP
- REPORT_RES_BITS
- REPORT_SPLASH_RESTART
- REPORT_SPLASH_SIZE
- REPORT_SUFFIX
- REPORT_TIMER
- REPORT_TYPE_CMD_GET_PAIRED_DEVICES
- REPORT_TYPE_CMD_SWITCH
- REPORT_TYPE_CONSUMER_CONTROL
- REPORT_TYPE_KEYBOARD
- REPORT_TYPE_LEDS
- REPORT_TYPE_MEDIA_CENTER
- REPORT_TYPE_MOUSE
- REPORT_TYPE_NOTIF_CONNECTION_STATUS
- REPORT_TYPE_NOTIF_DEVICE_CONNECTED
- REPORT_TYPE_NOTIF_DEVICE_PAIRED
- REPORT_TYPE_NOTIF_DEVICE_UNPAIRED
- REPORT_TYPE_NOTIF_ERROR
- REPORT_TYPE_RFREPORT_FIRST
- REPORT_TYPE_RFREPORT_LAST
- REPORT_TYPE_SYSTEM_CONTROL
- REPORT_VERSION
- REPORT_WRITE_MEMORY
- REPO_EXHAUST
- REPO_RELIEVE
- REPO_WARN
- REPRINT_CHAR
- REPROGRAM_PAR
- REPS
- REPZ_11_138
- REPZ_3_10
- REP_3_6
- REP_BASE
- REP_CNT
- REP_DELAY
- REP_ETH
- REP_IB
- REP_LOADED
- REP_MAX
- REP_PERIOD
- REP_REGISTERED
- REP_UNREGISTERED
- REQ
- REQ0_CMD_Q_SHIFT
- REQ0_INT_ON_COMPLETE
- REQ0_JOBID_SHIFT
- REQ0_REQOUT_MARK
- REQ0_STOP_ON_COMPLETE
- REQ0_WAIT_FOR_WRITE
- REQ1_AES_ACTION_SHIFT
- REQ1_AES_CFB_SIZE_SHIFT
- REQ1_AES_MODE_SHIFT
- REQ1_AES_TYPE_SHIFT
- REQ1_ECC_AFFINE_CONVERT
- REQ1_ECC_FUNCTION_SHIFT
- REQ1_ENGINE_SHIFT
- REQ1_EOM
- REQ1_INIT
- REQ1_KEY_KSB_SHIFT
- REQ1_MARK
- REQ1_PROTECT_SHIFT
- REQ1_PT_BS_SHIFT
- REQ1_PT_BW_SHIFT
- REQ1_RSA_MOD_SIZE_SHIFT
- REQ1_SHA_TYPE_SHIFT
- REQ1_XTS_AES_SIZE_SHIFT
- REQ2_MARK
- REQ3_MARK
- REQ4_KSB_SHIFT
- REQ4_MEMTYPE_SHIFT
- REQ6_MEMTYPE_SHIFT
- REQALG
- REQBASICRATE
- REQCNTLD
- REQCNT_UP
- REQINIT
- REQMBXREAD
- REQOVRLOOKUPINT_F
- REQOVRLOOKUPINT_S
- REQOVRLOOKUPINT_V
- REQQPARERR_F
- REQQPARERR_S
- REQQPARERR_V
- REQSACK_TIMEOUT_TIME
- REQSUMCHECKRD
- REQSUPPRATE
- REQTYPE_DEVICE_TO_HOST
- REQTYPE_F2_RD
- REQTYPE_HOST_TO_DEVICE
- REQTYPE_HOST_TO_INTERFACE
- REQTYPE_I2C_READ
- REQTYPE_I2C_WRITE
- REQTYPE_I2C_WRITE_STATT
- REQTYPE_INTERFACE_TO_HOST
- REQTYPE_LAST
- REQTYPE_MASK
- REQTYPE_NONE
- REQTYPE_NORESP_NET
- REQTYPE_NORESP_NET_SG
- REQTYPE_RD
- REQTYPE_RESP_NET
- REQTYPE_RESP_NET_SG
- REQTYPE_SOFT_COMMAND
- REQUEST
- REQUESTED_SERVICES_PROBLEM
- REQUEST_
- REQUEST_ALLOCATION
- REQUEST_ANY
- REQUEST_BEGIN
- REQUEST_BY_CAP
- REQUEST_BY_ID
- REQUEST_BY_NODE
- REQUEST_CAPABILITY
- REQUEST_CAPABILITY_RSP
- REQUEST_COMPLETION_FLAG
- REQUEST_CONFIGURATION_STRING
- REQUEST_COUNT_MSK
- REQUEST_DIR_ONLY
- REQUEST_EEPROM
- REQUEST_ENABLE_VIDEO
- REQUEST_END
- REQUEST_ENTRY_CNT
- REQUEST_ENTRY_CNT_2100
- REQUEST_ENTRY_CNT_2200
- REQUEST_ENTRY_CNT_24XX
- REQUEST_ENTRY_CNT_82XX
- REQUEST_ENTRY_CNT_83XX
- REQUEST_ENTRY_CNT_FX00
- REQUEST_ENTRY_SIZE
- REQUEST_FILE
- REQUEST_FILE_ONLY
- REQUEST_GET_VERSION
- REQUEST_I2C_READ
- REQUEST_I2C_WRITE
- REQUEST_IDX_KIND
- REQUEST_IN
- REQUEST_INTERNAL
- REQUEST_INTERNAL_CH
- REQUEST_IRQ
- REQUEST_JUMPRAM
- REQUEST_MAP
- REQUEST_MAP_RSP
- REQUEST_MAX_COORDINATES
- REQUEST_MODEL_AND_ROM_VERSION
- REQUEST_NAME
- REQUEST_NEW_I2C_READ
- REQUEST_NEW_I2C_WRITE
- REQUEST_NUM
- REQUEST_OUT
- REQUEST_PENDING
- REQUEST_POLL_RC
- REQUEST_QUEUE_DEPTH
- REQUEST_QUEUE_MAX_LEN
- REQUEST_QUEUE_WAKEUP
- REQUEST_READ
- REQUEST_REGISTER
- REQUEST_RESET_TO_PROTOCOL_IV
- REQUEST_SENSE
- REQUEST_SET_CLOCK
- REQUEST_SET_GPIO
- REQUEST_SET_I2C_PARAM
- REQUEST_SET_RC
- REQUEST_SET_USB_XFER_LEN
- REQUEST_STATES
- REQUEST_STATISTICS
- REQUEST_STATISTICS_RSP
- REQUEST_TRANSFER_ERROR
- REQUEST_TYPE
- REQUEST_UNALIGNED
- REQUEST_UNMAP
- REQUEST_UNMAP_RSP
- REQUEST_VALUE
- REQUEST_VALUE_
- REQUEST_VALUE__
- REQUEST_WRITE
- REQUEST_ZLP
- REQUEUE_PENDING
- REQUIRED_BOND_STATES
- REQUIRED_MASK0
- REQUIRED_MASK1
- REQUIRED_MASK10
- REQUIRED_MASK11
- REQUIRED_MASK12
- REQUIRED_MASK13
- REQUIRED_MASK14
- REQUIRED_MASK15
- REQUIRED_MASK16
- REQUIRED_MASK17
- REQUIRED_MASK18
- REQUIRED_MASK2
- REQUIRED_MASK3
- REQUIRED_MASK4
- REQUIRED_MASK5
- REQUIRED_MASK6
- REQUIRED_MASK7
- REQUIRED_MASK8
- REQUIRED_MASK9
- REQUIRED_MASK_BIT_SET
- REQUIRED_MASK_CHECK
- REQUIRED_SPACE_IN_RING_FOR_COMMAND_PACKET
- REQUIRE_ATIM_QUEUE
- REQUIRE_BEACON_GUARD
- REQUIRE_COPY_IV
- REQUIRE_DELAYED_RFKILL
- REQUIRE_DMA
- REQUIRE_FIRMWARE
- REQUIRE_HT_TX_DESC
- REQUIRE_L2PAD
- REQUIRE_PS_AUTOWAKE
- REQUIRE_R_LEVEL
- REQUIRE_SW_SEQNO
- REQUIRE_TASKLET_CONTEXT
- REQUIRE_TSF_SYNC_CONFIRM
- REQUIRE_TXSTATUS_FIFO
- REQ_00_SET_IR_VALUE
- REQ_01_SET_WAKEUP_IRCODE
- REQ_02_GET_IR_CODE
- REQ_03_SET_GET_MCU_PIN
- REQ_04_EN_DISABLE_MCU_INT
- REQ_05_SET_GET_USBREG
- REQ_06_SET_GET_USBREG_BIT
- REQ_07_SET_GET_AVREG
- REQ_08_SET_GET_AVREG_BIT
- REQ_09_SET_GET_TUNER_FQ
- REQ_10_SET_TUNER_SYSTEM
- REQ_11_SET_EEPROM_ADDR
- REQ_128BytesContiguous
- REQ_128BytesNonContiguous
- REQ_12_SET_GET_EEPROMBYTE
- REQ_13_GET_EEPROM_SEQREAD
- REQ_14_SET_GET_I2C_WR2_RDN
- REQ_15_SET_GET_I2CBYTE
- REQ_16_SET_GET_I2C_WR1_RDN
- REQ_17_SET_GET_I2CFP
- REQ_20_DATA_TRANSFER
- REQ_256Bytes
- REQ_30_I2C_WRITE
- REQ_31_I2C_READ
- REQ_35_AFTEK_TUNER_READ
- REQ_40_GET_VERSION
- REQ_50_SET_START
- REQ_51_SET_STOP
- REQ_52_TRANSMIT_DATA
- REQ_53_SPI_INITIAL
- REQ_54_SPI_SETSTART
- REQ_55_SPI_INOUTDATA
- REQ_56_SPI_SETSTOP
- REQ_ACS_FLAGS
- REQ_ALLOCATION
- REQ_ARGS
- REQ_ASPI_TRAN
- REQ_BACKGROUND
- REQ_BACKLOG
- REQ_BATCHOPLOCK
- REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF
- REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP
- REQ_BC_VER_4_FCOE_FEATURES
- REQ_BC_VER_4_INITIATE_FLR
- REQ_BC_VER_4_MT_SUPPORTED
- REQ_BC_VER_4_PFC_STATS_SUPPORTED
- REQ_BC_VER_4_RMMOD_CMD
- REQ_BC_VER_4_SET_MF_BW
- REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED
- REQ_BC_VER_4_VRFY_AFEX_SUPPORTED
- REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL
- REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL
- REQ_BUS_OFF
- REQ_BUS_ON
- REQ_CACHE_TYPE
- REQ_CGROUP_PUNT
- REQ_CID
- REQ_CLKS_OFF
- REQ_CLKS_ON
- REQ_CMD_BUSY
- REQ_CMD_EIO
- REQ_CMD_TMO
- REQ_COMM_ENG
- REQ_COMPLETE
- REQ_CONDITIONING
- REQ_COUNTER
- REQ_COUNTER_CLEAR
- REQ_DAT_ERR
- REQ_DELAY
- REQ_DEM_TYPE
- REQ_DEVICE_RESET
- REQ_DEVSET_EXEC
- REQ_DONE
- REQ_DPTDDL
- REQ_DRIVE_RESET
- REQ_DRV
- REQ_DUPLEX_PHY0_MASK
- REQ_DUPLEX_PHY0_SHIFT
- REQ_DUPLEX_PHY1_MASK
- REQ_DUPLEX_PHY1_SHIFT
- REQ_E
- REQ_ENGINE
- REQ_EOPNOTSUPP
- REQ_ERROR
- REQ_EXTENDED_INFO
- REQ_FAILFAST_DEV
- REQ_FAILFAST_DRIVER
- REQ_FAILFAST_MASK
- REQ_FAILFAST_TRANSPORT
- REQ_FC_AUTO_ADV0_SHIFT
- REQ_FC_AUTO_ADV_MASK
- REQ_FLAG_BITS
- REQ_FLOW_CTRL_PHY0_MASK
- REQ_FLOW_CTRL_PHY0_SHIFT
- REQ_FLOW_CTRL_PHY1_MASK
- REQ_FLOW_CTRL_PHY1_SHIFT
- REQ_FROM_IRQ_POOL
- REQ_FSEQ_ACTIONS
- REQ_FSEQ_DATA
- REQ_FSEQ_DONE
- REQ_FSEQ_POSTFLUSH
- REQ_FSEQ_PREFLUSH
- REQ_FUA
- REQ_F_FAIL_LINK
- REQ_F_FIXED_FILE
- REQ_F_IOPOLL_COMPLETED
- REQ_F_IO_DRAIN
- REQ_F_IO_DRAINED
- REQ_F_ISREG
- REQ_F_LINK
- REQ_F_LINK_DONE
- REQ_F_MUST_PUNT
- REQ_F_NOWAIT
- REQ_F_SEQ_PREV
- REQ_F_SHADOW_DRAIN
- REQ_F_TIMEOUT
- REQ_F_TIMEOUT_NOSEQ
- REQ_GEN_PREFIX
- REQ_HBA_DRIVER
- REQ_HDR_LEN
- REQ_HIPRI
- REQ_HIPRIO
- REQ_IDETAPE_PC1
- REQ_IDETAPE_PC2
- REQ_IDETAPE_READ
- REQ_IDETAPE_WRITE
- REQ_IDLE
- REQ_INTEGRITY
- REQ_IO_HIGH
- REQ_IO_LOW
- REQ_IO_TYPE
- REQ_L
- REQ_LEN0
- REQ_LEN1
- REQ_LINE_SPD_PHY0_MASK
- REQ_LINE_SPD_PHY0_SHIFT
- REQ_LINE_SPD_PHY1_MASK
- REQ_LINE_SPD_PHY1_SHIFT
- REQ_LOCK_TYPE
- REQ_LOW_ENABLE
- REQ_META
- REQ_MORE_INFO
- REQ_MTU
- REQ_NA
- REQ_NEW_CONTROL
- REQ_NOMERGE
- REQ_NOMERGE_FLAGS
- REQ_NOTFIY_CQ
- REQ_NOT_DELAY
- REQ_NOT_POSTED
- REQ_NOUNMAP
- REQ_NOWAIT
- REQ_NOWAIT_INLINE
- REQ_NVME_MPATH
- REQ_OOB
- REQ_OPENDIRONLY
- REQ_OPLOCK
- REQ_OP_BITS
- REQ_OP_DISCARD
- REQ_OP_DRV_IN
- REQ_OP_DRV_OUT
- REQ_OP_FLUSH
- REQ_OP_LAST
- REQ_OP_MASK
- REQ_OP_NAME
- REQ_OP_READ
- REQ_OP_SCSI_IN
- REQ_OP_SCSI_OUT
- REQ_OP_SECURE_ERASE
- REQ_OP_WRITE
- REQ_OP_WRITE_SAME
- REQ_OP_WRITE_ZEROES
- REQ_OP_ZONE_RESET
- REQ_OP_ZONE_RESET_ALL
- REQ_ORD_TYPE
- REQ_PARK_HEADS
- REQ_PASSKEY
- REQ_PENDING
- REQ_PHY_DPLL_CLK
- REQ_POOL_SIZE
- REQ_POSTED
- REQ_PREFLUSH
- REQ_PRIO
- REQ_QUEUE_DEPTH
- REQ_RAHEAD
- REQ_REG
- REQ_RX_ADD_ENTRIES_PER_SUBCRQ
- REQ_RX_ADD_QUEUES
- REQ_RX_DESCRIPTOR_MULTIPLE
- REQ_RX_QUEUES
- REQ_SAME_HOST_BRIDGE
- REQ_SENT
- REQ_SIZE
- REQ_SIZE_ENUM_10_BEAT
- REQ_SIZE_ENUM_11_BEAT
- REQ_SIZE_ENUM_12_BEAT
- REQ_SIZE_ENUM_13_BEAT
- REQ_SIZE_ENUM_14_BEAT
- REQ_SIZE_ENUM_15_BEAT
- REQ_SIZE_ENUM_16_BEAT
- REQ_SIZE_ENUM_1_BEAT
- REQ_SIZE_ENUM_2_BEAT
- REQ_SIZE_ENUM_3_BEAT
- REQ_SIZE_ENUM_4_BEAT
- REQ_SIZE_ENUM_5_BEAT
- REQ_SIZE_ENUM_6_BEAT
- REQ_SIZE_ENUM_7_BEAT
- REQ_SIZE_ENUM_8_BEAT
- REQ_SIZE_ENUM_9_BEAT
- REQ_SIZE_MASK
- REQ_SIZE_SHIFT
- REQ_SMARTROM
- REQ_SPLIT_TYPE
- REQ_START
- REQ_STATUS_ALLOC
- REQ_STATUS_ERROR
- REQ_STATUS_FLSHD
- REQ_STATUS_PENDING
- REQ_STATUS_RCVD
- REQ_STATUS_SENT
- REQ_STATUS_UNSENT
- REQ_STOP_EIO
- REQ_STOP_TMO
- REQ_SWAP
- REQ_SYNC
- REQ_TASK_ABORT
- REQ_TIMB_DMA_RESUME
- REQ_TIME
- REQ_TRI_STATE_ENABLE
- REQ_TRK_IN_ERROR
- REQ_TX_DESCRIPTOR_MULTIPLE
- REQ_TX_ENTRIES_PER_SUBCRQ
- REQ_TX_QUEUES
- REQ_TYPE0
- REQ_TYPE1
- REQ_TYPE_HCAM
- REQ_TYPE_IOACMD
- REQ_TYPE_MASK
- REQ_TYPE_SCSI
- REQ_TYPE_SHIFT
- REQ_UNCOMPLETE
- REQ_UNPARK_HEADS
- REQ_WAITING
- RER
- RERUN_ISR
- RES
- RES18
- RES1flag
- RES28
- RES2flag
- RES3
- RES4
- RES4313_AFE_PWRSW_RSRC
- RES4313_ALP_AVAIL_RSRC
- RES4313_BB_PLL_PWRSW_RSRC
- RES4313_BB_PU_RSRC
- RES4313_BB_PWRSW_RSRC
- RES4313_BG_PU_RSRC
- RES4313_HT_AVAIL_RSRC
- RES4313_ILP_REQ_RSRC
- RES4313_MACPHY_CLK_AVAIL_RSRC
- RES4313_MISC_PWRSW_RSRC
- RES4313_RADIO_PU_RSRC
- RES4313_RX_PWRSW_RSRC
- RES4313_SYNTH_PWRSW_RSRC
- RES4313_TX_PWRSW_RSRC
- RES4313_VREG1P4_PU_RSRC
- RES4313_XTAL_PU_RSRC
- RES5
- RES6
- RES7
- RES8
- RESCAN_REQUIRED_EVENT_BITS
- RESCHEDULE_VECTOR
- RESCNT2
- RESCNT2_PRES
- RESCODE_OFFSET
- RESCTL_ADRS
- RESCTL_QVGA
- RESCTL_VGA
- RESCUER_NICE_LEVEL
- RESC_END
- RESC_NUM
- RESC_START
- RESELECT
- RESELECT3
- RESELECTID
- RESELECT_EI
- RESELECT_FLAG
- RESELECT_ID
- RESELECT_IRQ
- RESEND
- RESEND_CTS_STATE
- RESEND_DPP_ON_LRTY_FMW
- RESERVATION_CAPABILITIES
- RESERVATION_CONFLICT
- RESERVATION_PREEMPTED
- RESERVATION_STATUS
- RESERVE
- RESERVED
- RESERVED0
- RESERVED1
- RESERVED10
- RESERVED1_EVENT_ID
- RESERVED1_ID_MASK
- RESERVED1_MASK
- RESERVED1_MASK_SFT
- RESERVED1_SFT
- RESERVED2
- RESERVED2_EVENT_ID
- RESERVED2_ID_MASK
- RESERVED3
- RESERVED4
- RESERVED5
- RESERVED6
- RESERVED7
- RESERVED8
- RESERVED9
- RESERVEDMEM_OF_DECLARE
- RESERVEDMEM_OF_TABLES
- RESERVED_0X6D
- RESERVED_0X73
- RESERVED_0X74
- RESERVED_0X75
- RESERVED_0X7E
- RESERVED_0X85
- RESERVED_0X86
- RESERVED_0X88
- RESERVED_0X89
- RESERVED_0X94
- RESERVED_0X95
- RESERVED_0X96
- RESERVED_0X97
- RESERVED_0X98
- RESERVED_0X99
- RESERVED_0X9A
- RESERVED_0X9B
- RESERVED_1
- RESERVED_2
- RESERVED_4
- RESERVED_5
- RESERVED_6
- RESERVED_60
- RESERVED_61
- RESERVED_62
- RESERVED_63
- RESERVED_7
- RESERVED_88
- RESERVED_89
- RESERVED_90
- RESERVED_91
- RESERVED_BIO_BASED_IOS
- RESERVED_BLOCKS
- RESERVED_BY_OTHER
- RESERVED_CLK_NAME
- RESERVED_CONNECTION_TYPE_0
- RESERVED_CONNECTION_TYPE_1
- RESERVED_CONNECTION_TYPE_2
- RESERVED_ES
- RESERVED_GENERAL_ATTENTION_BIT_0
- RESERVED_GENERAL_ATTENTION_BIT_10
- RESERVED_GENERAL_ATTENTION_BIT_11
- RESERVED_GENERAL_ATTENTION_BIT_12
- RESERVED_GENERAL_ATTENTION_BIT_13
- RESERVED_GENERAL_ATTENTION_BIT_14
- RESERVED_GENERAL_ATTENTION_BIT_15
- RESERVED_GENERAL_ATTENTION_BIT_16
- RESERVED_GENERAL_ATTENTION_BIT_17
- RESERVED_GENERAL_ATTENTION_BIT_18
- RESERVED_GENERAL_ATTENTION_BIT_19
- RESERVED_GENERAL_ATTENTION_BIT_20
- RESERVED_GENERAL_ATTENTION_BIT_21
- RESERVED_GENERAL_ATTENTION_BIT_6
- RESERVED_GENERAL_ATTENTION_BIT_7
- RESERVED_GENERAL_ATTENTION_BIT_8
- RESERVED_GENERAL_ATTENTION_BIT_9
- RESERVED_GROUP
- RESERVED_INTR
- RESERVED_IPC
- RESERVED_IRQ_PER_MBIGEN_CHIP
- RESERVED_ITT
- RESERVED_KEY
- RESERVED_LS
- RESERVED_PIDS
- RESERVED_PTT_DPC
- RESERVED_PTT_EDIAG
- RESERVED_PTT_MAIN
- RESERVED_PTT_MAX
- RESERVED_PTT_USER_SPACE
- RESERVED_RDPOLICY
- RESERVED_REGISTERS
- RESERVED_REQUEST_BASED_IOS
- RESERVED_TTBR0_SIZE
- RESERVED_VS
- RESERVE_10
- RESERVE_BRK
- RESERVE_BRK_ARRAY
- RESERVE_BTREE
- RESERVE_CHANNEL
- RESERVE_CONFLICT
- RESERVE_FREE_LIST_INDEX
- RESERVE_INT
- RESERVE_INT_MASK
- RESERVE_LD
- RESERVE_MOVINGGC
- RESERVE_NONE
- RESERVE_NR
- RESERVE_PD
- RESERVE_PRIO
- RESET
- RESET1_POL_HIGH
- RESET1_POL_LOW
- RESET2_POL_HIGH
- RESET2_POL_LOW
- RESETA_N_PU_OFF_MARK
- RESETA_N_PU_ON_MARK
- RESETCON_DMT_TIMEOUT
- RESETCON_TIMEOUT_IDLE
- RESETCON_TIMEOUT_SLEEP
- RESETCON_WDT_TIMEOUT
- RESETCSDMA
- RESETC_RSSR
- RESETC_RSSR_HWR
- RESETC_RSSR_SMR
- RESETC_RSSR_SWR
- RESETC_RSSR_WDR
- RESETC_SWRR
- RESETC_SWRR_SRB
- RESETDONE
- RESETOUTS_MARK
- RESETOUTS__MARK
- RESETOVLYDMA
- RESETP_PLAIN_MARK
- RESETP_PULLUP_MARK
- RESETUART
- RESET_A15_NCORERESET
- RESET_A2P_FLAGS
- RESET_A5
- RESET_A5_APB
- RESET_A5_AXI
- RESET_A5_DEBUG
- RESET_A7_NCORERESET
- RESET_A9_DMC_PIPEL
- RESET_ABORT
- RESET_ABUF
- RESET_ACCU
- RESET_ADAPTER
- RESET_AFIFO
- RESET_AFIFO2
- RESET_AHB_BRIDGE
- RESET_AHB_BRIDGE_CNTL
- RESET_AHB_CNTL
- RESET_AHB_DATA
- RESET_AHB_MON
- RESET_AHB_SRAM
- RESET_AI
- RESET_AIFIFO
- RESET_AIU
- RESET_ALL
- RESET_ALOCKER
- RESET_AL_PA
- RESET_ANTI_MUX_MASK
- RESET_AO_CPU_RESET
- RESET_AO_I2C_M
- RESET_AO_I2C_MASTER
- RESET_AO_I2C_S
- RESET_AO_I2C_SLAVE
- RESET_AO_IR_BLASTER
- RESET_AO_IR_IN
- RESET_AO_IR_OUT
- RESET_AO_REMOTE
- RESET_AO_RESET
- RESET_AO_SAR_ADC
- RESET_AO_UART
- RESET_AO_UART1
- RESET_AO_UART2
- RESET_ARM
- RESET_ARM0
- RESET_ARM1
- RESET_ARMDBG
- RESET_ASSIST
- RESET_ASSP
- RESET_ASYNC0
- RESET_ASYNC1
- RESET_ATM
- RESET_ATN
- RESET_AUDIN
- RESET_AUDIO
- RESET_AUDIO_APB
- RESET_AUDIO_CODEC
- RESET_AUDIO_DAC
- RESET_AUDIO_LOCKER
- RESET_AUDIO_PLL
- RESET_AUDIO_PLL_MODULATOR
- RESET_BISP_AXI
- RESET_BIT
- RESET_BLKMV
- RESET_BSS_EVENT_ID
- RESET_BT656
- RESET_BUS
- RESET_BUSY_CNT
- RESET_CALL_RETURN_STACK_THIS_THREAD
- RESET_CANCEL_WAIT_TIMEOUT
- RESET_CAPB3_DECODE
- RESET_CAUSE
- RESET_CAUSE_BEACON_STUCK
- RESET_CAUSE_MCU_HANG
- RESET_CAUSE_RESET_FAILED
- RESET_CAUSE_RX_BUSY
- RESET_CAUSE_RX_PSE_BUSY
- RESET_CAUSE_TX_BUSY
- RESET_CAUSE_TX_HANG
- RESET_CBUS_CAPB3
- RESET_CCPU
- RESET_CELL_CNTR
- RESET_CFG
- RESET_CFIFO
- RESET_CFIFO_RST
- RESET_CHIPID
- RESET_CIE_WATCHDOG
- RESET_CIF
- RESET_CIPHER
- RESET_CMN_BLOCK_RST_N
- RESET_CMN_I2C_RST_N
- RESET_CMN_RST_N
- RESET_CMU_DDR
- RESET_CNTL
- RESET_CNT_LIMIT
- RESET_COLOR
- RESET_COMMAND
- RESET_COMPLETE
- RESET_COMPLETE_TIME
- RESET_CONTROL_ADDRESS
- RESET_CONTROL_COLD_RST
- RESET_CONTROL_MBOX_RST
- RESET_CONTROL_MBOX_RST_MASK
- RESET_CONTROL_SI0_RST_MASK
- RESET_COPP_ID
- RESET_COPRO
- RESET_COUNT
- RESET_COUNT0
- RESET_CPPM
- RESET_CPR
- RESET_CPU_SCNT
- RESET_CREG
- RESET_CSI
- RESET_CSI0
- RESET_CSI1
- RESET_CTL
- RESET_CTL_CAT_ERROR
- RESET_CTL_DIGITAL_RST_
- RESET_CTL_READY_TO_RESET
- RESET_CTL_REQUEST_RESET
- RESET_CTRL
- RESET_CTRL_CMD_QUEUE
- RESET_CTRL_EN
- RESET_CTRL_IBI_QUEUE
- RESET_CTRL_RESP_QUEUE
- RESET_CTRL_RX_FIFO
- RESET_CTRL_SOFT
- RESET_CTRL_TX_FIFO
- RESET_DATA
- RESET_DATA_PHYS
- RESET_DBLK
- RESET_DC
- RESET_DCU_RESET
- RESET_DDR
- RESET_DDR_CTL_PHY
- RESET_DDR_CTL_PHY_AXI
- RESET_DDR_PHY
- RESET_DDR_PLL
- RESET_DDR_TOP
- RESET_DE
- RESET_DE4X5
- RESET_DELAY
- RESET_DELAY_DSM
- RESET_DEMUX
- RESET_DEMUX_0
- RESET_DEMUX_1
- RESET_DEMUX_2
- RESET_DEMUX_DES
- RESET_DEMUX_DES_PL
- RESET_DEMUX_RESET_0
- RESET_DEMUX_RESET_1
- RESET_DEMUX_RESET_2
- RESET_DEMUX_S2P_0
- RESET_DEMUX_S2P_1
- RESET_DEMUX_TOP
- RESET_DETECT
- RESET_DEV
- RESET_DEV0
- RESET_DEVICE_BUS
- RESET_DEVICE_COMMAND
- RESET_DEVICE_LUN
- RESET_DEVICE_MMC_ARB
- RESET_DEVICE_TARGET
- RESET_DMA
- RESET_DMAC
- RESET_DMC_VPU_PIPEL
- RESET_DMC_VPU_PIPL
- RESET_DMM
- RESET_DOMAIN_ATTRIBUTES
- RESET_DONE
- RESET_DOS
- RESET_DOS_CAPB3
- RESET_DOS_RESET
- RESET_DPE
- RESET_DP_TX
- RESET_DREQ_ALL
- RESET_DRP_PKT_CNTR
- RESET_DSI
- RESET_DVALIN
- RESET_DVALIN_CAPB3
- RESET_DVALIN_DMC_PIPL
- RESET_DVIN
- RESET_DVIN_RESET
- RESET_DVP
- RESET_EDP
- RESET_EFUSE
- RESET_EN
- RESET_ENABLE
- RESET_EP
- RESET_ERASED_DET
- RESET_ERROR
- RESET_ERR_CNTR
- RESET_ETHERNET
- RESET_EXT_SOFT
- RESET_FIFO
- RESET_FIRMWARE_TOV
- RESET_FLAGS
- RESET_FLG
- RESET_FREQ_MODE
- RESET_FROM_KSEG0
- RESET_FROM_KSEG1
- RESET_FX2
- RESET_GAMUT
- RESET_GE2D
- RESET_GE2D_DMC_PIPL
- RESET_GEN
- RESET_GET_BOARD_ID
- RESET_GET_BOARD_REV
- RESET_GIC
- RESET_GLOBAL_RST_N
- RESET_GPIO
- RESET_GPU3D_PA
- RESET_GPU3D_PB
- RESET_HCD
- RESET_HCFG
- RESET_HCODEC_DMC_PIPL
- RESET_HDCP
- RESET_HDCP2TX
- RESET_HDE
- RESET_HDMI
- RESET_HDMITX
- RESET_HDMITX_CAPB3
- RESET_HDMITX_PHY
- RESET_HDMI_APB
- RESET_HDMI_SYSTEM_RESET
- RESET_HDMI_TX
- RESET_HEAP
- RESET_HEVCF_DMC_PIPL
- RESET_HIU
- RESET_HOLD_TIME
- RESET_HORIZON
- RESET_HOST
- RESET_HPLL_PLL
- RESET_I2C0
- RESET_I2C1
- RESET_I2C2
- RESET_I2C3
- RESET_I2C4
- RESET_I2C5
- RESET_I2C_M0
- RESET_I2C_M1
- RESET_I2C_M2
- RESET_I2C_M3
- RESET_I2C_MASTER_1
- RESET_I2C_MASTER_2
- RESET_I2S
- RESET_IF
- RESET_IMX
- RESET_INITIATE_DRIVER
- RESET_INITIATE_FIRMWARE
- RESET_INTR
- RESET_INTR_TOV
- RESET_IPU
- RESET_IQIDCT
- RESET_IRQ_FLG
- RESET_ISA
- RESET_ISSUED
- RESET_JPEG
- RESET_JUMP_TARGET_BUFFER_THIS_THREAD
- RESET_KEY
- RESET_KIND_INIT
- RESET_KIND_SHUTDOWN
- RESET_KIND_SUSPEND
- RESET_KSV
- RESET_LCD0
- RESET_LEON
- RESET_LEVEL
- RESET_LINE
- RESET_LINK_ERROR_COUNT
- RESET_LNCNT_EN
- RESET_LOAD_REG
- RESET_LOOKUP
- RESET_LOOP_TIMEOUT
- RESET_LP_IRQC_DISABLE
- RESET_LVDS
- RESET_MAC
- RESET_MAC_2
- RESET_MAC_REQ
- RESET_MALI
- RESET_MALI_CAPB3
- RESET_MAX_RETRIES
- RESET_MBOX_STAT
- RESET_MC
- RESET_MCM
- RESET_MCPU
- RESET_MDEC
- RESET_MEDIA_CPU
- RESET_MICROC
- RESET_MIPI_0
- RESET_MIPI_1
- RESET_MIPI_2
- RESET_MIPI_3
- RESET_MIPI_DSI_HOST
- RESET_MIPI_DSI_PHY
- RESET_MIPI_HOST
- RESET_MIPI_PHY
- RESET_MISC
- RESET_MISC_PLL
- RESET_MMC
- RESET_MMC_FIRST
- RESET_MSG
- RESET_NAND
- RESET_NANDC0
- RESET_NANDC1
- RESET_NAND_CAPB3
- RESET_NIC_DMC_PIPL
- RESET_NO
- RESET_NORESPONSE
- RESET_NOTDONE
- RESET_NOTIFY
- RESET_NOTIFY_ENABLE
- RESET_NRST
- RESET_OFF
- RESET_OFFSET
- RESET_ON
- RESET_ON_TIMEOUT
- RESET_P2A_FLAGS
- RESET_PA
- RESET_PARITY_INTERRUPT_REG
- RESET_PARSER
- RESET_PARSER_CTL
- RESET_PARSER_FETCH
- RESET_PARSER_REG
- RESET_PARSER_TOP
- RESET_PASSTHRU_EN
- RESET_PCH_HANDSHAKE_ENABLE
- RESET_PCI
- RESET_PCIEA
- RESET_PCIEB
- RESET_PCIEPHY
- RESET_PCIE_A
- RESET_PCIE_APB
- RESET_PCIE_B
- RESET_PCIE_CTRL_A
- RESET_PCIE_PHY
- RESET_PCM0
- RESET_PCM1
- RESET_PENDING
- RESET_PERIPHS_ASYNC_0
- RESET_PERIPHS_ASYNC_1
- RESET_PERIPHS_GENERAL
- RESET_PERIPHS_I2C_MASTER_0
- RESET_PERIPHS_I2C_MASTER_1
- RESET_PERIPHS_I2C_MASTER_3
- RESET_PERIPHS_I2C_SLAVE
- RESET_PERIPHS_IR_REMOTE
- RESET_PERIPHS_LED_PWM
- RESET_PERIPHS_SAR_ADC
- RESET_PERIPHS_SDHC
- RESET_PERIPHS_SDIO
- RESET_PERIPHS_SMART_CARD
- RESET_PERIPHS_SPICC
- RESET_PERIPHS_SPI_0
- RESET_PERIPHS_SPI_1
- RESET_PERIPHS_STREAM_INTERFACE
- RESET_PERIPHS_UART_0
- RESET_PERIPHS_UART_1
- RESET_PERIPHS_UART_1_2
- RESET_PERSIST_MASK_FLAGS
- RESET_PHY
- RESET_PHY_PULSE
- RESET_PHY_RX_PKT_CNT
- RESET_PHY_WIDTH
- RESET_PIC_DC
- RESET_PID_FILTER
- RESET_PIN_WAKE
- RESET_PL310
- RESET_PLLA
- RESET_PLLB
- RESET_PMUX
- RESET_PORT
- RESET_PSC
- RESET_PULSE_WIDTH_10ms
- RESET_PULSE_WIDTH_1ms
- RESET_PULSE_WIDTH_2ms
- RESET_PULSE_WIDTH_500us
- RESET_QUEUES
- RESET_RDMA
- RESET_REASS
- RESET_REASS_ALL_REGS
- RESET_REASS_STATE
- RESET_RECV
- RESET_REG
- RESET_REG_UNRESET_OFFSET
- RESET_REQ_OR_DREQ
- RESET_RESERVATIONS
- RESET_RING_OSCILLATOR
- RESET_RING_VAR
- RESET_ROM_BOOT
- RESET_ROUTING_FLAG
- RESET_RTC
- RESET_RX
- RESET_RX_DMA
- RESET_RX_DMA_ERROR
- RESET_RX_FLAGS
- RESET_SANA
- RESET_SANA_3
- RESET_SATA
- RESET_SATA_LINK
- RESET_SATA_PHY
- RESET_SBUS_RECEIVER
- RESET_SC
- RESET_SCCB
- RESET_SCFG
- RESET_SCLK_CNT
- RESET_SCU
- RESET_SD
- RESET_SD0
- RESET_SD1
- RESET_SD2
- RESET_SD3
- RESET_SD_EMMC_A
- RESET_SD_EMMC_B
- RESET_SD_EMMC_C
- RESET_SE
- RESET_SECURITYPRIV
- RESET_SEG
- RESET_SEG_STATE
- RESET_SEMAPHORE
- RESET_SGDMA
- RESET_SI
- RESET_SIA
- RESET_SIG
- RESET_SIMCARD
- RESET_SOURCE_ENABLE_REG
- RESET_SPI0
- RESET_SPI1
- RESET_SPI2
- RESET_SPI3
- RESET_SPICC0
- RESET_SPICC1
- RESET_SPIFC0
- RESET_SRAMI
- RESET_STATUS
- RESET_STATUS_ALL
- RESET_STATUS_GPIO
- RESET_STATUS_HARDWARE
- RESET_STATUS_LOWPOWER
- RESET_STATUS_WATCHDOG
- RESET_STAT_INC
- RESET_STREAM
- RESET_SW_PD
- RESET_SYS_CPU
- RESET_SYS_CPU_0
- RESET_SYS_CPU_1
- RESET_SYS_CPU_2
- RESET_SYS_CPU_3
- RESET_SYS_CPU_AXI
- RESET_SYS_CPU_BVCI
- RESET_SYS_CPU_CAPB3
- RESET_SYS_CPU_CORE_0
- RESET_SYS_CPU_CORE_1
- RESET_SYS_CPU_CORE_2
- RESET_SYS_CPU_CORE_3
- RESET_SYS_CPU_L2
- RESET_SYS_CPU_MBIST
- RESET_SYS_CPU_P
- RESET_SYS_PLL
- RESET_SYS_PLL_DIV
- RESET_TIMEDOUT
- RESET_TIMEOUT
- RESET_TIMER
- RESET_TMDS
- RESET_TMPLT_HDR_SIGNATURE
- RESET_TOGGLE
- RESET_TO_HPI_ENABLE
- RESET_TO_LOWEST_VGT
- RESET_TRIES
- RESET_TRIG_TIME_0ms
- RESET_TRIG_TIME_1000ms
- RESET_TRIG_TIME_1500ms
- RESET_TRIG_TIME_2000ms
- RESET_TRIG_TIME_2500ms
- RESET_TRIG_TIME_3000ms
- RESET_TRIG_TIME_3500ms
- RESET_TRIG_TIME_4000ms
- RESET_TS_CPU
- RESET_TS_GPU
- RESET_TS_PLL
- RESET_TUNER
- RESET_TVFE
- RESET_TX
- RESET_TX_CELL_CTR
- RESET_TX_DMA_ERROR
- RESET_TX_RX_BLOCK_RST_N
- RESET_TX_RX_I2C_RST_N
- RESET_TX_RX_PIPE_RST_N
- RESET_TYPE
- RESET_TYPE_ALL
- RESET_TYPE_BB_HANG
- RESET_TYPE_BB_WATCHDOG
- RESET_TYPE_BEACON_STUCK
- RESET_TYPE_CALIBRATION
- RESET_TYPE_CPU_FAIL
- RESET_TYPE_DATAPATH
- RESET_TYPE_DISABLE
- RESET_TYPE_DMA_ERROR
- RESET_TYPE_FATAL_INT
- RESET_TYPE_GENERAL
- RESET_TYPE_HARD
- RESET_TYPE_INT_ERROR
- RESET_TYPE_INVISIBLE
- RESET_TYPE_MAC_HANG
- RESET_TYPE_MAX
- RESET_TYPE_MAX_METHOD
- RESET_TYPE_MCDI_TIMEOUT
- RESET_TYPE_MCI
- RESET_TYPE_MC_BIST
- RESET_TYPE_MC_FAILURE
- RESET_TYPE_NORESET
- RESET_TYPE_NORMAL
- RESET_TYPE_PLL_HANG
- RESET_TYPE_RECOVER_OR_ALL
- RESET_TYPE_RECOVER_OR_DISABLE
- RESET_TYPE_RX_RECOVERY
- RESET_TYPE_SHUTDOWN
- RESET_TYPE_SILENT
- RESET_TYPE_SOFTWARE
- RESET_TYPE_TX_ERROR
- RESET_TYPE_TX_GTT
- RESET_TYPE_TX_HANG
- RESET_TYPE_TX_SKIP
- RESET_TYPE_TX_WATCHDOG
- RESET_TYPE_ULP2
- RESET_TYPE_USER
- RESET_TYPE_WAKEUP
- RESET_TYPE_WARM
- RESET_TYPE_WATCHDOG
- RESET_TYPE_WORLD
- RESET_TYPE_XTAL_FAIL
- RESET_UART0
- RESET_UART1
- RESET_UART1_2
- RESET_UART2
- RESET_UART3
- RESET_UART4
- RESET_UART5
- RESET_UART6
- RESET_UART_SLIP
- RESET_UNDER_STOP_MACHINE
- RESET_UPKO_COUNT
- RESET_USB
- RESET_USB2HSIC
- RESET_USB2HUB
- RESET_USB3
- RESET_USBDEV
- RESET_USBHS
- RESET_USBHSPHY
- RESET_USBPHYA
- RESET_USBPHYB
- RESET_USB_DDR_0
- RESET_USB_DDR_1
- RESET_USB_DDR_2
- RESET_USB_DDR_3
- RESET_USB_OTG
- RESET_USB_PHY20
- RESET_USB_PHY21
- RESET_VAL
- RESET_VALUE
- RESET_VCBUS
- RESET_VCBUS_CLK81
- RESET_VDAC
- RESET_VDAC_1
- RESET_VDAC_4
- RESET_VDI6
- RESET_VD_RMEM
- RESET_VECT
- RESET_VECTOR
- RESET_VECTOR1_VADDR
- RESET_VECTOR_VADDR
- RESET_VEC_PHYS
- RESET_VEC_SIZE
- RESET_VENC
- RESET_VENCI
- RESET_VENCL
- RESET_VENCP
- RESET_VENCT
- RESET_VID2_PLL
- RESET_VIDEO
- RESET_VID_LOCK
- RESET_VID_PLL_DIV
- RESET_VIFIFO
- RESET_VIU
- RESET_VLD
- RESET_VLD_PART
- RESET_VP_IDX
- RESET_VTX_CNT
- RESET_WAIT
- RESET_WAVE420_DMC_PIPL
- RESET_WAVES
- RESET_WD1
- RESET_WD2
- RESET_WDT
- RESET_WHILE_LOADING
- RESET_XILINX
- RESETcfg
- RESETclear
- RESETflag
- RESETtime
- RESEVERED0
- RESFRC1
- RESFRC2
- RESIDENT_ATTR_FLAGS
- RESIDENT_ATTR_IS_INDEXED
- RESIDUAL_COMMAND
- RESIDUAL_SG_COMMAND
- RESIDUAL_VALID
- RESID_OVER
- RESID_UNDER
- RESIZER_INPUT_IPIPE
- RESIZER_INPUT_IPIPEIF
- RESIZER_INPUT_MEMORY
- RESIZER_INPUT_NONE
- RESIZER_INPUT_VP
- RESIZER_OUTPUT_MEMORY
- RESIZER_PADS_NUM
- RESIZER_PAD_SINK
- RESIZER_PAD_SOURCE_MEM
- RESIZE_CQ
- RESIZE_CQ_IN_SIZE
- RESIZE_CQ_LKEY_OFFSET
- RESIZE_CQ_LOG_SIZE_OFFSET
- RESIZE_DIVISOR
- RESIZE_GO
- RESIZE_HOLD_SEL
- RESIZE_PENDING
- RESM
- RESMAP_IDX_MASK
- RESMAP_MASK
- RESOLUTION
- RESOLUTION_CHANGE_DELAY
- RESOLUTION_LOC
- RESOLVED
- RESOLVE_CONFLICTS
- RESOLVE_PTR
- RESOLVE_STRUCT_OR_ARRAY
- RESOLVE_TBD
- RESOURCE_BDQ_E
- RESOURCE_CACHED_MEMORY
- RESOURCE_CMD_REQ_AGE_MASK
- RESOURCE_CMD_REQ_AGE_SHIFT
- RESOURCE_CMD_REQ_OPCODE_MASK
- RESOURCE_CMD_REQ_OPCODE_SHIFT
- RESOURCE_CMD_REQ_RESC_MASK
- RESOURCE_CMD_REQ_RESC_SHIFT
- RESOURCE_CMD_RSP_OPCODE_MASK
- RESOURCE_CMD_RSP_OPCODE_SHIFT
- RESOURCE_CMD_RSP_OWNER_MASK
- RESOURCE_CMD_RSP_OWNER_SHIFT
- RESOURCE_CODING_PROBLEM
- RESOURCE_CQS_E
- RESOURCE_DESC_SIZE_V0
- RESOURCE_DESC_SIZE_V1
- RESOURCE_DMA1_HPS
- RESOURCE_DMA2_CLP
- RESOURCE_DMA3_BRS
- RESOURCE_DUMP
- RESOURCE_ELEMENT_STRICT
- RESOURCE_EMPRESS
- RESOURCE_FACTOR_NUM_RSS_PF_E
- RESOURCE_FACTOR_RSS_PER_VF_E
- RESOURCE_GFT_PROFILES_E
- RESOURCE_ILT_E
- RESOURCE_LIMITS
- RESOURCE_LL2_QUEUE_E
- RESOURCE_MAX_NUM
- RESOURCE_MODIFIABLE
- RESOURCE_NUM_INVALID
- RESOURCE_NUM_L2_QUEUE_E
- RESOURCE_NUM_PQ_E
- RESOURCE_NUM_RL_E
- RESOURCE_NUM_RSS_ENGINES_E
- RESOURCE_NUM_SB_E
- RESOURCE_NUM_TC_E
- RESOURCE_NUM_VF_E
- RESOURCE_NUM_VMQ_E
- RESOURCE_NUM_VPORT_E
- RESOURCE_OPCODE_BUSY
- RESOURCE_OPCODE_FORCE_RELEASE
- RESOURCE_OPCODE_GNT
- RESOURCE_OPCODE_RELEASE
- RESOURCE_OPCODE_RELEASED
- RESOURCE_OPCODE_RELEASED_PREVIOUS
- RESOURCE_OPCODE_REQ
- RESOURCE_OPCODE_REQ_WO_AGING
- RESOURCE_OPCODE_REQ_W_AGING
- RESOURCE_OPCODE_UNKNOWN_CMD
- RESOURCE_OPCODE_WRONG_OWNER
- RESOURCE_OVERLAY
- RESOURCE_RDMA_STATS_QUEUE_E
- RESOURCE_UNCACHED_MEMORY
- RESOURCE_VBI
- RESOURCE_VFC_FILTER_E
- RESOURCE_VIDEO
- RESOURCE_VIDEO0
- RESOURCE_VIDEO1
- RESOURCE_VIDEO10
- RESOURCE_VIDEO11
- RESOURCE_VIDEO2
- RESOURCE_VIDEO3
- RESOURCE_VIDEO4
- RESOURCE_VIDEO5
- RESOURCE_VIDEO6
- RESOURCE_VIDEO7
- RESOURCE_VIDEO8
- RESOURCE_VIDEO9
- RESOURCE_VIDEO_READ
- RESOURCE_VIDEO_STREAM
- RESP
- RESP0
- RESP1
- RESP2
- RESPOND_BITS
- RESPOND_MASK
- RESPOND_SIZE
- RESPONSE
- RESPONSES
- RESPONSE_DATA
- RESPONSE_DEACTIVATE
- RESPONSE_ENTRIES
- RESPONSE_ENTRY_CNT
- RESPONSE_ENTRY_CNT_2100
- RESPONSE_ENTRY_CNT_2300
- RESPONSE_ENTRY_CNT_82XX
- RESPONSE_ENTRY_CNT_83XX
- RESPONSE_ENTRY_CNT_FX00
- RESPONSE_ENTRY_CNT_MQ
- RESPONSE_ENTRY_SIZE
- RESPONSE_ERROR
- RESPONSE_ERROR_ADDRESS_NACK
- RESPONSE_ERROR_CRC
- RESPONSE_ERROR_FRAME
- RESPONSE_ERROR_I2C_W_NACK_ERR
- RESPONSE_ERROR_IBA_NACK
- RESPONSE_ERROR_OVER_UNDER_FLOW
- RESPONSE_ERROR_PARITY
- RESPONSE_ERROR_TRANSF_ABORT
- RESPONSE_ID
- RESPONSE_INITIALIZE
- RESPONSE_INTERRUPT
- RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT_MASK
- RESPONSE_INTERRUPT_COUNT__N_RESPONSE_INTERRUPT_COUNT__SHIFT
- RESPONSE_IRQ_DISABLED
- RESPONSE_IRQ_ENABLED
- RESPONSE_LEN
- RESPONSE_MASK
- RESPONSE_NO_ERROR
- RESPONSE_NO_INTERRUPT
- RESPONSE_PIGGYBACKED
- RESPONSE_PIG_DISABLED
- RESPONSE_PIG_ENABLED
- RESPONSE_PORT_DATA_LEN
- RESPONSE_PORT_ERR_STATUS
- RESPONSE_PORT_TID
- RESPONSE_PROCESSED
- RESPONSE_QUEUE_DEPTH
- RESPONSE_QUEUE_PORT
- RESPONSE_Q_DOWN
- RESPONSE_RATE_BITMAP_ALL
- RESPONSE_RATE_RRSR_CCK_ONLY_1M
- RESPONSE_RECEIVED
- RESPONSE_REPORT
- RESPONSE_REPORT_SIZE
- RESPONSE_RESOLUTION
- RESPONSE_RING_SIZE
- RESPONSE_SCANFREQ
- RESPONSE_SETCONFIG
- RESPONSE_STATUS
- RESPONSE_TRANSFER_ERROR
- RESPONSE_TYPE_MASK
- RESPONSE_TYPE_SHIFT
- RESPST_ACKNOWLEDGE
- RESPST_CHK_LENGTH
- RESPST_CHK_OP_SEQ
- RESPST_CHK_OP_VALID
- RESPST_CHK_PSN
- RESPST_CHK_RESOURCE
- RESPST_CHK_RKEY
- RESPST_CLEANUP
- RESPST_COMPLETE
- RESPST_DONE
- RESPST_DUPLICATE_REQUEST
- RESPST_ERROR
- RESPST_ERR_CQ_OVERFLOW
- RESPST_ERR_LENGTH
- RESPST_ERR_MALFORMED_WQE
- RESPST_ERR_MISALIGNED_ATOMIC
- RESPST_ERR_MISSING_OPCODE_FIRST
- RESPST_ERR_MISSING_OPCODE_LAST_C
- RESPST_ERR_MISSING_OPCODE_LAST_D1E
- RESPST_ERR_PSN_OUT_OF_SEQ
- RESPST_ERR_RKEY_VIOLATION
- RESPST_ERR_RNR
- RESPST_ERR_TOO_MANY_RDMA_ATM_REQ
- RESPST_ERR_UNSUPPORTED_OPCODE
- RESPST_EXECUTE
- RESPST_EXIT
- RESPST_GET_REQ
- RESPST_NONE
- RESPST_READ_REPLY
- RESPST_RESET
- RESP_ADDRESS
- RESP_BAD_MEMADDR
- RESP_BTN_LEFT_BIT
- RESP_BTN_MIDDLE_BIT
- RESP_BTN_RIGHT_BIT
- RESP_DATA_ERR
- RESP_ENABLE_BIT
- RESP_FAILED
- RESP_FIFO_NOT_EMPTY
- RESP_FIFO_RDY
- RESP_FIFO_UNDERRUN
- RESP_HDR_INFO_OPCODE_SHIFT
- RESP_HDR_INFO_SUBSYS_SHIFT
- RESP_LENGTH
- RESP_LINKSTAT_ERRTYPE
- RESP_LINKSTAT_FDUPLEX
- RESP_LINKSTAT_SPEED
- RESP_LINKSTAT_UP
- RESP_MAC_ADDR
- RESP_MAJOR_VER
- RESP_MINOR_VER
- RESP_MKEX_PRFL_ADDR
- RESP_MKEX_PRFL_SIZE
- RESP_NACK
- RESP_NEEDED
- RESP_NONE
- RESP_NOT_IMPLEMENTED
- RESP_NOT_NEEDED
- RESP_OK
- RESP_R1
- RESP_R1B
- RESP_R2
- RESP_R3
- RESP_REMOTE_BIT
- RESP_SCALING_BIT
- RESP_SMBUS_BIT
- RESP_TIMEOUT
- RESRXFCNT
- REST
- RESTART
- RESTARTING
- RESTART_AREA
- RESTART_AREA_FLAGS
- RESTART_ARRAY_RW
- RESTART_FROZEN_DISK_IO
- RESTART_META
- RESTART_NONE
- RESTART_PAGE_HEADER
- RESTART_REQUEST_ENABLED
- RESTART_SPACE_FILLER
- RESTART_TRANS
- RESTART_VOLUME_IS_CLEAN
- RESTORE
- RESTOREEXR
- RESTOREREGS
- RESTORE_ABI_STATE
- RESTORE_ALL
- RESTORE_ALL_NMI
- RESTORE_ASI
- RESTORE_BREAK_REGS
- RESTORE_COMPLETE
- RESTORE_CTR
- RESTORE_FACTORY_DEFAULTS_FORMATTER
- RESTORE_GRAPH_ARGS
- RESTORE_GRAPH_REG_ARGS
- RESTORE_INT_REGS
- RESTORE_LOGLEVEL
- RESTORE_MAGIC
- RESTORE_MAS7
- RESTORE_MMU_REGS
- RESTORE_POINTERS
- RESTORE_PPR_PACA
- RESTORE_REG
- RESTORE_REGION_REGS
- RESTORE_REGISTER
- RESTORE_REGS
- RESTORE_REGS_GP
- RESTORE_REGS_RTBD
- RESTORE_REGS_STRING
- RESTORE_RENAMED_REGS
- RESTORE_RET_ABI_STATE
- RESTORE_SPECIAL
- RESTORE_SPR
- RESTORE_STATE
- RESTORE_TOC
- RESTORE_USER_DEFAULTS_FORMATTER
- RESTORE_XMM
- RESTORE_xSRR
- RESTRICTED_PARENT
- RESTRICT_TO_RANGE
- RESTXFCNT
- RESTYPE
- REST_10GPRS
- REST_16EVRS
- REST_16FPRS
- REST_16VRS
- REST_16VSRS
- REST_2EVRS
- REST_2FPRS
- REST_2GPRS
- REST_2VRS
- REST_2VSRS
- REST_32EVRS
- REST_32FPRS
- REST_32FPRS_VSRS
- REST_32FPVSRS
- REST_32VRS
- REST_32VSRS
- REST_4EVRS
- REST_4FPRS
- REST_4GPRS
- REST_4VRS
- REST_4VSRS
- REST_8EVRS
- REST_8FPRS
- REST_8GPRS
- REST_8VRS
- REST_8VSRS
- REST_CR
- REST_EVR
- REST_FPR
- REST_GPR
- REST_NVGPRS
- REST_SP
- REST_VR
- REST_VSR
- RESUBMIT
- RESUBMIT_DELAY
- RESULTS_DUMP_SHIFT
- RESULT_ALREADY_RUNNING
- RESULT_CONNECT
- RESULT_DISCONNECT
- RESULT_FAIL
- RESULT_INVALID_PARAMETERS
- RESULT_NOT_SUPPORTED
- RESULT_OFFSET
- RESULT_OK
- RESULT_PIPE
- RESULT_STATUS_MASK
- RESULT_SUCCESS
- RESULT_UNSUP_CARD
- RESULT_UNSUP_HOST
- RESULT_VALUE_MASK
- RESUME
- RESUME_BT_ADDR
- RESUME_ENABLE_ADDR
- RESUME_ENABLE_VAL
- RESUME_ENTRIES
- RESUME_FLAG_ARCH1
- RESUME_FLAG_ARCH2
- RESUME_FLAG_DR
- RESUME_FLAG_HOST
- RESUME_FLAG_NV
- RESUME_FLG
- RESUME_FROM_SUSP
- RESUME_GUEST
- RESUME_GUEST_DR
- RESUME_GUEST_NV
- RESUME_HOST
- RESUME_HOST_NV
- RESUME_INDEX_FCFI
- RESUME_INDEX_RPI
- RESUME_INDEX_VFI
- RESUME_INDEX_VPI
- RESUME_INDICATE
- RESUME_INTERRUPT
- RESUME_INTERRUPT_ENABLE
- RESUME_INTR
- RESUME_PAGE_FAULT
- RESUME_PASSTHROUGH
- RESUME_RX0
- RESUME_TERMINATE
- RESUME_TO_HPI_ENABLE
- RESUME_TX
- RESUME_UNKNOWN_ADDR
- RESUME_VECTOR_ADDR
- RESV0
- RESV1
- RESV2
- RESVEC
- RESVED_PTE
- RESYNC
- RESYNCING
- RESYNC_AFTER_NEG
- RESYNC_BLOCK_SIZE
- RESYNC_DEPTH
- RESYNC_MASK
- RESYNC_PAGES
- RESYNC_SECTORS
- RESYNC_SRC_CK_INV_MASK
- RESYNC_SRC_CK_INV_MASK_SFT
- RESYNC_SRC_CK_INV_SFT
- RESYNC_SRC_SEL_MASK
- RESYNC_SRC_SEL_MASK_SFT
- RESYNC_SRC_SEL_SFT
- RESYNC_WINDOW
- RESYNC_WINDOW_SECTORS
- RESZ_PADS_NUM
- RESZ_PAD_SINK
- RESZ_PAD_SOURCE
- RES_12BIT
- RES_32KCLKOUT
- RES_8BIT
- RES_ADDRESS_INVALID
- RES_ADDRESS_IOAFP
- RES_ANY_BUSY
- RES_BUS
- RES_CHANGE_ADD
- RES_CHANGE_DEL
- RES_CLKEN
- RES_COUNTER
- RES_COUNTER_ALLOCATED
- RES_COUNTER_BUSY
- RES_CQ
- RES_CQ_ALLOCATED
- RES_CQ_BUSY
- RES_CQ_HW
- RES_CTRL_REG1
- RES_DATA
- RES_DATA_CTRL
- RES_DEV_ID
- RES_DID
- RES_DINODE
- RES_DRD_ID
- RES_DRV
- RES_EATTR
- RES_ENDMSG
- RES_ENET_CSR
- RES_EOM_L
- RES_EQ
- RES_EQ_BUSY
- RES_EQ_HW
- RES_EQ_RESERVED
- RES_ERR
- RES_EXT_INT
- RES_FAILCNT
- RES_FS_RULE
- RES_FS_RULE_ALLOCATED
- RES_FS_RULE_BUSY
- RES_GET_FUNCS
- RES_GRP_ALL
- RES_GRP_PP
- RES_GRP_PP_PR
- RES_GRP_PP_RC
- RES_GRP_PR
- RES_GRP_RC
- RES_GRP_RC_PR
- RES_GRP_RES
- RES_HANDLE_IOA
- RES_HANDLE_NONE
- RES_HFCLKOUT
- RES_HOST_ID
- RES_H_IUS
- RES_INDIRECT
- RES_INT_CTRL1
- RES_IRQ_HOST_ID
- RES_IRQ_OTG_ID
- RES_IRQ_PERIPHERAL_ID
- RES_ISP
- RES_IS_AFDASD
- RES_IS_GSCSI
- RES_IS_IOA
- RES_IS_VSET
- RES_JDATA
- RES_JPEG
- RES_LEAF
- RES_LIMIT
- RES_LUN
- RES_MAC
- RES_MAIN_REF
- RES_MASK
- RES_MAX_USAGE
- RES_MEM
- RES_MPT
- RES_MPT_BUSY
- RES_MPT_HW
- RES_MPT_MAPPED
- RES_MPT_RESERVED
- RES_MTT
- RES_MTT_ALLOCATED
- RES_MTT_BUSY
- RES_NODE
- RES_NOK
- RES_NONE
- RES_NPORT_ID
- RES_NRES_PWRON
- RES_OK
- RES_OP_MAP_ICM
- RES_OP_RESERVE
- RES_OP_RESERVE_AND_MAP
- RES_PORT
- RES_QP
- RES_QP_BUSY
- RES_QP_HW
- RES_QP_MAPPED
- RES_QP_RESERVED
- RES_QUEUE_DEPTH
- RES_QUEUE_LEN
- RES_QUOTA
- RES_REGEN
- RES_RESET
- RES_RG_BIT
- RES_RG_HDR
- RES_RING_CMD
- RES_RING_CSR
- RES_RxINT_FC
- RES_Rx_CRC
- RES_SOFT_LIMIT
- RES_SRQ
- RES_SRQ_ALLOCATED
- RES_SRQ_BUSY
- RES_SRQ_HW
- RES_STATE_ACTIVE
- RES_STATE_OFF
- RES_STATE_SLEEP
- RES_STATE_WRST
- RES_STATFS
- RES_SYSEN
- RES_TARGET
- RES_TARGET_LNX
- RES_TO_U32_HIGH
- RES_TO_U32_LOW
- RES_TR_FREE_ALL
- RES_TR_FREE_SLAVES_ONLY
- RES_TR_FREE_STRUCTS_ONLY
- RES_TYPE2_R0
- RES_TYPE2_R1
- RES_TYPE2_R2
- RES_TYPE_AF_DASD
- RES_TYPE_ALL
- RES_TYPE_CQ
- RES_TYPE_DEPRECATED1
- RES_TYPE_DEPRECATED2
- RES_TYPE_DEVCMD
- RES_TYPE_DEVCMD2
- RES_TYPE_EOL
- RES_TYPE_GSCSI
- RES_TYPE_INTR_CTRL
- RES_TYPE_INTR_PBA
- RES_TYPE_INTR_PBA_LEGACY
- RES_TYPE_INTR_TABLE
- RES_TYPE_IOA_FP
- RES_TYPE_MAX
- RES_TYPE_MQ_CQ
- RES_TYPE_MQ_RQ
- RES_TYPE_MQ_WQ
- RES_TYPE_NIC_CFG
- RES_TYPE_PASS_THRU_PAGE
- RES_TYPE_R0
- RES_TYPE_RQ
- RES_TYPE_RSVD1
- RES_TYPE_RSVD2
- RES_TYPE_RSVD3
- RES_TYPE_RSVD4
- RES_TYPE_RSVD5
- RES_TYPE_RSVD6
- RES_TYPE_RSVD7
- RES_TYPE_SUBVNIC
- RES_TYPE_VENCLOSURE
- RES_TYPE_VSET
- RES_TYPE_WQ
- RES_Tx_CRC
- RES_Tx_P
- RES_UNKNOWN
- RES_USAGE
- RES_VAUX1
- RES_VAUX2
- RES_VAUX3
- RES_VAUX4
- RES_VDAC
- RES_VDD1
- RES_VDD2
- RES_VINTANA1
- RES_VINTANA2
- RES_VINTDIG
- RES_VIO
- RES_VLAN
- RES_VMMC1
- RES_VMMC2
- RES_VPLL1
- RES_VPLL2
- RES_VSIM
- RES_VUSBCP
- RES_VUSB_1V5
- RES_VUSB_1V8
- RES_VUSB_3V1
- RES_V_POS
- RES_X
- RES_XRCD
- RES_XRCD_ALLOCATED
- RES_XRCD_BUSY
- RES_Y
- RES_Z2CT0
- RES_Z2CT1
- RES_Z2CT2
- RET
- RETAIN_MEM
- RETAIN_PERIPH
- RETB_ENBL
- RETCODE_SIZE
- RETH_PRN
- RETIMER_REDRIVER_INFO
- RETPOLINE_EDX_BPF_JIT
- RETPOLINE_NONE
- RETPOLINE_RAX_BPF_JIT
- RETPOLINE_RAX_BPF_JIT_SIZE
- RETRAIN_WAIT_MAX_RETRIES
- RETRAIN_WAIT_USLEEP_US
- RETRIES
- RETRIEVE_FAT
- RETRIGGER_BIT
- RETRIM_MASK
- RETRIM_SHIFT
- RETRY
- RETRYCHAN
- RETRYCTR
- RETRYSIZE
- RETRY_1
- RETRY_A
- RETRY_B
- RETRY_CNT
- RETRY_COUNT
- RETRY_COUNTER
- RETRY_DELAY
- RETRY_LIM
- RETRY_LIMIT
- RETRY_LIMIT_LONG_MASK
- RETRY_LIMIT_LONG_SHIFT
- RETRY_LIMIT_SHORT_MASK
- RETRY_LIMIT_SHORT_SHIFT
- RETRY_LONG
- RETRY_LONG_DEF
- RETRY_LONG_FB
- RETRY_MASK
- RETRY_MAX
- RETRY_SHORT
- RETRY_SHORT_DEF
- RETRY_SHORT_FB
- RETRY_SHORT_MAX
- RETRY_TASK
- RETRY_TIMER
- RETRY_UNLIMITED
- RETRY_US_HI
- RETRY_US_LO
- RETRY_WAIT_CNT
- RETRY_X
- RETST
- RETUNING_TIMER_CNT_MAX
- RETURN
- RETURN_ALL
- RETURN_BACK
- RETURN_CMD
- RETURN_FAMILY_TEST
- RETURN_FILE
- RETURN_FIRST_TUPLE
- RETURN_FROM_TEST
- RETURN_FSID
- RETURN_MASK
- RETURN_STATUS
- RETU_INT_PWR
- RETU_REG_ASICR
- RETU_REG_ASICR_VILMA
- RETU_REG_CC1
- RETU_REG_IDR
- RETU_REG_IMR
- RETU_REG_STATUS
- RETU_REG_WATCHDOG
- RETU_STATUS_PWRONX
- RETU_WDT_MAX_TIMER
- RETVALREG
- RETVAL_DATA_ERROR
- RETVAL_LAST_BLOCK
- RETVAL_NOT_BZIP_DATA
- RETVAL_OBSOLETE_INPUT
- RETVAL_OK
- RETVAL_OUT_OF_MEMORY
- RETVAL_UNEXPECTED_INPUT_EOF
- RETVAL_UNEXPECTED_OUTPUT_EOF
- RET_CFG_REG
- RET_DDCB_APPENDED
- RET_DDCB_TAPPED
- RET_ENDP
- RET_ERROR
- RET_FAIL
- RET_FROM_EXC_LEVEL
- RET_INTEGER
- RET_PARTIAL_SGLIST
- RET_PASS
- RET_PF_EMULATE
- RET_PF_INVALID
- RET_PF_RETRY
- RET_PTR_TO_MAP_VALUE
- RET_PTR_TO_MAP_VALUE_OR_NULL
- RET_PTR_TO_SOCKET_OR_NULL
- RET_PTR_TO_SOCK_COMMON_OR_NULL
- RET_PTR_TO_TCP_SOCK_OR_NULL
- RET_SIZE
- RET_VAL_COUNT
- RET_VOID
- REUSEPORT_ARRAY_SIZE
- REUSEPORT_FD_IDX
- REUSEPORT_MIN_ID
- REUSE_SKBUFFS_WITHOUT_FREE
- REUSE_SPD_EN
- REV
- REV2MIN
- REV4
- REV8
- REVDRIVE
- REVERSE
- REVERSE_BIT
- REVERSE_HEARTBEAT_TIMEOUT
- REVERSE_POLARITY
- REVERT_TO_REFA
- REVE_WIDTH_128
- REVID
- REVIDREG
- REVID_FOREVER
- REVID_MASK
- REVID_SHIFT
- REVISION
- REVISION_B2_B3
- REVISION_C1
- REVISION_ID
- REVISION_ID_CHT_A0
- REVISION_ID_CHT_Ax_SI
- REVISION_ID_CHT_B0
- REVISION_ID_CHT_Bx_SI
- REVISION_ID_CHT_Dx_SI
- REVISION_ID_CHT_Kx_SI
- REVISION_ID_SI_MASK
- REVISION_ID_SPARROW_B0
- REVISION_ID_SPARROW_D0
- REVISION_ID__MAJOR_REV_ID_MASK
- REVISION_ID__MAJOR_REV_ID__MASK
- REVISION_ID__MAJOR_REV_ID__SHIFT
- REVISION_ID__MINOR_REV_ID_MASK
- REVISION_ID__MINOR_REV_ID__MASK
- REVISION_ID__MINOR_REV_ID__SHIFT
- REVISION_MASK
- REVISION_REG
- REVISION_SHIFT
- REVISION__VALUE
- REVISIT_24XX
- REVISON_BITS
- REVO_DEVICE_DESC
- REVPOL
- REV_A_CODE_MEMORY_BEGIN
- REV_A_CODE_MEMORY_END
- REV_A_CODE_MEMORY_LENGTH
- REV_A_CODE_MEMORY_UNIT_LENGTH
- REV_A_DATA_MEMORY_BEGIN
- REV_A_DATA_MEMORY_END
- REV_A_DATA_MEMORY_LENGTH
- REV_A_DATA_MEMORY_UNIT_LENGTH
- REV_B1
- REV_BST_CHG_GONE
- REV_B_CODE_MEMORY_BEGIN
- REV_B_CODE_MEMORY_END
- REV_B_CODE_MEMORY_LENGTH
- REV_B_CODE_MEMORY_UNIT_LENGTH
- REV_B_DATA_MEMORY_BEGIN
- REV_B_DATA_MEMORY_END
- REV_B_DATA_MEMORY_LENGTH
- REV_B_DATA_MEMORY_UNIT_LENGTH
- REV_CHIPID_MASK
- REV_CHIPID_SHIFT
- REV_CHIP_TYPE
- REV_CNTL
- REV_CX24113
- REV_FMT
- REV_G
- REV_HW
- REV_ID
- REV_ID_CHIPREV_SHIFT
- REV_ID_MAJOR_AR71XX
- REV_ID_MAJOR_AR7240
- REV_ID_MAJOR_AR7241
- REV_ID_MAJOR_AR7242
- REV_ID_MAJOR_AR913X
- REV_ID_MAJOR_AR9330
- REV_ID_MAJOR_AR9331
- REV_ID_MAJOR_AR9341
- REV_ID_MAJOR_AR9342
- REV_ID_MAJOR_AR9344
- REV_ID_MAJOR_MASK
- REV_ID_MAJOR_QCA9533
- REV_ID_MAJOR_QCA9533_V2
- REV_ID_MAJOR_QCA9556
- REV_ID_MAJOR_QCA9558
- REV_ID_MAJOR_QCA956X
- REV_ID_MAJOR_TP9343
- REV_ID_MASK
- REV_ID_NICREV_SHIFT
- REV_ID_NICROLL_SHIFT
- REV_ID_PID
- REV_ID_REV_MAJOR
- REV_ID_REV_MINOR
- REV_ID_VID
- REV_ID_VT3119_A0
- REV_ID_VT3119_A1
- REV_ID_VT3216_A0
- REV_ID_VT3253_A0
- REV_ID_VT3253_A1
- REV_ID_VT3253_B0
- REV_ID_VT3253_B1
- REV_ID_VT6110
- REV_ID_XGREV_SHIFT
- REV_ID_XGROLL_SHIFT
- REV_M
- REV_MAJOR
- REV_MASK
- REV_MINOR
- REV_NUMBER
- REV_PCI_ORDER
- REV_PIXELS_MASK1
- REV_PIXELS_MASK2
- REV_PIXELS_MASK4
- REV_PRODUCT_ID
- REV_REG
- REV_REVID_MASK
- REV_REVID_SHIFT
- REV_RT2860C
- REV_RT2860D
- REV_RT2872E
- REV_RT3070E
- REV_RT3070F
- REV_RT3071E
- REV_RT3090E
- REV_RT3390E
- REV_RT3593E
- REV_RT5370G
- REV_RT5390F
- REV_RT5390R
- REV_RT5592C
- REV_S
- REV_SHIFT
- REV_V
- REV_VENDOR_ID
- REW
- REWIND
- REWIND_DIS
- REWIND_UNLOAD
- REWRITE_HW_ACTION_NUM
- REW_DSCP_CFG
- REW_DSCP_CFG_GSZ
- REW_DSCP_REMAP_CFG
- REW_DSCP_REMAP_CFG_RSZ
- REW_DSCP_REMAP_DP1_CFG
- REW_DSCP_REMAP_DP1_CFG_RSZ
- REW_PCP_DEI_QOS_MAP_CFG
- REW_PCP_DEI_QOS_MAP_CFG_DEI_QOS_VAL
- REW_PCP_DEI_QOS_MAP_CFG_GSZ
- REW_PCP_DEI_QOS_MAP_CFG_PCP_QOS_VAL
- REW_PCP_DEI_QOS_MAP_CFG_PCP_QOS_VAL_M
- REW_PCP_DEI_QOS_MAP_CFG_RSZ
- REW_PORT_CFG
- REW_PORT_CFG_AGE_DIS
- REW_PORT_CFG_ES0_EN
- REW_PORT_CFG_FCS_UPDATE_CPU_ENA
- REW_PORT_CFG_FCS_UPDATE_NONCPU_CFG
- REW_PORT_CFG_FCS_UPDATE_NONCPU_CFG_M
- REW_PORT_CFG_FCS_UPDATE_NONCPU_CFG_X
- REW_PORT_CFG_FLUSH_ENA
- REW_PORT_CFG_GSZ
- REW_PORT_VLAN_CFG
- REW_PORT_VLAN_CFG_GSZ
- REW_PORT_VLAN_CFG_PORT_DEI
- REW_PORT_VLAN_CFG_PORT_PCP
- REW_PORT_VLAN_CFG_PORT_PCP_M
- REW_PORT_VLAN_CFG_PORT_PCP_X
- REW_PORT_VLAN_CFG_PORT_TPID
- REW_PORT_VLAN_CFG_PORT_TPID_M
- REW_PORT_VLAN_CFG_PORT_TPID_X
- REW_PORT_VLAN_CFG_PORT_VID
- REW_PORT_VLAN_CFG_PORT_VID_M
- REW_PPT
- REW_PPT_RSZ
- REW_PTP_CFG
- REW_PTP_CFG_GP_CFG_UNUSED
- REW_PTP_CFG_GP_CFG_UNUSED_M
- REW_PTP_CFG_GP_CFG_UNUSED_X
- REW_PTP_CFG_GSZ
- REW_PTP_CFG_PTP_1STEP_DIS
- REW_PTP_CFG_PTP_2STEP_DIS
- REW_PTP_CFG_PTP_BACKPLANE_MODE
- REW_PTP_CFG_PTP_UDP_KEEP
- REW_PTP_DLY1_CFG
- REW_PTP_DLY1_CFG_GSZ
- REW_RED_TAG_CFG
- REW_RED_TAG_CFG_GSZ
- REW_RED_TAG_CFG_RED_TAG_CFG
- REW_REW_STICKY
- REW_REW_STICKY_ES0_TAGB_PUSH_FAILED
- REW_STAT_CFG
- REW_TAG_CFG
- REW_TAG_CFG_GSZ
- REW_TAG_CFG_TAG_CFG
- REW_TAG_CFG_TAG_CFG_M
- REW_TAG_CFG_TAG_CFG_X
- REW_TAG_CFG_TAG_DEI_CFG
- REW_TAG_CFG_TAG_DEI_CFG_M
- REW_TAG_CFG_TAG_PCP_CFG
- REW_TAG_CFG_TAG_PCP_CFG_M
- REW_TAG_CFG_TAG_PCP_CFG_X
- REW_TAG_CFG_TAG_TPID_CFG
- REW_TAG_CFG_TAG_TPID_CFG_M
- REW_TAG_CFG_TAG_TPID_CFG_X
- REW_TAG_CFG_TAG_VID_CFG
- REXMIT_LOST
- REXMIT_NEW
- REXMIT_NONE
- REXPCAP
- REXT
- REXTVALID
- REX_LCOL
- REX_PRE
- REX_PREFIX
- REX_PROM_BOOTINIT
- REX_PROM_BOOTREAD
- REX_PROM_CLEARCACHE
- REX_PROM_GETBITMAP
- REX_PROM_GETCHAR
- REX_PROM_GETENV
- REX_PROM_GETSYSID
- REX_PROM_GETTCINFO
- REX_PROM_MAGIC
- REX_PROM_PRINTF
- REX_PROM_SLOTADDR
- REX_RTRY
- REX_UFLO
- REZERO_COMMAND
- REZERO_UNIT
- RE_2_RE
- RE_2_RE__VALUE
- RE_2_WE
- RE_2_WE__VALUE
- RE_ADD
- RE_ENTRANT_CHECK_OFF
- RE_ENTRANT_CHECK_ON
- RE_FIT_TYPE
- RE_INIT_ADAPTER
- RE_INIT_LL
- RE_IRQ_ENABLE
- RE_MASK
- RE_NEG_NOW
- RE_REG_IMM
- RE_REG_IMM_MAX
- RE_REG_IMM_encode
- RE_REG_LM
- RE_REG_LM_IDX
- RE_REG_LM_IDX_MAX
- RE_REG_NO_DST
- RE_REG_XFR
- RE_SH
- RE_Z
- RF1
- RF18_BAND_2G
- RF18_BAND_5G
- RF18_BAND_MASK
- RF18_BW_20M
- RF18_BW_40M
- RF18_BW_80M
- RF18_BW_MASK
- RF18_CHANNEL_MASK
- RF18_RFSI_GE_CH80
- RF18_RFSI_GT_CH140
- RF18_RFSI_GT_CH144
- RF18_RFSI_MASK
- RF1_MT9V011_CHIP_ENABLE
- RF1_TUNER
- RF2
- RF2020
- RF2420
- RF2421
- RF2522
- RF2523
- RF2524
- RF2525
- RF2525E
- RF2527
- RF2528
- RF2529
- RF2720
- RF2750
- RF2820
- RF2850
- RF2853
- RF2959_RF
- RF2_ANTENNA_RX1
- RF2_ANTENNA_RX2
- RF2_ANTENNA_TX1
- RF3
- RF3000_CCA_CTRL
- RF3000_DIVERSITY__RSSI
- RF3000_HIGH_GAIN_CALIB
- RF3000_LOW_GAIN_CALIB
- RF3000_MODEM_CTRL__RX_STATUS
- RF3000_RX_LEN_LSB
- RF3000_RX_LEN_MSB
- RF3000_RX_SERVICE_FIELD
- RF3000_RX_SIGNAL_FIELD
- RF3000_TX_LEN_LSB
- RF3000_TX_LEN_MSB
- RF3000_TX_VAR_GAIN__TX_LEN_EXT
- RF3020
- RF3021
- RF3022
- RF3052
- RF3053
- RF3070
- RF3290
- RF3320
- RF3322
- RF3322_RFCSR30_RX_H20M
- RF3322_RFCSR30_TX_H20M
- RF3853
- RF3_TUNER
- RF3_TXPOWER
- RF3_TXPOWER_A
- RF3_TXPOWER_A_7DBM_BOOST
- RF3_TXPOWER_G
- RF4_FREQ_OFFSET
- RF4_HT40
- RF4_TXPOWER_A
- RF4_TXPOWER_A_7DBM_BOOST
- RF4_TXPOWER_G
- RF5222
- RF5225
- RF5226
- RF5325
- RF5350
- RF5360
- RF5362
- RF5370
- RF5372
- RF5390
- RF5392
- RF5592
- RF5C_CHIP_ID
- RF5C_CHIP_RF5C296
- RF5C_CHIP_RF5C396
- RF5C_IO_OFF
- RF5C_MCTL3_DISABLE
- RF5C_MCTL3_DMA_ENA
- RF5C_MODE_3STATE_BIT7
- RF5C_MODE_ATA
- RF5C_MODE_CA21
- RF5C_MODE_CA22
- RF5C_MODE_CA23
- RF5C_MODE_CA24
- RF5C_MODE_CA25
- RF5C_MODE_CTL
- RF5C_MODE_CTL_3
- RF5C_MODE_LED_ENA
- RF5C_PWR_5V_DET
- RF5C_PWR_CTL
- RF5C_PWR_DREQ_INPACK
- RF5C_PWR_DREQ_IOIS16
- RF5C_PWR_DREQ_LOW
- RF5C_PWR_DREQ_OFF
- RF5C_PWR_DREQ_SPKR
- RF5C_PWR_INPACK_ENA
- RF5C_PWR_IREQ_HIGH
- RF5C_PWR_TC_SEL
- RF5C_PWR_VCC_3V
- RF6052_MAX_PATH
- RF6052_MAX_REG
- RF6052_MAX_REG_88E
- RF6052_MAX_REG_92C
- RF6052_MAX_TX_PWR
- RF6052_REG_AC
- RF6052_REG_BIAS
- RF6052_REG_BS_IQGEN
- RF6052_REG_BS_PA_APSET_G1_G4
- RF6052_REG_BS_PA_APSET_G5_G8
- RF6052_REG_BS_PA_APSET_G9_G11
- RF6052_REG_GAIN_RX
- RF6052_REG_GAIN_TX
- RF6052_REG_IPA
- RF6052_REG_IPA_A
- RF6052_REG_IPA_G
- RF6052_REG_IQADJ_G1
- RF6052_REG_IQADJ_G2
- RF6052_REG_MODE1
- RF6052_REG_MODE2
- RF6052_REG_MODE_AG
- RF6052_REG_POW_ABILITY
- RF6052_REG_POW_TRSW
- RF6052_REG_RCK1
- RF6052_REG_RCK2
- RF6052_REG_RCK_OS
- RF6052_REG_RX_AGC_HP
- RF6052_REG_RX_BB1
- RF6052_REG_RX_BB2
- RF6052_REG_RX_G1
- RF6052_REG_RX_G2
- RF6052_REG_S0S1
- RF6052_REG_SYN_G1
- RF6052_REG_SYN_G2
- RF6052_REG_SYN_G3
- RF6052_REG_SYN_G4
- RF6052_REG_SYN_G5
- RF6052_REG_SYN_G6
- RF6052_REG_SYN_G7
- RF6052_REG_SYN_G8
- RF6052_REG_TOP
- RF6052_REG_TXBIAS
- RF6052_REG_TXBIAS_A
- RF6052_REG_TXBIAS_G
- RF6052_REG_TXM_IDAC
- RF6052_REG_TXPA_AG
- RF6052_REG_TXPA_G1
- RF6052_REG_TXPA_G2
- RF6052_REG_TXPA_G3
- RF6052_REG_TX_AGC
- RF6052_REG_TX_BB1
- RF6052_REG_TX_G1
- RF6052_REG_TX_G2
- RF6052_REG_TX_G3
- RF6052_REG_T_METER
- RF6052_REG_T_METER_8723B
- RF6052_REG_UNKNOWN_43
- RF6052_REG_UNKNOWN_55
- RF6052_REG_UNKNOWN_56
- RF6052_REG_UNKNOWN_DF
- RF6052_REG_UNKNOWN_ED
- RF6052_REG_WE_LUT
- RF69_ENUM_H
- RF69_H
- RF7620
- RF90_PATH_A
- RF90_PATH_B
- RF90_PATH_C
- RF90_PATH_D
- RF90_PATH_MAX
- RF90_RADIO_PATH
- RFAAB
- RFAAM
- RFAAP
- RFAA_shift
- RFADDR_shift
- RFALSE
- RFANAEN
- RFA_CEIL
- RFA_ENCLKRFAGC
- RFA_FLR
- RFA_FULL_MINUS_1K
- RFA_FULL_MINUS_2K
- RFA_FULL_MINUS_3K
- RFA_FULL_MINUS_4K
- RFA_FULL_MINUS_5K
- RFA_FULL_MINUS_6K
- RFA_FULL_MINUS_7K
- RFA_RSSI_REF
- RFA_RSSI_REFH
- RFA_RSSI_REFL
- RFBE_MASK
- RFC
- RFC1001_NAME_LEN
- RFC1001_NAME_LEN_WITH_NULL
- RFC1001_PORT
- RFC1002_INSUFFICIENT_RESOURCE
- RFC1002_LENGTH_EXTEND
- RFC1002_NEGATIVE_SESSION_RESPONSE
- RFC1002_NOT_LISTENING_CALLED
- RFC1002_NOT_LISTENING_CALLING
- RFC1002_NOT_PRESENT
- RFC1002_POSITIVE_SESSION_RESPONSE
- RFC1002_RETARGET_SESSION_RESPONSE
- RFC1002_SESSION_KEEP_ALIVE
- RFC1002_SESSION_MESSAGE
- RFC1002_SESSION_REQUEST
- RFC1002_UNSPECIFIED_ERROR
- RFC1042_ENCAP
- RFC1051_HDR_SIZE
- RFC1201_HDR_SIZE
- RFC1483LLC_LEN
- RFC1626_MTU
- RFC2374_FRAG_HDR_SIZE
- RFC2374_FRAG_OVERHEAD
- RFC2374_HDR_FIRSTFRAG
- RFC2374_HDR_INTFRAG
- RFC2374_HDR_LASTFRAG
- RFC2374_HDR_UNFRAG
- RFC2374_UNFRAG_HDR_SIZE
- RFC2440_CIPHER_AES_128
- RFC2440_CIPHER_AES_192
- RFC2440_CIPHER_AES_256
- RFC2440_CIPHER_BLOWFISH
- RFC2440_CIPHER_CAST_5
- RFC2440_CIPHER_CAST_6
- RFC2440_CIPHER_DES3_EDE
- RFC2440_CIPHER_RSA
- RFC2440_CIPHER_TWOFISH
- RFC2734_SW_VERSION
- RFC3146_SW_VERSION
- RFC4106_HASH_SUBKEY_SIZE
- RFC4543_ICV_SIZE
- RFCC_CHIP0_PU
- RFCC_OE_POR_FORCE
- RFCC_POR_FORCE
- RFCF
- RFCOFF
- RFCOMMCREATEDEV
- RFCOMMGETDEVINFO
- RFCOMMGETDEVLIST
- RFCOMMRELEASEDEV
- RFCOMMSTEALDLC
- RFCOMM_AUTH_ACCEPT
- RFCOMM_AUTH_PENDING
- RFCOMM_AUTH_REJECT
- RFCOMM_AUTH_TIMEOUT
- RFCOMM_CFC_DISABLED
- RFCOMM_CFC_ENABLED
- RFCOMM_CFC_UNKNOWN
- RFCOMM_CONNINFO
- RFCOMM_CONN_TIMEOUT
- RFCOMM_DEFAULT_CREDITS
- RFCOMM_DEFAULT_MTU
- RFCOMM_DEFER_SETUP
- RFCOMM_DEFUNCT_BIT4
- RFCOMM_DEV_RELEASED
- RFCOMM_DISC
- RFCOMM_DISC_TIMEOUT
- RFCOMM_DM
- RFCOMM_ENC_DROP
- RFCOMM_FCOFF
- RFCOMM_FCON
- RFCOMM_HANGUP_NOW
- RFCOMM_IDLE_TIMEOUT
- RFCOMM_LM
- RFCOMM_LM_AUTH
- RFCOMM_LM_ENCRYPT
- RFCOMM_LM_FIPS
- RFCOMM_LM_MASTER
- RFCOMM_LM_RELIABLE
- RFCOMM_LM_SECURE
- RFCOMM_LM_TRUSTED
- RFCOMM_MAX_CREDITS
- RFCOMM_MAX_DEV
- RFCOMM_MAX_L2CAP_MTU
- RFCOMM_MSC
- RFCOMM_MSCEX_OK
- RFCOMM_MSCEX_RX
- RFCOMM_MSCEX_TX
- RFCOMM_MSC_PENDING
- RFCOMM_NSC
- RFCOMM_PN
- RFCOMM_RELEASE_ONHUP
- RFCOMM_REUSE_DLC
- RFCOMM_RLS
- RFCOMM_RPN
- RFCOMM_RPN_BR_115200
- RFCOMM_RPN_BR_19200
- RFCOMM_RPN_BR_230400
- RFCOMM_RPN_BR_2400
- RFCOMM_RPN_BR_38400
- RFCOMM_RPN_BR_4800
- RFCOMM_RPN_BR_57600
- RFCOMM_RPN_BR_7200
- RFCOMM_RPN_BR_9600
- RFCOMM_RPN_DATA_5
- RFCOMM_RPN_DATA_6
- RFCOMM_RPN_DATA_7
- RFCOMM_RPN_DATA_8
- RFCOMM_RPN_FLOW_NONE
- RFCOMM_RPN_PARITY_EVEN
- RFCOMM_RPN_PARITY_MARK
- RFCOMM_RPN_PARITY_NONE
- RFCOMM_RPN_PARITY_ODD
- RFCOMM_RPN_PARITY_SPACE
- RFCOMM_RPN_PM_ALL
- RFCOMM_RPN_PM_BITRATE
- RFCOMM_RPN_PM_DATA
- RFCOMM_RPN_PM_FLOW
- RFCOMM_RPN_PM_PARITY
- RFCOMM_RPN_PM_PARITY_TYPE
- RFCOMM_RPN_PM_STOP
- RFCOMM_RPN_PM_XOFF
- RFCOMM_RPN_PM_XON
- RFCOMM_RPN_STOP_1
- RFCOMM_RPN_STOP_15
- RFCOMM_RPN_XOFF_CHAR
- RFCOMM_RPN_XON_CHAR
- RFCOMM_RX_THROTTLED
- RFCOMM_SABM
- RFCOMM_SCHED_WAKEUP
- RFCOMM_SEC_PENDING
- RFCOMM_SKB_HEAD_RESERVE
- RFCOMM_SKB_RESERVE
- RFCOMM_SKB_TAIL_RESERVE
- RFCOMM_TEST
- RFCOMM_TIMED_OUT
- RFCOMM_TTY_ATTACHED
- RFCOMM_TTY_MAGIC
- RFCOMM_TTY_MAJOR
- RFCOMM_TTY_MINOR
- RFCOMM_TTY_OWNED
- RFCOMM_TTY_PORTS
- RFCOMM_TX_THROTTLED
- RFCOMM_UA
- RFCOMM_UIH
- RFCOMM_V24_DV
- RFCOMM_V24_FC
- RFCOMM_V24_IC
- RFCOMM_V24_RTC
- RFCOMM_V24_RTR
- RFCON
- RFCON0_CH_MASK
- RFCON0_CH_SHIFT
- RFCR
- RFCRAddressMask
- RFCR_AAB
- RFCR_AAM
- RFCR_AARP
- RFCR_AAU
- RFCR_APAT
- RFCR_APAT0
- RFCR_APAT1
- RFCR_APAT2
- RFCR_APAT3
- RFCR_APM
- RFCR_MHEN
- RFCR_RESET_SAVE
- RFCR_RFEN
- RFCR_UHEN
- RFCR_ULM
- RFCS
- RFCSR
- RFCSR11_MOD
- RFCSR11_PLL_IDOH
- RFCSR11_PLL_MOD
- RFCSR11_R
- RFCSR12_DR0
- RFCSR12_TX_POWER
- RFCSR13_DR0
- RFCSR13_RDIV_MT7620
- RFCSR13_TX_POWER
- RFCSR15_TX_LO2_EN
- RFCSR16_RF_PLL_FREQ_SEL_MT7620
- RFCSR16_SDM_MODE_MT7620
- RFCSR16_TXMIXER_GAIN
- RFCSR17_CODE
- RFCSR17_R
- RFCSR17_TXMIXER_GAIN
- RFCSR17_TX_LO1_EN
- RFCSR18_XO_TUNE_BYPASS
- RFCSR19_K
- RFCSR1_PLL_PD
- RFCSR1_RF_BLOCK_EN
- RFCSR1_RX0_PD
- RFCSR1_RX1_PD
- RFCSR1_RX2_PD
- RFCSR1_TX0_PD
- RFCSR1_TX1_PD
- RFCSR1_TX2_EN_MT7620
- RFCSR1_TX2_PD
- RFCSR20_RX_LO1_EN
- RFCSR21_BIT1
- RFCSR21_BIT8
- RFCSR21_RX_LO2_EN
- RFCSR22_BASEBAND_LOOPBACK
- RFCSR22_FREQPLAN_D_MT7620
- RFCSR23_FREQ_OFFSET
- RFCSR24_TX_AGC_FC
- RFCSR24_TX_CALIB
- RFCSR24_TX_H20M
- RFCSR27_R1
- RFCSR27_R2
- RFCSR27_R3
- RFCSR27_R4
- RFCSR28_CH11_HT40
- RFCSR29_ADC6_INT_TEST
- RFCSR29_ADC6_TEST
- RFCSR29_RSSI_GAIN
- RFCSR29_RSSI_ON
- RFCSR29_RSSI_RESET
- RFCSR29_RSSI_RIP_CTRL
- RFCSR2_RESCAL_BP
- RFCSR2_RESCAL_EN
- RFCSR2_RX2_EN_MT7620
- RFCSR2_TX2_EN_MT7620
- RFCSR30_RF_CALIBRATION
- RFCSR30_RX_H20M
- RFCSR30_RX_VCM
- RFCSR30_TX_H20M
- RFCSR31_RX_AGC_FC
- RFCSR31_RX_CALIB
- RFCSR31_RX_H20M
- RFCSR32_TX_AGC_FC
- RFCSR34_TX0_EXT_PA
- RFCSR34_TX1_EXT_PA
- RFCSR36_RF_BS
- RFCSR38_RX_LO1_EN
- RFCSR39_RX_DIV
- RFCSR39_RX_LO2_EN
- RFCSR3_BIT1
- RFCSR3_BIT2
- RFCSR3_BIT3
- RFCSR3_BIT4
- RFCSR3_BIT5
- RFCSR3_K
- RFCSR3_PA1_BIAS_CCK
- RFCSR3_PA2_CASCODE_BIAS_CCKK
- RFCSR3_VCOCAL_EN
- RFCSR41_BIT1
- RFCSR41_BIT4
- RFCSR42_BIT1
- RFCSR42_BIT4
- RFCSR42_TX2_EN_MT7620
- RFCSR49_EP
- RFCSR49_TX
- RFCSR49_TX_DIV
- RFCSR49_TX_LO1_IC
- RFCSR4_VCOCAL_EN
- RFCSR50_EP
- RFCSR50_TX
- RFCSR50_TX0_EXT_PA
- RFCSR50_TX1_EXT_PA
- RFCSR50_TX_LO1_EN
- RFCSR50_TX_LO2_EN
- RFCSR51_BITS01
- RFCSR51_BITS24
- RFCSR51_BITS57
- RFCSR53_TX_POWER
- RFCSR53_UNKNOWN
- RFCSR54_TX_POWER
- RFCSR54_UNKNOWN
- RFCSR55_TX_POWER
- RFCSR55_UNKNOWN
- RFCSR57_DRV_CC
- RFCSR5_R1
- RFCSR6_R1
- RFCSR6_R2
- RFCSR6_TXDIV
- RFCSR6_VCO_IC
- RFCSR7_BIT1
- RFCSR7_BIT2
- RFCSR7_BIT3
- RFCSR7_BIT4
- RFCSR7_BIT5
- RFCSR7_BITS67
- RFCSR7_RF_TUNING
- RFCSR9_K
- RFCSR9_MOD
- RFCSR9_N
- RFCSR9_UNKNOWN
- RFCSR_BASE
- RFCSR_BUSY
- RFCSR_IF_SELECT
- RFCSR_NUMBER_OF_BITS
- RFCSR_PLL_LD
- RFCSR_SIZE
- RFCSR_VALUE
- RFCS_ADDR
- RFCS_IDX
- RFC_AREA
- RFC_CODE
- RFD0_CONS_IDX_BMSK
- RFD0_CONS_IDX_SHFT
- RFD0_PROC_IDX_BMSK
- RFD0_PROC_IDX_SHFT
- RFD0_PROD_IDX_BMSK
- RFD0_PROD_IDX_SHFT
- RFD0_UR_INT
- RFD1_CONS_IDX_BMSK
- RFD1_CONS_IDX_SHFT
- RFD1_PROC_IDX_BMSK
- RFD1_PROC_IDX_SHFT
- RFD1_PROD_IDX_BMSK
- RFD1_PROD_IDX_SHFT
- RFD1_UR_INT
- RFD2_CONS_IDX_BMSK
- RFD2_CONS_IDX_SHFT
- RFD2_PROC_IDX_BMSK
- RFD2_PROC_IDX_SHFT
- RFD2_PROD_IDX_BMSK
- RFD2_PROD_IDX_SHFT
- RFD2_UR_INT
- RFD3_CONS_IDX_BMSK
- RFD3_CONS_IDX_SHFT
- RFD3_PROC_IDX_BMSK
- RFD3_PROC_IDX_SHFT
- RFD3_PROD_IDX_BMSK
- RFD3_PROD_IDX_SHFT
- RFD3_UR_INT
- RFD4_UR_INT
- RFD77402_CMD_CFGR_A
- RFD77402_CMD_CFGR_B
- RFD77402_CMD_MCPU_OFF
- RFD77402_CMD_MCPU_ON
- RFD77402_CMD_R
- RFD77402_CMD_RESET
- RFD77402_CMD_SINGLE
- RFD77402_CMD_STANDBY
- RFD77402_CMD_VALID
- RFD77402_DRV_NAME
- RFD77402_HFCFG_0
- RFD77402_HFCFG_1
- RFD77402_HFCFG_2
- RFD77402_HFCFG_3
- RFD77402_I2C_ADDR_INCR
- RFD77402_I2C_DATA_INCR
- RFD77402_I2C_HOST_DEBUG
- RFD77402_I2C_INIT_CFG
- RFD77402_I2C_MCPU_DEBUG
- RFD77402_ICSR
- RFD77402_ICSR_H2M_MSG
- RFD77402_ICSR_INT_MODE
- RFD77402_ICSR_INT_POL
- RFD77402_ICSR_M2H_MSG
- RFD77402_ICSR_RESET
- RFD77402_ICSR_RESULT
- RFD77402_MOD_CHIP_ID
- RFD77402_PMU_CFG
- RFD77402_PMU_MCPU_INIT
- RFD77402_RESULT_DIST_MASK
- RFD77402_RESULT_ERR_MASK
- RFD77402_RESULT_R
- RFD77402_RESULT_VALID
- RFD77402_STATUS_MCPU_OFF
- RFD77402_STATUS_MCPU_ON
- RFD77402_STATUS_PM_MASK
- RFD77402_STATUS_R
- RFD77402_STATUS_STANDBY
- RFDAT
- RFDDone
- RFDISABLE_DEFAULT
- RFDIV_MASK
- RFDListEnd
- RFDListPtr0
- RFDListPtr1
- RFDR
- RFDX_HARD_ADDR_SHIFT
- RFDX_HEAD_ADDR_MASK
- RFDX_TAIL_ADDR_MASK
- RFDX_TAIL_ADDR_SHIFT
- RFD_BUF_LEN
- RFD_BUSY
- RFD_COLLDET
- RFD_COMPL
- RFD_ERR_ALGN
- RFD_ERR_CRC
- RFD_ERR_FTS
- RFD_ERR_LEN
- RFD_ERR_NEOP
- RFD_ERR_OVR
- RFD_ERR_RNR
- RFD_ERR_TRUN
- RFD_FREE_HI_THRESH_SHIFT
- RFD_FREE_LO_THRESH_SHIFT
- RFD_FREE_THRESH_MASK
- RFD_FTL_MAJOR
- RFD_FULL_MINUS_1K
- RFD_FULL_MINUS_2K
- RFD_FULL_MINUS_3K
- RFD_FULL_MINUS_4K
- RFD_FULL_MINUS_5K
- RFD_FULL_MINUS_6K
- RFD_FULL_MINUS_7K
- RFD_LAST
- RFD_LOW_WATER_MARK
- RFD_MAGIC
- RFD_MATCHADD
- RFD_NIC_LEN_MASK
- RFD_OK
- RFD_PREF_LOW_TH
- RFD_PREF_LOW_THRESHOLD_BMSK
- RFD_PREF_LOW_THRESHOLD_SHFT
- RFD_PREF_UP_TH
- RFD_PREF_UP_THRESHOLD_BMSK
- RFD_PREF_UP_THRESHOLD_SHFT
- RFD_RING_SIZE_BMSK
- RFD_RING_SIZE_MASK
- RFD_SIZE
- RFD_SUSP
- RFEBB
- RFEN
- RFE_ADDR_FILT_HI
- RFE_ADDR_FILT_HI_VALID_
- RFE_ADDR_FILT_LO
- RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWRC_rst_MASK
- RFE_CLIENT_SOFTRST_TRIGGER__CLIENT0_RFE_RFEWRC_rst__SHIFT
- RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWRC_rst_MASK
- RFE_CLIENT_SOFTRST_TRIGGER__CLIENT1_RFE_RFEWRC_rst__SHIFT
- RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWRC_rst_MASK
- RFE_CLIENT_SOFTRST_TRIGGER__CLIENT2_RFE_RFEWRC_rst__SHIFT
- RFE_CTL
- RFE_CTL_AB
- RFE_CTL_AB_
- RFE_CTL_AM
- RFE_CTL_AM_
- RFE_CTL_AU
- RFE_CTL_AU_
- RFE_CTL_BCAST_EN_
- RFE_CTL_DA_HASH_
- RFE_CTL_DA_PERFECT_
- RFE_CTL_DHF
- RFE_CTL_DISCARD_UNTAGGED_
- RFE_CTL_DPF
- RFE_CTL_ICMP_COE_
- RFE_CTL_IGMP_COE_
- RFE_CTL_IP_CKM
- RFE_CTL_IP_COE_
- RFE_CTL_MCAST_EN_
- RFE_CTL_MCAST_HASH_
- RFE_CTL_MHF
- RFE_CTL_RST_
- RFE_CTL_RST_RF
- RFE_CTL_SA_FILTER_
- RFE_CTL_SPF
- RFE_CTL_TCPUDP_CKM
- RFE_CTL_TCPUDP_COE_
- RFE_CTL_UCAST_EN_
- RFE_CTL_UF
- RFE_CTL_VF
- RFE_CTL_VLAN_FILTER_
- RFE_CTL_VLAN_STRIP_
- RFE_CTL_VS
- RFE_HASH_KEY
- RFE_IMPARBH_CONTROL__REG_IMPA_throttleTimer_MASK
- RFE_IMPARBH_CONTROL__REG_IMPA_throttleTimer__SHIFT
- RFE_IMPARBH_STATUS__IMPAH_REG_calDone_MASK
- RFE_IMPARBH_STATUS__IMPAH_REG_calDone__SHIFT
- RFE_IMPRST_CNTL__REG_RST_impEn_MASK
- RFE_IMPRST_CNTL__REG_RST_impEn__SHIFT
- RFE_INDX
- RFE_MASTER_SOFTRST_TRIGGER__PCIEW0_rst_MASK
- RFE_MASTER_SOFTRST_TRIGGER__PCIEW0_rst__SHIFT
- RFE_MASTER_SOFTRST_TRIGGER__PCIEW1_rst_MASK
- RFE_MASTER_SOFTRST_TRIGGER__PCIEW1_rst__SHIFT
- RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWRC_rst_MASK
- RFE_MASTER_SOFTRST_TRIGGER__RWREG_RFEWRC_rst__SHIFT
- RFE_MST_PCIEW0_CMDSTATUS__PCIEW0_RFE_mstTimeout_MASK
- RFE_MST_PCIEW0_CMDSTATUS__PCIEW0_RFE_mstTimeout__SHIFT
- RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_clkGate_timer_MASK
- RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_clkGate_timer__SHIFT
- RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_clkSetup_timer_MASK
- RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_clkSetup_timer__SHIFT
- RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_timeout_timer_MASK
- RFE_MST_PCIEW0_CMDSTATUS__REG_PCIEW0_timeout_timer__SHIFT
- RFE_MST_PCIEW1_CMDSTATUS__PCIEW1_RFE_mstTimeout_MASK
- RFE_MST_PCIEW1_CMDSTATUS__PCIEW1_RFE_mstTimeout__SHIFT
- RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_clkGate_timer_MASK
- RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_clkGate_timer__SHIFT
- RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_clkSetup_timer_MASK
- RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_clkSetup_timer__SHIFT
- RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_timeout_timer_MASK
- RFE_MST_PCIEW1_CMDSTATUS__REG_PCIEW1_timeout_timer__SHIFT
- RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_clkGate_timer_MASK
- RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_clkGate_timer__SHIFT
- RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_clkSetup_timer_MASK
- RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_clkSetup_timer__SHIFT
- RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_timeout_timer_MASK
- RFE_MST_RWREG_RFEWRC_CMDSTATUS__REG_RWREG_RFEWRC_timeout_timer__SHIFT
- RFE_MST_RWREG_RFEWRC_CMDSTATUS__RWREG_RFEWRC_RFE_mstTimeout_MASK
- RFE_MST_RWREG_RFEWRC_CMDSTATUS__RWREG_RFEWRC_RFE_mstTimeout__SHIFT
- RFE_MST_TMOUT_STATUS__MstTmoutStatus_MASK
- RFE_MST_TMOUT_STATUS__MstTmoutStatus__SHIFT
- RFE_PWDN_COMMAND__REG_PCIEW0_pw_cmd_MASK
- RFE_PWDN_COMMAND__REG_PCIEW0_pw_cmd__SHIFT
- RFE_PWDN_COMMAND__REG_PCIEW1_pw_cmd_MASK
- RFE_PWDN_COMMAND__REG_PCIEW1_pw_cmd__SHIFT
- RFE_PWDN_COMMAND__REG_RWREG_RFEWRC_pw_cmd_MASK
- RFE_PWDN_COMMAND__REG_RWREG_RFEWRC_pw_cmd__SHIFT
- RFE_PWDN_STATUS__PCIEW0_REG_pw_status_MASK
- RFE_PWDN_STATUS__PCIEW0_REG_pw_status__SHIFT
- RFE_PWDN_STATUS__PCIEW1_REG_pw_status_MASK
- RFE_PWDN_STATUS__PCIEW1_REG_pw_status__SHIFT
- RFE_PWDN_STATUS__RWREG_RFEWRC_REG_pw_status_MASK
- RFE_PWDN_STATUS__RWREG_RFEWRC_REG_pw_status__SHIFT
- RFE_RSS_CFG
- RFE_RSS_CFG_IPV4_
- RFE_RSS_CFG_IPV6_
- RFE_RSS_CFG_IPV6_EX_
- RFE_RSS_CFG_RSS_ENABLE_
- RFE_RSS_CFG_RSS_HASH_STORE_
- RFE_RSS_CFG_RSS_QUEUE_ENABLE_
- RFE_RSS_CFG_TCP_IPV4_
- RFE_RSS_CFG_TCP_IPV6_
- RFE_RSS_CFG_TCP_IPV6_EX_
- RFE_RSS_CFG_UDP_IPV4_
- RFE_RSS_CFG_UDP_IPV6_
- RFE_RSS_CFG_UDP_IPV6_EX_
- RFE_RSS_CFG_VALID_HASH_BITS_
- RFE_SHIFT
- RFE_SOFTRST_CNTL__REG_RST_rstTimer_MASK
- RFE_SOFTRST_CNTL__REG_RST_rstTimer__SHIFT
- RFE_SOFTRST_CNTL__REG_RST_softRstPropEn_MASK
- RFE_SOFTRST_CNTL__REG_RST_softRstPropEn__SHIFT
- RFE_SOFTRST_CNTL__SoftRstReg_MASK
- RFE_SOFTRST_CNTL__SoftRstReg__SHIFT
- RFE_WARMRST_CNTL__REG_RST_warmRstImpEn_MASK
- RFE_WARMRST_CNTL__REG_RST_warmRstImpEn__SHIFT
- RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn_MASK
- RFE_WARMRST_CNTL__REG_RST_warmRstRfeEn__SHIFT
- RFF
- RFFE
- RFFEN_SHIFT
- RFF_ID_CMD
- RFF_ID_REQ_SIZE
- RFF_ID_RSP_SIZE
- RFF_REQUEST_SZ
- RFH_DMA_EN_ENABLE_VAL
- RFH_DMA_EN_MASK
- RFH_GEN_CFG
- RFH_GEN_CFG_DEFAULT_RXQ_NUM
- RFH_GEN_CFG_RB_CHUNK_SIZE
- RFH_GEN_CFG_RB_CHUNK_SIZE_128
- RFH_GEN_CFG_RB_CHUNK_SIZE_64
- RFH_GEN_CFG_RFH_DMA_SNOOP
- RFH_GEN_CFG_SERVICE_DMA_SNOOP
- RFH_GEN_CFG_VAL
- RFH_GEN_STATUS
- RFH_GEN_STATUS_GEN3
- RFH_Q0_FRBDCB_BA_LSB
- RFH_Q0_FRBDCB_RIDX
- RFH_Q0_FRBDCB_WIDX
- RFH_Q0_FRBDCB_WIDX_TRG
- RFH_Q0_ORB_WPTR_LSB
- RFH_Q0_URBDCB_BA_LSB
- RFH_Q0_URBDCB_VAID
- RFH_Q0_URBDCB_WIDX
- RFH_Q0_URBD_STTS_WPTR_LSB
- RFH_QUEUE_CONFIG_CMD
- RFH_Q_FRBDCB_BA_LSB
- RFH_Q_FRBDCB_RIDX
- RFH_Q_FRBDCB_WIDX
- RFH_Q_FRBDCB_WIDX_TRG
- RFH_Q_ORB_WPTR_LSB
- RFH_Q_URBDCB_BA_LSB
- RFH_Q_URBDCB_VAID
- RFH_Q_URBDCB_WIDX
- RFH_Q_URBD_STTS_WPTR_LSB
- RFH_RBDBUF_RBD0_LSB
- RFH_RBDBUF_RBD_LSB
- RFH_RXF_DMA_CFG
- RFH_RXF_DMA_CFG_GEN3
- RFH_RXF_DMA_DROP_TOO_LARGE_MASK
- RFH_RXF_DMA_MIN_RB_4_8
- RFH_RXF_DMA_MIN_RB_SIZE_MASK
- RFH_RXF_DMA_MIN_RB_SIZE_POS
- RFH_RXF_DMA_RBDCB_SIZE_1024
- RFH_RXF_DMA_RBDCB_SIZE_128
- RFH_RXF_DMA_RBDCB_SIZE_16
- RFH_RXF_DMA_RBDCB_SIZE_2048
- RFH_RXF_DMA_RBDCB_SIZE_256
- RFH_RXF_DMA_RBDCB_SIZE_32
- RFH_RXF_DMA_RBDCB_SIZE_512
- RFH_RXF_DMA_RBDCB_SIZE_64
- RFH_RXF_DMA_RBDCB_SIZE_8
- RFH_RXF_DMA_RBDCB_SIZE_MASK
- RFH_RXF_DMA_RBDCB_SIZE_POS
- RFH_RXF_DMA_RB_SIZE_12K
- RFH_RXF_DMA_RB_SIZE_16K
- RFH_RXF_DMA_RB_SIZE_1K
- RFH_RXF_DMA_RB_SIZE_20K
- RFH_RXF_DMA_RB_SIZE_24K
- RFH_RXF_DMA_RB_SIZE_28K
- RFH_RXF_DMA_RB_SIZE_2K
- RFH_RXF_DMA_RB_SIZE_32K
- RFH_RXF_DMA_RB_SIZE_4K
- RFH_RXF_DMA_RB_SIZE_8K
- RFH_RXF_DMA_RB_SIZE_MASK
- RFH_RXF_DMA_RB_SIZE_POS
- RFH_RXF_DMA_SINGLE_FRAME_MASK
- RFH_RXF_RXQ_ACTIVE
- RFI
- RFIC_REG_RD
- RFIFO_CRIT
- RFIG
- RFINI_RDY
- RFINTFS
- RFI_FLUSH_FIXUP_SECTION
- RFI_FLUSH_SLOT
- RFI_TO_GUEST
- RFI_TO_KERNEL
- RFI_TO_USER
- RFI_TO_USER_OR_KERNEL
- RFKILL_BLOCK_ANY
- RFKILL_BLOCK_HW
- RFKILL_BLOCK_SW
- RFKILL_BLOCK_SW_PREV
- RFKILL_BLOCK_SW_SETCALL
- RFKILL_EVENT_SIZE_V1
- RFKILL_GLOBAL_OP_EPO
- RFKILL_GLOBAL_OP_RESTORE
- RFKILL_GLOBAL_OP_UNBLOCK
- RFKILL_GLOBAL_OP_UNLOCK
- RFKILL_INPUT_MASTER_RESTORE
- RFKILL_INPUT_MASTER_UNBLOCKALL
- RFKILL_INPUT_MASTER_UNLOCK
- RFKILL_IOCTL_NOINPUT
- RFKILL_IOC_MAGIC
- RFKILL_IOC_NOINPUT
- RFKILL_MASK_8187_89_97
- RFKILL_MASK_8198
- RFKILL_MINOR
- RFKILL_NAME
- RFKILL_OPS_DELAY
- RFKILL_OP_ADD
- RFKILL_OP_CHANGE
- RFKILL_OP_CHANGE_ALL
- RFKILL_OP_DEL
- RFKILL_PM_OPS
- RFKILL_STATE_HARD_BLOCKED
- RFKILL_STATE_SOFT_BLOCKED
- RFKILL_STATE_UNBLOCKED
- RFKILL_TYPE_ALL
- RFKILL_TYPE_BLUETOOTH
- RFKILL_TYPE_FM
- RFKILL_TYPE_GPS
- RFKILL_TYPE_NFC
- RFKILL_TYPE_UWB
- RFKILL_TYPE_WIMAX
- RFKILL_TYPE_WLAN
- RFKILL_TYPE_WWAN
- RFKILL_USER_STATE_HARD_BLOCKED
- RFKILL_USER_STATE_SOFT_BLOCKED
- RFKILL_USER_STATE_UNBLOCKED
- RFLAG
- RFLR
- RFLR_ADDR
- RFLR_IDX
- RFMT
- RFM_HEAD_SIZE
- RFM_SEGMENTATION_BIT
- RFOCR
- RFOPT_RECOMMEND
- RFPC
- RFPGA0_ADDALLOCKEN
- RFPGA0_ANALOGPARAMETER1
- RFPGA0_ANALOGPARAMETER2
- RFPGA0_ANALOGPARAMETER3
- RFPGA0_ANALOGPARAMETER4
- RFPGA0_IQK
- RFPGA0_PSDFUNCTION
- RFPGA0_PSDREPORT
- RFPGA0_RFMOD
- RFPGA0_RFSLEEPUPPARAMETER
- RFPGA0_RFSLEEPUP_PARAMETER
- RFPGA0_RFTIMING1
- RFPGA0_RFTIMING2
- RFPGA0_RFWAKEUPPARAMETER
- RFPGA0_RFWAKEUP_PARAMETER
- RFPGA0_TXGAINSTAGE
- RFPGA0_TXINFO
- RFPGA0_XAB_RFINTERFACERB
- RFPGA0_XAB_RFINTERFACESW
- RFPGA0_XAB_RFPARAMETER
- RFPGA0_XAB_SWITCHCONTROL
- RFPGA0_XA_HSSIPARAMETER1
- RFPGA0_XA_HSSIPARAMETER2
- RFPGA0_XA_LSSIPARAMETER
- RFPGA0_XA_LSSIREADBACK
- RFPGA0_XA_RFINTERFACEOE
- RFPGA0_XB_HSSIPARAMETER1
- RFPGA0_XB_HSSIPARAMETER2
- RFPGA0_XB_LSSIPARAMETER
- RFPGA0_XB_LSSIREADBACK
- RFPGA0_XB_RFINTERFACEOE
- RFPGA0_XCD_RFINTERFACERB
- RFPGA0_XCD_RFINTERFACESW
- RFPGA0_XCD_RFPARAMETER
- RFPGA0_XCD_SWITCHCONTROL
- RFPGA0_XC_HSSIPARAMETER1
- RFPGA0_XC_HSSIPARAMETER2
- RFPGA0_XC_LSSIPARAMETER
- RFPGA0_XC_LSSIREADBACK
- RFPGA0_XC_RFINTERFACEOE
- RFPGA0_XD_HSSIPARAMETER1
- RFPGA0_XD_HSSIPARAMETER2
- RFPGA0_XD_LSSIPARAMETER
- RFPGA0_XD_LSSIREADBACK
- RFPGA0_XD_RFINTERFACEOE
- RFPGA1_DEBUGSELECT
- RFPGA1_RFMOD
- RFPGA1_TXBLOCK
- RFPGA1_TXINFO
- RFPromiscuous
- RFRAC
- RFREG_MASK
- RFREG_OFFSET_MASK
- RFREQ_37_32_MASK
- RFRG
- RFRG_ADDR
- RFRLEN1
- RFRLEN2
- RFS1
- RFS1d
- RFS2
- RFS2d
- RFS3
- RFS3d
- RFSE_ALIGN
- RFSILENT_BB
- RFSPOL_SHIFT
- RFSREN
- RFSSEL_SHIFT
- RFST0
- RFST1
- RFST2
- RFST3
- RFST4
- RFST5
- RFST6
- RFST7
- RFST8
- RFST9
- RFSW_CTRL
- RFSYN_CHP_GAIN
- RFSYN_DIVM
- RFSYN_EN_CHP_HIGAIN
- RFSYN_EN_DIV
- RFSYN_EN_OUTMUX
- RFSYN_LPF_R
- RFSYN_RF_DIV_BIAS
- RFSYN_R_DIV
- RFSYN_SEL_DIVM
- RFSYN_SEL_VCO_HI
- RFSYN_SEL_VCO_OUT
- RFSYN_VCO_BIAS
- RFS_CODE
- RFS_Errors
- RFS_bits
- RFTP_F
- RFTP_S
- RFTP_V
- RFTR
- RFTYPE_BASE
- RFTYPE_CTRL
- RFTYPE_FLAGS_CPUS_LIST
- RFTYPE_INFO
- RFTYPE_MON
- RFTYPE_RES_CACHE
- RFTYPE_RES_MB
- RFTYPE_TOP
- RFT_ID_CMD
- RFT_ID_REQ_SIZE
- RFT_ID_RSP_SIZE
- RFT_ID_SNS_CMD_SIZE
- RFT_ID_SNS_DATA_SIZE
- RFT_ID_SNS_SCMD_LEN
- RFT_REQUEST_SZ
- RFTrackingFiltersCorrection
- RFTrackingFiltersInit
- RFULL
- RFULL_CYCLE
- RFU_SHIFT
- RFVGA_0
- RFVGA_1
- RFVGA_2
- RFVGA_3
- RF_0x52
- RF_1ST_IBLK_BASE
- RF_1T1R
- RF_1T2R
- RF_1TX
- RF_2T2R
- RF_2T2R_GREEN
- RF_2T3R
- RF_2T4R
- RF_2TX
- RF_32LSB
- RF_32MSB
- RF_3T3R
- RF_3T4R
- RF_3TX
- RF_4T4R
- RF_4TX
- RF_6052
- RF_64LSB
- RF_64MSB
- RF_819X_MAX_TYPE
- RF_8225
- RF_8256
- RF_8258
- RF_A
- RF_AC
- RF_AGC_STATUS
- RF_AGC_VAL_1
- RF_AIROHA
- RF_AIROHA7230
- RF_AL2230
- RF_AL2230S
- RF_ANTENNA_1
- RF_ANTENNA_2
- RF_ANTENNA_AUTO
- RF_APK
- RF_A_BAND
- RF_A_BAND_11J
- RF_A_BAND_HB
- RF_A_BAND_LB
- RF_A_BAND_MB
- RF_B
- RF_BAD_HEADER
- RF_BAD_PAYLOAD
- RF_BAND
- RF_BASE
- RF_BB_CMD_ADDR
- RF_BB_CMD_DATA
- RF_BIAS
- RF_BS_IQGEN
- RF_BS_PA_APSET_G1_G4
- RF_BS_PA_APSET_G5_G8
- RF_BS_PA_APSET_G9_G11
- RF_BUFF
- RF_BUSY
- RF_BW_10
- RF_BW_20
- RF_BW_40
- RF_BW_80
- RF_BW_TRXBB
- RF_BYPASS0
- RF_BYPASS1
- RF_BYPASS2
- RF_BYPASS3
- RF_CAL
- RF_CAL_DC_OVER_DT
- RF_CAL_KMCO
- RF_CFGCH
- RF_CHANGE_BY_HW
- RF_CHANGE_BY_INIT
- RF_CHANGE_BY_IPS
- RF_CHANGE_BY_PS
- RF_CHANGE_BY_SW
- RF_CHANNEL
- RF_CHANPAIR
- RF_CHNLBW
- RF_CHNL_NUM_5G
- RF_CHNL_NUM_5G_40M
- RF_CLK
- RF_CONT
- RF_CONTENT
- RF_CONTROL0
- RF_CONTROL1
- RF_CONTROL2
- RF_CONTROL3
- RF_CRC
- RF_CSR_CFG
- RF_CSR_CFG0
- RF_CSR_CFG0_BITWIDTH
- RF_CSR_CFG0_BUSY
- RF_CSR_CFG0_REGID_AND_VALUE
- RF_CSR_CFG0_REG_VALUE_BW
- RF_CSR_CFG0_SEL
- RF_CSR_CFG0_STANDBYMODE
- RF_CSR_CFG1
- RF_CSR_CFG1_REGID_AND_VALUE
- RF_CSR_CFG1_RFGAP
- RF_CSR_CFG2
- RF_CSR_CFG2_VALUE
- RF_CSR_CFG_BUSY
- RF_CSR_CFG_BUSY_MT7620
- RF_CSR_CFG_DATA
- RF_CSR_CFG_DATA_MT7620
- RF_CSR_CFG_REGNUM
- RF_CSR_CFG_REGNUM_MT7620
- RF_CSR_CFG_WRITE
- RF_CSR_CFG_WRITE_MT7620
- RF_CTRL
- RF_CTRLSHIFT
- RF_CTRL_BASE
- RF_CTRL_INFO
- RF_DATA
- RF_DEBUG
- RF_DMA_EN
- RF_DSYNC_ST
- RF_DTXLOK
- RF_EMU
- RF_EN
- RF_ENABLE
- RF_ENP
- RF_ERR
- RF_EXTERNAL
- RF_EXT_TIA_BW
- RF_FAILURE_OK
- RF_FRAM
- RF_FULL
- RF_GAIN_OFFSET_MASK
- RF_GAIN_RX
- RF_GAIN_TX
- RF_GCT5103
- RF_G_BAND
- RF_IF_LE
- RF_INIT_ST
- RF_INSN14
- RF_INSN21B
- RF_INSN21F
- RF_INSN21M
- RF_INSN22
- RF_INSN60
- RF_INSN64
- RF_INV_E_COUNT
- RF_INV_E_ORDER
- RF_INV_E_PARAM
- RF_INV_E_TYPE
- RF_IPA
- RF_IPA_A
- RF_IPA_G
- RF_IQADJ_G1
- RF_IQADJ_G2
- RF_IRIS_WCN3620
- RF_KILLSWITCH_OFF
- RF_KILLSWITCH_ON
- RF_KILL_CHECK_DELAY
- RF_KILL_INDICATOR_FOR_WOWLAN
- RF_LOBF_9
- RF_LOOKUP_TABLE2_SIZE
- RF_LOOKUP_TABLE_SIZE
- RF_LUTDBG
- RF_LUTWA
- RF_LUTWD0
- RF_LUTWD1
- RF_LUTWE
- RF_LUTWE2
- RF_MALSEL
- RF_MARLON
- RF_MASK
- RF_MASK_24XX
- RF_MASK_A
- RF_MASK_B
- RF_MASK_C
- RF_MASK_D
- RF_MAX
- RF_MAXIM2829
- RF_MAXIMAG
- RF_MAXIMG
- RF_MAX_TX_NUM
- RF_MAX_TYPE
- RF_MODE1
- RF_MODE2
- RF_MODE_AG
- RF_MODE_TRXAGC
- RF_MODOPT
- RF_MONSHIFT
- RF_MON_INFO
- RF_NONE
- RF_NORMAL
- RF_NOTHING
- RF_NO_COMM
- RF_Normal
- RF_OFF
- RF_OFLO
- RF_OK
- RF_ON
- RF_OPTION1
- RF_OPTION2
- RF_OPTION3
- RF_OPTION4
- RF_OP_BY_FW
- RF_OP_BY_SW_3WIRE
- RF_OP_By_FW
- RF_OP_By_SW_3wire
- RF_OP_MAX
- RF_OWN
- RF_PARAM_ANALOGPHY
- RF_PARAM_ANTBDEFAULT
- RF_PARAM_CARRIERSENSE1
- RF_PARAM_CARRIERSENSE2
- RF_PATH
- RF_PATH_A
- RF_PATH_B
- RF_PATH_C
- RF_PATH_D
- RF_PATH_MAX
- RF_PATH_MAX_90_8812
- RF_PATH_MAX_92C_88E
- RF_POW_ABILITY
- RF_POW_TRSW
- RF_PROG_VALUES_REQUEST
- RF_PSEUDO_11N
- RF_RANDOM_WRITE
- RF_RCK
- RF_RCK1
- RF_RCK2
- RF_RCKD
- RF_RCK_OS
- RF_REG_BITS
- RF_REG_NUM
- RF_REG_NUM_FOR_C_CUT_2G
- RF_REG_NUM_FOR_C_CUT_5G
- RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA
- RF_REG_PAIR
- RF_RESET_ENABLE
- RF_RFMD2959
- RF_RL_ID
- RF_RQ_DMA_ERROR
- RF_RSTB
- RF_RV_BITS
- RF_RXAGC_OFFSET
- RF_RXA_MIX_GAIN
- RF_RXG_GAIN
- RF_RXRF_A3
- RF_RX_AGC_HP
- RF_RX_BB1
- RF_RX_BB2
- RF_RX_G1
- RF_RX_G2
- RF_S0S1
- RF_SAVE
- RF_SDMRSTB
- RF_SHUT_DOWN
- RF_SIZE
- RF_SLEEP
- RF_SPARROW
- RF_STP
- RF_SYN_G1
- RF_SYN_G2
- RF_SYN_G3
- RF_SYN_G4
- RF_SYN_G5
- RF_SYN_G6
- RF_SYN_G7
- RF_SYN_G8
- RF_Save
- RF_TALYNA1
- RF_TALYNA2
- RF_TEMPERATURE_CALIB_DEFAULT_DB
- RF_TEMPERATURE_CALIB_HIGH_POWER_DB
- RF_TOP
- RF_TOPSHIFT
- RF_TOP_INFO
- RF_TRSW
- RF_TXA_LB_SW
- RF_TXBIAS
- RF_TXBIAS_A
- RF_TXBIAS_G
- RF_TXM_IDAC
- RF_TXPA_A4
- RF_TXPA_AG
- RF_TXPA_G1
- RF_TXPA_G2
- RF_TXPA_G3
- RF_TXPA_G4
- RF_TXRF_A2
- RF_TX_AGC
- RF_TX_BB1
- RF_TX_BIAS_A
- RF_TX_BIAS_D
- RF_TX_G1
- RF_TX_G2
- RF_TX_G3
- RF_TX_GAIN
- RF_TX_GAIN_OFFSET
- RF_TX_NUM
- RF_TX_NUM_NONIMPLEMENT
- RF_TYPE
- RF_TYPE_1T1R
- RF_TYPE_1T2R
- RF_TYPE_2T2R
- RF_TYPE_2T3R
- RF_TYPE_2T4R
- RF_TYPE_3T3R
- RF_TYPE_3T4R
- RF_TYPE_4T4R
- RF_TYPE_ID
- RF_TYPE_MASK
- RF_TYPE_MAX
- RF_TYPE_MIN
- RF_T_METER
- RF_T_METER_8723B
- RF_T_METER_8812A
- RF_T_METER_88E
- RF_T_METER_NEW
- RF_T_METER_OLD
- RF_UNIT
- RF_UNKNOWN
- RF_UW2451
- RF_UW2452
- RF_UW2453
- RF_VALUE_BITS
- RF_VT3226
- RF_VT3226D0
- RF_VT3342A0
- RF_WE_LUT
- RF_WRONG_BOARD_FILE
- RF_XTALX2
- RFbAL2230Init
- RFbAL2230SelectChannel
- RFbAL7230SelectChannelPostProcess
- RFbInit
- RFbRawSetPower
- RFbSelectChannel
- RFbSetPower
- RFvRSSITodBm
- RFvWriteWakeProgSyn
- RGATE_TIMEOUT
- RGA_ALPHA_BLEND_GLOBAL
- RGA_ALPHA_BLEND_MULTIPLY
- RGA_ALPHA_BLEND_NORMAL
- RGA_ALPHA_CAL_CUT
- RGA_ALPHA_CAL_NORMAL
- RGA_ALPHA_COLOR_MULTIPLY_CAL
- RGA_ALPHA_COLOR_NORMAL
- RGA_ALPHA_CTRL0
- RGA_ALPHA_CTRL1
- RGA_ALPHA_FACTOR_ONE
- RGA_ALPHA_FACTOR_OTHER
- RGA_ALPHA_FACTOR_OTHER_REVERSE
- RGA_ALPHA_FACTOR_SELF
- RGA_ALPHA_FACTOR_ZERO
- RGA_ALPHA_MASK_BIG_ENDIAN
- RGA_ALPHA_MASK_LITTLE_ENDIAN
- RGA_ALPHA_NORMAL
- RGA_ALPHA_REVERSE
- RGA_ALPHA_ROP_MODE_2
- RGA_ALPHA_ROP_MODE_3
- RGA_ALPHA_ROP_MODE_4
- RGA_ALPHA_SELECT_ALPHA
- RGA_ALPHA_SELECT_ROP
- RGA_CMDBUF_SIZE
- RGA_CMD_BASE
- RGA_CMD_CTRL
- RGA_COLOR_ALPHA_SWAP
- RGA_COLOR_FMT_ABGR1555
- RGA_COLOR_FMT_ABGR4444
- RGA_COLOR_FMT_ABGR8888
- RGA_COLOR_FMT_BGR565
- RGA_COLOR_FMT_CP_1BPP
- RGA_COLOR_FMT_CP_2BPP
- RGA_COLOR_FMT_CP_4BPP
- RGA_COLOR_FMT_CP_8BPP
- RGA_COLOR_FMT_MASK
- RGA_COLOR_FMT_RGB888
- RGA_COLOR_FMT_XBGR8888
- RGA_COLOR_FMT_YUV420P
- RGA_COLOR_FMT_YUV420SP
- RGA_COLOR_FMT_YUV422P
- RGA_COLOR_FMT_YUV422SP
- RGA_COLOR_NONE_SWAP
- RGA_COLOR_RB_SWAP
- RGA_COLOR_UV_SWAP
- RGA_DST_ACT_INFO
- RGA_DST_CB_BASE_ADDR
- RGA_DST_CR_BASE_ADDR
- RGA_DST_CSC_MODE_BT601_R0
- RGA_DST_CSC_MODE_BT601_R1
- RGA_DST_CSC_MODE_BT709_R0
- RGA_DST_CSC_MODE_BYPASS
- RGA_DST_DITHER_MODE_888_TO_444
- RGA_DST_DITHER_MODE_888_TO_555
- RGA_DST_DITHER_MODE_888_TO_565
- RGA_DST_DITHER_MODE_888_TO_666
- RGA_DST_INFO
- RGA_DST_VIR_INFO
- RGA_DST_Y_RGB_BASE_ADDR
- RGA_FADING_CTRL
- RGA_INT
- RGA_MASK_BASE
- RGA_MMU_CTRL0
- RGA_MMU_CTRL1
- RGA_MMU_DST_BASE
- RGA_MMU_SRC1_BASE
- RGA_MMU_SRC_BASE
- RGA_MODE_BASE_REG
- RGA_MODE_BITBLT_MODE_SRC_SRC1_TO_DST
- RGA_MODE_BITBLT_MODE_SRC_TO_DST
- RGA_MODE_CF_ROP4_PATTERN
- RGA_MODE_CF_ROP4_SOLID
- RGA_MODE_CTRL
- RGA_MODE_MAX_REG
- RGA_MODE_RENDER_BITBLT
- RGA_MODE_RENDER_COLOR_PALETTE
- RGA_MODE_RENDER_RECTANGLE_FILL
- RGA_MODE_RENDER_UPDATE_PALETTE_LUT_RAM
- RGA_NAME
- RGA_PAT_CON
- RGA_ROP_CON0
- RGA_ROP_CON1
- RGA_SRC1_RGB_BASE_ADDR
- RGA_SRC_ACT_INFO
- RGA_SRC_BG_COLOR
- RGA_SRC_BIC_COE_SELEC_BSPLINE
- RGA_SRC_BIC_COE_SELEC_CATROM
- RGA_SRC_BIC_COE_SELEC_HERMITE
- RGA_SRC_BIC_COE_SELEC_MITCHELL
- RGA_SRC_CB_BASE_ADDR
- RGA_SRC_CR_BASE_ADDR
- RGA_SRC_CSC_MODE_BT601_R0
- RGA_SRC_CSC_MODE_BT601_R1
- RGA_SRC_CSC_MODE_BT709_R0
- RGA_SRC_CSC_MODE_BT709_R1
- RGA_SRC_CSC_MODE_BYPASS
- RGA_SRC_FG_COLOR
- RGA_SRC_HSCL_MODE_DOWN
- RGA_SRC_HSCL_MODE_NO
- RGA_SRC_HSCL_MODE_UP
- RGA_SRC_INFO
- RGA_SRC_MIRR_MODE_NO
- RGA_SRC_MIRR_MODE_X
- RGA_SRC_MIRR_MODE_X_Y
- RGA_SRC_MIRR_MODE_Y
- RGA_SRC_ROT_MODE_0_DEGREE
- RGA_SRC_ROT_MODE_180_DEGREE
- RGA_SRC_ROT_MODE_270_DEGREE
- RGA_SRC_ROT_MODE_90_DEGREE
- RGA_SRC_TRANS_ENABLE_A
- RGA_SRC_TRANS_ENABLE_B
- RGA_SRC_TRANS_ENABLE_G
- RGA_SRC_TRANS_ENABLE_R
- RGA_SRC_TR_COLOR0
- RGA_SRC_TR_COLOR1
- RGA_SRC_VIR_INFO
- RGA_SRC_VSCL_MODE_DOWN
- RGA_SRC_VSCL_MODE_NO
- RGA_SRC_VSCL_MODE_UP
- RGA_SRC_X_FACTOR
- RGA_SRC_Y_FACTOR
- RGA_SRC_Y_RGB_BASE_ADDR
- RGA_SYS_CTRL
- RGA_TIMEOUT
- RGA_VERSION_INFO
- RGB
- RGB08_COMPOSED
- RGB1
- RGB111110_FIX
- RGB111110_FLOAT
- RGB12A
- RGB12B
- RGB15_COMPOSED
- RGB15_TO_COLORKEY
- RGB16
- RGB16_555
- RGB16_565
- RGB16_655
- RGB16_664
- RGB16_COMPOSED
- RGB16_TO_COLORKEY
- RGB18
- RGB1_ENABLE
- RGB2
- RGB24
- RGB24_BPP
- RGB24_COMPOSED
- RGB2YUV
- RGB2_ENABLE
- RGB3
- RGB32_BPP
- RGB32_COMPOSED
- RGB444_10B
- RGB444_12B
- RGB444_16B
- RGB444_2X8_PADHI_BE
- RGB444_2X8_PADHI_LE
- RGB444_8B
- RGB555_2X8_PADHI_BE
- RGB555_2X8_PADHI_LE
- RGB565
- RGB565_2X8_BE
- RGB565_2X8_LE
- RGB565_BPP
- RGB666_1X18
- RGB8
- RGB888_1X24
- RGB888_2X12_BE
- RGB888_2X12_LE
- RGB888_TO_RGB565
- RGB888_TO_RGB666
- RGB9
- RGBA1010102
- RGBA16161616_10LSB
- RGBA16161616_10MSB
- RGBA16161616_12LSB
- RGBA16161616_12MSB
- RGBA16161616_FLOAT
- RGBA16161616_SNORM
- RGBA16161616_UNORM
- RGBA4444
- RGBA5551
- RGBA8888
- RGBA_BITS_A
- RGBA_BITS_B
- RGBA_BITS_G
- RGBA_BITS_R
- RGBFULL_ITU601
- RGBFULL_ITU709
- RGBLIMITED_ITU601
- RGBLIMITED_ITU709
- RGBLIMITED_RGBFULL
- RGBMAXDELTA
- RGBSenseDataOffset
- RGBT
- RGB_16
- RGB_4
- RGB_565_FMT
- RGB_666_FMT
- RGB_8
- RGB_888_FMT
- RGB_BASE_ADDR
- RGB_COEFF_ADDR
- RGB_FLIP_TO_BGR
- RGB_OUTPUT_SELECT
- RGB_QUANTIZATION_DEFAULT_RANGE
- RGB_QUANTIZATION_FULL_RANGE
- RGB_QUANTIZATION_LIMITED_RANGE
- RGB_QUANTIZATION_RESERVED
- RGB_TEST_DATA
- RGB_TIME
- RGB_TV_CLK
- RGB_VRFB_BPP
- RGDelay
- RGEN
- RGF_CAF_ICR
- RGF_CAF_ICR_TALYN_MB
- RGF_CAF_OSC_CONTROL
- RGF_CAF_PLL_LOCK_STATUS
- RGF_DMA_EP_MISC_ICR
- RGF_DMA_EP_RX_ICR
- RGF_DMA_EP_TX_ICR
- RGF_DMA_ITR_CNT_CRL
- RGF_DMA_ITR_CNT_DATA
- RGF_DMA_ITR_CNT_TRSH
- RGF_DMA_ITR_RX_CNT_CTL
- RGF_DMA_ITR_RX_CNT_DATA
- RGF_DMA_ITR_RX_CNT_TRSH
- RGF_DMA_ITR_RX_DESQ_NO_MOD
- RGF_DMA_ITR_RX_IDL_CNT_CTL
- RGF_DMA_ITR_RX_IDL_CNT_DATA
- RGF_DMA_ITR_RX_IDL_CNT_TRSH
- RGF_DMA_ITR_TX_CNT_CTL
- RGF_DMA_ITR_TX_CNT_DATA
- RGF_DMA_ITR_TX_CNT_TRSH
- RGF_DMA_ITR_TX_DESQ_NO_MOD
- RGF_DMA_ITR_TX_IDL_CNT_CTL
- RGF_DMA_ITR_TX_IDL_CNT_DATA
- RGF_DMA_ITR_TX_IDL_CNT_TRSH
- RGF_DMA_MISC_CTL
- RGF_DMA_OFUL_NID_0
- RGF_DMA_PSEUDO_CAUSE
- RGF_DMA_PSEUDO_CAUSE_MASK_FW
- RGF_DMA_PSEUDO_CAUSE_MASK_SW
- RGF_DMA_SCM_COMPQ_PROD
- RGF_DMA_SCM_SUBQ_CONS
- RGF_HP_CTRL
- RGF_ICR
- RGF_INT_COUNT_ON_SPECIAL_EVT
- RGF_INT_CTRL_INT_GEN_CFG_0
- RGF_INT_CTRL_INT_GEN_CFG_1
- RGF_INT_CTRL_RX_INT_MASK
- RGF_INT_CTRL_TX_INT_MASK
- RGF_INT_GEN_CTRL
- RGF_INT_GEN_IDLE_TIME_LIMIT
- RGF_INT_GEN_RX_ICR
- RGF_INT_GEN_TIME_UNIT_LIMIT
- RGF_INT_GEN_TX_ICR
- RGF_MAC_MTRL_COUNTER_0
- RGF_MBOX
- RGF_OTP_MAC
- RGF_OTP_MAC_TALYN_MB
- RGF_OTP_OEM_MAC
- RGF_OTP_QC_SECURED
- RGF_PAL_UNIT_ICR
- RGF_PCIE_LOS_COUNTER_CTL
- RGF_SCM_PTRS_COMPQ_RD_PTR
- RGF_SCM_PTRS_SUBQ_RD_PTR
- RGF_USER_BL
- RGF_USER_CLKS_CTL_0
- RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0
- RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1
- RGF_USER_CLKS_CTL_SW_RST_MASK_0
- RGF_USER_CLKS_CTL_SW_RST_VEC_0
- RGF_USER_CLKS_CTL_SW_RST_VEC_1
- RGF_USER_CLKS_CTL_SW_RST_VEC_2
- RGF_USER_CLKS_CTL_SW_RST_VEC_3
- RGF_USER_CPU_PC
- RGF_USER_FW_CALIB_RESULT
- RGF_USER_FW_REV_ID
- RGF_USER_HW_MACHINE_STATE
- RGF_USER_JTAG_DEV_ID
- RGF_USER_MAC_CPU_0
- RGF_USER_MAC_CPU_0_TALYN_MB
- RGF_USER_OTP_HW_RD_MACHINE_1
- RGF_USER_REVISION_ID
- RGF_USER_REVISION_ID_MASK
- RGF_USER_SPARROW_M_4
- RGF_USER_USAGE_1
- RGF_USER_USAGE_2
- RGF_USER_USAGE_6
- RGF_USER_USAGE_8
- RGF_USER_USER_CPU_0
- RGF_USER_USER_CPU_0_TALYN_MB
- RGF_USER_USER_ICR
- RGF_USER_USER_SCRATCH_PAD
- RGF_USER_XPM_IFC_RD_TIME1
- RGF_USER_XPM_IFC_RD_TIME10
- RGF_USER_XPM_IFC_RD_TIME2
- RGF_USER_XPM_IFC_RD_TIME3
- RGF_USER_XPM_IFC_RD_TIME4
- RGF_USER_XPM_IFC_RD_TIME5
- RGF_USER_XPM_IFC_RD_TIME6
- RGF_USER_XPM_IFC_RD_TIME7
- RGF_USER_XPM_IFC_RD_TIME8
- RGF_USER_XPM_IFC_RD_TIME9
- RGF_USER_XPM_RD_DOUT_SAMPLE_TIME
- RGGPE
- RGI1
- RGI1bh
- RGI1bl
- RGI2
- RGI2bh
- RGI2bl
- RGI3
- RGI3bh
- RGI3bl
- RGI4
- RGI4bh
- RGI4bl
- RGIO
- RGLOBALCTRL
- RGLVL
- RGMII_1000_NOM_CLK_FREQ
- RGMII_AXON
- RGMII_CONFIG2_CLK_DIVIDE_SEL
- RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL
- RGMII_CONFIG2_RGMII_CLK_SEL_CFG
- RGMII_CONFIG2_RSVD_CONFIG15
- RGMII_CONFIG2_RX_PROG_SWAP
- RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN
- RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN
- RGMII_CONFIG_BYPASS_TX_ID_EN
- RGMII_CONFIG_DDR_MODE
- RGMII_CONFIG_FUNC_CLK_EN
- RGMII_CONFIG_GPIO_CFG_RX_INT
- RGMII_CONFIG_GPIO_CFG_TX_INT
- RGMII_CONFIG_INTF_SEL
- RGMII_CONFIG_LOOPBACK_EN
- RGMII_CONFIG_MAX_SPD_PRG_2
- RGMII_CONFIG_MAX_SPD_PRG_9
- RGMII_CONFIG_POS_NEG_DATA_SEL
- RGMII_CONFIG_PROG_SWAP
- RGMII_CTRL_DLL_RXC
- RGMII_CTRL_DLL_TXC
- RGMII_CTRL_ENABLE_GMII
- RGMII_CTRL_TIMING_SEL
- RGMII_DBG
- RGMII_DBG2
- RGMII_FER_GMII
- RGMII_FER_MASK
- RGMII_FER_MII
- RGMII_FER_RGMII
- RGMII_FER_RTBI
- RGMII_FER_TBI
- RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ
- RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ
- RGMII_IO_MACRO_CONFIG
- RGMII_IO_MACRO_CONFIG2
- RGMII_IO_MACRO_DEBUG1
- RGMII_LINK
- RGMII_LINK_MAC_PHY
- RGMII_LINK_MAC_PHY_NO_MDIO
- RGMII_MODE
- RGMII_MODE_EN
- RGMII_MODE_EN_V123
- RGMII_REG_0
- RGMII_REG_0_ADDR
- RGMII_REG_STATUS_LINK
- RGMII_RX_BYP_DLL
- RGMII_RX_BYP_DLL_RX_DLL_BYPASS_
- RGMII_RX_BYP_DLL_RX_DLL_RESET_
- RGMII_RX_BYP_DLL_RX_TUNE_ADJ_MASK_
- RGMII_RX_BYP_DLL_RX_TUNE_SEL_MASK_
- RGMII_RX_CLK_DELAY_0_2_NS
- RGMII_RX_CLK_DELAY_0_8_NS
- RGMII_RX_CLK_DELAY_1_1_NS
- RGMII_RX_CLK_DELAY_1_7_NS
- RGMII_RX_CLK_DELAY_2_0_NS
- RGMII_RX_CLK_DELAY_2_3_NS
- RGMII_RX_CLK_DELAY_2_6_NS
- RGMII_RX_CLK_DELAY_3_4_NS
- RGMII_RX_CLK_DELAY_MASK
- RGMII_RX_CLK_DELAY_POS
- RGMII_SPEED_10
- RGMII_SPEED_100
- RGMII_SPEED_1000
- RGMII_SSR_10
- RGMII_SSR_100
- RGMII_SSR_1000
- RGMII_SSR_MASK
- RGMII_STANDARD
- RGMII_TX_BYP_DLL
- RGMII_TX_BYP_DLL_TX_DLL_BYPASS_
- RGMII_TX_BYP_DLL_TX_DLL_RESET_
- RGMII_TX_BYP_DLL_TX_TUNE_ADJ_MASK_
- RGMII_TX_BYP_DLL_TX_TUNE_SEL_MASK_
- RGND_INTP_1K
- RGND_INTP_2K
- RGND_INTP_MASK
- RGND_INTP_OPEN
- RGND_INTP_SHORT
- RGND_READY_INT
- RGND_READY_MASK
- RGN_BASE
- RGN_BITS
- RGN_GATE
- RGN_HPAGE
- RGN_KERNEL
- RGN_MAP_LIMIT
- RGN_MAP_SHIFT
- RGN_SHIFT
- RGN_UNCACHED
- RGPDATA
- RGPRDPT
- RGPVG
- RGPWRPT
- RGRP_RSRV_ADDBLKS
- RGRP_RSRV_MINBLKS
- RGS1
- RGS1d
- RGS2
- RGS2d
- RGS3
- RGS3d
- RGSMI
- RGSRC_REG_DBG_DWORD_ENABLE_E5
- RGSRC_REG_DBG_FORCE_FRAME_E5
- RGSRC_REG_DBG_FORCE_VALID_E5
- RGSRC_REG_DBG_SELECT_E5
- RGSRC_REG_DBG_SHIFT_E5
- RGS_AUDRCTUNE0READ_MASK
- RGS_AUDRCTUNE0READ_MASK_SFT
- RGS_AUDRCTUNE0READ_SFT
- RGS_AUDRCTUNE1READ_MASK
- RGS_AUDRCTUNE1READ_MASK_SFT
- RGS_AUDRCTUNE1READ_SFT
- RGS_AUDRCTUNELREAD_MASK
- RGS_AUDRCTUNELREAD_MASK_SFT
- RGS_AUDRCTUNELREAD_SFT
- RGS_AUDRCTUNERREAD_MASK
- RGS_AUDRCTUNERREAD_MASK_SFT
- RGS_AUDRCTUNERREAD_SFT
- RGS_HDMITX_2T1_EDG
- RGS_HDMITX_2T1_LEV
- RGS_HDMITX_5T1_EDG
- RGS_HDMITX_5T1_LEV
- RGS_HDMITX_PLL_AUTOK_BAND
- RGS_HDMITX_PLL_AUTOK_FAIL
- RGS_HDMITX_PLUG_TST
- RGTNE
- RGTPE
- RGTRY_OFT
- RGTRY_SZ
- RGTS
- RG_A1P6M_EN_SEL_MASK
- RG_A1P6M_EN_SEL_MASK_SFT
- RG_A1P6M_EN_SEL_SFT
- RG_ABIDEC_RSVD0_VA28_MASK
- RG_ABIDEC_RSVD0_VA28_MASK_SFT
- RG_ABIDEC_RSVD0_VA28_SFT
- RG_ABIDEC_RSVD0_VAUDP15_MASK
- RG_ABIDEC_RSVD0_VAUDP15_MASK_SFT
- RG_ABIDEC_RSVD0_VAUDP15_SFT
- RG_ABIDEC_RSVD0_VAUDP28_MASK
- RG_ABIDEC_RSVD0_VAUDP28_MASK_SFT
- RG_ABIDEC_RSVD0_VAUDP28_SFT
- RG_ABIDEC_RSVD0_VAUDP32_HPL_BIT
- RG_ABIDEC_RSVD0_VAUDP32_HPR_BIT
- RG_ABIDEC_RSVD0_VAUDP32_HS_BIT
- RG_ABIDEC_RSVD0_VAUDP32_LOL_BIT
- RG_ABIDEC_RSVD1_VAUDP15_MASK
- RG_ABIDEC_RSVD1_VAUDP15_MASK_SFT
- RG_ABIDEC_RSVD1_VAUDP15_SFT
- RG_ABIDEC_RSVD2_VAUDP15_MASK
- RG_ABIDEC_RSVD2_VAUDP15_MASK_SFT
- RG_ABIDEC_RSVD2_VAUDP15_SFT
- RG_ACCDET2AUXBUFFERBYPASS_MASK
- RG_ACCDET2AUXBUFFERBYPASS_MASK_SFT
- RG_ACCDET2AUXBUFFERBYPASS_SFT
- RG_ACCDET2AUXRESBYPASS_MASK
- RG_ACCDET2AUXRESBYPASS_MASK_SFT
- RG_ACCDET2AUXRESBYPASS_SFT
- RG_ACCDET2AUXSWEN_MASK
- RG_ACCDET2AUXSWEN_MASK_SFT
- RG_ACCDET2AUXSWEN_SFT
- RG_ACCDETSEL_MASK
- RG_ACCDETSEL_MASK_SFT
- RG_ACCDETSEL_SFT
- RG_ACCDET_CK_PDN_MASK
- RG_ACCDET_CK_PDN_MASK_SFT
- RG_ACCDET_CK_PDN_SFT
- RG_ACCDET_RST_MASK
- RG_ACCDET_RST_MASK_SFT
- RG_ACCDET_RST_SFT
- RG_AFE_ON_BIT
- RG_AMIC_UL_ADC_CLK_SEL_MASK
- RG_AMIC_UL_ADC_CLK_SEL_MASK_SFT
- RG_AMIC_UL_ADC_CLK_SEL_SFT
- RG_ANT_DIV
- RG_AUD26M_CK_TSTSEL_MASK
- RG_AUD26M_CK_TSTSEL_MASK_SFT
- RG_AUD26M_CK_TSTSEL_SFT
- RG_AUD26M_CK_TST_DIS_MASK
- RG_AUD26M_CK_TST_DIS_MASK_SFT
- RG_AUD26M_CK_TST_DIS_SFT
- RG_AUDACCDETMICBIAS0PULLLOW_MASK
- RG_AUDACCDETMICBIAS0PULLLOW_MASK_SFT
- RG_AUDACCDETMICBIAS0PULLLOW_SFT
- RG_AUDACCDETMICBIAS1PULLLOW_MASK
- RG_AUDACCDETMICBIAS1PULLLOW_MASK_SFT
- RG_AUDACCDETMICBIAS1PULLLOW_SFT
- RG_AUDACCDETTVDET_MASK
- RG_AUDACCDETTVDET_MASK_SFT
- RG_AUDACCDETTVDET_SFT
- RG_AUDACCDETVIN1PULLLOW_MASK
- RG_AUDACCDETVIN1PULLLOW_MASK_SFT
- RG_AUDACCDETVIN1PULLLOW_SFT
- RG_AUDACCDETVTHACAL_MASK
- RG_AUDACCDETVTHACAL_MASK_SFT
- RG_AUDACCDETVTHACAL_SFT
- RG_AUDACCDETVTHBCAL_MASK
- RG_AUDACCDETVTHBCAL_MASK_SFT
- RG_AUDACCDETVTHBCAL_SFT
- RG_AUDADC1STSTAGEIDDTEST_MASK
- RG_AUDADC1STSTAGEIDDTEST_MASK_SFT
- RG_AUDADC1STSTAGEIDDTEST_SFT
- RG_AUDADC1STSTAGELPEN_MASK
- RG_AUDADC1STSTAGELPEN_MASK_SFT
- RG_AUDADC1STSTAGELPEN_SFT
- RG_AUDADC1STSTAGESDENB_MASK
- RG_AUDADC1STSTAGESDENB_MASK_SFT
- RG_AUDADC1STSTAGESDENB_SFT
- RG_AUDADC2NDSTAGEIDDTEST_MASK
- RG_AUDADC2NDSTAGEIDDTEST_MASK_SFT
- RG_AUDADC2NDSTAGEIDDTEST_SFT
- RG_AUDADC2NDSTAGELPEN_MASK
- RG_AUDADC2NDSTAGELPEN_MASK_SFT
- RG_AUDADC2NDSTAGELPEN_SFT
- RG_AUDADC2NDSTAGERESET_MASK
- RG_AUDADC2NDSTAGERESET_MASK_SFT
- RG_AUDADC2NDSTAGERESET_SFT
- RG_AUDADC3RDSTAGERESET_MASK
- RG_AUDADC3RDSTAGERESET_MASK_SFT
- RG_AUDADC3RDSTAGERESET_SFT
- RG_AUDADCBYPASS_MASK
- RG_AUDADCBYPASS_MASK_SFT
- RG_AUDADCBYPASS_SFT
- RG_AUDADCCLKRSTB
- RG_AUDADCCLKSEL_MASK
- RG_AUDADCCLKSEL_MASK_SFT
- RG_AUDADCCLKSEL_SFT
- RG_AUDADCCLKSOURCE_MASK
- RG_AUDADCCLKSOURCE_MASK_SFT
- RG_AUDADCCLKSOURCE_SFT
- RG_AUDADCDAC0P25FS_MASK
- RG_AUDADCDAC0P25FS_MASK_SFT
- RG_AUDADCDAC0P25FS_SFT
- RG_AUDADCDACFBCURRENT_MASK
- RG_AUDADCDACFBCURRENT_MASK_SFT
- RG_AUDADCDACFBCURRENT_SFT
- RG_AUDADCDACIDDTEST_MASK
- RG_AUDADCDACIDDTEST_MASK_SFT
- RG_AUDADCDACIDDTEST_SFT
- RG_AUDADCDACNRZ_MASK
- RG_AUDADCDACNRZ_MASK_SFT
- RG_AUDADCDACNRZ_SFT
- RG_AUDADCDACTEST_MASK
- RG_AUDADCDACTEST_MASK_SFT
- RG_AUDADCDACTEST_SFT
- RG_AUDADCFFBYPASS_MASK
- RG_AUDADCFFBYPASS_MASK_SFT
- RG_AUDADCFFBYPASS_SFT
- RG_AUDADCFLASHIDDTEST_MASK
- RG_AUDADCFLASHIDDTEST_MASK_SFT
- RG_AUDADCFLASHIDDTEST_SFT
- RG_AUDADCFLASHLPEN_MASK
- RG_AUDADCFLASHLPEN_MASK_SFT
- RG_AUDADCFLASHLPEN_SFT
- RG_AUDADCFSRESET_MASK
- RG_AUDADCFSRESET_MASK_SFT
- RG_AUDADCFSRESET_SFT
- RG_AUDADCLINPUTSEL_MASK
- RG_AUDADCLINPUTSEL_MASK_SFT
- RG_AUDADCLINPUTSEL_SFT
- RG_AUDADCLPWRUP
- RG_AUDADCLPWRUP_MASK
- RG_AUDADCLPWRUP_MASK_SFT
- RG_AUDADCLPWRUP_SFT
- RG_AUDADCNODEM_MASK
- RG_AUDADCNODEM_MASK_SFT
- RG_AUDADCNODEM_SFT
- RG_AUDADCNOPATEST_MASK
- RG_AUDADCNOPATEST_MASK_SFT
- RG_AUDADCNOPATEST_SFT
- RG_AUDADCREFBUFIDDTEST_MASK
- RG_AUDADCREFBUFIDDTEST_MASK_SFT
- RG_AUDADCREFBUFIDDTEST_SFT
- RG_AUDADCRINPUTSEL_MASK
- RG_AUDADCRINPUTSEL_MASK_SFT
- RG_AUDADCRINPUTSEL_SFT
- RG_AUDADCRPWRUP
- RG_AUDADCRPWRUP_MASK
- RG_AUDADCRPWRUP_MASK_SFT
- RG_AUDADCRPWRUP_SFT
- RG_AUDADCWIDECM_MASK
- RG_AUDADCWIDECM_MASK_SFT
- RG_AUDADCWIDECM_SFT
- RG_AUDBIASADJ_0_VAUDP15_MASK
- RG_AUDBIASADJ_0_VAUDP15_MASK_SFT
- RG_AUDBIASADJ_0_VAUDP15_SFT
- RG_AUDBIASADJ_1_VAUDP15_MASK
- RG_AUDBIASADJ_1_VAUDP15_MASK_SFT
- RG_AUDBIASADJ_1_VAUDP15_SFT
- RG_AUDDACLPWRUP_VAUDP15_MASK
- RG_AUDDACLPWRUP_VAUDP15_MASK_SFT
- RG_AUDDACLPWRUP_VAUDP15_SFT
- RG_AUDDACLPWRUP_VAUDP32_BIT
- RG_AUDDACRPWRUP_VAUDP15_MASK
- RG_AUDDACRPWRUP_VAUDP15_MASK_SFT
- RG_AUDDACRPWRUP_VAUDP15_SFT
- RG_AUDDACRPWRUP_VAUDP32_BIT
- RG_AUDDIGMICBIAS_MASK
- RG_AUDDIGMICBIAS_MASK_SFT
- RG_AUDDIGMICBIAS_SFT
- RG_AUDDIGMICEN_MASK
- RG_AUDDIGMICEN_MASK_SFT
- RG_AUDDIGMICEN_SFT
- RG_AUDDIGMICNDUTY_MASK
- RG_AUDDIGMICNDUTY_MASK_SFT
- RG_AUDDIGMICNDUTY_SFT
- RG_AUDDIGMICPDUTY_MASK
- RG_AUDDIGMICPDUTY_MASK_SFT
- RG_AUDDIGMICPDUTY_SFT
- RG_AUDENCSPARE2_MASK
- RG_AUDENCSPARE2_MASK_SFT
- RG_AUDENCSPARE2_SFT
- RG_AUDENCSPARE_MASK
- RG_AUDENCSPARE_MASK_SFT
- RG_AUDENCSPARE_SFT
- RG_AUDGLBVOWLPWEN_MASK
- RG_AUDGLBVOWLPWEN_MASK_SFT
- RG_AUDGLBVOWLPWEN_SFT
- RG_AUDGLB_LP2_VOW_EN_VA32
- RG_AUDGLB_PWRDN_VA28_MASK
- RG_AUDGLB_PWRDN_VA28_MASK_SFT
- RG_AUDGLB_PWRDN_VA28_SFT
- RG_AUDGLB_PWRDN_VA32_BIT
- RG_AUDHPDECMGAINADJ_VAUDP15_MASK
- RG_AUDHPDECMGAINADJ_VAUDP15_MASK_SFT
- RG_AUDHPDECMGAINADJ_VAUDP15_SFT
- RG_AUDHPDEDMGAINADJ_VAUDP15_MASK
- RG_AUDHPDEDMGAINADJ_VAUDP15_MASK_SFT
- RG_AUDHPDEDMGAINADJ_VAUDP15_SFT
- RG_AUDHPLBSCCURRENT_VAUDP15_MASK
- RG_AUDHPLBSCCURRENT_VAUDP15_MASK_SFT
- RG_AUDHPLBSCCURRENT_VAUDP15_SFT
- RG_AUDHPLGAIN_MASK
- RG_AUDHPLGAIN_MASK_SFT
- RG_AUDHPLGAIN_SFT
- RG_AUDHPLMUXINPUTSEL_VAUDP15_MASK
- RG_AUDHPLMUXINPUTSEL_VAUDP15_MASK_SFT
- RG_AUDHPLMUXINPUTSEL_VAUDP15_SFT
- RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK
- RG_AUDHPLMUXINPUTSEL_VAUDP32_SFT
- RG_AUDHPLOUTAUXPWRUP_VAUDP15_MASK
- RG_AUDHPLOUTAUXPWRUP_VAUDP15_MASK_SFT
- RG_AUDHPLOUTAUXPWRUP_VAUDP15_SFT
- RG_AUDHPLOUTPWRUP_VAUDP15_MASK
- RG_AUDHPLOUTPWRUP_VAUDP15_MASK_SFT
- RG_AUDHPLOUTPWRUP_VAUDP15_SFT
- RG_AUDHPLPWRUP_IBIAS_VAUDP15_MASK
- RG_AUDHPLPWRUP_IBIAS_VAUDP15_MASK_SFT
- RG_AUDHPLPWRUP_IBIAS_VAUDP15_SFT
- RG_AUDHPLPWRUP_VAUDP15_MASK
- RG_AUDHPLPWRUP_VAUDP15_MASK_SFT
- RG_AUDHPLPWRUP_VAUDP15_SFT
- RG_AUDHPLPWRUP_VAUDP32_BIT
- RG_AUDHPLSCDISABLE_VAUDP15_MASK
- RG_AUDHPLSCDISABLE_VAUDP15_MASK_SFT
- RG_AUDHPLSCDISABLE_VAUDP15_SFT
- RG_AUDHPLSCDISABLE_VAUDP32_BIT
- RG_AUDHPRBSCCURRENT_VAUDP15_MASK
- RG_AUDHPRBSCCURRENT_VAUDP15_MASK_SFT
- RG_AUDHPRBSCCURRENT_VAUDP15_SFT
- RG_AUDHPRGAIN_MASK
- RG_AUDHPRGAIN_MASK_SFT
- RG_AUDHPRGAIN_SFT
- RG_AUDHPRMUXINPUTSEL_VAUDP15_MASK
- RG_AUDHPRMUXINPUTSEL_VAUDP15_MASK_SFT
- RG_AUDHPRMUXINPUTSEL_VAUDP15_SFT
- RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK
- RG_AUDHPRMUXINPUTSEL_VAUDP32_SFT
- RG_AUDHPROUTAUXPWRUP_VAUDP15_MASK
- RG_AUDHPROUTAUXPWRUP_VAUDP15_MASK_SFT
- RG_AUDHPROUTAUXPWRUP_VAUDP15_SFT
- RG_AUDHPROUTPWRUP_VAUDP15_MASK
- RG_AUDHPROUTPWRUP_VAUDP15_MASK_SFT
- RG_AUDHPROUTPWRUP_VAUDP15_SFT
- RG_AUDHPRPWRUP_IBIAS_VAUDP15_MASK
- RG_AUDHPRPWRUP_IBIAS_VAUDP15_MASK_SFT
- RG_AUDHPRPWRUP_IBIAS_VAUDP15_SFT
- RG_AUDHPRPWRUP_VAUDP15_MASK
- RG_AUDHPRPWRUP_VAUDP15_MASK_SFT
- RG_AUDHPRPWRUP_VAUDP15_SFT
- RG_AUDHPRPWRUP_VAUDP32_BIT
- RG_AUDHPRSCDISABLE_VAUDP15_MASK
- RG_AUDHPRSCDISABLE_VAUDP15_MASK_SFT
- RG_AUDHPRSCDISABLE_VAUDP15_SFT
- RG_AUDHPRSCDISABLE_VAUDP32_BIT
- RG_AUDHPSPKDET_EN_VAUDP15_MASK
- RG_AUDHPSPKDET_EN_VAUDP15_MASK_SFT
- RG_AUDHPSPKDET_EN_VAUDP15_SFT
- RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_MASK
- RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_MASK_SFT
- RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_SFT
- RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_MASK
- RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_MASK_SFT
- RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_SFT
- RG_AUDHPSTARTUP_VAUDP15_MASK
- RG_AUDHPSTARTUP_VAUDP15_MASK_SFT
- RG_AUDHPSTARTUP_VAUDP15_SFT
- RG_AUDHSBSCCURRENT_VAUDP15_MASK
- RG_AUDHSBSCCURRENT_VAUDP15_MASK_SFT
- RG_AUDHSBSCCURRENT_VAUDP15_SFT
- RG_AUDHSGAIN_MASK
- RG_AUDHSGAIN_MASK_SFT
- RG_AUDHSGAIN_SFT
- RG_AUDHSMUXINPUTSEL_VAUDP15_MASK
- RG_AUDHSMUXINPUTSEL_VAUDP15_MASK_SFT
- RG_AUDHSMUXINPUTSEL_VAUDP15_SFT
- RG_AUDHSMUXINPUTSEL_VAUDP32_MASK
- RG_AUDHSMUXINPUTSEL_VAUDP32_SFT
- RG_AUDHSPWRUP_IBIAS_VAUDP15_MASK
- RG_AUDHSPWRUP_IBIAS_VAUDP15_MASK_SFT
- RG_AUDHSPWRUP_IBIAS_VAUDP15_SFT
- RG_AUDHSPWRUP_VAUDP15_MASK
- RG_AUDHSPWRUP_VAUDP15_MASK_SFT
- RG_AUDHSPWRUP_VAUDP15_SFT
- RG_AUDHSPWRUP_VAUDP32_BIT
- RG_AUDHSSCDISABLE_VAUDP15_MASK
- RG_AUDHSSCDISABLE_VAUDP15_MASK_SFT
- RG_AUDHSSCDISABLE_VAUDP15_SFT
- RG_AUDHSSCDISABLE_VAUDP32
- RG_AUDHSSTARTUP_VAUDP15_MASK
- RG_AUDHSSTARTUP_VAUDP15_MASK_SFT
- RG_AUDHSSTARTUP_VAUDP15_SFT
- RG_AUDIBIASPWRDN_VAUDP15_MASK
- RG_AUDIBIASPWRDN_VAUDP15_MASK_SFT
- RG_AUDIBIASPWRDN_VAUDP15_SFT
- RG_AUDIBIASPWRDN_VAUDP32_BIT
- RG_AUDIF_CK_CKSEL_MASK
- RG_AUDIF_CK_CKSEL_MASK_SFT
- RG_AUDIF_CK_CKSEL_SFT
- RG_AUDIF_CK_PDN_BIT
- RG_AUDIF_CK_PDN_MASK
- RG_AUDIF_CK_PDN_MASK_SFT
- RG_AUDIF_CK_PDN_SFT
- RG_AUDIF_CK_TSTSEL_MASK
- RG_AUDIF_CK_TSTSEL_MASK_SFT
- RG_AUDIF_CK_TSTSEL_SFT
- RG_AUDINTGAIN1_MASK
- RG_AUDINTGAIN1_MASK_SFT
- RG_AUDINTGAIN1_SFT
- RG_AUDINTGAIN2_MASK
- RG_AUDINTGAIN2_MASK_SFT
- RG_AUDINTGAIN2_SFT
- RG_AUDIO_RST_MASK
- RG_AUDIO_RST_MASK_SFT
- RG_AUDIO_RST_SFT
- RG_AUDIO_VOW_EN_MASK
- RG_AUDIO_VOW_EN_MASK_SFT
- RG_AUDIO_VOW_EN_SFT
- RG_AUDIVLGAIN_MASK
- RG_AUDIVLGAIN_MASK_SFT
- RG_AUDIVLGAIN_SFT
- RG_AUDIVRGAIN_MASK
- RG_AUDIVRGAIN_MASK_SFT
- RG_AUDIVRGAIN_SFT
- RG_AUDLOLBSCCURRENT_VAUDP15_MASK
- RG_AUDLOLBSCCURRENT_VAUDP15_MASK_SFT
- RG_AUDLOLBSCCURRENT_VAUDP15_SFT
- RG_AUDLOLGAIN_MASK
- RG_AUDLOLGAIN_MASK_SFT
- RG_AUDLOLGAIN_SFT
- RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK
- RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK_SFT
- RG_AUDLOLMUXINPUTSEL_VAUDP15_SFT
- RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK
- RG_AUDLOLMUXINPUTSEL_VAUDP32_SFT
- RG_AUDLOLPWRUP_IBIAS_VAUDP15_MASK
- RG_AUDLOLPWRUP_IBIAS_VAUDP15_MASK_SFT
- RG_AUDLOLPWRUP_IBIAS_VAUDP15_SFT
- RG_AUDLOLPWRUP_VAUDP15_MASK
- RG_AUDLOLPWRUP_VAUDP15_MASK_SFT
- RG_AUDLOLPWRUP_VAUDP15_SFT
- RG_AUDLOLPWRUP_VAUDP32_BIT
- RG_AUDLOLSCDISABLE_VAUDP15_MASK
- RG_AUDLOLSCDISABLE_VAUDP15_MASK_SFT
- RG_AUDLOLSCDISABLE_VAUDP15_SFT
- RG_AUDLOLSCDISABLE_VAUDP32_BIT
- RG_AUDLORGAIN_MASK
- RG_AUDLORGAIN_MASK_SFT
- RG_AUDLORGAIN_SFT
- RG_AUDLOSTARTUP_VAUDP15_MASK
- RG_AUDLOSTARTUP_VAUDP15_MASK_SFT
- RG_AUDLOSTARTUP_VAUDP15_SFT
- RG_AUDMICBIAS0BYPASSEN_MASK
- RG_AUDMICBIAS0BYPASSEN_MASK_SFT
- RG_AUDMICBIAS0BYPASSEN_SFT
- RG_AUDMICBIAS0DCSW0NEN_MASK
- RG_AUDMICBIAS0DCSW0NEN_MASK_SFT
- RG_AUDMICBIAS0DCSW0NEN_SFT
- RG_AUDMICBIAS0DCSW0P1EN_MASK
- RG_AUDMICBIAS0DCSW0P1EN_MASK_SFT
- RG_AUDMICBIAS0DCSW0P1EN_SFT
- RG_AUDMICBIAS0DCSW0P2EN_MASK
- RG_AUDMICBIAS0DCSW0P2EN_MASK_SFT
- RG_AUDMICBIAS0DCSW0P2EN_SFT
- RG_AUDMICBIAS0DCSW2NEN_MASK
- RG_AUDMICBIAS0DCSW2NEN_MASK_SFT
- RG_AUDMICBIAS0DCSW2NEN_SFT
- RG_AUDMICBIAS0DCSW2P1EN_MASK
- RG_AUDMICBIAS0DCSW2P1EN_MASK_SFT
- RG_AUDMICBIAS0DCSW2P1EN_SFT
- RG_AUDMICBIAS0DCSW2P2EN_MASK
- RG_AUDMICBIAS0DCSW2P2EN_MASK_SFT
- RG_AUDMICBIAS0DCSW2P2EN_SFT
- RG_AUDMICBIAS0LOWPEN
- RG_AUDMICBIAS0LOWPEN_MASK
- RG_AUDMICBIAS0LOWPEN_MASK_SFT
- RG_AUDMICBIAS0LOWPEN_SFT
- RG_AUDMICBIAS0VREF
- RG_AUDMICBIAS0VREF_MASK
- RG_AUDMICBIAS0VREF_MASK_SFT
- RG_AUDMICBIAS0VREF_SFT
- RG_AUDMICBIAS1BYPASSEN_MASK
- RG_AUDMICBIAS1BYPASSEN_MASK_SFT
- RG_AUDMICBIAS1BYPASSEN_SFT
- RG_AUDMICBIAS1DCSW1NEN
- RG_AUDMICBIAS1DCSW1NEN_MASK
- RG_AUDMICBIAS1DCSW1NEN_MASK_SFT
- RG_AUDMICBIAS1DCSW1NEN_SFT
- RG_AUDMICBIAS1DCSW1PEN_MASK
- RG_AUDMICBIAS1DCSW1PEN_MASK_SFT
- RG_AUDMICBIAS1DCSW1PEN_SFT
- RG_AUDMICBIAS1LOWPEN
- RG_AUDMICBIAS1LOWPEN_MASK
- RG_AUDMICBIAS1LOWPEN_MASK_SFT
- RG_AUDMICBIAS1LOWPEN_SFT
- RG_AUDMICBIAS1VREF
- RG_AUDMICBIAS1VREF_MASK
- RG_AUDMICBIAS1VREF_MASK_SFT
- RG_AUDMICBIAS1VREF_SFT
- RG_AUDMICBIAS2LOWPEN
- RG_AUDMICBIAS2VREF
- RG_AUDNCP_CK_PDN_BIT
- RG_AUDNCP_CK_PDN_MASK
- RG_AUDNCP_CK_PDN_MASK_SFT
- RG_AUDNCP_CK_PDN_SFT
- RG_AUDNCP_RST_MASK
- RG_AUDNCP_RST_MASK_SFT
- RG_AUDNCP_RST_SFT
- RG_AUDPMU_RSD0_VA18_MASK
- RG_AUDPMU_RSD0_VA18_MASK_SFT
- RG_AUDPMU_RSD0_VA18_SFT
- RG_AUDPMU_RSD0_VA28_MASK
- RG_AUDPMU_RSD0_VA28_MASK_SFT
- RG_AUDPMU_RSD0_VA28_SFT
- RG_AUDPMU_RSD0_VAUDP15_MASK
- RG_AUDPMU_RSD0_VAUDP15_MASK_SFT
- RG_AUDPMU_RSD0_VAUDP15_SFT
- RG_AUDPREAMPAAFEN_MASK
- RG_AUDPREAMPAAFEN_MASK_SFT
- RG_AUDPREAMPAAFEN_SFT
- RG_AUDPREAMPIDDTEST_MASK
- RG_AUDPREAMPIDDTEST_MASK_SFT
- RG_AUDPREAMPIDDTEST_SFT
- RG_AUDPREAMPLDCCEN
- RG_AUDPREAMPLDCCEN_MASK
- RG_AUDPREAMPLDCCEN_MASK_SFT
- RG_AUDPREAMPLDCCEN_SFT
- RG_AUDPREAMPLDCPRECHARGE
- RG_AUDPREAMPLDCPRECHARGE_MASK
- RG_AUDPREAMPLDCPRECHARGE_MASK_SFT
- RG_AUDPREAMPLDCPRECHARGE_SFT
- RG_AUDPREAMPLGAIN_MASK
- RG_AUDPREAMPLGAIN_MASK_SFT
- RG_AUDPREAMPLGAIN_SFT
- RG_AUDPREAMPLINPUTSEL_MASK
- RG_AUDPREAMPLINPUTSEL_MASK_SFT
- RG_AUDPREAMPLINPUTSEL_SFT
- RG_AUDPREAMPLON
- RG_AUDPREAMPLON_MASK
- RG_AUDPREAMPLON_MASK_SFT
- RG_AUDPREAMPLON_SFT
- RG_AUDPREAMPLPEN_MASK
- RG_AUDPREAMPLPEN_MASK_SFT
- RG_AUDPREAMPLPEN_SFT
- RG_AUDPREAMPLPGATEST_MASK
- RG_AUDPREAMPLPGATEST_MASK_SFT
- RG_AUDPREAMPLPGATEST_SFT
- RG_AUDPREAMPLVSCALE_MASK
- RG_AUDPREAMPLVSCALE_MASK_SFT
- RG_AUDPREAMPLVSCALE_SFT
- RG_AUDPREAMPRDCCEN
- RG_AUDPREAMPRDCCEN_MASK
- RG_AUDPREAMPRDCCEN_MASK_SFT
- RG_AUDPREAMPRDCCEN_SFT
- RG_AUDPREAMPRDCPRECHARGE
- RG_AUDPREAMPRDCPRECHARGE_MASK
- RG_AUDPREAMPRDCPRECHARGE_MASK_SFT
- RG_AUDPREAMPRDCPRECHARGE_SFT
- RG_AUDPREAMPRGAIN_MASK
- RG_AUDPREAMPRGAIN_MASK_SFT
- RG_AUDPREAMPRGAIN_SFT
- RG_AUDPREAMPRINPUTSEL_MASK
- RG_AUDPREAMPRINPUTSEL_MASK_SFT
- RG_AUDPREAMPRINPUTSEL_SFT
- RG_AUDPREAMPRON
- RG_AUDPREAMPRON_MASK
- RG_AUDPREAMPRON_MASK_SFT
- RG_AUDPREAMPRON_SFT
- RG_AUDPREAMPRPGATEST_MASK
- RG_AUDPREAMPRPGATEST_MASK_SFT
- RG_AUDPREAMPRPGATEST_SFT
- RG_AUDPREAMPRVSCALE_MASK
- RG_AUDPREAMPRVSCALE_MASK_SFT
- RG_AUDPREAMPRVSCALE_SFT
- RG_AUDPWDBMICBIAS0
- RG_AUDPWDBMICBIAS0_MASK
- RG_AUDPWDBMICBIAS0_MASK_SFT
- RG_AUDPWDBMICBIAS0_SFT
- RG_AUDPWDBMICBIAS1
- RG_AUDPWDBMICBIAS1_MASK
- RG_AUDPWDBMICBIAS1_MASK_SFT
- RG_AUDPWDBMICBIAS1_SFT
- RG_AUDPWDBMICBIAS2
- RG_AUDRCTUNELSEL_MASK
- RG_AUDRCTUNELSEL_MASK_SFT
- RG_AUDRCTUNELSEL_SFT
- RG_AUDRCTUNEL_MASK
- RG_AUDRCTUNEL_MASK_SFT
- RG_AUDRCTUNEL_SFT
- RG_AUDRCTUNERSEL_MASK
- RG_AUDRCTUNERSEL_MASK_SFT
- RG_AUDRCTUNERSEL_SFT
- RG_AUDRCTUNER_MASK
- RG_AUDRCTUNER_MASK_SFT
- RG_AUDRCTUNER_SFT
- RG_AUDREFN_DERES_EN_VAUDP15_MASK
- RG_AUDREFN_DERES_EN_VAUDP15_MASK_SFT
- RG_AUDREFN_DERES_EN_VAUDP15_SFT
- RG_AUDSPAREVMIC_MASK
- RG_AUDSPAREVMIC_MASK_SFT
- RG_AUDSPAREVMIC_SFT
- RG_AUDSPARE_MASK
- RG_AUDSPARE_MASK_SFT
- RG_AUDSPARE_SFT
- RG_AUDTRIMBUF_EN_VAUDP15_MASK
- RG_AUDTRIMBUF_EN_VAUDP15_MASK_SFT
- RG_AUDTRIMBUF_EN_VAUDP15_SFT
- RG_AUDTRIMBUF_GAINSEL_VAUDP15_MASK
- RG_AUDTRIMBUF_GAINSEL_VAUDP15_MASK_SFT
- RG_AUDTRIMBUF_GAINSEL_VAUDP15_SFT
- RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_MASK
- RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_MASK_SFT
- RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_SFT
- RG_AUDULHALFBIAS_MASK
- RG_AUDULHALFBIAS_MASK_SFT
- RG_AUDULHALFBIAS_SFT
- RG_AUDZCDCLKSEL_VAUDP15_MASK
- RG_AUDZCDCLKSEL_VAUDP15_MASK_SFT
- RG_AUDZCDCLKSEL_VAUDP15_SFT
- RG_AUDZCDENABLE_MASK
- RG_AUDZCDENABLE_MASK_SFT
- RG_AUDZCDENABLE_SFT
- RG_AUDZCDGAINSTEPSIZE_MASK
- RG_AUDZCDGAINSTEPSIZE_MASK_SFT
- RG_AUDZCDGAINSTEPSIZE_SFT
- RG_AUDZCDGAINSTEPTIME_MASK
- RG_AUDZCDGAINSTEPTIME_MASK_SFT
- RG_AUDZCDGAINSTEPTIME_SFT
- RG_AUDZCDMUXSEL_VAUDP15_MASK
- RG_AUDZCDMUXSEL_VAUDP15_MASK_SFT
- RG_AUDZCDMUXSEL_VAUDP15_SFT
- RG_AUDZCDTIMEOUTMODESEL_MASK
- RG_AUDZCDTIMEOUTMODESEL_MASK_SFT
- RG_AUDZCDTIMEOUTMODESEL_SFT
- RG_AUD_CK_CKSEL_MASK
- RG_AUD_CK_CKSEL_MASK_SFT
- RG_AUD_CK_CKSEL_SFT
- RG_AUD_CK_PDN_BIT
- RG_AUD_CK_PDN_MASK
- RG_AUD_CK_PDN_MASK_SFT
- RG_AUD_CK_PDN_SFT
- RG_AUD_CK_TSTSEL_MASK
- RG_AUD_CK_TSTSEL_MASK_SFT
- RG_AUD_CK_TSTSEL_SFT
- RG_AUD_CLK_INT_MON_FLAG_EN_MASK
- RG_AUD_CLK_INT_MON_FLAG_EN_MASK_SFT
- RG_AUD_CLK_INT_MON_FLAG_EN_SFT
- RG_AUD_CLK_INT_MON_FLAG_SEL_MASK
- RG_AUD_CLK_INT_MON_FLAG_SEL_MASK_SFT
- RG_AUD_CLK_INT_MON_FLAG_SEL_SFT
- RG_AUD_DAC_PWL_UP_VA28_MASK
- RG_AUD_DAC_PWL_UP_VA28_MASK_SFT
- RG_AUD_DAC_PWL_UP_VA28_SFT
- RG_AUD_DAC_PWL_UP_VA32_BIT
- RG_AUD_DAC_PWR_UP_VA28_MASK
- RG_AUD_DAC_PWR_UP_VA28_MASK_SFT
- RG_AUD_DAC_PWR_UP_VA28_SFT
- RG_AUD_DAC_PWR_UP_VA32_BIT
- RG_AUD_INTRP_CK_PDN_HWEN_MASK
- RG_AUD_INTRP_CK_PDN_HWEN_MASK_SFT
- RG_AUD_INTRP_CK_PDN_HWEN_SFT
- RG_AUD_INTRP_CK_PDN_MASK
- RG_AUD_INTRP_CK_PDN_MASK_SFT
- RG_AUD_INTRP_CK_PDN_SFT
- RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK
- RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK_SFT
- RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_SFT
- RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK
- RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK_SFT
- RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_SFT
- RG_AUD_INT_CON0_CLR_MASK
- RG_AUD_INT_CON0_CLR_MASK_SFT
- RG_AUD_INT_CON0_CLR_SFT
- RG_AUD_INT_CON0_SET_MASK
- RG_AUD_INT_CON0_SET_MASK_SFT
- RG_AUD_INT_CON0_SET_SFT
- RG_AUD_INT_MASK_CON0_CLR_MASK
- RG_AUD_INT_MASK_CON0_CLR_MASK_SFT
- RG_AUD_INT_MASK_CON0_CLR_SFT
- RG_AUD_INT_MASK_CON0_SET_MASK
- RG_AUD_INT_MASK_CON0_SET_MASK_SFT
- RG_AUD_INT_MASK_CON0_SET_SFT
- RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK
- RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT
- RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT
- RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK
- RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT
- RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT
- RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK
- RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK_SFT
- RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_SFT
- RG_AUD_PAD_TOP_PHASE_MODE2_MASK
- RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT
- RG_AUD_PAD_TOP_PHASE_MODE2_SFT
- RG_AUD_PAD_TOP_PHASE_MODE_MASK
- RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT
- RG_AUD_PAD_TOP_PHASE_MODE_SFT
- RG_AUD_PAD_TOP_TX_FIFO_ON_MASK
- RG_AUD_PAD_TOP_TX_FIFO_ON_MASK_SFT
- RG_AUD_PAD_TOP_TX_FIFO_ON_SFT
- RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK
- RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK_SFT
- RG_AUD_PAD_TOP_TX_FIFO_RSP_SFT
- RG_AUD_TOP_CKPDN_CON0_CLR_MASK
- RG_AUD_TOP_CKPDN_CON0_CLR_MASK_SFT
- RG_AUD_TOP_CKPDN_CON0_CLR_SFT
- RG_AUD_TOP_CKPDN_CON0_SET_MASK
- RG_AUD_TOP_CKPDN_CON0_SET_MASK_SFT
- RG_AUD_TOP_CKPDN_CON0_SET_SFT
- RG_AUD_TOP_CKSEL_CON0_CLR_MASK
- RG_AUD_TOP_CKSEL_CON0_CLR_MASK_SFT
- RG_AUD_TOP_CKSEL_CON0_CLR_SFT
- RG_AUD_TOP_CKSEL_CON0_SET_MASK
- RG_AUD_TOP_CKSEL_CON0_SET_MASK_SFT
- RG_AUD_TOP_CKSEL_CON0_SET_SFT
- RG_AUD_TOP_INT_POLARITY_MASK
- RG_AUD_TOP_INT_POLARITY_MASK_SFT
- RG_AUD_TOP_INT_POLARITY_SFT
- RG_AUD_TOP_MON_SEL_MASK
- RG_AUD_TOP_MON_SEL_MASK_SFT
- RG_AUD_TOP_MON_SEL_SFT
- RG_AUD_TOP_RST_CON0_CLR_MASK
- RG_AUD_TOP_RST_CON0_CLR_MASK_SFT
- RG_AUD_TOP_RST_CON0_CLR_SFT
- RG_AUD_TOP_RST_CON0_SET_MASK
- RG_AUD_TOP_RST_CON0_SET_MASK_SFT
- RG_AUD_TOP_RST_CON0_SET_SFT
- RG_BANDGAPGEN_MASK
- RG_BANDGAPGEN_MASK_SFT
- RG_BANDGAPGEN_SFT
- RG_BASELINE_ALPHA_ORDER_MASK
- RG_BASELINE_ALPHA_ORDER_MASK_SFT
- RG_BASELINE_ALPHA_ORDER_SFT
- RG_BATMON
- RG_BUCK_CLK_DIV_MASK
- RG_BUCK_CLK_DIV_MASK_SFT
- RG_BUCK_CLK_DIV_SFT
- RG_BUCK_DVFS_DONE_HW_MODE_MASK
- RG_BUCK_DVFS_DONE_HW_MODE_MASK_SFT
- RG_BUCK_DVFS_DONE_HW_MODE_SFT
- RG_BUCK_DVFS_DONE_SW_CTL_MASK
- RG_BUCK_DVFS_DONE_SW_CTL_MASK_SFT
- RG_BUCK_DVFS_DONE_SW_CTL_SFT
- RG_BUCK_DVFS_HW_CNT_THR_MASK
- RG_BUCK_DVFS_HW_CNT_THR_MASK_SFT
- RG_BUCK_DVFS_HW_CNT_THR_SFT
- RG_CCA_THRES
- RG_CDR_BC_GEN1_MSK
- RG_CDR_BC_GEN1_VAL
- RG_CDR_BICLTD0_GEN1_MSK
- RG_CDR_BICLTD0_GEN1_VAL
- RG_CDR_BICLTD1_GEN1_MSK
- RG_CDR_BICLTD1_GEN1_VAL
- RG_CDR_BICLTR_GEN1_MSK
- RG_CDR_BICLTR_GEN1_VAL
- RG_CDR_BIRLTD0_GEN1_MSK
- RG_CDR_BIRLTD0_GEN1_VAL
- RG_CDR_BIRLTD0_GEN3_MSK
- RG_CDR_BIRLTD0_GEN3_VAL
- RG_CDR_BIRLTR_GEN1_MSK
- RG_CDR_BIRLTR_GEN1_VAL
- RG_CDR_BR_GEN2_MSK
- RG_CDR_BR_GEN2_VAL
- RG_CKRSEL
- RG_CLKSQ_EN_AUD_BIT
- RG_CLKSQ_EN_MASK
- RG_CLKSQ_EN_MASK_SFT
- RG_CLKSQ_EN_SFT
- RG_CLKSQ_EN_VOW_MASK
- RG_CLKSQ_EN_VOW_MASK_SFT
- RG_CLKSQ_EN_VOW_SFT
- RG_CLKSQ_IN_SEL_TEST_MASK
- RG_CLKSQ_IN_SEL_TEST_MASK_SFT
- RG_CLKSQ_IN_SEL_TEST_SFT
- RG_CMSTBENH_MASK
- RG_CMSTBENH_MASK_SFT
- RG_CMSTBENH_SFT
- RG_CM_REFGENSEL_MASK
- RG_CM_REFGENSEL_MASK_SFT
- RG_CM_REFGENSEL_SFT
- RG_CSMA_BE
- RG_CSMA_SEED_0
- RG_CSMA_SEED_1
- RG_DACQUIET_EN
- RG_DCCVCMBUFLPMODSEL_MASK
- RG_DCCVCMBUFLPMODSEL_MASK_SFT
- RG_DCCVCMBUFLPMODSEL_SFT
- RG_DCCVCMBUFLPSWEN_MASK
- RG_DCCVCMBUFLPSWEN_MASK_SFT
- RG_DCCVCMBUFLPSWEN_SFT
- RG_DIVCKS_CHG_MASK
- RG_DIVCKS_CHG_MASK_SFT
- RG_DIVCKS_CHG_SFT
- RG_DIVCKS_ON_MASK
- RG_DIVCKS_ON_MASK_SFT
- RG_DIVCKS_ON_SFT
- RG_DIVCKS_PRG_MASK
- RG_DIVCKS_PRG_MASK_SFT
- RG_DIVCKS_PRG_SFT
- RG_DIVCKS_PWD_NCP_MASK
- RG_DIVCKS_PWD_NCP_MASK_SFT
- RG_DIVCKS_PWD_NCP_SFT
- RG_DIVCKS_PWD_NCP_ST_SEL_MASK
- RG_DIVCKS_PWD_NCP_ST_SEL_MASK_SFT
- RG_DIVCKS_PWD_NCP_ST_SEL_SFT
- RG_DL_2_SRC_ON_TMP_CTL_PRE_BIT
- RG_DL_SINE_ON_MASK
- RG_DL_SINE_ON_SFT
- RG_DMICHPCLKEN_MASK
- RG_DMICHPCLKEN_MASK_SFT
- RG_DMICHPCLKEN_SFT
- RG_DMICMONEN_MASK
- RG_DMICMONEN_MASK_SFT
- RG_DMICMONEN_SFT
- RG_DMICMONSEL_MASK
- RG_DMICMONSEL_MASK_SFT
- RG_DMICMONSEL_SFT
- RG_DSI_BCLK_SEL
- RG_DSI_BG_CKEN
- RG_DSI_BG_CORE_EN
- RG_DSI_BG_DIV
- RG_DSI_BG_FAST_CHARGE
- RG_DSI_BG_R1_TRIM
- RG_DSI_BG_R2_TRIM
- RG_DSI_CKG_LDOOUT_EN
- RG_DSI_DEBUG_INPUT_EN
- RG_DSI_DSICLK_FREQ_SEL
- RG_DSI_LDOCORE_EN
- RG_DSI_LD_IDX_SEL
- RG_DSI_LNT_AIO_SEL
- RG_DSI_LNT_HS_BIAS_EN
- RG_DSI_LNT_IMP_CAL_CODE
- RG_DSI_LNT_IMP_CAL_EN
- RG_DSI_LNT_INTR_EN
- RG_DSI_LNT_TESTMODE_EN
- RG_DSI_LNTx_CKLANE_EN
- RG_DSI_LNTx_LDOOUT_EN
- RG_DSI_LNTx_LPCD_IMINUS
- RG_DSI_LNTx_LPCD_IPLUS
- RG_DSI_LNTx_LPTX_IMINUS
- RG_DSI_LNTx_LPTX_IPLUS1
- RG_DSI_LNTx_LPTX_IPLUS2
- RG_DSI_LNTx_RT_CODE
- RG_DSI_LPTX_CLMP_EN
- RG_DSI_MPPLL_DIV_MSK
- RG_DSI_MPPLL_MONREF_EN
- RG_DSI_MPPLL_MONVC_EN
- RG_DSI_MPPLL_PLL_EN
- RG_DSI_MPPLL_POSDIV
- RG_DSI_MPPLL_PREDIV
- RG_DSI_MPPLL_PRESERVE
- RG_DSI_MPPLL_SDM_FRA_EN
- RG_DSI_MPPLL_SDM_ISO_EN
- RG_DSI_MPPLL_SDM_PWR_ACK
- RG_DSI_MPPLL_SDM_PWR_ON
- RG_DSI_MPPLL_SDM_SSC_EN
- RG_DSI_MPPLL_SDM_SSC_PH_INIT
- RG_DSI_MPPLL_SDM_SSC_PRD
- RG_DSI_MPPLL_TXDIV0
- RG_DSI_MPPLL_TXDIV1
- RG_DSI_MPPLL_VOD_EN
- RG_DSI_PAD_TIE_LOW_EN
- RG_DSI_PHYCLK_SEL
- RG_DSI_PRESERVE
- RG_DSI_V02_SEL
- RG_DSI_V032_SEL
- RG_DSI_V04_SEL
- RG_DSI_V072_SEL
- RG_DSI_V10_SEL
- RG_DSI_V12_SEL
- RG_DSI_VOUT_MSK
- RG_EEEPRG_EN
- RG_EINTCOMPVTH_MASK
- RG_EINTCOMPVTH_MASK_SFT
- RG_EINTCOMPVTH_SFT
- RG_EINTCONFIGACCDET_MASK
- RG_EINTCONFIGACCDET_MASK_SFT
- RG_EINTCONFIGACCDET_SFT
- RG_EINTHIRENB_MASK
- RG_EINTHIRENB_MASK_SFT
- RG_EINTHIRENB_SFT
- RG_EQ_DLEQ_LFI_GEN1_MSK
- RG_EQ_DLEQ_LFI_GEN1_VAL
- RG_FLR_BYPASS_MASK
- RG_FLR_BYPASS_MASK_SFT
- RG_FLR_BYPASS_SFT
- RG_FLR_RATIO_MASK
- RG_FLR_RATIO_MASK_SFT
- RG_FLR_RATIO_SFT
- RG_FTN_CTRL
- RG_GSWPLL_BP
- RG_GSWPLL_BR
- RG_GSWPLL_EN_PRE
- RG_GSWPLL_FBKDIV_200M
- RG_GSWPLL_FBKDIV_500M
- RG_GSWPLL_FBKSEL
- RG_GSWPLL_POSDIV_200M
- RG_GSWPLL_POSDIV_500M
- RG_GSWPLL_PREDIV
- RG_HCLDO_EN_VA18_MASK
- RG_HCLDO_EN_VA18_MASK_SFT
- RG_HCLDO_EN_VA18_SFT
- RG_HCLDO_PDDIS_EN_VA18_MASK
- RG_HCLDO_PDDIS_EN_VA18_MASK_SFT
- RG_HCLDO_PDDIS_EN_VA18_SFT
- RG_HCLDO_REMOTE_SENSE_VA18_MASK
- RG_HCLDO_REMOTE_SENSE_VA18_MASK_SFT
- RG_HCLDO_REMOTE_SENSE_VA18_SFT
- RG_HCLDO_VOSEL_VA18_MASK
- RG_HCLDO_VOSEL_VA18_MASK_SFT
- RG_HCLDO_VOSEL_VA18_SFT
- RG_HDMITX_CHLCK_TST
- RG_HDMITX_CHLDC_TST
- RG_HDMITX_DRV_EN
- RG_HDMITX_DRV_IBIAS
- RG_HDMITX_DRV_IBIAS_CLK
- RG_HDMITX_DRV_IBIAS_D0
- RG_HDMITX_DRV_IBIAS_D1
- RG_HDMITX_DRV_IBIAS_D2
- RG_HDMITX_DRV_IBIAS_MASK
- RG_HDMITX_DRV_IMP
- RG_HDMITX_DRV_IMP_CLK
- RG_HDMITX_DRV_IMP_D0
- RG_HDMITX_DRV_IMP_D1
- RG_HDMITX_DRV_IMP_D2
- RG_HDMITX_DRV_IMP_EN
- RG_HDMITX_DRV_IMP_MASK
- RG_HDMITX_EN_DRV
- RG_HDMITX_EN_DRV_MASK
- RG_HDMITX_EN_IMP
- RG_HDMITX_EN_IMP_MASK
- RG_HDMITX_EN_MBIAS
- RG_HDMITX_EN_PRED
- RG_HDMITX_EN_PRED_MASK
- RG_HDMITX_EN_SER
- RG_HDMITX_EN_SER_MASK
- RG_HDMITX_EN_SLDO
- RG_HDMITX_EN_SLDO_MASK
- RG_HDMITX_EN_TX_CKLDO
- RG_HDMITX_EN_TX_POSDIV
- RG_HDMITX_MBIAS_LPF_EN
- RG_HDMITX_MHLCK_DRV_IBIAS
- RG_HDMITX_MHLCK_EN
- RG_HDMITX_MHLCK_FORCE
- RG_HDMITX_MHLCK_PPIX_EN
- RG_HDMITX_PLL_AUTOK_EN
- RG_HDMITX_PLL_AUTOK_KF
- RG_HDMITX_PLL_AUTOK_KS
- RG_HDMITX_PLL_AUTOK_LOAD
- RG_HDMITX_PLL_BAND
- RG_HDMITX_PLL_BC
- RG_HDMITX_PLL_BIAS_EN
- RG_HDMITX_PLL_BIAS_LPF_EN
- RG_HDMITX_PLL_BP
- RG_HDMITX_PLL_BR
- RG_HDMITX_PLL_DIVEN
- RG_HDMITX_PLL_EN
- RG_HDMITX_PLL_FBKDIV
- RG_HDMITX_PLL_FBKSEL
- RG_HDMITX_PLL_IC
- RG_HDMITX_PLL_IR
- RG_HDMITX_PLL_LVROD_EN
- RG_HDMITX_PLL_MONCK_EN
- RG_HDMITX_PLL_MONREF_EN
- RG_HDMITX_PLL_MONVC_EN
- RG_HDMITX_PLL_POSDIV
- RG_HDMITX_PLL_PREDIV
- RG_HDMITX_PLL_REF_SEL
- RG_HDMITX_PLL_RST_DLY
- RG_HDMITX_PLL_TST_CK_EN
- RG_HDMITX_PLL_TST_EN
- RG_HDMITX_PLL_TST_SEL
- RG_HDMITX_PLL_TXDIV
- RG_HDMITX_PLL_TXDIV_EN
- RG_HDMITX_PRD_EN
- RG_HDMITX_PRD_IBIAS_CLK
- RG_HDMITX_PRD_IBIAS_D0
- RG_HDMITX_PRD_IBIAS_D1
- RG_HDMITX_PRD_IBIAS_D2
- RG_HDMITX_PRD_IMP_EN
- RG_HDMITX_PRED_IBIAS
- RG_HDMITX_PRED_IBIAS_MASK
- RG_HDMITX_PRED_IMP
- RG_HDMITX_RESERVE
- RG_HDMITX_RESERVE_MASK
- RG_HDMITX_SER_5T1_BIST_EN
- RG_HDMITX_SER_BIST_TOG
- RG_HDMITX_SER_CLKDIG_INV
- RG_HDMITX_SER_DIN
- RG_HDMITX_SER_DIN_SEL
- RG_HDMITX_SER_DIN_TOG
- RG_HDMITX_SER_EN
- RG_HDMITX_TX_POSDIV
- RG_HDMITX_TX_POSDIV_MASK
- RG_HPF_ON_MASK
- RG_HPF_ON_MASK_SFT
- RG_HPF_ON_SFT
- RG_HPINPUTRESET0_VAUDP15_MASK
- RG_HPINPUTRESET0_VAUDP15_MASK_SFT
- RG_HPINPUTRESET0_VAUDP15_SFT
- RG_HPINPUTSTBENH_VAUDP15_MASK
- RG_HPINPUTSTBENH_VAUDP15_MASK_SFT
- RG_HPINPUTSTBENH_VAUDP15_SFT
- RG_HPLAUXFBRSW_EN_VAUDP15_MASK
- RG_HPLAUXFBRSW_EN_VAUDP15_MASK_SFT
- RG_HPLAUXFBRSW_EN_VAUDP15_SFT
- RG_HPLOUTPUTSTBENH_VAUDP15_MASK
- RG_HPLOUTPUTSTBENH_VAUDP15_MASK_SFT
- RG_HPLOUTPUTSTBENH_VAUDP15_SFT
- RG_HPLOUTSTGCTRL_VAUDP15_MASK
- RG_HPLOUTSTGCTRL_VAUDP15_MASK_SFT
- RG_HPLOUTSTGCTRL_VAUDP15_SFT
- RG_HPLSHORT2HPLAUX_EN_VAUDP15_MASK
- RG_HPLSHORT2HPLAUX_EN_VAUDP15_MASK_SFT
- RG_HPLSHORT2HPLAUX_EN_VAUDP15_SFT
- RG_HPOUTPUTRESET0_VAUDP15_MASK
- RG_HPOUTPUTRESET0_VAUDP15_MASK_SFT
- RG_HPOUTPUTRESET0_VAUDP15_SFT
- RG_HPPSHORT2VCM_VAUDP15_MASK
- RG_HPPSHORT2VCM_VAUDP15_MASK_SFT
- RG_HPPSHORT2VCM_VAUDP15_SFT
- RG_HPRAUXFBRSW_EN_VAUDP15_MASK
- RG_HPRAUXFBRSW_EN_VAUDP15_MASK_SFT
- RG_HPRAUXFBRSW_EN_VAUDP15_SFT
- RG_HPROUTPUTSTBENH_VAUDP15_MASK
- RG_HPROUTPUTSTBENH_VAUDP15_MASK_SFT
- RG_HPROUTPUTSTBENH_VAUDP15_SFT
- RG_HPROUTSTGCTRL_VAUDP15_MASK
- RG_HPROUTSTGCTRL_VAUDP15_MASK_SFT
- RG_HPROUTSTGCTRL_VAUDP15_SFT
- RG_HPRSHORT2HPRAUX_EN_VAUDP15_MASK
- RG_HPRSHORT2HPRAUX_EN_VAUDP15_MASK_SFT
- RG_HPRSHORT2HPRAUX_EN_VAUDP15_SFT
- RG_HSINPUTRESET0_VAUDP15_MASK
- RG_HSINPUTRESET0_VAUDP15_MASK_SFT
- RG_HSINPUTRESET0_VAUDP15_SFT
- RG_HSINPUTSTBENH_VAUDP15_MASK
- RG_HSINPUTSTBENH_VAUDP15_MASK_SFT
- RG_HSINPUTSTBENH_VAUDP15_SFT
- RG_HSOUTPUTRESET0_VAUDP15_MASK
- RG_HSOUTPUTRESET0_VAUDP15_MASK_SFT
- RG_HSOUTPUTRESET0_VAUDP15_SFT
- RG_HSOUTPUTSTBENH_VAUDP15_MASK
- RG_HSOUTPUTSTBENH_VAUDP15_MASK_SFT
- RG_HSOUTPUTSTBENH_VAUDP15_SFT
- RG_HSOUTPUTSTBENH_VAUDP32_BIT
- RG_HSOUT_SHORTVCM_VAUDP15_MASK
- RG_HSOUT_SHORTVCM_VAUDP15_MASK_SFT
- RG_HSOUT_SHORTVCM_VAUDP15_SFT
- RG_HTPLL_AUTOK_EN
- RG_HTPLL_BC
- RG_HTPLL_BC_MASK
- RG_HTPLL_BP
- RG_HTPLL_BP_MASK
- RG_HTPLL_BR
- RG_HTPLL_BR_MASK
- RG_HTPLL_DIVEN
- RG_HTPLL_DIVEN_MASK
- RG_HTPLL_EN
- RG_HTPLL_FBKDIV
- RG_HTPLL_FBKDIV_MASK
- RG_HTPLL_FBKSEL
- RG_HTPLL_FBKSEL_MASK
- RG_HTPLL_IC
- RG_HTPLL_IC_MASK
- RG_HTPLL_IR
- RG_HTPLL_IR_MASK
- RG_HTPLL_POSDIV
- RG_HTPLL_POSDIV_MASK
- RG_HTPLL_PREDIV
- RG_HTPLL_PREDIV_MASK
- RG_HTPLL_RLH_EN
- RG_IDRV_0DB_GEN1_MSK
- RG_IDRV_0DB_GEN1_VAL
- RG_IEEE_ADDR_0
- RG_IEEE_ADDR_1
- RG_IEEE_ADDR_2
- RG_IEEE_ADDR_3
- RG_IEEE_ADDR_4
- RG_IEEE_ADDR_5
- RG_IEEE_ADDR_6
- RG_IEEE_ADDR_7
- RG_INT_EN_ACCDET_EINT0_MASK
- RG_INT_EN_ACCDET_EINT0_MASK_SFT
- RG_INT_EN_ACCDET_EINT0_SFT
- RG_INT_EN_ACCDET_EINT1_MASK
- RG_INT_EN_ACCDET_EINT1_MASK_SFT
- RG_INT_EN_ACCDET_EINT1_SFT
- RG_INT_EN_ACCDET_MASK
- RG_INT_EN_ACCDET_MASK_SFT
- RG_INT_EN_ACCDET_SFT
- RG_INT_EN_AUDIO_MASK
- RG_INT_EN_AUDIO_MASK_SFT
- RG_INT_EN_AUDIO_SFT
- RG_INT_MASK_ACCDET_EINT0_MASK
- RG_INT_MASK_ACCDET_EINT0_MASK_SFT
- RG_INT_MASK_ACCDET_EINT0_SFT
- RG_INT_MASK_ACCDET_EINT1_MASK
- RG_INT_MASK_ACCDET_EINT1_MASK_SFT
- RG_INT_MASK_ACCDET_EINT1_SFT
- RG_INT_MASK_ACCDET_MASK
- RG_INT_MASK_ACCDET_MASK_SFT
- RG_INT_MASK_ACCDET_SFT
- RG_INT_MASK_AUDIO_MASK
- RG_INT_MASK_AUDIO_MASK_SFT
- RG_INT_MASK_AUDIO_SFT
- RG_INT_RAW_STATUS_ACCDET_EINT0_MASK
- RG_INT_RAW_STATUS_ACCDET_EINT0_MASK_SFT
- RG_INT_RAW_STATUS_ACCDET_EINT0_SFT
- RG_INT_RAW_STATUS_ACCDET_EINT1_MASK
- RG_INT_RAW_STATUS_ACCDET_EINT1_MASK_SFT
- RG_INT_RAW_STATUS_ACCDET_EINT1_SFT
- RG_INT_RAW_STATUS_ACCDET_MASK
- RG_INT_RAW_STATUS_ACCDET_MASK_SFT
- RG_INT_RAW_STATUS_ACCDET_SFT
- RG_INT_RAW_STATUS_AUDIO_MASK
- RG_INT_RAW_STATUS_AUDIO_MASK_SFT
- RG_INT_RAW_STATUS_AUDIO_SFT
- RG_INT_STATUS_ACCDET_EINT0_MASK
- RG_INT_STATUS_ACCDET_EINT0_MASK_SFT
- RG_INT_STATUS_ACCDET_EINT0_SFT
- RG_INT_STATUS_ACCDET_EINT1_MASK
- RG_INT_STATUS_ACCDET_EINT1_MASK_SFT
- RG_INT_STATUS_ACCDET_EINT1_SFT
- RG_INT_STATUS_ACCDET_MASK
- RG_INT_STATUS_ACCDET_MASK_SFT
- RG_INT_STATUS_ACCDET_SFT
- RG_INT_STATUS_AUDIO_MASK
- RG_INT_STATUS_AUDIO_MASK_SFT
- RG_INT_STATUS_AUDIO_SFT
- RG_IRQ_MASK
- RG_IRQ_STATUS
- RG_LCCDS_C
- RG_LCDDS_ISO_EN
- RG_LCDDS_PCW_NCPO0
- RG_LCDDS_PCW_NCPO1
- RG_LCDDS_PCW_NCPO_CHG
- RG_LCDDS_PWDB
- RG_LCDDS_SSC_DELTA
- RG_LCDDS_SSC_DELTA1
- RG_LCLDO_DEC_EN_VA32_BIT
- RG_LCLDO_DEC_REMOTE_SENSE_VA18_BIT
- RG_LCLDO_ENC_EN_VA28_MASK
- RG_LCLDO_ENC_EN_VA28_MASK_SFT
- RG_LCLDO_ENC_EN_VA28_SFT
- RG_LCLDO_ENC_PDDIS_EN_VA28_MASK
- RG_LCLDO_ENC_PDDIS_EN_VA28_MASK_SFT
- RG_LCLDO_ENC_PDDIS_EN_VA28_SFT
- RG_LCLDO_ENC_REMOTE_SENSE_VA28_MASK
- RG_LCLDO_ENC_REMOTE_SENSE_VA28_MASK_SFT
- RG_LCLDO_ENC_REMOTE_SENSE_VA28_SFT
- RG_LCLDO_EN_VA18_MASK
- RG_LCLDO_EN_VA18_MASK_SFT
- RG_LCLDO_EN_VA18_SFT
- RG_LCLDO_PDDIS_EN_VA18_MASK
- RG_LCLDO_PDDIS_EN_VA18_MASK_SFT
- RG_LCLDO_PDDIS_EN_VA18_SFT
- RG_LCLDO_REMOTE_SENSE_VA18_MASK
- RG_LCLDO_REMOTE_SENSE_VA18_MASK_SFT
- RG_LCLDO_REMOTE_SENSE_VA18_SFT
- RG_LCLDO_VOSEL_VA18_MASK
- RG_LCLDO_VOSEL_VA18_MASK_SFT
- RG_LCLDO_VOSEL_VA18_SFT
- RG_LDVQUIET_EN
- RG_LFS_SEL
- RG_LOCK_CNT_SEL_MSK
- RG_LOCK_CNT_SEL_VAL
- RG_LOINPUTRESET0_VAUDP15_MASK
- RG_LOINPUTRESET0_VAUDP15_MASK_SFT
- RG_LOINPUTRESET0_VAUDP15_SFT
- RG_LOINPUTSTBENH_VAUDP15_MASK
- RG_LOINPUTSTBENH_VAUDP15_MASK_SFT
- RG_LOINPUTSTBENH_VAUDP15_SFT
- RG_LOOUTPUTRESET0_VAUDP15_MASK
- RG_LOOUTPUTRESET0_VAUDP15_MASK_SFT
- RG_LOOUTPUTRESET0_VAUDP15_SFT
- RG_LOOUTPUTSTBENH_VAUDP15_MASK
- RG_LOOUTPUTSTBENH_VAUDP15_MASK_SFT
- RG_LOOUTPUTSTBENH_VAUDP15_SFT
- RG_LOOUTPUTSTBENH_VAUDP32_BIT
- RG_LOOUT_SHORTVCM_VAUDP15_MASK
- RG_LOOUT_SHORTVCM_VAUDP15_MASK_SFT
- RG_LOOUT_SHORTVCM_VAUDP15_SFT
- RG_LPIHYS_NUM
- RG_MAN_ID_0
- RG_MAN_ID_1
- RG_MATCLR_EN
- RG_MTEST_CURRENT_MASK
- RG_MTEST_CURRENT_MASK_SFT
- RG_MTEST_CURRENT_SFT
- RG_MTEST_EN_MASK
- RG_MTEST_EN_MASK_SFT
- RG_MTEST_EN_SFT
- RG_MTEST_SEL_MASK
- RG_MTEST_SEL_MASK_SFT
- RG_MTEST_SEL_SFT
- RG_MTKAIF_BYPASS_SRC_MODE_MASK
- RG_MTKAIF_BYPASS_SRC_MODE_MASK_SFT
- RG_MTKAIF_BYPASS_SRC_MODE_SFT
- RG_MTKAIF_BYPASS_SRC_TEST_MASK
- RG_MTKAIF_BYPASS_SRC_TEST_MASK_SFT
- RG_MTKAIF_BYPASS_SRC_TEST_SFT
- RG_MTKAIF_HPF_BYPASS_MASK
- RG_MTKAIF_HPF_BYPASS_MASK_SFT
- RG_MTKAIF_HPF_BYPASS_SFT
- RG_MTKAIF_LOOPBACK_TEST1_MASK
- RG_MTKAIF_LOOPBACK_TEST1_MASK_SFT
- RG_MTKAIF_LOOPBACK_TEST1_SFT
- RG_MTKAIF_LOOPBACK_TEST2_MASK
- RG_MTKAIF_LOOPBACK_TEST2_MASK_SFT
- RG_MTKAIF_LOOPBACK_TEST2_SFT
- RG_MTKAIF_PMIC_TXIF_8TO5_MASK
- RG_MTKAIF_PMIC_TXIF_8TO5_MASK_SFT
- RG_MTKAIF_PMIC_TXIF_8TO5_SFT
- RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK
- RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK_SFT
- RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_SFT
- RG_MTKAIF_RXIF_CLKINV_MASK
- RG_MTKAIF_RXIF_CLKINV_MASK_SFT
- RG_MTKAIF_RXIF_CLKINV_SFT
- RG_MTKAIF_RXIF_DATA_BIT_MASK
- RG_MTKAIF_RXIF_DATA_BIT_MASK_SFT
- RG_MTKAIF_RXIF_DATA_BIT_SFT
- RG_MTKAIF_RXIF_DATA_MODE_MASK
- RG_MTKAIF_RXIF_DATA_MODE_MASK_SFT
- RG_MTKAIF_RXIF_DATA_MODE_SFT
- RG_MTKAIF_RXIF_DETECT_ON_MASK
- RG_MTKAIF_RXIF_DETECT_ON_MASK_SFT
- RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK
- RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT
- RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_SFT
- RG_MTKAIF_RXIF_DETECT_ON_SFT
- RG_MTKAIF_RXIF_FIFO_INTEN_MASK
- RG_MTKAIF_RXIF_FIFO_INTEN_MASK_SFT
- RG_MTKAIF_RXIF_FIFO_INTEN_SFT
- RG_MTKAIF_RXIF_FIFO_RSP_MASK
- RG_MTKAIF_RXIF_FIFO_RSP_MASK_SFT
- RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK
- RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK_SFT
- RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_SFT
- RG_MTKAIF_RXIF_FIFO_RSP_SFT
- RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_MASK
- RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_MASK_SFT
- RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_SFT
- RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_MASK
- RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_MASK_SFT
- RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_SFT
- RG_MTKAIF_RXIF_PROTOCOL2_MASK
- RG_MTKAIF_RXIF_PROTOCOL2_MASK_SFT
- RG_MTKAIF_RXIF_PROTOCOL2_SFT
- RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_MASK
- RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_MASK_SFT
- RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_SFT
- RG_MTKAIF_RXIF_SYNC_CNT_TABLE_MASK
- RG_MTKAIF_RXIF_SYNC_CNT_TABLE_MASK_SFT
- RG_MTKAIF_RXIF_SYNC_CNT_TABLE_SFT
- RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_MASK
- RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_MASK_SFT
- RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_SFT
- RG_MTKAIF_RXIF_VOICE_MODE_MASK
- RG_MTKAIF_RXIF_VOICE_MODE_MASK_SFT
- RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_MASK
- RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_MASK_SFT
- RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_SFT
- RG_MTKAIF_RXIF_VOICE_MODE_SFT
- RG_MTKAIF_SYNC_WORD1_MASK
- RG_MTKAIF_SYNC_WORD1_MASK_SFT
- RG_MTKAIF_SYNC_WORD1_SFT
- RG_MTKAIF_SYNC_WORD2_MASK
- RG_MTKAIF_SYNC_WORD2_MASK_SFT
- RG_MTKAIF_SYNC_WORD2_SFT
- RG_MTKAIF_TXIF_PROTOCOL2_MASK
- RG_MTKAIF_TXIF_PROTOCOL2_MASK_SFT
- RG_MTKAIF_TXIF_PROTOCOL2_SFT
- RG_NCP_ON_BIT
- RG_NVREG_EN_VAUDP15_MASK
- RG_NVREG_EN_VAUDP15_MASK_SFT
- RG_NVREG_EN_VAUDP15_SFT
- RG_NVREG_EN_VAUDP32_BIT
- RG_NVREG_PULL0V_VAUDP15_MASK
- RG_NVREG_PULL0V_VAUDP15_MASK_SFT
- RG_NVREG_PULL0V_VAUDP15_SFT
- RG_P0_TO_P1_WIDTH
- RG_PAD_AUD_CLK_MISO_CK_PDN_MASK
- RG_PAD_AUD_CLK_MISO_CK_PDN_MASK_SFT
- RG_PAD_AUD_CLK_MISO_CK_PDN_SFT
- RG_PAN_ID_0
- RG_PAN_ID_1
- RG_PART_NUM
- RG_PE1_FRC_H_XTAL_REG
- RG_PE1_FRC_H_XTAL_TYPE
- RG_PE1_FRC_MSTCKDIV
- RG_PE1_FRC_PHY_EN
- RG_PE1_FRC_PHY_REG
- RG_PE1_H_LCDDS_PCW
- RG_PE1_H_LCDDS_PCW_VAL
- RG_PE1_H_LCDDS_REG
- RG_PE1_H_LCDDS_SSC_DELTA
- RG_PE1_H_LCDDS_SSC_DELTA1
- RG_PE1_H_LCDDS_SSC_DELTA1_VAL
- RG_PE1_H_LCDDS_SSC_DELTA_REG
- RG_PE1_H_LCDDS_SSC_DELTA_VAL
- RG_PE1_H_LCDDS_SSC_PRD
- RG_PE1_H_LCDDS_SSC_PRD_REG
- RG_PE1_H_LCDDS_SSC_PRD_VAL
- RG_PE1_H_PLL_BC
- RG_PE1_H_PLL_BC_VAL
- RG_PE1_H_PLL_BP
- RG_PE1_H_PLL_BP_VAL
- RG_PE1_H_PLL_BR
- RG_PE1_H_PLL_BR_REG
- RG_PE1_H_PLL_BR_VAL
- RG_PE1_H_PLL_FBKSEL
- RG_PE1_H_PLL_FBKSEL_REG
- RG_PE1_H_PLL_FBKSEL_VAL
- RG_PE1_H_PLL_IC
- RG_PE1_H_PLL_IC_VAL
- RG_PE1_H_PLL_IR
- RG_PE1_H_PLL_IR_VAL
- RG_PE1_H_PLL_PREDIV
- RG_PE1_H_PLL_PREDIV_VAL
- RG_PE1_H_PLL_REG
- RG_PE1_H_XTAL_TYPE
- RG_PE1_H_XTAL_TYPE_VAL
- RG_PE1_LCDDS_CLK_PH_INV
- RG_PE1_LCDDS_CLK_PH_INV_REG
- RG_PE1_MSTCKDIV
- RG_PE1_MSTCKDIV_REG
- RG_PE1_MSTCKDIV_VAL
- RG_PE1_PHY_EN
- RG_PE1_PIPE_CMD_FRC
- RG_PE1_PIPE_REG
- RG_PE1_PIPE_RST
- RG_PE1_PLL_DIVEN
- RG_PE1_PLL_DIVEN_VAL
- RG_PERIODIC_CNT_CLR_MASK
- RG_PERIODIC_CNT_CLR_MASK_SFT
- RG_PERIODIC_CNT_CLR_SFT
- RG_PERIODIC_CNT_PAUSE_MASK
- RG_PERIODIC_CNT_PAUSE_MASK_SFT
- RG_PERIODIC_CNT_PAUSE_SFT
- RG_PERIODIC_CNT_PERIOD_MASK
- RG_PERIODIC_CNT_PERIOD_MASK_SFT
- RG_PERIODIC_CNT_PERIOD_SFT
- RG_PERIODIC_CNT_SET_MASK
- RG_PERIODIC_CNT_SET_MASK_SFT
- RG_PERIODIC_CNT_SET_SFT
- RG_PERIODIC_CNT_SET_VALUE_MASK
- RG_PERIODIC_CNT_SET_VALUE_MASK_SFT
- RG_PERIODIC_CNT_SET_VALUE_SFT
- RG_PERIODIC_EN_MASK
- RG_PERIODIC_EN_MASK_SFT
- RG_PERIODIC_EN_SFT
- RG_PGABODYSW_MASK
- RG_PGABODYSW_MASK_SFT
- RG_PGABODYSW_SFT
- RG_PHY_CC_CCA
- RG_PHY_ED_LEVEL
- RG_PHY_RSSI
- RG_PHY_SPEED_1_25G
- RG_PHY_SPEED_3_125G
- RG_PHY_SPEED_MASK
- RG_PHY_TX_PWR
- RG_PLL_CF
- RG_PLL_DCU
- RG_REQ_SIZE
- RG_RESP_SIZE
- RG_RSTB_DECODER_VA28_MASK
- RG_RSTB_DECODER_VA28_MASK_SFT
- RG_RSTB_DECODER_VA28_SFT
- RG_RSTB_DECODER_VA32_BIT
- RG_RSTB_ENCODER_VA28_MASK
- RG_RSTB_ENCODER_VA28_MASK_SFT
- RG_RSTB_ENCODER_VA28_SFT
- RG_RXLPI_MSK_HFDUP
- RG_RX_CTRL
- RG_RX_SYN
- RG_SEL_DECODER_96K_VA28_MASK
- RG_SEL_DECODER_96K_VA28_MASK_SFT
- RG_SEL_DECODER_96K_VA28_SFT
- RG_SEL_DELAY_VCORE_MASK
- RG_SEL_DELAY_VCORE_MASK_SFT
- RG_SEL_DELAY_VCORE_SFT
- RG_SEL_ENCODER_96K_VA28_MASK
- RG_SEL_ENCODER_96K_VA28_MASK_SFT
- RG_SEL_ENCODER_96K_VA28_SFT
- RG_SFD_VALUE
- RG_SHORT_ADDR_0
- RG_SHORT_ADDR_1
- RG_SNRDET_HPF_BYPASS_MASK
- RG_SNRDET_HPF_BYPASS_MASK_SFT
- RG_SNRDET_HPF_BYPASS_SFT
- RG_SWBUFMODSEL_MASK
- RG_SWBUFMODSEL_MASK_SFT
- RG_SWBUFMODSEL_SFT
- RG_SWBUFSWEN_MASK
- RG_SWBUFSWEN_MASK_SFT
- RG_SWBUFSWEN_SFT
- RG_SYSPLL_BIAS_EN
- RG_SYSPLL_BIAS_LPF_EN
- RG_SYSPLL_DDSFBK_EN
- RG_SYSPLL_EN_NORMAL
- RG_SYSPLL_FBKSEL
- RG_SYSPLL_LF
- RG_SYSPLL_LVROD_EN
- RG_SYSPLL_POSDIV
- RG_SYSPLL_PREDIV
- RG_SYSPLL_RST_DLY
- RG_SYSPLL_VODEN
- RG_T2_MAX_MSK
- RG_T2_MAX_VAL
- RG_T2_MIN_MSK
- RG_T2_MIN_VAL
- RG_TG_MAX_MSK
- RG_TG_MAX_VAL
- RG_TG_MIN_MSK
- RG_TG_MIN_VAL
- RG_TRX_CTRL_0
- RG_TRX_CTRL_1
- RG_TRX_CTRL_2
- RG_TRX_STATE
- RG_TRX_STATUS
- RG_TXLPI_MSK_HFDUP
- RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK
- RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT
- RG_UL_ASYNC_FIFO_SOFT_RST_EN_SFT
- RG_UL_ASYNC_FIFO_SOFT_RST_MASK
- RG_UL_ASYNC_FIFO_SOFT_RST_MASK_SFT
- RG_UL_ASYNC_FIFO_SOFT_RST_SFT
- RG_UL_SINE_ON_MASK
- RG_UL_SINE_ON_SFT
- RG_VA18_EN
- RG_VA18_ON_CTRL
- RG_VA28REFGEN_EN_VA28_MASK
- RG_VA28REFGEN_EN_VA28_MASK_SFT
- RG_VA28REFGEN_EN_VA28_SFT
- RG_VA33REFGEN_EN_VA18_MASK
- RG_VA33REFGEN_EN_VA18_MASK_SFT
- RG_VA33REFGEN_EN_VA18_SFT
- RG_VERSION_NUM
- RG_VOW13M_CK_PDN_MASK
- RG_VOW13M_CK_PDN_MASK_SFT
- RG_VOW13M_CK_PDN_SFT
- RG_VOW13M_CK_TSTSEL_MASK
- RG_VOW13M_CK_TSTSEL_MASK_SFT
- RG_VOW13M_CK_TSTSEL_SFT
- RG_VOW13M_CK_TST_DIS_MASK
- RG_VOW13M_CK_TST_DIS_MASK_SFT
- RG_VOW13M_CK_TST_DIS_SFT
- RG_VOW32K_CK_PDN_MASK
- RG_VOW32K_CK_PDN_MASK_SFT
- RG_VOW32K_CK_PDN_SFT
- RG_VOW_POSDIV_MASK
- RG_VOW_POSDIV_MASK_SFT
- RG_VOW_POSDIV_SFT
- RG_VREG_CTRL
- RG_VUSB33_EN
- RG_VUSB33_ON_CTRL
- RG_WINDOW_SIZE_SEL_MASK
- RG_WINDOW_SIZE_SEL_MASK_SFT
- RG_WINDOW_SIZE_SEL_SFT
- RG_XAH_CTRL_0
- RG_XAH_CTRL_1
- RG_XOSC_CTRL
- RG_XO_AUDIO_EN_M_SFT
- RG_XO_VOW_EN_SFT
- RG_XTP_GLB_BIAS_INTR_CTRL
- RG_XTP_GLB_BIAS_INTR_CTRL_VAL
- RG_XTP_LN0_RX_IMPSEL
- RG_XTP_LN0_RX_IMPSEL_VAL
- RG_XTP_LN0_TX_IMPSEL
- RG_XTP_LN0_TX_IMPSEL_VAL
- RG_ZCD13M_CK_PDN_BIT
- RG_ZCD13M_CK_PDN_MASK
- RG_ZCD13M_CK_PDN_MASK_SFT
- RG_ZCD13M_CK_PDN_SFT
- RG_ZCD_RST_MASK
- RG_ZCD_RST_MASK_SFT
- RG_ZCD_RST_SFT
- RGen
- RHALL
- RHAT_CMD
- RHBA_BIOS_STATE
- RHBA_BIOS_VERSION
- RHBA_CMD
- RHBA_DRIVER_VERSION
- RHBA_FABRIC_WWNN
- RHBA_FIRMWARE_VERSION
- RHBA_HARDWARE_VERSION
- RHBA_MANUFACTURER
- RHBA_MAX_CT_PAYLOAD_LEN
- RHBA_MODEL
- RHBA_MODEL_DESCRIPTION
- RHBA_NODENAME
- RHBA_NUM_PORTS
- RHBA_OPTION_ROM_VERSION
- RHBA_OS_NAME_VERSION
- RHBA_RSP_SIZE
- RHBA_SERIAL_NUMBER
- RHBA_SYM_NODENAME
- RHBA_VENDOR_ID
- RHBA_VENDOR_INFO
- RHCR
- RHF_DC_ERR
- RHF_DC_INFO_MASK
- RHF_DC_INFO_SHIFT
- RHF_DC_INFO_SMASK
- RHF_DC_UNC_ERR
- RHF_ECC_ERR
- RHF_EGR_INDEX_MASK
- RHF_EGR_INDEX_SHIFT
- RHF_EGR_INDEX_SMASK
- RHF_EGR_OFFSET_MASK
- RHF_EGR_OFFSET_SHIFT
- RHF_EGR_OFFSET_SMASK
- RHF_ERROR_SMASK
- RHF_HARDWAY
- RHF_HDRQ_OFFSET_MASK
- RHF_HDRQ_OFFSET_SHIFT
- RHF_HDRQ_OFFSET_SMASK
- RHF_ICRC_ERR
- RHF_K_HDR_LEN_ERR
- RHF_LEN_ERR
- RHF_NONE
- RHF_NOTPOT
- RHF_PKT_LEN_MASK
- RHF_PKT_LEN_SHIFT
- RHF_PKT_LEN_SMASK
- RHF_RCV_CONTINUE
- RHF_RCV_DONE
- RHF_RCV_REPROCESS
- RHF_RCV_SEQ_MASK
- RHF_RCV_SEQ_SHIFT
- RHF_RCV_SEQ_SMASK
- RHF_RCV_TYPE_BYPASS
- RHF_RCV_TYPE_EAGER
- RHF_RCV_TYPE_ERROR
- RHF_RCV_TYPE_ERR_MASK
- RHF_RCV_TYPE_ERR_SHIFT
- RHF_RCV_TYPE_ERR_SMASK
- RHF_RCV_TYPE_EXPECTED
- RHF_RCV_TYPE_IB
- RHF_RCV_TYPE_INVALID5
- RHF_RCV_TYPE_INVALID6
- RHF_RCV_TYPE_INVALID7
- RHF_RCV_TYPE_MASK
- RHF_RCV_TYPE_SHIFT
- RHF_RCV_TYPE_SMASK
- RHF_RESERVED
- RHF_RTE_BYPASS_NO_ERR
- RHF_RTE_EAGER_NO_ERR
- RHF_RTE_ERROR_CONTEXT_ERR
- RHF_RTE_ERROR_KHDR_HCRC_ERR
- RHF_RTE_ERROR_KHDR_KVER_ERR
- RHF_RTE_ERROR_KHDR_MIN_LEN_ERR
- RHF_RTE_ERROR_KHDR_TID_ERR
- RHF_RTE_ERROR_NO_ERR
- RHF_RTE_ERROR_OP_CODE_ERR
- RHF_RTE_EXPECTED_FLOW_GEN_ERR
- RHF_RTE_EXPECTED_FLOW_SEQ_ERR
- RHF_RTE_IB_NO_ERR
- RHF_SGI_ONLY
- RHF_TID_ERR
- RHF_USE_EGR_BFR_MASK
- RHF_USE_EGR_BFR_SHIFT
- RHF_USE_EGR_BFR_SMASK
- RHGS_FREE
- RHGS_TAKEN
- RHIF_STATIC_BLOCK
- RHIF_STATIC_INFO
- RHINE_EVENT
- RHINE_EVENT_NAPI
- RHINE_EVENT_NAPI_RX
- RHINE_EVENT_NAPI_TX
- RHINE_EVENT_NAPI_TX_ERR
- RHINE_EVENT_SLOW
- RHINE_MSG_DEFAULT
- RHINE_PM_OPS
- RHOLD
- RHOLD_MAX
- RHOLD_SHIFT
- RHOLD_VAL
- RHRAR
- RHRCNT
- RHSSIPAR
- RHSSIREAD_8821AE
- RHST
- RHST_FULL_SPEED
- RHST_HIGH_SPEED
- RHST_LOW_SPEED
- RHT_ELASTICITY
- RHT_NULLS_MARKER
- RHT_PERM_READ
- RHT_PERM_RW
- RHT_PERM_WRITE
- RH_A_DT
- RH_A_NDP
- RH_A_NOCP
- RH_A_NPS
- RH_A_OCPM
- RH_A_POTPGT
- RH_A_PSM
- RH_B_DR
- RH_B_PPCM
- RH_CONFIG
- RH_HASH_MULT
- RH_HASH_SHIFT
- RH_HS_CRWE
- RH_HS_DRWE
- RH_HS_LPS
- RH_HS_LPSC
- RH_HS_OCI
- RH_HS_OCIC
- RH_OFS
- RH_PRTY
- RH_PS_CCS
- RH_PS_CSC
- RH_PS_LSDA
- RH_PS_OCIC
- RH_PS_PES
- RH_PS_PESC
- RH_PS_POCI
- RH_PS_PPS
- RH_PS_PRS
- RH_PS_PRSC
- RH_PS_PSS
- RH_PS_PSSC
- RI
- RI10
- RI16
- RI18
- RI7
- RI8
- RIC
- RIC0
- RIC0_BIT
- RIC0_FRE0
- RIC0_FRE1
- RIC0_FRE10
- RIC0_FRE11
- RIC0_FRE12
- RIC0_FRE13
- RIC0_FRE14
- RIC0_FRE15
- RIC0_FRE16
- RIC0_FRE17
- RIC0_FRE2
- RIC0_FRE3
- RIC0_FRE4
- RIC0_FRE5
- RIC0_FRE6
- RIC0_FRE7
- RIC0_FRE8
- RIC0_FRE9
- RIC1
- RIC1_BIT
- RIC1_RFWE
- RIC2
- RIC2_BIT
- RIC2_QFE0
- RIC2_QFE1
- RIC2_QFE10
- RIC2_QFE11
- RIC2_QFE12
- RIC2_QFE13
- RIC2_QFE14
- RIC2_QFE15
- RIC2_QFE16
- RIC2_QFE17
- RIC2_QFE2
- RIC2_QFE3
- RIC2_QFE4
- RIC2_QFE5
- RIC2_QFE6
- RIC2_QFE7
- RIC2_QFE8
- RIC2_QFE9
- RIC2_RFFE
- RICH
- RICH_SIMPLE
- RICH_SIMPLE_WB
- RICH_WB
- RICLK
- RICOH_ONOFFSEL_REG
- RICOH_SWCTL_REG
- RICR
- RIC_FLUSH_ALL
- RIC_FLUSH_PWC
- RIC_FLUSH_TLB
- RID0
- RID0_BIT
- RID0_FRD0
- RID0_FRD1
- RID0_FRD10
- RID0_FRD11
- RID0_FRD12
- RID0_FRD13
- RID0_FRD14
- RID0_FRD15
- RID0_FRD16
- RID0_FRD17
- RID0_FRD2
- RID0_FRD3
- RID0_FRD4
- RID0_FRD5
- RID0_FRD6
- RID0_FRD7
- RID0_FRD8
- RID0_FRD9
- RID1
- RID1d
- RID2
- RID2_BIT
- RID2_QFD0
- RID2_QFD1
- RID2_QFD10
- RID2_QFD11
- RID2_QFD12
- RID2_QFD13
- RID2_QFD14
- RID2_QFD15
- RID2_QFD16
- RID2_QFD17
- RID2_QFD2
- RID2_QFD3
- RID2_QFD4
- RID2_QFD5
- RID2_QFD6
- RID2_QFD7
- RID2_QFD8
- RID2_QFD9
- RID2_RFFD
- RID2d
- RIDRAM_CORRUPT_MASK
- RIDSIZE
- RID_ACTUALCONFIG
- RID_APINFO
- RID_APLIST
- RID_BEACON_HST
- RID_BSSLISTFIRST
- RID_BSSLISTNEXT
- RID_BUSY_HST
- RID_CAPABILITIES
- RID_CONFIG
- RID_DRVNAME
- RID_ECHOTEST_RESULTS
- RID_ECHOTEST_RID
- RID_ETHERENCAP
- RID_FACTORYCONFIG
- RID_LEAPPASSWORD
- RID_LEAPUSERNAME
- RID_MIC
- RID_MODULATION
- RID_OPTIONS
- RID_RADIOINFO
- RID_RETRIES_HST
- RID_RSSI
- RID_RW
- RID_SSID
- RID_STATS
- RID_STATS16
- RID_STATS16DELTA
- RID_STATS16DELTACLEAR
- RID_STATSDELTA
- RID_STATSDELTACLEAR
- RID_STATUS
- RID_UNKNOWN22
- RID_UNKNOWN3
- RID_UNKNOWN54
- RID_UNKNOWN55
- RID_UNKNOWN56
- RID_WEP_PERM
- RID_WEP_TEMP
- RID_WPA_BSSLISTFIRST
- RID_WPA_BSSLISTNEXT
- RIE0
- RIE0_BIT
- RIE0_FRS0
- RIE0_FRS1
- RIE0_FRS10
- RIE0_FRS11
- RIE0_FRS12
- RIE0_FRS13
- RIE0_FRS14
- RIE0_FRS15
- RIE0_FRS16
- RIE0_FRS17
- RIE0_FRS2
- RIE0_FRS3
- RIE0_FRS4
- RIE0_FRS5
- RIE0_FRS6
- RIE0_FRS7
- RIE0_FRS8
- RIE0_FRS9
- RIE2
- RIE2_BIT
- RIE2_QFS0
- RIE2_QFS1
- RIE2_QFS10
- RIE2_QFS11
- RIE2_QFS12
- RIE2_QFS13
- RIE2_QFS14
- RIE2_QFS15
- RIE2_QFS16
- RIE2_QFS17
- RIE2_QFS2
- RIE2_QFS3
- RIE2_QFS4
- RIE2_QFS5
- RIE2_QFS6
- RIE2_QFS7
- RIE2_QFS8
- RIE2_QFS9
- RIE2_RFFS
- RIEBL_HWADDR_ADDR
- RIEBL_IVEC_ADDR
- RIEBL_MAGIC
- RIEBL_MAGIC_ADDR
- RIEBL_RSVD_END
- RIEBL_RSVD_START
- RIF
- RIFF_HEADER
- RIFS_11N_TIME
- RIFS_ENABLE
- RIGHT
- RIGHTA_LEFTB
- RIGHTA_MUTEB
- RIGHTA_RIGHTB
- RIGHTA_SUMLRDIV2B
- RIGHTNODE
- RIGHTPATH
- RIGHT_ALIGNED
- RIGHT_ANTENNA
- RIGHT_BRANCH_VDSC_ENABLE
- RIGHT_CLIP
- RIGHT_DL_BUF_TARGET_DEPTH
- RIGHT_DL_BUF_TARGET_DEPTH_MASK
- RIGHT_EDGE
- RIGHT_END_POINT_DETECTION_LEVEL
- RIGHT_EYE
- RIGHT_EYE_3D_PRIMARY_SURFACE
- RIGHT_J
- RIGHT_J_DATA_FORMAT
- RIGHT_MIXER
- RIGHT_OUTPUT_MIXER_ROUTES
- RIGHT_PARENTS
- RIGHT_SHIFT_FLOW
- RIGHT_SHIFT_NO_FLOW
- RIGHT_SPK_TDM_TX_MASK
- RIGHT_TO_LEFT
- RIIC_ICBRH
- RIIC_ICBRL
- RIIC_ICCR1
- RIIC_ICCR2
- RIIC_ICDRR
- RIIC_ICDRT
- RIIC_ICIER
- RIIC_ICMR1
- RIIC_ICMR3
- RIIC_ICSER
- RIIC_ICSR2
- RIIC_INIT_MSG
- RIII_CLKSEL_DSP
- RIII_CLKSEL_DSP_IF
- RIII_CLKSEL_GFX
- RIII_CLKSEL_IVA
- RIII_CLKSEL_L3
- RIII_CLKSEL_L4
- RIII_CLKSEL_MPU
- RIII_CLKSEL_USB
- RIII_CM_CLKSEL1_CORE_VAL
- RIII_CM_CLKSEL_DSP_VAL
- RIII_CM_CLKSEL_GFX_VAL
- RIII_CM_CLKSEL_MPU_VAL
- RIII_SYNC_DSP
- RIII_SYNC_IVA
- RII_CLKSEL_DSP
- RII_CLKSEL_DSP_IF
- RII_CLKSEL_GFX
- RII_CLKSEL_IVA
- RII_CLKSEL_L3
- RII_CLKSEL_L4
- RII_CLKSEL_MPU
- RII_CLKSEL_USB
- RII_CM_CLKSEL1_CORE_VAL
- RII_CM_CLKSEL_DSP_VAL
- RII_CM_CLKSEL_GFX_VAL
- RII_CM_CLKSEL_MPU_VAL
- RII_SYNC_DSP
- RII_SYNC_IVA
- RIM_CHUNK_SIZE
- RING1_RQ_PENDING
- RING2_RQ_PENDING
- RINGADDRH_LEN
- RINGADDRH_POS
- RINGADDRL_LEN
- RINGADDRL_POS
- RINGBUFFERSIZE
- RINGBUFFER_HVS_MAX_SIZE
- RINGBUFFER_HVS_RCV_SIZE
- RINGBUFFER_HVS_SND_SIZE
- RINGBUFFER_SIZE
- RINGBUF_REG_CAPTURE
- RINGBUF_REG_PLAYBACK
- RINGBUF_TYPE_DATA
- RINGBUF_TYPE_DATA_TYPE_LEN_MAX
- RINGBUF_TYPE_PADDING
- RINGBUF_TYPE_TIME_EXTEND
- RINGBUF_TYPE_TIME_STAMP
- RINGB_2CODEC_ID_MASK
- RINGB_DIS_VALIDATION
- RINGB_EN_2CODEC
- RINGB_EN_SPDIF
- RINGB_SING_BIT_DUAL
- RINGF_DIR
- RINGID
- RINGID0
- RINGID1
- RINGID2
- RINGID3
- RINGMODE_LEN
- RINGMODE_POS
- RINGOSC_MASK__MASK_MASK
- RINGOSC_MASK__MASK__SHIFT
- RINGREF_NAME_LEN
- RINGSIZE
- RINGSIZE_LEN
- RINGSIZE_POS
- RINGTYPE_LEN
- RINGTYPE_POS
- RING_ACTHD
- RING_ACTHD_UDW
- RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR
- RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT
- RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX
- RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN
- RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT
- RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR
- RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT
- RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE
- RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET
- RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN
- RING_ALIGN
- RING_ALIGN_ORDER
- RING_ALLOC_REQ_ENABLES_MAX_BW_VALID
- RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID
- RING_ALLOC_REQ_ENABLES_RING_ARB_CFG
- RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID
- RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID
- RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID
- RING_ALLOC_REQ_FLAGS_RX_SOP_PAD
- RING_ALLOC_REQ_INT_MODE_LAST
- RING_ALLOC_REQ_INT_MODE_LEGACY
- RING_ALLOC_REQ_INT_MODE_MSIX
- RING_ALLOC_REQ_INT_MODE_POLL
- RING_ALLOC_REQ_INT_MODE_RSVD
- RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK
- RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT
- RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE
- RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA
- RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
- RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO
- RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST
- RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK
- RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA
- RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100
- RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT
- RING_ALLOC_REQ_MAX_BW_SCALE
- RING_ALLOC_REQ_MAX_BW_SCALE_BITS
- RING_ALLOC_REQ_MAX_BW_SCALE_BYTES
- RING_ALLOC_REQ_MAX_BW_SCALE_LAST
- RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST
- RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK
- RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK
- RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT
- RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT
- RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP
- RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ
- RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK
- RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT
- RING_ALLOC_REQ_RING_TYPE_L2_CMPL
- RING_ALLOC_REQ_RING_TYPE_LAST
- RING_ALLOC_REQ_RING_TYPE_NQ
- RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL
- RING_ALLOC_REQ_RING_TYPE_RX
- RING_ALLOC_REQ_RING_TYPE_RX_AGG
- RING_ALLOC_REQ_RING_TYPE_TX
- RING_AVAIL
- RING_AVAIL_PERCENT_HIWATER
- RING_AVAIL_PERCENT_LOWATER
- RING_BBADDR
- RING_BBADDR_UDW
- RING_BBSTATE
- RING_BB_PER_CTX_PTR
- RING_BB_PPGTT
- RING_BD_ALIGN_CHECK
- RING_BD_ALIGN_ORDER
- RING_BD_DESC_COUNT
- RING_BD_DESC_PER_REQ
- RING_BD_READ_PTR
- RING_BD_READ_PTR_DDR_CONTROL
- RING_BD_READ_PTR_DDR_LS
- RING_BD_READ_PTR_DDR_MS
- RING_BD_SIZE
- RING_BD_START_ADDR
- RING_BD_TOGGLE_INVALID
- RING_BD_TOGGLE_VALID
- RING_BD_WRITE_PTR
- RING_BELL
- RING_BUFFER
- RING_BUFFER_ALL_CPUS
- RING_BUFFER_INSTRUCTION
- RING_BUFFER_WRITABLE
- RING_BUFF_DONE_MASK
- RING_BUFF_DONE_SHIFT
- RING_BUFNUM_BUFPOOL
- RING_BUFNUM_INVALID
- RING_BUFNUM_MASK
- RING_BUFNUM_REGULAR
- RING_BUFPOOL
- RING_BUFSIZE
- RING_BUSY
- RING_BUS_CTRL_A
- RING_BUS_CTRL_B
- RING_CFGSIZE_16KB
- RING_CFGSIZE_2KB
- RING_CFGSIZE_512B
- RING_CFGSIZE_512KB
- RING_CFGSIZE_64KB
- RING_CFGSIZE_INVALID
- RING_CLK_EN
- RING_CLK_EN_SHT
- RING_CLOSED
- RING_CLOSING
- RING_CMP
- RING_CMPL_ALIGN_ORDER
- RING_CMPL_DESC_COUNT
- RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR
- RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX
- RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
- RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT
- RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR
- RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
- RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ
- RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE
- RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET
- RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE
- RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET
- RING_CMPL_SIZE
- RING_CMPL_START_ADDR
- RING_CMPL_WRITE_PTR
- RING_CONS_INDEX_MASK
- RING_CONS_INDEX_SHIFT
- RING_CONTEXT_CONTROL
- RING_CONTEXT_STATUS_PTR
- RING_CONTROL
- RING_COPY_REQUEST
- RING_COUNT
- RING_COUNT_MASK
- RING_CREDIT_MASK
- RING_CREDIT_SHIFT
- RING_CTL
- RING_CTL_SIZE
- RING_CTRL_OVERRIDE_HOST_THRSH_LEN
- RING_CTRL_OVERRIDE_HOST_THRSH_MSK
- RING_CTRL_OVERRIDE_HOST_THRSH_POS
- RING_CTRL_OVERRIDE_ITR_THRSH_LEN
- RING_CTRL_OVERRIDE_ITR_THRSH_MSK
- RING_CTRL_OVERRIDE_ITR_THRSH_POS
- RING_CTRL_OVERRIDE_PREFETCH_THRSH_LEN
- RING_CTRL_OVERRIDE_PREFETCH_THRSH_MSK
- RING_CTRL_OVERRIDE_PREFETCH_THRSH_POS
- RING_CTRL_OVERRIDE_WB_THRSH_LEN
- RING_CTRL_OVERRIDE_WB_THRSH_MSK
- RING_CTRL_OVERRIDE_WB_THRSH_POS
- RING_CTX_OFF
- RING_CTX_TIMESTAMP
- RING_DEF
- RING_DEI
- RING_DESC_ALIGN
- RING_DESC_BUFFER_OVERRUN
- RING_DESC_COMPLETED
- RING_DESC_CRC_ERROR
- RING_DESC_INDEX
- RING_DESC_INTERRUPT
- RING_DESC_ISOCH
- RING_DESC_OFFSET
- RING_DESC_POSTED
- RING_DESC_SIZE
- RING_DISABLED
- RING_DMA_FADD
- RING_DMA_FADD_UDW
- RING_DOWN
- RING_E2E_UNUSED_HOPID
- RING_ELSP
- RING_EMPTY_INTR_EN
- RING_EN
- RING_ENABLE
- RING_ENTRIES
- RING_ENTRY_CODE_DONE
- RING_ENTRY_CODE_MORE
- RING_ENTRY_SIZE
- RING_EXCC
- RING_EXECLIST0_ACTIVE
- RING_EXECLIST0_VALID
- RING_EXECLIST1_ACTIVE
- RING_EXECLIST1_VALID
- RING_EXECLIST_ACTIVE_STATUS
- RING_EXECLIST_CONTROL
- RING_EXECLIST_QFULL
- RING_EXECLIST_SQ_CONTENTS
- RING_EXECLIST_STATUS_HI
- RING_EXECLIST_STATUS_LO
- RING_FAILOVER_EN
- RING_FAULT_FAULT_TYPE
- RING_FAULT_GTTSEL_MASK
- RING_FAULT_REG
- RING_FAULT_SRCID
- RING_FAULT_VALID
- RING_FINAL_CHECK_FOR_REQUESTS
- RING_FINAL_CHECK_FOR_RESPONSES
- RING_FIRST_USABLE_HOPID
- RING_FLAG_E2E
- RING_FLAG_E2E_FLOW_CONTROL
- RING_FLAG_ENABLE
- RING_FLAG_FRAME
- RING_FLAG_ISOCH_ENABLE
- RING_FLAG_NO_SUSPEND
- RING_FLAG_PCI_NO_SNOOP
- RING_FLAG_RAW
- RING_FLUSH
- RING_FLUSH_DONE
- RING_FORCE_TO_NONPRIV
- RING_FORCE_TO_NONPRIV_ACCESS_INVALID
- RING_FORCE_TO_NONPRIV_ACCESS_MASK
- RING_FORCE_TO_NONPRIV_ACCESS_RD
- RING_FORCE_TO_NONPRIV_ACCESS_RW
- RING_FORCE_TO_NONPRIV_ACCESS_WR
- RING_FORCE_TO_NONPRIV_MASK_VALID
- RING_FORCE_TO_NONPRIV_RANGE_1
- RING_FORCE_TO_NONPRIV_RANGE_16
- RING_FORCE_TO_NONPRIV_RANGE_4
- RING_FORCE_TO_NONPRIV_RANGE_64
- RING_FORCE_TO_NONPRIV_RANGE_MASK
- RING_FREE_REQUESTS
- RING_FREE_REQ_RING_TYPE_L2_CMPL
- RING_FREE_REQ_RING_TYPE_LAST
- RING_FREE_REQ_RING_TYPE_NQ
- RING_FREE_REQ_RING_TYPE_ROCE_CMPL
- RING_FREE_REQ_RING_TYPE_RX
- RING_FREE_REQ_RING_TYPE_RX_AGG
- RING_FREE_REQ_RING_TYPE_TX
- RING_FULL
- RING_F_ARRAY_SIZE
- RING_F_FCOE
- RING_F_FDIR
- RING_F_NONE
- RING_F_QOS
- RING_F_RSS
- RING_F_VMDQ
- RING_GET_REQUEST
- RING_GET_RESPONSE
- RING_GFX_MODE
- RING_HAS_UNCONSUMED_REQUESTS
- RING_HAS_UNCONSUMED_RESPONSES
- RING_HEAD
- RING_HEAD_MASK
- RING_HEAD_TAIL_PTR
- RING_HEAD_WRAP_MASK
- RING_HEAD_WRAP_SHIFT
- RING_HWSTAM
- RING_HWS_PGA
- RING_HWS_PGA_GEN6
- RING_HYST_THRESH_MASK
- RING_HYST_THRESH_SHIFT
- RING_IDX
- RING_IGNORE_STATUS
- RING_IMR
- RING_INDIRECT_CTX
- RING_INDIRECT_CTX_OFFSET
- RING_INSTDONE
- RING_INSTPM
- RING_INSTPS
- RING_INTERRUPT_REG_COUNT
- RING_INTR_CONTROL
- RING_INTR_THRESH_MASK
- RING_INT_ENABLE
- RING_INT_PENDING
- RING_INUSE
- RING_INVALID
- RING_IN_ENABLE
- RING_IPEHR
- RING_IPEIR
- RING_LEN
- RING_LENGTH_MASK
- RING_LOCALS
- RING_MAPPING
- RING_MAX_DESC_VER_1
- RING_MAX_DESC_VER_2_3
- RING_MAX_HYST
- RING_MAX_IDLE
- RING_MAX_NONPRIV_SLOTS
- RING_MAX_REQ_COUNT
- RING_MAX_THRESH_MASK
- RING_MIN_FREE
- RING_MI_MODE
- RING_MODE_GEN7
- RING_MSI_ADDR_LS
- RING_MSI_ADDR_MS
- RING_MSI_CONTROL
- RING_MSI_DATA_VALUE
- RING_NEXT
- RING_NOPID
- RING_NOTIFY_REG_COUNT
- RING_NO_REPORT
- RING_NR_PAGES
- RING_NUM_FRAMES
- RING_NUM_REQ_OUTSTAND
- RING_NUM_REQ_RECV_LS
- RING_NUM_REQ_RECV_MS
- RING_NUM_REQ_TRANS_LS
- RING_NUM_REQ_TRANS_MS
- RING_OPEN
- RING_ORG_BUFF1
- RING_OWNER_CPU
- RING_OWNER_ETH0
- RING_OWNER_ETH1
- RING_OWNER_INVALID
- RING_OWNER_MASK
- RING_PCP_DEI_VID
- RING_PCP_MASK
- RING_PCP_SHIFT
- RING_PKT_SIZE_ADJ_MASK
- RING_PKT_SIZE_ADJ_SHIFT
- RING_POLL
- RING_PORT_ID_MASK
- RING_PORT_ID_SHIFT
- RING_PP_DIR_BASE
- RING_PP_DIR_BASE_READ
- RING_PP_DIR_DCLV
- RING_PROD_CONS_INDEX
- RING_PROD_INDEX_MASK
- RING_PSMI_CTL
- RING_PUSH_REQUESTS
- RING_PUSH_REQUESTS_AND_CHECK_NOTIFY
- RING_PUSH_RESPONSES
- RING_PUSH_RESPONSES_AND_CHECK_NOTIFY
- RING_QID_MASK
- RING_REG
- RING_REGS_SIZE
- RING_REGULAR
- RING_REPORT_128K
- RING_REPORT_4K
- RING_REPORT_64K
- RING_REPORT_MASK
- RING_REQUEST_CONS_OVERFLOW
- RING_REQUEST_PROD_OVERFLOW
- RING_RESET_CTL
- RING_RESET_REQ_RING_TYPE_L2_CMPL
- RING_RESET_REQ_RING_TYPE_LAST
- RING_RESET_REQ_RING_TYPE_ROCE_CMPL
- RING_RESET_REQ_RING_TYPE_RX
- RING_RESET_REQ_RING_TYPE_TX
- RING_SBBADDR
- RING_SBBADDR_UDW
- RING_SBBSTATE
- RING_SEMA_WAIT_POLL
- RING_SIZE
- RING_SIZE_AUDIO
- RING_SIZE_MASK
- RING_SIZE_MIN
- RING_SIZE_TS
- RING_SIZE_VIDEO
- RING_SPACE
- RING_SPACE_TEST_WITH_RETURN
- RING_START
- RING_START_MASK
- RING_SYNC_0
- RING_SYNC_1
- RING_SYNC_2
- RING_TAIL
- RING_TAIL_MASK
- RING_TAIL_SHIFT
- RING_TIMEOUT
- RING_TIMEOUT_MASK
- RING_TIMEOUT_SHIFT
- RING_TIMESTAMP
- RING_TIMESTAMP_UDW
- RING_TO_VFNO
- RING_TYPE
- RING_USED
- RING_VALID
- RING_VALID_MASK
- RING_VER
- RING_VER_MAGIC
- RING_VID_MASK
- RING_WAIT
- RING_WAIT_I8XX
- RING_WAIT_SEMAPHORE
- RING_WORDS
- RINT
- RINT0
- RINTEN0
- RINTM
- RINTOFSR
- RINT_SUM
- RINVOL_RIN_ENABLE_MUTE
- RINVOL_RIN_VOL
- RINVOL_RLIN_BOTH
- RIO
- RIO2_IO_ERROR
- RIO2_IO_SUREWRITE
- RIO2_IO_TYPE
- RIO2_IO_TYPE_READ
- RIO2_IO_TYPE_VERIFY
- RIO2_IO_TYPE_WRITE
- RIO2_SGL_CONFORMANT
- RIO2_SG_FORMAT
- RIO2_SG_FORMAT_ARC
- RIO2_SG_FORMAT_IEEE1212
- RIO2_SG_FORMAT_SRL
- RIOCM_CHNUM_AUTO
- RIOCM_CONNECT_TO
- RIOCM_MAX_CHNUM
- RIOCM_MAX_EP_COUNT
- RIOCM_RX_RING_SIZE
- RIOCM_TX_RING_SIZE
- RIOEN
- RIONET_DEFAULT_MSGLEVEL
- RIONET_DOORBELL_JOIN
- RIONET_DOORBELL_LEAVE
- RIONET_GET_DESTID
- RIONET_MAC_MATCH
- RIONET_MAILBOX
- RIONET_MAX_MTU
- RIONET_MAX_NETS
- RIONET_MSG_SIZE
- RIONET_RX_RING_SIZE
- RIONET_TX_RING_SIZE
- RIO_16_BAD
- RIO_32_BAD
- RIO_8_BAD
- RIO_ALLOC_DMA
- RIO_ANY_DESTID
- RIO_ANY_ID
- RIO_ASM_ID_CAR
- RIO_ASM_ID_MASK
- RIO_ASM_INFO_CAR
- RIO_ASM_REV_MASK
- RIO_ASM_VEN_ID_MASK
- RIO_ATMU_REGS_DBELL_OFFSET
- RIO_ATMU_REGS_PORT1_OFFSET
- RIO_ATMU_REGS_PORT2_OFFSET
- RIO_BAD_SIZE
- RIO_BC_L2_Gn_ENTRYx_CSR
- RIO_BC_RT_CTL_CSR
- RIO_BC_RT_LVL0_INFO_CSR
- RIO_BC_RT_LVL1_INFO_CSR
- RIO_BC_RT_LVL2_INFO_CSR
- RIO_CAP_DBL_RECV
- RIO_CAP_DBL_SEND
- RIO_CAP_MAP_INB
- RIO_CAP_MAP_OUTB
- RIO_CAP_PW_RECV
- RIO_CAP_PW_SEND
- RIO_CCSR
- RIO_CM_CHAN
- RIO_CM_CHAN_ACCEPT
- RIO_CM_CHAN_BIND
- RIO_CM_CHAN_BOUND
- RIO_CM_CHAN_CLOSE
- RIO_CM_CHAN_CONNECT
- RIO_CM_CHAN_CREATE
- RIO_CM_CHAN_LISTEN
- RIO_CM_CHAN_RECEIVE
- RIO_CM_CHAN_SEND
- RIO_CM_CONNECT
- RIO_CM_CONNECTED
- RIO_CM_DESTROYING
- RIO_CM_DISCONNECT
- RIO_CM_EP_GET_LIST
- RIO_CM_EP_GET_LIST_SIZE
- RIO_CM_IDLE
- RIO_CM_IOC_MAGIC
- RIO_CM_LISTEN
- RIO_CM_MPORT_GET_LIST
- RIO_CM_SYS
- RIO_COMPONENT_TAG_CSR
- RIO_CTAG_RESRVD
- RIO_CTAG_UDEVID
- RIO_DBELL_WIN_SIZE
- RIO_DEVICE
- RIO_DEVICE_GONE
- RIO_DEVICE_INITIALIZING
- RIO_DEVICE_RUNNING
- RIO_DEVICE_SHUTDOWN
- RIO_DEV_ADD
- RIO_DEV_DEL
- RIO_DEV_ID_CAR
- RIO_DEV_INFO_CAR
- RIO_DEV_PORT_N_ACK_STS_CSR
- RIO_DEV_PORT_N_CTL2_CSR
- RIO_DEV_PORT_N_CTL_CSR
- RIO_DEV_PORT_N_ERR_STS_CSR
- RIO_DEV_PORT_N_IB_ACK_CSR
- RIO_DEV_PORT_N_MNT_REQ_CSR
- RIO_DEV_PORT_N_MNT_RSP_CSR
- RIO_DEV_PORT_N_OB_ACK_CSR
- RIO_DID_CSR
- RIO_DID_IDT70K200
- RIO_DID_IDTCPS10Q
- RIO_DID_IDTCPS12
- RIO_DID_IDTCPS1432
- RIO_DID_IDTCPS16
- RIO_DID_IDTCPS1616
- RIO_DID_IDTCPS1848
- RIO_DID_IDTCPS6Q
- RIO_DID_IDTCPS8
- RIO_DID_IDTRXS1632
- RIO_DID_IDTRXS2448
- RIO_DID_IDTSPS1616
- RIO_DID_IDTVPS1616
- RIO_DID_MPC8560
- RIO_DID_TSI500
- RIO_DID_TSI568
- RIO_DID_TSI572
- RIO_DID_TSI574
- RIO_DID_TSI576
- RIO_DID_TSI577
- RIO_DID_TSI578
- RIO_DID_TSI721
- RIO_DISABLE_DOORBELL_RANGE
- RIO_DISABLE_PORTWRITE_RANGE
- RIO_DOORBELL
- RIO_DOORBELL_AVAIL
- RIO_DOORBELL_BUSY
- RIO_DOORBELL_CSR
- RIO_DOORBELL_EMPTY
- RIO_DOORBELL_ERROR
- RIO_DOORBELL_FAILED
- RIO_DOORBELL_FULL
- RIO_DOORBELL_RESOURCE
- RIO_DST_OPS_ATOMIC_CLR
- RIO_DST_OPS_ATOMIC_DEC
- RIO_DST_OPS_ATOMIC_INC
- RIO_DST_OPS_ATOMIC_SET
- RIO_DST_OPS_ATOMIC_TST_SWP
- RIO_DST_OPS_CAR
- RIO_DST_OPS_DATA_MSG
- RIO_DST_OPS_DOORBELL
- RIO_DST_OPS_PORT_WRITE
- RIO_DST_OPS_READ
- RIO_DST_OPS_STREAM_WRITE
- RIO_DST_OPS_WRITE
- RIO_DST_OPS_WRITE_RESPONSE
- RIO_EFB_ERR_MGMNT
- RIO_EFB_ERR_MGMNT_HS
- RIO_EFB_ID_MASK
- RIO_EFB_PTR_MASK
- RIO_EFB_SER_EPF_M1_ID
- RIO_EFB_SER_EPF_M2_ID
- RIO_EFB_SER_EPF_SW_M1_ID
- RIO_EFB_SER_EPF_SW_M2_ID
- RIO_EFB_SER_EP_FREE_ID
- RIO_EFB_SER_EP_ID
- RIO_EFB_SER_EP_M1_ID
- RIO_EFB_SER_EP_M2_ID
- RIO_EFB_SER_EP_REC_ID
- RIO_EFB_SER_EP_SW_M1_ID
- RIO_EFB_SER_EP_SW_M2_ID
- RIO_EFB_SW_ROUTING_TBL
- RIO_EM_DEV_INT_EN
- RIO_EM_EFB_HEADER
- RIO_EM_EMHS_CAR
- RIO_EM_LTL_ADDR_CAP
- RIO_EM_LTL_CTRL_CAP
- RIO_EM_LTL_DEVID_CAP
- RIO_EM_LTL_DID32_CAP
- RIO_EM_LTL_ERR_DETECT
- RIO_EM_LTL_ERR_EN
- RIO_EM_LTL_HIADDR_CAP
- RIO_EM_LTL_SID32_CAP
- RIO_EM_PKT_TTL
- RIO_EM_PKT_TTL_VAL
- RIO_EM_PN_ATTRIB_CAP
- RIO_EM_PN_ERRRATE
- RIO_EM_PN_ERRRATE_EN
- RIO_EM_PN_ERRRATE_EN_OK2U
- RIO_EM_PN_ERRRATE_EN_U2OK
- RIO_EM_PN_ERRRATE_EN_UPDA
- RIO_EM_PN_ERRRATE_TR
- RIO_EM_PN_ERR_DETECT
- RIO_EM_PN_LINK_UDT
- RIO_EM_PN_LINK_UDT_TO
- RIO_EM_PN_PKT_CAP_0
- RIO_EM_PN_PKT_CAP_1
- RIO_EM_PN_PKT_CAP_2
- RIO_EM_PN_PKT_CAP_3
- RIO_EM_PW_STAT
- RIO_EM_PW_TGT32_DEVID
- RIO_EM_PW_TGT_DEVID
- RIO_EM_PW_TGT_DEVID_D16M
- RIO_EM_PW_TGT_DEVID_D8
- RIO_EM_PW_TGT_DEVID_DEV16
- RIO_EM_PW_TGT_DEVID_DEV32
- RIO_EM_PW_TX_CTRL
- RIO_EM_PW_TX_CTRL_PW_DIS
- RIO_ENABLE_DOORBELL_RANGE
- RIO_ENABLE_PORTWRITE_RANGE
- RIO_ENTER_STORAGE
- RIO_EPWISR
- RIO_EPWISR_MU
- RIO_EPWISR_PINT1
- RIO_EPWISR_PINT2
- RIO_EPWISR_PW
- RIO_ESCSR
- RIO_EXCHANGE_DEFAULT
- RIO_EXCHANGE_NWRITE
- RIO_EXCHANGE_NWRITE_R
- RIO_EXCHANGE_NWRITE_R_ALL
- RIO_EXCHANGE_SWRITE
- RIO_EXCHANGE_SWRITE_R
- RIO_EXT_FTR_PTR_MASK
- RIO_FREE_DMA
- RIO_GCCSR
- RIO_GET_BLOCK_ID
- RIO_GET_BLOCK_PTR
- RIO_GET_DID
- RIO_GET_EVENT_MASK
- RIO_GET_PORT_NUM
- RIO_GET_TOTAL_PORTS
- RIO_GLOBAL_TABLE
- RIO_HDR_LETTER_MASK
- RIO_HDR_MBOX_MASK
- RIO_HOST_DID_LOCK_CSR
- RIO_IM0SR
- RIO_IM1SR
- RIO_INB_ATMU_COUNT
- RIO_INB_ATMU_REGS_PORT1_OFFSET
- RIO_INB_ATMU_REGS_PORT2_OFFSET
- RIO_INB_MBOX_RESOURCE
- RIO_INVALID_DESTID
- RIO_INVALID_ROUTE
- RIO_IO_SIZE
- RIO_IPWMR_CQ
- RIO_IPWMR_EIE
- RIO_IPWMR_PWE
- RIO_IPWMR_QFIE
- RIO_IPWMR_SEN
- RIO_IPWSR_PWB
- RIO_IPWSR_PWD
- RIO_IPWSR_QF
- RIO_IPWSR_QFI
- RIO_IPWSR_TE
- RIO_ISR_AACR
- RIO_ISR_AACR_AA
- RIO_LCSH_BA
- RIO_LCSL_BA
- RIO_LEAVE_STORAGE
- RIO_LINK_125
- RIO_LINK_16X
- RIO_LINK_1X
- RIO_LINK_1XR
- RIO_LINK_250
- RIO_LINK_2X
- RIO_LINK_312
- RIO_LINK_4X
- RIO_LINK_500
- RIO_LINK_625
- RIO_LINK_8X
- RIO_LINK_DOWN
- RIO_LOP_READ
- RIO_LOP_WRITE
- RIO_LTLEDCSR
- RIO_LTLEDCSR_IER
- RIO_LTLEDCSR_PRT
- RIO_LTLEECSR
- RIO_MAINT_SPACE_SZ
- RIO_MAINT_WIN_SIZE
- RIO_MAP_ANY_ADDR
- RIO_MAP_INBOUND
- RIO_MAP_OUTBOUND
- RIO_MAX_CHK_RETRY
- RIO_MAX_DEVNAME_SZ
- RIO_MAX_DEV_RESOURCES
- RIO_MAX_MBOX
- RIO_MAX_MPORTS
- RIO_MAX_MPORT_NAME
- RIO_MAX_MPORT_RESOURCES
- RIO_MAX_MSG_SIZE
- RIO_MAX_ROUTE_ENTRIES
- RIO_MAX_RX_RING_SIZE
- RIO_MAX_TX_RING_SIZE
- RIO_MBOX0_AVAIL
- RIO_MBOX0_BUSY
- RIO_MBOX0_EMPTY
- RIO_MBOX0_ERROR
- RIO_MBOX0_FAIL
- RIO_MBOX0_FULL
- RIO_MBOX1_AVAIL
- RIO_MBOX1_BUSY
- RIO_MBOX1_EMPTY
- RIO_MBOX1_ERROR
- RIO_MBOX1_FAIL
- RIO_MBOX1_FULL
- RIO_MBOX2_AVAIL
- RIO_MBOX2_BUSY
- RIO_MBOX2_EMPTY
- RIO_MBOX2_ERROR
- RIO_MBOX2_FAIL
- RIO_MBOX2_FULL
- RIO_MBOX3_AVAIL
- RIO_MBOX3_BUSY
- RIO_MBOX3_EMPTY
- RIO_MBOX3_ERROR
- RIO_MBOX3_FAIL
- RIO_MBOX3_FULL
- RIO_MBOX_CSR
- RIO_MIN_RX_RING_SIZE
- RIO_MIN_TX_RING_SIZE
- RIO_MNT_REQ_CMD_IS
- RIO_MNT_REQ_CMD_RD
- RIO_MPORT_ANY
- RIO_MPORT_DMA
- RIO_MPORT_DMA_SG
- RIO_MPORT_DRV_MAGIC
- RIO_MPORT_GET_PROPERTIES
- RIO_MPORT_IBSG
- RIO_MPORT_MAINT_COMPTAG_SET
- RIO_MPORT_MAINT_HDID_SET
- RIO_MPORT_MAINT_PORT_IDX_GET
- RIO_MPORT_MAINT_READ_LOCAL
- RIO_MPORT_MAINT_READ_REMOTE
- RIO_MPORT_MAINT_WRITE_LOCAL
- RIO_MPORT_MAINT_WRITE_REMOTE
- RIO_MSG_BUFFER_SIZE
- RIO_MSG_DESC_SIZE
- RIO_MSG_IMR_MI
- RIO_MSG_ISR_DIQI
- RIO_MSG_ISR_QFI
- RIO_MSG_ISR_TE
- RIO_MSG_OMR_MUI
- RIO_MSG_OSR_EOMI
- RIO_MSG_OSR_MUB
- RIO_MSG_OSR_QEI
- RIO_MSG_OSR_QFI
- RIO_MSG_OSR_QOI
- RIO_MSG_OSR_TE
- RIO_NO_HOPCOUNT
- RIO_OM0SR
- RIO_OM1SR
- RIO_OPS_ATOMIC_CLR
- RIO_OPS_ATOMIC_DEC
- RIO_OPS_ATOMIC_INC
- RIO_OPS_ATOMIC_SET
- RIO_OPS_ATOMIC_TST_SWP
- RIO_OPS_DATA_MSG
- RIO_OPS_DOORBELL
- RIO_OPS_PORT_WRITE
- RIO_OPS_READ
- RIO_OPS_STREAM_WRITE
- RIO_OPS_WRITE
- RIO_OPS_WRITE_RESPONSE
- RIO_OP_READ
- RIO_OP_WRITE
- RIO_OUTB_MBOX_RESOURCE
- RIO_PEF_ADDR_34
- RIO_PEF_ADDR_50
- RIO_PEF_ADDR_66
- RIO_PEF_BRIDGE
- RIO_PEF_CAR
- RIO_PEF_CTLS
- RIO_PEF_DEV16
- RIO_PEF_DEV32
- RIO_PEF_EXT_FEATURES
- RIO_PEF_EXT_RT
- RIO_PEF_INB_DOORBELL
- RIO_PEF_INB_MBOX
- RIO_PEF_INB_MBOX0
- RIO_PEF_INB_MBOX1
- RIO_PEF_INB_MBOX2
- RIO_PEF_INB_MBOX3
- RIO_PEF_MEMORY
- RIO_PEF_MULTIPORT
- RIO_PEF_PROCESSOR
- RIO_PEF_STD_RT
- RIO_PEF_SWITCH
- RIO_PELL_ADDR_34
- RIO_PELL_ADDR_50
- RIO_PELL_ADDR_66
- RIO_PELL_CTRL_CSR
- RIO_PLM_SPx_IMP_SPEC_CTL
- RIO_PLM_SPx_IMP_SPEC_CTL_SOFT_RST
- RIO_PLM_SPx_PW_EN
- RIO_PLM_SPx_PW_EN_LINIT
- RIO_PLM_SPx_PW_EN_OK2U
- RIO_PM_OPS
- RIO_PORT1_EDCSR
- RIO_PORT1_IECSR
- RIO_PORT2_EDCSR
- RIO_PORT2_ESCSR
- RIO_PORT2_IECSR
- RIO_PORTWRITE
- RIO_PORT_GEN_CTL_CSR
- RIO_PORT_GEN_DISCOVERED
- RIO_PORT_GEN_HOST
- RIO_PORT_GEN_MASTER
- RIO_PORT_LINKTO_CTL_CSR
- RIO_PORT_MNT_HEADER
- RIO_PORT_N_ACK_CLEAR
- RIO_PORT_N_ACK_INBOUND
- RIO_PORT_N_ACK_OUTBOUND
- RIO_PORT_N_ACK_OUTSTAND
- RIO_PORT_N_ACK_STS_CSR
- RIO_PORT_N_CTL2_CSR
- RIO_PORT_N_CTL2_SEL_BAUD
- RIO_PORT_N_CTL_CSR
- RIO_PORT_N_CTL_EN_RX
- RIO_PORT_N_CTL_EN_TX
- RIO_PORT_N_CTL_IPW
- RIO_PORT_N_CTL_LOCKOUT
- RIO_PORT_N_CTL_PWIDTH
- RIO_PORT_N_CTL_PWIDTH_1
- RIO_PORT_N_CTL_PWIDTH_4
- RIO_PORT_N_CTL_P_TYP_SER
- RIO_PORT_N_ERR_STS_CSR
- RIO_PORT_N_ERR_STS_INP_ES
- RIO_PORT_N_ERR_STS_OUT_ES
- RIO_PORT_N_ERR_STS_PORT_ERR
- RIO_PORT_N_ERR_STS_PORT_OK
- RIO_PORT_N_ERR_STS_PORT_UA
- RIO_PORT_N_ERR_STS_PORT_UNINIT
- RIO_PORT_N_ERR_STS_PW_PEND
- RIO_PORT_N_IB_ACK_CSR
- RIO_PORT_N_IB_ACK_INBND
- RIO_PORT_N_MNT_REQ_CSR
- RIO_PORT_N_MNT_RSP_ASTAT
- RIO_PORT_N_MNT_RSP_CSR
- RIO_PORT_N_MNT_RSP_LSTAT
- RIO_PORT_N_MNT_RSP_RVAL
- RIO_PORT_N_OB_ACK_CLEAR
- RIO_PORT_N_OB_ACK_CSR
- RIO_PORT_N_OB_ACK_OUTBND
- RIO_PORT_N_OB_ACK_OUTSTD
- RIO_PORT_REQ_CTL_CSR
- RIO_PORT_RSPTO_CTL_CSR
- RIO_PORT_RSP_CTL_CSR
- RIO_PREFIX
- RIO_PREFIX_LEN
- RIO_PW_CTL
- RIO_PW_CTL_PW_TMR
- RIO_PW_MSG_SIZE
- RIO_PW_ROUTE
- RIO_RECV_LEN
- RIO_REGS_WIN
- RIO_RESET
- RIO_RESOURCE_BUSY
- RIO_RESOURCE_CACHEABLE
- RIO_RESOURCE_DOORBELL
- RIO_RESOURCE_MAILBOX
- RIO_RESOURCE_MEM
- RIO_RESOURCE_PCI
- RIO_RT_CTL_DEV32_RT_CTRL
- RIO_RT_CTL_MC_MASK_SZ
- RIO_RT_CTL_THREE_LVL
- RIO_RT_ENTRY_DROP_PKT
- RIO_RT_L0I_GR_PTR
- RIO_RT_L0I_NUM_GR
- RIO_RT_L1I_GR_PTR
- RIO_RT_L1I_NUM_GR
- RIO_RT_L2I_GR_PTR
- RIO_RT_L2I_NUM_GR
- RIO_RT_Ln_ENTRY_IMPL_DEF
- RIO_RT_Ln_ENTRY_RTE_VAL
- RIO_RT_MAX_DESTID
- RIO_SCAN_ENUM_NO_WAIT
- RIO_SEND_LEN
- RIO_SET_DID
- RIO_SET_EVENT_MASK
- RIO_SPx_L2_Gn_ENTRYy_CSR
- RIO_SPx_RT_CTL_CSR
- RIO_SPx_RT_LVL0_INFO_CSR
- RIO_SPx_RT_LVL1_INFO_CSR
- RIO_SPx_RT_LVL2_INFO_CSR
- RIO_SRC_OPS_ATOMIC_CLR
- RIO_SRC_OPS_ATOMIC_DEC
- RIO_SRC_OPS_ATOMIC_INC
- RIO_SRC_OPS_ATOMIC_SET
- RIO_SRC_OPS_ATOMIC_TST_SWP
- RIO_SRC_OPS_CAR
- RIO_SRC_OPS_DATA_MSG
- RIO_SRC_OPS_DOORBELL
- RIO_SRC_OPS_PORT_WRITE
- RIO_SRC_OPS_READ
- RIO_SRC_OPS_STREAM_WRITE
- RIO_SRC_OPS_WRITE
- RIO_SRC_OPS_WRITE_RESPONSE
- RIO_STD_RTE_CONF_DESTID_SEL_CSR
- RIO_STD_RTE_CONF_EXTCFGEN
- RIO_STD_RTE_CONF_PORT_SEL_CSR
- RIO_STD_RTE_DEFAULT_PORT
- RIO_SUCCESSFUL
- RIO_SUREWRITE
- RIO_SWITCH_RT_LIMIT
- RIO_SWP_INFO_CAR
- RIO_SWP_INFO_PORT_NUM_MASK
- RIO_SWP_INFO_PORT_TOTAL_MASK
- RIO_S_DBELL_REGS_OFFSET
- RIO_S_PW_REGS_OFFSET
- RIO_TABLE_VERSION
- RIO_TRANSFER
- RIO_TRANSFER_ASYNC
- RIO_TRANSFER_DIR_READ
- RIO_TRANSFER_DIR_WRITE
- RIO_TRANSFER_FAF
- RIO_TRANSFER_MODE_MAPPED
- RIO_TRANSFER_MODE_TRANSFER
- RIO_TRANSFER_SYNC
- RIO_TT_CODE_16
- RIO_TT_CODE_8
- RIO_TYPE_READ
- RIO_TYPE_WRITE
- RIO_UNMAP_INBOUND
- RIO_UNMAP_OUTBOUND
- RIO_VID_FREESCALE
- RIO_VID_IDT
- RIO_VID_TUNDRA
- RIO_WAIT_FOR_ASYNC
- RIO_WRITE_PORT_AVAILABLE
- RIO_WRITE_PORT_BUSY
- RIO_WRITE_PORT_CSR
- RIO_WRITE_PORT_EMPTY
- RIO_WRITE_PORT_ERROR
- RIO_WRITE_PORT_FAILED
- RIO_WRITE_PORT_FULL
- RIOd
- RIP
- RIPTIDE_PM_OPS
- RIQK_AGC_CONT
- RIQK_AGC_PTS
- RIQK_AGC_RSP
- RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL
- RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED
- RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED
- RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL
- RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED
- RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED
- RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL_MASK
- RIRB_CONTROL__RESPONSE_INTERRUPT_CONTROL__SHIFT
- RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL_MASK
- RIRB_CONTROL__RESPONSE_OVERRUN_INTERRUPT_CONTROL__SHIFT
- RIRB_CONTROL__RIRB_DMA_ENABLE_MASK
- RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT
- RIRB_INT_MASK
- RIRB_INT_OVERRUN
- RIRB_INT_RESPONSE
- RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS_MASK
- RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_ADDRESS__SHIFT
- RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS_MASK
- RIRB_LOWER_BASE_ADDRESS__RIRB_LOWER_BASE_UNIMPLEMENTED_BITS__SHIFT
- RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK
- RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT
- RIRB_SIZE__RIRB_SIZE_MASK
- RIRB_SIZE__RIRB_SIZE__SHIFT
- RIRB_STATUS__RESPONSE_INTERRUPT_MASK
- RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT
- RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS_MASK
- RIRB_STATUS__RESPONSE_OVERRUN_INTERRUPT_STATUS__SHIFT
- RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS_MASK
- RIRB_UPPER_BASE_ADDRESS__RIRB_UPPER_BASE_ADDRESS__SHIFT
- RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_MASK
- RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET_MASK
- RIRB_WRITE_POINTER__RIRB_WRITE_POINTER_RESET__SHIFT
- RIRB_WRITE_POINTER__RIRB_WRITE_POINTER__SHIFT
- RIR_OFFSET
- RIR_RNK_TGT
- RIR_WAY
- RIS0
- RIS0_BIT
- RIS0_FRF0
- RIS0_FRF1
- RIS0_FRF10
- RIS0_FRF11
- RIS0_FRF12
- RIS0_FRF13
- RIS0_FRF14
- RIS0_FRF15
- RIS0_FRF16
- RIS0_FRF17
- RIS0_FRF2
- RIS0_FRF3
- RIS0_FRF4
- RIS0_FRF5
- RIS0_FRF6
- RIS0_FRF7
- RIS0_FRF8
- RIS0_FRF9
- RIS0_RESERVED
- RIS1
- RIS1_BIT
- RIS1_RFWF
- RIS2
- RIS2_BIT
- RIS2_QFF0
- RIS2_QFF1
- RIS2_QFF10
- RIS2_QFF11
- RIS2_QFF12
- RIS2_QFF13
- RIS2_QFF14
- RIS2_QFF15
- RIS2_QFF16
- RIS2_QFF17
- RIS2_QFF2
- RIS2_QFF3
- RIS2_QFF4
- RIS2_QFF5
- RIS2_QFF6
- RIS2_QFF7
- RIS2_QFF8
- RIS2_QFF9
- RIS2_RESERVED
- RIS2_RFFF
- RISCIX_MAGIC
- RISCOM8_CALLOUT_MAJOR
- RISCOM8_NORMAL_MAJOR
- RISCV_ACQUIRE_BARRIER
- RISCV_BASE_COUNTERS
- RISCV_FENCE
- RISCV_HEADER_VERSION
- RISCV_HEADER_VERSION_MAJOR
- RISCV_HEADER_VERSION_MINOR
- RISCV_IMAGE_FLAG_BE
- RISCV_IMAGE_FLAG_BE_MASK
- RISCV_IMAGE_FLAG_BE_SHIFT
- RISCV_IMAGE_FLAG_LE
- RISCV_IMAGE_MAGIC
- RISCV_IMAGE_MAGIC2
- RISCV_INT
- RISCV_LGINT
- RISCV_LGPTR
- RISCV_LGSHORT
- RISCV_MAX_COUNTERS
- RISCV_MAX_REGS
- RISCV_OP_UNSUPP
- RISCV_PMU_CYCLE
- RISCV_PMU_INSTRET
- RISCV_PMU_MHPMCOUNTER3
- RISCV_PMU_MHPMCOUNTER4
- RISCV_PMU_MHPMCOUNTER5
- RISCV_PMU_MHPMCOUNTER6
- RISCV_PMU_MHPMCOUNTER7
- RISCV_PMU_MHPMCOUNTER8
- RISCV_PTR
- RISCV_RELEASE_BARRIER
- RISCV_SHORT
- RISCV_SZINT
- RISCV_SZPTR
- RISCV_SZSHORT
- RISC_124
- RISC_127
- RISC_BYTES_ENABLE
- RISC_CNT_INC
- RISC_CNT_NONE
- RISC_CNT_RESET
- RISC_CNT_RSVR
- RISC_EOL
- RISC_EXT_MEM_DUMP_CMPL
- RISC_FLUSH
- RISC_IMM
- RISC_INLINE
- RISC_INSTR
- RISC_INT
- RISC_INT_BIT
- RISC_IRQ
- RISC_IRQ1
- RISC_IRQ2
- RISC_JMP_SRP
- RISC_JUMP
- RISC_JUMP_INSTRUCTION_SIZE
- RISC_LINESTART
- RISC_MTREG
- RISC_MTREG_P0DFLT
- RISC_MTREG_P0ULTRA
- RISC_MTREG_P1DFLT
- RISC_MTREG_P1ULTRA
- RISC_NOOP
- RISC_NOOP_INSTRUCTION_SIZE
- RISC_OP
- RISC_PAUSE_CMPL
- RISC_PSR
- RISC_PSR_ACARRY
- RISC_PSR_AMSB
- RISC_PSR_AOFLOW
- RISC_PSR_AZERO
- RISC_PSR_DIRQ
- RISC_PSR_FFALSE
- RISC_PSR_FTRUE
- RISC_PSR_HIRQ
- RISC_PSR_IPEND
- RISC_PSR_LCD
- RISC_PSR_RIRQ
- RISC_PSR_SIRQ
- RISC_PSR_TOFLOW
- RISC_PSR_ULTRA
- RISC_RDY_AFT_RESET
- RISC_READ
- RISC_READC
- RISC_REGISTER_BASE_OFFSET
- RISC_REGISTER_WINDOW_OFFET
- RISC_RESET_STATUS_SHIFT
- RISC_RESYNC
- RISC_RESYNC_EVEN
- RISC_RESYNC_ODD
- RISC_SEMAPHORE
- RISC_SEMAPHORE_CLR
- RISC_SEMAPHORE_FORCE
- RISC_SEMAPHORE_FORCE_CLR
- RISC_SEMAPHORE_FORCE_SET
- RISC_SEMAPHORE_FORCE_WE
- RISC_SEMAPHORE_SET
- RISC_SEMAPHORE_WE
- RISC_SET_STATUS_SHIFT
- RISC_SKIP
- RISC_SKIP_INSTRUCTION_SIZE
- RISC_SLOT_E_FIELD
- RISC_SLOT_E_VBI
- RISC_SLOT_LOOP
- RISC_SLOT_O_FIELD
- RISC_SLOT_O_VBI
- RISC_SOL
- RISC_SRAM_DUMP_CMPL
- RISC_START_ADDRESS_2100
- RISC_START_ADDRESS_2300
- RISC_START_ADDRESS_2400
- RISC_STATUS
- RISC_SYNC
- RISC_SYNCE
- RISC_SYNCO
- RISC_SYNC_EVEN
- RISC_SYNC_EVEN_VBI
- RISC_SYNC_FM1
- RISC_SYNC_INSTRUCTION_SIZE
- RISC_SYNC_ODD
- RISC_SYNC_ODD_VBI
- RISC_SYNC_RESYNC
- RISC_SYNC_VRO
- RISC_WRITE
- RISC_WRITEC
- RISC_WRITECM
- RISC_WRITECR
- RISC_WRITECR_INSTRUCTION_SIZE
- RISC_WRITERM
- RISC_WRITE_INSTRUCTION_SIZE
- RISC_WR_EOL
- RISC_WR_SOL
- RISING_EDGE
- RISO_KAGAKU
- RISO_KAGAKU_IX
- RIVAFB_VERSION
- RIVA_FIFO_FREE
- RIVA_HW_INST
- RIVA_HW_STATE
- RIVA_RESET
- RIVA_SW_VERSION
- RIWAR_ENABLE
- RIWAR_RDTYP_NO_SNOOP
- RIWAR_RDTYP_SNOOP
- RIWAR_SIZE_MASK
- RIWAR_TGINT_LOCAL
- RIWAR_WRTYP_ALLOC
- RIWAR_WRTYP_NO_SNOOP
- RIWAR_WRTYP_SNOOP
- RIWBAR_BADD_MASK
- RIWBAR_BADD_VAL_SHIFT
- RIWTAR_TRAD_MASK
- RIWTAR_TRAD_VAL_SHIFT
- RI_3DES_PRESENT
- RI_AES_PRESENT
- RI_CLKSEL_DSP
- RI_CLKSEL_DSP_IF
- RI_CLKSEL_GFX
- RI_CLKSEL_IVA
- RI_CLKSEL_L3
- RI_CLKSEL_L4
- RI_CLKSEL_MPU
- RI_CLKSEL_USB
- RI_CLR_RD_PERR
- RI_CLR_WR_PERR
- RI_CM_CLKSEL1_CORE_VAL
- RI_CM_CLKSEL_DSP_VAL
- RI_CM_CLKSEL_GFX_VAL
- RI_CM_CLKSEL_MPU_VAL
- RI_ECC_PRESENT
- RI_ELFC_PRESENT
- RI_ELFC_SHIFT
- RI_FORMAT
- RI_LSB_ENTRIES
- RI_NLSB
- RI_NLSB_SHIFT
- RI_NUM_VQM
- RI_NVQM
- RI_NVQM_SHIFT
- RI_RATE_ID_MCS
- RI_RSA_PRESENT
- RI_RST_CLR
- RI_RST_SET
- RI_SHA_PRESENT
- RI_SYNC_DSP
- RI_SYNC_IVA
- RI_TRNG_PRESENT
- RI_VERSION_NUM
- RI_ZCE_PRESENT
- RI_ZDE_PRESENT
- RJ54N1_APT_GAIN_UP
- RJ54N1_BIT8_WB
- RJ54N1_BYTE_SWAP
- RJ54N1_CLK_RST
- RJ54N1_COLUMN_SKIP
- RJ54N1_DEV_CODE
- RJ54N1_DEV_CODE2
- RJ54N1_EXPOSURE_CONTROL
- RJ54N1_FRAME_LENGTH_P_H
- RJ54N1_FRAME_LENGTH_P_L
- RJ54N1_FRAME_LENGTH_S_H
- RJ54N1_FRAME_LENGTH_S_L
- RJ54N1_FWFLG
- RJ54N1_HCAPE_WB
- RJ54N1_HCAPS_WB
- RJ54N1_H_OBEN_OFS
- RJ54N1_INC_USE_SEL_H
- RJ54N1_INC_USE_SEL_L
- RJ54N1_INIT_START
- RJ54N1_IOC
- RJ54N1_LINE_LENGTH_PCK_P_H
- RJ54N1_LINE_LENGTH_PCK_P_L
- RJ54N1_LINE_LENGTH_PCK_S_H
- RJ54N1_LINE_LENGTH_PCK_S_L
- RJ54N1_MAX_HEIGHT
- RJ54N1_MAX_WIDTH
- RJ54N1_MIRROR_STILL_MODE
- RJ54N1_OCLK_DSP
- RJ54N1_OCLK_SEL_EN
- RJ54N1_OUT_SEL
- RJ54N1_OUT_SIGPO
- RJ54N1_PEAK_50
- RJ54N1_PEAK_60
- RJ54N1_PEAK_DIFF
- RJ54N1_PEAK_H
- RJ54N1_PLL_EN
- RJ54N1_PLL_L
- RJ54N1_PLL_N
- RJ54N1_RAMP_TGCLK_EN
- RJ54N1_RATIO_O
- RJ54N1_RATIO_OP
- RJ54N1_RATIO_R
- RJ54N1_RATIO_T
- RJ54N1_RATIO_TG
- RJ54N1_RA_SEL_UL
- RJ54N1_RESET_STANDBY
- RJ54N1_RESIZE_CONTROL
- RJ54N1_RESIZE_HOLD_H
- RJ54N1_RESIZE_HOLD_L
- RJ54N1_RESIZE_N
- RJ54N1_RESIZE_N_STEP
- RJ54N1_RESIZE_STEP
- RJ54N1_ROW_SKIP
- RJ54N1_SCALE_1_2_LEV
- RJ54N1_SCALE_4_LEV
- RJ54N1_STILL_CONTROL
- RJ54N1_TG_BYPASS
- RJ54N1_VCAPE_WB
- RJ54N1_VCAPS_WB
- RJ54N1_V_OBEN_OFS
- RJ54N1_WB_SEL_WEIGHT_I
- RJ54N1_XY_OUTPUT_SIZE_P_H
- RJ54N1_XY_OUTPUT_SIZE_S_H
- RJ54N1_X_OUTPUT_SIZE_P_L
- RJ54N1_X_OUTPUT_SIZE_S_L
- RJ54N1_Y_GAIN
- RJ54N1_Y_OUTPUT_SIZE_P_L
- RJ54N1_Y_OUTPUT_SIZE_S_L
- RJBR
- RJBR_ADDR
- RJUST
- RK0
- RK0x
- RK1
- RK1x
- RK2
- RK2928
- RK2928_CLKGATE_CON
- RK2928_CLKSEL_CON
- RK2928_GLB_SRST_FST
- RK2928_GLB_SRST_SND
- RK2928_MISC_CON
- RK2928_MODE_CON
- RK2928_PLL_CON
- RK2928_PULL_BANK_STRIDE
- RK2928_PULL_OFFSET
- RK2928_PULL_PINS_PER_REG
- RK2928_SOFTRST_CON
- RK2x
- RK3
- RK3036_ALPHA_CTRL
- RK3036_AXI_BUS_CTRL
- RK3036_BCSH_BCS
- RK3036_BCSH_COLOR_BAR
- RK3036_BCSH_CTRL
- RK3036_BCSH_H
- RK3036_CLKSEL1
- RK3036_CODEC_FMTS
- RK3036_CODEC_RATES
- RK3036_CPUCLK_RATE
- RK3036_DIV_ACLK_MASK
- RK3036_DIV_ACLK_SHIFT
- RK3036_DIV_CPU_MASK
- RK3036_DIV_CPU_SHIFT
- RK3036_DIV_HCLK_MASK
- RK3036_DIV_HCLK_SHIFT
- RK3036_DIV_PCLK_MASK
- RK3036_DIV_PCLK_SHIFT
- RK3036_DIV_PERI_MASK
- RK3036_DIV_PERI_SHIFT
- RK3036_DSP_CTRL0
- RK3036_DSP_CTRL1
- RK3036_DSP_HACT_ST_END
- RK3036_DSP_HTOTAL_HS_END
- RK3036_DSP_VACT_ST_END
- RK3036_DSP_VACT_ST_END_F1
- RK3036_DSP_VS_ST_END_F1
- RK3036_DSP_VTOTAL_VS_END
- RK3036_EMMC_CON0
- RK3036_EMMC_CON1
- RK3036_GATHER_TRANSFER
- RK3036_GRF_SOC_CON0
- RK3036_GRF_SOC_STATUS0
- RK3036_HWC_DSP_ST
- RK3036_HWC_LUT_ADDR
- RK3036_HWC_MST
- RK3036_INT_STATUS
- RK3036_PD_CORE
- RK3036_PD_GPU
- RK3036_PD_MSCH
- RK3036_PD_PERI
- RK3036_PD_SYS
- RK3036_PD_VIO
- RK3036_PD_VPU
- RK3036_PLLCON
- RK3036_PLLCON0_FBDIV_MASK
- RK3036_PLLCON0_FBDIV_SHIFT
- RK3036_PLLCON0_POSTDIV1_MASK
- RK3036_PLLCON0_POSTDIV1_SHIFT
- RK3036_PLLCON1_DSMPD_MASK
- RK3036_PLLCON1_DSMPD_SHIFT
- RK3036_PLLCON1_POSTDIV2_MASK
- RK3036_PLLCON1_POSTDIV2_SHIFT
- RK3036_PLLCON1_PWRDOWN
- RK3036_PLLCON1_REFDIV_MASK
- RK3036_PLLCON1_REFDIV_SHIFT
- RK3036_PLLCON2_FRAC_MASK
- RK3036_PLLCON2_FRAC_SHIFT
- RK3036_PLL_RATE
- RK3036_REG_CFG_DONE
- RK3036_SDIO_CON0
- RK3036_SDIO_CON1
- RK3036_SDMMC_CON0
- RK3036_SDMMC_CON1
- RK3036_SYS_CTRL
- RK3036_VERSION_INFO
- RK3036_WIN0_ACT_INFO
- RK3036_WIN0_CBR_MST
- RK3036_WIN0_COLOR_KEY
- RK3036_WIN0_DSP_INFO
- RK3036_WIN0_DSP_ST
- RK3036_WIN0_SCL_FACTOR_CBR
- RK3036_WIN0_SCL_FACTOR_YRGB
- RK3036_WIN0_SCL_OFFSET
- RK3036_WIN0_VIR
- RK3036_WIN0_YRGB_MST
- RK3036_WIN1_ACT_INFO
- RK3036_WIN1_COLOR_KEY
- RK3036_WIN1_DSP_INFO
- RK3036_WIN1_DSP_ST
- RK3036_WIN1_LUT_ADDR
- RK3036_WIN1_MST
- RK3036_WIN1_SCL_FACTOR_YRGB
- RK3036_WIN1_SCL_OFFSET
- RK3036_WIN1_VIR
- RK3066B
- RK3066_BLEND_CTRL
- RK3066_CLKSEL0
- RK3066_CLKSEL1
- RK3066_CPUCLK_RATE
- RK3066_DIV_ACLK_CORE_MASK
- RK3066_DIV_ACLK_CORE_SHIFT
- RK3066_DIV_ACLK_HCLK_MASK
- RK3066_DIV_ACLK_HCLK_SHIFT
- RK3066_DIV_ACLK_PCLK_MASK
- RK3066_DIV_ACLK_PCLK_SHIFT
- RK3066_DIV_AHB2APB_MASK
- RK3066_DIV_AHB2APB_SHIFT
- RK3066_DIV_CORE_PERIPH_MASK
- RK3066_DIV_CORE_PERIPH_SHIFT
- RK3066_DSP_CTRL0
- RK3066_DSP_CTRL1
- RK3066_DSP_HACT_ST_END
- RK3066_DSP_HTOTAL_HS_END
- RK3066_DSP_LUT_ADDR
- RK3066_DSP_VACT_ST_END
- RK3066_DSP_VACT_ST_END_F1
- RK3066_DSP_VS_ST_END_F1
- RK3066_DSP_VTOTAL_VS_END
- RK3066_GRF_SOC_STATUS
- RK3066_HWC_COLOR_LUT0
- RK3066_HWC_COLOR_LUT1
- RK3066_HWC_COLOR_LUT2
- RK3066_HWC_DSP_ST
- RK3066_HWC_MST
- RK3066_INT_STATUS
- RK3066_MCU_BYPASS_RPORT
- RK3066_MCU_BYPASS_WPORT
- RK3066_MCU_CTRL
- RK3066_PD_A9_0
- RK3066_PD_A9_1
- RK3066_PD_ALIVE
- RK3066_PD_CPU
- RK3066_PD_DBG
- RK3066_PD_GPU
- RK3066_PD_PERI
- RK3066_PD_RTC
- RK3066_PD_SCU
- RK3066_PD_VIDEO
- RK3066_PD_VIO
- RK3066_PLLCON
- RK3066_PLLCON0_NR_MASK
- RK3066_PLLCON0_NR_SHIFT
- RK3066_PLLCON0_OD_MASK
- RK3066_PLLCON0_OD_SHIFT
- RK3066_PLLCON1_NF_MASK
- RK3066_PLLCON1_NF_SHIFT
- RK3066_PLLCON2_NB_MASK
- RK3066_PLLCON2_NB_SHIFT
- RK3066_PLLCON3_BYPASS
- RK3066_PLLCON3_PWRDOWN
- RK3066_PLLCON3_RESET
- RK3066_PLL_RATE
- RK3066_PLL_RATE_NB
- RK3066_PLL_RESET_DELAY
- RK3066_REG_CFG_DONE
- RK3066_SYS_CTRL0
- RK3066_SYS_CTRL1
- RK3066_WIN0_ACT_INFO
- RK3066_WIN0_CBR_MST0
- RK3066_WIN0_CBR_MST1
- RK3066_WIN0_COLOR_KEY_CTRL
- RK3066_WIN0_DSP_INFO
- RK3066_WIN0_DSP_ST
- RK3066_WIN0_SCL_FACTOR_CBR
- RK3066_WIN0_SCL_FACTOR_YRGB
- RK3066_WIN0_SCL_OFFSET
- RK3066_WIN0_VIR
- RK3066_WIN0_YRGB_MST0
- RK3066_WIN0_YRGB_MST1
- RK3066_WIN1_ACT_INFO
- RK3066_WIN1_CBR_MST
- RK3066_WIN1_COLOR_KEY_CTRL
- RK3066_WIN1_DSP_INFO
- RK3066_WIN1_DSP_ST
- RK3066_WIN1_SCL_FACTOR_CBR
- RK3066_WIN1_SCL_FACTOR_YRGB
- RK3066_WIN1_SCL_OFFSET
- RK3066_WIN1_VIR
- RK3066_WIN1_YRGB_MST
- RK3066_WIN2_COLOR_KEY_CTRL
- RK3066_WIN2_DSP_INFO
- RK3066_WIN2_DSP_ST
- RK3066_WIN2_LUT_ADDR
- RK3066_WIN2_MST
- RK3066_WIN2_VIR
- RK3126_WIN1_DSP_INFO
- RK3126_WIN1_DSP_ST
- RK3126_WIN1_MST
- RK3128
- RK3128_CLKSEL1
- RK3128_CPUCLK_RATE
- RK3128_DIV_ACLK_MASK
- RK3128_DIV_ACLK_SHIFT
- RK3128_DIV_CPU_MASK
- RK3128_DIV_CPU_SHIFT
- RK3128_DIV_HCLK_MASK
- RK3128_DIV_HCLK_SHIFT
- RK3128_DIV_PCLK_MASK
- RK3128_DIV_PCLK_SHIFT
- RK3128_DIV_PERI_MASK
- RK3128_DIV_PERI_SHIFT
- RK3128_GMAC_CLK_125M
- RK3128_GMAC_CLK_25M
- RK3128_GMAC_CLK_2_5M
- RK3128_GMAC_CLK_RX_DL_CFG
- RK3128_GMAC_CLK_TX_DL_CFG
- RK3128_GMAC_FLOW_CTRL
- RK3128_GMAC_FLOW_CTRL_CLR
- RK3128_GMAC_PHY_INTF_SEL_RGMII
- RK3128_GMAC_PHY_INTF_SEL_RMII
- RK3128_GMAC_RMII_CLK_25M
- RK3128_GMAC_RMII_CLK_2_5M
- RK3128_GMAC_RMII_MODE
- RK3128_GMAC_RMII_MODE_CLR
- RK3128_GMAC_RXCLK_DLY_DISABLE
- RK3128_GMAC_RXCLK_DLY_ENABLE
- RK3128_GMAC_SPEED_100M
- RK3128_GMAC_SPEED_10M
- RK3128_GMAC_TXCLK_DLY_DISABLE
- RK3128_GMAC_TXCLK_DLY_ENABLE
- RK3128_GRF_MAC_CON0
- RK3128_GRF_MAC_CON1
- RK3128_GRF_SOC_CON0
- RK3128_GRF_SOC_STATUS0
- RK3128_PD_CORE
- RK3128_PD_GPU
- RK3128_PD_MSCH
- RK3128_PD_VIDEO
- RK3128_PD_VIO
- RK3128_PULL_OFFSET
- RK3188
- RK3188_CLKSEL1
- RK3188_CPUCLK_RATE
- RK3188_DIV_ACLK_CORE_MASK
- RK3188_DIV_ACLK_CORE_SHIFT
- RK3188_DSP_CTRL0
- RK3188_DSP_CTRL1
- RK3188_DSP_HACT_ST_END
- RK3188_DSP_HTOTAL_HS_END
- RK3188_DSP_VACT_ST_END
- RK3188_DSP_VTOTAL_VS_END
- RK3188_GRF_SOC_STATUS
- RK3188_INT_STATUS
- RK3188_PD_A9_0
- RK3188_PD_A9_1
- RK3188_PD_A9_2
- RK3188_PD_A9_3
- RK3188_PD_ALIVE
- RK3188_PD_CPU
- RK3188_PD_DBG
- RK3188_PD_GPU
- RK3188_PD_PERI
- RK3188_PD_RTC
- RK3188_PD_SCU
- RK3188_PD_VIDEO
- RK3188_PD_VIO
- RK3188_PULL_BANK_STRIDE
- RK3188_PULL_BITS_PER_PIN
- RK3188_PULL_OFFSET
- RK3188_PULL_PINS_PER_REG
- RK3188_PULL_PMU_OFFSET
- RK3188_REG_CFG_DONE
- RK3188_SYS_CTRL
- RK3188_UOC0_CON0
- RK3188_UOC0_CON0_BYPASSDMEN
- RK3188_UOC0_CON0_BYPASSSEL
- RK3188_WIN0_ACT_INFO
- RK3188_WIN0_CBR_MST0
- RK3188_WIN0_CBR_MST1
- RK3188_WIN0_DSP_INFO
- RK3188_WIN0_DSP_ST
- RK3188_WIN0_SCL_FACTOR_CBR
- RK3188_WIN0_SCL_FACTOR_YRGB
- RK3188_WIN0_YRGB_MST0
- RK3188_WIN0_YRGB_MST1
- RK3188_WIN1_DSP_INFO
- RK3188_WIN1_DSP_ST
- RK3188_WIN1_MST
- RK3188_WIN_VIR
- RK3228_AUTO_TERM_RES_CAL_SPEED_14_8
- RK3228_AUTO_TERM_RES_CAL_SPEED_7_0
- RK3228_BANDGAP_ENABLE
- RK3228_BYPASS_AUTO_TERM_RES_CAL
- RK3228_BYPASS_PDATA_EN
- RK3228_BYPASS_PLLPD_EN
- RK3228_BYPASS_PWRON_EN
- RK3228_BYPASS_RXSENSE_EN
- RK3228_CLKSEL1
- RK3228_CPUCLK_RATE
- RK3228_DIV_ACLK_MASK
- RK3228_DIV_ACLK_SHIFT
- RK3228_DIV_CPU_MASK
- RK3228_DIV_CPU_SHIFT
- RK3228_DIV_HCLK_MASK
- RK3228_DIV_HCLK_SHIFT
- RK3228_DIV_PCLK_MASK
- RK3228_DIV_PCLK_SHIFT
- RK3228_DIV_PERI_MASK
- RK3228_DIV_PERI_SHIFT
- RK3228_DRV_GRF_OFFSET
- RK3228_EMMC_CON0
- RK3228_EMMC_CON1
- RK3228_GLB_SRST_FST
- RK3228_GLB_SRST_SND
- RK3228_GMAC_CLK_125M
- RK3228_GMAC_CLK_25M
- RK3228_GMAC_CLK_2_5M
- RK3228_GMAC_CLK_RX_DL_CFG
- RK3228_GMAC_CLK_TX_DL_CFG
- RK3228_GMAC_FLOW_CTRL
- RK3228_GMAC_FLOW_CTRL_CLR
- RK3228_GMAC_PHY_INTF_SEL_RGMII
- RK3228_GMAC_PHY_INTF_SEL_RMII
- RK3228_GMAC_RMII_CLK_25M
- RK3228_GMAC_RMII_CLK_2_5M
- RK3228_GMAC_RMII_MODE
- RK3228_GMAC_RMII_MODE_CLR
- RK3228_GMAC_RXCLK_DLY_DISABLE
- RK3228_GMAC_RXCLK_DLY_ENABLE
- RK3228_GMAC_SPEED_100M
- RK3228_GMAC_SPEED_10M
- RK3228_GMAC_TXCLK_DLY_DISABLE
- RK3228_GMAC_TXCLK_DLY_ENABLE
- RK3228_GRF_CON_MUX
- RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY
- RK3228_GRF_MAC_CON0
- RK3228_GRF_MAC_CON1
- RK3228_GRF_SOC_CON2
- RK3228_GRF_SOC_CON6
- RK3228_GRF_SOC_STATUS0
- RK3228_HDMI_HPD_VSEL
- RK3228_HDMI_SCLIN_MSK
- RK3228_HDMI_SCL_VSEL
- RK3228_HDMI_SDAIN_MSK
- RK3228_HDMI_SDA_VSEL
- RK3228_PCLK_VCO_DIV_5
- RK3228_PCLK_VCO_DIV_5_MASK
- RK3228_PDATAEN_DISABLE
- RK3228_PD_BUS
- RK3228_PD_CORE
- RK3228_PD_GMAC
- RK3228_PD_GPU
- RK3228_PD_MSCH
- RK3228_PD_PERI
- RK3228_PD_RKVDEC
- RK3228_PD_SYS
- RK3228_PD_VIO
- RK3228_PD_VOP
- RK3228_PD_VPU
- RK3228_POST_PLL_CTRL_MANUAL
- RK3228_POST_PLL_FB_DIV_7_0
- RK3228_POST_PLL_FB_DIV_8
- RK3228_POST_PLL_FB_DIV_8_MASK
- RK3228_POST_PLL_LOCK_STATUS
- RK3228_POST_PLL_POST_DIV
- RK3228_POST_PLL_POST_DIV_ENABLE
- RK3228_POST_PLL_POST_DIV_MASK
- RK3228_POST_PLL_POWER_DOWN
- RK3228_POST_PLL_PRE_DIV
- RK3228_POST_PLL_PRE_DIV_MASK
- RK3228_PRE_PLL_FB_DIV_7_0
- RK3228_PRE_PLL_FB_DIV_8
- RK3228_PRE_PLL_FB_DIV_8_MASK
- RK3228_PRE_PLL_LOCK_STATUS
- RK3228_PRE_PLL_PCLK_DIV_A
- RK3228_PRE_PLL_PCLK_DIV_A_MASK
- RK3228_PRE_PLL_PCLK_DIV_B
- RK3228_PRE_PLL_PCLK_DIV_B_MASK
- RK3228_PRE_PLL_PCLK_DIV_B_SHIFT
- RK3228_PRE_PLL_PCLK_DIV_C
- RK3228_PRE_PLL_PCLK_DIV_C_MASK
- RK3228_PRE_PLL_PCLK_DIV_D
- RK3228_PRE_PLL_PCLK_DIV_D_MASK
- RK3228_PRE_PLL_POWER_DOWN
- RK3228_PRE_PLL_PRE_DIV
- RK3228_PRE_PLL_PRE_DIV_MASK
- RK3228_PRE_PLL_REFCLK_SEL_PCLK
- RK3228_PRE_PLL_TMDSCLK_DIV_A
- RK3228_PRE_PLL_TMDSCLK_DIV_A_MASK
- RK3228_PRE_PLL_TMDSCLK_DIV_B
- RK3228_PRE_PLL_TMDSCLK_DIV_B_MASK
- RK3228_PRE_PLL_TMDSCLK_DIV_C
- RK3228_PRE_PLL_TMDSCLK_DIV_C_MASK
- RK3228_PULL_OFFSET
- RK3228_RXSENSE_CLK_CH_ENABLE
- RK3228_RXSENSE_DATA_CH0_ENABLE
- RK3228_RXSENSE_DATA_CH1_ENABLE
- RK3228_RXSENSE_DATA_CH2_ENABLE
- RK3228_SDIO_CON0
- RK3228_SDIO_CON1
- RK3228_SDMMC_CON0
- RK3228_SDMMC_CON1
- RK3228_TMDS_CH_TA_ENABLE
- RK3228_TMDS_CLK_CH_OUTPUT_SWING
- RK3228_TMDS_CLK_CH_TA
- RK3228_TMDS_DATA_CH0_OUTPUT_SWING
- RK3228_TMDS_DATA_CH0_PRE_EMPHASIS
- RK3228_TMDS_DATA_CH0_PRE_EMPHASIS_MASK
- RK3228_TMDS_DATA_CH0_TA
- RK3228_TMDS_DATA_CH1_OUTPUT_SWING
- RK3228_TMDS_DATA_CH1_PRE_EMPHASIS
- RK3228_TMDS_DATA_CH1_PRE_EMPHASIS_MASK
- RK3228_TMDS_DATA_CH1_TA
- RK3228_TMDS_DATA_CH2_OUTPUT_SWING
- RK3228_TMDS_DATA_CH2_PRE_EMPHASIS
- RK3228_TMDS_DATA_CH2_PRE_EMPHASIS_MASK
- RK3228_TMDS_DATA_CH2_TA
- RK3228_TMDS_DRIVER_ENABLE
- RK3288
- RK3288_ACLK_MAX_FREQ
- RK3288_A_MASK
- RK3288_A_SHIFT
- RK3288_CLKGATE_CON
- RK3288_CLKGEN_DIV
- RK3288_CLKSEL0
- RK3288_CLKSEL37
- RK3288_CLKSEL_CON
- RK3288_CPUCLK_RATE
- RK3288_CSB
- RK3288_DIV_ACLK_CORE_M0_MASK
- RK3288_DIV_ACLK_CORE_M0_SHIFT
- RK3288_DIV_ACLK_CORE_MP_MASK
- RK3288_DIV_ACLK_CORE_MP_SHIFT
- RK3288_DIV_ATCLK_MASK
- RK3288_DIV_ATCLK_SHIFT
- RK3288_DIV_L2RAM_MASK
- RK3288_DIV_L2RAM_SHIFT
- RK3288_DIV_PCLK_DBGPRE_MASK
- RK3288_DIV_PCLK_DBGPRE_SHIFT
- RK3288_DP
- RK3288_DRV_BANK_STRIDE
- RK3288_DRV_BITS_PER_PIN
- RK3288_DRV_GRF_OFFSET
- RK3288_DRV_PINS_PER_REG
- RK3288_DRV_PMU_OFFSET
- RK3288_DSI0_LCDC_SEL
- RK3288_DSI1_LCDC_SEL
- RK3288_DSP_BG
- RK3288_DSP_CTRL0
- RK3288_DSP_CTRL1
- RK3288_DSP_HACT_ST_END
- RK3288_DSP_HTOTAL_HS_END
- RK3288_DSP_VACT_ST_END
- RK3288_DSP_VACT_ST_END_F1
- RK3288_DSP_VS_ST_END_F1
- RK3288_DSP_VTOTAL_VS_END
- RK3288_EDP_LCDC_SEL
- RK3288_EMMC_CON0
- RK3288_EMMC_CON1
- RK3288_GLB_SRST_FST
- RK3288_GLB_SRST_SND
- RK3288_GMAC_CLK_125M
- RK3288_GMAC_CLK_25M
- RK3288_GMAC_CLK_2_5M
- RK3288_GMAC_CLK_RX_DL_CFG
- RK3288_GMAC_CLK_TX_DL_CFG
- RK3288_GMAC_FLOW_CTRL
- RK3288_GMAC_FLOW_CTRL_CLR
- RK3288_GMAC_PHY_INTF_SEL_RGMII
- RK3288_GMAC_PHY_INTF_SEL_RMII
- RK3288_GMAC_RMII_CLK_25M
- RK3288_GMAC_RMII_CLK_2_5M
- RK3288_GMAC_RMII_MODE
- RK3288_GMAC_RMII_MODE_CLR
- RK3288_GMAC_RXCLK_DLY_DISABLE
- RK3288_GMAC_RXCLK_DLY_ENABLE
- RK3288_GMAC_SPEED_100M
- RK3288_GMAC_SPEED_10M
- RK3288_GMAC_TXCLK_DLY_DISABLE
- RK3288_GMAC_TXCLK_DLY_ENABLE
- RK3288_GRF_GPIO6C_IOMUX
- RK3288_GRF_SOC_CON
- RK3288_GRF_SOC_CON0
- RK3288_GRF_SOC_CON1
- RK3288_GRF_SOC_CON2
- RK3288_GRF_SOC_CON3
- RK3288_GRF_SOC_CON6
- RK3288_GRF_SOC_STATUS1
- RK3288_HDMI_LCDC_SEL
- RK3288_HWC_CTRL0
- RK3288_HWC_CTRL1
- RK3288_HWC_DSP_ST
- RK3288_HWC_DST_ALPHA_CTRL
- RK3288_HWC_FADING_CTRL
- RK3288_HWC_MST
- RK3288_HWC_SRC_ALPHA_CTRL
- RK3288_INTR_CTRL0
- RK3288_INTR_CTRL1
- RK3288_LOAD
- RK3288_LVDS_CFG_REG21
- RK3288_LVDS_CFG_REG21_TX_DISABLE
- RK3288_LVDS_CFG_REG21_TX_ENABLE
- RK3288_LVDS_CFG_REGC
- RK3288_LVDS_CFG_REGC_PLL_DISABLE
- RK3288_LVDS_CFG_REGC_PLL_ENABLE
- RK3288_LVDS_CH0_REG0
- RK3288_LVDS_CH0_REG0_LANE0_EN
- RK3288_LVDS_CH0_REG0_LANE1_EN
- RK3288_LVDS_CH0_REG0_LANE2_EN
- RK3288_LVDS_CH0_REG0_LANE3_EN
- RK3288_LVDS_CH0_REG0_LANE4_EN
- RK3288_LVDS_CH0_REG0_LANECK_EN
- RK3288_LVDS_CH0_REG0_LVDS_EN
- RK3288_LVDS_CH0_REG0_TTL_EN
- RK3288_LVDS_CH0_REG1
- RK3288_LVDS_CH0_REG1_LANE0_BIAS
- RK3288_LVDS_CH0_REG1_LANE1_BIAS
- RK3288_LVDS_CH0_REG1_LANE2_BIAS
- RK3288_LVDS_CH0_REG1_LANE3_BIAS
- RK3288_LVDS_CH0_REG1_LANE4_BIAS
- RK3288_LVDS_CH0_REG1_LANECK_BIAS
- RK3288_LVDS_CH0_REG2
- RK3288_LVDS_CH0_REG20
- RK3288_LVDS_CH0_REG20_LSB
- RK3288_LVDS_CH0_REG20_MSB
- RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE
- RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE
- RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE
- RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE
- RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE
- RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE
- RK3288_LVDS_CH0_REG2_PLL_FBDIV8
- RK3288_LVDS_CH0_REG2_RESERVE_ON
- RK3288_LVDS_CH0_REG3
- RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK
- RK3288_LVDS_CH0_REG4
- RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE
- RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE
- RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE
- RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE
- RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE
- RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE
- RK3288_LVDS_CH0_REG5
- RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA
- RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA
- RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA
- RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA
- RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA
- RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA
- RK3288_LVDS_CH0_REGD
- RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK
- RK3288_LVDS_CH1_OFFSET
- RK3288_LVDS_PLL_FBDIV_REG2
- RK3288_LVDS_PLL_FBDIV_REG3
- RK3288_LVDS_PLL_PREDIV_REGD
- RK3288_LVDS_SOC_CON6_SEL_VOP_LIT
- RK3288_MCU_CTRL
- RK3288_MISC_CON
- RK3288_MMC_CLKGEN_DIV
- RK3288_MODE_CON
- RK3288_PD_A17_0
- RK3288_PD_A17_1
- RK3288_PD_A17_2
- RK3288_PD_A17_3
- RK3288_PD_ALIVE
- RK3288_PD_BUS
- RK3288_PD_DEBUG
- RK3288_PD_GPU
- RK3288_PD_HEVC
- RK3288_PD_MEM
- RK3288_PD_PERI
- RK3288_PD_PMU
- RK3288_PD_SCU
- RK3288_PD_VIDEO
- RK3288_PD_VIO
- RK3288_PGENB
- RK3288_PLL_CON
- RK3288_PMU_CORE_PWRDWN_CNT
- RK3288_PMU_CORE_PWRUP_CNT
- RK3288_PMU_DDR0IO_PWRON_CNT
- RK3288_PMU_DDR1IO_PWRON_CNT
- RK3288_PMU_GPU_PWRDWN_CNT
- RK3288_PMU_GPU_PWRUP_CNT
- RK3288_PMU_OSC_CNT
- RK3288_PMU_PLL_CNT
- RK3288_PMU_PWRMODE_CON
- RK3288_PMU_PWRMODE_CON1
- RK3288_PMU_STABL_CNT
- RK3288_PMU_WAKEUP_CFG0
- RK3288_PMU_WAKEUP_CFG1
- RK3288_PMU_WAKEUP_RST_CLR_CNT
- RK3288_POST_DSP_HACT_INFO
- RK3288_POST_DSP_VACT_INFO
- RK3288_POST_DSP_VACT_INFO_F1
- RK3288_POST_SCL_CTRL
- RK3288_POST_SCL_FACTOR_YRGB
- RK3288_PULL_OFFSET
- RK3288_REG_CFG_DONE
- RK3288_SDIO0_CON0
- RK3288_SDIO0_CON1
- RK3288_SDIO1_CON0
- RK3288_SDIO1_CON1
- RK3288_SDMMC_CON0
- RK3288_SDMMC_CON1
- RK3288_SGRF_CPU_CON0
- RK3288_SGRF_FAST_BOOT_ADDR
- RK3288_SGRF_SOC_CON0
- RK3288_SOC_CON2
- RK3288_SOC_CON2_FLASH0
- RK3288_SOC_FLASH_SUPPLY_NUM
- RK3288_SOFTRST_CON
- RK3288_STROBE
- RK3288_SYS_CTRL
- RK3288_SYS_CTRL1
- RK3288_TIMER6_7_PHYS
- RK3288_UOC0_CON3
- RK3288_UOC0_CON3_BYPASSDMEN
- RK3288_UOC0_CON3_BYPASSSEL
- RK3288_VERSION_INFO
- RK3288_VPU_ENC_FMT_UYVY422
- RK3288_VPU_ENC_FMT_YUV420P
- RK3288_VPU_ENC_FMT_YUV420SP
- RK3288_VPU_ENC_FMT_YUYV422
- RK3288_WIN0_ACT_INFO
- RK3288_WIN0_CBR_MST
- RK3288_WIN0_COLOR_KEY
- RK3288_WIN0_CTRL0
- RK3288_WIN0_CTRL1
- RK3288_WIN0_CTRL2
- RK3288_WIN0_DSP_INFO
- RK3288_WIN0_DSP_ST
- RK3288_WIN0_DST_ALPHA_CTRL
- RK3288_WIN0_FADING_CTRL
- RK3288_WIN0_SCL_FACTOR_CBR
- RK3288_WIN0_SCL_FACTOR_YRGB
- RK3288_WIN0_SCL_OFFSET
- RK3288_WIN0_SRC_ALPHA_CTRL
- RK3288_WIN0_VIR
- RK3288_WIN0_YRGB_MST
- RK3288_WIN1_ACT_INFO
- RK3288_WIN1_CBR_MST
- RK3288_WIN1_COLOR_KEY
- RK3288_WIN1_CTRL0
- RK3288_WIN1_CTRL1
- RK3288_WIN1_DSP_INFO
- RK3288_WIN1_DSP_ST
- RK3288_WIN1_DST_ALPHA_CTRL
- RK3288_WIN1_FADING_CTRL
- RK3288_WIN1_SCL_FACTOR_CBR
- RK3288_WIN1_SCL_FACTOR_YRGB
- RK3288_WIN1_SCL_OFFSET
- RK3288_WIN1_SRC_ALPHA_CTRL
- RK3288_WIN1_VIR
- RK3288_WIN1_YRGB_MST
- RK3288_WIN2_COLOR_KEY
- RK3288_WIN2_CTRL0
- RK3288_WIN2_CTRL1
- RK3288_WIN2_DSP_INFO0
- RK3288_WIN2_DSP_INFO1
- RK3288_WIN2_DSP_INFO2
- RK3288_WIN2_DSP_INFO3
- RK3288_WIN2_DSP_ST0
- RK3288_WIN2_DSP_ST1
- RK3288_WIN2_DSP_ST2
- RK3288_WIN2_DSP_ST3
- RK3288_WIN2_DST_ALPHA_CTRL
- RK3288_WIN2_FADING_CTRL
- RK3288_WIN2_MST0
- RK3288_WIN2_MST1
- RK3288_WIN2_MST2
- RK3288_WIN2_MST3
- RK3288_WIN2_SRC_ALPHA_CTRL
- RK3288_WIN2_VIR0_1
- RK3288_WIN2_VIR2_3
- RK3288_WIN3_COLOR_KEY
- RK3288_WIN3_CTRL0
- RK3288_WIN3_CTRL1
- RK3288_WIN3_DSP_INFO0
- RK3288_WIN3_DSP_INFO1
- RK3288_WIN3_DSP_INFO2
- RK3288_WIN3_DSP_INFO3
- RK3288_WIN3_DSP_ST0
- RK3288_WIN3_DSP_ST1
- RK3288_WIN3_DSP_ST2
- RK3288_WIN3_DSP_ST3
- RK3288_WIN3_DST_ALPHA_CTRL
- RK3288_WIN3_FADING_CTRL
- RK3288_WIN3_MST0
- RK3288_WIN3_MST1
- RK3288_WIN3_MST2
- RK3288_WIN3_MST3
- RK3288_WIN3_SRC_ALPHA_CTRL
- RK3288_WIN3_VIR0_1
- RK3288_WIN3_VIR2_3
- RK3308_CLKGATE_CON
- RK3308_CLKSEL0
- RK3308_CLKSEL_CON
- RK3308_CPUCLK_RATE
- RK3308_DIV_ACLKM_MASK
- RK3308_DIV_ACLKM_SHIFT
- RK3308_DIV_PCLK_DBG_MASK
- RK3308_DIV_PCLK_DBG_SHIFT
- RK3308_EMMC_CON0
- RK3308_EMMC_CON1
- RK3308_GLB_SRST_FST
- RK3308_GRF_SOC_STATUS0
- RK3308_MODE_CON
- RK3308_PLL_CON
- RK3308_SDIO_CON0
- RK3308_SDIO_CON1
- RK3308_SDMMC_CON0
- RK3308_SDMMC_CON1
- RK3308_SOFTRST_CON
- RK3328_AUTO_CTRL
- RK3328_AUTO_ENB
- RK3328_AUTO_GATING_EN
- RK3328_AUTO_RD
- RK3328_BANDGAP_ENABLE
- RK3328_BCSH_BCS
- RK3328_BCSH_COLOR_BAR
- RK3328_BCSH_CTRL
- RK3328_BCSH_H
- RK3328_BLANKING_VALUE
- RK3328_BYPASS_PDATA_EN
- RK3328_BYPASS_PLLPD_EN
- RK3328_BYPASS_POWERON_EN
- RK3328_BYPASS_RXSENSE_EN
- RK3328_BYPASS_TERM_RESISTOR_CALIB
- RK3328_CLKGATE_CON
- RK3328_CLKSEL1
- RK3328_CLKSEL_CON
- RK3328_CPUCLK_RATE
- RK3328_DBG_DATAO
- RK3328_DBG_DATAO_2
- RK3328_DBG_PERF_LATENCY_CTRL0
- RK3328_DBG_PERF_RD_LATENCY_SAMP_NUM0
- RK3328_DBG_PERF_RD_LATENCY_THR_NUM0
- RK3328_DBG_PERF_RD_MAX_LATENCY_NUM0
- RK3328_DBG_POST_REG0
- RK3328_DBG_POST_RESERVED
- RK3328_DBG_WIN0_REG0
- RK3328_DBG_WIN0_REG1
- RK3328_DBG_WIN0_REG2
- RK3328_DBG_WIN0_RESERVED
- RK3328_DBG_WIN1_REG0
- RK3328_DBG_WIN1_REG1
- RK3328_DBG_WIN1_REG2
- RK3328_DBG_WIN1_RESERVED
- RK3328_DBG_WIN2_REG0
- RK3328_DBG_WIN2_REG1
- RK3328_DBG_WIN2_REG2
- RK3328_DBG_WIN2_RESERVED
- RK3328_DBG_WIN3_REG0
- RK3328_DBG_WIN3_REG1
- RK3328_DBG_WIN3_REG2
- RK3328_DBG_WIN3_RESERVED
- RK3328_DIV_ACLKM_MASK
- RK3328_DIV_ACLKM_SHIFT
- RK3328_DIV_PCLK_DBG_MASK
- RK3328_DIV_PCLK_DBG_SHIFT
- RK3328_DOUT
- RK3328_DSP_BG
- RK3328_DSP_CTRL0
- RK3328_DSP_CTRL1
- RK3328_DSP_HACT_ST_END
- RK3328_DSP_HTOTAL_HS_END
- RK3328_DSP_VACT_ST_END
- RK3328_DSP_VACT_ST_END_F1
- RK3328_DSP_VS_ST_END_F1
- RK3328_DSP_VTOTAL_VS_END
- RK3328_EETF_OETF_Y0
- RK3328_EETF_OETF_Y1
- RK3328_EMMC_CON0
- RK3328_EMMC_CON1
- RK3328_EOTF_OETF_Y0
- RK3328_EOTF_OETF_Y1
- RK3328_EOTF_OETF_Y64
- RK3328_ESD_DETECT_240MV
- RK3328_ESD_DETECT_260MV
- RK3328_ESD_DETECT_280MV
- RK3328_ESD_DETECT_340MV
- RK3328_ESD_DETECT_MASK
- RK3328_FRC_LOWER01_0
- RK3328_FRC_LOWER01_1
- RK3328_FRC_LOWER10_0
- RK3328_FRC_LOWER10_1
- RK3328_FRC_LOWER11_0
- RK3328_FRC_LOWER11_1
- RK3328_GLB_SRST_FST
- RK3328_GLB_SRST_SND
- RK3328_GMAC_CLK_125M
- RK3328_GMAC_CLK_25M
- RK3328_GMAC_CLK_2_5M
- RK3328_GMAC_CLK_RX_DL_CFG
- RK3328_GMAC_CLK_TX_DL_CFG
- RK3328_GMAC_FLOW_CTRL
- RK3328_GMAC_FLOW_CTRL_CLR
- RK3328_GMAC_PHY_INTF_SEL_RGMII
- RK3328_GMAC_PHY_INTF_SEL_RMII
- RK3328_GMAC_RMII_CLK_25M
- RK3328_GMAC_RMII_CLK_2_5M
- RK3328_GMAC_RMII_MODE
- RK3328_GMAC_RMII_MODE_CLR
- RK3328_GMAC_RXCLK_DLY_DISABLE
- RK3328_GMAC_RXCLK_DLY_ENABLE
- RK3328_GMAC_SPEED_100M
- RK3328_GMAC_SPEED_10M
- RK3328_GMAC_TXCLK_DLY_DISABLE
- RK3328_GMAC_TXCLK_DLY_ENABLE
- RK3328_GRFCLKSEL_CON
- RK3328_GRF_MACPHY_CON1
- RK3328_GRF_MAC_CON0
- RK3328_GRF_MAC_CON1
- RK3328_GRF_MAC_CON2
- RK3328_GRF_SOC_CON10
- RK3328_GRF_SOC_CON2
- RK3328_GRF_SOC_CON3
- RK3328_GRF_SOC_CON4
- RK3328_GRF_SOC_STATUS0
- RK3328_HDMI_CEC5V_GRF
- RK3328_HDMI_CEC_5V
- RK3328_HDMI_HPD5V_GRF
- RK3328_HDMI_HPD_5V
- RK3328_HDMI_HPD_IOE
- RK3328_HDMI_HPD_SARADC
- RK3328_HDMI_SCL5V_GRF
- RK3328_HDMI_SCLIN_MSK
- RK3328_HDMI_SCL_5V
- RK3328_HDMI_SDA5V_GRF
- RK3328_HDMI_SDAIN_MSK
- RK3328_HDMI_SDA_5V
- RK3328_HDR2SDR_CTRL
- RK3328_HDR2SDR_DST_RANGE
- RK3328_HDR2SDR_NORMFACCGAMMA
- RK3328_HDR2SDR_NORMFACEETF
- RK3328_HDR2SDR_SRC_RANGE
- RK3328_HIFI
- RK3328_HWC_CTRL0
- RK3328_HWC_CTRL1
- RK3328_HWC_DSP_ST
- RK3328_HWC_DST_ALPHA_CTRL
- RK3328_HWC_FADING_CTRL
- RK3328_HWC_LUT_ADDR
- RK3328_HWC_MST
- RK3328_HWC_RESERVED1
- RK3328_HWC_SRC_ALPHA_CTRL
- RK3328_INTR_CLEAR0
- RK3328_INTR_CLEAR1
- RK3328_INTR_EN0
- RK3328_INTR_EN1
- RK3328_INTR_RAW_STATUS0
- RK3328_INTR_RAW_STATUS1
- RK3328_INTR_STATUS0
- RK3328_INTR_STATUS1
- RK3328_INT_AGND_LOW_PULSE_LOCKED
- RK3328_INT_AGND_VSS_ESD_DET
- RK3328_INT_FINISH
- RK3328_INT_POL_HIGH
- RK3328_INT_RXSENSE_LOW_PULSE_LOCKED
- RK3328_INT_STATUS
- RK3328_INT_TMDS_CLK
- RK3328_INT_TMDS_D0
- RK3328_INT_TMDS_D1
- RK3328_INT_TMDS_D2
- RK3328_INT_VSS_AGND_ESD_DET
- RK3328_LINE_FLAG
- RK3328_MACPHY_RMII_MODE
- RK3328_MISC_CON
- RK3328_MODE_CON
- RK3328_OETF_DX_DXPOW1
- RK3328_OETF_DX_DXPOW64
- RK3328_OETF_XN1
- RK3328_OETF_XN63
- RK3328_PCLK_VCO_DIV_5
- RK3328_PCLK_VCO_DIV_5_MASK
- RK3328_PDATA_EN
- RK3328_PD_BUS
- RK3328_PD_CORE
- RK3328_PD_GPU
- RK3328_PD_HEVC
- RK3328_PD_MSCH
- RK3328_PD_PERI
- RK3328_PD_SYS
- RK3328_PD_VIDEO
- RK3328_PD_VIO
- RK3328_PD_VPU
- RK3328_PLL_CON
- RK3328_POST_DSP_HACT_INFO
- RK3328_POST_DSP_VACT_INFO
- RK3328_POST_DSP_VACT_INFO_F1
- RK3328_POST_PLL_FB_DIV_7_0
- RK3328_POST_PLL_FB_DIV_8
- RK3328_POST_PLL_LOCK_STATUS
- RK3328_POST_PLL_POST_DIV_2
- RK3328_POST_PLL_POST_DIV_4
- RK3328_POST_PLL_POST_DIV_8
- RK3328_POST_PLL_POST_DIV_ENABLE
- RK3328_POST_PLL_POST_DIV_MASK
- RK3328_POST_PLL_POWER_DOWN
- RK3328_POST_PLL_PRE_DIV
- RK3328_POST_PLL_REFCLK_SEL_TMDS
- RK3328_POST_RESERVED
- RK3328_POST_SCL_CTRL
- RK3328_POST_SCL_FACTOR_YRGB
- RK3328_PRE_PLL_FB_DIV_11_8
- RK3328_PRE_PLL_FB_DIV_11_8_MASK
- RK3328_PRE_PLL_FB_DIV_7_0
- RK3328_PRE_PLL_FRAC_DIV_15_8
- RK3328_PRE_PLL_FRAC_DIV_23_16
- RK3328_PRE_PLL_FRAC_DIV_7_0
- RK3328_PRE_PLL_FRAC_DIV_DISABLE
- RK3328_PRE_PLL_LOCK_STATUS
- RK3328_PRE_PLL_PCLK_DIV_A
- RK3328_PRE_PLL_PCLK_DIV_A_MASK
- RK3328_PRE_PLL_PCLK_DIV_B
- RK3328_PRE_PLL_PCLK_DIV_B_MASK
- RK3328_PRE_PLL_PCLK_DIV_B_SHIFT
- RK3328_PRE_PLL_PCLK_DIV_C
- RK3328_PRE_PLL_PCLK_DIV_C_MASK
- RK3328_PRE_PLL_PCLK_DIV_C_SHIFT
- RK3328_PRE_PLL_PCLK_DIV_D
- RK3328_PRE_PLL_PCLK_DIV_D_MASK
- RK3328_PRE_PLL_POWER_DOWN
- RK3328_PRE_PLL_PRE_DIV
- RK3328_PRE_PLL_PRE_DIV_MASK
- RK3328_PRE_PLL_TMDSCLK_DIV_A
- RK3328_PRE_PLL_TMDSCLK_DIV_A_MASK
- RK3328_PRE_PLL_TMDSCLK_DIV_B
- RK3328_PRE_PLL_TMDSCLK_DIV_B_MASK
- RK3328_PRE_PLL_TMDSCLK_DIV_C
- RK3328_PRE_PLL_TMDSCLK_DIV_C_MASK
- RK3328_REG_CFG_DONE
- RK3328_RESERVED0001
- RK3328_RESERVED0002
- RK3328_RESERVED0003
- RK3328_SAT_Y0
- RK3328_SAT_Y1
- RK3328_SAT_Y8
- RK3328_SCHMITT_BANK_STRIDE
- RK3328_SCHMITT_BITS_PER_PIN
- RK3328_SCHMITT_GRF_OFFSET
- RK3328_SCHMITT_PINS_PER_REG
- RK3328_SDIO_CON0
- RK3328_SDIO_CON1
- RK3328_SDMMC_CON0
- RK3328_SDMMC_CON1
- RK3328_SDMMC_EXT_CON0
- RK3328_SDMMC_EXT_CON1
- RK3328_SDR2HDR_CTRL
- RK3328_SECURE_SIZES
- RK3328_SOC_CON4
- RK3328_SOC_CON4_VCCIO2
- RK3328_SOC_VCCIO2_SUPPLY_NUM
- RK3328_SOFTRST_CON
- RK3328_SPREAD_SPECTRUM_MOD_DISABLE
- RK3328_SPREAD_SPECTRUM_MOD_DOWN
- RK3328_SYS_CTRL
- RK3328_SYS_CTRL1
- RK3328_TERM_RESISTOR_100
- RK3328_TERM_RESISTOR_50
- RK3328_TERM_RESISTOR_62_5
- RK3328_TERM_RESISTOR_75
- RK3328_TERM_RESISTOR_CALIB_SPEED_14_8
- RK3328_TERM_RESISTOR_CALIB_SPEED_7_0
- RK3328_TMDS_CLK_DRIVER_EN
- RK3328_TMDS_D0_DRIVER_EN
- RK3328_TMDS_D1_DRIVER_EN
- RK3328_TMDS_D2_DRIVER_EN
- RK3328_TMDS_DRIVER_ENABLE
- RK3328_TMDS_TERM_RESIST_1000
- RK3328_TMDS_TERM_RESIST_150
- RK3328_TMDS_TERM_RESIST_2000
- RK3328_TMDS_TERM_RESIST_300
- RK3328_TMDS_TERM_RESIST_600
- RK3328_TMDS_TERM_RESIST_75
- RK3328_TMDS_TERM_RESIST_MASK
- RK3328_VERSION_INFO
- RK3328_VOP_STATUS
- RK3328_WIN0_ACT_INFO
- RK3328_WIN0_CBR_MST
- RK3328_WIN0_COLOR_KEY
- RK3328_WIN0_CTRL0
- RK3328_WIN0_CTRL1
- RK3328_WIN0_CTRL2
- RK3328_WIN0_DSP_BG
- RK3328_WIN0_DSP_INFO
- RK3328_WIN0_DSP_ST
- RK3328_WIN0_DST_ALPHA_CTRL
- RK3328_WIN0_FADING_CTRL
- RK3328_WIN0_SCL_FACTOR_CBR
- RK3328_WIN0_SCL_FACTOR_YRGB
- RK3328_WIN0_SCL_OFFSET
- RK3328_WIN0_SRC_ALPHA_CTRL
- RK3328_WIN0_VIR
- RK3328_WIN0_YRGB_MST
- RK3328_WIN1_ACT_INFO
- RK3328_WIN1_CBR_MST
- RK3328_WIN1_COLOR_KEY
- RK3328_WIN1_CTRL0
- RK3328_WIN1_CTRL1
- RK3328_WIN1_CTRL2
- RK3328_WIN1_DSP_BG
- RK3328_WIN1_DSP_INFO
- RK3328_WIN1_DSP_ST
- RK3328_WIN1_DST_ALPHA_CTRL
- RK3328_WIN1_FADING_CTRL
- RK3328_WIN1_SCL_FACTOR_CBR
- RK3328_WIN1_SCL_FACTOR_YRGB
- RK3328_WIN1_SCL_OFFSET
- RK3328_WIN1_SRC_ALPHA_CTRL
- RK3328_WIN1_VIR
- RK3328_WIN1_YRGB_MST
- RK3328_WIN2_ACT_INFO
- RK3328_WIN2_CBR_MST
- RK3328_WIN2_COLOR_KEY
- RK3328_WIN2_CTRL0
- RK3328_WIN2_CTRL1
- RK3328_WIN2_CTRL2
- RK3328_WIN2_DSP_INFO
- RK3328_WIN2_DSP_ST
- RK3328_WIN2_DST_ALPHA_CTRL
- RK3328_WIN2_FADING_CTRL
- RK3328_WIN2_SCL_FACTOR_CBR
- RK3328_WIN2_SCL_FACTOR_YRGB
- RK3328_WIN2_SCL_OFFSET
- RK3328_WIN2_SRC_ALPHA_CTRL
- RK3328_WIN2_VIR
- RK3328_WIN2_YRGB_MST
- RK3328_WIN3_ACT_INFO
- RK3328_WIN3_CBR_MST
- RK3328_WIN3_COLOR_KEY
- RK3328_WIN3_CTRL0
- RK3328_WIN3_CTRL1
- RK3328_WIN3_CTRL2
- RK3328_WIN3_DSP_INFO
- RK3328_WIN3_DSP_ST
- RK3328_WIN3_DST_ALPHA_CTRL
- RK3328_WIN3_FADING_CTRL
- RK3328_WIN3_SCL_FACTOR_CBR
- RK3328_WIN3_SCL_FACTOR_YRGB
- RK3328_WIN3_SCL_OFFSET
- RK3328_WIN3_SRC_ALPHA_CTRL
- RK3328_WIN3_VIR
- RK3328_WIN3_YRGB_MST
- RK3366_BCSH_BCS
- RK3366_BCSH_COLOR_BAR
- RK3366_BCSH_CTRL
- RK3366_BCSH_H
- RK3366_BLANKING_VALUE
- RK3366_CABC_CTRL0
- RK3366_CABC_CTRL1
- RK3366_CABC_CTRL2
- RK3366_CABC_CTRL3
- RK3366_CABC_GAMMA_LUT_ADDR
- RK3366_CABC_GAUSS_LINE0_0
- RK3366_CABC_GAUSS_LINE0_1
- RK3366_CABC_GAUSS_LINE1_0
- RK3366_CABC_GAUSS_LINE1_1
- RK3366_CABC_GAUSS_LINE2_0
- RK3366_CABC_GAUSS_LINE2_1
- RK3366_DSP_BG
- RK3366_DSP_CTRL0
- RK3366_DSP_CTRL1
- RK3366_DSP_HACT_ST_END
- RK3366_DSP_HTOTAL_HS_END
- RK3366_DSP_VACT_ST_END
- RK3366_DSP_VACT_ST_END_F1
- RK3366_DSP_VS_ST_END_F1
- RK3366_DSP_VTOTAL_VS_END
- RK3366_FRC_LOWER01_0
- RK3366_FRC_LOWER01_1
- RK3366_FRC_LOWER10_0
- RK3366_FRC_LOWER10_1
- RK3366_FRC_LOWER11_0
- RK3366_FRC_LOWER11_1
- RK3366_GAMMA0_LUT_ADDR
- RK3366_GAMMA1_LUT_ADDR
- RK3366_GMAC_CLK_125M
- RK3366_GMAC_CLK_25M
- RK3366_GMAC_CLK_2_5M
- RK3366_GMAC_CLK_RX_DL_CFG
- RK3366_GMAC_CLK_TX_DL_CFG
- RK3366_GMAC_FLOW_CTRL
- RK3366_GMAC_FLOW_CTRL_CLR
- RK3366_GMAC_PHY_INTF_SEL_RGMII
- RK3366_GMAC_PHY_INTF_SEL_RMII
- RK3366_GMAC_RMII_CLK_25M
- RK3366_GMAC_RMII_CLK_2_5M
- RK3366_GMAC_RMII_MODE
- RK3366_GMAC_RMII_MODE_CLR
- RK3366_GMAC_RXCLK_DLY_DISABLE
- RK3366_GMAC_RXCLK_DLY_ENABLE
- RK3366_GMAC_SPEED_100M
- RK3366_GMAC_SPEED_10M
- RK3366_GMAC_TXCLK_DLY_DISABLE
- RK3366_GMAC_TXCLK_DLY_ENABLE
- RK3366_GRF_SOC_CON6
- RK3366_GRF_SOC_CON7
- RK3366_HWC_CTRL0
- RK3366_HWC_CTRL1
- RK3366_HWC_DSP_ST
- RK3366_HWC_DST_ALPHA_CTRL
- RK3366_HWC_FADING_CTRL
- RK3366_HWC_LUT_ADDR
- RK3366_HWC_MST
- RK3366_HWC_RESERVED1
- RK3366_HWC_SRC_ALPHA_CTRL
- RK3366_INTR_CLEAR0
- RK3366_INTR_CLEAR1
- RK3366_INTR_EN0
- RK3366_INTR_EN1
- RK3366_INTR_RAW_STATUS0
- RK3366_INTR_RAW_STATUS1
- RK3366_INTR_STATUS0
- RK3366_INTR_STATUS1
- RK3366_LINE_FLAG
- RK3366_MCU_BYPASS_RPORT
- RK3366_MCU_BYPASS_WPORT
- RK3366_MCU_CTRL
- RK3366_MMU_AUTO_GATING
- RK3366_MMU_COMMAND
- RK3366_MMU_DTE_ADDR
- RK3366_MMU_INT_CLEAR
- RK3366_MMU_INT_MASK
- RK3366_MMU_INT_RAWSTAT
- RK3366_MMU_INT_STATUS
- RK3366_MMU_PAGE_FAULT_ADDR
- RK3366_MMU_STATUS
- RK3366_MMU_ZAP_ONE_LINE
- RK3366_PD_A53_0
- RK3366_PD_A53_1
- RK3366_PD_A53_2
- RK3366_PD_A53_3
- RK3366_PD_ALIVE
- RK3366_PD_BUS
- RK3366_PD_GPU
- RK3366_PD_PERI
- RK3366_PD_PMU
- RK3366_PD_RKVDEC
- RK3366_PD_VIDEO
- RK3366_PD_VIO
- RK3366_PD_VPU
- RK3366_PD_WIFIBT
- RK3366_POST_DSP_HACT_INFO
- RK3366_POST_DSP_VACT_INFO
- RK3366_POST_DSP_VACT_INFO_F1
- RK3366_POST_RESERVED
- RK3366_POST_SCL_CTRL
- RK3366_POST_SCL_FACTOR_YRGB
- RK3366_PWM_CNT
- RK3366_PWM_CTRL
- RK3366_PWM_DUTY_LPR
- RK3366_PWM_PERIOD_HPR
- RK3366_REG_CFG_DONE
- RK3366_SYS_CTRL
- RK3366_SYS_CTRL1
- RK3366_VERSION_INFO
- RK3366_VOP_STATUS
- RK3366_WB_CBR_MST
- RK3366_WB_CTRL0
- RK3366_WB_CTRL1
- RK3366_WB_YRGB_MST
- RK3366_WIN0_ACT_INFO
- RK3366_WIN0_CBR_MST
- RK3366_WIN0_COLOR_KEY
- RK3366_WIN0_CTRL0
- RK3366_WIN0_CTRL1
- RK3366_WIN0_CTRL2
- RK3366_WIN0_DSP_BG
- RK3366_WIN0_DSP_INFO
- RK3366_WIN0_DSP_ST
- RK3366_WIN0_DST_ALPHA_CTRL
- RK3366_WIN0_FADING_CTRL
- RK3366_WIN0_SCL_FACTOR_CBR
- RK3366_WIN0_SCL_FACTOR_YRGB
- RK3366_WIN0_SCL_OFFSET
- RK3366_WIN0_SRC_ALPHA_CTRL
- RK3366_WIN0_VIR
- RK3366_WIN0_YRGB_MST
- RK3366_WIN1_ACT_INFO
- RK3366_WIN1_CBR_MST
- RK3366_WIN1_COLOR_KEY
- RK3366_WIN1_CTRL0
- RK3366_WIN1_CTRL1
- RK3366_WIN1_CTRL2
- RK3366_WIN1_DSP_BG
- RK3366_WIN1_DSP_INFO
- RK3366_WIN1_DSP_ST
- RK3366_WIN1_DST_ALPHA_CTRL
- RK3366_WIN1_FADING_CTRL
- RK3366_WIN1_SCL_FACTOR_CBR
- RK3366_WIN1_SCL_FACTOR_YRGB
- RK3366_WIN1_SCL_OFFSET
- RK3366_WIN1_SRC_ALPHA_CTRL
- RK3366_WIN1_VIR
- RK3366_WIN1_YRGB_MST
- RK3366_WIN2_COLOR_KEY
- RK3366_WIN2_CTRL0
- RK3366_WIN2_CTRL1
- RK3366_WIN2_DSP_BG
- RK3366_WIN2_DSP_INFO0
- RK3366_WIN2_DSP_INFO1
- RK3366_WIN2_DSP_INFO2
- RK3366_WIN2_DSP_INFO3
- RK3366_WIN2_DSP_ST0
- RK3366_WIN2_DSP_ST1
- RK3366_WIN2_DSP_ST2
- RK3366_WIN2_DSP_ST3
- RK3366_WIN2_DST_ALPHA_CTRL
- RK3366_WIN2_FADING_CTRL
- RK3366_WIN2_LUT_ADDR
- RK3366_WIN2_MST0
- RK3366_WIN2_MST1
- RK3366_WIN2_MST2
- RK3366_WIN2_MST3
- RK3366_WIN2_SRC_ALPHA_CTRL
- RK3366_WIN2_VIR0_1
- RK3366_WIN2_VIR2_3
- RK3366_WIN3_COLOR_KEY
- RK3366_WIN3_CTRL0
- RK3366_WIN3_CTRL1
- RK3366_WIN3_DSP_BG
- RK3366_WIN3_DSP_INFO0
- RK3366_WIN3_DSP_INFO1
- RK3366_WIN3_DSP_INFO2
- RK3366_WIN3_DSP_INFO3
- RK3366_WIN3_DSP_ST0
- RK3366_WIN3_DSP_ST1
- RK3366_WIN3_DSP_ST2
- RK3366_WIN3_DSP_ST3
- RK3366_WIN3_DST_ALPHA_CTRL
- RK3366_WIN3_FADING_CTRL
- RK3366_WIN3_LUT_ADDR
- RK3366_WIN3_MST0
- RK3366_WIN3_MST1
- RK3366_WIN3_MST2
- RK3366_WIN3_MST3
- RK3366_WIN3_SRC_ALPHA_CTRL
- RK3366_WIN3_VIR0_1
- RK3366_WIN3_VIR2_3
- RK3368
- RK3368_BCSH_BCS
- RK3368_BCSH_COLOR_BAR
- RK3368_BCSH_CTRL
- RK3368_BCSH_H
- RK3368_CABC_CTRL0
- RK3368_CABC_CTRL1
- RK3368_CABC_CTRL2
- RK3368_CABC_CTRL3
- RK3368_CABC_DEBUG0
- RK3368_CABC_DEBUG1
- RK3368_CABC_DEBUG2
- RK3368_CABC_GAMMA_LUT_ADDR
- RK3368_CABC_GAUSS_LINE0_0
- RK3368_CABC_GAUSS_LINE0_1
- RK3368_CABC_GAUSS_LINE1_0
- RK3368_CABC_GAUSS_LINE1_1
- RK3368_CABC_GAUSS_LINE2_0
- RK3368_CABC_GAUSS_LINE2_1
- RK3368_CLKGATE_CON
- RK3368_CLKSEL0
- RK3368_CLKSEL1
- RK3368_CLKSEL_CON
- RK3368_CPUCLKB_RATE
- RK3368_CPUCLKL_RATE
- RK3368_DBG_REG_000
- RK3368_DBG_REG_001
- RK3368_DBG_REG_002
- RK3368_DBG_REG_003
- RK3368_DBG_REG_004
- RK3368_DBG_REG_005
- RK3368_DBG_REG_006
- RK3368_DBG_REG_007
- RK3368_DBG_REG_008
- RK3368_DBG_REG_016
- RK3368_DBG_REG_017
- RK3368_DBG_REG_018
- RK3368_DBG_REG_019
- RK3368_DBG_REG_020
- RK3368_DBG_REG_021
- RK3368_DBG_REG_022
- RK3368_DBG_REG_023
- RK3368_DBG_REG_028
- RK3368_DIV_ACLKM_MASK
- RK3368_DIV_ACLKM_SHIFT
- RK3368_DIV_ATCLK_MASK
- RK3368_DIV_ATCLK_SHIFT
- RK3368_DIV_PCLK_DBG_MASK
- RK3368_DIV_PCLK_DBG_SHIFT
- RK3368_DRV_GRF_OFFSET
- RK3368_DRV_PMU_OFFSET
- RK3368_DSP_BG
- RK3368_DSP_CTRL0
- RK3368_DSP_CTRL1
- RK3368_DSP_HACT_ST_END
- RK3368_DSP_HTOTAL_HS_END
- RK3368_DSP_VACT_ST_END
- RK3368_DSP_VACT_ST_END_F1
- RK3368_DSP_VS_ST_END_F1
- RK3368_DSP_VTOTAL_VS_END
- RK3368_EMMC_CON0
- RK3368_EMMC_CON1
- RK3368_FRC_LOWER01_0
- RK3368_FRC_LOWER01_1
- RK3368_FRC_LOWER10_0
- RK3368_FRC_LOWER10_1
- RK3368_FRC_LOWER11_0
- RK3368_FRC_LOWER11_1
- RK3368_GAMMA_LUT_ADDR
- RK3368_GLB_SRST_FST
- RK3368_GLB_SRST_SND
- RK3368_GMAC_CLK_125M
- RK3368_GMAC_CLK_25M
- RK3368_GMAC_CLK_2_5M
- RK3368_GMAC_CLK_RX_DL_CFG
- RK3368_GMAC_CLK_TX_DL_CFG
- RK3368_GMAC_FLOW_CTRL
- RK3368_GMAC_FLOW_CTRL_CLR
- RK3368_GMAC_PHY_INTF_SEL_RGMII
- RK3368_GMAC_PHY_INTF_SEL_RMII
- RK3368_GMAC_RMII_CLK_25M
- RK3368_GMAC_RMII_CLK_2_5M
- RK3368_GMAC_RMII_MODE
- RK3368_GMAC_RMII_MODE_CLR
- RK3368_GMAC_RXCLK_DLY_DISABLE
- RK3368_GMAC_RXCLK_DLY_ENABLE
- RK3368_GMAC_SPEED_100M
- RK3368_GMAC_SPEED_10M
- RK3368_GMAC_TXCLK_DLY_DISABLE
- RK3368_GMAC_TXCLK_DLY_ENABLE
- RK3368_GRF_SOC_CON15
- RK3368_GRF_SOC_CON16
- RK3368_GRF_SOC_STATUS0
- RK3368_HWC_CTRL0
- RK3368_HWC_CTRL1
- RK3368_HWC_DSP_ST
- RK3368_HWC_DST_ALPHA_CTRL
- RK3368_HWC_FADING_CTRL
- RK3368_HWC_LUT_ADDR
- RK3368_HWC_MST
- RK3368_HWC_RESERVED1
- RK3368_HWC_SRC_ALPHA_CTRL
- RK3368_IFBDC_BASE_ADDR
- RK3368_IFBDC_CMP_INDEX_INIT
- RK3368_IFBDC_CTRL
- RK3368_IFBDC_DEBUG0
- RK3368_IFBDC_DEBUG1
- RK3368_IFBDC_FRAME_RST_CYCLE
- RK3368_IFBDC_MB_SIZE
- RK3368_IFBDC_TILES_NUM
- RK3368_IFBDC_VIR
- RK3368_INTR_CLEAR
- RK3368_INTR_EN
- RK3368_INTR_STATUS
- RK3368_LATENCY_CTRL0
- RK3368_LINE_FLAG
- RK3368_MCU_BYPASS_RPORT
- RK3368_MCU_BYPASS_WPORT
- RK3368_MCU_CTRL
- RK3368_MISC_CON
- RK3368_MMU_AUTO_GATING
- RK3368_MMU_COMMAND
- RK3368_MMU_DTE_ADDR
- RK3368_MMU_INT_CLEAR
- RK3368_MMU_INT_MASK
- RK3368_MMU_INT_RAWSTAT
- RK3368_MMU_INT_STATUS
- RK3368_MMU_PAGE_FAULT_ADDR
- RK3368_MMU_STATUS
- RK3368_MMU_ZAP_ONE_LINE
- RK3368_PD_A53_B0
- RK3368_PD_A53_B1
- RK3368_PD_A53_B2
- RK3368_PD_A53_B3
- RK3368_PD_A53_L0
- RK3368_PD_A53_L1
- RK3368_PD_A53_L2
- RK3368_PD_A53_L3
- RK3368_PD_ALIVE
- RK3368_PD_BUS
- RK3368_PD_GPU_0
- RK3368_PD_GPU_1
- RK3368_PD_PERI
- RK3368_PD_PMU
- RK3368_PD_SCU_B
- RK3368_PD_SCU_L
- RK3368_PD_VIDEO
- RK3368_PD_VIO
- RK3368_PLL_CON
- RK3368_POST_DSP_HACT_INFO
- RK3368_POST_DSP_VACT_INFO
- RK3368_POST_DSP_VACT_INFO_F1
- RK3368_POST_RESERVED
- RK3368_POST_SCL_CTRL
- RK3368_POST_SCL_FACTOR_YRGB
- RK3368_PULL_GRF_OFFSET
- RK3368_PULL_PMU_OFFSET
- RK3368_PWM_CNT
- RK3368_PWM_CTRL
- RK3368_PWM_DUTY_LPR
- RK3368_PWM_PERIOD_HPR
- RK3368_RD_LATENCY_SAMP_NUM0
- RK3368_RD_LATENCY_THR_NUM0
- RK3368_RD_MAX_LATENCY_NUM0
- RK3368_REG_CFG_DONE
- RK3368_SCAN_LINE_NUM
- RK3368_SDIO0_CON0
- RK3368_SDIO0_CON1
- RK3368_SDIO1_CON0
- RK3368_SDIO1_CON1
- RK3368_SDMMC_CON0
- RK3368_SDMMC_CON1
- RK3368_SOC_CON15
- RK3368_SOC_CON15_FLASH0
- RK3368_SOC_FLASH_SUPPLY_NUM
- RK3368_SOFTRST_CON
- RK3368_SYS_CTRL
- RK3368_SYS_CTRL1
- RK3368_VERSION_INFO
- RK3368_WIN0_ACT_INFO
- RK3368_WIN0_CBR_MST
- RK3368_WIN0_COLOR_KEY
- RK3368_WIN0_CTRL0
- RK3368_WIN0_CTRL1
- RK3368_WIN0_CTRL2
- RK3368_WIN0_DSP_BG
- RK3368_WIN0_DSP_INFO
- RK3368_WIN0_DSP_ST
- RK3368_WIN0_DST_ALPHA_CTRL
- RK3368_WIN0_FADING_CTRL
- RK3368_WIN0_SCL_FACTOR_CBR
- RK3368_WIN0_SCL_FACTOR_YRGB
- RK3368_WIN0_SCL_OFFSET
- RK3368_WIN0_SRC_ALPHA_CTRL
- RK3368_WIN0_VIR
- RK3368_WIN0_YRGB_MST
- RK3368_WIN1_ACT_INFO
- RK3368_WIN1_CBR_MST
- RK3368_WIN1_COLOR_KEY
- RK3368_WIN1_CTRL0
- RK3368_WIN1_CTRL1
- RK3368_WIN1_CTRL2
- RK3368_WIN1_DSP_BG
- RK3368_WIN1_DSP_INFO
- RK3368_WIN1_DSP_ST
- RK3368_WIN1_DST_ALPHA_CTRL
- RK3368_WIN1_FADING_CTRL
- RK3368_WIN1_SCL_FACTOR_CBR
- RK3368_WIN1_SCL_FACTOR_YRGB
- RK3368_WIN1_SCL_OFFSET
- RK3368_WIN1_SRC_ALPHA_CTRL
- RK3368_WIN1_VIR
- RK3368_WIN1_YRGB_MST
- RK3368_WIN2_COLOR_KEY
- RK3368_WIN2_CTRL0
- RK3368_WIN2_CTRL1
- RK3368_WIN2_DSP_BG
- RK3368_WIN2_DSP_INFO0
- RK3368_WIN2_DSP_INFO1
- RK3368_WIN2_DSP_INFO2
- RK3368_WIN2_DSP_INFO3
- RK3368_WIN2_DSP_ST0
- RK3368_WIN2_DSP_ST1
- RK3368_WIN2_DSP_ST2
- RK3368_WIN2_DSP_ST3
- RK3368_WIN2_DST_ALPHA_CTRL
- RK3368_WIN2_FADING_CTRL
- RK3368_WIN2_LUT_ADDR
- RK3368_WIN2_MST0
- RK3368_WIN2_MST1
- RK3368_WIN2_MST2
- RK3368_WIN2_MST3
- RK3368_WIN2_SRC_ALPHA_CTRL
- RK3368_WIN2_VIR0_1
- RK3368_WIN2_VIR2_3
- RK3368_WIN3_COLOR_KEY
- RK3368_WIN3_CTRL0
- RK3368_WIN3_CTRL1
- RK3368_WIN3_DSP_BG
- RK3368_WIN3_DSP_INFO0
- RK3368_WIN3_DSP_INFO1
- RK3368_WIN3_DSP_INFO2
- RK3368_WIN3_DSP_INFO3
- RK3368_WIN3_DSP_ST0
- RK3368_WIN3_DSP_ST1
- RK3368_WIN3_DSP_ST2
- RK3368_WIN3_DSP_ST3
- RK3368_WIN3_DST_ALPHA_CTRL
- RK3368_WIN3_FADING_CTRL
- RK3368_WIN3_LUT_ADDR
- RK3368_WIN3_MST0
- RK3368_WIN3_MST1
- RK3368_WIN3_MST2
- RK3368_WIN3_MST3
- RK3368_WIN3_SRC_ALPHA_CTRL
- RK3368_WIN3_VIR0_1
- RK3368_WIN3_VIR2_3
- RK3399
- RK3399_ACLK_MAX_FREQ
- RK3399_AFBCD0_CTRL
- RK3399_AFBCD0_HDR_PTR
- RK3399_AFBCD0_PIC_SIZE
- RK3399_AFBCD0_STATUS
- RK3399_AFBCD1_CTRL
- RK3399_AFBCD1_HDR_PTR
- RK3399_AFBCD1_PIC_SIZE
- RK3399_AFBCD1_STATUS
- RK3399_AFBCD2_CTRL
- RK3399_AFBCD2_HDR_PTR
- RK3399_AFBCD2_PIC_SIZE
- RK3399_AFBCD2_STATUS
- RK3399_AFBCD3_CTRL
- RK3399_AFBCD3_HDR_PTR
- RK3399_AFBCD3_PIC_SIZE
- RK3399_AFBCD3_STATUS
- RK3399_AUTO_GATING_EN
- RK3399_A_MASK
- RK3399_A_SHIFT
- RK3399_BCSH_BCS
- RK3399_BCSH_COLOR_BAR
- RK3399_BCSH_CTRL
- RK3399_BCSH_H
- RK3399_BCSH_R2Y_CSC_COE
- RK3399_BCSH_Y2R_CSC_COE
- RK3399_BLANKING_VALUE
- RK3399_CABC_CTRL0
- RK3399_CABC_CTRL1
- RK3399_CABC_CTRL2
- RK3399_CABC_CTRL3
- RK3399_CABC_GAMMA_LUT_ADDR
- RK3399_CABC_GAUSS_LINE0_0
- RK3399_CABC_GAUSS_LINE0_1
- RK3399_CABC_GAUSS_LINE1_0
- RK3399_CABC_GAUSS_LINE1_1
- RK3399_CABC_GAUSS_LINE2_0
- RK3399_CABC_GAUSS_LINE2_1
- RK3399_CLKGATE_CON
- RK3399_CLKSEL0
- RK3399_CLKSEL1
- RK3399_CLKSEL_CON
- RK3399_CPUCLKB_RATE
- RK3399_CPUCLKL_RATE
- RK3399_CSB
- RK3399_DIV_ACLKM_MASK
- RK3399_DIV_ACLKM_SHIFT
- RK3399_DIV_ATCLK_MASK
- RK3399_DIV_ATCLK_SHIFT
- RK3399_DIV_PCLK_DBG_MASK
- RK3399_DIV_PCLK_DBG_SHIFT
- RK3399_DMC_NUM_CH
- RK3399_DRV_3BITS_PER_PIN
- RK3399_DSI0_FORCERXMODE
- RK3399_DSI0_FORCETXSTOPMODE
- RK3399_DSI0_LCDC_SEL
- RK3399_DSI0_TURNDISABLE
- RK3399_DSI0_TURNREQUEST
- RK3399_DSI1_ENABLE
- RK3399_DSI1_FORCERXMODE
- RK3399_DSI1_FORCETXSTOPMODE
- RK3399_DSI1_LCDC_SEL
- RK3399_DSI1_TURNDISABLE
- RK3399_DSP_BG
- RK3399_DSP_CTRL0
- RK3399_DSP_CTRL1
- RK3399_DSP_HACT_ST_END
- RK3399_DSP_HTOTAL_HS_END
- RK3399_DSP_VACT_ST_END
- RK3399_DSP_VACT_ST_END_F1
- RK3399_DSP_VS_ST_END_F1
- RK3399_DSP_VTOTAL_VS_END
- RK3399_EDP
- RK3399_EDP_LCDC_SEL
- RK3399_FRC_LOWER01_0
- RK3399_FRC_LOWER01_1
- RK3399_FRC_LOWER10_0
- RK3399_FRC_LOWER10_1
- RK3399_FRC_LOWER11_0
- RK3399_FRC_LOWER11_1
- RK3399_GAMMA_LUT_ADDR
- RK3399_GLB_CNT_TH
- RK3399_GLB_SRST_FST
- RK3399_GLB_SRST_SND
- RK3399_GMAC_CLK_125M
- RK3399_GMAC_CLK_25M
- RK3399_GMAC_CLK_2_5M
- RK3399_GMAC_CLK_RX_DL_CFG
- RK3399_GMAC_CLK_TX_DL_CFG
- RK3399_GMAC_FLOW_CTRL
- RK3399_GMAC_FLOW_CTRL_CLR
- RK3399_GMAC_PHY_INTF_SEL_RGMII
- RK3399_GMAC_PHY_INTF_SEL_RMII
- RK3399_GMAC_RMII_CLK_25M
- RK3399_GMAC_RMII_CLK_2_5M
- RK3399_GMAC_RMII_MODE
- RK3399_GMAC_RMII_MODE_CLR
- RK3399_GMAC_RXCLK_DLY_DISABLE
- RK3399_GMAC_RXCLK_DLY_ENABLE
- RK3399_GMAC_SPEED_100M
- RK3399_GMAC_SPEED_10M
- RK3399_GMAC_TXCLK_DLY_DISABLE
- RK3399_GMAC_TXCLK_DLY_ENABLE
- RK3399_GRF_SOC_CON20
- RK3399_GRF_SOC_CON22
- RK3399_GRF_SOC_CON23
- RK3399_GRF_SOC_CON24
- RK3399_GRF_SOC_CON5
- RK3399_GRF_SOC_CON6
- RK3399_GRF_SOC_CON7
- RK3399_HDMI_LCDC_SEL
- RK3399_HWC_CSC_COE
- RK3399_HWC_CTRL0
- RK3399_HWC_CTRL1
- RK3399_HWC_DSP_ST
- RK3399_HWC_DST_ALPHA_CTRL
- RK3399_HWC_FADING_CTRL
- RK3399_HWC_LUT_ADDR
- RK3399_HWC_MST
- RK3399_HWC_RESERVED1
- RK3399_HWC_SRC_ALPHA_CTRL
- RK3399_INTR_CLEAR0
- RK3399_INTR_CLEAR1
- RK3399_INTR_EN0
- RK3399_INTR_EN1
- RK3399_INTR_RAW_STATUS0
- RK3399_INTR_RAW_STATUS1
- RK3399_INTR_STATUS0
- RK3399_INTR_STATUS1
- RK3399_LINE_FLAG
- RK3399_LOAD
- RK3399_MCU_BYPASS_PORT
- RK3399_MCU_CTRL
- RK3399_MISC_CON
- RK3399_NBYTES
- RK3399_PD
- RK3399_PD_A53_L0
- RK3399_PD_A53_L1
- RK3399_PD_A53_L2
- RK3399_PD_A53_L3
- RK3399_PD_A72_B0
- RK3399_PD_A72_B1
- RK3399_PD_ALIVE
- RK3399_PD_CCI
- RK3399_PD_CCI0
- RK3399_PD_CCI1
- RK3399_PD_CENTER
- RK3399_PD_EDP
- RK3399_PD_EMMC
- RK3399_PD_GIC
- RK3399_PD_GMAC
- RK3399_PD_GPU
- RK3399_PD_HDCP
- RK3399_PD_IEP
- RK3399_PD_ISP0
- RK3399_PD_ISP1
- RK3399_PD_PERIHP
- RK3399_PD_PERILP
- RK3399_PD_PMU
- RK3399_PD_RGA
- RK3399_PD_SCU_B
- RK3399_PD_SCU_L
- RK3399_PD_SD
- RK3399_PD_SDIOAUDIO
- RK3399_PD_TCPD0
- RK3399_PD_TCPD1
- RK3399_PD_USB3
- RK3399_PD_VCODEC
- RK3399_PD_VDU
- RK3399_PD_VIO
- RK3399_PD_VO
- RK3399_PD_VOPB
- RK3399_PD_VOPL
- RK3399_PGENB
- RK3399_PLLCON
- RK3399_PLLCON0_FBDIV_MASK
- RK3399_PLLCON0_FBDIV_SHIFT
- RK3399_PLLCON1_POSTDIV1_MASK
- RK3399_PLLCON1_POSTDIV1_SHIFT
- RK3399_PLLCON1_POSTDIV2_MASK
- RK3399_PLLCON1_POSTDIV2_SHIFT
- RK3399_PLLCON1_REFDIV_MASK
- RK3399_PLLCON1_REFDIV_SHIFT
- RK3399_PLLCON2_FRAC_MASK
- RK3399_PLLCON2_FRAC_SHIFT
- RK3399_PLLCON2_LOCK_STATUS
- RK3399_PLLCON3_DSMPD_MASK
- RK3399_PLLCON3_DSMPD_SHIFT
- RK3399_PLLCON3_PWRDOWN
- RK3399_PLL_CON
- RK3399_PMUGRF_CON0
- RK3399_PMUGRF_CON0_VSEL
- RK3399_PMUGRF_DDRTYPE_DDR3
- RK3399_PMUGRF_DDRTYPE_LPDDR2
- RK3399_PMUGRF_DDRTYPE_LPDDR3
- RK3399_PMUGRF_DDRTYPE_LPDDR4
- RK3399_PMUGRF_DDRTYPE_MASK
- RK3399_PMUGRF_DDRTYPE_SHIFT
- RK3399_PMUGRF_OS_REG2
- RK3399_PMUGRF_VSEL_SUPPLY_NUM
- RK3399_PMU_CLKGATE_CON
- RK3399_PMU_CLKSEL_CON
- RK3399_PMU_PLL_CON
- RK3399_PMU_SOFTRST_CON
- RK3399_POST_DSP_HACT_INFO
- RK3399_POST_DSP_VACT_INFO
- RK3399_POST_DSP_VACT_INFO_F1
- RK3399_POST_RESERVED
- RK3399_POST_SCL_CTRL
- RK3399_POST_SCL_FACTOR_YRGB
- RK3399_POST_YUV2YUV_3X3_COE
- RK3399_POST_YUV2YUV_R2Y_COE
- RK3399_POST_YUV2YUV_Y2R_COE
- RK3399_PULL_GRF_OFFSET
- RK3399_PULL_PMU_OFFSET
- RK3399_PWM_CNT
- RK3399_PWM_CTRL
- RK3399_PWM_DUTY_LPR
- RK3399_PWM_PERIOD_HPR
- RK3399_REG_CFG_DONE
- RK3399_RSB
- RK3399_RST_CON
- RK3399_RST_ST
- RK3399_SDIO_CON0
- RK3399_SDIO_CON1
- RK3399_SDMMC_CON0
- RK3399_SDMMC_CON1
- RK3399_SOFTRST_CON
- RK3399_STROBE
- RK3399_STROBSFTSEL
- RK3399_SYS_CTRL
- RK3399_SYS_CTRL1
- RK3399_TXRX_BASEDIR
- RK3399_TXRX_ENABLECLK
- RK3399_TXRX_MASTERSLAVEZ
- RK3399_VERSION_INFO
- RK3399_VOP_STATUS
- RK3399_VPU_REGS_H_
- RK3399_WB_CBR_MST
- RK3399_WB_CTRL0
- RK3399_WB_CTRL1
- RK3399_WB_YRGB_MST
- RK3399_WIN0_ACT_INFO
- RK3399_WIN0_CBR_MST
- RK3399_WIN0_COLOR_KEY
- RK3399_WIN0_CSC_COE
- RK3399_WIN0_CTRL0
- RK3399_WIN0_CTRL1
- RK3399_WIN0_CTRL2
- RK3399_WIN0_DSP_BG
- RK3399_WIN0_DSP_INFO
- RK3399_WIN0_DSP_ST
- RK3399_WIN0_DST_ALPHA_CTRL
- RK3399_WIN0_FADING_CTRL
- RK3399_WIN0_SCL_FACTOR_CBR
- RK3399_WIN0_SCL_FACTOR_YRGB
- RK3399_WIN0_SCL_OFFSET
- RK3399_WIN0_SRC_ALPHA_CTRL
- RK3399_WIN0_VIR
- RK3399_WIN0_YRGB_MST
- RK3399_WIN0_YUV2YUV_3X3
- RK3399_WIN0_YUV2YUV_R2Y
- RK3399_WIN0_YUV2YUV_Y2R
- RK3399_WIN1_ACT_INFO
- RK3399_WIN1_CBR_MST
- RK3399_WIN1_COLOR_KEY
- RK3399_WIN1_CSC_COE
- RK3399_WIN1_CTRL0
- RK3399_WIN1_CTRL1
- RK3399_WIN1_CTRL2
- RK3399_WIN1_DSP_BG
- RK3399_WIN1_DSP_INFO
- RK3399_WIN1_DSP_ST
- RK3399_WIN1_DST_ALPHA_CTRL
- RK3399_WIN1_FADING_CTRL
- RK3399_WIN1_SCL_FACTOR_CBR
- RK3399_WIN1_SCL_FACTOR_YRGB
- RK3399_WIN1_SCL_OFFSET
- RK3399_WIN1_SRC_ALPHA_CTRL
- RK3399_WIN1_VIR
- RK3399_WIN1_YRGB_MST
- RK3399_WIN1_YUV2YUV_3X3
- RK3399_WIN1_YUV2YUV_R2Y
- RK3399_WIN1_YUV2YUV_Y2R
- RK3399_WIN2_COLOR_KEY
- RK3399_WIN2_CSC_COE
- RK3399_WIN2_CTRL0
- RK3399_WIN2_CTRL1
- RK3399_WIN2_DSP_BG
- RK3399_WIN2_DSP_INFO0
- RK3399_WIN2_DSP_INFO1
- RK3399_WIN2_DSP_INFO2
- RK3399_WIN2_DSP_INFO3
- RK3399_WIN2_DSP_ST0
- RK3399_WIN2_DSP_ST1
- RK3399_WIN2_DSP_ST2
- RK3399_WIN2_DSP_ST3
- RK3399_WIN2_DST_ALPHA_CTRL
- RK3399_WIN2_FADING_CTRL
- RK3399_WIN2_LUT_ADDR
- RK3399_WIN2_MST0
- RK3399_WIN2_MST1
- RK3399_WIN2_MST2
- RK3399_WIN2_MST3
- RK3399_WIN2_SRC_ALPHA_CTRL
- RK3399_WIN2_VIR0_1
- RK3399_WIN2_VIR2_3
- RK3399_WIN2_YUV2YUV_3X3
- RK3399_WIN2_YUV2YUV_R2Y
- RK3399_WIN2_YUV2YUV_Y2R
- RK3399_WIN3_COLOR_KEY
- RK3399_WIN3_CSC_COE
- RK3399_WIN3_CTRL0
- RK3399_WIN3_CTRL1
- RK3399_WIN3_DSP_BG
- RK3399_WIN3_DSP_INFO0
- RK3399_WIN3_DSP_INFO1
- RK3399_WIN3_DSP_INFO2
- RK3399_WIN3_DSP_INFO3
- RK3399_WIN3_DSP_ST0
- RK3399_WIN3_DSP_ST1
- RK3399_WIN3_DSP_ST2
- RK3399_WIN3_DSP_ST3
- RK3399_WIN3_DST_ALPHA_CTRL
- RK3399_WIN3_FADING_CTRL
- RK3399_WIN3_LUT_ADDR
- RK3399_WIN3_MST0
- RK3399_WIN3_MST1
- RK3399_WIN3_MST2
- RK3399_WIN3_MST3
- RK3399_WIN3_SRC_ALPHA_CTRL
- RK3399_WIN3_VIR0_1
- RK3399_WIN3_VIR2_3
- RK3399_WIN3_YUV2YUV_3X3
- RK3399_WIN3_YUV2YUV_R2Y
- RK3399_WIN3_YUV2YUV_Y2R
- RK3399_YUV2YUV_POST
- RK3399_YUV2YUV_WIN
- RK3x
- RK805_ALARM_INT_STATUS
- RK805_BUCK1_2_ILMAX_2500MA
- RK805_BUCK1_2_ILMAX_3000MA
- RK805_BUCK1_2_ILMAX_3500MA
- RK805_BUCK1_2_ILMAX_4000MA
- RK805_BUCK1_2_ILMAX_MASK
- RK805_BUCK1_CONFIG_REG
- RK805_BUCK1_ON_VSEL_REG
- RK805_BUCK1_SLP_VSEL_REG
- RK805_BUCK2_CONFIG_REG
- RK805_BUCK2_ON_VSEL_REG
- RK805_BUCK2_SLP_VSEL_REG
- RK805_BUCK3_4_ILMAX_MASK
- RK805_BUCK3_CONFIG_REG
- RK805_BUCK3_ILMAX_1500MA
- RK805_BUCK3_ILMAX_2000MA
- RK805_BUCK3_ILMAX_2500MA
- RK805_BUCK3_ILMAX_3000MA
- RK805_BUCK4_CONFIG_REG
- RK805_BUCK4_ILMAX_2000MA
- RK805_BUCK4_ILMAX_2500MA
- RK805_BUCK4_ILMAX_3000MA
- RK805_BUCK4_ILMAX_3500MA
- RK805_BUCK4_ON_VSEL_REG
- RK805_BUCK4_SLP_VSEL_REG
- RK805_BUCK_LDO_SLP_LP_EN_REG
- RK805_DCDC_EN_REG
- RK805_DESC
- RK805_DEV_CTRL_REG
- RK805_GPIO0
- RK805_GPIO0_VAL_MSK
- RK805_GPIO1
- RK805_GPIO1_VAL_MSK
- RK805_GPIO_IO_POL_REG
- RK805_HOTDIE_INT_STATUS
- RK805_ID
- RK805_ID_DCDC1
- RK805_ID_DCDC2
- RK805_ID_DCDC3
- RK805_ID_DCDC4
- RK805_ID_LDO1
- RK805_ID_LDO2
- RK805_ID_LDO3
- RK805_INT_ALARM_EN
- RK805_INT_STS_MSK_REG
- RK805_INT_STS_REG
- RK805_INT_TIMER_EN
- RK805_IRQ_HOTDIE
- RK805_IRQ_HOTDIE_MSK
- RK805_IRQ_PWRON
- RK805_IRQ_PWRON_FALL
- RK805_IRQ_PWRON_FALL_MSK
- RK805_IRQ_PWRON_LP
- RK805_IRQ_PWRON_LP_MSK
- RK805_IRQ_PWRON_MSK
- RK805_IRQ_PWRON_RISE
- RK805_IRQ_PWRON_RISE_MSK
- RK805_IRQ_RTC_ALARM
- RK805_IRQ_RTC_ALARM_MSK
- RK805_IRQ_RTC_PERIOD
- RK805_IRQ_RTC_PERIOD_MSK
- RK805_IRQ_VB_LOW
- RK805_IRQ_VB_LOW_MSK
- RK805_LDO1_ON_VSEL_REG
- RK805_LDO1_SLP_VSEL_REG
- RK805_LDO2_ON_VSEL_REG
- RK805_LDO2_SLP_VSEL_REG
- RK805_LDO3_ON_VSEL_REG
- RK805_LDO3_SLP_VSEL_REG
- RK805_LDO_EN_REG
- RK805_NUM_REGULATORS
- RK805_OFF_SOURCE_REG
- RK805_ON_SOURCE_REG
- RK805_OUT_REG
- RK805_PERIOD_INT_STATUS
- RK805_PINMUX_GPIO
- RK805_PWRON_DB_REG
- RK805_PWRON_FALL_RISE_INT_EN
- RK805_PWRON_FALL_RISE_INT_MSK
- RK805_PWRON_INT_STATUS
- RK805_PWRON_LP_INT_STATUS
- RK805_PWRON_LP_INT_TIME_REG
- RK805_PWR_FALL_INT_STATUS
- RK805_PWR_RISE_INT_STATUS
- RK805_RTC_ALARM_INT_MASK
- RK805_RTC_PERIOD_INT_MASK
- RK805_SLP_DCDC_EN_REG
- RK805_SLP_LDO_EN_REG
- RK805_THERMAL_REG
- RK805_VB_LOW_INT_STATUS
- RK805_VB_MON_REG
- RK808_ALARM_DAYS_REG
- RK808_ALARM_HOURS_REG
- RK808_ALARM_MINUTES_REG
- RK808_ALARM_MONTHS_REG
- RK808_ALARM_SECONDS_REG
- RK808_ALARM_YEARS_REG
- RK808_BOOST_CONFIG_REG
- RK808_BUCK1_CONFIG_REG
- RK808_BUCK1_DVS_VSEL_REG
- RK808_BUCK1_ON_VSEL_REG
- RK808_BUCK1_SLP_VSEL_REG
- RK808_BUCK2_CONFIG_REG
- RK808_BUCK2_DVS_VSEL_REG
- RK808_BUCK2_ON_VSEL_REG
- RK808_BUCK2_SLP_VSEL_REG
- RK808_BUCK3_CONFIG_REG
- RK808_BUCK4_CONFIG_REG
- RK808_BUCK4_ON_VSEL_REG
- RK808_BUCK4_SLP_VSEL_REG
- RK808_BUCK4_VSEL_MASK
- RK808_BUCK_VSEL_MASK
- RK808_CLK32OUT_REG
- RK808_CLKOUT0
- RK808_CLKOUT1
- RK808_DAYS_REG
- RK808_DCDC1
- RK808_DCDC_EN_REG
- RK808_DCDC_PG_REG
- RK808_DCDC_UV_ACT_REG
- RK808_DCDC_UV_STS_REG
- RK808_DEVCTRL_REG
- RK808_DVS1_POL
- RK808_DVS2_POL
- RK808_DVS_REG_OFFSET
- RK808_HOURS_REG
- RK808_ID
- RK808_ID_DCDC1
- RK808_ID_DCDC2
- RK808_ID_DCDC3
- RK808_ID_DCDC4
- RK808_ID_LDO1
- RK808_ID_LDO2
- RK808_ID_LDO3
- RK808_ID_LDO4
- RK808_ID_LDO5
- RK808_ID_LDO6
- RK808_ID_LDO7
- RK808_ID_LDO8
- RK808_ID_LSB
- RK808_ID_MSB
- RK808_ID_SWITCH1
- RK808_ID_SWITCH2
- RK808_INT_STS_MSK_REG1
- RK808_INT_STS_MSK_REG2
- RK808_INT_STS_REG1
- RK808_INT_STS_REG2
- RK808_IO_POL_REG
- RK808_IRQ_HOTDIE
- RK808_IRQ_HOTDIE_MSK
- RK808_IRQ_PLUG_IN_INT
- RK808_IRQ_PLUG_IN_INT_MSK
- RK808_IRQ_PLUG_OUT_INT
- RK808_IRQ_PLUG_OUT_INT_MSK
- RK808_IRQ_PWRON
- RK808_IRQ_PWRON_LP
- RK808_IRQ_PWRON_LP_MSK
- RK808_IRQ_PWRON_MSK
- RK808_IRQ_RTC_ALARM
- RK808_IRQ_RTC_ALARM_MSK
- RK808_IRQ_RTC_PERIOD
- RK808_IRQ_RTC_PERIOD_MSK
- RK808_IRQ_VB_LO
- RK808_IRQ_VB_LO_MSK
- RK808_IRQ_VOUT_LO
- RK808_IRQ_VOUT_LO_MSK
- RK808_LDO1
- RK808_LDO1_ON_VSEL_REG
- RK808_LDO1_SLP_VSEL_REG
- RK808_LDO2_ON_VSEL_REG
- RK808_LDO2_SLP_VSEL_REG
- RK808_LDO3_ON_VSEL_REG
- RK808_LDO3_SLP_VSEL_REG
- RK808_LDO4_ON_VSEL_REG
- RK808_LDO4_SLP_VSEL_REG
- RK808_LDO5_ON_VSEL_REG
- RK808_LDO5_SLP_VSEL_REG
- RK808_LDO6_ON_VSEL_REG
- RK808_LDO6_SLP_VSEL_REG
- RK808_LDO7_ON_VSEL_REG
- RK808_LDO7_SLP_VSEL_REG
- RK808_LDO8_ON_VSEL_REG
- RK808_LDO8_SLP_VSEL_REG
- RK808_LDO_EN_REG
- RK808_LDO_PG_REG
- RK808_LDO_UV_ACT_REG
- RK808_LDO_UV_STS_REG
- RK808_LDO_VSEL_MASK
- RK808_MINUTES_REG
- RK808_MONTHS_REG
- RK808_NUM_IRQ
- RK808_NUM_REGULATORS
- RK808_RAMP_RATE_10MV_PER_US
- RK808_RAMP_RATE_2MV_PER_US
- RK808_RAMP_RATE_4MV_PER_US
- RK808_RAMP_RATE_6MV_PER_US
- RK808_RAMP_RATE_MASK
- RK808_RAMP_RATE_OFFSET
- RK808_RTC_COMP_LSB_REG
- RK808_RTC_COMP_MSB_REG
- RK808_RTC_CTRL_REG
- RK808_RTC_INT_REG
- RK808_RTC_STATUS_REG
- RK808_SECONDS_REG
- RK808_SLEEP_SET_OFF_REG1
- RK808_SLEEP_SET_OFF_REG2
- RK808_SLP_REG_OFFSET
- RK808_SLP_SET_OFF_REG_OFFSET
- RK808_THERMAL_REG
- RK808_VBAT_LOW_2V8
- RK808_VBAT_LOW_2V9
- RK808_VBAT_LOW_3V0
- RK808_VBAT_LOW_3V1
- RK808_VBAT_LOW_3V2
- RK808_VBAT_LOW_3V3
- RK808_VBAT_LOW_3V4
- RK808_VBAT_LOW_3V5
- RK808_VB_MON_REG
- RK808_VOUT_MON_TDB_REG
- RK808_WEEKS_REG
- RK808_YEARS_REG
- RK809_BUCK5_CONFIG
- RK809_BUCK5_SEL_CNT
- RK809_BUCK5_VSEL_MASK
- RK809_ID
- RK809_ID_DCDC5
- RK809_ID_SW1
- RK809_ID_SW2
- RK809_NUM_REGULATORS
- RK817_ALARM_DAYS_REG
- RK817_ALARM_HOURS_REG
- RK817_ALARM_MINUTES_REG
- RK817_ALARM_MONTHS_REG
- RK817_ALARM_SECONDS_REG
- RK817_ALARM_YEARS_REG
- RK817_BOOST_DESC
- RK817_BOOST_OTG_CFG
- RK817_BOOST_VSEL_MASK
- RK817_BUCK1_MAX0
- RK817_BUCK1_MAX1
- RK817_BUCK1_MIN0
- RK817_BUCK1_MIN1
- RK817_BUCK1_ON_VSEL_REG
- RK817_BUCK1_SEL0
- RK817_BUCK1_SEL1
- RK817_BUCK1_SEL_CNT
- RK817_BUCK1_SLP_VSEL_REG
- RK817_BUCK1_STP0
- RK817_BUCK1_STP1
- RK817_BUCK2_CONFIG_REG
- RK817_BUCK2_ON_VSEL_REG
- RK817_BUCK2_SLP_VSEL_REG
- RK817_BUCK3_CONFIG_REG
- RK817_BUCK3_FB_RES_EXT
- RK817_BUCK3_FB_RES_INTER
- RK817_BUCK3_FB_RES_MSK
- RK817_BUCK3_MAX1
- RK817_BUCK3_ON_VSEL_REG
- RK817_BUCK3_SEL1
- RK817_BUCK3_SEL_CNT
- RK817_BUCK3_SLP_VSEL_REG
- RK817_BUCK4_CONFIG_REG
- RK817_BUCK4_ON_VSEL_REG
- RK817_BUCK4_SLP_VSEL_REG
- RK817_BUCK_CONFIG_REG
- RK817_BUCK_VSEL_MASK
- RK817_CLK32KOUT2_EN
- RK817_DAYS_REG
- RK817_DESC
- RK817_DESC_SWITCH
- RK817_GPIO_INT_CFG
- RK817_HOTDIE_105
- RK817_HOTDIE_115
- RK817_HOTDIE_85
- RK817_HOTDIE_95
- RK817_HOTDIE_TEMP_MSK
- RK817_HOURS_REG
- RK817_ID
- RK817_ID_BOOST
- RK817_ID_BOOST_OTG_SW
- RK817_ID_DCDC1
- RK817_ID_DCDC2
- RK817_ID_DCDC3
- RK817_ID_DCDC4
- RK817_ID_LDO1
- RK817_ID_LDO2
- RK817_ID_LDO3
- RK817_ID_LDO4
- RK817_ID_LDO5
- RK817_ID_LDO6
- RK817_ID_LDO7
- RK817_ID_LDO8
- RK817_ID_LDO9
- RK817_ID_LSB
- RK817_ID_MSB
- RK817_INT_POL_H
- RK817_INT_POL_L
- RK817_INT_POL_MSK
- RK817_INT_STS_MSK_REG0
- RK817_INT_STS_MSK_REG1
- RK817_INT_STS_MSK_REG2
- RK817_INT_STS_REG0
- RK817_INT_STS_REG1
- RK817_INT_STS_REG2
- RK817_IRQ_BAT_DIS_ILIM
- RK817_IRQ_BAT_OVP
- RK817_IRQ_CHRG_BAT_HI
- RK817_IRQ_CHRG_IN_CLMP
- RK817_IRQ_CHRG_TERM
- RK817_IRQ_CHRG_TIME
- RK817_IRQ_CHRG_TS
- RK817_IRQ_CLASSD_MUTE_DONE
- RK817_IRQ_CLASSD_OCP
- RK817_IRQ_CODEC_PD
- RK817_IRQ_CODEC_PO
- RK817_IRQ_END
- RK817_IRQ_GATE_GPIO
- RK817_IRQ_HOTDIE
- RK817_IRQ_PLUG_IN
- RK817_IRQ_PLUG_OUT
- RK817_IRQ_PWMON_LP
- RK817_IRQ_PWRON
- RK817_IRQ_PWRON_FALL
- RK817_IRQ_PWRON_RISE
- RK817_IRQ_RTC_ALARM
- RK817_IRQ_RTC_PERIOD
- RK817_IRQ_TS_GPIO
- RK817_IRQ_USB_OV
- RK817_IRQ_VB_LO
- RK817_LDO_ON_VSEL_REG
- RK817_LDO_VSEL_MASK
- RK817_MINUTES_REG
- RK817_MONTHS_REG
- RK817_NUM_REGULATORS
- RK817_OFF_SOURCE_REG
- RK817_ON_SOURCE_REG
- RK817_POWER_CONFIG
- RK817_POWER_EN_REG
- RK817_POWER_SLP_EN_REG
- RK817_RAMP_RATE_12_5MV_PER_US
- RK817_RAMP_RATE_25MV_PER_US
- RK817_RAMP_RATE_3MV_PER_US
- RK817_RAMP_RATE_6_3MV_PER_US
- RK817_RAMP_RATE_MASK
- RK817_RAMP_RATE_OFFSET
- RK817_RST_FUNC_CNT
- RK817_RST_FUNC_DEV
- RK817_RST_FUNC_MSK
- RK817_RST_FUNC_REG
- RK817_RST_FUNC_SFT
- RK817_RTC_COMP_LSB_REG
- RK817_RTC_COMP_MSB_REG
- RK817_RTC_CTRL_REG
- RK817_RTC_CTRL_RSV4
- RK817_RTC_INT_REG
- RK817_RTC_STATUS_REG
- RK817_SECONDS_REG
- RK817_SLPPIN_FUNC_MSK
- RK817_SLPPOL_H
- RK817_SLPPOL_L
- RK817_SLPPOL_MSK
- RK817_SYS_CFG
- RK817_SYS_STS
- RK817_TSD_140
- RK817_TSD_160
- RK817_TSD_TEMP_MSK
- RK817_WEEKS_REG
- RK817_YEARS_REG
- RK818_BOOST_CONFIG_REG
- RK818_BOOST_CTRL_REG
- RK818_BOOST_LDO9_ON_VSEL_REG
- RK818_BOOST_LDO9_SLP_VSEL_REG
- RK818_BOOST_ON_VSEL_MASK
- RK818_BUCK1_CONFIG_REG
- RK818_BUCK1_ON_VSEL_REG
- RK818_BUCK1_SLP_VSEL_REG
- RK818_BUCK2_CONFIG_REG
- RK818_BUCK2_ON_VSEL_REG
- RK818_BUCK2_SLP_VSEL_REG
- RK818_BUCK3_CONFIG_REG
- RK818_BUCK4_CONFIG_REG
- RK818_BUCK4_ON_VSEL_REG
- RK818_BUCK4_SLP_VSEL_REG
- RK818_BUCK4_VSEL_MASK
- RK818_BUCK_VSEL_MASK
- RK818_DCDC1
- RK818_DCDC_EN_REG
- RK818_DCDC_ILMAX
- RK818_DCDC_PG_REG
- RK818_DCDC_UV_ACT_REG
- RK818_DCDC_UV_STS_REG
- RK818_DEVCTRL_REG
- RK818_H5V_EN
- RK818_H5V_EN_REG
- RK818_ID
- RK818_ID_BOOST
- RK818_ID_DCDC1
- RK818_ID_DCDC2
- RK818_ID_DCDC3
- RK818_ID_DCDC4
- RK818_ID_HDMI_SWITCH
- RK818_ID_LDO1
- RK818_ID_LDO2
- RK818_ID_LDO3
- RK818_ID_LDO4
- RK818_ID_LDO5
- RK818_ID_LDO6
- RK818_ID_LDO7
- RK818_ID_LDO8
- RK818_ID_LDO9
- RK818_ID_OTG_SWITCH
- RK818_ID_SWITCH
- RK818_INT_STS_MSK_REG1
- RK818_INT_STS_MSK_REG2
- RK818_INT_STS_REG1
- RK818_INT_STS_REG2
- RK818_IO_POL_REG
- RK818_IRQ_CHG_CVTLIM
- RK818_IRQ_CHG_CVTLIM_MSK
- RK818_IRQ_CHG_OK
- RK818_IRQ_CHG_OK_MSK
- RK818_IRQ_CHG_TE
- RK818_IRQ_CHG_TE_MSK
- RK818_IRQ_CHG_TS1
- RK818_IRQ_CHG_TS1_MSK
- RK818_IRQ_DISCHG_ILIM
- RK818_IRQ_DISCHG_ILIM_MSK
- RK818_IRQ_HOTDIE
- RK818_IRQ_HOTDIE_MSK
- RK818_IRQ_PLUG_IN
- RK818_IRQ_PLUG_IN_MSK
- RK818_IRQ_PLUG_OUT
- RK818_IRQ_PLUG_OUT_MSK
- RK818_IRQ_PWRON
- RK818_IRQ_PWRON_LP
- RK818_IRQ_PWRON_LP_MSK
- RK818_IRQ_PWRON_MSK
- RK818_IRQ_RTC_ALARM
- RK818_IRQ_RTC_ALARM_MSK
- RK818_IRQ_RTC_PERIOD
- RK818_IRQ_RTC_PERIOD_MSK
- RK818_IRQ_TS2
- RK818_IRQ_TS2_MSK
- RK818_IRQ_USB_OV
- RK818_IRQ_USB_OV_MSK
- RK818_IRQ_VB_LO
- RK818_IRQ_VB_LO_MSK
- RK818_IRQ_VOUT_LO
- RK818_IRQ_VOUT_LO_MSK
- RK818_LDO1
- RK818_LDO1_ON_VSEL_REG
- RK818_LDO1_SLP_VSEL_REG
- RK818_LDO2_ON_VSEL_REG
- RK818_LDO2_SLP_VSEL_REG
- RK818_LDO3_ON_VSEL_MASK
- RK818_LDO3_ON_VSEL_REG
- RK818_LDO3_SLP_VSEL_REG
- RK818_LDO4_ON_VSEL_REG
- RK818_LDO4_SLP_VSEL_REG
- RK818_LDO5_ON_VSEL_REG
- RK818_LDO5_SLP_VSEL_REG
- RK818_LDO6_ON_VSEL_REG
- RK818_LDO6_SLP_VSEL_REG
- RK818_LDO7_ON_VSEL_REG
- RK818_LDO7_SLP_VSEL_REG
- RK818_LDO8_ON_VSEL_REG
- RK818_LDO8_SLP_VSEL_REG
- RK818_LDO_EN_REG
- RK818_LDO_PG_REG
- RK818_LDO_UV_ACT_REG
- RK818_LDO_UV_STS_REG
- RK818_LDO_VSEL_MASK
- RK818_NUM_IRQ
- RK818_NUM_REGULATORS
- RK818_REF_RDY_CTRL
- RK818_SLEEP_SET_OFF_REG1
- RK818_SLEEP_SET_OFF_REG2
- RK818_SLEEP_SET_OFF_REG3
- RK818_USB_CHG_SD_VSEL_MASK
- RK818_USB_CTRL_REG
- RK818_USB_ILIM_SEL_MASK
- RK818_USB_ILMIN_2000MA
- RK818_VOUT_MON_TDB_REG
- RK8XX_DESC
- RK8XX_DESC_COM
- RK8XX_DESC_SWITCH
- RK8XX_ID_MSK
- RKEY
- RKM
- RKR
- RKRF
- RKRR
- RKXX_DESC_SWITCH_COM
- RK_AUX_PD
- RK_CRYPTO_AES_128BIT_key
- RK_CRYPTO_AES_192BIT_key
- RK_CRYPTO_AES_256BIT_key
- RK_CRYPTO_AES_BYTESWAP_CNT
- RK_CRYPTO_AES_BYTESWAP_DI
- RK_CRYPTO_AES_BYTESWAP_DO
- RK_CRYPTO_AES_BYTESWAP_IV
- RK_CRYPTO_AES_BYTESWAP_KEY
- RK_CRYPTO_AES_CBC_MODE
- RK_CRYPTO_AES_CTRL
- RK_CRYPTO_AES_CTR_MODE
- RK_CRYPTO_AES_DEC
- RK_CRYPTO_AES_DIN_0
- RK_CRYPTO_AES_DIN_1
- RK_CRYPTO_AES_DIN_2
- RK_CRYPTO_AES_DIN_3
- RK_CRYPTO_AES_DONE
- RK_CRYPTO_AES_DOUT_0
- RK_CRYPTO_AES_DOUT_1
- RK_CRYPTO_AES_DOUT_2
- RK_CRYPTO_AES_DOUT_3
- RK_CRYPTO_AES_ECB_MODE
- RK_CRYPTO_AES_FIFO_MODE
- RK_CRYPTO_AES_IV_0
- RK_CRYPTO_AES_IV_1
- RK_CRYPTO_AES_IV_2
- RK_CRYPTO_AES_IV_3
- RK_CRYPTO_AES_KEY_0
- RK_CRYPTO_AES_KEY_1
- RK_CRYPTO_AES_KEY_2
- RK_CRYPTO_AES_KEY_3
- RK_CRYPTO_AES_KEY_4
- RK_CRYPTO_AES_KEY_5
- RK_CRYPTO_AES_KEY_6
- RK_CRYPTO_AES_KEY_7
- RK_CRYPTO_AES_KEY_CHANGE
- RK_CRYPTO_AES_START
- RK_CRYPTO_AES_STS
- RK_CRYPTO_BCDMA_DONE_ENA
- RK_CRYPTO_BCDMA_DONE_INT
- RK_CRYPTO_BCDMA_ERR_ENA
- RK_CRYPTO_BCDMA_ERR_INT
- RK_CRYPTO_BLOCK_FLUSH
- RK_CRYPTO_BLOCK_START
- RK_CRYPTO_BRDMAL
- RK_CRYPTO_BRDMAS
- RK_CRYPTO_BR_ADDR_MODE
- RK_CRYPTO_BTDMAS
- RK_CRYPTO_BT_ADDR_MODE
- RK_CRYPTO_BYTESWAP_BRFIFO
- RK_CRYPTO_BYTESWAP_BTFIFO
- RK_CRYPTO_BYTESWAP_HRFIFO
- RK_CRYPTO_CONF
- RK_CRYPTO_CTRL
- RK_CRYPTO_DEC
- RK_CRYPTO_DESSEL
- RK_CRYPTO_HASH_CTRL
- RK_CRYPTO_HASH_DONE
- RK_CRYPTO_HASH_DONE_ENA
- RK_CRYPTO_HASH_DONE_INT
- RK_CRYPTO_HASH_DOUT_0
- RK_CRYPTO_HASH_DOUT_1
- RK_CRYPTO_HASH_DOUT_2
- RK_CRYPTO_HASH_DOUT_3
- RK_CRYPTO_HASH_DOUT_4
- RK_CRYPTO_HASH_DOUT_5
- RK_CRYPTO_HASH_DOUT_6
- RK_CRYPTO_HASH_DOUT_7
- RK_CRYPTO_HASH_FLUSH
- RK_CRYPTO_HASH_MD5
- RK_CRYPTO_HASH_MSG_LEN
- RK_CRYPTO_HASH_PRNG
- RK_CRYPTO_HASH_SHA1
- RK_CRYPTO_HASH_SHA256
- RK_CRYPTO_HASH_START
- RK_CRYPTO_HASH_STS
- RK_CRYPTO_HASH_SWAP_DI
- RK_CRYPTO_HASH_SWAP_DO
- RK_CRYPTO_HRDMAL
- RK_CRYPTO_HRDMAS
- RK_CRYPTO_HRDMA_DONE_ENA
- RK_CRYPTO_HRDMA_DONE_INT
- RK_CRYPTO_HRDMA_ERR_ENA
- RK_CRYPTO_HRDMA_ERR_INT
- RK_CRYPTO_HR_ADDR_MODE
- RK_CRYPTO_INTENA
- RK_CRYPTO_INTSTS
- RK_CRYPTO_PKA_DONE_ENA
- RK_CRYPTO_PKA_DONE_INT
- RK_CRYPTO_PKA_FLUSH
- RK_CRYPTO_PKA_START
- RK_CRYPTO_TDES_BYTESWAP_DI
- RK_CRYPTO_TDES_BYTESWAP_DO
- RK_CRYPTO_TDES_BYTESWAP_IV
- RK_CRYPTO_TDES_BYTESWAP_KEY
- RK_CRYPTO_TDES_CHAINMODE_CBC
- RK_CRYPTO_TDES_CTRL
- RK_CRYPTO_TDES_DEC
- RK_CRYPTO_TDES_DIN_0
- RK_CRYPTO_TDES_DIN_1
- RK_CRYPTO_TDES_DONE
- RK_CRYPTO_TDES_DOUT_0
- RK_CRYPTO_TDES_DOUT_1
- RK_CRYPTO_TDES_EEE
- RK_CRYPTO_TDES_FIFO_MODE
- RK_CRYPTO_TDES_IV_0
- RK_CRYPTO_TDES_IV_1
- RK_CRYPTO_TDES_KEY1_0
- RK_CRYPTO_TDES_KEY1_1
- RK_CRYPTO_TDES_KEY2_0
- RK_CRYPTO_TDES_KEY2_1
- RK_CRYPTO_TDES_KEY3_0
- RK_CRYPTO_TDES_KEY3_1
- RK_CRYPTO_TDES_SELECT
- RK_CRYPTO_TDES_START
- RK_CRYPTO_TDES_STS
- RK_CRYPTO_TRNG_FLUSH
- RK_CRYPTO_TRNG_START
- RK_CRYPTO_WRITE_MASK
- RK_CYYPTO_HASHINSEL_BLOCK_CIPHER_INPUT
- RK_CYYPTO_HASHINSEL_BLOCK_CIPHER_OUTPUT
- RK_CYYPTO_HASHINSEL_INDEPENDENT_SOURCE
- RK_DTE_PT_ADDRESS_MASK
- RK_DTE_PT_VALID
- RK_FUNC_1
- RK_FUNC_2
- RK_FUNC_3
- RK_FUNC_4
- RK_FUNC_GPIO
- RK_GMAC2PHY_RMII_MODE
- RK_GPIO0
- RK_GPIO1
- RK_GPIO2
- RK_GPIO3
- RK_GPIO4
- RK_GPIO6
- RK_GRF_CON2_MACPHY_ID
- RK_GRF_CON3_MACPHY_ID
- RK_GRF_MACPHY_CON0
- RK_GRF_MACPHY_CON1
- RK_GRF_MACPHY_CON2
- RK_GRF_MACPHY_CON3
- RK_IOMMU_PGSIZE_BITMAP
- RK_IOVA_DTE_MASK
- RK_IOVA_DTE_SHIFT
- RK_IOVA_PAGE_MASK
- RK_IOVA_PAGE_SHIFT
- RK_IOVA_PTE_MASK
- RK_IOVA_PTE_SHIFT
- RK_MACPHY_CFG_CLK_50M
- RK_MACPHY_DISABLE
- RK_MACPHY_ENABLE
- RK_MMU_AUTO_GATING
- RK_MMU_CMD_DISABLE_PAGING
- RK_MMU_CMD_DISABLE_STALL
- RK_MMU_CMD_ENABLE_PAGING
- RK_MMU_CMD_ENABLE_STALL
- RK_MMU_CMD_FORCE_RESET
- RK_MMU_CMD_PAGE_FAULT_DONE
- RK_MMU_CMD_ZAP_CACHE
- RK_MMU_COMMAND
- RK_MMU_DTE_ADDR
- RK_MMU_FORCE_RESET_TIMEOUT_US
- RK_MMU_INT_CLEAR
- RK_MMU_INT_MASK
- RK_MMU_INT_RAWSTAT
- RK_MMU_INT_STATUS
- RK_MMU_IRQ_BUS_ERROR
- RK_MMU_IRQ_MASK
- RK_MMU_IRQ_PAGE_FAULT
- RK_MMU_PAGE_FAULT_ADDR
- RK_MMU_POLL_PERIOD_US
- RK_MMU_POLL_TIMEOUT_US
- RK_MMU_STATUS
- RK_MMU_STATUS_IDLE
- RK_MMU_STATUS_PAGE_FAULT_ACTIVE
- RK_MMU_STATUS_PAGE_FAULT_IS_WRITE
- RK_MMU_STATUS_PAGING_ENABLED
- RK_MMU_STATUS_REPLAY_BUFFER_EMPTY
- RK_MMU_STATUS_STALL_ACTIVE
- RK_MMU_STATUS_STALL_NOT_ACTIVE
- RK_MMU_ZAP_ONE_LINE
- RK_PA0
- RK_PA1
- RK_PA2
- RK_PA3
- RK_PA4
- RK_PA5
- RK_PA6
- RK_PA7
- RK_PB0
- RK_PB1
- RK_PB2
- RK_PB3
- RK_PB4
- RK_PB5
- RK_PB6
- RK_PB7
- RK_PC0
- RK_PC1
- RK_PC2
- RK_PC3
- RK_PC4
- RK_PC5
- RK_PC6
- RK_PC7
- RK_PD0
- RK_PD1
- RK_PD2
- RK_PD3
- RK_PD4
- RK_PD5
- RK_PD6
- RK_PD7
- RK_PDM_RK3229
- RK_PDM_RK3308
- RK_PLL_PD
- RK_PTE_PAGE_ADDRESS_MASK
- RK_PTE_PAGE_FLAGS_MASK
- RK_PTE_PAGE_READABLE
- RK_PTE_PAGE_VALID
- RK_PTE_PAGE_WRITABLE
- RK_SPDIF_RK3066
- RK_SPDIF_RK3188
- RK_SPDIF_RK3288
- RK_SPDIF_RK3366
- RK_VID_CAP_FUNC_EN_N
- RK_VID_FIFO_FUNC_EN_N
- RL
- RL0
- RL0d
- RL1
- RL1PEAKTH
- RL1d
- RL2
- RL2d
- RL3
- RL4
- RL5C46X_16CTL_LEVEL_1
- RL5C46X_16CTL_LEVEL_2
- RL5C46X_BCR_3E0_ENA
- RL5C46X_BCR_3E2_ENA
- RL5C46X_MISC_A_LOCK
- RL5C46X_MISC_B_LOCK
- RL5C46X_MISC_IFACE_BUSY
- RL5C46X_MISC_PCI_LOCK
- RL5C46X_MISC_PWR_SAVE_2
- RL5C46X_MISC_SUSPEND
- RL5C47X_MISC3_CB_CLKRUN_DIS
- RL5C47X_MISC_5V_DISABLE
- RL5C47X_MISC_IFACE_BUSY
- RL5C47X_MISC_LED_POL
- RL5C47X_MISC_PCI_INT_DIS
- RL5C47X_MISC_PCI_INT_MASK
- RL5C47X_MISC_SRIRQ_ENA
- RL5C47X_MISC_SUBSYS_WR
- RL5C4XX_16BIT_CTL
- RL5C4XX_16BIT_IO_0
- RL5C4XX_16BIT_MEM_0
- RL5C4XX_16CTL_IO_TIMING
- RL5C4XX_16CTL_MEM_TIMING
- RL5C4XX_CMD_MASK
- RL5C4XX_CMD_SHIFT
- RL5C4XX_CONFIG
- RL5C4XX_CONFIG_IO_0_MODE
- RL5C4XX_CONFIG_IO_1_MODE
- RL5C4XX_CONFIG_PREFETCH
- RL5C4XX_HOLD_MASK
- RL5C4XX_HOLD_SHIFT
- RL5C4XX_MISC
- RL5C4XX_MISC3
- RL5C4XX_MISC_CONTROL
- RL5C4XX_MISC_HW_SUSPEND_ENA
- RL5C4XX_MISC_VCCEN_POL
- RL5C4XX_MISC_VPPEN_POL
- RL5C4XX_SETUP_MASK
- RL5C4XX_SETUP_SHIFT
- RL5C4XX_ZV_ENABLE
- RL6231_PLL_INP_MAX
- RL6231_PLL_INP_MIN
- RL6231_PLL_K_MAX
- RL6231_PLL_M_MAX
- RL6231_PLL_N_MAX
- RL6347A_COEF_INDEX
- RL6347A_PROC_COEF
- RL6347A_VENDOR_REGISTERS
- RLBC_H
- RLBC_H2
- RLBC_T
- RLBF0_C
- RLBF0_H
- RLBF0_T
- RLBF1_C
- RLBF1_H
- RLBF1_T
- RLB_ARP_BURST_SIZE
- RLB_HASH_TABLE_SIZE
- RLB_NULL_INDEX
- RLB_PROMISC_TIMEOUT
- RLB_UPDATE_DELAY
- RLB_UPDATE_RETRY
- RLC
- RLCG_UCODE_LOADING_START_ADDRESS
- RLCR
- RLC_AUTO_PG_CTRL
- RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK
- RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT
- RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK
- RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT
- RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK
- RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT
- RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK
- RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT
- RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK
- RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT
- RLC_BUSY
- RLC_BUSY_CLK_CNTL__BUSY_OFF_LATENCY_MASK
- RLC_BUSY_CLK_CNTL__BUSY_OFF_LATENCY__SHIFT
- RLC_BUSY_STATUS
- RLC_CAPTURE_GPU_CLOCK_COUNT
- RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE_MASK
- RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE__SHIFT
- RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED_MASK
- RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED__SHIFT
- RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE_MASK
- RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE__SHIFT
- RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED_MASK
- RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED__SHIFT
- RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK
- RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT
- RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK
- RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT
- RLC_CGCG_CGLS_CTRL
- RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER_MASK
- RLC_CGCG_CGLS_CTRL_3D__CGCG_CONTROLLER__SHIFT
- RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK
- RLC_CGCG_CGLS_CTRL_3D__CGCG_EN__SHIFT
- RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK
- RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT
- RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL_MASK
- RLC_CGCG_CGLS_CTRL_3D__CGCG_REG_CTRL__SHIFT
- RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK
- RLC_CGCG_CGLS_CTRL_3D__CGLS_EN__SHIFT
- RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK
- RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT
- RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN_MASK
- RLC_CGCG_CGLS_CTRL_3D__SIM_SILICON_EN__SHIFT
- RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE_MASK
- RLC_CGCG_CGLS_CTRL_3D__SLEEP_MODE__SHIFT
- RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK
- RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT
- RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK
- RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT
- RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK
- RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT
- RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK
- RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT
- RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK
- RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT
- RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK
- RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT
- RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK
- RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT
- RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK
- RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT
- RLC_CGCG_CGLS_CTRL__SPARE_MASK
- RLC_CGCG_CGLS_CTRL__SPARE__SHIFT
- RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT_MASK
- RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_START_UNIT__SHIFT
- RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT_MASK
- RLC_CGCG_RAMP_CTRL_3D__DOWN_DIV_STEP_UNIT__SHIFT
- RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT_MASK
- RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_CNT__SHIFT
- RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT_MASK
- RLC_CGCG_RAMP_CTRL_3D__STEP_DELAY_UNIT__SHIFT
- RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT_MASK
- RLC_CGCG_RAMP_CTRL_3D__UP_DIV_START_UNIT__SHIFT
- RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT_MASK
- RLC_CGCG_RAMP_CTRL_3D__UP_DIV_STEP_UNIT__SHIFT
- RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK
- RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT
- RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK
- RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT
- RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK
- RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT
- RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK
- RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT
- RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK
- RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT
- RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK
- RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT
- RLC_CGTT_MGCG_OVERRIDE
- RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK
- RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK
- RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK
- RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE__SHIFT
- RLC_CGTT_MGCG_OVERRIDE__CPF_MASK
- RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK
- RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY__SHIFT
- RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK
- RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT
- RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK
- RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT
- RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK
- RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE__SHIFT
- RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK
- RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT
- RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK
- RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT
- RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK
- RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT
- RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK
- RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT
- RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK
- RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK
- RLC_CGTT_MGCG_OVERRIDE__OVERRIDE_MASK
- RLC_CGTT_MGCG_OVERRIDE__OVERRIDE__SHIFT
- RLC_CGTT_MGCG_OVERRIDE__RESERVED_0_MASK
- RLC_CGTT_MGCG_OVERRIDE__RESERVED_0__SHIFT
- RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_9_MASK
- RLC_CGTT_MGCG_OVERRIDE__RESERVED_15_9__SHIFT
- RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17_MASK
- RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_17__SHIFT
- RLC_CGTT_MGCG_OVERRIDE__RESERVED_MASK
- RLC_CGTT_MGCG_OVERRIDE__RESERVED__SHIFT
- RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK
- RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT
- RLC_CGTT_MGCG_OVERRIDE__RLC_MASK
- RLC_CG_REQ_TYPE_MASK
- RLC_CG_REQ_TYPE_SHIFT
- RLC_CLEAR_STATE_DESCRIPTOR_OFFSET
- RLC_CLEAR_STATE_END_MARKER
- RLC_CLEAR_STATE_RESTORE_BASE
- RLC_CLK_CNTL__RESERVED_15_MASK
- RLC_CLK_CNTL__RESERVED_15__SHIFT
- RLC_CLK_CNTL__RESERVED_7_MASK
- RLC_CLK_CNTL__RESERVED_7__SHIFT
- RLC_CLK_CNTL__RESERVED_9_MASK
- RLC_CLK_CNTL__RESERVED_9__SHIFT
- RLC_CLK_CNTL__RESERVED_MASK
- RLC_CLK_CNTL__RESERVED__SHIFT
- RLC_CLK_CNTL__RLC_CMN_CLK_CNTL_MASK
- RLC_CLK_CNTL__RLC_CMN_CLK_CNTL__SHIFT
- RLC_CLK_CNTL__RLC_DFLL_CLK_CNTL_MASK
- RLC_CLK_CNTL__RLC_DFLL_CLK_CNTL__SHIFT
- RLC_CLK_CNTL__RLC_GPM_CLK_CNTL_MASK
- RLC_CLK_CNTL__RLC_GPM_CLK_CNTL__SHIFT
- RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK
- RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT
- RLC_CLK_CNTL__RLC_SPP_CLK_CNTL_MASK
- RLC_CLK_CNTL__RLC_SPP_CLK_CNTL__SHIFT
- RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK
- RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE__SHIFT
- RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK
- RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT
- RLC_CLK_CNTL__RLC_TC_CLK_CNTL_MASK
- RLC_CLK_CNTL__RLC_TC_CLK_CNTL__SHIFT
- RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE_MASK
- RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE__SHIFT
- RLC_CLK_COUNT_CTRL__GFXCLK_RESET_MASK
- RLC_CLK_COUNT_CTRL__GFXCLK_RESET__SHIFT
- RLC_CLK_COUNT_CTRL__GFXCLK_RUN_MASK
- RLC_CLK_COUNT_CTRL__GFXCLK_RUN__SHIFT
- RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE_MASK
- RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE__SHIFT
- RLC_CLK_COUNT_CTRL__REFCLK_RESET_MASK
- RLC_CLK_COUNT_CTRL__REFCLK_RESET__SHIFT
- RLC_CLK_COUNT_CTRL__REFCLK_RUN_MASK
- RLC_CLK_COUNT_CTRL__REFCLK_RUN__SHIFT
- RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE_MASK
- RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE__SHIFT
- RLC_CLK_COUNT_CTRL__RESERVED_MASK
- RLC_CLK_COUNT_CTRL__RESERVED__SHIFT
- RLC_CLK_COUNT_GFXCLK_LSB__COUNTER_MASK
- RLC_CLK_COUNT_GFXCLK_LSB__COUNTER__SHIFT
- RLC_CLK_COUNT_GFXCLK_MSB__COUNTER_MASK
- RLC_CLK_COUNT_GFXCLK_MSB__COUNTER__SHIFT
- RLC_CLK_COUNT_REFCLK_LSB__COUNTER_MASK
- RLC_CLK_COUNT_REFCLK_LSB__COUNTER__SHIFT
- RLC_CLK_COUNT_REFCLK_MSB__COUNTER_MASK
- RLC_CLK_COUNT_REFCLK_MSB__COUNTER__SHIFT
- RLC_CLK_COUNT_STAT__GFXCLK_VALID_MASK
- RLC_CLK_COUNT_STAT__GFXCLK_VALID__SHIFT
- RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC_MASK
- RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC__SHIFT
- RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC_MASK
- RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC__SHIFT
- RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC_MASK
- RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC__SHIFT
- RLC_CLK_COUNT_STAT__REFCLK_VALID_MASK
- RLC_CLK_COUNT_STAT__REFCLK_VALID__SHIFT
- RLC_CLK_COUNT_STAT__RESERVED_MASK
- RLC_CLK_COUNT_STAT__RESERVED__SHIFT
- RLC_CNTL
- RLC_CNTL__FORCE_RETRY_MASK
- RLC_CNTL__FORCE_RETRY__SHIFT
- RLC_CNTL__READ_CACHE_DISABLE_MASK
- RLC_CNTL__READ_CACHE_DISABLE__SHIFT
- RLC_CNTL__RESERVED_MASK
- RLC_CNTL__RESERVED__SHIFT
- RLC_CNTL__RLC_ENABLE_F32_MASK
- RLC_CNTL__RLC_ENABLE_F32__SHIFT
- RLC_CNTL__RLC_STEP_F32_MASK
- RLC_CNTL__RLC_STEP_F32__SHIFT
- RLC_CNTL__SOFT_RESET_DEBUG_MODE_MASK
- RLC_CNTL__SOFT_RESET_DEBUG_MODE__SHIFT
- RLC_CPAXI_DOORBELL_MON_CTRL__EN_MASK
- RLC_CPAXI_DOORBELL_MON_CTRL__EN__SHIFT
- RLC_CPAXI_DOORBELL_MON_CTRL__ID_MASK
- RLC_CPAXI_DOORBELL_MON_CTRL__ID__SHIFT
- RLC_CPAXI_DOORBELL_MON_DATA_LSB__DATA_MASK
- RLC_CPAXI_DOORBELL_MON_DATA_LSB__DATA__SHIFT
- RLC_CPAXI_DOORBELL_MON_DATA_MSB__DATA_MASK
- RLC_CPAXI_DOORBELL_MON_DATA_MSB__DATA__SHIFT
- RLC_CPAXI_DOORBELL_MON_STAT__ADDR_MASK
- RLC_CPAXI_DOORBELL_MON_STAT__ADDR__SHIFT
- RLC_CPAXI_DOORBELL_MON_STAT__ID_MATCH_MASK
- RLC_CPAXI_DOORBELL_MON_STAT__ID_MATCH__SHIFT
- RLC_CPAXI_DOORBELL_MON_STAT__MATCH_CLEAR_MASK
- RLC_CPAXI_DOORBELL_MON_STAT__MATCH_CLEAR__SHIFT
- RLC_CPG_STAT_INVAL__CPG_stat_inval_MASK
- RLC_CPG_STAT_INVAL__CPG_stat_inval__SHIFT
- RLC_CP_EOF_INT_CNT__CNT_MASK
- RLC_CP_EOF_INT_CNT__CNT__SHIFT
- RLC_CP_EOF_INT__INTERRUPT_MASK
- RLC_CP_EOF_INT__INTERRUPT__SHIFT
- RLC_CP_EOF_INT__RESERVED_MASK
- RLC_CP_EOF_INT__RESERVED__SHIFT
- RLC_CP_RESPONSE0__RESPONSE_MASK
- RLC_CP_RESPONSE0__RESPONSE__SHIFT
- RLC_CP_RESPONSE1__RESPONSE_MASK
- RLC_CP_RESPONSE1__RESPONSE__SHIFT
- RLC_CP_RESPONSE2__RESPONSE_MASK
- RLC_CP_RESPONSE2__RESPONSE__SHIFT
- RLC_CP_RESPONSE3__RESPONSE_MASK
- RLC_CP_RESPONSE3__RESPONSE__SHIFT
- RLC_CP_SCHEDULERS__scheduler0_MASK
- RLC_CP_SCHEDULERS__scheduler0__SHIFT
- RLC_CP_SCHEDULERS__scheduler1_MASK
- RLC_CP_SCHEDULERS__scheduler1__SHIFT
- RLC_CP_SCHEDULERS__scheduler2_MASK
- RLC_CP_SCHEDULERS__scheduler2__SHIFT
- RLC_CP_SCHEDULERS__scheduler3_MASK
- RLC_CP_SCHEDULERS__scheduler3__SHIFT
- RLC_CP_STAT_INVAL_CTRL__CPC_STAT_INVAL_PEND_EN_MASK
- RLC_CP_STAT_INVAL_CTRL__CPC_STAT_INVAL_PEND_EN__SHIFT
- RLC_CP_STAT_INVAL_CTRL__CPF_STAT_INVAL_PEND_EN_MASK
- RLC_CP_STAT_INVAL_CTRL__CPF_STAT_INVAL_PEND_EN__SHIFT
- RLC_CP_STAT_INVAL_CTRL__CPG_STAT_INVAL_PEND_EN_MASK
- RLC_CP_STAT_INVAL_CTRL__CPG_STAT_INVAL_PEND_EN__SHIFT
- RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_CHANGED_MASK
- RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_CHANGED__SHIFT
- RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND_MASK
- RLC_CP_STAT_INVAL_STAT__CPC_STAT_INVAL_PEND__SHIFT
- RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_CHANGED_MASK
- RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_CHANGED__SHIFT
- RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND_MASK
- RLC_CP_STAT_INVAL_STAT__CPF_STAT_INVAL_PEND__SHIFT
- RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_CHANGED_MASK
- RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_CHANGED__SHIFT
- RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND_MASK
- RLC_CP_STAT_INVAL_STAT__CPG_STAT_INVAL_PEND__SHIFT
- RLC_CP_TABLE_RESTORE
- RLC_CSIB_ADDR_HI__ADDRESS_MASK
- RLC_CSIB_ADDR_HI__ADDRESS__SHIFT
- RLC_CSIB_ADDR_LO__ADDRESS_MASK
- RLC_CSIB_ADDR_LO__ADDRESS__SHIFT
- RLC_CSIB_LENGTH__LENGTH_MASK
- RLC_CSIB_LENGTH__LENGTH__SHIFT
- RLC_CU_STATUS__WORK_PENDING_MASK
- RLC_CU_STATUS__WORK_PENDING__SHIFT
- RLC_DEBUG_SELECT__RESERVED_MASK
- RLC_DEBUG_SELECT__RESERVED__SHIFT
- RLC_DEBUG_SELECT__SELECT_MASK
- RLC_DEBUG_SELECT__SELECT__SHIFT
- RLC_DEBUG__DATA_MASK
- RLC_DEBUG__DATA__SHIFT
- RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK_MASK
- RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK__SHIFT
- RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST_MASK
- RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST__SHIFT
- RLC_DRIVER_CPDMA_STATUS__RESERVED1_MASK
- RLC_DRIVER_CPDMA_STATUS__RESERVED1__SHIFT
- RLC_DRIVER_CPDMA_STATUS__RESERVED_MASK
- RLC_DRIVER_CPDMA_STATUS__RESERVED__SHIFT
- RLC_DRIVER_DMA_STATUS
- RLC_DSM_TRIG__START_MASK
- RLC_DSM_TRIG__START__SHIFT
- RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK
- RLC_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT
- RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK
- RLC_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT
- RLC_DS_CNTL__RESRVED_1_MASK
- RLC_DS_CNTL__RESRVED_1__SHIFT
- RLC_DS_CNTL__RESRVED_MASK
- RLC_DS_CNTL__RESRVED__SHIFT
- RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK
- RLC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT
- RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK
- RLC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT
- RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK
- RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT
- RLC_DYN_PG_REQUEST__PG_REQUEST_WGP_MASK_MASK
- RLC_DYN_PG_REQUEST__PG_REQUEST_WGP_MASK__SHIFT
- RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK
- RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT
- RLC_DYN_PG_STATUS__PG_STATUS_WGP_MASK_MASK
- RLC_DYN_PG_STATUS__PG_STATUS_WGP_MASK__SHIFT
- RLC_ENABLE
- RLC_F32_UCODE_VERSION__THREAD0_VERSION_MASK
- RLC_F32_UCODE_VERSION__THREAD0_VERSION__SHIFT
- RLC_F32_UCODE_VERSION__THREAD1_VERSION_MASK
- RLC_F32_UCODE_VERSION__THREAD1_VERSION__SHIFT
- RLC_F32_UCODE_VERSION__THREAD2_VERSION_MASK
- RLC_F32_UCODE_VERSION__THREAD2_VERSION__SHIFT
- RLC_FIREWALL_VIOLATION__ADDR_MASK
- RLC_FIREWALL_VIOLATION__ADDR__SHIFT
- RLC_FormatDirectRegListLength
- RLC_GCPM_GENERAL_3
- RLC_GFX_INDEX
- RLC_GFX_RM_CNTL_ADJ__RESERVED_MASK
- RLC_GFX_RM_CNTL_ADJ__RESERVED__SHIFT
- RLC_GFX_RM_CNTL_ADJ__RLC_GFX_RM_VALID_MASK
- RLC_GFX_RM_CNTL_ADJ__RLC_GFX_RM_VALID__SHIFT
- RLC_GFX_RM_CNTL__RESERVED_MASK
- RLC_GFX_RM_CNTL__RESERVED__SHIFT
- RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID_MASK
- RLC_GFX_RM_CNTL__RLC_GFX_RM_VALID__SHIFT
- RLC_GPM_BUSY
- RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK
- RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT
- RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK
- RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT
- RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK
- RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT
- RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK
- RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT
- RLC_GPM_CU_PD_TIMEOUT__TIMEOUT_MASK
- RLC_GPM_CU_PD_TIMEOUT__TIMEOUT__SHIFT
- RLC_GPM_DEBUG_INST_ADDR__ADDR_B_MASK
- RLC_GPM_DEBUG_INST_ADDR__ADDR_B__SHIFT
- RLC_GPM_DEBUG_INST_ADDR__ADRR_A_MASK
- RLC_GPM_DEBUG_INST_ADDR__ADRR_A__SHIFT
- RLC_GPM_DEBUG_INST_A__INST_A_MASK
- RLC_GPM_DEBUG_INST_A__INST_A__SHIFT
- RLC_GPM_DEBUG_INST_B__INST_B_MASK
- RLC_GPM_DEBUG_INST_B__INST_B__SHIFT
- RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT_MASK
- RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT__SHIFT
- RLC_GPM_DEBUG_SELECT__RESERVED_MASK
- RLC_GPM_DEBUG_SELECT__RESERVED__SHIFT
- RLC_GPM_DEBUG_SELECT__SELECT_MASK
- RLC_GPM_DEBUG_SELECT__SELECT__SHIFT
- RLC_GPM_DEBUG__DATA_MASK
- RLC_GPM_DEBUG__DATA__SHIFT
- RLC_GPM_GENERAL_0__DATA_MASK
- RLC_GPM_GENERAL_0__DATA__SHIFT
- RLC_GPM_GENERAL_10__DATA_MASK
- RLC_GPM_GENERAL_10__DATA__SHIFT
- RLC_GPM_GENERAL_11__DATA_MASK
- RLC_GPM_GENERAL_11__DATA__SHIFT
- RLC_GPM_GENERAL_12__DATA_MASK
- RLC_GPM_GENERAL_12__DATA__SHIFT
- RLC_GPM_GENERAL_13__DATA_MASK
- RLC_GPM_GENERAL_13__DATA__SHIFT
- RLC_GPM_GENERAL_14__DATA_MASK
- RLC_GPM_GENERAL_14__DATA__SHIFT
- RLC_GPM_GENERAL_15__DATA_MASK
- RLC_GPM_GENERAL_15__DATA__SHIFT
- RLC_GPM_GENERAL_1__DATA_MASK
- RLC_GPM_GENERAL_1__DATA__SHIFT
- RLC_GPM_GENERAL_2__DATA_MASK
- RLC_GPM_GENERAL_2__DATA__SHIFT
- RLC_GPM_GENERAL_3__DATA_MASK
- RLC_GPM_GENERAL_3__DATA__SHIFT
- RLC_GPM_GENERAL_4__DATA_MASK
- RLC_GPM_GENERAL_4__DATA__SHIFT
- RLC_GPM_GENERAL_5__DATA_MASK
- RLC_GPM_GENERAL_5__DATA__SHIFT
- RLC_GPM_GENERAL_6__DATA_MASK
- RLC_GPM_GENERAL_6__DATA__SHIFT
- RLC_GPM_GENERAL_7__DATA_MASK
- RLC_GPM_GENERAL_7__DATA__SHIFT
- RLC_GPM_GENERAL_8__DATA_MASK
- RLC_GPM_GENERAL_8__DATA__SHIFT
- RLC_GPM_GENERAL_9__DATA_MASK
- RLC_GPM_GENERAL_9__DATA__SHIFT
- RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK
- RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT
- RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK
- RLC_GPM_INT_DISABLE_TH1__DISABLE__SHIFT
- RLC_GPM_INT_FORCE_TH0__FORCE_MASK
- RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT
- RLC_GPM_INT_FORCE_TH1__FORCE_MASK
- RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT
- RLC_GPM_INT_STAT_TH0__STATUS_MASK
- RLC_GPM_INT_STAT_TH0__STATUS__SHIFT
- RLC_GPM_IRAM_ADDR__ADDR_MASK
- RLC_GPM_IRAM_ADDR__ADDR__SHIFT
- RLC_GPM_IRAM_DATA__DATA_MASK
- RLC_GPM_IRAM_DATA__DATA__SHIFT
- RLC_GPM_LOG_ADDR__ADDR_MASK
- RLC_GPM_LOG_ADDR__ADDR__SHIFT
- RLC_GPM_LOG_CONT__CONT_MASK
- RLC_GPM_LOG_CONT__CONT__SHIFT
- RLC_GPM_LOG_SIZE__SIZE_MASK
- RLC_GPM_LOG_SIZE__SIZE__SHIFT
- RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK
- RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT
- RLC_GPM_PERF_COUNT_0__ENABLE_MASK
- RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT
- RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK
- RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT
- RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK
- RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT
- RLC_GPM_PERF_COUNT_0__RESERVED_MASK
- RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT
- RLC_GPM_PERF_COUNT_0__SA_INDEX_MASK
- RLC_GPM_PERF_COUNT_0__SA_INDEX__SHIFT
- RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK
- RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT
- RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK
- RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT
- RLC_GPM_PERF_COUNT_0__UNUSED_MASK
- RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT
- RLC_GPM_PERF_COUNT_0__WGP_INDEX_MASK
- RLC_GPM_PERF_COUNT_0__WGP_INDEX__SHIFT
- RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK
- RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT
- RLC_GPM_PERF_COUNT_1__ENABLE_MASK
- RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT
- RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK
- RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT
- RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK
- RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT
- RLC_GPM_PERF_COUNT_1__RESERVED_MASK
- RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT
- RLC_GPM_PERF_COUNT_1__SA_INDEX_MASK
- RLC_GPM_PERF_COUNT_1__SA_INDEX__SHIFT
- RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK
- RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT
- RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK
- RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT
- RLC_GPM_PERF_COUNT_1__UNUSED_MASK
- RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT
- RLC_GPM_PERF_COUNT_1__WGP_INDEX_MASK
- RLC_GPM_PERF_COUNT_1__WGP_INDEX__SHIFT
- RLC_GPM_SCRATCH_ADDR
- RLC_GPM_SCRATCH_ADDR__ADDR_MASK
- RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT
- RLC_GPM_SCRATCH_ADDR__RESERVED_MASK
- RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT
- RLC_GPM_SCRATCH_DATA
- RLC_GPM_SCRATCH_DATA__DATA_MASK
- RLC_GPM_SCRATCH_DATA__DATA__SHIFT
- RLC_GPM_STAT
- RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK
- RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT
- RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK
- RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT
- RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK
- RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT
- RLC_GPM_STAT__CMP_power_status_MASK
- RLC_GPM_STAT__CMP_power_status__SHIFT
- RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK
- RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT
- RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK
- RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT
- RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK
- RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT
- RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK
- RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT
- RLC_GPM_STAT__DYN_WGP_POWERING_DOWN_MASK
- RLC_GPM_STAT__DYN_WGP_POWERING_DOWN__SHIFT
- RLC_GPM_STAT__DYN_WGP_POWERING_UP_MASK
- RLC_GPM_STAT__DYN_WGP_POWERING_UP__SHIFT
- RLC_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK
- RLC_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT
- RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK
- RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT
- RLC_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK
- RLC_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT
- RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK
- RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT
- RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK
- RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT
- RLC_GPM_STAT__GFX_LS_STATUS_3D_MASK
- RLC_GPM_STAT__GFX_LS_STATUS_3D__SHIFT
- RLC_GPM_STAT__GFX_LS_STATUS_MASK
- RLC_GPM_STAT__GFX_LS_STATUS__SHIFT
- RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK
- RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT
- RLC_GPM_STAT__GFX_POWER_STATUS_MASK
- RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT
- RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK
- RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT
- RLC_GPM_STAT__PG_ERROR_STATUS_MASK
- RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT
- RLC_GPM_STAT__RESERVED_MASK
- RLC_GPM_STAT__RESERVED__SHIFT
- RLC_GPM_STAT__RESTORING_REGISTERS_MASK
- RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT
- RLC_GPM_STAT__RLC_BUSY_MASK
- RLC_GPM_STAT__RLC_BUSY__SHIFT
- RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK
- RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT
- RLC_GPM_STAT__SAVING_REGISTERS_MASK
- RLC_GPM_STAT__SAVING_REGISTERS__SHIFT
- RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK
- RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT
- RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK
- RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT
- RLC_GPM_STAT__STATIC_WGP_POWERING_DOWN_MASK
- RLC_GPM_STAT__STATIC_WGP_POWERING_DOWN__SHIFT
- RLC_GPM_STAT__STATIC_WGP_POWERING_UP_MASK
- RLC_GPM_STAT__STATIC_WGP_POWERING_UP__SHIFT
- RLC_GPM_THREAD_ENABLE__RESERVED_MASK
- RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT
- RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK
- RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT
- RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK
- RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT
- RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK
- RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT
- RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK
- RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT
- RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK
- RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT
- RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK
- RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT
- RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK
- RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT
- RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK
- RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT
- RLC_GPM_THREAD_RESET__RESERVED_MASK
- RLC_GPM_THREAD_RESET__RESERVED__SHIFT
- RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK
- RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT
- RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK
- RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT
- RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK
- RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT
- RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK
- RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT
- RLC_GPM_TIMER_CTRL__RESERVED_MASK
- RLC_GPM_TIMER_CTRL__RESERVED__SHIFT
- RLC_GPM_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK
- RLC_GPM_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT
- RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK
- RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT
- RLC_GPM_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK
- RLC_GPM_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT
- RLC_GPM_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK
- RLC_GPM_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT
- RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK
- RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT
- RLC_GPM_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK
- RLC_GPM_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT
- RLC_GPM_TIMER_CTRL__TIMER_2_AUTO_REARM_MASK
- RLC_GPM_TIMER_CTRL__TIMER_2_AUTO_REARM__SHIFT
- RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK
- RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT
- RLC_GPM_TIMER_CTRL__TIMER_2_INT_CLEAR_MASK
- RLC_GPM_TIMER_CTRL__TIMER_2_INT_CLEAR__SHIFT
- RLC_GPM_TIMER_CTRL__TIMER_3_AUTO_REARM_MASK
- RLC_GPM_TIMER_CTRL__TIMER_3_AUTO_REARM__SHIFT
- RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK
- RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT
- RLC_GPM_TIMER_CTRL__TIMER_3_INT_CLEAR_MASK
- RLC_GPM_TIMER_CTRL__TIMER_3_INT_CLEAR__SHIFT
- RLC_GPM_TIMER_INT_0__TIMER_MASK
- RLC_GPM_TIMER_INT_0__TIMER__SHIFT
- RLC_GPM_TIMER_INT_1__TIMER_MASK
- RLC_GPM_TIMER_INT_1__TIMER__SHIFT
- RLC_GPM_TIMER_INT_2__TIMER_MASK
- RLC_GPM_TIMER_INT_2__TIMER__SHIFT
- RLC_GPM_TIMER_INT_3__TIMER_MASK
- RLC_GPM_TIMER_INT_3__TIMER__SHIFT
- RLC_GPM_TIMER_STAT__RESERVED_MASK
- RLC_GPM_TIMER_STAT__RESERVED__SHIFT
- RLC_GPM_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK
- RLC_GPM_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT
- RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK
- RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT
- RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK
- RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT
- RLC_GPM_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK
- RLC_GPM_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT
- RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK
- RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT
- RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK
- RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT
- RLC_GPM_TIMER_STAT__TIMER_2_AUTO_REARM_SYNC_MASK
- RLC_GPM_TIMER_STAT__TIMER_2_AUTO_REARM_SYNC__SHIFT
- RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC_MASK
- RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC__SHIFT
- RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK
- RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT
- RLC_GPM_TIMER_STAT__TIMER_3_AUTO_REARM_SYNC_MASK
- RLC_GPM_TIMER_STAT__TIMER_3_AUTO_REARM_SYNC__SHIFT
- RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC_MASK
- RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC__SHIFT
- RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK
- RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT
- RLC_GPM_UCODE_ADDR
- RLC_GPM_UCODE_ADDR__RESERVED_MASK
- RLC_GPM_UCODE_ADDR__RESERVED__SHIFT
- RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK
- RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT
- RLC_GPM_UCODE_DATA
- RLC_GPM_UCODE_DATA__UCODE_DATA_MASK
- RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT
- RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK
- RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT
- RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK
- RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT
- RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY_MASK
- RLC_GPM_UTCL1_CNTL_0__FORCE_SD_VMID_DIRTY__SHIFT
- RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK
- RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT
- RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK
- RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT
- RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK
- RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT
- RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK
- RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT
- RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK
- RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT
- RLC_GPM_UTCL1_CNTL_1__BYPASS_MASK
- RLC_GPM_UTCL1_CNTL_1__BYPASS__SHIFT
- RLC_GPM_UTCL1_CNTL_1__DROP_MODE_MASK
- RLC_GPM_UTCL1_CNTL_1__DROP_MODE__SHIFT
- RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY_MASK
- RLC_GPM_UTCL1_CNTL_1__FORCE_SD_VMID_DIRTY__SHIFT
- RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP_MASK
- RLC_GPM_UTCL1_CNTL_1__FORCE_SNOOP__SHIFT
- RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE_MASK
- RLC_GPM_UTCL1_CNTL_1__FRAG_LIMIT_MODE__SHIFT
- RLC_GPM_UTCL1_CNTL_1__INVALIDATE_MASK
- RLC_GPM_UTCL1_CNTL_1__INVALIDATE__SHIFT
- RLC_GPM_UTCL1_CNTL_1__RESERVED_MASK
- RLC_GPM_UTCL1_CNTL_1__RESERVED__SHIFT
- RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT_MASK
- RLC_GPM_UTCL1_CNTL_1__XNACK_REDO_TIMER_CNT__SHIFT
- RLC_GPM_UTCL1_CNTL_2__BYPASS_MASK
- RLC_GPM_UTCL1_CNTL_2__BYPASS__SHIFT
- RLC_GPM_UTCL1_CNTL_2__DROP_MODE_MASK
- RLC_GPM_UTCL1_CNTL_2__DROP_MODE__SHIFT
- RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY_MASK
- RLC_GPM_UTCL1_CNTL_2__FORCE_SD_VMID_DIRTY__SHIFT
- RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP_MASK
- RLC_GPM_UTCL1_CNTL_2__FORCE_SNOOP__SHIFT
- RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE_MASK
- RLC_GPM_UTCL1_CNTL_2__FRAG_LIMIT_MODE__SHIFT
- RLC_GPM_UTCL1_CNTL_2__INVALIDATE_MASK
- RLC_GPM_UTCL1_CNTL_2__INVALIDATE__SHIFT
- RLC_GPM_UTCL1_CNTL_2__RESERVED_MASK
- RLC_GPM_UTCL1_CNTL_2__RESERVED__SHIFT
- RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT_MASK
- RLC_GPM_UTCL1_CNTL_2__XNACK_REDO_TIMER_CNT__SHIFT
- RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK
- RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT
- RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK
- RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT
- RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK
- RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT
- RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK
- RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT
- RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK
- RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT
- RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid_MASK
- RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqErrorVmid__SHIFT
- RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError_MASK
- RLC_GPM_UTCL1_TH1_ERROR_1__Translated_ReqError__SHIFT
- RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK
- RLC_GPM_UTCL1_TH1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT
- RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB_MASK
- RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT
- RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid_MASK
- RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqErrorVmid__SHIFT
- RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError_MASK
- RLC_GPM_UTCL1_TH2_ERROR_1__Translated_ReqError__SHIFT
- RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB_MASK
- RLC_GPM_UTCL1_TH2_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT
- RLC_GPM_VMID_THREAD0__RESERVED0_MASK
- RLC_GPM_VMID_THREAD0__RESERVED0__SHIFT
- RLC_GPM_VMID_THREAD0__RESERVED1_MASK
- RLC_GPM_VMID_THREAD0__RESERVED1__SHIFT
- RLC_GPM_VMID_THREAD0__RESERVED_MASK
- RLC_GPM_VMID_THREAD0__RESERVED__SHIFT
- RLC_GPM_VMID_THREAD0__RLC_QUEUEID_MASK
- RLC_GPM_VMID_THREAD0__RLC_QUEUEID__SHIFT
- RLC_GPM_VMID_THREAD0__RLC_VMID_MASK
- RLC_GPM_VMID_THREAD0__RLC_VMID__SHIFT
- RLC_GPM_VMID_THREAD1__RESERVED0_MASK
- RLC_GPM_VMID_THREAD1__RESERVED0__SHIFT
- RLC_GPM_VMID_THREAD1__RESERVED1_MASK
- RLC_GPM_VMID_THREAD1__RESERVED1__SHIFT
- RLC_GPM_VMID_THREAD1__RESERVED_MASK
- RLC_GPM_VMID_THREAD1__RESERVED__SHIFT
- RLC_GPM_VMID_THREAD1__RLC_QUEUEID_MASK
- RLC_GPM_VMID_THREAD1__RLC_QUEUEID__SHIFT
- RLC_GPM_VMID_THREAD1__RLC_VMID_MASK
- RLC_GPM_VMID_THREAD1__RLC_VMID__SHIFT
- RLC_GPM_VMID_THREAD2__RESERVED0_MASK
- RLC_GPM_VMID_THREAD2__RESERVED0__SHIFT
- RLC_GPM_VMID_THREAD2__RESERVED1_MASK
- RLC_GPM_VMID_THREAD2__RESERVED1__SHIFT
- RLC_GPM_VMID_THREAD2__RLC_QUEUEID_MASK
- RLC_GPM_VMID_THREAD2__RLC_QUEUEID__SHIFT
- RLC_GPM_VMID_THREAD2__RLC_VMID_MASK
- RLC_GPM_VMID_THREAD2__RLC_VMID__SHIFT
- RLC_GPR_REG1__DATA_MASK
- RLC_GPR_REG1__DATA__SHIFT
- RLC_GPR_REG2
- RLC_GPR_REG2__DATA_MASK
- RLC_GPR_REG2__DATA__SHIFT
- RLC_GPR_REG2__MESSAGE_MASK
- RLC_GPR_REG2__MESSAGE__SHIFT
- RLC_GPR_REG2__REQ_MASK
- RLC_GPR_REG2__REQ__SHIFT
- RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK
- RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT
- RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK
- RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT
- RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK
- RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT
- RLC_GPU_CLOCK_COUNT_LSB
- RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB_MASK
- RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB__SHIFT
- RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB_MASK
- RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB__SHIFT
- RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK
- RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT
- RLC_GPU_CLOCK_COUNT_MSB
- RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB_MASK
- RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB__SHIFT
- RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB_MASK
- RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB__SHIFT
- RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK
- RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT
- RLC_GPU_CLOCK_COUNT_SPM_LSB__GPU_CLOCKS_LSB_MASK
- RLC_GPU_CLOCK_COUNT_SPM_LSB__GPU_CLOCKS_LSB__SHIFT
- RLC_GPU_CLOCK_COUNT_SPM_MSB__GPU_CLOCKS_MSB_MASK
- RLC_GPU_CLOCK_COUNT_SPM_MSB__GPU_CLOCKS_MSB__SHIFT
- RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK
- RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT
- RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK
- RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT
- RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK
- RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT
- RLC_GPU_IOV_CFG_REG10__RESERVED_MASK
- RLC_GPU_IOV_CFG_REG10__RESERVED__SHIFT
- RLC_GPU_IOV_CFG_REG10__TIME_QUANTA_PF_MASK
- RLC_GPU_IOV_CFG_REG10__TIME_QUANTA_PF__SHIFT
- RLC_GPU_IOV_CFG_REG11__YIELD_MASK
- RLC_GPU_IOV_CFG_REG11__YIELD__SHIFT
- RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF0_MASK
- RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF0__SHIFT
- RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF1_MASK
- RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF1__SHIFT
- RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF2_MASK
- RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF2__SHIFT
- RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF3_MASK
- RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF3__SHIFT
- RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF4_MASK
- RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF4__SHIFT
- RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF5_MASK
- RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF5__SHIFT
- RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF6_MASK
- RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF6__SHIFT
- RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF7_MASK
- RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF7__SHIFT
- RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF10_MASK
- RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF10__SHIFT
- RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF11_MASK
- RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF11__SHIFT
- RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF8_MASK
- RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF8__SHIFT
- RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF9_MASK
- RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF9__SHIFT
- RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF12_MASK
- RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF12__SHIFT
- RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF13_MASK
- RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF13__SHIFT
- RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF14_MASK
- RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF14__SHIFT
- RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF15_MASK
- RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF15__SHIFT
- RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK
- RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT
- RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK
- RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT
- RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK
- RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT
- RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK
- RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT
- RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK
- RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT
- RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK
- RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT
- RLC_GPU_IOV_CFG_REG1__RESERVED_MASK
- RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT
- RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK
- RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT
- RLC_GPU_IOV_CFG_REG2__RESERVED_MASK
- RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT
- RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK
- RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT
- RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK
- RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT
- RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK
- RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT
- RLC_GPU_IOV_CFG_REG6__RESERVED_MASK
- RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT
- RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK
- RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT
- RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_MASK
- RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_STATUS_MASK
- RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_STATUS__SHIFT
- RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID__SHIFT
- RLC_GPU_IOV_CFG_REG9__RESERVED_MASK
- RLC_GPU_IOV_CFG_REG9__RESERVED__SHIFT
- RLC_GPU_IOV_F32_CNTL__ENABLE_MASK
- RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT
- RLC_GPU_IOV_F32_CNTL__RESERVED_MASK
- RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT
- RLC_GPU_IOV_F32_RESET__RESERVED_MASK
- RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT
- RLC_GPU_IOV_F32_RESET__RESET_MASK
- RLC_GPU_IOV_F32_RESET__RESET__SHIFT
- RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK
- RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT
- RLC_GPU_IOV_INT_FORCE__FORCE_MASK
- RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT
- RLC_GPU_IOV_INT_STAT__STATUS_MASK
- RLC_GPU_IOV_INT_STAT__STATUS__SHIFT
- RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK
- RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT
- RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK
- RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT
- RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK
- RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT
- RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK
- RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT
- RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK
- RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT
- RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK
- RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT
- RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK
- RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT
- RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK
- RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT
- RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK
- RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT
- RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK
- RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT
- RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK
- RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT
- RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK
- RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT
- RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK
- RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT
- RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK
- RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT
- RLC_GPU_IOV_SCH_0__DATA_MASK
- RLC_GPU_IOV_SCH_0__DATA__SHIFT
- RLC_GPU_IOV_SCH_1__DATA_MASK
- RLC_GPU_IOV_SCH_1__DATA__SHIFT
- RLC_GPU_IOV_SCH_2__DATA_MASK
- RLC_GPU_IOV_SCH_2__DATA__SHIFT
- RLC_GPU_IOV_SCH_3__DATA_MASK
- RLC_GPU_IOV_SCH_3__DATA__SHIFT
- RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK
- RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT
- RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK
- RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT
- RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK
- RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT
- RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK
- RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT
- RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK
- RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT
- RLC_GPU_IOV_SCH_INT__interrupt_MASK
- RLC_GPU_IOV_SCH_INT__interrupt__SHIFT
- RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK
- RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT
- RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK
- RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT
- RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK
- RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT
- RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK
- RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT
- RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK
- RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT
- RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK
- RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT
- RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK
- RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT
- RLC_GPU_IOV_SDMA0_STATUS__RESERVED_11_9_MASK
- RLC_GPU_IOV_SDMA0_STATUS__RESERVED_11_9__SHIFT
- RLC_GPU_IOV_SDMA0_STATUS__RESERVED_31_13_MASK
- RLC_GPU_IOV_SDMA0_STATUS__RESERVED_31_13__SHIFT
- RLC_GPU_IOV_SDMA0_STATUS__RESERVED_7_1_MASK
- RLC_GPU_IOV_SDMA0_STATUS__RESERVED_7_1__SHIFT
- RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK
- RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT
- RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK
- RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT
- RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK
- RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT
- RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK
- RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT
- RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK
- RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT
- RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK
- RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT
- RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK
- RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT
- RLC_GPU_IOV_SDMA1_STATUS__RESERVED_11_9_MASK
- RLC_GPU_IOV_SDMA1_STATUS__RESERVED_11_9__SHIFT
- RLC_GPU_IOV_SDMA1_STATUS__RESERVED_31_13_MASK
- RLC_GPU_IOV_SDMA1_STATUS__RESERVED_31_13__SHIFT
- RLC_GPU_IOV_SDMA1_STATUS__RESERVED_7_1_MASK
- RLC_GPU_IOV_SDMA1_STATUS__RESERVED_7_1__SHIFT
- RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK
- RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT
- RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK
- RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT
- RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK
- RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT
- RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK
- RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT
- RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK
- RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT
- RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK
- RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT
- RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK
- RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT
- RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK
- RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT
- RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED_MASK
- RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__RESERVED__SHIFT
- RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK
- RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT
- RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK
- RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT
- RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED_MASK
- RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__RESERVED__SHIFT
- RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK
- RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT
- RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK
- RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT
- RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED_MASK
- RLC_GPU_IOV_VF_DOORBELL_STATUS__RESERVED__SHIFT
- RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK
- RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT
- RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK
- RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT
- RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK
- RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT
- RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK
- RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT
- RLC_GPU_IOV_VF_MASK__RESERVED_MASK
- RLC_GPU_IOV_VF_MASK__RESERVED__SHIFT
- RLC_GPU_IOV_VF_MASK__VF_MASK_MASK
- RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT
- RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK
- RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT
- RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK
- RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT
- RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK
- RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT
- RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK
- RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT
- RLC_GTS_OFFSET_LSB__DATA_MASK
- RLC_GTS_OFFSET_LSB__DATA__SHIFT
- RLC_GTS_OFFSET_MSB__DATA_MASK
- RLC_GTS_OFFSET_MSB__DATA__SHIFT
- RLC_HB_BASE
- RLC_HB_CNTL
- RLC_HB_RPTR
- RLC_HB_WPTR
- RLC_HB_WPTR_LSB_ADDR
- RLC_HB_WPTR_MSB_ADDR
- RLC_HYP_BOOTLOAD_ADDR_HI__ADDR_HI_MASK
- RLC_HYP_BOOTLOAD_ADDR_HI__ADDR_HI__SHIFT
- RLC_HYP_BOOTLOAD_ADDR_LO__ADDR_LO_MASK
- RLC_HYP_BOOTLOAD_ADDR_LO__ADDR_LO__SHIFT
- RLC_HYP_BOOTLOAD_SIZE__SIZE_MASK
- RLC_HYP_BOOTLOAD_SIZE__SIZE__SHIFT
- RLC_HYP_GPM_UCODE_ADDR__RESERVED_MASK
- RLC_HYP_GPM_UCODE_ADDR__RESERVED__SHIFT
- RLC_HYP_GPM_UCODE_ADDR__UCODE_ADDR_MASK
- RLC_HYP_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT
- RLC_HYP_GPM_UCODE_DATA__UCODE_DATA_MASK
- RLC_HYP_GPM_UCODE_DATA__UCODE_DATA__SHIFT
- RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK
- RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT__SHIFT
- RLC_HYP_RESET_VECTOR__RESERVED_4_MASK
- RLC_HYP_RESET_VECTOR__RESERVED_4__SHIFT
- RLC_HYP_RESET_VECTOR__RESERVED_5_MASK
- RLC_HYP_RESET_VECTOR__RESERVED_5__SHIFT
- RLC_HYP_RESET_VECTOR__RESERVED_6_MASK
- RLC_HYP_RESET_VECTOR__RESERVED_6__SHIFT
- RLC_HYP_RESET_VECTOR__RESERVED_7_MASK
- RLC_HYP_RESET_VECTOR__RESERVED_7__SHIFT
- RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK
- RLC_HYP_RESET_VECTOR__VDDGFX_EXIT__SHIFT
- RLC_HYP_RESET_VECTOR__VF_FLR_EXIT_MASK
- RLC_HYP_RESET_VECTOR__VF_FLR_EXIT__SHIFT
- RLC_HYP_RESET_VECTOR__WARM_RESET_EXIT_MASK
- RLC_HYP_RESET_VECTOR__WARM_RESET_EXIT__SHIFT
- RLC_HYP_RLCG_UCODE_CHKSUM__UCODE_CHKSUM_MASK
- RLC_HYP_RLCG_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT
- RLC_HYP_RLCP_UCODE_CHKSUM__UCODE_CHKSUM_MASK
- RLC_HYP_RLCP_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT
- RLC_HYP_RLCV_UCODE_CHKSUM__UCODE_CHKSUM_MASK
- RLC_HYP_RLCV_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT
- RLC_HYP_SEMAPHORE_0__CLIENT_ID_MASK
- RLC_HYP_SEMAPHORE_0__CLIENT_ID__SHIFT
- RLC_HYP_SEMAPHORE_0__RESERVED_MASK
- RLC_HYP_SEMAPHORE_0__RESERVED__SHIFT
- RLC_HYP_SEMAPHORE_1__CLIENT_ID_MASK
- RLC_HYP_SEMAPHORE_1__CLIENT_ID__SHIFT
- RLC_HYP_SEMAPHORE_1__RESERVED_MASK
- RLC_HYP_SEMAPHORE_1__RESERVED__SHIFT
- RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK
- RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT
- RLC_HYP_SEMAPHORE_2__RESERVED_MASK
- RLC_HYP_SEMAPHORE_2__RESERVED__SHIFT
- RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK
- RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT
- RLC_HYP_SEMAPHORE_3__RESERVED_MASK
- RLC_HYP_SEMAPHORE_3__RESERVED__SHIFT
- RLC_IH_COOKIE_CNTL__CREDIT_MASK
- RLC_IH_COOKIE_CNTL__CREDIT__SHIFT
- RLC_IH_COOKIE_CNTL__RESET_COUNTER_MASK
- RLC_IH_COOKIE_CNTL__RESET_COUNTER__SHIFT
- RLC_IH_COOKIE__DATA_MASK
- RLC_IH_COOKIE__DATA__SHIFT
- RLC_IH_SRC_ID_END
- RLC_IH_SRC_ID_START
- RLC_INT_STAT__CP_RLC_INT_PENDING_MASK
- RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT
- RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK
- RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT
- RLC_INT_STAT__RESERVED_MASK
- RLC_INT_STAT__RESERVED__SHIFT
- RLC_JUMP_TABLE_RESTORE__ADDR_MASK
- RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT
- RLC_LBPW_CU_STAT__MAX_CU_MASK
- RLC_LBPW_CU_STAT__MAX_CU__SHIFT
- RLC_LBPW_CU_STAT__ON_CU_MASK
- RLC_LBPW_CU_STAT__ON_CU__SHIFT
- RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK
- RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT
- RLC_LB_ALWAYS_ACTIVE_WGP_MASK__ALWAYS_ACTIVE_WGP_MASK_MASK
- RLC_LB_ALWAYS_ACTIVE_WGP_MASK__ALWAYS_ACTIVE_WGP_MASK__SHIFT
- RLC_LB_CNTL
- RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK
- RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT
- RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK
- RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT
- RLC_LB_CNTL__LB_CNT_REG_INC_MASK
- RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT
- RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK
- RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT
- RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK
- RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT
- RLC_LB_CNTL__RESERVED_MASK
- RLC_LB_CNTL__RESERVED__SHIFT
- RLC_LB_CNTR_1__RLC_LOAD_BALANCE_CNTR_MASK
- RLC_LB_CNTR_1__RLC_LOAD_BALANCE_CNTR__SHIFT
- RLC_LB_CNTR_2__RLC_LOAD_BALANCE_CNTR_MASK
- RLC_LB_CNTR_2__RLC_LOAD_BALANCE_CNTR__SHIFT
- RLC_LB_CNTR_INIT
- RLC_LB_CNTR_INIT_1__LB_CNTR_INIT_MASK
- RLC_LB_CNTR_INIT_1__LB_CNTR_INIT__SHIFT
- RLC_LB_CNTR_INIT_2__LB_CNTR_INIT_MASK
- RLC_LB_CNTR_INIT_2__LB_CNTR_INIT__SHIFT
- RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK
- RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT
- RLC_LB_CNTR_MAX
- RLC_LB_CNTR_MAX_1__LB_CNTR_MAX_MASK
- RLC_LB_CNTR_MAX_1__LB_CNTR_MAX__SHIFT
- RLC_LB_CNTR_MAX_2__LB_CNTR_MAX_MASK
- RLC_LB_CNTR_MAX_2__LB_CNTR_MAX__SHIFT
- RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK
- RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT
- RLC_LB_CONFIG_1__DATA_MASK
- RLC_LB_CONFIG_1__DATA__SHIFT
- RLC_LB_CONFIG_2__DATA_MASK
- RLC_LB_CONFIG_2__DATA__SHIFT
- RLC_LB_CONFIG_3__DATA_MASK
- RLC_LB_CONFIG_3__DATA__SHIFT
- RLC_LB_CONFIG_4__DATA_MASK
- RLC_LB_CONFIG_4__DATA__SHIFT
- RLC_LB_CONFIG_5__DATA_MASK
- RLC_LB_CONFIG_5__DATA__SHIFT
- RLC_LB_DELAY__LBPW_INNER_LOOP_DELAY_MASK
- RLC_LB_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT
- RLC_LB_DELAY__LBPW_OUTER_LOOP_DELAY_MASK
- RLC_LB_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT
- RLC_LB_DELAY__SPARE_MASK
- RLC_LB_DELAY__SPARE__SHIFT
- RLC_LB_DELAY__WGP_IDLE_DELAY_MASK
- RLC_LB_DELAY__WGP_IDLE_DELAY__SHIFT
- RLC_LB_INIT_CU_MASK
- RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK
- RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT
- RLC_LB_INIT_WGP_MASK__INIT_WGP_MASK_MASK
- RLC_LB_INIT_WGP_MASK__INIT_WGP_MASK__SHIFT
- RLC_LB_PARAMS
- RLC_LB_PARAMS__FIFO_SAMPLES_MASK
- RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT
- RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK
- RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT
- RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK
- RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT
- RLC_LB_PARAMS__SKIP_L2_CHECK_MASK
- RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT
- RLC_LB_THR_CONFIG_1__DATA_MASK
- RLC_LB_THR_CONFIG_1__DATA__SHIFT
- RLC_LB_THR_CONFIG_2__DATA_MASK
- RLC_LB_THR_CONFIG_2__DATA__SHIFT
- RLC_LB_THR_CONFIG_3__DATA_MASK
- RLC_LB_THR_CONFIG_3__DATA__SHIFT
- RLC_LB_THR_CONFIG_4__DATA_MASK
- RLC_LB_THR_CONFIG_4__DATA__SHIFT
- RLC_LB_WGP_STAT__MAX_WGP_MASK
- RLC_LB_WGP_STAT__MAX_WGP__SHIFT
- RLC_LB_WGP_STAT__ON_WGP_MASK
- RLC_LB_WGP_STAT__ON_WGP__SHIFT
- RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK
- RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT
- RLC_MASK
- RLC_MAX_PG_CU
- RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK
- RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT
- RLC_MAX_PG_CU__SPARE_MASK
- RLC_MAX_PG_CU__SPARE__SHIFT
- RLC_MAX_PG_WGP__MAX_POWERED_UP_WGP_MASK
- RLC_MAX_PG_WGP__MAX_POWERED_UP_WGP__SHIFT
- RLC_MAX_PG_WGP__SPARE_MASK
- RLC_MAX_PG_WGP__SPARE__SHIFT
- RLC_MC_CNTL
- RLC_MC_CNTL__RDNFO_STALL_MASK
- RLC_MC_CNTL__RDNFO_STALL__SHIFT
- RLC_MC_CNTL__RDNFO_URG_MASK
- RLC_MC_CNTL__RDNFO_URG__SHIFT
- RLC_MC_CNTL__RDREQ_PRIV_MASK
- RLC_MC_CNTL__RDREQ_PRIV__SHIFT
- RLC_MC_CNTL__RDREQ_SWAP_MASK
- RLC_MC_CNTL__RDREQ_SWAP__SHIFT
- RLC_MC_CNTL__RDREQ_TRAN_MASK
- RLC_MC_CNTL__RDREQ_TRAN__SHIFT
- RLC_MC_CNTL__RESERVED_B_MASK
- RLC_MC_CNTL__RESERVED_B__SHIFT
- RLC_MC_CNTL__RESERVED_MASK
- RLC_MC_CNTL__RESERVED__SHIFT
- RLC_MC_CNTL__WRNFO_STALL_MASK
- RLC_MC_CNTL__WRNFO_STALL__SHIFT
- RLC_MC_CNTL__WRNFO_URG_MASK
- RLC_MC_CNTL__WRNFO_URG__SHIFT
- RLC_MC_CNTL__WRREQ_DW_IMASK_MASK
- RLC_MC_CNTL__WRREQ_DW_IMASK__SHIFT
- RLC_MC_CNTL__WRREQ_PRIV_MASK
- RLC_MC_CNTL__WRREQ_PRIV__SHIFT
- RLC_MC_CNTL__WRREQ_SWAP_MASK
- RLC_MC_CNTL__WRREQ_SWAP__SHIFT
- RLC_MC_CNTL__WRREQ_TRAN_MASK
- RLC_MC_CNTL__WRREQ_TRAN__SHIFT
- RLC_MEM_LS_EN
- RLC_MEM_SLP_CNTL
- RLC_MEM_SLP_CNTL__RESERVED1_MASK
- RLC_MEM_SLP_CNTL__RESERVED1__SHIFT
- RLC_MEM_SLP_CNTL__RESERVED_MASK
- RLC_MEM_SLP_CNTL__RESERVED__SHIFT
- RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK
- RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT
- RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK
- RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT
- RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK
- RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT
- RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK
- RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT
- RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK
- RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT
- RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK
- RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT
- RLC_MGCG_CTRL__MGCG_EN_MASK
- RLC_MGCG_CTRL__MGCG_EN__SHIFT
- RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK
- RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT
- RLC_MGCG_CTRL__ON_DELAY_MASK
- RLC_MGCG_CTRL__ON_DELAY__SHIFT
- RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK
- RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT
- RLC_MGCG_CTRL__SILICON_EN_MASK
- RLC_MGCG_CTRL__SILICON_EN__SHIFT
- RLC_MGCG_CTRL__SIMULATION_EN_MASK
- RLC_MGCG_CTRL__SIMULATION_EN__SHIFT
- RLC_MGCG_CTRL__SPARE_MASK
- RLC_MGCG_CTRL__SPARE__SHIFT
- RLC_MSD
- RLC_MSD_MASK
- RLC_PACE_INT_DISABLE__DISABLE_MASK
- RLC_PACE_INT_DISABLE__DISABLE__SHIFT
- RLC_PACE_INT_FORCE__FORCE_MASK
- RLC_PACE_INT_FORCE__FORCE__SHIFT
- RLC_PACE_INT_STAT__STATUS_MASK
- RLC_PACE_INT_STAT__STATUS__SHIFT
- RLC_PACE_SCRATCH_ADDR__ADDR_MASK
- RLC_PACE_SCRATCH_ADDR__ADDR__SHIFT
- RLC_PACE_SCRATCH_DATA__DATA_MASK
- RLC_PACE_SCRATCH_DATA__DATA__SHIFT
- RLC_PACE_SPARE_INT_1__INTERRUPT_MASK
- RLC_PACE_SPARE_INT_1__INTERRUPT__SHIFT
- RLC_PACE_SPARE_INT_1__RESERVED_MASK
- RLC_PACE_SPARE_INT_1__RESERVED__SHIFT
- RLC_PACE_SPARE_INT__INTERRUPT_MASK
- RLC_PACE_SPARE_INT__INTERRUPT__SHIFT
- RLC_PACE_SPARE_INT__RESERVED_MASK
- RLC_PACE_SPARE_INT__RESERVED__SHIFT
- RLC_PACE_TABLE_NUM_LEVELS
- RLC_PACE_TIMER_CTRL__RESERVED_MASK
- RLC_PACE_TIMER_CTRL__RESERVED__SHIFT
- RLC_PACE_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK
- RLC_PACE_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT
- RLC_PACE_TIMER_CTRL__TIMER_0_EN_MASK
- RLC_PACE_TIMER_CTRL__TIMER_0_EN__SHIFT
- RLC_PACE_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK
- RLC_PACE_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT
- RLC_PACE_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK
- RLC_PACE_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT
- RLC_PACE_TIMER_CTRL__TIMER_1_EN_MASK
- RLC_PACE_TIMER_CTRL__TIMER_1_EN__SHIFT
- RLC_PACE_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK
- RLC_PACE_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT
- RLC_PACE_TIMER_INT_0__TIMER_MASK
- RLC_PACE_TIMER_INT_0__TIMER__SHIFT
- RLC_PACE_TIMER_INT_1__TIMER_MASK
- RLC_PACE_TIMER_INT_1__TIMER__SHIFT
- RLC_PACE_TIMER_STAT__RESERVED_MASK
- RLC_PACE_TIMER_STAT__RESERVED__SHIFT
- RLC_PACE_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK
- RLC_PACE_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT
- RLC_PACE_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK
- RLC_PACE_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT
- RLC_PACE_TIMER_STAT__TIMER_0_STAT_MASK
- RLC_PACE_TIMER_STAT__TIMER_0_STAT__SHIFT
- RLC_PACE_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK
- RLC_PACE_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT
- RLC_PACE_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK
- RLC_PACE_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT
- RLC_PACE_TIMER_STAT__TIMER_1_STAT_MASK
- RLC_PACE_TIMER_STAT__TIMER_1_STAT__SHIFT
- RLC_PACE_UCODE_ADDR__RESERVED_MASK
- RLC_PACE_UCODE_ADDR__RESERVED__SHIFT
- RLC_PACE_UCODE_ADDR__UCODE_ADDR_MASK
- RLC_PACE_UCODE_ADDR__UCODE_ADDR__SHIFT
- RLC_PACE_UCODE_DATA__UCODE_DATA_MASK
- RLC_PACE_UCODE_DATA__UCODE_DATA__SHIFT
- RLC_PCC_STRETCH_HYSTERESIS_CNTL__HYSTERESIS_CNT_MASK
- RLC_PCC_STRETCH_HYSTERESIS_CNTL__HYSTERESIS_CNT__SHIFT
- RLC_PCC_STRETCH_HYSTERESIS_CNTL__MAX_HYSTERESIS_MASK
- RLC_PCC_STRETCH_HYSTERESIS_CNTL__MAX_HYSTERESIS__SHIFT
- RLC_PDD
- RLC_PDD_MASK
- RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK
- RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT
- RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK
- RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT
- RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK
- RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT
- RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK
- RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT
- RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK
- RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT
- RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK
- RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT
- RLC_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE_MASK
- RLC_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE__SHIFT
- RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK
- RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT
- RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK
- RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT
- RLC_PERFMON_CNTL__PERFMON_STATE_MASK
- RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT
- RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK
- RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT
- RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK
- RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK__SHIFT
- RLC_PG_AO_CU_MASK
- RLC_PG_CNTL
- RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK
- RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT
- RLC_PG_CNTL__CP_PG_DISABLE_MASK
- RLC_PG_CNTL__CP_PG_DISABLE__SHIFT
- RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK
- RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT
- RLC_PG_CNTL__DYN_PER_WGP_PG_ENABLE_MASK
- RLC_PG_CNTL__DYN_PER_WGP_PG_ENABLE__SHIFT
- RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK
- RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT
- RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK
- RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT
- RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK
- RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT
- RLC_PG_CNTL__PG_ERROR_STATUS_MASK
- RLC_PG_CNTL__PG_ERROR_STATUS__SHIFT
- RLC_PG_CNTL__PG_OVERRIDE_MASK
- RLC_PG_CNTL__PG_OVERRIDE__SHIFT
- RLC_PG_CNTL__QUICK_PG_ENABLE_MASK
- RLC_PG_CNTL__QUICK_PG_ENABLE__SHIFT
- RLC_PG_CNTL__RESERVED1_MASK
- RLC_PG_CNTL__RESERVED1__SHIFT
- RLC_PG_CNTL__RESERVED2_MASK
- RLC_PG_CNTL__RESERVED2__SHIFT
- RLC_PG_CNTL__RESERVED_MASK
- RLC_PG_CNTL__RESERVED__SHIFT
- RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK
- RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT
- RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK
- RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT
- RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK
- RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT
- RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK
- RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT
- RLC_PG_CNTL__STATIC_PER_WGP_PG_ENABLE_MASK
- RLC_PG_CNTL__STATIC_PER_WGP_PG_ENABLE__SHIFT
- RLC_PG_CNTL__Ultra_Low_Voltage_Enable_MASK
- RLC_PG_CNTL__Ultra_Low_Voltage_Enable__SHIFT
- RLC_PG_DELAY
- RLC_PG_DELAY_2
- RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK
- RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT
- RLC_PG_DELAY_2__PERWGP_TIMEOUT_VALUE_MASK
- RLC_PG_DELAY_2__PERWGP_TIMEOUT_VALUE__SHIFT
- RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK
- RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT
- RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK
- RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT
- RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK
- RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT
- RLC_PG_DELAY_3__RESERVED_MASK
- RLC_PG_DELAY_3__RESERVED__SHIFT
- RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK
- RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT
- RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK
- RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT
- RLC_PG_DELAY__POWER_DOWN_DELAY_MASK
- RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT
- RLC_PG_DELAY__POWER_UP_DELAY_MASK
- RLC_PG_DELAY__POWER_UP_DELAY__SHIFT
- RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB_MASK
- RLC_PREWALKER_UTCL1_ADDR_LSB__ADDR_LSB__SHIFT
- RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB_MASK
- RLC_PREWALKER_UTCL1_ADDR_MSB__ADDR_MSB__SHIFT
- RLC_PREWALKER_UTCL1_CNTL__BYPASS_MASK
- RLC_PREWALKER_UTCL1_CNTL__BYPASS__SHIFT
- RLC_PREWALKER_UTCL1_CNTL__DROP_MODE_MASK
- RLC_PREWALKER_UTCL1_CNTL__DROP_MODE__SHIFT
- RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK
- RLC_PREWALKER_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT
- RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP_MASK
- RLC_PREWALKER_UTCL1_CNTL__FORCE_SNOOP__SHIFT
- RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK
- RLC_PREWALKER_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT
- RLC_PREWALKER_UTCL1_CNTL__INVALIDATE_MASK
- RLC_PREWALKER_UTCL1_CNTL__INVALIDATE__SHIFT
- RLC_PREWALKER_UTCL1_CNTL__RESERVED_MASK
- RLC_PREWALKER_UTCL1_CNTL__RESERVED__SHIFT
- RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK
- RLC_PREWALKER_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT
- RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB_MASK
- RLC_PREWALKER_UTCL1_SIZE_LSB__SIZE_LSB__SHIFT
- RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB_MASK
- RLC_PREWALKER_UTCL1_SIZE_MSB__SIZE_MSB__SHIFT
- RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM_MASK
- RLC_PREWALKER_UTCL1_TRIG__EXEC_PERM__SHIFT
- RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE_MASK
- RLC_PREWALKER_UTCL1_TRIG__PRIME_MODE__SHIFT
- RLC_PREWALKER_UTCL1_TRIG__READY_MASK
- RLC_PREWALKER_UTCL1_TRIG__READY__SHIFT
- RLC_PREWALKER_UTCL1_TRIG__READ_PERM_MASK
- RLC_PREWALKER_UTCL1_TRIG__READ_PERM__SHIFT
- RLC_PREWALKER_UTCL1_TRIG__RESERVED_MASK
- RLC_PREWALKER_UTCL1_TRIG__RESERVED__SHIFT
- RLC_PREWALKER_UTCL1_TRIG__VALID_MASK
- RLC_PREWALKER_UTCL1_TRIG__VALID__SHIFT
- RLC_PREWALKER_UTCL1_TRIG__VMID_MASK
- RLC_PREWALKER_UTCL1_TRIG__VMID__SHIFT
- RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM_MASK
- RLC_PREWALKER_UTCL1_TRIG__WRITE_PERM__SHIFT
- RLC_PUD
- RLC_PUD_MASK
- RLC_PWR_CTRL__DLDO_STATUS_MASK
- RLC_PWR_CTRL__DLDO_STATUS__SHIFT
- RLC_PWR_CTRL__MON_CGPG_RTN_EN_MASK
- RLC_PWR_CTRL__MON_CGPG_RTN_EN__SHIFT
- RLC_PWR_CTRL__RESERVED_MASK
- RLC_PWR_CTRL__RESERVED__SHIFT
- RLC_R2I_CNTL_0__Data_MASK
- RLC_R2I_CNTL_0__Data__SHIFT
- RLC_R2I_CNTL_1__Data_MASK
- RLC_R2I_CNTL_1__Data__SHIFT
- RLC_R2I_CNTL_2__Data_MASK
- RLC_R2I_CNTL_2__Data__SHIFT
- RLC_R2I_CNTL_3__Data_MASK
- RLC_R2I_CNTL_3__Data__SHIFT
- RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK
- RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT
- RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK
- RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT
- RLC_RLCP_IRAM_ADDR__ADDR_MASK
- RLC_RLCP_IRAM_ADDR__ADDR__SHIFT
- RLC_RLCP_IRAM_DATA__DATA_MASK
- RLC_RLCP_IRAM_DATA__DATA__SHIFT
- RLC_RLCS_ABORTED_PD_SEQUENCE__APS_MASK
- RLC_RLCS_ABORTED_PD_SEQUENCE__APS__SHIFT
- RLC_RLCS_ABORTED_PD_SEQUENCE__RESERVED_MASK
- RLC_RLCS_ABORTED_PD_SEQUENCE__RESERVED__SHIFT
- RLC_RLCS_AUXILIARY_REG_1__ADDR_MASK
- RLC_RLCS_AUXILIARY_REG_1__ADDR__SHIFT
- RLC_RLCS_AUXILIARY_REG_1__RESERVED_MASK
- RLC_RLCS_AUXILIARY_REG_1__RESERVED__SHIFT
- RLC_RLCS_AUXILIARY_REG_2__ADDR_MASK
- RLC_RLCS_AUXILIARY_REG_2__ADDR__SHIFT
- RLC_RLCS_AUXILIARY_REG_2__RESERVED_MASK
- RLC_RLCS_AUXILIARY_REG_2__RESERVED__SHIFT
- RLC_RLCS_AUXILIARY_REG_3__ADDR_MASK
- RLC_RLCS_AUXILIARY_REG_3__ADDR__SHIFT
- RLC_RLCS_AUXILIARY_REG_3__RESERVED_MASK
- RLC_RLCS_AUXILIARY_REG_3__RESERVED__SHIFT
- RLC_RLCS_AUXILIARY_REG_4__ADDR_MASK
- RLC_RLCS_AUXILIARY_REG_4__ADDR__SHIFT
- RLC_RLCS_AUXILIARY_REG_4__RESERVED_MASK
- RLC_RLCS_AUXILIARY_REG_4__RESERVED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_0_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_0_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_10_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_10_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_11_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_11_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_12_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_12_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_13_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_13_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_14_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_14_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_15_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_15_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_16_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_16_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_17_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_17_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_18_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_18_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_19_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_19_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_1_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_1_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_20_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_20_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_21_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_21_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_22_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_22_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_23_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_23_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_24_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_24_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_25_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_25_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_26_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_26_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_27_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_27_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_28_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_28_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_29_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_29_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_2_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_2_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_30_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_30_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_31_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_31_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_3_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_3_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_4_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_4_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_5_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_5_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_6_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_6_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_7_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_7_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_8_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_8_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_9_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_9_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_32_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_32_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_33_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_33_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_34_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_34_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_35_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_35_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_36_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_36_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_37_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_37_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_38_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_38_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_39_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_39_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_40_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_40_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_41_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_41_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_42_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_42_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_43_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_43_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_44_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_44_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_45_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_45_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_46_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_46_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_47_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_47_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_48_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_48_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_49_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_49_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_50_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_50_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_51_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_51_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_52_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_52_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_53_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_53_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_54_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_54_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_55_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_55_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_56_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_56_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_57_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_57_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_58_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_58_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_59_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_59_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_60_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_60_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_61_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_61_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_62_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_62_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_63_LOADED_MASK
- RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_63_LOADED__SHIFT
- RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE_MASK
- RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE__SHIFT
- RLC_RLCS_BOOTLOAD_STATUS__RESERVED_MASK
- RLC_RLCS_BOOTLOAD_STATUS__RESERVED__SHIFT
- RLC_RLCS_BOOTLOAD_STATUS__RLC_RLCG_IRAM_LOADED_MASK
- RLC_RLCS_BOOTLOAD_STATUS__RLC_RLCG_IRAM_LOADED__SHIFT
- RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_3D_MASK
- RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_3D__SHIFT
- RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_MASK
- RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST__SHIFT
- RLC_RLCS_CGCG_REQUEST__RESERVED_MASK
- RLC_RLCS_CGCG_REQUEST__RESERVED__SHIFT
- RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_3D_MASK
- RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_3D__SHIFT
- RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_MASK
- RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS__SHIFT
- RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_3D_MASK
- RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_3D__SHIFT
- RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_MASK
- RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS__SHIFT
- RLC_RLCS_CGCG_STATUS__RESERVED_MASK
- RLC_RLCS_CGCG_STATUS__RESERVED__SHIFT
- RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_HYST_MASK
- RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_HYST__SHIFT
- RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_MASK
- RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE__SHIFT
- RLC_RLCS_CMP_IDLE_CNTL__HYSTERESIS_CNT_MASK
- RLC_RLCS_CMP_IDLE_CNTL__HYSTERESIS_CNT__SHIFT
- RLC_RLCS_CMP_IDLE_CNTL__INT_CLEAR_MASK
- RLC_RLCS_CMP_IDLE_CNTL__INT_CLEAR__SHIFT
- RLC_RLCS_CMP_IDLE_CNTL__MAX_HYSTERESIS_MASK
- RLC_RLCS_CMP_IDLE_CNTL__MAX_HYSTERESIS__SHIFT
- RLC_RLCS_CMP_IDLE_CNTL__RESERVED_MASK
- RLC_RLCS_CMP_IDLE_CNTL__RESERVED__SHIFT
- RLC_RLCS_CP_DMA_SRCID_OVER__SRCID_OVERRIDE_MASK
- RLC_RLCS_CP_DMA_SRCID_OVER__SRCID_OVERRIDE__SHIFT
- RLC_RLCS_CP_INT_CTRL_1__INTERRUPT_ACK_MASK
- RLC_RLCS_CP_INT_CTRL_1__INTERRUPT_ACK__SHIFT
- RLC_RLCS_CP_INT_CTRL_1__RESERVED_MASK
- RLC_RLCS_CP_INT_CTRL_1__RESERVED__SHIFT
- RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_EN_MASK
- RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_EN__SHIFT
- RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_EN_MASK
- RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_EN__SHIFT
- RLC_RLCS_CP_INT_CTRL_2__RESERVED_MASK
- RLC_RLCS_CP_INT_CTRL_2__RESERVED__SHIFT
- RLC_RLCS_CP_INT_INFO_1__INTERRUPT_INFO_1_MASK
- RLC_RLCS_CP_INT_INFO_1__INTERRUPT_INFO_1__SHIFT
- RLC_RLCS_CP_INT_INFO_2__INTERRUPT_ID_MASK
- RLC_RLCS_CP_INT_INFO_2__INTERRUPT_ID__SHIFT
- RLC_RLCS_CP_INT_INFO_2__INTERRUPT_INFO_2_MASK
- RLC_RLCS_CP_INT_INFO_2__INTERRUPT_INFO_2__SHIFT
- RLC_RLCS_CP_INT_INFO_2__RESERVED_MASK
- RLC_RLCS_CP_INT_INFO_2__RESERVED__SHIFT
- RLC_RLCS_DIDT_FORCE_STALL__DFS_MASK
- RLC_RLCS_DIDT_FORCE_STALL__DFS__SHIFT
- RLC_RLCS_DIDT_FORCE_STALL__RESERVED_MASK
- RLC_RLCS_DIDT_FORCE_STALL__RESERVED__SHIFT
- RLC_RLCS_DSM_TRIG__RESERVED_MASK
- RLC_RLCS_DSM_TRIG__RESERVED__SHIFT
- RLC_RLCS_DSM_TRIG__START_MASK
- RLC_RLCS_DSM_TRIG__START__SHIFT
- RLC_RLCS_EDC_INT_CNTL__EDC_EVENT_INT_CLEAR_MASK
- RLC_RLCS_EDC_INT_CNTL__EDC_EVENT_INT_CLEAR__SHIFT
- RLC_RLCS_EXCEPTION_REG_1__ADDR_MASK
- RLC_RLCS_EXCEPTION_REG_1__ADDR__SHIFT
- RLC_RLCS_EXCEPTION_REG_1__RESERVED_MASK
- RLC_RLCS_EXCEPTION_REG_1__RESERVED__SHIFT
- RLC_RLCS_EXCEPTION_REG_2__ADDR_MASK
- RLC_RLCS_EXCEPTION_REG_2__ADDR__SHIFT
- RLC_RLCS_EXCEPTION_REG_2__RESERVED_MASK
- RLC_RLCS_EXCEPTION_REG_2__RESERVED__SHIFT
- RLC_RLCS_EXCEPTION_REG_3__ADDR_MASK
- RLC_RLCS_EXCEPTION_REG_3__ADDR__SHIFT
- RLC_RLCS_EXCEPTION_REG_3__RESERVED_MASK
- RLC_RLCS_EXCEPTION_REG_3__RESERVED__SHIFT
- RLC_RLCS_EXCEPTION_REG_4__ADDR_MASK
- RLC_RLCS_EXCEPTION_REG_4__ADDR__SHIFT
- RLC_RLCS_EXCEPTION_REG_4__RESERVED_MASK
- RLC_RLCS_EXCEPTION_REG_4__RESERVED__SHIFT
- RLC_RLCS_GENERAL_0__DATA_MASK
- RLC_RLCS_GENERAL_0__DATA__SHIFT
- RLC_RLCS_GENERAL_1__DATA_MASK
- RLC_RLCS_GENERAL_1__DATA__SHIFT
- RLC_RLCS_GENERAL_2__DATA_MASK
- RLC_RLCS_GENERAL_2__DATA__SHIFT
- RLC_RLCS_GENERAL_3__DATA_MASK
- RLC_RLCS_GENERAL_3__DATA__SHIFT
- RLC_RLCS_GENERAL_4__DATA_MASK
- RLC_RLCS_GENERAL_4__DATA__SHIFT
- RLC_RLCS_GENERAL_5__DATA_MASK
- RLC_RLCS_GENERAL_5__DATA__SHIFT
- RLC_RLCS_GENERAL_6__DATA_MASK
- RLC_RLCS_GENERAL_6__DATA__SHIFT
- RLC_RLCS_GENERAL_7__DATA_MASK
- RLC_RLCS_GENERAL_7__DATA__SHIFT
- RLC_RLCS_GE_FAST_CLOCK__FAST_CLKS_CHANGED_MASK
- RLC_RLCS_GE_FAST_CLOCK__FAST_CLKS_CHANGED__SHIFT
- RLC_RLCS_GE_FAST_CLOCK__FAST_CLKS_MASK
- RLC_RLCS_GE_FAST_CLOCK__FAST_CLKS__SHIFT
- RLC_RLCS_GE_FAST_CLOCK__INT_CLEAR_MASK
- RLC_RLCS_GE_FAST_CLOCK__INT_CLEAR__SHIFT
- RLC_RLCS_GE_FAST_CLOCK__RESERVED_MASK
- RLC_RLCS_GE_FAST_CLOCK__RESERVED__SHIFT
- RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_ALLOW_MASK
- RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_ALLOW__SHIFT
- RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK
- RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT
- RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_GFX_PWR_STALLED_MASK_MASK
- RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_GFX_PWR_STALLED_MASK__SHIFT
- RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_NON3D_PWR_STALLED_MASK_MASK
- RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_NON3D_PWR_STALLED_MASK__SHIFT
- RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK
- RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT
- RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_0_BUSY_MASK_MASK
- RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_0_BUSY_MASK__SHIFT
- RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_1_BUSY_MASK_MASK
- RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_1_BUSY_MASK__SHIFT
- RLC_RLCS_GFX_DS_CNTL__RESERVED_5_MASK
- RLC_RLCS_GFX_DS_CNTL__RESERVED_5__SHIFT
- RLC_RLCS_GFX_DS_CNTL__RESERVED_MASK
- RLC_RLCS_GFX_DS_CNTL__RESERVED__SHIFT
- RLC_RLCS_GPM_STAT_2__GFX_PWR_STALLED_STATUS_MASK
- RLC_RLCS_GPM_STAT_2__GFX_PWR_STALLED_STATUS__SHIFT
- RLC_RLCS_GPM_STAT_2__GFX_ULV_STATUS_MASK
- RLC_RLCS_GPM_STAT_2__GFX_ULV_STATUS__SHIFT
- RLC_RLCS_GPM_STAT_2__RESERVED_MASK
- RLC_RLCS_GPM_STAT_2__RESERVED__SHIFT
- RLC_RLCS_GPM_STAT_2__RLC_PWR_NON3D_STALLED_MASK
- RLC_RLCS_GPM_STAT_2__RLC_PWR_NON3D_STALLED__SHIFT
- RLC_RLCS_GPM_STAT_2__TC_TRANS_ERROR_MASK
- RLC_RLCS_GPM_STAT_2__TC_TRANS_ERROR__SHIFT
- RLC_RLCS_GPM_STAT__ABORTED_PD_SEQUENCE_MASK
- RLC_RLCS_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT
- RLC_RLCS_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK
- RLC_RLCS_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT
- RLC_RLCS_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK
- RLC_RLCS_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT
- RLC_RLCS_GPM_STAT__CMP_POWER_STATUS_MASK
- RLC_RLCS_GPM_STAT__CMP_POWER_STATUS__SHIFT
- RLC_RLCS_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK
- RLC_RLCS_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT
- RLC_RLCS_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK
- RLC_RLCS_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT
- RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_DOWN_MASK
- RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_DOWN__SHIFT
- RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_UP_MASK
- RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_UP__SHIFT
- RLC_RLCS_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK
- RLC_RLCS_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT
- RLC_RLCS_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK
- RLC_RLCS_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT
- RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_3D_MASK
- RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_3D__SHIFT
- RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_MASK
- RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS__SHIFT
- RLC_RLCS_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK
- RLC_RLCS_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT
- RLC_RLCS_GPM_STAT__GFX_LS_STATUS_3D_MASK
- RLC_RLCS_GPM_STAT__GFX_LS_STATUS_3D__SHIFT
- RLC_RLCS_GPM_STAT__GFX_LS_STATUS_MASK
- RLC_RLCS_GPM_STAT__GFX_LS_STATUS__SHIFT
- RLC_RLCS_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK
- RLC_RLCS_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT
- RLC_RLCS_GPM_STAT__GFX_POWER_STATUS_MASK
- RLC_RLCS_GPM_STAT__GFX_POWER_STATUS__SHIFT
- RLC_RLCS_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK
- RLC_RLCS_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT
- RLC_RLCS_GPM_STAT__PG_ERROR_STATUS_MASK
- RLC_RLCS_GPM_STAT__PG_ERROR_STATUS__SHIFT
- RLC_RLCS_GPM_STAT__RESTORING_REGISTERS_MASK
- RLC_RLCS_GPM_STAT__RESTORING_REGISTERS__SHIFT
- RLC_RLCS_GPM_STAT__RLC_BUSY_MASK
- RLC_RLCS_GPM_STAT__RLC_BUSY__SHIFT
- RLC_RLCS_GPM_STAT__RLC_EXEC_ROM_CODE_MASK
- RLC_RLCS_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT
- RLC_RLCS_GPM_STAT__SAVING_REGISTERS_MASK
- RLC_RLCS_GPM_STAT__SAVING_REGISTERS__SHIFT
- RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_DOWN_MASK
- RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_DOWN__SHIFT
- RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_UP_MASK
- RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_UP__SHIFT
- RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__RESERVED_2_MASK
- RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__RESERVED_2__SHIFT
- RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA0_BUSY_INT_CLEAR_MASK
- RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA0_BUSY_INT_CLEAR__SHIFT
- RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA1_BUSY_INT_CLEAR_MASK
- RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA1_BUSY_INT_CLEAR__SHIFT
- RLC_RLCS_GRBM_IDLE_BUSY_STAT__GRBM_RLC_gc_stat_idle_MASK
- RLC_RLCS_GRBM_IDLE_BUSY_STAT__GRBM_RLC_gc_stat_idle__SHIFT
- RLC_RLCS_GRBM_IDLE_BUSY_STAT__RESERVED_4_MASK
- RLC_RLCS_GRBM_IDLE_BUSY_STAT__RESERVED_4__SHIFT
- RLC_RLCS_GRBM_IDLE_BUSY_STAT__RESERVED_7_MASK
- RLC_RLCS_GRBM_IDLE_BUSY_STAT__RESERVED_7__SHIFT
- RLC_RLCS_GRBM_IDLE_BUSY_STAT__RESERVED_MASK
- RLC_RLCS_GRBM_IDLE_BUSY_STAT__RESERVED__SHIFT
- RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_CHANGED_MASK
- RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_CHANGED__SHIFT
- RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_MASK
- RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY__SHIFT
- RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_CHANGED_MASK
- RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_CHANGED__SHIFT
- RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_MASK
- RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY__SHIFT
- RLC_RLCS_GRBM_SOFT_RESET__RESERVED_MASK
- RLC_RLCS_GRBM_SOFT_RESET__RESERVED__SHIFT
- RLC_RLCS_GRBM_SOFT_RESET__RESET_MASK
- RLC_RLCS_GRBM_SOFT_RESET__RESET__SHIFT
- RLC_RLCS_IH_COOKIE_SEMAPHORE__CLIENT_ID_MASK
- RLC_RLCS_IH_COOKIE_SEMAPHORE__CLIENT_ID__SHIFT
- RLC_RLCS_IH_COOKIE_SEMAPHORE__RESERVED_MASK
- RLC_RLCS_IH_COOKIE_SEMAPHORE__RESERVED__SHIFT
- RLC_RLCS_IH_CTRL_1__IH_CONTEXT_ID_1_MASK
- RLC_RLCS_IH_CTRL_1__IH_CONTEXT_ID_1__SHIFT
- RLC_RLCS_IH_CTRL_2__IH_CONTEXT_ID_2_MASK
- RLC_RLCS_IH_CTRL_2__IH_CONTEXT_ID_2__SHIFT
- RLC_RLCS_IH_CTRL_2__IH_RING_ID_MASK
- RLC_RLCS_IH_CTRL_2__IH_RING_ID__SHIFT
- RLC_RLCS_IH_CTRL_2__IH_VM_ID_MASK
- RLC_RLCS_IH_CTRL_2__IH_VM_ID__SHIFT
- RLC_RLCS_IH_CTRL_2__RESERVED_MASK
- RLC_RLCS_IH_CTRL_2__RESERVED__SHIFT
- RLC_RLCS_IH_CTRL_3__IH_SOURCE_ID_MASK
- RLC_RLCS_IH_CTRL_3__IH_SOURCE_ID__SHIFT
- RLC_RLCS_IH_CTRL_3__IH_VF_ID_MASK
- RLC_RLCS_IH_CTRL_3__IH_VF_ID__SHIFT
- RLC_RLCS_IH_CTRL_3__IH_VF_MASK
- RLC_RLCS_IH_CTRL_3__IH_VF__SHIFT
- RLC_RLCS_IH_CTRL_3__RESERVED_MASK
- RLC_RLCS_IH_CTRL_3__RESERVED__SHIFT
- RLC_RLCS_IH_SEMAPHORE__CLIENT_ID_MASK
- RLC_RLCS_IH_SEMAPHORE__CLIENT_ID__SHIFT
- RLC_RLCS_IH_SEMAPHORE__RESERVED_MASK
- RLC_RLCS_IH_SEMAPHORE__RESERVED__SHIFT
- RLC_RLCS_IH_STATUS__IH_BUSY_MASK
- RLC_RLCS_IH_STATUS__IH_BUSY__SHIFT
- RLC_RLCS_IH_STATUS__IH_CREDIT_COUNT_MASK
- RLC_RLCS_IH_STATUS__IH_CREDIT_COUNT__SHIFT
- RLC_RLCS_IH_STATUS__RESERVED_MASK
- RLC_RLCS_IH_STATUS__RESERVED__SHIFT
- RLC_RLCS_IOV_CMD_STATUS__DATA_MASK
- RLC_RLCS_IOV_CMD_STATUS__DATA__SHIFT
- RLC_RLCS_IOV_CNTX_LOC_SIZE__DATA_MASK
- RLC_RLCS_IOV_CNTX_LOC_SIZE__DATA__SHIFT
- RLC_RLCS_IOV_CNTX_LOC_SIZE__RESERVED_MASK
- RLC_RLCS_IOV_CNTX_LOC_SIZE__RESERVED__SHIFT
- RLC_RLCS_IOV_SCH_BLOCK__DATA_MASK
- RLC_RLCS_IOV_SCH_BLOCK__DATA__SHIFT
- RLC_RLCS_IOV_VM_BUSY_STATUS__DATA_MASK
- RLC_RLCS_IOV_VM_BUSY_STATUS__DATA__SHIFT
- RLC_RLCS_LB_CONTROL__LB_CNTR_INC_CP_BUSY_MASK
- RLC_RLCS_LB_CONTROL__LB_CNTR_INC_CP_BUSY__SHIFT
- RLC_RLCS_LB_CONTROL__NEW_LBPW_REQ_MASK
- RLC_RLCS_LB_CONTROL__NEW_LBPW_REQ__SHIFT
- RLC_RLCS_LB_CONTROL__RESERVED_MASK
- RLC_RLCS_LB_CONTROL__RESERVED__SHIFT
- RLC_RLCS_LB_READ__LBPW_DISABLE_FLAG_MASK
- RLC_RLCS_LB_READ__LBPW_DISABLE_FLAG__SHIFT
- RLC_RLCS_LB_READ__LB_CNTR_1_MAX_FLAG_MASK
- RLC_RLCS_LB_READ__LB_CNTR_1_MAX_FLAG__SHIFT
- RLC_RLCS_LB_READ__LB_CNTR_2_MAX_FLAG_MASK
- RLC_RLCS_LB_READ__LB_CNTR_2_MAX_FLAG__SHIFT
- RLC_RLCS_LB_READ__LB_CNTR_START_MASK
- RLC_RLCS_LB_READ__LB_CNTR_START__SHIFT
- RLC_RLCS_LB_READ__LB_CNTR_STOP_MASK
- RLC_RLCS_LB_READ__LB_CNTR_STOP__SHIFT
- RLC_RLCS_LB_READ__RESERVED_MASK
- RLC_RLCS_LB_READ__RESERVED__SHIFT
- RLC_RLCS_LB_STATUS__LBPW_DISABLE_FLAG_MASK
- RLC_RLCS_LB_STATUS__LBPW_DISABLE_FLAG__SHIFT
- RLC_RLCS_LB_STATUS__LB_CNTR_1_MAX_FLAG_MASK
- RLC_RLCS_LB_STATUS__LB_CNTR_1_MAX_FLAG__SHIFT
- RLC_RLCS_LB_STATUS__LB_CNTR_2_MAX_FLAG_MASK
- RLC_RLCS_LB_STATUS__LB_CNTR_2_MAX_FLAG__SHIFT
- RLC_RLCS_LB_STATUS__LB_CNTR_START_MASK
- RLC_RLCS_LB_STATUS__LB_CNTR_START__SHIFT
- RLC_RLCS_LB_STATUS__LB_CNTR_STOP_MASK
- RLC_RLCS_LB_STATUS__LB_CNTR_STOP__SHIFT
- RLC_RLCS_LB_STATUS__RESERVED_MASK
- RLC_RLCS_LB_STATUS__RESERVED__SHIFT
- RLC_RLCS_MP1_RLC_DOORBELL_CTRL__DOORBELL_MASK
- RLC_RLCS_MP1_RLC_DOORBELL_CTRL__DOORBELL__SHIFT
- RLC_RLCS_MP1_RLC_DOORBELL_CTRL__INT_CLEAR_MASK
- RLC_RLCS_MP1_RLC_DOORBELL_CTRL__INT_CLEAR__SHIFT
- RLC_RLCS_MP1_RLC_DOORBELL_CTRL__RESERVED_MASK
- RLC_RLCS_MP1_RLC_DOORBELL_CTRL__RESERVED__SHIFT
- RLC_RLCS_PG_CHANGE_READ__DYN_PG_REQ_CHANGED_MASK
- RLC_RLCS_PG_CHANGE_READ__DYN_PG_REQ_CHANGED__SHIFT
- RLC_RLCS_PG_CHANGE_READ__DYN_PG_STATUS_CHANGED_MASK
- RLC_RLCS_PG_CHANGE_READ__DYN_PG_STATUS_CHANGED__SHIFT
- RLC_RLCS_PG_CHANGE_READ__PG_CNTL_CHANGED_MASK
- RLC_RLCS_PG_CHANGE_READ__PG_CNTL_CHANGED__SHIFT
- RLC_RLCS_PG_CHANGE_READ__PG_REG_CHANGED_MASK
- RLC_RLCS_PG_CHANGE_READ__PG_REG_CHANGED__SHIFT
- RLC_RLCS_PG_CHANGE_READ__RESERVED_MASK
- RLC_RLCS_PG_CHANGE_READ__RESERVED__SHIFT
- RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_REQ_CHANGED_MASK
- RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_REQ_CHANGED__SHIFT
- RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_STATUS_CHANGED_MASK
- RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_STATUS_CHANGED__SHIFT
- RLC_RLCS_PG_CHANGE_STATUS__PG_CNTL_CHANGED_MASK
- RLC_RLCS_PG_CHANGE_STATUS__PG_CNTL_CHANGED__SHIFT
- RLC_RLCS_PG_CHANGE_STATUS__PG_REG_CHANGED_MASK
- RLC_RLCS_PG_CHANGE_STATUS__PG_REG_CHANGED__SHIFT
- RLC_RLCS_PG_CHANGE_STATUS__RESERVED_MASK
- RLC_RLCS_PG_CHANGE_STATUS__RESERVED__SHIFT
- RLC_RLCS_POWER_BRAKE_CNTL_TH1__HYSTERESIS_CNT_MASK
- RLC_RLCS_POWER_BRAKE_CNTL_TH1__HYSTERESIS_CNT__SHIFT
- RLC_RLCS_POWER_BRAKE_CNTL_TH1__INT_CLEAR_MASK
- RLC_RLCS_POWER_BRAKE_CNTL_TH1__INT_CLEAR__SHIFT
- RLC_RLCS_POWER_BRAKE_CNTL_TH1__MAX_HYSTERESIS_MASK
- RLC_RLCS_POWER_BRAKE_CNTL_TH1__MAX_HYSTERESIS__SHIFT
- RLC_RLCS_POWER_BRAKE_CNTL_TH1__POWER_BRAKE_MASK
- RLC_RLCS_POWER_BRAKE_CNTL_TH1__POWER_BRAKE__SHIFT
- RLC_RLCS_POWER_BRAKE_CNTL_TH1__RESERVED_MASK
- RLC_RLCS_POWER_BRAKE_CNTL_TH1__RESERVED__SHIFT
- RLC_RLCS_POWER_BRAKE_CNTL__HYSTERESIS_CNT_MASK
- RLC_RLCS_POWER_BRAKE_CNTL__HYSTERESIS_CNT__SHIFT
- RLC_RLCS_POWER_BRAKE_CNTL__INT_CLEAR_MASK
- RLC_RLCS_POWER_BRAKE_CNTL__INT_CLEAR__SHIFT
- RLC_RLCS_POWER_BRAKE_CNTL__MAX_HYSTERESIS_MASK
- RLC_RLCS_POWER_BRAKE_CNTL__MAX_HYSTERESIS__SHIFT
- RLC_RLCS_POWER_BRAKE_CNTL__POWER_BRAKE_MASK
- RLC_RLCS_POWER_BRAKE_CNTL__POWER_BRAKE__SHIFT
- RLC_RLCS_POWER_BRAKE_CNTL__RESERVED_MASK
- RLC_RLCS_POWER_BRAKE_CNTL__RESERVED__SHIFT
- RLC_RLCS_SMU_GFXCLK_CONTROL__RESERVED_MASK
- RLC_RLCS_SMU_GFXCLK_CONTROL__RESERVED__SHIFT
- RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXCLK_CHGTOG_MASK
- RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXCLK_CHGTOG__SHIFT
- RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXCLK_DIVIDER_MASK
- RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXCLK_DIVIDER__SHIFT
- RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXMUX_SEL_MASK
- RLC_RLCS_SMU_GFXCLK_CONTROL__SMU_GFXMUX_SEL__SHIFT
- RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_DONETOG_MASK
- RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_DONETOG__SHIFT
- RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_PCC_CTRL_MASK
- RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_PCC_CTRL__SHIFT
- RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_STRETCH_PCC_MASK
- RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXCLK_STRETCH_PCC__SHIFT
- RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXMUX_CUR_VALUE_MASK
- RLC_RLCS_SMU_GFXCLK_STATUS__SMU_GFXMUX_CUR_VALUE__SHIFT
- RLC_RLCS_SOC_DS_CNTL__RESERVED_5_MASK
- RLC_RLCS_SOC_DS_CNTL__RESERVED_5__SHIFT
- RLC_RLCS_SOC_DS_CNTL__RESERVED_MASK
- RLC_RLCS_SOC_DS_CNTL__RESERVED__SHIFT
- RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_ALLOW_MASK
- RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_ALLOW__SHIFT
- RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK
- RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT
- RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_GFX_PWR_STALLED_MASK_MASK
- RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_GFX_PWR_STALLED_MASK__SHIFT
- RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_NON3D_PWR_STALLED_MASK_MASK
- RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_NON3D_PWR_STALLED_MASK__SHIFT
- RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK
- RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT
- RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_0_BUSY_MASK_MASK
- RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_0_BUSY_MASK__SHIFT
- RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_1_BUSY_MASK_MASK
- RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_1_BUSY_MASK__SHIFT
- RLC_RLCS_SPM_INT_CTRL__INTERRUPT_ACK_MASK
- RLC_RLCS_SPM_INT_CTRL__INTERRUPT_ACK__SHIFT
- RLC_RLCS_SPM_INT_CTRL__RESERVED_MASK
- RLC_RLCS_SPM_INT_CTRL__RESERVED__SHIFT
- RLC_RLCS_SPM_INT_INFO_1__INTERRUPT_INFO_1_MASK
- RLC_RLCS_SPM_INT_INFO_1__INTERRUPT_INFO_1__SHIFT
- RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_ID_MASK
- RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_ID__SHIFT
- RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_INFO_2_MASK
- RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_INFO_2__SHIFT
- RLC_RLCS_SPM_INT_INFO_2__RESERVED_MASK
- RLC_RLCS_SPM_INT_INFO_2__RESERVED__SHIFT
- RLC_RLCS_SPM_SQTT_MODE__MODE_MASK
- RLC_RLCS_SPM_SQTT_MODE__MODE__SHIFT
- RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_MASK
- RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_VALUE_MASK
- RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_VALUE__SHIFT
- RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE__SHIFT
- RLC_RLCS_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK
- RLC_RLCS_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT
- RLC_RLCS_UTCL2_CNTL__RESERVED_MASK
- RLC_RLCS_UTCL2_CNTL__RESERVED__SHIFT
- RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_MASK
- RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_VALUE_MASK
- RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_VALUE__SHIFT
- RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE__SHIFT
- RLC_RLCS_WGP_READ__CS_WORK_ACTIVE_MASK
- RLC_RLCS_WGP_READ__CS_WORK_ACTIVE__SHIFT
- RLC_RLCS_WGP_READ__DYMANIC_WGP_STATUS_CHANGED_MASK
- RLC_RLCS_WGP_READ__DYMANIC_WGP_STATUS_CHANGED__SHIFT
- RLC_RLCS_WGP_READ__RESERVED_MASK
- RLC_RLCS_WGP_READ__RESERVED__SHIFT
- RLC_RLCS_WGP_READ__STATIC_WGP_STATUS_CHANGED_MASK
- RLC_RLCS_WGP_READ__STATIC_WGP_STATUS_CHANGED__SHIFT
- RLC_RLCS_WGP_STATUS__CS_WORK_ACTIVE_MASK
- RLC_RLCS_WGP_STATUS__CS_WORK_ACTIVE__SHIFT
- RLC_RLCS_WGP_STATUS__DYMANIC_WGP_STATUS_CHANGED_MASK
- RLC_RLCS_WGP_STATUS__DYMANIC_WGP_STATUS_CHANGED__SHIFT
- RLC_RLCS_WGP_STATUS__RESERVED_MASK
- RLC_RLCS_WGP_STATUS__RESERVED__SHIFT
- RLC_RLCS_WGP_STATUS__STATIC_PERWGP_PD_INCOMPLETE_MASK
- RLC_RLCS_WGP_STATUS__STATIC_PERWGP_PD_INCOMPLETE__SHIFT
- RLC_RLCS_WGP_STATUS__STATIC_WGP_STATUS_CHANGED_MASK
- RLC_RLCS_WGP_STATUS__STATIC_WGP_STATUS_CHANGED__SHIFT
- RLC_RLCV_COMMAND__CMD_MASK
- RLC_RLCV_COMMAND__CMD__SHIFT
- RLC_RLCV_COMMAND__RESERVED_MASK
- RLC_RLCV_COMMAND__RESERVED__SHIFT
- RLC_RLCV_IRAM_ADDR__ADDR_MASK
- RLC_RLCV_IRAM_ADDR__ADDR__SHIFT
- RLC_RLCV_IRAM_DATA__DATA_MASK
- RLC_RLCV_IRAM_DATA__DATA__SHIFT
- RLC_RLCV_SAFE_MODE__CMD_MASK
- RLC_RLCV_SAFE_MODE__CMD__SHIFT
- RLC_RLCV_SAFE_MODE__MESSAGE_MASK
- RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT
- RLC_RLCV_SAFE_MODE__RESERVED1_MASK
- RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT
- RLC_RLCV_SAFE_MODE__RESERVED_MASK
- RLC_RLCV_SAFE_MODE__RESERVED__SHIFT
- RLC_RLCV_SAFE_MODE__RESPONSE_MASK
- RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT
- RLC_RLCV_SPARE_INT_1__INTERRUPT_MASK
- RLC_RLCV_SPARE_INT_1__INTERRUPT__SHIFT
- RLC_RLCV_SPARE_INT_1__RESERVED_MASK
- RLC_RLCV_SPARE_INT_1__RESERVED__SHIFT
- RLC_RLCV_SPARE_INT__INTERRUPT_MASK
- RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT
- RLC_RLCV_SPARE_INT__RESERVED_MASK
- RLC_RLCV_SPARE_INT__RESERVED__SHIFT
- RLC_RLCV_TIMER_CTRL__RESERVED_MASK
- RLC_RLCV_TIMER_CTRL__RESERVED__SHIFT
- RLC_RLCV_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK
- RLC_RLCV_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT
- RLC_RLCV_TIMER_CTRL__TIMER_0_EN_MASK
- RLC_RLCV_TIMER_CTRL__TIMER_0_EN__SHIFT
- RLC_RLCV_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK
- RLC_RLCV_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT
- RLC_RLCV_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK
- RLC_RLCV_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT
- RLC_RLCV_TIMER_CTRL__TIMER_1_EN_MASK
- RLC_RLCV_TIMER_CTRL__TIMER_1_EN__SHIFT
- RLC_RLCV_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK
- RLC_RLCV_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT
- RLC_RLCV_TIMER_INT_0__TIMER_MASK
- RLC_RLCV_TIMER_INT_0__TIMER__SHIFT
- RLC_RLCV_TIMER_INT_1__TIMER_MASK
- RLC_RLCV_TIMER_INT_1__TIMER__SHIFT
- RLC_RLCV_TIMER_STAT__RESERVED_MASK
- RLC_RLCV_TIMER_STAT__RESERVED__SHIFT
- RLC_RLCV_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK
- RLC_RLCV_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT
- RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK
- RLC_RLCV_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT
- RLC_RLCV_TIMER_STAT__TIMER_0_STAT_MASK
- RLC_RLCV_TIMER_STAT__TIMER_0_STAT__SHIFT
- RLC_RLCV_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK
- RLC_RLCV_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT
- RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK
- RLC_RLCV_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT
- RLC_RLCV_TIMER_STAT__TIMER_1_STAT_MASK
- RLC_RLCV_TIMER_STAT__TIMER_1_STAT__SHIFT
- RLC_RL_BASE
- RLC_RL_SIZE
- RLC_ROM_CNTL__CU_HARVEST_EN_MASK
- RLC_ROM_CNTL__CU_HARVEST_EN__SHIFT
- RLC_ROM_CNTL__EFUSE_DISTRIB_EN_MASK
- RLC_ROM_CNTL__EFUSE_DISTRIB_EN__SHIFT
- RLC_ROM_CNTL__HELLOWORLD_EN_MASK
- RLC_ROM_CNTL__HELLOWORLD_EN__SHIFT
- RLC_ROM_CNTL__RESERVED_MASK
- RLC_ROM_CNTL__RESERVED__SHIFT
- RLC_ROM_CNTL__SLP_MODE_EN_MASK
- RLC_ROM_CNTL__SLP_MODE_EN__SHIFT
- RLC_ROM_CNTL__USE_ROM_MASK
- RLC_ROM_CNTL__USE_ROM__SHIFT
- RLC_RQ_PENDING
- RLC_SAFE_MODE__CMD_MASK
- RLC_SAFE_MODE__CMD__SHIFT
- RLC_SAFE_MODE__MESSAGE_MASK
- RLC_SAFE_MODE__MESSAGE__SHIFT
- RLC_SAFE_MODE__REQ_MASK
- RLC_SAFE_MODE__REQ__SHIFT
- RLC_SAFE_MODE__RESERVED1_MASK
- RLC_SAFE_MODE__RESERVED1__SHIFT
- RLC_SAFE_MODE__RESERVED_MASK
- RLC_SAFE_MODE__RESERVED__SHIFT
- RLC_SAFE_MODE__RESPONSE_MASK
- RLC_SAFE_MODE__RESPONSE__SHIFT
- RLC_SAVE_AND_RESTORE_BASE
- RLC_SAVE_AND_RESTORE_BASE__BASE_MASK
- RLC_SAVE_AND_RESTORE_BASE__BASE__SHIFT
- RLC_SAVE_AND_RESTORE_STARTING_OFFSET
- RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET
- RLC_SAVE_RESTORE_LIST_END_MARKER
- RLC_SEMAPHORE_0__CLIENT_ID_MASK
- RLC_SEMAPHORE_0__CLIENT_ID__SHIFT
- RLC_SEMAPHORE_0__RESERVED_MASK
- RLC_SEMAPHORE_0__RESERVED__SHIFT
- RLC_SEMAPHORE_1__CLIENT_ID_MASK
- RLC_SEMAPHORE_1__CLIENT_ID__SHIFT
- RLC_SEMAPHORE_1__RESERVED_MASK
- RLC_SEMAPHORE_1__RESERVED__SHIFT
- RLC_SEMAPHORE_2__CLIENT_ID_MASK
- RLC_SEMAPHORE_2__CLIENT_ID__SHIFT
- RLC_SEMAPHORE_2__RESERVED_MASK
- RLC_SEMAPHORE_2__RESERVED__SHIFT
- RLC_SEMAPHORE_3__CLIENT_ID_MASK
- RLC_SEMAPHORE_3__CLIENT_ID__SHIFT
- RLC_SEMAPHORE_3__RESERVED_MASK
- RLC_SEMAPHORE_3__RESERVED__SHIFT
- RLC_SERDES_BUSY__GC_CENTER_HUB_0_MASK
- RLC_SERDES_BUSY__GC_CENTER_HUB_0__SHIFT
- RLC_SERDES_BUSY__GC_CENTER_HUB_1_MASK
- RLC_SERDES_BUSY__GC_CENTER_HUB_1__SHIFT
- RLC_SERDES_BUSY__GC_SE_0_MASK
- RLC_SERDES_BUSY__GC_SE_0__SHIFT
- RLC_SERDES_BUSY__GC_SE_1_MASK
- RLC_SERDES_BUSY__GC_SE_1__SHIFT
- RLC_SERDES_BUSY__GC_SE_2_MASK
- RLC_SERDES_BUSY__GC_SE_2__SHIFT
- RLC_SERDES_BUSY__GC_SE_3_MASK
- RLC_SERDES_BUSY__GC_SE_3__SHIFT
- RLC_SERDES_BUSY__RD_FIFO_NOT_EMPTY_MASK
- RLC_SERDES_BUSY__RD_FIFO_NOT_EMPTY__SHIFT
- RLC_SERDES_BUSY__RD_PENDING_MASK
- RLC_SERDES_BUSY__RD_PENDING__SHIFT
- RLC_SERDES_BUSY__RESERVED_29_20_MASK
- RLC_SERDES_BUSY__RESERVED_29_20__SHIFT
- RLC_SERDES_BUSY__RESERVED_MASK
- RLC_SERDES_BUSY__RESERVED__SHIFT
- RLC_SERDES_CTRL__BPM_ADDR_MASK
- RLC_SERDES_CTRL__BPM_ADDR__SHIFT
- RLC_SERDES_CTRL__BPM_BROADCAST_MASK
- RLC_SERDES_CTRL__BPM_BROADCAST__SHIFT
- RLC_SERDES_CTRL__BPM_LONG_CMD_MASK
- RLC_SERDES_CTRL__BPM_LONG_CMD__SHIFT
- RLC_SERDES_CTRL__BPM_REG_WRITE_MASK
- RLC_SERDES_CTRL__BPM_REG_WRITE__SHIFT
- RLC_SERDES_CTRL__REG_ADDR_MASK
- RLC_SERDES_CTRL__REG_ADDR__SHIFT
- RLC_SERDES_CU_MASTER_BUSY
- RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK
- RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT
- RLC_SERDES_DATA__DATA_MASK
- RLC_SERDES_DATA__DATA__SHIFT
- RLC_SERDES_MASK__GC_CENTER_HUB_0_MASK
- RLC_SERDES_MASK__GC_CENTER_HUB_0__SHIFT
- RLC_SERDES_MASK__GC_CENTER_HUB_1_MASK
- RLC_SERDES_MASK__GC_CENTER_HUB_1__SHIFT
- RLC_SERDES_MASK__GC_SE_0_MASK
- RLC_SERDES_MASK__GC_SE_0__SHIFT
- RLC_SERDES_MASK__GC_SE_1_MASK
- RLC_SERDES_MASK__GC_SE_1__SHIFT
- RLC_SERDES_MASK__GC_SE_2_MASK
- RLC_SERDES_MASK__GC_SE_2__SHIFT
- RLC_SERDES_MASK__GC_SE_3_MASK
- RLC_SERDES_MASK__GC_SE_3__SHIFT
- RLC_SERDES_MASK__RESERVED_1_MASK
- RLC_SERDES_MASK__RESERVED_1__SHIFT
- RLC_SERDES_MASK__RESERVED_MASK
- RLC_SERDES_MASK__RESERVED__SHIFT
- RLC_SERDES_MASTER_BUSY_0
- RLC_SERDES_MASTER_BUSY_1
- RLC_SERDES_NONCU_MASTER_BUSY
- RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY_MASK
- RLC_SERDES_NONCU_MASTER_BUSY_1__EA_1_MASTER_BUSY__SHIFT
- RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1_MASK
- RLC_SERDES_NONCU_MASTER_BUSY_1__GC_GFX_MASTER_BUSY_1__SHIFT
- RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1_MASK
- RLC_SERDES_NONCU_MASTER_BUSY_1__GC_MASTER_BUSY_1__SHIFT
- RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1_MASK
- RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_1__SHIFT
- RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED_MASK
- RLC_SERDES_NONCU_MASTER_BUSY_1__RESERVED__SHIFT
- RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1_MASK
- RLC_SERDES_NONCU_MASTER_BUSY_1__SE_MASTER_BUSY_1__SHIFT
- RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY_MASK
- RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE4_MASTER_BUSY__SHIFT
- RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY_MASK
- RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE5_MASTER_BUSY__SHIFT
- RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY_MASK
- RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE6_MASTER_BUSY__SHIFT
- RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY_MASK
- RLC_SERDES_NONCU_MASTER_BUSY_1__SPARE7_MASTER_BUSY__SHIFT
- RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1_MASK
- RLC_SERDES_NONCU_MASTER_BUSY_1__TC0_MASTER_BUSY_1__SHIFT
- RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY_MASK
- RLC_SERDES_NONCU_MASTER_BUSY__EA_0_MASTER_BUSY__SHIFT
- RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK
- RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT
- RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK
- RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT
- RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK
- RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT
- RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK
- RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT
- RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK
- RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT
- RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK
- RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT
- RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK
- RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT
- RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK
- RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT
- RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK
- RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT
- RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK
- RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT
- RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY_MASK
- RLC_SERDES_NONCU_MASTER_BUSY__TC2_MASTER_BUSY__SHIFT
- RLC_SERDES_RD_DATA_0__DATA_MASK
- RLC_SERDES_RD_DATA_0__DATA__SHIFT
- RLC_SERDES_RD_DATA_1__DATA_MASK
- RLC_SERDES_RD_DATA_1__DATA__SHIFT
- RLC_SERDES_RD_DATA_2__DATA_MASK
- RLC_SERDES_RD_DATA_2__DATA__SHIFT
- RLC_SERDES_RD_DATA_3__DATA_MASK
- RLC_SERDES_RD_DATA_3__DATA__SHIFT
- RLC_SERDES_RD_INDEX__DATA_REG_ID_MASK
- RLC_SERDES_RD_INDEX__DATA_REG_ID__SHIFT
- RLC_SERDES_RD_INDEX__SPARE_MASK
- RLC_SERDES_RD_INDEX__SPARE__SHIFT
- RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK
- RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT
- RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK
- RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT
- RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK
- RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT
- RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK
- RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT
- RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK
- RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT
- RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK
- RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT
- RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK
- RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT
- RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK
- RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT
- RLC_SERDES_RD_PENDING__RD_PENDING_MASK
- RLC_SERDES_RD_PENDING__RD_PENDING__SHIFT
- RLC_SERDES_WR_CTRL
- RLC_SERDES_WR_CTRL__BPM_ADDR_MASK
- RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT
- RLC_SERDES_WR_CTRL__BPM_DATA_MASK
- RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT
- RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK
- RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0__SHIFT
- RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1_MASK
- RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_1__SHIFT
- RLC_SERDES_WR_CTRL__CGLS_DISABLE_MASK
- RLC_SERDES_WR_CTRL__CGLS_DISABLE__SHIFT
- RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK
- RLC_SERDES_WR_CTRL__CGLS_ENABLE__SHIFT
- RLC_SERDES_WR_CTRL__CGLS_OFF_MASK
- RLC_SERDES_WR_CTRL__CGLS_OFF__SHIFT
- RLC_SERDES_WR_CTRL__CGLS_ON_MASK
- RLC_SERDES_WR_CTRL__CGLS_ON__SHIFT
- RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK
- RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0__SHIFT
- RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK
- RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1__SHIFT
- RLC_SERDES_WR_CTRL__P1_SELECT_MASK
- RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT
- RLC_SERDES_WR_CTRL__P2_SELECT_MASK
- RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT
- RLC_SERDES_WR_CTRL__POWER_DOWN_MASK
- RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT
- RLC_SERDES_WR_CTRL__POWER_UP_MASK
- RLC_SERDES_WR_CTRL__POWER_UP__SHIFT
- RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK
- RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT
- RLC_SERDES_WR_CTRL__READ_COMMAND_MASK
- RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT
- RLC_SERDES_WR_CTRL__REG_ADDR_MASK
- RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT
- RLC_SERDES_WR_CTRL__RESERVED_1_MASK
- RLC_SERDES_WR_CTRL__RESERVED_1__SHIFT
- RLC_SERDES_WR_CTRL__RESERVED_2_MASK
- RLC_SERDES_WR_CTRL__RESERVED_2__SHIFT
- RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK
- RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT
- RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK
- RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT
- RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK
- RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT
- RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK
- RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT
- RLC_SERDES_WR_CU_MASTER_MASK
- RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK
- RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT
- RLC_SERDES_WR_DATA__DATA_MASK
- RLC_SERDES_WR_DATA__DATA__SHIFT
- RLC_SERDES_WR_MASTER_MASK_0
- RLC_SERDES_WR_MASTER_MASK_1
- RLC_SERDES_WR_NONCU_MASTER_MASK
- RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK_MASK
- RLC_SERDES_WR_NONCU_MASTER_MASK_1__EA_1_MASTER_MASK__SHIFT
- RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1_MASK
- RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_GFX_MASTER_MASK_1__SHIFT
- RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1_MASK
- RLC_SERDES_WR_NONCU_MASTER_MASK_1__GC_MASTER_MASK_1__SHIFT
- RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1_MASK
- RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_1__SHIFT
- RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED_MASK
- RLC_SERDES_WR_NONCU_MASTER_MASK_1__RESERVED__SHIFT
- RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1_MASK
- RLC_SERDES_WR_NONCU_MASTER_MASK_1__SE_MASTER_MASK_1__SHIFT
- RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK_MASK
- RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE4_MASTER_MASK__SHIFT
- RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK_MASK
- RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE5_MASTER_MASK__SHIFT
- RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK_MASK
- RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE6_MASTER_MASK__SHIFT
- RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK_MASK
- RLC_SERDES_WR_NONCU_MASTER_MASK_1__SPARE7_MASTER_MASK__SHIFT
- RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK_MASK
- RLC_SERDES_WR_NONCU_MASTER_MASK_1__TC0_1_MASTER_MASK__SHIFT
- RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK_MASK
- RLC_SERDES_WR_NONCU_MASTER_MASK__EA_0_MASTER_MASK__SHIFT
- RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK
- RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT
- RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK
- RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT
- RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK
- RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT
- RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK
- RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT
- RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK
- RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT
- RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK
- RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT
- RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK
- RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT
- RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK
- RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT
- RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK
- RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT
- RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK
- RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT
- RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK_MASK
- RLC_SERDES_WR_NONCU_MASTER_MASK__TC2_MASTER_MASK__SHIFT
- RLC_SHIFT_BIT
- RLC_SMU_ARGUMENT_1__ARG_MASK
- RLC_SMU_ARGUMENT_1__ARG__SHIFT
- RLC_SMU_ARGUMENT_2__ARG_MASK
- RLC_SMU_ARGUMENT_2__ARG__SHIFT
- RLC_SMU_ARGUMENT_3__ARG_MASK
- RLC_SMU_ARGUMENT_3__ARG__SHIFT
- RLC_SMU_ARGUMENT_4__ARG_MASK
- RLC_SMU_ARGUMENT_4__ARG__SHIFT
- RLC_SMU_CLK_REQ__VALID_MASK
- RLC_SMU_CLK_REQ__VALID__SHIFT
- RLC_SMU_COMMAND__CMD_MASK
- RLC_SMU_COMMAND__CMD__SHIFT
- RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK
- RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT
- RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK
- RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT
- RLC_SMU_MESSAGE__CMD_MASK
- RLC_SMU_MESSAGE__CMD__SHIFT
- RLC_SMU_PG_CTRL__SPARE_MASK
- RLC_SMU_PG_CTRL__SPARE__SHIFT
- RLC_SMU_PG_CTRL__START_PG_MASK
- RLC_SMU_PG_CTRL__START_PG__SHIFT
- RLC_SMU_PG_WAKE_UP_CTRL__SPARE_MASK
- RLC_SMU_PG_WAKE_UP_CTRL__SPARE__SHIFT
- RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP_MASK
- RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP__SHIFT
- RLC_SMU_SAFE_MODE__CMD_MASK
- RLC_SMU_SAFE_MODE__CMD__SHIFT
- RLC_SMU_SAFE_MODE__MESSAGE_MASK
- RLC_SMU_SAFE_MODE__MESSAGE__SHIFT
- RLC_SMU_SAFE_MODE__RESERVED1_MASK
- RLC_SMU_SAFE_MODE__RESERVED1__SHIFT
- RLC_SMU_SAFE_MODE__RESERVED_MASK
- RLC_SMU_SAFE_MODE__RESERVED__SHIFT
- RLC_SMU_SAFE_MODE__RESPONSE_MASK
- RLC_SMU_SAFE_MODE__RESPONSE__SHIFT
- RLC_SOFT_RESET_GPU__RESERVED_MASK
- RLC_SOFT_RESET_GPU__RESERVED__SHIFT
- RLC_SOFT_RESET_GPU__SOFT_RESET_GPU_MASK
- RLC_SOFT_RESET_GPU__SOFT_RESET_GPU__SHIFT
- RLC_SPARE_INT_1__INTERRUPT_MASK
- RLC_SPARE_INT_1__INTERRUPT__SHIFT
- RLC_SPARE_INT_1__RESERVED_MASK
- RLC_SPARE_INT_1__RESERVED__SHIFT
- RLC_SPARE_INT__INTERRUPT_MASK
- RLC_SPARE_INT__INTERRUPT__SHIFT
- RLC_SPARE_INT__RESERVED_MASK
- RLC_SPARE_INT__RESERVED__SHIFT
- RLC_SPM_ACCUM_CTRLRAM_ADDR__RESERVED_MASK
- RLC_SPM_ACCUM_CTRLRAM_ADDR__RESERVED__SHIFT
- RLC_SPM_ACCUM_CTRLRAM_ADDR__addr_MASK
- RLC_SPM_ACCUM_CTRLRAM_ADDR__addr__SHIFT
- RLC_SPM_ACCUM_CTRLRAM_DATA__RESERVED_MASK
- RLC_SPM_ACCUM_CTRLRAM_DATA__RESERVED__SHIFT
- RLC_SPM_ACCUM_CTRLRAM_DATA__data_MASK
- RLC_SPM_ACCUM_CTRLRAM_DATA__data__SHIFT
- RLC_SPM_ACCUM_CTRL__RESERVED_MASK
- RLC_SPM_ACCUM_CTRL__RESERVED__SHIFT
- RLC_SPM_ACCUM_CTRL__StrobeAccumDoneInt_MASK
- RLC_SPM_ACCUM_CTRL__StrobeAccumDoneInt__SHIFT
- RLC_SPM_ACCUM_CTRL__StrobeRearmAccum_MASK
- RLC_SPM_ACCUM_CTRL__StrobeRearmAccum__SHIFT
- RLC_SPM_ACCUM_CTRL__StrobeResetAccum_MASK
- RLC_SPM_ACCUM_CTRL__StrobeResetAccum__SHIFT
- RLC_SPM_ACCUM_CTRL__StrobeResetPerfMonitors_MASK
- RLC_SPM_ACCUM_CTRL__StrobeResetPerfMonitors__SHIFT
- RLC_SPM_ACCUM_CTRL__StrobeSpmDoneInt_MASK
- RLC_SPM_ACCUM_CTRL__StrobeSpmDoneInt__SHIFT
- RLC_SPM_ACCUM_CTRL__StrobeStartAccumulation_MASK
- RLC_SPM_ACCUM_CTRL__StrobeStartAccumulation__SHIFT
- RLC_SPM_ACCUM_CTRL__StrobeStartSpm_MASK
- RLC_SPM_ACCUM_CTRL__StrobeStartSpm__SHIFT
- RLC_SPM_ACCUM_DATARAM_ADDR__RESERVED_MASK
- RLC_SPM_ACCUM_DATARAM_ADDR__RESERVED__SHIFT
- RLC_SPM_ACCUM_DATARAM_ADDR__addr_MASK
- RLC_SPM_ACCUM_DATARAM_ADDR__addr__SHIFT
- RLC_SPM_ACCUM_DATARAM_DATA__data_MASK
- RLC_SPM_ACCUM_DATARAM_DATA__data__SHIFT
- RLC_SPM_ACCUM_DATARAM_WRCOUNT__DataRamWrCount_MASK
- RLC_SPM_ACCUM_DATARAM_WRCOUNT__DataRamWrCount__SHIFT
- RLC_SPM_ACCUM_DATARAM_WRCOUNT__RESERVED_MASK
- RLC_SPM_ACCUM_DATARAM_WRCOUNT__RESERVED__SHIFT
- RLC_SPM_ACCUM_MODE__AutoAccumEn_MASK
- RLC_SPM_ACCUM_MODE__AutoAccumEn__SHIFT
- RLC_SPM_ACCUM_MODE__AutoResetPerfmonDisable_MASK
- RLC_SPM_ACCUM_MODE__AutoResetPerfmonDisable__SHIFT
- RLC_SPM_ACCUM_MODE__AutoSpmEn_MASK
- RLC_SPM_ACCUM_MODE__AutoSpmEn__SHIFT
- RLC_SPM_ACCUM_MODE__EnableAccum_MASK
- RLC_SPM_ACCUM_MODE__EnableAccum__SHIFT
- RLC_SPM_ACCUM_MODE__Globals_LoadOverride_MASK
- RLC_SPM_ACCUM_MODE__Globals_LoadOverride__SHIFT
- RLC_SPM_ACCUM_MODE__RESERVED_MASK
- RLC_SPM_ACCUM_MODE__RESERVED__SHIFT
- RLC_SPM_ACCUM_MODE__SE0_LoadOverride_MASK
- RLC_SPM_ACCUM_MODE__SE0_LoadOverride__SHIFT
- RLC_SPM_ACCUM_MODE__SE1_LoadOverride_MASK
- RLC_SPM_ACCUM_MODE__SE1_LoadOverride__SHIFT
- RLC_SPM_ACCUM_SAMPLES_REQUESTED__RESERVED_MASK
- RLC_SPM_ACCUM_SAMPLES_REQUESTED__RESERVED__SHIFT
- RLC_SPM_ACCUM_SAMPLES_REQUESTED__SamplesRequested_MASK
- RLC_SPM_ACCUM_SAMPLES_REQUESTED__SamplesRequested__SHIFT
- RLC_SPM_ACCUM_STATUS__AccumArmed_MASK
- RLC_SPM_ACCUM_STATUS__AccumArmed__SHIFT
- RLC_SPM_ACCUM_STATUS__AccumDone_MASK
- RLC_SPM_ACCUM_STATUS__AccumDone__SHIFT
- RLC_SPM_ACCUM_STATUS__AccumOverflow_MASK
- RLC_SPM_ACCUM_STATUS__AccumOverflow__SHIFT
- RLC_SPM_ACCUM_STATUS__AllFifosEmpty_MASK
- RLC_SPM_ACCUM_STATUS__AllFifosEmpty__SHIFT
- RLC_SPM_ACCUM_STATUS__FSMIsIdle_MASK
- RLC_SPM_ACCUM_STATUS__FSMIsIdle__SHIFT
- RLC_SPM_ACCUM_STATUS__FinalSequenceInProgress_MASK
- RLC_SPM_ACCUM_STATUS__FinalSequenceInProgress__SHIFT
- RLC_SPM_ACCUM_STATUS__NumbSamplesCompleted_MASK
- RLC_SPM_ACCUM_STATUS__NumbSamplesCompleted__SHIFT
- RLC_SPM_ACCUM_STATUS__RESERVED_MASK
- RLC_SPM_ACCUM_STATUS__RESERVED__SHIFT
- RLC_SPM_ACCUM_STATUS__SequenceInProgress_MASK
- RLC_SPM_ACCUM_STATUS__SequenceInProgress__SHIFT
- RLC_SPM_ACCUM_STATUS__SpmDone_MASK
- RLC_SPM_ACCUM_STATUS__SpmDone__SHIFT
- RLC_SPM_ACCUM_THRESHOLD__RESERVED_MASK
- RLC_SPM_ACCUM_THRESHOLD__RESERVED__SHIFT
- RLC_SPM_ACCUM_THRESHOLD__Threshold_MASK
- RLC_SPM_ACCUM_THRESHOLD__Threshold__SHIFT
- RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK
- RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT
- RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK
- RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT
- RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK
- RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT
- RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK
- RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT
- RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK
- RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT
- RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK
- RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT
- RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK
- RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT
- RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK
- RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT
- RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK
- RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT
- RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK
- RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT
- RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK
- RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT
- RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK
- RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT
- RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK
- RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT
- RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK
- RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT
- RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK
- RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT
- RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK
- RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT
- RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK
- RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT
- RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK
- RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT
- RLC_SPM_DEBUG_SELECT__RESERVED_MASK
- RLC_SPM_DEBUG_SELECT__RESERVED__SHIFT
- RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE_MASK
- RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE__SHIFT
- RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE_MASK
- RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE__SHIFT
- RLC_SPM_DEBUG_SELECT__SELECT_MASK
- RLC_SPM_DEBUG_SELECT__SELECT__SHIFT
- RLC_SPM_DEBUG__DATA_MASK
- RLC_SPM_DEBUG__DATA__SHIFT
- RLC_SPM_DESER_START_SKEW__DESER_START_SKEW_MASK
- RLC_SPM_DESER_START_SKEW__DESER_START_SKEW__SHIFT
- RLC_SPM_DESER_START_SKEW__RESERVED_MASK
- RLC_SPM_DESER_START_SKEW__RESERVED__SHIFT
- RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK
- RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT
- RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK
- RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT
- RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR__GLB_SAMPLEDELAY_INDEX_MASK
- RLC_SPM_GLB_SAMPLEDELAY_IND_ADDR__GLB_SAMPLEDELAY_INDEX__SHIFT
- RLC_SPM_GLB_SAMPLEDELAY_IND_DATA__RESERVED_MASK
- RLC_SPM_GLB_SAMPLEDELAY_IND_DATA__RESERVED__SHIFT
- RLC_SPM_GLB_SAMPLEDELAY_IND_DATA__data_MASK
- RLC_SPM_GLB_SAMPLEDELAY_IND_DATA__data__SHIFT
- RLC_SPM_GLOBALS_MUXSEL_SKEW__GLOBALS_MUXSEL_SKEW_MASK
- RLC_SPM_GLOBALS_MUXSEL_SKEW__GLOBALS_MUXSEL_SKEW__SHIFT
- RLC_SPM_GLOBALS_MUXSEL_SKEW__RESERVED_MASK
- RLC_SPM_GLOBALS_MUXSEL_SKEW__RESERVED__SHIFT
- RLC_SPM_GLOBALS_SAMPLE_SKEW__GLOBALS_SAMPLE_SKEW_MASK
- RLC_SPM_GLOBALS_SAMPLE_SKEW__GLOBALS_SAMPLE_SKEW__SHIFT
- RLC_SPM_GLOBALS_SAMPLE_SKEW__RESERVED_MASK
- RLC_SPM_GLOBALS_SAMPLE_SKEW__RESERVED__SHIFT
- RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK
- RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT
- RLC_SPM_GLOBAL_MUXSEL_ADDR__RESERVED_MASK
- RLC_SPM_GLOBAL_MUXSEL_ADDR__RESERVED__SHIFT
- RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK
- RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT
- RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK
- RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT
- RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK
- RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT
- RLC_SPM_INT_CNTL__RESERVED_MASK
- RLC_SPM_INT_CNTL__RESERVED__SHIFT
- RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK
- RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT
- RLC_SPM_INT_INFO_1__INTERRUPT_INFO_1_MASK
- RLC_SPM_INT_INFO_1__INTERRUPT_INFO_1__SHIFT
- RLC_SPM_INT_INFO_2__INTERRUPT_ID_MASK
- RLC_SPM_INT_INFO_2__INTERRUPT_ID__SHIFT
- RLC_SPM_INT_INFO_2__INTERRUPT_INFO_2_MASK
- RLC_SPM_INT_INFO_2__INTERRUPT_INFO_2__SHIFT
- RLC_SPM_INT_INFO_2__RESERVED_MASK
- RLC_SPM_INT_INFO_2__RESERVED__SHIFT
- RLC_SPM_INT_STATUS__RESERVED_MASK
- RLC_SPM_INT_STATUS__RESERVED__SHIFT
- RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK
- RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT
- RLC_SPM_MC_CNTL__RESERVED_2_MASK
- RLC_SPM_MC_CNTL__RESERVED_2__SHIFT
- RLC_SPM_MC_CNTL__RESERVED_MASK
- RLC_SPM_MC_CNTL__RESERVED__SHIFT
- RLC_SPM_MC_CNTL__RLC_SPM_BC_MASK
- RLC_SPM_MC_CNTL__RLC_SPM_BC__SHIFT
- RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK
- RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT
- RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK
- RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK
- RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT
- RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT
- RLC_SPM_MC_CNTL__RLC_SPM_NOFILL_MASK
- RLC_SPM_MC_CNTL__RLC_SPM_NOFILL__SHIFT
- RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK
- RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT
- RLC_SPM_MC_CNTL__RLC_SPM_POLICY_MASK
- RLC_SPM_MC_CNTL__RLC_SPM_POLICY__SHIFT
- RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK
- RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT
- RLC_SPM_MC_CNTL__RLC_SPM_VOL_MASK
- RLC_SPM_MC_CNTL__RLC_SPM_VOL__SHIFT
- RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK
- RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT
- RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK
- RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT
- RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK
- RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT
- RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK
- RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT
- RLC_SPM_PERFMON_CNTL__RESERVED1_MASK
- RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT
- RLC_SPM_PERFMON_CNTL__RESERVED_MASK
- RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT
- RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK
- RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT
- RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK
- RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT
- RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__RESERVED_MASK
- RLC_SPM_PERFMON_GLB_SEGMENT_SIZE__RESERVED__SHIFT
- RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK
- RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT
- RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK
- RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT
- RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK
- RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT
- RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK
- RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT
- RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__PERFMON_MAX_SAMPLE_DELAY_MASK
- RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__PERFMON_MAX_SAMPLE_DELAY__SHIFT
- RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__RESERVED_MASK
- RLC_SPM_PERFMON_SAMPLE_DELAY_MAX__RESERVED__SHIFT
- RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE0_NUM_LINE_MASK
- RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT
- RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE1_NUM_LINE_MASK
- RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT
- RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE2_NUM_LINE_MASK
- RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT
- RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE3_NUM_LINE_MASK
- RLC_SPM_PERFMON_SE3TO0_SEGMENT_SIZE__SE3_NUM_LINE__SHIFT
- RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK
- RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT
- RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK
- RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT
- RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK
- RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT
- RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK
- RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT
- RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK
- RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT
- RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK
- RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT
- RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK
- RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT
- RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK
- RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT
- RLC_SPM_RING_WRPTR__PERFMON_RING_WRPTR_MASK
- RLC_SPM_RING_WRPTR__PERFMON_RING_WRPTR__SHIFT
- RLC_SPM_RING_WRPTR__RESERVED_MASK
- RLC_SPM_RING_WRPTR__RESERVED__SHIFT
- RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK
- RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT
- RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED_MASK
- RLC_SPM_RMI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT
- RLC_SPM_SAMPLE_CNT__COUNT_MASK
- RLC_SPM_SAMPLE_CNT__COUNT__SHIFT
- RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK
- RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT
- RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK
- RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT
- RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK
- RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT
- RLC_SPM_SEGMENT_THRESHOLD__RESERVED_MASK
- RLC_SPM_SEGMENT_THRESHOLD__RESERVED__SHIFT
- RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK
- RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT
- RLC_SPM_SE_MUXSEL_ADDR__RESERVED_MASK
- RLC_SPM_SE_MUXSEL_ADDR__RESERVED__SHIFT
- RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK
- RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT
- RLC_SPM_SE_MUXSEL_SKEW__RESERVED_MASK
- RLC_SPM_SE_MUXSEL_SKEW__RESERVED__SHIFT
- RLC_SPM_SE_MUXSEL_SKEW__SE_MUXSEL_SKEW_MASK
- RLC_SPM_SE_MUXSEL_SKEW__SE_MUXSEL_SKEW__SHIFT
- RLC_SPM_SE_SAMPLEDELAY_IND_ADDR__SE_SAMPLEDELAY_INDEX_MASK
- RLC_SPM_SE_SAMPLEDELAY_IND_ADDR__SE_SAMPLEDELAY_INDEX__SHIFT
- RLC_SPM_SE_SAMPLEDELAY_IND_DATA__RESERVED_MASK
- RLC_SPM_SE_SAMPLEDELAY_IND_DATA__RESERVED__SHIFT
- RLC_SPM_SE_SAMPLEDELAY_IND_DATA__data_MASK
- RLC_SPM_SE_SAMPLEDELAY_IND_DATA__data__SHIFT
- RLC_SPM_SE_SAMPLE_SKEW__RESERVED_MASK
- RLC_SPM_SE_SAMPLE_SKEW__RESERVED__SHIFT
- RLC_SPM_SE_SAMPLE_SKEW__SE_SAMPLE_SKEW_MASK
- RLC_SPM_SE_SAMPLE_SKEW__SE_SAMPLE_SKEW__SHIFT
- RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK
- RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT
- RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK
- RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT
- RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK
- RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT
- RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK
- RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT
- RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK
- RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT
- RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK
- RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT
- RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK
- RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT
- RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK
- RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT
- RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK
- RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT
- RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK
- RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT
- RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK
- RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT
- RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK
- RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT
- RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK
- RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT
- RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK
- RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT
- RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK
- RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT
- RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__RESERVED_MASK
- RLC_SPM_TCS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT
- RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK
- RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT
- RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK
- RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT
- RLC_SPM_THREAD_TRACE_CTRL__THREAD_TRACE_INT_EN_MASK
- RLC_SPM_THREAD_TRACE_CTRL__THREAD_TRACE_INT_EN__SHIFT
- RLC_SPM_UTCL1_CNTL__BYPASS_MASK
- RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT
- RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK
- RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT
- RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY_MASK
- RLC_SPM_UTCL1_CNTL__FORCE_SD_VMID_DIRTY__SHIFT
- RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK
- RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT
- RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK
- RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT
- RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK
- RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT
- RLC_SPM_UTCL1_CNTL__RESERVED_MASK
- RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT
- RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK
- RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT
- RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK
- RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT
- RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK
- RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT
- RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK
- RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT
- RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK
- RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT
- RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK
- RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT
- RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK
- RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT
- RLC_SPM_VIRT_CTRL__PauseSpmSamplingRequest_MASK
- RLC_SPM_VIRT_CTRL__PauseSpmSamplingRequest__SHIFT
- RLC_SPM_VIRT_STATUS__SpmSamplingPaused_MASK
- RLC_SPM_VIRT_STATUS__SpmSamplingPaused__SHIFT
- RLC_SPM_VMID__RESERVED_MASK
- RLC_SPM_VMID__RESERVED__SHIFT
- RLC_SPM_VMID__RLC_SPM_VMID_MASK
- RLC_SPM_VMID__RLC_SPM_VMID__SHIFT
- RLC_SPP_CAM_ADDR__ADDR_MASK
- RLC_SPP_CAM_ADDR__ADDR__SHIFT
- RLC_SPP_CAM_DATA__DATA_MASK
- RLC_SPP_CAM_DATA__DATA__SHIFT
- RLC_SPP_CAM_DATA__TAG_MASK
- RLC_SPP_CAM_DATA__TAG__SHIFT
- RLC_SPP_CAM_EXT_ADDR__ADDR_MASK
- RLC_SPP_CAM_EXT_ADDR__ADDR__SHIFT
- RLC_SPP_CAM_EXT_DATA__LOCK_MASK
- RLC_SPP_CAM_EXT_DATA__LOCK__SHIFT
- RLC_SPP_CAM_EXT_DATA__VALID_MASK
- RLC_SPP_CAM_EXT_DATA__VALID__SHIFT
- RLC_SPP_CTRL__ENABLE_MASK
- RLC_SPP_CTRL__ENABLE_PPROF_MASK
- RLC_SPP_CTRL__ENABLE_PPROF__SHIFT
- RLC_SPP_CTRL__ENABLE_PWR_OPT_MASK
- RLC_SPP_CTRL__ENABLE_PWR_OPT__SHIFT
- RLC_SPP_CTRL__ENABLE__SHIFT
- RLC_SPP_CTRL__PAUSE_MASK
- RLC_SPP_CTRL__PAUSE__SHIFT
- RLC_SPP_GLOBAL_SH_ID_VALID__VALID_MASK
- RLC_SPP_GLOBAL_SH_ID_VALID__VALID__SHIFT
- RLC_SPP_GLOBAL_SH_ID__SH_ID_MASK
- RLC_SPP_GLOBAL_SH_ID__SH_ID__SHIFT
- RLC_SPP_INFLIGHT_RD_ADDR__ADDR_MASK
- RLC_SPP_INFLIGHT_RD_ADDR__ADDR__SHIFT
- RLC_SPP_INFLIGHT_RD_DATA__DATA_MASK
- RLC_SPP_INFLIGHT_RD_DATA__DATA__SHIFT
- RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_MASK
- RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_VALID_MASK
- RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_VALID__SHIFT
- RLC_SPP_PBB_INFO__PIPE0_OVERRIDE__SHIFT
- RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_MASK
- RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_VALID_MASK
- RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_VALID__SHIFT
- RLC_SPP_PBB_INFO__PIPE1_OVERRIDE__SHIFT
- RLC_SPP_PROF_INFO_1__SH_ID_MASK
- RLC_SPP_PROF_INFO_1__SH_ID__SHIFT
- RLC_SPP_PROF_INFO_2__CAM_CONFLICT_MASK
- RLC_SPP_PROF_INFO_2__CAM_CONFLICT__SHIFT
- RLC_SPP_PROF_INFO_2__CAM_HIT_MASK
- RLC_SPP_PROF_INFO_2__CAM_HIT__SHIFT
- RLC_SPP_PROF_INFO_2__CAM_LOCK_MASK
- RLC_SPP_PROF_INFO_2__CAM_LOCK__SHIFT
- RLC_SPP_PROF_INFO_2__SH_TYPE_MASK
- RLC_SPP_PROF_INFO_2__SH_TYPE__SHIFT
- RLC_SPP_PVT_LEVEL_MAX__LEVEL_MASK
- RLC_SPP_PVT_LEVEL_MAX__LEVEL__SHIFT
- RLC_SPP_PVT_STAT_0__LEVEL_0_COUNTER_MASK
- RLC_SPP_PVT_STAT_0__LEVEL_0_COUNTER__SHIFT
- RLC_SPP_PVT_STAT_0__LEVEL_1_COUNTER_MASK
- RLC_SPP_PVT_STAT_0__LEVEL_1_COUNTER__SHIFT
- RLC_SPP_PVT_STAT_0__LEVEL_2_COUNTER_MASK
- RLC_SPP_PVT_STAT_0__LEVEL_2_COUNTER__SHIFT
- RLC_SPP_PVT_STAT_0__LEVEL_3_COUNTER_MASK
- RLC_SPP_PVT_STAT_0__LEVEL_3_COUNTER__SHIFT
- RLC_SPP_PVT_STAT_0__LEVEL_4_COUNTER_MASK
- RLC_SPP_PVT_STAT_0__LEVEL_4_COUNTER__SHIFT
- RLC_SPP_PVT_STAT_1__LEVEL_5_COUNTER_MASK
- RLC_SPP_PVT_STAT_1__LEVEL_5_COUNTER__SHIFT
- RLC_SPP_PVT_STAT_1__LEVEL_6_COUNTER_MASK
- RLC_SPP_PVT_STAT_1__LEVEL_6_COUNTER__SHIFT
- RLC_SPP_PVT_STAT_1__LEVEL_7_COUNTER_MASK
- RLC_SPP_PVT_STAT_1__LEVEL_7_COUNTER__SHIFT
- RLC_SPP_PVT_STAT_1__LEVEL_8_COUNTER_MASK
- RLC_SPP_PVT_STAT_1__LEVEL_8_COUNTER__SHIFT
- RLC_SPP_PVT_STAT_1__LEVEL_9_COUNTER_MASK
- RLC_SPP_PVT_STAT_1__LEVEL_9_COUNTER__SHIFT
- RLC_SPP_PVT_STAT_2__LEVEL_10_COUNTER_MASK
- RLC_SPP_PVT_STAT_2__LEVEL_10_COUNTER__SHIFT
- RLC_SPP_PVT_STAT_2__LEVEL_11_COUNTER_MASK
- RLC_SPP_PVT_STAT_2__LEVEL_11_COUNTER__SHIFT
- RLC_SPP_PVT_STAT_2__LEVEL_12_COUNTER_MASK
- RLC_SPP_PVT_STAT_2__LEVEL_12_COUNTER__SHIFT
- RLC_SPP_PVT_STAT_2__LEVEL_13_COUNTER_MASK
- RLC_SPP_PVT_STAT_2__LEVEL_13_COUNTER__SHIFT
- RLC_SPP_PVT_STAT_2__LEVEL_14_COUNTER_MASK
- RLC_SPP_PVT_STAT_2__LEVEL_14_COUNTER__SHIFT
- RLC_SPP_PVT_STAT_3__LEVEL_15_COUNTER_MASK
- RLC_SPP_PVT_STAT_3__LEVEL_15_COUNTER__SHIFT
- RLC_SPP_RESET__CAM_RESET_MASK
- RLC_SPP_RESET__CAM_RESET__SHIFT
- RLC_SPP_RESET__EVENT_ARB_RESET_MASK
- RLC_SPP_RESET__EVENT_ARB_RESET__SHIFT
- RLC_SPP_RESET__PVT_RESET_MASK
- RLC_SPP_RESET__PVT_RESET__SHIFT
- RLC_SPP_RESET__SSF_RESET_MASK
- RLC_SPP_RESET__SSF_RESET__SHIFT
- RLC_SPP_SHADER_PROFILE_EN__CSG_ENABLE_MASK
- RLC_SPP_SHADER_PROFILE_EN__CSG_ENABLE__SHIFT
- RLC_SPP_SHADER_PROFILE_EN__CSG_STOP_CONDITION_MASK
- RLC_SPP_SHADER_PROFILE_EN__CSG_STOP_CONDITION__SHIFT
- RLC_SPP_SHADER_PROFILE_EN__CS_ENABLE_MASK
- RLC_SPP_SHADER_PROFILE_EN__CS_ENABLE__SHIFT
- RLC_SPP_SHADER_PROFILE_EN__CS_START_CONDITION_MASK
- RLC_SPP_SHADER_PROFILE_EN__CS_START_CONDITION__SHIFT
- RLC_SPP_SHADER_PROFILE_EN__CS_STOP_CONDITION_MASK
- RLC_SPP_SHADER_PROFILE_EN__CS_STOP_CONDITION__SHIFT
- RLC_SPP_SHADER_PROFILE_EN__ENABLE_PROF_INFO_LOCK_MASK
- RLC_SPP_SHADER_PROFILE_EN__ENABLE_PROF_INFO_LOCK__SHIFT
- RLC_SPP_SHADER_PROFILE_EN__FORCE_MISS_MASK
- RLC_SPP_SHADER_PROFILE_EN__FORCE_MISS__SHIFT
- RLC_SPP_SHADER_PROFILE_EN__FORCE_UNLOCKED_MASK
- RLC_SPP_SHADER_PROFILE_EN__FORCE_UNLOCKED__SHIFT
- RLC_SPP_SHADER_PROFILE_EN__GS_ENABLE_MASK
- RLC_SPP_SHADER_PROFILE_EN__GS_ENABLE__SHIFT
- RLC_SPP_SHADER_PROFILE_EN__GS_STOP_CONDITION_MASK
- RLC_SPP_SHADER_PROFILE_EN__GS_STOP_CONDITION__SHIFT
- RLC_SPP_SHADER_PROFILE_EN__HS_ENABLE_MASK
- RLC_SPP_SHADER_PROFILE_EN__HS_ENABLE__SHIFT
- RLC_SPP_SHADER_PROFILE_EN__HS_STOP_CONDITION_MASK
- RLC_SPP_SHADER_PROFILE_EN__HS_STOP_CONDITION__SHIFT
- RLC_SPP_SHADER_PROFILE_EN__PS_ENABLE_MASK
- RLC_SPP_SHADER_PROFILE_EN__PS_ENABLE__SHIFT
- RLC_SPP_SHADER_PROFILE_EN__PS_START_CONDITION_MASK
- RLC_SPP_SHADER_PROFILE_EN__PS_START_CONDITION__SHIFT
- RLC_SPP_SHADER_PROFILE_EN__PS_STOP_CONDITION_MASK
- RLC_SPP_SHADER_PROFILE_EN__PS_STOP_CONDITION__SHIFT
- RLC_SPP_SHADER_PROFILE_EN__VS_ENABLE_MASK
- RLC_SPP_SHADER_PROFILE_EN__VS_ENABLE__SHIFT
- RLC_SPP_SHADER_PROFILE_EN__VS_STOP_CONDITION_MASK
- RLC_SPP_SHADER_PROFILE_EN__VS_STOP_CONDITION__SHIFT
- RLC_SPP_SSF_CAPTURE_EN__CGS_ENABLE_MASK
- RLC_SPP_SSF_CAPTURE_EN__CGS_ENABLE__SHIFT
- RLC_SPP_SSF_CAPTURE_EN__CS_ENABLE_MASK
- RLC_SPP_SSF_CAPTURE_EN__CS_ENABLE__SHIFT
- RLC_SPP_SSF_CAPTURE_EN__GS_ENABLE_MASK
- RLC_SPP_SSF_CAPTURE_EN__GS_ENABLE__SHIFT
- RLC_SPP_SSF_CAPTURE_EN__HS_ENABLE_MASK
- RLC_SPP_SSF_CAPTURE_EN__HS_ENABLE__SHIFT
- RLC_SPP_SSF_CAPTURE_EN__PS_ENABLE_MASK
- RLC_SPP_SSF_CAPTURE_EN__PS_ENABLE__SHIFT
- RLC_SPP_SSF_CAPTURE_EN__VS_ENABLE_MASK
- RLC_SPP_SSF_CAPTURE_EN__VS_ENABLE__SHIFT
- RLC_SPP_SSF_THRESHOLD_0__PS_THRESHOLD_MASK
- RLC_SPP_SSF_THRESHOLD_0__PS_THRESHOLD__SHIFT
- RLC_SPP_SSF_THRESHOLD_0__VS_THRESHOLD_MASK
- RLC_SPP_SSF_THRESHOLD_0__VS_THRESHOLD__SHIFT
- RLC_SPP_SSF_THRESHOLD_1__GS_THRESHOLD_MASK
- RLC_SPP_SSF_THRESHOLD_1__GS_THRESHOLD__SHIFT
- RLC_SPP_SSF_THRESHOLD_1__HS_THRESHOLD_MASK
- RLC_SPP_SSF_THRESHOLD_1__HS_THRESHOLD__SHIFT
- RLC_SPP_SSF_THRESHOLD_2__CSG_THRESHOLD_MASK
- RLC_SPP_SSF_THRESHOLD_2__CSG_THRESHOLD__SHIFT
- RLC_SPP_SSF_THRESHOLD_2__CS_THRESHOLD_MASK
- RLC_SPP_SSF_THRESHOLD_2__CS_THRESHOLD__SHIFT
- RLC_SPP_STALL_STATE_UPDATE__ENABLE_MASK
- RLC_SPP_STALL_STATE_UPDATE__ENABLE__SHIFT
- RLC_SPP_STALL_STATE_UPDATE__STALL_MASK
- RLC_SPP_STALL_STATE_UPDATE__STALL__SHIFT
- RLC_SPP_STATUS__EVENT_ARB_BUSY_MASK
- RLC_SPP_STATUS__EVENT_ARB_BUSY__SHIFT
- RLC_SPP_STATUS__RESERVED_0_MASK
- RLC_SPP_STATUS__RESERVED_0__SHIFT
- RLC_SPP_STATUS__SPP_BUSY_MASK
- RLC_SPP_STATUS__SPP_BUSY__SHIFT
- RLC_SPP_STATUS__SSF_BUSY_MASK
- RLC_SPP_STATUS__SSF_BUSY__SHIFT
- RLC_SRM_ARAM_ADDR__ADDR_MASK
- RLC_SRM_ARAM_ADDR__ADDR__SHIFT
- RLC_SRM_ARAM_ADDR__RESERVED_MASK
- RLC_SRM_ARAM_ADDR__RESERVED__SHIFT
- RLC_SRM_ARAM_DATA__DATA_MASK
- RLC_SRM_ARAM_DATA__DATA__SHIFT
- RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK
- RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT
- RLC_SRM_CNTL__RESERVED_MASK
- RLC_SRM_CNTL__RESERVED__SHIFT
- RLC_SRM_CNTL__SRM_ENABLE_MASK
- RLC_SRM_CNTL__SRM_ENABLE__SHIFT
- RLC_SRM_DEBUG_SELECT__RESERVED_MASK
- RLC_SRM_DEBUG_SELECT__RESERVED__SHIFT
- RLC_SRM_DEBUG_SELECT__SELECT_MASK
- RLC_SRM_DEBUG_SELECT__SELECT__SHIFT
- RLC_SRM_DEBUG__DATA_MASK
- RLC_SRM_DEBUG__DATA__SHIFT
- RLC_SRM_DRAM_ADDR__ADDR_MASK
- RLC_SRM_DRAM_ADDR__ADDR__SHIFT
- RLC_SRM_DRAM_ADDR__RESERVED_MASK
- RLC_SRM_DRAM_ADDR__RESERVED__SHIFT
- RLC_SRM_DRAM_DATA__DATA_MASK
- RLC_SRM_DRAM_DATA__DATA__SHIFT
- RLC_SRM_GPM_ABORT__ABORT_MASK
- RLC_SRM_GPM_ABORT__ABORT__SHIFT
- RLC_SRM_GPM_ABORT__RESERVED_MASK
- RLC_SRM_GPM_ABORT__RESERVED__SHIFT
- RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK
- RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT
- RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK
- RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT
- RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK
- RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT
- RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK
- RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT
- RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK
- RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK
- RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT
- RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT
- RLC_SRM_GPM_COMMAND__OP_MASK
- RLC_SRM_GPM_COMMAND__OP__SHIFT
- RLC_SRM_GPM_COMMAND__RESERVED1_MASK
- RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT
- RLC_SRM_GPM_COMMAND__RESERVED_16_MASK
- RLC_SRM_GPM_COMMAND__RESERVED_16__SHIFT
- RLC_SRM_GPM_COMMAND__RESERVED_30_29_MASK
- RLC_SRM_GPM_COMMAND__RESERVED_30_29__SHIFT
- RLC_SRM_GPM_COMMAND__SIZE_MASK
- RLC_SRM_GPM_COMMAND__SIZE__SHIFT
- RLC_SRM_GPM_COMMAND__START_OFFSET_MASK
- RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT
- RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK
- RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT
- RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK
- RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT
- RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK
- RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT
- RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK
- RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT
- RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK
- RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT
- RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK
- RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT
- RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK
- RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT
- RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK
- RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT
- RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK
- RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT
- RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK
- RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT
- RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK
- RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT
- RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK
- RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT
- RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK
- RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT
- RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK
- RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT
- RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK
- RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT
- RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK
- RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT
- RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK
- RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT
- RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK
- RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT
- RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK
- RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT
- RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK
- RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT
- RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK
- RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT
- RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK
- RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT
- RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK
- RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT
- RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK
- RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT
- RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK
- RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT
- RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK
- RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT
- RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK
- RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT
- RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK
- RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT
- RLC_SRM_RLCV_COMMAND__OP_MASK
- RLC_SRM_RLCV_COMMAND__OP__SHIFT
- RLC_SRM_RLCV_COMMAND__RESERVED1_MASK
- RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT
- RLC_SRM_RLCV_COMMAND__RESERVED_MASK
- RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT
- RLC_SRM_RLCV_COMMAND__SIZE_MASK
- RLC_SRM_RLCV_COMMAND__SIZE__SHIFT
- RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK
- RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT
- RLC_SRM_STAT__RESERVED_MASK
- RLC_SRM_STAT__RESERVED__SHIFT
- RLC_SRM_STAT__SRM_BUSY_DELAY_MASK
- RLC_SRM_STAT__SRM_BUSY_DELAY__SHIFT
- RLC_SRM_STAT__SRM_BUSY_MASK
- RLC_SRM_STAT__SRM_BUSY__SHIFT
- RLC_SRM_STAT__SRM_STATUS_MASK
- RLC_SRM_STAT__SRM_STATUS__SHIFT
- RLC_STAT
- RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK
- RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT
- RLC_STATIC_PG_STATUS__PG_STATUS_WGP_MASK_MASK
- RLC_STATIC_PG_STATUS__PG_STATUS_WGP_MASK__SHIFT
- RLC_STAT__MC_BUSY_MASK
- RLC_STAT__MC_BUSY__SHIFT
- RLC_STAT__RESERVED_MASK
- RLC_STAT__RESERVED__SHIFT
- RLC_STAT__RLC_BUSY_MASK
- RLC_STAT__RLC_BUSY__SHIFT
- RLC_STAT__RLC_GPM_BUSY_MASK
- RLC_STAT__RLC_GPM_BUSY__SHIFT
- RLC_STAT__RLC_SPM_BUSY_MASK
- RLC_STAT__RLC_SPM_BUSY__SHIFT
- RLC_STAT__RLC_SRM_BUSY_MASK
- RLC_STAT__RLC_SRM_BUSY__SHIFT
- RLC_STAT__RLC_THREAD_0_BUSY_MASK
- RLC_STAT__RLC_THREAD_0_BUSY__SHIFT
- RLC_STAT__RLC_THREAD_1_BUSY_MASK
- RLC_STAT__RLC_THREAD_1_BUSY__SHIFT
- RLC_STAT__RLC_THREAD_2_BUSY_MASK
- RLC_STAT__RLC_THREAD_2_BUSY__SHIFT
- RLC_TABLE_OF_CONTENT
- RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK
- RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT
- RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK
- RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT
- RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK
- RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT
- RLC_THREAD1_DELAY__SPARE_MASK
- RLC_THREAD1_DELAY__SPARE__SHIFT
- RLC_TOC_MAX_SIZE
- RLC_TTOP_D
- RLC_TTPD
- RLC_TTPD_MASK
- RLC_UCODE_ADDR
- RLC_UCODE_CNTL
- RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK
- RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT
- RLC_UCODE_DATA
- RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK
- RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT
- RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK
- RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT
- RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK
- RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT
- RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK
- RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT
- RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK
- RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT
- RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK
- RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT
- RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY_MASK
- RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_BUSY__SHIFT
- RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans_MASK
- RLC_UTCL1_STATUS_2__PREWALKER_UTCL1_StallOnTrans__SHIFT
- RLC_UTCL1_STATUS_2__RESERVED_MASK
- RLC_UTCL1_STATUS_2__RESERVED__SHIFT
- RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK
- RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT
- RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK
- RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT
- RLC_UTCL1_STATUS__FAULT_DETECTED_MASK
- RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT
- RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK
- RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT
- RLC_UTCL1_STATUS__PRT_DETECTED_MASK
- RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT
- RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK
- RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT
- RLC_UTCL1_STATUS__RESERVED_1_MASK
- RLC_UTCL1_STATUS__RESERVED_1__SHIFT
- RLC_UTCL1_STATUS__RESERVED_2_MASK
- RLC_UTCL1_STATUS__RESERVED_2__SHIFT
- RLC_UTCL1_STATUS__RESERVED_3_MASK
- RLC_UTCL1_STATUS__RESERVED_3__SHIFT
- RLC_UTCL1_STATUS__RESERVED_MASK
- RLC_UTCL1_STATUS__RESERVED__SHIFT
- RLC_UTCL1_STATUS__RETRY_DETECTED_MASK
- RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT
- RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK
- RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT
- RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK
- RLC_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT
- RLC_UTCL2_CNTL__RESERVED_MASK
- RLC_UTCL2_CNTL__RESERVED__SHIFT
- RLC_WGP_STATUS__WORK_PENDING_MASK
- RLC_WGP_STATUS__WORK_PENDING__SHIFT
- RLE_HEADER_BYTES
- RLE_VLI_Bits
- RLIM64_INFINITY
- RLIMIT_AS
- RLIMIT_CORE
- RLIMIT_CPU
- RLIMIT_DATA
- RLIMIT_FSIZE
- RLIMIT_LOCKS
- RLIMIT_MEMLOCK
- RLIMIT_MSGQUEUE
- RLIMIT_NICE
- RLIMIT_NOFILE
- RLIMIT_NPROC
- RLIMIT_RSS
- RLIMIT_RTPRIO
- RLIMIT_RTTIME
- RLIMIT_SIGPENDING
- RLIMIT_STACK
- RLIM_INFINITY
- RLIM_NLIMITS
- RLOCK
- RLONG_ADDR
- RLOOKUP_TABLE_ENTRY_SIZE
- RLOPM_CTRL
- RLOPM_PWR_ON
- RLR_MAX
- RLR_MIN
- RLS
- RLS_RRS_SWAP
- RLS_RSP
- RLU
- RLX_HEADER_BYTES
- RL_BUCKET_ELEMS
- RL_COUNTER
- RL_PRTY
- RM
- RM0
- RM0_ISOLATED
- RM1
- RM1_NON_OP
- RM200_I8259A_IRQ_BASE
- RM2_RING_OP
- RM3
- RM3100_CHANNEL
- RM3100_CMM_AXIS_SHIFT
- RM3100_CMM_START
- RM3100_CMM_X
- RM3100_CMM_Y
- RM3100_CMM_Z
- RM3100_CORE_H
- RM3100_POLL_X
- RM3100_POLL_Y
- RM3100_POLL_Z
- RM3100_REG_CC_X
- RM3100_REG_CC_Y
- RM3100_REG_CC_Z
- RM3100_REG_CMM
- RM3100_REG_MX2
- RM3100_REG_MY2
- RM3100_REG_MZ2
- RM3100_REG_POLL
- RM3100_REG_STATUS
- RM3100_REG_TMRC
- RM3100_R_REG_END
- RM3100_R_REG_START
- RM3100_SAMP_NUM
- RM3100_SCAN_BYTES
- RM3100_STATUS_DRDY
- RM3100_TMRC_OFFSET
- RM3100_V_REG_END
- RM3100_V_REG_START
- RM3100_W_REG_END
- RM3100_W_REG_START
- RM3_DETECT
- RM4_NON_OP_DUP
- RM5_RING_OP_DUP
- RM6_BINNING
- RM6_BLIT2D
- RM6_BLIT2DSCALE
- RM6_BYPASS
- RM6_DIRECTED
- RM6_GMEM
- RM6_RESOLVE
- RM7K_CONF_CLK
- RM7K_CONF_SC
- RM7K_CONF_SE
- RM7K_CONF_SI
- RM7K_CONF_TC
- RM7K_CONF_TE
- RM7K_CPU_IRQ_BASE
- RM7_TRACE
- RM9200_USB_DIV_SHIFT
- RM9200_USB_DIV_TAB_SIZE
- RMA
- RMABORT
- RMABT
- RMAC_ADDR_CMD_MEM_OFFSET
- RMAC_ADDR_CMD_MEM_RD
- RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING
- RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD
- RMAC_ADDR_CMD_MEM_WE
- RMAC_ADDR_DATA0_MEM_ADDR
- RMAC_ADDR_DATA0_MEM_USER
- RMAC_ADDR_DATA1_MEM_MASK
- RMAC_CFG_KEY
- RMAC_DA_SHADOW_ECC_DB_ERR
- RMAC_DA_SHADOW_ECC_SG_ERR
- RMAC_DOUBLE_ECC_ERR
- RMAC_ERR_FCS
- RMAC_ERR_FCS_ACCEPT
- RMAC_ERR_LEN_MISMATCH
- RMAC_ERR_LEN_MISMATCH_ACCEPT
- RMAC_ERR_RUNT
- RMAC_ERR_RUNT_ACCEPT
- RMAC_ERR_TOO_LONG
- RMAC_ERR_TOO_LONG_ACCEPT
- RMAC_FRM_RCVD_INT
- RMAC_LINK_STATE_CHANGE_INT
- RMAC_MAX_PYLD_LEN
- RMAC_MAX_PYLD_LEN_DEF
- RMAC_MAX_PYLD_LEN_JUMBO_DEF
- RMAC_PAUSE_GEN
- RMAC_PAUSE_GEN_ENABLE
- RMAC_PAUSE_HG_PTIME
- RMAC_PAUSE_HG_PTIME_DEF
- RMAC_PAUSE_RX
- RMAC_PAUSE_RX_ENABLE
- RMAC_RD_BUF_ECC_DB_ERR
- RMAC_RD_BUF_ECC_SG_ERR
- RMAC_RTH_MAP_ECC_DB_ERR
- RMAC_RTH_MAP_ECC_SG_ERR
- RMAC_RTH_SPDM_ECC_DB_ERR
- RMAC_RTH_SPDM_ECC_SG_ERR
- RMAC_RTS_DS_ECC_DB_ERR
- RMAC_RTS_DS_ECC_SG_ERR
- RMAC_RTS_PNUM_ECC_DB_ERR
- RMAC_RTS_PNUM_ECC_SG_ERR
- RMAC_RTS_VID_ECC_DB_ERR
- RMAC_RTS_VID_ECC_SG_ERR
- RMAC_RX_BUFF_OVRN
- RMAC_RX_SM_ERR
- RMAC_SINGLE_ECC_ERR
- RMAC_UNUSED_INT
- RMAPBT_ATTRFLAG_BITLEN
- RMAPBT_BLOCKCOUNT_BITLEN
- RMAPBT_BMBTFLAG_BITLEN
- RMAPBT_EXNTFLAG_BITLEN
- RMAPBT_OFFSET_BITLEN
- RMAPBT_OWNER_BITLEN
- RMAPBT_STARTBLOCK_BITLEN
- RMAPBT_UNUSED_OFFSET_BITLEN
- RMAP_COMPOUND
- RMAP_EXCLUSIVE
- RMAP_LEFT_CONTIG
- RMAP_LEFT_FILLING
- RMAP_LEFT_VALID
- RMAP_NESTED_GPA_MASK
- RMAP_NESTED_IS_SINGLE_ENTRY
- RMAP_NESTED_LPID_MASK
- RMAP_NESTED_LPID_SHIFT
- RMAP_RECYCLE_THRESHOLD
- RMAP_RIGHT_CONTIG
- RMAP_RIGHT_FILLING
- RMAP_RIGHT_VALID
- RMA_LSMP_REPORT_ENABLE
- RMB_CMD_LOAD_READY
- RMB_CMD_META_DATA_READY
- RMB_DISC
- RMB_MBA_ALT_RESET
- RMB_MBA_AUTH_COMPLETE
- RMB_MBA_COMMAND_REG
- RMB_MBA_IMAGE_REG
- RMB_MBA_META_DATA_AUTH_SUCCESS
- RMB_MBA_MSS_STATUS
- RMB_MBA_STATUS_REG
- RMB_MBA_XPU_UNLOCKED
- RMB_MBA_XPU_UNLOCKED_SCRIBBLED
- RMB_PBL_STATUS_REG
- RMB_PBL_SUCCESS
- RMB_PMI_CODE_LENGTH_REG
- RMB_PMI_CODE_START_REG
- RMB_PMI_META_DATA_REG
- RMC
- RMCA
- RMCA_ADDR
- RMCEN_BIT
- RMCEN_SHIFT
- RMCM
- RMCR
- RMCR_BIT
- RMCR_LCDC_EN_MX1
- RMCR_RNC
- RMCR_SELF_REF
- RMCSF_BIT
- RMCSF_SHIFT
- RMC_BUCKETS
- RMC_QUEUE_MAX_LEN
- RMC_TIMEOUT
- RMD128_BLOCK_SIZE
- RMD128_DIGEST_SIZE
- RMD160_BLOCK_SIZE
- RMD160_DIGEST_SIZE
- RMD1_BUFF
- RMD1_CRC
- RMD1_ENP
- RMD1_ERR
- RMD1_FRAM
- RMD1_OFLO
- RMD1_OWN
- RMD1_OWN_CHIP
- RMD1_OWN_HOST
- RMD1_STP
- RMD256_BLOCK_SIZE
- RMD256_DIGEST_SIZE
- RMD320_BLOCK_SIZE
- RMD320_DIGEST_SIZE
- RMDMAE
- RMDNUM
- RMDNUMMASK
- RMDR1
- RMDR2
- RMDR3
- RMD_CRC
- RMD_ENP
- RMD_ERR
- RMD_FRAM
- RMD_H0
- RMD_H1
- RMD_H2
- RMD_H3
- RMD_H4
- RMD_H5
- RMD_H6
- RMD_H7
- RMD_H8
- RMD_H9
- RMD_K1
- RMD_K2
- RMD_K3
- RMD_K4
- RMD_K5
- RMD_K6
- RMD_K7
- RMD_K8
- RMD_K9
- RMD_OWN
- RMD_STP
- RME32_328_REVISION_NEW
- RME32_328_REVISION_OLD
- RME32_32_REVISION
- RME32_BLOCK_SIZE
- RME32_BUFFER_SIZE
- RME32_CLOCKMODE_MASTER_32
- RME32_CLOCKMODE_MASTER_44
- RME32_CLOCKMODE_MASTER_48
- RME32_CLOCKMODE_SLAVE
- RME32_INPUT_COAXIAL
- RME32_INPUT_INTERNAL
- RME32_INPUT_OPTICAL
- RME32_INPUT_XLR
- RME32_IO_CONFIRM_ACTION_IRQ
- RME32_IO_CONTROL_REGISTER
- RME32_IO_DATA_BUFFER
- RME32_IO_GET_POS
- RME32_IO_RESET_POS
- RME32_IO_SIZE
- RME32_ISWORKING
- RME32_MID_BUFFER_SIZE
- RME32_PRO_REVISION_WITH_8412
- RME32_PRO_REVISION_WITH_8414
- RME32_PRO_WITH_8414
- RME32_RCR_AUDIO_ADDR_MASK
- RME32_RCR_BITPOS_F0
- RME32_RCR_BITPOS_F1
- RME32_RCR_BITPOS_F2
- RME32_RCR_ERF
- RME32_RCR_FREQ_0
- RME32_RCR_FREQ_1
- RME32_RCR_FREQ_2
- RME32_RCR_IRQ
- RME32_RCR_KMODE
- RME32_RCR_LOCK
- RME32_SPDIF_NCHANNELS
- RME32_WCR_ADAT
- RME32_WCR_AUTOSYNC
- RME32_WCR_BITPOS_FREQ_0
- RME32_WCR_BITPOS_FREQ_1
- RME32_WCR_BITPOS_INP_0
- RME32_WCR_BITPOS_INP_1
- RME32_WCR_DS_BM
- RME32_WCR_EMP
- RME32_WCR_FREQ_0
- RME32_WCR_FREQ_1
- RME32_WCR_INP_0
- RME32_WCR_INP_1
- RME32_WCR_MODE24
- RME32_WCR_MONO
- RME32_WCR_MUTE
- RME32_WCR_PD
- RME32_WCR_PRO
- RME32_WCR_RESET
- RME32_WCR_SEL
- RME32_WCR_START
- RME9636_NCHANNELS
- RME9652_ADAT1_IN
- RME9652_ADAT1_INTERNAL
- RME9652_ADAT_SYNC
- RME9652_CHANNEL_BUFFER_BYTES
- RME9652_CHANNEL_BUFFER_SAMPLES
- RME9652_DMA_AREA_BYTES
- RME9652_DMA_AREA_KILOBYTES
- RME9652_DS
- RME9652_DS_rd
- RME9652_Dolby
- RME9652_EMP
- RME9652_ERF
- RME9652_F
- RME9652_F_0
- RME9652_F_1
- RME9652_F_2
- RME9652_IE
- RME9652_IO_EXTENT
- RME9652_IRQ
- RME9652_Master
- RME9652_NCHANNELS
- RME9652_PASSTHRU
- RME9652_PRO
- RME9652_REV15_buf_pos
- RME9652_SPDIFIN_COAXIAL
- RME9652_SPDIFIN_INTERN
- RME9652_SPDIFIN_OPTICAL
- RME9652_SPDIF_CLOCK
- RME9652_SPDIF_IN
- RME9652_SPDIF_OUT
- RME9652_SPDIF_RATE
- RME9652_SPDIF_READ
- RME9652_SPDIF_RESET
- RME9652_SPDIF_SELECT
- RME9652_SPDIF_WRITE
- RME9652_SYNC_FROM_ADAT1
- RME9652_SYNC_FROM_ADAT2
- RME9652_SYNC_FROM_ADAT3
- RME9652_SYNC_FROM_SPDIF
- RME9652_SYNC_MODE
- RME9652_SYNC_PREF
- RME9652_SyncPref_ADAT1
- RME9652_SyncPref_ADAT2
- RME9652_SyncPref_ADAT3
- RME9652_SyncPref_Mask
- RME9652_SyncPref_SPDIF
- RME9652_TC_VALID
- RME9652_buf_pos
- RME9652_buffer_id
- RME9652_control_register
- RME9652_freq
- RME9652_freq1
- RME9652_fs48
- RME9652_init_buffer
- RME9652_inp
- RME9652_inp_0
- RME9652_inp_1
- RME9652_irq_clear
- RME9652_latency
- RME9652_lock
- RME9652_lock_0
- RME9652_lock_1
- RME9652_lock_2
- RME9652_opt_out
- RME9652_play_buffer
- RME9652_rec_buffer
- RME9652_start_bit
- RME9652_status_register
- RME9652_sync
- RME9652_sync_0
- RME9652_sync_1
- RME9652_sync_2
- RME9652_tc_busy
- RME9652_tc_out
- RME9652_tc_valid
- RME9652_thru_base
- RME9652_time_code
- RME9652_wsel
- RME9652_wsel_rd
- RME96_185X_MAX_OUT
- RME96_AD1852_VOL_BITS
- RME96_AD1855_VOL_BITS
- RME96_AR_ANALOG
- RME96_AR_BITPOS_F0
- RME96_AR_BITPOS_F1
- RME96_AR_BITPOS_F2
- RME96_AR_CCLK
- RME96_AR_CDATA
- RME96_AR_CLATCH
- RME96_AR_DAC_EN
- RME96_AR_FREQPAD_0
- RME96_AR_FREQPAD_1
- RME96_AR_FREQPAD_2
- RME96_AR_PD2
- RME96_AR_WSEL
- RME96_ATTENUATION_0
- RME96_ATTENUATION_12
- RME96_ATTENUATION_18
- RME96_ATTENUATION_6
- RME96_BUFFER_SIZE
- RME96_CLOCKMODE_MASTER
- RME96_CLOCKMODE_SLAVE
- RME96_CLOCKMODE_WORDCLOCK
- RME96_DAC_IS_1852
- RME96_DAC_IS_1855
- RME96_HAS_ANALOG_IN
- RME96_HAS_ANALOG_OUT
- RME96_INPUT_ANALOG
- RME96_INPUT_COAXIAL
- RME96_INPUT_INTERNAL
- RME96_INPUT_OPTICAL
- RME96_INPUT_XLR
- RME96_IO_ADDITIONAL_REG
- RME96_IO_CONFIRM_PLAY_IRQ
- RME96_IO_CONFIRM_REC_IRQ
- RME96_IO_CONTROL_REGISTER
- RME96_IO_GET_PLAY_POS
- RME96_IO_GET_REC_POS
- RME96_IO_PLAY_BUFFER
- RME96_IO_REC_BUFFER
- RME96_IO_RESET_PLAY_POS
- RME96_IO_RESET_REC_POS
- RME96_IO_SET_PLAY_POS
- RME96_IO_SET_REC_POS
- RME96_IO_SIZE
- RME96_ISPLAYING
- RME96_ISRECORDING
- RME96_LARGE_BLOCK_SIZE
- RME96_MONITOR_TRACKS_1_2
- RME96_MONITOR_TRACKS_3_4
- RME96_MONITOR_TRACKS_5_6
- RME96_MONITOR_TRACKS_7_8
- RME96_PM_OPS
- RME96_RCR_AUDIO_ADDR_MASK
- RME96_RCR_AUTOSYNC
- RME96_RCR_BITPOS_F0
- RME96_RCR_BITPOS_F1
- RME96_RCR_BITPOS_F2
- RME96_RCR_DEV_ID_0
- RME96_RCR_DEV_ID_1
- RME96_RCR_F0
- RME96_RCR_F1
- RME96_RCR_F2
- RME96_RCR_IRQ
- RME96_RCR_IRQ_2
- RME96_RCR_LOCK
- RME96_RCR_T_OUT
- RME96_RCR_VERF
- RME96_RESUME_BOTH
- RME96_RESUME_CAPTURE
- RME96_RESUME_PLAYBACK
- RME96_SMALL_BLOCK_SIZE
- RME96_SPDIF_NCHANNELS
- RME96_START_BOTH
- RME96_START_CAPTURE
- RME96_START_PLAYBACK
- RME96_STOP_BOTH
- RME96_STOP_CAPTURE
- RME96_STOP_PLAYBACK
- RME96_TB_CLEAR_CAPTURE_IRQ
- RME96_TB_CLEAR_PLAYBACK_IRQ
- RME96_TB_RESET_CAPTUREPOS
- RME96_TB_RESET_PLAYPOS
- RME96_TB_START_CAPTURE
- RME96_TB_START_PLAYBACK
- RME96_TB_STOP_CAPTURE
- RME96_TB_STOP_PLAYBACK
- RME96_WCR_ADAT
- RME96_WCR_BITPOS_FREQ_0
- RME96_WCR_BITPOS_FREQ_1
- RME96_WCR_BITPOS_GAIN_0
- RME96_WCR_BITPOS_GAIN_1
- RME96_WCR_BITPOS_INP_0
- RME96_WCR_BITPOS_INP_1
- RME96_WCR_BITPOS_MONITOR_0
- RME96_WCR_BITPOS_MONITOR_1
- RME96_WCR_BM
- RME96_WCR_BM_2
- RME96_WCR_DOLBY
- RME96_WCR_DS
- RME96_WCR_EMP
- RME96_WCR_FREQ_0
- RME96_WCR_FREQ_1
- RME96_WCR_GAIN_0
- RME96_WCR_GAIN_1
- RME96_WCR_IDIS
- RME96_WCR_INP_0
- RME96_WCR_INP_1
- RME96_WCR_ISEL
- RME96_WCR_MASTER
- RME96_WCR_MODE24
- RME96_WCR_MODE24_2
- RME96_WCR_MONITOR_0
- RME96_WCR_MONITOR_1
- RME96_WCR_PD
- RME96_WCR_PRO
- RME96_WCR_SEL
- RME96_WCR_START
- RME96_WCR_START_2
- RME96_WCR_THRU_0
- RME96_WCR_THRU_1
- RME96_WCR_THRU_2
- RME96_WCR_THRU_3
- RME96_WCR_THRU_4
- RME96_WCR_THRU_5
- RME96_WCR_THRU_6
- RME96_WCR_THRU_7
- RMEM
- RME_Q_NUM
- RMExt
- RMFCR
- RMF_CODE
- RMH_SSIZE_ARG
- RMH_SSIZE_FIXED
- RMH_SSIZE_MASK
- RMI4_END_OF_PDT
- RMI4_MAX_PAGE
- RMI4_PAGE_MASK
- RMI4_PAGE_SIZE
- RMID_VAL_ERROR
- RMID_VAL_UNAVAIL
- RMII0_CRS_DV_A_MARK
- RMII0_CRS_DV_B_MARK
- RMII0_CRS_DV_MARK
- RMII0_MDC_A_MARK
- RMII0_MDC_B_MARK
- RMII0_MDIO_A_MARK
- RMII0_MDIO_B_MARK
- RMII0_REFCLK_MARK
- RMII0_RXD0_A_MARK
- RMII0_RXD0_B_MARK
- RMII0_RXD0_MARK
- RMII0_RXD1_A_MARK
- RMII0_RXD1_B_MARK
- RMII0_RXD1_MARK
- RMII0_RX_ER_A_MARK
- RMII0_RX_ER_B_MARK
- RMII0_RX_ER_MARK
- RMII0_TXD0_A_MARK
- RMII0_TXD0_B_MARK
- RMII0_TXD0_MARK
- RMII0_TXD1_A_MARK
- RMII0_TXD1_B_MARK
- RMII0_TXD1_MARK
- RMII0_TXD_EN_A_MARK
- RMII0_TXD_EN_B_MARK
- RMII0_TXEN_MARK
- RMII1_CRS_DV_MARK
- RMII1_DESC
- RMII1_REFCLK_MARK
- RMII1_RXD0_MARK
- RMII1_RXD1_MARK
- RMII1_RX_ER_MARK
- RMII1_TXD0_MARK
- RMII1_TXD1_MARK
- RMII1_TXEN_MARK
- RMII2_DESC
- RMIIMODE
- RMII_CLK_SRC_INTERNAL
- RMII_CLK_SRC_RXC
- RMII_CRS_DV_MARK
- RMII_MDC_MARK
- RMII_MDIO_MARK
- RMII_MII
- RMII_REF125CK_MARK
- RMII_REF50CK_MARK
- RMII_REF_CLK_MARK
- RMII_REGS_ADDR
- RMII_REGS_CNT
- RMII_RXD0_MARK
- RMII_RXD1_MARK
- RMII_RX_ER_MARK
- RMII_SEG_NUM
- RMII_TXD0_MARK
- RMII_TXD1_MARK
- RMII_TX_EN_MARK
- RMINAR
- RMINCNT
- RMIPerfSel
- RMI_2D_OBJECT_FINGER
- RMI_2D_OBJECT_NONE
- RMI_2D_OBJECT_PALM
- RMI_2D_OBJECT_STYLUS
- RMI_2D_OBJECT_UNCLASSIFIED
- RMI_2D_REL_POS_MAX
- RMI_2D_REL_POS_MIN
- RMI_ATTN_REPORT_ID
- RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK
- RMI_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT
- RMI_CGTT_SCLK_CTRL__ON_DELAY_MASK
- RMI_CGTT_SCLK_CTRL__ON_DELAY__SHIFT
- RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK
- RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT
- RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK
- RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT
- RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK
- RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT
- RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK
- RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT
- RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK
- RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT
- RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK
- RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT
- RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK
- RMI_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT
- RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0_MASK
- RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT
- RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1_MASK
- RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT
- RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2_MASK
- RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT
- RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3_MASK
- RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT
- RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4_MASK
- RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT
- RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5_MASK
- RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT
- RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6_MASK
- RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT
- RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7_MASK
- RMI_CGTT_SCLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT
- RMI_CID
- RMI_CID_CC
- RMI_CID_CM
- RMI_CID_DC
- RMI_CID_FC
- RMI_CID_S
- RMI_CID_TILE
- RMI_CID_Z
- RMI_CID_ZPCPSD
- RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK
- RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT
- RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK
- RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT
- RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK
- RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT
- RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK
- RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT
- RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK_MASK
- RMI_CLOCK_CNTRL__DYN_CLK_RB1_BUSY_MASK__SHIFT
- RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK_MASK
- RMI_CLOCK_CNTRL__DYN_CLK_RB1_WAKEUP_MASK__SHIFT
- RMI_DATE_CODE_LENGTH
- RMI_DEBUG_2D_SENSOR
- RMI_DEBUG_CORE
- RMI_DEBUG_FN
- RMI_DEBUG_XPORT
- RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN_MASK
- RMI_DEMUX_CNTL__DEMUX_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT
- RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK
- RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN_MASK
- RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN__SHIFT
- RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT
- RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_MASK
- RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE_MASK
- RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_OVERRIDE__SHIFT
- RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK
- RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT
- RMI_DEMUX_CNTL__DEMUX_ARB0_STALL__SHIFT
- RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN_MASK
- RMI_DEMUX_CNTL__DEMUX_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT
- RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK
- RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN_MASK
- RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN__SHIFT
- RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT
- RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_MASK
- RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE_MASK
- RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_OVERRIDE__SHIFT
- RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK
- RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT
- RMI_DEMUX_CNTL__DEMUX_ARB1_STALL__SHIFT
- RMI_DEVICE
- RMI_DEVICE_HAS_PHYS_BUTTONS
- RMI_DEVICE_OUTPUT_SET_REPORT
- RMI_DEVICE_RESET_CMD
- RMI_F01_BASIC_QUERY_LEN
- RMI_F01_CMD_DEVICE_RESET
- RMI_F01_CTRL0_CHARGER_BIT
- RMI_F01_CTRL0_CONFIGURED_BIT
- RMI_F01_CTRL0_NOSLEEP_BIT
- RMI_F01_CTRL0_REPORTRATE_BIT
- RMI_F01_CTRL0_SLEEP_MODE_MASK
- RMI_F01_QRY1_CUSTOM_MAP
- RMI_F01_QRY1_HAS_ADJ_DOZE
- RMI_F01_QRY1_HAS_ADJ_DOZE_HOFF
- RMI_F01_QRY1_HAS_CHARGER_INP
- RMI_F01_QRY1_HAS_LTS
- RMI_F01_QRY1_HAS_QUERY42
- RMI_F01_QRY1_HAS_SENSOR_ID
- RMI_F01_QRY1_NON_COMPLIANT
- RMI_F01_QRY2_PRODINFO_MASK
- RMI_F01_QRY5_YEAR_MASK
- RMI_F01_QRY6_MONTH_MASK
- RMI_F01_QRY7_DAY_MASK
- RMI_F01_STATUS_BOOTLOADER
- RMI_F01_STATUS_CODE
- RMI_F01_STATUS_UNCONFIGURED
- RMI_F03_BYTES_PER_DEVICE
- RMI_F03_BYTES_PER_DEVICE_SHIFT
- RMI_F03_DEVICE_COUNT
- RMI_F03_OB_DATA_OFFSET
- RMI_F03_OB_FLAG_PARITY
- RMI_F03_OB_FLAG_TIMEOUT
- RMI_F03_OB_OFFSET
- RMI_F03_OB_SIZE
- RMI_F03_QUEUE_LENGTH
- RMI_F03_RX_DATA_OFB
- RMI_F11_ABS_BYTES
- RMI_F11_ABS_DATA_SIZE_MASK
- RMI_F11_ABS_POS_FILT
- RMI_F11_CLICKPAD_PROPS_MASK
- RMI_F11_CLICKPAD_PROPS_SHIFT
- RMI_F11_CONFIGURABLE
- RMI_F11_CTRL_REG_COUNT
- RMI_F11_DELTA_X_THRESHOLD
- RMI_F11_DELTA_Y_THRESHOLD
- RMI_F11_DISABLE_ABS_REPORT
- RMI_F11_DOUBLE_TAP
- RMI_F11_DRIBBLE
- RMI_F11_EARLY_TAP
- RMI_F11_FLICK
- RMI_F11_GESTURE_FINGER_COUNT_MASK
- RMI_F11_HAS_8BIT_W
- RMI_F11_HAS_ABS
- RMI_F11_HAS_ADJUSTABLE_MAPPING
- RMI_F11_HAS_ADJ_HYST
- RMI_F11_HAS_ADVANCED_GESTURES
- RMI_F11_HAS_ALGORITHM_SELECTION
- RMI_F11_HAS_ANCHORED_FINGER
- RMI_F11_HAS_BENDING_CORRECTION
- RMI_F11_HAS_CHIRAL
- RMI_F11_HAS_CONTACT_GEOMETRY
- RMI_F11_HAS_DOUBLE_TAP
- RMI_F11_HAS_DRIBBLE
- RMI_F11_HAS_DRUMMING_FILTER
- RMI_F11_HAS_EARLY_TAP
- RMI_F11_HAS_FINGER_LIMIT
- RMI_F11_HAS_FINGER_SIZE
- RMI_F11_HAS_FLICK
- RMI_F11_HAS_GAPLESS_FINGER
- RMI_F11_HAS_GAPLESS_FINGER_TUNING
- RMI_F11_HAS_GESTURES
- RMI_F11_HAS_INDIVIDUAL_SCROLL_ZONES
- RMI_F11_HAS_INFO2
- RMI_F11_HAS_JITTER_FILTER
- RMI_F11_HAS_LARGE_OBJECT_SUPPRESSION
- RMI_F11_HAS_LINEAR_COEFF
- RMI_F11_HAS_MF_EDGE_MOTION
- RMI_F11_HAS_MF_SCROLL
- RMI_F11_HAS_MF_SCROLL_INERTIA
- RMI_F11_HAS_PALM_DET
- RMI_F11_HAS_PALM_DET_SENSITIVITY
- RMI_F11_HAS_PEN
- RMI_F11_HAS_PEN_FILTERS
- RMI_F11_HAS_PEN_HOVER_DISCRIMINATION
- RMI_F11_HAS_PHYSICAL_PROPS
- RMI_F11_HAS_PINCH
- RMI_F11_HAS_PITCH_INFO
- RMI_F11_HAS_PRESS
- RMI_F11_HAS_PROXIMITY
- RMI_F11_HAS_QUERY11
- RMI_F11_HAS_QUERY12
- RMI_F11_HAS_QUERY27
- RMI_F11_HAS_QUERY28
- RMI_F11_HAS_QUERY9
- RMI_F11_HAS_REL
- RMI_F11_HAS_ROTATE
- RMI_F11_HAS_SCROLL_ZONES
- RMI_F11_HAS_SEGMENTATION_AGGRESSIVENESS
- RMI_F11_HAS_SENSITIVITY_ADJ
- RMI_F11_HAS_SINGLE_TAP
- RMI_F11_HAS_SUPPRESS_ON_PALM_DETECT
- RMI_F11_HAS_TAP_AND_HOLD
- RMI_F11_HAS_TOUCH_SHAPES
- RMI_F11_HAS_TWO_PEN_THRESHOLDS
- RMI_F11_HAS_W_TUNING
- RMI_F11_HAS_XY_CLIP
- RMI_F11_HAS_Z_TUNING
- RMI_F11_IS_CLEAR
- RMI_F11_JITTER_FILTER_MASK
- RMI_F11_JITTER_FILTER_SHIFT
- RMI_F11_JITTER_WINDOW_MASK
- RMI_F11_LIGHT_CONTROL_MASK
- RMI_F11_MANUAL_TRACKED_FINGER
- RMI_F11_MANUAL_TRACKING
- RMI_F11_MOTION_SENSITIVITY_MASK
- RMI_F11_MOUSE_BUTTONS_MASK
- RMI_F11_MOUSE_BUTTONS_SHIFT
- RMI_F11_NR_ELECTRODES_MASK
- RMI_F11_NR_FINGERS_MASK
- RMI_F11_NR_TOUCH_SHAPES_MASK
- RMI_F11_PALM_DETECT
- RMI_F11_PALM_DETECT_THRESH_MASK
- RMI_F11_PINCH
- RMI_F11_PRESS
- RMI_F11_QUERY_GESTURE_SIZE
- RMI_F11_QUERY_SIZE
- RMI_F11_REL_BALLISTICS
- RMI_F11_REL_BYTES
- RMI_F11_REL_POS_FILT
- RMI_F11_REPORT_BEYOND_CLIP
- RMI_F11_REPORT_MODE_MASK
- RMI_F11_REZERO
- RMI_F11_ROTATE
- RMI_F11_SCROLLZONE
- RMI_F11_SHAPE
- RMI_F11_SINGLE_TAP
- RMI_F11_TAP_AND_HOLD
- RMI_F12_OBJECT_COVER
- RMI_F12_OBJECT_ERASER
- RMI_F12_OBJECT_FINGER
- RMI_F12_OBJECT_GLOVED_FINGER
- RMI_F12_OBJECT_HAND_EDGE
- RMI_F12_OBJECT_NARROW_OBJECT
- RMI_F12_OBJECT_NONE
- RMI_F12_OBJECT_PALM
- RMI_F12_OBJECT_SMALL_OBJECT
- RMI_F12_OBJECT_STYLUS
- RMI_F12_OBJECT_STYLUS_2
- RMI_F12_OBJECT_UNCLASSIFIED
- RMI_F30_CTRL_10_NUM_MECH_MOUSE_BTNS
- RMI_F30_CTRL_1_GPIO_DEBOUNCE
- RMI_F30_CTRL_1_HALT
- RMI_F30_CTRL_1_HALTED
- RMI_F30_CTRL_MAX_BYTES
- RMI_F30_CTRL_MAX_REGS
- RMI_F30_CTRL_MAX_REG_BLOCKS
- RMI_F30_CTRL_REGS_MAX_SIZE
- RMI_F30_EXTENDED_PATTERNS
- RMI_F30_GPIO_LED_COUNT
- RMI_F30_HAS_GPIO
- RMI_F30_HAS_GPIO_DRV_CTL
- RMI_F30_HAS_HAPTIC
- RMI_F30_HAS_LED
- RMI_F30_HAS_MAPPABLE_BUTTONS
- RMI_F30_HAS_MECH_MOUSE_BTNS
- RMI_F30_QUERY_SIZE
- RMI_FN_MAX_IRQS
- RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE_MASK
- RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE__SHIFT
- RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK
- RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT
- RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK
- RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT
- RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE_MASK
- RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE__SHIFT
- RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK
- RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK
- RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT
- RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT
- RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK
- RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT
- RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK
- RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT
- RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN_MASK
- RMI_GENERAL_CNTL1__UTCL1_PROBE0_RR_ARB_BURST_HINT_EN__SHIFT
- RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN_MASK
- RMI_GENERAL_CNTL1__UTCL1_PROBE1_RR_ARB_BURST_HINT_EN__SHIFT
- RMI_GENERAL_CNTL__BURST_DISABLE_MASK
- RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT
- RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK
- RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT
- RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK
- RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT
- RMI_GENERAL_CNTL__RB1_HARVEST_EN_MASK
- RMI_GENERAL_CNTL__RB1_HARVEST_EN__SHIFT
- RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK_MASK
- RMI_GENERAL_CNTL__SKID_FIFO_0_OVERFLOW_ERROR_MASK__SHIFT
- RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK_MASK
- RMI_GENERAL_CNTL__SKID_FIFO_0_UNDERFLOW_ERROR_MASK__SHIFT
- RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK_MASK
- RMI_GENERAL_CNTL__SKID_FIFO_1_OVERFLOW_ERROR_MASK__SHIFT
- RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK_MASK
- RMI_GENERAL_CNTL__SKID_FIFO_1_UNDERFLOW_ERROR_MASK__SHIFT
- RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK_MASK
- RMI_GENERAL_CNTL__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK__SHIFT
- RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK
- RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT
- RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_MASK
- RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE_MASK
- RMI_GENERAL_CNTL__XBAR_MUX_CONFIG_UPDATE__SHIFT
- RMI_GENERAL_CNTL__XBAR_MUX_CONFIG__SHIFT
- RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK
- RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT
- RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK
- RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT
- RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY_MASK
- RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_1_BUSY__SHIFT
- RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK
- RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT
- RMI_GENERAL_STATUS__RMI_UTCL1_BUSY_MASK
- RMI_GENERAL_STATUS__RMI_UTCL1_BUSY__SHIFT
- RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK
- RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT
- RMI_GENERAL_STATUS__RMI_XNACK_BUSY_MASK
- RMI_GENERAL_STATUS__RMI_XNACK_BUSY__SHIFT
- RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK
- RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT
- RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK
- RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT
- RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK
- RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT
- RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK
- RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT
- RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK
- RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT
- RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK
- RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT
- RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK
- RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT
- RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK
- RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT
- RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK
- RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT
- RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK
- RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT
- RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK
- RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT
- RMI_GENERAL_STATUS__UTC_PROBE0_BUSY_MASK
- RMI_GENERAL_STATUS__UTC_PROBE0_BUSY__SHIFT
- RMI_GENERAL_STATUS__UTC_PROBE1_BUSY_MASK
- RMI_GENERAL_STATUS__UTC_PROBE1_BUSY__SHIFT
- RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK
- RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT
- RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY_MASK
- RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_1_BUSY__SHIFT
- RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY_MASK
- RMI_GENERAL_STATUS__XNACK_FIFO_EMPTY__SHIFT
- RMI_GENERAL_STATUS__XNACK_FIFO_FULL_MASK
- RMI_GENERAL_STATUS__XNACK_FIFO_FULL__SHIFT
- RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED_MASK
- RMI_GENERAL_STATUS__XNACK_FIFO_NUM_USED__SHIFT
- RMI_I2C_PAGE
- RMI_MODE_ATTN_REPORTS
- RMI_MODE_NO_PACKED_ATTN_REPORTS
- RMI_MODE_OFF
- RMI_MOUSE_REPORT_ID
- RMI_PAGE
- RMI_PAGE_CONTENT_CONTAINER
- RMI_PAGE_SELECT_REGISTER
- RMI_PDT_ENTRY_SIZE
- RMI_PDT_FUNCTION_VERSION_MASK
- RMI_PDT_INT_SOURCE_COUNT_MASK
- RMI_PDT_PROPS_HAS_BSR
- RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK
- RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT
- RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK
- RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT
- RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK
- RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT
- RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK
- RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT
- RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK
- RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT
- RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK
- RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT
- RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK
- RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT
- RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK
- RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT
- RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK
- RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT
- RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK
- RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT
- RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK
- RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT
- RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK
- RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT
- RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK
- RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT
- RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK
- RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT
- RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK
- RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT
- RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK
- RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT
- RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK
- RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT
- RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK
- RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT
- RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK
- RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT
- RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK
- RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT
- RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK
- RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT
- RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK
- RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT
- RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK
- RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT
- RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK
- RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT
- RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK
- RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT
- RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK
- RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT
- RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK
- RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT
- RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK
- RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT
- RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK
- RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT
- RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK
- RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT
- RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK
- RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT
- RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK
- RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT
- RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK
- RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT
- RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK
- RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT
- RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK
- RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT
- RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK
- RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT
- RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK
- RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT
- RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK
- RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT
- RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK
- RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT
- RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK
- RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT
- RMI_PERF_SEL_BUSY
- RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR
- RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB
- RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR
- RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB
- RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0
- RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1
- RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2
- RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3
- RMI_PERF_SEL_DYN_CLK_CMN_VLD
- RMI_PERF_SEL_DYN_CLK_PERF_VLD
- RMI_PERF_SEL_DYN_CLK_RB_VLD
- RMI_PERF_SEL_EVENT_SEND
- RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ
- RMI_PERF_SEL_LAT_FIFO_FULL
- RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ
- RMI_PERF_SEL_LAT_FIFO_NUM_USED
- RMI_PERF_SEL_LEVEL_ADD_RMI_TO_UTC
- RMI_PERF_SEL_LEVEL_ADD_UTCL1_TO_UTCL2
- RMI_PERF_SEL_NONE
- RMI_PERF_SEL_PERF_WINDOW
- RMI_PERF_SEL_POP_DEMUX_RTSB_RTR
- RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB
- RMI_PERF_SEL_POP_DEMUX_RTS_RTR
- RMI_PERF_SEL_POP_DEMUX_RTS_RTRB
- RMI_PERF_SEL_POP_XNACK_RTSB_RTR
- RMI_PERF_SEL_POP_XNACK_RTSB_RTRB
- RMI_PERF_SEL_POP_XNACK_RTS_RTR
- RMI_PERF_SEL_POP_XNACK_RTS_RTRB
- RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR
- RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB
- RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR
- RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB
- RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT
- RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT
- RMI_PERF_SEL_PROBE_UTCL1_VMID_BYPASS
- RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT
- RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY
- RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR
- RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB
- RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR
- RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB
- RMI_PERF_SEL_PRT_FIFO_BUSY
- RMI_PERF_SEL_PRT_FIFO_NUM_USED
- RMI_PERF_SEL_PRT_FIFO_REQ
- RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID
- RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0
- RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1
- RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2
- RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3
- RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4
- RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5
- RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6
- RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7
- RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID
- RMI_PERF_SEL_RB_RMI_32BWRREQ_INFLIGHT_ALL_ORONE_CID
- RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID
- RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID
- RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID
- RMI_PERF_SEL_RB_RMI_RDREQ_BUSY
- RMI_PERF_SEL_RB_RMI_RDREQ_CID0
- RMI_PERF_SEL_RB_RMI_RDREQ_CID1
- RMI_PERF_SEL_RB_RMI_RDREQ_CID2
- RMI_PERF_SEL_RB_RMI_RDREQ_CID3
- RMI_PERF_SEL_RB_RMI_RDREQ_CID4
- RMI_PERF_SEL_RB_RMI_RDREQ_CID5
- RMI_PERF_SEL_RB_RMI_RDREQ_CID6
- RMI_PERF_SEL_RB_RMI_RDREQ_CID7
- RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY
- RMI_PERF_SEL_RB_RMI_RDREQ_TO_RDRET_BUSY
- RMI_PERF_SEL_RB_RMI_RD_BUSY
- RMI_PERF_SEL_RB_RMI_RD_FIFO_EMPTY
- RMI_PERF_SEL_RB_RMI_RD_FIFO_MAX
- RMI_PERF_SEL_RB_RMI_RD_IDLE
- RMI_PERF_SEL_RB_RMI_RD_INTF_BUSY
- RMI_PERF_SEL_RB_RMI_RD_STALL
- RMI_PERF_SEL_RB_RMI_RD_STARVE
- RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID
- RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID
- RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID
- RMI_PERF_SEL_RB_RMI_WRREQ_BUSY
- RMI_PERF_SEL_RB_RMI_WRREQ_CID0
- RMI_PERF_SEL_RB_RMI_WRREQ_CID1
- RMI_PERF_SEL_RB_RMI_WRREQ_CID2
- RMI_PERF_SEL_RB_RMI_WRREQ_CID3
- RMI_PERF_SEL_RB_RMI_WRREQ_CID4
- RMI_PERF_SEL_RB_RMI_WRREQ_CID5
- RMI_PERF_SEL_RB_RMI_WRREQ_CID6
- RMI_PERF_SEL_RB_RMI_WRREQ_CID7
- RMI_PERF_SEL_RB_RMI_WRREQ_INFLIGHT_ALL_ORONE_CID
- RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY
- RMI_PERF_SEL_RB_RMI_WRREQ_TO_WRRET_BUSY
- RMI_PERF_SEL_RB_RMI_WR_BUSY
- RMI_PERF_SEL_RB_RMI_WR_FIFO_EMPTY
- RMI_PERF_SEL_RB_RMI_WR_FIFO_MAX
- RMI_PERF_SEL_RB_RMI_WR_IDLE
- RMI_PERF_SEL_RB_RMI_WR_INTF_BUSY
- RMI_PERF_SEL_RB_RMI_WR_STALL
- RMI_PERF_SEL_RB_RMI_WR_STARVE
- RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR
- RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB
- RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR
- RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB
- RMI_PERF_SEL_REG_CLK_VLD
- RMI_PERF_SEL_REORDER_FIFO_BUSY
- RMI_PERF_SEL_REORDER_FIFO_REQ
- RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0
- RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1
- RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10
- RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11
- RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12
- RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13
- RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14
- RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15
- RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2
- RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3
- RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4
- RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5
- RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6
- RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7
- RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8
- RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9
- RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL
- RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0
- RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1
- RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10
- RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11
- RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12
- RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13
- RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14
- RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15
- RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2
- RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3
- RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4
- RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5
- RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6
- RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7
- RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8
- RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9
- RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL
- RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID
- RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0
- RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1
- RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2
- RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3
- RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4
- RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5
- RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6
- RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7
- RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0
- RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1
- RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2
- RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3
- RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID
- RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0
- RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1
- RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2
- RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3
- RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4
- RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5
- RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6
- RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7
- RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0
- RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1
- RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2
- RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3
- RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID
- RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0
- RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1
- RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2
- RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3
- RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4
- RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5
- RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6
- RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7
- RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0
- RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1
- RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2
- RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3
- RMI_PERF_SEL_RMI_TC_64BRDREQ_ALL_ORONE_CID
- RMI_PERF_SEL_RMI_TC_64BWRREQ_ALL_ORONE_CID
- RMI_PERF_SEL_RMI_TC_CREDIT_FULL_NO_PENDING_SEND
- RMI_PERF_SEL_RMI_TC_CREDIT_ZERO_PENDING_SEND
- RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID
- RMI_PERF_SEL_RMI_TC_RDREQ_CID0
- RMI_PERF_SEL_RMI_TC_RDREQ_CID1
- RMI_PERF_SEL_RMI_TC_RDREQ_CID2
- RMI_PERF_SEL_RMI_TC_RDREQ_CID3
- RMI_PERF_SEL_RMI_TC_RDREQ_CID4
- RMI_PERF_SEL_RMI_TC_RDREQ_CID5
- RMI_PERF_SEL_RMI_TC_RDREQ_CID6
- RMI_PERF_SEL_RMI_TC_RDREQ_CID7
- RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID
- RMI_PERF_SEL_RMI_TC_REQ_BUSY
- RMI_PERF_SEL_RMI_TC_STALL_ALLREQ
- RMI_PERF_SEL_RMI_TC_STALL_RDREQ
- RMI_PERF_SEL_RMI_TC_STALL_WRREQ
- RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID
- RMI_PERF_SEL_RMI_TC_WRREQ_CID0
- RMI_PERF_SEL_RMI_TC_WRREQ_CID1
- RMI_PERF_SEL_RMI_TC_WRREQ_CID2
- RMI_PERF_SEL_RMI_TC_WRREQ_CID3
- RMI_PERF_SEL_RMI_TC_WRREQ_CID4
- RMI_PERF_SEL_RMI_TC_WRREQ_CID5
- RMI_PERF_SEL_RMI_TC_WRREQ_CID6
- RMI_PERF_SEL_RMI_TC_WRREQ_CID7
- RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID
- RMI_PERF_SEL_RMI_UTC_BUSY
- RMI_PERF_SEL_RMI_UTC_REQ
- RMI_PERF_SEL_SKID_FIFO_BUSY
- RMI_PERF_SEL_SKID_FIFO_DEPTH
- RMI_PERF_SEL_SKID_FIFO_IN_RTS
- RMI_PERF_SEL_SKID_FIFO_IN_RTSB
- RMI_PERF_SEL_SKID_FIFO_OUT_RTS
- RMI_PERF_SEL_SKID_FIFO_OUT_RTSB
- RMI_PERF_SEL_SKID_FIFO_REQ
- RMI_PERF_SEL_TCIW_BUSY
- RMI_PERF_SEL_TCIW_INFLIGHT_COUNT
- RMI_PERF_SEL_TCIW_REQ
- RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID
- RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID
- RMI_PERF_SEL_UTCL1_BUSY
- RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL
- RMI_PERF_SEL_UTCL1_LFIFO_FULL
- RMI_PERF_SEL_UTCL1_PERMISSION_MISS
- RMI_PERF_SEL_UTCL1_REQUEST
- RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX
- RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES
- RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT
- RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL
- RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS
- RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS
- RMI_PERF_SEL_UTCL1_TRANSLATION_HIT
- RMI_PERF_SEL_UTCL1_TRANSLATION_MISS
- RMI_PERF_SEL_UTCL1_UTCL2_REQ
- RMI_PERF_SEL_UTC_POP_RTSB_RTR
- RMI_PERF_SEL_UTC_POP_RTSB_RTRB
- RMI_PERF_SEL_UTC_POP_RTS_RTR
- RMI_PERF_SEL_UTC_POP_RTS_RTRB
- RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR
- RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB
- RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR
- RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB
- RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR
- RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR
- RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR
- RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR
- RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR
- RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR
- RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB
- RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR
- RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB
- RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR
- RMI_PERF_SEL_XNACK_FIFO_BUSY
- RMI_PERF_SEL_XNACK_FIFO_FULL
- RMI_PERF_SEL_XNACK_FIFO_NUM_USED
- RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR
- RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB
- RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR
- RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB
- RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK
- RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT
- RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK
- RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT
- RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK
- RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT
- RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK
- RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT
- RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK
- RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT
- RMI_PRODUCT_ID_LENGTH
- RMI_PRODUCT_INFO_LENGTH
- RMI_PROT_VER_REG
- RMI_RB_GLX_CID_MAP__CB_CMASK_MAP_MASK
- RMI_RB_GLX_CID_MAP__CB_CMASK_MAP__SHIFT
- RMI_RB_GLX_CID_MAP__CB_COLOR_MAP_MASK
- RMI_RB_GLX_CID_MAP__CB_COLOR_MAP__SHIFT
- RMI_RB_GLX_CID_MAP__CB_DCC_MAP_MASK
- RMI_RB_GLX_CID_MAP__CB_DCC_MAP__SHIFT
- RMI_RB_GLX_CID_MAP__CB_FMASK_MAP_MASK
- RMI_RB_GLX_CID_MAP__CB_FMASK_MAP__SHIFT
- RMI_RB_GLX_CID_MAP__DB_S_MAP_MASK
- RMI_RB_GLX_CID_MAP__DB_S_MAP__SHIFT
- RMI_RB_GLX_CID_MAP__DB_TILE_MAP_MASK
- RMI_RB_GLX_CID_MAP__DB_TILE_MAP__SHIFT
- RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP_MASK
- RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP__SHIFT
- RMI_RB_GLX_CID_MAP__DB_Z_MAP_MASK
- RMI_RB_GLX_CID_MAP__DB_Z_MAP__SHIFT
- RMI_READ_ADDR_REPORT_ID
- RMI_READ_DATA_PENDING
- RMI_READ_DATA_REPORT_ID
- RMI_READ_REQUEST_PENDING
- RMI_REG_DESC_PRESENSE_BITS
- RMI_REG_DESC_SUBPACKET_BITS
- RMI_REG_STATE_DEFAULT
- RMI_REG_STATE_OFF
- RMI_REG_STATE_ON
- RMI_SCAN_CONTINUE
- RMI_SCAN_DONE
- RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK
- RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT
- RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK
- RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT
- RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN_MASK
- RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_EN__SHIFT
- RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK
- RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT
- RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK
- RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT
- RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK
- RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT
- RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0_MASK
- RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB0__SHIFT
- RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1_MASK
- RMI_SCOREBOARD_CNTL__TIME_STAMP_FLUSH_RB1__SHIFT
- RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK
- RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT
- RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK
- RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT
- RMI_SCOREBOARD_STATUS0__COUNTER_SELECT_MASK
- RMI_SCOREBOARD_STATUS0__COUNTER_SELECT__SHIFT
- RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK
- RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT
- RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK
- RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT
- RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK
- RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT
- RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK
- RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT
- RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK
- RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT
- RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK
- RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT
- RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK
- RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT
- RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK
- RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT
- RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK
- RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT
- RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK
- RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT
- RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK
- RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT
- RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK
- RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT
- RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK
- RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT
- RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK
- RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT
- RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK
- RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT
- RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK
- RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT
- RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK
- RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT
- RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK
- RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT
- RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK
- RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT
- RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK
- RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT
- RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK
- RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT
- RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK
- RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT
- RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK
- RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT
- RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK
- RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT
- RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK
- RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT
- RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK
- RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT
- RMI_SELF_DISCOVERY_CONTAINER
- RMI_SET_RMI_MODE_REPORT_ID
- RMI_SLEEP_MODE_NORMAL
- RMI_SLEEP_MODE_RESERVED0
- RMI_SLEEP_MODE_RESERVED1
- RMI_SLEEP_MODE_SENSOR_SLEEP
- RMI_SMB2_MAP_FLAGS_WE
- RMI_SMB2_MAP_SIZE
- RMI_SPARE_1__RMI_REORDER_DIS_BY_CID_MASK
- RMI_SPARE_1__RMI_REORDER_DIS_BY_CID__SHIFT
- RMI_SPARE_1__SPARE_BIT_10_MASK
- RMI_SPARE_1__SPARE_BIT_10__SHIFT
- RMI_SPARE_1__SPARE_BIT_11_MASK
- RMI_SPARE_1__SPARE_BIT_11__SHIFT
- RMI_SPARE_1__SPARE_BIT_12_MASK
- RMI_SPARE_1__SPARE_BIT_12__SHIFT
- RMI_SPARE_1__SPARE_BIT_13_MASK
- RMI_SPARE_1__SPARE_BIT_13__SHIFT
- RMI_SPARE_1__SPARE_BIT_14_MASK
- RMI_SPARE_1__SPARE_BIT_14__SHIFT
- RMI_SPARE_1__SPARE_BIT_15_MASK
- RMI_SPARE_1__SPARE_BIT_15__SHIFT
- RMI_SPARE_1__SPARE_BIT_16_1_MASK
- RMI_SPARE_1__SPARE_BIT_16_1__SHIFT
- RMI_SPARE_1__SPARE_BIT_8_1_MASK
- RMI_SPARE_1__SPARE_BIT_8_1__SHIFT
- RMI_SPARE_1__SPARE_BIT_8_MASK
- RMI_SPARE_1__SPARE_BIT_8__SHIFT
- RMI_SPARE_1__SPARE_BIT_9_MASK
- RMI_SPARE_1__SPARE_BIT_9__SHIFT
- RMI_SPARE_2__SPARE_BIT_16_MASK
- RMI_SPARE_2__SPARE_BIT_16__SHIFT
- RMI_SPARE_2__SPARE_BIT_17_MASK
- RMI_SPARE_2__SPARE_BIT_17__SHIFT
- RMI_SPARE_2__SPARE_BIT_18_MASK
- RMI_SPARE_2__SPARE_BIT_18__SHIFT
- RMI_SPARE_2__SPARE_BIT_19_MASK
- RMI_SPARE_2__SPARE_BIT_19__SHIFT
- RMI_SPARE_2__SPARE_BIT_20_MASK
- RMI_SPARE_2__SPARE_BIT_20__SHIFT
- RMI_SPARE_2__SPARE_BIT_21_MASK
- RMI_SPARE_2__SPARE_BIT_21__SHIFT
- RMI_SPARE_2__SPARE_BIT_22_MASK
- RMI_SPARE_2__SPARE_BIT_22__SHIFT
- RMI_SPARE_2__SPARE_BIT_23_MASK
- RMI_SPARE_2__SPARE_BIT_23__SHIFT
- RMI_SPARE_2__SPARE_BIT_4_0_MASK
- RMI_SPARE_2__SPARE_BIT_4_0__SHIFT
- RMI_SPARE_2__SPARE_BIT_4_1_MASK
- RMI_SPARE_2__SPARE_BIT_4_1__SHIFT
- RMI_SPARE_2__SPARE_BIT_8_2_MASK
- RMI_SPARE_2__SPARE_BIT_8_2__SHIFT
- RMI_SPARE_2__SPARE_BIT_8_3_MASK
- RMI_SPARE_2__SPARE_BIT_8_3__SHIFT
- RMI_SPARE__ARBITER_ADDRESS_MASK_MASK
- RMI_SPARE__ARBITER_ADDRESS_MASK__SHIFT
- RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS_MASK
- RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS__SHIFT
- RMI_SPARE__NOFILL_RMI_CID_CC_MASK
- RMI_SPARE__NOFILL_RMI_CID_CC__SHIFT
- RMI_SPARE__NOFILL_RMI_CID_CM_MASK
- RMI_SPARE__NOFILL_RMI_CID_CM__SHIFT
- RMI_SPARE__NOFILL_RMI_CID_DC_MASK
- RMI_SPARE__NOFILL_RMI_CID_DC__SHIFT
- RMI_SPARE__NOFILL_RMI_CID_FC_MASK
- RMI_SPARE__NOFILL_RMI_CID_FC__SHIFT
- RMI_SPARE__NOFILL_RMI_CID_S_MASK
- RMI_SPARE__NOFILL_RMI_CID_S__SHIFT
- RMI_SPARE__NOFILL_RMI_CID_TILE_MASK
- RMI_SPARE__NOFILL_RMI_CID_TILE__SHIFT
- RMI_SPARE__NOFILL_RMI_CID_Z_MASK
- RMI_SPARE__NOFILL_RMI_CID_Z__SHIFT
- RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE_MASK
- RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE__SHIFT
- RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE_MASK
- RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE__SHIFT
- RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE_MASK
- RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE__SHIFT
- RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING_MASK
- RMI_SPARE__RMI_ARBITER_STALL_TIMER_ENABLED_ALLOW_STREAMING__SHIFT
- RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS_MASK
- RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS__SHIFT
- RMI_SPARE__SPARE_BIT_15_0_MASK
- RMI_SPARE__SPARE_BIT_15_0__SHIFT
- RMI_SPARE__SPARE_BIT_16_0_MASK
- RMI_SPARE__SPARE_BIT_16_0__SHIFT
- RMI_SPARE__SPARE_BIT_1_MASK
- RMI_SPARE__SPARE_BIT_1__SHIFT
- RMI_SPARE__SPARE_BIT_2_MASK
- RMI_SPARE__SPARE_BIT_2__SHIFT
- RMI_SPARE__SPARE_BIT_3_MASK
- RMI_SPARE__SPARE_BIT_3__SHIFT
- RMI_SPARE__SPARE_BIT_4_MASK
- RMI_SPARE__SPARE_BIT_4__SHIFT
- RMI_SPARE__SPARE_BIT_5_MASK
- RMI_SPARE__SPARE_BIT_5__SHIFT
- RMI_SPARE__SPARE_BIT_6_MASK
- RMI_SPARE__SPARE_BIT_6__SHIFT
- RMI_SPARE__SPARE_BIT_7_MASK
- RMI_SPARE__SPARE_BIT_7__SHIFT
- RMI_SPARE__SPARE_BIT_8_0_MASK
- RMI_SPARE__SPARE_BIT_8_0__SHIFT
- RMI_SPI_DEFAULT_XFER_BUF_SIZE
- RMI_SPI_PAGE
- RMI_SPI_READ
- RMI_SPI_V2_READ_SPLIT
- RMI_SPI_V2_READ_UNIFIED
- RMI_SPI_V2_WRITE
- RMI_SPI_WRITE
- RMI_SPI_XFER_SIZE_LIMIT
- RMI_STARTED
- RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK
- RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT
- RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK
- RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT
- RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK
- RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT
- RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK
- RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT
- RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK
- RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT
- RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK
- RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT
- RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK
- RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT
- RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK
- RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT
- RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK
- RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT
- RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK
- RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT
- RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK
- RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT
- RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK
- RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT
- RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK
- RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT
- RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK
- RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT
- RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK
- RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT
- RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK
- RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT
- RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_MASK
- RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE_MASK
- RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA_UPDATE__SHIFT
- RMI_TCIW_FORMATTER0_CNTL__SKID_FIFO_0_FREE_SPACE_DELTA__SHIFT
- RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK
- RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT
- RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE_MASK
- RMI_TCIW_FORMATTER0_CNTL__TCIW0_REQ_SAFE_MODE__SHIFT
- RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST_MASK
- RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_AT_LAST_OF_BURST__SHIFT
- RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE_MASK
- RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_DIS_OVERRIDE__SHIFT
- RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW_MASK
- RMI_TCIW_FORMATTER0_CNTL__WR_COMBINE0_TIME_OUT_WINDOW__SHIFT
- RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK
- RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT
- RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK
- RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT
- RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_MASK
- RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE_MASK
- RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA_UPDATE__SHIFT
- RMI_TCIW_FORMATTER1_CNTL__SKID_FIFO_1_FREE_SPACE_DELTA__SHIFT
- RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK
- RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT
- RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE_MASK
- RMI_TCIW_FORMATTER1_CNTL__TCIW1_REQ_SAFE_MODE__SHIFT
- RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK
- RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT
- RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK
- RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT
- RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK
- RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT
- RMI_UTCL1_CNTL1__CLIENTID_MASK
- RMI_UTCL1_CNTL1__CLIENTID__SHIFT
- RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK
- RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT
- RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK
- RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT
- RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK
- RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT
- RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK
- RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT
- RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK
- RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT
- RMI_UTCL1_CNTL1__FORCE_MISS_MASK
- RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT
- RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK
- RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT
- RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK
- RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT
- RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK
- RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT
- RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK
- RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT
- RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK
- RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT
- RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK
- RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT
- RMI_UTCL1_CNTL1__REG_INV_VMID_MASK
- RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT
- RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK
- RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT
- RMI_UTCL1_CNTL1__RESP_MODE_MASK
- RMI_UTCL1_CNTL1__RESP_MODE__SHIFT
- RMI_UTCL1_CNTL1__USERVM_DIS_MASK
- RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT
- RMI_UTCL1_CNTL2__DIS_EDC_MASK
- RMI_UTCL1_CNTL2__DIS_EDC__SHIFT
- RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK
- RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT
- RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK
- RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT
- RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT_MASK
- RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT__SHIFT
- RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK
- RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT
- RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT_MASK
- RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT__SHIFT
- RMI_UTCL1_CNTL2__LINE_VALID_MASK
- RMI_UTCL1_CNTL2__LINE_VALID__SHIFT
- RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK
- RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT
- RMI_UTCL1_CNTL2__PERM_MODE_OVRD_MASK
- RMI_UTCL1_CNTL2__PERM_MODE_OVRD__SHIFT
- RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK
- RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT
- RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK
- RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT
- RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK
- RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT
- RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK
- RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT
- RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK
- RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT
- RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK
- RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT
- RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK
- RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT
- RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK
- RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT
- RMI_UTCL1_CNTL2__UTC_SPARE_MASK
- RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT
- RMI_UTCL1_STATUS__FAULT_DETECTED_MASK
- RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT
- RMI_UTCL1_STATUS__PRT_DETECTED_MASK
- RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT
- RMI_UTCL1_STATUS__RETRY_DETECTED_MASK
- RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT
- RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK
- RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT
- RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK
- RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT
- RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK
- RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT
- RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK
- RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT
- RMI_WRITE_REPORT_ID
- RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK
- RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT
- RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK
- RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT
- RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD_MASK
- RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_RD__SHIFT
- RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR_MASK
- RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB1_WR__SHIFT
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN_MASK
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN__SHIFT
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN_MASK
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN__SHIFT
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT
- RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT
- RMI_XBAR_CONFIG__ARBITER_DIS_MASK
- RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT
- RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK
- RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT
- RMI_XBAR_CONFIG__XBAR_EN_IN_RB1_MASK
- RMI_XBAR_CONFIG__XBAR_EN_IN_RB1__SHIFT
- RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK
- RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK
- RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT
- RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT
- RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK
- RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT
- RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK
- RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT
- RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK
- RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT
- RMI_XNACK_DEBUG__XNACK_PER_VMID_MASK
- RMI_XNACK_DEBUG__XNACK_PER_VMID__SHIFT
- RMMODE_PIPE
- RMMODE_PIPEALL
- RMMODE_PRESERVE
- RMMODE_TRASH
- RMNET_DFLT_PACKET_SIZE
- RMNET_EPMODE_BRIDGE
- RMNET_EPMODE_VND
- RMNET_FLAGS_EGRESS_MAP_CKSUMV4
- RMNET_FLAGS_INGRESS_DEAGGREGATION
- RMNET_FLAGS_INGRESS_MAP_CKSUMV4
- RMNET_FLAGS_INGRESS_MAP_COMMANDS
- RMNET_IP_VERSION_4
- RMNET_IP_VERSION_6
- RMNET_MAP_ADD_PAD_BYTES
- RMNET_MAP_COMMAND_ACK
- RMNET_MAP_COMMAND_ENUM_LENGTH
- RMNET_MAP_COMMAND_FLOW_DISABLE
- RMNET_MAP_COMMAND_FLOW_ENABLE
- RMNET_MAP_COMMAND_INVALID
- RMNET_MAP_COMMAND_NONE
- RMNET_MAP_COMMAND_REQUEST
- RMNET_MAP_COMMAND_UNKNOWN
- RMNET_MAP_COMMAND_UNSUPPORTED
- RMNET_MAP_DEAGGR_HEADROOM
- RMNET_MAP_DEAGGR_SPACING
- RMNET_MAP_GET_CD_BIT
- RMNET_MAP_GET_CMD_START
- RMNET_MAP_GET_LENGTH
- RMNET_MAP_GET_MUX_ID
- RMNET_MAP_GET_PAD
- RMNET_MAP_NO_PAD_BYTES
- RMNET_MAX_LOGICAL_EP
- RMNET_MAX_PACKET_SIZE
- RMNET_NEEDED_HEADROOM
- RMNET_TX_QUEUE_LEN
- RMODE_GUEST_OWNED_EFLAGS_BITS
- RMODE_TSS_SIZE
- RMONAR
- RMONCNT
- RMON_READ
- RMON_R_BC_PKT
- RMON_R_CRC_ALIGN
- RMON_R_FRAG
- RMON_R_JAB
- RMON_R_MC_PKT
- RMON_R_OCTETS
- RMON_R_OVERSIZE
- RMON_R_P1024TO2047
- RMON_R_P128TO255
- RMON_R_P256TO511
- RMON_R_P512TO1023
- RMON_R_P64
- RMON_R_P65TO127
- RMON_R_PACKETS
- RMON_R_P_GTE2048
- RMON_R_RESVD_O
- RMON_R_UNDERSIZE
- RMON_T_BC_PKT
- RMON_T_COL
- RMON_T_CRC_ALIGN
- RMON_T_DROP
- RMON_T_FRAG
- RMON_T_JAB
- RMON_T_MC_PKT
- RMON_T_OCTETS
- RMON_T_OVERSIZE
- RMON_T_P1024TO2047
- RMON_T_P128TO255
- RMON_T_P256TO511
- RMON_T_P512TO1023
- RMON_T_P64
- RMON_T_P65TO127
- RMON_T_PACKETS
- RMON_T_P_GTE2048
- RMON_T_UNDERSIZE
- RMON_UPDATE
- RMON_UPDATE64
- RMOUSE
- RMO_READ_BUF_MAX
- RMPP_STATE_ACTIVE
- RMPP_STATE_CANCELING
- RMPP_STATE_COMPLETE
- RMPP_STATE_TIMEOUT
- RMP_DN
- RMP_UP
- RMR
- RMR_CSRE
- RMSG_OK
- RMSG_Q_LEN
- RMSG_SZ
- RMSTPCR
- RMTPND_RES
- RMTPND_SET
- RMTPND_UNC
- RMW_BITS
- RMW_BUFFER_SIZE
- RMWcc_ARGS
- RMWcc_CONCAT
- RMX_ASPECT
- RMX_CENTER
- RMX_FULL
- RMX_HORZ_FILTER_0TAP_COEF
- RMX_HORZ_FILTER_1TAP_COEF
- RMX_HORZ_FILTER_2TAP_COEF
- RMX_HORZ_PHASE
- RMX_OFF
- RM_ADCSR_ABCM
- RM_ADCSR_ABM
- RM_ADCSR_ABR
- RM_ADCVOLL
- RM_ADCVOLR
- RM_ADD_BANK
- RM_AIC1_BCLKINV
- RM_AIC1_FORMAT
- RM_AIC1_LRP
- RM_AIC1_MS
- RM_AIC1_WL
- RM_AIC2_ADCDSEL
- RM_AIC2_BLRCM
- RM_AIC2_DACDSEL
- RM_AIC2_TRI
- RM_BANK_WAIT
- RM_BITS
- RM_BL_WRT_CMD_SIZE
- RM_BL_WRT_LEN
- RM_BL_WRT_PKG_SIZE
- RM_BOOT_BLDR
- RM_BOOT_DELAY_MS
- RM_BOOT_MAIN
- RM_BOOT_RDY
- RM_CATKTCH
- RM_CATKTCL
- RM_CLECTL_COMP_EN
- RM_CLECTL_EXP_EN
- RM_CLECTL_LIMIT_EN
- RM_CLECTL_LVL_MODE
- RM_CLECTL_WINDOWSEL
- RM_CMD_BANK_SWITCH
- RM_CMD_BOOT_ACK
- RM_CMD_BOOT_CHK
- RM_CMD_BOOT_PAGE_WRT
- RM_CMD_BOOT_READ
- RM_CMD_BOOT_WRT
- RM_CMD_DATA_BANK
- RM_CMD_ENTER_SLEEP
- RM_CMD_QUERY_BANK
- RM_CMPRAT
- RM_CNVRTR0_ADCHPDL
- RM_CNVRTR0_ADCHPDR
- RM_CNVRTR0_ADCMU
- RM_CNVRTR0_ADCPOLL
- RM_CNVRTR0_ADCPOLR
- RM_CNVRTR0_AMONOMIX
- RM_CNVRTR0_HPOR
- RM_CNVRTR1_DACDITH
- RM_CNVRTR1_DACMU
- RM_CNVRTR1_DACPOLL
- RM_CNVRTR1_DACPOLR
- RM_CNVRTR1_DEEMPH
- RM_CNVRTR1_DMONOMIX
- RM_COMPTH
- RM_CONFIG0_ASDM
- RM_CONFIG0_DC_BYPASS
- RM_CONFIG0_DSDM
- RM_CONFIG0_SD_FORCE_ON
- RM_CONFIG1_EQ1_BE
- RM_CONFIG1_EQ1_EN
- RM_CONFIG1_EQ2_BE
- RM_CONFIG1_EQ2_EN
- RM_CONTACT_PRESSURE_POS
- RM_CONTACT_STATE_POS
- RM_CONTACT_WIDTH_X_POS
- RM_CONTACT_WIDTH_Y_POS
- RM_CONTACT_X_POS
- RM_CONTACT_Y_POS
- RM_CRELTCH
- RM_CRELTCL
- RM_DACCRADDR_DACCRADD
- RM_DACCRRDH
- RM_DACCRRDL
- RM_DACCRRDM
- RM_DACCRSTAT_DACCR_BUSY
- RM_DACCRWRH_DACCRWDH
- RM_DACCRWRL_DACCRWDL
- RM_DACCRWRM_DACCRWDM
- RM_DACMBCATK1H_TCATKH
- RM_DACMBCATK1L_TCATKL
- RM_DACMBCATK2H_TCATKH
- RM_DACMBCATK2L_TCATKL
- RM_DACMBCATK3H_TCATKH
- RM_DACMBCATK3L_TCATKL
- RM_DACMBCCTL_LVLMODE1
- RM_DACMBCCTL_LVLMODE2
- RM_DACMBCCTL_LVLMODE3
- RM_DACMBCCTL_WINSEL1
- RM_DACMBCCTL_WINSEL2
- RM_DACMBCCTL_WINSEL3
- RM_DACMBCEN_MBCEN1
- RM_DACMBCEN_MBCEN2
- RM_DACMBCEN_MBCEN3
- RM_DACMBCMUG1_MUGAIN
- RM_DACMBCMUG1_PHASE
- RM_DACMBCMUG2_MUGAIN
- RM_DACMBCMUG2_PHASE
- RM_DACMBCMUG3_MUGAIN
- RM_DACMBCMUG3_PHASE
- RM_DACMBCRAT1_RATIO
- RM_DACMBCRAT2_RATIO
- RM_DACMBCRAT3_RATIO
- RM_DACMBCREL1H_TCRELH
- RM_DACMBCREL1L_TCRELL
- RM_DACMBCREL2H_TCRELH
- RM_DACMBCREL2L_TCRELL
- RM_DACMBCREL3H_TCRELH
- RM_DACMBCREL3L_TCRELL
- RM_DACMBCTHR1_THRESH
- RM_DACMBCTHR2_THRESH
- RM_DACMBCTHR3_THRESH
- RM_DACSR_DBCM
- RM_DACSR_DBM
- RM_DACSR_DBR
- RM_DACVOLL
- RM_DACVOLR
- RM_DCOFSEL_DC_COEF_SEL
- RM_DESL2
- RM_DEVIDH_DIDH
- RM_DEVIDL_DIDL
- RM_DMICCTL_DMICEN
- RM_DMICCTL_DMONO
- RM_DMICCTL_DMPHADJ
- RM_DMICCTL_DMRATE
- RM_DUP_ADDR
- RM_ENABLE_FLAG
- RM_EXPRAT
- RM_EXPTH
- RM_FW_PAGE_SIZE
- RM_FXCTL_3DEN
- RM_FXCTL_BEEN
- RM_FXCTL_BNLFBYPASS
- RM_FXCTL_TEEN
- RM_FXCTL_TNLFBYPASS
- RM_HPVOLL
- RM_HPVOLR
- RM_INMODE_DS
- RM_INSELL
- RM_INSELL_MICBSTL
- RM_INSELR
- RM_INSELR_MICBSTR
- RM_INVOLL
- RM_INVOLL_INMUTEL
- RM_INVOLL_IZCL
- RM_INVOLR
- RM_INVOLR_INMUTER
- RM_INVOLR_IZCR
- RM_JOIN
- RM_LATKTCH
- RM_LATKTCL
- RM_LIMTGT
- RM_LIMTH
- RM_LOOP
- RM_LRELTCH
- RM_LRELTCL
- RM_MAX_FW_RETRIES
- RM_MAX_FW_SIZE
- RM_MAX_READ_SIZE
- RM_MAX_RETRIES
- RM_MAX_TOUCH_NUM
- RM_MUGAIN_CLEMUG
- RM_MY_BEACON
- RM_MY_CLAIM
- RM_OTHER_BEACON
- RM_PACKET_CRC_SIZE
- RM_PAR_CHECK
- RM_PLLCTL0_PLL1_LOCK
- RM_PLLCTL0_PLL2_LOCK
- RM_PLLCTL10_FBDIV_PLL2L
- RM_PLLCTL11_FBDIV_PLL2H
- RM_PLLCTL12_CP_PLL2
- RM_PLLCTL12_RZ_PLL2
- RM_PLLCTL1B_VCOI_PLL1
- RM_PLLCTL1B_VCOI_PLL2
- RM_PLLCTL1C_PDB_PLL1
- RM_PLLCTL1C_PDB_PLL2
- RM_PLLCTL9_REFDIV_PLL1
- RM_PLLCTLA_OUTDIV_PLL1
- RM_PLLCTLB_FBDIV_PLL1L
- RM_PLLCTLC_FBDIV_PLL1H
- RM_PLLCTLD_CP_PLL1
- RM_PLLCTLD_RZ_PLL1
- RM_PLLCTLE_REFDIV_PLL2
- RM_PLLCTLF_OUTDIV_PLL2
- RM_PLLREFSEL_PLL1_REF_SEL
- RM_PLLREFSEL_PLL2_REF_SEL
- RM_POWERON_DELAY_USEC
- RM_PWRM1_ADCL
- RM_PWRM1_ADCR
- RM_PWRM1_BSTL
- RM_PWRM1_BSTR
- RM_PWRM1_DIGENB
- RM_PWRM1_MICB
- RM_PWRM1_PGAL
- RM_PWRM1_PGAR
- RM_PWRM2_D2S
- RM_PWRM2_HPL
- RM_PWRM2_HPR
- RM_PWRM2_INSELL
- RM_PWRM2_INSELR
- RM_PWRM2_SPKL
- RM_PWRM2_SPKR
- RM_PWRM2_VREF
- RM_RESET
- RM_RESET_DELAY_MSEC
- RM_RESET_MSG_ADDR
- RM_RING_NON_OP
- RM_RING_OP
- RM_RW_WAIT
- RM_SPKVOLL
- RM_SPKVOLR
- RM_SRAM_TYPE
- RM_STATUS_CODE_AE_TIMEOUT
- RM_STATUS_CODE_GOOD
- RM_STATUS_CODE_MASK
- RM_STATUS_CODE_SHIFT
- RM_TIMEBASE_DIVIDER
- RM_TIMEOUT
- RM_TIMEOUT_ANNOUNCE
- RM_TIMEOUT_D_MAX
- RM_TIMEOUT_NON_OP
- RM_TIMEOUT_POLL
- RM_TIMEOUT_T_DIRECT
- RM_TIMEOUT_T_STUCK
- RM_TRT_EXP
- RM_TX_STATE_CHANGE
- RM_TYPE
- RM_TYPE_4_0
- RM_VALID_CLAIM
- RM_XATKTCH
- RM_XATKTCL
- RM_XRELTCH
- RM_XRELTCL
- RN5T567
- RN5T618
- RN5T618_ADCCNT1
- RN5T618_ADCCNT2
- RN5T618_ADCCNT3
- RN5T618_AGE
- RN5T618_AIN0DATAH
- RN5T618_AIN0DATAL
- RN5T618_AIN0THH
- RN5T618_AIN0THL
- RN5T618_AIN1DATAH
- RN5T618_AIN1DATAL
- RN5T618_AIN1THH
- RN5T618_AIN1THL
- RN5T618_BATDAC
- RN5T618_BATSET1
- RN5T618_BATSET2
- RN5T618_CC_AVEREG0
- RN5T618_CC_AVEREG1
- RN5T618_CC_COUNT0
- RN5T618_CC_COUNT1
- RN5T618_CC_COUNT2
- RN5T618_CC_CTRL
- RN5T618_CC_GAINREG0
- RN5T618_CC_GAINREG1
- RN5T618_CC_OFFREG0
- RN5T618_CC_OFFREG1
- RN5T618_CC_SUMREG0
- RN5T618_CC_SUMREG1
- RN5T618_CC_SUMREG2
- RN5T618_CC_SUMREG3
- RN5T618_CHGCTL1
- RN5T618_CHGCTL2
- RN5T618_CHGCTRL_DETMOD1
- RN5T618_CHGCTRL_DETMOD2
- RN5T618_CHGCTRL_IRFMASK
- RN5T618_CHGCTRL_IRR
- RN5T618_CHGCTRL_MONI
- RN5T618_CHGERR_DETMOD1
- RN5T618_CHGERR_DETMOD2
- RN5T618_CHGERR_IRFMASK
- RN5T618_CHGERR_IRR
- RN5T618_CHGERR_MONI
- RN5T618_CHGISET
- RN5T618_CHGOSCCTL
- RN5T618_CHGOSCFREQSET1
- RN5T618_CHGOSCFREQSET2
- RN5T618_CHGOSCSCORESET1
- RN5T618_CHGOSCSCORESET2
- RN5T618_CHGOSCSCORESET3
- RN5T618_CHGSTATE
- RN5T618_CHGSTAT_DETMOD1
- RN5T618_CHGSTAT_DETMOD2
- RN5T618_CHGSTAT_DETMOD3
- RN5T618_CHGSTAT_IRFMASK1
- RN5T618_CHGSTAT_IRFMASK2
- RN5T618_CHGSTAT_IRR1
- RN5T618_CHGSTAT_IRR2
- RN5T618_CHGSTAT_MONI1
- RN5T618_CHGSTAT_MONI2
- RN5T618_CONTROL
- RN5T618_CPUCNT
- RN5T618_DC1CTL
- RN5T618_DC1CTL2
- RN5T618_DC1DAC
- RN5T618_DC1DAC_SLP
- RN5T618_DC1_SLOT
- RN5T618_DC2CTL
- RN5T618_DC2CTL2
- RN5T618_DC2DAC
- RN5T618_DC2DAC_SLP
- RN5T618_DC2_SLOT
- RN5T618_DC3CTL
- RN5T618_DC3CTL2
- RN5T618_DC3DAC
- RN5T618_DC3DAC_SLP
- RN5T618_DC3_SLOT
- RN5T618_DC4CTL
- RN5T618_DC4CTL2
- RN5T618_DC4DAC
- RN5T618_DC4DAC_SLP
- RN5T618_DC4_SLOT
- RN5T618_DC5CTL
- RN5T618_DC5CTL2
- RN5T618_DC5DAC
- RN5T618_DCDC1
- RN5T618_DCDC2
- RN5T618_DCDC3
- RN5T618_DCDC4
- RN5T618_DCDC5
- RN5T618_DCIREN
- RN5T618_DCIRMON
- RN5T618_DCIRQ
- RN5T618_DIESET
- RN5T618_EN_ADCIR1
- RN5T618_EN_ADCIR2
- RN5T618_EN_ADCIR3
- RN5T618_EN_GPIR
- RN5T618_FA_CAP_H
- RN5T618_FA_CAP_L
- RN5T618_GPEDGE1
- RN5T618_GPEDGE2
- RN5T618_GPLED_FUNC
- RN5T618_ILIMDATAH
- RN5T618_ILIMDATAL
- RN5T618_ILIMTHH
- RN5T618_ILIMTHL
- RN5T618_INTEN
- RN5T618_INTMON
- RN5T618_INTPOL
- RN5T618_IODAC
- RN5T618_IOOUT
- RN5T618_IOSEL
- RN5T618_IR_ADC1
- RN5T618_IR_ADC2
- RN5T618_IR_ADC3
- RN5T618_IR_GPF
- RN5T618_IR_GPR
- RN5T618_LDO1
- RN5T618_LDO10
- RN5T618_LDO10DAC
- RN5T618_LDO1DAC
- RN5T618_LDO1DAC_SLP
- RN5T618_LDO1_SLOT
- RN5T618_LDO2
- RN5T618_LDO2DAC
- RN5T618_LDO2DAC_SLP
- RN5T618_LDO2_SLOT
- RN5T618_LDO3
- RN5T618_LDO3DAC
- RN5T618_LDO3DAC_SLP
- RN5T618_LDO3_SLOT
- RN5T618_LDO4
- RN5T618_LDO4DAC
- RN5T618_LDO4DAC_SLP
- RN5T618_LDO4_SLOT
- RN5T618_LDO5
- RN5T618_LDO5DAC
- RN5T618_LDO5DAC_SLP
- RN5T618_LDO5_SLOT
- RN5T618_LDO6
- RN5T618_LDO6DAC
- RN5T618_LDO7
- RN5T618_LDO7DAC
- RN5T618_LDO8
- RN5T618_LDO8DAC
- RN5T618_LDO9
- RN5T618_LDO9DAC
- RN5T618_LDODIS
- RN5T618_LDOEN1
- RN5T618_LDOEN2
- RN5T618_LDORTC1
- RN5T618_LDORTC1_SLOT
- RN5T618_LDORTC2
- RN5T618_LDORTC2DAC
- RN5T618_LDORTCDAC
- RN5T618_LSIVER
- RN5T618_MAX_REG
- RN5T618_MON_IOIN
- RN5T618_NOETIMSETCNT
- RN5T618_OTPVER
- RN5T618_OUT32KEN
- RN5T618_POFFHIS
- RN5T618_PONHIS
- RN5T618_PREVINDAC
- RN5T618_PSO0_SLOT
- RN5T618_PSO1_SLOT
- RN5T618_PSO2_SLOT
- RN5T618_PSO3_SLOT
- RN5T618_PSWR
- RN5T618_PWRFUNC
- RN5T618_PWRIREN
- RN5T618_PWRIRQ
- RN5T618_PWRIRQ_IR_WDOG
- RN5T618_PWRIRSEL
- RN5T618_PWRMON
- RN5T618_PWRONTIMSET
- RN5T618_REGISET1
- RN5T618_REGISET2
- RN5T618_REG_NUM
- RN5T618_REPCNT
- RN5T618_REPCNT_REPWRON
- RN5T618_RE_CAP_H
- RN5T618_RE_CAP_L
- RN5T618_SLPCNT
- RN5T618_SLPCNT_SWPWROFF
- RN5T618_SOC
- RN5T618_TEMP_0
- RN5T618_TEMP_1
- RN5T618_TIMSET
- RN5T618_TT_EMPTY_H
- RN5T618_TT_EMPTY_L
- RN5T618_TT_FULL_H
- RN5T618_TT_FULL_L
- RN5T618_VADPDATAH
- RN5T618_VADPDATAL
- RN5T618_VADPTHH
- RN5T618_VADPTHL
- RN5T618_VBATDATAH
- RN5T618_VBATDATAL
- RN5T618_VBATTHH
- RN5T618_VBATTHL
- RN5T618_VINDAC
- RN5T618_VOLTAGE_0
- RN5T618_VOLTAGE_1
- RN5T618_VSYSDATAH
- RN5T618_VSYSDATAL
- RN5T618_VSYSSET
- RN5T618_VSYSTHH
- RN5T618_VSYSTHL
- RN5T618_VTHMDATAH
- RN5T618_VTHMDATAL
- RN5T618_VTHMTHH
- RN5T618_VTHMTHL
- RN5T618_VUSBDATAH
- RN5T618_VUSBDATAL
- RN5T618_VUSBTHH
- RN5T618_VUSBTHL
- RN5T618_WATCHDOG
- RN5T618_WATCHDOGCNT
- RN5T618_WATCHDOG_WDOGEN
- RN5T618_WATCHDOG_WDOGTIM_M
- RN5T618_WATCHDOG_WDOGTIM_S
- RNAT_OFF
- RNBLKS
- RNC_DEST_FINAL
- RNC_DEST_READY
- RNC_DEST_SUSPENDED
- RNC_DEST_SUSPENDED_RESUME
- RNC_DEST_UNSPECIFIED
- RNC_STATES
- RND
- RND4
- RNDADDENTROPY
- RNDADDTOENTCNT
- RNDCLEARPOOL
- RNDGETENTCNT
- RNDGETPOOL
- RNDIS_802_3_MAC_OPTION_PRIORITY
- RNDIS_AND_PPI_SIZE
- RNDIS_BCM4320A
- RNDIS_BCM4320B
- RNDIS_CONFIG_PARAM_TYPE_INTEGER
- RNDIS_CONFIG_PARAM_TYPE_STRING
- RNDIS_CONTROL_TIMEOUT_MS
- RNDIS_DATA_INITIALIZED
- RNDIS_DEFAULT_FILTER
- RNDIS_DEVICE_WAKE_ON_MAGIC_PACKET_ENABLE
- RNDIS_DEVICE_WAKE_ON_PATTERN_MATCH_ENABLE
- RNDIS_DEVICE_WAKE_UP_ENABLE
- RNDIS_DEV_DATAINITIALIZED
- RNDIS_DEV_INITIALIZED
- RNDIS_DEV_INITIALIZING
- RNDIS_DEV_UNINITIALIZED
- RNDIS_DF_CONNECTIONLESS
- RNDIS_DF_CONNECTION_ORIENTED
- RNDIS_DF_RAW_DATA
- RNDIS_DRIVER_DATA_POLL_STATUS
- RNDIS_EXT_LEN
- RNDIS_HEADER_SIZE
- RNDIS_INITIALIZED
- RNDIS_MAC_OPTION_8021P_PRIORITY
- RNDIS_MAC_OPTION_COPY_LOOKAHEAD_DATA
- RNDIS_MAC_OPTION_EOTX_INDICATION
- RNDIS_MAC_OPTION_FULL_DUPLEX
- RNDIS_MAC_OPTION_NO_LOOPBACK
- RNDIS_MAC_OPTION_RECEIVE_SERIALIZED
- RNDIS_MAC_OPTION_RESERVED
- RNDIS_MAC_OPTION_TRANSFERS_NOT_PEND
- RNDIS_MAJOR_VERSION
- RNDIS_MASTER_INTERFACE
- RNDIS_MAXIMUM_FRAME_SIZE
- RNDIS_MAX_PKT_DEFAULT
- RNDIS_MAX_TOTAL_SIZE
- RNDIS_MEDIA_STATE_CONNECTED
- RNDIS_MEDIA_STATE_DISCONNECTED
- RNDIS_MEDIUM_1394
- RNDIS_MEDIUM_802_3
- RNDIS_MEDIUM_802_5
- RNDIS_MEDIUM_ARCNET_878_2
- RNDIS_MEDIUM_ARCNET_RAW
- RNDIS_MEDIUM_ATM
- RNDIS_MEDIUM_BPC
- RNDIS_MEDIUM_CO_WAN
- RNDIS_MEDIUM_FDDI
- RNDIS_MEDIUM_IRDA
- RNDIS_MEDIUM_LOCAL_TALK
- RNDIS_MEDIUM_MAX
- RNDIS_MEDIUM_UNSPECIFIED
- RNDIS_MEDIUM_WAN
- RNDIS_MEDIUM_WIRELESS_LAN
- RNDIS_MESSAGE_SIZE
- RNDIS_MINIPORT_64BITS_DMA
- RNDIS_MINIPORT_BUS_MASTER
- RNDIS_MINIPORT_DESERIALIZE
- RNDIS_MINIPORT_HARDWARE_DEVICE
- RNDIS_MINIPORT_HIDDEN
- RNDIS_MINIPORT_IGNORE_PACKET_QUEUE
- RNDIS_MINIPORT_IGNORE_REQUEST_QUEUE
- RNDIS_MINIPORT_IGNORE_TOKEN_RING_ERRORS
- RNDIS_MINIPORT_INDICATES_PACKETS
- RNDIS_MINIPORT_INTERMEDIATE_DRIVER
- RNDIS_MINIPORT_IS_CO
- RNDIS_MINIPORT_IS_NDIS_5
- RNDIS_MINIPORT_NETBOOT_CARD
- RNDIS_MINIPORT_NO_HALT_ON_SUSPEND
- RNDIS_MINIPORT_PM_SUPPORTED
- RNDIS_MINIPORT_REQUIRES_MEDIA_POLLING
- RNDIS_MINIPORT_SG_LIST
- RNDIS_MINIPORT_SUPPORTS_CANCEL_SEND_PACKETS
- RNDIS_MINIPORT_SUPPORTS_MAC_ADDRESS_OVERWRITE
- RNDIS_MINIPORT_SUPPORTS_MEDIA_QUERY
- RNDIS_MINIPORT_SUPPORTS_MEDIA_SENSE
- RNDIS_MINIPORT_SURPRISE_REMOVE_OK
- RNDIS_MINIPORT_SWENUM
- RNDIS_MINIPORT_USES_SAFE_BUFFER_APIS
- RNDIS_MINIPORT_WDM_DRIVER
- RNDIS_MINOR_VERSION
- RNDIS_MSG_BUS
- RNDIS_MSG_COMPLETION
- RNDIS_MSG_HALT
- RNDIS_MSG_INDICATE
- RNDIS_MSG_INIT
- RNDIS_MSG_INIT_C
- RNDIS_MSG_KEEPALIVE
- RNDIS_MSG_KEEPALIVE_C
- RNDIS_MSG_PACKET
- RNDIS_MSG_QUERY
- RNDIS_MSG_QUERY_C
- RNDIS_MSG_RESET
- RNDIS_MSG_RESET_C
- RNDIS_MSG_SET
- RNDIS_MSG_SET_C
- RNDIS_OID_802_11_ADD_KEY
- RNDIS_OID_802_11_ADD_WEP
- RNDIS_OID_802_11_ASSOCIATION_INFORMATION
- RNDIS_OID_802_11_AUTHENTICATION_MODE
- RNDIS_OID_802_11_BSSID
- RNDIS_OID_802_11_BSSID_LIST
- RNDIS_OID_802_11_BSSID_LIST_SCAN
- RNDIS_OID_802_11_CAPABILITY
- RNDIS_OID_802_11_CONFIGURATION
- RNDIS_OID_802_11_DISASSOCIATE
- RNDIS_OID_802_11_ENCRYPTION_STATUS
- RNDIS_OID_802_11_FRAGMENTATION_THRESHOLD
- RNDIS_OID_802_11_INFRASTRUCTURE_MODE
- RNDIS_OID_802_11_NETWORK_TYPES_SUPPORTED
- RNDIS_OID_802_11_NETWORK_TYPE_IN_USE
- RNDIS_OID_802_11_PMKID
- RNDIS_OID_802_11_POWER_MODE
- RNDIS_OID_802_11_PRIVACY_FILTER
- RNDIS_OID_802_11_REMOVE_KEY
- RNDIS_OID_802_11_REMOVE_WEP
- RNDIS_OID_802_11_RSSI
- RNDIS_OID_802_11_RSSI_TRIGGER
- RNDIS_OID_802_11_RTS_THRESHOLD
- RNDIS_OID_802_11_SSID
- RNDIS_OID_802_11_SUPPORTED_RATES
- RNDIS_OID_802_11_TX_POWER_LEVEL
- RNDIS_OID_802_3_CURRENT_ADDRESS
- RNDIS_OID_802_3_MAC_OPTIONS
- RNDIS_OID_802_3_MAXIMUM_LIST_SIZE
- RNDIS_OID_802_3_MULTICAST_LIST
- RNDIS_OID_802_3_PERMANENT_ADDRESS
- RNDIS_OID_802_3_RCV_ERROR_ALIGNMENT
- RNDIS_OID_802_3_RCV_OVERRUN
- RNDIS_OID_802_3_XMIT_DEFERRED
- RNDIS_OID_802_3_XMIT_HEARTBEAT_FAILURE
- RNDIS_OID_802_3_XMIT_LATE_COLLISIONS
- RNDIS_OID_802_3_XMIT_MAX_COLLISIONS
- RNDIS_OID_802_3_XMIT_MORE_COLLISIONS
- RNDIS_OID_802_3_XMIT_ONE_COLLISION
- RNDIS_OID_802_3_XMIT_TIMES_CRS_LOST
- RNDIS_OID_802_3_XMIT_UNDERRUN
- RNDIS_OID_CO_ADDRESS_CHANGE
- RNDIS_OID_CO_ADD_ADDRESS
- RNDIS_OID_CO_ADD_PVC
- RNDIS_OID_CO_DELETE_ADDRESS
- RNDIS_OID_CO_DELETE_PVC
- RNDIS_OID_CO_GET_ADDRESSES
- RNDIS_OID_CO_GET_CALL_INFORMATION
- RNDIS_OID_CO_SIGNALING_DISABLED
- RNDIS_OID_CO_SIGNALING_ENABLED
- RNDIS_OID_GEN_BROADCAST_BYTES_RCV
- RNDIS_OID_GEN_BROADCAST_BYTES_XMIT
- RNDIS_OID_GEN_BROADCAST_FRAMES_RCV
- RNDIS_OID_GEN_BROADCAST_FRAMES_XMIT
- RNDIS_OID_GEN_CO_BYTES_RCV
- RNDIS_OID_GEN_CO_BYTES_XMIT
- RNDIS_OID_GEN_CO_BYTES_XMIT_OUTSTANDING
- RNDIS_OID_GEN_CO_DRIVER_VERSION
- RNDIS_OID_GEN_CO_GET_NETCARD_TIME
- RNDIS_OID_GEN_CO_GET_TIME_CAPS
- RNDIS_OID_GEN_CO_HARDWARE_STATUS
- RNDIS_OID_GEN_CO_LINK_SPEED
- RNDIS_OID_GEN_CO_MAC_OPTIONS
- RNDIS_OID_GEN_CO_MEDIA_CONNECT_STATUS
- RNDIS_OID_GEN_CO_MEDIA_IN_USE
- RNDIS_OID_GEN_CO_MEDIA_SUPPORTED
- RNDIS_OID_GEN_CO_MINIMUM_LINK_SPEED
- RNDIS_OID_GEN_CO_NETCARD_LOAD
- RNDIS_OID_GEN_CO_PROTOCOL_OPTIONS
- RNDIS_OID_GEN_CO_RCV_CRC_ERROR
- RNDIS_OID_GEN_CO_RCV_PDUS_ERROR
- RNDIS_OID_GEN_CO_RCV_PDUS_NO_BUFFER
- RNDIS_OID_GEN_CO_RCV_PDUS_OK
- RNDIS_OID_GEN_CO_SUPPORTED_LIST
- RNDIS_OID_GEN_CO_TRANSMIT_QUEUE_LENGTH
- RNDIS_OID_GEN_CO_VENDOR_DESCRIPTION
- RNDIS_OID_GEN_CO_VENDOR_DRIVER_VERSION
- RNDIS_OID_GEN_CO_VENDOR_ID
- RNDIS_OID_GEN_CO_XMIT_PDUS_ERROR
- RNDIS_OID_GEN_CO_XMIT_PDUS_OK
- RNDIS_OID_GEN_CURRENT_LOOKAHEAD
- RNDIS_OID_GEN_CURRENT_PACKET_FILTER
- RNDIS_OID_GEN_DEVICE_PROFILE
- RNDIS_OID_GEN_DIRECTED_BYTES_RCV
- RNDIS_OID_GEN_DIRECTED_BYTES_XMIT
- RNDIS_OID_GEN_DIRECTED_FRAMES_RCV
- RNDIS_OID_GEN_DIRECTED_FRAMES_XMIT
- RNDIS_OID_GEN_DRIVER_VERSION
- RNDIS_OID_GEN_FRIENDLY_NAME
- RNDIS_OID_GEN_GET_NETCARD_TIME
- RNDIS_OID_GEN_GET_TIME_CAPS
- RNDIS_OID_GEN_HARDWARE_STATUS
- RNDIS_OID_GEN_INIT_TIME_MS
- RNDIS_OID_GEN_LINK_SPEED
- RNDIS_OID_GEN_MACHINE_NAME
- RNDIS_OID_GEN_MAC_OPTIONS
- RNDIS_OID_GEN_MAXIMUM_FRAME_SIZE
- RNDIS_OID_GEN_MAXIMUM_LOOKAHEAD
- RNDIS_OID_GEN_MAXIMUM_SEND_PACKETS
- RNDIS_OID_GEN_MAXIMUM_TOTAL_SIZE
- RNDIS_OID_GEN_MEDIA_CAPABILITIES
- RNDIS_OID_GEN_MEDIA_CONNECT_STATUS
- RNDIS_OID_GEN_MEDIA_IN_USE
- RNDIS_OID_GEN_MEDIA_SENSE_COUNTS
- RNDIS_OID_GEN_MEDIA_SUPPORTED
- RNDIS_OID_GEN_MINIPORT_INFO
- RNDIS_OID_GEN_MULTICAST_BYTES_RCV
- RNDIS_OID_GEN_MULTICAST_BYTES_XMIT
- RNDIS_OID_GEN_MULTICAST_FRAMES_RCV
- RNDIS_OID_GEN_MULTICAST_FRAMES_XMIT
- RNDIS_OID_GEN_NETCARD_LOAD
- RNDIS_OID_GEN_NETWORK_LAYER_ADDRESSES
- RNDIS_OID_GEN_PHYSICAL_MEDIUM
- RNDIS_OID_GEN_PROTOCOL_OPTIONS
- RNDIS_OID_GEN_RCV_CRC_ERROR
- RNDIS_OID_GEN_RCV_ERROR
- RNDIS_OID_GEN_RCV_NO_BUFFER
- RNDIS_OID_GEN_RCV_OK
- RNDIS_OID_GEN_RECEIVE_BLOCK_SIZE
- RNDIS_OID_GEN_RECEIVE_BUFFER_SPACE
- RNDIS_OID_GEN_RESET_COUNTS
- RNDIS_OID_GEN_RESET_VERIFY_PARAMETERS
- RNDIS_OID_GEN_RNDIS_CONFIG_PARAMETER
- RNDIS_OID_GEN_SUPPORTED_GUIDS
- RNDIS_OID_GEN_SUPPORTED_LIST
- RNDIS_OID_GEN_TRANSMIT_BLOCK_SIZE
- RNDIS_OID_GEN_TRANSMIT_BUFFER_SPACE
- RNDIS_OID_GEN_TRANSMIT_QUEUE_LENGTH
- RNDIS_OID_GEN_TRANSPORT_HEADER_OFFSET
- RNDIS_OID_GEN_VENDOR_DESCRIPTION
- RNDIS_OID_GEN_VENDOR_DRIVER_VERSION
- RNDIS_OID_GEN_VENDOR_ID
- RNDIS_OID_GEN_VLAN_ID
- RNDIS_OID_GEN_XMIT_ERROR
- RNDIS_OID_GEN_XMIT_OK
- RNDIS_OID_PNP_ADD_WAKE_UP_PATTERN
- RNDIS_OID_PNP_CAPABILITIES
- RNDIS_OID_PNP_ENABLE_WAKE_UP
- RNDIS_OID_PNP_QUERY_POWER
- RNDIS_OID_PNP_REMOVE_WAKE_UP_PATTERN
- RNDIS_OID_PNP_SET_POWER
- RNDIS_PACKET_TYPE_ALL_FUNCTIONAL
- RNDIS_PACKET_TYPE_ALL_LOCAL
- RNDIS_PACKET_TYPE_ALL_MULTICAST
- RNDIS_PACKET_TYPE_BROADCAST
- RNDIS_PACKET_TYPE_DIRECTED
- RNDIS_PACKET_TYPE_FUNCTIONAL
- RNDIS_PACKET_TYPE_GROUP
- RNDIS_PACKET_TYPE_MAC_FRAME
- RNDIS_PACKET_TYPE_MULTICAST
- RNDIS_PACKET_TYPE_PROMISCUOUS
- RNDIS_PACKET_TYPE_SMT
- RNDIS_PACKET_TYPE_SOURCE_ROUTING
- RNDIS_PHYSICAL_MEDIUM_1394
- RNDIS_PHYSICAL_MEDIUM_CABLE_MODEM
- RNDIS_PHYSICAL_MEDIUM_DSL
- RNDIS_PHYSICAL_MEDIUM_FIBRE_CHANNEL
- RNDIS_PHYSICAL_MEDIUM_MAX
- RNDIS_PHYSICAL_MEDIUM_PHONE_LINE
- RNDIS_PHYSICAL_MEDIUM_POWER_LINE
- RNDIS_PHYSICAL_MEDIUM_UNSPECIFIED
- RNDIS_PHYSICAL_MEDIUM_WIRELESS_LAN
- RNDIS_PHYSICAL_MEDIUM_WIRELESS_WAN
- RNDIS_PKTINFO_1ST_FRAG
- RNDIS_PKTINFO_ID
- RNDIS_PKTINFO_ID_V1
- RNDIS_PKTINFO_LAST_FRAG
- RNDIS_PKTINFO_MAX
- RNDIS_PKTINFO_SUBALLOC
- RNDIS_PKT_ALIGN_DEFAULT
- RNDIS_PRODUCT_NUM
- RNDIS_REG
- RNDIS_STATUS_AAL_PARAMS_UNSUPPORTED
- RNDIS_STATUS_ADAPTER_NOT_FOUND
- RNDIS_STATUS_ADAPTER_NOT_OPEN
- RNDIS_STATUS_ADAPTER_NOT_READY
- RNDIS_STATUS_ADAPTER_REMOVED
- RNDIS_STATUS_ALREADY_MAPPED
- RNDIS_STATUS_BAD_CHARACTERISTICS
- RNDIS_STATUS_BAD_VERSION
- RNDIS_STATUS_BUFFER_OVERFLOW
- RNDIS_STATUS_BUFFER_TOO_SHORT
- RNDIS_STATUS_CALL_ACTIVE
- RNDIS_STATUS_CELLRATE_NOT_AVAILABLE
- RNDIS_STATUS_CLOSED
- RNDIS_STATUS_CLOSING
- RNDIS_STATUS_CLOSING_INDICATING
- RNDIS_STATUS_DEST_OUT_OF_ORDER
- RNDIS_STATUS_DEVICE_FAILED
- RNDIS_STATUS_ERROR_READING_FILE
- RNDIS_STATUS_FAILURE
- RNDIS_STATUS_FILE_NOT_FOUND
- RNDIS_STATUS_GROUP_ADDRESS_IN_USE
- RNDIS_STATUS_HARDWARE_LINE_DOWN
- RNDIS_STATUS_HARDWARE_LINE_UP
- RNDIS_STATUS_HARD_ERRORS
- RNDIS_STATUS_INCOMPATABLE_QOS
- RNDIS_STATUS_INTERFACE_DOWN
- RNDIS_STATUS_INTERFACE_UP
- RNDIS_STATUS_INTERVAL_MS
- RNDIS_STATUS_INVALID_ADDRESS
- RNDIS_STATUS_INVALID_DATA
- RNDIS_STATUS_INVALID_LENGTH
- RNDIS_STATUS_INVALID_OID
- RNDIS_STATUS_INVALID_PACKET
- RNDIS_STATUS_INVALID_SAP
- RNDIS_STATUS_LINK_SPEED_CHANGE
- RNDIS_STATUS_MEDIA_BUSY
- RNDIS_STATUS_MEDIA_CONNECT
- RNDIS_STATUS_MEDIA_DISCONNECT
- RNDIS_STATUS_MEDIA_SPECIFIC_INDICATION
- RNDIS_STATUS_MULTICAST_EXISTS
- RNDIS_STATUS_MULTICAST_FULL
- RNDIS_STATUS_MULTICAST_NOT_FOUND
- RNDIS_STATUS_NETWORK_CHANGE
- RNDIS_STATUS_NOT_ACCEPTED
- RNDIS_STATUS_NOT_COPIED
- RNDIS_STATUS_NOT_INDICATING
- RNDIS_STATUS_NOT_RECOGNIZED
- RNDIS_STATUS_NOT_RESETTABLE
- RNDIS_STATUS_NOT_SUPPORTED
- RNDIS_STATUS_NO_CABLE
- RNDIS_STATUS_NO_ROUTE_TO_DESTINATION
- RNDIS_STATUS_ONLINE
- RNDIS_STATUS_OPEN_FAILED
- RNDIS_STATUS_OPEN_LIST_FULL
- RNDIS_STATUS_PENDING
- RNDIS_STATUS_REQUEST_ABORTED
- RNDIS_STATUS_RESET_END
- RNDIS_STATUS_RESET_IN_PROGRESS
- RNDIS_STATUS_RESET_START
- RNDIS_STATUS_RESOURCES
- RNDIS_STATUS_RESOURCE_CONFLICT
- RNDIS_STATUS_RING_STATUS
- RNDIS_STATUS_SAP_IN_USE
- RNDIS_STATUS_SOFT_ERRORS
- RNDIS_STATUS_SUCCESS
- RNDIS_STATUS_TOKEN_RING_OPEN_ERROR
- RNDIS_STATUS_UNSUPPORTED_MEDIA
- RNDIS_STATUS_VC_NOT_ACTIVATED
- RNDIS_STATUS_VC_NOT_AVAILABLE
- RNDIS_STATUS_WAN_FRAGMENT
- RNDIS_STATUS_WAN_LINE_DOWN
- RNDIS_STATUS_WAN_LINE_UP
- RNDIS_STATUS_WW_INDICATION
- RNDIS_UNINITIALIZED
- RNDIS_UNKNOWN
- RNDIS_VENDOR_NUM
- RNDIS_WLAN_ALG_CCMP
- RNDIS_WLAN_ALG_NONE
- RNDIS_WLAN_ALG_TKIP
- RNDIS_WLAN_ALG_WEP
- RNDIS_WLAN_KEY_MGMT_802_1X
- RNDIS_WLAN_KEY_MGMT_NONE
- RNDIS_WLAN_KEY_MGMT_PSK
- RNDIS_WLAN_NUM_KEYS
- RNDRESEEDCRNG
- RNDZAPENTCNT
- RND_CNT
- RND_CODE
- RND_F1
- RND_F2
- RND_F3
- RND_FUN
- RNG1
- RNG1_K
- RNG1_R
- RNG2
- RNG2_K
- RNG2_R
- RNG4_MAX_HANDLES
- RNGA_CONTROL
- RNGA_CONTROL_CLEAR_INT
- RNGA_CONTROL_GO
- RNGA_CONTROL_HIGH_ASSURANCE
- RNGA_CONTROL_MASK_INTS
- RNGA_CONTROL_SLEEP
- RNGA_ENTROPY
- RNGA_MODE
- RNGA_OSC1_COUNTER
- RNGA_OSC2_COUNTER
- RNGA_OSC_CONTROL_COUNTER
- RNGA_OSC_COUNTER_STATUS
- RNGA_OUTPUT_FIFO
- RNGA_STATUS
- RNGA_STATUS_ERROR_INT
- RNGA_STATUS_FIFO_UNDERFLOW
- RNGA_STATUS_LAST_READ_STATUS
- RNGA_STATUS_LEVEL_MASK
- RNGA_STATUS_OSC_DEAD
- RNGA_STATUS_SECURITY_VIOLATION
- RNGA_STATUS_SLEEP
- RNGA_VERIFICATION_CONTROL
- RNGCON
- RNGC_CMD_CLR_ERR
- RNGC_CMD_CLR_INT
- RNGC_CMD_SEED
- RNGC_CMD_SELF_TEST
- RNGC_COMMAND
- RNGC_CONTROL
- RNGC_CTRL_MASK_DONE
- RNGC_CTRL_MASK_ERROR
- RNGC_ERROR
- RNGC_ERROR_STATUS_STAT_ERR
- RNGC_FIFO
- RNGC_STATUS
- RNGC_STATUS_ERROR
- RNGC_STATUS_FIFO_LEVEL_MASK
- RNGC_STATUS_FIFO_LEVEL_SHIFT
- RNGC_STATUS_SEED_DONE
- RNGC_STATUS_ST_DONE
- RNGC_TIMEOUT
- RNGDATA
- RNGDONE
- RNGDS_MITG_DIS
- RNGNR
- RNGNUMGEN1
- RNGNUMGEN2
- RNGPOLY1
- RNGPOLY2
- RNGRCNT
- RNGSEED1
- RNGSEED2
- RNG_ADDR_RANGE
- RNG_ALARMCNT
- RNG_ALARMCNT_ALARM_TH_MASK
- RNG_ALARMCNT_ALARM_TH_SHIFT
- RNG_ALARMCNT_REG
- RNG_ALARMCNT_SHUTDOWN_TH_MASK
- RNG_ALARMCNT_SHUTDOWN_TH_SHIFT
- RNG_ALARMMASK
- RNG_ALARMMASK_REG
- RNG_ALARMSTOP
- RNG_ALARMSTOP_REG
- RNG_ALARM_THRESHOLD
- RNG_AUTOSUSPEND_TIMEOUT
- RNG_CK
- RNG_CONFIG
- RNG_CONFIG_MAX_REFIL_CYCLES
- RNG_CONFIG_MAX_REFIL_CYCLES_MASK
- RNG_CONFIG_MAX_REFIL_CYCLES_SHIFT
- RNG_CONFIG_MIN_REFIL_CYCLES
- RNG_CONFIG_MIN_REFIL_CYCLES_MASK
- RNG_CONFIG_MIN_REFIL_CYCLES_SHIFT
- RNG_CONFIG_REG
- RNG_CONTROL
- RNG_CONTROL_ENABLE_TRNG_MASK
- RNG_CONTROL_ENABLE_TRNG_SHIFT
- RNG_CONTROL_REG
- RNG_CONTROL_STARTUP_CYCLES
- RNG_CONTROL_STARTUP_CYCLES_MASK
- RNG_CONTROL_STARTUP_CYCLES_SHIFT
- RNG_CR
- RNG_CR_CED
- RNG_CR_RNGEN
- RNG_CTL_ES1
- RNG_CTL_ES2
- RNG_CTL_ES3
- RNG_CTL_LFSR
- RNG_CTRL
- RNG_CTRL_OFFSET
- RNG_CTRL_RNG_RBGEN_DISABLE
- RNG_CTRL_RNG_RBGEN_ENABLE
- RNG_CTRL_RNG_RBGEN_MASK
- RNG_DATA
- RNG_DATA_FILL_TIMEOUT
- RNG_DR
- RNG_EIP_REV
- RNG_EN
- RNG_ENABLE
- RNG_ENABLED
- RNG_FIFO_COUNT_OFFSET
- RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK
- RNG_FIFO_DATA_OFFSET
- RNG_FRODETUNE
- RNG_FRODETUNE_REG
- RNG_FROENABLE
- RNG_FROENABLE_REG
- RNG_GEN_HW
- RNG_GEN_PRNG_HW_INIT
- RNG_INOUT_0
- RNG_INTACK_REG
- RNG_INTMASK_REG
- RNG_INTR_STS_ACK
- RNG_INT_MASK
- RNG_INT_OFF
- RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK
- RNG_INT_STATUS_NIST_FAIL_IRQ_MASK
- RNG_INT_STATUS_OFFSET
- RNG_INT_STATUS_STARTUP_TRANSITIONS_MET_IRQ_MASK
- RNG_INT_STATUS_TOTAL_BITS_COUNT_IRQ_MASK
- RNG_IP
- RNG_MAX_DATUM
- RNG_MISCDEV_MINOR
- RNG_MODULE_NAME
- RNG_OPTIONS
- RNG_OUTPUT_0_REG
- RNG_OUTPUT_1_REG
- RNG_OUTPUT_2_REG
- RNG_OUTPUT_3_REG
- RNG_PHY_SEED
- RNG_PRESENT
- RNG_RAN_NUM
- RNG_RBGEN
- RNG_READY
- RNG_REG_FRODETUNE_MASK
- RNG_REG_FROENABLE_MASK
- RNG_REG_INTACK_RDY_MASK
- RNG_REG_INTACK_SHUTDOWN_OFLO_MASK
- RNG_REG_STATUS_RDY
- RNG_RESET
- RNG_REV_REG
- RNG_RING_EN
- RNG_SEED
- RNG_SEED_SEL
- RNG_SEED_SIZE
- RNG_SHUTDOWN_OFLO_MASK
- RNG_SHUTDOWN_THRESHOLD
- RNG_SOFT_RESET
- RNG_SOFT_RESET_OFFSET
- RNG_SR
- RNG_SR_CEIS
- RNG_SR_DRDY
- RNG_SR_SEIS
- RNG_STATUS
- RNG_STATUS_REG
- RNG_SYSCONFIG_REG
- RNG_TIMEOUT
- RNG_VERSION
- RNG_WARMUP_COUNT
- RNG_v1_CTL_ASEL
- RNG_v1_CTL_ASEL_NOOUT
- RNG_v1_CTL_ASEL_SHIFT
- RNG_v1_CTL_BYPASS
- RNG_v1_CTL_VCO
- RNG_v1_CTL_VCO_SHIFT
- RNG_v1_CTL_WAIT
- RNG_v1_CTL_WAIT_SHIFT
- RNG_v1_SELFTEST_TICKS
- RNG_v1_SELFTEST_VAL
- RNG_v2_CTL_ASEL
- RNG_v2_CTL_ASEL_NOOUT
- RNG_v2_CTL_ASEL_SHIFT
- RNG_v2_CTL_BYPASS
- RNG_v2_CTL_PERF
- RNG_v2_CTL_VCO
- RNG_v2_CTL_VCO_SHIFT
- RNG_v2_CTL_WAIT
- RNG_v2_CTL_WAIT_SHIFT
- RNG_v2_SELFTEST_TICKS
- RNG_v2_SELFTEST_VAL
- RNID
- RNID_ASSOCIATED_TYPE_BRIDGE
- RNID_ASSOCIATED_TYPE_GATEWAY
- RNID_ASSOCIATED_TYPE_HOST
- RNID_ASSOCIATED_TYPE_HUB
- RNID_ASSOCIATED_TYPE_MULTI_FUNCTION_DEVICE
- RNID_ASSOCIATED_TYPE_NAS_SERVER
- RNID_ASSOCIATED_TYPE_OTHER
- RNID_ASSOCIATED_TYPE_STORAGE_ACCESS_DEVICE
- RNID_ASSOCIATED_TYPE_STORAGE_DEVICE
- RNID_ASSOCIATED_TYPE_STORAGE_SUBSYSTEM
- RNID_ASSOCIATED_TYPE_SWITCH
- RNID_ASSOCIATED_TYPE_UNKNOWN
- RNID_ASSOCIATED_TYPE_VIRTUALIZATION_DEVICE
- RNID_NODEID_DATA_FORMAT_COMMON
- RNID_NODEID_DATA_FORMAT_DISCOVERY
- RNID_NODEID_DATA_FORMAT_FCP3
- RNID_TOP_DISC
- RNID_TYPE_ASIC_TEMP
- RNID_TYPE_PORT_LOGIN
- RNID_TYPE_SET_VERSION
- RNN_ID_CMD
- RNN_ID_REQ_SIZE
- RNN_ID_RSP_SIZE
- RNN_ID_SNS_CMD_SIZE
- RNN_ID_SNS_DATA_SIZE
- RNN_ID_SNS_SCMD_LEN
- RNN_REQUEST_SZ
- RNOT
- RNPP_F
- RNPP_S
- RNPP_V
- RNR
- RNTPCO
- RNW
- RN_BITS
- RN_BUF_SIZE
- RN_OFFSET
- RO
- ROAMING_INITIATED
- ROAMING_LIMIT
- ROAMING_TRIGGER_LOW_RSSI_EVENT_ID
- ROAMING_TRIGGER_LOW_SNR_EVENT_ID
- ROAMING_TRIGGER_MAX_TX_RETRY_EVENT_ID
- ROAMING_TRIGGER_REGAINED_RSSI_EVENT_ID
- ROAMING_TRIGGER_REGAINED_SNR_EVENT_ID
- ROAM_DATA_TIME
- ROAM_OFFLOAD
- ROAM_SCAN_CTRL_FLAGS
- ROAM_TBL_PEND
- ROBUST_LIST_LIMIT
- ROCCATIOCGREPSIZE
- ROCCAT_CBUF_SIZE
- ROCCAT_COMMON2_BIN_ATTRIBUTE_R
- ROCCAT_COMMON2_BIN_ATTRIBUTE_RW
- ROCCAT_COMMON2_BIN_ATTRIBUTE_W
- ROCCAT_COMMON2_SYSFS_R
- ROCCAT_COMMON2_SYSFS_RW
- ROCCAT_COMMON2_SYSFS_W
- ROCCAT_COMMON_COMMAND_CONTROL
- ROCCAT_COMMON_CONTROL_STATUS_BUSY
- ROCCAT_COMMON_CONTROL_STATUS_CRITICAL
- ROCCAT_COMMON_CONTROL_STATUS_CRITICAL_NEW
- ROCCAT_COMMON_CONTROL_STATUS_INVALID
- ROCCAT_COMMON_CONTROL_STATUS_OK
- ROCCAT_FIRST_MINOR
- ROCCAT_MAX_DEVICES
- ROCEE_ACK_DELAY_REG
- ROCEE_BT_CMD_H_REG
- ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M
- ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S
- ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S
- ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M
- ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S
- ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M
- ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S
- ROCEE_BT_CMD_H_ROCEE_BT_CMD_S
- ROCEE_BT_CMD_L_REG
- ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_M
- ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_AEQE_SHIFT_S
- ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_M
- ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQC_STATE_S
- ROCEE_CAEP_AEQC_AEQE_SHIFT_CAEP_AEQ_ALM_OVF_INT_ST_S
- ROCEE_CAEP_AEQC_AEQE_SHIFT_REG
- ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_M
- ROCEE_CAEP_AEQE_CONS_IDX_CAEP_AEQE_CONS_IDX_S
- ROCEE_CAEP_AEQE_CONS_IDX_REG
- ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_M
- ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQE_CUR_IDX_S
- ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_M
- ROCEE_CAEP_AEQE_CUR_IDX_CAEP_AEQ_BT_H_S
- ROCEE_CAEP_AE_MASK_CAEP_AEQ_ALM_OVF_MASK_S
- ROCEE_CAEP_AE_MASK_CAEP_AE_IRQ_MASK_S
- ROCEE_CAEP_AE_MASK_REG
- ROCEE_CAEP_AE_ST_CAEP_AEQ_ALM_OVF_S
- ROCEE_CAEP_AE_ST_REG
- ROCEE_CAEP_CEQC_CONS_IDX_0_REG
- ROCEE_CAEP_CEQC_SHIFT_0_REG
- ROCEE_CAEP_CEQC_SHIFT_CAEP_CEQ_ALM_OVF_INT_ST_S
- ROCEE_CAEP_CEQ_ALM_OVF_0_REG
- ROCEE_CAEP_CEQ_ALM_OVF_CAEP_CEQ_ALM_OVF_S
- ROCEE_CAEP_CE_BURST_NUM_CFG_REG
- ROCEE_CAEP_CE_INTERVAL_CFG_REG
- ROCEE_CAEP_CE_IRQ_MASK_0_REG
- ROCEE_CAEP_CE_IRQ_MASK_CAEP_CEQ_ALM_OVF_MASK_S
- ROCEE_CAEP_CQE_WCMD_EMPTY
- ROCEE_CNT_CLR_CE_CNT_CLR_CE_S
- ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M
- ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_M
- ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_MDF_S
- ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S
- ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S
- ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_M
- ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_INP_H_S
- ROCEE_DB_OTHERS_L_0_REG
- ROCEE_DB_OTHERS_WL_REG
- ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M
- ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S
- ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M
- ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S
- ROCEE_DB_SQ_L_0_REG
- ROCEE_DB_SQ_WL_REG
- ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M
- ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S
- ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M
- ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S
- ROCEE_DMAE_USER_CFG1_REG
- ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M
- ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S
- ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M
- ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S
- ROCEE_DMAE_USER_CFG2_REG
- ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M
- ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S
- ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M
- ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S
- ROCEE_ECC_CERR_ALM0_REG
- ROCEE_ECC_CERR_ALM1_REG
- ROCEE_ECC_CERR_ALM2_REG
- ROCEE_ECC_UCERR_ALM0_REG
- ROCEE_ECC_UCERR_ALM1_REG
- ROCEE_ECC_UCERR_ALM2_REG
- ROCEE_EXT_DB_OTHERS_WL_EMPTY_REG
- ROCEE_EXT_DB_OTHERS_WL_REG
- ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M
- ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S
- ROCEE_EXT_DB_OTH_H_REG
- ROCEE_EXT_DB_OTH_REG
- ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M
- ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S
- ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M
- ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S
- ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M
- ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S
- ROCEE_EXT_DB_SQ_H_REG
- ROCEE_EXT_DB_SQ_REG
- ROCEE_EXT_DB_SQ_WL_EMPTY_REG
- ROCEE_EXT_DB_SQ_WL_REG
- ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_M
- ROCEE_EXT_RAQ_H_EXT_RAQ_BA_H_S
- ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_M
- ROCEE_EXT_RAQ_H_EXT_RAQ_SHIFT_S
- ROCEE_EXT_RAQ_H_REG
- ROCEE_EXT_RAQ_REG
- ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S
- ROCEE_GLB_CFG_REG
- ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S
- ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S
- ROCEE_GLB_CFG_ROCEE_PORT_ST_M
- ROCEE_GLB_CFG_ROCEE_PORT_ST_S
- ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S
- ROCEE_GLB_CFG_TRP_RAQ_DROP_EN_S
- ROCEE_MB1_REG
- ROCEE_MB6_REG
- ROCEE_MB6_ROCEE_MB_CMD_M
- ROCEE_MB6_ROCEE_MB_CMD_MDF_M
- ROCEE_MB6_ROCEE_MB_CMD_MDF_S
- ROCEE_MB6_ROCEE_MB_CMD_S
- ROCEE_MB6_ROCEE_MB_EVENT_S
- ROCEE_MB6_ROCEE_MB_HW_RUN_S
- ROCEE_MB6_ROCEE_MB_TOKEN_M
- ROCEE_MB6_ROCEE_MB_TOKEN_S
- ROCEE_PORT_GID_H_0_REG
- ROCEE_PORT_GID_L_0_REG
- ROCEE_PORT_GID_MH_0_REG
- ROCEE_PORT_GID_ML_0_REG
- ROCEE_QP1C_CFG0_0_REG
- ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M
- ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S
- ROCEE_QP1C_CFG3_0_REG
- ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M
- ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S
- ROCEE_RAQ_WL_REG
- ROCEE_RAQ_WL_ROCEE_RAQ_WL_M
- ROCEE_RAQ_WL_ROCEE_RAQ_WL_S
- ROCEE_RX_CMQ_BASEADDR_H_REG
- ROCEE_RX_CMQ_BASEADDR_L_REG
- ROCEE_RX_CMQ_DEPTH_REG
- ROCEE_RX_CMQ_HEAD_REG
- ROCEE_RX_CMQ_TAIL_REG
- ROCEE_SCAEP_WR_CQE_CNT
- ROCEE_SDB_CNT_CMP_BITS
- ROCEE_SDB_INV_CNT_SDB_INV_CNT_M
- ROCEE_SDB_INV_CNT_SDB_INV_CNT_S
- ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_M
- ROCEE_SDB_ISSUE_PTR_SDB_ISSUE_PTR_S
- ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_M
- ROCEE_SDB_RETRY_CNT_SDB_RETRY_CT_S
- ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_M
- ROCEE_SDB_SEND_PTR_SDB_SEND_PTR_S
- ROCEE_SMAC_H_0_REG
- ROCEE_SMAC_H_ROCEE_PORT_MTU_M
- ROCEE_SMAC_H_ROCEE_PORT_MTU_S
- ROCEE_SMAC_H_ROCEE_SMAC_H_M
- ROCEE_SMAC_H_ROCEE_SMAC_H_S
- ROCEE_SMAC_L_0_REG
- ROCEE_SYS_IMAGE_GUID_H_REG
- ROCEE_SYS_IMAGE_GUID_L_REG
- ROCEE_TSP_BP_ST_QH_FIFO_ENTRY_S
- ROCEE_TX_CMQ_BASEADDR_H_REG
- ROCEE_TX_CMQ_BASEADDR_L_REG
- ROCEE_TX_CMQ_DEPTH_REG
- ROCEE_TX_CMQ_HEAD_REG
- ROCEE_TX_CMQ_TAIL_REG
- ROCEE_VENDOR_ID_REG
- ROCEE_VENDOR_PART_ID_REG
- ROCEE_VF_ABN_INT_CFG_REG
- ROCEE_VF_ABN_INT_EN_REG
- ROCEE_VF_ABN_INT_ST_REG
- ROCEE_VF_EQ_DB_CFG0_REG
- ROCEE_VF_EQ_DB_CFG1_REG
- ROCEE_VF_EVENT_INT_EN_REG
- ROCEE_WRMS_POL_TIME_INTERVAL_REG
- ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_EXT_RAQ_MODE
- ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_M
- ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_POL_TIME_INTERVAL_S
- ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_M
- ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_CFG_S
- ROCEE_WRMS_POL_TIME_INTERVAL_WRMS_RAQ_TIMEOUT_CHK_EN_S
- ROCEV1_FLOW_ID
- ROCEV2_CNP_FLOW_ID
- ROCEV2_FLOW_ID
- ROCE_ASYNC_EVENT_COMM_EST
- ROCE_ASYNC_EVENT_CQ_ERR
- ROCE_ASYNC_EVENT_CQ_OVERFLOW_ERR
- ROCE_ASYNC_EVENT_DESTROY_QP_DONE
- ROCE_ASYNC_EVENT_INVALID_XRCETH_ERR
- ROCE_ASYNC_EVENT_LAST_WQE_REACHED
- ROCE_ASYNC_EVENT_LOCAL_ACCESS_ERR
- ROCE_ASYNC_EVENT_LOCAL_CATASTROPHIC_ERR
- ROCE_ASYNC_EVENT_LOCAL_INVALID_REQUEST_ERR
- ROCE_ASYNC_EVENT_NONE
- ROCE_ASYNC_EVENT_QP_CATASTROPHIC_ERR
- ROCE_ASYNC_EVENT_SQ_DRAINED
- ROCE_ASYNC_EVENT_SRQ_EMPTY
- ROCE_ASYNC_EVENT_SRQ_LIMIT
- ROCE_ASYNC_EVENT_XRC_DOMAIN_ERR
- ROCE_ASYNC_EVENT_XRC_SRQ_CATASTROPHIC_ERR
- ROCE_BITMAP_SZ
- ROCE_CQE_CMP_V
- ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_MASK
- ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_SHIFT
- ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK
- ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT
- ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK
- ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT
- ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK
- ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT
- ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK
- ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT
- ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK
- ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT
- ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK
- ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT
- ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK
- ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT
- ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_MASK
- ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_SHIFT
- ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK
- ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT
- ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK
- ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT
- ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK
- ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT
- ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK
- ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT
- ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK
- ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT
- ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK
- ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT
- ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK
- ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT
- ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_MASK
- ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_SHIFT
- ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK
- ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT
- ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK
- ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT
- ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_MASK
- ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_SHIFT
- ROCE_DCQCN_NP_MAX_QPS
- ROCE_DCQCN_RP_MAX_QPS
- ROCE_DRV_MODULE_NAME
- ROCE_EVENT_CREATE_QP
- ROCE_EVENT_CREATE_UD_QP
- ROCE_EVENT_DESTROY_QP
- ROCE_EVENT_DESTROY_UD_QP
- ROCE_EVENT_FUNC_UPDATE
- ROCE_EVENT_MODIFY_QP
- ROCE_EVENT_QUERY_QP
- ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_MASK
- ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_SHIFT
- ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_MASK
- ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_SHIFT
- ROCE_INIT_FUNC_PARAMS_RESERVED0_MASK
- ROCE_INIT_FUNC_PARAMS_RESERVED0_SHIFT
- ROCE_LKEY_MW_DIF_EN_BIT
- ROCE_MAX_QPS
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUES_FLG_MASK
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUES_FLG_SHIFT
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK
- ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUES_FLG_MASK
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUES_FLG_SHIFT
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK
- ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT
- ROCE_NETDEV_CALLBACK_SZ
- ROCE_PACKET
- ROCE_PG_SIZE_1G
- ROCE_PG_SIZE_2M
- ROCE_PG_SIZE_4K
- ROCE_PG_SIZE_64K
- ROCE_PG_SIZE_8K
- ROCE_PG_SIZE_8M
- ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK
- ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT
- ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK
- ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT
- ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK
- ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT
- ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK
- ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT
- ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK
- ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT
- ROCE_RAMROD_CREATE_QP
- ROCE_RAMROD_CREATE_UD_QP
- ROCE_RAMROD_DESTROY_QP
- ROCE_RAMROD_DESTROY_UD_QP
- ROCE_RAMROD_FUNC_UPDATE
- ROCE_RAMROD_MODIFY_QP
- ROCE_RAMROD_QUERY_QP
- ROCE_REQ_MAX_INLINE_DATA_SIZE
- ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE
- ROCE_SP_HSI_NA_SIGNATURE
- ROCE_SP_HSI_VERSION_MAJOR
- ROCE_SP_HSI_VERSION_MINOR
- ROCE_SP_HSI_VERSION_STR
- ROCE_SP_HSI_VERSION_UPDATE
- ROCE_TYPE
- ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_MASK
- ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_SHIFT
- ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_MASK
- ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_SHIFT
- ROCE_UPDATE_FUNC_PARAMS_RESERVED0_MASK
- ROCE_UPDATE_FUNC_PARAMS_RESERVED0_SHIFT
- ROCE_V1
- ROCE_V2_IPV4
- ROCE_V2_IPV6
- ROCE_V2_UDP_DPORT
- ROCE_VER_KEY
- ROCIT_CONFIG_GEN0
- ROCIT_CONFIG_GEN0_PCI_IOCU
- ROCIT_CONFIG_GEN1
- ROCIT_CONFIG_GEN1_MEMMAP_MASK
- ROCIT_CONFIG_GEN1_MEMMAP_SHIFT
- ROCIT_REG_BASE
- ROCKCHIP_ARM_OFF_LOGIC_DEEP
- ROCKCHIP_ARM_OFF_LOGIC_NORMAL
- ROCKCHIP_CPUCLK_NUM_DIVIDERS
- ROCKCHIP_DDRCLK_SIP
- ROCKCHIP_DIV_BCLK
- ROCKCHIP_DIV_MCLK
- ROCKCHIP_INVERTER_HIWORD_MASK
- ROCKCHIP_MAX_CONNECTOR
- ROCKCHIP_MAX_CRTC
- ROCKCHIP_MAX_FB_BUFFER
- ROCKCHIP_MMC_DEGREE_MASK
- ROCKCHIP_MMC_DELAYNUM_MASK
- ROCKCHIP_MMC_DELAYNUM_OFFSET
- ROCKCHIP_MMC_DELAY_ELEMENT_PSEC
- ROCKCHIP_MMC_DELAY_SEL
- ROCKCHIP_OUTPUT_DSI_DUAL
- ROCKCHIP_OUT_MODE_AAAA
- ROCKCHIP_OUT_MODE_P565
- ROCKCHIP_OUT_MODE_P666
- ROCKCHIP_OUT_MODE_P888
- ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0
- ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1
- ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0
- ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1
- ROCKCHIP_PCIE_AT_OB_REGION_DESC0
- ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN
- ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK
- ROCKCHIP_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID
- ROCKCHIP_PCIE_AT_OB_REGION_DESC1
- ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0
- ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_BUS
- ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK
- ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN
- ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK
- ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1
- ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_DISABLED
- ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_IO_32BITS
- ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_32BITS
- ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_64BITS
- ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_32BITS
- ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_64BITS
- ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0
- ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1
- ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE
- ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK
- ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL
- ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK
- ROCKCHIP_PCIE_EP_CMD_STATUS
- ROCKCHIP_PCIE_EP_CMD_STATUS_IS
- ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR
- ROCKCHIP_PCIE_EP_FUNC_BASE
- ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP
- ROCKCHIP_PCIE_EP_MSI_CTRL_ME
- ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK
- ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET
- ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK
- ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET
- ROCKCHIP_PCIE_EP_MSI_CTRL_REG
- ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR
- ROCKCHIP_PCIE_MSG_CODE
- ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTA
- ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTB
- ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTC
- ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTD
- ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTA
- ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTB
- ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTC
- ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTD
- ROCKCHIP_PCIE_MSG_CODE_MASK
- ROCKCHIP_PCIE_MSG_NO_DATA
- ROCKCHIP_PCIE_MSG_ROUTING
- ROCKCHIP_PCIE_MSG_ROUTING_BROADCAST
- ROCKCHIP_PCIE_MSG_ROUTING_LOCAL_INTX
- ROCKCHIP_PCIE_MSG_ROUTING_MASK
- ROCKCHIP_PCIE_MSG_ROUTING_PME_ACK
- ROCKCHIP_PCIE_MSG_ROUTING_TO_RC
- ROCKCHIP_PCIE_MSG_ROUTING_VIA_ADDR
- ROCKCHIP_PCIE_MSG_ROUTING_VIA_ID
- ROCKCHIP_PDM_FORMATS
- ROCKCHIP_PDM_RATES
- ROCKCHIP_PLL_SYNC_RATE
- ROCKCHIP_ROUTE_GRF
- ROCKCHIP_ROUTE_PMU
- ROCKCHIP_ROUTE_SAME
- ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ
- ROCKCHIP_SIP_CONFIG_DRAM_GET_BW
- ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE
- ROCKCHIP_SIP_CONFIG_DRAM_INIT
- ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE
- ROCKCHIP_SIP_CONFIG_DRAM_SET_AT_SR
- ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD
- ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM
- ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE
- ROCKCHIP_SIP_DRAM_FREQ
- ROCKCHIP_SOFTRST_HIWORD_MASK
- ROCKCHIP_SPI_BAUDR
- ROCKCHIP_SPI_CLR_BITS
- ROCKCHIP_SPI_CTRLR0
- ROCKCHIP_SPI_CTRLR1
- ROCKCHIP_SPI_DMACR
- ROCKCHIP_SPI_DMARDLR
- ROCKCHIP_SPI_DMATDLR
- ROCKCHIP_SPI_ICR
- ROCKCHIP_SPI_IMR
- ROCKCHIP_SPI_IPR
- ROCKCHIP_SPI_ISR
- ROCKCHIP_SPI_MAX_CS_NUM
- ROCKCHIP_SPI_MAX_TRANLEN
- ROCKCHIP_SPI_RISR
- ROCKCHIP_SPI_RXDR
- ROCKCHIP_SPI_RXFLR
- ROCKCHIP_SPI_RXFTLR
- ROCKCHIP_SPI_SER
- ROCKCHIP_SPI_SET_BITS
- ROCKCHIP_SPI_SR
- ROCKCHIP_SPI_SSIENR
- ROCKCHIP_SPI_TXDR
- ROCKCHIP_SPI_TXFLR
- ROCKCHIP_SPI_TXFTLR
- ROCKCHIP_VENDOR_ID
- ROCKER_BOGUS_REG0
- ROCKER_BOGUS_REG1
- ROCKER_BOGUS_REG2
- ROCKER_BOGUS_REG3
- ROCKER_CONTROL
- ROCKER_CONTROL_RESET
- ROCKER_DMA_CMD
- ROCKER_DMA_CMD_DEFAULT_SIZE
- ROCKER_DMA_DESC_ADDR
- ROCKER_DMA_DESC_COMP_ERR_GEN
- ROCKER_DMA_DESC_CREDITS
- ROCKER_DMA_DESC_CTRL
- ROCKER_DMA_DESC_CTRL_RESET
- ROCKER_DMA_DESC_HEAD
- ROCKER_DMA_DESC_RES1
- ROCKER_DMA_DESC_SIZE
- ROCKER_DMA_DESC_TAIL
- ROCKER_DMA_EVENT
- ROCKER_DMA_EVENT_DEFAULT_SIZE
- ROCKER_DMA_RX
- ROCKER_DMA_RX_DEFAULT_SIZE
- ROCKER_DMA_RX_DESC_SIZE
- ROCKER_DMA_SIZE_MAX
- ROCKER_DMA_SIZE_MIN
- ROCKER_DMA_TX
- ROCKER_DMA_TX_DEFAULT_SIZE
- ROCKER_DMA_TX_DESC_SIZE
- ROCKER_EEXIST
- ROCKER_EINVAL
- ROCKER_EMSGSIZE
- ROCKER_ENOBUFS
- ROCKER_ENOENT
- ROCKER_ENOMEM
- ROCKER_ENOTSUP
- ROCKER_ENXIO
- ROCKER_FP_PORTS_MAX
- ROCKER_GROUP_INDEX_GET
- ROCKER_GROUP_INDEX_LONG_GET
- ROCKER_GROUP_INDEX_LONG_MASK
- ROCKER_GROUP_INDEX_LONG_SET
- ROCKER_GROUP_INDEX_LONG_SHIFT
- ROCKER_GROUP_INDEX_MASK
- ROCKER_GROUP_INDEX_SET
- ROCKER_GROUP_INDEX_SHIFT
- ROCKER_GROUP_L2_FLOOD
- ROCKER_GROUP_L2_INTERFACE
- ROCKER_GROUP_L2_MCAST
- ROCKER_GROUP_L2_REWRITE
- ROCKER_GROUP_L3_UNICAST
- ROCKER_GROUP_NONE
- ROCKER_GROUP_PORT_GET
- ROCKER_GROUP_PORT_MASK
- ROCKER_GROUP_PORT_SET
- ROCKER_GROUP_PORT_SHIFT
- ROCKER_GROUP_SUBTYPE_MASK
- ROCKER_GROUP_SUBTYPE_SHIFT
- ROCKER_GROUP_TUNNEL_ID_MASK
- ROCKER_GROUP_TUNNEL_ID_SHIFT
- ROCKER_GROUP_TYPE_GET
- ROCKER_GROUP_TYPE_MASK
- ROCKER_GROUP_TYPE_SET
- ROCKER_GROUP_TYPE_SHIFT
- ROCKER_GROUP_VLAN_GET
- ROCKER_GROUP_VLAN_MASK
- ROCKER_GROUP_VLAN_SET
- ROCKER_GROUP_VLAN_SHIFT
- ROCKER_MSIX_VEC_CMD
- ROCKER_MSIX_VEC_COUNT
- ROCKER_MSIX_VEC_EVENT
- ROCKER_MSIX_VEC_RESERVED0
- ROCKER_MSIX_VEC_RX
- ROCKER_MSIX_VEC_TEST
- ROCKER_MSIX_VEC_TX
- ROCKER_OF_DPA_GROUP_TYPE_L2_FLOOD
- ROCKER_OF_DPA_GROUP_TYPE_L2_INTERFACE
- ROCKER_OF_DPA_GROUP_TYPE_L2_MCAST
- ROCKER_OF_DPA_GROUP_TYPE_L2_OVERLAY
- ROCKER_OF_DPA_GROUP_TYPE_L2_REWRITE
- ROCKER_OF_DPA_GROUP_TYPE_L3_ECMP
- ROCKER_OF_DPA_GROUP_TYPE_L3_INTERFACE
- ROCKER_OF_DPA_GROUP_TYPE_L3_MCAST
- ROCKER_OF_DPA_GROUP_TYPE_L3_UCAST
- ROCKER_OF_DPA_OVERLAY_TYPE_FLOOD_MCAST
- ROCKER_OF_DPA_OVERLAY_TYPE_FLOOD_UCAST
- ROCKER_OF_DPA_OVERLAY_TYPE_MCAST_MCAST
- ROCKER_OF_DPA_OVERLAY_TYPE_MCAST_UCAST
- ROCKER_OF_DPA_TABLE_ID_ACL_POLICY
- ROCKER_OF_DPA_TABLE_ID_BRIDGING
- ROCKER_OF_DPA_TABLE_ID_INGRESS_PORT
- ROCKER_OF_DPA_TABLE_ID_MULTICAST_ROUTING
- ROCKER_OF_DPA_TABLE_ID_TERMINATION_MAC
- ROCKER_OF_DPA_TABLE_ID_UNICAST_ROUTING
- ROCKER_OF_DPA_TABLE_ID_VLAN
- ROCKER_OK
- ROCKER_PCI_BAR0_SIZE
- ROCKER_PORT_MAX_MTU
- ROCKER_PORT_MIN_MTU
- ROCKER_PORT_MODE_OF_DPA
- ROCKER_PORT_PHYS_COUNT
- ROCKER_PORT_PHYS_ENABLE
- ROCKER_PORT_PHYS_LINK_STATUS
- ROCKER_PORT_STATS_LEN
- ROCKER_RX_FLAGS_CSUM_CALC
- ROCKER_RX_FLAGS_FWD_OFFLOAD
- ROCKER_RX_FLAGS_IPV4
- ROCKER_RX_FLAGS_IPV4_CSUM_GOOD
- ROCKER_RX_FLAGS_IPV6
- ROCKER_RX_FLAGS_IP_FRAG
- ROCKER_RX_FLAGS_TCP
- ROCKER_RX_FLAGS_TCP_UDP_CSUM_GOOD
- ROCKER_RX_FLAGS_UDP
- ROCKER_SWITCH_ID
- ROCKER_TEST_DMA_ADDR
- ROCKER_TEST_DMA_BUF_SIZE
- ROCKER_TEST_DMA_CTRL
- ROCKER_TEST_DMA_CTRL_CLEAR
- ROCKER_TEST_DMA_CTRL_FILL
- ROCKER_TEST_DMA_CTRL_INVERT
- ROCKER_TEST_DMA_FILL_PATTERN
- ROCKER_TEST_DMA_SIZE
- ROCKER_TEST_IRQ
- ROCKER_TEST_REG
- ROCKER_TEST_REG64
- ROCKER_TLV_ALIGN
- ROCKER_TLV_ALIGNTO
- ROCKER_TLV_CMD_INFO
- ROCKER_TLV_CMD_MAX
- ROCKER_TLV_CMD_PORT_SETTINGS_AUTONEG
- ROCKER_TLV_CMD_PORT_SETTINGS_DUPLEX
- ROCKER_TLV_CMD_PORT_SETTINGS_LEARNING
- ROCKER_TLV_CMD_PORT_SETTINGS_MACADDR
- ROCKER_TLV_CMD_PORT_SETTINGS_MAX
- ROCKER_TLV_CMD_PORT_SETTINGS_MODE
- ROCKER_TLV_CMD_PORT_SETTINGS_MTU
- ROCKER_TLV_CMD_PORT_SETTINGS_PHYS_NAME
- ROCKER_TLV_CMD_PORT_SETTINGS_PPORT
- ROCKER_TLV_CMD_PORT_SETTINGS_SPEED
- ROCKER_TLV_CMD_PORT_SETTINGS_UNSPEC
- ROCKER_TLV_CMD_PORT_STATS_MAX
- ROCKER_TLV_CMD_PORT_STATS_PPORT
- ROCKER_TLV_CMD_PORT_STATS_RX_BYTES
- ROCKER_TLV_CMD_PORT_STATS_RX_DROPPED
- ROCKER_TLV_CMD_PORT_STATS_RX_ERRORS
- ROCKER_TLV_CMD_PORT_STATS_RX_PKTS
- ROCKER_TLV_CMD_PORT_STATS_TX_BYTES
- ROCKER_TLV_CMD_PORT_STATS_TX_DROPPED
- ROCKER_TLV_CMD_PORT_STATS_TX_ERRORS
- ROCKER_TLV_CMD_PORT_STATS_TX_PKTS
- ROCKER_TLV_CMD_PORT_STATS_UNSPEC
- ROCKER_TLV_CMD_TYPE
- ROCKER_TLV_CMD_TYPE_CLEAR_PORT_STATS
- ROCKER_TLV_CMD_TYPE_GET_PORT_SETTINGS
- ROCKER_TLV_CMD_TYPE_GET_PORT_STATS
- ROCKER_TLV_CMD_TYPE_MAX
- ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_ADD
- ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_DEL
- ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_GET_STATS
- ROCKER_TLV_CMD_TYPE_OF_DPA_FLOW_MOD
- ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_ADD
- ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_DEL
- ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_GET_STATS
- ROCKER_TLV_CMD_TYPE_OF_DPA_GROUP_MOD
- ROCKER_TLV_CMD_TYPE_SET_PORT_SETTINGS
- ROCKER_TLV_CMD_TYPE_UNSPEC
- ROCKER_TLV_CMD_UNSPEC
- ROCKER_TLV_EVENT_INFO
- ROCKER_TLV_EVENT_LINK_CHANGED_LINKUP
- ROCKER_TLV_EVENT_LINK_CHANGED_MAX
- ROCKER_TLV_EVENT_LINK_CHANGED_PPORT
- ROCKER_TLV_EVENT_LINK_CHANGED_UNSPEC
- ROCKER_TLV_EVENT_MAC_VLAN_MAC
- ROCKER_TLV_EVENT_MAC_VLAN_MAX
- ROCKER_TLV_EVENT_MAC_VLAN_PPORT
- ROCKER_TLV_EVENT_MAC_VLAN_UNSPEC
- ROCKER_TLV_EVENT_MAC_VLAN_VLAN_ID
- ROCKER_TLV_EVENT_MAX
- ROCKER_TLV_EVENT_TYPE
- ROCKER_TLV_EVENT_TYPE_LINK_CHANGED
- ROCKER_TLV_EVENT_TYPE_MAC_VLAN_SEEN
- ROCKER_TLV_EVENT_TYPE_MAX
- ROCKER_TLV_EVENT_TYPE_UNSPEC
- ROCKER_TLV_EVENT_UNSPEC
- ROCKER_TLV_HDRLEN
- ROCKER_TLV_OF_DPA_CLEAR_ACTIONS
- ROCKER_TLV_OF_DPA_COOKIE
- ROCKER_TLV_OF_DPA_COPY_CPU_ACTION
- ROCKER_TLV_OF_DPA_DST_IP
- ROCKER_TLV_OF_DPA_DST_IPV6
- ROCKER_TLV_OF_DPA_DST_IPV6_MASK
- ROCKER_TLV_OF_DPA_DST_IP_MASK
- ROCKER_TLV_OF_DPA_DST_MAC
- ROCKER_TLV_OF_DPA_DST_MAC_MASK
- ROCKER_TLV_OF_DPA_ETHERTYPE
- ROCKER_TLV_OF_DPA_FLOW_STAT_DURATION
- ROCKER_TLV_OF_DPA_FLOW_STAT_MAX
- ROCKER_TLV_OF_DPA_FLOW_STAT_RX_PKTS
- ROCKER_TLV_OF_DPA_FLOW_STAT_TX_PKTS
- ROCKER_TLV_OF_DPA_FLOW_STAT_UNSPEC
- ROCKER_TLV_OF_DPA_GOTO_TABLE_ID
- ROCKER_TLV_OF_DPA_GROUP_COUNT
- ROCKER_TLV_OF_DPA_GROUP_ID
- ROCKER_TLV_OF_DPA_GROUP_IDS
- ROCKER_TLV_OF_DPA_GROUP_ID_LOWER
- ROCKER_TLV_OF_DPA_HARDTIME
- ROCKER_TLV_OF_DPA_ICMP_CODE
- ROCKER_TLV_OF_DPA_ICMP_CODE_MASK
- ROCKER_TLV_OF_DPA_ICMP_TYPE
- ROCKER_TLV_OF_DPA_ICMP_TYPE_MASK
- ROCKER_TLV_OF_DPA_IDLETIME
- ROCKER_TLV_OF_DPA_IN_PPORT
- ROCKER_TLV_OF_DPA_IN_PPORT_MASK
- ROCKER_TLV_OF_DPA_IPV6_LABEL
- ROCKER_TLV_OF_DPA_IPV6_LABEL_MASK
- ROCKER_TLV_OF_DPA_IP_DSCP
- ROCKER_TLV_OF_DPA_IP_DSCP_ACTION
- ROCKER_TLV_OF_DPA_IP_DSCP_MASK
- ROCKER_TLV_OF_DPA_IP_ECN
- ROCKER_TLV_OF_DPA_IP_ECN_MASK
- ROCKER_TLV_OF_DPA_IP_PROTO
- ROCKER_TLV_OF_DPA_IP_PROTO_MASK
- ROCKER_TLV_OF_DPA_L4_DST_PORT
- ROCKER_TLV_OF_DPA_L4_DST_PORT_MASK
- ROCKER_TLV_OF_DPA_L4_SRC_PORT
- ROCKER_TLV_OF_DPA_L4_SRC_PORT_MASK
- ROCKER_TLV_OF_DPA_MAX
- ROCKER_TLV_OF_DPA_NEW_IP_DSCP
- ROCKER_TLV_OF_DPA_NEW_QUEUE_ID
- ROCKER_TLV_OF_DPA_NEW_VLAN_ID
- ROCKER_TLV_OF_DPA_NEW_VLAN_PCP
- ROCKER_TLV_OF_DPA_OUT_PPORT
- ROCKER_TLV_OF_DPA_POP_VLAN
- ROCKER_TLV_OF_DPA_PRIORITY
- ROCKER_TLV_OF_DPA_QUEUE_ID_ACTION
- ROCKER_TLV_OF_DPA_SRC_ARP_IP
- ROCKER_TLV_OF_DPA_SRC_ARP_IP_MASK
- ROCKER_TLV_OF_DPA_SRC_IP
- ROCKER_TLV_OF_DPA_SRC_IPV6
- ROCKER_TLV_OF_DPA_SRC_IPV6_MASK
- ROCKER_TLV_OF_DPA_SRC_IP_MASK
- ROCKER_TLV_OF_DPA_SRC_MAC
- ROCKER_TLV_OF_DPA_SRC_MAC_MASK
- ROCKER_TLV_OF_DPA_TABLE_ID
- ROCKER_TLV_OF_DPA_TTL_CHECK
- ROCKER_TLV_OF_DPA_TUNNEL_ID
- ROCKER_TLV_OF_DPA_TUNNEL_LPORT
- ROCKER_TLV_OF_DPA_UNSPEC
- ROCKER_TLV_OF_DPA_VLAN_ID
- ROCKER_TLV_OF_DPA_VLAN_ID_MASK
- ROCKER_TLV_OF_DPA_VLAN_PCP
- ROCKER_TLV_OF_DPA_VLAN_PCP_ACTION
- ROCKER_TLV_OF_DPA_VLAN_PCP_MASK
- ROCKER_TLV_RX_CSUM
- ROCKER_TLV_RX_FLAGS
- ROCKER_TLV_RX_FRAG_ADDR
- ROCKER_TLV_RX_FRAG_LEN
- ROCKER_TLV_RX_FRAG_MAX_LEN
- ROCKER_TLV_RX_MAX
- ROCKER_TLV_RX_UNSPEC
- ROCKER_TLV_TX_FRAG
- ROCKER_TLV_TX_FRAGS
- ROCKER_TLV_TX_FRAG_ATTR_ADDR
- ROCKER_TLV_TX_FRAG_ATTR_LEN
- ROCKER_TLV_TX_FRAG_ATTR_MAX
- ROCKER_TLV_TX_FRAG_ATTR_UNSPEC
- ROCKER_TLV_TX_FRAG_MAX
- ROCKER_TLV_TX_FRAG_UNSPEC
- ROCKER_TLV_TX_L3_CSUM_OFF
- ROCKER_TLV_TX_MAX
- ROCKER_TLV_TX_OFFLOAD
- ROCKER_TLV_TX_TSO_HDR_LEN
- ROCKER_TLV_TX_TSO_MSS
- ROCKER_TLV_TX_UNSPEC
- ROCKER_TX_FRAGS_MAX
- ROCKER_TX_OFFLOAD_IP_CSUM
- ROCKER_TX_OFFLOAD_L3_CSUM
- ROCKER_TX_OFFLOAD_NONE
- ROCKER_TX_OFFLOAD_TCP_UDP_CSUM
- ROCKER_TX_OFFLOAD_TSO
- ROCKER_WORLD_OPS_LEN
- ROCKET_CLOSING_WAIT_INF
- ROCKET_CLOSING_WAIT_NONE
- ROCKET_DATE
- ROCKET_DEBUG_FLOW
- ROCKET_DEBUG_HANGUP
- ROCKET_DEBUG_INTR
- ROCKET_DEBUG_IO
- ROCKET_DEBUG_OPEN
- ROCKET_DEBUG_RECEIVE
- ROCKET_DEBUG_THROTTLE
- ROCKET_DEBUG_WAIT_UNTIL_SENT
- ROCKET_DEBUG_WRITE
- ROCKET_DISABLE_SIMUSAGE
- ROCKET_FLAGS
- ROCKET_FORCE_CD
- ROCKET_HUP_NOTIFY
- ROCKET_MODE_MASK
- ROCKET_MODE_RS232
- ROCKET_MODE_RS422
- ROCKET_MODE_RS485
- ROCKET_PARANOIA_CHECK
- ROCKET_PGRP_LOCKOUT
- ROCKET_RTS_TOGGLE
- ROCKET_SAK
- ROCKET_SESSION_LOCKOUT
- ROCKET_SOFT_FLOW
- ROCKET_SPD_HI
- ROCKET_SPD_MASK
- ROCKET_SPD_SHI
- ROCKET_SPD_VHI
- ROCKET_SPD_WARP
- ROCKET_SPLIT_TERMIOS
- ROCKET_TYPE_MODEM
- ROCKET_TYPE_MODEMII
- ROCKET_TYPE_MODEMIII
- ROCKET_TYPE_NORMAL
- ROCKET_TYPE_PC104
- ROCKET_USR_MASK
- ROCKET_VERSION
- ROCR_ROC
- ROCR_RXFU
- RODATA
- RODATA_MAIN
- ROF
- ROFDM0_AGCPARAMETER1
- ROFDM0_AGCPARAMETER2
- ROFDM0_AGCRSSITABLE
- ROFDM0_CCADROPTHRESHOLD
- ROFDM0_CCADROP_THRESHOLD
- ROFDM0_CFOANDDAGC
- ROFDM0_CFO_AND_DAGC
- ROFDM0_DFSREPORT
- ROFDM0_ECCATHRESHOLD
- ROFDM0_ECCA_THRESHOLD
- ROFDM0_FRAMESYNC
- ROFDM0_FRAME_SYNC
- ROFDM0_HTSTFAGC
- ROFDM0_LSTF
- ROFDM0_RXDETECTOR1
- ROFDM0_RXDETECTOR2
- ROFDM0_RXDETECTOR3
- ROFDM0_RXDETECTOR4
- ROFDM0_RXDSP
- ROFDM0_RXHPPARAMETER
- ROFDM0_RXHP_PARAMETER
- ROFDM0_RXIQEXTANTA
- ROFDM0_TRMUXPAR
- ROFDM0_TRSWISOLATION
- ROFDM0_TRXPATHENABLE
- ROFDM0_TXCOEFF1
- ROFDM0_TXCOEFF2
- ROFDM0_TXCOEFF3
- ROFDM0_TXCOEFF4
- ROFDM0_TXCOEFF5
- ROFDM0_TXCOEFF6
- ROFDM0_TXPSEUDONOISEWGT
- ROFDM0_TXPSEUDO_NOISE_WGT
- ROFDM0_XAAGCCORE1
- ROFDM0_XAAGCCORE2
- ROFDM0_XARXAFE
- ROFDM0_XARXIQIMBALANCE
- ROFDM0_XATXAFE
- ROFDM0_XATXIQIMBALANCE
- ROFDM0_XBAGCCORE1
- ROFDM0_XBAGCCORE2
- ROFDM0_XBRXAFE
- ROFDM0_XBRXIQIMBALANCE
- ROFDM0_XBTXAFE
- ROFDM0_XBTXIQIMBALANCE
- ROFDM0_XCAGCCORE1
- ROFDM0_XCAGCCORE2
- ROFDM0_XCRXAFE
- ROFDM0_XCRXIQIMBALANCE
- ROFDM0_XCRXIQIMBANLANCE
- ROFDM0_XCTXAFE
- ROFDM0_XCTXIQIMBALANCE
- ROFDM0_XDAGCCORE1
- ROFDM0_XDAGCCORE2
- ROFDM0_XDRXAFE
- ROFDM0_XDRXIQIMBALANCE
- ROFDM0_XDTXAFE
- ROFDM0_XDTXIQIMBALANCE
- ROFDM1_CF0
- ROFDM1_CFO
- ROFDM1_CFOTRACKING
- ROFDM1_CSI1
- ROFDM1_CSI2
- ROFDM1_INTFDET
- ROFDM1_INTF_DET
- ROFDM1_LSTF
- ROFDM1_PSEUDONOISESTATEAB
- ROFDM1_PSEUDONOISESTATECD
- ROFDM1_PSEUDO_NOISESTATEAB
- ROFDM1_PSEUDO_NOISESTATECD
- ROFDM1_RXPSEUDONOISEWGT
- ROFDM1_RX_PSEUDO_NOISE_WGT
- ROFDM1_SBD
- ROFDM1_TRXMESAURE1
- ROFDM1_TRXPATHENABLE
- ROFDMCCKEN
- ROFDM_AGCREPORT
- ROFDM_AGC_REPORT
- ROFDM_BWREPORT
- ROFDM_BW_REPORT
- ROFDM_LONGCFOAB
- ROFDM_LONGCFOCD
- ROFDM_LONG_CFOAB
- ROFDM_LONG_CFOCD
- ROFDM_PHYCOUNTER1
- ROFDM_PHYCOUNTER2
- ROFDM_PHYCOUNTER3
- ROFDM_PWMEASURE1
- ROFDM_PWMEASURE2
- ROFDM_PW_MEASURE1
- ROFDM_PW_MEASURE2
- ROFDM_RXEVMCSI
- ROFDM_RXSNR
- ROFDM_SHORTCFOAB
- ROFDM_SHORTCFOCD
- ROFDM_SHORT_CFOAB
- ROFDM_SHORT_CFOCD
- ROFDM_SIGREPORT
- ROFDM_SIG_REPORT
- ROFDM_TAILCF0AB
- ROFDM_TAILCF0CD
- ROFDM_TAILCFOAB
- ROFDM_TAILCFOCD
- ROFDM_TAIL_CFOAB
- ROFDM_TAIL_CFOCD
- ROFF
- ROHM_CHIP_TYPE_AMOUNT
- ROHM_CHIP_TYPE_BD70528
- ROHM_CHIP_TYPE_BD71837
- ROHM_CHIP_TYPE_BD71847
- ROHM_TS_ABS_X_MAX
- ROHM_TS_ABS_X_MIN
- ROHM_TS_ABS_Y_MAX
- ROHM_TS_ABS_Y_MIN
- ROHM_TS_DISPLACEMENT_MAX
- ROK_EXIT_LPM
- ROL
- ROL16
- ROL32
- ROLAND_SYNTH_PORT
- ROLDQ
- ROLDQo32
- ROLDSTACK
- ROLEX_EXTEN_FLAG
- ROLEX_POTENTIAL_KEY_FLAGS
- ROLE_INITIATOR
- ROLE_STOP_COMPLETE_EVENT_ID
- ROLE_SWAP_COMPELETE
- ROLE_TARGET
- ROLE_UNKNOWN
- ROLLOFF_20
- ROLLOFF_25
- ROLLOFF_35
- ROLLOFF_AUTO
- ROLLOFF_CONTROL
- ROLLOFF_STATUS
- ROLLOVER_HLEN
- ROM16
- ROM16_DESC
- ROM32
- ROMBASE
- ROMBMASK
- ROMBSBITS
- ROMBSIZE
- ROMCODEREADY_ER
- ROMCODESAVECONTEXT
- ROMCmd
- ROMControl
- ROMDEC
- ROME_SKIP_EVT_CC
- ROME_SKIP_EVT_NONE
- ROME_SKIP_EVT_VSE
- ROME_SKIP_EVT_VSE_CC
- ROMFH_BLK
- ROMFH_CHR
- ROMFH_DIR
- ROMFH_EXEC
- ROMFH_FIF
- ROMFH_HRD
- ROMFH_MASK
- ROMFH_PAD
- ROMFH_REG
- ROMFH_SCK
- ROMFH_SIZE
- ROMFH_SYM
- ROMFH_TYPE
- ROMFS_I
- ROMFS_MAGIC
- ROMFS_MAXFN
- ROMFS_MTD_READ
- ROMInterface
- ROMOE_DESC
- ROMPTR
- ROMSB_WORD0
- ROMSB_WORD1
- ROMSIGNATURE
- ROMTOP
- ROMUSB_GLB
- ROMUSB_ROM
- ROMVECTOR
- ROMWE_DESC
- ROM_ADR_CLEAR
- ROM_BASE_ADDR__BASE_ADDR_MASK
- ROM_BASE_ADDR__BASE_ADDR__MASK
- ROM_BASE_ADDR__BASE_ADDR__SHIFT
- ROM_BIOS_PAGE
- ROM_BUFF_SIZE
- ROM_CC_BIF_PINSTRAP__BIF_CLK_PM_EN_MASK
- ROM_CC_BIF_PINSTRAP__BIF_CLK_PM_EN__SHIFT
- ROM_CC_BIF_PINSTRAP__BIF_GEN3_DIS_A_MASK
- ROM_CC_BIF_PINSTRAP__BIF_GEN3_DIS_A__SHIFT
- ROM_CC_BIF_PINSTRAP__BIF_LC_TX_SWING_MASK
- ROM_CC_BIF_PINSTRAP__BIF_LC_TX_SWING__SHIFT
- ROM_CC_BIF_PINSTRAP__BIF_MEM_AP_SIZE_MASK
- ROM_CC_BIF_PINSTRAP__BIF_MEM_AP_SIZE__SHIFT
- ROM_CC_BIF_PINSTRAP__BIF_VGA_DIS_MASK
- ROM_CC_BIF_PINSTRAP__BIF_VGA_DIS__SHIFT
- ROM_CC_BIF_PINSTRAP__BIOS_ROM_EN_MASK
- ROM_CC_BIF_PINSTRAP__BIOS_ROM_EN__SHIFT
- ROM_CC_BIF_PINSTRAP__ROM_CONFIG_MASK
- ROM_CC_BIF_PINSTRAP__ROM_CONFIG__SHIFT
- ROM_CLUT
- ROM_CLUT0
- ROM_CLUT1
- ROM_CNTL__CLOCK_GATING_EN_MASK
- ROM_CNTL__CLOCK_GATING_EN__SHIFT
- ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME_MASK
- ROM_CNTL__CSB_ACTIVE_TO_SCK_HOLD_TIME__SHIFT
- ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME_MASK
- ROM_CNTL__CSB_ACTIVE_TO_SCK_SETUP_TIME__SHIFT
- ROM_CNTL__SCK_OVERWRITE_MASK
- ROM_CNTL__SCK_OVERWRITE__SHIFT
- ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK_MASK
- ROM_CNTL__SCK_PRESCALE_CRYSTAL_CLK__SHIFT
- ROM_CNTL__SCK_PRESCALE_REFCLK_MASK
- ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE_MASK
- ROM_CNTL__SCK_PRESCALE_REFCLK_OVERRIDE__SHIFT
- ROM_CNTL__SCK_PRESCALE_REFCLK__SHIFT
- ROM_CNTL__SPI_FAST_MODE_MASK
- ROM_CNTL__SPI_FAST_MODE_OVERRIDE_MASK
- ROM_CNTL__SPI_FAST_MODE_OVERRIDE__SHIFT
- ROM_CNTL__SPI_FAST_MODE__SHIFT
- ROM_CNTL__SPI_TIMING_RELAX_MASK
- ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE_MASK
- ROM_CNTL__SPI_TIMING_RELAX_OVERRIDE__SHIFT
- ROM_CNTL__SPI_TIMING_RELAX__SHIFT
- ROM_CODE_TYPE_BIOS
- ROM_CODE_TYPE_EFI
- ROM_CODE_TYPE_FCODE
- ROM_DATA__ROM_DATA_MASK
- ROM_DATA__ROM_DATA__SHIFT
- ROM_DEV_INIT_TIMEOUT
- ROM_DIR_OFFSET
- ROM_DLEN
- ROM_DRV_RESET_ACK_TIMEOUT
- ROM_FILE
- ROM_IH_SRC_ID_END
- ROM_IH_SRC_ID_START
- ROM_INDEX__ROM_INDEX_MASK
- ROM_INDEX__ROM_INDEX__SHIFT
- ROM_INT15_PHY_ADDR
- ROM_LOCK_DRIVER
- ROM_PHY_ADDR
- ROM_PHY_LEN
- ROM_PROBE_STEP_SIZE
- ROM_RESET
- ROM_SIGNATURE
- ROM_SIZE
- ROM_SMC_IND_DATA__SMC_IND_DATA_MASK
- ROM_SMC_IND_DATA__SMC_IND_DATA__SHIFT
- ROM_SMC_IND_INDEX__SMC_IND_ADDR_MASK
- ROM_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT
- ROM_START__ROM_START_MASK
- ROM_START__ROM_START__SHIFT
- ROM_STATUS__ROM_BUSY_MASK
- ROM_STATUS__ROM_BUSY__SHIFT
- ROM_SW_CNTL__COMMAND_SIZE_MASK
- ROM_SW_CNTL__COMMAND_SIZE__SHIFT
- ROM_SW_CNTL__DATA_SIZE_MASK
- ROM_SW_CNTL__DATA_SIZE__SHIFT
- ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE_MASK
- ROM_SW_CNTL__ROM_SW_RETURN_DATA_ENABLE__SHIFT
- ROM_SW_COMMAND__ROM_SW_ADDRESS_MASK
- ROM_SW_COMMAND__ROM_SW_ADDRESS__SHIFT
- ROM_SW_COMMAND__ROM_SW_INSTRUCTION_MASK
- ROM_SW_COMMAND__ROM_SW_INSTRUCTION__SHIFT
- ROM_SW_DATA_10__ROM_SW_DATA_MASK
- ROM_SW_DATA_10__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_11__ROM_SW_DATA_MASK
- ROM_SW_DATA_11__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_12__ROM_SW_DATA_MASK
- ROM_SW_DATA_12__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_13__ROM_SW_DATA_MASK
- ROM_SW_DATA_13__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_14__ROM_SW_DATA_MASK
- ROM_SW_DATA_14__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_15__ROM_SW_DATA_MASK
- ROM_SW_DATA_15__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_16__ROM_SW_DATA_MASK
- ROM_SW_DATA_16__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_17__ROM_SW_DATA_MASK
- ROM_SW_DATA_17__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_18__ROM_SW_DATA_MASK
- ROM_SW_DATA_18__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_19__ROM_SW_DATA_MASK
- ROM_SW_DATA_19__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_1__ROM_SW_DATA_MASK
- ROM_SW_DATA_1__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_20__ROM_SW_DATA_MASK
- ROM_SW_DATA_20__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_21__ROM_SW_DATA_MASK
- ROM_SW_DATA_21__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_22__ROM_SW_DATA_MASK
- ROM_SW_DATA_22__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_23__ROM_SW_DATA_MASK
- ROM_SW_DATA_23__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_24__ROM_SW_DATA_MASK
- ROM_SW_DATA_24__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_25__ROM_SW_DATA_MASK
- ROM_SW_DATA_25__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_26__ROM_SW_DATA_MASK
- ROM_SW_DATA_26__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_27__ROM_SW_DATA_MASK
- ROM_SW_DATA_27__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_28__ROM_SW_DATA_MASK
- ROM_SW_DATA_28__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_29__ROM_SW_DATA_MASK
- ROM_SW_DATA_29__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_2__ROM_SW_DATA_MASK
- ROM_SW_DATA_2__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_30__ROM_SW_DATA_MASK
- ROM_SW_DATA_30__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_31__ROM_SW_DATA_MASK
- ROM_SW_DATA_31__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_32__ROM_SW_DATA_MASK
- ROM_SW_DATA_32__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_33__ROM_SW_DATA_MASK
- ROM_SW_DATA_33__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_34__ROM_SW_DATA_MASK
- ROM_SW_DATA_34__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_35__ROM_SW_DATA_MASK
- ROM_SW_DATA_35__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_36__ROM_SW_DATA_MASK
- ROM_SW_DATA_36__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_37__ROM_SW_DATA_MASK
- ROM_SW_DATA_37__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_38__ROM_SW_DATA_MASK
- ROM_SW_DATA_38__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_39__ROM_SW_DATA_MASK
- ROM_SW_DATA_39__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_3__ROM_SW_DATA_MASK
- ROM_SW_DATA_3__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_40__ROM_SW_DATA_MASK
- ROM_SW_DATA_40__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_41__ROM_SW_DATA_MASK
- ROM_SW_DATA_41__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_42__ROM_SW_DATA_MASK
- ROM_SW_DATA_42__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_43__ROM_SW_DATA_MASK
- ROM_SW_DATA_43__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_44__ROM_SW_DATA_MASK
- ROM_SW_DATA_44__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_45__ROM_SW_DATA_MASK
- ROM_SW_DATA_45__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_46__ROM_SW_DATA_MASK
- ROM_SW_DATA_46__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_47__ROM_SW_DATA_MASK
- ROM_SW_DATA_47__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_48__ROM_SW_DATA_MASK
- ROM_SW_DATA_48__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_49__ROM_SW_DATA_MASK
- ROM_SW_DATA_49__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_4__ROM_SW_DATA_MASK
- ROM_SW_DATA_4__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_50__ROM_SW_DATA_MASK
- ROM_SW_DATA_50__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_51__ROM_SW_DATA_MASK
- ROM_SW_DATA_51__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_52__ROM_SW_DATA_MASK
- ROM_SW_DATA_52__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_53__ROM_SW_DATA_MASK
- ROM_SW_DATA_53__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_54__ROM_SW_DATA_MASK
- ROM_SW_DATA_54__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_55__ROM_SW_DATA_MASK
- ROM_SW_DATA_55__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_56__ROM_SW_DATA_MASK
- ROM_SW_DATA_56__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_57__ROM_SW_DATA_MASK
- ROM_SW_DATA_57__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_58__ROM_SW_DATA_MASK
- ROM_SW_DATA_58__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_59__ROM_SW_DATA_MASK
- ROM_SW_DATA_59__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_5__ROM_SW_DATA_MASK
- ROM_SW_DATA_5__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_60__ROM_SW_DATA_MASK
- ROM_SW_DATA_60__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_61__ROM_SW_DATA_MASK
- ROM_SW_DATA_61__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_62__ROM_SW_DATA_MASK
- ROM_SW_DATA_62__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_63__ROM_SW_DATA_MASK
- ROM_SW_DATA_63__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_64__ROM_SW_DATA_MASK
- ROM_SW_DATA_64__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_6__ROM_SW_DATA_MASK
- ROM_SW_DATA_6__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_7__ROM_SW_DATA_MASK
- ROM_SW_DATA_7__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_8__ROM_SW_DATA_MASK
- ROM_SW_DATA_8__ROM_SW_DATA__SHIFT
- ROM_SW_DATA_9__ROM_SW_DATA_MASK
- ROM_SW_DATA_9__ROM_SW_DATA__SHIFT
- ROM_SW_STATUS__ROM_SW_DONE_MASK
- ROM_SW_STATUS__ROM_SW_DONE__SHIFT
- ROM_TOKEN
- ROM_VERSION_MASK
- ROM_WRITE_ENB
- ROOM_LOW
- ROOM_NONE
- ROOM_NORMAL
- ROOM_POW_OFF
- ROOT
- ROOTCONTEXT_MNT
- ROOTCONTEXT_STR
- ROOTTREESIZE
- ROOT_CLOCK_RATE
- ROOT_ENTRY_NR
- ROOT_FREQ
- ROOT_HUB_PORT
- ROOT_I
- ROOT_IS_IDR
- ROOT_KEY
- ROOT_NID
- ROOT_OFFSET
- ROOT_PORT_INTR_ON_MESG_MASK
- ROOT_PORT_RESET_INTERRUPT
- ROOT_PORT_RESET_INTERRUPT_ENABLE
- ROOT_RDONLY
- ROOT_SIZE
- ROOT_TAG_SHIFT
- ROOT_TASK_GROUP_LOAD
- ROOT_USER
- ROP
- ROP3_P
- ROP3_PATCOPY
- ROP3_S
- ROP3_SRCCOPY
- ROP4_COPY
- ROP4_INVERT
- ROP4_REG
- ROPE0_CTL
- ROPE1_CTL
- ROPE2_CTL
- ROPE3_CTL
- ROPE4_CTL
- ROPE5_CTL
- ROPE6_CTL
- ROPE7_CTL
- ROPES_PER_IOC
- ROP_ALD
- ROP_AND
- ROP_AND_INVERTED
- ROP_AND_REVERSE
- ROP_BCAST
- ROP_CLEAR
- ROP_COPY
- ROP_COPY_INVERTED
- ROP_EN
- ROP_EQUIV
- ROP_INVERT
- ROP_NAND
- ROP_NOOP
- ROP_NOR
- ROP_OR
- ROP_OR_INVERTED
- ROP_OR_REVERSE
- ROP_P
- ROP_PWR
- ROP_S
- ROP_SET
- ROP_SHIFT
- ROP_SPS
- ROP_UNIT
- ROP_X
- ROP_XOR
- ROQ_END
- ROQ_IB1_START
- ROQ_IB2_START
- ROQ_PQ_IB_FLIP
- ROR
- ROR32
- RORQ
- RORc
- ROSE_ACCESS_BARRED
- ROSE_ADDR_LEN
- ROSE_CALL_ACCEPTED
- ROSE_CALL_REQUEST
- ROSE_CALL_REQ_ADDR_LEN_OFF
- ROSE_CALL_REQ_ADDR_LEN_VAL
- ROSE_CALL_REQ_DEST_ADDR_OFF
- ROSE_CALL_REQ_FACILITIES_OFF
- ROSE_CALL_REQ_SRC_ADDR_OFF
- ROSE_CLEAR_CONFIRMATION
- ROSE_CLEAR_REQUEST
- ROSE_COND_ACK_PENDING
- ROSE_COND_OWN_RX_BUSY
- ROSE_COND_PEER_RX_BUSY
- ROSE_DATA
- ROSE_DEFAULT_FAIL_TIMEOUT
- ROSE_DEFAULT_HB
- ROSE_DEFAULT_IDLE
- ROSE_DEFAULT_MAXVC
- ROSE_DEFAULT_ROUTING
- ROSE_DEFAULT_T0
- ROSE_DEFAULT_T1
- ROSE_DEFAULT_T2
- ROSE_DEFAULT_T3
- ROSE_DEFAULT_WINDOW_SIZE
- ROSE_DEFER
- ROSE_DIAGNOSTIC
- ROSE_DTE_ORIGINATED
- ROSE_D_BIT
- ROSE_GFI
- ROSE_HOLDBACK
- ROSE_IDLE
- ROSE_ILLEGAL
- ROSE_INTERRUPT
- ROSE_INTERRUPT_CONFIRMATION
- ROSE_INVALID_FACILITY
- ROSE_KERNEL_H
- ROSE_LOCAL_PROCEDURE
- ROSE_LOOPBACK_LIMIT
- ROSE_MAX_DIGIS
- ROSE_MAX_PACKET_SIZE
- ROSE_MIN_LEN
- ROSE_MODULUS
- ROSE_MTU
- ROSE_M_BIT
- ROSE_NETWORK_CONGESTION
- ROSE_NOT_OBTAINABLE
- ROSE_NUMBER_BUSY
- ROSE_OUT_OF_ORDER
- ROSE_PACLEN
- ROSE_QBITINCL
- ROSE_Q_BIT
- ROSE_REGISTRATION_CONFIRMATION
- ROSE_REGISTRATION_REQUEST
- ROSE_REJ
- ROSE_REMOTE_PROCEDURE
- ROSE_RESET_CONFIRMATION
- ROSE_RESET_REQUEST
- ROSE_RESTART_CONFIRMATION
- ROSE_RESTART_REQUEST
- ROSE_RNR
- ROSE_RR
- ROSE_SHIP_ABSENT
- ROSE_STATE_0
- ROSE_STATE_1
- ROSE_STATE_2
- ROSE_STATE_3
- ROSE_STATE_4
- ROSE_STATE_5
- ROSE_T1
- ROSE_T2
- ROSE_T3
- ROSS_604_REV_CDE
- ROSS_604_REV_F
- ROSS_605
- ROSS_605_REV_B
- ROTARYA
- ROTARYB
- ROTATE
- ROTATED_MICRO_TILING
- ROTATE_0
- ROTATE_0_DEGREES
- ROTATE_180_DEGREES
- ROTATE_270_DEGREES
- ROTATE_90
- ROTATE_90_DEGREES
- ROTATE_ANY
- ROTATE_ARGS
- ROTATE_COMPRESSED
- ROTATE_NONE
- ROTATE_REG
- ROTATE_STATE
- ROTATION_ANGLE
- ROTATION_ANGLE_0
- ROTATION_ANGLE_180
- ROTATION_ANGLE_270
- ROTATION_ANGLE_90
- ROTATION_ANGLE_COUNT
- ROTATOR_AUTOSUSPEND_DELAY
- ROTENC_BINARY
- ROTENC_GRAY
- ROTL128
- ROT_AHB_CLK
- ROT_AHB_RESET
- ROT_ALIGN
- ROT_AXI_CLK
- ROT_AXI_RESET
- ROT_CLK
- ROT_CONFIG
- ROT_CONFIG_IRQ
- ROT_CONTROL
- ROT_CONTROL_FLIP_HORIZONTAL
- ROT_CONTROL_FLIP_MASK
- ROT_CONTROL_FLIP_VERTICAL
- ROT_CONTROL_FMT_MASK
- ROT_CONTROL_FMT_RGB888
- ROT_CONTROL_FMT_YCBCR420_2P
- ROT_CONTROL_PATTERN_WRITE
- ROT_CONTROL_ROT_180
- ROT_CONTROL_ROT_270
- ROT_CONTROL_ROT_90
- ROT_CONTROL_ROT_MASK
- ROT_CONTROL_START
- ROT_CROP_POS_X
- ROT_CROP_POS_Y
- ROT_DST_BUF_ADDR
- ROT_DST_BUF_SIZE
- ROT_DST_CROP_POS
- ROT_FREQ_CTL
- ROT_GET_BUF_SIZE_H
- ROT_GET_BUF_SIZE_W
- ROT_IRQ_STATUS_COMPLETE
- ROT_IRQ_STATUS_ILLEGAL
- ROT_MAX
- ROT_MIN
- ROT_RESET
- ROT_SET_BUF_SIZE_H
- ROT_SET_BUF_SIZE_W
- ROT_SRC
- ROT_SRC_BUF_ADDR
- ROT_SRC_BUF_SIZE
- ROT_SRC_CROP_POS
- ROT_SRC_CROP_SIZE
- ROT_SRC_CROP_SIZE_H
- ROT_SRC_CROP_SIZE_W
- ROT_STATUS
- ROT_STATUS_IRQ
- ROT_STATUS_IRQ_PENDING
- ROT_STATUS_IRQ_VAL_COMPLETE
- ROT_STATUS_IRQ_VAL_ILLEGAL
- ROUGH_MAX_L2_L3_HDR_SZ
- ROUND
- ROUND1
- ROUND2
- ROUND3
- ROUNDING
- ROUNDMINUS
- ROUNDNEAREST
- ROUNDPLUS
- ROUNDS
- ROUNDTOEVEN
- ROUNDTOODD
- ROUNDUP
- ROUNDUP128
- ROUNDUP16
- ROUNDUP4
- ROUNDUP64
- ROUNDUP8
- ROUNDUP_LOG2
- ROUNDZERO
- ROUND_4M
- ROUND_BLOCK
- ROUND_BY_HALF
- ROUND_DOUBLE
- ROUND_DOWN
- ROUND_DOWN_TO
- ROUND_DOWN_TO_PAGE
- ROUND_EN
- ROUND_EXTENDED
- ROUND_F1
- ROUND_F2
- ROUND_F3
- ROUND_NEAREST
- ROUND_ON
- ROUND_SHIFT
- ROUND_SINGLE
- ROUND_TO_MINUS_INFINITY
- ROUND_TO_NEAREST
- ROUND_TO_PLUS_INFINITY
- ROUND_TO_RANGE
- ROUND_TO_ZERO
- ROUND_TRUNCATE
- ROUND_UP
- ROUND_UP_EXP_FOR_FLICKER
- ROUND_UP_TO
- ROUND_UP_TO_PAGE
- ROUT1
- ROUT1V_ENABLE_RZC
- ROUT1V_RHP_VOL
- ROUT1V_RLHP_BOTH
- ROUT2
- ROUT3
- ROUT4
- ROUT5
- ROUT6
- ROUTE4_APPLY_RESULT
- ROUTE4_FAILURE
- ROUTER_COMPONENT_INDEX
- ROUTER_I2C_EXTENDER_CNTL_ENUM_ID1
- ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL
- ROUTER_OBJECT_ID_NONE
- ROUTER_VECTOR_VERS
- ROUTE_BASE
- ROUTE_MASK
- ROUTE_ON
- ROUTE_SIZE
- ROUTE_STRING_MASK
- ROUTING
- ROUTING1_CENTER_LFE
- ROUTING1_FRONT
- ROUTING1_NULL
- ROUTING1_REAR
- ROUTING2_CENTER_LFE_MASK
- ROUTING2_FRONT_MASK
- ROUTING2_REAR_MASK
- ROUTING_CENTER_LFE
- ROUTING_ENTRY1
- ROUTING_ENTRY2
- ROUTING_FRONT_LEFT
- ROUTING_FRONT_RIGHT
- ROUTING_INDEX_SEG_NUM
- ROUTING_REAR_LEFT
- ROUTING_REAR_RIGHT
- ROUTING_WORDS_SEG_NUM
- ROVER_INC_ON_VISIT
- ROVER_INC_PARENT_ON_LOOP
- ROVER_NO_OP
- ROVF
- ROVFLEN
- ROVR
- ROVRN
- ROVR_ADDR
- ROWINDEX_S
- ROWINDEX_V
- ROWSIZE_MASK
- ROWSIZE_SHIFT
- ROW_ADDER
- ROW_ADDR
- ROW_ADDR_CHIP_SEL_MASK
- ROW_ADDR_CHIP_SEL_RB_MASK
- ROW_ADDR_CHIP_SEL_RB_SHIFT
- ROW_ADDR_CHIP_SEL_SHIFT
- ROW_ADDR_MASK
- ROW_ADDR_SHIFT
- ROW_B0_BASE
- ROW_B10_BASE
- ROW_B11_BASE
- ROW_B12_BASE
- ROW_B13_BASE
- ROW_B14_BASE
- ROW_B15_BASE
- ROW_B16_BASE
- ROW_B17_BASE
- ROW_B1_BASE
- ROW_B2_BASE
- ROW_B3_BASE
- ROW_B4_BASE
- ROW_B5_BASE
- ROW_B6_BASE
- ROW_B7_BASE
- ROW_B8_BASE
- ROW_B9_BASE
- ROW_INDEX_10BPP
- ROW_INDEX_12BPP
- ROW_INDEX_15BPP
- ROW_INDEX_6BPP
- ROW_INDEX_8BPP
- ROW_INDEX_BPP
- ROW_MAX_VAL_MASK
- ROW_SHIFT
- ROW_SIZE
- ROW_SIZE_MASK
- ROW_SIZE_SHIFT
- ROW_TILING
- ROW_X_COL
- RO_AFTER_INIT_DATA
- RO_DATA
- RO_DATA_SECTION
- RO_RENDERSTATE
- RO_SENSOR_TEMPLATE
- RP2_ASIC_CFG
- RP2_ASIC_IRQ
- RP2_ASIC_IRQ_EN_m
- RP2_ASIC_OFFSET
- RP2_ASIC_SPACING
- RP2_BAUD
- RP2_CHAN_STAT
- RP2_CHAN_STAT_CD_CHANGED_m
- RP2_CHAN_STAT_CTS_CHANGED_m
- RP2_CHAN_STAT_CTS_m
- RP2_CHAN_STAT_DCD_m
- RP2_CHAN_STAT_DSR_CHANGED_m
- RP2_CHAN_STAT_DSR_m
- RP2_CHAN_STAT_MS_CHANGED_MASK
- RP2_CHAN_STAT_OVERRUN_m
- RP2_CHAN_STAT_RI_CHANGED_m
- RP2_CHAN_STAT_RI_m
- RP2_CHAN_STAT_RXDATA_m
- RP2_CHAN_STAT_TXEMPTY_m
- RP2_CH_IRQ_MASK
- RP2_CH_IRQ_STAT
- RP2_CLK_PRESCALER
- RP2_DATA_BYTE
- RP2_DATA_BYTE_BREAK_m
- RP2_DATA_BYTE_ERR_FRAMING_m
- RP2_DATA_BYTE_ERR_OVERRUN_m
- RP2_DATA_BYTE_ERR_PARITY_m
- RP2_DATA_BYTE_EXCEPTION_MASK
- RP2_DATA_DWORD
- RP2_DUMMY_READ
- RP2_FPGA_CTL0
- RP2_FPGA_CTL1
- RP2_FW_NAME
- RP2_GLOBAL_CMD
- RP2_IRQ_MASK
- RP2_IRQ_MASK_EN_m
- RP2_IRQ_STATUS
- RP2_PORT_BASE
- RP2_PORT_SPACING
- RP2_RX_FIFO
- RP2_RX_FIFO_COUNT
- RP2_RX_FIFO_dis
- RP2_RX_FIFO_ena
- RP2_RX_SWFLOW
- RP2_RX_SWFLOW_dis
- RP2_RX_SWFLOW_ena
- RP2_TXRX_CTL
- RP2_TXRX_CTL_BREAK_m
- RP2_TXRX_CTL_CMSPAR_m
- RP2_TXRX_CTL_CTSFLOW_m
- RP2_TXRX_CTL_DSRFLOW_m
- RP2_TXRX_CTL_DTRFLOW_m
- RP2_TXRX_CTL_DTR_m
- RP2_TXRX_CTL_LOOP_m
- RP2_TXRX_CTL_MSRIRQ_m
- RP2_TXRX_CTL_PARENB_m
- RP2_TXRX_CTL_RTSFLOW_m
- RP2_TXRX_CTL_RTS_m
- RP2_TXRX_CTL_RXIRQ_m
- RP2_TXRX_CTL_RX_EN_m
- RP2_TXRX_CTL_RX_TRIG_1
- RP2_TXRX_CTL_RX_TRIG_256
- RP2_TXRX_CTL_RX_TRIG_448
- RP2_TXRX_CTL_RX_TRIG_m
- RP2_TXRX_CTL_RX_TRIG_s
- RP2_TXRX_CTL_TXIRQ_m
- RP2_TXRX_CTL_TX_EN_m
- RP2_TXRX_CTL_TX_TRIG_m
- RP2_TXRX_CTL_TX_TRIG_s
- RP2_TXRX_CTL_nPARODD_m
- RP2_TX_FIFO_COUNT
- RP2_TX_SWFLOW
- RP2_TX_SWFLOW_dis
- RP2_TX_SWFLOW_ena
- RP2_UART_CTL
- RP2_UART_CTL_DATABITS_5
- RP2_UART_CTL_DATABITS_6
- RP2_UART_CTL_DATABITS_7
- RP2_UART_CTL_DATABITS_8
- RP2_UART_CTL_DATABITS_m
- RP2_UART_CTL_DATABITS_s
- RP2_UART_CTL_FLUSH_RX_m
- RP2_UART_CTL_FLUSH_TX_m
- RP2_UART_CTL_MODE_m
- RP2_UART_CTL_MODE_rs232
- RP2_UART_CTL_MODE_s
- RP2_UART_CTL_RESET_CH_m
- RP2_UART_CTL_STOPBITS_m
- RP2_UART_CTL_XMIT_EN_m
- RP2_UCODE_BASE
- RP2_UCODE_BYTES
- RP2_UCODE_SPACING
- RP5C01_10_DAY
- RP5C01_10_HOUR
- RP5C01_10_HOUR_AM
- RP5C01_10_HOUR_PM
- RP5C01_10_MINUTE
- RP5C01_10_MONTH
- RP5C01_10_SECOND
- RP5C01_10_YEAR
- RP5C01_12_24_SELECT
- RP5C01_12_24_SELECT_12
- RP5C01_12_24_SELECT_24
- RP5C01_1_DAY
- RP5C01_1_HOUR
- RP5C01_1_MINUTE
- RP5C01_1_MONTH
- RP5C01_1_SECOND
- RP5C01_1_YEAR
- RP5C01_DAY_OF_WEEK
- RP5C01_LEAP_YEAR
- RP5C01_MODE
- RP5C01_MODE_ALARM_EN
- RP5C01_MODE_MODE00
- RP5C01_MODE_MODE01
- RP5C01_MODE_MODE_MASK
- RP5C01_MODE_RAM_BLOCK10
- RP5C01_MODE_RAM_BLOCK11
- RP5C01_MODE_TIMER_EN
- RP5C01_RESET
- RP5C01_RESET_16HZ_PULSE
- RP5C01_RESET_1HZ_PULSE
- RP5C01_RESET_ALARM
- RP5C01_RESET_SECOND
- RP5C01_TEST
- RPA
- RPA14R
- RPA15R
- RPABLK
- RPAC
- RPADIR
- RPADIR_BIT
- RPADIR_PADR
- RPADIR_PADS
- RPA_CMD
- RPA_CREDIT_ERR
- RPA_ECC_DB_ERR
- RPA_ECC_SG_ERR
- RPA_FLUSH_REQUEST
- RPA_RSP_SIZE
- RPA_SM_ERR_ALARM
- RPB0R
- RPB10R
- RPB14R
- RPB15R
- RPB1R
- RPB2R
- RPB3R
- RPB5R
- RPB6R
- RPB7R
- RPB8R
- RPB9R
- RPBBLK
- RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM_MASK
- RPB_ARB_CNTL2__ATC_PAGE_SWITCH_NUM__SHIFT
- RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM_MASK
- RPB_ARB_CNTL2__ATOMIC_SWITCH_NUM__SHIFT
- RPB_ARB_CNTL2__P2P_SWITCH_NUM_MASK
- RPB_ARB_CNTL2__P2P_SWITCH_NUM__SHIFT
- RPB_ARB_CNTL__ARB_MODE_MASK
- RPB_ARB_CNTL__ARB_MODE__SHIFT
- RPB_ARB_CNTL__ATC_TR_SWITCH_NUM_MASK
- RPB_ARB_CNTL__ATC_TR_SWITCH_NUM__SHIFT
- RPB_ARB_CNTL__RD_SWITCH_NUM_MASK
- RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT
- RPB_ARB_CNTL__SWITCH_NUM_MODE_MASK
- RPB_ARB_CNTL__SWITCH_NUM_MODE__SHIFT
- RPB_ARB_CNTL__WR_SWITCH_NUM_MASK
- RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT
- RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE_MASK
- RPB_ATS_CNTL2__INVAL_COM_ROUTING_CODE__SHIFT
- RPB_ATS_CNTL2__PAGE_REQ_CMD_MASK
- RPB_ATS_CNTL2__PAGE_REQ_CMD__SHIFT
- RPB_ATS_CNTL2__PAGE_ROUTING_CODE_MASK
- RPB_ATS_CNTL2__PAGE_ROUTING_CODE__SHIFT
- RPB_ATS_CNTL2__TRANS_CMD_MASK
- RPB_ATS_CNTL2__TRANS_CMD__SHIFT
- RPB_ATS_CNTL2__VENDOR_ID_MASK
- RPB_ATS_CNTL2__VENDOR_ID__SHIFT
- RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM_MASK
- RPB_ATS_CNTL__ATCPAGE_SWITCH_NUM__SHIFT
- RPB_ATS_CNTL__ATCTR_SWITCH_NUM_MASK
- RPB_ATS_CNTL__ATCTR_SWITCH_NUM__SHIFT
- RPB_ATS_CNTL__INVAL_COM_CMD_MASK
- RPB_ATS_CNTL__INVAL_COM_CMD__SHIFT
- RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE_MASK
- RPB_ATS_CNTL__PAGE_MIN_LATENCY_ENABLE__SHIFT
- RPB_ATS_CNTL__SWITCH_THRESHOLD_MASK
- RPB_ATS_CNTL__SWITCH_THRESHOLD__SHIFT
- RPB_ATS_CNTL__TIME_SLICE_MASK
- RPB_ATS_CNTL__TIME_SLICE__SHIFT
- RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE_MASK
- RPB_ATS_CNTL__TR_MIN_LATENCY_ENABLE__SHIFT
- RPB_ATS_CNTL__WR_AT_MASK
- RPB_ATS_CNTL__WR_AT__SHIFT
- RPB_BIF_CNTL2__NBIF_HST_COMPCLKCTL_EN_MASK
- RPB_BIF_CNTL2__NBIF_HST_COMPCLKCTL_EN__SHIFT
- RPB_BIF_CNTL__ARB_MODE_MASK
- RPB_BIF_CNTL__ARB_MODE__SHIFT
- RPB_BIF_CNTL__DRAIN_VC_NUM_MASK
- RPB_BIF_CNTL__DRAIN_VC_NUM__SHIFT
- RPB_BIF_CNTL__NBIF_DMA_ORIGCLKCTL_EN_MASK
- RPB_BIF_CNTL__NBIF_DMA_ORIGCLKCTL_EN__SHIFT
- RPB_BIF_CNTL__PAGE_PRI_EN_MASK
- RPB_BIF_CNTL__PAGE_PRI_EN__SHIFT
- RPB_BIF_CNTL__PARITY_CHECK_EN_MASK
- RPB_BIF_CNTL__PARITY_CHECK_EN__SHIFT
- RPB_BIF_CNTL__SWITCH_ENABLE_MASK
- RPB_BIF_CNTL__SWITCH_ENABLE__SHIFT
- RPB_BIF_CNTL__SWITCH_THRESHOLD_MASK
- RPB_BIF_CNTL__SWITCH_THRESHOLD__SHIFT
- RPB_BIF_CNTL__TR_PRI_EN_MASK
- RPB_BIF_CNTL__TR_PRI_EN__SHIFT
- RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE_MASK
- RPB_BIF_CNTL__VC0_CHAINED_OVERRIDE__SHIFT
- RPB_BIF_CNTL__VC0_SWITCH_NUM_MASK
- RPB_BIF_CNTL__VC0_SWITCH_NUM__SHIFT
- RPB_BIF_CNTL__VC1_SWITCH_NUM_MASK
- RPB_BIF_CNTL__VC1_SWITCH_NUM__SHIFT
- RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL_MASK
- RPB_BLOCKLEVEL_CONF__ATC_INV_BLOCKLEVEL__SHIFT
- RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL_MASK
- RPB_BLOCKLEVEL_CONF__ATC_PAGE_BLOCKLEVEL__SHIFT
- RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL_MASK
- RPB_BLOCKLEVEL_CONF__ATC_TR_BLOCKLEVEL__SHIFT
- RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN_MASK
- RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_EN__SHIFT
- RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE_MASK
- RPB_BLOCKLEVEL_CONF__ATOMIC_BLOCKLEVEL_OVERRIDE__SHIFT
- RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN_MASK
- RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_EN__SHIFT
- RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE_MASK
- RPB_BLOCKLEVEL_CONF__IO_RD_BLOCKLEVEL_OVERRIDE__SHIFT
- RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN_MASK
- RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_EN__SHIFT
- RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE_MASK
- RPB_BLOCKLEVEL_CONF__IO_WR_BLOCKLEVEL_OVERRIDE__SHIFT
- RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN_MASK
- RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_EN__SHIFT
- RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE_MASK
- RPB_BLOCKLEVEL_CONF__XPB_BLOCKLEVEL_OVERRIDE__SHIFT
- RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK
- RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT
- RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK
- RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT
- RPB_CID_QUEUE_EX__OFFSET_MASK
- RPB_CID_QUEUE_EX__OFFSET__SHIFT
- RPB_CID_QUEUE_EX__START_MASK
- RPB_CID_QUEUE_EX__START__SHIFT
- RPB_CID_QUEUE_RD__CLIENT_ID_HIGH_MASK
- RPB_CID_QUEUE_RD__CLIENT_ID_HIGH__SHIFT
- RPB_CID_QUEUE_RD__CLIENT_ID_LOW_MASK
- RPB_CID_QUEUE_RD__CLIENT_ID_LOW__SHIFT
- RPB_CID_QUEUE_RD__READ_QUEUE_MASK
- RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT
- RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK
- RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT
- RPB_CID_QUEUE_WR__CLIENT_ID_HIGH_MASK
- RPB_CID_QUEUE_WR__CLIENT_ID_HIGH__SHIFT
- RPB_CID_QUEUE_WR__CLIENT_ID_LOW_MASK
- RPB_CID_QUEUE_WR__CLIENT_ID_LOW__SHIFT
- RPB_CID_QUEUE_WR__READ_QUEUE_MASK
- RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT
- RPB_CID_QUEUE_WR__UPDATE_MASK
- RPB_CID_QUEUE_WR__UPDATE_MODE_MASK
- RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT
- RPB_CID_QUEUE_WR__UPDATE__SHIFT
- RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK
- RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT
- RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN_MASK
- RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_BREAK_EN__SHIFT
- RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER_MASK
- RPB_DEINTRLV_COMBINE_CNTL__WC_CHAINED_FLUSH_TIMER__SHIFT
- RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE_MASK
- RPB_DEINTRLV_COMBINE_CNTL__WC_HANDLE_CHECK_DISABLE__SHIFT
- RPB_DEINTRLV_COMBINE_CNTL__XPB_WRREQ_CRD_MASK
- RPB_DEINTRLV_COMBINE_CNTL__XPB_WRREQ_CRD__SHIFT
- RPB_DF_SDPPORT_CNTL__DF_DATA_CRD_MASK
- RPB_DF_SDPPORT_CNTL__DF_DATA_CRD__SHIFT
- RPB_DF_SDPPORT_CNTL__DF_HALT_THRESHOLD_MASK
- RPB_DF_SDPPORT_CNTL__DF_HALT_THRESHOLD__SHIFT
- RPB_DF_SDPPORT_CNTL__DF_REQ_CRD_MASK
- RPB_DF_SDPPORT_CNTL__DF_REQ_CRD__SHIFT
- RPB_EA_QUEUE_WR__EA_NUMBER_MASK
- RPB_EA_QUEUE_WR__EA_NUMBER__SHIFT
- RPB_EA_QUEUE_WR__READ_QUEUE_MASK
- RPB_EA_QUEUE_WR__READ_QUEUE__SHIFT
- RPB_EA_QUEUE_WR__UPDATE_MASK
- RPB_EA_QUEUE_WR__UPDATE__SHIFT
- RPB_EA_QUEUE_WR__WRITE_QUEUE_MASK
- RPB_EA_QUEUE_WR__WRITE_QUEUE__SHIFT
- RPB_EFF_CNTL__RD_LAZY_TIMER_MASK
- RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT
- RPB_EFF_CNTL__WR_LAZY_TIMER_MASK
- RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT
- RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_RDRSP_CRD_MASK
- RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_RDRSP_CRD__SHIFT
- RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_WRRSP_CRD_MASK
- RPB_NBIF_SDPPORT_CNTL__NBIF_DMA_WRRSP_CRD__SHIFT
- RPB_NBIF_SDPPORT_CNTL__NBIF_HST_DATA_CRD_MASK
- RPB_NBIF_SDPPORT_CNTL__NBIF_HST_DATA_CRD__SHIFT
- RPB_NBIF_SDPPORT_CNTL__NBIF_HST_REQ_CRD_MASK
- RPB_NBIF_SDPPORT_CNTL__NBIF_HST_REQ_CRD__SHIFT
- RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN_MASK
- RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_EN__SHIFT
- RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE_MASK
- RPB_PASSPW_CONF__ATC_PAGE_PASSPW_OVERRIDE__SHIFT
- RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN_MASK
- RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_EN__SHIFT
- RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE_MASK
- RPB_PASSPW_CONF__ATC_RSPPASSPW_OVERRIDE__SHIFT
- RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN_MASK
- RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_EN__SHIFT
- RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE_MASK
- RPB_PASSPW_CONF__ATC_TR_PASSPW_OVERRIDE__SHIFT
- RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE_MASK
- RPB_PASSPW_CONF__ATOMIC_PASSPW_OVERRIDE__SHIFT
- RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE_MASK
- RPB_PASSPW_CONF__ATOMIC_RSPPASSPW_OVERRIDE__SHIFT
- RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN_MASK
- RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_EN__SHIFT
- RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE_MASK
- RPB_PASSPW_CONF__RDRSP_PASSPW_OVERRIDE__SHIFT
- RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE_MASK
- RPB_PASSPW_CONF__RD_PASSPW_OVERRIDE__SHIFT
- RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE_MASK
- RPB_PASSPW_CONF__RD_RSPPASSPW_OVERRIDE__SHIFT
- RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN_MASK
- RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_EN__SHIFT
- RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE_MASK
- RPB_PASSPW_CONF__WRRSP_PASSPW_OVERRIDE__SHIFT
- RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE_MASK
- RPB_PASSPW_CONF__WR_PASSPW_OVERRIDE__SHIFT
- RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE_MASK
- RPB_PASSPW_CONF__WR_RSPPASSPW_OVERRIDE__SHIFT
- RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE_MASK
- RPB_PASSPW_CONF__XPB_PASSPW_OVERRIDE__SHIFT
- RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE_MASK
- RPB_PASSPW_CONF__XPB_RSPPASSPW_OVERRIDE__SHIFT
- RPB_PERFCOUNTER0_CFG__CLEAR_MASK
- RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT
- RPB_PERFCOUNTER0_CFG__ENABLE_MASK
- RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT
- RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK
- RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT
- RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK
- RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT
- RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK
- RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT
- RPB_PERFCOUNTER1_CFG__CLEAR_MASK
- RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT
- RPB_PERFCOUNTER1_CFG__ENABLE_MASK
- RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT
- RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK
- RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT
- RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK
- RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT
- RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK
- RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT
- RPB_PERFCOUNTER2_CFG__CLEAR_MASK
- RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT
- RPB_PERFCOUNTER2_CFG__ENABLE_MASK
- RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT
- RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK
- RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT
- RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK
- RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT
- RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK
- RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT
- RPB_PERFCOUNTER3_CFG__CLEAR_MASK
- RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT
- RPB_PERFCOUNTER3_CFG__ENABLE_MASK
- RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT
- RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK
- RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT
- RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK
- RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT
- RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK
- RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT
- RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK
- RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT
- RPB_PERFCOUNTER_HI__COUNTER_HI_MASK
- RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT
- RPB_PERFCOUNTER_LO__COUNTER_LO_MASK
- RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT
- RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK
- RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT
- RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK
- RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT
- RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK
- RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT
- RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK
- RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT
- RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK
- RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT
- RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK
- RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT
- RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK
- RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT
- RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK
- RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT
- RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK
- RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT
- RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK
- RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT
- RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK
- RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT
- RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK
- RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT
- RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK
- RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT
- RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK
- RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT
- RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK
- RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT
- RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK
- RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT
- RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK
- RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT
- RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK
- RPB_RD_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT
- RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK
- RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT
- RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK
- RPB_RD_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT
- RPB_RD_QUEUE_CNTL__ARB_MODE_MASK
- RPB_RD_QUEUE_CNTL__ARB_MODE__SHIFT
- RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK
- RPB_RD_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT
- RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW_MASK
- RPB_RD_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT
- RPB_RD_QUEUE_CNTL__Q4_SHARED_MASK
- RPB_RD_QUEUE_CNTL__Q4_SHARED__SHIFT
- RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK
- RPB_RD_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT
- RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK
- RPB_RD_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT
- RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW_MASK
- RPB_RD_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT
- RPB_RD_QUEUE_CNTL__Q5_SHARED_MASK
- RPB_RD_QUEUE_CNTL__Q5_SHARED__SHIFT
- RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK
- RPB_RD_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT
- RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK
- RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT
- RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK
- RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT
- RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK
- RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT
- RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK
- RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT
- RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE_MASK
- RPB_RD_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT
- RPB_RD_SWITCH_CNTL__WEIGHT_ADJUST_STEP_MASK
- RPB_RD_SWITCH_CNTL__WEIGHT_ADJUST_STEP__SHIFT
- RPB_RD_SWITCH_CNTL__WORKLOAD_ADJUST_EN_MASK
- RPB_RD_SWITCH_CNTL__WORKLOAD_ADJUST_EN__SHIFT
- RPB_REG_DBG_DWORD_ENABLE
- RPB_REG_DBG_FORCE_FRAME
- RPB_REG_DBG_FORCE_VALID
- RPB_REG_DBG_SELECT
- RPB_REG_DBG_SHIFT
- RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV_MASK
- RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKENRCV__SHIFT
- RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN_MASK
- RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPCKEN__SHIFT
- RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV_MASK
- RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKENRCV__SHIFT
- RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN_MASK
- RPB_SDPPORT_CNTL__DF_SDPVDCI_RDRSPDATACKEN__SHIFT
- RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV_MASK
- RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKENRCV__SHIFT
- RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN_MASK
- RPB_SDPPORT_CNTL__DF_SDPVDCI_WRRSPCKEN__SHIFT
- RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE_MASK
- RPB_SDPPORT_CNTL__NBIF_DMA_CFG_MODE__SHIFT
- RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS_MASK
- RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_DISRUPT_FULLDIS__SHIFT
- RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT_MASK
- RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_REISSUE_CREDIT__SHIFT
- RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER_MASK
- RPB_SDPPORT_CNTL__NBIF_DMA_ENABLE_SATURATE_COUNTER__SHIFT
- RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD_MASK
- RPB_SDPPORT_CNTL__NBIF_DMA_HALT_THRESHOLD__SHIFT
- RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE_MASK
- RPB_SDPPORT_CNTL__NBIF_DMA_SELF_ACTIVATE__SHIFT
- RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE_MASK
- RPB_SDPPORT_CNTL__NBIF_HST_CFG_MODE__SHIFT
- RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS_MASK
- RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_DISRUPT_FULLDIS__SHIFT
- RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT_MASK
- RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_REISSUE_CREDIT__SHIFT
- RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER_MASK
- RPB_SDPPORT_CNTL__NBIF_HST_ENABLE_SATURATE_COUNTER__SHIFT
- RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD_MASK
- RPB_SDPPORT_CNTL__NBIF_HST_HALT_THRESHOLD__SHIFT
- RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE_MASK
- RPB_SDPPORT_CNTL__NBIF_HST_PASSIVE_MODE__SHIFT
- RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK_MASK
- RPB_SDPPORT_CNTL__NBIF_HST_QUICK_COMACK__SHIFT
- RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE_MASK
- RPB_SDPPORT_CNTL__NBIF_HST_SELF_ACTIVATE__SHIFT
- RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM_MASK
- RPB_SWITCH_CNTL2__RD_QUEUE4_SWITCH_NUM__SHIFT
- RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM_MASK
- RPB_SWITCH_CNTL2__RD_QUEUE5_SWITCH_NUM__SHIFT
- RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM_MASK
- RPB_SWITCH_CNTL2__WR_QUEUE4_SWITCH_NUM__SHIFT
- RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM_MASK
- RPB_SWITCH_CNTL2__WR_QUEUE5_SWITCH_NUM__SHIFT
- RPB_TAG_CONF__RPB_ATS_PR_MASK
- RPB_TAG_CONF__RPB_ATS_PR__SHIFT
- RPB_TAG_CONF__RPB_ATS_TR_MASK
- RPB_TAG_CONF__RPB_ATS_TR__SHIFT
- RPB_TAG_CONF__RPB_IO_WR_MASK
- RPB_TAG_CONF__RPB_IO_WR__SHIFT
- RPB_VC_SWITCH_RDWR__MODE_MASK
- RPB_VC_SWITCH_RDWR__MODE__SHIFT
- RPB_VC_SWITCH_RDWR__NUM_RD_MASK
- RPB_VC_SWITCH_RDWR__NUM_RD__SHIFT
- RPB_VC_SWITCH_RDWR__NUM_WR_MASK
- RPB_VC_SWITCH_RDWR__NUM_WR__SHIFT
- RPB_VC_SWITCH_RDWR__XPB_RDREQ_CRD_MASK
- RPB_VC_SWITCH_RDWR__XPB_RDREQ_CRD__SHIFT
- RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK
- RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT
- RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK
- RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT
- RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK
- RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT
- RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH_MASK
- RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_HIGH__SHIFT
- RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW_MASK
- RPB_WR_QUEUE_CNTL2__Q4_PATTERN_MASK_LOW__SHIFT
- RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH_MASK
- RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_HIGH__SHIFT
- RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW_MASK
- RPB_WR_QUEUE_CNTL2__Q5_PATTERN_MASK_LOW__SHIFT
- RPB_WR_QUEUE_CNTL__ARB_MODE_MASK
- RPB_WR_QUEUE_CNTL__ARB_MODE__SHIFT
- RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH_MASK
- RPB_WR_QUEUE_CNTL__Q4_PATTERN_HIGH__SHIFT
- RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW_MASK
- RPB_WR_QUEUE_CNTL__Q4_PATTERN_LOW__SHIFT
- RPB_WR_QUEUE_CNTL__Q4_SHARED_MASK
- RPB_WR_QUEUE_CNTL__Q4_SHARED__SHIFT
- RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE_MASK
- RPB_WR_QUEUE_CNTL__Q4_UNITID_EA_MODE__SHIFT
- RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH_MASK
- RPB_WR_QUEUE_CNTL__Q5_PATTERN_HIGH__SHIFT
- RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW_MASK
- RPB_WR_QUEUE_CNTL__Q5_PATTERN_LOW__SHIFT
- RPB_WR_QUEUE_CNTL__Q5_SHARED_MASK
- RPB_WR_QUEUE_CNTL__Q5_SHARED__SHIFT
- RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE_MASK
- RPB_WR_QUEUE_CNTL__Q5_UNITID_EA_MODE__SHIFT
- RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK
- RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT
- RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK
- RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT
- RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK
- RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT
- RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK
- RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT
- RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE_MASK
- RPB_WR_SWITCH_CNTL__SWITCH_NUM_MODE__SHIFT
- RPB_WR_SWITCH_CNTL__WEIGHT_ADJUST_STEP_MASK
- RPB_WR_SWITCH_CNTL__WEIGHT_ADJUST_STEP__SHIFT
- RPB_WR_SWITCH_CNTL__WORKLOAD_ADJUST_EN_MASK
- RPB_WR_SWITCH_CNTL__WORKLOAD_ADJUST_EN__SHIFT
- RPC
- RPC13R
- RPC14R
- RPC1R
- RPC2R
- RPC3R
- RPC4R
- RPCAUTH_AUTH_DATATOUCH
- RPCAUTH_CRED_HASHED
- RPCAUTH_CRED_NEGATIVE
- RPCAUTH_CRED_NEW
- RPCAUTH_CRED_UPTODATE
- RPCAUTH_EOF
- RPCAUTH_GSSMAGIC
- RPCAUTH_LOOKUP_NEW
- RPCAUTH_RootEOF
- RPCAUTH_cache
- RPCAUTH_gssd
- RPCAUTH_info
- RPCAUTH_lockd
- RPCAUTH_mount
- RPCAUTH_nfs
- RPCAUTH_nfsd
- RPCAUTH_nfsd4_cb
- RPCAUTH_portmap
- RPCAUTH_statd
- RPCBIND_MAXNETIDLEN
- RPCBIND_MAXUADDR4LEN
- RPCBIND_MAXUADDR6LEN
- RPCBIND_MAXUADDRLEN
- RPCBIND_MAXUADDRPLEN
- RPCBIND_NETID_LOCAL
- RPCBIND_NETID_RDMA
- RPCBIND_NETID_RDMA6
- RPCBIND_NETID_SCTP
- RPCBIND_NETID_SCTP6
- RPCBIND_NETID_TCP
- RPCBIND_NETID_TCP6
- RPCBIND_NETID_UDP
- RPCBIND_NETID_UDP6
- RPCBIND_PORT
- RPCBIND_PROGRAM
- RPCBIND_SOCK_PATHNAME
- RPCBPROC_BCAST
- RPCBPROC_CALLIT
- RPCBPROC_DUMP
- RPCBPROC_GETADDR
- RPCBPROC_GETADDRLIST
- RPCBPROC_GETPORT
- RPCBPROC_GETSTAT
- RPCBPROC_GETTIME
- RPCBPROC_GETVERSADDR
- RPCBPROC_INDIRECT
- RPCBPROC_NULL
- RPCBPROC_SET
- RPCBPROC_TADDR2UADDR
- RPCBPROC_UADDR2TADDR
- RPCBPROC_UNSET
- RPCBVERS_2
- RPCBVERS_3
- RPCBVERS_4
- RPCB_MAXOWNERLEN
- RPCB_OWNER_STRING
- RPCB_addr_sz
- RPCB_boolean_sz
- RPCB_getaddrargs_sz
- RPCB_getaddrres_sz
- RPCB_getportres_sz
- RPCB_mappingargs_sz
- RPCB_netid_sz
- RPCB_ownerstring_sz
- RPCB_port_sz
- RPCB_program_sz
- RPCB_protocol_sz
- RPCB_setres_sz
- RPCB_version_sz
- RPCDBG_ALL
- RPCDBG_AUTH
- RPCDBG_BIND
- RPCDBG_CACHE
- RPCDBG_CALL
- RPCDBG_DEBUG
- RPCDBG_FACILITY
- RPCDBG_MISC
- RPCDBG_NFS
- RPCDBG_SCHED
- RPCDBG_SVCDSP
- RPCDBG_SVCXPRT
- RPCDBG_TRANS
- RPCDBG_XPRT
- RPCEIE
- RPCI_PROTOCOL_NUM
- RPCP_F
- RPCP_S
- RPCP_V
- RPCRDMA_ALLPHYSICAL
- RPCRDMA_BACKCHANNEL_DEBUG
- RPCRDMA_BACKWARD_WRS
- RPCRDMA_BIND_TO
- RPCRDMA_BOUNCEBUFFERS
- RPCRDMA_CMP_F_SND_W_INV_OK
- RPCRDMA_CMP_VERSION
- RPCRDMA_DEF_GFP
- RPCRDMA_DEF_INLINE
- RPCRDMA_DEF_INLINE_THRESH
- RPCRDMA_DEF_SLOT_TABLE
- RPCRDMA_FRWR
- RPCRDMA_HDRLEN_ERR
- RPCRDMA_HDRLEN_MIN
- RPCRDMA_IAF_REMOVING
- RPCRDMA_IDLE_DISC_TO
- RPCRDMA_INIT_REEST_TO
- RPCRDMA_LAST
- RPCRDMA_LISTEN_BACKLOG
- RPCRDMA_MAX_BC_REQUESTS
- RPCRDMA_MAX_DATA_SEGS
- RPCRDMA_MAX_HDR_SEGS
- RPCRDMA_MAX_INLINE
- RPCRDMA_MAX_INLINE_THRESH
- RPCRDMA_MAX_IOV_SEGS
- RPCRDMA_MAX_PAGE_SGES
- RPCRDMA_MAX_RECV_BATCH
- RPCRDMA_MAX_REEST_TO
- RPCRDMA_MAX_REQUESTS
- RPCRDMA_MAX_SEGS
- RPCRDMA_MAX_SEND_SGES
- RPCRDMA_MAX_SLOT_TABLE
- RPCRDMA_MEMWINDOWS
- RPCRDMA_MEMWINDOWS_ASYNC
- RPCRDMA_MIN_INLINE
- RPCRDMA_MIN_SEND_SGES
- RPCRDMA_MIN_SLOT_TABLE
- RPCRDMA_MTHCAFMR
- RPCRDMA_REGISTER
- RPCRDMA_V1_DEF_INLINE_SIZE
- RPCRDMA_VERSION
- RPCSEC_GSS_CREDPROBLEM
- RPCSEC_GSS_CTXPROBLEM
- RPCSVC_MAXPAGES
- RPCSVC_MAXPAYLOAD
- RPCSVC_MAXPAYLOAD_RDMA
- RPCSVC_MAXPAYLOAD_TCP
- RPCSVC_MAXPAYLOAD_UDP
- RPCXPRT_CONGESTED
- RPC_ANEG
- RPC_AUTH_BADCRED
- RPC_AUTH_BADVERF
- RPC_AUTH_DES
- RPC_AUTH_ERROR
- RPC_AUTH_EXPIRY_MORATORIUM
- RPC_AUTH_GSS
- RPC_AUTH_GSS_KRB5
- RPC_AUTH_GSS_KRB5I
- RPC_AUTH_GSS_KRB5P
- RPC_AUTH_GSS_LKEY
- RPC_AUTH_GSS_LKEYI
- RPC_AUTH_GSS_LKEYP
- RPC_AUTH_GSS_SPKM
- RPC_AUTH_GSS_SPKMI
- RPC_AUTH_GSS_SPKMP
- RPC_AUTH_KRB
- RPC_AUTH_MAXFLAVOR
- RPC_AUTH_NULL
- RPC_AUTH_OK
- RPC_AUTH_REJECTEDCRED
- RPC_AUTH_REJECTEDVERF
- RPC_AUTH_SHORT
- RPC_AUTH_TOOWEAK
- RPC_AUTH_UNIX
- RPC_BC_PA_IN_USE
- RPC_BIT
- RPC_BUFFER_MAXSIZE
- RPC_BUFFER_POOLSIZE
- RPC_CALL
- RPC_CALLHDRSIZE
- RPC_CALL_MAJORSEEN
- RPC_CLNT_CREATE_AUTOBIND
- RPC_CLNT_CREATE_DISCRTRY
- RPC_CLNT_CREATE_HARDRTRY
- RPC_CLNT_CREATE_INFINITE_SLOTS
- RPC_CLNT_CREATE_NONPRIVPORT
- RPC_CLNT_CREATE_NOPING
- RPC_CLNT_CREATE_NO_IDLE_TIMEOUT
- RPC_CLNT_CREATE_NO_RETRANS_TIMEOUT
- RPC_CLNT_CREATE_QUIET
- RPC_CLNT_CREATE_SOFTERR
- RPC_CLOCK_FREQ
- RPC_CREDCACHE_DEFAULT_HASHBITS
- RPC_CWNDSCALE
- RPC_CWNDSHIFT
- RPC_DCNT
- RPC_DEBUG_DATA
- RPC_DEFAULT
- RPC_DEF_MAX_RESVPORT
- RPC_DEF_MIN_RESVPORT
- RPC_DEF_SLOT_TABLE
- RPC_DISPLAY_ADDR
- RPC_DISPLAY_HEX_ADDR
- RPC_DISPLAY_HEX_PORT
- RPC_DISPLAY_MAX
- RPC_DISPLAY_NETID
- RPC_DISPLAY_PORT
- RPC_DISPLAY_PROTO
- RPC_DPLX
- RPC_DROP_REPLY
- RPC_FRAGMENT_SIZE_MASK
- RPC_GARBAGE_ARGS
- RPC_GSS_PROC_CONTINUE_INIT
- RPC_GSS_PROC_DATA
- RPC_GSS_PROC_DESTROY
- RPC_GSS_PROC_INIT
- RPC_GSS_SVC_INTEGRITY
- RPC_GSS_SVC_NONE
- RPC_GSS_SVC_PRIVACY
- RPC_GSS_VERSION
- RPC_I
- RPC_IFDEBUG
- RPC_INITCWND
- RPC_IOSTATS_VERS
- RPC_IS_ACTIVATED
- RPC_IS_ASYNC
- RPC_IS_PRIORITY
- RPC_IS_QUEUED
- RPC_IS_RUNNING
- RPC_IS_SOFT
- RPC_IS_SOFTCONN
- RPC_IS_SWAPPER
- RPC_LAST_STREAM_FRAGMENT
- RPC_LATCH
- RPC_LED_10
- RPC_LED_100
- RPC_LED_100_10
- RPC_LED_FD
- RPC_LED_RES
- RPC_LED_RX
- RPC_LED_TX
- RPC_LED_TX_RX
- RPC_LSA_DEFAULT
- RPC_LSB_DEFAULT
- RPC_LSXA_SHFT
- RPC_LSXB_SHFT
- RPC_MAXCWND
- RPC_MAXNETNAMELEN
- RPC_MAXVERSION
- RPC_MAX_ADDRBUFLEN
- RPC_MAX_AUTH_SIZE
- RPC_MAX_FRAGMENT_SIZE
- RPC_MAX_HEADER_WITH_AUTH
- RPC_MAX_HEADER_WITH_AUTH_SYS
- RPC_MAX_REPHEADER_WITH_AUTH
- RPC_MAX_REPHEADER_WITH_AUTH_SYS
- RPC_MAX_RESVPORT
- RPC_MAX_SLOT_TABLE
- RPC_MAX_SLOT_TABLE_LIMIT
- RPC_MIN_RESVPORT
- RPC_MIN_SLOT_TABLE
- RPC_MISMATCH
- RPC_MSG_ACCEPTED
- RPC_MSG_DENIED
- RPC_NR_PRIORITY
- RPC_NT_ADDRESS_ERROR
- RPC_NT_ALREADY_LISTENING
- RPC_NT_ALREADY_REGISTERED
- RPC_NT_BAD_STUB_DATA
- RPC_NT_BINDING_HAS_NO_AUTH
- RPC_NT_BINDING_INCOMPLETE
- RPC_NT_BYTE_COUNT_TOO_SMALL
- RPC_NT_CALL_CANCELLED
- RPC_NT_CALL_FAILED
- RPC_NT_CALL_FAILED_DNE
- RPC_NT_CALL_IN_PROGRESS
- RPC_NT_CANNOT_SUPPORT
- RPC_NT_CANT_CREATE_ENDPOINT
- RPC_NT_COMM_FAILURE
- RPC_NT_DUPLICATE_ENDPOINT
- RPC_NT_ENTRY_ALREADY_EXISTS
- RPC_NT_ENTRY_NOT_FOUND
- RPC_NT_ENUM_VALUE_OUT_OF_RANGE
- RPC_NT_FP_DIV_ZERO
- RPC_NT_FP_OVERFLOW
- RPC_NT_FP_UNDERFLOW
- RPC_NT_GROUP_MEMBER_NOT_FOUND
- RPC_NT_INCOMPLETE_NAME
- RPC_NT_INTERFACE_NOT_FOUND
- RPC_NT_INTERNAL_ERROR
- RPC_NT_INVALID_ASYNC_CALL
- RPC_NT_INVALID_ASYNC_HANDLE
- RPC_NT_INVALID_AUTH_IDENTITY
- RPC_NT_INVALID_BINDING
- RPC_NT_INVALID_BOUND
- RPC_NT_INVALID_ENDPOINT_FORMAT
- RPC_NT_INVALID_ES_ACTION
- RPC_NT_INVALID_NAF_ID
- RPC_NT_INVALID_NAME_SYNTAX
- RPC_NT_INVALID_NETWORK_OPTIONS
- RPC_NT_INVALID_NET_ADDR
- RPC_NT_INVALID_OBJECT
- RPC_NT_INVALID_PIPE_OBJECT
- RPC_NT_INVALID_PIPE_OPERATION
- RPC_NT_INVALID_RPC_PROTSEQ
- RPC_NT_INVALID_STRING_BINDING
- RPC_NT_INVALID_STRING_UUID
- RPC_NT_INVALID_TAG
- RPC_NT_INVALID_TIMEOUT
- RPC_NT_INVALID_VERS_OPTION
- RPC_NT_MAX_CALLS_TOO_SMALL
- RPC_NT_NAME_SERVICE_UNAVAILABLE
- RPC_NT_NOTHING_TO_EXPORT
- RPC_NT_NOT_ALL_OBJS_UNEXPORTED
- RPC_NT_NOT_CANCELLED
- RPC_NT_NOT_LISTENING
- RPC_NT_NOT_RPC_ERROR
- RPC_NT_NO_BINDINGS
- RPC_NT_NO_CALL_ACTIVE
- RPC_NT_NO_CONTEXT_AVAILABLE
- RPC_NT_NO_ENDPOINT_FOUND
- RPC_NT_NO_ENTRY_NAME
- RPC_NT_NO_INTERFACES
- RPC_NT_NO_MORE_BINDINGS
- RPC_NT_NO_MORE_ENTRIES
- RPC_NT_NO_MORE_MEMBERS
- RPC_NT_NO_PRINC_NAME
- RPC_NT_NO_PROTSEQS
- RPC_NT_NO_PROTSEQS_REGISTERED
- RPC_NT_NULL_REF_POINTER
- RPC_NT_OBJECT_NOT_FOUND
- RPC_NT_OUT_OF_RESOURCES
- RPC_NT_PIPE_CLOSED
- RPC_NT_PIPE_DISCIPLINE_ERROR
- RPC_NT_PIPE_EMPTY
- RPC_NT_PROCNUM_OUT_OF_RANGE
- RPC_NT_PROTOCOL_ERROR
- RPC_NT_PROTSEQ_NOT_FOUND
- RPC_NT_PROTSEQ_NOT_SUPPORTED
- RPC_NT_PROXY_ACCESS_DENIED
- RPC_NT_SEC_PKG_ERROR
- RPC_NT_SEND_INCOMPLETE
- RPC_NT_SERVER_TOO_BUSY
- RPC_NT_SERVER_UNAVAILABLE
- RPC_NT_SS_CANNOT_GET_CALL_HANDLE
- RPC_NT_SS_CHAR_TRANS_OPEN_FAIL
- RPC_NT_SS_CHAR_TRANS_SHORT_FILE
- RPC_NT_SS_CONTEXT_DAMAGED
- RPC_NT_SS_CONTEXT_MISMATCH
- RPC_NT_SS_HANDLES_MISMATCH
- RPC_NT_SS_IN_NULL_CONTEXT
- RPC_NT_STRING_TOO_LONG
- RPC_NT_TYPE_ALREADY_REGISTERED
- RPC_NT_UNKNOWN_AUTHN_LEVEL
- RPC_NT_UNKNOWN_AUTHN_SERVICE
- RPC_NT_UNKNOWN_AUTHN_TYPE
- RPC_NT_UNKNOWN_AUTHZ_SERVICE
- RPC_NT_UNKNOWN_IF
- RPC_NT_UNKNOWN_MGR_TYPE
- RPC_NT_UNSUPPORTED_AUTHN_LEVEL
- RPC_NT_UNSUPPORTED_NAME_SYNTAX
- RPC_NT_UNSUPPORTED_TRANS_SYN
- RPC_NT_UNSUPPORTED_TYPE
- RPC_NT_UUID_LOCAL_ONLY
- RPC_NT_UUID_NO_ADDRESS
- RPC_NT_WRONG_ES_VERSION
- RPC_NT_WRONG_KIND_OF_BINDING
- RPC_NT_WRONG_PIPE_VERSION
- RPC_NT_WRONG_STUB_VERSION
- RPC_NT_ZERO_DIVIDE
- RPC_PCNT
- RPC_PIPEFS_MOUNT
- RPC_PIPEFS_UMOUNT
- RPC_PIPE_WAIT_FOR_OPEN
- RPC_PRIORITY_HIGH
- RPC_PRIORITY_LOW
- RPC_PRIORITY_NORMAL
- RPC_PRIORITY_PRIVILEGED
- RPC_PROC_UNAVAIL
- RPC_PROG_MISMATCH
- RPC_PROG_UNAVAIL
- RPC_RAM_SIZE
- RPC_RAM_START
- RPC_REG
- RPC_REPHDRSIZE
- RPC_REPLY
- RPC_RTO_INIT
- RPC_RTO_MAX
- RPC_RTO_MIN
- RPC_SHOW_SOCK
- RPC_SHOW_SOCKET
- RPC_SIGNALLED
- RPC_SPEED
- RPC_SUCCESS
- RPC_SYSTEM_ERR
- RPC_TASK_ACTIVE
- RPC_TASK_ASYNC
- RPC_TASK_DYNAMIC
- RPC_TASK_MSG_PIN_WAIT
- RPC_TASK_NEED_RECV
- RPC_TASK_NEED_XMIT
- RPC_TASK_NOCONNECT
- RPC_TASK_NO_RETRANS_TIMEOUT
- RPC_TASK_NO_ROUND_ROBIN
- RPC_TASK_NULLCREDS
- RPC_TASK_POOLSIZE
- RPC_TASK_QUEUED
- RPC_TASK_ROOTCREDS
- RPC_TASK_RUNNING
- RPC_TASK_SENT
- RPC_TASK_SIGNALLED
- RPC_TASK_SOFT
- RPC_TASK_SOFTCONN
- RPC_TASK_SWAPPER
- RPC_TASK_TIMEOUT
- RPC_UPCALL_TIMEOUT
- RPC_VERSION
- RPC_WAS_SENT
- RPD
- RPD0R
- RPD10R
- RPD11R
- RPD12R
- RPD14R
- RPD15R
- RPD1R
- RPD2R
- RPD3R
- RPD4R
- RPD5R
- RPD6R
- RPD7R
- RPD9R
- RPDB_MASK
- RPDB_SHIFT
- RPDNT_100K
- RPDP_ANTA
- RPDP_ANTA_10
- RPDP_ANTA_14
- RPDP_ANTA_18
- RPDP_ANTA_1C
- RPDP_ANTA_20
- RPDP_ANTA_24
- RPDP_ANTA_4
- RPDP_ANTA_8
- RPDP_ANTA_C
- RPDP_ANTB
- RPDP_ANTB_10
- RPDP_ANTB_14
- RPDP_ANTB_18
- RPDP_ANTB_1C
- RPDP_ANTB_20
- RPDP_ANTB_24
- RPDP_ANTB_4
- RPDP_ANTB_8
- RPDP_ANTB_C
- RPDS_MASK
- RPD_CTRL
- RPD_CTRL_MASK
- RPD_CTRL_SHIFT
- RPE3R
- RPE5R
- RPE8R
- RPE9R
- RPEL_REQ_SIZE
- RPEL_RESP_SIZE
- RPF0R
- RPF12R
- RPF13R
- RPF1R
- RPF2R
- RPF3R
- RPF4R
- RPF5R
- RPF8R
- RPFSM_EVENT_FCXP_SENT
- RPFSM_EVENT_RPORT_OFFLINE
- RPFSM_EVENT_RPORT_ONLINE
- RPFSM_EVENT_RPSC_COMP
- RPFSM_EVENT_RPSC_ERROR
- RPFSM_EVENT_RPSC_FAIL
- RPFSM_EVENT_TIMEOUT
- RPF_MASK
- RPF_MAX_HEIGHT
- RPF_MAX_WIDTH
- RPF_SHIFT_BIT
- RPG0R
- RPG1R
- RPG6R
- RPG7R
- RPG8R
- RPG9R
- RPG_ENABLE_BIT
- RPHASE
- RPIPE_CRS_BULK
- RPIPE_CRS_CTL
- RPIPE_CRS_INTR
- RPIPE_CRS_ISO
- RPIPE_PAUSE
- RPIPE_STALL
- RPI_DSI_DRIVER_NAME
- RPI_EXP_GPIO_BASE
- RPI_EXP_GPIO_DIR_IN
- RPI_EXP_GPIO_DIR_OUT
- RPI_FIRMWARE_ALLOCATE_MEMORY
- RPI_FIRMWARE_ARM_CLK_ID
- RPI_FIRMWARE_EXECUTE_CODE
- RPI_FIRMWARE_EXECUTE_QPU
- RPI_FIRMWARE_FRAMEBUFFER_ALLOCATE
- RPI_FIRMWARE_FRAMEBUFFER_BLANK
- RPI_FIRMWARE_FRAMEBUFFER_GET_ALPHA_MODE
- RPI_FIRMWARE_FRAMEBUFFER_GET_DEPTH
- RPI_FIRMWARE_FRAMEBUFFER_GET_GPIOVIRTBUF
- RPI_FIRMWARE_FRAMEBUFFER_GET_OVERSCAN
- RPI_FIRMWARE_FRAMEBUFFER_GET_PALETTE
- RPI_FIRMWARE_FRAMEBUFFER_GET_PHYSICAL_WIDTH_HEIGHT
- RPI_FIRMWARE_FRAMEBUFFER_GET_PITCH
- RPI_FIRMWARE_FRAMEBUFFER_GET_PIXEL_ORDER
- RPI_FIRMWARE_FRAMEBUFFER_GET_TOUCHBUF
- RPI_FIRMWARE_FRAMEBUFFER_GET_VIRTUAL_OFFSET
- RPI_FIRMWARE_FRAMEBUFFER_GET_VIRTUAL_WIDTH_HEIGHT
- RPI_FIRMWARE_FRAMEBUFFER_RELEASE
- RPI_FIRMWARE_FRAMEBUFFER_SET_ALPHA_MODE
- RPI_FIRMWARE_FRAMEBUFFER_SET_BACKLIGHT
- RPI_FIRMWARE_FRAMEBUFFER_SET_DEPTH
- RPI_FIRMWARE_FRAMEBUFFER_SET_GPIOVIRTBUF
- RPI_FIRMWARE_FRAMEBUFFER_SET_OVERSCAN
- RPI_FIRMWARE_FRAMEBUFFER_SET_PALETTE
- RPI_FIRMWARE_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT
- RPI_FIRMWARE_FRAMEBUFFER_SET_PIXEL_ORDER
- RPI_FIRMWARE_FRAMEBUFFER_SET_TOUCHBUF
- RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_OFFSET
- RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT
- RPI_FIRMWARE_FRAMEBUFFER_SET_VSYNC
- RPI_FIRMWARE_FRAMEBUFFER_TEST_ALPHA_MODE
- RPI_FIRMWARE_FRAMEBUFFER_TEST_DEPTH
- RPI_FIRMWARE_FRAMEBUFFER_TEST_OVERSCAN
- RPI_FIRMWARE_FRAMEBUFFER_TEST_PALETTE
- RPI_FIRMWARE_FRAMEBUFFER_TEST_PHYSICAL_WIDTH_HEIGHT
- RPI_FIRMWARE_FRAMEBUFFER_TEST_PIXEL_ORDER
- RPI_FIRMWARE_FRAMEBUFFER_TEST_VIRTUAL_OFFSET
- RPI_FIRMWARE_FRAMEBUFFER_TEST_VIRTUAL_WIDTH_HEIGHT
- RPI_FIRMWARE_FRAMEBUFFER_TEST_VSYNC
- RPI_FIRMWARE_GET_ARM_MEMORY
- RPI_FIRMWARE_GET_BOARD_MAC_ADDRESS
- RPI_FIRMWARE_GET_BOARD_MODEL
- RPI_FIRMWARE_GET_BOARD_REVISION
- RPI_FIRMWARE_GET_BOARD_SERIAL
- RPI_FIRMWARE_GET_CLOCKS
- RPI_FIRMWARE_GET_CLOCK_MEASURED
- RPI_FIRMWARE_GET_CLOCK_RATE
- RPI_FIRMWARE_GET_CLOCK_STATE
- RPI_FIRMWARE_GET_COMMAND_LINE
- RPI_FIRMWARE_GET_CUSTOMER_OTP
- RPI_FIRMWARE_GET_DISPMANX_RESOURCE_MEM_HANDLE
- RPI_FIRMWARE_GET_DMA_CHANNELS
- RPI_FIRMWARE_GET_DOMAIN_STATE
- RPI_FIRMWARE_GET_EDID_BLOCK
- RPI_FIRMWARE_GET_FIRMWARE_REVISION
- RPI_FIRMWARE_GET_GPIO_CONFIG
- RPI_FIRMWARE_GET_GPIO_STATE
- RPI_FIRMWARE_GET_MAX_CLOCK_RATE
- RPI_FIRMWARE_GET_MAX_TEMPERATURE
- RPI_FIRMWARE_GET_MAX_VOLTAGE
- RPI_FIRMWARE_GET_MIN_CLOCK_RATE
- RPI_FIRMWARE_GET_MIN_VOLTAGE
- RPI_FIRMWARE_GET_PERIPH_REG
- RPI_FIRMWARE_GET_POE_HAT_VAL
- RPI_FIRMWARE_GET_POWER_STATE
- RPI_FIRMWARE_GET_STC
- RPI_FIRMWARE_GET_TEMPERATURE
- RPI_FIRMWARE_GET_THROTTLED
- RPI_FIRMWARE_GET_TIMING
- RPI_FIRMWARE_GET_TURBO
- RPI_FIRMWARE_GET_VC_MEMORY
- RPI_FIRMWARE_GET_VOLTAGE
- RPI_FIRMWARE_LOCK_MEMORY
- RPI_FIRMWARE_NOTIFY_REBOOT
- RPI_FIRMWARE_PLLB_ARM_DIV_RATE
- RPI_FIRMWARE_PROPERTY_END
- RPI_FIRMWARE_RELEASE_MEMORY
- RPI_FIRMWARE_SET_CLOCK_RATE
- RPI_FIRMWARE_SET_CLOCK_STATE
- RPI_FIRMWARE_SET_CURSOR_INFO
- RPI_FIRMWARE_SET_CURSOR_STATE
- RPI_FIRMWARE_SET_CUSTOMER_OTP
- RPI_FIRMWARE_SET_DOMAIN_STATE
- RPI_FIRMWARE_SET_ENABLE_QPU
- RPI_FIRMWARE_SET_GPIO_CONFIG
- RPI_FIRMWARE_SET_GPIO_STATE
- RPI_FIRMWARE_SET_PERIPH_REG
- RPI_FIRMWARE_SET_POE_HAT_VAL
- RPI_FIRMWARE_SET_POWER_STATE
- RPI_FIRMWARE_SET_SDHOST_CLOCK
- RPI_FIRMWARE_SET_TURBO
- RPI_FIRMWARE_SET_VOLTAGE
- RPI_FIRMWARE_STATE_ENABLE_BIT
- RPI_FIRMWARE_STATE_WAIT_BIT
- RPI_FIRMWARE_STATUS_ERROR
- RPI_FIRMWARE_STATUS_REQUEST
- RPI_FIRMWARE_STATUS_SUCCESS
- RPI_FIRMWARE_UNLOCK_MEMORY
- RPI_FIRMWARE_VCHIQ_INIT
- RPI_OLD_POWER_DOMAIN_USB
- RPI_OLD_POWER_DOMAIN_V3D
- RPI_POWER_DOMAIN_ARM
- RPI_POWER_DOMAIN_CCP2RX
- RPI_POWER_DOMAIN_CCP2TX
- RPI_POWER_DOMAIN_CDP
- RPI_POWER_DOMAIN_COUNT
- RPI_POWER_DOMAIN_CPI
- RPI_POWER_DOMAIN_CSI2
- RPI_POWER_DOMAIN_DSI0
- RPI_POWER_DOMAIN_DSI1
- RPI_POWER_DOMAIN_H264
- RPI_POWER_DOMAIN_HDMI
- RPI_POWER_DOMAIN_I2C0
- RPI_POWER_DOMAIN_I2C1
- RPI_POWER_DOMAIN_I2C2
- RPI_POWER_DOMAIN_ISP
- RPI_POWER_DOMAIN_JPEG
- RPI_POWER_DOMAIN_TRANSPOSER
- RPI_POWER_DOMAIN_UNICAM0
- RPI_POWER_DOMAIN_UNICAM1
- RPI_POWER_DOMAIN_USB
- RPI_POWER_DOMAIN_V3D
- RPI_POWER_DOMAIN_VEC
- RPI_POWER_DOMAIN_VIDEO_SCALER
- RPI_POWER_DOMAIN_VPU1
- RPI_TS_DEFAULT_HEIGHT
- RPI_TS_DEFAULT_WIDTH
- RPI_TS_FTS_TOUCH_CONTACT
- RPI_TS_FTS_TOUCH_DOWN
- RPI_TS_MAX_SUPPORTED_POINTS
- RPI_TS_NPOINTS_REG_INVALIDATE
- RPI_TS_POLL_INTERVAL
- RPKT_FINISH
- RPKT_FINISH_M
- RPKT_LOST
- RPKT_LOST_INT_STS
- RPKT_LOST_M
- RPKT_SAV
- RPKT_SAVE
- RPKT_SAV_M
- RPL
- RPLL
- RPLL_CON0
- RPLL_CON1
- RPLL_CON2
- RPLL_HALF
- RPLL_INT
- RPLL_INT_MUX
- RPLL_LOCK
- RPLL_POST_SRC
- RPLL_PRE_SRC
- RPLL_TO_FPD
- RPLPERR_F
- RPLPERR_S
- RPLPERR_V
- RPLSET
- RPLY_RECEIV
- RPL_DEV_FLAG_NON_DISK
- RPL_DEV_FLAG_UNCONFIG_DISK
- RPL_DEV_FLAG_UNCONFIG_DISK_REPORTING_SUPPORTED
- RPL_RSP
- RPM
- RPMAC_CCKCRC16
- RPMAC_CCKCRXRC16ER
- RPMAC_CCKCRXRC32ER
- RPMAC_CCKCRXRC32OK
- RPMAC_CCKPLCPHEADER
- RPMAC_CCKPLCPPREAMBLE
- RPMAC_OFDMRXCRC32ER
- RPMAC_OFDMRXCRC32OK
- RPMAC_OFDMRXCRC8ER
- RPMAC_OFDMRXPARITYER
- RPMAC_PHYDEBUG
- RPMAC_RESET
- RPMAC_TXDADATYPE
- RPMAC_TXDATATYPE
- RPMAC_TXHTSIG1
- RPMAC_TXHTSIG2
- RPMAC_TXIDLE
- RPMAC_TXLEGACYSIG
- RPMAC_TXMACHEADER0
- RPMAC_TXMACHEADER1
- RPMAC_TXMACHEADER2
- RPMAC_TXMACHEADER3
- RPMAC_TXMACHEADER4
- RPMAC_TXMACHEADER5
- RPMAC_TXPACKETNNM
- RPMAC_TXPACKETNUM
- RPMAC_TXRANDOMSEED
- RPMAC_TXSTART
- RPMAC_TXSTATUS
- RPMCAP
- RPMH_ACTIVE_ONLY_STATE
- RPMH_ARC_MAX_LEVELS
- RPMH_CXO_CLK
- RPMH_CXO_CLK_A
- RPMH_IPA_CLK
- RPMH_LN_BB_CLK2
- RPMH_LN_BB_CLK2_A
- RPMH_LN_BB_CLK3
- RPMH_LN_BB_CLK3_A
- RPMH_PDC_SYNC_RESET
- RPMH_REGULATOR_LEVEL_LOW_SVS
- RPMH_REGULATOR_LEVEL_MIN_SVS
- RPMH_REGULATOR_LEVEL_NOM
- RPMH_REGULATOR_LEVEL_NOM_L1
- RPMH_REGULATOR_LEVEL_NOM_L2
- RPMH_REGULATOR_LEVEL_RETENTION
- RPMH_REGULATOR_LEVEL_SVS
- RPMH_REGULATOR_LEVEL_SVS_L1
- RPMH_REGULATOR_LEVEL_TURBO
- RPMH_REGULATOR_LEVEL_TURBO_L1
- RPMH_REGULATOR_MODE_AUTO
- RPMH_REGULATOR_MODE_HPM
- RPMH_REGULATOR_MODE_LPM
- RPMH_REGULATOR_MODE_RET
- RPMH_REGULATOR_REG_ENABLE
- RPMH_REGULATOR_REG_VRM_MODE
- RPMH_REGULATOR_REG_VRM_VOLTAGE
- RPMH_RF_CLK1
- RPMH_RF_CLK1_A
- RPMH_RF_CLK2
- RPMH_RF_CLK2_A
- RPMH_RF_CLK3
- RPMH_RF_CLK3_A
- RPMH_SLEEP_STATE
- RPMH_TIMEOUT_MS
- RPMH_VREG
- RPMH_WAKE_ONLY_STATE
- RPMPD_ANAEN
- RPMPD_LDOA
- RPMPD_RWCX
- RPMPD_RWLC
- RPMPD_RWLM
- RPMPD_RWMX
- RPMPD_RWSC
- RPMPD_RWSM
- RPMPD_SMPA
- RPMSG_ADDR_ANY
- RPMSG_CREATE_EPT_IOCTL
- RPMSG_DESTROY_EPT_IOCTL
- RPMSG_DEVICE_MODALIAS_FMT
- RPMSG_DEV_MAX
- RPMSG_NAME_SIZE
- RPMSG_NS_ADDR
- RPMSG_NS_CREATE
- RPMSG_NS_DESTROY
- RPMSG_RESERVED_ADDRESSES
- RPM_ACTIVE
- RPM_APPS_FABRIC_A_CLK
- RPM_APPS_FABRIC_CLK
- RPM_ASYNC
- RPM_AUTO
- RPM_BUS_H_CLK
- RPM_BUS_MASTER_REQ
- RPM_BUS_RESET
- RPM_BUS_SLAVE_REQ
- RPM_CFPB_A_CLK
- RPM_CFPB_CLK
- RPM_CHANNELS
- RPM_CLK_SRC
- RPM_CMD_CLOSE
- RPM_CMD_CLOSE_ACK
- RPM_CMD_INTENT
- RPM_CMD_OPEN
- RPM_CMD_OPEN_ACK
- RPM_CMD_READ_NOTIF
- RPM_CMD_RX_DONE
- RPM_CMD_RX_DONE_W_REUSE
- RPM_CMD_RX_INTENT_REQ
- RPM_CMD_RX_INTENT_REQ_ACK
- RPM_CMD_TX_DATA
- RPM_CMD_TX_DATA_CONT
- RPM_CMD_VERSION
- RPM_CMD_VERSION_ACK
- RPM_CONFIG0
- RPM_CONFIG1
- RPM_CTRL_REG
- RPM_CXO_A_CLK
- RPM_CXO_CLK
- RPM_DAYTONA_FABRIC_A_CLK
- RPM_DAYTONA_FABRIC_CLK
- RPM_EBI1_A_CLK
- RPM_EBI1_CLK
- RPM_FROM_REG
- RPM_GET_CALLBACK
- RPM_GET_PUT
- RPM_GLINK_CID_MAX
- RPM_GLINK_CID_MIN
- RPM_KEY_BW
- RPM_KEY_MA
- RPM_KEY_SWEN
- RPM_KEY_UV
- RPM_MAX_SEL_SIZE
- RPM_MMFPB_A_CLK
- RPM_MMFPB_CLK
- RPM_MM_FABRIC_A_CLK
- RPM_MM_FABRIC_CLK
- RPM_MSG_RAM_H_CLK
- RPM_MSG_RAM_RESET
- RPM_MSG_TYPE_ERR
- RPM_MSG_TYPE_MSG_ID
- RPM_NOTIFICATION
- RPM_NOWAIT
- RPM_PID_USE_ACTUAL_SPEED
- RPM_PLL4_CLK
- RPM_PROC_CLK
- RPM_PROC_RESET
- RPM_PXO_A_CLK
- RPM_PXO_CLK
- RPM_QDSS_A_CLK
- RPM_QDSS_CLK
- RPM_REJECTED
- RPM_REQUEST_TIMEOUT
- RPM_REQ_AUTOSUSPEND
- RPM_REQ_IDLE
- RPM_REQ_NONE
- RPM_REQ_REG
- RPM_REQ_RESUME
- RPM_REQ_SUSPEND
- RPM_RESUMING
- RPM_RX0_ANTA
- RPM_RX0_ANTB
- RPM_RX1_ANTA
- RPM_RX1_ANTB
- RPM_RX2_ANTA
- RPM_RX2_ANTB
- RPM_RX3_ANTA
- RPM_RX3_ANTB
- RPM_RX_FIFO_ID
- RPM_SERVICE_TYPE_REQUEST
- RPM_SFPB_A_CLK
- RPM_SFPB_CLK
- RPM_SLEEP_CLK
- RPM_SMD_AGGR1_NOC_A_CLK
- RPM_SMD_AGGR1_NOC_CLK
- RPM_SMD_AGGR2_NOC_A_CLK
- RPM_SMD_AGGR2_NOC_CLK
- RPM_SMD_BB_CLK1
- RPM_SMD_BB_CLK1_A
- RPM_SMD_BB_CLK1_A_PIN
- RPM_SMD_BB_CLK1_PIN
- RPM_SMD_BB_CLK2
- RPM_SMD_BB_CLK2_A
- RPM_SMD_BB_CLK2_A_PIN
- RPM_SMD_BB_CLK2_PIN
- RPM_SMD_BIMC_A_CLK
- RPM_SMD_BIMC_CLK
- RPM_SMD_BIMC_GPU_A_CLK
- RPM_SMD_BIMC_GPU_CLK
- RPM_SMD_CE1_A_CLK
- RPM_SMD_CE1_CLK
- RPM_SMD_CNOC_A_CLK
- RPM_SMD_CNOC_CLK
- RPM_SMD_CXO_A0
- RPM_SMD_CXO_A0_A
- RPM_SMD_CXO_A0_A_PIN
- RPM_SMD_CXO_A0_PIN
- RPM_SMD_CXO_A1
- RPM_SMD_CXO_A1_A
- RPM_SMD_CXO_A1_A_PIN
- RPM_SMD_CXO_A1_PIN
- RPM_SMD_CXO_A2
- RPM_SMD_CXO_A2_A
- RPM_SMD_CXO_A2_A_PIN
- RPM_SMD_CXO_A2_PIN
- RPM_SMD_CXO_D0
- RPM_SMD_CXO_D0_A
- RPM_SMD_CXO_D0_A_PIN
- RPM_SMD_CXO_D0_PIN
- RPM_SMD_CXO_D1
- RPM_SMD_CXO_D1_A
- RPM_SMD_CXO_D1_A_PIN
- RPM_SMD_CXO_D1_PIN
- RPM_SMD_DIFF_A_CLK
- RPM_SMD_DIFF_CLK
- RPM_SMD_DIV_A_CLK1
- RPM_SMD_DIV_A_CLK2
- RPM_SMD_DIV_A_CLK3
- RPM_SMD_DIV_CLK1
- RPM_SMD_DIV_CLK2
- RPM_SMD_DIV_CLK3
- RPM_SMD_GFX3D_A_CLK_SRC
- RPM_SMD_GFX3D_CLK_SRC
- RPM_SMD_IPA_A_CLK
- RPM_SMD_IPA_CLK
- RPM_SMD_LEVEL_BINNING
- RPM_SMD_LEVEL_LOW_SVS
- RPM_SMD_LEVEL_MIN_SVS
- RPM_SMD_LEVEL_NOM
- RPM_SMD_LEVEL_NOM_PLUS
- RPM_SMD_LEVEL_RETENTION
- RPM_SMD_LEVEL_RETENTION_PLUS
- RPM_SMD_LEVEL_SVS
- RPM_SMD_LEVEL_SVS_PLUS
- RPM_SMD_LEVEL_TURBO
- RPM_SMD_LEVEL_TURBO_NO_CPR
- RPM_SMD_LN_BB_A_CLK
- RPM_SMD_LN_BB_CLK
- RPM_SMD_LN_BB_CLK1
- RPM_SMD_LN_BB_CLK1_A
- RPM_SMD_LN_BB_CLK2
- RPM_SMD_LN_BB_CLK2_A
- RPM_SMD_LN_BB_CLK3_A_PIN
- RPM_SMD_LN_BB_CLK3_PIN
- RPM_SMD_MMAXI_A_CLK
- RPM_SMD_MMAXI_CLK
- RPM_SMD_MMSSNOC_AHB_A_CLK
- RPM_SMD_MMSSNOC_AHB_CLK
- RPM_SMD_OCMEMGX_A_CLK
- RPM_SMD_OCMEMGX_CLK
- RPM_SMD_PCNOC_A_CLK
- RPM_SMD_PCNOC_CLK
- RPM_SMD_PNOC_A_CLK
- RPM_SMD_PNOC_CLK
- RPM_SMD_QDSS_A_CLK
- RPM_SMD_QDSS_CLK
- RPM_SMD_QPIC_CLK
- RPM_SMD_QPIC_CLK_A
- RPM_SMD_RF_CLK1
- RPM_SMD_RF_CLK1_A
- RPM_SMD_RF_CLK1_A_PIN
- RPM_SMD_RF_CLK1_PIN
- RPM_SMD_RF_CLK2
- RPM_SMD_RF_CLK2_A
- RPM_SMD_RF_CLK2_A_PIN
- RPM_SMD_RF_CLK2_PIN
- RPM_SMD_RF_CLK3
- RPM_SMD_RF_CLK3_A
- RPM_SMD_RF_CLK3_A_PIN
- RPM_SMD_RF_CLK3_PIN
- RPM_SMD_SNOC_A_CLK
- RPM_SMD_SNOC_CLK
- RPM_SMD_XO_A_CLK_SRC
- RPM_SMD_XO_CLK_SRC
- RPM_SMI_A_CLK
- RPM_SMI_CLK
- RPM_STATUS_REG
- RPM_SUSPENDED
- RPM_SUSPENDING
- RPM_SYS_FABRIC_A_CLK
- RPM_SYS_FABRIC_CLK
- RPM_TIMER_CLK
- RPM_TOC_MAGIC
- RPM_TOC_MAX_ENTRIES
- RPM_TOC_SIZE
- RPM_TO_REG
- RPM_TX_FIFO_ID
- RPM_XO_A0
- RPM_XO_A1
- RPM_XO_A2
- RPM_XO_D0
- RPM_XO_D1
- RPN_PATTERN
- RPO
- RPOLE2_225_OHM
- RPOLE2_300_OHM
- RPOLE2_450_OHM
- RPOLE2_900_OHM
- RPORT_ADD
- RPORT_DEL
- RPORT_EV_FAILED
- RPORT_EV_LOGO
- RPORT_EV_NONE
- RPORT_EV_READY
- RPORT_EV_STOP
- RPORT_MAGIC
- RPORT_NONE
- RPORT_OPTS
- RPORT_ST_ADISC
- RPORT_ST_DELETE
- RPORT_ST_FLOGI
- RPORT_ST_INIT
- RPORT_ST_PLOGI
- RPORT_ST_PLOGI_WAIT
- RPORT_ST_PRLI
- RPORT_ST_READY
- RPORT_ST_RTV
- RPP
- RPPREVBSYTDNAVG
- RPPREVBSYTUPAVG
- RPR0521_ALS_DATA0_GAIN_MASK
- RPR0521_ALS_DATA0_GAIN_SHIFT
- RPR0521_ALS_DATA1_GAIN_MASK
- RPR0521_ALS_DATA1_GAIN_SHIFT
- RPR0521_ALS_SCALE_AVAIL
- RPR0521_CHAN_ALS_DATA0
- RPR0521_CHAN_ALS_DATA1
- RPR0521_CHAN_INDEX_BOTH
- RPR0521_CHAN_INDEX_IR
- RPR0521_CHAN_INDEX_PXS
- RPR0521_CHAN_PXS
- RPR0521_DEFAULT_MEAS_TIME
- RPR0521_DRV_NAME
- RPR0521_INTERRUPT_ALS_INT_STATUS_MASK
- RPR0521_INTERRUPT_INT_REASSERT_DISABLE
- RPR0521_INTERRUPT_INT_REASSERT_ENABLE
- RPR0521_INTERRUPT_INT_REASSERT_MASK
- RPR0521_INTERRUPT_INT_TRIG_ALS_DISABLE
- RPR0521_INTERRUPT_INT_TRIG_ALS_ENABLE
- RPR0521_INTERRUPT_INT_TRIG_ALS_MASK
- RPR0521_INTERRUPT_INT_TRIG_PS_DISABLE
- RPR0521_INTERRUPT_INT_TRIG_PS_ENABLE
- RPR0521_INTERRUPT_INT_TRIG_PS_MASK
- RPR0521_INTERRUPT_PS_INT_STATUS_MASK
- RPR0521_IRQ_NAME
- RPR0521_MANUFACT_ID
- RPR0521_MODE_ALS_DISABLE
- RPR0521_MODE_ALS_ENABLE
- RPR0521_MODE_ALS_MASK
- RPR0521_MODE_MEAS_TIME_MASK
- RPR0521_MODE_PXS_DISABLE
- RPR0521_MODE_PXS_ENABLE
- RPR0521_MODE_PXS_MASK
- RPR0521_PXS_GAIN_MASK
- RPR0521_PXS_GAIN_SHIFT
- RPR0521_PXS_PERSISTENCE_DRDY
- RPR0521_PXS_PERSISTENCE_MASK
- RPR0521_PXS_SCALE_AVAIL
- RPR0521_REGMAP_NAME
- RPR0521_REG_ALS_CTRL
- RPR0521_REG_ALS_DATA0
- RPR0521_REG_ALS_DATA1
- RPR0521_REG_ID
- RPR0521_REG_INTERRUPT
- RPR0521_REG_MODE_CTRL
- RPR0521_REG_PS_OFFSET_LSB
- RPR0521_REG_PXS_CTRL
- RPR0521_REG_PXS_DATA
- RPR0521_REG_SYSTEM_CTRL
- RPR0521_SLEEP_DELAY_MS
- RPRIME
- RPRINTK
- RPROC_CRASHED
- RPROC_DELETED
- RPROC_FATAL_ERROR
- RPROC_LAST
- RPROC_MMUFAULT
- RPROC_OFFLINE
- RPROC_RUNNING
- RPROC_SUSPENDED
- RPROC_WATCHDOG
- RPRT_ACTIVE_FC4_TYPES
- RPRT_CMD
- RPRT_DISC_PORT
- RPRT_FABRICNAME
- RPRT_HOST_NAME
- RPRT_MAX_FRAME_SIZE
- RPRT_NODENAME
- RPRT_OS_DEVICE_NAME
- RPRT_PORTNAME
- RPRT_PORT_ID
- RPRT_PORT_SPEED
- RPRT_PORT_STATE
- RPRT_PORT_TYPE
- RPRT_SMART_GUID
- RPRT_SMART_MODEL
- RPRT_SMART_PORT_INFO
- RPRT_SMART_QOS
- RPRT_SMART_SECURITY
- RPRT_SMART_SERVICE
- RPRT_SMART_VERSION
- RPRT_SUPPORTED_CLASS
- RPRT_SUPPORTED_FC4_TYPES
- RPRT_SUPPORTED_SPEED
- RPRT_SYM_PORTNAME
- RPS
- RPSC2_PORT_TYPE_NLPORT
- RPSC2_PORT_TYPE_NPIV_PORT
- RPSC2_PORT_TYPE_NPORT
- RPSC2_PORT_TYPE_NPORT_TRUNK
- RPSC2_PORT_TYPE_UNKNOWN
- RPSC_OP_SPEED_10G
- RPSC_OP_SPEED_16G
- RPSC_OP_SPEED_1G
- RPSC_OP_SPEED_2G
- RPSC_OP_SPEED_4G
- RPSC_OP_SPEED_8G
- RPSC_OP_SPEED_NOT_EST
- RPSC_SPEED_CAP_10G
- RPSC_SPEED_CAP_16G
- RPSC_SPEED_CAP_1G
- RPSC_SPEED_CAP_2G
- RPSC_SPEED_CAP_4G
- RPSC_SPEED_CAP_8G
- RPSC_SPEED_CAP_UNKNOWN
- RPSM_EVENT_ACCEPTED
- RPSM_EVENT_ADDRESS_CHANGE
- RPSM_EVENT_ADDRESS_DISC
- RPSM_EVENT_DELETE
- RPSM_EVENT_FAB_SCN
- RPSM_EVENT_FAILED
- RPSM_EVENT_FC4_FCS_ONLINE
- RPSM_EVENT_FC4_OFFLINE
- RPSM_EVENT_FCXP_SENT
- RPSM_EVENT_HCB_OFFLINE
- RPSM_EVENT_HCB_ONLINE
- RPSM_EVENT_LOGO_IMP
- RPSM_EVENT_LOGO_RCVD
- RPSM_EVENT_PLOGI_COMP
- RPSM_EVENT_PLOGI_RCVD
- RPSM_EVENT_PLOGI_RETRY
- RPSM_EVENT_PLOGI_SEND
- RPSM_EVENT_PRLO_RCVD
- RPSM_EVENT_SCN_OFFLINE
- RPSM_EVENT_SCN_ONLINE
- RPSM_EVENT_TIMEOUT
- RPS_ADDR0
- RPS_ADDR1
- RPS_DEV_FLOW_TABLE_SIZE
- RPS_FLOW_ID_INVALID
- RPS_INV
- RPS_IRQ
- RPS_MAP_SIZE
- RPS_NO_CPU
- RPS_NO_FILTER
- RPS_OAN
- RPS_PAGE0
- RPS_PAGE1
- RPS_REQ_SIZE
- RPS_RESP_SIZE
- RPS_RSP
- RPS_SOCK_FLOW_TABLE_SIZE
- RPS_THRESH0
- RPS_THRESH1
- RPS_TOV0
- RPS_TOV1
- RPT
- RPTMaxCount
- RPTR_BLOCK_SIZE
- RPTR_BLOCK_SIZE_MASK
- RPTR_REARM
- RPTSET
- RPT_CNTRL_REPEAT
- RPUE
- RPUEIE
- RPUEIE_MASK
- RPUEIE_SHIFT
- RPUERE
- RPUERE_MASK
- RPUERE_SHIFT
- RPUE_MASK
- RPUE_SHIFT
- RPU_ACR
- RPW
- RPWM
- RPW_CODE
- RPW_MASK
- RPW_SHIFT
- RP_AUDIO
- RP_AV
- RP_BAR0
- RP_BAR1
- RP_CAP
- RP_CHECK_CALL
- RP_CHECK_CHAIN_CALL
- RP_CHECK_RET
- RP_DEVFN
- RP_ECTL_2_R1
- RP_ECTL_2_R1_RX_CTLE_1C_MASK
- RP_ECTL_2_R2
- RP_ECTL_2_R2_RX_CTLE_1C_MASK
- RP_ECTL_4_R1
- RP_ECTL_4_R1_RX_CDR_CTRL_1C_MASK
- RP_ECTL_4_R1_RX_CDR_CTRL_1C_SHIFT
- RP_ECTL_4_R2
- RP_ECTL_4_R2_RX_CDR_CTRL_1C_MASK
- RP_ECTL_4_R2_RX_CDR_CTRL_1C_SHIFT
- RP_ECTL_5_R1
- RP_ECTL_5_R1_RX_EQ_CTRL_L_1C_MASK
- RP_ECTL_5_R2
- RP_ECTL_5_R2_RX_EQ_CTRL_L_1C_MASK
- RP_ECTL_6_R1
- RP_ECTL_6_R1_RX_EQ_CTRL_H_1C_MASK
- RP_ECTL_6_R2
- RP_ECTL_6_R2_RX_EQ_CTRL_H_1C_MASK
- RP_ID
- RP_LINK_CONTROL_STATUS
- RP_LINK_CONTROL_STATUS_2
- RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE
- RP_LINK_CONTROL_STATUS_LINKSTAT_MASK
- RP_LTSSM
- RP_LTSSM_MASK
- RP_MBOX_ABORT_REQUEST
- RP_MBOX_CRASH
- RP_MBOX_ECHO_REPLY
- RP_MBOX_ECHO_REQUEST
- RP_MBOX_PENDING_MSG
- RP_MBOX_READY
- RP_NONE
- RP_NO_BAR
- RP_None
- RP_OFF
- RP_OFFSET
- RP_PRIV_MISC
- RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE
- RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD
- RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_MASK
- RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT
- RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT
- RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE
- RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD
- RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_MASK
- RP_PRIV_XP_DL
- RP_PRIV_XP_DL_GEN2_UPD_FC_TSHOLD
- RP_RXCPL_EOP
- RP_RXCPL_REG0
- RP_RXCPL_REG1
- RP_RXCPL_SOP
- RP_RXCPL_STATUS
- RP_RX_HDR_LIMIT
- RP_RX_HDR_LIMIT_PW
- RP_RX_HDR_LIMIT_PW_MASK
- RP_TX_CNTRL
- RP_TX_EOP
- RP_TX_REG0
- RP_TX_REG1
- RP_TX_SOP
- RP_VEND_CTL0
- RP_VEND_CTL0_DSK_RST_PULSE_WIDTH
- RP_VEND_CTL0_DSK_RST_PULSE_WIDTH_MASK
- RP_VEND_CTL1
- RP_VEND_CTL1_ERPT
- RP_VEND_CTL2
- RP_VEND_CTL2_PCA_ENABLE
- RP_VEND_XP
- RP_VEND_XP_BIST
- RP_VEND_XP_BIST_GOTO_L1_L2_AFTER_DLLP_DONE
- RP_VEND_XP_DL_UP
- RP_VEND_XP_OPPORTUNISTIC_ACK
- RP_VEND_XP_OPPORTUNISTIC_UPDATEFC
- RP_VEND_XP_UPDATE_FC_THRESHOLD_MASK
- RP_VIDEO
- RQC0
- RQC1
- RQC2
- RQC3
- RQC4
- RQCF_ACT_SKIP
- RQCF_REQ_SKIP
- RQCF_UPDATED
- RQC_BIT
- RQC_RSM0
- RQC_RSM1
- RQC_RSM2
- RQC_RSM3
- RQC_UFCC0
- RQC_UFCC1
- RQC_UFCC2
- RQC_UFCC3
- RQE_CNT_PER_PG
- RQE_IDX
- RQE_MAX_IDX_PER_PG
- RQE_PG
- RQFCR_AND
- RQFCR_CLE
- RQFCR_CMP_EXACT
- RQFCR_CMP_MATCH
- RQFCR_CMP_NOEXACT
- RQFCR_CMP_NOMATCH
- RQFCR_GPI
- RQFCR_HASH
- RQFCR_HASHTBL_0
- RQFCR_HASHTBL_1
- RQFCR_HASHTBL_2
- RQFCR_HASHTBL_3
- RQFCR_HASHTBL_Q
- RQFCR_PID_ARB
- RQFCR_PID_DAH
- RQFCR_PID_DAL
- RQFCR_PID_DIA
- RQFCR_PID_DPT
- RQFCR_PID_ETY
- RQFCR_PID_L4P
- RQFCR_PID_L4P_MASK
- RQFCR_PID_MAC_MASK
- RQFCR_PID_MASK
- RQFCR_PID_PARSE
- RQFCR_PID_PORT_MASK
- RQFCR_PID_PRI
- RQFCR_PID_PRI_MASK
- RQFCR_PID_SAH
- RQFCR_PID_SAL
- RQFCR_PID_SIA
- RQFCR_PID_SPT
- RQFCR_PID_TOS
- RQFCR_PID_VID
- RQFCR_PID_VID_MASK
- RQFCR_QUEUE
- RQFCR_RJE
- RQFPR_AR
- RQFPR_ARQ
- RQFPR_CFI
- RQFPR_EBC
- RQFPR_EER
- RQFPR_FIF
- RQFPR_HDR_GE_512
- RQFPR_ICC
- RQFPR_ICV
- RQFPR_IPF
- RQFPR_IPV4
- RQFPR_IPV6
- RQFPR_JUM
- RQFPR_LERR
- RQFPR_PER
- RQFPR_RAR
- RQFPR_RARQ
- RQFPR_TCP
- RQFPR_TUC
- RQFPR_TUV
- RQFPR_UDP
- RQFPR_VLN
- RQF_ALLOCED
- RQF_COPY_USER
- RQF_DONTPREP
- RQF_ELVPRIV
- RQF_FAILED
- RQF_FLUSH_SEQ
- RQF_HASHED
- RQF_IO_STAT
- RQF_MIXED_MERGE
- RQF_MQ_INFLIGHT
- RQF_MQ_POLL_SLEPT
- RQF_NAME
- RQF_NOMERGE_FLAGS
- RQF_PM
- RQF_PREEMPT
- RQF_QUIET
- RQF_SOFTBARRIER
- RQF_SORTED
- RQF_SPECIAL_PAYLOAD
- RQF_STARTED
- RQF_STATS
- RQF_TIMED_OUT
- RQF_ZONE_WRITE_LOCKED
- RQPN
- RQPN1
- RQPN10
- RQPN2
- RQPN3
- RQPN4
- RQPN5
- RQPN6
- RQPN7
- RQPN8
- RQPN9
- RQPN_EPQ_SHIFT
- RQPN_HI_PQ_SHIFT
- RQPN_LOAD
- RQPN_LO_PQ_SHIFT
- RQPN_NPQ_SHIFT
- RQPN_PUB_PQ_SHIFT
- RQST_TMPLT
- RQST_TMPLT_SIZE
- RQT_CHUNK
- RQT_OFF
- RQUEUEMASK
- RQUEUESIZE
- RQUEUE_EN0
- RQUEUE_EN1
- RQUEUE_EN2
- RQUEUE_EN3
- RQUEUE_EN4
- RQUEUE_EN5
- RQUEUE_EN6
- RQUEUE_EN7
- RQUEUE_EN_ALL
- RQUEUE_EX0
- RQUEUE_EX1
- RQUEUE_EX2
- RQUEUE_EX3
- RQUEUE_EX4
- RQUEUE_EX5
- RQUEUE_EX6
- RQUEUE_EX7
- RQUEUE_EX_ALL
- RQWB
- RQ_AUTHERR
- RQ_BFQQ
- RQ_BIC
- RQ_BUSY
- RQ_COMPLETE_SGE
- RQ_COMPLETION_SUSP
- RQ_CQE_OFFOLAD_TYPE_GET
- RQ_CQE_OFFOLAD_TYPE_PKT_TYPE_MASK
- RQ_CQE_OFFOLAD_TYPE_PKT_TYPE_SHIFT
- RQ_CQE_OFFOLAD_TYPE_VLAN_EN_MASK
- RQ_CQE_OFFOLAD_TYPE_VLAN_EN_SHIFT
- RQ_CQE_SGE_GET
- RQ_CQE_SGE_VLAN_MASK
- RQ_CQE_SGE_VLAN_SHIFT
- RQ_CQE_STATUS_GET
- RQ_CQE_STATUS_NUM_LRO_MASK
- RQ_CQE_STATUS_NUM_LRO_SHIFT
- RQ_CTXT_OFFSET
- RQ_DATA
- RQ_DOORBELL_U32_4_RQ_HEAD_M
- RQ_DOORBELL_U32_4_RQ_HEAD_S
- RQ_DOORBELL_U32_8_CMD_M
- RQ_DOORBELL_U32_8_CMD_S
- RQ_DOORBELL_U32_8_HW_SYNC_S
- RQ_DOORBELL_U32_8_QPN_M
- RQ_DOORBELL_U32_8_QPN_S
- RQ_DROPME
- RQ_DROP_CQ_LVL
- RQ_DROP_RBDR_LVL
- RQ_ENET_ADDR_BITS
- RQ_ENET_LEN_BITS
- RQ_ENET_LEN_MASK
- RQ_ENET_TYPE_BITS
- RQ_ENET_TYPE_MASK
- RQ_ENET_TYPE_NOT_SOP
- RQ_ENET_TYPE_ONLY_SOP
- RQ_ENET_TYPE_RESV2
- RQ_ENET_TYPE_RESV3
- RQ_EXP_BARR_ACK
- RQ_EXP_RECEIVE_ACK
- RQ_EXP_WRITE_ACK
- RQ_HDR
- RQ_HDR_1
- RQ_HDR_2
- RQ_HDR_3
- RQ_HDR_4
- RQ_IN_ACT_LOG
- RQ_LOCAL
- RQ_LOCAL_ABORTED
- RQ_LOCAL_COMPLETED
- RQ_LOCAL_MASK
- RQ_LOCAL_OK
- RQ_LOCAL_PENDING
- RQ_MASKED_IDX
- RQ_MAX_TIMEOUT
- RQ_NET_DONE
- RQ_NET_MASK
- RQ_NET_OK
- RQ_NET_PENDING
- RQ_NET_QUEUED
- RQ_NET_SENT
- RQ_NET_SIS
- RQ_NOT
- RQ_PASS_CQ_LVL
- RQ_PASS_RBDR_LVL
- RQ_POSTPONED
- RQ_QOS_COST
- RQ_QOS_H
- RQ_QOS_LATENCY
- RQ_QOS_WBT
- RQ_RES
- RQ_RRQ
- RQ_SA_8BIT_IDX
- RQ_SECURE
- RQ_SFW
- RQ_SGE_SET
- RQ_SIZE_DEFAULT
- RQ_SPLICE_OK
- RQ_SQ_STATS
- RQ_SQ_STATS_OCTS
- RQ_SQ_STATS_PKTS
- RQ_TIMEOUT_S1
- RQ_TIMEOUT_S2
- RQ_TYPE
- RQ_UNMAP
- RQ_UNPLUG
- RQ_USEDEFERRAL
- RQ_VENDOR_CONFIRM_WRITE
- RQ_VENDOR_ERASE_BLOCK
- RQ_VENDOR_FW_DATA
- RQ_VENDOR_GET_INQUEUE
- RQ_VENDOR_GET_MSR
- RQ_VENDOR_GET_OUTQUEUE
- RQ_VENDOR_GET_PAGE
- RQ_VENDOR_GET_ROM_PROC
- RQ_VENDOR_GET_VERSION
- RQ_VENDOR_LOCATE
- RQ_VENDOR_NONE
- RQ_VENDOR_PREPARE_WRITE
- RQ_VENDOR_PURGE
- RQ_VENDOR_QUERY_FW_CONFIG
- RQ_VENDOR_QUERY_FW_READY
- RQ_VENDOR_RESET_DEVICE
- RQ_VENDOR_ROM_DATA
- RQ_VENDOR_SET_BAUD
- RQ_VENDOR_SET_BREAK
- RQ_VENDOR_SET_CHARS
- RQ_VENDOR_SET_DTR
- RQ_VENDOR_SET_FIFO_DISABLE
- RQ_VENDOR_SET_HIGH_PERFOR
- RQ_VENDOR_SET_INTERFACE
- RQ_VENDOR_SET_LINE
- RQ_VENDOR_SET_MCR
- RQ_VENDOR_SET_OPEN
- RQ_VENDOR_SET_RTS
- RQ_VENDOR_SET_RX_HOST_EN
- RQ_VENDOR_SET_XONXOFF
- RQ_VENDOR_START_FW_DOWN
- RQ_VENDOR_START_ROM_DOWN
- RQ_VENDOR_STOP_FW_DOWN
- RQ_VENDOR_STOP_ROM_DOWN
- RQ_VENDOR_WRITE_PAGE
- RQ_VICTIM
- RQ_WA0
- RQ_WA1
- RQ_WA2
- RQ_WAIT_BUSY_PCT
- RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_M
- RQ_WQE_CTRL_RWQE_BYTE_12_RWQE_SGE_NUM_S
- RQ_WQE_RESERVED44_MASK
- RQ_WQE_RESERVED44_SFT
- RQ_WQE_WQE_TYPE_RCV
- RQ_WQE_WR_ID_MASK
- RQ_WQE_WR_ID_SFT
- RQ_WRITE
- RQ_WSAME
- RQ_WSQ
- RQ_ZEROES
- RQ_buf_posted
- RQ_no_buf_found
- RQ_no_posted_buf
- RQ_rcv_buf
- RR
- RR0
- RR0d
- RR1
- RR12
- RR1d
- RR2
- RR2d
- RR3
- RR3_BLINK_LED
- RR3_CLK
- RR3_CLK_CONV_FACTOR
- RR3_CLK_PER_COUNT
- RR3_CPUCS_REG_ADDR
- RR3_DRIVER_MAXLENS
- RR3_END_OF_SIGNAL
- RR3_ERROR
- RR3_FW_VERSION
- RR3_FW_VERSION_LEN
- RR3_GET_IR_PARAM
- RR3_IR_IO_LENGTH_FUZZ
- RR3_IR_IO_MAX_LENGTHS
- RR3_IR_IO_MIN_PAUSE
- RR3_IR_IO_PERIODS_MF
- RR3_IR_IO_SIG_MEM_SIZE
- RR3_IR_IO_SIG_TIMEOUT
- RR3_MAX_SIG_SIZE
- RR3_MODSIG_CAPTURE
- RR3_MOD_SIGNAL_IN
- RR3_MOD_SIGNAL_OUT
- RR3_NARROW_IN_EP_ADDR
- RR3_RC_DET_DISABLE
- RR3_RC_DET_ENABLE
- RR3_RC_DET_STATUS
- RR3_READ_SER_NO
- RR3_RESET
- RR3_RX_MAX_TIMEOUT
- RR3_RX_MIN_TIMEOUT
- RR3_SER_NO_LEN
- RR3_SET_IR_PARAM
- RR3_TIME_UNIT
- RR3_TX_SEND_SIGNAL
- RR3_TX_TRAILER_LEN
- RR3_WIDE_IN_EP_ADDR
- RR4
- RRBA
- RRBR_RTHR
- RRC
- RRCIV
- RRCPLMAPEN_F
- RRCPLMAPEN_S
- RRCPLMAPEN_V
- RRCPLQUEWIDTH_G
- RRCPLQUEWIDTH_M
- RRCPLQUEWIDTH_S
- RRCPLQUEWIDTH_V
- RRCR
- RRC_20
- RRC_25
- RRC_35
- RRDPCS_PHY_DP_TX_PSTATE_HOLD
- RRDPCS_PHY_DP_TX_PSTATE_HOLD_OFF
- RRDPCS_PHY_DP_TX_PSTATE_POWER_DOWN
- RRDPCS_PHY_DP_TX_PSTATE_POWER_UP
- RRDY
- RRDYEN
- RRD_BCAST_MASK
- RRD_BCAST_SHIFT
- RRD_CVALN_TAG
- RRD_CVTAG
- RRD_ERR_FAE_MASK
- RRD_ERR_FAE_SHIFT
- RRD_ERR_FCS_MASK
- RRD_ERR_FCS_SHIFT
- RRD_ERR_FIFOV_MASK
- RRD_ERR_FIFOV_SHIFT
- RRD_ERR_ICMP_MASK
- RRD_ERR_ICMP_SHIFT
- RRD_ERR_IPV4_MASK
- RRD_ERR_IPV4_SHIFT
- RRD_ERR_L4_MASK
- RRD_ERR_L4_SHIFT
- RRD_ERR_LEN_MASK
- RRD_ERR_LEN_SHIFT
- RRD_ERR_RES_MASK
- RRD_ERR_RES_SHIFT
- RRD_ERR_RUNT_MASK
- RRD_ERR_RUNT_SHIFT
- RRD_ERR_TRUNC_MASK
- RRD_ERR_TRUNC_SHIFT
- RRD_ETHTYPE_MASK
- RRD_ETHTYPE_SHIFT
- RRD_L4F
- RRD_MCAST_MASK
- RRD_MCAST_SHIFT
- RRD_NOR
- RRD_NOR_MASK
- RRD_NOR_SHIFT
- RRD_OLD_PID_MASK
- RRD_OLD_PID_SHIFT
- RRD_PID_1588
- RRD_PID_IPV4
- RRD_PID_IPV4TCP
- RRD_PID_IPV4UDP
- RRD_PID_IPV6
- RRD_PID_IPV6TCP
- RRD_PID_IPV6UDP
- RRD_PID_LLDP
- RRD_PID_MASK
- RRD_PID_NONIP
- RRD_PID_SHIFT
- RRD_PKTLEN_MASK
- RRD_PKTLEN_SHIFT
- RRD_PKT_SIZE
- RRD_RING_SIZE_BMSK
- RRD_RING_SIZE_MASK
- RRD_RSSALG_IPV4
- RRD_RSSALG_IPV6
- RRD_RSSALG_MASK
- RRD_RSSALG_SHIFT
- RRD_RSSALG_TCPV4
- RRD_RSSALG_TCPV6
- RRD_RSSQ_MASK
- RRD_RSSQ_SHIFT
- RRD_SI
- RRD_SI_MASK
- RRD_SI_SHIFT
- RRD_TS_HI
- RRD_TS_LOW
- RRD_UPDATED_MASK
- RRD_UPDATED_SHIFT
- RRD_UPDT
- RRD_UPDT_SET
- RRD_VLTAGGED_MASK
- RRD_VLTAGGED_SHIFT
- RRD_VLTAG_MASK
- RRD_VLTAG_SHIFT
- RRD_XSUM_MASK
- RRD_XSUM_SHIFT
- RRE
- RREADY
- RREF_CFG
- RREF_VBGSEL_1V25
- RREF_VBGSEL_MASK
- RREG16
- RREG32
- RREG32_AUDIO_ENDPT
- RREG32_CG
- RREG32_DIDT
- RREG32_ENDPOINT
- RREG32_GC_CAC
- RREG32_IDX
- RREG32_IO
- RREG32_MC
- RREG32_NO_KIQ
- RREG32_PCIE
- RREG32_PCIE_PORT
- RREG32_PIF_PHY0
- RREG32_PIF_PHY1
- RREG32_PLL
- RREG32_RCU
- RREG32_SDMA
- RREG32_SE_CAC
- RREG32_SMC
- RREG32_SOC15
- RREG32_SOC15_DPG_MODE
- RREG32_SOC15_DPG_MODE_2_0
- RREG32_SOC15_OFFSET
- RREG32_UVD_CTX
- RREG64_PCIE
- RREG64_UMC
- RREG8
- RREGDATASIZE
- RREQ_STATE_SR
- RRFCHANNEL
- RRFMOD
- RRF_EMULATE_CDB
- RRF_GOT_LBA
- RRI_REQ_SIZE
- RRI_RESP_SIZE
- RROCE_IPV4
- RROCE_IPV6
- RRQ
- RRR
- RRSC
- RRSR
- RRSR_11M
- RRSR_12M
- RRSR_18M
- RRSR_1M
- RRSR_24M
- RRSR_2M
- RRSR_36M
- RRSR_48M
- RRSR_54M
- RRSR_5_5M
- RRSR_6M
- RRSR_9M
- RRSR_CCK_RATES
- RRSR_MCS0
- RRSR_MCS1
- RRSR_MCS2
- RRSR_MCS3
- RRSR_MCS4
- RRSR_MCS5
- RRSR_MCS6
- RRSR_MCS7
- RRSR_OFDM_RATES
- RRSR_RSC_BW_40M
- RRSR_RSC_DUPLICATE
- RRSR_RSC_DUPLICATE_MODE
- RRSR_RSC_LOWER_SUBCHANNEL
- RRSR_RSC_LOWSUBCHNL
- RRSR_RSC_OFFSET
- RRSR_RSC_RESERVED
- RRSR_RSC_UPPER_SUBCHANNEL
- RRSR_RSC_UPSUBCHNL
- RRSR_SHORT
- RRSR_SHORT_OFFSET
- RRST
- RRS_802_3_LEN_ERR
- RRS_802_3_LEN_ERR_MASK
- RRS_802_3_LEN_ERR_SHIFT
- RRS_CPU_NUM_MASK
- RRS_CPU_NUM_SHIFT
- RRS_ERR_BAD_CRC
- RRS_ERR_CODE
- RRS_ERR_DES_ADDR
- RRS_ERR_DRIBBLE
- RRS_ERR_IP_CSUM
- RRS_ERR_IP_CSUM_MASK
- RRS_ERR_IP_CSUM_SHIFT
- RRS_ERR_L4_CSUM
- RRS_ERR_L4_CSUM_MASK
- RRS_ERR_L4_CSUM_SHIFT
- RRS_ERR_LENGTH
- RRS_ERR_RUNT
- RRS_ERR_RX_OVERFLOW
- RRS_ERR_TRUNC
- RRS_FIFO_FULL_MASK
- RRS_FIFO_FULL_SHIFT
- RRS_HASH_CTRL_EN
- RRS_HASH_FLG_MASK
- RRS_HASH_FLG_SHIFT
- RRS_HDS_TYPE_DATA
- RRS_HDS_TYPE_HEAD
- RRS_HDS_TYPE_MASK
- RRS_HDS_TYPE_SHIFT
- RRS_HEAD_LEN_MASK
- RRS_HEAD_LEN_SHIFT
- RRS_IS_802_3
- RRS_IS_BCAST
- RRS_IS_ERR_FRAME
- RRS_IS_HDS_DATA
- RRS_IS_HDS_HEAD
- RRS_IS_IPV4
- RRS_IS_IPV6
- RRS_IS_IP_DF
- RRS_IS_IP_FRAG
- RRS_IS_MCAST
- RRS_IS_NO_HDS_TYPE
- RRS_IS_PAUSE
- RRS_IS_RSS_IPV4
- RRS_IS_RSS_IPV4_TCP
- RRS_IS_RSS_IPV6
- RRS_IS_RSS_IPV6_TCP
- RRS_IS_TCP
- RRS_IS_UDP
- RRS_IS_VLAN_TAG
- RRS_PACKET_BCAST_MASK
- RRS_PACKET_BCAST_SHIFT
- RRS_PACKET_IS_ETH
- RRS_PACKET_MCAST_MASK
- RRS_PACKET_MCAST_SHIFT
- RRS_PACKET_PROT_IS_IPV4_ONLY
- RRS_PACKET_PROT_IS_IPV6_ONLY
- RRS_PACKET_TYPE_802_3
- RRS_PACKET_TYPE_ETH
- RRS_PACKET_TYPE_MASK
- RRS_PACKET_TYPE_SHIFT
- RRS_PKT_SIZE_MASK
- RRS_PKT_SIZE_SHIFT
- RRS_PROT_ID_MASK
- RRS_PROT_ID_SHIFT
- RRS_RXD_IS_VALID
- RRS_RXD_UPDATED
- RRS_RXD_UPDATED_MASK
- RRS_RXD_UPDATED_SHIFT
- RRS_RX_CSUM_MASK
- RRS_RX_CSUM_SHIFT
- RRS_RX_ERR_CRC
- RRS_RX_ERR_CRC_MASK
- RRS_RX_ERR_CRC_SHIFT
- RRS_RX_ERR_FAE_MASK
- RRS_RX_ERR_FAE_SHIFT
- RRS_RX_ERR_ICMP_MASK
- RRS_RX_ERR_ICMP_SHIFT
- RRS_RX_ERR_RUNC_MASK
- RRS_RX_ERR_RUNC_SHIFT
- RRS_RX_ERR_SUM
- RRS_RX_ERR_SUM_MASK
- RRS_RX_ERR_SUM_SHIFT
- RRS_RX_ERR_TRUNC_MASK
- RRS_RX_ERR_TRUNC_SHIFT
- RRS_RX_RFD_CNT_MASK
- RRS_RX_RFD_CNT_SHIFT
- RRS_RX_RFD_INDEX_MASK
- RRS_RX_RFD_INDEX_SHIFT
- RRS_VLAN_INS
- RRS_VLAN_INS_MASK
- RRS_VLAN_INS_SHIFT
- RRTL8256_RXLPF
- RRTL8256_TXLPF
- RRTL8258_RSSILPF
- RRTL8258_RXLPF
- RRTL8258_TXLPF
- RRXDATA
- RRXPATH
- RRXRDPT
- RRXWRPT
- RRX_CCK
- RRX_IQK
- RRX_IQK_PI_A
- RRX_IQK_PI_B
- RRX_IQK_TONE_A
- RRX_IQK_TONE_B
- RRX_OFDM
- RRX_POER_BEFORE_IQK_B
- RRX_POER_BEFORE_IQK_B_2
- RRX_POWER_AFTER_IQK_A
- RRX_POWER_AFTER_IQK_A_2
- RRX_POWER_AFTER_IQK_B
- RRX_POWER_AFTER_IQK_B_2
- RRX_POWER_BEFORE_IQK_A
- RRX_POWER_BEFORE_IQK_A_2
- RRX_POWER_BEFORE_IQK_B
- RRX_POWER_BEFORE_IQK_B_2
- RRX_TO_RX
- RRX_WAIT_CCA
- RRX_WAIT_RIFS
- RR_APP
- RR_BITS
- RR_CL
- RR_CLEAR
- RR_CLEAR_INT
- RR_CL_s
- RR_CMP
- RR_COPY
- RR_COPYINVERTED
- RR_CRC
- RR_DETECT
- RR_EOS
- RR_HW_CTL
- RR_HW_HIGH_POWER_FRAMES_MASK
- RR_HW_LOW_POWER_FRAMES_MASK
- RR_INT
- RR_INVERT
- RR_MAX_CE_ENTRIES
- RR_MIN_IO
- RR_NM
- RR_NM_s
- RR_NOOP
- RR_NRS
- RR_PL
- RR_PL_s
- RR_PN
- RR_PN_s
- RR_PS
- RR_PS_MASK
- RR_PS_SHIFT
- RR_PX
- RR_PX_s
- RR_RDP
- RR_RE
- RR_REG
- RR_REGARD_XA
- RR_RELOC_DE
- RR_REV_2
- RR_REV_MASK
- RR_RID_MASK
- RR_RR_s
- RR_SET
- RR_SH
- RR_SL
- RR_SL_s
- RR_TF
- RR_TF_s
- RR_TIMESLICE
- RR_TO_PS
- RR_TO_RID
- RR_TO_VE
- RR_VE
- RR_VERSION
- RR_VE_MASK
- RR_VE_SHIFT
- RR_VPP
- RR_XOR
- RR_ZF_s
- RRi
- RS
- RS1
- RS1024x768
- RS1056x344
- RS1056x400
- RS1056x480
- RS1152x864
- RS1280x1024
- RS1408x1056
- RS15bpp
- RS1600x1200
- RS16bpp
- RS1CONTSAV_FULL_RS1
- RS1CONTSAV_MASK
- RS1CONTSAV_NO_RS1
- RS1CONTSAV_RSVD
- RS1CONTSAV_SAVE_RS1
- RS1EN
- RS1_RXEVMDUMP
- RS1_RX_EVM_DUMP
- RS2
- RS2000_FE_CRYSTAL_KHZ
- RS232INT
- RS232_CABLE
- RS232_MODE
- RS232_ON
- RS24bpp
- RS2EN
- RS2INC0
- RS2_RXEVMDUMP
- RS2_RX_EVM_DUMP
- RS3
- RS32bpp
- RS3EN
- RS400_DISP1_ALLOW_FID_LEVEL_MASK
- RS400_DISP1_ALLOW_FID_LEVEL_SHIFT
- RS400_DISP1_CRITICAL_POINT_START_MASK
- RS400_DISP1_CRITICAL_POINT_START_SHIFT
- RS400_DISP1_CRITICAL_POINT_STOP_MASK
- RS400_DISP1_CRITICAL_POINT_STOP_SHIFT
- RS400_DISP1_REQ_CNTL1
- RS400_DISP1_START_REQ_LEVEL_MASK
- RS400_DISP1_START_REQ_LEVEL_SHIFT
- RS400_DISP1_STOP_REQ_LEVEL_MASK
- RS400_DISP1_STOP_REQ_LEVEL_SHIFT
- RS400_DISP2_ALLOW_FID_LEVEL_MASK
- RS400_DISP2_ALLOW_FID_LEVEL_SHIFT
- RS400_DISP2_CRITICAL_POINT_START_MASK
- RS400_DISP2_CRITICAL_POINT_START_SHIFT
- RS400_DISP2_CRITICAL_POINT_STOP_MASK
- RS400_DISP2_CRITICAL_POINT_STOP_SHIFT
- RS400_DISP2_REQ_CNTL1
- RS400_DISP2_REQ_CNTL2
- RS400_DISP2_START_ADR_MASK
- RS400_DISP2_START_ADR_SHIFT
- RS400_DISP2_START_REQ_LEVEL_MASK
- RS400_DISP2_START_REQ_LEVEL_SHIFT
- RS400_DISP2_STOP_REQ_LEVEL_MASK
- RS400_DISP2_STOP_REQ_LEVEL_SHIFT
- RS400_DMIF_MEM_CNTL1
- RS400_FP2_2_BLANK_EN
- RS400_FP2_2_DETECT_SENSE
- RS400_FP2_2_DVO2_EN
- RS400_FP2_2_GEN_CNTL
- RS400_FP2_2_ON
- RS400_FP2_2_PANEL_FORMAT
- RS400_FP2_2_SOURCE_SEL_CRTC1
- RS400_FP2_2_SOURCE_SEL_CRTC2
- RS400_FP2_2_SOURCE_SEL_MASK
- RS400_FP2_2_SOURCE_SEL_RMX
- RS400_FP_2ND_BLANK_EN
- RS400_FP_2ND_DETECT_EN
- RS400_FP_2ND_DETECT_SENSE
- RS400_FP_2ND_EN_TMDS
- RS400_FP_2ND_GEN_CNTL
- RS400_FP_2ND_ON
- RS400_FP_2ND_SOURCE_SEL_CRTC1
- RS400_FP_2ND_SOURCE_SEL_CRTC2
- RS400_FP_2ND_SOURCE_SEL_MASK
- RS400_FP_2ND_SOURCE_SEL_RMX
- RS400_HPD_2ND_SEL
- RS400_MSI_REARM
- RS400_PANEL_FORMAT_2ND
- RS400_PTE_READABLE
- RS400_PTE_UNSNOOPED
- RS400_PTE_WRITEABLE
- RS400_TMDS2_CNTL
- RS400_TMDS2_PLLEN
- RS400_TMDS2_PLLRST
- RS400_TMDS2_TRANSMITTER_CNTL
- RS400_TMDS_2ND_EN
- RS422_MODE
- RS480_1LEVEL_GART
- RS480_2LEVEL_GART
- RS480_AGP_ADDRESS_SPACE_SIZE
- RS480_AGP_BASE_2
- RS480_AGP_MODE_CNTL
- RS480_AGP_RD_BUF_SIZE
- RS480_DISABLE_GTW
- RS480_GART_BASE
- RS480_GART_CACHE_CNTRL
- RS480_GART_CACHE_INVALIDATE
- RS480_GART_EN
- RS480_GART_FEATURE_ID
- RS480_GART_INDEX_REG_EN
- RS480_GTW_LAC_EN
- RS480_HANG_EN
- RS480_MC_MISC_CNTL
- RS480_NB_MC_DATA
- RS480_NB_MC_INDEX
- RS480_NB_MC_IND_WR_EN
- RS480_NONGART_SNOOP
- RS480_P2P_ENABLE
- RS480_PDC_EN
- RS480_POST_GART_Q_SIZE
- RS480_REQ_TYPE_SNOOP_DIS
- RS480_REQ_TYPE_SNOOP_MASK
- RS480_REQ_TYPE_SNOOP_SHIFT
- RS480_TLB_ENABLE
- RS480_VA_SIZE_128MB
- RS480_VA_SIZE_1GB
- RS480_VA_SIZE_256MB
- RS480_VA_SIZE_2GB
- RS480_VA_SIZE_32MB
- RS480_VA_SIZE_512MB
- RS480_VA_SIZE_64MB
- RS485
- RS485_2WIRE_MODE
- RS485_4WIRE_MODE
- RS485_URA
- RS4bpp
- RS5C313_ADDR_CNTREG
- RS5C313_ADDR_DAY
- RS5C313_ADDR_DAY10
- RS5C313_ADDR_HOUR
- RS5C313_ADDR_HOUR10
- RS5C313_ADDR_INTINTVREG
- RS5C313_ADDR_MIN
- RS5C313_ADDR_MIN10
- RS5C313_ADDR_MON
- RS5C313_ADDR_MON10
- RS5C313_ADDR_SEC
- RS5C313_ADDR_SEC10
- RS5C313_ADDR_TESTREG
- RS5C313_ADDR_WEEK
- RS5C313_ADDR_YEAR
- RS5C313_ADDR_YEAR10
- RS5C313_CE
- RS5C313_CEDISABLE
- RS5C313_CEENABLE
- RS5C313_CE_RTCCE
- RS5C313_CNTBIT_AD
- RS5C313_CNTBIT_DT
- RS5C313_CNTBIT_READ
- RS5C313_CNTREG_12_24
- RS5C313_CNTREG_ADJ_BSY
- RS5C313_CNTREG_CTFG
- RS5C313_CNTREG_WTEN_XSTP
- RS5C313_MISCOP
- RS5C313_TESTREG_TEST
- RS5C348_BIT_24H
- RS5C348_BIT_PM
- RS5C348_BIT_VDET
- RS5C348_BIT_XSTP
- RS5C348_BIT_Y2K
- RS5C348_CMD_MR
- RS5C348_CMD_MW
- RS5C348_CMD_R
- RS5C348_CMD_W
- RS5C348_DAY_MASK
- RS5C348_HOURS_MASK
- RS5C348_MINS_MASK
- RS5C348_MONTH_MASK
- RS5C348_REG_CTL1
- RS5C348_REG_CTL2
- RS5C348_REG_DAY
- RS5C348_REG_HOURS
- RS5C348_REG_MINS
- RS5C348_REG_MONTH
- RS5C348_REG_SECS
- RS5C348_REG_WDAY
- RS5C348_REG_YEAR
- RS5C348_SECS_MASK
- RS5C348_WDAY_MASK
- RS5C372A_CTRL1_SL1
- RS5C372_CTRL2_24
- RS5C372_REG_DAY
- RS5C372_REG_HOURS
- RS5C372_REG_MINS
- RS5C372_REG_MONTH
- RS5C372_REG_SECS
- RS5C372_REG_TRIM
- RS5C372_REG_WDAY
- RS5C372_REG_YEAR
- RS5C372_TRIM_MASK
- RS5C372_TRIM_XSL
- RS5C_ADDR
- RS5C_CTRL1_AALE
- RS5C_CTRL1_BALE
- RS5C_CTRL1_CT0
- RS5C_CTRL1_CT4
- RS5C_CTRL1_CT_MASK
- RS5C_CTRL2_AAFG
- RS5C_CTRL2_BAFG
- RS5C_CTRL2_CTFG
- RS5C_CTRL2_XSTP
- RS5C_REG_ALARM_A_HOURS
- RS5C_REG_ALARM_A_MIN
- RS5C_REG_ALARM_A_WDAY
- RS5C_REG_ALARM_B_HOURS
- RS5C_REG_ALARM_B_MIN
- RS5C_REG_ALARM_B_WDAY
- RS5C_REG_CTRL1
- RS5C_REG_CTRL2
- RS600_BUS_MASTER_DIS
- RS600_EFFECTIVE_L1_CACHE_SIZE
- RS600_EFFECTIVE_L1_QUEUE_SIZE
- RS600_EFFECTIVE_L2_CACHE_SIZE
- RS600_EFFECTIVE_L2_QUEUE_SIZE
- RS600_ENABLE_FRAGMENT_PROCESSING
- RS600_ENABLE_PAGE_TABLE
- RS600_ENABLE_PAGE_TABLES
- RS600_ENABLE_PT
- RS600_ENABLE_TRANSLATION_MODE_OVERRIDE
- RS600_INVALIDATE_ALL_L1_TLBS
- RS600_INVALIDATE_L1_TLB
- RS600_INVALIDATE_L2_CACHE
- RS600_MC_ADDR_MASK
- RS600_MC_AGP_BASE
- RS600_MC_AGP_BASE_2
- RS600_MC_AGP_LOCATION
- RS600_MC_AGP_START_MASK
- RS600_MC_AGP_START_SHIFT
- RS600_MC_AGP_TOP_MASK
- RS600_MC_AGP_TOP_SHIFT
- RS600_MC_CNTL1
- RS600_MC_DATA
- RS600_MC_FB_LOCATION
- RS600_MC_FB_START_MASK
- RS600_MC_FB_START_SHIFT
- RS600_MC_FB_TOP_MASK
- RS600_MC_FB_TOP_SHIFT
- RS600_MC_IDLE
- RS600_MC_INDEX
- RS600_MC_IND_AIC_RBS
- RS600_MC_IND_CITF_ARB0
- RS600_MC_IND_CITF_ARB1
- RS600_MC_IND_SEQ_RBS_0
- RS600_MC_IND_SEQ_RBS_1
- RS600_MC_IND_SEQ_RBS_2
- RS600_MC_IND_SEQ_RBS_3
- RS600_MC_IND_WR_EN
- RS600_MC_PT0_CLIENT0_CNTL
- RS600_MC_PT0_CNTL
- RS600_MC_PT0_CONTEXT0_CNTL
- RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR
- RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR
- RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR
- RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR
- RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR
- RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR
- RS600_MC_STATUS
- RS600_MC_STATUS_IDLE
- RS600_MSI_REARM
- RS600_PAGE_TABLE_TYPE_FLAT
- RS600_SYSTEM_ACCESS_MODE_IN_SYS
- RS600_SYSTEM_ACCESS_MODE_MASK
- RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS
- RS600_SYSTEM_ACCESS_MODE_PA_ONLY
- RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP
- RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE
- RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH
- RS600_TRANSLATION_MODE_OVERRIDE
- RS640x350
- RS640x400
- RS640x480
- RS690_AIC_CTRL_SCRATCH
- RS690_BLOCK_GFX_D3_EN
- RS690_DIS_OUT_OF_PCI_GART_ACCESS
- RS690_HDP_FB_LOCATION
- RS690_MCCFG_AGP_BASE
- RS690_MCCFG_AGP_BASE_2
- RS690_MCCFG_AGP_LOCATION
- RS690_MCCFG_FB_LOCATION
- RS690_MC_AGP_START_MASK
- RS690_MC_AGP_START_SHIFT
- RS690_MC_AGP_TOP_MASK
- RS690_MC_AGP_TOP_SHIFT
- RS690_MC_DATA
- RS690_MC_FB_START_MASK
- RS690_MC_FB_START_SHIFT
- RS690_MC_FB_TOP_MASK
- RS690_MC_FB_TOP_SHIFT
- RS690_MC_INDEX
- RS690_MC_INDEX_MASK
- RS690_MC_INDEX_WR_ACK
- RS690_MC_INDEX_WR_EN
- RS690_MC_INIT_MISC_LAT_TIMER
- RS690_MC_STATUS
- RS690_MC_STATUS_IDLE
- RS6K_AOUTHDR_NMAGIC
- RS6K_AOUTHDR_OMAGIC
- RS6K_AOUTHDR_ZMAGIC
- RS70_PCI_REV_SUPPORTED
- RS768x576
- RS780D_FVTHROTPWMFBDIVRANGEREG0_DFLT
- RS780D_FVTHROTPWMFBDIVRANGEREG1_DFLT
- RS780D_FVTHROTPWMFBDIVRANGEREG2_DFLT
- RS780_CGCLKGATING_DFLT
- RS780_CGFTV_DFLT
- RS780_DEFAULT_DCLK_FREQ
- RS780_DEFAULT_VCLK_FREQ
- RS780_FBDIVTIMERVAL_DFLT
- RS780_FVTHROTDTC0_DFLT
- RS780_FVTHROTDTC1_DFLT
- RS780_FVTHROTDTC2_DFLT
- RS780_FVTHROTDTC3_DFLT
- RS780_FVTHROTDTC4_DFLT
- RS780_FVTHROTFBDSREG0_DFLT
- RS780_FVTHROTFBDSREG1_DFLT
- RS780_FVTHROTFBUSREG0_DFLT
- RS780_FVTHROTFBUSREG1_DFLT
- RS780_FVTHROTPWMDSREG0_DFLT
- RS780_FVTHROTPWMDSREG1_DFLT
- RS780_FVTHROTPWMFBDIVRANGEREG0_DFLT
- RS780_FVTHROTPWMFBDIVRANGEREG1_DFLT
- RS780_FVTHROTPWMFBDIVRANGEREG2_DFLT
- RS780_FVTHROTPWMRANGE0_GPIO_DFLT
- RS780_FVTHROTPWMRANGE1_GPIO_DFLT
- RS780_FVTHROTPWMRANGE2_GPIO_DFLT
- RS780_FVTHROTPWMRANGE3_GPIO_DFLT
- RS780_FVTHROTPWMUSREG0_DFLT
- RS780_FVTHROTPWMUSREG1_DFLT
- RS780_FVTHROTUTC0_DFLT
- RS780_FVTHROTUTC1_DFLT
- RS780_FVTHROTUTC2_DFLT
- RS780_FVTHROTUTC3_DFLT
- RS780_FVTHROTUTC4_DFLT
- RS780_SLOWCLKFEEDBACKDIV_DFLT
- RS780_VDDC_LEVEL_HIGH
- RS780_VDDC_LEVEL_LOW
- RS780_VDDC_LEVEL_UNKNOWN
- RS800x600
- RS880D_FVTHROTPWMFBDIVRANGEREG0_DFLT
- RS880D_FVTHROTPWMFBDIVRANGEREG1_DFLT
- RS880D_FVTHROTPWMFBDIVRANGEREG2_DFLT
- RS8bpp
- RS960x720
- RSASIG_LEN
- RSAT_REG
- RSA_CMD_INIT
- RSA_CMD_START
- RSA_ENABLE
- RSA_ENGINE_TIMEOUT
- RSA_PDB_D_MASK
- RSA_PDB_D_SHIFT
- RSA_PDB_E_MASK
- RSA_PDB_E_SHIFT
- RSA_PDB_Q_MASK
- RSA_PDB_Q_SHIFT
- RSA_PDB_SGF_F
- RSA_PDB_SGF_G
- RSA_PDB_SGF_SHIFT
- RSA_PRIV_KEY_FRM_1
- RSA_PRIV_KEY_FRM_2
- RSA_PRIV_KEY_FRM_3
- RSA_PRIV_PDB_SGF_F
- RSA_PRIV_PDB_SGF_G
- RSA_STATUS_ACTIVE
- RSA_STATUS_DONE
- RSA_STATUS_FAILED
- RSA_STATUS_IDLE
- RSB_ADDR
- RSB_CCR
- RSB_CCR_CLK_DIV
- RSB_CCR_MAX_CLK_DIV
- RSB_CCR_SDA_OUT_DELAY
- RSB_CLEAR_LOOPS
- RSB_CMD
- RSB_CMD_RD16
- RSB_CMD_RD32
- RSB_CMD_RD8
- RSB_CMD_STRA
- RSB_CMD_WR16
- RSB_CMD_WR32
- RSB_CMD_WR8
- RSB_CTRL
- RSB_CTRL_ABORT_TRANS
- RSB_CTRL_GLOBAL_INT_ENB
- RSB_CTRL_NAME
- RSB_CTRL_SOFT_RST
- RSB_CTRL_START_TRANS
- RSB_DAR
- RSB_DAR_DA
- RSB_DAR_RTA
- RSB_DATA
- RSB_DMCR
- RSB_DMCR_DEVICE_START
- RSB_DMCR_DEV_ADDR
- RSB_DMCR_MODE_DATA
- RSB_DMCR_MODE_REG
- RSB_FILL_LOOPS
- RSB_INTE
- RSB_INTS
- RSB_INTS_LOAD_BSY
- RSB_INTS_TRANS_ERR
- RSB_INTS_TRANS_ERR_ACK
- RSB_INTS_TRANS_ERR_DATA
- RSB_INTS_TRANS_ERR_DATA_BIT
- RSB_INTS_TRANS_OVER
- RSB_LCR
- RSB_LCR_SCL_CTL
- RSB_LCR_SCL_CTL_EN
- RSB_LCR_SCL_STATE
- RSB_LCR_SDA_CTL
- RSB_LCR_SDA_CTL_EN
- RSB_LCR_SDA_STATE
- RSB_MASTER_UNCERTAIN
- RSB_MAX_FREQ
- RSB_NEW_MASTER
- RSB_NEW_MASTER2
- RSB_RECOVER_CONVERT
- RSB_RECOVER_GRANT
- RSB_RECOVER_LVB_INVAL
- RSB_VALNOTVALID
- RSB_VALNOTVALID_PREV
- RSCCR
- RSCFG_RG
- RSCFG_RSTYPE_HARD
- RSCFG_RSTYPE_SOFT
- RSCNTH
- RSCNTL
- RSCN_ADDRESS_FORMAT_AREA
- RSCN_ADDRESS_FORMAT_DOMAIN
- RSCN_ADDRESS_FORMAT_FABRIC
- RSCN_ADDRESS_FORMAT_MASK
- RSCN_ADDRESS_FORMAT_PORT
- RSCN_AREA_ADDR
- RSCN_DEV_LOST
- RSCN_DOM_ADDR
- RSCN_FAB_ADDR
- RSCN_PORT_ADDR
- RSCONFIG_DMA_ENABLE
- RSCONFIG_DMA_TO_HOST
- RSCONFIG_MAX_DMA_SIZE_MASK
- RSCONFIG_MAX_DMA_SIZE_SHIFT
- RSCONFIG_MODULO_1024
- RSCONFIG_MODULO_128
- RSCONFIG_MODULO_16
- RSCONFIG_MODULO_256
- RSCONFIG_MODULO_32
- RSCONFIG_MODULO_4
- RSCONFIG_MODULO_512
- RSCONFIG_MODULO_64
- RSCONFIG_MODULO_8
- RSCONFIG_MODULO_SIZE_MASK
- RSCONFIG_PRIORITY_HIGH
- RSCONFIG_PRIORITY_LOW
- RSCONFIG_PRIORITY_MASK
- RSCONFIG_PRIORITY_MEDIUM_HIGH
- RSCONFIG_PRIORITY_MEDIUM_LOW
- RSCONFIG_SAMPLE_16MONO
- RSCONFIG_SAMPLE_16STEREO
- RSCONFIG_SAMPLE_8MONO
- RSCONFIG_SAMPLE_8STEREO
- RSCONFIG_SAMPLE_SIZE_MASK
- RSCONFIG_STREAM_NUM_MASK
- RSCONFIG_STREAM_NUM_SHIFT
- RSCONFIG_UNDERRUN_ZERO
- RSCORESTATUS
- RSCR
- RSCRP
- RSCTRL_KEY
- RSCTRL_KEY_MASK
- RSCTRL_RESET_MASK
- RSCTRL_RG
- RSCTYP
- RSC_CARVEOUT
- RSC_DEVMEM
- RSC_DRV_CMD_ADDR
- RSC_DRV_CMD_DATA
- RSC_DRV_CMD_ENABLE
- RSC_DRV_CMD_MSGID
- RSC_DRV_CMD_OFFSET
- RSC_DRV_CMD_RESP_DATA
- RSC_DRV_CMD_STATUS
- RSC_DRV_CMD_WAIT_FOR_CMPL
- RSC_DRV_CONTROL
- RSC_DRV_IRQ_CLEAR
- RSC_DRV_IRQ_ENABLE
- RSC_DRV_IRQ_STATUS
- RSC_DRV_STATUS
- RSC_DRV_TCS_OFFSET
- RSC_HANDLED
- RSC_HASHBITS
- RSC_HASHMAX
- RSC_IGNORED
- RSC_LAST
- RSC_TRACE
- RSC_VDEV
- RSC_VENDOR_END
- RSC_VENDOR_START
- RSCreate
- RSDMAE
- RSD_EXTENSION
- RSD_FIXED
- RSD_NBR
- RSD_REQUIRED
- RSDepth
- RSECAR
- RSECCNT
- RSEED
- RSEL
- RSEL_MASK
- RSEN_CHANGE_INT
- RSEN_CHANGE_INT_MASK
- RSEN_STATUS
- RSEQ_ACCESS_ONCE
- RSEQ_ASM_CMP_CPU_ID
- RSEQ_ASM_DEFINE_ABORT
- RSEQ_ASM_DEFINE_CMPFAIL
- RSEQ_ASM_DEFINE_EXIT_POINT
- RSEQ_ASM_DEFINE_TABLE
- RSEQ_ASM_OP_CMPEQ
- RSEQ_ASM_OP_CMPEQ32
- RSEQ_ASM_OP_CMPNE
- RSEQ_ASM_OP_FINAL_STORE
- RSEQ_ASM_OP_FINAL_STORE_RELEASE
- RSEQ_ASM_OP_R_ADD
- RSEQ_ASM_OP_R_BAD_MEMCPY
- RSEQ_ASM_OP_R_FINAL_STORE
- RSEQ_ASM_OP_R_LOAD
- RSEQ_ASM_OP_R_LOADX
- RSEQ_ASM_OP_R_LOAD_OFF
- RSEQ_ASM_OP_R_MEMCPY
- RSEQ_ASM_OP_R_STORE
- RSEQ_ASM_OP_STORE
- RSEQ_ASM_OP_STORE_RELEASE
- RSEQ_ASM_STORE_RSEQ_CS
- RSEQ_ASM_TMP_REG
- RSEQ_ASM_TMP_REG32
- RSEQ_ASM_TMP_REG_2
- RSEQ_CPU_ID_OFFSET
- RSEQ_CPU_ID_REGISTRATION_FAILED
- RSEQ_CPU_ID_UNINITIALIZED
- RSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE
- RSEQ_CS_FLAG_NO_RESTART_ON_MIGRATE_BIT
- RSEQ_CS_FLAG_NO_RESTART_ON_PREEMPT
- RSEQ_CS_FLAG_NO_RESTART_ON_PREEMPT_BIT
- RSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL
- RSEQ_CS_FLAG_NO_RESTART_ON_SIGNAL_BIT
- RSEQ_CS_OFFSET
- RSEQ_CS_PREEMPT_MIGRATE_FLAGS
- RSEQ_EVENT_MIGRATE
- RSEQ_EVENT_MIGRATE_BIT
- RSEQ_EVENT_PREEMPT
- RSEQ_EVENT_PREEMPT_BIT
- RSEQ_EVENT_SIGNAL
- RSEQ_EVENT_SIGNAL_BIT
- RSEQ_FLAG_UNREGISTER
- RSEQ_H
- RSEQ_INJECT_ASM
- RSEQ_INJECT_C
- RSEQ_INJECT_CLOBBER
- RSEQ_INJECT_FAILED
- RSEQ_INJECT_INPUT
- RSEQ_READ_ONCE
- RSEQ_SIG
- RSEQ_SIG_CODE
- RSEQ_SIG_DATA
- RSEQ_WRITE_ONCE
- RSERVED_ENCRYPTION
- RSETUP
- RSETUP_MAX
- RSETUP_SHIFT
- RSETUP_VAL
- RSET_6345_ENETDMA_SIZE
- RSET_ATM
- RSET_ATM_SIZE
- RSET_DDR
- RSET_DSL
- RSET_DSL_LMEM
- RSET_DSL_LMEM_SIZE
- RSET_DSL_SIZE
- RSET_EHCI0
- RSET_EHCI_SIZE
- RSET_ENET0
- RSET_ENET1
- RSET_ENETDMA
- RSET_ENETDMAC
- RSET_ENETDMAC_SIZE
- RSET_ENETDMAS
- RSET_ENETDMAS_SIZE
- RSET_ENETDMA_SIZE
- RSET_ENETSW
- RSET_ENETSW_SIZE
- RSET_ENET_SIZE
- RSET_GPIO
- RSET_HSSPI
- RSET_HSSPI_SIZE
- RSET_M2M
- RSET_M2M_SIZE
- RSET_MEMC
- RSET_MISC
- RSET_MPI
- RSET_OHCI0
- RSET_OHCI_PRIV
- RSET_OHCI_SIZE
- RSET_PCIE
- RSET_PCM
- RSET_PCMCIA
- RSET_PCMCIA_SIZE
- RSET_PCMDMA
- RSET_PCMDMAC
- RSET_PCMDMAS
- RSET_PERF
- RSET_RNG
- RSET_RNG_SIZE
- RSET_SDRAM
- RSET_SPI
- RSET_TIMER
- RSET_UART0
- RSET_UART1
- RSET_UART_SIZE
- RSET_UDC0
- RSET_UDC_SIZE
- RSET_USBD
- RSET_USBDMA
- RSET_USBDMA_SIZE
- RSET_USBD_SIZE
- RSET_USBH_PRIV
- RSET_WDT
- RSET_WDT_SIZE
- RSET_XTM
- RSET_XTMDMA
- RSET_XTMDMAC
- RSET_XTMDMAC_SIZE
- RSET_XTMDMAS
- RSET_XTMDMAS_SIZE
- RSET_XTMDMA_SIZE
- RSET_XTM_SIZE
- RSE_HINTS_COUNT
- RSE_MASK
- RSE_WORKAROUND
- RSF16_MAXFREQ
- RSF16_MINFREQ
- RSF_CODE
- RSI
- RSIF_CLE_BUFF_THRESH_SET
- RSIF_CONFIG_REG_ADDR
- RSIF_PLC_CLE_BUFF_THRESH_SET
- RSIF_RAM_DBG_REG0_ADDR
- RSISO_RG
- RSIZE
- RSIZE_MASK
- RSI_11B_MODE
- RSI_11G_MODE
- RSI_9116_DEF_TA_AGGR
- RSI_9116_FW_MAGIC_WORD
- RSI_9116_REG_SIZE
- RSI_ACTIVE_SCAN_TIME
- RSI_ADD_DELTA_TSF_VAP_ID
- RSI_ADD_PEER
- RSI_AGGR_PARAMS_RX_AGGR
- RSI_AGGR_PARAMS_START
- RSI_AGGR_PARAMS_TID_MASK
- RSI_BCN_MISS_THRESHOLD
- RSI_BEACON_INTERVAL
- RSI_BGSCAN_PERIODICITY
- RSI_BL_CTRL_LAST_ENTRY
- RSI_BL_CTRL_LEN_MASK
- RSI_BL_CTRL_REL_TA_SOFTRESET
- RSI_BL_CTRL_SPI_32BIT_MODE
- RSI_BL_CTRL_SPI_8BIT_MODE
- RSI_BL_CTRL_START_FROM_ROM_PC
- RSI_BROADCAST_MAGICPKT
- RSI_BROADCAST_PKT
- RSI_BT_DATA_Q
- RSI_BT_MGMT_Q
- RSI_BT_Q
- RSI_BYPASS_ULP_ON_WDT
- RSI_CHANNEL_SCAN_TIME
- RSI_CHAN_RADAR
- RSI_CIPHER_TKIP
- RSI_CIPHER_WPA
- RSI_CMDDESC_40MHZ
- RSI_CMDDESC_FULL_40_ENABLE
- RSI_CMDDESC_LOWER_20_ENABLE
- RSI_CMDDESC_UPPER_20_ENABLE
- RSI_COEX_Q
- RSI_COEX_Q_BT
- RSI_COEX_Q_COMMON
- RSI_COEX_Q_INVALID
- RSI_COEX_Q_WLAN
- RSI_COMMON_REG_SIZE
- RSI_CONNECTED_SLEEP
- RSI_DATA_DESC_BEACON_FRAME
- RSI_DATA_DESC_DTIM_BEACON
- RSI_DATA_DESC_DTIM_BEACON_GATED_FRAME
- RSI_DATA_DESC_INSERT_SEQ_NO
- RSI_DATA_DESC_INSERT_TSF
- RSI_DATA_DESC_MAC_BBP_INFO
- RSI_DATA_DESC_NORMAL_FRAME
- RSI_DATA_DESC_NO_ACK_IND
- RSI_DATA_DESC_QOS_EN
- RSI_DEEP_SLEEP
- RSI_DEF_BGSCAN_THRLD
- RSI_DEF_DS_WAKEUP_PERIOD
- RSI_DEF_KEEPALIVE
- RSI_DEF_LISTEN_INTERVAL
- RSI_DEF_ROAM_THRLD
- RSI_DELETE_PEER
- RSI_DESC_REQUIRE_CFM_TO_HOST
- RSI_DESC_VAP_ID_MASK
- RSI_DESC_VAP_ID_OFST
- RSI_DEVICE_BUFFER_STATUS_REGISTER
- RSI_DEV_9113
- RSI_DEV_9116
- RSI_DEV_COEX_MODE_WIFI_ALONE
- RSI_DEV_OPMODE_WIFI_ALONE
- RSI_DISCONNECT_PKT
- RSI_DMA_ALIGN
- RSI_DPD
- RSI_DTIM_COUNT
- RSI_DUTY_CYCLING
- RSI_EAPOL_PKT
- RSI_EEPROM_HDR_SIZE_MASK
- RSI_EEPROM_HDR_SIZE_OFFSET
- RSI_EEPROM_LEN_MASK
- RSI_EEPROM_LEN_OFFSET
- RSI_ENABLE_40MHZ
- RSI_ENCRYPT_PKT
- RSI_END_OF_FRAME
- RSI_FETCH_RETRY_CNT_FRM_HST
- RSI_FN1_INT_REGISTER
- RSI_FRAME_DESC_SIZE
- RSI_FSM_STATES
- RSI_FW_WDT_DISABLE_REQ
- RSI_GET_SDIO_INTERRUPT_TYPE
- RSI_GPIO_0_PSPI_CSN_0
- RSI_GPIO_10_UART1_TX
- RSI_GPIO_11_UART1_RTS_I2S_CLK
- RSI_GPIO_12_UART1_CTS_I2S_WS
- RSI_GPIO_13_DBG_UART_RX_I2S_DIN
- RSI_GPIO_14_DBG_UART_RX_I2S_DOUT
- RSI_GPIO_15_LP_WAKEUP_BOOT_BYPASS
- RSI_GPIO_16_LED_0
- RSI_GPIO_17_BTCOEX_WLAN_ACT_EXT_ANT_SEL
- RSI_GPIO_18_BTCOEX_BT_PRIO_EXT_ANT_SEL
- RSI_GPIO_19_BTCOEX_BT_ACT_EXT_ON_OFF
- RSI_GPIO_1_PSPI_CSN_1
- RSI_GPIO_20_RF_RESET
- RSI_GPIO_21_SLEEP_IND_FROM_DEVICE
- RSI_GPIO_2_HOST_WAKEUP_INTR
- RSI_GPIO_2_ULP
- RSI_GPIO_3_PSPI_DATA_0
- RSI_GPIO_4_PSPI_DATA_1
- RSI_GPIO_5_PSPI_DATA_2
- RSI_GPIO_6_PSPI_DATA_3
- RSI_GPIO_7_I2C_SCL
- RSI_GPIO_8_I2C_SDA
- RSI_GPIO_9_UART1_RX
- RSI_GPIO_MOTION_SENSOR_ULP_WAKEUP
- RSI_GPIO_PUSH_BUTTON_ULP_WAKEUP
- RSI_GPIO_SLEEP_IND_FROM_DEVICE
- RSI_GROUP_KEY
- RSI_GSPI_2_ULP
- RSI_GSPI_CTRL_REG0
- RSI_GSPI_CTRL_REG0_VALUE
- RSI_GSPI_CTRL_REG1
- RSI_GSPI_DATA_REG0
- RSI_GSPI_DATA_REG1
- RSI_GSPI_DATA_REG2
- RSI_GSPI_DMA_MODE
- RSI_GSPI_READ
- RSI_GSPI_RF_SPI_ACTIVE
- RSI_GSPI_TRIG
- RSI_HASHBITS
- RSI_HASHMAX
- RSI_HEADROOM_FOR_BT_HAL
- RSI_HOST_INTF_SDIO
- RSI_HOST_INTF_USB
- RSI_HW_BMISS_PKT
- RSI_IEEE80211_UAPSD_QUEUES
- RSI_IFTYPE_STATION
- RSI_INSERT_SEQ_IN_FW
- RSI_INT_ENABLE_MASK
- RSI_INT_ENABLE_REGISTER
- RSI_KEY_ID_MASK
- RSI_KEY_ID_OFFSET
- RSI_KEY_MODE_AP
- RSI_KEY_TYPE_BROADCAST
- RSI_LMAC_CLOCK_80MHZ
- RSI_MASTER_REG_BUF_SIZE
- RSI_MAX_ASSOC_STAS
- RSI_MAX_RX_AGGR_FRMS
- RSI_MAX_RX_PKTS
- RSI_MAX_RX_USB_PKT_SIZE
- RSI_MAX_SCAN_IE_LEN
- RSI_MAX_SCAN_SSIDS
- RSI_MAX_TX_AGGR_FRMS
- RSI_MAX_VIFS
- RSI_MODEM_CLK_160MHZ
- RSI_MPDU_DENSITY
- RSI_NEEDED_HEADROOM
- RSI_OPMODE_AP
- RSI_OPMODE_P2P_CLIENT
- RSI_OPMODE_P2P_GO
- RSI_OPMODE_STA
- RSI_OPMODE_UNSUPPORTED
- RSI_PAIRWISE_KEY
- RSI_PASSIVE_SCAN_TIME
- RSI_PROTECT_DATA_FRAMES
- RSI_PS_DISABLE
- RSI_PS_DISABLE_IND
- RSI_PS_ENABLE
- RSI_QOS_ENABLE
- RSI_RATE_00
- RSI_RATE_1
- RSI_RATE_11
- RSI_RATE_12
- RSI_RATE_18
- RSI_RATE_2
- RSI_RATE_24
- RSI_RATE_36
- RSI_RATE_48
- RSI_RATE_54
- RSI_RATE_5_5
- RSI_RATE_6
- RSI_RATE_9
- RSI_RATE_AUTO
- RSI_RATE_MCS0
- RSI_RATE_MCS1
- RSI_RATE_MCS2
- RSI_RATE_MCS3
- RSI_RATE_MCS4
- RSI_RATE_MCS5
- RSI_RATE_MCS6
- RSI_RATE_MCS7
- RSI_RATE_MCS7_SG
- RSI_RCV_BUFFER_LEN
- RSI_REGION_ETSI
- RSI_REGION_FCC
- RSI_REGION_TELEC
- RSI_REGION_WORLD
- RSI_REKEY_PURPOSE
- RSI_RESTART_WDT
- RSI_RF_SPI_PROG_REG_BASE_ADDR
- RSI_RF_TYPE
- RSI_RX_DESC_MSG_TYPE_OFFSET
- RSI_SDIO_PID_9113
- RSI_SDIO_PID_9116
- RSI_SDIO_VENDOR_ID
- RSI_SD_REQUEST_MASTER
- RSI_SET_PS_ENABLE
- RSI_SIFS_TX_ENABLE
- RSI_SLEEP_REQUEST
- RSI_SLEEP_TYPE_LP
- RSI_START_BGSCAN
- RSI_STOP_BGSCAN
- RSI_SUPP_FILTERS
- RSI_SWITCH_BBP_LMAC_CLK_REG
- RSI_SWITCH_QSPI_CLK
- RSI_SWITCH_SLP_CLK_2_32
- RSI_SWITCH_TASS_CLK
- RSI_SWITCH_WLAN_BBP_LMAC_CLK_REG
- RSI_SWITCH_ZBBT_BBP_LMAC_CLK_REG
- RSI_TA_HOLD_REG
- RSI_TBL_SZ
- RSI_TX_STATUS
- RSI_TX_STATUS_TYPE
- RSI_ULP_RESET_REG
- RSI_ULP_TIMER_ENABLE
- RSI_ULP_WRITE_0
- RSI_ULP_WRITE_2
- RSI_ULP_WRITE_50
- RSI_UNICAST_MAGIC_PKT
- RSI_UNUSED_SOC_GPIO_BITMAP
- RSI_UNUSED_ULP_GPIO_BITMAP
- RSI_USB_BUF_SIZE
- RSI_USB_CTRL_BUF_SIZE
- RSI_USB_PID_9113
- RSI_USB_PID_9116
- RSI_USB_READY_MAGIC_NUM
- RSI_USB_REQ_IN
- RSI_USB_REQ_OUT
- RSI_USB_TX_HEAD_ROOM
- RSI_USB_VENDOR_ID
- RSI_WAKEUP_REQUEST
- RSI_WATCH_DOG_DELAY_TIMER_1
- RSI_WATCH_DOG_DELAY_TIMER_2
- RSI_WATCH_DOG_TIMER_1
- RSI_WATCH_DOG_TIMER_2
- RSI_WATCH_DOG_TIMER_ENABLE
- RSI_WEP_KEY
- RSI_WEP_KEY_104
- RSI_WIFI_DATA_Q
- RSI_WIFI_MGMT_Q
- RSI_WLAN_Q
- RSI_WOW_ANY
- RSI_WOW_DISCONNECT
- RSI_WOW_ENABLED
- RSI_WOW_GTK_REKEY
- RSI_WOW_KEEPALIVE
- RSI_WOW_MAGIC_PKT
- RSI_WOW_NO_CONNECTION
- RSL
- RSLEEP
- RSLT_RESET_ERR
- RSLT_RESET_WAITING
- RSME
- RSMUX_LOCK_MASK
- RSMUX_LOCK_SET
- RSMUX_OMODE_MASK
- RSMUX_OMODE_RESET_OFF
- RSMUX_OMODE_RESET_ON
- RSMU_BASE__INST0_SEG0
- RSMU_BASE__INST0_SEG1
- RSMU_BASE__INST0_SEG2
- RSMU_BASE__INST0_SEG3
- RSMU_BASE__INST0_SEG4
- RSMU_BASE__INST0_SEG5
- RSMU_BASE__INST1_SEG0
- RSMU_BASE__INST1_SEG1
- RSMU_BASE__INST1_SEG2
- RSMU_BASE__INST1_SEG3
- RSMU_BASE__INST1_SEG4
- RSMU_BASE__INST1_SEG5
- RSMU_BASE__INST2_SEG0
- RSMU_BASE__INST2_SEG1
- RSMU_BASE__INST2_SEG2
- RSMU_BASE__INST2_SEG3
- RSMU_BASE__INST2_SEG4
- RSMU_BASE__INST2_SEG5
- RSMU_BASE__INST3_SEG0
- RSMU_BASE__INST3_SEG1
- RSMU_BASE__INST3_SEG2
- RSMU_BASE__INST3_SEG3
- RSMU_BASE__INST3_SEG4
- RSMU_BASE__INST3_SEG5
- RSMU_BASE__INST4_SEG0
- RSMU_BASE__INST4_SEG1
- RSMU_BASE__INST4_SEG2
- RSMU_BASE__INST4_SEG3
- RSMU_BASE__INST4_SEG4
- RSMU_BASE__INST4_SEG5
- RSMU_BASE__INST5_SEG0
- RSMU_BASE__INST5_SEG1
- RSMU_BASE__INST5_SEG2
- RSMU_BASE__INST5_SEG3
- RSMU_BASE__INST5_SEG4
- RSMU_BASE__INST5_SEG5
- RSMU_BASE__INST6_SEG0
- RSMU_BASE__INST6_SEG1
- RSMU_BASE__INST6_SEG2
- RSMU_BASE__INST6_SEG3
- RSMU_BASE__INST6_SEG4
- RSMU_BASE__INST6_SEG5
- RSMU_BASE__INST7_SEG0
- RSMU_BASE__INST7_SEG1
- RSMU_BASE__INST7_SEG2
- RSMU_BASE__INST7_SEG3
- RSMU_BASE__INST7_SEG4
- RSMU_BASE__INST7_SEG5
- RSMU_BIOS_TIMER_CMD__CFG_TMR_MICROSECONDS_MASK
- RSMU_BIOS_TIMER_CMD__CFG_TMR_MICROSECONDS__SHIFT
- RSMU_BIOS_TIMER_CNTL__CFG_TMR_CLOCKRATE_MASK
- RSMU_BIOS_TIMER_CNTL__CFG_TMR_CLOCKRATE__SHIFT
- RSMU_HWIP
- RSMU_MASTER_CONTROL__RSMU_MASTER_MESSAGE_SEND_ENABLE_MASK
- RSMU_MASTER_CONTROL__RSMU_MASTER_MESSAGE_SEND_ENABLE__SHIFT
- RSMU_POWER_GATING_CONTROL__CFG_IDLE_HYSTERESIS_MASK
- RSMU_POWER_GATING_CONTROL__CFG_IDLE_HYSTERESIS__SHIFT
- RSMU_POWER_GATING_CONTROL__CFG_PG_EN_MASK
- RSMU_POWER_GATING_CONTROL__CFG_PG_EN__SHIFT
- RSMU_POWER_GATING_CONTROL__CFG_PG_HYSTERESIS_MASK
- RSMU_POWER_GATING_CONTROL__CFG_PG_HYSTERESIS__SHIFT
- RSMU_POWER_GATING_CONTROL__PWR_GATE_MAC_ONLY_MASK
- RSMU_POWER_GATING_CONTROL__PWR_GATE_MAC_ONLY__SHIFT
- RSMU_POWER_GATING_CONTROL__PWR_GATE_PHY_ONLY_MASK
- RSMU_POWER_GATING_CONTROL__PWR_GATE_PHY_ONLY__SHIFT
- RSMU_SLAVE_CONTROL__RSMU_SLAVE_IGNORE_INVALID_CONFIG_WRITE_MASK
- RSMU_SLAVE_CONTROL__RSMU_SLAVE_IGNORE_INVALID_CONFIG_WRITE__SHIFT
- RSMU_SLAVE_CONTROL__RSMU_SLAVE_INVALID_READ_RETURN_ZERO_MASK
- RSMU_SLAVE_CONTROL__RSMU_SLAVE_INVALID_READ_RETURN_ZERO__SHIFT
- RSMU_SOFT_RST_CTRL__CORE_RST_EN_MASK
- RSMU_SOFT_RST_CTRL__CORE_RST_EN__MASK
- RSMU_SOFT_RST_CTRL__CORE_RST_EN__SHIFT
- RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN_MASK
- RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN__MASK
- RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN__SHIFT
- RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN_MASK
- RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN__MASK
- RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN__SHIFT
- RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK
- RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN__MASK
- RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT
- RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN_MASK
- RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN__MASK
- RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN__SHIFT
- RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK
- RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN__MASK
- RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT
- RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN_MASK
- RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN__MASK
- RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN__SHIFT
- RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK
- RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN__MASK
- RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT
- RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN_MASK
- RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN__MASK
- RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN__SHIFT
- RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK
- RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN__MASK
- RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT
- RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN_MASK
- RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN__MASK
- RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN__SHIFT
- RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN_MASK
- RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN__MASK
- RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT
- RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU__RSMU_UMC_INDEX_INSTANCE_MASK
- RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU__RSMU_UMC_INDEX_INSTANCE__SHIFT
- RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU__RSMU_UMC_INDEX_MODE_EN_MASK
- RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU__RSMU_UMC_INDEX_MODE_EN__SHIFT
- RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU__RSMU_UMC_INDEX_WREN_MASK
- RSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU__RSMU_UMC_INDEX_WREN__SHIFT
- RSM_EN
- RSM_INS_FECN
- RSM_INS_VERBS
- RSM_INS_VNIC
- RSM_PSR_BE_I
- RSM_PSR_DT
- RSM_PSR_I
- RSM_PSR_IC
- RSM_PSR_I_IC
- RSND_BASE_MAX
- RSND_DAI_NAME_SIZE
- RSND_DVC_NAME_SIZE
- RSND_FMTS
- RSND_GEN1
- RSND_GEN1_ADG
- RSND_GEN1_SRU
- RSND_GEN1_SSI
- RSND_GEN2
- RSND_GEN2_ADG
- RSND_GEN2_SCU
- RSND_GEN2_SSI
- RSND_GEN2_SSIU
- RSND_GEN3
- RSND_GEN_MASK
- RSND_GEN_M_REG
- RSND_GEN_S_REG
- RSND_H
- RSND_MAX_CHANNELS
- RSND_MOD_AUDMA
- RSND_MOD_AUDMAPP
- RSND_MOD_CMD
- RSND_MOD_CTU
- RSND_MOD_DVC
- RSND_MOD_MAX
- RSND_MOD_MIX
- RSND_MOD_SRC
- RSND_MOD_SSI
- RSND_MOD_SSIM1
- RSND_MOD_SSIM2
- RSND_MOD_SSIM3
- RSND_MOD_SSIP
- RSND_MOD_SSIU
- RSND_NODE_CTU
- RSND_NODE_DAI
- RSND_NODE_DVC
- RSND_NODE_MIX
- RSND_NODE_SRC
- RSND_NODE_SSI
- RSND_NODE_SSIU
- RSND_RATES
- RSND_REG_SET
- RSND_SOC_E
- RSND_SOC_MASK
- RSND_SRC_NAME_SIZE
- RSND_SSI_CLK_PIN_SHARE
- RSND_SSI_NAME_SIZE
- RSND_SSI_NO_BUSIF
- RSND_SSI_PROBED
- RSND_STREAM_HDMI0
- RSND_STREAM_HDMI1
- RSND_STREAM_TDM_SPLIT
- RSNN_NN_CMD
- RSNN_NN_REQ_SIZE
- RSNN_NN_RSP_SIZE
- RSNN_REQUEST_SZ
- RSN_AKM_NONE
- RSN_AKM_PSK
- RSN_AKM_SHA256_1X
- RSN_AKM_SHA256_PSK
- RSN_AKM_UNSPECIFIED
- RSN_BODY_SIZE
- RSN_CAP_LEN
- RSN_CAP_MFPC_MASK
- RSN_CAP_MFPR_MASK
- RSN_CAP_PTK_REPLAY_CNTR_MASK
- RSN_GTK_OUI_OFFSET
- RSN_HEADER_LEN
- RSN_IE_BODY_MAX
- RSN_INFO_ELEM_ID
- RSN_MODE_NONE
- RSN_MODE_WPA
- RSN_MODE_WPA2
- RSN_OUI
- RSN_PMKID_COUNT_LEN
- RSN_SELECTOR_LEN
- RSNoxNo
- RSO
- RSP
- RSPCK0_MARK
- RSPCK0_PB17_MARK
- RSPCK0_PJ16_MARK
- RSPCK1_MARK
- RSPDIF
- RSPD_CTRL_MASK
- RSPD_GEN_S
- RSPD_GTS_MASK
- RSPD_LEN_G
- RSPD_LEN_M
- RSPD_LEN_S
- RSPD_NEWBUF_F
- RSPD_NEWBUF_S
- RSPD_NEWBUF_V
- RSPD_QID_G
- RSPD_QID_M
- RSPD_QID_S
- RSPD_TYPE_CPL_X
- RSPD_TYPE_FLBUF_X
- RSPD_TYPE_G
- RSPD_TYPE_INTR_X
- RSPD_TYPE_M
- RSPD_TYPE_S
- RSPEC_BW_MASK
- RSPEC_BW_SHIFT
- RSPEC_CT_MASK
- RSPEC_CT_SHIFT
- RSPEC_LDPC_CODING
- RSPEC_MIMORATE
- RSPEC_OVERRIDE
- RSPEC_OVERRIDE_MCS_ONLY
- RSPEC_RATE_MASK
- RSPEC_SHORT_GI
- RSPEC_STC_MASK
- RSPEC_STC_SHIFT
- RSPEC_STF_MASK
- RSPEC_STF_SHIFT
- RSPI
- RSPIC0
- RSPIC1
- RSPI_CK_A_MARK
- RSPI_MISO_A_MARK
- RSPI_MOSI_A_MARK
- RSPI_NUM_SPCMD
- RSPI_RSPCK_A_MARK
- RSPI_RZ_NUM_SPCMD
- RSPI_SPBFCR
- RSPI_SPBFDR
- RSPI_SPBR
- RSPI_SPCKD
- RSPI_SPCMD
- RSPI_SPCMD0
- RSPI_SPCMD1
- RSPI_SPCMD2
- RSPI_SPCMD3
- RSPI_SPCMD4
- RSPI_SPCMD5
- RSPI_SPCMD6
- RSPI_SPCMD7
- RSPI_SPCR
- RSPI_SPCR2
- RSPI_SPDCR
- RSPI_SPDR
- RSPI_SPND
- RSPI_SPPCR
- RSPI_SPSCR
- RSPI_SPSR
- RSPI_SPSSR
- RSPI_SSL0_A_MARK
- RSPI_SSL1_A_MARK
- RSPI_SSL2_A_MARK
- RSPI_SSL3_A_MARK
- RSPI_SSLND
- RSPI_SSLP
- RSPI_SSL_A_MARK
- RSPMBXAVAIL
- RSPN_REQUEST_SZ
- RSPOVRLOOKUPINT_F
- RSPOVRLOOKUPINT_S
- RSPOVRLOOKUPINT_V
- RSPQ_AN
- RSPQ_CQBRANCH
- RSPQ_CQID
- RSPQ_CQPTR
- RSPQ_CREDIT_THRESH
- RSPQ_E_DB_READY
- RSPQ_E_FAIL
- RSPQ_E_INIT_RESP
- RSPQ_E_RESP
- RSPQ_E_START
- RSPQ_E_STOP
- RSPQ_GENBIT
- RSPQ_HASH_BITS
- RSPQ_NOTIFY
- RSPQ_OVERFLOW
- RSPQ_SE
- RSPSAVE
- RSP_ANY
- RSP_CMD_APP
- RSP_CMD_FIELD_ERR
- RSP_CMD_IDX_MASK
- RSP_CRC_FAIL
- RSP_CRC_OK
- RSP_DATA
- RSP_DATA_BURST_ERR
- RSP_DATA_IDX
- RSP_ERROR
- RSP_ID
- RSP_ID_MASK
- RSP_INFO_PRN
- RSP_INIT
- RSP_INVAL
- RSP_KEYBOARD_DATA
- RSP_LAST
- RSP_LEN_VALID
- RSP_NMBR
- RSP_NODEV
- RSP_NONE
- RSP_NO_FAILURE
- RSP_NULL
- RSP_OK
- RSP_OVER
- RSP_RADIO_CMD
- RSP_RADIO_RDDAT
- RSP_RING
- RSP_RO_MISMATCH_ERR
- RSP_STR
- RSP_STRING
- RSP_TIMEOUT
- RSP_TMF_FAILED
- RSP_TMF_INVALID_LUN
- RSP_TMF_REJECTED
- RSP_TM_INVALID_LU
- RSP_TM_NOT_COMPLETED
- RSP_TM_NOT_SUPPORTED
- RSP_TOUCHPAD_DATA
- RSP_TYPE
- RSP_TYPE_CPL
- RSP_TYPE_FLBUF
- RSP_TYPE_INTR
- RSP_TYPE_MASK
- RSP_TYPE_SHIFT
- RSP_VAR
- RSP_WRONG_CID
- RSP_ZBC
- RSP_ZCAU
- RSP_ZCON
- RSP_ZCPN
- RSP_ZCTP
- RSP_ZDLE
- RSP_ZGCI
- RSP_ZHLC
- RSP_ZSAU
- RSP_ZVLS
- RSQ
- RSQB
- RSQH
- RSQSIZE
- RSQT
- RSQ_ALIGNMENT
- RSQ_NUM_ENTRIES
- RSR
- RSR0_AAL0
- RSR0_AAL0_SDU
- RSR0_AAL5
- RSR0_CLOSE_CONN
- RSR0_EPD_ENABLE
- RSR0_OPEN_CONN
- RSR0_PPD_ENABLE
- RSR0_RAWCELL
- RSR0_RAWCELL_CRC10
- RSR0_START_PDU
- RSR0_TCP_CKSUM
- RSR1_AQI_ENABLE
- RSR1_GROUP
- RSR1_RBPL_ONLY
- RSR4_AQI_ENABLE
- RSR4_GROUP
- RSR4_RBPL_ONLY
- RSRC
- RSRC_BUF_SIZE
- RSRR
- RSRR_SWR
- RSR_11M
- RSR_12M
- RSR_18M
- RSR_1M
- RSR_24M
- RSR_2M
- RSR_36M
- RSR_48M
- RSR_54M
- RSR_5_5M
- RSR_6M
- RSR_9M
- RSR_ACK_SHORT_PREAMBLE
- RSR_ADDRBROAD
- RSR_ADDRMULTI
- RSR_ADDROK
- RSR_ADDRUNI
- RSR_AE
- RSR_BAR
- RSR_BCNSSIDOK
- RSR_BSSIDOK
- RSR_CE
- RSR_CRC
- RSR_CRCOK
- RSR_DE
- RSR_DETAG
- RSR_DI
- RSR_EDP
- RSR_ERRORS
- RSR_FAE
- RSR_FOE
- RSR_IVLDLEN
- RSR_IVLDTYP
- RSR_LCS
- RSR_MAR
- RSR_MCS0
- RSR_MCS1
- RSR_MCS2
- RSR_MCS3
- RSR_MCS4
- RSR_MCS5
- RSR_MCS6
- RSR_MCS7
- RSR_MF
- RSR_PFT
- RSR_PHY
- RSR_PLE
- RSR_RF
- RSR_RI
- RSR_RL
- RSR_RO
- RSR_RSC_BANDWIDTH_40M
- RSR_RSC_LOWER_SUB_CHANNEL
- RSR_RSC_UPPER_SUB_CHANNEL
- RSR_RWTO
- RSR_RXEMPTY
- RSR_RXER
- RSR_RXOK
- RSR_SNTAG
- RSR_STARY
- RSR_STDRY
- RSR_STP
- RSR_VIDM
- RSR_VTAG
- RSResolution
- RSS
- RSS1
- RSS2
- RSSCONTROL_S
- RSSCONTROL_V
- RSSE_ALIGN
- RSSI_ANT_MERGE_AVG
- RSSI_ANT_MERGE_MAX
- RSSI_ANT_MERGE_MIN
- RSSI_BLOCK_SCAN_DATA_GET
- RSSI_BLOCK_SCAN_FREQ_SET
- RSSI_BLOCK_SCAN_START
- RSSI_CCK
- RSSI_DEFAULT
- RSSI_EVENT
- RSSI_EVENT_HIGH
- RSSI_EVENT_LOW
- RSSI_HIGH_RECVD
- RSSI_LEVEL_BITMASK
- RSSI_LOW_RECVD
- RSSI_LPF_THRESHOLD
- RSSI_LVL_GET
- RSSI_MODE
- RSSI_OFDM
- RSSI_OFFSET
- RSSI_OFFSET_DIG
- RSSI_SNR_TRIGGER_0_EVENT_ID
- RSSI_SNR_TRIGGER_1_EVENT_ID
- RSSI_SNR_TRIGGER_2_EVENT_ID
- RSSI_SNR_TRIGGER_3_EVENT_ID
- RSSI_SNR_TRIGGER_4_EVENT_ID
- RSSI_SNR_TRIGGER_5_EVENT_ID
- RSSI_SNR_TRIGGER_6_EVENT_ID
- RSSI_SNR_TRIGGER_7_EVENT_ID
- RSSI_STA
- RSSI_VALID
- RSSV
- RSS_ALG_GRE_IP
- RSS_ALG_IP
- RSS_ALG_NONE
- RSS_ALG_PORT
- RSS_ALG_ROCE
- RSS_ALG_SCTP_IP
- RSS_ALG_TCP_IP
- RSS_ALG_UDP_IP
- RSS_AQ
- RSS_CAPABLE
- RSS_CFG
- RSS_CONFIG_CMD
- RSS_CONTEXT_FLAGS_DEFAULT
- RSS_CTRL0
- RSS_ENABLE_IPV4
- RSS_ENABLE_IPV6
- RSS_ENABLE_NONE
- RSS_ENABLE_TCP_IPV4
- RSS_ENABLE_TCP_IPV6
- RSS_ENABLE_UDP_IPV4
- RSS_ENABLE_UDP_IPV6
- RSS_HASHTYPE_IP_TCP
- RSS_HASH_2_TUPLE
- RSS_HASH_4_TUPLE
- RSS_HASH_EN
- RSS_HASH_IP
- RSS_HASH_KEY_LEN
- RSS_HASH_KEY_SIZE
- RSS_HASH_L2ETC
- RSS_HASH_L4ETC
- RSS_HASH_NONE
- RSS_HASH_ROCE
- RSS_HASH_TCP
- RSS_HASH_TCPV6
- RSS_HASH_TCP_SYN_DIS
- RSS_HASH_TYPE_DEFAULT
- RSS_HASH_TYPE_IPV4
- RSS_HASH_TYPE_IPV6
- RSS_HASH_TYPE_TCP_IPV4
- RSS_HASH_TYPE_TCP_IPV6
- RSS_HASH_TYPE_UDP_IPV4
- RSS_HASH_TYPE_UDP_IPV6
- RSS_HASH_UDP
- RSS_HDR
- RSS_IDT
- RSS_INDIR_TABLE_LEN
- RSS_IND_TBL_LEN_PER_MBX_MSG
- RSS_IPV4_12B
- RSS_IPV4_8B
- RSS_IPV4_CAP_MASK
- RSS_IPV4_HASH_SKEY
- RSS_IPV4_OTHERS_NODE
- RSS_IPV4_TCP_CAP_MASK
- RSS_IPV4_TCP_NODE
- RSS_IPV4_UDP_NODE
- RSS_IPV6_CAP_MASK
- RSS_IPV6_TCP_CAP_MASK
- RSS_IP_HASH_ENA
- RSS_KEY
- RSS_L2_EXTENDED_HASH_ENA
- RSS_L3_BIDI
- RSS_L3_BI_DIRECTION_ENA
- RSS_L4K
- RSS_L4_BIDI
- RSS_L4_BI_DIRECTION_ENA
- RSS_L4_EXTENDED_HASH_ENA
- RSS_L6K
- RSS_LB
- RSS_LI
- RSS_LM
- RSS_MODE_DIS
- RSS_MODE_HASH_ADDRS
- RSS_MODE_HASH_DST_ADDR_LBN
- RSS_MODE_HASH_DST_ADDR_WIDTH
- RSS_MODE_HASH_DST_PORT_LBN
- RSS_MODE_HASH_DST_PORT_WIDTH
- RSS_MODE_HASH_PORTS
- RSS_MODE_HASH_SELECTOR_LBN
- RSS_MODE_HASH_SELECTOR_LEN
- RSS_MODE_HASH_SELECTOR_OFST
- RSS_MODE_HASH_SELECTOR_WIDTH
- RSS_MODE_HASH_SRC_ADDR_LBN
- RSS_MODE_HASH_SRC_ADDR_WIDTH
- RSS_MODE_HASH_SRC_PORT_LBN
- RSS_MODE_HASH_SRC_PORT_WIDTH
- RSS_MODE_LEN
- RSS_MODE_MASK
- RSS_MODE_MQMI
- RSS_MODE_MQSI
- RSS_MODE_SHIFT
- RSS_MODE_SQSI
- RSS_NENTRIES
- RSS_NIP_QUEUE_SEL
- RSS_PF
- RSS_PROFILE_ID_MASK
- RSS_QUEUE_G
- RSS_QUEUE_M
- RSS_QUEUE_S
- RSS_QUEUE_V
- RSS_QUEUE_VALID_F
- RSS_QUEUE_VALID_S
- RSS_QUEUE_VALID_V
- RSS_REG
- RSS_REG_DBG_DWORD_ENABLE
- RSS_REG_DBG_FORCE_FRAME
- RSS_REG_DBG_FORCE_VALID
- RSS_REG_DBG_SELECT
- RSS_REG_DBG_SHIFT
- RSS_REG_RSS_INIT_EN
- RSS_REG_RSS_RAM_ADDR
- RSS_REG_RSS_RAM_DATA
- RSS_REG_RSS_RAM_DATA_SIZE
- RSS_RI4
- RSS_RI6
- RSS_ROCE_ENA
- RSS_RT4
- RSS_RT6
- RSS_TABLE_SIZE
- RSS_TCP_HASH_ENA
- RSS_TCP_SYN_DIS
- RSS_UDP_HASH_ENA
- RST
- RST0_POR_PICOPHY
- RST0_USBOTG
- RST0_USBOTG_32K
- RST0_USBOTG_BUS
- RSTA
- RSTANDBY
- RSTAT0_AM
- RSTAT0_CRCE
- RSTAT0_CRCI
- RSTAT0_EDATA
- RSTAT0_EOB
- RSTAT0_EOF
- RSTAT0_FE
- RSTAT0_HTI
- RSTAT0_OE
- RSTAT0_RFP
- RSTAT0_RUNT
- RSTAT0_RWE
- RSTAT0_RX_ERR
- RSTAT1_BUFFER_INDEX
- RSTAT1_FRAME_LENGTH
- RSTAT1_RFP
- RSTATE
- RSTAT_CLEAR_RHALT
- RSTAT_CLEAR_RXF0
- RSTAT_GO_BITS
- RSTAT_RXF_MASK
- RSTA_DONE_EN
- RSTA_DONE_MASK
- RSTA_DONE_ST
- RSTB_MODE_DETECT
- RSTCHN0_F
- RSTCHN0_S
- RSTCHN0_V
- RSTCHN1_F
- RSTCHN1_S
- RSTCHN1_V
- RSTCHN2_F
- RSTCHN2_S
- RSTCHN2_V
- RSTCHN3_F
- RSTCHN3_S
- RSTCHN3_V
- RSTCSR
- RSTCSR_R
- RSTCSR_RSTS
- RSTCTL_RESET_PCI
- RSTCTL_RESET_SYSTEM
- RSTCTL_RST_CHIP
- RSTCTL_RST_FAB
- RSTCTL_RST_SYS
- RSTCTL_RST_ZERO
- RSTCTRL
- RSTCTRL_FE
- RSTCTRL_PPE
- RSTDBYCTL
- RSTFIFO
- RSTINTCTL
- RSTMGR_CTRL_SWCOLDRSTREQ
- RSTMGR_CTRL_SWWARMRSTREQ
- RSTMGR_MPUMODRST_CPU1
- RSTMGR_REG_CHIP_SOFT_RST_OFFSET
- RSTMGR_REG_WR_ACCESS_OFFSET
- RSTMGR_WR_ACCESS_ENABLE
- RSTMGR_WR_PASSWORD
- RSTMGR_WR_PASSWORD_SHIFT
- RSTN
- RSTOUTn_MASK
- RSTOUTn_MASK_PHYS
- RSTPWRDWN
- RSTROBE
- RSTROBE_MAX
- RSTROBE_SHIFT
- RSTROBE_VAL
- RSTST
- RSTV0910_BCHERR
- RSTV0910_CFGEXT
- RSTV0910_DACR1
- RSTV0910_DACR2
- RSTV0910_DID
- RSTV0910_FILTCTRL
- RSTV0910_FSKRAGC
- RSTV0910_FSKRAGCR
- RSTV0910_FSKRALPHA
- RSTV0910_FSKRDET0
- RSTV0910_FSKRDET1
- RSTV0910_FSKRDF0
- RSTV0910_FSKRDF1
- RSTV0910_FSKRDTH0
- RSTV0910_FSKRDTH1
- RSTV0910_FSKRFC0
- RSTV0910_FSKRFC1
- RSTV0910_FSKRFC2
- RSTV0910_FSKRK1
- RSTV0910_FSKRK2
- RSTV0910_FSKRLOSS
- RSTV0910_FSKRPLTH0
- RSTV0910_FSKRPLTH1
- RSTV0910_FSKRSTEPM
- RSTV0910_FSKRSTEPP
- RSTV0910_FSKTCTRL
- RSTV0910_FSKTDELTAF0
- RSTV0910_FSKTDELTAF1
- RSTV0910_FSKTFC0
- RSTV0910_FSKTFC1
- RSTV0910_FSKTFC2
- RSTV0910_GAINLLR_NF1
- RSTV0910_GAINLLR_NF10
- RSTV0910_GAINLLR_NF11
- RSTV0910_GAINLLR_NF12
- RSTV0910_GAINLLR_NF13
- RSTV0910_GAINLLR_NF14
- RSTV0910_GAINLLR_NF15
- RSTV0910_GAINLLR_NF16
- RSTV0910_GAINLLR_NF17
- RSTV0910_GAINLLR_NF18
- RSTV0910_GAINLLR_NF19
- RSTV0910_GAINLLR_NF2
- RSTV0910_GAINLLR_NF20
- RSTV0910_GAINLLR_NF21
- RSTV0910_GAINLLR_NF22
- RSTV0910_GAINLLR_NF23
- RSTV0910_GAINLLR_NF24
- RSTV0910_GAINLLR_NF25
- RSTV0910_GAINLLR_NF26
- RSTV0910_GAINLLR_NF27
- RSTV0910_GAINLLR_NF28
- RSTV0910_GAINLLR_NF3
- RSTV0910_GAINLLR_NF4
- RSTV0910_GAINLLR_NF5
- RSTV0910_GAINLLR_NF6
- RSTV0910_GAINLLR_NF7
- RSTV0910_GAINLLR_NF8
- RSTV0910_GAINLLR_NF9
- RSTV0910_GAINLLR_SF1
- RSTV0910_GAINLLR_SF10
- RSTV0910_GAINLLR_SF12
- RSTV0910_GAINLLR_SF13
- RSTV0910_GAINLLR_SF14
- RSTV0910_GAINLLR_SF15
- RSTV0910_GAINLLR_SF16
- RSTV0910_GAINLLR_SF18
- RSTV0910_GAINLLR_SF19
- RSTV0910_GAINLLR_SF2
- RSTV0910_GAINLLR_SF20
- RSTV0910_GAINLLR_SF21
- RSTV0910_GAINLLR_SF22
- RSTV0910_GAINLLR_SF24
- RSTV0910_GAINLLR_SF25
- RSTV0910_GAINLLR_SF26
- RSTV0910_GAINLLR_SF27
- RSTV0910_GAINLLR_SF3
- RSTV0910_GAINLLR_SF4
- RSTV0910_GAINLLR_SF5
- RSTV0910_GAINLLR_SF6
- RSTV0910_GAINLLR_SF7
- RSTV0910_GAINLLR_SF8
- RSTV0910_GAINLLR_SF9
- RSTV0910_GENCFG
- RSTV0910_GPIO0CFG
- RSTV0910_GPIO10CFG
- RSTV0910_GPIO11CFG
- RSTV0910_GPIO12CFG
- RSTV0910_GPIO13CFG
- RSTV0910_GPIO14CFG
- RSTV0910_GPIO15CFG
- RSTV0910_GPIO16CFG
- RSTV0910_GPIO17CFG
- RSTV0910_GPIO18CFG
- RSTV0910_GPIO19CFG
- RSTV0910_GPIO1CFG
- RSTV0910_GPIO20CFG
- RSTV0910_GPIO21CFG
- RSTV0910_GPIO22CFG
- RSTV0910_GPIO2CFG
- RSTV0910_GPIO3CFG
- RSTV0910_GPIO4CFG
- RSTV0910_GPIO5CFG
- RSTV0910_GPIO6CFG
- RSTV0910_GPIO7CFG
- RSTV0910_GPIO8CFG
- RSTV0910_GPIO9CFG
- RSTV0910_I2CCFG
- RSTV0910_IRQMASK0
- RSTV0910_IRQMASK1
- RSTV0910_IRQMASK2
- RSTV0910_IRQMASK3
- RSTV0910_IRQSTATUS0
- RSTV0910_IRQSTATUS1
- RSTV0910_IRQSTATUS2
- RSTV0910_IRQSTATUS3
- RSTV0910_LDPCERR0
- RSTV0910_LDPCERR1
- RSTV0910_MID
- RSTV0910_NCOARSE
- RSTV0910_NCOARSE1
- RSTV0910_NCOARSE2
- RSTV0910_OUTCFG
- RSTV0910_OUTCFG2
- RSTV0910_P1_ACLC
- RSTV0910_P1_ACLC2S216A
- RSTV0910_P1_ACLC2S232A
- RSTV0910_P1_ACLC2S28
- RSTV0910_P1_ACLC2S2Q
- RSTV0910_P1_ACLCS2
- RSTV0910_P1_ACRDIV
- RSTV0910_P1_ACRPRESC
- RSTV0910_P1_AGC1ADJ
- RSTV0910_P1_AGC1AMM
- RSTV0910_P1_AGC1CFG
- RSTV0910_P1_AGC1CN
- RSTV0910_P1_AGC1QUAD
- RSTV0910_P1_AGC1REF
- RSTV0910_P1_AGC2I0
- RSTV0910_P1_AGC2I1
- RSTV0910_P1_AGC2O
- RSTV0910_P1_AGC2REF
- RSTV0910_P1_AGCIQIN0
- RSTV0910_P1_AGCIQIN1
- RSTV0910_P1_AGCK16
- RSTV0910_P1_AGCK32
- RSTV0910_P1_AGCK8
- RSTV0910_P1_AGCKQ
- RSTV0910_P1_AGCKS
- RSTV0910_P1_AGCNADJ
- RSTV0910_P1_AGCR1ADJ
- RSTV0910_P1_AGCR2ADJ
- RSTV0910_P1_AGCR3ADJ
- RSTV0910_P1_AGCR8ADJ
- RSTV0910_P1_AGCREFADJ
- RSTV0910_P1_AGCRQADJ
- RSTV0910_P1_AGCRSADJ
- RSTV0910_P1_BBFCRCKO0
- RSTV0910_P1_BBFCRCKO1
- RSTV0910_P1_BCLC
- RSTV0910_P1_BCLC2S216A
- RSTV0910_P1_BCLC2S232A
- RSTV0910_P1_BCLC2S28
- RSTV0910_P1_BCLC2S2Q
- RSTV0910_P1_BCLCS2
- RSTV0910_P1_CAR2CFG
- RSTV0910_P1_CAR3CFG
- RSTV0910_P1_CARCFG
- RSTV0910_P1_CARFREQ
- RSTV0910_P1_CARHDR
- RSTV0910_P1_CCIACC
- RSTV0910_P1_CCIQUANT
- RSTV0910_P1_CCIR0
- RSTV0910_P1_CCITHRES
- RSTV0910_P1_CFR0
- RSTV0910_P1_CFR1
- RSTV0910_P1_CFR2
- RSTV0910_P1_CFR20
- RSTV0910_P1_CFR21
- RSTV0910_P1_CFR22
- RSTV0910_P1_CFR2CFR1
- RSTV0910_P1_CFRIBASE0
- RSTV0910_P1_CFRIBASE1
- RSTV0910_P1_CFRICFG
- RSTV0910_P1_CFRINC0
- RSTV0910_P1_CFRINC1
- RSTV0910_P1_CFRINIT0
- RSTV0910_P1_CFRINIT1
- RSTV0910_P1_CFRLOW0
- RSTV0910_P1_CFRLOW1
- RSTV0910_P1_CFRUP0
- RSTV0910_P1_CFRUP1
- RSTV0910_P1_CORRELABS
- RSTV0910_P1_CORRELEXP
- RSTV0910_P1_CORRELMANT
- RSTV0910_P1_DEMOD
- RSTV0910_P1_DFLSTR0
- RSTV0910_P1_DFLSTR1
- RSTV0910_P1_DISIRQCFG
- RSTV0910_P1_DISIRQSTAT
- RSTV0910_P1_DISRXBYTES
- RSTV0910_P1_DISRXCFG
- RSTV0910_P1_DISRXDC0
- RSTV0910_P1_DISRXDC1
- RSTV0910_P1_DISRXF100
- RSTV0910_P1_DISRXF220
- RSTV0910_P1_DISRXF221
- RSTV0910_P1_DISRXFIFO
- RSTV0910_P1_DISRXPARITY0
- RSTV0910_P1_DISRXPARITY1
- RSTV0910_P1_DISRXSHORT22K
- RSTV0910_P1_DISRXSTAT0
- RSTV0910_P1_DISRXSTAT1
- RSTV0910_P1_DISTIMEOCFG
- RSTV0910_P1_DISTIMEOUT
- RSTV0910_P1_DISTXBYTES
- RSTV0910_P1_DISTXCFG
- RSTV0910_P1_DISTXF22
- RSTV0910_P1_DISTXFIFO
- RSTV0910_P1_DISTXSTATUS
- RSTV0910_P1_DMDCFG2
- RSTV0910_P1_DMDCFG3
- RSTV0910_P1_DMDCFG4
- RSTV0910_P1_DMDCFGMD
- RSTV0910_P1_DMDFLYW
- RSTV0910_P1_DMDISTATE
- RSTV0910_P1_DMDMODCOD
- RSTV0910_P1_DMDPLHSTAT
- RSTV0910_P1_DMDREG
- RSTV0910_P1_DMDRESADR
- RSTV0910_P1_DMDRESCFG
- RSTV0910_P1_DMDRESDATA0
- RSTV0910_P1_DMDRESDATA1
- RSTV0910_P1_DMDRESDATA2
- RSTV0910_P1_DMDRESDATA3
- RSTV0910_P1_DMDRESDATA4
- RSTV0910_P1_DMDRESDATA5
- RSTV0910_P1_DMDRESDATA6
- RSTV0910_P1_DMDRESDATA7
- RSTV0910_P1_DMDSTATE
- RSTV0910_P1_DMDT0M
- RSTV0910_P1_DSTATUS
- RSTV0910_P1_DSTATUS2
- RSTV0910_P1_DSTATUS3
- RSTV0910_P1_DSTATUS4
- RSTV0910_P1_EQUAI1
- RSTV0910_P1_EQUAI2
- RSTV0910_P1_EQUAI3
- RSTV0910_P1_EQUAI4
- RSTV0910_P1_EQUAI5
- RSTV0910_P1_EQUAI6
- RSTV0910_P1_EQUAI7
- RSTV0910_P1_EQUAI8
- RSTV0910_P1_EQUALCFG
- RSTV0910_P1_EQUAQ1
- RSTV0910_P1_EQUAQ2
- RSTV0910_P1_EQUAQ3
- RSTV0910_P1_EQUAQ4
- RSTV0910_P1_EQUAQ5
- RSTV0910_P1_EQUAQ6
- RSTV0910_P1_EQUAQ7
- RSTV0910_P1_EQUAQ8
- RSTV0910_P1_ERRCNT10
- RSTV0910_P1_ERRCNT11
- RSTV0910_P1_ERRCNT12
- RSTV0910_P1_ERRCNT20
- RSTV0910_P1_ERRCNT21
- RSTV0910_P1_ERRCNT22
- RSTV0910_P1_ERRCTRL1
- RSTV0910_P1_ERRCTRL2
- RSTV0910_P1_FBERCPT0
- RSTV0910_P1_FBERCPT1
- RSTV0910_P1_FBERCPT2
- RSTV0910_P1_FBERCPT3
- RSTV0910_P1_FBERCPT4
- RSTV0910_P1_FBERERR0
- RSTV0910_P1_FBERERR1
- RSTV0910_P1_FBERERR2
- RSTV0910_P1_FECM
- RSTV0910_P1_FECSPY
- RSTV0910_P1_FFECFG
- RSTV0910_P1_FFEI1
- RSTV0910_P1_FFEI2
- RSTV0910_P1_FFEI3
- RSTV0910_P1_FFEI4
- RSTV0910_P1_FFEQ1
- RSTV0910_P1_FFEQ2
- RSTV0910_P1_FFEQ3
- RSTV0910_P1_FFEQ4
- RSTV0910_P1_FSPYBER
- RSTV0910_P1_FSPYCFG
- RSTV0910_P1_FSPYDATA
- RSTV0910_P1_FSPYOUT
- RSTV0910_P1_FSTATUS
- RSTV0910_P1_GAUSSR0
- RSTV0910_P1_HYSTTHRESH
- RSTV0910_P1_I2CRPT
- RSTV0910_P1_IDCCOMP
- RSTV0910_P1_IQCONST
- RSTV0910_P1_ISIBITENA
- RSTV0910_P1_ISIENTRY
- RSTV0910_P1_ISYMB
- RSTV0910_P1_KDIV12
- RSTV0910_P1_KDIV23
- RSTV0910_P1_KDIV34
- RSTV0910_P1_KDIV56
- RSTV0910_P1_KDIV67
- RSTV0910_P1_KDIV78
- RSTV0910_P1_KREFTMG
- RSTV0910_P1_KREFTMG2
- RSTV0910_P1_KTTMG
- RSTV0910_P1_LDI
- RSTV0910_P1_LDT
- RSTV0910_P1_LDT2
- RSTV0910_P1_LOCKTIME0
- RSTV0910_P1_LOCKTIME1
- RSTV0910_P1_LOCKTIME2
- RSTV0910_P1_LOCKTIME3
- RSTV0910_P1_MATSTR0
- RSTV0910_P1_MATSTR1
- RSTV0910_P1_MAXEXTRAITER
- RSTV0910_P1_MODCODLST0
- RSTV0910_P1_MODCODLST1
- RSTV0910_P1_MODCODLST2
- RSTV0910_P1_MODCODLST3
- RSTV0910_P1_MODCODLST4
- RSTV0910_P1_MODCODLST5
- RSTV0910_P1_MODCODLST6
- RSTV0910_P1_MODCODLST7
- RSTV0910_P1_MODCODLST8
- RSTV0910_P1_MODCODLST9
- RSTV0910_P1_MODCODLSTA
- RSTV0910_P1_MODCODLSTB
- RSTV0910_P1_MODCODLSTC
- RSTV0910_P1_MODCODLSTD
- RSTV0910_P1_MODCODLSTE
- RSTV0910_P1_MODCODLSTF
- RSTV0910_P1_NBITER_NF1
- RSTV0910_P1_NBITER_NF10
- RSTV0910_P1_NBITER_NF11
- RSTV0910_P1_NBITER_NF12
- RSTV0910_P1_NBITER_NF13
- RSTV0910_P1_NBITER_NF14
- RSTV0910_P1_NBITER_NF15
- RSTV0910_P1_NBITER_NF16
- RSTV0910_P1_NBITER_NF17
- RSTV0910_P1_NBITER_NF18
- RSTV0910_P1_NBITER_NF19
- RSTV0910_P1_NBITER_NF2
- RSTV0910_P1_NBITER_NF20
- RSTV0910_P1_NBITER_NF21
- RSTV0910_P1_NBITER_NF22
- RSTV0910_P1_NBITER_NF23
- RSTV0910_P1_NBITER_NF24
- RSTV0910_P1_NBITER_NF25
- RSTV0910_P1_NBITER_NF26
- RSTV0910_P1_NBITER_NF27
- RSTV0910_P1_NBITER_NF28
- RSTV0910_P1_NBITER_NF3
- RSTV0910_P1_NBITER_NF4
- RSTV0910_P1_NBITER_NF5
- RSTV0910_P1_NBITER_NF6
- RSTV0910_P1_NBITER_NF7
- RSTV0910_P1_NBITER_NF8
- RSTV0910_P1_NBITER_NF9
- RSTV0910_P1_NBITER_SF1
- RSTV0910_P1_NBITER_SF10
- RSTV0910_P1_NBITER_SF12
- RSTV0910_P1_NBITER_SF13
- RSTV0910_P1_NBITER_SF14
- RSTV0910_P1_NBITER_SF15
- RSTV0910_P1_NBITER_SF16
- RSTV0910_P1_NBITER_SF18
- RSTV0910_P1_NBITER_SF19
- RSTV0910_P1_NBITER_SF2
- RSTV0910_P1_NBITER_SF20
- RSTV0910_P1_NBITER_SF21
- RSTV0910_P1_NBITER_SF22
- RSTV0910_P1_NBITER_SF24
- RSTV0910_P1_NBITER_SF25
- RSTV0910_P1_NBITER_SF26
- RSTV0910_P1_NBITER_SF27
- RSTV0910_P1_NBITER_SF3
- RSTV0910_P1_NBITER_SF4
- RSTV0910_P1_NBITER_SF5
- RSTV0910_P1_NBITER_SF6
- RSTV0910_P1_NBITER_SF7
- RSTV0910_P1_NBITER_SF8
- RSTV0910_P1_NBITER_SF9
- RSTV0910_P1_NNOSDATA0
- RSTV0910_P1_NNOSDATA1
- RSTV0910_P1_NNOSDATAT0
- RSTV0910_P1_NNOSDATAT1
- RSTV0910_P1_NNOSFRAME0
- RSTV0910_P1_NNOSFRAME1
- RSTV0910_P1_NNOSPLH0
- RSTV0910_P1_NNOSPLH1
- RSTV0910_P1_NNOSPLHT0
- RSTV0910_P1_NNOSPLHT1
- RSTV0910_P1_NNOSRAD0
- RSTV0910_P1_NNOSRAD1
- RSTV0910_P1_NOSCFG
- RSTV0910_P1_NOSCFGF1
- RSTV0910_P1_NOSCFGF2
- RSTV0910_P1_NOSDATAT0
- RSTV0910_P1_NOSDATAT1
- RSTV0910_P1_NOSDIFF1
- RSTV0910_P1_NOSRAMCFG
- RSTV0910_P1_NOSRAMPOS
- RSTV0910_P1_NOSRAMVAL
- RSTV0910_P1_NOSTHRES1
- RSTV0910_P1_NOSTHRES2
- RSTV0910_P1_PDELCTRL0
- RSTV0910_P1_PDELCTRL1
- RSTV0910_P1_PDELCTRL2
- RSTV0910_P1_PDELCTRL3
- RSTV0910_P1_PDELSTATUS1
- RSTV0910_P1_PDELSTATUS2
- RSTV0910_P1_PLHMODCOD
- RSTV0910_P1_PLROOT0
- RSTV0910_P1_PLROOT1
- RSTV0910_P1_PLROOT2
- RSTV0910_P1_POWERI
- RSTV0910_P1_POWERQ
- RSTV0910_P1_PRVIT
- RSTV0910_P1_QDCCOMP
- RSTV0910_P1_QSYMB
- RSTV0910_P1_RAINFADE
- RSTV0910_P1_RTC
- RSTV0910_P1_RTCS2
- RSTV0910_P1_SFDLYSET2
- RSTV0910_P1_SFECSTATUS
- RSTV0910_P1_SFERRCNT0
- RSTV0910_P1_SFERRCNT1
- RSTV0910_P1_SFERRCNT2
- RSTV0910_P1_SFERRCTRL
- RSTV0910_P1_SFERROR
- RSTV0910_P1_SFKDIV12
- RSTV0910_P1_SFKDIV23
- RSTV0910_P1_SFKDIV34
- RSTV0910_P1_SFKDIV56
- RSTV0910_P1_SFKDIV67
- RSTV0910_P1_SFKDIV78
- RSTV0910_P1_SFR0
- RSTV0910_P1_SFR1
- RSTV0910_P1_SFR2
- RSTV0910_P1_SFR3
- RSTV0910_P1_SFRINIT0
- RSTV0910_P1_SFRINIT1
- RSTV0910_P1_SFRLOW0
- RSTV0910_P1_SFRLOW1
- RSTV0910_P1_SFRLOWRATIO
- RSTV0910_P1_SFRSTEP
- RSTV0910_P1_SFRUP0
- RSTV0910_P1_SFRUP1
- RSTV0910_P1_SFRUPRATIO
- RSTV0910_P1_SFSTATUS
- RSTV0910_P1_SMAPCOEF0
- RSTV0910_P1_SMAPCOEF1
- RSTV0910_P1_SMAPCOEF2
- RSTV0910_P1_SMAPCOEF3
- RSTV0910_P1_SMAPCOEF4
- RSTV0910_P1_SMAPCOEF5
- RSTV0910_P1_SMAPCOEF6
- RSTV0910_P1_SMAPCOEF7
- RSTV0910_P1_STATUSITER
- RSTV0910_P1_STATUSMAXITER
- RSTV0910_P1_SYNCDSTR0
- RSTV0910_P1_SYNCDSTR1
- RSTV0910_P1_SYNCSTR
- RSTV0910_P1_TCTL1
- RSTV0910_P1_TCTL4
- RSTV0910_P1_TMGCFG
- RSTV0910_P1_TMGCFG2
- RSTV0910_P1_TMGCFG3
- RSTV0910_P1_TMGLOCK0
- RSTV0910_P1_TMGLOCK1
- RSTV0910_P1_TMGOBS
- RSTV0910_P1_TMGREG0
- RSTV0910_P1_TMGREG1
- RSTV0910_P1_TMGREG2
- RSTV0910_P1_TMGTHFALL
- RSTV0910_P1_TMGTHRISE
- RSTV0910_P1_TNRCFG2
- RSTV0910_P1_TPKTDELIN
- RSTV0910_P1_TSBITRATE0
- RSTV0910_P1_TSBITRATE1
- RSTV0910_P1_TSBUFSTAT0
- RSTV0910_P1_TSBUFSTAT1
- RSTV0910_P1_TSBUFSTAT2
- RSTV0910_P1_TSCFG4
- RSTV0910_P1_TSCFGH
- RSTV0910_P1_TSCFGL
- RSTV0910_P1_TSCFGM
- RSTV0910_P1_TSDEBUGL
- RSTV0910_P1_TSDIVN
- RSTV0910_P1_TSDLY0
- RSTV0910_P1_TSDLY1
- RSTV0910_P1_TSDLY2
- RSTV0910_P1_TSDLYSET0
- RSTV0910_P1_TSDLYSET1
- RSTV0910_P1_TSDLYSET2
- RSTV0910_P1_TSINSDELH
- RSTV0910_P1_TSINSDELL
- RSTV0910_P1_TSINSDELM
- RSTV0910_P1_TSNPDAV
- RSTV0910_P1_TSPACKLEN1
- RSTV0910_P1_TSPIDFLT0
- RSTV0910_P1_TSPIDFLT1
- RSTV0910_P1_TSSPEED
- RSTV0910_P1_TSSTATEL
- RSTV0910_P1_TSSTATEM
- RSTV0910_P1_TSSTATUS
- RSTV0910_P1_TSSTATUS2
- RSTV0910_P1_TSSYNC
- RSTV0910_P1_TSTDMD
- RSTV0910_P1_UPCRCKO0
- RSTV0910_P1_UPCRCKO1
- RSTV0910_P1_UPLCCST0
- RSTV0910_P1_UPLSTR0
- RSTV0910_P1_UPLSTR1
- RSTV0910_P1_VAVSRVIT
- RSTV0910_P1_VERROR
- RSTV0910_P1_VITCURPUN
- RSTV0910_P1_VITSCALE
- RSTV0910_P1_VSTATUSVIT
- RSTV0910_P1_VTH12
- RSTV0910_P1_VTH23
- RSTV0910_P1_VTH34
- RSTV0910_P1_VTH56
- RSTV0910_P1_VTH67
- RSTV0910_P1_VTH78
- RSTV0910_P1_VTHINUSE
- RSTV0910_P2_ACLC
- RSTV0910_P2_ACLC2S216A
- RSTV0910_P2_ACLC2S232A
- RSTV0910_P2_ACLC2S28
- RSTV0910_P2_ACLC2S2Q
- RSTV0910_P2_ACLCS2
- RSTV0910_P2_ACRDIV
- RSTV0910_P2_ACRPRESC
- RSTV0910_P2_AGC1ADJ
- RSTV0910_P2_AGC1AMM
- RSTV0910_P2_AGC1CFG
- RSTV0910_P2_AGC1CN
- RSTV0910_P2_AGC1QUAD
- RSTV0910_P2_AGC1REF
- RSTV0910_P2_AGC2I0
- RSTV0910_P2_AGC2I1
- RSTV0910_P2_AGC2O
- RSTV0910_P2_AGC2REF
- RSTV0910_P2_AGCIQIN0
- RSTV0910_P2_AGCIQIN1
- RSTV0910_P2_AGCK16
- RSTV0910_P2_AGCK32
- RSTV0910_P2_AGCK8
- RSTV0910_P2_AGCKQ
- RSTV0910_P2_AGCKS
- RSTV0910_P2_AGCNADJ
- RSTV0910_P2_AGCR1ADJ
- RSTV0910_P2_AGCR2ADJ
- RSTV0910_P2_AGCR3ADJ
- RSTV0910_P2_AGCR8ADJ
- RSTV0910_P2_AGCREFADJ
- RSTV0910_P2_AGCRQADJ
- RSTV0910_P2_AGCRSADJ
- RSTV0910_P2_BBFCRCKO0
- RSTV0910_P2_BBFCRCKO1
- RSTV0910_P2_BCLC
- RSTV0910_P2_BCLC2S216A
- RSTV0910_P2_BCLC2S232A
- RSTV0910_P2_BCLC2S28
- RSTV0910_P2_BCLC2S2Q
- RSTV0910_P2_BCLCS2
- RSTV0910_P2_CAR2CFG
- RSTV0910_P2_CAR3CFG
- RSTV0910_P2_CARCFG
- RSTV0910_P2_CARFREQ
- RSTV0910_P2_CARHDR
- RSTV0910_P2_CCIACC
- RSTV0910_P2_CCIQUANT
- RSTV0910_P2_CCIR0
- RSTV0910_P2_CCITHRES
- RSTV0910_P2_CFR0
- RSTV0910_P2_CFR1
- RSTV0910_P2_CFR2
- RSTV0910_P2_CFR20
- RSTV0910_P2_CFR21
- RSTV0910_P2_CFR22
- RSTV0910_P2_CFR2CFR1
- RSTV0910_P2_CFRIBASE0
- RSTV0910_P2_CFRIBASE1
- RSTV0910_P2_CFRICFG
- RSTV0910_P2_CFRINC0
- RSTV0910_P2_CFRINC1
- RSTV0910_P2_CFRINIT0
- RSTV0910_P2_CFRINIT1
- RSTV0910_P2_CFRLOW0
- RSTV0910_P2_CFRLOW1
- RSTV0910_P2_CFRUP0
- RSTV0910_P2_CFRUP1
- RSTV0910_P2_CORRELABS
- RSTV0910_P2_CORRELEXP
- RSTV0910_P2_CORRELMANT
- RSTV0910_P2_DEMOD
- RSTV0910_P2_DFLSTR0
- RSTV0910_P2_DFLSTR1
- RSTV0910_P2_DISIRQCFG
- RSTV0910_P2_DISIRQSTAT
- RSTV0910_P2_DISRXBYTES
- RSTV0910_P2_DISRXCFG
- RSTV0910_P2_DISRXDC0
- RSTV0910_P2_DISRXDC1
- RSTV0910_P2_DISRXF100
- RSTV0910_P2_DISRXF220
- RSTV0910_P2_DISRXF221
- RSTV0910_P2_DISRXFIFO
- RSTV0910_P2_DISRXPARITY0
- RSTV0910_P2_DISRXPARITY1
- RSTV0910_P2_DISRXSHORT22K
- RSTV0910_P2_DISRXSTAT0
- RSTV0910_P2_DISRXSTAT1
- RSTV0910_P2_DISTIMEOCFG
- RSTV0910_P2_DISTIMEOUT
- RSTV0910_P2_DISTXBYTES
- RSTV0910_P2_DISTXCFG
- RSTV0910_P2_DISTXF22
- RSTV0910_P2_DISTXFIFO
- RSTV0910_P2_DISTXSTATUS
- RSTV0910_P2_DMDCFG2
- RSTV0910_P2_DMDCFG3
- RSTV0910_P2_DMDCFG4
- RSTV0910_P2_DMDCFGMD
- RSTV0910_P2_DMDFLYW
- RSTV0910_P2_DMDISTATE
- RSTV0910_P2_DMDMODCOD
- RSTV0910_P2_DMDPLHSTAT
- RSTV0910_P2_DMDREG
- RSTV0910_P2_DMDRESADR
- RSTV0910_P2_DMDRESCFG
- RSTV0910_P2_DMDRESDATA0
- RSTV0910_P2_DMDRESDATA1
- RSTV0910_P2_DMDRESDATA2
- RSTV0910_P2_DMDRESDATA3
- RSTV0910_P2_DMDRESDATA4
- RSTV0910_P2_DMDRESDATA5
- RSTV0910_P2_DMDRESDATA6
- RSTV0910_P2_DMDRESDATA7
- RSTV0910_P2_DMDSTATE
- RSTV0910_P2_DMDT0M
- RSTV0910_P2_DSTATUS
- RSTV0910_P2_DSTATUS2
- RSTV0910_P2_DSTATUS3
- RSTV0910_P2_DSTATUS4
- RSTV0910_P2_EQUAI1
- RSTV0910_P2_EQUAI2
- RSTV0910_P2_EQUAI3
- RSTV0910_P2_EQUAI4
- RSTV0910_P2_EQUAI5
- RSTV0910_P2_EQUAI6
- RSTV0910_P2_EQUAI7
- RSTV0910_P2_EQUAI8
- RSTV0910_P2_EQUALCFG
- RSTV0910_P2_EQUAQ1
- RSTV0910_P2_EQUAQ2
- RSTV0910_P2_EQUAQ3
- RSTV0910_P2_EQUAQ4
- RSTV0910_P2_EQUAQ5
- RSTV0910_P2_EQUAQ6
- RSTV0910_P2_EQUAQ7
- RSTV0910_P2_EQUAQ8
- RSTV0910_P2_ERRCNT10
- RSTV0910_P2_ERRCNT11
- RSTV0910_P2_ERRCNT12
- RSTV0910_P2_ERRCNT20
- RSTV0910_P2_ERRCNT21
- RSTV0910_P2_ERRCNT22
- RSTV0910_P2_ERRCTRL1
- RSTV0910_P2_ERRCTRL2
- RSTV0910_P2_FBERCPT0
- RSTV0910_P2_FBERCPT1
- RSTV0910_P2_FBERCPT2
- RSTV0910_P2_FBERCPT3
- RSTV0910_P2_FBERCPT4
- RSTV0910_P2_FBERERR0
- RSTV0910_P2_FBERERR1
- RSTV0910_P2_FBERERR2
- RSTV0910_P2_FECM
- RSTV0910_P2_FECSPY
- RSTV0910_P2_FFECFG
- RSTV0910_P2_FFEI1
- RSTV0910_P2_FFEI2
- RSTV0910_P2_FFEI3
- RSTV0910_P2_FFEI4
- RSTV0910_P2_FFEQ1
- RSTV0910_P2_FFEQ2
- RSTV0910_P2_FFEQ3
- RSTV0910_P2_FFEQ4
- RSTV0910_P2_FSPYBER
- RSTV0910_P2_FSPYCFG
- RSTV0910_P2_FSPYDATA
- RSTV0910_P2_FSPYOUT
- RSTV0910_P2_FSTATUS
- RSTV0910_P2_GAUSSR0
- RSTV0910_P2_HYSTTHRESH
- RSTV0910_P2_I2CRPT
- RSTV0910_P2_IDCCOMP
- RSTV0910_P2_IQCONST
- RSTV0910_P2_ISIBITENA
- RSTV0910_P2_ISIENTRY
- RSTV0910_P2_ISYMB
- RSTV0910_P2_KDIV12
- RSTV0910_P2_KDIV23
- RSTV0910_P2_KDIV34
- RSTV0910_P2_KDIV56
- RSTV0910_P2_KDIV67
- RSTV0910_P2_KDIV78
- RSTV0910_P2_KREFTMG
- RSTV0910_P2_KREFTMG2
- RSTV0910_P2_KTTMG
- RSTV0910_P2_LDI
- RSTV0910_P2_LDT
- RSTV0910_P2_LDT2
- RSTV0910_P2_LOCKTIME0
- RSTV0910_P2_LOCKTIME1
- RSTV0910_P2_LOCKTIME2
- RSTV0910_P2_LOCKTIME3
- RSTV0910_P2_MATSTR0
- RSTV0910_P2_MATSTR1
- RSTV0910_P2_MAXEXTRAITER
- RSTV0910_P2_MODCODLST0
- RSTV0910_P2_MODCODLST1
- RSTV0910_P2_MODCODLST2
- RSTV0910_P2_MODCODLST3
- RSTV0910_P2_MODCODLST4
- RSTV0910_P2_MODCODLST5
- RSTV0910_P2_MODCODLST6
- RSTV0910_P2_MODCODLST7
- RSTV0910_P2_MODCODLST8
- RSTV0910_P2_MODCODLST9
- RSTV0910_P2_MODCODLSTA
- RSTV0910_P2_MODCODLSTB
- RSTV0910_P2_MODCODLSTC
- RSTV0910_P2_MODCODLSTD
- RSTV0910_P2_MODCODLSTE
- RSTV0910_P2_MODCODLSTF
- RSTV0910_P2_NBITER_NF1
- RSTV0910_P2_NBITER_NF10
- RSTV0910_P2_NBITER_NF11
- RSTV0910_P2_NBITER_NF12
- RSTV0910_P2_NBITER_NF13
- RSTV0910_P2_NBITER_NF14
- RSTV0910_P2_NBITER_NF15
- RSTV0910_P2_NBITER_NF16
- RSTV0910_P2_NBITER_NF17
- RSTV0910_P2_NBITER_NF18
- RSTV0910_P2_NBITER_NF19
- RSTV0910_P2_NBITER_NF2
- RSTV0910_P2_NBITER_NF20
- RSTV0910_P2_NBITER_NF21
- RSTV0910_P2_NBITER_NF22
- RSTV0910_P2_NBITER_NF23
- RSTV0910_P2_NBITER_NF24
- RSTV0910_P2_NBITER_NF25
- RSTV0910_P2_NBITER_NF26
- RSTV0910_P2_NBITER_NF27
- RSTV0910_P2_NBITER_NF28
- RSTV0910_P2_NBITER_NF3
- RSTV0910_P2_NBITER_NF4
- RSTV0910_P2_NBITER_NF5
- RSTV0910_P2_NBITER_NF6
- RSTV0910_P2_NBITER_NF7
- RSTV0910_P2_NBITER_NF8
- RSTV0910_P2_NBITER_NF9
- RSTV0910_P2_NBITER_SF1
- RSTV0910_P2_NBITER_SF10
- RSTV0910_P2_NBITER_SF12
- RSTV0910_P2_NBITER_SF13
- RSTV0910_P2_NBITER_SF14
- RSTV0910_P2_NBITER_SF15
- RSTV0910_P2_NBITER_SF16
- RSTV0910_P2_NBITER_SF18
- RSTV0910_P2_NBITER_SF19
- RSTV0910_P2_NBITER_SF2
- RSTV0910_P2_NBITER_SF20
- RSTV0910_P2_NBITER_SF21
- RSTV0910_P2_NBITER_SF22
- RSTV0910_P2_NBITER_SF24
- RSTV0910_P2_NBITER_SF25
- RSTV0910_P2_NBITER_SF26
- RSTV0910_P2_NBITER_SF27
- RSTV0910_P2_NBITER_SF3
- RSTV0910_P2_NBITER_SF4
- RSTV0910_P2_NBITER_SF5
- RSTV0910_P2_NBITER_SF6
- RSTV0910_P2_NBITER_SF7
- RSTV0910_P2_NBITER_SF8
- RSTV0910_P2_NBITER_SF9
- RSTV0910_P2_NNOSDATA0
- RSTV0910_P2_NNOSDATA1
- RSTV0910_P2_NNOSDATAT0
- RSTV0910_P2_NNOSDATAT1
- RSTV0910_P2_NNOSFRAME0
- RSTV0910_P2_NNOSFRAME1
- RSTV0910_P2_NNOSPLH0
- RSTV0910_P2_NNOSPLH1
- RSTV0910_P2_NNOSPLHT0
- RSTV0910_P2_NNOSPLHT1
- RSTV0910_P2_NNOSRAD0
- RSTV0910_P2_NNOSRAD1
- RSTV0910_P2_NOSCFG
- RSTV0910_P2_NOSCFGF1
- RSTV0910_P2_NOSCFGF2
- RSTV0910_P2_NOSDATAT0
- RSTV0910_P2_NOSDATAT1
- RSTV0910_P2_NOSDIFF1
- RSTV0910_P2_NOSRAMCFG
- RSTV0910_P2_NOSRAMPOS
- RSTV0910_P2_NOSRAMVAL
- RSTV0910_P2_NOSTHRES1
- RSTV0910_P2_NOSTHRES2
- RSTV0910_P2_PDELCTRL0
- RSTV0910_P2_PDELCTRL1
- RSTV0910_P2_PDELCTRL2
- RSTV0910_P2_PDELCTRL3
- RSTV0910_P2_PDELSTATUS1
- RSTV0910_P2_PDELSTATUS2
- RSTV0910_P2_PLHMODCOD
- RSTV0910_P2_PLROOT0
- RSTV0910_P2_PLROOT1
- RSTV0910_P2_PLROOT2
- RSTV0910_P2_POWERI
- RSTV0910_P2_POWERQ
- RSTV0910_P2_PRVIT
- RSTV0910_P2_QDCCOMP
- RSTV0910_P2_QSYMB
- RSTV0910_P2_RAINFADE
- RSTV0910_P2_RTC
- RSTV0910_P2_RTCS2
- RSTV0910_P2_SFDLYSET2
- RSTV0910_P2_SFECSTATUS
- RSTV0910_P2_SFERRCNT0
- RSTV0910_P2_SFERRCNT1
- RSTV0910_P2_SFERRCNT2
- RSTV0910_P2_SFERRCTRL
- RSTV0910_P2_SFERROR
- RSTV0910_P2_SFKDIV12
- RSTV0910_P2_SFKDIV23
- RSTV0910_P2_SFKDIV34
- RSTV0910_P2_SFKDIV56
- RSTV0910_P2_SFKDIV67
- RSTV0910_P2_SFKDIV78
- RSTV0910_P2_SFR0
- RSTV0910_P2_SFR1
- RSTV0910_P2_SFR2
- RSTV0910_P2_SFR3
- RSTV0910_P2_SFRINIT0
- RSTV0910_P2_SFRINIT1
- RSTV0910_P2_SFRLOW0
- RSTV0910_P2_SFRLOW1
- RSTV0910_P2_SFRLOWRATIO
- RSTV0910_P2_SFRSTEP
- RSTV0910_P2_SFRUP0
- RSTV0910_P2_SFRUP1
- RSTV0910_P2_SFRUPRATIO
- RSTV0910_P2_SFSTATUS
- RSTV0910_P2_SMAPCOEF0
- RSTV0910_P2_SMAPCOEF1
- RSTV0910_P2_SMAPCOEF2
- RSTV0910_P2_SMAPCOEF3
- RSTV0910_P2_SMAPCOEF4
- RSTV0910_P2_SMAPCOEF5
- RSTV0910_P2_SMAPCOEF6
- RSTV0910_P2_SMAPCOEF7
- RSTV0910_P2_STATUSITER
- RSTV0910_P2_STATUSMAXITER
- RSTV0910_P2_SYNCDSTR0
- RSTV0910_P2_SYNCDSTR1
- RSTV0910_P2_SYNCSTR
- RSTV0910_P2_TCTL1
- RSTV0910_P2_TCTL4
- RSTV0910_P2_TMGCFG
- RSTV0910_P2_TMGCFG2
- RSTV0910_P2_TMGCFG3
- RSTV0910_P2_TMGLOCK0
- RSTV0910_P2_TMGLOCK1
- RSTV0910_P2_TMGOBS
- RSTV0910_P2_TMGREG0
- RSTV0910_P2_TMGREG1
- RSTV0910_P2_TMGREG2
- RSTV0910_P2_TMGTHFALL
- RSTV0910_P2_TMGTHRISE
- RSTV0910_P2_TNRCFG2
- RSTV0910_P2_TPKTDELIN
- RSTV0910_P2_TSBITRATE0
- RSTV0910_P2_TSBITRATE1
- RSTV0910_P2_TSBUFSTAT0
- RSTV0910_P2_TSBUFSTAT1
- RSTV0910_P2_TSBUFSTAT2
- RSTV0910_P2_TSCFG4
- RSTV0910_P2_TSCFGH
- RSTV0910_P2_TSCFGL
- RSTV0910_P2_TSCFGM
- RSTV0910_P2_TSDEBUGL
- RSTV0910_P2_TSDIVN
- RSTV0910_P2_TSDLY0
- RSTV0910_P2_TSDLY1
- RSTV0910_P2_TSDLY2
- RSTV0910_P2_TSDLYSET0
- RSTV0910_P2_TSDLYSET1
- RSTV0910_P2_TSDLYSET2
- RSTV0910_P2_TSINSDELH
- RSTV0910_P2_TSINSDELL
- RSTV0910_P2_TSINSDELM
- RSTV0910_P2_TSNPDAV
- RSTV0910_P2_TSPACKLEN1
- RSTV0910_P2_TSPIDFLT0
- RSTV0910_P2_TSPIDFLT1
- RSTV0910_P2_TSSPEED
- RSTV0910_P2_TSSTATEL
- RSTV0910_P2_TSSTATEM
- RSTV0910_P2_TSSTATUS
- RSTV0910_P2_TSSTATUS2
- RSTV0910_P2_TSSYNC
- RSTV0910_P2_TSTDMD
- RSTV0910_P2_UPCRCKO0
- RSTV0910_P2_UPCRCKO1
- RSTV0910_P2_UPLCCST0
- RSTV0910_P2_UPLSTR0
- RSTV0910_P2_UPLSTR1
- RSTV0910_P2_VAVSRVIT
- RSTV0910_P2_VERROR
- RSTV0910_P2_VITCURPUN
- RSTV0910_P2_VITSCALE
- RSTV0910_P2_VSTATUSVIT
- RSTV0910_P2_VTH12
- RSTV0910_P2_VTH23
- RSTV0910_P2_VTH34
- RSTV0910_P2_VTH56
- RSTV0910_P2_VTH67
- RSTV0910_P2_VTH78
- RSTV0910_P2_VTHINUSE
- RSTV0910_PADCFG
- RSTV0910_PLLSTAT
- RSTV0910_PREGCTL
- RSTV0910_RCCFG0
- RSTV0910_RCCFG1
- RSTV0910_RCCFG2
- RSTV0910_RCINSDEL0
- RSTV0910_RCINSDEL1
- RSTV0910_RCINSDEL2
- RSTV0910_RCSPEED
- RSTV0910_RCSTATUS
- RSTV0910_SELSATUR0
- RSTV0910_SELSATUR1
- RSTV0910_SELSATUR2
- RSTV0910_SELSATUR3
- RSTV0910_SELSATUR4
- RSTV0910_SELSATUR5
- RSTV0910_SELSATUR6
- RSTV0910_STOPCLK1
- RSTV0910_STOPCLK2
- RSTV0910_STRSTATUS1
- RSTV0910_STRSTATUS2
- RSTV0910_STRSTATUS3
- RSTV0910_SYNTCTRL
- RSTV0910_TSGENERAL
- RSTV0910_TSTIN
- RSTV0910_TSTOUT
- RSTV0910_TSTRES0
- RSTV0910_TSTTNR0
- RSTV0910_TSTTNR1
- RSTV0910_TSTTNR2
- RSTV0910_TSTTNR3
- RSTV0910_TSTTSRS
- RSTV6110_CTRL1
- RSTV6110_CTRL2
- RSTV6110_CTRL3
- RSTV6110_STAT1
- RSTV6110_STAT2
- RSTV6110_STAT3
- RSTV6110_TUNING1
- RSTV6110_TUNING2
- RSTYPE_RG
- RST_ACE
- RST_ADC_DPZ
- RST_ADV7171
- RST_AHB1_BE0
- RST_AHB1_BE1
- RST_AHB1_CSI
- RST_AHB1_DEU0
- RST_AHB1_DEU1
- RST_AHB1_DMA
- RST_AHB1_DRC0
- RST_AHB1_DRC1
- RST_AHB1_EHCI0
- RST_AHB1_EHCI1
- RST_AHB1_EMAC
- RST_AHB1_FE0
- RST_AHB1_FE1
- RST_AHB1_GPU
- RST_AHB1_HDMI
- RST_AHB1_HSTIMER
- RST_AHB1_LCD0
- RST_AHB1_LCD1
- RST_AHB1_LVDS
- RST_AHB1_MIPI_DSI
- RST_AHB1_MMC0
- RST_AHB1_MMC1
- RST_AHB1_MMC2
- RST_AHB1_MMC3
- RST_AHB1_MP
- RST_AHB1_NAND0
- RST_AHB1_NAND1
- RST_AHB1_OHCI0
- RST_AHB1_OHCI1
- RST_AHB1_OHCI2
- RST_AHB1_OTG
- RST_AHB1_SDRAM
- RST_AHB1_SPI0
- RST_AHB1_SPI1
- RST_AHB1_SPI2
- RST_AHB1_SPI3
- RST_AHB1_SS
- RST_AHB1_TS
- RST_AHB1_VE
- RST_APB0_I2C
- RST_APB0_IR
- RST_APB0_RSB
- RST_APB0_TIMER
- RST_APB0_UART
- RST_APB1_CODEC
- RST_APB1_DAUDIO0
- RST_APB1_DAUDIO1
- RST_APB1_DIGITAL_MIC
- RST_APB1_SPDIF
- RST_APB2_I2C0
- RST_APB2_I2C1
- RST_APB2_I2C2
- RST_APB2_I2C3
- RST_APB2_UART0
- RST_APB2_UART1
- RST_APB2_UART2
- RST_APB2_UART3
- RST_APB2_UART4
- RST_APB2_UART5
- RST_APPLI_SW
- RST_BA_MAC_MATCH
- RST_BA_MAC_TID_MATCH
- RST_BA_NO_MATCH
- RST_BE0
- RST_BE1
- RST_BE2
- RST_BOOT
- RST_BUS_AC97
- RST_BUS_AUDIO_HUB
- RST_BUS_CAN
- RST_BUS_CE
- RST_BUS_CIR_TX
- RST_BUS_CODEC
- RST_BUS_CSI
- RST_BUS_CSI0
- RST_BUS_CSI1
- RST_BUS_DBG
- RST_BUS_DE
- RST_BUS_DEINTERLACE
- RST_BUS_DE_BE
- RST_BUS_DE_FE
- RST_BUS_DMA
- RST_BUS_DMIC
- RST_BUS_DRAM
- RST_BUS_DRC
- RST_BUS_EDP
- RST_BUS_EHCI
- RST_BUS_EHCI0
- RST_BUS_EHCI1
- RST_BUS_EHCI2
- RST_BUS_EHCI3
- RST_BUS_EMAC
- RST_BUS_EMCE
- RST_BUS_EPHY
- RST_BUS_FD
- RST_BUS_GMAC
- RST_BUS_GPADC
- RST_BUS_GPU
- RST_BUS_GPU_CTRL
- RST_BUS_HDCP
- RST_BUS_HDMI
- RST_BUS_HDMI0
- RST_BUS_HDMI1
- RST_BUS_HDMI_SUB
- RST_BUS_HSTIMER
- RST_BUS_I2C0
- RST_BUS_I2C1
- RST_BUS_I2C2
- RST_BUS_I2C3
- RST_BUS_I2C4
- RST_BUS_I2S0
- RST_BUS_I2S1
- RST_BUS_I2S2
- RST_BUS_I2S3
- RST_BUS_IOMMU
- RST_BUS_IR
- RST_BUS_IR0
- RST_BUS_IR1
- RST_BUS_IR_TX
- RST_BUS_KEYPAD
- RST_BUS_LCD
- RST_BUS_LCD0
- RST_BUS_LCD1
- RST_BUS_LRADC
- RST_BUS_LVDS
- RST_BUS_MIPI_DSI
- RST_BUS_MIPI_HSI
- RST_BUS_MMC
- RST_BUS_MMC0
- RST_BUS_MMC1
- RST_BUS_MMC2
- RST_BUS_MMC3
- RST_BUS_MP
- RST_BUS_MSGBOX
- RST_BUS_NAND
- RST_BUS_NAND0
- RST_BUS_NAND1
- RST_BUS_OHCI
- RST_BUS_OHCI0
- RST_BUS_OHCI1
- RST_BUS_OHCI2
- RST_BUS_OHCI3
- RST_BUS_OTG
- RST_BUS_OTG_PHY
- RST_BUS_PCIE
- RST_BUS_PS20
- RST_BUS_PS21
- RST_BUS_PSI
- RST_BUS_PWM
- RST_BUS_RSB
- RST_BUS_SAT
- RST_BUS_SATA
- RST_BUS_SCR
- RST_BUS_SCR0
- RST_BUS_SCR1
- RST_BUS_SDRAM
- RST_BUS_SPDIF
- RST_BUS_SPI0
- RST_BUS_SPI1
- RST_BUS_SPI2
- RST_BUS_SPI3
- RST_BUS_SPINLOCK
- RST_BUS_SS
- RST_BUS_TCON0
- RST_BUS_TCON1
- RST_BUS_TCON_LCD0
- RST_BUS_TCON_LCD1
- RST_BUS_TCON_TOP
- RST_BUS_TCON_TV0
- RST_BUS_TCON_TV1
- RST_BUS_TDM
- RST_BUS_THS
- RST_BUS_TS
- RST_BUS_TVD
- RST_BUS_TVD0
- RST_BUS_TVD1
- RST_BUS_TVD2
- RST_BUS_TVD3
- RST_BUS_TVD_TOP
- RST_BUS_TVE
- RST_BUS_TVE0
- RST_BUS_TVE1
- RST_BUS_TVE_TOP
- RST_BUS_UART0
- RST_BUS_UART1
- RST_BUS_UART2
- RST_BUS_UART3
- RST_BUS_UART4
- RST_BUS_UART5
- RST_BUS_UART6
- RST_BUS_UART7
- RST_BUS_VE
- RST_BUS_VP9
- RST_BUS_XHCI
- RST_CFG
- RST_CHIMINTEN
- RST_CLR_REG
- RST_CLR_REGOFFSET
- RST_CMP
- RST_COMP_SW
- RST_CONF_SW
- RST_COUNT
- RST_CPU
- RST_CPU_EN
- RST_CSI
- RST_CSI0
- RST_CSI1
- RST_CSR_AE_LSB
- RST_CSR_QAT_LSB
- RST_CTL
- RST_CTL_ACK_TO_EN
- RST_CTL_ACK_TO_VAL
- RST_CTL_DIG_SW_RST_N_MASK
- RST_CTL_DIG_SW_RST_N_REMOVE_RESET
- RST_CTL_DIG_SW_RST_N_RESET
- RST_CTL_MAC_RST0
- RST_CTL_MAC_RST1
- RST_CTL_MAC_RST2
- RST_CTL_MAC_RST3
- RST_CTRL_REG
- RST_DAC_DPZ
- RST_DAP
- RST_DC
- RST_DC_EN
- RST_DDR
- RST_DDR_EN
- RST_DELAY
- RST_DEU0
- RST_DEU1
- RST_DEVICES_CLR_H
- RST_DEVICES_CLR_L
- RST_DEVICES_CLR_U
- RST_DEVICES_CLR_V
- RST_DEVICES_CLR_W
- RST_DEVICES_CLR_X
- RST_DEVICES_CLR_Y
- RST_DEVICES_H
- RST_DEVICES_L
- RST_DEVICES_SET_H
- RST_DEVICES_SET_L
- RST_DEVICES_SET_U
- RST_DEVICES_SET_V
- RST_DEVICES_SET_W
- RST_DEVICES_SET_X
- RST_DEVICES_SET_Y
- RST_DEVICES_U
- RST_DEVICES_V
- RST_DEVICES_W
- RST_DEVICES_X
- RST_DEVICES_Y
- RST_DE_BE
- RST_DE_BE0
- RST_DE_BE1
- RST_DE_FE
- RST_DE_FE0
- RST_DE_FE1
- RST_DE_MP
- RST_DFLL_DVCO
- RST_DRAM
- RST_DRC0
- RST_DRC1
- RST_DTRANRST0
- RST_DTRANRST1
- RST_EN_COMINT
- RST_EN_DEVINT
- RST_EN_DEVTIMER1
- RST_EN_DEVTIMER2
- RST_EN_DLAVAIL
- RST_EN_EXT_INT0
- RST_EN_EXT_INT1
- RST_EN_HOSTERR
- RST_EN_INITERR
- RST_EVB_REG
- RST_FE0
- RST_FE1
- RST_FE2
- RST_FM
- RST_FO
- RST_FO_FR
- RST_FO_FRB
- RST_FO_MOP
- RST_FO_REG
- RST_FO_RR_CQ_CAM
- RST_FO_RR_DQ
- RST_FO_RR_DROP
- RST_FO_RR_MASK
- RST_FO_RR_RCV_FUNC_CQ
- RST_FO_TFO
- RST_GL_PSE
- RST_GMAC_0_MASK
- RST_GMAC_0_SHIFT
- RST_GPIO_PIN
- RST_GPS
- RST_GPU
- RST_HDMI_AUDIO_DMA
- RST_HDMI_H
- RST_HDMI_SYS
- RST_HOLD0
- RST_HOLD1
- RST_HWARE
- RST_IEP
- RST_INT
- RST_LCD
- RST_LVDS
- RST_MACRO_SW
- RST_MASK
- RST_MBUS
- RST_MERGE
- RST_MIB_CNT
- RST_MIXER0
- RST_MIXER1
- RST_OFFSET
- RST_OFS
- RST_PCIE_POWERUP
- RST_PER_FRAME
- RST_PIX_CNT
- RST_PLL_SW
- RST_POLL_INVL
- RST_POLL_TIMEOUT
- RST_PROT_REG
- RST_REG
- RST_RESERVED_BITS
- RST_ROT
- RST_R_APB1_IR
- RST_R_APB1_PWM
- RST_R_APB1_TIMER
- RST_R_APB1_TWD
- RST_R_APB1_W1
- RST_R_APB2_I2C
- RST_R_APB2_UART
- RST_SCSI_BUS
- RST_SET_REG
- RST_SET_REGOFFSET
- RST_SPCS_MASK
- RST_SPCS_SHIFT
- RST_STAT0
- RST_STAT1
- RST_STS_REG
- RST_TCON0
- RST_TCON1
- RST_TIME
- RST_TIMEOUT
- RST_TVE
- RST_TVE0
- RST_TVE1
- RST_UCB1X00
- RST_UDA1341
- RST_USB0_HCI
- RST_USB0_PHY
- RST_USB1_HCI
- RST_USB1_HSIC
- RST_USB1_PHY
- RST_USB2_HCI
- RST_USB2_HSIC
- RST_USB2_PHY
- RST_USB_HSIC
- RST_USB_PHY0
- RST_USB_PHY1
- RST_USB_PHY2
- RST_USB_PHY3
- RST_VE
- RST_VTX_CNT
- RST_WB
- RST_WIFI_GPIO
- RSText
- RSText8
- RSU
- RSUM_EN
- RSUM_IN
- RSUM_INT
- RSUM_OUT
- RSU_ERROR_DETAIL_MASK
- RSU_ERROR_LOCATION_MASK
- RSU_FW_VERSION_MASK
- RSU_STATE_MASK
- RSU_TIMEOUT
- RSU_VERSION_MASK
- RSV0
- RSVD
- RSVD2
- RSVD3
- RSVD4
- RSVD5
- RSVD6_MSK
- RSVD6_SHT
- RSVD7
- RSVDPAGE_LOC
- RSVDSPACEINT_F
- RSVDSPACEINT_S
- RSVDSPACEINT_V
- RSVD_BEACON
- RSVD_FW_QUEUE_PAGE_BCN_SHIFT
- RSVD_FW_QUEUE_PAGE_BE_SHIFT
- RSVD_FW_QUEUE_PAGE_BK_SHIFT
- RSVD_FW_QUEUE_PAGE_CMD_SHIFT
- RSVD_FW_QUEUE_PAGE_MGNT_SHIFT
- RSVD_FW_QUEUE_PAGE_PUB_SHIFT
- RSVD_FW_QUEUE_PAGE_VI_SHIFT
- RSVD_FW_QUEUE_PAGE_VO_SHIFT
- RSVD_MAC_TUNE_US
- RSVD_MASK
- RSVD_MCAM_ENTRIES_PER_NIXLF
- RSVD_MCAM_ENTRIES_PER_PF
- RSVD_NULL
- RSVD_PAGE_START_ADDR
- RSVD_PG_CPU_INSTRUCTION_NUM
- RSVD_PG_DRV_NUM
- RSVD_PG_FW_TXBUF_NUM
- RSVD_PG_H2CQ_NUM
- RSVD_PG_H2C_EXTRAINFO_NUM
- RSVD_PG_H2C_STATICINFO_NUM
- RSVD_PROBE_RESP
- RSVD_PS_POLL
- RSVD_QOS_NULL
- RSVD_ROOM_SZ
- RSVD_SERVICE_GROUP
- RSVD_WOL_PATTERN_NUM
- RSVP_APPLY_RESULT
- RSVP_DST_LEN
- RSVP_ID
- RSVP_OPS
- RSV_BITMASK
- RSV_CARRIEREV
- RSV_CRCERROR
- RSV_CTRL
- RSV_DRIBBLENIBBLE
- RSV_GETBIT
- RSV_HASHFILTERMATCH
- RSV_INTR_OFFSET
- RSV_LENCHECKERR
- RSV_LENOUTOFRANGE
- RSV_MAGICPKTFILTERMATCH
- RSV_NOTMEFILTERMATCH
- RSV_PTRNMTCHFILTERMATCH
- RSV_RUNTFILTERMATCH
- RSV_RXBROADCAST
- RSV_RXCONTROLFRAME
- RSV_RXLONGEVDROPEV
- RSV_RXMULTICAST
- RSV_RXOK
- RSV_RXPAUSEFRAME
- RSV_RXTYPEVLAN
- RSV_RXUNKNOWNOPCODE
- RSV_SIZE
- RSV_TAG_RAM
- RSV_UNICASTFILTERMATCH
- RSW
- RSWAP
- RSXX_CFG_VERSION
- RSXX_CS_IDX_MASK
- RSXX_DISCARD_SUPPORT
- RSXX_EEH_SUPPORT
- RSXX_FLUSH_BUSY
- RSXX_FLUSH_TIMEOUT
- RSXX_GETREG
- RSXX_HW_BLK_MASK
- RSXX_HW_BLK_SHIFT
- RSXX_HW_BLK_SIZE
- RSXX_INTR_COAL_AUTO_TUNE
- RSXX_INTR_COAL_DISABLED
- RSXX_INTR_COAL_EXPLICIT
- RSXX_IOC_MAGIC
- RSXX_MAX_DATA
- RSXX_MAX_OUTSTANDING_CMDS
- RSXX_MAX_REG_CNT
- RSXX_MAX_TARGETS
- RSXX_SETREG
- RSXX_VENDOR_COUNT
- RSXX_VENDOR_ID_DSI
- RSXX_VENDOR_ID_IBM
- RSX_STATUS_MASK
- RSX_STATUS_ON
- RSX_STATUS_RC1
- RSX_STATUS_RC1E
- RSX_STATUS_RS1
- RSX_STATUS_RS2
- RSX_STATUS_RS3
- RSX_STATUS_RSVD
- RSX_STATUS_RSVD2
- RSYNCERREN
- RSYNC_CHANGE
- RSYNC_ERR
- RSZ_420_CEN
- RSZ_420_YEN
- RSZ_BILINEAR
- RSZ_COLOR8
- RSZ_DATA_STEP
- RSZ_DATA_STEP_MASK
- RSZ_DATA_STEP_SHIFT
- RSZ_DEST_CFG
- RSZ_DMA_RZA
- RSZ_DMA_RZB
- RSZ_DMA_STA
- RSZ_DWN_EN_DWN_EN
- RSZ_ENABLE_CFG
- RSZ_EN_EN
- RSZ_FRACDIV
- RSZ_FRACDIV_MASK
- RSZ_GCK_MMR
- RSZ_GCK_MMR_MMR
- RSZ_GCK_SDR
- RSZ_GCK_SDR_CORE
- RSZ_HOR
- RSZ_HOR_MASK
- RSZ_HOR_SHIFT
- RSZ_H_DIF_MASK
- RSZ_H_LPF_C_MASK
- RSZ_H_LPF_C_SHIFT
- RSZ_H_LPF_Y_MASK
- RSZ_H_LPF_Y_SHIFT
- RSZ_H_PHS_MASK
- RSZ_H_TYP_C
- RSZ_H_TYP_Y
- RSZ_IN_FIFO_CTRL
- RSZ_IN_FIFO_CTRL_THRLD_HIGH_MASK
- RSZ_IN_FIFO_CTRL_THRLD_HIGH_SHIFT
- RSZ_IN_FIFO_CTRL_THRLD_LOW_MASK
- RSZ_IN_FIFO_CTRL_THRLD_LOW_SHIFT
- RSZ_IRQ_RZA
- RSZ_IRQ_RZA_MASK
- RSZ_IRQ_RZB
- RSZ_IRQ_RZB_MASK
- RSZ_I_HPS_MASK
- RSZ_I_VPS_MASK
- RSZ_O_HSZ_MASK
- RSZ_O_VSZ_MASK
- RSZ_PARA_STEP
- RSZ_PARA_STEP_MASK
- RSZ_PARA_STEP_SHIFT
- RSZ_PRINT_REGISTER
- RSZ_REVISION
- RSZ_SEQ
- RSZ_SEQ_HRVA
- RSZ_SEQ_HRVB
- RSZ_SRC_CFG
- RSZ_SRC_EN
- RSZ_SRC_EN_SRC_EN
- RSZ_SRC_FMT0
- RSZ_SRC_FMT0_BYPASS
- RSZ_SRC_FMT0_SEL
- RSZ_SRC_FMT1
- RSZ_SRC_FMT1_IN420
- RSZ_SRC_HPS
- RSZ_SRC_HSZ
- RSZ_SRC_MODE
- RSZ_SRC_MODE_OST
- RSZ_SRC_MODE_WRT
- RSZ_SRC_VPS
- RSZ_SRC_VSZ
- RSZ_SYSCONFIG
- RSZ_SYSCONFIG_RSZA_CLK_EN
- RSZ_SYSCONFIG_RSZB_CLK_EN
- RSZ_THE_SAME
- RSZ_VER
- RSZ_VER_MASK
- RSZ_VER_SHIFT
- RSZ_VL1_U0
- RSZ_VL_CHROMA_HOR
- RSZ_VL_CHROMA_VER
- RSZ_VL_CTRL_CFG
- RSZ_VL_ENABLE_CFG
- RSZ_VL_FMT_MASK
- RSZ_VL_FMT_SHIFT
- RSZ_VL_FMT_YCBCR420
- RSZ_VL_FMT_YCBCR422
- RSZ_VL_FMT_YCBCR444
- RSZ_VL_LUMA_HOR
- RSZ_VL_LUMA_VER
- RSZ_VL_OFFSET
- RSZ_V_DIF_MASK
- RSZ_V_LPF_C_MASK
- RSZ_V_LPF_C_SHIFT
- RSZ_V_LPF_Y_MASK
- RSZ_V_LPF_Y_SHIFT
- RSZ_V_PHS_C_MASK
- RSZ_V_PHS_Y_MASK
- RSZ_V_TYP_C
- RSZ_V_TYP_Y
- RSZ_YUV422
- RSZ_YUV_C_MAX
- RSZ_YUV_C_MIN
- RSZ_YUV_Y_MAX
- RSZ_YUV_Y_MIN
- RS_32
- RS_32_1
- RS_64
- RS_64_1
- RS_ABORTED
- RS_ACTION_DOWNSCALE
- RS_ACTION_STAY
- RS_ACTION_UPSCALE
- RS_ALGNERR
- RS_AUTO
- RS_BADCRC
- RS_BAD_PARAM
- RS_BEACON
- RS_BERCNT_H
- RS_BERCNT_L
- RS_BERCNT_M
- RS_BRODCAST
- RS_BUSY
- RS_CEOR
- RS_CFG_BASE
- RS_CFG_ERR_BUSY
- RS_CFG_ERR_DATE
- RS_CFG_ERR_SGE
- RS_CFG_ERR_TIME
- RS_CFG_SAVE
- RS_CLEAR
- RS_CLEAR_EVENT
- RS_CLI_INTERNAL
- RS_CLRD
- RS_CLSN
- RS_COLUMN_COUNT
- RS_COLUMN_INVALID
- RS_COLUMN_LAST
- RS_COLUMN_LEGACY_ANT_A
- RS_COLUMN_LEGACY_ANT_B
- RS_COLUMN_MIMO2
- RS_COLUMN_MIMO2_SGI
- RS_COLUMN_SISO_ANT_A
- RS_COLUMN_SISO_ANT_A_SGI
- RS_COLUMN_SISO_ANT_B
- RS_COLUMN_SISO_ANT_B_SGI
- RS_COR_INSTAT
- RS_COR_INTEN
- RS_COR_STAT
- RS_COR_SYNC_PARAM
- RS_COUNT
- RS_CSTATE_C367_RS1
- RS_CSTATE_C367_RS2
- RS_CSTATE_C36_RS1_C7_RS2
- RS_CSTATE_MASK
- RS_CSTATE_RSVD
- RS_DECODE_B
- RS_DECODE_LAMBDA
- RS_DECODE_LOC
- RS_DECODE_NUM_BUFFERS
- RS_DECODE_OMEGA
- RS_DECODE_REG
- RS_DECODE_ROOT
- RS_DECODE_SYN
- RS_DECODE_T
- RS_DEGRADED
- RS_DEV_ASSIGNED
- RS_DEV_INVALID
- RS_DEV_LOST
- RS_DEV_REMOVE
- RS_DISCONNECT
- RS_DONE
- RS_DQ_RD_RET_CONF
- RS_DRV_DATA_LQ_COLOR_GET
- RS_DRV_DATA_LQ_COLOR_MSK
- RS_DRV_DATA_LQ_COLOR_POS
- RS_DRV_DATA_PACK
- RS_DRV_DATA_TXP_MSK
- RS_DUAL
- RS_DUPADDR
- RS_ELEM_INVALID
- RS_ERRORS
- RS_ERR_CNT_0
- RS_ERR_CNT_1
- RS_ERR_CNT_2
- RS_ERR_DMA_DATA
- RS_ERR_DMA_SG
- RS_ERR_PER_0
- RS_ERR_PER_1
- RS_ERS
- RS_EVENT
- RS_EVENT_WRITE_WAKEUP
- RS_FCSERR
- RS_FLS_BASE
- RS_FLS_ERR_AREA
- RS_FLS_ERR_BEGIN
- RS_FLS_ERR_BUSY
- RS_FLS_ERR_CHECK
- RS_FLS_ERR_FAIL
- RS_FLS_ERR_FSIZE
- RS_FLS_ERR_NOFILE
- RS_FLS_ERR_RANGE
- RS_FLS_ERR_RSRC
- RS_FLUSH
- RS_FRAMERR
- RS_FRD
- RS_GRP_BLOCK_SIZE
- RS_GRP_COMMIT
- RS_GRP_EXISTS
- RS_GRP_INTLV
- RS_GRP_INVALID
- RS_GRP_LIMIT
- RS_GRP_MEMBERS
- RS_GRP_MEMBER_SIZE
- RS_GRP_REBUILD
- RS_GRP_REBUILD_TYPE
- RS_GRP_SPAN
- RS_GRP_TYPE
- RS_HARDERROR
- RS_HS_ERROR
- RS_IN
- RS_INIT_FAILURE_ALRT
- RS_INIT_FAILURE_BSDES
- RS_INIT_FAILURE_PERF
- RS_INIT_FAILURE_QSI
- RS_INVALID
- RS_INV_FUNC
- RS_ISR_PASS_LIMIT
- RS_LEGACY
- RS_LOCK_DET_MASK
- RS_MASK
- RS_METRICS_ERROR
- RS_MGT_BASE
- RS_MIMO2
- RS_MULTICAST
- RS_NAME
- RS_NORINGOP
- RS_NO_LUN
- RS_NO_METRICS_TEST
- RS_ODDFRAME
- RS_OFLO
- RS_OFS
- RS_OUT
- RS_OVERRUN
- RS_PART_CAP
- RS_PART_DUP
- RS_PART_LAST
- RS_PART_LUN
- RS_PART_MAPPED
- RS_PART_MAX
- RS_PART_NOMAP
- RS_PART_STATE
- RS_PART_TARGET
- RS_PATHTEST
- RS_PENDING
- RS_PERCENT
- RS_PERIODIC_TIMEOUT_USEC
- RS_PROGRESS
- RS_QRFS
- RS_RES0
- RS_RES15
- RS_RES7
- RS_RES9
- RS_RESET
- RS_RESID_MISM
- RS_RINGOPCHANGE
- RS_SCAN_FAIL
- RS_SCAN_GEN
- RS_SCSI_ERROR
- RS_SEL
- RS_SEL2
- RS_SELFTEST
- RS_SET
- RS_SH
- RS_SISO
- RS_SOFTERROR
- RS_SS_FORCE_BFER
- RS_SS_FORCE_NONE
- RS_SS_FORCE_SISO
- RS_SS_FORCE_STBC
- RS_START
- RS_STARTED
- RS_STATE_SEARCH_CYCLE_ENDED
- RS_STATE_SEARCH_CYCLE_STARTED
- RS_STATE_STAY_IN_COLUMN
- RS_STOP
- RS_STUCKBYPASSS
- RS_SUCCESS
- RS_SUSP
- RS_TEST_IN_PROG
- RS_TIMEOUT
- RS_TM_FAILED
- RS_TOOLONG
- RS_TOOSHORT
- RS_UBC_0
- RS_UBC_1
- RS_UBC_H
- RS_UBC_L
- RS_UNDERRUN
- RS_UNSUPPORTED
- RS_VDA_BASE
- RS_VDA_INTERNAL
- RS_VERSION
- RS_WFRP
- RT
- RT0
- RT0d
- RT1
- RT1011_ADCDAT1_INPUT
- RT1011_ADCDAT1_OUTPUT
- RT1011_ADCDAT1_PIN_CONFIG
- RT1011_ADCDAT2_INPUT
- RT1011_ADCDAT2_OUTPUT
- RT1011_ADCDAT2_PIN_CONFIG
- RT1011_ADCDAT_OUT_SOURCE
- RT1011_ADC_SET
- RT1011_ADC_SET_1
- RT1011_ADC_SET_2
- RT1011_ADC_SET_3
- RT1011_ADC_SET_4
- RT1011_ADC_SET_5
- RT1011_ADRC_LIMIT
- RT1011_ADVMODE_BQ_UI_COEFF
- RT1011_ADVMODE_EQ_BQ_COEFF
- RT1011_ADVMODE_INITIAL_SET
- RT1011_ADVMODE_NUM
- RT1011_ADVMODE_SEP_BQ_COEFF
- RT1011_ADVMODE_SMARTBOOST_COEFF
- RT1011_AD_EN_CKGEN_ADC
- RT1011_AD_EN_CKGEN_ADC_MASK
- RT1011_AD_EN_CKGEN_ADC_SFT
- RT1011_AIF1
- RT1011_AIFS
- RT1011_ALC_BK_GAIN_O
- RT1011_ALC_BK_GAIN_O_PRE
- RT1011_ALC_DRC_BB_INTERNAL_1
- RT1011_ALC_DRC_BB_INTERNAL_5
- RT1011_ALC_DRC_BB_INTERNAL_6
- RT1011_ALC_DRC_BB_INTERNAL_7
- RT1011_ALC_DRC_HB_INTERNAL_1
- RT1011_ALC_DRC_HB_INTERNAL_5
- RT1011_ALC_DRC_HB_INTERNAL_6
- RT1011_ALC_DRC_HB_INTERNAL_7
- RT1011_ALC_DRC_POS_INTERNAL_1
- RT1011_ALC_DRC_POS_INTERNAL_10
- RT1011_ALC_DRC_POS_INTERNAL_11
- RT1011_ALC_DRC_POS_INTERNAL_5
- RT1011_ALC_DRC_POS_INTERNAL_6
- RT1011_ALC_DRC_POS_INTERNAL_7
- RT1011_ALC_DRC_POS_INTERNAL_8
- RT1011_ALC_DRC_POS_INTERNAL_9
- RT1011_ANALOG_CTRL
- RT1011_A_PRO
- RT1011_A_TEMP_SEN
- RT1011_A_TIMING_1
- RT1011_A_TIMING_2
- RT1011_BAT_GAIN_1
- RT1011_BAT_GAIN_10
- RT1011_BAT_GAIN_11
- RT1011_BAT_GAIN_2
- RT1011_BAT_GAIN_3
- RT1011_BAT_GAIN_4
- RT1011_BAT_GAIN_5
- RT1011_BAT_GAIN_6
- RT1011_BAT_GAIN_7
- RT1011_BAT_GAIN_8
- RT1011_BAT_GAIN_9
- RT1011_BAT_RT_THMAX_1
- RT1011_BAT_RT_THMAX_10
- RT1011_BAT_RT_THMAX_11
- RT1011_BAT_RT_THMAX_12
- RT1011_BAT_RT_THMAX_2
- RT1011_BAT_RT_THMAX_3
- RT1011_BAT_RT_THMAX_4
- RT1011_BAT_RT_THMAX_5
- RT1011_BAT_RT_THMAX_6
- RT1011_BAT_RT_THMAX_7
- RT1011_BAT_RT_THMAX_8
- RT1011_BAT_RT_THMAX_9
- RT1011_BOOST_CON_1
- RT1011_BOOST_CON_2
- RT1011_BQ_10_A2_15_0
- RT1011_BQ_10_H0_28_16
- RT1011_BQ_10_PARAMS_CHECK_1
- RT1011_BQ_10_PARAMS_CHECK_5
- RT1011_BQ_1_A2_15_0
- RT1011_BQ_1_H0_28_16
- RT1011_BQ_1_PARAMS_CHECK_5
- RT1011_BQ_2_A2_15_0
- RT1011_BQ_2_H0_28_16
- RT1011_BQ_2_PARAMS_CHECK_1
- RT1011_BQ_2_PARAMS_CHECK_5
- RT1011_BQ_3_A2_15_0
- RT1011_BQ_3_H0_28_16
- RT1011_BQ_3_PARAMS_CHECK_1
- RT1011_BQ_3_PARAMS_CHECK_5
- RT1011_BQ_4_A2_15_0
- RT1011_BQ_4_H0_28_16
- RT1011_BQ_4_PARAMS_CHECK_1
- RT1011_BQ_4_PARAMS_CHECK_5
- RT1011_BQ_5_A2_15_0
- RT1011_BQ_5_H0_28_16
- RT1011_BQ_5_PARAMS_CHECK_1
- RT1011_BQ_5_PARAMS_CHECK_5
- RT1011_BQ_6_A2_15_0
- RT1011_BQ_6_H0_28_16
- RT1011_BQ_6_PARAMS_CHECK_1
- RT1011_BQ_6_PARAMS_CHECK_5
- RT1011_BQ_7_A2_15_0
- RT1011_BQ_7_H0_28_16
- RT1011_BQ_7_PARAMS_CHECK_1
- RT1011_BQ_7_PARAMS_CHECK_5
- RT1011_BQ_8_A2_15_0
- RT1011_BQ_8_H0_28_16
- RT1011_BQ_8_PARAMS_CHECK_1
- RT1011_BQ_8_PARAMS_CHECK_5
- RT1011_BQ_9_A2_15_0
- RT1011_BQ_9_H0_28_16
- RT1011_BQ_9_PARAMS_CHECK_1
- RT1011_BQ_9_PARAMS_CHECK_5
- RT1011_BQ_A2_15_0
- RT1011_BQ_DRC
- RT1011_BQ_DRC_NUM
- RT1011_BQ_H0_28_16
- RT1011_BQ_POST_GAIN_15_0
- RT1011_BQ_POST_GAIN_28_16
- RT1011_BQ_PRE_GAIN_15_0
- RT1011_BQ_PRE_GAIN_28_16
- RT1011_BQ_SET_0
- RT1011_BQ_SET_1
- RT1011_BQ_SET_2
- RT1011_BYPASS_MIX_T
- RT1011_BYPASS_MIX_T_BIT
- RT1011_CLASSD_INTERNAL_SET_1
- RT1011_CLASSD_INTERNAL_SET_3
- RT1011_CLASSD_INTERNAL_SET_8
- RT1011_CLASS_D_POS
- RT1011_CLK_1
- RT1011_CLK_2
- RT1011_CLK_3
- RT1011_CLK_4
- RT1011_CLK_DET
- RT1011_CROSS_BQ_SET_1
- RT1011_CROSS_BQ_SET_2
- RT1011_CUSTOMER_ID
- RT1011_DAC_SET_1
- RT1011_DAC_SET_2
- RT1011_DAC_SET_3
- RT1011_DA_MUTE_EN_MASK
- RT1011_DA_MUTE_EN_SFT
- RT1011_DC_CALIB_CLASSD_1
- RT1011_DC_CALIB_CLASSD_10
- RT1011_DC_CALIB_CLASSD_2
- RT1011_DC_CALIB_CLASSD_3
- RT1011_DC_CALIB_CLASSD_5
- RT1011_DC_CALIB_CLASSD_6
- RT1011_DC_CALIB_CLASSD_7
- RT1011_DC_CALIB_CLASSD_8
- RT1011_DEVICE_ID
- RT1011_DEVICE_ID_NUM
- RT1011_DRC_CF_PARAMS_1
- RT1011_DRC_CF_PARAMS_12
- RT1011_DRIVER_READY_SPK
- RT1011_DRIVER_READY_SPK_BIT
- RT1011_DUM_RO
- RT1011_DUM_RW_0
- RT1011_DUM_RW_1
- RT1011_DUM_YUN
- RT1011_EFUSE_ADC_OFFSET_15_0
- RT1011_EFUSE_ADC_OFFSET_18_16
- RT1011_EFUSE_CONTROL_1
- RT1011_EFUSE_CONTROL_2
- RT1011_EFUSE_DAC_OFFSET_G0_15_0
- RT1011_EFUSE_DAC_OFFSET_G0_20_16
- RT1011_EFUSE_DAC_OFFSET_G1_15_0
- RT1011_EFUSE_DAC_OFFSET_G1_20_16
- RT1011_EFUSE_MATCH_DONE
- RT1011_EFUSE_READ_R0_3_15_0
- RT1011_EN_CKGEN_DAC
- RT1011_EN_CKGEN_DAC_MASK
- RT1011_EN_CKGEN_DAC_SFT
- RT1011_EN_MCLK_DET
- RT1011_EN_MCLK_DET_MASK
- RT1011_EN_MCLK_DET_SFT
- RT1011_EXCUR_PROTECT_1
- RT1011_EXCUR_PROTECT_2
- RT1011_EXCUR_PROTECT_3
- RT1011_EXCUR_PROTECT_4
- RT1011_FM_VER
- RT1011_FORMATS
- RT1011_FS_SYS_DIV_MASK
- RT1011_FS_SYS_DIV_SFT
- RT1011_FS_SYS_PRE_BCLK
- RT1011_FS_SYS_PRE_MASK
- RT1011_FS_SYS_PRE_MCLK
- RT1011_FS_SYS_PRE_PLL1
- RT1011_FS_SYS_PRE_RCCLK
- RT1011_FS_SYS_PRE_SFT
- RT1011_FS_SYS_PRE_S_BCLK
- RT1011_FS_SYS_PRE_S_MCLK
- RT1011_FS_SYS_PRE_S_PLL1
- RT1011_FS_SYS_PRE_S_RCCLK
- RT1011_I2S_CH_RX_LEN_16B
- RT1011_I2S_CH_RX_LEN_20B
- RT1011_I2S_CH_RX_LEN_24B
- RT1011_I2S_CH_RX_LEN_32B
- RT1011_I2S_CH_RX_LEN_8B
- RT1011_I2S_CH_RX_LEN_MASK
- RT1011_I2S_CH_RX_LEN_SFT
- RT1011_I2S_CH_RX_MASK
- RT1011_I2S_CH_RX_SFT
- RT1011_I2S_CH_TX_LEN_16B
- RT1011_I2S_CH_TX_LEN_20B
- RT1011_I2S_CH_TX_LEN_24B
- RT1011_I2S_CH_TX_LEN_32B
- RT1011_I2S_CH_TX_LEN_8B
- RT1011_I2S_CH_TX_LEN_MASK
- RT1011_I2S_CH_TX_LEN_SFT
- RT1011_I2S_CH_TX_MASK
- RT1011_I2S_CH_TX_SFT
- RT1011_I2S_LEFT_CH_SEL
- RT1011_I2S_LR_CH_SEL_MASK
- RT1011_I2S_LR_CH_SEL_SFT
- RT1011_I2S_RIGHT_CH_SEL
- RT1011_I2S_RX_2CH
- RT1011_I2S_RX_4CH
- RT1011_I2S_RX_6CH
- RT1011_I2S_RX_8CH
- RT1011_I2S_RX_DL_16B
- RT1011_I2S_RX_DL_20B
- RT1011_I2S_RX_DL_24B
- RT1011_I2S_RX_DL_32B
- RT1011_I2S_RX_DL_8B
- RT1011_I2S_RX_DL_MASK
- RT1011_I2S_RX_DL_SFT
- RT1011_I2S_TDM_DF_I2S
- RT1011_I2S_TDM_DF_LEFT
- RT1011_I2S_TDM_DF_MASK
- RT1011_I2S_TDM_DF_PCM_A
- RT1011_I2S_TDM_DF_PCM_A_N
- RT1011_I2S_TDM_DF_PCM_B
- RT1011_I2S_TDM_DF_PCM_B_N
- RT1011_I2S_TDM_DF_SFT
- RT1011_I2S_TDM_MS_M
- RT1011_I2S_TDM_MS_MASK
- RT1011_I2S_TDM_MS_S
- RT1011_I2S_TDM_MS_SFT
- RT1011_I2S_TX_2CH
- RT1011_I2S_TX_4CH
- RT1011_I2S_TX_6CH
- RT1011_I2S_TX_8CH
- RT1011_I2S_TX_DL_16B
- RT1011_I2S_TX_DL_20B
- RT1011_I2S_TX_DL_24B
- RT1011_I2S_TX_DL_32B
- RT1011_I2S_TX_DL_8B
- RT1011_I2S_TX_DL_MASK
- RT1011_I2S_TX_DL_SFT
- RT1011_INIT_RECIPROCAL_REG_15_0
- RT1011_INIT_RECIPROCAL_REG_24_16
- RT1011_INIT_RECIPROCAL_SYN_15_0
- RT1011_INIT_RECIPROCAL_SYN_24_16
- RT1011_INIT_REG_LEN
- RT1011_IRQ_1
- RT1011_MAN_I2C_DEV
- RT1011_MAX_REG
- RT1011_MIXER_1
- RT1011_MIXER_2
- RT1011_MIXER_MUTE_MIX_I
- RT1011_MIXER_MUTE_MIX_I_MASK
- RT1011_MIXER_MUTE_MIX_I_SFT
- RT1011_MIXER_MUTE_MIX_V
- RT1011_MIXER_MUTE_MIX_V_MASK
- RT1011_MIXER_MUTE_MIX_V_SFT
- RT1011_MIXER_MUTE_SUM_I
- RT1011_MIXER_MUTE_SUM_I_MASK
- RT1011_MIXER_MUTE_SUM_I_SFT
- RT1011_MIXER_MUTE_SUM_V
- RT1011_MIXER_MUTE_SUM_V_MASK
- RT1011_MIXER_MUTE_SUM_V_SFT
- RT1011_PART_NUMBER_EFUSE
- RT1011_PLL1_BPM
- RT1011_PLL1_BPM_MASK
- RT1011_PLL1_BPM_SFT
- RT1011_PLL1_QM_MASK
- RT1011_PLL1_QM_SFT
- RT1011_PLL1_QN_MASK
- RT1011_PLL1_QN_SFT
- RT1011_PLL1_SRC_BCLK
- RT1011_PLL1_SRC_MASK
- RT1011_PLL1_SRC_PLL2
- RT1011_PLL1_SRC_SFT
- RT1011_PLL1_S_BCLK
- RT1011_PLL2_BPK
- RT1011_PLL2_BPK_MASK
- RT1011_PLL2_BPK_SFT
- RT1011_PLL2_QK_MASK
- RT1011_PLL2_QK_SFT
- RT1011_PLL2_SRC_DIV_MASK
- RT1011_PLL2_SRC_DIV_SFT
- RT1011_PLL2_SRC_MASK
- RT1011_PLL2_SRC_MCLK
- RT1011_PLL2_SRC_RCCLK
- RT1011_PLL2_SRC_SFT
- RT1011_PLL2_S_MCLK
- RT1011_PLL2_S_RCCLK
- RT1011_PLLEN
- RT1011_PLLEN_BIT
- RT1011_PLL_1
- RT1011_PLL_2
- RT1011_PLL_INTERNAL_SET
- RT1011_POWD_ADC_T
- RT1011_POWD_ADC_T_BIT
- RT1011_POWER_1
- RT1011_POWER_2
- RT1011_POWER_3
- RT1011_POWER_4
- RT1011_POWER_5
- RT1011_POWER_6
- RT1011_POWER_7
- RT1011_POWER_8
- RT1011_POWER_9
- RT1011_POWER_SEQ
- RT1011_POW_ADC_I
- RT1011_POW_ADC_I_BIT
- RT1011_POW_ADC_T
- RT1011_POW_ADC_T_BIT
- RT1011_POW_ADC_V
- RT1011_POW_ADC_V_BIT
- RT1011_POW_BG
- RT1011_POW_BG_BIT
- RT1011_POW_BG_MBIAS_LV
- RT1011_POW_BG_MBIAS_LV_BIT
- RT1011_POW_CLK12M
- RT1011_POW_CLK12M_BIT
- RT1011_POW_DAC
- RT1011_POW_DAC_BIT
- RT1011_POW_DET_SPKVDD
- RT1011_POW_DET_SPKVDD_BIT
- RT1011_POW_DET_VBAT
- RT1011_POW_DET_VBAT_BIT
- RT1011_POW_EN_PASS_BGOK_SWR
- RT1011_POW_EN_PASS_BGOK_SWR_BIT
- RT1011_POW_EN_PASS_VPOK_SWR
- RT1011_POW_EN_PASS_VPOK_SWR_BIT
- RT1011_POW_EN_SWR
- RT1011_POW_EN_SWR_BIT
- RT1011_POW_FC
- RT1011_POW_FC_BIT
- RT1011_POW_ISENSE_SPK
- RT1011_POW_ISENSE_SPK_BIT
- RT1011_POW_LDO2
- RT1011_POW_LDO2_BIT
- RT1011_POW_LPF_SPK
- RT1011_POW_LPF_SPK_BIT
- RT1011_POW_MBIAS_LV
- RT1011_POW_MBIAS_LV_BIT
- RT1011_POW_MIX_I
- RT1011_POW_MIX_I_BIT
- RT1011_POW_MIX_T
- RT1011_POW_MIX_T_BIT
- RT1011_POW_MIX_V
- RT1011_POW_MIX_V_BIT
- RT1011_POW_MNL_SDB
- RT1011_POW_MNL_SDB_BIT
- RT1011_POW_MNL_SDB_MASK
- RT1011_POW_SDB_REG
- RT1011_POW_SDB_REG_BIT
- RT1011_POW_SDB_REG_MASK
- RT1011_POW_SEL_SDB_MODE
- RT1011_POW_SEL_SDB_MODE_BIT
- RT1011_POW_SEL_SDB_MODE_MASK
- RT1011_POW_SUM_I
- RT1011_POW_SUM_I_BIT
- RT1011_POW_SUM_V
- RT1011_POW_SUM_V_BIT
- RT1011_POW_TEMP
- RT1011_POW_TEMP_BIT
- RT1011_POW_TEMP_REG
- RT1011_POW_TEMP_REG_BIT
- RT1011_POW_TWO_BATTERY_SPK
- RT1011_POW_TWO_BATTERY_SPK_BIT
- RT1011_POW_VREF_LV
- RT1011_POW_VREF_LV_BIT
- RT1011_POW_VSENSE_SPK
- RT1011_POW_VSENSE_SPK_BIT
- RT1011_PRIV_DATA
- RT1011_PRIV_INDEX
- RT1011_PRO_GAIN_MODE
- RT1011_PWM_CAL
- RT1011_R0_LOAD
- RT1011_RECV_MODE
- RT1011_RECV_MODE_SPK_BIT
- RT1011_RECV_MODE_SPK_MASK
- RT1011_REG_DISP_LEN
- RT1011_REG_GAIN_CLASSD_RI_410K
- RT1011_REG_GAIN_CLASSD_RI_62P5K
- RT1011_REG_GAIN_CLASSD_RI_72P5K
- RT1011_REG_GAIN_CLASSD_RI_82P5K
- RT1011_REG_GAIN_CLASSD_RI_95K
- RT1011_REG_GAIN_CLASSD_RI_SPK_MASK
- RT1011_RESET
- RT1011_RT_DRC_BB_1
- RT1011_RT_DRC_BB_2
- RT1011_RT_DRC_BB_3
- RT1011_RT_DRC_BB_4
- RT1011_RT_DRC_BB_5
- RT1011_RT_DRC_BB_6
- RT1011_RT_DRC_BB_7
- RT1011_RT_DRC_BB_8
- RT1011_RT_DRC_CROSS
- RT1011_RT_DRC_HB_1
- RT1011_RT_DRC_HB_2
- RT1011_RT_DRC_HB_3
- RT1011_RT_DRC_HB_4
- RT1011_RT_DRC_HB_5
- RT1011_RT_DRC_HB_6
- RT1011_RT_DRC_HB_7
- RT1011_RT_DRC_HB_8
- RT1011_RT_DRC_POS_1
- RT1011_RT_DRC_POS_2
- RT1011_RT_DRC_POS_3
- RT1011_RT_DRC_POS_4
- RT1011_RT_DRC_POS_5
- RT1011_RT_DRC_POS_6
- RT1011_RT_DRC_POS_7
- RT1011_RT_DRC_POS_8
- RT1011_SEP_MAIN_OUT_15_0
- RT1011_SEP_MAIN_OUT_23_16
- RT1011_SEP_RE_REG_15_0
- RT1011_SHORT_CIRCUIT_DET_1
- RT1011_SHORT_CIRCUIT_DET_2
- RT1011_SIL_DET
- RT1011_SINE_GEN_REG_1
- RT1011_SINE_GEN_REG_2
- RT1011_SINE_GEN_REG_3
- RT1011_SMART_BOOST_TIMING_1
- RT1011_SMART_BOOST_TIMING_36
- RT1011_SPK_DC_O_15_0
- RT1011_SPK_DC_O_23_16
- RT1011_SPK_EXCURSION_15_0
- RT1011_SPK_EXCURSION_23_16
- RT1011_SPK_MODE
- RT1011_SPK_PRO_DC_DET_1
- RT1011_SPK_PRO_DC_DET_2
- RT1011_SPK_PRO_DC_DET_3
- RT1011_SPK_PRO_DC_DET_4
- RT1011_SPK_PRO_DC_DET_5
- RT1011_SPK_PRO_DC_DET_6
- RT1011_SPK_PRO_DC_DET_7
- RT1011_SPK_PRO_DC_DET_8
- RT1011_SPK_RESISTANCE_1
- RT1011_SPK_RESISTANCE_2
- RT1011_SPK_TEMP_PROTECT_0
- RT1011_SPK_TEMP_PROTECT_1
- RT1011_SPK_TEMP_PROTECT_2
- RT1011_SPK_TEMP_PROTECT_3
- RT1011_SPK_TEMP_PROTECT_4
- RT1011_SPK_TEMP_PROTECT_5
- RT1011_SPK_TEMP_PROTECT_6
- RT1011_SPK_TEMP_PROTECT_7
- RT1011_SPK_TEMP_PROTECT_8
- RT1011_SPK_TEMP_PROTECT_9
- RT1011_SPK_THERMAL
- RT1011_SPK_VOL_DET_1
- RT1011_SPK_VOL_DET_2
- RT1011_SPK_VOL_TEST_OUT
- RT1011_SPL_1
- RT1011_SPL_2
- RT1011_SPL_3
- RT1011_SPL_4
- RT1011_SPREAD_SPECTURM
- RT1011_SRCIN_DIV_MASK
- RT1011_SRCIN_DIV_SFT
- RT1011_SRC_1
- RT1011_SRC_2
- RT1011_SRC_3
- RT1011_STEREO_RATES
- RT1011_STP_ALPHA_RECIPROCAL_MSB
- RT1011_STP_BQ_1_A1_L_28_16
- RT1011_STP_BQ_1_H0_R_15_0
- RT1011_STP_BQ_2_A1_L_28_16
- RT1011_STP_CALIB_RS_TEMP
- RT1011_STP_EN
- RT1011_STP_EN_BIT
- RT1011_STP_EN_MASK
- RT1011_STP_INITIAL_RESISTANCE_TEMP
- RT1011_STP_INITIAL_RS_TEMP
- RT1011_STP_OTP_TH
- RT1011_STP_R0_EN
- RT1011_STP_R0_EN_BIT
- RT1011_STP_R0_EN_MASK
- RT1011_STP_R0_SELECT_EFUSE
- RT1011_STP_R0_SELECT_FORCE_ZERO
- RT1011_STP_R0_SELECT_MASK
- RT1011_STP_R0_SELECT_REG
- RT1011_STP_R0_SELECT_START_VAL
- RT1011_STP_RS_CLB_EN
- RT1011_STP_RS_CLB_EN_BIT
- RT1011_STP_RS_CLB_EN_MASK
- RT1011_STP_SIN_GEN_EN
- RT1011_STP_SIN_GEN_EN_BIT
- RT1011_STP_SIN_GEN_EN_MASK
- RT1011_STP_T0_EN
- RT1011_STP_T0_EN_BIT
- RT1011_STP_T0_EN_MASK
- RT1011_SYSTEM_RESET_1
- RT1011_SYSTEM_RESET_2
- RT1011_SYSTEM_RESET_3
- RT1011_TCON_BCLK_MST_INV
- RT1011_TCON_BCLK_MST_MASK
- RT1011_TCON_BCLK_MST_SFT
- RT1011_TCON_BCLK_SEL_128FS
- RT1011_TCON_BCLK_SEL_256FS
- RT1011_TCON_BCLK_SEL_32FS
- RT1011_TCON_BCLK_SEL_64FS
- RT1011_TCON_BCLK_SEL_MASK
- RT1011_TCON_BCLK_SEL_SFT
- RT1011_TCON_CH_LEN_16B
- RT1011_TCON_CH_LEN_20B
- RT1011_TCON_CH_LEN_24B
- RT1011_TCON_CH_LEN_32B
- RT1011_TCON_CH_LEN_MASK
- RT1011_TCON_CH_LEN_SFT
- RT1011_TCON_DF_I2S
- RT1011_TCON_DF_LEFT
- RT1011_TCON_DF_MASK
- RT1011_TCON_DF_PCM_A
- RT1011_TCON_DF_PCM_A_N
- RT1011_TCON_DF_PCM_B
- RT1011_TCON_DF_PCM_B_N
- RT1011_TCON_DF_SFT
- RT1011_TDM1_SET_1
- RT1011_TDM1_SET_2
- RT1011_TDM1_SET_3
- RT1011_TDM1_SET_4
- RT1011_TDM1_SET_5
- RT1011_TDM1_SET_TCON
- RT1011_TDM2_SET_1
- RT1011_TDM2_SET_2
- RT1011_TDM2_SET_3
- RT1011_TDM2_SET_4
- RT1011_TDM2_SET_5
- RT1011_TDM_I2S_DOCK_ADCDAT_2CH
- RT1011_TDM_I2S_DOCK_ADCDAT_4CH
- RT1011_TDM_I2S_DOCK_ADCDAT_6CH
- RT1011_TDM_I2S_DOCK_ADCDAT_8CH
- RT1011_TDM_I2S_DOCK_ADCDAT_LEN_1_MASK
- RT1011_TDM_I2S_DOCK_ADCDAT_LEN_2_MASK
- RT1011_TDM_I2S_DOCK_EN_1
- RT1011_TDM_I2S_DOCK_EN_1_MASK
- RT1011_TDM_I2S_DOCK_EN_1_SFT
- RT1011_TDM_I2S_DOCK_EN_2
- RT1011_TDM_I2S_DOCK_EN_2_MASK
- RT1011_TDM_I2S_DOCK_EN_2_SFT
- RT1011_TDM_INV_BCLK
- RT1011_TDM_INV_BCLK_MASK
- RT1011_TDM_INV_BCLK_SFT
- RT1011_TDM_TOTAL_SET
- RT1011_TEST_OUT_1
- RT1011_TEST_OUT_3
- RT1011_TEST_PAD_STATUS
- RT1011_THER_FOLD_BACK_1
- RT1011_THER_FOLD_BACK_2
- RT1011_TM_PORPVDD_SPK
- RT1011_TM_PORPVDD_SPK_BIT
- RT1011_VBAT_DET
- RT1011_VBAT_PROTECTION
- RT1011_VBAT_TEST_OUT_1
- RT1011_VBAT_TEST_OUT_2
- RT1011_VBAT_VOL_DET_1
- RT1011_VBAT_VOL_DET_2
- RT1011_VENDOR_ID
- RT1011_VERSION_ID
- RT1011_VREF_LV_1
- RT1305_ADC_SET_1
- RT1305_ADC_SET_2
- RT1305_ADC_SET_3
- RT1305_ADJUSTED_HPF_1
- RT1305_ADJUSTED_HPF_2
- RT1305_AIF1
- RT1305_AIFS
- RT1305_ALC_DRC_1
- RT1305_ALC_DRC_2
- RT1305_ALC_DRC_3
- RT1305_ALC_DRC_4
- RT1305_BIQUAD1_H0_L_28_16
- RT1305_BIQUAD3_A2_R_15_0
- RT1305_BIQUAD_SET_1
- RT1305_BIQUAD_SET_2
- RT1305_CAL_EFUSE_CLOCK
- RT1305_CLK_1
- RT1305_CLK_2
- RT1305_CLK_3
- RT1305_CLOCK_DETECT
- RT1305_DAC_OFFSET_1
- RT1305_DAC_OFFSET_10
- RT1305_DAC_OFFSET_11
- RT1305_DAC_OFFSET_12
- RT1305_DAC_OFFSET_13
- RT1305_DAC_OFFSET_14
- RT1305_DAC_OFFSET_2
- RT1305_DAC_OFFSET_3
- RT1305_DAC_OFFSET_4
- RT1305_DAC_OFFSET_5
- RT1305_DAC_OFFSET_6
- RT1305_DAC_OFFSET_7
- RT1305_DAC_OFFSET_8
- RT1305_DAC_OFFSET_9
- RT1305_DAC_SET_1
- RT1305_DAC_SET_2
- RT1305_DC_CALIB_1
- RT1305_DC_CALIB_2
- RT1305_DC_CALIB_3
- RT1305_DEVICE_ID
- RT1305_DEVICE_ID_NUM
- RT1305_DFLL_REG
- RT1305_DIV_FS_SYS_MASK
- RT1305_DIV_FS_SYS_SFT
- RT1305_DIV_PLL_SRC_2_MASK
- RT1305_DIV_PLL_SRC_2_SFT
- RT1305_DVOL_MUTE_L_EN_SFT
- RT1305_DVOL_MUTE_R_EN_SFT
- RT1305_EFUSE_1
- RT1305_EFUSE_2
- RT1305_EFUSE_3
- RT1305_EN_EFUSE_1P8V
- RT1305_EN_EFUSE_1P8V_BIT
- RT1305_EN_EFUSE_5V
- RT1305_EN_EFUSE_5V_BIT
- RT1305_EN_K_HV
- RT1305_EN_K_HV_BIT
- RT1305_EN_PRE_K_HV
- RT1305_EN_PRE_K_HV_BIT
- RT1305_EN_VCM_6172
- RT1305_EN_VCM_6172_BIT
- RT1305_EQ_SET_1
- RT1305_EQ_SET_2
- RT1305_FORMATS
- RT1305_FS_SYS_PRE_S_MCLK
- RT1305_FS_SYS_PRE_S_PLL1
- RT1305_FS_SYS_PRE_S_RCCLK
- RT1305_I2S_BCLK_INV
- RT1305_I2S_BCLK_MASK
- RT1305_I2S_BCLK_NORMAL
- RT1305_I2S_BCLK_SFT
- RT1305_I2S_DF_SEL_I2S
- RT1305_I2S_DF_SEL_LEFT
- RT1305_I2S_DF_SEL_MASK
- RT1305_I2S_DF_SEL_PCM_A
- RT1305_I2S_DF_SEL_PCM_B
- RT1305_I2S_DF_SEL_SFT
- RT1305_I2S_DL_SEL_16B
- RT1305_I2S_DL_SEL_20B
- RT1305_I2S_DL_SEL_24B
- RT1305_I2S_DL_SEL_8B
- RT1305_I2S_DL_SEL_MASK
- RT1305_I2S_DL_SEL_SFT
- RT1305_I2S_SET_1
- RT1305_I2S_SET_2
- RT1305_INIT_REG_LEN
- RT1305_LOUDNESS
- RT1305_MANUALLY_I2C_DEVICE
- RT1305_MAX_REG
- RT1305_MIXER_CTRL_1
- RT1305_MIXER_CTRL_2
- RT1305_PATH_SET
- RT1305_PBTL_MONO_MODE_SRC
- RT1305_PLL0_1
- RT1305_PLL0_2
- RT1305_PLL1_1
- RT1305_PLL1_2
- RT1305_PLL1_S_BCLK
- RT1305_PLL2_S_MCLK
- RT1305_PLL2_S_RCCLK
- RT1305_PLL_1_M_BYPASS
- RT1305_PLL_1_M_BYPASS_MASK
- RT1305_PLL_1_M_BYPASS_SFT
- RT1305_PLL_1_M_SFT
- RT1305_PLL_1_N_MASK
- RT1305_POR_AVDD1
- RT1305_POR_AVDD1_BIT
- RT1305_POR_AVDD2
- RT1305_POR_AVDD2_BIT
- RT1305_POR_EFUSE
- RT1305_POR_EFUSE_BIT
- RT1305_POWER_CTRL_1
- RT1305_POWER_CTRL_2
- RT1305_POWER_CTRL_3
- RT1305_POWER_CTRL_4
- RT1305_POWER_CTRL_5
- RT1305_POWER_STATUS
- RT1305_POW_ADC3_L
- RT1305_POW_ADC3_L_BIT
- RT1305_POW_ADC3_R
- RT1305_POW_ADC3_R_BIT
- RT1305_POW_BG2
- RT1305_POW_BG2_BIT
- RT1305_POW_BG_MBIAS_LV
- RT1305_POW_BG_MBIAS_LV_BIT
- RT1305_POW_BUFL
- RT1305_POW_BUFL_BIT
- RT1305_POW_BUFR
- RT1305_POW_BUFR_BIT
- RT1305_POW_CKXEN_DAC
- RT1305_POW_CKXEN_DAC_BIT
- RT1305_POW_CLAMP
- RT1305_POW_CLAMP_BIT
- RT1305_POW_DAC1_L
- RT1305_POW_DAC1_L_BIT
- RT1305_POW_DAC1_R
- RT1305_POW_DAC1_R_BIT
- RT1305_POW_DISC_VREF
- RT1305_POW_DISC_VREF_BIT
- RT1305_POW_EN_CKGEN_ADC
- RT1305_POW_EN_CKGEN_ADC_BIT
- RT1305_POW_EN_CKGEN_DAC
- RT1305_POW_EN_CKGEN_DAC_BIT
- RT1305_POW_FASTB_VREF
- RT1305_POW_FASTB_VREF_BIT
- RT1305_POW_ISENSE_LCH
- RT1305_POW_ISENSE_LCH_BIT
- RT1305_POW_ISENSE_RCH
- RT1305_POW_ISENSE_RCH_BIT
- RT1305_POW_LDO2
- RT1305_POW_LDO2_BIT
- RT1305_POW_LDO2_IB2
- RT1305_POW_LDO2_IB2_BIT
- RT1305_POW_MBIAS_LV
- RT1305_POW_MBIAS_LV_BIT
- RT1305_POW_PDB_JD
- RT1305_POW_PDB_JD_BIT
- RT1305_POW_PDB_JD_MASK
- RT1305_POW_PDB_JD_POLARITY
- RT1305_POW_PDB_JD_POLARITY_BIT
- RT1305_POW_PLL0_EN
- RT1305_POW_PLL0_EN_BIT
- RT1305_POW_PLL1_EN
- RT1305_POW_PLL1_EN_BIT
- RT1305_POW_POR_AVDD1
- RT1305_POW_POR_AVDD1_BIT
- RT1305_POW_POR_AVDD2
- RT1305_POW_POR_AVDD2_BIT
- RT1305_POW_TRIOSC
- RT1305_POW_TRIOSC_BIT
- RT1305_POW_ULTRA_FAST_VREF
- RT1305_POW_ULTRA_FAST_VREF_BIT
- RT1305_POW_VREF
- RT1305_POW_VREF1
- RT1305_POW_VREF1_BIT
- RT1305_POW_VREF2
- RT1305_POW_VREF2_BIT
- RT1305_POW_VREF_BIT
- RT1305_POW_VSENSE_LCH
- RT1305_POW_VSENSE_LCH_BIT
- RT1305_POW_VSENSE_RCH
- RT1305_POW_VSENSE_RCH_BIT
- RT1305_PRIV_DATA
- RT1305_PRIV_INDEX
- RT1305_PR_BASE
- RT1305_PR_RANGE_BASE
- RT1305_PR_SPACING
- RT1305_RESET
- RT1305_SEL_CLK_DET_SRC_BCLK
- RT1305_SEL_CLK_DET_SRC_MASK
- RT1305_SEL_CLK_DET_SRC_MCLK
- RT1305_SEL_CLK_DET_SRC_SFT
- RT1305_SEL_FS_SYS_PRE_MASK
- RT1305_SEL_FS_SYS_PRE_MCLK
- RT1305_SEL_FS_SYS_PRE_PLL
- RT1305_SEL_FS_SYS_PRE_RCCLK
- RT1305_SEL_FS_SYS_PRE_SFT
- RT1305_SEL_I2S_OUT_MODE_M
- RT1305_SEL_I2S_OUT_MODE_MASK
- RT1305_SEL_I2S_OUT_MODE_S
- RT1305_SEL_I2S_OUT_MODE_SFT
- RT1305_SEL_PLL_SRC_1_BCLK
- RT1305_SEL_PLL_SRC_1_DFLL
- RT1305_SEL_PLL_SRC_1_MASK
- RT1305_SEL_PLL_SRC_1_PLL2
- RT1305_SEL_PLL_SRC_1_SFT
- RT1305_SEL_PLL_SRC_2_MASK
- RT1305_SEL_PLL_SRC_2_MCLK
- RT1305_SEL_PLL_SRC_2_RCCLK
- RT1305_SEL_PLL_SRC_2_SFT
- RT1305_SILENCE_DETECT
- RT1305_SPDIF_IN_SET_1
- RT1305_SPDIF_IN_SET_2
- RT1305_SPDIF_IN_SET_3
- RT1305_SPDIF_OUT_SET_1
- RT1305_SPDIF_OUT_SET_2
- RT1305_SPDIF_OUT_SET_3
- RT1305_SPK_DC_DETECT_1
- RT1305_SPK_DC_DETECT_2
- RT1305_SPK_EXCURSION_LIMITER_7
- RT1305_SPK_TEMP_PROTECTION_0
- RT1305_SPK_TEMP_PROTECTION_1
- RT1305_SPK_TEMP_PROTECTION_2
- RT1305_SPK_TEMP_PROTECTION_3
- RT1305_STEREO_RATES
- RT1305_THERMAL_FOLD_BACK_1
- RT1305_THERMAL_FOLD_BACK_2
- RT1305_TRIM_1
- RT1305_TRIM_2
- RT1305_TUNE_INTERNAL_OSC
- RT1305_VENDOR_ID
- RT1305_VERSION_ID
- RT1308_ADC_SET
- RT1308_ADC_SET_INT
- RT1308_AD_FILTER_SET
- RT1308_AIF1
- RT1308_AIFS
- RT1308_BCLK_DET_EN
- RT1308_BCLK_DET_EN_MASK
- RT1308_BCLK_DET_EN_SFT
- RT1308_BQ1_EQ_L_1
- RT1308_BQ1_EQ_L_2
- RT1308_BQ1_EQ_L_3
- RT1308_BQ1_EQ_R_1
- RT1308_BQ1_EQ_R_2
- RT1308_BQ1_EQ_R_3
- RT1308_BQ1_L_A1
- RT1308_BQ1_L_A2
- RT1308_BQ1_L_B1
- RT1308_BQ1_L_B2
- RT1308_BQ1_L_H0
- RT1308_BQ1_R_A1
- RT1308_BQ1_R_A2
- RT1308_BQ1_R_B1
- RT1308_BQ1_R_B2
- RT1308_BQ1_R_H0
- RT1308_BQ2_EQ_L_1
- RT1308_BQ2_EQ_L_2
- RT1308_BQ2_EQ_L_3
- RT1308_BQ2_EQ_R_1
- RT1308_BQ2_EQ_R_2
- RT1308_BQ2_EQ_R_3
- RT1308_BQ2_L_A1
- RT1308_BQ2_L_A2
- RT1308_BQ2_L_B1
- RT1308_BQ2_L_B2
- RT1308_BQ2_L_H0
- RT1308_BQ2_R_A1
- RT1308_BQ2_R_A2
- RT1308_BQ2_R_B1
- RT1308_BQ2_R_B2
- RT1308_BQ2_R_H0
- RT1308_BQ_PARA_UPDATE
- RT1308_BQ_POST_VOL_L
- RT1308_BQ_POST_VOL_R
- RT1308_BQ_PRE_VOL_L
- RT1308_BQ_PRE_VOL_R
- RT1308_BQ_SET
- RT1308_CAL_OFFSET_DAC_L
- RT1308_CAL_OFFSET_DAC_PBTL
- RT1308_CAL_OFFSET_DAC_R
- RT1308_CAL_OFFSET_PWM_L
- RT1308_CAL_OFFSET_PWM_R
- RT1308_CAL_PWM_VOS_ADC_L
- RT1308_CAL_PWM_VOS_ADC_R
- RT1308_CLASS_D_SET_1
- RT1308_CLASS_D_SET_2
- RT1308_CLK_1
- RT1308_CLK_2
- RT1308_CLK_DET
- RT1308_CLK_GATING
- RT1308_DAC_BUF
- RT1308_DAC_SET
- RT1308_DATA_PATH
- RT1308_DC_CAL_1
- RT1308_DC_CAL_2
- RT1308_DC_CAL_L_OFFSET
- RT1308_DC_CAL_R_OFFSET
- RT1308_DC_DET
- RT1308_DC_DET_THRES
- RT1308_DEVICE_ID_NUM
- RT1308_DIV_FS_SYS_MASK
- RT1308_DIV_FS_SYS_SFT
- RT1308_DIV_PRE_PLL_MASK
- RT1308_DIV_PRE_PLL_SFT
- RT1308_DUMMY_REG
- RT1308_DVOL_MUTE_L_EN_SFT
- RT1308_DVOL_MUTE_R_EN_SFT
- RT1308_EFUSE_1
- RT1308_EFUSE_2
- RT1308_EFUSE_DATA_0_LSB
- RT1308_EFUSE_DATA_0_MSB
- RT1308_EFUSE_DATA_1_LSB
- RT1308_EFUSE_DATA_1_MSB
- RT1308_EFUSE_DATA_2_LSB
- RT1308_EFUSE_DATA_2_MSB
- RT1308_EFUSE_DATA_3_LSB
- RT1308_EFUSE_DATA_3_MSB
- RT1308_EFUSE_DATA_TEST_LSB
- RT1308_EFUSE_DATA_TEST_MSB
- RT1308_EFUSE_PROG_DEV
- RT1308_EFUSE_PROG_PVDD_L
- RT1308_EFUSE_PROG_PVDD_R
- RT1308_EFUSE_PROG_R0_L
- RT1308_EFUSE_PROG_R0_R
- RT1308_EFUSE_READ_ADC_L
- RT1308_EFUSE_READ_ADC_PBTL
- RT1308_EFUSE_READ_ADC_R
- RT1308_EFUSE_READ_DEV
- RT1308_EFUSE_READ_PVDD_L
- RT1308_EFUSE_READ_PVDD_PTBL
- RT1308_EFUSE_READ_PVDD_R
- RT1308_EFUSE_READ_R0
- RT1308_EFUSE_RESERVE
- RT1308_EFUSE_STATUS_1
- RT1308_EFUSE_STATUS_2
- RT1308_FORMATS
- RT1308_FS_SYS_S_BCLK
- RT1308_FS_SYS_S_MCLK
- RT1308_FS_SYS_S_PLL
- RT1308_FS_SYS_S_RCCLK
- RT1308_I2C_I2S_SDW_SET
- RT1308_I2S_BCLK_INV
- RT1308_I2S_BCLK_MASK
- RT1308_I2S_BCLK_NORMAL
- RT1308_I2S_BCLK_SFT
- RT1308_I2S_DF_SEL_I2S
- RT1308_I2S_DF_SEL_LEFT
- RT1308_I2S_DF_SEL_MASK
- RT1308_I2S_DF_SEL_PCM_A
- RT1308_I2S_DF_SEL_PCM_B
- RT1308_I2S_DF_SEL_SFT
- RT1308_I2S_DL_RX_SEL_16B
- RT1308_I2S_DL_RX_SEL_20B
- RT1308_I2S_DL_RX_SEL_24B
- RT1308_I2S_DL_RX_SEL_32B
- RT1308_I2S_DL_RX_SEL_8B
- RT1308_I2S_DL_RX_SEL_MASK
- RT1308_I2S_DL_RX_SEL_SFT
- RT1308_I2S_DL_SEL_16B
- RT1308_I2S_DL_SEL_20B
- RT1308_I2S_DL_SEL_24B
- RT1308_I2S_DL_SEL_32B
- RT1308_I2S_DL_SEL_8B
- RT1308_I2S_DL_SEL_MASK
- RT1308_I2S_DL_SEL_SFT
- RT1308_I2S_DL_TX_SEL_16B
- RT1308_I2S_DL_TX_SEL_20B
- RT1308_I2S_DL_TX_SEL_24B
- RT1308_I2S_DL_TX_SEL_32B
- RT1308_I2S_DL_TX_SEL_8B
- RT1308_I2S_DL_TX_SEL_MASK
- RT1308_I2S_DL_TX_SEL_SFT
- RT1308_I2S_SET_1
- RT1308_I2S_SET_2
- RT1308_I2S_TX_DAC_SET
- RT1308_INIT_REG_LEN
- RT1308_IV_SENSE
- RT1308_LDO
- RT1308_MAX_REG
- RT1308_MBIAS
- RT1308_MCLK_DET_EN
- RT1308_MCLK_DET_EN_MASK
- RT1308_MCLK_DET_EN_SFT
- RT1308_PADS_1
- RT1308_PADS_2
- RT1308_PLL1_K_MASK
- RT1308_PLL1_K_SFT
- RT1308_PLL1_M_BYPASS
- RT1308_PLL1_M_BYPASS_MASK
- RT1308_PLL1_M_BYPASS_SFT
- RT1308_PLL1_M_MASK
- RT1308_PLL1_M_SFT
- RT1308_PLL1_N_MASK
- RT1308_PLL1_N_SFT
- RT1308_PLL_1
- RT1308_PLL_2
- RT1308_PLL_INT
- RT1308_PLL_S_BCLK
- RT1308_PLL_S_MCLK
- RT1308_PLL_S_RCCLK
- RT1308_POWER
- RT1308_POWER_INT
- RT1308_POWER_STATUS
- RT1308_POW_ADC_L
- RT1308_POW_ADC_L_BIT
- RT1308_POW_ADC_R
- RT1308_POW_ADC_R_BIT
- RT1308_POW_ALDO
- RT1308_POW_ALDO_BIT
- RT1308_POW_CLK25M
- RT1308_POW_CLK25M_BIT
- RT1308_POW_DAC1
- RT1308_POW_DAC1_BIT
- RT1308_POW_DACL
- RT1308_POW_DACL_BIT
- RT1308_POW_DBG
- RT1308_POW_DBG_BIT
- RT1308_POW_DLDO
- RT1308_POW_DLDO_BIT
- RT1308_POW_MBIAS20U
- RT1308_POW_MBIAS20U_BIT
- RT1308_POW_MBIAS4U
- RT1308_POW_MBIAS4U_BIT
- RT1308_POW_MIXER_L
- RT1308_POW_MIXER_L_BIT
- RT1308_POW_MIXER_R
- RT1308_POW_MIXER_R_BIT
- RT1308_POW_PDB_MN_BIT
- RT1308_POW_PDB_REG_BIT
- RT1308_POW_PDB_SRC_BIT
- RT1308_POW_PLL2B2_EN
- RT1308_POW_PLL2B2_EN_BIT
- RT1308_POW_PLL2B_EN
- RT1308_POW_PLL2B_EN_BIT
- RT1308_POW_PLL2F2_EN
- RT1308_POW_PLL2F2_EN_BIT
- RT1308_POW_PLL2F_EN
- RT1308_POW_PLL2F_EN_BIT
- RT1308_POW_PLL2_LDO_EN
- RT1308_POW_PLL2_LDO_EN_BIT
- RT1308_POW_VREF
- RT1308_POW_VREF_BIT
- RT1308_PVDD_OFFSET_CTL
- RT1308_PVDD_OFFSET_L
- RT1308_PVDD_OFFSET_PBTL
- RT1308_PVDD_OFFSET_PVDD
- RT1308_PVDD_OFFSET_R
- RT1308_RESET
- RT1308_RESET_N
- RT1308_SDW_REG_RDATA
- RT1308_SDW_REG_RW
- RT1308_SEL_FS_SYS_MASK
- RT1308_SEL_FS_SYS_SFT
- RT1308_SEL_FS_SYS_SRC_BCLK
- RT1308_SEL_FS_SYS_SRC_MCLK
- RT1308_SEL_FS_SYS_SRC_PLL
- RT1308_SEL_FS_SYS_SRC_RCCLK
- RT1308_SEL_PLL_SRC_BCLK
- RT1308_SEL_PLL_SRC_MASK
- RT1308_SEL_PLL_SRC_MCLK
- RT1308_SEL_PLL_SRC_RCCLK
- RT1308_SEL_PLL_SRC_SFT
- RT1308_SIL_DET
- RT1308_SINE_TONE_GEN_1
- RT1308_SINE_TONE_GEN_2
- RT1308_SPK_BOUND
- RT1308_SRC_SET
- RT1308_STEREO_RATES
- RT1308_TCON_1
- RT1308_TCON_2
- RT1308_TEST_1
- RT1308_TEST_2
- RT1308_TEST_3
- RT1308_TEST_4
- RT1308_TEST_MODE
- RT1308_VEN_DEV_ID
- RT1308_VERSION_ID
- RT1308_VREF
- RT1711H_PID
- RT1711H_RTCTRL11
- RT1711H_RTCTRL11_SET
- RT1711H_RTCTRL13
- RT1711H_RTCTRL14
- RT1711H_RTCTRL15
- RT1711H_RTCTRL16
- RT1711H_RTCTRL8
- RT1711H_RTCTRL8_SET
- RT1711H_VID
- RT1bl
- RT1d
- RT2
- RT2400PCI_H
- RT2460
- RT2500PCI_H
- RT2500USB_H
- RT2560
- RT2560_VERSION_B
- RT2560_VERSION_C
- RT2560_VERSION_D
- RT2561_PCI_ID
- RT2561s_PCI_ID
- RT2570
- RT2570_VERSION_B
- RT2570_VERSION_C
- RT2570_VERSION_D
- RT2573
- RT2661
- RT2661_PCI_ID
- RT274_ADC0_MUX
- RT274_ADC1_MUX
- RT274_ADCL_GAIN
- RT274_ADCR_GAIN
- RT274_ADC_FORMAT
- RT274_ADC_IN1
- RT274_ADC_IN2
- RT274_ADC_SEL_DMIC
- RT274_ADC_SEL_LINE1
- RT274_ADC_SEL_LINE2
- RT274_ADC_SEL_MASK
- RT274_ADC_SEL_MIC
- RT274_ADC_SEL_SFT
- RT274_AIF1
- RT274_AIFS
- RT274_AUDIO_FUNCTION_GROUP
- RT274_CLK_CTRL
- RT274_CLK_SRC_MASK
- RT274_CLK_SRC_MCLK
- RT274_CLK_SRC_PLL2
- RT274_COEF58_COEF
- RT274_COEF58_INDEX
- RT274_COEF5b_COEF
- RT274_COEF5b_INDEX
- RT274_COEF_INDEX
- RT274_DAC0L_GAIN
- RT274_DAC0R_GAIN
- RT274_DAC1L_GAIN
- RT274_DAC1R_GAIN
- RT274_DAC_FORMAT
- RT274_DAC_OUT0
- RT274_DAC_OUT1
- RT274_DIG_CVT
- RT274_DMIC1
- RT274_DMIC2
- RT274_EAPD_GPIO_IRQ_CTRL
- RT274_FORMATS
- RT274_GET_HP_SENSE
- RT274_GET_MIC_SENSE
- RT274_GET_PARAM
- RT274_GPI2_SEL_CBJ
- RT274_GPI2_SEL_DMIC_CLK
- RT274_GPI2_SEL_GPIO2
- RT274_GPI2_SEL_I2S
- RT274_GPI2_SEL_MASK
- RT274_HPOL_GAIN
- RT274_HPOR_GAIN
- RT274_HPO_MUX
- RT274_HP_OUT
- RT274_HP_SEL_F
- RT274_HP_SEL_MASK
- RT274_HP_SEL_S
- RT274_HP_SEL_SFT
- RT274_I2S_CTRL1
- RT274_I2S_CTRL2
- RT274_I2S_FMT_I2S
- RT274_I2S_FMT_LJ
- RT274_I2S_FMT_MASK
- RT274_I2S_FMT_PCMA
- RT274_I2S_FMT_PCMB
- RT274_I2S_MODE_M
- RT274_I2S_MODE_MASK
- RT274_I2S_MODE_S
- RT274_INLINE_CMD
- RT274_IRQ_CLR
- RT274_IRQ_DIS
- RT274_IRQ_EN
- RT274_LINE1
- RT274_LINE2
- RT274_LINE3
- RT274_LOUTL_GAIN
- RT274_LOUTR_GAIN
- RT274_LOUT_MUX
- RT274_MCLK_CTRL
- RT274_MCLK_MODE_DIS
- RT274_MCLK_MODE_EN
- RT274_MCLK_MODE_MASK
- RT274_MIC
- RT274_MIC_GAIN
- RT274_MIXER_IN1
- RT274_MIXER_IN2
- RT274_MUTE_SFT
- RT274_M_HP_MUX_SFT
- RT274_PAD_CTRL12
- RT274_PLL2_CTRL
- RT274_PLL2_SRC_BCLK
- RT274_PLL2_SRC_MASK
- RT274_PLL2_SRC_MCLK
- RT274_PLL2_S_BCLK
- RT274_PLL2_S_MCLK
- RT274_PROC_COEF
- RT274_RESET
- RT274_SCLK_S_MCLK
- RT274_SCLK_S_PLL1
- RT274_SCLK_S_PLL2
- RT274_SET_AMP_GAIN_ADC_IN1
- RT274_SET_AMP_GAIN_ADC_IN2
- RT274_SET_AMP_GAIN_HPO
- RT274_SET_AUDIO_POWER
- RT274_SET_DMIC1_POWER
- RT274_SET_DMIC2_DEFAULT
- RT274_SET_EAPD_HIGH
- RT274_SET_EAPD_LOW
- RT274_SET_HPO_POWER
- RT274_SET_MIC
- RT274_SET_PIN_DIG_CVT
- RT274_SET_PIN_DISABLE
- RT274_SET_PIN_DMIC1
- RT274_SET_PIN_ENABLE
- RT274_SET_PIN_HPO
- RT274_SET_PIN_LOUT3
- RT274_SET_PIN_SFT
- RT274_SET_PIN_SPDIF
- RT274_SET_POWER
- RT274_SET_SPDIF_DEFAULT
- RT274_SET_STREAMID_ADC1
- RT274_SET_STREAMID_ADC2
- RT274_SET_STREAMID_DAC0
- RT274_SET_STREAMID_DAC1
- RT274_SPDIF
- RT274_STEREO_RATES
- RT274_TDM_2CH
- RT274_TDM_4CH
- RT274_TDM_CH_NUM
- RT274_TDM_DIS
- RT274_TDM_EN
- RT274_UNSOLICITED_HP_OUT
- RT274_UNSOLICITED_INLINE_CMD
- RT274_UNSOLICITED_MIC
- RT274_VENDOR_ID
- RT274_VENDOR_REGISTERS
- RT2800LIB_H
- RT2800MMIO_H
- RT2800PCI_H
- RT2800USB_H
- RT2800_H
- RT2860
- RT286_ADC0_MUX
- RT286_ADC1_MUX
- RT286_ADCL_GAIN
- RT286_ADCR_GAIN
- RT286_ADC_FORMAT
- RT286_ADC_IN1
- RT286_ADC_IN2
- RT286_ADC_SEL_BEEP
- RT286_ADC_SEL_DMIC
- RT286_ADC_SEL_FRONT
- RT286_ADC_SEL_I2S
- RT286_ADC_SEL_LINE1
- RT286_ADC_SEL_MASK
- RT286_ADC_SEL_MIC1
- RT286_ADC_SEL_SFT
- RT286_ADC_SEL_SURR
- RT286_AIF1
- RT286_AIF2
- RT286_AIFS
- RT286_AUDIO_FUNCTION_GROUP
- RT286_A_BIAS_CTRL1
- RT286_A_BIAS_CTRL2
- RT286_A_BIAS_CTRL3
- RT286_BEEP
- RT286_CBJ_CTRL1
- RT286_CBJ_CTRL2
- RT286_CLK_DIV
- RT286_COEF_INDEX
- RT286_DACL_GAIN
- RT286_DACR_GAIN
- RT286_DAC_FORMAT
- RT286_DAC_OUT1
- RT286_DAC_OUT2
- RT286_DC_GAIN
- RT286_DEPOP_CTRL1
- RT286_DEPOP_CTRL2
- RT286_DEPOP_CTRL3
- RT286_DEPOP_CTRL4
- RT286_DMIC1
- RT286_DMIC2
- RT286_FORMATS
- RT286_F_DAC_SWITCH
- RT286_F_RECMIX_SWITCH
- RT286_GET_HP_SENSE
- RT286_GET_MIC1_SENSE
- RT286_GET_PARAM
- RT286_GPIO_CTRL
- RT286_HPOL_GAIN
- RT286_HPOR_GAIN
- RT286_HPO_MUX
- RT286_HP_OUT
- RT286_HP_SEL_F
- RT286_HP_SEL_MASK
- RT286_HP_SEL_S
- RT286_HP_SEL_SFT
- RT286_I2S_CTRL1
- RT286_I2S_CTRL2
- RT286_IRQ_CTRL
- RT286_LINE1
- RT286_MIC1
- RT286_MIC1_DET_CTRL
- RT286_MIC_GAIN
- RT286_MISC_CTRL1
- RT286_MIXER_IN
- RT286_MIXER_IN1
- RT286_MIXER_IN2
- RT286_MIXER_OUT1
- RT286_MIXER_OUT2
- RT286_MUTE_SFT
- RT286_M_FRONT_DAC_SFT
- RT286_M_FRONT_REC_SFT
- RT286_M_HP_MUX_SFT
- RT286_M_REC_BEEP_SFT
- RT286_M_REC_I2S_SFT
- RT286_M_REC_LINE1_SFT
- RT286_M_REC_MIC1_SFT
- RT286_M_SPK_MUX_SFT
- RT286_PLL_CTRL
- RT286_PLL_CTRL1
- RT286_POWER_CTRL1
- RT286_POWER_CTRL2
- RT286_POWER_CTRL3
- RT286_POWER_REG_LEN
- RT286_PROC_COEF
- RT286_REC_BEEP_SWITCH
- RT286_REC_I2S_SWITCH
- RT286_REC_LINE_SWITCH
- RT286_REC_MIC_SWITCH
- RT286_SCLK_S_MCLK
- RT286_SCLK_S_PLL
- RT286_SET_AMP_GAIN_ADC_IN1
- RT286_SET_AMP_GAIN_ADC_IN2
- RT286_SET_AMP_GAIN_HPO
- RT286_SET_AUDIO_POWER
- RT286_SET_DMIC1_POWER
- RT286_SET_DMIC2_DEFAULT
- RT286_SET_EAPD_HIGH
- RT286_SET_EAPD_LOW
- RT286_SET_GPIO_DATA
- RT286_SET_GPIO_DIRECTION
- RT286_SET_GPIO_MASK
- RT286_SET_HPO_POWER
- RT286_SET_MIC1
- RT286_SET_PIN_DISABLE
- RT286_SET_PIN_DMIC1
- RT286_SET_PIN_ENABLE
- RT286_SET_PIN_HPO
- RT286_SET_PIN_SFT
- RT286_SET_PIN_SPK
- RT286_SET_POWER
- RT286_SET_SPK_POWER
- RT286_SPDIF
- RT286_SPDIF_SEL_PCM0
- RT286_SPDIF_SEL_PCM1
- RT286_SPDIF_SEL_PP
- RT286_SPDIF_SEL_SFT
- RT286_SPDIF_SEL_SPOUT
- RT286_SPK_EAPD
- RT286_SPK_MUX
- RT286_SPK_OUT
- RT286_SPK_SEL_F
- RT286_SPK_SEL_MASK
- RT286_SPK_SEL_S
- RT286_SPK_SEL_SFT
- RT286_SPOL_GAIN
- RT286_SPOR_GAIN
- RT286_STEREO_RATES
- RT286_VENDOR_ID
- RT286_VENDOR_REGISTERS
- RT2872
- RT2880_CHIP_NAME0
- RT2880_CHIP_NAME1
- RT2880_GPIO_MODE_I2C
- RT2880_GPIO_MODE_JTAG
- RT2880_GPIO_MODE_MDIO
- RT2880_GPIO_MODE_PCI
- RT2880_GPIO_MODE_SDRAM
- RT2880_GPIO_MODE_SPI
- RT2880_GPIO_MODE_UART0
- RT2880_GPIO_MODE_UART1
- RT2880_MEM_SIZE_MAX
- RT2880_MEM_SIZE_MIN
- RT2880_PCI_BASE
- RT2880_PCI_IO_BASE
- RT2880_PCI_IO_SIZE
- RT2880_PCI_MEM_BASE
- RT2880_PCI_MEM_SIZE
- RT2880_PCI_REG_ARBCTL
- RT2880_PCI_REG_BAR0SETUP_ADDR
- RT2880_PCI_REG_CLASS
- RT2880_PCI_REG_CONFIG_ADDR
- RT2880_PCI_REG_CONFIG_DATA
- RT2880_PCI_REG_ID
- RT2880_PCI_REG_IMBASEBAR0_ADDR
- RT2880_PCI_REG_IOBASE
- RT2880_PCI_REG_MEMBASE
- RT2880_PCI_REG_PCICFG_ADDR
- RT2880_PCI_REG_PCIMSK_ADDR
- RT2880_PCI_REG_SUBID
- RT2880_SDRAM_BASE
- RT2880_SOC
- RT2880_SYSC_BASE
- RT2883
- RT288X_CPU_IRQ_PCI
- RT288_VENDOR_ID
- RT298_ADC0_MUX
- RT298_ADC1_MUX
- RT298_ADCL_GAIN
- RT298_ADCR_GAIN
- RT298_ADC_FORMAT
- RT298_ADC_IN1
- RT298_ADC_IN2
- RT298_ADC_SEL_BEEP
- RT298_ADC_SEL_DMIC
- RT298_ADC_SEL_FRONT
- RT298_ADC_SEL_I2S
- RT298_ADC_SEL_LINE1
- RT298_ADC_SEL_MASK
- RT298_ADC_SEL_MIC1
- RT298_ADC_SEL_SFT
- RT298_ADC_SEL_SURR
- RT298_AIF1
- RT298_AIF2
- RT298_AIFS
- RT298_AUDIO_FUNCTION_GROUP
- RT298_A_BIAS_CTRL1
- RT298_A_BIAS_CTRL2
- RT298_A_BIAS_CTRL3
- RT298_BEEP
- RT298_CBJ_CTRL1
- RT298_CBJ_CTRL2
- RT298_CLK_DIV
- RT298_COEF_INDEX
- RT298_DACL_GAIN
- RT298_DACR_GAIN
- RT298_DAC_FORMAT
- RT298_DAC_OUT1
- RT298_DAC_OUT2
- RT298_DC_GAIN
- RT298_DEPOP_CTRL1
- RT298_DEPOP_CTRL2
- RT298_DEPOP_CTRL3
- RT298_DEPOP_CTRL4
- RT298_DIG_CVT
- RT298_DMIC1
- RT298_DMIC2
- RT298_D_FILTER_CTRL
- RT298_FORMATS
- RT298_F_DAC_SWITCH
- RT298_F_RECMIX_SWITCH
- RT298_GET_HP_SENSE
- RT298_GET_MIC1_SENSE
- RT298_GET_PARAM
- RT298_HPOL_GAIN
- RT298_HPOR_GAIN
- RT298_HPO_MUX
- RT298_HP_OUT
- RT298_HP_SEL_F
- RT298_HP_SEL_MASK
- RT298_HP_SEL_S
- RT298_HP_SEL_SFT
- RT298_I2S_CTRL1
- RT298_I2S_CTRL2
- RT298_INLINE_CMD
- RT298_IRQ_CTRL
- RT298_IRQ_FLAG_CTRL
- RT298_LINE1
- RT298_MIC1
- RT298_MIC1_DET_CTRL
- RT298_MIC_GAIN
- RT298_MISC_CTRL1
- RT298_MIXER_IN
- RT298_MIXER_IN1
- RT298_MIXER_IN2
- RT298_MIXER_OUT1
- RT298_MIXER_OUT2
- RT298_MUTE_SFT
- RT298_M_FRONT_DAC_SFT
- RT298_M_FRONT_REC_SFT
- RT298_M_HP_MUX_SFT
- RT298_M_REC_BEEP_SFT
- RT298_M_REC_I2S_SFT
- RT298_M_REC_LINE1_SFT
- RT298_M_REC_MIC1_SFT
- RT298_M_SPK_MUX_SFT
- RT298_PLL_CTRL
- RT298_PLL_CTRL1
- RT298_POWER_CTRL1
- RT298_POWER_CTRL2
- RT298_POWER_CTRL3
- RT298_POWER_REG_LEN
- RT298_PROC_COEF
- RT298_REC_BEEP_SWITCH
- RT298_REC_I2S_SWITCH
- RT298_REC_LINE_SWITCH
- RT298_REC_MIC_SWITCH
- RT298_SCLK_S_MCLK
- RT298_SCLK_S_PLL
- RT298_SET_AMP_GAIN_ADC_IN1
- RT298_SET_AMP_GAIN_ADC_IN2
- RT298_SET_AMP_GAIN_HPO
- RT298_SET_AUDIO_POWER
- RT298_SET_DMIC1_POWER
- RT298_SET_DMIC2_DEFAULT
- RT298_SET_EAPD_HIGH
- RT298_SET_EAPD_LOW
- RT298_SET_HPO_POWER
- RT298_SET_MIC1
- RT298_SET_PIN_DIG_CVT
- RT298_SET_PIN_DISABLE
- RT298_SET_PIN_DMIC1
- RT298_SET_PIN_ENABLE
- RT298_SET_PIN_HPO
- RT298_SET_PIN_SFT
- RT298_SET_PIN_SPDIF
- RT298_SET_PIN_SPK
- RT298_SET_POWER
- RT298_SET_SPDIF_DEFAULT
- RT298_SET_SPK_POWER
- RT298_SPDIF
- RT298_SPDIF_SEL_PCM0
- RT298_SPDIF_SEL_PCM1
- RT298_SPDIF_SEL_PP
- RT298_SPDIF_SEL_SFT
- RT298_SPDIF_SEL_SPOUT
- RT298_SPK_EAPD
- RT298_SPK_MUX
- RT298_SPK_OUT
- RT298_SPK_SEL_F
- RT298_SPK_SEL_MASK
- RT298_SPK_SEL_S
- RT298_SPK_SEL_SFT
- RT298_SPOL_GAIN
- RT298_SPOR_GAIN
- RT298_STEREO_RATES
- RT298_UNSOLICITED_HP_OUT
- RT298_UNSOLICITED_INLINE_CMD
- RT298_UNSOLICITED_MIC1
- RT298_VAD_CTRL
- RT298_VENDOR_ID
- RT298_VENDOR_REGISTERS
- RT298_WIND_FILTER_CTRL
- RT2X00DEBUGFS_CREATE_REGISTER_ENTRY
- RT2X00DEBUGFS_OFFSET
- RT2X00DEBUGFS_OPS
- RT2X00DEBUGFS_OPS_READ
- RT2X00DEBUGFS_OPS_WRITE
- RT2X00DEBUGFS_REGISTER_ENTRY
- RT2X00DEBUGFS_SPRINTF_REGISTER
- RT2X00DEBUG_H
- RT2X00DUMP_H
- RT2X00LEDS_H
- RT2X00LIB_H
- RT2X00MMIO_H
- RT2X00PCI_H
- RT2X00QUEUE_H
- RT2X00REG_H
- RT2X00SOC_H
- RT2X00USB_H
- RT2X00_ALIGN_SIZE
- RT2X00_CHIP_INTF_PCI
- RT2X00_CHIP_INTF_PCIE
- RT2X00_CHIP_INTF_SOC
- RT2X00_CHIP_INTF_USB
- RT2X00_H
- RT2X00_L2PAD_SIZE
- RT2X00_TASKLET_INIT
- RT2_OFFSET
- RT2bl
- RT2d
- RT3
- RT3052_CHIP_NAME0
- RT3052_CHIP_NAME1
- RT305X_GPIO_10
- RT305X_GPIO_14
- RT305X_GPIO_7
- RT305X_GPIO_GE0_RXCLK
- RT305X_GPIO_GE0_TXD0
- RT305X_GPIO_I2C_SCLK
- RT305X_GPIO_I2C_SD
- RT305X_GPIO_JTAG_TDI
- RT305X_GPIO_JTAG_TDO
- RT305X_GPIO_MDIO_MDC
- RT305X_GPIO_MDIO_MDIO
- RT305X_GPIO_MODE_GPIO
- RT305X_GPIO_MODE_GPIO_I2S
- RT305X_GPIO_MODE_GPIO_UARTF
- RT305X_GPIO_MODE_I2C
- RT305X_GPIO_MODE_I2S_UARTF
- RT305X_GPIO_MODE_JTAG
- RT305X_GPIO_MODE_MDIO
- RT305X_GPIO_MODE_PCM_GPIO
- RT305X_GPIO_MODE_PCM_I2S
- RT305X_GPIO_MODE_PCM_UARTF
- RT305X_GPIO_MODE_RGMII
- RT305X_GPIO_MODE_SDRAM
- RT305X_GPIO_MODE_SPI
- RT305X_GPIO_MODE_UART0
- RT305X_GPIO_MODE_UART0_MASK
- RT305X_GPIO_MODE_UART0_SHIFT
- RT305X_GPIO_MODE_UART1
- RT305X_GPIO_MODE_UARTF
- RT305X_GPIO_SDRAM_MD16
- RT305X_GPIO_SDRAM_MD31
- RT305X_GPIO_SPI_CLK
- RT305X_GPIO_SPI_EN
- RT305X_GPIO_UART1_RXD
- RT305X_GPIO_UART1_TXD
- RT305X_MEM_SIZE_MAX
- RT305X_MEM_SIZE_MIN
- RT305X_SDRAM_BASE
- RT305X_SOC_RT3050
- RT305X_SOC_RT3052
- RT305X_SOC_RT3350
- RT305X_SOC_RT3352
- RT305X_SOC_RT5350
- RT305X_SYSCFG_CPUCLK_HIGH
- RT305X_SYSCFG_CPUCLK_LOW
- RT305X_SYSCFG_CPUCLK_MASK
- RT305X_SYSCFG_CPUCLK_SHIFT
- RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT
- RT305X_SYSCFG_SRAM_CS0_MODE_WDT
- RT305X_SYSC_BASE
- RT3070
- RT3071
- RT3090
- RT3290
- RT3350_CHIP_NAME0
- RT3350_CHIP_NAME1
- RT3352
- RT3352_CHIP_NAME0
- RT3352_CHIP_NAME1
- RT3352_CLKCFG0_XTAL_SEL
- RT3352_CLKCFG1_UPHY0_CLK_EN
- RT3352_CLKCFG1_UPHY1_CLK_EN
- RT3352_GPIO_MODE_LNA
- RT3352_GPIO_MODE_PA
- RT3352_MEM_SIZE_MAX
- RT3352_MEM_SIZE_MIN
- RT3352_RSTCTRL_UDEV
- RT3352_RSTCTRL_UHST
- RT3352_SYSCFG0_CPUCLK_HIGH
- RT3352_SYSCFG0_CPUCLK_LOW
- RT3352_SYSCFG0_CPUCLK_MASK
- RT3352_SYSCFG0_CPUCLK_SHIFT
- RT3352_SYSCFG1_USB0_HOST_MODE
- RT3352_SYSC_REG_CLKCFG1
- RT3352_SYSC_REG_RSTCTRL
- RT3352_SYSC_REG_SYSCFG0
- RT3352_SYSC_REG_SYSCFG1
- RT3352_SYSC_REG_USB_PS
- RT3390
- RT3572
- RT3593
- RT3883
- RT3883_BOOT_BASE
- RT3883_BOOT_SIZE
- RT3883_CHIP_NAME0
- RT3883_CHIP_NAME1
- RT3883_CLKCFG1_PCIE_CLK_EN
- RT3883_CLKCFG1_PCI_CLK_EN
- RT3883_CLKCFG1_UPHY0_CLK_EN
- RT3883_CLKCFG1_UPHY1_CLK_EN
- RT3883_CODEC1_BASE
- RT3883_CODEC1_SIZE
- RT3883_CODEC2_BASE
- RT3883_CODEC2_SIZE
- RT3883_EHCI_BASE
- RT3883_FE_BASE
- RT3883_FE_SIZE
- RT3883_FLASH_CFG_WIDTH_16BIT
- RT3883_FLASH_CFG_WIDTH_32BIT
- RT3883_FLASH_CFG_WIDTH_8BIT
- RT3883_FLASH_CFG_WIDTH_MASK
- RT3883_FLASH_CFG_WIDTH_SHIFT
- RT3883_FSCC_BASE
- RT3883_FSCC_REG_CODEC_CFG0
- RT3883_FSCC_REG_CODEC_CFG1
- RT3883_FSCC_REG_FLASH_CFG0
- RT3883_FSCC_REG_FLASH_CFG1
- RT3883_FSCC_SIZE
- RT3883_GDMA_BASE
- RT3883_GDMA_SIZE
- RT3883_GPIO_10
- RT3883_GPIO_11
- RT3883_GPIO_14
- RT3883_GPIO_7
- RT3883_GPIO_GE1_RXCLK
- RT3883_GPIO_GE1_RXD0
- RT3883_GPIO_GE1_RXD1
- RT3883_GPIO_GE1_RXD2
- RT3883_GPIO_GE1_RXD3
- RT3883_GPIO_GE1_RXDV
- RT3883_GPIO_GE1_TXCLK
- RT3883_GPIO_GE1_TXD0
- RT3883_GPIO_GE1_TXD1
- RT3883_GPIO_GE1_TXD2
- RT3883_GPIO_GE1_TXD3
- RT3883_GPIO_GE1_TXEN
- RT3883_GPIO_GE2_RXCLK
- RT3883_GPIO_GE2_RXD0
- RT3883_GPIO_GE2_RXD1
- RT3883_GPIO_GE2_RXD2
- RT3883_GPIO_GE2_RXD3
- RT3883_GPIO_GE2_RXDV
- RT3883_GPIO_GE2_TXCLK
- RT3883_GPIO_GE2_TXD0
- RT3883_GPIO_GE2_TXD1
- RT3883_GPIO_GE2_TXD2
- RT3883_GPIO_GE2_TXD3
- RT3883_GPIO_GE2_TXEN
- RT3883_GPIO_I2C_SCLK
- RT3883_GPIO_I2C_SD
- RT3883_GPIO_JTAG_TCLK
- RT3883_GPIO_JTAG_TDI
- RT3883_GPIO_JTAG_TDO
- RT3883_GPIO_JTAG_TMS
- RT3883_GPIO_JTAG_TRST_N
- RT3883_GPIO_LNA_PE_A0
- RT3883_GPIO_LNA_PE_A1
- RT3883_GPIO_LNA_PE_A2
- RT3883_GPIO_LNA_PE_G0
- RT3883_GPIO_LNA_PE_G1
- RT3883_GPIO_LNA_PE_G2
- RT3883_GPIO_MDIO_MDC
- RT3883_GPIO_MDIO_MDIO
- RT3883_GPIO_MODE_GE1
- RT3883_GPIO_MODE_GE2
- RT3883_GPIO_MODE_GPIO
- RT3883_GPIO_MODE_GPIO_I2S
- RT3883_GPIO_MODE_GPIO_UARTF
- RT3883_GPIO_MODE_I2C
- RT3883_GPIO_MODE_I2S_UARTF
- RT3883_GPIO_MODE_JTAG
- RT3883_GPIO_MODE_LNA_A
- RT3883_GPIO_MODE_LNA_A_GPIO
- RT3883_GPIO_MODE_LNA_A_MASK
- RT3883_GPIO_MODE_LNA_A_SHIFT
- RT3883_GPIO_MODE_LNA_G
- RT3883_GPIO_MODE_LNA_G_GPIO
- RT3883_GPIO_MODE_LNA_G_MASK
- RT3883_GPIO_MODE_LNA_G_SHIFT
- RT3883_GPIO_MODE_MDIO
- RT3883_GPIO_MODE_PCI
- RT3883_GPIO_MODE_PCI_MASK
- RT3883_GPIO_MODE_PCI_SHIFT
- RT3883_GPIO_MODE_PCM_GPIO
- RT3883_GPIO_MODE_PCM_I2S
- RT3883_GPIO_MODE_PCM_UARTF
- RT3883_GPIO_MODE_SPI
- RT3883_GPIO_MODE_UART0
- RT3883_GPIO_MODE_UART0_MASK
- RT3883_GPIO_MODE_UART0_SHIFT
- RT3883_GPIO_MODE_UART1
- RT3883_GPIO_MODE_UARTF
- RT3883_GPIO_PCI_AD0
- RT3883_GPIO_PCI_AD31
- RT3883_GPIO_SPI_CLK
- RT3883_GPIO_SPI_CS0
- RT3883_GPIO_SPI_MISO
- RT3883_GPIO_SPI_MOSI
- RT3883_GPIO_UART1_RXD
- RT3883_GPIO_UART1_TXD
- RT3883_I2C_BASE
- RT3883_I2C_SIZE
- RT3883_I2S_BASE
- RT3883_I2S_SIZE
- RT3883_INTC_BASE
- RT3883_INTC_INT_DMA
- RT3883_INTC_INT_I2S
- RT3883_INTC_INT_IA
- RT3883_INTC_INT_NAND
- RT3883_INTC_INT_PCM
- RT3883_INTC_INT_PERFC
- RT3883_INTC_INT_PIO
- RT3883_INTC_INT_SYSCTL
- RT3883_INTC_INT_TIMER0
- RT3883_INTC_INT_TIMER1
- RT3883_INTC_INT_UART0
- RT3883_INTC_INT_UART1
- RT3883_INTC_INT_UDEV
- RT3883_INTC_INT_UHST
- RT3883_INTC_SIZE
- RT3883_MEMC_BASE
- RT3883_MEMC_SIZE
- RT3883_MEMORY_BASE
- RT3883_MEMORY_SIZE
- RT3883_MEM_SIZE_MAX
- RT3883_MEM_SIZE_MIN
- RT3883_NANDC_BASE
- RT3883_NANDC_SIZE
- RT3883_OHCI_BASE
- RT3883_P2P_BR_DEVNUM
- RT3883_PCICFG_P2P_BR_DEVNUM_M
- RT3883_PCICFG_P2P_BR_DEVNUM_S
- RT3883_PCICFG_PCIRST
- RT3883_PCIMEM_BASE
- RT3883_PCI_BASE
- RT3883_PCI_IRQ_COUNT
- RT3883_PCI_MODE_BOTH
- RT3883_PCI_MODE_NONE
- RT3883_PCI_MODE_PCI
- RT3883_PCI_MODE_PCIE
- RT3883_PCI_REG_ARBCTL
- RT3883_PCI_REG_BAR0SETUP
- RT3883_PCI_REG_BASE
- RT3883_PCI_REG_CFGADDR
- RT3883_PCI_REG_CFGDATA
- RT3883_PCI_REG_CLASS
- RT3883_PCI_REG_ID
- RT3883_PCI_REG_IMBASEBAR0
- RT3883_PCI_REG_IOBASE
- RT3883_PCI_REG_MEMBASE
- RT3883_PCI_REG_PCICFG
- RT3883_PCI_REG_PCIENA
- RT3883_PCI_REG_PCIINT
- RT3883_PCI_REG_PCIRAW
- RT3883_PCI_REG_STATUS
- RT3883_PCI_REG_SUBID
- RT3883_PCI_SIZE
- RT3883_PCM_BASE
- RT3883_PCM_SIZE
- RT3883_PIO_BASE
- RT3883_PIO_SIZE
- RT3883_REVID_ECO_ID_MASK
- RT3883_REVID_VER_ID_MASK
- RT3883_REVID_VER_ID_SHIFT
- RT3883_ROM_BASE
- RT3883_ROM_SIZE
- RT3883_RSTCTRL_DMA
- RT3883_RSTCTRL_FE
- RT3883_RSTCTRL_FLASH
- RT3883_RSTCTRL_I2C
- RT3883_RSTCTRL_I2S
- RT3883_RSTCTRL_INTC
- RT3883_RSTCTRL_MC
- RT3883_RSTCTRL_NAND
- RT3883_RSTCTRL_PCI
- RT3883_RSTCTRL_PCIE
- RT3883_RSTCTRL_PCIE_PCI_PDM
- RT3883_RSTCTRL_PCM
- RT3883_RSTCTRL_PIO
- RT3883_RSTCTRL_SPI
- RT3883_RSTCTRL_SYS
- RT3883_RSTCTRL_TIMER
- RT3883_RSTCTRL_UART
- RT3883_RSTCTRL_UART1
- RT3883_RSTCTRL_UDEV
- RT3883_RSTCTRL_UHST
- RT3883_RSTCTRL_WLAN
- RT3883_SDRAM_BASE
- RT3883_SOC
- RT3883_SPI_BASE
- RT3883_SPI_SIZE
- RT3883_SRAM_BASE
- RT3883_SRAM_SIZE
- RT3883_SYSCFG0_CPUCLK_250
- RT3883_SYSCFG0_CPUCLK_384
- RT3883_SYSCFG0_CPUCLK_480
- RT3883_SYSCFG0_CPUCLK_500
- RT3883_SYSCFG0_CPUCLK_MASK
- RT3883_SYSCFG0_CPUCLK_SHIFT
- RT3883_SYSCFG0_DRAM_TYPE_DDR2
- RT3883_SYSCFG1_GPIO2_AS_WDT_OUT
- RT3883_SYSCFG1_PCIE_RC_MODE
- RT3883_SYSCFG1_PCI_66M_MODE
- RT3883_SYSCFG1_PCI_HOST_MODE
- RT3883_SYSCFG1_USB0_HOST_MODE
- RT3883_SYSC_BASE
- RT3883_SYSC_REG_CHIPID0_3
- RT3883_SYSC_REG_CHIPID4_7
- RT3883_SYSC_REG_CLKCFG0
- RT3883_SYSC_REG_CLKCFG1
- RT3883_SYSC_REG_GPIO_MODE
- RT3883_SYSC_REG_PCIE_CLK_GEN0
- RT3883_SYSC_REG_PCIE_CLK_GEN1
- RT3883_SYSC_REG_PCIE_CLK_GEN2
- RT3883_SYSC_REG_PMU
- RT3883_SYSC_REG_PMU1
- RT3883_SYSC_REG_REVID
- RT3883_SYSC_REG_RSTCTRL
- RT3883_SYSC_REG_RSTSTAT
- RT3883_SYSC_REG_SYSCFG0
- RT3883_SYSC_REG_SYSCFG1
- RT3883_SYSC_REG_USB_PS
- RT3883_SYSC_SIZE
- RT3883_TIMER_BASE
- RT3883_TIMER_SIZE
- RT3883_UART0_BASE
- RT3883_UART0_SIZE
- RT3883_UART1_BASE
- RT3883_UART1_SIZE
- RT3883_USBDEV_BASE
- RT3883_USBDEV_SIZE
- RT3883_USBHOST_BASE
- RT3883_USBHOST_SIZE
- RT3883_WLAN_BASE
- RT3883_WLAN_SIZE
- RT3d
- RT4
- RT5033_AICR_100_MODE
- RT5033_AICR_1500_MODE
- RT5033_AICR_2000_MODE
- RT5033_AICR_500_MODE
- RT5033_AICR_700_MODE
- RT5033_AICR_900_MODE
- RT5033_AICR_MODE_MASK
- RT5033_BOOST_MODE
- RT5033_BUCK
- RT5033_BUCK_CTRL_MASK
- RT5033_CFO_ENABLE
- RT5033_CHARGER_CONST_VOLTAGE_LIMIT_MAX
- RT5033_CHARGER_CONST_VOLTAGE_LIMIT_MIN
- RT5033_CHARGER_CONST_VOLTAGE_STEP_NUM
- RT5033_CHARGER_EOC_MAX
- RT5033_CHARGER_EOC_MIN
- RT5033_CHARGER_EOC_REF
- RT5033_CHARGER_EOC_STEP_NUM1
- RT5033_CHARGER_EOC_STEP_NUM2
- RT5033_CHARGER_FAST_CURRENT_MAX
- RT5033_CHARGER_FAST_CURRENT_MIN
- RT5033_CHARGER_FAST_CURRENT_STEP_NUM
- RT5033_CHARGER_HZ_DISABLE
- RT5033_CHARGER_HZ_ENABLE
- RT5033_CHARGER_MODE
- RT5033_CHARGER_MODEL
- RT5033_CHARGER_PRE_CURRENT_LIMIT_MAX
- RT5033_CHARGER_PRE_CURRENT_LIMIT_MIN
- RT5033_CHARGER_PRE_CURRENT_STEP_NUM
- RT5033_CHARGER_PRE_THRESHOLD_LIMIT_MAX
- RT5033_CHARGER_PRE_THRESHOLD_LIMIT_MIN
- RT5033_CHARGER_PRE_THRESHOLD_STEP_NUM
- RT5033_CHARGER_UUG_ENABLE
- RT5033_CHGCTRL1_IAICR_MASK
- RT5033_CHGCTRL1_MODE_MASK
- RT5033_CHGCTRL2_CV_MASK
- RT5033_CHGCTRL3_CFO_EN_MASK
- RT5033_CHGCTRL3_TIMER_EN_MASK
- RT5033_CHGCTRL3_TIMER_MASK
- RT5033_CHGCTRL4_EOC_MASK
- RT5033_CHGCTRL4_IPREC_MASK
- RT5033_CHGCTRL5_ICHG_MASK
- RT5033_CHGCTRL5_ICHG_SHIFT
- RT5033_CHGCTRL5_VPREC_MASK
- RT5033_CHG_MAX_CURRENT
- RT5033_CHG_STAT_CHARGING
- RT5033_CHG_STAT_DISCHARGING
- RT5033_CHG_STAT_FULL
- RT5033_CHG_STAT_MASK
- RT5033_CHG_STAT_NOT_CHARGING
- RT5033_CHG_STAT_TYPE_FAST
- RT5033_CHG_STAT_TYPE_MASK
- RT5033_CHG_STAT_TYPE_PRE
- RT5033_CTRL_BUCKOMS_MASK
- RT5033_CTRL_EN_BUCK_MASK
- RT5033_CTRL_EN_LDO_MASK
- RT5033_CTRL_EN_SAFE_LDO_MASK
- RT5033_CTRL_FCCM_BUCK_MASK
- RT5033_CTRL_LDOOMS_MASK
- RT5033_CTRL_LDO_SLEEP_MASK
- RT5033_CTRL_SLDOOMS_MASK
- RT5033_FAST_CHARGE_TIMER12
- RT5033_FAST_CHARGE_TIMER14
- RT5033_FAST_CHARGE_TIMER16
- RT5033_FAST_CHARGE_TIMER4
- RT5033_FAST_CHARGE_TIMER6
- RT5033_FAST_CHARGE_TIMER8
- RT5033_FAST_CHARGE_TIMER9
- RT5033_FUEL_BAT_PRESENT
- RT5033_FUEL_MFA_H
- RT5033_FUEL_MFA_L
- RT5033_FUEL_REG_AVG_VOLT_H
- RT5033_FUEL_REG_AVG_VOLT_L
- RT5033_FUEL_REG_CONFIG_H
- RT5033_FUEL_REG_CONFIG_L
- RT5033_FUEL_REG_CRATE
- RT5033_FUEL_REG_CTRL_H
- RT5033_FUEL_REG_CTRL_L
- RT5033_FUEL_REG_DEVICE_ID
- RT5033_FUEL_REG_END
- RT5033_FUEL_REG_IRQ_CTRL
- RT5033_FUEL_REG_IRQ_FLAG
- RT5033_FUEL_REG_OCV_H
- RT5033_FUEL_REG_OCV_L
- RT5033_FUEL_REG_SOC_H
- RT5033_FUEL_REG_SOC_L
- RT5033_FUEL_REG_VBAT_H
- RT5033_FUEL_REG_VBAT_L
- RT5033_FUEL_SMIN
- RT5033_FUEL_VGCOMP1
- RT5033_FUEL_VGCOMP2
- RT5033_FUEL_VGCOMP3
- RT5033_FUEL_VGCOMP4
- RT5033_FUEL_VMIN
- RT5033_INT_TIMER_ENABLE
- RT5033_LDO
- RT5033_LDO_CTRL_MASK
- RT5033_MANUFACTURER
- RT5033_PMIC_IRQ_BUCKLV
- RT5033_PMIC_IRQ_BUCKOCP
- RT5033_PMIC_IRQ_LDOLV
- RT5033_PMIC_IRQ_OT
- RT5033_PMIC_IRQ_SAFELDOLV
- RT5033_PMIC_IRQ_VDDA_UV
- RT5033_REGULATOR_BUCK_VOLTAGE_MAX
- RT5033_REGULATOR_BUCK_VOLTAGE_MIN
- RT5033_REGULATOR_BUCK_VOLTAGE_STEP
- RT5033_REGULATOR_BUCK_VOLTAGE_STEP_NUM
- RT5033_REGULATOR_LDO_VOLTAGE_MAX
- RT5033_REGULATOR_LDO_VOLTAGE_MIN
- RT5033_REGULATOR_LDO_VOLTAGE_STEP
- RT5033_REGULATOR_LDO_VOLTAGE_STEP_NUM
- RT5033_REGULATOR_NUM
- RT5033_REGULATOR_SAFE_LDO_VOLTAGE
- RT5033_REG_BUCK_CTRL
- RT5033_REG_CHG_CTRL1
- RT5033_REG_CHG_CTRL2
- RT5033_REG_CHG_CTRL3
- RT5033_REG_CHG_CTRL4
- RT5033_REG_CHG_CTRL5
- RT5033_REG_CHG_IRQ1
- RT5033_REG_CHG_IRQ1_CTRL
- RT5033_REG_CHG_IRQ2
- RT5033_REG_CHG_IRQ2_CTRL
- RT5033_REG_CHG_IRQ3
- RT5033_REG_CHG_IRQ3_CTRL
- RT5033_REG_CHG_RESET
- RT5033_REG_CHG_STAT
- RT5033_REG_CTRL
- RT5033_REG_DEVICE_ID
- RT5033_REG_END
- RT5033_REG_FLED_CTRL1
- RT5033_REG_FLED_CTRL2
- RT5033_REG_FLED_CTRL3
- RT5033_REG_FLED_CTRL4
- RT5033_REG_FLED_CTRL5
- RT5033_REG_FLED_FUNCTION1
- RT5033_REG_FLED_FUNCTION2
- RT5033_REG_FLED_STROBE_CTRL1
- RT5033_REG_FLED_STROBE_CTRL2
- RT5033_REG_LDO_CTRL
- RT5033_REG_LED_IRQ_CTRL
- RT5033_REG_LED_IRQ_STAT
- RT5033_REG_MANUAL_RESET_CTRL
- RT5033_REG_OFF_EVENT
- RT5033_REG_PMIC_IRQ_CTRL
- RT5033_REG_PMIC_IRQ_STAT
- RT5033_REG_RT_CTRL0
- RT5033_REG_RT_CTRL1
- RT5033_REG_SHDN_CTRL
- RT5033_RT_CTRL1_UUG_MASK
- RT5033_RT_HZ_MASK
- RT5033_SAFE_LDO
- RT5033_TE_ENABLE
- RT5033_TE_ENABLE_MASK
- RT5350
- RT5350_CHIP_NAME0
- RT5350_CHIP_NAME1
- RT5350_GPIO_MODE_PHY_LED
- RT5350_GPIO_MODE_SPI_CS1
- RT5350_SYSCFG0_CPUCLK_300
- RT5350_SYSCFG0_CPUCLK_320
- RT5350_SYSCFG0_CPUCLK_360
- RT5350_SYSCFG0_CPUCLK_MASK
- RT5350_SYSCFG0_CPUCLK_SHIFT
- RT5350_SYSCFG0_DRAM_SIZE_16M
- RT5350_SYSCFG0_DRAM_SIZE_2M
- RT5350_SYSCFG0_DRAM_SIZE_32M
- RT5350_SYSCFG0_DRAM_SIZE_64M
- RT5350_SYSCFG0_DRAM_SIZE_8M
- RT5350_SYSCFG0_DRAM_SIZE_MASK
- RT5350_SYSCFG0_DRAM_SIZE_SHIFT
- RT5390
- RT5392
- RT5514_AD0_DMIC_INPUT_SEL
- RT5514_AD0_DMIC_INPUT_SEL_SFT
- RT5514_AD1_DMIC_INPUT_SEL
- RT5514_AD1_DMIC_INPUT_SEL_SFT
- RT5514_AD_AD_MIX
- RT5514_AD_AD_MIX_BIT
- RT5514_AD_AD_MUTE
- RT5514_AD_AD_MUTE_BIT
- RT5514_AD_DMIC_MIX
- RT5514_AD_DMIC_MIX_BIT
- RT5514_AD_GAIN_MASK
- RT5514_AD_GAIN_SFT
- RT5514_AIF1_BCLK_FREQ
- RT5514_AIF1_SYSCLK_FREQ
- RT5514_ANA_CTRL_ADC12
- RT5514_ANA_CTRL_ADC21
- RT5514_ANA_CTRL_ADC22
- RT5514_ANA_CTRL_ADC23
- RT5514_ANA_CTRL_ADCFED
- RT5514_ANA_CTRL_INBUF
- RT5514_ANA_CTRL_LDO10
- RT5514_ANA_CTRL_LDO18_16
- RT5514_ANA_CTRL_MICBST
- RT5514_ANA_CTRL_PLL1_1
- RT5514_ANA_CTRL_PLL1_2
- RT5514_ANA_CTRL_PLL3
- RT5514_ANA_CTRL_VREF
- RT5514_ASRC_IN_CTRL1
- RT5514_BUFFER_VOICE_BASE
- RT5514_BUFFER_VOICE_LIMIT
- RT5514_BUFFER_VOICE_WP
- RT5514_CH_LEN_RX_16
- RT5514_CH_LEN_RX_20
- RT5514_CH_LEN_RX_24
- RT5514_CH_LEN_RX_32
- RT5514_CH_LEN_RX_MASK
- RT5514_CH_LEN_RX_SFT
- RT5514_CH_LEN_TX_16
- RT5514_CH_LEN_TX_20
- RT5514_CH_LEN_TX_24
- RT5514_CH_LEN_TX_32
- RT5514_CH_LEN_TX_MASK
- RT5514_CH_LEN_TX_SFT
- RT5514_CLK_AD0_ASRC_EN
- RT5514_CLK_AD0_ASRC_EN_BIT
- RT5514_CLK_AD0_EN
- RT5514_CLK_AD0_EN_BIT
- RT5514_CLK_AD1_ASRC_EN
- RT5514_CLK_AD1_ASRC_EN_BIT
- RT5514_CLK_AD1_EN
- RT5514_CLK_AD1_EN_BIT
- RT5514_CLK_AD_ANA1_EN
- RT5514_CLK_AD_ANA1_EN_BIT
- RT5514_CLK_AD_ANA1_SEL_MASK
- RT5514_CLK_AD_ANA1_SEL_SFT
- RT5514_CLK_CTRL1
- RT5514_CLK_CTRL2
- RT5514_CLK_DMIC_OUT_SEL_MASK
- RT5514_CLK_DMIC_OUT_SEL_SFT
- RT5514_CLK_SYS_DIV_OUT_MASK
- RT5514_CLK_SYS_DIV_OUT_SFT
- RT5514_CLK_SYS_PRE_SEL_MASK
- RT5514_CLK_SYS_PRE_SEL_MCLK
- RT5514_CLK_SYS_PRE_SEL_PLL
- RT5514_CLK_SYS_PRE_SEL_SFT
- RT5514_DELAY_BUF_CTRL1
- RT5514_DELAY_BUF_CTRL3
- RT5514_DEVICE_ID
- RT5514_DEV_NAME
- RT5514_DIG_IO_CTRL
- RT5514_DIG_SOURCE_CTRL
- RT5514_DMIC_DATA_CTRL
- RT5514_DMIC_LP_CTRL
- RT5514_DOWNFILTER0_CTRL1
- RT5514_DOWNFILTER0_CTRL2
- RT5514_DOWNFILTER0_CTRL3
- RT5514_DOWNFILTER1_CTRL1
- RT5514_DOWNFILTER1_CTRL2
- RT5514_DOWNFILTER1_CTRL3
- RT5514_DOWNFILTER2_CTRL1
- RT5514_DSP_CTRL1
- RT5514_DSP_CTRL3
- RT5514_DSP_CTRL4
- RT5514_DSP_MAPPING
- RT5514_EN_LDO_PLL1
- RT5514_EN_LDO_PLL1_BIT
- RT5514_EXT_VAD_CTRL
- RT5514_FIRMWARE1
- RT5514_FIRMWARE2
- RT5514_FORMATS
- RT5514_I2S_BP_INV
- RT5514_I2S_BP_MASK
- RT5514_I2S_BP_NOR
- RT5514_I2S_BP_SFT
- RT5514_I2S_CTRL1
- RT5514_I2S_CTRL2
- RT5514_I2S_DF_I2S
- RT5514_I2S_DF_LEFT
- RT5514_I2S_DF_MASK
- RT5514_I2S_DF_PCM_A
- RT5514_I2S_DF_PCM_B
- RT5514_I2S_DF_SFT
- RT5514_I2S_DL_16
- RT5514_I2S_DL_20
- RT5514_I2S_DL_24
- RT5514_I2S_DL_8
- RT5514_I2S_DL_MASK
- RT5514_I2S_DL_SFT
- RT5514_I2S_LR_INV
- RT5514_I2S_LR_MASK
- RT5514_I2S_LR_NOR
- RT5514_I2S_LR_SFT
- RT5514_IRQ_CTRL
- RT5514_IRQ_STATUS_BIT
- RT5514_MISC_CTRL_DSP
- RT5514_PAD_CTRL1
- RT5514_PLL1_S_BCLK
- RT5514_PLL1_S_MCLK
- RT5514_PLL3_CALIB_CTRL1
- RT5514_PLL3_CALIB_CTRL4
- RT5514_PLL3_CALIB_CTRL5
- RT5514_PLL3_CALIB_CTRL6
- RT5514_PLL_1_SEL_MASK
- RT5514_PLL_1_SEL_MCLK
- RT5514_PLL_1_SEL_SCLK
- RT5514_PLL_1_SEL_SFT
- RT5514_PLL_INP_MAX
- RT5514_PLL_INP_MIN
- RT5514_PLL_K_BP
- RT5514_PLL_K_BP_SFT
- RT5514_PLL_K_MASK
- RT5514_PLL_K_MAX
- RT5514_PLL_K_SFT
- RT5514_PLL_M_BP
- RT5514_PLL_M_BP_SFT
- RT5514_PLL_M_MASK
- RT5514_PLL_M_MAX
- RT5514_PLL_M_SFT
- RT5514_PLL_N_MASK
- RT5514_PLL_N_MAX
- RT5514_PLL_N_SFT
- RT5514_PLL_SOURCE_CTRL
- RT5514_POW2_BSTL
- RT5514_POW2_BSTL_BIT
- RT5514_POW2_BSTR
- RT5514_POW2_BSTR_BIT
- RT5514_POWL_LDO16
- RT5514_POWL_LDO16_BIT
- RT5514_POWR_LDO16
- RT5514_POWR_LDO16_BIT
- RT5514_POW_ADC1_L
- RT5514_POW_ADC1_L_BIT
- RT5514_POW_ADC1_R
- RT5514_POW_ADC1_R_BIT
- RT5514_POW_ADC2
- RT5514_POW_ADC2_BIT
- RT5514_POW_ADCFEDL
- RT5514_POW_ADCFEDL_BIT
- RT5514_POW_ADCFEDR
- RT5514_POW_ADCFEDR_BIT
- RT5514_POW_BG_LDO18_IN
- RT5514_POW_BG_LDO18_IN_BIT
- RT5514_POW_BG_LDO21
- RT5514_POW_BG_LDO21_BIT
- RT5514_POW_BG_MBIAS
- RT5514_POW_BG_MBIAS_BIT
- RT5514_POW_BSTL
- RT5514_POW_BSTL_BIT
- RT5514_POW_BSTR
- RT5514_POW_BSTR_BIT
- RT5514_POW_INPUT_BUF
- RT5514_POW_INPUT_BUF_BIT
- RT5514_POW_LDO18_ADC
- RT5514_POW_LDO18_ADC_BIT
- RT5514_POW_LDO18_IN
- RT5514_POW_LDO18_IN_BIT
- RT5514_POW_LDO21
- RT5514_POW_LDO21_BIT
- RT5514_POW_MBIAS
- RT5514_POW_MBIAS_BIT
- RT5514_POW_PLL1
- RT5514_POW_PLL1_BIT
- RT5514_POW_PLL1_LDO
- RT5514_POW_PLL1_LDO_BIT
- RT5514_POW_VREF1
- RT5514_POW_VREF1_BIT
- RT5514_POW_VREF2
- RT5514_POW_VREF2_BIT
- RT5514_PWR_ANA1
- RT5514_PWR_ANA2
- RT5514_RESET
- RT5514_SCLK_S_MCLK
- RT5514_SCLK_S_PLL1
- RT5514_SEL_ADC_OSR_MASK
- RT5514_SEL_ADC_OSR_SFT
- RT5514_SEL_BSTL_MASK
- RT5514_SEL_BSTL_SFT
- RT5514_SEL_BSTR_MASK
- RT5514_SEL_BSTR_SFT
- RT5514_SPI_BUF_LEN
- RT5514_SPI_CMD_16_READ
- RT5514_SPI_CMD_16_WRITE
- RT5514_SPI_CMD_32_READ
- RT5514_SPI_CMD_32_WRITE
- RT5514_SPI_CMD_BURST_READ
- RT5514_SPI_CMD_BURST_WRITE
- RT5514_SRC_CTRL
- RT5514_STEREO_RATES
- RT5514_TDMSLOT_SEL_RX_4CH
- RT5514_TDMSLOT_SEL_RX_6CH
- RT5514_TDMSLOT_SEL_RX_8CH
- RT5514_TDMSLOT_SEL_RX_MASK
- RT5514_TDMSLOT_SEL_RX_SFT
- RT5514_TDMSLOT_SEL_TX_4CH
- RT5514_TDMSLOT_SEL_TX_6CH
- RT5514_TDMSLOT_SEL_TX_8CH
- RT5514_TDMSLOT_SEL_TX_MASK
- RT5514_TDMSLOT_SEL_TX_SFT
- RT5514_TDM_DOCKING_MODE
- RT5514_TDM_DOCKING_MODE_SFT
- RT5514_TDM_DOCKING_START_MASK
- RT5514_TDM_DOCKING_START_SFT
- RT5514_TDM_DOCKING_START_SLOT0
- RT5514_TDM_DOCKING_START_SLOT4
- RT5514_TDM_DOCKING_VALID_CH2
- RT5514_TDM_DOCKING_VALID_CH4
- RT5514_TDM_DOCKING_VALID_CH_MASK
- RT5514_TDM_DOCKING_VALID_CH_SFT
- RT5514_TDM_MODE
- RT5514_TDM_MODE2
- RT5514_TDM_MODE2_SFT
- RT5514_TDM_MODE_SFT
- RT5514_VAD_CTRL6
- RT5514_VENDOR_ID1
- RT5514_VENDOR_ID2
- RT5592
- RT5616_2ND_HPF_DIS
- RT5616_2ND_HPF_EN
- RT5616_2ND_HPF_MASK
- RT5616_2ND_HPF_SFT
- RT5616_3D_1F_MIX_MASK
- RT5616_3D_1F_MIX_SFT
- RT5616_3D_BT_DIS
- RT5616_3D_BT_EN
- RT5616_3D_BT_MASK
- RT5616_3D_BT_SFT
- RT5616_3D_CF_DIS
- RT5616_3D_CF_EN
- RT5616_3D_CF_MASK
- RT5616_3D_CF_SFT
- RT5616_3D_HP_DIS
- RT5616_3D_HP_EN
- RT5616_3D_HP_MASK
- RT5616_3D_HP_M_FRO
- RT5616_3D_HP_M_MASK
- RT5616_3D_HP_M_SFT
- RT5616_3D_HP_M_SUR
- RT5616_3D_HP_SFT
- RT5616_3D_SPK
- RT5616_3D_SPK_CG_MASK
- RT5616_3D_SPK_CG_SFT
- RT5616_3D_SPK_DIS
- RT5616_3D_SPK_EN
- RT5616_3D_SPK_MASK
- RT5616_3D_SPK_M_MASK
- RT5616_3D_SPK_M_SFT
- RT5616_3D_SPK_SFT
- RT5616_3D_SPK_SG_MASK
- RT5616_3D_SPK_SG_SFT
- RT5616_ADC_BST_VOL
- RT5616_ADC_COMP_MASK
- RT5616_ADC_COMP_SFT
- RT5616_ADC_DIG_VOL
- RT5616_ADC_L_BST_MASK
- RT5616_ADC_L_BST_SFT
- RT5616_ADC_L_VOL_MASK
- RT5616_ADC_L_VOL_SFT
- RT5616_ADC_M_ASRC
- RT5616_ADC_M_MASK
- RT5616_ADC_M_NOR
- RT5616_ADC_M_SFT
- RT5616_ADC_OSR_128
- RT5616_ADC_OSR_128_3
- RT5616_ADC_OSR_32
- RT5616_ADC_OSR_64
- RT5616_ADC_OSR_MASK
- RT5616_ADC_OSR_SFT
- RT5616_ADC_R_BST_MASK
- RT5616_ADC_R_BST_SFT
- RT5616_ADC_R_VOL_MASK
- RT5616_ADC_R_VOL_SFT
- RT5616_ADDA_CLK1
- RT5616_ADDA_CLK2
- RT5616_ADHPF_EN
- RT5616_ADHPF_EN_SFT
- RT5616_ADJ_HPF_CTRL1
- RT5616_ADJ_HPF_CTRL2
- RT5616_AD_DA_MIXER
- RT5616_AIF1
- RT5616_AIFS
- RT5616_AMP_DET_EN
- RT5616_AMP_DET_EN_SFT
- RT5616_ASRC2_REF_LRCK1
- RT5616_ASRC2_REF_LRCK2
- RT5616_ASRC2_REF_MASK
- RT5616_ASRC2_REF_SFT
- RT5616_ASRC_LP_F_M
- RT5616_ASRC_LP_F_NOR
- RT5616_ASRC_LP_F_SB
- RT5616_ASRC_LP_F_SFT
- RT5616_A_JD_CTL1
- RT5616_A_JD_CTL2
- RT5616_BASE_BACK
- RT5616_BB_CT_A
- RT5616_BB_CT_B
- RT5616_BB_CT_C
- RT5616_BB_CT_D
- RT5616_BB_CT_MASK
- RT5616_BB_CT_SFT
- RT5616_BB_DIS
- RT5616_BB_EN
- RT5616_BB_MASK
- RT5616_BB_SFT
- RT5616_BIAS_CUR1
- RT5616_BIAS_CUR3
- RT5616_BPS_DIS
- RT5616_BPS_EN
- RT5616_BPS_MASK
- RT5616_BPS_SFT
- RT5616_BREEZE
- RT5616_BST_MASK1
- RT5616_BST_MASK2
- RT5616_BST_SFT1
- RT5616_BST_SFT2
- RT5616_CAL_DIS
- RT5616_CAL_EN
- RT5616_CAL_MASK
- RT5616_CAL_M_CAL
- RT5616_CAL_M_DEP
- RT5616_CAL_M_MASK
- RT5616_CAL_M_SFT
- RT5616_CAL_P_CAL
- RT5616_CAL_P_DAC_CAL
- RT5616_CAL_P_MASK
- RT5616_CAL_P_NONE
- RT5616_CAL_P_SFT
- RT5616_CAL_SFT
- RT5616_CAL_TEST_DIS
- RT5616_CAL_TEST_EN
- RT5616_CAL_TEST_MASK
- RT5616_CAL_TEST_SFT
- RT5616_CHARGE_PUMP
- RT5616_CHOP_DAC_ADC
- RT5616_CLK_DET_EN
- RT5616_CLK_DET_EN_SFT
- RT5616_CLSD_INT_REG1
- RT5616_CP_FQ1_MASK
- RT5616_CP_FQ1_SFT
- RT5616_CP_FQ2_MASK
- RT5616_CP_FQ2_SFT
- RT5616_CP_FQ3_MASK
- RT5616_CP_FQ3_SFT
- RT5616_CP_FQ_12_KHZ
- RT5616_CP_FQ_192_KHZ
- RT5616_CP_FQ_1_5_KHZ
- RT5616_CP_FQ_24_KHZ
- RT5616_CP_FQ_3_KHZ
- RT5616_CP_FQ_48_KHZ
- RT5616_CP_FQ_6_KHZ
- RT5616_CP_FQ_96_KHZ
- RT5616_CP_SYS_MASK
- RT5616_CP_SYS_SFT
- RT5616_DAC1_DIG_VOL
- RT5616_DAC_DD_L1_VOL_SFT
- RT5616_DAC_L1_STO_L_VOL_MASK
- RT5616_DAC_L1_STO_L_VOL_SFT
- RT5616_DAC_L1_STO_R_VOL_MASK
- RT5616_DAC_L1_STO_R_VOL_SFT
- RT5616_DAC_L1_VOL_MASK
- RT5616_DAC_L1_VOL_SFT
- RT5616_DAC_L2_DAC_L_VOL_MASK
- RT5616_DAC_L2_DAC_L_VOL_SFT
- RT5616_DAC_L2_SEL_BASS
- RT5616_DAC_L2_SEL_IF2
- RT5616_DAC_L2_SEL_IF3
- RT5616_DAC_L2_SEL_MASK
- RT5616_DAC_L2_SEL_SFT
- RT5616_DAC_L2_SEL_TXDC
- RT5616_DAC_L2_VOL_MASK
- RT5616_DAC_L2_VOL_SFT
- RT5616_DAC_OSR_128
- RT5616_DAC_OSR_128_3
- RT5616_DAC_OSR_32
- RT5616_DAC_OSR_64
- RT5616_DAC_OSR_MASK
- RT5616_DAC_OSR_SFT
- RT5616_DAC_R1_STO_L_VOL_MASK
- RT5616_DAC_R1_STO_L_VOL_SFT
- RT5616_DAC_R1_STO_R_VOL_MASK
- RT5616_DAC_R1_STO_R_VOL_SFT
- RT5616_DAC_R1_VOL_MASK
- RT5616_DAC_R1_VOL_SFT
- RT5616_DAC_R2_DAC_R_VOL_MASK
- RT5616_DAC_R2_DAC_R_VOL_SFT
- RT5616_DAC_R2_SEL_IF2
- RT5616_DAC_R2_SEL_IF3
- RT5616_DAC_R2_SEL_MASK
- RT5616_DAC_R2_SEL_SFT
- RT5616_DAC_R2_SEL_TXDC
- RT5616_DAC_R2_VOL_MASK
- RT5616_DAC_R2_VOL_SFT
- RT5616_DAHPF_EN
- RT5616_DAHPF_EN_SFT
- RT5616_DC_CAL_DIS
- RT5616_DC_CAL_EN
- RT5616_DC_CAL_MASK
- RT5616_DC_CAL_M_CAL
- RT5616_DC_CAL_M_MASK
- RT5616_DC_CAL_M_NOR
- RT5616_DC_CAL_M_SFT
- RT5616_DC_CAL_SFT
- RT5616_DEPOP_AUTO
- RT5616_DEPOP_M1
- RT5616_DEPOP_M2
- RT5616_DEPOP_M3
- RT5616_DEPOP_MAN
- RT5616_DEPOP_MASK
- RT5616_DEPOP_SFT
- RT5616_DEVICE_ID
- RT5616_DIG_DP_DIS
- RT5616_DIG_DP_EN
- RT5616_DIG_DP_MASK
- RT5616_DIG_DP_SFT
- RT5616_DIP_SPK_INF
- RT5616_DMIC_1_M_ASYN
- RT5616_DMIC_1_M_MASK
- RT5616_DMIC_1_M_NOR
- RT5616_DMIC_1_M_SFT
- RT5616_DP_ATT_MASK
- RT5616_DP_ATT_SFT
- RT5616_DP_SPK_DIS
- RT5616_DP_SPK_EN
- RT5616_DP_SPK_MASK
- RT5616_DP_SPK_SFT
- RT5616_DP_TH_MASK
- RT5616_DP_TH_SFT
- RT5616_DRC_AGC_1
- RT5616_DRC_AGC_2
- RT5616_DRC_AGC_3
- RT5616_DRC_AGC_AR_MASK
- RT5616_DRC_AGC_AR_SFT
- RT5616_DRC_AGC_CPR_1_1
- RT5616_DRC_AGC_CPR_1_2
- RT5616_DRC_AGC_CPR_1_3
- RT5616_DRC_AGC_CPR_1_4
- RT5616_DRC_AGC_CPR_MASK
- RT5616_DRC_AGC_CPR_SFT
- RT5616_DRC_AGC_CP_DIS
- RT5616_DRC_AGC_CP_EN
- RT5616_DRC_AGC_CP_MASK
- RT5616_DRC_AGC_CP_SFT
- RT5616_DRC_AGC_DIS
- RT5616_DRC_AGC_EN
- RT5616_DRC_AGC_MASK
- RT5616_DRC_AGC_NGB_MASK
- RT5616_DRC_AGC_NGB_SFT
- RT5616_DRC_AGC_NGH_DIS
- RT5616_DRC_AGC_NGH_EN
- RT5616_DRC_AGC_NGH_MASK
- RT5616_DRC_AGC_NGH_SFT
- RT5616_DRC_AGC_NGT_MASK
- RT5616_DRC_AGC_NGT_SFT
- RT5616_DRC_AGC_NG_DIS
- RT5616_DRC_AGC_NG_EN
- RT5616_DRC_AGC_NG_MASK
- RT5616_DRC_AGC_NG_SFT
- RT5616_DRC_AGC_POB_MASK
- RT5616_DRC_AGC_POB_SFT
- RT5616_DRC_AGC_PRB_MASK
- RT5616_DRC_AGC_PRB_SFT
- RT5616_DRC_AGC_P_ADC
- RT5616_DRC_AGC_P_DAC
- RT5616_DRC_AGC_P_MASK
- RT5616_DRC_AGC_P_SFT
- RT5616_DRC_AGC_RC_MASK
- RT5616_DRC_AGC_RC_SFT
- RT5616_DRC_AGC_R_1764K
- RT5616_DRC_AGC_R_192K
- RT5616_DRC_AGC_R_441K
- RT5616_DRC_AGC_R_48K
- RT5616_DRC_AGC_R_882K
- RT5616_DRC_AGC_R_96K
- RT5616_DRC_AGC_R_MASK
- RT5616_DRC_AGC_R_SFT
- RT5616_DRC_AGC_SFT
- RT5616_DRC_AGC_TAR_MASK
- RT5616_DRC_AGC_TAR_SFT
- RT5616_DRC_AGC_UPD
- RT5616_DRC_AGC_UPD_BIT
- RT5616_DUMMY2
- RT5616_DUMMY3
- RT5616_D_GATE_EN
- RT5616_D_GATE_EN_SFT
- RT5616_D_MISC
- RT5616_EG_MP3_MASK
- RT5616_EG_MP3_SFT
- RT5616_EN_DFO
- RT5616_EQ_BPF1_DIS
- RT5616_EQ_BPF1_EN
- RT5616_EQ_BPF1_MASK
- RT5616_EQ_BPF1_SFT
- RT5616_EQ_BPF2_DIS
- RT5616_EQ_BPF2_EN
- RT5616_EQ_BPF2_MASK
- RT5616_EQ_BPF2_SFT
- RT5616_EQ_BPF3_DIS
- RT5616_EQ_BPF3_EN
- RT5616_EQ_BPF3_MASK
- RT5616_EQ_BPF3_SFT
- RT5616_EQ_BPF4_DIS
- RT5616_EQ_BPF4_EN
- RT5616_EQ_BPF4_MASK
- RT5616_EQ_BPF4_SFT
- RT5616_EQ_BW_BP1
- RT5616_EQ_BW_BP2
- RT5616_EQ_BW_BP3
- RT5616_EQ_BW_BP4
- RT5616_EQ_BW_HIP2
- RT5616_EQ_BW_LOP
- RT5616_EQ_CD_DIS
- RT5616_EQ_CD_EN
- RT5616_EQ_CD_F
- RT5616_EQ_CD_F_BIT
- RT5616_EQ_CD_MASK
- RT5616_EQ_CD_SFT
- RT5616_EQ_CTRL1
- RT5616_EQ_CTRL2
- RT5616_EQ_CTRL_MASK
- RT5616_EQ_DITH_LSB
- RT5616_EQ_DITH_LSB_1
- RT5616_EQ_DITH_LSB_2
- RT5616_EQ_DITH_MASK
- RT5616_EQ_DITH_NOR
- RT5616_EQ_DITH_SFT
- RT5616_EQ_FC_BP1
- RT5616_EQ_FC_BP2
- RT5616_EQ_FC_BP3
- RT5616_EQ_FC_BP4
- RT5616_EQ_FC_HIP1
- RT5616_EQ_FC_HIP2
- RT5616_EQ_GN_BP1
- RT5616_EQ_GN_BP2
- RT5616_EQ_GN_BP3
- RT5616_EQ_GN_BP4
- RT5616_EQ_GN_HIP1
- RT5616_EQ_GN_HIP2
- RT5616_EQ_GN_LOP
- RT5616_EQ_HPF1_DIS
- RT5616_EQ_HPF1_EN
- RT5616_EQ_HPF1_MASK
- RT5616_EQ_HPF1_M_1ST
- RT5616_EQ_HPF1_M_HI
- RT5616_EQ_HPF1_M_MASK
- RT5616_EQ_HPF1_M_SFT
- RT5616_EQ_HPF1_SFT
- RT5616_EQ_HPF2_DIS
- RT5616_EQ_HPF2_EN
- RT5616_EQ_HPF2_MASK
- RT5616_EQ_HPF2_SFT
- RT5616_EQ_LPF1_M_1ST
- RT5616_EQ_LPF1_M_LO
- RT5616_EQ_LPF1_M_MASK
- RT5616_EQ_LPF1_M_SFT
- RT5616_EQ_LPF_DIS
- RT5616_EQ_LPF_EN
- RT5616_EQ_LPF_MASK
- RT5616_EQ_LPF_SFT
- RT5616_EQ_PRE_VOL
- RT5616_EQ_PRE_VOL_MASK
- RT5616_EQ_PRE_VOL_SFT
- RT5616_EQ_PST_VOL
- RT5616_EQ_PST_VOL_MASK
- RT5616_EQ_PST_VOL_SFT
- RT5616_EQ_SRC_ADC
- RT5616_EQ_SRC_DAC
- RT5616_EQ_SRC_MASK
- RT5616_EQ_SRC_SFT
- RT5616_EQ_STA_BP1
- RT5616_EQ_STA_BP1_BIT
- RT5616_EQ_STA_BP2
- RT5616_EQ_STA_BP2_BIT
- RT5616_EQ_STA_BP3
- RT5616_EQ_STA_BP3_BIT
- RT5616_EQ_STA_BP4
- RT5616_EQ_STA_BP4_BIT
- RT5616_EQ_STA_HP1
- RT5616_EQ_STA_HP1_BIT
- RT5616_EQ_STA_HP2
- RT5616_EQ_STA_HP2_BIT
- RT5616_EQ_STA_LP
- RT5616_EQ_STA_LP_BIT
- RT5616_EQ_UPD
- RT5616_EQ_UPD_BIT
- RT5616_FAST_UPDN_DIS
- RT5616_FAST_UPDN_EN
- RT5616_FAST_UPDN_MASK
- RT5616_FAST_UPDN_SFT
- RT5616_FORMATS
- RT5616_FSI1_RATE_MASK
- RT5616_FSI1_RATE_SFT
- RT5616_FSI2_RATE_MASK
- RT5616_FSI2_RATE_SFT
- RT5616_FTK_PH_DET_DIV1
- RT5616_FTK_PH_DET_DIV2
- RT5616_FTK_PH_DET_DIV4
- RT5616_FTK_PH_DET_DIV8
- RT5616_FTK_PH_DET_MASK
- RT5616_FTK_PH_DET_SFT
- RT5616_GLB_CLK
- RT5616_GP1_DR_IN
- RT5616_GP1_DR_MASK
- RT5616_GP1_DR_OUT
- RT5616_GP1_DR_SFT
- RT5616_GP1_OUT_HI
- RT5616_GP1_OUT_LO
- RT5616_GP1_OUT_MASK
- RT5616_GP1_OUT_SFT
- RT5616_GP1_PIN_GPIO1
- RT5616_GP1_PIN_IRQ
- RT5616_GP1_PIN_MASK
- RT5616_GP1_PIN_SFT
- RT5616_GP1_P_INV
- RT5616_GP1_P_MASK
- RT5616_GP1_P_NOR
- RT5616_GP1_P_SFT
- RT5616_GP2_DR_IN
- RT5616_GP2_DR_MASK
- RT5616_GP2_DR_OUT
- RT5616_GP2_DR_SFT
- RT5616_GP2_OUT_HI
- RT5616_GP2_OUT_LO
- RT5616_GP2_OUT_MASK
- RT5616_GP2_OUT_SFT
- RT5616_GP2_PIN_DMIC1_SCL
- RT5616_GP2_PIN_GPIO2
- RT5616_GP2_PIN_MASK
- RT5616_GP2_PIN_SFT
- RT5616_GP2_P_INV
- RT5616_GP2_P_MASK
- RT5616_GP2_P_NOR
- RT5616_GP2_P_SFT
- RT5616_GP3_DR_IN
- RT5616_GP3_DR_MASK
- RT5616_GP3_DR_OUT
- RT5616_GP3_DR_SFT
- RT5616_GP3_OUT_HI
- RT5616_GP3_OUT_LO
- RT5616_GP3_OUT_MASK
- RT5616_GP3_OUT_SFT
- RT5616_GP3_P_INV
- RT5616_GP3_P_MASK
- RT5616_GP3_P_NOR
- RT5616_GP3_P_SFT
- RT5616_GP4_DR_IN
- RT5616_GP4_DR_MASK
- RT5616_GP4_DR_OUT
- RT5616_GP4_DR_SFT
- RT5616_GP4_OUT_HI
- RT5616_GP4_OUT_LO
- RT5616_GP4_OUT_MASK
- RT5616_GP4_OUT_SFT
- RT5616_GP4_P_INV
- RT5616_GP4_P_MASK
- RT5616_GP4_P_NOR
- RT5616_GP4_P_SFT
- RT5616_GP5_DR_IN
- RT5616_GP5_DR_MASK
- RT5616_GP5_DR_OUT
- RT5616_GP5_DR_SFT
- RT5616_GP5_OUT_HI
- RT5616_GP5_OUT_LO
- RT5616_GP5_OUT_MASK
- RT5616_GP5_OUT_SFT
- RT5616_GP5_PIN_GPIO5
- RT5616_GP5_PIN_IRQ
- RT5616_GP5_PIN_MASK
- RT5616_GP5_PIN_SFT
- RT5616_GP5_P_INV
- RT5616_GP5_P_MASK
- RT5616_GP5_P_NOR
- RT5616_GP5_P_SFT
- RT5616_GP6_DR_IN
- RT5616_GP6_DR_MASK
- RT5616_GP6_DR_OUT
- RT5616_GP6_DR_SFT
- RT5616_GP6_OUT_HI
- RT5616_GP6_OUT_LO
- RT5616_GP6_OUT_MASK
- RT5616_GP6_OUT_SFT
- RT5616_GP6_PIN_DMIC_SDA
- RT5616_GP6_PIN_GPIO6
- RT5616_GP6_PIN_MASK
- RT5616_GP6_PIN_SFT
- RT5616_GP6_P_INV
- RT5616_GP6_P_MASK
- RT5616_GP6_P_NOR
- RT5616_GP6_P_SFT
- RT5616_GP7_DR_IN
- RT5616_GP7_DR_MASK
- RT5616_GP7_DR_OUT
- RT5616_GP7_DR_SFT
- RT5616_GP7_OUT_HI
- RT5616_GP7_OUT_LO
- RT5616_GP7_OUT_MASK
- RT5616_GP7_OUT_SFT
- RT5616_GP7_PIN_GPIO7
- RT5616_GP7_PIN_IRQ
- RT5616_GP7_PIN_MASK
- RT5616_GP7_PIN_SFT
- RT5616_GP7_P_INV
- RT5616_GP7_P_MASK
- RT5616_GP7_P_NOR
- RT5616_GP7_P_SFT
- RT5616_GP8_DR_IN
- RT5616_GP8_DR_MASK
- RT5616_GP8_DR_OUT
- RT5616_GP8_DR_SFT
- RT5616_GP8_OUT_HI
- RT5616_GP8_OUT_LO
- RT5616_GP8_OUT_MASK
- RT5616_GP8_OUT_SFT
- RT5616_GP8_PIN_DMIC_SDA
- RT5616_GP8_PIN_GPIO8
- RT5616_GP8_PIN_MASK
- RT5616_GP8_PIN_SFT
- RT5616_GP8_P_INV
- RT5616_GP8_P_MASK
- RT5616_GP8_P_NOR
- RT5616_GP8_P_SFT
- RT5616_GPIO_CTRL1
- RT5616_GPIO_CTRL2
- RT5616_GPIO_CTRL3
- RT5616_GPIO_M_FLT
- RT5616_GPIO_M_MASK
- RT5616_GPIO_M_PH
- RT5616_GPIO_M_SFT
- RT5616_GPIO_PDM_SEL_GPIO
- RT5616_GPIO_PDM_SEL_MASK
- RT5616_GPIO_PDM_SEL_PDM
- RT5616_GPIO_PDM_SEL_SFT
- RT5616_G_ASRC_LP_MASK
- RT5616_G_ASRC_LP_SFT
- RT5616_G_BB_BST_MASK
- RT5616_G_BB_BST_SFT
- RT5616_G_BST1_OM_L_MASK
- RT5616_G_BST1_OM_L_SFT
- RT5616_G_BST1_OM_R_MASK
- RT5616_G_BST1_OM_R_SFT
- RT5616_G_BST1_RM_L_MASK
- RT5616_G_BST1_RM_L_SFT
- RT5616_G_BST1_RM_R_MASK
- RT5616_G_BST1_RM_R_SFT
- RT5616_G_BST2_OM_L_MASK
- RT5616_G_BST2_OM_L_SFT
- RT5616_G_BST2_OM_R_MASK
- RT5616_G_BST2_OM_R_SFT
- RT5616_G_BST2_RM_L_MASK
- RT5616_G_BST2_RM_L_SFT
- RT5616_G_BST2_RM_R_MASK
- RT5616_G_BST2_RM_R_SFT
- RT5616_G_BST3_RM_L_MASK
- RT5616_G_BST3_RM_L_SFT
- RT5616_G_BST3_RM_R_MASK
- RT5616_G_BST3_RM_R_SFT
- RT5616_G_DAC_L1_OM_L_MASK
- RT5616_G_DAC_L1_OM_L_SFT
- RT5616_G_DAC_L1_SM_L_MASK
- RT5616_G_DAC_L1_SM_L_SFT
- RT5616_G_DAC_L2_SM_L_MASK
- RT5616_G_DAC_L2_SM_L_SFT
- RT5616_G_DAC_R1_OM_R_MASK
- RT5616_G_DAC_R1_OM_R_SFT
- RT5616_G_DAC_R1_SM_R_MASK
- RT5616_G_DAC_R1_SM_R_SFT
- RT5616_G_DAC_R2_SM_R_MASK
- RT5616_G_DAC_R2_SM_R_SFT
- RT5616_G_HPOMIX_MASK
- RT5616_G_HPOMIX_SFT
- RT5616_G_IN1_L_OM_L_MASK
- RT5616_G_IN1_L_OM_L_SFT
- RT5616_G_IN1_R_OM_R_MASK
- RT5616_G_IN1_R_OM_R_SFT
- RT5616_G_IN1_R_RM_R_MASK
- RT5616_G_IN1_R_RM_R_SFT
- RT5616_G_IN2_L_OM_L_MASK
- RT5616_G_IN2_L_OM_L_SFT
- RT5616_G_IN2_R_OM_R_MASK
- RT5616_G_IN2_R_OM_R_SFT
- RT5616_G_IN2_R_RM_R_MASK
- RT5616_G_IN2_R_RM_R_SFT
- RT5616_G_IN_L1_RM_L_SFT
- RT5616_G_IN_L2_RM_L_SFT
- RT5616_G_IN_L_SM_L_MASK
- RT5616_G_IN_L_SM_L_SFT
- RT5616_G_IN_R_SM_R_MASK
- RT5616_G_IN_R_SM_R_SFT
- RT5616_G_LN_L1_RM_L_MASK
- RT5616_G_LN_L2_RM_L_MASK
- RT5616_G_LOUTMIX_MASK
- RT5616_G_LOUTMIX_SFT
- RT5616_G_MONOMIX_MASK
- RT5616_G_MONOMIX_SFT
- RT5616_G_OM_L_RM_L_MASK
- RT5616_G_OM_L_RM_L_SFT
- RT5616_G_OM_L_SM_L_MASK
- RT5616_G_OM_L_SM_L_SFT
- RT5616_G_OM_R_RM_R_MASK
- RT5616_G_OM_R_RM_R_SFT
- RT5616_G_OM_R_SM_R_MASK
- RT5616_G_OM_R_SM_R_SFT
- RT5616_G_RM_L_OM_L_MASK
- RT5616_G_RM_L_OM_L_SFT
- RT5616_G_RM_L_SM_L_MASK
- RT5616_G_RM_L_SM_L_SFT
- RT5616_G_RM_R_OM_R_MASK
- RT5616_G_RM_R_OM_R_SFT
- RT5616_G_RM_R_SM_R_MASK
- RT5616_G_RM_R_SM_R_SFT
- RT5616_HG_MP3_MASK
- RT5616_HG_MP3_SFT
- RT5616_HPD_PS_DIS
- RT5616_HPD_PS_EN
- RT5616_HPD_PS_MASK
- RT5616_HPD_PS_SFT
- RT5616_HPD_RCV_MASK
- RT5616_HPD_RCV_SFT
- RT5616_HPF_CF_L_MASK
- RT5616_HPF_CF_L_NUM_MASK
- RT5616_HPF_CF_L_NUM_SFT
- RT5616_HPF_CF_L_SFT
- RT5616_HPF_CF_R_MASK
- RT5616_HPF_CF_R_NUM_MASK
- RT5616_HPF_CF_R_NUM_SFT
- RT5616_HPF_CF_R_SFT
- RT5616_HPF_FC_MASK
- RT5616_HPF_FC_SFT
- RT5616_HPO_MIXER
- RT5616_HP_CALIB2
- RT5616_HP_CALIB_AMP_DET
- RT5616_HP_CB_MASK
- RT5616_HP_CB_PD
- RT5616_HP_CB_PU
- RT5616_HP_CB_SFT
- RT5616_HP_CD_PD_DIS
- RT5616_HP_CD_PD_EN
- RT5616_HP_CD_PD_MASK
- RT5616_HP_CD_PD_SFT
- RT5616_HP_CO_DIS
- RT5616_HP_CO_EN
- RT5616_HP_CO_MASK
- RT5616_HP_CO_SFT
- RT5616_HP_CP_MASK
- RT5616_HP_CP_PD
- RT5616_HP_CP_PU
- RT5616_HP_CP_SFT
- RT5616_HP_DCC_INT1
- RT5616_HP_DP_MASK
- RT5616_HP_DP_PD
- RT5616_HP_DP_PU
- RT5616_HP_DP_SFT
- RT5616_HP_L_SMT_DIS
- RT5616_HP_L_SMT_EN
- RT5616_HP_L_SMT_MASK
- RT5616_HP_L_SMT_SFT
- RT5616_HP_OC_TH_105
- RT5616_HP_OC_TH_120
- RT5616_HP_OC_TH_135
- RT5616_HP_OC_TH_90
- RT5616_HP_OC_TH_MASK
- RT5616_HP_OC_TH_SFT
- RT5616_HP_OVCD
- RT5616_HP_OVCD_DIS
- RT5616_HP_OVCD_EN
- RT5616_HP_OVCD_MASK
- RT5616_HP_OVCD_SFT
- RT5616_HP_R_SMT_DIS
- RT5616_HP_R_SMT_EN
- RT5616_HP_R_SMT_MASK
- RT5616_HP_R_SMT_SFT
- RT5616_HP_SG_DIS
- RT5616_HP_SG_EN
- RT5616_HP_SG_MASK
- RT5616_HP_SG_SFT
- RT5616_HP_SV_DIS
- RT5616_HP_SV_EN
- RT5616_HP_SV_MASK
- RT5616_HP_SV_SFT
- RT5616_HP_VOL
- RT5616_I2S1_PD_MASK
- RT5616_I2S1_PD_SFT
- RT5616_I2S1_RATE_MASK
- RT5616_I2S1_RATE_SFT
- RT5616_I2S1_R_D_DIS
- RT5616_I2S1_R_D_EN
- RT5616_I2S1_R_D_MASK
- RT5616_I2S1_R_D_SFT
- RT5616_I2S1_SDP
- RT5616_I2S2_MS_SP_50
- RT5616_I2S2_MS_SP_64
- RT5616_I2S2_MS_SP_MASK
- RT5616_I2S2_MS_SP_SEL
- RT5616_I2S2_PD_MASK
- RT5616_I2S2_PD_SFT
- RT5616_I2S2_RATE_MASK
- RT5616_I2S2_RATE_SFT
- RT5616_I2S2_R_D_DIS
- RT5616_I2S2_R_D_EN
- RT5616_I2S2_R_D_MASK
- RT5616_I2S2_R_D_SFT
- RT5616_I2S2_SEL_GPIO
- RT5616_I2S2_SEL_I2S
- RT5616_I2S2_SEL_MASK
- RT5616_I2S2_SEL_SFT
- RT5616_I2S_BCLK_MS2_MASK
- RT5616_I2S_BP_INV
- RT5616_I2S_BP_MASK
- RT5616_I2S_BP_NOR
- RT5616_I2S_BP_SFT
- RT5616_I2S_DF_I2S
- RT5616_I2S_DF_LEFT
- RT5616_I2S_DF_MASK
- RT5616_I2S_DF_PCM_A
- RT5616_I2S_DF_PCM_B
- RT5616_I2S_DF_SFT
- RT5616_I2S_DL_16
- RT5616_I2S_DL_20
- RT5616_I2S_DL_24
- RT5616_I2S_DL_8
- RT5616_I2S_DL_MASK
- RT5616_I2S_DL_SFT
- RT5616_I2S_I_CP_A_LAW
- RT5616_I2S_I_CP_MASK
- RT5616_I2S_I_CP_OFF
- RT5616_I2S_I_CP_SFT
- RT5616_I2S_I_CP_U_LAW
- RT5616_I2S_MS_M
- RT5616_I2S_MS_MASK
- RT5616_I2S_MS_S
- RT5616_I2S_MS_SFT
- RT5616_I2S_O_CP_A_LAW
- RT5616_I2S_O_CP_MASK
- RT5616_I2S_O_CP_OFF
- RT5616_I2S_O_CP_SFT
- RT5616_I2S_O_CP_U_LAW
- RT5616_I2S_PD1_1
- RT5616_I2S_PD1_12
- RT5616_I2S_PD1_16
- RT5616_I2S_PD1_2
- RT5616_I2S_PD1_3
- RT5616_I2S_PD1_4
- RT5616_I2S_PD1_6
- RT5616_I2S_PD1_8
- RT5616_I2S_PD1_MASK
- RT5616_I2S_PD1_SFT
- RT5616_IB_HP_125IL
- RT5616_IB_HP_1IL
- RT5616_IB_HP_25IL
- RT5616_IB_HP_5IL
- RT5616_IB_HP_MASK
- RT5616_IB_HP_SFT
- RT5616_IF2_ADC_L_SEL_MASK
- RT5616_IF2_ADC_L_SEL_PASS
- RT5616_IF2_ADC_L_SEL_SFT
- RT5616_IF2_ADC_L_SEL_TXDP
- RT5616_IF2_ADC_R_SEL_MASK
- RT5616_IF2_ADC_R_SEL_PASS
- RT5616_IF2_ADC_R_SEL_SFT
- RT5616_IF2_ADC_R_SEL_TXDP
- RT5616_IN1_IN2
- RT5616_INIT_REG_LEN
- RT5616_INL1_INR1_VOL
- RT5616_INL_VOL_MASK
- RT5616_INL_VOL_SFT
- RT5616_INR_SEL_IN4N
- RT5616_INR_SEL_MASK
- RT5616_INR_SEL_MONON
- RT5616_INR_SEL_SFT
- RT5616_INR_VOL_MASK
- RT5616_INR_VOL_SFT
- RT5616_INT_IRQ_ST
- RT5616_IN_DF1
- RT5616_IN_DF2
- RT5616_IN_SFT1
- RT5616_IN_SFT2
- RT5616_IRQ_CTRL1
- RT5616_IRQ_CTRL2
- RT5616_IRQ_JD_BP
- RT5616_IRQ_JD_MASK
- RT5616_IRQ_JD_NOR
- RT5616_IRQ_JD_SFT
- RT5616_IRQ_MB1_OC_BP
- RT5616_IRQ_MB1_OC_MASK
- RT5616_IRQ_MB1_OC_NOR
- RT5616_IRQ_MB1_OC_SFT
- RT5616_JD1_1_EN_STKY
- RT5616_JD1_1_EN_STKY_SFT
- RT5616_JD1_1_INV
- RT5616_JD1_1_INV_SFT
- RT5616_JD1_1_IRQ_EN
- RT5616_JD1_1_IRQ_EN_SFT
- RT5616_JD1_2_EN_STKY
- RT5616_JD1_2_EN_STKY_SFT
- RT5616_JD1_2_INV
- RT5616_JD1_2_INV_SFT
- RT5616_JD1_2_IRQ_EN
- RT5616_JD1_2_IRQ_EN_SFT
- RT5616_JD2_CMP_MASK
- RT5616_JD2_CMP_SFT
- RT5616_JD2_EN_STKY
- RT5616_JD2_EN_STKY_SFT
- RT5616_JD2_INV
- RT5616_JD2_INV_SFT
- RT5616_JD2_IRQ_EN
- RT5616_JD2_IRQ_EN_SFT
- RT5616_JD3_CMP_MASK
- RT5616_JD3_CMP_SFT
- RT5616_JD3_EN_STKY
- RT5616_JD3_EN_STKY_SFT
- RT5616_JD3_INV
- RT5616_JD3_INV_SFT
- RT5616_JD3_IRQ_EN
- RT5616_JD3_IRQ_EN_SFT
- RT5616_JD_CTRL1
- RT5616_JD_CTRL2
- RT5616_JD_DIS
- RT5616_JD_GPIO1
- RT5616_JD_GPIO2
- RT5616_JD_GPIO3
- RT5616_JD_GPIO4
- RT5616_JD_GPIO5
- RT5616_JD_GPIO6
- RT5616_JD_HP_DIS
- RT5616_JD_HP_EN
- RT5616_JD_HP_MASK
- RT5616_JD_HP_SFT
- RT5616_JD_HP_TRG_HI
- RT5616_JD_HP_TRG_LO
- RT5616_JD_HP_TRG_MASK
- RT5616_JD_HP_TRG_SFT
- RT5616_JD_LO_DIS
- RT5616_JD_LO_EN
- RT5616_JD_LO_MASK
- RT5616_JD_LO_SFT
- RT5616_JD_LO_TRG_HI
- RT5616_JD_LO_TRG_LO
- RT5616_JD_LO_TRG_MASK
- RT5616_JD_LO_TRG_SFT
- RT5616_JD_MASK
- RT5616_JD_MODE_SEL_M0
- RT5616_JD_MODE_SEL_M1
- RT5616_JD_MODE_SEL_M2
- RT5616_JD_MODE_SEL_MASK
- RT5616_JD_MODE_SEL_SFT
- RT5616_JD_M_CMP
- RT5616_JD_M_CMP_SFT
- RT5616_JD_M_MODE_SEL_M0
- RT5616_JD_M_MODE_SEL_M1
- RT5616_JD_M_MODE_SEL_M2
- RT5616_JD_M_MODE_SEL_MASK
- RT5616_JD_M_MODE_SEL_SFT
- RT5616_JD_M_PD
- RT5616_JD_M_PD_SFT
- RT5616_JD_M_PU
- RT5616_JD_M_PU_SFT
- RT5616_JD_PD
- RT5616_JD_PD_SFT
- RT5616_JD_PU
- RT5616_JD_PU_SFT
- RT5616_JD_P_INV
- RT5616_JD_P_MASK
- RT5616_JD_P_NOR
- RT5616_JD_P_SFT
- RT5616_JD_SFT
- RT5616_JD_SPL_DIS
- RT5616_JD_SPL_EN
- RT5616_JD_SPL_MASK
- RT5616_JD_SPL_SFT
- RT5616_JD_SPL_TRG_HI
- RT5616_JD_SPL_TRG_LO
- RT5616_JD_SPL_TRG_MASK
- RT5616_JD_SPL_TRG_SFT
- RT5616_JD_SPR_DIS
- RT5616_JD_SPR_EN
- RT5616_JD_SPR_MASK
- RT5616_JD_SPR_SFT
- RT5616_JD_SPR_TRG_HI
- RT5616_JD_SPR_TRG_LO
- RT5616_JD_SPR_TRG_MASK
- RT5616_JD_SPR_TRG_SFT
- RT5616_JD_STKY_DIS
- RT5616_JD_STKY_EN
- RT5616_JD_STKY_MASK
- RT5616_JD_STKY_SFT
- RT5616_JD_TRG_SEL_GPIO
- RT5616_JD_TRG_SEL_JD1_1
- RT5616_JD_TRG_SEL_JD1_2
- RT5616_JD_TRG_SEL_JD2
- RT5616_JD_TRG_SEL_JD3
- RT5616_JD_TRG_SEL_MASK
- RT5616_JD_TRG_SEL_SFT
- RT5616_LOUT_CTRL1
- RT5616_LOUT_CTRL2
- RT5616_LOUT_MIXER
- RT5616_L_MUTE
- RT5616_L_MUTE_SFT
- RT5616_L_VOL_MASK
- RT5616_L_VOL_SFT
- RT5616_MAMP_INT_REG2
- RT5616_MB1_OC_CLR
- RT5616_MB1_OC_CLR_SFT
- RT5616_MB1_OC_P_INV
- RT5616_MB1_OC_P_MASK
- RT5616_MB1_OC_P_NOR
- RT5616_MB1_OC_P_SFT
- RT5616_MB1_OC_STKY_DIS
- RT5616_MB1_OC_STKY_EN
- RT5616_MB1_OC_STKY_MASK
- RT5616_MB1_OC_STKY_SFT
- RT5616_MB2_OC_P_MASK
- RT5616_MIC1_BS_75AV
- RT5616_MIC1_BS_9AV
- RT5616_MIC1_BS_MASK
- RT5616_MIC1_BS_SFT
- RT5616_MIC1_CLK_DIS
- RT5616_MIC1_CLK_EN
- RT5616_MIC1_CLK_MASK
- RT5616_MIC1_CLK_SFT
- RT5616_MIC1_OVCD_DIS
- RT5616_MIC1_OVCD_EN
- RT5616_MIC1_OVCD_MASK
- RT5616_MIC1_OVCD_SFT
- RT5616_MIC1_OVTH_1500UA
- RT5616_MIC1_OVTH_2000UA
- RT5616_MIC1_OVTH_600UA
- RT5616_MIC1_OVTH_MASK
- RT5616_MIC1_OVTH_SFT
- RT5616_MICBIAS
- RT5616_MONO_ADC_L_VOL_MASK
- RT5616_MONO_ADC_L_VOL_SFT
- RT5616_MONO_ADC_R_VOL_MASK
- RT5616_MONO_ADC_R_VOL_SFT
- RT5616_MP3_HLP_DIS
- RT5616_MP3_HLP_EN
- RT5616_MP3_HLP_MASK
- RT5616_MP3_HLP_SFT
- RT5616_MP3_PLUS1
- RT5616_MP3_PLUS2
- RT5616_MP3_WT_1_2
- RT5616_MP3_WT_1_4
- RT5616_MP3_WT_MASK
- RT5616_MP3_WT_SFT
- RT5616_MRES_15MO
- RT5616_MRES_25MO
- RT5616_MRES_35MO
- RT5616_MRES_45MO
- RT5616_MRES_MASK
- RT5616_MRES_SFT
- RT5616_MT_DIS
- RT5616_MT_EN
- RT5616_MT_MASK
- RT5616_MT_SFT
- RT5616_M_3D_D2H_MASK
- RT5616_M_3D_D2H_SFT
- RT5616_M_3D_D2R_MASK
- RT5616_M_3D_D2R_SFT
- RT5616_M_3D_HRTF_MASK
- RT5616_M_3D_HRTF_SFT
- RT5616_M_3D_REVB_MASK
- RT5616_M_3D_REVB_SFT
- RT5616_M_ADCMIX_L
- RT5616_M_ADCMIX_L_SFT
- RT5616_M_ADCMIX_R
- RT5616_M_ADCMIX_R_SFT
- RT5616_M_BB_HPF_L_MASK
- RT5616_M_BB_HPF_L_SFT
- RT5616_M_BB_HPF_R_MASK
- RT5616_M_BB_HPF_R_SFT
- RT5616_M_BB_L_MASK
- RT5616_M_BB_L_SFT
- RT5616_M_BB_R_MASK
- RT5616_M_BB_R_SFT
- RT5616_M_BST1_MM
- RT5616_M_BST1_MM_SFT
- RT5616_M_BST1_OM_L
- RT5616_M_BST1_OM_L_SFT
- RT5616_M_BST1_OM_R
- RT5616_M_BST1_OM_R_SFT
- RT5616_M_BST1_RM_L
- RT5616_M_BST1_RM_L_SFT
- RT5616_M_BST1_RM_R
- RT5616_M_BST1_RM_R_SFT
- RT5616_M_BST1_SPM_L
- RT5616_M_BST1_SPM_L_SFT
- RT5616_M_BST1_SPM_R
- RT5616_M_BST1_SPM_R_SFT
- RT5616_M_BST2_OM_L
- RT5616_M_BST2_OM_L_SFT
- RT5616_M_BST2_OM_R
- RT5616_M_BST2_OM_R_SFT
- RT5616_M_BST2_RM_L
- RT5616_M_BST2_RM_L_SFT
- RT5616_M_BST2_RM_R
- RT5616_M_BST2_RM_R_SFT
- RT5616_M_BST3_RM_L
- RT5616_M_BST3_RM_L_SFT
- RT5616_M_BST3_RM_R
- RT5616_M_BST3_RM_R_SFT
- RT5616_M_DAC1_HM
- RT5616_M_DAC1_HM_SFT
- RT5616_M_DAC_L1_LM
- RT5616_M_DAC_L1_LM_SFT
- RT5616_M_DAC_L1_MIXL
- RT5616_M_DAC_L1_MIXL_SFT
- RT5616_M_DAC_L1_MIXR
- RT5616_M_DAC_L1_MIXR_SFT
- RT5616_M_DAC_L1_OM_L
- RT5616_M_DAC_L1_OM_L_SFT
- RT5616_M_DAC_L1_SM_L
- RT5616_M_DAC_L1_SM_L_SFT
- RT5616_M_DAC_L1_SPM_L
- RT5616_M_DAC_L1_SPM_L_SFT
- RT5616_M_DAC_L2_DAC_L
- RT5616_M_DAC_L2_DAC_L_SFT
- RT5616_M_DAC_L2_MM
- RT5616_M_DAC_L2_MM_SFT
- RT5616_M_DAC_L2_SM_L
- RT5616_M_DAC_L2_SM_L_SFT
- RT5616_M_DAC_R1_LM
- RT5616_M_DAC_R1_LM_SFT
- RT5616_M_DAC_R1_MIXL
- RT5616_M_DAC_R1_MIXL_SFT
- RT5616_M_DAC_R1_MIXR
- RT5616_M_DAC_R1_MIXR_SFT
- RT5616_M_DAC_R1_OM_R
- RT5616_M_DAC_R1_OM_R_SFT
- RT5616_M_DAC_R1_SM_R
- RT5616_M_DAC_R1_SM_R_SFT
- RT5616_M_DAC_R1_SPM_L
- RT5616_M_DAC_R1_SPM_L_SFT
- RT5616_M_DAC_R1_SPM_R
- RT5616_M_DAC_R1_SPM_R_SFT
- RT5616_M_DAC_R2_DAC_R
- RT5616_M_DAC_R2_DAC_R_SFT
- RT5616_M_DAC_R2_MM
- RT5616_M_DAC_R2_MM_SFT
- RT5616_M_DAC_R2_SM_R
- RT5616_M_DAC_R2_SM_R_SFT
- RT5616_M_HPVOL_HM
- RT5616_M_HPVOL_HM_SFT
- RT5616_M_IF1_DAC_L
- RT5616_M_IF1_DAC_L_SFT
- RT5616_M_IF1_DAC_R
- RT5616_M_IF1_DAC_R_SFT
- RT5616_M_IN1_L_OM_L
- RT5616_M_IN1_L_OM_L_SFT
- RT5616_M_IN1_L_RM_L
- RT5616_M_IN1_L_RM_L_SFT
- RT5616_M_IN1_R_OM_R
- RT5616_M_IN1_R_OM_R_SFT
- RT5616_M_IN1_R_RM_R
- RT5616_M_IN1_R_RM_R_SFT
- RT5616_M_IN2_L_OM_L
- RT5616_M_IN2_L_OM_L_SFT
- RT5616_M_IN2_L_RM_L
- RT5616_M_IN2_L_RM_L_SFT
- RT5616_M_IN2_R_OM_R
- RT5616_M_IN2_R_OM_R_SFT
- RT5616_M_IN2_R_RM_R
- RT5616_M_IN2_R_RM_R_SFT
- RT5616_M_IN_L_SM_L
- RT5616_M_IN_L_SM_L_SFT
- RT5616_M_IN_R_SM_R
- RT5616_M_IN_R_SM_R_SFT
- RT5616_M_MONO_ADC_L
- RT5616_M_MONO_ADC_L_SFT
- RT5616_M_MONO_ADC_R
- RT5616_M_MONO_ADC_R_SFT
- RT5616_M_MP3_DIS
- RT5616_M_MP3_EN
- RT5616_M_MP3_L_MASK
- RT5616_M_MP3_L_SFT
- RT5616_M_MP3_MASK
- RT5616_M_MP3_ORG_L_MASK
- RT5616_M_MP3_ORG_L_SFT
- RT5616_M_MP3_ORG_R_MASK
- RT5616_M_MP3_ORG_R_SFT
- RT5616_M_MP3_R_MASK
- RT5616_M_MP3_R_SFT
- RT5616_M_MP3_SFT
- RT5616_M_OM_L_RM_L
- RT5616_M_OM_L_RM_L_SFT
- RT5616_M_OM_L_SM_L
- RT5616_M_OM_L_SM_L_SFT
- RT5616_M_OM_R_RM_R
- RT5616_M_OM_R_RM_R_SFT
- RT5616_M_OM_R_SM_R
- RT5616_M_OM_R_SM_R_SFT
- RT5616_M_OV_L_LM
- RT5616_M_OV_L_LM_SFT
- RT5616_M_OV_L_MM
- RT5616_M_OV_L_MM_SFT
- RT5616_M_OV_R_LM
- RT5616_M_OV_R_LM_SFT
- RT5616_M_OV_R_MM
- RT5616_M_OV_R_MM_SFT
- RT5616_M_RM_L_OM_L
- RT5616_M_RM_L_OM_L_SFT
- RT5616_M_RM_L_SM_L
- RT5616_M_RM_L_SM_L_SFT
- RT5616_M_RM_R_OM_R
- RT5616_M_RM_R_OM_R_SFT
- RT5616_M_RM_R_SM_R
- RT5616_M_RM_R_SM_R_SFT
- RT5616_M_STO1_ADC_L1
- RT5616_M_STO1_ADC_L1_SFT
- RT5616_M_STO1_ADC_R1
- RT5616_M_STO1_ADC_R1_SFT
- RT5616_M_STO_DD_L1
- RT5616_M_STO_DD_L1_SFT
- RT5616_M_STO_DD_L2
- RT5616_M_STO_DD_L2_R
- RT5616_M_STO_DD_L2_R_SFT
- RT5616_M_STO_DD_L2_SFT
- RT5616_M_STO_DD_R1
- RT5616_M_STO_DD_R1_SFT
- RT5616_M_STO_DD_R2
- RT5616_M_STO_DD_R2_L
- RT5616_M_STO_DD_R2_L_SFT
- RT5616_M_STO_DD_R2_SFT
- RT5616_M_STO_L_DAC_L
- RT5616_M_STO_L_DAC_L_SFT
- RT5616_M_STO_R_DAC_R
- RT5616_M_STO_R_DAC_R_SFT
- RT5616_M_SV_L_SPM_L
- RT5616_M_SV_L_SPM_L_SFT
- RT5616_M_SV_R_SPM_L
- RT5616_M_SV_R_SPM_L_SFT
- RT5616_M_SV_R_SPM_R
- RT5616_M_SV_R_SPM_R_SFT
- RT5616_M_TDM2_L
- RT5616_M_TDM2_L_SFT
- RT5616_M_TDM2_R
- RT5616_M_TDM2_R_SFT
- RT5616_M_TDM4_L
- RT5616_M_TDM4_L_SFT
- RT5616_M_TDM4_R
- RT5616_M_TDM4_R_SFT
- RT5616_M_ZCD_MASK
- RT5616_M_ZCD_OM_L
- RT5616_M_ZCD_OM_R
- RT5616_M_ZCD_RM_L
- RT5616_M_ZCD_RM_R
- RT5616_M_ZCD_SFT
- RT5616_NO_WIND
- RT5616_OG_MP3_MASK
- RT5616_OG_MP3_SFT
- RT5616_OSW_L_DIS
- RT5616_OSW_L_EN
- RT5616_OSW_L_MASK
- RT5616_OSW_L_SFT
- RT5616_OSW_R_DIS
- RT5616_OSW_R_EN
- RT5616_OSW_R_MASK
- RT5616_OSW_R_SFT
- RT5616_OUT_L1_MIXER
- RT5616_OUT_L2_MIXER
- RT5616_OUT_L3_MIXER
- RT5616_OUT_R1_MIXER
- RT5616_OUT_R2_MIXER
- RT5616_OUT_R3_MIXER
- RT5616_OUT_SV_DIS
- RT5616_OUT_SV_EN
- RT5616_OUT_SV_MASK
- RT5616_OUT_SV_SFT
- RT5616_PGM_REG_ARR1
- RT5616_PGM_REG_ARR2
- RT5616_PGM_REG_ARR3
- RT5616_PGM_REG_ARR4
- RT5616_PGM_REG_ARR5
- RT5616_PLL1_PD_1
- RT5616_PLL1_PD_2
- RT5616_PLL1_PD_MASK
- RT5616_PLL1_PD_SFT
- RT5616_PLL1_SRC_BCLK1
- RT5616_PLL1_SRC_BCLK2
- RT5616_PLL1_SRC_MASK
- RT5616_PLL1_SRC_MCLK
- RT5616_PLL1_SRC_SFT
- RT5616_PLL1_S_BCLK1
- RT5616_PLL1_S_BCLK2
- RT5616_PLL1_S_MCLK
- RT5616_PLL_CTRL1
- RT5616_PLL_CTRL2
- RT5616_PLL_INP_MAX
- RT5616_PLL_INP_MIN
- RT5616_PLL_K_MASK
- RT5616_PLL_K_MAX
- RT5616_PLL_K_SFT
- RT5616_PLL_M_BP
- RT5616_PLL_M_BP_SFT
- RT5616_PLL_M_MASK
- RT5616_PLL_M_MAX
- RT5616_PLL_M_SFT
- RT5616_PLL_N_MASK
- RT5616_PLL_N_MAX
- RT5616_PLL_N_SFT
- RT5616_PM_HP_HV
- RT5616_PM_HP_LV
- RT5616_PM_HP_MASK
- RT5616_PM_HP_MV
- RT5616_PM_HP_SFT
- RT5616_PRE_SCLK_1024
- RT5616_PRE_SCLK_2048
- RT5616_PRE_SCLK_512
- RT5616_PRE_SCLK_MASK
- RT5616_PRE_SCLK_SFT
- RT5616_PRIV_DATA
- RT5616_PRIV_INDEX
- RT5616_PR_BASE
- RT5616_PR_RANGE_BASE
- RT5616_PR_SPACING
- RT5616_PV_DET_SPK_G
- RT5616_PWM_JD2_BIT
- RT5616_PWM_JD3_BIT
- RT5616_PWM_JD_M_BIT
- RT5616_PWR_ADC_L
- RT5616_PWR_ADC_L_BIT
- RT5616_PWR_ADC_R
- RT5616_PWR_ADC_R_BIT
- RT5616_PWR_ADC_STO1_F
- RT5616_PWR_ADC_STO1_F_BIT
- RT5616_PWR_ANLG1
- RT5616_PWR_ANLG2
- RT5616_PWR_BG
- RT5616_PWR_BG_BIT
- RT5616_PWR_BST1
- RT5616_PWR_BST1_BIT
- RT5616_PWR_BST1_OP2
- RT5616_PWR_BST1_OP2_BIT
- RT5616_PWR_BST2
- RT5616_PWR_BST2_BIT
- RT5616_PWR_BST2_OP2
- RT5616_PWR_BST2_OP2_BIT
- RT5616_PWR_BST3_OP2
- RT5616_PWR_BST3_OP2_BIT
- RT5616_PWR_CLK12M_MASK
- RT5616_PWR_CLK12M_PD
- RT5616_PWR_CLK12M_PU
- RT5616_PWR_CLK12M_SFT
- RT5616_PWR_DAC_L1
- RT5616_PWR_DAC_L1_BIT
- RT5616_PWR_DAC_R1
- RT5616_PWR_DAC_R1_BIT
- RT5616_PWR_DAC_STO1_F
- RT5616_PWR_DAC_STO1_F_BIT
- RT5616_PWR_DIG1
- RT5616_PWR_DIG2
- RT5616_PWR_FV1
- RT5616_PWR_FV1_BIT
- RT5616_PWR_FV2
- RT5616_PWR_FV2_BIT
- RT5616_PWR_HA
- RT5616_PWR_HA_BIT
- RT5616_PWR_HP_L
- RT5616_PWR_HP_L_BIT
- RT5616_PWR_HP_R
- RT5616_PWR_HP_R_BIT
- RT5616_PWR_HV_L
- RT5616_PWR_HV_L_BIT
- RT5616_PWR_HV_R
- RT5616_PWR_HV_R_BIT
- RT5616_PWR_I2S1
- RT5616_PWR_I2S1_BIT
- RT5616_PWR_I2S2
- RT5616_PWR_I2S2_BIT
- RT5616_PWR_IN1_L
- RT5616_PWR_IN1_L_BIT
- RT5616_PWR_IN1_R
- RT5616_PWR_IN1_R_BIT
- RT5616_PWR_IN2_L
- RT5616_PWR_IN2_L_BIT
- RT5616_PWR_IN2_R
- RT5616_PWR_IN2_R_BIT
- RT5616_PWR_JD2
- RT5616_PWR_JD3
- RT5616_PWR_JD_M
- RT5616_PWR_LDO
- RT5616_PWR_LDO_BIT
- RT5616_PWR_LDO_DVO_1_0V
- RT5616_PWR_LDO_DVO_1_1V
- RT5616_PWR_LDO_DVO_1_2V
- RT5616_PWR_LDO_DVO_1_3V
- RT5616_PWR_LDO_DVO_MASK
- RT5616_PWR_LM
- RT5616_PWR_LM_BIT
- RT5616_PWR_MB
- RT5616_PWR_MB1
- RT5616_PWR_MB1_BIT
- RT5616_PWR_MB_BIT
- RT5616_PWR_MB_MASK
- RT5616_PWR_MB_PD
- RT5616_PWR_MB_PU
- RT5616_PWR_MB_SFT
- RT5616_PWR_MIXER
- RT5616_PWR_OM_L
- RT5616_PWR_OM_L_BIT
- RT5616_PWR_OM_R
- RT5616_PWR_OM_R_BIT
- RT5616_PWR_OV_L
- RT5616_PWR_OV_L_BIT
- RT5616_PWR_OV_R
- RT5616_PWR_OV_R_BIT
- RT5616_PWR_PLL
- RT5616_PWR_PLL_BIT
- RT5616_PWR_RM_L
- RT5616_PWR_RM_L_BIT
- RT5616_PWR_RM_R
- RT5616_PWR_RM_R_BIT
- RT5616_PWR_VOL
- RT5616_PWR_VREF1
- RT5616_PWR_VREF1_BIT
- RT5616_PWR_VREF2
- RT5616_PWR_VREF2_BIT
- RT5616_RAMP_DIS
- RT5616_RAMP_EN
- RT5616_RAMP_MASK
- RT5616_RAMP_SFT
- RT5616_REC_L1_MIXER
- RT5616_REC_L2_MIXER
- RT5616_REC_R1_MIXER
- RT5616_REC_R2_MIXER
- RT5616_RESET
- RT5616_RSTN_DIS
- RT5616_RSTN_EN
- RT5616_RSTN_MASK
- RT5616_RSTN_SFT
- RT5616_RSTP_DIS
- RT5616_RSTP_EN
- RT5616_RSTP_MASK
- RT5616_RSTP_SFT
- RT5616_RXDC_SEL_L2R
- RT5616_RXDC_SEL_MASK
- RT5616_RXDC_SEL_NOR
- RT5616_RXDC_SEL_R2L
- RT5616_RXDC_SEL_SFT
- RT5616_RXDC_SEL_SWAP
- RT5616_RXDP_SEL_L2R
- RT5616_RXDP_SEL_MASK
- RT5616_RXDP_SEL_NOR
- RT5616_RXDP_SEL_R2L
- RT5616_RXDP_SEL_SFT
- RT5616_RXDP_SEL_SWAP
- RT5616_RXDP_SRC_DIV3
- RT5616_RXDP_SRC_MASK
- RT5616_RXDP_SRC_NOR
- RT5616_RXDP_SRC_SFT
- RT5616_R_MUTE
- RT5616_R_MUTE_SFT
- RT5616_R_VOL_MASK
- RT5616_R_VOL_SFT
- RT5616_SCB_CTRL
- RT5616_SCB_DIS
- RT5616_SCB_EN
- RT5616_SCB_FUNC
- RT5616_SCB_MASK
- RT5616_SCB_SFT
- RT5616_SCB_SWAP_DIS
- RT5616_SCB_SWAP_EN
- RT5616_SCB_SWAP_MASK
- RT5616_SCB_SWAP_SFT
- RT5616_SCLK_SRC_MASK
- RT5616_SCLK_SRC_MCLK
- RT5616_SCLK_SRC_PLL1
- RT5616_SCLK_SRC_SFT
- RT5616_SCLK_S_MCLK
- RT5616_SCLK_S_PLL1
- RT5616_SI_DAC_AUTO
- RT5616_SI_DAC_MASK
- RT5616_SI_DAC_SFT
- RT5616_SI_DAC_TEST
- RT5616_SMT_TRIG_DIS
- RT5616_SMT_TRIG_EN
- RT5616_SMT_TRIG_MASK
- RT5616_SMT_TRIG_SFT
- RT5616_SPO_CLSD_RATIO_MASK
- RT5616_SPO_CLSD_RATIO_SFT
- RT5616_STA_GP1
- RT5616_STA_GP1_BIT
- RT5616_STA_GP2
- RT5616_STA_GP2_BIT
- RT5616_STA_GP3
- RT5616_STA_GP3_BIT
- RT5616_STA_GP4
- RT5616_STA_GP4_BIT
- RT5616_STA_GP5
- RT5616_STA_GP5_BIT
- RT5616_STA_GP6
- RT5616_STA_GP6_BIT
- RT5616_STA_GP7
- RT5616_STA_GP7_BIT
- RT5616_STA_GPIO8
- RT5616_STA_GPIO8_BIT
- RT5616_STA_GP_JD
- RT5616_STA_GP_JD_BIT
- RT5616_STA_JD1_1
- RT5616_STA_JD1_1_BIT
- RT5616_STA_JD1_2
- RT5616_STA_JD1_2_BIT
- RT5616_STA_JD2
- RT5616_STA_JD2_BIT
- RT5616_STA_JD3
- RT5616_STA_JD3_BIT
- RT5616_STEREO_RATES
- RT5616_STO1_ADC_MIXER
- RT5616_STO1_ASRC_EN
- RT5616_STO1_ASRC_EN_SFT
- RT5616_STO1_DAC_M_ASRC
- RT5616_STO1_DAC_M_MASK
- RT5616_STO1_DAC_M_NOR
- RT5616_STO1_DAC_M_SFT
- RT5616_STO1_T_LRCK1
- RT5616_STO1_T_MASK
- RT5616_STO1_T_SCLK
- RT5616_STO1_T_SFT
- RT5616_STO2_ASRC_EN
- RT5616_STO2_ASRC_EN_SFT
- RT5616_STO2_DAC_M_ASRC
- RT5616_STO2_DAC_M_MASK
- RT5616_STO2_DAC_M_NOR
- RT5616_STO2_DAC_M_SFT
- RT5616_STO2_T_I2S2
- RT5616_STO2_T_LRCK2
- RT5616_STO2_T_MASK
- RT5616_STO2_T_SFT
- RT5616_STORM
- RT5616_STO_DAC_MIXER
- RT5616_STO_DD_L1_VOL_MASK
- RT5616_STO_DD_L2_R_VOL_MASK
- RT5616_STO_DD_L2_R_VOL_SFT
- RT5616_STO_DD_L2_VOL_MASK
- RT5616_STO_DD_L2_VOL_SFT
- RT5616_STO_DD_R1_VOL_MASK
- RT5616_STO_DD_R1_VOL_SFT
- RT5616_STO_DD_R2_L_VOL_MASK
- RT5616_STO_DD_R2_L_VOL_SFT
- RT5616_STO_DD_R2_VOL_MASK
- RT5616_STO_DD_R2_VOL_SFT
- RT5616_STO_L_DAC_L_VOL_MASK
- RT5616_STO_L_DAC_L_VOL_SFT
- RT5616_STO_R_DAC_R_VOL_MASK
- RT5616_STO_R_DAC_R_VOL_SFT
- RT5616_SVOL_ZC
- RT5616_SV_DIS
- RT5616_SV_DLY_MASK
- RT5616_SV_DLY_SFT
- RT5616_SV_EN
- RT5616_SV_MASK
- RT5616_SV_SFT
- RT5616_SV_ZCD1
- RT5616_SV_ZCD2
- RT5616_TDM_ADC_SEL_MASK
- RT5616_TDM_ADC_SEL_NOR
- RT5616_TDM_ADC_SEL_SFT
- RT5616_TDM_ADC_SEL_SWAP
- RT5616_TDM_ADC_START_SEL_MASK
- RT5616_TDM_ADC_START_SEL_SFT
- RT5616_TDM_ADC_START_SEL_SL0
- RT5616_TDM_ADC_START_SEL_SL4
- RT5616_TDM_CH_LEN_SEL_16
- RT5616_TDM_CH_LEN_SEL_20
- RT5616_TDM_CH_LEN_SEL_24
- RT5616_TDM_CH_LEN_SEL_32
- RT5616_TDM_CH_LEN_SEL_MASK
- RT5616_TDM_CH_LEN_SEL_SFT
- RT5616_TDM_CH_NUM_SEL_2
- RT5616_TDM_CH_NUM_SEL_4
- RT5616_TDM_CH_NUM_SEL_6
- RT5616_TDM_CH_NUM_SEL_8
- RT5616_TDM_CH_NUM_SEL_MASK
- RT5616_TDM_CH_NUM_SEL_SFT
- RT5616_TDM_CH_VAL_EN
- RT5616_TDM_CH_VAL_SEL_CH01
- RT5616_TDM_CH_VAL_SEL_CH0123
- RT5616_TDM_CH_VAL_SEL_MASK
- RT5616_TDM_CH_VAL_SEL_SFT
- RT5616_TDM_CH_VAL_SFT
- RT5616_TDM_END_EDGE_EN
- RT5616_TDM_END_EDGE_EN_SFT
- RT5616_TDM_END_EDGE_SEL_MASK
- RT5616_TDM_END_EDGE_SEL_NEG
- RT5616_TDM_END_EDGE_SEL_POS
- RT5616_TDM_END_EDGE_SEL_SFT
- RT5616_TDM_I2S_CH2_SEL_LL
- RT5616_TDM_I2S_CH2_SEL_LR
- RT5616_TDM_I2S_CH2_SEL_MASK
- RT5616_TDM_I2S_CH2_SEL_RL
- RT5616_TDM_I2S_CH2_SEL_RR
- RT5616_TDM_I2S_CH2_SEL_SFT
- RT5616_TDM_I2S_CH4_SEL_LL
- RT5616_TDM_I2S_CH4_SEL_LR
- RT5616_TDM_I2S_CH4_SEL_MASK
- RT5616_TDM_I2S_CH4_SEL_RL
- RT5616_TDM_I2S_CH4_SEL_RR
- RT5616_TDM_I2S_CH4_SEL_SFT
- RT5616_TDM_I2S_CH6_SEL_LL
- RT5616_TDM_I2S_CH6_SEL_LR
- RT5616_TDM_I2S_CH6_SEL_MASK
- RT5616_TDM_I2S_CH6_SEL_RL
- RT5616_TDM_I2S_CH6_SEL_RR
- RT5616_TDM_I2S_CH6_SEL_SFT
- RT5616_TDM_I2S_CH8_SEL_LL
- RT5616_TDM_I2S_CH8_SEL_LR
- RT5616_TDM_I2S_CH8_SEL_MASK
- RT5616_TDM_I2S_CH8_SEL_RL
- RT5616_TDM_I2S_CH8_SEL_RR
- RT5616_TDM_I2S_CH8_SEL_SFT
- RT5616_TDM_INTEL_SEL_50
- RT5616_TDM_INTEL_SEL_64
- RT5616_TDM_INTEL_SEL_MASK
- RT5616_TDM_INTEL_SEL_SFT
- RT5616_TDM_LPBK_EN
- RT5616_TDM_LPBK_SFT
- RT5616_TDM_LRCK_POL_SEL_INV
- RT5616_TDM_LRCK_POL_SEL_MASK
- RT5616_TDM_LRCK_POL_SEL_NOR
- RT5616_TDM_LRCK_POL_SEL_SFT
- RT5616_TDM_LRCK_PULSE_SEL_BCLK
- RT5616_TDM_LRCK_PULSE_SEL_CH
- RT5616_TDM_LRCK_PULSE_SEL_MASK
- RT5616_TDM_LRCK_PULSE_SEL_SFT
- RT5616_TDM_MODE_SEL_MASK
- RT5616_TDM_MODE_SEL_NOR
- RT5616_TDM_MODE_SEL_SFT
- RT5616_TDM_MODE_SEL_TDM
- RT5616_TDM_TRAN_EDGE_SEL_MASK
- RT5616_TDM_TRAN_EDGE_SEL_NEG
- RT5616_TDM_TRAN_EDGE_SEL_POS
- RT5616_TDM_TRAN_EDGE_SEL_SFT
- RT5616_TRXDP_SEL_SWAP
- RT5616_TXDC_SEL_L2R
- RT5616_TXDC_SEL_MASK
- RT5616_TXDC_SEL_NOR
- RT5616_TXDC_SEL_R2L
- RT5616_TXDC_SEL_SFT
- RT5616_TXDC_SEL_SWAP
- RT5616_TXDP_SEL_L2R
- RT5616_TXDP_SEL_MASK
- RT5616_TXDP_SEL_NOR
- RT5616_TXDP_SEL_R2L
- RT5616_TXDP_SEL_SFT
- RT5616_TXDP_SRC_DIV3
- RT5616_TXDP_SRC_MASK
- RT5616_TXDP_SRC_NOR
- RT5616_TXDP_SRC_SFT
- RT5616_VENDOR_ID
- RT5616_VERSION_ID
- RT5616_VLO_32V
- RT5616_VLO_3V
- RT5616_VLO_MASK
- RT5616_VLO_SFT
- RT5616_VOL_L_MUTE
- RT5616_VOL_L_SFT
- RT5616_VOL_R_MUTE
- RT5616_VOL_R_SFT
- RT5616_WIND_FILTER
- RT5616_WND_1
- RT5616_WND_2
- RT5616_WND_3
- RT5616_WND_4
- RT5616_WND_5
- RT5616_WND_8
- RT5616_WND_DIS
- RT5616_WND_EN
- RT5616_WND_FC_NW_MASK
- RT5616_WND_FC_NW_SFT
- RT5616_WND_FC_ST_MASK
- RT5616_WND_FC_ST_SFT
- RT5616_WND_FC_WK_MASK
- RT5616_WND_FC_WK_SFT
- RT5616_WND_MASK
- RT5616_WND_SFT
- RT5616_WND_STRONG_MASK
- RT5616_WND_STRONG_SFT
- RT5616_WND_TH_HI_MASK
- RT5616_WND_TH_HI_SFT
- RT5616_WND_TH_LO_MASK
- RT5616_WND_TH_LO_SFT
- RT5616_WND_WIND_MASK
- RT5616_WND_WIND_SFT
- RT5616_ZCD_DIG_DIS
- RT5616_ZCD_DIG_EN
- RT5616_ZCD_DIG_MASK
- RT5616_ZCD_DIG_SFT
- RT5616_ZCD_HP_DIS
- RT5616_ZCD_HP_EN
- RT5616_ZCD_HP_MASK
- RT5616_ZCD_HP_SFT
- RT5616_ZCD_MASK
- RT5616_ZCD_PD
- RT5616_ZCD_PU
- RT5616_ZCD_SFT
- RT5616_ZD_F_IM
- RT5616_ZD_F_MASK
- RT5616_ZD_F_SFT
- RT5616_ZD_F_UN
- RT5616_ZD_F_ZC_IM
- RT5616_ZD_F_ZC_IOD
- RT5616_ZD_T_MASK
- RT5616_ZD_T_SFT
- RT5631_ADC_CTRL_1
- RT5631_ADC_CTRL_2
- RT5631_ADC_DATA_SEL_Disable
- RT5631_ADC_DATA_SEL_MASK
- RT5631_ADC_DATA_SEL_MIC1
- RT5631_ADC_DATA_SEL_MIC1_SHIFT
- RT5631_ADC_DATA_SEL_MIC2
- RT5631_ADC_DATA_SEL_MIC2_SHIFT
- RT5631_ADC_DATA_SEL_SHIFT
- RT5631_ADC_DATA_SEL_STO
- RT5631_ADC_OSR_SEL_128FS
- RT5631_ADC_OSR_SEL_16FS
- RT5631_ADC_OSR_SEL_32FS
- RT5631_ADC_OSR_SEL_64FS
- RT5631_ADC_OSR_SEL_MASK
- RT5631_ADC_REC_MIXER
- RT5631_ADC_WIND_CNR_FREQ_102_141_153
- RT5631_ADC_WIND_CNR_FREQ_131_180_156
- RT5631_ADC_WIND_CNR_FREQ_163_225_245
- RT5631_ADC_WIND_CNR_FREQ_204_281_306
- RT5631_ADC_WIND_CNR_FREQ_261_360_392
- RT5631_ADC_WIND_CNR_FREQ_327_450_490
- RT5631_ADC_WIND_CNR_FREQ_408_563_612
- RT5631_ADC_WIND_CNR_FREQ_82_113_122
- RT5631_ADC_WIND_CNR_FREQ_MASK
- RT5631_ADC_WIND_FILT_11_22_44K
- RT5631_ADC_WIND_FILT_12_24_48K
- RT5631_ADC_WIND_FILT_8_16_32K
- RT5631_ADC_WIND_FILT_EN
- RT5631_ADC_WIND_FILT_MASK
- RT5631_ADDA_FILTER_CLK_SEL_256FS
- RT5631_ADDA_FILTER_CLK_SEL_384FS
- RT5631_ADDA_MIXER_INTL_REG3
- RT5631_ALC_ATTACK_RATE_MASK
- RT5631_ALC_COM_NOISE_GATE_MASK
- RT5631_ALC_CTRL_1
- RT5631_ALC_CTRL_2
- RT5631_ALC_CTRL_3
- RT5631_ALC_ENA_ADC_PATH
- RT5631_ALC_ENA_DAC_PATH
- RT5631_ALC_FUN_DIS
- RT5631_ALC_FUN_MASK
- RT5631_ALC_LIMIT_LEVEL_MASK
- RT5631_ALC_NOISE_GATE_FUN_DIS
- RT5631_ALC_NOISE_GATE_FUN_ENA
- RT5631_ALC_NOISE_GATE_FUN_MASK
- RT5631_ALC_NOISE_GATE_H_D_DIS
- RT5631_ALC_NOISE_GATE_H_D_ENA
- RT5631_ALC_NOISE_GATE_H_D_MASK
- RT5631_ALC_PARA_UPDATE
- RT5631_ALC_RECOVERY_RATE_MASK
- RT5631_ALL_PASS_FILTER_EN
- RT5631_APF_FUN_DIS
- RT5631_APF_FUN_SEL_32K
- RT5631_APF_FUN_SEL_44_1K
- RT5631_APF_FUN_SEL_48K
- RT5631_APF_FUN_SLE_MASK
- RT5631_AUXOUT_1_VOL_SEL_MASK
- RT5631_AUXOUT_1_VOL_SEL_OUTMIX_L
- RT5631_AUXOUT_1_VOL_SEL_VMID
- RT5631_AUXOUT_2_VOL_SEL_MASK
- RT5631_AUXOUT_2_VOL_SEL_OUTMIX_R
- RT5631_AUXOUT_2_VOL_SEL_VMID
- RT5631_AUX_IN_VOL
- RT5631_AXO1MIXER_CTRL
- RT5631_AXO2MIXER_CTRL
- RT5631_CP_INTL_REG2
- RT5631_DAC_OSR_SEL_128FS
- RT5631_DAC_OSR_SEL_16FS
- RT5631_DAC_OSR_SEL_32FS
- RT5631_DAC_OSR_SEL_64FS
- RT5631_DAC_OSR_SEL_MASK
- RT5631_DAC_VOL_MASK
- RT5631_DEPOP_FUN_CTRL_1
- RT5631_DEPOP_FUN_CTRL_2
- RT5631_DIG_MIC_CTRL
- RT5631_DMIC_CLK_CTRL_MASK
- RT5631_DMIC_CLK_CTRL_TO_128FS
- RT5631_DMIC_CLK_CTRL_TO_32FS
- RT5631_DMIC_CLK_CTRL_TO_64FS
- RT5631_DMIC_DIS
- RT5631_DMIC_ENA
- RT5631_DMIC_ENA_MASK
- RT5631_DMIC_ENA_SHIFT
- RT5631_DMIC_L_CH_LATCH_FALLING
- RT5631_DMIC_L_CH_LATCH_MASK
- RT5631_DMIC_L_CH_LATCH_RISING
- RT5631_DMIC_L_CH_MUTE
- RT5631_DMIC_L_CH_MUTE_SHIFT
- RT5631_DMIC_R_CH_LATCH_FALLING
- RT5631_DMIC_R_CH_LATCH_MASK
- RT5631_DMIC_R_CH_LATCH_RISING
- RT5631_DMIC_R_CH_MUTE
- RT5631_DMIC_R_CH_MUTE_SHIFT
- RT5631_EN_CAP_FREE_DEPOP
- RT5631_EN_DEPOP2_FOR_HP
- RT5631_EN_HP_L_M_UN_MUTE_DEPOP
- RT5631_EN_HP_R_M_UN_MUTE_DEPOP
- RT5631_EN_HW_EQ_BP1
- RT5631_EN_HW_EQ_BP2
- RT5631_EN_HW_EQ_BP3
- RT5631_EN_HW_EQ_HPF1
- RT5631_EN_HW_EQ_HPF2
- RT5631_EN_HW_EQ_LPF
- RT5631_EN_MUTE_UNMUTE_DEPOP
- RT5631_EN_ONE_BIT_DEPOP
- RT5631_EQ_BW_BP1
- RT5631_EQ_BW_BP2
- RT5631_EQ_BW_BP3
- RT5631_EQ_BW_HIP
- RT5631_EQ_BW_LOP
- RT5631_EQ_CTRL
- RT5631_EQ_FC_BP1
- RT5631_EQ_FC_BP2
- RT5631_EQ_FC_BP3
- RT5631_EQ_GAIN_BP1
- RT5631_EQ_GAIN_BP2
- RT5631_EQ_GAIN_BP3
- RT5631_EQ_GAIN_HIP
- RT5631_EQ_GAIN_LOP
- RT5631_EQ_HPF_A1
- RT5631_EQ_HPF_A2
- RT5631_EQ_HPF_GAIN
- RT5631_EQ_POST_VOL_CTRL
- RT5631_EQ_PRE_VOL_CTRL
- RT5631_FORMAT
- RT5631_GAIN_3D_PARA_1_00
- RT5631_GAIN_3D_PARA_1_50
- RT5631_GAIN_3D_PARA_2_00
- RT5631_GAIN_3D_PARA_MASK
- RT5631_GEN_PUR_CTRL_REG
- RT5631_GLOBAL_CLK_CTRL
- RT5631_GPIO_CTRL
- RT5631_GPIO_DMIC_FUN_SEL_DIMC
- RT5631_GPIO_DMIC_FUN_SEL_GPIO
- RT5631_GPIO_DMIC_FUN_SEL_MASK
- RT5631_GPIO_PIN_CON_MASK
- RT5631_GPIO_PIN_FUN_SEL_GPIO_DIMC
- RT5631_GPIO_PIN_FUN_SEL_IRQ
- RT5631_GPIO_PIN_FUN_SEL_MASK
- RT5631_GPIO_PIN_SET_INPUT
- RT5631_GPIO_PIN_SET_OUTPUT
- RT5631_HP_L_MUX_SEL_DAC_L
- RT5631_HP_L_MUX_SEL_HPVOL_L
- RT5631_HP_L_MUX_SEL_MASK
- RT5631_HP_L_MUX_SEL_SHIFT
- RT5631_HP_L_VOL_SEL_MASK
- RT5631_HP_L_VOL_SEL_OUTMIX_L
- RT5631_HP_L_VOL_SEL_VMID
- RT5631_HP_OUT_VOL
- RT5631_HP_R_MUX_SEL_DAC_R
- RT5631_HP_R_MUX_SEL_HPVOL_R
- RT5631_HP_R_MUX_SEL_MASK
- RT5631_HP_R_MUX_SEL_SHIFT
- RT5631_HP_R_VOL_SEL_MASK
- RT5631_HP_R_VOL_SEL_OUTMIX_R
- RT5631_HP_R_VOL_SEL_VMID
- RT5631_HW_EQ_PATH_SEL_ADC
- RT5631_HW_EQ_PATH_SEL_DAC
- RT5631_HW_EQ_PATH_SEL_MASK
- RT5631_HW_EQ_UPDATE_CTRL
- RT5631_I2S_LRCK_SEL_32_BCLK
- RT5631_I2S_LRCK_SEL_64_BCLK
- RT5631_I2S_LRCK_SEL_N_BCLK_MASK
- RT5631_I2S_PRE_DIV_1
- RT5631_I2S_PRE_DIV_16
- RT5631_I2S_PRE_DIV_2
- RT5631_I2S_PRE_DIV_32
- RT5631_I2S_PRE_DIV_4
- RT5631_I2S_PRE_DIV_8
- RT5631_I2S_PRE_DIV_MASK
- RT5631_INDEX_ADD
- RT5631_INDEX_DATA
- RT5631_INT_ST_IRQ_CTRL_1
- RT5631_INT_ST_IRQ_CTRL_2
- RT5631_JACK_DET_CTRL
- RT5631_JD_AUX_1_EN
- RT5631_JD_AUX_1_MASK
- RT5631_JD_AUX_1_TRI_HI
- RT5631_JD_AUX_1_TRI_LO
- RT5631_JD_AUX_2_EN
- RT5631_JD_AUX_2_MASK
- RT5631_JD_AUX_2_TRI_HI
- RT5631_JD_AUX_2_TRI_LO
- RT5631_JD_HP_EN
- RT5631_JD_HP_TRI_HI
- RT5631_JD_HP_TRI_LO
- RT5631_JD_HP_TRI_MASK
- RT5631_JD_MONO_EN
- RT5631_JD_MONO_TRI_HI
- RT5631_JD_MONO_TRI_LO
- RT5631_JD_MONO_TRI_MASK
- RT5631_JD_OFF
- RT5631_JD_SPK_L_EN
- RT5631_JD_SPK_L_TRI_HI
- RT5631_JD_SPK_L_TRI_LO
- RT5631_JD_SPK_L_TRI_MASK
- RT5631_JD_SPK_R_EN
- RT5631_JD_SPK_R_TRI_HI
- RT5631_JD_SPK_R_TRI_LO
- RT5631_JD_SPK_R_TRI_MASK
- RT5631_JD_USE_GPIO
- RT5631_JD_USE_JD1
- RT5631_JD_USE_JD2
- RT5631_JD_USE_MASK
- RT5631_L_EN
- RT5631_L_EN_SHIFT
- RT5631_L_MUTE
- RT5631_L_MUTE_SHIFT
- RT5631_L_VOL_SHIFT
- RT5631_MIC1_BOOST_CTRL_20DB
- RT5631_MIC1_BOOST_CTRL_24DB
- RT5631_MIC1_BOOST_CTRL_30DB
- RT5631_MIC1_BOOST_CTRL_34DB
- RT5631_MIC1_BOOST_CTRL_35DB
- RT5631_MIC1_BOOST_CTRL_40DB
- RT5631_MIC1_BOOST_CTRL_50DB
- RT5631_MIC1_BOOST_CTRL_52DB
- RT5631_MIC1_BOOST_CTRL_BYPASS
- RT5631_MIC1_BOOST_CTRL_MASK
- RT5631_MIC1_BOOST_SHIFT
- RT5631_MIC1_DIFF_INPUT_CTRL
- RT5631_MIC1_DIFF_INPUT_SHIFT
- RT5631_MIC2_BOOST_CTRL_20DB
- RT5631_MIC2_BOOST_CTRL_24DB
- RT5631_MIC2_BOOST_CTRL_30DB
- RT5631_MIC2_BOOST_CTRL_34DB
- RT5631_MIC2_BOOST_CTRL_35DB
- RT5631_MIC2_BOOST_CTRL_40DB
- RT5631_MIC2_BOOST_CTRL_50DB
- RT5631_MIC2_BOOST_CTRL_52DB
- RT5631_MIC2_BOOST_CTRL_BYPASS
- RT5631_MIC2_BOOST_CTRL_MASK
- RT5631_MIC2_BOOST_SHIFT
- RT5631_MIC2_DIFF_INPUT_CTRL
- RT5631_MIC2_DIFF_INPUT_SHIFT
- RT5631_MICBIAS1_SHORT_CURR_DET_1500UA
- RT5631_MICBIAS1_SHORT_CURR_DET_2000UA
- RT5631_MICBIAS1_SHORT_CURR_DET_600UA
- RT5631_MICBIAS1_SHORT_CURR_DET_MASK
- RT5631_MICBIAS1_S_C_DET_DIS
- RT5631_MICBIAS1_S_C_DET_ENA
- RT5631_MICBIAS1_S_C_DET_MASK
- RT5631_MICBIAS1_VOLT_CTRL_75P
- RT5631_MICBIAS1_VOLT_CTRL_90P
- RT5631_MICBIAS1_VOLT_CTRL_MASK
- RT5631_MICBIAS2_SHORT_CURR_DET_1500UA
- RT5631_MICBIAS2_SHORT_CURR_DET_2000UA
- RT5631_MICBIAS2_SHORT_CURR_DET_600UA
- RT5631_MICBIAS2_SHORT_CURR_DET_MASK
- RT5631_MICBIAS2_S_C_DET_DIS
- RT5631_MICBIAS2_S_C_DET_ENA
- RT5631_MICBIAS2_S_C_DET_MASK
- RT5631_MICBIAS2_VOLT_CTRL_75P
- RT5631_MICBIAS2_VOLT_CTRL_90P
- RT5631_MICBIAS2_VOLT_CTRL_MASK
- RT5631_MIC_BIAS_75_PRECNET_AVDD
- RT5631_MIC_BIAS_90_PRECNET_AVDD
- RT5631_MIC_CTRL_1
- RT5631_MIC_CTRL_2
- RT5631_MISC_CTRL
- RT5631_MONO_AXO_1_2_VOL
- RT5631_MONO_DIFF_INPUT_SHIFT
- RT5631_MONO_INPUT_VOL
- RT5631_MONO_MUX_SEL_MASK
- RT5631_MONO_MUX_SEL_MONOMIXER
- RT5631_MONO_MUX_SEL_MONO_IN
- RT5631_MONO_MUX_SEL_SHIFT
- RT5631_MONO_SDP_CTRL
- RT5631_MUTE_MONO
- RT5631_MUTE_MONO_SHIFT
- RT5631_M_AXIL_OUTMIXL_BIT
- RT5631_M_AXIL_OUTMIXR_BIT
- RT5631_M_AXIL_RECMIXL_BIT
- RT5631_M_AXIL_TO_OUTMIXER_L
- RT5631_M_AXIL_TO_OUTMIXER_R
- RT5631_M_AXIL_TO_RECMIXER_L
- RT5631_M_AXIR_OUTMIXL_BIT
- RT5631_M_AXIR_OUTMIXR_BIT
- RT5631_M_AXIR_RECMIXR_BIT
- RT5631_M_AXIR_TO_OUTMIXER_L
- RT5631_M_AXIR_TO_OUTMIXER_R
- RT5631_M_AXIR_TO_RECMIXER_R
- RT5631_M_DACL_OUTMIXL_BIT
- RT5631_M_DACL_SPKMIXL_BIT
- RT5631_M_DACR_OUTMIXR_BIT
- RT5631_M_DACR_SPKMIXR_BIT
- RT5631_M_DAC_L_TO_OUTMIXER_L
- RT5631_M_DAC_L_TO_SPKMIXER_L
- RT5631_M_DAC_R_TO_OUTMIXER_R
- RT5631_M_DAC_R_TO_SPKMIXER_R
- RT5631_M_MIC1P_SPKMIXL_BIT
- RT5631_M_MIC1_AXO1MIX_BIT
- RT5631_M_MIC1_AXO2MIX_BIT
- RT5631_M_MIC1_OUTMIXL_BIT
- RT5631_M_MIC1_OUTMIXR_BIT
- RT5631_M_MIC1_P_TO_SPKMIXER_L
- RT5631_M_MIC1_RECMIXL_BIT
- RT5631_M_MIC1_TO_AXO1MIXER
- RT5631_M_MIC1_TO_AXO2MIXER
- RT5631_M_MIC1_TO_OUTMIXER_L
- RT5631_M_MIC1_TO_OUTMIXER_R
- RT5631_M_MIC1_TO_RECMIXER_L
- RT5631_M_MIC2P_SPKMIXR_BIT
- RT5631_M_MIC2_AXO1MIX_BIT
- RT5631_M_MIC2_AXO2MIX_BIT
- RT5631_M_MIC2_OUTMIXL_BIT
- RT5631_M_MIC2_OUTMIXR_BIT
- RT5631_M_MIC2_P_TO_SPKMIXER_R
- RT5631_M_MIC2_RECMIXR_BIT
- RT5631_M_MIC2_TO_AXO1MIXER
- RT5631_M_MIC2_TO_AXO2MIXER
- RT5631_M_MIC2_TO_OUTMIXER_L
- RT5631_M_MIC2_TO_OUTMIXER_R
- RT5631_M_MIC2_TO_RECMIXER_R
- RT5631_M_MONO_INN_OUTMIXR_BIT
- RT5631_M_MONO_INP_OUTMIXL_BIT
- RT5631_M_MONO_IN_N_TO_OUTMIXER_R
- RT5631_M_MONO_IN_P_TO_OUTMIXER_L
- RT5631_M_MONO_IN_RECMIXL_BIT
- RT5631_M_MONO_IN_RECMIXR_BIT
- RT5631_M_MONO_IN_TO_RECMIXER_L
- RT5631_M_MONO_IN_TO_RECMIXER_R
- RT5631_M_OUTMIXER_L_TO_AXO1MIXER
- RT5631_M_OUTMIXER_L_TO_AXO2MIXER
- RT5631_M_OUTMIXER_L_TO_RECMIXER_L
- RT5631_M_OUTMIXER_L_TO_SPKMIXER_L
- RT5631_M_OUTMIXER_R_TO_AXO1MIXER
- RT5631_M_OUTMIXER_R_TO_AXO2MIXER
- RT5631_M_OUTMIXER_R_TO_RECMIXER_R
- RT5631_M_OUTMIXER_R_TO_SPKMIXER_R
- RT5631_M_OUTMIXL_AXO1MIX_BIT
- RT5631_M_OUTMIXL_AXO2MIX_BIT
- RT5631_M_OUTMIXL_RECMIXL_BIT
- RT5631_M_OUTMIXL_SPKMIXL_BIT
- RT5631_M_OUTMIXR_AXO1MIX_BIT
- RT5631_M_OUTMIXR_AXO2MIX_BIT
- RT5631_M_OUTMIXR_RECMIXR_BIT
- RT5631_M_OUTMIXR_SPKMIXR_BIT
- RT5631_M_OUTVOLL_MONOMIX_BIT
- RT5631_M_OUTVOLR_MONOMIX_BIT
- RT5631_M_OUTVOL_L_TO_MONOMIXER
- RT5631_M_OUTVOL_R_TO_MONOMIXER
- RT5631_M_RECMIXER_L_TO_OUTMIXER_L
- RT5631_M_RECMIXER_L_TO_OUTMIXER_R
- RT5631_M_RECMIXER_L_TO_SPKMIXER_L
- RT5631_M_RECMIXER_R_TO_OUTMIXER_L
- RT5631_M_RECMIXER_R_TO_OUTMIXER_R
- RT5631_M_RECMIXER_R_TO_SPKMIXER_R
- RT5631_M_RECMIXL_OUTMIXL_BIT
- RT5631_M_RECMIXL_OUTMIXR_BIT
- RT5631_M_RECMIXL_SPKMIXL_BIT
- RT5631_M_RECMIXR_OUTMIXL_BIT
- RT5631_M_RECMIXR_OUTMIXR_BIT
- RT5631_M_RECMIXR_SPKMIXR_BIT
- RT5631_M_SPKVOLL_SPOLMIX_BIT
- RT5631_M_SPKVOLL_SPORMIX_BIT
- RT5631_M_SPKVOLR_SPOLMIX_BIT
- RT5631_M_SPKVOLR_SPORMIX_BIT
- RT5631_M_SPKVOL_L_TO_SPOL_MIXER
- RT5631_M_SPKVOL_L_TO_SPOR_MIXER
- RT5631_M_SPKVOL_R_TO_SPOL_MIXER
- RT5631_M_SPKVOL_R_TO_SPOR_MIXER
- RT5631_M_VDAC_OUTMIXL_BIT
- RT5631_M_VDAC_OUTMIXR_BIT
- RT5631_M_VDAC_TO_OUTMIXER_L
- RT5631_M_VDAC_TO_OUTMIXER_R
- RT5631_OUTMIXER_L_CTRL
- RT5631_OUTMIXER_R_CTRL
- RT5631_PD_HPAMP_L_ST_UP
- RT5631_PD_HPAMP_R_ST_UP
- RT5631_PLLCLK_PRE_DIV1
- RT5631_PLLCLK_PRE_DIV2
- RT5631_PLLCLK_SOUR_SEL_BCLK
- RT5631_PLLCLK_SOUR_SEL_MASK
- RT5631_PLLCLK_SOUR_SEL_MCLK
- RT5631_PLLCLK_SOUR_SEL_VBCLK
- RT5631_PLL_CTRL
- RT5631_PLL_CTRL_K_VAL
- RT5631_PLL_CTRL_M_VAL
- RT5631_PLL_CTRL_N_VAL
- RT5631_POW_ON_SOFT_GEN
- RT5631_PSEUDO_SPATL_CTRL
- RT5631_PSEUDO_STEREO_EN
- RT5631_PWR_ADC_L_CLK
- RT5631_PWR_ADC_L_CLK_BIT
- RT5631_PWR_ADC_R_CLK
- RT5631_PWR_ADC_R_CLK_BIT
- RT5631_PWR_AXIL_IN_VOL
- RT5631_PWR_AXIL_IN_VOL_BIT
- RT5631_PWR_AXIR_IN_VOL
- RT5631_PWR_AXIR_IN_VOL_BIT
- RT5631_PWR_AXO1MIXER
- RT5631_PWR_AXO1MIXER_BIT
- RT5631_PWR_AXO2MIXER
- RT5631_PWR_AXO2MIXER_BIT
- RT5631_PWR_CHARGE_PUMP
- RT5631_PWR_CHARGE_PUMP_BIT
- RT5631_PWR_CLASS_D
- RT5631_PWR_CLASS_D_BIT
- RT5631_PWR_DAC_L_CLK
- RT5631_PWR_DAC_L_CLK_BIT
- RT5631_PWR_DAC_L_TO_MIXER
- RT5631_PWR_DAC_L_TO_MIXER_BIT
- RT5631_PWR_DAC_REF
- RT5631_PWR_DAC_REF_BIT
- RT5631_PWR_DAC_R_CLK
- RT5631_PWR_DAC_R_CLK_BIT
- RT5631_PWR_DAC_R_TO_MIXER
- RT5631_PWR_DAC_R_TO_MIXER_BIT
- RT5631_PWR_FAST_VREF_CTRL
- RT5631_PWR_FAST_VREF_CTRL_BIT
- RT5631_PWR_HP_AMP_DRIVING
- RT5631_PWR_HP_AMP_DRIVING_BIT
- RT5631_PWR_HP_DEPOP_DIS
- RT5631_PWR_HP_DEPOP_DIS_BIT
- RT5631_PWR_HP_L_AMP
- RT5631_PWR_HP_L_AMP_BIT
- RT5631_PWR_HP_L_OUT_VOL
- RT5631_PWR_HP_L_OUT_VOL_BIT
- RT5631_PWR_HP_R_AMP
- RT5631_PWR_HP_R_AMP_BIT
- RT5631_PWR_HP_R_OUT_VOL
- RT5631_PWR_HP_R_OUT_VOL_BIT
- RT5631_PWR_LOUT_VOL
- RT5631_PWR_LOUT_VOL_BIT
- RT5631_PWR_MAIN_BIAS
- RT5631_PWR_MAIN_BIAS_BIT
- RT5631_PWR_MAIN_I2S_BIT
- RT5631_PWR_MAIN_I2S_EN
- RT5631_PWR_MANAG_ADD1
- RT5631_PWR_MANAG_ADD2
- RT5631_PWR_MANAG_ADD3
- RT5631_PWR_MANAG_ADD4
- RT5631_PWR_MIC1_BOOT_GAIN
- RT5631_PWR_MIC1_BOOT_GAIN_BIT
- RT5631_PWR_MIC2_BOOT_GAIN
- RT5631_PWR_MIC2_BOOT_GAIN_BIT
- RT5631_PWR_MICBIAS1_VOL
- RT5631_PWR_MICBIAS1_VOL_BIT
- RT5631_PWR_MICBIAS2_VOL
- RT5631_PWR_MICBIAS2_VOL_BIT
- RT5631_PWR_MONOMIXER
- RT5631_PWR_MONOMIXER_BIT
- RT5631_PWR_MONO_AMP_EN
- RT5631_PWR_MONO_AMP_EN_BIT
- RT5631_PWR_MONO_DEPOP_DIS
- RT5631_PWR_MONO_DEPOP_DIS_BIT
- RT5631_PWR_MONO_IN_N_VOL
- RT5631_PWR_MONO_IN_N_VOL_BIT
- RT5631_PWR_MONO_IN_P_VOL
- RT5631_PWR_MONO_IN_P_VOL_BIT
- RT5631_PWR_OUTMIXER_L
- RT5631_PWR_OUTMIXER_L_BIT
- RT5631_PWR_OUTMIXER_R
- RT5631_PWR_OUTMIXER_R_BIT
- RT5631_PWR_PLL1
- RT5631_PWR_PLL1_BIT
- RT5631_PWR_PLL2
- RT5631_PWR_PLL2_BIT
- RT5631_PWR_RECMIXER_L
- RT5631_PWR_RECMIXER_L_BIT
- RT5631_PWR_RECMIXER_R
- RT5631_PWR_RECMIXER_R_BIT
- RT5631_PWR_ROUT_VOL
- RT5631_PWR_ROUT_VOL_BIT
- RT5631_PWR_SPKMIXER_L
- RT5631_PWR_SPKMIXER_L_BIT
- RT5631_PWR_SPKMIXER_R
- RT5631_PWR_SPKMIXER_R_BIT
- RT5631_PWR_SPK_L_VOL
- RT5631_PWR_SPK_L_VOL_BIT
- RT5631_PWR_SPK_R_VOL
- RT5631_PWR_SPK_R_VOL_BIT
- RT5631_PWR_VREF
- RT5631_PWR_VREF_BIT
- RT5631_RATIO_3D_0_0
- RT5631_RATIO_3D_0_66
- RT5631_RATIO_3D_1_0
- RT5631_RATIO_3D_MASK
- RT5631_RESET
- RT5631_R_EN
- RT5631_R_EN_SHIFT
- RT5631_R_MUTE
- RT5631_R_MUTE_SHIFT
- RT5631_R_VOL_SHIFT
- RT5631_SDP_ADC_CPS_SEL_A_LAW
- RT5631_SDP_ADC_CPS_SEL_MASK
- RT5631_SDP_ADC_CPS_SEL_OFF
- RT5631_SDP_ADC_CPS_SEL_U_LAW
- RT5631_SDP_ADC_DATA_L_R_SWAP
- RT5631_SDP_CTRL
- RT5631_SDP_DAC_CPS_SEL_A_LAW
- RT5631_SDP_DAC_CPS_SEL_MASK
- RT5631_SDP_DAC_CPS_SEL_OFF
- RT5631_SDP_DAC_CPS_SEL_U_LAW
- RT5631_SDP_DAC_DATA_L_R_SWAP
- RT5631_SDP_DAC_R_INV
- RT5631_SDP_I2S_BCLK_POL_CTRL
- RT5631_SDP_I2S_DF_I2S
- RT5631_SDP_I2S_DF_LEFT
- RT5631_SDP_I2S_DF_MASK
- RT5631_SDP_I2S_DF_PCM_A
- RT5631_SDP_I2S_DF_PCM_B
- RT5631_SDP_I2S_DL_16
- RT5631_SDP_I2S_DL_20
- RT5631_SDP_I2S_DL_24
- RT5631_SDP_I2S_DL_8
- RT5631_SDP_I2S_DL_MASK
- RT5631_SDP_MODE_SEL_MASK
- RT5631_SDP_MODE_SEL_MASTER
- RT5631_SDP_MODE_SEL_SLAVE
- RT5631_SOFT_VOL_CTRL
- RT5631_SPATIAL_CTRL_EN
- RT5631_SPK_AMP_AUTO_RATIO_EN
- RT5631_SPK_AMP_RATIO_CTRL_1_00
- RT5631_SPK_AMP_RATIO_CTRL_1_09
- RT5631_SPK_AMP_RATIO_CTRL_1_27
- RT5631_SPK_AMP_RATIO_CTRL_1_44
- RT5631_SPK_AMP_RATIO_CTRL_1_56
- RT5631_SPK_AMP_RATIO_CTRL_1_68
- RT5631_SPK_AMP_RATIO_CTRL_1_99
- RT5631_SPK_AMP_RATIO_CTRL_2_34
- RT5631_SPK_AMP_RATIO_CTRL_MASK
- RT5631_SPK_AMP_RATIO_CTRL_SHIFT
- RT5631_SPK_INTL_CTRL
- RT5631_SPK_L_MUX_SEL_DAC_L
- RT5631_SPK_L_MUX_SEL_MASK
- RT5631_SPK_L_MUX_SEL_MONO_IN
- RT5631_SPK_L_MUX_SEL_SHIFT
- RT5631_SPK_L_MUX_SEL_SPKMIXER_L
- RT5631_SPK_L_VOL_SEL_MASK
- RT5631_SPK_L_VOL_SEL_SPKMIX_L
- RT5631_SPK_L_VOL_SEL_VMID
- RT5631_SPK_MIXER_CTRL
- RT5631_SPK_MONO_HP_OUT_CTRL
- RT5631_SPK_MONO_OUT_CTRL
- RT5631_SPK_OUT_VOL
- RT5631_SPK_R_MUX_SEL_DAC_R
- RT5631_SPK_R_MUX_SEL_MASK
- RT5631_SPK_R_MUX_SEL_MONO_IN
- RT5631_SPK_R_MUX_SEL_SHIFT
- RT5631_SPK_R_MUX_SEL_SPKMIXER_R
- RT5631_SPK_R_VOL_SEL_MASK
- RT5631_SPK_R_VOL_SEL_SPKMIX_R
- RT5631_SPK_R_VOL_SEL_VMID
- RT5631_STEREO_ADC_HI_PASS_FILT_EN
- RT5631_STEREO_AD_DA_CLK_CTRL
- RT5631_STEREO_DAC_HI_PASS_FILT_EN
- RT5631_STEREO_DAC_VOL_1
- RT5631_STEREO_DAC_VOL_2
- RT5631_STEREO_EXPENSION_EN
- RT5631_STEREO_RATES
- RT5631_SYSCLK_SOUR_SEL_MASK
- RT5631_SYSCLK_SOUR_SEL_MCLK
- RT5631_SYSCLK_SOUR_SEL_PLL
- RT5631_SYSCLK_SOUR_SEL_PLL_TCK
- RT5631_TEST_MODE_CTRL
- RT5631_VDAC_DIG_VOL
- RT5631_VENDOR_ID
- RT5631_VENDOR_ID1
- RT5631_VENDOR_ID2
- RT5631_VOL_MASK
- RT5640_1ST_HPF_DIS
- RT5640_1ST_HPF_EN
- RT5640_1ST_HPF_MASK
- RT5640_1ST_HPF_SFT
- RT5640_2ND_HPF_DIS
- RT5640_2ND_HPF_EN
- RT5640_2ND_HPF_MASK
- RT5640_2ND_HPF_SFT
- RT5640_3D_1F_MIX_MASK
- RT5640_3D_1F_MIX_SFT
- RT5640_3D_BT_DIS
- RT5640_3D_BT_EN
- RT5640_3D_BT_MASK
- RT5640_3D_BT_SFT
- RT5640_3D_CF_DIS
- RT5640_3D_CF_EN
- RT5640_3D_CF_MASK
- RT5640_3D_CF_SFT
- RT5640_3D_HP
- RT5640_3D_HP_DIS
- RT5640_3D_HP_EN
- RT5640_3D_HP_MASK
- RT5640_3D_HP_M_FRO
- RT5640_3D_HP_M_MASK
- RT5640_3D_HP_M_SFT
- RT5640_3D_HP_M_SUR
- RT5640_3D_HP_SFT
- RT5640_3D_SPK
- RT5640_3D_SPK_CG_MASK
- RT5640_3D_SPK_CG_SFT
- RT5640_3D_SPK_DIS
- RT5640_3D_SPK_EN
- RT5640_3D_SPK_MASK
- RT5640_3D_SPK_M_MASK
- RT5640_3D_SPK_M_SFT
- RT5640_3D_SPK_SFT
- RT5640_3D_SPK_SG_MASK
- RT5640_3D_SPK_SG_SFT
- RT5640_ADC_1_SRC_ADC
- RT5640_ADC_1_SRC_DACMIX
- RT5640_ADC_1_SRC_MASK
- RT5640_ADC_1_SRC_SFT
- RT5640_ADC_2_SRC_DACMIX
- RT5640_ADC_2_SRC_DMIC1
- RT5640_ADC_2_SRC_DMIC2
- RT5640_ADC_2_SRC_MASK
- RT5640_ADC_2_SRC_SFT
- RT5640_ADC_BST_VOL
- RT5640_ADC_COMP_MASK
- RT5640_ADC_COMP_SFT
- RT5640_ADC_DATA
- RT5640_ADC_DIG_VOL
- RT5640_ADC_L_BST_MASK
- RT5640_ADC_L_BST_SFT
- RT5640_ADC_L_VOL_MASK
- RT5640_ADC_L_VOL_SFT
- RT5640_ADC_M_ASYN
- RT5640_ADC_M_MASK
- RT5640_ADC_M_NOR
- RT5640_ADC_M_SFT
- RT5640_ADC_OSR_128
- RT5640_ADC_OSR_16
- RT5640_ADC_OSR_32
- RT5640_ADC_OSR_64
- RT5640_ADC_OSR_MASK
- RT5640_ADC_OSR_SFT
- RT5640_ADC_R_BST_MASK
- RT5640_ADC_R_BST_SFT
- RT5640_ADC_R_OSR_128
- RT5640_ADC_R_OSR_16
- RT5640_ADC_R_OSR_32
- RT5640_ADC_R_OSR_64
- RT5640_ADC_R_OSR_MASK
- RT5640_ADC_R_OSR_SFT
- RT5640_ADC_R_VOL_MASK
- RT5640_ADC_R_VOL_SFT
- RT5640_ADDA_CLK1
- RT5640_ADDA_CLK2
- RT5640_ADHPF_EN
- RT5640_ADHPF_EN_SFT
- RT5640_ADJ_HPF
- RT5640_AD_DA_MIXER
- RT5640_AD_MONO_L_FILTER
- RT5640_AD_MONO_R_FILTER
- RT5640_AD_STEREO_FILTER
- RT5640_AD_TRG_HI
- RT5640_AD_TRG_LO
- RT5640_AD_TRG_MASK
- RT5640_AD_TRG_SFT
- RT5640_AIF1
- RT5640_AIF2
- RT5640_AIF3
- RT5640_AIFS
- RT5640_AMD_TRG_HI
- RT5640_AMD_TRG_LO
- RT5640_AMD_TRG_MASK
- RT5640_AMD_TRG_SFT
- RT5640_ANCM_DET_DIS
- RT5640_ANCM_DET_JD
- RT5640_ANCM_DET_MASK
- RT5640_ANCM_DET_MB1
- RT5640_ANCM_DET_MB2
- RT5640_ANCM_DET_SFT
- RT5640_ANC_CD_BOTH
- RT5640_ANC_CD_IND
- RT5640_ANC_CD_MASK
- RT5640_ANC_CD_SFT
- RT5640_ANC_CG_L_MASK
- RT5640_ANC_CG_L_SFT
- RT5640_ANC_CG_R_MASK
- RT5640_ANC_CG_R_SFT
- RT5640_ANC_CLK_ANC
- RT5640_ANC_CLK_MASK
- RT5640_ANC_CLK_REG
- RT5640_ANC_CLK_SFT
- RT5640_ANC_CO_L_MASK
- RT5640_ANC_CO_L_SFT
- RT5640_ANC_CO_R_MASK
- RT5640_ANC_CO_R_SFT
- RT5640_ANC_CS_DIS
- RT5640_ANC_CS_EN
- RT5640_ANC_CS_MASK
- RT5640_ANC_CS_SFT
- RT5640_ANC_CTRL1
- RT5640_ANC_CTRL2
- RT5640_ANC_CTRL3
- RT5640_ANC_DET_DIS
- RT5640_ANC_DET_JD
- RT5640_ANC_DET_MASK
- RT5640_ANC_DET_MB1
- RT5640_ANC_DET_MB2
- RT5640_ANC_DET_SFT
- RT5640_ANC_DIS
- RT5640_ANC_EN
- RT5640_ANC_FG_L_MASK
- RT5640_ANC_FG_L_SFT
- RT5640_ANC_FG_R_MASK
- RT5640_ANC_FG_R_SFT
- RT5640_ANC_JD
- RT5640_ANC_MASK
- RT5640_ANC_MD_1067MS
- RT5640_ANC_MD_267MS
- RT5640_ANC_MD_67MS
- RT5640_ANC_MD_DIS
- RT5640_ANC_MD_MASK
- RT5640_ANC_MD_SFT
- RT5640_ANC_M_MASK
- RT5640_ANC_M_NOR
- RT5640_ANC_M_REV
- RT5640_ANC_M_SFT
- RT5640_ANC_SFT
- RT5640_ANC_SN_DIS
- RT5640_ANC_SN_EN
- RT5640_ANC_SN_MASK
- RT5640_ANC_SN_SFT
- RT5640_ANC_SW_AUTO
- RT5640_ANC_SW_MASK
- RT5640_ANC_SW_NOR
- RT5640_ANC_SW_SFT
- RT5640_ANC_ZCD_DIS
- RT5640_ANC_ZCD_MASK
- RT5640_ANC_ZCD_SFT
- RT5640_ANC_ZCD_T1
- RT5640_ANC_ZCD_T2
- RT5640_ANC_ZCD_WT
- RT5640_ASRC_1
- RT5640_ASRC_2
- RT5640_ASRC_3
- RT5640_ASRC_4
- RT5640_ASRC_5
- RT5640_AUTO_PD_DIS
- RT5640_AUTO_PD_EN
- RT5640_AUTO_PD_MASK
- RT5640_AUTO_PD_SFT
- RT5640_BASE_BACK
- RT5640_BB_CT_A
- RT5640_BB_CT_B
- RT5640_BB_CT_C
- RT5640_BB_CT_D
- RT5640_BB_CT_MASK
- RT5640_BB_CT_SFT
- RT5640_BB_DIS
- RT5640_BB_EN
- RT5640_BB_MASK
- RT5640_BB_SFT
- RT5640_BIAS_CUR4
- RT5640_BPS_DIS
- RT5640_BPS_EN
- RT5640_BPS_MASK
- RT5640_BPS_SFT
- RT5640_BREEZE
- RT5640_BST_SFT1
- RT5640_BST_SFT2
- RT5640_CAL_DIS
- RT5640_CAL_EN
- RT5640_CAL_MASK
- RT5640_CAL_M_CAL
- RT5640_CAL_M_DEP
- RT5640_CAL_M_MASK
- RT5640_CAL_M_SFT
- RT5640_CAL_P_CAL
- RT5640_CAL_P_DAC_CAL
- RT5640_CAL_P_MASK
- RT5640_CAL_P_NONE
- RT5640_CAL_P_SFT
- RT5640_CAL_SFT
- RT5640_CAL_TEST_DIS
- RT5640_CAL_TEST_EN
- RT5640_CAL_TEST_MASK
- RT5640_CAL_TEST_SFT
- RT5640_CHARGE_PUMP
- RT5640_CHPUMP_INT_REG1
- RT5640_CLK_SEL_ASRC
- RT5640_CLK_SEL_SYS
- RT5640_CLSD_OC_MASK
- RT5640_CLSD_OC_PD
- RT5640_CLSD_OC_PU
- RT5640_CLSD_OC_SFT
- RT5640_CLSD_OC_TH_MASK
- RT5640_CLSD_OC_TH_SFT
- RT5640_CLSD_OM_MASK
- RT5640_CLSD_OM_MONO
- RT5640_CLSD_OM_SFT
- RT5640_CLSD_OM_STO
- RT5640_CLSD_RATIO_MASK
- RT5640_CLSD_RATIO_SFT
- RT5640_CLSD_SCH_L
- RT5640_CLSD_SCH_MASK
- RT5640_CLSD_SCH_S
- RT5640_CLSD_SCH_SFT
- RT5640_CLS_D_OUT
- RT5640_CLS_D_OVCD
- RT5640_CLS_D_OVCD_STATUS
- RT5640_CP_FQ1_MASK
- RT5640_CP_FQ1_SFT
- RT5640_CP_FQ2_MASK
- RT5640_CP_FQ2_SFT
- RT5640_CP_FQ3_MASK
- RT5640_CP_FQ3_SFT
- RT5640_CP_FQ_12_KHZ
- RT5640_CP_FQ_192_KHZ
- RT5640_CP_FQ_1_5_KHZ
- RT5640_CP_FQ_24_KHZ
- RT5640_CP_FQ_3_KHZ
- RT5640_CP_FQ_48_KHZ
- RT5640_CP_FQ_6_KHZ
- RT5640_CP_FQ_96_KHZ
- RT5640_CP_SYS_MASK
- RT5640_CP_SYS_SFT
- RT5640_DAC1_DIG_VOL
- RT5640_DAC2_CTRL
- RT5640_DAC2_DIG_VOL
- RT5640_DAC_L1_MONO_L_VOL_MASK
- RT5640_DAC_L1_MONO_L_VOL_SFT
- RT5640_DAC_L1_STO_L_VOL_MASK
- RT5640_DAC_L1_STO_L_VOL_SFT
- RT5640_DAC_L1_VOL_MASK
- RT5640_DAC_L1_VOL_SFT
- RT5640_DAC_L2_DAC_L_VOL_MASK
- RT5640_DAC_L2_DAC_L_VOL_SFT
- RT5640_DAC_L2_MONO_L_VOL_MASK
- RT5640_DAC_L2_MONO_L_VOL_SFT
- RT5640_DAC_L2_MONO_R_VOL_MASK
- RT5640_DAC_L2_MONO_R_VOL_SFT
- RT5640_DAC_L2_SEL_BASS
- RT5640_DAC_L2_SEL_IF2
- RT5640_DAC_L2_SEL_IF3
- RT5640_DAC_L2_SEL_MASK
- RT5640_DAC_L2_SEL_SFT
- RT5640_DAC_L2_SEL_TXDC
- RT5640_DAC_L2_STO_L_VOL_MASK
- RT5640_DAC_L2_STO_L_VOL_SFT
- RT5640_DAC_L2_VOL_MASK
- RT5640_DAC_L2_VOL_SFT
- RT5640_DAC_L_OSR_128
- RT5640_DAC_L_OSR_16
- RT5640_DAC_L_OSR_32
- RT5640_DAC_L_OSR_64
- RT5640_DAC_L_OSR_MASK
- RT5640_DAC_L_OSR_SFT
- RT5640_DAC_OSR_128
- RT5640_DAC_OSR_16
- RT5640_DAC_OSR_32
- RT5640_DAC_OSR_64
- RT5640_DAC_OSR_MASK
- RT5640_DAC_OSR_SFT
- RT5640_DAC_R1_MONO_R_VOL_MASK
- RT5640_DAC_R1_MONO_R_VOL_SFT
- RT5640_DAC_R1_STO_R_VOL_MASK
- RT5640_DAC_R1_STO_R_VOL_SFT
- RT5640_DAC_R1_VOL_MASK
- RT5640_DAC_R1_VOL_SFT
- RT5640_DAC_R2_DAC_R_VOL_MASK
- RT5640_DAC_R2_DAC_R_VOL_SFT
- RT5640_DAC_R2_MONO_L_VOL_MASK
- RT5640_DAC_R2_MONO_L_VOL_SFT
- RT5640_DAC_R2_MONO_R_VOL_MASK
- RT5640_DAC_R2_MONO_R_VOL_SFT
- RT5640_DAC_R2_SEL_IF2
- RT5640_DAC_R2_SEL_IF3
- RT5640_DAC_R2_SEL_MASK
- RT5640_DAC_R2_SEL_SFT
- RT5640_DAC_R2_SEL_TXDC
- RT5640_DAC_R2_STO_R_VOL_MASK
- RT5640_DAC_R2_STO_R_VOL_SFT
- RT5640_DAC_R2_VOL_MASK
- RT5640_DAC_R2_VOL_SFT
- RT5640_DAHPF_EN
- RT5640_DAHPF_EN_SFT
- RT5640_DA_MONO_L_FILTER
- RT5640_DA_MONO_R_FILTER
- RT5640_DA_STEREO_FILTER
- RT5640_DC_CAL_DIS
- RT5640_DC_CAL_EN
- RT5640_DC_CAL_MASK
- RT5640_DC_CAL_M_CAL
- RT5640_DC_CAL_M_MASK
- RT5640_DC_CAL_M_NOR
- RT5640_DC_CAL_M_SFT
- RT5640_DC_CAL_SFT
- RT5640_DEPOP_AUTO
- RT5640_DEPOP_M1
- RT5640_DEPOP_M2
- RT5640_DEPOP_M3
- RT5640_DEPOP_MAN
- RT5640_DEPOP_MASK
- RT5640_DEPOP_SFT
- RT5640_DEVICE_ID
- RT5640_DIG_DP_DIS
- RT5640_DIG_DP_EN
- RT5640_DIG_DP_MASK
- RT5640_DIG_DP_SFT
- RT5640_DIG_INF_DATA
- RT5640_DIG_MIXER
- RT5640_DIP_SPK_INF
- RT5640_DMIC
- RT5640_DMIC1
- RT5640_DMIC1_DATA_PIN_GPIO3
- RT5640_DMIC1_DATA_PIN_IN1P
- RT5640_DMIC1_DATA_PIN_NONE
- RT5640_DMIC2
- RT5640_DMIC2_DATA_PIN_GPIO4
- RT5640_DMIC2_DATA_PIN_IN1N
- RT5640_DMIC2_DATA_PIN_NONE
- RT5640_DMIC_1L_LH_FALLING
- RT5640_DMIC_1L_LH_MASK
- RT5640_DMIC_1L_LH_RISING
- RT5640_DMIC_1L_LH_SFT
- RT5640_DMIC_1R_LH_FALLING
- RT5640_DMIC_1R_LH_MASK
- RT5640_DMIC_1R_LH_RISING
- RT5640_DMIC_1R_LH_SFT
- RT5640_DMIC_1_DIS
- RT5640_DMIC_1_DP_GPIO3
- RT5640_DMIC_1_DP_IN1P
- RT5640_DMIC_1_DP_MASK
- RT5640_DMIC_1_DP_SFT
- RT5640_DMIC_1_EN
- RT5640_DMIC_1_EN_MASK
- RT5640_DMIC_1_EN_SFT
- RT5640_DMIC_1_M_ASYN
- RT5640_DMIC_1_M_MASK
- RT5640_DMIC_1_M_NOR
- RT5640_DMIC_1_M_SFT
- RT5640_DMIC_2L_LH_FALLING
- RT5640_DMIC_2L_LH_MASK
- RT5640_DMIC_2L_LH_RISING
- RT5640_DMIC_2L_LH_SFT
- RT5640_DMIC_2R_LH_FALLING
- RT5640_DMIC_2R_LH_MASK
- RT5640_DMIC_2R_LH_RISING
- RT5640_DMIC_2R_LH_SFT
- RT5640_DMIC_2_DIS
- RT5640_DMIC_2_DP_GPIO4
- RT5640_DMIC_2_DP_IN1N
- RT5640_DMIC_2_DP_MASK
- RT5640_DMIC_2_DP_SFT
- RT5640_DMIC_2_EN
- RT5640_DMIC_2_EN_MASK
- RT5640_DMIC_2_EN_SFT
- RT5640_DMIC_2_M_ASYN
- RT5640_DMIC_2_M_MASK
- RT5640_DMIC_2_M_NOR
- RT5640_DMIC_2_M_SFT
- RT5640_DMIC_CLK_MASK
- RT5640_DMIC_CLK_SFT
- RT5640_DMIC_DIS
- RT5640_DP_ATT_MASK
- RT5640_DP_ATT_SFT
- RT5640_DP_SIG_AP
- RT5640_DP_SIG_MASK
- RT5640_DP_SIG_SFT
- RT5640_DP_SIG_TEST
- RT5640_DP_SPK_DIS
- RT5640_DP_SPK_EN
- RT5640_DP_SPK_MASK
- RT5640_DP_SPK_SFT
- RT5640_DP_TH_MASK
- RT5640_DP_TH_SFT
- RT5640_DRC_AGC_1
- RT5640_DRC_AGC_2
- RT5640_DRC_AGC_3
- RT5640_DRC_AGC_AR_MASK
- RT5640_DRC_AGC_AR_SFT
- RT5640_DRC_AGC_CPR_1_1
- RT5640_DRC_AGC_CPR_1_2
- RT5640_DRC_AGC_CPR_1_3
- RT5640_DRC_AGC_CPR_1_4
- RT5640_DRC_AGC_CPR_MASK
- RT5640_DRC_AGC_CPR_SFT
- RT5640_DRC_AGC_CP_DIS
- RT5640_DRC_AGC_CP_EN
- RT5640_DRC_AGC_CP_MASK
- RT5640_DRC_AGC_CP_SFT
- RT5640_DRC_AGC_DIS
- RT5640_DRC_AGC_EN
- RT5640_DRC_AGC_MASK
- RT5640_DRC_AGC_NGB_MASK
- RT5640_DRC_AGC_NGB_SFT
- RT5640_DRC_AGC_NGH_DIS
- RT5640_DRC_AGC_NGH_EN
- RT5640_DRC_AGC_NGH_MASK
- RT5640_DRC_AGC_NGH_SFT
- RT5640_DRC_AGC_NGT_MASK
- RT5640_DRC_AGC_NGT_SFT
- RT5640_DRC_AGC_NG_DIS
- RT5640_DRC_AGC_NG_EN
- RT5640_DRC_AGC_NG_MASK
- RT5640_DRC_AGC_NG_SFT
- RT5640_DRC_AGC_POB_MASK
- RT5640_DRC_AGC_POB_SFT
- RT5640_DRC_AGC_PRB_MASK
- RT5640_DRC_AGC_PRB_SFT
- RT5640_DRC_AGC_P_ADC
- RT5640_DRC_AGC_P_DAC
- RT5640_DRC_AGC_P_MASK
- RT5640_DRC_AGC_P_SFT
- RT5640_DRC_AGC_RC_MASK
- RT5640_DRC_AGC_RC_SFT
- RT5640_DRC_AGC_R_1764K
- RT5640_DRC_AGC_R_192K
- RT5640_DRC_AGC_R_441K
- RT5640_DRC_AGC_R_48K
- RT5640_DRC_AGC_R_882K
- RT5640_DRC_AGC_R_96K
- RT5640_DRC_AGC_R_MASK
- RT5640_DRC_AGC_R_SFT
- RT5640_DRC_AGC_SFT
- RT5640_DRC_AGC_TAR_MASK
- RT5640_DRC_AGC_TAR_SFT
- RT5640_DRC_AGC_UPD
- RT5640_DRC_AGC_UPD_BIT
- RT5640_DSP_ADD_SFT
- RT5640_DSP_BUSY_BIT
- RT5640_DSP_BUSY_MASK
- RT5640_DSP_CLK_192K
- RT5640_DSP_CLK_384K
- RT5640_DSP_CLK_64K
- RT5640_DSP_CLK_96K
- RT5640_DSP_CLK_MASK
- RT5640_DSP_CLK_SFT
- RT5640_DSP_CMD_MASK
- RT5640_DSP_CMD_MR
- RT5640_DSP_CMD_MW
- RT5640_DSP_CMD_RR
- RT5640_DSP_CMD_RW
- RT5640_DSP_CMD_SFT
- RT5640_DSP_CTRL1
- RT5640_DSP_CTRL2
- RT5640_DSP_CTRL3
- RT5640_DSP_CTRL4
- RT5640_DSP_DAT_SFT
- RT5640_DSP_DS_FM3010
- RT5640_DSP_DS_MASK
- RT5640_DSP_DS_SFT
- RT5640_DSP_DS_TEMP
- RT5640_DSP_PATH1
- RT5640_DSP_PATH2
- RT5640_DSP_PD_PIN_HI
- RT5640_DSP_PD_PIN_LO
- RT5640_DSP_PD_PIN_MASK
- RT5640_DSP_PD_PIN_SFT
- RT5640_DSP_RST_PIN_HI
- RT5640_DSP_RST_PIN_LO
- RT5640_DSP_RST_PIN_MASK
- RT5640_DSP_RST_PIN_SFT
- RT5640_DSP_R_EN
- RT5640_DSP_R_EN_BIT
- RT5640_DSP_W_EN
- RT5640_DSP_W_EN_BIT
- RT5640_DUMMY1
- RT5640_DUMMY2
- RT5640_DUMMY3
- RT5640_EG_MP3_MASK
- RT5640_EG_MP3_SFT
- RT5640_EQ_BPF1_DIS
- RT5640_EQ_BPF1_EN
- RT5640_EQ_BPF1_MASK
- RT5640_EQ_BPF1_SFT
- RT5640_EQ_BPF2_DIS
- RT5640_EQ_BPF2_EN
- RT5640_EQ_BPF2_MASK
- RT5640_EQ_BPF2_SFT
- RT5640_EQ_BPF3_DIS
- RT5640_EQ_BPF3_EN
- RT5640_EQ_BPF3_MASK
- RT5640_EQ_BPF3_SFT
- RT5640_EQ_BPF4_DIS
- RT5640_EQ_BPF4_EN
- RT5640_EQ_BPF4_MASK
- RT5640_EQ_BPF4_SFT
- RT5640_EQ_BW_BP1
- RT5640_EQ_BW_BP2
- RT5640_EQ_BW_BP3
- RT5640_EQ_BW_BP4
- RT5640_EQ_BW_HIP2
- RT5640_EQ_BW_LOP
- RT5640_EQ_CD_DIS
- RT5640_EQ_CD_EN
- RT5640_EQ_CD_MASK
- RT5640_EQ_CD_SFT
- RT5640_EQ_CTRL1
- RT5640_EQ_CTRL2
- RT5640_EQ_DITH_LSB
- RT5640_EQ_DITH_LSB_1
- RT5640_EQ_DITH_LSB_2
- RT5640_EQ_DITH_MASK
- RT5640_EQ_DITH_NOR
- RT5640_EQ_DITH_SFT
- RT5640_EQ_FC_BP1
- RT5640_EQ_FC_BP2
- RT5640_EQ_FC_BP3
- RT5640_EQ_FC_BP4
- RT5640_EQ_FC_HIP1
- RT5640_EQ_FC_HIP2
- RT5640_EQ_GN_BP1
- RT5640_EQ_GN_BP2
- RT5640_EQ_GN_BP3
- RT5640_EQ_GN_BP4
- RT5640_EQ_GN_HIP1
- RT5640_EQ_GN_HIP2
- RT5640_EQ_GN_LOP
- RT5640_EQ_HPF1_DIS
- RT5640_EQ_HPF1_EN
- RT5640_EQ_HPF1_MASK
- RT5640_EQ_HPF1_M_1ST
- RT5640_EQ_HPF1_M_HI
- RT5640_EQ_HPF1_M_MASK
- RT5640_EQ_HPF1_M_SFT
- RT5640_EQ_HPF1_SFT
- RT5640_EQ_HPF2_DIS
- RT5640_EQ_HPF2_EN
- RT5640_EQ_HPF2_MASK
- RT5640_EQ_HPF2_SFT
- RT5640_EQ_LPF1_M_1ST
- RT5640_EQ_LPF1_M_LO
- RT5640_EQ_LPF1_M_MASK
- RT5640_EQ_LPF1_M_SFT
- RT5640_EQ_LPF_DIS
- RT5640_EQ_LPF_EN
- RT5640_EQ_LPF_MASK
- RT5640_EQ_LPF_SFT
- RT5640_EQ_PRE_VOL
- RT5640_EQ_PRE_VOL_MASK
- RT5640_EQ_PRE_VOL_SFT
- RT5640_EQ_PST_VOL
- RT5640_EQ_PST_VOL_MASK
- RT5640_EQ_PST_VOL_SFT
- RT5640_EQ_SRC_ADC
- RT5640_EQ_SRC_DAC
- RT5640_EQ_SRC_MASK
- RT5640_EQ_SRC_SFT
- RT5640_EQ_UPD
- RT5640_EQ_UPD_BIT
- RT5640_FAST_UPDN_DIS
- RT5640_FAST_UPDN_EN
- RT5640_FAST_UPDN_MASK
- RT5640_FAST_UPDN_SFT
- RT5640_FORMATS
- RT5640_GLB_CLK
- RT5640_GP1_OUT_HI
- RT5640_GP1_OUT_LO
- RT5640_GP1_OUT_MASK
- RT5640_GP1_OUT_SFT
- RT5640_GP1_PF_IN
- RT5640_GP1_PF_MASK
- RT5640_GP1_PF_OUT
- RT5640_GP1_PF_SFT
- RT5640_GP1_PIN_GPIO1
- RT5640_GP1_PIN_IRQ
- RT5640_GP1_PIN_MASK
- RT5640_GP1_PIN_SFT
- RT5640_GP1_P_INV
- RT5640_GP1_P_MASK
- RT5640_GP1_P_NOR
- RT5640_GP1_P_SFT
- RT5640_GP2_OUT_HI
- RT5640_GP2_OUT_LO
- RT5640_GP2_OUT_MASK
- RT5640_GP2_OUT_SFT
- RT5640_GP2_PF_IN
- RT5640_GP2_PF_MASK
- RT5640_GP2_PF_OUT
- RT5640_GP2_PF_SFT
- RT5640_GP2_PIN_DMIC1_SCL
- RT5640_GP2_PIN_GPIO2
- RT5640_GP2_PIN_MASK
- RT5640_GP2_PIN_SFT
- RT5640_GP2_P_INV
- RT5640_GP2_P_MASK
- RT5640_GP2_P_NOR
- RT5640_GP2_P_SFT
- RT5640_GP3_OUT_HI
- RT5640_GP3_OUT_LO
- RT5640_GP3_OUT_MASK
- RT5640_GP3_OUT_SFT
- RT5640_GP3_PF_IN
- RT5640_GP3_PF_MASK
- RT5640_GP3_PF_OUT
- RT5640_GP3_PF_SFT
- RT5640_GP3_PIN_DMIC1_SDA
- RT5640_GP3_PIN_GPIO3
- RT5640_GP3_PIN_IRQ
- RT5640_GP3_PIN_MASK
- RT5640_GP3_PIN_SFT
- RT5640_GP3_P_INV
- RT5640_GP3_P_MASK
- RT5640_GP3_P_NOR
- RT5640_GP3_P_SFT
- RT5640_GP4_OUT_HI
- RT5640_GP4_OUT_LO
- RT5640_GP4_OUT_MASK
- RT5640_GP4_OUT_SFT
- RT5640_GP4_PF_IN
- RT5640_GP4_PF_MASK
- RT5640_GP4_PF_OUT
- RT5640_GP4_PF_SFT
- RT5640_GP4_PIN_DMIC2_SDA
- RT5640_GP4_PIN_GPIO4
- RT5640_GP4_PIN_MASK
- RT5640_GP4_PIN_SFT
- RT5640_GP4_P_INV
- RT5640_GP4_P_MASK
- RT5640_GP4_P_NOR
- RT5640_GP4_P_SFT
- RT5640_GPIO1_STATUS
- RT5640_GPIO2_STATUS
- RT5640_GPIO_CTRL1
- RT5640_GPIO_CTRL2
- RT5640_GPIO_CTRL3
- RT5640_GPIO_M_FLT
- RT5640_GPIO_M_MASK
- RT5640_GPIO_M_PH
- RT5640_GPIO_M_SFT
- RT5640_G_BB_BST_MASK
- RT5640_G_BB_BST_SFT
- RT5640_G_BST1_OM_L_MASK
- RT5640_G_BST1_OM_L_SFT
- RT5640_G_BST1_OM_R_MASK
- RT5640_G_BST1_OM_R_SFT
- RT5640_G_BST1_RM_L_MASK
- RT5640_G_BST1_RM_L_SFT
- RT5640_G_BST1_RM_R_MASK
- RT5640_G_BST1_RM_R_SFT
- RT5640_G_BST2_OM_L_MASK
- RT5640_G_BST2_OM_L_SFT
- RT5640_G_BST2_OM_R_MASK
- RT5640_G_BST2_OM_R_SFT
- RT5640_G_BST2_RM_L_MASK
- RT5640_G_BST2_RM_L_SFT
- RT5640_G_BST2_RM_R_MASK
- RT5640_G_BST2_RM_R_SFT
- RT5640_G_BST3_OM_L_MASK
- RT5640_G_BST3_OM_L_SFT
- RT5640_G_BST3_RM_L_MASK
- RT5640_G_BST3_RM_L_SFT
- RT5640_G_BST3_RM_R_MASK
- RT5640_G_BST3_RM_R_SFT
- RT5640_G_BST4_OM_R_MASK
- RT5640_G_BST4_OM_R_SFT
- RT5640_G_BST4_RM_L_MASK
- RT5640_G_BST4_RM_L_SFT
- RT5640_G_BST4_RM_R_MASK
- RT5640_G_BST4_RM_R_SFT
- RT5640_G_DAC_L1_OM_L_MASK
- RT5640_G_DAC_L1_OM_L_SFT
- RT5640_G_DAC_L1_SM_L_MASK
- RT5640_G_DAC_L1_SM_L_SFT
- RT5640_G_DAC_L2_OM_L_MASK
- RT5640_G_DAC_L2_OM_L_SFT
- RT5640_G_DAC_L2_OM_R_MASK
- RT5640_G_DAC_L2_OM_R_SFT
- RT5640_G_DAC_L2_SM_L_MASK
- RT5640_G_DAC_L2_SM_L_SFT
- RT5640_G_DAC_R1_OM_R_MASK
- RT5640_G_DAC_R1_OM_R_SFT
- RT5640_G_DAC_R1_SM_R_MASK
- RT5640_G_DAC_R1_SM_R_SFT
- RT5640_G_DAC_R2_OM_L_MASK
- RT5640_G_DAC_R2_OM_L_SFT
- RT5640_G_DAC_R2_OM_R_MASK
- RT5640_G_DAC_R2_OM_R_SFT
- RT5640_G_DAC_R2_SM_R_MASK
- RT5640_G_DAC_R2_SM_R_SFT
- RT5640_G_HPOMIX_MASK
- RT5640_G_HPOMIX_SFT
- RT5640_G_HP_L_RM_L_MASK
- RT5640_G_HP_L_RM_L_SFT
- RT5640_G_HP_R_RM_R_MASK
- RT5640_G_HP_R_RM_R_SFT
- RT5640_G_IN_L_OM_L_MASK
- RT5640_G_IN_L_OM_L_SFT
- RT5640_G_IN_L_RM_L_MASK
- RT5640_G_IN_L_RM_L_SFT
- RT5640_G_IN_L_SM_L_MASK
- RT5640_G_IN_L_SM_L_SFT
- RT5640_G_IN_R_OM_R_MASK
- RT5640_G_IN_R_OM_R_SFT
- RT5640_G_IN_R_RM_R_MASK
- RT5640_G_IN_R_RM_R_SFT
- RT5640_G_IN_R_SM_R_MASK
- RT5640_G_IN_R_SM_R_SFT
- RT5640_G_LOUTMIX_MASK
- RT5640_G_LOUTMIX_SFT
- RT5640_G_MONOMIX_MASK
- RT5640_G_MONOMIX_SFT
- RT5640_G_OM_L_RM_L_MASK
- RT5640_G_OM_L_RM_L_SFT
- RT5640_G_OM_L_SM_L_MASK
- RT5640_G_OM_L_SM_L_SFT
- RT5640_G_OM_R_RM_R_MASK
- RT5640_G_OM_R_RM_R_SFT
- RT5640_G_OM_R_SM_R_MASK
- RT5640_G_OM_R_SM_R_SFT
- RT5640_G_RM_L_OM_L_MASK
- RT5640_G_RM_L_OM_L_SFT
- RT5640_G_RM_L_SM_L_MASK
- RT5640_G_RM_L_SM_L_SFT
- RT5640_G_RM_R_OM_R_MASK
- RT5640_G_RM_R_OM_R_SFT
- RT5640_G_RM_R_SM_R_MASK
- RT5640_G_RM_R_SM_R_SFT
- RT5640_HEADPHO_DET
- RT5640_HEADSET_DET
- RT5640_HG_MP3_MASK
- RT5640_HG_MP3_SFT
- RT5640_HPD_PS_DIS
- RT5640_HPD_PS_EN
- RT5640_HPD_PS_MASK
- RT5640_HPD_PS_SFT
- RT5640_HPD_RCV_MASK
- RT5640_HPD_RCV_SFT
- RT5640_HPF_CF_L_MASK
- RT5640_HPF_CF_L_SFT
- RT5640_HPF_CF_R_MASK
- RT5640_HPF_CF_R_SFT
- RT5640_HPF_FC_MASK
- RT5640_HPF_FC_SFT
- RT5640_HPO_MIXER
- RT5640_HP_CALIB2
- RT5640_HP_CALIB_AMP_DET
- RT5640_HP_CB_MASK
- RT5640_HP_CB_PD
- RT5640_HP_CB_PU
- RT5640_HP_CB_SFT
- RT5640_HP_CD_PD_DIS
- RT5640_HP_CD_PD_EN
- RT5640_HP_CD_PD_MASK
- RT5640_HP_CD_PD_SFT
- RT5640_HP_CO_DIS
- RT5640_HP_CO_EN
- RT5640_HP_CO_MASK
- RT5640_HP_CO_SFT
- RT5640_HP_CP_MASK
- RT5640_HP_CP_PD
- RT5640_HP_CP_PU
- RT5640_HP_CP_SFT
- RT5640_HP_DCC_INT1
- RT5640_HP_DP_MASK
- RT5640_HP_DP_PD
- RT5640_HP_DP_PU
- RT5640_HP_DP_SFT
- RT5640_HP_L_SMT_DIS
- RT5640_HP_L_SMT_EN
- RT5640_HP_L_SMT_MASK
- RT5640_HP_L_SMT_SFT
- RT5640_HP_OC_TH_105
- RT5640_HP_OC_TH_120
- RT5640_HP_OC_TH_135
- RT5640_HP_OC_TH_90
- RT5640_HP_OC_TH_MASK
- RT5640_HP_OC_TH_SFT
- RT5640_HP_OVCD
- RT5640_HP_OVCD_DIS
- RT5640_HP_OVCD_EN
- RT5640_HP_OVCD_MASK
- RT5640_HP_OVCD_SFT
- RT5640_HP_R_SMT_DIS
- RT5640_HP_R_SMT_EN
- RT5640_HP_R_SMT_MASK
- RT5640_HP_R_SMT_SFT
- RT5640_HP_SG_DIS
- RT5640_HP_SG_EN
- RT5640_HP_SG_MASK
- RT5640_HP_SG_SFT
- RT5640_HP_SV_DIS
- RT5640_HP_SV_EN
- RT5640_HP_SV_MASK
- RT5640_HP_SV_SFT
- RT5640_HP_VOL
- RT5640_I2S1_PD_MASK
- RT5640_I2S1_PD_SFT
- RT5640_I2S1_RATE_MASK
- RT5640_I2S1_RATE_SFT
- RT5640_I2S1_R_D_DIS
- RT5640_I2S1_R_D_EN
- RT5640_I2S1_R_D_MASK
- RT5640_I2S1_R_D_SFT
- RT5640_I2S1_SDP
- RT5640_I2S2_F_I2S1_TCLK
- RT5640_I2S2_F_I2S2_D2
- RT5640_I2S2_F_MASK
- RT5640_I2S2_F_SFT
- RT5640_I2S2_PD_MASK
- RT5640_I2S2_PD_SFT
- RT5640_I2S2_RATE_MASK
- RT5640_I2S2_RATE_SFT
- RT5640_I2S2_R_D_DIS
- RT5640_I2S2_R_D_EN
- RT5640_I2S2_R_D_MASK
- RT5640_I2S2_R_D_SFT
- RT5640_I2S2_SDI_I2S1
- RT5640_I2S2_SDI_I2S2
- RT5640_I2S2_SDI_MASK
- RT5640_I2S2_SDI_SFT
- RT5640_I2S2_SDP
- RT5640_I2S_BCLK_MS1_32
- RT5640_I2S_BCLK_MS1_64
- RT5640_I2S_BCLK_MS1_MASK
- RT5640_I2S_BCLK_MS1_SFT
- RT5640_I2S_BCLK_MS2_32
- RT5640_I2S_BCLK_MS2_64
- RT5640_I2S_BCLK_MS2_MASK
- RT5640_I2S_BCLK_MS2_SFT
- RT5640_I2S_BCLK_MS3_32
- RT5640_I2S_BCLK_MS3_64
- RT5640_I2S_BCLK_MS3_MASK
- RT5640_I2S_BCLK_MS3_SFT
- RT5640_I2S_BP_INV
- RT5640_I2S_BP_MASK
- RT5640_I2S_BP_NOR
- RT5640_I2S_BP_SFT
- RT5640_I2S_DF_I2S
- RT5640_I2S_DF_LEFT
- RT5640_I2S_DF_MASK
- RT5640_I2S_DF_PCM_A
- RT5640_I2S_DF_PCM_B
- RT5640_I2S_DF_SFT
- RT5640_I2S_DL_16
- RT5640_I2S_DL_20
- RT5640_I2S_DL_24
- RT5640_I2S_DL_8
- RT5640_I2S_DL_MASK
- RT5640_I2S_DL_SFT
- RT5640_I2S_IF_MASK
- RT5640_I2S_IF_SFT
- RT5640_I2S_I_CP_A_LAW
- RT5640_I2S_I_CP_MASK
- RT5640_I2S_I_CP_OFF
- RT5640_I2S_I_CP_SFT
- RT5640_I2S_I_CP_U_LAW
- RT5640_I2S_MS_M
- RT5640_I2S_MS_MASK
- RT5640_I2S_MS_S
- RT5640_I2S_MS_SFT
- RT5640_I2S_O_CP_A_LAW
- RT5640_I2S_O_CP_MASK
- RT5640_I2S_O_CP_OFF
- RT5640_I2S_O_CP_SFT
- RT5640_I2S_O_CP_U_LAW
- RT5640_I2S_PD1_1
- RT5640_I2S_PD1_12
- RT5640_I2S_PD1_16
- RT5640_I2S_PD1_2
- RT5640_I2S_PD1_3
- RT5640_I2S_PD1_4
- RT5640_I2S_PD1_6
- RT5640_I2S_PD1_8
- RT5640_I2S_PD1_MASK
- RT5640_I2S_PD1_SFT
- RT5640_I2S_PD2_1
- RT5640_I2S_PD2_12
- RT5640_I2S_PD2_16
- RT5640_I2S_PD2_2
- RT5640_I2S_PD2_3
- RT5640_I2S_PD2_4
- RT5640_I2S_PD2_6
- RT5640_I2S_PD2_8
- RT5640_I2S_PD2_MASK
- RT5640_I2S_PD2_SFT
- RT5640_I2S_PD3_1
- RT5640_I2S_PD3_12
- RT5640_I2S_PD3_16
- RT5640_I2S_PD3_2
- RT5640_I2S_PD3_3
- RT5640_I2S_PD3_4
- RT5640_I2S_PD3_6
- RT5640_I2S_PD3_8
- RT5640_I2S_PD3_MASK
- RT5640_I2S_PD3_SFT
- RT5640_IB_HP_125IL
- RT5640_IB_HP_1IL
- RT5640_IB_HP_25IL
- RT5640_IB_HP_5IL
- RT5640_IB_HP_MASK
- RT5640_IB_HP_SFT
- RT5640_ID_5639
- RT5640_ID_5640
- RT5640_ID_5642
- RT5640_ID_MASK
- RT5640_IF1_ADC_SEL_L2R
- RT5640_IF1_ADC_SEL_MASK
- RT5640_IF1_ADC_SEL_NOR
- RT5640_IF1_ADC_SEL_R2L
- RT5640_IF1_ADC_SEL_SFT
- RT5640_IF1_ADC_SEL_SWAP
- RT5640_IF1_DAC_SEL_L2R
- RT5640_IF1_DAC_SEL_MASK
- RT5640_IF1_DAC_SEL_NOR
- RT5640_IF1_DAC_SEL_R2L
- RT5640_IF1_DAC_SEL_SFT
- RT5640_IF1_DAC_SEL_SWAP
- RT5640_IF2_ADC_L_SEL_MASK
- RT5640_IF2_ADC_L_SEL_PASS
- RT5640_IF2_ADC_L_SEL_SFT
- RT5640_IF2_ADC_L_SEL_TXDP
- RT5640_IF2_ADC_R_SEL_MASK
- RT5640_IF2_ADC_R_SEL_PASS
- RT5640_IF2_ADC_R_SEL_SFT
- RT5640_IF2_ADC_R_SEL_TXDP
- RT5640_IF2_ADC_SEL_L2R
- RT5640_IF2_ADC_SEL_MASK
- RT5640_IF2_ADC_SEL_NOR
- RT5640_IF2_ADC_SEL_R2L
- RT5640_IF2_ADC_SEL_SFT
- RT5640_IF2_ADC_SEL_SWAP
- RT5640_IF2_DAC_SEL_L2R
- RT5640_IF2_DAC_SEL_MASK
- RT5640_IF2_DAC_SEL_NOR
- RT5640_IF2_DAC_SEL_R2L
- RT5640_IF2_DAC_SEL_SFT
- RT5640_IF2_DAC_SEL_SWAP
- RT5640_IF3_ADC_SEL_L2R
- RT5640_IF3_ADC_SEL_MASK
- RT5640_IF3_ADC_SEL_NOR
- RT5640_IF3_ADC_SEL_R2L
- RT5640_IF3_ADC_SEL_SFT
- RT5640_IF3_ADC_SEL_SWAP
- RT5640_IF3_DAC_SEL_L2R
- RT5640_IF3_DAC_SEL_MASK
- RT5640_IF3_DAC_SEL_NOR
- RT5640_IF3_DAC_SEL_R2L
- RT5640_IF3_DAC_SEL_SFT
- RT5640_IF3_DAC_SEL_SWAP
- RT5640_IF_113
- RT5640_IF_123
- RT5640_IF_132
- RT5640_IF_213
- RT5640_IF_223
- RT5640_IF_231
- RT5640_IF_312
- RT5640_IF_321
- RT5640_IF_ALL
- RT5640_IN1_IN2
- RT5640_IN3_IN4
- RT5640_INL_INR_VOL
- RT5640_INL_SEL_IN4P
- RT5640_INL_SEL_MASK
- RT5640_INL_SEL_MONOP
- RT5640_INL_SEL_SFT
- RT5640_INL_VOL_MASK
- RT5640_INL_VOL_SFT
- RT5640_INR_SEL_IN4N
- RT5640_INR_SEL_MASK
- RT5640_INR_SEL_MONON
- RT5640_INR_SEL_SFT
- RT5640_INR_VOL_MASK
- RT5640_INR_VOL_SFT
- RT5640_INT_IRQ_ST
- RT5640_IN_DF1
- RT5640_IN_DF2
- RT5640_IN_SFT1
- RT5640_IN_SFT2
- RT5640_IRQ_CTRL1
- RT5640_IRQ_CTRL2
- RT5640_IRQ_JD_BP
- RT5640_IRQ_JD_MASK
- RT5640_IRQ_JD_NOR
- RT5640_IRQ_JD_SFT
- RT5640_IRQ_MB1_OC_BP
- RT5640_IRQ_MB1_OC_MASK
- RT5640_IRQ_MB1_OC_NOR
- RT5640_IRQ_MB1_OC_SFT
- RT5640_IRQ_MB2_OC_BP
- RT5640_IRQ_MB2_OC_MASK
- RT5640_IRQ_MB2_OC_NOR
- RT5640_IRQ_MB2_OC_SFT
- RT5640_IRQ_OT_BP
- RT5640_IRQ_OT_MASK
- RT5640_IRQ_OT_NOR
- RT5640_IRQ_OT_SFT
- RT5640_JD1_IN4P_DIS
- RT5640_JD1_IN4P_EN
- RT5640_JD1_IN4P_MASK
- RT5640_JD1_IN4P_SFT
- RT5640_JD2_IN4N_DIS
- RT5640_JD2_IN4N_EN
- RT5640_JD2_IN4N_MASK
- RT5640_JD2_IN4N_SFT
- RT5640_JD_CTRL
- RT5640_JD_DIS
- RT5640_JD_GPIO1
- RT5640_JD_GPIO2
- RT5640_JD_GPIO3
- RT5640_JD_GPIO4
- RT5640_JD_HP_DIS
- RT5640_JD_HP_EN
- RT5640_JD_HP_MASK
- RT5640_JD_HP_SFT
- RT5640_JD_HP_TRG_HI
- RT5640_JD_HP_TRG_LO
- RT5640_JD_HP_TRG_MASK
- RT5640_JD_HP_TRG_SFT
- RT5640_JD_JD1_IN4P
- RT5640_JD_JD2_IN4N
- RT5640_JD_LO_DIS
- RT5640_JD_LO_EN
- RT5640_JD_LO_MASK
- RT5640_JD_LO_SFT
- RT5640_JD_LO_TRG_HI
- RT5640_JD_LO_TRG_LO
- RT5640_JD_LO_TRG_MASK
- RT5640_JD_LO_TRG_SFT
- RT5640_JD_MASK
- RT5640_JD_MO_DIS
- RT5640_JD_MO_EN
- RT5640_JD_MO_MASK
- RT5640_JD_MO_SFT
- RT5640_JD_MO_TRG_HI
- RT5640_JD_MO_TRG_LO
- RT5640_JD_MO_TRG_MASK
- RT5640_JD_MO_TRG_SFT
- RT5640_JD_P_INV
- RT5640_JD_P_MASK
- RT5640_JD_P_NOR
- RT5640_JD_P_SFT
- RT5640_JD_SFT
- RT5640_JD_SPL_DIS
- RT5640_JD_SPL_EN
- RT5640_JD_SPL_MASK
- RT5640_JD_SPL_SFT
- RT5640_JD_SPL_TRG_HI
- RT5640_JD_SPL_TRG_LO
- RT5640_JD_SPL_TRG_MASK
- RT5640_JD_SPL_TRG_SFT
- RT5640_JD_SPR_DIS
- RT5640_JD_SPR_EN
- RT5640_JD_SPR_MASK
- RT5640_JD_SPR_SFT
- RT5640_JD_SPR_TRG_HI
- RT5640_JD_SPR_TRG_LO
- RT5640_JD_SPR_TRG_MASK
- RT5640_JD_SPR_TRG_SFT
- RT5640_JD_SRC_GPIO1
- RT5640_JD_SRC_GPIO2
- RT5640_JD_SRC_GPIO3
- RT5640_JD_SRC_GPIO4
- RT5640_JD_SRC_JD1_IN4P
- RT5640_JD_SRC_JD2_IN4N
- RT5640_JD_STATUS
- RT5640_JD_STKY_DIS
- RT5640_JD_STKY_EN
- RT5640_JD_STKY_MASK
- RT5640_JD_STKY_SFT
- RT5640_LOUT_MIXER
- RT5640_L_MUTE
- RT5640_L_MUTE_SFT
- RT5640_L_VOL_MASK
- RT5640_L_VOL_SFT
- RT5640_M1_T_I2S2
- RT5640_M1_T_I2S2_D3
- RT5640_M1_T_MASK
- RT5640_M1_T_SFT
- RT5640_MAD_L_M_ASYN
- RT5640_MAD_L_M_MASK
- RT5640_MAD_L_M_NOR
- RT5640_MAD_L_M_SFT
- RT5640_MAD_R_M_ASYN
- RT5640_MAD_R_M_MASK
- RT5640_MAD_R_M_NOR
- RT5640_MAD_R_M_SFT
- RT5640_MAMP_INT_REG2
- RT5640_MB1_OC_P_INV
- RT5640_MB1_OC_P_MASK
- RT5640_MB1_OC_P_NOR
- RT5640_MB1_OC_P_SFT
- RT5640_MB1_OC_STATUS
- RT5640_MB1_OC_STATUS_SFT
- RT5640_MB1_OC_STKY_DIS
- RT5640_MB1_OC_STKY_EN
- RT5640_MB1_OC_STKY_MASK
- RT5640_MB1_OC_STKY_SFT
- RT5640_MB2_OC_P_INV
- RT5640_MB2_OC_P_MASK
- RT5640_MB2_OC_P_NOR
- RT5640_MB2_OC_P_SFT
- RT5640_MB2_OC_STATUS
- RT5640_MB2_OC_STATUS_SFT
- RT5640_MB2_OC_STKY_DIS
- RT5640_MB2_OC_STKY_EN
- RT5640_MB2_OC_STKY_MASK
- RT5640_MB2_OC_STKY_SFT
- RT5640_MCLK_DET
- RT5640_MDA_L_M_ASYN
- RT5640_MDA_L_M_MASK
- RT5640_MDA_L_M_NOR
- RT5640_MDA_L_M_SFT
- RT5640_MDA_R_M_ASYN
- RT5640_MDA_R_M_MASK
- RT5640_MDA_R_M_NOR
- RT5640_MDA_R_M_SFT
- RT5640_MIC1_BS_75AV
- RT5640_MIC1_BS_9AV
- RT5640_MIC1_BS_MASK
- RT5640_MIC1_BS_SFT
- RT5640_MIC1_CLK_DIS
- RT5640_MIC1_CLK_EN
- RT5640_MIC1_CLK_MASK
- RT5640_MIC1_CLK_SFT
- RT5640_MIC1_OVCD_DIS
- RT5640_MIC1_OVCD_EN
- RT5640_MIC1_OVCD_MASK
- RT5640_MIC1_OVCD_SFT
- RT5640_MIC1_OVTH_1500UA
- RT5640_MIC1_OVTH_2000UA
- RT5640_MIC1_OVTH_600UA
- RT5640_MIC1_OVTH_MASK
- RT5640_MIC1_OVTH_SFT
- RT5640_MIC2_BS_75AV
- RT5640_MIC2_BS_9AV
- RT5640_MIC2_BS_MASK
- RT5640_MIC2_BS_SFT
- RT5640_MIC2_CLK_DIS
- RT5640_MIC2_CLK_EN
- RT5640_MIC2_CLK_MASK
- RT5640_MIC2_CLK_SFT
- RT5640_MIC2_OVCD_DIS
- RT5640_MIC2_OVCD_EN
- RT5640_MIC2_OVCD_MASK
- RT5640_MIC2_OVCD_SFT
- RT5640_MIC2_OVTH_1500UA
- RT5640_MIC2_OVTH_2000UA
- RT5640_MIC2_OVTH_600UA
- RT5640_MIC2_OVTH_MASK
- RT5640_MIC2_OVTH_SFT
- RT5640_MICBIAS
- RT5640_MIC_OVCD_SF_0P5
- RT5640_MIC_OVCD_SF_0P75
- RT5640_MIC_OVCD_SF_1P0
- RT5640_MIC_OVCD_SF_1P5
- RT5640_MIC_OVCD_SF_MASK
- RT5640_MIC_OVCD_SF_SFT
- RT5640_MONO_ADC_L1_SRC_ADCL
- RT5640_MONO_ADC_L1_SRC_DACMIXL
- RT5640_MONO_ADC_L1_SRC_MASK
- RT5640_MONO_ADC_L1_SRC_SFT
- RT5640_MONO_ADC_L2_SRC_DACMIXL
- RT5640_MONO_ADC_L2_SRC_DMIC_L1
- RT5640_MONO_ADC_L2_SRC_DMIC_L2
- RT5640_MONO_ADC_L2_SRC_MASK
- RT5640_MONO_ADC_L2_SRC_SFT
- RT5640_MONO_ADC_L_VOL_MASK
- RT5640_MONO_ADC_L_VOL_SFT
- RT5640_MONO_ADC_MIXER
- RT5640_MONO_ADC_R1_SRC_ADCR
- RT5640_MONO_ADC_R1_SRC_DACMIXR
- RT5640_MONO_ADC_R1_SRC_MASK
- RT5640_MONO_ADC_R1_SRC_SFT
- RT5640_MONO_ADC_R2_SRC_DACMIXR
- RT5640_MONO_ADC_R2_SRC_DMIC_R1
- RT5640_MONO_ADC_R2_SRC_DMIC_R2
- RT5640_MONO_ADC_R2_SRC_MASK
- RT5640_MONO_ADC_R2_SRC_SFT
- RT5640_MONO_ADC_R_VOL_MASK
- RT5640_MONO_ADC_R_VOL_SFT
- RT5640_MONO_DAC_MIXER
- RT5640_MONO_MIXER
- RT5640_MONO_OUT
- RT5640_MP3_HLP_DIS
- RT5640_MP3_HLP_EN
- RT5640_MP3_HLP_MASK
- RT5640_MP3_HLP_SFT
- RT5640_MP3_PLUS1
- RT5640_MP3_PLUS2
- RT5640_MP3_WT_1_2
- RT5640_MP3_WT_1_4
- RT5640_MP3_WT_MASK
- RT5640_MP3_WT_SFT
- RT5640_MRES_15MO
- RT5640_MRES_25MO
- RT5640_MRES_35MO
- RT5640_MRES_45MO
- RT5640_MRES_MASK
- RT5640_MRES_SFT
- RT5640_MT_DIS
- RT5640_MT_EN
- RT5640_MT_MASK
- RT5640_MT_SFT
- RT5640_M_3D_D2H_MASK
- RT5640_M_3D_D2H_SFT
- RT5640_M_3D_D2R_MASK
- RT5640_M_3D_D2R_SFT
- RT5640_M_3D_HRTF_MASK
- RT5640_M_3D_HRTF_SFT
- RT5640_M_3D_REVB_MASK
- RT5640_M_3D_REVB_SFT
- RT5640_M_ADCMIX_L
- RT5640_M_ADCMIX_L_SFT
- RT5640_M_ADCMIX_R
- RT5640_M_ADCMIX_R_SFT
- RT5640_M_ADC_L1
- RT5640_M_ADC_L1_SFT
- RT5640_M_ADC_L2
- RT5640_M_ADC_L2_SFT
- RT5640_M_ADC_R1
- RT5640_M_ADC_R1_SFT
- RT5640_M_ADC_R2
- RT5640_M_ADC_R2_SFT
- RT5640_M_ANC_DAC_L
- RT5640_M_ANC_DAC_L_SFT
- RT5640_M_ANC_DAC_R
- RT5640_M_ANC_DAC_R_SFT
- RT5640_M_BB_HPF_L_MASK
- RT5640_M_BB_HPF_L_SFT
- RT5640_M_BB_HPF_R_MASK
- RT5640_M_BB_HPF_R_SFT
- RT5640_M_BB_L_MASK
- RT5640_M_BB_L_SFT
- RT5640_M_BB_R_MASK
- RT5640_M_BB_R_SFT
- RT5640_M_BST1_MM
- RT5640_M_BST1_MM_SFT
- RT5640_M_BST1_OM_L
- RT5640_M_BST1_OM_L_SFT
- RT5640_M_BST1_OM_R
- RT5640_M_BST1_OM_R_SFT
- RT5640_M_BST1_RM_L
- RT5640_M_BST1_RM_L_SFT
- RT5640_M_BST1_RM_R
- RT5640_M_BST1_RM_R_SFT
- RT5640_M_BST1_SPM_L
- RT5640_M_BST1_SPM_L_SFT
- RT5640_M_BST1_SPM_R
- RT5640_M_BST1_SPM_R_SFT
- RT5640_M_BST2_OM_L
- RT5640_M_BST2_OM_L_SFT
- RT5640_M_BST2_OM_R
- RT5640_M_BST2_OM_R_SFT
- RT5640_M_BST2_RM_L
- RT5640_M_BST2_RM_L_SFT
- RT5640_M_BST2_RM_R
- RT5640_M_BST2_RM_R_SFT
- RT5640_M_BST3_OM_L
- RT5640_M_BST3_OM_L_SFT
- RT5640_M_BST3_RM_L
- RT5640_M_BST3_RM_L_SFT
- RT5640_M_BST3_RM_R
- RT5640_M_BST3_RM_R_SFT
- RT5640_M_BST4_OM_R
- RT5640_M_BST4_OM_R_SFT
- RT5640_M_BST4_RM_L
- RT5640_M_BST4_RM_L_SFT
- RT5640_M_BST4_RM_R
- RT5640_M_BST4_RM_R_SFT
- RT5640_M_DAC1_HM
- RT5640_M_DAC1_HM_SFT
- RT5640_M_DAC2_HM
- RT5640_M_DAC2_HM_SFT
- RT5640_M_DAC_L1
- RT5640_M_DAC_L1_LM
- RT5640_M_DAC_L1_LM_SFT
- RT5640_M_DAC_L1_MONO_L
- RT5640_M_DAC_L1_MONO_L_SFT
- RT5640_M_DAC_L1_OM_L
- RT5640_M_DAC_L1_OM_L_SFT
- RT5640_M_DAC_L1_SFT
- RT5640_M_DAC_L1_SM_L
- RT5640_M_DAC_L1_SM_L_SFT
- RT5640_M_DAC_L1_SPM_L
- RT5640_M_DAC_L1_SPM_L_SFT
- RT5640_M_DAC_L2
- RT5640_M_DAC_L2_DAC_L
- RT5640_M_DAC_L2_DAC_L_SFT
- RT5640_M_DAC_L2_MM
- RT5640_M_DAC_L2_MM_SFT
- RT5640_M_DAC_L2_MONO_L
- RT5640_M_DAC_L2_MONO_L_SFT
- RT5640_M_DAC_L2_MONO_R
- RT5640_M_DAC_L2_MONO_R_SFT
- RT5640_M_DAC_L2_OM_L
- RT5640_M_DAC_L2_OM_L_SFT
- RT5640_M_DAC_L2_OM_R
- RT5640_M_DAC_L2_OM_R_SFT
- RT5640_M_DAC_L2_SFT
- RT5640_M_DAC_L2_SM_L
- RT5640_M_DAC_L2_SM_L_SFT
- RT5640_M_DAC_L2_VOL
- RT5640_M_DAC_L2_VOL_SFT
- RT5640_M_DAC_R1
- RT5640_M_DAC_R1_LM
- RT5640_M_DAC_R1_LM_SFT
- RT5640_M_DAC_R1_MONO_R
- RT5640_M_DAC_R1_MONO_R_SFT
- RT5640_M_DAC_R1_OM_R
- RT5640_M_DAC_R1_OM_R_SFT
- RT5640_M_DAC_R1_SFT
- RT5640_M_DAC_R1_SM_R
- RT5640_M_DAC_R1_SM_R_SFT
- RT5640_M_DAC_R1_SPM_L
- RT5640_M_DAC_R1_SPM_L_SFT
- RT5640_M_DAC_R1_SPM_R
- RT5640_M_DAC_R1_SPM_R_SFT
- RT5640_M_DAC_R2
- RT5640_M_DAC_R2_DAC_R
- RT5640_M_DAC_R2_DAC_R_SFT
- RT5640_M_DAC_R2_MM
- RT5640_M_DAC_R2_MM_SFT
- RT5640_M_DAC_R2_MONO_L
- RT5640_M_DAC_R2_MONO_L_SFT
- RT5640_M_DAC_R2_MONO_R
- RT5640_M_DAC_R2_MONO_R_SFT
- RT5640_M_DAC_R2_OM_L
- RT5640_M_DAC_R2_OM_L_SFT
- RT5640_M_DAC_R2_OM_R
- RT5640_M_DAC_R2_OM_R_SFT
- RT5640_M_DAC_R2_SFT
- RT5640_M_DAC_R2_SM_R
- RT5640_M_DAC_R2_SM_R_SFT
- RT5640_M_DAC_R2_VOL
- RT5640_M_DAC_R2_VOL_SFT
- RT5640_M_HPVOL_HM
- RT5640_M_HPVOL_HM_SFT
- RT5640_M_HP_L_RM_L
- RT5640_M_HP_L_RM_L_SFT
- RT5640_M_HP_R_RM_R
- RT5640_M_HP_R_RM_R_SFT
- RT5640_M_IF1_DAC_L
- RT5640_M_IF1_DAC_L_SFT
- RT5640_M_IF1_DAC_R
- RT5640_M_IF1_DAC_R_SFT
- RT5640_M_IN_L_OM_L
- RT5640_M_IN_L_OM_L_SFT
- RT5640_M_IN_L_RM_L
- RT5640_M_IN_L_RM_L_SFT
- RT5640_M_IN_L_SM_L
- RT5640_M_IN_L_SM_L_SFT
- RT5640_M_IN_R_OM_R
- RT5640_M_IN_R_OM_R_SFT
- RT5640_M_IN_R_RM_R
- RT5640_M_IN_R_RM_R_SFT
- RT5640_M_IN_R_SM_R
- RT5640_M_IN_R_SM_R_SFT
- RT5640_M_MONO_ADC_L
- RT5640_M_MONO_ADC_L1
- RT5640_M_MONO_ADC_L1_SFT
- RT5640_M_MONO_ADC_L2
- RT5640_M_MONO_ADC_L2_SFT
- RT5640_M_MONO_ADC_L_SFT
- RT5640_M_MONO_ADC_R
- RT5640_M_MONO_ADC_R1
- RT5640_M_MONO_ADC_R1_SFT
- RT5640_M_MONO_ADC_R2
- RT5640_M_MONO_ADC_R2_SFT
- RT5640_M_MONO_ADC_R_SFT
- RT5640_M_MP3_DIS
- RT5640_M_MP3_EN
- RT5640_M_MP3_L_MASK
- RT5640_M_MP3_L_SFT
- RT5640_M_MP3_MASK
- RT5640_M_MP3_ORG_L_MASK
- RT5640_M_MP3_ORG_L_SFT
- RT5640_M_MP3_ORG_R_MASK
- RT5640_M_MP3_ORG_R_SFT
- RT5640_M_MP3_R_MASK
- RT5640_M_MP3_R_SFT
- RT5640_M_MP3_SFT
- RT5640_M_OM_L_RM_L
- RT5640_M_OM_L_RM_L_SFT
- RT5640_M_OM_L_SM_L
- RT5640_M_OM_L_SM_L_SFT
- RT5640_M_OM_R_RM_R
- RT5640_M_OM_R_RM_R_SFT
- RT5640_M_OM_R_SM_R
- RT5640_M_OM_R_SM_R_SFT
- RT5640_M_OV_L_LM
- RT5640_M_OV_L_LM_SFT
- RT5640_M_OV_L_MM
- RT5640_M_OV_L_MM_SFT
- RT5640_M_OV_R_LM
- RT5640_M_OV_R_LM_SFT
- RT5640_M_OV_R_MM
- RT5640_M_OV_R_MM_SFT
- RT5640_M_RM_L_OM_L
- RT5640_M_RM_L_OM_L_SFT
- RT5640_M_RM_L_SM_L
- RT5640_M_RM_L_SM_L_SFT
- RT5640_M_RM_R_OM_R
- RT5640_M_RM_R_OM_R_SFT
- RT5640_M_RM_R_SM_R
- RT5640_M_RM_R_SM_R_SFT
- RT5640_M_SM_L_OM_L
- RT5640_M_SM_L_OM_L_SFT
- RT5640_M_SM_L_OM_R
- RT5640_M_SM_L_OM_R_SFT
- RT5640_M_STO_L_DAC_L
- RT5640_M_STO_L_DAC_L_SFT
- RT5640_M_STO_R_DAC_R
- RT5640_M_STO_R_DAC_R_SFT
- RT5640_M_SV_L_SPM_L
- RT5640_M_SV_L_SPM_L_SFT
- RT5640_M_SV_R_SPM_L
- RT5640_M_SV_R_SPM_L_SFT
- RT5640_M_SV_R_SPM_R
- RT5640_M_SV_R_SPM_R_SFT
- RT5640_M_ZCD_MASK
- RT5640_M_ZCD_OM_L
- RT5640_M_ZCD_OM_R
- RT5640_M_ZCD_RM_L
- RT5640_M_ZCD_RM_R
- RT5640_M_ZCD_SFT
- RT5640_M_ZCD_SM_L
- RT5640_M_ZCD_SM_R
- RT5640_NO_JACK
- RT5640_NO_WIND
- RT5640_OG_MP3_MASK
- RT5640_OG_MP3_SFT
- RT5640_OSW_L_DIS
- RT5640_OSW_L_EN
- RT5640_OSW_L_MASK
- RT5640_OSW_L_SFT
- RT5640_OSW_R_DIS
- RT5640_OSW_R_EN
- RT5640_OSW_R_MASK
- RT5640_OSW_R_SFT
- RT5640_OT_P_INV
- RT5640_OT_P_MASK
- RT5640_OT_P_NOR
- RT5640_OT_P_SFT
- RT5640_OT_STKY_DIS
- RT5640_OT_STKY_EN
- RT5640_OT_STKY_MASK
- RT5640_OT_STKY_SFT
- RT5640_OUTPUT
- RT5640_OUT_L1_MIXER
- RT5640_OUT_L2_MIXER
- RT5640_OUT_L3_MIXER
- RT5640_OUT_R1_MIXER
- RT5640_OUT_R2_MIXER
- RT5640_OUT_R3_MIXER
- RT5640_OUT_SV_DIS
- RT5640_OUT_SV_EN
- RT5640_OUT_SV_MASK
- RT5640_OUT_SV_SFT
- RT5640_OVCD_SF_0P5
- RT5640_OVCD_SF_0P75
- RT5640_OVCD_SF_1P0
- RT5640_OVCD_SF_1P5
- RT5640_OVT_STATUS
- RT5640_PGM_REG_ARR1
- RT5640_PGM_REG_ARR2
- RT5640_PGM_REG_ARR3
- RT5640_PGM_REG_ARR4
- RT5640_PGM_REG_ARR5
- RT5640_PLL1_PD_1
- RT5640_PLL1_PD_2
- RT5640_PLL1_PD_MASK
- RT5640_PLL1_PD_SFT
- RT5640_PLL1_SRC_BCLK1
- RT5640_PLL1_SRC_BCLK2
- RT5640_PLL1_SRC_BCLK3
- RT5640_PLL1_SRC_MASK
- RT5640_PLL1_SRC_MCLK
- RT5640_PLL1_SRC_SFT
- RT5640_PLL1_S_BCLK1
- RT5640_PLL1_S_BCLK2
- RT5640_PLL1_S_BCLK3
- RT5640_PLL1_S_MCLK
- RT5640_PLL_CTRL1
- RT5640_PLL_CTRL2
- RT5640_PLL_INP_MAX
- RT5640_PLL_INP_MIN
- RT5640_PLL_K_MASK
- RT5640_PLL_K_MAX
- RT5640_PLL_K_SFT
- RT5640_PLL_M_BP
- RT5640_PLL_M_BP_SFT
- RT5640_PLL_M_MASK
- RT5640_PLL_M_MAX
- RT5640_PLL_M_SFT
- RT5640_PLL_N_MASK
- RT5640_PLL_N_MAX
- RT5640_PLL_N_SFT
- RT5640_PM_HP_HV
- RT5640_PM_HP_LV
- RT5640_PM_HP_MASK
- RT5640_PM_HP_MV
- RT5640_PM_HP_SFT
- RT5640_PRE_SCLK_1024
- RT5640_PRE_SCLK_2048
- RT5640_PRE_SCLK_512
- RT5640_PRE_SCLK_MASK
- RT5640_PRE_SCLK_SFT
- RT5640_PRIV_DATA
- RT5640_PRIV_INDEX
- RT5640_PROG_DIS
- RT5640_PROG_EN
- RT5640_PROG_MASK
- RT5640_PROG_SFT
- RT5640_PR_BASE
- RT5640_PR_RANGE_BASE
- RT5640_PR_SPACING
- RT5640_PVDD_DET_DIS
- RT5640_PVDD_DET_EN
- RT5640_PVDD_DET_MASK
- RT5640_PVDD_DET_SFT
- RT5640_PV_DET_SPK_G
- RT5640_PWR_ADC_L
- RT5640_PWR_ADC_L_BIT
- RT5640_PWR_ADC_MF_L
- RT5640_PWR_ADC_MF_L_BIT
- RT5640_PWR_ADC_MF_R
- RT5640_PWR_ADC_MF_R_BIT
- RT5640_PWR_ADC_R
- RT5640_PWR_ADC_R_BIT
- RT5640_PWR_ADC_SF
- RT5640_PWR_ADC_SF_BIT
- RT5640_PWR_ANLG1
- RT5640_PWR_ANLG2
- RT5640_PWR_BG
- RT5640_PWR_BG_BIT
- RT5640_PWR_BST1
- RT5640_PWR_BST1_BIT
- RT5640_PWR_BST2
- RT5640_PWR_BST2_BIT
- RT5640_PWR_BST3
- RT5640_PWR_BST3_BIT
- RT5640_PWR_BST4
- RT5640_PWR_BST4_BIT
- RT5640_PWR_CLK25M_MASK
- RT5640_PWR_CLK25M_PD
- RT5640_PWR_CLK25M_PU
- RT5640_PWR_CLK25M_SFT
- RT5640_PWR_CLS_D
- RT5640_PWR_CLS_D_BIT
- RT5640_PWR_DAC_L1
- RT5640_PWR_DAC_L1_BIT
- RT5640_PWR_DAC_L2
- RT5640_PWR_DAC_L2_BIT
- RT5640_PWR_DAC_R1
- RT5640_PWR_DAC_R1_BIT
- RT5640_PWR_DAC_R2
- RT5640_PWR_DAC_R2_BIT
- RT5640_PWR_DIG1
- RT5640_PWR_DIG2
- RT5640_PWR_FV1
- RT5640_PWR_FV1_BIT
- RT5640_PWR_FV2
- RT5640_PWR_FV2_BIT
- RT5640_PWR_HA
- RT5640_PWR_HA_BIT
- RT5640_PWR_HP_L
- RT5640_PWR_HP_L_BIT
- RT5640_PWR_HP_R
- RT5640_PWR_HP_R_BIT
- RT5640_PWR_HV_L
- RT5640_PWR_HV_L_BIT
- RT5640_PWR_HV_R
- RT5640_PWR_HV_R_BIT
- RT5640_PWR_I2S1
- RT5640_PWR_I2S1_BIT
- RT5640_PWR_I2S2
- RT5640_PWR_I2S2_BIT
- RT5640_PWR_I2S_DSP
- RT5640_PWR_I2S_DSP_BIT
- RT5640_PWR_IN_L
- RT5640_PWR_IN_L_BIT
- RT5640_PWR_IN_R
- RT5640_PWR_IN_R_BIT
- RT5640_PWR_LDO2
- RT5640_PWR_LDO2_BIT
- RT5640_PWR_LM
- RT5640_PWR_LM_BIT
- RT5640_PWR_MA
- RT5640_PWR_MA_BIT
- RT5640_PWR_MB
- RT5640_PWR_MB1
- RT5640_PWR_MB1_BIT
- RT5640_PWR_MB_BIT
- RT5640_PWR_MB_MASK
- RT5640_PWR_MB_PD
- RT5640_PWR_MB_PU
- RT5640_PWR_MB_SFT
- RT5640_PWR_MIXER
- RT5640_PWR_MM
- RT5640_PWR_MM_BIT
- RT5640_PWR_OM_L
- RT5640_PWR_OM_L_BIT
- RT5640_PWR_OM_R
- RT5640_PWR_OM_R_BIT
- RT5640_PWR_OV_L
- RT5640_PWR_OV_L_BIT
- RT5640_PWR_OV_R
- RT5640_PWR_OV_R_BIT
- RT5640_PWR_PLL
- RT5640_PWR_PLL_BIT
- RT5640_PWR_RM_L
- RT5640_PWR_RM_L_BIT
- RT5640_PWR_RM_R
- RT5640_PWR_RM_R_BIT
- RT5640_PWR_SM_L
- RT5640_PWR_SM_L_BIT
- RT5640_PWR_SM_R
- RT5640_PWR_SM_R_BIT
- RT5640_PWR_SV_L
- RT5640_PWR_SV_L_BIT
- RT5640_PWR_SV_R
- RT5640_PWR_SV_R_BIT
- RT5640_PWR_VOL
- RT5640_PWR_VREF1
- RT5640_PWR_VREF1_BIT
- RT5640_PWR_VREF2
- RT5640_PWR_VREF2_BIT
- RT5640_RAMP_DIS
- RT5640_RAMP_EN
- RT5640_RAMP_MASK
- RT5640_RAMP_SFT
- RT5640_REC_L1_MIXER
- RT5640_REC_L2_MIXER
- RT5640_REC_R1_MIXER
- RT5640_REC_R2_MIXER
- RT5640_REG_DAT_MASK
- RT5640_REG_DAT_SFT
- RT5640_REG_IDX_MASK
- RT5640_REG_IDX_SFT
- RT5640_REG_LV_MASK
- RT5640_REG_LV_MX
- RT5640_REG_LV_PR
- RT5640_REG_LV_SFT
- RT5640_REG_SEQ_MASK
- RT5640_REG_SEQ_SFT
- RT5640_RESET
- RT5640_RSTN_DIS
- RT5640_RSTN_EN
- RT5640_RSTN_MASK
- RT5640_RSTN_SFT
- RT5640_RSTP_DIS
- RT5640_RSTP_EN
- RT5640_RSTP_MASK
- RT5640_RSTP_SFT
- RT5640_RXDC_SEL_L2R
- RT5640_RXDC_SEL_MASK
- RT5640_RXDC_SEL_NOR
- RT5640_RXDC_SEL_R2L
- RT5640_RXDC_SEL_SFT
- RT5640_RXDC_SEL_SWAP
- RT5640_RXDP_SEL_L2R
- RT5640_RXDP_SEL_MASK
- RT5640_RXDP_SEL_NOR
- RT5640_RXDP_SEL_R2L
- RT5640_RXDP_SEL_SFT
- RT5640_RXDP_SEL_SWAP
- RT5640_RXDP_SRC_DIV3
- RT5640_RXDP_SRC_MASK
- RT5640_RXDP_SRC_NOR
- RT5640_RXDP_SRC_SFT
- RT5640_R_MUTE
- RT5640_R_MUTE_SFT
- RT5640_R_VOL_MASK
- RT5640_R_VOL_SFT
- RT5640_SCB_CTRL
- RT5640_SCB_DIS
- RT5640_SCB_EN
- RT5640_SCB_FUNC
- RT5640_SCB_KEY_MASK
- RT5640_SCB_KEY_SFT
- RT5640_SCB_MASK
- RT5640_SCB_SFT
- RT5640_SCB_SWAP_DIS
- RT5640_SCB_SWAP_EN
- RT5640_SCB_SWAP_MASK
- RT5640_SCB_SWAP_SFT
- RT5640_SCLK_SRC_MASK
- RT5640_SCLK_SRC_MCLK
- RT5640_SCLK_SRC_PLL1
- RT5640_SCLK_SRC_RCCLK
- RT5640_SCLK_SRC_SFT
- RT5640_SCLK_S_MCLK
- RT5640_SCLK_S_PLL1
- RT5640_SCLK_S_PLL1_TK
- RT5640_SCLK_S_RCCLK
- RT5640_SEQ1_END_MASK
- RT5640_SEQ1_END_SFT
- RT5640_SEQ1_PT_RUN
- RT5640_SEQ1_PT_RUN_BIT
- RT5640_SEQ1_START_MASK
- RT5640_SEQ1_START_SFT
- RT5640_SEQ1_ST_FIN
- RT5640_SEQ1_ST_MASK
- RT5640_SEQ1_ST_RUN
- RT5640_SEQ1_ST_SFT
- RT5640_SEQ2_END_MASK
- RT5640_SEQ2_END_SFT
- RT5640_SEQ2_PT_RUN
- RT5640_SEQ2_PT_RUN_BIT
- RT5640_SEQ2_START_MASK
- RT5640_SEQ2_START_SFT
- RT5640_SEQ2_ST_FIN
- RT5640_SEQ2_ST_MASK
- RT5640_SEQ2_ST_RUN
- RT5640_SEQ2_ST_SFT
- RT5640_SEQ_2_PT_BIT
- RT5640_SEQ_2_PT_MASK
- RT5640_SEQ_DLY_MASK
- RT5640_SEQ_DLY_SFT
- RT5640_SI_DAC_AUTO
- RT5640_SI_DAC_MASK
- RT5640_SI_DAC_SFT
- RT5640_SI_DAC_TEST
- RT5640_SMT_TRIG_DIS
- RT5640_SMT_TRIG_EN
- RT5640_SMT_TRIG_MASK
- RT5640_SMT_TRIG_SFT
- RT5640_SPK_AG_DIS
- RT5640_SPK_AG_EN
- RT5640_SPK_AG_MASK
- RT5640_SPK_AG_SFT
- RT5640_SPK_L_MIXER
- RT5640_SPK_R_MIXER
- RT5640_SPK_VOL
- RT5640_SPO_CLSD_RATIO
- RT5640_SPO_CLSD_RATIO_MASK
- RT5640_SPO_CLSD_RATIO_SFT
- RT5640_SPO_L_MIXER
- RT5640_SPO_R_MIXER
- RT5640_SPO_SV_DIS
- RT5640_SPO_SV_EN
- RT5640_SPO_SV_MASK
- RT5640_SPO_SV_SFT
- RT5640_STEREO_RATES
- RT5640_STORM
- RT5640_STO_ADC_MIXER
- RT5640_STO_DAC_MIXER
- RT5640_STO_DAC_M_ASYN
- RT5640_STO_DAC_M_MASK
- RT5640_STO_DAC_M_NOR
- RT5640_STO_DAC_M_SFT
- RT5640_STO_L_DAC_L_VOL_MASK
- RT5640_STO_L_DAC_L_VOL_SFT
- RT5640_STO_R_DAC_R_VOL_MASK
- RT5640_STO_R_DAC_R_VOL_SFT
- RT5640_STO_T_LRCK1
- RT5640_STO_T_MASK
- RT5640_STO_T_SCLK
- RT5640_STO_T_SFT
- RT5640_SVOL_ZC
- RT5640_SV_DIS
- RT5640_SV_DLY_MASK
- RT5640_SV_DLY_SFT
- RT5640_SV_EN
- RT5640_SV_MASK
- RT5640_SV_SFT
- RT5640_SV_ZCD1
- RT5640_SV_ZCD2
- RT5640_TRXDP_SEL_SWAP
- RT5640_TXDC_SEL_L2R
- RT5640_TXDC_SEL_MASK
- RT5640_TXDC_SEL_NOR
- RT5640_TXDC_SEL_R2L
- RT5640_TXDC_SEL_SFT
- RT5640_TXDC_SEL_SWAP
- RT5640_TXDP_SEL_L2R
- RT5640_TXDP_SEL_MASK
- RT5640_TXDP_SEL_NOR
- RT5640_TXDP_SEL_R2L
- RT5640_TXDP_SEL_SFT
- RT5640_TXDP_SRC_DIV3
- RT5640_TXDP_SRC_MASK
- RT5640_TXDP_SRC_NOR
- RT5640_TXDP_SRC_SFT
- RT5640_U_IF1
- RT5640_U_IF2
- RT5640_U_IF3
- RT5640_VENDOR_ID
- RT5640_VENDOR_ID1
- RT5640_VENDOR_ID2
- RT5640_VLO_32V
- RT5640_VLO_3V
- RT5640_VLO_MASK
- RT5640_VLO_SFT
- RT5640_VOL_L_MUTE
- RT5640_VOL_L_SFT
- RT5640_VOL_R_MUTE
- RT5640_VOL_R_SFT
- RT5640_WIND_FILTER
- RT5640_WND_1
- RT5640_WND_2
- RT5640_WND_3
- RT5640_WND_4
- RT5640_WND_5
- RT5640_WND_8
- RT5640_WND_DIS
- RT5640_WND_EN
- RT5640_WND_FC_NW_MASK
- RT5640_WND_FC_NW_SFT
- RT5640_WND_FC_ST_MASK
- RT5640_WND_FC_ST_SFT
- RT5640_WND_FC_WK_MASK
- RT5640_WND_FC_WK_SFT
- RT5640_WND_MASK
- RT5640_WND_SFT
- RT5640_WND_STRONG_MASK
- RT5640_WND_STRONG_SFT
- RT5640_WND_TH_HI_MASK
- RT5640_WND_TH_HI_SFT
- RT5640_WND_TH_LO_MASK
- RT5640_WND_TH_LO_SFT
- RT5640_WND_WIND_MASK
- RT5640_WND_WIND_SFT
- RT5640_ZCD_DIG_DIS
- RT5640_ZCD_DIG_EN
- RT5640_ZCD_DIG_MASK
- RT5640_ZCD_DIG_SFT
- RT5640_ZCD_HP_DIS
- RT5640_ZCD_HP_EN
- RT5640_ZCD_HP_MASK
- RT5640_ZCD_HP_SFT
- RT5640_ZCD_MASK
- RT5640_ZCD_PD
- RT5640_ZCD_PU
- RT5640_ZCD_SFT
- RT5640_ZD_F_IM
- RT5640_ZD_F_MASK
- RT5640_ZD_F_SFT
- RT5640_ZD_F_UN
- RT5640_ZD_F_ZC_IM
- RT5640_ZD_F_ZC_IOD
- RT5640_ZD_T_MASK
- RT5640_ZD_T_SFT
- RT5645_1ST_HPF_DIS
- RT5645_1ST_HPF_EN
- RT5645_1ST_HPF_MASK
- RT5645_1ST_HPF_SFT
- RT5645_2ND_HPF_DIS
- RT5645_2ND_HPF_EN
- RT5645_2ND_HPF_MASK
- RT5645_2ND_HPF_SFT
- RT5645_3D_1F_MIX_MASK
- RT5645_3D_1F_MIX_SFT
- RT5645_3D_BT_DIS
- RT5645_3D_BT_EN
- RT5645_3D_BT_MASK
- RT5645_3D_BT_SFT
- RT5645_3D_CF_DIS
- RT5645_3D_CF_EN
- RT5645_3D_CF_MASK
- RT5645_3D_CF_SFT
- RT5645_3D_HP_DIS
- RT5645_3D_HP_EN
- RT5645_3D_HP_MASK
- RT5645_3D_HP_M_FRO
- RT5645_3D_HP_M_MASK
- RT5645_3D_HP_M_SFT
- RT5645_3D_HP_M_SUR
- RT5645_3D_HP_SFT
- RT5645_3D_SPK
- RT5645_3D_SPK_CG_MASK
- RT5645_3D_SPK_CG_SFT
- RT5645_3D_SPK_DIS
- RT5645_3D_SPK_EN
- RT5645_3D_SPK_MASK
- RT5645_3D_SPK_M_MASK
- RT5645_3D_SPK_M_SFT
- RT5645_3D_SPK_SFT
- RT5645_3D_SPK_SG_MASK
- RT5645_3D_SPK_SG_SFT
- RT5645_ADC_1_SRC_ADC
- RT5645_ADC_1_SRC_DACMIX
- RT5645_ADC_1_SRC_MASK
- RT5645_ADC_1_SRC_SFT
- RT5645_ADC_2_SRC_MASK
- RT5645_ADC_2_SRC_SFT
- RT5645_ADC_BST_VOL1
- RT5645_ADC_BST_VOL2
- RT5645_ADC_EQ_CTRL1
- RT5645_ADC_EQ_CTRL2
- RT5645_ADC_L_VOL_MASK
- RT5645_ADC_L_VOL_SFT
- RT5645_ADC_MONO_HP_CTRL1
- RT5645_ADC_MONO_HP_CTRL2
- RT5645_ADC_OSR_128
- RT5645_ADC_OSR_16
- RT5645_ADC_OSR_32
- RT5645_ADC_OSR_64
- RT5645_ADC_OSR_MASK
- RT5645_ADC_OSR_SFT
- RT5645_ADC_R_OSR_128
- RT5645_ADC_R_OSR_16
- RT5645_ADC_R_OSR_32
- RT5645_ADC_R_OSR_64
- RT5645_ADC_R_OSR_MASK
- RT5645_ADC_R_OSR_SFT
- RT5645_ADC_R_VOL_MASK
- RT5645_ADC_R_VOL_SFT
- RT5645_ADDA_CLK1
- RT5645_ADDA_CLK2
- RT5645_ADHPF_EN
- RT5645_ADHPF_EN_SFT
- RT5645_ADJ_HPF1
- RT5645_ADJ_HPF2
- RT5645_ADJ_HPF_CTRL
- RT5645_AD_DA_MIXER
- RT5645_AD_MONOL_CLK_SEL_MASK
- RT5645_AD_MONOL_CLK_SEL_SFT
- RT5645_AD_MONOR_CLK_SEL_MASK
- RT5645_AD_MONOR_CLK_SEL_SFT
- RT5645_AD_MONO_L_FILTER
- RT5645_AD_MONO_R_FILTER
- RT5645_AD_STEREO_FILTER
- RT5645_AD_STO1_CLK_SEL_MASK
- RT5645_AD_STO1_CLK_SEL_SFT
- RT5645_AD_TRG_HI
- RT5645_AD_TRG_LO
- RT5645_AD_TRG_MASK
- RT5645_AD_TRG_SFT
- RT5645_AIF1
- RT5645_AIF2
- RT5645_AIFS
- RT5645_ALC_CTRL_1
- RT5645_ALC_CTRL_2
- RT5645_ALC_CTRL_3
- RT5645_ALC_CTRL_4
- RT5645_ALC_CTRL_5
- RT5645_AMD_TRG_HI
- RT5645_AMD_TRG_LO
- RT5645_AMD_TRG_MASK
- RT5645_AMD_TRG_SFT
- RT5645_ANCM_DET_DIS
- RT5645_ANCM_DET_JD
- RT5645_ANCM_DET_MASK
- RT5645_ANCM_DET_MB1
- RT5645_ANCM_DET_MB2
- RT5645_ANCM_DET_SFT
- RT5645_ANC_CD_BOTH
- RT5645_ANC_CD_IND
- RT5645_ANC_CD_MASK
- RT5645_ANC_CD_SFT
- RT5645_ANC_CG_L_MASK
- RT5645_ANC_CG_L_SFT
- RT5645_ANC_CG_R_MASK
- RT5645_ANC_CG_R_SFT
- RT5645_ANC_CLK_ANC
- RT5645_ANC_CLK_MASK
- RT5645_ANC_CLK_REG
- RT5645_ANC_CLK_SFT
- RT5645_ANC_CO_L_MASK
- RT5645_ANC_CO_L_SFT
- RT5645_ANC_CO_R_MASK
- RT5645_ANC_CO_R_SFT
- RT5645_ANC_CS_DIS
- RT5645_ANC_CS_EN
- RT5645_ANC_CS_MASK
- RT5645_ANC_CS_SFT
- RT5645_ANC_DET_DIS
- RT5645_ANC_DET_JD
- RT5645_ANC_DET_MASK
- RT5645_ANC_DET_MB1
- RT5645_ANC_DET_MB2
- RT5645_ANC_DET_SFT
- RT5645_ANC_DIS
- RT5645_ANC_EN
- RT5645_ANC_FG_L_MASK
- RT5645_ANC_FG_L_SFT
- RT5645_ANC_FG_R_MASK
- RT5645_ANC_FG_R_SFT
- RT5645_ANC_MASK
- RT5645_ANC_MD_1067MS
- RT5645_ANC_MD_267MS
- RT5645_ANC_MD_67MS
- RT5645_ANC_MD_DIS
- RT5645_ANC_MD_MASK
- RT5645_ANC_MD_SFT
- RT5645_ANC_M_MASK
- RT5645_ANC_M_NOR
- RT5645_ANC_M_REV
- RT5645_ANC_M_SFT
- RT5645_ANC_SFT
- RT5645_ANC_SN_DIS
- RT5645_ANC_SN_EN
- RT5645_ANC_SN_MASK
- RT5645_ANC_SN_SFT
- RT5645_ANC_SW_AUTO
- RT5645_ANC_SW_MASK
- RT5645_ANC_SW_NOR
- RT5645_ANC_SW_SFT
- RT5645_ANC_ZCD_DIS
- RT5645_ANC_ZCD_MASK
- RT5645_ANC_ZCD_SFT
- RT5645_ANC_ZCD_T1
- RT5645_ANC_ZCD_T2
- RT5645_ANC_ZCD_WT
- RT5645_ASRC_1
- RT5645_ASRC_2
- RT5645_ASRC_3
- RT5645_ASRC_4
- RT5645_AUTO_PD_DIS
- RT5645_AUTO_PD_EN
- RT5645_AUTO_PD_MASK
- RT5645_AUTO_PD_SFT
- RT5645_A_JD_CTRL1
- RT5645_BASS_BACK
- RT5645_BB_CT_A
- RT5645_BB_CT_B
- RT5645_BB_CT_C
- RT5645_BB_CT_D
- RT5645_BB_CT_MASK
- RT5645_BB_CT_SFT
- RT5645_BB_DIS
- RT5645_BB_EN
- RT5645_BB_MASK
- RT5645_BB_SFT
- RT5645_BIAS_CUR1
- RT5645_BIAS_CUR3
- RT5645_BPS_DIS
- RT5645_BPS_EN
- RT5645_BPS_MASK
- RT5645_BPS_SFT
- RT5645_BREEZE
- RT5645_BST_MASK1
- RT5645_BST_MASK2
- RT5645_BST_SFT1
- RT5645_BST_SFT2
- RT5645_CAL_DIS
- RT5645_CAL_EN
- RT5645_CAL_MASK
- RT5645_CAL_M_CAL
- RT5645_CAL_M_DEP
- RT5645_CAL_M_MASK
- RT5645_CAL_M_SFT
- RT5645_CAL_P_CAL
- RT5645_CAL_P_DAC_CAL
- RT5645_CAL_P_MASK
- RT5645_CAL_P_NONE
- RT5645_CAL_P_SFT
- RT5645_CAL_SFT
- RT5645_CAL_TEST_DIS
- RT5645_CAL_TEST_EN
- RT5645_CAL_TEST_MASK
- RT5645_CAL_TEST_SFT
- RT5645_CAPLESS_EN
- RT5645_CBJ_BST1_EN
- RT5645_CBJ_BST1_MASK
- RT5645_CBJ_BST1_SFT
- RT5645_CBJ_DET_MODE
- RT5645_CBJ_JD_HP_EN
- RT5645_CBJ_JD_MIC_EN
- RT5645_CBJ_JD_MIC_SW_EN
- RT5645_CBJ_MIC_SEL_L
- RT5645_CBJ_MIC_SEL_R
- RT5645_CBJ_MIC_SW
- RT5645_CBJ_MN_JD
- RT5645_CBJ_TIE_G_L
- RT5645_CBJ_TIE_G_R
- RT5645_CHARGE_PUMP
- RT5645_CHOP_DAC_ADC
- RT5645_CLK_SEL_I2S1_ASRC
- RT5645_CLK_SEL_I2S2_ASRC
- RT5645_CLK_SEL_SYS
- RT5645_CLK_SEL_SYS2
- RT5645_CLSD_INT_REG1
- RT5645_CLSD_OC_MASK
- RT5645_CLSD_OC_PD
- RT5645_CLSD_OC_PU
- RT5645_CLSD_OC_SFT
- RT5645_CLSD_OC_TH_MASK
- RT5645_CLSD_OC_TH_SFT
- RT5645_CLSD_OM_MASK
- RT5645_CLSD_OM_MONO
- RT5645_CLSD_OM_SFT
- RT5645_CLSD_OM_STO
- RT5645_CLSD_OUT_CTRL
- RT5645_CLSD_RATIO_MASK
- RT5645_CLSD_RATIO_SFT
- RT5645_CLSD_SCH_L
- RT5645_CLSD_SCH_MASK
- RT5645_CLSD_SCH_S
- RT5645_CLSD_SCH_SFT
- RT5645_CMP_MIC_IN_DET_MASK
- RT5645_CP_FQ1_MASK
- RT5645_CP_FQ1_SFT
- RT5645_CP_FQ2_MASK
- RT5645_CP_FQ2_SFT
- RT5645_CP_FQ3_MASK
- RT5645_CP_FQ3_SFT
- RT5645_CP_FQ_12_KHZ
- RT5645_CP_FQ_192_KHZ
- RT5645_CP_FQ_1_5_KHZ
- RT5645_CP_FQ_24_KHZ
- RT5645_CP_FQ_3_KHZ
- RT5645_CP_FQ_48_KHZ
- RT5645_CP_FQ_6_KHZ
- RT5645_CP_FQ_96_KHZ
- RT5645_CP_SYS_MASK
- RT5645_CP_SYS_SFT
- RT5645_DA1_ZDET_SFT
- RT5645_DAC1_DIG_VOL
- RT5645_DAC1_L_SEL_IF1
- RT5645_DAC1_L_SEL_IF2
- RT5645_DAC1_L_SEL_IF3
- RT5645_DAC1_L_SEL_IF4
- RT5645_DAC1_L_SEL_MASK
- RT5645_DAC1_L_SEL_SFT
- RT5645_DAC1_R_SEL_IF1
- RT5645_DAC1_R_SEL_IF2
- RT5645_DAC1_R_SEL_IF3
- RT5645_DAC1_R_SEL_IF4
- RT5645_DAC1_R_SEL_MASK
- RT5645_DAC1_R_SEL_SFT
- RT5645_DAC2_DIG_VOL
- RT5645_DAC2_L_SEL_MASK
- RT5645_DAC2_L_SEL_SFT
- RT5645_DAC2_R_SEL_MASK
- RT5645_DAC2_R_SEL_SFT
- RT5645_DAC_CTRL
- RT5645_DAC_L1_MONO_L_VOL_MASK
- RT5645_DAC_L1_MONO_L_VOL_SFT
- RT5645_DAC_L1_STO_L_VOL_MASK
- RT5645_DAC_L1_STO_L_VOL_SFT
- RT5645_DAC_L1_STO_R_VOL_MASK
- RT5645_DAC_L1_STO_R_VOL_SFT
- RT5645_DAC_L1_VOL_MASK
- RT5645_DAC_L1_VOL_SFT
- RT5645_DAC_L2_DAC_L_VOL_MASK
- RT5645_DAC_L2_DAC_L_VOL_SFT
- RT5645_DAC_L2_DAC_R_VOL_MASK
- RT5645_DAC_L2_DAC_R_VOL_SFT
- RT5645_DAC_L2_MONO_L_VOL_MASK
- RT5645_DAC_L2_MONO_L_VOL_SFT
- RT5645_DAC_L2_MONO_R_VOL_MASK
- RT5645_DAC_L2_MONO_R_VOL_SFT
- RT5645_DAC_L2_STO_L_VOL_MASK
- RT5645_DAC_L2_STO_L_VOL_SFT
- RT5645_DAC_L2_VOL_MASK
- RT5645_DAC_L2_VOL_SFT
- RT5645_DAC_L_OSR_128
- RT5645_DAC_L_OSR_16
- RT5645_DAC_L_OSR_32
- RT5645_DAC_L_OSR_64
- RT5645_DAC_L_OSR_MASK
- RT5645_DAC_L_OSR_SFT
- RT5645_DAC_OSR_128
- RT5645_DAC_OSR_16
- RT5645_DAC_OSR_32
- RT5645_DAC_OSR_64
- RT5645_DAC_OSR_MASK
- RT5645_DAC_OSR_SFT
- RT5645_DAC_R1_MONO_R_VOL_MASK
- RT5645_DAC_R1_MONO_R_VOL_SFT
- RT5645_DAC_R1_STO_L_VOL_MASK
- RT5645_DAC_R1_STO_L_VOL_SFT
- RT5645_DAC_R1_STO_R_VOL_MASK
- RT5645_DAC_R1_STO_R_VOL_SFT
- RT5645_DAC_R1_VOL_MASK
- RT5645_DAC_R1_VOL_SFT
- RT5645_DAC_R2_DAC_L_VOL_MASK
- RT5645_DAC_R2_DAC_L_VOL_SFT
- RT5645_DAC_R2_DAC_R_VOL_MASK
- RT5645_DAC_R2_DAC_R_VOL_SFT
- RT5645_DAC_R2_MONO_L_VOL_MASK
- RT5645_DAC_R2_MONO_L_VOL_SFT
- RT5645_DAC_R2_MONO_R_VOL_MASK
- RT5645_DAC_R2_MONO_R_VOL_SFT
- RT5645_DAC_R2_STO_R_VOL_MASK
- RT5645_DAC_R2_STO_R_VOL_SFT
- RT5645_DAC_R2_VOL_MASK
- RT5645_DAC_R2_VOL_SFT
- RT5645_DAHPF_EN
- RT5645_DAHPF_EN_SFT
- RT5645_DA_MONOL_CLK_SEL_MASK
- RT5645_DA_MONOL_CLK_SEL_SFT
- RT5645_DA_MONOR_CLK_SEL_MASK
- RT5645_DA_MONOR_CLK_SEL_SFT
- RT5645_DA_MONO_L_FILTER
- RT5645_DA_MONO_R_FILTER
- RT5645_DA_STEREO_FILTER
- RT5645_DA_STO_CLK_SEL_MASK
- RT5645_DA_STO_CLK_SEL_SFT
- RT5645_DC_CAL_DIS
- RT5645_DC_CAL_EN
- RT5645_DC_CAL_MASK
- RT5645_DC_CAL_M_CAL
- RT5645_DC_CAL_M_MASK
- RT5645_DC_CAL_M_NOR
- RT5645_DC_CAL_M_SFT
- RT5645_DC_CAL_SFT
- RT5645_DEPOP_AUTO
- RT5645_DEPOP_M1
- RT5645_DEPOP_M2
- RT5645_DEPOP_M3
- RT5645_DEPOP_MAN
- RT5645_DEPOP_MASK
- RT5645_DEPOP_SFT
- RT5645_DET_CLK_DIS
- RT5645_DET_CLK_MASK
- RT5645_DET_CLK_MODE1
- RT5645_DET_CLK_MODE2
- RT5645_DEVICE_ID
- RT5645_DIG_DP_DIS
- RT5645_DIG_DP_EN
- RT5645_DIG_DP_MASK
- RT5645_DIG_DP_SFT
- RT5645_DIG_GATE_CTRL
- RT5645_DIG_INF1_DATA
- RT5645_DIG_MIXER
- RT5645_DIG_VOL
- RT5645_DIP_SPK_INF
- RT5645_DMIC1_DISABLE
- RT5645_DMIC2_DISABLE
- RT5645_DMIC3_SRC_MASK
- RT5645_DMIC3_SRC_SFT
- RT5645_DMIC_1L_LH_FALLING
- RT5645_DMIC_1L_LH_MASK
- RT5645_DMIC_1L_LH_RISING
- RT5645_DMIC_1L_LH_SFT
- RT5645_DMIC_1R_LH_FALLING
- RT5645_DMIC_1R_LH_MASK
- RT5645_DMIC_1R_LH_RISING
- RT5645_DMIC_1R_LH_SFT
- RT5645_DMIC_1_DIS
- RT5645_DMIC_1_DP_GPIO11
- RT5645_DMIC_1_DP_GPIO5
- RT5645_DMIC_1_DP_IN2N
- RT5645_DMIC_1_DP_MASK
- RT5645_DMIC_1_DP_SFT
- RT5645_DMIC_1_EN
- RT5645_DMIC_1_EN_MASK
- RT5645_DMIC_1_EN_SFT
- RT5645_DMIC_1_M_ASYN
- RT5645_DMIC_1_M_MASK
- RT5645_DMIC_1_M_NOR
- RT5645_DMIC_1_M_SFT
- RT5645_DMIC_2L_LH_FALLING
- RT5645_DMIC_2L_LH_MASK
- RT5645_DMIC_2L_LH_RISING
- RT5645_DMIC_2L_LH_SFT
- RT5645_DMIC_2R_LH_FALLING
- RT5645_DMIC_2R_LH_MASK
- RT5645_DMIC_2R_LH_RISING
- RT5645_DMIC_2R_LH_SFT
- RT5645_DMIC_2_DIS
- RT5645_DMIC_2_DP_GPIO10
- RT5645_DMIC_2_DP_GPIO12
- RT5645_DMIC_2_DP_GPIO6
- RT5645_DMIC_2_DP_IN2P
- RT5645_DMIC_2_DP_MASK
- RT5645_DMIC_2_DP_SFT
- RT5645_DMIC_2_EN
- RT5645_DMIC_2_EN_MASK
- RT5645_DMIC_2_EN_SFT
- RT5645_DMIC_2_M_ASYN
- RT5645_DMIC_2_M_MASK
- RT5645_DMIC_2_M_NOR
- RT5645_DMIC_2_M_SFT
- RT5645_DMIC_3_DIS
- RT5645_DMIC_3_EN
- RT5645_DMIC_3_EN_MASK
- RT5645_DMIC_3_EN_SFT
- RT5645_DMIC_CLK_MASK
- RT5645_DMIC_CLK_SFT
- RT5645_DMIC_CTRL1
- RT5645_DMIC_CTRL2
- RT5645_DMIC_DATA_GPIO10
- RT5645_DMIC_DATA_GPIO11
- RT5645_DMIC_DATA_GPIO12
- RT5645_DMIC_DATA_GPIO5
- RT5645_DMIC_DATA_GPIO6
- RT5645_DMIC_DATA_IN2N
- RT5645_DMIC_DATA_IN2P
- RT5645_DMIC_SRC_MASK
- RT5645_DMIC_SRC_SFT
- RT5645_DP_ATT_MASK
- RT5645_DP_ATT_SFT
- RT5645_DP_SIG_AP
- RT5645_DP_SIG_MASK
- RT5645_DP_SIG_SFT
- RT5645_DP_SIG_TEST
- RT5645_DP_SPK_DIS
- RT5645_DP_SPK_EN
- RT5645_DP_SPK_MASK
- RT5645_DP_SPK_SFT
- RT5645_DP_TH_MASK
- RT5645_DP_TH_SFT
- RT5645_DRC1_HL_CTRL1
- RT5645_DRC2_CTRL1
- RT5645_DRC2_CTRL2
- RT5645_DRC2_CTRL3
- RT5645_DRC2_CTRL4
- RT5645_DRC2_CTRL5
- RT5645_DRC2_HL_CTRL1
- RT5645_DRC_AGC_AR_MASK
- RT5645_DRC_AGC_AR_SFT
- RT5645_DRC_AGC_CPR_1_1
- RT5645_DRC_AGC_CPR_1_2
- RT5645_DRC_AGC_CPR_1_3
- RT5645_DRC_AGC_CPR_1_4
- RT5645_DRC_AGC_CPR_MASK
- RT5645_DRC_AGC_CPR_SFT
- RT5645_DRC_AGC_CP_DIS
- RT5645_DRC_AGC_CP_EN
- RT5645_DRC_AGC_CP_MASK
- RT5645_DRC_AGC_CP_SFT
- RT5645_DRC_AGC_DIS
- RT5645_DRC_AGC_EN
- RT5645_DRC_AGC_MASK
- RT5645_DRC_AGC_NGB_MASK
- RT5645_DRC_AGC_NGB_SFT
- RT5645_DRC_AGC_NGH_DIS
- RT5645_DRC_AGC_NGH_EN
- RT5645_DRC_AGC_NGH_MASK
- RT5645_DRC_AGC_NGH_SFT
- RT5645_DRC_AGC_NGT_MASK
- RT5645_DRC_AGC_NGT_SFT
- RT5645_DRC_AGC_NG_DIS
- RT5645_DRC_AGC_NG_EN
- RT5645_DRC_AGC_NG_MASK
- RT5645_DRC_AGC_NG_SFT
- RT5645_DRC_AGC_POB_MASK
- RT5645_DRC_AGC_POB_SFT
- RT5645_DRC_AGC_PRB_MASK
- RT5645_DRC_AGC_PRB_SFT
- RT5645_DRC_AGC_P_ADC
- RT5645_DRC_AGC_P_DAC
- RT5645_DRC_AGC_P_MASK
- RT5645_DRC_AGC_P_SFT
- RT5645_DRC_AGC_RC_MASK
- RT5645_DRC_AGC_RC_SFT
- RT5645_DRC_AGC_R_1764K
- RT5645_DRC_AGC_R_192K
- RT5645_DRC_AGC_R_441K
- RT5645_DRC_AGC_R_48K
- RT5645_DRC_AGC_R_882K
- RT5645_DRC_AGC_R_96K
- RT5645_DRC_AGC_R_MASK
- RT5645_DRC_AGC_R_SFT
- RT5645_DRC_AGC_SFT
- RT5645_DRC_AGC_TAR_MASK
- RT5645_DRC_AGC_TAR_SFT
- RT5645_DRC_AGC_UPD
- RT5645_DRC_AGC_UPD_BIT
- RT5645_EG_MP3_MASK
- RT5645_EG_MP3_SFT
- RT5645_EQ_BPF1_DIS
- RT5645_EQ_BPF1_EN
- RT5645_EQ_BPF1_MASK
- RT5645_EQ_BPF1_SFT
- RT5645_EQ_BPF2_DIS
- RT5645_EQ_BPF2_EN
- RT5645_EQ_BPF2_MASK
- RT5645_EQ_BPF2_SFT
- RT5645_EQ_BPF3_DIS
- RT5645_EQ_BPF3_EN
- RT5645_EQ_BPF3_MASK
- RT5645_EQ_BPF3_SFT
- RT5645_EQ_BPF4_DIS
- RT5645_EQ_BPF4_EN
- RT5645_EQ_BPF4_MASK
- RT5645_EQ_BPF4_SFT
- RT5645_EQ_BW_BP1
- RT5645_EQ_BW_BP2
- RT5645_EQ_BW_BP3
- RT5645_EQ_BW_BP4
- RT5645_EQ_BW_HIP2
- RT5645_EQ_BW_LOP
- RT5645_EQ_CD_DIS
- RT5645_EQ_CD_EN
- RT5645_EQ_CD_MASK
- RT5645_EQ_CD_SFT
- RT5645_EQ_CTRL1
- RT5645_EQ_CTRL2
- RT5645_EQ_CTRL_MASK
- RT5645_EQ_DITH_LSB
- RT5645_EQ_DITH_LSB_1
- RT5645_EQ_DITH_LSB_2
- RT5645_EQ_DITH_MASK
- RT5645_EQ_DITH_NOR
- RT5645_EQ_DITH_SFT
- RT5645_EQ_FC_BP1
- RT5645_EQ_FC_BP2
- RT5645_EQ_FC_BP3
- RT5645_EQ_FC_BP4
- RT5645_EQ_FC_HIP1
- RT5645_EQ_FC_HIP2
- RT5645_EQ_GN_BP1
- RT5645_EQ_GN_BP2
- RT5645_EQ_GN_BP3
- RT5645_EQ_GN_BP4
- RT5645_EQ_GN_HIP1
- RT5645_EQ_GN_HIP2
- RT5645_EQ_GN_LOP
- RT5645_EQ_HPF1_DIS
- RT5645_EQ_HPF1_EN
- RT5645_EQ_HPF1_MASK
- RT5645_EQ_HPF1_M_1ST
- RT5645_EQ_HPF1_M_HI
- RT5645_EQ_HPF1_M_MASK
- RT5645_EQ_HPF1_M_SFT
- RT5645_EQ_HPF1_SFT
- RT5645_EQ_HPF2_DIS
- RT5645_EQ_HPF2_EN
- RT5645_EQ_HPF2_MASK
- RT5645_EQ_HPF2_SFT
- RT5645_EQ_LPF1_M_1ST
- RT5645_EQ_LPF1_M_LO
- RT5645_EQ_LPF1_M_MASK
- RT5645_EQ_LPF1_M_SFT
- RT5645_EQ_LPF_DIS
- RT5645_EQ_LPF_EN
- RT5645_EQ_LPF_MASK
- RT5645_EQ_LPF_SFT
- RT5645_EQ_PRE_VOL
- RT5645_EQ_PRE_VOL_MASK
- RT5645_EQ_PRE_VOL_SFT
- RT5645_EQ_PST_VOL
- RT5645_EQ_PST_VOL_MASK
- RT5645_EQ_PST_VOL_SFT
- RT5645_EQ_SRC_ADC
- RT5645_EQ_SRC_DAC
- RT5645_EQ_SRC_MASK
- RT5645_EQ_SRC_SFT
- RT5645_EQ_UPD
- RT5645_EQ_UPD_BIT
- RT5645_FAST_UPDN_DIS
- RT5645_FAST_UPDN_EN
- RT5645_FAST_UPDN_MASK
- RT5645_FAST_UPDN_SFT
- RT5645_FORMATS
- RT5645_GEN_CTRL1
- RT5645_GEN_CTRL2
- RT5645_GEN_CTRL3
- RT5645_GLB_CLK
- RT5645_GP10_PIN_DMIC2_SDA
- RT5645_GP10_PIN_GPIO10
- RT5645_GP10_PIN_MASK
- RT5645_GP10_PIN_SFT
- RT5645_GP11_PIN_DMIC1_SDA
- RT5645_GP11_PIN_GPIO11
- RT5645_GP11_PIN_MASK
- RT5645_GP11_PIN_SFT
- RT5645_GP12_PIN_DMIC2_SDA
- RT5645_GP12_PIN_GPIO12
- RT5645_GP12_PIN_MASK
- RT5645_GP12_PIN_SFT
- RT5645_GP1_OUT_HI
- RT5645_GP1_OUT_LO
- RT5645_GP1_OUT_MASK
- RT5645_GP1_OUT_SFT
- RT5645_GP1_PF_IN
- RT5645_GP1_PF_MASK
- RT5645_GP1_PF_OUT
- RT5645_GP1_PF_SFT
- RT5645_GP1_PIN_GPIO1
- RT5645_GP1_PIN_IRQ
- RT5645_GP1_PIN_MASK
- RT5645_GP1_PIN_SFT
- RT5645_GP1_P_INV
- RT5645_GP1_P_MASK
- RT5645_GP1_P_NOR
- RT5645_GP1_P_SFT
- RT5645_GP2_OUT_HI
- RT5645_GP2_OUT_LO
- RT5645_GP2_OUT_MASK
- RT5645_GP2_OUT_SFT
- RT5645_GP2_PF_IN
- RT5645_GP2_PF_MASK
- RT5645_GP2_PF_OUT
- RT5645_GP2_PF_SFT
- RT5645_GP2_PIN_DMIC1_SCL
- RT5645_GP2_PIN_GPIO2
- RT5645_GP2_PIN_MASK
- RT5645_GP2_PIN_SFT
- RT5645_GP2_P_INV
- RT5645_GP2_P_MASK
- RT5645_GP2_P_NOR
- RT5645_GP2_P_SFT
- RT5645_GP3_OUT_HI
- RT5645_GP3_OUT_LO
- RT5645_GP3_OUT_MASK
- RT5645_GP3_OUT_SFT
- RT5645_GP3_PF_IN
- RT5645_GP3_PF_MASK
- RT5645_GP3_PF_OUT
- RT5645_GP3_PF_SFT
- RT5645_GP3_PIN_DMIC1_SDA
- RT5645_GP3_PIN_GPIO3
- RT5645_GP3_PIN_IRQ
- RT5645_GP3_PIN_MASK
- RT5645_GP3_PIN_SFT
- RT5645_GP3_P_INV
- RT5645_GP3_P_MASK
- RT5645_GP3_P_NOR
- RT5645_GP3_P_SFT
- RT5645_GP4_OUT_HI
- RT5645_GP4_OUT_LO
- RT5645_GP4_OUT_MASK
- RT5645_GP4_OUT_SFT
- RT5645_GP4_PF_IN
- RT5645_GP4_PF_MASK
- RT5645_GP4_PF_OUT
- RT5645_GP4_PF_SFT
- RT5645_GP4_PIN_DMIC2_SDA
- RT5645_GP4_PIN_GPIO4
- RT5645_GP4_PIN_MASK
- RT5645_GP4_PIN_SFT
- RT5645_GP4_P_INV
- RT5645_GP4_P_MASK
- RT5645_GP4_P_NOR
- RT5645_GP4_P_SFT
- RT5645_GP5_PIN_DMIC1_SDA
- RT5645_GP5_PIN_GPIO5
- RT5645_GP5_PIN_MASK
- RT5645_GP5_PIN_SFT
- RT5645_GP6_PIN_DMIC2_SDA
- RT5645_GP6_PIN_GPIO6
- RT5645_GP6_PIN_MASK
- RT5645_GP6_PIN_SFT
- RT5645_GP8_PIN_DMIC2_SDA
- RT5645_GP8_PIN_GPIO8
- RT5645_GP8_PIN_MASK
- RT5645_GP8_PIN_SFT
- RT5645_GPIO_CTRL1
- RT5645_GPIO_CTRL2
- RT5645_GPIO_CTRL3
- RT5645_GPIO_M_FLT
- RT5645_GPIO_M_MASK
- RT5645_GPIO_M_PH
- RT5645_GPIO_M_SFT
- RT5645_G_BB_BST_25DB
- RT5645_G_BB_BST_MASK
- RT5645_G_BB_BST_SFT
- RT5645_G_BST1_OM_L_MASK
- RT5645_G_BST1_OM_L_SFT
- RT5645_G_BST1_OM_R_MASK
- RT5645_G_BST1_OM_R_SFT
- RT5645_G_BST1_RM_L_MASK
- RT5645_G_BST1_RM_L_SFT
- RT5645_G_BST1_RM_R_MASK
- RT5645_G_BST1_RM_R_SFT
- RT5645_G_BST2_OM_L_MASK
- RT5645_G_BST2_OM_L_SFT
- RT5645_G_BST2_OM_R_MASK
- RT5645_G_BST2_OM_R_SFT
- RT5645_G_BST2_RM_L_MASK
- RT5645_G_BST2_RM_L_SFT
- RT5645_G_BST2_RM_R_MASK
- RT5645_G_BST2_RM_R_SFT
- RT5645_G_BST3_OM_L_MASK
- RT5645_G_BST3_OM_L_SFT
- RT5645_G_BST3_RM_L_MASK
- RT5645_G_BST3_RM_L_SFT
- RT5645_G_BST3_RM_R_MASK
- RT5645_G_BST3_RM_R_SFT
- RT5645_G_BST4_OM_R_MASK
- RT5645_G_BST4_OM_R_SFT
- RT5645_G_BST4_RM_L_MASK
- RT5645_G_BST4_RM_L_SFT
- RT5645_G_BST4_RM_R_MASK
- RT5645_G_BST4_RM_R_SFT
- RT5645_G_DAC_L1_OM_L_MASK
- RT5645_G_DAC_L1_OM_L_SFT
- RT5645_G_DAC_L1_SM_L_MASK
- RT5645_G_DAC_L1_SM_L_SFT
- RT5645_G_DAC_L2_OM_L_MASK
- RT5645_G_DAC_L2_OM_L_SFT
- RT5645_G_DAC_L2_OM_R_MASK
- RT5645_G_DAC_L2_OM_R_SFT
- RT5645_G_DAC_L2_SM_L_MASK
- RT5645_G_DAC_L2_SM_L_SFT
- RT5645_G_DAC_R1_OM_R_MASK
- RT5645_G_DAC_R1_OM_R_SFT
- RT5645_G_DAC_R1_SM_R_MASK
- RT5645_G_DAC_R1_SM_R_SFT
- RT5645_G_DAC_R2_OM_L_MASK
- RT5645_G_DAC_R2_OM_L_SFT
- RT5645_G_DAC_R2_OM_R_MASK
- RT5645_G_DAC_R2_OM_R_SFT
- RT5645_G_DAC_R2_SM_R_MASK
- RT5645_G_DAC_R2_SM_R_SFT
- RT5645_G_HP_L_RM_L_MASK
- RT5645_G_HP_L_RM_L_SFT
- RT5645_G_HP_R_RM_R_MASK
- RT5645_G_HP_R_RM_R_SFT
- RT5645_G_IN_L_OM_L_MASK
- RT5645_G_IN_L_OM_L_SFT
- RT5645_G_IN_L_RM_L_MASK
- RT5645_G_IN_L_RM_L_SFT
- RT5645_G_IN_L_SM_L_MASK
- RT5645_G_IN_L_SM_L_SFT
- RT5645_G_IN_R_OM_R_MASK
- RT5645_G_IN_R_OM_R_SFT
- RT5645_G_IN_R_RM_R_MASK
- RT5645_G_IN_R_RM_R_SFT
- RT5645_G_IN_R_SM_R_MASK
- RT5645_G_IN_R_SM_R_SFT
- RT5645_G_LOUTMIX_MASK
- RT5645_G_LOUTMIX_SFT
- RT5645_G_MONOMIX_MASK
- RT5645_G_MONOMIX_SFT
- RT5645_G_OM_L_RM_L_MASK
- RT5645_G_OM_L_RM_L_SFT
- RT5645_G_OM_L_SM_L_MASK
- RT5645_G_OM_L_SM_L_SFT
- RT5645_G_OM_R_RM_R_MASK
- RT5645_G_OM_R_RM_R_SFT
- RT5645_G_OM_R_SM_R_MASK
- RT5645_G_OM_R_SM_R_SFT
- RT5645_G_RM_L_OM_L_MASK
- RT5645_G_RM_L_OM_L_SFT
- RT5645_G_RM_L_SM_L_MASK
- RT5645_G_RM_L_SM_L_SFT
- RT5645_G_RM_R_OM_R_MASK
- RT5645_G_RM_R_OM_R_SFT
- RT5645_G_RM_R_SM_R_MASK
- RT5645_G_RM_R_SM_R_SFT
- RT5645_HAPTIC_CTRL1
- RT5645_HAPTIC_CTRL10
- RT5645_HAPTIC_CTRL2
- RT5645_HAPTIC_CTRL3
- RT5645_HAPTIC_CTRL4
- RT5645_HAPTIC_CTRL5
- RT5645_HAPTIC_CTRL6
- RT5645_HAPTIC_CTRL7
- RT5645_HAPTIC_CTRL8
- RT5645_HAPTIC_CTRL9
- RT5645_HG_MP3_MASK
- RT5645_HG_MP3_SFT
- RT5645_HPD_PS_DIS
- RT5645_HPD_PS_EN
- RT5645_HPD_PS_MASK
- RT5645_HPD_PS_SFT
- RT5645_HPD_RCV_MASK
- RT5645_HPD_RCV_SFT
- RT5645_HPF_CF_L_MASK
- RT5645_HPF_CF_L_SFT
- RT5645_HPF_CF_R_MASK
- RT5645_HPF_CF_R_SFT
- RT5645_HPF_FC_MASK
- RT5645_HPF_FC_SFT
- RT5645_HPMIXL_CTRL
- RT5645_HPMIXR_CTRL
- RT5645_HPOMIXL_CTRL
- RT5645_HPOMIXR_CTRL
- RT5645_HPO_MIXER
- RT5645_HP_CALIB_AMP_DET
- RT5645_HP_CB_MASK
- RT5645_HP_CB_PD
- RT5645_HP_CB_PU
- RT5645_HP_CB_SFT
- RT5645_HP_CD_PD_DIS
- RT5645_HP_CD_PD_EN
- RT5645_HP_CD_PD_MASK
- RT5645_HP_CD_PD_SFT
- RT5645_HP_CO_DIS
- RT5645_HP_CO_EN
- RT5645_HP_CO_MASK
- RT5645_HP_CO_SFT
- RT5645_HP_CP_MASK
- RT5645_HP_CP_PD
- RT5645_HP_CP_PU
- RT5645_HP_CP_SFT
- RT5645_HP_DCC_INT1
- RT5645_HP_DP_MASK
- RT5645_HP_DP_PD
- RT5645_HP_DP_PU
- RT5645_HP_DP_SFT
- RT5645_HP_L_SMT_DIS
- RT5645_HP_L_SMT_EN
- RT5645_HP_L_SMT_MASK
- RT5645_HP_L_SMT_SFT
- RT5645_HP_OC_TH_105
- RT5645_HP_OC_TH_120
- RT5645_HP_OC_TH_135
- RT5645_HP_OC_TH_90
- RT5645_HP_OC_TH_MASK
- RT5645_HP_OC_TH_SFT
- RT5645_HP_OVCD_DIS
- RT5645_HP_OVCD_EN
- RT5645_HP_OVCD_MASK
- RT5645_HP_OVCD_SFT
- RT5645_HP_R_SMT_DIS
- RT5645_HP_R_SMT_EN
- RT5645_HP_R_SMT_MASK
- RT5645_HP_R_SMT_SFT
- RT5645_HP_SG_DIS
- RT5645_HP_SG_EN
- RT5645_HP_SG_MASK
- RT5645_HP_SG_SFT
- RT5645_HP_SV_DIS
- RT5645_HP_SV_EN
- RT5645_HP_SV_MASK
- RT5645_HP_SV_SFT
- RT5645_HP_VOL
- RT5645_HWEQ
- RT5645_HWEQ_NUM
- RT5645_I2S1_PD_MASK
- RT5645_I2S1_PD_SFT
- RT5645_I2S1_SDP
- RT5645_I2S2_DAC_PIN_GPIO
- RT5645_I2S2_DAC_PIN_I2S
- RT5645_I2S2_DAC_PIN_MASK
- RT5645_I2S2_DAC_PIN_SFT
- RT5645_I2S2_F_I2S1_TCLK
- RT5645_I2S2_F_I2S2_D2
- RT5645_I2S2_F_MASK
- RT5645_I2S2_F_SFT
- RT5645_I2S2_PD_MASK
- RT5645_I2S2_PD_SFT
- RT5645_I2S2_SDI_I2S1
- RT5645_I2S2_SDI_I2S2
- RT5645_I2S2_SDI_MASK
- RT5645_I2S2_SDI_SFT
- RT5645_I2S2_SDP
- RT5645_I2S2_SEL
- RT5645_I2S2_SEL_SFT
- RT5645_I2S_BCLK_MS2_32
- RT5645_I2S_BCLK_MS2_64
- RT5645_I2S_BCLK_MS2_MASK
- RT5645_I2S_BCLK_MS2_SFT
- RT5645_I2S_BCLK_MS3_32
- RT5645_I2S_BCLK_MS3_64
- RT5645_I2S_BCLK_MS3_MASK
- RT5645_I2S_BCLK_MS3_SFT
- RT5645_I2S_BP_INV
- RT5645_I2S_BP_MASK
- RT5645_I2S_BP_NOR
- RT5645_I2S_BP_SFT
- RT5645_I2S_DF_I2S
- RT5645_I2S_DF_LEFT
- RT5645_I2S_DF_MASK
- RT5645_I2S_DF_PCM_A
- RT5645_I2S_DF_PCM_B
- RT5645_I2S_DF_SFT
- RT5645_I2S_DL_16
- RT5645_I2S_DL_20
- RT5645_I2S_DL_24
- RT5645_I2S_DL_8
- RT5645_I2S_DL_MASK
- RT5645_I2S_DL_SFT
- RT5645_I2S_I_CP_A_LAW
- RT5645_I2S_I_CP_MASK
- RT5645_I2S_I_CP_OFF
- RT5645_I2S_I_CP_SFT
- RT5645_I2S_I_CP_U_LAW
- RT5645_I2S_MS_M
- RT5645_I2S_MS_MASK
- RT5645_I2S_MS_S
- RT5645_I2S_MS_SFT
- RT5645_I2S_O_CP_A_LAW
- RT5645_I2S_O_CP_MASK
- RT5645_I2S_O_CP_OFF
- RT5645_I2S_O_CP_SFT
- RT5645_I2S_O_CP_U_LAW
- RT5645_I2S_PD1_1
- RT5645_I2S_PD1_12
- RT5645_I2S_PD1_16
- RT5645_I2S_PD1_2
- RT5645_I2S_PD1_3
- RT5645_I2S_PD1_4
- RT5645_I2S_PD1_6
- RT5645_I2S_PD1_8
- RT5645_I2S_PD1_MASK
- RT5645_I2S_PD1_SFT
- RT5645_I2S_PD2_1
- RT5645_I2S_PD2_12
- RT5645_I2S_PD2_16
- RT5645_I2S_PD2_2
- RT5645_I2S_PD2_3
- RT5645_I2S_PD2_4
- RT5645_I2S_PD2_6
- RT5645_I2S_PD2_8
- RT5645_I2S_PD2_MASK
- RT5645_I2S_PD2_SFT
- RT5645_I2S_PD3_1
- RT5645_I2S_PD3_12
- RT5645_I2S_PD3_16
- RT5645_I2S_PD3_2
- RT5645_I2S_PD3_3
- RT5645_I2S_PD3_4
- RT5645_I2S_PD3_6
- RT5645_I2S_PD3_8
- RT5645_I2S_PD3_MASK
- RT5645_I2S_PD3_SFT
- RT5645_IF1_ADC1_IN1_SEL
- RT5645_IF1_ADC1_IN1_SFT
- RT5645_IF1_ADC1_IN2_SEL
- RT5645_IF1_ADC1_IN2_SFT
- RT5645_IF1_ADC2_IN1_SEL
- RT5645_IF1_ADC2_IN1_SFT
- RT5645_IF1_ADC2_IN_SEL
- RT5645_IF1_ADC2_IN_SFT
- RT5645_IF1_ADC_IN_MASK
- RT5645_IF1_ADC_IN_SFT
- RT5645_IF2_ADC_IN_MASK
- RT5645_IF2_ADC_IN_SFT
- RT5645_IF2_ADC_SEL_MASK
- RT5645_IF2_ADC_SEL_SFT
- RT5645_IF2_DAC_SEL_MASK
- RT5645_IF2_DAC_SEL_SFT
- RT5645_IF3_ADC_IN_MASK
- RT5645_IF3_ADC_IN_SFT
- RT5645_IF3_ADC_SEL_MASK
- RT5645_IF3_ADC_SEL_SFT
- RT5645_IF3_DAC_SEL_MASK
- RT5645_IF3_DAC_SEL_SFT
- RT5645_IL_CMD
- RT5645_IL_CMD2
- RT5645_IL_CMD3
- RT5645_IN1_CTRL1
- RT5645_IN1_CTRL2
- RT5645_IN1_CTRL3
- RT5645_IN2_CTRL
- RT5645_INL1_INR1_VOL
- RT5645_INL_SEL_IN4P
- RT5645_INL_SEL_MASK
- RT5645_INL_SEL_MONOP
- RT5645_INL_SEL_SFT
- RT5645_INL_VOL_MASK
- RT5645_INL_VOL_SFT
- RT5645_INR_SEL_IN4N
- RT5645_INR_SEL_MASK
- RT5645_INR_SEL_MONON
- RT5645_INR_SEL_SFT
- RT5645_INR_VOL_MASK
- RT5645_INR_VOL_SFT
- RT5645_INT_IRQ_ST
- RT5645_IN_DF2
- RT5645_IN_SFT2
- RT5645_IRQ_CLK_GATE_CTRL
- RT5645_IRQ_CLK_INT
- RT5645_IRQ_CLK_MCLK
- RT5645_IRQ_CTRL1
- RT5645_IRQ_CTRL2
- RT5645_IRQ_CTRL3
- RT5645_IRQ_JD_1_1_EN
- RT5645_IRQ_JD_BP
- RT5645_IRQ_JD_MASK
- RT5645_IRQ_JD_NOR
- RT5645_IRQ_JD_SFT
- RT5645_IRQ_MB1_OC_BP
- RT5645_IRQ_MB1_OC_MASK
- RT5645_IRQ_MB1_OC_NOR
- RT5645_IRQ_MB1_OC_SFT
- RT5645_IRQ_MB2_OC_BP
- RT5645_IRQ_MB2_OC_MASK
- RT5645_IRQ_MB2_OC_NOR
- RT5645_IRQ_MB2_OC_SFT
- RT5645_IRQ_OT_BP
- RT5645_IRQ_OT_MASK
- RT5645_IRQ_OT_NOR
- RT5645_IRQ_OT_SFT
- RT5645_IRQ_PSV_MODE
- RT5645_JD1_IN4P_DIS
- RT5645_JD1_IN4P_EN
- RT5645_JD1_IN4P_MASK
- RT5645_JD1_IN4P_SFT
- RT5645_JD1_MODE_0
- RT5645_JD1_MODE_1
- RT5645_JD1_MODE_2
- RT5645_JD1_MODE_MASK
- RT5645_JD2_IN4N_DIS
- RT5645_JD2_IN4N_EN
- RT5645_JD2_IN4N_MASK
- RT5645_JD2_IN4N_SFT
- RT5645_JD_1_1_INV
- RT5645_JD_1_1_MASK
- RT5645_JD_1_1_NOR
- RT5645_JD_1_1_SFT
- RT5645_JD_CBJ_EN
- RT5645_JD_CBJ_POL
- RT5645_JD_CTRL
- RT5645_JD_CTRL3
- RT5645_JD_CTRL4
- RT5645_JD_DIS
- RT5645_JD_F_GPIO_JD1
- RT5645_JD_F_GPIO_JD2
- RT5645_JD_F_JD1_1
- RT5645_JD_F_JD1_2
- RT5645_JD_F_JD2
- RT5645_JD_F_JD3
- RT5645_JD_F_MX0B_12
- RT5645_JD_GPIO1
- RT5645_JD_GPIO2
- RT5645_JD_GPIO3
- RT5645_JD_GPIO4
- RT5645_JD_HP_DIS
- RT5645_JD_HP_EN
- RT5645_JD_HP_MASK
- RT5645_JD_HP_SFT
- RT5645_JD_HP_TRG_HI
- RT5645_JD_HP_TRG_LO
- RT5645_JD_HP_TRG_MASK
- RT5645_JD_HP_TRG_SFT
- RT5645_JD_JD1_IN4P
- RT5645_JD_JD2_IN4N
- RT5645_JD_LO_DIS
- RT5645_JD_LO_EN
- RT5645_JD_LO_MASK
- RT5645_JD_LO_SFT
- RT5645_JD_LO_TRG_HI
- RT5645_JD_LO_TRG_LO
- RT5645_JD_LO_TRG_MASK
- RT5645_JD_LO_TRG_SFT
- RT5645_JD_MASK
- RT5645_JD_MO_DIS
- RT5645_JD_MO_EN
- RT5645_JD_MO_MASK
- RT5645_JD_MO_SFT
- RT5645_JD_MO_TRG_HI
- RT5645_JD_MO_TRG_LO
- RT5645_JD_MO_TRG_MASK
- RT5645_JD_MO_TRG_SFT
- RT5645_JD_PSV_MODE
- RT5645_JD_P_INV
- RT5645_JD_P_MASK
- RT5645_JD_P_NOR
- RT5645_JD_P_SFT
- RT5645_JD_SFT
- RT5645_JD_SPL_DIS
- RT5645_JD_SPL_EN
- RT5645_JD_SPL_MASK
- RT5645_JD_SPL_SFT
- RT5645_JD_SPL_TRG_HI
- RT5645_JD_SPL_TRG_LO
- RT5645_JD_SPL_TRG_MASK
- RT5645_JD_SPL_TRG_SFT
- RT5645_JD_SPR_DIS
- RT5645_JD_SPR_EN
- RT5645_JD_SPR_MASK
- RT5645_JD_SPR_SFT
- RT5645_JD_SPR_TRG_HI
- RT5645_JD_SPR_TRG_LO
- RT5645_JD_SPR_TRG_MASK
- RT5645_JD_SPR_TRG_SFT
- RT5645_JD_STKY_DIS
- RT5645_JD_STKY_EN
- RT5645_JD_STKY_MASK
- RT5645_JD_STKY_SFT
- RT5645_JD_TRI_CBJ_SEL_MASK
- RT5645_JD_TRI_CBJ_SEL_SFT
- RT5645_JD_TRI_HPO_SEL_MASK
- RT5645_JD_TRI_HPO_SEL_SFT
- RT5645_LDO_SEL_MASK
- RT5645_LDO_SEL_SFT
- RT5645_LOUT1
- RT5645_LOUT_CTRL
- RT5645_LOUT_MIXER
- RT5645_L_MUTE
- RT5645_L_MUTE_SFT
- RT5645_L_VOL_MASK
- RT5645_L_VOL_SFT
- RT5645_M1_T_I2S2
- RT5645_M1_T_I2S2_D3
- RT5645_M1_T_MASK
- RT5645_M1_T_SFT
- RT5645_MAMP_INT_REG2
- RT5645_MB1_OC_CLR
- RT5645_MB1_OC_CLR_SFT
- RT5645_MB1_OC_P_INV
- RT5645_MB1_OC_P_MASK
- RT5645_MB1_OC_P_NOR
- RT5645_MB1_OC_P_SFT
- RT5645_MB1_OC_STKY_DIS
- RT5645_MB1_OC_STKY_EN
- RT5645_MB1_OC_STKY_MASK
- RT5645_MB1_OC_STKY_SFT
- RT5645_MB2_OC_CLR
- RT5645_MB2_OC_CLR_SFT
- RT5645_MB2_OC_P_INV
- RT5645_MB2_OC_P_MASK
- RT5645_MB2_OC_P_NOR
- RT5645_MB2_OC_P_SFT
- RT5645_MB2_OC_STKY_DIS
- RT5645_MB2_OC_STKY_EN
- RT5645_MB2_OC_STKY_MASK
- RT5645_MB2_OC_STKY_SFT
- RT5645_MIC1_BS_75AV
- RT5645_MIC1_BS_9AV
- RT5645_MIC1_BS_MASK
- RT5645_MIC1_BS_SFT
- RT5645_MIC1_CLK_DIS
- RT5645_MIC1_CLK_EN
- RT5645_MIC1_CLK_MASK
- RT5645_MIC1_CLK_SFT
- RT5645_MIC1_OVCD_DIS
- RT5645_MIC1_OVCD_EN
- RT5645_MIC1_OVCD_MASK
- RT5645_MIC1_OVCD_SFT
- RT5645_MIC1_OVTH_1500UA
- RT5645_MIC1_OVTH_2000UA
- RT5645_MIC1_OVTH_600UA
- RT5645_MIC1_OVTH_MASK
- RT5645_MIC1_OVTH_SFT
- RT5645_MIC2_BS_75AV
- RT5645_MIC2_BS_9AV
- RT5645_MIC2_BS_MASK
- RT5645_MIC2_BS_SFT
- RT5645_MIC2_CLK_DIS
- RT5645_MIC2_CLK_EN
- RT5645_MIC2_CLK_MASK
- RT5645_MIC2_CLK_SFT
- RT5645_MIC2_OVCD_DIS
- RT5645_MIC2_OVCD_EN
- RT5645_MIC2_OVCD_MASK
- RT5645_MIC2_OVCD_SFT
- RT5645_MIC2_OVTH_1500UA
- RT5645_MIC2_OVTH_2000UA
- RT5645_MIC2_OVTH_600UA
- RT5645_MIC2_OVTH_MASK
- RT5645_MIC2_OVTH_SFT
- RT5645_MICBIAS
- RT5645_MICBIAS1_POW_CTRL_SEL_A
- RT5645_MICBIAS1_POW_CTRL_SEL_M
- RT5645_MICBIAS1_POW_CTRL_SEL_MASK
- RT5645_MICBIAS2_POW_CTRL_SEL_A
- RT5645_MICBIAS2_POW_CTRL_SEL_M
- RT5645_MICBIAS2_POW_CTRL_SEL_MASK
- RT5645_MICINDET_MANU
- RT5645_MIXER_INT_REG
- RT5645_MONO_ADC_COMP_MASK
- RT5645_MONO_ADC_COMP_SFT
- RT5645_MONO_ADC_DIG_VOL
- RT5645_MONO_ADC_L1_SRC_ADCL
- RT5645_MONO_ADC_L1_SRC_DACMIXL
- RT5645_MONO_ADC_L1_SRC_MASK
- RT5645_MONO_ADC_L1_SRC_SFT
- RT5645_MONO_ADC_L2_SRC_MASK
- RT5645_MONO_ADC_L2_SRC_SFT
- RT5645_MONO_ADC_L_BST_MASK
- RT5645_MONO_ADC_L_BST_SFT
- RT5645_MONO_ADC_L_VOL_MASK
- RT5645_MONO_ADC_L_VOL_SFT
- RT5645_MONO_ADC_MIXER
- RT5645_MONO_ADC_R1_SRC_ADCR
- RT5645_MONO_ADC_R1_SRC_DACMIXR
- RT5645_MONO_ADC_R1_SRC_MASK
- RT5645_MONO_ADC_R1_SRC_SFT
- RT5645_MONO_ADC_R2_SRC_MASK
- RT5645_MONO_ADC_R2_SRC_SFT
- RT5645_MONO_ADC_R_BST_MASK
- RT5645_MONO_ADC_R_BST_SFT
- RT5645_MONO_ADC_R_VOL_MASK
- RT5645_MONO_ADC_R_VOL_SFT
- RT5645_MONO_DAC_MIXER
- RT5645_MONO_DMIC_L_SRC_MASK
- RT5645_MONO_DMIC_L_SRC_SFT
- RT5645_MONO_DMIC_R_SRC_MASK
- RT5645_MONO_DMIC_R_SRC_SFT
- RT5645_MP3_HLP_DIS
- RT5645_MP3_HLP_EN
- RT5645_MP3_HLP_MASK
- RT5645_MP3_HLP_SFT
- RT5645_MP3_PLUS1
- RT5645_MP3_PLUS2
- RT5645_MP3_WT_1_2
- RT5645_MP3_WT_1_4
- RT5645_MP3_WT_MASK
- RT5645_MP3_WT_SFT
- RT5645_MRES_15MO
- RT5645_MRES_25MO
- RT5645_MRES_35MO
- RT5645_MRES_45MO
- RT5645_MRES_MASK
- RT5645_MRES_SFT
- RT5645_MT_DIS
- RT5645_MT_EN
- RT5645_MT_MASK
- RT5645_MT_SFT
- RT5645_MUTI_DRC_CTRL1
- RT5645_M_3D_D2H_MASK
- RT5645_M_3D_D2H_SFT
- RT5645_M_3D_D2R_MASK
- RT5645_M_3D_D2R_SFT
- RT5645_M_3D_HRTF_MASK
- RT5645_M_3D_HRTF_SFT
- RT5645_M_3D_REVB_MASK
- RT5645_M_3D_REVB_SFT
- RT5645_M_ADCMIX_L
- RT5645_M_ADCMIX_L_SFT
- RT5645_M_ADCMIX_R
- RT5645_M_ADCMIX_R_SFT
- RT5645_M_ADC_L1
- RT5645_M_ADC_L1_SFT
- RT5645_M_ADC_L2
- RT5645_M_ADC_L2_SFT
- RT5645_M_ADC_R1
- RT5645_M_ADC_R1_SFT
- RT5645_M_ADC_R2
- RT5645_M_ADC_R2_SFT
- RT5645_M_ANC_DAC_L
- RT5645_M_ANC_DAC_L_SFT
- RT5645_M_ANC_DAC_R
- RT5645_M_ANC_DAC_R_SFT
- RT5645_M_BB_HPF_L_MASK
- RT5645_M_BB_HPF_L_SFT
- RT5645_M_BB_HPF_R_MASK
- RT5645_M_BB_HPF_R_SFT
- RT5645_M_BB_L_MASK
- RT5645_M_BB_L_SFT
- RT5645_M_BB_R_MASK
- RT5645_M_BB_R_SFT
- RT5645_M_BST1_HV
- RT5645_M_BST1_HV_SFT
- RT5645_M_BST1_L_SM_L
- RT5645_M_BST1_L_SM_L_SFT
- RT5645_M_BST1_OM_L
- RT5645_M_BST1_OM_L_SFT
- RT5645_M_BST1_RM_L
- RT5645_M_BST1_RM_L_SFT
- RT5645_M_BST1_RM_R
- RT5645_M_BST1_RM_R_SFT
- RT5645_M_BST2_HV
- RT5645_M_BST2_HV_SFT
- RT5645_M_BST2_MM
- RT5645_M_BST2_MM_SFT
- RT5645_M_BST2_OM_R
- RT5645_M_BST2_OM_R_SFT
- RT5645_M_BST2_RM_L
- RT5645_M_BST2_RM_L_SFT
- RT5645_M_BST2_RM_R
- RT5645_M_BST2_RM_R_SFT
- RT5645_M_BST2_R_SM_R
- RT5645_M_BST2_R_SM_R_SFT
- RT5645_M_BST3_HV
- RT5645_M_BST3_HV_SFT
- RT5645_M_BST3_L_SM_L
- RT5645_M_BST3_L_SM_L_SFT
- RT5645_M_BST3_MM
- RT5645_M_BST3_MM_SFT
- RT5645_M_BST3_OM_L
- RT5645_M_BST3_OM_L_SFT
- RT5645_M_BST3_OM_R
- RT5645_M_BST3_OM_R_SFT
- RT5645_M_BST3_RM_L
- RT5645_M_BST3_RM_L_SFT
- RT5645_M_BST3_RM_R
- RT5645_M_BST3_RM_R_SFT
- RT5645_M_BST3_R_SM_R
- RT5645_M_BST3_R_SM_R_SFT
- RT5645_M_BST3_SPM_L
- RT5645_M_BST3_SPM_L_SFT
- RT5645_M_BST3_SPM_R
- RT5645_M_BST3_SPM_R_SFT
- RT5645_M_DAC1_HM
- RT5645_M_DAC1_HM_SFT
- RT5645_M_DAC1_HV
- RT5645_M_DAC1_HV_SFT
- RT5645_M_DAC1_L
- RT5645_M_DAC1_L_SFT
- RT5645_M_DAC1_R
- RT5645_M_DAC1_R_SFT
- RT5645_M_DAC2_HV
- RT5645_M_DAC2_HV_SFT
- RT5645_M_DAC_L1
- RT5645_M_DAC_L1_LM
- RT5645_M_DAC_L1_LM_SFT
- RT5645_M_DAC_L1_MONO_L
- RT5645_M_DAC_L1_MONO_L_SFT
- RT5645_M_DAC_L1_OM_L
- RT5645_M_DAC_L1_OM_L_SFT
- RT5645_M_DAC_L1_SFT
- RT5645_M_DAC_L1_SM_L
- RT5645_M_DAC_L1_SM_L_SFT
- RT5645_M_DAC_L1_SPM_L
- RT5645_M_DAC_L1_SPM_L_SFT
- RT5645_M_DAC_L1_STO_R
- RT5645_M_DAC_L1_STO_R_SFT
- RT5645_M_DAC_L2
- RT5645_M_DAC_L2_DAC_L
- RT5645_M_DAC_L2_DAC_L_SFT
- RT5645_M_DAC_L2_DAC_R
- RT5645_M_DAC_L2_DAC_R_SFT
- RT5645_M_DAC_L2_MA
- RT5645_M_DAC_L2_MA_SFT
- RT5645_M_DAC_L2_MM
- RT5645_M_DAC_L2_MM_SFT
- RT5645_M_DAC_L2_MONO_L
- RT5645_M_DAC_L2_MONO_L_SFT
- RT5645_M_DAC_L2_MONO_R
- RT5645_M_DAC_L2_MONO_R_SFT
- RT5645_M_DAC_L2_OM_L
- RT5645_M_DAC_L2_OM_L_SFT
- RT5645_M_DAC_L2_SFT
- RT5645_M_DAC_L2_SM_L
- RT5645_M_DAC_L2_SM_L_SFT
- RT5645_M_DAC_L2_VOL
- RT5645_M_DAC_L2_VOL_SFT
- RT5645_M_DAC_R1
- RT5645_M_DAC_R1_LM
- RT5645_M_DAC_R1_LM_SFT
- RT5645_M_DAC_R1_MM
- RT5645_M_DAC_R1_MM_SFT
- RT5645_M_DAC_R1_MONO_R
- RT5645_M_DAC_R1_MONO_R_SFT
- RT5645_M_DAC_R1_OM_R
- RT5645_M_DAC_R1_OM_R_SFT
- RT5645_M_DAC_R1_SFT
- RT5645_M_DAC_R1_SM_R
- RT5645_M_DAC_R1_SM_R_SFT
- RT5645_M_DAC_R1_SPM_L
- RT5645_M_DAC_R1_SPM_L_SFT
- RT5645_M_DAC_R1_SPM_R
- RT5645_M_DAC_R1_SPM_R_SFT
- RT5645_M_DAC_R1_STO_L
- RT5645_M_DAC_R1_STO_L_SFT
- RT5645_M_DAC_R2
- RT5645_M_DAC_R2_DAC_L
- RT5645_M_DAC_R2_DAC_L_SFT
- RT5645_M_DAC_R2_DAC_R
- RT5645_M_DAC_R2_DAC_R_SFT
- RT5645_M_DAC_R2_MM
- RT5645_M_DAC_R2_MM_SFT
- RT5645_M_DAC_R2_MONO_L
- RT5645_M_DAC_R2_MONO_L_SFT
- RT5645_M_DAC_R2_MONO_R
- RT5645_M_DAC_R2_MONO_R_SFT
- RT5645_M_DAC_R2_OM_R
- RT5645_M_DAC_R2_OM_R_SFT
- RT5645_M_DAC_R2_SFT
- RT5645_M_DAC_R2_SM_R
- RT5645_M_DAC_R2_SM_R_SFT
- RT5645_M_DAC_R2_VOL
- RT5645_M_DAC_R2_VOL_SFT
- RT5645_M_HPVOL_HM
- RT5645_M_HPVOL_HM_SFT
- RT5645_M_HP_L_RM_L
- RT5645_M_HP_L_RM_L_SFT
- RT5645_M_HP_R_RM_R
- RT5645_M_HP_R_RM_R_SFT
- RT5645_M_IN_HV
- RT5645_M_IN_HV_SFT
- RT5645_M_IN_L_OM_L
- RT5645_M_IN_L_OM_L_SFT
- RT5645_M_IN_L_RM_L
- RT5645_M_IN_L_RM_L_SFT
- RT5645_M_IN_L_SM_L
- RT5645_M_IN_L_SM_L_SFT
- RT5645_M_IN_R_OM_R
- RT5645_M_IN_R_OM_R_SFT
- RT5645_M_IN_R_RM_R
- RT5645_M_IN_R_RM_R_SFT
- RT5645_M_IN_R_SM_R
- RT5645_M_IN_R_SM_R_SFT
- RT5645_M_MM_L_RM_L
- RT5645_M_MM_L_RM_L_SFT
- RT5645_M_MM_R_RM_R
- RT5645_M_MM_R_RM_R_SFT
- RT5645_M_MONO_ADC_L1
- RT5645_M_MONO_ADC_L1_SFT
- RT5645_M_MONO_ADC_L2
- RT5645_M_MONO_ADC_L2_SFT
- RT5645_M_MONO_ADC_R1
- RT5645_M_MONO_ADC_R1_SFT
- RT5645_M_MONO_ADC_R2
- RT5645_M_MONO_ADC_R2_SFT
- RT5645_M_MP3_DIS
- RT5645_M_MP3_EN
- RT5645_M_MP3_L_MASK
- RT5645_M_MP3_L_SFT
- RT5645_M_MP3_MASK
- RT5645_M_MP3_ORG_L_MASK
- RT5645_M_MP3_ORG_L_SFT
- RT5645_M_MP3_ORG_R_MASK
- RT5645_M_MP3_ORG_R_SFT
- RT5645_M_MP3_R_MASK
- RT5645_M_MP3_R_SFT
- RT5645_M_MP3_SFT
- RT5645_M_OM_L_RM_L
- RT5645_M_OM_L_RM_L_SFT
- RT5645_M_OM_R_RM_R
- RT5645_M_OM_R_RM_R_SFT
- RT5645_M_OV_L_LM
- RT5645_M_OV_L_LM_SFT
- RT5645_M_OV_L_MM
- RT5645_M_OV_L_MM_SFT
- RT5645_M_OV_R_LM
- RT5645_M_OV_R_LM_SFT
- RT5645_M_PDM1_L
- RT5645_M_PDM1_L_SFT
- RT5645_M_PDM1_R
- RT5645_M_PDM1_R_SFT
- RT5645_M_PDM2_L
- RT5645_M_PDM2_L_SFT
- RT5645_M_PDM2_R
- RT5645_M_PDM2_R_SFT
- RT5645_M_STO_L_DAC_L
- RT5645_M_STO_L_DAC_L_SFT
- RT5645_M_STO_R_DAC_R
- RT5645_M_STO_R_DAC_R_SFT
- RT5645_M_SV_L_SPM_L
- RT5645_M_SV_L_SPM_L_SFT
- RT5645_M_SV_R_SPM_L
- RT5645_M_SV_R_SPM_L_SFT
- RT5645_M_SV_R_SPM_R
- RT5645_M_SV_R_SPM_R_SFT
- RT5645_M_ZCD_MASK
- RT5645_M_ZCD_OM_L
- RT5645_M_ZCD_OM_R
- RT5645_M_ZCD_RM_L
- RT5645_M_ZCD_RM_R
- RT5645_M_ZCD_SFT
- RT5645_M_ZCD_SM_L
- RT5645_M_ZCD_SM_R
- RT5645_NO_WIND
- RT5645_OG_MP3_MASK
- RT5645_OG_MP3_SFT
- RT5645_OT_P_INV
- RT5645_OT_P_MASK
- RT5645_OT_P_NOR
- RT5645_OT_P_SFT
- RT5645_OT_STKY_DIS
- RT5645_OT_STKY_EN
- RT5645_OT_STKY_MASK
- RT5645_OT_STKY_SFT
- RT5645_OUT_L1_MIXER
- RT5645_OUT_L_GAIN1
- RT5645_OUT_L_GAIN2
- RT5645_OUT_R1_MIXER
- RT5645_OUT_R_GAIN1
- RT5645_OUT_R_GAIN2
- RT5645_OUT_SV_DIS
- RT5645_OUT_SV_EN
- RT5645_OUT_SV_MASK
- RT5645_OUT_SV_SFT
- RT5645_PDM1_BUSY
- RT5645_PDM1_L_MASK
- RT5645_PDM1_L_SFT
- RT5645_PDM1_R_MASK
- RT5645_PDM1_R_SFT
- RT5645_PDM2_BUSY
- RT5645_PDM2_L_MASK
- RT5645_PDM2_L_SFT
- RT5645_PDM2_R_MASK
- RT5645_PDM2_R_SFT
- RT5645_PDM_DIV_MASK
- RT5645_PDM_GAIN
- RT5645_PDM_OUT_CTRL
- RT5645_PDM_PATTERN
- RT5645_PLL1_PD_1
- RT5645_PLL1_PD_2
- RT5645_PLL1_PD_MASK
- RT5645_PLL1_PD_SFT
- RT5645_PLL1_SRC_BCLK1
- RT5645_PLL1_SRC_BCLK2
- RT5645_PLL1_SRC_BCLK3
- RT5645_PLL1_SRC_MASK
- RT5645_PLL1_SRC_MCLK
- RT5645_PLL1_SRC_RCCLK
- RT5645_PLL1_SRC_SFT
- RT5645_PLL1_S_BCLK1
- RT5645_PLL1_S_BCLK2
- RT5645_PLL1_S_MCLK
- RT5645_PLL_CTRL1
- RT5645_PLL_CTRL2
- RT5645_PLL_INP_MAX
- RT5645_PLL_INP_MIN
- RT5645_PLL_K_MASK
- RT5645_PLL_K_MAX
- RT5645_PLL_K_SFT
- RT5645_PLL_M_BP
- RT5645_PLL_M_BP_SFT
- RT5645_PLL_M_MASK
- RT5645_PLL_M_MAX
- RT5645_PLL_M_SFT
- RT5645_PLL_N_MASK
- RT5645_PLL_N_MAX
- RT5645_PLL_N_SFT
- RT5645_PRIV_DATA
- RT5645_PRIV_INDEX
- RT5645_PROG_DIS
- RT5645_PROG_EN
- RT5645_PROG_MASK
- RT5645_PROG_SFT
- RT5645_PR_ALC_CTRL_1
- RT5645_PR_ALC_CTRL_2
- RT5645_PR_ALC_CTRL_3
- RT5645_PR_ALC_CTRL_4
- RT5645_PR_ALC_CTRL_5
- RT5645_PR_ALC_CTRL_6
- RT5645_PR_BASE
- RT5645_PR_RANGE_BASE
- RT5645_PR_SPACING
- RT5645_PVDD_DET_DIS
- RT5645_PVDD_DET_EN
- RT5645_PVDD_DET_MASK
- RT5645_PVDD_DET_SFT
- RT5645_PWR_ADC_L
- RT5645_PWR_ADC_L_BIT
- RT5645_PWR_ADC_MF_L
- RT5645_PWR_ADC_MF_L_BIT
- RT5645_PWR_ADC_MF_R
- RT5645_PWR_ADC_MF_R_BIT
- RT5645_PWR_ADC_R
- RT5645_PWR_ADC_R_BIT
- RT5645_PWR_ADC_S1F
- RT5645_PWR_ADC_S1F_BIT
- RT5645_PWR_ANLG1
- RT5645_PWR_ANLG2
- RT5645_PWR_BG
- RT5645_PWR_BG_BIT
- RT5645_PWR_BST1
- RT5645_PWR_BST1_BIT
- RT5645_PWR_BST2
- RT5645_PWR_BST2_BIT
- RT5645_PWR_BST2_P
- RT5645_PWR_BST2_P_BIT
- RT5645_PWR_BST3
- RT5645_PWR_BST3_BIT
- RT5645_PWR_BST3_P
- RT5645_PWR_BST3_P_BIT
- RT5645_PWR_BST4
- RT5645_PWR_BST4_BIT
- RT5645_PWR_BST4_P
- RT5645_PWR_BST4_P_BIT
- RT5645_PWR_CLK25M_MASK
- RT5645_PWR_CLK25M_PD
- RT5645_PWR_CLK25M_PU
- RT5645_PWR_CLK25M_SFT
- RT5645_PWR_CLS_D
- RT5645_PWR_CLS_D_BIT
- RT5645_PWR_CLS_D_L
- RT5645_PWR_CLS_D_L_BIT
- RT5645_PWR_CLS_D_R
- RT5645_PWR_CLS_D_R_BIT
- RT5645_PWR_DAC_L1
- RT5645_PWR_DAC_L1_BIT
- RT5645_PWR_DAC_L2
- RT5645_PWR_DAC_L2_BIT
- RT5645_PWR_DAC_MF_L
- RT5645_PWR_DAC_MF_L_BIT
- RT5645_PWR_DAC_MF_R
- RT5645_PWR_DAC_MF_R_BIT
- RT5645_PWR_DAC_R1
- RT5645_PWR_DAC_R1_BIT
- RT5645_PWR_DAC_R2
- RT5645_PWR_DAC_R2_BIT
- RT5645_PWR_DAC_S1F
- RT5645_PWR_DAC_S1F_BIT
- RT5645_PWR_DIG1
- RT5645_PWR_DIG2
- RT5645_PWR_FV1
- RT5645_PWR_FV1_BIT
- RT5645_PWR_FV2
- RT5645_PWR_FV2_BIT
- RT5645_PWR_HA
- RT5645_PWR_HA_BIT
- RT5645_PWR_HM_L
- RT5645_PWR_HM_L_BIT
- RT5645_PWR_HM_R
- RT5645_PWR_HM_R_BIT
- RT5645_PWR_HP_L
- RT5645_PWR_HP_L_BIT
- RT5645_PWR_HP_R
- RT5645_PWR_HP_R_BIT
- RT5645_PWR_HV_L
- RT5645_PWR_HV_L_BIT
- RT5645_PWR_HV_R
- RT5645_PWR_HV_R_BIT
- RT5645_PWR_I2S1
- RT5645_PWR_I2S1_BIT
- RT5645_PWR_I2S2
- RT5645_PWR_I2S2_BIT
- RT5645_PWR_I2S3
- RT5645_PWR_I2S3_BIT
- RT5645_PWR_I2S_DSP
- RT5645_PWR_I2S_DSP_BIT
- RT5645_PWR_IN_L
- RT5645_PWR_IN_L_BIT
- RT5645_PWR_IN_R
- RT5645_PWR_IN_R_BIT
- RT5645_PWR_IPTV
- RT5645_PWR_IPTV_BIT
- RT5645_PWR_JD
- RT5645_PWR_JD1
- RT5645_PWR_JD1_BIT
- RT5645_PWR_JD_BIT
- RT5645_PWR_LDO2
- RT5645_PWR_LDO2_BIT
- RT5645_PWR_LM
- RT5645_PWR_LM_BIT
- RT5645_PWR_MA
- RT5645_PWR_MA_BIT
- RT5645_PWR_MB
- RT5645_PWR_MB1
- RT5645_PWR_MB1_BIT
- RT5645_PWR_MB2
- RT5645_PWR_MB2_BIT
- RT5645_PWR_MB_BIT
- RT5645_PWR_MB_MASK
- RT5645_PWR_MB_PD
- RT5645_PWR_MB_PU
- RT5645_PWR_MB_SFT
- RT5645_PWR_MIC_DET
- RT5645_PWR_MIC_DET_BIT
- RT5645_PWR_MIXER
- RT5645_PWR_MM
- RT5645_PWR_MM_BIT
- RT5645_PWR_OM_L
- RT5645_PWR_OM_L_BIT
- RT5645_PWR_OM_R
- RT5645_PWR_OM_R_BIT
- RT5645_PWR_PAD
- RT5645_PWR_PAD_BIT
- RT5645_PWR_PDM1
- RT5645_PWR_PDM1_BIT
- RT5645_PWR_PDM2
- RT5645_PWR_PDM2_BIT
- RT5645_PWR_PLL
- RT5645_PWR_PLL_BIT
- RT5645_PWR_RM_L
- RT5645_PWR_RM_L_BIT
- RT5645_PWR_RM_R
- RT5645_PWR_RM_R_BIT
- RT5645_PWR_SM_L
- RT5645_PWR_SM_L_BIT
- RT5645_PWR_SM_R
- RT5645_PWR_SM_R_BIT
- RT5645_PWR_SV_L
- RT5645_PWR_SV_L_BIT
- RT5645_PWR_SV_R
- RT5645_PWR_SV_R_BIT
- RT5645_PWR_VOL
- RT5645_PWR_VREF1
- RT5645_PWR_VREF1_BIT
- RT5645_PWR_VREF2
- RT5645_PWR_VREF2_BIT
- RT5645_RAMP_DIS
- RT5645_RAMP_EN
- RT5645_RAMP_MASK
- RT5645_RAMP_SFT
- RT5645_REC_L1_MIXER
- RT5645_REC_L2_MIXER
- RT5645_REC_R1_MIXER
- RT5645_REC_R2_MIXER
- RT5645_REG_DAT_MASK
- RT5645_REG_DAT_SFT
- RT5645_REG_DISP_LEN
- RT5645_REG_IDX_MASK
- RT5645_REG_IDX_SFT
- RT5645_REG_LV_MASK
- RT5645_REG_LV_MX
- RT5645_REG_LV_PR
- RT5645_REG_LV_SFT
- RT5645_REG_SEQ_MASK
- RT5645_REG_SEQ_SFT
- RT5645_RESET
- RT5645_RING2_SLEEVE_GND
- RT5645_RSTN_DIS
- RT5645_RSTN_EN
- RT5645_RSTN_MASK
- RT5645_RSTN_SFT
- RT5645_RSTP_DIS
- RT5645_RSTP_EN
- RT5645_RSTP_MASK
- RT5645_RSTP_SFT
- RT5645_RST_DSP
- RT5645_RXDC_SRC_MASK
- RT5645_RXDC_SRC_MONO
- RT5645_RXDC_SRC_SFT
- RT5645_RXDC_SRC_STO
- RT5645_RXDP2_SEL_ADC
- RT5645_RXDP2_SEL_IF2
- RT5645_RXDP2_SEL_MASK
- RT5645_RXDP2_SEL_SFT
- RT5645_R_MUTE
- RT5645_R_MUTE_SFT
- RT5645_R_VOL_MASK
- RT5645_R_VOL_SFT
- RT5645_SCB_DIS
- RT5645_SCB_EN
- RT5645_SCB_KEY_MASK
- RT5645_SCB_KEY_SFT
- RT5645_SCB_MASK
- RT5645_SCB_SFT
- RT5645_SCB_SWAP_DIS
- RT5645_SCB_SWAP_EN
- RT5645_SCB_SWAP_MASK
- RT5645_SCB_SWAP_SFT
- RT5645_SCLK_SRC_MASK
- RT5645_SCLK_SRC_MCLK
- RT5645_SCLK_SRC_PLL1
- RT5645_SCLK_SRC_RCCLK
- RT5645_SCLK_SRC_SFT
- RT5645_SCLK_S_MCLK
- RT5645_SCLK_S_PLL1
- RT5645_SCLK_S_RCCLK
- RT5645_SEQ1_END_MASK
- RT5645_SEQ1_END_SFT
- RT5645_SEQ1_PT_RUN
- RT5645_SEQ1_PT_RUN_BIT
- RT5645_SEQ1_START_MASK
- RT5645_SEQ1_START_SFT
- RT5645_SEQ1_ST_FIN
- RT5645_SEQ1_ST_MASK
- RT5645_SEQ1_ST_RUN
- RT5645_SEQ1_ST_SFT
- RT5645_SEQ2_END_MASK
- RT5645_SEQ2_END_SFT
- RT5645_SEQ2_PT_RUN
- RT5645_SEQ2_PT_RUN_BIT
- RT5645_SEQ2_START_MASK
- RT5645_SEQ2_START_SFT
- RT5645_SEQ2_ST_FIN
- RT5645_SEQ2_ST_MASK
- RT5645_SEQ2_ST_RUN
- RT5645_SEQ2_ST_SFT
- RT5645_SEQ_2_PT_BIT
- RT5645_SEQ_2_PT_MASK
- RT5645_SEQ_DLY_MASK
- RT5645_SEQ_DLY_SFT
- RT5645_SI_DAC_AUTO
- RT5645_SI_DAC_MASK
- RT5645_SI_DAC_SFT
- RT5645_SI_DAC_TEST
- RT5645_SMT_TRIG_DIS
- RT5645_SMT_TRIG_EN
- RT5645_SMT_TRIG_MASK
- RT5645_SMT_TRIG_SFT
- RT5645_SPK_AG_DIS
- RT5645_SPK_AG_EN
- RT5645_SPK_AG_MASK
- RT5645_SPK_AG_SFT
- RT5645_SPK_FUNC_LIM
- RT5645_SPK_G_CLSD_MASK
- RT5645_SPK_G_CLSD_SFT
- RT5645_SPK_L_MIXER
- RT5645_SPK_R_MIXER
- RT5645_SPK_VOL
- RT5645_SPO_CLSD_RATIO
- RT5645_SPO_MIXER
- RT5645_SPO_SV_DIS
- RT5645_SPO_SV_EN
- RT5645_SPO_SV_MASK
- RT5645_SPO_SV_SFT
- RT5645_STEREO_RATES
- RT5645_STO1_ADC_COMP_MASK
- RT5645_STO1_ADC_COMP_SFT
- RT5645_STO1_ADC_DIG_VOL
- RT5645_STO1_ADC_L_BST_MASK
- RT5645_STO1_ADC_L_BST_SFT
- RT5645_STO1_ADC_MIXER
- RT5645_STO1_ADC_R_BST_MASK
- RT5645_STO1_ADC_R_BST_SFT
- RT5645_STO2_ADC_SRC_MASK
- RT5645_STO2_ADC_SRC_SFT
- RT5645_STORM
- RT5645_STO_DAC_MIXER
- RT5645_STO_L_DAC_L_VOL_MASK
- RT5645_STO_L_DAC_L_VOL_SFT
- RT5645_STO_R_DAC_R_VOL_MASK
- RT5645_STO_R_DAC_R_VOL_SFT
- RT5645_STO_T_LRCK1
- RT5645_STO_T_MASK
- RT5645_STO_T_SCLK
- RT5645_STO_T_SFT
- RT5645_SV_DIS
- RT5645_SV_DLY_MASK
- RT5645_SV_DLY_SFT
- RT5645_SV_EN
- RT5645_SV_MASK
- RT5645_SV_SFT
- RT5645_SV_ZCD1
- RT5645_SV_ZCD2
- RT5645_TDM_CTRL_1
- RT5645_TDM_CTRL_2
- RT5645_TDM_CTRL_3
- RT5645_VAD_CTRL4
- RT5645_VAD_SEL_MASK
- RT5645_VAD_SEL_SFT
- RT5645_VENDOR_ID
- RT5645_VENDOR_ID1
- RT5645_VENDOR_ID2
- RT5645_VER_C
- RT5645_VER_D
- RT5645_VLO_32V
- RT5645_VLO_3V
- RT5645_VLO_MASK
- RT5645_VLO_SFT
- RT5645_VOL_L_MUTE
- RT5645_VOL_L_SFT
- RT5645_VOL_RSCL_MAX
- RT5645_VOL_RSCL_RANGE
- RT5645_VOL_R_MUTE
- RT5645_VOL_R_SFT
- RT5645_WND_1
- RT5645_WND_2
- RT5645_WND_3
- RT5645_WND_4
- RT5645_WND_5
- RT5645_WND_8
- RT5645_WND_DIS
- RT5645_WND_EN
- RT5645_WND_FC_NW_MASK
- RT5645_WND_FC_NW_SFT
- RT5645_WND_FC_ST_MASK
- RT5645_WND_FC_ST_SFT
- RT5645_WND_FC_WK_MASK
- RT5645_WND_FC_WK_SFT
- RT5645_WND_MASK
- RT5645_WND_SFT
- RT5645_WND_STRONG_MASK
- RT5645_WND_STRONG_SFT
- RT5645_WND_TH_HI_MASK
- RT5645_WND_TH_HI_SFT
- RT5645_WND_TH_LO_MASK
- RT5645_WND_TH_LO_SFT
- RT5645_WND_WIND_MASK
- RT5645_WND_WIND_SFT
- RT5645_ZCD_DIG_DIS
- RT5645_ZCD_DIG_EN
- RT5645_ZCD_DIG_MASK
- RT5645_ZCD_DIG_SFT
- RT5645_ZCD_HP_DIS
- RT5645_ZCD_HP_EN
- RT5645_ZCD_HP_MASK
- RT5645_ZCD_HP_SFT
- RT5645_ZCD_MASK
- RT5645_ZCD_PD
- RT5645_ZCD_PU
- RT5645_ZCD_SFT
- RT5645_ZD_F_IM
- RT5645_ZD_F_MASK
- RT5645_ZD_F_SFT
- RT5645_ZD_F_UN
- RT5645_ZD_F_ZC_IM
- RT5645_ZD_F_ZC_IOD
- RT5645_ZD_T_MASK
- RT5645_ZD_T_SFT
- RT5650_4BTN_IL_CMD1
- RT5650_4BTN_IL_CMD2
- RT5650_A_DAC1_L_IN_SFT
- RT5650_A_DAC1_R_IN_SFT
- RT5650_A_DAC2_L_IN_SFT
- RT5650_A_DAC2_R_IN_SFT
- RT5650_A_DAC_SOUR
- RT5650_DEVICE_ID
- RT5650_TDM_CTRL_4
- RT5651_2ND_HPF_DIS
- RT5651_2ND_HPF_EN
- RT5651_2ND_HPF_MASK
- RT5651_2ND_HPF_SFT
- RT5651_3D_1F_MIX_MASK
- RT5651_3D_1F_MIX_SFT
- RT5651_3D_BT_DIS
- RT5651_3D_BT_EN
- RT5651_3D_BT_MASK
- RT5651_3D_BT_SFT
- RT5651_3D_CF_DIS
- RT5651_3D_CF_EN
- RT5651_3D_CF_MASK
- RT5651_3D_CF_SFT
- RT5651_3D_HP_DIS
- RT5651_3D_HP_EN
- RT5651_3D_HP_MASK
- RT5651_3D_HP_M_FRO
- RT5651_3D_HP_M_MASK
- RT5651_3D_HP_M_SFT
- RT5651_3D_HP_M_SUR
- RT5651_3D_HP_SFT
- RT5651_3D_SPK
- RT5651_3D_SPK_CG_MASK
- RT5651_3D_SPK_CG_SFT
- RT5651_3D_SPK_DIS
- RT5651_3D_SPK_EN
- RT5651_3D_SPK_MASK
- RT5651_3D_SPK_M_MASK
- RT5651_3D_SPK_M_SFT
- RT5651_3D_SPK_SFT
- RT5651_3D_SPK_SG_MASK
- RT5651_3D_SPK_SG_SFT
- RT5651_ADC_BST_VOL
- RT5651_ADC_COMP_MASK
- RT5651_ADC_COMP_SFT
- RT5651_ADC_DATA
- RT5651_ADC_DIG_VOL
- RT5651_ADC_L_BST_MASK
- RT5651_ADC_L_BST_SFT
- RT5651_ADC_L_VOL_MASK
- RT5651_ADC_L_VOL_SFT
- RT5651_ADC_M_ASRC
- RT5651_ADC_M_MASK
- RT5651_ADC_M_NOR
- RT5651_ADC_M_SFT
- RT5651_ADC_OSR_128
- RT5651_ADC_OSR_128_3
- RT5651_ADC_OSR_32
- RT5651_ADC_OSR_64
- RT5651_ADC_OSR_MASK
- RT5651_ADC_OSR_SFT
- RT5651_ADC_R_BST_MASK
- RT5651_ADC_R_BST_SFT
- RT5651_ADC_R_VOL_MASK
- RT5651_ADC_R_VOL_SFT
- RT5651_ADDA_CLK1
- RT5651_ADDA_CLK2
- RT5651_ADHPF_EN
- RT5651_ADHPF_EN_SFT
- RT5651_ADJ_HPF_CTRL1
- RT5651_ADJ_HPF_CTRL2
- RT5651_AD_DA_MIXER
- RT5651_AIF1
- RT5651_AIF2
- RT5651_AIFS
- RT5651_ALC_1
- RT5651_ALC_2
- RT5651_ALC_3
- RT5651_ALC_AR_MASK
- RT5651_ALC_AR_SFT
- RT5651_ALC_CPR_1_1
- RT5651_ALC_CPR_1_2
- RT5651_ALC_CPR_1_4
- RT5651_ALC_CPR_1_8
- RT5651_ALC_CPR_MASK
- RT5651_ALC_CPR_SFT
- RT5651_ALC_DIS
- RT5651_ALC_DRC_DIS
- RT5651_ALC_DRC_EN
- RT5651_ALC_DRC_MASK
- RT5651_ALC_DRC_SFT
- RT5651_ALC_EN
- RT5651_ALC_MASK
- RT5651_ALC_NGB_MASK
- RT5651_ALC_NGB_SFT
- RT5651_ALC_NGH_DIS
- RT5651_ALC_NGH_EN
- RT5651_ALC_NGH_MASK
- RT5651_ALC_NGH_SFT
- RT5651_ALC_NGT_MASK
- RT5651_ALC_NGT_SFT
- RT5651_ALC_NG_DIS
- RT5651_ALC_NG_EN
- RT5651_ALC_NG_MASK
- RT5651_ALC_NG_SFT
- RT5651_ALC_POB_MASK
- RT5651_ALC_POB_SFT
- RT5651_ALC_PRB_MASK
- RT5651_ALC_PRB_SFT
- RT5651_ALC_P_ADC
- RT5651_ALC_P_DAC
- RT5651_ALC_P_MASK
- RT5651_ALC_P_SFT
- RT5651_ALC_RC_MASK
- RT5651_ALC_RC_SFT
- RT5651_ALC_R_1764K
- RT5651_ALC_R_192K
- RT5651_ALC_R_441K
- RT5651_ALC_R_48K
- RT5651_ALC_R_882K
- RT5651_ALC_R_96K
- RT5651_ALC_R_MASK
- RT5651_ALC_R_SFT
- RT5651_ALC_SFT
- RT5651_ALC_TAR_MASK
- RT5651_ALC_TAR_SFT
- RT5651_ALC_UPD
- RT5651_ALC_UPD_BIT
- RT5651_AMP_DET_EN
- RT5651_AMP_DET_EN_SFT
- RT5651_ASRC2_REF_LRCK1
- RT5651_ASRC2_REF_LRCK2
- RT5651_ASRC2_REF_MASK
- RT5651_ASRC2_REF_SFT
- RT5651_ASRC_LP_F_M
- RT5651_ASRC_LP_F_NOR
- RT5651_ASRC_LP_F_SB
- RT5651_ASRC_LP_F_SFT
- RT5651_A_JD_CTL1
- RT5651_BASE_BACK
- RT5651_BB_CT_A
- RT5651_BB_CT_B
- RT5651_BB_CT_C
- RT5651_BB_CT_D
- RT5651_BB_CT_MASK
- RT5651_BB_CT_SFT
- RT5651_BB_DIS
- RT5651_BB_EN
- RT5651_BB_MASK
- RT5651_BB_SFT
- RT5651_BIAS_CUR1
- RT5651_BIAS_CUR3
- RT5651_BIAS_CUR4
- RT5651_BPS_DIS
- RT5651_BPS_EN
- RT5651_BPS_MASK
- RT5651_BPS_SFT
- RT5651_BREEZE
- RT5651_BST_MASK1
- RT5651_BST_MASK2
- RT5651_BST_SFT1
- RT5651_BST_SFT2
- RT5651_CAL_DIS
- RT5651_CAL_EN
- RT5651_CAL_MASK
- RT5651_CAL_M_CAL
- RT5651_CAL_M_DEP
- RT5651_CAL_M_MASK
- RT5651_CAL_M_SFT
- RT5651_CAL_P_CAL
- RT5651_CAL_P_DAC_CAL
- RT5651_CAL_P_MASK
- RT5651_CAL_P_NONE
- RT5651_CAL_P_SFT
- RT5651_CAL_SFT
- RT5651_CAL_TEST_DIS
- RT5651_CAL_TEST_EN
- RT5651_CAL_TEST_MASK
- RT5651_CAL_TEST_SFT
- RT5651_CH2_L_SEL_MASK
- RT5651_CH2_L_SEL_SFT
- RT5651_CH2_L_SEL_SL0
- RT5651_CH2_L_SEL_SL1
- RT5651_CH2_L_SEL_SL2
- RT5651_CH2_L_SEL_SL3
- RT5651_CH2_L_SEL_SL4
- RT5651_CH2_L_SEL_SL5
- RT5651_CH2_L_SEL_SL6
- RT5651_CH2_L_SEL_SL7
- RT5651_CH2_R_SEL_MASK
- RT5651_CH2_R_SEL_SFT
- RT5651_CH2_R_SEL_SL0
- RT5651_CH2_R_SEL_SL1
- RT5651_CH2_R_SEL_SL2
- RT5651_CH2_R_SEL_SL3
- RT5651_CH2_R_SEL_SL4
- RT5651_CH2_R_SEL_SL5
- RT5651_CH2_R_SEL_SL6
- RT5651_CH2_R_SEL_SL7
- RT5651_CH4_L_SEL_MASK
- RT5651_CH4_L_SEL_SFT
- RT5651_CH4_L_SEL_SL0
- RT5651_CH4_L_SEL_SL1
- RT5651_CH4_L_SEL_SL2
- RT5651_CH4_L_SEL_SL3
- RT5651_CH4_L_SEL_SL4
- RT5651_CH4_L_SEL_SL5
- RT5651_CH4_L_SEL_SL6
- RT5651_CH4_L_SEL_SL7
- RT5651_CH4_R_SEL_MASK
- RT5651_CH4_R_SEL_SFT
- RT5651_CH4_R_SEL_SL0
- RT5651_CH4_R_SEL_SL1
- RT5651_CH4_R_SEL_SL2
- RT5651_CH4_R_SEL_SL3
- RT5651_CH4_R_SEL_SL4
- RT5651_CH4_R_SEL_SL5
- RT5651_CH4_R_SEL_SL6
- RT5651_CH4_R_SEL_SL7
- RT5651_CHARGE_PUMP
- RT5651_CHOP_DAC_ADC
- RT5651_CHPUMP_INT_REG1
- RT5651_CLK_DET_EN
- RT5651_CLK_DET_EN_SFT
- RT5651_CLSD_INT_REG1
- RT5651_CP_FQ1_MASK
- RT5651_CP_FQ1_SFT
- RT5651_CP_FQ2_MASK
- RT5651_CP_FQ2_SFT
- RT5651_CP_FQ3_MASK
- RT5651_CP_FQ3_SFT
- RT5651_CP_FQ_12_KHZ
- RT5651_CP_FQ_192_KHZ
- RT5651_CP_FQ_1_5_KHZ
- RT5651_CP_FQ_24_KHZ
- RT5651_CP_FQ_3_KHZ
- RT5651_CP_FQ_48_KHZ
- RT5651_CP_FQ_6_KHZ
- RT5651_CP_FQ_96_KHZ
- RT5651_CP_SYS_MASK
- RT5651_CP_SYS_SFT
- RT5651_DAC1_DIG_VOL
- RT5651_DAC2_CTRL
- RT5651_DAC2_DIG_VOL
- RT5651_DAC_DD_L1_VOL_SFT
- RT5651_DAC_L1_STO_L_VOL_MASK
- RT5651_DAC_L1_STO_L_VOL_SFT
- RT5651_DAC_L1_STO_R_VOL_MASK
- RT5651_DAC_L1_STO_R_VOL_SFT
- RT5651_DAC_L1_VOL_MASK
- RT5651_DAC_L1_VOL_SFT
- RT5651_DAC_L2_DAC_L_VOL_MASK
- RT5651_DAC_L2_DAC_L_VOL_SFT
- RT5651_DAC_L2_SEL_BASS
- RT5651_DAC_L2_SEL_IF2
- RT5651_DAC_L2_SEL_IF3
- RT5651_DAC_L2_SEL_MASK
- RT5651_DAC_L2_SEL_SFT
- RT5651_DAC_L2_SEL_TXDC
- RT5651_DAC_L2_STO_L_VOL_MASK
- RT5651_DAC_L2_STO_L_VOL_SFT
- RT5651_DAC_L2_VOL_MASK
- RT5651_DAC_L2_VOL_SFT
- RT5651_DAC_OSR_128
- RT5651_DAC_OSR_128_3
- RT5651_DAC_OSR_32
- RT5651_DAC_OSR_64
- RT5651_DAC_OSR_MASK
- RT5651_DAC_OSR_SFT
- RT5651_DAC_R1_STO_L_VOL_MASK
- RT5651_DAC_R1_STO_L_VOL_SFT
- RT5651_DAC_R1_STO_R_VOL_MASK
- RT5651_DAC_R1_STO_R_VOL_SFT
- RT5651_DAC_R1_VOL_MASK
- RT5651_DAC_R1_VOL_SFT
- RT5651_DAC_R2_DAC_R_VOL_MASK
- RT5651_DAC_R2_DAC_R_VOL_SFT
- RT5651_DAC_R2_SEL_IF2
- RT5651_DAC_R2_SEL_IF3
- RT5651_DAC_R2_SEL_MASK
- RT5651_DAC_R2_SEL_SFT
- RT5651_DAC_R2_SEL_TXDC
- RT5651_DAC_R2_STO_R_VOL_MASK
- RT5651_DAC_R2_STO_R_VOL_SFT
- RT5651_DAC_R2_VOL_MASK
- RT5651_DAC_R2_VOL_SFT
- RT5651_DAHPF_EN
- RT5651_DAHPF_EN_SFT
- RT5651_DC_CAL_DIS
- RT5651_DC_CAL_EN
- RT5651_DC_CAL_MASK
- RT5651_DC_CAL_M_CAL
- RT5651_DC_CAL_M_MASK
- RT5651_DC_CAL_M_NOR
- RT5651_DC_CAL_M_SFT
- RT5651_DC_CAL_SFT
- RT5651_DD_MIXER
- RT5651_DEPOP_AUTO
- RT5651_DEPOP_M1
- RT5651_DEPOP_M2
- RT5651_DEPOP_M3
- RT5651_DEPOP_MAN
- RT5651_DEPOP_MASK
- RT5651_DEPOP_SFT
- RT5651_DEVICE_ID
- RT5651_DEVICE_ID_VALUE
- RT5651_DIG_DP_DIS
- RT5651_DIG_DP_EN
- RT5651_DIG_DP_MASK
- RT5651_DIG_DP_SFT
- RT5651_DIG_INF_DATA
- RT5651_DIP_SPK_INF
- RT5651_DMIC
- RT5651_DMIC_1L_LH_FALLING
- RT5651_DMIC_1L_LH_MASK
- RT5651_DMIC_1L_LH_RISING
- RT5651_DMIC_1L_LH_SFT
- RT5651_DMIC_1R_LH_FALLING
- RT5651_DMIC_1R_LH_MASK
- RT5651_DMIC_1R_LH_RISING
- RT5651_DMIC_1R_LH_SFT
- RT5651_DMIC_1_DIS
- RT5651_DMIC_1_DP_GPIO6
- RT5651_DMIC_1_DP_IN1P
- RT5651_DMIC_1_DP_MASK
- RT5651_DMIC_1_DP_SFT
- RT5651_DMIC_1_EN
- RT5651_DMIC_1_EN_MASK
- RT5651_DMIC_1_EN_SFT
- RT5651_DMIC_1_M_ASYN
- RT5651_DMIC_1_M_MASK
- RT5651_DMIC_1_M_NOR
- RT5651_DMIC_1_M_SFT
- RT5651_DMIC_2_DP_GPIO8
- RT5651_DMIC_CLK_MASK
- RT5651_DMIC_CLK_SFT
- RT5651_DP_ATT_MASK
- RT5651_DP_ATT_SFT
- RT5651_DP_SPK_DIS
- RT5651_DP_SPK_EN
- RT5651_DP_SPK_MASK
- RT5651_DP_SPK_SFT
- RT5651_DP_TH_MASK
- RT5651_DP_TH_SFT
- RT5651_DUMMY2
- RT5651_DUMMY3
- RT5651_D_GATE_EN
- RT5651_D_GATE_EN_SFT
- RT5651_D_MISC
- RT5651_EG_MP3_MASK
- RT5651_EG_MP3_SFT
- RT5651_EN_DFO
- RT5651_EQ_BPF1_DIS
- RT5651_EQ_BPF1_EN
- RT5651_EQ_BPF1_MASK
- RT5651_EQ_BPF1_SFT
- RT5651_EQ_BPF2_DIS
- RT5651_EQ_BPF2_EN
- RT5651_EQ_BPF2_MASK
- RT5651_EQ_BPF2_SFT
- RT5651_EQ_BPF3_DIS
- RT5651_EQ_BPF3_EN
- RT5651_EQ_BPF3_MASK
- RT5651_EQ_BPF3_SFT
- RT5651_EQ_BPF4_DIS
- RT5651_EQ_BPF4_EN
- RT5651_EQ_BPF4_MASK
- RT5651_EQ_BPF4_SFT
- RT5651_EQ_BW_BP1
- RT5651_EQ_BW_BP2
- RT5651_EQ_BW_BP3
- RT5651_EQ_BW_BP4
- RT5651_EQ_BW_HIP2
- RT5651_EQ_BW_LOP
- RT5651_EQ_CD_DIS
- RT5651_EQ_CD_EN
- RT5651_EQ_CD_F
- RT5651_EQ_CD_F_BIT
- RT5651_EQ_CD_MASK
- RT5651_EQ_CD_SFT
- RT5651_EQ_CTRL1
- RT5651_EQ_CTRL2
- RT5651_EQ_CTRL_MASK
- RT5651_EQ_DITH_LSB
- RT5651_EQ_DITH_LSB_1
- RT5651_EQ_DITH_LSB_2
- RT5651_EQ_DITH_MASK
- RT5651_EQ_DITH_NOR
- RT5651_EQ_DITH_SFT
- RT5651_EQ_FC_BP1
- RT5651_EQ_FC_BP2
- RT5651_EQ_FC_BP3
- RT5651_EQ_FC_BP4
- RT5651_EQ_FC_HIP1
- RT5651_EQ_FC_HIP2
- RT5651_EQ_GN_BP1
- RT5651_EQ_GN_BP2
- RT5651_EQ_GN_BP3
- RT5651_EQ_GN_BP4
- RT5651_EQ_GN_HIP1
- RT5651_EQ_GN_HIP2
- RT5651_EQ_GN_LOP
- RT5651_EQ_HPF1_DIS
- RT5651_EQ_HPF1_EN
- RT5651_EQ_HPF1_MASK
- RT5651_EQ_HPF1_M_1ST
- RT5651_EQ_HPF1_M_HI
- RT5651_EQ_HPF1_M_MASK
- RT5651_EQ_HPF1_M_SFT
- RT5651_EQ_HPF1_SFT
- RT5651_EQ_HPF2_DIS
- RT5651_EQ_HPF2_EN
- RT5651_EQ_HPF2_MASK
- RT5651_EQ_HPF2_SFT
- RT5651_EQ_LPF1_M_1ST
- RT5651_EQ_LPF1_M_LO
- RT5651_EQ_LPF1_M_MASK
- RT5651_EQ_LPF1_M_SFT
- RT5651_EQ_LPF_DIS
- RT5651_EQ_LPF_EN
- RT5651_EQ_LPF_MASK
- RT5651_EQ_LPF_SFT
- RT5651_EQ_PRE_VOL
- RT5651_EQ_PRE_VOL_MASK
- RT5651_EQ_PRE_VOL_SFT
- RT5651_EQ_PST_VOL
- RT5651_EQ_PST_VOL_MASK
- RT5651_EQ_PST_VOL_SFT
- RT5651_EQ_SRC_ADC
- RT5651_EQ_SRC_DAC
- RT5651_EQ_SRC_MASK
- RT5651_EQ_SRC_SFT
- RT5651_EQ_STA_BP1
- RT5651_EQ_STA_BP1_BIT
- RT5651_EQ_STA_BP2
- RT5651_EQ_STA_BP2_BIT
- RT5651_EQ_STA_BP3
- RT5651_EQ_STA_BP3_BIT
- RT5651_EQ_STA_BP4
- RT5651_EQ_STA_BP4_BIT
- RT5651_EQ_STA_HP1
- RT5651_EQ_STA_HP1_BIT
- RT5651_EQ_STA_HP2
- RT5651_EQ_STA_HP2_BIT
- RT5651_EQ_STA_LP
- RT5651_EQ_STA_LP_BIT
- RT5651_EQ_UPD
- RT5651_EQ_UPD_BIT
- RT5651_FAST_UPDN_DIS
- RT5651_FAST_UPDN_EN
- RT5651_FAST_UPDN_MASK
- RT5651_FAST_UPDN_SFT
- RT5651_FORMATS
- RT5651_FSI1_RATE_MASK
- RT5651_FSI1_RATE_SFT
- RT5651_FSI2_RATE_MASK
- RT5651_FSI2_RATE_SFT
- RT5651_FTK_PH_DET_DIV1
- RT5651_FTK_PH_DET_DIV2
- RT5651_FTK_PH_DET_DIV4
- RT5651_FTK_PH_DET_DIV8
- RT5651_FTK_PH_DET_MASK
- RT5651_FTK_PH_DET_SFT
- RT5651_GLB_CLK
- RT5651_GP1_DR_IN
- RT5651_GP1_DR_MASK
- RT5651_GP1_DR_OUT
- RT5651_GP1_DR_SFT
- RT5651_GP1_OUT_HI
- RT5651_GP1_OUT_LO
- RT5651_GP1_OUT_MASK
- RT5651_GP1_OUT_SFT
- RT5651_GP1_PIN_GPIO1
- RT5651_GP1_PIN_IRQ
- RT5651_GP1_PIN_MASK
- RT5651_GP1_PIN_SFT
- RT5651_GP1_P_INV
- RT5651_GP1_P_MASK
- RT5651_GP1_P_NOR
- RT5651_GP1_P_SFT
- RT5651_GP2_DR_IN
- RT5651_GP2_DR_MASK
- RT5651_GP2_DR_OUT
- RT5651_GP2_DR_SFT
- RT5651_GP2_OUT_HI
- RT5651_GP2_OUT_LO
- RT5651_GP2_OUT_MASK
- RT5651_GP2_OUT_SFT
- RT5651_GP2_PIN_DMIC1_SCL
- RT5651_GP2_PIN_GPIO2
- RT5651_GP2_PIN_MASK
- RT5651_GP2_PIN_SFT
- RT5651_GP2_P_INV
- RT5651_GP2_P_MASK
- RT5651_GP2_P_NOR
- RT5651_GP2_P_SFT
- RT5651_GP3_DR_IN
- RT5651_GP3_DR_MASK
- RT5651_GP3_DR_OUT
- RT5651_GP3_DR_SFT
- RT5651_GP3_OUT_HI
- RT5651_GP3_OUT_LO
- RT5651_GP3_OUT_MASK
- RT5651_GP3_OUT_SFT
- RT5651_GP3_P_INV
- RT5651_GP3_P_MASK
- RT5651_GP3_P_NOR
- RT5651_GP3_P_SFT
- RT5651_GP4_DR_IN
- RT5651_GP4_DR_MASK
- RT5651_GP4_DR_OUT
- RT5651_GP4_DR_SFT
- RT5651_GP4_OUT_HI
- RT5651_GP4_OUT_LO
- RT5651_GP4_OUT_MASK
- RT5651_GP4_OUT_SFT
- RT5651_GP4_P_INV
- RT5651_GP4_P_MASK
- RT5651_GP4_P_NOR
- RT5651_GP4_P_SFT
- RT5651_GP5_DR_IN
- RT5651_GP5_DR_MASK
- RT5651_GP5_DR_OUT
- RT5651_GP5_DR_SFT
- RT5651_GP5_OUT_HI
- RT5651_GP5_OUT_LO
- RT5651_GP5_OUT_MASK
- RT5651_GP5_OUT_SFT
- RT5651_GP5_PIN_GPIO5
- RT5651_GP5_PIN_IRQ
- RT5651_GP5_PIN_MASK
- RT5651_GP5_PIN_SFT
- RT5651_GP5_P_INV
- RT5651_GP5_P_MASK
- RT5651_GP5_P_NOR
- RT5651_GP5_P_SFT
- RT5651_GP6_DR_IN
- RT5651_GP6_DR_MASK
- RT5651_GP6_DR_OUT
- RT5651_GP6_DR_SFT
- RT5651_GP6_OUT_HI
- RT5651_GP6_OUT_LO
- RT5651_GP6_OUT_MASK
- RT5651_GP6_OUT_SFT
- RT5651_GP6_PIN_DMIC_SDA
- RT5651_GP6_PIN_GPIO6
- RT5651_GP6_PIN_MASK
- RT5651_GP6_PIN_SFT
- RT5651_GP6_P_INV
- RT5651_GP6_P_MASK
- RT5651_GP6_P_NOR
- RT5651_GP6_P_SFT
- RT5651_GP7_DR_IN
- RT5651_GP7_DR_MASK
- RT5651_GP7_DR_OUT
- RT5651_GP7_DR_SFT
- RT5651_GP7_OUT_HI
- RT5651_GP7_OUT_LO
- RT5651_GP7_OUT_MASK
- RT5651_GP7_OUT_SFT
- RT5651_GP7_PIN_GPIO7
- RT5651_GP7_PIN_IRQ
- RT5651_GP7_PIN_MASK
- RT5651_GP7_PIN_SFT
- RT5651_GP7_P_INV
- RT5651_GP7_P_MASK
- RT5651_GP7_P_NOR
- RT5651_GP7_P_SFT
- RT5651_GP8_DR_IN
- RT5651_GP8_DR_MASK
- RT5651_GP8_DR_OUT
- RT5651_GP8_DR_SFT
- RT5651_GP8_OUT_HI
- RT5651_GP8_OUT_LO
- RT5651_GP8_OUT_MASK
- RT5651_GP8_OUT_SFT
- RT5651_GP8_PIN_DMIC_SDA
- RT5651_GP8_PIN_GPIO8
- RT5651_GP8_PIN_MASK
- RT5651_GP8_PIN_SFT
- RT5651_GP8_P_INV
- RT5651_GP8_P_MASK
- RT5651_GP8_P_NOR
- RT5651_GP8_P_SFT
- RT5651_GPIO_CTRL1
- RT5651_GPIO_CTRL2
- RT5651_GPIO_CTRL3
- RT5651_GPIO_M_FLT
- RT5651_GPIO_M_MASK
- RT5651_GPIO_M_PH
- RT5651_GPIO_M_SFT
- RT5651_GPIO_PDM_SEL_GPIO
- RT5651_GPIO_PDM_SEL_MASK
- RT5651_GPIO_PDM_SEL_PDM
- RT5651_GPIO_PDM_SEL_SFT
- RT5651_G_ASRC_LP_MASK
- RT5651_G_ASRC_LP_SFT
- RT5651_G_BB_BST_MASK
- RT5651_G_BB_BST_SFT
- RT5651_G_BST1_OM_L_MASK
- RT5651_G_BST1_OM_L_SFT
- RT5651_G_BST1_OM_R_MASK
- RT5651_G_BST1_OM_R_SFT
- RT5651_G_BST1_RM_L_MASK
- RT5651_G_BST1_RM_L_SFT
- RT5651_G_BST1_RM_R_MASK
- RT5651_G_BST1_RM_R_SFT
- RT5651_G_BST2_OM_L_MASK
- RT5651_G_BST2_OM_L_SFT
- RT5651_G_BST2_OM_R_MASK
- RT5651_G_BST2_OM_R_SFT
- RT5651_G_BST2_RM_L_MASK
- RT5651_G_BST2_RM_L_SFT
- RT5651_G_BST2_RM_R_MASK
- RT5651_G_BST2_RM_R_SFT
- RT5651_G_BST3_RM_L_MASK
- RT5651_G_BST3_RM_L_SFT
- RT5651_G_BST3_RM_R_MASK
- RT5651_G_BST3_RM_R_SFT
- RT5651_G_DAC_L1_OM_L_MASK
- RT5651_G_DAC_L1_OM_L_SFT
- RT5651_G_DAC_L1_SM_L_MASK
- RT5651_G_DAC_L1_SM_L_SFT
- RT5651_G_DAC_L2_SM_L_MASK
- RT5651_G_DAC_L2_SM_L_SFT
- RT5651_G_DAC_R1_OM_R_MASK
- RT5651_G_DAC_R1_OM_R_SFT
- RT5651_G_DAC_R1_SM_R_MASK
- RT5651_G_DAC_R1_SM_R_SFT
- RT5651_G_DAC_R2_SM_R_MASK
- RT5651_G_DAC_R2_SM_R_SFT
- RT5651_G_HPOMIX_MASK
- RT5651_G_HPOMIX_SFT
- RT5651_G_IN1_L_OM_L_MASK
- RT5651_G_IN1_L_OM_L_SFT
- RT5651_G_IN1_R_OM_R_MASK
- RT5651_G_IN1_R_OM_R_SFT
- RT5651_G_IN1_R_RM_R_MASK
- RT5651_G_IN1_R_RM_R_SFT
- RT5651_G_IN2_L_OM_L_MASK
- RT5651_G_IN2_L_OM_L_SFT
- RT5651_G_IN2_R_OM_R_MASK
- RT5651_G_IN2_R_OM_R_SFT
- RT5651_G_IN2_R_RM_R_MASK
- RT5651_G_IN2_R_RM_R_SFT
- RT5651_G_IN_L1_RM_L_SFT
- RT5651_G_IN_L2_RM_L_SFT
- RT5651_G_IN_L_SM_L_MASK
- RT5651_G_IN_L_SM_L_SFT
- RT5651_G_IN_R_SM_R_MASK
- RT5651_G_IN_R_SM_R_SFT
- RT5651_G_LN_L1_RM_L_MASK
- RT5651_G_LN_L2_RM_L_MASK
- RT5651_G_LOUTMIX_MASK
- RT5651_G_LOUTMIX_SFT
- RT5651_G_MONOMIX_MASK
- RT5651_G_MONOMIX_SFT
- RT5651_G_OM_L_RM_L_MASK
- RT5651_G_OM_L_RM_L_SFT
- RT5651_G_OM_L_SM_L_MASK
- RT5651_G_OM_L_SM_L_SFT
- RT5651_G_OM_R_RM_R_MASK
- RT5651_G_OM_R_RM_R_SFT
- RT5651_G_OM_R_SM_R_MASK
- RT5651_G_OM_R_SM_R_SFT
- RT5651_G_RM_L_OM_L_MASK
- RT5651_G_RM_L_OM_L_SFT
- RT5651_G_RM_L_SM_L_MASK
- RT5651_G_RM_L_SM_L_SFT
- RT5651_G_RM_R_OM_R_MASK
- RT5651_G_RM_R_OM_R_SFT
- RT5651_G_RM_R_SM_R_MASK
- RT5651_G_RM_R_SM_R_SFT
- RT5651_HG_MP3_MASK
- RT5651_HG_MP3_SFT
- RT5651_HPD_PS_DIS
- RT5651_HPD_PS_EN
- RT5651_HPD_PS_MASK
- RT5651_HPD_PS_SFT
- RT5651_HPD_RCV_MASK
- RT5651_HPD_RCV_SFT
- RT5651_HPF_CF_L_MASK
- RT5651_HPF_CF_L_NUM_MASK
- RT5651_HPF_CF_L_NUM_SFT
- RT5651_HPF_CF_L_SFT
- RT5651_HPF_CF_R_MASK
- RT5651_HPF_CF_R_NUM_MASK
- RT5651_HPF_CF_R_NUM_SFT
- RT5651_HPF_CF_R_SFT
- RT5651_HPF_FC_MASK
- RT5651_HPF_FC_SFT
- RT5651_HPO_MIXER
- RT5651_HP_CALIB2
- RT5651_HP_CALIB_AMP_DET
- RT5651_HP_CB_MASK
- RT5651_HP_CB_PD
- RT5651_HP_CB_PU
- RT5651_HP_CB_SFT
- RT5651_HP_CD_PD_DIS
- RT5651_HP_CD_PD_EN
- RT5651_HP_CD_PD_MASK
- RT5651_HP_CD_PD_SFT
- RT5651_HP_CO_DIS
- RT5651_HP_CO_EN
- RT5651_HP_CO_MASK
- RT5651_HP_CO_SFT
- RT5651_HP_CP_MASK
- RT5651_HP_CP_PD
- RT5651_HP_CP_PU
- RT5651_HP_CP_SFT
- RT5651_HP_DCC_INT1
- RT5651_HP_DP_MASK
- RT5651_HP_DP_PD
- RT5651_HP_DP_PU
- RT5651_HP_DP_SFT
- RT5651_HP_L_SMT_DIS
- RT5651_HP_L_SMT_EN
- RT5651_HP_L_SMT_MASK
- RT5651_HP_L_SMT_SFT
- RT5651_HP_OC_TH_105
- RT5651_HP_OC_TH_120
- RT5651_HP_OC_TH_135
- RT5651_HP_OC_TH_90
- RT5651_HP_OC_TH_MASK
- RT5651_HP_OC_TH_SFT
- RT5651_HP_OVCD_DIS
- RT5651_HP_OVCD_EN
- RT5651_HP_OVCD_MASK
- RT5651_HP_OVCD_SFT
- RT5651_HP_R_SMT_DIS
- RT5651_HP_R_SMT_EN
- RT5651_HP_R_SMT_MASK
- RT5651_HP_R_SMT_SFT
- RT5651_HP_SG_DIS
- RT5651_HP_SG_EN
- RT5651_HP_SG_MASK
- RT5651_HP_SG_SFT
- RT5651_HP_SV_DIS
- RT5651_HP_SV_EN
- RT5651_HP_SV_MASK
- RT5651_HP_SV_SFT
- RT5651_HP_VOL
- RT5651_I2S1_PD_MASK
- RT5651_I2S1_PD_SFT
- RT5651_I2S1_RATE_MASK
- RT5651_I2S1_RATE_SFT
- RT5651_I2S1_R_D_DIS
- RT5651_I2S1_R_D_EN
- RT5651_I2S1_R_D_MASK
- RT5651_I2S1_R_D_SFT
- RT5651_I2S1_SDP
- RT5651_I2S2_MS_SP_50
- RT5651_I2S2_MS_SP_64
- RT5651_I2S2_MS_SP_MASK
- RT5651_I2S2_MS_SP_SEL
- RT5651_I2S2_PD_MASK
- RT5651_I2S2_PD_SFT
- RT5651_I2S2_RATE_MASK
- RT5651_I2S2_RATE_SFT
- RT5651_I2S2_R_D_DIS
- RT5651_I2S2_R_D_EN
- RT5651_I2S2_R_D_MASK
- RT5651_I2S2_R_D_SFT
- RT5651_I2S2_SDP
- RT5651_I2S2_SEL_GPIO
- RT5651_I2S2_SEL_I2S
- RT5651_I2S2_SEL_MASK
- RT5651_I2S2_SEL_SFT
- RT5651_I2S_BCLK_MS2_32
- RT5651_I2S_BCLK_MS2_64
- RT5651_I2S_BCLK_MS2_MASK
- RT5651_I2S_BCLK_MS2_SFT
- RT5651_I2S_BP_INV
- RT5651_I2S_BP_MASK
- RT5651_I2S_BP_NOR
- RT5651_I2S_BP_SFT
- RT5651_I2S_DF_I2S
- RT5651_I2S_DF_LEFT
- RT5651_I2S_DF_MASK
- RT5651_I2S_DF_PCM_A
- RT5651_I2S_DF_PCM_B
- RT5651_I2S_DF_SFT
- RT5651_I2S_DL_16
- RT5651_I2S_DL_20
- RT5651_I2S_DL_24
- RT5651_I2S_DL_8
- RT5651_I2S_DL_MASK
- RT5651_I2S_DL_SFT
- RT5651_I2S_I_CP_A_LAW
- RT5651_I2S_I_CP_MASK
- RT5651_I2S_I_CP_OFF
- RT5651_I2S_I_CP_SFT
- RT5651_I2S_I_CP_U_LAW
- RT5651_I2S_MS_M
- RT5651_I2S_MS_MASK
- RT5651_I2S_MS_S
- RT5651_I2S_MS_SFT
- RT5651_I2S_O_CP_A_LAW
- RT5651_I2S_O_CP_MASK
- RT5651_I2S_O_CP_OFF
- RT5651_I2S_O_CP_SFT
- RT5651_I2S_O_CP_U_LAW
- RT5651_I2S_PD1_1
- RT5651_I2S_PD1_12
- RT5651_I2S_PD1_16
- RT5651_I2S_PD1_2
- RT5651_I2S_PD1_3
- RT5651_I2S_PD1_4
- RT5651_I2S_PD1_6
- RT5651_I2S_PD1_8
- RT5651_I2S_PD1_MASK
- RT5651_I2S_PD1_SFT
- RT5651_I2S_PD2_1
- RT5651_I2S_PD2_12
- RT5651_I2S_PD2_16
- RT5651_I2S_PD2_2
- RT5651_I2S_PD2_3
- RT5651_I2S_PD2_4
- RT5651_I2S_PD2_6
- RT5651_I2S_PD2_8
- RT5651_I2S_PD2_MASK
- RT5651_I2S_PD2_SFT
- RT5651_IB_HP_125IL
- RT5651_IB_HP_1IL
- RT5651_IB_HP_25IL
- RT5651_IB_HP_5IL
- RT5651_IB_HP_MASK
- RT5651_IB_HP_SFT
- RT5651_IF1_ADC1
- RT5651_IF1_ADC2
- RT5651_IF1_DAC_L2
- RT5651_IF1_DAC_R2
- RT5651_IF2_ADC_L_SEL_MASK
- RT5651_IF2_ADC_L_SEL_PASS
- RT5651_IF2_ADC_L_SEL_SFT
- RT5651_IF2_ADC_L_SEL_TXDP
- RT5651_IF2_ADC_R_SEL_MASK
- RT5651_IF2_ADC_R_SEL_PASS
- RT5651_IF2_ADC_R_SEL_SFT
- RT5651_IF2_ADC_R_SEL_TXDP
- RT5651_IF2_ADC_SEL_L2R
- RT5651_IF2_ADC_SEL_MASK
- RT5651_IF2_ADC_SEL_NOR
- RT5651_IF2_ADC_SEL_R2L
- RT5651_IF2_ADC_SEL_SFT
- RT5651_IF2_ADC_SEL_SWAP
- RT5651_IF2_ADC_SRC_MASK
- RT5651_IF2_ADC_SRC_SFT
- RT5651_IF2_DAC_L2
- RT5651_IF2_DAC_R2
- RT5651_IF2_DAC_SEL_L2R
- RT5651_IF2_DAC_SEL_MASK
- RT5651_IF2_DAC_SEL_NOR
- RT5651_IF2_DAC_SEL_R2L
- RT5651_IF2_DAC_SEL_SFT
- RT5651_IF2_DAC_SEL_SWAP
- RT5651_IN1_IN2
- RT5651_IN3
- RT5651_INL1_INR1_VOL
- RT5651_INL2_INR2_VOL
- RT5651_INL_SEL_IN4P
- RT5651_INL_SEL_MASK
- RT5651_INL_SEL_MONOP
- RT5651_INL_SEL_SFT
- RT5651_INL_VOL_MASK
- RT5651_INL_VOL_SFT
- RT5651_INR_SEL_IN4N
- RT5651_INR_SEL_MASK
- RT5651_INR_SEL_MONON
- RT5651_INR_SEL_SFT
- RT5651_INR_VOL_MASK
- RT5651_INR_VOL_SFT
- RT5651_INT_IRQ_ST
- RT5651_IN_DF1
- RT5651_IN_DF2
- RT5651_IN_SFT1
- RT5651_IN_SFT2
- RT5651_IRQ_CTRL1
- RT5651_IRQ_CTRL2
- RT5651_IRQ_JD_BP
- RT5651_IRQ_JD_MASK
- RT5651_IRQ_JD_NOR
- RT5651_IRQ_JD_SFT
- RT5651_IRQ_MB1_OC_BP
- RT5651_IRQ_MB1_OC_MASK
- RT5651_IRQ_MB1_OC_NOR
- RT5651_IRQ_MB1_OC_SFT
- RT5651_JD1_1
- RT5651_JD1_1_EN_STKY
- RT5651_JD1_1_EN_STKY_SFT
- RT5651_JD1_1_INV
- RT5651_JD1_1_INV_SFT
- RT5651_JD1_1_IRQ_EN
- RT5651_JD1_1_IRQ_EN_SFT
- RT5651_JD1_2
- RT5651_JD1_2_EN_STKY
- RT5651_JD1_2_EN_STKY_SFT
- RT5651_JD1_2_INV
- RT5651_JD1_2_INV_SFT
- RT5651_JD1_2_IRQ_EN
- RT5651_JD1_2_IRQ_EN_SFT
- RT5651_JD2
- RT5651_JD2_CMP_MASK
- RT5651_JD2_CMP_SFT
- RT5651_JD2_EN_STKY
- RT5651_JD2_EN_STKY_SFT
- RT5651_JD2_INV
- RT5651_JD2_INV_SFT
- RT5651_JD2_IRQ_EN
- RT5651_JD2_IRQ_EN_SFT
- RT5651_JD3_CMP_MASK
- RT5651_JD3_CMP_SFT
- RT5651_JD3_EN_STKY
- RT5651_JD3_EN_STKY_SFT
- RT5651_JD3_INV
- RT5651_JD3_INV_SFT
- RT5651_JD3_IRQ_EN
- RT5651_JD3_IRQ_EN_SFT
- RT5651_JD_CTRL1
- RT5651_JD_CTRL2
- RT5651_JD_DIS
- RT5651_JD_GPIO1
- RT5651_JD_GPIO2
- RT5651_JD_GPIO3
- RT5651_JD_GPIO4
- RT5651_JD_GPIO5
- RT5651_JD_GPIO6
- RT5651_JD_HP_DIS
- RT5651_JD_HP_EN
- RT5651_JD_HP_MASK
- RT5651_JD_HP_SFT
- RT5651_JD_HP_TRG_HI
- RT5651_JD_HP_TRG_LO
- RT5651_JD_HP_TRG_MASK
- RT5651_JD_HP_TRG_SFT
- RT5651_JD_LO_DIS
- RT5651_JD_LO_EN
- RT5651_JD_LO_MASK
- RT5651_JD_LO_SFT
- RT5651_JD_LO_TRG_HI
- RT5651_JD_LO_TRG_LO
- RT5651_JD_LO_TRG_MASK
- RT5651_JD_LO_TRG_SFT
- RT5651_JD_MASK
- RT5651_JD_MODE_SEL_M0
- RT5651_JD_MODE_SEL_M1
- RT5651_JD_MODE_SEL_M2
- RT5651_JD_MODE_SEL_MASK
- RT5651_JD_MODE_SEL_SFT
- RT5651_JD_M_CMP
- RT5651_JD_M_CMP_SFT
- RT5651_JD_M_MODE_SEL_M0
- RT5651_JD_M_MODE_SEL_M1
- RT5651_JD_M_MODE_SEL_M2
- RT5651_JD_M_MODE_SEL_MASK
- RT5651_JD_M_MODE_SEL_SFT
- RT5651_JD_M_PD
- RT5651_JD_M_PD_SFT
- RT5651_JD_M_PU
- RT5651_JD_M_PU_SFT
- RT5651_JD_NULL
- RT5651_JD_PD
- RT5651_JD_PD_SFT
- RT5651_JD_PU
- RT5651_JD_PU_SFT
- RT5651_JD_P_INV
- RT5651_JD_P_MASK
- RT5651_JD_P_NOR
- RT5651_JD_P_SFT
- RT5651_JD_SFT
- RT5651_JD_SPL_DIS
- RT5651_JD_SPL_EN
- RT5651_JD_SPL_MASK
- RT5651_JD_SPL_SFT
- RT5651_JD_SPL_TRG_HI
- RT5651_JD_SPL_TRG_LO
- RT5651_JD_SPL_TRG_MASK
- RT5651_JD_SPL_TRG_SFT
- RT5651_JD_SPR_DIS
- RT5651_JD_SPR_EN
- RT5651_JD_SPR_MASK
- RT5651_JD_SPR_SFT
- RT5651_JD_SPR_TRG_HI
- RT5651_JD_SPR_TRG_LO
- RT5651_JD_SPR_TRG_MASK
- RT5651_JD_SPR_TRG_SFT
- RT5651_JD_STKY_DIS
- RT5651_JD_STKY_EN
- RT5651_JD_STKY_MASK
- RT5651_JD_STKY_SFT
- RT5651_JD_TRG_SEL_GPIO
- RT5651_JD_TRG_SEL_JD1_1
- RT5651_JD_TRG_SEL_JD1_2
- RT5651_JD_TRG_SEL_JD2
- RT5651_JD_TRG_SEL_JD3
- RT5651_JD_TRG_SEL_MASK
- RT5651_JD_TRG_SEL_SFT
- RT5651_LOUT_CTRL1
- RT5651_LOUT_CTRL2
- RT5651_LOUT_MIXER
- RT5651_L_MUTE
- RT5651_L_MUTE_SFT
- RT5651_L_VOL_MASK
- RT5651_L_VOL_SFT
- RT5651_MAMP_INT_REG2
- RT5651_MB1_OC_CLR
- RT5651_MB1_OC_CLR_SFT
- RT5651_MB1_OC_P_INV
- RT5651_MB1_OC_P_MASK
- RT5651_MB1_OC_P_NOR
- RT5651_MB1_OC_P_SFT
- RT5651_MB1_OC_STKY_DIS
- RT5651_MB1_OC_STKY_EN
- RT5651_MB1_OC_STKY_MASK
- RT5651_MB1_OC_STKY_SFT
- RT5651_MB2_OC_P_MASK
- RT5651_MIC1_BS_75AV
- RT5651_MIC1_BS_9AV
- RT5651_MIC1_BS_MASK
- RT5651_MIC1_BS_SFT
- RT5651_MIC1_CLK_DIS
- RT5651_MIC1_CLK_EN
- RT5651_MIC1_CLK_MASK
- RT5651_MIC1_CLK_SFT
- RT5651_MIC1_OVCD_DIS
- RT5651_MIC1_OVCD_EN
- RT5651_MIC1_OVCD_MASK
- RT5651_MIC1_OVCD_SFT
- RT5651_MIC1_OVTH_1500UA
- RT5651_MIC1_OVTH_2000UA
- RT5651_MIC1_OVTH_600UA
- RT5651_MIC1_OVTH_MASK
- RT5651_MIC1_OVTH_SFT
- RT5651_MICBIAS
- RT5651_MIC_OVCD_SF_0P5
- RT5651_MIC_OVCD_SF_0P75
- RT5651_MIC_OVCD_SF_1P0
- RT5651_MIC_OVCD_SF_1P5
- RT5651_MIC_OVCD_SF_MASK
- RT5651_MIC_OVCD_SF_SFT
- RT5651_MONO_ADC_L_VOL_MASK
- RT5651_MONO_ADC_L_VOL_SFT
- RT5651_MONO_ADC_R_VOL_MASK
- RT5651_MONO_ADC_R_VOL_SFT
- RT5651_MP3_HLP_DIS
- RT5651_MP3_HLP_EN
- RT5651_MP3_HLP_MASK
- RT5651_MP3_HLP_SFT
- RT5651_MP3_PLUS1
- RT5651_MP3_PLUS2
- RT5651_MP3_WT_1_2
- RT5651_MP3_WT_1_4
- RT5651_MP3_WT_MASK
- RT5651_MP3_WT_SFT
- RT5651_MRES_15MO
- RT5651_MRES_25MO
- RT5651_MRES_35MO
- RT5651_MRES_45MO
- RT5651_MRES_MASK
- RT5651_MRES_SFT
- RT5651_MT_DIS
- RT5651_MT_EN
- RT5651_MT_MASK
- RT5651_MT_SFT
- RT5651_M_3D_D2H_MASK
- RT5651_M_3D_D2H_SFT
- RT5651_M_3D_D2R_MASK
- RT5651_M_3D_D2R_SFT
- RT5651_M_3D_HRTF_MASK
- RT5651_M_3D_HRTF_SFT
- RT5651_M_3D_REVB_MASK
- RT5651_M_3D_REVB_SFT
- RT5651_M_ADCMIX_L
- RT5651_M_ADCMIX_L_SFT
- RT5651_M_ADCMIX_R
- RT5651_M_ADCMIX_R_SFT
- RT5651_M_BB_HPF_L_MASK
- RT5651_M_BB_HPF_L_SFT
- RT5651_M_BB_HPF_R_MASK
- RT5651_M_BB_HPF_R_SFT
- RT5651_M_BB_L_MASK
- RT5651_M_BB_L_SFT
- RT5651_M_BB_R_MASK
- RT5651_M_BB_R_SFT
- RT5651_M_BST1_MM
- RT5651_M_BST1_MM_SFT
- RT5651_M_BST1_OM_L
- RT5651_M_BST1_OM_L_SFT
- RT5651_M_BST1_OM_R
- RT5651_M_BST1_OM_R_SFT
- RT5651_M_BST1_RM_L
- RT5651_M_BST1_RM_L_SFT
- RT5651_M_BST1_RM_R
- RT5651_M_BST1_RM_R_SFT
- RT5651_M_BST1_SPM_L
- RT5651_M_BST1_SPM_L_SFT
- RT5651_M_BST1_SPM_R
- RT5651_M_BST1_SPM_R_SFT
- RT5651_M_BST2_OM_L
- RT5651_M_BST2_OM_L_SFT
- RT5651_M_BST2_OM_R
- RT5651_M_BST2_OM_R_SFT
- RT5651_M_BST2_RM_L
- RT5651_M_BST2_RM_L_SFT
- RT5651_M_BST2_RM_R
- RT5651_M_BST2_RM_R_SFT
- RT5651_M_BST3_RM_L
- RT5651_M_BST3_RM_L_SFT
- RT5651_M_BST3_RM_R
- RT5651_M_BST3_RM_R_SFT
- RT5651_M_DAC1_HM
- RT5651_M_DAC1_HM_SFT
- RT5651_M_DAC_L1_LM
- RT5651_M_DAC_L1_LM_SFT
- RT5651_M_DAC_L1_MIXL
- RT5651_M_DAC_L1_MIXL_SFT
- RT5651_M_DAC_L1_MIXR
- RT5651_M_DAC_L1_MIXR_SFT
- RT5651_M_DAC_L1_OM_L
- RT5651_M_DAC_L1_OM_L_SFT
- RT5651_M_DAC_L1_SM_L
- RT5651_M_DAC_L1_SM_L_SFT
- RT5651_M_DAC_L1_SPM_L
- RT5651_M_DAC_L1_SPM_L_SFT
- RT5651_M_DAC_L2_DAC_L
- RT5651_M_DAC_L2_DAC_L_SFT
- RT5651_M_DAC_L2_MIXL
- RT5651_M_DAC_L2_MIXL_SFT
- RT5651_M_DAC_L2_MM
- RT5651_M_DAC_L2_MM_SFT
- RT5651_M_DAC_L2_SM_L
- RT5651_M_DAC_L2_SM_L_SFT
- RT5651_M_DAC_L2_VOL
- RT5651_M_DAC_L2_VOL_SFT
- RT5651_M_DAC_R1_LM
- RT5651_M_DAC_R1_LM_SFT
- RT5651_M_DAC_R1_MIXL
- RT5651_M_DAC_R1_MIXL_SFT
- RT5651_M_DAC_R1_MIXR
- RT5651_M_DAC_R1_MIXR_SFT
- RT5651_M_DAC_R1_OM_R
- RT5651_M_DAC_R1_OM_R_SFT
- RT5651_M_DAC_R1_SM_R
- RT5651_M_DAC_R1_SM_R_SFT
- RT5651_M_DAC_R1_SPM_L
- RT5651_M_DAC_R1_SPM_L_SFT
- RT5651_M_DAC_R1_SPM_R
- RT5651_M_DAC_R1_SPM_R_SFT
- RT5651_M_DAC_R2_DAC_R
- RT5651_M_DAC_R2_DAC_R_SFT
- RT5651_M_DAC_R2_MIXR
- RT5651_M_DAC_R2_MIXR_SFT
- RT5651_M_DAC_R2_MM
- RT5651_M_DAC_R2_MM_SFT
- RT5651_M_DAC_R2_SM_R
- RT5651_M_DAC_R2_SM_R_SFT
- RT5651_M_DAC_R2_VOL
- RT5651_M_DAC_R2_VOL_SFT
- RT5651_M_HPVOL_HM
- RT5651_M_HPVOL_HM_SFT
- RT5651_M_IF1_DAC_L
- RT5651_M_IF1_DAC_L_SFT
- RT5651_M_IF1_DAC_R
- RT5651_M_IF1_DAC_R_SFT
- RT5651_M_IN1_L_OM_L
- RT5651_M_IN1_L_OM_L_SFT
- RT5651_M_IN1_L_RM_L
- RT5651_M_IN1_L_RM_L_SFT
- RT5651_M_IN1_R_OM_R
- RT5651_M_IN1_R_OM_R_SFT
- RT5651_M_IN1_R_RM_R
- RT5651_M_IN1_R_RM_R_SFT
- RT5651_M_IN2_L_OM_L
- RT5651_M_IN2_L_OM_L_SFT
- RT5651_M_IN2_L_RM_L
- RT5651_M_IN2_L_RM_L_SFT
- RT5651_M_IN2_R_OM_R
- RT5651_M_IN2_R_OM_R_SFT
- RT5651_M_IN2_R_RM_R
- RT5651_M_IN2_R_RM_R_SFT
- RT5651_M_IN_L_SM_L
- RT5651_M_IN_L_SM_L_SFT
- RT5651_M_IN_R_SM_R
- RT5651_M_IN_R_SM_R_SFT
- RT5651_M_MONO_ADC_L
- RT5651_M_MONO_ADC_L_SFT
- RT5651_M_MONO_ADC_R
- RT5651_M_MONO_ADC_R_SFT
- RT5651_M_MP3_DIS
- RT5651_M_MP3_EN
- RT5651_M_MP3_L_MASK
- RT5651_M_MP3_L_SFT
- RT5651_M_MP3_MASK
- RT5651_M_MP3_ORG_L_MASK
- RT5651_M_MP3_ORG_L_SFT
- RT5651_M_MP3_ORG_R_MASK
- RT5651_M_MP3_ORG_R_SFT
- RT5651_M_MP3_R_MASK
- RT5651_M_MP3_R_SFT
- RT5651_M_MP3_SFT
- RT5651_M_OM_L_RM_L
- RT5651_M_OM_L_RM_L_SFT
- RT5651_M_OM_L_SM_L
- RT5651_M_OM_L_SM_L_SFT
- RT5651_M_OM_R_RM_R
- RT5651_M_OM_R_RM_R_SFT
- RT5651_M_OM_R_SM_R
- RT5651_M_OM_R_SM_R_SFT
- RT5651_M_OV_L_LM
- RT5651_M_OV_L_LM_SFT
- RT5651_M_OV_L_MM
- RT5651_M_OV_L_MM_SFT
- RT5651_M_OV_R_LM
- RT5651_M_OV_R_LM_SFT
- RT5651_M_OV_R_MM
- RT5651_M_OV_R_MM_SFT
- RT5651_M_PDM_L
- RT5651_M_PDM_L_SFT
- RT5651_M_PDM_R
- RT5651_M_PDM_R_SFT
- RT5651_M_RM_L_OM_L
- RT5651_M_RM_L_OM_L_SFT
- RT5651_M_RM_L_SM_L
- RT5651_M_RM_L_SM_L_SFT
- RT5651_M_RM_R_OM_R
- RT5651_M_RM_R_OM_R_SFT
- RT5651_M_RM_R_SM_R
- RT5651_M_RM_R_SM_R_SFT
- RT5651_M_STO1_ADC_L1
- RT5651_M_STO1_ADC_L1_SFT
- RT5651_M_STO1_ADC_L2
- RT5651_M_STO1_ADC_L2_SFT
- RT5651_M_STO1_ADC_R1
- RT5651_M_STO1_ADC_R1_SFT
- RT5651_M_STO1_ADC_R2
- RT5651_M_STO1_ADC_R2_SFT
- RT5651_M_STO2_ADC_L1
- RT5651_M_STO2_ADC_L1_SFT
- RT5651_M_STO2_ADC_L2
- RT5651_M_STO2_ADC_L2_SFT
- RT5651_M_STO2_ADC_R1
- RT5651_M_STO2_ADC_R1_SFT
- RT5651_M_STO2_ADC_R2
- RT5651_M_STO2_ADC_R2_SFT
- RT5651_M_STO_DD_L1
- RT5651_M_STO_DD_L1_SFT
- RT5651_M_STO_DD_L2
- RT5651_M_STO_DD_L2_R
- RT5651_M_STO_DD_L2_R_SFT
- RT5651_M_STO_DD_L2_SFT
- RT5651_M_STO_DD_R1
- RT5651_M_STO_DD_R1_SFT
- RT5651_M_STO_DD_R2
- RT5651_M_STO_DD_R2_L
- RT5651_M_STO_DD_R2_L_SFT
- RT5651_M_STO_DD_R2_SFT
- RT5651_M_STO_L_DAC_L
- RT5651_M_STO_L_DAC_L_SFT
- RT5651_M_STO_R_DAC_R
- RT5651_M_STO_R_DAC_R_SFT
- RT5651_M_SV_L_SPM_L
- RT5651_M_SV_L_SPM_L_SFT
- RT5651_M_SV_R_SPM_L
- RT5651_M_SV_R_SPM_L_SFT
- RT5651_M_SV_R_SPM_R
- RT5651_M_SV_R_SPM_R_SFT
- RT5651_M_TDM2_L
- RT5651_M_TDM2_L_SFT
- RT5651_M_TDM2_R
- RT5651_M_TDM2_R_SFT
- RT5651_M_TDM4_L
- RT5651_M_TDM4_L_SFT
- RT5651_M_TDM4_R
- RT5651_M_TDM4_R_SFT
- RT5651_M_ZCD_MASK
- RT5651_M_ZCD_OM_L
- RT5651_M_ZCD_OM_R
- RT5651_M_ZCD_RM_L
- RT5651_M_ZCD_RM_R
- RT5651_M_ZCD_SFT
- RT5651_NO_WIND
- RT5651_OG_MP3_MASK
- RT5651_OG_MP3_SFT
- RT5651_OSW_L_DIS
- RT5651_OSW_L_EN
- RT5651_OSW_L_MASK
- RT5651_OSW_L_SFT
- RT5651_OSW_R_DIS
- RT5651_OSW_R_EN
- RT5651_OSW_R_MASK
- RT5651_OSW_R_SFT
- RT5651_OUT_L1_MIXER
- RT5651_OUT_L2_MIXER
- RT5651_OUT_L3_MIXER
- RT5651_OUT_R1_MIXER
- RT5651_OUT_R2_MIXER
- RT5651_OUT_R3_MIXER
- RT5651_OUT_SV_DIS
- RT5651_OUT_SV_EN
- RT5651_OUT_SV_MASK
- RT5651_OUT_SV_SFT
- RT5651_OVCD_SF_0P5
- RT5651_OVCD_SF_0P75
- RT5651_OVCD_SF_1P0
- RT5651_OVCD_SF_1P5
- RT5651_PDM_BUSY
- RT5651_PDM_BUSY_SFT
- RT5651_PDM_CTL
- RT5651_PDM_DIV_1
- RT5651_PDM_DIV_2
- RT5651_PDM_DIV_3
- RT5651_PDM_DIV_4
- RT5651_PDM_DIV_MASK
- RT5651_PDM_DIV_SFT
- RT5651_PDM_I2C_ADDR
- RT5651_PDM_I2C_BUSY
- RT5651_PDM_I2C_CMD_EXE
- RT5651_PDM_I2C_CMD_MASK
- RT5651_PDM_I2C_CMD_PATTERN
- RT5651_PDM_I2C_CMD_R
- RT5651_PDM_I2C_CMD_W
- RT5651_PDM_I2C_CTL1
- RT5651_PDM_I2C_CTL2
- RT5651_PDM_I2C_DATA_R
- RT5651_PDM_I2C_DATA_W
- RT5651_PDM_I2C_ID_MASK
- RT5651_PDM_I2C_NORMAL
- RT5651_PDM_L_SEL_DD_L
- RT5651_PDM_L_SEL_MASK
- RT5651_PDM_L_SEL_SFT
- RT5651_PDM_L_SEL_STO_L
- RT5651_PDM_PATTERN_SEL_128
- RT5651_PDM_PATTERN_SEL_64
- RT5651_PDM_PATTERN_SEL_MASK
- RT5651_PDM_R_SEL_DD_L
- RT5651_PDM_R_SEL_MASK
- RT5651_PDM_R_SEL_SFT
- RT5651_PDM_R_SEL_STO_L
- RT5651_PDM_VOL_MASK
- RT5651_PDM_VOL_SFT
- RT5651_PGM_REG_ARR1
- RT5651_PGM_REG_ARR2
- RT5651_PGM_REG_ARR3
- RT5651_PGM_REG_ARR4
- RT5651_PGM_REG_ARR5
- RT5651_PLL1_PD_1
- RT5651_PLL1_PD_2
- RT5651_PLL1_PD_MASK
- RT5651_PLL1_PD_SFT
- RT5651_PLL1_SRC_BCLK1
- RT5651_PLL1_SRC_BCLK2
- RT5651_PLL1_SRC_MASK
- RT5651_PLL1_SRC_MCLK
- RT5651_PLL1_SRC_SFT
- RT5651_PLL1_S_BCLK1
- RT5651_PLL1_S_BCLK2
- RT5651_PLL1_S_MCLK
- RT5651_PLL_CTRL1
- RT5651_PLL_CTRL2
- RT5651_PLL_INP_MAX
- RT5651_PLL_INP_MIN
- RT5651_PLL_K_MASK
- RT5651_PLL_K_MAX
- RT5651_PLL_K_SFT
- RT5651_PLL_MODE_1
- RT5651_PLL_MODE_2
- RT5651_PLL_MODE_3
- RT5651_PLL_MODE_4
- RT5651_PLL_MODE_5
- RT5651_PLL_MODE_6
- RT5651_PLL_MODE_7
- RT5651_PLL_M_BP
- RT5651_PLL_M_BP_SFT
- RT5651_PLL_M_MASK
- RT5651_PLL_M_MAX
- RT5651_PLL_M_SFT
- RT5651_PLL_N_MASK
- RT5651_PLL_N_MAX
- RT5651_PLL_N_SFT
- RT5651_PM_HP_HV
- RT5651_PM_HP_LV
- RT5651_PM_HP_MASK
- RT5651_PM_HP_MV
- RT5651_PM_HP_SFT
- RT5651_PRE_SCLK_1024
- RT5651_PRE_SCLK_2048
- RT5651_PRE_SCLK_512
- RT5651_PRE_SCLK_MASK
- RT5651_PRE_SCLK_SFT
- RT5651_PRIV_DATA
- RT5651_PRIV_INDEX
- RT5651_PR_BASE
- RT5651_PR_RANGE_BASE
- RT5651_PR_SPACING
- RT5651_PWM_JD2_BIT
- RT5651_PWM_JD3_BIT
- RT5651_PWM_JD_M_BIT
- RT5651_PWR_ADC_L
- RT5651_PWR_ADC_L_BIT
- RT5651_PWR_ADC_R
- RT5651_PWR_ADC_R_BIT
- RT5651_PWR_ADC_STO1_F
- RT5651_PWR_ADC_STO1_F_BIT
- RT5651_PWR_ADC_STO2_F
- RT5651_PWR_ADC_STO2_F_BIT
- RT5651_PWR_ANLG1
- RT5651_PWR_ANLG2
- RT5651_PWR_BG
- RT5651_PWR_BG_BIT
- RT5651_PWR_BST1
- RT5651_PWR_BST1_BIT
- RT5651_PWR_BST1_OP2
- RT5651_PWR_BST1_OP2_BIT
- RT5651_PWR_BST2
- RT5651_PWR_BST2_BIT
- RT5651_PWR_BST2_OP2
- RT5651_PWR_BST2_OP2_BIT
- RT5651_PWR_BST3
- RT5651_PWR_BST3_BIT
- RT5651_PWR_BST3_OP2
- RT5651_PWR_BST3_OP2_BIT
- RT5651_PWR_CLK12M_MASK
- RT5651_PWR_CLK12M_PD
- RT5651_PWR_CLK12M_PU
- RT5651_PWR_CLK12M_SFT
- RT5651_PWR_DAC_L1
- RT5651_PWR_DAC_L1_BIT
- RT5651_PWR_DAC_R1
- RT5651_PWR_DAC_R1_BIT
- RT5651_PWR_DAC_STO1_F
- RT5651_PWR_DAC_STO1_F_BIT
- RT5651_PWR_DAC_STO2_F
- RT5651_PWR_DAC_STO2_F_BIT
- RT5651_PWR_DIG1
- RT5651_PWR_DIG2
- RT5651_PWR_FV1
- RT5651_PWR_FV1_BIT
- RT5651_PWR_FV2
- RT5651_PWR_FV2_BIT
- RT5651_PWR_HA
- RT5651_PWR_HA_BIT
- RT5651_PWR_HP_L
- RT5651_PWR_HP_L_BIT
- RT5651_PWR_HP_R
- RT5651_PWR_HP_R_BIT
- RT5651_PWR_HV_L
- RT5651_PWR_HV_L_BIT
- RT5651_PWR_HV_R
- RT5651_PWR_HV_R_BIT
- RT5651_PWR_I2S1
- RT5651_PWR_I2S1_BIT
- RT5651_PWR_I2S2
- RT5651_PWR_I2S2_BIT
- RT5651_PWR_IN1_L
- RT5651_PWR_IN1_L_BIT
- RT5651_PWR_IN1_R
- RT5651_PWR_IN1_R_BIT
- RT5651_PWR_IN2_L
- RT5651_PWR_IN2_L_BIT
- RT5651_PWR_IN2_R
- RT5651_PWR_IN2_R_BIT
- RT5651_PWR_JD2
- RT5651_PWR_JD3
- RT5651_PWR_JD_M
- RT5651_PWR_LDO
- RT5651_PWR_LDO_BIT
- RT5651_PWR_LDO_DVO_1_0V
- RT5651_PWR_LDO_DVO_1_1V
- RT5651_PWR_LDO_DVO_1_2V
- RT5651_PWR_LDO_DVO_1_3V
- RT5651_PWR_LDO_DVO_MASK
- RT5651_PWR_LM
- RT5651_PWR_LM_BIT
- RT5651_PWR_MB
- RT5651_PWR_MB1
- RT5651_PWR_MB1_BIT
- RT5651_PWR_MB_BIT
- RT5651_PWR_MB_MASK
- RT5651_PWR_MB_PD
- RT5651_PWR_MB_PU
- RT5651_PWR_MB_SFT
- RT5651_PWR_MIXER
- RT5651_PWR_OM_L
- RT5651_PWR_OM_L_BIT
- RT5651_PWR_OM_R
- RT5651_PWR_OM_R_BIT
- RT5651_PWR_OV_L
- RT5651_PWR_OV_L_BIT
- RT5651_PWR_OV_R
- RT5651_PWR_OV_R_BIT
- RT5651_PWR_PDM
- RT5651_PWR_PDM_BIT
- RT5651_PWR_PLL
- RT5651_PWR_PLL_BIT
- RT5651_PWR_RM_L
- RT5651_PWR_RM_L_BIT
- RT5651_PWR_RM_R
- RT5651_PWR_RM_R_BIT
- RT5651_PWR_VOL
- RT5651_PWR_VREF1
- RT5651_PWR_VREF1_BIT
- RT5651_PWR_VREF2
- RT5651_PWR_VREF2_BIT
- RT5651_RAMP_DIS
- RT5651_RAMP_EN
- RT5651_RAMP_MASK
- RT5651_RAMP_SFT
- RT5651_REC_L1_MIXER
- RT5651_REC_L2_MIXER
- RT5651_REC_R1_MIXER
- RT5651_REC_R2_MIXER
- RT5651_RESET
- RT5651_RSTN_DIS
- RT5651_RSTN_EN
- RT5651_RSTN_MASK
- RT5651_RSTN_SFT
- RT5651_RSTP_DIS
- RT5651_RSTP_EN
- RT5651_RSTP_MASK
- RT5651_RSTP_SFT
- RT5651_RXDC_SEL_L2R
- RT5651_RXDC_SEL_MASK
- RT5651_RXDC_SEL_NOR
- RT5651_RXDC_SEL_R2L
- RT5651_RXDC_SEL_SFT
- RT5651_RXDC_SEL_SWAP
- RT5651_RXDP_SEL_L2R
- RT5651_RXDP_SEL_MASK
- RT5651_RXDP_SEL_NOR
- RT5651_RXDP_SEL_R2L
- RT5651_RXDP_SEL_SFT
- RT5651_RXDP_SEL_SWAP
- RT5651_RXDP_SRC_DIV3
- RT5651_RXDP_SRC_MASK
- RT5651_RXDP_SRC_NOR
- RT5651_RXDP_SRC_SFT
- RT5651_R_MUTE
- RT5651_R_MUTE_SFT
- RT5651_R_VOL_MASK
- RT5651_R_VOL_SFT
- RT5651_SCB_CTRL
- RT5651_SCB_DIS
- RT5651_SCB_EN
- RT5651_SCB_FUNC
- RT5651_SCB_MASK
- RT5651_SCB_SFT
- RT5651_SCB_SWAP_DIS
- RT5651_SCB_SWAP_EN
- RT5651_SCB_SWAP_MASK
- RT5651_SCB_SWAP_SFT
- RT5651_SCLK_SRC_MASK
- RT5651_SCLK_SRC_MCLK
- RT5651_SCLK_SRC_PLL1
- RT5651_SCLK_SRC_RCCLK
- RT5651_SCLK_SRC_SFT
- RT5651_SCLK_S_MCLK
- RT5651_SCLK_S_PLL1
- RT5651_SCLK_S_RCCLK
- RT5651_SEL_DAC_L2
- RT5651_SEL_DAC_L2_SFT
- RT5651_SEL_DAC_R2
- RT5651_SEL_DAC_R2_SFT
- RT5651_SI_DAC_AUTO
- RT5651_SI_DAC_MASK
- RT5651_SI_DAC_SFT
- RT5651_SI_DAC_TEST
- RT5651_SMT_TRIG_DIS
- RT5651_SMT_TRIG_EN
- RT5651_SMT_TRIG_MASK
- RT5651_SMT_TRIG_SFT
- RT5651_SPO_CLSD_RATIO_MASK
- RT5651_SPO_CLSD_RATIO_SFT
- RT5651_STA_GP1
- RT5651_STA_GP1_BIT
- RT5651_STA_GP2
- RT5651_STA_GP2_BIT
- RT5651_STA_GP3
- RT5651_STA_GP3_BIT
- RT5651_STA_GP4
- RT5651_STA_GP4_BIT
- RT5651_STA_GP5
- RT5651_STA_GP5_BIT
- RT5651_STA_GP6
- RT5651_STA_GP6_BIT
- RT5651_STA_GP7
- RT5651_STA_GP7_BIT
- RT5651_STA_GPIO8
- RT5651_STA_GPIO8_BIT
- RT5651_STA_GP_JD
- RT5651_STA_GP_JD_BIT
- RT5651_STA_JD1_1
- RT5651_STA_JD1_1_BIT
- RT5651_STA_JD1_2
- RT5651_STA_JD1_2_BIT
- RT5651_STA_JD2
- RT5651_STA_JD2_BIT
- RT5651_STA_JD3
- RT5651_STA_JD3_BIT
- RT5651_STEREO_RATES
- RT5651_STO1_ADC_1_SRC_ADC
- RT5651_STO1_ADC_1_SRC_DACMIX
- RT5651_STO1_ADC_1_SRC_MASK
- RT5651_STO1_ADC_1_SRC_SFT
- RT5651_STO1_ADC_2_SRC_DACMIXR
- RT5651_STO1_ADC_2_SRC_DMIC
- RT5651_STO1_ADC_2_SRC_MASK
- RT5651_STO1_ADC_2_SRC_SFT
- RT5651_STO1_ADC_MIXER
- RT5651_STO1_ASRC_EN
- RT5651_STO1_ASRC_EN_SFT
- RT5651_STO1_DAC_M_ASRC
- RT5651_STO1_DAC_M_MASK
- RT5651_STO1_DAC_M_NOR
- RT5651_STO1_DAC_M_SFT
- RT5651_STO1_T_LRCK1
- RT5651_STO1_T_MASK
- RT5651_STO1_T_SCLK
- RT5651_STO1_T_SFT
- RT5651_STO2_ADC_L1_SRC_ADCL
- RT5651_STO2_ADC_L1_SRC_DACMIXL
- RT5651_STO2_ADC_L1_SRC_MASK
- RT5651_STO2_ADC_L1_SRC_SFT
- RT5651_STO2_ADC_L2_SRC_DACMIXR
- RT5651_STO2_ADC_L2_SRC_DMIC
- RT5651_STO2_ADC_L2_SRC_MASK
- RT5651_STO2_ADC_L2_SRC_SFT
- RT5651_STO2_ADC_MIXER
- RT5651_STO2_ADC_R1_SRC_ADCR
- RT5651_STO2_ADC_R1_SRC_DACMIXR
- RT5651_STO2_ADC_R1_SRC_MASK
- RT5651_STO2_ADC_R1_SRC_SFT
- RT5651_STO2_ADC_R2_SRC_DACMIXR
- RT5651_STO2_ADC_R2_SRC_DMIC
- RT5651_STO2_ADC_R2_SRC_MASK
- RT5651_STO2_ADC_R2_SRC_SFT
- RT5651_STO2_ASRC_EN
- RT5651_STO2_ASRC_EN_SFT
- RT5651_STO2_DAC_M_ASRC
- RT5651_STO2_DAC_M_MASK
- RT5651_STO2_DAC_M_NOR
- RT5651_STO2_DAC_M_SFT
- RT5651_STO2_T_I2S2
- RT5651_STO2_T_LRCK2
- RT5651_STO2_T_MASK
- RT5651_STO2_T_SFT
- RT5651_STORM
- RT5651_STO_DAC_MIXER
- RT5651_STO_DD_L1_VOL_MASK
- RT5651_STO_DD_L2_R_VOL_MASK
- RT5651_STO_DD_L2_R_VOL_SFT
- RT5651_STO_DD_L2_VOL_MASK
- RT5651_STO_DD_L2_VOL_SFT
- RT5651_STO_DD_R1_VOL_MASK
- RT5651_STO_DD_R1_VOL_SFT
- RT5651_STO_DD_R2_L_VOL_MASK
- RT5651_STO_DD_R2_L_VOL_SFT
- RT5651_STO_DD_R2_VOL_MASK
- RT5651_STO_DD_R2_VOL_SFT
- RT5651_STO_L_DAC_L_VOL_MASK
- RT5651_STO_L_DAC_L_VOL_SFT
- RT5651_STO_R_DAC_R_VOL_MASK
- RT5651_STO_R_DAC_R_VOL_SFT
- RT5651_SV_DIS
- RT5651_SV_DLY_MASK
- RT5651_SV_DLY_SFT
- RT5651_SV_EN
- RT5651_SV_MASK
- RT5651_SV_SFT
- RT5651_SV_ZCD1
- RT5651_SV_ZCD2
- RT5651_TDM_ADC_SEL_MASK
- RT5651_TDM_ADC_SEL_NOR
- RT5651_TDM_ADC_SEL_SFT
- RT5651_TDM_ADC_SEL_SWAP
- RT5651_TDM_ADC_START_SEL_MASK
- RT5651_TDM_ADC_START_SEL_SFT
- RT5651_TDM_ADC_START_SEL_SL0
- RT5651_TDM_ADC_START_SEL_SL4
- RT5651_TDM_CH_LEN_SEL_16
- RT5651_TDM_CH_LEN_SEL_20
- RT5651_TDM_CH_LEN_SEL_24
- RT5651_TDM_CH_LEN_SEL_32
- RT5651_TDM_CH_LEN_SEL_MASK
- RT5651_TDM_CH_LEN_SEL_SFT
- RT5651_TDM_CH_NUM_SEL_2
- RT5651_TDM_CH_NUM_SEL_4
- RT5651_TDM_CH_NUM_SEL_6
- RT5651_TDM_CH_NUM_SEL_8
- RT5651_TDM_CH_NUM_SEL_MASK
- RT5651_TDM_CH_NUM_SEL_SFT
- RT5651_TDM_CH_VAL_EN
- RT5651_TDM_CH_VAL_SEL_CH01
- RT5651_TDM_CH_VAL_SEL_CH0123
- RT5651_TDM_CH_VAL_SEL_MASK
- RT5651_TDM_CH_VAL_SEL_SFT
- RT5651_TDM_CH_VAL_SFT
- RT5651_TDM_CTL_1
- RT5651_TDM_CTL_2
- RT5651_TDM_CTL_3
- RT5651_TDM_END_EDGE_EN
- RT5651_TDM_END_EDGE_EN_SFT
- RT5651_TDM_END_EDGE_SEL_MASK
- RT5651_TDM_END_EDGE_SEL_NEG
- RT5651_TDM_END_EDGE_SEL_POS
- RT5651_TDM_END_EDGE_SEL_SFT
- RT5651_TDM_I2S_CH2_SEL_LL
- RT5651_TDM_I2S_CH2_SEL_LR
- RT5651_TDM_I2S_CH2_SEL_MASK
- RT5651_TDM_I2S_CH2_SEL_RL
- RT5651_TDM_I2S_CH2_SEL_RR
- RT5651_TDM_I2S_CH2_SEL_SFT
- RT5651_TDM_I2S_CH4_SEL_LL
- RT5651_TDM_I2S_CH4_SEL_LR
- RT5651_TDM_I2S_CH4_SEL_MASK
- RT5651_TDM_I2S_CH4_SEL_RL
- RT5651_TDM_I2S_CH4_SEL_RR
- RT5651_TDM_I2S_CH4_SEL_SFT
- RT5651_TDM_I2S_CH6_SEL_LL
- RT5651_TDM_I2S_CH6_SEL_LR
- RT5651_TDM_I2S_CH6_SEL_MASK
- RT5651_TDM_I2S_CH6_SEL_RL
- RT5651_TDM_I2S_CH6_SEL_RR
- RT5651_TDM_I2S_CH6_SEL_SFT
- RT5651_TDM_I2S_CH8_SEL_LL
- RT5651_TDM_I2S_CH8_SEL_LR
- RT5651_TDM_I2S_CH8_SEL_MASK
- RT5651_TDM_I2S_CH8_SEL_RL
- RT5651_TDM_I2S_CH8_SEL_RR
- RT5651_TDM_I2S_CH8_SEL_SFT
- RT5651_TDM_INTEL_SEL_50
- RT5651_TDM_INTEL_SEL_64
- RT5651_TDM_INTEL_SEL_MASK
- RT5651_TDM_INTEL_SEL_SFT
- RT5651_TDM_LPBK_EN
- RT5651_TDM_LPBK_SFT
- RT5651_TDM_LRCK_POL_SEL_INV
- RT5651_TDM_LRCK_POL_SEL_MASK
- RT5651_TDM_LRCK_POL_SEL_NOR
- RT5651_TDM_LRCK_POL_SEL_SFT
- RT5651_TDM_LRCK_PULSE_SEL_BCLK
- RT5651_TDM_LRCK_PULSE_SEL_CH
- RT5651_TDM_LRCK_PULSE_SEL_MASK
- RT5651_TDM_LRCK_PULSE_SEL_SFT
- RT5651_TDM_MODE_SEL_MASK
- RT5651_TDM_MODE_SEL_NOR
- RT5651_TDM_MODE_SEL_SFT
- RT5651_TDM_MODE_SEL_TDM
- RT5651_TDM_TRAN_EDGE_SEL_MASK
- RT5651_TDM_TRAN_EDGE_SEL_NEG
- RT5651_TDM_TRAN_EDGE_SEL_POS
- RT5651_TDM_TRAN_EDGE_SEL_SFT
- RT5651_TRXDP_SEL_SWAP
- RT5651_TXDC_SEL_L2R
- RT5651_TXDC_SEL_MASK
- RT5651_TXDC_SEL_NOR
- RT5651_TXDC_SEL_R2L
- RT5651_TXDC_SEL_SFT
- RT5651_TXDC_SEL_SWAP
- RT5651_TXDP_SEL_L2R
- RT5651_TXDP_SEL_MASK
- RT5651_TXDP_SEL_NOR
- RT5651_TXDP_SEL_R2L
- RT5651_TXDP_SEL_SFT
- RT5651_TXDP_SRC_DIV3
- RT5651_TXDP_SRC_MASK
- RT5651_TXDP_SRC_NOR
- RT5651_TXDP_SRC_SFT
- RT5651_VENDOR_ID
- RT5651_VERSION_ID
- RT5651_VLO_32V
- RT5651_VLO_3V
- RT5651_VLO_MASK
- RT5651_VLO_SFT
- RT5651_VOL_L_MUTE
- RT5651_VOL_L_SFT
- RT5651_VOL_R_MUTE
- RT5651_VOL_R_SFT
- RT5651_WND_1
- RT5651_WND_2
- RT5651_WND_3
- RT5651_WND_4
- RT5651_WND_5
- RT5651_WND_8
- RT5651_WND_DIS
- RT5651_WND_EN
- RT5651_WND_FC_NW_MASK
- RT5651_WND_FC_NW_SFT
- RT5651_WND_FC_ST_MASK
- RT5651_WND_FC_ST_SFT
- RT5651_WND_FC_WK_MASK
- RT5651_WND_FC_WK_SFT
- RT5651_WND_MASK
- RT5651_WND_SFT
- RT5651_WND_STRONG_MASK
- RT5651_WND_STRONG_SFT
- RT5651_WND_TH_HI_MASK
- RT5651_WND_TH_HI_SFT
- RT5651_WND_TH_LO_MASK
- RT5651_WND_TH_LO_SFT
- RT5651_WND_WIND_MASK
- RT5651_WND_WIND_SFT
- RT5651_ZCD_DIG_DIS
- RT5651_ZCD_DIG_EN
- RT5651_ZCD_DIG_MASK
- RT5651_ZCD_DIG_SFT
- RT5651_ZCD_HP_DIS
- RT5651_ZCD_HP_EN
- RT5651_ZCD_HP_MASK
- RT5651_ZCD_HP_SFT
- RT5651_ZCD_MASK
- RT5651_ZCD_PD
- RT5651_ZCD_PU
- RT5651_ZCD_SFT
- RT5651_ZD_F_IM
- RT5651_ZD_F_MASK
- RT5651_ZD_F_SFT
- RT5651_ZD_F_UN
- RT5651_ZD_F_ZC_IM
- RT5651_ZD_F_ZC_IOD
- RT5651_ZD_T_MASK
- RT5651_ZD_T_SFT
- RT5659_3D_SPK_COEF_1
- RT5659_3D_SPK_COEF_2
- RT5659_3D_SPK_COEF_3
- RT5659_3D_SPK_COEF_4
- RT5659_3D_SPK_COEF_5
- RT5659_3D_SPK_COEF_6
- RT5659_3D_SPK_COEF_7
- RT5659_3D_SPK_CTRL
- RT5659_4BTN_IL_CMD_1
- RT5659_4BTN_IL_CMD_2
- RT5659_4BTN_IL_CMD_3
- RT5659_4BTN_IL_DIS
- RT5659_4BTN_IL_EN
- RT5659_4BTN_IL_MASK
- RT5659_AD2DA_LB_MASK
- RT5659_AD2DA_LB_SFT
- RT5659_ADCDAT_SRC_MASK
- RT5659_ADCDAT_SRC_SFT
- RT5659_ADC_EQ_CTRL_1
- RT5659_ADC_EQ_CTRL_2
- RT5659_ADC_L_EQ_BPF1_A1
- RT5659_ADC_L_EQ_BPF1_A2
- RT5659_ADC_L_EQ_BPF1_H0
- RT5659_ADC_L_EQ_BPF2_A1
- RT5659_ADC_L_EQ_BPF2_A2
- RT5659_ADC_L_EQ_BPF2_H0
- RT5659_ADC_L_EQ_BPF3_A1
- RT5659_ADC_L_EQ_BPF3_A2
- RT5659_ADC_L_EQ_BPF3_H0
- RT5659_ADC_L_EQ_BPF4_A1
- RT5659_ADC_L_EQ_BPF4_A2
- RT5659_ADC_L_EQ_BPF4_H0
- RT5659_ADC_L_EQ_HPF1_A1
- RT5659_ADC_L_EQ_HPF1_H0
- RT5659_ADC_L_EQ_LPF1_A1
- RT5659_ADC_L_EQ_LPF1_H0
- RT5659_ADC_L_EQ_POST_VOL
- RT5659_ADC_L_EQ_PRE_VOL
- RT5659_ADC_L_VOL_MASK
- RT5659_ADC_L_VOL_SFT
- RT5659_ADC_MONO_HP_CTRL_1
- RT5659_ADC_MONO_HP_CTRL_2
- RT5659_ADC_MONO_L_ASRC_MASK
- RT5659_ADC_MONO_L_ASRC_SFT
- RT5659_ADC_MONO_R_ASRC_MASK
- RT5659_ADC_MONO_R_ASRC_SFT
- RT5659_ADC_OSR_128
- RT5659_ADC_OSR_16
- RT5659_ADC_OSR_32
- RT5659_ADC_OSR_64
- RT5659_ADC_OSR_MASK
- RT5659_ADC_OSR_SFT
- RT5659_ADC_R_EQ_BPF1_A1
- RT5659_ADC_R_EQ_BPF1_A2
- RT5659_ADC_R_EQ_BPF1_H0
- RT5659_ADC_R_EQ_BPF2_A1
- RT5659_ADC_R_EQ_BPF2_A2
- RT5659_ADC_R_EQ_BPF2_H0
- RT5659_ADC_R_EQ_BPF3_A1
- RT5659_ADC_R_EQ_BPF3_A2
- RT5659_ADC_R_EQ_BPF3_H0
- RT5659_ADC_R_EQ_BPF4_A1
- RT5659_ADC_R_EQ_BPF4_A2
- RT5659_ADC_R_EQ_BPF4_H0
- RT5659_ADC_R_EQ_HPF1_A1
- RT5659_ADC_R_EQ_HPF1_H0
- RT5659_ADC_R_EQ_LPF1_A1
- RT5659_ADC_R_EQ_LPF1_H0
- RT5659_ADC_R_EQ_POST_VOL
- RT5659_ADC_R_EQ_PRE_VOL
- RT5659_ADC_R_VOL_MASK
- RT5659_ADC_R_VOL_SFT
- RT5659_ADC_STO1_ASRC_MASK
- RT5659_ADC_STO1_ASRC_SFT
- RT5659_ADC_STO1_HP_CTRL_1
- RT5659_ADC_STO1_HP_CTRL_2
- RT5659_ADDA_CLK_1
- RT5659_ADDA_CLK_2
- RT5659_ADJ_HPF_CTRL_1
- RT5659_ADJ_HPF_CTRL_2
- RT5659_AD_DA_MIXER
- RT5659_AD_MONO_L_T_MASK
- RT5659_AD_MONO_L_T_SFT
- RT5659_AD_MONO_R_T_MASK
- RT5659_AD_MONO_R_T_SFT
- RT5659_AD_STO1_T_MASK
- RT5659_AD_STO1_T_SFT
- RT5659_AD_STO2_T_MASK
- RT5659_AD_STO2_T_SFT
- RT5659_AIF1
- RT5659_AIF2
- RT5659_AIF3
- RT5659_AIF4
- RT5659_AIFS
- RT5659_AJD1_CTRL
- RT5659_AJD2_AJD3_CTRL
- RT5659_ALC_BACK_GAIN
- RT5659_ALC_PGA_CTRL_1
- RT5659_ALC_PGA_CTRL_2
- RT5659_ALC_PGA_CTRL_3
- RT5659_ALC_PGA_CTRL_4
- RT5659_ALC_PGA_CTRL_5
- RT5659_ALC_PGA_CTRL_6
- RT5659_ALC_PGA_CTRL_7
- RT5659_ALC_PGA_CTRL_8
- RT5659_ALC_PGA_STA_1
- RT5659_ALC_PGA_STA_2
- RT5659_ALC_PGA_STA_3
- RT5659_AM_DIS
- RT5659_AM_EN
- RT5659_AM_MASK
- RT5659_ASRC_1
- RT5659_ASRC_10
- RT5659_ASRC_11
- RT5659_ASRC_12
- RT5659_ASRC_13
- RT5659_ASRC_2
- RT5659_ASRC_3
- RT5659_ASRC_4
- RT5659_ASRC_5
- RT5659_ASRC_6
- RT5659_ASRC_7
- RT5659_ASRC_8
- RT5659_ASRC_9
- RT5659_A_DACL1_SEL
- RT5659_A_DACL1_SFT
- RT5659_A_DACL2_SEL
- RT5659_A_DACL2_SFT
- RT5659_A_DACR1_SEL
- RT5659_A_DACR1_SFT
- RT5659_A_DACR2_SEL
- RT5659_A_DACR2_SFT
- RT5659_A_DAC_MUX
- RT5659_BASSBACK_CTRL
- RT5659_BIAS_CUR_CTRL_1
- RT5659_BIAS_CUR_CTRL_10
- RT5659_BIAS_CUR_CTRL_2
- RT5659_BIAS_CUR_CTRL_3
- RT5659_BIAS_CUR_CTRL_4
- RT5659_BIAS_CUR_CTRL_5
- RT5659_BIAS_CUR_CTRL_6
- RT5659_BIAS_CUR_CTRL_7
- RT5659_BIAS_CUR_CTRL_8
- RT5659_BIAS_CUR_CTRL_9
- RT5659_BPS_DIS
- RT5659_BPS_EN
- RT5659_BPS_MASK
- RT5659_BPS_SFT
- RT5659_BST1_MASK
- RT5659_BST1_SFT
- RT5659_BST2_MASK
- RT5659_BST2_SFT
- RT5659_BST3_MASK
- RT5659_BST3_SFT
- RT5659_BST4_MASK
- RT5659_BST4_SFT
- RT5659_CALIB_ADC_CTRL
- RT5659_CAL_BST_CTRL
- RT5659_CAL_REC
- RT5659_CHARGE_PUMP_1
- RT5659_CHARGE_PUMP_2
- RT5659_CHOP_ADC
- RT5659_CHOP_DAC
- RT5659_CKGEN_ADC1_MASK
- RT5659_CKGEN_ADC1_SFT
- RT5659_CKGEN_ADC2_MASK
- RT5659_CKGEN_ADC2_SFT
- RT5659_CKGEN_DAC1_MASK
- RT5659_CKGEN_DAC1_SFT
- RT5659_CKGEN_DAC2_MASK
- RT5659_CKGEN_DAC2_SFT
- RT5659_CKXEN_ADC1_MASK
- RT5659_CKXEN_ADC1_SFT
- RT5659_CKXEN_ADC2_MASK
- RT5659_CKXEN_ADC2_SFT
- RT5659_CKXEN_DAC1_MASK
- RT5659_CKXEN_DAC1_SFT
- RT5659_CKXEN_DAC2_MASK
- RT5659_CKXEN_DAC2_SFT
- RT5659_CLASSD_0
- RT5659_CLASSD_1
- RT5659_CLASSD_10
- RT5659_CLASSD_2
- RT5659_CLASSD_3
- RT5659_CLASSD_4
- RT5659_CLASSD_5
- RT5659_CLASSD_6
- RT5659_CLASSD_7
- RT5659_CLASSD_8
- RT5659_CLASSD_9
- RT5659_CLASSD_CTRL_1
- RT5659_CLASSD_CTRL_2
- RT5659_CLK_DET
- RT5659_CP_FQ1_MASK
- RT5659_CP_FQ1_SFT
- RT5659_CP_FQ2_MASK
- RT5659_CP_FQ2_SFT
- RT5659_CP_FQ3_MASK
- RT5659_CP_FQ3_SFT
- RT5659_CP_FQ_12_KHZ
- RT5659_CP_FQ_192_KHZ
- RT5659_CP_FQ_1_5_KHZ
- RT5659_CP_FQ_24_KHZ
- RT5659_CP_FQ_3_KHZ
- RT5659_CP_FQ_48_KHZ
- RT5659_CP_FQ_6_KHZ
- RT5659_CP_FQ_96_KHZ
- RT5659_CP_SYS_MASK
- RT5659_CP_SYS_SFT
- RT5659_CROSS_OVER_1
- RT5659_CROSS_OVER_10
- RT5659_CROSS_OVER_2
- RT5659_CROSS_OVER_3
- RT5659_CROSS_OVER_4
- RT5659_CROSS_OVER_5
- RT5659_CROSS_OVER_6
- RT5659_CROSS_OVER_7
- RT5659_CROSS_OVER_8
- RT5659_CROSS_OVER_9
- RT5659_DAC1_DIG_VOL
- RT5659_DAC1_L_SEL_IF1
- RT5659_DAC1_L_SEL_IF2
- RT5659_DAC1_L_SEL_IF3
- RT5659_DAC1_L_SEL_MASK
- RT5659_DAC1_L_SEL_SFT
- RT5659_DAC1_R_SEL_IF1
- RT5659_DAC1_R_SEL_IF2
- RT5659_DAC1_R_SEL_IF3
- RT5659_DAC1_R_SEL_MASK
- RT5659_DAC1_R_SEL_SFT
- RT5659_DAC2_DIG_VOL
- RT5659_DAC_ADC_DIG_VOL
- RT5659_DAC_CTRL
- RT5659_DAC_EQ_CTRL_1
- RT5659_DAC_EQ_CTRL_2
- RT5659_DAC_EQ_CTRL_3
- RT5659_DAC_L1_VOL_MASK
- RT5659_DAC_L1_VOL_SFT
- RT5659_DAC_L2_SEL_MASK
- RT5659_DAC_L2_SEL_SFT
- RT5659_DAC_L2_VOL_MASK
- RT5659_DAC_L2_VOL_SFT
- RT5659_DAC_L_BI_EQ_BPF1_A1_1
- RT5659_DAC_L_BI_EQ_BPF1_A1_2
- RT5659_DAC_L_BI_EQ_BPF1_A2_1
- RT5659_DAC_L_BI_EQ_BPF1_A2_2
- RT5659_DAC_L_BI_EQ_BPF1_B1_1
- RT5659_DAC_L_BI_EQ_BPF1_B1_2
- RT5659_DAC_L_BI_EQ_BPF1_B2_1
- RT5659_DAC_L_BI_EQ_BPF1_B2_2
- RT5659_DAC_L_BI_EQ_BPF1_H0_1
- RT5659_DAC_L_BI_EQ_BPF1_H0_2
- RT5659_DAC_L_EQ_BPF2_A1
- RT5659_DAC_L_EQ_BPF2_A2
- RT5659_DAC_L_EQ_BPF2_H0
- RT5659_DAC_L_EQ_BPF3_A1
- RT5659_DAC_L_EQ_BPF3_A2
- RT5659_DAC_L_EQ_BPF3_H0
- RT5659_DAC_L_EQ_BPF4_A1
- RT5659_DAC_L_EQ_BPF4_A2
- RT5659_DAC_L_EQ_BPF4_H0
- RT5659_DAC_L_EQ_HPF1_A1
- RT5659_DAC_L_EQ_HPF1_H0
- RT5659_DAC_L_EQ_HPF2_A1
- RT5659_DAC_L_EQ_HPF2_A2
- RT5659_DAC_L_EQ_HPF2_H0
- RT5659_DAC_L_EQ_LPF1_A1
- RT5659_DAC_L_EQ_LPF1_H0
- RT5659_DAC_L_EQ_POST_VOL
- RT5659_DAC_L_EQ_PRE_VOL
- RT5659_DAC_MIX_L_MASK
- RT5659_DAC_MIX_L_SFT
- RT5659_DAC_MIX_R_MASK
- RT5659_DAC_MIX_R_SFT
- RT5659_DAC_MONO_L_ASRC_MASK
- RT5659_DAC_MONO_L_ASRC_SFT
- RT5659_DAC_MONO_R_ASRC_MASK
- RT5659_DAC_MONO_R_ASRC_SFT
- RT5659_DAC_OSR_128
- RT5659_DAC_OSR_16
- RT5659_DAC_OSR_32
- RT5659_DAC_OSR_64
- RT5659_DAC_OSR_MASK
- RT5659_DAC_OSR_SFT
- RT5659_DAC_R1_VOL_MASK
- RT5659_DAC_R1_VOL_SFT
- RT5659_DAC_R2_SEL_MASK
- RT5659_DAC_R2_SEL_SFT
- RT5659_DAC_R2_VOL_MASK
- RT5659_DAC_R2_VOL_SFT
- RT5659_DAC_R_BI_EQ_BPF1_A1_1
- RT5659_DAC_R_BI_EQ_BPF1_A1_2
- RT5659_DAC_R_BI_EQ_BPF1_A2_1
- RT5659_DAC_R_BI_EQ_BPF1_A2_2
- RT5659_DAC_R_BI_EQ_BPF1_B1_1
- RT5659_DAC_R_BI_EQ_BPF1_B1_2
- RT5659_DAC_R_BI_EQ_BPF1_B2_1
- RT5659_DAC_R_BI_EQ_BPF1_B2_2
- RT5659_DAC_R_BI_EQ_BPF1_H0_1
- RT5659_DAC_R_BI_EQ_BPF1_H0_2
- RT5659_DAC_R_EQ_BPF2_A1
- RT5659_DAC_R_EQ_BPF2_A2
- RT5659_DAC_R_EQ_BPF2_H0
- RT5659_DAC_R_EQ_BPF3_A1
- RT5659_DAC_R_EQ_BPF3_A2
- RT5659_DAC_R_EQ_BPF3_H0
- RT5659_DAC_R_EQ_BPF4_A1
- RT5659_DAC_R_EQ_BPF4_A2
- RT5659_DAC_R_EQ_BPF4_H0
- RT5659_DAC_R_EQ_HPF1_A1
- RT5659_DAC_R_EQ_HPF1_H0
- RT5659_DAC_R_EQ_HPF2_A1
- RT5659_DAC_R_EQ_HPF2_A2
- RT5659_DAC_R_EQ_HPF2_H0
- RT5659_DAC_R_EQ_LPF1_A1
- RT5659_DAC_R_EQ_LPF1_H0
- RT5659_DAC_R_EQ_POST_VOL
- RT5659_DAC_R_EQ_PRE_VOL
- RT5659_DAC_STO_ASRC_MASK
- RT5659_DAC_STO_ASRC_SFT
- RT5659_DA_MONO_L_T_MASK
- RT5659_DA_MONO_L_T_SFT
- RT5659_DA_MONO_R_T_MASK
- RT5659_DA_MONO_R_T_SFT
- RT5659_DA_STO_T_MASK
- RT5659_DA_STO_T_SFT
- RT5659_DEPOP_1
- RT5659_DEPOP_2
- RT5659_DEPOP_3
- RT5659_DEPOP_AUTO
- RT5659_DEPOP_MAN
- RT5659_DEPOP_MASK
- RT5659_DEPOP_SFT
- RT5659_DEVICE_ID
- RT5659_DIG_DP_DIS
- RT5659_DIG_DP_EN
- RT5659_DIG_DP_MASK
- RT5659_DIG_DP_SFT
- RT5659_DIG_GATE_CTRL
- RT5659_DIG_GATE_CTRL_SFT
- RT5659_DIG_INF23_DATA
- RT5659_DIG_IN_CTRL_1
- RT5659_DIG_IN_CTRL_2
- RT5659_DIG_MISC
- RT5659_DIG_MIXER
- RT5659_DMIC1_DATA_GPIO11
- RT5659_DMIC1_DATA_GPIO5
- RT5659_DMIC1_DATA_GPIO9
- RT5659_DMIC1_DATA_IN2N
- RT5659_DMIC1_NULL
- RT5659_DMIC2_DATA_GPIO10
- RT5659_DMIC2_DATA_GPIO12
- RT5659_DMIC2_DATA_GPIO6
- RT5659_DMIC2_DATA_IN2P
- RT5659_DMIC2_NULL
- RT5659_DMIC_1L_LH_FALLING
- RT5659_DMIC_1L_LH_MASK
- RT5659_DMIC_1L_LH_RISING
- RT5659_DMIC_1L_LH_SFT
- RT5659_DMIC_1R_LH_FALLING
- RT5659_DMIC_1R_LH_MASK
- RT5659_DMIC_1R_LH_RISING
- RT5659_DMIC_1R_LH_SFT
- RT5659_DMIC_1_DIS
- RT5659_DMIC_1_DP_GPIO11
- RT5659_DMIC_1_DP_GPIO5
- RT5659_DMIC_1_DP_GPIO9
- RT5659_DMIC_1_DP_IN2N
- RT5659_DMIC_1_DP_MASK
- RT5659_DMIC_1_DP_SFT
- RT5659_DMIC_1_EN
- RT5659_DMIC_1_EN_MASK
- RT5659_DMIC_1_EN_SFT
- RT5659_DMIC_2_DIS
- RT5659_DMIC_2_DP_GPIO10
- RT5659_DMIC_2_DP_GPIO12
- RT5659_DMIC_2_DP_GPIO6
- RT5659_DMIC_2_DP_IN2P
- RT5659_DMIC_2_DP_MASK
- RT5659_DMIC_2_DP_SFT
- RT5659_DMIC_2_EN
- RT5659_DMIC_2_EN_MASK
- RT5659_DMIC_2_EN_SFT
- RT5659_DMIC_CLK_MASK
- RT5659_DMIC_CLK_SFT
- RT5659_DMIC_CTRL_1
- RT5659_DMIC_CTRL_2
- RT5659_DMIC_MONO_L_ASRC_MASK
- RT5659_DMIC_MONO_L_ASRC_SFT
- RT5659_DMIC_MONO_R_ASRC_MASK
- RT5659_DMIC_MONO_R_ASRC_SFT
- RT5659_DMIC_STO1_ASRC_MASK
- RT5659_DMIC_STO1_ASRC_SFT
- RT5659_DP_TH_MASK
- RT5659_DP_TH_SFT
- RT5659_DRC1_CTRL_1
- RT5659_DRC1_CTRL_2
- RT5659_DRC1_CTRL_3
- RT5659_DRC1_CTRL_4
- RT5659_DRC1_CTRL_5
- RT5659_DRC1_CTRL_6
- RT5659_DRC1_HARD_LMT_CTRL_1
- RT5659_DRC1_HARD_LMT_CTRL_2
- RT5659_DRC1_PRIV_1
- RT5659_DRC1_PRIV_2
- RT5659_DRC1_PRIV_3
- RT5659_DRC1_PRIV_4
- RT5659_DRC1_PRIV_5
- RT5659_DRC1_PRIV_6
- RT5659_DRC1_PRIV_7
- RT5659_DRC2_CTRL_1
- RT5659_DRC2_CTRL_2
- RT5659_DRC2_CTRL_3
- RT5659_DRC2_CTRL_4
- RT5659_DRC2_CTRL_5
- RT5659_DRC2_CTRL_6
- RT5659_DRC2_HARD_LMT_CTRL_1
- RT5659_DRC2_HARD_LMT_CTRL_2
- RT5659_DRC2_PRIV_1
- RT5659_DRC2_PRIV_2
- RT5659_DRC2_PRIV_3
- RT5659_DRC2_PRIV_4
- RT5659_DRC2_PRIV_5
- RT5659_DRC2_PRIV_6
- RT5659_DRC2_PRIV_7
- RT5659_DS_ADC_SLOT01_SFT
- RT5659_DS_ADC_SLOT23_SFT
- RT5659_DS_ADC_SLOT45_SFT
- RT5659_DS_ADC_SLOT67_SFT
- RT5659_DUMMY_2
- RT5659_DUMMY_3
- RT5659_DUMMY_4
- RT5659_DUMMY_5
- RT5659_DUMMY_6
- RT5659_EJD_CTRL_1
- RT5659_EJD_CTRL_2
- RT5659_EJD_CTRL_3
- RT5659_EMB_JD_EN
- RT5659_EMB_JD_EN_SFT
- RT5659_EQ_CD_DIS
- RT5659_EQ_CD_EN
- RT5659_EQ_CD_MASK
- RT5659_EQ_CD_SFT
- RT5659_EQ_DITH_LSB
- RT5659_EQ_DITH_LSB_1
- RT5659_EQ_DITH_LSB_2
- RT5659_EQ_DITH_MASK
- RT5659_EQ_DITH_NOR
- RT5659_EQ_DITH_SFT
- RT5659_EQ_SRC_ADC
- RT5659_EQ_SRC_DAC
- RT5659_EQ_UPD
- RT5659_EQ_UPD_BIT
- RT5659_EXT_JD_DIG
- RT5659_EXT_JD_EN
- RT5659_EXT_JD_EN_SFT
- RT5659_EXT_JD_SRC
- RT5659_EXT_JD_SRC_GPIO_JD1
- RT5659_EXT_JD_SRC_GPIO_JD2
- RT5659_EXT_JD_SRC_JD1_1
- RT5659_EXT_JD_SRC_JD1_2
- RT5659_EXT_JD_SRC_JD2
- RT5659_EXT_JD_SRC_JD3
- RT5659_EXT_JD_SRC_MANUAL
- RT5659_EXT_JD_SRC_SFT
- RT5659_FAST_UPDN_DIS
- RT5659_FAST_UPDN_EN
- RT5659_FAST_UPDN_MASK
- RT5659_FAST_UPDN_SFT
- RT5659_FLEX_SPK_BST_CTRL_1
- RT5659_FLEX_SPK_BST_CTRL_2
- RT5659_FLEX_SPK_BST_CTRL_3
- RT5659_FLEX_SPK_BST_CTRL_4
- RT5659_FORMATS
- RT5659_GLB_CLK
- RT5659_GP10_PIN_DMIC2_SDA
- RT5659_GP10_PIN_GPIO10
- RT5659_GP10_PIN_MASK
- RT5659_GP10_PIN_SFT
- RT5659_GP11_PIN_DMIC1_SDA
- RT5659_GP11_PIN_GPIO11
- RT5659_GP11_PIN_MASK
- RT5659_GP11_PIN_SFT
- RT5659_GP12_PIN_DMIC2_SDA
- RT5659_GP12_PIN_GPIO12
- RT5659_GP12_PIN_MASK
- RT5659_GP12_PIN_SFT
- RT5659_GP13_PIN_DMIC2_SCL
- RT5659_GP13_PIN_GPIO13
- RT5659_GP13_PIN_MASK
- RT5659_GP13_PIN_PDM_SCL
- RT5659_GP13_PIN_SFT
- RT5659_GP13_PIN_SPDIF_SDA
- RT5659_GP15_PIN_DMIC3_SCL
- RT5659_GP15_PIN_GPIO15
- RT5659_GP15_PIN_MASK
- RT5659_GP15_PIN_PDM_SDA
- RT5659_GP15_PIN_SFT
- RT5659_GP1_PF_IN
- RT5659_GP1_PF_MASK
- RT5659_GP1_PF_OUT
- RT5659_GP1_PF_SFT
- RT5659_GP1_PIN_GPIO1
- RT5659_GP1_PIN_IRQ
- RT5659_GP1_PIN_MASK
- RT5659_GP1_PIN_SFT
- RT5659_GP2_PIN_DMIC1_SCL
- RT5659_GP2_PIN_GPIO2
- RT5659_GP2_PIN_MASK
- RT5659_GP2_PIN_SFT
- RT5659_GP3_PIN_GPIO3
- RT5659_GP3_PIN_MASK
- RT5659_GP3_PIN_PDM_SCL
- RT5659_GP3_PIN_SFT
- RT5659_GP4_PIN_GPIO4
- RT5659_GP4_PIN_MASK
- RT5659_GP4_PIN_PDM_SDA
- RT5659_GP4_PIN_SFT
- RT5659_GP5_PIN_DMIC1_SDA
- RT5659_GP5_PIN_GPIO5
- RT5659_GP5_PIN_MASK
- RT5659_GP5_PIN_SFT
- RT5659_GP6_PIN_DMIC2_SDA
- RT5659_GP6_PIN_GPIO6
- RT5659_GP6_PIN_MASK
- RT5659_GP6_PIN_SFT
- RT5659_GP7_PIN_GPIO7
- RT5659_GP7_PIN_MASK
- RT5659_GP7_PIN_PDM_SCL
- RT5659_GP7_PIN_SFT
- RT5659_GP8_PIN_GPIO8
- RT5659_GP8_PIN_MASK
- RT5659_GP8_PIN_PDM_SDA
- RT5659_GP8_PIN_SFT
- RT5659_GP9_PIN_DMIC1_SDA
- RT5659_GP9_PIN_GPIO9
- RT5659_GP9_PIN_MASK
- RT5659_GP9_PIN_SFT
- RT5659_GPIO_CTRL_1
- RT5659_GPIO_CTRL_2
- RT5659_GPIO_CTRL_3
- RT5659_GPIO_CTRL_4
- RT5659_GPIO_CTRL_5
- RT5659_GPIO_STA
- RT5659_G_BST1_OM_L_MASK
- RT5659_G_BST1_OM_L_SFT
- RT5659_G_BST2_OM_L_MASK
- RT5659_G_BST2_OM_L_SFT
- RT5659_G_BST3_OM_L_MASK
- RT5659_G_BST3_OM_L_SFT
- RT5659_G_DAC_L1_MONO_L_MASK
- RT5659_G_DAC_L1_MONO_L_SFT
- RT5659_G_DAC_L1_MONO_R_MASK
- RT5659_G_DAC_L1_MONO_R_SFT
- RT5659_G_DAC_L1_STO_L_MASK
- RT5659_G_DAC_L1_STO_L_SFT
- RT5659_G_DAC_L1_STO_R_MASK
- RT5659_G_DAC_L1_STO_R_SFT
- RT5659_G_DAC_L2_MONO_L_MASK
- RT5659_G_DAC_L2_MONO_L_SFT
- RT5659_G_DAC_L2_MONO_R_MASK
- RT5659_G_DAC_L2_MONO_R_SFT
- RT5659_G_DAC_L2_OM_L_MASK
- RT5659_G_DAC_L2_OM_L_SFT
- RT5659_G_DAC_L2_STO_L_MASK
- RT5659_G_DAC_L2_STO_L_SFT
- RT5659_G_DAC_L2_STO_R_MASK
- RT5659_G_DAC_L2_STO_R_SFT
- RT5659_G_DAC_R1_MONO_L_MASK
- RT5659_G_DAC_R1_MONO_L_SFT
- RT5659_G_DAC_R1_MONO_R_MASK
- RT5659_G_DAC_R1_MONO_R_SFT
- RT5659_G_DAC_R1_STO_L_MASK
- RT5659_G_DAC_R1_STO_L_SFT
- RT5659_G_DAC_R1_STO_R_MASK
- RT5659_G_DAC_R1_STO_R_SFT
- RT5659_G_DAC_R2_MONO_L_MASK
- RT5659_G_DAC_R2_MONO_L_SFT
- RT5659_G_DAC_R2_MONO_R_MASK
- RT5659_G_DAC_R2_MONO_R_SFT
- RT5659_G_DAC_R2_STO_L_MASK
- RT5659_G_DAC_R2_STO_L_SFT
- RT5659_G_DAC_R2_STO_R_MASK
- RT5659_G_DAC_R2_STO_R_SFT
- RT5659_G_HP
- RT5659_G_HP_SFT
- RT5659_G_IN_L_OM_L_MASK
- RT5659_G_IN_L_OM_L_SFT
- RT5659_G_STO_DA_DMIX
- RT5659_G_STO_DA_SFT
- RT5659_HAPTIC_GEN_CTRL_1
- RT5659_HAPTIC_GEN_CTRL_10
- RT5659_HAPTIC_GEN_CTRL_11
- RT5659_HAPTIC_GEN_CTRL_2
- RT5659_HAPTIC_GEN_CTRL_3
- RT5659_HAPTIC_GEN_CTRL_4
- RT5659_HAPTIC_GEN_CTRL_5
- RT5659_HAPTIC_GEN_CTRL_6
- RT5659_HAPTIC_GEN_CTRL_7
- RT5659_HAPTIC_GEN_CTRL_8
- RT5659_HAPTIC_GEN_CTRL_9
- RT5659_HAPTIC_LPF_CTRL_1
- RT5659_HAPTIC_LPF_CTRL_2
- RT5659_HAPTIC_LPF_CTRL_3
- RT5659_HPL_GAIN
- RT5659_HPR_GAIN
- RT5659_HP_AMP_DET_CTRL_1
- RT5659_HP_AMP_DET_CTRL_2
- RT5659_HP_CALIB_CTRL_1
- RT5659_HP_CALIB_CTRL_10
- RT5659_HP_CALIB_CTRL_11
- RT5659_HP_CALIB_CTRL_2
- RT5659_HP_CALIB_CTRL_3
- RT5659_HP_CALIB_CTRL_4
- RT5659_HP_CALIB_CTRL_5
- RT5659_HP_CALIB_CTRL_6
- RT5659_HP_CALIB_CTRL_7
- RT5659_HP_CALIB_CTRL_9
- RT5659_HP_CALIB_STA_1
- RT5659_HP_CALIB_STA_2
- RT5659_HP_CALIB_STA_3
- RT5659_HP_CALIB_STA_4
- RT5659_HP_CALIB_STA_5
- RT5659_HP_CALIB_STA_6
- RT5659_HP_CALIB_STA_7
- RT5659_HP_CALIB_STA_8
- RT5659_HP_CALIB_STA_9
- RT5659_HP_CB_MASK
- RT5659_HP_CB_PD
- RT5659_HP_CB_PU
- RT5659_HP_CB_SFT
- RT5659_HP_CD_PD_DIS
- RT5659_HP_CD_PD_EN
- RT5659_HP_CD_PD_MASK
- RT5659_HP_CD_PD_SFT
- RT5659_HP_CHARGE_PUMP_1
- RT5659_HP_CHARGE_PUMP_2
- RT5659_HP_CO_DIS
- RT5659_HP_CO_EN
- RT5659_HP_CO_MASK
- RT5659_HP_CO_SFT
- RT5659_HP_CP_MASK
- RT5659_HP_CP_PD
- RT5659_HP_CP_PU
- RT5659_HP_CP_SFT
- RT5659_HP_DECROSS_CTRL_1
- RT5659_HP_DECROSS_CTRL_2
- RT5659_HP_DECROSS_CTRL_3
- RT5659_HP_DECROSS_CTRL_4
- RT5659_HP_DP_MASK
- RT5659_HP_DP_PD
- RT5659_HP_DP_PU
- RT5659_HP_DP_SFT
- RT5659_HP_IMP_GAIN_1
- RT5659_HP_IMP_GAIN_2
- RT5659_HP_IMP_SENS_CTRL_1
- RT5659_HP_IMP_SENS_CTRL_2
- RT5659_HP_IMP_SENS_CTRL_3
- RT5659_HP_IMP_SENS_CTRL_4
- RT5659_HP_IMP_SENS_MAP_1
- RT5659_HP_IMP_SENS_MAP_2
- RT5659_HP_IMP_SENS_MAP_3
- RT5659_HP_IMP_SENS_MAP_4
- RT5659_HP_IMP_SENS_MAP_5
- RT5659_HP_IMP_SENS_MAP_6
- RT5659_HP_IMP_SENS_MAP_7
- RT5659_HP_IMP_SENS_MAP_8
- RT5659_HP_LOGIC_CTRL_1
- RT5659_HP_LOGIC_CTRL_2
- RT5659_HP_L_SMT_DIS
- RT5659_HP_L_SMT_EN
- RT5659_HP_L_SMT_MASK
- RT5659_HP_L_SMT_SFT
- RT5659_HP_R_SMT_DIS
- RT5659_HP_R_SMT_EN
- RT5659_HP_R_SMT_MASK
- RT5659_HP_R_SMT_SFT
- RT5659_HP_SG_DIS
- RT5659_HP_SG_EN
- RT5659_HP_SG_MASK
- RT5659_HP_SG_SFT
- RT5659_HP_SV_DIS
- RT5659_HP_SV_EN
- RT5659_HP_SV_MASK
- RT5659_HP_SV_SFT
- RT5659_HP_VOL
- RT5659_I2S1_ASRC_MASK
- RT5659_I2S1_ASRC_SFT
- RT5659_I2S1_RATE_MASK
- RT5659_I2S1_RATE_SFT
- RT5659_I2S1_SDP
- RT5659_I2S2_ASRC_MASK
- RT5659_I2S2_ASRC_SFT
- RT5659_I2S2_PIN_GPIO
- RT5659_I2S2_PIN_I2S
- RT5659_I2S2_PIN_MASK
- RT5659_I2S2_PIN_SFT
- RT5659_I2S2_RATE_MASK
- RT5659_I2S2_RATE_SFT
- RT5659_I2S2_SDP
- RT5659_I2S3_ASRC_MASK
- RT5659_I2S3_ASRC_SFT
- RT5659_I2S3_RATE_MASK
- RT5659_I2S3_RATE_SFT
- RT5659_I2S3_SDP
- RT5659_I2S_BCLK_MS2_32
- RT5659_I2S_BCLK_MS2_64
- RT5659_I2S_BCLK_MS2_MASK
- RT5659_I2S_BCLK_MS2_SFT
- RT5659_I2S_BCLK_MS3_32
- RT5659_I2S_BCLK_MS3_64
- RT5659_I2S_BCLK_MS3_MASK
- RT5659_I2S_BCLK_MS3_SFT
- RT5659_I2S_BP_INV
- RT5659_I2S_BP_MASK
- RT5659_I2S_BP_NOR
- RT5659_I2S_BP_SFT
- RT5659_I2S_DF_I2S
- RT5659_I2S_DF_LEFT
- RT5659_I2S_DF_MASK
- RT5659_I2S_DF_PCM_A
- RT5659_I2S_DF_PCM_A_N
- RT5659_I2S_DF_PCM_B
- RT5659_I2S_DF_PCM_B_N
- RT5659_I2S_DF_SFT
- RT5659_I2S_DL_16
- RT5659_I2S_DL_20
- RT5659_I2S_DL_24
- RT5659_I2S_DL_8
- RT5659_I2S_DL_MASK
- RT5659_I2S_DL_SFT
- RT5659_I2S_I_CP_A_LAW
- RT5659_I2S_I_CP_MASK
- RT5659_I2S_I_CP_OFF
- RT5659_I2S_I_CP_SFT
- RT5659_I2S_I_CP_U_LAW
- RT5659_I2S_MS_M
- RT5659_I2S_MS_MASK
- RT5659_I2S_MS_S
- RT5659_I2S_MS_SFT
- RT5659_I2S_O_CP_A_LAW
- RT5659_I2S_O_CP_MASK
- RT5659_I2S_O_CP_OFF
- RT5659_I2S_O_CP_SFT
- RT5659_I2S_O_CP_U_LAW
- RT5659_I2S_PD1_1
- RT5659_I2S_PD1_12
- RT5659_I2S_PD1_16
- RT5659_I2S_PD1_2
- RT5659_I2S_PD1_3
- RT5659_I2S_PD1_4
- RT5659_I2S_PD1_6
- RT5659_I2S_PD1_8
- RT5659_I2S_PD1_MASK
- RT5659_I2S_PD1_SFT
- RT5659_I2S_PD2_1
- RT5659_I2S_PD2_12
- RT5659_I2S_PD2_16
- RT5659_I2S_PD2_2
- RT5659_I2S_PD2_3
- RT5659_I2S_PD2_4
- RT5659_I2S_PD2_6
- RT5659_I2S_PD2_8
- RT5659_I2S_PD2_MASK
- RT5659_I2S_PD2_SFT
- RT5659_I2S_PD3_1
- RT5659_I2S_PD3_12
- RT5659_I2S_PD3_16
- RT5659_I2S_PD3_2
- RT5659_I2S_PD3_3
- RT5659_I2S_PD3_4
- RT5659_I2S_PD3_6
- RT5659_I2S_PD3_8
- RT5659_I2S_PD3_MASK
- RT5659_I2S_PD3_SFT
- RT5659_IB_HP_125IL
- RT5659_IB_HP_1IL
- RT5659_IB_HP_25IL
- RT5659_IB_HP_5IL
- RT5659_IB_HP_MASK
- RT5659_IB_HP_SFT
- RT5659_IF2_ADC3_IN_MASK
- RT5659_IF2_ADC3_IN_SFT
- RT5659_IF2_ADC_IN_MASK
- RT5659_IF2_ADC_IN_SFT
- RT5659_IF2_ADC_SEL_MASK
- RT5659_IF2_ADC_SEL_SFT
- RT5659_IF2_DAC_SEL_MASK
- RT5659_IF2_DAC_SEL_SFT
- RT5659_IF3_ADC_IN_MASK
- RT5659_IF3_ADC_IN_SFT
- RT5659_IF3_ADC_SEL_MASK
- RT5659_IF3_ADC_SEL_SFT
- RT5659_IF3_DAC_SEL_MASK
- RT5659_IF3_DAC_SEL_SFT
- RT5659_IL_CMD_1
- RT5659_IL_CMD_2
- RT5659_IL_CMD_3
- RT5659_IL_CMD_4
- RT5659_IL_IRQ_DIS
- RT5659_IL_IRQ_EN
- RT5659_IL_IRQ_MASK
- RT5659_IN1_DF
- RT5659_IN1_DF_MASK
- RT5659_IN1_IN2
- RT5659_IN3_DF
- RT5659_IN3_DF_MASK
- RT5659_IN3_IN4
- RT5659_IN4_DF
- RT5659_IN4_DF_MASK
- RT5659_INL1_INR1_VOL
- RT5659_INL_VOL_MASK
- RT5659_INL_VOL_SFT
- RT5659_INR_VOL_MASK
- RT5659_INR_VOL_SFT
- RT5659_INT_ST_1
- RT5659_INT_ST_2
- RT5659_IRQ_CTRL_1
- RT5659_IRQ_CTRL_2
- RT5659_IRQ_CTRL_3
- RT5659_IRQ_CTRL_4
- RT5659_IRQ_CTRL_5
- RT5659_IRQ_CTRL_6
- RT5659_IRQ_JD_EN
- RT5659_IRQ_JD_EN_SFT
- RT5659_JD1_1_DIS
- RT5659_JD1_1_EN
- RT5659_JD1_1_EN_MASK
- RT5659_JD1_1_EN_SFT
- RT5659_JD1_2_DIS
- RT5659_JD1_2_EN
- RT5659_JD1_2_EN_MASK
- RT5659_JD1_2_EN_SFT
- RT5659_JD1_MODE_0
- RT5659_JD1_MODE_1
- RT5659_JD1_MODE_2
- RT5659_JD1_MODE_MASK
- RT5659_JD1_THD
- RT5659_JD2_THD
- RT5659_JD3
- RT5659_JD3_THD
- RT5659_JD_CTRL_1
- RT5659_JD_CTRL_2
- RT5659_JD_CTRL_3
- RT5659_JD_CTRL_4
- RT5659_JD_HDA_HEADER
- RT5659_JD_HPO_GPIO_JD1
- RT5659_JD_HPO_GPIO_JD2
- RT5659_JD_HPO_JD1_1
- RT5659_JD_HPO_JD1_2
- RT5659_JD_HPO_JD2
- RT5659_JD_HPO_JD3
- RT5659_JD_HPO_JD_D
- RT5659_JD_MODE
- RT5659_JD_MODE_SFT
- RT5659_JD_NULL
- RT5659_JD_TRI_HPO_SEL_MASK
- RT5659_JD_TRI_HPO_SEL_SFT
- RT5659_LDO_CTRL
- RT5659_LOUT
- RT5659_LOUT_MIXER
- RT5659_LOW_HP_AMP_DET
- RT5659_L_MUTE
- RT5659_L_MUTE_SFT
- RT5659_L_VOL_MASK
- RT5659_L_VOL_SFT
- RT5659_MEMORY_TEST
- RT5659_MIC1_BS_75AV
- RT5659_MIC1_BS_9AV
- RT5659_MIC1_BS_MASK
- RT5659_MIC1_BS_SFT
- RT5659_MIC1_CLK_DIS
- RT5659_MIC1_CLK_EN
- RT5659_MIC1_CLK_MASK
- RT5659_MIC1_CLK_SFT
- RT5659_MIC1_OVCD_DIS
- RT5659_MIC1_OVCD_EN
- RT5659_MIC1_OVCD_MASK
- RT5659_MIC1_OVCD_SFT
- RT5659_MIC1_OVTH_1500UA
- RT5659_MIC1_OVTH_2000UA
- RT5659_MIC1_OVTH_600UA
- RT5659_MIC1_OVTH_MASK
- RT5659_MIC1_OVTH_SFT
- RT5659_MIC2_BS_75AV
- RT5659_MIC2_BS_9AV
- RT5659_MIC2_BS_MASK
- RT5659_MIC2_BS_SFT
- RT5659_MIC2_CLK_DIS
- RT5659_MIC2_CLK_EN
- RT5659_MIC2_CLK_MASK
- RT5659_MIC2_CLK_SFT
- RT5659_MIC2_OVCD_DIS
- RT5659_MIC2_OVCD_EN
- RT5659_MIC2_OVCD_MASK
- RT5659_MIC2_OVCD_SFT
- RT5659_MIC2_OVTH_1500UA
- RT5659_MIC2_OVTH_2000UA
- RT5659_MIC2_OVTH_600UA
- RT5659_MIC2_OVTH_MASK
- RT5659_MIC2_OVTH_SFT
- RT5659_MICBIAS_1
- RT5659_MICBIAS_2
- RT5659_MID_HP_AMP_DET
- RT5659_MONOMIX_GAIN
- RT5659_MONOMIX_IN_GAIN
- RT5659_MONO_ADC_DIG_VOL
- RT5659_MONO_ADC_L1_SRC_MASK
- RT5659_MONO_ADC_L1_SRC_SFT
- RT5659_MONO_ADC_L2_SRC_MASK
- RT5659_MONO_ADC_L2_SRC_SFT
- RT5659_MONO_ADC_L_BST_MASK
- RT5659_MONO_ADC_L_BST_SFT
- RT5659_MONO_ADC_L_SRC_MASK
- RT5659_MONO_ADC_L_SRC_SFT
- RT5659_MONO_ADC_L_VOL_MASK
- RT5659_MONO_ADC_L_VOL_SFT
- RT5659_MONO_ADC_MIXER
- RT5659_MONO_ADC_R1_SRC_MASK
- RT5659_MONO_ADC_R1_SRC_SFT
- RT5659_MONO_ADC_R2_SRC_MASK
- RT5659_MONO_ADC_R2_SRC_SFT
- RT5659_MONO_ADC_R_BST_MASK
- RT5659_MONO_ADC_R_BST_SFT
- RT5659_MONO_ADC_R_SRC_MASK
- RT5659_MONO_ADC_R_SRC_SFT
- RT5659_MONO_ADC_R_VOL_MASK
- RT5659_MONO_ADC_R_VOL_SFT
- RT5659_MONO_AMP_CALIB_CTRL_1
- RT5659_MONO_AMP_CALIB_CTRL_2
- RT5659_MONO_AMP_CALIB_CTRL_3
- RT5659_MONO_AMP_CALIB_CTRL_4
- RT5659_MONO_AMP_CALIB_CTRL_5
- RT5659_MONO_AMP_CALIB_STA_1
- RT5659_MONO_AMP_CALIB_STA_2
- RT5659_MONO_AMP_CALIB_STA_3
- RT5659_MONO_AMP_CALIB_STA_4
- RT5659_MONO_BOOST
- RT5659_MONO_DAC_MIXER
- RT5659_MONO_DMIC_L_SRC_MASK
- RT5659_MONO_DMIC_L_SRC_SFT
- RT5659_MONO_DMIC_R_SRC_MASK
- RT5659_MONO_DMIC_R_SRC_SFT
- RT5659_MONO_GAIN
- RT5659_MONO_NG2_CTRL_1
- RT5659_MONO_NG2_CTRL_2
- RT5659_MONO_NG2_CTRL_3
- RT5659_MONO_NG2_CTRL_4
- RT5659_MONO_NG2_CTRL_5
- RT5659_MONO_NG2_CTRL_6
- RT5659_MONO_OUT
- RT5659_MP3_HPF_A1
- RT5659_MP3_HPF_A2
- RT5659_MP3_HPF_H0
- RT5659_MP3_LPF_H0
- RT5659_MP3_PLUS_CTRL_1
- RT5659_MP3_PLUS_CTRL_2
- RT5659_MRES_15MO
- RT5659_MRES_25MO
- RT5659_MRES_35MO
- RT5659_MRES_45MO
- RT5659_MRES_MASK
- RT5659_MRES_SFT
- RT5659_MULTI_DRC_CTRL
- RT5659_M_ADCMIX_L
- RT5659_M_ADCMIX_L_SFT
- RT5659_M_ADCMIX_R
- RT5659_M_ADCMIX_R_SFT
- RT5659_M_BST1_MM
- RT5659_M_BST1_MM_SFT
- RT5659_M_BST1_OM_L
- RT5659_M_BST1_OM_L_SFT
- RT5659_M_BST1_RM1_L
- RT5659_M_BST1_RM1_L_SFT
- RT5659_M_BST1_RM1_R
- RT5659_M_BST1_RM1_R_SFT
- RT5659_M_BST1_RM2_L
- RT5659_M_BST1_RM2_L_SFT
- RT5659_M_BST1_RM2_R
- RT5659_M_BST1_RM2_R_SFT
- RT5659_M_BST1_SM_L
- RT5659_M_BST1_SM_L_SFT
- RT5659_M_BST2_MM
- RT5659_M_BST2_MM_SFT
- RT5659_M_BST2_OM_L
- RT5659_M_BST2_OM_L_SFT
- RT5659_M_BST2_OM_R
- RT5659_M_BST2_OM_R_SFT
- RT5659_M_BST2_RM1_L
- RT5659_M_BST2_RM1_L_SFT
- RT5659_M_BST2_RM1_R
- RT5659_M_BST2_RM1_R_SFT
- RT5659_M_BST2_RM2_L
- RT5659_M_BST2_RM2_L_SFT
- RT5659_M_BST2_RM2_R
- RT5659_M_BST2_RM2_R_SFT
- RT5659_M_BST3_MM
- RT5659_M_BST3_MM_SFT
- RT5659_M_BST3_OM_L
- RT5659_M_BST3_OM_L_SFT
- RT5659_M_BST3_OM_R
- RT5659_M_BST3_OM_R_SFT
- RT5659_M_BST3_RM1_L
- RT5659_M_BST3_RM1_L_SFT
- RT5659_M_BST3_RM1_R
- RT5659_M_BST3_RM1_R_SFT
- RT5659_M_BST3_RM2_L
- RT5659_M_BST3_RM2_L_SFT
- RT5659_M_BST3_RM2_R
- RT5659_M_BST3_RM2_R_SFT
- RT5659_M_BST3_SM_L
- RT5659_M_BST3_SM_L_SFT
- RT5659_M_BST3_SM_R
- RT5659_M_BST3_SM_R_SFT
- RT5659_M_BST4_OM_R
- RT5659_M_BST4_OM_R_SFT
- RT5659_M_BST4_RM1_L
- RT5659_M_BST4_RM1_L_SFT
- RT5659_M_BST4_RM1_R
- RT5659_M_BST4_RM1_R_SFT
- RT5659_M_BST4_RM2_L
- RT5659_M_BST4_RM2_L_SFT
- RT5659_M_BST4_RM2_R
- RT5659_M_BST4_RM2_R_SFT
- RT5659_M_BST4_SM_R
- RT5659_M_BST4_SM_R_SFT
- RT5659_M_DAC1_L
- RT5659_M_DAC1_L_SFT
- RT5659_M_DAC1_R
- RT5659_M_DAC1_R_SFT
- RT5659_M_DAC2_L_VOL
- RT5659_M_DAC2_L_VOL_SFT
- RT5659_M_DAC2_R_VOL
- RT5659_M_DAC2_R_VOL_SFT
- RT5659_M_DAC_L1_MONO_L
- RT5659_M_DAC_L1_MONO_L_SFT
- RT5659_M_DAC_L1_MONO_R
- RT5659_M_DAC_L1_MONO_R_SFT
- RT5659_M_DAC_L1_STO_L
- RT5659_M_DAC_L1_STO_L_SFT
- RT5659_M_DAC_L1_STO_R
- RT5659_M_DAC_L1_STO_R_SFT
- RT5659_M_DAC_L2_LM
- RT5659_M_DAC_L2_LM_SFT
- RT5659_M_DAC_L2_MA
- RT5659_M_DAC_L2_MA_SFT
- RT5659_M_DAC_L2_MM
- RT5659_M_DAC_L2_MM_SFT
- RT5659_M_DAC_L2_MONO_L
- RT5659_M_DAC_L2_MONO_L_SFT
- RT5659_M_DAC_L2_MONO_R
- RT5659_M_DAC_L2_MONO_R_SFT
- RT5659_M_DAC_L2_OM_L
- RT5659_M_DAC_L2_OM_L_SFT
- RT5659_M_DAC_L2_SM_L
- RT5659_M_DAC_L2_SM_L_SFT
- RT5659_M_DAC_L2_SPKOMIX
- RT5659_M_DAC_L2_SPKOMIX_SFT
- RT5659_M_DAC_L2_STO_L
- RT5659_M_DAC_L2_STO_L_SFT
- RT5659_M_DAC_L2_STO_R
- RT5659_M_DAC_L2_STO_R_SFT
- RT5659_M_DAC_MIX_L
- RT5659_M_DAC_MIX_L_SFT
- RT5659_M_DAC_MIX_R
- RT5659_M_DAC_MIX_R_SFT
- RT5659_M_DAC_R1_MONO_L
- RT5659_M_DAC_R1_MONO_L_SFT
- RT5659_M_DAC_R1_MONO_R
- RT5659_M_DAC_R1_MONO_R_SFT
- RT5659_M_DAC_R1_STO_L
- RT5659_M_DAC_R1_STO_L_SFT
- RT5659_M_DAC_R1_STO_R
- RT5659_M_DAC_R1_STO_R_SFT
- RT5659_M_DAC_R2_LM
- RT5659_M_DAC_R2_LM_SFT
- RT5659_M_DAC_R2_MM
- RT5659_M_DAC_R2_MM_SFT
- RT5659_M_DAC_R2_MONO_L
- RT5659_M_DAC_R2_MONO_L_SFT
- RT5659_M_DAC_R2_MONO_R
- RT5659_M_DAC_R2_MONO_R_SFT
- RT5659_M_DAC_R2_OM_R
- RT5659_M_DAC_R2_OM_R_SFT
- RT5659_M_DAC_R2_SM_R
- RT5659_M_DAC_R2_SM_R_SFT
- RT5659_M_DAC_R2_SPKOMIX
- RT5659_M_DAC_R2_SPKOMIX_SFT
- RT5659_M_DAC_R2_STO_L
- RT5659_M_DAC_R2_STO_L_SFT
- RT5659_M_DAC_R2_STO_R
- RT5659_M_DAC_R2_STO_R_SFT
- RT5659_M_HPOVOLR_RM1_R
- RT5659_M_HPOVOLR_RM1_R_SFT
- RT5659_M_INL_RM1_L
- RT5659_M_INL_RM1_L_SFT
- RT5659_M_INR_RM1_R
- RT5659_M_INR_RM1_R_SFT
- RT5659_M_IN_L_OM_L
- RT5659_M_IN_L_OM_L_SFT
- RT5659_M_IN_L_SM_L
- RT5659_M_IN_L_SM_L_SFT
- RT5659_M_IN_L_SM_R
- RT5659_M_IN_L_SM_R_SFT
- RT5659_M_IN_R_OM_R
- RT5659_M_IN_R_OM_R_SFT
- RT5659_M_IN_R_SM_L
- RT5659_M_IN_R_SM_L_SFT
- RT5659_M_IN_R_SM_R
- RT5659_M_IN_R_SM_R_SFT
- RT5659_M_MONOVOL_MA
- RT5659_M_MONOVOL_MA_SFT
- RT5659_M_MONOVOL_RM2_R
- RT5659_M_MONOVOL_RM2_R_SFT
- RT5659_M_MONO_ADC_L1
- RT5659_M_MONO_ADC_L1_SFT
- RT5659_M_MONO_ADC_L2
- RT5659_M_MONO_ADC_L2_SFT
- RT5659_M_MONO_ADC_R1
- RT5659_M_MONO_ADC_R1_SFT
- RT5659_M_MONO_ADC_R2
- RT5659_M_MONO_ADC_R2_SFT
- RT5659_M_OUTVOLL_RM2_L
- RT5659_M_OUTVOLL_RM2_L_SFT
- RT5659_M_OUTVOLR_RM2_R
- RT5659_M_OUTVOLR_RM2_R_SFT
- RT5659_M_OV_L_LM
- RT5659_M_OV_L_LM_SFT
- RT5659_M_OV_R_LM
- RT5659_M_OV_R_LM_SFT
- RT5659_M_PDM1_L
- RT5659_M_PDM1_L_SFT
- RT5659_M_PDM1_R
- RT5659_M_PDM1_R_SFT
- RT5659_M_RF_DIG_MASK
- RT5659_M_RF_DIG_SFT
- RT5659_M_RI_DIG
- RT5659_M_SPKVOLL_RM1_L
- RT5659_M_SPKVOLL_RM1_L_SFT
- RT5659_M_SPKVOLL_SPKOMIX
- RT5659_M_SPKVOLL_SPKOMIX_SFT
- RT5659_M_SPKVOLR_SPKOMIX
- RT5659_M_SPKVOLR_SPKOMIX_SFT
- RT5659_M_SPKVOL_RM2_L
- RT5659_M_SPKVOL_RM2_L_SFT
- RT5659_M_STO1_ADC_L1
- RT5659_M_STO1_ADC_L1_SFT
- RT5659_M_STO1_ADC_L2
- RT5659_M_STO1_ADC_L2_SFT
- RT5659_M_STO1_ADC_R1
- RT5659_M_STO1_ADC_R1_SFT
- RT5659_M_STO1_ADC_R2
- RT5659_M_STO1_ADC_R2_SFT
- RT5659_NG2_DIS
- RT5659_NG2_EN
- RT5659_NG2_EN_MASK
- RT5659_OSW_L_DIS
- RT5659_OSW_L_EN
- RT5659_OSW_L_MASK
- RT5659_OSW_L_SFT
- RT5659_OSW_R_DIS
- RT5659_OSW_R_EN
- RT5659_OSW_R_MASK
- RT5659_OSW_R_SFT
- RT5659_OUT_L_GAIN
- RT5659_OUT_L_MIXER
- RT5659_OUT_R_GAIN
- RT5659_OUT_R_MIXER
- RT5659_OUT_SV_DIS
- RT5659_OUT_SV_EN
- RT5659_OUT_SV_MASK
- RT5659_OUT_SV_SFT
- RT5659_PAD_DRIVING_CTRL
- RT5659_PDM1_BUSY
- RT5659_PDM1_L_MASK
- RT5659_PDM1_L_SFT
- RT5659_PDM1_R_MASK
- RT5659_PDM1_R_SFT
- RT5659_PDM2_BUSY
- RT5659_PDM_DATA_CTRL_1
- RT5659_PDM_DATA_CTRL_2
- RT5659_PDM_DATA_CTRL_3
- RT5659_PDM_DATA_CTRL_4
- RT5659_PDM_DIV_MASK
- RT5659_PDM_GAIN
- RT5659_PDM_OUT_CTRL
- RT5659_PDM_PATTERN
- RT5659_PLL
- RT5659_PLL1_PD_1
- RT5659_PLL1_PD_2
- RT5659_PLL1_PD_MASK
- RT5659_PLL1_PD_SFT
- RT5659_PLL1_SRC_BCLK1
- RT5659_PLL1_SRC_BCLK2
- RT5659_PLL1_SRC_BCLK3
- RT5659_PLL1_SRC_MASK
- RT5659_PLL1_SRC_MCLK
- RT5659_PLL1_SRC_SFT
- RT5659_PLL1_S_BCLK1
- RT5659_PLL1_S_BCLK2
- RT5659_PLL1_S_BCLK3
- RT5659_PLL1_S_BCLK4
- RT5659_PLL1_S_MCLK
- RT5659_PLL_CTRL_1
- RT5659_PLL_CTRL_2
- RT5659_PLL_INP_MAX
- RT5659_PLL_INP_MIN
- RT5659_PLL_K_MASK
- RT5659_PLL_K_MAX
- RT5659_PLL_K_SFT
- RT5659_PLL_M_BP
- RT5659_PLL_M_BP_SFT
- RT5659_PLL_M_MASK
- RT5659_PLL_M_MAX
- RT5659_PLL_M_SFT
- RT5659_PLL_N_MASK
- RT5659_PLL_N_MAX
- RT5659_PLL_N_SFT
- RT5659_PM_HP_HV
- RT5659_PM_HP_LV
- RT5659_PM_HP_MASK
- RT5659_PM_HP_MV
- RT5659_PM_HP_SFT
- RT5659_POW_CLSD_DB_DIS
- RT5659_POW_CLSD_DB_EN
- RT5659_POW_CLSD_DB_MASK
- RT5659_PRE_DIV_1
- RT5659_PRE_DIV_2
- RT5659_PRIV_DATA
- RT5659_PRIV_INDEX
- RT5659_PSV_CTRL
- RT5659_PSV_IL_CMD_1
- RT5659_PSV_IL_CMD_2
- RT5659_PURE_DC_DET_CTRL_1
- RT5659_PURE_DC_DET_CTRL_2
- RT5659_PVDD_DET_DIS
- RT5659_PVDD_DET_EN
- RT5659_PVDD_DET_MASK
- RT5659_PVDD_DET_SFT
- RT5659_PWR_ADC_L1
- RT5659_PWR_ADC_L1_BIT
- RT5659_PWR_ADC_L2
- RT5659_PWR_ADC_L2_BIT
- RT5659_PWR_ADC_MF_L
- RT5659_PWR_ADC_MF_L_BIT
- RT5659_PWR_ADC_MF_R
- RT5659_PWR_ADC_MF_R_BIT
- RT5659_PWR_ADC_R1
- RT5659_PWR_ADC_R1_BIT
- RT5659_PWR_ADC_R2
- RT5659_PWR_ADC_R2_BIT
- RT5659_PWR_ADC_S1F
- RT5659_PWR_ADC_S1F_BIT
- RT5659_PWR_ADC_S2F
- RT5659_PWR_ADC_S2F_BIT
- RT5659_PWR_ANLG_1
- RT5659_PWR_ANLG_2
- RT5659_PWR_ANLG_3
- RT5659_PWR_BG
- RT5659_PWR_BG_BIT
- RT5659_PWR_BST1
- RT5659_PWR_BST1_BIT
- RT5659_PWR_BST1_P
- RT5659_PWR_BST1_P_BIT
- RT5659_PWR_BST2
- RT5659_PWR_BST2_BIT
- RT5659_PWR_BST2_P
- RT5659_PWR_BST2_P_BIT
- RT5659_PWR_BST3
- RT5659_PWR_BST3_BIT
- RT5659_PWR_BST3_P
- RT5659_PWR_BST3_P_BIT
- RT5659_PWR_BST4
- RT5659_PWR_BST4_BIT
- RT5659_PWR_BST4_P
- RT5659_PWR_BST4_P_BIT
- RT5659_PWR_BST_L
- RT5659_PWR_BST_L_BIT
- RT5659_PWR_BST_R
- RT5659_PWR_BST_R_BIT
- RT5659_PWR_CLK25M_MASK
- RT5659_PWR_CLK25M_PD
- RT5659_PWR_CLK25M_PU
- RT5659_PWR_CLK25M_SFT
- RT5659_PWR_CLS_D
- RT5659_PWR_CLS_D_BIT
- RT5659_PWR_DAC_L1
- RT5659_PWR_DAC_L1_BIT
- RT5659_PWR_DAC_L2
- RT5659_PWR_DAC_L2_BIT
- RT5659_PWR_DAC_MF_L
- RT5659_PWR_DAC_MF_L_BIT
- RT5659_PWR_DAC_MF_R
- RT5659_PWR_DAC_MF_R_BIT
- RT5659_PWR_DAC_R1
- RT5659_PWR_DAC_R1_BIT
- RT5659_PWR_DAC_R2
- RT5659_PWR_DAC_R2_BIT
- RT5659_PWR_DAC_S1F
- RT5659_PWR_DAC_S1F_BIT
- RT5659_PWR_DIG_1
- RT5659_PWR_DIG_2
- RT5659_PWR_FV1
- RT5659_PWR_FV1_BIT
- RT5659_PWR_FV2
- RT5659_PWR_FV2_BIT
- RT5659_PWR_FV3
- RT5659_PWR_FV3_BIT
- RT5659_PWR_HA_L
- RT5659_PWR_HA_L_BIT
- RT5659_PWR_HA_R
- RT5659_PWR_HA_R_BIT
- RT5659_PWR_I2S1
- RT5659_PWR_I2S1_BIT
- RT5659_PWR_I2S2
- RT5659_PWR_I2S2_BIT
- RT5659_PWR_I2S3
- RT5659_PWR_I2S3_BIT
- RT5659_PWR_IN_L
- RT5659_PWR_IN_L_BIT
- RT5659_PWR_IN_R
- RT5659_PWR_IN_R_BIT
- RT5659_PWR_JD1
- RT5659_PWR_JD1_BIT
- RT5659_PWR_JD2
- RT5659_PWR_JD2_BIT
- RT5659_PWR_JD3
- RT5659_PWR_JD3_BIT
- RT5659_PWR_LDO
- RT5659_PWR_LDO2
- RT5659_PWR_LDO2_BIT
- RT5659_PWR_LDO3
- RT5659_PWR_LDO3_BIT
- RT5659_PWR_LDO4
- RT5659_PWR_LDO4_BIT
- RT5659_PWR_LDO5
- RT5659_PWR_LDO5_BIT
- RT5659_PWR_LDO_BIT
- RT5659_PWR_LM
- RT5659_PWR_LM_BIT
- RT5659_PWR_MA
- RT5659_PWR_MA_BIT
- RT5659_PWR_MB
- RT5659_PWR_MB1
- RT5659_PWR_MB1_BIT
- RT5659_PWR_MB2
- RT5659_PWR_MB2_BIT
- RT5659_PWR_MB3
- RT5659_PWR_MB3_BIT
- RT5659_PWR_MB_BIT
- RT5659_PWR_MB_MASK
- RT5659_PWR_MB_PD
- RT5659_PWR_MB_PU
- RT5659_PWR_MB_SFT
- RT5659_PWR_MIC_DET
- RT5659_PWR_MIC_DET_BIT
- RT5659_PWR_MIXER
- RT5659_PWR_MM
- RT5659_PWR_MM_BIT
- RT5659_PWR_MV
- RT5659_PWR_MV_BIT
- RT5659_PWR_OM_L
- RT5659_PWR_OM_L_BIT
- RT5659_PWR_OM_R
- RT5659_PWR_OM_R_BIT
- RT5659_PWR_OV_L
- RT5659_PWR_OV_L_BIT
- RT5659_PWR_OV_R
- RT5659_PWR_OV_R_BIT
- RT5659_PWR_PDM1
- RT5659_PWR_PDM1_BIT
- RT5659_PWR_PLL
- RT5659_PWR_PLL_BIT
- RT5659_PWR_RM1_L
- RT5659_PWR_RM1_L_BIT
- RT5659_PWR_RM1_R
- RT5659_PWR_RM1_R_BIT
- RT5659_PWR_RM2_L
- RT5659_PWR_RM2_L_BIT
- RT5659_PWR_RM2_R
- RT5659_PWR_RM2_R_BIT
- RT5659_PWR_SM_L
- RT5659_PWR_SM_L_BIT
- RT5659_PWR_SM_R
- RT5659_PWR_SM_R_BIT
- RT5659_PWR_SPDIF
- RT5659_PWR_SPDIF_BIT
- RT5659_PWR_SVD
- RT5659_PWR_SVD_BIT
- RT5659_PWR_SV_L
- RT5659_PWR_SV_L_BIT
- RT5659_PWR_SV_R
- RT5659_PWR_SV_R_BIT
- RT5659_PWR_VOL
- RT5659_PWR_VREF1
- RT5659_PWR_VREF1_BIT
- RT5659_PWR_VREF2
- RT5659_PWR_VREF2_BIT
- RT5659_PWR_VREF3
- RT5659_PWR_VREF3_BIT
- RT5659_RAMP_DIS
- RT5659_RAMP_EN
- RT5659_RAMP_MASK
- RT5659_RAMP_SFT
- RT5659_RC_CLK_CTRL
- RT5659_REC1_GAIN
- RT5659_REC1_L1_MIXER
- RT5659_REC1_L2_MIXER
- RT5659_REC1_R1_MIXER
- RT5659_REC1_R2_MIXER
- RT5659_REC2_L1_MIXER
- RT5659_REC2_L2_MIXER
- RT5659_REC2_R1_MIXER
- RT5659_REC2_R2_MIXER
- RT5659_REC_M1_M2_GAIN_CTRL
- RT5659_RESET
- RT5659_RSTN_DIS
- RT5659_RSTN_EN
- RT5659_RSTN_MASK
- RT5659_RSTN_SFT
- RT5659_RSTP_DIS
- RT5659_RSTP_EN
- RT5659_RSTP_MASK
- RT5659_RSTP_SFT
- RT5659_R_MUTE
- RT5659_R_MUTE_SFT
- RT5659_R_VOL_MASK
- RT5659_R_VOL_SFT
- RT5659_SCLK_SRC_MASK
- RT5659_SCLK_SRC_MCLK
- RT5659_SCLK_SRC_PLL1
- RT5659_SCLK_SRC_RCCLK
- RT5659_SCLK_SRC_SFT
- RT5659_SCLK_S_MCLK
- RT5659_SCLK_S_PLL1
- RT5659_SCLK_S_RCCLK
- RT5659_SIDETONE_CTRL
- RT5659_SILENCE_CTRL
- RT5659_SIL_DET_DIS
- RT5659_SIL_DET_EN
- RT5659_SIL_DET_MASK
- RT5659_SINE_GEN_CTRL_1
- RT5659_SINE_GEN_CTRL_2
- RT5659_SINE_GEN_CTRL_3
- RT5659_SMT_TRIG_DIS
- RT5659_SMT_TRIG_EN
- RT5659_SMT_TRIG_MASK
- RT5659_SMT_TRIG_SFT
- RT5659_SOFT_RAMP_DEPOP
- RT5659_SOFT_RAMP_DEPOP_DAC_CLK_CTRL
- RT5659_SPDIF_CTRL
- RT5659_SPDIF_CTRL_1
- RT5659_SPDIF_CTRL_2
- RT5659_SPDIF_SEL_MASK
- RT5659_SPDIF_SEL_SFT
- RT5659_SPK_AG_DIS
- RT5659_SPK_AG_EN
- RT5659_SPK_AG_MASK
- RT5659_SPK_AG_SFT
- RT5659_SPK_DC_CAILB_CTRL_1
- RT5659_SPK_DC_CAILB_CTRL_2
- RT5659_SPK_DC_CAILB_CTRL_3
- RT5659_SPK_DC_CAILB_CTRL_4
- RT5659_SPK_DC_CAILB_CTRL_5
- RT5659_SPK_DC_CAILB_STA_1
- RT5659_SPK_DC_CAILB_STA_10
- RT5659_SPK_DC_CAILB_STA_2
- RT5659_SPK_DC_CAILB_STA_3
- RT5659_SPK_DC_CAILB_STA_4
- RT5659_SPK_DC_CAILB_STA_5
- RT5659_SPK_DC_CAILB_STA_6
- RT5659_SPK_DC_CAILB_STA_7
- RT5659_SPK_DC_CAILB_STA_8
- RT5659_SPK_DC_CAILB_STA_9
- RT5659_SPK_DC_DET_CTRL_1
- RT5659_SPK_DC_DET_CTRL_2
- RT5659_SPK_DC_DET_CTRL_3
- RT5659_SPK_EX_LMT_CTRL_1
- RT5659_SPK_EX_LMT_CTRL_2
- RT5659_SPK_EX_LMT_CTRL_3
- RT5659_SPK_EX_LMT_CTRL_4
- RT5659_SPK_EX_LMT_CTRL_5
- RT5659_SPK_EX_LMT_CTRL_6
- RT5659_SPK_EX_LMT_CTRL_7
- RT5659_SPK_L_MIXER
- RT5659_SPK_PWR_LMT_CTRL_1
- RT5659_SPK_PWR_LMT_CTRL_2
- RT5659_SPK_PWR_LMT_CTRL_3
- RT5659_SPK_PWR_LMT_STA_1
- RT5659_SPK_PWR_LMT_STA_2
- RT5659_SPK_PWR_LMT_STA_3
- RT5659_SPK_PWR_LMT_STA_4
- RT5659_SPK_PWR_LMT_STA_5
- RT5659_SPK_PWR_LMT_STA_6
- RT5659_SPK_R_MIXER
- RT5659_SPK_VDD_STA_1
- RT5659_SPK_VDD_STA_2
- RT5659_SPO_AMP_GAIN
- RT5659_SPO_VOL
- RT5659_STEREO_RATES
- RT5659_STO1_ADC1_SRC_ADC
- RT5659_STO1_ADC1_SRC_DACMIX
- RT5659_STO1_ADC1_SRC_MASK
- RT5659_STO1_ADC1_SRC_SFT
- RT5659_STO1_ADC2_SRC_MASK
- RT5659_STO1_ADC2_SRC_SFT
- RT5659_STO1_ADC_DIG_VOL
- RT5659_STO1_ADC_L_BST_MASK
- RT5659_STO1_ADC_L_BST_SFT
- RT5659_STO1_ADC_MIXER
- RT5659_STO1_ADC_R_BST_MASK
- RT5659_STO1_ADC_R_BST_SFT
- RT5659_STO1_ADC_SRC_ADC1
- RT5659_STO1_ADC_SRC_ADC2
- RT5659_STO1_ADC_SRC_MASK
- RT5659_STO1_ADC_SRC_SFT
- RT5659_STO1_BOOST
- RT5659_STO1_DMIC_SRC_DMIC1
- RT5659_STO1_DMIC_SRC_DMIC2
- RT5659_STO1_DMIC_SRC_MASK
- RT5659_STO1_DMIC_SRC_SFT
- RT5659_STO2_ADC_DIG_VOL
- RT5659_STO2_ADC_L_BST_MASK
- RT5659_STO2_ADC_L_BST_SFT
- RT5659_STO2_ADC_R_BST_MASK
- RT5659_STO2_ADC_R_BST_SFT
- RT5659_STO2_ADC_SRC_MASK
- RT5659_STO2_ADC_SRC_SFT
- RT5659_STO2_BOOST
- RT5659_STO_DAC_MIXER
- RT5659_STO_NG2_CTRL_1
- RT5659_STO_NG2_CTRL_2
- RT5659_STO_NG2_CTRL_3
- RT5659_STO_NG2_CTRL_4
- RT5659_STO_NG2_CTRL_5
- RT5659_STO_NG2_CTRL_6
- RT5659_STO_NG2_CTRL_7
- RT5659_STO_NG2_CTRL_8
- RT5659_ST_EN
- RT5659_ST_EN_SFT
- RT5659_ST_SEL_MASK
- RT5659_ST_SEL_SFT
- RT5659_SV_DIS
- RT5659_SV_DLY_MASK
- RT5659_SV_DLY_SFT
- RT5659_SV_EN
- RT5659_SV_MASK
- RT5659_SV_SFT
- RT5659_SV_ZCD_1
- RT5659_SV_ZCD_2
- RT5659_TDM_CTRL_1
- RT5659_TDM_CTRL_2
- RT5659_TDM_CTRL_3
- RT5659_TDM_CTRL_4
- RT5659_TDM_CTRL_5
- RT5659_TEST_MODE_CTRL_1
- RT5659_TEST_MODE_CTRL_2
- RT5659_TEST_MODE_CTRL_3
- RT5659_TEST_MODE_CTRL_4
- RT5659_VENDOR_ID
- RT5659_VENDOR_ID_1
- RT5659_VLO_32V
- RT5659_VLO_3V
- RT5659_VLO_MASK
- RT5659_VLO_SFT
- RT5659_VOL_L_MUTE
- RT5659_VOL_L_SFT
- RT5659_VOL_R_MUTE
- RT5659_VOL_R_SFT
- RT5659_VOL_TEST
- RT5659_VREF_REC_OP_FB_CAP_CTRL
- RT5659_ZCD_DIG_DIS
- RT5659_ZCD_DIG_EN
- RT5659_ZCD_DIG_MASK
- RT5659_ZCD_DIG_SFT
- RT5659_ZCD_HP_DIS
- RT5659_ZCD_HP_EN
- RT5659_ZCD_HP_MASK
- RT5659_ZCD_HP_SFT
- RT5659_ZCD_MASK
- RT5659_ZCD_PD
- RT5659_ZCD_PU
- RT5659_ZCD_SFT
- RT5660_ADC_BST_VOL1
- RT5660_ADC_L_VOL_MASK
- RT5660_ADC_L_VOL_SFT
- RT5660_ADC_OSR_128
- RT5660_ADC_OSR_16
- RT5660_ADC_OSR_32
- RT5660_ADC_OSR_64
- RT5660_ADC_OSR_MASK
- RT5660_ADC_OSR_SFT
- RT5660_ADC_R_VOL_MASK
- RT5660_ADC_R_VOL_SFT
- RT5660_ADDA_CLK1
- RT5660_ADDA_CLK2
- RT5660_ADHPF_EN
- RT5660_ADHPF_EN_SFT
- RT5660_AD_DA_MIXER
- RT5660_AIF1
- RT5660_AIFS
- RT5660_ALC_PGA_CTRL1
- RT5660_ALC_PGA_CTRL2
- RT5660_ALC_PGA_CTRL3
- RT5660_ALC_PGA_CTRL4
- RT5660_ALC_PGA_CTRL5
- RT5660_ALC_PGA_CTRL6
- RT5660_ALC_PGA_CTRL7
- RT5660_AUTO_DIS_AMP
- RT5660_AUTO_PD_DIS
- RT5660_AUTO_PD_EN
- RT5660_AUTO_PD_MASK
- RT5660_AUTO_PD_SFT
- RT5660_BST_MASK1
- RT5660_BST_MASK2
- RT5660_BST_MASK3
- RT5660_BST_MASK4
- RT5660_BST_SFT1
- RT5660_BST_SFT2
- RT5660_BST_SFT3
- RT5660_BST_SFT4
- RT5660_CHOP_DAC_ADC
- RT5660_CLSD_AMP_CTRL
- RT5660_CLSD_AMP_OC_CTRL
- RT5660_CLSD_OC_MASK
- RT5660_CLSD_OC_PD
- RT5660_CLSD_OC_PU
- RT5660_CLSD_OC_SFT
- RT5660_CLSD_OC_TH_MASK
- RT5660_CLSD_OC_TH_SFT
- RT5660_CLSD_OUT_CTRL1
- RT5660_CLSD_OUT_CTRL2
- RT5660_CLSD_RATIO_MASK
- RT5660_CLSD_RATIO_SFT
- RT5660_DAC1_DIG_VOL
- RT5660_DAC_L1_STO_L_VOL_MASK
- RT5660_DAC_L1_STO_L_VOL_SFT
- RT5660_DAC_L1_STO_R_VOL_MASK
- RT5660_DAC_L1_STO_R_VOL_SFT
- RT5660_DAC_L1_VOL_MASK
- RT5660_DAC_L1_VOL_SFT
- RT5660_DAC_OSR_128
- RT5660_DAC_OSR_16
- RT5660_DAC_OSR_32
- RT5660_DAC_OSR_64
- RT5660_DAC_OSR_MASK
- RT5660_DAC_OSR_SFT
- RT5660_DAC_R1_STO_L_VOL_MASK
- RT5660_DAC_R1_STO_L_VOL_SFT
- RT5660_DAC_R1_STO_R_VOL_MASK
- RT5660_DAC_R1_STO_R_VOL_SFT
- RT5660_DAC_R1_VOL_MASK
- RT5660_DAC_R1_VOL_SFT
- RT5660_DAHPF_EN
- RT5660_DAHPF_EN_SFT
- RT5660_DEVICE_ID
- RT5660_DIG_GATE_CTRL
- RT5660_DIG_GATE_CTRL_SFT
- RT5660_DIG_INF1_DATA
- RT5660_DIPOLE_MIC_CTRL1
- RT5660_DIPOLE_MIC_CTRL10
- RT5660_DIPOLE_MIC_CTRL11
- RT5660_DIPOLE_MIC_CTRL12
- RT5660_DIPOLE_MIC_CTRL2
- RT5660_DIPOLE_MIC_CTRL3
- RT5660_DIPOLE_MIC_CTRL4
- RT5660_DIPOLE_MIC_CTRL5
- RT5660_DIPOLE_MIC_CTRL6
- RT5660_DIPOLE_MIC_CTRL7
- RT5660_DIPOLE_MIC_CTRL8
- RT5660_DIPOLE_MIC_CTRL9
- RT5660_DMIC1_DATA_GPIO2
- RT5660_DMIC1_DATA_IN1P
- RT5660_DMIC1_NULL
- RT5660_DMIC_1L_LH_FALLING
- RT5660_DMIC_1L_LH_MASK
- RT5660_DMIC_1L_LH_RISING
- RT5660_DMIC_1L_LH_SFT
- RT5660_DMIC_1R_LH_FALLING
- RT5660_DMIC_1R_LH_MASK
- RT5660_DMIC_1R_LH_RISING
- RT5660_DMIC_1R_LH_SFT
- RT5660_DMIC_1_DIS
- RT5660_DMIC_1_EN
- RT5660_DMIC_1_EN_MASK
- RT5660_DMIC_1_EN_SFT
- RT5660_DMIC_CLK_MASK
- RT5660_DMIC_CLK_SFT
- RT5660_DMIC_CTRL1
- RT5660_DRC1_LM_CTRL1
- RT5660_DRC1_LM_CTRL2
- RT5660_DRC2_CTRL1
- RT5660_DRC2_CTRL2
- RT5660_DRC2_CTRL3
- RT5660_DRC2_CTRL4
- RT5660_DRC2_CTRL5
- RT5660_DRC2_LM_CTRL1
- RT5660_DRC2_LM_CTRL2
- RT5660_DRC_AGC_CTRL1
- RT5660_DRC_AGC_CTRL2
- RT5660_DRC_AGC_CTRL3
- RT5660_DRC_AGC_CTRL4
- RT5660_DRC_AGC_CTRL5
- RT5660_EQ_CTRL1
- RT5660_EQ_CTRL2
- RT5660_EQ_SRC_ADC
- RT5660_EQ_SRC_DAC
- RT5660_EQ_SRC_MASK
- RT5660_EQ_SRC_SFT
- RT5660_EQ_UPD
- RT5660_EQ_UPD_BIT
- RT5660_FORMATS
- RT5660_GEN_CTRL1
- RT5660_GEN_CTRL2
- RT5660_GEN_CTRL3
- RT5660_GLB_CLK
- RT5660_GP1_OUT_HI
- RT5660_GP1_OUT_LO
- RT5660_GP1_OUT_MASK
- RT5660_GP1_OUT_SFT
- RT5660_GP1_PF_IN
- RT5660_GP1_PF_MASK
- RT5660_GP1_PF_OUT
- RT5660_GP1_PF_SFT
- RT5660_GP1_PIN_DMIC1_SCL
- RT5660_GP1_PIN_GPIO1
- RT5660_GP1_PIN_IRQ
- RT5660_GP1_PIN_MASK
- RT5660_GP1_PIN_SFT
- RT5660_GP1_P_INV
- RT5660_GP1_P_MASK
- RT5660_GP1_P_NOR
- RT5660_GP1_P_SFT
- RT5660_GP2_OUT_HI
- RT5660_GP2_OUT_LO
- RT5660_GP2_OUT_MASK
- RT5660_GP2_OUT_SFT
- RT5660_GP2_PF_IN
- RT5660_GP2_PF_MASK
- RT5660_GP2_PF_OUT
- RT5660_GP2_PF_SFT
- RT5660_GP2_PIN_DMIC1_SDA
- RT5660_GP2_PIN_GPIO2
- RT5660_GP2_PIN_MASK
- RT5660_GP2_PIN_SFT
- RT5660_GP2_P_INV
- RT5660_GP2_P_MASK
- RT5660_GP2_P_NOR
- RT5660_GP2_P_SFT
- RT5660_GPIO_CTRL1
- RT5660_GPIO_CTRL2
- RT5660_GPIO_M_FLT
- RT5660_GPIO_M_MASK
- RT5660_GPIO_M_PH
- RT5660_GPIO_M_SFT
- RT5660_G_BST1_OM_L_MASK
- RT5660_G_BST1_OM_L_SFT
- RT5660_G_BST1_OM_R_MASK
- RT5660_G_BST1_OM_R_SFT
- RT5660_G_BST1_RM_L_MASK
- RT5660_G_BST1_RM_L_SFT
- RT5660_G_BST1_RM_R_MASK
- RT5660_G_BST1_RM_R_SFT
- RT5660_G_BST1_SM_MASK
- RT5660_G_BST1_SM_SFT
- RT5660_G_BST2_OM_L_MASK
- RT5660_G_BST2_OM_L_SFT
- RT5660_G_BST2_OM_R_MASK
- RT5660_G_BST2_OM_R_SFT
- RT5660_G_BST2_RM_L_MASK
- RT5660_G_BST2_RM_L_SFT
- RT5660_G_BST2_RM_R_MASK
- RT5660_G_BST2_RM_R_SFT
- RT5660_G_BST3_OM_L_MASK
- RT5660_G_BST3_OM_L_SFT
- RT5660_G_BST3_RM_L_MASK
- RT5660_G_BST3_RM_L_SFT
- RT5660_G_BST3_RM_R_MASK
- RT5660_G_BST3_RM_R_SFT
- RT5660_G_BST3_SM_MASK
- RT5660_G_BST3_SM_SFT
- RT5660_G_DACR_SM_MASK
- RT5660_G_DACR_SM_SFT
- RT5660_G_DAC_L1_OM_L_MASK
- RT5660_G_DAC_L1_OM_L_SFT
- RT5660_G_DAC_L_OM_R_MASK
- RT5660_G_DAC_L_OM_R_SFT
- RT5660_G_DAC_R1_OM_L_MASK
- RT5660_G_DAC_R1_OM_L_SFT
- RT5660_G_DAC_R_OM_R_MASK
- RT5660_G_DAC_R_OM_R_SFT
- RT5660_G_DACl_SM_MASK
- RT5660_G_DACl_SM_SFT
- RT5660_G_OM_L_RM_L_MASK
- RT5660_G_OM_L_RM_L_SFT
- RT5660_G_OM_L_SM_MASK
- RT5660_G_OM_L_SM_SFT
- RT5660_G_OM_R_RM_R_MASK
- RT5660_G_OM_R_RM_R_SFT
- RT5660_G_RM_L_OM_L_MASK
- RT5660_G_RM_L_OM_L_SFT
- RT5660_G_RM_R_OM_R_MASK
- RT5660_G_RM_R_OM_R_SFT
- RT5660_I2S1_SDP
- RT5660_I2S_BCLK_MS1_32
- RT5660_I2S_BCLK_MS1_64
- RT5660_I2S_BCLK_MS1_MASK
- RT5660_I2S_BCLK_MS1_SFT
- RT5660_I2S_BP_INV
- RT5660_I2S_BP_MASK
- RT5660_I2S_BP_NOR
- RT5660_I2S_BP_SFT
- RT5660_I2S_DF_I2S
- RT5660_I2S_DF_LEFT
- RT5660_I2S_DF_MASK
- RT5660_I2S_DF_PCM_A
- RT5660_I2S_DF_PCM_B
- RT5660_I2S_DF_SFT
- RT5660_I2S_DL_16
- RT5660_I2S_DL_20
- RT5660_I2S_DL_24
- RT5660_I2S_DL_8
- RT5660_I2S_DL_MASK
- RT5660_I2S_DL_SFT
- RT5660_I2S_I_CP_A_LAW
- RT5660_I2S_I_CP_MASK
- RT5660_I2S_I_CP_OFF
- RT5660_I2S_I_CP_SFT
- RT5660_I2S_I_CP_U_LAW
- RT5660_I2S_MS_M
- RT5660_I2S_MS_MASK
- RT5660_I2S_MS_S
- RT5660_I2S_MS_SFT
- RT5660_I2S_O_CP_A_LAW
- RT5660_I2S_O_CP_MASK
- RT5660_I2S_O_CP_OFF
- RT5660_I2S_O_CP_SFT
- RT5660_I2S_O_CP_U_LAW
- RT5660_I2S_PD1_1
- RT5660_I2S_PD1_12
- RT5660_I2S_PD1_16
- RT5660_I2S_PD1_2
- RT5660_I2S_PD1_3
- RT5660_I2S_PD1_4
- RT5660_I2S_PD1_6
- RT5660_I2S_PD1_8
- RT5660_I2S_PD1_MASK
- RT5660_I2S_PD1_SFT
- RT5660_IF1_ADC_IN_SEL
- RT5660_IF1_ADC_IN_SFT
- RT5660_IF1_DAC_IN_SEL
- RT5660_IF1_DAC_IN_SFT
- RT5660_IN1_IN2
- RT5660_IN3_IN4
- RT5660_INT_IRQ_ST
- RT5660_IN_DF1
- RT5660_IN_DF2
- RT5660_IN_DF3
- RT5660_IN_DF4
- RT5660_IN_SFT1
- RT5660_IN_SFT2
- RT5660_IN_SFT3
- RT5660_IN_SFT4
- RT5660_IRQ_CTRL1
- RT5660_IRQ_CTRL2
- RT5660_IRQ_JD_BP
- RT5660_IRQ_JD_MASK
- RT5660_IRQ_JD_NOR
- RT5660_IRQ_JD_SFT
- RT5660_IRQ_MB1_OC_BP
- RT5660_IRQ_MB1_OC_MASK
- RT5660_IRQ_MB1_OC_NOR
- RT5660_IRQ_MB1_OC_SFT
- RT5660_IRQ_MB2_OC_BP
- RT5660_IRQ_MB2_OC_MASK
- RT5660_IRQ_MB2_OC_NOR
- RT5660_IRQ_MB2_OC_SFT
- RT5660_IRQ_OT_BP
- RT5660_IRQ_OT_MASK
- RT5660_IRQ_OT_NOR
- RT5660_IRQ_OT_SFT
- RT5660_JD_CTRL
- RT5660_JD_DIS
- RT5660_JD_GPIO1
- RT5660_JD_GPIO2
- RT5660_JD_LOUT_DIS
- RT5660_JD_LOUT_EN
- RT5660_JD_LOUT_MASK
- RT5660_JD_LOUT_SFT
- RT5660_JD_LOUT_TRG_HI
- RT5660_JD_LOUT_TRG_LO
- RT5660_JD_LOUT_TRG_MASK
- RT5660_JD_LOUT_TRG_SFT
- RT5660_JD_MASK
- RT5660_JD_P_INV
- RT5660_JD_P_MASK
- RT5660_JD_P_NOR
- RT5660_JD_P_SFT
- RT5660_JD_SFT
- RT5660_JD_SPO_DIS
- RT5660_JD_SPO_EN
- RT5660_JD_SPO_MASK
- RT5660_JD_SPO_SFT
- RT5660_JD_SPO_TRG_HI
- RT5660_JD_SPO_TRG_LO
- RT5660_JD_SPO_TRG_MASK
- RT5660_JD_SPO_TRG_SFT
- RT5660_JD_STKY_DIS
- RT5660_JD_STKY_EN
- RT5660_JD_STKY_MASK
- RT5660_JD_STKY_SFT
- RT5660_LOUT_AMP_CTRL
- RT5660_LOUT_CB_MASK
- RT5660_LOUT_CB_PD
- RT5660_LOUT_CB_PU
- RT5660_LOUT_CB_SFT
- RT5660_LOUT_CO_DIS
- RT5660_LOUT_CO_EN
- RT5660_LOUT_CO_MASK
- RT5660_LOUT_CO_SFT
- RT5660_LOUT_MIXER
- RT5660_LOUT_VOL
- RT5660_L_MUTE
- RT5660_L_MUTE_SFT
- RT5660_L_VOL_MASK
- RT5660_L_VOL_SFT
- RT5660_MB1_OC_CLR
- RT5660_MB1_OC_CLR_SFT
- RT5660_MB1_OC_P_INV
- RT5660_MB1_OC_P_MASK
- RT5660_MB1_OC_P_NOR
- RT5660_MB1_OC_P_SFT
- RT5660_MB1_OC_STKY_DIS
- RT5660_MB1_OC_STKY_EN
- RT5660_MB1_OC_STKY_MASK
- RT5660_MB1_OC_STKY_SFT
- RT5660_MB2_OC_CLR
- RT5660_MB2_OC_CLR_SFT
- RT5660_MB2_OC_P_INV
- RT5660_MB2_OC_P_MASK
- RT5660_MB2_OC_P_NOR
- RT5660_MB2_OC_P_SFT
- RT5660_MB2_OC_STKY_DIS
- RT5660_MB2_OC_STKY_EN
- RT5660_MB2_OC_STKY_MASK
- RT5660_MB2_OC_STKY_SFT
- RT5660_MCLK_DET
- RT5660_MIC1_BS_75AV
- RT5660_MIC1_BS_9AV
- RT5660_MIC1_BS_MASK
- RT5660_MIC1_BS_SFT
- RT5660_MIC1_OVCD_DIS
- RT5660_MIC1_OVCD_EN
- RT5660_MIC1_OVCD_MASK
- RT5660_MIC1_OVCD_SFT
- RT5660_MIC1_OVTH_1500UA
- RT5660_MIC1_OVTH_2000UA
- RT5660_MIC1_OVTH_600UA
- RT5660_MIC1_OVTH_MASK
- RT5660_MIC1_OVTH_SFT
- RT5660_MIC2_BS_75AV
- RT5660_MIC2_BS_9AV
- RT5660_MIC2_BS_MASK
- RT5660_MIC2_BS_SFT
- RT5660_MIC2_OVCD_DIS
- RT5660_MIC2_OVCD_EN
- RT5660_MIC2_OVCD_MASK
- RT5660_MIC2_OVCD_SFT
- RT5660_MIC2_OVTH_1500UA
- RT5660_MIC2_OVTH_2000UA
- RT5660_MIC2_OVTH_600UA
- RT5660_MIC2_OVTH_MASK
- RT5660_MIC2_OVTH_SFT
- RT5660_MICBIAS
- RT5660_MULTI_DRC_CTRL
- RT5660_M_ADCMIX_L
- RT5660_M_ADCMIX_L_SFT
- RT5660_M_ADCMIX_R
- RT5660_M_ADCMIX_R_SFT
- RT5660_M_ADC_L1
- RT5660_M_ADC_L1_SFT
- RT5660_M_ADC_L2
- RT5660_M_ADC_L2_SFT
- RT5660_M_ADC_R1
- RT5660_M_ADC_R1_SFT
- RT5660_M_ADC_R2
- RT5660_M_ADC_R2_SFT
- RT5660_M_BST1_OM_L
- RT5660_M_BST1_OM_L_SFT
- RT5660_M_BST1_OM_R
- RT5660_M_BST1_OM_R_SFT
- RT5660_M_BST1_RM_L
- RT5660_M_BST1_RM_L_SFT
- RT5660_M_BST1_RM_R
- RT5660_M_BST1_RM_R_SFT
- RT5660_M_BST1_SM
- RT5660_M_BST1_SM_SFT
- RT5660_M_BST1_SPM
- RT5660_M_BST1_SPM_SFT
- RT5660_M_BST2_OM_L
- RT5660_M_BST2_OM_L_SFT
- RT5660_M_BST2_OM_R
- RT5660_M_BST2_OM_R_SFT
- RT5660_M_BST2_RM_L
- RT5660_M_BST2_RM_L_SFT
- RT5660_M_BST2_RM_R
- RT5660_M_BST2_RM_R_SFT
- RT5660_M_BST3_OM_L
- RT5660_M_BST3_OM_L_SFT
- RT5660_M_BST3_RM_L
- RT5660_M_BST3_RM_L_SFT
- RT5660_M_BST3_RM_R
- RT5660_M_BST3_RM_R_SFT
- RT5660_M_BST3_SM
- RT5660_M_BST3_SM_SFT
- RT5660_M_DAC1_L
- RT5660_M_DAC1_LM
- RT5660_M_DAC1_LM_SFT
- RT5660_M_DAC1_L_SFT
- RT5660_M_DAC1_R
- RT5660_M_DAC1_R_SFT
- RT5660_M_DACL_SM
- RT5660_M_DACL_SM_SFT
- RT5660_M_DACR_SM
- RT5660_M_DACR_SM_SFT
- RT5660_M_DAC_L1
- RT5660_M_DAC_L1_SFT
- RT5660_M_DAC_L1_STO_R
- RT5660_M_DAC_L1_STO_R_SFT
- RT5660_M_DAC_L_OM_L
- RT5660_M_DAC_L_OM_L_SFT
- RT5660_M_DAC_L_OM_R
- RT5660_M_DAC_L_OM_R_SFT
- RT5660_M_DAC_L_SPM
- RT5660_M_DAC_L_SPM_SFT
- RT5660_M_DAC_R1
- RT5660_M_DAC_R1_SFT
- RT5660_M_DAC_R1_STO_L
- RT5660_M_DAC_R1_STO_L_SFT
- RT5660_M_DAC_R_OM_L
- RT5660_M_DAC_R_OM_L_SFT
- RT5660_M_DAC_R_OM_R
- RT5660_M_DAC_R_OM_R_SFT
- RT5660_M_DAC_R_SPM
- RT5660_M_DAC_R_SPM_SFT
- RT5660_M_LOVOL_LM_SFT
- RT5660_M_LOVOL_M
- RT5660_M_OM_L_RM_L
- RT5660_M_OM_L_RM_L_SFT
- RT5660_M_OM_L_SM
- RT5660_M_OM_L_SM_SFT
- RT5660_M_OM_R_RM_R
- RT5660_M_OM_R_RM_R_SFT
- RT5660_M_RM_L_OM_L
- RT5660_M_RM_L_OM_L_SFT
- RT5660_M_RM_R_OM_R
- RT5660_M_RM_R_OM_R_SFT
- RT5660_M_SV_SPM
- RT5660_M_SV_SPM_SFT
- RT5660_OT_P_INV
- RT5660_OT_P_MASK
- RT5660_OT_P_NOR
- RT5660_OT_P_SFT
- RT5660_OT_STKY_DIS
- RT5660_OT_STKY_EN
- RT5660_OT_STKY_MASK
- RT5660_OT_STKY_SFT
- RT5660_OUT_L1_MIXER
- RT5660_OUT_L_GAIN1
- RT5660_OUT_L_GAIN2
- RT5660_OUT_R1_MIXER
- RT5660_OUT_R_GAIN1
- RT5660_OUT_R_GAIN2
- RT5660_OUT_SV_DIS
- RT5660_OUT_SV_EN
- RT5660_OUT_SV_MASK
- RT5660_OUT_SV_SFT
- RT5660_PLL1_PD_1
- RT5660_PLL1_PD_2
- RT5660_PLL1_PD_MASK
- RT5660_PLL1_PD_SFT
- RT5660_PLL1_SRC_BCLK1
- RT5660_PLL1_SRC_MASK
- RT5660_PLL1_SRC_MCLK
- RT5660_PLL1_SRC_RCCLK
- RT5660_PLL1_SRC_SFT
- RT5660_PLL1_S_BCLK
- RT5660_PLL1_S_MCLK
- RT5660_PLL_CTRL1
- RT5660_PLL_CTRL2
- RT5660_PLL_INP_MAX
- RT5660_PLL_INP_MIN
- RT5660_PLL_K_MASK
- RT5660_PLL_K_MAX
- RT5660_PLL_K_SFT
- RT5660_PLL_M_BP
- RT5660_PLL_M_BP_SFT
- RT5660_PLL_M_MASK
- RT5660_PLL_M_MAX
- RT5660_PLL_M_SFT
- RT5660_PLL_N_MASK
- RT5660_PLL_N_MAX
- RT5660_PLL_N_SFT
- RT5660_POW_CLKDET
- RT5660_PRIV_DATA
- RT5660_PRIV_INDEX
- RT5660_PR_BASE
- RT5660_PR_RANGE_BASE
- RT5660_PR_SPACING
- RT5660_PWR_ADC_L
- RT5660_PWR_ADC_L_BIT
- RT5660_PWR_ADC_R
- RT5660_PWR_ADC_R_BIT
- RT5660_PWR_ADC_S1F
- RT5660_PWR_ADC_S1F_BIT
- RT5660_PWR_ANLG1
- RT5660_PWR_ANLG2
- RT5660_PWR_BG
- RT5660_PWR_BG_BIT
- RT5660_PWR_BST1
- RT5660_PWR_BST1_BIT
- RT5660_PWR_BST2
- RT5660_PWR_BST2_BIT
- RT5660_PWR_BST3
- RT5660_PWR_BST3_BIT
- RT5660_PWR_CLK25M_MASK
- RT5660_PWR_CLK25M_PD
- RT5660_PWR_CLK25M_PU
- RT5660_PWR_CLK25M_SFT
- RT5660_PWR_CLS_D
- RT5660_PWR_CLS_D_BIT
- RT5660_PWR_DAC_L1
- RT5660_PWR_DAC_L1_BIT
- RT5660_PWR_DAC_R1
- RT5660_PWR_DAC_R1_BIT
- RT5660_PWR_DAC_S1F
- RT5660_PWR_DAC_S1F_BIT
- RT5660_PWR_DIG1
- RT5660_PWR_DIG2
- RT5660_PWR_FV1
- RT5660_PWR_FV1_BIT
- RT5660_PWR_FV2
- RT5660_PWR_FV2_BIT
- RT5660_PWR_HA
- RT5660_PWR_HA_BIT
- RT5660_PWR_HP_L
- RT5660_PWR_HP_L_BIT
- RT5660_PWR_HP_R
- RT5660_PWR_HP_R_BIT
- RT5660_PWR_I2S1
- RT5660_PWR_I2S1_BIT
- RT5660_PWR_LDO2
- RT5660_PWR_LDO2_BIT
- RT5660_PWR_LV_L
- RT5660_PWR_LV_L_BIT
- RT5660_PWR_LV_R
- RT5660_PWR_LV_R_BIT
- RT5660_PWR_MB
- RT5660_PWR_MB1
- RT5660_PWR_MB1_BIT
- RT5660_PWR_MB2
- RT5660_PWR_MB2_BIT
- RT5660_PWR_MB_BIT
- RT5660_PWR_MIXER
- RT5660_PWR_OM_L
- RT5660_PWR_OM_L_BIT
- RT5660_PWR_OM_R
- RT5660_PWR_OM_R_BIT
- RT5660_PWR_PLL
- RT5660_PWR_PLL_BIT
- RT5660_PWR_RM_L
- RT5660_PWR_RM_L_BIT
- RT5660_PWR_RM_R
- RT5660_PWR_RM_R_BIT
- RT5660_PWR_SM
- RT5660_PWR_SM_BIT
- RT5660_PWR_SV
- RT5660_PWR_SV_BIT
- RT5660_PWR_VOL
- RT5660_PWR_VREF1
- RT5660_PWR_VREF1_BIT
- RT5660_PWR_VREF2
- RT5660_PWR_VREF2_BIT
- RT5660_PWR_VREF_HP
- RT5660_PWR_VREF_HP_SFT
- RT5660_REC_L1_MIXER
- RT5660_REC_L2_MIXER
- RT5660_REC_R1_MIXER
- RT5660_REC_R2_MIXER
- RT5660_RESET
- RT5660_RESET_ADF
- RT5660_RESET_ADF_SFT
- RT5660_RESET_DAF
- RT5660_RESET_DAF_SFT
- RT5660_R_MUTE
- RT5660_R_MUTE_SFT
- RT5660_R_VOL_MASK
- RT5660_R_VOL_SFT
- RT5660_SCLK_SRC_MASK
- RT5660_SCLK_SRC_MCLK
- RT5660_SCLK_SRC_PLL1
- RT5660_SCLK_SRC_RCCLK
- RT5660_SCLK_SRC_SFT
- RT5660_SCLK_S_MCLK
- RT5660_SCLK_S_PLL1
- RT5660_SCLK_S_RCCLK
- RT5660_SEL_DMIC_DATA_GPIO2
- RT5660_SEL_DMIC_DATA_IN1P
- RT5660_SEL_DMIC_DATA_MASK
- RT5660_SEL_DMIC_DATA_SFT
- RT5660_SPKVDD_DET_DIS
- RT5660_SPKVDD_DET_EN
- RT5660_SPKVDD_DET_MASK
- RT5660_SPKVDD_DET_SFT
- RT5660_SPK_AG_DIS
- RT5660_SPK_AG_EN
- RT5660_SPK_AG_MASK
- RT5660_SPK_AG_SFT
- RT5660_SPK_AMP_SPKVDD
- RT5660_SPK_MIXER
- RT5660_SPK_VOL
- RT5660_SPO_CLSD_RATIO
- RT5660_SPO_MIXER
- RT5660_SPO_SV_DIS
- RT5660_SPO_SV_EN
- RT5660_SPO_SV_MASK
- RT5660_SPO_SV_SFT
- RT5660_STEREO_RATES
- RT5660_STO1_ADC_DIG_VOL
- RT5660_STO1_ADC_L_BST_MASK
- RT5660_STO1_ADC_L_BST_SFT
- RT5660_STO1_ADC_MIXER
- RT5660_STO1_ADC_R_BST_MASK
- RT5660_STO1_ADC_R_BST_SFT
- RT5660_STO_DAC_MIXER
- RT5660_SV_DIS
- RT5660_SV_DLY_MASK
- RT5660_SV_DLY_SFT
- RT5660_SV_EN
- RT5660_SV_MASK
- RT5660_SV_SFT
- RT5660_SV_ZCD1
- RT5660_SV_ZCD2
- RT5660_VENDOR_ID
- RT5660_VENDOR_ID1
- RT5660_VENDOR_ID2
- RT5660_VOL_L_MUTE
- RT5660_VOL_L_SFT
- RT5660_VOL_R_MUTE
- RT5660_VOL_R_SFT
- RT5660_WIND_FILTER_CTRL1
- RT5660_ZCD_DIG_DIS
- RT5660_ZCD_DIG_EN
- RT5660_ZCD_DIG_MASK
- RT5660_ZCD_DIG_SFT
- RT5660_ZCD_MASK
- RT5660_ZCD_OML_DIS
- RT5660_ZCD_OML_EN
- RT5660_ZCD_OML_MASK
- RT5660_ZCD_OML_SFT
- RT5660_ZCD_OMR_DIS
- RT5660_ZCD_OMR_EN
- RT5660_ZCD_OMR_MASK
- RT5660_ZCD_OMR_SFT
- RT5660_ZCD_PD
- RT5660_ZCD_PU
- RT5660_ZCD_RML_DIS
- RT5660_ZCD_RML_EN
- RT5660_ZCD_RML_MASK
- RT5660_ZCD_RML_SFT
- RT5660_ZCD_RMR_DIS
- RT5660_ZCD_RMR_EN
- RT5660_ZCD_RMR_MASK
- RT5660_ZCD_RMR_SFT
- RT5660_ZCD_SFT
- RT5660_ZCD_SPM_DIS
- RT5660_ZCD_SPM_EN
- RT5660_ZCD_SPM_MASK
- RT5660_ZCD_SPM_SFT
- RT5660_ZCD_SPO_DIS
- RT5660_ZCD_SPO_EN
- RT5660_ZCD_SPO_MASK
- RT5660_ZCD_SPO_SFT
- RT5663_4BTN_CLK_DEB_16MS
- RT5663_4BTN_CLK_DEB_32MS
- RT5663_4BTN_CLK_DEB_65MS
- RT5663_4BTN_CLK_DEB_8MS
- RT5663_4BTN_CLK_DEB_MASK
- RT5663_4BTN_CLK_DEB_SHIFT
- RT5663_ADCDAC_RST
- RT5663_ADC_EQ_1
- RT5663_ADC_EQ_2
- RT5663_ADC_EQ_POST_VOL_L
- RT5663_ADC_EQ_POST_VOL_R
- RT5663_ADC_EQ_PRE_VOL_L
- RT5663_ADC_EQ_PRE_VOL_R
- RT5663_ADC_EQ_RECOV_1
- RT5663_ADC_EQ_RECOV_10
- RT5663_ADC_EQ_RECOV_11
- RT5663_ADC_EQ_RECOV_12
- RT5663_ADC_EQ_RECOV_13
- RT5663_ADC_EQ_RECOV_2
- RT5663_ADC_EQ_RECOV_3
- RT5663_ADC_EQ_RECOV_4
- RT5663_ADC_EQ_RECOV_5
- RT5663_ADC_EQ_RECOV_6
- RT5663_ADC_EQ_RECOV_7
- RT5663_ADC_EQ_RECOV_8
- RT5663_ADC_EQ_RECOV_9
- RT5663_ADC_LCH_BPF1_A1
- RT5663_ADC_LCH_BPF1_A2
- RT5663_ADC_LCH_BPF1_H0
- RT5663_ADC_LCH_BPF2_A1
- RT5663_ADC_LCH_BPF2_A2
- RT5663_ADC_LCH_BPF2_H0
- RT5663_ADC_LCH_BPF3_A1
- RT5663_ADC_LCH_BPF3_A2
- RT5663_ADC_LCH_BPF3_H0
- RT5663_ADC_LCH_BPF4_A1
- RT5663_ADC_LCH_BPF4_A2
- RT5663_ADC_LCH_BPF4_H0
- RT5663_ADC_LCH_HPF1_A1
- RT5663_ADC_LCH_HPF1_H0
- RT5663_ADC_LCH_LPF1_A1
- RT5663_ADC_LCH_LPF1_H0
- RT5663_ADC_L_MUTE_MASK
- RT5663_ADC_L_MUTE_SHIFT
- RT5663_ADC_L_VOL_MASK
- RT5663_ADC_L_VOL_SHIFT
- RT5663_ADC_OSR_128
- RT5663_ADC_OSR_32
- RT5663_ADC_OSR_64
- RT5663_ADC_OSR_MASK
- RT5663_ADC_OSR_SHIFT
- RT5663_ADC_RCH_BPF1_A1
- RT5663_ADC_RCH_BPF1_A2
- RT5663_ADC_RCH_BPF1_H0
- RT5663_ADC_RCH_BPF2_A1
- RT5663_ADC_RCH_BPF2_A2
- RT5663_ADC_RCH_BPF2_H0
- RT5663_ADC_RCH_BPF3_A1
- RT5663_ADC_RCH_BPF3_A2
- RT5663_ADC_RCH_BPF3_H0
- RT5663_ADC_RCH_BPF4_A1
- RT5663_ADC_RCH_BPF4_A2
- RT5663_ADC_RCH_BPF4_H0
- RT5663_ADC_RCH_HPF1_A1
- RT5663_ADC_RCH_HPF1_H0
- RT5663_ADC_RCH_LPF1_A1
- RT5663_ADC_RCH_LPF1_H0
- RT5663_ADC_R_MUTE_MASK
- RT5663_ADC_R_MUTE_SHIFT
- RT5663_ADC_R_VOL_MASK
- RT5663_ADC_R_VOL_SHIFT
- RT5663_ADC_STO1_ASRC_MASK
- RT5663_ADC_STO1_ASRC_SHIFT
- RT5663_ADC_STO2_ADJ1
- RT5663_ADC_STO2_ADJ2
- RT5663_ADDA_CLK_1
- RT5663_ADDA_RST
- RT5663_AD_DA_MIXER
- RT5663_AD_STEREO_FILTER
- RT5663_AD_STO1_TRACK_I2S1
- RT5663_AD_STO1_TRACK_MASK
- RT5663_AD_STO1_TRACK_SHIFT
- RT5663_AD_STO1_TRACK_SYSCLK
- RT5663_AEC_BST
- RT5663_AIF
- RT5663_AIFS
- RT5663_ALC_BK_GAIN
- RT5663_ALC_PGA_CTL_1
- RT5663_ALC_PGA_CTL_2
- RT5663_ALC_PGA_CTL_3
- RT5663_ALC_PGA_CTL_4
- RT5663_ALC_PGA_CTL_5
- RT5663_ALC_PGA_CTL_6
- RT5663_ALC_PGA_CTL_7
- RT5663_ALC_PGA_CTL_8
- RT5663_ALC_PGA_REG_1
- RT5663_ALC_PGA_REG_2
- RT5663_ALC_PGA_REG_3
- RT5663_AMP_HP_1X
- RT5663_AMP_HP_3X
- RT5663_AMP_HP_5X
- RT5663_AMP_HP_MASK
- RT5663_AMP_HP_SHIFT
- RT5663_ANA_BIAS_CUR_1
- RT5663_ANA_BIAS_CUR_2
- RT5663_ANA_BIAS_CUR_3
- RT5663_ANA_BIAS_CUR_4
- RT5663_ANA_BIAS_CUR_5
- RT5663_ANA_BIAS_CUR_6
- RT5663_ANA_JD
- RT5663_ASRC_1
- RT5663_ASRC_11
- RT5663_ASRC_11_2
- RT5663_ASRC_2
- RT5663_ASRC_3
- RT5663_ASRC_4
- RT5663_ASRC_6
- RT5663_ASRC_7
- RT5663_ASRC_8
- RT5663_ASRC_9
- RT5663_AUTO_1MRC_CLK
- RT5663_A_JD_CTRL
- RT5663_BIAS_CUR_5
- RT5663_BIAS_CUR_6
- RT5663_BIAS_CUR_7
- RT5663_BIAS_CUR_8
- RT5663_BIAS_CUR_9
- RT5663_BYPASS_STO_DAC
- RT5663_CALIB_ADC
- RT5663_CALIB_BST
- RT5663_CALIB_REC_LR
- RT5663_CALIB_REC_MIX
- RT5663_CBJ_1
- RT5663_CBJ_2
- RT5663_CBJ_3
- RT5663_CBJ_DET_DIS
- RT5663_CBJ_DET_EN
- RT5663_CBJ_DET_MASK
- RT5663_CBJ_DET_SHIFT
- RT5663_CBJ_SENSE_BST1_L
- RT5663_CBJ_SENSE_BST1_MASK
- RT5663_CBJ_SENSE_BST1_R
- RT5663_CBJ_SENSE_BST1_SHIFT
- RT5663_CBJ_TYPE_2
- RT5663_CBJ_TYPE_3
- RT5663_CBJ_TYPE_4
- RT5663_CBJ_TYPE_5
- RT5663_CBJ_TYPE_8
- RT5663_CHARGE_PUMP_1
- RT5663_CHARGE_PUMP_1_2
- RT5663_CHARGE_PUMP_1_3
- RT5663_CHARGE_PUMP_2
- RT5663_CHOP_ADC
- RT5663_CHOP_DAC_L
- RT5663_CHOP_DAC_R
- RT5663_CKGEN_ADCC_MASK
- RT5663_CKGEN_ADCC_SHIFT
- RT5663_CKGEN_DAC1_MASK
- RT5663_CKGEN_DAC1_SHIFT
- RT5663_CKXEN_ADCC_MASK
- RT5663_CKXEN_ADCC_SHIFT
- RT5663_CKXEN_DAC1_MASK
- RT5663_CKXEN_DAC1_SHIFT
- RT5663_CLK_SEL_I2S1_ASRC
- RT5663_CLK_SEL_SYS
- RT5663_CLK_SRC_DIV
- RT5663_CLK_SRC_MASK
- RT5663_CLK_SRC_MCLK
- RT5663_CLK_SRC_PLL_OUT
- RT5663_CLK_SRC_RC
- RT5663_DAC2_SRC_CTRL
- RT5663_DAC3_CTRL
- RT5663_DAC3_DIG_VOL
- RT5663_DACADC_DIG_VOL2
- RT5663_DACL1_SRC_MASK
- RT5663_DACL1_SRC_SHIFT
- RT5663_DACR1_SRC_MASK
- RT5663_DACR1_SRC_SHIFT
- RT5663_DACREF_LDO
- RT5663_DAC_L1_VOL_MASK
- RT5663_DAC_L1_VOL_SHIFT
- RT5663_DAC_OSR_128
- RT5663_DAC_OSR_32
- RT5663_DAC_OSR_64
- RT5663_DAC_OSR_MASK
- RT5663_DAC_OSR_SHIFT
- RT5663_DAC_R1_VOL_MASK
- RT5663_DAC_R1_VOL_SHIFT
- RT5663_DAC_STO1_ASRC_MASK
- RT5663_DAC_STO1_ASRC_SHIFT
- RT5663_DATA_SWAP_ADCDAT1_LL
- RT5663_DATA_SWAP_ADCDAT1_LR
- RT5663_DATA_SWAP_ADCDAT1_MASK
- RT5663_DATA_SWAP_ADCDAT1_RL
- RT5663_DATA_SWAP_ADCDAT1_RR
- RT5663_DATA_SWAP_ADCDAT1_SHIFT
- RT5663_DA_STEREO_FILTER
- RT5663_DA_STO1_TRACK_I2S1
- RT5663_DA_STO1_TRACK_MASK
- RT5663_DA_STO1_TRACK_SHIFT
- RT5663_DA_STO1_TRACK_SYSCLK
- RT5663_DEPOP_1
- RT5663_DEPOP_2
- RT5663_DEPOP_3
- RT5663_DET_TYPE_MASK
- RT5663_DET_TYPE_QFN
- RT5663_DET_TYPE_SHIFT
- RT5663_DET_TYPE_WLCSP
- RT5663_DEVICE_ID_1
- RT5663_DEVICE_ID_2
- RT5663_DEV_NAME
- RT5663_DIG_1M_CLK_DIS
- RT5663_DIG_1M_CLK_EN
- RT5663_DIG_1M_CLK_MASK
- RT5663_DIG_1M_CLK_SHIFT
- RT5663_DIG_25M_CLK_DIS
- RT5663_DIG_25M_CLK_EN
- RT5663_DIG_25M_CLK_MASK
- RT5663_DIG_25M_CLK_SHIFT
- RT5663_DIG_GATE_CTRL_DIS
- RT5663_DIG_GATE_CTRL_EN
- RT5663_DIG_GATE_CTRL_MASK
- RT5663_DIG_GATE_CTRL_SHIFT
- RT5663_DIG_IN_PIN1
- RT5663_DIG_IN_PIN2
- RT5663_DIG_MISC
- RT5663_DIG_SIDE_MIXER
- RT5663_DIG_VOL_ZCD
- RT5663_DRC1_CTRL_2
- RT5663_DRC1_CTRL_3
- RT5663_DRC1_CTRL_4
- RT5663_DRC1_CTRL_5
- RT5663_DRC1_CTRL_6
- RT5663_DRC1_HD_CTRL_1
- RT5663_DRC1_HD_CTRL_2
- RT5663_DRC1_PRI_REG_1
- RT5663_DRC1_PRI_REG_2
- RT5663_DRC1_PRI_REG_3
- RT5663_DRC1_PRI_REG_4
- RT5663_DRC1_PRI_REG_5
- RT5663_DRC1_PRI_REG_6
- RT5663_DRC1_PRI_REG_7
- RT5663_DRC1_PRI_REG_8
- RT5663_DRC_CTRL_1
- RT5663_DRE_GAIN_HP_MASK
- RT5663_DRE_GAIN_HP_SHIFT
- RT5663_DUMMY_1
- RT5663_DUMMY_2
- RT5663_DUMMY_3
- RT5663_DUMMY_BIAS_0_5
- RT5663_DUMMY_BIAS_1
- RT5663_DUMMY_BIAS_2
- RT5663_DUMMY_BIAS_3
- RT5663_DUMMY_BIAS_4_1
- RT5663_DUMMY_BIAS_4_2
- RT5663_DUMMY_BIAS_6
- RT5663_DUMMY_BIAS_8
- RT5663_DUMMY_BIAS_MASK
- RT5663_DUMMY_BIAS_SHIFT
- RT5663_DUMMY_CTL_DACLR
- RT5663_DUMMY_REG
- RT5663_DUMMY_REG_2
- RT5663_DUMMY_REG_3
- RT5663_DUMMY_REG_4
- RT5663_DUMMY_REG_5
- RT5663_DUMMY_REG_6
- RT5663_DUM_REG_2
- RT5663_DUM_REG_3
- RT5663_EMB_CLK_DIS
- RT5663_EMB_CLK_EN
- RT5663_EMB_CLK_MASK
- RT5663_EMB_CLK_SHIFT
- RT5663_EM_JACK_TYPE_1
- RT5663_EM_JACK_TYPE_2
- RT5663_EM_JACK_TYPE_3
- RT5663_EM_JACK_TYPE_4
- RT5663_EM_JACK_TYPE_5
- RT5663_EM_JACK_TYPE_6
- RT5663_EM_JD_MASK
- RT5663_EM_JD_NOR
- RT5663_EM_JD_RST
- RT5663_EM_JD_SHIFT
- RT5663_EN_4BTN_INL_DIS
- RT5663_EN_4BTN_INL_EN
- RT5663_EN_4BTN_INL_MASK
- RT5663_EN_4BTN_INL_SHIFT
- RT5663_EN_ANA_CLK_DET_AUTO
- RT5663_EN_ANA_CLK_DET_DIS
- RT5663_EN_ANA_CLK_DET_MASK
- RT5663_EN_ANA_CLK_DET_SHIFT
- RT5663_EN_CB_JD_DIS
- RT5663_EN_CB_JD_EN
- RT5663_EN_CB_JD_MASK
- RT5663_EN_CB_JD_SHIFT
- RT5663_EN_DAC_HPO_DIS
- RT5663_EN_DAC_HPO_EN
- RT5663_EN_DAC_HPO_MASK
- RT5663_EN_DAC_HPO_SHIFT
- RT5663_EN_IRQ_INLINE_BYP
- RT5663_EN_IRQ_INLINE_MASK
- RT5663_EN_IRQ_INLINE_NOR
- RT5663_EN_IRQ_INLINE_SHIFT
- RT5663_EN_IRQ_JD1_DIS
- RT5663_EN_IRQ_JD1_EN
- RT5663_EN_IRQ_JD1_MASK
- RT5663_EN_IRQ_JD1_SHIFT
- RT5663_EXT_JD_DIS
- RT5663_EXT_JD_EN
- RT5663_EXT_JD_MASK
- RT5663_EXT_JD_SHIFT
- RT5663_FAST_OFF_MICBIAS
- RT5663_FDIV_I2S34_M_CLK
- RT5663_FDIV_I2S34_M_CLK2
- RT5663_FDIV_I2S5_M_CLK
- RT5663_FDIV_I2S5_M_CLK2
- RT5663_FORMATS
- RT5663_FRAC_DIV_1
- RT5663_FRAC_DIV_2
- RT5663_GAIN_BST1_MASK
- RT5663_GAIN_BST1_SHIFT
- RT5663_GAIN_CBJ_MASK
- RT5663_GAIN_CBJ_SHIFT
- RT5663_GAIN_HP
- RT5663_GAIN_HP_SHIFT
- RT5663_GLB_CLK
- RT5663_GP1_PIN_CONF_INPUT
- RT5663_GP1_PIN_CONF_MASK
- RT5663_GP1_PIN_CONF_OUTPUT
- RT5663_GP1_PIN_CONF_SHIFT
- RT5663_GP1_PIN_GPIO1
- RT5663_GP1_PIN_IRQ
- RT5663_GP1_PIN_MASK
- RT5663_GP1_PIN_SHIFT
- RT5663_GP4_PIN_CONF_INPUT
- RT5663_GP4_PIN_CONF_MASK
- RT5663_GP4_PIN_CONF_OUTPUT
- RT5663_GP4_PIN_CONF_SHIFT
- RT5663_GP8_PIN_CONF_INPUT
- RT5663_GP8_PIN_CONF_MASK
- RT5663_GP8_PIN_CONF_OUTPUT
- RT5663_GP8_PIN_CONF_SHIFT
- RT5663_GPIO1_TYPE_DIS
- RT5663_GPIO1_TYPE_EN
- RT5663_GPIO1_TYPE_MASK
- RT5663_GPIO1_TYPE_SHIFT
- RT5663_GPIO_1
- RT5663_GPIO_2
- RT5663_GPIO_3
- RT5663_GPIO_4
- RT5663_GPIO_STA1
- RT5663_GPIO_STA2
- RT5663_HPA_CPL_BIAS_0_5
- RT5663_HPA_CPL_BIAS_1
- RT5663_HPA_CPL_BIAS_2
- RT5663_HPA_CPL_BIAS_3
- RT5663_HPA_CPL_BIAS_4_1
- RT5663_HPA_CPL_BIAS_4_2
- RT5663_HPA_CPL_BIAS_6
- RT5663_HPA_CPL_BIAS_8
- RT5663_HPA_CPL_BIAS_MASK
- RT5663_HPA_CPL_BIAS_SHIFT
- RT5663_HPA_CPR_BIAS_0_5
- RT5663_HPA_CPR_BIAS_1
- RT5663_HPA_CPR_BIAS_2
- RT5663_HPA_CPR_BIAS_3
- RT5663_HPA_CPR_BIAS_4_1
- RT5663_HPA_CPR_BIAS_4_2
- RT5663_HPA_CPR_BIAS_6
- RT5663_HPA_CPR_BIAS_8
- RT5663_HPA_CPR_BIAS_MASK
- RT5663_HPA_CPR_BIAS_SHIFT
- RT5663_HP_AMP_2
- RT5663_HP_AMP_DET
- RT5663_HP_AMP_DET1
- RT5663_HP_AMP_DET2
- RT5663_HP_AMP_DET3
- RT5663_HP_BIAS
- RT5663_HP_CALIB_1
- RT5663_HP_CALIB_10
- RT5663_HP_CALIB_11
- RT5663_HP_CALIB_1_1
- RT5663_HP_CALIB_2
- RT5663_HP_CALIB_3
- RT5663_HP_CALIB_4
- RT5663_HP_CALIB_5
- RT5663_HP_CALIB_5_1
- RT5663_HP_CALIB_6
- RT5663_HP_CALIB_7
- RT5663_HP_CALIB_9
- RT5663_HP_CALIB_ST1
- RT5663_HP_CALIB_ST10
- RT5663_HP_CALIB_ST11
- RT5663_HP_CALIB_ST2
- RT5663_HP_CALIB_ST3
- RT5663_HP_CALIB_ST4
- RT5663_HP_CALIB_ST5
- RT5663_HP_CALIB_ST6
- RT5663_HP_CALIB_ST7
- RT5663_HP_CALIB_ST8
- RT5663_HP_CALIB_ST9
- RT5663_HP_CHARGE_PUMP_1
- RT5663_HP_CHARGE_PUMP_2
- RT5663_HP_DECOUP
- RT5663_HP_DECRO_1
- RT5663_HP_DECRO_2
- RT5663_HP_DECRO_3
- RT5663_HP_DECRO_4
- RT5663_HP_IMPSEN_DIG5
- RT5663_HP_IMPSEN_MAP1
- RT5663_HP_IMPSEN_MAP2
- RT5663_HP_IMPSEN_MAP3
- RT5663_HP_IMPSEN_MAP4
- RT5663_HP_IMPSEN_MAP5
- RT5663_HP_IMPSEN_MAP7
- RT5663_HP_IMP_GAIN_1
- RT5663_HP_IMP_GAIN_2
- RT5663_HP_IMP_SEN_1
- RT5663_HP_IMP_SEN_10
- RT5663_HP_IMP_SEN_11
- RT5663_HP_IMP_SEN_12
- RT5663_HP_IMP_SEN_13
- RT5663_HP_IMP_SEN_14
- RT5663_HP_IMP_SEN_15
- RT5663_HP_IMP_SEN_16
- RT5663_HP_IMP_SEN_17
- RT5663_HP_IMP_SEN_18
- RT5663_HP_IMP_SEN_19
- RT5663_HP_IMP_SEN_2
- RT5663_HP_IMP_SEN_3
- RT5663_HP_IMP_SEN_4
- RT5663_HP_IMP_SEN_5
- RT5663_HP_IMP_SEN_6
- RT5663_HP_IMP_SEN_7
- RT5663_HP_IMP_SEN_8
- RT5663_HP_IMP_SEN_9
- RT5663_HP_IMP_SEN_MAP10
- RT5663_HP_IMP_SEN_MAP11
- RT5663_HP_IMP_SEN_MAP8
- RT5663_HP_IMP_SEN_MAP9
- RT5663_HP_LCH_DRE
- RT5663_HP_LOGIC_1
- RT5663_HP_LOGIC_2
- RT5663_HP_LOGIC_3
- RT5663_HP_OUT_EN
- RT5663_HP_RCH_DRE
- RT5663_HP_SIG_SRC1_HP_CALIB
- RT5663_HP_SIG_SRC1_HP_DC
- RT5663_HP_SIG_SRC1_MASK
- RT5663_HP_SIG_SRC1_REG
- RT5663_HP_SIG_SRC1_SHIFT
- RT5663_HP_SIG_SRC1_SILENCE
- RT5663_I2C_BYPA
- RT5663_I2S1_ASRC_MASK
- RT5663_I2S1_ASRC_SHIFT
- RT5663_I2S1_SDP
- RT5663_I2S34_SDP
- RT5663_I2S5_SDP
- RT5663_I2S_BP_INV
- RT5663_I2S_BP_MASK
- RT5663_I2S_BP_NOR
- RT5663_I2S_BP_SHIFT
- RT5663_I2S_DF_I2S
- RT5663_I2S_DF_LEFT
- RT5663_I2S_DF_MASK
- RT5663_I2S_DF_PCM_A
- RT5663_I2S_DF_PCM_A_N
- RT5663_I2S_DF_PCM_B
- RT5663_I2S_DF_PCM_B_N
- RT5663_I2S_DF_SHIFT
- RT5663_I2S_DL_16
- RT5663_I2S_DL_20
- RT5663_I2S_DL_24
- RT5663_I2S_DL_8
- RT5663_I2S_DL_MASK
- RT5663_I2S_DL_SHIFT
- RT5663_I2S_MS_M
- RT5663_I2S_MS_MASK
- RT5663_I2S_MS_S
- RT5663_I2S_MS_SHIFT
- RT5663_I2S_M_CLK_CTL
- RT5663_I2S_PD1_MASK
- RT5663_I2S_PD1_SHIFT
- RT5663_IF_3_4_DATA_CTL
- RT5663_IF_5_DATA_CTL
- RT5663_IL_CMD_1
- RT5663_IL_CMD_2
- RT5663_IL_CMD_3
- RT5663_IL_CMD_4
- RT5663_IL_CMD_5
- RT5663_IL_CMD_6
- RT5663_IL_CMD_7
- RT5663_IL_CMD_8
- RT5663_IL_CMD_PWRSAV1
- RT5663_IL_CMD_PWRSAV2
- RT5663_IN1_DF_MASK
- RT5663_IN1_DF_SHIFT
- RT5663_IN1_IN2
- RT5663_IN3_IN4
- RT5663_INBUF_CBJ_BST1_MASK
- RT5663_INBUF_CBJ_BST1_OFF
- RT5663_INBUF_CBJ_BST1_ON
- RT5663_INBUF_CBJ_BST1_SHIFT
- RT5663_INL1_INR1
- RT5663_INT_ST_1
- RT5663_INT_ST_2
- RT5663_IRQ_1
- RT5663_IRQ_2
- RT5663_IRQ_3
- RT5663_IRQ_4
- RT5663_IRQ_5
- RT5663_IRQ_MANUAL_DIS
- RT5663_IRQ_MANUAL_EN
- RT5663_IRQ_MANUAL_MASK
- RT5663_IRQ_MANUAL_SHIFT
- RT5663_IRQ_POW_SAV_DIS
- RT5663_IRQ_POW_SAV_EN
- RT5663_IRQ_POW_SAV_JD1_DIS
- RT5663_IRQ_POW_SAV_JD1_EN
- RT5663_IRQ_POW_SAV_JD1_MASK
- RT5663_IRQ_POW_SAV_JD1_SHIFT
- RT5663_IRQ_POW_SAV_MASK
- RT5663_IRQ_POW_SAV_SHIFT
- RT5663_JD1_TRES_CTRL
- RT5663_JD2_TRES_CTRL
- RT5663_JD_CTRL1
- RT5663_JD_CTRL2
- RT5663_LDO1_DVO_0_9V
- RT5663_LDO1_DVO_1_0V
- RT5663_LDO1_DVO_1_2V
- RT5663_LDO1_DVO_1_4V
- RT5663_LDO1_DVO_MASK
- RT5663_LDO1_DVO_SHIFT
- RT5663_LOUT_CTRL
- RT5663_LOUT_MIXER_CTRL
- RT5663_LOW_BD_HP_AMP
- RT5663_MICBIAS_1
- RT5663_MIC_DECRO_1
- RT5663_MIC_DECRO_2
- RT5663_MIC_DECRO_3
- RT5663_MIC_DECRO_4
- RT5663_MIC_DECRO_5
- RT5663_MIC_DECRO_6
- RT5663_MID_BD_HP_AMP
- RT5663_MONO1_ADC_MIXER
- RT5663_MONOL_SIL_DET
- RT5663_MONOMIX_GAIN
- RT5663_MONOMIX_IN_GAIN
- RT5663_MONOR_SIL_DET
- RT5663_MONO_ADC_BST_GAIN
- RT5663_MONO_ADC_DIG_VOL
- RT5663_MONO_AMP_CAL1
- RT5663_MONO_AMP_CAL2
- RT5663_MONO_AMP_CAL3
- RT5663_MONO_AMP_CAL4
- RT5663_MONO_AMP_CAL5
- RT5663_MONO_AMP_CAL6
- RT5663_MONO_AMP_CAL7
- RT5663_MONO_AMP_CAL_ST1
- RT5663_MONO_AMP_CAL_ST2
- RT5663_MONO_AMP_CAL_ST3
- RT5663_MONO_AMP_CAL_ST4
- RT5663_MONO_AMP_CAL_ST5
- RT5663_MONO_DAC_MIXER
- RT5663_MONO_DYNA_1
- RT5663_MONO_DYNA_2
- RT5663_MONO_DYNA_3
- RT5663_MONO_DYNA_4
- RT5663_MONO_DYNA_5
- RT5663_MONO_DYNA_6
- RT5663_MONO_GAIN
- RT5663_MONO_OUT
- RT5663_M_ADCMIX_L
- RT5663_M_ADCMIX_L_SHIFT
- RT5663_M_ADCMIX_R
- RT5663_M_ADCMIX_R_SHIFT
- RT5663_M_DAC1_L
- RT5663_M_DAC1_L_SHIFT
- RT5663_M_DAC1_R
- RT5663_M_DAC1_R_SHIFT
- RT5663_M_DAC_L1_STO_L
- RT5663_M_DAC_L1_STO_L_SHIFT
- RT5663_M_DAC_L1_STO_R
- RT5663_M_DAC_L1_STO_R_SHIFT
- RT5663_M_DAC_R1_STO_L
- RT5663_M_DAC_R1_STO_L_SHIFT
- RT5663_M_DAC_R1_STO_R
- RT5663_M_DAC_R1_STO_R_SHIFT
- RT5663_M_I2S_DIV_MASK
- RT5663_M_I2S_DIV_SHIFT
- RT5663_M_STO1_ADC_L1
- RT5663_M_STO1_ADC_L1_SHIFT
- RT5663_M_STO1_ADC_L2
- RT5663_M_STO1_ADC_L2_SHIFT
- RT5663_M_STO1_ADC_R1
- RT5663_M_STO1_ADC_R1_SHIFT
- RT5663_M_STO1_ADC_R2
- RT5663_M_STO1_ADC_R2_SHIFT
- RT5663_OSW_HP_L_DIS
- RT5663_OSW_HP_L_EN
- RT5663_OSW_HP_L_MASK
- RT5663_OSW_HP_L_SHIFT
- RT5663_OSW_HP_R_DIS
- RT5663_OSW_HP_R_EN
- RT5663_OSW_HP_R_MASK
- RT5663_OSW_HP_R_SHIFT
- RT5663_OUT_LMIX_IN_GAIN
- RT5663_OUT_MIXL_GAIN
- RT5663_OUT_RMIX_IN_GAIN
- RT5663_OUT_RMIX_IN_GAIN1
- RT5663_OVCD_HP_DIS
- RT5663_OVCD_HP_EN
- RT5663_OVCD_HP_MASK
- RT5663_OVCD_HP_SHIFT
- RT5663_PAD_DRV_CTL
- RT5663_PAD_DRV_CTL1
- RT5663_PDM_I2C_DATA_CTL1
- RT5663_PDM_I2C_DATA_CTL2
- RT5663_PDM_I2C_DATA_CTL3
- RT5663_PDM_I2C_DATA_CTL4
- RT5663_PDM_OUT_CTL
- RT5663_PLL1_PD_MASK
- RT5663_PLL1_PD_SHIFT
- RT5663_PLL1_SRC_BCLK1
- RT5663_PLL1_SRC_MASK
- RT5663_PLL1_SRC_MCLK
- RT5663_PLL1_SRC_SHIFT
- RT5663_PLL1_S_BCLK1
- RT5663_PLL1_S_MCLK
- RT5663_PLL_1
- RT5663_PLL_2
- RT5663_PLL_INP_MAX
- RT5663_PLL_INP_MIN
- RT5663_PLL_INT_REG
- RT5663_PLL_K_MASK
- RT5663_PLL_K_MAX
- RT5663_PLL_K_SHIFT
- RT5663_PLL_M_BP
- RT5663_PLL_M_BP_SHIFT
- RT5663_PLL_M_MASK
- RT5663_PLL_M_MAX
- RT5663_PLL_M_SHIFT
- RT5663_PLL_N_MASK
- RT5663_PLL_N_MAX
- RT5663_PLL_N_SHIFT
- RT5663_PLL_TRK_13
- RT5663_POL_EXT_JD_DIS
- RT5663_POL_EXT_JD_EN
- RT5663_POL_EXT_JD_MASK
- RT5663_POL_EXT_JD_SHIFT
- RT5663_POWER_ON_DELAY_MS
- RT5663_PRE_DIV_GATING_1
- RT5663_PRE_DIV_GATING_2
- RT5663_PRO_REG_TBL_4
- RT5663_PRO_REG_TBL_5
- RT5663_PRO_REG_TBL_6
- RT5663_PRO_REG_TBL_7
- RT5663_PRO_REG_TBL_8
- RT5663_PRO_REG_TBL_9
- RT5663_PWR_ADC_L1
- RT5663_PWR_ADC_L1_SHIFT
- RT5663_PWR_ADC_R1
- RT5663_PWR_ADC_R1_SHIFT
- RT5663_PWR_ADC_S1F
- RT5663_PWR_ADC_S1F_SHIFT
- RT5663_PWR_ANLG_1
- RT5663_PWR_ANLG_2
- RT5663_PWR_ANLG_3
- RT5663_PWR_BST1
- RT5663_PWR_BST1_MASK
- RT5663_PWR_BST1_OFF
- RT5663_PWR_BST1_ON
- RT5663_PWR_BST1_SHIFT
- RT5663_PWR_BST2
- RT5663_PWR_BST2_MASK
- RT5663_PWR_BST2_OP
- RT5663_PWR_BST2_OP_MASK
- RT5663_PWR_BST2_OP_SHIFT
- RT5663_PWR_BST2_SHIFT
- RT5663_PWR_CBJ_MASK
- RT5663_PWR_CBJ_OFF
- RT5663_PWR_CBJ_ON
- RT5663_PWR_CBJ_SHIFT
- RT5663_PWR_CLK_DET_DIS
- RT5663_PWR_CLK_DET_EN
- RT5663_PWR_CLK_DET_MASK
- RT5663_PWR_CLK_DET_SHIFT
- RT5663_PWR_DAC_L1
- RT5663_PWR_DAC_L1_SHIFT
- RT5663_PWR_DAC_R1
- RT5663_PWR_DAC_R1_SHIFT
- RT5663_PWR_DAC_S1F
- RT5663_PWR_DAC_S1F_SHIFT
- RT5663_PWR_DIG_1
- RT5663_PWR_DIG_2
- RT5663_PWR_FV1
- RT5663_PWR_FV1_MASK
- RT5663_PWR_FV1_SHIFT
- RT5663_PWR_FV2
- RT5663_PWR_FV2_MASK
- RT5663_PWR_FV2_SHIFT
- RT5663_PWR_I2S1
- RT5663_PWR_I2S1_SHIFT
- RT5663_PWR_JD1
- RT5663_PWR_JD1_MASK
- RT5663_PWR_JD1_SHIFT
- RT5663_PWR_JD2
- RT5663_PWR_JD2_MASK
- RT5663_PWR_JD2_SHIFT
- RT5663_PWR_LDO2
- RT5663_PWR_LDO2_SHIFT
- RT5663_PWR_LDO_DACREFL_MASK
- RT5663_PWR_LDO_DACREFL_SHIFT
- RT5663_PWR_LDO_DACREFR_MASK
- RT5663_PWR_LDO_DACREFR_SHIFT
- RT5663_PWR_LDO_DACREF_DOWN
- RT5663_PWR_LDO_DACREF_MASK
- RT5663_PWR_LDO_DACREF_ON
- RT5663_PWR_LDO_DACREF_SHIFT
- RT5663_PWR_LDO_SHIFT
- RT5663_PWR_MB
- RT5663_PWR_MB1
- RT5663_PWR_MB1_SHIFT
- RT5663_PWR_MB2
- RT5663_PWR_MB2_SHIFT
- RT5663_PWR_MB_MASK
- RT5663_PWR_MB_SHIFT
- RT5663_PWR_MIC_DET_MASK
- RT5663_PWR_MIC_DET_OFF
- RT5663_PWR_MIC_DET_ON
- RT5663_PWR_MIC_DET_SHIFT
- RT5663_PWR_MIXER
- RT5663_PWR_PLL
- RT5663_PWR_PLL_SHIFT
- RT5663_PWR_RECMIX1
- RT5663_PWR_RECMIX1_SHIFT
- RT5663_PWR_RECMIX2
- RT5663_PWR_RECMIX2_SHIFT
- RT5663_PWR_SAV_CTL1
- RT5663_PWR_SAV_CTL2
- RT5663_PWR_SAV_CTL3
- RT5663_PWR_SAV_CTL4
- RT5663_PWR_SAV_CTL5
- RT5663_PWR_SAV_CTL6
- RT5663_PWR_SAV_SILDET
- RT5663_PWR_VOL
- RT5663_PWR_VREF1
- RT5663_PWR_VREF1_MASK
- RT5663_PWR_VREF1_SHIFT
- RT5663_PWR_VREF2
- RT5663_PWR_VREF2_MASK
- RT5663_PWR_VREF2_SHIFT
- RT5663_RC_CLK
- RT5663_RECMIX
- RT5663_RECMIX1L
- RT5663_RECMIX1L_0
- RT5663_RECMIX1L_BST1_CBJ
- RT5663_RECMIX1L_BST1_CBJ_SHIFT
- RT5663_RECMIX1L_BST2
- RT5663_RECMIX1L_BST2_SHIFT
- RT5663_RECMIX1R
- RT5663_RECMIX1R_0
- RT5663_RECMIX1R_BST2
- RT5663_RECMIX1R_BST2_SHIFT
- RT5663_RECMIX1_BST1_MASK
- RT5663_RECMIX1_BST1_OFF
- RT5663_RECMIX1_BST1_ON
- RT5663_RECMIX1_BST1_SHIFT
- RT5663_RECMIX1_NEW
- RT5663_RECMIX2_L_2
- RT5663_RECMIX2_NEW
- RT5663_RECMIX2_R
- RT5663_RECMIX2_R_2
- RT5663_REC_PATH_GAIN
- RT5663_RESET
- RT5663_RESET_4BTN_INL_MASK
- RT5663_RESET_4BTN_INL_NOR
- RT5663_RESET_4BTN_INL_RESET
- RT5663_RESET_4BTN_INL_SHIFT
- RT5663_SAR_ADC_INL_1
- RT5663_SAR_ADC_INL_10
- RT5663_SAR_ADC_INL_11
- RT5663_SAR_ADC_INL_12
- RT5663_SAR_ADC_INL_2
- RT5663_SAR_ADC_INL_3
- RT5663_SAR_ADC_INL_4
- RT5663_SAR_ADC_INL_5
- RT5663_SAR_ADC_INL_6
- RT5663_SAR_ADC_INL_7
- RT5663_SAR_ADC_INL_8
- RT5663_SAR_ADC_INL_9
- RT5663_SCAN_MODE
- RT5663_SCLK_SRC_MASK
- RT5663_SCLK_SRC_MCLK
- RT5663_SCLK_SRC_PLL1
- RT5663_SCLK_SRC_RCCLK
- RT5663_SCLK_SRC_SHIFT
- RT5663_SCLK_S_MCLK
- RT5663_SCLK_S_PLL1
- RT5663_SCLK_S_RCCLK
- RT5663_SEL_GPIO1_DIS
- RT5663_SEL_GPIO1_EN
- RT5663_SEL_GPIO1_MASK
- RT5663_SEL_GPIO1_SHIFT
- RT5663_SEL_PM_HP_0_6
- RT5663_SEL_PM_HP_0_9
- RT5663_SEL_PM_HP_1_8
- RT5663_SEL_PM_HP_HIGH
- RT5663_SEL_PM_HP_MASK
- RT5663_SEL_PM_HP_SHIFT
- RT5663_SIDETONE_CTL
- RT5663_SIDETONE_CTRL
- RT5663_SIG_CLK_DET
- RT5663_SIL_DET_CTL
- RT5663_SIN_GEN_1
- RT5663_SIN_GEN_2
- RT5663_SIN_GEN_3
- RT5663_SI_HP_DIS
- RT5663_SI_HP_EN
- RT5663_SI_HP_MASK
- RT5663_SI_HP_SHIFT
- RT5663_SOFT_RAMP
- RT5663_SOF_RAM_DEPOP
- RT5663_SOF_VOL_ZC1
- RT5663_SOF_VOL_ZC2
- RT5663_STEREO_RATES
- RT5663_STO1_ADC_DIG_VOL
- RT5663_STO1_ADC_L1_SRC
- RT5663_STO1_ADC_L1_SRC_SHIFT
- RT5663_STO1_ADC_L2_SRC
- RT5663_STO1_ADC_L2_SRC_SHIFT
- RT5663_STO1_ADC_L_SRC
- RT5663_STO1_ADC_L_SRC_SHIFT
- RT5663_STO1_ADC_MIXER
- RT5663_STO1_ADC_R1_SRC
- RT5663_STO1_ADC_R1_SRC_SHIFT
- RT5663_STO1_ADC_R2_SRC
- RT5663_STO1_ADC_R2_SRC_SHIFT
- RT5663_STO1_ADC_R_SRC
- RT5663_STO1_ADC_R_SRC_SHIFT
- RT5663_STO1_BOOST
- RT5663_STO1_DAC_DIG_VOL
- RT5663_STO1_HPF_ADJ1
- RT5663_STO1_HPF_ADJ2
- RT5663_STO1_SIL_DET
- RT5663_STO2_ADC_BST_GAIN
- RT5663_STO2_ADC_DIG_VOL
- RT5663_STO2_ADC_MIXER
- RT5663_STO2_DAC_SIL
- RT5663_STO_DAC_MIXER
- RT5663_STO_DRE_1
- RT5663_STO_DRE_10
- RT5663_STO_DRE_2
- RT5663_STO_DRE_3
- RT5663_STO_DRE_4
- RT5663_STO_DRE_5
- RT5663_STO_DRE_6
- RT5663_STO_DRE_7
- RT5663_STO_DRE_8
- RT5663_STO_DRE_9
- RT5663_SUPPLY_CURRENT_UA
- RT5663_TDM_1
- RT5663_TDM_2
- RT5663_TDM_3
- RT5663_TDM_4
- RT5663_TDM_5
- RT5663_TDM_6
- RT5663_TDM_7
- RT5663_TDM_8
- RT5663_TDM_9
- RT5663_TDM_IN_CH_2
- RT5663_TDM_IN_CH_4
- RT5663_TDM_IN_CH_6
- RT5663_TDM_IN_CH_8
- RT5663_TDM_IN_CH_MASK
- RT5663_TDM_IN_CH_SHIFT
- RT5663_TDM_IN_LEN_16
- RT5663_TDM_IN_LEN_20
- RT5663_TDM_IN_LEN_24
- RT5663_TDM_IN_LEN_32
- RT5663_TDM_IN_LEN_MASK
- RT5663_TDM_IN_LEN_SHIFT
- RT5663_TDM_LENGTN_16
- RT5663_TDM_LENGTN_20
- RT5663_TDM_LENGTN_24
- RT5663_TDM_LENGTN_32
- RT5663_TDM_LENGTN_MASK
- RT5663_TDM_LENGTN_SHIFT
- RT5663_TDM_MODE_I2S
- RT5663_TDM_MODE_MASK
- RT5663_TDM_MODE_SHIFT
- RT5663_TDM_MODE_TDM
- RT5663_TDM_OUT_CH_2
- RT5663_TDM_OUT_CH_4
- RT5663_TDM_OUT_CH_6
- RT5663_TDM_OUT_CH_8
- RT5663_TDM_OUT_CH_MASK
- RT5663_TDM_OUT_CH_SHIFT
- RT5663_TDM_OUT_LEN_16
- RT5663_TDM_OUT_LEN_20
- RT5663_TDM_OUT_LEN_24
- RT5663_TDM_OUT_LEN_32
- RT5663_TDM_OUT_LEN_MASK
- RT5663_TDM_OUT_LEN_SHIFT
- RT5663_TEST_MODE_1
- RT5663_TEST_MODE_2
- RT5663_TEST_MODE_3
- RT5663_TEST_MODE_4
- RT5663_TEST_MODE_5
- RT5663_V2_ADC_STO1_ASRC_MASK
- RT5663_V2_ADC_STO1_ASRC_SHIFT
- RT5663_V2_AD_STO1_TRACK_I2S1
- RT5663_V2_AD_STO1_TRACK_MASK
- RT5663_V2_AD_STO1_TRACK_SHIFT
- RT5663_V2_AD_STO1_TRACK_SYSCLK
- RT5663_V2_DAC_STO1_ASRC_MASK
- RT5663_V2_DAC_STO1_ASRC_SHIFT
- RT5663_V2_EN_IRQ_INLINE_BYP
- RT5663_V2_EN_IRQ_INLINE_MASK
- RT5663_V2_EN_IRQ_INLINE_NOR
- RT5663_V2_EN_IRQ_INLINE_SHIFT
- RT5663_V2_HP_IMP_SEN_10
- RT5663_V2_HP_IMP_SEN_13
- RT5663_V2_HP_IMP_SEN_14
- RT5663_V2_HP_IMP_SEN_6
- RT5663_V2_HP_IMP_SEN_7
- RT5663_V2_HP_IMP_SEN_8
- RT5663_V2_HP_IMP_SEN_9
- RT5663_V2_I2S1_ASRC_MASK
- RT5663_V2_I2S1_ASRC_SHIFT
- RT5663_V2_IRQ_4
- RT5663_V2_JD_CTRL2
- RT5663_V2_PLL1_SRC_BCLK1
- RT5663_V2_PLL1_SRC_MASK
- RT5663_V2_PLL1_SRC_MCLK
- RT5663_V2_PLL1_SRC_SHIFT
- RT5663_V2_PWR_MIC_DET
- RT5663_V2_PWR_MIC_DET_SHIFT
- RT5663_VENDOR_ID
- RT5663_VENDOR_ID_1
- RT5663_VENDOR_ID_2
- RT5663_VID_CUSTOMER
- RT5663_VID_HIDDEN
- RT5663_VOL_TEST
- RT5663_VREFADJ_OP
- RT5663_VREF_BIAS_FSM
- RT5663_VREF_BIAS_MASK
- RT5663_VREF_BIAS_REG
- RT5663_VREF_BIAS_SHIFT
- RT5663_VREF_RECMIX
- RT5665_4BTN_IL_CMD_1
- RT5665_4BTN_IL_CMD_2
- RT5665_4BTN_IL_CMD_3
- RT5665_4BTN_IL_DIS
- RT5665_4BTN_IL_EN
- RT5665_4BTN_IL_MASK
- RT5665_4BTN_IL_NOR
- RT5665_4BTN_IL_RST
- RT5665_4BTN_IL_RST_MASK
- RT5665_AD2DA_LB_MASK
- RT5665_AD2DA_LB_SFT
- RT5665_ADC_L_EQ_LPF1_A1
- RT5665_ADC_L_VOL_MASK
- RT5665_ADC_L_VOL_SFT
- RT5665_ADC_MONO_HP_CTRL_1
- RT5665_ADC_MONO_HP_CTRL_2
- RT5665_ADC_MONO_L_ASRC_MASK
- RT5665_ADC_MONO_L_ASRC_SFT
- RT5665_ADC_MONO_R_ASRC_MASK
- RT5665_ADC_MONO_R_ASRC_SFT
- RT5665_ADC_OSR_128
- RT5665_ADC_OSR_32
- RT5665_ADC_OSR_64
- RT5665_ADC_OSR_MASK
- RT5665_ADC_OSR_SFT
- RT5665_ADC_R_VOL_MASK
- RT5665_ADC_R_VOL_SFT
- RT5665_ADC_STO1_ASRC_MASK
- RT5665_ADC_STO1_ASRC_SFT
- RT5665_ADC_STO1_HP_CTRL_1
- RT5665_ADC_STO1_HP_CTRL_2
- RT5665_ADC_STO2_ASRC_MASK
- RT5665_ADC_STO2_ASRC_SFT
- RT5665_ADC_STO2_HP_CTRL_1
- RT5665_ADC_STO2_HP_CTRL_2
- RT5665_ADDA_CLK_1
- RT5665_ADDA_CLK_2
- RT5665_AD_DA_MIXER
- RT5665_AD_MONOL_CLK_SEL_MASK
- RT5665_AD_MONOL_CLK_SEL_SFT
- RT5665_AD_MONOR_CLK_SEL_MASK
- RT5665_AD_MONOR_CLK_SEL_SFT
- RT5665_AD_MONO_L_FILTER
- RT5665_AD_MONO_R_FILTER
- RT5665_AD_STEREO1_FILTER
- RT5665_AD_STEREO2_FILTER
- RT5665_AD_STO1_CLK_SEL_MASK
- RT5665_AD_STO1_CLK_SEL_SFT
- RT5665_AD_STO2_CLK_SEL_MASK
- RT5665_AD_STO2_CLK_SEL_SFT
- RT5665_AIF1_1
- RT5665_AIF1_2
- RT5665_AIF2_1
- RT5665_AIF2_2
- RT5665_AIF3
- RT5665_AIFS
- RT5665_AJD1_CTRL
- RT5665_ALC_BACK_GAIN
- RT5665_ALC_PGA_CTRL_1
- RT5665_ALC_PGA_CTRL_2
- RT5665_ALC_PGA_CTRL_3
- RT5665_ALC_PGA_CTRL_4
- RT5665_ALC_PGA_CTRL_5
- RT5665_ALC_PGA_CTRL_6
- RT5665_ALC_PGA_CTRL_7
- RT5665_ALC_PGA_CTRL_8
- RT5665_ALC_PGA_STA_1
- RT5665_ALC_PGA_STA_2
- RT5665_ALC_PGA_STA_3
- RT5665_AM_DIS
- RT5665_AM_EN
- RT5665_AM_MASK
- RT5665_ASRC_1
- RT5665_ASRC_10
- RT5665_ASRC_12
- RT5665_ASRC_13
- RT5665_ASRC_14
- RT5665_ASRC_2
- RT5665_ASRC_3
- RT5665_ASRC_4
- RT5665_ASRC_5
- RT5665_ASRC_6
- RT5665_ASRC_7
- RT5665_ASRC_8
- RT5665_ASRC_9
- RT5665_A_DAC1_MUX
- RT5665_A_DAC2_MUX
- RT5665_A_DACL1_SFT
- RT5665_A_DACL2_SEL
- RT5665_A_DACL2_SFT
- RT5665_A_DACR1_SFT
- RT5665_A_DACR2_SEL
- RT5665_A_DACR2_SFT
- RT5665_BASSBACK_CTRL
- RT5665_BIAS_CUR_CTRL_1
- RT5665_BIAS_CUR_CTRL_10
- RT5665_BIAS_CUR_CTRL_2
- RT5665_BIAS_CUR_CTRL_3
- RT5665_BIAS_CUR_CTRL_4
- RT5665_BIAS_CUR_CTRL_5
- RT5665_BIAS_CUR_CTRL_6
- RT5665_BIAS_CUR_CTRL_7
- RT5665_BIAS_CUR_CTRL_8
- RT5665_BIAS_CUR_CTRL_9
- RT5665_BPS_DIS
- RT5665_BPS_EN
- RT5665_BPS_MASK
- RT5665_BPS_SFT
- RT5665_BST1_MASK
- RT5665_BST1_SFT
- RT5665_BST2_MASK
- RT5665_BST2_SFT
- RT5665_BST3_MASK
- RT5665_BST3_SFT
- RT5665_BST4_MASK
- RT5665_BST4_SFT
- RT5665_BST_CBJ_MASK
- RT5665_BST_CBJ_SFT
- RT5665_CALIB_ADC_CTRL
- RT5665_CAL_BST_CTRL
- RT5665_CAL_REC
- RT5665_CBJ_BST_CTRL
- RT5665_CBJ_JD_TEST_MASK
- RT5665_CBJ_JD_TEST_MODE
- RT5665_CBJ_JD_TEST_NORM
- RT5665_CHARGE_PUMP_1
- RT5665_CHOP_ADC
- RT5665_CHOP_DAC
- RT5665_CKGEN_ADC1_MASK
- RT5665_CKGEN_ADC1_SFT
- RT5665_CKGEN_ADC2_MASK
- RT5665_CKGEN_ADC2_SFT
- RT5665_CKGEN_DAC1_MASK
- RT5665_CKGEN_DAC1_SFT
- RT5665_CKGEN_DAC2_MASK
- RT5665_CKGEN_DAC2_SFT
- RT5665_CKXEN_ADC1_MASK
- RT5665_CKXEN_ADC1_SFT
- RT5665_CKXEN_ADC2_MASK
- RT5665_CKXEN_ADC2_SFT
- RT5665_CKXEN_DAC1_MASK
- RT5665_CKXEN_DAC1_SFT
- RT5665_CKXEN_DAC2_MASK
- RT5665_CKXEN_DAC2_SFT
- RT5665_CLK_DET
- RT5665_CLK_SEL_I2S1_ASRC
- RT5665_CLK_SEL_I2S2_ASRC
- RT5665_CLK_SEL_I2S3_ASRC
- RT5665_CLK_SEL_SYS
- RT5665_CLK_SEL_SYS2
- RT5665_CLK_SEL_SYS3
- RT5665_CLK_SEL_SYS4
- RT5665_CLK_SRC_MCLK
- RT5665_CLK_SRC_PLL1
- RT5665_CLK_SRC_RCCLK
- RT5665_CP_FQ1_MASK
- RT5665_CP_FQ1_SFT
- RT5665_CP_FQ2_MASK
- RT5665_CP_FQ2_SFT
- RT5665_CP_FQ3_MASK
- RT5665_CP_FQ3_SFT
- RT5665_CP_FQ_12_KHZ
- RT5665_CP_FQ_192_KHZ
- RT5665_CP_FQ_1_5_KHZ
- RT5665_CP_FQ_24_KHZ
- RT5665_CP_FQ_3_KHZ
- RT5665_CP_FQ_48_KHZ
- RT5665_CP_FQ_6_KHZ
- RT5665_CP_FQ_96_KHZ
- RT5665_CP_SYS_MASK
- RT5665_CP_SYS_SFT
- RT5665_CTRL_MB1_FSM
- RT5665_CTRL_MB1_REG
- RT5665_CTRL_MB2_FSM
- RT5665_CTRL_MB2_REG
- RT5665_DAC1_DIG_VOL
- RT5665_DAC1_L_SEL_MASK
- RT5665_DAC1_L_SEL_SFT
- RT5665_DAC1_R_SEL_MASK
- RT5665_DAC1_R_SEL_SFT
- RT5665_DAC2_CTRL
- RT5665_DAC2_DIG_VOL
- RT5665_DAC3_CTRL
- RT5665_DAC3_DIG_VOL
- RT5665_DAC_ADC_DIG_VOL1
- RT5665_DAC_ADC_DIG_VOL2
- RT5665_DAC_L1_SRC_MASK
- RT5665_DAC_L1_VOL_MASK
- RT5665_DAC_L1_VOL_SFT
- RT5665_DAC_L2_SEL_MASK
- RT5665_DAC_L2_SEL_SFT
- RT5665_DAC_L2_VOL_MASK
- RT5665_DAC_L2_VOL_SFT
- RT5665_DAC_L3_SEL_MASK
- RT5665_DAC_L3_SEL_SFT
- RT5665_DAC_MIX_L_MASK
- RT5665_DAC_MIX_L_SFT
- RT5665_DAC_MIX_R_MASK
- RT5665_DAC_MIX_R_SFT
- RT5665_DAC_MONO_L_ASRC_MASK
- RT5665_DAC_MONO_L_ASRC_SFT
- RT5665_DAC_MONO_R_ASRC_MASK
- RT5665_DAC_MONO_R_ASRC_SFT
- RT5665_DAC_OSR_128
- RT5665_DAC_OSR_32
- RT5665_DAC_OSR_64
- RT5665_DAC_OSR_MASK
- RT5665_DAC_OSR_SFT
- RT5665_DAC_R1_SRC_MASK
- RT5665_DAC_R1_VOL_MASK
- RT5665_DAC_R1_VOL_SFT
- RT5665_DAC_R2_SEL_MASK
- RT5665_DAC_R2_SEL_SFT
- RT5665_DAC_R2_VOL_MASK
- RT5665_DAC_R2_VOL_SFT
- RT5665_DAC_R3_SEL_MASK
- RT5665_DAC_R3_SEL_SFT
- RT5665_DAC_STO1_ASRC_MASK
- RT5665_DAC_STO1_ASRC_SFT
- RT5665_DAC_STO2_ASRC_MASK
- RT5665_DAC_STO2_ASRC_SFT
- RT5665_DA_MONOL_CLK_SEL_MASK
- RT5665_DA_MONOL_CLK_SEL_SFT
- RT5665_DA_MONOR_CLK_SEL_MASK
- RT5665_DA_MONOR_CLK_SEL_SFT
- RT5665_DA_MONO_L_FILTER
- RT5665_DA_MONO_R_FILTER
- RT5665_DA_STEREO1_FILTER
- RT5665_DA_STEREO2_FILTER
- RT5665_DA_STO1_CLK_SEL_MASK
- RT5665_DA_STO1_CLK_SEL_SFT
- RT5665_DA_STO2_CLK_SEL_MASK
- RT5665_DA_STO2_CLK_SEL_SFT
- RT5665_DEB_80_MS
- RT5665_DEB_STO_DAC_MASK
- RT5665_DEPOP_1
- RT5665_DEPOP_2
- RT5665_DEPOP_AUTO
- RT5665_DEPOP_MAN
- RT5665_DEPOP_MASK
- RT5665_DEPOP_SFT
- RT5665_DEVICE_ID
- RT5665_DIG_DP_DIS
- RT5665_DIG_DP_EN
- RT5665_DIG_DP_MASK
- RT5665_DIG_DP_SFT
- RT5665_DIG_GATE_CTRL
- RT5665_DIG_GATE_CTRL_SFT
- RT5665_DIG_INF2_DATA
- RT5665_DIG_INF3_DATA
- RT5665_DIG_IN_CTRL_1
- RT5665_DIG_IN_CTRL_2
- RT5665_DIG_MISC
- RT5665_DMIC1_DATA_GPIO4
- RT5665_DMIC1_DATA_IN2N
- RT5665_DMIC1_NULL
- RT5665_DMIC2_DATA_GPIO5
- RT5665_DMIC2_DATA_IN2P
- RT5665_DMIC2_NULL
- RT5665_DMIC_1L_LH_FALLING
- RT5665_DMIC_1L_LH_MASK
- RT5665_DMIC_1L_LH_RISING
- RT5665_DMIC_1L_LH_SFT
- RT5665_DMIC_1R_LH_FALLING
- RT5665_DMIC_1R_LH_MASK
- RT5665_DMIC_1R_LH_RISING
- RT5665_DMIC_1R_LH_SFT
- RT5665_DMIC_1_DIS
- RT5665_DMIC_1_DP_GPIO4
- RT5665_DMIC_1_DP_IN2N
- RT5665_DMIC_1_DP_MASK
- RT5665_DMIC_1_DP_SFT
- RT5665_DMIC_1_EN
- RT5665_DMIC_1_EN_MASK
- RT5665_DMIC_1_EN_SFT
- RT5665_DMIC_2L_LH_FALLING
- RT5665_DMIC_2L_LH_MASK
- RT5665_DMIC_2L_LH_RISING
- RT5665_DMIC_2L_LH_SFT
- RT5665_DMIC_2R_LH_FALLING
- RT5665_DMIC_2R_LH_MASK
- RT5665_DMIC_2R_LH_RISING
- RT5665_DMIC_2R_LH_SFT
- RT5665_DMIC_2_DIS
- RT5665_DMIC_2_DP_GPIO5
- RT5665_DMIC_2_DP_IN2P
- RT5665_DMIC_2_DP_MASK
- RT5665_DMIC_2_DP_SFT
- RT5665_DMIC_2_EN
- RT5665_DMIC_2_EN_MASK
- RT5665_DMIC_2_EN_SFT
- RT5665_DMIC_CLK_MASK
- RT5665_DMIC_CLK_SFT
- RT5665_DMIC_CTRL_1
- RT5665_DMIC_CTRL_2
- RT5665_DMIC_MONO_L_ASRC_MASK
- RT5665_DMIC_MONO_L_ASRC_SFT
- RT5665_DMIC_MONO_R_ASRC_MASK
- RT5665_DMIC_MONO_R_ASRC_SFT
- RT5665_DMIC_STO1_ASRC_MASK
- RT5665_DMIC_STO1_ASRC_SFT
- RT5665_DMIC_STO2_ASRC_MASK
- RT5665_DMIC_STO2_ASRC_SFT
- RT5665_DP_TH_MASK
- RT5665_DP_TH_SFT
- RT5665_DRC1_CTRL_0
- RT5665_DRC1_CTRL_1
- RT5665_DRC1_CTRL_2
- RT5665_DRC1_CTRL_3
- RT5665_DRC1_CTRL_4
- RT5665_DRC1_CTRL_5
- RT5665_DRC1_CTRL_6
- RT5665_DRC1_HARD_LMT_CTRL_1
- RT5665_DRC1_HARD_LMT_CTRL_2
- RT5665_DRC1_PRIV_1
- RT5665_DRC1_PRIV_2
- RT5665_DRC1_PRIV_3
- RT5665_DRC1_PRIV_4
- RT5665_DRC1_PRIV_5
- RT5665_DRC1_PRIV_6
- RT5665_DRC1_PRIV_7
- RT5665_DRC1_PRIV_8
- RT5665_DUMMY_2
- RT5665_DUMMY_3
- RT5665_EJD_CTRL_1
- RT5665_EJD_CTRL_2
- RT5665_EJD_CTRL_3
- RT5665_EJD_CTRL_4
- RT5665_EJD_CTRL_5
- RT5665_EJD_CTRL_6
- RT5665_EJD_CTRL_7
- RT5665_EMB_JD_EN
- RT5665_EMB_JD_EN_SFT
- RT5665_EQ_AUTO_RCV_CTRL1
- RT5665_EQ_AUTO_RCV_CTRL10
- RT5665_EQ_AUTO_RCV_CTRL11
- RT5665_EQ_AUTO_RCV_CTRL12
- RT5665_EQ_AUTO_RCV_CTRL13
- RT5665_EQ_AUTO_RCV_CTRL2
- RT5665_EQ_AUTO_RCV_CTRL3
- RT5665_EQ_AUTO_RCV_CTRL4
- RT5665_EQ_AUTO_RCV_CTRL5
- RT5665_EQ_AUTO_RCV_CTRL6
- RT5665_EQ_AUTO_RCV_CTRL7
- RT5665_EQ_AUTO_RCV_CTRL8
- RT5665_EQ_AUTO_RCV_CTRL9
- RT5665_EQ_CD_DIS
- RT5665_EQ_CD_EN
- RT5665_EQ_CD_MASK
- RT5665_EQ_CD_SFT
- RT5665_EQ_CTRL_1
- RT5665_EQ_CTRL_2
- RT5665_EQ_DITH_LSB
- RT5665_EQ_DITH_LSB_1
- RT5665_EQ_DITH_LSB_2
- RT5665_EQ_DITH_MASK
- RT5665_EQ_DITH_NOR
- RT5665_EQ_DITH_SFT
- RT5665_EQ_SRC_ADC
- RT5665_EQ_SRC_DAC
- RT5665_EQ_UPD
- RT5665_EQ_UPD_BIT
- RT5665_EXT_JD_DIG
- RT5665_EXT_JD_SRC
- RT5665_EXT_JD_SRC_GPIO_JD1
- RT5665_EXT_JD_SRC_GPIO_JD2
- RT5665_EXT_JD_SRC_JD1_1
- RT5665_EXT_JD_SRC_JD1_2
- RT5665_EXT_JD_SRC_JD2
- RT5665_EXT_JD_SRC_JD3
- RT5665_EXT_JD_SRC_MANUAL
- RT5665_EXT_JD_SRC_SFT
- RT5665_FAST_UPDN_DIS
- RT5665_FAST_UPDN_EN
- RT5665_FAST_UPDN_MASK
- RT5665_FAST_UPDN_SFT
- RT5665_FORMATS
- RT5665_GLB_CLK
- RT5665_GP10_OUT_H
- RT5665_GP10_OUT_L
- RT5665_GP10_OUT_MASK
- RT5665_GP10_PF_IN
- RT5665_GP10_PF_MASK
- RT5665_GP10_PF_OUT
- RT5665_GP10_PIN_ADCDAT1_2
- RT5665_GP10_PIN_GPIO10
- RT5665_GP10_PIN_LPD
- RT5665_GP10_PIN_MASK
- RT5665_GP10_PIN_SFT
- RT5665_GP11_OUT_H
- RT5665_GP11_OUT_L
- RT5665_GP11_OUT_MASK
- RT5665_GP11_PF_IN
- RT5665_GP11_PF_MASK
- RT5665_GP11_PF_OUT
- RT5665_GP1_OUT_H
- RT5665_GP1_OUT_L
- RT5665_GP1_OUT_MASK
- RT5665_GP1_PF_IN
- RT5665_GP1_PF_MASK
- RT5665_GP1_PF_OUT
- RT5665_GP1_PIN_GPIO1
- RT5665_GP1_PIN_IRQ
- RT5665_GP1_PIN_MASK
- RT5665_GP1_PIN_SFT
- RT5665_GP2_OUT_H
- RT5665_GP2_OUT_L
- RT5665_GP2_OUT_MASK
- RT5665_GP2_PF_IN
- RT5665_GP2_PF_MASK
- RT5665_GP2_PF_OUT
- RT5665_GP2_PIN_BCLK2
- RT5665_GP2_PIN_GPIO2
- RT5665_GP2_PIN_MASK
- RT5665_GP2_PIN_PDM_SCL
- RT5665_GP2_PIN_SFT
- RT5665_GP3_OUT_H
- RT5665_GP3_OUT_L
- RT5665_GP3_OUT_MASK
- RT5665_GP3_PF_IN
- RT5665_GP3_PF_MASK
- RT5665_GP3_PF_OUT
- RT5665_GP3_PIN_GPIO3
- RT5665_GP3_PIN_LRCK2
- RT5665_GP3_PIN_MASK
- RT5665_GP3_PIN_PDM_SDA
- RT5665_GP3_PIN_SFT
- RT5665_GP4_OUT_H
- RT5665_GP4_OUT_L
- RT5665_GP4_OUT_MASK
- RT5665_GP4_PF_IN
- RT5665_GP4_PF_MASK
- RT5665_GP4_PF_OUT
- RT5665_GP4_PIN_DACDAT2_1
- RT5665_GP4_PIN_DMIC1_SDA
- RT5665_GP4_PIN_GPIO4
- RT5665_GP4_PIN_MASK
- RT5665_GP4_PIN_SFT
- RT5665_GP5_OUT_H
- RT5665_GP5_OUT_L
- RT5665_GP5_OUT_MASK
- RT5665_GP5_PF_IN
- RT5665_GP5_PF_MASK
- RT5665_GP5_PF_OUT
- RT5665_GP5_PIN_ADCDAT2_1
- RT5665_GP5_PIN_DMIC2_SDA
- RT5665_GP5_PIN_GPIO5
- RT5665_GP5_PIN_MASK
- RT5665_GP5_PIN_SFT
- RT5665_GP6_OUT_H
- RT5665_GP6_OUT_L
- RT5665_GP6_OUT_MASK
- RT5665_GP6_PF_IN
- RT5665_GP6_PF_MASK
- RT5665_GP6_PF_OUT
- RT5665_GP6_PIN_BCLK3
- RT5665_GP6_PIN_GPIO6
- RT5665_GP6_PIN_MASK
- RT5665_GP6_PIN_PDM_SCL
- RT5665_GP6_PIN_SFT
- RT5665_GP7_OUT_H
- RT5665_GP7_OUT_L
- RT5665_GP7_OUT_MASK
- RT5665_GP7_PF_IN
- RT5665_GP7_PF_MASK
- RT5665_GP7_PF_OUT
- RT5665_GP7_PIN_GPIO7
- RT5665_GP7_PIN_LRCK3
- RT5665_GP7_PIN_MASK
- RT5665_GP7_PIN_PDM_SDA
- RT5665_GP7_PIN_SFT
- RT5665_GP8_OUT_H
- RT5665_GP8_OUT_L
- RT5665_GP8_OUT_MASK
- RT5665_GP8_PF_IN
- RT5665_GP8_PF_MASK
- RT5665_GP8_PF_OUT
- RT5665_GP8_PIN_DACDAT2_2
- RT5665_GP8_PIN_DACDAT3
- RT5665_GP8_PIN_DMIC2_SCL
- RT5665_GP8_PIN_GPIO8
- RT5665_GP8_PIN_MASK
- RT5665_GP8_PIN_SFT
- RT5665_GP9_OUT_H
- RT5665_GP9_OUT_L
- RT5665_GP9_OUT_MASK
- RT5665_GP9_PF_IN
- RT5665_GP9_PF_MASK
- RT5665_GP9_PF_OUT
- RT5665_GP9_PIN_ADCDAT2_2
- RT5665_GP9_PIN_ADCDAT3
- RT5665_GP9_PIN_DMIC1_SCL
- RT5665_GP9_PIN_GPIO9
- RT5665_GP9_PIN_MASK
- RT5665_GP9_PIN_SFT
- RT5665_GPIO_CTRL_1
- RT5665_GPIO_CTRL_2
- RT5665_GPIO_CTRL_3
- RT5665_GPIO_CTRL_4
- RT5665_GPIO_STA
- RT5665_G_BST1_OM_L_MASK
- RT5665_G_BST1_OM_L_SFT
- RT5665_G_BST2_OM_L_MASK
- RT5665_G_BST2_OM_L_SFT
- RT5665_G_BST3_OM_L_MASK
- RT5665_G_BST3_OM_L_SFT
- RT5665_G_DAC_L1_MONO_L_MASK
- RT5665_G_DAC_L1_MONO_L_SFT
- RT5665_G_DAC_L1_MONO_R_MASK
- RT5665_G_DAC_L1_MONO_R_SFT
- RT5665_G_DAC_L1_STO2_L_MASK
- RT5665_G_DAC_L1_STO2_L_SFT
- RT5665_G_DAC_L1_STO_L_MASK
- RT5665_G_DAC_L1_STO_L_SFT
- RT5665_G_DAC_L1_STO_R_MASK
- RT5665_G_DAC_L1_STO_R_SFT
- RT5665_G_DAC_L2_MONO_L_MASK
- RT5665_G_DAC_L2_MONO_L_SFT
- RT5665_G_DAC_L2_MONO_R_MASK
- RT5665_G_DAC_L2_MONO_R_SFT
- RT5665_G_DAC_L2_OM_L_MASK
- RT5665_G_DAC_L2_OM_L_SFT
- RT5665_G_DAC_L2_STO2_L_MASK
- RT5665_G_DAC_L2_STO2_L_SFT
- RT5665_G_DAC_L2_STO_L_MASK
- RT5665_G_DAC_L2_STO_L_SFT
- RT5665_G_DAC_L2_STO_R_MASK
- RT5665_G_DAC_L2_STO_R_SFT
- RT5665_G_DAC_L3_STO2_L_MASK
- RT5665_G_DAC_L3_STO2_L_SFT
- RT5665_G_DAC_R1_MONO_L_MASK
- RT5665_G_DAC_R1_MONO_L_SFT
- RT5665_G_DAC_R1_MONO_R_MASK
- RT5665_G_DAC_R1_MONO_R_SFT
- RT5665_G_DAC_R1_STO2_R_MASK
- RT5665_G_DAC_R1_STO2_R_SFT
- RT5665_G_DAC_R1_STO_L_MASK
- RT5665_G_DAC_R1_STO_L_SFT
- RT5665_G_DAC_R1_STO_R_MASK
- RT5665_G_DAC_R1_STO_R_SFT
- RT5665_G_DAC_R2_MONO_L_MASK
- RT5665_G_DAC_R2_MONO_L_SFT
- RT5665_G_DAC_R2_MONO_R_MASK
- RT5665_G_DAC_R2_MONO_R_SFT
- RT5665_G_DAC_R2_STO2_R_MASK
- RT5665_G_DAC_R2_STO2_R_SFT
- RT5665_G_DAC_R2_STO_L_MASK
- RT5665_G_DAC_R2_STO_L_SFT
- RT5665_G_DAC_R2_STO_R_MASK
- RT5665_G_DAC_R2_STO_R_SFT
- RT5665_G_DAC_R3_STO2_R_MASK
- RT5665_G_DAC_R3_STO2_R_SFT
- RT5665_G_HP
- RT5665_G_HP_SFT
- RT5665_G_IN_L_OM_L_MASK
- RT5665_G_IN_L_OM_L_SFT
- RT5665_G_MONOVOL_MA
- RT5665_G_MONOVOL_MA_SFT
- RT5665_G_STO_DA_DMIX
- RT5665_G_STO_DA_SFT
- RT5665_HPF_CTRL1
- RT5665_HPL_GAIN
- RT5665_HPR_GAIN
- RT5665_HP_AMP_DET_CTRL_1
- RT5665_HP_AMP_DET_CTRL_2
- RT5665_HP_CALIB_CTRL_1
- RT5665_HP_CALIB_CTRL_10
- RT5665_HP_CALIB_CTRL_11
- RT5665_HP_CALIB_CTRL_2
- RT5665_HP_CALIB_CTRL_3
- RT5665_HP_CALIB_CTRL_4
- RT5665_HP_CALIB_CTRL_5
- RT5665_HP_CALIB_CTRL_6
- RT5665_HP_CALIB_CTRL_7
- RT5665_HP_CALIB_CTRL_9
- RT5665_HP_CALIB_STA_1
- RT5665_HP_CALIB_STA_10
- RT5665_HP_CALIB_STA_11
- RT5665_HP_CALIB_STA_2
- RT5665_HP_CALIB_STA_3
- RT5665_HP_CALIB_STA_4
- RT5665_HP_CALIB_STA_5
- RT5665_HP_CALIB_STA_6
- RT5665_HP_CALIB_STA_7
- RT5665_HP_CALIB_STA_8
- RT5665_HP_CALIB_STA_9
- RT5665_HP_CHARGE_PUMP_1
- RT5665_HP_CHARGE_PUMP_2
- RT5665_HP_CLK_DET
- RT5665_HP_CTRL_1
- RT5665_HP_CTRL_2
- RT5665_HP_DRIVER_1X
- RT5665_HP_DRIVER_3X
- RT5665_HP_DRIVER_5X
- RT5665_HP_DRIVER_MASK
- RT5665_HP_IMP_GAIN_1
- RT5665_HP_IMP_GAIN_2
- RT5665_HP_IMP_SENS_CTRL_01
- RT5665_HP_IMP_SENS_CTRL_02
- RT5665_HP_IMP_SENS_CTRL_03
- RT5665_HP_IMP_SENS_CTRL_04
- RT5665_HP_IMP_SENS_CTRL_05
- RT5665_HP_IMP_SENS_CTRL_06
- RT5665_HP_IMP_SENS_CTRL_07
- RT5665_HP_IMP_SENS_CTRL_08
- RT5665_HP_IMP_SENS_CTRL_09
- RT5665_HP_IMP_SENS_CTRL_10
- RT5665_HP_IMP_SENS_CTRL_11
- RT5665_HP_IMP_SENS_CTRL_12
- RT5665_HP_IMP_SENS_CTRL_13
- RT5665_HP_IMP_SENS_CTRL_14
- RT5665_HP_IMP_SENS_CTRL_15
- RT5665_HP_IMP_SENS_CTRL_16
- RT5665_HP_IMP_SENS_CTRL_17
- RT5665_HP_IMP_SENS_CTRL_18
- RT5665_HP_IMP_SENS_CTRL_19
- RT5665_HP_IMP_SENS_CTRL_20
- RT5665_HP_IMP_SENS_CTRL_21
- RT5665_HP_IMP_SENS_CTRL_22
- RT5665_HP_IMP_SENS_CTRL_23
- RT5665_HP_IMP_SENS_CTRL_24
- RT5665_HP_IMP_SENS_CTRL_25
- RT5665_HP_IMP_SENS_CTRL_26
- RT5665_HP_IMP_SENS_CTRL_27
- RT5665_HP_IMP_SENS_CTRL_28
- RT5665_HP_IMP_SENS_CTRL_29
- RT5665_HP_IMP_SENS_CTRL_30
- RT5665_HP_IMP_SENS_CTRL_31
- RT5665_HP_IMP_SENS_CTRL_32
- RT5665_HP_IMP_SENS_CTRL_33
- RT5665_HP_IMP_SENS_CTRL_34
- RT5665_HP_LOGIC_CTRL_1
- RT5665_HP_LOGIC_CTRL_2
- RT5665_HP_LOGIC_CTRL_3
- RT5665_HP_SV_DIS
- RT5665_HP_SV_EN
- RT5665_HP_SV_MASK
- RT5665_HP_SV_SFT
- RT5665_I2C_MODE
- RT5665_I2S1_1_DS_ADC_SLOT01_SFT
- RT5665_I2S1_1_DS_ADC_SLOT23_SFT
- RT5665_I2S1_1_DS_ADC_SLOT45_SFT
- RT5665_I2S1_1_DS_ADC_SLOT67_SFT
- RT5665_I2S1_2_DS_ADC_SLOT01_SFT
- RT5665_I2S1_2_DS_ADC_SLOT23_SFT
- RT5665_I2S1_2_DS_ADC_SLOT45_SFT
- RT5665_I2S1_2_DS_ADC_SLOT67_SFT
- RT5665_I2S1_ASRC_MASK
- RT5665_I2S1_ASRC_SFT
- RT5665_I2S1_F_DIV_CTRL_1
- RT5665_I2S1_F_DIV_CTRL_2
- RT5665_I2S1_MODE_I2S
- RT5665_I2S1_MODE_MASK
- RT5665_I2S1_MODE_TDM
- RT5665_I2S1_RATE_MASK
- RT5665_I2S1_RATE_SFT
- RT5665_I2S1_SDP
- RT5665_I2S2_ASRC_MASK
- RT5665_I2S2_ASRC_SFT
- RT5665_I2S2_F_DIV_CTRL_1
- RT5665_I2S2_F_DIV_CTRL_2
- RT5665_I2S2_M_PD_MASK
- RT5665_I2S2_M_PD_SFT
- RT5665_I2S2_RATE_MASK
- RT5665_I2S2_RATE_SFT
- RT5665_I2S2_SDP
- RT5665_I2S2_SRC_MASK
- RT5665_I2S2_SRC_SFT
- RT5665_I2S3_ASRC_MASK
- RT5665_I2S3_ASRC_SFT
- RT5665_I2S3_F_DIV_CTRL_1
- RT5665_I2S3_F_DIV_CTRL_2
- RT5665_I2S3_M_PD_MASK
- RT5665_I2S3_M_PD_SFT
- RT5665_I2S3_RATE_MASK
- RT5665_I2S3_RATE_SFT
- RT5665_I2S3_SDP
- RT5665_I2S3_SRC_MASK
- RT5665_I2S3_SRC_SFT
- RT5665_I2S_BCLK_MS2_32
- RT5665_I2S_BCLK_MS2_64
- RT5665_I2S_BCLK_MS2_MASK
- RT5665_I2S_BCLK_MS2_SFT
- RT5665_I2S_BCLK_MS3_32
- RT5665_I2S_BCLK_MS3_64
- RT5665_I2S_BCLK_MS3_MASK
- RT5665_I2S_BCLK_MS3_SFT
- RT5665_I2S_BP_INV
- RT5665_I2S_BP_MASK
- RT5665_I2S_BP_NOR
- RT5665_I2S_BP_SFT
- RT5665_I2S_CLK_SEL_MASK
- RT5665_I2S_CLK_SEL_SFT
- RT5665_I2S_CLK_SRC_MASK
- RT5665_I2S_CLK_SRC_MCLK
- RT5665_I2S_CLK_SRC_PLL1
- RT5665_I2S_CLK_SRC_RCCLK
- RT5665_I2S_CLK_SRC_SFT
- RT5665_I2S_DF_I2S
- RT5665_I2S_DF_LEFT
- RT5665_I2S_DF_MASK
- RT5665_I2S_DF_PCM_A
- RT5665_I2S_DF_PCM_A_N
- RT5665_I2S_DF_PCM_B
- RT5665_I2S_DF_PCM_B_N
- RT5665_I2S_DF_SFT
- RT5665_I2S_DL_16
- RT5665_I2S_DL_20
- RT5665_I2S_DL_24
- RT5665_I2S_DL_8
- RT5665_I2S_DL_MASK
- RT5665_I2S_DL_SFT
- RT5665_I2S_MS_M
- RT5665_I2S_MS_MASK
- RT5665_I2S_MS_S
- RT5665_I2S_MS_SFT
- RT5665_I2S_M_CLK_CTRL_1
- RT5665_I2S_M_PD2_1
- RT5665_I2S_M_PD2_12
- RT5665_I2S_M_PD2_16
- RT5665_I2S_M_PD2_2
- RT5665_I2S_M_PD2_3
- RT5665_I2S_M_PD2_4
- RT5665_I2S_M_PD2_6
- RT5665_I2S_M_PD2_8
- RT5665_I2S_M_PD2_MASK
- RT5665_I2S_M_PD2_SFT
- RT5665_I2S_PD1_1
- RT5665_I2S_PD1_12
- RT5665_I2S_PD1_16
- RT5665_I2S_PD1_2
- RT5665_I2S_PD1_3
- RT5665_I2S_PD1_4
- RT5665_I2S_PD1_6
- RT5665_I2S_PD1_8
- RT5665_I2S_PD1_MASK
- RT5665_I2S_PD1_SFT
- RT5665_I2S_PD2_1
- RT5665_I2S_PD2_12
- RT5665_I2S_PD2_16
- RT5665_I2S_PD2_2
- RT5665_I2S_PD2_3
- RT5665_I2S_PD2_4
- RT5665_I2S_PD2_6
- RT5665_I2S_PD2_8
- RT5665_I2S_PD2_MASK
- RT5665_I2S_PD2_SFT
- RT5665_I2S_PD3_1
- RT5665_I2S_PD3_12
- RT5665_I2S_PD3_16
- RT5665_I2S_PD3_2
- RT5665_I2S_PD3_3
- RT5665_I2S_PD3_4
- RT5665_I2S_PD3_6
- RT5665_I2S_PD3_8
- RT5665_I2S_PD3_MASK
- RT5665_I2S_PD3_SFT
- RT5665_I2S_PD4_1
- RT5665_I2S_PD4_12
- RT5665_I2S_PD4_16
- RT5665_I2S_PD4_2
- RT5665_I2S_PD4_3
- RT5665_I2S_PD4_4
- RT5665_I2S_PD4_6
- RT5665_I2S_PD4_8
- RT5665_I2S_PD4_MASK
- RT5665_I2S_PD4_SFT
- RT5665_I2S_PD_1
- RT5665_I2S_PD_12
- RT5665_I2S_PD_16
- RT5665_I2S_PD_2
- RT5665_I2S_PD_3
- RT5665_I2S_PD_4
- RT5665_I2S_PD_6
- RT5665_I2S_PD_8
- RT5665_I2S_PIN_CFG_MASK
- RT5665_I2S_PIN_CFG_SFT
- RT5665_IB_HP_125IL
- RT5665_IB_HP_1IL
- RT5665_IB_HP_25IL
- RT5665_IB_HP_5IL
- RT5665_IB_HP_MASK
- RT5665_IB_HP_SFT
- RT5665_IF1_ADC1_SEL_SFT
- RT5665_IF1_ADC2_SEL_SFT
- RT5665_IF1_ADC3_SEL_SFT
- RT5665_IF1_ADC4_SEL_SFT
- RT5665_IF2_1_ADC_IN_MASK
- RT5665_IF2_1_ADC_IN_SFT
- RT5665_IF2_1_ADC_SEL_MASK
- RT5665_IF2_1_ADC_SEL_SFT
- RT5665_IF2_1_DAC_SEL_MASK
- RT5665_IF2_1_DAC_SEL_SFT
- RT5665_IF2_2_ADC_IN_MASK
- RT5665_IF2_2_ADC_IN_SFT
- RT5665_IF2_2_ADC_SEL_MASK
- RT5665_IF2_2_ADC_SEL_SFT
- RT5665_IF2_2_DAC_SEL_MASK
- RT5665_IF2_2_DAC_SEL_SFT
- RT5665_IF3_ADC_IN_MASK
- RT5665_IF3_ADC_IN_SFT
- RT5665_IF3_ADC_SEL_MASK
- RT5665_IF3_ADC_SEL_SFT
- RT5665_IF3_DAC_SEL_MASK
- RT5665_IF3_DAC_SEL_SFT
- RT5665_IL_CMD_1
- RT5665_IL_CMD_2
- RT5665_IL_CMD_3
- RT5665_IL_CMD_4
- RT5665_IL_IRQ_DIS
- RT5665_IL_IRQ_EN
- RT5665_IL_IRQ_MASK
- RT5665_IN1_DF
- RT5665_IN1_DF_MASK
- RT5665_IN1_IN2
- RT5665_IN2_DF
- RT5665_IN2_DF_MASK
- RT5665_IN3_DF
- RT5665_IN3_DF_MASK
- RT5665_IN3_IN4
- RT5665_IN4_DF
- RT5665_IN4_DF_MASK
- RT5665_INL1_INR1_VOL
- RT5665_INL_VOL_MASK
- RT5665_INL_VOL_SFT
- RT5665_INR_VOL_MASK
- RT5665_INR_VOL_SFT
- RT5665_INT_ST_1
- RT5665_IRQ_CTRL_1
- RT5665_IRQ_CTRL_2
- RT5665_IRQ_CTRL_3
- RT5665_IRQ_CTRL_4
- RT5665_IRQ_CTRL_5
- RT5665_IRQ_CTRL_6
- RT5665_IRQ_JD_EN
- RT5665_IRQ_JD_EN_SFT
- RT5665_JD1
- RT5665_JD1_1_DIS
- RT5665_JD1_1_EN
- RT5665_JD1_1_EN_MASK
- RT5665_JD1_1_EN_SFT
- RT5665_JD1_2_DIS
- RT5665_JD1_2_EN
- RT5665_JD1_2_EN_MASK
- RT5665_JD1_2_EN_SFT
- RT5665_JD1_MODE_0
- RT5665_JD1_MODE_1
- RT5665_JD1_MODE_2
- RT5665_JD1_MODE_MASK
- RT5665_JD1_THD
- RT5665_JD2_THD
- RT5665_JD_CTRL_1
- RT5665_JD_CTRL_2
- RT5665_JD_CTRL_3
- RT5665_JD_HPO_GPIO_JD1
- RT5665_JD_HPO_GPIO_JD2
- RT5665_JD_HPO_JD1_1
- RT5665_JD_HPO_JD1_2
- RT5665_JD_HPO_JD2
- RT5665_JD_HPO_JD3
- RT5665_JD_HPO_JD_D
- RT5665_JD_MODE
- RT5665_JD_MODE_SFT
- RT5665_JD_NULL
- RT5665_JD_TRI_HPO_SEL_MASK
- RT5665_JD_TRI_HPO_SEL_SFT
- RT5665_LDO1_DVO_09
- RT5665_LDO1_DVO_10
- RT5665_LDO1_DVO_12
- RT5665_LDO1_DVO_14
- RT5665_LDO1_DVO_MASK
- RT5665_LOUT
- RT5665_LOUT_BST_SFT
- RT5665_LOUT_CLK_DET
- RT5665_LOUT_DF
- RT5665_LOUT_DF_SFT
- RT5665_LOUT_MIXER
- RT5665_LOW_HP_AMP_DET
- RT5665_LRCK_PDM_PI2C
- RT5665_L_EQ_BPF1_A1
- RT5665_L_EQ_BPF1_A2
- RT5665_L_EQ_BPF1_H0
- RT5665_L_EQ_BPF2_A1
- RT5665_L_EQ_BPF2_A2
- RT5665_L_EQ_BPF2_H0
- RT5665_L_EQ_BPF3_A1
- RT5665_L_EQ_BPF3_A2
- RT5665_L_EQ_BPF3_H0
- RT5665_L_EQ_BPF4_A1
- RT5665_L_EQ_BPF4_A2
- RT5665_L_EQ_BPF4_H0
- RT5665_L_EQ_HPF1_A1
- RT5665_L_EQ_HPF1_H0
- RT5665_L_EQ_LPF1_H0
- RT5665_L_EQ_POST_VOL
- RT5665_L_EQ_PRE_VOL
- RT5665_L_MUTE
- RT5665_L_MUTE_SFT
- RT5665_L_VOL_MASK
- RT5665_L_VOL_SFT
- RT5665_MB1_PATH_MASK
- RT5665_MB2_PATH_MASK
- RT5665_MIC1_BS_75AV
- RT5665_MIC1_BS_9AV
- RT5665_MIC1_BS_MASK
- RT5665_MIC1_BS_SFT
- RT5665_MIC1_CLK_DIS
- RT5665_MIC1_CLK_EN
- RT5665_MIC1_CLK_MASK
- RT5665_MIC1_CLK_SFT
- RT5665_MIC1_OVCD_DIS
- RT5665_MIC1_OVCD_EN
- RT5665_MIC1_OVCD_MASK
- RT5665_MIC1_OVCD_SFT
- RT5665_MIC1_OVTH_1500UA
- RT5665_MIC1_OVTH_2000UA
- RT5665_MIC1_OVTH_600UA
- RT5665_MIC1_OVTH_MASK
- RT5665_MIC1_OVTH_SFT
- RT5665_MIC2_BS_75AV
- RT5665_MIC2_BS_9AV
- RT5665_MIC2_BS_MASK
- RT5665_MIC2_BS_SFT
- RT5665_MIC2_CLK_DIS
- RT5665_MIC2_CLK_EN
- RT5665_MIC2_CLK_MASK
- RT5665_MIC2_CLK_SFT
- RT5665_MIC2_OVCD_DIS
- RT5665_MIC2_OVCD_EN
- RT5665_MIC2_OVCD_MASK
- RT5665_MIC2_OVCD_SFT
- RT5665_MIC2_OVTH_1500UA
- RT5665_MIC2_OVTH_2000UA
- RT5665_MIC2_OVTH_600UA
- RT5665_MIC2_OVTH_MASK
- RT5665_MIC2_OVTH_SFT
- RT5665_MICBIAS_1
- RT5665_MICBIAS_2
- RT5665_MID_HP_AMP_DET
- RT5665_MONOL_DAC_SIL_DET
- RT5665_MONOMIX_GAIN
- RT5665_MONOMIX_IN_GAIN
- RT5665_MONOR_DAC_SIL_DET
- RT5665_MONO_ADC_BOOST
- RT5665_MONO_ADC_DIG_VOL
- RT5665_MONO_ADC_L1_SRC_MASK
- RT5665_MONO_ADC_L1_SRC_SFT
- RT5665_MONO_ADC_L2_SRC_MASK
- RT5665_MONO_ADC_L2_SRC_SFT
- RT5665_MONO_ADC_L_BST_MASK
- RT5665_MONO_ADC_L_BST_SFT
- RT5665_MONO_ADC_L_SRC_MASK
- RT5665_MONO_ADC_L_SRC_SFT
- RT5665_MONO_ADC_L_VOL_MASK
- RT5665_MONO_ADC_L_VOL_SFT
- RT5665_MONO_ADC_MIXER
- RT5665_MONO_ADC_R1_SRC_MASK
- RT5665_MONO_ADC_R1_SRC_SFT
- RT5665_MONO_ADC_R2_SRC_MASK
- RT5665_MONO_ADC_R2_SRC_SFT
- RT5665_MONO_ADC_R_BST_MASK
- RT5665_MONO_ADC_R_BST_SFT
- RT5665_MONO_ADC_R_SRC_MASK
- RT5665_MONO_ADC_R_SRC_SFT
- RT5665_MONO_ADC_R_VOL_MASK
- RT5665_MONO_ADC_R_VOL_SFT
- RT5665_MONO_AMP_CALIB_CTRL_1
- RT5665_MONO_AMP_CALIB_CTRL_2
- RT5665_MONO_AMP_CALIB_CTRL_3
- RT5665_MONO_AMP_CALIB_CTRL_4
- RT5665_MONO_AMP_CALIB_CTRL_5
- RT5665_MONO_AMP_CALIB_CTRL_6
- RT5665_MONO_AMP_CALIB_CTRL_7
- RT5665_MONO_AMP_CALIB_STA1
- RT5665_MONO_AMP_CALIB_STA2
- RT5665_MONO_AMP_CALIB_STA3
- RT5665_MONO_AMP_CALIB_STA4
- RT5665_MONO_AMP_CALIB_STA6
- RT5665_MONO_CLK_DET
- RT5665_MONO_DAC_MIXER
- RT5665_MONO_DD_L_SRC_MASK
- RT5665_MONO_DD_L_SRC_SFT
- RT5665_MONO_DD_R_SRC_MASK
- RT5665_MONO_DD_R_SRC_SFT
- RT5665_MONO_DMIC_L_SRC_MASK
- RT5665_MONO_DMIC_L_SRC_SFT
- RT5665_MONO_DMIC_R_SRC_MASK
- RT5665_MONO_DMIC_R_SRC_SFT
- RT5665_MONO_GAIN
- RT5665_MONO_NG2_CTRL_1
- RT5665_MONO_NG2_CTRL_2
- RT5665_MONO_NG2_CTRL_3
- RT5665_MONO_NG2_CTRL_4
- RT5665_MONO_NG2_CTRL_5
- RT5665_MONO_NG2_CTRL_6
- RT5665_MONO_OUT
- RT5665_MRES_15MO
- RT5665_MRES_25MO
- RT5665_MRES_35MO
- RT5665_MRES_45MO
- RT5665_MRES_MASK
- RT5665_MRES_SFT
- RT5665_M_ADCMIX_L
- RT5665_M_ADCMIX_L_SFT
- RT5665_M_ADCMIX_R
- RT5665_M_ADCMIX_R_SFT
- RT5665_M_AEC_REF_RM1_R
- RT5665_M_AEC_REF_RM1_R_SFT
- RT5665_M_BST1_MM
- RT5665_M_BST1_MM_SFT
- RT5665_M_BST1_OM_L
- RT5665_M_BST1_OM_L_SFT
- RT5665_M_BST1_RM1_L
- RT5665_M_BST1_RM1_L_SFT
- RT5665_M_BST1_RM1_R
- RT5665_M_BST1_RM1_R_SFT
- RT5665_M_BST1_RM2_L
- RT5665_M_BST1_RM2_L_SFT
- RT5665_M_BST1_RM2_R
- RT5665_M_BST1_RM2_R_SFT
- RT5665_M_BST1_SM_L
- RT5665_M_BST1_SM_L_SFT
- RT5665_M_BST2_MM
- RT5665_M_BST2_MM_SFT
- RT5665_M_BST2_OM_L
- RT5665_M_BST2_OM_L_SFT
- RT5665_M_BST2_OM_R
- RT5665_M_BST2_OM_R_SFT
- RT5665_M_BST2_RM1_L
- RT5665_M_BST2_RM1_L_SFT
- RT5665_M_BST2_RM1_R
- RT5665_M_BST2_RM1_R_SFT
- RT5665_M_BST2_RM2_L
- RT5665_M_BST2_RM2_L_SFT
- RT5665_M_BST2_RM2_R
- RT5665_M_BST2_RM2_R_SFT
- RT5665_M_BST3_MM
- RT5665_M_BST3_MM_SFT
- RT5665_M_BST3_OM_L
- RT5665_M_BST3_OM_L_SFT
- RT5665_M_BST3_OM_R
- RT5665_M_BST3_OM_R_SFT
- RT5665_M_BST3_RM1_L
- RT5665_M_BST3_RM1_L_SFT
- RT5665_M_BST3_RM1_R
- RT5665_M_BST3_RM1_R_SFT
- RT5665_M_BST3_RM2_L
- RT5665_M_BST3_RM2_L_SFT
- RT5665_M_BST3_RM2_R
- RT5665_M_BST3_RM2_R_SFT
- RT5665_M_BST3_SM_L
- RT5665_M_BST3_SM_L_SFT
- RT5665_M_BST3_SM_R
- RT5665_M_BST3_SM_R_SFT
- RT5665_M_BST4_OM_R
- RT5665_M_BST4_OM_R_SFT
- RT5665_M_BST4_RM1_L
- RT5665_M_BST4_RM1_L_SFT
- RT5665_M_BST4_RM1_R
- RT5665_M_BST4_RM1_R_SFT
- RT5665_M_BST4_RM2_L
- RT5665_M_BST4_RM2_L_SFT
- RT5665_M_BST4_RM2_R
- RT5665_M_BST4_RM2_R_SFT
- RT5665_M_BST4_SM_R
- RT5665_M_BST4_SM_R_SFT
- RT5665_M_CBJ_RM1_L
- RT5665_M_CBJ_RM1_L_SFT
- RT5665_M_CBJ_RM2_L
- RT5665_M_CBJ_RM2_L_SFT
- RT5665_M_DAC1_L
- RT5665_M_DAC1_L_SFT
- RT5665_M_DAC1_R
- RT5665_M_DAC1_R_SFT
- RT5665_M_DAC2_L_VOL
- RT5665_M_DAC2_L_VOL_SFT
- RT5665_M_DAC2_R_VOL
- RT5665_M_DAC2_R_VOL_SFT
- RT5665_M_DAC3_L_VOL
- RT5665_M_DAC3_L_VOL_SFT
- RT5665_M_DAC3_R_VOL
- RT5665_M_DAC3_R_VOL_SFT
- RT5665_M_DAC_L1_MONO_L
- RT5665_M_DAC_L1_MONO_L_SFT
- RT5665_M_DAC_L1_MONO_R
- RT5665_M_DAC_L1_MONO_R_SFT
- RT5665_M_DAC_L1_STO2_L
- RT5665_M_DAC_L1_STO2_L_SFT
- RT5665_M_DAC_L1_STO_L
- RT5665_M_DAC_L1_STO_L_SFT
- RT5665_M_DAC_L1_STO_R
- RT5665_M_DAC_L1_STO_R_SFT
- RT5665_M_DAC_L2_LM
- RT5665_M_DAC_L2_LM_SFT
- RT5665_M_DAC_L2_MA
- RT5665_M_DAC_L2_MA_SFT
- RT5665_M_DAC_L2_MM
- RT5665_M_DAC_L2_MM_SFT
- RT5665_M_DAC_L2_MONO_L
- RT5665_M_DAC_L2_MONO_L_SFT
- RT5665_M_DAC_L2_MONO_R
- RT5665_M_DAC_L2_MONO_R_SFT
- RT5665_M_DAC_L2_OM_L
- RT5665_M_DAC_L2_OM_L_SFT
- RT5665_M_DAC_L2_SM_L
- RT5665_M_DAC_L2_SM_L_SFT
- RT5665_M_DAC_L2_SPKOMIX
- RT5665_M_DAC_L2_SPKOMIX_SFT
- RT5665_M_DAC_L2_STO2_L
- RT5665_M_DAC_L2_STO2_L_SFT
- RT5665_M_DAC_L2_STO_L
- RT5665_M_DAC_L2_STO_L_SFT
- RT5665_M_DAC_L2_STO_R
- RT5665_M_DAC_L2_STO_R_SFT
- RT5665_M_DAC_L3_STO2_L
- RT5665_M_DAC_L3_STO2_L_SFT
- RT5665_M_DAC_R1_MONO_L
- RT5665_M_DAC_R1_MONO_L_SFT
- RT5665_M_DAC_R1_MONO_R
- RT5665_M_DAC_R1_MONO_R_SFT
- RT5665_M_DAC_R1_STO2_R
- RT5665_M_DAC_R1_STO2_R_SFT
- RT5665_M_DAC_R1_STO_L
- RT5665_M_DAC_R1_STO_L_SFT
- RT5665_M_DAC_R1_STO_R
- RT5665_M_DAC_R1_STO_R_SFT
- RT5665_M_DAC_R2_LM
- RT5665_M_DAC_R2_LM_SFT
- RT5665_M_DAC_R2_MONO_L
- RT5665_M_DAC_R2_MONO_L_SFT
- RT5665_M_DAC_R2_MONO_R
- RT5665_M_DAC_R2_MONO_R_SFT
- RT5665_M_DAC_R2_OM_R
- RT5665_M_DAC_R2_OM_R_SFT
- RT5665_M_DAC_R2_SM_R
- RT5665_M_DAC_R2_SM_R_SFT
- RT5665_M_DAC_R2_SPKOMIX
- RT5665_M_DAC_R2_SPKOMIX_SFT
- RT5665_M_DAC_R2_STO2_R
- RT5665_M_DAC_R2_STO2_R_SFT
- RT5665_M_DAC_R2_STO_L
- RT5665_M_DAC_R2_STO_L_SFT
- RT5665_M_DAC_R2_STO_R
- RT5665_M_DAC_R2_STO_R_SFT
- RT5665_M_DAC_R3_STO2_R
- RT5665_M_DAC_R3_STO2_R_SFT
- RT5665_M_INL_RM1_L
- RT5665_M_INL_RM1_L_SFT
- RT5665_M_INL_RM2_L
- RT5665_M_INL_RM2_L_SFT
- RT5665_M_INL_RM2_R
- RT5665_M_INL_RM2_R_SFT
- RT5665_M_INR_RM1_L
- RT5665_M_INR_RM1_L_SFT
- RT5665_M_INR_RM1_R
- RT5665_M_INR_RM1_R_SFT
- RT5665_M_INR_RM2_L
- RT5665_M_INR_RM2_L_SFT
- RT5665_M_INR_RM2_R
- RT5665_M_INR_RM2_R_SFT
- RT5665_M_IN_L_OM_L
- RT5665_M_IN_L_OM_L_SFT
- RT5665_M_IN_L_SM_L
- RT5665_M_IN_L_SM_L_SFT
- RT5665_M_IN_L_SM_R
- RT5665_M_IN_L_SM_R_SFT
- RT5665_M_IN_R_OM_R
- RT5665_M_IN_R_OM_R_SFT
- RT5665_M_IN_R_SM_L
- RT5665_M_IN_R_SM_L_SFT
- RT5665_M_IN_R_SM_R
- RT5665_M_IN_R_SM_R_SFT
- RT5665_M_MONOVOL_MA
- RT5665_M_MONOVOL_MA_SFT
- RT5665_M_MONOVOL_RM1_R
- RT5665_M_MONOVOL_RM1_R_SFT
- RT5665_M_MONOVOL_RM2_R
- RT5665_M_MONOVOL_RM2_R_SFT
- RT5665_M_MONO_ADC_L1
- RT5665_M_MONO_ADC_L1_SFT
- RT5665_M_MONO_ADC_L2
- RT5665_M_MONO_ADC_L2_SFT
- RT5665_M_MONO_ADC_R1
- RT5665_M_MONO_ADC_R1_SFT
- RT5665_M_MONO_ADC_R2
- RT5665_M_MONO_ADC_R2_SFT
- RT5665_M_OV_L_LM
- RT5665_M_OV_L_LM_SFT
- RT5665_M_OV_R_LM
- RT5665_M_OV_R_LM_SFT
- RT5665_M_PDM1_L
- RT5665_M_PDM1_L_SFT
- RT5665_M_PDM1_R
- RT5665_M_PDM1_R_SFT
- RT5665_M_RECMIC2L_MM
- RT5665_M_RECMIC2L_MM_SFT
- RT5665_M_RF_DIG_MASK
- RT5665_M_RF_DIG_SFT
- RT5665_M_RI_DIG
- RT5665_M_SPKVOLL_SPKOMIX
- RT5665_M_SPKVOLL_SPKOMIX_SFT
- RT5665_M_SPKVOLR_SPKOMIX
- RT5665_M_SPKVOLR_SPKOMIX_SFT
- RT5665_M_STO1_ADC_L1
- RT5665_M_STO1_ADC_L1_SFT
- RT5665_M_STO1_ADC_L2
- RT5665_M_STO1_ADC_L2_SFT
- RT5665_M_STO1_ADC_R1
- RT5665_M_STO1_ADC_R1_SFT
- RT5665_M_STO1_ADC_R2
- RT5665_M_STO1_ADC_R2_SFT
- RT5665_M_STO2_ADC_L1
- RT5665_M_STO2_ADC_L1_SFT
- RT5665_M_STO2_ADC_L1_UN
- RT5665_M_STO2_ADC_L2
- RT5665_M_STO2_ADC_L2_SFT
- RT5665_M_STO2_ADC_R1
- RT5665_M_STO2_ADC_R1_SFT
- RT5665_M_STO2_ADC_R1_UN
- RT5665_M_STO2_ADC_R2
- RT5665_M_STO2_ADC_R2_SFT
- RT5665_M_ST_DAC_L1
- RT5665_M_ST_DAC_L1_SFT
- RT5665_M_ST_DAC_R1
- RT5665_M_ST_DAC_R1_SFT
- RT5665_NG2_DIS
- RT5665_NG2_EN
- RT5665_NG2_EN_MASK
- RT5665_NUM_SUPPLIES
- RT5665_OSW_L_DIS
- RT5665_OSW_L_EN
- RT5665_OSW_L_MASK
- RT5665_OSW_L_SFT
- RT5665_OSW_R_DIS
- RT5665_OSW_R_EN
- RT5665_OSW_R_MASK
- RT5665_OSW_R_SFT
- RT5665_OUT_L_GAIN
- RT5665_OUT_L_MIXER
- RT5665_OUT_R_GAIN
- RT5665_OUT_R_MIXER
- RT5665_OUT_SV_DIS
- RT5665_OUT_SV_EN
- RT5665_OUT_SV_MASK
- RT5665_OUT_SV_SFT
- RT5665_PAD_DRIVING_CTRL
- RT5665_PDM1_BUSY
- RT5665_PDM1_L_MASK
- RT5665_PDM1_L_SFT
- RT5665_PDM1_R_MASK
- RT5665_PDM1_R_SFT
- RT5665_PDM_DATA_CTRL_1
- RT5665_PDM_DATA_CTRL_2
- RT5665_PDM_DATA_CTRL_3
- RT5665_PDM_DATA_CTRL_4
- RT5665_PDM_DIV_MASK
- RT5665_PDM_GAIN
- RT5665_PDM_OUT_CTRL
- RT5665_PDM_PATTERN
- RT5665_PGM_TAB_CTRL1
- RT5665_PGM_TAB_CTRL2
- RT5665_PGM_TAB_CTRL3
- RT5665_PGM_TAB_CTRL4
- RT5665_PGM_TAB_CTRL5
- RT5665_PGM_TAB_CTRL6
- RT5665_PGM_TAB_CTRL7
- RT5665_PGM_TAB_CTRL8
- RT5665_PGM_TAB_CTRL9
- RT5665_PLL
- RT5665_PLL1_PD_MASK
- RT5665_PLL1_PD_SFT
- RT5665_PLL1_SRC_BCLK1
- RT5665_PLL1_SRC_BCLK2
- RT5665_PLL1_SRC_BCLK3
- RT5665_PLL1_SRC_MASK
- RT5665_PLL1_SRC_MCLK
- RT5665_PLL1_SRC_SFT
- RT5665_PLL1_S_BCLK1
- RT5665_PLL1_S_BCLK2
- RT5665_PLL1_S_BCLK3
- RT5665_PLL1_S_BCLK4
- RT5665_PLL1_S_MCLK
- RT5665_PLL_CTRL_1
- RT5665_PLL_CTRL_2
- RT5665_PLL_INP_MAX
- RT5665_PLL_INP_MIN
- RT5665_PLL_K_BP
- RT5665_PLL_K_BP_SFT
- RT5665_PLL_K_MASK
- RT5665_PLL_K_MAX
- RT5665_PLL_K_SFT
- RT5665_PLL_M_BP
- RT5665_PLL_M_BP_SFT
- RT5665_PLL_M_MASK
- RT5665_PLL_M_MAX
- RT5665_PLL_M_SFT
- RT5665_PLL_N_MASK
- RT5665_PLL_N_MAX
- RT5665_PLL_N_SFT
- RT5665_PM_HP_HV
- RT5665_PM_HP_LV
- RT5665_PM_HP_MASK
- RT5665_PM_HP_MV
- RT5665_PM_HP_SFT
- RT5665_POLA_EXT_JD_HIGH
- RT5665_POLA_EXT_JD_LOW
- RT5665_POLA_EXT_JD_MASK
- RT5665_POL_FAST_OFF_HIGH
- RT5665_POL_FAST_OFF_LOW
- RT5665_POL_FAST_OFF_MASK
- RT5665_POW_CLK_DET
- RT5665_PSV_IL_CMD_1
- RT5665_PUMP_EN
- RT5665_PVDD_DET_DIS
- RT5665_PVDD_DET_EN
- RT5665_PVDD_DET_MASK
- RT5665_PVDD_DET_SFT
- RT5665_PWR_ADC_L1
- RT5665_PWR_ADC_L1_BIT
- RT5665_PWR_ADC_L2
- RT5665_PWR_ADC_L2_BIT
- RT5665_PWR_ADC_MF_L
- RT5665_PWR_ADC_MF_L_BIT
- RT5665_PWR_ADC_MF_R
- RT5665_PWR_ADC_MF_R_BIT
- RT5665_PWR_ADC_R1
- RT5665_PWR_ADC_R1_BIT
- RT5665_PWR_ADC_R2
- RT5665_PWR_ADC_R2_BIT
- RT5665_PWR_ADC_S1F
- RT5665_PWR_ADC_S1F_BIT
- RT5665_PWR_ADC_S2F
- RT5665_PWR_ADC_S2F_BIT
- RT5665_PWR_AEC_REF
- RT5665_PWR_AEC_REF_BIT
- RT5665_PWR_ANLG_1
- RT5665_PWR_ANLG_2
- RT5665_PWR_ANLG_3
- RT5665_PWR_BG
- RT5665_PWR_BG_BIT
- RT5665_PWR_BST1
- RT5665_PWR_BST1_BIT
- RT5665_PWR_BST1_P
- RT5665_PWR_BST1_P_BIT
- RT5665_PWR_BST2
- RT5665_PWR_BST2_BIT
- RT5665_PWR_BST2_P
- RT5665_PWR_BST2_P_BIT
- RT5665_PWR_BST3
- RT5665_PWR_BST3_BIT
- RT5665_PWR_BST3_P
- RT5665_PWR_BST3_P_BIT
- RT5665_PWR_BST4
- RT5665_PWR_BST4_BIT
- RT5665_PWR_BST4_P
- RT5665_PWR_BST4_P_BIT
- RT5665_PWR_BST_L
- RT5665_PWR_BST_L_BIT
- RT5665_PWR_BST_R
- RT5665_PWR_BST_R_BIT
- RT5665_PWR_CBJ
- RT5665_PWR_CBJ_BIT
- RT5665_PWR_CLK1M_MASK
- RT5665_PWR_CLK1M_PD
- RT5665_PWR_CLK1M_PU
- RT5665_PWR_CLK1M_SFT
- RT5665_PWR_CLK25M_MASK
- RT5665_PWR_CLK25M_PD
- RT5665_PWR_CLK25M_PU
- RT5665_PWR_CLK25M_SFT
- RT5665_PWR_DAC_L1
- RT5665_PWR_DAC_L1_BIT
- RT5665_PWR_DAC_L2
- RT5665_PWR_DAC_L2_BIT
- RT5665_PWR_DAC_MF_L
- RT5665_PWR_DAC_MF_L_BIT
- RT5665_PWR_DAC_MF_R
- RT5665_PWR_DAC_MF_R_BIT
- RT5665_PWR_DAC_R1
- RT5665_PWR_DAC_R1_BIT
- RT5665_PWR_DAC_R2
- RT5665_PWR_DAC_R2_BIT
- RT5665_PWR_DAC_S1F
- RT5665_PWR_DAC_S1F_BIT
- RT5665_PWR_DAC_S2F
- RT5665_PWR_DAC_S2F_BIT
- RT5665_PWR_DIG_1
- RT5665_PWR_DIG_2
- RT5665_PWR_FV1
- RT5665_PWR_FV1_BIT
- RT5665_PWR_FV2
- RT5665_PWR_FV2_BIT
- RT5665_PWR_FV3
- RT5665_PWR_FV3_BIT
- RT5665_PWR_HA_L
- RT5665_PWR_HA_L_BIT
- RT5665_PWR_HA_R
- RT5665_PWR_HA_R_BIT
- RT5665_PWR_I2S1_1
- RT5665_PWR_I2S1_1_BIT
- RT5665_PWR_I2S1_2
- RT5665_PWR_I2S1_2_BIT
- RT5665_PWR_I2S2_1
- RT5665_PWR_I2S2_1_BIT
- RT5665_PWR_I2S2_2
- RT5665_PWR_I2S2_2_BIT
- RT5665_PWR_I2S3
- RT5665_PWR_I2S3_BIT
- RT5665_PWR_IN_L
- RT5665_PWR_IN_L_BIT
- RT5665_PWR_IN_R
- RT5665_PWR_IN_R_BIT
- RT5665_PWR_JD1
- RT5665_PWR_JD1_BIT
- RT5665_PWR_JD2
- RT5665_PWR_JD2_BIT
- RT5665_PWR_LDO
- RT5665_PWR_LDO2
- RT5665_PWR_LDO2_BIT
- RT5665_PWR_LDO_BIT
- RT5665_PWR_LM
- RT5665_PWR_LM_BIT
- RT5665_PWR_MA
- RT5665_PWR_MA_BIT
- RT5665_PWR_MB
- RT5665_PWR_MB1
- RT5665_PWR_MB1_BIT
- RT5665_PWR_MB1_PWR_DOWN
- RT5665_PWR_MB2
- RT5665_PWR_MB2_BIT
- RT5665_PWR_MB2_PWR_DOWN
- RT5665_PWR_MB3
- RT5665_PWR_MB3_BIT
- RT5665_PWR_MB_BIT
- RT5665_PWR_MB_MASK
- RT5665_PWR_MB_PD
- RT5665_PWR_MB_PU
- RT5665_PWR_MB_SFT
- RT5665_PWR_MIC_DET
- RT5665_PWR_MIC_DET_BIT
- RT5665_PWR_MIXER
- RT5665_PWR_MM
- RT5665_PWR_MM_BIT
- RT5665_PWR_MONO_DAC_L
- RT5665_PWR_MONO_DAC_L_BIT
- RT5665_PWR_MONO_DAC_R
- RT5665_PWR_MONO_DAC_R_BIT
- RT5665_PWR_MV
- RT5665_PWR_MV_BIT
- RT5665_PWR_OM_L
- RT5665_PWR_OM_L_BIT
- RT5665_PWR_OM_R
- RT5665_PWR_OM_R_BIT
- RT5665_PWR_OV_L
- RT5665_PWR_OV_L_BIT
- RT5665_PWR_OV_R
- RT5665_PWR_OV_R_BIT
- RT5665_PWR_PDM1
- RT5665_PWR_PDM1_BIT
- RT5665_PWR_PLL
- RT5665_PWR_PLL_BIT
- RT5665_PWR_RM1_L
- RT5665_PWR_RM1_L_BIT
- RT5665_PWR_RM1_R
- RT5665_PWR_RM1_R_BIT
- RT5665_PWR_RM2_L
- RT5665_PWR_RM2_L_BIT
- RT5665_PWR_RM2_R
- RT5665_PWR_RM2_R_BIT
- RT5665_PWR_STO1_DAC_L
- RT5665_PWR_STO1_DAC_L_BIT
- RT5665_PWR_STO1_DAC_R
- RT5665_PWR_STO1_DAC_R_BIT
- RT5665_PWR_STO2_DAC_L
- RT5665_PWR_STO2_DAC_L_BIT
- RT5665_PWR_STO2_DAC_R
- RT5665_PWR_STO2_DAC_R_BIT
- RT5665_PWR_SVD
- RT5665_PWR_SVD_BIT
- RT5665_PWR_VOL
- RT5665_PWR_VREF1
- RT5665_PWR_VREF1_BIT
- RT5665_PWR_VREF2
- RT5665_PWR_VREF2_BIT
- RT5665_PWR_VREF3
- RT5665_PWR_VREF3_BIT
- RT5665_RAMP_DIS
- RT5665_RAMP_EN
- RT5665_RAMP_MASK
- RT5665_RAMP_SFT
- RT5665_RC_CLK_CTRL
- RT5665_REC1_GAIN
- RT5665_REC1_L1_MIXER
- RT5665_REC1_L2_MIXER
- RT5665_REC1_R1_MIXER
- RT5665_REC1_R2_MIXER
- RT5665_REC2_GAIN
- RT5665_REC2_L1_MIXER
- RT5665_REC2_L2_MIXER
- RT5665_REC2_R1_MIXER
- RT5665_REC2_R2_MIXER
- RT5665_RESET
- RT5665_R_EQ_BPF1_A1
- RT5665_R_EQ_BPF1_A2
- RT5665_R_EQ_BPF1_H0
- RT5665_R_EQ_BPF2_A1
- RT5665_R_EQ_BPF2_A2
- RT5665_R_EQ_BPF2_H0
- RT5665_R_EQ_BPF3_A1
- RT5665_R_EQ_BPF3_A2
- RT5665_R_EQ_BPF3_H0
- RT5665_R_EQ_BPF4_A1
- RT5665_R_EQ_BPF4_A2
- RT5665_R_EQ_BPF4_H0
- RT5665_R_EQ_HPF1_A1
- RT5665_R_EQ_HPF1_H0
- RT5665_R_EQ_LPF1_A1
- RT5665_R_EQ_LPF1_H0
- RT5665_R_EQ_POST_VOL
- RT5665_R_EQ_PRE_VOL
- RT5665_R_MUTE
- RT5665_R_MUTE_SFT
- RT5665_R_VOL_MASK
- RT5665_R_VOL_SFT
- RT5665_SAR_BUTDET_MODE_MASK
- RT5665_SAR_BUTDET_POW_NORM
- RT5665_SAR_BUTDET_POW_SAV
- RT5665_SAR_BUTDET_RST
- RT5665_SAR_BUTDET_RST_MASK
- RT5665_SAR_BUTDET_RST_NORMAL
- RT5665_SAR_BUTT_DET_DIS
- RT5665_SAR_BUTT_DET_EN
- RT5665_SAR_BUTT_DET_MASK
- RT5665_SAR_BYPASS_DIS
- RT5665_SAR_BYPASS_EN
- RT5665_SAR_BYPASS_MASK
- RT5665_SAR_IL_CMD_1
- RT5665_SAR_IL_CMD_10
- RT5665_SAR_IL_CMD_11
- RT5665_SAR_IL_CMD_12
- RT5665_SAR_IL_CMD_2
- RT5665_SAR_IL_CMD_3
- RT5665_SAR_IL_CMD_4
- RT5665_SAR_IL_CMD_5
- RT5665_SAR_IL_CMD_6
- RT5665_SAR_IL_CMD_7
- RT5665_SAR_IL_CMD_8
- RT5665_SAR_IL_CMD_9
- RT5665_SAR_POW_DIS
- RT5665_SAR_POW_EN
- RT5665_SAR_POW_MASK
- RT5665_SAR_RST
- RT5665_SAR_RST_MASK
- RT5665_SAR_RST_NORMAL
- RT5665_SAR_SEL_MB1_MASK
- RT5665_SAR_SEL_MB1_MB2_AUTO
- RT5665_SAR_SEL_MB1_MB2_MANU
- RT5665_SAR_SEL_MB1_MB2_MASK
- RT5665_SAR_SEL_MB1_NOSEL
- RT5665_SAR_SEL_MB1_SEL
- RT5665_SAR_SEL_MB2_MASK
- RT5665_SAR_SEL_MB2_NOSEL
- RT5665_SAR_SEL_MB2_SEL
- RT5665_SAR_SEL_MODE_ADC
- RT5665_SAR_SEL_MODE_CMP
- RT5665_SAR_SEL_MODE_MASK
- RT5665_SAR_SEL_SIGNAL_AUTO
- RT5665_SAR_SEL_SIGNAL_MANU
- RT5665_SAR_SEL_SIGNAL_MASK
- RT5665_SCAN_MODE_CTRL
- RT5665_SCLK_SRC_MASK
- RT5665_SCLK_SRC_MCLK
- RT5665_SCLK_SRC_PLL1
- RT5665_SCLK_SRC_RCCLK
- RT5665_SCLK_SRC_SFT
- RT5665_SCLK_S_MCLK
- RT5665_SCLK_S_PLL1
- RT5665_SCLK_S_RCCLK
- RT5665_SEL_CLK_VOL_DIS
- RT5665_SEL_CLK_VOL_EN
- RT5665_SEL_CLK_VOL_MASK
- RT5665_SEL_SHT_MID_TON_2
- RT5665_SEL_SHT_MID_TON_3
- RT5665_SEL_SHT_MID_TON_MASK
- RT5665_SIL_DET_DIS
- RT5665_SIL_DET_EN
- RT5665_SIL_DET_MASK
- RT5665_SIL_PSV_CTRL1
- RT5665_SIL_PSV_CTRL2
- RT5665_SIL_PSV_CTRL3
- RT5665_SIL_PSV_CTRL4
- RT5665_SIL_PSV_CTRL5
- RT5665_SIL_PSV_CTRL6
- RT5665_SOFT_RAMP_DEPOP
- RT5665_SPDIF_SEL_MASK
- RT5665_SPDIF_SEL_SFT
- RT5665_SPK_AG_DIS
- RT5665_SPK_AG_EN
- RT5665_SPK_AG_MASK
- RT5665_SPK_AG_SFT
- RT5665_STEREO_RATES
- RT5665_STO1_ADC1L_SRC_MASK
- RT5665_STO1_ADC1L_SRC_SFT
- RT5665_STO1_ADC1R_SRC_MASK
- RT5665_STO1_ADC1R_SRC_SFT
- RT5665_STO1_ADC1_SRC_ADC
- RT5665_STO1_ADC1_SRC_DACMIX
- RT5665_STO1_ADC2L_SRC_MASK
- RT5665_STO1_ADC2L_SRC_SFT
- RT5665_STO1_ADC2R_SRC_MASK
- RT5665_STO1_ADC2R_SRC_SFT
- RT5665_STO1_ADCL_SRC_MASK
- RT5665_STO1_ADCL_SRC_SFT
- RT5665_STO1_ADCR_SRC_MASK
- RT5665_STO1_ADCR_SRC_SFT
- RT5665_STO1_ADC_BOOST
- RT5665_STO1_ADC_DIG_VOL
- RT5665_STO1_ADC_L_BST_MASK
- RT5665_STO1_ADC_L_BST_SFT
- RT5665_STO1_ADC_MIXER
- RT5665_STO1_ADC_R_BST_MASK
- RT5665_STO1_ADC_R_BST_SFT
- RT5665_STO1_DAC_MIXER
- RT5665_STO1_DAC_SIL_DET
- RT5665_STO1_DD_L_SRC_MASK
- RT5665_STO1_DD_L_SRC_SFT
- RT5665_STO1_DD_R_SRC_MASK
- RT5665_STO1_DD_R_SRC_SFT
- RT5665_STO1_DMIC_SRC_DMIC1
- RT5665_STO1_DMIC_SRC_DMIC2
- RT5665_STO1_DMIC_SRC_MASK
- RT5665_STO1_DMIC_SRC_SFT
- RT5665_STO2_ADC1L_SRC_MASK
- RT5665_STO2_ADC1L_SRC_SFT
- RT5665_STO2_ADC1R_SRC_MASK
- RT5665_STO2_ADC1R_SRC_SFT
- RT5665_STO2_ADC1_SRC_ADC
- RT5665_STO2_ADC1_SRC_DACMIX
- RT5665_STO2_ADC2L_SRC_MASK
- RT5665_STO2_ADC2L_SRC_SFT
- RT5665_STO2_ADC2R_SRC_MASK
- RT5665_STO2_ADC2R_SRC_SFT
- RT5665_STO2_ADCL_SRC_MASK
- RT5665_STO2_ADCL_SRC_SFT
- RT5665_STO2_ADCR_SRC_MASK
- RT5665_STO2_ADCR_SRC_SFT
- RT5665_STO2_ADC_BOOST
- RT5665_STO2_ADC_DIG_VOL
- RT5665_STO2_ADC_L_BST_MASK
- RT5665_STO2_ADC_L_BST_SFT
- RT5665_STO2_ADC_MIXER
- RT5665_STO2_ADC_R_BST_MASK
- RT5665_STO2_ADC_R_BST_SFT
- RT5665_STO2_DAC_MIXER
- RT5665_STO2_DAC_SIL_DET
- RT5665_STO2_DD_L_SRC_MASK
- RT5665_STO2_DD_L_SRC_SFT
- RT5665_STO2_DD_R_SRC_MASK
- RT5665_STO2_DD_R_SRC_SFT
- RT5665_STO2_DMIC_SRC_DMIC1
- RT5665_STO2_DMIC_SRC_DMIC2
- RT5665_STO2_DMIC_SRC_MASK
- RT5665_STO2_DMIC_SRC_SFT
- RT5665_STO_NG2_CTRL_1
- RT5665_STO_NG2_CTRL_2
- RT5665_STO_NG2_CTRL_3
- RT5665_STO_NG2_CTRL_4
- RT5665_STO_NG2_CTRL_5
- RT5665_STO_NG2_CTRL_6
- RT5665_STO_NG2_CTRL_7
- RT5665_STO_NG2_CTRL_8
- RT5665_ST_EN
- RT5665_ST_EN_SFT
- RT5665_ST_SEL_MASK
- RT5665_ST_SEL_SFT
- RT5665_SV_DIS
- RT5665_SV_DLY_MASK
- RT5665_SV_DLY_SFT
- RT5665_SV_EN
- RT5665_SV_MASK
- RT5665_SV_SFT
- RT5665_SV_ZCD_1
- RT5665_SV_ZCD_2
- RT5665_SYS_CLK_DET
- RT5665_TDM_ADC_CTRL_MASK
- RT5665_TDM_ADC_DATA_06
- RT5665_TDM_ADC_SEL_SFT
- RT5665_TDM_CTRL_1
- RT5665_TDM_CTRL_2
- RT5665_TDM_CTRL_3
- RT5665_TDM_CTRL_4
- RT5665_TDM_CTRL_5
- RT5665_TDM_CTRL_6
- RT5665_TDM_CTRL_7
- RT5665_TDM_CTRL_8
- RT5665_TDM_IN_CH_2
- RT5665_TDM_IN_CH_4
- RT5665_TDM_IN_CH_6
- RT5665_TDM_IN_CH_8
- RT5665_TDM_IN_CH_MASK
- RT5665_TDM_IN_LEN_16
- RT5665_TDM_IN_LEN_20
- RT5665_TDM_IN_LEN_24
- RT5665_TDM_IN_LEN_32
- RT5665_TDM_IN_LEN_MASK
- RT5665_TDM_OUT_CH_2
- RT5665_TDM_OUT_CH_4
- RT5665_TDM_OUT_CH_6
- RT5665_TDM_OUT_CH_8
- RT5665_TDM_OUT_CH_MASK
- RT5665_TDM_OUT_LEN_16
- RT5665_TDM_OUT_LEN_20
- RT5665_TDM_OUT_LEN_24
- RT5665_TDM_OUT_LEN_32
- RT5665_TDM_OUT_LEN_MASK
- RT5665_TEST_MODE_CTRL_1
- RT5665_TEST_MODE_CTRL_2
- RT5665_TEST_MODE_CTRL_3
- RT5665_TEST_MODE_CTRL_4
- RT5665_TRIG_JD_HIGH
- RT5665_TRIG_JD_LOW
- RT5665_TRIG_JD_MASK
- RT5665_VENDOR_ID
- RT5665_VENDOR_ID_1
- RT5665_VLO_32V
- RT5665_VLO_3V
- RT5665_VLO_MASK
- RT5665_VLO_SFT
- RT5665_VOL_L_MUTE
- RT5665_VOL_L_SFT
- RT5665_VOL_R_MUTE
- RT5665_VOL_R_SFT
- RT5665_VOL_TEST
- RT5665_VREF_POW_FSM
- RT5665_VREF_POW_MASK
- RT5665_VREF_POW_REG
- RT5665_VREF_REC_OP_FB_CAP_CTRL
- RT5665_ZCD_DIG_DIS
- RT5665_ZCD_DIG_EN
- RT5665_ZCD_DIG_MASK
- RT5665_ZCD_DIG_SFT
- RT5665_ZCD_HP_DIS
- RT5665_ZCD_HP_EN
- RT5665_ZCD_HP_MASK
- RT5665_ZCD_HP_SFT
- RT5665_ZCD_MASK
- RT5665_ZCD_PD
- RT5665_ZCD_PU
- RT5665_ZCD_SFT
- RT5668_4BTN_IL_CMD_1
- RT5668_4BTN_IL_CMD_2
- RT5668_4BTN_IL_CMD_3
- RT5668_4BTN_IL_CMD_4
- RT5668_4BTN_IL_CMD_5
- RT5668_4BTN_IL_CMD_6
- RT5668_4BTN_IL_CMD_7
- RT5668_4BTN_IL_DIS
- RT5668_4BTN_IL_EN
- RT5668_4BTN_IL_MASK
- RT5668_4BTN_IL_NOR
- RT5668_4BTN_IL_RST
- RT5668_4BTN_IL_RST_MASK
- RT5668_AD2DA_LB_MASK
- RT5668_AD2DA_LB_SFT
- RT5668_ADC_L_EQ_LPF1_A1
- RT5668_ADC_L_VOL_MASK
- RT5668_ADC_L_VOL_SFT
- RT5668_ADC_OSR_D_1
- RT5668_ADC_OSR_D_12
- RT5668_ADC_OSR_D_16
- RT5668_ADC_OSR_D_2
- RT5668_ADC_OSR_D_24
- RT5668_ADC_OSR_D_32
- RT5668_ADC_OSR_D_4
- RT5668_ADC_OSR_D_48
- RT5668_ADC_OSR_D_6
- RT5668_ADC_OSR_D_8
- RT5668_ADC_OSR_MASK
- RT5668_ADC_OSR_SFT
- RT5668_ADC_R_VOL_MASK
- RT5668_ADC_R_VOL_SFT
- RT5668_ADC_STO1_ASRC_MASK
- RT5668_ADC_STO1_ASRC_SFT
- RT5668_ADC_STO1_HP_CTRL_1
- RT5668_ADC_STO1_HP_CTRL_2
- RT5668_ADDA_CLK_1
- RT5668_ADDA_CLK_2
- RT5668_AD_ASRC_MASK
- RT5668_AD_ASRC_SEL_MASK
- RT5668_AD_ASRC_SEL_SFT
- RT5668_AD_ASRC_SFT
- RT5668_AD_DA_MIXER
- RT5668_AD_STEREO1_FILTER
- RT5668_AIF1
- RT5668_AIF2
- RT5668_AIFS
- RT5668_AJD1_CTRL
- RT5668_ALC_BACK_GAIN
- RT5668_ASRCIN_FTK_M1_MASK
- RT5668_ASRCIN_FTK_M1_SFT
- RT5668_ASRCIN_FTK_M2_MASK
- RT5668_ASRCIN_FTK_M2_SFT
- RT5668_ASRCIN_FTK_N1_MASK
- RT5668_ASRCIN_FTK_N1_SFT
- RT5668_ASRCIN_FTK_N2_MASK
- RT5668_ASRCIN_FTK_N2_SFT
- RT5668_A_DAC1_MUX
- RT5668_A_DACL1_SFT
- RT5668_A_DACR1_SFT
- RT5668_BIAS_CUR_CTRL_10
- RT5668_BIAS_CUR_CTRL_2
- RT5668_BIAS_CUR_CTRL_3
- RT5668_BIAS_CUR_CTRL_4
- RT5668_BIAS_CUR_CTRL_5
- RT5668_BIAS_CUR_CTRL_6
- RT5668_BIAS_CUR_CTRL_7
- RT5668_BIAS_CUR_CTRL_8
- RT5668_BIAS_CUR_CTRL_9
- RT5668_BPS_DIS
- RT5668_BPS_EN
- RT5668_BPS_MASK
- RT5668_BPS_SFT
- RT5668_BST_CBJ_MASK
- RT5668_BST_CBJ_SFT
- RT5668_CALIB_ADC_CTRL
- RT5668_CAL_REC
- RT5668_CAPLESS_EN
- RT5668_CAPLESS_EN_SFT
- RT5668_CBJ_BST_CTRL
- RT5668_CBJ_CTRL_1
- RT5668_CBJ_CTRL_2
- RT5668_CBJ_CTRL_3
- RT5668_CBJ_CTRL_4
- RT5668_CBJ_CTRL_5
- RT5668_CBJ_CTRL_6
- RT5668_CBJ_CTRL_7
- RT5668_CBJ_IN_BUF_EN
- RT5668_CBJ_JD_TEST_MASK
- RT5668_CBJ_JD_TEST_MODE
- RT5668_CBJ_JD_TEST_NORM
- RT5668_CHARGE_PUMP_1
- RT5668_CHOP_ADC
- RT5668_CHOP_DAC
- RT5668_CKGEN_ADC1_MASK
- RT5668_CKGEN_ADC1_SFT
- RT5668_CKGEN_DAC1_MASK
- RT5668_CKGEN_DAC1_SFT
- RT5668_CKXEN_ADC1_MASK
- RT5668_CKXEN_ADC1_SFT
- RT5668_CKXEN_DAC1_MASK
- RT5668_CKXEN_DAC1_SFT
- RT5668_CLK_DET
- RT5668_CLK_SEL_I2S1_ASRC
- RT5668_CLK_SEL_I2S2_ASRC
- RT5668_CLK_SEL_SYS
- RT5668_CLK_SRC_MCLK
- RT5668_CLK_SRC_PLL1
- RT5668_CLK_SRC_PLL2
- RT5668_CLK_SRC_RCCLK
- RT5668_CLK_SRC_SDW
- RT5668_CTRL_MB1_FSM
- RT5668_CTRL_MB1_REG
- RT5668_CTRL_MB2_FSM
- RT5668_CTRL_MB2_REG
- RT5668_DAC1_DIG_VOL
- RT5668_DAC1_L_SEL_MASK
- RT5668_DAC1_L_SEL_SFT
- RT5668_DAC1_R_SEL_MASK
- RT5668_DAC1_R_SEL_SFT
- RT5668_DAC_ADC_DIG_VOL1
- RT5668_DAC_L1_SRC_MASK
- RT5668_DAC_L1_VOL_MASK
- RT5668_DAC_L1_VOL_SFT
- RT5668_DAC_OSR_D_1
- RT5668_DAC_OSR_D_12
- RT5668_DAC_OSR_D_16
- RT5668_DAC_OSR_D_2
- RT5668_DAC_OSR_D_24
- RT5668_DAC_OSR_D_32
- RT5668_DAC_OSR_D_4
- RT5668_DAC_OSR_D_48
- RT5668_DAC_OSR_D_6
- RT5668_DAC_OSR_D_8
- RT5668_DAC_OSR_MASK
- RT5668_DAC_OSR_SFT
- RT5668_DAC_R1_SRC_MASK
- RT5668_DAC_R1_VOL_MASK
- RT5668_DAC_R1_VOL_SFT
- RT5668_DAC_STO1_ASRC_MASK
- RT5668_DAC_STO1_ASRC_SFT
- RT5668_DATA_SEL_CTRL_1
- RT5668_DA_ASRC_MASK
- RT5668_DA_ASRC_SEL_MASK
- RT5668_DA_ASRC_SEL_SFT
- RT5668_DA_ASRC_SFT
- RT5668_DA_STEREO1_FILTER
- RT5668_DEB_80_MS
- RT5668_DEB_STO_DAC_MASK
- RT5668_DELAY_BUF_CTRL
- RT5668_DEPOP_1
- RT5668_DEPOP_2
- RT5668_DET_TYPE
- RT5668_DET_TYPE_SFT
- RT5668_DEVICE_ID
- RT5668_DIG_GATE_CTRL
- RT5668_DIG_GATE_CTRL_SFT
- RT5668_DIG_INF2_DATA
- RT5668_DIG_IN_CTRL_1
- RT5668_DMIC1_CLK_GPIO1
- RT5668_DMIC1_CLK_GPIO3
- RT5668_DMIC1_DATA_GPIO2
- RT5668_DMIC1_DATA_GPIO5
- RT5668_DMIC1_NULL
- RT5668_DMIC_1_DIS
- RT5668_DMIC_1_DP_GPIO2
- RT5668_DMIC_1_DP_GPIO5
- RT5668_DMIC_1_DP_MASK
- RT5668_DMIC_1_DP_SFT
- RT5668_DMIC_1_EN
- RT5668_DMIC_1_EN_MASK
- RT5668_DMIC_1_EN_SFT
- RT5668_DMIC_ASRC_MASK
- RT5668_DMIC_ASRC_SFT
- RT5668_DMIC_CLK_MASK
- RT5668_DMIC_CLK_SFT
- RT5668_DMIC_CTRL_1
- RT5668_DRC1_CTRL_0
- RT5668_DRC1_CTRL_1
- RT5668_DRC1_CTRL_2
- RT5668_DRC1_CTRL_3
- RT5668_DRC1_CTRL_4
- RT5668_DRC1_CTRL_5
- RT5668_DRC1_CTRL_6
- RT5668_DRC1_HARD_LMT_CTRL_1
- RT5668_DRC1_HARD_LMT_CTRL_2
- RT5668_DRC1_PRIV_1
- RT5668_DRC1_PRIV_2
- RT5668_DRC1_PRIV_3
- RT5668_DRC1_PRIV_4
- RT5668_DRC1_PRIV_5
- RT5668_DRC1_PRIV_6
- RT5668_DRC1_PRIV_7
- RT5668_DRC1_PRIV_8
- RT5668_DUMMY_1
- RT5668_DUMMY_2
- RT5668_DUMMY_3
- RT5668_EFUSE_CTRL_1
- RT5668_EFUSE_CTRL_10
- RT5668_EFUSE_CTRL_11
- RT5668_EFUSE_CTRL_2
- RT5668_EFUSE_CTRL_3
- RT5668_EFUSE_CTRL_4
- RT5668_EFUSE_CTRL_5
- RT5668_EFUSE_CTRL_6
- RT5668_EFUSE_CTRL_7
- RT5668_EFUSE_CTRL_8
- RT5668_EFUSE_CTRL_9
- RT5668_EMB_JD_EN
- RT5668_EMB_JD_EN_SFT
- RT5668_EMB_JD_RST
- RT5668_EQ_AUTO_RCV_CTRL1
- RT5668_EQ_AUTO_RCV_CTRL10
- RT5668_EQ_AUTO_RCV_CTRL11
- RT5668_EQ_AUTO_RCV_CTRL12
- RT5668_EQ_AUTO_RCV_CTRL13
- RT5668_EQ_AUTO_RCV_CTRL2
- RT5668_EQ_AUTO_RCV_CTRL3
- RT5668_EQ_AUTO_RCV_CTRL4
- RT5668_EQ_AUTO_RCV_CTRL5
- RT5668_EQ_AUTO_RCV_CTRL6
- RT5668_EQ_AUTO_RCV_CTRL7
- RT5668_EQ_AUTO_RCV_CTRL8
- RT5668_EQ_AUTO_RCV_CTRL9
- RT5668_EQ_CTRL_1
- RT5668_EQ_CTRL_2
- RT5668_EXT_JD_DIG
- RT5668_EXT_JD_SRC
- RT5668_EXT_JD_SRC_GPIO_JD1
- RT5668_EXT_JD_SRC_GPIO_JD2
- RT5668_EXT_JD_SRC_JDH
- RT5668_EXT_JD_SRC_JDL
- RT5668_EXT_JD_SRC_MANUAL
- RT5668_EXT_JD_SRC_SFT
- RT5668_FAST_OFF_DIS
- RT5668_FAST_OFF_EN
- RT5668_FAST_OFF_MASK
- RT5668_FAST_UPDN_DIS
- RT5668_FAST_UPDN_EN
- RT5668_FAST_UPDN_MASK
- RT5668_FAST_UPDN_SFT
- RT5668_FILTER_CLK_SEL_MASK
- RT5668_FILTER_CLK_SEL_SFT
- RT5668_FORMATS
- RT5668_GLB_CLK
- RT5668_GP1_OUT_H
- RT5668_GP1_OUT_L
- RT5668_GP1_OUT_MASK
- RT5668_GP1_PF_IN
- RT5668_GP1_PF_MASK
- RT5668_GP1_PF_OUT
- RT5668_GP1_PIN_DMIC_CLK
- RT5668_GP1_PIN_GPIO1
- RT5668_GP1_PIN_IRQ
- RT5668_GP1_PIN_MASK
- RT5668_GP1_PIN_SFT
- RT5668_GP1_STA
- RT5668_GP2_OUT_H
- RT5668_GP2_OUT_L
- RT5668_GP2_OUT_MASK
- RT5668_GP2_PF_IN
- RT5668_GP2_PF_MASK
- RT5668_GP2_PF_OUT
- RT5668_GP2_PIN_DMIC_SDA
- RT5668_GP2_PIN_GPIO2
- RT5668_GP2_PIN_LRCK2
- RT5668_GP2_PIN_MASK
- RT5668_GP2_PIN_SFT
- RT5668_GP2_STA
- RT5668_GP3_OUT_H
- RT5668_GP3_OUT_L
- RT5668_GP3_OUT_MASK
- RT5668_GP3_PF_IN
- RT5668_GP3_PF_MASK
- RT5668_GP3_PF_OUT
- RT5668_GP3_PIN_BCLK2
- RT5668_GP3_PIN_DMIC_CLK
- RT5668_GP3_PIN_GPIO3
- RT5668_GP3_PIN_MASK
- RT5668_GP3_PIN_SFT
- RT5668_GP3_STA
- RT5668_GP4_OUT_H
- RT5668_GP4_OUT_L
- RT5668_GP4_OUT_MASK
- RT5668_GP4_PF_IN
- RT5668_GP4_PF_MASK
- RT5668_GP4_PF_OUT
- RT5668_GP4_PIN_ADCDAT1
- RT5668_GP4_PIN_ADCDAT2
- RT5668_GP4_PIN_DMIC_CLK
- RT5668_GP4_PIN_GPIO4
- RT5668_GP4_PIN_MASK
- RT5668_GP4_PIN_SFT
- RT5668_GP4_STA
- RT5668_GP5_OUT_H
- RT5668_GP5_OUT_L
- RT5668_GP5_OUT_MASK
- RT5668_GP5_PF_IN
- RT5668_GP5_PF_MASK
- RT5668_GP5_PF_OUT
- RT5668_GP5_PIN_DACDAT1
- RT5668_GP5_PIN_DMIC_SDA
- RT5668_GP5_PIN_GPIO5
- RT5668_GP5_PIN_MASK
- RT5668_GP5_PIN_SFT
- RT5668_GP5_STA
- RT5668_GP6_OUT_H
- RT5668_GP6_OUT_L
- RT5668_GP6_OUT_MASK
- RT5668_GP6_PF_IN
- RT5668_GP6_PF_MASK
- RT5668_GP6_PF_OUT
- RT5668_GP6_PIN_GPIO6
- RT5668_GP6_PIN_LRCK1
- RT5668_GP6_PIN_MASK
- RT5668_GP6_PIN_SFT
- RT5668_GP6_STA
- RT5668_GPIO_CTRL_1
- RT5668_GPIO_CTRL_2
- RT5668_GPIO_CTRL_3
- RT5668_G_CBJ_RM1_L
- RT5668_G_CBJ_RM1_L_SFT
- RT5668_G_DAC_L1_STO_L_MASK
- RT5668_G_DAC_L1_STO_L_SFT
- RT5668_G_DAC_L1_STO_R_MASK
- RT5668_G_DAC_L1_STO_R_SFT
- RT5668_G_DAC_R1_STO_L_MASK
- RT5668_G_DAC_R1_STO_L_SFT
- RT5668_G_DAC_R1_STO_R_MASK
- RT5668_G_DAC_R1_STO_R_SFT
- RT5668_G_HP
- RT5668_G_HP_SFT
- RT5668_G_STO_DA_DMIX
- RT5668_G_STO_DA_SFT
- RT5668_HPL_GAIN
- RT5668_HPR_GAIN
- RT5668_HP_AMP_DET_CTRL_1
- RT5668_HP_AMP_DET_CTRL_2
- RT5668_HP_CALIB_CTRL_1
- RT5668_HP_CALIB_CTRL_10
- RT5668_HP_CALIB_CTRL_11
- RT5668_HP_CALIB_CTRL_2
- RT5668_HP_CALIB_CTRL_3
- RT5668_HP_CALIB_CTRL_4
- RT5668_HP_CALIB_CTRL_5
- RT5668_HP_CALIB_CTRL_6
- RT5668_HP_CALIB_CTRL_7
- RT5668_HP_CALIB_CTRL_9
- RT5668_HP_CALIB_STA_1
- RT5668_HP_CALIB_STA_10
- RT5668_HP_CALIB_STA_11
- RT5668_HP_CALIB_STA_2
- RT5668_HP_CALIB_STA_3
- RT5668_HP_CALIB_STA_4
- RT5668_HP_CALIB_STA_5
- RT5668_HP_CALIB_STA_6
- RT5668_HP_CALIB_STA_7
- RT5668_HP_CALIB_STA_8
- RT5668_HP_CALIB_STA_9
- RT5668_HP_CHARGE_PUMP_1
- RT5668_HP_CHARGE_PUMP_2
- RT5668_HP_CTRL_1
- RT5668_HP_CTRL_2
- RT5668_HP_DRIVER_1X
- RT5668_HP_DRIVER_3X
- RT5668_HP_DRIVER_5X
- RT5668_HP_DRIVER_MASK
- RT5668_HP_IMP_GAIN_1
- RT5668_HP_IMP_GAIN_2
- RT5668_HP_IMP_SENS_CTRL_01
- RT5668_HP_IMP_SENS_CTRL_02
- RT5668_HP_IMP_SENS_CTRL_03
- RT5668_HP_IMP_SENS_CTRL_04
- RT5668_HP_IMP_SENS_CTRL_05
- RT5668_HP_IMP_SENS_CTRL_06
- RT5668_HP_IMP_SENS_CTRL_07
- RT5668_HP_IMP_SENS_CTRL_08
- RT5668_HP_IMP_SENS_CTRL_09
- RT5668_HP_IMP_SENS_CTRL_10
- RT5668_HP_IMP_SENS_CTRL_11
- RT5668_HP_IMP_SENS_CTRL_12
- RT5668_HP_IMP_SENS_CTRL_13
- RT5668_HP_IMP_SENS_CTRL_14
- RT5668_HP_IMP_SENS_CTRL_15
- RT5668_HP_IMP_SENS_CTRL_16
- RT5668_HP_IMP_SENS_CTRL_17
- RT5668_HP_IMP_SENS_CTRL_18
- RT5668_HP_IMP_SENS_CTRL_19
- RT5668_HP_IMP_SENS_CTRL_20
- RT5668_HP_IMP_SENS_CTRL_21
- RT5668_HP_IMP_SENS_CTRL_22
- RT5668_HP_IMP_SENS_CTRL_23
- RT5668_HP_IMP_SENS_CTRL_24
- RT5668_HP_IMP_SENS_CTRL_25
- RT5668_HP_IMP_SENS_CTRL_26
- RT5668_HP_IMP_SENS_CTRL_27
- RT5668_HP_IMP_SENS_CTRL_28
- RT5668_HP_IMP_SENS_CTRL_29
- RT5668_HP_IMP_SENS_CTRL_30
- RT5668_HP_IMP_SENS_CTRL_31
- RT5668_HP_IMP_SENS_CTRL_32
- RT5668_HP_IMP_SENS_CTRL_33
- RT5668_HP_IMP_SENS_CTRL_34
- RT5668_HP_IMP_SENS_CTRL_35
- RT5668_HP_IMP_SENS_CTRL_36
- RT5668_HP_IMP_SENS_CTRL_37
- RT5668_HP_IMP_SENS_CTRL_38
- RT5668_HP_IMP_SENS_CTRL_39
- RT5668_HP_IMP_SENS_CTRL_40
- RT5668_HP_IMP_SENS_CTRL_41
- RT5668_HP_IMP_SENS_CTRL_42
- RT5668_HP_IMP_SENS_CTRL_43
- RT5668_HP_LOGIC_CTRL_1
- RT5668_HP_LOGIC_CTRL_2
- RT5668_HP_LOGIC_CTRL_3
- RT5668_I2C_CTRL
- RT5668_I2C_MODE
- RT5668_I2S1_DL_16
- RT5668_I2S1_DL_20
- RT5668_I2S1_DL_24
- RT5668_I2S1_DL_32
- RT5668_I2S1_DL_8
- RT5668_I2S1_DL_MASK
- RT5668_I2S1_DL_SFT
- RT5668_I2S1_F_DIV_CTRL_1
- RT5668_I2S1_F_DIV_CTRL_2
- RT5668_I2S1_MONO_DIS
- RT5668_I2S1_MONO_EN
- RT5668_I2S1_MONO_MASK
- RT5668_I2S1_RX_CHL_16
- RT5668_I2S1_RX_CHL_20
- RT5668_I2S1_RX_CHL_24
- RT5668_I2S1_RX_CHL_32
- RT5668_I2S1_RX_CHL_8
- RT5668_I2S1_RX_CHL_MASK
- RT5668_I2S1_RX_CHL_SFT
- RT5668_I2S1_SDP
- RT5668_I2S1_TX_CHL_16
- RT5668_I2S1_TX_CHL_20
- RT5668_I2S1_TX_CHL_24
- RT5668_I2S1_TX_CHL_32
- RT5668_I2S1_TX_CHL_8
- RT5668_I2S1_TX_CHL_MASK
- RT5668_I2S1_TX_CHL_SFT
- RT5668_I2S2_BCLK_MS2_32
- RT5668_I2S2_BCLK_MS2_64
- RT5668_I2S2_BCLK_MS2_MASK
- RT5668_I2S2_BCLK_MS2_SFT
- RT5668_I2S2_CLK_SEL_MASK
- RT5668_I2S2_CLK_SEL_SFT
- RT5668_I2S2_DL_16
- RT5668_I2S2_DL_20
- RT5668_I2S2_DL_24
- RT5668_I2S2_DL_8
- RT5668_I2S2_DL_MASK
- RT5668_I2S2_DL_SFT
- RT5668_I2S2_F_DIV_CTRL_1
- RT5668_I2S2_F_DIV_CTRL_2
- RT5668_I2S2_MONO_DIS
- RT5668_I2S2_MONO_EN
- RT5668_I2S2_MONO_MASK
- RT5668_I2S2_MS_M
- RT5668_I2S2_MS_MASK
- RT5668_I2S2_MS_S
- RT5668_I2S2_MS_SFT
- RT5668_I2S2_M_PD_MASK
- RT5668_I2S2_M_PD_SFT
- RT5668_I2S2_OUT_M
- RT5668_I2S2_OUT_MASK
- RT5668_I2S2_OUT_SFT
- RT5668_I2S2_OUT_UM
- RT5668_I2S2_PIN_CFG_MASK
- RT5668_I2S2_PIN_CFG_SFT
- RT5668_I2S2_SDP
- RT5668_I2S2_SRC_MASK
- RT5668_I2S2_SRC_SFT
- RT5668_I2S_BP_INV
- RT5668_I2S_BP_MASK
- RT5668_I2S_BP_NOR
- RT5668_I2S_BP_SFT
- RT5668_I2S_CLK_SRC_MASK
- RT5668_I2S_CLK_SRC_MCLK
- RT5668_I2S_CLK_SRC_PLL1
- RT5668_I2S_CLK_SRC_PLL2
- RT5668_I2S_CLK_SRC_RCCLK
- RT5668_I2S_CLK_SRC_SDW
- RT5668_I2S_CLK_SRC_SFT
- RT5668_I2S_DF_I2S
- RT5668_I2S_DF_LEFT
- RT5668_I2S_DF_MASK
- RT5668_I2S_DF_PCM_A
- RT5668_I2S_DF_PCM_A_N
- RT5668_I2S_DF_PCM_B
- RT5668_I2S_DF_PCM_B_N
- RT5668_I2S_DF_SFT
- RT5668_I2S_M_CLK_CTRL_1
- RT5668_I2S_M_DIV_MASK
- RT5668_I2S_M_DIV_SFT
- RT5668_I2S_M_D_1
- RT5668_I2S_M_D_12
- RT5668_I2S_M_D_16
- RT5668_I2S_M_D_2
- RT5668_I2S_M_D_24
- RT5668_I2S_M_D_3
- RT5668_I2S_M_D_32
- RT5668_I2S_M_D_4
- RT5668_I2S_M_D_48
- RT5668_I2S_M_D_6
- RT5668_I2S_M_D_8
- RT5668_I2S_PD_1
- RT5668_I2S_PD_12
- RT5668_I2S_PD_16
- RT5668_I2S_PD_2
- RT5668_I2S_PD_24
- RT5668_I2S_PD_3
- RT5668_I2S_PD_32
- RT5668_I2S_PD_4
- RT5668_I2S_PD_48
- RT5668_I2S_PD_6
- RT5668_I2S_PD_8
- RT5668_IB_HP_125IL
- RT5668_IB_HP_1IL
- RT5668_IB_HP_25IL
- RT5668_IB_HP_5IL
- RT5668_IB_HP_MASK
- RT5668_IB_HP_SFT
- RT5668_IF1_ADC1_SEL_SFT
- RT5668_IF1_ADC2_SEL_SFT
- RT5668_IF1_ADC3_SEL_SFT
- RT5668_IF1_ADC4_SEL_SFT
- RT5668_IF2_ADC_SEL_MASK
- RT5668_IF2_ADC_SEL_SFT
- RT5668_IL_CMD_1
- RT5668_IL_CMD_2
- RT5668_IL_CMD_3
- RT5668_IL_CMD_4
- RT5668_IL_CMD_5
- RT5668_IL_CMD_6
- RT5668_IL_IRQ_DIS
- RT5668_IL_IRQ_EN
- RT5668_IL_IRQ_MASK
- RT5668_INT_ST_1
- RT5668_IRQ_CTRL_1
- RT5668_IRQ_CTRL_2
- RT5668_IRQ_CTRL_3
- RT5668_IRQ_CTRL_4
- RT5668_JACK_TYPE_MASK
- RT5668_JD1
- RT5668_JD1_DIS
- RT5668_JD1_EN
- RT5668_JD1_EN_MASK
- RT5668_JD1_EN_SFT
- RT5668_JD1_POL_INV
- RT5668_JD1_POL_MASK
- RT5668_JD1_POL_NOR
- RT5668_JD1_PULSE_DIS
- RT5668_JD1_PULSE_EN
- RT5668_JD1_PULSE_EN_MASK
- RT5668_JD1_PULSE_EN_SFT
- RT5668_JD1_THD
- RT5668_JD2_THD
- RT5668_JDH_NO_PLUG
- RT5668_JDH_PLUG
- RT5668_JDH_RS_MASK
- RT5668_JD_CTRL_1
- RT5668_JD_MODE
- RT5668_JD_MODE_SFT
- RT5668_JD_NULL
- RT5668_JD_TOP_VC_VTRL
- RT5668_LDO1_BYPASS
- RT5668_LDO1_BYPASS_MASK
- RT5668_LDO1_DBG_MASK
- RT5668_LDO1_DVO_09
- RT5668_LDO1_DVO_10
- RT5668_LDO1_DVO_12
- RT5668_LDO1_DVO_14
- RT5668_LDO1_DVO_MASK
- RT5668_LDO1_NOT_BYPASS
- RT5668_LOW_HP_AMP_DET
- RT5668_L_EQ_BPF1_A1
- RT5668_L_EQ_BPF1_A2
- RT5668_L_EQ_BPF1_H0
- RT5668_L_EQ_BPF2_A1
- RT5668_L_EQ_BPF2_A2
- RT5668_L_EQ_BPF2_H0
- RT5668_L_EQ_BPF3_A1
- RT5668_L_EQ_BPF3_A2
- RT5668_L_EQ_BPF3_H0
- RT5668_L_EQ_BPF4_A1
- RT5668_L_EQ_BPF4_A2
- RT5668_L_EQ_BPF4_H0
- RT5668_L_EQ_HPF1_A1
- RT5668_L_EQ_HPF1_H0
- RT5668_L_EQ_LPF1_H0
- RT5668_L_EQ_POST_VOL
- RT5668_L_EQ_PRE_VOL
- RT5668_L_MUTE
- RT5668_L_MUTE_SFT
- RT5668_L_VOL_MASK
- RT5668_L_VOL_SFT
- RT5668_MB1_PATH_MASK
- RT5668_MB2_PATH_MASK
- RT5668_MIC1_CLK_DIS
- RT5668_MIC1_CLK_EN
- RT5668_MIC1_CLK_MASK
- RT5668_MIC1_CLK_SFT
- RT5668_MIC1_OVCD_DIS
- RT5668_MIC1_OVCD_EN
- RT5668_MIC1_OVCD_MASK
- RT5668_MIC1_OVCD_SFT
- RT5668_MIC1_OVTH_1152UA
- RT5668_MIC1_OVTH_1960UA
- RT5668_MIC1_OVTH_768UA
- RT5668_MIC1_OVTH_960UA
- RT5668_MIC1_OVTH_MASK
- RT5668_MIC1_OVTH_SFT
- RT5668_MIC1_OV_1V8
- RT5668_MIC1_OV_2V25
- RT5668_MIC1_OV_2V4
- RT5668_MIC1_OV_2V7
- RT5668_MIC1_OV_MASK
- RT5668_MIC1_OV_SFT
- RT5668_MIC2_CLK_DIS
- RT5668_MIC2_CLK_EN
- RT5668_MIC2_CLK_MASK
- RT5668_MIC2_CLK_SFT
- RT5668_MIC2_OVTH_1152UA
- RT5668_MIC2_OVTH_1960UA
- RT5668_MIC2_OVTH_768UA
- RT5668_MIC2_OVTH_960UA
- RT5668_MIC2_OVTH_MASK
- RT5668_MIC2_OVTH_SFT
- RT5668_MIC2_OV_1V8
- RT5668_MIC2_OV_2V25
- RT5668_MIC2_OV_2V4
- RT5668_MIC2_OV_2V7
- RT5668_MIC2_OV_MASK
- RT5668_MIC2_OV_SFT
- RT5668_MICBIAS_1
- RT5668_MICBIAS_2
- RT5668_MIC_CAP_HP
- RT5668_MIC_CAP_HS
- RT5668_MIC_CAP_MASK
- RT5668_MIC_CAP_SRC_ANA
- RT5668_MIC_CAP_SRC_MASK
- RT5668_MIC_CAP_SRC_REG
- RT5668_MID_HP_AMP_DET
- RT5668_M_ADCMIX_L
- RT5668_M_ADCMIX_L_SFT
- RT5668_M_ADCMIX_R
- RT5668_M_ADCMIX_R_SFT
- RT5668_M_CBJ_RM1_L
- RT5668_M_CBJ_RM1_L_SFT
- RT5668_M_DAC1_L
- RT5668_M_DAC1_L_SFT
- RT5668_M_DAC1_R
- RT5668_M_DAC1_R_SFT
- RT5668_M_DAC_L1_STO_L
- RT5668_M_DAC_L1_STO_L_SFT
- RT5668_M_DAC_L1_STO_R
- RT5668_M_DAC_L1_STO_R_SFT
- RT5668_M_DAC_R1_STO_L
- RT5668_M_DAC_R1_STO_L_SFT
- RT5668_M_DAC_R1_STO_R
- RT5668_M_DAC_R1_STO_R_SFT
- RT5668_M_STO1_ADC_L1
- RT5668_M_STO1_ADC_L1_SFT
- RT5668_M_STO1_ADC_L2
- RT5668_M_STO1_ADC_L2_SFT
- RT5668_M_STO1_ADC_R1
- RT5668_M_STO1_ADC_R1_SFT
- RT5668_M_STO1_ADC_R2
- RT5668_M_STO1_ADC_R2_SFT
- RT5668_M_ST_STO_L
- RT5668_M_ST_STO_L_SFT
- RT5668_M_ST_STO_R
- RT5668_M_ST_STO_R_SFT
- RT5668_NG2_DIS
- RT5668_NG2_EN
- RT5668_NG2_EN_MASK
- RT5668_NUM_SUPPLIES
- RT5668_OSW_L_DIS
- RT5668_OSW_L_EN
- RT5668_OSW_L_MASK
- RT5668_OSW_L_SFT
- RT5668_OSW_R_DIS
- RT5668_OSW_R_EN
- RT5668_OSW_R_MASK
- RT5668_OSW_R_SFT
- RT5668_PAD_DRIVING_CTRL
- RT5668_PLL1_CLK_DET
- RT5668_PLL1_CLK_DET_SFT
- RT5668_PLL1_INTERNAL
- RT5668_PLL1_SRC_BCLK1
- RT5668_PLL1_SRC_MASK
- RT5668_PLL1_SRC_MCLK
- RT5668_PLL1_SRC_RC
- RT5668_PLL1_SRC_SDW
- RT5668_PLL1_SRC_SFT
- RT5668_PLL1_S_BCLK1
- RT5668_PLL1_S_MCLK
- RT5668_PLL1_S_RCCLK
- RT5668_PLL2_CLK_DET
- RT5668_PLL2_CLK_DET_SFT
- RT5668_PLL2_CTRL_1
- RT5668_PLL2_CTRL_2
- RT5668_PLL2_CTRL_3
- RT5668_PLL2_CTRL_4
- RT5668_PLL2_INTERNAL
- RT5668_PLL2_OUT_49M
- RT5668_PLL2_OUT_98M
- RT5668_PLL2_OUT_MASK
- RT5668_PLL2_SRC_BCLK1
- RT5668_PLL2_SRC_MASK
- RT5668_PLL2_SRC_MCLK
- RT5668_PLL2_SRC_RC
- RT5668_PLL2_SRC_SDW
- RT5668_PLL2_SRC_SFT
- RT5668_PLL_CTRL_1
- RT5668_PLL_CTRL_2
- RT5668_PLL_INP_MAX
- RT5668_PLL_INP_MIN
- RT5668_PLL_K_BP
- RT5668_PLL_K_BP_SFT
- RT5668_PLL_K_MASK
- RT5668_PLL_K_MAX
- RT5668_PLL_K_SFT
- RT5668_PLL_M_BP
- RT5668_PLL_M_BP_SFT
- RT5668_PLL_M_MASK
- RT5668_PLL_M_MAX
- RT5668_PLL_M_SFT
- RT5668_PLL_N_MASK
- RT5668_PLL_N_MAX
- RT5668_PLL_N_SFT
- RT5668_PLL_TRACK_1
- RT5668_PLL_TRACK_11
- RT5668_PLL_TRACK_12
- RT5668_PLL_TRACK_14
- RT5668_PLL_TRACK_2
- RT5668_PLL_TRACK_3
- RT5668_PLL_TRACK_4
- RT5668_PLL_TRACK_5
- RT5668_PLL_TRACK_6
- RT5668_PM_HP_HV
- RT5668_PM_HP_LV
- RT5668_PM_HP_MASK
- RT5668_PM_HP_MV
- RT5668_PM_HP_SFT
- RT5668_POLA_EXT_JD_HIGH
- RT5668_POLA_EXT_JD_LOW
- RT5668_POLA_EXT_JD_MASK
- RT5668_POL_FAST_OFF_HIGH
- RT5668_POL_FAST_OFF_LOW
- RT5668_POL_FAST_OFF_MASK
- RT5668_POW_ANA
- RT5668_POW_CLK_DET2_SFT
- RT5668_POW_CLK_DET_SFT
- RT5668_POW_IRQ
- RT5668_POW_JDH
- RT5668_POW_JDL
- RT5668_PUMP_EN
- RT5668_PUMP_EN_SFT
- RT5668_PWR_ADC_L1
- RT5668_PWR_ADC_L1_BIT
- RT5668_PWR_ADC_R1
- RT5668_PWR_ADC_R1_BIT
- RT5668_PWR_ADC_S1F
- RT5668_PWR_ADC_S1F_BIT
- RT5668_PWR_ANLG_1
- RT5668_PWR_ANLG_2
- RT5668_PWR_ANLG_3
- RT5668_PWR_BG
- RT5668_PWR_BG_BIT
- RT5668_PWR_CBJ
- RT5668_PWR_CBJ_BIT
- RT5668_PWR_CLK1M_MASK
- RT5668_PWR_CLK1M_PD
- RT5668_PWR_CLK1M_PU
- RT5668_PWR_CLK1M_SFT
- RT5668_PWR_CLK25M_MASK
- RT5668_PWR_CLK25M_PD
- RT5668_PWR_CLK25M_PU
- RT5668_PWR_CLK25M_SFT
- RT5668_PWR_DAC_L1
- RT5668_PWR_DAC_L1_BIT
- RT5668_PWR_DAC_R1
- RT5668_PWR_DAC_R1_BIT
- RT5668_PWR_DAC_S1F
- RT5668_PWR_DAC_S1F_BIT
- RT5668_PWR_DET_SPKVDD
- RT5668_PWR_DET_SPKVDD_BIT
- RT5668_PWR_DIG_1
- RT5668_PWR_DIG_2
- RT5668_PWR_FV1
- RT5668_PWR_FV1_BIT
- RT5668_PWR_FV2
- RT5668_PWR_FV2_BIT
- RT5668_PWR_HA_L
- RT5668_PWR_HA_L_BIT
- RT5668_PWR_HA_R
- RT5668_PWR_HA_R_BIT
- RT5668_PWR_I2S1
- RT5668_PWR_I2S1_BIT
- RT5668_PWR_I2S2
- RT5668_PWR_I2S2_BIT
- RT5668_PWR_JDH
- RT5668_PWR_JDH_BIT
- RT5668_PWR_JDL
- RT5668_PWR_JDL_BIT
- RT5668_PWR_LDO
- RT5668_PWR_LDO2
- RT5668_PWR_LDO2_BIT
- RT5668_PWR_LDO_BIT
- RT5668_PWR_MA_BIT
- RT5668_PWR_MB
- RT5668_PWR_MB1
- RT5668_PWR_MB1_BIT
- RT5668_PWR_MB1_PWR_DOWN
- RT5668_PWR_MB2
- RT5668_PWR_MB2_BIT
- RT5668_PWR_MB2_PWR_DOWN
- RT5668_PWR_MB_BIT
- RT5668_PWR_MB_MASK
- RT5668_PWR_MB_PD
- RT5668_PWR_MB_PU
- RT5668_PWR_MB_SFT
- RT5668_PWR_MIXER
- RT5668_PWR_PLL
- RT5668_PWR_PLL2B
- RT5668_PWR_PLL2B_BIT
- RT5668_PWR_PLL2F
- RT5668_PWR_PLL2F_BIT
- RT5668_PWR_PLL_BIT
- RT5668_PWR_RM1_L
- RT5668_PWR_RM1_L_BIT
- RT5668_PWR_STO1_DAC_L
- RT5668_PWR_STO1_DAC_L_BIT
- RT5668_PWR_STO1_DAC_R
- RT5668_PWR_STO1_DAC_R_BIT
- RT5668_PWR_VOL
- RT5668_PWR_VREF1
- RT5668_PWR_VREF1_BIT
- RT5668_PWR_VREF2
- RT5668_PWR_VREF2_BIT
- RT5668_RAMP_DIS
- RT5668_RAMP_EN
- RT5668_RAMP_MASK
- RT5668_RAMP_SFT
- RT5668_RC_CLK_CTRL
- RT5668_REC_MIXER
- RT5668_RESET
- RT5668_RESET_HPF_CTRL
- RT5668_RESET_LPF_CTRL
- RT5668_R_EQ_BPF1_A1
- RT5668_R_EQ_BPF1_A2
- RT5668_R_EQ_BPF1_H0
- RT5668_R_EQ_BPF2_A1
- RT5668_R_EQ_BPF2_A2
- RT5668_R_EQ_BPF2_H0
- RT5668_R_EQ_BPF3_A1
- RT5668_R_EQ_BPF3_A2
- RT5668_R_EQ_BPF3_H0
- RT5668_R_EQ_BPF4_A1
- RT5668_R_EQ_BPF4_A2
- RT5668_R_EQ_BPF4_H0
- RT5668_R_EQ_HPF1_A1
- RT5668_R_EQ_HPF1_H0
- RT5668_R_EQ_LPF1_A1
- RT5668_R_EQ_LPF1_H0
- RT5668_R_EQ_POST_VOL
- RT5668_R_EQ_PRE_VOL
- RT5668_R_MUTE
- RT5668_R_MUTE_SFT
- RT5668_R_VOL_MASK
- RT5668_R_VOL_SFT
- RT5668_SAR_BUTDET_MODE_MASK
- RT5668_SAR_BUTDET_POW_NORM
- RT5668_SAR_BUTDET_POW_SAV
- RT5668_SAR_BUTDET_RST
- RT5668_SAR_BUTDET_RST_MASK
- RT5668_SAR_BUTDET_RST_NORMAL
- RT5668_SAR_BUTT_DET_DIS
- RT5668_SAR_BUTT_DET_EN
- RT5668_SAR_BUTT_DET_MASK
- RT5668_SAR_BYPASS_DIS
- RT5668_SAR_BYPASS_EN
- RT5668_SAR_BYPASS_MASK
- RT5668_SAR_IL_CMD_1
- RT5668_SAR_IL_CMD_10
- RT5668_SAR_IL_CMD_11
- RT5668_SAR_IL_CMD_12
- RT5668_SAR_IL_CMD_13
- RT5668_SAR_IL_CMD_2
- RT5668_SAR_IL_CMD_3
- RT5668_SAR_IL_CMD_4
- RT5668_SAR_IL_CMD_5
- RT5668_SAR_IL_CMD_6
- RT5668_SAR_IL_CMD_7
- RT5668_SAR_IL_CMD_8
- RT5668_SAR_IL_CMD_9
- RT5668_SAR_POW_DIS
- RT5668_SAR_POW_EN
- RT5668_SAR_POW_MASK
- RT5668_SAR_RST
- RT5668_SAR_RST_MASK
- RT5668_SAR_RST_NORMAL
- RT5668_SAR_SEL_MB1_MASK
- RT5668_SAR_SEL_MB1_MB2_AUTO
- RT5668_SAR_SEL_MB1_MB2_MANU
- RT5668_SAR_SEL_MB1_MB2_MASK
- RT5668_SAR_SEL_MB1_NOSEL
- RT5668_SAR_SEL_MB1_SEL
- RT5668_SAR_SEL_MB2_MASK
- RT5668_SAR_SEL_MB2_NOSEL
- RT5668_SAR_SEL_MB2_SEL
- RT5668_SAR_SEL_MODE_ADC
- RT5668_SAR_SEL_MODE_CMP
- RT5668_SAR_SEL_MODE_MASK
- RT5668_SAR_SEL_SIGNAL_AUTO
- RT5668_SAR_SEL_SIGNAL_MANU
- RT5668_SAR_SEL_SIGNAL_MASK
- RT5668_SAR_SOUR_BTN
- RT5668_SAR_SOUR_MASK
- RT5668_SAR_SOUR_TYPE
- RT5668_SCLK_SRC_MASK
- RT5668_SCLK_SRC_MCLK
- RT5668_SCLK_SRC_PLL1
- RT5668_SCLK_SRC_PLL2
- RT5668_SCLK_SRC_RCCLK
- RT5668_SCLK_SRC_SDW
- RT5668_SCLK_SRC_SFT
- RT5668_SCLK_S_MCLK
- RT5668_SCLK_S_PLL1
- RT5668_SCLK_S_PLL2
- RT5668_SCLK_S_RCCLK
- RT5668_SDW_REF_1_11K
- RT5668_SDW_REF_1_12K
- RT5668_SDW_REF_1_16K
- RT5668_SDW_REF_1_176K
- RT5668_SDW_REF_1_192K
- RT5668_SDW_REF_1_22K
- RT5668_SDW_REF_1_24K
- RT5668_SDW_REF_1_32K
- RT5668_SDW_REF_1_353K
- RT5668_SDW_REF_1_384K
- RT5668_SDW_REF_1_44K
- RT5668_SDW_REF_1_48K
- RT5668_SDW_REF_1_88K
- RT5668_SDW_REF_1_8K
- RT5668_SDW_REF_1_96K
- RT5668_SDW_REF_1_MASK
- RT5668_SDW_REF_1_SFT
- RT5668_SDW_REF_2_11K
- RT5668_SDW_REF_2_12K
- RT5668_SDW_REF_2_16K
- RT5668_SDW_REF_2_176K
- RT5668_SDW_REF_2_192K
- RT5668_SDW_REF_2_22K
- RT5668_SDW_REF_2_24K
- RT5668_SDW_REF_2_32K
- RT5668_SDW_REF_2_353K
- RT5668_SDW_REF_2_384K
- RT5668_SDW_REF_2_44K
- RT5668_SDW_REF_2_48K
- RT5668_SDW_REF_2_88K
- RT5668_SDW_REF_2_8K
- RT5668_SDW_REF_2_96K
- RT5668_SDW_REF_2_MASK
- RT5668_SDW_REF_2_SFT
- RT5668_SDW_REF_CLK
- RT5668_SEL_ADCDAT_IN
- RT5668_SEL_ADCDAT_MASK
- RT5668_SEL_ADCDAT_OUT
- RT5668_SEL_ADCDAT_SFT
- RT5668_SEL_CLK_VOL_DIS
- RT5668_SEL_CLK_VOL_EN
- RT5668_SEL_CLK_VOL_MASK
- RT5668_SEL_SHT_MID_TON_2
- RT5668_SEL_SHT_MID_TON_3
- RT5668_SEL_SHT_MID_TON_MASK
- RT5668_SIDETONE_CTRL
- RT5668_SIL_PSV_CTRL1
- RT5668_SIL_PSV_CTRL2
- RT5668_SIL_PSV_CTRL3
- RT5668_SIL_PSV_CTRL4
- RT5668_SIL_PSV_CTRL5
- RT5668_SOFT_RAMP_DEPOP
- RT5668_SPKVDD_DET_STA
- RT5668_STEREO_RATES
- RT5668_STO1_ADC1L_SRC_MASK
- RT5668_STO1_ADC1L_SRC_SFT
- RT5668_STO1_ADC1R_SRC_MASK
- RT5668_STO1_ADC1R_SRC_SFT
- RT5668_STO1_ADC1_SRC_ADC
- RT5668_STO1_ADC1_SRC_DACMIX
- RT5668_STO1_ADC2L_SRC_MASK
- RT5668_STO1_ADC2L_SRC_SFT
- RT5668_STO1_ADC2R_SRC_MASK
- RT5668_STO1_ADC2R_SRC_SFT
- RT5668_STO1_ADCL_SRC_MASK
- RT5668_STO1_ADCL_SRC_SFT
- RT5668_STO1_ADCR_SRC_MASK
- RT5668_STO1_ADCR_SRC_SFT
- RT5668_STO1_ADC_BOOST
- RT5668_STO1_ADC_DIG_VOL
- RT5668_STO1_ADC_L_BST_MASK
- RT5668_STO1_ADC_L_BST_SFT
- RT5668_STO1_ADC_MIXER
- RT5668_STO1_ADC_R_BST_MASK
- RT5668_STO1_ADC_R_BST_SFT
- RT5668_STO1_DAC_MIXER
- RT5668_STO1_DAC_SIL_DET
- RT5668_STO1_DD_L_SRC_MASK
- RT5668_STO1_DD_L_SRC_SFT
- RT5668_STO1_DMIC_SRC_DMIC1
- RT5668_STO1_DMIC_SRC_DMIC2
- RT5668_STO1_DMIC_SRC_MASK
- RT5668_STO1_DMIC_SRC_SFT
- RT5668_STO_NG2_CTRL_1
- RT5668_STO_NG2_CTRL_10
- RT5668_STO_NG2_CTRL_2
- RT5668_STO_NG2_CTRL_3
- RT5668_STO_NG2_CTRL_4
- RT5668_STO_NG2_CTRL_5
- RT5668_STO_NG2_CTRL_6
- RT5668_STO_NG2_CTRL_7
- RT5668_STO_NG2_CTRL_8
- RT5668_STO_NG2_CTRL_9
- RT5668_ST_DIS
- RT5668_ST_EN
- RT5668_ST_EN_MASK
- RT5668_ST_EN_SFT
- RT5668_ST_SRC_SEL
- RT5668_ST_SRC_SFT
- RT5668_SV_DIS
- RT5668_SV_DLY_MASK
- RT5668_SV_DLY_SFT
- RT5668_SV_EN
- RT5668_SV_MASK
- RT5668_SV_SFT
- RT5668_SV_ZCD_1
- RT5668_SV_ZCD_2
- RT5668_SYS_CLK_DET
- RT5668_SYS_CLK_DET_SFT
- RT5668_TDM_ADC_DL_SFT
- RT5668_TDM_ADC_LCA_MASK
- RT5668_TDM_ADC_LCA_SFT
- RT5668_TDM_ADC_SEL_SFT
- RT5668_TDM_ADDA_CTRL_1
- RT5668_TDM_ADDA_CTRL_2
- RT5668_TDM_CL_16
- RT5668_TDM_CL_20
- RT5668_TDM_CL_24
- RT5668_TDM_CL_32
- RT5668_TDM_CL_MASK
- RT5668_TDM_CTRL
- RT5668_TDM_DF_I2S
- RT5668_TDM_DF_LEFT
- RT5668_TDM_DF_MASK
- RT5668_TDM_DF_PCM_A
- RT5668_TDM_DF_PCM_A_N
- RT5668_TDM_DF_PCM_B
- RT5668_TDM_DF_PCM_B_N
- RT5668_TDM_DF_SFT
- RT5668_TDM_MS_M
- RT5668_TDM_MS_MASK
- RT5668_TDM_MS_S
- RT5668_TDM_MS_SFT
- RT5668_TDM_M_BP_INV
- RT5668_TDM_M_BP_MASK
- RT5668_TDM_M_BP_NOR
- RT5668_TDM_M_BP_SFT
- RT5668_TDM_M_LP_INV
- RT5668_TDM_M_LP_MASK
- RT5668_TDM_M_LP_NOR
- RT5668_TDM_M_LP_SFT
- RT5668_TDM_RX_CH_2
- RT5668_TDM_RX_CH_4
- RT5668_TDM_RX_CH_6
- RT5668_TDM_RX_CH_8
- RT5668_TDM_RX_CH_MASK
- RT5668_TDM_S_BP_INV
- RT5668_TDM_S_BP_MASK
- RT5668_TDM_S_BP_NOR
- RT5668_TDM_S_BP_SFT
- RT5668_TDM_S_LP_INV
- RT5668_TDM_S_LP_MASK
- RT5668_TDM_S_LP_NOR
- RT5668_TDM_S_LP_SFT
- RT5668_TDM_TCON_CTRL
- RT5668_TDM_TX_CH_2
- RT5668_TDM_TX_CH_4
- RT5668_TDM_TX_CH_6
- RT5668_TDM_TX_CH_8
- RT5668_TDM_TX_CH_MASK
- RT5668_TEST_MODE_CTRL_1
- RT5668_TEST_MODE_CTRL_2
- RT5668_TEST_MODE_CTRL_3
- RT5668_TEST_MODE_CTRL_4
- RT5668_TEST_MODE_CTRL_5
- RT5668_TRIG_JD_HIGH
- RT5668_TRIG_JD_LOW
- RT5668_TRIG_JD_MASK
- RT5668_VENDOR_ID
- RT5668_VERSION_ID
- RT5668_VLO_33V
- RT5668_VLO_3V
- RT5668_VLO_MASK
- RT5668_VLO_SFT
- RT5668_VOL_L_MUTE
- RT5668_VOL_L_SFT
- RT5668_VOL_R_MUTE
- RT5668_VOL_R_SFT
- RT5668_VOL_TEST
- RT5668_VREF_POW_FSM
- RT5668_VREF_POW_MASK
- RT5668_VREF_POW_REG
- RT5668_VREF_REC_OP_FB_CAP_CTRL
- RT5668_ZCD_BST1_CBJ_DIS
- RT5668_ZCD_BST1_CBJ_EN
- RT5668_ZCD_BST1_CBJ_MASK
- RT5668_ZCD_BST1_CBJ_SFT
- RT5668_ZCD_MASK
- RT5668_ZCD_PD
- RT5668_ZCD_PU
- RT5668_ZCD_RECMIX_DIS
- RT5668_ZCD_RECMIX_EN
- RT5668_ZCD_RECMIX_MASK
- RT5668_ZCD_RECMIX_SFT
- RT5668_ZCD_SFT
- RT5670_1ST_HPF_DIS
- RT5670_1ST_HPF_EN
- RT5670_1ST_HPF_MASK
- RT5670_1ST_HPF_SFT
- RT5670_2ND_HPF_DIS
- RT5670_2ND_HPF_EN
- RT5670_2ND_HPF_MASK
- RT5670_2ND_HPF_SFT
- RT5670_3D_1F_MIX_MASK
- RT5670_3D_1F_MIX_SFT
- RT5670_3D_BT_DIS
- RT5670_3D_BT_EN
- RT5670_3D_BT_MASK
- RT5670_3D_BT_SFT
- RT5670_3D_CF_DIS
- RT5670_3D_CF_EN
- RT5670_3D_CF_MASK
- RT5670_3D_CF_SFT
- RT5670_3D_HP_DIS
- RT5670_3D_HP_EN
- RT5670_3D_HP_MASK
- RT5670_3D_HP_M_FRO
- RT5670_3D_HP_M_MASK
- RT5670_3D_HP_M_SFT
- RT5670_3D_HP_M_SUR
- RT5670_3D_HP_SFT
- RT5670_3D_SPK
- RT5670_3D_SPK_CG_MASK
- RT5670_3D_SPK_CG_SFT
- RT5670_3D_SPK_DIS
- RT5670_3D_SPK_EN
- RT5670_3D_SPK_MASK
- RT5670_3D_SPK_M_MASK
- RT5670_3D_SPK_M_SFT
- RT5670_3D_SPK_SFT
- RT5670_3D_SPK_SG_MASK
- RT5670_3D_SPK_SG_SFT
- RT5670_ADC_1_SRC_ADC
- RT5670_ADC_1_SRC_DACMIX
- RT5670_ADC_1_SRC_MASK
- RT5670_ADC_1_SRC_SFT
- RT5670_ADC_2_SRC_MASK
- RT5670_ADC_2_SRC_SFT
- RT5670_ADC_BST_VOL1
- RT5670_ADC_BST_VOL2
- RT5670_ADC_EQ_CTRL1
- RT5670_ADC_EQ_CTRL2
- RT5670_ADC_L_VOL_MASK
- RT5670_ADC_L_VOL_SFT
- RT5670_ADC_MONO_HP_CTRL1
- RT5670_ADC_MONO_HP_CTRL2
- RT5670_ADC_OSR_128
- RT5670_ADC_OSR_16
- RT5670_ADC_OSR_32
- RT5670_ADC_OSR_64
- RT5670_ADC_OSR_MASK
- RT5670_ADC_OSR_SFT
- RT5670_ADC_R_OSR_128
- RT5670_ADC_R_OSR_16
- RT5670_ADC_R_OSR_32
- RT5670_ADC_R_OSR_64
- RT5670_ADC_R_OSR_MASK
- RT5670_ADC_R_OSR_SFT
- RT5670_ADC_R_VOL_MASK
- RT5670_ADC_R_VOL_SFT
- RT5670_ADC_SRC_MASK
- RT5670_ADC_SRC_SFT
- RT5670_ADC_STO2_HP_CTRL1
- RT5670_ADC_STO2_HP_CTRL2
- RT5670_ADDA_CLK1
- RT5670_ADDA_CLK2
- RT5670_ADHPF_EN
- RT5670_ADHPF_EN_SFT
- RT5670_ADJ_HPF1
- RT5670_ADJ_HPF2
- RT5670_AD_DA_MIXER
- RT5670_AD_MONOL_CLK_SEL_MASK
- RT5670_AD_MONOL_CLK_SEL_SFT
- RT5670_AD_MONOR_CLK_SEL_MASK
- RT5670_AD_MONOR_CLK_SEL_SFT
- RT5670_AD_MONO_L_FILTER
- RT5670_AD_MONO_R_FILTER
- RT5670_AD_STEREO_FILTER
- RT5670_AD_STO1_CLK_SEL_MASK
- RT5670_AD_STO1_CLK_SEL_SFT
- RT5670_AIF1
- RT5670_AIF2
- RT5670_AIF3
- RT5670_AIF4
- RT5670_AIFS
- RT5670_ALC_CTRL_1
- RT5670_ALC_CTRL_2
- RT5670_ALC_CTRL_3
- RT5670_ALC_CTRL_4
- RT5670_ALC_DRC_CTRL1
- RT5670_ALC_DRC_CTRL2
- RT5670_ASRC_1
- RT5670_ASRC_10
- RT5670_ASRC_11
- RT5670_ASRC_12
- RT5670_ASRC_13
- RT5670_ASRC_14
- RT5670_ASRC_2
- RT5670_ASRC_3
- RT5670_ASRC_4
- RT5670_ASRC_5
- RT5670_ASRC_7
- RT5670_ASRC_8
- RT5670_ASRC_9
- RT5670_AUTO_PD_DIS
- RT5670_AUTO_PD_EN
- RT5670_AUTO_PD_MASK
- RT5670_AUTO_PD_SFT
- RT5670_A_JD_CTRL1
- RT5670_A_JD_CTRL2
- RT5670_BASE_BACK
- RT5670_BB_CT_A
- RT5670_BB_CT_B
- RT5670_BB_CT_C
- RT5670_BB_CT_D
- RT5670_BB_CT_MASK
- RT5670_BB_CT_SFT
- RT5670_BB_DIS
- RT5670_BB_EN
- RT5670_BB_MASK
- RT5670_BB_SFT
- RT5670_BIAS_CUR1
- RT5670_BIAS_CUR3
- RT5670_BPS_DIS
- RT5670_BPS_EN
- RT5670_BPS_MASK
- RT5670_BPS_SFT
- RT5670_BREEZE
- RT5670_BST_MASK1
- RT5670_BST_MASK2
- RT5670_BST_SFT1
- RT5670_BST_SFT2
- RT5670_CAL_DIS
- RT5670_CAL_EN
- RT5670_CAL_MASK
- RT5670_CAL_M_CAL
- RT5670_CAL_M_DEP
- RT5670_CAL_M_MASK
- RT5670_CAL_M_SFT
- RT5670_CAL_P_CAL
- RT5670_CAL_P_DAC_CAL
- RT5670_CAL_P_MASK
- RT5670_CAL_P_NONE
- RT5670_CAL_P_SFT
- RT5670_CAL_SFT
- RT5670_CAL_TEST_DIS
- RT5670_CAL_TEST_EN
- RT5670_CAL_TEST_MASK
- RT5670_CAL_TEST_SFT
- RT5670_CAPLESS_EN
- RT5670_CBJ_BST1_EN
- RT5670_CBJ_BST1_MASK
- RT5670_CBJ_BST1_SFT
- RT5670_CBJ_DET_MODE
- RT5670_CBJ_JD_HP_EN
- RT5670_CBJ_JD_MIC_EN
- RT5670_CBJ_MN_JD
- RT5670_CHARGE_PUMP
- RT5670_CHOP_DAC_ADC
- RT5670_CJ_CTRL1
- RT5670_CJ_CTRL2
- RT5670_CJ_CTRL3
- RT5670_CLK_SEL_I2S1_ASRC
- RT5670_CLK_SEL_I2S2_ASRC
- RT5670_CLK_SEL_I2S3_ASRC
- RT5670_CLK_SEL_SYS
- RT5670_CLK_SEL_SYS2
- RT5670_CLK_SEL_SYS3
- RT5670_CLSD_INT_REG1
- RT5670_CLSD_OC_MASK
- RT5670_CLSD_OC_PD
- RT5670_CLSD_OC_PU
- RT5670_CLSD_OC_SFT
- RT5670_CLSD_OC_TH_MASK
- RT5670_CLSD_OC_TH_SFT
- RT5670_CLSD_OM_MASK
- RT5670_CLSD_OM_MONO
- RT5670_CLSD_OM_SFT
- RT5670_CLSD_OM_STO
- RT5670_CLSD_RATIO_MASK
- RT5670_CLSD_RATIO_SFT
- RT5670_CLSD_SCH_L
- RT5670_CLSD_SCH_MASK
- RT5670_CLSD_SCH_S
- RT5670_CLSD_SCH_SFT
- RT5670_CMP_MIC_IN_DET_MASK
- RT5670_CP_FQ1_MASK
- RT5670_CP_FQ1_SFT
- RT5670_CP_FQ2_MASK
- RT5670_CP_FQ2_SFT
- RT5670_CP_FQ3_MASK
- RT5670_CP_FQ3_SFT
- RT5670_CP_FQ_12_KHZ
- RT5670_CP_FQ_192_KHZ
- RT5670_CP_FQ_1_5_KHZ
- RT5670_CP_FQ_24_KHZ
- RT5670_CP_FQ_3_KHZ
- RT5670_CP_FQ_48_KHZ
- RT5670_CP_FQ_6_KHZ
- RT5670_CP_FQ_96_KHZ
- RT5670_CP_SYS_MASK
- RT5670_CP_SYS_SFT
- RT5670_DAC1_DIG_VOL
- RT5670_DAC1_L_SEL_IF1
- RT5670_DAC1_L_SEL_IF2
- RT5670_DAC1_L_SEL_IF3
- RT5670_DAC1_L_SEL_IF4
- RT5670_DAC1_L_SEL_MASK
- RT5670_DAC1_L_SEL_SFT
- RT5670_DAC1_R_SEL_IF1
- RT5670_DAC1_R_SEL_IF2
- RT5670_DAC1_R_SEL_IF3
- RT5670_DAC1_R_SEL_IF4
- RT5670_DAC1_R_SEL_MASK
- RT5670_DAC1_R_SEL_SFT
- RT5670_DAC2_DIG_VOL
- RT5670_DAC2_L_SEL_MASK
- RT5670_DAC2_L_SEL_SFT
- RT5670_DAC2_R_SEL_MASK
- RT5670_DAC2_R_SEL_SFT
- RT5670_DAC_CTRL
- RT5670_DAC_L1_MONO_L_VOL_MASK
- RT5670_DAC_L1_MONO_L_VOL_SFT
- RT5670_DAC_L1_STO_L_VOL_MASK
- RT5670_DAC_L1_STO_L_VOL_SFT
- RT5670_DAC_L1_STO_R_VOL_MASK
- RT5670_DAC_L1_STO_R_VOL_SFT
- RT5670_DAC_L1_VOL_MASK
- RT5670_DAC_L1_VOL_SFT
- RT5670_DAC_L2_DAC_L_VOL_MASK
- RT5670_DAC_L2_DAC_L_VOL_SFT
- RT5670_DAC_L2_DAC_R_VOL_MASK
- RT5670_DAC_L2_DAC_R_VOL_SFT
- RT5670_DAC_L2_MONO_L_VOL_MASK
- RT5670_DAC_L2_MONO_L_VOL_SFT
- RT5670_DAC_L2_MONO_R_VOL_MASK
- RT5670_DAC_L2_MONO_R_VOL_SFT
- RT5670_DAC_L2_STO_L_VOL_MASK
- RT5670_DAC_L2_STO_L_VOL_SFT
- RT5670_DAC_L2_VOL_MASK
- RT5670_DAC_L2_VOL_SFT
- RT5670_DAC_L_OSR_128
- RT5670_DAC_L_OSR_16
- RT5670_DAC_L_OSR_32
- RT5670_DAC_L_OSR_64
- RT5670_DAC_L_OSR_MASK
- RT5670_DAC_L_OSR_SFT
- RT5670_DAC_OSR_128
- RT5670_DAC_OSR_16
- RT5670_DAC_OSR_32
- RT5670_DAC_OSR_64
- RT5670_DAC_OSR_MASK
- RT5670_DAC_OSR_SFT
- RT5670_DAC_R1_MONO_R_VOL_MASK
- RT5670_DAC_R1_MONO_R_VOL_SFT
- RT5670_DAC_R1_STO_L_VOL_MASK
- RT5670_DAC_R1_STO_L_VOL_SFT
- RT5670_DAC_R1_STO_R_VOL_MASK
- RT5670_DAC_R1_STO_R_VOL_SFT
- RT5670_DAC_R1_VOL_MASK
- RT5670_DAC_R1_VOL_SFT
- RT5670_DAC_R2_DAC_L_VOL_MASK
- RT5670_DAC_R2_DAC_L_VOL_SFT
- RT5670_DAC_R2_DAC_R_VOL_MASK
- RT5670_DAC_R2_DAC_R_VOL_SFT
- RT5670_DAC_R2_MONO_L_VOL_MASK
- RT5670_DAC_R2_MONO_L_VOL_SFT
- RT5670_DAC_R2_MONO_R_VOL_MASK
- RT5670_DAC_R2_MONO_R_VOL_SFT
- RT5670_DAC_R2_STO_R_VOL_MASK
- RT5670_DAC_R2_STO_R_VOL_SFT
- RT5670_DAC_R2_VOL_MASK
- RT5670_DAC_R2_VOL_SFT
- RT5670_DAHPF_EN
- RT5670_DAHPF_EN_SFT
- RT5670_DA_MONOL_CLK_SEL_MASK
- RT5670_DA_MONOL_CLK_SEL_SFT
- RT5670_DA_MONOR_CLK_SEL_MASK
- RT5670_DA_MONOR_CLK_SEL_SFT
- RT5670_DA_MONO_L_FILTER
- RT5670_DA_MONO_R_FILTER
- RT5670_DA_STEREO_FILTER
- RT5670_DA_STO_CLK_SEL_MASK
- RT5670_DA_STO_CLK_SEL_SFT
- RT5670_DC_CAL_DIS
- RT5670_DC_CAL_EN
- RT5670_DC_CAL_MASK
- RT5670_DC_CAL_M_CAL
- RT5670_DC_CAL_M_MASK
- RT5670_DC_CAL_M_NOR
- RT5670_DC_CAL_M_SFT
- RT5670_DC_CAL_SFT
- RT5670_DD_MIXER
- RT5670_DEPOP_AUTO
- RT5670_DEPOP_M1
- RT5670_DEPOP_M2
- RT5670_DEPOP_M3
- RT5670_DEPOP_MAN
- RT5670_DEPOP_MASK
- RT5670_DEPOP_SFT
- RT5670_DEVICE_ID
- RT5670_DEV_GPIO
- RT5670_DIG_DP_DIS
- RT5670_DIG_DP_EN
- RT5670_DIG_DP_MASK
- RT5670_DIG_DP_SFT
- RT5670_DIG_INF1_DATA
- RT5670_DIG_INF2_DATA
- RT5670_DIG_MISC
- RT5670_DIG_MIXER
- RT5670_DIG_VOL
- RT5670_DIP_SPK_INF
- RT5670_DMIC1_DISABLED
- RT5670_DMIC1_GPIO6
- RT5670_DMIC1_GPIO7
- RT5670_DMIC1_IN2P
- RT5670_DMIC2_DISABLED
- RT5670_DMIC2_GPIO8
- RT5670_DMIC2_INR
- RT5670_DMIC3_DISABLED
- RT5670_DMIC3_GPIO5
- RT5670_DMIC3_SRC_MASK
- RT5670_DMIC3_SRC_SFT
- RT5670_DMIC_1L_LH_FALLING
- RT5670_DMIC_1L_LH_MASK
- RT5670_DMIC_1L_LH_RISING
- RT5670_DMIC_1L_LH_SFT
- RT5670_DMIC_1R_LH_FALLING
- RT5670_DMIC_1R_LH_MASK
- RT5670_DMIC_1R_LH_RISING
- RT5670_DMIC_1R_LH_SFT
- RT5670_DMIC_1_DIS
- RT5670_DMIC_1_DP_GPIO6
- RT5670_DMIC_1_DP_GPIO7
- RT5670_DMIC_1_DP_IN2P
- RT5670_DMIC_1_DP_MASK
- RT5670_DMIC_1_DP_SFT
- RT5670_DMIC_1_EN
- RT5670_DMIC_1_EN_MASK
- RT5670_DMIC_1_EN_SFT
- RT5670_DMIC_1_M_ASYN
- RT5670_DMIC_1_M_MASK
- RT5670_DMIC_1_M_NOR
- RT5670_DMIC_1_M_SFT
- RT5670_DMIC_2L_LH_FALLING
- RT5670_DMIC_2L_LH_MASK
- RT5670_DMIC_2L_LH_RISING
- RT5670_DMIC_2L_LH_SFT
- RT5670_DMIC_2R_LH_FALLING
- RT5670_DMIC_2R_LH_MASK
- RT5670_DMIC_2R_LH_RISING
- RT5670_DMIC_2R_LH_SFT
- RT5670_DMIC_2_DIS
- RT5670_DMIC_2_DP_GPIO8
- RT5670_DMIC_2_DP_IN3N
- RT5670_DMIC_2_DP_MASK
- RT5670_DMIC_2_DP_SFT
- RT5670_DMIC_2_EN
- RT5670_DMIC_2_EN_MASK
- RT5670_DMIC_2_EN_SFT
- RT5670_DMIC_2_M_ASYN
- RT5670_DMIC_2_M_MASK
- RT5670_DMIC_2_M_NOR
- RT5670_DMIC_2_M_SFT
- RT5670_DMIC_3_DIS
- RT5670_DMIC_3_DP_GPIO10
- RT5670_DMIC_3_DP_GPIO5
- RT5670_DMIC_3_DP_GPIO9
- RT5670_DMIC_3_DP_MASK
- RT5670_DMIC_3_DP_SFT
- RT5670_DMIC_3_EN
- RT5670_DMIC_3_EN_MASK
- RT5670_DMIC_3_EN_SFT
- RT5670_DMIC_CLK_MASK
- RT5670_DMIC_CLK_SFT
- RT5670_DMIC_CTRL1
- RT5670_DMIC_CTRL2
- RT5670_DMIC_DATA_GPIO10
- RT5670_DMIC_DATA_GPIO5
- RT5670_DMIC_DATA_GPIO6
- RT5670_DMIC_DATA_GPIO7
- RT5670_DMIC_DATA_GPIO8
- RT5670_DMIC_DATA_GPIO9
- RT5670_DMIC_DATA_IN2P
- RT5670_DMIC_DATA_IN3N
- RT5670_DMIC_EN
- RT5670_DMIC_SRC_MASK
- RT5670_DMIC_SRC_SFT
- RT5670_DOWN_CLK_SEL_MASK
- RT5670_DOWN_CLK_SEL_SFT
- RT5670_DOWN_RATE_FILTER
- RT5670_DP_ATT_MASK
- RT5670_DP_ATT_SFT
- RT5670_DP_SIG_AP
- RT5670_DP_SIG_MASK
- RT5670_DP_SIG_SFT
- RT5670_DP_SIG_TEST
- RT5670_DP_SPK_DIS
- RT5670_DP_SPK_EN
- RT5670_DP_SPK_MASK
- RT5670_DP_SPK_SFT
- RT5670_DP_TH_MASK
- RT5670_DP_TH_SFT
- RT5670_DRC_AGC_AR_MASK
- RT5670_DRC_AGC_AR_SFT
- RT5670_DRC_AGC_CPR_1_1
- RT5670_DRC_AGC_CPR_1_2
- RT5670_DRC_AGC_CPR_1_3
- RT5670_DRC_AGC_CPR_1_4
- RT5670_DRC_AGC_CPR_MASK
- RT5670_DRC_AGC_CPR_SFT
- RT5670_DRC_AGC_CP_DIS
- RT5670_DRC_AGC_CP_EN
- RT5670_DRC_AGC_CP_MASK
- RT5670_DRC_AGC_CP_SFT
- RT5670_DRC_AGC_DIS
- RT5670_DRC_AGC_EN
- RT5670_DRC_AGC_MASK
- RT5670_DRC_AGC_NGB_MASK
- RT5670_DRC_AGC_NGB_SFT
- RT5670_DRC_AGC_NGH_DIS
- RT5670_DRC_AGC_NGH_EN
- RT5670_DRC_AGC_NGH_MASK
- RT5670_DRC_AGC_NGH_SFT
- RT5670_DRC_AGC_NGT_MASK
- RT5670_DRC_AGC_NGT_SFT
- RT5670_DRC_AGC_NG_DIS
- RT5670_DRC_AGC_NG_EN
- RT5670_DRC_AGC_NG_MASK
- RT5670_DRC_AGC_NG_SFT
- RT5670_DRC_AGC_POB_MASK
- RT5670_DRC_AGC_POB_SFT
- RT5670_DRC_AGC_PRB_MASK
- RT5670_DRC_AGC_PRB_SFT
- RT5670_DRC_AGC_P_ADC
- RT5670_DRC_AGC_P_DAC
- RT5670_DRC_AGC_P_MASK
- RT5670_DRC_AGC_P_SFT
- RT5670_DRC_AGC_RC_MASK
- RT5670_DRC_AGC_RC_SFT
- RT5670_DRC_AGC_R_1764K
- RT5670_DRC_AGC_R_192K
- RT5670_DRC_AGC_R_441K
- RT5670_DRC_AGC_R_48K
- RT5670_DRC_AGC_R_882K
- RT5670_DRC_AGC_R_96K
- RT5670_DRC_AGC_R_MASK
- RT5670_DRC_AGC_R_SFT
- RT5670_DRC_AGC_SFT
- RT5670_DRC_AGC_TAR_MASK
- RT5670_DRC_AGC_TAR_SFT
- RT5670_DRC_AGC_UPD
- RT5670_DRC_AGC_UPD_BIT
- RT5670_DRC_HL_CTRL1
- RT5670_DRC_HL_CTRL2
- RT5670_DSP_BUSY_MASK
- RT5670_DSP_CLK
- RT5670_DSP_CLK_192K
- RT5670_DSP_CLK_384K
- RT5670_DSP_CLK_768K
- RT5670_DSP_CLK_96K
- RT5670_DSP_CLK_MASK
- RT5670_DSP_CLK_SFT
- RT5670_DSP_CMD_EN
- RT5670_DSP_CMD_MASK
- RT5670_DSP_CMD_MR
- RT5670_DSP_CMD_MW
- RT5670_DSP_CMD_PE
- RT5670_DSP_CMD_RR
- RT5670_DSP_CMD_RW
- RT5670_DSP_CTRL1
- RT5670_DSP_CTRL2
- RT5670_DSP_CTRL3
- RT5670_DSP_CTRL4
- RT5670_DSP_CTRL5
- RT5670_DSP_DL_0
- RT5670_DSP_DL_1
- RT5670_DSP_DL_2
- RT5670_DSP_DL_3
- RT5670_DSP_DL_MASK
- RT5670_DSP_DL_SEL
- RT5670_DSP_DL_SFT
- RT5670_DSP_I2C_AL_16
- RT5670_DSP_PATH1
- RT5670_DSP_PATH2
- RT5670_DSP_REG_DATHI
- RT5670_DSP_REG_DATLO
- RT5670_DSP_RW_MASK
- RT5670_DSP_UL_SEL
- RT5670_DSP_UL_SFT
- RT5670_EG_MP3_MASK
- RT5670_EG_MP3_SFT
- RT5670_EQ_BPF1_DIS
- RT5670_EQ_BPF1_EN
- RT5670_EQ_BPF1_MASK
- RT5670_EQ_BPF1_SFT
- RT5670_EQ_BPF2_DIS
- RT5670_EQ_BPF2_EN
- RT5670_EQ_BPF2_MASK
- RT5670_EQ_BPF2_SFT
- RT5670_EQ_BPF3_DIS
- RT5670_EQ_BPF3_EN
- RT5670_EQ_BPF3_MASK
- RT5670_EQ_BPF3_SFT
- RT5670_EQ_BPF4_DIS
- RT5670_EQ_BPF4_EN
- RT5670_EQ_BPF4_MASK
- RT5670_EQ_BPF4_SFT
- RT5670_EQ_BW_BP1
- RT5670_EQ_BW_BP2
- RT5670_EQ_BW_BP3
- RT5670_EQ_BW_BP4
- RT5670_EQ_BW_HIP2
- RT5670_EQ_BW_LOP
- RT5670_EQ_CD_DIS
- RT5670_EQ_CD_EN
- RT5670_EQ_CD_MASK
- RT5670_EQ_CD_SFT
- RT5670_EQ_CTRL1
- RT5670_EQ_CTRL2
- RT5670_EQ_CTRL_MASK
- RT5670_EQ_DITH_LSB
- RT5670_EQ_DITH_LSB_1
- RT5670_EQ_DITH_LSB_2
- RT5670_EQ_DITH_MASK
- RT5670_EQ_DITH_NOR
- RT5670_EQ_DITH_SFT
- RT5670_EQ_FC_BP1
- RT5670_EQ_FC_BP2
- RT5670_EQ_FC_BP3
- RT5670_EQ_FC_BP4
- RT5670_EQ_FC_HIP1
- RT5670_EQ_FC_HIP2
- RT5670_EQ_GN_BP1
- RT5670_EQ_GN_BP2
- RT5670_EQ_GN_BP3
- RT5670_EQ_GN_BP4
- RT5670_EQ_GN_HIP1
- RT5670_EQ_GN_HIP2
- RT5670_EQ_GN_LOP
- RT5670_EQ_HPF1_DIS
- RT5670_EQ_HPF1_EN
- RT5670_EQ_HPF1_MASK
- RT5670_EQ_HPF1_M_1ST
- RT5670_EQ_HPF1_M_HI
- RT5670_EQ_HPF1_M_MASK
- RT5670_EQ_HPF1_M_SFT
- RT5670_EQ_HPF1_SFT
- RT5670_EQ_HPF2_DIS
- RT5670_EQ_HPF2_EN
- RT5670_EQ_HPF2_MASK
- RT5670_EQ_HPF2_SFT
- RT5670_EQ_LPF1_M_1ST
- RT5670_EQ_LPF1_M_LO
- RT5670_EQ_LPF1_M_MASK
- RT5670_EQ_LPF1_M_SFT
- RT5670_EQ_LPF_DIS
- RT5670_EQ_LPF_EN
- RT5670_EQ_LPF_MASK
- RT5670_EQ_LPF_SFT
- RT5670_EQ_PRE_VOL
- RT5670_EQ_PRE_VOL_MASK
- RT5670_EQ_PRE_VOL_SFT
- RT5670_EQ_PST_VOL
- RT5670_EQ_PST_VOL_MASK
- RT5670_EQ_PST_VOL_SFT
- RT5670_EQ_SRC_ADC
- RT5670_EQ_SRC_DAC
- RT5670_EQ_SRC_MASK
- RT5670_EQ_SRC_SFT
- RT5670_EQ_UPD
- RT5670_EQ_UPD_BIT
- RT5670_FAST_UPDN_DIS
- RT5670_FAST_UPDN_EN
- RT5670_FAST_UPDN_MASK
- RT5670_FAST_UPDN_SFT
- RT5670_FORMATS
- RT5670_GEN_CTRL2
- RT5670_GEN_CTRL3
- RT5670_GLB_CLK
- RT5670_GP10_PIN_DMIC3_SDA
- RT5670_GP10_PIN_GPIO9
- RT5670_GP10_PIN_MASK
- RT5670_GP10_PIN_PDM_ADT2
- RT5670_GP10_PIN_SFT
- RT5670_GP1_OUT_HI
- RT5670_GP1_OUT_LO
- RT5670_GP1_OUT_MASK
- RT5670_GP1_OUT_SFT
- RT5670_GP1_PF_IN
- RT5670_GP1_PF_MASK
- RT5670_GP1_PF_OUT
- RT5670_GP1_PF_SFT
- RT5670_GP1_PIN_GPIO1
- RT5670_GP1_PIN_IRQ
- RT5670_GP1_PIN_MASK
- RT5670_GP1_PIN_SFT
- RT5670_GP1_P_INV
- RT5670_GP1_P_MASK
- RT5670_GP1_P_NOR
- RT5670_GP1_P_SFT
- RT5670_GP2_OUT_HI
- RT5670_GP2_OUT_LO
- RT5670_GP2_OUT_MASK
- RT5670_GP2_OUT_SFT
- RT5670_GP2_PF_IN
- RT5670_GP2_PF_MASK
- RT5670_GP2_PF_OUT
- RT5670_GP2_PF_SFT
- RT5670_GP2_PIN_DMIC1_SCL
- RT5670_GP2_PIN_GPIO2
- RT5670_GP2_PIN_MASK
- RT5670_GP2_PIN_SFT
- RT5670_GP2_P_INV
- RT5670_GP2_P_MASK
- RT5670_GP2_P_NOR
- RT5670_GP2_P_SFT
- RT5670_GP3_OUT_HI
- RT5670_GP3_OUT_LO
- RT5670_GP3_OUT_MASK
- RT5670_GP3_OUT_SFT
- RT5670_GP3_PF_IN
- RT5670_GP3_PF_MASK
- RT5670_GP3_PF_OUT
- RT5670_GP3_PF_SFT
- RT5670_GP3_PIN_DMIC1_SDA
- RT5670_GP3_PIN_GPIO3
- RT5670_GP3_PIN_IRQ
- RT5670_GP3_PIN_MASK
- RT5670_GP3_PIN_SFT
- RT5670_GP3_P_INV
- RT5670_GP3_P_MASK
- RT5670_GP3_P_NOR
- RT5670_GP3_P_SFT
- RT5670_GP4_OUT_HI
- RT5670_GP4_OUT_LO
- RT5670_GP4_OUT_MASK
- RT5670_GP4_OUT_SFT
- RT5670_GP4_PF_IN
- RT5670_GP4_PF_MASK
- RT5670_GP4_PF_OUT
- RT5670_GP4_PF_SFT
- RT5670_GP4_PIN_DMIC2_SDA
- RT5670_GP4_PIN_GPIO4
- RT5670_GP4_PIN_MASK
- RT5670_GP4_PIN_SFT
- RT5670_GP4_P_INV
- RT5670_GP4_P_MASK
- RT5670_GP4_P_NOR
- RT5670_GP4_P_SFT
- RT5670_GP5_PIN_DMIC3_SDA
- RT5670_GP5_PIN_GPIO5
- RT5670_GP5_PIN_MASK
- RT5670_GP5_PIN_SFT
- RT5670_GP6_PIN_DMIC1_SDA
- RT5670_GP6_PIN_GPIO6
- RT5670_GP6_PIN_MASK
- RT5670_GP6_PIN_SFT
- RT5670_GP7_PIN_DMIC1_SDA
- RT5670_GP7_PIN_GPIO7
- RT5670_GP7_PIN_MASK
- RT5670_GP7_PIN_PDM_SCL2
- RT5670_GP7_PIN_SFT
- RT5670_GP8_PIN_DMIC2_SDA
- RT5670_GP8_PIN_GPIO8
- RT5670_GP8_PIN_MASK
- RT5670_GP8_PIN_SFT
- RT5670_GP9_PIN_DMIC3_SDA
- RT5670_GP9_PIN_GPIO9
- RT5670_GP9_PIN_MASK
- RT5670_GP9_PIN_SFT
- RT5670_GPIO_CTRL1
- RT5670_GPIO_CTRL2
- RT5670_GPIO_CTRL3
- RT5670_GPIO_M_FLT
- RT5670_GPIO_M_MASK
- RT5670_GPIO_M_PH
- RT5670_GPIO_M_SFT
- RT5670_G_BB_BST_MASK
- RT5670_G_BB_BST_SFT
- RT5670_G_BST1_OM_L_MASK
- RT5670_G_BST1_OM_L_SFT
- RT5670_G_BST1_OM_R_MASK
- RT5670_G_BST1_OM_R_SFT
- RT5670_G_BST1_RM_L_MASK
- RT5670_G_BST1_RM_L_SFT
- RT5670_G_BST1_RM_R_MASK
- RT5670_G_BST1_RM_R_SFT
- RT5670_G_BST2_OM_L_MASK
- RT5670_G_BST2_OM_L_SFT
- RT5670_G_BST2_OM_R_MASK
- RT5670_G_BST2_OM_R_SFT
- RT5670_G_BST2_RM_L_MASK
- RT5670_G_BST2_RM_L_SFT
- RT5670_G_BST2_RM_R_MASK
- RT5670_G_BST2_RM_R_SFT
- RT5670_G_BST3_OM_L_MASK
- RT5670_G_BST3_OM_L_SFT
- RT5670_G_BST3_RM_L_MASK
- RT5670_G_BST3_RM_L_SFT
- RT5670_G_BST3_RM_R_MASK
- RT5670_G_BST3_RM_R_SFT
- RT5670_G_BST4_OM_R_MASK
- RT5670_G_BST4_OM_R_SFT
- RT5670_G_BST4_RM_L_MASK
- RT5670_G_BST4_RM_L_SFT
- RT5670_G_BST4_RM_R_MASK
- RT5670_G_BST4_RM_R_SFT
- RT5670_G_DAC_L1_OM_L_MASK
- RT5670_G_DAC_L1_OM_L_SFT
- RT5670_G_DAC_L2_OM_L_MASK
- RT5670_G_DAC_L2_OM_L_SFT
- RT5670_G_DAC_L2_OM_R_MASK
- RT5670_G_DAC_L2_OM_R_SFT
- RT5670_G_DAC_R1_OM_R_MASK
- RT5670_G_DAC_R1_OM_R_SFT
- RT5670_G_DAC_R2_OM_L_MASK
- RT5670_G_DAC_R2_OM_L_SFT
- RT5670_G_DAC_R2_OM_R_MASK
- RT5670_G_DAC_R2_OM_R_SFT
- RT5670_G_HPOMIX_MASK
- RT5670_G_HPOMIX_SFT
- RT5670_G_HP_L_RM_L_MASK
- RT5670_G_HP_L_RM_L_SFT
- RT5670_G_HP_R_RM_R_MASK
- RT5670_G_HP_R_RM_R_SFT
- RT5670_G_IN_L_OM_L_MASK
- RT5670_G_IN_L_OM_L_SFT
- RT5670_G_IN_L_RM_L_MASK
- RT5670_G_IN_L_RM_L_SFT
- RT5670_G_IN_R_OM_R_MASK
- RT5670_G_IN_R_OM_R_SFT
- RT5670_G_IN_R_RM_R_MASK
- RT5670_G_IN_R_RM_R_SFT
- RT5670_G_LOUTMIX_MASK
- RT5670_G_LOUTMIX_SFT
- RT5670_G_MONOMIX_MASK
- RT5670_G_MONOMIX_SFT
- RT5670_G_RM_L_OM_L_MASK
- RT5670_G_RM_L_OM_L_SFT
- RT5670_G_RM_R_OM_R_MASK
- RT5670_G_RM_R_OM_R_SFT
- RT5670_HG_MP3_MASK
- RT5670_HG_MP3_SFT
- RT5670_HPD_PS_DIS
- RT5670_HPD_PS_EN
- RT5670_HPD_PS_MASK
- RT5670_HPD_PS_SFT
- RT5670_HPD_RCV_MASK
- RT5670_HPD_RCV_SFT
- RT5670_HPF_CF_L_MASK
- RT5670_HPF_CF_L_SFT
- RT5670_HPF_CF_R_MASK
- RT5670_HPF_CF_R_SFT
- RT5670_HPF_FC_MASK
- RT5670_HPF_FC_SFT
- RT5670_HPO_MIXER
- RT5670_HP_CALIB_AMP_DET
- RT5670_HP_CB_MASK
- RT5670_HP_CB_PD
- RT5670_HP_CB_PU
- RT5670_HP_CB_SFT
- RT5670_HP_CD_PD_DIS
- RT5670_HP_CD_PD_EN
- RT5670_HP_CD_PD_MASK
- RT5670_HP_CD_PD_SFT
- RT5670_HP_CO_DIS
- RT5670_HP_CO_EN
- RT5670_HP_CO_MASK
- RT5670_HP_CO_SFT
- RT5670_HP_CP_MASK
- RT5670_HP_CP_PD
- RT5670_HP_CP_PU
- RT5670_HP_CP_SFT
- RT5670_HP_DCC_INT1
- RT5670_HP_DP_MASK
- RT5670_HP_DP_PD
- RT5670_HP_DP_PU
- RT5670_HP_DP_SFT
- RT5670_HP_L_SMT_DIS
- RT5670_HP_L_SMT_EN
- RT5670_HP_L_SMT_MASK
- RT5670_HP_L_SMT_SFT
- RT5670_HP_OC_TH_105
- RT5670_HP_OC_TH_120
- RT5670_HP_OC_TH_135
- RT5670_HP_OC_TH_90
- RT5670_HP_OC_TH_MASK
- RT5670_HP_OC_TH_SFT
- RT5670_HP_OVCD_DIS
- RT5670_HP_OVCD_EN
- RT5670_HP_OVCD_MASK
- RT5670_HP_OVCD_SFT
- RT5670_HP_R_SMT_DIS
- RT5670_HP_R_SMT_EN
- RT5670_HP_R_SMT_MASK
- RT5670_HP_R_SMT_SFT
- RT5670_HP_SG_DIS
- RT5670_HP_SG_EN
- RT5670_HP_SG_MASK
- RT5670_HP_SG_SFT
- RT5670_HP_SV_DIS
- RT5670_HP_SV_EN
- RT5670_HP_SV_MASK
- RT5670_HP_SV_SFT
- RT5670_HP_VOL
- RT5670_I2S1_PD_MASK
- RT5670_I2S1_PD_SFT
- RT5670_I2S1_SDP
- RT5670_I2S2_F_I2S1_TCLK
- RT5670_I2S2_F_I2S2_D2
- RT5670_I2S2_F_MASK
- RT5670_I2S2_F_SFT
- RT5670_I2S2_PD_MASK
- RT5670_I2S2_PD_SFT
- RT5670_I2S2_PIN_GPIO
- RT5670_I2S2_PIN_I2S
- RT5670_I2S2_PIN_MASK
- RT5670_I2S2_PIN_SFT
- RT5670_I2S2_SDI_I2S1
- RT5670_I2S2_SDI_I2S2
- RT5670_I2S2_SDI_MASK
- RT5670_I2S2_SDI_SFT
- RT5670_I2S2_SDP
- RT5670_I2S3_SDP
- RT5670_I2S4_SDP
- RT5670_I2S_BCLK_MS1_32
- RT5670_I2S_BCLK_MS1_64
- RT5670_I2S_BCLK_MS1_MASK
- RT5670_I2S_BCLK_MS1_SFT
- RT5670_I2S_BCLK_MS2_32
- RT5670_I2S_BCLK_MS2_64
- RT5670_I2S_BCLK_MS2_MASK
- RT5670_I2S_BCLK_MS2_SFT
- RT5670_I2S_BCLK_MS3_32
- RT5670_I2S_BCLK_MS3_64
- RT5670_I2S_BCLK_MS3_MASK
- RT5670_I2S_BCLK_MS3_SFT
- RT5670_I2S_BP_INV
- RT5670_I2S_BP_MASK
- RT5670_I2S_BP_NOR
- RT5670_I2S_BP_SFT
- RT5670_I2S_DF_I2S
- RT5670_I2S_DF_LEFT
- RT5670_I2S_DF_MASK
- RT5670_I2S_DF_PCM_A
- RT5670_I2S_DF_PCM_B
- RT5670_I2S_DF_SFT
- RT5670_I2S_DL_16
- RT5670_I2S_DL_20
- RT5670_I2S_DL_24
- RT5670_I2S_DL_8
- RT5670_I2S_DL_MASK
- RT5670_I2S_DL_SFT
- RT5670_I2S_IF_MASK
- RT5670_I2S_IF_SFT
- RT5670_I2S_I_CP_A_LAW
- RT5670_I2S_I_CP_MASK
- RT5670_I2S_I_CP_OFF
- RT5670_I2S_I_CP_SFT
- RT5670_I2S_I_CP_U_LAW
- RT5670_I2S_MS_M
- RT5670_I2S_MS_MASK
- RT5670_I2S_MS_S
- RT5670_I2S_MS_SFT
- RT5670_I2S_O_CP_A_LAW
- RT5670_I2S_O_CP_MASK
- RT5670_I2S_O_CP_OFF
- RT5670_I2S_O_CP_SFT
- RT5670_I2S_O_CP_U_LAW
- RT5670_I2S_PD1_1
- RT5670_I2S_PD1_12
- RT5670_I2S_PD1_16
- RT5670_I2S_PD1_2
- RT5670_I2S_PD1_3
- RT5670_I2S_PD1_4
- RT5670_I2S_PD1_6
- RT5670_I2S_PD1_8
- RT5670_I2S_PD1_MASK
- RT5670_I2S_PD1_SFT
- RT5670_I2S_PD2_1
- RT5670_I2S_PD2_12
- RT5670_I2S_PD2_16
- RT5670_I2S_PD2_2
- RT5670_I2S_PD2_3
- RT5670_I2S_PD2_4
- RT5670_I2S_PD2_6
- RT5670_I2S_PD2_8
- RT5670_I2S_PD2_MASK
- RT5670_I2S_PD2_SFT
- RT5670_I2S_PD3_1
- RT5670_I2S_PD3_12
- RT5670_I2S_PD3_16
- RT5670_I2S_PD3_2
- RT5670_I2S_PD3_3
- RT5670_I2S_PD3_4
- RT5670_I2S_PD3_6
- RT5670_I2S_PD3_8
- RT5670_I2S_PD3_MASK
- RT5670_I2S_PD3_SFT
- RT5670_IB_HP_125IL
- RT5670_IB_HP_1IL
- RT5670_IB_HP_25IL
- RT5670_IB_HP_5IL
- RT5670_IB_HP_MASK
- RT5670_IB_HP_SFT
- RT5670_ID_5670
- RT5670_ID_5671
- RT5670_ID_5672
- RT5670_ID_MASK
- RT5670_IF1_ADC1_IN1_SEL
- RT5670_IF1_ADC1_IN1_SFT
- RT5670_IF1_ADC1_IN2_SEL
- RT5670_IF1_ADC1_IN2_SFT
- RT5670_IF1_ADC2_IN1_SEL
- RT5670_IF1_ADC2_IN1_SFT
- RT5670_IF1_ADC2_IN_SEL
- RT5670_IF1_ADC2_IN_SFT
- RT5670_IF2_ADC_IN_MASK
- RT5670_IF2_ADC_IN_SFT
- RT5670_IF2_ADC_SEL_MASK
- RT5670_IF2_ADC_SEL_SFT
- RT5670_IF2_DAC_SEL_MASK
- RT5670_IF2_DAC_SEL_SFT
- RT5670_IF4_ADC_IN_MASK
- RT5670_IF4_ADC_IN_SFT
- RT5670_IL_CMD
- RT5670_IL_CMD2
- RT5670_IL_CMD3
- RT5670_IN2
- RT5670_IN2_DIFF
- RT5670_INL1_INR1_VOL
- RT5670_INL_SEL_IN4P
- RT5670_INL_SEL_MASK
- RT5670_INL_SEL_MONOP
- RT5670_INL_SEL_SFT
- RT5670_INL_VOL_MASK
- RT5670_INL_VOL_SFT
- RT5670_INR_SEL_IN4N
- RT5670_INR_SEL_MASK
- RT5670_INR_SEL_MONON
- RT5670_INR_SEL_SFT
- RT5670_INR_VOL_MASK
- RT5670_INR_VOL_SFT
- RT5670_INT_IRQ_ST
- RT5670_IN_DF1
- RT5670_IN_DF2
- RT5670_IN_SFT1
- RT5670_IN_SFT2
- RT5670_IRQ_CTRL1
- RT5670_IRQ_CTRL2
- RT5670_IRQ_JD_BP
- RT5670_IRQ_JD_MASK
- RT5670_IRQ_JD_NOR
- RT5670_IRQ_JD_SFT
- RT5670_IRQ_MB1_OC_BP
- RT5670_IRQ_MB1_OC_MASK
- RT5670_IRQ_MB1_OC_NOR
- RT5670_IRQ_MB1_OC_SFT
- RT5670_IRQ_MB2_OC_BP
- RT5670_IRQ_MB2_OC_MASK
- RT5670_IRQ_MB2_OC_NOR
- RT5670_IRQ_MB2_OC_SFT
- RT5670_IRQ_OT_BP
- RT5670_IRQ_OT_MASK
- RT5670_IRQ_OT_NOR
- RT5670_IRQ_OT_SFT
- RT5670_JD1_1_DIS
- RT5670_JD1_1_EN
- RT5670_JD1_1_EN_MASK
- RT5670_JD1_1_EN_SFT
- RT5670_JD1_IN4P_DIS
- RT5670_JD1_IN4P_EN
- RT5670_JD1_IN4P_MASK
- RT5670_JD1_IN4P_SFT
- RT5670_JD1_MODE_0
- RT5670_JD1_MODE_1
- RT5670_JD1_MODE_2
- RT5670_JD1_MODE_MASK
- RT5670_JD2_IN4N_DIS
- RT5670_JD2_IN4N_EN
- RT5670_JD2_IN4N_MASK
- RT5670_JD2_IN4N_SFT
- RT5670_JD_CBJ_EN
- RT5670_JD_CBJ_GPIO_JD1
- RT5670_JD_CBJ_GPIO_JD2
- RT5670_JD_CBJ_JD1_1
- RT5670_JD_CBJ_JD1_2
- RT5670_JD_CBJ_JD2
- RT5670_JD_CBJ_JD3
- RT5670_JD_CBJ_MX0B_12
- RT5670_JD_CBJ_POL
- RT5670_JD_CTRL
- RT5670_JD_CTRL3
- RT5670_JD_CTRL4
- RT5670_JD_DIS
- RT5670_JD_GPIO1
- RT5670_JD_GPIO2
- RT5670_JD_GPIO3
- RT5670_JD_GPIO4
- RT5670_JD_HPO_GPIO_JD1
- RT5670_JD_HPO_GPIO_JD2
- RT5670_JD_HPO_JD1_1
- RT5670_JD_HPO_JD1_2
- RT5670_JD_HPO_JD2
- RT5670_JD_HPO_JD3
- RT5670_JD_HPO_MX0B_12
- RT5670_JD_HP_DIS
- RT5670_JD_HP_EN
- RT5670_JD_HP_MASK
- RT5670_JD_HP_SFT
- RT5670_JD_HP_TRG_HI
- RT5670_JD_HP_TRG_LO
- RT5670_JD_HP_TRG_MASK
- RT5670_JD_HP_TRG_SFT
- RT5670_JD_JD1_IN4P
- RT5670_JD_JD2_IN4N
- RT5670_JD_LO_DIS
- RT5670_JD_LO_EN
- RT5670_JD_LO_MASK
- RT5670_JD_LO_SFT
- RT5670_JD_LO_TRG_HI
- RT5670_JD_LO_TRG_LO
- RT5670_JD_LO_TRG_MASK
- RT5670_JD_LO_TRG_SFT
- RT5670_JD_MASK
- RT5670_JD_MODE1
- RT5670_JD_MODE2
- RT5670_JD_MODE3
- RT5670_JD_MO_DIS
- RT5670_JD_MO_EN
- RT5670_JD_MO_MASK
- RT5670_JD_MO_SFT
- RT5670_JD_MO_TRG_HI
- RT5670_JD_MO_TRG_LO
- RT5670_JD_MO_TRG_MASK
- RT5670_JD_MO_TRG_SFT
- RT5670_JD_P_INV
- RT5670_JD_P_MASK
- RT5670_JD_P_NOR
- RT5670_JD_P_SFT
- RT5670_JD_SFT
- RT5670_JD_SPL_DIS
- RT5670_JD_SPL_EN
- RT5670_JD_SPL_MASK
- RT5670_JD_SPL_SFT
- RT5670_JD_SPL_TRG_HI
- RT5670_JD_SPL_TRG_LO
- RT5670_JD_SPL_TRG_MASK
- RT5670_JD_SPL_TRG_SFT
- RT5670_JD_SPR_DIS
- RT5670_JD_SPR_EN
- RT5670_JD_SPR_MASK
- RT5670_JD_SPR_SFT
- RT5670_JD_SPR_TRG_HI
- RT5670_JD_SPR_TRG_LO
- RT5670_JD_SPR_TRG_MASK
- RT5670_JD_SPR_TRG_SFT
- RT5670_JD_STKY_DIS
- RT5670_JD_STKY_EN
- RT5670_JD_STKY_MASK
- RT5670_JD_STKY_SFT
- RT5670_JD_TRI_CBJ_SEL_MASK
- RT5670_JD_TRI_CBJ_SEL_SFT
- RT5670_JD_TRI_HPO_SEL_MASK
- RT5670_JD_TRI_HPO_SEL_SFT
- RT5670_LDO_SEL_MASK
- RT5670_LDO_SEL_SFT
- RT5670_LOUT1
- RT5670_LOUT_MIXER
- RT5670_L_MUTE
- RT5670_L_MUTE_SFT
- RT5670_L_VOL_MASK
- RT5670_L_VOL_SFT
- RT5670_M1_T_I2S2
- RT5670_M1_T_I2S2_D3
- RT5670_M1_T_MASK
- RT5670_M1_T_SFT
- RT5670_MAMP_INT_REG2
- RT5670_MB1_OC_CLR
- RT5670_MB1_OC_CLR_SFT
- RT5670_MB1_OC_P_INV
- RT5670_MB1_OC_P_MASK
- RT5670_MB1_OC_P_NOR
- RT5670_MB1_OC_P_SFT
- RT5670_MB1_OC_STKY_DIS
- RT5670_MB1_OC_STKY_EN
- RT5670_MB1_OC_STKY_MASK
- RT5670_MB1_OC_STKY_SFT
- RT5670_MB2_OC_CLR
- RT5670_MB2_OC_CLR_SFT
- RT5670_MB2_OC_P_INV
- RT5670_MB2_OC_P_MASK
- RT5670_MB2_OC_P_NOR
- RT5670_MB2_OC_P_SFT
- RT5670_MB2_OC_STKY_DIS
- RT5670_MB2_OC_STKY_EN
- RT5670_MB2_OC_STKY_MASK
- RT5670_MB2_OC_STKY_SFT
- RT5670_MCLK_DET
- RT5670_MIC1_BS_75AV
- RT5670_MIC1_BS_9AV
- RT5670_MIC1_BS_MASK
- RT5670_MIC1_BS_SFT
- RT5670_MIC1_CLK_DIS
- RT5670_MIC1_CLK_EN
- RT5670_MIC1_CLK_MASK
- RT5670_MIC1_CLK_SFT
- RT5670_MIC1_OVCD_DIS
- RT5670_MIC1_OVCD_EN
- RT5670_MIC1_OVCD_MASK
- RT5670_MIC1_OVCD_SFT
- RT5670_MIC1_OVTH_1500UA
- RT5670_MIC1_OVTH_2000UA
- RT5670_MIC1_OVTH_600UA
- RT5670_MIC1_OVTH_MASK
- RT5670_MIC1_OVTH_SFT
- RT5670_MIC2_BS_75AV
- RT5670_MIC2_BS_9AV
- RT5670_MIC2_BS_MASK
- RT5670_MIC2_BS_SFT
- RT5670_MIC2_CLK_DIS
- RT5670_MIC2_CLK_EN
- RT5670_MIC2_CLK_MASK
- RT5670_MIC2_CLK_SFT
- RT5670_MIC2_OVCD_DIS
- RT5670_MIC2_OVCD_EN
- RT5670_MIC2_OVCD_MASK
- RT5670_MIC2_OVCD_SFT
- RT5670_MIC2_OVTH_1500UA
- RT5670_MIC2_OVTH_2000UA
- RT5670_MIC2_OVTH_600UA
- RT5670_MIC2_OVTH_MASK
- RT5670_MIC2_OVTH_SFT
- RT5670_MICBIAS
- RT5670_MIXER_INT_REG
- RT5670_MONO_ADC_DIG_VOL
- RT5670_MONO_ADC_L1_SRC_ADCL
- RT5670_MONO_ADC_L1_SRC_DACMIXL
- RT5670_MONO_ADC_L1_SRC_MASK
- RT5670_MONO_ADC_L1_SRC_SFT
- RT5670_MONO_ADC_L2_SRC_MASK
- RT5670_MONO_ADC_L2_SRC_SFT
- RT5670_MONO_ADC_L_SRC_MASK
- RT5670_MONO_ADC_L_SRC_SFT
- RT5670_MONO_ADC_L_VOL_MASK
- RT5670_MONO_ADC_L_VOL_SFT
- RT5670_MONO_ADC_MIXER
- RT5670_MONO_ADC_R1_SRC_ADCR
- RT5670_MONO_ADC_R1_SRC_DACMIXR
- RT5670_MONO_ADC_R1_SRC_MASK
- RT5670_MONO_ADC_R1_SRC_SFT
- RT5670_MONO_ADC_R2_SRC_MASK
- RT5670_MONO_ADC_R2_SRC_SFT
- RT5670_MONO_ADC_R_VOL_MASK
- RT5670_MONO_ADC_R_VOL_SFT
- RT5670_MONO_DMIC_L_SRC_MASK
- RT5670_MONO_DMIC_L_SRC_SFT
- RT5670_MONO_DMIC_R_SRC_MASK
- RT5670_MONO_DMIC_R_SRC_SFT
- RT5670_MONO_MIXER
- RT5670_MP3_HLP_DIS
- RT5670_MP3_HLP_EN
- RT5670_MP3_HLP_MASK
- RT5670_MP3_HLP_SFT
- RT5670_MP3_PLUS1
- RT5670_MP3_PLUS2
- RT5670_MP3_WT_1_2
- RT5670_MP3_WT_1_4
- RT5670_MP3_WT_MASK
- RT5670_MP3_WT_SFT
- RT5670_MRES_15MO
- RT5670_MRES_25MO
- RT5670_MRES_35MO
- RT5670_MRES_45MO
- RT5670_MRES_MASK
- RT5670_MRES_SFT
- RT5670_MT_DIS
- RT5670_MT_EN
- RT5670_MT_MASK
- RT5670_MT_SFT
- RT5670_M_3D_D2H_MASK
- RT5670_M_3D_D2H_SFT
- RT5670_M_3D_D2R_MASK
- RT5670_M_3D_D2R_SFT
- RT5670_M_3D_HRTF_MASK
- RT5670_M_3D_HRTF_SFT
- RT5670_M_3D_REVB_MASK
- RT5670_M_3D_REVB_SFT
- RT5670_M_ADCMIX_L
- RT5670_M_ADCMIX_L_SFT
- RT5670_M_ADCMIX_R
- RT5670_M_ADCMIX_R_SFT
- RT5670_M_ADC_L1
- RT5670_M_ADC_L1_SFT
- RT5670_M_ADC_L2
- RT5670_M_ADC_L2_SFT
- RT5670_M_ADC_R1
- RT5670_M_ADC_R1_SFT
- RT5670_M_ADC_R2
- RT5670_M_ADC_R2_SFT
- RT5670_M_BB_HPF_L_MASK
- RT5670_M_BB_HPF_L_SFT
- RT5670_M_BB_HPF_R_MASK
- RT5670_M_BB_HPF_R_SFT
- RT5670_M_BB_L_MASK
- RT5670_M_BB_L_SFT
- RT5670_M_BB_R_MASK
- RT5670_M_BB_R_SFT
- RT5670_M_BST1_OM_L
- RT5670_M_BST1_OM_L_SFT
- RT5670_M_BST1_RM_L
- RT5670_M_BST1_RM_L_SFT
- RT5670_M_BST1_RM_R
- RT5670_M_BST1_RM_R_SFT
- RT5670_M_BST2_OM_R
- RT5670_M_BST2_OM_R_SFT
- RT5670_M_BST2_RM_L
- RT5670_M_BST2_RM_L_SFT
- RT5670_M_BST2_RM_R
- RT5670_M_BST2_RM_R_SFT
- RT5670_M_BST4_MM
- RT5670_M_BST4_MM_SFT
- RT5670_M_DAC1_HM
- RT5670_M_DAC1_HM_SFT
- RT5670_M_DAC1_L
- RT5670_M_DAC1_L_SFT
- RT5670_M_DAC1_R
- RT5670_M_DAC1_R_SFT
- RT5670_M_DAC2_HM
- RT5670_M_DAC2_HM_SFT
- RT5670_M_DACL1_HML
- RT5670_M_DACL1_HML_SFT
- RT5670_M_DACR1_HMR
- RT5670_M_DACR1_HMR_SFT
- RT5670_M_DAC_L1
- RT5670_M_DAC_L1_LM
- RT5670_M_DAC_L1_LM_SFT
- RT5670_M_DAC_L1_MONO_L
- RT5670_M_DAC_L1_MONO_L_SFT
- RT5670_M_DAC_L1_OM_L
- RT5670_M_DAC_L1_OM_L_SFT
- RT5670_M_DAC_L1_SFT
- RT5670_M_DAC_L1_STO_R
- RT5670_M_DAC_L1_STO_R_SFT
- RT5670_M_DAC_L2
- RT5670_M_DAC_L2_DAC_L
- RT5670_M_DAC_L2_DAC_L_SFT
- RT5670_M_DAC_L2_DAC_R
- RT5670_M_DAC_L2_DAC_R_SFT
- RT5670_M_DAC_L2_MA
- RT5670_M_DAC_L2_MA_SFT
- RT5670_M_DAC_L2_MM
- RT5670_M_DAC_L2_MM_SFT
- RT5670_M_DAC_L2_MONO_L
- RT5670_M_DAC_L2_MONO_L_SFT
- RT5670_M_DAC_L2_MONO_R
- RT5670_M_DAC_L2_MONO_R_SFT
- RT5670_M_DAC_L2_OM_L
- RT5670_M_DAC_L2_OM_L_SFT
- RT5670_M_DAC_L2_SFT
- RT5670_M_DAC_L2_VOL
- RT5670_M_DAC_L2_VOL_SFT
- RT5670_M_DAC_R1
- RT5670_M_DAC_R1_LM
- RT5670_M_DAC_R1_LM_SFT
- RT5670_M_DAC_R1_MONO_R
- RT5670_M_DAC_R1_MONO_R_SFT
- RT5670_M_DAC_R1_OM_R
- RT5670_M_DAC_R1_OM_R_SFT
- RT5670_M_DAC_R1_SFT
- RT5670_M_DAC_R1_STO_L
- RT5670_M_DAC_R1_STO_L_SFT
- RT5670_M_DAC_R2
- RT5670_M_DAC_R2_DAC_L
- RT5670_M_DAC_R2_DAC_L_SFT
- RT5670_M_DAC_R2_DAC_R
- RT5670_M_DAC_R2_DAC_R_SFT
- RT5670_M_DAC_R2_MA
- RT5670_M_DAC_R2_MA_SFT
- RT5670_M_DAC_R2_MM
- RT5670_M_DAC_R2_MM_SFT
- RT5670_M_DAC_R2_MONO_L
- RT5670_M_DAC_R2_MONO_L_SFT
- RT5670_M_DAC_R2_MONO_R
- RT5670_M_DAC_R2_MONO_R_SFT
- RT5670_M_DAC_R2_OM_R
- RT5670_M_DAC_R2_OM_R_SFT
- RT5670_M_DAC_R2_SFT
- RT5670_M_DAC_R2_VOL
- RT5670_M_DAC_R2_VOL_SFT
- RT5670_M_HPVOL_HM
- RT5670_M_HPVOL_HM_SFT
- RT5670_M_INL1_HML
- RT5670_M_INL1_HML_SFT
- RT5670_M_INR1_HMR
- RT5670_M_INR1_HMR_SFT
- RT5670_M_IN_L_OM_L
- RT5670_M_IN_L_OM_L_SFT
- RT5670_M_IN_L_RM_L
- RT5670_M_IN_L_RM_L_SFT
- RT5670_M_IN_R_OM_R
- RT5670_M_IN_R_OM_R_SFT
- RT5670_M_IN_R_RM_R
- RT5670_M_IN_R_RM_R_SFT
- RT5670_M_MONO_ADC_L1
- RT5670_M_MONO_ADC_L1_SFT
- RT5670_M_MONO_ADC_L2
- RT5670_M_MONO_ADC_L2_SFT
- RT5670_M_MONO_ADC_R1
- RT5670_M_MONO_ADC_R1_SFT
- RT5670_M_MONO_ADC_R2
- RT5670_M_MONO_ADC_R2_SFT
- RT5670_M_MP3_DIS
- RT5670_M_MP3_EN
- RT5670_M_MP3_L_MASK
- RT5670_M_MP3_L_SFT
- RT5670_M_MP3_MASK
- RT5670_M_MP3_ORG_L_MASK
- RT5670_M_MP3_ORG_L_SFT
- RT5670_M_MP3_ORG_R_MASK
- RT5670_M_MP3_ORG_R_SFT
- RT5670_M_MP3_R_MASK
- RT5670_M_MP3_R_SFT
- RT5670_M_MP3_SFT
- RT5670_M_OV_L_LM
- RT5670_M_OV_L_LM_SFT
- RT5670_M_OV_L_MM
- RT5670_M_OV_L_MM_SFT
- RT5670_M_OV_R_LM
- RT5670_M_OV_R_LM_SFT
- RT5670_M_OV_R_MM
- RT5670_M_OV_R_MM_SFT
- RT5670_M_PDM1_L
- RT5670_M_PDM1_L_SFT
- RT5670_M_PDM1_R
- RT5670_M_PDM1_R_SFT
- RT5670_M_PDM2_L
- RT5670_M_PDM2_L_SFT
- RT5670_M_PDM2_R
- RT5670_M_PDM2_R_SFT
- RT5670_M_STO_L_DAC_L
- RT5670_M_STO_L_DAC_L_SFT
- RT5670_M_STO_R_DAC_R
- RT5670_M_STO_R_DAC_R_SFT
- RT5670_M_ST_DACL2
- RT5670_M_ST_DACL2_SFT
- RT5670_M_ST_DACR2
- RT5670_M_ST_DACR2_SFT
- RT5670_M_ZCD_MASK
- RT5670_M_ZCD_OM_L
- RT5670_M_ZCD_OM_R
- RT5670_M_ZCD_RM_L
- RT5670_M_ZCD_RM_R
- RT5670_M_ZCD_SFT
- RT5670_M_ZCD_SM_L
- RT5670_M_ZCD_SM_R
- RT5670_NO_WIND
- RT5670_OG_MP3_MASK
- RT5670_OG_MP3_SFT
- RT5670_OSW_L_DIS
- RT5670_OSW_L_EN
- RT5670_OSW_L_MASK
- RT5670_OSW_L_SFT
- RT5670_OSW_R_DIS
- RT5670_OSW_R_EN
- RT5670_OSW_R_MASK
- RT5670_OSW_R_SFT
- RT5670_OT_P_INV
- RT5670_OT_P_MASK
- RT5670_OT_P_NOR
- RT5670_OT_P_SFT
- RT5670_OT_STKY_DIS
- RT5670_OT_STKY_EN
- RT5670_OT_STKY_MASK
- RT5670_OT_STKY_SFT
- RT5670_OUT_L1_MIXER
- RT5670_OUT_R1_MIXER
- RT5670_OUT_SV_DIS
- RT5670_OUT_SV_EN
- RT5670_OUT_SV_MASK
- RT5670_OUT_SV_SFT
- RT5670_PDM1_BUSY
- RT5670_PDM1_DATA_CTRL2
- RT5670_PDM1_DATA_CTRL3
- RT5670_PDM1_DATA_CTRL4
- RT5670_PDM1_L_MASK
- RT5670_PDM1_L_SFT
- RT5670_PDM1_R_MASK
- RT5670_PDM1_R_SFT
- RT5670_PDM2_BUSY
- RT5670_PDM2_DATA_CTRL2
- RT5670_PDM2_DATA_CTRL3
- RT5670_PDM2_DATA_CTRL4
- RT5670_PDM2_L_MASK
- RT5670_PDM2_L_SFT
- RT5670_PDM2_R_MASK
- RT5670_PDM2_R_SFT
- RT5670_PDM_DATA_CTRL1
- RT5670_PDM_DIV_MASK
- RT5670_PDM_GAIN
- RT5670_PDM_OUT_CTRL
- RT5670_PDM_PATTERN
- RT5670_PLL1_PD_1
- RT5670_PLL1_PD_2
- RT5670_PLL1_PD_MASK
- RT5670_PLL1_PD_SFT
- RT5670_PLL1_SRC_BCLK1
- RT5670_PLL1_SRC_BCLK2
- RT5670_PLL1_SRC_BCLK3
- RT5670_PLL1_SRC_MASK
- RT5670_PLL1_SRC_MCLK
- RT5670_PLL1_SRC_SFT
- RT5670_PLL1_S_BCLK1
- RT5670_PLL1_S_BCLK2
- RT5670_PLL1_S_BCLK3
- RT5670_PLL1_S_BCLK4
- RT5670_PLL1_S_MCLK
- RT5670_PLL_CTRL1
- RT5670_PLL_CTRL2
- RT5670_PLL_INP_MAX
- RT5670_PLL_INP_MIN
- RT5670_PLL_K_MASK
- RT5670_PLL_K_MAX
- RT5670_PLL_K_SFT
- RT5670_PLL_M_BP
- RT5670_PLL_M_BP_SFT
- RT5670_PLL_M_MASK
- RT5670_PLL_M_MAX
- RT5670_PLL_M_SFT
- RT5670_PLL_N_MASK
- RT5670_PLL_N_MAX
- RT5670_PLL_N_SFT
- RT5670_PM_HP_HV
- RT5670_PM_HP_LV
- RT5670_PM_HP_MASK
- RT5670_PM_HP_MV
- RT5670_PM_HP_SFT
- RT5670_PRIV_DATA
- RT5670_PRIV_INDEX
- RT5670_PR_ALC_CTRL_1
- RT5670_PR_ALC_CTRL_2
- RT5670_PR_ALC_CTRL_3
- RT5670_PR_ALC_CTRL_4
- RT5670_PR_ALC_CTRL_5
- RT5670_PR_ALC_CTRL_6
- RT5670_PR_BASE
- RT5670_PR_RANGE_BASE
- RT5670_PR_SPACING
- RT5670_PVDD_DET_DIS
- RT5670_PVDD_DET_EN
- RT5670_PVDD_DET_MASK
- RT5670_PVDD_DET_SFT
- RT5670_PWR_ADC_L
- RT5670_PWR_ADC_L_BIT
- RT5670_PWR_ADC_MF_L
- RT5670_PWR_ADC_MF_L_BIT
- RT5670_PWR_ADC_MF_R
- RT5670_PWR_ADC_MF_R_BIT
- RT5670_PWR_ADC_R
- RT5670_PWR_ADC_R_BIT
- RT5670_PWR_ADC_S1F
- RT5670_PWR_ADC_S1F_BIT
- RT5670_PWR_ADC_S2F
- RT5670_PWR_ADC_S2F_BIT
- RT5670_PWR_ANLG1
- RT5670_PWR_ANLG2
- RT5670_PWR_BG
- RT5670_PWR_BG_BIT
- RT5670_PWR_BST1
- RT5670_PWR_BST1_BIT
- RT5670_PWR_BST1_P
- RT5670_PWR_BST1_P_BIT
- RT5670_PWR_BST2
- RT5670_PWR_BST2_BIT
- RT5670_PWR_BST2_P
- RT5670_PWR_BST2_P_BIT
- RT5670_PWR_CLK25M_MASK
- RT5670_PWR_CLK25M_PD
- RT5670_PWR_CLK25M_PU
- RT5670_PWR_CLK25M_SFT
- RT5670_PWR_CLS_D
- RT5670_PWR_CLS_D_BIT
- RT5670_PWR_DAC_L1
- RT5670_PWR_DAC_L1_BIT
- RT5670_PWR_DAC_L2
- RT5670_PWR_DAC_L2_BIT
- RT5670_PWR_DAC_MF_L
- RT5670_PWR_DAC_MF_L_BIT
- RT5670_PWR_DAC_MF_R
- RT5670_PWR_DAC_MF_R_BIT
- RT5670_PWR_DAC_R1
- RT5670_PWR_DAC_R1_BIT
- RT5670_PWR_DAC_R2
- RT5670_PWR_DAC_R2_BIT
- RT5670_PWR_DAC_S1F
- RT5670_PWR_DAC_S1F_BIT
- RT5670_PWR_DIG1
- RT5670_PWR_DIG2
- RT5670_PWR_FV1
- RT5670_PWR_FV1_BIT
- RT5670_PWR_FV2
- RT5670_PWR_FV2_BIT
- RT5670_PWR_HA
- RT5670_PWR_HA_BIT
- RT5670_PWR_HP_L
- RT5670_PWR_HP_L_BIT
- RT5670_PWR_HP_R
- RT5670_PWR_HP_R_BIT
- RT5670_PWR_HV_L
- RT5670_PWR_HV_L_BIT
- RT5670_PWR_HV_R
- RT5670_PWR_HV_R_BIT
- RT5670_PWR_I2S1
- RT5670_PWR_I2S1_BIT
- RT5670_PWR_I2S2
- RT5670_PWR_I2S2_BIT
- RT5670_PWR_I2S_DSP
- RT5670_PWR_I2S_DSP_BIT
- RT5670_PWR_IN_L
- RT5670_PWR_IN_L_BIT
- RT5670_PWR_IN_R
- RT5670_PWR_IN_R_BIT
- RT5670_PWR_JD
- RT5670_PWR_JD1
- RT5670_PWR_JD1_BIT
- RT5670_PWR_JD_BIT
- RT5670_PWR_LM
- RT5670_PWR_LM_BIT
- RT5670_PWR_MB
- RT5670_PWR_MB1
- RT5670_PWR_MB1_BIT
- RT5670_PWR_MB2
- RT5670_PWR_MB2_BIT
- RT5670_PWR_MB_BIT
- RT5670_PWR_MB_MASK
- RT5670_PWR_MB_PD
- RT5670_PWR_MB_PU
- RT5670_PWR_MB_SFT
- RT5670_PWR_MIC_DET
- RT5670_PWR_MIC_DET_BIT
- RT5670_PWR_MIXER
- RT5670_PWR_OM_L
- RT5670_PWR_OM_L_BIT
- RT5670_PWR_OM_R
- RT5670_PWR_OM_R_BIT
- RT5670_PWR_PDM1
- RT5670_PWR_PDM1_BIT
- RT5670_PWR_PDM2
- RT5670_PWR_PDM2_BIT
- RT5670_PWR_PLL
- RT5670_PWR_PLL_BIT
- RT5670_PWR_RM_L
- RT5670_PWR_RM_L_BIT
- RT5670_PWR_RM_R
- RT5670_PWR_RM_R_BIT
- RT5670_PWR_VOL
- RT5670_PWR_VREF1
- RT5670_PWR_VREF1_BIT
- RT5670_PWR_VREF2
- RT5670_PWR_VREF2_BIT
- RT5670_RAMP_DIS
- RT5670_RAMP_EN
- RT5670_RAMP_MASK
- RT5670_RAMP_SFT
- RT5670_REC_L1_MIXER
- RT5670_REC_L2_MIXER
- RT5670_REC_R1_MIXER
- RT5670_REC_R2_MIXER
- RT5670_RESET
- RT5670_RSTN_DIS
- RT5670_RSTN_EN
- RT5670_RSTN_MASK
- RT5670_RSTN_SFT
- RT5670_RSTP_DIS
- RT5670_RSTP_EN
- RT5670_RSTP_MASK
- RT5670_RSTP_SFT
- RT5670_RST_DSP
- RT5670_RXDC_SRC_MASK
- RT5670_RXDC_SRC_MONO
- RT5670_RXDC_SRC_SFT
- RT5670_RXDC_SRC_STO
- RT5670_RXDP2_SEL_ADC
- RT5670_RXDP2_SEL_IF2
- RT5670_RXDP2_SEL_MASK
- RT5670_RXDP2_SEL_SFT
- RT5670_RXDP_SEL_MASK
- RT5670_RXDP_SEL_SFT
- RT5670_RXDP_SRC_DIV2
- RT5670_RXDP_SRC_DIV3
- RT5670_RXDP_SRC_MASK
- RT5670_RXDP_SRC_NOR
- RT5670_RXDP_SRC_SFT
- RT5670_R_MUTE
- RT5670_R_MUTE_SFT
- RT5670_R_VOL_MASK
- RT5670_R_VOL_SFT
- RT5670_SCB_DIS
- RT5670_SCB_EN
- RT5670_SCB_KEY_MASK
- RT5670_SCB_KEY_SFT
- RT5670_SCB_MASK
- RT5670_SCB_SFT
- RT5670_SCB_SWAP_DIS
- RT5670_SCB_SWAP_EN
- RT5670_SCB_SWAP_MASK
- RT5670_SCB_SWAP_SFT
- RT5670_SCLK_SRC_MASK
- RT5670_SCLK_SRC_MCLK
- RT5670_SCLK_SRC_PLL1
- RT5670_SCLK_SRC_RCCLK
- RT5670_SCLK_SRC_SFT
- RT5670_SCLK_S_MCLK
- RT5670_SCLK_S_PLL1
- RT5670_SCLK_S_RCCLK
- RT5670_SCRABBLE_CTRL
- RT5670_SCRABBLE_FUN
- RT5670_SI_DAC_AUTO
- RT5670_SI_DAC_MASK
- RT5670_SI_DAC_SFT
- RT5670_SI_DAC_TEST
- RT5670_SMT_TRIG_DIS
- RT5670_SMT_TRIG_EN
- RT5670_SMT_TRIG_MASK
- RT5670_SMT_TRIG_SFT
- RT5670_SPK_AG_DIS
- RT5670_SPK_AG_EN
- RT5670_SPK_AG_MASK
- RT5670_SPK_AG_SFT
- RT5670_SPO_SV_DIS
- RT5670_SPO_SV_EN
- RT5670_SPO_SV_MASK
- RT5670_SPO_SV_SFT
- RT5670_STEREO_RATES
- RT5670_STO1_ADC_COMP_MASK
- RT5670_STO1_ADC_COMP_SFT
- RT5670_STO1_ADC_DIG_VOL
- RT5670_STO1_ADC_L_BST_MASK
- RT5670_STO1_ADC_L_BST_SFT
- RT5670_STO1_ADC_MIXER
- RT5670_STO1_ADC_R_BST_MASK
- RT5670_STO1_ADC_R_BST_SFT
- RT5670_STO2_ADC_COMP_MASK
- RT5670_STO2_ADC_COMP_SFT
- RT5670_STO2_ADC_DIG_VOL
- RT5670_STO2_ADC_L_BST_MASK
- RT5670_STO2_ADC_L_BST_SFT
- RT5670_STO2_ADC_MIXER
- RT5670_STO2_ADC_R_BST_MASK
- RT5670_STO2_ADC_R_BST_SFT
- RT5670_STO2_ADC_SRC_MASK
- RT5670_STO2_ADC_SRC_SFT
- RT5670_STORM
- RT5670_STO_DAC_MIXER
- RT5670_STO_L_DAC_L_VOL_MASK
- RT5670_STO_L_DAC_L_VOL_SFT
- RT5670_STO_R_DAC_R_VOL_MASK
- RT5670_STO_R_DAC_R_VOL_SFT
- RT5670_STO_T_LRCK1
- RT5670_STO_T_MASK
- RT5670_STO_T_SCLK
- RT5670_STO_T_SFT
- RT5670_ST_EN
- RT5670_ST_EN_SFT
- RT5670_ST_SEL_MASK
- RT5670_ST_SEL_SFT
- RT5670_SV_DIS
- RT5670_SV_DLY_MASK
- RT5670_SV_DLY_SFT
- RT5670_SV_EN
- RT5670_SV_MASK
- RT5670_SV_SFT
- RT5670_SV_ZCD1
- RT5670_SV_ZCD2
- RT5670_TDM_CTRL_1
- RT5670_TDM_CTRL_2
- RT5670_TDM_CTRL_3
- RT5670_TDM_DATA_MODE_50FS
- RT5670_TDM_DATA_MODE_NOR
- RT5670_TDM_DATA_MODE_SEL
- RT5670_TXDP_L_VOL_MASK
- RT5670_TXDP_L_VOL_SFT
- RT5670_TXDP_R_VOL_MASK
- RT5670_TXDP_R_VOL_SFT
- RT5670_TXDP_SLOT_SEL_MASK
- RT5670_TXDP_SLOT_SEL_SFT
- RT5670_TXDP_SRC_DIV2
- RT5670_TXDP_SRC_DIV3
- RT5670_TXDP_SRC_MASK
- RT5670_TXDP_SRC_NOR
- RT5670_TXDP_SRC_SFT
- RT5670_UP_CLK_SEL_MASK
- RT5670_UP_CLK_SEL_SFT
- RT5670_UP_RATE_FILTER
- RT5670_VAD_CTRL1
- RT5670_VAD_CTRL2
- RT5670_VAD_CTRL3
- RT5670_VAD_CTRL4
- RT5670_VAD_CTRL5
- RT5670_VAD_SEL_MASK
- RT5670_VAD_SEL_SFT
- RT5670_VENDOR_ID
- RT5670_VENDOR_ID1
- RT5670_VENDOR_ID2
- RT5670_VLO_32V
- RT5670_VLO_3V
- RT5670_VLO_MASK
- RT5670_VLO_SFT
- RT5670_VOL_L_MUTE
- RT5670_VOL_L_SFT
- RT5670_VOL_R_MUTE
- RT5670_VOL_R_SFT
- RT5670_WND_1
- RT5670_WND_2
- RT5670_WND_3
- RT5670_WND_4
- RT5670_WND_5
- RT5670_WND_8
- RT5670_WND_DIS
- RT5670_WND_EN
- RT5670_WND_FC_NW_MASK
- RT5670_WND_FC_NW_SFT
- RT5670_WND_FC_ST_MASK
- RT5670_WND_FC_ST_SFT
- RT5670_WND_FC_WK_MASK
- RT5670_WND_FC_WK_SFT
- RT5670_WND_MASK
- RT5670_WND_SFT
- RT5670_WND_STRONG_MASK
- RT5670_WND_STRONG_SFT
- RT5670_WND_TH_HI_MASK
- RT5670_WND_TH_HI_SFT
- RT5670_WND_TH_LO_MASK
- RT5670_WND_TH_LO_SFT
- RT5670_WND_WIND_MASK
- RT5670_WND_WIND_SFT
- RT5670_ZCD_DIG_DIS
- RT5670_ZCD_DIG_EN
- RT5670_ZCD_DIG_MASK
- RT5670_ZCD_DIG_SFT
- RT5670_ZCD_HP_DIS
- RT5670_ZCD_HP_EN
- RT5670_ZCD_HP_MASK
- RT5670_ZCD_HP_SFT
- RT5670_ZCD_MASK
- RT5670_ZCD_PD
- RT5670_ZCD_PU
- RT5670_ZCD_SFT
- RT5670_ZD_F_IM
- RT5670_ZD_F_MASK
- RT5670_ZD_F_SFT
- RT5670_ZD_F_UN
- RT5670_ZD_F_ZC_IM
- RT5670_ZD_F_ZC_IOD
- RT5670_ZD_T_MASK
- RT5670_ZD_T_SFT
- RT5672_I2C_DEFAULT
- RT5676
- RT5677
- RT5677_ADC_BST_CTRL2
- RT5677_ADC_DAC_HPF_CTRL1
- RT5677_ADC_EQ_CTRL1
- RT5677_ADC_EQ_CTRL2
- RT5677_ADC_IF_DSP_DAC1_MIXER
- RT5677_ADC_OSR_128
- RT5677_ADC_OSR_32
- RT5677_ADC_OSR_64
- RT5677_ADC_OSR_MASK
- RT5677_ADC_OSR_SFT
- RT5677_ADDA1_SEL_MASK
- RT5677_ADDA1_SEL_SFT
- RT5677_AD_MONOL_CLK_SEL_MASK
- RT5677_AD_MONOL_CLK_SEL_SFT
- RT5677_AD_MONOR_CLK_SEL_MASK
- RT5677_AD_MONOR_CLK_SEL_SFT
- RT5677_AD_MONO_L_FILTER
- RT5677_AD_MONO_R_FILTER
- RT5677_AD_STEREO1_FILTER
- RT5677_AD_STEREO2_FILTER
- RT5677_AD_STEREO3_FILTER
- RT5677_AD_STEREO4_FILTER
- RT5677_AD_STO1_CLK_SEL_MASK
- RT5677_AD_STO1_CLK_SEL_SFT
- RT5677_AD_STO2_CLK_SEL_MASK
- RT5677_AD_STO2_CLK_SEL_SFT
- RT5677_AD_STO3_CLK_SEL_MASK
- RT5677_AD_STO3_CLK_SEL_SFT
- RT5677_AD_STO4_CLK_SEL_MASK
- RT5677_AD_STO4_CLK_SEL_SFT
- RT5677_AIF1
- RT5677_AIF2
- RT5677_AIF3
- RT5677_AIF4
- RT5677_AIF5
- RT5677_AIFS
- RT5677_ANA_ADC_GAIN_CTRL
- RT5677_ANA_DAC1_2_3_SRC
- RT5677_ANA_DAC1_2_SRC_SEL_MASK
- RT5677_ANA_DAC1_2_SRC_SEL_SFT
- RT5677_ANA_DAC3_SRC_SEL_MASK
- RT5677_ANA_DAC3_SRC_SEL_SFT
- RT5677_ASRC_1
- RT5677_ASRC_10
- RT5677_ASRC_11
- RT5677_ASRC_12
- RT5677_ASRC_13
- RT5677_ASRC_14
- RT5677_ASRC_15
- RT5677_ASRC_16
- RT5677_ASRC_17
- RT5677_ASRC_18
- RT5677_ASRC_19
- RT5677_ASRC_2
- RT5677_ASRC_20
- RT5677_ASRC_21
- RT5677_ASRC_22
- RT5677_ASRC_23
- RT5677_ASRC_3
- RT5677_ASRC_4
- RT5677_ASRC_5
- RT5677_ASRC_6
- RT5677_ASRC_7
- RT5677_ASRC_8
- RT5677_ASRC_9
- RT5677_BIAS_CUR1
- RT5677_BIAS_CUR2
- RT5677_BIAS_CUR3
- RT5677_BIAS_CUR4
- RT5677_BIAS_CUR5
- RT5677_BST_MASK1
- RT5677_BST_MASK2
- RT5677_BST_SFT1
- RT5677_BST_SFT2
- RT5677_CHOP_DAC_ADC
- RT5677_CLK_SEL_I2S1_ASRC
- RT5677_CLK_SEL_I2S2_ASRC
- RT5677_CLK_SEL_I2S3_ASRC
- RT5677_CLK_SEL_I2S4_ASRC
- RT5677_CLK_SEL_I2S5_ASRC
- RT5677_CLK_SEL_I2S6_ASRC
- RT5677_CLK_SEL_SYS
- RT5677_CLK_SEL_SYS2
- RT5677_CLK_SEL_SYS3
- RT5677_CLK_SEL_SYS4
- RT5677_CLK_SEL_SYS5
- RT5677_CLK_SEL_SYS6
- RT5677_CLK_SEL_SYS7
- RT5677_CLK_TREE_CTRL1
- RT5677_CLK_TREE_CTRL2
- RT5677_CLK_TREE_CTRL3
- RT5677_CROSS_OVER_FILTER1
- RT5677_CROSS_OVER_FILTER10
- RT5677_CROSS_OVER_FILTER2
- RT5677_CROSS_OVER_FILTER3
- RT5677_CROSS_OVER_FILTER4
- RT5677_CROSS_OVER_FILTER5
- RT5677_CROSS_OVER_FILTER6
- RT5677_CROSS_OVER_FILTER7
- RT5677_CROSS_OVER_FILTER8
- RT5677_CROSS_OVER_FILTER9
- RT5677_DAC1_DIG_VOL
- RT5677_DAC1_L_MONO_L_VOL_MASK
- RT5677_DAC1_L_MONO_L_VOL_SFT
- RT5677_DAC1_L_SEL_MASK
- RT5677_DAC1_L_SEL_SFT
- RT5677_DAC1_L_STO_L_VOL_MASK
- RT5677_DAC1_L_STO_L_VOL_SFT
- RT5677_DAC1_L_STO_R_VOL_MASK
- RT5677_DAC1_L_STO_R_VOL_SFT
- RT5677_DAC1_L_VOL_MASK
- RT5677_DAC1_L_VOL_SFT
- RT5677_DAC1_R_MONO_R_VOL_MASK
- RT5677_DAC1_R_MONO_R_VOL_SFT
- RT5677_DAC1_R_STO_L_VOL_MASK
- RT5677_DAC1_R_STO_L_VOL_SFT
- RT5677_DAC1_R_STO_R_VOL_MASK
- RT5677_DAC1_R_STO_R_VOL_SFT
- RT5677_DAC1_R_VOL_MASK
- RT5677_DAC1_R_VOL_SFT
- RT5677_DAC2_DIG_VOL
- RT5677_DAC2_L_MONO_L_VOL_MASK
- RT5677_DAC2_L_MONO_L_VOL_SFT
- RT5677_DAC2_L_MONO_R_VOL_MASK
- RT5677_DAC2_L_MONO_R_VOL_SFT
- RT5677_DAC2_L_STO_L_VOL_MASK
- RT5677_DAC2_L_STO_L_VOL_SFT
- RT5677_DAC2_L_VOL_MASK
- RT5677_DAC2_L_VOL_SFT
- RT5677_DAC2_R_MONO_L_VOL_MASK
- RT5677_DAC2_R_MONO_L_VOL_SFT
- RT5677_DAC2_R_MONO_R_VOL_MASK
- RT5677_DAC2_R_MONO_R_VOL_SFT
- RT5677_DAC2_R_STO_R_VOL_MASK
- RT5677_DAC2_R_STO_R_VOL_SFT
- RT5677_DAC2_R_VOL_MASK
- RT5677_DAC2_R_VOL_SFT
- RT5677_DAC3_DIG_VOL
- RT5677_DAC3_L_DD1_L_VOL_MASK
- RT5677_DAC3_L_DD1_L_VOL_SFT
- RT5677_DAC3_L_DD1_R_VOL_MASK
- RT5677_DAC3_L_DD1_R_VOL_SFT
- RT5677_DAC3_L_VOL_MASK
- RT5677_DAC3_L_VOL_SFT
- RT5677_DAC3_R_DD1_L_VOL_MASK
- RT5677_DAC3_R_DD1_L_VOL_SFT
- RT5677_DAC3_R_DD1_R_VOL_MASK
- RT5677_DAC3_R_DD1_R_VOL_SFT
- RT5677_DAC3_R_VOL_MASK
- RT5677_DAC3_R_VOL_SFT
- RT5677_DAC4_DIG_VOL
- RT5677_DAC4_L_DD2_L_VOL_MASK
- RT5677_DAC4_L_DD2_L_VOL_SFT
- RT5677_DAC4_L_DD2_R_VOL_MASK
- RT5677_DAC4_L_DD2_R_VOL_SFT
- RT5677_DAC4_L_VOL_MASK
- RT5677_DAC4_L_VOL_SFT
- RT5677_DAC4_R_DD2_L_VOL_MASK
- RT5677_DAC4_R_DD2_L_VOL_SFT
- RT5677_DAC4_R_DD2_R_VOL_MASK
- RT5677_DAC4_R_DD2_R_VOL_SFT
- RT5677_DAC4_R_VOL_MASK
- RT5677_DAC4_R_VOL_SFT
- RT5677_DAC_OSR_128
- RT5677_DAC_OSR_32
- RT5677_DAC_OSR_64
- RT5677_DAC_OSR_MASK
- RT5677_DAC_OSR_SFT
- RT5677_DA_MONO2L_CLK_SEL_MASK
- RT5677_DA_MONO2L_CLK_SEL_SFT
- RT5677_DA_MONO2R_CLK_SEL_MASK
- RT5677_DA_MONO2R_CLK_SEL_SFT
- RT5677_DA_MONO2_L_FILTER
- RT5677_DA_MONO2_R_FILTER
- RT5677_DA_MONO3L_CLK_SEL_MASK
- RT5677_DA_MONO3L_CLK_SEL_SFT
- RT5677_DA_MONO3R_CLK_SEL_MASK
- RT5677_DA_MONO3R_CLK_SEL_SFT
- RT5677_DA_MONO3_L_FILTER
- RT5677_DA_MONO3_R_FILTER
- RT5677_DA_MONO4L_CLK_SEL_MASK
- RT5677_DA_MONO4L_CLK_SEL_SFT
- RT5677_DA_MONO4R_CLK_SEL_MASK
- RT5677_DA_MONO4R_CLK_SEL_SFT
- RT5677_DA_MONO4_L_FILTER
- RT5677_DA_MONO4_R_FILTER
- RT5677_DA_STEREO_FILTER
- RT5677_DA_STO_CLK_SEL_MASK
- RT5677_DA_STO_CLK_SEL_SFT
- RT5677_DD1_MIXER
- RT5677_DD2_MIXER
- RT5677_DEVICE_ID
- RT5677_DIG_IN_PIN_ST_CTRL1
- RT5677_DIG_IN_PIN_ST_CTRL2
- RT5677_DIG_IN_PIN_ST_CTRL3
- RT5677_DIG_MISC
- RT5677_DIG_VOL_CTRL1
- RT5677_DIG_VOL_CTRL2
- RT5677_DMIC_1L_LH_FALLING
- RT5677_DMIC_1L_LH_MASK
- RT5677_DMIC_1L_LH_RISING
- RT5677_DMIC_1L_LH_SFT
- RT5677_DMIC_1R_LH_FALLING
- RT5677_DMIC_1R_LH_MASK
- RT5677_DMIC_1R_LH_RISING
- RT5677_DMIC_1R_LH_SFT
- RT5677_DMIC_1_DIS
- RT5677_DMIC_1_EN
- RT5677_DMIC_1_EN_MASK
- RT5677_DMIC_1_EN_SFT
- RT5677_DMIC_2L_LH_FALLING
- RT5677_DMIC_2L_LH_MASK
- RT5677_DMIC_2L_LH_RISING
- RT5677_DMIC_2L_LH_SFT
- RT5677_DMIC_2R_LH_FALLING
- RT5677_DMIC_2R_LH_MASK
- RT5677_DMIC_2R_LH_RISING
- RT5677_DMIC_2R_LH_SFT
- RT5677_DMIC_2_DIS
- RT5677_DMIC_2_EN
- RT5677_DMIC_2_EN_MASK
- RT5677_DMIC_2_EN_SFT
- RT5677_DMIC_3L_LH_FALLING
- RT5677_DMIC_3L_LH_MASK
- RT5677_DMIC_3L_LH_RISING
- RT5677_DMIC_3L_LH_SFT
- RT5677_DMIC_3R_LH_FALLING
- RT5677_DMIC_3R_LH_MASK
- RT5677_DMIC_3R_LH_RISING
- RT5677_DMIC_3R_LH_SFT
- RT5677_DMIC_3_DIS
- RT5677_DMIC_3_EN
- RT5677_DMIC_3_EN_MASK
- RT5677_DMIC_3_EN_SFT
- RT5677_DMIC_4L_LH_FALLING
- RT5677_DMIC_4L_LH_MASK
- RT5677_DMIC_4L_LH_RISING
- RT5677_DMIC_4L_LH_SFT
- RT5677_DMIC_4R_LH_FALLING
- RT5677_DMIC_4R_LH_MASK
- RT5677_DMIC_4R_LH_RISING
- RT5677_DMIC_4R_LH_SFT
- RT5677_DMIC_4_DIS
- RT5677_DMIC_4_EN
- RT5677_DMIC_4_EN_MASK
- RT5677_DMIC_4_EN_SFT
- RT5677_DMIC_CLK1
- RT5677_DMIC_CLK2
- RT5677_DMIC_CLK_MASK
- RT5677_DMIC_CLK_SFT
- RT5677_DMIC_CTRL1
- RT5677_DMIC_CTRL2
- RT5677_DMIC_L_STO1_LH_FALLING
- RT5677_DMIC_L_STO1_LH_MASK
- RT5677_DMIC_L_STO1_LH_RISING
- RT5677_DMIC_L_STO1_LH_SFT
- RT5677_DMIC_L_STO2_LH_FALLING
- RT5677_DMIC_L_STO2_LH_MASK
- RT5677_DMIC_L_STO2_LH_RISING
- RT5677_DMIC_L_STO2_LH_SFT
- RT5677_DMIC_L_STO3_LH_FALLING
- RT5677_DMIC_L_STO3_LH_MASK
- RT5677_DMIC_L_STO3_LH_RISING
- RT5677_DMIC_L_STO3_LH_SFT
- RT5677_DMIC_L_STO4_LH_FALLING
- RT5677_DMIC_L_STO4_LH_MASK
- RT5677_DMIC_L_STO4_LH_RISING
- RT5677_DMIC_L_STO4_LH_SFT
- RT5677_DMIC_R_MONO_LH_FALLING
- RT5677_DMIC_R_MONO_LH_MASK
- RT5677_DMIC_R_MONO_LH_RISING
- RT5677_DMIC_R_MONO_LH_SFT
- RT5677_DMIC_R_STO1_LH_FALLING
- RT5677_DMIC_R_STO1_LH_MASK
- RT5677_DMIC_R_STO1_LH_RISING
- RT5677_DMIC_R_STO1_LH_SFT
- RT5677_DMIC_R_STO2_LH_FALLING
- RT5677_DMIC_R_STO2_LH_MASK
- RT5677_DMIC_R_STO2_LH_RISING
- RT5677_DMIC_R_STO2_LH_SFT
- RT5677_DMIC_R_STO3_LH_FALLING
- RT5677_DMIC_R_STO3_LH_MASK
- RT5677_DMIC_R_STO3_LH_RISING
- RT5677_DMIC_R_STO3_LH_SFT
- RT5677_DMIC_R_STO4_LH_FALLING
- RT5677_DMIC_R_STO4_LH_MASK
- RT5677_DMIC_R_STO4_LH_RISING
- RT5677_DMIC_R_STO4_LH_SFT
- RT5677_DRC1_CTRL1
- RT5677_DRC1_CTRL2
- RT5677_DRC1_CTRL3
- RT5677_DRC1_CTRL4
- RT5677_DRC1_CTRL5
- RT5677_DRC1_CTRL6
- RT5677_DRC1_HL_CTRL1
- RT5677_DRC1_HL_CTRL2
- RT5677_DRC2_CTRL1
- RT5677_DRC2_CTRL2
- RT5677_DRC2_CTRL3
- RT5677_DRC2_CTRL4
- RT5677_DRC2_CTRL5
- RT5677_DRC2_CTRL6
- RT5677_DRC2_HL_CTRL1
- RT5677_DRC2_HL_CTRL2
- RT5677_DRV_NAME
- RT5677_DSP_ASRC_I_1_0
- RT5677_DSP_ASRC_I_1_5
- RT5677_DSP_ASRC_I_2_0
- RT5677_DSP_ASRC_I_3_0
- RT5677_DSP_ASRC_I_MASK
- RT5677_DSP_ASRC_I_MCLK
- RT5677_DSP_ASRC_I_PLL1
- RT5677_DSP_ASRC_I_RCCLK
- RT5677_DSP_ASRC_I_SFT
- RT5677_DSP_ASRC_I_SLIM
- RT5677_DSP_ASRC_I_SRC
- RT5677_DSP_ASRC_I_SRC_SFT
- RT5677_DSP_ASRC_O_1_0
- RT5677_DSP_ASRC_O_1_5
- RT5677_DSP_ASRC_O_2_0
- RT5677_DSP_ASRC_O_3_0
- RT5677_DSP_ASRC_O_MASK
- RT5677_DSP_ASRC_O_MCLK
- RT5677_DSP_ASRC_O_PLL1
- RT5677_DSP_ASRC_O_RCCLK
- RT5677_DSP_ASRC_O_SFT
- RT5677_DSP_ASRC_O_SLIM
- RT5677_DSP_ASRC_O_SRC
- RT5677_DSP_ASRC_O_SRC_SFT
- RT5677_DSP_BUS_PD_1
- RT5677_DSP_BUS_PD_12
- RT5677_DSP_BUS_PD_16
- RT5677_DSP_BUS_PD_2
- RT5677_DSP_BUS_PD_3
- RT5677_DSP_BUS_PD_4
- RT5677_DSP_BUS_PD_6
- RT5677_DSP_BUS_PD_8
- RT5677_DSP_BUS_PD_MASK
- RT5677_DSP_BUS_PD_SFT
- RT5677_DSP_CLK_SRC_BYPASS
- RT5677_DSP_CLK_SRC_MASK
- RT5677_DSP_CLK_SRC_PLL2
- RT5677_DSP_CLK_SRC_SFT
- RT5677_DSP_I2C_ADDR_LSB
- RT5677_DSP_I2C_ADDR_MSB
- RT5677_DSP_I2C_DATA_LSB
- RT5677_DSP_I2C_DATA_MSB
- RT5677_DSP_I2C_OP_CODE
- RT5677_DSP_IB_01_H
- RT5677_DSP_IB_01_H_SFT
- RT5677_DSP_IB_01_L
- RT5677_DSP_IB_01_L_SFT
- RT5677_DSP_IB_23_H
- RT5677_DSP_IB_23_H_SFT
- RT5677_DSP_IB_23_L
- RT5677_DSP_IB_23_L_SFT
- RT5677_DSP_IB_45_H
- RT5677_DSP_IB_45_H_SFT
- RT5677_DSP_IB_45_L
- RT5677_DSP_IB_45_L_SFT
- RT5677_DSP_IB_6_H
- RT5677_DSP_IB_6_H_SFT
- RT5677_DSP_IB_6_L
- RT5677_DSP_IB_6_L_SFT
- RT5677_DSP_IB_7_H
- RT5677_DSP_IB_7_H_SFT
- RT5677_DSP_IB_7_L
- RT5677_DSP_IB_7_L_SFT
- RT5677_DSP_IB_8_H
- RT5677_DSP_IB_8_H_SFT
- RT5677_DSP_IB_8_L
- RT5677_DSP_IB_8_L_SFT
- RT5677_DSP_IB_9_H
- RT5677_DSP_IB_9_H_SFT
- RT5677_DSP_IB_9_L
- RT5677_DSP_IB_9_L_SFT
- RT5677_DSP_INB1_SRC_CTRL1
- RT5677_DSP_INB1_SRC_CTRL2
- RT5677_DSP_INB1_SRC_CTRL3
- RT5677_DSP_INB1_SRC_CTRL4
- RT5677_DSP_INB2_SRC_CTRL1
- RT5677_DSP_INB2_SRC_CTRL2
- RT5677_DSP_INB2_SRC_CTRL3
- RT5677_DSP_INB2_SRC_CTRL4
- RT5677_DSP_INB3_SRC_CTRL1
- RT5677_DSP_INB3_SRC_CTRL2
- RT5677_DSP_INB3_SRC_CTRL3
- RT5677_DSP_INB3_SRC_CTRL4
- RT5677_DSP_INB_CTRL1
- RT5677_DSP_INB_CTRL2
- RT5677_DSP_IN_OUTB_CTRL
- RT5677_DSP_OB_0_3_CLK_SEL_MASK
- RT5677_DSP_OB_0_3_CLK_SEL_SFT
- RT5677_DSP_OB_0_3_FILTER
- RT5677_DSP_OB_4_7_CLK_SEL_MASK
- RT5677_DSP_OB_4_7_CLK_SEL_SFT
- RT5677_DSP_OB_4_7_FILTER
- RT5677_DSP_OUTB0_1_DIG_VOL
- RT5677_DSP_OUTB1_SRC_CTRL1
- RT5677_DSP_OUTB1_SRC_CTRL2
- RT5677_DSP_OUTB1_SRC_CTRL3
- RT5677_DSP_OUTB1_SRC_CTRL4
- RT5677_DSP_OUTB2_3_DIG_VOL
- RT5677_DSP_OUTB2_SRC_CTRL1
- RT5677_DSP_OUTB2_SRC_CTRL2
- RT5677_DSP_OUTB2_SRC_CTRL3
- RT5677_DSP_OUTB2_SRC_CTRL4
- RT5677_DSP_OUTB4_5_DIG_VOL
- RT5677_DSP_OUTB6_7_DIG_VOL
- RT5677_DSP_OUTB_0123_MIXER_CTRL
- RT5677_DSP_OUTB_45_MIXER_CTRL
- RT5677_DSP_OUTB_67_MIXER_CTRL
- RT5677_EN_GPIO_JD1_STICKY
- RT5677_EN_GPIO_JD1_STICKY_SFT
- RT5677_EN_GPIO_JD2_STICKY
- RT5677_EN_GPIO_JD2_STICKY_SFT
- RT5677_EN_GPIO_JD3_STICKY
- RT5677_EN_GPIO_JD3_STICKY_SFT
- RT5677_EN_IRQ_GPIO_JD1
- RT5677_EN_IRQ_GPIO_JD1_SFT
- RT5677_EN_IRQ_GPIO_JD2
- RT5677_EN_IRQ_GPIO_JD2_SFT
- RT5677_EN_IRQ_GPIO_JD3
- RT5677_EN_IRQ_GPIO_JD3_SFT
- RT5677_EN_IRQ_MICBIAS1_OVCD
- RT5677_EN_IRQ_MICBIAS1_OVCD_SFT
- RT5677_EN_MICBIAS1_OVCD_STICKY
- RT5677_EN_MICBIAS1_OVCD_STICKY_SFT
- RT5677_EQ_CTRL1
- RT5677_EQ_CTRL2
- RT5677_EQ_CTRL3
- RT5677_FIRMWARE1
- RT5677_FIRMWARE2
- RT5677_FORMATS
- RT5677_FUNC_MODE_DMIC_GPIO
- RT5677_FUNC_MODE_JTAG
- RT5677_FUNC_MODE_MASK
- RT5677_FUNC_MODE_SFT
- RT5677_GEN_CTRL1
- RT5677_GEN_CTRL2
- RT5677_GLB_CLK1
- RT5677_GLB_CLK2
- RT5677_GPIO1
- RT5677_GPIO1_DIR_IN
- RT5677_GPIO1_DIR_MASK
- RT5677_GPIO1_DIR_OUT
- RT5677_GPIO1_DIR_SFT
- RT5677_GPIO1_OUT_HI
- RT5677_GPIO1_OUT_LO
- RT5677_GPIO1_OUT_MASK
- RT5677_GPIO1_OUT_SFT
- RT5677_GPIO1_PIN_GPIO1
- RT5677_GPIO1_PIN_IRQ
- RT5677_GPIO1_PIN_MASK
- RT5677_GPIO1_PIN_SFT
- RT5677_GPIO1_P_INV
- RT5677_GPIO1_P_MASK
- RT5677_GPIO1_P_NOR
- RT5677_GPIO1_P_SFT
- RT5677_GPIO1_STATUS_MASK
- RT5677_GPIO1_STATUS_SFT
- RT5677_GPIO2
- RT5677_GPIO2_DIR_IN
- RT5677_GPIO2_DIR_MASK
- RT5677_GPIO2_DIR_OUT
- RT5677_GPIO2_DIR_SFT
- RT5677_GPIO2_OUT_HI
- RT5677_GPIO2_OUT_LO
- RT5677_GPIO2_OUT_MASK
- RT5677_GPIO2_OUT_SFT
- RT5677_GPIO2_P_INV
- RT5677_GPIO2_P_MASK
- RT5677_GPIO2_P_NOR
- RT5677_GPIO2_P_SFT
- RT5677_GPIO2_STATUS_MASK
- RT5677_GPIO2_STATUS_SFT
- RT5677_GPIO3
- RT5677_GPIO3_DIR_IN
- RT5677_GPIO3_DIR_MASK
- RT5677_GPIO3_DIR_OUT
- RT5677_GPIO3_DIR_SFT
- RT5677_GPIO3_OUT_HI
- RT5677_GPIO3_OUT_LO
- RT5677_GPIO3_OUT_MASK
- RT5677_GPIO3_OUT_SFT
- RT5677_GPIO3_P_INV
- RT5677_GPIO3_P_MASK
- RT5677_GPIO3_P_NOR
- RT5677_GPIO3_P_SFT
- RT5677_GPIO3_STATUS_MASK
- RT5677_GPIO3_STATUS_SFT
- RT5677_GPIO4
- RT5677_GPIO4_DIR_IN
- RT5677_GPIO4_DIR_MASK
- RT5677_GPIO4_DIR_OUT
- RT5677_GPIO4_DIR_SFT
- RT5677_GPIO4_OUT_HI
- RT5677_GPIO4_OUT_LO
- RT5677_GPIO4_OUT_MASK
- RT5677_GPIO4_OUT_SFT
- RT5677_GPIO4_P_INV
- RT5677_GPIO4_P_MASK
- RT5677_GPIO4_P_NOR
- RT5677_GPIO4_P_SFT
- RT5677_GPIO4_STATUS_MASK
- RT5677_GPIO4_STATUS_SFT
- RT5677_GPIO5
- RT5677_GPIO5_DIR_IN
- RT5677_GPIO5_DIR_MASK
- RT5677_GPIO5_DIR_OUT
- RT5677_GPIO5_DIR_SFT
- RT5677_GPIO5_FUNC_DMIC
- RT5677_GPIO5_FUNC_GPIO
- RT5677_GPIO5_FUNC_MASK
- RT5677_GPIO5_OUT_HI
- RT5677_GPIO5_OUT_LO
- RT5677_GPIO5_OUT_MASK
- RT5677_GPIO5_OUT_SFT
- RT5677_GPIO5_P_INV
- RT5677_GPIO5_P_MASK
- RT5677_GPIO5_P_NOR
- RT5677_GPIO5_P_SFT
- RT5677_GPIO5_STATUS_MASK
- RT5677_GPIO5_STATUS_SFT
- RT5677_GPIO6
- RT5677_GPIO6_DIR_IN
- RT5677_GPIO6_DIR_MASK
- RT5677_GPIO6_DIR_OUT
- RT5677_GPIO6_DIR_SFT
- RT5677_GPIO6_OUT_HI
- RT5677_GPIO6_OUT_LO
- RT5677_GPIO6_OUT_MASK
- RT5677_GPIO6_OUT_SFT
- RT5677_GPIO6_P_INV
- RT5677_GPIO6_P_MASK
- RT5677_GPIO6_P_NOR
- RT5677_GPIO6_P_SFT
- RT5677_GPIO6_STATUS_MASK
- RT5677_GPIO6_STATUS_SFT
- RT5677_GPIO_CTRL1
- RT5677_GPIO_CTRL2
- RT5677_GPIO_CTRL3
- RT5677_GPIO_DSP_INT
- RT5677_GPIO_HOTWORD_DET_L
- RT5677_GPIO_HP_AMP_SHDN_L
- RT5677_GPIO_MIC_PRESENT_L
- RT5677_GPIO_NUM
- RT5677_GPIO_PLUG_DET
- RT5677_GPIO_ST
- RT5677_HAP_GENE_CTRL1
- RT5677_HAP_GENE_CTRL10
- RT5677_HAP_GENE_CTRL2
- RT5677_HAP_GENE_CTRL3
- RT5677_HAP_GENE_CTRL4
- RT5677_HAP_GENE_CTRL5
- RT5677_HAP_GENE_CTRL6
- RT5677_HAP_GENE_CTRL7
- RT5677_HAP_GENE_CTRL8
- RT5677_HAP_GENE_CTRL9
- RT5677_I2C_MASTER_CTRL1
- RT5677_I2C_MASTER_CTRL2
- RT5677_I2C_MASTER_CTRL3
- RT5677_I2C_MASTER_CTRL4
- RT5677_I2C_MASTER_CTRL5
- RT5677_I2C_MASTER_CTRL6
- RT5677_I2C_MASTER_CTRL7
- RT5677_I2C_MASTER_CTRL8
- RT5677_I2S1_CLK_SEL_MASK
- RT5677_I2S1_CLK_SEL_SFT
- RT5677_I2S1_SDP
- RT5677_I2S1_SOURCE
- RT5677_I2S2_CLK_SEL_MASK
- RT5677_I2S2_CLK_SEL_SFT
- RT5677_I2S2_SDP
- RT5677_I2S2_SOURCE
- RT5677_I2S3_CLK_SEL_MASK
- RT5677_I2S3_CLK_SEL_SFT
- RT5677_I2S3_SDP
- RT5677_I2S3_SOURCE
- RT5677_I2S4_CLK_SEL_MASK
- RT5677_I2S4_CLK_SEL_SFT
- RT5677_I2S4_SDP
- RT5677_I2S4_SOURCE
- RT5677_I2S_BCLK_MS2_32
- RT5677_I2S_BCLK_MS2_64
- RT5677_I2S_BCLK_MS2_MASK
- RT5677_I2S_BCLK_MS2_SFT
- RT5677_I2S_BCLK_MS3_32
- RT5677_I2S_BCLK_MS3_64
- RT5677_I2S_BCLK_MS3_MASK
- RT5677_I2S_BCLK_MS3_SFT
- RT5677_I2S_BCLK_MS4_32
- RT5677_I2S_BCLK_MS4_64
- RT5677_I2S_BCLK_MS4_MASK
- RT5677_I2S_BCLK_MS4_SFT
- RT5677_I2S_BP_INV
- RT5677_I2S_BP_MASK
- RT5677_I2S_BP_NOR
- RT5677_I2S_BP_SFT
- RT5677_I2S_DF_I2S
- RT5677_I2S_DF_LEFT
- RT5677_I2S_DF_MASK
- RT5677_I2S_DF_PCM_A
- RT5677_I2S_DF_PCM_B
- RT5677_I2S_DF_SFT
- RT5677_I2S_DL_16
- RT5677_I2S_DL_20
- RT5677_I2S_DL_24
- RT5677_I2S_DL_8
- RT5677_I2S_DL_MASK
- RT5677_I2S_DL_SFT
- RT5677_I2S_I_CP_A_LAW
- RT5677_I2S_I_CP_MASK
- RT5677_I2S_I_CP_OFF
- RT5677_I2S_I_CP_SFT
- RT5677_I2S_I_CP_U_LAW
- RT5677_I2S_MS_M
- RT5677_I2S_MS_MASK
- RT5677_I2S_MS_S
- RT5677_I2S_MS_SFT
- RT5677_I2S_O_CP_A_LAW
- RT5677_I2S_O_CP_MASK
- RT5677_I2S_O_CP_OFF
- RT5677_I2S_O_CP_SFT
- RT5677_I2S_O_CP_U_LAW
- RT5677_I2S_PD1_1
- RT5677_I2S_PD1_12
- RT5677_I2S_PD1_16
- RT5677_I2S_PD1_2
- RT5677_I2S_PD1_3
- RT5677_I2S_PD1_4
- RT5677_I2S_PD1_6
- RT5677_I2S_PD1_8
- RT5677_I2S_PD1_MASK
- RT5677_I2S_PD1_SFT
- RT5677_I2S_PD2_1
- RT5677_I2S_PD2_12
- RT5677_I2S_PD2_16
- RT5677_I2S_PD2_2
- RT5677_I2S_PD2_3
- RT5677_I2S_PD2_4
- RT5677_I2S_PD2_6
- RT5677_I2S_PD2_8
- RT5677_I2S_PD2_MASK
- RT5677_I2S_PD2_SFT
- RT5677_I2S_PD3_1
- RT5677_I2S_PD3_12
- RT5677_I2S_PD3_16
- RT5677_I2S_PD3_2
- RT5677_I2S_PD3_3
- RT5677_I2S_PD3_4
- RT5677_I2S_PD3_6
- RT5677_I2S_PD3_8
- RT5677_I2S_PD3_MASK
- RT5677_I2S_PD3_SFT
- RT5677_I2S_PD4_1
- RT5677_I2S_PD4_12
- RT5677_I2S_PD4_16
- RT5677_I2S_PD4_2
- RT5677_I2S_PD4_3
- RT5677_I2S_PD4_4
- RT5677_I2S_PD4_6
- RT5677_I2S_PD4_8
- RT5677_I2S_PD4_MASK
- RT5677_I2S_PD4_SFT
- RT5677_I2S_PD5_1
- RT5677_I2S_PD5_12
- RT5677_I2S_PD5_16
- RT5677_I2S_PD5_2
- RT5677_I2S_PD5_3
- RT5677_I2S_PD5_4
- RT5677_I2S_PD5_6
- RT5677_I2S_PD5_8
- RT5677_I2S_PD5_MASK
- RT5677_I2S_PD5_SFT
- RT5677_I2S_PD6_1
- RT5677_I2S_PD6_12
- RT5677_I2S_PD6_16
- RT5677_I2S_PD6_2
- RT5677_I2S_PD6_3
- RT5677_I2S_PD6_4
- RT5677_I2S_PD6_6
- RT5677_I2S_PD6_8
- RT5677_I2S_PD6_MASK
- RT5677_I2S_PD6_SFT
- RT5677_I2S_PD7_1
- RT5677_I2S_PD7_12
- RT5677_I2S_PD7_16
- RT5677_I2S_PD7_2
- RT5677_I2S_PD7_3
- RT5677_I2S_PD7_4
- RT5677_I2S_PD7_6
- RT5677_I2S_PD7_8
- RT5677_I2S_PD7_MASK
- RT5677_I2S_PD7_SFT
- RT5677_I2S_PD8_1
- RT5677_I2S_PD8_12
- RT5677_I2S_PD8_16
- RT5677_I2S_PD8_2
- RT5677_I2S_PD8_3
- RT5677_I2S_PD8_4
- RT5677_I2S_PD8_6
- RT5677_I2S_PD8_8
- RT5677_I2S_PD8_MASK
- RT5677_I2S_PD8_SFT
- RT5677_IB01_SRC_MASK
- RT5677_IB01_SRC_SFT
- RT5677_IB23_SRC_MASK
- RT5677_IB23_SRC_SFT
- RT5677_IB45_SRC_MASK
- RT5677_IB45_SRC_SFT
- RT5677_IB6_SRC_MASK
- RT5677_IB6_SRC_SFT
- RT5677_IB7_SRC_MASK
- RT5677_IB7_SRC_SFT
- RT5677_IB8_SRC_MASK
- RT5677_IB8_SRC_SFT
- RT5677_IB9_SRC_MASK
- RT5677_IB9_SRC_SFT
- RT5677_IF1_ADC1_MASK
- RT5677_IF1_ADC1_SFT
- RT5677_IF1_ADC1_SWAP_MASK
- RT5677_IF1_ADC1_SWAP_SFT
- RT5677_IF1_ADC2_MASK
- RT5677_IF1_ADC2_SFT
- RT5677_IF1_ADC2_SWAP_MASK
- RT5677_IF1_ADC2_SWAP_SFT
- RT5677_IF1_ADC3_MASK
- RT5677_IF1_ADC3_SFT
- RT5677_IF1_ADC3_SWAP_MASK
- RT5677_IF1_ADC3_SWAP_SFT
- RT5677_IF1_ADC4_MASK
- RT5677_IF1_ADC4_SFT
- RT5677_IF1_ADC4_SWAP_MASK
- RT5677_IF1_ADC4_SWAP_SFT
- RT5677_IF1_ADC_CTRL_MASK
- RT5677_IF1_ADC_CTRL_SFT
- RT5677_IF1_ADC_MODE_I2S
- RT5677_IF1_ADC_MODE_MASK
- RT5677_IF1_ADC_MODE_SFT
- RT5677_IF1_ADC_MODE_TDM
- RT5677_IF1_DAC0_MASK
- RT5677_IF1_DAC0_SFT
- RT5677_IF1_DAC1_MASK
- RT5677_IF1_DAC1_SFT
- RT5677_IF1_DAC2_MASK
- RT5677_IF1_DAC2_SFT
- RT5677_IF1_DAC3_MASK
- RT5677_IF1_DAC3_SFT
- RT5677_IF1_DAC4_MASK
- RT5677_IF1_DAC4_SFT
- RT5677_IF1_DAC5_MASK
- RT5677_IF1_DAC5_SFT
- RT5677_IF1_DAC6_MASK
- RT5677_IF1_DAC6_SFT
- RT5677_IF1_DAC7_MASK
- RT5677_IF1_DAC7_SFT
- RT5677_IF2_ADC1_MASK
- RT5677_IF2_ADC1_SFT
- RT5677_IF2_ADC1_SWAP_MASK
- RT5677_IF2_ADC1_SWAP_SFT
- RT5677_IF2_ADC2_MASK
- RT5677_IF2_ADC2_SFT
- RT5677_IF2_ADC2_SWAP_MASK
- RT5677_IF2_ADC2_SWAP_SFT
- RT5677_IF2_ADC3_MASK
- RT5677_IF2_ADC3_SFT
- RT5677_IF2_ADC3_SWAP_MASK
- RT5677_IF2_ADC3_SWAP_SFT
- RT5677_IF2_ADC4_MASK
- RT5677_IF2_ADC4_SFT
- RT5677_IF2_ADC4_SWAP_MASK
- RT5677_IF2_ADC4_SWAP_SFT
- RT5677_IF2_ADC_CTRL_MASK
- RT5677_IF2_ADC_CTRL_SFT
- RT5677_IF2_ADC_MODE_I2S
- RT5677_IF2_ADC_MODE_MASK
- RT5677_IF2_ADC_MODE_SFT
- RT5677_IF2_ADC_MODE_TDM
- RT5677_IF2_DAC0_MASK
- RT5677_IF2_DAC0_SFT
- RT5677_IF2_DAC1_MASK
- RT5677_IF2_DAC1_SFT
- RT5677_IF2_DAC2_MASK
- RT5677_IF2_DAC2_SFT
- RT5677_IF2_DAC3_MASK
- RT5677_IF2_DAC3_SFT
- RT5677_IF2_DAC4_MASK
- RT5677_IF2_DAC4_SFT
- RT5677_IF2_DAC5_MASK
- RT5677_IF2_DAC5_SFT
- RT5677_IF2_DAC6_MASK
- RT5677_IF2_DAC6_SFT
- RT5677_IF2_DAC7_MASK
- RT5677_IF2_DAC7_SFT
- RT5677_IF3_ADC_IN_MASK
- RT5677_IF3_ADC_IN_SFT
- RT5677_IF3_ADC_SEL_MASK
- RT5677_IF3_ADC_SEL_SFT
- RT5677_IF3_DAC_SEL_MASK
- RT5677_IF3_DAC_SEL_SFT
- RT5677_IF3_DATA
- RT5677_IF4_ADC_IN_MASK
- RT5677_IF4_ADC_IN_SFT
- RT5677_IF4_ADC_SEL_MASK
- RT5677_IF4_ADC_SEL_SFT
- RT5677_IF4_DAC_SEL_MASK
- RT5677_IF4_DAC_SEL_SFT
- RT5677_IF4_DATA
- RT5677_IF_DSP_DAC2_MIXER
- RT5677_IF_DSP_DAC3_4_MIXER
- RT5677_IN1
- RT5677_INIT_REG_LEN
- RT5677_INV_GPIO_JD1
- RT5677_INV_GPIO_JD1_SFT
- RT5677_INV_GPIO_JD2
- RT5677_INV_GPIO_JD2_SFT
- RT5677_INV_GPIO_JD3
- RT5677_INV_GPIO_JD3_SFT
- RT5677_INV_MICBIAS1_OVCD
- RT5677_INV_MICBIAS1_OVCD_SFT
- RT5677_IN_DF1
- RT5677_IN_DF1_SFT
- RT5677_IN_DF2
- RT5677_IN_DF2_SFT
- RT5677_IPTV_MODE_GPIO
- RT5677_IPTV_MODE_IPTV
- RT5677_IPTV_MODE_MASK
- RT5677_IPTV_MODE_SFT
- RT5677_IRQ_CTRL1
- RT5677_IRQ_CTRL2
- RT5677_IRQ_DEBOUNCE_SEL_MASK
- RT5677_IRQ_DEBOUNCE_SEL_MCLK
- RT5677_IRQ_DEBOUNCE_SEL_RC
- RT5677_IRQ_DEBOUNCE_SEL_SLIM
- RT5677_IRQ_JD1
- RT5677_IRQ_JD2
- RT5677_IRQ_JD3
- RT5677_IRQ_NUM
- RT5677_JD_CTRL1
- RT5677_JD_CTRL2
- RT5677_JD_CTRL3
- RT5677_LDO1_SEL_MASK
- RT5677_LDO1_SEL_SFT
- RT5677_LDO2_SEL_MASK
- RT5677_LDO2_SEL_SFT
- RT5677_LOUT1
- RT5677_LOUT1_ENH_DRV
- RT5677_LOUT1_ENH_DRV_SFT
- RT5677_LOUT1_L_DF
- RT5677_LOUT1_L_DF_SFT
- RT5677_LOUT1_L_MUTE
- RT5677_LOUT1_L_MUTE_SFT
- RT5677_LOUT2_ENH_DRV
- RT5677_LOUT2_ENH_DRV_SFT
- RT5677_LOUT2_L_DF
- RT5677_LOUT2_L_DF_SFT
- RT5677_LOUT2_L_MUTE
- RT5677_LOUT2_L_MUTE_SFT
- RT5677_LOUT3_ENH_DRV
- RT5677_LOUT3_ENH_DRV_SFT
- RT5677_LOUT3_L_DF
- RT5677_LOUT3_L_DF_SFT
- RT5677_LOUT3_L_MUTE
- RT5677_LOUT3_L_MUTE_SFT
- RT5677_L_MUTE
- RT5677_L_MUTE_SFT
- RT5677_L_VOL_MASK
- RT5677_L_VOL_SFT
- RT5677_MB_DRC_CTRL1
- RT5677_MCLK1_SRC
- RT5677_MCLK2_SRC
- RT5677_MCLK_SRC_MASK
- RT5677_MCLK_SRC_SFT
- RT5677_MICBIAS
- RT5677_MICBIAS1_CTRL_VDD_1_8V
- RT5677_MICBIAS1_CTRL_VDD_3_3V
- RT5677_MICBIAS1_CTRL_VDD_MASK
- RT5677_MICBIAS1_CTRL_VDD_SFT
- RT5677_MICBIAS1_OUTVOLT_2_25V
- RT5677_MICBIAS1_OUTVOLT_2_7V
- RT5677_MICBIAS1_OUTVOLT_MASK
- RT5677_MICBIAS1_OUTVOLT_SFT
- RT5677_MICBIAS1_OVCD_DIS
- RT5677_MICBIAS1_OVCD_EN
- RT5677_MICBIAS1_OVCD_MASK
- RT5677_MICBIAS1_OVCD_SHIFT
- RT5677_MICBIAS1_OVTH_1280UA
- RT5677_MICBIAS1_OVTH_1920UA
- RT5677_MICBIAS1_OVTH_640UA
- RT5677_MICBIAS1_OVTH_MASK
- RT5677_MICBIAS1_OVTH_SFT
- RT5677_MONO_ADC_COMP_MASK
- RT5677_MONO_ADC_COMP_SFT
- RT5677_MONO_ADC_DIG_VOL
- RT5677_MONO_ADC_HI_FILTER1
- RT5677_MONO_ADC_HI_FILTER2
- RT5677_MONO_ADC_L_BST_MASK
- RT5677_MONO_ADC_L_BST_SFT
- RT5677_MONO_ADC_L_VOL_MASK
- RT5677_MONO_ADC_L_VOL_SFT
- RT5677_MONO_ADC_MIXER
- RT5677_MONO_ADC_R_BST_MASK
- RT5677_MONO_ADC_R_BST_SFT
- RT5677_MONO_ADC_R_VOL_MASK
- RT5677_MONO_ADC_R_VOL_SFT
- RT5677_MONO_DAC_MIXER
- RT5677_MONO_L_DD1_L_VOL_MASK
- RT5677_MONO_L_DD1_L_VOL_SFT
- RT5677_MONO_L_DD2_L_VOL_MASK
- RT5677_MONO_L_DD2_L_VOL_SFT
- RT5677_MONO_R_DD1_R_VOL_MASK
- RT5677_MONO_R_DD1_R_VOL_SFT
- RT5677_MONO_R_DD2_R_VOL_MASK
- RT5677_MONO_R_DD2_R_VOL_SFT
- RT5677_M_ADDA_MIXER1_L
- RT5677_M_ADDA_MIXER1_L_SFT
- RT5677_M_ADDA_MIXER1_R
- RT5677_M_ADDA_MIXER1_R_SFT
- RT5677_M_DAC1_L
- RT5677_M_DAC1_L_MONO_L
- RT5677_M_DAC1_L_MONO_L_SFT
- RT5677_M_DAC1_L_SFT
- RT5677_M_DAC1_L_STO_L
- RT5677_M_DAC1_L_STO_L_SFT
- RT5677_M_DAC1_L_STO_R
- RT5677_M_DAC1_L_STO_R_SFT
- RT5677_M_DAC1_R
- RT5677_M_DAC1_R_MONO_R
- RT5677_M_DAC1_R_MONO_R_SFT
- RT5677_M_DAC1_R_SFT
- RT5677_M_DAC1_R_STO_L
- RT5677_M_DAC1_R_STO_L_SFT
- RT5677_M_DAC1_R_STO_R
- RT5677_M_DAC1_R_STO_R_SFT
- RT5677_M_DAC2_L_MONO_L
- RT5677_M_DAC2_L_MONO_L_SFT
- RT5677_M_DAC2_L_MONO_R
- RT5677_M_DAC2_L_MONO_R_SFT
- RT5677_M_DAC2_L_STO_L
- RT5677_M_DAC2_L_STO_L_SFT
- RT5677_M_DAC2_L_VOL
- RT5677_M_DAC2_L_VOL_SFT
- RT5677_M_DAC2_R_MONO_L
- RT5677_M_DAC2_R_MONO_L_SFT
- RT5677_M_DAC2_R_MONO_R
- RT5677_M_DAC2_R_MONO_R_SFT
- RT5677_M_DAC2_R_STO_R
- RT5677_M_DAC2_R_STO_R_SFT
- RT5677_M_DAC2_R_VOL
- RT5677_M_DAC2_R_VOL_SFT
- RT5677_M_DAC3_L_DD1_L
- RT5677_M_DAC3_L_DD1_L_SFT
- RT5677_M_DAC3_L_DD1_R
- RT5677_M_DAC3_L_DD1_R_SFT
- RT5677_M_DAC3_L_VOL
- RT5677_M_DAC3_L_VOL_SFT
- RT5677_M_DAC3_R_DD1_L
- RT5677_M_DAC3_R_DD1_L_SFT
- RT5677_M_DAC3_R_DD1_R
- RT5677_M_DAC3_R_DD1_R_SFT
- RT5677_M_DAC3_R_VOL
- RT5677_M_DAC3_R_VOL_SFT
- RT5677_M_DAC4_L_DD2_L
- RT5677_M_DAC4_L_DD2_L_SFT
- RT5677_M_DAC4_L_DD2_R
- RT5677_M_DAC4_L_DD2_R_SFT
- RT5677_M_DAC4_L_VOL
- RT5677_M_DAC4_L_VOL_SFT
- RT5677_M_DAC4_R_DD2_L
- RT5677_M_DAC4_R_DD2_L_SFT
- RT5677_M_DAC4_R_DD2_R
- RT5677_M_DAC4_R_DD2_R_SFT
- RT5677_M_DAC4_R_VOL
- RT5677_M_DAC4_R_VOL_SFT
- RT5677_M_MONO_ADC_L1
- RT5677_M_MONO_ADC_L1_SFT
- RT5677_M_MONO_ADC_L2
- RT5677_M_MONO_ADC_L2_SFT
- RT5677_M_MONO_ADC_R1
- RT5677_M_MONO_ADC_R1_SFT
- RT5677_M_MONO_ADC_R2
- RT5677_M_MONO_ADC_R2_SFT
- RT5677_M_MONO_L_DD1_L
- RT5677_M_MONO_L_DD1_L_SFT
- RT5677_M_MONO_L_DD2_L
- RT5677_M_MONO_L_DD2_L_SFT
- RT5677_M_MONO_R_DD1_R
- RT5677_M_MONO_R_DD1_R_SFT
- RT5677_M_MONO_R_DD2_R
- RT5677_M_MONO_R_DD2_R_SFT
- RT5677_M_PDM1_L
- RT5677_M_PDM1_L_SFT
- RT5677_M_PDM1_R
- RT5677_M_PDM1_R_SFT
- RT5677_M_PDM2_L
- RT5677_M_PDM2_L_SFT
- RT5677_M_PDM2_R
- RT5677_M_PDM2_R_SFT
- RT5677_M_STO1_ADC_L1
- RT5677_M_STO1_ADC_L1_SFT
- RT5677_M_STO1_ADC_L2
- RT5677_M_STO1_ADC_L2_SFT
- RT5677_M_STO1_ADC_R1
- RT5677_M_STO1_ADC_R1_SFT
- RT5677_M_STO1_ADC_R2
- RT5677_M_STO1_ADC_R2_SFT
- RT5677_M_STO2_ADC_L1
- RT5677_M_STO2_ADC_L1_SFT
- RT5677_M_STO2_ADC_L2
- RT5677_M_STO2_ADC_L2_SFT
- RT5677_M_STO2_ADC_R1
- RT5677_M_STO2_ADC_R1_SFT
- RT5677_M_STO2_ADC_R2
- RT5677_M_STO2_ADC_R2_SFT
- RT5677_M_STO3_ADC_L1
- RT5677_M_STO3_ADC_L1_SFT
- RT5677_M_STO3_ADC_L2
- RT5677_M_STO3_ADC_L2_SFT
- RT5677_M_STO3_ADC_R1
- RT5677_M_STO3_ADC_R1_SFT
- RT5677_M_STO3_ADC_R2
- RT5677_M_STO3_ADC_R2_SFT
- RT5677_M_STO4_ADC_L1
- RT5677_M_STO4_ADC_L1_SFT
- RT5677_M_STO4_ADC_L2
- RT5677_M_STO4_ADC_L2_SFT
- RT5677_M_STO4_ADC_R1
- RT5677_M_STO4_ADC_R1_SFT
- RT5677_M_STO4_ADC_R2
- RT5677_M_STO4_ADC_R2_SFT
- RT5677_M_STO_L_DD1_L
- RT5677_M_STO_L_DD1_L_SFT
- RT5677_M_STO_L_DD2_L
- RT5677_M_STO_L_DD2_L_SFT
- RT5677_M_STO_R_DD1_R
- RT5677_M_STO_R_DD1_R_SFT
- RT5677_M_STO_R_DD2_R
- RT5677_M_STO_R_DD2_R_SFT
- RT5677_M_ST_DAC1_L
- RT5677_M_ST_DAC1_L_SFT
- RT5677_M_ST_DAC1_R
- RT5677_M_ST_DAC1_R_SFT
- RT5677_M_ST_DAC2_L
- RT5677_M_ST_DAC2_L_SFT
- RT5677_M_ST_DAC2_R
- RT5677_M_ST_DAC2_R_SFT
- RT5677_PAD_DRV_CTRL
- RT5677_PDM1_BUSY
- RT5677_PDM1_DATA_CTRL2
- RT5677_PDM1_DATA_CTRL3
- RT5677_PDM1_DATA_CTRL4
- RT5677_PDM1_EXE
- RT5677_PDM1_I2C_BUSY
- RT5677_PDM1_I2C_CMD
- RT5677_PDM1_I2C_EXE
- RT5677_PDM1_I2C_ID
- RT5677_PDM1_PW_DOWN
- RT5677_PDM2_BUSY
- RT5677_PDM2_DATA_CTRL2
- RT5677_PDM2_DATA_CTRL3
- RT5677_PDM2_DATA_CTRL4
- RT5677_PDM2_EXE
- RT5677_PDM2_I2C_BUSY
- RT5677_PDM2_I2C_CMD
- RT5677_PDM2_I2C_EXE
- RT5677_PDM2_I2C_ID
- RT5677_PDM2_PW_DOWN
- RT5677_PDM_DATA_CTRL1
- RT5677_PDM_DATA_CTRL2
- RT5677_PDM_DIV_MASK
- RT5677_PDM_GAIN
- RT5677_PDM_OUT_CTRL
- RT5677_PDM_PATTERN
- RT5677_PLL1_CTRL1
- RT5677_PLL1_CTRL2
- RT5677_PLL1_INT
- RT5677_PLL1_PD_1
- RT5677_PLL1_PD_2
- RT5677_PLL1_PD_MASK
- RT5677_PLL1_PD_SFT
- RT5677_PLL1_SRC_BCLK1
- RT5677_PLL1_SRC_BCLK2
- RT5677_PLL1_SRC_BCLK3
- RT5677_PLL1_SRC_BCLK4
- RT5677_PLL1_SRC_MASK
- RT5677_PLL1_SRC_MCLK
- RT5677_PLL1_SRC_RCCLK
- RT5677_PLL1_SRC_SFT
- RT5677_PLL1_SRC_SLIM
- RT5677_PLL1_S_BCLK1
- RT5677_PLL1_S_BCLK2
- RT5677_PLL1_S_BCLK3
- RT5677_PLL1_S_BCLK4
- RT5677_PLL1_S_MCLK
- RT5677_PLL2_CTRL1
- RT5677_PLL2_CTRL2
- RT5677_PLL2_INT
- RT5677_PLL2_PR_SRC_MASK
- RT5677_PLL2_PR_SRC_MCLK1
- RT5677_PLL2_PR_SRC_MCLK2
- RT5677_PLL2_PR_SRC_SFT
- RT5677_PLL2_SRC_BCLK1
- RT5677_PLL2_SRC_BCLK2
- RT5677_PLL2_SRC_BCLK3
- RT5677_PLL2_SRC_BCLK4
- RT5677_PLL2_SRC_MASK
- RT5677_PLL2_SRC_MCLK
- RT5677_PLL2_SRC_RCCLK
- RT5677_PLL2_SRC_SFT
- RT5677_PLL2_SRC_SLIM
- RT5677_PLL_INP_MAX
- RT5677_PLL_INP_MIN
- RT5677_PLL_K_BP
- RT5677_PLL_K_BP_SFT
- RT5677_PLL_K_MASK
- RT5677_PLL_K_MAX
- RT5677_PLL_K_SFT
- RT5677_PLL_M_BP
- RT5677_PLL_M_BP_SFT
- RT5677_PLL_M_MASK
- RT5677_PLL_M_MAX
- RT5677_PLL_M_SFT
- RT5677_PLL_N_MASK
- RT5677_PLL_N_MAX
- RT5677_PLL_N_SFT
- RT5677_PRIV_DATA
- RT5677_PRIV_INDEX
- RT5677_PR_BASE
- RT5677_PR_DRC1_CTRL_1
- RT5677_PR_DRC1_CTRL_2
- RT5677_PR_DRC1_CTRL_3
- RT5677_PR_DRC1_CTRL_4
- RT5677_PR_DRC1_CTRL_5
- RT5677_PR_DRC1_CTRL_6
- RT5677_PR_DRC1_CTRL_7
- RT5677_PR_DRC2_CTRL_1
- RT5677_PR_DRC2_CTRL_2
- RT5677_PR_DRC2_CTRL_3
- RT5677_PR_DRC2_CTRL_4
- RT5677_PR_DRC2_CTRL_5
- RT5677_PR_DRC2_CTRL_6
- RT5677_PR_DRC2_CTRL_7
- RT5677_PR_RANGE_BASE
- RT5677_PR_SPACING
- RT5677_PWR_25M_CLK
- RT5677_PWR_25M_CLK_BIT
- RT5677_PWR_ADCFED1
- RT5677_PWR_ADCFED1_BIT
- RT5677_PWR_ADCFED2
- RT5677_PWR_ADCFED2_BIT
- RT5677_PWR_ADC_L
- RT5677_PWR_ADC_L_BIT
- RT5677_PWR_ADC_MF_L
- RT5677_PWR_ADC_MF_L_BIT
- RT5677_PWR_ADC_MF_R
- RT5677_PWR_ADC_MF_R_BIT
- RT5677_PWR_ADC_R
- RT5677_PWR_ADC_R_BIT
- RT5677_PWR_ADC_S1F
- RT5677_PWR_ADC_S1F_BIT
- RT5677_PWR_ADC_S2F
- RT5677_PWR_ADC_S2F_BIT
- RT5677_PWR_ADC_S3F
- RT5677_PWR_ADC_S3F_BIT
- RT5677_PWR_ADC_S4F
- RT5677_PWR_ADC_S4F_BIT
- RT5677_PWR_ANLG1
- RT5677_PWR_ANLG2
- RT5677_PWR_BG
- RT5677_PWR_BG_BIT
- RT5677_PWR_BST1
- RT5677_PWR_BST1_BIT
- RT5677_PWR_BST1_P
- RT5677_PWR_BST1_P_BIT
- RT5677_PWR_BST2
- RT5677_PWR_BST2_BIT
- RT5677_PWR_BST2_P
- RT5677_PWR_BST2_P_BIT
- RT5677_PWR_CLK_MB
- RT5677_PWR_CLK_MB1
- RT5677_PWR_CLK_MB1_BIT
- RT5677_PWR_CLK_MB_BIT
- RT5677_PWR_CORE
- RT5677_PWR_CORE_BIT
- RT5677_PWR_CORE_ISO
- RT5677_PWR_CORE_ISO_BIT
- RT5677_PWR_DAC1
- RT5677_PWR_DAC1_BIT
- RT5677_PWR_DAC2
- RT5677_PWR_DAC2_BIT
- RT5677_PWR_DAC3
- RT5677_PWR_DAC3_BIT
- RT5677_PWR_DAC_M2F_L
- RT5677_PWR_DAC_M2F_L_BIT
- RT5677_PWR_DAC_M2F_R
- RT5677_PWR_DAC_M2F_R_BIT
- RT5677_PWR_DAC_M3F_L
- RT5677_PWR_DAC_M3F_L_BIT
- RT5677_PWR_DAC_M3F_R
- RT5677_PWR_DAC_M3F_R_BIT
- RT5677_PWR_DAC_M4F_L
- RT5677_PWR_DAC_M4F_L_BIT
- RT5677_PWR_DAC_M4F_R
- RT5677_PWR_DAC_M4F_R_BIT
- RT5677_PWR_DAC_S1F
- RT5677_PWR_DAC_S1F_BIT
- RT5677_PWR_DIG1
- RT5677_PWR_DIG2
- RT5677_PWR_DSP
- RT5677_PWR_DSP1
- RT5677_PWR_DSP2
- RT5677_PWR_DSP_BIT
- RT5677_PWR_DSP_CPU
- RT5677_PWR_DSP_CPU_BIT
- RT5677_PWR_DSP_ISO
- RT5677_PWR_DSP_ISO_BIT
- RT5677_PWR_DSP_RDY
- RT5677_PWR_DSP_RDY_BIT
- RT5677_PWR_DSP_ST
- RT5677_PWR_FV1
- RT5677_PWR_FV1_BIT
- RT5677_PWR_FV2
- RT5677_PWR_FV2_BIT
- RT5677_PWR_I2C_MASTER
- RT5677_PWR_I2C_MASTER_BIT
- RT5677_PWR_I2S1
- RT5677_PWR_I2S1_BIT
- RT5677_PWR_I2S2
- RT5677_PWR_I2S2_BIT
- RT5677_PWR_I2S3
- RT5677_PWR_I2S3_BIT
- RT5677_PWR_I2S4
- RT5677_PWR_I2S4_BIT
- RT5677_PWR_IPTV
- RT5677_PWR_IPTV_BIT
- RT5677_PWR_LDO1
- RT5677_PWR_LDO1_BIT
- RT5677_PWR_LO1
- RT5677_PWR_LO1_BIT
- RT5677_PWR_LO2
- RT5677_PWR_LO2_BIT
- RT5677_PWR_LO3
- RT5677_PWR_LO3_BIT
- RT5677_PWR_MB
- RT5677_PWR_MB1
- RT5677_PWR_MB1_BIT
- RT5677_PWR_MB_BIT
- RT5677_PWR_MLT
- RT5677_PWR_MLT_BIT
- RT5677_PWR_MLT_ISO
- RT5677_PWR_MLT_ISO_BIT
- RT5677_PWR_MLT_RDY
- RT5677_PWR_MLT_RDY_BIT
- RT5677_PWR_PDM1
- RT5677_PWR_PDM1_BIT
- RT5677_PWR_PDM2
- RT5677_PWR_PDM2_BIT
- RT5677_PWR_PLL1
- RT5677_PWR_PLL1_BIT
- RT5677_PWR_PLL2
- RT5677_PWR_PLL2_BIT
- RT5677_PWR_PP_MB1
- RT5677_PWR_PP_MB1_BIT
- RT5677_PWR_SLB
- RT5677_PWR_SLB_BIT
- RT5677_PWR_SLIM
- RT5677_PWR_SLIM_BIT
- RT5677_PWR_SLIM_ISO
- RT5677_PWR_SLIM_ISO_BIT
- RT5677_PWR_SR0
- RT5677_PWR_SR0_BIT
- RT5677_PWR_SR0_ISO
- RT5677_PWR_SR0_ISO_BIT
- RT5677_PWR_SR0_RDY
- RT5677_PWR_SR0_RDY_BIT
- RT5677_PWR_SR1
- RT5677_PWR_SR1_BIT
- RT5677_PWR_SR1_ISO
- RT5677_PWR_SR1_ISO_BIT
- RT5677_PWR_SR1_RDY
- RT5677_PWR_SR1_RDY_BIT
- RT5677_PWR_SR2
- RT5677_PWR_SR2_BIT
- RT5677_PWR_SR2_ISO
- RT5677_PWR_SR2_ISO_BIT
- RT5677_PWR_SR2_RDY
- RT5677_PWR_SR2_RDY_BIT
- RT5677_PWR_SR3
- RT5677_PWR_SR3_BIT
- RT5677_PWR_SR3_ISO
- RT5677_PWR_SR3_ISO_BIT
- RT5677_PWR_SR3_RDY
- RT5677_PWR_SR3_RDY_BIT
- RT5677_PWR_SR4
- RT5677_PWR_SR4_BIT
- RT5677_PWR_SR4_ISO
- RT5677_PWR_SR4_ISO_BIT
- RT5677_PWR_SR4_RDY
- RT5677_PWR_SR4_RDY_BIT
- RT5677_PWR_SR5
- RT5677_PWR_SR5_BIT
- RT5677_PWR_SR5_ISO
- RT5677_PWR_SR5_ISO_BIT
- RT5677_PWR_SR5_RDY
- RT5677_PWR_SR5_RDY_BIT
- RT5677_PWR_SR6
- RT5677_PWR_SR6_BIT
- RT5677_PWR_SR6_ISO
- RT5677_PWR_SR6_ISO_BIT
- RT5677_PWR_SR6_RDY
- RT5677_PWR_SR6_RDY_BIT
- RT5677_PWR_SR7
- RT5677_PWR_SR7_BIT
- RT5677_PWR_SR7_ISO
- RT5677_PWR_SR7_ISO_BIT
- RT5677_PWR_SR7_RDY
- RT5677_PWR_SR7_RDY_BIT
- RT5677_PWR_VREF1
- RT5677_PWR_VREF1_BIT
- RT5677_PWR_VREF2
- RT5677_PWR_VREF2_BIT
- RT5677_RESET
- RT5677_R_MUTE
- RT5677_R_MUTE_SFT
- RT5677_R_VOL_MASK
- RT5677_R_VOL_SFT
- RT5677_SCLK_SRC_MASK
- RT5677_SCLK_SRC_MCLK
- RT5677_SCLK_SRC_PLL1
- RT5677_SCLK_SRC_RCCLK
- RT5677_SCLK_SRC_SFT
- RT5677_SCLK_SRC_SLIM
- RT5677_SCLK_S_MCLK
- RT5677_SCLK_S_PLL1
- RT5677_SCLK_S_RCCLK
- RT5677_SEL_DAC2_L_SRC_MASK
- RT5677_SEL_DAC2_L_SRC_SFT
- RT5677_SEL_DAC2_R_SRC_MASK
- RT5677_SEL_DAC2_R_SRC_SFT
- RT5677_SEL_DAC3_L_SRC_MASK
- RT5677_SEL_DAC3_L_SRC_SFT
- RT5677_SEL_DAC3_R_SRC_MASK
- RT5677_SEL_DAC3_R_SRC_SFT
- RT5677_SEL_DAC4_L_SRC_MASK
- RT5677_SEL_DAC4_L_SRC_SFT
- RT5677_SEL_DAC4_R_SRC_MASK
- RT5677_SEL_DAC4_R_SRC_SFT
- RT5677_SEL_GPIO_JD1_MASK
- RT5677_SEL_GPIO_JD1_SFT
- RT5677_SEL_GPIO_JD2_MASK
- RT5677_SEL_GPIO_JD2_SFT
- RT5677_SEL_GPIO_JD3_MASK
- RT5677_SEL_GPIO_JD3_SFT
- RT5677_SEL_MONO_ADC_L1_MASK
- RT5677_SEL_MONO_ADC_L1_SFT
- RT5677_SEL_MONO_ADC_L2_MASK
- RT5677_SEL_MONO_ADC_L2_SFT
- RT5677_SEL_MONO_ADC_R1_MASK
- RT5677_SEL_MONO_ADC_R1_SFT
- RT5677_SEL_MONO_ADC_R2_MASK
- RT5677_SEL_MONO_ADC_R2_SFT
- RT5677_SEL_MONO_DMIC_L_MASK
- RT5677_SEL_MONO_DMIC_L_SFT
- RT5677_SEL_MONO_DMIC_R_MASK
- RT5677_SEL_MONO_DMIC_R_SFT
- RT5677_SEL_PDM1_L_MASK
- RT5677_SEL_PDM1_L_SFT
- RT5677_SEL_PDM1_R_MASK
- RT5677_SEL_PDM1_R_SFT
- RT5677_SEL_PDM2_L_MASK
- RT5677_SEL_PDM2_L_SFT
- RT5677_SEL_PDM2_R_MASK
- RT5677_SEL_PDM2_R_SFT
- RT5677_SEL_SRC_IB01
- RT5677_SEL_SRC_IB01_SFT
- RT5677_SEL_SRC_IB23
- RT5677_SEL_SRC_IB23_SFT
- RT5677_SEL_SRC_IB45
- RT5677_SEL_SRC_IB45_SFT
- RT5677_SEL_SRC_OB01
- RT5677_SEL_SRC_OB01_SFT
- RT5677_SEL_SRC_OB23
- RT5677_SEL_SRC_OB23_SFT
- RT5677_SEL_STO1_ADC1_MASK
- RT5677_SEL_STO1_ADC1_SFT
- RT5677_SEL_STO1_ADC2_MASK
- RT5677_SEL_STO1_ADC2_SFT
- RT5677_SEL_STO1_DMIC_MASK
- RT5677_SEL_STO1_DMIC_SFT
- RT5677_SEL_STO2_ADC1_MASK
- RT5677_SEL_STO2_ADC1_SFT
- RT5677_SEL_STO2_ADC2_MASK
- RT5677_SEL_STO2_ADC2_SFT
- RT5677_SEL_STO2_DMIC_MASK
- RT5677_SEL_STO2_DMIC_SFT
- RT5677_SEL_STO2_LR_MIX_L
- RT5677_SEL_STO2_LR_MIX_LR
- RT5677_SEL_STO2_LR_MIX_MASK
- RT5677_SEL_STO2_LR_MIX_SFT
- RT5677_SEL_STO3_ADC1_MASK
- RT5677_SEL_STO3_ADC1_SFT
- RT5677_SEL_STO3_ADC2_MASK
- RT5677_SEL_STO3_ADC2_SFT
- RT5677_SEL_STO3_DMIC_MASK
- RT5677_SEL_STO3_DMIC_SFT
- RT5677_SEL_STO4_ADC1_MASK
- RT5677_SEL_STO4_ADC1_SFT
- RT5677_SEL_STO4_ADC2_MASK
- RT5677_SEL_STO4_ADC2_SFT
- RT5677_SEL_STO4_DMIC_MASK
- RT5677_SEL_STO4_DMIC_SFT
- RT5677_SIDETONE_CTRL
- RT5677_SLB_ADC1_MASK
- RT5677_SLB_ADC1_SFT
- RT5677_SLB_ADC2_MASK
- RT5677_SLB_ADC2_SFT
- RT5677_SLB_ADC3_MASK
- RT5677_SLB_ADC3_SFT
- RT5677_SLB_ADC4_MASK
- RT5677_SLB_ADC4_SFT
- RT5677_SLIMBUS_CTRL
- RT5677_SLIMBUS_PARAM
- RT5677_SLIMBUS_RX
- RT5677_SOFT_DEPOP_DAC_CLK_CTRL
- RT5677_SOFT_VOL_ZERO_CROSS1
- RT5677_SPI_BURST_LEN
- RT5677_SPI_FREQ
- RT5677_SPI_HEADER
- RT5677_SPI_READ_16
- RT5677_SPI_READ_32
- RT5677_SPI_READ_BURST
- RT5677_SPI_WRITE_16
- RT5677_SPI_WRITE_32
- RT5677_SPI_WRITE_BURST
- RT5677_STA_GPIO_JD1
- RT5677_STA_GPIO_JD1_SFT
- RT5677_STA_GPIO_JD2
- RT5677_STA_GPIO_JD2_SFT
- RT5677_STA_GPIO_JD3
- RT5677_STA_GPIO_JD3_SFT
- RT5677_STA_MICBIAS1_OVCD
- RT5677_STA_MICBIAS1_OVCD_SFT
- RT5677_STEREO_RATES
- RT5677_STO1_2_ADC_BST
- RT5677_STO1_ADC_COMP_MASK
- RT5677_STO1_ADC_COMP_SFT
- RT5677_STO1_ADC_DIG_VOL
- RT5677_STO1_ADC_HI_FILTER1
- RT5677_STO1_ADC_HI_FILTER2
- RT5677_STO1_ADC_L_BST_MASK
- RT5677_STO1_ADC_L_BST_SFT
- RT5677_STO1_ADC_L_VOL_MASK
- RT5677_STO1_ADC_L_VOL_SFT
- RT5677_STO1_ADC_MIXER
- RT5677_STO1_ADC_R_BST_MASK
- RT5677_STO1_ADC_R_BST_SFT
- RT5677_STO1_ADC_R_VOL_MASK
- RT5677_STO1_ADC_R_VOL_SFT
- RT5677_STO1_DAC_MIXER
- RT5677_STO2_ADC_COMP_MASK
- RT5677_STO2_ADC_COMP_SFT
- RT5677_STO2_ADC_DIG_VOL
- RT5677_STO2_ADC_HI_FILTER1
- RT5677_STO2_ADC_HI_FILTER2
- RT5677_STO2_ADC_L_BST_MASK
- RT5677_STO2_ADC_L_BST_SFT
- RT5677_STO2_ADC_L_VOL_MASK
- RT5677_STO2_ADC_L_VOL_SFT
- RT5677_STO2_ADC_MIXER
- RT5677_STO2_ADC_R_BST_MASK
- RT5677_STO2_ADC_R_BST_SFT
- RT5677_STO2_ADC_R_VOL_MASK
- RT5677_STO2_ADC_R_VOL_SFT
- RT5677_STO3_4_ADC_BST
- RT5677_STO3_ADC_COMP_MASK
- RT5677_STO3_ADC_COMP_SFT
- RT5677_STO3_ADC_DIG_VOL
- RT5677_STO3_ADC_HI_FILTER1
- RT5677_STO3_ADC_HI_FILTER2
- RT5677_STO3_ADC_L_BST_MASK
- RT5677_STO3_ADC_L_BST_SFT
- RT5677_STO3_ADC_L_VOL_MASK
- RT5677_STO3_ADC_L_VOL_SFT
- RT5677_STO3_ADC_MIXER
- RT5677_STO3_ADC_R_BST_MASK
- RT5677_STO3_ADC_R_BST_SFT
- RT5677_STO3_ADC_R_VOL_MASK
- RT5677_STO3_ADC_R_VOL_SFT
- RT5677_STO4_ADC_COMP_MASK
- RT5677_STO4_ADC_COMP_SFT
- RT5677_STO4_ADC_DIG_VOL
- RT5677_STO4_ADC_HI_FILTER1
- RT5677_STO4_ADC_HI_FILTER2
- RT5677_STO4_ADC_L_BST_MASK
- RT5677_STO4_ADC_L_BST_SFT
- RT5677_STO4_ADC_L_VOL_MASK
- RT5677_STO4_ADC_L_VOL_SFT
- RT5677_STO4_ADC_MIXER
- RT5677_STO4_ADC_R_BST_MASK
- RT5677_STO4_ADC_R_BST_SFT
- RT5677_STO4_ADC_R_VOL_MASK
- RT5677_STO4_ADC_R_VOL_SFT
- RT5677_STO_L_DD1_L_VOL_MASK
- RT5677_STO_L_DD1_L_VOL_SFT
- RT5677_STO_L_DD2_L_VOL_MASK
- RT5677_STO_L_DD2_L_VOL_SFT
- RT5677_STO_R_DD1_R_VOL_MASK
- RT5677_STO_R_DD1_R_VOL_SFT
- RT5677_STO_R_DD2_R_VOL_MASK
- RT5677_STO_R_DD2_R_VOL_SFT
- RT5677_ST_EN
- RT5677_ST_EN_SFT
- RT5677_ST_GAIN
- RT5677_ST_GAIN_SFT
- RT5677_ST_HPF_PATH
- RT5677_ST_HPF_PATH_SFT
- RT5677_ST_HPF_SEL_MASK
- RT5677_ST_HPF_SEL_SFT
- RT5677_ST_SEL_MASK
- RT5677_ST_SEL_SFT
- RT5677_ST_VOL_MASK
- RT5677_ST_VOL_SFT
- RT5677_TDM1_CTRL1
- RT5677_TDM1_CTRL2
- RT5677_TDM1_CTRL3
- RT5677_TDM1_CTRL4
- RT5677_TDM1_CTRL5
- RT5677_TDM2_CTRL1
- RT5677_TDM2_CTRL2
- RT5677_TDM2_CTRL3
- RT5677_TDM2_CTRL4
- RT5677_TDM2_CTRL5
- RT5677_TEST_CTRL1
- RT5677_TEST_CTRL2
- RT5677_TEST_CTRL3
- RT5677_VAD_ADPCM_BYPASS
- RT5677_VAD_ADPCM_BYPASS_BIT
- RT5677_VAD_BUF_OW
- RT5677_VAD_BUF_OW_BIT
- RT5677_VAD_BUF_POP
- RT5677_VAD_BUF_POP_BIT
- RT5677_VAD_BUF_PUSH
- RT5677_VAD_BUF_PUSH_BIT
- RT5677_VAD_CLR_FLAG
- RT5677_VAD_CLR_FLAG_BIT
- RT5677_VAD_CTRL1
- RT5677_VAD_CTRL2
- RT5677_VAD_CTRL3
- RT5677_VAD_CTRL4
- RT5677_VAD_CTRL5
- RT5677_VAD_DET_ENABLE
- RT5677_VAD_DET_ENABLE_BIT
- RT5677_VAD_FG2ENC
- RT5677_VAD_FG2ENC_BIT
- RT5677_VAD_FUNC_ENABLE
- RT5677_VAD_FUNC_ENABLE_BIT
- RT5677_VAD_FUNC_RESET
- RT5677_VAD_FUNC_RESET_BIT
- RT5677_VAD_LV_DIFF_MASK
- RT5677_VAD_LV_DIFF_SFT
- RT5677_VAD_MIN_DUR_MASK
- RT5677_VAD_MIN_DUR_SFT
- RT5677_VAD_OUT_SRC_MASK
- RT5677_VAD_OUT_SRC_RATE_MASK
- RT5677_VAD_OUT_SRC_RATE_SFT
- RT5677_VAD_OUT_SRC_SFT
- RT5677_VAD_SRAM_TEST1
- RT5677_VAD_SRAM_TEST2
- RT5677_VAD_SRAM_TEST3
- RT5677_VAD_SRAM_TEST4
- RT5677_VAD_SRC_MASK
- RT5677_VAD_SRC_SFT
- RT5677_VENDOR_ID
- RT5677_VENDOR_ID1
- RT5677_VENDOR_ID2
- RT5677_VOL_L_MUTE
- RT5677_VOL_L_SFT
- RT5677_VOL_R_MUTE
- RT5677_VOL_R_SFT
- RT5677_VREF_LOUT_CTRL
- RT5682_4BTN_IL_CMD_1
- RT5682_4BTN_IL_CMD_2
- RT5682_4BTN_IL_CMD_3
- RT5682_4BTN_IL_CMD_4
- RT5682_4BTN_IL_CMD_5
- RT5682_4BTN_IL_CMD_6
- RT5682_4BTN_IL_CMD_7
- RT5682_4BTN_IL_DIS
- RT5682_4BTN_IL_EN
- RT5682_4BTN_IL_MASK
- RT5682_4BTN_IL_NOR
- RT5682_4BTN_IL_RST
- RT5682_4BTN_IL_RST_MASK
- RT5682_AD2DA_LB_MASK
- RT5682_AD2DA_LB_SFT
- RT5682_ADC_L_EQ_LPF1_A1
- RT5682_ADC_L_VOL_MASK
- RT5682_ADC_L_VOL_SFT
- RT5682_ADC_OSR_D_1
- RT5682_ADC_OSR_D_12
- RT5682_ADC_OSR_D_16
- RT5682_ADC_OSR_D_2
- RT5682_ADC_OSR_D_24
- RT5682_ADC_OSR_D_32
- RT5682_ADC_OSR_D_4
- RT5682_ADC_OSR_D_48
- RT5682_ADC_OSR_D_6
- RT5682_ADC_OSR_D_8
- RT5682_ADC_OSR_MASK
- RT5682_ADC_OSR_SFT
- RT5682_ADC_R_VOL_MASK
- RT5682_ADC_R_VOL_SFT
- RT5682_ADC_STO1_ASRC_MASK
- RT5682_ADC_STO1_ASRC_SFT
- RT5682_ADC_STO1_HP_CTRL_1
- RT5682_ADC_STO1_HP_CTRL_2
- RT5682_ADDA_CLK_1
- RT5682_ADDA_CLK_2
- RT5682_AD_ASRC_MASK
- RT5682_AD_ASRC_SEL_MASK
- RT5682_AD_ASRC_SEL_SFT
- RT5682_AD_ASRC_SFT
- RT5682_AD_DA_MIXER
- RT5682_AD_STEREO1_FILTER
- RT5682_AIF1
- RT5682_AIF2
- RT5682_AIFS
- RT5682_AJD1_CTRL
- RT5682_ALC_BACK_GAIN
- RT5682_ASRCIN_FTK_M1_MASK
- RT5682_ASRCIN_FTK_M1_SFT
- RT5682_ASRCIN_FTK_M2_MASK
- RT5682_ASRCIN_FTK_M2_SFT
- RT5682_ASRCIN_FTK_N1_MASK
- RT5682_ASRCIN_FTK_N1_SFT
- RT5682_ASRCIN_FTK_N2_MASK
- RT5682_ASRCIN_FTK_N2_SFT
- RT5682_A_DAC1_MUX
- RT5682_A_DACL1_SFT
- RT5682_A_DACR1_SFT
- RT5682_BIAS_CUR_CTRL_10
- RT5682_BIAS_CUR_CTRL_2
- RT5682_BIAS_CUR_CTRL_3
- RT5682_BIAS_CUR_CTRL_4
- RT5682_BIAS_CUR_CTRL_5
- RT5682_BIAS_CUR_CTRL_6
- RT5682_BIAS_CUR_CTRL_7
- RT5682_BIAS_CUR_CTRL_8
- RT5682_BIAS_CUR_CTRL_9
- RT5682_BPS_DIS
- RT5682_BPS_EN
- RT5682_BPS_MASK
- RT5682_BPS_SFT
- RT5682_BST_CBJ_MASK
- RT5682_BST_CBJ_SFT
- RT5682_CALIB_ADC_CTRL
- RT5682_CAL_REC
- RT5682_CAPLESS_EN
- RT5682_CAPLESS_EN_SFT
- RT5682_CBJ_BST_CTRL
- RT5682_CBJ_CTRL_1
- RT5682_CBJ_CTRL_2
- RT5682_CBJ_CTRL_3
- RT5682_CBJ_CTRL_4
- RT5682_CBJ_CTRL_5
- RT5682_CBJ_CTRL_6
- RT5682_CBJ_CTRL_7
- RT5682_CBJ_IN_BUF_EN
- RT5682_CBJ_JD_TEST_MASK
- RT5682_CBJ_JD_TEST_MODE
- RT5682_CBJ_JD_TEST_NORM
- RT5682_CHARGE_PUMP_1
- RT5682_CHOP_ADC
- RT5682_CHOP_DAC
- RT5682_CKGEN_ADC1_MASK
- RT5682_CKGEN_ADC1_SFT
- RT5682_CKGEN_DAC1_MASK
- RT5682_CKGEN_DAC1_SFT
- RT5682_CKXEN_ADC1_MASK
- RT5682_CKXEN_ADC1_SFT
- RT5682_CKXEN_DAC1_MASK
- RT5682_CKXEN_DAC1_SFT
- RT5682_CLK_DET
- RT5682_CLK_SEL_I2S1_ASRC
- RT5682_CLK_SEL_I2S2_ASRC
- RT5682_CLK_SEL_SYS
- RT5682_CLK_SRC_MCLK
- RT5682_CLK_SRC_PLL1
- RT5682_CLK_SRC_PLL2
- RT5682_CLK_SRC_RCCLK
- RT5682_CLK_SRC_SDW
- RT5682_CP_CLK_HP_100KHZ
- RT5682_CP_CLK_HP_200KHZ
- RT5682_CP_CLK_HP_300KHZ
- RT5682_CP_CLK_HP_600KHZ
- RT5682_CP_CLK_HP_MASK
- RT5682_CTRL_MB1_FSM
- RT5682_CTRL_MB1_REG
- RT5682_CTRL_MB2_FSM
- RT5682_CTRL_MB2_REG
- RT5682_DAC1_DIG_VOL
- RT5682_DAC1_L_SEL_MASK
- RT5682_DAC1_L_SEL_SFT
- RT5682_DAC1_R_SEL_MASK
- RT5682_DAC1_R_SEL_SFT
- RT5682_DAC_ADC_DIG_VOL1
- RT5682_DAC_L1_SRC_MASK
- RT5682_DAC_L1_VOL_MASK
- RT5682_DAC_L1_VOL_SFT
- RT5682_DAC_OSR_D_1
- RT5682_DAC_OSR_D_12
- RT5682_DAC_OSR_D_16
- RT5682_DAC_OSR_D_2
- RT5682_DAC_OSR_D_24
- RT5682_DAC_OSR_D_32
- RT5682_DAC_OSR_D_4
- RT5682_DAC_OSR_D_48
- RT5682_DAC_OSR_D_6
- RT5682_DAC_OSR_D_8
- RT5682_DAC_OSR_MASK
- RT5682_DAC_OSR_SFT
- RT5682_DAC_R1_SRC_MASK
- RT5682_DAC_R1_VOL_MASK
- RT5682_DAC_R1_VOL_SFT
- RT5682_DAC_STO1_ASRC_MASK
- RT5682_DAC_STO1_ASRC_SFT
- RT5682_DATA_SEL_CTRL_1
- RT5682_DA_ASRC_MASK
- RT5682_DA_ASRC_SEL_MASK
- RT5682_DA_ASRC_SEL_SFT
- RT5682_DA_ASRC_SFT
- RT5682_DA_STEREO1_FILTER
- RT5682_DEB_80_MS
- RT5682_DEB_STO_DAC_MASK
- RT5682_DELAY_BUF_CTRL
- RT5682_DEPOP_1
- RT5682_DEPOP_2
- RT5682_DET_TYPE
- RT5682_DET_TYPE_SFT
- RT5682_DEVICE_ID
- RT5682_DIG_GATE_CTRL
- RT5682_DIG_GATE_CTRL_SFT
- RT5682_DIG_INF2_DATA
- RT5682_DIG_IN_CTRL_1
- RT5682_DMIC1_CLK_GPIO1
- RT5682_DMIC1_CLK_GPIO3
- RT5682_DMIC1_DATA_GPIO2
- RT5682_DMIC1_DATA_GPIO5
- RT5682_DMIC1_NULL
- RT5682_DMIC_1_DIS
- RT5682_DMIC_1_DP_GPIO2
- RT5682_DMIC_1_DP_GPIO5
- RT5682_DMIC_1_DP_MASK
- RT5682_DMIC_1_DP_SFT
- RT5682_DMIC_1_EN
- RT5682_DMIC_1_EN_MASK
- RT5682_DMIC_1_EN_SFT
- RT5682_DMIC_ASRC_MASK
- RT5682_DMIC_ASRC_SFT
- RT5682_DMIC_CLK_MASK
- RT5682_DMIC_CLK_SFT
- RT5682_DMIC_CTRL_1
- RT5682_DRC1_CTRL_0
- RT5682_DRC1_CTRL_1
- RT5682_DRC1_CTRL_2
- RT5682_DRC1_CTRL_3
- RT5682_DRC1_CTRL_4
- RT5682_DRC1_CTRL_5
- RT5682_DRC1_CTRL_6
- RT5682_DRC1_HARD_LMT_CTRL_1
- RT5682_DRC1_HARD_LMT_CTRL_2
- RT5682_DRC1_PRIV_1
- RT5682_DRC1_PRIV_2
- RT5682_DRC1_PRIV_3
- RT5682_DRC1_PRIV_4
- RT5682_DRC1_PRIV_5
- RT5682_DRC1_PRIV_6
- RT5682_DRC1_PRIV_7
- RT5682_DRC1_PRIV_8
- RT5682_DUMMY_1
- RT5682_DUMMY_2
- RT5682_DUMMY_3
- RT5682_EFUSE_CTRL_1
- RT5682_EFUSE_CTRL_10
- RT5682_EFUSE_CTRL_11
- RT5682_EFUSE_CTRL_2
- RT5682_EFUSE_CTRL_3
- RT5682_EFUSE_CTRL_4
- RT5682_EFUSE_CTRL_5
- RT5682_EFUSE_CTRL_6
- RT5682_EFUSE_CTRL_7
- RT5682_EFUSE_CTRL_8
- RT5682_EFUSE_CTRL_9
- RT5682_EMB_JD_EN
- RT5682_EMB_JD_EN_SFT
- RT5682_EMB_JD_RST
- RT5682_EQ_AUTO_RCV_CTRL1
- RT5682_EQ_AUTO_RCV_CTRL10
- RT5682_EQ_AUTO_RCV_CTRL11
- RT5682_EQ_AUTO_RCV_CTRL12
- RT5682_EQ_AUTO_RCV_CTRL13
- RT5682_EQ_AUTO_RCV_CTRL2
- RT5682_EQ_AUTO_RCV_CTRL3
- RT5682_EQ_AUTO_RCV_CTRL4
- RT5682_EQ_AUTO_RCV_CTRL5
- RT5682_EQ_AUTO_RCV_CTRL6
- RT5682_EQ_AUTO_RCV_CTRL7
- RT5682_EQ_AUTO_RCV_CTRL8
- RT5682_EQ_AUTO_RCV_CTRL9
- RT5682_EQ_CTRL_1
- RT5682_EQ_CTRL_2
- RT5682_EXT_JD_DIG
- RT5682_EXT_JD_SRC
- RT5682_EXT_JD_SRC_GPIO_JD1
- RT5682_EXT_JD_SRC_GPIO_JD2
- RT5682_EXT_JD_SRC_JDH
- RT5682_EXT_JD_SRC_JDL
- RT5682_EXT_JD_SRC_MANUAL
- RT5682_EXT_JD_SRC_SFT
- RT5682_FAST_OFF_DIS
- RT5682_FAST_OFF_EN
- RT5682_FAST_OFF_MASK
- RT5682_FAST_UPDN_DIS
- RT5682_FAST_UPDN_EN
- RT5682_FAST_UPDN_MASK
- RT5682_FAST_UPDN_SFT
- RT5682_FILTER_CLK_DIV_MASK
- RT5682_FILTER_CLK_DIV_SFT
- RT5682_FILTER_CLK_SEL_MASK
- RT5682_FILTER_CLK_SEL_SFT
- RT5682_FORMATS
- RT5682_GLB_CLK
- RT5682_GP1_OUT_H
- RT5682_GP1_OUT_L
- RT5682_GP1_OUT_MASK
- RT5682_GP1_PF_IN
- RT5682_GP1_PF_MASK
- RT5682_GP1_PF_OUT
- RT5682_GP1_PIN_DMIC_CLK
- RT5682_GP1_PIN_GPIO1
- RT5682_GP1_PIN_IRQ
- RT5682_GP1_PIN_MASK
- RT5682_GP1_PIN_SFT
- RT5682_GP1_STA
- RT5682_GP2_OUT_H
- RT5682_GP2_OUT_L
- RT5682_GP2_OUT_MASK
- RT5682_GP2_PF_IN
- RT5682_GP2_PF_MASK
- RT5682_GP2_PF_OUT
- RT5682_GP2_PIN_DMIC_SDA
- RT5682_GP2_PIN_GPIO2
- RT5682_GP2_PIN_LRCK2
- RT5682_GP2_PIN_MASK
- RT5682_GP2_PIN_SFT
- RT5682_GP2_STA
- RT5682_GP3_OUT_H
- RT5682_GP3_OUT_L
- RT5682_GP3_OUT_MASK
- RT5682_GP3_PF_IN
- RT5682_GP3_PF_MASK
- RT5682_GP3_PF_OUT
- RT5682_GP3_PIN_BCLK2
- RT5682_GP3_PIN_DMIC_CLK
- RT5682_GP3_PIN_GPIO3
- RT5682_GP3_PIN_MASK
- RT5682_GP3_PIN_SFT
- RT5682_GP3_STA
- RT5682_GP4_OUT_H
- RT5682_GP4_OUT_L
- RT5682_GP4_OUT_MASK
- RT5682_GP4_PF_IN
- RT5682_GP4_PF_MASK
- RT5682_GP4_PF_OUT
- RT5682_GP4_PIN_ADCDAT1
- RT5682_GP4_PIN_ADCDAT2
- RT5682_GP4_PIN_DMIC_CLK
- RT5682_GP4_PIN_GPIO4
- RT5682_GP4_PIN_MASK
- RT5682_GP4_PIN_SFT
- RT5682_GP4_STA
- RT5682_GP5_OUT_H
- RT5682_GP5_OUT_L
- RT5682_GP5_OUT_MASK
- RT5682_GP5_PF_IN
- RT5682_GP5_PF_MASK
- RT5682_GP5_PF_OUT
- RT5682_GP5_PIN_DACDAT1
- RT5682_GP5_PIN_DMIC_SDA
- RT5682_GP5_PIN_GPIO5
- RT5682_GP5_PIN_MASK
- RT5682_GP5_PIN_SFT
- RT5682_GP5_STA
- RT5682_GP6_OUT_H
- RT5682_GP6_OUT_L
- RT5682_GP6_OUT_MASK
- RT5682_GP6_PF_IN
- RT5682_GP6_PF_MASK
- RT5682_GP6_PF_OUT
- RT5682_GP6_PIN_GPIO6
- RT5682_GP6_PIN_LRCK1
- RT5682_GP6_PIN_MASK
- RT5682_GP6_PIN_SFT
- RT5682_GP6_STA
- RT5682_GPIO_CTRL_1
- RT5682_GPIO_CTRL_2
- RT5682_GPIO_CTRL_3
- RT5682_G_CBJ_RM1_L
- RT5682_G_CBJ_RM1_L_SFT
- RT5682_G_DAC_L1_STO_L_MASK
- RT5682_G_DAC_L1_STO_L_SFT
- RT5682_G_DAC_L1_STO_R_MASK
- RT5682_G_DAC_L1_STO_R_SFT
- RT5682_G_DAC_R1_STO_L_MASK
- RT5682_G_DAC_R1_STO_L_SFT
- RT5682_G_DAC_R1_STO_R_MASK
- RT5682_G_DAC_R1_STO_R_SFT
- RT5682_G_HP
- RT5682_G_HP_SFT
- RT5682_G_STO_DA_DMIX
- RT5682_G_STO_DA_SFT
- RT5682_HPA_CP_BIAS_2UA
- RT5682_HPA_CP_BIAS_3UA
- RT5682_HPA_CP_BIAS_4UA
- RT5682_HPA_CP_BIAS_6UA
- RT5682_HPA_CP_BIAS_CTRL_MASK
- RT5682_HPL_GAIN
- RT5682_HPR_GAIN
- RT5682_HP_AMP_DET_CTRL_1
- RT5682_HP_AMP_DET_CTRL_2
- RT5682_HP_CALIB_CTRL_1
- RT5682_HP_CALIB_CTRL_10
- RT5682_HP_CALIB_CTRL_11
- RT5682_HP_CALIB_CTRL_2
- RT5682_HP_CALIB_CTRL_3
- RT5682_HP_CALIB_CTRL_4
- RT5682_HP_CALIB_CTRL_5
- RT5682_HP_CALIB_CTRL_6
- RT5682_HP_CALIB_CTRL_7
- RT5682_HP_CALIB_CTRL_9
- RT5682_HP_CALIB_STA_1
- RT5682_HP_CALIB_STA_10
- RT5682_HP_CALIB_STA_11
- RT5682_HP_CALIB_STA_2
- RT5682_HP_CALIB_STA_3
- RT5682_HP_CALIB_STA_4
- RT5682_HP_CALIB_STA_5
- RT5682_HP_CALIB_STA_6
- RT5682_HP_CALIB_STA_7
- RT5682_HP_CALIB_STA_8
- RT5682_HP_CALIB_STA_9
- RT5682_HP_CHARGE_PUMP_1
- RT5682_HP_CHARGE_PUMP_2
- RT5682_HP_CTRL_1
- RT5682_HP_CTRL_2
- RT5682_HP_DRIVER_1X
- RT5682_HP_DRIVER_3X
- RT5682_HP_DRIVER_5X
- RT5682_HP_DRIVER_MASK
- RT5682_HP_IMP_GAIN_1
- RT5682_HP_IMP_GAIN_2
- RT5682_HP_IMP_SENS_CTRL_01
- RT5682_HP_IMP_SENS_CTRL_02
- RT5682_HP_IMP_SENS_CTRL_03
- RT5682_HP_IMP_SENS_CTRL_04
- RT5682_HP_IMP_SENS_CTRL_05
- RT5682_HP_IMP_SENS_CTRL_06
- RT5682_HP_IMP_SENS_CTRL_07
- RT5682_HP_IMP_SENS_CTRL_08
- RT5682_HP_IMP_SENS_CTRL_09
- RT5682_HP_IMP_SENS_CTRL_10
- RT5682_HP_IMP_SENS_CTRL_11
- RT5682_HP_IMP_SENS_CTRL_12
- RT5682_HP_IMP_SENS_CTRL_13
- RT5682_HP_IMP_SENS_CTRL_14
- RT5682_HP_IMP_SENS_CTRL_15
- RT5682_HP_IMP_SENS_CTRL_16
- RT5682_HP_IMP_SENS_CTRL_17
- RT5682_HP_IMP_SENS_CTRL_18
- RT5682_HP_IMP_SENS_CTRL_19
- RT5682_HP_IMP_SENS_CTRL_20
- RT5682_HP_IMP_SENS_CTRL_21
- RT5682_HP_IMP_SENS_CTRL_22
- RT5682_HP_IMP_SENS_CTRL_23
- RT5682_HP_IMP_SENS_CTRL_24
- RT5682_HP_IMP_SENS_CTRL_25
- RT5682_HP_IMP_SENS_CTRL_26
- RT5682_HP_IMP_SENS_CTRL_27
- RT5682_HP_IMP_SENS_CTRL_28
- RT5682_HP_IMP_SENS_CTRL_29
- RT5682_HP_IMP_SENS_CTRL_30
- RT5682_HP_IMP_SENS_CTRL_31
- RT5682_HP_IMP_SENS_CTRL_32
- RT5682_HP_IMP_SENS_CTRL_33
- RT5682_HP_IMP_SENS_CTRL_34
- RT5682_HP_IMP_SENS_CTRL_35
- RT5682_HP_IMP_SENS_CTRL_36
- RT5682_HP_IMP_SENS_CTRL_37
- RT5682_HP_IMP_SENS_CTRL_38
- RT5682_HP_IMP_SENS_CTRL_39
- RT5682_HP_IMP_SENS_CTRL_40
- RT5682_HP_IMP_SENS_CTRL_41
- RT5682_HP_IMP_SENS_CTRL_42
- RT5682_HP_IMP_SENS_CTRL_43
- RT5682_HP_LOGIC_CTRL_1
- RT5682_HP_LOGIC_CTRL_2
- RT5682_HP_LOGIC_CTRL_3
- RT5682_I2C_CTRL
- RT5682_I2C_MODE
- RT5682_I2S1_DL_16
- RT5682_I2S1_DL_20
- RT5682_I2S1_DL_24
- RT5682_I2S1_DL_32
- RT5682_I2S1_DL_8
- RT5682_I2S1_DL_MASK
- RT5682_I2S1_DL_SFT
- RT5682_I2S1_F_DIV_CTRL_1
- RT5682_I2S1_F_DIV_CTRL_2
- RT5682_I2S1_MONO_DIS
- RT5682_I2S1_MONO_EN
- RT5682_I2S1_MONO_MASK
- RT5682_I2S1_RX_CHL_16
- RT5682_I2S1_RX_CHL_20
- RT5682_I2S1_RX_CHL_24
- RT5682_I2S1_RX_CHL_32
- RT5682_I2S1_RX_CHL_8
- RT5682_I2S1_RX_CHL_MASK
- RT5682_I2S1_RX_CHL_SFT
- RT5682_I2S1_SDP
- RT5682_I2S1_TX_CHL_16
- RT5682_I2S1_TX_CHL_20
- RT5682_I2S1_TX_CHL_24
- RT5682_I2S1_TX_CHL_32
- RT5682_I2S1_TX_CHL_8
- RT5682_I2S1_TX_CHL_MASK
- RT5682_I2S1_TX_CHL_SFT
- RT5682_I2S2_BCLK_MS2_32
- RT5682_I2S2_BCLK_MS2_64
- RT5682_I2S2_BCLK_MS2_MASK
- RT5682_I2S2_BCLK_MS2_SFT
- RT5682_I2S2_CLK_SEL_MASK
- RT5682_I2S2_CLK_SEL_SFT
- RT5682_I2S2_DL_16
- RT5682_I2S2_DL_20
- RT5682_I2S2_DL_24
- RT5682_I2S2_DL_8
- RT5682_I2S2_DL_MASK
- RT5682_I2S2_DL_SFT
- RT5682_I2S2_F_DIV_CTRL_1
- RT5682_I2S2_F_DIV_CTRL_2
- RT5682_I2S2_MONO_DIS
- RT5682_I2S2_MONO_EN
- RT5682_I2S2_MONO_MASK
- RT5682_I2S2_MS_M
- RT5682_I2S2_MS_MASK
- RT5682_I2S2_MS_S
- RT5682_I2S2_MS_SFT
- RT5682_I2S2_M_PD_MASK
- RT5682_I2S2_M_PD_SFT
- RT5682_I2S2_OUT_M
- RT5682_I2S2_OUT_MASK
- RT5682_I2S2_OUT_SFT
- RT5682_I2S2_OUT_UM
- RT5682_I2S2_PIN_CFG_MASK
- RT5682_I2S2_PIN_CFG_SFT
- RT5682_I2S2_SDP
- RT5682_I2S2_SRC_MASK
- RT5682_I2S2_SRC_SFT
- RT5682_I2S_BP_INV
- RT5682_I2S_BP_MASK
- RT5682_I2S_BP_NOR
- RT5682_I2S_BP_SFT
- RT5682_I2S_CLK_SRC_MASK
- RT5682_I2S_CLK_SRC_MCLK
- RT5682_I2S_CLK_SRC_PLL1
- RT5682_I2S_CLK_SRC_PLL2
- RT5682_I2S_CLK_SRC_RCCLK
- RT5682_I2S_CLK_SRC_SDW
- RT5682_I2S_CLK_SRC_SFT
- RT5682_I2S_DF_I2S
- RT5682_I2S_DF_LEFT
- RT5682_I2S_DF_MASK
- RT5682_I2S_DF_PCM_A
- RT5682_I2S_DF_PCM_A_N
- RT5682_I2S_DF_PCM_B
- RT5682_I2S_DF_PCM_B_N
- RT5682_I2S_DF_SFT
- RT5682_I2S_M_CLK_CTRL_1
- RT5682_I2S_M_DIV_MASK
- RT5682_I2S_M_DIV_SFT
- RT5682_I2S_M_D_1
- RT5682_I2S_M_D_12
- RT5682_I2S_M_D_16
- RT5682_I2S_M_D_2
- RT5682_I2S_M_D_24
- RT5682_I2S_M_D_3
- RT5682_I2S_M_D_32
- RT5682_I2S_M_D_4
- RT5682_I2S_M_D_48
- RT5682_I2S_M_D_6
- RT5682_I2S_M_D_8
- RT5682_I2S_PD_1
- RT5682_I2S_PD_12
- RT5682_I2S_PD_16
- RT5682_I2S_PD_2
- RT5682_I2S_PD_24
- RT5682_I2S_PD_3
- RT5682_I2S_PD_32
- RT5682_I2S_PD_4
- RT5682_I2S_PD_48
- RT5682_I2S_PD_6
- RT5682_I2S_PD_8
- RT5682_IB_HP_125IL
- RT5682_IB_HP_1IL
- RT5682_IB_HP_25IL
- RT5682_IB_HP_5IL
- RT5682_IB_HP_MASK
- RT5682_IB_HP_SFT
- RT5682_IF1_ADC1_SEL_SFT
- RT5682_IF1_ADC2_SEL_SFT
- RT5682_IF1_ADC3_SEL_SFT
- RT5682_IF1_ADC4_SEL_SFT
- RT5682_IF2_ADC_SEL_MASK
- RT5682_IF2_ADC_SEL_SFT
- RT5682_IL_CMD_1
- RT5682_IL_CMD_2
- RT5682_IL_CMD_3
- RT5682_IL_CMD_4
- RT5682_IL_CMD_5
- RT5682_IL_CMD_6
- RT5682_IL_IRQ_DIS
- RT5682_IL_IRQ_EN
- RT5682_IL_IRQ_MASK
- RT5682_INT_ST_1
- RT5682_IRQ_CTRL_1
- RT5682_IRQ_CTRL_2
- RT5682_IRQ_CTRL_3
- RT5682_IRQ_CTRL_4
- RT5682_JACK_TYPE_MASK
- RT5682_JD1
- RT5682_JD1_DIS
- RT5682_JD1_EN
- RT5682_JD1_EN_MASK
- RT5682_JD1_EN_SFT
- RT5682_JD1_POL_INV
- RT5682_JD1_POL_MASK
- RT5682_JD1_POL_NOR
- RT5682_JD1_PULSE_DIS
- RT5682_JD1_PULSE_EN
- RT5682_JD1_PULSE_EN_MASK
- RT5682_JD1_PULSE_EN_SFT
- RT5682_JD1_THD
- RT5682_JD2_THD
- RT5682_JDH_NO_PLUG
- RT5682_JDH_PLUG
- RT5682_JDH_RS_MASK
- RT5682_JD_CTRL_1
- RT5682_JD_MODE
- RT5682_JD_MODE_SFT
- RT5682_JD_NULL
- RT5682_JD_TOP_VC_VTRL
- RT5682_LDO1_BYPASS
- RT5682_LDO1_BYPASS_MASK
- RT5682_LDO1_DBG_MASK
- RT5682_LDO1_DVO_09
- RT5682_LDO1_DVO_10
- RT5682_LDO1_DVO_12
- RT5682_LDO1_DVO_14
- RT5682_LDO1_DVO_MASK
- RT5682_LDO1_NOT_BYPASS
- RT5682_LOW_HP_AMP_DET
- RT5682_L_EQ_BPF1_A1
- RT5682_L_EQ_BPF1_A2
- RT5682_L_EQ_BPF1_H0
- RT5682_L_EQ_BPF2_A1
- RT5682_L_EQ_BPF2_A2
- RT5682_L_EQ_BPF2_H0
- RT5682_L_EQ_BPF3_A1
- RT5682_L_EQ_BPF3_A2
- RT5682_L_EQ_BPF3_H0
- RT5682_L_EQ_BPF4_A1
- RT5682_L_EQ_BPF4_A2
- RT5682_L_EQ_BPF4_H0
- RT5682_L_EQ_HPF1_A1
- RT5682_L_EQ_HPF1_H0
- RT5682_L_EQ_LPF1_H0
- RT5682_L_EQ_POST_VOL
- RT5682_L_EQ_PRE_VOL
- RT5682_L_MUTE
- RT5682_L_MUTE_SFT
- RT5682_L_VOL_MASK
- RT5682_L_VOL_SFT
- RT5682_MB1_PATH_MASK
- RT5682_MB2_PATH_MASK
- RT5682_MIC1_CLK_DIS
- RT5682_MIC1_CLK_EN
- RT5682_MIC1_CLK_MASK
- RT5682_MIC1_CLK_SFT
- RT5682_MIC1_OVCD_DIS
- RT5682_MIC1_OVCD_EN
- RT5682_MIC1_OVCD_MASK
- RT5682_MIC1_OVCD_SFT
- RT5682_MIC1_OVTH_1152UA
- RT5682_MIC1_OVTH_1960UA
- RT5682_MIC1_OVTH_768UA
- RT5682_MIC1_OVTH_960UA
- RT5682_MIC1_OVTH_MASK
- RT5682_MIC1_OVTH_SFT
- RT5682_MIC1_OV_1V8
- RT5682_MIC1_OV_2V25
- RT5682_MIC1_OV_2V4
- RT5682_MIC1_OV_2V7
- RT5682_MIC1_OV_MASK
- RT5682_MIC1_OV_SFT
- RT5682_MIC2_CLK_DIS
- RT5682_MIC2_CLK_EN
- RT5682_MIC2_CLK_MASK
- RT5682_MIC2_CLK_SFT
- RT5682_MIC2_OVTH_1152UA
- RT5682_MIC2_OVTH_1960UA
- RT5682_MIC2_OVTH_768UA
- RT5682_MIC2_OVTH_960UA
- RT5682_MIC2_OVTH_MASK
- RT5682_MIC2_OVTH_SFT
- RT5682_MIC2_OV_1V8
- RT5682_MIC2_OV_2V25
- RT5682_MIC2_OV_2V4
- RT5682_MIC2_OV_2V7
- RT5682_MIC2_OV_MASK
- RT5682_MIC2_OV_SFT
- RT5682_MICBIAS_1
- RT5682_MICBIAS_2
- RT5682_MIC_CAP_HP
- RT5682_MIC_CAP_HS
- RT5682_MIC_CAP_MASK
- RT5682_MIC_CAP_SRC_ANA
- RT5682_MIC_CAP_SRC_MASK
- RT5682_MIC_CAP_SRC_REG
- RT5682_MID_HP_AMP_DET
- RT5682_M_ADCMIX_L
- RT5682_M_ADCMIX_L_SFT
- RT5682_M_ADCMIX_R
- RT5682_M_ADCMIX_R_SFT
- RT5682_M_CBJ_RM1_L
- RT5682_M_CBJ_RM1_L_SFT
- RT5682_M_DAC1_L
- RT5682_M_DAC1_L_SFT
- RT5682_M_DAC1_R
- RT5682_M_DAC1_R_SFT
- RT5682_M_DAC_L1_STO_L
- RT5682_M_DAC_L1_STO_L_SFT
- RT5682_M_DAC_L1_STO_R
- RT5682_M_DAC_L1_STO_R_SFT
- RT5682_M_DAC_R1_STO_L
- RT5682_M_DAC_R1_STO_L_SFT
- RT5682_M_DAC_R1_STO_R
- RT5682_M_DAC_R1_STO_R_SFT
- RT5682_M_STO1_ADC_L1
- RT5682_M_STO1_ADC_L1_SFT
- RT5682_M_STO1_ADC_L2
- RT5682_M_STO1_ADC_L2_SFT
- RT5682_M_STO1_ADC_R1
- RT5682_M_STO1_ADC_R1_SFT
- RT5682_M_STO1_ADC_R2
- RT5682_M_STO1_ADC_R2_SFT
- RT5682_M_ST_STO_L
- RT5682_M_ST_STO_L_SFT
- RT5682_M_ST_STO_R
- RT5682_M_ST_STO_R_SFT
- RT5682_NG2_DIS
- RT5682_NG2_EN
- RT5682_NG2_EN_MASK
- RT5682_NUM_SUPPLIES
- RT5682_OSW_L_DIS
- RT5682_OSW_L_EN
- RT5682_OSW_L_MASK
- RT5682_OSW_L_SFT
- RT5682_OSW_R_DIS
- RT5682_OSW_R_EN
- RT5682_OSW_R_MASK
- RT5682_OSW_R_SFT
- RT5682_PAD_DRIVING_CTRL
- RT5682_PLL1_CLK_DET
- RT5682_PLL1_CLK_DET_SFT
- RT5682_PLL1_INTERNAL
- RT5682_PLL1_SRC_BCLK1
- RT5682_PLL1_SRC_MASK
- RT5682_PLL1_SRC_MCLK
- RT5682_PLL1_SRC_RC
- RT5682_PLL1_SRC_SDW
- RT5682_PLL1_SRC_SFT
- RT5682_PLL1_S_BCLK1
- RT5682_PLL1_S_MCLK
- RT5682_PLL1_S_RCCLK
- RT5682_PLL2_CLK_DET
- RT5682_PLL2_CLK_DET_SFT
- RT5682_PLL2_CTRL_1
- RT5682_PLL2_CTRL_2
- RT5682_PLL2_CTRL_3
- RT5682_PLL2_CTRL_4
- RT5682_PLL2_INTERNAL
- RT5682_PLL2_OUT_49M
- RT5682_PLL2_OUT_98M
- RT5682_PLL2_OUT_MASK
- RT5682_PLL2_SRC_BCLK1
- RT5682_PLL2_SRC_MASK
- RT5682_PLL2_SRC_MCLK
- RT5682_PLL2_SRC_RC
- RT5682_PLL2_SRC_SDW
- RT5682_PLL2_SRC_SFT
- RT5682_PLL_CTRL_1
- RT5682_PLL_CTRL_2
- RT5682_PLL_FREQ
- RT5682_PLL_INP_MAX
- RT5682_PLL_INP_MIN
- RT5682_PLL_K_BP
- RT5682_PLL_K_BP_SFT
- RT5682_PLL_K_MASK
- RT5682_PLL_K_MAX
- RT5682_PLL_K_SFT
- RT5682_PLL_M_BP
- RT5682_PLL_M_BP_SFT
- RT5682_PLL_M_MASK
- RT5682_PLL_M_MAX
- RT5682_PLL_M_SFT
- RT5682_PLL_N_MASK
- RT5682_PLL_N_MAX
- RT5682_PLL_N_SFT
- RT5682_PLL_RST
- RT5682_PLL_TRACK_1
- RT5682_PLL_TRACK_11
- RT5682_PLL_TRACK_12
- RT5682_PLL_TRACK_14
- RT5682_PLL_TRACK_2
- RT5682_PLL_TRACK_3
- RT5682_PLL_TRACK_4
- RT5682_PLL_TRACK_5
- RT5682_PLL_TRACK_6
- RT5682_PM_HP_HV
- RT5682_PM_HP_LV
- RT5682_PM_HP_MASK
- RT5682_PM_HP_MV
- RT5682_PM_HP_SFT
- RT5682_POLA_EXT_JD_HIGH
- RT5682_POLA_EXT_JD_LOW
- RT5682_POLA_EXT_JD_MASK
- RT5682_POL_FAST_OFF_HIGH
- RT5682_POL_FAST_OFF_LOW
- RT5682_POL_FAST_OFF_MASK
- RT5682_POW_ANA
- RT5682_POW_CLK_DET2_SFT
- RT5682_POW_CLK_DET_SFT
- RT5682_POW_IRQ
- RT5682_POW_JDH
- RT5682_POW_JDL
- RT5682_PUMP_EN
- RT5682_PUMP_EN_SFT
- RT5682_PWR_ADC_L1
- RT5682_PWR_ADC_L1_BIT
- RT5682_PWR_ADC_R1
- RT5682_PWR_ADC_R1_BIT
- RT5682_PWR_ADC_S1F
- RT5682_PWR_ADC_S1F_BIT
- RT5682_PWR_ANLG_1
- RT5682_PWR_ANLG_2
- RT5682_PWR_ANLG_3
- RT5682_PWR_BG
- RT5682_PWR_BG_BIT
- RT5682_PWR_CBJ
- RT5682_PWR_CBJ_BIT
- RT5682_PWR_CLK1M_MASK
- RT5682_PWR_CLK1M_PD
- RT5682_PWR_CLK1M_PU
- RT5682_PWR_CLK1M_SFT
- RT5682_PWR_CLK25M_MASK
- RT5682_PWR_CLK25M_PD
- RT5682_PWR_CLK25M_PU
- RT5682_PWR_CLK25M_SFT
- RT5682_PWR_DAC_L1
- RT5682_PWR_DAC_L1_BIT
- RT5682_PWR_DAC_R1
- RT5682_PWR_DAC_R1_BIT
- RT5682_PWR_DAC_S1F
- RT5682_PWR_DAC_S1F_BIT
- RT5682_PWR_DET_SPKVDD
- RT5682_PWR_DET_SPKVDD_BIT
- RT5682_PWR_DIG_1
- RT5682_PWR_DIG_2
- RT5682_PWR_FV1
- RT5682_PWR_FV1_BIT
- RT5682_PWR_FV2
- RT5682_PWR_FV2_BIT
- RT5682_PWR_HA_L
- RT5682_PWR_HA_L_BIT
- RT5682_PWR_HA_R
- RT5682_PWR_HA_R_BIT
- RT5682_PWR_I2S1
- RT5682_PWR_I2S1_BIT
- RT5682_PWR_I2S2
- RT5682_PWR_I2S2_BIT
- RT5682_PWR_JDH
- RT5682_PWR_JDH_BIT
- RT5682_PWR_JDL
- RT5682_PWR_JDL_BIT
- RT5682_PWR_LDO
- RT5682_PWR_LDO2
- RT5682_PWR_LDO2_BIT
- RT5682_PWR_LDO_BIT
- RT5682_PWR_MA_BIT
- RT5682_PWR_MB
- RT5682_PWR_MB1
- RT5682_PWR_MB1_BIT
- RT5682_PWR_MB1_PWR_DOWN
- RT5682_PWR_MB2
- RT5682_PWR_MB2_BIT
- RT5682_PWR_MB2_PWR_DOWN
- RT5682_PWR_MB_BIT
- RT5682_PWR_MB_MASK
- RT5682_PWR_MB_PD
- RT5682_PWR_MB_PU
- RT5682_PWR_MB_SFT
- RT5682_PWR_MIXER
- RT5682_PWR_PLL
- RT5682_PWR_PLL2B
- RT5682_PWR_PLL2B_BIT
- RT5682_PWR_PLL2F
- RT5682_PWR_PLL2F_BIT
- RT5682_PWR_PLL_BIT
- RT5682_PWR_RM1_L
- RT5682_PWR_RM1_L_BIT
- RT5682_PWR_STO1_DAC_L
- RT5682_PWR_STO1_DAC_L_BIT
- RT5682_PWR_STO1_DAC_R
- RT5682_PWR_STO1_DAC_R_BIT
- RT5682_PWR_VOL
- RT5682_PWR_VREF1
- RT5682_PWR_VREF1_BIT
- RT5682_PWR_VREF2
- RT5682_PWR_VREF2_BIT
- RT5682_RAMP_DIS
- RT5682_RAMP_EN
- RT5682_RAMP_MASK
- RT5682_RAMP_SFT
- RT5682_RC_CLK_CTRL
- RT5682_REC_MIXER
- RT5682_RESET
- RT5682_RESET_HPF_CTRL
- RT5682_RESET_LPF_CTRL
- RT5682_R_EQ_BPF1_A1
- RT5682_R_EQ_BPF1_A2
- RT5682_R_EQ_BPF1_H0
- RT5682_R_EQ_BPF2_A1
- RT5682_R_EQ_BPF2_A2
- RT5682_R_EQ_BPF2_H0
- RT5682_R_EQ_BPF3_A1
- RT5682_R_EQ_BPF3_A2
- RT5682_R_EQ_BPF3_H0
- RT5682_R_EQ_BPF4_A1
- RT5682_R_EQ_BPF4_A2
- RT5682_R_EQ_BPF4_H0
- RT5682_R_EQ_HPF1_A1
- RT5682_R_EQ_HPF1_H0
- RT5682_R_EQ_LPF1_A1
- RT5682_R_EQ_LPF1_H0
- RT5682_R_EQ_POST_VOL
- RT5682_R_EQ_PRE_VOL
- RT5682_R_MUTE
- RT5682_R_MUTE_SFT
- RT5682_R_VOL_MASK
- RT5682_R_VOL_SFT
- RT5682_SAR_BUTDET_MODE_MASK
- RT5682_SAR_BUTDET_POW_NORM
- RT5682_SAR_BUTDET_POW_SAV
- RT5682_SAR_BUTDET_RST
- RT5682_SAR_BUTDET_RST_MASK
- RT5682_SAR_BUTDET_RST_NORMAL
- RT5682_SAR_BUTT_DET_DIS
- RT5682_SAR_BUTT_DET_EN
- RT5682_SAR_BUTT_DET_MASK
- RT5682_SAR_BYPASS_DIS
- RT5682_SAR_BYPASS_EN
- RT5682_SAR_BYPASS_MASK
- RT5682_SAR_IL_CMD_1
- RT5682_SAR_IL_CMD_10
- RT5682_SAR_IL_CMD_11
- RT5682_SAR_IL_CMD_12
- RT5682_SAR_IL_CMD_13
- RT5682_SAR_IL_CMD_2
- RT5682_SAR_IL_CMD_3
- RT5682_SAR_IL_CMD_4
- RT5682_SAR_IL_CMD_5
- RT5682_SAR_IL_CMD_6
- RT5682_SAR_IL_CMD_7
- RT5682_SAR_IL_CMD_8
- RT5682_SAR_IL_CMD_9
- RT5682_SAR_POW_DIS
- RT5682_SAR_POW_EN
- RT5682_SAR_POW_MASK
- RT5682_SAR_RST
- RT5682_SAR_RST_MASK
- RT5682_SAR_RST_NORMAL
- RT5682_SAR_SEL_MB1_MASK
- RT5682_SAR_SEL_MB1_MB2_AUTO
- RT5682_SAR_SEL_MB1_MB2_MANU
- RT5682_SAR_SEL_MB1_MB2_MASK
- RT5682_SAR_SEL_MB1_NOSEL
- RT5682_SAR_SEL_MB1_SEL
- RT5682_SAR_SEL_MB2_MASK
- RT5682_SAR_SEL_MB2_NOSEL
- RT5682_SAR_SEL_MB2_SEL
- RT5682_SAR_SEL_MODE_ADC
- RT5682_SAR_SEL_MODE_CMP
- RT5682_SAR_SEL_MODE_MASK
- RT5682_SAR_SEL_SIGNAL_AUTO
- RT5682_SAR_SEL_SIGNAL_MANU
- RT5682_SAR_SEL_SIGNAL_MASK
- RT5682_SAR_SOUR_BTN
- RT5682_SAR_SOUR_MASK
- RT5682_SAR_SOUR_TYPE
- RT5682_SCLK_SRC_MASK
- RT5682_SCLK_SRC_MCLK
- RT5682_SCLK_SRC_PLL1
- RT5682_SCLK_SRC_PLL2
- RT5682_SCLK_SRC_RCCLK
- RT5682_SCLK_SRC_SDW
- RT5682_SCLK_SRC_SFT
- RT5682_SCLK_S_MCLK
- RT5682_SCLK_S_PLL1
- RT5682_SCLK_S_PLL2
- RT5682_SCLK_S_RCCLK
- RT5682_SDW_REF_1_11K
- RT5682_SDW_REF_1_12K
- RT5682_SDW_REF_1_16K
- RT5682_SDW_REF_1_176K
- RT5682_SDW_REF_1_192K
- RT5682_SDW_REF_1_22K
- RT5682_SDW_REF_1_24K
- RT5682_SDW_REF_1_32K
- RT5682_SDW_REF_1_353K
- RT5682_SDW_REF_1_384K
- RT5682_SDW_REF_1_44K
- RT5682_SDW_REF_1_48K
- RT5682_SDW_REF_1_88K
- RT5682_SDW_REF_1_8K
- RT5682_SDW_REF_1_96K
- RT5682_SDW_REF_1_MASK
- RT5682_SDW_REF_1_SFT
- RT5682_SDW_REF_2_11K
- RT5682_SDW_REF_2_12K
- RT5682_SDW_REF_2_16K
- RT5682_SDW_REF_2_176K
- RT5682_SDW_REF_2_192K
- RT5682_SDW_REF_2_22K
- RT5682_SDW_REF_2_24K
- RT5682_SDW_REF_2_32K
- RT5682_SDW_REF_2_353K
- RT5682_SDW_REF_2_384K
- RT5682_SDW_REF_2_44K
- RT5682_SDW_REF_2_48K
- RT5682_SDW_REF_2_88K
- RT5682_SDW_REF_2_8K
- RT5682_SDW_REF_2_96K
- RT5682_SDW_REF_2_MASK
- RT5682_SDW_REF_2_SFT
- RT5682_SDW_REF_CLK
- RT5682_SEL_ADCDAT_IN
- RT5682_SEL_ADCDAT_MASK
- RT5682_SEL_ADCDAT_OUT
- RT5682_SEL_ADCDAT_SFT
- RT5682_SEL_CLK_VOL_DIS
- RT5682_SEL_CLK_VOL_EN
- RT5682_SEL_CLK_VOL_MASK
- RT5682_SEL_SHT_MID_TON_2
- RT5682_SEL_SHT_MID_TON_3
- RT5682_SEL_SHT_MID_TON_MASK
- RT5682_SIDETONE_CTRL
- RT5682_SIL_PSV_CTRL1
- RT5682_SIL_PSV_CTRL2
- RT5682_SIL_PSV_CTRL3
- RT5682_SIL_PSV_CTRL4
- RT5682_SIL_PSV_CTRL5
- RT5682_SOFT_RAMP_DEPOP
- RT5682_SPKVDD_DET_STA
- RT5682_STEREO_RATES
- RT5682_STO1_ADC1L_SRC_MASK
- RT5682_STO1_ADC1L_SRC_SFT
- RT5682_STO1_ADC1R_SRC_MASK
- RT5682_STO1_ADC1R_SRC_SFT
- RT5682_STO1_ADC1_SRC_ADC
- RT5682_STO1_ADC1_SRC_DACMIX
- RT5682_STO1_ADC2L_SRC_MASK
- RT5682_STO1_ADC2L_SRC_SFT
- RT5682_STO1_ADC2R_SRC_MASK
- RT5682_STO1_ADC2R_SRC_SFT
- RT5682_STO1_ADCL_SRC_MASK
- RT5682_STO1_ADCL_SRC_SFT
- RT5682_STO1_ADCR_SRC_MASK
- RT5682_STO1_ADCR_SRC_SFT
- RT5682_STO1_ADC_BOOST
- RT5682_STO1_ADC_DIG_VOL
- RT5682_STO1_ADC_L_BST_MASK
- RT5682_STO1_ADC_L_BST_SFT
- RT5682_STO1_ADC_MIXER
- RT5682_STO1_ADC_R_BST_MASK
- RT5682_STO1_ADC_R_BST_SFT
- RT5682_STO1_DAC_MIXER
- RT5682_STO1_DAC_SIL_DET
- RT5682_STO1_DD_L_SRC_MASK
- RT5682_STO1_DD_L_SRC_SFT
- RT5682_STO1_DMIC_SRC_DMIC1
- RT5682_STO1_DMIC_SRC_DMIC2
- RT5682_STO1_DMIC_SRC_MASK
- RT5682_STO1_DMIC_SRC_SFT
- RT5682_STO_NG2_CTRL_1
- RT5682_STO_NG2_CTRL_10
- RT5682_STO_NG2_CTRL_2
- RT5682_STO_NG2_CTRL_3
- RT5682_STO_NG2_CTRL_4
- RT5682_STO_NG2_CTRL_5
- RT5682_STO_NG2_CTRL_6
- RT5682_STO_NG2_CTRL_7
- RT5682_STO_NG2_CTRL_8
- RT5682_STO_NG2_CTRL_9
- RT5682_ST_DIS
- RT5682_ST_EN
- RT5682_ST_EN_MASK
- RT5682_ST_EN_SFT
- RT5682_ST_SRC_SEL
- RT5682_ST_SRC_SFT
- RT5682_SV_DIS
- RT5682_SV_DLY_MASK
- RT5682_SV_DLY_SFT
- RT5682_SV_EN
- RT5682_SV_MASK
- RT5682_SV_SFT
- RT5682_SV_ZCD_1
- RT5682_SV_ZCD_2
- RT5682_SYS_CLK_DET
- RT5682_SYS_CLK_DET_SFT
- RT5682_TDM_ADC_DL_SFT
- RT5682_TDM_ADC_LCA_MASK
- RT5682_TDM_ADC_LCA_SFT
- RT5682_TDM_ADC_SEL_SFT
- RT5682_TDM_ADDA_CTRL_1
- RT5682_TDM_ADDA_CTRL_2
- RT5682_TDM_CL_16
- RT5682_TDM_CL_20
- RT5682_TDM_CL_24
- RT5682_TDM_CL_32
- RT5682_TDM_CL_MASK
- RT5682_TDM_CTRL
- RT5682_TDM_DF_I2S
- RT5682_TDM_DF_LEFT
- RT5682_TDM_DF_MASK
- RT5682_TDM_DF_PCM_A
- RT5682_TDM_DF_PCM_A_N
- RT5682_TDM_DF_PCM_B
- RT5682_TDM_DF_PCM_B_N
- RT5682_TDM_DF_SFT
- RT5682_TDM_EN
- RT5682_TDM_MS_M
- RT5682_TDM_MS_MASK
- RT5682_TDM_MS_S
- RT5682_TDM_MS_SFT
- RT5682_TDM_M_BP_INV
- RT5682_TDM_M_BP_MASK
- RT5682_TDM_M_BP_NOR
- RT5682_TDM_M_BP_SFT
- RT5682_TDM_M_LP_INV
- RT5682_TDM_M_LP_MASK
- RT5682_TDM_M_LP_NOR
- RT5682_TDM_M_LP_SFT
- RT5682_TDM_RX_CH_2
- RT5682_TDM_RX_CH_4
- RT5682_TDM_RX_CH_6
- RT5682_TDM_RX_CH_8
- RT5682_TDM_RX_CH_MASK
- RT5682_TDM_S_BP_INV
- RT5682_TDM_S_BP_MASK
- RT5682_TDM_S_BP_NOR
- RT5682_TDM_S_BP_SFT
- RT5682_TDM_S_LP_INV
- RT5682_TDM_S_LP_MASK
- RT5682_TDM_S_LP_NOR
- RT5682_TDM_S_LP_SFT
- RT5682_TDM_TCON_CTRL
- RT5682_TDM_TX_CH_2
- RT5682_TDM_TX_CH_4
- RT5682_TDM_TX_CH_6
- RT5682_TDM_TX_CH_8
- RT5682_TDM_TX_CH_MASK
- RT5682_TEST_MODE_CTRL_1
- RT5682_TEST_MODE_CTRL_2
- RT5682_TEST_MODE_CTRL_3
- RT5682_TEST_MODE_CTRL_4
- RT5682_TEST_MODE_CTRL_5
- RT5682_TRIG_JD_HIGH
- RT5682_TRIG_JD_LOW
- RT5682_TRIG_JD_MASK
- RT5682_VENDOR_ID
- RT5682_VERSION_ID
- RT5682_VLO_33V
- RT5682_VLO_3V
- RT5682_VLO_MASK
- RT5682_VLO_SFT
- RT5682_VOL_L_MUTE
- RT5682_VOL_L_SFT
- RT5682_VOL_R_MUTE
- RT5682_VOL_R_SFT
- RT5682_VOL_TEST
- RT5682_VREF_POW_FSM
- RT5682_VREF_POW_MASK
- RT5682_VREF_POW_REG
- RT5682_VREF_REC_OP_FB_CAP_CTRL
- RT5682_ZCD_BST1_CBJ_DIS
- RT5682_ZCD_BST1_CBJ_EN
- RT5682_ZCD_BST1_CBJ_MASK
- RT5682_ZCD_BST1_CBJ_SFT
- RT5682_ZCD_MASK
- RT5682_ZCD_PD
- RT5682_ZCD_PU
- RT5682_ZCD_RECMIX_DIS
- RT5682_ZCD_RECMIX_EN
- RT5682_ZCD_RECMIX_MASK
- RT5682_ZCD_RECMIX_SFT
- RT5682_ZCD_SFT
- RT61PCI_H
- RT6352
- RT6_DEBUG
- RT6_LOOKUP_F_DST_NOREF
- RT6_LOOKUP_F_HAS_SADDR
- RT6_LOOKUP_F_IFACE
- RT6_LOOKUP_F_IGNORE_LINKSTATE
- RT6_LOOKUP_F_REACHABLE
- RT6_LOOKUP_F_SRCPREF_COA
- RT6_LOOKUP_F_SRCPREF_PUBLIC
- RT6_LOOKUP_F_SRCPREF_TMP
- RT6_NUD_FAIL_DO_RR
- RT6_NUD_FAIL_HARD
- RT6_NUD_FAIL_PROBE
- RT6_NUD_SUCCEED
- RT6_TABLE_DFLT
- RT6_TABLE_HAS_DFLT_ROUTER
- RT6_TABLE_INFO
- RT6_TABLE_LOCAL
- RT6_TABLE_MAIN
- RT6_TABLE_PREFIX
- RT6_TABLE_UNSPEC
- RT6_TRACE
- RT73USB_H
- RT8973A_EVENT_ATTACH
- RT8973A_EVENT_DETACH
- RT8973A_EVENT_OTP
- RT8973A_EVENT_OVP
- RT8973A_INT1_ADC_CHG
- RT8973A_INT1_ADC_CHG_MASK
- RT8973A_INT1_ATTACH
- RT8973A_INT1_ATTACH_MASK
- RT8973A_INT1_CHGDET
- RT8973A_INT1_CHGDET_MASK
- RT8973A_INT1_CONNECT
- RT8973A_INT1_CONNECT_MASK
- RT8973A_INT1_DCD_T
- RT8973A_INT1_DCD_T_MASK
- RT8973A_INT1_DETACH
- RT8973A_INT1_DETACH_MASK
- RT8973A_INT1_OTP
- RT8973A_INT1_OTP_MASK
- RT8973A_INT1_OVP
- RT8973A_INT1_OVP_MASK
- RT8973A_INT2_OCP
- RT8973A_INT2_OCP_LATCH
- RT8973A_INT2_OCP_LATCH_MASK
- RT8973A_INT2_OCP_MASK
- RT8973A_INT2_OTP_FET
- RT8973A_INT2_OTP_FET_MASK
- RT8973A_INT2_OVP_FET
- RT8973A_INT2_OVP_FET_MASK
- RT8973A_INT2_OVP_OCP
- RT8973A_INT2_OVP_OCP_MASK
- RT8973A_INT2_POR
- RT8973A_INT2_POR_MASK
- RT8973A_INT2_UVLO
- RT8973A_INT2_UVLOT_MASK
- RT8973A_MUIC_ADC_AUDIO_REMOTE_S10_BUTTON
- RT8973A_MUIC_ADC_AUDIO_REMOTE_S11_BUTTON
- RT8973A_MUIC_ADC_AUDIO_REMOTE_S12_BUTTON
- RT8973A_MUIC_ADC_AUDIO_REMOTE_S1_BUTTON
- RT8973A_MUIC_ADC_AUDIO_REMOTE_S2_BUTTON
- RT8973A_MUIC_ADC_AUDIO_REMOTE_S3_BUTTON
- RT8973A_MUIC_ADC_AUDIO_REMOTE_S4_BUTTON
- RT8973A_MUIC_ADC_AUDIO_REMOTE_S5_BUTTON
- RT8973A_MUIC_ADC_AUDIO_REMOTE_S6_BUTTON
- RT8973A_MUIC_ADC_AUDIO_REMOTE_S7_BUTTON
- RT8973A_MUIC_ADC_AUDIO_REMOTE_S8_BUTTON
- RT8973A_MUIC_ADC_AUDIO_REMOTE_S9_BUTTON
- RT8973A_MUIC_ADC_AUDIO_SEND_END_BUTTON
- RT8973A_MUIC_ADC_AUDIO_TYPE2
- RT8973A_MUIC_ADC_FACTORY_MODE_BOOT_OFF_UART
- RT8973A_MUIC_ADC_FACTORY_MODE_BOOT_OFF_USB
- RT8973A_MUIC_ADC_FACTORY_MODE_BOOT_ON_UART
- RT8973A_MUIC_ADC_FACTORY_MODE_BOOT_ON_USB
- RT8973A_MUIC_ADC_OPEN
- RT8973A_MUIC_ADC_OTG
- RT8973A_MUIC_ADC_PHONE_POWERED_DEV
- RT8973A_MUIC_ADC_RESERVED_ACC_1
- RT8973A_MUIC_ADC_RESERVED_ACC_2
- RT8973A_MUIC_ADC_RESERVED_ACC_3
- RT8973A_MUIC_ADC_RESERVED_ACC_4
- RT8973A_MUIC_ADC_RESERVED_ACC_5
- RT8973A_MUIC_ADC_TA
- RT8973A_MUIC_ADC_UNKNOWN_ACC_1
- RT8973A_MUIC_ADC_UNKNOWN_ACC_2
- RT8973A_MUIC_ADC_UNKNOWN_ACC_3
- RT8973A_MUIC_ADC_UNKNOWN_ACC_4
- RT8973A_MUIC_ADC_UNKNOWN_ACC_5
- RT8973A_MUIC_ADC_USB
- RT8973A_NUM
- RT8973A_REG_ADC
- RT8973A_REG_ADC_MASK
- RT8973A_REG_ADC_SHIFT
- RT8973A_REG_CONTROL1
- RT8973A_REG_CONTROL1_ADC_EN_MASK
- RT8973A_REG_CONTROL1_ADC_EN_SHIFT
- RT8973A_REG_CONTROL1_AUTO_CONFIG_MASK
- RT8973A_REG_CONTROL1_AUTO_CONFIG_SHIFT
- RT8973A_REG_CONTROL1_CHGTYP_MASK
- RT8973A_REG_CONTROL1_CHGTYP_SHIFT
- RT8973A_REG_CONTROL1_I2C_RST_EN_MASK
- RT8973A_REG_CONTROL1_I2C_RST_EN_SHIFT
- RT8973A_REG_CONTROL1_INTM_MASK
- RT8973A_REG_CONTROL1_INTM_SHIFT
- RT8973A_REG_CONTROL1_SWITCH_OPEN_MASK
- RT8973A_REG_CONTROL1_SWITCH_OPEN_SHIFT
- RT8973A_REG_CONTROL1_USB_CHD_EN_MASK
- RT8973A_REG_CONTROL1_USB_CHD_EN_SHIFT
- RT8973A_REG_DEV1
- RT8973A_REG_DEV1_CAR_KIT_TYPE1_MASK
- RT8973A_REG_DEV1_CAR_KIT_TYPE1_SHIFT
- RT8973A_REG_DEV1_CDPORT_MASK
- RT8973A_REG_DEV1_CDPORT_SHIFT
- RT8973A_REG_DEV1_DCPORT_MASK
- RT8973A_REG_DEV1_DCPORT_SHIFT
- RT8973A_REG_DEV1_OTG_MASK
- RT8973A_REG_DEV1_OTG_SHIFT
- RT8973A_REG_DEV1_SDP_MASK
- RT8973A_REG_DEV1_SDP_SHIFT
- RT8973A_REG_DEV1_UART_MASK
- RT8973A_REG_DEV1_UART_SHIFT
- RT8973A_REG_DEV1_USB_MASK
- RT8973A_REG_DEV2
- RT8973A_REG_DEV2_JIG_UART_OFF_MASK
- RT8973A_REG_DEV2_JIG_UART_OFF_SHIFT
- RT8973A_REG_DEV2_JIG_UART_ON_MASK
- RT8973A_REG_DEV2_JIG_UART_ON_SHIFT
- RT8973A_REG_DEV2_JIG_USB_OFF_MASK
- RT8973A_REG_DEV2_JIG_USB_OFF_SHIFT
- RT8973A_REG_DEV2_JIG_USB_ON_MASK
- RT8973A_REG_DEV2_JIG_USB_ON_SHIFT
- RT8973A_REG_DEVICE_ID
- RT8973A_REG_DEVICE_ID_VENDOR_MASK
- RT8973A_REG_DEVICE_ID_VENDOR_SHIFT
- RT8973A_REG_DEVICE_ID_VERSION_MASK
- RT8973A_REG_DEVICE_ID_VERSION_SHIFT
- RT8973A_REG_END
- RT8973A_REG_INT1
- RT8973A_REG_INT2
- RT8973A_REG_INTM1
- RT8973A_REG_INTM2
- RT8973A_REG_MANUAL_SW1
- RT8973A_REG_MANUAL_SW1_DM_MASK
- RT8973A_REG_MANUAL_SW1_DM_SHIFT
- RT8973A_REG_MANUAL_SW1_DP_MASK
- RT8973A_REG_MANUAL_SW1_DP_SHIFT
- RT8973A_REG_MANUAL_SW2
- RT8973A_REG_MANUAL_SW2_BOOT_SW_MASK
- RT8973A_REG_MANUAL_SW2_BOOT_SW_OFF
- RT8973A_REG_MANUAL_SW2_BOOT_SW_ON
- RT8973A_REG_MANUAL_SW2_BOOT_SW_SHIFT
- RT8973A_REG_MANUAL_SW2_FET_OFF
- RT8973A_REG_MANUAL_SW2_FET_ON
- RT8973A_REG_MANUAL_SW2_FET_ON_MASK
- RT8973A_REG_MANUAL_SW2_FET_ON_SHIFT
- RT8973A_REG_MANUAL_SW2_JIG_OFF
- RT8973A_REG_MANUAL_SW2_JIG_ON
- RT8973A_REG_MANUAL_SW2_JIG_ON_MASK
- RT8973A_REG_MANUAL_SW2_JIG_ON_SHIFT
- RT8973A_REG_RESET
- RT8973A_REG_RESET_MASK
- RT8973A_REG_RESET_SHIFT
- RT8973A_REG_RSVD_1
- RT8973A_REG_RSVD_10
- RT8973A_REG_RSVD_11
- RT8973A_REG_RSVD_12
- RT8973A_REG_RSVD_13
- RT8973A_REG_RSVD_14
- RT8973A_REG_RSVD_15
- RT8973A_REG_RSVD_2
- RT8973A_REG_RSVD_3
- RT8973A_REG_RSVD_4
- RT8973A_REG_RSVD_5
- RT8973A_REG_RSVD_6
- RT8973A_REG_RSVD_7
- RT8973A_REG_RSVD_8
- RT8973A_REG_RSVD_9
- RT9455_BATT_PRESENCE_DELAY
- RT9455_BOOST_MODE
- RT9455_CHARGE_DISABLE
- RT9455_CHARGE_ENABLE
- RT9455_CHARGE_MODE
- RT9455_DRIVER_NAME
- RT9455_FAULT
- RT9455_IAICR_100MA
- RT9455_IAICR_500MA
- RT9455_IAICR_NO_LIMIT
- RT9455_IRQ_NAME
- RT9455_MANUFACTURER
- RT9455_MAX_CHARGING_TIME
- RT9455_MODEL_NAME
- RT9455_PWR_FAULT
- RT9455_PWR_GOOD
- RT9455_PWR_RDY_DELAY
- RT9455_REG_CTRL1
- RT9455_REG_CTRL2
- RT9455_REG_CTRL3
- RT9455_REG_CTRL4
- RT9455_REG_CTRL5
- RT9455_REG_CTRL6
- RT9455_REG_CTRL7
- RT9455_REG_DEV_ID
- RT9455_REG_IRQ1
- RT9455_REG_IRQ2
- RT9455_REG_IRQ3
- RT9455_REG_MASK1
- RT9455_REG_MASK2
- RT9455_REG_MASK3
- RT9873A_REG_INTM1_ADC_CHG_MASK
- RT9873A_REG_INTM1_ADC_CHG_SHIFT
- RT9873A_REG_INTM1_ATTACH_MASK
- RT9873A_REG_INTM1_ATTACH_SHIFT
- RT9873A_REG_INTM1_CHGDET_MASK
- RT9873A_REG_INTM1_CHGDET_SHIFT
- RT9873A_REG_INTM1_CONNECT_MASK
- RT9873A_REG_INTM1_CONNECT_SHIFT
- RT9873A_REG_INTM1_DCD_T_MASK
- RT9873A_REG_INTM1_DCD_T_SHIFT
- RT9873A_REG_INTM1_DETACH_MASK
- RT9873A_REG_INTM1_DETACH_SHIFT
- RT9873A_REG_INTM1_OTP_MASK
- RT9873A_REG_INTM1_OTP_SHIFT
- RT9873A_REG_INTM1_OVP_MASK
- RT9873A_REG_INTM1_OVP_SHIFT
- RT9873A_REG_INTM2_OCP_LATCH_MASK
- RT9873A_REG_INTM2_OCP_LATCH_SHIFT
- RT9873A_REG_INTM2_OCP_MASK
- RT9873A_REG_INTM2_OCP_SHIFT
- RT9873A_REG_INTM2_OTP_FET_MASK
- RT9873A_REG_INTM2_OTP_FET_SHIFT
- RT9873A_REG_INTM2_OVP_FET_MASK
- RT9873A_REG_INTM2_OVP_FET_SHIFT
- RT9873A_REG_INTM2_OVP_OCP_MASK
- RT9873A_REG_INTM2_OVP_OCP_SHIFT
- RT9873A_REG_INTM2_POR_MASK
- RT9873A_REG_INTM2_POR_SHIFT
- RT9873A_REG_INTM2_UVLO_MASK
- RT9873A_REG_INTM2_UVLO_SHIFT
- RTA
- RTABORT
- RTABT
- RTAIL
- RTAR
- RTAS_BLKLIST_LENGTH
- RTAS_BLK_SIZE
- RTAS_BUSY
- RTAS_CHANGE_32MSI_FN
- RTAS_CHANGE_FN
- RTAS_CHANGE_MSIX_FN
- RTAS_CHANGE_MSI_FN
- RTAS_CLOCK_BUSY
- RTAS_COMMIT_TMP_IMG
- RTAS_DATA_BUF_SIZE
- RTAS_DEBUG
- RTAS_DISP_FULLY_RECOVERED
- RTAS_DISP_LIMITED_RECOVERY
- RTAS_DISP_NOT_RECOVERED
- RTAS_EPOW_WARNING
- RTAS_ERROR_LOG_MAX
- RTAS_EVENT_SCAN_ALL_EVENTS
- RTAS_EXTENDED_DELAY_MAX
- RTAS_EXTENDED_DELAY_MIN
- RTAS_FADUMP_CPU_ID_MASK
- RTAS_FADUMP_CPU_STATE_DATA
- RTAS_FADUMP_ERROR_FLAG
- RTAS_FADUMP_GPR_MASK
- RTAS_FADUMP_HPTE_REGION
- RTAS_FADUMP_MIN_BOOT_MEM
- RTAS_FADUMP_REAL_MODE_REGION
- RTAS_FADUMP_REQUEST_FLAG
- RTAS_FADUMP_SKIP_TO_NEXT_CPU
- RTAS_HOTPLUG_EVENTS
- RTAS_INITIATOR_CPU
- RTAS_INITIATOR_ISA
- RTAS_INITIATOR_MEMORY
- RTAS_INITIATOR_PCI
- RTAS_INITIATOR_POWERMGM
- RTAS_INITIATOR_UNKNOWN
- RTAS_INSTANTIATE_MAX
- RTAS_INTERNAL_ERROR
- RTAS_IO_EVENTS
- RTAS_MSG_MAXLEN
- RTAS_NOT_SUSPENDABLE
- RTAS_QUERY_FN
- RTAS_RC_BUSY
- RTAS_RC_HW_ERR
- RTAS_RC_SUCCESS
- RTAS_REJECT_TMP_IMG
- RTAS_RESET_FN
- RTAS_RMOBUF_MAX
- RTAS_SEVERITY_ERROR
- RTAS_SEVERITY_ERROR_SYNC
- RTAS_SEVERITY_EVENT
- RTAS_SEVERITY_FATAL
- RTAS_SEVERITY_NO_ERROR
- RTAS_SEVERITY_WARNING
- RTAS_TARGET_CPU
- RTAS_TARGET_ISA
- RTAS_TARGET_MEMORY
- RTAS_TARGET_PCI
- RTAS_TARGET_POWERMGM
- RTAS_TARGET_UNKNOWN
- RTAS_TYPE_ADDR_INVALID
- RTAS_TYPE_ADDR_PARITY
- RTAS_TYPE_CACHE_PARITY
- RTAS_TYPE_DATA_PARITY
- RTAS_TYPE_DEALLOC
- RTAS_TYPE_DUMP
- RTAS_TYPE_ECC_CORR
- RTAS_TYPE_ECC_UNCORR
- RTAS_TYPE_EPOW
- RTAS_TYPE_HOTPLUG
- RTAS_TYPE_INFO
- RTAS_TYPE_INTERN_DEV_FAIL
- RTAS_TYPE_IO
- RTAS_TYPE_PLATFORM
- RTAS_TYPE_PMGM_BATTERY_CRIT
- RTAS_TYPE_PMGM_BATTERY_WARN
- RTAS_TYPE_PMGM_CONFIG_CHANGE
- RTAS_TYPE_PMGM_ENCLOS_CLOSED
- RTAS_TYPE_PMGM_ENCLOS_OPEN
- RTAS_TYPE_PMGM_KBD_OR_MOUSE
- RTAS_TYPE_PMGM_LAN_ATTENTION
- RTAS_TYPE_PMGM_LID_CLOSE
- RTAS_TYPE_PMGM_LID_OPEN
- RTAS_TYPE_PMGM_POWER_SW_OFF
- RTAS_TYPE_PMGM_POWER_SW_ON
- RTAS_TYPE_PMGM_RING_INDICATE
- RTAS_TYPE_PMGM_SERVICE_PROC
- RTAS_TYPE_PMGM_SLEEP_BTN
- RTAS_TYPE_PMGM_SWITCH_TO_AC
- RTAS_TYPE_PMGM_SWITCH_TO_BAT
- RTAS_TYPE_PMGM_TIME_ALARM
- RTAS_TYPE_PMGM_WAKE_BTN
- RTAS_TYPE_PRRN
- RTAS_TYPE_RETRY
- RTAS_TYPE_TCE_ERR
- RTAS_TYPE_TIMEOUT
- RTAS_UNKNOWN_SERVICE
- RTAS_V6EXT_COMPANY_ID_IBM
- RTAS_V6EXT_LOG_FORMAT_EVENT_LOG
- RTAS_VECTOR_EXTERNAL_INTERRUPT
- RTAX_ADVMSS
- RTAX_CC_ALGO
- RTAX_CWND
- RTAX_FASTOPEN_NO_COOKIE
- RTAX_FEATURES
- RTAX_FEATURE_ALLFRAG
- RTAX_FEATURE_ECN
- RTAX_FEATURE_MASK
- RTAX_FEATURE_SACK
- RTAX_FEATURE_TIMESTAMP
- RTAX_HOPLIMIT
- RTAX_INITCWND
- RTAX_INITRWND
- RTAX_LOCK
- RTAX_MAX
- RTAX_MTU
- RTAX_QUICKACK
- RTAX_REORDERING
- RTAX_RTO_MIN
- RTAX_RTT
- RTAX_RTTVAR
- RTAX_SSTHRESH
- RTAX_UNSPEC
- RTAX_WINDOW
- RTA_ALIGN
- RTA_ALIGNTO
- RTA_CACHEINFO
- RTA_DATA
- RTA_DPORT
- RTA_DST
- RTA_ENCAP
- RTA_ENCAP_TYPE
- RTA_EXPIRES
- RTA_FLOW
- RTA_GATEWAY
- RTA_IIF
- RTA_IP_PROTO
- RTA_LENGTH
- RTA_MARK
- RTA_MAX
- RTA_METRICS
- RTA_MFC_STATS
- RTA_MP_ALGO
- RTA_MULTIPATH
- RTA_NEWDST
- RTA_NEXT
- RTA_NH_ID
- RTA_OIF
- RTA_OK
- RTA_PAD
- RTA_PAYLOAD
- RTA_PREF
- RTA_PREFSRC
- RTA_PRIORITY
- RTA_PROTOINFO
- RTA_SESSION
- RTA_SPACE
- RTA_SPORT
- RTA_SRC
- RTA_TABLE
- RTA_TTL_PROPAGATE
- RTA_UID
- RTA_UNSPEC
- RTA_VIA
- RTC
- RTC1_USE_XO
- RTC7301_1000_YEAR
- RTC7301_100_YEAR
- RTC7301_10_DAY
- RTC7301_10_HOUR
- RTC7301_10_MIN
- RTC7301_10_MONTH
- RTC7301_10_SEC
- RTC7301_10_YEAR
- RTC7301_1_DAY
- RTC7301_1_HOUR
- RTC7301_1_MIN
- RTC7301_1_MONTH
- RTC7301_1_SEC
- RTC7301_1_YEAR
- RTC7301_AE
- RTC7301_ALARM_CONTROL
- RTC7301_ALARM_CONTROL_AF
- RTC7301_ALARM_CONTROL_AIE
- RTC7301_CONTROL
- RTC7301_CONTROL_BANK_SEL_0
- RTC7301_CONTROL_BANK_SEL_1
- RTC7301_CONTROL_BUSY
- RTC7301_CONTROL_STOP
- RTC7301_DAY_OF_WEEK
- RTC7301_TIMER_CONTROL
- RTC7301_TIMER_CONTROL_TF
- RTC7301_TIMER_CONTROL_TIE
- RTCALRM
- RTCALRM_ADDR
- RTCALRM_HOURS_MASK
- RTCALRM_HOURS_SHIFT
- RTCALRM_MINUTES_MASK
- RTCALRM_MINUTES_SHIFT
- RTCALRM_SECONDS_MASK
- RTCALRM_SECONDS_SHIFT
- RTCAPB
- RTCAPB_CK
- RTCBASE
- RTCCTL
- RTCCTL_384
- RTCCTL_ADDR
- RTCCTL_EN
- RTCCTL_ENABLE
- RTCCTL_XTL
- RTCF_BROADCAST
- RTCF_DEAD
- RTCF_DIRECTDST
- RTCF_DIRECTSRC
- RTCF_DNAT
- RTCF_DOREDIRECT
- RTCF_FAST
- RTCF_LOCAL
- RTCF_MASQ
- RTCF_MULTICAST
- RTCF_NAT
- RTCF_NOPMTUDISC
- RTCF_NOTIFY
- RTCF_ONLINK
- RTCF_REDIRECTED
- RTCF_REJECT
- RTCF_SNAT
- RTCF_TPROXY
- RTCIENR
- RTCIENR_1HZ
- RTCIENR_ADDR
- RTCIENR_ALM
- RTCIENR_DAY
- RTCIENR_HR
- RTCIENR_MIN
- RTCIENR_SAM0
- RTCIENR_SAM1
- RTCIENR_SAM2
- RTCIENR_SAM3
- RTCIENR_SAM4
- RTCIENR_SAM5
- RTCIENR_SAM6
- RTCIENR_SAM7
- RTCIENR_SW
- RTCINTREG
- RTCISR
- RTCISR_1HZ
- RTCISR_ADDR
- RTCISR_ALM
- RTCISR_DAY
- RTCISR_HR
- RTCISR_MIN
- RTCISR_SAM0
- RTCISR_SAM1
- RTCISR_SAM2
- RTCISR_SAM3
- RTCISR_SAM4
- RTCISR_SAM5
- RTCISR_SAM6
- RTCISR_SAM7
- RTCISR_SW
- RTCL
- RTCL1CNTHREG
- RTCL1CNTLREG
- RTCL1HREG
- RTCL1LREG
- RTCL2CNTHREG
- RTCL2CNTLREG
- RTCL2HREG
- RTCL2LREG
- RTCLONG1_INT
- RTCLONG1_IRQ
- RTCLONG2_INT
- RTCLONG2_IRQ
- RTCNT
- RTCPICR
- RTCS2
- RTCSC_38K
- RTCSC_ALE
- RTCSC_ALR
- RTCSC_RTCIRQ_MASK
- RTCSC_RTE
- RTCSC_RTF
- RTCSC_SEC
- RTCSC_SIE
- RTCTIME
- RTCTIME_ADDR
- RTCTIME_HOURS_MASK
- RTCTIME_HOURS_SHIFT
- RTCTIME_MINUTES_MASK
- RTCTIME_MINUTES_SHIFT
- RTCTIME_SECONDS_MASK
- RTCTIME_SECONDS_SHIFT
- RTC_1HZ_BIT
- RTC_24H
- RTC_2HZ_BIT
- RTC_38X_BRIDGE_TIMING_CTL
- RTC_38X_PERIOD_MASK
- RTC_38X_PERIOD_OFFS
- RTC_38X_READ_DELAY_MASK
- RTC_38X_READ_DELAY_OFFS
- RTC_8K_ALARM2
- RTC_8K_BRIDGE_TIMING_CTL0
- RTC_8K_BRIDGE_TIMING_CTL1
- RTC_8K_IMR
- RTC_8K_ISR
- RTC_8K_READ_DELAY_MASK
- RTC_8K_READ_DELAY_OFFS
- RTC_8K_WRCLK_PERIOD_MASK
- RTC_8K_WRCLK_PERIOD_OFFS
- RTC_8K_WRCLK_SETUP_MASK
- RTC_8K_WRCLK_SETUP_OFFS
- RTC_A
- RTC_ADDR0
- RTC_ADDR0_DATA
- RTC_ADDR0_LINE_SCLK
- RTC_ADDR0_LINE_SDI
- RTC_ADDR0_LINE_SEN
- RTC_ADDR0_START_SER
- RTC_ADDR0_WAIT_SER
- RTC_ADDR1
- RTC_ADDR1_SDO
- RTC_ADDR1_S_READY
- RTC_ADDR2
- RTC_ADDR3
- RTC_ADDR_BITS
- RTC_ADDR_CTRL
- RTC_ADDR_DATE
- RTC_ADDR_DAY
- RTC_ADDR_HOUR
- RTC_ADDR_MIN
- RTC_ADDR_MON
- RTC_ADDR_RAM0
- RTC_ADDR_SEC
- RTC_ADDR_TCR
- RTC_ADDR_YEAR
- RTC_AF
- RTC_AIE
- RTC_AIE_OFF
- RTC_AIE_ON
- RTC_ALARM0
- RTC_ALARM0_B
- RTC_ALARM1
- RTC_ALARM1_B
- RTC_ALARM1_HI
- RTC_ALARM2
- RTC_ALARM_BIT
- RTC_ALARM_DATE
- RTC_ALARM_DATE_REG_OFFS
- RTC_ALARM_DONT_CARE
- RTC_ALARM_ENA
- RTC_ALARM_ENABLE
- RTC_ALARM_HOUR
- RTC_ALARM_INTERRUPT_CASUE_REG_OFFS
- RTC_ALARM_INTERRUPT_MASK_REG_OFFS
- RTC_ALARM_MIN
- RTC_ALARM_SEC
- RTC_ALARM_TIME_REG_OFFS
- RTC_ALARM_VALID
- RTC_ALM_BIT
- RTC_ALM_READ
- RTC_ALM_SET
- RTC_ALRM
- RTC_ALRM_HM
- RTC_ALRM_SEC
- RTC_ALWAYS_BCD
- RTC_AL_ALL
- RTC_AL_DOM_MASK
- RTC_AL_DOW_MASK
- RTC_AL_EN
- RTC_AL_HOU_MASK
- RTC_AL_MASK
- RTC_AL_MASK_DOW
- RTC_AL_MIN_MASK
- RTC_AL_MTH_MASK
- RTC_AL_SEC
- RTC_AL_SEC_MASK
- RTC_AL_YEA_MASK
- RTC_ATI
- RTC_BANK1_PWR_CTR_LSB
- RTC_BANK1_PWR_CTR_MSB
- RTC_BANK1_RAM_ADDR
- RTC_BANK1_RAM_ADDR_LSB
- RTC_BANK1_RAM_ADDR_MSB
- RTC_BANK1_RAM_DATA_PORT
- RTC_BANK1_SSN_BYTE_1
- RTC_BANK1_SSN_BYTE_2
- RTC_BANK1_SSN_BYTE_3
- RTC_BANK1_SSN_BYTE_4
- RTC_BANK1_SSN_BYTE_5
- RTC_BANK1_SSN_BYTE_6
- RTC_BANK1_SSN_CRC
- RTC_BANK1_SSN_MODEL
- RTC_BANK1_UNIQ_SN
- RTC_BANK1_VBAT_CTR_LSB
- RTC_BANK1_VBAT_CTR_MSB
- RTC_BANK1_VCC_CTR_LSB
- RTC_BANK1_VCC_CTR_MSB
- RTC_BANK1_WRITE_CTR
- RTC_BASE
- RTC_BASE_ADDRESS
- RTC_BASE_YEAR
- RTC_BATT_EN
- RTC_BATT_FLAG
- RTC_BBPU
- RTC_BBPU_CBUSY
- RTC_BIT
- RTC_BIT_AI
- RTC_BIT_INVERTED
- RTC_BIT_PI
- RTC_BUF_ENABLE
- RTC_BUP_CH_ENA
- RTC_BUSY
- RTC_CALIBRATION
- RTC_CALIB_DEF
- RTC_CALIB_MASK
- RTC_CALIB_RD
- RTC_CALIB_WR
- RTC_CAL_MASK
- RTC_CAP_4_DIGIT_YEAR
- RTC_CCR
- RTC_CCR_EN
- RTC_CCR_IE
- RTC_CCR_MASK
- RTC_CCR_MODE
- RTC_CCR_WEN
- RTC_CCVR
- RTC_CENTURY
- RTC_CENTURY_MASK
- RTC_CK
- RTC_CLASS_DEV_PM_OPS
- RTC_CLCK_BURST
- RTC_CLCK_LEN
- RTC_CLK_ENB
- RTC_CLOCK_SWITCH
- RTC_CLR
- RTC_CMD
- RTC_CMD1
- RTC_CMD_READ
- RTC_CMD_WRITE
- RTC_CMD_WRITE_DISABLE
- RTC_CMD_WRITE_ENABLE
- RTC_CMD_XPRAM_ARG
- RTC_CMD_XPRAM_READ
- RTC_CMD_XPRAM_WRITE
- RTC_CMR
- RTC_CN
- RTC_CNTR_OK
- RTC_CONF_TEST
- RTC_CONTROL
- RTC_COUNT4
- RTC_COUNT4_DUMMYREAD
- RTC_COUNTER
- RTC_CR
- RTC_CR_CWEN
- RTC_CR_EN
- RTC_CR_MIE
- RTC_CTL
- RTC_CTRL
- RTC_CTRL_4A_BME
- RTC_CTRL_4A_INCR
- RTC_CTRL_4A_KF
- RTC_CTRL_4A_PAB
- RTC_CTRL_4A_RF
- RTC_CTRL_4A_RWK_MASK
- RTC_CTRL_4A_VRT2
- RTC_CTRL_4A_WF
- RTC_CTRL_4B_ABE
- RTC_CTRL_4B_CS
- RTC_CTRL_4B_E32K
- RTC_CTRL_4B_KSE
- RTC_CTRL_4B_PRS
- RTC_CTRL_4B_RCE
- RTC_CTRL_4B_RIE
- RTC_CTRL_4B_RWK_MASK
- RTC_CTRL_4B_WIE
- RTC_CTRL_A
- RTC_CTRL_AL_EN
- RTC_CTRL_A_DV0
- RTC_CTRL_A_DV1
- RTC_CTRL_A_DV2
- RTC_CTRL_A_RS0
- RTC_CTRL_A_RS1
- RTC_CTRL_A_RS2
- RTC_CTRL_A_RS3
- RTC_CTRL_A_RS_MASK
- RTC_CTRL_A_UIP
- RTC_CTRL_B
- RTC_CTRL_B_2412
- RTC_CTRL_B_AIE
- RTC_CTRL_B_DM
- RTC_CTRL_B_DSE
- RTC_CTRL_B_PAU_MASK
- RTC_CTRL_B_PIE
- RTC_CTRL_B_SET
- RTC_CTRL_B_SQWE
- RTC_CTRL_B_UIE
- RTC_CTRL_C
- RTC_CTRL_C_AF
- RTC_CTRL_C_IRQF
- RTC_CTRL_C_PAU_MASK
- RTC_CTRL_C_PF
- RTC_CTRL_C_UF
- RTC_CTRL_D
- RTC_CTRL_D_VRT
- RTC_CTRL_EVERY_DAY
- RTC_CTRL_EVERY_HR
- RTC_CTRL_EVERY_MASK
- RTC_CTRL_EVERY_MIN
- RTC_CTRL_EVERY_SEC
- RTC_CTRL_MODE12
- RTC_CTRL_OFFSET
- RTC_CTRL_RTC_EN
- RTC_CUI
- RTC_CUR_TICK
- RTC_CUR_TM
- RTC_DATA
- RTC_DATA_BITS
- RTC_DATA_LEN
- RTC_DATA_RDY
- RTC_DATE
- RTC_DATE_ALARM
- RTC_DATE_REG_OFFS
- RTC_DAY
- RTC_DAY1
- RTC_DAY10
- RTC_DAYALARM
- RTC_DAYR
- RTC_DAY_ALARM
- RTC_DAY_MASK
- RTC_DAY_OFFSET
- RTC_DAY_OF_MONTH
- RTC_DAY_OF_WEEK
- RTC_DEBNCE_MASK
- RTC_DEC_YEAR
- RTC_DEEP_CTRL
- RTC_DEF_CAPABILITIES
- RTC_DEF_DIVIDER
- RTC_DEF_TRIM
- RTC_DEV_BUSY
- RTC_DEV_MAX
- RTC_DIV
- RTC_DIV_CTL
- RTC_DIV_RESET1
- RTC_DIV_RESET2
- RTC_DM_BINARY
- RTC_DOM
- RTC_DOW
- RTC_DR
- RTC_DST_EN
- RTC_ENABLE
- RTC_ENABLE_BIT
- RTC_EOI
- RTC_EOSC
- RTC_EPOCH_READ
- RTC_EPOCH_READ32
- RTC_EPOCH_SET
- RTC_EPOCH_SET32
- RTC_ESQW
- RTC_EXTCLK_EN
- RTC_EXTCLK_OK
- RTC_EXT_CTRL_4A
- RTC_EXT_CTRL_4B
- RTC_FLAGS
- RTC_FLAGS_AF
- RTC_FLAGS_BLF
- RTC_FLAGS_PF
- RTC_FLG_READ
- RTC_FLG_WRITE_PROTECT
- RTC_FREQ
- RTC_FREQUENCY
- RTC_FREQ_SELECT
- RTC_FR_DATSHIFT
- RTC_FR_EN
- RTC_GSI
- RTC_HOU1
- RTC_HOU10
- RTC_HOUR
- RTC_HOUR1_24HMODE
- RTC_HOURMIN
- RTC_HOURS
- RTC_HOURS_12H_MODE
- RTC_HOURS_ALARM
- RTC_HOURS_OFFS
- RTC_HOUR_ALM_OFFSET
- RTC_HOUR_MASK
- RTC_HOUR_OFFSET
- RTC_HOUR_SHIFT
- RTC_HRS
- RTC_HRS_12_BCD_MASK
- RTC_HRS_12_BIN_MASK
- RTC_HRS_24_BCD_MASK
- RTC_HRS_24_BIN_MASK
- RTC_HRS_ALARM
- RTC_HRS_AMPM_MASK
- RTC_HR_PM
- RTC_HUNDREDTH_SECOND
- RTC_HZ
- RTC_I2C_ADDR
- RTC_IBH_LO
- RTC_ICR
- RTC_IMSC
- RTC_INPUT_CLK_32000HZ
- RTC_INPUT_CLK_32768HZ
- RTC_INPUT_CLK_38400HZ
- RTC_INT
- RTC_INTERRUPTS
- RTC_INTR_FLAGS
- RTC_INTR_OFFSET
- RTC_INTR_STS_OFFSET
- RTC_INTS_AE
- RTC_INTS_AIE
- RTC_INT_ALRM
- RTC_INT_AL_STA
- RTC_INT_DIS
- RTC_INT_EN
- RTC_INT_GPIO
- RTC_INT_MASK
- RTC_INT_SEC
- RTC_INT_STS
- RTC_IOMAPPED
- RTC_IO_EXTENT
- RTC_IO_EXTENT_USED
- RTC_IPSW
- RTC_IRQ
- RTC_IRQ1_CONF
- RTC_IRQ2_CONF
- RTC_IRQF
- RTC_IRQMASK
- RTC_IRQP_READ
- RTC_IRQP_READ32
- RTC_IRQP_SET
- RTC_IRQP_SET32
- RTC_IRQ_AL_EN
- RTC_IRQ_EN
- RTC_IRQ_EN_AL
- RTC_IRQ_EN_LP
- RTC_IRQ_EN_ONESHOT
- RTC_IRQ_EN_ONESHOT_AL
- RTC_IRQ_FREQ_1HZ
- RTC_IRQ_FREQ_EN
- RTC_IRQ_MASK
- RTC_IRQ_NUM
- RTC_IRQ_STA
- RTC_IRQ_STA_AL
- RTC_IRQ_STA_LP
- RTC_IS_OPEN
- RTC_KEY_MAGIC
- RTC_LATCH
- RTC_LR
- RTC_M41T81
- RTC_MAX_FREQ
- RTC_MAX_NUM_TIME_REGS
- RTC_MAX_USER_FREQ
- RTC_MDAY
- RTC_MDAY_ALARM
- RTC_MDAY_ALARM_MASK
- RTC_MDAY_BCD_MASK
- RTC_MDAY_BIN_MASK
- RTC_MDAY_MASK
- RTC_MDAY_OFFS
- RTC_MDAY_SHIFT
- RTC_MFL0
- RTC_MFL1
- RTC_MILLISECONDS
- RTC_MIN
- RTC_MIN1
- RTC_MIN10
- RTC_MINOR
- RTC_MINS
- RTC_MINS_ALARM
- RTC_MINS_BCD_MASK
- RTC_MINS_BIN_MASK
- RTC_MINUTES
- RTC_MINUTES_ALARM
- RTC_MINUTES_OFFS
- RTC_MIN_ALM_OFFSET
- RTC_MIN_MASK
- RTC_MIN_OFFSET
- RTC_MIN_SHIFT
- RTC_MIN_YEAR
- RTC_MIN_YEAR_OFFSET
- RTC_MIS
- RTC_MODEL_DS1685
- RTC_MODEL_DS1689
- RTC_MODEL_DS17285
- RTC_MODEL_DS17485
- RTC_MODEL_DS17885
- RTC_MON
- RTC_MON1
- RTC_MON10
- RTC_MONTH
- RTC_MONTH_BCD_MASK
- RTC_MONTH_BIN_MASK
- RTC_MONTH_OFFS
- RTC_MON_MASK
- RTC_MON_SHIFT
- RTC_MR
- RTC_NAME
- RTC_NOMINAL_TIMING
- RTC_NONE
- RTC_NR_TIME
- RTC_NUM_INTS
- RTC_NUM_YEARS
- RTC_OFFSET
- RTC_OFFSET_COUNT
- RTC_OFFSET_DOM
- RTC_OFFSET_DOW
- RTC_OFFSET_HOUR
- RTC_OFFSET_MIN
- RTC_OFFSET_MTH
- RTC_OFFSET_SEC
- RTC_OFFSET_YEAR
- RTC_OSC_DISABLE
- RTC_OSC_EN
- RTC_OSC_ENABLE
- RTC_PDN2
- RTC_PDN2_PWRON_ALARM
- RTC_PF
- RTC_PHYS_BASE
- RTC_PIE
- RTC_PIE_OFF
- RTC_PIE_ON
- RTC_PLL_GET
- RTC_PLL_SET
- RTC_PLL_SETTLE_DELAY
- RTC_PMIC_EXT_WAKEUP_EN
- RTC_PMIC_EXT_WAKEUP_POL
- RTC_PMIC_EXT_WAKEUP_STS
- RTC_PMIC_POWER_EN
- RTC_PMIC_REG
- RTC_PORT
- RTC_PRI
- RTC_PRIMARY_BASE
- RTC_PRIORITY
- RTC_PROT1_MAGIC
- RTC_PROT2_MAGIC
- RTC_PROT3_MAGIC
- RTC_PROT4_MAGIC
- RTC_PU_LVL
- RTC_PWRCHK1_MAGIC
- RTC_PWRCHK2_MAGIC
- RTC_RATE_SELECT
- RTC_RBUDR_MASK
- RTC_RBUDR_SHIFT
- RTC_RCNR
- RTC_RC_STOP
- RTC_RD_TIME
- RTC_READ
- RTC_READREG
- RTC_READ_REQUEST
- RTC_REC_OFFSET
- RTC_REF_CLCK_1MHZ
- RTC_REF_CLCK_32KHZ
- RTC_REF_CLCK_4MHZ
- RTC_REG
- RTC_REG4
- RTC_REG4_STATIC_VALUE
- RTC_REGMEM_0
- RTC_REGMEM_1
- RTC_REGMEM_2
- RTC_REGMEM_3
- RTC_REG_A
- RTC_REG_B
- RTC_REG_BOOT_MAGIC
- RTC_REG_C
- RTC_REG_D
- RTC_REG_DAY1
- RTC_REG_DAY2
- RTC_REG_HOUR1
- RTC_REG_HOUR2
- RTC_REG_MIN1
- RTC_REG_MIN2
- RTC_REG_MON1
- RTC_REG_MON2
- RTC_REG_SEC1
- RTC_REG_SEC2
- RTC_REG_SECONDS_0
- RTC_REG_SECONDS_1
- RTC_REG_SECONDS_2
- RTC_REG_SECONDS_3
- RTC_REG_SIZE
- RTC_REG_WDAY
- RTC_REG_WRITE_PROTECT
- RTC_REG_XPRAM
- RTC_REG_YEAR1
- RTC_REG_YEAR2
- RTC_RIS
- RTC_RSTAT
- RTC_RTAR
- RTC_RTCCTL
- RTC_RTCIENR
- RTC_RTCISR
- RTC_RTSR
- RTC_RTSR_AL
- RTC_RTSR_ALE
- RTC_RTSR_HZ
- RTC_RTSR_HZE
- RTC_RTTR
- RTC_SAM0_BIT
- RTC_SAM1_BIT
- RTC_SAM2_BIT
- RTC_SAM3_BIT
- RTC_SAM4_BIT
- RTC_SAM5_BIT
- RTC_SAM6_BIT
- RTC_SAM7_BIT
- RTC_SCRATCH_MAGIC_REG
- RTC_SCRATCH_RESUME_REG
- RTC_SEC
- RTC_SEC1
- RTC_SEC10
- RTC_SECOND
- RTC_SECONDS
- RTC_SECONDS_ALARM
- RTC_SECONDS_MASK
- RTC_SECONDS_OFFS
- RTC_SECONDS_REG
- RTC_SECS
- RTC_SECS_ALARM
- RTC_SECS_BCD_MASK
- RTC_SECS_BIN_MASK
- RTC_SEC_ADJ
- RTC_SEC_ALM_OFFSET
- RTC_SEC_MASK
- RTC_SEC_OFFSET
- RTC_SEC_SHIFT
- RTC_SET
- RTC_SETREG
- RTC_SETTING
- RTC_SET_TIME
- RTC_SET_TM_RD
- RTC_SET_TM_WR
- RTC_SHADOW_SECONDS
- RTC_SHIFT
- RTC_SIZE
- RTC_SOC_3MSB
- RTC_SOC_5LSB
- RTC_SOC_BASE_ADDRESS
- RTC_SQWE
- RTC_SQW_0HZ
- RTC_SQW_1024HZ
- RTC_SQW_128HZ
- RTC_SQW_16HZ
- RTC_SQW_2048HZ
- RTC_SQW_256HZ
- RTC_SQW_2HZ
- RTC_SQW_32768HZ
- RTC_SQW_32HZ
- RTC_SQW_4096HZ
- RTC_SQW_4HZ
- RTC_SQW_512HZ
- RTC_SQW_64HZ
- RTC_SQW_8192HZ
- RTC_SQW_8HZ
- RTC_STAT
- RTC_STATE_ADDRESS
- RTC_STATE_V_GET
- RTC_STATE_V_LSB
- RTC_STATE_V_MASK
- RTC_STATE_V_ON
- RTC_STATUS
- RTC_STATUS_ALARM1
- RTC_STATUS_ALARM2
- RTC_STATUS_DATA
- RTC_STATUS_MASK
- RTC_STAT_BIT
- RTC_STAT_MASK
- RTC_STAT_RDY
- RTC_STOP
- RTC_STPWCH
- RTC_SW_BIT
- RTC_SW_VALUE
- RTC_SYNC_STATUS_OFFSET
- RTC_SYNC_STATUS_PLL_CHANGING_LSB
- RTC_SYNC_STATUS_PLL_CHANGING_MASK
- RTC_T
- RTC_TCON_MASK
- RTC_TCON_SHIFT
- RTC_TCR
- RTC_TCR_EN
- RTC_TC_SEC
- RTC_TDF
- RTC_TDM
- RTC_TDR
- RTC_TE
- RTC_TEST1
- RTC_TEST2
- RTC_TEST3
- RTC_TICK_MASK
- RTC_TIE
- RTC_TIME
- RTC_TIMER_CLOCK_FREQ
- RTC_TIMER_COUNT
- RTC_TIMER_CYCLES
- RTC_TIMER_FREQ
- RTC_TIMER_ON
- RTC_TIMESTAMP_BEGIN_1900
- RTC_TIMESTAMP_BEGIN_2000
- RTC_TIMESTAMP_END_2063
- RTC_TIMESTAMP_END_2099
- RTC_TIMESTAMP_END_9999
- RTC_TIME_REG_OFFS
- RTC_TLR
- RTC_UDR_MASK
- RTC_UDR_SHIFT
- RTC_UF
- RTC_UIE
- RTC_UIE_OFF
- RTC_UIE_ON
- RTC_UIP
- RTC_UNLOCK
- RTC_UNUSED
- RTC_UPDATE_EVERY
- RTC_VALID
- RTC_VER
- RTC_VERSION
- RTC_VL_CLR
- RTC_VL_READ
- RTC_VRT
- RTC_WAF
- RTC_WAM
- RTC_WATCHDOG
- RTC_WDAY
- RTC_WDAY_MASK
- RTC_WDAY_OFFS
- RTC_WDAY_SHIFT
- RTC_WEE1
- RTC_WEEKDAY
- RTC_WHSEC
- RTC_WIE_OFF
- RTC_WIE_ON
- RTC_WKALM_RD
- RTC_WKALM_SET
- RTC_WMAC_BASE_ADDRESS
- RTC_WPR_1ST_KEY
- RTC_WPR_2ND_KEY
- RTC_WPR_WRONG_KEY
- RTC_WRITE
- RTC_WRITEREG
- RTC_WRITE_REQUEST
- RTC_WRTGR
- RTC_WSEC
- RTC_XICOR
- RTC_YDR
- RTC_YEA1
- RTC_YEA10
- RTC_YEA100
- RTC_YEA1000
- RTC_YEAR
- RTC_YEAR1
- RTC_YEAR2
- RTC_YEAR_BCD_MASK
- RTC_YEAR_BIN_MASK
- RTC_YEAR_OFFS
- RTC_YEAR_OFFSET
- RTC_YLR
- RTC_YMR
- RTCmd_LoadRcc
- RTCmd_LoadRccAndTcc
- RTCmd_LoadTC0
- RTCmd_LoadTC0AndTC1
- RTCmd_LoadTC1
- RTCmd_LoadTcc
- RTCmd_Null
- RTCmd_PurgeRxAndTxFifo
- RTCmd_PurgeRxFifo
- RTCmd_PurgeTxFifo
- RTCmd_ResetHighestIus
- RTCmd_SelectBigEndian
- RTCmd_SelectLittleEndian
- RTCmd_SerialDataLSBFirst
- RTCmd_SerialDataMSBFirst
- RTCmd_TriggerChannelLoadDma
- RTCmd_TriggerRxAndTxDma
- RTCmd_TriggerRxDma
- RTCmd_TriggerTxDma
- RTD119X_TCWCR
- RTD119X_TCWCR_WDEN_DISABLED
- RTD119X_TCWCR_WDEN_ENABLED
- RTD119X_TCWCR_WDEN_MASK
- RTD119X_TCWOV
- RTD119X_TCWTR
- RTD119X_TCWTR_WDCLR
- RTDID
- RTD_CLOCK_BASE
- RTD_CLOCK_RATE
- RTD_MAX_CHANLIST
- RTD_MAX_SPEED
- RTD_MAX_SPEED_1
- RTD_MIN_SPEED
- RTD_MIN_SPEED_1
- RTD_RTCACR
- RTD_RTCACR_RTCPWR
- RTD_RTCCR
- RTD_RTCCR_RTCRST
- RTD_RTCDATE1
- RTD_RTCDATE1_RTCDATE1_MASK
- RTD_RTCDATE2
- RTD_RTCDATE2_RTCDATE2_MASK
- RTD_RTCEN
- RTD_RTCEN_RTCEN_MASK
- RTD_RTCHR
- RTD_RTCHR_RTCHR_MASK
- RTD_RTCMIN
- RTD_RTCMIN_RTCMIN_MASK
- RTD_RTCSEC
- RTD_RTCSEC_RTCSEC_MASK
- RTEMPHIL
- RTERM_SELECT
- RTERM_SELECT_MASK
- RTEXT_FILTER_BRVLAN
- RTEXT_FILTER_BRVLAN_COMPRESSED
- RTEXT_FILTER_SKIP_STATS
- RTEXT_FILTER_VF
- RTFRQMAX_DISABLE
- RTF_ADDRCONF
- RTF_ALLONLINK
- RTF_ANYCAST
- RTF_CACHE
- RTF_CACHE_GATEWAY
- RTF_DEFAULT
- RTF_DYNAMIC
- RTF_EXPIRES
- RTF_FLOW
- RTF_GATEWAY
- RTF_HOST
- RTF_IRTT
- RTF_LOCAL
- RTF_MAJOR
- RTF_MODIFIED
- RTF_MSS
- RTF_MTU
- RTF_NONEXTHOP
- RTF_PCPU
- RTF_POLICY
- RTF_PREF
- RTF_PREFIX_RT
- RTF_PREF_MASK
- RTF_RA_ROUTER
- RTF_REINSTATE
- RTF_REJECT
- RTF_ROUTEINFO
- RTF_UP
- RTF_WINDOW
- RTGTBL_OFFSET
- RTH_ALG_CRC32C
- RTH_ALG_JENKINS
- RTH_ALG_MS_RSS
- RTH_BUCKET_SIZE
- RTH_STEERING
- RTI
- RTI800_9513A_CNTRL
- RTI800_9513A_DATA
- RTI800_9513A_STATUS
- RTI800_ADCHI
- RTI800_ADCLO
- RTI800_CLRFLAGS
- RTI800_CONVERT
- RTI800_CSR
- RTI800_CSR_BUSY
- RTI800_CSR_DMA_ENAB
- RTI800_CSR_DONE
- RTI800_CSR_INTR_EC
- RTI800_CSR_INTR_OVRN
- RTI800_CSR_INTR_TC
- RTI800_CSR_OVERRUN
- RTI800_CSR_TCR
- RTI800_DAC0HI
- RTI800_DAC0LO
- RTI800_DAC1HI
- RTI800_DAC1LO
- RTI800_DI
- RTI800_DO
- RTI800_MUXGAIN
- RTI802_DATAHIGH
- RTI802_DATALOW
- RTI802_SELECT
- RTIMCNT
- RTIT_ADDR_RANGE
- RTIT_CTL_ADDR0
- RTIT_CTL_ADDR0_OFFSET
- RTIT_CTL_ADDR1
- RTIT_CTL_ADDR1_OFFSET
- RTIT_CTL_ADDR2
- RTIT_CTL_ADDR2_OFFSET
- RTIT_CTL_ADDR3
- RTIT_CTL_ADDR3_OFFSET
- RTIT_CTL_BRANCH_EN
- RTIT_CTL_CR3EN
- RTIT_CTL_CYCLEACC
- RTIT_CTL_CYC_PSB
- RTIT_CTL_CYC_THRESH
- RTIT_CTL_CYC_THRESH_OFFSET
- RTIT_CTL_DISRETC
- RTIT_CTL_FABRIC_EN
- RTIT_CTL_FUP_ON_PTW
- RTIT_CTL_MTC
- RTIT_CTL_MTC_EN
- RTIT_CTL_MTC_RANGE
- RTIT_CTL_MTC_RANGE_OFFSET
- RTIT_CTL_OS
- RTIT_CTL_PASSTHROUGH
- RTIT_CTL_PSB_FREQ
- RTIT_CTL_PSB_FREQ_OFFSET
- RTIT_CTL_PTW
- RTIT_CTL_PTW_EN
- RTIT_CTL_PWR_EVT_EN
- RTIT_CTL_TOPA
- RTIT_CTL_TRACEEN
- RTIT_CTL_TSC_EN
- RTIT_CTL_USR
- RTIT_STATUS_BUFFOVF
- RTIT_STATUS_BYTECNT
- RTIT_STATUS_BYTECNT_OFFSET
- RTIT_STATUS_CONTEXTEN
- RTIT_STATUS_ERROR
- RTIT_STATUS_FILTEREN
- RTIT_STATUS_STOPPED
- RTIT_STATUS_TRIGGEREN
- RTI_CMD_MEM_OFFSET
- RTI_CMD_MEM_STROBE
- RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED
- RTI_CMD_MEM_STROBE_NEW_CMD
- RTI_CMD_MEM_WE
- RTI_DATA1_MEM_RX_TIMER_AC_EN
- RTI_DATA1_MEM_RX_TIMER_CI_EN
- RTI_DATA1_MEM_RX_TIMER_VAL
- RTI_DATA1_MEM_RX_URNG_A
- RTI_DATA1_MEM_RX_URNG_B
- RTI_DATA1_MEM_RX_URNG_C
- RTI_DATA2_MEM_RX_UFC_A
- RTI_DATA2_MEM_RX_UFC_B
- RTI_DATA2_MEM_RX_UFC_C
- RTI_DATA2_MEM_RX_UFC_D
- RTI_ECC_DB_ERR
- RTI_ECC_SG_ERR
- RTI_RX_UFC_A
- RTI_RX_UFC_B
- RTI_RX_UFC_C
- RTI_RX_UFC_D
- RTI_RX_URANGE_A
- RTI_RX_URANGE_B
- RTI_RX_URANGE_C
- RTI_SM_ERR_ALARM
- RTI_T1A_RX_UFC_B
- RTI_T1A_RX_UFC_C
- RTI_T1A_RX_UFC_D
- RTI_T1A_RX_URANGE_A
- RTI_T1A_RX_URANGE_B
- RTI_T1A_RX_URANGE_C
- RTK_BEQ_TX_DESC_NUM
- RTK_DEFAULT_TX_DESC_NUM
- RTK_DL_EDCA
- RTK_MAX_RX_DESC_NUM
- RTK_MAX_RX_QUEUE_NUM
- RTK_MAX_TX_QUEUE_NUM
- RTK_PCI_CTRL
- RTK_PCI_DEVICE
- RTK_PCI_HIMR0
- RTK_PCI_HIMR1
- RTK_PCI_HIMR2
- RTK_PCI_HIMR3
- RTK_PCI_HISR0
- RTK_PCI_HISR1
- RTK_PCI_HISR2
- RTK_PCI_HISR3
- RTK_PCI_RXBD_DESA_MPDUQ
- RTK_PCI_RXBD_IDX_MPDUQ
- RTK_PCI_RXBD_NUM_MPDUQ
- RTK_PCI_RX_BUF_SIZE
- RTK_PCI_TXBD_BCN_WORK
- RTK_PCI_TXBD_DESA_BCNQ
- RTK_PCI_TXBD_DESA_BEQ
- RTK_PCI_TXBD_DESA_BKQ
- RTK_PCI_TXBD_DESA_H2CQ
- RTK_PCI_TXBD_DESA_HI0Q
- RTK_PCI_TXBD_DESA_MGMTQ
- RTK_PCI_TXBD_DESA_VIQ
- RTK_PCI_TXBD_DESA_VOQ
- RTK_PCI_TXBD_H2CQ_CSR
- RTK_PCI_TXBD_IDX_BEQ
- RTK_PCI_TXBD_IDX_BKQ
- RTK_PCI_TXBD_IDX_H2CQ
- RTK_PCI_TXBD_IDX_HI0Q
- RTK_PCI_TXBD_IDX_MGMTQ
- RTK_PCI_TXBD_IDX_VIQ
- RTK_PCI_TXBD_IDX_VOQ
- RTK_PCI_TXBD_NUM_BEQ
- RTK_PCI_TXBD_NUM_BKQ
- RTK_PCI_TXBD_NUM_H2CQ
- RTK_PCI_TXBD_NUM_HI0Q
- RTK_PCI_TXBD_NUM_MGMTQ
- RTK_PCI_TXBD_NUM_VIQ
- RTK_PCI_TXBD_NUM_VOQ
- RTK_PCI_TXBD_OWN_OFFSET
- RTK_PCI_TXBD_RWPTR_CLR
- RTK_TX_MAX_AGG_NUM_MASK
- RTK_UL_EDCA
- RTL
- RTL2830_H
- RTL2830_PRIV_H
- RTL2832_H
- RTL2832_PRIV_H
- RTL2832_SDR_H
- RTL2832_SDR_TUNER_E4000
- RTL2832_SDR_TUNER_FC0012
- RTL2832_SDR_TUNER_FC0013
- RTL2832_SDR_TUNER_FC2580
- RTL2832_SDR_TUNER_R820T
- RTL2832_SDR_TUNER_R828D
- RTL2832_SDR_TUNER_TUA9001
- RTL2832_TUNER_E4000
- RTL2832_TUNER_FC0012
- RTL2832_TUNER_FC0013
- RTL2832_TUNER_FC2580
- RTL2832_TUNER_R820T
- RTL2832_TUNER_R828D
- RTL2832_TUNER_SI2157
- RTL2832_TUNER_TUA9001
- RTL28XXU_H
- RTL8129
- RTL8129_CAPS
- RTL8139
- RTL8139B_IO_SIZE
- RTL8139_1_IRQ
- RTL8139_2_IRQ
- RTL8139_CAPS
- RTL8139_DEBUG
- RTL8139_DEF_MSG_ENABLE
- RTL8139_DRIVER_NAME
- RTL8139_NDEBUG
- RTL8139_registers
- RTL8150_HW_CRC
- RTL8150_MTU
- RTL8150_REQT_READ
- RTL8150_REQT_WRITE
- RTL8150_REQ_GET_REGS
- RTL8150_REQ_SET_REGS
- RTL8150_TX_TIMEOUT
- RTL8150_UNPLUG
- RTL8152_LINK_CHG
- RTL8152_MAX_RX
- RTL8152_MAX_TX
- RTL8152_NAPI_WEIGHT
- RTL8152_REQT_READ
- RTL8152_REQT_WRITE
- RTL8152_REQ_GET_REGS
- RTL8152_REQ_SET_REGS
- RTL8152_RMS
- RTL8152_RXFG_HEADSZ
- RTL8152_RX_MAX_PENDING
- RTL8152_SET_RX_MODE
- RTL8152_TX_TIMEOUT
- RTL8152_UNPLUG
- RTL8153_MAX_MTU
- RTL8153_MAX_PACKET
- RTL8153_RMS
- RTL8169_PM_OPS
- RTL8180_GRF5101_H
- RTL8180_H
- RTL8180_MAX2820_H
- RTL8180_NR_TX_QUEUES
- RTL8180_RTL8225_H
- RTL8180_SA2400_H
- RTL8187B_RTL8225_ANAPARAM2_OFF
- RTL8187B_RTL8225_ANAPARAM2_ON
- RTL8187B_RTL8225_ANAPARAM3_OFF
- RTL8187B_RTL8225_ANAPARAM3_ON
- RTL8187B_RTL8225_ANAPARAM_OFF
- RTL8187B_RTL8225_ANAPARAM_ON
- RTL8187BvB
- RTL8187BvD
- RTL8187BvE
- RTL8187SE_NR_TX_QUEUES
- RTL8187SE_POWER_OFF
- RTL8187SE_POWER_ON
- RTL8187SE_POWER_SLEEP
- RTL8187SE_RTL8225_H
- RTL8187_EEPROM_MAC_ADDR
- RTL8187_EEPROM_SELECT_GPIO
- RTL8187_EEPROM_TXPWR_BASE
- RTL8187_EEPROM_TXPWR_CHAN_1
- RTL8187_EEPROM_TXPWR_CHAN_4
- RTL8187_EEPROM_TXPWR_CHAN_6
- RTL8187_H
- RTL8187_LED_H
- RTL8187_LED_MAX_NAME_LEN
- RTL8187_MAX_RX
- RTL8187_REQT_READ
- RTL8187_REQT_WRITE
- RTL8187_REQ_GET_REG
- RTL8187_REQ_GET_REGS
- RTL8187_REQ_SET_REG
- RTL8187_REQ_SET_REGS
- RTL8187_RFKILL_H
- RTL8187_RTL8225_ANAPARAM2_OFF
- RTL8187_RTL8225_ANAPARAM2_ON
- RTL8187_RTL8225_ANAPARAM_OFF
- RTL8187_RTL8225_ANAPARAM_ON
- RTL8187_RTL8225_H
- RTL8188C
- RTL8188C_8192C
- RTL8188E
- RTL8188EEAGCTAB_1TARRAYLEN
- RTL8188EEMAC_1T_ARRAYLEN
- RTL8188EEPHY_REG_1TARRAYLEN
- RTL8188EEPHY_REG_ARRAY_PGLEN
- RTL8188EE_NIC_DISABLE_FLOW
- RTL8188EE_NIC_ENABLE_FLOW
- RTL8188EE_NIC_LPS_ENTER_FLOW
- RTL8188EE_NIC_LPS_LEAVE_FLOW
- RTL8188EE_NIC_PDN_FLOW
- RTL8188EE_NIC_PWR_ON_FLOW
- RTL8188EE_NIC_RESUME_FLOW
- RTL8188EE_NIC_RF_OFF_FLOW
- RTL8188EE_NIC_SUSPEND_FLOW
- RTL8188EE_RADIOA_1TARRAYLEN
- RTL8188EE_TRANS_ACT_TO_CARDEMU
- RTL8188EE_TRANS_ACT_TO_CARDEMU_STEPS
- RTL8188EE_TRANS_ACT_TO_LPS
- RTL8188EE_TRANS_ACT_TO_LPS_STEPS
- RTL8188EE_TRANS_CARDDIS_TO_CARDEMU
- RTL8188EE_TRANS_CARDEMU_TO_ACT
- RTL8188EE_TRANS_CARDEMU_TO_ACT_STEPS
- RTL8188EE_TRANS_CARDEMU_TO_CARDDIS
- RTL8188EE_TRANS_CARDEMU_TO_PDN
- RTL8188EE_TRANS_CARDEMU_TO_PDN_STEPS
- RTL8188EE_TRANS_CARDEMU_TO_SUS
- RTL8188EE_TRANS_CARDEMU_TO_SUS_STEPS
- RTL8188EE_TRANS_END
- RTL8188EE_TRANS_END_STEPS
- RTL8188EE_TRANS_LPS_TO_ACT
- RTL8188EE_TRANS_LPS_TO_ACT_STEPS
- RTL8188EE_TRANS_PDN_TO_CARDEMU
- RTL8188EE_TRANS_PDN_TO_CARDEMU_STEPS
- RTL8188EE_TRANS_SUS_TO_CARDEMU
- RTL8188EE_TRANS_SUS_TO_CARDEMU_STEPS
- RTL8188E_AGC_TAB
- RTL8188E_EEPROM_ID
- RTL8188E_FW_UMC_IMG
- RTL8188E_H2C_CMD_ID
- RTL8188E_PHY_MACREG
- RTL8188E_PHY_RADIO_A
- RTL8188E_PHY_RADIO_B
- RTL8188E_PHY_REG
- RTL8188E_PHY_REG_MP
- RTL8188E_PHY_REG_PG
- RTL8188E_TRANS_ACT_TO_CARDEMU
- RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS
- RTL8188E_TRANS_ACT_TO_LPS
- RTL8188E_TRANS_ACT_TO_LPS_STEPS
- RTL8188E_TRANS_CARDDIS_TO_CARDEMU
- RTL8188E_TRANS_CARDEMU_TO_ACT
- RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS
- RTL8188E_TRANS_CARDEMU_TO_CARDDIS
- RTL8188E_TRANS_CARDEMU_TO_PDN
- RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS
- RTL8188E_TRANS_CARDEMU_TO_SUS
- RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS
- RTL8188E_TRANS_END
- RTL8188E_TRANS_END_STEPS
- RTL8188E_TRANS_LPS_TO_ACT
- RTL8188E_TRANS_LPS_TO_ACT_STEPS
- RTL8188E_TRANS_PDN_TO_CARDEMU
- RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS
- RTL8188E_TRANS_SUS_TO_CARDEMU
- RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS
- RTL8188F
- RTL8188R
- RTL8188_RX_HAL_IS_CCK_RATE
- RTL818X_CHIP_FAMILY_RTL8180
- RTL818X_CHIP_FAMILY_RTL8185
- RTL818X_CHIP_FAMILY_RTL8187SE
- RTL818X_CMD_RESET
- RTL818X_CMD_RX_ENABLE
- RTL818X_CMD_TX_ENABLE
- RTL818X_CONFIG2_ANTENNA_DIV
- RTL818X_CONFIG3_ANAPARAM_WRITE
- RTL818X_CONFIG3_GNT_SELECT
- RTL818X_CONFIG4_POWEROFF
- RTL818X_CONFIG4_VCOOFF
- RTL818X_CW_CONF_PERPACKET_CW
- RTL818X_CW_CONF_PERPACKET_RETRY
- RTL818X_EEPROM_CMD_CK
- RTL818X_EEPROM_CMD_CONFIG
- RTL818X_EEPROM_CMD_CS
- RTL818X_EEPROM_CMD_LOAD
- RTL818X_EEPROM_CMD_NORMAL
- RTL818X_EEPROM_CMD_PROGRAM
- RTL818X_EEPROM_CMD_READ
- RTL818X_EEPROM_CMD_WRITE
- RTL818X_H
- RTL818X_INT_ATIM
- RTL818X_INT_BEACON
- RTL818X_INT_RX_DU
- RTL818X_INT_RX_ERR
- RTL818X_INT_RX_FO
- RTL818X_INT_RX_OK
- RTL818X_INT_SE_ATIM_TO
- RTL818X_INT_SE_BK_DMA
- RTL818X_INT_SE_BK_TO
- RTL818X_INT_SE_RQ0SOR
- RTL818X_INT_SE_RX_DU
- RTL818X_INT_SE_RX_ERR
- RTL818X_INT_SE_RX_FIFO
- RTL818X_INT_SE_RX_OK
- RTL818X_INT_SE_TIMER1
- RTL818X_INT_SE_TIMER2
- RTL818X_INT_SE_TIMER3
- RTL818X_INT_SE_TMGD_OK
- RTL818X_INT_SE_TXBED_ERR
- RTL818X_INT_SE_TXBED_OK
- RTL818X_INT_SE_TXBE_ERR
- RTL818X_INT_SE_TXBE_OK
- RTL818X_INT_SE_TXB_ERR
- RTL818X_INT_SE_TXB_OK
- RTL818X_INT_SE_TXH_ERR
- RTL818X_INT_SE_TXH_OK
- RTL818X_INT_SE_TXL_ERR
- RTL818X_INT_SE_TXL_OK
- RTL818X_INT_SE_TXN_ERR
- RTL818X_INT_SE_TXN_OK
- RTL818X_INT_SE_TX_FIFO
- RTL818X_INT_SE_WAKEUP
- RTL818X_INT_TIME_OUT
- RTL818X_INT_TXB_ERR
- RTL818X_INT_TXB_OK
- RTL818X_INT_TXH_ERR
- RTL818X_INT_TXH_OK
- RTL818X_INT_TXL_ERR
- RTL818X_INT_TXL_OK
- RTL818X_INT_TXN_ERR
- RTL818X_INT_TXN_OK
- RTL818X_INT_TX_FO
- RTL818X_MSR_ADHOC
- RTL818X_MSR_ENEDCA
- RTL818X_MSR_INFRA
- RTL818X_MSR_MASTER
- RTL818X_MSR_NO_LINK
- RTL818X_NR_TX_QUEUES
- RTL818X_R8187B_B
- RTL818X_R8187B_D
- RTL818X_R8187B_E
- RTL818X_RATE_FALLBACK_ENABLE
- RTL818X_RX_CONF_ADDR3
- RTL818X_RX_CONF_BROADCAST
- RTL818X_RX_CONF_BSSID
- RTL818X_RX_CONF_CSDM1
- RTL818X_RX_CONF_CSDM2
- RTL818X_RX_CONF_CTRL
- RTL818X_RX_CONF_DATA
- RTL818X_RX_CONF_FCS
- RTL818X_RX_CONF_MGMT
- RTL818X_RX_CONF_MONITOR
- RTL818X_RX_CONF_MULTICAST
- RTL818X_RX_CONF_NICMAC
- RTL818X_RX_CONF_ONLYERLPKT
- RTL818X_RX_CONF_PM
- RTL818X_RX_CONF_RX_AUTORESETPHY
- RTL818X_RX_DESC_FLAG_BCAST
- RTL818X_RX_DESC_FLAG_CRC32_ERR
- RTL818X_RX_DESC_FLAG_DMA_FAIL
- RTL818X_RX_DESC_FLAG_EOR
- RTL818X_RX_DESC_FLAG_FOF
- RTL818X_RX_DESC_FLAG_FS
- RTL818X_RX_DESC_FLAG_ICV_ERR
- RTL818X_RX_DESC_FLAG_LS
- RTL818X_RX_DESC_FLAG_MCAST
- RTL818X_RX_DESC_FLAG_OWN
- RTL818X_RX_DESC_FLAG_PAM
- RTL818X_RX_DESC_FLAG_PM
- RTL818X_RX_DESC_FLAG_QOS
- RTL818X_RX_DESC_FLAG_RX_ERR
- RTL818X_RX_DESC_FLAG_SPLCP
- RTL818X_RX_DESC_FLAG_TRSW
- RTL818X_TX_AGC_CTL_FEEDBACK_ANT
- RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL
- RTL818X_TX_AGC_CTL_PERPACKET_GAIN
- RTL818X_TX_CONF_CW_MIN
- RTL818X_TX_CONF_DISCW
- RTL818X_TX_CONF_DISREQQSIZE
- RTL818X_TX_CONF_HWVER_MASK
- RTL818X_TX_CONF_HW_SEQNUM
- RTL818X_TX_CONF_LOOPBACK_CONT
- RTL818X_TX_CONF_LOOPBACK_MAC
- RTL818X_TX_CONF_NO_ICV
- RTL818X_TX_CONF_PROBE_DTS
- RTL818X_TX_CONF_R8180_ABCD
- RTL818X_TX_CONF_R8180_F
- RTL818X_TX_CONF_R8185_ABC
- RTL818X_TX_CONF_R8185_D
- RTL818X_TX_CONF_R8187vD
- RTL818X_TX_CONF_R8187vD_B
- RTL818X_TX_CONF_RTL8187SE
- RTL818X_TX_CONF_SAT_HWPLCP
- RTL818X_TX_DESC_FLAG_CTS
- RTL818X_TX_DESC_FLAG_DMA
- RTL818X_TX_DESC_FLAG_FS
- RTL818X_TX_DESC_FLAG_LS
- RTL818X_TX_DESC_FLAG_MOREFRAG
- RTL818X_TX_DESC_FLAG_NO_ENC
- RTL818X_TX_DESC_FLAG_OWN
- RTL818X_TX_DESC_FLAG_RTS
- RTL818X_TX_DESC_FLAG_RX_UNDER
- RTL818X_TX_DESC_FLAG_SPLCP
- RTL818X_TX_DESC_FLAG_TX_OK
- RTL818x_TPPOLL_STOP_BE
- RTL818x_TPPOLL_STOP_BK
- RTL818x_TPPOLL_STOP_BQ
- RTL818x_TPPOLL_STOP_HI
- RTL818x_TPPOLL_STOP_MG
- RTL818x_TPPOLL_STOP_VI
- RTL818x_TPPOLL_STOP_VO
- RTL8190_CPU_START_OFFSET
- RTL8190_EEPROM_ID
- RTL8190_MAX_FIRMWARE_CODE_SIZE
- RTL8190_MAX_RAW_FIRMWARE_CODE_SIZE
- RTL8191C
- RTL8191E
- RTL8191S
- RTL8192C
- RTL8192CUAGCTAB_1TARRAYLENGTH
- RTL8192CUAGCTAB_1T_HPARRAYLENGTH
- RTL8192CUAGCTAB_2TARRAYLENGTH
- RTL8192CUMAC_2T_ARRAYLENGTH
- RTL8192CUPHY_REG_1TARRAY_LENGTH
- RTL8192CUPHY_REG_1T_HPARRAYLENGTH
- RTL8192CUPHY_REG_2TARRAY_LENGTH
- RTL8192CUPHY_REG_ARRAY_PGLENGTH
- RTL8192CUPHY_REG_ARRAY_PG_HPLENGTH
- RTL8192CURADIOA_1TARRAYLENGTH
- RTL8192CURADIOA_1T_HPARRAYLENGTH
- RTL8192CURADIOA_2TARRAYLENGTH
- RTL8192CURADIOB_1TARRAYLENGTH
- RTL8192CURADIOB_2TARRAYLENGTH
- RTL8192D
- RTL8192E
- RTL8192EE_AGC_TAB_ARRAY_LEN
- RTL8192EE_MAC_ARRAY_LEN
- RTL8192EE_PHY_REG_ARRAY_LEN
- RTL8192EE_PHY_REG_ARRAY_PG_LEN
- RTL8192EE_RADIOA_ARRAY_LEN
- RTL8192EE_RADIOB_ARRAY_LEN
- RTL8192EE_SEG_NUM
- RTL8192E_BOOT_IMG_FW
- RTL8192E_DATA_IMG_FW
- RTL8192E_EEPROM_ID
- RTL8192E_MAIN_IMG_FW
- RTL8192E_NIC_DISABLE_FLOW
- RTL8192E_NIC_ENABLE_FLOW
- RTL8192E_NIC_LPS_ENTER_FLOW
- RTL8192E_NIC_LPS_LEAVE_FLOW
- RTL8192E_NIC_PDN_FLOW
- RTL8192E_NIC_PWR_ON_FLOW
- RTL8192E_NIC_RESUME_FLOW
- RTL8192E_NIC_RF_OFF_FLOW
- RTL8192E_NIC_SUSPEND_FLOW
- RTL8192E_TRANS_ACT_TO_CARDEMU
- RTL8192E_TRANS_ACT_TO_CARDEMU_STEPS
- RTL8192E_TRANS_ACT_TO_LPS
- RTL8192E_TRANS_ACT_TO_LPS_STEPS
- RTL8192E_TRANS_CARDDIS_TO_CARDEMU
- RTL8192E_TRANS_CARDEMU_TO_ACT
- RTL8192E_TRANS_CARDEMU_TO_ACT_STEPS
- RTL8192E_TRANS_CARDEMU_TO_CARDDIS
- RTL8192E_TRANS_CARDEMU_TO_PDN
- RTL8192E_TRANS_CARDEMU_TO_PDN_STEPS
- RTL8192E_TRANS_CARDEMU_TO_SUS
- RTL8192E_TRANS_CARDEMU_TO_SUS_STEPS
- RTL8192E_TRANS_END
- RTL8192E_TRANS_END_STEPS
- RTL8192E_TRANS_LPS_TO_ACT
- RTL8192E_TRANS_LPS_TO_ACT_STEPS
- RTL8192E_TRANS_PDN_TO_CARDEMU
- RTL8192E_TRANS_PDN_TO_CARDEMU_STEPS
- RTL8192E_TRANS_SUS_TO_CARDEMU
- RTL8192E_TRANS_SUS_TO_CARDEMU_STEPS
- RTL8192S
- RTL8192U
- RTL8192U_ASSERT
- RTL8192_EEPROM_ID
- RTL8195A
- RTL819XU_MODULE_NAME
- RTL819X_CCK_LOOPBACK
- RTL819X_DEFAULT_RF_TYPE
- RTL819X_DMA_LOOPBACK
- RTL819X_MAC_LOOPBACK
- RTL819X_NO_LOOPBACK
- RTL819X_TOTAL_RF_PATH
- RTL819xU_CCK_LOOPBACK
- RTL819xU_DMA_LOOPBACK
- RTL819xU_MAC_LOOPBACK
- RTL819xU_NO_LOOPBACK
- RTL819x_2GHZ_CH01_11
- RTL819x_2GHZ_CH12_13
- RTL819x_2GHZ_CH14
- RTL819x_5GHZ_5150_5350
- RTL819x_5GHZ_5470_5850
- RTL819x_5GHZ_5725_5850
- RTL819x_5GHZ_ALL
- RTL819x_DEBUG
- RTL8201F_IER
- RTL8201F_ISR
- RTL8201N_PHY_ID
- RTL8211B_INER_INIT
- RTL8211B_PHY_ID
- RTL8211E_INER_LINK_STATUS
- RTL8211E_MODE_MII_GMII
- RTL8211E_RX_DELAY
- RTL8211E_TX_DELAY
- RTL8211F_INER_LINK_STATUS
- RTL8211F_INSR
- RTL8211F_TX_DELAY
- RTL821x_EXT_PAGE_SELECT
- RTL821x_INER
- RTL821x_INSR
- RTL821x_PAGE_SELECT
- RTL821x_PHYSR
- RTL821x_PHYSR_DUPLEX
- RTL821x_PHYSR_SPEED
- RTL8225H
- RTL8225SE_ANAPARAM2_OFF
- RTL8225SE_ANAPARAM2_ON
- RTL8225SE_ANAPARAM3
- RTL8225SE_ANAPARAM_OFF
- RTL8225SE_ANAPARAM_OFF2
- RTL8225SE_ANAPARAM_ON
- RTL8225_ANAPARAM2_OFF
- RTL8225_ANAPARAM2_ON
- RTL8225_ANAPARAM_OFF
- RTL8225_ANAPARAM_ON
- RTL8366RB_BDTH_REG_DEFAULT
- RTL8366RB_BDTH_SW_MAX
- RTL8366RB_BDTH_UNIT
- RTL8366RB_CHIP_CTRL_RESET_HW
- RTL8366RB_CHIP_CTRL_RESET_SW
- RTL8366RB_CHIP_ID_8366
- RTL8366RB_CHIP_ID_REG
- RTL8366RB_CHIP_VERSION_CTRL_REG
- RTL8366RB_CHIP_VERSION_MASK
- RTL8366RB_EB_BASE
- RTL8366RB_EB_BDTH_MASK
- RTL8366RB_EB_PREIFG
- RTL8366RB_EB_PREIFG_REG
- RTL8366RB_EB_REG
- RTL8366RB_FIDMAX
- RTL8366RB_GLOBAL_MIB_COUNT
- RTL8366RB_GREEN_FEATURE_MSK
- RTL8366RB_GREEN_FEATURE_REG
- RTL8366RB_GREEN_FEATURE_RX
- RTL8366RB_GREEN_FEATURE_TX
- RTL8366RB_IB_BASE
- RTL8366RB_IB_BDTH_MASK
- RTL8366RB_IB_PREIFG
- RTL8366RB_IB_REG
- RTL8366RB_INTERRUPT_ACLEXCEED
- RTL8366RB_INTERRUPT_CONTROL_REG
- RTL8366RB_INTERRUPT_LINK_CHGALL
- RTL8366RB_INTERRUPT_MASK_REG
- RTL8366RB_INTERRUPT_P4_FIBER
- RTL8366RB_INTERRUPT_P4_UTP
- RTL8366RB_INTERRUPT_POLARITY
- RTL8366RB_INTERRUPT_STATUS_REG
- RTL8366RB_INTERRUPT_STORMEXCEED
- RTL8366RB_INTERRUPT_VALID
- RTL8366RB_LED_0_1_CTRL_REG
- RTL8366RB_LED_1_OFFSET
- RTL8366RB_LED_2_3_CTRL_REG
- RTL8366RB_LED_3_OFFSET
- RTL8366RB_LED_AN_FAULT
- RTL8366RB_LED_BLINKRATE_111MS
- RTL8366RB_LED_BLINKRATE_222MS
- RTL8366RB_LED_BLINKRATE_28MS
- RTL8366RB_LED_BLINKRATE_446MS
- RTL8366RB_LED_BLINKRATE_56MS
- RTL8366RB_LED_BLINKRATE_84MS
- RTL8366RB_LED_BLINKRATE_MASK
- RTL8366RB_LED_BLINKRATE_REG
- RTL8366RB_LED_CTRL_REG
- RTL8366RB_LED_DUP_COL
- RTL8366RB_LED_FIBER
- RTL8366RB_LED_FORCE
- RTL8366RB_LED_LINK_ACT
- RTL8366RB_LED_LINK_RX
- RTL8366RB_LED_LINK_TX
- RTL8366RB_LED_MASTER
- RTL8366RB_LED_OFF
- RTL8366RB_LED_SPD10
- RTL8366RB_LED_SPD100
- RTL8366RB_LED_SPD1000
- RTL8366RB_LED_SPD1000_ACT
- RTL8366RB_LED_SPD100_10_ACT
- RTL8366RB_LED_SPD100_ACT
- RTL8366RB_LED_SPD10_ACT
- RTL8366RB_MAC_FORCE_CTRL_REG
- RTL8366RB_MIB_COUNT
- RTL8366RB_MIB_COUNTER_BASE
- RTL8366RB_MIB_COUNTER_PORT_OFFSET
- RTL8366RB_MIB_CTRL_BUSY_MASK
- RTL8366RB_MIB_CTRL_GLOBAL_RESET
- RTL8366RB_MIB_CTRL_PORT_RESET
- RTL8366RB_MIB_CTRL_REG
- RTL8366RB_MIB_CTRL_RESET_MASK
- RTL8366RB_MIB_CTRL_USER_MASK
- RTL8366RB_NUM_INTERRUPT
- RTL8366RB_NUM_LEDGROUPS
- RTL8366RB_NUM_PORTS
- RTL8366RB_NUM_VIDS
- RTL8366RB_NUM_VLANS
- RTL8366RB_OAM_MULTIPLEXER_REG
- RTL8366RB_OAM_PARSER_REG
- RTL8366RB_P4_RGMII_LED
- RTL8366RB_PAACR0
- RTL8366RB_PAACR1
- RTL8366RB_PAACR2
- RTL8366RB_PAACR_AN
- RTL8366RB_PAACR_CPU_PORT
- RTL8366RB_PAACR_FULL_DUPLEX
- RTL8366RB_PAACR_LINK_UP
- RTL8366RB_PAACR_RX_PAUSE
- RTL8366RB_PAACR_SPEED_1000M
- RTL8366RB_PAACR_SPEED_100M
- RTL8366RB_PAACR_SPEED_10M
- RTL8366RB_PAACR_TX_PAUSE
- RTL8366RB_PECR
- RTL8366RB_PHY_ACCESS_BUSY_REG
- RTL8366RB_PHY_ACCESS_CTRL_REG
- RTL8366RB_PHY_ACCESS_DATA_REG
- RTL8366RB_PHY_ADDR_MAX
- RTL8366RB_PHY_CTRL_READ
- RTL8366RB_PHY_CTRL_WRITE
- RTL8366RB_PHY_EXT_BUSY
- RTL8366RB_PHY_EXT_CTRL_REG
- RTL8366RB_PHY_EXT_RDDATA_REG
- RTL8366RB_PHY_EXT_WRDATA_REG
- RTL8366RB_PHY_INT_BUSY
- RTL8366RB_PHY_NO_MASK
- RTL8366RB_PHY_NO_MAX
- RTL8366RB_PHY_NO_OFFSET
- RTL8366RB_PHY_PAGE_MASK
- RTL8366RB_PHY_PAGE_OFFSET
- RTL8366RB_PHY_REG_MASK
- RTL8366RB_PMC0
- RTL8366RB_PMC0_ADCTEST
- RTL8366RB_PMC0_DIS_BISR
- RTL8366RB_PMC0_EN_AUTOLOAD
- RTL8366RB_PMC0_EN_SCAN
- RTL8366RB_PMC0_P4_IOMODE_MASK
- RTL8366RB_PMC0_P4_IOMODE_SHIFT
- RTL8366RB_PMC0_P5_IOMODE_MASK
- RTL8366RB_PMC0_P5_IOMODE_SHIFT
- RTL8366RB_PMC0_PROBE
- RTL8366RB_PMC0_SDSMODE_MASK
- RTL8366RB_PMC0_SDSMODE_SHIFT
- RTL8366RB_PMC0_SPI
- RTL8366RB_PMC0_SRAM_DIAG
- RTL8366RB_PMC1
- RTL8366RB_PMCR
- RTL8366RB_PMCR_MIRROR_ISO
- RTL8366RB_PMCR_MIRROR_RX
- RTL8366RB_PMCR_MIRROR_SPC
- RTL8366RB_PMCR_MIRROR_TX
- RTL8366RB_PMCR_MONITOR_PORT
- RTL8366RB_PMCR_MONITOR_PORT_MASK
- RTL8366RB_PMCR_SOURCE_PORT
- RTL8366RB_PMCR_SOURCE_PORT_MASK
- RTL8366RB_PORT_1
- RTL8366RB_PORT_2
- RTL8366RB_PORT_3
- RTL8366RB_PORT_4
- RTL8366RB_PORT_5
- RTL8366RB_PORT_ALL
- RTL8366RB_PORT_ALL_BUT_CPU
- RTL8366RB_PORT_ALL_EXTERNAL
- RTL8366RB_PORT_ALL_INTERNAL
- RTL8366RB_PORT_CPU
- RTL8366RB_PORT_LINK_STATUS_BASE
- RTL8366RB_PORT_NUM_CPU
- RTL8366RB_PORT_STATUS_AN_MASK
- RTL8366RB_PORT_STATUS_DUPLEX_MASK
- RTL8366RB_PORT_STATUS_LINK_MASK
- RTL8366RB_PORT_STATUS_RXPAUSE_MASK
- RTL8366RB_PORT_STATUS_SPEED_MASK
- RTL8366RB_PORT_STATUS_TXPAUSE_MASK
- RTL8366RB_PORT_VLAN_CTRL_BASE
- RTL8366RB_PORT_VLAN_CTRL_MASK
- RTL8366RB_PORT_VLAN_CTRL_REG
- RTL8366RB_PORT_VLAN_CTRL_SHIFT
- RTL8366RB_POWER_SAVE
- RTL8366RB_POWER_SAVE_ON
- RTL8366RB_POWER_SAVING_REG
- RTL8366RB_PRIORITYMAX
- RTL8366RB_PSTAT0
- RTL8366RB_PSTAT1
- RTL8366RB_PSTAT2
- RTL8366RB_QOS
- RTL8366RB_QOS_DEFAULT_PREIFG
- RTL8366RB_RESET_CTRL_REG
- RTL8366RB_SGCR
- RTL8366RB_SGCR_EN_BC_STORM_CTRL
- RTL8366RB_SGCR_EN_VLAN
- RTL8366RB_SGCR_EN_VLAN_4KTB
- RTL8366RB_SGCR_MAX_LENGTH
- RTL8366RB_SGCR_MAX_LENGTH_1522
- RTL8366RB_SGCR_MAX_LENGTH_1536
- RTL8366RB_SGCR_MAX_LENGTH_1552
- RTL8366RB_SGCR_MAX_LENGTH_9216
- RTL8366RB_SGCR_MAX_LENGTH_MASK
- RTL8366RB_SMAR0
- RTL8366RB_SMAR1
- RTL8366RB_SMAR2
- RTL8366RB_SSCR0
- RTL8366RB_SSCR1
- RTL8366RB_SSCR2
- RTL8366RB_SSCR2_DROP_UNKNOWN_DA
- RTL8366RB_TABLE_ACCESS_CTRL_REG
- RTL8366RB_TABLE_VLAN_READ_CTRL
- RTL8366RB_TABLE_VLAN_WRITE_CTRL
- RTL8366RB_VLAN_FID_MASK
- RTL8366RB_VLAN_INGRESS_CTRL2_REG
- RTL8366RB_VLAN_MC_BASE
- RTL8366RB_VLAN_MEMBER_MASK
- RTL8366RB_VLAN_PRIORITY_MASK
- RTL8366RB_VLAN_PRIORITY_SHIFT
- RTL8366RB_VLAN_STAG_IDX_MASK
- RTL8366RB_VLAN_STAG_IDX_SHIFT
- RTL8366RB_VLAN_STAG_MBR_MASK
- RTL8366RB_VLAN_STAG_MBR_SHIFT
- RTL8366RB_VLAN_TABLE_READ_BASE
- RTL8366RB_VLAN_TABLE_WRITE_BASE
- RTL8366RB_VLAN_UNTAG_MASK
- RTL8366RB_VLAN_UNTAG_SHIFT
- RTL8366RB_VLAN_VID_MASK
- RTL8368RB_CPU_CTRL_REG
- RTL8368RB_CPU_INSTAG
- RTL8368RB_CPU_PORTS_MSK
- RTL8411B_PACKAGE_MODE
- RTL8411_CARD_DRIVE_DEFAULT
- RTL8703B
- RTL8711_NIC
- RTL8711_RF_DEF_SENS
- RTL8711_RF_MAX_SENS
- RTL8712_1stCUT
- RTL8712_2ndCUT
- RTL8712_3rdCUT
- RTL8712_8188S_8191S_8192S
- RTL8712_AIR_TRX
- RTL8712_BB_FW_LBK
- RTL8712_BB_LBK
- RTL8712_CMDCTRL_
- RTL8712_DEBUGCTRL_
- RTL8712_DMA_BCNQ
- RTL8712_DMA_BEQ
- RTL8712_DMA_BKQ
- RTL8712_DMA_BMCQ
- RTL8712_DMA_C2HCMD
- RTL8712_DMA_H2CCMD
- RTL8712_DMA_MGTQ
- RTL8712_DMA_RX0FF
- RTL8712_DMA_VIQ
- RTL8712_DMA_VOQ
- RTL8712_EDCASETTING_
- RTL8712_EEPROM_ID
- RTL8712_FIFOCTRL_
- RTL8712_FPGA
- RTL8712_GP_
- RTL8712_HCI_TYPE_72SDIO
- RTL8712_HCI_TYPE_72USB
- RTL8712_HCI_TYPE_92USB
- RTL8712_HCI_TYPE_AP_PCIE
- RTL8712_HCI_TYPE_AP_USB
- RTL8712_HCI_TYPE_PCIE
- RTL8712_HCI_TYPE_SDIO
- RTL8712_HCI_TYPE_USB
- RTL8712_INTERRUPT_
- RTL8712_IOBASE_ACCESS_PHYREG
- RTL8712_IOBASE_FF
- RTL8712_IOBASE_FW2HW
- RTL8712_IOBASE_IOREG
- RTL8712_IOBASE_RXCMD
- RTL8712_IOBASE_RXPKT
- RTL8712_IOBASE_RXSTATUS
- RTL8712_IOBASE_SCHEDULER
- RTL8712_IOBASE_TRXDMA
- RTL8712_IOBASE_TXLLT
- RTL8712_IOBASE_TXPKT
- RTL8712_IOBASE_TXSTATUS
- RTL8712_IOBASE_WMAC
- RTL8712_MACIDSETTING_
- RTL8712_MAC_FW_LBK
- RTL8712_MAC_LBK
- RTL8712_NIC
- RTL8712_OFFLOAD_
- RTL8712_POWERSAVE_
- RTL8712_RATECTRL_
- RTL8712_RFCONFIG_1R
- RTL8712_RFCONFIG_1T
- RTL8712_RFCONFIG_1T1R
- RTL8712_RFCONFIG_1T2R
- RTL8712_RFCONFIG_2R
- RTL8712_RFCONFIG_2T
- RTL8712_RFCONFIG_2T2R
- RTL8712_RFCONFIG_TURBO
- RTL8712_RFC_1R
- RTL8712_RFC_1T
- RTL8712_RFC_1T1R
- RTL8712_RFC_1T2R
- RTL8712_RFC_2R
- RTL8712_RFC_2T
- RTL8712_RFC_2T2R
- RTL8712_RFC_TURBO
- RTL8712_RF_1T1R
- RTL8712_RF_1T2R
- RTL8712_RF_2T2R
- RTL8712_RF_CONFIG
- RTL8712_SDIO
- RTL8712_SDIO_LOCAL_BASE
- RTL8712_SECURITY_
- RTL8712_SYSCFG_
- RTL8712_TIMECTRL_
- RTL8712_USB
- RTL8712_WMAC_
- RTL8713_NIC
- RTL8716_NIC
- RTL871X_GET_ENCRYPTION
- RTL871X_HCI_TYPE
- RTL871X_HOSTAPD_ACL_ADD_STA
- RTL871X_HOSTAPD_ACL_REMOVE_STA
- RTL871X_HOSTAPD_ADD_STA
- RTL871X_HOSTAPD_FLUSH
- RTL871X_HOSTAPD_GET_INFO_STA
- RTL871X_HOSTAPD_GET_RID
- RTL871X_HOSTAPD_GET_WPAIE_STA
- RTL871X_HOSTAPD_MLME
- RTL871X_HOSTAPD_REMOVE_STA
- RTL871X_HOSTAPD_SCAN_REQ
- RTL871X_HOSTAPD_SET_ASSOC_AP_ADDR
- RTL871X_HOSTAPD_SET_BEACON
- RTL871X_HOSTAPD_SET_FLAGS_STA
- RTL871X_HOSTAPD_SET_GENERIC_ELEMENT
- RTL871X_HOSTAPD_SET_HIDDEN_SSID
- RTL871X_HOSTAPD_SET_MACADDR_ACL
- RTL871X_HOSTAPD_SET_RID
- RTL871X_HOSTAPD_SET_WPS_ASSOC_RESP
- RTL871X_HOSTAPD_SET_WPS_BEACON
- RTL871X_HOSTAPD_SET_WPS_PROBE_RESP
- RTL871X_HOSTAPD_STA_CLEAR_STATS
- RTL871X_MP_IOCTL_SUBCODE
- RTL871X_SET_ENCRYPTION
- RTL871X_VENQT_READ
- RTL871X_VENQT_WRITE
- RTL8723A
- RTL8723A_CHANNEL_GROUPS
- RTL8723A_MAX_RF_PATHS
- RTL8723A_TRANS_ACT_TO_CARDEMU
- RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS
- RTL8723A_TRANS_ACT_TO_LPS
- RTL8723A_TRANS_ACT_TO_LPS_STEPS
- RTL8723A_TRANS_CARDDIS_TO_CARDEMU
- RTL8723A_TRANS_CARDEMU_TO_ACT
- RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS
- RTL8723A_TRANS_CARDEMU_TO_CARDDIS
- RTL8723A_TRANS_CARDEMU_TO_PDN
- RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS
- RTL8723A_TRANS_CARDEMU_TO_SUS
- RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS
- RTL8723A_TRANS_END
- RTL8723A_TRANS_END_STEPS
- RTL8723A_TRANS_LPS_TO_ACT
- RTL8723A_TRANS_LPS_TO_ACT_STEPS
- RTL8723A_TRANS_PDN_TO_CARDEMU
- RTL8723A_TRANS_PDN_TO_CARDEMU_STEPS
- RTL8723A_TRANS_SUS_TO_CARDEMU
- RTL8723A_TRANS_SUS_TO_CARDEMU_STEPS
- RTL8723B
- RTL8723BE_EEPROM_ID
- RTL8723B_AGC_TAB
- RTL8723B_CHANNEL_GROUPS
- RTL8723B_EX_MESSAGE_BOX_SIZE
- RTL8723B_FW_IMG
- RTL8723B_FW_WW_IMG
- RTL8723B_MAX_CMD_LEN
- RTL8723B_MAX_RF_PATHS
- RTL8723B_PHY_MACREG
- RTL8723B_PHY_RADIO_A
- RTL8723B_PHY_RADIO_B
- RTL8723B_PHY_REG
- RTL8723B_PHY_REG_MP
- RTL8723B_PHY_REG_PG
- RTL8723B_TRANS_ACT_TO_CARDEMU
- RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS
- RTL8723B_TRANS_ACT_TO_LPS
- RTL8723B_TRANS_ACT_TO_LPS_STEPS
- RTL8723B_TRANS_ACT_TO_SWLPS
- RTL8723B_TRANS_ACT_TO_SWLPS_STEPS
- RTL8723B_TRANS_CARDDIS_TO_CARDEMU
- RTL8723B_TRANS_CARDEMU_TO_ACT
- RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS
- RTL8723B_TRANS_CARDEMU_TO_CARDDIS
- RTL8723B_TRANS_CARDEMU_TO_PDN
- RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS
- RTL8723B_TRANS_CARDEMU_TO_SUS
- RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS
- RTL8723B_TRANS_END
- RTL8723B_TRANS_END_STEPS
- RTL8723B_TRANS_LPS_TO_ACT
- RTL8723B_TRANS_LPS_TO_ACT_STEPS
- RTL8723B_TRANS_PDN_TO_CARDEMU
- RTL8723B_TRANS_PDN_TO_CARDEMU_STEPS
- RTL8723B_TRANS_SUS_TO_CARDEMU
- RTL8723B_TRANS_SUS_TO_CARDEMU_STEPS
- RTL8723B_TRANS_SWLPS_TO_ACT
- RTL8723B_TRANS_SWLPS_TO_ACT_STEPS
- RTL8723B_TXPWR_LMT
- RTL8723B_TXPWR_TRACK
- RTL8723B_TX_COUNT
- RTL8723ERADIOA_1TARRAYLENGTH
- RTL8723E_AGCTAB_1TARRAYLENGTH
- RTL8723E_MACARRAYLENGTH
- RTL8723E_PHY_REG_1TARRAY_LENGTH
- RTL8723E_PHY_REG_ARRAY_PGLENGTH
- RTL8723_NIC_DISABLE_FLOW
- RTL8723_NIC_ENABLE_FLOW
- RTL8723_NIC_LPS_ENTER_FLOW
- RTL8723_NIC_LPS_LEAVE_FLOW
- RTL8723_NIC_PDN_FLOW
- RTL8723_NIC_PWR_ON_FLOW
- RTL8723_NIC_RESUME_FLOW
- RTL8723_NIC_RF_OFF_FLOW
- RTL8723_NIC_SUSPEND_FLOW
- RTL8812
- RTL8812_NIC_DISABLE_FLOW
- RTL8812_NIC_ENABLE_FLOW
- RTL8812_NIC_LPS_ENTER_FLOW
- RTL8812_NIC_LPS_LEAVE_FLOW
- RTL8812_NIC_PDN_FLOW
- RTL8812_NIC_PWR_ON_FLOW
- RTL8812_NIC_RESUME_FLOW
- RTL8812_NIC_RF_OFF_FLOW
- RTL8812_NIC_SUSPEND_FLOW
- RTL8812_TRANS_ACT_TO_CARDEMU
- RTL8812_TRANS_ACT_TO_CARDEMU_STEPS
- RTL8812_TRANS_ACT_TO_LPS
- RTL8812_TRANS_ACT_TO_LPS_STEPS
- RTL8812_TRANS_CARDDIS_TO_CARDEMU
- RTL8812_TRANS_CARDEMU_TO_ACT
- RTL8812_TRANS_CARDEMU_TO_ACT_STEPS
- RTL8812_TRANS_CARDEMU_TO_CARDDIS
- RTL8812_TRANS_CARDEMU_TO_PDN
- RTL8812_TRANS_CARDEMU_TO_PDN_STEPS
- RTL8812_TRANS_CARDEMU_TO_SUS
- RTL8812_TRANS_CARDEMU_TO_SUS_STEPS
- RTL8812_TRANS_END
- RTL8812_TRANS_END_STEPS
- RTL8812_TRANS_LPS_TO_ACT
- RTL8812_TRANS_LPS_TO_ACT_STEPS
- RTL8812_TRANS_PDN_TO_CARDEMU
- RTL8812_TRANS_PDN_TO_CARDEMU_STEPS
- RTL8812_TRANS_SUS_TO_CARDEMU
- RTL8812_TRANS_SUS_TO_CARDEMU_STEPS
- RTL8814A
- RTL8821
- RTL8821AE_MAX_PATH_NUM
- RTL8821AE_RX_HAL_IS_CCK_RATE
- RTL8821A_NIC_DISABLE_FLOW
- RTL8821A_NIC_ENABLE_FLOW
- RTL8821A_NIC_LPS_ENTER_FLOW
- RTL8821A_NIC_LPS_LEAVE_FLOW
- RTL8821A_NIC_PDN_FLOW
- RTL8821A_NIC_PWR_ON_FLOW
- RTL8821A_NIC_RESUME_FLOW
- RTL8821A_NIC_RF_OFF_FLOW
- RTL8821A_NIC_SUSPEND_FLOW
- RTL8821A_TRANS_ACT_TO_CARDEMU
- RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS
- RTL8821A_TRANS_ACT_TO_LPS
- RTL8821A_TRANS_ACT_TO_LPS_STEPS
- RTL8821A_TRANS_CARDDIS_TO_CARDEMU
- RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS
- RTL8821A_TRANS_CARDEMU_TO_ACT
- RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS
- RTL8821A_TRANS_CARDEMU_TO_CARDDIS
- RTL8821A_TRANS_CARDEMU_TO_PDN
- RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS
- RTL8821A_TRANS_CARDEMU_TO_SUS
- RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS
- RTL8821A_TRANS_END
- RTL8821A_TRANS_END_STEPS
- RTL8821A_TRANS_LPS_TO_ACT
- RTL8821A_TRANS_LPS_TO_ACT_STEPS
- RTL8821A_TRANS_PDN_TO_CARDEMU
- RTL8821A_TRANS_PDN_TO_CARDEMU_STEPS
- RTL8821A_TRANS_SUS_TO_CARDEMU
- RTL8821A_TRANS_SUS_TO_CARDEMU_STEPS
- RTL8821B
- RTL8822B
- RTL8881A
- RTL88E_EX_MESSAGE_BOX_SIZE
- RTL88E_MAX_CMD_LEN
- RTL88E_MAX_H2C_BOX_NUMS
- RTL88E_MESSAGE_BOX_SIZE
- RTL8XXXU_ADDA_REGS
- RTL8XXXU_BB_REGS
- RTL8XXXU_DEBUG_ACTION
- RTL8XXXU_DEBUG_CHANNEL
- RTL8XXXU_DEBUG_EFUSE
- RTL8XXXU_DEBUG_H2C
- RTL8XXXU_DEBUG_INTERRUPT
- RTL8XXXU_DEBUG_KEY
- RTL8XXXU_DEBUG_REG_READ
- RTL8XXXU_DEBUG_REG_WRITE
- RTL8XXXU_DEBUG_RFREG_READ
- RTL8XXXU_DEBUG_RFREG_WRITE
- RTL8XXXU_DEBUG_RX
- RTL8XXXU_DEBUG_RX_DUMP
- RTL8XXXU_DEBUG_TX
- RTL8XXXU_DEBUG_TX_DUMP
- RTL8XXXU_DEBUG_USB
- RTL8XXXU_FIRMWARE_POLL_MAX
- RTL8XXXU_MAC_REGS
- RTL8XXXU_MAX_CHANNEL_GROUPS
- RTL8XXXU_MAX_REG_POLL
- RTL8XXXU_OUT_ENDPOINTS
- RTL8XXXU_RX_URBS
- RTL8XXXU_RX_URB_PENDING_WATER
- RTL8XXXU_TX_URBS
- RTL8XXXU_TX_URB_HIGH_WATER
- RTL8XXXU_TX_URB_LOW_WATER
- RTL92C_DRIVER_INFO_SIZE
- RTL92C_MAX_PATH_NUM
- RTL92C_NUM_RX_URBS
- RTL92C_NUM_TX_URBS
- RTL92C_SIZE_MAX_RX_BUFFER
- RTL92C_USB_BULK_IN_NUM
- RTL92EE_RX_HAL_IS_CCK_RATE
- RTLLIB_1ADDR_LEN
- RTLLIB_24GHZ_BAND
- RTLLIB_2ADDR_LEN
- RTLLIB_3ADDR_LEN
- RTLLIB_4ADDR_LEN
- RTLLIB_52GHZ_BAND
- RTLLIB_ASSOCIATING
- RTLLIB_ASSOCIATING_AUTHENTICATED
- RTLLIB_ASSOCIATING_AUTHENTICATING
- RTLLIB_ASSOCIATING_RETRY
- RTLLIB_BASIC_RATE_MASK
- RTLLIB_CCK_MODULATION
- RTLLIB_CCK_RATE_11MB
- RTLLIB_CCK_RATE_1MB
- RTLLIB_CCK_RATE_2MB
- RTLLIB_CCK_RATE_5MB
- RTLLIB_CCK_RATE_LEN
- RTLLIB_DEFAULT_BASIC_RATE
- RTLLIB_DEFAULT_TX_ESSID
- RTLLIB_DTIM_INVALID
- RTLLIB_DTIM_MBCAST
- RTLLIB_DTIM_UCAST
- RTLLIB_DTIM_VALID
- RTLLIB_FC0_SUBTYPE_MASK
- RTLLIB_FC0_SUBTYPE_QOS
- RTLLIB_FC0_TYPE_DATA
- RTLLIB_FC0_TYPE_MASK
- RTLLIB_FCS_LEN
- RTLLIB_FCTL_DSTODS
- RTLLIB_FCTL_FRAMETYPE
- RTLLIB_FCTL_FROMDS
- RTLLIB_FCTL_FTYPE
- RTLLIB_FCTL_MOREDATA
- RTLLIB_FCTL_MOREFRAGS
- RTLLIB_FCTL_ORDER
- RTLLIB_FCTL_PM
- RTLLIB_FCTL_RETRY
- RTLLIB_FCTL_STYPE
- RTLLIB_FCTL_TODS
- RTLLIB_FCTL_WEP
- RTLLIB_FRAG_CACHE_LEN
- RTLLIB_FTYPE_CTL
- RTLLIB_FTYPE_DATA
- RTLLIB_FTYPE_MGMT
- RTLLIB_H
- RTLLIB_LINKED
- RTLLIB_LINKED_SCANNING
- RTLLIB_NOLINK
- RTLLIB_OFDM_MODULATION
- RTLLIB_OFDM_RATE_12MB
- RTLLIB_OFDM_RATE_18MB
- RTLLIB_OFDM_RATE_24MB
- RTLLIB_OFDM_RATE_36MB
- RTLLIB_OFDM_RATE_48MB
- RTLLIB_OFDM_RATE_54MB
- RTLLIB_OFDM_RATE_6MB
- RTLLIB_OFDM_RATE_9MB
- RTLLIB_OFDM_RATE_LEN
- RTLLIB_PS_DISABLED
- RTLLIB_PS_MBCAST
- RTLLIB_PS_UNICAST
- RTLLIB_QCTL_TID
- RTLLIB_QOS_HAS_SEQ
- RTLLIB_QOS_TID
- RTLLIB_SCTL_FRAG
- RTLLIB_SCTL_SEQ
- RTLLIB_SKBBUFFER_SIZE
- RTLLIB_SOFTMAC_ASSOC_RETRY_TIME
- RTLLIB_SOFTMAC_SCAN_TIME
- RTLLIB_STATMASK_NOISE
- RTLLIB_STATMASK_RSSI
- RTLLIB_STATMASK_SIGNAL
- RTLLIB_STATMASK_WEMASK
- RTLLIB_STYPE_ACK
- RTLLIB_STYPE_ASSOC_REQ
- RTLLIB_STYPE_ASSOC_RESP
- RTLLIB_STYPE_ATIM
- RTLLIB_STYPE_AUTH
- RTLLIB_STYPE_BEACON
- RTLLIB_STYPE_CTS
- RTLLIB_STYPE_DATA
- RTLLIB_STYPE_DATA_CFACK
- RTLLIB_STYPE_DATA_CFACKPOLL
- RTLLIB_STYPE_DATA_CFPOLL
- RTLLIB_STYPE_DEAUTH
- RTLLIB_STYPE_DISASSOC
- RTLLIB_STYPE_MANAGE_ACT
- RTLLIB_STYPE_NULLFUNC
- RTLLIB_STYPE_PROBE_REQ
- RTLLIB_STYPE_PROBE_RESP
- RTLLIB_STYPE_PSPOLL
- RTLLIB_STYPE_QOS_DATA
- RTLLIB_STYPE_QOS_NULL
- RTLLIB_STYPE_REASSOC_REQ
- RTLLIB_STYPE_REASSOC_RESP
- RTLLIB_STYPE_RTS
- RTLLIB_WATCH_DOG_TIME
- RTLPRIV
- RTLX_BUFFER_SIZE
- RTLX_CHANNELS
- RTLX_CHANNEL_DBG
- RTLX_CHANNEL_STDIO
- RTLX_CHANNEL_SYSIO
- RTLX_ID
- RTLX_MODULE_NAME
- RTLX_STATE_INITIALISED
- RTLX_STATE_OPENED
- RTLX_STATE_REMOTE_READY
- RTLX_STATE_UNUSED
- RTLX_VERSION
- RTLX_xID
- RTL_ADDR_TYPE_IO
- RTL_ADDR_TYPE_MMIO
- RTL_ADVERTISED_1000_FULL
- RTL_ADVERTISED_1000_HALF
- RTL_ADVERTISED_100_FULL
- RTL_ADVERTISED_100_HALF
- RTL_ADVERTISED_10_FULL
- RTL_ADVERTISED_10_HALF
- RTL_ADV_2500FULL
- RTL_AGG_EMPTYING_HW_QUEUE_ADDBA
- RTL_AGG_EMPTYING_HW_QUEUE_DELBA
- RTL_AGG_OFF
- RTL_AGG_ON
- RTL_AGG_OPERATIONAL
- RTL_AGG_PROGRESS
- RTL_AGG_START
- RTL_AGG_STOP
- RTL_CFG_NO_GBIT
- RTL_CMD_ENTER_PRTM
- RTL_CMD_EXIT_PRTM
- RTL_COALESCE_FRAME_MAX
- RTL_COALESCE_MASK
- RTL_COALESCE_SHIFT
- RTL_COALESCE_T_MAX
- RTL_CONFIG_MAGIC
- RTL_DEBUG
- RTL_DEBUGFS_ADD
- RTL_DEBUGFS_ADD_CORE
- RTL_DEBUGFS_ADD_W
- RTL_DEBUG_IMPL_BB_SERIES
- RTL_DEBUG_IMPL_CAM_SERIES
- RTL_DEBUG_IMPL_MAC_SERIES
- RTL_DEBUG_IMPL_RF_SERIES
- RTL_DEFAULT_HARDWARE_TYPE
- RTL_DUMMY_OFFSET
- RTL_DUMMY_UNIT
- RTL_EEPROM_ID
- RTL_EPATCH_SIGNATURE
- RTL_EVENT_NAPI
- RTL_EVENT_NAPI_RX
- RTL_EVENT_NAPI_TX
- RTL_FLAG_MAX
- RTL_FLAG_TASK_ENABLED
- RTL_FLAG_TASK_RESET_PENDING
- RTL_FRAG_LEN
- RTL_FW_PAGE_SIZE
- RTL_GENERIC_PHYID
- RTL_GIGA_MAC_NONE
- RTL_GIGA_MAC_VER_02
- RTL_GIGA_MAC_VER_03
- RTL_GIGA_MAC_VER_04
- RTL_GIGA_MAC_VER_05
- RTL_GIGA_MAC_VER_06
- RTL_GIGA_MAC_VER_07
- RTL_GIGA_MAC_VER_08
- RTL_GIGA_MAC_VER_09
- RTL_GIGA_MAC_VER_10
- RTL_GIGA_MAC_VER_11
- RTL_GIGA_MAC_VER_12
- RTL_GIGA_MAC_VER_13
- RTL_GIGA_MAC_VER_14
- RTL_GIGA_MAC_VER_15
- RTL_GIGA_MAC_VER_16
- RTL_GIGA_MAC_VER_17
- RTL_GIGA_MAC_VER_18
- RTL_GIGA_MAC_VER_19
- RTL_GIGA_MAC_VER_20
- RTL_GIGA_MAC_VER_21
- RTL_GIGA_MAC_VER_22
- RTL_GIGA_MAC_VER_23
- RTL_GIGA_MAC_VER_24
- RTL_GIGA_MAC_VER_25
- RTL_GIGA_MAC_VER_26
- RTL_GIGA_MAC_VER_27
- RTL_GIGA_MAC_VER_28
- RTL_GIGA_MAC_VER_29
- RTL_GIGA_MAC_VER_30
- RTL_GIGA_MAC_VER_31
- RTL_GIGA_MAC_VER_32
- RTL_GIGA_MAC_VER_33
- RTL_GIGA_MAC_VER_34
- RTL_GIGA_MAC_VER_35
- RTL_GIGA_MAC_VER_36
- RTL_GIGA_MAC_VER_37
- RTL_GIGA_MAC_VER_38
- RTL_GIGA_MAC_VER_39
- RTL_GIGA_MAC_VER_40
- RTL_GIGA_MAC_VER_41
- RTL_GIGA_MAC_VER_42
- RTL_GIGA_MAC_VER_43
- RTL_GIGA_MAC_VER_44
- RTL_GIGA_MAC_VER_45
- RTL_GIGA_MAC_VER_46
- RTL_GIGA_MAC_VER_47
- RTL_GIGA_MAC_VER_48
- RTL_GIGA_MAC_VER_49
- RTL_GIGA_MAC_VER_50
- RTL_GIGA_MAC_VER_51
- RTL_GIGA_MAC_VER_60
- RTL_GIGA_MAC_VER_61
- RTL_GSO_MAX_SEGS_V1
- RTL_GSO_MAX_SEGS_V2
- RTL_GSO_MAX_SIZE_V1
- RTL_GSO_MAX_SIZE_V2
- RTL_HW_TYPE
- RTL_IBSS_INT_MASKS
- RTL_ID
- RTL_IMR_ATIMEND
- RTL_IMR_BCNDMAINT1
- RTL_IMR_BCNDMAINT2
- RTL_IMR_BCNDMAINT3
- RTL_IMR_BCNDMAINT4
- RTL_IMR_BCNDMAINT5
- RTL_IMR_BCNDMAINT6
- RTL_IMR_BCNDOK1
- RTL_IMR_BCNDOK2
- RTL_IMR_BCNDOK3
- RTL_IMR_BCNDOK4
- RTL_IMR_BCNDOK5
- RTL_IMR_BCNDOK6
- RTL_IMR_BCNDOK7
- RTL_IMR_BCNDOK8
- RTL_IMR_BCNINT
- RTL_IMR_BDOK
- RTL_IMR_BEDOK
- RTL_IMR_BKDOK
- RTL_IMR_C2HCMD
- RTL_IMR_COMDOK
- RTL_IMR_H2CDOK
- RTL_IMR_HIGHDOK
- RTL_IMR_HSISR_IND
- RTL_IMR_MGNTDOK
- RTL_IMR_PSTIMEOUT
- RTL_IMR_RDU
- RTL_IMR_ROK
- RTL_IMR_RXFOVW
- RTL_IMR_TBDER
- RTL_IMR_TBDOK
- RTL_IMR_TIMEOUT1
- RTL_IMR_TIMEOUT2
- RTL_IMR_TXFOVW
- RTL_IMR_VIDOK
- RTL_IMR_VODOK
- RTL_IOCTL_HOSTAPD
- RTL_IOCTL_WPA_SUPPLICANT
- RTL_LIMITED_TSO_SIZE
- RTL_LPADV_10000FULL
- RTL_LPADV_2500FULL
- RTL_LPADV_5000FULL
- RTL_MAC80211_NUM_QUEUE
- RTL_MASK
- RTL_MEM_MAPPED_IO_RANGE_8190PCI
- RTL_MEM_MAPPED_IO_RANGE_8192CE
- RTL_MEM_MAPPED_IO_RANGE_8192DE
- RTL_MEM_MAPPED_IO_RANGE_8192PCIE
- RTL_MEM_MAPPED_IO_RANGE_8192SE
- RTL_MIN_IO_SIZE
- RTL_NUM_STATS
- RTL_PCI_0044_DID
- RTL_PCI_0045_DID
- RTL_PCI_0046_DID
- RTL_PCI_0047_DID
- RTL_PCI_700F_DID
- RTL_PCI_701F_DID
- RTL_PCI_8171_DID
- RTL_PCI_8172_DID
- RTL_PCI_8173_DID
- RTL_PCI_8174_DID
- RTL_PCI_8188CE_DID
- RTL_PCI_8188EE_DID
- RTL_PCI_8191CE_DID
- RTL_PCI_8192CET_DID
- RTL_PCI_8192CE_DID
- RTL_PCI_8192CU_DID
- RTL_PCI_8192DE_DID
- RTL_PCI_8192DE_DID2
- RTL_PCI_8192EE_DID
- RTL_PCI_8192SE_DID
- RTL_PCI_8192_DID
- RTL_PCI_8723AE_DID
- RTL_PCI_8723BE_DID
- RTL_PCI_8812AE_DID
- RTL_PCI_8821AE_DID
- RTL_PCI_8822BE_DID
- RTL_PCI_DEVICE
- RTL_PCI_DLINK_DID
- RTL_PCI_MAX_RX_COUNT
- RTL_PCI_MAX_RX_QUEUE
- RTL_PCI_MAX_TX_QUEUE_COUNT
- RTL_PCI_REVISION_ID_8190PCI
- RTL_PCI_REVISION_ID_8192CE
- RTL_PCI_REVISION_ID_8192DE
- RTL_PCI_REVISION_ID_8192PCIE
- RTL_PCI_REVISION_ID_8192SE
- RTL_PCI_RX_CMD_QUEUE
- RTL_PCI_RX_MPDU_QUEUE
- RTL_PHY_CTRL_FD
- RTL_PHY_CTRL_SPD_100
- RTL_R16
- RTL_R32
- RTL_R8
- RTL_RC_CCK_RATE11M
- RTL_RC_CCK_RATE1M
- RTL_RC_CCK_RATE2M
- RTL_RC_CCK_RATE5_5M
- RTL_RC_HT_RATEMCS15
- RTL_RC_HT_RATEMCS7
- RTL_RC_OFDM_RATE12M
- RTL_RC_OFDM_RATE18M
- RTL_RC_OFDM_RATE24M
- RTL_RC_OFDM_RATE36M
- RTL_RC_OFDM_RATE48M
- RTL_RC_OFDM_RATE54M
- RTL_RC_OFDM_RATE6M
- RTL_RC_OFDM_RATE9M
- RTL_RC_VHT_RATE_1SS_MCS7
- RTL_RC_VHT_RATE_1SS_MCS8
- RTL_RC_VHT_RATE_1SS_MCS9
- RTL_RC_VHT_RATE_2SS_MCS7
- RTL_RC_VHT_RATE_2SS_MCS8
- RTL_RC_VHT_RATE_2SS_MCS9
- RTL_REGS_VER
- RTL_ROM_LMP_3499
- RTL_ROM_LMP_8723A
- RTL_ROM_LMP_8723B
- RTL_ROM_LMP_8723D
- RTL_ROM_LMP_8761A
- RTL_ROM_LMP_8821A
- RTL_ROM_LMP_8822B
- RTL_RX_AGG_START
- RTL_RX_AGG_STOP
- RTL_RX_DESC_SIZE
- RTL_RX_DRV_INFO_UNIT
- RTL_SIGNATURE
- RTL_SLOT_TIME_20
- RTL_SLOT_TIME_9
- RTL_SPEC_EXT_C2H
- RTL_SPEC_NEW_RATEID
- RTL_SPEC_SUPPORT_VHT
- RTL_STATUS_INTERFACE_START
- RTL_SUPPORTED_FILTERS
- RTL_SUPPORTS_10000FULL
- RTL_SUPPORTS_2500FULL
- RTL_SUPPORTS_5000FULL
- RTL_TXQ_BCN
- RTL_TXQ_BE
- RTL_TXQ_BK
- RTL_TXQ_HI
- RTL_TXQ_MGT
- RTL_TXQ_VI
- RTL_TXQ_VO
- RTL_TX_DESC_SIZE
- RTL_TX_DUMMY_SIZE
- RTL_TX_HEADER_SIZE
- RTL_USB_DEVICE
- RTL_USB_MAX_EP_NUM
- RTL_USB_MAX_RX_COUNT
- RTL_USB_MAX_TXQ_NUM
- RTL_USB_MAX_TX_URBS_NUM
- RTL_USB_RX_AGG_BLOCK_NUM
- RTL_USB_RX_AGG_BLOCK_TIMEOUT
- RTL_USB_RX_AGG_PAGE_NUM
- RTL_USB_RX_AGG_PAGE_TIMEOUT
- RTL_USB_TX_AGG_NUM_DESC
- RTL_VAR_MAP_MAX
- RTL_VERSION_MASK
- RTL_VERSION_SHIFT
- RTL_VER_01
- RTL_VER_02
- RTL_VER_03
- RTL_VER_04
- RTL_VER_05
- RTL_VER_06
- RTL_VER_07
- RTL_VER_08
- RTL_VER_09
- RTL_VER_MASK
- RTL_VER_MAX
- RTL_VER_SHIFT
- RTL_VER_SIZE
- RTL_VER_UNKNOWN
- RTL_W16
- RTL_W16_F
- RTL_W32
- RTL_W32_F
- RTL_W8
- RTL_W8_F
- RTL_WATCH_DOG_TIME
- RTMCTL_PRGM
- RTMCTL_SAMP_MODE_INVALID
- RTMCTL_SAMP_MODE_RAW_ES_SC
- RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC
- RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC
- RTMGRP_DECnet_IFADDR
- RTMGRP_DECnet_ROUTE
- RTMGRP_IPV4_IFADDR
- RTMGRP_IPV4_MROUTE
- RTMGRP_IPV4_ROUTE
- RTMGRP_IPV4_RULE
- RTMGRP_IPV6_IFADDR
- RTMGRP_IPV6_IFINFO
- RTMGRP_IPV6_MROUTE
- RTMGRP_IPV6_PREFIX
- RTMGRP_IPV6_ROUTE
- RTMGRP_LINK
- RTMGRP_NEIGH
- RTMGRP_NOTIFY
- RTMGRP_TC
- RTMP
- RTMSG_DELDEVICE
- RTMSG_DELROUTE
- RTMSG_NEWDEVICE
- RTMSG_NEWROUTE
- RTM_BASE
- RTM_DELACTION
- RTM_DELADDR
- RTM_DELADDRLABEL
- RTM_DELCHAIN
- RTM_DELLINK
- RTM_DELMDB
- RTM_DELNEIGH
- RTM_DELNETCONF
- RTM_DELNEXTHOP
- RTM_DELNSID
- RTM_DELQDISC
- RTM_DELROUTE
- RTM_DELRULE
- RTM_DELTCLASS
- RTM_DELTFILTER
- RTM_FAM
- RTM_F_CLONED
- RTM_F_EQUALIZE
- RTM_F_FIB_MATCH
- RTM_F_LOOKUP_TABLE
- RTM_F_NOTIFY
- RTM_F_PREFIX
- RTM_GETACTION
- RTM_GETADDR
- RTM_GETADDRLABEL
- RTM_GETANYCAST
- RTM_GETCHAIN
- RTM_GETDCB
- RTM_GETLINK
- RTM_GETMDB
- RTM_GETMULTICAST
- RTM_GETNEIGH
- RTM_GETNEIGHTBL
- RTM_GETNETCONF
- RTM_GETNEXTHOP
- RTM_GETNSID
- RTM_GETQDISC
- RTM_GETROUTE
- RTM_GETRULE
- RTM_GETSTATS
- RTM_GETTCLASS
- RTM_GETTFILTER
- RTM_MAX
- RTM_NEWACTION
- RTM_NEWADDR
- RTM_NEWADDRLABEL
- RTM_NEWCACHEREPORT
- RTM_NEWCHAIN
- RTM_NEWLINK
- RTM_NEWMDB
- RTM_NEWNDUSEROPT
- RTM_NEWNEIGH
- RTM_NEWNEIGHTBL
- RTM_NEWNETCONF
- RTM_NEWNEXTHOP
- RTM_NEWNSID
- RTM_NEWPREFIX
- RTM_NEWQDISC
- RTM_NEWROUTE
- RTM_NEWRULE
- RTM_NEWSTATS
- RTM_NEWTCLASS
- RTM_NEWTFILTER
- RTM_NR_FAMILIES
- RTM_NR_MSGTYPES
- RTM_PAYLOAD
- RTM_RTA
- RTM_SETDCB
- RTM_SETLINK
- RTM_SETNEIGHTBL
- RTNETLINK_HAVE_PEERINFO
- RTNH_ALIGN
- RTNH_ALIGNTO
- RTNH_COMPARE_MASK
- RTNH_DATA
- RTNH_F_DEAD
- RTNH_F_LINKDOWN
- RTNH_F_OFFLOAD
- RTNH_F_ONLINK
- RTNH_F_PERVASIVE
- RTNH_F_UNRESOLVED
- RTNH_LENGTH
- RTNH_NEXT
- RTNH_OK
- RTNH_SPACE
- RTNLGRP_DCB
- RTNLGRP_DECnet_IFADDR
- RTNLGRP_DECnet_ROUTE
- RTNLGRP_DECnet_RULE
- RTNLGRP_IPV4_IFADDR
- RTNLGRP_IPV4_MROUTE
- RTNLGRP_IPV4_MROUTE_R
- RTNLGRP_IPV4_NETCONF
- RTNLGRP_IPV4_ROUTE
- RTNLGRP_IPV4_RULE
- RTNLGRP_IPV6_IFADDR
- RTNLGRP_IPV6_IFINFO
- RTNLGRP_IPV6_MROUTE
- RTNLGRP_IPV6_MROUTE_R
- RTNLGRP_IPV6_NETCONF
- RTNLGRP_IPV6_PREFIX
- RTNLGRP_IPV6_ROUTE
- RTNLGRP_IPV6_RULE
- RTNLGRP_LINK
- RTNLGRP_MAX
- RTNLGRP_MDB
- RTNLGRP_MPLS_NETCONF
- RTNLGRP_MPLS_ROUTE
- RTNLGRP_ND_USEROPT
- RTNLGRP_NEIGH
- RTNLGRP_NEXTHOP
- RTNLGRP_NONE
- RTNLGRP_NOP2
- RTNLGRP_NOP4
- RTNLGRP_NOTIFY
- RTNLGRP_NSID
- RTNLGRP_PHONET_IFADDR
- RTNLGRP_PHONET_ROUTE
- RTNLGRP_TC
- RTNL_FAMILY_IP6MR
- RTNL_FAMILY_IPMR
- RTNL_FAMILY_MAX
- RTNL_FLAG_DOIT_UNLOCKED
- RTNL_LINK_INITIALIZED
- RTNL_LINK_INITIALIZING
- RTNL_MAX_TYPE
- RTNL_SLAVE_MAX_TYPE
- RTN_ANYCAST
- RTN_BLACKHOLE
- RTN_BROADCAST
- RTN_LOCAL
- RTN_MAX
- RTN_MULTICAST
- RTN_NAT
- RTN_PROHIBIT
- RTN_ROOT
- RTN_RTINFO
- RTN_THROW
- RTN_TL_ROOT
- RTN_UNICAST
- RTN_UNREACHABLE
- RTN_UNSPEC
- RTN_XRESOLVE
- RTO
- RTOBSERVESELECT
- RTOR_CLK
- RTOR_EN
- RTOR_PSC
- RTOS_TIMER_INT
- RTOS_TIMER_REGS_ADDR
- RTO_ONLINK
- RTPE
- RTPG_FMT_EXT_HDR
- RTPG_FMT_MASK
- RTPORT
- RTPRINT
- RTPROT_BABEL
- RTPROT_BGP
- RTPROT_BIRD
- RTPROT_BOOT
- RTPROT_DHCP
- RTPROT_DNROUTED
- RTPROT_EIGRP
- RTPROT_GATED
- RTPROT_ISIS
- RTPROT_KERNEL
- RTPROT_MROUTED
- RTPROT_MRT
- RTPROT_NTK
- RTPROT_OSPF
- RTPROT_RA
- RTPROT_REDIRECT
- RTPROT_RIP
- RTPROT_STATIC
- RTPROT_UNSPEC
- RTPROT_XORP
- RTPROT_ZEBRA
- RTP_TIMER_CFG_WK_CID
- RTQ
- RTR
- RTRACK2_MAX
- RTRACK_MAX
- RTRAP_PSTATE
- RTRAP_PSTATE_AG_IRQOFF
- RTRAP_PSTATE_IRQOFF
- RTRATE
- RTRD
- RTRE
- RTRIM_EN
- RTRY
- RTRYCNT
- RTRY_LMT_DIS
- RTR_DEFAULT
- RTR_READ
- RTR_SEND
- RTR_SOLICITATION_INTERVAL
- RTR_SOLICITATION_MAX_INTERVAL
- RTR_WRITE
- RTS
- RTS0_A_MARK
- RTS0_B_MARK
- RTS0_B_TANS_B_MARK
- RTS0_C_MARK
- RTS0_C_TANS_C_MARK
- RTS0_D_TANS_D_MARK
- RTS0_MARK
- RTS0_N_MARK
- RTS0_TANS_MARK
- RTS1_A_MARK
- RTS1_B_MARK
- RTS1_B_TANS_B_MARK
- RTS1_C_MARK
- RTS1_C_TANS_C_MARK
- RTS1_E_MARK
- RTS1_MARK
- RTS1_MASK
- RTS1_N_MARK
- RTS1_SHIFT
- RTS1_TANS_MARK
- RTS2_MARK
- RTS2_MASK
- RTS2_SHIFT
- RTS3_MARK
- RTS4_MARK
- RTS5179
- RTS51X_GET_PID
- RTS51X_GET_VID
- RTS51X_STAT
- RTS51X_STAT_IDLE
- RTS51X_STAT_INIT
- RTS51X_STAT_RUN
- RTS51X_STAT_SS
- RTS5209_CARD_DRIVE_DEFAULT
- RTS5227_DEVICE_ID
- RTS522A_OCP_THD_800
- RTS522A_PM_CTRL3
- RTS524A_OCP_THD_800
- RTS524A_PME_FORCE_CTL
- RTS524A_PM_CTRL3
- RTS525A_OCP_THD_800
- RTS5260_ADMA3_RST
- RTS5260_AUTOLOAD_CFG4
- RTS5260_DMA_RST
- RTS5260_DMA_RST_CTL_0
- RTS5260_DV331812_CFG
- RTS5260_DV331812_OCP_EN
- RTS5260_DV331812_OCP_THD_120
- RTS5260_DV331812_OCP_THD_140
- RTS5260_DV331812_OCP_THD_160
- RTS5260_DV331812_OCP_THD_180
- RTS5260_DV331812_OCP_THD_210
- RTS5260_DV331812_OCP_THD_240
- RTS5260_DV331812_OCP_THD_270
- RTS5260_DV331812_OCP_THD_300
- RTS5260_DV331812_OCP_THD_MASK
- RTS5260_DV331812_POWERON
- RTS5260_DV331812_SEL
- RTS5260_DV331812_VDD1
- RTS5260_DV331812_VDD2
- RTS5260_DVCC_33
- RTS5260_DVCC_CTRL
- RTS5260_DVCC_OCP_CL_EN
- RTS5260_DVCC_OCP_EN
- RTS5260_DVCC_OCP_THD_550
- RTS5260_DVCC_OCP_THD_970
- RTS5260_DVCC_OCP_THD_MASK
- RTS5260_DVCC_POWERON
- RTS5260_DVCC_TUNE_MASK
- RTS5260_DVIO_CTRL
- RTS5260_DVIO_OCP_CL_EN
- RTS5260_DVIO_OCP_EN
- RTS5260_DVIO_OCP_THD_250
- RTS5260_DVIO_OCP_THD_300
- RTS5260_DVIO_OCP_THD_350
- RTS5260_DVIO_OCP_THD_400
- RTS5260_DVIO_OCP_THD_450
- RTS5260_DVIO_OCP_THD_500
- RTS5260_DVIO_OCP_THD_550
- RTS5260_DVIO_OCP_THD_600
- RTS5260_DVIO_OCP_THD_MASK
- RTS5260_DVIO_POWERON
- RTS5260_MIMO_DISABLE
- RTS5260_REG_GPIO_CTL0
- RTS5260_REG_GPIO_MASK
- RTS5260_REG_GPIO_OFF
- RTS5260_REG_GPIO_ON
- RTS5_MARK
- RTS7_MARK
- RTSCTS_SH_CTS_MOD_TYPE
- RTSCTS_SH_CTS_PMB_TYPE
- RTSCTS_SH_CTS_RATE
- RTSCTS_SH_EXP_CTS_RATE
- RTSCTS_SH_RTS_MOD_TYPE
- RTSCTS_SH_RTS_PMB_TYPE
- RTSCTS_SH_RTS_RATE
- RTSCTS_TO_CONNECTOR
- RTSC_SUSP
- RTSDCTL_ENT_DLY_MASK
- RTSDCTL_ENT_DLY_MAX
- RTSDCTL_ENT_DLY_MIN
- RTSDCTL_ENT_DLY_SHIFT
- RTSDUR_AA
- RTSDUR_AA_F0
- RTSDUR_AA_F1
- RTSDUR_BA
- RTSDUR_BA_F0
- RTSDUR_BA_F1
- RTSDUR_BB
- RTSEL_DET50
- RTSEL_FIELD
- RTSEL_HLOCK
- RTSEL_MASK
- RTSEL_MONO
- RTSEL_RTCO
- RTSEL_SLOCK
- RTSEL_VLOCK
- RTSEL_VLOSS
- RTSFC_EN
- RTSIG_MAX
- RTSI_CLOCKING
- RTSI_SW_SHIFT_REG
- RTSI_SW_STROBE_REG
- RTSOFF_MASK
- RTSR
- RTSR_AL
- RTSR_ALE
- RTSR_HZ
- RTSR_HZE
- RTSR_PIAL
- RTSR_PIALE
- RTSR_PICE
- RTSR_RDAL1
- RTSR_RDAL2
- RTSR_RDALE1
- RTSR_RDALE2
- RTSR_SWAL1
- RTSR_SWAL2
- RTSR_SWALE1
- RTSR_SWALE2
- RTSR_TRIG_MASK
- RTSTOG_EN
- RTSXOFF
- RTSX_BIER
- RTSX_BIPR
- RTSX_CARD_DRIVE_DEFAULT
- RTSX_CLR_DELINK
- RTSX_FLIDX_ABORTING
- RTSX_FLIDX_DISCONNECTING
- RTSX_FLIDX_RESETTING
- RTSX_FLIDX_TIMED_OUT
- RTSX_FLIDX_TRANS_ACTIVE
- RTSX_HAIMR
- RTSX_HCBAR
- RTSX_HCBCTLR
- RTSX_HDBAR
- RTSX_HDBCTLR
- RTSX_INT
- RTSX_MSG_IN_INT
- RTSX_MS_CARD
- RTSX_PHASE_MAX
- RTSX_REG_PAIR
- RTSX_RESV_BUF_LEN
- RTSX_SD_CARD
- RTSX_SET_DELINK
- RTSX_SG_END
- RTSX_SG_INT
- RTSX_SG_LINK_DESC
- RTSX_SG_NO_OP
- RTSX_SG_TRANS_DATA
- RTSX_SG_VALID
- RTSX_SSC_DEPTH_1M
- RTSX_SSC_DEPTH_250K
- RTSX_SSC_DEPTH_2M
- RTSX_SSC_DEPTH_4M
- RTSX_SSC_DEPTH_500K
- RTSX_STAT
- RTSX_STAT_ABORT
- RTSX_STAT_DELINK
- RTSX_STAT_DISCONNECT
- RTSX_STAT_IDLE
- RTSX_STAT_INIT
- RTSX_STAT_RUN
- RTSX_STAT_SS
- RTSX_STAT_SUSPEND
- RTSX_TST_DELINK
- RTSX_USB_MS_CARD
- RTSX_USB_REQ_POLL
- RTSX_USB_REQ_REG_OP
- RTSX_USB_SD_CARD
- RTSX_USB_USE_LEDS_CLASS
- RTSYSTEMS_USB_29A_PID
- RTSYSTEMS_USB_29B_PID
- RTSYSTEMS_USB_29C_PID
- RTSYSTEMS_USB_29F_PID
- RTSYSTEMS_USB_57A_PID
- RTSYSTEMS_USB_57B_PID
- RTSYSTEMS_USB_59_PID
- RTSYSTEMS_USB_60_PID
- RTSYSTEMS_USB_61_PID
- RTSYSTEMS_USB_62B_PID
- RTSYSTEMS_USB_62_PID
- RTSYSTEMS_USB_63B_PID
- RTSYSTEMS_USB_63_PID
- RTSYSTEMS_USB_64_PID
- RTSYSTEMS_USB_65_PID
- RTSYSTEMS_USB_81B_PID
- RTSYSTEMS_USB_82B_PID
- RTSYSTEMS_USB_92D_PID
- RTSYSTEMS_USB_92_PID
- RTSYSTEMS_USB_A5R_PID
- RTSYSTEMS_USB_K4Y_PID
- RTSYSTEMS_USB_K5D_PID
- RTSYSTEMS_USB_K5G_PID
- RTSYSTEMS_USB_PW1_PID
- RTSYSTEMS_USB_S01_PID
- RTSYSTEMS_USB_S03_PID
- RTSYSTEMS_USB_S05_PID
- RTSYSTEMS_USB_VX8_PID
- RTSYSTEMS_USB_W5R_PID
- RTSYSTEMS_VID
- RTS_AT_AUART
- RTS_CTRL_IGNORE_LLC_CTRL
- RTS_CTRL_IGNORE_SNAP_OUI
- RTS_CTS
- RTS_DISABLED
- RTS_DIX_MAP_ETYPE
- RTS_DIX_MAP_SCW
- RTS_DS_MEM_CTRL_OFFSET
- RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED
- RTS_DS_MEM_CTRL_STROBE_NEW_CMD
- RTS_DS_MEM_CTRL_WE
- RTS_DS_MEM_DATA
- RTS_EN
- RTS_FlowCtl
- RTS_INVERT
- RTS_LEVEL_SHIFT_BITS
- RTS_MAX_TIMES_FREQ_REDUCTION
- RTS_OFF
- RTS_ON
- RTS_OP
- RTS_PN_CAM_CTRL_OFFSET
- RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED
- RTS_PN_CAM_CTRL_STROBE_NEW_CMD
- RTS_PN_CAM_CTRL_WE
- RTS_PN_CAM_DATA_PORT
- RTS_PN_CAM_DATA_SCW
- RTS_PN_CAM_DATA_TCP_SELECT
- RTS_RC_SHT
- RTS_THRESHOLD
- RTS_THRESHOLD_DEF
- RTS_THRESHOLD_MAX
- RTS_THRESHOLD_MIN
- RTS_THRESH_DEF
- RTS_THRESH_I
- RTS_TXB0
- RTS_TXB1
- RTS_TXB2
- RTT
- RTT3
- RTTAVG_INIT
- RTTDEV_INIT
- RTTDSCALE
- RTTR
- RTTSCALE
- RTT_ACCESS_TIMEOUT
- RTT_BAD_VALUE
- RTT_DONE
- RTT_INVALID
- RTT_MAX
- RTT_RESTORE_TIMEOUT
- RTT_VALID
- RTU
- RTV_RSP
- RTWS_ASYNC
- RTWS_BARRIER
- RTWS_COND_GET
- RTWS_COND_SYNC
- RTWS_DEF_FREE
- RTWS_DELAY
- RTWS_EXP_SYNC
- RTWS_FIXED_DELAY
- RTWS_IDLE
- RTWS_INIT
- RTWS_REPLACE
- RTWS_STOPPING
- RTWS_STUTTER
- RTWS_SYNC
- RTW_2GHZ_CH01_11
- RTW_2GHZ_CH12_13
- RTW_2G_CHANNELS_NUM
- RTW_5G_CHANNELS_NUM
- RTW_ALL_ON
- RTW_A_RATES_NUM
- RTW_BAND_2G
- RTW_BAND_5G
- RTW_BAND_60G
- RTW_BAND_MAX
- RTW_BC_MC_MACID
- RTW_CAM_AES
- RTW_CAM_NONE
- RTW_CAM_TKIP
- RTW_CAM_WEP104
- RTW_CAM_WEP40
- RTW_CANNOT_IO
- RTW_CANNOT_RX
- RTW_CANNOT_TX
- RTW_CCK_CS_ERR1
- RTW_CCK_CS_ERR2
- RTW_CCK_CS_MAX
- RTW_CCK_PD_MAX
- RTW_CHANNEL_SCAN_AMOUNT
- RTW_CHANNEL_WIDTH_10
- RTW_CHANNEL_WIDTH_160
- RTW_CHANNEL_WIDTH_20
- RTW_CHANNEL_WIDTH_40
- RTW_CHANNEL_WIDTH_5
- RTW_CHANNEL_WIDTH_80
- RTW_CHANNEL_WIDTH_80_80
- RTW_CHANNEL_WIDTH_MAX
- RTW_CHIP_TYPE_8822B
- RTW_CHIP_TYPE_8822C
- RTW_CHIP_VER_CUT_A
- RTW_CHIP_VER_CUT_B
- RTW_CHIP_VER_CUT_C
- RTW_CHIP_VER_CUT_D
- RTW_CHIP_VER_CUT_E
- RTW_CHIP_VER_CUT_F
- RTW_CHIP_VER_CUT_G
- RTW_CHPLAN_ETSI1_ETSI12
- RTW_CHPLAN_ETSI1_ETSI4
- RTW_CHPLAN_ETSI1_NULL
- RTW_CHPLAN_FCC1_FCC7
- RTW_CHPLAN_FCC1_NCC3
- RTW_CHPLAN_FCC2_FCC1
- RTW_CHPLAN_FCC2_FCC11
- RTW_CHPLAN_FCC2_FCC17
- RTW_CHPLAN_FCC2_FCC7
- RTW_CHPLAN_IC1_IC2
- RTW_CHPLAN_KCC1_KCC2
- RTW_CHPLAN_KCC1_KCC3
- RTW_CHPLAN_MKK1_MKK1
- RTW_CHPLAN_REALTEK_DEFINE
- RTW_CHPLAN_WORLD_ACMA1
- RTW_CHPLAN_WORLD_CHILE1
- RTW_CHPLAN_WORLD_ETSI1
- RTW_CHPLAN_WORLD_ETSI10
- RTW_CHPLAN_WORLD_ETSI14
- RTW_CHPLAN_WORLD_ETSI15
- RTW_CHPLAN_WORLD_ETSI2
- RTW_CHPLAN_WORLD_ETSI20
- RTW_CHPLAN_WORLD_ETSI3
- RTW_CHPLAN_WORLD_ETSI6
- RTW_CHPLAN_WORLD_ETSI7
- RTW_CHPLAN_WORLD_ETSI8
- RTW_CHPLAN_WORLD_FCC3
- RTW_CHPLAN_WORLD_FCC5
- RTW_CHPLAN_WORLD_FCC7
- RTW_CMDF_DIRECTLY
- RTW_CMDF_WAIT_ACK
- RTW_DBGDUMP
- RTW_DBG_ALL
- RTW_DBG_COEX
- RTW_DBG_DEBUGFS
- RTW_DBG_EFUSE
- RTW_DBG_FW
- RTW_DBG_PCI
- RTW_DBG_PHY
- RTW_DBG_REGD
- RTW_DBG_RFK
- RTW_DBG_RX
- RTW_DBG_TX
- RTW_DECL_TABLE_BB_PG
- RTW_DECL_TABLE_DPK
- RTW_DECL_TABLE_PHY_COND
- RTW_DECL_TABLE_PHY_COND_CORE
- RTW_DECL_TABLE_RF_RADIO
- RTW_DECL_TABLE_TXPWR_LMT
- RTW_DEF_RFE
- RTW_DISABLE_FUNC
- RTW_DMA_MAPPING_EXTRA
- RTW_DMA_MAPPING_HIGH
- RTW_DMA_MAPPING_LOW
- RTW_DMA_MAPPING_NORMAL
- RTW_DMA_MAPPING_UNDEF
- RTW_DPD_RATE_CHECK
- RTW_DPK_ACTION_MAX
- RTW_DPK_AGC_OUT
- RTW_DPK_CAL_PWR
- RTW_DPK_DAGC
- RTW_DPK_DO_DPK
- RTW_DPK_DPK_ON
- RTW_DPK_GAIN_CHECK
- RTW_DPK_GAIN_LARGE
- RTW_DPK_GAIN_LESS
- RTW_DPK_GAIN_LOSS
- RTW_DPK_GL_LARGE
- RTW_DPK_GL_LESS
- RTW_DPK_LOSS_CHECK
- RTW_EFUSE_BANK_WIFI
- RTW_ENABLE_FUNC
- RTW_ERP_INFO_BARKER_PREAMBLE_MODE
- RTW_ERP_INFO_NON_ERP_PRESENT
- RTW_ERP_INFO_USE_PROTECTION
- RTW_FLAG_BUSY_TRAFFIC
- RTW_FLAG_DIG_DISABLE
- RTW_FLAG_FW_RUNNING
- RTW_FLAG_INACTIVE_PS
- RTW_FLAG_LEISURE_PS
- RTW_FLAG_RUNNING
- RTW_FLAG_SCANNING
- RTW_GET_BE16
- RTW_GET_BE24
- RTW_GET_BE32
- RTW_GET_BE64
- RTW_GET_LE16
- RTW_GET_LE32
- RTW_GET_LE64
- RTW_GSPI
- RTW_G_RATES_NUM
- RTW_HCI_TYPE_PCIE
- RTW_HCI_TYPE_SDIO
- RTW_HCI_TYPE_UNDEFINE
- RTW_HCI_TYPE_USB
- RTW_HIQ_FILTER_ALLOW_ALL
- RTW_HIQ_FILTER_ALLOW_SPECIAL
- RTW_HIQ_FILTER_DENY_ALL
- RTW_HW_PORT_NUM
- RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK
- RTW_IEEE80211_CHAN_DISABLED
- RTW_IEEE80211_CHAN_NO_HT40
- RTW_IEEE80211_CHAN_NO_HT40MINUS
- RTW_IEEE80211_CHAN_NO_HT40PLUS
- RTW_IEEE80211_CHAN_NO_IBSS
- RTW_IEEE80211_CHAN_PASSIVE_SCAN
- RTW_IEEE80211_CHAN_RADAR
- RTW_IEEE80211_SCTL_FRAG
- RTW_IEEE80211_SCTL_SEQ
- RTW_INTF_PHY_CUT_A
- RTW_INTF_PHY_CUT_ALL
- RTW_INTF_PHY_CUT_B
- RTW_INTF_PHY_CUT_C
- RTW_INTF_PHY_CUT_D
- RTW_INTF_PHY_CUT_E
- RTW_INTF_PHY_CUT_F
- RTW_INTF_PHY_CUT_G
- RTW_INTF_PHY_PLATFORM_ALL
- RTW_IP_SEL_DBI
- RTW_IP_SEL_MAC
- RTW_IP_SEL_PHY
- RTW_IP_SEL_UNDEF
- RTW_IS_FUNC_DISABLED
- RTW_KCK_LEN
- RTW_KEK_LEN
- RTW_LED_OFF
- RTW_LED_ON
- RTW_LPS_THRESHOLD
- RTW_MAX_CHANNEL_NUM_2G
- RTW_MAX_CHANNEL_NUM_5G
- RTW_MAX_CHANNEL_WIDTH
- RTW_MAX_MAC_ID_NUM
- RTW_MAX_MGMT_TX_CNT
- RTW_MAX_NUM_PMKIDS
- RTW_MAX_REMAIN_ON_CHANNEL_DURATION
- RTW_MAX_SEC_CAM_NUM
- RTW_MODE_ACTIVE
- RTW_MODE_LPS
- RTW_MODE_WMM_PS
- RTW_NET_AD_HOC
- RTW_NET_AP_MODE
- RTW_NET_MGD_LINKED
- RTW_NET_NO_LINK
- RTW_NOTCH_FILTER
- RTW_ODM_ABILITY_MAX
- RTW_ODM_COMP_MAX
- RTW_ODM_DBG_LEVEL_NUM
- RTW_PCIE
- RTW_PQ_MAP_BE
- RTW_PQ_MAP_BK
- RTW_PQ_MAP_HI
- RTW_PQ_MAP_MG
- RTW_PQ_MAP_NUM
- RTW_PQ_MAP_UNDEF
- RTW_PQ_MAP_VI
- RTW_PQ_MAP_VO
- RTW_PUT_BE16
- RTW_PUT_BE24
- RTW_PUT_BE32
- RTW_PUT_BE64
- RTW_PUT_LE16
- RTW_PUT_LE32
- RTW_PWR_ADDR_MAC
- RTW_PWR_ADDR_PCIE
- RTW_PWR_ADDR_SDIO
- RTW_PWR_ADDR_USB
- RTW_PWR_CMD_DELAY
- RTW_PWR_CMD_END
- RTW_PWR_CMD_POLLING
- RTW_PWR_CMD_READ
- RTW_PWR_CMD_WRITE
- RTW_PWR_CUT_ALL_MSK
- RTW_PWR_CUT_A_MSK
- RTW_PWR_CUT_B_MSK
- RTW_PWR_CUT_C_MSK
- RTW_PWR_CUT_D_MSK
- RTW_PWR_CUT_E_MSK
- RTW_PWR_CUT_F_MSK
- RTW_PWR_CUT_G_MSK
- RTW_PWR_DELAY_MS
- RTW_PWR_DELAY_US
- RTW_PWR_INTF_ALL_MSK
- RTW_PWR_INTF_PCI_MSK
- RTW_PWR_INTF_SDIO_MSK
- RTW_PWR_INTF_USB_MSK
- RTW_PWR_POLLING_CNT
- RTW_PWR_STATE_CHK_INTERVAL
- RTW_RATEID_ARFR0_AC_2SS
- RTW_RATEID_ARFR1_AC_1SS
- RTW_RATEID_ARFR2_AC_2G_1SS
- RTW_RATEID_ARFR3_AC_2G_2SS
- RTW_RATEID_ARFR4_AC_3SS
- RTW_RATEID_ARFR5_N_3SS
- RTW_RATEID_ARFR6_AC_4SS
- RTW_RATEID_ARFR7_N_4SS
- RTW_RATEID_BG
- RTW_RATEID_BGN_20M_1SS
- RTW_RATEID_BGN_20M_2SS
- RTW_RATEID_BGN_40M_1SS
- RTW_RATEID_BGN_40M_2SS
- RTW_RATEID_B_20M
- RTW_RATEID_G
- RTW_RATEID_GN_N1SS
- RTW_RATEID_GN_N2SS
- RTW_RATE_SECTION_CCK
- RTW_RATE_SECTION_HT_1S
- RTW_RATE_SECTION_HT_2S
- RTW_RATE_SECTION_MAX
- RTW_RATE_SECTION_OFDM
- RTW_RATE_SECTION_VHT_1S
- RTW_RATE_SECTION_VHT_2S
- RTW_REGD_ACMA
- RTW_REGD_CHILE
- RTW_REGD_ETSI
- RTW_REGD_FCC
- RTW_REGD_IC
- RTW_REGD_KCC
- RTW_REGD_MAX
- RTW_REGD_MEXICO
- RTW_REGD_MKK
- RTW_REGD_UKRAINE
- RTW_REGD_WW
- RTW_REPLAY_CTR_LEN
- RTW_RFE_EFEM
- RTW_RFE_IFEM
- RTW_RFE_IFEM2G_EFEM5G
- RTW_RFE_NUM
- RTW_RF_OFF
- RTW_RF_ON
- RTW_RF_PATH_MAX
- RTW_ROAM_ACTIVE
- RTW_ROAM_ON_EXPIRED
- RTW_ROAM_ON_RESUME
- RTW_ROAM_RSSI_DIFF_TH
- RTW_ROAM_SCAN_INTERVAL_MS
- RTW_ROAM_SCAN_RESULT_EXP_MS
- RTW_RX_HANDLED
- RTW_RX_QUEUE_C2H
- RTW_RX_QUEUE_MPDU
- RTW_SCAN_IE_LEN_MAX
- RTW_SCAN_RESULT_EXPIRE
- RTW_SCTX_DONE_BUF_ALLOC
- RTW_SCTX_DONE_BUF_FREE
- RTW_SCTX_DONE_CCX_PKT_FAIL
- RTW_SCTX_DONE_CMD_ERROR
- RTW_SCTX_DONE_DEV_REMOVE
- RTW_SCTX_DONE_DRV_STOP
- RTW_SCTX_DONE_SUCCESS
- RTW_SCTX_DONE_TIMEOUT
- RTW_SCTX_DONE_TX_DENY
- RTW_SCTX_DONE_TX_DESC_NA
- RTW_SCTX_DONE_UNKNOWN
- RTW_SCTX_DONE_WRITE_PORT_ERR
- RTW_SCTX_SUBMITTED
- RTW_SDIO
- RTW_SEC_CAM_ENTRY_SHIFT
- RTW_SEC_CMD_CLEAR
- RTW_SEC_CMD_POLLING
- RTW_SEC_CMD_REG
- RTW_SEC_CMD_WRITE_ENABLE
- RTW_SEC_CONFIG
- RTW_SEC_DEFAULT_KEY_NUM
- RTW_SEC_ENGINE_EN
- RTW_SEC_READ_REG
- RTW_SEC_RX_BC_USE_DK
- RTW_SEC_RX_DEC_EN
- RTW_SEC_RX_UNI_USE_DK
- RTW_SEC_TX_BC_USE_DK
- RTW_SEC_TX_DEC_EN
- RTW_SEC_TX_UNI_USE_DK
- RTW_SEC_WRITE_REG
- RTW_SSID_SCAN_AMOUNT
- RTW_STATUS_CODE
- RTW_TX_PROBE_TIMEOUT
- RTW_TX_QUEUE_BCN
- RTW_TX_QUEUE_BE
- RTW_TX_QUEUE_BK
- RTW_TX_QUEUE_H2C
- RTW_TX_QUEUE_HI0
- RTW_TX_QUEUE_MGMT
- RTW_TX_QUEUE_VI
- RTW_TX_QUEUE_VO
- RTW_USB
- RTW_USB_BULKOUT_TIME
- RTW_USB_CONTROL_MSG_TIMEOUT
- RTW_USB_CONTROL_MSG_TIMEOUT_TEST
- RTW_WATCH_DOG_DELAY_TIME
- RTW_WLAN_ACTION_ADDBA_REQ
- RTW_WLAN_ACTION_ADDBA_RESP
- RTW_WLAN_ACTION_ASEL_INDICATES_FB
- RTW_WLAN_ACTION_DELBA
- RTW_WLAN_ACTION_HI_INFO_EXCHG
- RTW_WLAN_ACTION_HT_ASEL_FEEDBACK
- RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING
- RTW_WLAN_ACTION_HT_CSI
- RTW_WLAN_ACTION_HT_NON_COMPRESS_BEAMFORMING
- RTW_WLAN_ACTION_HT_NOTI_CHNL_WIDTH
- RTW_WLAN_ACTION_HT_PSMP
- RTW_WLAN_ACTION_HT_SET_PCO_PHASE
- RTW_WLAN_ACTION_HT_SM_PS
- RTW_WLAN_ACTION_MIMO_CSI_MX
- RTW_WLAN_ACTION_MIMO_NONCP_BF
- RTW_WLAN_ACTION_MIMP_CP_BF
- RTW_WLAN_ACTION_NOTIFY_CH_WIDTH
- RTW_WLAN_ACTION_PCO_PHASE
- RTW_WLAN_ACTION_PSPM
- RTW_WLAN_ACTION_SM_PS
- RTW_WLAN_ACTION_SPCT_CHL_SWITCH
- RTW_WLAN_ACTION_SPCT_EXT_CHL_SWITCH
- RTW_WLAN_ACTION_SPCT_MSR_REQ
- RTW_WLAN_ACTION_SPCT_MSR_RPRT
- RTW_WLAN_ACTION_SPCT_TPC_REQ
- RTW_WLAN_ACTION_SPCT_TPC_RPRT
- RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING
- RTW_WLAN_ACTION_VHT_GROUPID_MANAGEMENT
- RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION
- RTW_WLAN_BACK_INITIATOR
- RTW_WLAN_BACK_RECIPIENT
- RTW_WLAN_BACK_TIMER
- RTW_WLAN_CATEGORY_BACK
- RTW_WLAN_CATEGORY_DLS
- RTW_WLAN_CATEGORY_FT
- RTW_WLAN_CATEGORY_HT
- RTW_WLAN_CATEGORY_P2P
- RTW_WLAN_CATEGORY_PUBLIC
- RTW_WLAN_CATEGORY_QOS
- RTW_WLAN_CATEGORY_RADIO_MEASUREMENT
- RTW_WLAN_CATEGORY_SA_QUERY
- RTW_WLAN_CATEGORY_SELF_PROTECTED
- RTW_WLAN_CATEGORY_SPECTRUM_MGMT
- RTW_WLAN_CATEGORY_TDLS
- RTW_WLAN_CATEGORY_UNPROTECTED_WNM
- RTW_WLAN_CATEGORY_VHT
- RTW_WLAN_CATEGORY_WMM
- RTXAGC_A_CCK11_CCK1
- RTXAGC_A_CCK1_MCS32
- RTXAGC_A_MCS03_MCS00
- RTXAGC_A_MCS07_MCS04
- RTXAGC_A_MCS11_MCS08
- RTXAGC_A_MCS15_MCS12
- RTXAGC_A_NSS1INDEX3_NSS1INDEX0
- RTXAGC_A_NSS1INDEX7_NSS1INDEX4
- RTXAGC_A_NSS2INDEX1_NSS1INDEX8
- RTXAGC_A_NSS2INDEX5_NSS2INDEX2
- RTXAGC_A_NSS2INDEX9_NSS2INDEX6
- RTXAGC_A_OFDM18_OFDM6
- RTXAGC_A_OFDM54_OFDM24
- RTXAGC_A_RATE18_06
- RTXAGC_A_RATE54_24
- RTXAGC_B_CCK11_A_CCK2_11
- RTXAGC_B_CCK11_CCK1
- RTXAGC_B_CCK1_55_MCS32
- RTXAGC_B_MCS03_MCS00
- RTXAGC_B_MCS07_MCS04
- RTXAGC_B_MCS11_MCS08
- RTXAGC_B_MCS15_MCS12
- RTXAGC_B_NSS1INDEX3_NSS1INDEX0
- RTXAGC_B_NSS1INDEX7_NSS1INDEX4
- RTXAGC_B_NSS2INDEX1_NSS1INDEX8
- RTXAGC_B_NSS2INDEX5_NSS2INDEX2
- RTXAGC_B_NSS2INDEX9_NSS2INDEX6
- RTXAGC_B_OFDM18_OFDM6
- RTXAGC_B_OFDM54_OFDM24
- RTXAGC_B_RATE18_06
- RTXAGC_B_RATE54_24
- RTXAGC_CCK_MCS32
- RTXAGC_MCS03_MCS00
- RTXAGC_MCS07_MCS04
- RTXAGC_MCS11_MCS08
- RTXAGC_MCS15_MCS12
- RTXAGC_RATE18_06
- RTXAGC_RATE54_24
- RTXPATH
- RTX_CCK_BBON
- RTX_CCK_RFON
- RTX_IQK
- RTX_IQK_PI_A
- RTX_IQK_PI_B
- RTX_IQK_TONE_A
- RTX_IQK_TONE_B
- RTX_OFDM_BBON
- RTX_OFDM_RFON
- RTX_POWER_AFTER_IQK_A
- RTX_POWER_AFTER_IQK_B
- RTX_POWER_BEFORE_IQK_A
- RTX_POWER_BEFORE_IQK_B
- RTX_TO_RX
- RTX_TO_TX
- RTYCLR
- RTYMSK
- RTYRCH
- RTYVAL
- RTYVAL_MASK
- RTY_LMT_EN
- RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE
- RT_8192S_FIRMWARE_HDR_SIZE
- RT_AC_INT_MASKS
- RT_ADDR_SHIFT
- RT_ALIGNEDSZ
- RT_AMPDU_BURST
- RT_AMPDU_BURST_8723B
- RT_AMPDU_BURST_8812_12
- RT_AMPDU_BURST_8812_15
- RT_AMPDU_BURST_8812_4
- RT_AMPDU_BURST_8812_8
- RT_AMPDU_BURST_88E
- RT_AMPDU_BURST_92D
- RT_AMPDU_BURST_NONE
- RT_AR_DELTA
- RT_ASOC_RETRY_LIMIT
- RT_AWB_SPINLOCK
- RT_BTData_SPINLOCK
- RT_BUFFER_SPINLOCK
- RT_BW_SPINLOCK
- RT_CACHE_STAT_INC
- RT_CAM_SPINLOCK
- RT_CANNOT_IO
- RT_CCK_PAGEA_SPINLOCK
- RT_CHANNEL_AND_BANDWIDTH_SPINLOCK
- RT_CHANNEL_DOMAIN
- RT_CHANNEL_DOMAIN_2G
- RT_CHANNEL_DOMAIN_2G_ETSI1
- RT_CHANNEL_DOMAIN_2G_ETSI2
- RT_CHANNEL_DOMAIN_2G_FCC1
- RT_CHANNEL_DOMAIN_2G_GLOBAL
- RT_CHANNEL_DOMAIN_2G_MAX
- RT_CHANNEL_DOMAIN_2G_MKK1
- RT_CHANNEL_DOMAIN_2G_NULL
- RT_CHANNEL_DOMAIN_2G_WORLD
- RT_CHANNEL_DOMAIN_5G
- RT_CHANNEL_DOMAIN_5G_40M
- RT_CHANNEL_DOMAIN_5G_ETSI1
- RT_CHANNEL_DOMAIN_5G_ETSI10
- RT_CHANNEL_DOMAIN_5G_ETSI11
- RT_CHANNEL_DOMAIN_5G_ETSI12
- RT_CHANNEL_DOMAIN_5G_ETSI13
- RT_CHANNEL_DOMAIN_5G_ETSI2
- RT_CHANNEL_DOMAIN_5G_ETSI3
- RT_CHANNEL_DOMAIN_5G_ETSI4
- RT_CHANNEL_DOMAIN_5G_ETSI5
- RT_CHANNEL_DOMAIN_5G_ETSI6
- RT_CHANNEL_DOMAIN_5G_ETSI7
- RT_CHANNEL_DOMAIN_5G_ETSI8
- RT_CHANNEL_DOMAIN_5G_ETSI9
- RT_CHANNEL_DOMAIN_5G_FCC
- RT_CHANNEL_DOMAIN_5G_FCC1
- RT_CHANNEL_DOMAIN_5G_FCC10
- RT_CHANNEL_DOMAIN_5G_FCC2
- RT_CHANNEL_DOMAIN_5G_FCC3
- RT_CHANNEL_DOMAIN_5G_FCC4
- RT_CHANNEL_DOMAIN_5G_FCC4_NO_DFS
- RT_CHANNEL_DOMAIN_5G_FCC5
- RT_CHANNEL_DOMAIN_5G_FCC6
- RT_CHANNEL_DOMAIN_5G_FCC7_IC1
- RT_CHANNEL_DOMAIN_5G_FCC8
- RT_CHANNEL_DOMAIN_5G_FCC9
- RT_CHANNEL_DOMAIN_5G_JAPAN_NO_DFS
- RT_CHANNEL_DOMAIN_5G_KCC1
- RT_CHANNEL_DOMAIN_5G_MAX
- RT_CHANNEL_DOMAIN_5G_MKK1
- RT_CHANNEL_DOMAIN_5G_MKK2
- RT_CHANNEL_DOMAIN_5G_MKK3
- RT_CHANNEL_DOMAIN_5G_NCC1
- RT_CHANNEL_DOMAIN_5G_NCC2
- RT_CHANNEL_DOMAIN_5G_NCC3
- RT_CHANNEL_DOMAIN_5G_NCC4
- RT_CHANNEL_DOMAIN_5G_NULL
- RT_CHANNEL_DOMAIN_CHINA
- RT_CHANNEL_DOMAIN_ETSI
- RT_CHANNEL_DOMAIN_ETSI1_ETSI4
- RT_CHANNEL_DOMAIN_ETSI1_NULL
- RT_CHANNEL_DOMAIN_ETSI2_NULL
- RT_CHANNEL_DOMAIN_FCC
- RT_CHANNEL_DOMAIN_FCC1_FCC1
- RT_CHANNEL_DOMAIN_FCC1_FCC10
- RT_CHANNEL_DOMAIN_FCC1_FCC2
- RT_CHANNEL_DOMAIN_FCC1_FCC7
- RT_CHANNEL_DOMAIN_FCC1_FCC8
- RT_CHANNEL_DOMAIN_FCC1_FCC9
- RT_CHANNEL_DOMAIN_FCC1_NCC1
- RT_CHANNEL_DOMAIN_FCC1_NCC2
- RT_CHANNEL_DOMAIN_FCC1_NCC3
- RT_CHANNEL_DOMAIN_FCC1_NCC4
- RT_CHANNEL_DOMAIN_FCC1_NULL
- RT_CHANNEL_DOMAIN_FCC_NO_DFS
- RT_CHANNEL_DOMAIN_FRANCE
- RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN
- RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN_2G
- RT_CHANNEL_DOMAIN_GLOBAL_NULL
- RT_CHANNEL_DOMAIN_IC
- RT_CHANNEL_DOMAIN_ISRAEL
- RT_CHANNEL_DOMAIN_JAPAN
- RT_CHANNEL_DOMAIN_JAPAN_NO_DFS
- RT_CHANNEL_DOMAIN_KOREA
- RT_CHANNEL_DOMAIN_MAX
- RT_CHANNEL_DOMAIN_MIC
- RT_CHANNEL_DOMAIN_MKK
- RT_CHANNEL_DOMAIN_MKK1
- RT_CHANNEL_DOMAIN_MKK1_MKK1
- RT_CHANNEL_DOMAIN_MKK1_MKK2
- RT_CHANNEL_DOMAIN_MKK1_MKK3
- RT_CHANNEL_DOMAIN_MKK1_NULL
- RT_CHANNEL_DOMAIN_NCC
- RT_CHANNEL_DOMAIN_REALTEK_DEFINE
- RT_CHANNEL_DOMAIN_SINGAPORE_INDIA_MEXICO
- RT_CHANNEL_DOMAIN_SPAIN
- RT_CHANNEL_DOMAIN_TAIWAN
- RT_CHANNEL_DOMAIN_TAIWAN_NO_DFS
- RT_CHANNEL_DOMAIN_TELEC
- RT_CHANNEL_DOMAIN_TELEC_NETGEAR
- RT_CHANNEL_DOMAIN_TURKEY
- RT_CHANNEL_DOMAIN_WORLD_ETSI1
- RT_CHANNEL_DOMAIN_WORLD_ETSI10
- RT_CHANNEL_DOMAIN_WORLD_ETSI11
- RT_CHANNEL_DOMAIN_WORLD_ETSI12
- RT_CHANNEL_DOMAIN_WORLD_ETSI13
- RT_CHANNEL_DOMAIN_WORLD_ETSI2
- RT_CHANNEL_DOMAIN_WORLD_ETSI3
- RT_CHANNEL_DOMAIN_WORLD_ETSI5
- RT_CHANNEL_DOMAIN_WORLD_ETSI6
- RT_CHANNEL_DOMAIN_WORLD_ETSI7
- RT_CHANNEL_DOMAIN_WORLD_ETSI8
- RT_CHANNEL_DOMAIN_WORLD_ETSI9
- RT_CHANNEL_DOMAIN_WORLD_FCC2
- RT_CHANNEL_DOMAIN_WORLD_FCC3
- RT_CHANNEL_DOMAIN_WORLD_FCC4
- RT_CHANNEL_DOMAIN_WORLD_FCC5
- RT_CHANNEL_DOMAIN_WORLD_FCC6
- RT_CHANNEL_DOMAIN_WORLD_KCC1
- RT_CHANNEL_DOMAIN_WORLD_NULL
- RT_CHANNEL_DOMAIN_WORLD_WIDE_13
- RT_CHANNEL_DOMAIN_WORLD_WIDE_5G
- RT_CHANNEL_IDS
- RT_CHANNEL_INFO
- RT_CHANNEL_PLAN
- RT_CHANNEL_PLAN_2G
- RT_CHANNEL_PLAN_5G
- RT_CHANNEL_PLAN_MAP
- RT_CHECK_FOR_HANG_PERIOD
- RT_CHNLLIST_SPINLOCK
- RT_CHNLOP_SPINLOCK
- RT_CID_8187_ALPHA0
- RT_CID_8187_HW_LED
- RT_CID_8187_NETGEAR
- RT_CID_8187_SERCOMM_PS
- RT_CID_819X_ACER
- RT_CID_819X_ALPHA
- RT_CID_819X_ARCADYAN_BELKIN
- RT_CID_819X_CAMEO
- RT_CID_819X_CAMEO1
- RT_CID_819X_CLEVO
- RT_CID_819X_DELL
- RT_CID_819X_EDIMAX_ASUS
- RT_CID_819X_EDIMAX_BELKIN
- RT_CID_819X_FOXCOON
- RT_CID_819X_HP
- RT_CID_819X_LENOVO
- RT_CID_819X_MSI
- RT_CID_819X_NETCORE
- RT_CID_819X_PRONETS
- RT_CID_819X_QMI
- RT_CID_819X_RUNTOP
- RT_CID_819X_SAMSUNG
- RT_CID_819X_SENAO
- RT_CID_819X_SERCOMM_BELKIN
- RT_CID_819X_SITECOM
- RT_CID_819X_WNC_COREGA
- RT_CID_819x_ALPHA
- RT_CID_819x_ALPHA_Dlink
- RT_CID_819x_ALPHA_WD
- RT_CID_819x_Acer
- RT_CID_819x_Arcadyan_Belkin
- RT_CID_819x_AzWave
- RT_CID_819x_AzWave_ASUS
- RT_CID_819x_CAMEO
- RT_CID_819x_CAMEO1
- RT_CID_819x_CAMEO_NETGEAR
- RT_CID_819x_CLEVO
- RT_CID_819x_DELL
- RT_CID_819x_Edimax_ASUS
- RT_CID_819x_Edimax_Belkin
- RT_CID_819x_FUNAI_TV
- RT_CID_819x_HP
- RT_CID_819x_Lenovo
- RT_CID_819x_MSI
- RT_CID_819x_Netcore
- RT_CID_819x_PRONETS
- RT_CID_819x_QMI
- RT_CID_819x_RUNTOP
- RT_CID_819x_SAMSUNG
- RT_CID_819x_Senao
- RT_CID_819x_Sercomm_Belkin
- RT_CID_819x_Sercomm_Netgear
- RT_CID_819x_Sitecom
- RT_CID_819x_WNC_COREGA
- RT_CID_819x_Xavi
- RT_CID_CCX
- RT_CID_CC_C
- RT_CID_CHINA_MOBILE
- RT_CID_COREGA
- RT_CID_DEFAULT
- RT_CID_DLINK
- RT_CID_DNI_BUFFALO
- RT_CID_INTEL_CHINA
- RT_CID_LENOVO_CHINA
- RT_CID_NETGEAR
- RT_CID_NETTRONIX
- RT_CID_Nettronix
- RT_CID_PLANEX
- RT_CID_PRONET
- RT_CID_TOSHIBA
- RT_CID_TPLINK_HPWR
- RT_CID_WHQL
- RT_CID_WNC_NEC
- RT_CLEAR_PS_LEVEL
- RT_CLIENT
- RT_CLKCFG1_UPHY0_CLK_EN
- RT_CLKCFG1_UPHY1_CLK_EN
- RT_CONN_FLAGS
- RT_CONN_FLAGS_TOS
- RT_CUSTOMER_ID
- RT_DATA
- RT_DBG_SPIN_LOCK
- RT_DEBUG_DATA
- RT_DISC_REQ
- RT_DISP
- RT_D_CFGS_PER_BANK
- RT_D_CFG_CLKNOTDATA_MASK
- RT_D_CFG_CLKNOTDATA_SHIFT
- RT_D_CFG_CLK_MASK
- RT_D_CFG_CLK_SHIFT
- RT_D_CFG_DELAY_INNOTOUT_MASK
- RT_D_CFG_DELAY_INNOTOUT_SHIFT
- RT_D_CFG_DELAY_MASK
- RT_D_CFG_DELAY_SHIFT
- RT_D_CFG_DOUBLE_EDGE_MASK
- RT_D_CFG_DOUBLE_EDGE_SHIFT
- RT_D_CFG_INVERTCLK_MASK
- RT_D_CFG_INVERTCLK_SHIFT
- RT_D_CFG_RETIME_MASK
- RT_D_CFG_RETIME_SHIFT
- RT_EEPROM_TYPE
- RT_FLAG_RESHAPE_RS
- RT_FLAG_RS_BITMAP_LOADED
- RT_FLAG_RS_IN_SYNC
- RT_FLAG_RS_PRERESUMED
- RT_FLAG_RS_RESUMED
- RT_FLAG_RS_RESYNCING
- RT_FLAG_RS_SUSPENDED
- RT_FLAG_UPDATE_SBS
- RT_FL_TOS
- RT_FW_PS_SPINLOCK
- RT_GC_TIMEOUT
- RT_GEN_TEMP_BUF_SPINLOCK
- RT_GetInterfaceSelection
- RT_H2C_SPINLOCK
- RT_HIGH_THROUGHPUT
- RT_HT_CAP_USE_88C_92C
- RT_HT_CAP_USE_92SE
- RT_HT_CAP_USE_AMPDU
- RT_HT_CAP_USE_AP_CLIENT_MODE
- RT_HT_CAP_USE_JAGUAR_BCUT
- RT_HT_CAP_USE_JAGUAR_CCUT
- RT_HT_CAP_USE_LONG_PREAMBLE
- RT_HT_CAP_USE_SOFTAP
- RT_HT_CAP_USE_TURBO_AGGR
- RT_HT_CAP_USE_VIDEO_CLIENT
- RT_HT_CAP_USE_WOW
- RT_HT_INF0_CAPBILITY
- RT_HT_INF1_CAPBILITY
- RT_HW_TIMER_SPIN_LOCK
- RT_IDX
- RT_IDX_802_3
- RT_IDX_ALLMULTI_SLOT
- RT_IDX_ALL_ERR_SLOT
- RT_IDX_BCAST
- RT_IDX_BCAST_MCAST_MATCH
- RT_IDX_BCAST_SLOT
- RT_IDX_CAM_BIT0
- RT_IDX_CAM_BIT1
- RT_IDX_CAM_HIT
- RT_IDX_CAM_HIT_SLOT
- RT_IDX_DST_CAM_Q
- RT_IDX_DST_COS_Q
- RT_IDX_DST_DEST_Q
- RT_IDX_DST_DFLT_Q
- RT_IDX_DST_MASK
- RT_IDX_DST_RSS
- RT_IDX_DUMP_ENTRIES
- RT_IDX_DUMP_TOT_WORDS
- RT_IDX_DUMP_WORDS_PER_ENTRY
- RT_IDX_E
- RT_IDX_ERR
- RT_IDX_ETH_FCOE
- RT_IDX_ETH_SKIP1
- RT_IDX_ETH_SKIP2
- RT_IDX_FC_MACH
- RT_IDX_IDX_SHIFT
- RT_IDX_IP_CSUM_ERR
- RT_IDX_IP_CSUM_ERR_SLOT
- RT_IDX_LLDP
- RT_IDX_MAC_ERR
- RT_IDX_MAC_ERR_SLOT
- RT_IDX_MAX_NIC_SLOTS
- RT_IDX_MAX_RT_SLOTS
- RT_IDX_MCAST
- RT_IDX_MCAST_HASH_MATCH
- RT_IDX_MCAST_MATCH
- RT_IDX_MCAST_MATCH_SLOT
- RT_IDX_MCAST_REG_MATCH
- RT_IDX_MR
- RT_IDX_MW
- RT_IDX_PROMISCUOUS_SLOT
- RT_IDX_RS
- RT_IDX_RSS_IPV4
- RT_IDX_RSS_IPV4_SLOT
- RT_IDX_RSS_IPV6
- RT_IDX_RSS_IPV6_SLOT
- RT_IDX_RSS_MATCH
- RT_IDX_RSS_MATCH_SLOT
- RT_IDX_RSS_TCP4
- RT_IDX_RSS_TCP4_SLOT
- RT_IDX_RSS_TCP6
- RT_IDX_RSS_TCP6_SLOT
- RT_IDX_TCP_UDP_CSUM_ERR_SLOT
- RT_IDX_TU_CSUM_ERR
- RT_IDX_TYPE_MASK
- RT_IDX_TYPE_NICQ
- RT_IDX_TYPE_NICQ_INV
- RT_IDX_TYPE_RT
- RT_IDX_TYPE_RT_INV
- RT_IDX_TYPE_SHIFT
- RT_IDX_UNUSED013
- RT_IDX_UNUSED014
- RT_IDX_UNUSED018
- RT_IDX_UNUSED019
- RT_IDX_UNUSED20
- RT_IDX_UNUSED21
- RT_IDX_UNUSED6_SLOT
- RT_IDX_UNUSED7_SLOT
- RT_IDX_VALID
- RT_IDX_VLAN_FILTER
- RT_IDX_VLAN_MATCH
- RT_IDX_VLAN_TAG
- RT_INDIC_SPINLOCK
- RT_INITIAL_SPINLOCK
- RT_INI_REQ
- RT_IN_PS_LEVEL
- RT_IQK_SPINLOCK
- RT_JOIN_ACTION
- RT_JOIN_IBSS
- RT_JOIN_INFRA
- RT_LDO_REGULATOR
- RT_LINK_DETECT_T
- RT_LOCK
- RT_LOG_SPINLOCK
- RT_MAN_CTRL_RT
- RT_MAN_CTRL_RT_A
- RT_MAN_CTRL_RT_AUTO
- RT_MAN_CTRL_RT_B
- RT_MASK
- RT_MAX_LD_SLOT_NUM
- RT_MAX_TRIES
- RT_MEDIA_CONNECT
- RT_MEDIA_DISCONNECT
- RT_MEDIA_STATUS
- RT_MIN_TABLE
- RT_MPT_WI_SPINLOCK
- RT_MULTI_FUNC
- RT_MULTI_FUNC_BT
- RT_MULTI_FUNC_GPS
- RT_MULTI_FUNC_NONE
- RT_MULTI_FUNC_WIFI
- RT_MUTEX_FULL_CHAINWALK
- RT_MUTEX_HAS_WAITERS
- RT_MUTEX_MIN_CHAINWALK
- RT_NOTHING
- RT_NO_ACTION
- RT_NUMBER
- RT_OFFSET
- RT_OP_MODE_AP
- RT_OP_MODE_IBSS
- RT_OP_MODE_INFRASTRUCTURE
- RT_OP_MODE_NO_LINK
- RT_P2P_SPIN_LOCK
- RT_PCI_ASPM_OSC_DISABLE
- RT_PCI_ASPM_OSC_ENABLE
- RT_PCI_ASPM_OSC_IGNORE
- RT_PCI_INTERFACE
- RT_PENDED_OID_SPINLOCK
- RT_PMKID_LIST
- RT_POLARITY_CTL
- RT_POLARITY_HIGH_ACT
- RT_POLARITY_LOW_ACT
- RT_PORT_SPINLOCK
- RT_PRINTK
- RT_PRINT_DATA
- RT_PS_LEVEL_ASPM
- RT_PS_MODE
- RT_P_CFG0_CLK1NOTCLK0_FIELD
- RT_P_CFG0_DELAY_0_FIELD
- RT_P_CFG0_DELAY_1_FIELD
- RT_P_CFG1_CLKNOTDATA_FIELD
- RT_P_CFG1_DOUBLE_EDGE_FIELD
- RT_P_CFG1_INVERTCLK_FIELD
- RT_P_CFG1_RETIME_FIELD
- RT_P_CFGS_PER_BANK
- RT_REGULATOR_MODE
- RT_RF_CHANGE_SOURCE
- RT_RF_LPS_DISALBE_2R
- RT_RF_LPS_LEVEL_ASPM
- RT_RF_OFF_LEVL_ASPM
- RT_RF_OFF_LEVL_CLK_REQ
- RT_RF_OFF_LEVL_FREE_FW
- RT_RF_OFF_LEVL_FW_32K
- RT_RF_OFF_LEVL_HALT_NIC
- RT_RF_OFF_LEVL_PCI_D3
- RT_RF_OPERATE_SPINLOCK
- RT_RF_POWER_STATE
- RT_RF_PS_LEVEL_ALWAYS_ASPM
- RT_RF_STATE_SPINLOCK
- RT_RF_TYPE_819xU
- RT_RF_TYPE_DEFINITION
- RT_RING
- RT_RM_SPINLOCK
- RT_RSTCTRL_UDEV
- RT_RSTCTRL_UHST
- RT_RX_SPINLOCK
- RT_SCAN_SPINLOCK
- RT_SCAN_TYPE
- RT_SCOPE_HOST
- RT_SCOPE_LINK
- RT_SCOPE_NOWHERE
- RT_SCOPE_SITE
- RT_SCOPE_UNIVERSE
- RT_SDIO_INTERFACE
- RT_SET_PS_LEVEL
- RT_SH
- RT_SHIFT
- RT_SMOOTH_DATA_4RF
- RT_SPINLOCK_TYPE
- RT_START_IBSS
- RT_STATUS
- RT_STATUS_FAILURE
- RT_STATUS_INVALID_CONTEXT
- RT_STATUS_INVALID_PARAMETER
- RT_STATUS_NOT_SUPPORT
- RT_STATUS_OS_API_FAILED
- RT_STATUS_PENDING
- RT_STATUS_RESOURCE
- RT_STATUS_SUCCESS
- RT_STRING
- RT_SWITCHING_REGULATOR
- RT_SYSCFG1_USB0_HOST_MODE
- RT_SYSC_REG_CLKCFG1
- RT_SYSC_REG_SYSCFG1
- RT_SYSC_REG_USB_PHY_CFG
- RT_SYSPLL_EN_AFE_OLT
- RT_TABLE_COMPAT
- RT_TABLE_DEFAULT
- RT_TABLE_LOCAL
- RT_TABLE_MAIN
- RT_TABLE_MAX
- RT_TABLE_MIN
- RT_TABLE_UNSPEC
- RT_TIMER_CALL_BACK
- RT_TOS
- RT_TRACE
- RT_TXDESC_NUM
- RT_TXDESC_NUM_BE_QUEUE
- RT_TX_SPINLOCK
- RT_TYPE_BACKOFF
- RT_TYPE_DISABLE
- RT_TYPE_ENABLE
- RT_TYPE_RX_GAIN_MAX
- RT_TYPE_RX_GAIN_MIN
- RT_TYPE_THRESH_HIGH
- RT_TYPE_THRESH_LOW
- RT_UNLOCK
- RT_USB_INTERFACE
- RT_WAPI_OPTION_SPINLOCK
- RT_WAPI_RX_SPINLOCK
- RT_ZCAU
- RT_ZSAU
- RTxCX
- RU
- RUBIN_REG_SIZE
- RUC
- RUC_ABORT
- RUC_MASK
- RUC_NOP
- RUC_RESUME
- RUC_START
- RUC_SUSPEND
- RUDADATA
- RUDARDPT
- RUDAWRPT
- RUD_ITEM
- RUFFIAN_LATCH
- RUI_ITEM
- RUN
- RUND
- RUNDFLEN
- RUND_ADDR
- RUND_IDX
- RUNLATCH_ON
- RUNM_RUN
- RUNNING
- RUNNING_HELPERS_TIMEOUT
- RUNNING_MERGE
- RUNNING_MFW
- RUNSTATE_blocked
- RUNSTATE_offline
- RUNSTATE_runnable
- RUNSTATE_running
- RUNT
- RUNTEEN
- RUNTEN
- RUNTIME_9060
- RUNTIME_ARRAY_SIZE
- RUNTIME_INF
- RUNTIME_INFO
- RUNTPKT
- RUNT_CNT_MASK
- RUNT_CNT_SHIFT_BIT
- RUNT_MAC_STS
- RUNWAY_DEBUG
- RUNWAY_STATUS
- RUN_ARRAY
- RUN_ASSP
- RUN_AT
- RUN_AT_LOAD_DEFAULT
- RUN_BITS
- RUN_COMMAND_NO_STDIN
- RUN_COMMAND_STDOUT_TO_STDERR
- RUN_CONTEXT
- RUN_DELAYED_IPUTS
- RUN_EXEC_CMD
- RUN_FAIL_MASK
- RUN_FAIL_MASK_SET
- RUN_FROM_INT_ROM
- RUN_FW_UPGRADE
- RUN_MASK
- RUN_MODE
- RUN_RL
- RUN_SEN
- RUN_SETUP
- RUN_TEST
- RUN_TIME
- RUSAGE_BOTH
- RUSAGE_CHILDREN
- RUSAGE_SELF
- RUSAGE_THREAD
- RU_NOSPACE
- RU_READY
- RU_RUNNING
- RU_STATUS
- RU_SUSPEND
- RU_SUSPENDED
- RU_UNINITIALIZED
- RV
- RV100_HALF_MODE
- RV100_MEM_HALF_MODE
- RV1108
- RV1108_CLKGATE_CON
- RV1108_CLKSEL0
- RV1108_CLKSEL_CON
- RV1108_CPUCLK_RATE
- RV1108_DIV_CORE_MASK
- RV1108_DIV_CORE_SHIFT
- RV1108_DRV_BANK_STRIDE
- RV1108_DRV_BITS_PER_PIN
- RV1108_DRV_GRF_OFFSET
- RV1108_DRV_PINS_PER_REG
- RV1108_DRV_PMU_OFFSET
- RV1108_EMMC_CON0
- RV1108_EMMC_CON1
- RV1108_GLB_SRST_FST
- RV1108_GLB_SRST_SND
- RV1108_GMAC_FLOW_CTRL
- RV1108_GMAC_FLOW_CTRL_CLR
- RV1108_GMAC_PHY_INTF_SEL_RMII
- RV1108_GMAC_RMII_CLK_25M
- RV1108_GMAC_RMII_CLK_2_5M
- RV1108_GMAC_SPEED_100M
- RV1108_GMAC_SPEED_10M
- RV1108_GRF_GMAC_CON0
- RV1108_GRF_SOC_STATUS0
- RV1108_MISC_CON
- RV1108_PLL_CON
- RV1108_PULL_BANK_STRIDE
- RV1108_PULL_BITS_PER_PIN
- RV1108_PULL_OFFSET
- RV1108_PULL_PINS_PER_REG
- RV1108_PULL_PMU_OFFSET
- RV1108_SCHMITT_BANK_STRIDE
- RV1108_SCHMITT_GRF_OFFSET
- RV1108_SCHMITT_PINS_PER_GRF_REG
- RV1108_SCHMITT_PINS_PER_PMU_REG
- RV1108_SCHMITT_PMU_OFFSET
- RV1108_SDIO_CON0
- RV1108_SDIO_CON1
- RV1108_SDMMC_CON0
- RV1108_SDMMC_CON1
- RV1108_SOFTRST_CON
- RV1805
- RV2P_BD_PAGE_SIZE
- RV2P_BD_PAGE_SIZE_MSK
- RV2P_P1_FIXUP_PAGE_SIZE_IDX
- RV2P_PROC1
- RV2P_PROC2
- RV3028_ALARM_DAY
- RV3028_ALARM_HOUR
- RV3028_ALARM_MIN
- RV3028_BACKUP
- RV3028_BACKUP_TCE
- RV3028_BACKUP_TCR_MASK
- RV3028_CLKOUT
- RV3028_CTRL1
- RV3028_CTRL1_EERD
- RV3028_CTRL1_WADA
- RV3028_CTRL2
- RV3028_CTRL2_12_24
- RV3028_CTRL2_AIE
- RV3028_CTRL2_EIE
- RV3028_CTRL2_RESET
- RV3028_CTRL2_TIE
- RV3028_CTRL2_TSE
- RV3028_CTRL2_UIE
- RV3028_DAY
- RV3028_EEBUSY_POLL
- RV3028_EEBUSY_TIMEOUT
- RV3028_EEPROM_ADDR
- RV3028_EEPROM_CMD
- RV3028_EEPROM_CMD_READ
- RV3028_EEPROM_CMD_WRITE
- RV3028_EEPROM_DATA
- RV3028_EVT_CTRL
- RV3028_EVT_CTRL_TSR
- RV3028_HOUR
- RV3028_MIN
- RV3028_MONTH
- RV3028_OFFSET
- RV3028_RAM1
- RV3028_SEC
- RV3028_STATUS
- RV3028_STATUS_AF
- RV3028_STATUS_BSF
- RV3028_STATUS_CLKF
- RV3028_STATUS_EEBUSY
- RV3028_STATUS_EVF
- RV3028_STATUS_PORF
- RV3028_STATUS_TF
- RV3028_STATUS_UF
- RV3028_TS_COUNT
- RV3028_TS_SEC
- RV3028_WDAY
- RV3028_YEAR
- RV3029_ALARM_SECTION_LEN
- RV3029_A_AE_X
- RV3029_A_DT
- RV3029_A_DW
- RV3029_A_HR
- RV3029_A_MN
- RV3029_A_MO
- RV3029_A_SC
- RV3029_A_YR
- RV3029_CONTROL_E2P_EECTRL
- RV3029_CONTROL_E2P_QCOEF
- RV3029_CONTROL_E2P_TOV_MASK
- RV3029_CONTROL_E2P_TURNOVER
- RV3029_CONTROL_E2P_XOFFS
- RV3029_CONTROL_E2P_XOFFS_SIGN
- RV3029_CONTROL_SECTION_LEN
- RV3029_E2PDATA_SECTION_LEN
- RV3029_E2P_EEDATA1
- RV3029_E2P_EEDATA2
- RV3029_EECTRL_FD0
- RV3029_EECTRL_FD1
- RV3029_EECTRL_THE
- RV3029_EECTRL_THP
- RV3029_IRQ_CTRL
- RV3029_IRQ_CTRL_AIE
- RV3029_IRQ_CTRL_SRIE
- RV3029_IRQ_CTRL_TIE
- RV3029_IRQ_CTRL_V1IE
- RV3029_IRQ_CTRL_V2IE
- RV3029_IRQ_FLAGS
- RV3029_IRQ_FLAGS_AF
- RV3029_IRQ_FLAGS_SRF
- RV3029_IRQ_FLAGS_TF
- RV3029_IRQ_FLAGS_V1IF
- RV3029_IRQ_FLAGS_V2IF
- RV3029_ONOFF_CTRL
- RV3029_ONOFF_CTRL_CLKINT
- RV3029_ONOFF_CTRL_EERE
- RV3029_ONOFF_CTRL_SRON
- RV3029_ONOFF_CTRL_TAR
- RV3029_ONOFF_CTRL_TD0
- RV3029_ONOFF_CTRL_TD1
- RV3029_ONOFF_CTRL_TE
- RV3029_ONOFF_CTRL_WE
- RV3029_REG_HR_12_24
- RV3029_REG_HR_PM
- RV3029_RST_CTRL
- RV3029_RST_CTRL_SYSR
- RV3029_STATUS
- RV3029_STATUS_EEBUSY
- RV3029_STATUS_PON
- RV3029_STATUS_SR
- RV3029_STATUS_VLOW1
- RV3029_STATUS_VLOW2
- RV3029_TEMP_PAGE
- RV3029_TIMER_HIGH
- RV3029_TIMER_LOW
- RV3029_TRICKLE_1K
- RV3029_TRICKLE_20K
- RV3029_TRICKLE_5K
- RV3029_TRICKLE_80K
- RV3029_TRICKLE_MASK
- RV3029_TRICKLE_SHIFT
- RV3029_USR1_RAM_PAGE
- RV3029_USR1_SECTION_LEN
- RV3029_USR2_RAM_PAGE
- RV3029_USR2_SECTION_LEN
- RV3029_WATCH_SECTION_LEN
- RV3029_W_DATE
- RV3029_W_DAYS
- RV3029_W_HOURS
- RV3029_W_MINUTES
- RV3029_W_MONTHS
- RV3029_W_SEC
- RV3029_W_YEARS
- RV370_BUS_BIOS_DIS_ROM
- RV370_BUS_CNTL
- RV370_MSI_REARM_EN
- RV515_MC_AGP_BASE
- RV515_MC_AGP_BASE_2
- RV515_MC_AGP_LOCATION
- RV515_MC_AGP_START_MASK
- RV515_MC_AGP_START_SHIFT
- RV515_MC_AGP_TOP_MASK
- RV515_MC_AGP_TOP_SHIFT
- RV515_MC_CNTL
- RV515_MC_FB_LOCATION
- RV515_MC_FB_START_MASK
- RV515_MC_FB_START_SHIFT
- RV515_MC_FB_TOP_MASK
- RV515_MC_FB_TOP_SHIFT
- RV515_MC_INIT_MISC_LAT_TIMER
- RV515_MC_STATUS
- RV515_MC_STATUS_IDLE
- RV515_MEM_NUM_CHANNELS_MASK
- RV530_FG_ZBREG_DEST
- RV530_GB_PIPE_SELECT2
- RV5C387_CTRL1_24
- RV6XXD_H
- RV6XX_DEFAULT_DCLK_FREQ
- RV6XX_DEFAULT_VCLK_FREQ
- RV710_SMC_INT_VECTOR_SIZE
- RV710_SMC_INT_VECTOR_START
- RV710_SMC_UCODE_SIZE
- RV710_SMC_UCODE_START
- RV730_H
- RV730_MPLL_MCLK_SEL
- RV730_SMC_INT_VECTOR_SIZE
- RV730_SMC_INT_VECTOR_START
- RV730_SMC_MCLK_VALUE
- RV730_SMC_UCODE_SIZE
- RV730_SMC_UCODE_START
- RV740_H
- RV740_SMC_INT_VECTOR_SIZE
- RV740_SMC_INT_VECTOR_START
- RV740_SMC_UCODE_SIZE
- RV740_SMC_UCODE_START
- RV770_ASI_DFLT
- RV770_CG_THERMAL_INT
- RV770_DEFAULT_DCLK_FREQ
- RV770_DEFAULT_VCLK_FREQ
- RV770_H
- RV770_HASI_DFLT
- RV770_LHP_DFLT
- RV770_LMP_DFLT
- RV770_MGCGCGTSSMCTRL_DFLT
- RV770_MGCGTTLOCAL0_DFLT
- RV770_MGCGTTLOCAL1_DFLT
- RV770_RLP_DFLT
- RV770_RMP_DFLT
- RV770_SMC_HW_PERFORMANCE_LEVEL
- RV770_SMC_INT_VECTOR_SIZE
- RV770_SMC_INT_VECTOR_START
- RV770_SMC_MCLK_VALUE
- RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE
- RV770_SMC_SCLK_VALUE
- RV770_SMC_SOFT_REGISTERS_START
- RV770_SMC_SOFT_REGISTER_baby_step_timer
- RV770_SMC_SOFT_REGISTER_delay_acpi
- RV770_SMC_SOFT_REGISTER_delay_bbias
- RV770_SMC_SOFT_REGISTER_delay_vreg
- RV770_SMC_SOFT_REGISTER_is_asic_lombok
- RV770_SMC_SOFT_REGISTER_mc_block_delay
- RV770_SMC_SOFT_REGISTER_mclk_chg_timeout
- RV770_SMC_SOFT_REGISTER_mclk_switch_lim
- RV770_SMC_SOFT_REGISTER_mvdd_chg_time
- RV770_SMC_SOFT_REGISTER_seq_index
- RV770_SMC_SOFT_REGISTER_uvd_enabled
- RV770_SMC_STATETABLE
- RV770_SMC_SWSTATE
- RV770_SMC_TABLE_ADDRESS
- RV770_SMC_UCODE_SIZE
- RV770_SMC_UCODE_START
- RV770_SMC_VOLTAGEMASKTABLE
- RV770_SMC_VOLTAGEMASK_MAX
- RV770_SMC_VOLTAGEMASK_MVDD
- RV770_SMC_VOLTAGEMASK_VDDC
- RV770_SMC_VOLTAGEMASK_VDDCI
- RV770_SMC_VOLTAGE_VALUE
- RV770_SOFT_RESET_DMA
- RV770_VRC_DFLT
- RV7XX_MGCGTTLOCAL0_DFLT
- RV7XX_SMC_MCLK_VALUE
- RV8803_ALARM_HOUR
- RV8803_ALARM_MIN
- RV8803_ALARM_WEEK_OR_DAY
- RV8803_CTRL
- RV8803_CTRL_AIE
- RV8803_CTRL_EIE
- RV8803_CTRL_RESET
- RV8803_CTRL_TIE
- RV8803_CTRL_UIE
- RV8803_DAY
- RV8803_EXT
- RV8803_EXT_WADA
- RV8803_FLAG
- RV8803_FLAG_AF
- RV8803_FLAG_TF
- RV8803_FLAG_UF
- RV8803_FLAG_V1F
- RV8803_FLAG_V2F
- RV8803_HOUR
- RV8803_I2C_TRY_COUNT
- RV8803_MIN
- RV8803_MONTH
- RV8803_RAM
- RV8803_SEC
- RV8803_WEEK
- RV8803_YEAR
- RV9
- RVCCAP
- RVDEV_NUM_VRINGS
- RVHTLEN_USE_LSIG
- RVII_CLKSEL_DSP
- RVII_CLKSEL_DSP_IF
- RVII_CLKSEL_DSS1
- RVII_CLKSEL_DSS2
- RVII_CLKSEL_GFX
- RVII_CLKSEL_IVA
- RVII_CLKSEL_L3
- RVII_CLKSEL_L4
- RVII_CLKSEL_MPU
- RVII_CLKSEL_SSI
- RVII_CLKSEL_USB
- RVII_CLKSEL_VLYNQ
- RVII_CM_CLKSEL1_CORE_VAL
- RVII_CM_CLKSEL_DSP_VAL
- RVII_CM_CLKSEL_GFX_VAL
- RVII_CM_CLKSEL_MPU_VAL
- RVII_SYNC_DSP
- RVII_SYNC_IVA
- RVIN_CSI20
- RVIN_CSI21
- RVIN_CSI40
- RVIN_CSI41
- RVIN_CSI_MAX
- RVIN_DEFAULT_COLORSPACE
- RVIN_DEFAULT_FIELD
- RVIN_DEFAULT_FORMAT
- RVIN_DEFAULT_HEIGHT
- RVIN_DEFAULT_WIDTH
- RVIN_RETRIES
- RVIN_TIMEOUT_MS
- RVMII_REF_SEL
- RVO_MASK
- RVO_SHIFT
- RVPOLE
- RVT_ABI_USER_H
- RVT_BITS_PER_PAGE
- RVT_BITS_PER_PAGE_MASK
- RVT_BRANCH_TAKEN
- RVT_CQN_MAX
- RVT_CQ_NONE
- RVT_DONE
- RVT_FALL_THROUGH
- RVT_FLUSH_RECV
- RVT_FLUSH_SEND
- RVT_MAX_LKEY_TABLE_BITS
- RVT_MAX_PKEY_VALUES
- RVT_MAX_TRAP_LEN
- RVT_MAX_TRAP_LISTS
- RVT_OPCODE_QP_MASK
- RVT_OPERATION_ATOMIC
- RVT_OPERATION_ATOMIC_SGE
- RVT_OPERATION_IGN_RNR_CNT
- RVT_OPERATION_LOCAL
- RVT_OPERATION_MAX
- RVT_OPERATION_PRIV
- RVT_OPERATION_USE_RESERVE
- RVT_POST_RECV_OK
- RVT_POST_SEND_OK
- RVT_PROCESS_NEXT_SEND_OK
- RVT_PROCESS_OR_FLUSH_SEND
- RVT_PROCESS_RECV_OK
- RVT_PROCESS_SEND_OK
- RVT_QPNMAP_ENTRIES
- RVT_QPN_MASK
- RVT_QPN_MAX
- RVT_RWQ_COUNT_THRESHOLD
- RVT_R_COMM_EST
- RVT_R_RDMAR_SEQ
- RVT_R_REUSE_SGE
- RVT_R_REWIND_SGE
- RVT_R_RSP_NAK
- RVT_R_RSP_SEND
- RVT_R_WRID_VALID
- RVT_SEGSZ
- RVT_SEND_COMPLETION_ONLY
- RVT_SEND_OR_FLUSH_OR_RECV_OK
- RVT_SEND_RESERVE_USED
- RVT_SGE_COPY_ADAPTIVE
- RVT_SGE_COPY_CACHELESS
- RVT_SGE_COPY_MEMCPY
- RVT_S_ACK_PENDING
- RVT_S_ANY_WAIT
- RVT_S_ANY_WAIT_IO
- RVT_S_ANY_WAIT_SEND
- RVT_S_BUSY
- RVT_S_ECN
- RVT_S_MAX_BIT_MASK
- RVT_S_RESP_PENDING
- RVT_S_SEND_ONE
- RVT_S_SIGNAL_REQ_WR
- RVT_S_TIMER
- RVT_S_UNLIMITED_CREDIT
- RVT_S_WAIT_ACK
- RVT_S_WAIT_DMA
- RVT_S_WAIT_DMA_DESC
- RVT_S_WAIT_FENCE
- RVT_S_WAIT_KMEM
- RVT_S_WAIT_PIO
- RVT_S_WAIT_PSN
- RVT_S_WAIT_RDMAR
- RVT_S_WAIT_RNR
- RVT_S_WAIT_SSN_CREDIT
- RVT_S_WAIT_TX
- RVT_TRAP_TIMEOUT
- RVT_UVERBS_ABI_VERSION
- RVT_VISITED_MASK
- RVU_AF_AFPFX_MBOXX
- RVU_AF_AFPF_MBOX0
- RVU_AF_AFPF_MBOX1
- RVU_AF_BLK_RST
- RVU_AF_ECO
- RVU_AF_GEN_INT
- RVU_AF_GEN_INT_ENA_W1C
- RVU_AF_GEN_INT_ENA_W1S
- RVU_AF_GEN_INT_W1S
- RVU_AF_HWVF_RST
- RVU_AF_INT_VEC_CNT
- RVU_AF_INT_VEC_GEN
- RVU_AF_INT_VEC_MBOX
- RVU_AF_INT_VEC_PFFLR
- RVU_AF_INT_VEC_PFME
- RVU_AF_INT_VEC_POISON
- RVU_AF_MSIXTR_BASE
- RVU_AF_PFAF_MBOX_INT
- RVU_AF_PFAF_MBOX_INT_ENA_W1C
- RVU_AF_PFAF_MBOX_INT_ENA_W1S
- RVU_AF_PFAF_MBOX_INT_W1S
- RVU_AF_PFFLR_INT
- RVU_AF_PFFLR_INT_ENA_W1C
- RVU_AF_PFFLR_INT_ENA_W1S
- RVU_AF_PFFLR_INT_W1S
- RVU_AF_PFME_INT
- RVU_AF_PFME_INT_ENA_W1C
- RVU_AF_PFME_INT_ENA_W1S
- RVU_AF_PFME_INT_W1S
- RVU_AF_PFME_STATUS
- RVU_AF_PFTRPEND
- RVU_AF_PFTRPEND_W1S
- RVU_AF_PF_BAR4_ADDR
- RVU_AF_PF_RST
- RVU_AF_RAS
- RVU_AF_RAS_ENA_W1C
- RVU_AF_RAS_ENA_W1S
- RVU_AF_RAS_W1S
- RVU_DEFAULT_PF_FUNC
- RVU_H
- RVU_INVALID_VF_ID
- RVU_PFVF_FUNC_MASK
- RVU_PFVF_FUNC_SHIFT
- RVU_PFVF_PF_MASK
- RVU_PFVF_PF_SHIFT
- RVU_PF_BLOCK_ADDRX_DISC
- RVU_PF_INT
- RVU_PF_INT_ENA_W1C
- RVU_PF_INT_ENA_W1S
- RVU_PF_INT_VEC_AFPF_MBOX
- RVU_PF_INT_VEC_CNT
- RVU_PF_INT_VEC_VFFLR0
- RVU_PF_INT_VEC_VFFLR1
- RVU_PF_INT_VEC_VFME0
- RVU_PF_INT_VEC_VFME1
- RVU_PF_INT_VEC_VFPF_MBOX0
- RVU_PF_INT_VEC_VFPF_MBOX1
- RVU_PF_INT_W1S
- RVU_PF_MSIX_PBAX
- RVU_PF_MSIX_VECX_ADDR
- RVU_PF_MSIX_VECX_CTL
- RVU_PF_PFAF_MBOX0
- RVU_PF_PFAF_MBOX1
- RVU_PF_PFAF_MBOXX
- RVU_PF_VFFLR_INTX
- RVU_PF_VFFLR_INT_ENA_W1CX
- RVU_PF_VFFLR_INT_ENA_W1SX
- RVU_PF_VFFLR_INT_W1SX
- RVU_PF_VFME_INTX
- RVU_PF_VFME_INT_ENA_W1CX
- RVU_PF_VFME_INT_ENA_W1SX
- RVU_PF_VFME_INT_W1SX
- RVU_PF_VFME_STATUSX
- RVU_PF_VFPF_MBOX_INTX
- RVU_PF_VFPF_MBOX_INT_ENA_W1CX
- RVU_PF_VFPF_MBOX_INT_ENA_W1SX
- RVU_PF_VFPF_MBOX_INT_W1SX
- RVU_PF_VFTRPENDX
- RVU_PF_VFTRPEND_W1SX
- RVU_PF_VFX_PFVF_MBOX0
- RVU_PF_VFX_PFVF_MBOX1
- RVU_PF_VFX_PFVF_MBOXX
- RVU_PF_VF_BAR4_ADDR
- RVU_PRIV_ACTIVE_PC
- RVU_PRIV_BLOCK_TYPEX_REV
- RVU_PRIV_CLK_CFG
- RVU_PRIV_CONST
- RVU_PRIV_GEN_CFG
- RVU_PRIV_HWVFX_CPT0_CFG
- RVU_PRIV_HWVFX_INT_CFG
- RVU_PRIV_HWVFX_NIX0_CFG
- RVU_PRIV_HWVFX_NPA_CFG
- RVU_PRIV_HWVFX_SSOW_CFG
- RVU_PRIV_HWVFX_SSO_CFG
- RVU_PRIV_HWVFX_TIM_CFG
- RVU_PRIV_PFX_CFG
- RVU_PRIV_PFX_CPT0_CFG
- RVU_PRIV_PFX_ID_CFG
- RVU_PRIV_PFX_INT_CFG
- RVU_PRIV_PFX_MSIX_CFG
- RVU_PRIV_PFX_NIX0_CFG
- RVU_PRIV_PFX_NPA_CFG
- RVU_PRIV_PFX_SSOW_CFG
- RVU_PRIV_PFX_SSO_CFG
- RVU_PRIV_PFX_TIM_CFG
- RVU_REG_H
- RVU_STRUCT_H
- RVU_VF_VFPF_MBOX0
- RVU_VF_VFPF_MBOX1
- RVW
- RV_ADCSR_ABCM_32
- RV_ADCSR_ABCM_40
- RV_ADCSR_ABCM_64
- RV_ADCSR_ABCM_AUTO
- RV_ADCSR_ABM_1
- RV_ADCSR_ABM_2
- RV_ADCSR_ABM_PT25
- RV_ADCSR_ABM_PT5
- RV_ADCSR_ABR_
- RV_ADCSR_ABR_32
- RV_ADCSR_ABR_44_1
- RV_ADCSR_ABR_48
- RV_ADCVOLL_MUTE
- RV_ADCVOLL_N71PT25DB
- RV_ADCVOLL_P24DB
- RV_ADCVOLR_MUTE
- RV_ADCVOLR_N71PT25DB
- RV_ADCVOLR_P24DB
- RV_AIC1_BCLKINV_DISABLE
- RV_AIC1_BCLKINV_ENABLE
- RV_AIC1_FORMAT_I2S
- RV_AIC1_FORMAT_LEFT
- RV_AIC1_FORMAT_RIGHT
- RV_AIC1_LRP_INVERT
- RV_AIC1_LRP_NORMAL
- RV_AIC1_MS_MASTER
- RV_AIC1_MS_SLAVE
- RV_AIC1_WL_16
- RV_AIC1_WL_20
- RV_AIC1_WL_24
- RV_AIC1_WL_32
- RV_AIC2_BLRCM_DAC_BCLK_LRCLK_SHARED
- RV_BDREL
- RV_CLECTL_COMP_EN_DISABLE
- RV_CLECTL_COMP_EN_ENABLE
- RV_CLECTL_EXP_EN_DISABLE
- RV_CLECTL_EXP_EN_ENABLE
- RV_CLECTL_LIMIT_EN_DISABLE
- RV_CLECTL_LIMIT_EN_ENABLE
- RV_CLECTL_LVL_MODE_AVG
- RV_CLECTL_LVL_MODE_PEAK
- RV_CLECTL_WINDOWSEL_512
- RV_CLECTL_WINDOWSEL_64
- RV_CNVRTR0_ADCHPDL_DISABLE
- RV_CNVRTR0_ADCHPDL_ENABLE
- RV_CNVRTR0_ADCHPDR_DISABLE
- RV_CNVRTR0_ADCHPDR_ENABLE
- RV_CNVRTR0_ADCMU_DISABLE
- RV_CNVRTR0_ADCMU_ENABLE
- RV_CNVRTR0_ADCPOLL_INVERT
- RV_CNVRTR0_ADCPOLL_NORMAL
- RV_CNVRTR0_ADCPOLR_INVERT
- RV_CNVRTR0_ADCPOLR_NORMAL
- RV_CNVRTR1_DACMU_DISABLE
- RV_CNVRTR1_DACMU_ENABLE
- RV_CNVRTR1_DACPOLL_INVERT
- RV_CNVRTR1_DACPOLL_NORMAL
- RV_CNVRTR1_DACPOLR_INVERT
- RV_CNVRTR1_DACPOLR_NORMAL
- RV_CNVRTR1_DMONOMIX_DISABLE
- RV_CNVRTR1_DMONOMIX_ENABLE
- RV_COMPTH_0DB
- RV_COMPTH_N95PT625DB
- RV_CONFIG0_ASDM_AUTO
- RV_CONFIG0_ASDM_FULL
- RV_CONFIG0_ASDM_HALF
- RV_CONFIG0_DC_BYPASS_DISABLE
- RV_CONFIG0_DC_BYPASS_ENABLE
- RV_CONFIG0_DSDM_AUTO
- RV_CONFIG0_DSDM_FULL
- RV_CONFIG0_DSDM_HALF
- RV_CONFIG0_SD_FORCE_ON_DISABLE
- RV_CONFIG0_SD_FORCE_ON_ENABLE
- RV_CONFIG1_EQ1_BE_PRE
- RV_CONFIG1_EQ1_BE_PRE_EQ0_1
- RV_CONFIG1_EQ1_BE_PRE_EQ0_2
- RV_CONFIG1_EQ1_BE_PRE_EQ0_3
- RV_CONFIG1_EQ1_BE_PRE_EQ0_4
- RV_CONFIG1_EQ1_BE_PRE_EQ0_5
- RV_CONFIG1_EQ1_BE_PRE_EQ_0
- RV_CONFIG1_EQ1_EN_DISABLE
- RV_CONFIG1_EQ1_EN_ENABLE
- RV_CONFIG1_EQ2_BE_PRE
- RV_CONFIG1_EQ2_BE_PRE_EQ0_1
- RV_CONFIG1_EQ2_BE_PRE_EQ0_2
- RV_CONFIG1_EQ2_BE_PRE_EQ0_3
- RV_CONFIG1_EQ2_BE_PRE_EQ0_4
- RV_CONFIG1_EQ2_BE_PRE_EQ0_5
- RV_CONFIG1_EQ2_BE_PRE_EQ_0
- RV_CONFIG1_EQ2_EN_DISABLE
- RV_CONFIG1_EQ2_EN_ENABLE
- RV_CTX_F_SEEN_CALL
- RV_CTX_F_SEEN_S1
- RV_CTX_F_SEEN_S2
- RV_CTX_F_SEEN_S3
- RV_CTX_F_SEEN_S4
- RV_CTX_F_SEEN_S5
- RV_CTX_F_SEEN_S6
- RV_CTX_F_SEEN_TAIL_CALL
- RV_DACSR_DBCM_32
- RV_DACSR_DBCM_40
- RV_DACSR_DBCM_64
- RV_DACSR_DBCM_AUTO
- RV_DACSR_DBM_1
- RV_DACSR_DBM_2
- RV_DACSR_DBM_PT25
- RV_DACSR_DBM_PT5
- RV_DACSR_DBR_32
- RV_DACSR_DBR_44_1
- RV_DACSR_DBR_48
- RV_DACVOLL_0DB
- RV_DACVOLL_MUTE
- RV_DACVOLL_N95PT625DB
- RV_DACVOLR_0DB
- RV_DACVOLR_MUTE
- RV_DACVOLR_N95PT625DB
- RV_DCOFSEL_DC_COEF_SEL_2_N10
- RV_DCOFSEL_DC_COEF_SEL_2_N11
- RV_DCOFSEL_DC_COEF_SEL_2_N12
- RV_DCOFSEL_DC_COEF_SEL_2_N13
- RV_DCOFSEL_DC_COEF_SEL_2_N14
- RV_DCOFSEL_DC_COEF_SEL_2_N15
- RV_DCOFSEL_DC_COEF_SEL_2_N8
- RV_DCOFSEL_DC_COEF_SEL_2_N9
- RV_DIRECT
- RV_DMICCTL_DMICEN_DISABLE
- RV_DMICCTL_DMICEN_ENABLE
- RV_DMICCTL_DMONO_MONO
- RV_DMICCTL_DMONO_STEREO
- RV_DTPMOD
- RV_DTPREL
- RV_EXPTH_0DB
- RV_EXPTH_N95PT625DB
- RV_FPTR
- RV_FXCTL_3DEN_DISABLE
- RV_FXCTL_3DEN_ENABLE
- RV_FXCTL_BEEN_DISABLE
- RV_FXCTL_BEEN_ENABLE
- RV_FXCTL_BNLFBYPASS_DISABLE
- RV_FXCTL_BNLFBYPASS_ENABLE
- RV_FXCTL_TEEN_DISABLE
- RV_FXCTL_TEEN_ENABLE
- RV_FXCTL_TNLFBYPASS_DISABLE
- RV_FXCTL_TNLFBYPASS_ENABLE
- RV_GPREL
- RV_HPVOLL_MUTE
- RV_HPVOLL_N88PT5DB
- RV_HPVOLL_P6DB
- RV_HPVOLR_MUTE
- RV_HPVOLR_N88PT5DB
- RV_HPVOLR_P6DB
- RV_INMODE_DS_LRIN1
- RV_INMODE_DS_LRIN2
- RV_INSELL_D2S
- RV_INSELL_IN1
- RV_INSELL_IN2
- RV_INSELL_IN3
- RV_INSELL_MICBSTL_10DB
- RV_INSELL_MICBSTL_20DB
- RV_INSELL_MICBSTL_30DB
- RV_INSELL_MICBSTL_OFF
- RV_INSELR_D2S
- RV_INSELR_IN1
- RV_INSELR_IN2
- RV_INSELR_IN3
- RV_INSELR_MICBSTR_10DB
- RV_INSELR_MICBSTR_20DB
- RV_INSELR_MICBSTR_30DB
- RV_INSELR_MICBSTR_OFF
- RV_INVOLL_INMUTEL_DISABLE
- RV_INVOLL_INMUTEL_ENABLE
- RV_INVOLL_IZCL_DISABLE
- RV_INVOLL_IZCL_ENABLE
- RV_INVOLL_N17PT25DB
- RV_INVOLL_P30DB
- RV_INVOLR_INMUTER_DISABLE
- RV_INVOLR_INMUTER_ENABLE
- RV_INVOLR_IZCR_DISABLE
- RV_INVOLR_IZCR_ENABLE
- RV_INVOLR_N17PT25DB
- RV_INVOLR_P30DB
- RV_LIMTGT_0DB
- RV_LIMTGT_N95PT625DB
- RV_LIMTH_0DB
- RV_LIMTH_N95PT625DB
- RV_LTREL
- RV_LTREL_DTPMOD
- RV_LTREL_DTPREL
- RV_LTREL_FPTR
- RV_LTREL_TPREL
- RV_LTV
- RV_MUGAIN_CLEMUG_0DB
- RV_MUGAIN_CLEMUG_46PT5DB
- RV_PCREL
- RV_PCREL2
- RV_PLLCTL1C_PDB_PLL1_DISABLE
- RV_PLLCTL1C_PDB_PLL1_ENABLE
- RV_PLLCTL1C_PDB_PLL2_DISABLE
- RV_PLLCTL1C_PDB_PLL2_ENABLE
- RV_PLLREFSEL_PLL1_REF_SEL_MCLK2
- RV_PLLREFSEL_PLL1_REF_SEL_XTAL_MCLK1
- RV_PLLREFSEL_PLL2_REF_SEL_MCLK2
- RV_PLLREFSEL_PLL2_REF_SEL_XTAL_MCLK1
- RV_PLTREL
- RV_PWRM1_ADCL_DISABLE
- RV_PWRM1_ADCL_ENABLE
- RV_PWRM1_ADCR_DISABLE
- RV_PWRM1_ADCR_ENABLE
- RV_PWRM1_BSTL_DISABLE
- RV_PWRM1_BSTL_ENABLE
- RV_PWRM1_BSTR_DISABLE
- RV_PWRM1_BSTR_ENABLE
- RV_PWRM1_DIGENB_DISABLE
- RV_PWRM1_DIGENB_ENABLE
- RV_PWRM1_MICB_DISABLE
- RV_PWRM1_MICB_ENABLE
- RV_PWRM1_PGAL_DISABLE
- RV_PWRM1_PGAL_ENABLE
- RV_PWRM1_PGAR_DISABLE
- RV_PWRM1_PGAR_ENABLE
- RV_PWRM2_D2S_DISABLE
- RV_PWRM2_D2S_ENABLE
- RV_PWRM2_HPL_DISABLE
- RV_PWRM2_HPL_ENABLE
- RV_PWRM2_HPR_DISABLE
- RV_PWRM2_HPR_ENABLE
- RV_PWRM2_INSELL_DISABLE
- RV_PWRM2_INSELL_ENABLE
- RV_PWRM2_INSELR_DISABLE
- RV_PWRM2_INSELR_ENABLE
- RV_PWRM2_SPKL_DISABLE
- RV_PWRM2_SPKL_ENABLE
- RV_PWRM2_SPKR_DISABLE
- RV_PWRM2_SPKR_ENABLE
- RV_PWRM2_VREF_DISABLE
- RV_PWRM2_VREF_ENABLE
- RV_REG_A0
- RV_REG_A1
- RV_REG_A2
- RV_REG_A3
- RV_REG_A4
- RV_REG_A5
- RV_REG_A6
- RV_REG_A7
- RV_REG_FP
- RV_REG_GP
- RV_REG_RA
- RV_REG_S1
- RV_REG_S10
- RV_REG_S11
- RV_REG_S2
- RV_REG_S3
- RV_REG_S4
- RV_REG_S5
- RV_REG_S6
- RV_REG_S7
- RV_REG_S8
- RV_REG_S9
- RV_REG_SP
- RV_REG_T0
- RV_REG_T1
- RV_REG_T2
- RV_REG_T3
- RV_REG_T4
- RV_REG_T5
- RV_REG_T6
- RV_REG_TCC
- RV_REG_TCC_SAVED
- RV_REG_TP
- RV_REG_ZERO
- RV_RESET_ENABLE
- RV_RSVD17
- RV_RSVD24
- RV_RSVD25
- RV_RSVD26
- RV_RSVD27
- RV_SECREL
- RV_SEGREL
- RV_SPECIAL
- RV_SPKVOLL_MUTE
- RV_SPKVOLL_N77PT25DB
- RV_SPKVOLL_P12DB
- RV_SPKVOLR_MUTE
- RV_SPKVOLR_N77PT25DB
- RV_SPKVOLR_P12DB
- RV_TPREL
- RVi
- RVij
- RW
- RW0
- RW0bh
- RW0bl
- RW0d
- RW1
- RW1bh
- RW1bl
- RW1d
- RW2
- RW2bh
- RW2bl
- RW2d
- RWAKE
- RWBS_LEN
- RWB_DEF_DEPTH
- RWB_MIN_WRITE_SAMPLES
- RWB_UNKNOWN_BUMP
- RWB_WINDOW_NSEC
- RWCAM
- RWCAM_8723B
- RWC_BITS
- RWDEBUG
- RWDLEN1
- RWDLEN2
- RWDT_DEFAULT_TIMEOUT
- RWE
- RWE_MASK
- RWE_SHIFT
- RWF_APPEND
- RWF_DSYNC
- RWF_HIPRI
- RWF_NOWAIT
- RWF_STM_RD
- RWF_STM_WT
- RWF_SUPPORTED
- RWF_SYNC
- RWF_WRITE_LIFE_NOT_SET
- RWGE
- RWGE_MASK
- RWGE_SHIFT
- RWH_WRITE_LIFE_EXTREME
- RWH_WRITE_LIFE_LONG
- RWH_WRITE_LIFE_MEDIUM
- RWH_WRITE_LIFE_NONE
- RWH_WRITE_LIFE_SHORT
- RWI
- RWK
- RWKAR
- RWKCNT
- RWLOCK_BUG_ON
- RWLOCK_MAGIC
- RWMR_RPA_P8_1THREAD
- RWMR_RPA_P8_2THREAD
- RWMR_RPA_P8_3THREAD
- RWMR_RPA_P8_4THREAD
- RWMR_RPA_P8_5THREAD
- RWMR_RPA_P8_6THREAD
- RWMR_RPA_P8_7THREAD
- RWMR_RPA_P8_8THREAD
- RWPF_MIN_HEIGHT
- RWPF_MIN_WIDTH
- RWPF_PAD_SINK
- RWPF_PAD_SOURCE
- RWPTR_DISTANCE
- RWPTR_NEXT
- RWPTR_PREV
- RWSEM_FLAG_HANDOFF
- RWSEM_FLAG_READFAIL
- RWSEM_FLAG_WAITERS
- RWSEM_LOCK_MASK
- RWSEM_NONSPINNABLE
- RWSEM_OWNER_FLAGS_MASK
- RWSEM_OWNER_UNKNOWN
- RWSEM_RD_NONSPINNABLE
- RWSEM_READER_BIAS
- RWSEM_READER_MASK
- RWSEM_READER_OWNED
- RWSEM_READER_SHIFT
- RWSEM_READ_FAILED_MASK
- RWSEM_UNLOCKED_VALUE
- RWSEM_WAITING_FOR_READ
- RWSEM_WAITING_FOR_WRITE
- RWSEM_WAIT_TIMEOUT
- RWSEM_WAKE_ANY
- RWSEM_WAKE_READERS
- RWSEM_WAKE_READ_OWNED
- RWSEM_WRITER_LOCKED
- RWSEM_WRITER_MASK
- RWSEM_WR_NONSPINNABLE
- RWSI
- RWSIG_ACTION_ABORT
- RWSIG_ACTION_CONTINUE
- RWTCNT
- RWTCSRA
- RWTCSRA_ADDRESS
- RWTCSRA_TME
- RWTCSRA_WOVF
- RWTCSRA_WRFLG
- RWTCSRB
- RWTM_HOST_INT_MASK
- RWTM_HOST_INT_RESET
- RWTM_MBOX_COMMAND
- RWTM_MBOX_FIFO_STATUS
- RWTM_MBOX_PARAM
- RWTM_MBOX_RETURN_STATUS
- RWTM_MBOX_STATUS
- RWUPE
- RWVMID
- RWVMID_MASK
- RWVMID_SHIFT
- RWW_CFG
- RWW_CTRL
- RW_040
- RW_ATTR
- RW_BIO
- RW_DATA_SECTION
- RW_DEP_MAP_INIT
- RW_DFET
- RW_I0
- RW_I1
- RW_I2
- RW_I3
- RW_I4
- RW_I5
- RW_I6
- RW_I7
- RW_IFET
- RW_L0
- RW_L1
- RW_L2
- RW_L3
- RW_L4
- RW_L5
- RW_L6
- RW_L7
- RW_LOCK_BIAS
- RW_OP
- RW_PDFET
- RW_RECOVERY_MPAGE
- RW_RECOVERY_MPAGE_LEN
- RW_RELEASE_EN
- RW_SDFET
- RW_SENSOR_TEMPLATE
- RW_STATE_LSB
- RW_STATE_MSB
- RW_STATE_WORD0
- RW_STATE_WORD1
- RW_V9_I0
- RW_V9_I1
- RW_V9_I2
- RW_V9_I3
- RW_V9_I4
- RW_V9_I5
- RW_V9_I6
- RW_V9_I7
- RW_V9_L0
- RW_V9_L1
- RW_V9_L2
- RW_V9_L3
- RW_V9_L4
- RW_V9_L5
- RW_V9_L6
- RW_V9_L7
- RW_WDFET
- RX
- RX0
- RX0BYTE_EP1
- RX0BYTE_EP2
- RX0BYTE_EP3
- RX0BYTE_EP4
- RX0BYTE_EP5
- RX0BYTE_EP6
- RX0BYTE_EP7
- RX0BYTE_EP8
- RX0PKTNUM
- RX0_A_MARK
- RX0_B_MARK
- RX0_C_MARK
- RX0_DISABLE_STATE
- RX0_D_MARK
- RX0_ENABLE_STATE
- RX0_E_MARK
- RX0_MARK
- RX0_SLEEP_STATE
- RX0_SNOOZE_STATE
- RX0_UDT_SIZE
- RX0bh
- RX0bl
- RX0d
- RX1
- RX128_INT_EN
- RX1MATCH
- RX1PKTNUM
- RX1_A_MARK
- RX1_B_MARK
- RX1_C_MARK
- RX1_D_MARK
- RX1_E_MARK
- RX1_MARK
- RX1bh
- RX1bl
- RX1d
- RX2
- RX2MATCH
- RX2_A_MARK
- RX2_B_MARK
- RX2_C_MARK
- RX2_D_MARK
- RX2_E_MARK
- RX2_MARK
- RX2bh
- RX2bl
- RX2d
- RX3
- RX3_A_MARK
- RX3_B_IRDA_RX_B_MARK
- RX3_B_MARK
- RX3_C_IRDA_RX_C_MARK
- RX3_C_MARK
- RX3_D_IRDA_RX_D_MARK
- RX3_D_MARK
- RX3_E_IRDA_RX_E_MARK
- RX3_E_MARK
- RX3_IRDA_RX_MARK
- RX3_MARK
- RX3bh
- RX3bl
- RX3d
- RX4581_CTRL_AIE
- RX4581_CTRL_RESET
- RX4581_CTRL_STOP
- RX4581_CTRL_TIE
- RX4581_CTRL_UIE
- RX4581_FLAG_AF
- RX4581_FLAG_TF
- RX4581_FLAG_UF
- RX4581_FLAG_VLF
- RX4581_REG_ADM
- RX4581_REG_ADW
- RX4581_REG_AHR
- RX4581_REG_AMN
- RX4581_REG_CTRL
- RX4581_REG_DM
- RX4581_REG_DW
- RX4581_REG_EXT
- RX4581_REG_FLAG
- RX4581_REG_HR
- RX4581_REG_MN
- RX4581_REG_MO
- RX4581_REG_RAM
- RX4581_REG_SC
- RX4581_REG_TMR0
- RX4581_REG_TMR1
- RX4581_REG_YR
- RX4_A_MARK
- RX4_B_MARK
- RX4_C_MARK
- RX4_D_MARK
- RX4_E_MARK
- RX4_MARK
- RX51_JACK_DISABLED
- RX51_JACK_HP
- RX51_JACK_HS
- RX51_JACK_TVOUT
- RX51_PPA_HWRNG
- RX51_PPA_L2_INVAL
- RX51_PPA_WRITE_ACR
- RX5_A_MARK
- RX5_B_MARK
- RX5_C_MARK
- RX5_D_MARK
- RX5_E_MARK
- RX5_F_MARK
- RX5_MARK
- RX6110_BIT_ALARM_EN
- RX6110_BIT_CTRL_AIE
- RX6110_BIT_CTRL_STOP
- RX6110_BIT_CTRL_TBKE
- RX6110_BIT_CTRL_TBKON
- RX6110_BIT_CTRL_TEST
- RX6110_BIT_CTRL_TIE
- RX6110_BIT_CTRL_TSTP
- RX6110_BIT_CTRL_UIE
- RX6110_BIT_EXT_FSEL0
- RX6110_BIT_EXT_FSEL1
- RX6110_BIT_EXT_TE
- RX6110_BIT_EXT_TSEL0
- RX6110_BIT_EXT_TSEL1
- RX6110_BIT_EXT_TSEL2
- RX6110_BIT_EXT_USEL
- RX6110_BIT_EXT_WADA
- RX6110_BIT_FLAG_AF
- RX6110_BIT_FLAG_TF
- RX6110_BIT_FLAG_UF
- RX6110_BIT_FLAG_VLF
- RX6110_DRIVER_NAME
- RX6110_REG_ALHOUR
- RX6110_REG_ALMIN
- RX6110_REG_ALWDAY
- RX6110_REG_CTRL
- RX6110_REG_EXT
- RX6110_REG_FLAG
- RX6110_REG_HOUR
- RX6110_REG_IRQ
- RX6110_REG_MDAY
- RX6110_REG_MIN
- RX6110_REG_MONTH
- RX6110_REG_RES1
- RX6110_REG_RES2
- RX6110_REG_RES3
- RX6110_REG_SEC
- RX6110_REG_TCOUNT0
- RX6110_REG_TCOUNT1
- RX6110_REG_USER0
- RX6110_REG_USER1
- RX6110_REG_USER2
- RX6110_REG_USER3
- RX6110_REG_USER4
- RX6110_REG_USER5
- RX6110_REG_USER6
- RX6110_REG_USER7
- RX6110_REG_USER8
- RX6110_REG_USER9
- RX6110_REG_USERA
- RX6110_REG_USERB
- RX6110_REG_USERC
- RX6110_REG_USERD
- RX6110_REG_USERE
- RX6110_REG_USERF
- RX6110_REG_WDAY
- RX6110_REG_YEAR
- RX71_FM_I2C_ADDR
- RX8010_ALARM_AE
- RX8010_ALHOUR
- RX8010_ALMIN
- RX8010_ALWDAY
- RX8010_CTRL
- RX8010_CTRL_AIE
- RX8010_CTRL_STOP
- RX8010_CTRL_TEST
- RX8010_CTRL_UIE
- RX8010_EXT
- RX8010_EXT_WADA
- RX8010_FLAG
- RX8010_FLAG_AF
- RX8010_FLAG_TF
- RX8010_FLAG_UF
- RX8010_FLAG_VLF
- RX8010_HOUR
- RX8010_IRQ
- RX8010_MDAY
- RX8010_MIN
- RX8010_MONTH
- RX8010_RESV17
- RX8010_RESV30
- RX8010_RESV31
- RX8010_SEC
- RX8010_TCOUNT0
- RX8010_TCOUNT1
- RX8010_WDAY
- RX8010_YEAR
- RX8025_ADJ_DATA_MAX
- RX8025_ADJ_DATA_MIN
- RX8025_ADJ_RESOLUTION
- RX8025_BIT_2412
- RX8025_BIT_CTRL1_1224
- RX8025_BIT_CTRL1_CT
- RX8025_BIT_CTRL1_CT_1HZ
- RX8025_BIT_CTRL1_DALE
- RX8025_BIT_CTRL1_TEST
- RX8025_BIT_CTRL1_WALE
- RX8025_BIT_CTRL2_CTFG
- RX8025_BIT_CTRL2_DAFG
- RX8025_BIT_CTRL2_PON
- RX8025_BIT_CTRL2_VDET
- RX8025_BIT_CTRL2_WAFG
- RX8025_BIT_CTRL2_XST
- RX8025_BIT_PON
- RX8025_BIT_VDET
- RX8025_BIT_XST
- RX8025_REG_ALDHOUR
- RX8025_REG_ALDMIN
- RX8025_REG_ALWHOUR
- RX8025_REG_ALWMIN
- RX8025_REG_ALWWDAY
- RX8025_REG_CTRL1
- RX8025_REG_CTRL2
- RX8025_REG_DIGOFF
- RX8025_REG_HOUR
- RX8025_REG_MDAY
- RX8025_REG_MIN
- RX8025_REG_MONTH
- RX8025_REG_SEC
- RX8025_REG_WDAY
- RX8025_REG_YEAR
- RX8130_REG_ALARM_HOUR
- RX8130_REG_ALARM_MIN
- RX8130_REG_ALARM_WEEK_OR_DAY
- RX8130_REG_CONTROL0
- RX8130_REG_CONTROL0_AIE
- RX8130_REG_EXTENSION
- RX8130_REG_EXTENSION_WADA
- RX8130_REG_FLAG
- RX8130_REG_FLAG_AF
- RX8130_REG_FLAG_VLF
- RX8571_NVRAM_SIZE
- RX8571_USER_RAM
- RX8581_CTRL_AIE
- RX8581_CTRL_RESET
- RX8581_CTRL_STOP
- RX8581_CTRL_TIE
- RX8581_CTRL_UIE
- RX8581_FLAG_AF
- RX8581_FLAG_TF
- RX8581_FLAG_UF
- RX8581_FLAG_VLF
- RX8581_REG_ADM
- RX8581_REG_ADW
- RX8581_REG_AHR
- RX8581_REG_AMN
- RX8581_REG_CTRL
- RX8581_REG_DM
- RX8581_REG_DW
- RX8581_REG_EXT
- RX8581_REG_FLAG
- RX8581_REG_HR
- RX8581_REG_MN
- RX8581_REG_MO
- RX8581_REG_RAM
- RX8581_REG_SC
- RX8581_REG_TMR0
- RX8581_REG_TMR1
- RX8581_REG_YR
- RX8900_BACKUP_CTRL
- RX8900_FLAG_SWOFF
- RX8900_FLAG_VDETOFF
- RXABTIE
- RXABTIF
- RXAC
- RXACKE
- RXACTIVE_SHIFT
- RXADDR1_OAM_PRESERVE
- RXADDR1_SET_MODE
- RXADDR1_SET_RMMODE
- RXADDR1_SET_SIZE
- RXAEQ_MODE_AUTO
- RXAEQ_MODE_MANUAL
- RXAEQ_MODE_OFF
- RXALCR0
- RXALCR1
- RXAVAIL
- RXBAF
- RXBCTRL
- RXBCTRL_BUKT
- RXBCTRL_OFF
- RXBCTRL_RXM0
- RXBCTRL_RXM1
- RXBDAT_OFF
- RXBDLC
- RXBDLC_LEN_MASK
- RXBDLC_OFF
- RXBDLC_RTR
- RXBD_BROADCAST
- RXBD_CRCERR
- RXBD_EMPTY
- RXBD_ERR
- RXBD_FIRST
- RXBD_INTERRUPT
- RXBD_LARGE
- RXBD_LAST
- RXBD_MISS
- RXBD_MULTICAST
- RXBD_NONOCTET
- RXBD_OVERRUN
- RXBD_RING_SIZE
- RXBD_RO1
- RXBD_SHORT
- RXBD_STATS
- RXBD_TRUNCATED
- RXBD_WRAP
- RXBEID0
- RXBEID0_OFF
- RXBEID8
- RXBEID8_OFF
- RXBF
- RXBIT
- RXBNAE
- RXBND
- RXBPDU_EN
- RXBR
- RXBREAK
- RXBSIDH
- RXBSIDH_OFF
- RXBSIDH_SHIFT
- RXBSIDL
- RXBSIDL_EID
- RXBSIDL_IDE
- RXBSIDL_OFF
- RXBSIDL_SHIFT
- RXBSIDL_SRR
- RXBUF
- RXBUFFER_BASE
- RXBUFSTART_CI
- RXBUFSTART_CLP
- RXBUFSZ
- RXBUF_ALIGNMENT
- RXBUF_PAUSE_OFF_THRESH
- RXBUF_PAUSE_THRESH
- RXBUSY
- RXB_ELEMENT_SIZE
- RXB_FP
- RXB_RQ
- RXC0_LAN_LOAD
- RXC0_MODE_CM
- RXC0_MODE_OFF
- RXC0_MODE_RSSI
- RXC0_OFF_ADJ_MASK
- RXC0_RSSI_RST
- RXCALCTRL
- RXCDRCALFOSC0
- RXCEIE
- RXCF
- RXCFF_EMPTY_INT
- RXCFF_FULL_INT
- RXCFG
- RXCFG_AEP
- RXCFG_AIRL
- RXCFG_ALP
- RXCFG_ARP
- RXCFG_DMA_SHIFT
- RXCFG_DRTH
- RXCFG_DRTH0
- RXCFG_FIFO_SHIFT
- RXCFG_MXDMA512
- RXCFG_RX_FD
- RXCFG_STRIPCRC
- RXCF_ADDR
- RXCHAIN_DEF
- RXCHAIN_DEF_HTPHY
- RXCHAIN_DEF_NPHY
- RXCHAN
- RXCHECKSUM_ERROR
- RXCHK_BAD_CSUM_CNTR
- RXCHK_BAD_CSUM_DIS
- RXCHK_BRCM_TAG
- RXCHK_BRCM_TAG0
- RXCHK_BRCM_TAG0_MASK
- RXCHK_BRCM_TAG_CID_MASK
- RXCHK_BRCM_TAG_CID_SHIFT
- RXCHK_BRCM_TAG_EN
- RXCHK_BRCM_TAG_MASK
- RXCHK_BRCM_TAG_MATCH_MASK
- RXCHK_BRCM_TAG_MATCH_SHIFT
- RXCHK_BRCM_TAG_MATCH_STATUS
- RXCHK_BRCM_TAG_MAX
- RXCHK_CONTROL
- RXCHK_EN
- RXCHK_ETHERTYPE
- RXCHK_ETHERTYPE_DIS
- RXCHK_INCOM_PKT
- RXCHK_L2_HDR_DIS
- RXCHK_L3_HDR_DIS
- RXCHK_MAC_RX_ERR_DIS
- RXCHK_OTHER_DISC_CNTR
- RXCHK_PARSE_AUTH
- RXCHK_PARSE_TNL
- RXCHK_SKIP_FCS
- RXCHK_V6_DUPEXT_DIS
- RXCHK_V6_DUPEXT_EN
- RXCHK_VIOL_DIS
- RXCHK_VIOL_EN
- RXCLKRST
- RXCLK_RCD
- RXCOL
- RXCONFIG_ALLMULTI
- RXCONFIG_CAM_ABSENT
- RXCONFIG_DBCAST
- RXCONFIG_FLOW
- RXCONFIG_FLOW_ACCEPT
- RXCONFIG_LPBACK
- RXCONFIG_NORX_WHILE_TX
- RXCONFIG_PROMISC
- RXCONFIG_RFILT
- RXCON_CLOSE
- RXCPLPERR_F
- RXCPLPERR_S
- RXCPLPERR_V
- RXCR1_FILTER_MASK
- RXCR1_FRXQ
- RXCR1_RXAE
- RXCR1_RXBE
- RXCR1_RXE
- RXCR1_RXEFE
- RXCR1_RXFCE
- RXCR1_RXINVF
- RXCR1_RXIPFCC
- RXCR1_RXMAFMA
- RXCR1_RXME
- RXCR1_RXPAFMA
- RXCR1_RXTCPFCC
- RXCR1_RXUDPFCC
- RXCR1_RXUE
- RXCR2_IUFFP
- RXCR2_RXICMPFCC
- RXCR2_RXIUFCEZ
- RXCR2_RXSAF
- RXCR2_SRDBL_16B
- RXCR2_SRDBL_32B
- RXCR2_SRDBL_4B
- RXCR2_SRDBL_8B
- RXCR2_SRDBL_FRAME
- RXCR2_SRDBL_MASK
- RXCR2_SRDBL_SHIFT
- RXCR2_UDPLFE
- RXCRCCALC
- RXCRCEXCL
- RXCRCINIT
- RXCR_MASK
- RXCSR0
- RXCSR0_DISABLE_RX
- RXCSR0_DROP_BCAST
- RXCSR0_DROP_CONTROL
- RXCSR0_DROP_CRC
- RXCSR0_DROP_MCAST
- RXCSR0_DROP_NOT_TO_ME
- RXCSR0_DROP_PHYSICAL
- RXCSR0_DROP_TODS
- RXCSR0_DROP_VERSION_ERROR
- RXCSR0_ENABLE_QOS
- RXCSR0_PASS_CRC
- RXCSR0_PASS_PLCP
- RXCSR1
- RXCSR1_NUM_RXD
- RXCSR1_RXD_SIZE
- RXCSR2
- RXCSR2_RX_RING_REGISTER
- RXCSR3
- RXCSR3_BBP_ID0
- RXCSR3_BBP_ID0_VALID
- RXCSR3_BBP_ID1
- RXCSR3_BBP_ID1_VALID
- RXCSR3_BBP_ID2
- RXCSR3_BBP_ID2_VALID
- RXCSR3_BBP_ID3
- RXCSR3_BBP_ID3_VALID
- RXCSR4
- RXCSR4_BBP_ID4
- RXCSR4_BBP_ID4_VALID
- RXCSR4_BBP_ID5
- RXCSR4_BBP_ID5_VALID
- RXCS_ABORT
- RXCS_DEFAULT
- RXCS_DMAREQSZ
- RXCS_DMAREQSZ_128B
- RXCS_DMAREQSZ_16B
- RXCS_DMAREQSZ_32B
- RXCS_DMAREQSZ_64B
- RXCS_ENABLE
- RXCS_FIFOTHNP
- RXCS_FIFOTHNP_128QW
- RXCS_FIFOTHNP_16QW
- RXCS_FIFOTHNP_32QW
- RXCS_FIFOTHNP_64QW
- RXCS_FIFOTHTP
- RXCS_FIFOTHTP_128T
- RXCS_FIFOTHTP_16T
- RXCS_FIFOTHTP_32T
- RXCS_FIFOTHTP_64T
- RXCS_MAGIC
- RXCS_QST
- RXCS_QUEUESEL
- RXCS_QUEUESEL_Q0
- RXCS_QUEUESEL_Q1
- RXCS_QUEUESEL_Q2
- RXCS_QUEUESEL_Q3
- RXCS_RETRYCNT
- RXCS_RETRYCNT_0
- RXCS_RETRYCNT_12
- RXCS_RETRYCNT_16
- RXCS_RETRYCNT_20
- RXCS_RETRYCNT_24
- RXCS_RETRYCNT_28
- RXCS_RETRYCNT_32
- RXCS_RETRYCNT_36
- RXCS_RETRYCNT_4
- RXCS_RETRYCNT_40
- RXCS_RETRYCNT_44
- RXCS_RETRYCNT_48
- RXCS_RETRYCNT_52
- RXCS_RETRYCNT_56
- RXCS_RETRYCNT_60
- RXCS_RETRYCNT_8
- RXCS_RETRYGAP
- RXCS_RETRYGAP_1024ns
- RXCS_RETRYGAP_16384ns
- RXCS_RETRYGAP_2048ns
- RXCS_RETRYGAP_256ns
- RXCS_RETRYGAP_32768ns
- RXCS_RETRYGAP_4096ns
- RXCS_RETRYGAP_512ns
- RXCS_RETRYGAP_8192ns
- RXCS_SHORT
- RXCS_SUSPEND
- RXCS_WAKEUP
- RXCTL_DMWTLAT
- RXCV
- RXCWP
- RXC_DQSISEL
- RXC_RST
- RXD
- RXD0_MARK
- RXD1_MARK
- RXD2_MARK
- RXD3_MARK
- RXD4_MARK
- RXD5_MARK
- RXD6_MARK
- RXD7_MARK
- RXDATA
- RXDATA0
- RXDATA1
- RXDATADMADIS
- RXDCTRL_ALTMAC
- RXDCTRL_BAD
- RXDCTRL_BUFSZ
- RXDCTRL_FRESH
- RXDCTRL_HASHVAL
- RXDCTRL_HPASS
- RXDCTRL_OWN
- RXDCTRL_TCPCSUM
- RXDEBUG
- RXDES0_ANY_ERROR
- RXDESC1_END_RING
- RXDESC_CONTROL_INT
- RXDESC_CONTROL_SIZE
- RXDESC_CRC_ERR
- RXDESC_DA_FILTER_FAIL
- RXDESC_DESCRIPTOR_ERR
- RXDESC_ERROR_SUMMARY
- RXDESC_EXT_STATUS
- RXDESC_FIRST_SEG
- RXDESC_FRAME_LEN_MASK
- RXDESC_FRAME_LEN_OFFSET
- RXDESC_FRAME_TYPE
- RXDESC_GIANT_FRAME
- RXDESC_IPV4_PACKET
- RXDESC_IPV6_PACKET
- RXDESC_IP_HEADER_ERR
- RXDESC_IP_PAYLOAD_ERR
- RXDESC_IP_PAYLOAD_ICMP
- RXDESC_IP_PAYLOAD_MASK
- RXDESC_IP_PAYLOAD_TCP
- RXDESC_IP_PAYLOAD_UDP
- RXDESC_LAST_SEG
- RXDESC_LENGTH_ERR
- RXDESC_OFFSET
- RXDESC_OVERFLOW_ERR
- RXDESC_RX_ERR
- RXDESC_RX_WDOG
- RXDESC_SA_FILTER_FAIL
- RXDESC_SIZE
- RXDESC_VLAN_FRAME
- RXDET_SUCCESS_INTR
- RXDF
- RXDIRECTCTRL2
- RXDISABLE
- RXDMA
- RXDMABUFSIZE
- RXDMASIZE
- RXDMA_AGG_EN
- RXDMA_AGG_MODE_EN
- RXDMA_AGG_PG_TH
- RXDMA_ARBBW_EN
- RXDMA_BLANK
- RXDMA_BLANK_IPKTS
- RXDMA_BLANK_ITIME
- RXDMA_CFG
- RXDMA_CFG_BASE
- RXDMA_CFG_CSUMOFF
- RXDMA_CFG_ENABLE
- RXDMA_CFG_FBOFF
- RXDMA_CFG_FTHRESH
- RXDMA_CFG_FTHRESH_128
- RXDMA_CFG_FTHRESH_1K
- RXDMA_CFG_FTHRESH_256
- RXDMA_CFG_FTHRESH_2K
- RXDMA_CFG_FTHRESH_512
- RXDMA_CFG_FTHRESH_64
- RXDMA_CFG_RINGSZ
- RXDMA_CFG_RINGSZ_128
- RXDMA_CFG_RINGSZ_1K
- RXDMA_CFG_RINGSZ_256
- RXDMA_CFG_RINGSZ_2K
- RXDMA_CFG_RINGSZ_32
- RXDMA_CFG_RINGSZ_4K
- RXDMA_CFG_RINGSZ_512
- RXDMA_CFG_RINGSZ_64
- RXDMA_CFG_RINGSZ_8K
- RXDMA_CFG_RINGSZ_BDISAB
- RXDMA_CFIG1
- RXDMA_CFIG1_EN
- RXDMA_CFIG1_MBADDR_H
- RXDMA_CFIG1_QST
- RXDMA_CFIG1_RST
- RXDMA_CFIG2
- RXDMA_CFIG2_FULL_HDR
- RXDMA_CFIG2_MBADDR_L
- RXDMA_CFIG2_OFFSET
- RXDMA_CFIG2_OFFSET_SHIFT
- RXDMA_DBHI
- RXDMA_DBLOW
- RXDMA_DHIT0
- RXDMA_DHIT1
- RXDMA_DLOW
- RXDMA_DONE
- RXDMA_DPHI
- RXDMA_DPLOW
- RXDMA_EN
- RXDMA_FADDR
- RXDMA_FRPTR
- RXDMA_FSWPTR
- RXDMA_FSZ
- RXDMA_FTAG
- RXDMA_FWPTR
- RXDMA_IDLE
- RXDMA_INT_M
- RXDMA_INT_RC_INT_M
- RXDMA_INT_RDA_INT_M
- RXDMA_INT_RPA_INT_M
- RXDMA_INT_RTI_INT_M
- RXDMA_KICK
- RXDMA_PCNT
- RXDMA_PTHRESH
- RXDMA_PTHRESH_OFF
- RXDMA_PTHRESH_ON
- RXDMA_RXCTRL
- RXDMA_SMACHINE
- RXDMA_USB_AGG_ENABLE
- RXDONE_CRYPTO_ICV
- RXDONE_CRYPTO_IV
- RXDONE_L2PAD
- RXDONE_MY_BSS
- RXDONE_SIGNAL_BITRATE
- RXDONE_SIGNAL_MASK
- RXDONE_SIGNAL_MCS
- RXDONE_SIGNAL_PLCP
- RXDP
- RXDPIF
- RXDP_HI
- RXDRVINFO_SZ
- RXDSI_DATA_TYPE_NOT_REGOGNISED
- RXDSI_VC_ID_INVALID
- RXDV_GATED_EN
- RXDV_SPDWN_EN
- RXDY_GATED_EN
- RXD_DESC_SIZE
- RXD_DMA_DOWN_TIMER_MASK
- RXD_DMA_DOWN_TIMER_SHIFT
- RXD_DMA_THRESH_MASK
- RXD_DMA_THRESH_SHIFT
- RXD_ERR_BAD_CRC
- RXD_ERR_COLLISION
- RXD_ERR_HUGE_FRAME
- RXD_ERR_LINK_LOST
- RXD_ERR_MAC_ABRT
- RXD_ERR_MASK
- RXD_ERR_NO_RESOURCES
- RXD_ERR_ODD_NIBBLE_RCVD_MII
- RXD_ERR_PHY_DECODE
- RXD_ERR_TOO_SMALL
- RXD_FLAGS_SHIFT
- RXD_FLAG_END
- RXD_FLAG_ERROR
- RXD_FLAG_IP_CSUM
- RXD_FLAG_IS_TCP
- RXD_FLAG_JUMBO
- RXD_FLAG_MINI
- RXD_FLAG_PTPSTAT_MASK
- RXD_FLAG_PTPSTAT_PTPV1
- RXD_FLAG_PTPSTAT_PTPV2
- RXD_FLAG_TCPUDP_CSUM
- RXD_FLAG_VLAN
- RXD_FRAME_IP_FRAG
- RXD_FRAME_PROTO
- RXD_FRAME_PROTO_IPV4
- RXD_FRAME_PROTO_IPV6
- RXD_FRAME_PROTO_TCP
- RXD_FRAME_PROTO_UDP
- RXD_FRAME_VLAN_TAG
- RXD_GET_BUFFER0_SIZE_1
- RXD_GET_BUFFER0_SIZE_3
- RXD_GET_BUFFER1_SIZE_3
- RXD_GET_BUFFER2_SIZE_3
- RXD_GET_L3_CKSUM
- RXD_GET_L4_CKSUM
- RXD_GET_VLAN_TAG
- RXD_IDX_MASK
- RXD_IDX_SHIFT
- RXD_IPCSUM_MASK
- RXD_IPCSUM_SHIFT
- RXD_IS_UP2DT
- RXD_LENGTH
- RXD_LEN_MASK
- RXD_LEN_SHIFT
- RXD_MODE_1
- RXD_MODE_3B
- RXD_OPAQUE_INDEX_MASK
- RXD_OPAQUE_INDEX_SHIFT
- RXD_OPAQUE_RING_JUMBO
- RXD_OPAQUE_RING_MASK
- RXD_OPAQUE_RING_MINI
- RXD_OPAQUE_RING_STD
- RXD_OWN
- RXD_OWN_XENA
- RXD_PKT_SZ
- RXD_TCPCSUM_MASK
- RXD_TCPCSUM_SHIFT
- RXD_TH
- RXD_THRESHOLD_BMSK
- RXD_THRESHOLD_SHFT
- RXD_TIMER_BMSK
- RXD_TXD_COUNT
- RXD_TYPE_SHIFT
- RXD_T_CODE
- RXD_UPDATE
- RXD_VLAN_MASK
- RXD_W0_AMPDU
- RXD_W0_AMSDU
- RXD_W0_BA
- RXD_W0_BROADCAST
- RXD_W0_CIPHER
- RXD_W0_CIPHER_ALG
- RXD_W0_CIPHER_ERROR
- RXD_W0_CIPHER_OWNER
- RXD_W0_CRC_ERROR
- RXD_W0_DATA
- RXD_W0_DATABYTE_COUNT
- RXD_W0_DECRYPTED
- RXD_W0_DROP
- RXD_W0_FRAG
- RXD_W0_HTC
- RXD_W0_ICV_ERROR
- RXD_W0_IV_OFFSET
- RXD_W0_KEY_INDEX
- RXD_W0_L2PAD
- RXD_W0_LAST_AMSDU
- RXD_W0_MULTICAST
- RXD_W0_MY_BSS
- RXD_W0_NULLDATA
- RXD_W0_OFDM
- RXD_W0_OWNER_NIC
- RXD_W0_PHYSICAL_ERROR
- RXD_W0_PLCP_RSSI
- RXD_W0_PLCP_SIGNAL
- RXD_W0_RSSI
- RXD_W0_SDP0
- RXD_W0_UNICAST_TO_ME
- RXD_W10_DROP
- RXD_W10_RESERVED
- RXD_W11_RESERVED
- RXD_W12_RESERVED
- RXD_W13_RESERVED
- RXD_W14_RESERVED
- RXD_W15_RESERVED
- RXD_W1_BUFFER_ADDRESS
- RXD_W1_DMA_DONE
- RXD_W1_FRAME_OFFSET
- RXD_W1_LS0
- RXD_W1_RSSI
- RXD_W1_RSSI_AGC
- RXD_W1_RSSI_LNA
- RXD_W1_SDL0
- RXD_W1_SDL1
- RXD_W1_SIGNAL
- RXD_W2_BBR0
- RXD_W2_BUFFER_LENGTH
- RXD_W2_IV
- RXD_W2_RSSI
- RXD_W2_SDP1
- RXD_W2_SIGNAL
- RXD_W2_TA
- RXD_W3_AMPDU
- RXD_W3_AMSDU
- RXD_W3_BA
- RXD_W3_BBR3
- RXD_W3_BBR4
- RXD_W3_BBR5
- RXD_W3_BROADCAST
- RXD_W3_CIPHER_ERROR
- RXD_W3_CRC_ERROR
- RXD_W3_DATA
- RXD_W3_DECRYPTED
- RXD_W3_EIV
- RXD_W3_FRAG
- RXD_W3_HTC
- RXD_W3_L2PAD
- RXD_W3_MULTICAST
- RXD_W3_MY_BSS
- RXD_W3_NULLDATA
- RXD_W3_PLCP_RSSI
- RXD_W3_PLCP_SIGNAL
- RXD_W3_RSSI
- RXD_W3_TA
- RXD_W3_UNICAST_TO_ME
- RXD_W4_ICV
- RXD_W4_IV
- RXD_W4_RX_END_TIME
- RXD_W5_BUFFER_PHYSICAL_ADDRESS
- RXD_W5_EIV
- RXD_W5_RESERVED
- RXD_W6_KEY
- RXD_W6_RESERVED
- RXD_W7_KEY
- RXD_W7_RESERVED
- RXD_W8_KEY
- RXD_W8_RESERVED
- RXD_W9_KEY
- RXD_W9_RESERVED
- RXE
- RXE32_DEV_CNTR_ELEM
- RXE32_PORT_CNTR_ELEM
- RXE64_DEV_CNTR_ELEM
- RXE64_PORT_CNTR_ELEM
- RXECC_MULTIBIT_ERROR
- RXECC_SINGLE_BIT_ERROR
- RXEMEMPARITYERR_DATAINFO
- RXEMEMPARITYERR_EAGERTID
- RXEMEMPARITYERR_EXPTID
- RXEMEMPARITYERR_FLAGBUF
- RXEMEMPARITYERR_HDRINFO
- RXEMEMPARITYERR_LOOKUPQ
- RXEMEMPARITYERR_RCVBUF
- RXEMPTY
- RXEN
- RXENABLE
- RXEND
- RXEND_INIT
- RXENT_ENTRIES
- RXEN_SHIFT
- RXEOT_SYNC_ERROR
- RXEQ_DISABLE_MSECS
- RXEQ_INIT_RDESC
- RXEQ_ROWS
- RXEQ_SDR_DFELTH
- RXEQ_SDR_G1CNT_Z1CNT
- RXEQ_SDR_TLTH
- RXEQ_SDR_ZCNT
- RXEQ_VAL
- RXEQ_VAL_ALL
- RXER
- RXERROR_BREAK
- RXERROR_FRAMING
- RXERROR_OVERRUN
- RXERROR_PARITY
- RXERR_CCK_FALSE_ALARM
- RXERR_CCK_MPDU_FAIL
- RXERR_CCK_MPDU_OK
- RXERR_CCK_PPDU
- RXERR_COUNTER_MASK
- RXERR_CSUM_F
- RXERR_CSUM_S
- RXERR_CSUM_V
- RXERR_HT_FALSE_ALARM
- RXERR_HT_MPDU_FAIL
- RXERR_HT_MPDU_OK
- RXERR_HT_MPDU_TOTAL
- RXERR_HT_PPDU
- RXERR_OFDM_FALSE_ALARM
- RXERR_OFDM_MPDU_FAIL
- RXERR_OFDM_MPDU_OK
- RXERR_OFDM_PPDU
- RXERR_RPT
- RXERR_RPT_RST
- RXERR_RX_FULL_DROP
- RXERR_TYPE_CCK_FALSE_ALARM
- RXERR_TYPE_CCK_MPDU_FAIL
- RXERR_TYPE_CCK_MPDU_OK
- RXERR_TYPE_CCK_PPDU
- RXERR_TYPE_CCK_false_ALARM
- RXERR_TYPE_CCKfalse_ALARM
- RXERR_TYPE_HT_FALSE_ALARM
- RXERR_TYPE_HT_MPDU_FAIL
- RXERR_TYPE_HT_MPDU_OK
- RXERR_TYPE_HT_MPDU_TOTAL
- RXERR_TYPE_HT_PPDU
- RXERR_TYPE_HT_false_ALARM
- RXERR_TYPE_HTfalse_ALARM
- RXERR_TYPE_OFDM_FALSE_ALARM
- RXERR_TYPE_OFDM_MPDU_FAIL
- RXERR_TYPE_OFDM_MPDU_OK
- RXERR_TYPE_OFDM_PPDU
- RXERR_TYPE_OFDM_false_ALARM
- RXERR_TYPE_OFDMfalse_ALARM
- RXERR_TYPE_RX_FULL_DROP
- RXES
- RXESR_RDRBS
- RXESR_RDSTR
- RXESR_RDWBS
- RXESR_RFDBS
- RXEXCAPE_MODE_ENTRY_ERROR
- RXE_ACK_MASK
- RXE_AETH
- RXE_AETH_BYTES
- RXE_AETH_MASK
- RXE_ATMACK
- RXE_ATMACK_BYTES
- RXE_ATMACK_MASK
- RXE_ATMETH
- RXE_ATMETH_BYTES
- RXE_ATMETH_MASK
- RXE_ATOMIC_MASK
- RXE_BTH
- RXE_BTH_BYTES
- RXE_BTH_MASK
- RXE_BUF_PER_MAP
- RXE_CNT_COMPLETER_SCHED
- RXE_CNT_COMP_RETRY
- RXE_CNT_DUP_REQ
- RXE_CNT_LINK_DOWNED
- RXE_CNT_OUT_OF_SEQ_REQ
- RXE_CNT_RCVD_PKTS
- RXE_CNT_RCV_RNR
- RXE_CNT_RCV_SEQ_ERR
- RXE_CNT_RDMA_RECV
- RXE_CNT_RDMA_SEND
- RXE_CNT_RETRY_EXCEEDED
- RXE_CNT_RNR_RETRY_EXCEEDED
- RXE_CNT_SEND_ERR
- RXE_CNT_SENT_PKTS
- RXE_CNT_SND_RNR
- RXE_COMP_MASK
- RXE_DETH
- RXE_DETH_BYTES
- RXE_DETH_MASK
- RXE_DEVICE_CAP_FLAGS
- RXE_END_MASK
- RXE_ERR_INT
- RXE_FREEZE_ABORT_MASK
- RXE_FW_VER
- RXE_GRH
- RXE_GRH_MASK
- RXE_H
- RXE_HDR_H
- RXE_HW_COUNTERS_H
- RXE_HW_VER
- RXE_ICRC_SIZE
- RXE_IETH
- RXE_IETH_BYTES
- RXE_IETH_MASK
- RXE_IMMDT
- RXE_IMMDT_BYTES
- RXE_IMMDT_MASK
- RXE_INFLIGHT_SKBS_PER_QP_HIGH
- RXE_INFLIGHT_SKBS_PER_QP_LOW
- RXE_LOCAL_CA_ACK_DELAY
- RXE_LOC_H
- RXE_LOOPBACK_MASK
- RXE_LRH
- RXE_LRH_MASK
- RXE_MAX_AH
- RXE_MAX_CQ
- RXE_MAX_EE
- RXE_MAX_EE_INIT_RD_ATOM
- RXE_MAX_EE_RD_ATOM
- RXE_MAX_FMR
- RXE_MAX_FMR_PAGE_LIST_LEN
- RXE_MAX_HDR_LENGTH
- RXE_MAX_INLINE_DATA
- RXE_MAX_LOG_CQE
- RXE_MAX_MAP_PER_FMR
- RXE_MAX_MCAST_GRP
- RXE_MAX_MCAST_QP_ATTACH
- RXE_MAX_MR
- RXE_MAX_MR_INDEX
- RXE_MAX_MR_SIZE
- RXE_MAX_MW
- RXE_MAX_MW_INDEX
- RXE_MAX_PD
- RXE_MAX_PKEYS
- RXE_MAX_PKT_PER_ACK
- RXE_MAX_QP
- RXE_MAX_QP_INDEX
- RXE_MAX_QP_INIT_RD_ATOM
- RXE_MAX_QP_RD_ATOM
- RXE_MAX_QP_WR
- RXE_MAX_RAW_ETHY_QP
- RXE_MAX_RAW_IPV6_QP
- RXE_MAX_RDD
- RXE_MAX_RES_RD_ATOM
- RXE_MAX_SGE
- RXE_MAX_SGE_RD
- RXE_MAX_SRQ
- RXE_MAX_SRQ_INDEX
- RXE_MAX_SRQ_SGE
- RXE_MAX_SRQ_WR
- RXE_MAX_TOT_MCAST_QP_ATTACH
- RXE_MAX_UCONTEXT
- RXE_MAX_UNACKED_PSNS
- RXE_MEM_STATE_FREE
- RXE_MEM_STATE_INVALID
- RXE_MEM_STATE_VALID
- RXE_MEM_STATE_ZOMBIE
- RXE_MEM_TYPE_DMA
- RXE_MEM_TYPE_FMR
- RXE_MEM_TYPE_MR
- RXE_MEM_TYPE_MW
- RXE_MEM_TYPE_NONE
- RXE_MIDDLE_MASK
- RXE_MIN_MR_INDEX
- RXE_MIN_MW_INDEX
- RXE_MIN_QP_INDEX
- RXE_MIN_SRQ_INDEX
- RXE_MIN_SRQ_SGE
- RXE_MIN_SRQ_WR
- RXE_NET_H
- RXE_NSEC_ARB_TIMER_DELAY
- RXE_NUM_32_BIT_COUNTERS
- RXE_NUM_64_BIT_COUNTERS
- RXE_NUM_CONTEXTS
- RXE_NUM_DATA_VL
- RXE_NUM_OF_COUNTERS
- RXE_NUM_OPCODE
- RXE_NUM_PORT
- RXE_NUM_RSM_INSTANCES
- RXE_NUM_TID_FLOWS
- RXE_NUM_TYPES
- RXE_OPCODE_H
- RXE_PAGE_SIZE_CAP
- RXE_PARAM_H
- RXE_PARITY
- RXE_PAYLOAD
- RXE_PAYLOAD_MASK
- RXE_PER_CONTEXT_OFFSET
- RXE_PER_CONTEXT_SIZE
- RXE_PER_CONTEXT_USER
- RXE_POOL_ALIGN
- RXE_POOL_ATOMIC
- RXE_POOL_CACHE_FLAGS
- RXE_POOL_H
- RXE_POOL_INDEX
- RXE_POOL_KEY
- RXE_POOL_NO_ALLOC
- RXE_POOL_STATE_INVALID
- RXE_POOL_STATE_VALID
- RXE_PORT_ACTIVE_SPEED
- RXE_PORT_ACTIVE_WIDTH
- RXE_PORT_BAD_PKEY_CNTR
- RXE_PORT_GID_TBL_LEN
- RXE_PORT_INFO_MTU_CAP
- RXE_PORT_INFO_OPER_VL
- RXE_PORT_INFO_VL_CAP
- RXE_PORT_INIT_TYPE_REPLY
- RXE_PORT_LID
- RXE_PORT_LMC
- RXE_PORT_MAX_MSG_SZ
- RXE_PORT_MAX_VL_NUM
- RXE_PORT_PHYS_STATE
- RXE_PORT_PKEY_TBL_LEN
- RXE_PORT_PORT_CAP_FLAGS
- RXE_PORT_QKEY_VIOL_CNTR
- RXE_PORT_SM_LID
- RXE_PORT_SM_SL
- RXE_PORT_SUBNET_PREFIX
- RXE_PORT_SUBNET_TIMEOUT
- RXE_QUEUE_H
- RXE_RDETH
- RXE_RDETH_BYTES
- RXE_RDETH_MASK
- RXE_READ_MASK
- RXE_READ_OR_ATOMIC
- RXE_REQ_MASK
- RXE_RETH
- RXE_RETH_BYTES
- RXE_RETH_MASK
- RXE_ROCE_V2_SPORT
- RXE_RWR_MASK
- RXE_SEND_MASK
- RXE_START_MASK
- RXE_TASK_H
- RXE_TYPE_AH
- RXE_TYPE_CQ
- RXE_TYPE_MC_ELEM
- RXE_TYPE_MC_GRP
- RXE_TYPE_MR
- RXE_TYPE_MW
- RXE_TYPE_PD
- RXE_TYPE_QP
- RXE_TYPE_SRQ
- RXE_TYPE_UC
- RXE_UVERBS_ABI_VERSION
- RXE_VENDOR_ID
- RXE_VENDOR_PART_ID
- RXE_VERBS_H
- RXE_WRITE_MASK
- RXE_WRITE_OR_SEND
- RXF0_ELEMENT_SIZE
- RXF1_ELEMENT_SIZE
- RXFAF
- RXFALSE_CONTROL_ERROR
- RXFC
- RXFCB_CIP
- RXFCB_CSUM_MASK
- RXFCB_CTU
- RXFCB_EIP
- RXFCB_ETU
- RXFCB_IP
- RXFCB_IP6
- RXFCB_PERR_BADL3
- RXFCB_PERR_MASK
- RXFCB_TUP
- RXFCB_VLN
- RXFCR_NACK_EN_SHIFT
- RXFCR_OFFSET
- RXFCR_READ_COUNT_SHIFT
- RXFCTR_RXFCT_MASK
- RXFCTR_RXFCT_SHIFT
- RXFCTR_RXFC_GET
- RXFCTR_RXFC_MASK
- RXFCTR_RXFC_SHIFT
- RXFC_FS_MASK
- RXFC_FS_SHIFT
- RXFC_FWM_MASK
- RXFC_FWM_SHIFT
- RXFDPR_EMS
- RXFDPR_RXFPAI
- RXFDPR_RXFP_MASK
- RXFDPR_RXFP_SHIFT
- RXFDPR_WST
- RXFEID0
- RXFEID8
- RXFERR
- RXFF
- RXFF0_RDPTR
- RXFF0_WTPTR
- RXFF1_RDPTR
- RXFF1_WTPTR
- RXFFR
- RXFF_BNDY
- RXFF_STATUS
- RXFHBCR_CNT_MASK
- RXFID
- RXFIFO
- RXFIFOCSR
- RXFIFOH
- RXFIFORDOUT_OFFSET
- RXFIFO_EMPTY
- RXFIFO_ERR_DET
- RXFIFO_FL
- RXFIFO_HTHR_MASK
- RXFIFO_LTHR_MASK
- RXFIFO_PRTY_ERR_F
- RXFIFO_PRTY_ERR_S
- RXFIFO_PRTY_ERR_V
- RXFIFO_RD
- RXFIFO_RD_REQ
- RXFIFO_REG
- RXFIFO_REMPTY
- RXFIFO_SIZE
- RXFIFO_THR1_NORMAL
- RXFIFO_THR1_OOB
- RXFIFO_THR2_FULL
- RXFIFO_THR2_HIGH
- RXFIFO_THR2_NORMAL
- RXFIFO_THR2_OOB
- RXFIFO_THR3_FULL
- RXFIFO_THR3_HIGH
- RXFIFO_THR3_NORMAL
- RXFIFO_THR3_OOB
- RXFILTERMAP
- RXFILTERMAP_GP1
- RXFILTERMAP_GP2
- RXFILTERMAP_GP3
- RXFILTER_MULTI
- RXFILTER_NORMAL
- RXFILTER_PROMISC
- RXFL
- RXFLAGS
- RXFLAG_64BIT
- RXFLAG_CSUM
- RXFLAG_INT
- RXFLAG_OVERFLOW
- RXFLAG_OWN
- RXFLAG_SIZE
- RXFLOW_CNTL
- RXFLOW_DSR_SENSITIVITY
- RXFLOW_DTR
- RXFLOW_RTS
- RXFLOW_XOFF
- RXFLTMAP0
- RXFLTMAP1
- RXFLTMAP2
- RXFLTMAP3
- RXFL_MASK
- RXFOVERFL
- RXFRAME
- RXFRAME_ALIGN
- RXFRAME_ALIGN_SZ
- RXFREE_ENTRIES
- RXFREE_QUEUE
- RXFR_MASK
- RXFSD
- RXFSHR_RXBF
- RXFSHR_RXCE
- RXFSHR_RXFT
- RXFSHR_RXFTL
- RXFSHR_RXFV
- RXFSHR_RXICMPFCS
- RXFSHR_RXIPFCS
- RXFSHR_RXMF
- RXFSHR_RXMR
- RXFSHR_RXRF
- RXFSHR_RXTCPFCS
- RXFSHR_RXUDPFCS
- RXFSHR_RXUF
- RXFSID
- RXFSIDH
- RXFSIDL
- RXFSRST
- RXFS_FF
- RXFS_FFL_MASK
- RXFS_FGI_MASK
- RXFS_FGI_SHIFT
- RXFS_FPI_MASK
- RXFS_FPI_SHIFT
- RXFS_RFL
- RXFTHR_MODE_4X
- RXFTHR_MODE_MASK
- RXFULL
- RXFULL1
- RXF_DIFF_FROM_PREV
- RXF_DMA_IDLE
- RXF_DOF_THRESFHOLD
- RXF_DOF_THRESHOLD_BMSK
- RXF_DOF_THRESHOLD_SHFT
- RXF_E_CONFIG
- RXF_E_FAIL
- RXF_E_FW_RESP
- RXF_E_START
- RXF_E_STOP
- RXF_FCOE_F
- RXF_FCOE_S
- RXF_FCOE_V
- RXF_FIFO_RD_FENCE_ADDR
- RXF_FIFO_RD_FENCE_INC
- RXF_IP6_F
- RXF_IP6_S
- RXF_IP6_V
- RXF_IP_F
- RXF_IP_S
- RXF_IP_V
- RXF_LD_FENCE_OFFSET_ADDR
- RXF_LD_WR2FENCE
- RXF_LRO_F
- RXF_LRO_S
- RXF_LRO_V
- RXF_OF_INT
- RXF_PSH_F
- RXF_PSH_S
- RXF_PSH_V
- RXF_RD_D_SPACE
- RXF_RD_FENCE_PTR
- RXF_RD_RD_PTR
- RXF_RD_WR_PTR
- RXF_SET_FENCE_MODE
- RXF_SIZE_ADDR
- RXF_SIZE_BYTE_CND_POS
- RXF_SIZE_BYTE_CNT_MSK
- RXF_SYN_COOKIE_F
- RXF_SYN_COOKIE_S
- RXF_SYN_COOKIE_V
- RXF_SYN_F
- RXF_SYN_S
- RXF_SYN_V
- RXF_TCP_F
- RXF_TCP_S
- RXF_TCP_V
- RXF_TRIG
- RXF_UDP_F
- RXF_UDP_S
- RXF_UDP_V
- RXF_UOF_THRESFHOLD
- RXF_UOF_THRESHOLD_BMSK
- RXF_UOF_THRESHOLD_SHFT
- RXGEN_CC_MARSHAL
- RXGEN_CC_UNMARSHAL
- RXGEN_CC_XDRFREE
- RXGEN_DECODE
- RXGEN_OPCODE
- RXGEN_SS_MARSHAL
- RXGEN_SS_UNMARSHAL
- RXGEN_SS_XDRFREE
- RXGROUP
- RXGXS_ESTORE_OFLOW
- RXGXS_RX_SM_ERR
- RXHCLKRST
- RXHDR_CHAINCONTINUE
- RXHDR_LEN_MASK
- RXHDR_NEXT_ADDR_MASK
- RXHDR_NEXT_RECV_FLAG
- RXHDR_NEXT_VALID
- RXHDR_RECEIVE
- RXHPCRA0
- RXHP_T
- RXHSCTRL0
- RXHSSTATUS
- RXHS_RECEIVE_TIMEOUT_ERROR
- RXH_2TUPLE
- RXH_4TUPLE
- RXH_DISCARD
- RXH_IP_DST
- RXH_IP_SRC
- RXH_L2DA
- RXH_L3_PROTO
- RXH_L4_B_0_1
- RXH_L4_B_2_3
- RXH_VLAN
- RXI
- RXI1
- RXIC
- RXIDLE
- RXIENB
- RXIE_RES
- RXIE_SET
- RXIE_UNC
- RXINFO_DESC_SIZE
- RXINFO_W0_USB_DMA_RX_PKT_LEN
- RXINT
- RXINTE
- RXINT_CNT_MASK
- RXINT_EN
- RXINT_MASK
- RXINT_THR_MASK
- RXINT_TIME_SEL
- RXIQC_AC
- RXIQC_BD
- RXISERR
- RXJ_BAD
- RXJ_GOOD
- RXKADBADKEY
- RXKADBADTICKET
- RXKADDATALEN
- RXKADEXPIRED
- RXKADILLEGALLEVEL
- RXKADINCONSISTENCY
- RXKADLEVELFAIL
- RXKADNOAUTH
- RXKADOUTOFSEQUENCE
- RXKADPACKETSHORT
- RXKADSEALEDINCON
- RXKADTICKETLEN
- RXKADUNKNOWNKEY
- RXKAD_TKT_TYPE_KERBEROS_V5
- RXKAD_VERSION
- RXLBA
- RXLSD
- RXLSPPM
- RXMAC_ALIGN_ERR_CNT
- RXMAC_ALIGN_ERR_CNT_COUNT
- RXMAC_BC_FRM_CNT
- RXMAC_BC_FRM_CNT_COUNT
- RXMAC_BT_CNT
- RXMAC_BT_CNT_COUNT
- RXMAC_CD_VIO_CNT
- RXMAC_CD_VIO_CNT_COUNT
- RXMAC_CRC_ER_CNT
- RXMAC_CRC_ER_CNT_COUNT
- RXMAC_FRAG_CNT
- RXMAC_FRAG_CNT_COUNT
- RXMAC_HIST_CNT1
- RXMAC_HIST_CNT1_COUNT
- RXMAC_HIST_CNT2
- RXMAC_HIST_CNT2_COUNT
- RXMAC_HIST_CNT3
- RXMAC_HIST_CNT3_COUNT
- RXMAC_HIST_CNT4
- RXMAC_HIST_CNT4_COUNT
- RXMAC_HIST_CNT5
- RXMAC_HIST_CNT5_COUNT
- RXMAC_HIST_CNT6
- RXMAC_HIST_CNT6_COUNT
- RXMAC_HIST_CNT7
- RXMAC_HIST_CNT7_COUNT
- RXMAC_INT_M
- RXMAC_MC_FRM_CNT
- RXMAC_MC_FRM_CNT_COUNT
- RXMAC_MPSZER_CNT
- RXMAC_MPSZER_CNT_COUNT
- RXMASK_LEARNING
- RXMASK_REGULAR
- RXMAX
- RXMCS_ALLFRAME
- RXMCS_ALLMULFRAME
- RXMCS_BRDFRAME
- RXMCS_CHECKSUM
- RXMCS_DEFAULT
- RXMCS_FLOWCTRL
- RXMCS_MULFILTERED
- RXMCS_MULFRAME
- RXMCS_PREPAD
- RXMCS_RXCOLLDEC
- RXMCS_UNIFRAME
- RXMCS_VTAGRM
- RXMEID0
- RXMEID8
- RXMIN
- RXMISC
- RXMISC_COUNT
- RXMISC_OFLOW
- RXMODE_AAL0
- RXMODE_AAL5
- RXMODE_AAL5_STREAM
- RXMODE_ADDR
- RXMODE_BC_ADDR
- RXMODE_BC_MC_ADDR
- RXMODE_BYHAND
- RXMODE_DISABLE_802_3_HEADER
- RXMODE_DMA
- RXMODE_FULL_MASK
- RXMODE_LANMON
- RXMODE_MASK
- RXMODE_NORMALIZED_RSSI
- RXMODE_RFMON
- RXMODE_RFMON_ANYBSS
- RXMODE_TRASH
- RXMSIDH
- RXMSIDL
- RXNLCR0
- RXNLCR1
- RXOERR
- RXON
- RXON_CARD_DISABLED
- RXON_DEV_TYPE_2STA
- RXON_DEV_TYPE_AP
- RXON_DEV_TYPE_CP
- RXON_DEV_TYPE_ESS
- RXON_DEV_TYPE_IBSS
- RXON_DEV_TYPE_P2P
- RXON_DEV_TYPE_SNIFFER
- RXON_FILTER_ACCEPT_GRP_MSK
- RXON_FILTER_ASSOC_MSK
- RXON_FILTER_BCON_AWARE_MSK
- RXON_FILTER_CTL2HOST_MSK
- RXON_FILTER_DIS_DECRYPT_MSK
- RXON_FILTER_DIS_GRP_DECRYPT_MSK
- RXON_FILTER_PROMISC_MSK
- RXON_FLG_ANT_A_MSK
- RXON_FLG_ANT_B_MSK
- RXON_FLG_ANT_SEL_MSK
- RXON_FLG_AUTO_DETECT_MSK
- RXON_FLG_BAND_24G_MSK
- RXON_FLG_CCK_MSK
- RXON_FLG_CHANNEL_MODE_LEGACY
- RXON_FLG_CHANNEL_MODE_MIXED
- RXON_FLG_CHANNEL_MODE_MSK
- RXON_FLG_CHANNEL_MODE_POS
- RXON_FLG_CHANNEL_MODE_PURE_40
- RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK
- RXON_FLG_CTRL_CHANNEL_LOC_POS
- RXON_FLG_DIS_DIV_MSK
- RXON_FLG_HT40_PROT_MSK
- RXON_FLG_HT_OPERATING_MODE_POS
- RXON_FLG_HT_PROT_MSK
- RXON_FLG_RADAR_DETECT_MSK
- RXON_FLG_SELF_CTS_EN
- RXON_FLG_SHORT_PREAMBLE_MSK
- RXON_FLG_SHORT_SLOT_MSK
- RXON_FLG_TGG_PROTECT_MSK
- RXON_FLG_TGJ_NARROW_BAND_MSK
- RXON_FLG_TSF2HOST_MSK
- RXON_RX_CHAIN_CNT_MSK
- RXON_RX_CHAIN_CNT_POS
- RXON_RX_CHAIN_DRIVER_FORCE_MSK
- RXON_RX_CHAIN_DRIVER_FORCE_POS
- RXON_RX_CHAIN_FORCE_MIMO_SEL_MSK
- RXON_RX_CHAIN_FORCE_MIMO_SEL_POS
- RXON_RX_CHAIN_FORCE_SEL_MSK
- RXON_RX_CHAIN_FORCE_SEL_POS
- RXON_RX_CHAIN_MIMO_CNT_MSK
- RXON_RX_CHAIN_MIMO_CNT_POS
- RXON_RX_CHAIN_MIMO_FORCE_MSK
- RXON_RX_CHAIN_MIMO_FORCE_POS
- RXON_RX_CHAIN_VALID_MSK
- RXON_RX_CHAIN_VALID_POS
- RXOP_CHECK_CFG_H
- RXOR
- RXORD
- RXORbl
- RXORd
- RXOUTCFF_EMPTY_INT
- RXOUTCFF_FULL_INT
- RXOVER
- RXOVR
- RXOWN
- RXP
- RXPAD
- RXPARITY
- RXPATHSELECTION_DIFF_TH
- RXPATHSELECTION_SS_TH_LOW
- RXPATHSELECTION_SS_TH_W
- RXPAUS
- RXPBIT
- RXPDR
- RXPEIEC
- RXPEIEE
- RXPEN
- RXPF
- RXPF_ADDR
- RXPHY_BITMASK
- RXPI
- RXPKTCOUNT_LEN
- RXPKTCOUNT_POS
- RXPKTCPLMODE_F
- RXPKTCPLMODE_S
- RXPKTCPLMODE_SPLIT_X
- RXPKTCPLMODE_V
- RXPKT_BUF_SELECT
- RXPKT_NUM
- RXPKT_NUM_C2H
- RXPKT_NUM_RW_RELEASE_EN
- RXPKT_NUM_RXDMA_IDLE
- RXPKT_RELEASE_POLL
- RXPMD_REG_BANK
- RXPMD_RX_FREQ_MON_CONTROL1
- RXPNTR
- RXPOLL_CNT_MASK
- RXPOLL_CNT_SHIFT_BIT
- RXPOLL_TIME_SEL
- RXPRINTK
- RXPROC_EN
- RXPTR
- RXPTR_CSR
- RXQ0_NUM_RFD_PREF_DEF
- RXQ0_RSS_HSTYP_IPV4_EN
- RXQ0_RSS_HSTYP_IPV4_TCP_EN
- RXQ0_RSS_HSTYP_IPV6_EN
- RXQ0_RSS_HSTYP_IPV6_TCP_EN
- RXQCR_ADRFE
- RXQCR_CMD_CNTL
- RXQCR_RRXEF
- RXQCR_RXDBCTE
- RXQCR_RXDBCTS
- RXQCR_RXDTTE
- RXQCR_RXDTTS
- RXQCR_RXFCTE
- RXQCR_RXFCTS
- RXQCR_RXIPHTOE
- RXQCR_SDA
- RXQ_ATTN
- RXQ_CMD_RX
- RXQ_COMMAND
- RXQ_CSERR_INT
- RXQ_CTRL_CUT_THRU_EN
- RXQ_CTRL_EN
- RXQ_CTRL_HASH_ENABLE
- RXQ_CTRL_HASH_TLEN_MASK
- RXQ_CTRL_HASH_TLEN_SHIFT
- RXQ_CTRL_HASH_TYPE_IPV4
- RXQ_CTRL_HASH_TYPE_IPV4_TCP
- RXQ_CTRL_HASH_TYPE_IPV6
- RXQ_CTRL_HASH_TYPE_IPV6_TCP
- RXQ_CTRL_IPV6_XSUM_VERIFY_EN
- RXQ_CTRL_NIP_QUEUE_SEL_TBL
- RXQ_CTRL_PBA_ALIGN_128
- RXQ_CTRL_PBA_ALIGN_256
- RXQ_CTRL_PBA_ALIGN_32
- RXQ_CTRL_PBA_ALIGN_64
- RXQ_CTRL_Q1_EN
- RXQ_CTRL_Q2_EN
- RXQ_CTRL_Q3_EN
- RXQ_CTRL_RFD_BURST_NUM_MASK
- RXQ_CTRL_RFD_BURST_NUM_SHIFT
- RXQ_CTRL_RFD_PREF_MIN_IPG_MASK
- RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT
- RXQ_CTRL_RRD_BURST_THRESH_MASK
- RXQ_CTRL_RRD_BURST_THRESH_SHIFT
- RXQ_CTRL_RSS_MODE_DISABLE
- RXQ_CTRL_RSS_MODE_MQUEMINT
- RXQ_CTRL_RSS_MODE_MQUESINT
- RXQ_CTRL_RSS_MODE_SQSINT
- RXQ_CURRENT_DESC_PTR
- RXQ_DONE
- RXQ_EMPTY_INT
- RXQ_EN
- RXQ_ERR
- RXQ_GOOD
- RXQ_JMBOSZ_TH_MASK
- RXQ_JMBOSZ_TH_SHIFT
- RXQ_JMBO_LKAH_MASK
- RXQ_JMBO_LKAH_SHIFT
- RXQ_LENERR_INT
- RXQ_NUM
- RXQ_NUM_RFD_PREF_DEF
- RXQ_RFD_BURST_NUM_MASK
- RXQ_RFD_BURST_NUM_SHIFT
- RXQ_RRD_PAUSE_TH_HI_MASK
- RXQ_RRD_PAUSE_TH_HI_SHIFT
- RXQ_RRD_PAUSE_TH_LO_MASK
- RXQ_RRD_PAUSE_TH_LO_SHIFT
- RXQ_RRD_TIMER_MASK
- RXQ_RRD_TIMER_SHIFT
- RXQ_RSP
- RXQ_RXF_PAUSE_TH_HI_MASK
- RXQ_RXF_PAUSE_TH_HI_SHIFT
- RXQ_RXF_PAUSE_TH_LO_MASK
- RXQ_RXF_PAUSE_TH_LO_SHIFT
- RXQ_SLOT_MASK
- RXQ_SLOT_RESET
- RXQ_ZLPERR_INT
- RXR
- RXRDYE
- RXREJECT
- RXREOR_FORCE_NO_DROP
- RXREOR_INIT_WINDOW_SHIFT
- RXREPORT
- RXRESET
- RXRN_MASK
- RXROT
- RXRPC_ABORT
- RXRPC_ACCEPT
- RXRPC_ACK
- RXRPC_ACK_DELAY
- RXRPC_ACK_DUPLICATE
- RXRPC_ACK_EXCEEDS_WINDOW
- RXRPC_ACK_IDLE
- RXRPC_ACK_NOSPACE
- RXRPC_ACK_OUT_OF_SEQUENCE
- RXRPC_ACK_PING
- RXRPC_ACK_PING_RESPONSE
- RXRPC_ACK_REQUESTED
- RXRPC_ACK_TYPE_ACK
- RXRPC_ACK_TYPE_NACK
- RXRPC_ACK_UPDATEABLE
- RXRPC_ACK__INVALID
- RXRPC_ACTIVE_CHANS_MASK
- RXRPC_BACKLOG_MAX
- RXRPC_BUSY
- RXRPC_CALL_BEGAN_RX_TIMER
- RXRPC_CALL_CLIENT_AWAIT_CONN
- RXRPC_CALL_CLIENT_AWAIT_REPLY
- RXRPC_CALL_CLIENT_RECV_REPLY
- RXRPC_CALL_CLIENT_SEND_REQUEST
- RXRPC_CALL_COMPLETE
- RXRPC_CALL_CONGEST_AVOIDANCE
- RXRPC_CALL_DISCONNECTED
- RXRPC_CALL_EV_ABORT
- RXRPC_CALL_EV_ACK
- RXRPC_CALL_EV_ACK_LOST
- RXRPC_CALL_EV_EXPIRED
- RXRPC_CALL_EV_PING
- RXRPC_CALL_EV_RESEND
- RXRPC_CALL_EXPOSED
- RXRPC_CALL_FAST_RETRANSMIT
- RXRPC_CALL_HAS_USERID
- RXRPC_CALL_IS_SERVICE
- RXRPC_CALL_LOCALLY_ABORTED
- RXRPC_CALL_LOCAL_ERROR
- RXRPC_CALL_NETWORK_ERROR
- RXRPC_CALL_PACKET_LOSS
- RXRPC_CALL_PINGING
- RXRPC_CALL_RELEASED
- RXRPC_CALL_REMOTELY_ABORTED
- RXRPC_CALL_RETRANS_TIMEOUT
- RXRPC_CALL_RX_HEARD
- RXRPC_CALL_RX_LAST
- RXRPC_CALL_RX_UNDERRUN
- RXRPC_CALL_SEND_PING
- RXRPC_CALL_SERVER_ACCEPTING
- RXRPC_CALL_SERVER_ACK_REQUEST
- RXRPC_CALL_SERVER_AWAIT_ACK
- RXRPC_CALL_SERVER_PREALLOC
- RXRPC_CALL_SERVER_RECV_REQUEST
- RXRPC_CALL_SERVER_SECURING
- RXRPC_CALL_SERVER_SEND_REPLY
- RXRPC_CALL_SLOW_START
- RXRPC_CALL_SUCCEEDED
- RXRPC_CALL_TX_LAST
- RXRPC_CALL_UNINITIALISED
- RXRPC_CHANNELMASK
- RXRPC_CIDMASK
- RXRPC_CIDSHIFT
- RXRPC_CID_INC
- RXRPC_CLIENT_BOUND
- RXRPC_CLIENT_INITIATED
- RXRPC_CLIENT_UNBOUND
- RXRPC_CLOSE
- RXRPC_CMD_ACCEPT
- RXRPC_CMD_REJECT_BUSY
- RXRPC_CMD_SEND_ABORT
- RXRPC_CMD_SEND_DATA
- RXRPC_CONN_CLIENT
- RXRPC_CONN_CLIENT_ACTIVE
- RXRPC_CONN_CLIENT_CULLED
- RXRPC_CONN_CLIENT_IDLE
- RXRPC_CONN_CLIENT_INACTIVE
- RXRPC_CONN_CLIENT_UPGRADE
- RXRPC_CONN_CLIENT_WAITING
- RXRPC_CONN_COUNTED
- RXRPC_CONN_DONT_REUSE
- RXRPC_CONN_EV_CHALLENGE
- RXRPC_CONN_EXPOSED
- RXRPC_CONN_FINAL_ACK_0
- RXRPC_CONN_FINAL_ACK_1
- RXRPC_CONN_FINAL_ACK_2
- RXRPC_CONN_FINAL_ACK_3
- RXRPC_CONN_FINAL_ACK_MASK
- RXRPC_CONN_HAS_IDR
- RXRPC_CONN_IN_CLIENT_CONNS
- RXRPC_CONN_IN_SERVICE_CONNS
- RXRPC_CONN_LOCALLY_ABORTED
- RXRPC_CONN_PROBING_FOR_UPGRADE
- RXRPC_CONN_REMOTELY_ABORTED
- RXRPC_CONN_SERVICE
- RXRPC_CONN_SERVICE_CHALLENGING
- RXRPC_CONN_SERVICE_PREALLOC
- RXRPC_CONN_SERVICE_UNSECURED
- RXRPC_CONN_UNUSED
- RXRPC_CONN__NR_CACHE_STATES
- RXRPC_CONN__NR_STATES
- RXRPC_DEBUG_KDEBUG
- RXRPC_DEBUG_KENTER
- RXRPC_DEBUG_KLEAVE
- RXRPC_DEBUG_KNET
- RXRPC_DEBUG_KPROTO
- RXRPC_EXCLUSIVE_CALL
- RXRPC_EXCLUSIVE_CONNECTION
- RXRPC_INIT_RX_WINDOW_SIZE
- RXRPC_INTERRUPTIBLE
- RXRPC_JUMBO_DATALEN
- RXRPC_JUMBO_PACKET
- RXRPC_JUMBO_SUBPKTLEN
- RXRPC_KEEPALIVE_TIME
- RXRPC_LAST_PACKET
- RXRPC_LOCAL_ERROR
- RXRPC_MAXACKS
- RXRPC_MAXCALLS
- RXRPC_MAX_NR_JUMBO
- RXRPC_MIN_SECURITY_LEVEL
- RXRPC_MORE_PACKETS
- RXRPC_NET_ERROR
- RXRPC_NEW_CALL
- RXRPC_PACKET_TYPE_10
- RXRPC_PACKET_TYPE_11
- RXRPC_PACKET_TYPE_ABORT
- RXRPC_PACKET_TYPE_ACK
- RXRPC_PACKET_TYPE_ACKALL
- RXRPC_PACKET_TYPE_BUSY
- RXRPC_PACKET_TYPE_CHALLENGE
- RXRPC_PACKET_TYPE_DATA
- RXRPC_PACKET_TYPE_DEBUG
- RXRPC_PACKET_TYPE_PARAMS
- RXRPC_PACKET_TYPE_RESPONSE
- RXRPC_PACKET_TYPE_VERSION
- RXRPC_PREINTERRUPTIBLE
- RXRPC_RANDOM_EPOCH
- RXRPC_REQUEST_ACK
- RXRPC_RTO_MAX
- RXRPC_RTT_CACHE_SIZE
- RXRPC_RXTX_BUFF_MASK
- RXRPC_RXTX_BUFF_SIZE
- RXRPC_RX_ANNO_SUBPACKET
- RXRPC_RX_ANNO_VERIFIED
- RXRPC_SECURITY_AUTH
- RXRPC_SECURITY_ENCRYPT
- RXRPC_SECURITY_KEY
- RXRPC_SECURITY_KEYRING
- RXRPC_SECURITY_MAX
- RXRPC_SECURITY_NONE
- RXRPC_SECURITY_PLAIN
- RXRPC_SECURITY_RXGK
- RXRPC_SECURITY_RXK5
- RXRPC_SECURITY_RXKAD
- RXRPC_SERVER_BOUND
- RXRPC_SERVER_BOUND2
- RXRPC_SERVER_LISTENING
- RXRPC_SERVER_LISTEN_DISABLED
- RXRPC_SET_CALL_TIMEOUT
- RXRPC_SKB_INCL_LAST
- RXRPC_SKB_MARK_REJECT_ABORT
- RXRPC_SKB_MARK_REJECT_BUSY
- RXRPC_SKB_TX_BUFFER
- RXRPC_SLOW_START_OK
- RXRPC_SOCK_CONNECTED
- RXRPC_SUPPORTED_CMSG
- RXRPC_TIMEOUT_INIT
- RXRPC_TX_ANNO_ACK
- RXRPC_TX_ANNO_LAST
- RXRPC_TX_ANNO_MASK
- RXRPC_TX_ANNO_NAK
- RXRPC_TX_ANNO_RESENT
- RXRPC_TX_ANNO_RETRANS
- RXRPC_TX_ANNO_UNACK
- RXRPC_TX_LENGTH
- RXRPC_TX_SMSS
- RXRPC_UNBOUND
- RXRPC_UNINTERRUPTIBLE
- RXRPC_UPGRADEABLE_SERVICE
- RXRPC_UPGRADE_SERVICE
- RXRPC_USERSTATUS_SERVICE_UPGRADE
- RXRPC_USER_CALL_ID
- RXRPC__SUPPORTED
- RXRPT0FF_RDPTR
- RXRPT0FF_WTPTR
- RXRPT0_RDPTR
- RXRPT0_WTPTR
- RXRPT1FF_RDPTR
- RXRPT1FF_WTPTR
- RXRPT1_RDPTR
- RXRPT1_WTPTR
- RXRPT_BNDY
- RXRQ_NENTRIES
- RXRST
- RXS
- RXSB_BREAK
- RXSB_CTS
- RXSB_DATA_VALID
- RXSB_DCD
- RXSB_FRAME_ERR
- RXSB_MODEM_VALID
- RXSB_OVERRUN
- RXSB_PAR_ERR
- RXSEL
- RXSERCLR
- RXSHFT_EN
- RXSM
- RXSMRST
- RXSOT_ERROR
- RXSOT_SYNC_ERROR
- RXSQCTRL
- RXSR_BROADCAST
- RXSR_CRC_ERROR
- RXSR_ERROR
- RXSR_FRAMETYPE
- RXSR_MULTICAST
- RXSR_RUNT
- RXSR_TOO_LONG
- RXSR_UNICAST
- RXSR_VALID
- RXSSZ
- RXSTART_INIT
- RXSTATE
- RXSTATUS_ABORT
- RXSTATUS_ABORT_RECEIVED
- RXSTATUS_ALIGN
- RXSTATUS_ALL
- RXSTATUS_BREAK_RECEIVED
- RXSTATUS_BROADCAST
- RXSTATUS_CODE_VIOLATION
- RXSTATUS_CONTROL
- RXSTATUS_CRC
- RXSTATUS_CRC_ERROR
- RXSTATUS_DATA_AVAILABLE
- RXSTATUS_ERROR
- RXSTATUS_EXITED_HUNT
- RXSTATUS_FILTER
- RXSTATUS_FRAMING_ERROR
- RXSTATUS_IDLE_RECEIVED
- RXSTATUS_LAST
- RXSTATUS_LENGTH
- RXSTATUS_MULTICAST
- RXSTATUS_NODESC
- RXSTATUS_OVERRUN
- RXSTATUS_PARITY_ERROR
- RXSTATUS_RANGE
- RXSTATUS_RXBOUND
- RXSTATUS_RXPKTRCVD
- RXSTATUS_SHORT_FRAME
- RXSTATUS_SIZE
- RXSTATUS_STATUS_ERROR
- RXSTATUS_SYMBOL
- RXSTATUS_VLAN
- RXSTAT_ANYERR
- RXSTAT_CRCERROR
- RXSTAT_DONE
- RXSTAT_DRIBBLEERROR
- RXSTAT_DUMMY_READ
- RXSTAT_FRAME
- RXSTAT_OVERRUN
- RXSTAT_OVERSIZE
- RXSTAT_PARITY
- RXSTAT_SHORTPACKET
- RXS_AGGTYPE_MASK
- RXS_AGGTYPE_SHIFT
- RXS_AMSDU_MASK
- RXS_BCNSENT
- RXS_BR0
- RXS_BR1
- RXS_BR2
- RXS_BR3
- RXS_CHAN_40
- RXS_CHAN_5G
- RXS_CHAN_ID_MASK
- RXS_CHAN_ID_SHIFT
- RXS_CHAN_PHYTYPE_MASK
- RXS_CHAN_PHYTYPE_SHIFT
- RXS_DECATMPT
- RXS_DECERR
- RXS_DRTXC
- RXS_ECLK
- RXS_ECLK_NS
- RXS_ERR
- RXS_FCSERR
- RXS_IBRG
- RXS_PBPRES
- RXS_PHYRXST_VALID
- RXS_PLL1
- RXS_PLL2
- RXS_PLL3
- RXS_RESPFRAMETX
- RXS_RXANT_MASK
- RXS_RXANT_SHIFT
- RXS_SECKINDX_MASK
- RXS_SECKINDX_SHIFT
- RXTDMS
- RXTHRSH
- RXTH_MASK
- RXTL_DEFAULT
- RXTL_DMA
- RXTOL
- RXTOUT
- RXTRAFFIC_INT_M
- RXTSHIFTMAXR1_G
- RXTSHIFTMAXR1_M
- RXTSHIFTMAXR1_S
- RXTSHIFTMAXR1_V
- RXTSHIFTMAXR2_G
- RXTSHIFTMAXR2_M
- RXTSHIFTMAXR2_S
- RXTSHIFTMAXR2_V
- RXTS_IE
- RXTS_NS_OFF_MASK
- RXTS_NS_OFF_SHIFT
- RXTS_RDY
- RXTS_SEC_OFF_MASK
- RXTS_SEC_OFF_SHIFT
- RXTT
- RXTX_EMPTY
- RXTX_REG0
- RXTX_REG0_CTLE_EQ_FR_SET
- RXTX_REG0_CTLE_EQ_HR_SET
- RXTX_REG0_CTLE_EQ_QR_SET
- RXTX_REG1
- RXTX_REG102
- RXTX_REG102_FREQLOOP_LIMIT_SET
- RXTX_REG11
- RXTX_REG114
- RXTX_REG114_PQ_REG_INDEX
- RXTX_REG114_PQ_REG_WIDTH
- RXTX_REG11_PHASE_ADJUST_LIMIT_SET
- RXTX_REG12
- RXTX_REG121
- RXTX_REG121_SUMOS_CAL_CODE_RD
- RXTX_REG125
- RXTX_REG125_PHZ_MANUALCODE_SET
- RXTX_REG125_PHZ_MANUAL_SET
- RXTX_REG125_PQ_REG_SET
- RXTX_REG125_SIGN_PQ_2C_SET
- RXTX_REG125_SIGN_PQ_SET
- RXTX_REG127
- RXTX_REG127_DO_LATCH_MANCAL_SET
- RXTX_REG127_FORCE_LAT_CAL_START_MASK
- RXTX_REG127_FORCE_LAT_CAL_START_SET
- RXTX_REG127_FORCE_SUM_CAL_START_MASK
- RXTX_REG127_FORCE_SUM_CAL_START_SET
- RXTX_REG127_LATCH_MAN_CAL_ENA_SET
- RXTX_REG127_XO_LATCH_MANCAL_SET
- RXTX_REG128
- RXTX_REG128_EO_LATCH_MANCAL_SET
- RXTX_REG128_LATCH_CAL_WAIT_SEL_SET
- RXTX_REG128_SO_LATCH_MANCAL_SET
- RXTX_REG129
- RXTX_REG129_DE_LATCH_MANCAL_SET
- RXTX_REG129_RXDFE_CONFIG_INDEX
- RXTX_REG129_RXDFE_CONFIG_WIDTH
- RXTX_REG129_XE_LATCH_MANCAL_SET
- RXTX_REG12_LATCH_OFF_ENA_SET
- RXTX_REG12_RX_DET_TERM_ENABLE_MASK
- RXTX_REG12_RX_DET_TERM_ENABLE_SET
- RXTX_REG12_SUMOS_ENABLE_SET
- RXTX_REG13
- RXTX_REG130
- RXTX_REG130_EE_LATCH_MANCAL_SET
- RXTX_REG130_SE_LATCH_MANCAL_SET
- RXTX_REG14
- RXTX_REG145
- RXTX_REG145_RXDFE_CONFIG_SET
- RXTX_REG145_RXES_ENA_SET
- RXTX_REG145_RXVWES_LATENA_SET
- RXTX_REG145_TX_IDLE_SATA_SET
- RXTX_REG147
- RXTX_REG148
- RXTX_REG14_CLTE_LATCAL_MAN_PROG_SET
- RXTX_REG14_CTLE_LATCAL_MAN_ENA_SET
- RXTX_REG1_CTLE_EQ_SET
- RXTX_REG1_RXACVCM_SET
- RXTX_REG1_RXIREF_ADJ_SET
- RXTX_REG1_RXVREG1_SET
- RXTX_REG2
- RXTX_REG20
- RXTX_REG20_BLWC_ENA_INDEX
- RXTX_REG20_BLWC_ENA_WIDTH
- RXTX_REG21
- RXTX_REG21_DO_LATCH_CALOUT_RD
- RXTX_REG21_LATCH_CAL_FAIL_ODD_RD
- RXTX_REG21_XO_LATCH_CALOUT_RD
- RXTX_REG22
- RXTX_REG22_EO_LATCH_CALOUT_RD
- RXTX_REG22_LATCH_CAL_FAIL_EVEN_RD
- RXTX_REG22_SO_LATCH_CALOUT_RD
- RXTX_REG23
- RXTX_REG23_DE_LATCH_CALOUT_RD
- RXTX_REG23_XE_LATCH_CALOUT_RD
- RXTX_REG24
- RXTX_REG24_EE_LATCH_CALOUT_RD
- RXTX_REG24_SE_LATCH_CALOUT_RD
- RXTX_REG26
- RXTX_REG26_BLWC_ENA_SET
- RXTX_REG26_PERIOD_ERROR_LATCH_SET
- RXTX_REG27
- RXTX_REG28
- RXTX_REG2_TX_FIFO_ENA_SET
- RXTX_REG2_VTT_ENA_SET
- RXTX_REG2_VTT_SEL_SET
- RXTX_REG31
- RXTX_REG38
- RXTX_REG38_CUSTOMER_PINMODE_INV_SET
- RXTX_REG39
- RXTX_REG4
- RXTX_REG40
- RXTX_REG41
- RXTX_REG42
- RXTX_REG43
- RXTX_REG44
- RXTX_REG45
- RXTX_REG46
- RXTX_REG47
- RXTX_REG48
- RXTX_REG49
- RXTX_REG4_TX_DATA_RATE_SET
- RXTX_REG4_TX_LOOPBACK_BUF_EN_MASK
- RXTX_REG4_TX_WORD_MODE_SET
- RXTX_REG5
- RXTX_REG50
- RXTX_REG51
- RXTX_REG52
- RXTX_REG53
- RXTX_REG54
- RXTX_REG55
- RXTX_REG5_TX_CN1_SET
- RXTX_REG5_TX_CN2_SET
- RXTX_REG5_TX_CP1_SET
- RXTX_REG6
- RXTX_REG61
- RXTX_REG61_EYE_COUNT_WIDTH_SEL_SET
- RXTX_REG61_ISCAN_INBERT_SET
- RXTX_REG61_LOADFREQ_SHIFT_SET
- RXTX_REG61_SPD_SEL_CDR_SET
- RXTX_REG62
- RXTX_REG62_PERIOD_H1_QLATCH_SET
- RXTX_REG6_RESETB_RXD_INDEX
- RXTX_REG6_RESETB_RXD_WIDTH
- RXTX_REG6_RX_BIST_ERRCNT_RD_SET
- RXTX_REG6_RX_BIST_RESYNC_SET
- RXTX_REG6_TXAMP_CNTL_SET
- RXTX_REG6_TXAMP_ENA_SET
- RXTX_REG6_TX_IDLE_SET
- RXTX_REG7
- RXTX_REG7_BIST_ENA_RX_SET
- RXTX_REG7_LOOP_BACK_ENA_CTLE_MASK
- RXTX_REG7_LOOP_BACK_ENA_CTLE_SET
- RXTX_REG7_RESETB_RXA_MASK
- RXTX_REG7_RESETB_RXA_SET
- RXTX_REG7_RESETB_RXD_MASK
- RXTX_REG7_RESETB_RXD_SET
- RXTX_REG7_RX_WORD_MODE_SET
- RXTX_REG8
- RXTX_REG81
- RXTX_REG89_MU_TH7_SET
- RXTX_REG89_MU_TH8_SET
- RXTX_REG89_MU_TH9_SET
- RXTX_REG8_CDR_BYPASS_RXLOS_SET
- RXTX_REG8_CDR_LOOP_ENA_SET
- RXTX_REG8_SD_DISABLE_SET
- RXTX_REG8_SD_VREF_SET
- RXTX_REG8_SSC_ENABLE_SET
- RXTX_REG96
- RXTX_REG96_MU_FREQ1_SET
- RXTX_REG96_MU_FREQ2_SET
- RXTX_REG96_MU_FREQ3_SET
- RXTX_REG99
- RXTX_REG99_MU_PHASE1_SET
- RXTX_REG99_MU_PHASE2_SET
- RXTX_REG99_MU_PHASE3_SET
- RXTX_TIMEOUT
- RXUC_HW_CGC_EN
- RXUO
- RXUO_ADDR
- RXW4C_IRA
- RXWBDCNT_DCNT
- RXWBDCNT_WBCPL
- RXWBERR_ABORT
- RXWBERR_ALLERR
- RXWBERR_COLON
- RXWBERR_CRCERR
- RXWBERR_LIMIT
- RXWBERR_MIIER
- RXWBERR_NIBON
- RXWBERR_OVERUN
- RXWBERR_SHORT
- RXWBFLAG_64BIT
- RXWBFLAG_DEST
- RXWBFLAG_DEST_BRO
- RXWBFLAG_DEST_MUL
- RXWBFLAG_DEST_UNI
- RXWBFLAG_INT
- RXWBFLAG_IPCS
- RXWBFLAG_IPV4
- RXWBFLAG_IPV6
- RXWBFLAG_MAGIC
- RXWBFLAG_MF
- RXWBFLAG_OWN
- RXWBFLAG_PAUSE
- RXWBFLAG_TAGON
- RXWBFLAG_TCPCS
- RXWBFLAG_TCPON
- RXWBFLAG_UDPCS
- RXWBFLAG_UDPON
- RXWBFLAG_WAKEUP
- RXWI_DESC_SIZE_4WORDS
- RXWI_DESC_SIZE_5WORDS
- RXWI_DESC_SIZE_6WORDS
- RXWI_W0_BSSID
- RXWI_W0_KEY_INDEX
- RXWI_W0_MPDU_TOTAL_BYTE_COUNT
- RXWI_W0_TID
- RXWI_W0_UDF
- RXWI_W0_WIRELESS_CLI_ID
- RXWI_W1_BW
- RXWI_W1_FRAG
- RXWI_W1_MCS
- RXWI_W1_PHYMODE
- RXWI_W1_SEQUENCE
- RXWI_W1_SHORT_GI
- RXWI_W1_STBC
- RXWI_W2_RSSI0
- RXWI_W2_RSSI1
- RXWI_W2_RSSI2
- RXWI_W3_SNR0
- RXWI_W3_SNR1
- RXWRITEPTR_DROPPING
- RXWRITEPTR_LASTEFCI
- RXWRITEPTR_TRASHING
- RXWRPERR_F
- RXWRPERR_S
- RXWRPERR_V
- RXW_PADDING
- RXXGXS_INT_M
- RXXG_CONF1_VAL
- RXX_CLKSEL_SSI
- RXX_CLKSEL_VLYNQ
- RX_1024_TO_1518_PKTS
- RX_10G_PORT_BASE
- RX_128_255_PKTS
- RX_128_BYTE
- RX_128_BYTE_ENBL
- RX_1519_TO_MAX_PKTS
- RX_256_511_PKTS
- RX_512_TO_1023_PKTS
- RX_64_PKTS
- RX_65_TO_127_PKTS
- RX_AAL5_LIMIT
- RX_ABORT
- RX_AC3_CAPABILITIES
- RX_AC3_ENABLE
- RX_ACK_CURRENT
- RX_ACK_NEXT
- RX_ACT
- RX_ADC_FREQUENCY
- RX_ADDRH
- RX_ADDRH_MASK
- RX_ADDRH_MASK_
- RX_ADDRINUSE
- RX_ADDRL
- RX_ADDRL_MASK_
- RX_ADDR_MD
- RX_ADDR_MD_DBG_PT_MUX_SEL
- RX_ADDR_MD_MODE32
- RX_ADDR_MD_RAM_ACC
- RX_AE1_THRESH_FREE_MASK
- RX_AE1_THRESH_FREE_SHIFT
- RX_AE_COMP_VAL
- RX_AE_FREEN_VAL
- RX_AE_THRESH_COMP_MASK
- RX_AE_THRESH_COMP_SHIFT
- RX_AE_THRESH_FREE_MASK
- RX_AE_THRESH_FREE_SHIFT
- RX_AF_EN
- RX_AGG_CMP_AGG_ID
- RX_AGG_CMP_AGG_ID_SHIFT
- RX_AGG_CMP_LEN
- RX_AGG_CMP_LEN_SHIFT
- RX_AGG_CMP_TYPE
- RX_AGG_CMP_V
- RX_AGG_CMP_VALID
- RX_AGG_DISABLE
- RX_ALIGN
- RX_ALIGNMENT_ERROR
- RX_ALIGNMENT_ERROR_COUNTER
- RX_ALIGN_ERR
- RX_ALL
- RX_ALLOC_SIZE
- RX_ALL_ACCEPT
- RX_ALMOST_EMPTY_INTR
- RX_ALMOST_FULL_INTR
- RX_ANNOUNCE_RESUME
- RX_ANTENNA_SELECT
- RX_AREA_END
- RX_AREA_START
- RX_ARP_PKT
- RX_ASF_NEWFLAG_DIS
- RX_ASF_NEWFLAG_ENA
- RX_ASYNC
- RX_ATTENTION_FLAGS_BUFFER_FRAGMENT
- RX_ATTENTION_FLAGS_CLASSIFICATION
- RX_ATTENTION_FLAGS_CTRL_TYPE
- RX_ATTENTION_FLAGS_DA_IDX_INVALID
- RX_ATTENTION_FLAGS_DA_IDX_TIMEOUT
- RX_ATTENTION_FLAGS_DECRYPT_ERR
- RX_ATTENTION_FLAGS_DIRECTED
- RX_ATTENTION_FLAGS_ENCRYPT_REQUIRED
- RX_ATTENTION_FLAGS_EOSP
- RX_ATTENTION_FLAGS_FCS_ERR
- RX_ATTENTION_FLAGS_FIRST_MPDU
- RX_ATTENTION_FLAGS_FRAGMENT
- RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL
- RX_ATTENTION_FLAGS_LAST_MPDU
- RX_ATTENTION_FLAGS_MCAST_BCAST
- RX_ATTENTION_FLAGS_MGMT_TYPE
- RX_ATTENTION_FLAGS_MORE_DATA
- RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR
- RX_ATTENTION_FLAGS_MSDU_DONE
- RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR
- RX_ATTENTION_FLAGS_NON_QOS
- RX_ATTENTION_FLAGS_NULL_DATA
- RX_ATTENTION_FLAGS_ORDER
- RX_ATTENTION_FLAGS_OVERFLOW_ERR
- RX_ATTENTION_FLAGS_PEER_IDX_INVALID
- RX_ATTENTION_FLAGS_PEER_IDX_TIMEOUT
- RX_ATTENTION_FLAGS_POWER_MGMT
- RX_ATTENTION_FLAGS_SA_IDX_INVALID
- RX_ATTENTION_FLAGS_SA_IDX_TIMEOUT
- RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL
- RX_ATTENTION_FLAGS_TKIP_MIC_ERR
- RX_ATTENTION_FLAGS_U_APSD_TRIGGER
- RX_AUTO_ACK_EN
- RX_AUTO_NEG_MASK
- RX_AUTO_NEG_SHIFT
- RX_BAD_CRC_ACCEPT
- RX_BANDWIDTH
- RX_BAR_INTR_PACKET_MASK
- RX_BAR_INTR_TIME_MASK
- RX_BASE_ADDR
- RX_BASE_ADDRH
- RX_BASE_ADDRL
- RX_BASE_CSR
- RX_BASE_CSR_RING_REGISTER
- RX_BASE_PTR
- RX_BATCH_SIZE
- RX_BA_INDICATION
- RX_BA_WIN_SIZE_CHANGE_EVENT_ID
- RX_BCAST
- RX_BCAST_CHG_MSK
- RX_BCAST_CHG_OFF
- RX_BCAST_FRAME
- RX_BCAST_PKTS
- RX_BCST_EN
- RX_BC_DISABLE
- RX_BD
- RX_BD_CF
- RX_BD_CRC
- RX_BD_DN
- RX_BD_EMPTY
- RX_BD_ERRORS
- RX_BD_FLAGS_1_BUFFER_PACKET
- RX_BD_FLAGS_2_BUFFER_PACKET
- RX_BD_FLAGS_3_BUFFER_PACKET
- RX_BD_FLAGS_4_BUFFER_PACKET
- RX_BD_FLAGS_BUFFERS
- RX_BD_FLAGS_DUMMY
- RX_BD_FLAGS_END
- RX_BD_FLAGS_EOP
- RX_BD_FLAGS_NOPUSH
- RX_BD_FLAGS_SOP
- RX_BD_FLAGS_START
- RX_BD_IRQ
- RX_BD_IS
- RX_BD_LC
- RX_BD_LEN
- RX_BD_LEN_SHIFT
- RX_BD_MISS
- RX_BD_NUM
- RX_BD_NUM_DEFAULT
- RX_BD_NUM_MAX
- RX_BD_OR
- RX_BD_RING_LEN
- RX_BD_SF
- RX_BD_STATS
- RX_BD_TL
- RX_BD_TYPE
- RX_BD_TYPE_16B_BD_SIZE
- RX_BD_TYPE_32B_BD_SIZE
- RX_BD_TYPE_48B_BD_SIZE
- RX_BD_TYPE_64B_BD_SIZE
- RX_BD_TYPE_RX_AGG_BD
- RX_BD_TYPE_RX_BUFFER_BD
- RX_BD_TYPE_RX_PACKET_BD
- RX_BD_WRAP
- RX_BINTERVAL
- RX_BIST_32A_PASS
- RX_BIST_32B_PASS
- RX_BIST_32C_PASS
- RX_BIST_33A_PASS
- RX_BIST_33B_PASS
- RX_BIST_33C_PASS
- RX_BIST_CTRL_32_PASS
- RX_BIST_CTRL_33_PASS
- RX_BIST_IPP_32A_PASS
- RX_BIST_IPP_32B_PASS
- RX_BIST_IPP_32C_PASS
- RX_BIST_IPP_33A_PASS
- RX_BIST_IPP_33B_PASS
- RX_BIST_IPP_33C_PASS
- RX_BIST_REAS_26A_PASS
- RX_BIST_REAS_26B_PASS
- RX_BIST_REAS_27_PASS
- RX_BIST_START
- RX_BIST_STATE_MASK
- RX_BIST_SUMMARY
- RX_BIT_CHAN
- RX_BIT_MASK
- RX_BLANK_INTR_PKT_MASK
- RX_BLANK_INTR_PKT_SHIFT
- RX_BLANK_INTR_PKT_VAL
- RX_BLANK_INTR_TIME_MASK
- RX_BLANK_INTR_TIME_SHIFT
- RX_BLANK_INTR_TIME_VAL
- RX_BQ_ALEMPTY_INT
- RX_BQ_ALEMPTY_TH
- RX_BQ_ALFULL_INT
- RX_BQ_ALFULL_TH
- RX_BQ_DEPTH
- RX_BQ_EMPTY_INT
- RX_BQ_FREE_DESC_CNT
- RX_BQ_FULL_INT
- RX_BQ_INT_THRESHOLD
- RX_BQ_IN_INT
- RX_BQ_IN_TIMEOUT
- RX_BQ_IN_TIMEOUT_INT
- RX_BQ_IN_TIMEOUT_TH
- RX_BQ_RD_ADDR
- RX_BQ_REG_EN
- RX_BQ_START_ADDR
- RX_BQ_WR_ADDR
- RX_BROADCAST
- RX_BROADCAST_ACCEPT
- RX_BROADCAST_IN_PS_DEF_VALUE
- RX_BROADCAST_PACKET_COUNTER
- RX_BROADCAST_PKT
- RX_BROADPKT
- RX_BUCKET_SIZE
- RX_BUDGET
- RX_BUF
- RX_BUFF
- RX_BUFFERS
- RX_BUFFER_INFO_FLAG_ACTIVE
- RX_BUFFER_MULTIPLE
- RX_BUFFER_OFFSET
- RX_BUFFER_SIZE
- RX_BUFFER_SIZE_BMSK
- RX_BUFFS
- RX_BUFF_ADDR
- RX_BUFF_END
- RX_BUFF_MOD_MASK
- RX_BUFF_SIZE
- RX_BUFF_SZ
- RX_BUFLEN
- RX_BUF_ALIGN
- RX_BUF_ALIGN_ORDER
- RX_BUF_ALLOC_SIZE
- RX_BUF_ANMF
- RX_BUF_BASE
- RX_BUF_BRS
- RX_BUF_CFG
- RX_BUF_DMA_ALIGN
- RX_BUF_ESI
- RX_BUF_FDF
- RX_BUF_FLAGS
- RX_BUF_IDX
- RX_BUF_L
- RX_BUF_LEN
- RX_BUF_LENGTH
- RX_BUF_LEN_IDX
- RX_BUF_MASK
- RX_BUF_NUM
- RX_BUF_P
- RX_BUF_PAD
- RX_BUF_PADDED_PAYLOAD
- RX_BUF_RTR
- RX_BUF_SIZE
- RX_BUF_SIZE_MASK
- RX_BUF_SIZE_MAX
- RX_BUF_SIZE_SHIFT_DIV
- RX_BUF_SZ
- RX_BUF_TOT_LEN
- RX_BUF_UNALIGNED_PAYLOAD
- RX_BUF_WRAP_PAD
- RX_BUF_XTD
- RX_BUNDLE_SIZE
- RX_BURST_MASK
- RX_BURST_SIZE_16_64BIT
- RX_BURST_SIZE_4_64BIT
- RX_BUSY
- RX_BUS_ERROR
- RX_BUS_MASTER_COMPLETE
- RX_BYPASS_8B10B_ENABLE
- RX_BYTES
- RX_BYTES_OK
- RX_BYTES_TRANSFERRED
- RX_BYTE_COUNTER
- RX_CALL_DEAD
- RX_CALL_TIMEOUT
- RX_CARRIER_SENSE_ERROR_COUNTER
- RX_CDRLF_CNFG2
- RX_CELL_COUNT_OFF
- RX_CELL_CTR_OF
- RX_CER
- RX_CFF_NUM_REG
- RX_CFG
- RX_CFGCLKFREQVAL
- RX_CFG_A
- RX_CFG_A_RX_HP_WB_EN_
- RX_CFG_A_RX_PF_PRI_THRES_MASK_
- RX_CFG_A_RX_PF_PRI_THRES_SET_
- RX_CFG_A_RX_PF_THRES_MASK_
- RX_CFG_A_RX_PF_THRES_SET_
- RX_CFG_A_RX_WB_ON_INT_TMR_
- RX_CFG_A_RX_WB_THRES_MASK_
- RX_CFG_A_RX_WB_THRES_SET_
- RX_CFG_B
- RX_CFG_BATCH_DIS
- RX_CFG_BSSID
- RX_CFG_B_RDMABL_512_
- RX_CFG_B_RX_PAD_0_
- RX_CFG_B_RX_PAD_2_
- RX_CFG_B_RX_PAD_MASK_
- RX_CFG_B_RX_RING_LEN_MASK_
- RX_CFG_B_TS_ALL_RX_
- RX_CFG_C
- RX_CFG_COMP_RING_MASK
- RX_CFG_COMP_RING_SHIFT
- RX_CFG_COPY_RX_STATUS
- RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_
- RX_CFG_C_RX_INT_EN_R2C_
- RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_
- RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_
- RX_CFG_DESC_RING1_MASK
- RX_CFG_DESC_RING1_SHIFT
- RX_CFG_DESC_RING_MASK
- RX_CFG_DESC_RING_SHIFT
- RX_CFG_DISABLE_BCAST
- RX_CFG_DMA_EN
- RX_CFG_EN
- RX_CFG_ENABLE_ANY_BSSID
- RX_CFG_ENABLE_ANY_DEST_MAC
- RX_CFG_ENABLE_ONLY_MY_BSSID
- RX_CFG_ENABLE_ONLY_MY_DEST_MAC
- RX_CFG_ENABLE_ONLY_MY_SSID
- RX_CFG_ENABLE_PHY_HEADER_PLCP
- RX_CFG_ENABLE_RX_CMPLT_FCS_ERROR
- RX_CFG_MAC
- RX_CFG_PREAM
- RX_CFG_PROMISCUOUS
- RX_CFG_RESET
- RX_CFG_RXDOFF_
- RX_CFG_RX_DMA_CNT_
- RX_CFG_RX_DUMP_
- RX_CFG_RX_END_ALGN16_
- RX_CFG_RX_END_ALGN32_
- RX_CFG_RX_END_ALGN4_
- RX_CFG_RX_END_ALGN_
- RX_CFG_SWIVEL_MASK
- RX_CFG_SWIVEL_SHIFT
- RX_CFG_TSF
- RX_CHANGED
- RX_CHANNEL_DISABLED
- RX_CHANNEL_F
- RX_CHANNEL_IDLE
- RX_CHANNEL_MASK
- RX_CHANNEL_PORT_OFF
- RX_CHANNEL_S
- RX_CHANNEL_UPDATE_IN_PROGRESS
- RX_CHANNEL_V
- RX_CHANS
- RX_CHAN_G
- RX_CHAN_M
- RX_CHAN_S
- RX_CHAN_V
- RX_CHECKSUM
- RX_CHECKSUM_ERROR
- RX_CHECK_DLC
- RX_CHKSUM_EN
- RX_CHKSUM_IP_ERR
- RX_CHKSUM_IP_ERR_UNKNOWN
- RX_CHKSUM_IP_OK_ONLY
- RX_CHKSUM_IP_UDP_TCP_OK
- RX_CHKSUM_NONE
- RX_CHKSUM_NUM
- RX_CHKSUM_TCP_UDP_ERR
- RX_CHNL_CTRL
- RX_CHNL_STS
- RX_CID
- RX_CLAIM_REQ_ALLOC
- RX_CLEAN_MAX
- RX_CLKSEL_DSS1
- RX_CLKSEL_DSS2
- RX_CLKSEL_SSI
- RX_CLK_110
- RX_CLK_1200
- RX_CLK_150
- RX_CLK_1800
- RX_CLK_19200
- RX_CLK_2000
- RX_CLK_2400
- RX_CLK_300
- RX_CLK_38400
- RX_CLK_4800
- RX_CLK_600
- RX_CLK_75
- RX_CLK_9600
- RX_CLK_CGC_ON
- RX_CLK_POL_MASK
- RX_CLK_POL_RISING
- RX_CLK_SEL_MASK
- RX_CLK_SEL_SRG
- RX_CLK_SHIFT_BASE
- RX_CLS_FLOW_DISC
- RX_CLS_FLOW_WAKE
- RX_CLS_LOC_ANY
- RX_CLS_LOC_FIRST
- RX_CLS_LOC_LAST
- RX_CLS_LOC_SPECIAL
- RX_CMD_A_BAM
- RX_CMD_A_BAM_
- RX_CMD_A_CSE_MASK_
- RX_CMD_A_DRB
- RX_CMD_A_DRB_
- RX_CMD_A_FCS
- RX_CMD_A_FCS_
- RX_CMD_A_FVTG
- RX_CMD_A_FVTG_
- RX_CMD_A_ICE
- RX_CMD_A_ICE_
- RX_CMD_A_ICSM_
- RX_CMD_A_IPV
- RX_CMD_A_IPV_
- RX_CMD_A_LCSM
- RX_CMD_A_LEN
- RX_CMD_A_LEN_MASK_
- RX_CMD_A_LONG
- RX_CMD_A_LONG_
- RX_CMD_A_MAM
- RX_CMD_A_MAM_
- RX_CMD_A_PFF
- RX_CMD_A_PFF_
- RX_CMD_A_PID
- RX_CMD_A_PID_IP_
- RX_CMD_A_PID_MASK_
- RX_CMD_A_PID_NIP
- RX_CMD_A_PID_NONE_IP_
- RX_CMD_A_PID_PP
- RX_CMD_A_PID_TCP
- RX_CMD_A_PID_TCP_IP_
- RX_CMD_A_PID_UDP
- RX_CMD_A_PID_UDP_IP_
- RX_CMD_A_RED
- RX_CMD_A_RED_
- RX_CMD_A_RUNT
- RX_CMD_A_RUNT_
- RX_CMD_A_RWT
- RX_CMD_A_RWT_
- RX_CMD_A_RXE
- RX_CMD_A_RXE_
- RX_CMD_A_RX_ERRS_MASK_
- RX_CMD_A_TCE
- RX_CMD_A_TCE_
- RX_CMD_A_UAM
- RX_CMD_A_UAM_
- RX_CMD_B_CSUM
- RX_CMD_B_CSUM_MASK_
- RX_CMD_B_CSUM_SHIFT
- RX_CMD_B_CSUM_SHIFT_
- RX_CMD_B_VTAG
- RX_CMD_B_VTAG_CFI_MASK_
- RX_CMD_B_VTAG_MASK_
- RX_CMD_B_VTAG_PRI_MASK_
- RX_CMD_B_VTAG_VID_MASK_
- RX_CMD_C_REF_FAIL_
- RX_CMD_C_REF_FAIL_SHIFT_
- RX_CMD_C_WAKE_
- RX_CMD_C_WAKE_SHIFT_
- RX_CMD_ELE_MAX
- RX_CMD_QUEUE
- RX_CMN_STAT_INC
- RX_CMPL_CFA_CODE_MASK
- RX_CMPL_CFA_CODE_SFT
- RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT
- RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT
- RX_CMPL_ERRORS_BUFFER_ERROR_MASK
- RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP
- RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER
- RX_CMPL_ERRORS_CRC_ERROR
- RX_CMPL_ERRORS_IP_CS_ERROR
- RX_CMPL_ERRORS_L4_CS_ERROR
- RX_CMPL_ERRORS_MASK
- RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR
- RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN
- RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL
- RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION
- RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN
- RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL
- RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
- RX_CMPL_ERRORS_PKT_ERROR_MASK
- RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR
- RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR
- RX_CMPL_ERRORS_SFT
- RX_CMPL_ERRORS_T_IP_CS_ERROR
- RX_CMPL_ERRORS_T_L4_CS_ERROR
- RX_CMPL_ERRORS_T_PKT_ERROR_MASK
- RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR
- RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR
- RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR
- RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN
- RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
- RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION
- RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR
- RX_CMP_AGG_BUFS
- RX_CMP_AGG_BUFS_SHIFT
- RX_CMP_CFA_CODE
- RX_CMP_CMP_TYPE
- RX_CMP_ENCAP
- RX_CMP_FLAGS2_IP_CS_CALC
- RX_CMP_FLAGS2_L4_CS_CALC
- RX_CMP_FLAGS2_METADATA_TCI_MASK
- RX_CMP_FLAGS2_METADATA_TPID_MASK
- RX_CMP_FLAGS2_METADATA_TPID_SFT
- RX_CMP_FLAGS2_METADATA_VID_MASK
- RX_CMP_FLAGS2_META_FORMAT_VLAN
- RX_CMP_FLAGS2_T_IP_CS_CALC
- RX_CMP_FLAGS2_T_L4_CS_CALC
- RX_CMP_FLAGS_ERROR
- RX_CMP_FLAGS_ITYPES_SHIFT
- RX_CMP_FLAGS_ITYPE_FCOE
- RX_CMP_FLAGS_ITYPE_IP
- RX_CMP_FLAGS_ITYPE_PTP_WO_TS
- RX_CMP_FLAGS_ITYPE_PTP_W_TS
- RX_CMP_FLAGS_ITYPE_ROCE
- RX_CMP_FLAGS_ITYPE_TCP
- RX_CMP_FLAGS_ITYPE_UDP
- RX_CMP_FLAGS_ITYPE_UNKNOWN
- RX_CMP_FLAGS_PLACEMENT
- RX_CMP_FLAGS_RSS_VALID
- RX_CMP_FLAGS_UNUSED
- RX_CMP_HASH_TYPE
- RX_CMP_HASH_VALID
- RX_CMP_L2_ERRORS
- RX_CMP_L4_CS_BITS
- RX_CMP_L4_CS_ERR_BITS
- RX_CMP_L4_CS_OK
- RX_CMP_LEN
- RX_CMP_LEN_SHIFT
- RX_CMP_PAYLOAD_OFFSET
- RX_CMP_PAYLOAD_OFFSET_SHIFT
- RX_CMP_RSS_HASH_TYPE
- RX_CMP_RSS_HASH_TYPE_SHIFT
- RX_CMP_TYPE
- RX_CMP_V
- RX_CMP_V1
- RX_CMP_VALID
- RX_CNG
- RX_CNTL_CSR
- RX_CNTL_CSR_ENABLE_RX_DMA
- RX_CNTL_CSR_LOAD_RXD
- RX_CNTRL0_ADDR_FLTR_EN
- RX_CNTRL0_BCAST_DIS
- RX_CNTRL0_LOOP_EN
- RX_CNTRL0_PADSTRIP_EN
- RX_CNTRL0_PAUSE_EN
- RX_CNTRL0_RX_EN
- RX_CNTRL0_RX_RUNT_EN
- RX_CNTRL0_SEND_FCS
- RX_CNTRL1_DEFER_EN
- RX_CNTRL_FRAME
- RX_COALESCED_FRAMES
- RX_COALESCED_FRAME_OFFSET
- RX_COALESCED_TIMER
- RX_COALESCE_S
- RX_COALESCE_SET
- RX_COALESCE_V
- RX_COALESCE_VALID_F
- RX_COALESCE_VALID_S
- RX_COALESCE_VALID_V
- RX_CODE_ERROR_COUNTER
- RX_COE_EN
- RX_COE_MODE
- RX_COLL
- RX_COMP1_DATA_INDEX_MASK
- RX_COMP1_DATA_INDEX_SHIFT
- RX_COMP1_DATA_OFF_MASK
- RX_COMP1_DATA_OFF_SHIFT
- RX_COMP1_DATA_SIZE_MASK
- RX_COMP1_DATA_SIZE_SHIFT
- RX_COMP1_RELEASE_DATA
- RX_COMP1_RELEASE_FLOW
- RX_COMP1_RELEASE_HDR
- RX_COMP1_RELEASE_NEXT
- RX_COMP1_SKIP_MASK
- RX_COMP1_SKIP_SHIFT
- RX_COMP1_SPLIT_PKT
- RX_COMP1_TYPE_MASK
- RX_COMP1_TYPE_SHIFT
- RX_COMP2_HDR_INDEX_MASK
- RX_COMP2_HDR_INDEX_SHIFT
- RX_COMP2_HDR_OFF_MASK
- RX_COMP2_HDR_OFF_SHIFT
- RX_COMP2_HDR_SIZE_MASK
- RX_COMP2_HDR_SIZE_SHIFT
- RX_COMP2_NEXT_INDEX_MASK
- RX_COMP2_NEXT_INDEX_SHIFT
- RX_COMP3_CSUM_START_MASK
- RX_COMP3_CSUM_START_SHIFT
- RX_COMP3_FLOWID_MASK
- RX_COMP3_FLOWID_SHIFT
- RX_COMP3_FORCE_FLAG
- RX_COMP3_JUMBO_HDR_SPLIT_EN
- RX_COMP3_JUMBO_PKT
- RX_COMP3_L3_HEAD_OFF_MASK
- RX_COMP3_L3_HEAD_OFF_SHIFT
- RX_COMP3_LOAD_BAL_MASK
- RX_COMP3_LOAD_BAL_SHIFT
- RX_COMP3_NO_ASSIST
- RX_COMP3_OPCODE_MASK
- RX_COMP3_OPCODE_SHIFT
- RX_COMP3_SAP_MASK
- RX_COMP3_SAP_SHIFT
- RX_COMP3_SMALL_PKT
- RX_COMP4_BAD
- RX_COMP4_HASH_PASS
- RX_COMP4_HASH_VAL_MASK
- RX_COMP4_HASH_VAL_SHIFT
- RX_COMP4_LEN_MISMATCH
- RX_COMP4_PERFECT_MATCH_MASK
- RX_COMP4_PERFECT_MATCH_SHIFT
- RX_COMP4_PKT_LEN_MASK
- RX_COMP4_PKT_LEN_SHIFT
- RX_COMP4_TCP_CSUM_MASK
- RX_COMP4_TCP_CSUM_SHIFT
- RX_COMP4_ZERO
- RX_COMPLETE
- RX_COMPLETE_FRAME
- RX_COMPL_Q_ADDR_SIZE
- RX_COMP_ENTRY
- RX_COMP_RINGN_INDEX
- RX_COMP_RINGN_SIZE
- RX_COMP_RING_INDEX
- RX_COMP_RING_SIZE
- RX_COM_BIAS_DAC_DAC_REF_EN_ENABLE
- RX_COM_BIAS_DAC_DAC_REF_EN_MASK
- RX_COM_BIAS_DAC_RX_BIAS_EN_ENABLE
- RX_COM_BIAS_DAC_RX_BIAS_EN_MASK
- RX_CONFIG_ACCEPT_MASK
- RX_CONFIG_OFF
- RX_CONFIG_OPTION_ANY_DST_ANY_BSS
- RX_CONFIG_OPTION_ANY_DST_MY_BSS
- RX_CONFIG_OPTION_FOR_IBSS_JOIN
- RX_CONFIG_OPTION_FOR_JOIN
- RX_CONFIG_OPTION_FOR_MEASUREMENT
- RX_CONFIG_OPTION_FOR_SCAN
- RX_CONFIG_OPTION_MY_DST_ANY_BSS
- RX_CONFIG_OPTION_MY_DST_MY_BSS
- RX_CONGESTION_EXPERIENCED
- RX_CONTENTION_DETECTED
- RX_CONTEXT_DESC3_TSA_INDEX
- RX_CONTEXT_DESC3_TSA_LEN
- RX_CONTEXT_DESC3_TSA_POS
- RX_CONTEXT_DESC3_TSA_WIDTH
- RX_CONTEXT_DESC3_TSD_INDEX
- RX_CONTEXT_DESC3_TSD_LEN
- RX_CONTEXT_DESC3_TSD_POS
- RX_CONTEXT_DESC3_TSD_WIDTH
- RX_CONTINUE
- RX_CONTROL
- RX_CONTROL_FRAME_PACKET_COUNTER
- RX_COPYBREAK
- RX_COPYBREAK_DEFAULT
- RX_COPYHDR
- RX_COPY_ALWAYS
- RX_COPY_BREAK
- RX_COPY_MIN
- RX_COPY_SIZE
- RX_COPY_THRES
- RX_COPY_THRESH
- RX_COPY_THRESHOLD
- RX_COUNT_BUFFERS
- RX_CPU_BASE
- RX_CPU_HWBKPT
- RX_CPU_MODE
- RX_CPU_PGMCTR
- RX_CPU_SCRATCH_BASE
- RX_CPU_SCRATCH_SIZE
- RX_CPU_STATE
- RX_CQ_LEN
- RX_CRC
- RX_CRC_10_OK
- RX_CRC_32_OK
- RX_CRC_ERR
- RX_CRC_ERROR
- RX_CRC_ERROR_ENBL
- RX_CREDITS_S
- RX_CREDITS_V
- RX_CRX_IDX
- RX_CRYPTO_FAIL_ICV
- RX_CRYPTO_FAIL_KEY
- RX_CRYPTO_FAIL_MIC
- RX_CRYPTO_SUCCESS
- RX_CSR
- RX_CTL_CMD
- RX_CTL_CRC_MASK
- RX_CTL_CRC_SHIFT
- RX_CTL_CR_MASK
- RX_CTL_CR_SHIFT
- RX_CTL_DAT_FIFO_MASK
- RX_CTL_DAT_FIFO_MASK_ID_MISMATCH
- RX_CTL_DAT_FIFO_MASK_IPP_EOP_ERR
- RX_CTL_DAT_FIFO_MASK_ZCP_EOP_ERR
- RX_CTL_DAT_FIFO_STAT
- RX_CTL_DAT_FIFO_STAT_DBG
- RX_CTL_DAT_FIFO_STAT_DBG_ID_MISMATCH
- RX_CTL_DAT_FIFO_STAT_DBG_IPP_EOP_ERR
- RX_CTL_DAT_FIFO_STAT_DBG_ZCP_EOP_ERR
- RX_CTL_DAT_FIFO_STAT_ID_MISMATCH
- RX_CTL_DAT_FIFO_STAT_IPP_EOP_ERR
- RX_CTL_DAT_FIFO_STAT_ZCP_EOP_ERR
- RX_CTL_ER_MASK
- RX_CTL_ER_SHIFT
- RX_CTL_NR_MASK
- RX_CTL_NR_SHIFT
- RX_CTL_PKTS
- RX_CTRL_FIFO_DATA_HI_CTRL
- RX_CTRL_FIFO_DATA_HI_FLOW_MASK
- RX_CTRL_RXE
- RX_CURBUF_ADDR
- RX_CURBUF_LENGTH
- RX_CURDESC_PTR
- RX_CUT_THRU_EN
- RX_CVLAN_PKT
- RX_DACK_CHANGE_F
- RX_DACK_CHANGE_S
- RX_DACK_CHANGE_V
- RX_DACK_MODE_G
- RX_DACK_MODE_M
- RX_DACK_MODE_S
- RX_DACK_MODE_V
- RX_DAT
- RX_DATA_AV
- RX_DATA_FIFO
- RX_DATA_IN
- RX_DATA_LEN_UNDERFLOW_MSK
- RX_DATA_LEN_UNDERFLOW_OFF
- RX_DATA_READY
- RX_DATA_RESET
- RX_DATA_SIZE
- RX_DBGINFO_FEEDBACK
- RX_DCBCTL_PKT
- RX_DCD
- RX_DCNT
- RX_DC_ENTRIES
- RX_DC_ENTRIES_ORDER
- RX_DEBUG
- RX_DEBUGI_BADTYPE
- RX_DEBUG_DATA_STATE_MASK
- RX_DEBUG_DESC_STATE_MASK
- RX_DEBUG_FC_STATE_MASK
- RX_DEBUG_INTR_READ_PTR_MASK
- RX_DEBUG_INTR_WRITE_PTR_MASK
- RX_DEBUG_LM_STATE_MASK
- RX_DEBUG_LOAD_STATE_MASK
- RX_DEF_PENDING
- RX_DELETE
- RX_DEPTH_OFFSET
- RX_DESC
- RX_DESC0_BROADCAST
- RX_DESC0_CRC_ERR
- RX_DESC0_DMA_OWN
- RX_DESC0_ERR
- RX_DESC0_FRAME_LEN
- RX_DESC0_FRAME_LEN_MASK
- RX_DESC0_FRS
- RX_DESC0_FTL
- RX_DESC0_LRS
- RX_DESC0_MULTICAST
- RX_DESC0_ODD_NB
- RX_DESC0_RUNT
- RX_DESC1_BUF_SIZE_MASK
- RX_DESC1_END
- RX_DESC2_ADDRESS_PHYS
- RX_DESC2_ADDRESS_VIRT
- RX_DESC3_L34T_IPV4_ICMP
- RX_DESC3_L34T_IPV4_TCP
- RX_DESC3_L34T_IPV4_UDP
- RX_DESC3_L34T_IPV4_UNKNOWN
- RX_DESC3_L34T_IPV6_ICMP
- RX_DESC3_L34T_IPV6_TCP
- RX_DESC3_L34T_IPV6_UDP
- RX_DESC3_L34T_IPV6_UNKNOWN
- RX_DESCRIPTORS
- RX_DESCR_SIZE
- RX_DESCS
- RX_DESC_ADDR_SIZE
- RX_DESC_BASE
- RX_DESC_BCAST
- RX_DESC_CNT
- RX_DESC_COUNT
- RX_DESC_DATA0_BUF_LENGTH_MASK_
- RX_DESC_DATA0_EXT_
- RX_DESC_DATA0_FRAME_LENGTH_GET_
- RX_DESC_DATA0_FRAME_LENGTH_MASK_
- RX_DESC_DATA0_FS_
- RX_DESC_DATA0_LS_
- RX_DESC_DATA0_OWN_
- RX_DESC_DATA2_TS_NS_MASK_
- RX_DESC_DECRYPT_FAIL
- RX_DESC_DEF
- RX_DESC_DEF0
- RX_DESC_DEF1
- RX_DESC_DURATION_OFFSET
- RX_DESC_ENCRYPTION_MASK
- RX_DESC_ENTRY
- RX_DESC_FLAGS_OFFSET
- RX_DESC_FLAG_CONSUMED
- RX_DESC_FLAG_IDLE
- RX_DESC_FLAG_VALID
- RX_DESC_INFO
- RX_DESC_LINK_QUALITY_OFFSET
- RX_DESC_MASK
- RX_DESC_MATCH_BSSID
- RX_DESC_MATCH_RXADDR1
- RX_DESC_MATCH_SSID
- RX_DESC_MAX
- RX_DESC_MAX0
- RX_DESC_MAX1
- RX_DESC_MCAST
- RX_DESC_MEASURMENT
- RX_DESC_MIC_FAIL
- RX_DESC_MIN
- RX_DESC_MIN0
- RX_DESC_MIN1
- RX_DESC_MSDU_POS_OFFSET
- RX_DESC_MSDU_SIZE_OFFSET
- RX_DESC_NUM
- RX_DESC_NUM_92E
- RX_DESC_NUM_MASK
- RX_DESC_PACKETID_SHIFT
- RX_DESC_PREAMBLE_TYPE_OFFSET
- RX_DESC_Q_ADDR_SIZE
- RX_DESC_RINGN_INDEX
- RX_DESC_RINGN_SIZE
- RX_DESC_RING_INDEX
- RX_DESC_RING_SIZE
- RX_DESC_RSSI_OFFSET
- RX_DESC_RX_TIME_OFFSET
- RX_DESC_SEQNUM_MASK
- RX_DESC_SIZE
- RX_DESC_STAINTIM
- RX_DESC_STATUS_OFFSET
- RX_DESC_TABLE_SZ
- RX_DESC_VALID_FCS
- RX_DESC_VIRTUAL_BM
- RX_DEST_MATCH
- RX_DEST_MATCH_ENBL
- RX_DEVICE_BUFF_SIZE
- RX_DIAG_SC2C_DELAY
- RX_DIAG_SIGDET_TUNE
- RX_DIED
- RX_DIR
- RX_DIS
- RX_DISABLE
- RX_DISABLED
- RX_DISABLE_ALLMULTI
- RX_DISABLE_LLC_PROMISC
- RX_DISABLE_NSA
- RX_DISABLE_PASS_ALL
- RX_DISABLE_PASS_DB
- RX_DISABLE_PASS_NSA
- RX_DISABLE_PASS_SMT
- RX_DISABLE_PROMISC
- RX_DISCARD_FRAME_CNT
- RX_DIVIDER_BIT_1_2
- RX_DIVIDER_BIT_3_4
- RX_DMA
- RX_DMA1_SM_MASK
- RX_DMA2_SM_MASK
- RX_DMACX_CAM_EN
- RX_DMACX_CAM_LMACID
- RX_DMAC_COUNT
- RX_DMAREQEN
- RX_DMA_ADDR
- RX_DMA_BOUNDARY_8723B
- RX_DMA_BUF
- RX_DMA_BURST
- RX_DMA_CK_DIV
- RX_DMA_CK_DIV_CNT
- RX_DMA_CTL_STAT
- RX_DMA_CTL_STAT_BYTE_EN_BUS
- RX_DMA_CTL_STAT_CFIGLOGPAGE
- RX_DMA_CTL_STAT_CHAN_FATAL
- RX_DMA_CTL_STAT_CONFIG_ERR
- RX_DMA_CTL_STAT_DBG
- RX_DMA_CTL_STAT_DBG_BYTE_EN_BUS
- RX_DMA_CTL_STAT_DBG_CFIGLOGPAGE
- RX_DMA_CTL_STAT_DBG_CONFIG_ERR
- RX_DMA_CTL_STAT_DBG_DC_FIFO_ERR
- RX_DMA_CTL_STAT_DBG_MEX
- RX_DMA_CTL_STAT_DBG_PKTREAD
- RX_DMA_CTL_STAT_DBG_PORT_DROP_PKT
- RX_DMA_CTL_STAT_DBG_PTRREAD
- RX_DMA_CTL_STAT_DBG_RBRFULL
- RX_DMA_CTL_STAT_DBG_RBRLOGPAGE
- RX_DMA_CTL_STAT_DBG_RBR_EMPTY
- RX_DMA_CTL_STAT_DBG_RBR_PRE_EMTY
- RX_DMA_CTL_STAT_DBG_RBR_PRE_PAR
- RX_DMA_CTL_STAT_DBG_RBR_TMOUT
- RX_DMA_CTL_STAT_DBG_RCRFULL
- RX_DMA_CTL_STAT_DBG_RCRINCON
- RX_DMA_CTL_STAT_DBG_RCRSHADOW_FULL
- RX_DMA_CTL_STAT_DBG_RCRTHRES
- RX_DMA_CTL_STAT_DBG_RCRTO
- RX_DMA_CTL_STAT_DBG_RCR_ACK_ERR
- RX_DMA_CTL_STAT_DBG_RCR_SHA_PAR
- RX_DMA_CTL_STAT_DBG_RSP_CNT_ERR
- RX_DMA_CTL_STAT_DBG_RSP_DAT_ERR
- RX_DMA_CTL_STAT_DBG_WRED_DROP
- RX_DMA_CTL_STAT_DC_FIFO_ERR
- RX_DMA_CTL_STAT_MEX
- RX_DMA_CTL_STAT_PKTREAD
- RX_DMA_CTL_STAT_PKTREAD_SHIFT
- RX_DMA_CTL_STAT_PORT_DROP_PKT
- RX_DMA_CTL_STAT_PORT_FATAL
- RX_DMA_CTL_STAT_PTRREAD
- RX_DMA_CTL_STAT_PTRREAD_SHIFT
- RX_DMA_CTL_STAT_RBRFULL
- RX_DMA_CTL_STAT_RBRLOGPAGE
- RX_DMA_CTL_STAT_RBR_EMPTY
- RX_DMA_CTL_STAT_RBR_PRE_EMTY
- RX_DMA_CTL_STAT_RBR_PRE_PAR
- RX_DMA_CTL_STAT_RBR_TMOUT
- RX_DMA_CTL_STAT_RCRFULL
- RX_DMA_CTL_STAT_RCRINCON
- RX_DMA_CTL_STAT_RCRSHADOW_FULL
- RX_DMA_CTL_STAT_RCRTHRES
- RX_DMA_CTL_STAT_RCRTO
- RX_DMA_CTL_STAT_RCR_ACK_ERR
- RX_DMA_CTL_STAT_RCR_SHA_PAR
- RX_DMA_CTL_STAT_RSP_CNT_ERR
- RX_DMA_CTL_STAT_RSP_DAT_ERR
- RX_DMA_CTL_STAT_WRED_DROP
- RX_DMA_CTL_WRITE_CLEAR_ERRS
- RX_DMA_D0_CMD_DMA_EOP
- RX_DMA_D0_CMD_DMA_IT
- RX_DMA_D0_CMD_DMA_RT
- RX_DMA_DONE
- RX_DMA_EN
- RX_DMA_ENABLE
- RX_DMA_ENBL
- RX_DMA_ENT_MSK
- RX_DMA_ENT_MSK_ALL
- RX_DMA_ENT_MSK_BYTE_EN_BUS
- RX_DMA_ENT_MSK_CFIGLOGPAGE
- RX_DMA_ENT_MSK_CONFIG_ERR
- RX_DMA_ENT_MSK_DC_FIFO_ERR
- RX_DMA_ENT_MSK_PORT_DROP_PKT
- RX_DMA_ENT_MSK_RBRFULL
- RX_DMA_ENT_MSK_RBRLOGPAGE
- RX_DMA_ENT_MSK_RBR_EMPTY
- RX_DMA_ENT_MSK_RBR_PRE_EMTY
- RX_DMA_ENT_MSK_RBR_PRE_PAR
- RX_DMA_ENT_MSK_RBR_TMOUT
- RX_DMA_ENT_MSK_RCRFULL
- RX_DMA_ENT_MSK_RCRINCON
- RX_DMA_ENT_MSK_RCRTHRES
- RX_DMA_ENT_MSK_RCRTO
- RX_DMA_ENT_MSK_RCR_ACK_ERR
- RX_DMA_ENT_MSK_RCR_SHADOW_FULL
- RX_DMA_ENT_MSK_RCR_SHA_PAR
- RX_DMA_ENT_MSK_RSP_CNT_ERR
- RX_DMA_ENT_MSK_RSP_DAT_ERR
- RX_DMA_ENT_MSK_WRED_DROP
- RX_DMA_ERROR_FCS
- RX_DMA_ERROR_KEY
- RX_DMA_ERROR_L3_ERR
- RX_DMA_ERROR_L4_ERR
- RX_DMA_ERROR_MIC
- RX_DMA_ERROR_REPLAY
- RX_DMA_FPORT_MASK
- RX_DMA_FPORT_SHIFT
- RX_DMA_GET_PLEN0
- RX_DMA_GRANT
- RX_DMA_INTR
- RX_DMA_IRQ_DELAY_MSK
- RX_DMA_IRQ_DELAY_SHFT
- RX_DMA_L4_VALID
- RX_DMA_L4_VALID_PDMA
- RX_DMA_LSO
- RX_DMA_ONLY
- RX_DMA_PERIODS
- RX_DMA_PLEN0
- RX_DMA_REQUEST
- RX_DMA_RESERVED_SIZE_8723B
- RX_DMA_SIZE
- RX_DMA_SIZE_64K
- RX_DMA_SIZE_8723B
- RX_DMA_SKBUFF
- RX_DMA_STATUS_DU
- RX_DMA_STATUS_EOP
- RX_DMA_STATUS_ERROR
- RX_DMA_STATUS_FFM
- RX_DMA_STATUS_L3I
- RX_DMA_STATUS_L4I
- RX_DMA_STATUS_MI
- RX_DMA_STATUS_PHY_INFO
- RX_DMA_VID
- RX_DMA_ZERO_PADDING_EN
- RX_DONE
- RX_DONE_INT
- RX_DONE_INTR_MSK
- RX_DONT_BATCH
- RX_DOT11_MGMT
- RX_DP_CTRL
- RX_DP_CTRL_FFWD_BUSY_
- RX_DP_CTRL_RX_FFWD_
- RX_DP_STOR
- RX_DP_STORE_TOT_RXUSED_MASK_
- RX_DP_STORE_UTX_RXUSED_MASK_
- RX_DRIBBLE
- RX_DRIBBLING
- RX_DRIVING_MASK
- RX_DROP
- RX_DROP_EVENTS
- RX_DROP_MONITOR
- RX_DROP_PACKET_COUNTER
- RX_DROP_UNUSABLE
- RX_DRP_BCAST
- RX_DRP_L3BCAST
- RX_DRP_L3MCAST
- RX_DRP_MCAST
- RX_DRTH_VAL
- RX_DRVINFO_SZ
- RX_DRV_INFO_SIZE_UNIT
- RX_DRV_INFO_SIZE_UNIT_8723B
- RX_DRX_IDX
- RX_DS
- RX_DSCP_PRI_MAP0
- RX_DSCP_PRI_MAP1
- RX_DSCP_PRI_MAP2
- RX_DSCP_PRI_MAP3
- RX_DSCP_PRI_MAP4
- RX_DSCP_PRI_MAP5
- RX_DSCP_PRI_MAP6
- RX_DSCP_PRI_MAP7
- RX_DSI_DATA_TYPE_NOT_RECOGNIZED
- RX_DSI_VC_ID_INVALID
- RX_DS_CC_BIT
- RX_DVLAN_OCVLAN_ICVLAN_PKT
- RX_DVLAN_OCVLAN_ISVLAN_PKT
- RX_DVLAN_OSVLAN_ICVLAN_PKT
- RX_DVLAN_OSVLAN_ISVLAN_PKT
- RX_DV_GATE_EN0
- RX_DV_GATE_REG
- RX_DV_GATE_REG_0_ADDR
- RX_EARLY
- RX_EARLY_OFF
- RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE
- RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK
- RX_ECC_MULTI_BIT_ERROR
- RX_ECC_SINGLE_BIT_ERROR
- RX_EI
- RX_EMPTY
- RX_EMPTY_INTR
- RX_EN
- RX_ENABLE
- RX_ENABLE_ALLMULTI
- RX_ENABLE_BIT
- RX_ENABLE_INTERRUPT
- RX_ENABLE_LLC_PROMISC
- RX_ENABLE_MASK
- RX_ENABLE_NSA
- RX_ENABLE_PASS_DB
- RX_ENABLE_PASS_NSA
- RX_ENABLE_PASS_SMT
- RX_ENABLE_PROMISC
- RX_ENC_FLAG_BF
- RX_ENC_FLAG_HT_GF
- RX_ENC_FLAG_LDPC
- RX_ENC_FLAG_SHORTPRE
- RX_ENC_FLAG_SHORT_GI
- RX_ENC_FLAG_STBC_MASK
- RX_ENC_FLAG_STBC_SHIFT
- RX_ENC_HE
- RX_ENC_HT
- RX_ENC_LEGACY
- RX_ENC_VHT
- RX_END
- RX_ENP
- RX_ENTER_HIBERN8
- RX_ENTRIES
- RX_ENTRY_LPI_MODE
- RX_EN_INT
- RX_EOF
- RX_EOP
- RX_EOT
- RX_EPI_ILL_CAL_OVRD
- RX_EQ_ADJ
- RX_EQ_ADJ_EN
- RX_EQ_ADJ_VAL
- RX_EQ_GAIN1
- RX_EQ_GAIN2
- RX_ERR
- RX_ERROR
- RX_ERRORS_BC
- RX_ERRORS_CMR
- RX_ERRORS_M
- RX_ERRORS_MC
- RX_ERROR_CRC
- RX_ERROR_FIFO
- RX_ERROR_FRAME
- RX_ERROR_LENGTH
- RX_ERROR_MASK
- RX_ERROR_OVER
- RX_ERROR_Q
- RX_ERRS_TO_ENQ
- RX_ERR_CTR_OF
- RX_ERR_DET
- RX_ERR_INT
- RX_ER_BITSTUFF
- RX_ER_CRC
- RX_ER_NONOCT
- RX_ER_OVERUN
- RX_ER_PID
- RX_ESCAPE_MODE_ENTRY_ERROR
- RX_ETHER
- RX_ETHHDR_LEN_G
- RX_ETHHDR_LEN_M
- RX_ETHHDR_LEN_S
- RX_ETHHDR_LEN_V
- RX_ETH_CQE_TYPE_ETH_FASTPATH
- RX_ETH_CQE_TYPE_ETH_RAMROD
- RX_ETH_CQE_TYPE_ETH_START_AGG
- RX_ETH_CQE_TYPE_ETH_STOP_AGG
- RX_EVENT
- RX_EVM
- RX_EXCPQ_FL
- RX_EXCP_RCVD
- RX_EXIT_LPI_MODE
- RX_EXTRA
- RX_EXTRA_DATA
- RX_EXTRA_DATA_ACCEPT
- RX_EXTRA_DATA_ENBL
- RX_EXTRA_LEN
- RX_E_CLEANUP_DONE
- RX_E_FAIL
- RX_E_RXF_STARTED
- RX_E_RXF_STOPPED
- RX_E_START
- RX_E_STARTED
- RX_E_STOP
- RX_E_STOPPED
- RX_FALSE_CONTROL_ERROR
- RX_FAST_SPND
- RX_FCERR_PKTS
- RX_FCS
- RX_FCS_ERR
- RX_FCS_ERROR_COUNTER
- RX_FC_ACTIVE
- RX_FC_DEACTIVE
- RX_FC_DISABLE_F
- RX_FC_DISABLE_S
- RX_FC_DISABLE_V
- RX_FC_VALID_F
- RX_FC_VALID_S
- RX_FC_VALID_V
- RX_FD_NUM
- RX_FD_RESERVE
- RX_FETCH_DFLT_8125
- RX_FF_FL_DEF_MSK
- RX_FIFO
- RX_FIFOADDR
- RX_FIFOSEGSIZE
- RX_FIFO_CHECK
- RX_FIFO_DEPTH
- RX_FIFO_DEPTH_MSK
- RX_FIFO_DEPTH_SHFT
- RX_FIFO_EMPTY
- RX_FIFO_ENABLE
- RX_FIFO_ENABLE_MASK
- RX_FIFO_FLUSH_
- RX_FIFO_FULL
- RX_FIFO_FULLNESS_IPP_FIFO_MASK
- RX_FIFO_FULLNESS_RX_FIFO_MASK
- RX_FIFO_FULLNESS_RX_PKT_MASK
- RX_FIFO_FULL_COUNT_ZERO
- RX_FIFO_HALF_FULL
- RX_FIFO_HC
- RX_FIFO_INF
- RX_FIFO_INF_RXDUSED_
- RX_FIFO_INF_RXSUSED_
- RX_FIFO_INF_USED_
- RX_FIFO_INTS
- RX_FIFO_LC
- RX_FIFO_LVL
- RX_FIFO_MAX_NUM
- RX_FIFO_NOT_EMPTY
- RX_FIFO_OFF
- RX_FIFO_OVERRUN
- RX_FIFO_PKT_IN_NUM
- RX_FIFO_PKT_OUT_NUM
- RX_FIFO_RESET_BIT
- RX_FIFO_RST_MASK
- RX_FIFO_SC
- RX_FIFO_SIZE
- RX_FIFO_SIZE_REG
- RX_FIFO_SPACE
- RX_FIFO_SYNC_HI
- RX_FIFO_THRESH
- RX_FIFO_THRESHOLD_MASK
- RX_FIFO_THRESHOLD_NONE
- RX_FIFO_THRESHOLD_SHIFT
- RX_FIFO_WC_MSK
- RX_FIFO_WIDTH_MSK
- RX_FIFO_WIDTH_SHFT
- RX_FIFO_WORDS_REG
- RX_FIL
- RX_FILTER
- RX_FILTER_ACK
- RX_FILTER_ASSOC_REQUEST
- RX_FILTER_ASSOC_RESPONSE
- RX_FILTER_ATIM
- RX_FILTER_AUTH
- RX_FILTER_BEACON
- RX_FILTER_CFACK
- RX_FILTER_CFEND
- RX_FILTER_CFG
- RX_FILTER_CFG_DROP_ACK
- RX_FILTER_CFG_DROP_BA
- RX_FILTER_CFG_DROP_BAR
- RX_FILTER_CFG_DROP_BROADCAST
- RX_FILTER_CFG_DROP_CF_END
- RX_FILTER_CFG_DROP_CF_END_ACK
- RX_FILTER_CFG_DROP_CNTL
- RX_FILTER_CFG_DROP_CRC_ERROR
- RX_FILTER_CFG_DROP_CTS
- RX_FILTER_CFG_DROP_DUPLICATE
- RX_FILTER_CFG_DROP_MULTICAST
- RX_FILTER_CFG_DROP_NOT_MY_BSSD
- RX_FILTER_CFG_DROP_NOT_TO_ME
- RX_FILTER_CFG_DROP_PHY_ERROR
- RX_FILTER_CFG_DROP_PSPOLL
- RX_FILTER_CFG_DROP_RTS
- RX_FILTER_CFG_DROP_VER_ERROR
- RX_FILTER_CTRL
- RX_FILTER_CTS
- RX_FILTER_DEAUTH
- RX_FILTER_DISASSOC
- RX_FILTER_FAIL
- RX_FILTER_FIELD_OVERHEAD
- RX_FILTER_ID
- RX_FILTER_OPTION_DEF
- RX_FILTER_OPTION_DEF_PRSP_BCN
- RX_FILTER_OPTION_FILTER_ALL
- RX_FILTER_OPTION_JOIN
- RX_FILTER_PRESERVE
- RX_FILTER_PROBE_REQUEST
- RX_FILTER_PROBE_RESPONSE
- RX_FILTER_PSPOLL
- RX_FILTER_REASSOC_REQUEST
- RX_FILTER_REASSOC_RESPONSE
- RX_FILTER_RTS
- RX_FINISH
- RX_FIRST_DESC
- RX_FIS_D2H_REG
- RX_FIS_PIO_SETUP
- RX_FIS_SDB
- RX_FIS_UNK
- RX_FLAG
- RX_FLAG_ALLOW_SAME_PN
- RX_FLAG_AMPDU_DELIM_CRC_ERROR
- RX_FLAG_AMPDU_DELIM_CRC_KNOWN
- RX_FLAG_AMPDU_DETAILS
- RX_FLAG_AMPDU_EOF_BIT
- RX_FLAG_AMPDU_EOF_BIT_KNOWN
- RX_FLAG_AMPDU_IS_LAST
- RX_FLAG_AMPDU_LAST_KNOWN
- RX_FLAG_AMSDU_MORE
- RX_FLAG_BCAST
- RX_FLAG_BITS
- RX_FLAG_CRCERR
- RX_FLAG_DECRYPTED
- RX_FLAG_DUP_VALIDATED
- RX_FLAG_ERRORS
- RX_FLAG_FAILED_FCS_CRC
- RX_FLAG_FAILED_PLCP_CRC
- RX_FLAG_ICV_STRIPPED
- RX_FLAG_IV_STRIPPED
- RX_FLAG_LARGE
- RX_FLAG_LAST
- RX_FLAG_MACTIME_END
- RX_FLAG_MACTIME_PLCP_START
- RX_FLAG_MACTIME_START
- RX_FLAG_MCAST
- RX_FLAG_MIC_STRIPPED
- RX_FLAG_MISS
- RX_FLAG_MMIC_ERROR
- RX_FLAG_MMIC_STRIPPED
- RX_FLAG_NO_PSDU
- RX_FLAG_NO_SIGNAL_VAL
- RX_FLAG_ODD
- RX_FLAG_OFIFO
- RX_FLAG_ONLY_MONITOR
- RX_FLAG_PN_VALIDATED
- RX_FLAG_RADIOTAP_HE
- RX_FLAG_RADIOTAP_HE_MU
- RX_FLAG_RADIOTAP_LSIG
- RX_FLAG_RADIOTAP_VENDOR_DATA
- RX_FLAG_SERR
- RX_FLAG_SKIP_MONITOR
- RX_FLOW_EN
- RX_FLOW_ON_BIT
- RX_FLSH_MISSPKT_DIS
- RX_FLSH_MISSPKT_ENA
- RX_FLUSH
- RX_FLUSH_CNTL
- RX_FLUSH_DONE
- RX_FORCE_ACK_F
- RX_FORCE_ACK_S
- RX_FORCE_ACK_V
- RX_FQ_ALEMPTY_INT
- RX_FQ_ALEMPTY_TH
- RX_FQ_ALFULL_INT
- RX_FQ_ALFULL_TH
- RX_FQ_DEPTH
- RX_FQ_EMPTY_INT
- RX_FQ_FULL_INT
- RX_FQ_OUT_INT
- RX_FQ_RD_ADDR
- RX_FQ_REG_EN
- RX_FQ_START_ADDR
- RX_FQ_VLDDESC_CNT
- RX_FQ_WR_ADDR
- RX_FRAGMENTS_COUNTER
- RX_FRAGS_REFILL_WM
- RX_FRAM
- RX_FRAME_LENGTH_ERROR_COUNTER
- RX_FRAME_LEN_MASK
- RX_FRAME_PORT
- RX_FRAME_TYPE
- RX_FREEQ_EMPT
- RX_FREE_BUFFERS
- RX_FREE_BUFFER_COUNT_OFF
- RX_FSYNC_ERR_INT
- RX_FSYNC_INT
- RX_FSYNC_MASK
- RX_FS_A
- RX_FS_ADDRESS
- RX_FS_C
- RX_FS_CRC
- RX_FS_E
- RX_FS_IMPL
- RX_FS_LLC
- RX_FS_MAC
- RX_FS_SMT
- RX_FTL
- RX_FULL_INTR
- RX_GAINT_ERR
- RX_GCLKMAC_ENA
- RX_GCLKMAC_OFF
- RX_GENI_CANCEL_IRQ
- RX_GENI_GP_IRQ
- RX_GENI_GP_IRQ_EXT
- RX_GEN_WD
- RX_GET_DMA_BUFFER
- RX_GF_MM_AUTO
- RX_GF_OR_MM
- RX_GMF_AF_THR
- RX_GMF_CTRL_T
- RX_GMF_EA
- RX_GMF_FL_CTRL
- RX_GMF_FL_MSK
- RX_GMF_FL_THR
- RX_GMF_FL_THR_DEF
- RX_GMF_LP_THR
- RX_GMF_RLEV
- RX_GMF_RP
- RX_GMF_TR_THR
- RX_GMF_UP_THR
- RX_GMF_VLAN
- RX_GMF_WLEV
- RX_GMF_WP
- RX_GMII_ERR
- RX_HALF_FULL_DET
- RX_HALF_FULL_MASK
- RX_HAL_IS_CCK_RATE
- RX_HAL_IS_CCK_RATE_8723B
- RX_HANDLER
- RX_HANDLER_ANOTHER
- RX_HANDLER_ASYNC_LOCKED
- RX_HANDLER_ASYNC_UNLOCKED
- RX_HANDLER_CONSUMED
- RX_HANDLER_EXACT
- RX_HANDLER_GRP
- RX_HANDLER_PASS
- RX_HANDLER_SYNC
- RX_HASHED
- RX_HBUF
- RX_HEAD
- RX_HEADER_0
- RX_HEADER_1
- RX_HEADER_LEN
- RX_HEAD_PADDING
- RX_HEAD_WRITEBACK_ADDRH
- RX_HEAD_WRITEBACK_ADDRL
- RX_HFC_THLD_DEF
- RX_HIBERN8TIME_CAPABILITY
- RX_HOST_CMD_RESPONSE_TYPE
- RX_HOST_NOTIFICATION_TYPE
- RX_HPA_L_PA_DAC_CTL_DATA_RESET_MASK
- RX_HPA_L_PA_DAC_CTL_DATA_RESET_RESET
- RX_HPH_R_PA_DAC_CTL_DATA_RESET
- RX_HPH_R_PA_DAC_CTL_DATA_RESET_MASK
- RX_HSGEAR
- RX_HSRATE_SERIES
- RX_HS_RECEIVE_TIMEOUT_ERROR
- RX_HS_UNTERMINATED_ENABLE
- RX_HTT_HDR_STATUS_LEN
- RX_HUGE_FRAME
- RX_HW_FLOW_CTL_EN
- RX_HW_FLOW_CTL_THLD
- RX_I2S_CTL_RX_I2S_FS_RATE_F_16_KHZ
- RX_I2S_CTL_RX_I2S_FS_RATE_F_192_KHZ
- RX_I2S_CTL_RX_I2S_FS_RATE_F_32_KHZ
- RX_I2S_CTL_RX_I2S_FS_RATE_F_48_KHZ
- RX_I2S_CTL_RX_I2S_FS_RATE_F_8_KHZ
- RX_I2S_CTL_RX_I2S_FS_RATE_F_96_KHZ
- RX_I2S_CTL_RX_I2S_FS_RATE_MASK
- RX_I2S_CTL_RX_I2S_MODE_16
- RX_I2S_CTL_RX_I2S_MODE_32
- RX_I2S_CTL_RX_I2S_MODE_MASK
- RX_IA
- RX_IA_ACCEPT
- RX_IA_HASHED
- RX_IA_HASH_ACCEPT
- RX_IDAF_DWORD0
- RX_IDAF_DWORD1
- RX_IDAF_DWORD2
- RX_IDAF_DWORD3
- RX_IDAF_DWORD4
- RX_IDAF_DWORD5
- RX_IDAF_DWORD6
- RX_IDLE
- RX_IDX
- RX_IF_GAIN
- RX_INDEX_MAPPING_NUM
- RX_INDEX_NUM_MASK
- RX_INDEX_NUM_SHIFT
- RX_INDEX_RELEASE
- RX_INDEX_RING_MASK
- RX_INDEX_RING_SHIFT
- RX_INSERT_1_BYTE
- RX_INSERT_2_BYTE
- RX_INSERT_3_BYTE
- RX_INSERT_NONE
- RX_INT
- RX_INTEN
- RX_INTERRUPT_STATUS
- RX_INTR
- RX_INTR_COAL
- RX_INTS
- RX_INT_32K_CLR
- RX_INT_32K_EN
- RX_INT_THRESHOLD_MASK
- RX_INT_THRESHOLD_MULT
- RX_INV
- RX_INVALID_OPERATION
- RX_INVALID_TX_LENGTH
- RX_IPHDR_LEN_G
- RX_IPHDR_LEN_M
- RX_IPHDR_LEN_S
- RX_IPHDR_LEN_V
- RX_IPV4_EN
- RX_IPV4_ICMP_PKT
- RX_IPV4_TCP_PKT
- RX_IPV4_UDP_PKT
- RX_IPV4_UNKNOWN_PKT
- RX_IPV6_DA_MOB_DIS
- RX_IPV6_DA_MOB_ENA
- RX_IPV6_EN
- RX_IPV6_ICMP_PKT
- RX_IPV6_SA_MOB_DIS
- RX_IPV6_SA_MOB_ENA
- RX_IPV6_TCP_PKT
- RX_IPV6_UDP_PKT
- RX_IPV6_UNKNOWN_PKT
- RX_IP_HDR_ERR
- RX_IP_HDR_OK
- RX_IQPI_ILL_CAL_OVRD
- RX_IRQ_NO_COALESC
- RX_IRQ_NO_CREDIT
- RX_IRQ_NO_LLI_TIMER
- RX_IRQ_NO_PENDING
- RX_IRQ_NO_RESEND_TIMER
- RX_IRQ_REG
- RX_ISOCHRONOUS
- RX_ISOC_COMM_CHANNEL_MASK
- RX_ISOC_COMM_CHANNEL_SHIFT
- RX_ISOC_COMM_IS_ACTIVATED
- RX_JABBER_COUNTER
- RX_JABBER_INT
- RX_JABBER_PKTS
- RX_JUMBO_RING_ENTRIES
- RX_JUMBO_RING_SIZE
- RX_JUMBO_SIZE
- RX_L2ERR
- RX_L2_EN
- RX_L2_ERR
- RX_LARGE_BUF
- RX_LARGE_FIFO
- RX_LARGE_MTU_BUF
- RX_LARGE_PG_BUF
- RX_LAST
- RX_LAST_BYTE_VALID_MSK
- RX_LAST_BYTE_VALID_SHFT
- RX_LAST_DESC
- RX_LATE_COLLISION
- RX_LED_CTRL
- RX_LED_INI
- RX_LED_TST
- RX_LED_VAL
- RX_LEN
- RX_LENGTH_ERR
- RX_LENGTH_INFO_TAG
- RX_LEN_ERROR
- RX_LEN_ERR_PKTS
- RX_LEN_MASK
- RX_LEN_PKT
- RX_LEN_SHIFT
- RX_LEVEL
- RX_LE_BYTES
- RX_LE_SIZE
- RX_LINE_CONFIG_OFF
- RX_LINE_COUNT_REG
- RX_LNA_GAIN
- RX_LOCATION_INFO0_RTT_FAC_LEGACY_LSB
- RX_LOCATION_INFO0_RTT_FAC_LEGACY_MASK
- RX_LOCATION_INFO0_RTT_FAC_LEGACY_STATUS
- RX_LOCATION_INFO0_RTT_FAC_VHT_LSB
- RX_LOCATION_INFO0_RTT_FAC_VHT_MASK
- RX_LOCATION_INFO0_RTT_FAC_VHT_STATUS
- RX_LOCATION_INFO0_RTT_STRONGEST_CHAIN_LSB
- RX_LOCATION_INFO0_RTT_STRONGEST_CHAIN_MASK
- RX_LOCATION_INFO1_PKT_BW_LSB
- RX_LOCATION_INFO1_PKT_BW_MASK
- RX_LOCATION_INFO1_RTT_CFR_STATUS
- RX_LOCATION_INFO1_RTT_CIR_STATUS
- RX_LOCATION_INFO1_RTT_GI_TYPE
- RX_LOCATION_INFO1_RTT_MAC_PHY_PHASE
- RX_LOCATION_INFO1_RTT_MSC_RATE_LSB
- RX_LOCATION_INFO1_RTT_MSC_RATE_MASK
- RX_LOCATION_INFO1_RTT_PBD_LEG_BW_LSB
- RX_LOCATION_INFO1_RTT_PBD_LEG_BW_MASK
- RX_LOCATION_INFO1_RTT_PREAMBLE_TYPE_LSB
- RX_LOCATION_INFO1_RTT_PREAMBLE_TYPE_MASK
- RX_LOCATION_INFO1_RTT_TX_DATA_START_X_PHASE
- RX_LOCATION_INFO1_RTT_TX_FRAME_PHASE_LSB
- RX_LOCATION_INFO1_RTT_TX_FRAME_PHASE_MASK
- RX_LOCATION_INFO1_RX_LOCATION_VALID
- RX_LOCATION_INFO1_SKIP_P_SKIP_BTCF_LSB
- RX_LOCATION_INFO1_SKIP_P_SKIP_BTCF_MASK
- RX_LOCATION_INFO1_TIMING_BACKOFF_LSB
- RX_LOCATION_INFO1_TIMING_BACKOFF_MASK
- RX_LOCATION_INFO_CIR_STATUS
- RX_LOCATION_INFO_FAC_STATUS_LSB
- RX_LOCATION_INFO_FAC_STATUS_MASK
- RX_LOCATION_INFO_HW_IFFT_MODE
- RX_LOCATION_INFO_PKT_BW_LSB
- RX_LOCATION_INFO_PKT_BW_MASK
- RX_LOCATION_INFO_RTT_CORR_VAL_LSB
- RX_LOCATION_INFO_RTT_CORR_VAL_MASK
- RX_LOCATION_INFO_RTT_MAC_PHY_PHASE
- RX_LOCATION_INFO_RTT_TX_DATA_START_X
- RX_LOCATION_INFO_RTT_TX_FRAME_PHASE_LSB
- RX_LOCATION_INFO_RTT_TX_FRAME_PHASE_MASK
- RX_LOCATION_INFO_RX_LOCATION_VALID
- RX_LOG_MASK1
- RX_LOG_MASK1_MASK
- RX_LOG_MASK2
- RX_LOG_MASK2_MASK
- RX_LOG_PAGE_HDL
- RX_LOG_PAGE_HDL_HANDLE
- RX_LOG_PAGE_RELO1
- RX_LOG_PAGE_RELO1_RELO
- RX_LOG_PAGE_RELO2
- RX_LOG_PAGE_RELO2_RELO
- RX_LOG_PAGE_VLD
- RX_LOG_PAGE_VLD_FUNC
- RX_LOG_PAGE_VLD_FUNC_SHIFT
- RX_LOG_PAGE_VLD_PAGE0
- RX_LOG_PAGE_VLD_PAGE1
- RX_LOG_RING_SIZE
- RX_LOG_VAL1
- RX_LOG_VAL1_VALUE
- RX_LOG_VAL2
- RX_LOG_VAL2_VALUE
- RX_LOOKAHEAD_VALID_ADDRESS
- RX_LOW_JUMBO_THRES
- RX_LOW_MINI_THRES
- RX_LOW_STD_THRES
- RX_LOW_WATERMARK
- RX_LP_TX_SYNC_ERROR
- RX_LS_TERMINATED_ENABLE
- RX_MACCTL_PKT
- RX_MACIDX_G
- RX_MACIDX_M
- RX_MACIDX_S
- RX_MACIDX_V
- RX_MACSEC_ASF_FLUSH_OFF
- RX_MACSEC_ASF_FLUSH_ON
- RX_MACSEC_FLUSH_OFF
- RX_MACSEC_FLUSH_ON
- RX_MAC_D0_MAC_ID_VALID
- RX_MAC_ERR
- RX_MAC_HEADER_LENGTH
- RX_MAC_INTR
- RX_MASK
- RX_MAT_SET
- RX_MAX
- RX_MAX_ALLOC_ORDER
- RX_MAX_BURST
- RX_MAX_CNT
- RX_MAX_COUNT
- RX_MAX_PACKET_ID
- RX_MAX_PENDING
- RX_MAX_PKT
- RX_MAX_PKT_G2
- RX_MAX_PKT_OG
- RX_MAX_QUEUE
- RX_MAX_QUEUE_MEMORY
- RX_MAX_RINGS
- RX_MAX_RINGS_SZ
- RX_MAX_RING_SIZE
- RX_MAX_RSS_RINGS
- RX_MCAST
- RX_MCAST_FRAME
- RX_MCAST_PKTS
- RX_MCST_EN
- RX_MCS_MAP
- RX_MDPU_RES_STATUS_STA_ID_SHIFT
- RX_MEM_BLOCK_MASK
- RX_MEM_TEST_FAILED
- RX_MEM_TEST_FINISHED
- RX_MFF_CTRL1
- RX_MFF_CTRL2
- RX_MFF_EA
- RX_MFF_LEV
- RX_MFF_PC
- RX_MFF_RP
- RX_MFF_STAT_TO
- RX_MFF_TIST_TO
- RX_MFF_TST1
- RX_MFF_TST2
- RX_MFF_WP
- RX_MII_ERROR
- RX_MINI_RING_ENTRIES
- RX_MINI_RING_SIZE
- RX_MINI_SIZE
- RX_MIN_ACTIVATETIME_CAPABILITY
- RX_MIN_ACTIVATETIME_UNIT_US
- RX_MIN_RINGS_SZ
- RX_MISS
- RX_MISSED_FRAME
- RX_MISS_COUNT
- RX_MISS_COUNT_OVRFLOW_ENBL
- RX_MISS_ENBL
- RX_MISS_OVRFLW
- RX_MODE
- RX_MODE_ACCEPT_OVERSIZED
- RX_MODE_ACCEPT_RUNTS
- RX_MODE_ALL_MULTI
- RX_MODE_ENABLE
- RX_MODE_FLOW_CTRL_ENABLE
- RX_MODE_IPV4_FRAG_FIX
- RX_MODE_IPV6_CSUM_ENABLE
- RX_MODE_KEEP_MAC_CTRL
- RX_MODE_KEEP_PAUSE
- RX_MODE_KEEP_VLAN_TAG
- RX_MODE_LEN_CHECK
- RX_MODE_MULTI
- RX_MODE_NO_CRC_CHECK
- RX_MODE_PROM
- RX_MODE_PROMISC
- RX_MODE_RESET
- RX_MODE_RSS_ENABLE
- RX_MODE_RSS_IPV4_HASH_EN
- RX_MODE_RSS_IPV6_HASH_EN
- RX_MODE_RSS_ITBL_HASH_BITS_7
- RX_MODE_RSS_TCP_IPV4_HASH_EN
- RX_MODE_RSS_TCP_IPV6_HASH_EN
- RX_MODE_UNI
- RX_MPDU_END_INFO0_DECRYPT_ERR
- RX_MPDU_END_INFO0_FCS_ERR
- RX_MPDU_END_INFO0_LAST_MPDU
- RX_MPDU_END_INFO0_MPDU_LENGTH_ERR
- RX_MPDU_END_INFO0_OVERFLOW_ERR
- RX_MPDU_END_INFO0_POST_DELIM_CNT_LSB
- RX_MPDU_END_INFO0_POST_DELIM_CNT_MASK
- RX_MPDU_END_INFO0_POST_DELIM_ERR
- RX_MPDU_END_INFO0_RESERVED_0_LSB
- RX_MPDU_END_INFO0_RESERVED_0_MASK
- RX_MPDU_END_INFO0_TKIP_MIC_ERR
- RX_MPDU_QUEUE
- RX_MPDU_RES_STATUS_CRC_OK
- RX_MPDU_RES_STATUS_CSUM_DONE
- RX_MPDU_RES_STATUS_CSUM_OK
- RX_MPDU_RES_STATUS_DEC_DONE
- RX_MPDU_RES_STATUS_DEC_DONE_MSK
- RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP
- RX_MPDU_RES_STATUS_ICV_OK
- RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT
- RX_MPDU_RES_STATUS_KEY_PARAM_OK
- RX_MPDU_RES_STATUS_KEY_VALID
- RX_MPDU_RES_STATUS_MIC_OK
- RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR
- RX_MPDU_RES_STATUS_OVERRUN_OK
- RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME
- RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC
- RX_MPDU_RES_STATUS_SEC_CCM_ENC
- RX_MPDU_RES_STATUS_SEC_ENC_ERR
- RX_MPDU_RES_STATUS_SEC_ENC_MSK
- RX_MPDU_RES_STATUS_SEC_EXT_ENC
- RX_MPDU_RES_STATUS_SEC_NO_ENC
- RX_MPDU_RES_STATUS_SEC_TKIP_ENC
- RX_MPDU_RES_STATUS_SEC_WEP_ENC
- RX_MPDU_RES_STATUS_SRC_STA_FOUND
- RX_MPDU_RES_STATUS_STA_ID_MSK
- RX_MPDU_RES_STATUS_TTAK_OK
- RX_MPDU_START_INFO0_ENCRYPTED
- RX_MPDU_START_INFO0_ENCRYPT_TYPE_LSB
- RX_MPDU_START_INFO0_ENCRYPT_TYPE_MASK
- RX_MPDU_START_INFO0_FROM_DS
- RX_MPDU_START_INFO0_PEER_IDX_LSB
- RX_MPDU_START_INFO0_PEER_IDX_MASK
- RX_MPDU_START_INFO0_RETRY
- RX_MPDU_START_INFO0_SEQ_NUM_LSB
- RX_MPDU_START_INFO0_SEQ_NUM_MASK
- RX_MPDU_START_INFO0_TO_DS
- RX_MPDU_START_INFO0_TXBF_H_INFO
- RX_MPDU_START_INFO1_DIRECTED
- RX_MPDU_START_INFO1_TID_LSB
- RX_MPDU_START_INFO1_TID_MASK
- RX_MSDU_DECAP_8023_SNAP_LLC
- RX_MSDU_DECAP_ETHERNET2_DIX
- RX_MSDU_DECAP_NATIVE_WIFI
- RX_MSDU_DECAP_RAW
- RX_MSDU_END_INFO0_FIRST_MSDU
- RX_MSDU_END_INFO0_LAST_MSDU
- RX_MSDU_END_INFO0_MSDU_LIMIT_ERR
- RX_MSDU_END_INFO0_PRE_DELIM_ERR
- RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_LSB
- RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_MASK
- RX_MSDU_END_INFO0_RESERVED_3B
- RX_MSDU_END_INFO1_IRO_ELIGIBLE
- RX_MSDU_END_INFO1_L3_HDR_PAD_LSB
- RX_MSDU_END_INFO1_L3_HDR_PAD_MASK
- RX_MSDU_END_INFO1_TCP_FLAG_LSB
- RX_MSDU_END_INFO1_TCP_FLAG_MASK
- RX_MSDU_END_INFO1_WINDOW_SIZE_LSB
- RX_MSDU_END_INFO1_WINDOW_SIZE_MASK
- RX_MSDU_END_INFO2_DA_OFFSET_LSB
- RX_MSDU_END_INFO2_DA_OFFSET_MASK
- RX_MSDU_END_INFO2_SA_OFFSET_LSB
- RX_MSDU_END_INFO2_SA_OFFSET_MASK
- RX_MSDU_END_INFO2_TYPE_OFFSET_LSB
- RX_MSDU_END_INFO2_TYPE_OFFSET_MASK
- RX_MSDU_LIFETIME_DEF
- RX_MSDU_LIFETIME_MAX
- RX_MSDU_LIFETIME_MIN
- RX_MSDU_START_INFO0_IP_OFFSET_LSB
- RX_MSDU_START_INFO0_IP_OFFSET_MASK
- RX_MSDU_START_INFO0_MSDU_LENGTH_LSB
- RX_MSDU_START_INFO0_MSDU_LENGTH_MASK
- RX_MSDU_START_INFO0_RING_MASK_LSB
- RX_MSDU_START_INFO0_RING_MASK_MASK
- RX_MSDU_START_INFO0_TCP_UDP_OFFSET_LSB
- RX_MSDU_START_INFO0_TCP_UDP_OFFSET_MASK
- RX_MSDU_START_INFO1_DECAP_FORMAT_LSB
- RX_MSDU_START_INFO1_DECAP_FORMAT_MASK
- RX_MSDU_START_INFO1_IPV4_PROTO
- RX_MSDU_START_INFO1_IPV6_PROTO
- RX_MSDU_START_INFO1_IP_FRAG
- RX_MSDU_START_INFO1_MSDU_NUMBER_LSB
- RX_MSDU_START_INFO1_MSDU_NUMBER_MASK
- RX_MSDU_START_INFO1_SA_IDX_LSB
- RX_MSDU_START_INFO1_SA_IDX_MASK
- RX_MSDU_START_INFO1_TCP_ONLY_ACK
- RX_MSDU_START_INFO1_TCP_PROTO
- RX_MSDU_START_INFO1_UDP_PROTO
- RX_MSDU_START_INFO2_DA_BCAST_MCAST
- RX_MSDU_START_INFO2_DA_IDX_LSB
- RX_MSDU_START_INFO2_DA_IDX_MASK
- RX_MSDU_START_INFO2_IP_PROTO_FIELD_LSB
- RX_MSDU_START_INFO2_IP_PROTO_FIELD_MASK
- RX_MSRABT
- RX_MSVALID
- RX_MTU_SIZE_MASK
- RX_MULT
- RX_MULTCAST_ACCEPT
- RX_MULTICAST
- RX_MULTICAST_PACKET_COUNTER
- RX_MULTICAST_PKT
- RX_MULTIPKT
- RX_MULTI_EN
- RX_MULT_G2
- RX_MULT_OG
- RX_NAMES
- RX_NAMES_SIZE
- RX_NEXT
- RX_NIC_BUFSIZE
- RX_NOBUFF
- RX_NON_PTP_PKT
- RX_NORMAL_DESC0_OVT_INDEX
- RX_NORMAL_DESC0_OVT_LEN
- RX_NORMAL_DESC0_OVT_POS
- RX_NORMAL_DESC0_OVT_WIDTH
- RX_NORMAL_DESC2_HL_INDEX
- RX_NORMAL_DESC2_HL_LEN
- RX_NORMAL_DESC2_HL_POS
- RX_NORMAL_DESC2_HL_WIDTH
- RX_NORMAL_DESC2_TNP_INDEX
- RX_NORMAL_DESC2_TNP_WIDTH
- RX_NORMAL_DESC3_CDA_INDEX
- RX_NORMAL_DESC3_CDA_LEN
- RX_NORMAL_DESC3_CDA_POS
- RX_NORMAL_DESC3_CDA_WIDTH
- RX_NORMAL_DESC3_CTXT_INDEX
- RX_NORMAL_DESC3_CTXT_LEN
- RX_NORMAL_DESC3_CTXT_POS
- RX_NORMAL_DESC3_CTXT_WIDTH
- RX_NORMAL_DESC3_ES_INDEX
- RX_NORMAL_DESC3_ES_LEN
- RX_NORMAL_DESC3_ES_POS
- RX_NORMAL_DESC3_ES_WIDTH
- RX_NORMAL_DESC3_ETLT_INDEX
- RX_NORMAL_DESC3_ETLT_LEN
- RX_NORMAL_DESC3_ETLT_POS
- RX_NORMAL_DESC3_ETLT_WIDTH
- RX_NORMAL_DESC3_FD_INDEX
- RX_NORMAL_DESC3_FD_LEN
- RX_NORMAL_DESC3_FD_POS
- RX_NORMAL_DESC3_FD_WIDTH
- RX_NORMAL_DESC3_INTE_INDEX
- RX_NORMAL_DESC3_INTE_LEN
- RX_NORMAL_DESC3_INTE_POS
- RX_NORMAL_DESC3_INTE_WIDTH
- RX_NORMAL_DESC3_L34T_INDEX
- RX_NORMAL_DESC3_L34T_LEN
- RX_NORMAL_DESC3_L34T_POS
- RX_NORMAL_DESC3_L34T_WIDTH
- RX_NORMAL_DESC3_LD_INDEX
- RX_NORMAL_DESC3_LD_LEN
- RX_NORMAL_DESC3_LD_POS
- RX_NORMAL_DESC3_LD_WIDTH
- RX_NORMAL_DESC3_OWN_INDEX
- RX_NORMAL_DESC3_OWN_LEN
- RX_NORMAL_DESC3_OWN_POS
- RX_NORMAL_DESC3_OWN_WIDTH
- RX_NORMAL_DESC3_PL_INDEX
- RX_NORMAL_DESC3_PL_LEN
- RX_NORMAL_DESC3_PL_POS
- RX_NORMAL_DESC3_PL_WIDTH
- RX_NORMAL_DESC3_RSV_INDEX
- RX_NORMAL_DESC3_RSV_LEN
- RX_NORMAL_DESC3_RSV_POS
- RX_NORMAL_DESC3_RSV_WIDTH
- RX_NOT_ALMOST_EMPTY_BIT
- RX_NOT_ALMOST_FULL_BIT
- RX_NOT_EMPTY_BIT
- RX_NOT_FULL_BIT
- RX_NOT_IP_PKT
- RX_NO_AUTOTIMER
- RX_NO_DATA_CHAIN_A_MSK
- RX_NO_DATA_CHAIN_A_POS
- RX_NO_DATA_CHAIN_B_MSK
- RX_NO_DATA_CHAIN_B_POS
- RX_NO_DATA_CHANNEL_MSK
- RX_NO_DATA_CHANNEL_POS
- RX_NO_DATA_FRAME_TIME_MSK
- RX_NO_DATA_FRAME_TIME_POS
- RX_NO_DATA_INFO_ERR_BAD_MAC_HDR
- RX_NO_DATA_INFO_ERR_BAD_PLCP
- RX_NO_DATA_INFO_ERR_MSK
- RX_NO_DATA_INFO_ERR_NONE
- RX_NO_DATA_INFO_ERR_NO_DELIM
- RX_NO_DATA_INFO_ERR_POS
- RX_NO_DATA_INFO_ERR_UNSUPPORTED_RATE
- RX_NO_DATA_INFO_TYPE_HE_TB_UNMATCHED
- RX_NO_DATA_INFO_TYPE_MSK
- RX_NO_DATA_INFO_TYPE_MU_UNMATCHED
- RX_NO_DATA_INFO_TYPE_NDP
- RX_NO_DATA_INFO_TYPE_NONE
- RX_NO_DATA_INFO_TYPE_POS
- RX_NO_DATA_INFO_TYPE_RX_ERR
- RX_NO_DATA_NOTIF
- RX_NO_DATA_RX_VEC0_HE_NSTS_MSK
- RX_NO_DATA_RX_VEC0_VHT_NSTS_MSK
- RX_NO_DESC
- RX_NO_OP
- RX_NO_PTP
- RX_NUMBER
- RX_NUMBER_AUDIO
- RX_NUMBER_MIDI
- RX_NUM_FIFO
- RX_NUM_QUEUES
- RX_NXTDESC_PTR
- RX_OAM_PKT
- RX_OCTS
- RX_OFF
- RX_OFFLOADS
- RX_OFFSET
- RX_OFL
- RX_OFLO
- RX_OK
- RX_OK_ACCEPT
- RX_OK_ENBL
- RX_ON
- RX_ORUN
- RX_ORUN_OCTS
- RX_OTHER_PKT
- RX_OVERFLOW_DET
- RX_OVERFLOW_ERR
- RX_OVERFLOW_MASK
- RX_OVERLEN
- RX_OVERRUN
- RX_OVERRUN_BIT
- RX_OVERRUN_ERROR_INT
- RX_OVERRUN_FRAME_CNT
- RX_OVERRUN_IDX
- RX_OVERSIZE_PACKET_COUNTER
- RX_OVERSIZE_PKTS
- RX_P0
- RX_P1
- RX_PACKET_ATTRIBUTES_CONTEXT_INDEX
- RX_PACKET_ATTRIBUTES_CONTEXT_LEN
- RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX
- RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_LEN
- RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_POS
- RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH
- RX_PACKET_ATTRIBUTES_CONTEXT_POS
- RX_PACKET_ATTRIBUTES_CONTEXT_WIDTH
- RX_PACKET_ATTRIBUTES_CSUM_DONE_INDEX
- RX_PACKET_ATTRIBUTES_CSUM_DONE_LEN
- RX_PACKET_ATTRIBUTES_CSUM_DONE_POS
- RX_PACKET_ATTRIBUTES_CSUM_DONE_WIDTH
- RX_PACKET_ATTRIBUTES_FIRST_INDEX
- RX_PACKET_ATTRIBUTES_FIRST_WIDTH
- RX_PACKET_ATTRIBUTES_INCOMPLETE_LEN
- RX_PACKET_ATTRIBUTES_INCOMPLETE_POS
- RX_PACKET_ATTRIBUTES_LAST_INDEX
- RX_PACKET_ATTRIBUTES_LAST_WIDTH
- RX_PACKET_ATTRIBUTES_RSS_HASH_INDEX
- RX_PACKET_ATTRIBUTES_RSS_HASH_LEN
- RX_PACKET_ATTRIBUTES_RSS_HASH_POS
- RX_PACKET_ATTRIBUTES_RSS_HASH_WIDTH
- RX_PACKET_ATTRIBUTES_RX_TSTAMP_INDEX
- RX_PACKET_ATTRIBUTES_RX_TSTAMP_LEN
- RX_PACKET_ATTRIBUTES_RX_TSTAMP_POS
- RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH
- RX_PACKET_ATTRIBUTES_TNPCSUM_DONE_INDEX
- RX_PACKET_ATTRIBUTES_TNPCSUM_DONE_WIDTH
- RX_PACKET_ATTRIBUTES_TNP_INDEX
- RX_PACKET_ATTRIBUTES_TNP_WIDTH
- RX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX
- RX_PACKET_ATTRIBUTES_VLAN_CTAG_LEN
- RX_PACKET_ATTRIBUTES_VLAN_CTAG_POS
- RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH
- RX_PACKET_COUNTER
- RX_PACKET_ERRORS_CRC_INDEX
- RX_PACKET_ERRORS_CRC_LEN
- RX_PACKET_ERRORS_CRC_POS
- RX_PACKET_ERRORS_CRC_WIDTH
- RX_PACKET_ERRORS_FRAME_INDEX
- RX_PACKET_ERRORS_FRAME_LEN
- RX_PACKET_ERRORS_FRAME_POS
- RX_PACKET_ERRORS_FRAME_WIDTH
- RX_PACKET_ERRORS_LENGTH_INDEX
- RX_PACKET_ERRORS_LENGTH_LEN
- RX_PACKET_ERRORS_LENGTH_POS
- RX_PACKET_ERRORS_LENGTH_WIDTH
- RX_PACKET_ERRORS_OVERRUN_INDEX
- RX_PACKET_ERRORS_OVERRUN_LEN
- RX_PACKET_ERRORS_OVERRUN_POS
- RX_PACKET_ERRORS_OVERRUN_WIDTH
- RX_PACKET_EXCLUDE_DIFFERED_DATA_CHUNKS
- RX_PACKET_FILTER
- RX_PACKET_RAM
- RX_PACKET_TYPE
- RX_PAD_STRIP
- RX_PAGE_SIZE_MASK
- RX_PAGE_SIZE_MTU_COUNT_MASK
- RX_PAGE_SIZE_MTU_COUNT_SHIFT
- RX_PAGE_SIZE_MTU_OFF_MASK
- RX_PAGE_SIZE_MTU_OFF_SHIFT
- RX_PAGE_SIZE_MTU_STRIDE_MASK
- RX_PAGE_SIZE_MTU_STRIDE_SHIFT
- RX_PAGE_SIZE_REG_VALUE
- RX_PAGE_SIZE_SHIFT
- RX_PANIC_JUMBO_REFILL
- RX_PANIC_JUMBO_THRES
- RX_PANIC_MINI_REFILL
- RX_PANIC_MINI_THRES
- RX_PANIC_STD_REFILL
- RX_PANIC_STD_THRES
- RX_PARITY_BIT
- RX_PARSER_CFG
- RX_PATH_SELECTION_DIFF_TH
- RX_PATH_SELECTION_SS_TH_LOW
- RX_PAUSE
- RX_PAUSE_EN
- RX_PAUSE_FRAME_PACKET_COUNTER
- RX_PAUSE_PKTS
- RX_PAUSE_THRESH_OFF_MASK
- RX_PAUSE_THRESH_OFF_SHIFT
- RX_PAUSE_THRESH_ON_MASK
- RX_PAUSE_THRESH_ON_SHIFT
- RX_PAUSE_THRESH_QUANTUM
- RX_PAYLOAD_ERR
- RX_PA_CFG_IGNORE_FRM_ERR
- RX_PA_CFG_IGNORE_L2_ERR
- RX_PA_CFG_IGNORE_LLC_CTRL
- RX_PA_CFG_IGNORE_SNAP_OUI
- RX_PA_CFG_STRIP_VLAN_TAG
- RX_PENDING
- RX_PENDING_WATERMARK
- RX_PERPKT
- RX_PERPKTCLR
- RX_PHY_ERR_INC
- RX_PHY_PPDU_END_INFO0_ERR_CCK_BLOCKER
- RX_PHY_PPDU_END_INFO0_ERR_CCK_HEADER_CRC
- RX_PHY_PPDU_END_INFO0_ERR_CCK_LENGTH
- RX_PHY_PPDU_END_INFO0_ERR_CCK_POWER_DROP
- RX_PHY_PPDU_END_INFO0_ERR_CCK_RATE
- RX_PHY_PPDU_END_INFO0_ERR_CCK_RESTART
- RX_PHY_PPDU_END_INFO0_ERR_CCK_SERVICE
- RX_PHY_PPDU_END_INFO0_ERR_CCK_TIMING
- RX_PHY_PPDU_END_INFO0_ERR_FALSE_RADAR_EXT
- RX_PHY_PPDU_END_INFO0_ERR_GREEN_FIELD
- RX_PHY_PPDU_END_INFO0_ERR_HT_CRC
- RX_PHY_PPDU_END_INFO0_ERR_HT_LENGTH
- RX_PHY_PPDU_END_INFO0_ERR_HT_RATE
- RX_PHY_PPDU_END_INFO0_ERR_HT_ZLF
- RX_PHY_PPDU_END_INFO0_ERR_LEG_HT_MISMATCH
- RX_PHY_PPDU_END_INFO0_ERR_OFDM_LENGTH
- RX_PHY_PPDU_END_INFO0_ERR_OFDM_PARITY
- RX_PHY_PPDU_END_INFO0_ERR_OFDM_POWER_DROP
- RX_PHY_PPDU_END_INFO0_ERR_OFDM_RATE
- RX_PHY_PPDU_END_INFO0_ERR_OFDM_RESTART
- RX_PHY_PPDU_END_INFO0_ERR_OFDM_SERVICE
- RX_PHY_PPDU_END_INFO0_ERR_OFDM_TIMING
- RX_PHY_PPDU_END_INFO0_ERR_RADAR
- RX_PHY_PPDU_END_INFO0_ERR_RX_ABORT
- RX_PHY_PPDU_END_INFO0_ERR_RX_DYN_BW
- RX_PHY_PPDU_END_INFO0_ERR_RX_NAP
- RX_PHY_PPDU_END_INFO0_ERR_SPECTRAL_SCAN
- RX_PHY_PPDU_END_INFO0_ERR_VHT_CRC
- RX_PHY_PPDU_END_INFO0_ERR_VHT_LSIG
- RX_PHY_PPDU_END_INFO0_ERR_VHT_SIGA
- RX_PHY_PPDU_END_INFO1_ERR_BT_COLLISION
- RX_PHY_PPDU_END_INFO1_ERR_DEFER_NAP
- RX_PHY_PPDU_END_INFO1_ERR_FDOMAIN_TIMEOUT
- RX_PHY_PPDU_END_INFO1_ERR_LSIG_REL_CHECK
- RX_PHY_PPDU_END_INFO1_ERR_MU_FEEDBACK
- RX_PHY_PPDU_END_INFO1_ERR_OFDM_LDPC_DECODER
- RX_PHY_PPDU_END_INFO1_ERR_RX_CBF
- RX_PHY_PPDU_END_INFO1_ERR_TX_INTERRUPT_RX
- RX_PHY_PPDU_END_INFO1_ERR_VHT_NDP
- RX_PHY_PPDU_END_INFO1_ERR_VHT_NSYM
- RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_EXT_SYM
- RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID0
- RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID1_62
- RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID63
- RX_PI
- RX_PIC_INTR
- RX_PKTS
- RX_PKTS_OK
- RX_PKT_ALIGNMENT
- RX_PKT_BROADCAST
- RX_PKT_BUF_SZ
- RX_PKT_CTR_OF
- RX_PKT_DEST_ADDR
- RX_PKT_DROP
- RX_PKT_END_INFO0_ERR_CCK_POWER_DROP
- RX_PKT_END_INFO0_ERR_CCK_RESTART
- RX_PKT_END_INFO0_ERR_OFDM_POWER_DROP
- RX_PKT_END_INFO0_ERR_OFDM_RESTART
- RX_PKT_END_INFO0_ERR_TX_INTERRUPT_RX
- RX_PKT_END_INFO0_RX_SUCCESS
- RX_PKT_ERR
- RX_PKT_INT0
- RX_PKT_INT1
- RX_PKT_INT2
- RX_PKT_INT3
- RX_PKT_IS_ETHERNETV2
- RX_PKT_IS_IPV4
- RX_PKT_IS_VLAN_TAGGED
- RX_PKT_LAYER4_TYPE_MASK
- RX_PKT_LAYER4_TYPE_TCP_IPV4
- RX_PKT_LEN
- RX_PKT_OFFSET
- RX_PKT_PHY_MATCH
- RX_PKT_RCVD
- RX_PKT_RESET
- RX_PKT_SIZE
- RX_PKT_SKB_LEN
- RX_PKT_STATUS_ALIGN_MASK
- RX_PKT_STATUS_ALIGN_SHIFT
- RX_PKT_STATUS_BCAST_MASK
- RX_PKT_STATUS_BCAST_SHIFT
- RX_PKT_STATUS_CODE_MASK
- RX_PKT_STATUS_CODE_SHIFT
- RX_PKT_STATUS_CRC_MASK
- RX_PKT_STATUS_CRC_SHIFT
- RX_PKT_STATUS_CTRL_MASK
- RX_PKT_STATUS_CTRL_SHIFT
- RX_PKT_STATUS_FRAG_MASK
- RX_PKT_STATUS_FRAG_SHIFT
- RX_PKT_STATUS_MCAST_MASK
- RX_PKT_STATUS_MCAST_SHIFT
- RX_PKT_STATUS_OK_MASK
- RX_PKT_STATUS_OK_SHIFT
- RX_PKT_STATUS_PAUSE_MASK
- RX_PKT_STATUS_PAUSE_SHIFT
- RX_PKT_STATUS_RUNT_MASK
- RX_PKT_STATUS_RUNT_SHIFT
- RX_PKT_STATUS_SIZE_MASK
- RX_PKT_STATUS_SIZE_SHIFT
- RX_PKT_STATUS_TRUNK_MASK
- RX_PKT_STATUS_TRUNK_SHIFT
- RX_PKT_STATUS_UPDATE_MASK
- RX_PKT_STATUS_UPDATE_SHIFT
- RX_PKT_STATUS_VLAN_MASK
- RX_PKT_STATUS_VLAN_SHIFT
- RX_PKT_STATUS_VLAN_TAG_MASK
- RX_PKT_STATUS_VLAN_TAG_SHIFT
- RX_PKT_SZ
- RX_PKY_LIMIT
- RX_PLUS_COMP3_ENC_PKT
- RX_PLUS_COMP_L3_HEAD_OFF_MASK
- RX_PLUS_COMP_L3_HEAD_OFF_SHIFT
- RX_PNOWakeUp
- RX_POLARITY_INVERSION_MASK
- RX_POLARITY_INVERSION_SHIFT
- RX_POLL_DEMAND
- RX_POOL_SIZE
- RX_POST_REQ_ALLOC
- RX_PPDU_END_FLAGS_PHY_ERR
- RX_PPDU_END_FLAGS_RX_LOCATION
- RX_PPDU_END_FLAGS_TXBF_H_INFO
- RX_PPDU_END_INFO0_BB_CAPTURED_CHANNEL
- RX_PPDU_END_INFO0_FLAGS_TX_HT_VHT_ACK
- RX_PPDU_END_INFO0_RX_ANTENNA_LSB
- RX_PPDU_END_INFO0_RX_ANTENNA_MASK
- RX_PPDU_END_INFO1_BB_DATA
- RX_PPDU_END_INFO1_PEER_IDX_LSB
- RX_PPDU_END_INFO1_PEER_IDX_MASK
- RX_PPDU_END_INFO1_PEER_IDX_VALID
- RX_PPDU_END_INFO1_PPDU_DONE
- RX_PPDU_END_RTT_CORRELATION_VALUE_LSB
- RX_PPDU_END_RTT_CORRELATION_VALUE_MASK
- RX_PPDU_END_RTT_NORMAL_MODE
- RX_PPDU_END_RTT_UNUSED_LSB
- RX_PPDU_END_RTT_UNUSED_MASK
- RX_PPDU_END_RX_INFO_BB_CAPTURED_CHANNEL
- RX_PPDU_END_RX_INFO_OTP_TXBF_DISABLE
- RX_PPDU_END_RX_INFO_RX_ANTENNA_LSB
- RX_PPDU_END_RX_INFO_RX_ANTENNA_MASK
- RX_PPDU_END_RX_INFO_RX_PHY_PPDU_END_VALID
- RX_PPDU_END_RX_INFO_RX_PKT_END_VALID
- RX_PPDU_END_RX_INFO_RX_TIMING_OFFSET_VALID
- RX_PPDU_END_RX_INFO_TX_HT_VHT_ACK
- RX_PPDU_END_RX_INFO_UNSUPPORTED_MU_NC
- RX_PPDU_END_RX_TIMING_OFFSET_LSB
- RX_PPDU_END_RX_TIMING_OFFSET_MASK
- RX_PPDU_START_INFO0_IS_GREENFIELD
- RX_PPDU_START_INFO1_L_SIG_LENGTH_LSB
- RX_PPDU_START_INFO1_L_SIG_LENGTH_MASK
- RX_PPDU_START_INFO1_L_SIG_PARITY
- RX_PPDU_START_INFO1_L_SIG_RATE_LSB
- RX_PPDU_START_INFO1_L_SIG_RATE_MASK
- RX_PPDU_START_INFO1_L_SIG_RATE_SELECT
- RX_PPDU_START_INFO1_L_SIG_TAIL_LSB
- RX_PPDU_START_INFO1_L_SIG_TAIL_MASK
- RX_PPDU_START_INFO1_PREAMBLE_TYPE_LSB
- RX_PPDU_START_INFO1_PREAMBLE_TYPE_MASK
- RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_LSB
- RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_MASK
- RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_LSB
- RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_MASK
- RX_PPDU_START_INFO3_TXBF_H_INFO
- RX_PPDU_START_INFO4_VHT_SIG_B_LSB
- RX_PPDU_START_INFO4_VHT_SIG_B_MASK
- RX_PPDU_START_INFO5_SERVICE_LSB
- RX_PPDU_START_INFO5_SERVICE_MASK
- RX_PPDU_START_RATE_FLAG
- RX_PREPAD_SIZE
- RX_PRESET_TABLE_MAX
- RX_PRESET_TABLE_QSFP_RX_AMP
- RX_PRESET_TABLE_QSFP_RX_AMP_APPLY
- RX_PRESET_TABLE_QSFP_RX_CDR
- RX_PRESET_TABLE_QSFP_RX_CDR_APPLY
- RX_PRESET_TABLE_QSFP_RX_EMP
- RX_PRESET_TABLE_QSFP_RX_EMP_APPLY
- RX_PRESET_TABLE_RESERVED
- RX_PRIMS_STATUS
- RX_PRIORITY_MAPPING
- RX_PRIO_QUEUES
- RX_PROCESS_RESULT_NOTHING_TO_DO
- RX_PROCESS_RESULT_PACKET_DROPPED
- RX_PROCESS_RESULT_PACKET_RECEIVED
- RX_PROG_ALMOST_REG
- RX_PROMISCUOUS
- RX_PROM_ACCEPT
- RX_PROTOCOL_ERROR
- RX_PROT_VIOLATION
- RX_PS
- RX_PSC_A0
- RX_PSC_A1
- RX_PSC_A2
- RX_PSC_A3
- RX_PSC_CAL
- RX_PSC_RDY
- RX_PTE
- RX_PTP_ANNOUNCE
- RX_PTP_DELAY_REQ
- RX_PTP_DELAY_RESP
- RX_PTP_FOLLOW_UP
- RX_PTP_MGMT
- RX_PTP_PDELAY_FOLLOW_UP
- RX_PTP_PDELAY_REQ
- RX_PTP_PDELAY_RESP
- RX_PTP_PKT_ERR
- RX_PTP_PKT_SUC
- RX_PTP_RESV_MSG
- RX_PTP_SIGNAL
- RX_PTP_SYNC
- RX_PTP_VER_MASK
- RX_PTP_VER_SHIFT
- RX_PTR_BOUNDARY_SHIFT
- RX_PTR_MAX_SHIFT
- RX_PTR_SYNCDLY_DIS
- RX_PTR_SYNCDLY_ENA
- RX_PULL_LEN
- RX_PWMGEAR
- RX_Q
- RX_QCHECK_PERIOD
- RX_QLEN
- RX_QS
- RX_QUEUED
- RX_QUEUES_NOTIFICATION
- RX_QUEUE_0_PRIORITY
- RX_QUEUE_1_PRIORITY
- RX_QUEUE_2_PRIORITY
- RX_QUEUE_3_PRIORITY
- RX_QUEUE_4_PRIORITY
- RX_QUEUE_5_PRIORITY
- RX_QUEUE_6_PRIORITY
- RX_QUEUE_7_PRIORITY
- RX_QUEUE_CB_SIZE
- RX_QUEUE_CFG_Q0_SZ
- RX_QUEUE_CFG_Q1_SZ
- RX_QUEUE_CFG_Q2_SZ
- RX_QUEUE_CFG_Q3_SZ
- RX_QUEUE_CFG_Q4_SZ
- RX_QUEUE_CFG_Q5_SZ
- RX_QUEUE_CFG_Q6_SZ
- RX_QUEUE_CFG_Q7_SZ
- RX_QUEUE_DYNAMIC
- RX_QUEUE_ENTRIES
- RX_QUEUE_LENGTH
- RX_QUEUE_MASK
- RX_QUEUE_OFFSET
- RX_QUEUE_PRI_0
- RX_QUEUE_PRI_1
- RX_QUEUE_PRI_2
- RX_QUEUE_PRI_3
- RX_QUEUE_PRI_4
- RX_QUEUE_PRI_5
- RX_QUEUE_PRI_6
- RX_QUEUE_PRI_7
- RX_QUEUE_RD_PTR_OFF
- RX_QUEUE_SIZE
- RX_QUEUE_SIZE_LOG
- RX_QUEUE_WR_PTR_OFF
- RX_QUIET_EN
- RX_Q_ENTRIES
- RX_Q_ENTRY_CHANNEL_SHIFT
- RX_Q_ENTRY_LENGTH_MASK
- RX_Q_LEN
- RX_RADIOTAP_PRESENT
- RX_RAM
- RX_RAWQ_FL
- RX_RAW_RCVD
- RX_RB_TIMEOUT
- RX_RDY_MASK
- RX_RDY_SHIFT
- RX_READ
- RX_READY
- RX_RECLAIM_PERIOD
- RX_RECV
- RX_RED
- RX_RED_10K_12K_FIFO_MASK
- RX_RED_4K_6K_FIFO_MASK
- RX_RED_6K_8K_FIFO_MASK
- RX_RED_8K_10K_FIFO_MASK
- RX_RED_OCTS
- RX_REE_CTRL_DATA_MASK
- RX_REFCLKFREQ
- RX_REG_DESC_SIZE
- RX_REG_OFFSET_DESC0
- RX_REG_OFFSET_DESC1
- RX_REG_OFFSET_DESC2
- RX_REG_SET
- RX_REORDER_BUF_TIMEOUT_MQ
- RX_RESET_DONE
- RX_RESET_TRIES
- RX_RESOLUTION
- RX_RESUME
- RX_RES_PHY_FLAGS_AGG
- RX_RES_PHY_FLAGS_AGG_MSK
- RX_RES_PHY_FLAGS_ANTENNA
- RX_RES_PHY_FLAGS_ANTENNA_MSK
- RX_RES_PHY_FLAGS_ANTENNA_POS
- RX_RES_PHY_FLAGS_BAND_24
- RX_RES_PHY_FLAGS_BAND_24_MSK
- RX_RES_PHY_FLAGS_MOD_CCK
- RX_RES_PHY_FLAGS_MOD_CCK_MSK
- RX_RES_PHY_FLAGS_NARROW_BAND
- RX_RES_PHY_FLAGS_NARROW_BAND_MSK
- RX_RES_PHY_FLAGS_OFDM_GF
- RX_RES_PHY_FLAGS_OFDM_HT
- RX_RES_PHY_FLAGS_OFDM_VHT
- RX_RES_PHY_FLAGS_SHORT_PREAMBLE
- RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK
- RX_RES_STATUS_BAD_ICV_MIC
- RX_RES_STATUS_BAD_KEY_TTAK
- RX_RES_STATUS_DECRYPT_OK
- RX_RES_STATUS_DECRYPT_TYPE_MSK
- RX_RES_STATUS_NOT_DECRYPT
- RX_RES_STATUS_NO_CRC32_ERROR
- RX_RES_STATUS_NO_RXE_OVERFLOW
- RX_RES_STATUS_NO_STATION_INFO_MISMATCH
- RX_RES_STATUS_SEC_TYPE_CCMP
- RX_RES_STATUS_SEC_TYPE_ERR
- RX_RES_STATUS_SEC_TYPE_MSK
- RX_RES_STATUS_SEC_TYPE_NONE
- RX_RES_STATUS_SEC_TYPE_TKIP
- RX_RES_STATUS_SEC_TYPE_WEP
- RX_RES_STATUS_STATION_FOUND
- RX_RETURN_RING_ENTRIES
- RX_RETURN_RING_SIZE
- RX_RF_FREQUENCY
- RX_RF_GAIN
- RX_RING
- RX_RING_ALLOC_SIZE
- RX_RING_BUFFERS
- RX_RING_BYTES
- RX_RING_CSR
- RX_RING_CSR_RING_SIZE
- RX_RING_CSR_RXD_SIZE
- RX_RING_CSR_RXD_WRITEBACK_SIZE
- RX_RING_DEFAULT
- RX_RING_DR_MOD_MASK
- RX_RING_ENTRIES
- RX_RING_LEN_BITS
- RX_RING_MASK
- RX_RING_MAX
- RX_RING_MAXSIZE
- RX_RING_MIN
- RX_RING_MOD_MASK
- RX_RING_NR
- RX_RING_ORG_BUFF3
- RX_RING_ORG_BUFF5
- RX_RING_PRI_0
- RX_RING_PRI_1
- RX_RING_PRI_2
- RX_RING_PRI_3
- RX_RING_PRI_4
- RX_RING_PRI_5
- RX_RING_PRI_6
- RX_RING_PRI_7
- RX_RING_SHADOW_SPACE
- RX_RING_SIZE
- RX_RING_SIZE_POW
- RX_RING_SZ
- RX_RING_SZ_MASK
- RX_RISC_INT_32K_STATUS
- RX_RISC_INT_32K_STA_MASK
- RX_RSS_CID
- RX_RST
- RX_RTR_FRAME
- RX_RUNNING
- RX_RUNT
- RX_RUNT_ACCEPT
- RX_RUNT_ENBL
- RX_RUNT_PKT
- RX_RX0FF_BASE
- RX_RXMAXPKTSZ
- RX_RXMAXPKTSZ_MSK
- RX_RXPKTRDY
- RX_SBE
- RX_SDCAL0_OVRD
- RX_SDCAL1_OVRD
- RX_SEC_CNT0
- RX_SENDSTALL
- RX_SEND_CRC
- RX_SENT
- RX_SENTSTALL
- RX_SEQ_START
- RX_SERVICE_INT
- RX_SETUP
- RX_SET_BUFF_ADDR
- RX_SFD_GPIO_MASK
- RX_SFD_GPIO_SHIFT
- RX_SGE
- RX_SGE_CNT
- RX_SGE_MASK
- RX_SGE_MASK_LEN
- RX_SGE_MASK_LEN_MASK
- RX_SG_REQUESTED
- RX_SG_SUPPORTED
- RX_SHIFT
- RX_SIGDET_HL_FILT_TMR
- RX_SIGQ
- RX_SIZE
- RX_SKB_ALLOC_SIZE
- RX_SKB_LEN
- RX_SKB_POOL_SIZE
- RX_SKIP
- RX_SLAVE
- RX_SLC_EEN0_OVRD
- RX_SLC_EEN1_OVRD
- RX_SLC_EEP0_OVRD
- RX_SLC_EEP1_OVRD
- RX_SLC_EON0_OVRD
- RX_SLC_EON1_OVRD
- RX_SLC_EOP0_OVRD
- RX_SLC_EOP1_OVRD
- RX_SLC_IEN0_OVRD
- RX_SLC_IEN1_OVRD
- RX_SLC_IEP0_OVRD
- RX_SLC_IEP1_OVRD
- RX_SLC_INIT
- RX_SLC_ION0_OVRD
- RX_SLC_ION1_OVRD
- RX_SLC_IOP0_OVRD
- RX_SLC_IOP1_OVRD
- RX_SLC_QEN0_OVRD
- RX_SLC_QEN1_OVRD
- RX_SLC_QEP0_OVRD
- RX_SLC_QEP1_OVRD
- RX_SLC_QON0_OVRD
- RX_SLC_QON1_OVRD
- RX_SLC_QOP0_OVRD
- RX_SLC_QOP1_OVRD
- RX_SLC_RUN
- RX_SLOT
- RX_SLOT_8CH
- RX_SLOT_MONO
- RX_SLOT_STEREO
- RX_SMALL_FIFO
- RX_SMALL_MTU_BUF
- RX_SMALL_PG_BUF
- RX_SMASK
- RX_SMOOTH
- RX_SMOOTH_FACTOR
- RX_SNAPSHOT_LOCKED
- RX_SOT_ERROR
- RX_SOT_SYNC_ERROR
- RX_SPARE_COUNT
- RX_SPARE_RECOVER_VAL
- RX_SPDSEL_20DEC
- RX_SPDSEL_40DEC
- RX_SPDSEL_80DEC
- RX_SPND
- RX_SQ_EN
- RX_SRAM_END
- RX_SRAM_POOL_FREE
- RX_SRAM_START
- RX_SS_BURST
- RX_STALE_CNT
- RX_START
- RX_STATS_ENUM_LAST
- RX_STATS_NUM
- RX_STATUS
- RX_STATUS_ALIGNMENT_ERROR
- RX_STATUS_BCAST
- RX_STATUS_BE
- RX_STATUS_BUFFER_FULL
- RX_STATUS_COUNT_REG
- RX_STATUS_CRC_ERROR
- RX_STATUS_DA_FILTERED
- RX_STATUS_DESC_SIZE
- RX_STATUS_DESC_SIZE_8723B
- RX_STATUS_ERR
- RX_STATUS_FIFO
- RX_STATUS_FIFO_PEEK
- RX_STATUS_GOOD_FRAME
- RX_STATUS_L2_MCAST
- RX_STATUS_LEN
- RX_STATUS_MCAST
- RX_STATUS_NUM
- RX_STATUS_OF
- RX_STATUS_OVERFLOW
- RX_STATUS_OVFLOW
- RX_STATUS_PARSE_FAIL
- RX_STATUS_PR
- RX_STATUS_REMOTE_TX_XOFFED
- RX_STATUS_RUNT_FRAME
- RX_STATUS_RX_ERR
- RX_STATUS_SFD_NOT_FOUND
- RX_STATUS_SUCCESS
- RX_STATUS_TOO_LONG_BAD_ALIGN
- RX_STATUS_TOO_LONG_BAD_CRC
- RX_STATUS_TOO_LONG_GOOD_CRC
- RX_STATUS_UCAST
- RX_STATUS_XOFF_RCVD
- RX_STATUS_XON_RCVD
- RX_STAT_ADD
- RX_STAT_INC
- RX_STAT_M
- RX_STA_CNT0
- RX_STA_CNT0_CRC_ERR
- RX_STA_CNT0_PHY_ERR
- RX_STA_CNT1
- RX_STA_CNT1_FALSE_CCA
- RX_STA_CNT1_PLCP_ERR
- RX_STA_CNT2
- RX_STA_CNT2_RX_DUPLI_COUNT
- RX_STA_CNT2_RX_FIFO_OVERFLOW
- RX_STD_RING_ENTRIES
- RX_STD_RING_SIZE
- RX_STFW_DIS
- RX_STFW_ENA
- RX_STP
- RX_STREAM_ENBL
- RX_STS_BCST_
- RX_STS_BF_
- RX_STS_COLL_
- RX_STS_CRC_
- RX_STS_CRC_ERR_
- RX_STS_CS_
- RX_STS_DB_
- RX_STS_DRIBBLING_
- RX_STS_ES_
- RX_STS_ETH_TYPE_
- RX_STS_FF_
- RX_STS_FL_
- RX_STS_FRAME_TYPE_
- RX_STS_FT_
- RX_STS_LENGTH_ERR_
- RX_STS_LEN_ERR_
- RX_STS_LE_
- RX_STS_MCAST_
- RX_STS_ME_
- RX_STS_MF_
- RX_STS_MII_ERR_
- RX_STS_PKT_LEN_
- RX_STS_RF_
- RX_STS_RUNT_ERR_
- RX_STS_RW_
- RX_STS_TL_
- RX_STS_TOO_LONG_
- RX_STS_WDOG_TMT_
- RX_SUSPEND
- RX_SUSPENDED
- RX_SVLAN_PKT
- RX_SWIVEL_OFF_VAL
- RX_SYMBOL_CLK_GATE_EN
- RX_SYMBOL_ERR
- RX_SYNC_SEL_MASK
- RX_SYNC_SHIFT_BASE
- RX_SYNC_SRG
- RX_T5_ETHHDR_LEN_G
- RX_T5_ETHHDR_LEN_M
- RX_T5_ETHHDR_LEN_S
- RX_T5_ETHHDR_LEN_V
- RX_T6_ETHHDR_LEN_G
- RX_T6_ETHHDR_LEN_M
- RX_TABLE_ADDR_MASK
- RX_TAG_MAX
- RX_TAIL
- RX_TAILDESC_PTR
- RX_TAIL_SET_TOP_INT_EN_
- RX_TAIL_SET_TOP_INT_VEC_EN_
- RX_TCPHDR_LEN_G
- RX_TCPHDR_LEN_M
- RX_TCPHDR_LEN_S
- RX_TCPHDR_LEN_V
- RX_TC_INT
- RX_TERMINATION_FORCE_ENABLE
- RX_TERM_LOAD_DIS
- RX_THR
- RX_THRESHOLD
- RX_THRESH_CE4100_DFLT
- RX_THRESH_DEF
- RX_THRESH_DFLT
- RX_THRESH_MAX
- RX_THRESH_MIN
- RX_THRESH_QUARK_X1000_DFLT
- RX_THR_B
- RX_THR_EN
- RX_THR_HIGH
- RX_THR_SLOW
- RX_THR_SUPPER
- RX_TIMEOUT
- RX_TIMEOUT_PS_POLL_DEF
- RX_TIMEOUT_PS_POLL_MAX
- RX_TIMEOUT_PS_POLL_MIN
- RX_TIMEOUT_UPSD_DEF
- RX_TIMEOUT_UPSD_MAX
- RX_TIMEOUT_UPSD_MIN
- RX_TOS_STEERING
- RX_TOTAL_DISCARDS
- RX_TOTAL_SIZE
- RX_TOUT_THLD_DEF
- RX_TPA_END_CMPL_ERRORS_SHIFT
- RX_TPA_END_CMP_AGG_BUFS
- RX_TPA_END_CMP_AGG_BUFS_P5
- RX_TPA_END_CMP_AGG_BUFS_SHIFT
- RX_TPA_END_CMP_AGG_BUFS_SHIFT_P5
- RX_TPA_END_CMP_AGG_ID
- RX_TPA_END_CMP_AGG_ID_P5
- RX_TPA_END_CMP_AGG_ID_SHIFT
- RX_TPA_END_CMP_AGG_ID_SHIFT_P5
- RX_TPA_END_CMP_ERRORS
- RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT
- RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_FLUSH
- RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NOT_ON_CHIP
- RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER
- RX_TPA_END_CMP_ERRORS_BUFFER_ERROR_RSV_ERROR
- RX_TPA_END_CMP_ERRORS_P5
- RX_TPA_END_CMP_FLAGS
- RX_TPA_END_CMP_FLAGS_ITYPES
- RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT
- RX_TPA_END_CMP_FLAGS_ITYPE_TCP
- RX_TPA_END_CMP_FLAGS_PLACEMENT
- RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO
- RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS
- RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO
- RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS
- RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO
- RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT
- RX_TPA_END_CMP_FLAGS_RSS_VALID
- RX_TPA_END_CMP_FLAGS_SHIFT
- RX_TPA_END_CMP_LEN
- RX_TPA_END_CMP_LEN_SHIFT
- RX_TPA_END_CMP_PAYLOAD_OFFSET
- RX_TPA_END_CMP_PAYLOAD_OFFSET_P5
- RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT
- RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT_P5
- RX_TPA_END_CMP_TPA_DUP_ACKS
- RX_TPA_END_CMP_TPA_SEGS
- RX_TPA_END_CMP_TPA_SEGS_SHIFT
- RX_TPA_END_CMP_TPA_SEG_LEN
- RX_TPA_END_CMP_TYPE
- RX_TPA_END_CMP_V1
- RX_TPA_END_CMP_V2
- RX_TPA_END_GRO_TS
- RX_TPA_START_CMPL_CFA_CODE_SHIFT
- RX_TPA_START_CMP_AGG_ID
- RX_TPA_START_CMP_AGG_ID_P5
- RX_TPA_START_CMP_AGG_ID_SHIFT
- RX_TPA_START_CMP_AGG_ID_SHIFT_P5
- RX_TPA_START_CMP_CFA_CODE
- RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT
- RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_FLUSH
- RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_MASK
- RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_NO_BUFFER
- RX_TPA_START_CMP_ERRORS_BUFFER_ERROR_SHIFT
- RX_TPA_START_CMP_FLAGS
- RX_TPA_START_CMP_FLAGS2_CSUM_CMPL
- RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_SHIFT
- RX_TPA_START_CMP_FLAGS2_CSUM_CMPL_VALID
- RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT
- RX_TPA_START_CMP_FLAGS2_EXT_META_FORMAT_SHIFT
- RX_TPA_START_CMP_FLAGS2_IP_CS_CALC
- RX_TPA_START_CMP_FLAGS2_IP_TYPE
- RX_TPA_START_CMP_FLAGS2_L4_CS_CALC
- RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC
- RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC
- RX_TPA_START_CMP_FLAGS_ERROR
- RX_TPA_START_CMP_FLAGS_ITYPES
- RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT
- RX_TPA_START_CMP_FLAGS_ITYPE_TCP
- RX_TPA_START_CMP_FLAGS_PLACEMENT
- RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS
- RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO
- RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS
- RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO
- RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT
- RX_TPA_START_CMP_FLAGS_RSS_VALID
- RX_TPA_START_CMP_FLAGS_SHIFT
- RX_TPA_START_CMP_FLAGS_TIMESTAMP
- RX_TPA_START_CMP_LEN
- RX_TPA_START_CMP_LEN_SHIFT
- RX_TPA_START_CMP_RSS_HASH_TYPE
- RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT
- RX_TPA_START_CMP_TYPE
- RX_TPA_START_CMP_V1
- RX_TPA_START_CMP_V2
- RX_TR
- RX_TRAFFIC_INTR
- RX_TRAFFIC_INT_n
- RX_TRAFFIC_STEER_RULE_COUNT
- RX_TRANSFER
- RX_TRIGGER
- RX_TRUNC_OFF
- RX_TRUNC_ON
- RX_TS_EN
- RX_TS_FIFO1_SYNC_RST
- RX_TS_FIFO2_SYNC_RST
- RX_TUNING_CNT
- RX_TXSTATUS_FIFO
- RX_TX_DATA_PORT
- RX_TX_FEEDBACK
- RX_TX_FRAME_RESPONSE_TYPE
- RX_TX_PER_PKT_FEEDBACK
- RX_TX_RATE_HISTORY
- RX_TX_STATUS
- RX_TYPE
- RX_TYPE_C2H
- RX_TYPE_DATA_PKT
- RX_TYPE_ERROR
- RX_T_DONE
- RX_UCAST
- RX_UCAST_PKTS
- RX_UCST_EN
- RX_UNCPL_INT_EN
- RX_UNDERRUN_BIT
- RX_UNDERSIZE_FCERR_PKTS
- RX_UNDERSIZE_PACKET_COUNTER
- RX_UNDERSIZE_PKTS
- RX_UNKNOWN_OP_CODE_COUNTER
- RX_UNMAPPED_BUF
- RX_UNTAG_PKT
- RX_URBS_COUNT
- RX_URB_COUNT
- RX_URB_FAIL
- RX_URB_SIZE
- RX_USED_ADD
- RX_USED_SET
- RX_USER_ABORT
- RX_U_CNTRL_FRAME
- RX_VALVC
- RX_VALVP
- RX_VC_TABLE
- RX_VC_TABLE_SZ
- RX_VLAN1
- RX_VLAN2
- RX_VLANHDR_LEN
- RX_VLAN_8125
- RX_VLAN_HEADER_INSERTION
- RX_VLAN_INNER_8125
- RX_VLAN_OUTER_8125
- RX_VLAN_STEERING
- RX_VLAN_STRIP_OFF
- RX_VLAN_STRIP_ON
- RX_VLAN_TAG
- RX_VPVC
- RX_W1C_BITS
- RX_WATCHDOG_ERR
- RX_WATERMARK
- RX_WDOG_TIMER
- RX_WORD_LEN_MASK
- RX_WORK_PER_LOOP
- RX_XGXS_INTR
- RX_ZERO_EN
- RX_mask
- RXbcasts
- RXcmd
- RXn_B6_CTL_MUTE_DISABLE
- RXn_B6_CTL_MUTE_ENABLE
- RXn_B6_CTL_MUTE_MASK
- RXrptr
- RXwptr
- RY
- RY0
- RY0d
- RY1
- RY1d
- RY2
- RY2d
- RYAR1
- RYCR
- RYEGAIN
- RYOS_REPORT_NUMBER_SPECIAL
- RYOS_USB_INTERFACE_PROTOCOL
- RYRCNT
- RYxR_DAY_MASK
- RYxR_MONTH_MASK
- RYxR_MONTH_S
- RYxR_YEAR_MASK
- RYxR_YEAR_S
- RZ
- RZA1_ADDR
- RZA1_NPINS
- RZA1_NPORTS
- RZA1_PBDC_REG
- RZA1_PFCEA_REG
- RZA1_PFCE_REG
- RZA1_PFC_REG
- RZA1_PIBC_REG
- RZA1_PINMUX
- RZA1_PINS_PER_PORT
- RZA1_PIN_ID_TO_PIN
- RZA1_PIN_ID_TO_PORT
- RZA1_PIPC_REG
- RZA1_PMC_REG
- RZA1_PM_REG
- RZA1_PPR_REG
- RZA1_P_REG
- RZA2_DSCR
- RZA2_PCKIO
- RZA2_PDR
- RZA2_PDR_INPUT
- RZA2_PDR_MASK
- RZA2_PDR_OUTPUT
- RZA2_PFENET
- RZA2_PFS
- RZA2_PHMOMO
- RZA2_PIDR
- RZA2_PIN
- RZA2_PINMUX
- RZA2_PINS_PER_PORT
- RZA2_PIN_ID_TO_PIN
- RZA2_PIN_ID_TO_PORT
- RZA2_PMR
- RZA2_PODR
- RZA2_PPOC
- RZA2_PWPR
- RZA_420
- RZA_DWN_EN
- RZA_EN
- RZA_H_DIF
- RZA_H_LPF
- RZA_H_PHS
- RZA_H_TYP
- RZA_I_HPS
- RZA_I_VPS
- RZA_MODE
- RZA_MODE_ONE_SHOT
- RZA_O_HSZ
- RZA_O_VSZ
- RZA_PRINT_REGISTER
- RZA_SDR_C_BAD_H
- RZA_SDR_C_BAD_L
- RZA_SDR_C_OFT
- RZA_SDR_C_PTR_E
- RZA_SDR_C_PTR_S
- RZA_SDR_C_SAD_H
- RZA_SDR_C_SAD_L
- RZA_SDR_Y_BAD_H
- RZA_SDR_Y_BAD_L
- RZA_SDR_Y_OFT
- RZA_SDR_Y_PTR_E
- RZA_SDR_Y_PTR_S
- RZA_SDR_Y_SAD_H
- RZA_SDR_Y_SAD_L
- RZA_V_DIF
- RZA_V_LPF
- RZA_V_PHS_C
- RZA_V_PHS_Y
- RZA_V_TYP
- RZB_420
- RZB_EN
- RZB_H_DIF
- RZB_H_LPF
- RZB_H_TYP
- RZB_I_HPS
- RZB_I_VPS
- RZB_MODE
- RZB_O_HSZ
- RZB_O_VSZ
- RZB_SDR_C_BAD_H
- RZB_SDR_C_BAD_L
- RZB_SDR_C_PTR_E
- RZB_SDR_C_PTR_S
- RZB_SDR_C_SAD_H
- RZB_SDR_C_SAD_L
- RZB_SDR_Y_BAD_H
- RZB_SDR_Y_BAD_L
- RZB_SDR_Y_OFT
- RZB_SDR_Y_PTR_E
- RZB_SDR_Y_PTR_S
- RZB_SDR_Y_SAD_H
- RZB_SDR_Y_SAD_L
- RZB_V_DIF
- RZB_V_LPF
- RZB_V_TYP
- RZEBRA1_AGC
- RZEBRA1_CHANNEL
- RZEBRA1_CHARGEPUMP
- RZEBRA1_HSSIENABLE
- RZEBRA1_RXHPFCORNER
- RZEBRA1_RXLPF
- RZEBRA1_TRXENABLE1
- RZEBRA1_TRXENABLE2
- RZEBRA1_TXGAIN
- RZEBRA1_TXLPF
- RZERO_10_OHM
- RZERO_135_OHM
- RZERO_1850_OHM
- RZERO_2000_OHM
- RZERO_2100_OHM
- RZERO_2250_OHM
- RZERO_2500_OHM
- RZERO_2750_OHM
- RZERO_3000_OHM
- RZERO_3250_OHM
- RZERO_341_OHM
- RZERO_677_OHM
- RZERO_883_OHM
- RZERO_USE_EXT_RES
- RZN1_FUNC_0L
- RZN1_FUNC_CAN
- RZN1_FUNC_CLK_ETH_MII_RGMII_RMII
- RZN1_FUNC_CLK_ETH_NAND
- RZN1_FUNC_DELTA_SIGMA
- RZN1_FUNC_ETHERCAT
- RZN1_FUNC_ETH_MDIO
- RZN1_FUNC_ETH_MDIO_E1
- RZN1_FUNC_GPIO
- RZN1_FUNC_HIGHZ
- RZN1_FUNC_HIGHZ1
- RZN1_FUNC_I2C
- RZN1_FUNC_L2_OFFSET
- RZN1_FUNC_LCD
- RZN1_FUNC_LCD_E
- RZN1_FUNC_MAC_MTIP_SWITCH
- RZN1_FUNC_MAX
- RZN1_FUNC_MDIO0_E1_ECAT
- RZN1_FUNC_MDIO0_E1_GMAC0
- RZN1_FUNC_MDIO0_E1_GMAC1
- RZN1_FUNC_MDIO0_E1_HIGHZ
- RZN1_FUNC_MDIO0_E1_HWRTOS
- RZN1_FUNC_MDIO0_E1_S3_MDIO0
- RZN1_FUNC_MDIO0_E1_S3_MDIO1
- RZN1_FUNC_MDIO0_E1_SWITCH
- RZN1_FUNC_MDIO0_ECAT
- RZN1_FUNC_MDIO0_GMAC0
- RZN1_FUNC_MDIO0_GMAC1
- RZN1_FUNC_MDIO0_HIGHZ
- RZN1_FUNC_MDIO0_HWRTOS
- RZN1_FUNC_MDIO0_S3_MDIO0
- RZN1_FUNC_MDIO0_S3_MDIO1
- RZN1_FUNC_MDIO0_SWITCH
- RZN1_FUNC_MDIO1_E1_ECAT
- RZN1_FUNC_MDIO1_E1_GMAC0
- RZN1_FUNC_MDIO1_E1_GMAC1
- RZN1_FUNC_MDIO1_E1_HIGHZ
- RZN1_FUNC_MDIO1_E1_HWRTOS
- RZN1_FUNC_MDIO1_E1_S3_MDIO0
- RZN1_FUNC_MDIO1_E1_S3_MDIO1
- RZN1_FUNC_MDIO1_E1_SWITCH
- RZN1_FUNC_MDIO1_ECAT
- RZN1_FUNC_MDIO1_GMAC0
- RZN1_FUNC_MDIO1_GMAC1
- RZN1_FUNC_MDIO1_HIGHZ
- RZN1_FUNC_MDIO1_HWRTOS
- RZN1_FUNC_MDIO1_S3_MDIO0
- RZN1_FUNC_MDIO1_S3_MDIO1
- RZN1_FUNC_MDIO1_SWITCH
- RZN1_FUNC_MDIO_OFFSET
- RZN1_FUNC_MSEBIM
- RZN1_FUNC_MSEBIM_E
- RZN1_FUNC_MSEBIS
- RZN1_FUNC_MSEBIS_E
- RZN1_FUNC_PTO_PWM
- RZN1_FUNC_PTO_PWM1
- RZN1_FUNC_PTO_PWM2
- RZN1_FUNC_PTO_PWM3
- RZN1_FUNC_PTO_PWM4
- RZN1_FUNC_QSPI
- RZN1_FUNC_RSV
- RZN1_FUNC_RSV_E
- RZN1_FUNC_RSV_E1
- RZN1_FUNC_SAFE
- RZN1_FUNC_SDIO
- RZN1_FUNC_SDIO_E
- RZN1_FUNC_SERCOS3
- RZN1_FUNC_SGPIO0_M
- RZN1_FUNC_SGPIO1_M
- RZN1_FUNC_SGPIO2_M
- RZN1_FUNC_SGPIO3_M
- RZN1_FUNC_SGPIO4_S
- RZN1_FUNC_SPI0_M
- RZN1_FUNC_SPI0_M_E
- RZN1_FUNC_SPI1_M
- RZN1_FUNC_SPI1_M_E
- RZN1_FUNC_SPI2_M
- RZN1_FUNC_SPI2_M_E
- RZN1_FUNC_SPI3_M
- RZN1_FUNC_SPI3_M_E
- RZN1_FUNC_SPI4_S
- RZN1_FUNC_SPI4_S_E
- RZN1_FUNC_SPI5_S
- RZN1_FUNC_SPI5_S_E
- RZN1_FUNC_UART0
- RZN1_FUNC_UART0_E
- RZN1_FUNC_UART0_I
- RZN1_FUNC_UART0_I_E
- RZN1_FUNC_UART1
- RZN1_FUNC_UART1_E
- RZN1_FUNC_UART1_I
- RZN1_FUNC_UART1_I_E
- RZN1_FUNC_UART2
- RZN1_FUNC_UART2_E
- RZN1_FUNC_UART2_I
- RZN1_FUNC_UART2_I_E
- RZN1_FUNC_UART3
- RZN1_FUNC_UART3_E
- RZN1_FUNC_UART4
- RZN1_FUNC_UART4_E
- RZN1_FUNC_UART5
- RZN1_FUNC_UART5_E
- RZN1_FUNC_UART6
- RZN1_FUNC_UART6_E
- RZN1_FUNC_UART7
- RZN1_FUNC_UART7_E
- RZN1_FUNC_USB
- RZN1_L1_FUNCTION
- RZN1_L1_FUNCTION_L2
- RZN1_L1_FUNC_MASK
- RZN1_L1_PIN_DRIVE_STRENGTH
- RZN1_L1_PIN_DRIVE_STRENGTH_12MA
- RZN1_L1_PIN_DRIVE_STRENGTH_4MA
- RZN1_L1_PIN_DRIVE_STRENGTH_6MA
- RZN1_L1_PIN_DRIVE_STRENGTH_8MA
- RZN1_L1_PIN_PULL
- RZN1_L1_PIN_PULL_DOWN
- RZN1_L1_PIN_PULL_NONE
- RZN1_L1_PIN_PULL_UP
- RZN1_PIN
- RZN1_PINMUX
- RZN1_PINS_PROP
- R_000000_MC_STATUS
- R_000001_MC_FB_LOCATION
- R_000002_MC_AGP_LOCATION
- R_000003_MC_AGP_BASE
- R_000004_MC_AGP_BASE_2
- R_000004_MC_FB_LOCATION
- R_000005_MC_AGP_LOCATION
- R_000006_AGP_BASE
- R_000007_AGP_BASE_2
- R_000009_MC_CNTL1
- R_00000D_SCLK_CNTL
- R_00000D_SCLK_CNTL_M6
- R_00000F_CP_DYN_CNTL
- R_000011_E2_DYN_CNTL
- R_000011_K8_FB_LOCATION
- R_000012_MC_MISC_UMA_CNTL
- R_000013_IDCT_DYN_CNTL
- R_00001E_K8_FB_LOCATION
- R_000030_BUS_CNTL
- R_000040_GEN_INT_CNTL
- R_000044_GEN_INT_STATUS
- R_00004C_BUS_CNTL
- R_000050_CRTC_GEN_CNTL
- R_000054_CRTC_EXT_CNTL
- R_00005F_MC_MISC_UMA_CNTL
- R_000070_MC_IND_INDEX
- R_000074_MC_IND_DATA
- R_000078_MC_INDEX
- R_00007C_MC_DATA
- R_000090_MC_SYSTEM_STATUS
- R_0000F0_RBBM_SOFT_RESET
- R_0000F8_CONFIG_MEMSIZE
- R_000100_MCCFG_FB_LOCATION
- R_000100_MC_PT0_CNTL
- R_000102_MC_PT0_CONTEXT0_CNTL
- R_000104_MC_INIT_MISC_LAT_TIMER
- R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR
- R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR
- R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR
- R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR
- R_000134_HDP_FB_LOCATION
- R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR
- R_000148_MC_FB_LOCATION
- R_00014C_MC_AGP_LOCATION
- R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR
- R_00015C_AGP_BASE_2
- R_00015C_NB_TOM
- R_00016C_MC_PT0_CLIENT0_CNTL
- R_000170_AGP_BASE
- R_0001F8_MC_IND_INDEX
- R_0001FC_MC_IND_DATA
- R_00023C_DISPLAY_BASE_ADDR
- R_000260_CUR_OFFSET
- R_000300_VGA_RENDER_CONTROL
- R_000310_VGA_MEMORY_BASE_ADDRESS
- R_000328_VGA_HDP_CONTROL
- R_000330_D1VGA_CONTROL
- R_000338_D2VGA_CONTROL
- R_00033C_CRTC2_DISPLAY_BASE_ADDR
- R_000360_CUR2_OFFSET
- R_0003C2_GENMO_WT
- R_0003F8_CRTC2_GEN_CNTL
- R_000420_OV0_SCALE_CNTL
- R_00070C_CP_RB_RPTR_ADDR
- R_000740_CP_CSQ_CNTL
- R_000770_SCRATCH_UMSK
- R_000774_SCRATCH_ADDR
- R_0007C0_CP_STAT
- R_000E40_RBBM_STATUS
- R_000E50_SRBM_STATUS
- R_000E60_SRBM_SOFT_RESET
- R_0028F8_MC_INDEX
- R_0028FC_MC_DATA
- R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL
- R_006080_D1CRTC_CONTROL
- R_0060A4_D1CRTC_STATUS_FRAME_COUNT
- R_0060E8_D1CRTC_UPDATE_LOCK
- R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS
- R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS
- R_006520_DC_LB_MEMORY_SPLIT
- R_006534_D1MODE_VBLANK_STATUS
- R_006540_DxMODE_INT_MASK
- R_006548_D1MODE_PRIORITY_A_CNT
- R_00654C_D1MODE_PRIORITY_B_CNT
- R_006880_D2CRTC_CONTROL
- R_0068A4_D2CRTC_STATUS_FRAME_COUNT
- R_0068E8_D2CRTC_UPDATE_LOCK
- R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS
- R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS
- R_006C9C_DCP_CONTROL
- R_006D34_D2MODE_VBLANK_STATUS
- R_006D48_D2MODE_PRIORITY_A_CNT
- R_006D4C_D2MODE_PRIORITY_B_CNT
- R_006D58_LB_MAX_REQ_OUTSTANDING
- R_007404_HDMI0_STATUS
- R_007408_HDMI0_AUDIO_PACKET_CONTROL
- R_007828_DACA_AUTODETECT_CONTROL
- R_007838_DACA_AUTODETECT_INT_CONTROL
- R_007A28_DACB_AUTODETECT_CONTROL
- R_007A38_DACB_AUTODETECT_INT_CONTROL
- R_007D00_DC_HOT_PLUG_DETECT1_CONTROL
- R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS
- R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL
- R_007D10_DC_HOT_PLUG_DETECT2_CONTROL
- R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS
- R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL
- R_007EDC_DISP_INTERRUPT_STATUS
- R_008010_GRBM_STATUS
- R_008014_GRBM_STATUS2
- R_008020_GRBM_SOFT_RESET
- R_0086D8_CP_ME_CNTL
- R_008C44_SQ_ESGS_RING_SIZE
- R_008C4C_SQ_GSVS_RING_SIZE
- R_008C54_SQ_ESTMP_RING_SIZE
- R_008C5C_SQ_GSTMP_RING_SIZE
- R_008C64_SQ_VSTMP_RING_SIZE
- R_008C6C_SQ_PSTMP_RING_SIZE
- R_008C74_SQ_FBUF_RING_SIZE
- R_008C7C_SQ_REDUC_RING_SIZE
- R_00_15
- R_00_CHIP_VERSION
- R_01_INC_DELAY
- R_028000_DB_DEPTH_SIZE
- R_028004_DB_DEPTH_VIEW
- R_028008_DB_DEPTH_VIEW
- R_028010_DB_DEPTH_INFO
- R_028040_DB_Z_INFO
- R_028044_DB_STENCIL_INFO
- R_028058_DB_DEPTH_SIZE
- R_02805C_DB_DEPTH_SLICE
- R_028060_CB_COLOR0_SIZE
- R_028064_CB_COLOR1_SIZE
- R_028068_CB_COLOR2_SIZE
- R_02806C_CB_COLOR3_SIZE
- R_028070_CB_COLOR4_SIZE
- R_028074_CB_COLOR5_SIZE
- R_028078_CB_COLOR6_SIZE
- R_02807C_CB_COLOR7_SIZE
- R_028080_CB_COLOR0_VIEW
- R_028084_CB_COLOR1_VIEW
- R_028088_CB_COLOR2_VIEW
- R_02808C_CB_COLOR3_VIEW
- R_028090_CB_COLOR4_VIEW
- R_028094_CB_COLOR5_VIEW
- R_028098_CB_COLOR6_VIEW
- R_02809C_CB_COLOR7_VIEW
- R_0280A0_CB_COLOR0_INFO
- R_0280A4_CB_COLOR1_INFO
- R_0280A8_CB_COLOR2_INFO
- R_0280AC_CB_COLOR3_INFO
- R_0280B0_CB_COLOR4_INFO
- R_0280B4_CB_COLOR5_INFO
- R_0280B8_CB_COLOR6_INFO
- R_0280BC_CB_COLOR7_INFO
- R_0280C0_CB_COLOR0_TILE
- R_0280C4_CB_COLOR1_TILE
- R_0280C8_CB_COLOR2_TILE
- R_0280CC_CB_COLOR3_TILE
- R_0280D0_CB_COLOR4_TILE
- R_0280D4_CB_COLOR5_TILE
- R_0280D8_CB_COLOR6_TILE
- R_0280DC_CB_COLOR7_TILE
- R_0280E0_CB_COLOR0_FRAG
- R_0280E4_CB_COLOR1_FRAG
- R_0280E8_CB_COLOR2_FRAG
- R_0280EC_CB_COLOR3_FRAG
- R_0280F0_CB_COLOR4_FRAG
- R_0280F4_CB_COLOR5_FRAG
- R_0280F8_CB_COLOR6_FRAG
- R_0280FC_CB_COLOR7_FRAG
- R_028100_CB_COLOR0_MASK
- R_028104_CB_COLOR1_MASK
- R_028108_CB_COLOR2_MASK
- R_02810C_CB_COLOR3_MASK
- R_028110_CB_COLOR4_MASK
- R_028114_CB_COLOR5_MASK
- R_028118_CB_COLOR6_MASK
- R_02811C_CB_COLOR7_MASK
- R_028238_CB_TARGET_MASK
- R_02823C_CB_SHADER_MASK
- R_028800_DB_DEPTH_CONTROL
- R_028808_CB_COLOR_CONTROL
- R_0288A8_SQ_ESGS_RING_ITEMSIZE
- R_0288AC_SQ_GSVS_RING_ITEMSIZE
- R_0288B0_SQ_ESTMP_RING_ITEMSIZE
- R_0288B4_SQ_GSTMP_RING_ITEMSIZE
- R_0288B8_SQ_VSTMP_RING_ITEMSIZE
- R_0288BC_SQ_PSTMP_RING_ITEMSIZE
- R_0288C0_SQ_FBUF_RING_ITEMSIZE
- R_0288C4_SQ_REDUC_RING_ITEMSIZE
- R_0288C8_SQ_GS_VERT_ITEMSIZE
- R_028AB0_VGT_STRMOUT_EN
- R_028B20_VGT_STRMOUT_BUFFER_EN
- R_028C04_PA_SC_AA_CONFIG
- R_028C6C_CB_COLOR0_VIEW
- R_028C70_CB_COLOR0_INFO
- R_028C74_CB_COLOR0_ATTRIB
- R_02_INPUT_CNTL_1
- R_030000_SQ_TEX_RESOURCE_WORD0_0
- R_030004_SQ_TEX_RESOURCE_WORD1_0
- R_030008_SQ_TEX_RESOURCE_WORD2_0
- R_03000C_SQ_TEX_RESOURCE_WORD3_0
- R_030010_SQ_TEX_RESOURCE_WORD4_0
- R_030014_SQ_TEX_RESOURCE_WORD5_0
- R_030018_SQ_TEX_RESOURCE_WORD6_0
- R_03001C_SQ_TEX_RESOURCE_WORD7_0
- R_038000_SQ_TEX_RESOURCE_WORD0_0
- R_038004_SQ_TEX_RESOURCE_WORD1_0
- R_038010_SQ_TEX_RESOURCE_WORD4_0
- R_038014_SQ_TEX_RESOURCE_WORD5_0
- R_03_INPUT_CNTL_2
- R_04_INPUT_CNTL_3
- R_05_INPUT_CNTL_4
- R_06_H_SYNC_START
- R_07_H_SYNC_STOP
- R_08_SYNC_CNTL
- R_09_LUMA_CNTL
- R_0A_LUMA_BRIGHT_CNTL
- R_0B_LUMA_CONTRAST_CNTL
- R_0C_CHROMA_SAT_CNTL
- R_0D_CHROMA_HUE_CNTL
- R_0E_CHROMA_CNTL_1
- R_0F_CHROMA_GAIN_CNTL
- R_10_CHROMA_CNTL_2
- R_11_MODE_DELAY_CNTL
- R_12
- R_12_RT_SIGNAL_CNTL
- R_13_RT_X_PORT_OUT_CNTL
- R_14_ANAL_ADC_COMPAT_CNTL
- R_15_VGATE_START_FID_CHG
- R_16
- R_16_19
- R_16_31
- R_16_VGATE_STOP
- R_17_MISC_VGATE_CONF_AND_MSB
- R_18_RAW_DATA_GAIN_CNTL
- R_19_RAW_DATA_OFF_CNTL
- R_1A_COLOR_KILL_LVL_CNTL
- R_1B_MISC_TVVCRDET
- R_1C_ENHAN_COMB_CTRL1
- R_1D_ENHAN_COMB_CTRL2
- R_1E_STATUS_BYTE_1_VD_DEC
- R_1F_STATUS_BYTE_2_VD_DEC
- R_20_39
- R_23_INPUT_CNTL_5
- R_24
- R_24_INPUT_CNTL_6
- R_25_INPUT_CNTL_7
- R_28
- R_29_COMP_DELAY
- R_2A_COMP_BRIGHT_CNTL
- R_2B_COMP_CONTRAST_CNTL
- R_2C_COMP_SAT_CNTL
- R_2D_INTERRUPT_MASK_1
- R_2E_INTERRUPT_MASK_2
- R_2F_INTERRUPT_MASK_3
- R_30_AUD_MAST_CLK_CYCLES_PER_FIELD
- R_32_47
- R_34_AUD_MAST_CLK_NOMINAL_INC
- R_386_32
- R_386_COPY
- R_386_GLOB_DAT
- R_386_GOT32
- R_386_GOTOFF
- R_386_GOTPC
- R_386_JMP_SLOT
- R_386_NONE
- R_386_NUM
- R_386_PC32
- R_386_PLT32
- R_386_RELATIVE
- R_38_CLK_RATIO_AMXCLK_TO_ASCLK
- R_390_12
- R_390_16
- R_390_20
- R_390_32
- R_390_64
- R_390_8
- R_390_COPY
- R_390_GLOB_DAT
- R_390_GOT12
- R_390_GOT16
- R_390_GOT20
- R_390_GOT32
- R_390_GOT64
- R_390_GOTENT
- R_390_GOTOFF16
- R_390_GOTOFF32
- R_390_GOTOFF64
- R_390_GOTPC
- R_390_GOTPCDBL
- R_390_GOTPLT12
- R_390_GOTPLT16
- R_390_GOTPLT20
- R_390_GOTPLT32
- R_390_GOTPLT64
- R_390_GOTPLTENT
- R_390_JMP_SLOT
- R_390_NONE
- R_390_NUM
- R_390_PC16
- R_390_PC16DBL
- R_390_PC32
- R_390_PC32DBL
- R_390_PC64
- R_390_PLT16DBL
- R_390_PLT32
- R_390_PLT32DBL
- R_390_PLT64
- R_390_PLTOFF16
- R_390_PLTOFF32
- R_390_PLTOFF64
- R_390_RELATIVE
- R_390_TLS_DTPMOD
- R_390_TLS_DTPOFF
- R_390_TLS_GD32
- R_390_TLS_GD64
- R_390_TLS_GDCALL
- R_390_TLS_GOTIE12
- R_390_TLS_GOTIE20
- R_390_TLS_GOTIE32
- R_390_TLS_GOTIE64
- R_390_TLS_IE32
- R_390_TLS_IE64
- R_390_TLS_IEENT
- R_390_TLS_LDCALL
- R_390_TLS_LDM32
- R_390_TLS_LDM64
- R_390_TLS_LDO32
- R_390_TLS_LDO64
- R_390_TLS_LE32
- R_390_TLS_LE64
- R_390_TLS_LOAD
- R_390_TLS_TPOFF
- R_39_CLK_RATIO_ASCLK_TO_ALRCLK
- R_3A_AUD_CLK_GEN_BASIC_SETUP
- R_40_59
- R_40_SLICER_CNTL_1
- R_41_LCR_BASE
- R_48_63
- R_58_PROGRAM_FRAMING_CODE
- R_59_H_OFF_FOR_SLICER
- R_5A_V_OFF_FOR_SLICER
- R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF
- R_5D_DID
- R_5E_SDID
- R_60_79
- R_60_SLICER_STATUS_BYTE_0
- R_61_SLICER_STATUS_BYTE_1
- R_62_SLICER_STATUS_BYTE_2
- R_68K_16
- R_68K_32
- R_68K_8
- R_68K_COPY
- R_68K_GLOB_DAT
- R_68K_GOT16
- R_68K_GOT16O
- R_68K_GOT32
- R_68K_GOT32O
- R_68K_GOT8
- R_68K_GOT8O
- R_68K_JMP_SLOT
- R_68K_NONE
- R_68K_PC16
- R_68K_PC32
- R_68K_PC8
- R_68K_PLT16
- R_68K_PLT16O
- R_68K_PLT32
- R_68K_PLT32O
- R_68K_PLT8
- R_68K_PLT8O
- R_68K_RELATIVE
- R_8
- R_80_GLOBAL_CNTL_1
- R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F
- R_83_X_PORT_I_O_ENA_AND_OUT_CLK
- R_84_I_PORT_SIGNAL_DEF
- R_85_I_PORT_SIGNAL_POLAR
- R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT
- R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED
- R_88_POWER_SAVE_ADC_PORT_CNTL
- R_8F_STATUS_INFO_SCALER
- R_90_A_TASK_HANDLING_CNTL
- R_91_A_X_PORT_FORMATS_AND_CONF
- R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL
- R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF
- R_94_A_HORIZ_INPUT_WINDOW_START
- R_95_A_HORIZ_INPUT_WINDOW_START_MSB
- R_96_A_HORIZ_INPUT_WINDOW_LENGTH
- R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB
- R_98_A_VERT_INPUT_WINDOW_START
- R_99_A_VERT_INPUT_WINDOW_START_MSB
- R_9A_A_VERT_INPUT_WINDOW_LENGTH
- R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB
- R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH
- R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB
- R_9E_A_VERT_OUTPUT_WINDOW_LENGTH
- R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB
- R_A
- R_A0_A_HORIZ_PRESCALING
- R_A1_A_ACCUMULATION_LENGTH
- R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER
- R_A4_A_LUMA_BRIGHTNESS_CNTL
- R_A5_A_LUMA_CONTRAST_CNTL
- R_A6_A_CHROMA_SATURATION_CNTL
- R_A8_A_HORIZ_LUMA_SCALING_INC
- R_A9_A_HORIZ_LUMA_SCALING_INC_MSB
- R_AARCH64_ABS16
- R_AARCH64_ABS32
- R_AARCH64_ABS64
- R_AARCH64_ADD_ABS_LO12_NC
- R_AARCH64_ADR_PREL_LO21
- R_AARCH64_ADR_PREL_PG_HI21
- R_AARCH64_ADR_PREL_PG_HI21_NC
- R_AARCH64_CALL26
- R_AARCH64_CONDBR19
- R_AARCH64_JUMP26
- R_AARCH64_LDST128_ABS_LO12_NC
- R_AARCH64_LDST16_ABS_LO12_NC
- R_AARCH64_LDST32_ABS_LO12_NC
- R_AARCH64_LDST64_ABS_LO12_NC
- R_AARCH64_LDST8_ABS_LO12_NC
- R_AARCH64_LD_PREL_LO19
- R_AARCH64_MOVW_PREL_G0
- R_AARCH64_MOVW_PREL_G0_NC
- R_AARCH64_MOVW_PREL_G1
- R_AARCH64_MOVW_PREL_G1_NC
- R_AARCH64_MOVW_PREL_G2
- R_AARCH64_MOVW_PREL_G2_NC
- R_AARCH64_MOVW_PREL_G3
- R_AARCH64_MOVW_SABS_G0
- R_AARCH64_MOVW_SABS_G1
- R_AARCH64_MOVW_SABS_G2
- R_AARCH64_MOVW_UABS_G0
- R_AARCH64_MOVW_UABS_G0_NC
- R_AARCH64_MOVW_UABS_G1
- R_AARCH64_MOVW_UABS_G1_NC
- R_AARCH64_MOVW_UABS_G2
- R_AARCH64_MOVW_UABS_G2_NC
- R_AARCH64_MOVW_UABS_G3
- R_AARCH64_NONE
- R_AARCH64_PREL16
- R_AARCH64_PREL32
- R_AARCH64_PREL64
- R_AARCH64_RELATIVE
- R_AARCH64_TSTBR14
- R_AA_A_HORIZ_LUMA_PHASE_OFF
- R_AB
- R_AB_S
- R_AC_A_HORIZ_CHROMA_SCALING_INC
- R_ADCSR
- R_ADCVOLL
- R_ADCVOLR
- R_ADDRH
- R_ADDRL
- R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB
- R_AE_A_HORIZ_CHROMA_PHASE_OFF
- R_AF_A_HORIZ_CHROMA_PHASE_OFF_MSB
- R_AIC1
- R_AIC2
- R_ALCCTL0
- R_ALCCTL1
- R_ALCCTL2
- R_ALCCTL3
- R_ALL
- R_ALPHA_BRADDR
- R_ALPHA_BRSGP
- R_ALPHA_COPY
- R_ALPHA_DTPMOD64
- R_ALPHA_DTPREL16
- R_ALPHA_DTPREL64
- R_ALPHA_DTPRELHI
- R_ALPHA_DTPRELLO
- R_ALPHA_GLOB_DAT
- R_ALPHA_GOTDTPREL
- R_ALPHA_GOTTPREL
- R_ALPHA_GPDISP
- R_ALPHA_GPREL16
- R_ALPHA_GPREL32
- R_ALPHA_GPRELHIGH
- R_ALPHA_GPRELLOW
- R_ALPHA_HINT
- R_ALPHA_JMP_SLOT
- R_ALPHA_LITERAL
- R_ALPHA_LITUSE
- R_ALPHA_NONE
- R_ALPHA_REFLONG
- R_ALPHA_REFQUAD
- R_ALPHA_RELATIVE
- R_ALPHA_SREL16
- R_ALPHA_SREL32
- R_ALPHA_SREL64
- R_ALPHA_TLSGD
- R_ALPHA_TLS_LDM
- R_ALPHA_TPREL16
- R_ALPHA_TPREL64
- R_ALPHA_TPRELHI
- R_ALPHA_TPRELLO
- R_AM
- R_ANTENNA_SELECT_CCK
- R_ANTENNA_SELECT_OFDM
- R_ARC_32
- R_ARC_32_ME
- R_ARC_32_PCREL
- R_ARM_ABS32
- R_ARM_CALL
- R_ARM_JUMP24
- R_ARM_MOVT_ABS
- R_ARM_MOVW_ABS_NC
- R_ARM_NONE
- R_ARM_PC24
- R_ARM_PREL31
- R_ARM_TARGET1
- R_ARM_THM_CALL
- R_ARM_THM_JUMP19
- R_ARM_THM_JUMP24
- R_ARM_THM_MOVT_ABS
- R_ARM_THM_MOVW_ABS_NC
- R_ARM_V4BX
- R_ASRC
- R_ASRCILVOL
- R_ASRCIRVOL
- R_ASRCOLVOL
- R_ASRCORVOL
- R_AUDIOMUX1
- R_AUDIOMUX2
- R_AUDIOMUX3
- R_AUD_DAC_MONO_SEL_MASK
- R_AUD_DAC_MONO_SEL_MASK_SFT
- R_AUD_DAC_MONO_SEL_SFT
- R_AUD_DAC_NEG_LARGE_MONO_MASK
- R_AUD_DAC_NEG_LARGE_MONO_MASK_SFT
- R_AUD_DAC_NEG_LARGE_MONO_SFT
- R_AUD_DAC_NEG_SMALL_MONO_MASK
- R_AUD_DAC_NEG_SMALL_MONO_MASK_SFT
- R_AUD_DAC_NEG_SMALL_MONO_SFT
- R_AUD_DAC_NEG_TINY_MONO_MASK
- R_AUD_DAC_NEG_TINY_MONO_MASK_SFT
- R_AUD_DAC_NEG_TINY_MONO_SFT
- R_AUD_DAC_POS_LARGE_MONO_MASK
- R_AUD_DAC_POS_LARGE_MONO_MASK_SFT
- R_AUD_DAC_POS_LARGE_MONO_SFT
- R_AUD_DAC_POS_SMALL_MONO_MASK
- R_AUD_DAC_POS_SMALL_MONO_MASK_SFT
- R_AUD_DAC_POS_SMALL_MONO_SFT
- R_AUD_DAC_POS_TINY_MONO_MASK
- R_AUD_DAC_POS_TINY_MONO_MASK_SFT
- R_AUD_DAC_POS_TINY_MONO_SFT
- R_AUD_DAC_SW_RSTB_MASK
- R_AUD_DAC_SW_RSTB_MASK_SFT
- R_AUD_DAC_SW_RSTB_SFT
- R_AUD_SDM_MUTE_L_MASK
- R_AUD_SDM_MUTE_L_MASK_SFT
- R_AUD_SDM_MUTE_L_SFT
- R_AUD_SDM_MUTE_R_MASK
- R_AUD_SDM_MUTE_R_MASK_SFT
- R_AUD_SDM_MUTE_R_SFT
- R_B0_A_VERT_LUMA_SCALING_INC
- R_B1_A_VERT_LUMA_SCALING_INC_MSB
- R_B2_A_VERT_CHROMA_SCALING_INC
- R_B3_A_VERT_CHROMA_SCALING_INC_MSB
- R_B4_A_VERT_SCALING_MODE_CNTL
- R_B8_A_VERT_CHROMA_PHASE_OFF_00
- R_B9_A_VERT_CHROMA_PHASE_OFF_01
- R_BAUDH
- R_BAUDL
- R_BA_A_VERT_CHROMA_PHASE_OFF_10
- R_BB_A_VERT_CHROMA_PHASE_OFF_11
- R_BC
- R_BCM1480_DUART_IMRREG
- R_BCM1480_DUART_INCHREG
- R_BCM1480_DUART_ISRREG
- R_BCM1480_GPIO_INT_ADD_TYPE
- R_BCM1480_HR_CFG
- R_BCM1480_HR_EX_LEAF0
- R_BCM1480_HR_HA_LEAF0
- R_BCM1480_HR_MAPPING
- R_BCM1480_HR_PATH
- R_BCM1480_HR_PATH_DEFAULT
- R_BCM1480_HR_RT_WORD
- R_BCM1480_HR_RULE_OP
- R_BCM1480_HR_RULE_TYPE
- R_BCM1480_HSP_RX_CALIBRATION
- R_BCM1480_HSP_RX_DIAG_CRC_0
- R_BCM1480_HSP_RX_DIAG_CRC_1
- R_BCM1480_HSP_RX_DIAG_DETAILS
- R_BCM1480_HSP_RX_DIAG_HTCMD
- R_BCM1480_HSP_RX_DIAG_PKTCTL
- R_BCM1480_HSP_RX_HT_RAMALLOC_0
- R_BCM1480_HSP_RX_HT_RAMALLOC_1
- R_BCM1480_HSP_RX_HT_RAMALLOC_2
- R_BCM1480_HSP_RX_HT_RAMALLOC_3
- R_BCM1480_HSP_RX_HT_RAMALLOC_4
- R_BCM1480_HSP_RX_HT_RAMALLOC_5
- R_BCM1480_HSP_RX_PKT_RAMALLOC
- R_BCM1480_HSP_RX_PKT_RAMALLOC_0
- R_BCM1480_HSP_RX_PKT_RAMALLOC_1
- R_BCM1480_HSP_RX_PKT_RAMALLOC_2
- R_BCM1480_HSP_RX_PKT_RAMALLOC_3
- R_BCM1480_HSP_RX_PKT_RAMALLOC_4
- R_BCM1480_HSP_RX_PKT_RAMALLOC_5
- R_BCM1480_HSP_RX_PKT_RAMALLOC_6
- R_BCM1480_HSP_RX_PKT_RAMALLOC_7
- R_BCM1480_HSP_RX_PLL_CNFG
- R_BCM1480_HSP_RX_RAM_READCTL
- R_BCM1480_HSP_RX_RAM_READWINDOW
- R_BCM1480_HSP_RX_RF_READCTL
- R_BCM1480_HSP_RX_RF_READWINDOW
- R_BCM1480_HSP_RX_SPI4_CALENDAR_0
- R_BCM1480_HSP_RX_SPI4_CALENDAR_1
- R_BCM1480_HSP_RX_SPI4_CFG_0
- R_BCM1480_HSP_RX_SPI4_CFG_1
- R_BCM1480_HSP_RX_SPI4_DESKEW_DATAPATH
- R_BCM1480_HSP_RX_SPI4_DESKEW_OVERRIDE
- R_BCM1480_HSP_RX_SPI4_PORT_INT_EN
- R_BCM1480_HSP_RX_SPI4_PORT_INT_STATUS
- R_BCM1480_HSP_RX_SPI_WATERMARK
- R_BCM1480_HSP_RX_SPI_WATERMARK_0
- R_BCM1480_HSP_RX_SPI_WATERMARK_1
- R_BCM1480_HSP_RX_SPI_WATERMARK_2
- R_BCM1480_HSP_RX_SPI_WATERMARK_3
- R_BCM1480_HSP_RX_SPI_WATERMARK_4
- R_BCM1480_HSP_RX_SPI_WATERMARK_5
- R_BCM1480_HSP_RX_SPI_WATERMARK_6
- R_BCM1480_HSP_RX_SPI_WATERMARK_7
- R_BCM1480_HSP_RX_TEST
- R_BCM1480_HSP_RX_VIS_CMDQ_0
- R_BCM1480_HSP_RX_VIS_CMDQ_1
- R_BCM1480_HSP_RX_VIS_CMDQ_2
- R_BCM1480_HSP_RX_VIS_FLCTRL_COUNTER
- R_BCM1480_HSP_TX_CALIBRATION
- R_BCM1480_HSP_TX_HTCC_RAMALLOC_0
- R_BCM1480_HSP_TX_HTCC_RAMALLOC_1
- R_BCM1480_HSP_TX_HTCC_RAMALLOC_2
- R_BCM1480_HSP_TX_HTCC_RXPHITCNT
- R_BCM1480_HSP_TX_HTCC_TXPHITCNT
- R_BCM1480_HSP_TX_HTIO_RXPHITCNT
- R_BCM1480_HSP_TX_HTIO_TXPHITCNT
- R_BCM1480_HSP_TX_NEXT_ADDR_BASE
- R_BCM1480_HSP_TX_NEXT_ADDR_REGISTER
- R_BCM1480_HSP_TX_NPC_RAMALLOC
- R_BCM1480_HSP_TX_PC_RAMALLOC
- R_BCM1480_HSP_TX_PKT_RAMALLOC
- R_BCM1480_HSP_TX_PKT_RAMALLOC_0
- R_BCM1480_HSP_TX_PKT_RAMALLOC_1
- R_BCM1480_HSP_TX_PKT_RAMALLOC_2
- R_BCM1480_HSP_TX_PKT_RAMALLOC_3
- R_BCM1480_HSP_TX_PKT_RAMALLOC_4
- R_BCM1480_HSP_TX_PKT_RAMALLOC_5
- R_BCM1480_HSP_TX_PKT_RAMALLOC_6
- R_BCM1480_HSP_TX_PKT_RAMALLOC_7
- R_BCM1480_HSP_TX_PKT_RXPHITCNT
- R_BCM1480_HSP_TX_PKT_RXPHITCNT_0
- R_BCM1480_HSP_TX_PKT_RXPHITCNT_1
- R_BCM1480_HSP_TX_PKT_RXPHITCNT_2
- R_BCM1480_HSP_TX_PKT_RXPHITCNT_3
- R_BCM1480_HSP_TX_PKT_TXPHITCNT
- R_BCM1480_HSP_TX_PKT_TXPHITCNT_0
- R_BCM1480_HSP_TX_PKT_TXPHITCNT_1
- R_BCM1480_HSP_TX_PKT_TXPHITCNT_2
- R_BCM1480_HSP_TX_PKT_TXPHITCNT_3
- R_BCM1480_HSP_TX_PLL_CNFG
- R_BCM1480_HSP_TX_RAM_READCTL
- R_BCM1480_HSP_TX_RAM_READWINDOW
- R_BCM1480_HSP_TX_RF_READCTL
- R_BCM1480_HSP_TX_RF_READWINDOW
- R_BCM1480_HSP_TX_RSP_RAMALLOC
- R_BCM1480_HSP_TX_SPI4_CALENDAR_0
- R_BCM1480_HSP_TX_SPI4_CALENDAR_1
- R_BCM1480_HSP_TX_SPI4_CFG_0
- R_BCM1480_HSP_TX_SPI4_CFG_1
- R_BCM1480_HSP_TX_SPI4_PORT_INT_EN
- R_BCM1480_HSP_TX_SPI4_PORT_INT_STATUS
- R_BCM1480_HSP_TX_SPI4_TRAINING_FMT
- R_BCM1480_HSP_TX_TEST
- R_BCM1480_HSP_TX_VIS_CMDQ_0
- R_BCM1480_HSP_TX_VIS_CMDQ_1
- R_BCM1480_HSP_TX_VIS_CMDQ_2
- R_BCM1480_IMR_ALIAS_MAILBOX_0
- R_BCM1480_IMR_ALIAS_MAILBOX_0_SET
- R_BCM1480_IMR_INTERRUPT_DIAG_H
- R_BCM1480_IMR_INTERRUPT_DIAG_L
- R_BCM1480_IMR_INTERRUPT_MAP_BASE_H
- R_BCM1480_IMR_INTERRUPT_MAP_BASE_L
- R_BCM1480_IMR_INTERRUPT_MASK_H
- R_BCM1480_IMR_INTERRUPT_MASK_L
- R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_H
- R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_L
- R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H
- R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L
- R_BCM1480_IMR_INTERRUPT_TRACE_H
- R_BCM1480_IMR_INTERRUPT_TRACE_L
- R_BCM1480_IMR_LDT_INTERRUPT_CLR_H
- R_BCM1480_IMR_LDT_INTERRUPT_CLR_L
- R_BCM1480_IMR_LDT_INTERRUPT_H
- R_BCM1480_IMR_LDT_INTERRUPT_L
- R_BCM1480_IMR_LDT_INTERRUPT_SET
- R_BCM1480_IMR_MAILBOX_0_CLR_CPU
- R_BCM1480_IMR_MAILBOX_0_CPU
- R_BCM1480_IMR_MAILBOX_0_SET_CPU
- R_BCM1480_IMR_MAILBOX_1_CLR_CPU
- R_BCM1480_IMR_MAILBOX_1_CPU
- R_BCM1480_IMR_MAILBOX_1_SET_CPU
- R_BCM1480_IMR_MAILBOX_CLR
- R_BCM1480_IMR_MAILBOX_CPU
- R_BCM1480_IMR_MAILBOX_NUM_SPACING
- R_BCM1480_IMR_MAILBOX_SET
- R_BCM1480_MAC_DMA_OODPKTLOST
- R_BCM1480_MC_CLOCK_CFG
- R_BCM1480_MC_CONFIG
- R_BCM1480_MC_CS01_BA
- R_BCM1480_MC_CS01_COL0
- R_BCM1480_MC_CS01_COL1
- R_BCM1480_MC_CS01_ROW0
- R_BCM1480_MC_CS01_ROW1
- R_BCM1480_MC_CS23_BA
- R_BCM1480_MC_CS23_COL0
- R_BCM1480_MC_CS23_COL1
- R_BCM1480_MC_CS23_ROW0
- R_BCM1480_MC_CS23_ROW1
- R_BCM1480_MC_CSX_BASE
- R_BCM1480_MC_CSX_COL0
- R_BCM1480_MC_CSX_COL1
- R_BCM1480_MC_CSX_ROW0
- R_BCM1480_MC_CSX_ROW1
- R_BCM1480_MC_CS_END
- R_BCM1480_MC_CS_START
- R_BCM1480_MC_DLL_CFG
- R_BCM1480_MC_DRAMCMD
- R_BCM1480_MC_DRAMMODE
- R_BCM1480_MC_DRIVE_CFG
- R_BCM1480_MC_ECC_STATUS
- R_BCM1480_MC_MCLK_CFG
- R_BCM1480_MC_ODT
- R_BCM1480_MC_TEST_DATA
- R_BCM1480_MC_TEST_ECC
- R_BCM1480_MC_TIMING1
- R_BCM1480_MC_TIMING2
- R_BCM1480_PM_BASE_SIZE
- R_BCM1480_PM_CACHEABILITY
- R_BCM1480_PM_CNT
- R_BCM1480_PM_CONFIG0
- R_BCM1480_PM_DESC_MERGE_TIMER
- R_BCM1480_PM_INT_CLR
- R_BCM1480_PM_INT_CNFG
- R_BCM1480_PM_INT_MSK
- R_BCM1480_PM_INT_ST
- R_BCM1480_PM_INT_WMK
- R_BCM1480_PM_LAST
- R_BCM1480_PM_LOCALDEBUG
- R_BCM1480_PM_LOCALDEBUG_PIB
- R_BCM1480_PM_LOCALDEBUG_POB
- R_BCM1480_PM_MRGD_INT
- R_BCM1480_PM_PFCNT
- R_BCM1480_PM_PFINDX
- R_BCM1480_PM_PMO_MAPPING
- R_BCS
- R_BC_A_VERT_LUMA_PHASE_OFF_00
- R_BD_A_VERT_LUMA_PHASE_OFF_01
- R_BD_MASK
- R_BERT_EC
- R_BERT_ECH
- R_BERT_ECL
- R_BERT_STA
- R_BERT_WD_MD
- R_BE_A_VERT_LUMA_PHASE_OFF_10
- R_BF_A_VERT_LUMA_PHASE_OFF_11
- R_BR
- R_BRG_CTRL
- R_BRG_MD
- R_BRG_PCM_CFG
- R_BRG_TIM0
- R_BRG_TIM1
- R_BRG_TIM2
- R_BRG_TIM3
- R_BRG_TIM_SEL01
- R_BRG_TIM_SEL23
- R_BRG_TIM_SEL45
- R_BRG_TIM_SEL67
- R_BUF_MAXSIZE
- R_BUF_SIZE
- R_BUTCTL
- R_BYPASS
- R_BYPASS_DSP_BYPAS
- R_BYPASS_USE_DSP
- R_BYTEOFFSET0
- R_BYTEOFFSET1
- R_C
- R_C0_B_TASK_HANDLING_CNTL
- R_C1_B_X_PORT_FORMATS_AND_CONF
- R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION
- R_C3_B_I_PORT_FORMATS_AND_CONF
- R_C4_B_HORIZ_INPUT_WINDOW_START
- R_C5_B_HORIZ_INPUT_WINDOW_START_MSB
- R_C6000_ABS16
- R_C6000_ABS32
- R_C6000_ABS8
- R_C6000_ABS_H16
- R_C6000_ABS_L16
- R_C6000_ABS_S16
- R_C6000_ALIGN
- R_C6000_COPY
- R_C6000_DSBT_INDEX
- R_C6000_FPHEAD
- R_C6000_NOCMP
- R_C6000_NONE
- R_C6000_PCR_S10
- R_C6000_PCR_S12
- R_C6000_PCR_S21
- R_C6000_PCR_S7
- R_C6000_PREL31
- R_C6000_SBR_GOT_H16_W
- R_C6000_SBR_GOT_L16_W
- R_C6000_SBR_GOT_U15_W
- R_C6000_SBR_H16_B
- R_C6000_SBR_H16_H
- R_C6000_SBR_H16_W
- R_C6000_SBR_L16_B
- R_C6000_SBR_L16_H
- R_C6000_SBR_L16_W
- R_C6000_SBR_S16
- R_C6000_SBR_U15_B
- R_C6000_SBR_U15_H
- R_C6000_SBR_U15_W
- R_C6_B_HORIZ_INPUT_WINDOW_LENGTH
- R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB
- R_C8_B_VERT_INPUT_WINDOW_START
- R_C9_B_VERT_INPUT_WINDOW_START_MSB
- R_CALC_W
- R_CAM4X128KEY
- R_CAM4X128TABLE
- R_CATKTCH
- R_CATKTCL
- R_CA_B_VERT_INPUT_WINDOW_LENGTH
- R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB
- R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH
- R_CC_CPU0_0
- R_CC_CPU1_0
- R_CC_CPU2_0
- R_CC_CPU3_0
- R_CC_CPU4_0
- R_CC_CPU5_0
- R_CC_CPU6_0
- R_CC_CPU7_0
- R_CD
- R_CD1
- R_CD2
- R_CD3
- R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB
- R_CD_S
- R_CE_B_VERT_OUTPUT_WINDOW_LENGTH
- R_CFG_BOOT
- R_CFG_P1_TRANSITION
- R_CFG_P2_TRANSITION
- R_CFG_P3_TRANSITION
- R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB
- R_CH0AIC
- R_CH1AIC
- R_CH2AIC
- R_CH3AIC
- R_CHIP_ID
- R_CHIP_RV
- R_CIRM
- R_CIS
- R_CL
- R_CLASS0_SPILL_MEM_SIZE
- R_CLASS0_SPILL_MEM_START_0
- R_CLASS0_SPILL_MEM_START_1
- R_CLASS1_SPILL_MEM_SIZE
- R_CLASS1_SPILL_MEM_START_0
- R_CLASS1_SPILL_MEM_START_1
- R_CLASS2_SPILL_MEM_SIZE
- R_CLASS2_SPILL_MEM_START_0
- R_CLASS2_SPILL_MEM_START_1
- R_CLASS3_SPILL_MEM_SIZE
- R_CLASS3_SPILL_MEM_START_0
- R_CLASS3_SPILL_MEM_START_1
- R_CLASSWATERMARKS
- R_CLECTL
- R_CM
- R_CMPRAT
- R_CMR
- R_CM_S
- R_CNVRTR0
- R_CNVRTR1
- R_COMPOSE
- R_COMPTH
- R_CONFIG0
- R_CONFIG1
- R_CONF_EN
- R_CONF_OFLOW
- R_COP0
- R_COP1
- R_COPSTAT
- R_CORECONTROL
- R_CPD
- R_CPUCFG_CLUSTER_PO_RST_CTRL
- R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE
- R_CPUCFG_CPU_SOFT_ENTRY_REG
- R_CR
- R_CRC_DEF_0
- R_CRC_EC
- R_CRC_ECH
- R_CRC_ECL
- R_CRELTCH
- R_CRELTCL
- R_CROP_SINK
- R_CROP_SOURCE
- R_CR_S
- R_CSKY_32
- R_CSKY_ADDR_HI16
- R_CSKY_ADDR_LO16
- R_CSKY_COPY
- R_CSKY_GLOB_DAT
- R_CSKY_GNU_VTENTRY
- R_CSKY_GNU_VTINHERIT
- R_CSKY_JUMP_SLOT
- R_CSKY_NONE
- R_CSKY_PC32
- R_CSKY_PCIMM11BY2
- R_CSKY_PCIMM4BY2
- R_CSKY_PCIMM8BY4
- R_CSKY_PCRELJSR_IMM11BY2
- R_CSKY_PCRELJSR_IMM26BY2
- R_CSKY_RELATIVE
- R_CTCP_DEF_0
- R_CTL
- R_CTL_BASIC_LINK_SERV
- R_CTL_B_ACC
- R_CTL_B_RJT
- R_CTRL
- R_D0_B_HORIZ_PRESCALING
- R_D1_B_ACCUMULATION_LENGTH
- R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER
- R_D4_B_LUMA_BRIGHTNESS_CNTL
- R_D5_B_LUMA_CONTRAST_CNTL
- R_D6_B_CHROMA_SATURATION_CNTL
- R_D8_B_HORIZ_LUMA_SCALING_INC
- R_D9_B_HORIZ_LUMA_SCALING_INC_MSB
- R_DACCLECTL
- R_DACCLEMUG
- R_DACCOMPATKH
- R_DACCOMPATKL
- R_DACCOMPRAT
- R_DACCOMPRELH
- R_DACCOMPRELL
- R_DACCOMPTHR
- R_DACCRADD
- R_DACCRADDR
- R_DACCRRDH
- R_DACCRRDL
- R_DACCRRDM
- R_DACCRS
- R_DACCRSTAT
- R_DACCRWDH
- R_DACCRWDL
- R_DACCRWDM
- R_DACCRWRH
- R_DACCRWRL
- R_DACCRWRM
- R_DACCTL
- R_DACEQFILT
- R_DACEXPATKH
- R_DACEXPATKL
- R_DACEXPRAT
- R_DACEXPRELH
- R_DACEXPRELL
- R_DACEXPTHR
- R_DACFXCTL
- R_DACLIMATKH
- R_DACLIMATKL
- R_DACLIMRELH
- R_DACLIMRELL
- R_DACLIMTGT
- R_DACLIMTHR
- R_DACMBCATK1H
- R_DACMBCATK1L
- R_DACMBCATK2H
- R_DACMBCATK2L
- R_DACMBCATK3H
- R_DACMBCATK3L
- R_DACMBCCTL
- R_DACMBCEN
- R_DACMBCMUG1
- R_DACMBCMUG2
- R_DACMBCMUG3
- R_DACMBCRAT1
- R_DACMBCRAT2
- R_DACMBCRAT3
- R_DACMBCREL1H
- R_DACMBCREL1L
- R_DACMBCREL2H
- R_DACMBCREL2L
- R_DACMBCREL3H
- R_DACMBCREL3L
- R_DACMBCTHR1
- R_DACMBCTHR2
- R_DACMBCTHR3
- R_DACSR
- R_DACVOLL
- R_DACVOLR
- R_DATA
- R_DA_B_HORIZ_LUMA_PHASE_OFF
- R_DCB_XMAP9_PROTOCOL
- R_DCCTL
- R_DCOFSEL
- R_DC_B_HORIZ_CHROMA_SCALING
- R_DD_B_HORIZ_CHROMA_SCALING_MSB
- R_DE
- R_DESC_PACK_CTRL
- R_DEVADD0
- R_DEVID
- R_DEVIDH
- R_DEVIDL
- R_DEVREV
- R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA
- R_DIS
- R_DIS_PRST_0
- R_DIS_PRST_1
- R_DIV
- R_DMACR0
- R_DMACR1
- R_DMACR2
- R_DMACR3
- R_DMA_DSCRB_ADDR
- R_DMICCTL
- R_DM_CUR_DSCR_ADDR
- R_DM_DSCR_BASE
- R_DM_DSCR_BASE_DEBUG
- R_DM_DSCR_COUNT
- R_DTMF
- R_DTMF_N
- R_DUART_AUXCTL_X
- R_DUART_AUX_CTRL
- R_DUART_CLEAR_OPR
- R_DUART_CLK_SEL
- R_DUART_CMD
- R_DUART_FULL_CTL
- R_DUART_IMRREG
- R_DUART_IMR_A
- R_DUART_IMR_B
- R_DUART_INCHREG
- R_DUART_IN_CHNG_A
- R_DUART_IN_CHNG_B
- R_DUART_IN_PORT
- R_DUART_ISRREG
- R_DUART_ISR_A
- R_DUART_ISR_B
- R_DUART_MODE_REG_1
- R_DUART_MODE_REG_2
- R_DUART_NUM_PORTS
- R_DUART_OPCR
- R_DUART_OPCR_X
- R_DUART_OUT_PORT
- R_DUART_RX_HOLD
- R_DUART_SET_OPR
- R_DUART_STATUS
- R_DUART_TX_HOLD
- R_DVC
- R_DVP_SP
- R_DVP_SP_AUTO_MODE
- R_DVP_SP_DVP_MASK
- R_E
- R_E0_B_VERT_LUMA_SCALING_INC
- R_E1_B_VERT_LUMA_SCALING_INC_MSB
- R_E1_RD_STA
- R_E1_WR_STA
- R_E2_B_VERT_CHROMA_SCALING_INC
- R_E3_B_VERT_CHROMA_SCALING_INC_MSB
- R_E4_B_VERT_SCALING_MODE_CNTL
- R_E8_B_VERT_CHROMA_PHASE_OFF_00
- R_E9_B_VERT_CHROMA_PHASE_OFF_01
- R_EA_B_VERT_CHROMA_PHASE_OFF_10
- R_EB1
- R_EB10
- R_EB11
- R_EB12
- R_EB13
- R_EB14
- R_EB15
- R_EB16
- R_EB17
- R_EB18
- R_EB19
- R_EB2
- R_EB20
- R_EB21
- R_EB22
- R_EB23
- R_EB3
- R_EB4
- R_EB5
- R_EB6
- R_EB7
- R_EB8
- R_EB9
- R_EB_B_VERT_CHROMA_PHASE_OFF_11
- R_EC_B_VERT_LUMA_PHASE_OFF_00
- R_ED_B_VERT_LUMA_PHASE_OFF_01
- R_EE_B_VERT_LUMA_PHASE_OFF_10
- R_EF_B_VERT_LUMA_PHASE_OFF_11
- R_EGRESSFIFOCARVINGSLOTS
- R_ENABLE
- R_EP1
- R_EP2
- R_EP3
- R_EP4
- R_EP5
- R_ERR
- R_ERROR
- R_ERRORS_FATAL
- R_ERRORS_REPORT
- R_EXPRAT
- R_EXPTH
- R_E_EC
- R_E_ECH
- R_E_ECL
- R_E_S
- R_F
- R_F0_CNTH
- R_F0_CNTL
- R_F0_LFCO_PER_LINE
- R_F1_P_I_PARAM_SELECT
- R_F2_NOMINAL_PLL2_DTO
- R_F3_PLL_INCREMENT
- R_F4_PLL2_STATUS
- R_F5_PULSGEN_LINE_LENGTH
- R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG
- R_F7_PULSE_A_POS_MSB
- R_F8_PULSE_B_POS
- R_F9_PULSE_B_POS_MSB
- R_FAS_EC
- R_FAS_ECH
- R_FAS_ECL
- R_FA_PULSE_C_POS
- R_FB_PULSE_C_POS_MSB
- R_FCR
- R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES
- R_FIFO
- R_FIFO_MD
- R_FIRST_FIFO
- R_FR
- R_FREEQCARVE
- R_FREEWATERMARKS
- R_FROUT_SPILL_MEM_SIZE
- R_FROUT_SPILL_MEM_START_0
- R_FROUT_SPILL_MEM_START_1
- R_FSM_IDX
- R_FXCTL
- R_F_S
- R_GAFR
- R_GEDR
- R_GENMO
- R_GFER
- R_GMAC_JFR0_BUCKET_SIZE
- R_GMAC_JFR1_BUCKET_SIZE
- R_GMAC_RFR0_BUCKET_SIZE
- R_GMAC_RFR1_BUCKET_SIZE
- R_GMAC_TX0_BUCKET_SIZE
- R_GMAC_TX1_BUCKET_SIZE
- R_GMAC_TX2_BUCKET_SIZE
- R_GMAC_TX3_BUCKET_SIZE
- R_GPCR
- R_GPDR
- R_GPIOCTL0
- R_GPIOCTL1
- R_GPIO_CLR_EDGE
- R_GPIO_DIRECTION
- R_GPIO_EN0
- R_GPIO_EN1
- R_GPIO_GLITCH
- R_GPIO_IN0
- R_GPIO_IN1
- R_GPIO_INPUT_INVERT
- R_GPIO_INT_ADD_TYPE
- R_GPIO_INT_TYPE
- R_GPIO_OUT0
- R_GPIO_OUT1
- R_GPIO_PIN_CLR
- R_GPIO_PIN_SET
- R_GPIO_READ
- R_GPIO_SEL
- R_GPI_IN0
- R_GPI_IN1
- R_GPI_IN2
- R_GPI_IN3
- R_GPLR
- R_GPSR
- R_GRER
- R_H8_ABS32
- R_H8_ABS32A16
- R_H8_BPOS
- R_H8_DIR16
- R_H8_DIR16A8
- R_H8_DIR16R8
- R_H8_DIR16S
- R_H8_DIR16S_20
- R_H8_DIR16S_24
- R_H8_DIR16S_28
- R_H8_DIR16S_32
- R_H8_DIR16U
- R_H8_DIR24
- R_H8_DIR24A8
- R_H8_DIR24R8
- R_H8_DIR24U
- R_H8_DIR24U_16
- R_H8_DIR24U_20
- R_H8_DIR24_16
- R_H8_DIR24_20
- R_H8_DIR32
- R_H8_DIR32A16
- R_H8_DIR32U
- R_H8_DIR32U_16
- R_H8_DIR32U_20
- R_H8_DIR32U_24
- R_H8_DIR32U_28
- R_H8_DIR32_16
- R_H8_DIR32_24
- R_H8_DIR32_28
- R_H8_DIR8
- R_H8_DIR8U
- R_H8_DIR8Z_16
- R_H8_DIR8Z_20
- R_H8_DIR8Z_24
- R_H8_DIR8Z_28
- R_H8_DIR8Z_32
- R_H8_GOT16O
- R_H8_GOT32O
- R_H8_NONE
- R_H8_PCREL16
- R_H8_PCREL32
- R_H8_PCREL8
- R_HALF_DUPLEX
- R_HASH_TABLE_VECTOR
- R_HEAD
- R_HEXAGON_10_X
- R_HEXAGON_11_X
- R_HEXAGON_12_X
- R_HEXAGON_16
- R_HEXAGON_16_X
- R_HEXAGON_32
- R_HEXAGON_32_6_X
- R_HEXAGON_32_PCREL
- R_HEXAGON_6_X
- R_HEXAGON_7_X
- R_HEXAGON_8
- R_HEXAGON_8_X
- R_HEXAGON_9_X
- R_HEXAGON_B13_PCREL
- R_HEXAGON_B13_PCREL_X
- R_HEXAGON_B15_PCREL
- R_HEXAGON_B15_PCREL_X
- R_HEXAGON_B22_PCREL
- R_HEXAGON_B22_PCREL_X
- R_HEXAGON_B32_PCREL_X
- R_HEXAGON_B7_PCREL
- R_HEXAGON_B7_PCREL_X
- R_HEXAGON_B9_PCREL
- R_HEXAGON_B9_PCREL_X
- R_HEXAGON_COPY
- R_HEXAGON_GLOB_DAT
- R_HEXAGON_GOTOFF_32
- R_HEXAGON_GOTOFF_HI16
- R_HEXAGON_GOTOFF_LO16
- R_HEXAGON_GOT_16
- R_HEXAGON_GOT_32
- R_HEXAGON_GOT_HI16
- R_HEXAGON_GOT_LO16
- R_HEXAGON_GPREL16_0
- R_HEXAGON_GPREL16_1
- R_HEXAGON_GPREL16_2
- R_HEXAGON_GPREL16_3
- R_HEXAGON_HI16
- R_HEXAGON_HL16
- R_HEXAGON_JMP_SLOT
- R_HEXAGON_LO16
- R_HEXAGON_NONE
- R_HEXAGON_PLT_B22_PCREL
- R_HEXAGON_RELATIVE
- R_HFCLKOUT_DEV_GRP
- R_HPSW
- R_HPVOLL
- R_HPVOLR
- R_HSDCTL1
- R_HSDCTL2
- R_HSDDELAY
- R_HSDSTAT
- R_I
- R_I2S1MRATE
- R_I2S2MRATE
- R_I2S3MRATE
- R_I2SCMC
- R_I2SIDCTL
- R_I2SODCTL
- R_I2SP1CTL
- R_I2SP2CTL
- R_I2SP3CTL
- R_I2SPINC0
- R_I2SPINC1
- R_I2SPINC2
- R_IA64_COPY
- R_IA64_DIR32LSB
- R_IA64_DIR32MSB
- R_IA64_DIR64LSB
- R_IA64_DIR64MSB
- R_IA64_DTPMOD64LSB
- R_IA64_DTPMOD64MSB
- R_IA64_DTPREL14
- R_IA64_DTPREL22
- R_IA64_DTPREL32LSB
- R_IA64_DTPREL32MSB
- R_IA64_DTPREL64I
- R_IA64_DTPREL64LSB
- R_IA64_DTPREL64MSB
- R_IA64_FPTR32LSB
- R_IA64_FPTR32MSB
- R_IA64_FPTR64I
- R_IA64_FPTR64LSB
- R_IA64_FPTR64MSB
- R_IA64_GPREL22
- R_IA64_GPREL32LSB
- R_IA64_GPREL32MSB
- R_IA64_GPREL64I
- R_IA64_GPREL64LSB
- R_IA64_GPREL64MSB
- R_IA64_IMM14
- R_IA64_IMM22
- R_IA64_IMM64
- R_IA64_IPLTLSB
- R_IA64_IPLTMSB
- R_IA64_LDXMOV
- R_IA64_LTOFF22
- R_IA64_LTOFF22X
- R_IA64_LTOFF64I
- R_IA64_LTOFF_DTPMOD22
- R_IA64_LTOFF_DTPREL22
- R_IA64_LTOFF_FPTR22
- R_IA64_LTOFF_FPTR32LSB
- R_IA64_LTOFF_FPTR32MSB
- R_IA64_LTOFF_FPTR64I
- R_IA64_LTOFF_FPTR64LSB
- R_IA64_LTOFF_FPTR64MSB
- R_IA64_LTOFF_TPREL22
- R_IA64_LTV32LSB
- R_IA64_LTV32MSB
- R_IA64_LTV64LSB
- R_IA64_LTV64MSB
- R_IA64_NONE
- R_IA64_PCREL21B
- R_IA64_PCREL21BI
- R_IA64_PCREL21F
- R_IA64_PCREL21M
- R_IA64_PCREL22
- R_IA64_PCREL32LSB
- R_IA64_PCREL32MSB
- R_IA64_PCREL60B
- R_IA64_PCREL64I
- R_IA64_PCREL64LSB
- R_IA64_PCREL64MSB
- R_IA64_PLTOFF22
- R_IA64_PLTOFF64I
- R_IA64_PLTOFF64LSB
- R_IA64_PLTOFF64MSB
- R_IA64_REL32LSB
- R_IA64_REL32MSB
- R_IA64_REL64LSB
- R_IA64_REL64MSB
- R_IA64_SECREL32LSB
- R_IA64_SECREL32MSB
- R_IA64_SECREL64LSB
- R_IA64_SECREL64MSB
- R_IA64_SEGREL32LSB
- R_IA64_SEGREL32MSB
- R_IA64_SEGREL64LSB
- R_IA64_SEGREL64MSB
- R_IA64_SUB
- R_IA64_TPREL14
- R_IA64_TPREL22
- R_IA64_TPREL64I
- R_IA64_TPREL64LSB
- R_IA64_TPREL64MSB
- R_ICH0VOL
- R_ICH1VOL
- R_ICH2VOL
- R_ICH3VOL
- R_ICTL0
- R_ICTL1
- R_ID
- R_ID0
- R_ID1
- R_ID2
- R_ID3
- R_IER
- R_IIR
- R_IMR_ALIAS_MAILBOX_CPU
- R_IMR_ALIAS_MAILBOX_SET_CPU
- R_IMR_INTERRUPT_DIAG
- R_IMR_INTERRUPT_LDT
- R_IMR_INTERRUPT_MAP_BASE
- R_IMR_INTERRUPT_MAP_COUNT
- R_IMR_INTERRUPT_MASK
- R_IMR_INTERRUPT_SOURCE_STATUS
- R_IMR_INTERRUPT_STATUS_BASE
- R_IMR_INTERRUPT_STATUS_COUNT
- R_IMR_INTERRUPT_TRACE
- R_IMR_LDT_INTERRUPT
- R_IMR_LDT_INTERRUPT_CLR
- R_IMR_LDT_INTERRUPT_SET
- R_IMR_MAILBOX_CLR_CPU
- R_IMR_MAILBOX_CPU
- R_IMR_MAILBOX_SET_CPU
- R_INC_RES_FIFO
- R_INMODE
- R_INSELL
- R_INSELR
- R_INTERFACE_CONTROL
- R_INTERFACE_STATUS
- R_INTMASK
- R_INTREG
- R_INT_DATA
- R_INVALID
- R_INVOLL
- R_INVOLR
- R_IO_DRIVE
- R_IO_EXT_CFG
- R_IO_EXT_MULT_SIZE
- R_IO_EXT_REG
- R_IO_EXT_START_ADDR
- R_IO_EXT_TIME_CFG0
- R_IO_EXT_TIME_CFG1
- R_IO_INTERRUPT_ADDR0
- R_IO_INTERRUPT_ADDR1
- R_IO_INTERRUPT_DATA0
- R_IO_INTERRUPT_DATA1
- R_IO_INTERRUPT_DATA2
- R_IO_INTERRUPT_DATA3
- R_IO_INTERRUPT_PARITY
- R_IO_INTERRUPT_STATUS
- R_IO_PCMCIA_CFG
- R_IO_PCMCIA_STATUS
- R_IPCH
- R_IPG_IFG
- R_IRQEN
- R_IRQMASK
- R_IRQMSK_MISC
- R_IRQSTAT
- R_IRQ_CTRL
- R_IRQ_FIFO_BL0
- R_IRQ_FIFO_BL1
- R_IRQ_FIFO_BL2
- R_IRQ_FIFO_BL3
- R_IRQ_FIFO_BL4
- R_IRQ_FIFO_BL5
- R_IRQ_FIFO_BL6
- R_IRQ_FIFO_BL7
- R_IRQ_MISC
- R_IRQ_OVIEW
- R_IRQ_STATECH
- R_ISRC
- R_IVC
- R_IVOLCTLU
- R_I_S
- R_JATT_ATT
- R_JATT_DIR
- R_JUMFRIN_SPILL_MEM_SIZE
- R_JUMFRIN_SPILL_MEM_START_0
- R_JUMFRIN_SPILL_MEM_START_1
- R_L
- R_L2ALLOCCTRL
- R_L2TYPE_0
- R_L2TYPE_1
- R_L2TYPE_2
- R_L2TYPE_3
- R_L3CTABLE
- R_L4CTABLE
- R_LAFH
- R_LAFL
- R_LATKTCH
- R_LATKTCL
- R_LDT_TYPE1_ADDSTATUS
- R_LDT_TYPE1_BAR0
- R_LDT_TYPE1_BAR1
- R_LDT_TYPE1_BRCTL
- R_LDT_TYPE1_BUSID
- R_LDT_TYPE1_CAPPTR
- R_LDT_TYPE1_CLASSREV
- R_LDT_TYPE1_CMD
- R_LDT_TYPE1_CMDSTATUS
- R_LDT_TYPE1_DEVHDR
- R_LDT_TYPE1_DEVICEID
- R_LDT_TYPE1_ERRSTATUS
- R_LDT_TYPE1_EXPCRC
- R_LDT_TYPE1_IOLIMIT
- R_LDT_TYPE1_LINKCTRL
- R_LDT_TYPE1_LINKFREQ
- R_LDT_TYPE1_MEMLIMIT
- R_LDT_TYPE1_PREFETCH
- R_LDT_TYPE1_PREF_BASE
- R_LDT_TYPE1_PREF_LIMIT
- R_LDT_TYPE1_RESERVED1
- R_LDT_TYPE1_ROMADDR
- R_LDT_TYPE1_RXCRC
- R_LDT_TYPE1_SECSTATUS
- R_LDT_TYPE1_SRICMD
- R_LDT_TYPE1_SRICTRL
- R_LDT_TYPE1_SRIRXNUM
- R_LDT_TYPE1_SRITXNUM
- R_LDT_TYPE1_TXBUFCNT
- R_LG
- R_LG_S
- R_LIMTGT
- R_LIMTH
- R_LOAD_W
- R_LOS0
- R_LOS1
- R_LRELTCH
- R_LRELTCL
- R_L_S
- R_M
- R_MAC_ADDR0
- R_MAC_ADDR1
- R_MAC_ADDR2
- R_MAC_ADDR3
- R_MAC_ADDR_BASE
- R_MAC_ADDR_MASK2
- R_MAC_ADDR_MASK3
- R_MAC_ADFILTER_CFG
- R_MAC_ADMASK0
- R_MAC_ADMASK1
- R_MAC_CFG
- R_MAC_CHLO0_BASE
- R_MAC_CHUP0_BASE
- R_MAC_CONFIG_1
- R_MAC_CONFIG_2
- R_MAC_DEBUG_STATUS
- R_MAC_DMA_CHANNELS
- R_MAC_DMA_CHANNEL_BASE
- R_MAC_DMA_CONFIG0
- R_MAC_DMA_CONFIG1
- R_MAC_DMA_CUR_DSCRA
- R_MAC_DMA_CUR_DSCRADDR
- R_MAC_DMA_CUR_DSCRB
- R_MAC_DMA_DSCR_BASE
- R_MAC_DMA_DSCR_CNT
- R_MAC_DMA_OODPKTLOST
- R_MAC_DMA_OODPKTLOST_RX
- R_MAC_DMA_REGISTER
- R_MAC_ENABLE
- R_MAC_EOPCNT
- R_MAC_ETHERNET_ADDR
- R_MAC_FIFO_PTRS
- R_MAC_FILTER_CONFIG
- R_MAC_FRAMECFG
- R_MAC_HASH_BASE
- R_MAC_INT_MASK
- R_MAC_MDIO
- R_MAC_PKT_TYPE
- R_MAC_RMON_COLLISIONS
- R_MAC_RMON_EX_COL
- R_MAC_RMON_FCS_ERROR
- R_MAC_RMON_LATE_COL
- R_MAC_RMON_RX_ALIGN_ERROR
- R_MAC_RMON_RX_BAD
- R_MAC_RMON_RX_BCAST
- R_MAC_RMON_RX_BYTES
- R_MAC_RMON_RX_CODE_ERROR
- R_MAC_RMON_RX_FCS_ERROR
- R_MAC_RMON_RX_GOOD
- R_MAC_RMON_RX_LENGTH_ERROR
- R_MAC_RMON_RX_MCAST
- R_MAC_RMON_RX_OVERSIZE
- R_MAC_RMON_RX_RUNT
- R_MAC_RMON_TX_ABORT
- R_MAC_RMON_TX_BAD
- R_MAC_RMON_TX_BYTES
- R_MAC_RMON_TX_GOOD
- R_MAC_RMON_TX_OVERSIZE
- R_MAC_RMON_TX_RUNT
- R_MAC_STATUS
- R_MAC_STATUS1
- R_MAC_THRSH_CFG
- R_MAC_TXD_CTL
- R_MAC_VLANTAG
- R_MASK
- R_MAX
- R_MAXIMUM_FRAME_LENGTH
- R_MC
- R_MCLK2PINC
- R_MC_CONFIG
- R_MC_CS0_BA
- R_MC_CS0_COL
- R_MC_CS0_ROW
- R_MC_CS1_BA
- R_MC_CS1_COL
- R_MC_CS1_ROW
- R_MC_CS2_BA
- R_MC_CS2_COL
- R_MC_CS2_ROW
- R_MC_CS3_BA
- R_MC_CS3_COL
- R_MC_CS3_ROW
- R_MC_CSX_BA
- R_MC_CSX_BASE
- R_MC_CSX_COL
- R_MC_CSX_ROW
- R_MC_CS_ATTR
- R_MC_CS_END
- R_MC_CS_INTERLEAVE
- R_MC_CS_START
- R_MC_DRAMCMD
- R_MC_DRAMMODE
- R_MC_MCLK_CFG
- R_MC_TEST_DATA
- R_MC_TEST_ECC
- R_MC_TIMING1
- R_MC_TIMING2
- R_MD1
- R_MD2
- R_MD3
- R_MDIO
- R_MEMORY_ADDRESS
- R_MEMORY_DATA
- R_MICBIAS
- R_MICROBLAZE_32
- R_MICROBLAZE_32_LO
- R_MICROBLAZE_32_PCREL
- R_MICROBLAZE_32_PCREL_LO
- R_MICROBLAZE_32_SYM_OP_SYM
- R_MICROBLAZE_64
- R_MICROBLAZE_64_NONE
- R_MICROBLAZE_64_PCREL
- R_MICROBLAZE_NONE
- R_MICROBLAZE_NUM
- R_MICROBLAZE_SRO32
- R_MICROBLAZE_SRW32
- R_MII_MGMT_ADDRESS
- R_MII_MGMT_COMMAND
- R_MII_MGMT_CONFIG
- R_MII_MGMT_INDICATORS
- R_MII_MGMT_STATUS
- R_MII_MGMT_WRITE_DATA
- R_MIPS_16
- R_MIPS_26
- R_MIPS_32
- R_MIPS_64
- R_MIPS_CALL16
- R_MIPS_CALLHI16
- R_MIPS_CALLLO16
- R_MIPS_DELETE
- R_MIPS_GOT16
- R_MIPS_GOTHI16
- R_MIPS_GOTLO16
- R_MIPS_GOT_DISP
- R_MIPS_GOT_OFST
- R_MIPS_GOT_PAGE
- R_MIPS_GPREL16
- R_MIPS_GPREL32
- R_MIPS_HI16
- R_MIPS_HIGHER
- R_MIPS_HIGHEST
- R_MIPS_HIVENDOR
- R_MIPS_INSERT_A
- R_MIPS_INSERT_B
- R_MIPS_LITERAL
- R_MIPS_LO16
- R_MIPS_LOVENDOR
- R_MIPS_NONE
- R_MIPS_PC16
- R_MIPS_PC21_S2
- R_MIPS_PC26_S2
- R_MIPS_REL32
- R_MIPS_SHIFT5
- R_MIPS_SHIFT6
- R_MIPS_SUB
- R_MIPS_UNUSED1
- R_MIPS_UNUSED2
- R_MIPS_UNUSED3
- R_MISS
- R_MPD
- R_MSG_TX_THRESHOLD
- R_MUGAIN
- R_MUTEC
- R_MVOLL
- R_MVOLR
- R_NDS32_15_FIXED_RELA
- R_NDS32_15_PCREL_RELA
- R_NDS32_16_RELA
- R_NDS32_17_FIXED_RELA
- R_NDS32_17_PCREL_RELA
- R_NDS32_25_FIXED_RELA
- R_NDS32_25_PCREL_RELA
- R_NDS32_25_PLTREL
- R_NDS32_32_RELA
- R_NDS32_9_FIXED_RELA
- R_NDS32_9_PCREL_RELA
- R_NDS32_COPY
- R_NDS32_DWARF2_LEB_RELA
- R_NDS32_DWARF2_OP1_RELA
- R_NDS32_DWARF2_OP2_RELA
- R_NDS32_GLOB_DAT
- R_NDS32_GOT20
- R_NDS32_GOTOFF
- R_NDS32_GOTOFF_HI20
- R_NDS32_GOTOFF_LO12
- R_NDS32_GOTPC20
- R_NDS32_GOTPC_HI20
- R_NDS32_GOTPC_LO12
- R_NDS32_GOT_HI20
- R_NDS32_GOT_LO12
- R_NDS32_HI20_RELA
- R_NDS32_INSN16
- R_NDS32_JMP_SLOT
- R_NDS32_LABEL
- R_NDS32_LO12S0_ORI_RELA
- R_NDS32_LO12S0_RELA
- R_NDS32_LO12S1_RELA
- R_NDS32_LO12S2_RELA
- R_NDS32_LO12S3_RELA
- R_NDS32_LOADSTORE
- R_NDS32_LONGCALL1
- R_NDS32_LONGCALL2
- R_NDS32_LONGCALL3
- R_NDS32_LONGCALL4
- R_NDS32_LONGJUMP1
- R_NDS32_LONGJUMP2
- R_NDS32_LONGJUMP3
- R_NDS32_NONE
- R_NDS32_PLTREL_HI20
- R_NDS32_PLTREL_LO12
- R_NDS32_PLT_GOTREL_HI20
- R_NDS32_PLT_GOTREL_LO12
- R_NDS32_RELATIVE
- R_NDS32_RELA_NOP_MAX
- R_NDS32_RELA_NOP_MIX
- R_NDS32_SDA15S0_RELA
- R_NDS32_SDA15S1_RELA
- R_NDS32_SDA15S2_RELA
- R_NDS32_SDA15S3_RELA
- R_NDS32_WORD_9_PCREL_RELA
- R_NGATE
- R_NIOS2_ALIGN
- R_NIOS2_BFD_RELOC_16
- R_NIOS2_BFD_RELOC_32
- R_NIOS2_BFD_RELOC_8
- R_NIOS2_CACHE_OPX
- R_NIOS2_CALL26
- R_NIOS2_CALLR
- R_NIOS2_CJMP
- R_NIOS2_GNU_VTENTRY
- R_NIOS2_GNU_VTINHERIT
- R_NIOS2_GPREL
- R_NIOS2_HI16
- R_NIOS2_HIADJ16
- R_NIOS2_IMM5
- R_NIOS2_IMM6
- R_NIOS2_IMM8
- R_NIOS2_LO16
- R_NIOS2_NONE
- R_NIOS2_NUM
- R_NIOS2_PCREL16
- R_NIOS2_S16
- R_NIOS2_U16
- R_NIOS2_UJMP
- R_NO
- R_NO_S
- R_ONLINE
- R_OPCODE_LSB
- R_OP_NOP
- R_OP_SHIFT
- R_OP_UPDATE
- R_OR32_16
- R_OR32_32
- R_OR32_8
- R_OR32_CONST
- R_OR32_CONSTH
- R_OR32_JUMPTARG
- R_OR32_NONE
- R_OR32_VTENTRY
- R_OR32_VTINHERIT
- R_OV
- R_OVOLCTLU
- R_OV_S
- R_OWN
- R_P1_SW_EVENTS
- R_P2_SW_EVENTS
- R_P3_SW_EVENTS
- R_PAGESEL
- R_PARISC_COPY
- R_PARISC_DIR14DR
- R_PARISC_DIR14R
- R_PARISC_DIR14WR
- R_PARISC_DIR16DF
- R_PARISC_DIR16F
- R_PARISC_DIR16WF
- R_PARISC_DIR17F
- R_PARISC_DIR17R
- R_PARISC_DIR21L
- R_PARISC_DIR32
- R_PARISC_DIR64
- R_PARISC_DPREL14R
- R_PARISC_DPREL21L
- R_PARISC_EPLT
- R_PARISC_FPTR64
- R_PARISC_GPREL14DR
- R_PARISC_GPREL14R
- R_PARISC_GPREL14WR
- R_PARISC_GPREL16DF
- R_PARISC_GPREL16F
- R_PARISC_GPREL16WF
- R_PARISC_GPREL21L
- R_PARISC_GPREL64
- R_PARISC_HIRESERVE
- R_PARISC_IPLT
- R_PARISC_LORESERVE
- R_PARISC_LTOFF14DR
- R_PARISC_LTOFF14R
- R_PARISC_LTOFF14WR
- R_PARISC_LTOFF16DF
- R_PARISC_LTOFF16F
- R_PARISC_LTOFF16WF
- R_PARISC_LTOFF21L
- R_PARISC_LTOFF64
- R_PARISC_LTOFF_FPTR14DR
- R_PARISC_LTOFF_FPTR14R
- R_PARISC_LTOFF_FPTR14WR
- R_PARISC_LTOFF_FPTR16DF
- R_PARISC_LTOFF_FPTR16F
- R_PARISC_LTOFF_FPTR16WF
- R_PARISC_LTOFF_FPTR21L
- R_PARISC_LTOFF_FPTR32
- R_PARISC_LTOFF_FPTR64
- R_PARISC_LTOFF_TP14DR
- R_PARISC_LTOFF_TP14F
- R_PARISC_LTOFF_TP14R
- R_PARISC_LTOFF_TP14WR
- R_PARISC_LTOFF_TP16DF
- R_PARISC_LTOFF_TP16F
- R_PARISC_LTOFF_TP16WF
- R_PARISC_LTOFF_TP21L
- R_PARISC_LTOFF_TP64
- R_PARISC_NONE
- R_PARISC_PCREL14DR
- R_PARISC_PCREL14R
- R_PARISC_PCREL14WR
- R_PARISC_PCREL16DF
- R_PARISC_PCREL16F
- R_PARISC_PCREL16WF
- R_PARISC_PCREL17F
- R_PARISC_PCREL17R
- R_PARISC_PCREL21L
- R_PARISC_PCREL22F
- R_PARISC_PCREL32
- R_PARISC_PCREL64
- R_PARISC_PLABEL32
- R_PARISC_PLTOFF14DR
- R_PARISC_PLTOFF14R
- R_PARISC_PLTOFF14WR
- R_PARISC_PLTOFF16DF
- R_PARISC_PLTOFF16F
- R_PARISC_PLTOFF16WF
- R_PARISC_PLTOFF21L
- R_PARISC_SECREL32
- R_PARISC_SECREL64
- R_PARISC_SEGBASE
- R_PARISC_SEGREL32
- R_PARISC_SEGREL64
- R_PARISC_TPREL14DR
- R_PARISC_TPREL14R
- R_PARISC_TPREL14WR
- R_PARISC_TPREL16DF
- R_PARISC_TPREL16F
- R_PARISC_TPREL16WF
- R_PARISC_TPREL21L
- R_PARISC_TPREL32
- R_PARISC_TPREL64
- R_PARSERCONFIGREG
- R_PCMP2CTL0
- R_PCMP2CTL1
- R_PCMP3CTL0
- R_PCMP3CTL1
- R_PCM_MD0
- R_PCM_MD1
- R_PCM_MD2
- R_PDE_CLASS_0
- R_PDE_CLASS_1
- R_PDE_CLASS_2
- R_PDE_CLASS_3
- R_PGACTL0
- R_PGACTL1
- R_PGACTL2
- R_PGACTL3
- R_PGAZ
- R_PID
- R_PID_DATA0
- R_PID_DATA1
- R_PID_SETUP
- R_PL
- R_PLL1CTL
- R_PLL1FDIVH
- R_PLL1FDIVL
- R_PLL1ODIV
- R_PLL1RDIV
- R_PLL2CTL
- R_PLL2FDIVH
- R_PLL2FDIVL
- R_PLL2ODIV
- R_PLL2RDIV
- R_PLLCTL
- R_PLLCTL0
- R_PLLCTL10
- R_PLLCTL11
- R_PLLCTL12
- R_PLLCTL1B
- R_PLLCTL1C
- R_PLLCTL9
- R_PLLCTLA
- R_PLLCTLB
- R_PLLCTLC
- R_PLLCTLD
- R_PLLCTLE
- R_PLLCTLF
- R_PLLREFSEL
- R_PLLSTAT
- R_POLLRATE
- R_PPC64_ADDR14
- R_PPC64_ADDR14_BRNTAKEN
- R_PPC64_ADDR14_BRTAKEN
- R_PPC64_ADDR16
- R_PPC64_ADDR16_DS
- R_PPC64_ADDR16_HA
- R_PPC64_ADDR16_HI
- R_PPC64_ADDR16_HIGHER
- R_PPC64_ADDR16_HIGHERA
- R_PPC64_ADDR16_HIGHEST
- R_PPC64_ADDR16_HIGHESTA
- R_PPC64_ADDR16_LO
- R_PPC64_ADDR16_LO_DS
- R_PPC64_ADDR24
- R_PPC64_ADDR30
- R_PPC64_ADDR32
- R_PPC64_ADDR64
- R_PPC64_COPY
- R_PPC64_DTPMOD64
- R_PPC64_DTPREL16
- R_PPC64_DTPREL16_DS
- R_PPC64_DTPREL16_HA
- R_PPC64_DTPREL16_HI
- R_PPC64_DTPREL16_HIGHER
- R_PPC64_DTPREL16_HIGHERA
- R_PPC64_DTPREL16_HIGHEST
- R_PPC64_DTPREL16_HIGHESTA
- R_PPC64_DTPREL16_LO
- R_PPC64_DTPREL16_LO_DS
- R_PPC64_DTPREL64
- R_PPC64_ENTRY
- R_PPC64_GLOB_DAT
- R_PPC64_GOT16
- R_PPC64_GOT16_DS
- R_PPC64_GOT16_HA
- R_PPC64_GOT16_HI
- R_PPC64_GOT16_LO
- R_PPC64_GOT16_LO_DS
- R_PPC64_GOT_DTPREL16_DS
- R_PPC64_GOT_DTPREL16_HA
- R_PPC64_GOT_DTPREL16_HI
- R_PPC64_GOT_DTPREL16_LO_DS
- R_PPC64_GOT_TLSGD16
- R_PPC64_GOT_TLSGD16_HA
- R_PPC64_GOT_TLSGD16_HI
- R_PPC64_GOT_TLSGD16_LO
- R_PPC64_GOT_TLSLD16
- R_PPC64_GOT_TLSLD16_HA
- R_PPC64_GOT_TLSLD16_HI
- R_PPC64_GOT_TLSLD16_LO
- R_PPC64_GOT_TPREL16_DS
- R_PPC64_GOT_TPREL16_HA
- R_PPC64_GOT_TPREL16_HI
- R_PPC64_GOT_TPREL16_LO_DS
- R_PPC64_JMP_SLOT
- R_PPC64_NONE
- R_PPC64_NUM
- R_PPC64_PLT16_HA
- R_PPC64_PLT16_HI
- R_PPC64_PLT16_LO
- R_PPC64_PLT16_LO_DS
- R_PPC64_PLT32
- R_PPC64_PLT64
- R_PPC64_PLTGOT16
- R_PPC64_PLTGOT16_DS
- R_PPC64_PLTGOT16_HA
- R_PPC64_PLTGOT16_HI
- R_PPC64_PLTGOT16_LO
- R_PPC64_PLTGOT16_LO_DS
- R_PPC64_PLTREL32
- R_PPC64_PLTREL64
- R_PPC64_REL14
- R_PPC64_REL14_BRNTAKEN
- R_PPC64_REL14_BRTAKEN
- R_PPC64_REL16
- R_PPC64_REL16_HA
- R_PPC64_REL16_HI
- R_PPC64_REL16_LO
- R_PPC64_REL24
- R_PPC64_REL32
- R_PPC64_REL64
- R_PPC64_RELATIVE
- R_PPC64_SECTOFF
- R_PPC64_SECTOFF_DS
- R_PPC64_SECTOFF_HA
- R_PPC64_SECTOFF_HI
- R_PPC64_SECTOFF_LO
- R_PPC64_SECTOFF_LO_DS
- R_PPC64_TLS
- R_PPC64_TLSGD
- R_PPC64_TLSLD
- R_PPC64_TOC
- R_PPC64_TOC16
- R_PPC64_TOC16_DS
- R_PPC64_TOC16_HA
- R_PPC64_TOC16_HI
- R_PPC64_TOC16_LO
- R_PPC64_TOC16_LO_DS
- R_PPC64_TOCSAVE
- R_PPC64_TPREL16
- R_PPC64_TPREL16_DS
- R_PPC64_TPREL16_HA
- R_PPC64_TPREL16_HI
- R_PPC64_TPREL16_HIGHER
- R_PPC64_TPREL16_HIGHERA
- R_PPC64_TPREL16_HIGHEST
- R_PPC64_TPREL16_HIGHESTA
- R_PPC64_TPREL16_LO
- R_PPC64_TPREL16_LO_DS
- R_PPC64_TPREL64
- R_PPC64_UADDR16
- R_PPC64_UADDR32
- R_PPC64_UADDR64
- R_PPC_ADDR14
- R_PPC_ADDR14_BRNTAKEN
- R_PPC_ADDR14_BRTAKEN
- R_PPC_ADDR16
- R_PPC_ADDR16_HA
- R_PPC_ADDR16_HI
- R_PPC_ADDR16_LO
- R_PPC_ADDR24
- R_PPC_ADDR32
- R_PPC_COPY
- R_PPC_DTPMOD32
- R_PPC_DTPREL16
- R_PPC_DTPREL16_HA
- R_PPC_DTPREL16_HI
- R_PPC_DTPREL16_LO
- R_PPC_DTPREL32
- R_PPC_GLOB_DAT
- R_PPC_GOT16
- R_PPC_GOT16_HA
- R_PPC_GOT16_HI
- R_PPC_GOT16_LO
- R_PPC_GOT_DTPREL16
- R_PPC_GOT_DTPREL16_HA
- R_PPC_GOT_DTPREL16_HI
- R_PPC_GOT_DTPREL16_LO
- R_PPC_GOT_TLSGD16
- R_PPC_GOT_TLSGD16_HA
- R_PPC_GOT_TLSGD16_HI
- R_PPC_GOT_TLSGD16_LO
- R_PPC_GOT_TLSLD16
- R_PPC_GOT_TLSLD16_HA
- R_PPC_GOT_TLSLD16_HI
- R_PPC_GOT_TLSLD16_LO
- R_PPC_GOT_TPREL16
- R_PPC_GOT_TPREL16_HA
- R_PPC_GOT_TPREL16_HI
- R_PPC_GOT_TPREL16_LO
- R_PPC_JMP_SLOT
- R_PPC_LOCAL24PC
- R_PPC_NONE
- R_PPC_NUM
- R_PPC_PLT16_HA
- R_PPC_PLT16_HI
- R_PPC_PLT16_LO
- R_PPC_PLT32
- R_PPC_PLTREL24
- R_PPC_PLTREL32
- R_PPC_REL14
- R_PPC_REL14_BRNTAKEN
- R_PPC_REL14_BRTAKEN
- R_PPC_REL24
- R_PPC_REL32
- R_PPC_RELATIVE
- R_PPC_SDAREL16
- R_PPC_SECTOFF
- R_PPC_SECTOFF_HA
- R_PPC_SECTOFF_HI
- R_PPC_SECTOFF_LO
- R_PPC_TLS
- R_PPC_TPREL16
- R_PPC_TPREL16_HA
- R_PPC_TPREL16_HI
- R_PPC_TPREL16_LO
- R_PPC_TPREL32
- R_PPC_UADDR16
- R_PPC_UADDR32
- R_PR
- R_PRIMARY
- R_PWM0
- R_PWM1
- R_PWM2
- R_PWM3
- R_PWM_MD
- R_PWRM0
- R_PWRM1
- R_PWRM2
- R_PWRM3
- R_PWRM4
- R_RALN
- R_RAM_ADDR0
- R_RAM_ADDR1
- R_RAM_ADDR2
- R_RAM_DATA
- R_RAM_SZ
- R_RAM_USE
- R_RBCA
- R_RBYT
- R_RCDE
- R_RCS
- R_RCSE
- R_RDY
- R_RDY_MASK
- R_RDY_MASK_SFT
- R_RDY_SFT
- R_RECEIVE_RECOVER
- R_RECEIVE_REQUEST
- R_REG_FRIN1_SPILL_MEM_SIZE
- R_REG_FRIN1_SPILL_MEM_START_0
- R_REG_FRIN1_SPILL_MEM_START_1
- R_REG_FRIN_SPILL_MEM_SIZE
- R_REG_FRIN_SPILL_MEM_START_0
- R_REG_FRIN_SPILL_MEM_START_1
- R_REQUEST
- R_RESET
- R_RFCS
- R_RFLR
- R_RISCV_32
- R_RISCV_32_PCREL
- R_RISCV_64
- R_RISCV_ADD16
- R_RISCV_ADD32
- R_RISCV_ADD64
- R_RISCV_ADD8
- R_RISCV_ALIGN
- R_RISCV_BRANCH
- R_RISCV_CALL
- R_RISCV_CALL_PLT
- R_RISCV_COPY
- R_RISCV_GNU_VTENTRY
- R_RISCV_GNU_VTINHERIT
- R_RISCV_GOT_HI20
- R_RISCV_GPREL_I
- R_RISCV_GPREL_S
- R_RISCV_HI20
- R_RISCV_JAL
- R_RISCV_JUMP_SLOT
- R_RISCV_LO12_I
- R_RISCV_LO12_S
- R_RISCV_LUI
- R_RISCV_NONE
- R_RISCV_PCREL_HI20
- R_RISCV_PCREL_LO12_I
- R_RISCV_PCREL_LO12_S
- R_RISCV_RELATIVE
- R_RISCV_RELAX
- R_RISCV_RVC_BRANCH
- R_RISCV_RVC_JUMP
- R_RISCV_SET16
- R_RISCV_SET32
- R_RISCV_SET6
- R_RISCV_SET8
- R_RISCV_SUB16
- R_RISCV_SUB32
- R_RISCV_SUB6
- R_RISCV_SUB64
- R_RISCV_SUB8
- R_RISCV_TLS_DTPMOD32
- R_RISCV_TLS_DTPMOD64
- R_RISCV_TLS_DTPREL32
- R_RISCV_TLS_DTPREL64
- R_RISCV_TLS_GD_HI20
- R_RISCV_TLS_GOT_HI20
- R_RISCV_TLS_TPREL32
- R_RISCV_TLS_TPREL64
- R_RISCV_TPREL_ADD
- R_RISCV_TPREL_HI20
- R_RISCV_TPREL_I
- R_RISCV_TPREL_LO12_I
- R_RISCV_TPREL_LO12_S
- R_RISCV_TPREL_S
- R_RMCA
- R_ROTATE_0
- R_ROTATE_90
- R_ROUND_ROBIN_TABLE
- R_ROVR
- R_RPKT
- R_RUND
- R_RX0
- R_RXCF
- R_RXDATAFIFO0
- R_RXDATAFIFO1
- R_RXDATAFIFO2
- R_RXDATAFIFO3
- R_RXDATAFIFO4
- R_RXDATAFIFO5
- R_RXDATAFIFO6
- R_RXDATAFIFO7
- R_RXERR
- R_RXPF
- R_RXUO
- R_RXWATERMARKS1
- R_RXWATERMARKS2
- R_RXWATERMARKS3
- R_RXWATERMARKS4
- R_RX_CONTROL
- R_RX_FR0
- R_RX_FR1
- R_RX_OFF
- R_RX_RING
- R_RX_SL0_0
- R_RX_SL0_1
- R_RX_SL0_2
- R_SA6_SA13_EC
- R_SA6_SA13_ECH
- R_SA6_SA13_ECL
- R_SA6_SA23_EC
- R_SA6_SA23_ECH
- R_SA6_SA23_ECL
- R_SCD_TIMER_CFG
- R_SCD_TIMER_CNT
- R_SCD_TIMER_INIT
- R_SCD_WDOG_CFG
- R_SCD_WDOG_CNT
- R_SCD_WDOG_INIT
- R_SCI_MSK
- R_SCLKCTL
- R_SCSTAT
- R_SDMON
- R_SECONDARY
- R_SECTOR
- R_SEQ_ADD_A2S
- R_SEQ_ADD_S2A12
- R_SEQ_ADD_S2A3
- R_SEQ_ADD_WARM
- R_SER_ADDR
- R_SER_CMD
- R_SER_DMA_CHANNELS
- R_SER_DMA_CONFIG0
- R_SER_DMA_CONFIG0_RX
- R_SER_DMA_CONFIG0_TX
- R_SER_DMA_CONFIG1
- R_SER_DMA_CONFIG1_RX
- R_SER_DMA_CONFIG1_TX
- R_SER_DMA_CUR_DSCRA
- R_SER_DMA_CUR_DSCRADDR
- R_SER_DMA_CUR_DSCRB
- R_SER_DMA_CUR_DSCR_ADDR_RX
- R_SER_DMA_CUR_DSCR_ADDR_TX
- R_SER_DMA_CUR_DSCR_A_RX
- R_SER_DMA_CUR_DSCR_A_TX
- R_SER_DMA_CUR_DSCR_B_RX
- R_SER_DMA_CUR_DSCR_B_TX
- R_SER_DMA_DSCR_BASE
- R_SER_DMA_DSCR_BASE_RX
- R_SER_DMA_DSCR_BASE_TX
- R_SER_DMA_DSCR_CNT
- R_SER_DMA_DSCR_COUNT_RX
- R_SER_DMA_DSCR_COUNT_TX
- R_SER_DMA_ENABLE
- R_SER_INT_MASK
- R_SER_LINE_MODE
- R_SER_MAXFRM_SZ
- R_SER_MINFRM_SZ
- R_SER_MODE
- R_SER_RMON_RX_BADADDR
- R_SER_RMON_RX_BYTE_HI
- R_SER_RMON_RX_BYTE_LO
- R_SER_RMON_RX_ERRORS
- R_SER_RMON_RX_OVERFLOW
- R_SER_RMON_TX_BYTE_HI
- R_SER_RMON_TX_BYTE_LO
- R_SER_RMON_TX_UNDERRUN
- R_SER_RX_RD_THRSH
- R_SER_RX_TABLE_BASE
- R_SER_STATUS
- R_SER_STATUS_DEBUG
- R_SER_TX_RD_THRSH
- R_SER_TX_TABLE_BASE
- R_SER_TX_WR_THRSH
- R_SER_USR0_ADDR
- R_SER_USR1_ADDR
- R_SER_USR2_ADDR
- R_SER_USR3_ADDR
- R_SH
- R_SH0H
- R_SH0L
- R_SH1H
- R_SH1L
- R_SHIFT_1_MASK
- R_SHIFT_2_MASK
- R_SHIFT_4_MASK
- R_SH_ALIGN
- R_SH_CODE
- R_SH_COPY
- R_SH_COUNT
- R_SH_DATA
- R_SH_DIR32
- R_SH_DIR8BP
- R_SH_DIR8L
- R_SH_DIR8W
- R_SH_DIR8WPL
- R_SH_DIR8WPN
- R_SH_DIR8WPZ
- R_SH_FUNCDESC
- R_SH_FUNCDESC_VALUE
- R_SH_GLOB_DAT
- R_SH_GNU_VTENTRY
- R_SH_GNU_VTINHERIT
- R_SH_GOT20
- R_SH_GOT32
- R_SH_GOTFUNCDESC
- R_SH_GOTFUNCDESC20
- R_SH_GOTOFF
- R_SH_GOTOFF20
- R_SH_GOTOFFFUNCDESC
- R_SH_GOTOFFFUNCDESC20
- R_SH_GOTPC
- R_SH_IMM_LOW16
- R_SH_IMM_LOW16_PCREL
- R_SH_IMM_MEDLOW16
- R_SH_IMM_MEDLOW16_PCREL
- R_SH_IND12W
- R_SH_JMP_SLOT
- R_SH_LABEL
- R_SH_NONE
- R_SH_NUM
- R_SH_PLT32
- R_SH_REL32
- R_SH_RELATIVE
- R_SH_SWITCH16
- R_SH_SWITCH32
- R_SH_SWITCH8
- R_SH_TLS_DTPMOD32
- R_SH_TLS_DTPOFF32
- R_SH_TLS_GD_32
- R_SH_TLS_IE_32
- R_SH_TLS_LDO_32
- R_SH_TLS_LD_32
- R_SH_TLS_LE_32
- R_SH_TLS_TPOFF32
- R_SH_USES
- R_SIZECODE
- R_SLIP
- R_SLOT
- R_SL_SEL0
- R_SL_SEL1
- R_SL_SEL2
- R_SL_SEL3
- R_SL_SEL4
- R_SL_SEL5
- R_SL_SEL6
- R_SL_SEL7
- R_SMB_CMD
- R_SMB_CONTROL
- R_SMB_DATA
- R_SMB_FREQ
- R_SMB_PEC
- R_SMB_START
- R_SMB_STATUS
- R_SMB_XTRA
- R_SPARC_10
- R_SPARC_11
- R_SPARC_13
- R_SPARC_16
- R_SPARC_22
- R_SPARC_32
- R_SPARC_5
- R_SPARC_6
- R_SPARC_64
- R_SPARC_7
- R_SPARC_8
- R_SPARC_COPY
- R_SPARC_DISP16
- R_SPARC_DISP32
- R_SPARC_DISP8
- R_SPARC_GLOB_DAT
- R_SPARC_GOT10
- R_SPARC_GOT13
- R_SPARC_GOT22
- R_SPARC_HI22
- R_SPARC_HIPLT22
- R_SPARC_JMP_SLOT
- R_SPARC_LO10
- R_SPARC_LOPLT10
- R_SPARC_NONE
- R_SPARC_OLO10
- R_SPARC_PC10
- R_SPARC_PC22
- R_SPARC_PCPLT10
- R_SPARC_PCPLT22
- R_SPARC_PCPLT32
- R_SPARC_PLT32
- R_SPARC_RELATIVE
- R_SPARC_UA32
- R_SPARC_WDISP16
- R_SPARC_WDISP19
- R_SPARC_WDISP22
- R_SPARC_WDISP30
- R_SPARC_WPLT30
- R_SPI4CONTROL
- R_SPI4STATICDELAY0
- R_SPI4STATICDELAY1
- R_SPI4STATICDELAY2
- R_SPIHNGY0
- R_SPIHNGY1
- R_SPIHNGY2
- R_SPIHNGY3
- R_SPISTRV0
- R_SPISTRV1
- R_SPISTRV2
- R_SPISTRV3
- R_SPI_MISO_MARK
- R_SPI_MOSI_MARK
- R_SPI_RSPCK_MARK
- R_SPI_SSL0_MARK
- R_SPI_SSL1_MARK
- R_SPKCLECTL
- R_SPKCLEMUG
- R_SPKCOMPATKH
- R_SPKCOMPATKL
- R_SPKCOMPRAT
- R_SPKCOMPRELH
- R_SPKCOMPRELL
- R_SPKCOMPTHR
- R_SPKCRADD
- R_SPKCRRDH
- R_SPKCRRDL
- R_SPKCRRDM
- R_SPKCRS
- R_SPKCRWDH
- R_SPKCRWDL
- R_SPKCRWDM
- R_SPKCTL
- R_SPKEQFILT
- R_SPKEXPATKH
- R_SPKEXPATKL
- R_SPKEXPRAT
- R_SPKEXPRELH
- R_SPKEXPRELL
- R_SPKEXPTHR
- R_SPKFXCTL
- R_SPKLIMATKH
- R_SPKLIMATKL
- R_SPKLIMRELH
- R_SPKLIMRELL
- R_SPKLIMTGT
- R_SPKLIMTHR
- R_SPKMBCATK1H
- R_SPKMBCATK1L
- R_SPKMBCATK2H
- R_SPKMBCATK2L
- R_SPKMBCATK3H
- R_SPKMBCATK3L
- R_SPKMBCCTL
- R_SPKMBCEN
- R_SPKMBCMUG1
- R_SPKMBCMUG2
- R_SPKMBCMUG3
- R_SPKMBCRAT1
- R_SPKMBCRAT2
- R_SPKMBCRAT3
- R_SPKMBCREL1H
- R_SPKMBCREL1L
- R_SPKMBCREL2H
- R_SPKMBCREL2L
- R_SPKMBCREL3H
- R_SPKMBCREL3L
- R_SPKMBCTHR1
- R_SPKMBCTHR2
- R_SPKMBCTHR3
- R_SPKVOLL
- R_SPKVOLR
- R_STATCTRL
- R_STATE
- R_STATION_ADDRESS_LS
- R_STATION_ADDRESS_MS
- R_STATUS
- R_STS
- R_ST_SEL
- R_ST_SYNC
- R_SUBCLECTL
- R_SUBCLEMUG
- R_SUBCOMPATKH
- R_SUBCOMPATKL
- R_SUBCOMPRAT
- R_SUBCOMPRELH
- R_SUBCOMPRELL
- R_SUBCOMPTHR
- R_SUBCRADD
- R_SUBCRRDH
- R_SUBCRRDL
- R_SUBCRRDM
- R_SUBCRS
- R_SUBCRWDH
- R_SUBCRWDL
- R_SUBCRWDM
- R_SUBCTL
- R_SUBEQFILT
- R_SUBEXPATKH
- R_SUBEXPATKL
- R_SUBEXPRAT
- R_SUBEXPRELH
- R_SUBEXPRELL
- R_SUBEXPTHR
- R_SUBFXCTL
- R_SUBLIMATKH
- R_SUBLIMATKL
- R_SUBLIMRELH
- R_SUBLIMRELL
- R_SUBLIMTGT
- R_SUBLIMTHR
- R_SUBMBCATK1H
- R_SUBMBCATK1L
- R_SUBMBCATK2H
- R_SUBMBCATK2L
- R_SUBMBCATK3H
- R_SUBMBCATK3L
- R_SUBMBCCTL
- R_SUBMBCEN
- R_SUBMBCMUG1
- R_SUBMBCMUG2
- R_SUBMBCMUG3
- R_SUBMBCRAT1
- R_SUBMBCRAT2
- R_SUBMBCRAT3
- R_SUBMBCREL1H
- R_SUBMBCREL1L
- R_SUBMBCREL2H
- R_SUBMBCREL2L
- R_SUBMBCREL3H
- R_SUBMBCREL3L
- R_SUBMBCTHR1
- R_SUBMBCTHR2
- R_SUBMBCTHR3
- R_SUBVOL
- R_SYNC_CTRL
- R_SYNC_OUT
- R_SYNC_STA
- R_TBCA
- R_TBYT
- R_TDFR
- R_TDI_LSB
- R_TDMCTL0
- R_TDMCTL1
- R_TDO_LSB
- R_TEDF
- R_TEST
- R_TFCS
- R_TFRG
- R_THERMSPK1
- R_THERMSTAT
- R_THERMTS
- R_TIMEBASE
- R_TI_WD
- R_TJBR
- R_TLCL
- R_TM
- R_TMCA
- R_TMCL
- R_TNCL
- R_TOVR
- R_TPKT
- R_TRACK
- R_TRANSLATETABLE
- R_TSCL
- R_TUND
- R_TUNE_EN
- R_TX0
- R_TX1
- R_TXCF
- R_TXCL
- R_TXDATAFIFO0
- R_TXDATAFIFO1
- R_TXDATAFIFO2
- R_TXDATAFIFO3
- R_TXDATAFIFO4
- R_TXDATAFIFO5
- R_TXDATAFIFO6
- R_TXDATAFIFO7
- R_TXPF
- R_TXRETRY
- R_TX_CONTROL
- R_TX_FR0
- R_TX_FR1
- R_TX_FR2
- R_TX_OFF
- R_TX_RING
- R_UNICORE_ABS32
- R_UNICORE_CALL
- R_UNICORE_JUMP24
- R_UNICORE_NONE
- R_UNICORE_PC24
- R_UNKNOWN
- R_VCS
- R_VCS1
- R_VCS2
- R_VECS
- R_VIO_EC
- R_VIO_ECH
- R_VIO_ECL
- R_W
- R_W_EN_MASK
- R_W_EN_MASK_SFT
- R_W_EN_SFT
- R_W_S
- R_W_SEL_MASK
- R_W_SEL_MASK_SFT
- R_W_SEL_SFT
- R_X86_64_16
- R_X86_64_32
- R_X86_64_32S
- R_X86_64_64
- R_X86_64_8
- R_X86_64_COPY
- R_X86_64_GLOB_DAT
- R_X86_64_GOT32
- R_X86_64_GOTPCREL
- R_X86_64_JUMP_SLOT
- R_X86_64_NONE
- R_X86_64_PC16
- R_X86_64_PC32
- R_X86_64_PC64
- R_X86_64_PC8
- R_X86_64_PLT32
- R_X86_64_RELATIVE
- R_XATKTCH
- R_XATKTCL
- R_XGMACPADCALIBRATION
- R_XGMAC_CONFIG_0
- R_XGMAC_CONFIG_1
- R_XGMAC_CONFIG_2
- R_XGMAC_CONFIG_3
- R_XGMAC_MAX_FRAME_LEN
- R_XGMAC_MIIM_COMMAND
- R_XGMAC_MIIM_CONFIG
- R_XGMAC_MIIM_FILED
- R_XGMAC_MIIM_INDICATOR
- R_XGMAC_MIIM_LINK_FAIL_VECTOR
- R_XGMAC_REV_LEVEL
- R_XGMAC_STATION_ADDRESS_LS
- R_XGMAC_STATION_ADDRESS_MS
- R_XGS_JFR_BUCKET_SIZE
- R_XGS_RFR_BUCKET_SIZE
- R_XGS_TX0_BUCKET_SIZE
- R_XGS_TX10_BUCKET_SIZE
- R_XGS_TX11_BUCKET_SIZE
- R_XGS_TX12_BUCKET_SIZE
- R_XGS_TX13_BUCKET_SIZE
- R_XGS_TX14_BUCKET_SIZE
- R_XGS_TX15_BUCKET_SIZE
- R_XGS_TX1_BUCKET_SIZE
- R_XGS_TX2_BUCKET_SIZE
- R_XGS_TX3_BUCKET_SIZE
- R_XGS_TX4_BUCKET_SIZE
- R_XGS_TX5_BUCKET_SIZE
- R_XGS_TX6_BUCKET_SIZE
- R_XGS_TX7_BUCKET_SIZE
- R_XGS_TX8_BUCKET_SIZE
- R_XGS_TX9_BUCKET_SIZE
- R_XRELTCH
- R_XRELTCL
- R_XTENSA_32
- R_XTENSA_ASM_EXPAND
- R_XTENSA_ASM_SIMPLIFY
- R_XTENSA_DIFF16
- R_XTENSA_DIFF32
- R_XTENSA_DIFF8
- R_XTENSA_GLOB_DAT
- R_XTENSA_GNU_VTENTRY
- R_XTENSA_GNU_VTINHERIT
- R_XTENSA_JMP_SLOT
- R_XTENSA_NONE
- R_XTENSA_OP0
- R_XTENSA_OP1
- R_XTENSA_OP2
- R_XTENSA_PLT
- R_XTENSA_RELATIVE
- R_XTENSA_RTLD
- R_XTENSA_SLOT0_ALT
- R_XTENSA_SLOT0_OP
- R_XTENSA_SLOT10_ALT
- R_XTENSA_SLOT10_OP
- R_XTENSA_SLOT11_ALT
- R_XTENSA_SLOT11_OP
- R_XTENSA_SLOT12_ALT
- R_XTENSA_SLOT12_OP
- R_XTENSA_SLOT13_ALT
- R_XTENSA_SLOT13_OP
- R_XTENSA_SLOT14_ALT
- R_XTENSA_SLOT14_OP
- R_XTENSA_SLOT1_ALT
- R_XTENSA_SLOT1_OP
- R_XTENSA_SLOT2_ALT
- R_XTENSA_SLOT2_OP
- R_XTENSA_SLOT3_ALT
- R_XTENSA_SLOT3_OP
- R_XTENSA_SLOT4_ALT
- R_XTENSA_SLOT4_OP
- R_XTENSA_SLOT5_ALT
- R_XTENSA_SLOT5_OP
- R_XTENSA_SLOT6_ALT
- R_XTENSA_SLOT6_OP
- R_XTENSA_SLOT7_ALT
- R_XTENSA_SLOT7_OP
- R_XTENSA_SLOT8_ALT
- R_XTENSA_SLOT8_OP
- R_XTENSA_SLOT9_ALT
- R_XTENSA_SLOT9_OP
- Rabit
- RadioA_ArrayLength
- RadioA_ArrayLengthPciE
- RadioB_ArrayLength
- RadioB_ArrayLengthPciE
- RadioC_ArrayLength
- RadioC_ArrayLengthPciE
- RadioD_ArrayLength
- RadioD_ArrayLengthPciE
- RaidCfgData
- RaidPhysDisk0ErrorData_t
- RaidPhysDisk0InquiryData
- RaidPhysDisk1Path_t
- RaidPhysDiskPage0_t
- RaidPhysDiskPage1_t
- RaidPhysDiskSettings_t
- RaidPhysDiskStatus_t
- RaidVol0PhysDisk_t
- RaidVol0Settings
- RaidVol0Status_t
- RaidVolumePage0_t
- RaidVolumePage1_t
- RamMemType
- Ram_size
- Ram_speed
- Ram_split
- Ram_split_shift
- Ram_width
- RasMessage
- RateAdaptiveTH_High
- RateAdaptiveTH_Low_20M
- RateAdaptiveTH_Low_40M
- Rate_ID_SHT
- Ratio_Add
- Ratio_Val
- RawNTLMSSP
- Raw_Video
- RayDAT
- RbMap
- RbXsel
- RbXsel2
- RbYsel
- RcvFCS
- RdAddr
- RdExBase
- RdExLimit
- RdramMemType
- Rdy_to_L23
- Read
- Read16
- Read32
- ReadAdapterInfo8723BS
- ReadChipVersion8723B
- ReadDOC
- ReadDOC_
- ReadDirectory
- ReadDirectoryPlus
- ReadEDIDFromHWAssistedI2C
- ReadEEProm
- ReadExtented
- ReadFiFoISAC_V1
- ReadFiFoISAC_V2
- ReadFiFoISAC_nj
- ReadFixable
- ReadGenCfg
- ReadHSCX
- ReadIFAgc
- ReadIPAC
- ReadISAC
- ReadISAC_V1
- ReadISAC_V2
- ReadISAC_nj
- ReadInterrupt8723BSdio
- ReadLink
- ReadMem
- ReadMsaCfg
- ReadOnly
- ReadPersistent
- ReadPolicy
- ReadRFThermalMeter
- ReadROM
- ReadReg
- ReadSize
- ReadTransient
- ReadW6692
- ReadW6692B
- Read_hfc
- ReceiveAllFrames
- ReceiveBroadcast
- ReceiveIPMulticast
- ReceiveMode
- ReceiveMode_bits
- ReceiveMulticast
- ReceiveMulticastHash
- ReceiveUnicast
- ReceiveVLANHash
- ReceiveVLANMatch
- RecvOnePkt
- Reg1d
- Reg7b
- Reg81
- RegC38_Default
- RegC38_Fsync_AP_BCM
- RegC38_NonFsync_Other_AP
- RegC38_TH
- RegDesc
- RegInitializer
- Reg_CSM_MC
- Reg_CSM_MR
- Register
- RegistrationConfirm
- RegistrationConfirm_callSignalAddress
- RegistrationRequest
- RegistrationRequest_callSignalAddress
- RegistrationRequest_rasAddress
- ReinitAdapHighCommandQueue
- ReinitAdapHighRespQueue
- ReinitAdapNormCommandQueue
- ReinitAdapNormRespQueue
- ReinitHostHighCommandQueue
- ReinitHostHighRespQueue
- ReinitHostNormCommandQueue
- ReinitHostNormRespQueue
- ReleaseBitmap
- ReleaseBmp
- ReleaseWin
- Removable
- RemoveAllTS
- RemoveDirectoryx
- RemoveNode
- RemovePeerTS
- RemoveSynchronized
- RemoveTsEntry
- Removex
- Rename
- Replacement
- ReportExtendedLUNdata
- ReportLUNdata
- ReqRegister
- ReqSTC
- ReqSecFilterError
- ReqVCXO
- ReqVersion
- RequestAdapterInfo
- RequestBlock
- RequestBlock_struct
- RequestMessage
- RequestPerfData
- RequestSupplementAdapterInfo
- ResId
- ReserveArea
- Reserved
- Reserved142
- Reserved143
- Reserved144
- Reserved145
- Reserved146
- Reserved147
- Reserved148
- Reserved149
- Reserved18
- Reserved182
- Reserved183
- Reserved184
- Reserved185
- Reserved186
- Reserved187
- Reserved188
- Reserved189
- Reserved190
- Reserved191
- Reserved192
- Reserved193
- Reserved194
- Reserved195
- Reserved196
- Reserved197
- Reserved198
- Reserved199
- Reserved200
- Reserved201
- Reserved202
- Reserved203
- Reserved204
- Reserved205
- Reserved206
- Reserved207
- Reserved208
- Reserved209
- Reserved210
- Reserved211
- Reserved212
- Reserved213
- Reserved214
- Reserved215
- Reserved216
- Reserved217
- Reserved218
- Reserved219
- Reserved23
- Reserved252
- Reserved253
- Reserved254
- Reserved255
- Reserved256
- Reserved257
- Reserved258
- Reserved259
- Reserved26
- Reserved260
- Reserved261
- Reserved262
- Reserved263
- Reserved264
- Reserved265
- Reserved266
- Reserved267
- Reserved27
- Reserved28
- Reserved29
- Reserved300
- Reserved301
- Reserved302
- Reserved303
- Reserved304
- Reserved305
- Reserved306
- Reserved307
- Reserved308
- Reserved309
- Reserved310
- Reserved311
- Reserved312
- Reserved313
- Reserved314
- Reserved315
- Reserved316
- Reserved317
- Reserved318
- Reserved319
- Reserved320
- Reserved321
- Reserved322
- Reserved323
- Reserved324
- Reserved325
- Reserved326
- Reserved327
- Reserved328
- Reserved329
- Reserved330
- Reserved331
- Reserved364
- Reserved365
- Reserved366
- Reserved367
- Reserved368
- Reserved369
- Reserved370
- Reserved371
- Reserved372
- Reserved373
- Reserved374
- Reserved375
- Reserved376
- Reserved377
- Reserved378
- Reserved379
- Reserved412
- Reserved413
- Reserved414
- Reserved415
- Reserved416
- Reserved417
- Reserved418
- Reserved419
- Reserved420
- Reserved421
- Reserved422
- Reserved423
- Reserved424
- Reserved425
- Reserved426
- Reserved427
- Reserved428
- Reserved429
- Reserved430
- Reserved431
- Reserved432
- Reserved433
- Reserved434
- Reserved435
- Reserved436
- Reserved437
- Reserved438
- Reserved439
- Reserved440
- Reserved441
- Reserved442
- Reserved443
- Reserved444
- Reserved445
- Reserved446
- Reserved447
- Reserved448
- Reserved449
- Reserved450
- Reserved451
- Reserved452
- Reserved453
- Reserved454
- Reserved455
- Reserved456
- Reserved457
- Reserved458
- Reserved459
- Reserved460
- Reserved461
- Reserved462
- Reserved463
- Reserved464
- Reserved465
- Reserved466
- Reserved467
- Reserved468
- Reserved469
- Reserved470
- Reserved471
- Reserved472
- Reserved473
- Reserved474
- Reserved475
- Reserved476
- Reserved477
- Reserved478
- Reserved479
- Reserved480
- Reserved481
- Reserved482
- Reserved483
- Reserved484
- Reserved485
- Reserved486
- Reserved487
- Reserved488
- Reserved489
- Reserved490
- Reserved491
- Reserved492
- Reserved493
- Reserved494
- Reserved495
- Reserved496
- Reserved497
- Reserved498
- Reserved499
- Reserved500
- Reserved501
- Reserved502
- Reserved503
- Reserved504
- Reserved505
- Reserved506
- Reserved507
- Reserved508
- Reserved509
- Reserved510
- Reserved511
- Reserved_0x00
- Reserved_0x09
- Reserved_0x0E
- Reserved_0x13
- Reserved_0x25
- Reserved_0x3f
- Reserved_SIZE
- Reset
- ResetAdapter
- ResetBaEntry
- ResetBusy
- ResetCEFR
- ResetECOD
- ResetLedStatus
- ResetOverlayRegisters
- ResetRxTsEntry
- ResetTT
- ResetTsCommonInfo
- ResetTxTsEntry
- Reset_Cnt_Limit
- Reset_Reg
- Resp
- ResponseExpected
- ResponseMessage
- RestartTx
- Restore_DM_Func_Flag
- ResumeTxBeacon
- RetryTxLC
- Rev012A
- Rev072A
- RevisionID
- Rf01
- RfOnOffDetect
- Rg
- Rid
- RightAntenna
- RigidDiskBlock
- RingCounterControl
- RingEnd
- RivaBitmap
- RivaClip
- RivaGetConfig
- RivaLine
- RivaPattern
- RivaPixmap
- RivaRectangle
- RivaRop
- RivaScreenBlt
- RivaSurface
- RivaSurface3D
- RivaTexturedTriangle03
- RivaTexturedTriangle05
- RlcPaceFlopsPerByteOverride_t
- Rm
- RmonStatMask
- Rn
- RomMemType
- Rom_size
- Root_CIFS
- Root_FD0
- Root_HDA1
- Root_HDA2
- Root_HDC1
- Root_NFS
- Root_RAM0
- Root_RAM1
- Root_SDA1
- Root_SDA2
- Root_SR0
- RopSrc
- RotR1
- Rot_0
- Rot_ALL_H_V
- RotateState
- RoundMode
- RoundToDFSGranularityDown
- RoundToDFSGranularityUp
- Rounding_mode
- Roundingmode
- RowSize
- RowTiling
- Rpending
- Rs01
- RsvdMask
- RtcPtr_t
- RtcRegs_t
- Rtl8188E_FWImgArrayLength
- Rtl8188E_FwImageArray
- Rtl8188E_NIC_DISABLE_FLOW
- Rtl8188E_NIC_ENABLE_FLOW
- Rtl8188E_NIC_LPS_ENTER_FLOW
- Rtl8188E_NIC_LPS_LEAVE_FLOW
- Rtl8188E_NIC_PDN_FLOW
- Rtl8188E_NIC_PWR_ON_FLOW
- Rtl8188E_NIC_RESUME_FLOW
- Rtl8188E_NIC_RF_OFF_FLOW
- Rtl8188E_NIC_SUSPEND_FLOW
- Rtl819XAGCTAB_Array
- Rtl819XMACPHY_Array
- Rtl819XMACPHY_Array_PG
- Rtl819XPHY_REGArray
- Rtl819XPHY_REG_1T2RArray
- Rtl819XRadioA_Array
- Rtl819XRadioB_Array
- Rtl819XRadioC_Array
- Rtl819XRadioD_Array
- RunInThread_param
- RunModeException
- RunnerRdCtrl
- RunnerWrCtrl
- Running
- Rworksched
- Rx2048QEntries
- Rx256QEntries
- Rx5
- Rx6
- Rx7
- Rx8
- RxAEP
- RxAJAB
- RxARP
- RxATX
- RxAcceptAllPhys
- RxAcceptBroadcast
- RxAcceptErr
- RxAcceptLong
- RxAcceptRunt
- RxAcceptTx
- RxAckBits
- RxAddrFilterEnable
- RxAddrMatch
- RxAlignCntExp
- RxAlignment
- RxAlignmentError
- RxAllMulti
- RxAllphys
- RxBaInactTimeout
- RxBadAlign
- RxBadBytes
- RxBadSymbol
- RxBranchSel
- RxBroadcast
- RxBroadcastFramesReceivedOK
- RxBuf
- RxBufAddr
- RxBufCount
- RxBufEmpty
- RxBufPtr
- RxBufQ2
- RxBufRPtr
- RxBufWPtr
- RxBufferLenShift
- RxBurstSizeShift
- RxCFGReserved
- RxCRC
- RxCRCCntExp
- RxCRCErr
- RxCRCErrs
- RxCRCNoStrip
- RxCRCOK
- RxCRC_ENAB
- RxCfg
- RxCfgDMAShift
- RxCfgDMAUnlimited
- RxCfgFIFONone
- RxCfgFIFOShift
- RxCfgRcv16K
- RxCfgRcv32K
- RxCfgRcv64K
- RxCfgRcv8K
- RxCheckStuck
- RxChecksum
- RxChecksumIgnore
- RxChecksumRejectTCPOnly
- RxChecksumRejectTCPUDP
- RxChkSum
- RxCmd
- RxCodeViolation
- RxComplProducerWrEn
- RxComplQAddr32bit
- RxComplQAddr64bit
- RxComplThreshShift
- RxComplType
- RxComplType0
- RxComplType1
- RxComplType2
- RxComplType3
- RxComplete
- RxCompletionAddr
- RxCompletionQ2Addr
- RxCompletionQ2Enable
- RxConfig
- RxConfigBits
- RxConfig_bits
- RxConsumerWrEn
- RxControl
- RxCrlFrame
- RxCtrl
- RxCurPtr
- RxD1
- RxD3
- RxDComplete
- RxDESC
- RxDError
- RxDIS
- RxDMABadFrames
- RxDMABurstThresh
- RxDMACRC
- RxDMAComplete
- RxDMAControlFrame
- RxDMACrcErrorFrames
- RxDMACtrl
- RxDMAError
- RxDMAIntCtrl
- RxDMALateErr
- RxDMAPauseFrame
- RxDMAPollPeriod
- RxDMAPriority
- RxDMAQ2Disable
- RxDMAQ2FPOnly
- RxDMAQ2HighPrio
- RxDMAQ2NonIP
- RxDMAQ2SmallPkt
- RxDMAShortFrames
- RxDMAStatus
- RxDMAUrgentThresh
- RxDRNT
- RxDRNT_10
- RxDRNT_100
- RxDRNT_shift
- RxD_block
- RxD_t
- RxDefaultAnt1
- RxDefaultAnt2
- RxDepth
- RxDesc
- RxDescAddr32bit
- RxDescAddr64bit
- RxDescAddrHigh
- RxDescAddrLow
- RxDescCRCError
- RxDescCollisionSeen
- RxDescCountMask
- RxDescDescErr
- RxDescEndRing
- RxDescErrorSummary
- RxDescFrameTooLong
- RxDescQAddr
- RxDescQAddr32bit
- RxDescQAddr64bit
- RxDescQCtrl
- RxDescQHiAddr
- RxDescQIdx
- RxDescRunt
- RxDescSpace128
- RxDescSpace16
- RxDescSpace32
- RxDescSpace4
- RxDescSpace64
- RxDescSpace8
- RxDescStartAddr
- RxDescValid
- RxDied
- RxDisable
- RxDiscard
- RxDone
- RxDrthMask
- RxEARLY
- RxENA
- RxENAB
- RxENABLE
- RxENDPKT_INT
- RxERR
- RxEarly
- RxEarlyIntThreshShift
- RxEarlyThresh
- RxEarlyWarn
- RxEmpty
- RxEnable
- RxEnabled
- RxEnb
- RxErr
- RxErrCRC
- RxErrFIFO
- RxErrFrame
- RxErrIntr
- RxErrLong
- RxErrRunt
- RxError
- RxErrorMask
- RxErrors
- RxFCSError
- RxFD
- RxFIFOEnable
- RxFIFOErr
- RxFIFOOver
- RxFIFOOverrun
- RxFIFOOvr
- RxFIFOToHost
- RxFIFOTrig1
- RxFIFOTrig14
- RxFIFOTrig4
- RxFIFOTrig8
- RxFIFO_LVL
- RxFid
- RxFilter
- RxFilterAddr
- RxFilterAddr_bits
- RxFilterData
- RxFilterEnable
- RxFilterMode
- RxFlowControlEnable
- RxFlowCtrl
- RxFlowEnable
- RxForceOK
- RxFrag_EnPack
- RxFrag_MinFragMask
- RxFragments
- RxFramErr
- RxFrameCheckSequenceErrors
- RxFrameCntExp
- RxFramesLostDueToInternalMACErrors
- RxFramesOK
- RxFramesTooLongErrors
- RxFull
- RxFullDx
- RxFullPkt
- RxGFPEnable
- RxGfpMem
- RxGrpPromisck
- RxHalt
- RxHashFilterEnable
- RxHashTable
- RxHeader
- RxHighPrioThreshShift
- RxHuge
- RxHugeFrame
- RxIDLE
- RxINT_ALL
- RxINT_DISAB
- RxINT_ERR
- RxINT_FCERR
- RxINT_MASK
- RxIdle
- RxInBytes
- RxInRangeLengthError
- RxInRangeLengthErrors
- RxIntr
- RxIntrCtrl
- RxIntrSel
- RxIpgShrink
- RxJabber
- RxJabbers
- RxJumboFrames
- RxJumboFramesReceivedOK
- RxJumboOctetsReceivedOK
- RxLenCntExp
- RxLengthError
- RxLengthOver2047
- RxListPtr
- RxLoopBack
- RxMACEnable
- RxMPSControl
- RxMXDMA_shift
- RxMacAddr
- RxMacControl
- RxMaxSize
- RxMcast
- RxMinDescrThreshShift
- RxMissed
- RxMissedMask
- RxMissedOver
- RxMode
- RxMultiCast
- RxMulticast
- RxMulticastFramesReceivedOK
- RxMxdmaMask
- RxMxdma_128
- RxMxdma_16
- RxMxdma_256
- RxMxdma_32
- RxMxdma_4
- RxMxdma_512
- RxMxdma_64
- RxMxdma_8
- RxNBITS_MASK
- RxN_MASK
- RxNoBuf
- RxNoDescriptors
- RxNoErrCheck
- RxNoWrap
- RxOK
- RxORN
- RxOctetsHigh
- RxOctetsLow
- RxOctetsReceivedOK
- RxOff
- RxOkBytes
- RxOn
- RxOutOfRangeError
- RxOverFlow
- RxOverSizedFrame
- RxOverflow
- RxOversize
- RxPAUSEMACCtrlFramesReceived
- RxPD_CONTROL_WDS_FRAME
- RxPD_MESH_FRAME
- RxPadStripEnab
- RxParityErr
- RxPathSelection_SS_TH_low
- RxPathSelection_diff_TH
- RxPause
- RxPhysical
- RxPktErrs
- RxPktPendingTimeout
- RxPktRej
- RxPolarity
- RxPoll
- RxPollInt
- RxPrefetchMode
- RxProm
- RxPromisc
- RxPromiscEnable
- RxProtoIP
- RxProtoMask
- RxProtoTCP
- RxProtoUDP
- RxPtr
- RxQEmpty
- RxQInt
- RxQed
- RxQueued
- RxRCMP
- RxRES
- RxRESET
- RxRUNT
- RxRWT
- RxRejectOwnPackets
- RxReorderIndicatePacket
- RxReportBadFrames
- RxReset
- RxResetDone
- RxResetValue
- RxRingAddr
- RxRingPtr
- RxRunt
- RxRuntFrame
- RxSOVR
- RxSTAT
- RxSeqValid
- RxSize1024To1518
- RxSize128To255
- RxSize1519ToMax
- RxSize256To511
- RxSize512To1023
- RxSize64
- RxSize65To127
- RxSizeMask
- RxSmall
- RxSmallFrame
- RxStartDemand
- RxStarted
- RxState
- RxStatesOK
- RxStation
- RxStatus
- RxStatus0
- RxStatusBits
- RxStatusFIFOOver
- RxStatusOK
- RxStopped
- RxStripCRC
- RxSts
- RxSymbolCarrier
- RxSymbolErrors
- RxTagError
- RxTooLong
- RxTrigger
- RxTsDeleteBA
- RxTx
- RxUnderrun
- RxUndersize
- RxUndersizedFrames
- RxUnicast
- RxUnicastFramesReceivedOK
- RxUnit
- RxUnsupOpcode
- RxUseBackupQueue
- RxVariableQ
- RxVlan
- RxVlanOn
- RxVlanTag
- RxVlanTagged
- RxWaitSel
- RxWholePkt
- RxWolCtrl
- RxWolData
- Rx_10Stat
- Rx_ARPReq
- Rx_Align
- Rx_BRK
- Rx_Broadcast
- Rx_CH_AV
- Rx_COE_EN_
- Rx_COE_MODE_
- Rx_CRCErr
- Rx_CtlRecd
- Rx_DeAuth
- Rx_DisAssoc
- Rx_EnAlign
- Rx_EnCRCErr
- Rx_EnGood
- Rx_EnLongErr
- Rx_EnOver
- Rx_EnRxPar
- Rx_FlowCtl
- Rx_GTK
- Rx_Good
- Rx_Halted
- Rx_IgnoreCRC
- Rx_InLenErr
- Rx_IntRx
- Rx_LongEn
- Rx_LongErr
- Rx_MagicPkt
- Rx_Multicast
- Rx_OVR
- Rx_Over
- Rx_Pairwisekey
- Rx_PatternPkt
- Rx_RxEn
- Rx_RxHalt
- Rx_RxPar
- Rx_SYS
- Rx_ShortEn
- Rx_Smooth_Factor
- Rx_Stat_Mask
- Rx_StripCRC
- Rx_TypePkt
- Rx_UnicastPkt
- Rx_over
- RxbufAddr
[..]